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drm/i915: Take ownership of atomic state on success in intel_set_mode()
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
47
48 /* Primary plane formats supported by all gen */
49 #define COMMON_PRIMARY_FORMATS \
50 DRM_FORMAT_C8, \
51 DRM_FORMAT_RGB565, \
52 DRM_FORMAT_XRGB8888, \
53 DRM_FORMAT_ARGB8888
54
55 /* Primary plane formats for gen <= 3 */
56 static const uint32_t intel_primary_formats_gen2[] = {
57 COMMON_PRIMARY_FORMATS,
58 DRM_FORMAT_XRGB1555,
59 DRM_FORMAT_ARGB1555,
60 };
61
62 /* Primary plane formats for gen >= 4 */
63 static const uint32_t intel_primary_formats_gen4[] = {
64 COMMON_PRIMARY_FORMATS, \
65 DRM_FORMAT_XBGR8888,
66 DRM_FORMAT_ABGR8888,
67 DRM_FORMAT_XRGB2101010,
68 DRM_FORMAT_ARGB2101010,
69 DRM_FORMAT_XBGR2101010,
70 DRM_FORMAT_ABGR2101010,
71 };
72
73 /* Cursor formats */
74 static const uint32_t intel_cursor_formats[] = {
75 DRM_FORMAT_ARGB8888,
76 };
77
78 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79
80 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
81 struct intel_crtc_state *pipe_config);
82 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
83 struct intel_crtc_state *pipe_config);
84
85 static int intel_set_mode(struct drm_crtc *crtc,
86 struct drm_atomic_state *state);
87 static int intel_framebuffer_init(struct drm_device *dev,
88 struct intel_framebuffer *ifb,
89 struct drm_mode_fb_cmd2 *mode_cmd,
90 struct drm_i915_gem_object *obj);
91 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
92 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
93 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
94 struct intel_link_m_n *m_n,
95 struct intel_link_m_n *m2_n2);
96 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
97 static void haswell_set_pipeconf(struct drm_crtc *crtc);
98 static void intel_set_pipe_csc(struct drm_crtc *crtc);
99 static void vlv_prepare_pll(struct intel_crtc *crtc,
100 const struct intel_crtc_state *pipe_config);
101 static void chv_prepare_pll(struct intel_crtc *crtc,
102 const struct intel_crtc_state *pipe_config);
103 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
104 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
105 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
106 struct intel_crtc_state *crtc_state);
107 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
108 int num_connectors);
109 static void intel_crtc_enable_planes(struct drm_crtc *crtc);
110 static void intel_crtc_disable_planes(struct drm_crtc *crtc);
111
112 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
113 {
114 if (!connector->mst_port)
115 return connector->encoder;
116 else
117 return &connector->mst_port->mst_encoders[pipe]->base;
118 }
119
120 typedef struct {
121 int min, max;
122 } intel_range_t;
123
124 typedef struct {
125 int dot_limit;
126 int p2_slow, p2_fast;
127 } intel_p2_t;
128
129 typedef struct intel_limit intel_limit_t;
130 struct intel_limit {
131 intel_range_t dot, vco, n, m, m1, m2, p, p1;
132 intel_p2_t p2;
133 };
134
135 int
136 intel_pch_rawclk(struct drm_device *dev)
137 {
138 struct drm_i915_private *dev_priv = dev->dev_private;
139
140 WARN_ON(!HAS_PCH_SPLIT(dev));
141
142 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
143 }
144
145 static inline u32 /* units of 100MHz */
146 intel_fdi_link_freq(struct drm_device *dev)
147 {
148 if (IS_GEN5(dev)) {
149 struct drm_i915_private *dev_priv = dev->dev_private;
150 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
151 } else
152 return 27;
153 }
154
155 static const intel_limit_t intel_limits_i8xx_dac = {
156 .dot = { .min = 25000, .max = 350000 },
157 .vco = { .min = 908000, .max = 1512000 },
158 .n = { .min = 2, .max = 16 },
159 .m = { .min = 96, .max = 140 },
160 .m1 = { .min = 18, .max = 26 },
161 .m2 = { .min = 6, .max = 16 },
162 .p = { .min = 4, .max = 128 },
163 .p1 = { .min = 2, .max = 33 },
164 .p2 = { .dot_limit = 165000,
165 .p2_slow = 4, .p2_fast = 2 },
166 };
167
168 static const intel_limit_t intel_limits_i8xx_dvo = {
169 .dot = { .min = 25000, .max = 350000 },
170 .vco = { .min = 908000, .max = 1512000 },
171 .n = { .min = 2, .max = 16 },
172 .m = { .min = 96, .max = 140 },
173 .m1 = { .min = 18, .max = 26 },
174 .m2 = { .min = 6, .max = 16 },
175 .p = { .min = 4, .max = 128 },
176 .p1 = { .min = 2, .max = 33 },
177 .p2 = { .dot_limit = 165000,
178 .p2_slow = 4, .p2_fast = 4 },
179 };
180
181 static const intel_limit_t intel_limits_i8xx_lvds = {
182 .dot = { .min = 25000, .max = 350000 },
183 .vco = { .min = 908000, .max = 1512000 },
184 .n = { .min = 2, .max = 16 },
185 .m = { .min = 96, .max = 140 },
186 .m1 = { .min = 18, .max = 26 },
187 .m2 = { .min = 6, .max = 16 },
188 .p = { .min = 4, .max = 128 },
189 .p1 = { .min = 1, .max = 6 },
190 .p2 = { .dot_limit = 165000,
191 .p2_slow = 14, .p2_fast = 7 },
192 };
193
194 static const intel_limit_t intel_limits_i9xx_sdvo = {
195 .dot = { .min = 20000, .max = 400000 },
196 .vco = { .min = 1400000, .max = 2800000 },
197 .n = { .min = 1, .max = 6 },
198 .m = { .min = 70, .max = 120 },
199 .m1 = { .min = 8, .max = 18 },
200 .m2 = { .min = 3, .max = 7 },
201 .p = { .min = 5, .max = 80 },
202 .p1 = { .min = 1, .max = 8 },
203 .p2 = { .dot_limit = 200000,
204 .p2_slow = 10, .p2_fast = 5 },
205 };
206
207 static const intel_limit_t intel_limits_i9xx_lvds = {
208 .dot = { .min = 20000, .max = 400000 },
209 .vco = { .min = 1400000, .max = 2800000 },
210 .n = { .min = 1, .max = 6 },
211 .m = { .min = 70, .max = 120 },
212 .m1 = { .min = 8, .max = 18 },
213 .m2 = { .min = 3, .max = 7 },
214 .p = { .min = 7, .max = 98 },
215 .p1 = { .min = 1, .max = 8 },
216 .p2 = { .dot_limit = 112000,
217 .p2_slow = 14, .p2_fast = 7 },
218 };
219
220
221 static const intel_limit_t intel_limits_g4x_sdvo = {
222 .dot = { .min = 25000, .max = 270000 },
223 .vco = { .min = 1750000, .max = 3500000},
224 .n = { .min = 1, .max = 4 },
225 .m = { .min = 104, .max = 138 },
226 .m1 = { .min = 17, .max = 23 },
227 .m2 = { .min = 5, .max = 11 },
228 .p = { .min = 10, .max = 30 },
229 .p1 = { .min = 1, .max = 3},
230 .p2 = { .dot_limit = 270000,
231 .p2_slow = 10,
232 .p2_fast = 10
233 },
234 };
235
236 static const intel_limit_t intel_limits_g4x_hdmi = {
237 .dot = { .min = 22000, .max = 400000 },
238 .vco = { .min = 1750000, .max = 3500000},
239 .n = { .min = 1, .max = 4 },
240 .m = { .min = 104, .max = 138 },
241 .m1 = { .min = 16, .max = 23 },
242 .m2 = { .min = 5, .max = 11 },
243 .p = { .min = 5, .max = 80 },
244 .p1 = { .min = 1, .max = 8},
245 .p2 = { .dot_limit = 165000,
246 .p2_slow = 10, .p2_fast = 5 },
247 };
248
249 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
250 .dot = { .min = 20000, .max = 115000 },
251 .vco = { .min = 1750000, .max = 3500000 },
252 .n = { .min = 1, .max = 3 },
253 .m = { .min = 104, .max = 138 },
254 .m1 = { .min = 17, .max = 23 },
255 .m2 = { .min = 5, .max = 11 },
256 .p = { .min = 28, .max = 112 },
257 .p1 = { .min = 2, .max = 8 },
258 .p2 = { .dot_limit = 0,
259 .p2_slow = 14, .p2_fast = 14
260 },
261 };
262
263 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
264 .dot = { .min = 80000, .max = 224000 },
265 .vco = { .min = 1750000, .max = 3500000 },
266 .n = { .min = 1, .max = 3 },
267 .m = { .min = 104, .max = 138 },
268 .m1 = { .min = 17, .max = 23 },
269 .m2 = { .min = 5, .max = 11 },
270 .p = { .min = 14, .max = 42 },
271 .p1 = { .min = 2, .max = 6 },
272 .p2 = { .dot_limit = 0,
273 .p2_slow = 7, .p2_fast = 7
274 },
275 };
276
277 static const intel_limit_t intel_limits_pineview_sdvo = {
278 .dot = { .min = 20000, .max = 400000},
279 .vco = { .min = 1700000, .max = 3500000 },
280 /* Pineview's Ncounter is a ring counter */
281 .n = { .min = 3, .max = 6 },
282 .m = { .min = 2, .max = 256 },
283 /* Pineview only has one combined m divider, which we treat as m2. */
284 .m1 = { .min = 0, .max = 0 },
285 .m2 = { .min = 0, .max = 254 },
286 .p = { .min = 5, .max = 80 },
287 .p1 = { .min = 1, .max = 8 },
288 .p2 = { .dot_limit = 200000,
289 .p2_slow = 10, .p2_fast = 5 },
290 };
291
292 static const intel_limit_t intel_limits_pineview_lvds = {
293 .dot = { .min = 20000, .max = 400000 },
294 .vco = { .min = 1700000, .max = 3500000 },
295 .n = { .min = 3, .max = 6 },
296 .m = { .min = 2, .max = 256 },
297 .m1 = { .min = 0, .max = 0 },
298 .m2 = { .min = 0, .max = 254 },
299 .p = { .min = 7, .max = 112 },
300 .p1 = { .min = 1, .max = 8 },
301 .p2 = { .dot_limit = 112000,
302 .p2_slow = 14, .p2_fast = 14 },
303 };
304
305 /* Ironlake / Sandybridge
306 *
307 * We calculate clock using (register_value + 2) for N/M1/M2, so here
308 * the range value for them is (actual_value - 2).
309 */
310 static const intel_limit_t intel_limits_ironlake_dac = {
311 .dot = { .min = 25000, .max = 350000 },
312 .vco = { .min = 1760000, .max = 3510000 },
313 .n = { .min = 1, .max = 5 },
314 .m = { .min = 79, .max = 127 },
315 .m1 = { .min = 12, .max = 22 },
316 .m2 = { .min = 5, .max = 9 },
317 .p = { .min = 5, .max = 80 },
318 .p1 = { .min = 1, .max = 8 },
319 .p2 = { .dot_limit = 225000,
320 .p2_slow = 10, .p2_fast = 5 },
321 };
322
323 static const intel_limit_t intel_limits_ironlake_single_lvds = {
324 .dot = { .min = 25000, .max = 350000 },
325 .vco = { .min = 1760000, .max = 3510000 },
326 .n = { .min = 1, .max = 3 },
327 .m = { .min = 79, .max = 118 },
328 .m1 = { .min = 12, .max = 22 },
329 .m2 = { .min = 5, .max = 9 },
330 .p = { .min = 28, .max = 112 },
331 .p1 = { .min = 2, .max = 8 },
332 .p2 = { .dot_limit = 225000,
333 .p2_slow = 14, .p2_fast = 14 },
334 };
335
336 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
337 .dot = { .min = 25000, .max = 350000 },
338 .vco = { .min = 1760000, .max = 3510000 },
339 .n = { .min = 1, .max = 3 },
340 .m = { .min = 79, .max = 127 },
341 .m1 = { .min = 12, .max = 22 },
342 .m2 = { .min = 5, .max = 9 },
343 .p = { .min = 14, .max = 56 },
344 .p1 = { .min = 2, .max = 8 },
345 .p2 = { .dot_limit = 225000,
346 .p2_slow = 7, .p2_fast = 7 },
347 };
348
349 /* LVDS 100mhz refclk limits. */
350 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
351 .dot = { .min = 25000, .max = 350000 },
352 .vco = { .min = 1760000, .max = 3510000 },
353 .n = { .min = 1, .max = 2 },
354 .m = { .min = 79, .max = 126 },
355 .m1 = { .min = 12, .max = 22 },
356 .m2 = { .min = 5, .max = 9 },
357 .p = { .min = 28, .max = 112 },
358 .p1 = { .min = 2, .max = 8 },
359 .p2 = { .dot_limit = 225000,
360 .p2_slow = 14, .p2_fast = 14 },
361 };
362
363 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
364 .dot = { .min = 25000, .max = 350000 },
365 .vco = { .min = 1760000, .max = 3510000 },
366 .n = { .min = 1, .max = 3 },
367 .m = { .min = 79, .max = 126 },
368 .m1 = { .min = 12, .max = 22 },
369 .m2 = { .min = 5, .max = 9 },
370 .p = { .min = 14, .max = 42 },
371 .p1 = { .min = 2, .max = 6 },
372 .p2 = { .dot_limit = 225000,
373 .p2_slow = 7, .p2_fast = 7 },
374 };
375
376 static const intel_limit_t intel_limits_vlv = {
377 /*
378 * These are the data rate limits (measured in fast clocks)
379 * since those are the strictest limits we have. The fast
380 * clock and actual rate limits are more relaxed, so checking
381 * them would make no difference.
382 */
383 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
384 .vco = { .min = 4000000, .max = 6000000 },
385 .n = { .min = 1, .max = 7 },
386 .m1 = { .min = 2, .max = 3 },
387 .m2 = { .min = 11, .max = 156 },
388 .p1 = { .min = 2, .max = 3 },
389 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
390 };
391
392 static const intel_limit_t intel_limits_chv = {
393 /*
394 * These are the data rate limits (measured in fast clocks)
395 * since those are the strictest limits we have. The fast
396 * clock and actual rate limits are more relaxed, so checking
397 * them would make no difference.
398 */
399 .dot = { .min = 25000 * 5, .max = 540000 * 5},
400 .vco = { .min = 4800000, .max = 6480000 },
401 .n = { .min = 1, .max = 1 },
402 .m1 = { .min = 2, .max = 2 },
403 .m2 = { .min = 24 << 22, .max = 175 << 22 },
404 .p1 = { .min = 2, .max = 4 },
405 .p2 = { .p2_slow = 1, .p2_fast = 14 },
406 };
407
408 static const intel_limit_t intel_limits_bxt = {
409 /* FIXME: find real dot limits */
410 .dot = { .min = 0, .max = INT_MAX },
411 .vco = { .min = 4800000, .max = 6480000 },
412 .n = { .min = 1, .max = 1 },
413 .m1 = { .min = 2, .max = 2 },
414 /* FIXME: find real m2 limits */
415 .m2 = { .min = 2 << 22, .max = 255 << 22 },
416 .p1 = { .min = 2, .max = 4 },
417 .p2 = { .p2_slow = 1, .p2_fast = 20 },
418 };
419
420 static void vlv_clock(int refclk, intel_clock_t *clock)
421 {
422 clock->m = clock->m1 * clock->m2;
423 clock->p = clock->p1 * clock->p2;
424 if (WARN_ON(clock->n == 0 || clock->p == 0))
425 return;
426 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
427 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
428 }
429
430 /**
431 * Returns whether any output on the specified pipe is of the specified type
432 */
433 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
434 {
435 struct drm_device *dev = crtc->base.dev;
436 struct intel_encoder *encoder;
437
438 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
439 if (encoder->type == type)
440 return true;
441
442 return false;
443 }
444
445 /**
446 * Returns whether any output on the specified pipe will have the specified
447 * type after a staged modeset is complete, i.e., the same as
448 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
449 * encoder->crtc.
450 */
451 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
452 int type)
453 {
454 struct drm_atomic_state *state = crtc_state->base.state;
455 struct drm_connector *connector;
456 struct drm_connector_state *connector_state;
457 struct intel_encoder *encoder;
458 int i, num_connectors = 0;
459
460 for_each_connector_in_state(state, connector, connector_state, i) {
461 if (connector_state->crtc != crtc_state->base.crtc)
462 continue;
463
464 num_connectors++;
465
466 encoder = to_intel_encoder(connector_state->best_encoder);
467 if (encoder->type == type)
468 return true;
469 }
470
471 WARN_ON(num_connectors == 0);
472
473 return false;
474 }
475
476 static const intel_limit_t *
477 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
478 {
479 struct drm_device *dev = crtc_state->base.crtc->dev;
480 const intel_limit_t *limit;
481
482 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
483 if (intel_is_dual_link_lvds(dev)) {
484 if (refclk == 100000)
485 limit = &intel_limits_ironlake_dual_lvds_100m;
486 else
487 limit = &intel_limits_ironlake_dual_lvds;
488 } else {
489 if (refclk == 100000)
490 limit = &intel_limits_ironlake_single_lvds_100m;
491 else
492 limit = &intel_limits_ironlake_single_lvds;
493 }
494 } else
495 limit = &intel_limits_ironlake_dac;
496
497 return limit;
498 }
499
500 static const intel_limit_t *
501 intel_g4x_limit(struct intel_crtc_state *crtc_state)
502 {
503 struct drm_device *dev = crtc_state->base.crtc->dev;
504 const intel_limit_t *limit;
505
506 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
507 if (intel_is_dual_link_lvds(dev))
508 limit = &intel_limits_g4x_dual_channel_lvds;
509 else
510 limit = &intel_limits_g4x_single_channel_lvds;
511 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
512 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
513 limit = &intel_limits_g4x_hdmi;
514 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
515 limit = &intel_limits_g4x_sdvo;
516 } else /* The option is for other outputs */
517 limit = &intel_limits_i9xx_sdvo;
518
519 return limit;
520 }
521
522 static const intel_limit_t *
523 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
524 {
525 struct drm_device *dev = crtc_state->base.crtc->dev;
526 const intel_limit_t *limit;
527
528 if (IS_BROXTON(dev))
529 limit = &intel_limits_bxt;
530 else if (HAS_PCH_SPLIT(dev))
531 limit = intel_ironlake_limit(crtc_state, refclk);
532 else if (IS_G4X(dev)) {
533 limit = intel_g4x_limit(crtc_state);
534 } else if (IS_PINEVIEW(dev)) {
535 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
536 limit = &intel_limits_pineview_lvds;
537 else
538 limit = &intel_limits_pineview_sdvo;
539 } else if (IS_CHERRYVIEW(dev)) {
540 limit = &intel_limits_chv;
541 } else if (IS_VALLEYVIEW(dev)) {
542 limit = &intel_limits_vlv;
543 } else if (!IS_GEN2(dev)) {
544 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
545 limit = &intel_limits_i9xx_lvds;
546 else
547 limit = &intel_limits_i9xx_sdvo;
548 } else {
549 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
550 limit = &intel_limits_i8xx_lvds;
551 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
552 limit = &intel_limits_i8xx_dvo;
553 else
554 limit = &intel_limits_i8xx_dac;
555 }
556 return limit;
557 }
558
559 /* m1 is reserved as 0 in Pineview, n is a ring counter */
560 static void pineview_clock(int refclk, intel_clock_t *clock)
561 {
562 clock->m = clock->m2 + 2;
563 clock->p = clock->p1 * clock->p2;
564 if (WARN_ON(clock->n == 0 || clock->p == 0))
565 return;
566 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
567 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
568 }
569
570 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
571 {
572 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
573 }
574
575 static void i9xx_clock(int refclk, intel_clock_t *clock)
576 {
577 clock->m = i9xx_dpll_compute_m(clock);
578 clock->p = clock->p1 * clock->p2;
579 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
580 return;
581 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
582 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
583 }
584
585 static void chv_clock(int refclk, intel_clock_t *clock)
586 {
587 clock->m = clock->m1 * clock->m2;
588 clock->p = clock->p1 * clock->p2;
589 if (WARN_ON(clock->n == 0 || clock->p == 0))
590 return;
591 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
592 clock->n << 22);
593 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
594 }
595
596 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
597 /**
598 * Returns whether the given set of divisors are valid for a given refclk with
599 * the given connectors.
600 */
601
602 static bool intel_PLL_is_valid(struct drm_device *dev,
603 const intel_limit_t *limit,
604 const intel_clock_t *clock)
605 {
606 if (clock->n < limit->n.min || limit->n.max < clock->n)
607 INTELPllInvalid("n out of range\n");
608 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
609 INTELPllInvalid("p1 out of range\n");
610 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
611 INTELPllInvalid("m2 out of range\n");
612 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
613 INTELPllInvalid("m1 out of range\n");
614
615 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
616 if (clock->m1 <= clock->m2)
617 INTELPllInvalid("m1 <= m2\n");
618
619 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
620 if (clock->p < limit->p.min || limit->p.max < clock->p)
621 INTELPllInvalid("p out of range\n");
622 if (clock->m < limit->m.min || limit->m.max < clock->m)
623 INTELPllInvalid("m out of range\n");
624 }
625
626 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
627 INTELPllInvalid("vco out of range\n");
628 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
629 * connector, etc., rather than just a single range.
630 */
631 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
632 INTELPllInvalid("dot out of range\n");
633
634 return true;
635 }
636
637 static bool
638 i9xx_find_best_dpll(const intel_limit_t *limit,
639 struct intel_crtc_state *crtc_state,
640 int target, int refclk, intel_clock_t *match_clock,
641 intel_clock_t *best_clock)
642 {
643 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
644 struct drm_device *dev = crtc->base.dev;
645 intel_clock_t clock;
646 int err = target;
647
648 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
649 /*
650 * For LVDS just rely on its current settings for dual-channel.
651 * We haven't figured out how to reliably set up different
652 * single/dual channel state, if we even can.
653 */
654 if (intel_is_dual_link_lvds(dev))
655 clock.p2 = limit->p2.p2_fast;
656 else
657 clock.p2 = limit->p2.p2_slow;
658 } else {
659 if (target < limit->p2.dot_limit)
660 clock.p2 = limit->p2.p2_slow;
661 else
662 clock.p2 = limit->p2.p2_fast;
663 }
664
665 memset(best_clock, 0, sizeof(*best_clock));
666
667 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
668 clock.m1++) {
669 for (clock.m2 = limit->m2.min;
670 clock.m2 <= limit->m2.max; clock.m2++) {
671 if (clock.m2 >= clock.m1)
672 break;
673 for (clock.n = limit->n.min;
674 clock.n <= limit->n.max; clock.n++) {
675 for (clock.p1 = limit->p1.min;
676 clock.p1 <= limit->p1.max; clock.p1++) {
677 int this_err;
678
679 i9xx_clock(refclk, &clock);
680 if (!intel_PLL_is_valid(dev, limit,
681 &clock))
682 continue;
683 if (match_clock &&
684 clock.p != match_clock->p)
685 continue;
686
687 this_err = abs(clock.dot - target);
688 if (this_err < err) {
689 *best_clock = clock;
690 err = this_err;
691 }
692 }
693 }
694 }
695 }
696
697 return (err != target);
698 }
699
700 static bool
701 pnv_find_best_dpll(const intel_limit_t *limit,
702 struct intel_crtc_state *crtc_state,
703 int target, int refclk, intel_clock_t *match_clock,
704 intel_clock_t *best_clock)
705 {
706 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
707 struct drm_device *dev = crtc->base.dev;
708 intel_clock_t clock;
709 int err = target;
710
711 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
712 /*
713 * For LVDS just rely on its current settings for dual-channel.
714 * We haven't figured out how to reliably set up different
715 * single/dual channel state, if we even can.
716 */
717 if (intel_is_dual_link_lvds(dev))
718 clock.p2 = limit->p2.p2_fast;
719 else
720 clock.p2 = limit->p2.p2_slow;
721 } else {
722 if (target < limit->p2.dot_limit)
723 clock.p2 = limit->p2.p2_slow;
724 else
725 clock.p2 = limit->p2.p2_fast;
726 }
727
728 memset(best_clock, 0, sizeof(*best_clock));
729
730 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
731 clock.m1++) {
732 for (clock.m2 = limit->m2.min;
733 clock.m2 <= limit->m2.max; clock.m2++) {
734 for (clock.n = limit->n.min;
735 clock.n <= limit->n.max; clock.n++) {
736 for (clock.p1 = limit->p1.min;
737 clock.p1 <= limit->p1.max; clock.p1++) {
738 int this_err;
739
740 pineview_clock(refclk, &clock);
741 if (!intel_PLL_is_valid(dev, limit,
742 &clock))
743 continue;
744 if (match_clock &&
745 clock.p != match_clock->p)
746 continue;
747
748 this_err = abs(clock.dot - target);
749 if (this_err < err) {
750 *best_clock = clock;
751 err = this_err;
752 }
753 }
754 }
755 }
756 }
757
758 return (err != target);
759 }
760
761 static bool
762 g4x_find_best_dpll(const intel_limit_t *limit,
763 struct intel_crtc_state *crtc_state,
764 int target, int refclk, intel_clock_t *match_clock,
765 intel_clock_t *best_clock)
766 {
767 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
768 struct drm_device *dev = crtc->base.dev;
769 intel_clock_t clock;
770 int max_n;
771 bool found;
772 /* approximately equals target * 0.00585 */
773 int err_most = (target >> 8) + (target >> 9);
774 found = false;
775
776 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
777 if (intel_is_dual_link_lvds(dev))
778 clock.p2 = limit->p2.p2_fast;
779 else
780 clock.p2 = limit->p2.p2_slow;
781 } else {
782 if (target < limit->p2.dot_limit)
783 clock.p2 = limit->p2.p2_slow;
784 else
785 clock.p2 = limit->p2.p2_fast;
786 }
787
788 memset(best_clock, 0, sizeof(*best_clock));
789 max_n = limit->n.max;
790 /* based on hardware requirement, prefer smaller n to precision */
791 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
792 /* based on hardware requirement, prefere larger m1,m2 */
793 for (clock.m1 = limit->m1.max;
794 clock.m1 >= limit->m1.min; clock.m1--) {
795 for (clock.m2 = limit->m2.max;
796 clock.m2 >= limit->m2.min; clock.m2--) {
797 for (clock.p1 = limit->p1.max;
798 clock.p1 >= limit->p1.min; clock.p1--) {
799 int this_err;
800
801 i9xx_clock(refclk, &clock);
802 if (!intel_PLL_is_valid(dev, limit,
803 &clock))
804 continue;
805
806 this_err = abs(clock.dot - target);
807 if (this_err < err_most) {
808 *best_clock = clock;
809 err_most = this_err;
810 max_n = clock.n;
811 found = true;
812 }
813 }
814 }
815 }
816 }
817 return found;
818 }
819
820 /*
821 * Check if the calculated PLL configuration is more optimal compared to the
822 * best configuration and error found so far. Return the calculated error.
823 */
824 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
825 const intel_clock_t *calculated_clock,
826 const intel_clock_t *best_clock,
827 unsigned int best_error_ppm,
828 unsigned int *error_ppm)
829 {
830 /*
831 * For CHV ignore the error and consider only the P value.
832 * Prefer a bigger P value based on HW requirements.
833 */
834 if (IS_CHERRYVIEW(dev)) {
835 *error_ppm = 0;
836
837 return calculated_clock->p > best_clock->p;
838 }
839
840 if (WARN_ON_ONCE(!target_freq))
841 return false;
842
843 *error_ppm = div_u64(1000000ULL *
844 abs(target_freq - calculated_clock->dot),
845 target_freq);
846 /*
847 * Prefer a better P value over a better (smaller) error if the error
848 * is small. Ensure this preference for future configurations too by
849 * setting the error to 0.
850 */
851 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
852 *error_ppm = 0;
853
854 return true;
855 }
856
857 return *error_ppm + 10 < best_error_ppm;
858 }
859
860 static bool
861 vlv_find_best_dpll(const intel_limit_t *limit,
862 struct intel_crtc_state *crtc_state,
863 int target, int refclk, intel_clock_t *match_clock,
864 intel_clock_t *best_clock)
865 {
866 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
867 struct drm_device *dev = crtc->base.dev;
868 intel_clock_t clock;
869 unsigned int bestppm = 1000000;
870 /* min update 19.2 MHz */
871 int max_n = min(limit->n.max, refclk / 19200);
872 bool found = false;
873
874 target *= 5; /* fast clock */
875
876 memset(best_clock, 0, sizeof(*best_clock));
877
878 /* based on hardware requirement, prefer smaller n to precision */
879 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
880 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
881 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
882 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
883 clock.p = clock.p1 * clock.p2;
884 /* based on hardware requirement, prefer bigger m1,m2 values */
885 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
886 unsigned int ppm;
887
888 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
889 refclk * clock.m1);
890
891 vlv_clock(refclk, &clock);
892
893 if (!intel_PLL_is_valid(dev, limit,
894 &clock))
895 continue;
896
897 if (!vlv_PLL_is_optimal(dev, target,
898 &clock,
899 best_clock,
900 bestppm, &ppm))
901 continue;
902
903 *best_clock = clock;
904 bestppm = ppm;
905 found = true;
906 }
907 }
908 }
909 }
910
911 return found;
912 }
913
914 static bool
915 chv_find_best_dpll(const intel_limit_t *limit,
916 struct intel_crtc_state *crtc_state,
917 int target, int refclk, intel_clock_t *match_clock,
918 intel_clock_t *best_clock)
919 {
920 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
921 struct drm_device *dev = crtc->base.dev;
922 unsigned int best_error_ppm;
923 intel_clock_t clock;
924 uint64_t m2;
925 int found = false;
926
927 memset(best_clock, 0, sizeof(*best_clock));
928 best_error_ppm = 1000000;
929
930 /*
931 * Based on hardware doc, the n always set to 1, and m1 always
932 * set to 2. If requires to support 200Mhz refclk, we need to
933 * revisit this because n may not 1 anymore.
934 */
935 clock.n = 1, clock.m1 = 2;
936 target *= 5; /* fast clock */
937
938 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
939 for (clock.p2 = limit->p2.p2_fast;
940 clock.p2 >= limit->p2.p2_slow;
941 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
942 unsigned int error_ppm;
943
944 clock.p = clock.p1 * clock.p2;
945
946 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
947 clock.n) << 22, refclk * clock.m1);
948
949 if (m2 > INT_MAX/clock.m1)
950 continue;
951
952 clock.m2 = m2;
953
954 chv_clock(refclk, &clock);
955
956 if (!intel_PLL_is_valid(dev, limit, &clock))
957 continue;
958
959 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
960 best_error_ppm, &error_ppm))
961 continue;
962
963 *best_clock = clock;
964 best_error_ppm = error_ppm;
965 found = true;
966 }
967 }
968
969 return found;
970 }
971
972 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
973 intel_clock_t *best_clock)
974 {
975 int refclk = i9xx_get_refclk(crtc_state, 0);
976
977 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
978 target_clock, refclk, NULL, best_clock);
979 }
980
981 bool intel_crtc_active(struct drm_crtc *crtc)
982 {
983 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
984
985 /* Be paranoid as we can arrive here with only partial
986 * state retrieved from the hardware during setup.
987 *
988 * We can ditch the adjusted_mode.crtc_clock check as soon
989 * as Haswell has gained clock readout/fastboot support.
990 *
991 * We can ditch the crtc->primary->fb check as soon as we can
992 * properly reconstruct framebuffers.
993 *
994 * FIXME: The intel_crtc->active here should be switched to
995 * crtc->state->active once we have proper CRTC states wired up
996 * for atomic.
997 */
998 return intel_crtc->active && crtc->primary->state->fb &&
999 intel_crtc->config->base.adjusted_mode.crtc_clock;
1000 }
1001
1002 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1003 enum pipe pipe)
1004 {
1005 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1006 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1007
1008 return intel_crtc->config->cpu_transcoder;
1009 }
1010
1011 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1012 {
1013 struct drm_i915_private *dev_priv = dev->dev_private;
1014 u32 reg = PIPEDSL(pipe);
1015 u32 line1, line2;
1016 u32 line_mask;
1017
1018 if (IS_GEN2(dev))
1019 line_mask = DSL_LINEMASK_GEN2;
1020 else
1021 line_mask = DSL_LINEMASK_GEN3;
1022
1023 line1 = I915_READ(reg) & line_mask;
1024 mdelay(5);
1025 line2 = I915_READ(reg) & line_mask;
1026
1027 return line1 == line2;
1028 }
1029
1030 /*
1031 * intel_wait_for_pipe_off - wait for pipe to turn off
1032 * @crtc: crtc whose pipe to wait for
1033 *
1034 * After disabling a pipe, we can't wait for vblank in the usual way,
1035 * spinning on the vblank interrupt status bit, since we won't actually
1036 * see an interrupt when the pipe is disabled.
1037 *
1038 * On Gen4 and above:
1039 * wait for the pipe register state bit to turn off
1040 *
1041 * Otherwise:
1042 * wait for the display line value to settle (it usually
1043 * ends up stopping at the start of the next frame).
1044 *
1045 */
1046 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1047 {
1048 struct drm_device *dev = crtc->base.dev;
1049 struct drm_i915_private *dev_priv = dev->dev_private;
1050 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1051 enum pipe pipe = crtc->pipe;
1052
1053 if (INTEL_INFO(dev)->gen >= 4) {
1054 int reg = PIPECONF(cpu_transcoder);
1055
1056 /* Wait for the Pipe State to go off */
1057 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1058 100))
1059 WARN(1, "pipe_off wait timed out\n");
1060 } else {
1061 /* Wait for the display line to settle */
1062 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1063 WARN(1, "pipe_off wait timed out\n");
1064 }
1065 }
1066
1067 /*
1068 * ibx_digital_port_connected - is the specified port connected?
1069 * @dev_priv: i915 private structure
1070 * @port: the port to test
1071 *
1072 * Returns true if @port is connected, false otherwise.
1073 */
1074 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1075 struct intel_digital_port *port)
1076 {
1077 u32 bit;
1078
1079 if (HAS_PCH_IBX(dev_priv->dev)) {
1080 switch (port->port) {
1081 case PORT_B:
1082 bit = SDE_PORTB_HOTPLUG;
1083 break;
1084 case PORT_C:
1085 bit = SDE_PORTC_HOTPLUG;
1086 break;
1087 case PORT_D:
1088 bit = SDE_PORTD_HOTPLUG;
1089 break;
1090 default:
1091 return true;
1092 }
1093 } else {
1094 switch (port->port) {
1095 case PORT_B:
1096 bit = SDE_PORTB_HOTPLUG_CPT;
1097 break;
1098 case PORT_C:
1099 bit = SDE_PORTC_HOTPLUG_CPT;
1100 break;
1101 case PORT_D:
1102 bit = SDE_PORTD_HOTPLUG_CPT;
1103 break;
1104 default:
1105 return true;
1106 }
1107 }
1108
1109 return I915_READ(SDEISR) & bit;
1110 }
1111
1112 static const char *state_string(bool enabled)
1113 {
1114 return enabled ? "on" : "off";
1115 }
1116
1117 /* Only for pre-ILK configs */
1118 void assert_pll(struct drm_i915_private *dev_priv,
1119 enum pipe pipe, bool state)
1120 {
1121 int reg;
1122 u32 val;
1123 bool cur_state;
1124
1125 reg = DPLL(pipe);
1126 val = I915_READ(reg);
1127 cur_state = !!(val & DPLL_VCO_ENABLE);
1128 I915_STATE_WARN(cur_state != state,
1129 "PLL state assertion failure (expected %s, current %s)\n",
1130 state_string(state), state_string(cur_state));
1131 }
1132
1133 /* XXX: the dsi pll is shared between MIPI DSI ports */
1134 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1135 {
1136 u32 val;
1137 bool cur_state;
1138
1139 mutex_lock(&dev_priv->dpio_lock);
1140 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1141 mutex_unlock(&dev_priv->dpio_lock);
1142
1143 cur_state = val & DSI_PLL_VCO_EN;
1144 I915_STATE_WARN(cur_state != state,
1145 "DSI PLL state assertion failure (expected %s, current %s)\n",
1146 state_string(state), state_string(cur_state));
1147 }
1148 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1149 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1150
1151 struct intel_shared_dpll *
1152 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1153 {
1154 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1155
1156 if (crtc->config->shared_dpll < 0)
1157 return NULL;
1158
1159 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1160 }
1161
1162 /* For ILK+ */
1163 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1164 struct intel_shared_dpll *pll,
1165 bool state)
1166 {
1167 bool cur_state;
1168 struct intel_dpll_hw_state hw_state;
1169
1170 if (WARN (!pll,
1171 "asserting DPLL %s with no DPLL\n", state_string(state)))
1172 return;
1173
1174 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1175 I915_STATE_WARN(cur_state != state,
1176 "%s assertion failure (expected %s, current %s)\n",
1177 pll->name, state_string(state), state_string(cur_state));
1178 }
1179
1180 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1181 enum pipe pipe, bool state)
1182 {
1183 int reg;
1184 u32 val;
1185 bool cur_state;
1186 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1187 pipe);
1188
1189 if (HAS_DDI(dev_priv->dev)) {
1190 /* DDI does not have a specific FDI_TX register */
1191 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1192 val = I915_READ(reg);
1193 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1194 } else {
1195 reg = FDI_TX_CTL(pipe);
1196 val = I915_READ(reg);
1197 cur_state = !!(val & FDI_TX_ENABLE);
1198 }
1199 I915_STATE_WARN(cur_state != state,
1200 "FDI TX state assertion failure (expected %s, current %s)\n",
1201 state_string(state), state_string(cur_state));
1202 }
1203 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1204 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1205
1206 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1207 enum pipe pipe, bool state)
1208 {
1209 int reg;
1210 u32 val;
1211 bool cur_state;
1212
1213 reg = FDI_RX_CTL(pipe);
1214 val = I915_READ(reg);
1215 cur_state = !!(val & FDI_RX_ENABLE);
1216 I915_STATE_WARN(cur_state != state,
1217 "FDI RX state assertion failure (expected %s, current %s)\n",
1218 state_string(state), state_string(cur_state));
1219 }
1220 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1221 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1222
1223 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1224 enum pipe pipe)
1225 {
1226 int reg;
1227 u32 val;
1228
1229 /* ILK FDI PLL is always enabled */
1230 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1231 return;
1232
1233 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1234 if (HAS_DDI(dev_priv->dev))
1235 return;
1236
1237 reg = FDI_TX_CTL(pipe);
1238 val = I915_READ(reg);
1239 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1240 }
1241
1242 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1243 enum pipe pipe, bool state)
1244 {
1245 int reg;
1246 u32 val;
1247 bool cur_state;
1248
1249 reg = FDI_RX_CTL(pipe);
1250 val = I915_READ(reg);
1251 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1252 I915_STATE_WARN(cur_state != state,
1253 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1254 state_string(state), state_string(cur_state));
1255 }
1256
1257 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1258 enum pipe pipe)
1259 {
1260 struct drm_device *dev = dev_priv->dev;
1261 int pp_reg;
1262 u32 val;
1263 enum pipe panel_pipe = PIPE_A;
1264 bool locked = true;
1265
1266 if (WARN_ON(HAS_DDI(dev)))
1267 return;
1268
1269 if (HAS_PCH_SPLIT(dev)) {
1270 u32 port_sel;
1271
1272 pp_reg = PCH_PP_CONTROL;
1273 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1274
1275 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1276 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1277 panel_pipe = PIPE_B;
1278 /* XXX: else fix for eDP */
1279 } else if (IS_VALLEYVIEW(dev)) {
1280 /* presumably write lock depends on pipe, not port select */
1281 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1282 panel_pipe = pipe;
1283 } else {
1284 pp_reg = PP_CONTROL;
1285 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1286 panel_pipe = PIPE_B;
1287 }
1288
1289 val = I915_READ(pp_reg);
1290 if (!(val & PANEL_POWER_ON) ||
1291 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1292 locked = false;
1293
1294 I915_STATE_WARN(panel_pipe == pipe && locked,
1295 "panel assertion failure, pipe %c regs locked\n",
1296 pipe_name(pipe));
1297 }
1298
1299 static void assert_cursor(struct drm_i915_private *dev_priv,
1300 enum pipe pipe, bool state)
1301 {
1302 struct drm_device *dev = dev_priv->dev;
1303 bool cur_state;
1304
1305 if (IS_845G(dev) || IS_I865G(dev))
1306 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1307 else
1308 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1309
1310 I915_STATE_WARN(cur_state != state,
1311 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1312 pipe_name(pipe), state_string(state), state_string(cur_state));
1313 }
1314 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1315 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1316
1317 void assert_pipe(struct drm_i915_private *dev_priv,
1318 enum pipe pipe, bool state)
1319 {
1320 int reg;
1321 u32 val;
1322 bool cur_state;
1323 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1324 pipe);
1325
1326 /* if we need the pipe quirk it must be always on */
1327 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1328 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1329 state = true;
1330
1331 if (!intel_display_power_is_enabled(dev_priv,
1332 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1333 cur_state = false;
1334 } else {
1335 reg = PIPECONF(cpu_transcoder);
1336 val = I915_READ(reg);
1337 cur_state = !!(val & PIPECONF_ENABLE);
1338 }
1339
1340 I915_STATE_WARN(cur_state != state,
1341 "pipe %c assertion failure (expected %s, current %s)\n",
1342 pipe_name(pipe), state_string(state), state_string(cur_state));
1343 }
1344
1345 static void assert_plane(struct drm_i915_private *dev_priv,
1346 enum plane plane, bool state)
1347 {
1348 int reg;
1349 u32 val;
1350 bool cur_state;
1351
1352 reg = DSPCNTR(plane);
1353 val = I915_READ(reg);
1354 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1355 I915_STATE_WARN(cur_state != state,
1356 "plane %c assertion failure (expected %s, current %s)\n",
1357 plane_name(plane), state_string(state), state_string(cur_state));
1358 }
1359
1360 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1361 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1362
1363 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1364 enum pipe pipe)
1365 {
1366 struct drm_device *dev = dev_priv->dev;
1367 int reg, i;
1368 u32 val;
1369 int cur_pipe;
1370
1371 /* Primary planes are fixed to pipes on gen4+ */
1372 if (INTEL_INFO(dev)->gen >= 4) {
1373 reg = DSPCNTR(pipe);
1374 val = I915_READ(reg);
1375 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1376 "plane %c assertion failure, should be disabled but not\n",
1377 plane_name(pipe));
1378 return;
1379 }
1380
1381 /* Need to check both planes against the pipe */
1382 for_each_pipe(dev_priv, i) {
1383 reg = DSPCNTR(i);
1384 val = I915_READ(reg);
1385 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1386 DISPPLANE_SEL_PIPE_SHIFT;
1387 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1388 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1389 plane_name(i), pipe_name(pipe));
1390 }
1391 }
1392
1393 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1394 enum pipe pipe)
1395 {
1396 struct drm_device *dev = dev_priv->dev;
1397 int reg, sprite;
1398 u32 val;
1399
1400 if (INTEL_INFO(dev)->gen >= 9) {
1401 for_each_sprite(dev_priv, pipe, sprite) {
1402 val = I915_READ(PLANE_CTL(pipe, sprite));
1403 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1404 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1405 sprite, pipe_name(pipe));
1406 }
1407 } else if (IS_VALLEYVIEW(dev)) {
1408 for_each_sprite(dev_priv, pipe, sprite) {
1409 reg = SPCNTR(pipe, sprite);
1410 val = I915_READ(reg);
1411 I915_STATE_WARN(val & SP_ENABLE,
1412 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1413 sprite_name(pipe, sprite), pipe_name(pipe));
1414 }
1415 } else if (INTEL_INFO(dev)->gen >= 7) {
1416 reg = SPRCTL(pipe);
1417 val = I915_READ(reg);
1418 I915_STATE_WARN(val & SPRITE_ENABLE,
1419 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1420 plane_name(pipe), pipe_name(pipe));
1421 } else if (INTEL_INFO(dev)->gen >= 5) {
1422 reg = DVSCNTR(pipe);
1423 val = I915_READ(reg);
1424 I915_STATE_WARN(val & DVS_ENABLE,
1425 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1426 plane_name(pipe), pipe_name(pipe));
1427 }
1428 }
1429
1430 static void assert_vblank_disabled(struct drm_crtc *crtc)
1431 {
1432 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1433 drm_crtc_vblank_put(crtc);
1434 }
1435
1436 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1437 {
1438 u32 val;
1439 bool enabled;
1440
1441 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1442
1443 val = I915_READ(PCH_DREF_CONTROL);
1444 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1445 DREF_SUPERSPREAD_SOURCE_MASK));
1446 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1447 }
1448
1449 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1450 enum pipe pipe)
1451 {
1452 int reg;
1453 u32 val;
1454 bool enabled;
1455
1456 reg = PCH_TRANSCONF(pipe);
1457 val = I915_READ(reg);
1458 enabled = !!(val & TRANS_ENABLE);
1459 I915_STATE_WARN(enabled,
1460 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1461 pipe_name(pipe));
1462 }
1463
1464 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1465 enum pipe pipe, u32 port_sel, u32 val)
1466 {
1467 if ((val & DP_PORT_EN) == 0)
1468 return false;
1469
1470 if (HAS_PCH_CPT(dev_priv->dev)) {
1471 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1472 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1473 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1474 return false;
1475 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1476 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1477 return false;
1478 } else {
1479 if ((val & DP_PIPE_MASK) != (pipe << 30))
1480 return false;
1481 }
1482 return true;
1483 }
1484
1485 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1486 enum pipe pipe, u32 val)
1487 {
1488 if ((val & SDVO_ENABLE) == 0)
1489 return false;
1490
1491 if (HAS_PCH_CPT(dev_priv->dev)) {
1492 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1493 return false;
1494 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1495 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1496 return false;
1497 } else {
1498 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1499 return false;
1500 }
1501 return true;
1502 }
1503
1504 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1505 enum pipe pipe, u32 val)
1506 {
1507 if ((val & LVDS_PORT_EN) == 0)
1508 return false;
1509
1510 if (HAS_PCH_CPT(dev_priv->dev)) {
1511 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1512 return false;
1513 } else {
1514 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1515 return false;
1516 }
1517 return true;
1518 }
1519
1520 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1521 enum pipe pipe, u32 val)
1522 {
1523 if ((val & ADPA_DAC_ENABLE) == 0)
1524 return false;
1525 if (HAS_PCH_CPT(dev_priv->dev)) {
1526 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1527 return false;
1528 } else {
1529 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1530 return false;
1531 }
1532 return true;
1533 }
1534
1535 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1536 enum pipe pipe, int reg, u32 port_sel)
1537 {
1538 u32 val = I915_READ(reg);
1539 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1540 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1541 reg, pipe_name(pipe));
1542
1543 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1544 && (val & DP_PIPEB_SELECT),
1545 "IBX PCH dp port still using transcoder B\n");
1546 }
1547
1548 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1549 enum pipe pipe, int reg)
1550 {
1551 u32 val = I915_READ(reg);
1552 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1553 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1554 reg, pipe_name(pipe));
1555
1556 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1557 && (val & SDVO_PIPE_B_SELECT),
1558 "IBX PCH hdmi port still using transcoder B\n");
1559 }
1560
1561 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1562 enum pipe pipe)
1563 {
1564 int reg;
1565 u32 val;
1566
1567 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1568 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1569 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1570
1571 reg = PCH_ADPA;
1572 val = I915_READ(reg);
1573 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1574 "PCH VGA enabled on transcoder %c, should be disabled\n",
1575 pipe_name(pipe));
1576
1577 reg = PCH_LVDS;
1578 val = I915_READ(reg);
1579 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1580 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1581 pipe_name(pipe));
1582
1583 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1584 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1585 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1586 }
1587
1588 static void intel_init_dpio(struct drm_device *dev)
1589 {
1590 struct drm_i915_private *dev_priv = dev->dev_private;
1591
1592 if (!IS_VALLEYVIEW(dev))
1593 return;
1594
1595 /*
1596 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1597 * CHV x1 PHY (DP/HDMI D)
1598 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1599 */
1600 if (IS_CHERRYVIEW(dev)) {
1601 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1602 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1603 } else {
1604 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1605 }
1606 }
1607
1608 static void vlv_enable_pll(struct intel_crtc *crtc,
1609 const struct intel_crtc_state *pipe_config)
1610 {
1611 struct drm_device *dev = crtc->base.dev;
1612 struct drm_i915_private *dev_priv = dev->dev_private;
1613 int reg = DPLL(crtc->pipe);
1614 u32 dpll = pipe_config->dpll_hw_state.dpll;
1615
1616 assert_pipe_disabled(dev_priv, crtc->pipe);
1617
1618 /* No really, not for ILK+ */
1619 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1620
1621 /* PLL is protected by panel, make sure we can write it */
1622 if (IS_MOBILE(dev_priv->dev))
1623 assert_panel_unlocked(dev_priv, crtc->pipe);
1624
1625 I915_WRITE(reg, dpll);
1626 POSTING_READ(reg);
1627 udelay(150);
1628
1629 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1630 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1631
1632 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1633 POSTING_READ(DPLL_MD(crtc->pipe));
1634
1635 /* We do this three times for luck */
1636 I915_WRITE(reg, dpll);
1637 POSTING_READ(reg);
1638 udelay(150); /* wait for warmup */
1639 I915_WRITE(reg, dpll);
1640 POSTING_READ(reg);
1641 udelay(150); /* wait for warmup */
1642 I915_WRITE(reg, dpll);
1643 POSTING_READ(reg);
1644 udelay(150); /* wait for warmup */
1645 }
1646
1647 static void chv_enable_pll(struct intel_crtc *crtc,
1648 const struct intel_crtc_state *pipe_config)
1649 {
1650 struct drm_device *dev = crtc->base.dev;
1651 struct drm_i915_private *dev_priv = dev->dev_private;
1652 int pipe = crtc->pipe;
1653 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1654 u32 tmp;
1655
1656 assert_pipe_disabled(dev_priv, crtc->pipe);
1657
1658 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1659
1660 mutex_lock(&dev_priv->dpio_lock);
1661
1662 /* Enable back the 10bit clock to display controller */
1663 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1664 tmp |= DPIO_DCLKP_EN;
1665 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1666
1667 /*
1668 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1669 */
1670 udelay(1);
1671
1672 /* Enable PLL */
1673 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1674
1675 /* Check PLL is locked */
1676 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1677 DRM_ERROR("PLL %d failed to lock\n", pipe);
1678
1679 /* not sure when this should be written */
1680 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1681 POSTING_READ(DPLL_MD(pipe));
1682
1683 mutex_unlock(&dev_priv->dpio_lock);
1684 }
1685
1686 static int intel_num_dvo_pipes(struct drm_device *dev)
1687 {
1688 struct intel_crtc *crtc;
1689 int count = 0;
1690
1691 for_each_intel_crtc(dev, crtc)
1692 count += crtc->active &&
1693 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1694
1695 return count;
1696 }
1697
1698 static void i9xx_enable_pll(struct intel_crtc *crtc)
1699 {
1700 struct drm_device *dev = crtc->base.dev;
1701 struct drm_i915_private *dev_priv = dev->dev_private;
1702 int reg = DPLL(crtc->pipe);
1703 u32 dpll = crtc->config->dpll_hw_state.dpll;
1704
1705 assert_pipe_disabled(dev_priv, crtc->pipe);
1706
1707 /* No really, not for ILK+ */
1708 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1709
1710 /* PLL is protected by panel, make sure we can write it */
1711 if (IS_MOBILE(dev) && !IS_I830(dev))
1712 assert_panel_unlocked(dev_priv, crtc->pipe);
1713
1714 /* Enable DVO 2x clock on both PLLs if necessary */
1715 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1716 /*
1717 * It appears to be important that we don't enable this
1718 * for the current pipe before otherwise configuring the
1719 * PLL. No idea how this should be handled if multiple
1720 * DVO outputs are enabled simultaneosly.
1721 */
1722 dpll |= DPLL_DVO_2X_MODE;
1723 I915_WRITE(DPLL(!crtc->pipe),
1724 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1725 }
1726
1727 /* Wait for the clocks to stabilize. */
1728 POSTING_READ(reg);
1729 udelay(150);
1730
1731 if (INTEL_INFO(dev)->gen >= 4) {
1732 I915_WRITE(DPLL_MD(crtc->pipe),
1733 crtc->config->dpll_hw_state.dpll_md);
1734 } else {
1735 /* The pixel multiplier can only be updated once the
1736 * DPLL is enabled and the clocks are stable.
1737 *
1738 * So write it again.
1739 */
1740 I915_WRITE(reg, dpll);
1741 }
1742
1743 /* We do this three times for luck */
1744 I915_WRITE(reg, dpll);
1745 POSTING_READ(reg);
1746 udelay(150); /* wait for warmup */
1747 I915_WRITE(reg, dpll);
1748 POSTING_READ(reg);
1749 udelay(150); /* wait for warmup */
1750 I915_WRITE(reg, dpll);
1751 POSTING_READ(reg);
1752 udelay(150); /* wait for warmup */
1753 }
1754
1755 /**
1756 * i9xx_disable_pll - disable a PLL
1757 * @dev_priv: i915 private structure
1758 * @pipe: pipe PLL to disable
1759 *
1760 * Disable the PLL for @pipe, making sure the pipe is off first.
1761 *
1762 * Note! This is for pre-ILK only.
1763 */
1764 static void i9xx_disable_pll(struct intel_crtc *crtc)
1765 {
1766 struct drm_device *dev = crtc->base.dev;
1767 struct drm_i915_private *dev_priv = dev->dev_private;
1768 enum pipe pipe = crtc->pipe;
1769
1770 /* Disable DVO 2x clock on both PLLs if necessary */
1771 if (IS_I830(dev) &&
1772 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1773 intel_num_dvo_pipes(dev) == 1) {
1774 I915_WRITE(DPLL(PIPE_B),
1775 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1776 I915_WRITE(DPLL(PIPE_A),
1777 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1778 }
1779
1780 /* Don't disable pipe or pipe PLLs if needed */
1781 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1782 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1783 return;
1784
1785 /* Make sure the pipe isn't still relying on us */
1786 assert_pipe_disabled(dev_priv, pipe);
1787
1788 I915_WRITE(DPLL(pipe), 0);
1789 POSTING_READ(DPLL(pipe));
1790 }
1791
1792 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1793 {
1794 u32 val = 0;
1795
1796 /* Make sure the pipe isn't still relying on us */
1797 assert_pipe_disabled(dev_priv, pipe);
1798
1799 /*
1800 * Leave integrated clock source and reference clock enabled for pipe B.
1801 * The latter is needed for VGA hotplug / manual detection.
1802 */
1803 if (pipe == PIPE_B)
1804 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1805 I915_WRITE(DPLL(pipe), val);
1806 POSTING_READ(DPLL(pipe));
1807
1808 }
1809
1810 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1811 {
1812 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1813 u32 val;
1814
1815 /* Make sure the pipe isn't still relying on us */
1816 assert_pipe_disabled(dev_priv, pipe);
1817
1818 /* Set PLL en = 0 */
1819 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1820 if (pipe != PIPE_A)
1821 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1822 I915_WRITE(DPLL(pipe), val);
1823 POSTING_READ(DPLL(pipe));
1824
1825 mutex_lock(&dev_priv->dpio_lock);
1826
1827 /* Disable 10bit clock to display controller */
1828 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1829 val &= ~DPIO_DCLKP_EN;
1830 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1831
1832 /* disable left/right clock distribution */
1833 if (pipe != PIPE_B) {
1834 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1835 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1836 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1837 } else {
1838 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1839 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1840 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1841 }
1842
1843 mutex_unlock(&dev_priv->dpio_lock);
1844 }
1845
1846 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1847 struct intel_digital_port *dport)
1848 {
1849 u32 port_mask;
1850 int dpll_reg;
1851
1852 switch (dport->port) {
1853 case PORT_B:
1854 port_mask = DPLL_PORTB_READY_MASK;
1855 dpll_reg = DPLL(0);
1856 break;
1857 case PORT_C:
1858 port_mask = DPLL_PORTC_READY_MASK;
1859 dpll_reg = DPLL(0);
1860 break;
1861 case PORT_D:
1862 port_mask = DPLL_PORTD_READY_MASK;
1863 dpll_reg = DPIO_PHY_STATUS;
1864 break;
1865 default:
1866 BUG();
1867 }
1868
1869 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1870 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1871 port_name(dport->port), I915_READ(dpll_reg));
1872 }
1873
1874 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1875 {
1876 struct drm_device *dev = crtc->base.dev;
1877 struct drm_i915_private *dev_priv = dev->dev_private;
1878 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1879
1880 if (WARN_ON(pll == NULL))
1881 return;
1882
1883 WARN_ON(!pll->config.crtc_mask);
1884 if (pll->active == 0) {
1885 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1886 WARN_ON(pll->on);
1887 assert_shared_dpll_disabled(dev_priv, pll);
1888
1889 pll->mode_set(dev_priv, pll);
1890 }
1891 }
1892
1893 /**
1894 * intel_enable_shared_dpll - enable PCH PLL
1895 * @dev_priv: i915 private structure
1896 * @pipe: pipe PLL to enable
1897 *
1898 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1899 * drives the transcoder clock.
1900 */
1901 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1902 {
1903 struct drm_device *dev = crtc->base.dev;
1904 struct drm_i915_private *dev_priv = dev->dev_private;
1905 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1906
1907 if (WARN_ON(pll == NULL))
1908 return;
1909
1910 if (WARN_ON(pll->config.crtc_mask == 0))
1911 return;
1912
1913 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1914 pll->name, pll->active, pll->on,
1915 crtc->base.base.id);
1916
1917 if (pll->active++) {
1918 WARN_ON(!pll->on);
1919 assert_shared_dpll_enabled(dev_priv, pll);
1920 return;
1921 }
1922 WARN_ON(pll->on);
1923
1924 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1925
1926 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1927 pll->enable(dev_priv, pll);
1928 pll->on = true;
1929 }
1930
1931 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1932 {
1933 struct drm_device *dev = crtc->base.dev;
1934 struct drm_i915_private *dev_priv = dev->dev_private;
1935 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1936
1937 /* PCH only available on ILK+ */
1938 BUG_ON(INTEL_INFO(dev)->gen < 5);
1939 if (WARN_ON(pll == NULL))
1940 return;
1941
1942 if (WARN_ON(pll->config.crtc_mask == 0))
1943 return;
1944
1945 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1946 pll->name, pll->active, pll->on,
1947 crtc->base.base.id);
1948
1949 if (WARN_ON(pll->active == 0)) {
1950 assert_shared_dpll_disabled(dev_priv, pll);
1951 return;
1952 }
1953
1954 assert_shared_dpll_enabled(dev_priv, pll);
1955 WARN_ON(!pll->on);
1956 if (--pll->active)
1957 return;
1958
1959 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1960 pll->disable(dev_priv, pll);
1961 pll->on = false;
1962
1963 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1964 }
1965
1966 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1967 enum pipe pipe)
1968 {
1969 struct drm_device *dev = dev_priv->dev;
1970 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1971 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1972 uint32_t reg, val, pipeconf_val;
1973
1974 /* PCH only available on ILK+ */
1975 BUG_ON(!HAS_PCH_SPLIT(dev));
1976
1977 /* Make sure PCH DPLL is enabled */
1978 assert_shared_dpll_enabled(dev_priv,
1979 intel_crtc_to_shared_dpll(intel_crtc));
1980
1981 /* FDI must be feeding us bits for PCH ports */
1982 assert_fdi_tx_enabled(dev_priv, pipe);
1983 assert_fdi_rx_enabled(dev_priv, pipe);
1984
1985 if (HAS_PCH_CPT(dev)) {
1986 /* Workaround: Set the timing override bit before enabling the
1987 * pch transcoder. */
1988 reg = TRANS_CHICKEN2(pipe);
1989 val = I915_READ(reg);
1990 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1991 I915_WRITE(reg, val);
1992 }
1993
1994 reg = PCH_TRANSCONF(pipe);
1995 val = I915_READ(reg);
1996 pipeconf_val = I915_READ(PIPECONF(pipe));
1997
1998 if (HAS_PCH_IBX(dev_priv->dev)) {
1999 /*
2000 * make the BPC in transcoder be consistent with
2001 * that in pipeconf reg.
2002 */
2003 val &= ~PIPECONF_BPC_MASK;
2004 val |= pipeconf_val & PIPECONF_BPC_MASK;
2005 }
2006
2007 val &= ~TRANS_INTERLACE_MASK;
2008 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2009 if (HAS_PCH_IBX(dev_priv->dev) &&
2010 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2011 val |= TRANS_LEGACY_INTERLACED_ILK;
2012 else
2013 val |= TRANS_INTERLACED;
2014 else
2015 val |= TRANS_PROGRESSIVE;
2016
2017 I915_WRITE(reg, val | TRANS_ENABLE);
2018 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2019 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2020 }
2021
2022 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2023 enum transcoder cpu_transcoder)
2024 {
2025 u32 val, pipeconf_val;
2026
2027 /* PCH only available on ILK+ */
2028 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2029
2030 /* FDI must be feeding us bits for PCH ports */
2031 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2032 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2033
2034 /* Workaround: set timing override bit. */
2035 val = I915_READ(_TRANSA_CHICKEN2);
2036 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2037 I915_WRITE(_TRANSA_CHICKEN2, val);
2038
2039 val = TRANS_ENABLE;
2040 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2041
2042 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2043 PIPECONF_INTERLACED_ILK)
2044 val |= TRANS_INTERLACED;
2045 else
2046 val |= TRANS_PROGRESSIVE;
2047
2048 I915_WRITE(LPT_TRANSCONF, val);
2049 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2050 DRM_ERROR("Failed to enable PCH transcoder\n");
2051 }
2052
2053 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2054 enum pipe pipe)
2055 {
2056 struct drm_device *dev = dev_priv->dev;
2057 uint32_t reg, val;
2058
2059 /* FDI relies on the transcoder */
2060 assert_fdi_tx_disabled(dev_priv, pipe);
2061 assert_fdi_rx_disabled(dev_priv, pipe);
2062
2063 /* Ports must be off as well */
2064 assert_pch_ports_disabled(dev_priv, pipe);
2065
2066 reg = PCH_TRANSCONF(pipe);
2067 val = I915_READ(reg);
2068 val &= ~TRANS_ENABLE;
2069 I915_WRITE(reg, val);
2070 /* wait for PCH transcoder off, transcoder state */
2071 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2072 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2073
2074 if (!HAS_PCH_IBX(dev)) {
2075 /* Workaround: Clear the timing override chicken bit again. */
2076 reg = TRANS_CHICKEN2(pipe);
2077 val = I915_READ(reg);
2078 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2079 I915_WRITE(reg, val);
2080 }
2081 }
2082
2083 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2084 {
2085 u32 val;
2086
2087 val = I915_READ(LPT_TRANSCONF);
2088 val &= ~TRANS_ENABLE;
2089 I915_WRITE(LPT_TRANSCONF, val);
2090 /* wait for PCH transcoder off, transcoder state */
2091 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2092 DRM_ERROR("Failed to disable PCH transcoder\n");
2093
2094 /* Workaround: clear timing override bit. */
2095 val = I915_READ(_TRANSA_CHICKEN2);
2096 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2097 I915_WRITE(_TRANSA_CHICKEN2, val);
2098 }
2099
2100 /**
2101 * intel_enable_pipe - enable a pipe, asserting requirements
2102 * @crtc: crtc responsible for the pipe
2103 *
2104 * Enable @crtc's pipe, making sure that various hardware specific requirements
2105 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2106 */
2107 static void intel_enable_pipe(struct intel_crtc *crtc)
2108 {
2109 struct drm_device *dev = crtc->base.dev;
2110 struct drm_i915_private *dev_priv = dev->dev_private;
2111 enum pipe pipe = crtc->pipe;
2112 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2113 pipe);
2114 enum pipe pch_transcoder;
2115 int reg;
2116 u32 val;
2117
2118 assert_planes_disabled(dev_priv, pipe);
2119 assert_cursor_disabled(dev_priv, pipe);
2120 assert_sprites_disabled(dev_priv, pipe);
2121
2122 if (HAS_PCH_LPT(dev_priv->dev))
2123 pch_transcoder = TRANSCODER_A;
2124 else
2125 pch_transcoder = pipe;
2126
2127 /*
2128 * A pipe without a PLL won't actually be able to drive bits from
2129 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2130 * need the check.
2131 */
2132 if (HAS_GMCH_DISPLAY(dev_priv->dev))
2133 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2134 assert_dsi_pll_enabled(dev_priv);
2135 else
2136 assert_pll_enabled(dev_priv, pipe);
2137 else {
2138 if (crtc->config->has_pch_encoder) {
2139 /* if driving the PCH, we need FDI enabled */
2140 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2141 assert_fdi_tx_pll_enabled(dev_priv,
2142 (enum pipe) cpu_transcoder);
2143 }
2144 /* FIXME: assert CPU port conditions for SNB+ */
2145 }
2146
2147 reg = PIPECONF(cpu_transcoder);
2148 val = I915_READ(reg);
2149 if (val & PIPECONF_ENABLE) {
2150 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2151 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2152 return;
2153 }
2154
2155 I915_WRITE(reg, val | PIPECONF_ENABLE);
2156 POSTING_READ(reg);
2157 }
2158
2159 /**
2160 * intel_disable_pipe - disable a pipe, asserting requirements
2161 * @crtc: crtc whose pipes is to be disabled
2162 *
2163 * Disable the pipe of @crtc, making sure that various hardware
2164 * specific requirements are met, if applicable, e.g. plane
2165 * disabled, panel fitter off, etc.
2166 *
2167 * Will wait until the pipe has shut down before returning.
2168 */
2169 static void intel_disable_pipe(struct intel_crtc *crtc)
2170 {
2171 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2172 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2173 enum pipe pipe = crtc->pipe;
2174 int reg;
2175 u32 val;
2176
2177 /*
2178 * Make sure planes won't keep trying to pump pixels to us,
2179 * or we might hang the display.
2180 */
2181 assert_planes_disabled(dev_priv, pipe);
2182 assert_cursor_disabled(dev_priv, pipe);
2183 assert_sprites_disabled(dev_priv, pipe);
2184
2185 reg = PIPECONF(cpu_transcoder);
2186 val = I915_READ(reg);
2187 if ((val & PIPECONF_ENABLE) == 0)
2188 return;
2189
2190 /*
2191 * Double wide has implications for planes
2192 * so best keep it disabled when not needed.
2193 */
2194 if (crtc->config->double_wide)
2195 val &= ~PIPECONF_DOUBLE_WIDE;
2196
2197 /* Don't disable pipe or pipe PLLs if needed */
2198 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2199 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2200 val &= ~PIPECONF_ENABLE;
2201
2202 I915_WRITE(reg, val);
2203 if ((val & PIPECONF_ENABLE) == 0)
2204 intel_wait_for_pipe_off(crtc);
2205 }
2206
2207 /*
2208 * Plane regs are double buffered, going from enabled->disabled needs a
2209 * trigger in order to latch. The display address reg provides this.
2210 */
2211 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2212 enum plane plane)
2213 {
2214 struct drm_device *dev = dev_priv->dev;
2215 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2216
2217 I915_WRITE(reg, I915_READ(reg));
2218 POSTING_READ(reg);
2219 }
2220
2221 /**
2222 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2223 * @plane: plane to be enabled
2224 * @crtc: crtc for the plane
2225 *
2226 * Enable @plane on @crtc, making sure that the pipe is running first.
2227 */
2228 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2229 struct drm_crtc *crtc)
2230 {
2231 struct drm_device *dev = plane->dev;
2232 struct drm_i915_private *dev_priv = dev->dev_private;
2233 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2234
2235 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2236 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2237 to_intel_plane_state(plane->state)->visible = true;
2238
2239 dev_priv->display.update_primary_plane(crtc, plane->fb,
2240 crtc->x, crtc->y);
2241 }
2242
2243 static bool need_vtd_wa(struct drm_device *dev)
2244 {
2245 #ifdef CONFIG_INTEL_IOMMU
2246 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2247 return true;
2248 #endif
2249 return false;
2250 }
2251
2252 unsigned int
2253 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2254 uint64_t fb_format_modifier)
2255 {
2256 unsigned int tile_height;
2257 uint32_t pixel_bytes;
2258
2259 switch (fb_format_modifier) {
2260 case DRM_FORMAT_MOD_NONE:
2261 tile_height = 1;
2262 break;
2263 case I915_FORMAT_MOD_X_TILED:
2264 tile_height = IS_GEN2(dev) ? 16 : 8;
2265 break;
2266 case I915_FORMAT_MOD_Y_TILED:
2267 tile_height = 32;
2268 break;
2269 case I915_FORMAT_MOD_Yf_TILED:
2270 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2271 switch (pixel_bytes) {
2272 default:
2273 case 1:
2274 tile_height = 64;
2275 break;
2276 case 2:
2277 case 4:
2278 tile_height = 32;
2279 break;
2280 case 8:
2281 tile_height = 16;
2282 break;
2283 case 16:
2284 WARN_ONCE(1,
2285 "128-bit pixels are not supported for display!");
2286 tile_height = 16;
2287 break;
2288 }
2289 break;
2290 default:
2291 MISSING_CASE(fb_format_modifier);
2292 tile_height = 1;
2293 break;
2294 }
2295
2296 return tile_height;
2297 }
2298
2299 unsigned int
2300 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2301 uint32_t pixel_format, uint64_t fb_format_modifier)
2302 {
2303 return ALIGN(height, intel_tile_height(dev, pixel_format,
2304 fb_format_modifier));
2305 }
2306
2307 static int
2308 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2309 const struct drm_plane_state *plane_state)
2310 {
2311 struct intel_rotation_info *info = &view->rotation_info;
2312
2313 *view = i915_ggtt_view_normal;
2314
2315 if (!plane_state)
2316 return 0;
2317
2318 if (!intel_rotation_90_or_270(plane_state->rotation))
2319 return 0;
2320
2321 *view = i915_ggtt_view_rotated;
2322
2323 info->height = fb->height;
2324 info->pixel_format = fb->pixel_format;
2325 info->pitch = fb->pitches[0];
2326 info->fb_modifier = fb->modifier[0];
2327
2328 return 0;
2329 }
2330
2331 int
2332 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2333 struct drm_framebuffer *fb,
2334 const struct drm_plane_state *plane_state,
2335 struct intel_engine_cs *pipelined)
2336 {
2337 struct drm_device *dev = fb->dev;
2338 struct drm_i915_private *dev_priv = dev->dev_private;
2339 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2340 struct i915_ggtt_view view;
2341 u32 alignment;
2342 int ret;
2343
2344 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2345
2346 switch (fb->modifier[0]) {
2347 case DRM_FORMAT_MOD_NONE:
2348 if (INTEL_INFO(dev)->gen >= 9)
2349 alignment = 256 * 1024;
2350 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2351 alignment = 128 * 1024;
2352 else if (INTEL_INFO(dev)->gen >= 4)
2353 alignment = 4 * 1024;
2354 else
2355 alignment = 64 * 1024;
2356 break;
2357 case I915_FORMAT_MOD_X_TILED:
2358 if (INTEL_INFO(dev)->gen >= 9)
2359 alignment = 256 * 1024;
2360 else {
2361 /* pin() will align the object as required by fence */
2362 alignment = 0;
2363 }
2364 break;
2365 case I915_FORMAT_MOD_Y_TILED:
2366 case I915_FORMAT_MOD_Yf_TILED:
2367 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2368 "Y tiling bo slipped through, driver bug!\n"))
2369 return -EINVAL;
2370 alignment = 1 * 1024 * 1024;
2371 break;
2372 default:
2373 MISSING_CASE(fb->modifier[0]);
2374 return -EINVAL;
2375 }
2376
2377 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2378 if (ret)
2379 return ret;
2380
2381 /* Note that the w/a also requires 64 PTE of padding following the
2382 * bo. We currently fill all unused PTE with the shadow page and so
2383 * we should always have valid PTE following the scanout preventing
2384 * the VT-d warning.
2385 */
2386 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2387 alignment = 256 * 1024;
2388
2389 /*
2390 * Global gtt pte registers are special registers which actually forward
2391 * writes to a chunk of system memory. Which means that there is no risk
2392 * that the register values disappear as soon as we call
2393 * intel_runtime_pm_put(), so it is correct to wrap only the
2394 * pin/unpin/fence and not more.
2395 */
2396 intel_runtime_pm_get(dev_priv);
2397
2398 dev_priv->mm.interruptible = false;
2399 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2400 &view);
2401 if (ret)
2402 goto err_interruptible;
2403
2404 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2405 * fence, whereas 965+ only requires a fence if using
2406 * framebuffer compression. For simplicity, we always install
2407 * a fence as the cost is not that onerous.
2408 */
2409 ret = i915_gem_object_get_fence(obj);
2410 if (ret)
2411 goto err_unpin;
2412
2413 i915_gem_object_pin_fence(obj);
2414
2415 dev_priv->mm.interruptible = true;
2416 intel_runtime_pm_put(dev_priv);
2417 return 0;
2418
2419 err_unpin:
2420 i915_gem_object_unpin_from_display_plane(obj, &view);
2421 err_interruptible:
2422 dev_priv->mm.interruptible = true;
2423 intel_runtime_pm_put(dev_priv);
2424 return ret;
2425 }
2426
2427 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2428 const struct drm_plane_state *plane_state)
2429 {
2430 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2431 struct i915_ggtt_view view;
2432 int ret;
2433
2434 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2435
2436 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2437 WARN_ONCE(ret, "Couldn't get view from plane state!");
2438
2439 i915_gem_object_unpin_fence(obj);
2440 i915_gem_object_unpin_from_display_plane(obj, &view);
2441 }
2442
2443 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2444 * is assumed to be a power-of-two. */
2445 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2446 unsigned int tiling_mode,
2447 unsigned int cpp,
2448 unsigned int pitch)
2449 {
2450 if (tiling_mode != I915_TILING_NONE) {
2451 unsigned int tile_rows, tiles;
2452
2453 tile_rows = *y / 8;
2454 *y %= 8;
2455
2456 tiles = *x / (512/cpp);
2457 *x %= 512/cpp;
2458
2459 return tile_rows * pitch * 8 + tiles * 4096;
2460 } else {
2461 unsigned int offset;
2462
2463 offset = *y * pitch + *x * cpp;
2464 *y = 0;
2465 *x = (offset & 4095) / cpp;
2466 return offset & -4096;
2467 }
2468 }
2469
2470 static int i9xx_format_to_fourcc(int format)
2471 {
2472 switch (format) {
2473 case DISPPLANE_8BPP:
2474 return DRM_FORMAT_C8;
2475 case DISPPLANE_BGRX555:
2476 return DRM_FORMAT_XRGB1555;
2477 case DISPPLANE_BGRX565:
2478 return DRM_FORMAT_RGB565;
2479 default:
2480 case DISPPLANE_BGRX888:
2481 return DRM_FORMAT_XRGB8888;
2482 case DISPPLANE_RGBX888:
2483 return DRM_FORMAT_XBGR8888;
2484 case DISPPLANE_BGRX101010:
2485 return DRM_FORMAT_XRGB2101010;
2486 case DISPPLANE_RGBX101010:
2487 return DRM_FORMAT_XBGR2101010;
2488 }
2489 }
2490
2491 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2492 {
2493 switch (format) {
2494 case PLANE_CTL_FORMAT_RGB_565:
2495 return DRM_FORMAT_RGB565;
2496 default:
2497 case PLANE_CTL_FORMAT_XRGB_8888:
2498 if (rgb_order) {
2499 if (alpha)
2500 return DRM_FORMAT_ABGR8888;
2501 else
2502 return DRM_FORMAT_XBGR8888;
2503 } else {
2504 if (alpha)
2505 return DRM_FORMAT_ARGB8888;
2506 else
2507 return DRM_FORMAT_XRGB8888;
2508 }
2509 case PLANE_CTL_FORMAT_XRGB_2101010:
2510 if (rgb_order)
2511 return DRM_FORMAT_XBGR2101010;
2512 else
2513 return DRM_FORMAT_XRGB2101010;
2514 }
2515 }
2516
2517 static bool
2518 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2519 struct intel_initial_plane_config *plane_config)
2520 {
2521 struct drm_device *dev = crtc->base.dev;
2522 struct drm_i915_gem_object *obj = NULL;
2523 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2524 struct drm_framebuffer *fb = &plane_config->fb->base;
2525 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2526 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2527 PAGE_SIZE);
2528
2529 size_aligned -= base_aligned;
2530
2531 if (plane_config->size == 0)
2532 return false;
2533
2534 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2535 base_aligned,
2536 base_aligned,
2537 size_aligned);
2538 if (!obj)
2539 return false;
2540
2541 obj->tiling_mode = plane_config->tiling;
2542 if (obj->tiling_mode == I915_TILING_X)
2543 obj->stride = fb->pitches[0];
2544
2545 mode_cmd.pixel_format = fb->pixel_format;
2546 mode_cmd.width = fb->width;
2547 mode_cmd.height = fb->height;
2548 mode_cmd.pitches[0] = fb->pitches[0];
2549 mode_cmd.modifier[0] = fb->modifier[0];
2550 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2551
2552 mutex_lock(&dev->struct_mutex);
2553 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2554 &mode_cmd, obj)) {
2555 DRM_DEBUG_KMS("intel fb init failed\n");
2556 goto out_unref_obj;
2557 }
2558 mutex_unlock(&dev->struct_mutex);
2559
2560 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2561 return true;
2562
2563 out_unref_obj:
2564 drm_gem_object_unreference(&obj->base);
2565 mutex_unlock(&dev->struct_mutex);
2566 return false;
2567 }
2568
2569 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2570 static void
2571 update_state_fb(struct drm_plane *plane)
2572 {
2573 if (plane->fb == plane->state->fb)
2574 return;
2575
2576 if (plane->state->fb)
2577 drm_framebuffer_unreference(plane->state->fb);
2578 plane->state->fb = plane->fb;
2579 if (plane->state->fb)
2580 drm_framebuffer_reference(plane->state->fb);
2581 }
2582
2583 static void
2584 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2585 struct intel_initial_plane_config *plane_config)
2586 {
2587 struct drm_device *dev = intel_crtc->base.dev;
2588 struct drm_i915_private *dev_priv = dev->dev_private;
2589 struct drm_crtc *c;
2590 struct intel_crtc *i;
2591 struct drm_i915_gem_object *obj;
2592 struct drm_plane *primary = intel_crtc->base.primary;
2593 struct drm_framebuffer *fb;
2594
2595 if (!plane_config->fb)
2596 return;
2597
2598 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2599 fb = &plane_config->fb->base;
2600 goto valid_fb;
2601 }
2602
2603 kfree(plane_config->fb);
2604
2605 /*
2606 * Failed to alloc the obj, check to see if we should share
2607 * an fb with another CRTC instead
2608 */
2609 for_each_crtc(dev, c) {
2610 i = to_intel_crtc(c);
2611
2612 if (c == &intel_crtc->base)
2613 continue;
2614
2615 if (!i->active)
2616 continue;
2617
2618 fb = c->primary->fb;
2619 if (!fb)
2620 continue;
2621
2622 obj = intel_fb_obj(fb);
2623 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2624 drm_framebuffer_reference(fb);
2625 goto valid_fb;
2626 }
2627 }
2628
2629 return;
2630
2631 valid_fb:
2632 obj = intel_fb_obj(fb);
2633 if (obj->tiling_mode != I915_TILING_NONE)
2634 dev_priv->preserve_bios_swizzle = true;
2635
2636 primary->fb = fb;
2637 primary->state->crtc = &intel_crtc->base;
2638 primary->crtc = &intel_crtc->base;
2639 update_state_fb(primary);
2640 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2641 }
2642
2643 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2644 struct drm_framebuffer *fb,
2645 int x, int y)
2646 {
2647 struct drm_device *dev = crtc->dev;
2648 struct drm_i915_private *dev_priv = dev->dev_private;
2649 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2650 struct drm_plane *primary = crtc->primary;
2651 bool visible = to_intel_plane_state(primary->state)->visible;
2652 struct drm_i915_gem_object *obj;
2653 int plane = intel_crtc->plane;
2654 unsigned long linear_offset;
2655 u32 dspcntr;
2656 u32 reg = DSPCNTR(plane);
2657 int pixel_size;
2658
2659 if (!visible || !fb) {
2660 I915_WRITE(reg, 0);
2661 if (INTEL_INFO(dev)->gen >= 4)
2662 I915_WRITE(DSPSURF(plane), 0);
2663 else
2664 I915_WRITE(DSPADDR(plane), 0);
2665 POSTING_READ(reg);
2666 return;
2667 }
2668
2669 obj = intel_fb_obj(fb);
2670 if (WARN_ON(obj == NULL))
2671 return;
2672
2673 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2674
2675 dspcntr = DISPPLANE_GAMMA_ENABLE;
2676
2677 dspcntr |= DISPLAY_PLANE_ENABLE;
2678
2679 if (INTEL_INFO(dev)->gen < 4) {
2680 if (intel_crtc->pipe == PIPE_B)
2681 dspcntr |= DISPPLANE_SEL_PIPE_B;
2682
2683 /* pipesrc and dspsize control the size that is scaled from,
2684 * which should always be the user's requested size.
2685 */
2686 I915_WRITE(DSPSIZE(plane),
2687 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2688 (intel_crtc->config->pipe_src_w - 1));
2689 I915_WRITE(DSPPOS(plane), 0);
2690 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2691 I915_WRITE(PRIMSIZE(plane),
2692 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2693 (intel_crtc->config->pipe_src_w - 1));
2694 I915_WRITE(PRIMPOS(plane), 0);
2695 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2696 }
2697
2698 switch (fb->pixel_format) {
2699 case DRM_FORMAT_C8:
2700 dspcntr |= DISPPLANE_8BPP;
2701 break;
2702 case DRM_FORMAT_XRGB1555:
2703 case DRM_FORMAT_ARGB1555:
2704 dspcntr |= DISPPLANE_BGRX555;
2705 break;
2706 case DRM_FORMAT_RGB565:
2707 dspcntr |= DISPPLANE_BGRX565;
2708 break;
2709 case DRM_FORMAT_XRGB8888:
2710 case DRM_FORMAT_ARGB8888:
2711 dspcntr |= DISPPLANE_BGRX888;
2712 break;
2713 case DRM_FORMAT_XBGR8888:
2714 case DRM_FORMAT_ABGR8888:
2715 dspcntr |= DISPPLANE_RGBX888;
2716 break;
2717 case DRM_FORMAT_XRGB2101010:
2718 case DRM_FORMAT_ARGB2101010:
2719 dspcntr |= DISPPLANE_BGRX101010;
2720 break;
2721 case DRM_FORMAT_XBGR2101010:
2722 case DRM_FORMAT_ABGR2101010:
2723 dspcntr |= DISPPLANE_RGBX101010;
2724 break;
2725 default:
2726 BUG();
2727 }
2728
2729 if (INTEL_INFO(dev)->gen >= 4 &&
2730 obj->tiling_mode != I915_TILING_NONE)
2731 dspcntr |= DISPPLANE_TILED;
2732
2733 if (IS_G4X(dev))
2734 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2735
2736 linear_offset = y * fb->pitches[0] + x * pixel_size;
2737
2738 if (INTEL_INFO(dev)->gen >= 4) {
2739 intel_crtc->dspaddr_offset =
2740 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2741 pixel_size,
2742 fb->pitches[0]);
2743 linear_offset -= intel_crtc->dspaddr_offset;
2744 } else {
2745 intel_crtc->dspaddr_offset = linear_offset;
2746 }
2747
2748 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2749 dspcntr |= DISPPLANE_ROTATE_180;
2750
2751 x += (intel_crtc->config->pipe_src_w - 1);
2752 y += (intel_crtc->config->pipe_src_h - 1);
2753
2754 /* Finding the last pixel of the last line of the display
2755 data and adding to linear_offset*/
2756 linear_offset +=
2757 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2758 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2759 }
2760
2761 I915_WRITE(reg, dspcntr);
2762
2763 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2764 if (INTEL_INFO(dev)->gen >= 4) {
2765 I915_WRITE(DSPSURF(plane),
2766 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2767 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2768 I915_WRITE(DSPLINOFF(plane), linear_offset);
2769 } else
2770 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2771 POSTING_READ(reg);
2772 }
2773
2774 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2775 struct drm_framebuffer *fb,
2776 int x, int y)
2777 {
2778 struct drm_device *dev = crtc->dev;
2779 struct drm_i915_private *dev_priv = dev->dev_private;
2780 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2781 struct drm_plane *primary = crtc->primary;
2782 bool visible = to_intel_plane_state(primary->state)->visible;
2783 struct drm_i915_gem_object *obj;
2784 int plane = intel_crtc->plane;
2785 unsigned long linear_offset;
2786 u32 dspcntr;
2787 u32 reg = DSPCNTR(plane);
2788 int pixel_size;
2789
2790 if (!visible || !fb) {
2791 I915_WRITE(reg, 0);
2792 I915_WRITE(DSPSURF(plane), 0);
2793 POSTING_READ(reg);
2794 return;
2795 }
2796
2797 obj = intel_fb_obj(fb);
2798 if (WARN_ON(obj == NULL))
2799 return;
2800
2801 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2802
2803 dspcntr = DISPPLANE_GAMMA_ENABLE;
2804
2805 dspcntr |= DISPLAY_PLANE_ENABLE;
2806
2807 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2808 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2809
2810 switch (fb->pixel_format) {
2811 case DRM_FORMAT_C8:
2812 dspcntr |= DISPPLANE_8BPP;
2813 break;
2814 case DRM_FORMAT_RGB565:
2815 dspcntr |= DISPPLANE_BGRX565;
2816 break;
2817 case DRM_FORMAT_XRGB8888:
2818 case DRM_FORMAT_ARGB8888:
2819 dspcntr |= DISPPLANE_BGRX888;
2820 break;
2821 case DRM_FORMAT_XBGR8888:
2822 case DRM_FORMAT_ABGR8888:
2823 dspcntr |= DISPPLANE_RGBX888;
2824 break;
2825 case DRM_FORMAT_XRGB2101010:
2826 case DRM_FORMAT_ARGB2101010:
2827 dspcntr |= DISPPLANE_BGRX101010;
2828 break;
2829 case DRM_FORMAT_XBGR2101010:
2830 case DRM_FORMAT_ABGR2101010:
2831 dspcntr |= DISPPLANE_RGBX101010;
2832 break;
2833 default:
2834 BUG();
2835 }
2836
2837 if (obj->tiling_mode != I915_TILING_NONE)
2838 dspcntr |= DISPPLANE_TILED;
2839
2840 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2841 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2842
2843 linear_offset = y * fb->pitches[0] + x * pixel_size;
2844 intel_crtc->dspaddr_offset =
2845 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2846 pixel_size,
2847 fb->pitches[0]);
2848 linear_offset -= intel_crtc->dspaddr_offset;
2849 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2850 dspcntr |= DISPPLANE_ROTATE_180;
2851
2852 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2853 x += (intel_crtc->config->pipe_src_w - 1);
2854 y += (intel_crtc->config->pipe_src_h - 1);
2855
2856 /* Finding the last pixel of the last line of the display
2857 data and adding to linear_offset*/
2858 linear_offset +=
2859 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2860 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2861 }
2862 }
2863
2864 I915_WRITE(reg, dspcntr);
2865
2866 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2867 I915_WRITE(DSPSURF(plane),
2868 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2869 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2870 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2871 } else {
2872 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2873 I915_WRITE(DSPLINOFF(plane), linear_offset);
2874 }
2875 POSTING_READ(reg);
2876 }
2877
2878 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2879 uint32_t pixel_format)
2880 {
2881 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2882
2883 /*
2884 * The stride is either expressed as a multiple of 64 bytes
2885 * chunks for linear buffers or in number of tiles for tiled
2886 * buffers.
2887 */
2888 switch (fb_modifier) {
2889 case DRM_FORMAT_MOD_NONE:
2890 return 64;
2891 case I915_FORMAT_MOD_X_TILED:
2892 if (INTEL_INFO(dev)->gen == 2)
2893 return 128;
2894 return 512;
2895 case I915_FORMAT_MOD_Y_TILED:
2896 /* No need to check for old gens and Y tiling since this is
2897 * about the display engine and those will be blocked before
2898 * we get here.
2899 */
2900 return 128;
2901 case I915_FORMAT_MOD_Yf_TILED:
2902 if (bits_per_pixel == 8)
2903 return 64;
2904 else
2905 return 128;
2906 default:
2907 MISSING_CASE(fb_modifier);
2908 return 64;
2909 }
2910 }
2911
2912 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2913 struct drm_i915_gem_object *obj)
2914 {
2915 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2916
2917 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2918 view = &i915_ggtt_view_rotated;
2919
2920 return i915_gem_obj_ggtt_offset_view(obj, view);
2921 }
2922
2923 /*
2924 * This function detaches (aka. unbinds) unused scalers in hardware
2925 */
2926 void skl_detach_scalers(struct intel_crtc *intel_crtc)
2927 {
2928 struct drm_device *dev;
2929 struct drm_i915_private *dev_priv;
2930 struct intel_crtc_scaler_state *scaler_state;
2931 int i;
2932
2933 if (!intel_crtc || !intel_crtc->config)
2934 return;
2935
2936 dev = intel_crtc->base.dev;
2937 dev_priv = dev->dev_private;
2938 scaler_state = &intel_crtc->config->scaler_state;
2939
2940 /* loop through and disable scalers that aren't in use */
2941 for (i = 0; i < intel_crtc->num_scalers; i++) {
2942 if (!scaler_state->scalers[i].in_use) {
2943 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2944 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2945 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2946 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2947 intel_crtc->base.base.id, intel_crtc->pipe, i);
2948 }
2949 }
2950 }
2951
2952 u32 skl_plane_ctl_format(uint32_t pixel_format)
2953 {
2954 u32 plane_ctl_format = 0;
2955 switch (pixel_format) {
2956 case DRM_FORMAT_RGB565:
2957 plane_ctl_format = PLANE_CTL_FORMAT_RGB_565;
2958 break;
2959 case DRM_FORMAT_XBGR8888:
2960 plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2961 break;
2962 case DRM_FORMAT_XRGB8888:
2963 plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888;
2964 break;
2965 /*
2966 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2967 * to be already pre-multiplied. We need to add a knob (or a different
2968 * DRM_FORMAT) for user-space to configure that.
2969 */
2970 case DRM_FORMAT_ABGR8888:
2971 plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2972 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2973 break;
2974 case DRM_FORMAT_ARGB8888:
2975 plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888 |
2976 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2977 break;
2978 case DRM_FORMAT_XRGB2101010:
2979 plane_ctl_format = PLANE_CTL_FORMAT_XRGB_2101010;
2980 break;
2981 case DRM_FORMAT_XBGR2101010:
2982 plane_ctl_format = PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2983 break;
2984 case DRM_FORMAT_YUYV:
2985 plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2986 break;
2987 case DRM_FORMAT_YVYU:
2988 plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2989 break;
2990 case DRM_FORMAT_UYVY:
2991 plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2992 break;
2993 case DRM_FORMAT_VYUY:
2994 plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2995 break;
2996 default:
2997 BUG();
2998 }
2999 return plane_ctl_format;
3000 }
3001
3002 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3003 {
3004 u32 plane_ctl_tiling = 0;
3005 switch (fb_modifier) {
3006 case DRM_FORMAT_MOD_NONE:
3007 break;
3008 case I915_FORMAT_MOD_X_TILED:
3009 plane_ctl_tiling = PLANE_CTL_TILED_X;
3010 break;
3011 case I915_FORMAT_MOD_Y_TILED:
3012 plane_ctl_tiling = PLANE_CTL_TILED_Y;
3013 break;
3014 case I915_FORMAT_MOD_Yf_TILED:
3015 plane_ctl_tiling = PLANE_CTL_TILED_YF;
3016 break;
3017 default:
3018 MISSING_CASE(fb_modifier);
3019 }
3020 return plane_ctl_tiling;
3021 }
3022
3023 u32 skl_plane_ctl_rotation(unsigned int rotation)
3024 {
3025 u32 plane_ctl_rotation = 0;
3026 switch (rotation) {
3027 case BIT(DRM_ROTATE_0):
3028 break;
3029 case BIT(DRM_ROTATE_90):
3030 plane_ctl_rotation = PLANE_CTL_ROTATE_90;
3031 break;
3032 case BIT(DRM_ROTATE_180):
3033 plane_ctl_rotation = PLANE_CTL_ROTATE_180;
3034 break;
3035 case BIT(DRM_ROTATE_270):
3036 plane_ctl_rotation = PLANE_CTL_ROTATE_270;
3037 break;
3038 default:
3039 MISSING_CASE(rotation);
3040 }
3041
3042 return plane_ctl_rotation;
3043 }
3044
3045 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3046 struct drm_framebuffer *fb,
3047 int x, int y)
3048 {
3049 struct drm_device *dev = crtc->dev;
3050 struct drm_i915_private *dev_priv = dev->dev_private;
3051 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3052 struct drm_plane *plane = crtc->primary;
3053 bool visible = to_intel_plane_state(plane->state)->visible;
3054 struct drm_i915_gem_object *obj;
3055 int pipe = intel_crtc->pipe;
3056 u32 plane_ctl, stride_div, stride;
3057 u32 tile_height, plane_offset, plane_size;
3058 unsigned int rotation;
3059 int x_offset, y_offset;
3060 unsigned long surf_addr;
3061 struct intel_crtc_state *crtc_state = intel_crtc->config;
3062 struct intel_plane_state *plane_state;
3063 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3064 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3065 int scaler_id = -1;
3066
3067 plane_state = to_intel_plane_state(plane->state);
3068
3069 if (!visible || !fb) {
3070 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3071 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3072 POSTING_READ(PLANE_CTL(pipe, 0));
3073 return;
3074 }
3075
3076 plane_ctl = PLANE_CTL_ENABLE |
3077 PLANE_CTL_PIPE_GAMMA_ENABLE |
3078 PLANE_CTL_PIPE_CSC_ENABLE;
3079
3080 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3081 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3082 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3083
3084 rotation = plane->state->rotation;
3085 plane_ctl |= skl_plane_ctl_rotation(rotation);
3086
3087 obj = intel_fb_obj(fb);
3088 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3089 fb->pixel_format);
3090 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3091
3092 /*
3093 * FIXME: intel_plane_state->src, dst aren't set when transitional
3094 * update_plane helpers are called from legacy paths.
3095 * Once full atomic crtc is available, below check can be avoided.
3096 */
3097 if (drm_rect_width(&plane_state->src)) {
3098 scaler_id = plane_state->scaler_id;
3099 src_x = plane_state->src.x1 >> 16;
3100 src_y = plane_state->src.y1 >> 16;
3101 src_w = drm_rect_width(&plane_state->src) >> 16;
3102 src_h = drm_rect_height(&plane_state->src) >> 16;
3103 dst_x = plane_state->dst.x1;
3104 dst_y = plane_state->dst.y1;
3105 dst_w = drm_rect_width(&plane_state->dst);
3106 dst_h = drm_rect_height(&plane_state->dst);
3107
3108 WARN_ON(x != src_x || y != src_y);
3109 } else {
3110 src_w = intel_crtc->config->pipe_src_w;
3111 src_h = intel_crtc->config->pipe_src_h;
3112 }
3113
3114 if (intel_rotation_90_or_270(rotation)) {
3115 /* stride = Surface height in tiles */
3116 tile_height = intel_tile_height(dev, fb->bits_per_pixel,
3117 fb->modifier[0]);
3118 stride = DIV_ROUND_UP(fb->height, tile_height);
3119 x_offset = stride * tile_height - y - src_h;
3120 y_offset = x;
3121 plane_size = (src_w - 1) << 16 | (src_h - 1);
3122 } else {
3123 stride = fb->pitches[0] / stride_div;
3124 x_offset = x;
3125 y_offset = y;
3126 plane_size = (src_h - 1) << 16 | (src_w - 1);
3127 }
3128 plane_offset = y_offset << 16 | x_offset;
3129
3130 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3131 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3132 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3133 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3134
3135 if (scaler_id >= 0) {
3136 uint32_t ps_ctrl = 0;
3137
3138 WARN_ON(!dst_w || !dst_h);
3139 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3140 crtc_state->scaler_state.scalers[scaler_id].mode;
3141 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3142 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3143 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3144 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3145 I915_WRITE(PLANE_POS(pipe, 0), 0);
3146 } else {
3147 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3148 }
3149
3150 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3151
3152 POSTING_READ(PLANE_SURF(pipe, 0));
3153 }
3154
3155 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3156 static int
3157 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3158 int x, int y, enum mode_set_atomic state)
3159 {
3160 struct drm_device *dev = crtc->dev;
3161 struct drm_i915_private *dev_priv = dev->dev_private;
3162
3163 if (dev_priv->display.disable_fbc)
3164 dev_priv->display.disable_fbc(dev);
3165
3166 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3167
3168 return 0;
3169 }
3170
3171 static void intel_complete_page_flips(struct drm_device *dev)
3172 {
3173 struct drm_crtc *crtc;
3174
3175 for_each_crtc(dev, crtc) {
3176 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3177 enum plane plane = intel_crtc->plane;
3178
3179 intel_prepare_page_flip(dev, plane);
3180 intel_finish_page_flip_plane(dev, plane);
3181 }
3182 }
3183
3184 static void intel_update_primary_planes(struct drm_device *dev)
3185 {
3186 struct drm_i915_private *dev_priv = dev->dev_private;
3187 struct drm_crtc *crtc;
3188
3189 for_each_crtc(dev, crtc) {
3190 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3191
3192 drm_modeset_lock(&crtc->mutex, NULL);
3193 /*
3194 * FIXME: Once we have proper support for primary planes (and
3195 * disabling them without disabling the entire crtc) allow again
3196 * a NULL crtc->primary->fb.
3197 */
3198 if (intel_crtc->active && crtc->primary->fb)
3199 dev_priv->display.update_primary_plane(crtc,
3200 crtc->primary->fb,
3201 crtc->x,
3202 crtc->y);
3203 drm_modeset_unlock(&crtc->mutex);
3204 }
3205 }
3206
3207 void intel_crtc_reset(struct intel_crtc *crtc)
3208 {
3209 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3210
3211 if (!crtc->active)
3212 return;
3213
3214 intel_crtc_disable_planes(&crtc->base);
3215 dev_priv->display.crtc_disable(&crtc->base);
3216 dev_priv->display.crtc_enable(&crtc->base);
3217 intel_crtc_enable_planes(&crtc->base);
3218 }
3219
3220 void intel_prepare_reset(struct drm_device *dev)
3221 {
3222 struct drm_i915_private *dev_priv = to_i915(dev);
3223 struct intel_crtc *crtc;
3224
3225 /* no reset support for gen2 */
3226 if (IS_GEN2(dev))
3227 return;
3228
3229 /* reset doesn't touch the display */
3230 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3231 return;
3232
3233 drm_modeset_lock_all(dev);
3234
3235 /*
3236 * Disabling the crtcs gracefully seems nicer. Also the
3237 * g33 docs say we should at least disable all the planes.
3238 */
3239 for_each_intel_crtc(dev, crtc) {
3240 if (!crtc->active)
3241 continue;
3242
3243 intel_crtc_disable_planes(&crtc->base);
3244 dev_priv->display.crtc_disable(&crtc->base);
3245 }
3246 }
3247
3248 void intel_finish_reset(struct drm_device *dev)
3249 {
3250 struct drm_i915_private *dev_priv = to_i915(dev);
3251
3252 /*
3253 * Flips in the rings will be nuked by the reset,
3254 * so complete all pending flips so that user space
3255 * will get its events and not get stuck.
3256 */
3257 intel_complete_page_flips(dev);
3258
3259 /* no reset support for gen2 */
3260 if (IS_GEN2(dev))
3261 return;
3262
3263 /* reset doesn't touch the display */
3264 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3265 /*
3266 * Flips in the rings have been nuked by the reset,
3267 * so update the base address of all primary
3268 * planes to the the last fb to make sure we're
3269 * showing the correct fb after a reset.
3270 */
3271 intel_update_primary_planes(dev);
3272 return;
3273 }
3274
3275 /*
3276 * The display has been reset as well,
3277 * so need a full re-initialization.
3278 */
3279 intel_runtime_pm_disable_interrupts(dev_priv);
3280 intel_runtime_pm_enable_interrupts(dev_priv);
3281
3282 intel_modeset_init_hw(dev);
3283
3284 spin_lock_irq(&dev_priv->irq_lock);
3285 if (dev_priv->display.hpd_irq_setup)
3286 dev_priv->display.hpd_irq_setup(dev);
3287 spin_unlock_irq(&dev_priv->irq_lock);
3288
3289 intel_modeset_setup_hw_state(dev, true);
3290
3291 intel_hpd_init(dev_priv);
3292
3293 drm_modeset_unlock_all(dev);
3294 }
3295
3296 static int
3297 intel_finish_fb(struct drm_framebuffer *old_fb)
3298 {
3299 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3300 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3301 bool was_interruptible = dev_priv->mm.interruptible;
3302 int ret;
3303
3304 /* Big Hammer, we also need to ensure that any pending
3305 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3306 * current scanout is retired before unpinning the old
3307 * framebuffer.
3308 *
3309 * This should only fail upon a hung GPU, in which case we
3310 * can safely continue.
3311 */
3312 dev_priv->mm.interruptible = false;
3313 ret = i915_gem_object_finish_gpu(obj);
3314 dev_priv->mm.interruptible = was_interruptible;
3315
3316 return ret;
3317 }
3318
3319 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3320 {
3321 struct drm_device *dev = crtc->dev;
3322 struct drm_i915_private *dev_priv = dev->dev_private;
3323 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3324 bool pending;
3325
3326 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3327 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3328 return false;
3329
3330 spin_lock_irq(&dev->event_lock);
3331 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3332 spin_unlock_irq(&dev->event_lock);
3333
3334 return pending;
3335 }
3336
3337 static void intel_update_pipe_size(struct intel_crtc *crtc)
3338 {
3339 struct drm_device *dev = crtc->base.dev;
3340 struct drm_i915_private *dev_priv = dev->dev_private;
3341 const struct drm_display_mode *adjusted_mode;
3342
3343 if (!i915.fastboot)
3344 return;
3345
3346 /*
3347 * Update pipe size and adjust fitter if needed: the reason for this is
3348 * that in compute_mode_changes we check the native mode (not the pfit
3349 * mode) to see if we can flip rather than do a full mode set. In the
3350 * fastboot case, we'll flip, but if we don't update the pipesrc and
3351 * pfit state, we'll end up with a big fb scanned out into the wrong
3352 * sized surface.
3353 *
3354 * To fix this properly, we need to hoist the checks up into
3355 * compute_mode_changes (or above), check the actual pfit state and
3356 * whether the platform allows pfit disable with pipe active, and only
3357 * then update the pipesrc and pfit state, even on the flip path.
3358 */
3359
3360 adjusted_mode = &crtc->config->base.adjusted_mode;
3361
3362 I915_WRITE(PIPESRC(crtc->pipe),
3363 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3364 (adjusted_mode->crtc_vdisplay - 1));
3365 if (!crtc->config->pch_pfit.enabled &&
3366 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3367 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3368 I915_WRITE(PF_CTL(crtc->pipe), 0);
3369 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3370 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3371 }
3372 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3373 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3374 }
3375
3376 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3377 {
3378 struct drm_device *dev = crtc->dev;
3379 struct drm_i915_private *dev_priv = dev->dev_private;
3380 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3381 int pipe = intel_crtc->pipe;
3382 u32 reg, temp;
3383
3384 /* enable normal train */
3385 reg = FDI_TX_CTL(pipe);
3386 temp = I915_READ(reg);
3387 if (IS_IVYBRIDGE(dev)) {
3388 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3389 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3390 } else {
3391 temp &= ~FDI_LINK_TRAIN_NONE;
3392 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3393 }
3394 I915_WRITE(reg, temp);
3395
3396 reg = FDI_RX_CTL(pipe);
3397 temp = I915_READ(reg);
3398 if (HAS_PCH_CPT(dev)) {
3399 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3400 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3401 } else {
3402 temp &= ~FDI_LINK_TRAIN_NONE;
3403 temp |= FDI_LINK_TRAIN_NONE;
3404 }
3405 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3406
3407 /* wait one idle pattern time */
3408 POSTING_READ(reg);
3409 udelay(1000);
3410
3411 /* IVB wants error correction enabled */
3412 if (IS_IVYBRIDGE(dev))
3413 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3414 FDI_FE_ERRC_ENABLE);
3415 }
3416
3417 /* The FDI link training functions for ILK/Ibexpeak. */
3418 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3419 {
3420 struct drm_device *dev = crtc->dev;
3421 struct drm_i915_private *dev_priv = dev->dev_private;
3422 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3423 int pipe = intel_crtc->pipe;
3424 u32 reg, temp, tries;
3425
3426 /* FDI needs bits from pipe first */
3427 assert_pipe_enabled(dev_priv, pipe);
3428
3429 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3430 for train result */
3431 reg = FDI_RX_IMR(pipe);
3432 temp = I915_READ(reg);
3433 temp &= ~FDI_RX_SYMBOL_LOCK;
3434 temp &= ~FDI_RX_BIT_LOCK;
3435 I915_WRITE(reg, temp);
3436 I915_READ(reg);
3437 udelay(150);
3438
3439 /* enable CPU FDI TX and PCH FDI RX */
3440 reg = FDI_TX_CTL(pipe);
3441 temp = I915_READ(reg);
3442 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3443 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3444 temp &= ~FDI_LINK_TRAIN_NONE;
3445 temp |= FDI_LINK_TRAIN_PATTERN_1;
3446 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3447
3448 reg = FDI_RX_CTL(pipe);
3449 temp = I915_READ(reg);
3450 temp &= ~FDI_LINK_TRAIN_NONE;
3451 temp |= FDI_LINK_TRAIN_PATTERN_1;
3452 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3453
3454 POSTING_READ(reg);
3455 udelay(150);
3456
3457 /* Ironlake workaround, enable clock pointer after FDI enable*/
3458 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3459 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3460 FDI_RX_PHASE_SYNC_POINTER_EN);
3461
3462 reg = FDI_RX_IIR(pipe);
3463 for (tries = 0; tries < 5; tries++) {
3464 temp = I915_READ(reg);
3465 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3466
3467 if ((temp & FDI_RX_BIT_LOCK)) {
3468 DRM_DEBUG_KMS("FDI train 1 done.\n");
3469 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3470 break;
3471 }
3472 }
3473 if (tries == 5)
3474 DRM_ERROR("FDI train 1 fail!\n");
3475
3476 /* Train 2 */
3477 reg = FDI_TX_CTL(pipe);
3478 temp = I915_READ(reg);
3479 temp &= ~FDI_LINK_TRAIN_NONE;
3480 temp |= FDI_LINK_TRAIN_PATTERN_2;
3481 I915_WRITE(reg, temp);
3482
3483 reg = FDI_RX_CTL(pipe);
3484 temp = I915_READ(reg);
3485 temp &= ~FDI_LINK_TRAIN_NONE;
3486 temp |= FDI_LINK_TRAIN_PATTERN_2;
3487 I915_WRITE(reg, temp);
3488
3489 POSTING_READ(reg);
3490 udelay(150);
3491
3492 reg = FDI_RX_IIR(pipe);
3493 for (tries = 0; tries < 5; tries++) {
3494 temp = I915_READ(reg);
3495 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3496
3497 if (temp & FDI_RX_SYMBOL_LOCK) {
3498 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3499 DRM_DEBUG_KMS("FDI train 2 done.\n");
3500 break;
3501 }
3502 }
3503 if (tries == 5)
3504 DRM_ERROR("FDI train 2 fail!\n");
3505
3506 DRM_DEBUG_KMS("FDI train done\n");
3507
3508 }
3509
3510 static const int snb_b_fdi_train_param[] = {
3511 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3512 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3513 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3514 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3515 };
3516
3517 /* The FDI link training functions for SNB/Cougarpoint. */
3518 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3519 {
3520 struct drm_device *dev = crtc->dev;
3521 struct drm_i915_private *dev_priv = dev->dev_private;
3522 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3523 int pipe = intel_crtc->pipe;
3524 u32 reg, temp, i, retry;
3525
3526 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3527 for train result */
3528 reg = FDI_RX_IMR(pipe);
3529 temp = I915_READ(reg);
3530 temp &= ~FDI_RX_SYMBOL_LOCK;
3531 temp &= ~FDI_RX_BIT_LOCK;
3532 I915_WRITE(reg, temp);
3533
3534 POSTING_READ(reg);
3535 udelay(150);
3536
3537 /* enable CPU FDI TX and PCH FDI RX */
3538 reg = FDI_TX_CTL(pipe);
3539 temp = I915_READ(reg);
3540 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3541 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3542 temp &= ~FDI_LINK_TRAIN_NONE;
3543 temp |= FDI_LINK_TRAIN_PATTERN_1;
3544 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3545 /* SNB-B */
3546 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3547 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3548
3549 I915_WRITE(FDI_RX_MISC(pipe),
3550 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3551
3552 reg = FDI_RX_CTL(pipe);
3553 temp = I915_READ(reg);
3554 if (HAS_PCH_CPT(dev)) {
3555 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3556 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3557 } else {
3558 temp &= ~FDI_LINK_TRAIN_NONE;
3559 temp |= FDI_LINK_TRAIN_PATTERN_1;
3560 }
3561 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3562
3563 POSTING_READ(reg);
3564 udelay(150);
3565
3566 for (i = 0; i < 4; i++) {
3567 reg = FDI_TX_CTL(pipe);
3568 temp = I915_READ(reg);
3569 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3570 temp |= snb_b_fdi_train_param[i];
3571 I915_WRITE(reg, temp);
3572
3573 POSTING_READ(reg);
3574 udelay(500);
3575
3576 for (retry = 0; retry < 5; retry++) {
3577 reg = FDI_RX_IIR(pipe);
3578 temp = I915_READ(reg);
3579 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3580 if (temp & FDI_RX_BIT_LOCK) {
3581 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3582 DRM_DEBUG_KMS("FDI train 1 done.\n");
3583 break;
3584 }
3585 udelay(50);
3586 }
3587 if (retry < 5)
3588 break;
3589 }
3590 if (i == 4)
3591 DRM_ERROR("FDI train 1 fail!\n");
3592
3593 /* Train 2 */
3594 reg = FDI_TX_CTL(pipe);
3595 temp = I915_READ(reg);
3596 temp &= ~FDI_LINK_TRAIN_NONE;
3597 temp |= FDI_LINK_TRAIN_PATTERN_2;
3598 if (IS_GEN6(dev)) {
3599 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3600 /* SNB-B */
3601 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3602 }
3603 I915_WRITE(reg, temp);
3604
3605 reg = FDI_RX_CTL(pipe);
3606 temp = I915_READ(reg);
3607 if (HAS_PCH_CPT(dev)) {
3608 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3609 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3610 } else {
3611 temp &= ~FDI_LINK_TRAIN_NONE;
3612 temp |= FDI_LINK_TRAIN_PATTERN_2;
3613 }
3614 I915_WRITE(reg, temp);
3615
3616 POSTING_READ(reg);
3617 udelay(150);
3618
3619 for (i = 0; i < 4; i++) {
3620 reg = FDI_TX_CTL(pipe);
3621 temp = I915_READ(reg);
3622 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3623 temp |= snb_b_fdi_train_param[i];
3624 I915_WRITE(reg, temp);
3625
3626 POSTING_READ(reg);
3627 udelay(500);
3628
3629 for (retry = 0; retry < 5; retry++) {
3630 reg = FDI_RX_IIR(pipe);
3631 temp = I915_READ(reg);
3632 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3633 if (temp & FDI_RX_SYMBOL_LOCK) {
3634 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3635 DRM_DEBUG_KMS("FDI train 2 done.\n");
3636 break;
3637 }
3638 udelay(50);
3639 }
3640 if (retry < 5)
3641 break;
3642 }
3643 if (i == 4)
3644 DRM_ERROR("FDI train 2 fail!\n");
3645
3646 DRM_DEBUG_KMS("FDI train done.\n");
3647 }
3648
3649 /* Manual link training for Ivy Bridge A0 parts */
3650 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3651 {
3652 struct drm_device *dev = crtc->dev;
3653 struct drm_i915_private *dev_priv = dev->dev_private;
3654 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3655 int pipe = intel_crtc->pipe;
3656 u32 reg, temp, i, j;
3657
3658 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3659 for train result */
3660 reg = FDI_RX_IMR(pipe);
3661 temp = I915_READ(reg);
3662 temp &= ~FDI_RX_SYMBOL_LOCK;
3663 temp &= ~FDI_RX_BIT_LOCK;
3664 I915_WRITE(reg, temp);
3665
3666 POSTING_READ(reg);
3667 udelay(150);
3668
3669 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3670 I915_READ(FDI_RX_IIR(pipe)));
3671
3672 /* Try each vswing and preemphasis setting twice before moving on */
3673 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3674 /* disable first in case we need to retry */
3675 reg = FDI_TX_CTL(pipe);
3676 temp = I915_READ(reg);
3677 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3678 temp &= ~FDI_TX_ENABLE;
3679 I915_WRITE(reg, temp);
3680
3681 reg = FDI_RX_CTL(pipe);
3682 temp = I915_READ(reg);
3683 temp &= ~FDI_LINK_TRAIN_AUTO;
3684 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3685 temp &= ~FDI_RX_ENABLE;
3686 I915_WRITE(reg, temp);
3687
3688 /* enable CPU FDI TX and PCH FDI RX */
3689 reg = FDI_TX_CTL(pipe);
3690 temp = I915_READ(reg);
3691 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3692 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3693 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3694 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3695 temp |= snb_b_fdi_train_param[j/2];
3696 temp |= FDI_COMPOSITE_SYNC;
3697 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3698
3699 I915_WRITE(FDI_RX_MISC(pipe),
3700 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3701
3702 reg = FDI_RX_CTL(pipe);
3703 temp = I915_READ(reg);
3704 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3705 temp |= FDI_COMPOSITE_SYNC;
3706 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3707
3708 POSTING_READ(reg);
3709 udelay(1); /* should be 0.5us */
3710
3711 for (i = 0; i < 4; i++) {
3712 reg = FDI_RX_IIR(pipe);
3713 temp = I915_READ(reg);
3714 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3715
3716 if (temp & FDI_RX_BIT_LOCK ||
3717 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3718 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3719 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3720 i);
3721 break;
3722 }
3723 udelay(1); /* should be 0.5us */
3724 }
3725 if (i == 4) {
3726 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3727 continue;
3728 }
3729
3730 /* Train 2 */
3731 reg = FDI_TX_CTL(pipe);
3732 temp = I915_READ(reg);
3733 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3734 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3735 I915_WRITE(reg, temp);
3736
3737 reg = FDI_RX_CTL(pipe);
3738 temp = I915_READ(reg);
3739 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3740 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3741 I915_WRITE(reg, temp);
3742
3743 POSTING_READ(reg);
3744 udelay(2); /* should be 1.5us */
3745
3746 for (i = 0; i < 4; i++) {
3747 reg = FDI_RX_IIR(pipe);
3748 temp = I915_READ(reg);
3749 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3750
3751 if (temp & FDI_RX_SYMBOL_LOCK ||
3752 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3753 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3754 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3755 i);
3756 goto train_done;
3757 }
3758 udelay(2); /* should be 1.5us */
3759 }
3760 if (i == 4)
3761 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3762 }
3763
3764 train_done:
3765 DRM_DEBUG_KMS("FDI train done.\n");
3766 }
3767
3768 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3769 {
3770 struct drm_device *dev = intel_crtc->base.dev;
3771 struct drm_i915_private *dev_priv = dev->dev_private;
3772 int pipe = intel_crtc->pipe;
3773 u32 reg, temp;
3774
3775
3776 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3777 reg = FDI_RX_CTL(pipe);
3778 temp = I915_READ(reg);
3779 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3780 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3781 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3782 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3783
3784 POSTING_READ(reg);
3785 udelay(200);
3786
3787 /* Switch from Rawclk to PCDclk */
3788 temp = I915_READ(reg);
3789 I915_WRITE(reg, temp | FDI_PCDCLK);
3790
3791 POSTING_READ(reg);
3792 udelay(200);
3793
3794 /* Enable CPU FDI TX PLL, always on for Ironlake */
3795 reg = FDI_TX_CTL(pipe);
3796 temp = I915_READ(reg);
3797 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3798 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3799
3800 POSTING_READ(reg);
3801 udelay(100);
3802 }
3803 }
3804
3805 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3806 {
3807 struct drm_device *dev = intel_crtc->base.dev;
3808 struct drm_i915_private *dev_priv = dev->dev_private;
3809 int pipe = intel_crtc->pipe;
3810 u32 reg, temp;
3811
3812 /* Switch from PCDclk to Rawclk */
3813 reg = FDI_RX_CTL(pipe);
3814 temp = I915_READ(reg);
3815 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3816
3817 /* Disable CPU FDI TX PLL */
3818 reg = FDI_TX_CTL(pipe);
3819 temp = I915_READ(reg);
3820 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3821
3822 POSTING_READ(reg);
3823 udelay(100);
3824
3825 reg = FDI_RX_CTL(pipe);
3826 temp = I915_READ(reg);
3827 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3828
3829 /* Wait for the clocks to turn off. */
3830 POSTING_READ(reg);
3831 udelay(100);
3832 }
3833
3834 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3835 {
3836 struct drm_device *dev = crtc->dev;
3837 struct drm_i915_private *dev_priv = dev->dev_private;
3838 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3839 int pipe = intel_crtc->pipe;
3840 u32 reg, temp;
3841
3842 /* disable CPU FDI tx and PCH FDI rx */
3843 reg = FDI_TX_CTL(pipe);
3844 temp = I915_READ(reg);
3845 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3846 POSTING_READ(reg);
3847
3848 reg = FDI_RX_CTL(pipe);
3849 temp = I915_READ(reg);
3850 temp &= ~(0x7 << 16);
3851 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3852 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3853
3854 POSTING_READ(reg);
3855 udelay(100);
3856
3857 /* Ironlake workaround, disable clock pointer after downing FDI */
3858 if (HAS_PCH_IBX(dev))
3859 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3860
3861 /* still set train pattern 1 */
3862 reg = FDI_TX_CTL(pipe);
3863 temp = I915_READ(reg);
3864 temp &= ~FDI_LINK_TRAIN_NONE;
3865 temp |= FDI_LINK_TRAIN_PATTERN_1;
3866 I915_WRITE(reg, temp);
3867
3868 reg = FDI_RX_CTL(pipe);
3869 temp = I915_READ(reg);
3870 if (HAS_PCH_CPT(dev)) {
3871 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3872 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3873 } else {
3874 temp &= ~FDI_LINK_TRAIN_NONE;
3875 temp |= FDI_LINK_TRAIN_PATTERN_1;
3876 }
3877 /* BPC in FDI rx is consistent with that in PIPECONF */
3878 temp &= ~(0x07 << 16);
3879 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3880 I915_WRITE(reg, temp);
3881
3882 POSTING_READ(reg);
3883 udelay(100);
3884 }
3885
3886 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3887 {
3888 struct intel_crtc *crtc;
3889
3890 /* Note that we don't need to be called with mode_config.lock here
3891 * as our list of CRTC objects is static for the lifetime of the
3892 * device and so cannot disappear as we iterate. Similarly, we can
3893 * happily treat the predicates as racy, atomic checks as userspace
3894 * cannot claim and pin a new fb without at least acquring the
3895 * struct_mutex and so serialising with us.
3896 */
3897 for_each_intel_crtc(dev, crtc) {
3898 if (atomic_read(&crtc->unpin_work_count) == 0)
3899 continue;
3900
3901 if (crtc->unpin_work)
3902 intel_wait_for_vblank(dev, crtc->pipe);
3903
3904 return true;
3905 }
3906
3907 return false;
3908 }
3909
3910 static void page_flip_completed(struct intel_crtc *intel_crtc)
3911 {
3912 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3913 struct intel_unpin_work *work = intel_crtc->unpin_work;
3914
3915 /* ensure that the unpin work is consistent wrt ->pending. */
3916 smp_rmb();
3917 intel_crtc->unpin_work = NULL;
3918
3919 if (work->event)
3920 drm_send_vblank_event(intel_crtc->base.dev,
3921 intel_crtc->pipe,
3922 work->event);
3923
3924 drm_crtc_vblank_put(&intel_crtc->base);
3925
3926 wake_up_all(&dev_priv->pending_flip_queue);
3927 queue_work(dev_priv->wq, &work->work);
3928
3929 trace_i915_flip_complete(intel_crtc->plane,
3930 work->pending_flip_obj);
3931 }
3932
3933 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3934 {
3935 struct drm_device *dev = crtc->dev;
3936 struct drm_i915_private *dev_priv = dev->dev_private;
3937
3938 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3939 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3940 !intel_crtc_has_pending_flip(crtc),
3941 60*HZ) == 0)) {
3942 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3943
3944 spin_lock_irq(&dev->event_lock);
3945 if (intel_crtc->unpin_work) {
3946 WARN_ONCE(1, "Removing stuck page flip\n");
3947 page_flip_completed(intel_crtc);
3948 }
3949 spin_unlock_irq(&dev->event_lock);
3950 }
3951
3952 if (crtc->primary->fb) {
3953 mutex_lock(&dev->struct_mutex);
3954 intel_finish_fb(crtc->primary->fb);
3955 mutex_unlock(&dev->struct_mutex);
3956 }
3957 }
3958
3959 /* Program iCLKIP clock to the desired frequency */
3960 static void lpt_program_iclkip(struct drm_crtc *crtc)
3961 {
3962 struct drm_device *dev = crtc->dev;
3963 struct drm_i915_private *dev_priv = dev->dev_private;
3964 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3965 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3966 u32 temp;
3967
3968 mutex_lock(&dev_priv->dpio_lock);
3969
3970 /* It is necessary to ungate the pixclk gate prior to programming
3971 * the divisors, and gate it back when it is done.
3972 */
3973 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3974
3975 /* Disable SSCCTL */
3976 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3977 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3978 SBI_SSCCTL_DISABLE,
3979 SBI_ICLK);
3980
3981 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3982 if (clock == 20000) {
3983 auxdiv = 1;
3984 divsel = 0x41;
3985 phaseinc = 0x20;
3986 } else {
3987 /* The iCLK virtual clock root frequency is in MHz,
3988 * but the adjusted_mode->crtc_clock in in KHz. To get the
3989 * divisors, it is necessary to divide one by another, so we
3990 * convert the virtual clock precision to KHz here for higher
3991 * precision.
3992 */
3993 u32 iclk_virtual_root_freq = 172800 * 1000;
3994 u32 iclk_pi_range = 64;
3995 u32 desired_divisor, msb_divisor_value, pi_value;
3996
3997 desired_divisor = (iclk_virtual_root_freq / clock);
3998 msb_divisor_value = desired_divisor / iclk_pi_range;
3999 pi_value = desired_divisor % iclk_pi_range;
4000
4001 auxdiv = 0;
4002 divsel = msb_divisor_value - 2;
4003 phaseinc = pi_value;
4004 }
4005
4006 /* This should not happen with any sane values */
4007 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4008 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4009 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4010 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4011
4012 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4013 clock,
4014 auxdiv,
4015 divsel,
4016 phasedir,
4017 phaseinc);
4018
4019 /* Program SSCDIVINTPHASE6 */
4020 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4021 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4022 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4023 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4024 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4025 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4026 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4027 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4028
4029 /* Program SSCAUXDIV */
4030 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4031 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4032 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4033 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4034
4035 /* Enable modulator and associated divider */
4036 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4037 temp &= ~SBI_SSCCTL_DISABLE;
4038 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4039
4040 /* Wait for initialization time */
4041 udelay(24);
4042
4043 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4044
4045 mutex_unlock(&dev_priv->dpio_lock);
4046 }
4047
4048 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4049 enum pipe pch_transcoder)
4050 {
4051 struct drm_device *dev = crtc->base.dev;
4052 struct drm_i915_private *dev_priv = dev->dev_private;
4053 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4054
4055 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4056 I915_READ(HTOTAL(cpu_transcoder)));
4057 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4058 I915_READ(HBLANK(cpu_transcoder)));
4059 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4060 I915_READ(HSYNC(cpu_transcoder)));
4061
4062 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4063 I915_READ(VTOTAL(cpu_transcoder)));
4064 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4065 I915_READ(VBLANK(cpu_transcoder)));
4066 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4067 I915_READ(VSYNC(cpu_transcoder)));
4068 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4069 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4070 }
4071
4072 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4073 {
4074 struct drm_i915_private *dev_priv = dev->dev_private;
4075 uint32_t temp;
4076
4077 temp = I915_READ(SOUTH_CHICKEN1);
4078 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4079 return;
4080
4081 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4082 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4083
4084 temp &= ~FDI_BC_BIFURCATION_SELECT;
4085 if (enable)
4086 temp |= FDI_BC_BIFURCATION_SELECT;
4087
4088 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4089 I915_WRITE(SOUTH_CHICKEN1, temp);
4090 POSTING_READ(SOUTH_CHICKEN1);
4091 }
4092
4093 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4094 {
4095 struct drm_device *dev = intel_crtc->base.dev;
4096
4097 switch (intel_crtc->pipe) {
4098 case PIPE_A:
4099 break;
4100 case PIPE_B:
4101 if (intel_crtc->config->fdi_lanes > 2)
4102 cpt_set_fdi_bc_bifurcation(dev, false);
4103 else
4104 cpt_set_fdi_bc_bifurcation(dev, true);
4105
4106 break;
4107 case PIPE_C:
4108 cpt_set_fdi_bc_bifurcation(dev, true);
4109
4110 break;
4111 default:
4112 BUG();
4113 }
4114 }
4115
4116 /*
4117 * Enable PCH resources required for PCH ports:
4118 * - PCH PLLs
4119 * - FDI training & RX/TX
4120 * - update transcoder timings
4121 * - DP transcoding bits
4122 * - transcoder
4123 */
4124 static void ironlake_pch_enable(struct drm_crtc *crtc)
4125 {
4126 struct drm_device *dev = crtc->dev;
4127 struct drm_i915_private *dev_priv = dev->dev_private;
4128 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4129 int pipe = intel_crtc->pipe;
4130 u32 reg, temp;
4131
4132 assert_pch_transcoder_disabled(dev_priv, pipe);
4133
4134 if (IS_IVYBRIDGE(dev))
4135 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4136
4137 /* Write the TU size bits before fdi link training, so that error
4138 * detection works. */
4139 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4140 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4141
4142 /* For PCH output, training FDI link */
4143 dev_priv->display.fdi_link_train(crtc);
4144
4145 /* We need to program the right clock selection before writing the pixel
4146 * mutliplier into the DPLL. */
4147 if (HAS_PCH_CPT(dev)) {
4148 u32 sel;
4149
4150 temp = I915_READ(PCH_DPLL_SEL);
4151 temp |= TRANS_DPLL_ENABLE(pipe);
4152 sel = TRANS_DPLLB_SEL(pipe);
4153 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4154 temp |= sel;
4155 else
4156 temp &= ~sel;
4157 I915_WRITE(PCH_DPLL_SEL, temp);
4158 }
4159
4160 /* XXX: pch pll's can be enabled any time before we enable the PCH
4161 * transcoder, and we actually should do this to not upset any PCH
4162 * transcoder that already use the clock when we share it.
4163 *
4164 * Note that enable_shared_dpll tries to do the right thing, but
4165 * get_shared_dpll unconditionally resets the pll - we need that to have
4166 * the right LVDS enable sequence. */
4167 intel_enable_shared_dpll(intel_crtc);
4168
4169 /* set transcoder timing, panel must allow it */
4170 assert_panel_unlocked(dev_priv, pipe);
4171 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4172
4173 intel_fdi_normal_train(crtc);
4174
4175 /* For PCH DP, enable TRANS_DP_CTL */
4176 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4177 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4178 reg = TRANS_DP_CTL(pipe);
4179 temp = I915_READ(reg);
4180 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4181 TRANS_DP_SYNC_MASK |
4182 TRANS_DP_BPC_MASK);
4183 temp |= (TRANS_DP_OUTPUT_ENABLE |
4184 TRANS_DP_ENH_FRAMING);
4185 temp |= bpc << 9; /* same format but at 11:9 */
4186
4187 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4188 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4189 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4190 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4191
4192 switch (intel_trans_dp_port_sel(crtc)) {
4193 case PCH_DP_B:
4194 temp |= TRANS_DP_PORT_SEL_B;
4195 break;
4196 case PCH_DP_C:
4197 temp |= TRANS_DP_PORT_SEL_C;
4198 break;
4199 case PCH_DP_D:
4200 temp |= TRANS_DP_PORT_SEL_D;
4201 break;
4202 default:
4203 BUG();
4204 }
4205
4206 I915_WRITE(reg, temp);
4207 }
4208
4209 ironlake_enable_pch_transcoder(dev_priv, pipe);
4210 }
4211
4212 static void lpt_pch_enable(struct drm_crtc *crtc)
4213 {
4214 struct drm_device *dev = crtc->dev;
4215 struct drm_i915_private *dev_priv = dev->dev_private;
4216 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4217 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4218
4219 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4220
4221 lpt_program_iclkip(crtc);
4222
4223 /* Set transcoder timing. */
4224 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4225
4226 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4227 }
4228
4229 void intel_put_shared_dpll(struct intel_crtc *crtc)
4230 {
4231 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4232
4233 if (pll == NULL)
4234 return;
4235
4236 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
4237 WARN(1, "bad %s crtc mask\n", pll->name);
4238 return;
4239 }
4240
4241 pll->config.crtc_mask &= ~(1 << crtc->pipe);
4242 if (pll->config.crtc_mask == 0) {
4243 WARN_ON(pll->on);
4244 WARN_ON(pll->active);
4245 }
4246
4247 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
4248 }
4249
4250 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4251 struct intel_crtc_state *crtc_state)
4252 {
4253 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4254 struct intel_shared_dpll *pll;
4255 enum intel_dpll_id i;
4256
4257 if (HAS_PCH_IBX(dev_priv->dev)) {
4258 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4259 i = (enum intel_dpll_id) crtc->pipe;
4260 pll = &dev_priv->shared_dplls[i];
4261
4262 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4263 crtc->base.base.id, pll->name);
4264
4265 WARN_ON(pll->new_config->crtc_mask);
4266
4267 goto found;
4268 }
4269
4270 if (IS_BROXTON(dev_priv->dev)) {
4271 /* PLL is attached to port in bxt */
4272 struct intel_encoder *encoder;
4273 struct intel_digital_port *intel_dig_port;
4274
4275 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4276 if (WARN_ON(!encoder))
4277 return NULL;
4278
4279 intel_dig_port = enc_to_dig_port(&encoder->base);
4280 /* 1:1 mapping between ports and PLLs */
4281 i = (enum intel_dpll_id)intel_dig_port->port;
4282 pll = &dev_priv->shared_dplls[i];
4283 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4284 crtc->base.base.id, pll->name);
4285 WARN_ON(pll->new_config->crtc_mask);
4286
4287 goto found;
4288 }
4289
4290 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4291 pll = &dev_priv->shared_dplls[i];
4292
4293 /* Only want to check enabled timings first */
4294 if (pll->new_config->crtc_mask == 0)
4295 continue;
4296
4297 if (memcmp(&crtc_state->dpll_hw_state,
4298 &pll->new_config->hw_state,
4299 sizeof(pll->new_config->hw_state)) == 0) {
4300 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4301 crtc->base.base.id, pll->name,
4302 pll->new_config->crtc_mask,
4303 pll->active);
4304 goto found;
4305 }
4306 }
4307
4308 /* Ok no matching timings, maybe there's a free one? */
4309 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4310 pll = &dev_priv->shared_dplls[i];
4311 if (pll->new_config->crtc_mask == 0) {
4312 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4313 crtc->base.base.id, pll->name);
4314 goto found;
4315 }
4316 }
4317
4318 return NULL;
4319
4320 found:
4321 if (pll->new_config->crtc_mask == 0)
4322 pll->new_config->hw_state = crtc_state->dpll_hw_state;
4323
4324 crtc_state->shared_dpll = i;
4325 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4326 pipe_name(crtc->pipe));
4327
4328 pll->new_config->crtc_mask |= 1 << crtc->pipe;
4329
4330 return pll;
4331 }
4332
4333 /**
4334 * intel_shared_dpll_start_config - start a new PLL staged config
4335 * @dev_priv: DRM device
4336 * @clear_pipes: mask of pipes that will have their PLLs freed
4337 *
4338 * Starts a new PLL staged config, copying the current config but
4339 * releasing the references of pipes specified in clear_pipes.
4340 */
4341 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4342 unsigned clear_pipes)
4343 {
4344 struct intel_shared_dpll *pll;
4345 enum intel_dpll_id i;
4346
4347 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4348 pll = &dev_priv->shared_dplls[i];
4349
4350 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4351 GFP_KERNEL);
4352 if (!pll->new_config)
4353 goto cleanup;
4354
4355 pll->new_config->crtc_mask &= ~clear_pipes;
4356 }
4357
4358 return 0;
4359
4360 cleanup:
4361 while (--i >= 0) {
4362 pll = &dev_priv->shared_dplls[i];
4363 kfree(pll->new_config);
4364 pll->new_config = NULL;
4365 }
4366
4367 return -ENOMEM;
4368 }
4369
4370 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4371 {
4372 struct intel_shared_dpll *pll;
4373 enum intel_dpll_id i;
4374
4375 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4376 pll = &dev_priv->shared_dplls[i];
4377
4378 WARN_ON(pll->new_config == &pll->config);
4379
4380 pll->config = *pll->new_config;
4381 kfree(pll->new_config);
4382 pll->new_config = NULL;
4383 }
4384 }
4385
4386 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4387 {
4388 struct intel_shared_dpll *pll;
4389 enum intel_dpll_id i;
4390
4391 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4392 pll = &dev_priv->shared_dplls[i];
4393
4394 WARN_ON(pll->new_config == &pll->config);
4395
4396 kfree(pll->new_config);
4397 pll->new_config = NULL;
4398 }
4399 }
4400
4401 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4402 {
4403 struct drm_i915_private *dev_priv = dev->dev_private;
4404 int dslreg = PIPEDSL(pipe);
4405 u32 temp;
4406
4407 temp = I915_READ(dslreg);
4408 udelay(500);
4409 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4410 if (wait_for(I915_READ(dslreg) != temp, 5))
4411 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4412 }
4413 }
4414
4415 /**
4416 * skl_update_scaler_users - Stages update to crtc's scaler state
4417 * @intel_crtc: crtc
4418 * @crtc_state: crtc_state
4419 * @plane: plane (NULL indicates crtc is requesting update)
4420 * @plane_state: plane's state
4421 * @force_detach: request unconditional detachment of scaler
4422 *
4423 * This function updates scaler state for requested plane or crtc.
4424 * To request scaler usage update for a plane, caller shall pass plane pointer.
4425 * To request scaler usage update for crtc, caller shall pass plane pointer
4426 * as NULL.
4427 *
4428 * Return
4429 * 0 - scaler_usage updated successfully
4430 * error - requested scaling cannot be supported or other error condition
4431 */
4432 int
4433 skl_update_scaler_users(
4434 struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state,
4435 struct intel_plane *intel_plane, struct intel_plane_state *plane_state,
4436 int force_detach)
4437 {
4438 int need_scaling;
4439 int idx;
4440 int src_w, src_h, dst_w, dst_h;
4441 int *scaler_id;
4442 struct drm_framebuffer *fb;
4443 struct intel_crtc_scaler_state *scaler_state;
4444 unsigned int rotation;
4445
4446 if (!intel_crtc || !crtc_state)
4447 return 0;
4448
4449 scaler_state = &crtc_state->scaler_state;
4450
4451 idx = intel_plane ? drm_plane_index(&intel_plane->base) : SKL_CRTC_INDEX;
4452 fb = intel_plane ? plane_state->base.fb : NULL;
4453
4454 if (intel_plane) {
4455 src_w = drm_rect_width(&plane_state->src) >> 16;
4456 src_h = drm_rect_height(&plane_state->src) >> 16;
4457 dst_w = drm_rect_width(&plane_state->dst);
4458 dst_h = drm_rect_height(&plane_state->dst);
4459 scaler_id = &plane_state->scaler_id;
4460 rotation = plane_state->base.rotation;
4461 } else {
4462 struct drm_display_mode *adjusted_mode =
4463 &crtc_state->base.adjusted_mode;
4464 src_w = crtc_state->pipe_src_w;
4465 src_h = crtc_state->pipe_src_h;
4466 dst_w = adjusted_mode->hdisplay;
4467 dst_h = adjusted_mode->vdisplay;
4468 scaler_id = &scaler_state->scaler_id;
4469 rotation = DRM_ROTATE_0;
4470 }
4471
4472 need_scaling = intel_rotation_90_or_270(rotation) ?
4473 (src_h != dst_w || src_w != dst_h):
4474 (src_w != dst_w || src_h != dst_h);
4475
4476 /*
4477 * if plane is being disabled or scaler is no more required or force detach
4478 * - free scaler binded to this plane/crtc
4479 * - in order to do this, update crtc->scaler_usage
4480 *
4481 * Here scaler state in crtc_state is set free so that
4482 * scaler can be assigned to other user. Actual register
4483 * update to free the scaler is done in plane/panel-fit programming.
4484 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4485 */
4486 if (force_detach || !need_scaling || (intel_plane &&
4487 (!fb || !plane_state->visible))) {
4488 if (*scaler_id >= 0) {
4489 scaler_state->scaler_users &= ~(1 << idx);
4490 scaler_state->scalers[*scaler_id].in_use = 0;
4491
4492 DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d "
4493 "crtc_state = %p scaler_users = 0x%x\n",
4494 intel_crtc->pipe, *scaler_id, intel_plane ? "PLANE" : "CRTC",
4495 intel_plane ? intel_plane->base.base.id :
4496 intel_crtc->base.base.id, crtc_state,
4497 scaler_state->scaler_users);
4498 *scaler_id = -1;
4499 }
4500 return 0;
4501 }
4502
4503 /* range checks */
4504 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4505 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4506
4507 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4508 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4509 DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u "
4510 "size is out of scaler range\n",
4511 intel_plane ? "PLANE" : "CRTC",
4512 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4513 intel_crtc->pipe, idx, src_w, src_h, dst_w, dst_h);
4514 return -EINVAL;
4515 }
4516
4517 /* check colorkey */
4518 if (intel_plane && intel_plane->ckey.flags != I915_SET_COLORKEY_NONE) {
4519 DRM_DEBUG_KMS("PLANE:%d scaling with color key not allowed",
4520 intel_plane->base.base.id);
4521 return -EINVAL;
4522 }
4523
4524 /* Check src format */
4525 if (intel_plane) {
4526 switch (fb->pixel_format) {
4527 case DRM_FORMAT_RGB565:
4528 case DRM_FORMAT_XBGR8888:
4529 case DRM_FORMAT_XRGB8888:
4530 case DRM_FORMAT_ABGR8888:
4531 case DRM_FORMAT_ARGB8888:
4532 case DRM_FORMAT_XRGB2101010:
4533 case DRM_FORMAT_ARGB2101010:
4534 case DRM_FORMAT_XBGR2101010:
4535 case DRM_FORMAT_ABGR2101010:
4536 case DRM_FORMAT_YUYV:
4537 case DRM_FORMAT_YVYU:
4538 case DRM_FORMAT_UYVY:
4539 case DRM_FORMAT_VYUY:
4540 break;
4541 default:
4542 DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n",
4543 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4544 return -EINVAL;
4545 }
4546 }
4547
4548 /* mark this plane as a scaler user in crtc_state */
4549 scaler_state->scaler_users |= (1 << idx);
4550 DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u "
4551 "crtc_state = %p scaler_users = 0x%x\n",
4552 intel_plane ? "PLANE" : "CRTC",
4553 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4554 src_w, src_h, dst_w, dst_h, crtc_state, scaler_state->scaler_users);
4555 return 0;
4556 }
4557
4558 static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
4559 {
4560 struct drm_device *dev = crtc->base.dev;
4561 struct drm_i915_private *dev_priv = dev->dev_private;
4562 int pipe = crtc->pipe;
4563 struct intel_crtc_scaler_state *scaler_state =
4564 &crtc->config->scaler_state;
4565
4566 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4567
4568 /* To update pfit, first update scaler state */
4569 skl_update_scaler_users(crtc, crtc->config, NULL, NULL, !enable);
4570 intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4571 skl_detach_scalers(crtc);
4572 if (!enable)
4573 return;
4574
4575 if (crtc->config->pch_pfit.enabled) {
4576 int id;
4577
4578 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4579 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4580 return;
4581 }
4582
4583 id = scaler_state->scaler_id;
4584 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4585 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4586 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4587 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4588
4589 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4590 }
4591 }
4592
4593 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4594 {
4595 struct drm_device *dev = crtc->base.dev;
4596 struct drm_i915_private *dev_priv = dev->dev_private;
4597 int pipe = crtc->pipe;
4598
4599 if (crtc->config->pch_pfit.enabled) {
4600 /* Force use of hard-coded filter coefficients
4601 * as some pre-programmed values are broken,
4602 * e.g. x201.
4603 */
4604 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4605 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4606 PF_PIPE_SEL_IVB(pipe));
4607 else
4608 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4609 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4610 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4611 }
4612 }
4613
4614 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4615 {
4616 struct drm_device *dev = crtc->dev;
4617 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4618 struct drm_plane *plane;
4619 struct intel_plane *intel_plane;
4620
4621 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4622 intel_plane = to_intel_plane(plane);
4623 if (intel_plane->pipe == pipe)
4624 intel_plane_restore(&intel_plane->base);
4625 }
4626 }
4627
4628 void hsw_enable_ips(struct intel_crtc *crtc)
4629 {
4630 struct drm_device *dev = crtc->base.dev;
4631 struct drm_i915_private *dev_priv = dev->dev_private;
4632
4633 if (!crtc->config->ips_enabled)
4634 return;
4635
4636 /* We can only enable IPS after we enable a plane and wait for a vblank */
4637 intel_wait_for_vblank(dev, crtc->pipe);
4638
4639 assert_plane_enabled(dev_priv, crtc->plane);
4640 if (IS_BROADWELL(dev)) {
4641 mutex_lock(&dev_priv->rps.hw_lock);
4642 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4643 mutex_unlock(&dev_priv->rps.hw_lock);
4644 /* Quoting Art Runyan: "its not safe to expect any particular
4645 * value in IPS_CTL bit 31 after enabling IPS through the
4646 * mailbox." Moreover, the mailbox may return a bogus state,
4647 * so we need to just enable it and continue on.
4648 */
4649 } else {
4650 I915_WRITE(IPS_CTL, IPS_ENABLE);
4651 /* The bit only becomes 1 in the next vblank, so this wait here
4652 * is essentially intel_wait_for_vblank. If we don't have this
4653 * and don't wait for vblanks until the end of crtc_enable, then
4654 * the HW state readout code will complain that the expected
4655 * IPS_CTL value is not the one we read. */
4656 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4657 DRM_ERROR("Timed out waiting for IPS enable\n");
4658 }
4659 }
4660
4661 void hsw_disable_ips(struct intel_crtc *crtc)
4662 {
4663 struct drm_device *dev = crtc->base.dev;
4664 struct drm_i915_private *dev_priv = dev->dev_private;
4665
4666 if (!crtc->config->ips_enabled)
4667 return;
4668
4669 assert_plane_enabled(dev_priv, crtc->plane);
4670 if (IS_BROADWELL(dev)) {
4671 mutex_lock(&dev_priv->rps.hw_lock);
4672 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4673 mutex_unlock(&dev_priv->rps.hw_lock);
4674 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4675 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4676 DRM_ERROR("Timed out waiting for IPS disable\n");
4677 } else {
4678 I915_WRITE(IPS_CTL, 0);
4679 POSTING_READ(IPS_CTL);
4680 }
4681
4682 /* We need to wait for a vblank before we can disable the plane. */
4683 intel_wait_for_vblank(dev, crtc->pipe);
4684 }
4685
4686 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4687 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4688 {
4689 struct drm_device *dev = crtc->dev;
4690 struct drm_i915_private *dev_priv = dev->dev_private;
4691 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4692 enum pipe pipe = intel_crtc->pipe;
4693 int palreg = PALETTE(pipe);
4694 int i;
4695 bool reenable_ips = false;
4696
4697 /* The clocks have to be on to load the palette. */
4698 if (!crtc->state->enable || !intel_crtc->active)
4699 return;
4700
4701 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4702 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4703 assert_dsi_pll_enabled(dev_priv);
4704 else
4705 assert_pll_enabled(dev_priv, pipe);
4706 }
4707
4708 /* use legacy palette for Ironlake */
4709 if (!HAS_GMCH_DISPLAY(dev))
4710 palreg = LGC_PALETTE(pipe);
4711
4712 /* Workaround : Do not read or write the pipe palette/gamma data while
4713 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4714 */
4715 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4716 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4717 GAMMA_MODE_MODE_SPLIT)) {
4718 hsw_disable_ips(intel_crtc);
4719 reenable_ips = true;
4720 }
4721
4722 for (i = 0; i < 256; i++) {
4723 I915_WRITE(palreg + 4 * i,
4724 (intel_crtc->lut_r[i] << 16) |
4725 (intel_crtc->lut_g[i] << 8) |
4726 intel_crtc->lut_b[i]);
4727 }
4728
4729 if (reenable_ips)
4730 hsw_enable_ips(intel_crtc);
4731 }
4732
4733 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4734 {
4735 if (intel_crtc->overlay) {
4736 struct drm_device *dev = intel_crtc->base.dev;
4737 struct drm_i915_private *dev_priv = dev->dev_private;
4738
4739 mutex_lock(&dev->struct_mutex);
4740 dev_priv->mm.interruptible = false;
4741 (void) intel_overlay_switch_off(intel_crtc->overlay);
4742 dev_priv->mm.interruptible = true;
4743 mutex_unlock(&dev->struct_mutex);
4744 }
4745
4746 /* Let userspace switch the overlay on again. In most cases userspace
4747 * has to recompute where to put it anyway.
4748 */
4749 }
4750
4751 /**
4752 * intel_post_enable_primary - Perform operations after enabling primary plane
4753 * @crtc: the CRTC whose primary plane was just enabled
4754 *
4755 * Performs potentially sleeping operations that must be done after the primary
4756 * plane is enabled, such as updating FBC and IPS. Note that this may be
4757 * called due to an explicit primary plane update, or due to an implicit
4758 * re-enable that is caused when a sprite plane is updated to no longer
4759 * completely hide the primary plane.
4760 */
4761 static void
4762 intel_post_enable_primary(struct drm_crtc *crtc)
4763 {
4764 struct drm_device *dev = crtc->dev;
4765 struct drm_i915_private *dev_priv = dev->dev_private;
4766 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4767 int pipe = intel_crtc->pipe;
4768
4769 /*
4770 * BDW signals flip done immediately if the plane
4771 * is disabled, even if the plane enable is already
4772 * armed to occur at the next vblank :(
4773 */
4774 if (IS_BROADWELL(dev))
4775 intel_wait_for_vblank(dev, pipe);
4776
4777 /*
4778 * FIXME IPS should be fine as long as one plane is
4779 * enabled, but in practice it seems to have problems
4780 * when going from primary only to sprite only and vice
4781 * versa.
4782 */
4783 hsw_enable_ips(intel_crtc);
4784
4785 mutex_lock(&dev->struct_mutex);
4786 intel_fbc_update(dev);
4787 mutex_unlock(&dev->struct_mutex);
4788
4789 /*
4790 * Gen2 reports pipe underruns whenever all planes are disabled.
4791 * So don't enable underrun reporting before at least some planes
4792 * are enabled.
4793 * FIXME: Need to fix the logic to work when we turn off all planes
4794 * but leave the pipe running.
4795 */
4796 if (IS_GEN2(dev))
4797 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4798
4799 /* Underruns don't raise interrupts, so check manually. */
4800 if (HAS_GMCH_DISPLAY(dev))
4801 i9xx_check_fifo_underruns(dev_priv);
4802 }
4803
4804 /**
4805 * intel_pre_disable_primary - Perform operations before disabling primary plane
4806 * @crtc: the CRTC whose primary plane is to be disabled
4807 *
4808 * Performs potentially sleeping operations that must be done before the
4809 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4810 * be called due to an explicit primary plane update, or due to an implicit
4811 * disable that is caused when a sprite plane completely hides the primary
4812 * plane.
4813 */
4814 static void
4815 intel_pre_disable_primary(struct drm_crtc *crtc)
4816 {
4817 struct drm_device *dev = crtc->dev;
4818 struct drm_i915_private *dev_priv = dev->dev_private;
4819 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4820 int pipe = intel_crtc->pipe;
4821
4822 /*
4823 * Gen2 reports pipe underruns whenever all planes are disabled.
4824 * So diasble underrun reporting before all the planes get disabled.
4825 * FIXME: Need to fix the logic to work when we turn off all planes
4826 * but leave the pipe running.
4827 */
4828 if (IS_GEN2(dev))
4829 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4830
4831 /*
4832 * Vblank time updates from the shadow to live plane control register
4833 * are blocked if the memory self-refresh mode is active at that
4834 * moment. So to make sure the plane gets truly disabled, disable
4835 * first the self-refresh mode. The self-refresh enable bit in turn
4836 * will be checked/applied by the HW only at the next frame start
4837 * event which is after the vblank start event, so we need to have a
4838 * wait-for-vblank between disabling the plane and the pipe.
4839 */
4840 if (HAS_GMCH_DISPLAY(dev))
4841 intel_set_memory_cxsr(dev_priv, false);
4842
4843 mutex_lock(&dev->struct_mutex);
4844 if (dev_priv->fbc.crtc == intel_crtc)
4845 intel_fbc_disable(dev);
4846 mutex_unlock(&dev->struct_mutex);
4847
4848 /*
4849 * FIXME IPS should be fine as long as one plane is
4850 * enabled, but in practice it seems to have problems
4851 * when going from primary only to sprite only and vice
4852 * versa.
4853 */
4854 hsw_disable_ips(intel_crtc);
4855 }
4856
4857 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4858 {
4859 intel_enable_primary_hw_plane(crtc->primary, crtc);
4860 intel_enable_sprite_planes(crtc);
4861 intel_crtc_update_cursor(crtc, true);
4862
4863 intel_post_enable_primary(crtc);
4864 }
4865
4866 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4867 {
4868 struct drm_device *dev = crtc->dev;
4869 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4870 struct intel_plane *intel_plane;
4871 int pipe = intel_crtc->pipe;
4872
4873 intel_crtc_wait_for_pending_flips(crtc);
4874
4875 intel_pre_disable_primary(crtc);
4876
4877 intel_crtc_dpms_overlay_disable(intel_crtc);
4878 for_each_intel_plane(dev, intel_plane) {
4879 if (intel_plane->pipe == pipe) {
4880 struct drm_crtc *from = intel_plane->base.crtc;
4881
4882 intel_plane->disable_plane(&intel_plane->base,
4883 from ?: crtc, true);
4884 }
4885 }
4886
4887 /*
4888 * FIXME: Once we grow proper nuclear flip support out of this we need
4889 * to compute the mask of flip planes precisely. For the time being
4890 * consider this a flip to a NULL plane.
4891 */
4892 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4893 }
4894
4895 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4896 {
4897 struct drm_device *dev = crtc->dev;
4898 struct drm_i915_private *dev_priv = dev->dev_private;
4899 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4900 struct intel_encoder *encoder;
4901 int pipe = intel_crtc->pipe;
4902
4903 WARN_ON(!crtc->state->enable);
4904
4905 if (intel_crtc->active)
4906 return;
4907
4908 if (intel_crtc->config->has_pch_encoder)
4909 intel_prepare_shared_dpll(intel_crtc);
4910
4911 if (intel_crtc->config->has_dp_encoder)
4912 intel_dp_set_m_n(intel_crtc, M1_N1);
4913
4914 intel_set_pipe_timings(intel_crtc);
4915
4916 if (intel_crtc->config->has_pch_encoder) {
4917 intel_cpu_transcoder_set_m_n(intel_crtc,
4918 &intel_crtc->config->fdi_m_n, NULL);
4919 }
4920
4921 ironlake_set_pipeconf(crtc);
4922
4923 intel_crtc->active = true;
4924
4925 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4926 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4927
4928 for_each_encoder_on_crtc(dev, crtc, encoder)
4929 if (encoder->pre_enable)
4930 encoder->pre_enable(encoder);
4931
4932 if (intel_crtc->config->has_pch_encoder) {
4933 /* Note: FDI PLL enabling _must_ be done before we enable the
4934 * cpu pipes, hence this is separate from all the other fdi/pch
4935 * enabling. */
4936 ironlake_fdi_pll_enable(intel_crtc);
4937 } else {
4938 assert_fdi_tx_disabled(dev_priv, pipe);
4939 assert_fdi_rx_disabled(dev_priv, pipe);
4940 }
4941
4942 ironlake_pfit_enable(intel_crtc);
4943
4944 /*
4945 * On ILK+ LUT must be loaded before the pipe is running but with
4946 * clocks enabled
4947 */
4948 intel_crtc_load_lut(crtc);
4949
4950 intel_update_watermarks(crtc);
4951 intel_enable_pipe(intel_crtc);
4952
4953 if (intel_crtc->config->has_pch_encoder)
4954 ironlake_pch_enable(crtc);
4955
4956 assert_vblank_disabled(crtc);
4957 drm_crtc_vblank_on(crtc);
4958
4959 for_each_encoder_on_crtc(dev, crtc, encoder)
4960 encoder->enable(encoder);
4961
4962 if (HAS_PCH_CPT(dev))
4963 cpt_verify_modeset(dev, intel_crtc->pipe);
4964 }
4965
4966 /* IPS only exists on ULT machines and is tied to pipe A. */
4967 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4968 {
4969 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4970 }
4971
4972 /*
4973 * This implements the workaround described in the "notes" section of the mode
4974 * set sequence documentation. When going from no pipes or single pipe to
4975 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4976 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4977 */
4978 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4979 {
4980 struct drm_device *dev = crtc->base.dev;
4981 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4982
4983 /* We want to get the other_active_crtc only if there's only 1 other
4984 * active crtc. */
4985 for_each_intel_crtc(dev, crtc_it) {
4986 if (!crtc_it->active || crtc_it == crtc)
4987 continue;
4988
4989 if (other_active_crtc)
4990 return;
4991
4992 other_active_crtc = crtc_it;
4993 }
4994 if (!other_active_crtc)
4995 return;
4996
4997 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4998 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4999 }
5000
5001 static void haswell_crtc_enable(struct drm_crtc *crtc)
5002 {
5003 struct drm_device *dev = crtc->dev;
5004 struct drm_i915_private *dev_priv = dev->dev_private;
5005 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5006 struct intel_encoder *encoder;
5007 int pipe = intel_crtc->pipe;
5008
5009 WARN_ON(!crtc->state->enable);
5010
5011 if (intel_crtc->active)
5012 return;
5013
5014 if (intel_crtc_to_shared_dpll(intel_crtc))
5015 intel_enable_shared_dpll(intel_crtc);
5016
5017 if (intel_crtc->config->has_dp_encoder)
5018 intel_dp_set_m_n(intel_crtc, M1_N1);
5019
5020 intel_set_pipe_timings(intel_crtc);
5021
5022 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
5023 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
5024 intel_crtc->config->pixel_multiplier - 1);
5025 }
5026
5027 if (intel_crtc->config->has_pch_encoder) {
5028 intel_cpu_transcoder_set_m_n(intel_crtc,
5029 &intel_crtc->config->fdi_m_n, NULL);
5030 }
5031
5032 haswell_set_pipeconf(crtc);
5033
5034 intel_set_pipe_csc(crtc);
5035
5036 intel_crtc->active = true;
5037
5038 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5039 for_each_encoder_on_crtc(dev, crtc, encoder)
5040 if (encoder->pre_enable)
5041 encoder->pre_enable(encoder);
5042
5043 if (intel_crtc->config->has_pch_encoder) {
5044 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5045 true);
5046 dev_priv->display.fdi_link_train(crtc);
5047 }
5048
5049 intel_ddi_enable_pipe_clock(intel_crtc);
5050
5051 if (INTEL_INFO(dev)->gen == 9)
5052 skylake_pfit_update(intel_crtc, 1);
5053 else if (INTEL_INFO(dev)->gen < 9)
5054 ironlake_pfit_enable(intel_crtc);
5055 else
5056 MISSING_CASE(INTEL_INFO(dev)->gen);
5057
5058 /*
5059 * On ILK+ LUT must be loaded before the pipe is running but with
5060 * clocks enabled
5061 */
5062 intel_crtc_load_lut(crtc);
5063
5064 intel_ddi_set_pipe_settings(crtc);
5065 intel_ddi_enable_transcoder_func(crtc);
5066
5067 intel_update_watermarks(crtc);
5068 intel_enable_pipe(intel_crtc);
5069
5070 if (intel_crtc->config->has_pch_encoder)
5071 lpt_pch_enable(crtc);
5072
5073 if (intel_crtc->config->dp_encoder_is_mst)
5074 intel_ddi_set_vc_payload_alloc(crtc, true);
5075
5076 assert_vblank_disabled(crtc);
5077 drm_crtc_vblank_on(crtc);
5078
5079 for_each_encoder_on_crtc(dev, crtc, encoder) {
5080 encoder->enable(encoder);
5081 intel_opregion_notify_encoder(encoder, true);
5082 }
5083
5084 /* If we change the relative order between pipe/planes enabling, we need
5085 * to change the workaround. */
5086 haswell_mode_set_planes_workaround(intel_crtc);
5087 }
5088
5089 static void ironlake_pfit_disable(struct intel_crtc *crtc)
5090 {
5091 struct drm_device *dev = crtc->base.dev;
5092 struct drm_i915_private *dev_priv = dev->dev_private;
5093 int pipe = crtc->pipe;
5094
5095 /* To avoid upsetting the power well on haswell only disable the pfit if
5096 * it's in use. The hw state code will make sure we get this right. */
5097 if (crtc->config->pch_pfit.enabled) {
5098 I915_WRITE(PF_CTL(pipe), 0);
5099 I915_WRITE(PF_WIN_POS(pipe), 0);
5100 I915_WRITE(PF_WIN_SZ(pipe), 0);
5101 }
5102 }
5103
5104 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5105 {
5106 struct drm_device *dev = crtc->dev;
5107 struct drm_i915_private *dev_priv = dev->dev_private;
5108 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5109 struct intel_encoder *encoder;
5110 int pipe = intel_crtc->pipe;
5111 u32 reg, temp;
5112
5113 if (!intel_crtc->active)
5114 return;
5115
5116 for_each_encoder_on_crtc(dev, crtc, encoder)
5117 encoder->disable(encoder);
5118
5119 drm_crtc_vblank_off(crtc);
5120 assert_vblank_disabled(crtc);
5121
5122 if (intel_crtc->config->has_pch_encoder)
5123 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5124
5125 intel_disable_pipe(intel_crtc);
5126
5127 ironlake_pfit_disable(intel_crtc);
5128
5129 for_each_encoder_on_crtc(dev, crtc, encoder)
5130 if (encoder->post_disable)
5131 encoder->post_disable(encoder);
5132
5133 if (intel_crtc->config->has_pch_encoder) {
5134 ironlake_fdi_disable(crtc);
5135
5136 ironlake_disable_pch_transcoder(dev_priv, pipe);
5137
5138 if (HAS_PCH_CPT(dev)) {
5139 /* disable TRANS_DP_CTL */
5140 reg = TRANS_DP_CTL(pipe);
5141 temp = I915_READ(reg);
5142 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5143 TRANS_DP_PORT_SEL_MASK);
5144 temp |= TRANS_DP_PORT_SEL_NONE;
5145 I915_WRITE(reg, temp);
5146
5147 /* disable DPLL_SEL */
5148 temp = I915_READ(PCH_DPLL_SEL);
5149 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5150 I915_WRITE(PCH_DPLL_SEL, temp);
5151 }
5152
5153 /* disable PCH DPLL */
5154 intel_disable_shared_dpll(intel_crtc);
5155
5156 ironlake_fdi_pll_disable(intel_crtc);
5157 }
5158
5159 intel_crtc->active = false;
5160 intel_update_watermarks(crtc);
5161
5162 mutex_lock(&dev->struct_mutex);
5163 intel_fbc_update(dev);
5164 mutex_unlock(&dev->struct_mutex);
5165 }
5166
5167 static void haswell_crtc_disable(struct drm_crtc *crtc)
5168 {
5169 struct drm_device *dev = crtc->dev;
5170 struct drm_i915_private *dev_priv = dev->dev_private;
5171 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5172 struct intel_encoder *encoder;
5173 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5174
5175 if (!intel_crtc->active)
5176 return;
5177
5178 for_each_encoder_on_crtc(dev, crtc, encoder) {
5179 intel_opregion_notify_encoder(encoder, false);
5180 encoder->disable(encoder);
5181 }
5182
5183 drm_crtc_vblank_off(crtc);
5184 assert_vblank_disabled(crtc);
5185
5186 if (intel_crtc->config->has_pch_encoder)
5187 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5188 false);
5189 intel_disable_pipe(intel_crtc);
5190
5191 if (intel_crtc->config->dp_encoder_is_mst)
5192 intel_ddi_set_vc_payload_alloc(crtc, false);
5193
5194 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5195
5196 if (INTEL_INFO(dev)->gen == 9)
5197 skylake_pfit_update(intel_crtc, 0);
5198 else if (INTEL_INFO(dev)->gen < 9)
5199 ironlake_pfit_disable(intel_crtc);
5200 else
5201 MISSING_CASE(INTEL_INFO(dev)->gen);
5202
5203 intel_ddi_disable_pipe_clock(intel_crtc);
5204
5205 if (intel_crtc->config->has_pch_encoder) {
5206 lpt_disable_pch_transcoder(dev_priv);
5207 intel_ddi_fdi_disable(crtc);
5208 }
5209
5210 for_each_encoder_on_crtc(dev, crtc, encoder)
5211 if (encoder->post_disable)
5212 encoder->post_disable(encoder);
5213
5214 intel_crtc->active = false;
5215 intel_update_watermarks(crtc);
5216
5217 mutex_lock(&dev->struct_mutex);
5218 intel_fbc_update(dev);
5219 mutex_unlock(&dev->struct_mutex);
5220
5221 if (intel_crtc_to_shared_dpll(intel_crtc))
5222 intel_disable_shared_dpll(intel_crtc);
5223 }
5224
5225 static void ironlake_crtc_off(struct drm_crtc *crtc)
5226 {
5227 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5228 intel_put_shared_dpll(intel_crtc);
5229 }
5230
5231
5232 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5233 {
5234 struct drm_device *dev = crtc->base.dev;
5235 struct drm_i915_private *dev_priv = dev->dev_private;
5236 struct intel_crtc_state *pipe_config = crtc->config;
5237
5238 if (!pipe_config->gmch_pfit.control)
5239 return;
5240
5241 /*
5242 * The panel fitter should only be adjusted whilst the pipe is disabled,
5243 * according to register description and PRM.
5244 */
5245 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5246 assert_pipe_disabled(dev_priv, crtc->pipe);
5247
5248 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5249 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5250
5251 /* Border color in case we don't scale up to the full screen. Black by
5252 * default, change to something else for debugging. */
5253 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5254 }
5255
5256 static enum intel_display_power_domain port_to_power_domain(enum port port)
5257 {
5258 switch (port) {
5259 case PORT_A:
5260 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5261 case PORT_B:
5262 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5263 case PORT_C:
5264 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5265 case PORT_D:
5266 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5267 default:
5268 WARN_ON_ONCE(1);
5269 return POWER_DOMAIN_PORT_OTHER;
5270 }
5271 }
5272
5273 #define for_each_power_domain(domain, mask) \
5274 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5275 if ((1 << (domain)) & (mask))
5276
5277 enum intel_display_power_domain
5278 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5279 {
5280 struct drm_device *dev = intel_encoder->base.dev;
5281 struct intel_digital_port *intel_dig_port;
5282
5283 switch (intel_encoder->type) {
5284 case INTEL_OUTPUT_UNKNOWN:
5285 /* Only DDI platforms should ever use this output type */
5286 WARN_ON_ONCE(!HAS_DDI(dev));
5287 case INTEL_OUTPUT_DISPLAYPORT:
5288 case INTEL_OUTPUT_HDMI:
5289 case INTEL_OUTPUT_EDP:
5290 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5291 return port_to_power_domain(intel_dig_port->port);
5292 case INTEL_OUTPUT_DP_MST:
5293 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5294 return port_to_power_domain(intel_dig_port->port);
5295 case INTEL_OUTPUT_ANALOG:
5296 return POWER_DOMAIN_PORT_CRT;
5297 case INTEL_OUTPUT_DSI:
5298 return POWER_DOMAIN_PORT_DSI;
5299 default:
5300 return POWER_DOMAIN_PORT_OTHER;
5301 }
5302 }
5303
5304 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5305 {
5306 struct drm_device *dev = crtc->dev;
5307 struct intel_encoder *intel_encoder;
5308 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5309 enum pipe pipe = intel_crtc->pipe;
5310 unsigned long mask;
5311 enum transcoder transcoder;
5312
5313 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5314
5315 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5316 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5317 if (intel_crtc->config->pch_pfit.enabled ||
5318 intel_crtc->config->pch_pfit.force_thru)
5319 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5320
5321 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5322 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5323
5324 return mask;
5325 }
5326
5327 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5328 {
5329 struct drm_device *dev = state->dev;
5330 struct drm_i915_private *dev_priv = dev->dev_private;
5331 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5332 struct intel_crtc *crtc;
5333
5334 /*
5335 * First get all needed power domains, then put all unneeded, to avoid
5336 * any unnecessary toggling of the power wells.
5337 */
5338 for_each_intel_crtc(dev, crtc) {
5339 enum intel_display_power_domain domain;
5340
5341 if (!crtc->base.state->enable)
5342 continue;
5343
5344 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
5345
5346 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5347 intel_display_power_get(dev_priv, domain);
5348 }
5349
5350 if (dev_priv->display.modeset_global_resources)
5351 dev_priv->display.modeset_global_resources(state);
5352
5353 for_each_intel_crtc(dev, crtc) {
5354 enum intel_display_power_domain domain;
5355
5356 for_each_power_domain(domain, crtc->enabled_power_domains)
5357 intel_display_power_put(dev_priv, domain);
5358
5359 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5360 }
5361
5362 intel_display_set_init_power(dev_priv, false);
5363 }
5364
5365 void broxton_set_cdclk(struct drm_device *dev, int frequency)
5366 {
5367 struct drm_i915_private *dev_priv = dev->dev_private;
5368 uint32_t divider;
5369 uint32_t ratio;
5370 uint32_t current_freq;
5371 int ret;
5372
5373 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5374 switch (frequency) {
5375 case 144000:
5376 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5377 ratio = BXT_DE_PLL_RATIO(60);
5378 break;
5379 case 288000:
5380 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5381 ratio = BXT_DE_PLL_RATIO(60);
5382 break;
5383 case 384000:
5384 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5385 ratio = BXT_DE_PLL_RATIO(60);
5386 break;
5387 case 576000:
5388 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5389 ratio = BXT_DE_PLL_RATIO(60);
5390 break;
5391 case 624000:
5392 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5393 ratio = BXT_DE_PLL_RATIO(65);
5394 break;
5395 case 19200:
5396 /*
5397 * Bypass frequency with DE PLL disabled. Init ratio, divider
5398 * to suppress GCC warning.
5399 */
5400 ratio = 0;
5401 divider = 0;
5402 break;
5403 default:
5404 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5405
5406 return;
5407 }
5408
5409 mutex_lock(&dev_priv->rps.hw_lock);
5410 /* Inform power controller of upcoming frequency change */
5411 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5412 0x80000000);
5413 mutex_unlock(&dev_priv->rps.hw_lock);
5414
5415 if (ret) {
5416 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5417 ret, frequency);
5418 return;
5419 }
5420
5421 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5422 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5423 current_freq = current_freq * 500 + 1000;
5424
5425 /*
5426 * DE PLL has to be disabled when
5427 * - setting to 19.2MHz (bypass, PLL isn't used)
5428 * - before setting to 624MHz (PLL needs toggling)
5429 * - before setting to any frequency from 624MHz (PLL needs toggling)
5430 */
5431 if (frequency == 19200 || frequency == 624000 ||
5432 current_freq == 624000) {
5433 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5434 /* Timeout 200us */
5435 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5436 1))
5437 DRM_ERROR("timout waiting for DE PLL unlock\n");
5438 }
5439
5440 if (frequency != 19200) {
5441 uint32_t val;
5442
5443 val = I915_READ(BXT_DE_PLL_CTL);
5444 val &= ~BXT_DE_PLL_RATIO_MASK;
5445 val |= ratio;
5446 I915_WRITE(BXT_DE_PLL_CTL, val);
5447
5448 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5449 /* Timeout 200us */
5450 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5451 DRM_ERROR("timeout waiting for DE PLL lock\n");
5452
5453 val = I915_READ(CDCLK_CTL);
5454 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5455 val |= divider;
5456 /*
5457 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5458 * enable otherwise.
5459 */
5460 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5461 if (frequency >= 500000)
5462 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5463
5464 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5465 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5466 val |= (frequency - 1000) / 500;
5467 I915_WRITE(CDCLK_CTL, val);
5468 }
5469
5470 mutex_lock(&dev_priv->rps.hw_lock);
5471 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5472 DIV_ROUND_UP(frequency, 25000));
5473 mutex_unlock(&dev_priv->rps.hw_lock);
5474
5475 if (ret) {
5476 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5477 ret, frequency);
5478 return;
5479 }
5480
5481 dev_priv->cdclk_freq = frequency;
5482 }
5483
5484 void broxton_init_cdclk(struct drm_device *dev)
5485 {
5486 struct drm_i915_private *dev_priv = dev->dev_private;
5487 uint32_t val;
5488
5489 /*
5490 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5491 * or else the reset will hang because there is no PCH to respond.
5492 * Move the handshake programming to initialization sequence.
5493 * Previously was left up to BIOS.
5494 */
5495 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5496 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5497 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5498
5499 /* Enable PG1 for cdclk */
5500 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5501
5502 /* check if cd clock is enabled */
5503 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5504 DRM_DEBUG_KMS("Display already initialized\n");
5505 return;
5506 }
5507
5508 /*
5509 * FIXME:
5510 * - The initial CDCLK needs to be read from VBT.
5511 * Need to make this change after VBT has changes for BXT.
5512 * - check if setting the max (or any) cdclk freq is really necessary
5513 * here, it belongs to modeset time
5514 */
5515 broxton_set_cdclk(dev, 624000);
5516
5517 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5518 POSTING_READ(DBUF_CTL);
5519
5520 udelay(10);
5521
5522 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5523 DRM_ERROR("DBuf power enable timeout!\n");
5524 }
5525
5526 void broxton_uninit_cdclk(struct drm_device *dev)
5527 {
5528 struct drm_i915_private *dev_priv = dev->dev_private;
5529
5530 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5531 POSTING_READ(DBUF_CTL);
5532
5533 udelay(10);
5534
5535 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5536 DRM_ERROR("DBuf power disable timeout!\n");
5537
5538 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5539 broxton_set_cdclk(dev, 19200);
5540
5541 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5542 }
5543
5544 /* returns HPLL frequency in kHz */
5545 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
5546 {
5547 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
5548
5549 /* Obtain SKU information */
5550 mutex_lock(&dev_priv->dpio_lock);
5551 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5552 CCK_FUSE_HPLL_FREQ_MASK;
5553 mutex_unlock(&dev_priv->dpio_lock);
5554
5555 return vco_freq[hpll_freq] * 1000;
5556 }
5557
5558 static void vlv_update_cdclk(struct drm_device *dev)
5559 {
5560 struct drm_i915_private *dev_priv = dev->dev_private;
5561
5562 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5563 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5564 dev_priv->cdclk_freq);
5565
5566 /*
5567 * Program the gmbus_freq based on the cdclk frequency.
5568 * BSpec erroneously claims we should aim for 4MHz, but
5569 * in fact 1MHz is the correct frequency.
5570 */
5571 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5572 }
5573
5574 /* Adjust CDclk dividers to allow high res or save power if possible */
5575 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5576 {
5577 struct drm_i915_private *dev_priv = dev->dev_private;
5578 u32 val, cmd;
5579
5580 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5581 != dev_priv->cdclk_freq);
5582
5583 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5584 cmd = 2;
5585 else if (cdclk == 266667)
5586 cmd = 1;
5587 else
5588 cmd = 0;
5589
5590 mutex_lock(&dev_priv->rps.hw_lock);
5591 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5592 val &= ~DSPFREQGUAR_MASK;
5593 val |= (cmd << DSPFREQGUAR_SHIFT);
5594 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5595 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5596 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5597 50)) {
5598 DRM_ERROR("timed out waiting for CDclk change\n");
5599 }
5600 mutex_unlock(&dev_priv->rps.hw_lock);
5601
5602 if (cdclk == 400000) {
5603 u32 divider;
5604
5605 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5606
5607 mutex_lock(&dev_priv->dpio_lock);
5608 /* adjust cdclk divider */
5609 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5610 val &= ~DISPLAY_FREQUENCY_VALUES;
5611 val |= divider;
5612 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5613
5614 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5615 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5616 50))
5617 DRM_ERROR("timed out waiting for CDclk change\n");
5618 mutex_unlock(&dev_priv->dpio_lock);
5619 }
5620
5621 mutex_lock(&dev_priv->dpio_lock);
5622 /* adjust self-refresh exit latency value */
5623 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5624 val &= ~0x7f;
5625
5626 /*
5627 * For high bandwidth configs, we set a higher latency in the bunit
5628 * so that the core display fetch happens in time to avoid underruns.
5629 */
5630 if (cdclk == 400000)
5631 val |= 4500 / 250; /* 4.5 usec */
5632 else
5633 val |= 3000 / 250; /* 3.0 usec */
5634 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5635 mutex_unlock(&dev_priv->dpio_lock);
5636
5637 vlv_update_cdclk(dev);
5638 }
5639
5640 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5641 {
5642 struct drm_i915_private *dev_priv = dev->dev_private;
5643 u32 val, cmd;
5644
5645 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5646 != dev_priv->cdclk_freq);
5647
5648 switch (cdclk) {
5649 case 333333:
5650 case 320000:
5651 case 266667:
5652 case 200000:
5653 break;
5654 default:
5655 MISSING_CASE(cdclk);
5656 return;
5657 }
5658
5659 /*
5660 * Specs are full of misinformation, but testing on actual
5661 * hardware has shown that we just need to write the desired
5662 * CCK divider into the Punit register.
5663 */
5664 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5665
5666 mutex_lock(&dev_priv->rps.hw_lock);
5667 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5668 val &= ~DSPFREQGUAR_MASK_CHV;
5669 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5670 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5671 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5672 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5673 50)) {
5674 DRM_ERROR("timed out waiting for CDclk change\n");
5675 }
5676 mutex_unlock(&dev_priv->rps.hw_lock);
5677
5678 vlv_update_cdclk(dev);
5679 }
5680
5681 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5682 int max_pixclk)
5683 {
5684 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5685 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5686
5687 /*
5688 * Really only a few cases to deal with, as only 4 CDclks are supported:
5689 * 200MHz
5690 * 267MHz
5691 * 320/333MHz (depends on HPLL freq)
5692 * 400MHz (VLV only)
5693 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5694 * of the lower bin and adjust if needed.
5695 *
5696 * We seem to get an unstable or solid color picture at 200MHz.
5697 * Not sure what's wrong. For now use 200MHz only when all pipes
5698 * are off.
5699 */
5700 if (!IS_CHERRYVIEW(dev_priv) &&
5701 max_pixclk > freq_320*limit/100)
5702 return 400000;
5703 else if (max_pixclk > 266667*limit/100)
5704 return freq_320;
5705 else if (max_pixclk > 0)
5706 return 266667;
5707 else
5708 return 200000;
5709 }
5710
5711 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5712 int max_pixclk)
5713 {
5714 /*
5715 * FIXME:
5716 * - remove the guardband, it's not needed on BXT
5717 * - set 19.2MHz bypass frequency if there are no active pipes
5718 */
5719 if (max_pixclk > 576000*9/10)
5720 return 624000;
5721 else if (max_pixclk > 384000*9/10)
5722 return 576000;
5723 else if (max_pixclk > 288000*9/10)
5724 return 384000;
5725 else if (max_pixclk > 144000*9/10)
5726 return 288000;
5727 else
5728 return 144000;
5729 }
5730
5731 /* compute the max pixel clock for new configuration */
5732 static int intel_mode_max_pixclk(struct drm_atomic_state *state)
5733 {
5734 struct drm_device *dev = state->dev;
5735 struct intel_crtc *intel_crtc;
5736 struct intel_crtc_state *crtc_state;
5737 int max_pixclk = 0;
5738
5739 for_each_intel_crtc(dev, intel_crtc) {
5740 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5741 if (IS_ERR(crtc_state))
5742 return PTR_ERR(crtc_state);
5743
5744 if (!crtc_state->base.enable)
5745 continue;
5746
5747 max_pixclk = max(max_pixclk,
5748 crtc_state->base.adjusted_mode.crtc_clock);
5749 }
5750
5751 return max_pixclk;
5752 }
5753
5754 static int valleyview_modeset_global_pipes(struct drm_atomic_state *state)
5755 {
5756 struct drm_i915_private *dev_priv = to_i915(state->dev);
5757 struct drm_crtc *crtc;
5758 struct drm_crtc_state *crtc_state;
5759 int max_pixclk = intel_mode_max_pixclk(state);
5760 int cdclk, i;
5761
5762 if (max_pixclk < 0)
5763 return max_pixclk;
5764
5765 if (IS_VALLEYVIEW(dev_priv))
5766 cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5767 else
5768 cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
5769
5770 if (cdclk == dev_priv->cdclk_freq)
5771 return 0;
5772
5773 /* add all active pipes to the state */
5774 for_each_crtc(state->dev, crtc) {
5775 if (!crtc->state->enable)
5776 continue;
5777
5778 crtc_state = drm_atomic_get_crtc_state(state, crtc);
5779 if (IS_ERR(crtc_state))
5780 return PTR_ERR(crtc_state);
5781 }
5782
5783 /* disable/enable all currently active pipes while we change cdclk */
5784 for_each_crtc_in_state(state, crtc, crtc_state, i)
5785 if (crtc_state->enable)
5786 crtc_state->mode_changed = true;
5787
5788 return 0;
5789 }
5790
5791 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5792 {
5793 unsigned int credits, default_credits;
5794
5795 if (IS_CHERRYVIEW(dev_priv))
5796 default_credits = PFI_CREDIT(12);
5797 else
5798 default_credits = PFI_CREDIT(8);
5799
5800 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5801 /* CHV suggested value is 31 or 63 */
5802 if (IS_CHERRYVIEW(dev_priv))
5803 credits = PFI_CREDIT_31;
5804 else
5805 credits = PFI_CREDIT(15);
5806 } else {
5807 credits = default_credits;
5808 }
5809
5810 /*
5811 * WA - write default credits before re-programming
5812 * FIXME: should we also set the resend bit here?
5813 */
5814 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5815 default_credits);
5816
5817 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5818 credits | PFI_CREDIT_RESEND);
5819
5820 /*
5821 * FIXME is this guaranteed to clear
5822 * immediately or should we poll for it?
5823 */
5824 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5825 }
5826
5827 static void valleyview_modeset_global_resources(struct drm_atomic_state *state)
5828 {
5829 struct drm_device *dev = state->dev;
5830 struct drm_i915_private *dev_priv = dev->dev_private;
5831 int max_pixclk = intel_mode_max_pixclk(state);
5832 int req_cdclk;
5833
5834 /* The only reason this can fail is if we fail to add the crtc_state
5835 * to the atomic state. But that can't happen since the call to
5836 * intel_mode_max_pixclk() in valleyview_modeset_global_pipes() (which
5837 * can't have failed otherwise the mode set would be aborted) added all
5838 * the states already. */
5839 if (WARN_ON(max_pixclk < 0))
5840 return;
5841
5842 req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5843
5844 if (req_cdclk != dev_priv->cdclk_freq) {
5845 /*
5846 * FIXME: We can end up here with all power domains off, yet
5847 * with a CDCLK frequency other than the minimum. To account
5848 * for this take the PIPE-A power domain, which covers the HW
5849 * blocks needed for the following programming. This can be
5850 * removed once it's guaranteed that we get here either with
5851 * the minimum CDCLK set, or the required power domains
5852 * enabled.
5853 */
5854 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5855
5856 if (IS_CHERRYVIEW(dev))
5857 cherryview_set_cdclk(dev, req_cdclk);
5858 else
5859 valleyview_set_cdclk(dev, req_cdclk);
5860
5861 vlv_program_pfi_credits(dev_priv);
5862
5863 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5864 }
5865 }
5866
5867 static void valleyview_crtc_enable(struct drm_crtc *crtc)
5868 {
5869 struct drm_device *dev = crtc->dev;
5870 struct drm_i915_private *dev_priv = to_i915(dev);
5871 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5872 struct intel_encoder *encoder;
5873 int pipe = intel_crtc->pipe;
5874 bool is_dsi;
5875
5876 WARN_ON(!crtc->state->enable);
5877
5878 if (intel_crtc->active)
5879 return;
5880
5881 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5882
5883 if (!is_dsi) {
5884 if (IS_CHERRYVIEW(dev))
5885 chv_prepare_pll(intel_crtc, intel_crtc->config);
5886 else
5887 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5888 }
5889
5890 if (intel_crtc->config->has_dp_encoder)
5891 intel_dp_set_m_n(intel_crtc, M1_N1);
5892
5893 intel_set_pipe_timings(intel_crtc);
5894
5895 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5896 struct drm_i915_private *dev_priv = dev->dev_private;
5897
5898 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5899 I915_WRITE(CHV_CANVAS(pipe), 0);
5900 }
5901
5902 i9xx_set_pipeconf(intel_crtc);
5903
5904 intel_crtc->active = true;
5905
5906 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5907
5908 for_each_encoder_on_crtc(dev, crtc, encoder)
5909 if (encoder->pre_pll_enable)
5910 encoder->pre_pll_enable(encoder);
5911
5912 if (!is_dsi) {
5913 if (IS_CHERRYVIEW(dev))
5914 chv_enable_pll(intel_crtc, intel_crtc->config);
5915 else
5916 vlv_enable_pll(intel_crtc, intel_crtc->config);
5917 }
5918
5919 for_each_encoder_on_crtc(dev, crtc, encoder)
5920 if (encoder->pre_enable)
5921 encoder->pre_enable(encoder);
5922
5923 i9xx_pfit_enable(intel_crtc);
5924
5925 intel_crtc_load_lut(crtc);
5926
5927 intel_update_watermarks(crtc);
5928 intel_enable_pipe(intel_crtc);
5929
5930 assert_vblank_disabled(crtc);
5931 drm_crtc_vblank_on(crtc);
5932
5933 for_each_encoder_on_crtc(dev, crtc, encoder)
5934 encoder->enable(encoder);
5935 }
5936
5937 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5938 {
5939 struct drm_device *dev = crtc->base.dev;
5940 struct drm_i915_private *dev_priv = dev->dev_private;
5941
5942 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5943 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5944 }
5945
5946 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5947 {
5948 struct drm_device *dev = crtc->dev;
5949 struct drm_i915_private *dev_priv = to_i915(dev);
5950 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5951 struct intel_encoder *encoder;
5952 int pipe = intel_crtc->pipe;
5953
5954 WARN_ON(!crtc->state->enable);
5955
5956 if (intel_crtc->active)
5957 return;
5958
5959 i9xx_set_pll_dividers(intel_crtc);
5960
5961 if (intel_crtc->config->has_dp_encoder)
5962 intel_dp_set_m_n(intel_crtc, M1_N1);
5963
5964 intel_set_pipe_timings(intel_crtc);
5965
5966 i9xx_set_pipeconf(intel_crtc);
5967
5968 intel_crtc->active = true;
5969
5970 if (!IS_GEN2(dev))
5971 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5972
5973 for_each_encoder_on_crtc(dev, crtc, encoder)
5974 if (encoder->pre_enable)
5975 encoder->pre_enable(encoder);
5976
5977 i9xx_enable_pll(intel_crtc);
5978
5979 i9xx_pfit_enable(intel_crtc);
5980
5981 intel_crtc_load_lut(crtc);
5982
5983 intel_update_watermarks(crtc);
5984 intel_enable_pipe(intel_crtc);
5985
5986 assert_vblank_disabled(crtc);
5987 drm_crtc_vblank_on(crtc);
5988
5989 for_each_encoder_on_crtc(dev, crtc, encoder)
5990 encoder->enable(encoder);
5991 }
5992
5993 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5994 {
5995 struct drm_device *dev = crtc->base.dev;
5996 struct drm_i915_private *dev_priv = dev->dev_private;
5997
5998 if (!crtc->config->gmch_pfit.control)
5999 return;
6000
6001 assert_pipe_disabled(dev_priv, crtc->pipe);
6002
6003 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6004 I915_READ(PFIT_CONTROL));
6005 I915_WRITE(PFIT_CONTROL, 0);
6006 }
6007
6008 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6009 {
6010 struct drm_device *dev = crtc->dev;
6011 struct drm_i915_private *dev_priv = dev->dev_private;
6012 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6013 struct intel_encoder *encoder;
6014 int pipe = intel_crtc->pipe;
6015
6016 if (!intel_crtc->active)
6017 return;
6018
6019 /*
6020 * On gen2 planes are double buffered but the pipe isn't, so we must
6021 * wait for planes to fully turn off before disabling the pipe.
6022 * We also need to wait on all gmch platforms because of the
6023 * self-refresh mode constraint explained above.
6024 */
6025 intel_wait_for_vblank(dev, pipe);
6026
6027 for_each_encoder_on_crtc(dev, crtc, encoder)
6028 encoder->disable(encoder);
6029
6030 drm_crtc_vblank_off(crtc);
6031 assert_vblank_disabled(crtc);
6032
6033 intel_disable_pipe(intel_crtc);
6034
6035 i9xx_pfit_disable(intel_crtc);
6036
6037 for_each_encoder_on_crtc(dev, crtc, encoder)
6038 if (encoder->post_disable)
6039 encoder->post_disable(encoder);
6040
6041 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6042 if (IS_CHERRYVIEW(dev))
6043 chv_disable_pll(dev_priv, pipe);
6044 else if (IS_VALLEYVIEW(dev))
6045 vlv_disable_pll(dev_priv, pipe);
6046 else
6047 i9xx_disable_pll(intel_crtc);
6048 }
6049
6050 if (!IS_GEN2(dev))
6051 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6052
6053 intel_crtc->active = false;
6054 intel_update_watermarks(crtc);
6055
6056 mutex_lock(&dev->struct_mutex);
6057 intel_fbc_update(dev);
6058 mutex_unlock(&dev->struct_mutex);
6059 }
6060
6061 static void i9xx_crtc_off(struct drm_crtc *crtc)
6062 {
6063 }
6064
6065 /* Master function to enable/disable CRTC and corresponding power wells */
6066 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
6067 {
6068 struct drm_device *dev = crtc->dev;
6069 struct drm_i915_private *dev_priv = dev->dev_private;
6070 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6071 enum intel_display_power_domain domain;
6072 unsigned long domains;
6073
6074 if (enable) {
6075 if (!intel_crtc->active) {
6076 domains = get_crtc_power_domains(crtc);
6077 for_each_power_domain(domain, domains)
6078 intel_display_power_get(dev_priv, domain);
6079 intel_crtc->enabled_power_domains = domains;
6080
6081 dev_priv->display.crtc_enable(crtc);
6082 intel_crtc_enable_planes(crtc);
6083 }
6084 } else {
6085 if (intel_crtc->active) {
6086 intel_crtc_disable_planes(crtc);
6087 dev_priv->display.crtc_disable(crtc);
6088
6089 domains = intel_crtc->enabled_power_domains;
6090 for_each_power_domain(domain, domains)
6091 intel_display_power_put(dev_priv, domain);
6092 intel_crtc->enabled_power_domains = 0;
6093 }
6094 }
6095 }
6096
6097 /**
6098 * Sets the power management mode of the pipe and plane.
6099 */
6100 void intel_crtc_update_dpms(struct drm_crtc *crtc)
6101 {
6102 struct drm_device *dev = crtc->dev;
6103 struct intel_encoder *intel_encoder;
6104 bool enable = false;
6105
6106 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6107 enable |= intel_encoder->connectors_active;
6108
6109 intel_crtc_control(crtc, enable);
6110
6111 crtc->state->active = enable;
6112 }
6113
6114 static void intel_crtc_disable(struct drm_crtc *crtc)
6115 {
6116 struct drm_device *dev = crtc->dev;
6117 struct drm_connector *connector;
6118 struct drm_i915_private *dev_priv = dev->dev_private;
6119
6120 /* crtc should still be enabled when we disable it. */
6121 WARN_ON(!crtc->state->enable);
6122
6123 intel_crtc_disable_planes(crtc);
6124 dev_priv->display.crtc_disable(crtc);
6125 dev_priv->display.off(crtc);
6126
6127 drm_plane_helper_disable(crtc->primary);
6128
6129 /* Update computed state. */
6130 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6131 if (!connector->encoder || !connector->encoder->crtc)
6132 continue;
6133
6134 if (connector->encoder->crtc != crtc)
6135 continue;
6136
6137 connector->dpms = DRM_MODE_DPMS_OFF;
6138 to_intel_encoder(connector->encoder)->connectors_active = false;
6139 }
6140 }
6141
6142 void intel_encoder_destroy(struct drm_encoder *encoder)
6143 {
6144 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6145
6146 drm_encoder_cleanup(encoder);
6147 kfree(intel_encoder);
6148 }
6149
6150 /* Simple dpms helper for encoders with just one connector, no cloning and only
6151 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6152 * state of the entire output pipe. */
6153 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
6154 {
6155 if (mode == DRM_MODE_DPMS_ON) {
6156 encoder->connectors_active = true;
6157
6158 intel_crtc_update_dpms(encoder->base.crtc);
6159 } else {
6160 encoder->connectors_active = false;
6161
6162 intel_crtc_update_dpms(encoder->base.crtc);
6163 }
6164 }
6165
6166 /* Cross check the actual hw state with our own modeset state tracking (and it's
6167 * internal consistency). */
6168 static void intel_connector_check_state(struct intel_connector *connector)
6169 {
6170 if (connector->get_hw_state(connector)) {
6171 struct intel_encoder *encoder = connector->encoder;
6172 struct drm_crtc *crtc;
6173 bool encoder_enabled;
6174 enum pipe pipe;
6175
6176 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6177 connector->base.base.id,
6178 connector->base.name);
6179
6180 /* there is no real hw state for MST connectors */
6181 if (connector->mst_port)
6182 return;
6183
6184 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
6185 "wrong connector dpms state\n");
6186 I915_STATE_WARN(connector->base.encoder != &encoder->base,
6187 "active connector not linked to encoder\n");
6188
6189 if (encoder) {
6190 I915_STATE_WARN(!encoder->connectors_active,
6191 "encoder->connectors_active not set\n");
6192
6193 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
6194 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6195 if (I915_STATE_WARN_ON(!encoder->base.crtc))
6196 return;
6197
6198 crtc = encoder->base.crtc;
6199
6200 I915_STATE_WARN(!crtc->state->enable,
6201 "crtc not enabled\n");
6202 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6203 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
6204 "encoder active on the wrong pipe\n");
6205 }
6206 }
6207 }
6208
6209 int intel_connector_init(struct intel_connector *connector)
6210 {
6211 struct drm_connector_state *connector_state;
6212
6213 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6214 if (!connector_state)
6215 return -ENOMEM;
6216
6217 connector->base.state = connector_state;
6218 return 0;
6219 }
6220
6221 struct intel_connector *intel_connector_alloc(void)
6222 {
6223 struct intel_connector *connector;
6224
6225 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6226 if (!connector)
6227 return NULL;
6228
6229 if (intel_connector_init(connector) < 0) {
6230 kfree(connector);
6231 return NULL;
6232 }
6233
6234 return connector;
6235 }
6236
6237 /* Even simpler default implementation, if there's really no special case to
6238 * consider. */
6239 void intel_connector_dpms(struct drm_connector *connector, int mode)
6240 {
6241 /* All the simple cases only support two dpms states. */
6242 if (mode != DRM_MODE_DPMS_ON)
6243 mode = DRM_MODE_DPMS_OFF;
6244
6245 if (mode == connector->dpms)
6246 return;
6247
6248 connector->dpms = mode;
6249
6250 /* Only need to change hw state when actually enabled */
6251 if (connector->encoder)
6252 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
6253
6254 intel_modeset_check_state(connector->dev);
6255 }
6256
6257 /* Simple connector->get_hw_state implementation for encoders that support only
6258 * one connector and no cloning and hence the encoder state determines the state
6259 * of the connector. */
6260 bool intel_connector_get_hw_state(struct intel_connector *connector)
6261 {
6262 enum pipe pipe = 0;
6263 struct intel_encoder *encoder = connector->encoder;
6264
6265 return encoder->get_hw_state(encoder, &pipe);
6266 }
6267
6268 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6269 {
6270 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6271 return crtc_state->fdi_lanes;
6272
6273 return 0;
6274 }
6275
6276 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6277 struct intel_crtc_state *pipe_config)
6278 {
6279 struct drm_atomic_state *state = pipe_config->base.state;
6280 struct intel_crtc *other_crtc;
6281 struct intel_crtc_state *other_crtc_state;
6282
6283 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6284 pipe_name(pipe), pipe_config->fdi_lanes);
6285 if (pipe_config->fdi_lanes > 4) {
6286 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6287 pipe_name(pipe), pipe_config->fdi_lanes);
6288 return -EINVAL;
6289 }
6290
6291 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6292 if (pipe_config->fdi_lanes > 2) {
6293 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6294 pipe_config->fdi_lanes);
6295 return -EINVAL;
6296 } else {
6297 return 0;
6298 }
6299 }
6300
6301 if (INTEL_INFO(dev)->num_pipes == 2)
6302 return 0;
6303
6304 /* Ivybridge 3 pipe is really complicated */
6305 switch (pipe) {
6306 case PIPE_A:
6307 return 0;
6308 case PIPE_B:
6309 if (pipe_config->fdi_lanes <= 2)
6310 return 0;
6311
6312 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6313 other_crtc_state =
6314 intel_atomic_get_crtc_state(state, other_crtc);
6315 if (IS_ERR(other_crtc_state))
6316 return PTR_ERR(other_crtc_state);
6317
6318 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6319 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6320 pipe_name(pipe), pipe_config->fdi_lanes);
6321 return -EINVAL;
6322 }
6323 return 0;
6324 case PIPE_C:
6325 if (pipe_config->fdi_lanes > 2) {
6326 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6327 pipe_name(pipe), pipe_config->fdi_lanes);
6328 return -EINVAL;
6329 }
6330
6331 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6332 other_crtc_state =
6333 intel_atomic_get_crtc_state(state, other_crtc);
6334 if (IS_ERR(other_crtc_state))
6335 return PTR_ERR(other_crtc_state);
6336
6337 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6338 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6339 return -EINVAL;
6340 }
6341 return 0;
6342 default:
6343 BUG();
6344 }
6345 }
6346
6347 #define RETRY 1
6348 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6349 struct intel_crtc_state *pipe_config)
6350 {
6351 struct drm_device *dev = intel_crtc->base.dev;
6352 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6353 int lane, link_bw, fdi_dotclock, ret;
6354 bool needs_recompute = false;
6355
6356 retry:
6357 /* FDI is a binary signal running at ~2.7GHz, encoding
6358 * each output octet as 10 bits. The actual frequency
6359 * is stored as a divider into a 100MHz clock, and the
6360 * mode pixel clock is stored in units of 1KHz.
6361 * Hence the bw of each lane in terms of the mode signal
6362 * is:
6363 */
6364 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6365
6366 fdi_dotclock = adjusted_mode->crtc_clock;
6367
6368 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6369 pipe_config->pipe_bpp);
6370
6371 pipe_config->fdi_lanes = lane;
6372
6373 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6374 link_bw, &pipe_config->fdi_m_n);
6375
6376 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6377 intel_crtc->pipe, pipe_config);
6378 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6379 pipe_config->pipe_bpp -= 2*3;
6380 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6381 pipe_config->pipe_bpp);
6382 needs_recompute = true;
6383 pipe_config->bw_constrained = true;
6384
6385 goto retry;
6386 }
6387
6388 if (needs_recompute)
6389 return RETRY;
6390
6391 return ret;
6392 }
6393
6394 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6395 struct intel_crtc_state *pipe_config)
6396 {
6397 pipe_config->ips_enabled = i915.enable_ips &&
6398 hsw_crtc_supports_ips(crtc) &&
6399 pipe_config->pipe_bpp <= 24;
6400 }
6401
6402 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6403 struct intel_crtc_state *pipe_config)
6404 {
6405 struct drm_device *dev = crtc->base.dev;
6406 struct drm_i915_private *dev_priv = dev->dev_private;
6407 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6408 int ret;
6409
6410 /* FIXME should check pixel clock limits on all platforms */
6411 if (INTEL_INFO(dev)->gen < 4) {
6412 int clock_limit =
6413 dev_priv->display.get_display_clock_speed(dev);
6414
6415 /*
6416 * Enable pixel doubling when the dot clock
6417 * is > 90% of the (display) core speed.
6418 *
6419 * GDG double wide on either pipe,
6420 * otherwise pipe A only.
6421 */
6422 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6423 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6424 clock_limit *= 2;
6425 pipe_config->double_wide = true;
6426 }
6427
6428 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6429 return -EINVAL;
6430 }
6431
6432 /*
6433 * Pipe horizontal size must be even in:
6434 * - DVO ganged mode
6435 * - LVDS dual channel mode
6436 * - Double wide pipe
6437 */
6438 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6439 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6440 pipe_config->pipe_src_w &= ~1;
6441
6442 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6443 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6444 */
6445 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6446 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
6447 return -EINVAL;
6448
6449 if (HAS_IPS(dev))
6450 hsw_compute_ips_config(crtc, pipe_config);
6451
6452 if (pipe_config->has_pch_encoder)
6453 return ironlake_fdi_compute_config(crtc, pipe_config);
6454
6455 /* FIXME: remove below call once atomic mode set is place and all crtc
6456 * related checks called from atomic_crtc_check function */
6457 ret = 0;
6458 DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n",
6459 crtc, pipe_config->base.state);
6460 ret = intel_atomic_setup_scalers(dev, crtc, pipe_config);
6461
6462 return ret;
6463 }
6464
6465 static int skylake_get_display_clock_speed(struct drm_device *dev)
6466 {
6467 struct drm_i915_private *dev_priv = to_i915(dev);
6468 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6469 uint32_t cdctl = I915_READ(CDCLK_CTL);
6470 uint32_t linkrate;
6471
6472 if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
6473 WARN(1, "LCPLL1 not enabled\n");
6474 return 24000; /* 24MHz is the cd freq with NSSC ref */
6475 }
6476
6477 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6478 return 540000;
6479
6480 linkrate = (I915_READ(DPLL_CTRL1) &
6481 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6482
6483 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6484 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6485 /* vco 8640 */
6486 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6487 case CDCLK_FREQ_450_432:
6488 return 432000;
6489 case CDCLK_FREQ_337_308:
6490 return 308570;
6491 case CDCLK_FREQ_675_617:
6492 return 617140;
6493 default:
6494 WARN(1, "Unknown cd freq selection\n");
6495 }
6496 } else {
6497 /* vco 8100 */
6498 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6499 case CDCLK_FREQ_450_432:
6500 return 450000;
6501 case CDCLK_FREQ_337_308:
6502 return 337500;
6503 case CDCLK_FREQ_675_617:
6504 return 675000;
6505 default:
6506 WARN(1, "Unknown cd freq selection\n");
6507 }
6508 }
6509
6510 /* error case, do as if DPLL0 isn't enabled */
6511 return 24000;
6512 }
6513
6514 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6515 {
6516 struct drm_i915_private *dev_priv = dev->dev_private;
6517 uint32_t lcpll = I915_READ(LCPLL_CTL);
6518 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6519
6520 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6521 return 800000;
6522 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6523 return 450000;
6524 else if (freq == LCPLL_CLK_FREQ_450)
6525 return 450000;
6526 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6527 return 540000;
6528 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6529 return 337500;
6530 else
6531 return 675000;
6532 }
6533
6534 static int haswell_get_display_clock_speed(struct drm_device *dev)
6535 {
6536 struct drm_i915_private *dev_priv = dev->dev_private;
6537 uint32_t lcpll = I915_READ(LCPLL_CTL);
6538 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6539
6540 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6541 return 800000;
6542 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6543 return 450000;
6544 else if (freq == LCPLL_CLK_FREQ_450)
6545 return 450000;
6546 else if (IS_HSW_ULT(dev))
6547 return 337500;
6548 else
6549 return 540000;
6550 }
6551
6552 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6553 {
6554 struct drm_i915_private *dev_priv = dev->dev_private;
6555 u32 val;
6556 int divider;
6557
6558 if (dev_priv->hpll_freq == 0)
6559 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6560
6561 mutex_lock(&dev_priv->dpio_lock);
6562 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6563 mutex_unlock(&dev_priv->dpio_lock);
6564
6565 divider = val & DISPLAY_FREQUENCY_VALUES;
6566
6567 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6568 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6569 "cdclk change in progress\n");
6570
6571 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
6572 }
6573
6574 static int ilk_get_display_clock_speed(struct drm_device *dev)
6575 {
6576 return 450000;
6577 }
6578
6579 static int i945_get_display_clock_speed(struct drm_device *dev)
6580 {
6581 return 400000;
6582 }
6583
6584 static int i915_get_display_clock_speed(struct drm_device *dev)
6585 {
6586 return 333333;
6587 }
6588
6589 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6590 {
6591 return 200000;
6592 }
6593
6594 static int pnv_get_display_clock_speed(struct drm_device *dev)
6595 {
6596 u16 gcfgc = 0;
6597
6598 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6599
6600 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6601 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6602 return 266667;
6603 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6604 return 333333;
6605 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6606 return 444444;
6607 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6608 return 200000;
6609 default:
6610 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6611 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6612 return 133333;
6613 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6614 return 166667;
6615 }
6616 }
6617
6618 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6619 {
6620 u16 gcfgc = 0;
6621
6622 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6623
6624 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6625 return 133333;
6626 else {
6627 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6628 case GC_DISPLAY_CLOCK_333_MHZ:
6629 return 333333;
6630 default:
6631 case GC_DISPLAY_CLOCK_190_200_MHZ:
6632 return 190000;
6633 }
6634 }
6635 }
6636
6637 static int i865_get_display_clock_speed(struct drm_device *dev)
6638 {
6639 return 266667;
6640 }
6641
6642 static int i855_get_display_clock_speed(struct drm_device *dev)
6643 {
6644 u16 hpllcc = 0;
6645 /* Assume that the hardware is in the high speed state. This
6646 * should be the default.
6647 */
6648 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6649 case GC_CLOCK_133_200:
6650 case GC_CLOCK_100_200:
6651 return 200000;
6652 case GC_CLOCK_166_250:
6653 return 250000;
6654 case GC_CLOCK_100_133:
6655 return 133333;
6656 }
6657
6658 /* Shouldn't happen */
6659 return 0;
6660 }
6661
6662 static int i830_get_display_clock_speed(struct drm_device *dev)
6663 {
6664 return 133333;
6665 }
6666
6667 static void
6668 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6669 {
6670 while (*num > DATA_LINK_M_N_MASK ||
6671 *den > DATA_LINK_M_N_MASK) {
6672 *num >>= 1;
6673 *den >>= 1;
6674 }
6675 }
6676
6677 static void compute_m_n(unsigned int m, unsigned int n,
6678 uint32_t *ret_m, uint32_t *ret_n)
6679 {
6680 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6681 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6682 intel_reduce_m_n_ratio(ret_m, ret_n);
6683 }
6684
6685 void
6686 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6687 int pixel_clock, int link_clock,
6688 struct intel_link_m_n *m_n)
6689 {
6690 m_n->tu = 64;
6691
6692 compute_m_n(bits_per_pixel * pixel_clock,
6693 link_clock * nlanes * 8,
6694 &m_n->gmch_m, &m_n->gmch_n);
6695
6696 compute_m_n(pixel_clock, link_clock,
6697 &m_n->link_m, &m_n->link_n);
6698 }
6699
6700 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6701 {
6702 if (i915.panel_use_ssc >= 0)
6703 return i915.panel_use_ssc != 0;
6704 return dev_priv->vbt.lvds_use_ssc
6705 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6706 }
6707
6708 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
6709 int num_connectors)
6710 {
6711 struct drm_device *dev = crtc_state->base.crtc->dev;
6712 struct drm_i915_private *dev_priv = dev->dev_private;
6713 int refclk;
6714
6715 WARN_ON(!crtc_state->base.state);
6716
6717 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
6718 refclk = 100000;
6719 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6720 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6721 refclk = dev_priv->vbt.lvds_ssc_freq;
6722 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
6723 } else if (!IS_GEN2(dev)) {
6724 refclk = 96000;
6725 } else {
6726 refclk = 48000;
6727 }
6728
6729 return refclk;
6730 }
6731
6732 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6733 {
6734 return (1 << dpll->n) << 16 | dpll->m2;
6735 }
6736
6737 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6738 {
6739 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6740 }
6741
6742 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6743 struct intel_crtc_state *crtc_state,
6744 intel_clock_t *reduced_clock)
6745 {
6746 struct drm_device *dev = crtc->base.dev;
6747 u32 fp, fp2 = 0;
6748
6749 if (IS_PINEVIEW(dev)) {
6750 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6751 if (reduced_clock)
6752 fp2 = pnv_dpll_compute_fp(reduced_clock);
6753 } else {
6754 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6755 if (reduced_clock)
6756 fp2 = i9xx_dpll_compute_fp(reduced_clock);
6757 }
6758
6759 crtc_state->dpll_hw_state.fp0 = fp;
6760
6761 crtc->lowfreq_avail = false;
6762 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6763 reduced_clock) {
6764 crtc_state->dpll_hw_state.fp1 = fp2;
6765 crtc->lowfreq_avail = true;
6766 } else {
6767 crtc_state->dpll_hw_state.fp1 = fp;
6768 }
6769 }
6770
6771 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6772 pipe)
6773 {
6774 u32 reg_val;
6775
6776 /*
6777 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6778 * and set it to a reasonable value instead.
6779 */
6780 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6781 reg_val &= 0xffffff00;
6782 reg_val |= 0x00000030;
6783 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6784
6785 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6786 reg_val &= 0x8cffffff;
6787 reg_val = 0x8c000000;
6788 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6789
6790 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6791 reg_val &= 0xffffff00;
6792 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6793
6794 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6795 reg_val &= 0x00ffffff;
6796 reg_val |= 0xb0000000;
6797 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6798 }
6799
6800 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6801 struct intel_link_m_n *m_n)
6802 {
6803 struct drm_device *dev = crtc->base.dev;
6804 struct drm_i915_private *dev_priv = dev->dev_private;
6805 int pipe = crtc->pipe;
6806
6807 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6808 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6809 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6810 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6811 }
6812
6813 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6814 struct intel_link_m_n *m_n,
6815 struct intel_link_m_n *m2_n2)
6816 {
6817 struct drm_device *dev = crtc->base.dev;
6818 struct drm_i915_private *dev_priv = dev->dev_private;
6819 int pipe = crtc->pipe;
6820 enum transcoder transcoder = crtc->config->cpu_transcoder;
6821
6822 if (INTEL_INFO(dev)->gen >= 5) {
6823 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6824 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6825 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6826 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6827 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6828 * for gen < 8) and if DRRS is supported (to make sure the
6829 * registers are not unnecessarily accessed).
6830 */
6831 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6832 crtc->config->has_drrs) {
6833 I915_WRITE(PIPE_DATA_M2(transcoder),
6834 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6835 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6836 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6837 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6838 }
6839 } else {
6840 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6841 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6842 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6843 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6844 }
6845 }
6846
6847 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6848 {
6849 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6850
6851 if (m_n == M1_N1) {
6852 dp_m_n = &crtc->config->dp_m_n;
6853 dp_m2_n2 = &crtc->config->dp_m2_n2;
6854 } else if (m_n == M2_N2) {
6855
6856 /*
6857 * M2_N2 registers are not supported. Hence m2_n2 divider value
6858 * needs to be programmed into M1_N1.
6859 */
6860 dp_m_n = &crtc->config->dp_m2_n2;
6861 } else {
6862 DRM_ERROR("Unsupported divider value\n");
6863 return;
6864 }
6865
6866 if (crtc->config->has_pch_encoder)
6867 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6868 else
6869 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6870 }
6871
6872 static void vlv_update_pll(struct intel_crtc *crtc,
6873 struct intel_crtc_state *pipe_config)
6874 {
6875 u32 dpll, dpll_md;
6876
6877 /*
6878 * Enable DPIO clock input. We should never disable the reference
6879 * clock for pipe B, since VGA hotplug / manual detection depends
6880 * on it.
6881 */
6882 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
6883 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
6884 /* We should never disable this, set it here for state tracking */
6885 if (crtc->pipe == PIPE_B)
6886 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6887 dpll |= DPLL_VCO_ENABLE;
6888 pipe_config->dpll_hw_state.dpll = dpll;
6889
6890 dpll_md = (pipe_config->pixel_multiplier - 1)
6891 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6892 pipe_config->dpll_hw_state.dpll_md = dpll_md;
6893 }
6894
6895 static void vlv_prepare_pll(struct intel_crtc *crtc,
6896 const struct intel_crtc_state *pipe_config)
6897 {
6898 struct drm_device *dev = crtc->base.dev;
6899 struct drm_i915_private *dev_priv = dev->dev_private;
6900 int pipe = crtc->pipe;
6901 u32 mdiv;
6902 u32 bestn, bestm1, bestm2, bestp1, bestp2;
6903 u32 coreclk, reg_val;
6904
6905 mutex_lock(&dev_priv->dpio_lock);
6906
6907 bestn = pipe_config->dpll.n;
6908 bestm1 = pipe_config->dpll.m1;
6909 bestm2 = pipe_config->dpll.m2;
6910 bestp1 = pipe_config->dpll.p1;
6911 bestp2 = pipe_config->dpll.p2;
6912
6913 /* See eDP HDMI DPIO driver vbios notes doc */
6914
6915 /* PLL B needs special handling */
6916 if (pipe == PIPE_B)
6917 vlv_pllb_recal_opamp(dev_priv, pipe);
6918
6919 /* Set up Tx target for periodic Rcomp update */
6920 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6921
6922 /* Disable target IRef on PLL */
6923 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6924 reg_val &= 0x00ffffff;
6925 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6926
6927 /* Disable fast lock */
6928 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6929
6930 /* Set idtafcrecal before PLL is enabled */
6931 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6932 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6933 mdiv |= ((bestn << DPIO_N_SHIFT));
6934 mdiv |= (1 << DPIO_K_SHIFT);
6935
6936 /*
6937 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6938 * but we don't support that).
6939 * Note: don't use the DAC post divider as it seems unstable.
6940 */
6941 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6942 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6943
6944 mdiv |= DPIO_ENABLE_CALIBRATION;
6945 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6946
6947 /* Set HBR and RBR LPF coefficients */
6948 if (pipe_config->port_clock == 162000 ||
6949 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
6950 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
6951 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6952 0x009f0003);
6953 else
6954 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6955 0x00d0000f);
6956
6957 if (pipe_config->has_dp_encoder) {
6958 /* Use SSC source */
6959 if (pipe == PIPE_A)
6960 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6961 0x0df40000);
6962 else
6963 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6964 0x0df70000);
6965 } else { /* HDMI or VGA */
6966 /* Use bend source */
6967 if (pipe == PIPE_A)
6968 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6969 0x0df70000);
6970 else
6971 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6972 0x0df40000);
6973 }
6974
6975 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6976 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6977 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6978 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
6979 coreclk |= 0x01000000;
6980 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6981
6982 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6983 mutex_unlock(&dev_priv->dpio_lock);
6984 }
6985
6986 static void chv_update_pll(struct intel_crtc *crtc,
6987 struct intel_crtc_state *pipe_config)
6988 {
6989 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
6990 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6991 DPLL_VCO_ENABLE;
6992 if (crtc->pipe != PIPE_A)
6993 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6994
6995 pipe_config->dpll_hw_state.dpll_md =
6996 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6997 }
6998
6999 static void chv_prepare_pll(struct intel_crtc *crtc,
7000 const struct intel_crtc_state *pipe_config)
7001 {
7002 struct drm_device *dev = crtc->base.dev;
7003 struct drm_i915_private *dev_priv = dev->dev_private;
7004 int pipe = crtc->pipe;
7005 int dpll_reg = DPLL(crtc->pipe);
7006 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7007 u32 loopfilter, tribuf_calcntr;
7008 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7009 u32 dpio_val;
7010 int vco;
7011
7012 bestn = pipe_config->dpll.n;
7013 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7014 bestm1 = pipe_config->dpll.m1;
7015 bestm2 = pipe_config->dpll.m2 >> 22;
7016 bestp1 = pipe_config->dpll.p1;
7017 bestp2 = pipe_config->dpll.p2;
7018 vco = pipe_config->dpll.vco;
7019 dpio_val = 0;
7020 loopfilter = 0;
7021
7022 /*
7023 * Enable Refclk and SSC
7024 */
7025 I915_WRITE(dpll_reg,
7026 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7027
7028 mutex_lock(&dev_priv->dpio_lock);
7029
7030 /* p1 and p2 divider */
7031 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7032 5 << DPIO_CHV_S1_DIV_SHIFT |
7033 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7034 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7035 1 << DPIO_CHV_K_DIV_SHIFT);
7036
7037 /* Feedback post-divider - m2 */
7038 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7039
7040 /* Feedback refclk divider - n and m1 */
7041 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7042 DPIO_CHV_M1_DIV_BY_2 |
7043 1 << DPIO_CHV_N_DIV_SHIFT);
7044
7045 /* M2 fraction division */
7046 if (bestm2_frac)
7047 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7048
7049 /* M2 fraction division enable */
7050 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7051 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7052 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7053 if (bestm2_frac)
7054 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7055 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7056
7057 /* Program digital lock detect threshold */
7058 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7059 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7060 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7061 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7062 if (!bestm2_frac)
7063 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7064 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7065
7066 /* Loop filter */
7067 if (vco == 5400000) {
7068 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7069 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7070 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7071 tribuf_calcntr = 0x9;
7072 } else if (vco <= 6200000) {
7073 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7074 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7075 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7076 tribuf_calcntr = 0x9;
7077 } else if (vco <= 6480000) {
7078 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7079 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7080 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7081 tribuf_calcntr = 0x8;
7082 } else {
7083 /* Not supported. Apply the same limits as in the max case */
7084 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7085 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7086 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7087 tribuf_calcntr = 0;
7088 }
7089 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7090
7091 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7092 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7093 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7094 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7095
7096 /* AFC Recal */
7097 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7098 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7099 DPIO_AFC_RECAL);
7100
7101 mutex_unlock(&dev_priv->dpio_lock);
7102 }
7103
7104 /**
7105 * vlv_force_pll_on - forcibly enable just the PLL
7106 * @dev_priv: i915 private structure
7107 * @pipe: pipe PLL to enable
7108 * @dpll: PLL configuration
7109 *
7110 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7111 * in cases where we need the PLL enabled even when @pipe is not going to
7112 * be enabled.
7113 */
7114 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7115 const struct dpll *dpll)
7116 {
7117 struct intel_crtc *crtc =
7118 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7119 struct intel_crtc_state pipe_config = {
7120 .base.crtc = &crtc->base,
7121 .pixel_multiplier = 1,
7122 .dpll = *dpll,
7123 };
7124
7125 if (IS_CHERRYVIEW(dev)) {
7126 chv_update_pll(crtc, &pipe_config);
7127 chv_prepare_pll(crtc, &pipe_config);
7128 chv_enable_pll(crtc, &pipe_config);
7129 } else {
7130 vlv_update_pll(crtc, &pipe_config);
7131 vlv_prepare_pll(crtc, &pipe_config);
7132 vlv_enable_pll(crtc, &pipe_config);
7133 }
7134 }
7135
7136 /**
7137 * vlv_force_pll_off - forcibly disable just the PLL
7138 * @dev_priv: i915 private structure
7139 * @pipe: pipe PLL to disable
7140 *
7141 * Disable the PLL for @pipe. To be used in cases where we need
7142 * the PLL enabled even when @pipe is not going to be enabled.
7143 */
7144 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7145 {
7146 if (IS_CHERRYVIEW(dev))
7147 chv_disable_pll(to_i915(dev), pipe);
7148 else
7149 vlv_disable_pll(to_i915(dev), pipe);
7150 }
7151
7152 static void i9xx_update_pll(struct intel_crtc *crtc,
7153 struct intel_crtc_state *crtc_state,
7154 intel_clock_t *reduced_clock,
7155 int num_connectors)
7156 {
7157 struct drm_device *dev = crtc->base.dev;
7158 struct drm_i915_private *dev_priv = dev->dev_private;
7159 u32 dpll;
7160 bool is_sdvo;
7161 struct dpll *clock = &crtc_state->dpll;
7162
7163 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7164
7165 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7166 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7167
7168 dpll = DPLL_VGA_MODE_DIS;
7169
7170 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7171 dpll |= DPLLB_MODE_LVDS;
7172 else
7173 dpll |= DPLLB_MODE_DAC_SERIAL;
7174
7175 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7176 dpll |= (crtc_state->pixel_multiplier - 1)
7177 << SDVO_MULTIPLIER_SHIFT_HIRES;
7178 }
7179
7180 if (is_sdvo)
7181 dpll |= DPLL_SDVO_HIGH_SPEED;
7182
7183 if (crtc_state->has_dp_encoder)
7184 dpll |= DPLL_SDVO_HIGH_SPEED;
7185
7186 /* compute bitmask from p1 value */
7187 if (IS_PINEVIEW(dev))
7188 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7189 else {
7190 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7191 if (IS_G4X(dev) && reduced_clock)
7192 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7193 }
7194 switch (clock->p2) {
7195 case 5:
7196 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7197 break;
7198 case 7:
7199 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7200 break;
7201 case 10:
7202 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7203 break;
7204 case 14:
7205 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7206 break;
7207 }
7208 if (INTEL_INFO(dev)->gen >= 4)
7209 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7210
7211 if (crtc_state->sdvo_tv_clock)
7212 dpll |= PLL_REF_INPUT_TVCLKINBC;
7213 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7214 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7215 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7216 else
7217 dpll |= PLL_REF_INPUT_DREFCLK;
7218
7219 dpll |= DPLL_VCO_ENABLE;
7220 crtc_state->dpll_hw_state.dpll = dpll;
7221
7222 if (INTEL_INFO(dev)->gen >= 4) {
7223 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7224 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7225 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7226 }
7227 }
7228
7229 static void i8xx_update_pll(struct intel_crtc *crtc,
7230 struct intel_crtc_state *crtc_state,
7231 intel_clock_t *reduced_clock,
7232 int num_connectors)
7233 {
7234 struct drm_device *dev = crtc->base.dev;
7235 struct drm_i915_private *dev_priv = dev->dev_private;
7236 u32 dpll;
7237 struct dpll *clock = &crtc_state->dpll;
7238
7239 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7240
7241 dpll = DPLL_VGA_MODE_DIS;
7242
7243 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7244 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7245 } else {
7246 if (clock->p1 == 2)
7247 dpll |= PLL_P1_DIVIDE_BY_TWO;
7248 else
7249 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7250 if (clock->p2 == 4)
7251 dpll |= PLL_P2_DIVIDE_BY_4;
7252 }
7253
7254 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7255 dpll |= DPLL_DVO_2X_MODE;
7256
7257 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7258 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7259 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7260 else
7261 dpll |= PLL_REF_INPUT_DREFCLK;
7262
7263 dpll |= DPLL_VCO_ENABLE;
7264 crtc_state->dpll_hw_state.dpll = dpll;
7265 }
7266
7267 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7268 {
7269 struct drm_device *dev = intel_crtc->base.dev;
7270 struct drm_i915_private *dev_priv = dev->dev_private;
7271 enum pipe pipe = intel_crtc->pipe;
7272 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7273 struct drm_display_mode *adjusted_mode =
7274 &intel_crtc->config->base.adjusted_mode;
7275 uint32_t crtc_vtotal, crtc_vblank_end;
7276 int vsyncshift = 0;
7277
7278 /* We need to be careful not to changed the adjusted mode, for otherwise
7279 * the hw state checker will get angry at the mismatch. */
7280 crtc_vtotal = adjusted_mode->crtc_vtotal;
7281 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7282
7283 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7284 /* the chip adds 2 halflines automatically */
7285 crtc_vtotal -= 1;
7286 crtc_vblank_end -= 1;
7287
7288 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7289 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7290 else
7291 vsyncshift = adjusted_mode->crtc_hsync_start -
7292 adjusted_mode->crtc_htotal / 2;
7293 if (vsyncshift < 0)
7294 vsyncshift += adjusted_mode->crtc_htotal;
7295 }
7296
7297 if (INTEL_INFO(dev)->gen > 3)
7298 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7299
7300 I915_WRITE(HTOTAL(cpu_transcoder),
7301 (adjusted_mode->crtc_hdisplay - 1) |
7302 ((adjusted_mode->crtc_htotal - 1) << 16));
7303 I915_WRITE(HBLANK(cpu_transcoder),
7304 (adjusted_mode->crtc_hblank_start - 1) |
7305 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7306 I915_WRITE(HSYNC(cpu_transcoder),
7307 (adjusted_mode->crtc_hsync_start - 1) |
7308 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7309
7310 I915_WRITE(VTOTAL(cpu_transcoder),
7311 (adjusted_mode->crtc_vdisplay - 1) |
7312 ((crtc_vtotal - 1) << 16));
7313 I915_WRITE(VBLANK(cpu_transcoder),
7314 (adjusted_mode->crtc_vblank_start - 1) |
7315 ((crtc_vblank_end - 1) << 16));
7316 I915_WRITE(VSYNC(cpu_transcoder),
7317 (adjusted_mode->crtc_vsync_start - 1) |
7318 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7319
7320 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7321 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7322 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7323 * bits. */
7324 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7325 (pipe == PIPE_B || pipe == PIPE_C))
7326 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7327
7328 /* pipesrc controls the size that is scaled from, which should
7329 * always be the user's requested size.
7330 */
7331 I915_WRITE(PIPESRC(pipe),
7332 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7333 (intel_crtc->config->pipe_src_h - 1));
7334 }
7335
7336 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7337 struct intel_crtc_state *pipe_config)
7338 {
7339 struct drm_device *dev = crtc->base.dev;
7340 struct drm_i915_private *dev_priv = dev->dev_private;
7341 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7342 uint32_t tmp;
7343
7344 tmp = I915_READ(HTOTAL(cpu_transcoder));
7345 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7346 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7347 tmp = I915_READ(HBLANK(cpu_transcoder));
7348 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7349 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7350 tmp = I915_READ(HSYNC(cpu_transcoder));
7351 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7352 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7353
7354 tmp = I915_READ(VTOTAL(cpu_transcoder));
7355 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7356 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7357 tmp = I915_READ(VBLANK(cpu_transcoder));
7358 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7359 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7360 tmp = I915_READ(VSYNC(cpu_transcoder));
7361 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7362 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7363
7364 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7365 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7366 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7367 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7368 }
7369
7370 tmp = I915_READ(PIPESRC(crtc->pipe));
7371 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7372 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7373
7374 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7375 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7376 }
7377
7378 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7379 struct intel_crtc_state *pipe_config)
7380 {
7381 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7382 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7383 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7384 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7385
7386 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7387 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7388 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7389 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7390
7391 mode->flags = pipe_config->base.adjusted_mode.flags;
7392
7393 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7394 mode->flags |= pipe_config->base.adjusted_mode.flags;
7395 }
7396
7397 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7398 {
7399 struct drm_device *dev = intel_crtc->base.dev;
7400 struct drm_i915_private *dev_priv = dev->dev_private;
7401 uint32_t pipeconf;
7402
7403 pipeconf = 0;
7404
7405 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7406 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7407 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7408
7409 if (intel_crtc->config->double_wide)
7410 pipeconf |= PIPECONF_DOUBLE_WIDE;
7411
7412 /* only g4x and later have fancy bpc/dither controls */
7413 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7414 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7415 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7416 pipeconf |= PIPECONF_DITHER_EN |
7417 PIPECONF_DITHER_TYPE_SP;
7418
7419 switch (intel_crtc->config->pipe_bpp) {
7420 case 18:
7421 pipeconf |= PIPECONF_6BPC;
7422 break;
7423 case 24:
7424 pipeconf |= PIPECONF_8BPC;
7425 break;
7426 case 30:
7427 pipeconf |= PIPECONF_10BPC;
7428 break;
7429 default:
7430 /* Case prevented by intel_choose_pipe_bpp_dither. */
7431 BUG();
7432 }
7433 }
7434
7435 if (HAS_PIPE_CXSR(dev)) {
7436 if (intel_crtc->lowfreq_avail) {
7437 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7438 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7439 } else {
7440 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7441 }
7442 }
7443
7444 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7445 if (INTEL_INFO(dev)->gen < 4 ||
7446 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7447 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7448 else
7449 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7450 } else
7451 pipeconf |= PIPECONF_PROGRESSIVE;
7452
7453 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7454 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7455
7456 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7457 POSTING_READ(PIPECONF(intel_crtc->pipe));
7458 }
7459
7460 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7461 struct intel_crtc_state *crtc_state)
7462 {
7463 struct drm_device *dev = crtc->base.dev;
7464 struct drm_i915_private *dev_priv = dev->dev_private;
7465 int refclk, num_connectors = 0;
7466 intel_clock_t clock, reduced_clock;
7467 bool ok, has_reduced_clock = false;
7468 bool is_lvds = false, is_dsi = false;
7469 struct intel_encoder *encoder;
7470 const intel_limit_t *limit;
7471 struct drm_atomic_state *state = crtc_state->base.state;
7472 struct drm_connector *connector;
7473 struct drm_connector_state *connector_state;
7474 int i;
7475
7476 for_each_connector_in_state(state, connector, connector_state, i) {
7477 if (connector_state->crtc != &crtc->base)
7478 continue;
7479
7480 encoder = to_intel_encoder(connector_state->best_encoder);
7481
7482 switch (encoder->type) {
7483 case INTEL_OUTPUT_LVDS:
7484 is_lvds = true;
7485 break;
7486 case INTEL_OUTPUT_DSI:
7487 is_dsi = true;
7488 break;
7489 default:
7490 break;
7491 }
7492
7493 num_connectors++;
7494 }
7495
7496 if (is_dsi)
7497 return 0;
7498
7499 if (!crtc_state->clock_set) {
7500 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7501
7502 /*
7503 * Returns a set of divisors for the desired target clock with
7504 * the given refclk, or FALSE. The returned values represent
7505 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7506 * 2) / p1 / p2.
7507 */
7508 limit = intel_limit(crtc_state, refclk);
7509 ok = dev_priv->display.find_dpll(limit, crtc_state,
7510 crtc_state->port_clock,
7511 refclk, NULL, &clock);
7512 if (!ok) {
7513 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7514 return -EINVAL;
7515 }
7516
7517 if (is_lvds && dev_priv->lvds_downclock_avail) {
7518 /*
7519 * Ensure we match the reduced clock's P to the target
7520 * clock. If the clocks don't match, we can't switch
7521 * the display clock by using the FP0/FP1. In such case
7522 * we will disable the LVDS downclock feature.
7523 */
7524 has_reduced_clock =
7525 dev_priv->display.find_dpll(limit, crtc_state,
7526 dev_priv->lvds_downclock,
7527 refclk, &clock,
7528 &reduced_clock);
7529 }
7530 /* Compat-code for transition, will disappear. */
7531 crtc_state->dpll.n = clock.n;
7532 crtc_state->dpll.m1 = clock.m1;
7533 crtc_state->dpll.m2 = clock.m2;
7534 crtc_state->dpll.p1 = clock.p1;
7535 crtc_state->dpll.p2 = clock.p2;
7536 }
7537
7538 if (IS_GEN2(dev)) {
7539 i8xx_update_pll(crtc, crtc_state,
7540 has_reduced_clock ? &reduced_clock : NULL,
7541 num_connectors);
7542 } else if (IS_CHERRYVIEW(dev)) {
7543 chv_update_pll(crtc, crtc_state);
7544 } else if (IS_VALLEYVIEW(dev)) {
7545 vlv_update_pll(crtc, crtc_state);
7546 } else {
7547 i9xx_update_pll(crtc, crtc_state,
7548 has_reduced_clock ? &reduced_clock : NULL,
7549 num_connectors);
7550 }
7551
7552 return 0;
7553 }
7554
7555 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7556 struct intel_crtc_state *pipe_config)
7557 {
7558 struct drm_device *dev = crtc->base.dev;
7559 struct drm_i915_private *dev_priv = dev->dev_private;
7560 uint32_t tmp;
7561
7562 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7563 return;
7564
7565 tmp = I915_READ(PFIT_CONTROL);
7566 if (!(tmp & PFIT_ENABLE))
7567 return;
7568
7569 /* Check whether the pfit is attached to our pipe. */
7570 if (INTEL_INFO(dev)->gen < 4) {
7571 if (crtc->pipe != PIPE_B)
7572 return;
7573 } else {
7574 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7575 return;
7576 }
7577
7578 pipe_config->gmch_pfit.control = tmp;
7579 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7580 if (INTEL_INFO(dev)->gen < 5)
7581 pipe_config->gmch_pfit.lvds_border_bits =
7582 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7583 }
7584
7585 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7586 struct intel_crtc_state *pipe_config)
7587 {
7588 struct drm_device *dev = crtc->base.dev;
7589 struct drm_i915_private *dev_priv = dev->dev_private;
7590 int pipe = pipe_config->cpu_transcoder;
7591 intel_clock_t clock;
7592 u32 mdiv;
7593 int refclk = 100000;
7594
7595 /* In case of MIPI DPLL will not even be used */
7596 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7597 return;
7598
7599 mutex_lock(&dev_priv->dpio_lock);
7600 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7601 mutex_unlock(&dev_priv->dpio_lock);
7602
7603 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7604 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7605 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7606 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7607 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7608
7609 vlv_clock(refclk, &clock);
7610
7611 /* clock.dot is the fast clock */
7612 pipe_config->port_clock = clock.dot / 5;
7613 }
7614
7615 static void
7616 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7617 struct intel_initial_plane_config *plane_config)
7618 {
7619 struct drm_device *dev = crtc->base.dev;
7620 struct drm_i915_private *dev_priv = dev->dev_private;
7621 u32 val, base, offset;
7622 int pipe = crtc->pipe, plane = crtc->plane;
7623 int fourcc, pixel_format;
7624 unsigned int aligned_height;
7625 struct drm_framebuffer *fb;
7626 struct intel_framebuffer *intel_fb;
7627
7628 val = I915_READ(DSPCNTR(plane));
7629 if (!(val & DISPLAY_PLANE_ENABLE))
7630 return;
7631
7632 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7633 if (!intel_fb) {
7634 DRM_DEBUG_KMS("failed to alloc fb\n");
7635 return;
7636 }
7637
7638 fb = &intel_fb->base;
7639
7640 if (INTEL_INFO(dev)->gen >= 4) {
7641 if (val & DISPPLANE_TILED) {
7642 plane_config->tiling = I915_TILING_X;
7643 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7644 }
7645 }
7646
7647 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7648 fourcc = i9xx_format_to_fourcc(pixel_format);
7649 fb->pixel_format = fourcc;
7650 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7651
7652 if (INTEL_INFO(dev)->gen >= 4) {
7653 if (plane_config->tiling)
7654 offset = I915_READ(DSPTILEOFF(plane));
7655 else
7656 offset = I915_READ(DSPLINOFF(plane));
7657 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7658 } else {
7659 base = I915_READ(DSPADDR(plane));
7660 }
7661 plane_config->base = base;
7662
7663 val = I915_READ(PIPESRC(pipe));
7664 fb->width = ((val >> 16) & 0xfff) + 1;
7665 fb->height = ((val >> 0) & 0xfff) + 1;
7666
7667 val = I915_READ(DSPSTRIDE(pipe));
7668 fb->pitches[0] = val & 0xffffffc0;
7669
7670 aligned_height = intel_fb_align_height(dev, fb->height,
7671 fb->pixel_format,
7672 fb->modifier[0]);
7673
7674 plane_config->size = fb->pitches[0] * aligned_height;
7675
7676 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7677 pipe_name(pipe), plane, fb->width, fb->height,
7678 fb->bits_per_pixel, base, fb->pitches[0],
7679 plane_config->size);
7680
7681 plane_config->fb = intel_fb;
7682 }
7683
7684 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7685 struct intel_crtc_state *pipe_config)
7686 {
7687 struct drm_device *dev = crtc->base.dev;
7688 struct drm_i915_private *dev_priv = dev->dev_private;
7689 int pipe = pipe_config->cpu_transcoder;
7690 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7691 intel_clock_t clock;
7692 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
7693 int refclk = 100000;
7694
7695 mutex_lock(&dev_priv->dpio_lock);
7696 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7697 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7698 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7699 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7700 mutex_unlock(&dev_priv->dpio_lock);
7701
7702 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7703 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
7704 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7705 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7706 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7707
7708 chv_clock(refclk, &clock);
7709
7710 /* clock.dot is the fast clock */
7711 pipe_config->port_clock = clock.dot / 5;
7712 }
7713
7714 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7715 struct intel_crtc_state *pipe_config)
7716 {
7717 struct drm_device *dev = crtc->base.dev;
7718 struct drm_i915_private *dev_priv = dev->dev_private;
7719 uint32_t tmp;
7720
7721 if (!intel_display_power_is_enabled(dev_priv,
7722 POWER_DOMAIN_PIPE(crtc->pipe)))
7723 return false;
7724
7725 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7726 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7727
7728 tmp = I915_READ(PIPECONF(crtc->pipe));
7729 if (!(tmp & PIPECONF_ENABLE))
7730 return false;
7731
7732 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7733 switch (tmp & PIPECONF_BPC_MASK) {
7734 case PIPECONF_6BPC:
7735 pipe_config->pipe_bpp = 18;
7736 break;
7737 case PIPECONF_8BPC:
7738 pipe_config->pipe_bpp = 24;
7739 break;
7740 case PIPECONF_10BPC:
7741 pipe_config->pipe_bpp = 30;
7742 break;
7743 default:
7744 break;
7745 }
7746 }
7747
7748 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
7749 pipe_config->limited_color_range = true;
7750
7751 if (INTEL_INFO(dev)->gen < 4)
7752 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7753
7754 intel_get_pipe_timings(crtc, pipe_config);
7755
7756 i9xx_get_pfit_config(crtc, pipe_config);
7757
7758 if (INTEL_INFO(dev)->gen >= 4) {
7759 tmp = I915_READ(DPLL_MD(crtc->pipe));
7760 pipe_config->pixel_multiplier =
7761 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7762 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7763 pipe_config->dpll_hw_state.dpll_md = tmp;
7764 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7765 tmp = I915_READ(DPLL(crtc->pipe));
7766 pipe_config->pixel_multiplier =
7767 ((tmp & SDVO_MULTIPLIER_MASK)
7768 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7769 } else {
7770 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7771 * port and will be fixed up in the encoder->get_config
7772 * function. */
7773 pipe_config->pixel_multiplier = 1;
7774 }
7775 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7776 if (!IS_VALLEYVIEW(dev)) {
7777 /*
7778 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7779 * on 830. Filter it out here so that we don't
7780 * report errors due to that.
7781 */
7782 if (IS_I830(dev))
7783 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7784
7785 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7786 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7787 } else {
7788 /* Mask out read-only status bits. */
7789 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7790 DPLL_PORTC_READY_MASK |
7791 DPLL_PORTB_READY_MASK);
7792 }
7793
7794 if (IS_CHERRYVIEW(dev))
7795 chv_crtc_clock_get(crtc, pipe_config);
7796 else if (IS_VALLEYVIEW(dev))
7797 vlv_crtc_clock_get(crtc, pipe_config);
7798 else
7799 i9xx_crtc_clock_get(crtc, pipe_config);
7800
7801 return true;
7802 }
7803
7804 static void ironlake_init_pch_refclk(struct drm_device *dev)
7805 {
7806 struct drm_i915_private *dev_priv = dev->dev_private;
7807 struct intel_encoder *encoder;
7808 u32 val, final;
7809 bool has_lvds = false;
7810 bool has_cpu_edp = false;
7811 bool has_panel = false;
7812 bool has_ck505 = false;
7813 bool can_ssc = false;
7814
7815 /* We need to take the global config into account */
7816 for_each_intel_encoder(dev, encoder) {
7817 switch (encoder->type) {
7818 case INTEL_OUTPUT_LVDS:
7819 has_panel = true;
7820 has_lvds = true;
7821 break;
7822 case INTEL_OUTPUT_EDP:
7823 has_panel = true;
7824 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
7825 has_cpu_edp = true;
7826 break;
7827 default:
7828 break;
7829 }
7830 }
7831
7832 if (HAS_PCH_IBX(dev)) {
7833 has_ck505 = dev_priv->vbt.display_clock_mode;
7834 can_ssc = has_ck505;
7835 } else {
7836 has_ck505 = false;
7837 can_ssc = true;
7838 }
7839
7840 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
7841 has_panel, has_lvds, has_ck505);
7842
7843 /* Ironlake: try to setup display ref clock before DPLL
7844 * enabling. This is only under driver's control after
7845 * PCH B stepping, previous chipset stepping should be
7846 * ignoring this setting.
7847 */
7848 val = I915_READ(PCH_DREF_CONTROL);
7849
7850 /* As we must carefully and slowly disable/enable each source in turn,
7851 * compute the final state we want first and check if we need to
7852 * make any changes at all.
7853 */
7854 final = val;
7855 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7856 if (has_ck505)
7857 final |= DREF_NONSPREAD_CK505_ENABLE;
7858 else
7859 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7860
7861 final &= ~DREF_SSC_SOURCE_MASK;
7862 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7863 final &= ~DREF_SSC1_ENABLE;
7864
7865 if (has_panel) {
7866 final |= DREF_SSC_SOURCE_ENABLE;
7867
7868 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7869 final |= DREF_SSC1_ENABLE;
7870
7871 if (has_cpu_edp) {
7872 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7873 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7874 else
7875 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7876 } else
7877 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7878 } else {
7879 final |= DREF_SSC_SOURCE_DISABLE;
7880 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7881 }
7882
7883 if (final == val)
7884 return;
7885
7886 /* Always enable nonspread source */
7887 val &= ~DREF_NONSPREAD_SOURCE_MASK;
7888
7889 if (has_ck505)
7890 val |= DREF_NONSPREAD_CK505_ENABLE;
7891 else
7892 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7893
7894 if (has_panel) {
7895 val &= ~DREF_SSC_SOURCE_MASK;
7896 val |= DREF_SSC_SOURCE_ENABLE;
7897
7898 /* SSC must be turned on before enabling the CPU output */
7899 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7900 DRM_DEBUG_KMS("Using SSC on panel\n");
7901 val |= DREF_SSC1_ENABLE;
7902 } else
7903 val &= ~DREF_SSC1_ENABLE;
7904
7905 /* Get SSC going before enabling the outputs */
7906 I915_WRITE(PCH_DREF_CONTROL, val);
7907 POSTING_READ(PCH_DREF_CONTROL);
7908 udelay(200);
7909
7910 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7911
7912 /* Enable CPU source on CPU attached eDP */
7913 if (has_cpu_edp) {
7914 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7915 DRM_DEBUG_KMS("Using SSC on eDP\n");
7916 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7917 } else
7918 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7919 } else
7920 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7921
7922 I915_WRITE(PCH_DREF_CONTROL, val);
7923 POSTING_READ(PCH_DREF_CONTROL);
7924 udelay(200);
7925 } else {
7926 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7927
7928 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7929
7930 /* Turn off CPU output */
7931 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7932
7933 I915_WRITE(PCH_DREF_CONTROL, val);
7934 POSTING_READ(PCH_DREF_CONTROL);
7935 udelay(200);
7936
7937 /* Turn off the SSC source */
7938 val &= ~DREF_SSC_SOURCE_MASK;
7939 val |= DREF_SSC_SOURCE_DISABLE;
7940
7941 /* Turn off SSC1 */
7942 val &= ~DREF_SSC1_ENABLE;
7943
7944 I915_WRITE(PCH_DREF_CONTROL, val);
7945 POSTING_READ(PCH_DREF_CONTROL);
7946 udelay(200);
7947 }
7948
7949 BUG_ON(val != final);
7950 }
7951
7952 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7953 {
7954 uint32_t tmp;
7955
7956 tmp = I915_READ(SOUTH_CHICKEN2);
7957 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7958 I915_WRITE(SOUTH_CHICKEN2, tmp);
7959
7960 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
7961 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7962 DRM_ERROR("FDI mPHY reset assert timeout\n");
7963
7964 tmp = I915_READ(SOUTH_CHICKEN2);
7965 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7966 I915_WRITE(SOUTH_CHICKEN2, tmp);
7967
7968 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
7969 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7970 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7971 }
7972
7973 /* WaMPhyProgramming:hsw */
7974 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7975 {
7976 uint32_t tmp;
7977
7978 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7979 tmp &= ~(0xFF << 24);
7980 tmp |= (0x12 << 24);
7981 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7982
7983 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7984 tmp |= (1 << 11);
7985 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7986
7987 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7988 tmp |= (1 << 11);
7989 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7990
7991 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7992 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7993 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7994
7995 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7996 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7997 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7998
7999 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8000 tmp &= ~(7 << 13);
8001 tmp |= (5 << 13);
8002 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8003
8004 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8005 tmp &= ~(7 << 13);
8006 tmp |= (5 << 13);
8007 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8008
8009 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8010 tmp &= ~0xFF;
8011 tmp |= 0x1C;
8012 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8013
8014 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8015 tmp &= ~0xFF;
8016 tmp |= 0x1C;
8017 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8018
8019 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8020 tmp &= ~(0xFF << 16);
8021 tmp |= (0x1C << 16);
8022 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8023
8024 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8025 tmp &= ~(0xFF << 16);
8026 tmp |= (0x1C << 16);
8027 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8028
8029 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8030 tmp |= (1 << 27);
8031 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8032
8033 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8034 tmp |= (1 << 27);
8035 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8036
8037 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8038 tmp &= ~(0xF << 28);
8039 tmp |= (4 << 28);
8040 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8041
8042 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8043 tmp &= ~(0xF << 28);
8044 tmp |= (4 << 28);
8045 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8046 }
8047
8048 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8049 * Programming" based on the parameters passed:
8050 * - Sequence to enable CLKOUT_DP
8051 * - Sequence to enable CLKOUT_DP without spread
8052 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8053 */
8054 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8055 bool with_fdi)
8056 {
8057 struct drm_i915_private *dev_priv = dev->dev_private;
8058 uint32_t reg, tmp;
8059
8060 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8061 with_spread = true;
8062 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8063 with_fdi, "LP PCH doesn't have FDI\n"))
8064 with_fdi = false;
8065
8066 mutex_lock(&dev_priv->dpio_lock);
8067
8068 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8069 tmp &= ~SBI_SSCCTL_DISABLE;
8070 tmp |= SBI_SSCCTL_PATHALT;
8071 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8072
8073 udelay(24);
8074
8075 if (with_spread) {
8076 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8077 tmp &= ~SBI_SSCCTL_PATHALT;
8078 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8079
8080 if (with_fdi) {
8081 lpt_reset_fdi_mphy(dev_priv);
8082 lpt_program_fdi_mphy(dev_priv);
8083 }
8084 }
8085
8086 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8087 SBI_GEN0 : SBI_DBUFF0;
8088 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8089 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8090 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8091
8092 mutex_unlock(&dev_priv->dpio_lock);
8093 }
8094
8095 /* Sequence to disable CLKOUT_DP */
8096 static void lpt_disable_clkout_dp(struct drm_device *dev)
8097 {
8098 struct drm_i915_private *dev_priv = dev->dev_private;
8099 uint32_t reg, tmp;
8100
8101 mutex_lock(&dev_priv->dpio_lock);
8102
8103 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8104 SBI_GEN0 : SBI_DBUFF0;
8105 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8106 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8107 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8108
8109 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8110 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8111 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8112 tmp |= SBI_SSCCTL_PATHALT;
8113 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8114 udelay(32);
8115 }
8116 tmp |= SBI_SSCCTL_DISABLE;
8117 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8118 }
8119
8120 mutex_unlock(&dev_priv->dpio_lock);
8121 }
8122
8123 static void lpt_init_pch_refclk(struct drm_device *dev)
8124 {
8125 struct intel_encoder *encoder;
8126 bool has_vga = false;
8127
8128 for_each_intel_encoder(dev, encoder) {
8129 switch (encoder->type) {
8130 case INTEL_OUTPUT_ANALOG:
8131 has_vga = true;
8132 break;
8133 default:
8134 break;
8135 }
8136 }
8137
8138 if (has_vga)
8139 lpt_enable_clkout_dp(dev, true, true);
8140 else
8141 lpt_disable_clkout_dp(dev);
8142 }
8143
8144 /*
8145 * Initialize reference clocks when the driver loads
8146 */
8147 void intel_init_pch_refclk(struct drm_device *dev)
8148 {
8149 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8150 ironlake_init_pch_refclk(dev);
8151 else if (HAS_PCH_LPT(dev))
8152 lpt_init_pch_refclk(dev);
8153 }
8154
8155 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8156 {
8157 struct drm_device *dev = crtc_state->base.crtc->dev;
8158 struct drm_i915_private *dev_priv = dev->dev_private;
8159 struct drm_atomic_state *state = crtc_state->base.state;
8160 struct drm_connector *connector;
8161 struct drm_connector_state *connector_state;
8162 struct intel_encoder *encoder;
8163 int num_connectors = 0, i;
8164 bool is_lvds = false;
8165
8166 for_each_connector_in_state(state, connector, connector_state, i) {
8167 if (connector_state->crtc != crtc_state->base.crtc)
8168 continue;
8169
8170 encoder = to_intel_encoder(connector_state->best_encoder);
8171
8172 switch (encoder->type) {
8173 case INTEL_OUTPUT_LVDS:
8174 is_lvds = true;
8175 break;
8176 default:
8177 break;
8178 }
8179 num_connectors++;
8180 }
8181
8182 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8183 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8184 dev_priv->vbt.lvds_ssc_freq);
8185 return dev_priv->vbt.lvds_ssc_freq;
8186 }
8187
8188 return 120000;
8189 }
8190
8191 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8192 {
8193 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8194 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8195 int pipe = intel_crtc->pipe;
8196 uint32_t val;
8197
8198 val = 0;
8199
8200 switch (intel_crtc->config->pipe_bpp) {
8201 case 18:
8202 val |= PIPECONF_6BPC;
8203 break;
8204 case 24:
8205 val |= PIPECONF_8BPC;
8206 break;
8207 case 30:
8208 val |= PIPECONF_10BPC;
8209 break;
8210 case 36:
8211 val |= PIPECONF_12BPC;
8212 break;
8213 default:
8214 /* Case prevented by intel_choose_pipe_bpp_dither. */
8215 BUG();
8216 }
8217
8218 if (intel_crtc->config->dither)
8219 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8220
8221 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8222 val |= PIPECONF_INTERLACED_ILK;
8223 else
8224 val |= PIPECONF_PROGRESSIVE;
8225
8226 if (intel_crtc->config->limited_color_range)
8227 val |= PIPECONF_COLOR_RANGE_SELECT;
8228
8229 I915_WRITE(PIPECONF(pipe), val);
8230 POSTING_READ(PIPECONF(pipe));
8231 }
8232
8233 /*
8234 * Set up the pipe CSC unit.
8235 *
8236 * Currently only full range RGB to limited range RGB conversion
8237 * is supported, but eventually this should handle various
8238 * RGB<->YCbCr scenarios as well.
8239 */
8240 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8241 {
8242 struct drm_device *dev = crtc->dev;
8243 struct drm_i915_private *dev_priv = dev->dev_private;
8244 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8245 int pipe = intel_crtc->pipe;
8246 uint16_t coeff = 0x7800; /* 1.0 */
8247
8248 /*
8249 * TODO: Check what kind of values actually come out of the pipe
8250 * with these coeff/postoff values and adjust to get the best
8251 * accuracy. Perhaps we even need to take the bpc value into
8252 * consideration.
8253 */
8254
8255 if (intel_crtc->config->limited_color_range)
8256 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8257
8258 /*
8259 * GY/GU and RY/RU should be the other way around according
8260 * to BSpec, but reality doesn't agree. Just set them up in
8261 * a way that results in the correct picture.
8262 */
8263 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8264 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8265
8266 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8267 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8268
8269 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8270 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8271
8272 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8273 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8274 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8275
8276 if (INTEL_INFO(dev)->gen > 6) {
8277 uint16_t postoff = 0;
8278
8279 if (intel_crtc->config->limited_color_range)
8280 postoff = (16 * (1 << 12) / 255) & 0x1fff;
8281
8282 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8283 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8284 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8285
8286 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8287 } else {
8288 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8289
8290 if (intel_crtc->config->limited_color_range)
8291 mode |= CSC_BLACK_SCREEN_OFFSET;
8292
8293 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8294 }
8295 }
8296
8297 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8298 {
8299 struct drm_device *dev = crtc->dev;
8300 struct drm_i915_private *dev_priv = dev->dev_private;
8301 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8302 enum pipe pipe = intel_crtc->pipe;
8303 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8304 uint32_t val;
8305
8306 val = 0;
8307
8308 if (IS_HASWELL(dev) && intel_crtc->config->dither)
8309 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8310
8311 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8312 val |= PIPECONF_INTERLACED_ILK;
8313 else
8314 val |= PIPECONF_PROGRESSIVE;
8315
8316 I915_WRITE(PIPECONF(cpu_transcoder), val);
8317 POSTING_READ(PIPECONF(cpu_transcoder));
8318
8319 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8320 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8321
8322 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8323 val = 0;
8324
8325 switch (intel_crtc->config->pipe_bpp) {
8326 case 18:
8327 val |= PIPEMISC_DITHER_6_BPC;
8328 break;
8329 case 24:
8330 val |= PIPEMISC_DITHER_8_BPC;
8331 break;
8332 case 30:
8333 val |= PIPEMISC_DITHER_10_BPC;
8334 break;
8335 case 36:
8336 val |= PIPEMISC_DITHER_12_BPC;
8337 break;
8338 default:
8339 /* Case prevented by pipe_config_set_bpp. */
8340 BUG();
8341 }
8342
8343 if (intel_crtc->config->dither)
8344 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8345
8346 I915_WRITE(PIPEMISC(pipe), val);
8347 }
8348 }
8349
8350 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8351 struct intel_crtc_state *crtc_state,
8352 intel_clock_t *clock,
8353 bool *has_reduced_clock,
8354 intel_clock_t *reduced_clock)
8355 {
8356 struct drm_device *dev = crtc->dev;
8357 struct drm_i915_private *dev_priv = dev->dev_private;
8358 int refclk;
8359 const intel_limit_t *limit;
8360 bool ret, is_lvds = false;
8361
8362 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
8363
8364 refclk = ironlake_get_refclk(crtc_state);
8365
8366 /*
8367 * Returns a set of divisors for the desired target clock with the given
8368 * refclk, or FALSE. The returned values represent the clock equation:
8369 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8370 */
8371 limit = intel_limit(crtc_state, refclk);
8372 ret = dev_priv->display.find_dpll(limit, crtc_state,
8373 crtc_state->port_clock,
8374 refclk, NULL, clock);
8375 if (!ret)
8376 return false;
8377
8378 if (is_lvds && dev_priv->lvds_downclock_avail) {
8379 /*
8380 * Ensure we match the reduced clock's P to the target clock.
8381 * If the clocks don't match, we can't switch the display clock
8382 * by using the FP0/FP1. In such case we will disable the LVDS
8383 * downclock feature.
8384 */
8385 *has_reduced_clock =
8386 dev_priv->display.find_dpll(limit, crtc_state,
8387 dev_priv->lvds_downclock,
8388 refclk, clock,
8389 reduced_clock);
8390 }
8391
8392 return true;
8393 }
8394
8395 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8396 {
8397 /*
8398 * Account for spread spectrum to avoid
8399 * oversubscribing the link. Max center spread
8400 * is 2.5%; use 5% for safety's sake.
8401 */
8402 u32 bps = target_clock * bpp * 21 / 20;
8403 return DIV_ROUND_UP(bps, link_bw * 8);
8404 }
8405
8406 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8407 {
8408 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8409 }
8410
8411 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8412 struct intel_crtc_state *crtc_state,
8413 u32 *fp,
8414 intel_clock_t *reduced_clock, u32 *fp2)
8415 {
8416 struct drm_crtc *crtc = &intel_crtc->base;
8417 struct drm_device *dev = crtc->dev;
8418 struct drm_i915_private *dev_priv = dev->dev_private;
8419 struct drm_atomic_state *state = crtc_state->base.state;
8420 struct drm_connector *connector;
8421 struct drm_connector_state *connector_state;
8422 struct intel_encoder *encoder;
8423 uint32_t dpll;
8424 int factor, num_connectors = 0, i;
8425 bool is_lvds = false, is_sdvo = false;
8426
8427 for_each_connector_in_state(state, connector, connector_state, i) {
8428 if (connector_state->crtc != crtc_state->base.crtc)
8429 continue;
8430
8431 encoder = to_intel_encoder(connector_state->best_encoder);
8432
8433 switch (encoder->type) {
8434 case INTEL_OUTPUT_LVDS:
8435 is_lvds = true;
8436 break;
8437 case INTEL_OUTPUT_SDVO:
8438 case INTEL_OUTPUT_HDMI:
8439 is_sdvo = true;
8440 break;
8441 default:
8442 break;
8443 }
8444
8445 num_connectors++;
8446 }
8447
8448 /* Enable autotuning of the PLL clock (if permissible) */
8449 factor = 21;
8450 if (is_lvds) {
8451 if ((intel_panel_use_ssc(dev_priv) &&
8452 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8453 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8454 factor = 25;
8455 } else if (crtc_state->sdvo_tv_clock)
8456 factor = 20;
8457
8458 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8459 *fp |= FP_CB_TUNE;
8460
8461 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8462 *fp2 |= FP_CB_TUNE;
8463
8464 dpll = 0;
8465
8466 if (is_lvds)
8467 dpll |= DPLLB_MODE_LVDS;
8468 else
8469 dpll |= DPLLB_MODE_DAC_SERIAL;
8470
8471 dpll |= (crtc_state->pixel_multiplier - 1)
8472 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8473
8474 if (is_sdvo)
8475 dpll |= DPLL_SDVO_HIGH_SPEED;
8476 if (crtc_state->has_dp_encoder)
8477 dpll |= DPLL_SDVO_HIGH_SPEED;
8478
8479 /* compute bitmask from p1 value */
8480 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8481 /* also FPA1 */
8482 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8483
8484 switch (crtc_state->dpll.p2) {
8485 case 5:
8486 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8487 break;
8488 case 7:
8489 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8490 break;
8491 case 10:
8492 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8493 break;
8494 case 14:
8495 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8496 break;
8497 }
8498
8499 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8500 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8501 else
8502 dpll |= PLL_REF_INPUT_DREFCLK;
8503
8504 return dpll | DPLL_VCO_ENABLE;
8505 }
8506
8507 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8508 struct intel_crtc_state *crtc_state)
8509 {
8510 struct drm_device *dev = crtc->base.dev;
8511 intel_clock_t clock, reduced_clock;
8512 u32 dpll = 0, fp = 0, fp2 = 0;
8513 bool ok, has_reduced_clock = false;
8514 bool is_lvds = false;
8515 struct intel_shared_dpll *pll;
8516
8517 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8518
8519 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8520 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8521
8522 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8523 &has_reduced_clock, &reduced_clock);
8524 if (!ok && !crtc_state->clock_set) {
8525 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8526 return -EINVAL;
8527 }
8528 /* Compat-code for transition, will disappear. */
8529 if (!crtc_state->clock_set) {
8530 crtc_state->dpll.n = clock.n;
8531 crtc_state->dpll.m1 = clock.m1;
8532 crtc_state->dpll.m2 = clock.m2;
8533 crtc_state->dpll.p1 = clock.p1;
8534 crtc_state->dpll.p2 = clock.p2;
8535 }
8536
8537 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8538 if (crtc_state->has_pch_encoder) {
8539 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8540 if (has_reduced_clock)
8541 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8542
8543 dpll = ironlake_compute_dpll(crtc, crtc_state,
8544 &fp, &reduced_clock,
8545 has_reduced_clock ? &fp2 : NULL);
8546
8547 crtc_state->dpll_hw_state.dpll = dpll;
8548 crtc_state->dpll_hw_state.fp0 = fp;
8549 if (has_reduced_clock)
8550 crtc_state->dpll_hw_state.fp1 = fp2;
8551 else
8552 crtc_state->dpll_hw_state.fp1 = fp;
8553
8554 pll = intel_get_shared_dpll(crtc, crtc_state);
8555 if (pll == NULL) {
8556 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8557 pipe_name(crtc->pipe));
8558 return -EINVAL;
8559 }
8560 }
8561
8562 if (is_lvds && has_reduced_clock)
8563 crtc->lowfreq_avail = true;
8564 else
8565 crtc->lowfreq_avail = false;
8566
8567 return 0;
8568 }
8569
8570 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8571 struct intel_link_m_n *m_n)
8572 {
8573 struct drm_device *dev = crtc->base.dev;
8574 struct drm_i915_private *dev_priv = dev->dev_private;
8575 enum pipe pipe = crtc->pipe;
8576
8577 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8578 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8579 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8580 & ~TU_SIZE_MASK;
8581 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8582 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8583 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8584 }
8585
8586 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8587 enum transcoder transcoder,
8588 struct intel_link_m_n *m_n,
8589 struct intel_link_m_n *m2_n2)
8590 {
8591 struct drm_device *dev = crtc->base.dev;
8592 struct drm_i915_private *dev_priv = dev->dev_private;
8593 enum pipe pipe = crtc->pipe;
8594
8595 if (INTEL_INFO(dev)->gen >= 5) {
8596 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8597 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8598 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8599 & ~TU_SIZE_MASK;
8600 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8601 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8602 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8603 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8604 * gen < 8) and if DRRS is supported (to make sure the
8605 * registers are not unnecessarily read).
8606 */
8607 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8608 crtc->config->has_drrs) {
8609 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8610 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8611 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8612 & ~TU_SIZE_MASK;
8613 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8614 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8615 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8616 }
8617 } else {
8618 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8619 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8620 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8621 & ~TU_SIZE_MASK;
8622 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8623 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8624 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8625 }
8626 }
8627
8628 void intel_dp_get_m_n(struct intel_crtc *crtc,
8629 struct intel_crtc_state *pipe_config)
8630 {
8631 if (pipe_config->has_pch_encoder)
8632 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8633 else
8634 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8635 &pipe_config->dp_m_n,
8636 &pipe_config->dp_m2_n2);
8637 }
8638
8639 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8640 struct intel_crtc_state *pipe_config)
8641 {
8642 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8643 &pipe_config->fdi_m_n, NULL);
8644 }
8645
8646 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8647 struct intel_crtc_state *pipe_config)
8648 {
8649 struct drm_device *dev = crtc->base.dev;
8650 struct drm_i915_private *dev_priv = dev->dev_private;
8651 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8652 uint32_t ps_ctrl = 0;
8653 int id = -1;
8654 int i;
8655
8656 /* find scaler attached to this pipe */
8657 for (i = 0; i < crtc->num_scalers; i++) {
8658 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8659 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8660 id = i;
8661 pipe_config->pch_pfit.enabled = true;
8662 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8663 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8664 break;
8665 }
8666 }
8667
8668 scaler_state->scaler_id = id;
8669 if (id >= 0) {
8670 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8671 } else {
8672 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8673 }
8674 }
8675
8676 static void
8677 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8678 struct intel_initial_plane_config *plane_config)
8679 {
8680 struct drm_device *dev = crtc->base.dev;
8681 struct drm_i915_private *dev_priv = dev->dev_private;
8682 u32 val, base, offset, stride_mult, tiling;
8683 int pipe = crtc->pipe;
8684 int fourcc, pixel_format;
8685 unsigned int aligned_height;
8686 struct drm_framebuffer *fb;
8687 struct intel_framebuffer *intel_fb;
8688
8689 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8690 if (!intel_fb) {
8691 DRM_DEBUG_KMS("failed to alloc fb\n");
8692 return;
8693 }
8694
8695 fb = &intel_fb->base;
8696
8697 val = I915_READ(PLANE_CTL(pipe, 0));
8698 if (!(val & PLANE_CTL_ENABLE))
8699 goto error;
8700
8701 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8702 fourcc = skl_format_to_fourcc(pixel_format,
8703 val & PLANE_CTL_ORDER_RGBX,
8704 val & PLANE_CTL_ALPHA_MASK);
8705 fb->pixel_format = fourcc;
8706 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8707
8708 tiling = val & PLANE_CTL_TILED_MASK;
8709 switch (tiling) {
8710 case PLANE_CTL_TILED_LINEAR:
8711 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
8712 break;
8713 case PLANE_CTL_TILED_X:
8714 plane_config->tiling = I915_TILING_X;
8715 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8716 break;
8717 case PLANE_CTL_TILED_Y:
8718 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
8719 break;
8720 case PLANE_CTL_TILED_YF:
8721 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
8722 break;
8723 default:
8724 MISSING_CASE(tiling);
8725 goto error;
8726 }
8727
8728 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8729 plane_config->base = base;
8730
8731 offset = I915_READ(PLANE_OFFSET(pipe, 0));
8732
8733 val = I915_READ(PLANE_SIZE(pipe, 0));
8734 fb->height = ((val >> 16) & 0xfff) + 1;
8735 fb->width = ((val >> 0) & 0x1fff) + 1;
8736
8737 val = I915_READ(PLANE_STRIDE(pipe, 0));
8738 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
8739 fb->pixel_format);
8740 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8741
8742 aligned_height = intel_fb_align_height(dev, fb->height,
8743 fb->pixel_format,
8744 fb->modifier[0]);
8745
8746 plane_config->size = fb->pitches[0] * aligned_height;
8747
8748 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8749 pipe_name(pipe), fb->width, fb->height,
8750 fb->bits_per_pixel, base, fb->pitches[0],
8751 plane_config->size);
8752
8753 plane_config->fb = intel_fb;
8754 return;
8755
8756 error:
8757 kfree(fb);
8758 }
8759
8760 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8761 struct intel_crtc_state *pipe_config)
8762 {
8763 struct drm_device *dev = crtc->base.dev;
8764 struct drm_i915_private *dev_priv = dev->dev_private;
8765 uint32_t tmp;
8766
8767 tmp = I915_READ(PF_CTL(crtc->pipe));
8768
8769 if (tmp & PF_ENABLE) {
8770 pipe_config->pch_pfit.enabled = true;
8771 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8772 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8773
8774 /* We currently do not free assignements of panel fitters on
8775 * ivb/hsw (since we don't use the higher upscaling modes which
8776 * differentiates them) so just WARN about this case for now. */
8777 if (IS_GEN7(dev)) {
8778 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8779 PF_PIPE_SEL_IVB(crtc->pipe));
8780 }
8781 }
8782 }
8783
8784 static void
8785 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8786 struct intel_initial_plane_config *plane_config)
8787 {
8788 struct drm_device *dev = crtc->base.dev;
8789 struct drm_i915_private *dev_priv = dev->dev_private;
8790 u32 val, base, offset;
8791 int pipe = crtc->pipe;
8792 int fourcc, pixel_format;
8793 unsigned int aligned_height;
8794 struct drm_framebuffer *fb;
8795 struct intel_framebuffer *intel_fb;
8796
8797 val = I915_READ(DSPCNTR(pipe));
8798 if (!(val & DISPLAY_PLANE_ENABLE))
8799 return;
8800
8801 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8802 if (!intel_fb) {
8803 DRM_DEBUG_KMS("failed to alloc fb\n");
8804 return;
8805 }
8806
8807 fb = &intel_fb->base;
8808
8809 if (INTEL_INFO(dev)->gen >= 4) {
8810 if (val & DISPPLANE_TILED) {
8811 plane_config->tiling = I915_TILING_X;
8812 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8813 }
8814 }
8815
8816 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8817 fourcc = i9xx_format_to_fourcc(pixel_format);
8818 fb->pixel_format = fourcc;
8819 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8820
8821 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
8822 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
8823 offset = I915_READ(DSPOFFSET(pipe));
8824 } else {
8825 if (plane_config->tiling)
8826 offset = I915_READ(DSPTILEOFF(pipe));
8827 else
8828 offset = I915_READ(DSPLINOFF(pipe));
8829 }
8830 plane_config->base = base;
8831
8832 val = I915_READ(PIPESRC(pipe));
8833 fb->width = ((val >> 16) & 0xfff) + 1;
8834 fb->height = ((val >> 0) & 0xfff) + 1;
8835
8836 val = I915_READ(DSPSTRIDE(pipe));
8837 fb->pitches[0] = val & 0xffffffc0;
8838
8839 aligned_height = intel_fb_align_height(dev, fb->height,
8840 fb->pixel_format,
8841 fb->modifier[0]);
8842
8843 plane_config->size = fb->pitches[0] * aligned_height;
8844
8845 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8846 pipe_name(pipe), fb->width, fb->height,
8847 fb->bits_per_pixel, base, fb->pitches[0],
8848 plane_config->size);
8849
8850 plane_config->fb = intel_fb;
8851 }
8852
8853 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8854 struct intel_crtc_state *pipe_config)
8855 {
8856 struct drm_device *dev = crtc->base.dev;
8857 struct drm_i915_private *dev_priv = dev->dev_private;
8858 uint32_t tmp;
8859
8860 if (!intel_display_power_is_enabled(dev_priv,
8861 POWER_DOMAIN_PIPE(crtc->pipe)))
8862 return false;
8863
8864 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8865 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8866
8867 tmp = I915_READ(PIPECONF(crtc->pipe));
8868 if (!(tmp & PIPECONF_ENABLE))
8869 return false;
8870
8871 switch (tmp & PIPECONF_BPC_MASK) {
8872 case PIPECONF_6BPC:
8873 pipe_config->pipe_bpp = 18;
8874 break;
8875 case PIPECONF_8BPC:
8876 pipe_config->pipe_bpp = 24;
8877 break;
8878 case PIPECONF_10BPC:
8879 pipe_config->pipe_bpp = 30;
8880 break;
8881 case PIPECONF_12BPC:
8882 pipe_config->pipe_bpp = 36;
8883 break;
8884 default:
8885 break;
8886 }
8887
8888 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8889 pipe_config->limited_color_range = true;
8890
8891 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8892 struct intel_shared_dpll *pll;
8893
8894 pipe_config->has_pch_encoder = true;
8895
8896 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8897 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8898 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8899
8900 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8901
8902 if (HAS_PCH_IBX(dev_priv->dev)) {
8903 pipe_config->shared_dpll =
8904 (enum intel_dpll_id) crtc->pipe;
8905 } else {
8906 tmp = I915_READ(PCH_DPLL_SEL);
8907 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8908 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
8909 else
8910 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
8911 }
8912
8913 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8914
8915 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8916 &pipe_config->dpll_hw_state));
8917
8918 tmp = pipe_config->dpll_hw_state.dpll;
8919 pipe_config->pixel_multiplier =
8920 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8921 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8922
8923 ironlake_pch_clock_get(crtc, pipe_config);
8924 } else {
8925 pipe_config->pixel_multiplier = 1;
8926 }
8927
8928 intel_get_pipe_timings(crtc, pipe_config);
8929
8930 ironlake_get_pfit_config(crtc, pipe_config);
8931
8932 return true;
8933 }
8934
8935 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8936 {
8937 struct drm_device *dev = dev_priv->dev;
8938 struct intel_crtc *crtc;
8939
8940 for_each_intel_crtc(dev, crtc)
8941 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8942 pipe_name(crtc->pipe));
8943
8944 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8945 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8946 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8947 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8948 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
8949 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8950 "CPU PWM1 enabled\n");
8951 if (IS_HASWELL(dev))
8952 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8953 "CPU PWM2 enabled\n");
8954 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8955 "PCH PWM1 enabled\n");
8956 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8957 "Utility pin enabled\n");
8958 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8959
8960 /*
8961 * In theory we can still leave IRQs enabled, as long as only the HPD
8962 * interrupts remain enabled. We used to check for that, but since it's
8963 * gen-specific and since we only disable LCPLL after we fully disable
8964 * the interrupts, the check below should be enough.
8965 */
8966 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8967 }
8968
8969 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8970 {
8971 struct drm_device *dev = dev_priv->dev;
8972
8973 if (IS_HASWELL(dev))
8974 return I915_READ(D_COMP_HSW);
8975 else
8976 return I915_READ(D_COMP_BDW);
8977 }
8978
8979 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8980 {
8981 struct drm_device *dev = dev_priv->dev;
8982
8983 if (IS_HASWELL(dev)) {
8984 mutex_lock(&dev_priv->rps.hw_lock);
8985 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8986 val))
8987 DRM_ERROR("Failed to write to D_COMP\n");
8988 mutex_unlock(&dev_priv->rps.hw_lock);
8989 } else {
8990 I915_WRITE(D_COMP_BDW, val);
8991 POSTING_READ(D_COMP_BDW);
8992 }
8993 }
8994
8995 /*
8996 * This function implements pieces of two sequences from BSpec:
8997 * - Sequence for display software to disable LCPLL
8998 * - Sequence for display software to allow package C8+
8999 * The steps implemented here are just the steps that actually touch the LCPLL
9000 * register. Callers should take care of disabling all the display engine
9001 * functions, doing the mode unset, fixing interrupts, etc.
9002 */
9003 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9004 bool switch_to_fclk, bool allow_power_down)
9005 {
9006 uint32_t val;
9007
9008 assert_can_disable_lcpll(dev_priv);
9009
9010 val = I915_READ(LCPLL_CTL);
9011
9012 if (switch_to_fclk) {
9013 val |= LCPLL_CD_SOURCE_FCLK;
9014 I915_WRITE(LCPLL_CTL, val);
9015
9016 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9017 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9018 DRM_ERROR("Switching to FCLK failed\n");
9019
9020 val = I915_READ(LCPLL_CTL);
9021 }
9022
9023 val |= LCPLL_PLL_DISABLE;
9024 I915_WRITE(LCPLL_CTL, val);
9025 POSTING_READ(LCPLL_CTL);
9026
9027 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9028 DRM_ERROR("LCPLL still locked\n");
9029
9030 val = hsw_read_dcomp(dev_priv);
9031 val |= D_COMP_COMP_DISABLE;
9032 hsw_write_dcomp(dev_priv, val);
9033 ndelay(100);
9034
9035 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9036 1))
9037 DRM_ERROR("D_COMP RCOMP still in progress\n");
9038
9039 if (allow_power_down) {
9040 val = I915_READ(LCPLL_CTL);
9041 val |= LCPLL_POWER_DOWN_ALLOW;
9042 I915_WRITE(LCPLL_CTL, val);
9043 POSTING_READ(LCPLL_CTL);
9044 }
9045 }
9046
9047 /*
9048 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9049 * source.
9050 */
9051 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9052 {
9053 uint32_t val;
9054
9055 val = I915_READ(LCPLL_CTL);
9056
9057 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9058 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9059 return;
9060
9061 /*
9062 * Make sure we're not on PC8 state before disabling PC8, otherwise
9063 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9064 */
9065 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9066
9067 if (val & LCPLL_POWER_DOWN_ALLOW) {
9068 val &= ~LCPLL_POWER_DOWN_ALLOW;
9069 I915_WRITE(LCPLL_CTL, val);
9070 POSTING_READ(LCPLL_CTL);
9071 }
9072
9073 val = hsw_read_dcomp(dev_priv);
9074 val |= D_COMP_COMP_FORCE;
9075 val &= ~D_COMP_COMP_DISABLE;
9076 hsw_write_dcomp(dev_priv, val);
9077
9078 val = I915_READ(LCPLL_CTL);
9079 val &= ~LCPLL_PLL_DISABLE;
9080 I915_WRITE(LCPLL_CTL, val);
9081
9082 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9083 DRM_ERROR("LCPLL not locked yet\n");
9084
9085 if (val & LCPLL_CD_SOURCE_FCLK) {
9086 val = I915_READ(LCPLL_CTL);
9087 val &= ~LCPLL_CD_SOURCE_FCLK;
9088 I915_WRITE(LCPLL_CTL, val);
9089
9090 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9091 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9092 DRM_ERROR("Switching back to LCPLL failed\n");
9093 }
9094
9095 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9096 }
9097
9098 /*
9099 * Package states C8 and deeper are really deep PC states that can only be
9100 * reached when all the devices on the system allow it, so even if the graphics
9101 * device allows PC8+, it doesn't mean the system will actually get to these
9102 * states. Our driver only allows PC8+ when going into runtime PM.
9103 *
9104 * The requirements for PC8+ are that all the outputs are disabled, the power
9105 * well is disabled and most interrupts are disabled, and these are also
9106 * requirements for runtime PM. When these conditions are met, we manually do
9107 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9108 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9109 * hang the machine.
9110 *
9111 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9112 * the state of some registers, so when we come back from PC8+ we need to
9113 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9114 * need to take care of the registers kept by RC6. Notice that this happens even
9115 * if we don't put the device in PCI D3 state (which is what currently happens
9116 * because of the runtime PM support).
9117 *
9118 * For more, read "Display Sequences for Package C8" on the hardware
9119 * documentation.
9120 */
9121 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9122 {
9123 struct drm_device *dev = dev_priv->dev;
9124 uint32_t val;
9125
9126 DRM_DEBUG_KMS("Enabling package C8+\n");
9127
9128 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9129 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9130 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9131 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9132 }
9133
9134 lpt_disable_clkout_dp(dev);
9135 hsw_disable_lcpll(dev_priv, true, true);
9136 }
9137
9138 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9139 {
9140 struct drm_device *dev = dev_priv->dev;
9141 uint32_t val;
9142
9143 DRM_DEBUG_KMS("Disabling package C8+\n");
9144
9145 hsw_restore_lcpll(dev_priv);
9146 lpt_init_pch_refclk(dev);
9147
9148 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9149 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9150 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9151 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9152 }
9153
9154 intel_prepare_ddi(dev);
9155 }
9156
9157 static void broxton_modeset_global_resources(struct drm_atomic_state *state)
9158 {
9159 struct drm_device *dev = state->dev;
9160 struct drm_i915_private *dev_priv = dev->dev_private;
9161 int max_pixclk = intel_mode_max_pixclk(state);
9162 int req_cdclk;
9163
9164 /* see the comment in valleyview_modeset_global_resources */
9165 if (WARN_ON(max_pixclk < 0))
9166 return;
9167
9168 req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
9169
9170 if (req_cdclk != dev_priv->cdclk_freq)
9171 broxton_set_cdclk(dev, req_cdclk);
9172 }
9173
9174 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9175 struct intel_crtc_state *crtc_state)
9176 {
9177 if (!intel_ddi_pll_select(crtc, crtc_state))
9178 return -EINVAL;
9179
9180 crtc->lowfreq_avail = false;
9181
9182 return 0;
9183 }
9184
9185 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9186 enum port port,
9187 struct intel_crtc_state *pipe_config)
9188 {
9189 switch (port) {
9190 case PORT_A:
9191 pipe_config->ddi_pll_sel = SKL_DPLL0;
9192 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9193 break;
9194 case PORT_B:
9195 pipe_config->ddi_pll_sel = SKL_DPLL1;
9196 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9197 break;
9198 case PORT_C:
9199 pipe_config->ddi_pll_sel = SKL_DPLL2;
9200 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9201 break;
9202 default:
9203 DRM_ERROR("Incorrect port type\n");
9204 }
9205 }
9206
9207 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9208 enum port port,
9209 struct intel_crtc_state *pipe_config)
9210 {
9211 u32 temp, dpll_ctl1;
9212
9213 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9214 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9215
9216 switch (pipe_config->ddi_pll_sel) {
9217 case SKL_DPLL0:
9218 /*
9219 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9220 * of the shared DPLL framework and thus needs to be read out
9221 * separately
9222 */
9223 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9224 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9225 break;
9226 case SKL_DPLL1:
9227 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9228 break;
9229 case SKL_DPLL2:
9230 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9231 break;
9232 case SKL_DPLL3:
9233 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9234 break;
9235 }
9236 }
9237
9238 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9239 enum port port,
9240 struct intel_crtc_state *pipe_config)
9241 {
9242 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9243
9244 switch (pipe_config->ddi_pll_sel) {
9245 case PORT_CLK_SEL_WRPLL1:
9246 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9247 break;
9248 case PORT_CLK_SEL_WRPLL2:
9249 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9250 break;
9251 }
9252 }
9253
9254 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9255 struct intel_crtc_state *pipe_config)
9256 {
9257 struct drm_device *dev = crtc->base.dev;
9258 struct drm_i915_private *dev_priv = dev->dev_private;
9259 struct intel_shared_dpll *pll;
9260 enum port port;
9261 uint32_t tmp;
9262
9263 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9264
9265 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9266
9267 if (IS_SKYLAKE(dev))
9268 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9269 else if (IS_BROXTON(dev))
9270 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9271 else
9272 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9273
9274 if (pipe_config->shared_dpll >= 0) {
9275 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9276
9277 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9278 &pipe_config->dpll_hw_state));
9279 }
9280
9281 /*
9282 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9283 * DDI E. So just check whether this pipe is wired to DDI E and whether
9284 * the PCH transcoder is on.
9285 */
9286 if (INTEL_INFO(dev)->gen < 9 &&
9287 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9288 pipe_config->has_pch_encoder = true;
9289
9290 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9291 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9292 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9293
9294 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9295 }
9296 }
9297
9298 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9299 struct intel_crtc_state *pipe_config)
9300 {
9301 struct drm_device *dev = crtc->base.dev;
9302 struct drm_i915_private *dev_priv = dev->dev_private;
9303 enum intel_display_power_domain pfit_domain;
9304 uint32_t tmp;
9305
9306 if (!intel_display_power_is_enabled(dev_priv,
9307 POWER_DOMAIN_PIPE(crtc->pipe)))
9308 return false;
9309
9310 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9311 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9312
9313 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9314 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9315 enum pipe trans_edp_pipe;
9316 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9317 default:
9318 WARN(1, "unknown pipe linked to edp transcoder\n");
9319 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9320 case TRANS_DDI_EDP_INPUT_A_ON:
9321 trans_edp_pipe = PIPE_A;
9322 break;
9323 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9324 trans_edp_pipe = PIPE_B;
9325 break;
9326 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9327 trans_edp_pipe = PIPE_C;
9328 break;
9329 }
9330
9331 if (trans_edp_pipe == crtc->pipe)
9332 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9333 }
9334
9335 if (!intel_display_power_is_enabled(dev_priv,
9336 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9337 return false;
9338
9339 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9340 if (!(tmp & PIPECONF_ENABLE))
9341 return false;
9342
9343 haswell_get_ddi_port_state(crtc, pipe_config);
9344
9345 intel_get_pipe_timings(crtc, pipe_config);
9346
9347 if (INTEL_INFO(dev)->gen >= 9) {
9348 skl_init_scalers(dev, crtc, pipe_config);
9349 }
9350
9351 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9352 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9353 if (INTEL_INFO(dev)->gen == 9)
9354 skylake_get_pfit_config(crtc, pipe_config);
9355 else if (INTEL_INFO(dev)->gen < 9)
9356 ironlake_get_pfit_config(crtc, pipe_config);
9357 else
9358 MISSING_CASE(INTEL_INFO(dev)->gen);
9359
9360 } else {
9361 pipe_config->scaler_state.scaler_id = -1;
9362 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9363 }
9364
9365 if (IS_HASWELL(dev))
9366 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9367 (I915_READ(IPS_CTL) & IPS_ENABLE);
9368
9369 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9370 pipe_config->pixel_multiplier =
9371 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9372 } else {
9373 pipe_config->pixel_multiplier = 1;
9374 }
9375
9376 return true;
9377 }
9378
9379 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9380 {
9381 struct drm_device *dev = crtc->dev;
9382 struct drm_i915_private *dev_priv = dev->dev_private;
9383 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9384 uint32_t cntl = 0, size = 0;
9385
9386 if (base) {
9387 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9388 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9389 unsigned int stride = roundup_pow_of_two(width) * 4;
9390
9391 switch (stride) {
9392 default:
9393 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9394 width, stride);
9395 stride = 256;
9396 /* fallthrough */
9397 case 256:
9398 case 512:
9399 case 1024:
9400 case 2048:
9401 break;
9402 }
9403
9404 cntl |= CURSOR_ENABLE |
9405 CURSOR_GAMMA_ENABLE |
9406 CURSOR_FORMAT_ARGB |
9407 CURSOR_STRIDE(stride);
9408
9409 size = (height << 12) | width;
9410 }
9411
9412 if (intel_crtc->cursor_cntl != 0 &&
9413 (intel_crtc->cursor_base != base ||
9414 intel_crtc->cursor_size != size ||
9415 intel_crtc->cursor_cntl != cntl)) {
9416 /* On these chipsets we can only modify the base/size/stride
9417 * whilst the cursor is disabled.
9418 */
9419 I915_WRITE(_CURACNTR, 0);
9420 POSTING_READ(_CURACNTR);
9421 intel_crtc->cursor_cntl = 0;
9422 }
9423
9424 if (intel_crtc->cursor_base != base) {
9425 I915_WRITE(_CURABASE, base);
9426 intel_crtc->cursor_base = base;
9427 }
9428
9429 if (intel_crtc->cursor_size != size) {
9430 I915_WRITE(CURSIZE, size);
9431 intel_crtc->cursor_size = size;
9432 }
9433
9434 if (intel_crtc->cursor_cntl != cntl) {
9435 I915_WRITE(_CURACNTR, cntl);
9436 POSTING_READ(_CURACNTR);
9437 intel_crtc->cursor_cntl = cntl;
9438 }
9439 }
9440
9441 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9442 {
9443 struct drm_device *dev = crtc->dev;
9444 struct drm_i915_private *dev_priv = dev->dev_private;
9445 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9446 int pipe = intel_crtc->pipe;
9447 uint32_t cntl;
9448
9449 cntl = 0;
9450 if (base) {
9451 cntl = MCURSOR_GAMMA_ENABLE;
9452 switch (intel_crtc->base.cursor->state->crtc_w) {
9453 case 64:
9454 cntl |= CURSOR_MODE_64_ARGB_AX;
9455 break;
9456 case 128:
9457 cntl |= CURSOR_MODE_128_ARGB_AX;
9458 break;
9459 case 256:
9460 cntl |= CURSOR_MODE_256_ARGB_AX;
9461 break;
9462 default:
9463 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
9464 return;
9465 }
9466 cntl |= pipe << 28; /* Connect to correct pipe */
9467
9468 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9469 cntl |= CURSOR_PIPE_CSC_ENABLE;
9470 }
9471
9472 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
9473 cntl |= CURSOR_ROTATE_180;
9474
9475 if (intel_crtc->cursor_cntl != cntl) {
9476 I915_WRITE(CURCNTR(pipe), cntl);
9477 POSTING_READ(CURCNTR(pipe));
9478 intel_crtc->cursor_cntl = cntl;
9479 }
9480
9481 /* and commit changes on next vblank */
9482 I915_WRITE(CURBASE(pipe), base);
9483 POSTING_READ(CURBASE(pipe));
9484
9485 intel_crtc->cursor_base = base;
9486 }
9487
9488 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9489 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9490 bool on)
9491 {
9492 struct drm_device *dev = crtc->dev;
9493 struct drm_i915_private *dev_priv = dev->dev_private;
9494 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9495 int pipe = intel_crtc->pipe;
9496 int x = crtc->cursor_x;
9497 int y = crtc->cursor_y;
9498 u32 base = 0, pos = 0;
9499
9500 if (on)
9501 base = intel_crtc->cursor_addr;
9502
9503 if (x >= intel_crtc->config->pipe_src_w)
9504 base = 0;
9505
9506 if (y >= intel_crtc->config->pipe_src_h)
9507 base = 0;
9508
9509 if (x < 0) {
9510 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
9511 base = 0;
9512
9513 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9514 x = -x;
9515 }
9516 pos |= x << CURSOR_X_SHIFT;
9517
9518 if (y < 0) {
9519 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
9520 base = 0;
9521
9522 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9523 y = -y;
9524 }
9525 pos |= y << CURSOR_Y_SHIFT;
9526
9527 if (base == 0 && intel_crtc->cursor_base == 0)
9528 return;
9529
9530 I915_WRITE(CURPOS(pipe), pos);
9531
9532 /* ILK+ do this automagically */
9533 if (HAS_GMCH_DISPLAY(dev) &&
9534 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
9535 base += (intel_crtc->base.cursor->state->crtc_h *
9536 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
9537 }
9538
9539 if (IS_845G(dev) || IS_I865G(dev))
9540 i845_update_cursor(crtc, base);
9541 else
9542 i9xx_update_cursor(crtc, base);
9543 }
9544
9545 static bool cursor_size_ok(struct drm_device *dev,
9546 uint32_t width, uint32_t height)
9547 {
9548 if (width == 0 || height == 0)
9549 return false;
9550
9551 /*
9552 * 845g/865g are special in that they are only limited by
9553 * the width of their cursors, the height is arbitrary up to
9554 * the precision of the register. Everything else requires
9555 * square cursors, limited to a few power-of-two sizes.
9556 */
9557 if (IS_845G(dev) || IS_I865G(dev)) {
9558 if ((width & 63) != 0)
9559 return false;
9560
9561 if (width > (IS_845G(dev) ? 64 : 512))
9562 return false;
9563
9564 if (height > 1023)
9565 return false;
9566 } else {
9567 switch (width | height) {
9568 case 256:
9569 case 128:
9570 if (IS_GEN2(dev))
9571 return false;
9572 case 64:
9573 break;
9574 default:
9575 return false;
9576 }
9577 }
9578
9579 return true;
9580 }
9581
9582 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
9583 u16 *blue, uint32_t start, uint32_t size)
9584 {
9585 int end = (start + size > 256) ? 256 : start + size, i;
9586 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9587
9588 for (i = start; i < end; i++) {
9589 intel_crtc->lut_r[i] = red[i] >> 8;
9590 intel_crtc->lut_g[i] = green[i] >> 8;
9591 intel_crtc->lut_b[i] = blue[i] >> 8;
9592 }
9593
9594 intel_crtc_load_lut(crtc);
9595 }
9596
9597 /* VESA 640x480x72Hz mode to set on the pipe */
9598 static struct drm_display_mode load_detect_mode = {
9599 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9600 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9601 };
9602
9603 struct drm_framebuffer *
9604 __intel_framebuffer_create(struct drm_device *dev,
9605 struct drm_mode_fb_cmd2 *mode_cmd,
9606 struct drm_i915_gem_object *obj)
9607 {
9608 struct intel_framebuffer *intel_fb;
9609 int ret;
9610
9611 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9612 if (!intel_fb) {
9613 drm_gem_object_unreference(&obj->base);
9614 return ERR_PTR(-ENOMEM);
9615 }
9616
9617 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
9618 if (ret)
9619 goto err;
9620
9621 return &intel_fb->base;
9622 err:
9623 drm_gem_object_unreference(&obj->base);
9624 kfree(intel_fb);
9625
9626 return ERR_PTR(ret);
9627 }
9628
9629 static struct drm_framebuffer *
9630 intel_framebuffer_create(struct drm_device *dev,
9631 struct drm_mode_fb_cmd2 *mode_cmd,
9632 struct drm_i915_gem_object *obj)
9633 {
9634 struct drm_framebuffer *fb;
9635 int ret;
9636
9637 ret = i915_mutex_lock_interruptible(dev);
9638 if (ret)
9639 return ERR_PTR(ret);
9640 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
9641 mutex_unlock(&dev->struct_mutex);
9642
9643 return fb;
9644 }
9645
9646 static u32
9647 intel_framebuffer_pitch_for_width(int width, int bpp)
9648 {
9649 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9650 return ALIGN(pitch, 64);
9651 }
9652
9653 static u32
9654 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9655 {
9656 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
9657 return PAGE_ALIGN(pitch * mode->vdisplay);
9658 }
9659
9660 static struct drm_framebuffer *
9661 intel_framebuffer_create_for_mode(struct drm_device *dev,
9662 struct drm_display_mode *mode,
9663 int depth, int bpp)
9664 {
9665 struct drm_i915_gem_object *obj;
9666 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
9667
9668 obj = i915_gem_alloc_object(dev,
9669 intel_framebuffer_size_for_mode(mode, bpp));
9670 if (obj == NULL)
9671 return ERR_PTR(-ENOMEM);
9672
9673 mode_cmd.width = mode->hdisplay;
9674 mode_cmd.height = mode->vdisplay;
9675 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9676 bpp);
9677 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
9678
9679 return intel_framebuffer_create(dev, &mode_cmd, obj);
9680 }
9681
9682 static struct drm_framebuffer *
9683 mode_fits_in_fbdev(struct drm_device *dev,
9684 struct drm_display_mode *mode)
9685 {
9686 #ifdef CONFIG_DRM_I915_FBDEV
9687 struct drm_i915_private *dev_priv = dev->dev_private;
9688 struct drm_i915_gem_object *obj;
9689 struct drm_framebuffer *fb;
9690
9691 if (!dev_priv->fbdev)
9692 return NULL;
9693
9694 if (!dev_priv->fbdev->fb)
9695 return NULL;
9696
9697 obj = dev_priv->fbdev->fb->obj;
9698 BUG_ON(!obj);
9699
9700 fb = &dev_priv->fbdev->fb->base;
9701 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9702 fb->bits_per_pixel))
9703 return NULL;
9704
9705 if (obj->base.size < mode->vdisplay * fb->pitches[0])
9706 return NULL;
9707
9708 return fb;
9709 #else
9710 return NULL;
9711 #endif
9712 }
9713
9714 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9715 struct drm_crtc *crtc,
9716 struct drm_display_mode *mode,
9717 struct drm_framebuffer *fb,
9718 int x, int y)
9719 {
9720 struct drm_plane_state *plane_state;
9721 int hdisplay, vdisplay;
9722 int ret;
9723
9724 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
9725 if (IS_ERR(plane_state))
9726 return PTR_ERR(plane_state);
9727
9728 if (mode)
9729 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
9730 else
9731 hdisplay = vdisplay = 0;
9732
9733 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
9734 if (ret)
9735 return ret;
9736 drm_atomic_set_fb_for_plane(plane_state, fb);
9737 plane_state->crtc_x = 0;
9738 plane_state->crtc_y = 0;
9739 plane_state->crtc_w = hdisplay;
9740 plane_state->crtc_h = vdisplay;
9741 plane_state->src_x = x << 16;
9742 plane_state->src_y = y << 16;
9743 plane_state->src_w = hdisplay << 16;
9744 plane_state->src_h = vdisplay << 16;
9745
9746 return 0;
9747 }
9748
9749 bool intel_get_load_detect_pipe(struct drm_connector *connector,
9750 struct drm_display_mode *mode,
9751 struct intel_load_detect_pipe *old,
9752 struct drm_modeset_acquire_ctx *ctx)
9753 {
9754 struct intel_crtc *intel_crtc;
9755 struct intel_encoder *intel_encoder =
9756 intel_attached_encoder(connector);
9757 struct drm_crtc *possible_crtc;
9758 struct drm_encoder *encoder = &intel_encoder->base;
9759 struct drm_crtc *crtc = NULL;
9760 struct drm_device *dev = encoder->dev;
9761 struct drm_framebuffer *fb;
9762 struct drm_mode_config *config = &dev->mode_config;
9763 struct drm_atomic_state *state = NULL;
9764 struct drm_connector_state *connector_state;
9765 struct intel_crtc_state *crtc_state;
9766 int ret, i = -1;
9767
9768 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9769 connector->base.id, connector->name,
9770 encoder->base.id, encoder->name);
9771
9772 retry:
9773 ret = drm_modeset_lock(&config->connection_mutex, ctx);
9774 if (ret)
9775 goto fail_unlock;
9776
9777 /*
9778 * Algorithm gets a little messy:
9779 *
9780 * - if the connector already has an assigned crtc, use it (but make
9781 * sure it's on first)
9782 *
9783 * - try to find the first unused crtc that can drive this connector,
9784 * and use that if we find one
9785 */
9786
9787 /* See if we already have a CRTC for this connector */
9788 if (encoder->crtc) {
9789 crtc = encoder->crtc;
9790
9791 ret = drm_modeset_lock(&crtc->mutex, ctx);
9792 if (ret)
9793 goto fail_unlock;
9794 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9795 if (ret)
9796 goto fail_unlock;
9797
9798 old->dpms_mode = connector->dpms;
9799 old->load_detect_temp = false;
9800
9801 /* Make sure the crtc and connector are running */
9802 if (connector->dpms != DRM_MODE_DPMS_ON)
9803 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
9804
9805 return true;
9806 }
9807
9808 /* Find an unused one (if possible) */
9809 for_each_crtc(dev, possible_crtc) {
9810 i++;
9811 if (!(encoder->possible_crtcs & (1 << i)))
9812 continue;
9813 if (possible_crtc->state->enable)
9814 continue;
9815 /* This can occur when applying the pipe A quirk on resume. */
9816 if (to_intel_crtc(possible_crtc)->new_enabled)
9817 continue;
9818
9819 crtc = possible_crtc;
9820 break;
9821 }
9822
9823 /*
9824 * If we didn't find an unused CRTC, don't use any.
9825 */
9826 if (!crtc) {
9827 DRM_DEBUG_KMS("no pipe available for load-detect\n");
9828 goto fail_unlock;
9829 }
9830
9831 ret = drm_modeset_lock(&crtc->mutex, ctx);
9832 if (ret)
9833 goto fail_unlock;
9834 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9835 if (ret)
9836 goto fail_unlock;
9837 intel_encoder->new_crtc = to_intel_crtc(crtc);
9838 to_intel_connector(connector)->new_encoder = intel_encoder;
9839
9840 intel_crtc = to_intel_crtc(crtc);
9841 intel_crtc->new_enabled = true;
9842 old->dpms_mode = connector->dpms;
9843 old->load_detect_temp = true;
9844 old->release_fb = NULL;
9845
9846 state = drm_atomic_state_alloc(dev);
9847 if (!state)
9848 return false;
9849
9850 state->acquire_ctx = ctx;
9851
9852 connector_state = drm_atomic_get_connector_state(state, connector);
9853 if (IS_ERR(connector_state)) {
9854 ret = PTR_ERR(connector_state);
9855 goto fail;
9856 }
9857
9858 connector_state->crtc = crtc;
9859 connector_state->best_encoder = &intel_encoder->base;
9860
9861 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9862 if (IS_ERR(crtc_state)) {
9863 ret = PTR_ERR(crtc_state);
9864 goto fail;
9865 }
9866
9867 crtc_state->base.enable = true;
9868
9869 if (!mode)
9870 mode = &load_detect_mode;
9871
9872 /* We need a framebuffer large enough to accommodate all accesses
9873 * that the plane may generate whilst we perform load detection.
9874 * We can not rely on the fbcon either being present (we get called
9875 * during its initialisation to detect all boot displays, or it may
9876 * not even exist) or that it is large enough to satisfy the
9877 * requested mode.
9878 */
9879 fb = mode_fits_in_fbdev(dev, mode);
9880 if (fb == NULL) {
9881 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
9882 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9883 old->release_fb = fb;
9884 } else
9885 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
9886 if (IS_ERR(fb)) {
9887 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
9888 goto fail;
9889 }
9890
9891 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
9892 if (ret)
9893 goto fail;
9894
9895 drm_mode_copy(&crtc_state->base.mode, mode);
9896
9897 if (intel_set_mode(crtc, state)) {
9898 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
9899 if (old->release_fb)
9900 old->release_fb->funcs->destroy(old->release_fb);
9901 goto fail;
9902 }
9903 crtc->primary->crtc = crtc;
9904
9905 /* let the connector get through one full cycle before testing */
9906 intel_wait_for_vblank(dev, intel_crtc->pipe);
9907 return true;
9908
9909 fail:
9910 intel_crtc->new_enabled = crtc->state->enable;
9911 fail_unlock:
9912 drm_atomic_state_free(state);
9913 state = NULL;
9914
9915 if (ret == -EDEADLK) {
9916 drm_modeset_backoff(ctx);
9917 goto retry;
9918 }
9919
9920 return false;
9921 }
9922
9923 void intel_release_load_detect_pipe(struct drm_connector *connector,
9924 struct intel_load_detect_pipe *old,
9925 struct drm_modeset_acquire_ctx *ctx)
9926 {
9927 struct drm_device *dev = connector->dev;
9928 struct intel_encoder *intel_encoder =
9929 intel_attached_encoder(connector);
9930 struct drm_encoder *encoder = &intel_encoder->base;
9931 struct drm_crtc *crtc = encoder->crtc;
9932 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9933 struct drm_atomic_state *state;
9934 struct drm_connector_state *connector_state;
9935 struct intel_crtc_state *crtc_state;
9936 int ret;
9937
9938 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9939 connector->base.id, connector->name,
9940 encoder->base.id, encoder->name);
9941
9942 if (old->load_detect_temp) {
9943 state = drm_atomic_state_alloc(dev);
9944 if (!state)
9945 goto fail;
9946
9947 state->acquire_ctx = ctx;
9948
9949 connector_state = drm_atomic_get_connector_state(state, connector);
9950 if (IS_ERR(connector_state))
9951 goto fail;
9952
9953 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9954 if (IS_ERR(crtc_state))
9955 goto fail;
9956
9957 to_intel_connector(connector)->new_encoder = NULL;
9958 intel_encoder->new_crtc = NULL;
9959 intel_crtc->new_enabled = false;
9960
9961 connector_state->best_encoder = NULL;
9962 connector_state->crtc = NULL;
9963
9964 crtc_state->base.enable = false;
9965
9966 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
9967 0, 0);
9968 if (ret)
9969 goto fail;
9970
9971 ret = intel_set_mode(crtc, state);
9972 if (ret)
9973 goto fail;
9974
9975 if (old->release_fb) {
9976 drm_framebuffer_unregister_private(old->release_fb);
9977 drm_framebuffer_unreference(old->release_fb);
9978 }
9979
9980 return;
9981 }
9982
9983 /* Switch crtc and encoder back off if necessary */
9984 if (old->dpms_mode != DRM_MODE_DPMS_ON)
9985 connector->funcs->dpms(connector, old->dpms_mode);
9986
9987 return;
9988 fail:
9989 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
9990 drm_atomic_state_free(state);
9991 }
9992
9993 static int i9xx_pll_refclk(struct drm_device *dev,
9994 const struct intel_crtc_state *pipe_config)
9995 {
9996 struct drm_i915_private *dev_priv = dev->dev_private;
9997 u32 dpll = pipe_config->dpll_hw_state.dpll;
9998
9999 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10000 return dev_priv->vbt.lvds_ssc_freq;
10001 else if (HAS_PCH_SPLIT(dev))
10002 return 120000;
10003 else if (!IS_GEN2(dev))
10004 return 96000;
10005 else
10006 return 48000;
10007 }
10008
10009 /* Returns the clock of the currently programmed mode of the given pipe. */
10010 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10011 struct intel_crtc_state *pipe_config)
10012 {
10013 struct drm_device *dev = crtc->base.dev;
10014 struct drm_i915_private *dev_priv = dev->dev_private;
10015 int pipe = pipe_config->cpu_transcoder;
10016 u32 dpll = pipe_config->dpll_hw_state.dpll;
10017 u32 fp;
10018 intel_clock_t clock;
10019 int refclk = i9xx_pll_refclk(dev, pipe_config);
10020
10021 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10022 fp = pipe_config->dpll_hw_state.fp0;
10023 else
10024 fp = pipe_config->dpll_hw_state.fp1;
10025
10026 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10027 if (IS_PINEVIEW(dev)) {
10028 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10029 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10030 } else {
10031 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10032 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10033 }
10034
10035 if (!IS_GEN2(dev)) {
10036 if (IS_PINEVIEW(dev))
10037 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10038 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10039 else
10040 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10041 DPLL_FPA01_P1_POST_DIV_SHIFT);
10042
10043 switch (dpll & DPLL_MODE_MASK) {
10044 case DPLLB_MODE_DAC_SERIAL:
10045 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10046 5 : 10;
10047 break;
10048 case DPLLB_MODE_LVDS:
10049 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10050 7 : 14;
10051 break;
10052 default:
10053 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10054 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10055 return;
10056 }
10057
10058 if (IS_PINEVIEW(dev))
10059 pineview_clock(refclk, &clock);
10060 else
10061 i9xx_clock(refclk, &clock);
10062 } else {
10063 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10064 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10065
10066 if (is_lvds) {
10067 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10068 DPLL_FPA01_P1_POST_DIV_SHIFT);
10069
10070 if (lvds & LVDS_CLKB_POWER_UP)
10071 clock.p2 = 7;
10072 else
10073 clock.p2 = 14;
10074 } else {
10075 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10076 clock.p1 = 2;
10077 else {
10078 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10079 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10080 }
10081 if (dpll & PLL_P2_DIVIDE_BY_4)
10082 clock.p2 = 4;
10083 else
10084 clock.p2 = 2;
10085 }
10086
10087 i9xx_clock(refclk, &clock);
10088 }
10089
10090 /*
10091 * This value includes pixel_multiplier. We will use
10092 * port_clock to compute adjusted_mode.crtc_clock in the
10093 * encoder's get_config() function.
10094 */
10095 pipe_config->port_clock = clock.dot;
10096 }
10097
10098 int intel_dotclock_calculate(int link_freq,
10099 const struct intel_link_m_n *m_n)
10100 {
10101 /*
10102 * The calculation for the data clock is:
10103 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10104 * But we want to avoid losing precison if possible, so:
10105 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10106 *
10107 * and the link clock is simpler:
10108 * link_clock = (m * link_clock) / n
10109 */
10110
10111 if (!m_n->link_n)
10112 return 0;
10113
10114 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10115 }
10116
10117 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10118 struct intel_crtc_state *pipe_config)
10119 {
10120 struct drm_device *dev = crtc->base.dev;
10121
10122 /* read out port_clock from the DPLL */
10123 i9xx_crtc_clock_get(crtc, pipe_config);
10124
10125 /*
10126 * This value does not include pixel_multiplier.
10127 * We will check that port_clock and adjusted_mode.crtc_clock
10128 * agree once we know their relationship in the encoder's
10129 * get_config() function.
10130 */
10131 pipe_config->base.adjusted_mode.crtc_clock =
10132 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10133 &pipe_config->fdi_m_n);
10134 }
10135
10136 /** Returns the currently programmed mode of the given pipe. */
10137 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10138 struct drm_crtc *crtc)
10139 {
10140 struct drm_i915_private *dev_priv = dev->dev_private;
10141 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10142 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10143 struct drm_display_mode *mode;
10144 struct intel_crtc_state pipe_config;
10145 int htot = I915_READ(HTOTAL(cpu_transcoder));
10146 int hsync = I915_READ(HSYNC(cpu_transcoder));
10147 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10148 int vsync = I915_READ(VSYNC(cpu_transcoder));
10149 enum pipe pipe = intel_crtc->pipe;
10150
10151 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10152 if (!mode)
10153 return NULL;
10154
10155 /*
10156 * Construct a pipe_config sufficient for getting the clock info
10157 * back out of crtc_clock_get.
10158 *
10159 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10160 * to use a real value here instead.
10161 */
10162 pipe_config.cpu_transcoder = (enum transcoder) pipe;
10163 pipe_config.pixel_multiplier = 1;
10164 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10165 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10166 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10167 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10168
10169 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10170 mode->hdisplay = (htot & 0xffff) + 1;
10171 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10172 mode->hsync_start = (hsync & 0xffff) + 1;
10173 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10174 mode->vdisplay = (vtot & 0xffff) + 1;
10175 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10176 mode->vsync_start = (vsync & 0xffff) + 1;
10177 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10178
10179 drm_mode_set_name(mode);
10180
10181 return mode;
10182 }
10183
10184 static void intel_decrease_pllclock(struct drm_crtc *crtc)
10185 {
10186 struct drm_device *dev = crtc->dev;
10187 struct drm_i915_private *dev_priv = dev->dev_private;
10188 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10189
10190 if (!HAS_GMCH_DISPLAY(dev))
10191 return;
10192
10193 if (!dev_priv->lvds_downclock_avail)
10194 return;
10195
10196 /*
10197 * Since this is called by a timer, we should never get here in
10198 * the manual case.
10199 */
10200 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
10201 int pipe = intel_crtc->pipe;
10202 int dpll_reg = DPLL(pipe);
10203 int dpll;
10204
10205 DRM_DEBUG_DRIVER("downclocking LVDS\n");
10206
10207 assert_panel_unlocked(dev_priv, pipe);
10208
10209 dpll = I915_READ(dpll_reg);
10210 dpll |= DISPLAY_RATE_SELECT_FPA1;
10211 I915_WRITE(dpll_reg, dpll);
10212 intel_wait_for_vblank(dev, pipe);
10213 dpll = I915_READ(dpll_reg);
10214 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
10215 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
10216 }
10217
10218 }
10219
10220 void intel_mark_busy(struct drm_device *dev)
10221 {
10222 struct drm_i915_private *dev_priv = dev->dev_private;
10223
10224 if (dev_priv->mm.busy)
10225 return;
10226
10227 intel_runtime_pm_get(dev_priv);
10228 i915_update_gfx_val(dev_priv);
10229 if (INTEL_INFO(dev)->gen >= 6)
10230 gen6_rps_busy(dev_priv);
10231 dev_priv->mm.busy = true;
10232 }
10233
10234 void intel_mark_idle(struct drm_device *dev)
10235 {
10236 struct drm_i915_private *dev_priv = dev->dev_private;
10237 struct drm_crtc *crtc;
10238
10239 if (!dev_priv->mm.busy)
10240 return;
10241
10242 dev_priv->mm.busy = false;
10243
10244 for_each_crtc(dev, crtc) {
10245 if (!crtc->primary->fb)
10246 continue;
10247
10248 intel_decrease_pllclock(crtc);
10249 }
10250
10251 if (INTEL_INFO(dev)->gen >= 6)
10252 gen6_rps_idle(dev->dev_private);
10253
10254 intel_runtime_pm_put(dev_priv);
10255 }
10256
10257 static void intel_crtc_set_state(struct intel_crtc *crtc,
10258 struct intel_crtc_state *crtc_state)
10259 {
10260 kfree(crtc->config);
10261 crtc->config = crtc_state;
10262 crtc->base.state = &crtc_state->base;
10263 }
10264
10265 static void intel_crtc_destroy(struct drm_crtc *crtc)
10266 {
10267 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10268 struct drm_device *dev = crtc->dev;
10269 struct intel_unpin_work *work;
10270
10271 spin_lock_irq(&dev->event_lock);
10272 work = intel_crtc->unpin_work;
10273 intel_crtc->unpin_work = NULL;
10274 spin_unlock_irq(&dev->event_lock);
10275
10276 if (work) {
10277 cancel_work_sync(&work->work);
10278 kfree(work);
10279 }
10280
10281 intel_crtc_set_state(intel_crtc, NULL);
10282 drm_crtc_cleanup(crtc);
10283
10284 kfree(intel_crtc);
10285 }
10286
10287 static void intel_unpin_work_fn(struct work_struct *__work)
10288 {
10289 struct intel_unpin_work *work =
10290 container_of(__work, struct intel_unpin_work, work);
10291 struct drm_device *dev = work->crtc->dev;
10292 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
10293
10294 mutex_lock(&dev->struct_mutex);
10295 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
10296 drm_gem_object_unreference(&work->pending_flip_obj->base);
10297
10298 intel_fbc_update(dev);
10299
10300 if (work->flip_queued_req)
10301 i915_gem_request_assign(&work->flip_queued_req, NULL);
10302 mutex_unlock(&dev->struct_mutex);
10303
10304 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
10305 drm_framebuffer_unreference(work->old_fb);
10306
10307 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
10308 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
10309
10310 kfree(work);
10311 }
10312
10313 static void do_intel_finish_page_flip(struct drm_device *dev,
10314 struct drm_crtc *crtc)
10315 {
10316 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10317 struct intel_unpin_work *work;
10318 unsigned long flags;
10319
10320 /* Ignore early vblank irqs */
10321 if (intel_crtc == NULL)
10322 return;
10323
10324 /*
10325 * This is called both by irq handlers and the reset code (to complete
10326 * lost pageflips) so needs the full irqsave spinlocks.
10327 */
10328 spin_lock_irqsave(&dev->event_lock, flags);
10329 work = intel_crtc->unpin_work;
10330
10331 /* Ensure we don't miss a work->pending update ... */
10332 smp_rmb();
10333
10334 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10335 spin_unlock_irqrestore(&dev->event_lock, flags);
10336 return;
10337 }
10338
10339 page_flip_completed(intel_crtc);
10340
10341 spin_unlock_irqrestore(&dev->event_lock, flags);
10342 }
10343
10344 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10345 {
10346 struct drm_i915_private *dev_priv = dev->dev_private;
10347 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10348
10349 do_intel_finish_page_flip(dev, crtc);
10350 }
10351
10352 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10353 {
10354 struct drm_i915_private *dev_priv = dev->dev_private;
10355 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10356
10357 do_intel_finish_page_flip(dev, crtc);
10358 }
10359
10360 /* Is 'a' after or equal to 'b'? */
10361 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10362 {
10363 return !((a - b) & 0x80000000);
10364 }
10365
10366 static bool page_flip_finished(struct intel_crtc *crtc)
10367 {
10368 struct drm_device *dev = crtc->base.dev;
10369 struct drm_i915_private *dev_priv = dev->dev_private;
10370
10371 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10372 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10373 return true;
10374
10375 /*
10376 * The relevant registers doen't exist on pre-ctg.
10377 * As the flip done interrupt doesn't trigger for mmio
10378 * flips on gmch platforms, a flip count check isn't
10379 * really needed there. But since ctg has the registers,
10380 * include it in the check anyway.
10381 */
10382 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10383 return true;
10384
10385 /*
10386 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10387 * used the same base address. In that case the mmio flip might
10388 * have completed, but the CS hasn't even executed the flip yet.
10389 *
10390 * A flip count check isn't enough as the CS might have updated
10391 * the base address just after start of vblank, but before we
10392 * managed to process the interrupt. This means we'd complete the
10393 * CS flip too soon.
10394 *
10395 * Combining both checks should get us a good enough result. It may
10396 * still happen that the CS flip has been executed, but has not
10397 * yet actually completed. But in case the base address is the same
10398 * anyway, we don't really care.
10399 */
10400 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10401 crtc->unpin_work->gtt_offset &&
10402 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10403 crtc->unpin_work->flip_count);
10404 }
10405
10406 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10407 {
10408 struct drm_i915_private *dev_priv = dev->dev_private;
10409 struct intel_crtc *intel_crtc =
10410 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10411 unsigned long flags;
10412
10413
10414 /*
10415 * This is called both by irq handlers and the reset code (to complete
10416 * lost pageflips) so needs the full irqsave spinlocks.
10417 *
10418 * NB: An MMIO update of the plane base pointer will also
10419 * generate a page-flip completion irq, i.e. every modeset
10420 * is also accompanied by a spurious intel_prepare_page_flip().
10421 */
10422 spin_lock_irqsave(&dev->event_lock, flags);
10423 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10424 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10425 spin_unlock_irqrestore(&dev->event_lock, flags);
10426 }
10427
10428 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
10429 {
10430 /* Ensure that the work item is consistent when activating it ... */
10431 smp_wmb();
10432 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10433 /* and that it is marked active as soon as the irq could fire. */
10434 smp_wmb();
10435 }
10436
10437 static int intel_gen2_queue_flip(struct drm_device *dev,
10438 struct drm_crtc *crtc,
10439 struct drm_framebuffer *fb,
10440 struct drm_i915_gem_object *obj,
10441 struct intel_engine_cs *ring,
10442 uint32_t flags)
10443 {
10444 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10445 u32 flip_mask;
10446 int ret;
10447
10448 ret = intel_ring_begin(ring, 6);
10449 if (ret)
10450 return ret;
10451
10452 /* Can't queue multiple flips, so wait for the previous
10453 * one to finish before executing the next.
10454 */
10455 if (intel_crtc->plane)
10456 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10457 else
10458 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10459 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10460 intel_ring_emit(ring, MI_NOOP);
10461 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10462 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10463 intel_ring_emit(ring, fb->pitches[0]);
10464 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10465 intel_ring_emit(ring, 0); /* aux display base address, unused */
10466
10467 intel_mark_page_flip_active(intel_crtc);
10468 __intel_ring_advance(ring);
10469 return 0;
10470 }
10471
10472 static int intel_gen3_queue_flip(struct drm_device *dev,
10473 struct drm_crtc *crtc,
10474 struct drm_framebuffer *fb,
10475 struct drm_i915_gem_object *obj,
10476 struct intel_engine_cs *ring,
10477 uint32_t flags)
10478 {
10479 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10480 u32 flip_mask;
10481 int ret;
10482
10483 ret = intel_ring_begin(ring, 6);
10484 if (ret)
10485 return ret;
10486
10487 if (intel_crtc->plane)
10488 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10489 else
10490 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10491 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10492 intel_ring_emit(ring, MI_NOOP);
10493 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10494 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10495 intel_ring_emit(ring, fb->pitches[0]);
10496 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10497 intel_ring_emit(ring, MI_NOOP);
10498
10499 intel_mark_page_flip_active(intel_crtc);
10500 __intel_ring_advance(ring);
10501 return 0;
10502 }
10503
10504 static int intel_gen4_queue_flip(struct drm_device *dev,
10505 struct drm_crtc *crtc,
10506 struct drm_framebuffer *fb,
10507 struct drm_i915_gem_object *obj,
10508 struct intel_engine_cs *ring,
10509 uint32_t flags)
10510 {
10511 struct drm_i915_private *dev_priv = dev->dev_private;
10512 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10513 uint32_t pf, pipesrc;
10514 int ret;
10515
10516 ret = intel_ring_begin(ring, 4);
10517 if (ret)
10518 return ret;
10519
10520 /* i965+ uses the linear or tiled offsets from the
10521 * Display Registers (which do not change across a page-flip)
10522 * so we need only reprogram the base address.
10523 */
10524 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10525 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10526 intel_ring_emit(ring, fb->pitches[0]);
10527 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
10528 obj->tiling_mode);
10529
10530 /* XXX Enabling the panel-fitter across page-flip is so far
10531 * untested on non-native modes, so ignore it for now.
10532 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10533 */
10534 pf = 0;
10535 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10536 intel_ring_emit(ring, pf | pipesrc);
10537
10538 intel_mark_page_flip_active(intel_crtc);
10539 __intel_ring_advance(ring);
10540 return 0;
10541 }
10542
10543 static int intel_gen6_queue_flip(struct drm_device *dev,
10544 struct drm_crtc *crtc,
10545 struct drm_framebuffer *fb,
10546 struct drm_i915_gem_object *obj,
10547 struct intel_engine_cs *ring,
10548 uint32_t flags)
10549 {
10550 struct drm_i915_private *dev_priv = dev->dev_private;
10551 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10552 uint32_t pf, pipesrc;
10553 int ret;
10554
10555 ret = intel_ring_begin(ring, 4);
10556 if (ret)
10557 return ret;
10558
10559 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10560 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10561 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
10562 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10563
10564 /* Contrary to the suggestions in the documentation,
10565 * "Enable Panel Fitter" does not seem to be required when page
10566 * flipping with a non-native mode, and worse causes a normal
10567 * modeset to fail.
10568 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10569 */
10570 pf = 0;
10571 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10572 intel_ring_emit(ring, pf | pipesrc);
10573
10574 intel_mark_page_flip_active(intel_crtc);
10575 __intel_ring_advance(ring);
10576 return 0;
10577 }
10578
10579 static int intel_gen7_queue_flip(struct drm_device *dev,
10580 struct drm_crtc *crtc,
10581 struct drm_framebuffer *fb,
10582 struct drm_i915_gem_object *obj,
10583 struct intel_engine_cs *ring,
10584 uint32_t flags)
10585 {
10586 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10587 uint32_t plane_bit = 0;
10588 int len, ret;
10589
10590 switch (intel_crtc->plane) {
10591 case PLANE_A:
10592 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10593 break;
10594 case PLANE_B:
10595 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10596 break;
10597 case PLANE_C:
10598 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10599 break;
10600 default:
10601 WARN_ONCE(1, "unknown plane in flip command\n");
10602 return -ENODEV;
10603 }
10604
10605 len = 4;
10606 if (ring->id == RCS) {
10607 len += 6;
10608 /*
10609 * On Gen 8, SRM is now taking an extra dword to accommodate
10610 * 48bits addresses, and we need a NOOP for the batch size to
10611 * stay even.
10612 */
10613 if (IS_GEN8(dev))
10614 len += 2;
10615 }
10616
10617 /*
10618 * BSpec MI_DISPLAY_FLIP for IVB:
10619 * "The full packet must be contained within the same cache line."
10620 *
10621 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10622 * cacheline, if we ever start emitting more commands before
10623 * the MI_DISPLAY_FLIP we may need to first emit everything else,
10624 * then do the cacheline alignment, and finally emit the
10625 * MI_DISPLAY_FLIP.
10626 */
10627 ret = intel_ring_cacheline_align(ring);
10628 if (ret)
10629 return ret;
10630
10631 ret = intel_ring_begin(ring, len);
10632 if (ret)
10633 return ret;
10634
10635 /* Unmask the flip-done completion message. Note that the bspec says that
10636 * we should do this for both the BCS and RCS, and that we must not unmask
10637 * more than one flip event at any time (or ensure that one flip message
10638 * can be sent by waiting for flip-done prior to queueing new flips).
10639 * Experimentation says that BCS works despite DERRMR masking all
10640 * flip-done completion events and that unmasking all planes at once
10641 * for the RCS also doesn't appear to drop events. Setting the DERRMR
10642 * to zero does lead to lockups within MI_DISPLAY_FLIP.
10643 */
10644 if (ring->id == RCS) {
10645 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
10646 intel_ring_emit(ring, DERRMR);
10647 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
10648 DERRMR_PIPEB_PRI_FLIP_DONE |
10649 DERRMR_PIPEC_PRI_FLIP_DONE));
10650 if (IS_GEN8(dev))
10651 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
10652 MI_SRM_LRM_GLOBAL_GTT);
10653 else
10654 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
10655 MI_SRM_LRM_GLOBAL_GTT);
10656 intel_ring_emit(ring, DERRMR);
10657 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
10658 if (IS_GEN8(dev)) {
10659 intel_ring_emit(ring, 0);
10660 intel_ring_emit(ring, MI_NOOP);
10661 }
10662 }
10663
10664 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
10665 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
10666 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10667 intel_ring_emit(ring, (MI_NOOP));
10668
10669 intel_mark_page_flip_active(intel_crtc);
10670 __intel_ring_advance(ring);
10671 return 0;
10672 }
10673
10674 static bool use_mmio_flip(struct intel_engine_cs *ring,
10675 struct drm_i915_gem_object *obj)
10676 {
10677 /*
10678 * This is not being used for older platforms, because
10679 * non-availability of flip done interrupt forces us to use
10680 * CS flips. Older platforms derive flip done using some clever
10681 * tricks involving the flip_pending status bits and vblank irqs.
10682 * So using MMIO flips there would disrupt this mechanism.
10683 */
10684
10685 if (ring == NULL)
10686 return true;
10687
10688 if (INTEL_INFO(ring->dev)->gen < 5)
10689 return false;
10690
10691 if (i915.use_mmio_flip < 0)
10692 return false;
10693 else if (i915.use_mmio_flip > 0)
10694 return true;
10695 else if (i915.enable_execlists)
10696 return true;
10697 else
10698 return ring != i915_gem_request_get_ring(obj->last_read_req);
10699 }
10700
10701 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
10702 {
10703 struct drm_device *dev = intel_crtc->base.dev;
10704 struct drm_i915_private *dev_priv = dev->dev_private;
10705 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
10706 const enum pipe pipe = intel_crtc->pipe;
10707 u32 ctl, stride;
10708
10709 ctl = I915_READ(PLANE_CTL(pipe, 0));
10710 ctl &= ~PLANE_CTL_TILED_MASK;
10711 switch (fb->modifier[0]) {
10712 case DRM_FORMAT_MOD_NONE:
10713 break;
10714 case I915_FORMAT_MOD_X_TILED:
10715 ctl |= PLANE_CTL_TILED_X;
10716 break;
10717 case I915_FORMAT_MOD_Y_TILED:
10718 ctl |= PLANE_CTL_TILED_Y;
10719 break;
10720 case I915_FORMAT_MOD_Yf_TILED:
10721 ctl |= PLANE_CTL_TILED_YF;
10722 break;
10723 default:
10724 MISSING_CASE(fb->modifier[0]);
10725 }
10726
10727 /*
10728 * The stride is either expressed as a multiple of 64 bytes chunks for
10729 * linear buffers or in number of tiles for tiled buffers.
10730 */
10731 stride = fb->pitches[0] /
10732 intel_fb_stride_alignment(dev, fb->modifier[0],
10733 fb->pixel_format);
10734
10735 /*
10736 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10737 * PLANE_SURF updates, the update is then guaranteed to be atomic.
10738 */
10739 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
10740 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
10741
10742 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
10743 POSTING_READ(PLANE_SURF(pipe, 0));
10744 }
10745
10746 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
10747 {
10748 struct drm_device *dev = intel_crtc->base.dev;
10749 struct drm_i915_private *dev_priv = dev->dev_private;
10750 struct intel_framebuffer *intel_fb =
10751 to_intel_framebuffer(intel_crtc->base.primary->fb);
10752 struct drm_i915_gem_object *obj = intel_fb->obj;
10753 u32 dspcntr;
10754 u32 reg;
10755
10756 reg = DSPCNTR(intel_crtc->plane);
10757 dspcntr = I915_READ(reg);
10758
10759 if (obj->tiling_mode != I915_TILING_NONE)
10760 dspcntr |= DISPPLANE_TILED;
10761 else
10762 dspcntr &= ~DISPPLANE_TILED;
10763
10764 I915_WRITE(reg, dspcntr);
10765
10766 I915_WRITE(DSPSURF(intel_crtc->plane),
10767 intel_crtc->unpin_work->gtt_offset);
10768 POSTING_READ(DSPSURF(intel_crtc->plane));
10769
10770 }
10771
10772 /*
10773 * XXX: This is the temporary way to update the plane registers until we get
10774 * around to using the usual plane update functions for MMIO flips
10775 */
10776 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
10777 {
10778 struct drm_device *dev = intel_crtc->base.dev;
10779 bool atomic_update;
10780 u32 start_vbl_count;
10781
10782 intel_mark_page_flip_active(intel_crtc);
10783
10784 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
10785
10786 if (INTEL_INFO(dev)->gen >= 9)
10787 skl_do_mmio_flip(intel_crtc);
10788 else
10789 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10790 ilk_do_mmio_flip(intel_crtc);
10791
10792 if (atomic_update)
10793 intel_pipe_update_end(intel_crtc, start_vbl_count);
10794 }
10795
10796 static void intel_mmio_flip_work_func(struct work_struct *work)
10797 {
10798 struct intel_crtc *crtc =
10799 container_of(work, struct intel_crtc, mmio_flip.work);
10800 struct intel_mmio_flip *mmio_flip;
10801
10802 mmio_flip = &crtc->mmio_flip;
10803 if (mmio_flip->req)
10804 WARN_ON(__i915_wait_request(mmio_flip->req,
10805 crtc->reset_counter,
10806 false, NULL, NULL) != 0);
10807
10808 intel_do_mmio_flip(crtc);
10809 if (mmio_flip->req) {
10810 mutex_lock(&crtc->base.dev->struct_mutex);
10811 i915_gem_request_assign(&mmio_flip->req, NULL);
10812 mutex_unlock(&crtc->base.dev->struct_mutex);
10813 }
10814 }
10815
10816 static int intel_queue_mmio_flip(struct drm_device *dev,
10817 struct drm_crtc *crtc,
10818 struct drm_framebuffer *fb,
10819 struct drm_i915_gem_object *obj,
10820 struct intel_engine_cs *ring,
10821 uint32_t flags)
10822 {
10823 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10824
10825 i915_gem_request_assign(&intel_crtc->mmio_flip.req,
10826 obj->last_write_req);
10827
10828 schedule_work(&intel_crtc->mmio_flip.work);
10829
10830 return 0;
10831 }
10832
10833 static int intel_default_queue_flip(struct drm_device *dev,
10834 struct drm_crtc *crtc,
10835 struct drm_framebuffer *fb,
10836 struct drm_i915_gem_object *obj,
10837 struct intel_engine_cs *ring,
10838 uint32_t flags)
10839 {
10840 return -ENODEV;
10841 }
10842
10843 static bool __intel_pageflip_stall_check(struct drm_device *dev,
10844 struct drm_crtc *crtc)
10845 {
10846 struct drm_i915_private *dev_priv = dev->dev_private;
10847 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10848 struct intel_unpin_work *work = intel_crtc->unpin_work;
10849 u32 addr;
10850
10851 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
10852 return true;
10853
10854 if (!work->enable_stall_check)
10855 return false;
10856
10857 if (work->flip_ready_vblank == 0) {
10858 if (work->flip_queued_req &&
10859 !i915_gem_request_completed(work->flip_queued_req, true))
10860 return false;
10861
10862 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
10863 }
10864
10865 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
10866 return false;
10867
10868 /* Potential stall - if we see that the flip has happened,
10869 * assume a missed interrupt. */
10870 if (INTEL_INFO(dev)->gen >= 4)
10871 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
10872 else
10873 addr = I915_READ(DSPADDR(intel_crtc->plane));
10874
10875 /* There is a potential issue here with a false positive after a flip
10876 * to the same address. We could address this by checking for a
10877 * non-incrementing frame counter.
10878 */
10879 return addr == work->gtt_offset;
10880 }
10881
10882 void intel_check_page_flip(struct drm_device *dev, int pipe)
10883 {
10884 struct drm_i915_private *dev_priv = dev->dev_private;
10885 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10886 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10887 struct intel_unpin_work *work;
10888
10889 WARN_ON(!in_interrupt());
10890
10891 if (crtc == NULL)
10892 return;
10893
10894 spin_lock(&dev->event_lock);
10895 work = intel_crtc->unpin_work;
10896 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
10897 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
10898 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
10899 page_flip_completed(intel_crtc);
10900 work = NULL;
10901 }
10902 if (work != NULL &&
10903 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
10904 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
10905 spin_unlock(&dev->event_lock);
10906 }
10907
10908 static int intel_crtc_page_flip(struct drm_crtc *crtc,
10909 struct drm_framebuffer *fb,
10910 struct drm_pending_vblank_event *event,
10911 uint32_t page_flip_flags)
10912 {
10913 struct drm_device *dev = crtc->dev;
10914 struct drm_i915_private *dev_priv = dev->dev_private;
10915 struct drm_framebuffer *old_fb = crtc->primary->fb;
10916 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10917 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10918 struct drm_plane *primary = crtc->primary;
10919 enum pipe pipe = intel_crtc->pipe;
10920 struct intel_unpin_work *work;
10921 struct intel_engine_cs *ring;
10922 bool mmio_flip;
10923 int ret;
10924
10925 /*
10926 * drm_mode_page_flip_ioctl() should already catch this, but double
10927 * check to be safe. In the future we may enable pageflipping from
10928 * a disabled primary plane.
10929 */
10930 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
10931 return -EBUSY;
10932
10933 /* Can't change pixel format via MI display flips. */
10934 if (fb->pixel_format != crtc->primary->fb->pixel_format)
10935 return -EINVAL;
10936
10937 /*
10938 * TILEOFF/LINOFF registers can't be changed via MI display flips.
10939 * Note that pitch changes could also affect these register.
10940 */
10941 if (INTEL_INFO(dev)->gen > 3 &&
10942 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
10943 fb->pitches[0] != crtc->primary->fb->pitches[0]))
10944 return -EINVAL;
10945
10946 if (i915_terminally_wedged(&dev_priv->gpu_error))
10947 goto out_hang;
10948
10949 work = kzalloc(sizeof(*work), GFP_KERNEL);
10950 if (work == NULL)
10951 return -ENOMEM;
10952
10953 work->event = event;
10954 work->crtc = crtc;
10955 work->old_fb = old_fb;
10956 INIT_WORK(&work->work, intel_unpin_work_fn);
10957
10958 ret = drm_crtc_vblank_get(crtc);
10959 if (ret)
10960 goto free_work;
10961
10962 /* We borrow the event spin lock for protecting unpin_work */
10963 spin_lock_irq(&dev->event_lock);
10964 if (intel_crtc->unpin_work) {
10965 /* Before declaring the flip queue wedged, check if
10966 * the hardware completed the operation behind our backs.
10967 */
10968 if (__intel_pageflip_stall_check(dev, crtc)) {
10969 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10970 page_flip_completed(intel_crtc);
10971 } else {
10972 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
10973 spin_unlock_irq(&dev->event_lock);
10974
10975 drm_crtc_vblank_put(crtc);
10976 kfree(work);
10977 return -EBUSY;
10978 }
10979 }
10980 intel_crtc->unpin_work = work;
10981 spin_unlock_irq(&dev->event_lock);
10982
10983 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
10984 flush_workqueue(dev_priv->wq);
10985
10986 /* Reference the objects for the scheduled work. */
10987 drm_framebuffer_reference(work->old_fb);
10988 drm_gem_object_reference(&obj->base);
10989
10990 crtc->primary->fb = fb;
10991 update_state_fb(crtc->primary);
10992
10993 work->pending_flip_obj = obj;
10994
10995 ret = i915_mutex_lock_interruptible(dev);
10996 if (ret)
10997 goto cleanup;
10998
10999 atomic_inc(&intel_crtc->unpin_work_count);
11000 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11001
11002 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11003 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
11004
11005 if (IS_VALLEYVIEW(dev)) {
11006 ring = &dev_priv->ring[BCS];
11007 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11008 /* vlv: DISPLAY_FLIP fails to change tiling */
11009 ring = NULL;
11010 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11011 ring = &dev_priv->ring[BCS];
11012 } else if (INTEL_INFO(dev)->gen >= 7) {
11013 ring = i915_gem_request_get_ring(obj->last_read_req);
11014 if (ring == NULL || ring->id != RCS)
11015 ring = &dev_priv->ring[BCS];
11016 } else {
11017 ring = &dev_priv->ring[RCS];
11018 }
11019
11020 mmio_flip = use_mmio_flip(ring, obj);
11021
11022 /* When using CS flips, we want to emit semaphores between rings.
11023 * However, when using mmio flips we will create a task to do the
11024 * synchronisation, so all we want here is to pin the framebuffer
11025 * into the display plane and skip any waits.
11026 */
11027 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11028 crtc->primary->state,
11029 mmio_flip ? i915_gem_request_get_ring(obj->last_read_req) : ring);
11030 if (ret)
11031 goto cleanup_pending;
11032
11033 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11034 + intel_crtc->dspaddr_offset;
11035
11036 if (mmio_flip) {
11037 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11038 page_flip_flags);
11039 if (ret)
11040 goto cleanup_unpin;
11041
11042 i915_gem_request_assign(&work->flip_queued_req,
11043 obj->last_write_req);
11044 } else {
11045 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
11046 page_flip_flags);
11047 if (ret)
11048 goto cleanup_unpin;
11049
11050 i915_gem_request_assign(&work->flip_queued_req,
11051 intel_ring_get_request(ring));
11052 }
11053
11054 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11055 work->enable_stall_check = true;
11056
11057 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11058 INTEL_FRONTBUFFER_PRIMARY(pipe));
11059
11060 intel_fbc_disable(dev);
11061 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
11062 mutex_unlock(&dev->struct_mutex);
11063
11064 trace_i915_flip_request(intel_crtc->plane, obj);
11065
11066 return 0;
11067
11068 cleanup_unpin:
11069 intel_unpin_fb_obj(fb, crtc->primary->state);
11070 cleanup_pending:
11071 atomic_dec(&intel_crtc->unpin_work_count);
11072 mutex_unlock(&dev->struct_mutex);
11073 cleanup:
11074 crtc->primary->fb = old_fb;
11075 update_state_fb(crtc->primary);
11076
11077 drm_gem_object_unreference_unlocked(&obj->base);
11078 drm_framebuffer_unreference(work->old_fb);
11079
11080 spin_lock_irq(&dev->event_lock);
11081 intel_crtc->unpin_work = NULL;
11082 spin_unlock_irq(&dev->event_lock);
11083
11084 drm_crtc_vblank_put(crtc);
11085 free_work:
11086 kfree(work);
11087
11088 if (ret == -EIO) {
11089 out_hang:
11090 ret = intel_plane_restore(primary);
11091 if (ret == 0 && event) {
11092 spin_lock_irq(&dev->event_lock);
11093 drm_send_vblank_event(dev, pipe, event);
11094 spin_unlock_irq(&dev->event_lock);
11095 }
11096 }
11097 return ret;
11098 }
11099
11100 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11101 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11102 .load_lut = intel_crtc_load_lut,
11103 .atomic_begin = intel_begin_crtc_commit,
11104 .atomic_flush = intel_finish_crtc_commit,
11105 };
11106
11107 /**
11108 * intel_modeset_update_staged_output_state
11109 *
11110 * Updates the staged output configuration state, e.g. after we've read out the
11111 * current hw state.
11112 */
11113 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
11114 {
11115 struct intel_crtc *crtc;
11116 struct intel_encoder *encoder;
11117 struct intel_connector *connector;
11118
11119 for_each_intel_connector(dev, connector) {
11120 connector->new_encoder =
11121 to_intel_encoder(connector->base.encoder);
11122 }
11123
11124 for_each_intel_encoder(dev, encoder) {
11125 encoder->new_crtc =
11126 to_intel_crtc(encoder->base.crtc);
11127 }
11128
11129 for_each_intel_crtc(dev, crtc) {
11130 crtc->new_enabled = crtc->base.state->enable;
11131 }
11132 }
11133
11134 /* Transitional helper to copy current connector/encoder state to
11135 * connector->state. This is needed so that code that is partially
11136 * converted to atomic does the right thing.
11137 */
11138 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11139 {
11140 struct intel_connector *connector;
11141
11142 for_each_intel_connector(dev, connector) {
11143 if (connector->base.encoder) {
11144 connector->base.state->best_encoder =
11145 connector->base.encoder;
11146 connector->base.state->crtc =
11147 connector->base.encoder->crtc;
11148 } else {
11149 connector->base.state->best_encoder = NULL;
11150 connector->base.state->crtc = NULL;
11151 }
11152 }
11153 }
11154
11155 /**
11156 * intel_modeset_commit_output_state
11157 *
11158 * This function copies the stage display pipe configuration to the real one.
11159 *
11160 * FIXME: we want to replace this with a proper state swap in the future
11161 */
11162 static void intel_modeset_commit_output_state(struct drm_atomic_state *state)
11163 {
11164 struct drm_crtc *crtc;
11165 struct drm_crtc_state *crtc_state;
11166 struct drm_connector *connector;
11167 struct drm_connector_state *connector_state;
11168 struct intel_encoder *encoder;
11169 struct intel_connector *intel_connector;
11170 int i;
11171
11172 for_each_connector_in_state(state, connector, connector_state, i) {
11173 *connector->state = *connector_state;
11174
11175 connector->encoder = connector_state->best_encoder;
11176 if (connector->encoder)
11177 connector->encoder->crtc = connector_state->crtc;
11178 }
11179
11180 /* Update crtc of disabled encoders */
11181 for_each_intel_encoder(state->dev, encoder) {
11182 int num_connectors = 0;
11183
11184 for_each_intel_connector(state->dev, intel_connector)
11185 if (intel_connector->base.encoder == &encoder->base)
11186 num_connectors++;
11187
11188 if (num_connectors == 0)
11189 encoder->base.crtc = NULL;
11190 }
11191
11192 for_each_crtc_in_state(state, crtc, crtc_state, i) {
11193 crtc->state->enable = crtc_state->enable;
11194 crtc->enabled = crtc_state->enable;
11195 }
11196
11197 /* Copy the new configuration to the staged state, to keep the few
11198 * pieces of code that haven't been converted yet happy */
11199 intel_modeset_update_staged_output_state(state->dev);
11200 }
11201
11202 static void
11203 connected_sink_compute_bpp(struct intel_connector *connector,
11204 struct intel_crtc_state *pipe_config)
11205 {
11206 int bpp = pipe_config->pipe_bpp;
11207
11208 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11209 connector->base.base.id,
11210 connector->base.name);
11211
11212 /* Don't use an invalid EDID bpc value */
11213 if (connector->base.display_info.bpc &&
11214 connector->base.display_info.bpc * 3 < bpp) {
11215 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11216 bpp, connector->base.display_info.bpc*3);
11217 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11218 }
11219
11220 /* Clamp bpp to 8 on screens without EDID 1.4 */
11221 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11222 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11223 bpp);
11224 pipe_config->pipe_bpp = 24;
11225 }
11226 }
11227
11228 static int
11229 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11230 struct intel_crtc_state *pipe_config)
11231 {
11232 struct drm_device *dev = crtc->base.dev;
11233 struct drm_atomic_state *state;
11234 struct drm_connector *connector;
11235 struct drm_connector_state *connector_state;
11236 int bpp, i;
11237
11238 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11239 bpp = 10*3;
11240 else if (INTEL_INFO(dev)->gen >= 5)
11241 bpp = 12*3;
11242 else
11243 bpp = 8*3;
11244
11245
11246 pipe_config->pipe_bpp = bpp;
11247
11248 state = pipe_config->base.state;
11249
11250 /* Clamp display bpp to EDID value */
11251 for_each_connector_in_state(state, connector, connector_state, i) {
11252 if (connector_state->crtc != &crtc->base)
11253 continue;
11254
11255 connected_sink_compute_bpp(to_intel_connector(connector),
11256 pipe_config);
11257 }
11258
11259 return bpp;
11260 }
11261
11262 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11263 {
11264 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11265 "type: 0x%x flags: 0x%x\n",
11266 mode->crtc_clock,
11267 mode->crtc_hdisplay, mode->crtc_hsync_start,
11268 mode->crtc_hsync_end, mode->crtc_htotal,
11269 mode->crtc_vdisplay, mode->crtc_vsync_start,
11270 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11271 }
11272
11273 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11274 struct intel_crtc_state *pipe_config,
11275 const char *context)
11276 {
11277 struct drm_device *dev = crtc->base.dev;
11278 struct drm_plane *plane;
11279 struct intel_plane *intel_plane;
11280 struct intel_plane_state *state;
11281 struct drm_framebuffer *fb;
11282
11283 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11284 context, pipe_config, pipe_name(crtc->pipe));
11285
11286 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11287 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11288 pipe_config->pipe_bpp, pipe_config->dither);
11289 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11290 pipe_config->has_pch_encoder,
11291 pipe_config->fdi_lanes,
11292 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11293 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11294 pipe_config->fdi_m_n.tu);
11295 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11296 pipe_config->has_dp_encoder,
11297 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11298 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11299 pipe_config->dp_m_n.tu);
11300
11301 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11302 pipe_config->has_dp_encoder,
11303 pipe_config->dp_m2_n2.gmch_m,
11304 pipe_config->dp_m2_n2.gmch_n,
11305 pipe_config->dp_m2_n2.link_m,
11306 pipe_config->dp_m2_n2.link_n,
11307 pipe_config->dp_m2_n2.tu);
11308
11309 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11310 pipe_config->has_audio,
11311 pipe_config->has_infoframe);
11312
11313 DRM_DEBUG_KMS("requested mode:\n");
11314 drm_mode_debug_printmodeline(&pipe_config->base.mode);
11315 DRM_DEBUG_KMS("adjusted mode:\n");
11316 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11317 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11318 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
11319 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11320 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
11321 DRM_DEBUG_KMS("num_scalers: %d\n", crtc->num_scalers);
11322 DRM_DEBUG_KMS("scaler_users: 0x%x\n", pipe_config->scaler_state.scaler_users);
11323 DRM_DEBUG_KMS("scaler id: %d\n", pipe_config->scaler_state.scaler_id);
11324 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11325 pipe_config->gmch_pfit.control,
11326 pipe_config->gmch_pfit.pgm_ratios,
11327 pipe_config->gmch_pfit.lvds_border_bits);
11328 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11329 pipe_config->pch_pfit.pos,
11330 pipe_config->pch_pfit.size,
11331 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
11332 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
11333 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
11334
11335 DRM_DEBUG_KMS("planes on this crtc\n");
11336 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11337 intel_plane = to_intel_plane(plane);
11338 if (intel_plane->pipe != crtc->pipe)
11339 continue;
11340
11341 state = to_intel_plane_state(plane->state);
11342 fb = state->base.fb;
11343 if (!fb) {
11344 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11345 "disabled, scaler_id = %d\n",
11346 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11347 plane->base.id, intel_plane->pipe,
11348 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11349 drm_plane_index(plane), state->scaler_id);
11350 continue;
11351 }
11352
11353 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11354 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11355 plane->base.id, intel_plane->pipe,
11356 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
11357 drm_plane_index(plane));
11358 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11359 fb->base.id, fb->width, fb->height, fb->pixel_format);
11360 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11361 state->scaler_id,
11362 state->src.x1 >> 16, state->src.y1 >> 16,
11363 drm_rect_width(&state->src) >> 16,
11364 drm_rect_height(&state->src) >> 16,
11365 state->dst.x1, state->dst.y1,
11366 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
11367 }
11368 }
11369
11370 static bool encoders_cloneable(const struct intel_encoder *a,
11371 const struct intel_encoder *b)
11372 {
11373 /* masks could be asymmetric, so check both ways */
11374 return a == b || (a->cloneable & (1 << b->type) &&
11375 b->cloneable & (1 << a->type));
11376 }
11377
11378 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11379 struct intel_crtc *crtc,
11380 struct intel_encoder *encoder)
11381 {
11382 struct intel_encoder *source_encoder;
11383 struct drm_connector *connector;
11384 struct drm_connector_state *connector_state;
11385 int i;
11386
11387 for_each_connector_in_state(state, connector, connector_state, i) {
11388 if (connector_state->crtc != &crtc->base)
11389 continue;
11390
11391 source_encoder =
11392 to_intel_encoder(connector_state->best_encoder);
11393 if (!encoders_cloneable(encoder, source_encoder))
11394 return false;
11395 }
11396
11397 return true;
11398 }
11399
11400 static bool check_encoder_cloning(struct drm_atomic_state *state,
11401 struct intel_crtc *crtc)
11402 {
11403 struct intel_encoder *encoder;
11404 struct drm_connector *connector;
11405 struct drm_connector_state *connector_state;
11406 int i;
11407
11408 for_each_connector_in_state(state, connector, connector_state, i) {
11409 if (connector_state->crtc != &crtc->base)
11410 continue;
11411
11412 encoder = to_intel_encoder(connector_state->best_encoder);
11413 if (!check_single_encoder_cloning(state, crtc, encoder))
11414 return false;
11415 }
11416
11417 return true;
11418 }
11419
11420 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
11421 {
11422 struct drm_device *dev = state->dev;
11423 struct intel_encoder *encoder;
11424 struct drm_connector *connector;
11425 struct drm_connector_state *connector_state;
11426 unsigned int used_ports = 0;
11427 int i;
11428
11429 /*
11430 * Walk the connector list instead of the encoder
11431 * list to detect the problem on ddi platforms
11432 * where there's just one encoder per digital port.
11433 */
11434 for_each_connector_in_state(state, connector, connector_state, i) {
11435 if (!connector_state->best_encoder)
11436 continue;
11437
11438 encoder = to_intel_encoder(connector_state->best_encoder);
11439
11440 WARN_ON(!connector_state->crtc);
11441
11442 switch (encoder->type) {
11443 unsigned int port_mask;
11444 case INTEL_OUTPUT_UNKNOWN:
11445 if (WARN_ON(!HAS_DDI(dev)))
11446 break;
11447 case INTEL_OUTPUT_DISPLAYPORT:
11448 case INTEL_OUTPUT_HDMI:
11449 case INTEL_OUTPUT_EDP:
11450 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11451
11452 /* the same port mustn't appear more than once */
11453 if (used_ports & port_mask)
11454 return false;
11455
11456 used_ports |= port_mask;
11457 default:
11458 break;
11459 }
11460 }
11461
11462 return true;
11463 }
11464
11465 static void
11466 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11467 {
11468 struct drm_crtc_state tmp_state;
11469 struct intel_crtc_scaler_state scaler_state;
11470
11471 /* Clear only the intel specific part of the crtc state excluding scalers */
11472 tmp_state = crtc_state->base;
11473 scaler_state = crtc_state->scaler_state;
11474 memset(crtc_state, 0, sizeof *crtc_state);
11475 crtc_state->base = tmp_state;
11476 crtc_state->scaler_state = scaler_state;
11477 }
11478
11479 static int
11480 intel_modeset_pipe_config(struct drm_crtc *crtc,
11481 struct drm_atomic_state *state,
11482 struct intel_crtc_state *pipe_config)
11483 {
11484 struct intel_encoder *encoder;
11485 struct drm_connector *connector;
11486 struct drm_connector_state *connector_state;
11487 int base_bpp, ret = -EINVAL;
11488 int i;
11489 bool retry = true;
11490
11491 if (!check_encoder_cloning(state, to_intel_crtc(crtc))) {
11492 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11493 return -EINVAL;
11494 }
11495
11496 if (!check_digital_port_conflicts(state)) {
11497 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
11498 return -EINVAL;
11499 }
11500
11501 clear_intel_crtc_state(pipe_config);
11502
11503 pipe_config->cpu_transcoder =
11504 (enum transcoder) to_intel_crtc(crtc)->pipe;
11505 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
11506
11507 /*
11508 * Sanitize sync polarity flags based on requested ones. If neither
11509 * positive or negative polarity is requested, treat this as meaning
11510 * negative polarity.
11511 */
11512 if (!(pipe_config->base.adjusted_mode.flags &
11513 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
11514 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
11515
11516 if (!(pipe_config->base.adjusted_mode.flags &
11517 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
11518 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
11519
11520 /* Compute a starting value for pipe_config->pipe_bpp taking the source
11521 * plane pixel format and any sink constraints into account. Returns the
11522 * source plane bpp so that dithering can be selected on mismatches
11523 * after encoders and crtc also have had their say. */
11524 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11525 pipe_config);
11526 if (base_bpp < 0)
11527 goto fail;
11528
11529 /*
11530 * Determine the real pipe dimensions. Note that stereo modes can
11531 * increase the actual pipe size due to the frame doubling and
11532 * insertion of additional space for blanks between the frame. This
11533 * is stored in the crtc timings. We use the requested mode to do this
11534 * computation to clearly distinguish it from the adjusted mode, which
11535 * can be changed by the connectors in the below retry loop.
11536 */
11537 drm_crtc_get_hv_timing(&pipe_config->base.mode,
11538 &pipe_config->pipe_src_w,
11539 &pipe_config->pipe_src_h);
11540
11541 encoder_retry:
11542 /* Ensure the port clock defaults are reset when retrying. */
11543 pipe_config->port_clock = 0;
11544 pipe_config->pixel_multiplier = 1;
11545
11546 /* Fill in default crtc timings, allow encoders to overwrite them. */
11547 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11548 CRTC_STEREO_DOUBLE);
11549
11550 /* Pass our mode to the connectors and the CRTC to give them a chance to
11551 * adjust it according to limitations or connector properties, and also
11552 * a chance to reject the mode entirely.
11553 */
11554 for_each_connector_in_state(state, connector, connector_state, i) {
11555 if (connector_state->crtc != crtc)
11556 continue;
11557
11558 encoder = to_intel_encoder(connector_state->best_encoder);
11559
11560 if (!(encoder->compute_config(encoder, pipe_config))) {
11561 DRM_DEBUG_KMS("Encoder config failure\n");
11562 goto fail;
11563 }
11564 }
11565
11566 /* Set default port clock if not overwritten by the encoder. Needs to be
11567 * done afterwards in case the encoder adjusts the mode. */
11568 if (!pipe_config->port_clock)
11569 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
11570 * pipe_config->pixel_multiplier;
11571
11572 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
11573 if (ret < 0) {
11574 DRM_DEBUG_KMS("CRTC fixup failed\n");
11575 goto fail;
11576 }
11577
11578 if (ret == RETRY) {
11579 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11580 ret = -EINVAL;
11581 goto fail;
11582 }
11583
11584 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11585 retry = false;
11586 goto encoder_retry;
11587 }
11588
11589 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
11590 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
11591 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
11592
11593 return 0;
11594 fail:
11595 return ret;
11596 }
11597
11598 static bool intel_crtc_in_use(struct drm_crtc *crtc)
11599 {
11600 struct drm_encoder *encoder;
11601 struct drm_device *dev = crtc->dev;
11602
11603 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
11604 if (encoder->crtc == crtc)
11605 return true;
11606
11607 return false;
11608 }
11609
11610 static bool
11611 needs_modeset(struct drm_crtc_state *state)
11612 {
11613 return state->mode_changed || state->active_changed;
11614 }
11615
11616 static void
11617 intel_modeset_update_state(struct drm_atomic_state *state)
11618 {
11619 struct drm_device *dev = state->dev;
11620 struct drm_i915_private *dev_priv = dev->dev_private;
11621 struct intel_encoder *intel_encoder;
11622 struct drm_crtc *crtc;
11623 struct drm_crtc_state *crtc_state;
11624 struct drm_connector *connector;
11625 int i;
11626
11627 intel_shared_dpll_commit(dev_priv);
11628
11629 for_each_intel_encoder(dev, intel_encoder) {
11630 if (!intel_encoder->base.crtc)
11631 continue;
11632
11633 for_each_crtc_in_state(state, crtc, crtc_state, i)
11634 if (crtc == intel_encoder->base.crtc)
11635 break;
11636
11637 if (crtc != intel_encoder->base.crtc)
11638 continue;
11639
11640 if (crtc_state->enable && needs_modeset(crtc_state))
11641 intel_encoder->connectors_active = false;
11642 }
11643
11644 intel_modeset_commit_output_state(state);
11645
11646 /* Double check state. */
11647 for_each_crtc(dev, crtc) {
11648 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
11649 }
11650
11651 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11652 if (!connector->encoder || !connector->encoder->crtc)
11653 continue;
11654
11655 for_each_crtc_in_state(state, crtc, crtc_state, i)
11656 if (crtc == connector->encoder->crtc)
11657 break;
11658
11659 if (crtc != connector->encoder->crtc)
11660 continue;
11661
11662 if (crtc_state->enable && needs_modeset(crtc_state)) {
11663 struct drm_property *dpms_property =
11664 dev->mode_config.dpms_property;
11665
11666 connector->dpms = DRM_MODE_DPMS_ON;
11667 drm_object_property_set_value(&connector->base,
11668 dpms_property,
11669 DRM_MODE_DPMS_ON);
11670
11671 intel_encoder = to_intel_encoder(connector->encoder);
11672 intel_encoder->connectors_active = true;
11673 }
11674 }
11675
11676 }
11677
11678 static bool intel_fuzzy_clock_check(int clock1, int clock2)
11679 {
11680 int diff;
11681
11682 if (clock1 == clock2)
11683 return true;
11684
11685 if (!clock1 || !clock2)
11686 return false;
11687
11688 diff = abs(clock1 - clock2);
11689
11690 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11691 return true;
11692
11693 return false;
11694 }
11695
11696 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
11697 list_for_each_entry((intel_crtc), \
11698 &(dev)->mode_config.crtc_list, \
11699 base.head) \
11700 if (mask & (1 <<(intel_crtc)->pipe))
11701
11702 static bool
11703 intel_pipe_config_compare(struct drm_device *dev,
11704 struct intel_crtc_state *current_config,
11705 struct intel_crtc_state *pipe_config)
11706 {
11707 #define PIPE_CONF_CHECK_X(name) \
11708 if (current_config->name != pipe_config->name) { \
11709 DRM_ERROR("mismatch in " #name " " \
11710 "(expected 0x%08x, found 0x%08x)\n", \
11711 current_config->name, \
11712 pipe_config->name); \
11713 return false; \
11714 }
11715
11716 #define PIPE_CONF_CHECK_I(name) \
11717 if (current_config->name != pipe_config->name) { \
11718 DRM_ERROR("mismatch in " #name " " \
11719 "(expected %i, found %i)\n", \
11720 current_config->name, \
11721 pipe_config->name); \
11722 return false; \
11723 }
11724
11725 /* This is required for BDW+ where there is only one set of registers for
11726 * switching between high and low RR.
11727 * This macro can be used whenever a comparison has to be made between one
11728 * hw state and multiple sw state variables.
11729 */
11730 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
11731 if ((current_config->name != pipe_config->name) && \
11732 (current_config->alt_name != pipe_config->name)) { \
11733 DRM_ERROR("mismatch in " #name " " \
11734 "(expected %i or %i, found %i)\n", \
11735 current_config->name, \
11736 current_config->alt_name, \
11737 pipe_config->name); \
11738 return false; \
11739 }
11740
11741 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
11742 if ((current_config->name ^ pipe_config->name) & (mask)) { \
11743 DRM_ERROR("mismatch in " #name "(" #mask ") " \
11744 "(expected %i, found %i)\n", \
11745 current_config->name & (mask), \
11746 pipe_config->name & (mask)); \
11747 return false; \
11748 }
11749
11750 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11751 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11752 DRM_ERROR("mismatch in " #name " " \
11753 "(expected %i, found %i)\n", \
11754 current_config->name, \
11755 pipe_config->name); \
11756 return false; \
11757 }
11758
11759 #define PIPE_CONF_QUIRK(quirk) \
11760 ((current_config->quirks | pipe_config->quirks) & (quirk))
11761
11762 PIPE_CONF_CHECK_I(cpu_transcoder);
11763
11764 PIPE_CONF_CHECK_I(has_pch_encoder);
11765 PIPE_CONF_CHECK_I(fdi_lanes);
11766 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
11767 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
11768 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
11769 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
11770 PIPE_CONF_CHECK_I(fdi_m_n.tu);
11771
11772 PIPE_CONF_CHECK_I(has_dp_encoder);
11773
11774 if (INTEL_INFO(dev)->gen < 8) {
11775 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
11776 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
11777 PIPE_CONF_CHECK_I(dp_m_n.link_m);
11778 PIPE_CONF_CHECK_I(dp_m_n.link_n);
11779 PIPE_CONF_CHECK_I(dp_m_n.tu);
11780
11781 if (current_config->has_drrs) {
11782 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
11783 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
11784 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
11785 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
11786 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
11787 }
11788 } else {
11789 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
11790 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
11791 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
11792 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
11793 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
11794 }
11795
11796 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11797 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11798 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11799 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11800 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11801 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
11802
11803 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11804 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11805 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11806 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11807 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11808 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
11809
11810 PIPE_CONF_CHECK_I(pixel_multiplier);
11811 PIPE_CONF_CHECK_I(has_hdmi_sink);
11812 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
11813 IS_VALLEYVIEW(dev))
11814 PIPE_CONF_CHECK_I(limited_color_range);
11815 PIPE_CONF_CHECK_I(has_infoframe);
11816
11817 PIPE_CONF_CHECK_I(has_audio);
11818
11819 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11820 DRM_MODE_FLAG_INTERLACE);
11821
11822 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
11823 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11824 DRM_MODE_FLAG_PHSYNC);
11825 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11826 DRM_MODE_FLAG_NHSYNC);
11827 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11828 DRM_MODE_FLAG_PVSYNC);
11829 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11830 DRM_MODE_FLAG_NVSYNC);
11831 }
11832
11833 PIPE_CONF_CHECK_I(pipe_src_w);
11834 PIPE_CONF_CHECK_I(pipe_src_h);
11835
11836 /*
11837 * FIXME: BIOS likes to set up a cloned config with lvds+external
11838 * screen. Since we don't yet re-compute the pipe config when moving
11839 * just the lvds port away to another pipe the sw tracking won't match.
11840 *
11841 * Proper atomic modesets with recomputed global state will fix this.
11842 * Until then just don't check gmch state for inherited modes.
11843 */
11844 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
11845 PIPE_CONF_CHECK_I(gmch_pfit.control);
11846 /* pfit ratios are autocomputed by the hw on gen4+ */
11847 if (INTEL_INFO(dev)->gen < 4)
11848 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
11849 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
11850 }
11851
11852 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11853 if (current_config->pch_pfit.enabled) {
11854 PIPE_CONF_CHECK_I(pch_pfit.pos);
11855 PIPE_CONF_CHECK_I(pch_pfit.size);
11856 }
11857
11858 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11859
11860 /* BDW+ don't expose a synchronous way to read the state */
11861 if (IS_HASWELL(dev))
11862 PIPE_CONF_CHECK_I(ips_enabled);
11863
11864 PIPE_CONF_CHECK_I(double_wide);
11865
11866 PIPE_CONF_CHECK_X(ddi_pll_sel);
11867
11868 PIPE_CONF_CHECK_I(shared_dpll);
11869 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
11870 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
11871 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11872 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
11873 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
11874 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11875 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11876 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
11877
11878 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
11879 PIPE_CONF_CHECK_I(pipe_bpp);
11880
11881 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
11882 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
11883
11884 #undef PIPE_CONF_CHECK_X
11885 #undef PIPE_CONF_CHECK_I
11886 #undef PIPE_CONF_CHECK_I_ALT
11887 #undef PIPE_CONF_CHECK_FLAGS
11888 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11889 #undef PIPE_CONF_QUIRK
11890
11891 return true;
11892 }
11893
11894 static void check_wm_state(struct drm_device *dev)
11895 {
11896 struct drm_i915_private *dev_priv = dev->dev_private;
11897 struct skl_ddb_allocation hw_ddb, *sw_ddb;
11898 struct intel_crtc *intel_crtc;
11899 int plane;
11900
11901 if (INTEL_INFO(dev)->gen < 9)
11902 return;
11903
11904 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11905 sw_ddb = &dev_priv->wm.skl_hw.ddb;
11906
11907 for_each_intel_crtc(dev, intel_crtc) {
11908 struct skl_ddb_entry *hw_entry, *sw_entry;
11909 const enum pipe pipe = intel_crtc->pipe;
11910
11911 if (!intel_crtc->active)
11912 continue;
11913
11914 /* planes */
11915 for_each_plane(dev_priv, pipe, plane) {
11916 hw_entry = &hw_ddb.plane[pipe][plane];
11917 sw_entry = &sw_ddb->plane[pipe][plane];
11918
11919 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11920 continue;
11921
11922 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
11923 "(expected (%u,%u), found (%u,%u))\n",
11924 pipe_name(pipe), plane + 1,
11925 sw_entry->start, sw_entry->end,
11926 hw_entry->start, hw_entry->end);
11927 }
11928
11929 /* cursor */
11930 hw_entry = &hw_ddb.cursor[pipe];
11931 sw_entry = &sw_ddb->cursor[pipe];
11932
11933 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11934 continue;
11935
11936 DRM_ERROR("mismatch in DDB state pipe %c cursor "
11937 "(expected (%u,%u), found (%u,%u))\n",
11938 pipe_name(pipe),
11939 sw_entry->start, sw_entry->end,
11940 hw_entry->start, hw_entry->end);
11941 }
11942 }
11943
11944 static void
11945 check_connector_state(struct drm_device *dev)
11946 {
11947 struct intel_connector *connector;
11948
11949 for_each_intel_connector(dev, connector) {
11950 /* This also checks the encoder/connector hw state with the
11951 * ->get_hw_state callbacks. */
11952 intel_connector_check_state(connector);
11953
11954 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
11955 "connector's staged encoder doesn't match current encoder\n");
11956 }
11957 }
11958
11959 static void
11960 check_encoder_state(struct drm_device *dev)
11961 {
11962 struct intel_encoder *encoder;
11963 struct intel_connector *connector;
11964
11965 for_each_intel_encoder(dev, encoder) {
11966 bool enabled = false;
11967 bool active = false;
11968 enum pipe pipe, tracked_pipe;
11969
11970 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11971 encoder->base.base.id,
11972 encoder->base.name);
11973
11974 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
11975 "encoder's stage crtc doesn't match current crtc\n");
11976 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
11977 "encoder's active_connectors set, but no crtc\n");
11978
11979 for_each_intel_connector(dev, connector) {
11980 if (connector->base.encoder != &encoder->base)
11981 continue;
11982 enabled = true;
11983 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
11984 active = true;
11985 }
11986 /*
11987 * for MST connectors if we unplug the connector is gone
11988 * away but the encoder is still connected to a crtc
11989 * until a modeset happens in response to the hotplug.
11990 */
11991 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
11992 continue;
11993
11994 I915_STATE_WARN(!!encoder->base.crtc != enabled,
11995 "encoder's enabled state mismatch "
11996 "(expected %i, found %i)\n",
11997 !!encoder->base.crtc, enabled);
11998 I915_STATE_WARN(active && !encoder->base.crtc,
11999 "active encoder with no crtc\n");
12000
12001 I915_STATE_WARN(encoder->connectors_active != active,
12002 "encoder's computed active state doesn't match tracked active state "
12003 "(expected %i, found %i)\n", active, encoder->connectors_active);
12004
12005 active = encoder->get_hw_state(encoder, &pipe);
12006 I915_STATE_WARN(active != encoder->connectors_active,
12007 "encoder's hw state doesn't match sw tracking "
12008 "(expected %i, found %i)\n",
12009 encoder->connectors_active, active);
12010
12011 if (!encoder->base.crtc)
12012 continue;
12013
12014 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
12015 I915_STATE_WARN(active && pipe != tracked_pipe,
12016 "active encoder's pipe doesn't match"
12017 "(expected %i, found %i)\n",
12018 tracked_pipe, pipe);
12019
12020 }
12021 }
12022
12023 static void
12024 check_crtc_state(struct drm_device *dev)
12025 {
12026 struct drm_i915_private *dev_priv = dev->dev_private;
12027 struct intel_crtc *crtc;
12028 struct intel_encoder *encoder;
12029 struct intel_crtc_state pipe_config;
12030
12031 for_each_intel_crtc(dev, crtc) {
12032 bool enabled = false;
12033 bool active = false;
12034
12035 memset(&pipe_config, 0, sizeof(pipe_config));
12036
12037 DRM_DEBUG_KMS("[CRTC:%d]\n",
12038 crtc->base.base.id);
12039
12040 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
12041 "active crtc, but not enabled in sw tracking\n");
12042
12043 for_each_intel_encoder(dev, encoder) {
12044 if (encoder->base.crtc != &crtc->base)
12045 continue;
12046 enabled = true;
12047 if (encoder->connectors_active)
12048 active = true;
12049 }
12050
12051 I915_STATE_WARN(active != crtc->active,
12052 "crtc's computed active state doesn't match tracked active state "
12053 "(expected %i, found %i)\n", active, crtc->active);
12054 I915_STATE_WARN(enabled != crtc->base.state->enable,
12055 "crtc's computed enabled state doesn't match tracked enabled state "
12056 "(expected %i, found %i)\n", enabled,
12057 crtc->base.state->enable);
12058
12059 active = dev_priv->display.get_pipe_config(crtc,
12060 &pipe_config);
12061
12062 /* hw state is inconsistent with the pipe quirk */
12063 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12064 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12065 active = crtc->active;
12066
12067 for_each_intel_encoder(dev, encoder) {
12068 enum pipe pipe;
12069 if (encoder->base.crtc != &crtc->base)
12070 continue;
12071 if (encoder->get_hw_state(encoder, &pipe))
12072 encoder->get_config(encoder, &pipe_config);
12073 }
12074
12075 I915_STATE_WARN(crtc->active != active,
12076 "crtc active state doesn't match with hw state "
12077 "(expected %i, found %i)\n", crtc->active, active);
12078
12079 if (active &&
12080 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
12081 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12082 intel_dump_pipe_config(crtc, &pipe_config,
12083 "[hw state]");
12084 intel_dump_pipe_config(crtc, crtc->config,
12085 "[sw state]");
12086 }
12087 }
12088 }
12089
12090 static void
12091 check_shared_dpll_state(struct drm_device *dev)
12092 {
12093 struct drm_i915_private *dev_priv = dev->dev_private;
12094 struct intel_crtc *crtc;
12095 struct intel_dpll_hw_state dpll_hw_state;
12096 int i;
12097
12098 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12099 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12100 int enabled_crtcs = 0, active_crtcs = 0;
12101 bool active;
12102
12103 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12104
12105 DRM_DEBUG_KMS("%s\n", pll->name);
12106
12107 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12108
12109 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12110 "more active pll users than references: %i vs %i\n",
12111 pll->active, hweight32(pll->config.crtc_mask));
12112 I915_STATE_WARN(pll->active && !pll->on,
12113 "pll in active use but not on in sw tracking\n");
12114 I915_STATE_WARN(pll->on && !pll->active,
12115 "pll in on but not on in use in sw tracking\n");
12116 I915_STATE_WARN(pll->on != active,
12117 "pll on state mismatch (expected %i, found %i)\n",
12118 pll->on, active);
12119
12120 for_each_intel_crtc(dev, crtc) {
12121 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12122 enabled_crtcs++;
12123 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12124 active_crtcs++;
12125 }
12126 I915_STATE_WARN(pll->active != active_crtcs,
12127 "pll active crtcs mismatch (expected %i, found %i)\n",
12128 pll->active, active_crtcs);
12129 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12130 "pll enabled crtcs mismatch (expected %i, found %i)\n",
12131 hweight32(pll->config.crtc_mask), enabled_crtcs);
12132
12133 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12134 sizeof(dpll_hw_state)),
12135 "pll hw state mismatch\n");
12136 }
12137 }
12138
12139 void
12140 intel_modeset_check_state(struct drm_device *dev)
12141 {
12142 check_wm_state(dev);
12143 check_connector_state(dev);
12144 check_encoder_state(dev);
12145 check_crtc_state(dev);
12146 check_shared_dpll_state(dev);
12147 }
12148
12149 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12150 int dotclock)
12151 {
12152 /*
12153 * FDI already provided one idea for the dotclock.
12154 * Yell if the encoder disagrees.
12155 */
12156 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12157 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12158 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12159 }
12160
12161 static void update_scanline_offset(struct intel_crtc *crtc)
12162 {
12163 struct drm_device *dev = crtc->base.dev;
12164
12165 /*
12166 * The scanline counter increments at the leading edge of hsync.
12167 *
12168 * On most platforms it starts counting from vtotal-1 on the
12169 * first active line. That means the scanline counter value is
12170 * always one less than what we would expect. Ie. just after
12171 * start of vblank, which also occurs at start of hsync (on the
12172 * last active line), the scanline counter will read vblank_start-1.
12173 *
12174 * On gen2 the scanline counter starts counting from 1 instead
12175 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12176 * to keep the value positive), instead of adding one.
12177 *
12178 * On HSW+ the behaviour of the scanline counter depends on the output
12179 * type. For DP ports it behaves like most other platforms, but on HDMI
12180 * there's an extra 1 line difference. So we need to add two instead of
12181 * one to the value.
12182 */
12183 if (IS_GEN2(dev)) {
12184 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
12185 int vtotal;
12186
12187 vtotal = mode->crtc_vtotal;
12188 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12189 vtotal /= 2;
12190
12191 crtc->scanline_offset = vtotal - 1;
12192 } else if (HAS_DDI(dev) &&
12193 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12194 crtc->scanline_offset = 2;
12195 } else
12196 crtc->scanline_offset = 1;
12197 }
12198
12199 static struct intel_crtc_state *
12200 intel_modeset_compute_config(struct drm_crtc *crtc,
12201 struct drm_atomic_state *state)
12202 {
12203 struct intel_crtc_state *pipe_config;
12204 int ret = 0;
12205
12206 ret = drm_atomic_add_affected_connectors(state, crtc);
12207 if (ret)
12208 return ERR_PTR(ret);
12209
12210 ret = drm_atomic_helper_check_modeset(state->dev, state);
12211 if (ret)
12212 return ERR_PTR(ret);
12213
12214 /*
12215 * Note this needs changes when we start tracking multiple modes
12216 * and crtcs. At that point we'll need to compute the whole config
12217 * (i.e. one pipe_config for each crtc) rather than just the one
12218 * for this crtc.
12219 */
12220 pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
12221 if (IS_ERR(pipe_config))
12222 return pipe_config;
12223
12224 if (!pipe_config->base.enable)
12225 return pipe_config;
12226
12227 ret = intel_modeset_pipe_config(crtc, state, pipe_config);
12228 if (ret)
12229 return ERR_PTR(ret);
12230
12231 /* Check things that can only be changed through modeset */
12232 if (pipe_config->has_audio !=
12233 to_intel_crtc(crtc)->config->has_audio)
12234 pipe_config->base.mode_changed = true;
12235
12236 /*
12237 * Note we have an issue here with infoframes: current code
12238 * only updates them on the full mode set path per hw
12239 * requirements. So here we should be checking for any
12240 * required changes and forcing a mode set.
12241 */
12242
12243 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,"[modeset]");
12244
12245 ret = drm_atomic_helper_check_planes(state->dev, state);
12246 if (ret)
12247 return ERR_PTR(ret);
12248
12249 return pipe_config;
12250 }
12251
12252 static int __intel_set_mode_setup_plls(struct drm_atomic_state *state)
12253 {
12254 struct drm_device *dev = state->dev;
12255 struct drm_i915_private *dev_priv = to_i915(dev);
12256 unsigned clear_pipes = 0;
12257 struct intel_crtc *intel_crtc;
12258 struct intel_crtc_state *intel_crtc_state;
12259 struct drm_crtc *crtc;
12260 struct drm_crtc_state *crtc_state;
12261 int ret = 0;
12262 int i;
12263
12264 if (!dev_priv->display.crtc_compute_clock)
12265 return 0;
12266
12267 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12268 intel_crtc = to_intel_crtc(crtc);
12269
12270 if (needs_modeset(crtc_state))
12271 clear_pipes |= 1 << intel_crtc->pipe;
12272 }
12273
12274 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
12275 if (ret)
12276 goto done;
12277
12278 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12279 if (!needs_modeset(crtc_state) || !crtc_state->enable)
12280 continue;
12281
12282 intel_crtc = to_intel_crtc(crtc);
12283 intel_crtc_state = to_intel_crtc_state(crtc_state);
12284
12285 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12286 intel_crtc_state);
12287 if (ret) {
12288 intel_shared_dpll_abort_config(dev_priv);
12289 goto done;
12290 }
12291 }
12292
12293 done:
12294 return ret;
12295 }
12296
12297 /* Code that should eventually be part of atomic_check() */
12298 static int __intel_set_mode_checks(struct drm_atomic_state *state)
12299 {
12300 struct drm_device *dev = state->dev;
12301 int ret;
12302
12303 /*
12304 * See if the config requires any additional preparation, e.g.
12305 * to adjust global state with pipes off. We need to do this
12306 * here so we can get the modeset_pipe updated config for the new
12307 * mode set on this crtc. For other crtcs we need to use the
12308 * adjusted_mode bits in the crtc directly.
12309 */
12310 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
12311 ret = valleyview_modeset_global_pipes(state);
12312 if (ret)
12313 return ret;
12314 }
12315
12316 ret = __intel_set_mode_setup_plls(state);
12317 if (ret)
12318 return ret;
12319
12320 return 0;
12321 }
12322
12323 static int __intel_set_mode(struct drm_crtc *modeset_crtc,
12324 struct intel_crtc_state *pipe_config)
12325 {
12326 struct drm_device *dev = modeset_crtc->dev;
12327 struct drm_i915_private *dev_priv = dev->dev_private;
12328 struct drm_atomic_state *state = pipe_config->base.state;
12329 struct intel_crtc_state *crtc_state_copy = NULL;
12330 struct intel_crtc *intel_crtc;
12331 struct drm_crtc *crtc;
12332 struct drm_crtc_state *crtc_state;
12333 struct drm_plane *plane;
12334 struct drm_plane_state *plane_state;
12335 int ret = 0;
12336 int i;
12337
12338 ret = __intel_set_mode_checks(state);
12339 if (ret < 0)
12340 return ret;
12341
12342 crtc_state_copy = kmalloc(sizeof(*crtc_state_copy), GFP_KERNEL);
12343 if (!crtc_state_copy)
12344 return -ENOMEM;
12345
12346 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12347 if (!needs_modeset(crtc_state))
12348 continue;
12349
12350 if (!crtc_state->enable) {
12351 intel_crtc_disable(crtc);
12352 } else if (crtc->state->enable) {
12353 intel_crtc_disable_planes(crtc);
12354 dev_priv->display.crtc_disable(crtc);
12355 }
12356 }
12357
12358 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
12359 * to set it here already despite that we pass it down the callchain.
12360 *
12361 * Note we'll need to fix this up when we start tracking multiple
12362 * pipes; here we assume a single modeset_pipe and only track the
12363 * single crtc and mode.
12364 */
12365 if (pipe_config->base.enable && needs_modeset(&pipe_config->base)) {
12366 modeset_crtc->mode = pipe_config->base.mode;
12367 /* mode_set/enable/disable functions rely on a correct pipe
12368 * config. */
12369 intel_crtc_set_state(to_intel_crtc(modeset_crtc), pipe_config);
12370
12371 /*
12372 * Calculate and store various constants which
12373 * are later needed by vblank and swap-completion
12374 * timestamping. They are derived from true hwmode.
12375 */
12376 drm_calc_timestamping_constants(modeset_crtc,
12377 &pipe_config->base.adjusted_mode);
12378 }
12379
12380 /* Only after disabling all output pipelines that will be changed can we
12381 * update the the output configuration. */
12382 intel_modeset_update_state(state);
12383
12384 modeset_update_crtc_power_domains(state);
12385
12386 for_each_plane_in_state(state, plane, plane_state, i) {
12387 if (WARN_ON(plane != modeset_crtc->primary))
12388 continue;
12389
12390 /* Primary plane is disabled in intel_crtc_disable() */
12391 if (!pipe_config->base.enable)
12392 continue;
12393
12394 ret = drm_plane_helper_update(plane, plane_state->crtc,
12395 plane_state->fb,
12396 plane_state->crtc_x,
12397 plane_state->crtc_y,
12398 plane_state->crtc_w,
12399 plane_state->crtc_h,
12400 plane_state->src_x,
12401 plane_state->src_y,
12402 plane_state->src_w,
12403 plane_state->src_h);
12404 WARN_ON(ret != 0);
12405 }
12406
12407 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12408 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12409 if (!needs_modeset(crtc_state) || !crtc_state->enable)
12410 continue;
12411
12412 update_scanline_offset(to_intel_crtc(crtc));
12413
12414 dev_priv->display.crtc_enable(crtc);
12415 intel_crtc_enable_planes(crtc);
12416 }
12417
12418 /* FIXME: add subpixel order */
12419
12420 intel_crtc = to_intel_crtc(modeset_crtc);
12421
12422 /* The pipe_config will be freed with the atomic state, so
12423 * make a copy. */
12424 memcpy(crtc_state_copy, intel_crtc->config, sizeof *crtc_state_copy);
12425 intel_crtc->config = crtc_state_copy;
12426 intel_crtc->base.state = &crtc_state_copy->base;
12427
12428 drm_atomic_state_free(state);
12429
12430 return 0;
12431 }
12432
12433 static int intel_set_mode_with_config(struct drm_crtc *crtc,
12434 struct intel_crtc_state *pipe_config)
12435 {
12436 int ret;
12437
12438 ret = __intel_set_mode(crtc, pipe_config);
12439
12440 if (ret == 0)
12441 intel_modeset_check_state(crtc->dev);
12442
12443 return ret;
12444 }
12445
12446 static int intel_set_mode(struct drm_crtc *crtc,
12447 struct drm_atomic_state *state)
12448 {
12449 struct intel_crtc_state *pipe_config;
12450 int ret = 0;
12451
12452 pipe_config = intel_modeset_compute_config(crtc, state);
12453 if (IS_ERR(pipe_config)) {
12454 ret = PTR_ERR(pipe_config);
12455 goto out;
12456 }
12457
12458 ret = intel_set_mode_with_config(crtc, pipe_config);
12459 if (ret)
12460 goto out;
12461
12462 out:
12463 return ret;
12464 }
12465
12466 void intel_crtc_restore_mode(struct drm_crtc *crtc)
12467 {
12468 struct drm_device *dev = crtc->dev;
12469 struct drm_atomic_state *state;
12470 struct intel_crtc *intel_crtc;
12471 struct intel_encoder *encoder;
12472 struct intel_connector *connector;
12473 struct drm_connector_state *connector_state;
12474 struct intel_crtc_state *crtc_state;
12475 int ret;
12476
12477 state = drm_atomic_state_alloc(dev);
12478 if (!state) {
12479 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
12480 crtc->base.id);
12481 return;
12482 }
12483
12484 state->acquire_ctx = dev->mode_config.acquire_ctx;
12485
12486 /* The force restore path in the HW readout code relies on the staged
12487 * config still keeping the user requested config while the actual
12488 * state has been overwritten by the configuration read from HW. We
12489 * need to copy the staged config to the atomic state, otherwise the
12490 * mode set will just reapply the state the HW is already in. */
12491 for_each_intel_encoder(dev, encoder) {
12492 if (&encoder->new_crtc->base != crtc)
12493 continue;
12494
12495 for_each_intel_connector(dev, connector) {
12496 if (connector->new_encoder != encoder)
12497 continue;
12498
12499 connector_state = drm_atomic_get_connector_state(state, &connector->base);
12500 if (IS_ERR(connector_state)) {
12501 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
12502 connector->base.base.id,
12503 connector->base.name,
12504 PTR_ERR(connector_state));
12505 continue;
12506 }
12507
12508 connector_state->crtc = crtc;
12509 connector_state->best_encoder = &encoder->base;
12510 }
12511 }
12512
12513 for_each_intel_crtc(dev, intel_crtc) {
12514 if (intel_crtc->new_enabled == intel_crtc->base.enabled)
12515 continue;
12516
12517 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
12518 if (IS_ERR(crtc_state)) {
12519 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
12520 intel_crtc->base.base.id,
12521 PTR_ERR(crtc_state));
12522 continue;
12523 }
12524
12525 crtc_state->base.enable = intel_crtc->new_enabled;
12526
12527 if (&intel_crtc->base == crtc)
12528 drm_mode_copy(&crtc_state->base.mode, &crtc->mode);
12529 }
12530
12531 intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
12532 crtc->primary->fb, crtc->x, crtc->y);
12533
12534 ret = intel_set_mode(crtc, state);
12535 if (ret)
12536 drm_atomic_state_free(state);
12537 }
12538
12539 #undef for_each_intel_crtc_masked
12540
12541 static bool intel_connector_in_mode_set(struct intel_connector *connector,
12542 struct drm_mode_set *set)
12543 {
12544 int ro;
12545
12546 for (ro = 0; ro < set->num_connectors; ro++)
12547 if (set->connectors[ro] == &connector->base)
12548 return true;
12549
12550 return false;
12551 }
12552
12553 static int
12554 intel_modeset_stage_output_state(struct drm_device *dev,
12555 struct drm_mode_set *set,
12556 struct drm_atomic_state *state)
12557 {
12558 struct intel_connector *connector;
12559 struct drm_connector *drm_connector;
12560 struct drm_connector_state *connector_state;
12561 struct drm_crtc *crtc;
12562 struct drm_crtc_state *crtc_state;
12563 int i, ret;
12564
12565 /* The upper layers ensure that we either disable a crtc or have a list
12566 * of connectors. For paranoia, double-check this. */
12567 WARN_ON(!set->fb && (set->num_connectors != 0));
12568 WARN_ON(set->fb && (set->num_connectors == 0));
12569
12570 for_each_intel_connector(dev, connector) {
12571 bool in_mode_set = intel_connector_in_mode_set(connector, set);
12572
12573 if (!in_mode_set && connector->base.state->crtc != set->crtc)
12574 continue;
12575
12576 connector_state =
12577 drm_atomic_get_connector_state(state, &connector->base);
12578 if (IS_ERR(connector_state))
12579 return PTR_ERR(connector_state);
12580
12581 if (in_mode_set) {
12582 int pipe = to_intel_crtc(set->crtc)->pipe;
12583 connector_state->best_encoder =
12584 &intel_find_encoder(connector, pipe)->base;
12585 }
12586
12587 if (connector->base.state->crtc != set->crtc)
12588 continue;
12589
12590 /* If we disable the crtc, disable all its connectors. Also, if
12591 * the connector is on the changing crtc but not on the new
12592 * connector list, disable it. */
12593 if (!set->fb || !in_mode_set) {
12594 connector_state->best_encoder = NULL;
12595
12596 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
12597 connector->base.base.id,
12598 connector->base.name);
12599 }
12600 }
12601 /* connector->new_encoder is now updated for all connectors. */
12602
12603 for_each_connector_in_state(state, drm_connector, connector_state, i) {
12604 connector = to_intel_connector(drm_connector);
12605
12606 if (!connector_state->best_encoder) {
12607 ret = drm_atomic_set_crtc_for_connector(connector_state,
12608 NULL);
12609 if (ret)
12610 return ret;
12611
12612 continue;
12613 }
12614
12615 if (intel_connector_in_mode_set(connector, set)) {
12616 struct drm_crtc *crtc = connector->base.state->crtc;
12617
12618 /* If this connector was in a previous crtc, add it
12619 * to the state. We might need to disable it. */
12620 if (crtc) {
12621 crtc_state =
12622 drm_atomic_get_crtc_state(state, crtc);
12623 if (IS_ERR(crtc_state))
12624 return PTR_ERR(crtc_state);
12625 }
12626
12627 ret = drm_atomic_set_crtc_for_connector(connector_state,
12628 set->crtc);
12629 if (ret)
12630 return ret;
12631 }
12632
12633 /* Make sure the new CRTC will work with the encoder */
12634 if (!drm_encoder_crtc_ok(connector_state->best_encoder,
12635 connector_state->crtc)) {
12636 return -EINVAL;
12637 }
12638
12639 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
12640 connector->base.base.id,
12641 connector->base.name,
12642 connector_state->crtc->base.id);
12643
12644 if (connector_state->best_encoder != &connector->encoder->base)
12645 connector->encoder =
12646 to_intel_encoder(connector_state->best_encoder);
12647 }
12648
12649 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12650 ret = drm_atomic_add_affected_connectors(state, crtc);
12651 if (ret)
12652 return ret;
12653
12654 crtc_state->enable = drm_atomic_connectors_for_crtc(state, crtc);
12655 }
12656
12657 ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode,
12658 set->fb, set->x, set->y);
12659 if (ret)
12660 return ret;
12661
12662 crtc_state = drm_atomic_get_crtc_state(state, set->crtc);
12663 if (IS_ERR(crtc_state))
12664 return PTR_ERR(crtc_state);
12665
12666 if (set->mode)
12667 drm_mode_copy(&crtc_state->mode, set->mode);
12668
12669 if (set->num_connectors)
12670 crtc_state->active = true;
12671
12672 return 0;
12673 }
12674
12675 static bool primary_plane_visible(struct drm_crtc *crtc)
12676 {
12677 struct intel_plane_state *plane_state =
12678 to_intel_plane_state(crtc->primary->state);
12679
12680 return plane_state->visible;
12681 }
12682
12683 static int intel_crtc_set_config(struct drm_mode_set *set)
12684 {
12685 struct drm_device *dev;
12686 struct drm_atomic_state *state = NULL;
12687 struct intel_crtc_state *pipe_config;
12688 bool primary_plane_was_visible;
12689 int ret;
12690
12691 BUG_ON(!set);
12692 BUG_ON(!set->crtc);
12693 BUG_ON(!set->crtc->helper_private);
12694
12695 /* Enforce sane interface api - has been abused by the fb helper. */
12696 BUG_ON(!set->mode && set->fb);
12697 BUG_ON(set->fb && set->num_connectors == 0);
12698
12699 if (set->fb) {
12700 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
12701 set->crtc->base.id, set->fb->base.id,
12702 (int)set->num_connectors, set->x, set->y);
12703 } else {
12704 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
12705 }
12706
12707 dev = set->crtc->dev;
12708
12709 state = drm_atomic_state_alloc(dev);
12710 if (!state)
12711 return -ENOMEM;
12712
12713 state->acquire_ctx = dev->mode_config.acquire_ctx;
12714
12715 ret = intel_modeset_stage_output_state(dev, set, state);
12716 if (ret)
12717 goto out;
12718
12719 pipe_config = intel_modeset_compute_config(set->crtc, state);
12720 if (IS_ERR(pipe_config)) {
12721 ret = PTR_ERR(pipe_config);
12722 goto out;
12723 }
12724
12725 intel_update_pipe_size(to_intel_crtc(set->crtc));
12726
12727 primary_plane_was_visible = primary_plane_visible(set->crtc);
12728
12729 ret = intel_set_mode_with_config(set->crtc, pipe_config);
12730
12731 if (ret == 0 &&
12732 pipe_config->base.enable &&
12733 pipe_config->base.planes_changed &&
12734 !needs_modeset(&pipe_config->base)) {
12735 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
12736
12737 /*
12738 * We need to make sure the primary plane is re-enabled if it
12739 * has previously been turned off.
12740 */
12741 if (ret == 0 && !primary_plane_was_visible &&
12742 primary_plane_visible(set->crtc)) {
12743 WARN_ON(!intel_crtc->active);
12744 intel_post_enable_primary(set->crtc);
12745 }
12746
12747 /*
12748 * In the fastboot case this may be our only check of the
12749 * state after boot. It would be better to only do it on
12750 * the first update, but we don't have a nice way of doing that
12751 * (and really, set_config isn't used much for high freq page
12752 * flipping, so increasing its cost here shouldn't be a big
12753 * deal).
12754 */
12755 if (i915.fastboot && ret == 0)
12756 intel_modeset_check_state(set->crtc->dev);
12757 }
12758
12759 if (ret) {
12760 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
12761 set->crtc->base.id, ret);
12762 }
12763
12764 out:
12765 if (ret)
12766 drm_atomic_state_free(state);
12767 return ret;
12768 }
12769
12770 static const struct drm_crtc_funcs intel_crtc_funcs = {
12771 .gamma_set = intel_crtc_gamma_set,
12772 .set_config = intel_crtc_set_config,
12773 .destroy = intel_crtc_destroy,
12774 .page_flip = intel_crtc_page_flip,
12775 .atomic_duplicate_state = intel_crtc_duplicate_state,
12776 .atomic_destroy_state = intel_crtc_destroy_state,
12777 };
12778
12779 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
12780 struct intel_shared_dpll *pll,
12781 struct intel_dpll_hw_state *hw_state)
12782 {
12783 uint32_t val;
12784
12785 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
12786 return false;
12787
12788 val = I915_READ(PCH_DPLL(pll->id));
12789 hw_state->dpll = val;
12790 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
12791 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
12792
12793 return val & DPLL_VCO_ENABLE;
12794 }
12795
12796 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
12797 struct intel_shared_dpll *pll)
12798 {
12799 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
12800 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
12801 }
12802
12803 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
12804 struct intel_shared_dpll *pll)
12805 {
12806 /* PCH refclock must be enabled first */
12807 ibx_assert_pch_refclk_enabled(dev_priv);
12808
12809 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
12810
12811 /* Wait for the clocks to stabilize. */
12812 POSTING_READ(PCH_DPLL(pll->id));
12813 udelay(150);
12814
12815 /* The pixel multiplier can only be updated once the
12816 * DPLL is enabled and the clocks are stable.
12817 *
12818 * So write it again.
12819 */
12820 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
12821 POSTING_READ(PCH_DPLL(pll->id));
12822 udelay(200);
12823 }
12824
12825 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
12826 struct intel_shared_dpll *pll)
12827 {
12828 struct drm_device *dev = dev_priv->dev;
12829 struct intel_crtc *crtc;
12830
12831 /* Make sure no transcoder isn't still depending on us. */
12832 for_each_intel_crtc(dev, crtc) {
12833 if (intel_crtc_to_shared_dpll(crtc) == pll)
12834 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
12835 }
12836
12837 I915_WRITE(PCH_DPLL(pll->id), 0);
12838 POSTING_READ(PCH_DPLL(pll->id));
12839 udelay(200);
12840 }
12841
12842 static char *ibx_pch_dpll_names[] = {
12843 "PCH DPLL A",
12844 "PCH DPLL B",
12845 };
12846
12847 static void ibx_pch_dpll_init(struct drm_device *dev)
12848 {
12849 struct drm_i915_private *dev_priv = dev->dev_private;
12850 int i;
12851
12852 dev_priv->num_shared_dpll = 2;
12853
12854 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12855 dev_priv->shared_dplls[i].id = i;
12856 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
12857 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
12858 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
12859 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
12860 dev_priv->shared_dplls[i].get_hw_state =
12861 ibx_pch_dpll_get_hw_state;
12862 }
12863 }
12864
12865 static void intel_shared_dpll_init(struct drm_device *dev)
12866 {
12867 struct drm_i915_private *dev_priv = dev->dev_private;
12868
12869 if (HAS_DDI(dev))
12870 intel_ddi_pll_init(dev);
12871 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
12872 ibx_pch_dpll_init(dev);
12873 else
12874 dev_priv->num_shared_dpll = 0;
12875
12876 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
12877 }
12878
12879 /**
12880 * intel_wm_need_update - Check whether watermarks need updating
12881 * @plane: drm plane
12882 * @state: new plane state
12883 *
12884 * Check current plane state versus the new one to determine whether
12885 * watermarks need to be recalculated.
12886 *
12887 * Returns true or false.
12888 */
12889 bool intel_wm_need_update(struct drm_plane *plane,
12890 struct drm_plane_state *state)
12891 {
12892 /* Update watermarks on tiling changes. */
12893 if (!plane->state->fb || !state->fb ||
12894 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
12895 plane->state->rotation != state->rotation)
12896 return true;
12897
12898 return false;
12899 }
12900
12901 /**
12902 * intel_prepare_plane_fb - Prepare fb for usage on plane
12903 * @plane: drm plane to prepare for
12904 * @fb: framebuffer to prepare for presentation
12905 *
12906 * Prepares a framebuffer for usage on a display plane. Generally this
12907 * involves pinning the underlying object and updating the frontbuffer tracking
12908 * bits. Some older platforms need special physical address handling for
12909 * cursor planes.
12910 *
12911 * Returns 0 on success, negative error code on failure.
12912 */
12913 int
12914 intel_prepare_plane_fb(struct drm_plane *plane,
12915 struct drm_framebuffer *fb,
12916 const struct drm_plane_state *new_state)
12917 {
12918 struct drm_device *dev = plane->dev;
12919 struct intel_plane *intel_plane = to_intel_plane(plane);
12920 enum pipe pipe = intel_plane->pipe;
12921 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12922 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
12923 unsigned frontbuffer_bits = 0;
12924 int ret = 0;
12925
12926 if (!obj)
12927 return 0;
12928
12929 switch (plane->type) {
12930 case DRM_PLANE_TYPE_PRIMARY:
12931 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
12932 break;
12933 case DRM_PLANE_TYPE_CURSOR:
12934 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
12935 break;
12936 case DRM_PLANE_TYPE_OVERLAY:
12937 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
12938 break;
12939 }
12940
12941 mutex_lock(&dev->struct_mutex);
12942
12943 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
12944 INTEL_INFO(dev)->cursor_needs_physical) {
12945 int align = IS_I830(dev) ? 16 * 1024 : 256;
12946 ret = i915_gem_object_attach_phys(obj, align);
12947 if (ret)
12948 DRM_DEBUG_KMS("failed to attach phys object\n");
12949 } else {
12950 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
12951 }
12952
12953 if (ret == 0)
12954 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
12955
12956 mutex_unlock(&dev->struct_mutex);
12957
12958 return ret;
12959 }
12960
12961 /**
12962 * intel_cleanup_plane_fb - Cleans up an fb after plane use
12963 * @plane: drm plane to clean up for
12964 * @fb: old framebuffer that was on plane
12965 *
12966 * Cleans up a framebuffer that has just been removed from a plane.
12967 */
12968 void
12969 intel_cleanup_plane_fb(struct drm_plane *plane,
12970 struct drm_framebuffer *fb,
12971 const struct drm_plane_state *old_state)
12972 {
12973 struct drm_device *dev = plane->dev;
12974 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12975
12976 if (WARN_ON(!obj))
12977 return;
12978
12979 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
12980 !INTEL_INFO(dev)->cursor_needs_physical) {
12981 mutex_lock(&dev->struct_mutex);
12982 intel_unpin_fb_obj(fb, old_state);
12983 mutex_unlock(&dev->struct_mutex);
12984 }
12985 }
12986
12987 int
12988 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
12989 {
12990 int max_scale;
12991 struct drm_device *dev;
12992 struct drm_i915_private *dev_priv;
12993 int crtc_clock, cdclk;
12994
12995 if (!intel_crtc || !crtc_state)
12996 return DRM_PLANE_HELPER_NO_SCALING;
12997
12998 dev = intel_crtc->base.dev;
12999 dev_priv = dev->dev_private;
13000 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13001 cdclk = dev_priv->display.get_display_clock_speed(dev);
13002
13003 if (!crtc_clock || !cdclk)
13004 return DRM_PLANE_HELPER_NO_SCALING;
13005
13006 /*
13007 * skl max scale is lower of:
13008 * close to 3 but not 3, -1 is for that purpose
13009 * or
13010 * cdclk/crtc_clock
13011 */
13012 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13013
13014 return max_scale;
13015 }
13016
13017 static int
13018 intel_check_primary_plane(struct drm_plane *plane,
13019 struct intel_plane_state *state)
13020 {
13021 struct drm_device *dev = plane->dev;
13022 struct drm_i915_private *dev_priv = dev->dev_private;
13023 struct drm_crtc *crtc = state->base.crtc;
13024 struct intel_crtc *intel_crtc;
13025 struct intel_crtc_state *crtc_state;
13026 struct drm_framebuffer *fb = state->base.fb;
13027 struct drm_rect *dest = &state->dst;
13028 struct drm_rect *src = &state->src;
13029 const struct drm_rect *clip = &state->clip;
13030 bool can_position = false;
13031 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13032 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13033 int ret;
13034
13035 crtc = crtc ? crtc : plane->crtc;
13036 intel_crtc = to_intel_crtc(crtc);
13037 crtc_state = state->base.state ?
13038 intel_atomic_get_crtc_state(state->base.state, intel_crtc) : NULL;
13039
13040 if (INTEL_INFO(dev)->gen >= 9) {
13041 min_scale = 1;
13042 max_scale = skl_max_scale(intel_crtc, crtc_state);
13043 can_position = true;
13044 }
13045
13046 ret = drm_plane_helper_check_update(plane, crtc, fb,
13047 src, dest, clip,
13048 min_scale,
13049 max_scale,
13050 can_position, true,
13051 &state->visible);
13052 if (ret)
13053 return ret;
13054
13055 if (intel_crtc->active) {
13056 struct intel_plane_state *old_state =
13057 to_intel_plane_state(plane->state);
13058
13059 intel_crtc->atomic.wait_for_flips = true;
13060
13061 /*
13062 * FBC does not work on some platforms for rotated
13063 * planes, so disable it when rotation is not 0 and
13064 * update it when rotation is set back to 0.
13065 *
13066 * FIXME: This is redundant with the fbc update done in
13067 * the primary plane enable function except that that
13068 * one is done too late. We eventually need to unify
13069 * this.
13070 */
13071 if (state->visible &&
13072 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
13073 dev_priv->fbc.crtc == intel_crtc &&
13074 state->base.rotation != BIT(DRM_ROTATE_0)) {
13075 intel_crtc->atomic.disable_fbc = true;
13076 }
13077
13078 if (state->visible && !old_state->visible) {
13079 /*
13080 * BDW signals flip done immediately if the plane
13081 * is disabled, even if the plane enable is already
13082 * armed to occur at the next vblank :(
13083 */
13084 if (IS_BROADWELL(dev))
13085 intel_crtc->atomic.wait_vblank = true;
13086 }
13087
13088 intel_crtc->atomic.fb_bits |=
13089 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
13090
13091 intel_crtc->atomic.update_fbc = true;
13092
13093 if (intel_wm_need_update(plane, &state->base))
13094 intel_crtc->atomic.update_wm = true;
13095 }
13096
13097 if (INTEL_INFO(dev)->gen >= 9) {
13098 ret = skl_update_scaler_users(intel_crtc, crtc_state,
13099 to_intel_plane(plane), state, 0);
13100 if (ret)
13101 return ret;
13102 }
13103
13104 return 0;
13105 }
13106
13107 static void
13108 intel_commit_primary_plane(struct drm_plane *plane,
13109 struct intel_plane_state *state)
13110 {
13111 struct drm_crtc *crtc = state->base.crtc;
13112 struct drm_framebuffer *fb = state->base.fb;
13113 struct drm_device *dev = plane->dev;
13114 struct drm_i915_private *dev_priv = dev->dev_private;
13115 struct intel_crtc *intel_crtc;
13116 struct drm_rect *src = &state->src;
13117
13118 crtc = crtc ? crtc : plane->crtc;
13119 intel_crtc = to_intel_crtc(crtc);
13120
13121 plane->fb = fb;
13122 crtc->x = src->x1 >> 16;
13123 crtc->y = src->y1 >> 16;
13124
13125 if (intel_crtc->active) {
13126 if (state->visible)
13127 /* FIXME: kill this fastboot hack */
13128 intel_update_pipe_size(intel_crtc);
13129
13130 dev_priv->display.update_primary_plane(crtc, plane->fb,
13131 crtc->x, crtc->y);
13132 }
13133 }
13134
13135 static void
13136 intel_disable_primary_plane(struct drm_plane *plane,
13137 struct drm_crtc *crtc,
13138 bool force)
13139 {
13140 struct drm_device *dev = plane->dev;
13141 struct drm_i915_private *dev_priv = dev->dev_private;
13142
13143 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13144 }
13145
13146 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
13147 {
13148 struct drm_device *dev = crtc->dev;
13149 struct drm_i915_private *dev_priv = dev->dev_private;
13150 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13151 struct intel_plane *intel_plane;
13152 struct drm_plane *p;
13153 unsigned fb_bits = 0;
13154
13155 /* Track fb's for any planes being disabled */
13156 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
13157 intel_plane = to_intel_plane(p);
13158
13159 if (intel_crtc->atomic.disabled_planes &
13160 (1 << drm_plane_index(p))) {
13161 switch (p->type) {
13162 case DRM_PLANE_TYPE_PRIMARY:
13163 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
13164 break;
13165 case DRM_PLANE_TYPE_CURSOR:
13166 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
13167 break;
13168 case DRM_PLANE_TYPE_OVERLAY:
13169 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
13170 break;
13171 }
13172
13173 mutex_lock(&dev->struct_mutex);
13174 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
13175 mutex_unlock(&dev->struct_mutex);
13176 }
13177 }
13178
13179 if (intel_crtc->atomic.wait_for_flips)
13180 intel_crtc_wait_for_pending_flips(crtc);
13181
13182 if (intel_crtc->atomic.disable_fbc)
13183 intel_fbc_disable(dev);
13184
13185 if (intel_crtc->atomic.pre_disable_primary)
13186 intel_pre_disable_primary(crtc);
13187
13188 if (intel_crtc->atomic.update_wm)
13189 intel_update_watermarks(crtc);
13190
13191 intel_runtime_pm_get(dev_priv);
13192
13193 /* Perform vblank evasion around commit operation */
13194 if (intel_crtc->active)
13195 intel_crtc->atomic.evade =
13196 intel_pipe_update_start(intel_crtc,
13197 &intel_crtc->atomic.start_vbl_count);
13198 }
13199
13200 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13201 {
13202 struct drm_device *dev = crtc->dev;
13203 struct drm_i915_private *dev_priv = dev->dev_private;
13204 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13205 struct drm_plane *p;
13206
13207 if (intel_crtc->atomic.evade)
13208 intel_pipe_update_end(intel_crtc,
13209 intel_crtc->atomic.start_vbl_count);
13210
13211 intel_runtime_pm_put(dev_priv);
13212
13213 if (intel_crtc->atomic.wait_vblank)
13214 intel_wait_for_vblank(dev, intel_crtc->pipe);
13215
13216 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
13217
13218 if (intel_crtc->atomic.update_fbc) {
13219 mutex_lock(&dev->struct_mutex);
13220 intel_fbc_update(dev);
13221 mutex_unlock(&dev->struct_mutex);
13222 }
13223
13224 if (intel_crtc->atomic.post_enable_primary)
13225 intel_post_enable_primary(crtc);
13226
13227 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
13228 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
13229 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
13230 false, false);
13231
13232 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
13233 }
13234
13235 /**
13236 * intel_plane_destroy - destroy a plane
13237 * @plane: plane to destroy
13238 *
13239 * Common destruction function for all types of planes (primary, cursor,
13240 * sprite).
13241 */
13242 void intel_plane_destroy(struct drm_plane *plane)
13243 {
13244 struct intel_plane *intel_plane = to_intel_plane(plane);
13245 drm_plane_cleanup(plane);
13246 kfree(intel_plane);
13247 }
13248
13249 const struct drm_plane_funcs intel_plane_funcs = {
13250 .update_plane = drm_atomic_helper_update_plane,
13251 .disable_plane = drm_atomic_helper_disable_plane,
13252 .destroy = intel_plane_destroy,
13253 .set_property = drm_atomic_helper_plane_set_property,
13254 .atomic_get_property = intel_plane_atomic_get_property,
13255 .atomic_set_property = intel_plane_atomic_set_property,
13256 .atomic_duplicate_state = intel_plane_duplicate_state,
13257 .atomic_destroy_state = intel_plane_destroy_state,
13258
13259 };
13260
13261 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13262 int pipe)
13263 {
13264 struct intel_plane *primary;
13265 struct intel_plane_state *state;
13266 const uint32_t *intel_primary_formats;
13267 int num_formats;
13268
13269 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13270 if (primary == NULL)
13271 return NULL;
13272
13273 state = intel_create_plane_state(&primary->base);
13274 if (!state) {
13275 kfree(primary);
13276 return NULL;
13277 }
13278 primary->base.state = &state->base;
13279
13280 primary->can_scale = false;
13281 primary->max_downscale = 1;
13282 if (INTEL_INFO(dev)->gen >= 9) {
13283 primary->can_scale = true;
13284 }
13285 state->scaler_id = -1;
13286 primary->pipe = pipe;
13287 primary->plane = pipe;
13288 primary->check_plane = intel_check_primary_plane;
13289 primary->commit_plane = intel_commit_primary_plane;
13290 primary->disable_plane = intel_disable_primary_plane;
13291 primary->ckey.flags = I915_SET_COLORKEY_NONE;
13292 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13293 primary->plane = !pipe;
13294
13295 if (INTEL_INFO(dev)->gen <= 3) {
13296 intel_primary_formats = intel_primary_formats_gen2;
13297 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
13298 } else {
13299 intel_primary_formats = intel_primary_formats_gen4;
13300 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
13301 }
13302
13303 drm_universal_plane_init(dev, &primary->base, 0,
13304 &intel_plane_funcs,
13305 intel_primary_formats, num_formats,
13306 DRM_PLANE_TYPE_PRIMARY);
13307
13308 if (INTEL_INFO(dev)->gen >= 4)
13309 intel_create_rotation_property(dev, primary);
13310
13311 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13312
13313 return &primary->base;
13314 }
13315
13316 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13317 {
13318 if (!dev->mode_config.rotation_property) {
13319 unsigned long flags = BIT(DRM_ROTATE_0) |
13320 BIT(DRM_ROTATE_180);
13321
13322 if (INTEL_INFO(dev)->gen >= 9)
13323 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13324
13325 dev->mode_config.rotation_property =
13326 drm_mode_create_rotation_property(dev, flags);
13327 }
13328 if (dev->mode_config.rotation_property)
13329 drm_object_attach_property(&plane->base.base,
13330 dev->mode_config.rotation_property,
13331 plane->base.state->rotation);
13332 }
13333
13334 static int
13335 intel_check_cursor_plane(struct drm_plane *plane,
13336 struct intel_plane_state *state)
13337 {
13338 struct drm_crtc *crtc = state->base.crtc;
13339 struct drm_device *dev = plane->dev;
13340 struct drm_framebuffer *fb = state->base.fb;
13341 struct drm_rect *dest = &state->dst;
13342 struct drm_rect *src = &state->src;
13343 const struct drm_rect *clip = &state->clip;
13344 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13345 struct intel_crtc *intel_crtc;
13346 unsigned stride;
13347 int ret;
13348
13349 crtc = crtc ? crtc : plane->crtc;
13350 intel_crtc = to_intel_crtc(crtc);
13351
13352 ret = drm_plane_helper_check_update(plane, crtc, fb,
13353 src, dest, clip,
13354 DRM_PLANE_HELPER_NO_SCALING,
13355 DRM_PLANE_HELPER_NO_SCALING,
13356 true, true, &state->visible);
13357 if (ret)
13358 return ret;
13359
13360
13361 /* if we want to turn off the cursor ignore width and height */
13362 if (!obj)
13363 goto finish;
13364
13365 /* Check for which cursor types we support */
13366 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
13367 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13368 state->base.crtc_w, state->base.crtc_h);
13369 return -EINVAL;
13370 }
13371
13372 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13373 if (obj->base.size < stride * state->base.crtc_h) {
13374 DRM_DEBUG_KMS("buffer is too small\n");
13375 return -ENOMEM;
13376 }
13377
13378 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13379 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13380 ret = -EINVAL;
13381 }
13382
13383 finish:
13384 if (intel_crtc->active) {
13385 if (plane->state->crtc_w != state->base.crtc_w)
13386 intel_crtc->atomic.update_wm = true;
13387
13388 intel_crtc->atomic.fb_bits |=
13389 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
13390 }
13391
13392 return ret;
13393 }
13394
13395 static void
13396 intel_disable_cursor_plane(struct drm_plane *plane,
13397 struct drm_crtc *crtc,
13398 bool force)
13399 {
13400 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13401
13402 if (!force) {
13403 plane->fb = NULL;
13404 intel_crtc->cursor_bo = NULL;
13405 intel_crtc->cursor_addr = 0;
13406 }
13407
13408 intel_crtc_update_cursor(crtc, false);
13409 }
13410
13411 static void
13412 intel_commit_cursor_plane(struct drm_plane *plane,
13413 struct intel_plane_state *state)
13414 {
13415 struct drm_crtc *crtc = state->base.crtc;
13416 struct drm_device *dev = plane->dev;
13417 struct intel_crtc *intel_crtc;
13418 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13419 uint32_t addr;
13420
13421 crtc = crtc ? crtc : plane->crtc;
13422 intel_crtc = to_intel_crtc(crtc);
13423
13424 plane->fb = state->base.fb;
13425 crtc->cursor_x = state->base.crtc_x;
13426 crtc->cursor_y = state->base.crtc_y;
13427
13428 if (intel_crtc->cursor_bo == obj)
13429 goto update;
13430
13431 if (!obj)
13432 addr = 0;
13433 else if (!INTEL_INFO(dev)->cursor_needs_physical)
13434 addr = i915_gem_obj_ggtt_offset(obj);
13435 else
13436 addr = obj->phys_handle->busaddr;
13437
13438 intel_crtc->cursor_addr = addr;
13439 intel_crtc->cursor_bo = obj;
13440 update:
13441
13442 if (intel_crtc->active)
13443 intel_crtc_update_cursor(crtc, state->visible);
13444 }
13445
13446 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13447 int pipe)
13448 {
13449 struct intel_plane *cursor;
13450 struct intel_plane_state *state;
13451
13452 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13453 if (cursor == NULL)
13454 return NULL;
13455
13456 state = intel_create_plane_state(&cursor->base);
13457 if (!state) {
13458 kfree(cursor);
13459 return NULL;
13460 }
13461 cursor->base.state = &state->base;
13462
13463 cursor->can_scale = false;
13464 cursor->max_downscale = 1;
13465 cursor->pipe = pipe;
13466 cursor->plane = pipe;
13467 state->scaler_id = -1;
13468 cursor->check_plane = intel_check_cursor_plane;
13469 cursor->commit_plane = intel_commit_cursor_plane;
13470 cursor->disable_plane = intel_disable_cursor_plane;
13471
13472 drm_universal_plane_init(dev, &cursor->base, 0,
13473 &intel_plane_funcs,
13474 intel_cursor_formats,
13475 ARRAY_SIZE(intel_cursor_formats),
13476 DRM_PLANE_TYPE_CURSOR);
13477
13478 if (INTEL_INFO(dev)->gen >= 4) {
13479 if (!dev->mode_config.rotation_property)
13480 dev->mode_config.rotation_property =
13481 drm_mode_create_rotation_property(dev,
13482 BIT(DRM_ROTATE_0) |
13483 BIT(DRM_ROTATE_180));
13484 if (dev->mode_config.rotation_property)
13485 drm_object_attach_property(&cursor->base.base,
13486 dev->mode_config.rotation_property,
13487 state->base.rotation);
13488 }
13489
13490 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13491
13492 return &cursor->base;
13493 }
13494
13495 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13496 struct intel_crtc_state *crtc_state)
13497 {
13498 int i;
13499 struct intel_scaler *intel_scaler;
13500 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13501
13502 for (i = 0; i < intel_crtc->num_scalers; i++) {
13503 intel_scaler = &scaler_state->scalers[i];
13504 intel_scaler->in_use = 0;
13505 intel_scaler->id = i;
13506
13507 intel_scaler->mode = PS_SCALER_MODE_DYN;
13508 }
13509
13510 scaler_state->scaler_id = -1;
13511 }
13512
13513 static void intel_crtc_init(struct drm_device *dev, int pipe)
13514 {
13515 struct drm_i915_private *dev_priv = dev->dev_private;
13516 struct intel_crtc *intel_crtc;
13517 struct intel_crtc_state *crtc_state = NULL;
13518 struct drm_plane *primary = NULL;
13519 struct drm_plane *cursor = NULL;
13520 int i, ret;
13521
13522 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13523 if (intel_crtc == NULL)
13524 return;
13525
13526 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13527 if (!crtc_state)
13528 goto fail;
13529 intel_crtc_set_state(intel_crtc, crtc_state);
13530 crtc_state->base.crtc = &intel_crtc->base;
13531
13532 /* initialize shared scalers */
13533 if (INTEL_INFO(dev)->gen >= 9) {
13534 if (pipe == PIPE_C)
13535 intel_crtc->num_scalers = 1;
13536 else
13537 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13538
13539 skl_init_scalers(dev, intel_crtc, crtc_state);
13540 }
13541
13542 primary = intel_primary_plane_create(dev, pipe);
13543 if (!primary)
13544 goto fail;
13545
13546 cursor = intel_cursor_plane_create(dev, pipe);
13547 if (!cursor)
13548 goto fail;
13549
13550 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
13551 cursor, &intel_crtc_funcs);
13552 if (ret)
13553 goto fail;
13554
13555 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
13556 for (i = 0; i < 256; i++) {
13557 intel_crtc->lut_r[i] = i;
13558 intel_crtc->lut_g[i] = i;
13559 intel_crtc->lut_b[i] = i;
13560 }
13561
13562 /*
13563 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13564 * is hooked to pipe B. Hence we want plane A feeding pipe B.
13565 */
13566 intel_crtc->pipe = pipe;
13567 intel_crtc->plane = pipe;
13568 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
13569 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13570 intel_crtc->plane = !pipe;
13571 }
13572
13573 intel_crtc->cursor_base = ~0;
13574 intel_crtc->cursor_cntl = ~0;
13575 intel_crtc->cursor_size = ~0;
13576
13577 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13578 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13579 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13580 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13581
13582 INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
13583
13584 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13585
13586 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13587 return;
13588
13589 fail:
13590 if (primary)
13591 drm_plane_cleanup(primary);
13592 if (cursor)
13593 drm_plane_cleanup(cursor);
13594 kfree(crtc_state);
13595 kfree(intel_crtc);
13596 }
13597
13598 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13599 {
13600 struct drm_encoder *encoder = connector->base.encoder;
13601 struct drm_device *dev = connector->base.dev;
13602
13603 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13604
13605 if (!encoder || WARN_ON(!encoder->crtc))
13606 return INVALID_PIPE;
13607
13608 return to_intel_crtc(encoder->crtc)->pipe;
13609 }
13610
13611 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13612 struct drm_file *file)
13613 {
13614 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13615 struct drm_crtc *drmmode_crtc;
13616 struct intel_crtc *crtc;
13617
13618 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13619
13620 if (!drmmode_crtc) {
13621 DRM_ERROR("no such CRTC id\n");
13622 return -ENOENT;
13623 }
13624
13625 crtc = to_intel_crtc(drmmode_crtc);
13626 pipe_from_crtc_id->pipe = crtc->pipe;
13627
13628 return 0;
13629 }
13630
13631 static int intel_encoder_clones(struct intel_encoder *encoder)
13632 {
13633 struct drm_device *dev = encoder->base.dev;
13634 struct intel_encoder *source_encoder;
13635 int index_mask = 0;
13636 int entry = 0;
13637
13638 for_each_intel_encoder(dev, source_encoder) {
13639 if (encoders_cloneable(encoder, source_encoder))
13640 index_mask |= (1 << entry);
13641
13642 entry++;
13643 }
13644
13645 return index_mask;
13646 }
13647
13648 static bool has_edp_a(struct drm_device *dev)
13649 {
13650 struct drm_i915_private *dev_priv = dev->dev_private;
13651
13652 if (!IS_MOBILE(dev))
13653 return false;
13654
13655 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13656 return false;
13657
13658 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13659 return false;
13660
13661 return true;
13662 }
13663
13664 static bool intel_crt_present(struct drm_device *dev)
13665 {
13666 struct drm_i915_private *dev_priv = dev->dev_private;
13667
13668 if (INTEL_INFO(dev)->gen >= 9)
13669 return false;
13670
13671 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
13672 return false;
13673
13674 if (IS_CHERRYVIEW(dev))
13675 return false;
13676
13677 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13678 return false;
13679
13680 return true;
13681 }
13682
13683 static void intel_setup_outputs(struct drm_device *dev)
13684 {
13685 struct drm_i915_private *dev_priv = dev->dev_private;
13686 struct intel_encoder *encoder;
13687 bool dpd_is_edp = false;
13688
13689 intel_lvds_init(dev);
13690
13691 if (intel_crt_present(dev))
13692 intel_crt_init(dev);
13693
13694 if (IS_BROXTON(dev)) {
13695 /*
13696 * FIXME: Broxton doesn't support port detection via the
13697 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13698 * detect the ports.
13699 */
13700 intel_ddi_init(dev, PORT_A);
13701 intel_ddi_init(dev, PORT_B);
13702 intel_ddi_init(dev, PORT_C);
13703 } else if (HAS_DDI(dev)) {
13704 int found;
13705
13706 /*
13707 * Haswell uses DDI functions to detect digital outputs.
13708 * On SKL pre-D0 the strap isn't connected, so we assume
13709 * it's there.
13710 */
13711 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
13712 /* WaIgnoreDDIAStrap: skl */
13713 if (found ||
13714 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
13715 intel_ddi_init(dev, PORT_A);
13716
13717 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13718 * register */
13719 found = I915_READ(SFUSE_STRAP);
13720
13721 if (found & SFUSE_STRAP_DDIB_DETECTED)
13722 intel_ddi_init(dev, PORT_B);
13723 if (found & SFUSE_STRAP_DDIC_DETECTED)
13724 intel_ddi_init(dev, PORT_C);
13725 if (found & SFUSE_STRAP_DDID_DETECTED)
13726 intel_ddi_init(dev, PORT_D);
13727 } else if (HAS_PCH_SPLIT(dev)) {
13728 int found;
13729 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
13730
13731 if (has_edp_a(dev))
13732 intel_dp_init(dev, DP_A, PORT_A);
13733
13734 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
13735 /* PCH SDVOB multiplex with HDMIB */
13736 found = intel_sdvo_init(dev, PCH_SDVOB, true);
13737 if (!found)
13738 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
13739 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
13740 intel_dp_init(dev, PCH_DP_B, PORT_B);
13741 }
13742
13743 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
13744 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
13745
13746 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
13747 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
13748
13749 if (I915_READ(PCH_DP_C) & DP_DETECTED)
13750 intel_dp_init(dev, PCH_DP_C, PORT_C);
13751
13752 if (I915_READ(PCH_DP_D) & DP_DETECTED)
13753 intel_dp_init(dev, PCH_DP_D, PORT_D);
13754 } else if (IS_VALLEYVIEW(dev)) {
13755 /*
13756 * The DP_DETECTED bit is the latched state of the DDC
13757 * SDA pin at boot. However since eDP doesn't require DDC
13758 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13759 * eDP ports may have been muxed to an alternate function.
13760 * Thus we can't rely on the DP_DETECTED bit alone to detect
13761 * eDP ports. Consult the VBT as well as DP_DETECTED to
13762 * detect eDP ports.
13763 */
13764 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
13765 !intel_dp_is_edp(dev, PORT_B))
13766 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
13767 PORT_B);
13768 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
13769 intel_dp_is_edp(dev, PORT_B))
13770 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
13771
13772 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
13773 !intel_dp_is_edp(dev, PORT_C))
13774 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
13775 PORT_C);
13776 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
13777 intel_dp_is_edp(dev, PORT_C))
13778 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
13779
13780 if (IS_CHERRYVIEW(dev)) {
13781 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
13782 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
13783 PORT_D);
13784 /* eDP not supported on port D, so don't check VBT */
13785 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
13786 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
13787 }
13788
13789 intel_dsi_init(dev);
13790 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
13791 bool found = false;
13792
13793 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13794 DRM_DEBUG_KMS("probing SDVOB\n");
13795 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
13796 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
13797 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
13798 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
13799 }
13800
13801 if (!found && SUPPORTS_INTEGRATED_DP(dev))
13802 intel_dp_init(dev, DP_B, PORT_B);
13803 }
13804
13805 /* Before G4X SDVOC doesn't have its own detect register */
13806
13807 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13808 DRM_DEBUG_KMS("probing SDVOC\n");
13809 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
13810 }
13811
13812 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
13813
13814 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
13815 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
13816 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
13817 }
13818 if (SUPPORTS_INTEGRATED_DP(dev))
13819 intel_dp_init(dev, DP_C, PORT_C);
13820 }
13821
13822 if (SUPPORTS_INTEGRATED_DP(dev) &&
13823 (I915_READ(DP_D) & DP_DETECTED))
13824 intel_dp_init(dev, DP_D, PORT_D);
13825 } else if (IS_GEN2(dev))
13826 intel_dvo_init(dev);
13827
13828 if (SUPPORTS_TV(dev))
13829 intel_tv_init(dev);
13830
13831 intel_psr_init(dev);
13832
13833 for_each_intel_encoder(dev, encoder) {
13834 encoder->base.possible_crtcs = encoder->crtc_mask;
13835 encoder->base.possible_clones =
13836 intel_encoder_clones(encoder);
13837 }
13838
13839 intel_init_pch_refclk(dev);
13840
13841 drm_helper_move_panel_connectors_to_head(dev);
13842 }
13843
13844 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
13845 {
13846 struct drm_device *dev = fb->dev;
13847 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13848
13849 drm_framebuffer_cleanup(fb);
13850 mutex_lock(&dev->struct_mutex);
13851 WARN_ON(!intel_fb->obj->framebuffer_references--);
13852 drm_gem_object_unreference(&intel_fb->obj->base);
13853 mutex_unlock(&dev->struct_mutex);
13854 kfree(intel_fb);
13855 }
13856
13857 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
13858 struct drm_file *file,
13859 unsigned int *handle)
13860 {
13861 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13862 struct drm_i915_gem_object *obj = intel_fb->obj;
13863
13864 return drm_gem_handle_create(file, &obj->base, handle);
13865 }
13866
13867 static const struct drm_framebuffer_funcs intel_fb_funcs = {
13868 .destroy = intel_user_framebuffer_destroy,
13869 .create_handle = intel_user_framebuffer_create_handle,
13870 };
13871
13872 static
13873 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
13874 uint32_t pixel_format)
13875 {
13876 u32 gen = INTEL_INFO(dev)->gen;
13877
13878 if (gen >= 9) {
13879 /* "The stride in bytes must not exceed the of the size of 8K
13880 * pixels and 32K bytes."
13881 */
13882 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
13883 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
13884 return 32*1024;
13885 } else if (gen >= 4) {
13886 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13887 return 16*1024;
13888 else
13889 return 32*1024;
13890 } else if (gen >= 3) {
13891 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13892 return 8*1024;
13893 else
13894 return 16*1024;
13895 } else {
13896 /* XXX DSPC is limited to 4k tiled */
13897 return 8*1024;
13898 }
13899 }
13900
13901 static int intel_framebuffer_init(struct drm_device *dev,
13902 struct intel_framebuffer *intel_fb,
13903 struct drm_mode_fb_cmd2 *mode_cmd,
13904 struct drm_i915_gem_object *obj)
13905 {
13906 unsigned int aligned_height;
13907 int ret;
13908 u32 pitch_limit, stride_alignment;
13909
13910 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
13911
13912 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
13913 /* Enforce that fb modifier and tiling mode match, but only for
13914 * X-tiled. This is needed for FBC. */
13915 if (!!(obj->tiling_mode == I915_TILING_X) !=
13916 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
13917 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
13918 return -EINVAL;
13919 }
13920 } else {
13921 if (obj->tiling_mode == I915_TILING_X)
13922 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
13923 else if (obj->tiling_mode == I915_TILING_Y) {
13924 DRM_DEBUG("No Y tiling for legacy addfb\n");
13925 return -EINVAL;
13926 }
13927 }
13928
13929 /* Passed in modifier sanity checking. */
13930 switch (mode_cmd->modifier[0]) {
13931 case I915_FORMAT_MOD_Y_TILED:
13932 case I915_FORMAT_MOD_Yf_TILED:
13933 if (INTEL_INFO(dev)->gen < 9) {
13934 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
13935 mode_cmd->modifier[0]);
13936 return -EINVAL;
13937 }
13938 case DRM_FORMAT_MOD_NONE:
13939 case I915_FORMAT_MOD_X_TILED:
13940 break;
13941 default:
13942 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
13943 mode_cmd->modifier[0]);
13944 return -EINVAL;
13945 }
13946
13947 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
13948 mode_cmd->pixel_format);
13949 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
13950 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
13951 mode_cmd->pitches[0], stride_alignment);
13952 return -EINVAL;
13953 }
13954
13955 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
13956 mode_cmd->pixel_format);
13957 if (mode_cmd->pitches[0] > pitch_limit) {
13958 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
13959 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
13960 "tiled" : "linear",
13961 mode_cmd->pitches[0], pitch_limit);
13962 return -EINVAL;
13963 }
13964
13965 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
13966 mode_cmd->pitches[0] != obj->stride) {
13967 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
13968 mode_cmd->pitches[0], obj->stride);
13969 return -EINVAL;
13970 }
13971
13972 /* Reject formats not supported by any plane early. */
13973 switch (mode_cmd->pixel_format) {
13974 case DRM_FORMAT_C8:
13975 case DRM_FORMAT_RGB565:
13976 case DRM_FORMAT_XRGB8888:
13977 case DRM_FORMAT_ARGB8888:
13978 break;
13979 case DRM_FORMAT_XRGB1555:
13980 case DRM_FORMAT_ARGB1555:
13981 if (INTEL_INFO(dev)->gen > 3) {
13982 DRM_DEBUG("unsupported pixel format: %s\n",
13983 drm_get_format_name(mode_cmd->pixel_format));
13984 return -EINVAL;
13985 }
13986 break;
13987 case DRM_FORMAT_XBGR8888:
13988 case DRM_FORMAT_ABGR8888:
13989 case DRM_FORMAT_XRGB2101010:
13990 case DRM_FORMAT_ARGB2101010:
13991 case DRM_FORMAT_XBGR2101010:
13992 case DRM_FORMAT_ABGR2101010:
13993 if (INTEL_INFO(dev)->gen < 4) {
13994 DRM_DEBUG("unsupported pixel format: %s\n",
13995 drm_get_format_name(mode_cmd->pixel_format));
13996 return -EINVAL;
13997 }
13998 break;
13999 case DRM_FORMAT_YUYV:
14000 case DRM_FORMAT_UYVY:
14001 case DRM_FORMAT_YVYU:
14002 case DRM_FORMAT_VYUY:
14003 if (INTEL_INFO(dev)->gen < 5) {
14004 DRM_DEBUG("unsupported pixel format: %s\n",
14005 drm_get_format_name(mode_cmd->pixel_format));
14006 return -EINVAL;
14007 }
14008 break;
14009 default:
14010 DRM_DEBUG("unsupported pixel format: %s\n",
14011 drm_get_format_name(mode_cmd->pixel_format));
14012 return -EINVAL;
14013 }
14014
14015 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14016 if (mode_cmd->offsets[0] != 0)
14017 return -EINVAL;
14018
14019 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14020 mode_cmd->pixel_format,
14021 mode_cmd->modifier[0]);
14022 /* FIXME drm helper for size checks (especially planar formats)? */
14023 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14024 return -EINVAL;
14025
14026 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14027 intel_fb->obj = obj;
14028 intel_fb->obj->framebuffer_references++;
14029
14030 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14031 if (ret) {
14032 DRM_ERROR("framebuffer init failed %d\n", ret);
14033 return ret;
14034 }
14035
14036 return 0;
14037 }
14038
14039 static struct drm_framebuffer *
14040 intel_user_framebuffer_create(struct drm_device *dev,
14041 struct drm_file *filp,
14042 struct drm_mode_fb_cmd2 *mode_cmd)
14043 {
14044 struct drm_i915_gem_object *obj;
14045
14046 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14047 mode_cmd->handles[0]));
14048 if (&obj->base == NULL)
14049 return ERR_PTR(-ENOENT);
14050
14051 return intel_framebuffer_create(dev, mode_cmd, obj);
14052 }
14053
14054 #ifndef CONFIG_DRM_I915_FBDEV
14055 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14056 {
14057 }
14058 #endif
14059
14060 static const struct drm_mode_config_funcs intel_mode_funcs = {
14061 .fb_create = intel_user_framebuffer_create,
14062 .output_poll_changed = intel_fbdev_output_poll_changed,
14063 .atomic_check = intel_atomic_check,
14064 .atomic_commit = intel_atomic_commit,
14065 };
14066
14067 /* Set up chip specific display functions */
14068 static void intel_init_display(struct drm_device *dev)
14069 {
14070 struct drm_i915_private *dev_priv = dev->dev_private;
14071
14072 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14073 dev_priv->display.find_dpll = g4x_find_best_dpll;
14074 else if (IS_CHERRYVIEW(dev))
14075 dev_priv->display.find_dpll = chv_find_best_dpll;
14076 else if (IS_VALLEYVIEW(dev))
14077 dev_priv->display.find_dpll = vlv_find_best_dpll;
14078 else if (IS_PINEVIEW(dev))
14079 dev_priv->display.find_dpll = pnv_find_best_dpll;
14080 else
14081 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14082
14083 if (INTEL_INFO(dev)->gen >= 9) {
14084 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14085 dev_priv->display.get_initial_plane_config =
14086 skylake_get_initial_plane_config;
14087 dev_priv->display.crtc_compute_clock =
14088 haswell_crtc_compute_clock;
14089 dev_priv->display.crtc_enable = haswell_crtc_enable;
14090 dev_priv->display.crtc_disable = haswell_crtc_disable;
14091 dev_priv->display.off = ironlake_crtc_off;
14092 dev_priv->display.update_primary_plane =
14093 skylake_update_primary_plane;
14094 } else if (HAS_DDI(dev)) {
14095 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14096 dev_priv->display.get_initial_plane_config =
14097 ironlake_get_initial_plane_config;
14098 dev_priv->display.crtc_compute_clock =
14099 haswell_crtc_compute_clock;
14100 dev_priv->display.crtc_enable = haswell_crtc_enable;
14101 dev_priv->display.crtc_disable = haswell_crtc_disable;
14102 dev_priv->display.off = ironlake_crtc_off;
14103 dev_priv->display.update_primary_plane =
14104 ironlake_update_primary_plane;
14105 } else if (HAS_PCH_SPLIT(dev)) {
14106 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14107 dev_priv->display.get_initial_plane_config =
14108 ironlake_get_initial_plane_config;
14109 dev_priv->display.crtc_compute_clock =
14110 ironlake_crtc_compute_clock;
14111 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14112 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14113 dev_priv->display.off = ironlake_crtc_off;
14114 dev_priv->display.update_primary_plane =
14115 ironlake_update_primary_plane;
14116 } else if (IS_VALLEYVIEW(dev)) {
14117 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14118 dev_priv->display.get_initial_plane_config =
14119 i9xx_get_initial_plane_config;
14120 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14121 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14122 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14123 dev_priv->display.off = i9xx_crtc_off;
14124 dev_priv->display.update_primary_plane =
14125 i9xx_update_primary_plane;
14126 } else {
14127 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14128 dev_priv->display.get_initial_plane_config =
14129 i9xx_get_initial_plane_config;
14130 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14131 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14132 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14133 dev_priv->display.off = i9xx_crtc_off;
14134 dev_priv->display.update_primary_plane =
14135 i9xx_update_primary_plane;
14136 }
14137
14138 /* Returns the core display clock speed */
14139 if (IS_SKYLAKE(dev))
14140 dev_priv->display.get_display_clock_speed =
14141 skylake_get_display_clock_speed;
14142 else if (IS_BROADWELL(dev))
14143 dev_priv->display.get_display_clock_speed =
14144 broadwell_get_display_clock_speed;
14145 else if (IS_HASWELL(dev))
14146 dev_priv->display.get_display_clock_speed =
14147 haswell_get_display_clock_speed;
14148 else if (IS_VALLEYVIEW(dev))
14149 dev_priv->display.get_display_clock_speed =
14150 valleyview_get_display_clock_speed;
14151 else if (IS_GEN5(dev))
14152 dev_priv->display.get_display_clock_speed =
14153 ilk_get_display_clock_speed;
14154 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14155 IS_GEN6(dev) || IS_IVYBRIDGE(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
14156 dev_priv->display.get_display_clock_speed =
14157 i945_get_display_clock_speed;
14158 else if (IS_I915G(dev))
14159 dev_priv->display.get_display_clock_speed =
14160 i915_get_display_clock_speed;
14161 else if (IS_I945GM(dev) || IS_845G(dev))
14162 dev_priv->display.get_display_clock_speed =
14163 i9xx_misc_get_display_clock_speed;
14164 else if (IS_PINEVIEW(dev))
14165 dev_priv->display.get_display_clock_speed =
14166 pnv_get_display_clock_speed;
14167 else if (IS_I915GM(dev))
14168 dev_priv->display.get_display_clock_speed =
14169 i915gm_get_display_clock_speed;
14170 else if (IS_I865G(dev))
14171 dev_priv->display.get_display_clock_speed =
14172 i865_get_display_clock_speed;
14173 else if (IS_I85X(dev))
14174 dev_priv->display.get_display_clock_speed =
14175 i855_get_display_clock_speed;
14176 else /* 852, 830 */
14177 dev_priv->display.get_display_clock_speed =
14178 i830_get_display_clock_speed;
14179
14180 if (IS_GEN5(dev)) {
14181 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14182 } else if (IS_GEN6(dev)) {
14183 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14184 } else if (IS_IVYBRIDGE(dev)) {
14185 /* FIXME: detect B0+ stepping and use auto training */
14186 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14187 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14188 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14189 } else if (IS_VALLEYVIEW(dev)) {
14190 dev_priv->display.modeset_global_resources =
14191 valleyview_modeset_global_resources;
14192 } else if (IS_BROXTON(dev)) {
14193 dev_priv->display.modeset_global_resources =
14194 broxton_modeset_global_resources;
14195 }
14196
14197 switch (INTEL_INFO(dev)->gen) {
14198 case 2:
14199 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14200 break;
14201
14202 case 3:
14203 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14204 break;
14205
14206 case 4:
14207 case 5:
14208 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14209 break;
14210
14211 case 6:
14212 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14213 break;
14214 case 7:
14215 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14216 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14217 break;
14218 case 9:
14219 /* Drop through - unsupported since execlist only. */
14220 default:
14221 /* Default just returns -ENODEV to indicate unsupported */
14222 dev_priv->display.queue_flip = intel_default_queue_flip;
14223 }
14224
14225 intel_panel_init_backlight_funcs(dev);
14226
14227 mutex_init(&dev_priv->pps_mutex);
14228 }
14229
14230 /*
14231 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14232 * resume, or other times. This quirk makes sure that's the case for
14233 * affected systems.
14234 */
14235 static void quirk_pipea_force(struct drm_device *dev)
14236 {
14237 struct drm_i915_private *dev_priv = dev->dev_private;
14238
14239 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14240 DRM_INFO("applying pipe a force quirk\n");
14241 }
14242
14243 static void quirk_pipeb_force(struct drm_device *dev)
14244 {
14245 struct drm_i915_private *dev_priv = dev->dev_private;
14246
14247 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14248 DRM_INFO("applying pipe b force quirk\n");
14249 }
14250
14251 /*
14252 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14253 */
14254 static void quirk_ssc_force_disable(struct drm_device *dev)
14255 {
14256 struct drm_i915_private *dev_priv = dev->dev_private;
14257 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14258 DRM_INFO("applying lvds SSC disable quirk\n");
14259 }
14260
14261 /*
14262 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14263 * brightness value
14264 */
14265 static void quirk_invert_brightness(struct drm_device *dev)
14266 {
14267 struct drm_i915_private *dev_priv = dev->dev_private;
14268 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14269 DRM_INFO("applying inverted panel brightness quirk\n");
14270 }
14271
14272 /* Some VBT's incorrectly indicate no backlight is present */
14273 static void quirk_backlight_present(struct drm_device *dev)
14274 {
14275 struct drm_i915_private *dev_priv = dev->dev_private;
14276 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14277 DRM_INFO("applying backlight present quirk\n");
14278 }
14279
14280 struct intel_quirk {
14281 int device;
14282 int subsystem_vendor;
14283 int subsystem_device;
14284 void (*hook)(struct drm_device *dev);
14285 };
14286
14287 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14288 struct intel_dmi_quirk {
14289 void (*hook)(struct drm_device *dev);
14290 const struct dmi_system_id (*dmi_id_list)[];
14291 };
14292
14293 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14294 {
14295 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14296 return 1;
14297 }
14298
14299 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14300 {
14301 .dmi_id_list = &(const struct dmi_system_id[]) {
14302 {
14303 .callback = intel_dmi_reverse_brightness,
14304 .ident = "NCR Corporation",
14305 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14306 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14307 },
14308 },
14309 { } /* terminating entry */
14310 },
14311 .hook = quirk_invert_brightness,
14312 },
14313 };
14314
14315 static struct intel_quirk intel_quirks[] = {
14316 /* HP Mini needs pipe A force quirk (LP: #322104) */
14317 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
14318
14319 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14320 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14321
14322 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14323 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14324
14325 /* 830 needs to leave pipe A & dpll A up */
14326 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14327
14328 /* 830 needs to leave pipe B & dpll B up */
14329 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14330
14331 /* Lenovo U160 cannot use SSC on LVDS */
14332 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14333
14334 /* Sony Vaio Y cannot use SSC on LVDS */
14335 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14336
14337 /* Acer Aspire 5734Z must invert backlight brightness */
14338 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14339
14340 /* Acer/eMachines G725 */
14341 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14342
14343 /* Acer/eMachines e725 */
14344 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14345
14346 /* Acer/Packard Bell NCL20 */
14347 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14348
14349 /* Acer Aspire 4736Z */
14350 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14351
14352 /* Acer Aspire 5336 */
14353 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14354
14355 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14356 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14357
14358 /* Acer C720 Chromebook (Core i3 4005U) */
14359 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14360
14361 /* Apple Macbook 2,1 (Core 2 T7400) */
14362 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14363
14364 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14365 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14366
14367 /* HP Chromebook 14 (Celeron 2955U) */
14368 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14369
14370 /* Dell Chromebook 11 */
14371 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14372 };
14373
14374 static void intel_init_quirks(struct drm_device *dev)
14375 {
14376 struct pci_dev *d = dev->pdev;
14377 int i;
14378
14379 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14380 struct intel_quirk *q = &intel_quirks[i];
14381
14382 if (d->device == q->device &&
14383 (d->subsystem_vendor == q->subsystem_vendor ||
14384 q->subsystem_vendor == PCI_ANY_ID) &&
14385 (d->subsystem_device == q->subsystem_device ||
14386 q->subsystem_device == PCI_ANY_ID))
14387 q->hook(dev);
14388 }
14389 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14390 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14391 intel_dmi_quirks[i].hook(dev);
14392 }
14393 }
14394
14395 /* Disable the VGA plane that we never use */
14396 static void i915_disable_vga(struct drm_device *dev)
14397 {
14398 struct drm_i915_private *dev_priv = dev->dev_private;
14399 u8 sr1;
14400 u32 vga_reg = i915_vgacntrl_reg(dev);
14401
14402 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14403 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14404 outb(SR01, VGA_SR_INDEX);
14405 sr1 = inb(VGA_SR_DATA);
14406 outb(sr1 | 1<<5, VGA_SR_DATA);
14407 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14408 udelay(300);
14409
14410 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14411 POSTING_READ(vga_reg);
14412 }
14413
14414 void intel_modeset_init_hw(struct drm_device *dev)
14415 {
14416 intel_prepare_ddi(dev);
14417
14418 if (IS_VALLEYVIEW(dev))
14419 vlv_update_cdclk(dev);
14420
14421 intel_init_clock_gating(dev);
14422
14423 intel_enable_gt_powersave(dev);
14424 }
14425
14426 void intel_modeset_init(struct drm_device *dev)
14427 {
14428 struct drm_i915_private *dev_priv = dev->dev_private;
14429 int sprite, ret;
14430 enum pipe pipe;
14431 struct intel_crtc *crtc;
14432
14433 drm_mode_config_init(dev);
14434
14435 dev->mode_config.min_width = 0;
14436 dev->mode_config.min_height = 0;
14437
14438 dev->mode_config.preferred_depth = 24;
14439 dev->mode_config.prefer_shadow = 1;
14440
14441 dev->mode_config.allow_fb_modifiers = true;
14442
14443 dev->mode_config.funcs = &intel_mode_funcs;
14444
14445 intel_init_quirks(dev);
14446
14447 intel_init_pm(dev);
14448
14449 if (INTEL_INFO(dev)->num_pipes == 0)
14450 return;
14451
14452 intel_init_display(dev);
14453 intel_init_audio(dev);
14454
14455 if (IS_GEN2(dev)) {
14456 dev->mode_config.max_width = 2048;
14457 dev->mode_config.max_height = 2048;
14458 } else if (IS_GEN3(dev)) {
14459 dev->mode_config.max_width = 4096;
14460 dev->mode_config.max_height = 4096;
14461 } else {
14462 dev->mode_config.max_width = 8192;
14463 dev->mode_config.max_height = 8192;
14464 }
14465
14466 if (IS_845G(dev) || IS_I865G(dev)) {
14467 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14468 dev->mode_config.cursor_height = 1023;
14469 } else if (IS_GEN2(dev)) {
14470 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14471 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14472 } else {
14473 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14474 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14475 }
14476
14477 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
14478
14479 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14480 INTEL_INFO(dev)->num_pipes,
14481 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
14482
14483 for_each_pipe(dev_priv, pipe) {
14484 intel_crtc_init(dev, pipe);
14485 for_each_sprite(dev_priv, pipe, sprite) {
14486 ret = intel_plane_init(dev, pipe, sprite);
14487 if (ret)
14488 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14489 pipe_name(pipe), sprite_name(pipe, sprite), ret);
14490 }
14491 }
14492
14493 intel_init_dpio(dev);
14494
14495 intel_shared_dpll_init(dev);
14496
14497 /* Just disable it once at startup */
14498 i915_disable_vga(dev);
14499 intel_setup_outputs(dev);
14500
14501 /* Just in case the BIOS is doing something questionable. */
14502 intel_fbc_disable(dev);
14503
14504 drm_modeset_lock_all(dev);
14505 intel_modeset_setup_hw_state(dev, false);
14506 drm_modeset_unlock_all(dev);
14507
14508 for_each_intel_crtc(dev, crtc) {
14509 if (!crtc->active)
14510 continue;
14511
14512 /*
14513 * Note that reserving the BIOS fb up front prevents us
14514 * from stuffing other stolen allocations like the ring
14515 * on top. This prevents some ugliness at boot time, and
14516 * can even allow for smooth boot transitions if the BIOS
14517 * fb is large enough for the active pipe configuration.
14518 */
14519 if (dev_priv->display.get_initial_plane_config) {
14520 dev_priv->display.get_initial_plane_config(crtc,
14521 &crtc->plane_config);
14522 /*
14523 * If the fb is shared between multiple heads, we'll
14524 * just get the first one.
14525 */
14526 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
14527 }
14528 }
14529 }
14530
14531 static void intel_enable_pipe_a(struct drm_device *dev)
14532 {
14533 struct intel_connector *connector;
14534 struct drm_connector *crt = NULL;
14535 struct intel_load_detect_pipe load_detect_temp;
14536 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
14537
14538 /* We can't just switch on the pipe A, we need to set things up with a
14539 * proper mode and output configuration. As a gross hack, enable pipe A
14540 * by enabling the load detect pipe once. */
14541 for_each_intel_connector(dev, connector) {
14542 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14543 crt = &connector->base;
14544 break;
14545 }
14546 }
14547
14548 if (!crt)
14549 return;
14550
14551 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
14552 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
14553 }
14554
14555 static bool
14556 intel_check_plane_mapping(struct intel_crtc *crtc)
14557 {
14558 struct drm_device *dev = crtc->base.dev;
14559 struct drm_i915_private *dev_priv = dev->dev_private;
14560 u32 reg, val;
14561
14562 if (INTEL_INFO(dev)->num_pipes == 1)
14563 return true;
14564
14565 reg = DSPCNTR(!crtc->plane);
14566 val = I915_READ(reg);
14567
14568 if ((val & DISPLAY_PLANE_ENABLE) &&
14569 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14570 return false;
14571
14572 return true;
14573 }
14574
14575 static void intel_sanitize_crtc(struct intel_crtc *crtc)
14576 {
14577 struct drm_device *dev = crtc->base.dev;
14578 struct drm_i915_private *dev_priv = dev->dev_private;
14579 u32 reg;
14580
14581 /* Clear any frame start delays used for debugging left by the BIOS */
14582 reg = PIPECONF(crtc->config->cpu_transcoder);
14583 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14584
14585 /* restore vblank interrupts to correct state */
14586 drm_crtc_vblank_reset(&crtc->base);
14587 if (crtc->active) {
14588 update_scanline_offset(crtc);
14589 drm_crtc_vblank_on(&crtc->base);
14590 }
14591
14592 /* We need to sanitize the plane -> pipe mapping first because this will
14593 * disable the crtc (and hence change the state) if it is wrong. Note
14594 * that gen4+ has a fixed plane -> pipe mapping. */
14595 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
14596 struct intel_connector *connector;
14597 bool plane;
14598
14599 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14600 crtc->base.base.id);
14601
14602 /* Pipe has the wrong plane attached and the plane is active.
14603 * Temporarily change the plane mapping and disable everything
14604 * ... */
14605 plane = crtc->plane;
14606 to_intel_plane_state(crtc->base.primary->state)->visible = true;
14607 crtc->plane = !plane;
14608 intel_crtc_disable_planes(&crtc->base);
14609 dev_priv->display.crtc_disable(&crtc->base);
14610 crtc->plane = plane;
14611
14612 /* ... and break all links. */
14613 for_each_intel_connector(dev, connector) {
14614 if (connector->encoder->base.crtc != &crtc->base)
14615 continue;
14616
14617 connector->base.dpms = DRM_MODE_DPMS_OFF;
14618 connector->base.encoder = NULL;
14619 }
14620 /* multiple connectors may have the same encoder:
14621 * handle them and break crtc link separately */
14622 for_each_intel_connector(dev, connector)
14623 if (connector->encoder->base.crtc == &crtc->base) {
14624 connector->encoder->base.crtc = NULL;
14625 connector->encoder->connectors_active = false;
14626 }
14627
14628 WARN_ON(crtc->active);
14629 crtc->base.state->enable = false;
14630 crtc->base.enabled = false;
14631 }
14632
14633 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14634 crtc->pipe == PIPE_A && !crtc->active) {
14635 /* BIOS forgot to enable pipe A, this mostly happens after
14636 * resume. Force-enable the pipe to fix this, the update_dpms
14637 * call below we restore the pipe to the right state, but leave
14638 * the required bits on. */
14639 intel_enable_pipe_a(dev);
14640 }
14641
14642 /* Adjust the state of the output pipe according to whether we
14643 * have active connectors/encoders. */
14644 intel_crtc_update_dpms(&crtc->base);
14645
14646 if (crtc->active != crtc->base.state->enable) {
14647 struct intel_encoder *encoder;
14648
14649 /* This can happen either due to bugs in the get_hw_state
14650 * functions or because the pipe is force-enabled due to the
14651 * pipe A quirk. */
14652 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14653 crtc->base.base.id,
14654 crtc->base.state->enable ? "enabled" : "disabled",
14655 crtc->active ? "enabled" : "disabled");
14656
14657 crtc->base.state->enable = crtc->active;
14658 crtc->base.enabled = crtc->active;
14659
14660 /* Because we only establish the connector -> encoder ->
14661 * crtc links if something is active, this means the
14662 * crtc is now deactivated. Break the links. connector
14663 * -> encoder links are only establish when things are
14664 * actually up, hence no need to break them. */
14665 WARN_ON(crtc->active);
14666
14667 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
14668 WARN_ON(encoder->connectors_active);
14669 encoder->base.crtc = NULL;
14670 }
14671 }
14672
14673 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
14674 /*
14675 * We start out with underrun reporting disabled to avoid races.
14676 * For correct bookkeeping mark this on active crtcs.
14677 *
14678 * Also on gmch platforms we dont have any hardware bits to
14679 * disable the underrun reporting. Which means we need to start
14680 * out with underrun reporting disabled also on inactive pipes,
14681 * since otherwise we'll complain about the garbage we read when
14682 * e.g. coming up after runtime pm.
14683 *
14684 * No protection against concurrent access is required - at
14685 * worst a fifo underrun happens which also sets this to false.
14686 */
14687 crtc->cpu_fifo_underrun_disabled = true;
14688 crtc->pch_fifo_underrun_disabled = true;
14689 }
14690 }
14691
14692 static void intel_sanitize_encoder(struct intel_encoder *encoder)
14693 {
14694 struct intel_connector *connector;
14695 struct drm_device *dev = encoder->base.dev;
14696
14697 /* We need to check both for a crtc link (meaning that the
14698 * encoder is active and trying to read from a pipe) and the
14699 * pipe itself being active. */
14700 bool has_active_crtc = encoder->base.crtc &&
14701 to_intel_crtc(encoder->base.crtc)->active;
14702
14703 if (encoder->connectors_active && !has_active_crtc) {
14704 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14705 encoder->base.base.id,
14706 encoder->base.name);
14707
14708 /* Connector is active, but has no active pipe. This is
14709 * fallout from our resume register restoring. Disable
14710 * the encoder manually again. */
14711 if (encoder->base.crtc) {
14712 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14713 encoder->base.base.id,
14714 encoder->base.name);
14715 encoder->disable(encoder);
14716 if (encoder->post_disable)
14717 encoder->post_disable(encoder);
14718 }
14719 encoder->base.crtc = NULL;
14720 encoder->connectors_active = false;
14721
14722 /* Inconsistent output/port/pipe state happens presumably due to
14723 * a bug in one of the get_hw_state functions. Or someplace else
14724 * in our code, like the register restore mess on resume. Clamp
14725 * things to off as a safer default. */
14726 for_each_intel_connector(dev, connector) {
14727 if (connector->encoder != encoder)
14728 continue;
14729 connector->base.dpms = DRM_MODE_DPMS_OFF;
14730 connector->base.encoder = NULL;
14731 }
14732 }
14733 /* Enabled encoders without active connectors will be fixed in
14734 * the crtc fixup. */
14735 }
14736
14737 void i915_redisable_vga_power_on(struct drm_device *dev)
14738 {
14739 struct drm_i915_private *dev_priv = dev->dev_private;
14740 u32 vga_reg = i915_vgacntrl_reg(dev);
14741
14742 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
14743 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14744 i915_disable_vga(dev);
14745 }
14746 }
14747
14748 void i915_redisable_vga(struct drm_device *dev)
14749 {
14750 struct drm_i915_private *dev_priv = dev->dev_private;
14751
14752 /* This function can be called both from intel_modeset_setup_hw_state or
14753 * at a very early point in our resume sequence, where the power well
14754 * structures are not yet restored. Since this function is at a very
14755 * paranoid "someone might have enabled VGA while we were not looking"
14756 * level, just check if the power well is enabled instead of trying to
14757 * follow the "don't touch the power well if we don't need it" policy
14758 * the rest of the driver uses. */
14759 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
14760 return;
14761
14762 i915_redisable_vga_power_on(dev);
14763 }
14764
14765 static bool primary_get_hw_state(struct intel_crtc *crtc)
14766 {
14767 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
14768
14769 if (!crtc->active)
14770 return false;
14771
14772 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
14773 }
14774
14775 static void intel_modeset_readout_hw_state(struct drm_device *dev)
14776 {
14777 struct drm_i915_private *dev_priv = dev->dev_private;
14778 enum pipe pipe;
14779 struct intel_crtc *crtc;
14780 struct intel_encoder *encoder;
14781 struct intel_connector *connector;
14782 int i;
14783
14784 for_each_intel_crtc(dev, crtc) {
14785 struct drm_plane *primary = crtc->base.primary;
14786 struct intel_plane_state *plane_state;
14787
14788 memset(crtc->config, 0, sizeof(*crtc->config));
14789
14790 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
14791
14792 crtc->active = dev_priv->display.get_pipe_config(crtc,
14793 crtc->config);
14794
14795 crtc->base.state->enable = crtc->active;
14796 crtc->base.enabled = crtc->active;
14797
14798 plane_state = to_intel_plane_state(primary->state);
14799 plane_state->visible = primary_get_hw_state(crtc);
14800
14801 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
14802 crtc->base.base.id,
14803 crtc->active ? "enabled" : "disabled");
14804 }
14805
14806 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14807 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14808
14809 pll->on = pll->get_hw_state(dev_priv, pll,
14810 &pll->config.hw_state);
14811 pll->active = 0;
14812 pll->config.crtc_mask = 0;
14813 for_each_intel_crtc(dev, crtc) {
14814 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
14815 pll->active++;
14816 pll->config.crtc_mask |= 1 << crtc->pipe;
14817 }
14818 }
14819
14820 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
14821 pll->name, pll->config.crtc_mask, pll->on);
14822
14823 if (pll->config.crtc_mask)
14824 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
14825 }
14826
14827 for_each_intel_encoder(dev, encoder) {
14828 pipe = 0;
14829
14830 if (encoder->get_hw_state(encoder, &pipe)) {
14831 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
14832 encoder->base.crtc = &crtc->base;
14833 encoder->get_config(encoder, crtc->config);
14834 } else {
14835 encoder->base.crtc = NULL;
14836 }
14837
14838 encoder->connectors_active = false;
14839 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
14840 encoder->base.base.id,
14841 encoder->base.name,
14842 encoder->base.crtc ? "enabled" : "disabled",
14843 pipe_name(pipe));
14844 }
14845
14846 for_each_intel_connector(dev, connector) {
14847 if (connector->get_hw_state(connector)) {
14848 connector->base.dpms = DRM_MODE_DPMS_ON;
14849 connector->encoder->connectors_active = true;
14850 connector->base.encoder = &connector->encoder->base;
14851 } else {
14852 connector->base.dpms = DRM_MODE_DPMS_OFF;
14853 connector->base.encoder = NULL;
14854 }
14855 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
14856 connector->base.base.id,
14857 connector->base.name,
14858 connector->base.encoder ? "enabled" : "disabled");
14859 }
14860 }
14861
14862 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
14863 * and i915 state tracking structures. */
14864 void intel_modeset_setup_hw_state(struct drm_device *dev,
14865 bool force_restore)
14866 {
14867 struct drm_i915_private *dev_priv = dev->dev_private;
14868 enum pipe pipe;
14869 struct intel_crtc *crtc;
14870 struct intel_encoder *encoder;
14871 int i;
14872
14873 intel_modeset_readout_hw_state(dev);
14874
14875 /*
14876 * Now that we have the config, copy it to each CRTC struct
14877 * Note that this could go away if we move to using crtc_config
14878 * checking everywhere.
14879 */
14880 for_each_intel_crtc(dev, crtc) {
14881 if (crtc->active && i915.fastboot) {
14882 intel_mode_from_pipe_config(&crtc->base.mode,
14883 crtc->config);
14884 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
14885 crtc->base.base.id);
14886 drm_mode_debug_printmodeline(&crtc->base.mode);
14887 }
14888 }
14889
14890 /* HW state is read out, now we need to sanitize this mess. */
14891 for_each_intel_encoder(dev, encoder) {
14892 intel_sanitize_encoder(encoder);
14893 }
14894
14895 for_each_pipe(dev_priv, pipe) {
14896 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
14897 intel_sanitize_crtc(crtc);
14898 intel_dump_pipe_config(crtc, crtc->config,
14899 "[setup_hw_state]");
14900 }
14901
14902 intel_modeset_update_connector_atomic_state(dev);
14903
14904 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14905 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14906
14907 if (!pll->on || pll->active)
14908 continue;
14909
14910 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
14911
14912 pll->disable(dev_priv, pll);
14913 pll->on = false;
14914 }
14915
14916 if (IS_GEN9(dev))
14917 skl_wm_get_hw_state(dev);
14918 else if (HAS_PCH_SPLIT(dev))
14919 ilk_wm_get_hw_state(dev);
14920
14921 if (force_restore) {
14922 i915_redisable_vga(dev);
14923
14924 /*
14925 * We need to use raw interfaces for restoring state to avoid
14926 * checking (bogus) intermediate states.
14927 */
14928 for_each_pipe(dev_priv, pipe) {
14929 struct drm_crtc *crtc =
14930 dev_priv->pipe_to_crtc_mapping[pipe];
14931
14932 intel_crtc_restore_mode(crtc);
14933 }
14934 } else {
14935 intel_modeset_update_staged_output_state(dev);
14936 }
14937
14938 intel_modeset_check_state(dev);
14939 }
14940
14941 void intel_modeset_gem_init(struct drm_device *dev)
14942 {
14943 struct drm_i915_private *dev_priv = dev->dev_private;
14944 struct drm_crtc *c;
14945 struct drm_i915_gem_object *obj;
14946 int ret;
14947
14948 mutex_lock(&dev->struct_mutex);
14949 intel_init_gt_powersave(dev);
14950 mutex_unlock(&dev->struct_mutex);
14951
14952 /*
14953 * There may be no VBT; and if the BIOS enabled SSC we can
14954 * just keep using it to avoid unnecessary flicker. Whereas if the
14955 * BIOS isn't using it, don't assume it will work even if the VBT
14956 * indicates as much.
14957 */
14958 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
14959 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14960 DREF_SSC1_ENABLE);
14961
14962 intel_modeset_init_hw(dev);
14963
14964 intel_setup_overlay(dev);
14965
14966 /*
14967 * Make sure any fbs we allocated at startup are properly
14968 * pinned & fenced. When we do the allocation it's too early
14969 * for this.
14970 */
14971 for_each_crtc(dev, c) {
14972 obj = intel_fb_obj(c->primary->fb);
14973 if (obj == NULL)
14974 continue;
14975
14976 mutex_lock(&dev->struct_mutex);
14977 ret = intel_pin_and_fence_fb_obj(c->primary,
14978 c->primary->fb,
14979 c->primary->state,
14980 NULL);
14981 mutex_unlock(&dev->struct_mutex);
14982 if (ret) {
14983 DRM_ERROR("failed to pin boot fb on pipe %d\n",
14984 to_intel_crtc(c)->pipe);
14985 drm_framebuffer_unreference(c->primary->fb);
14986 c->primary->fb = NULL;
14987 update_state_fb(c->primary);
14988 }
14989 }
14990
14991 intel_backlight_register(dev);
14992 }
14993
14994 void intel_connector_unregister(struct intel_connector *intel_connector)
14995 {
14996 struct drm_connector *connector = &intel_connector->base;
14997
14998 intel_panel_destroy_backlight(connector);
14999 drm_connector_unregister(connector);
15000 }
15001
15002 void intel_modeset_cleanup(struct drm_device *dev)
15003 {
15004 struct drm_i915_private *dev_priv = dev->dev_private;
15005 struct drm_connector *connector;
15006
15007 intel_disable_gt_powersave(dev);
15008
15009 intel_backlight_unregister(dev);
15010
15011 /*
15012 * Interrupts and polling as the first thing to avoid creating havoc.
15013 * Too much stuff here (turning of connectors, ...) would
15014 * experience fancy races otherwise.
15015 */
15016 intel_irq_uninstall(dev_priv);
15017
15018 /*
15019 * Due to the hpd irq storm handling the hotplug work can re-arm the
15020 * poll handlers. Hence disable polling after hpd handling is shut down.
15021 */
15022 drm_kms_helper_poll_fini(dev);
15023
15024 mutex_lock(&dev->struct_mutex);
15025
15026 intel_unregister_dsm_handler();
15027
15028 intel_fbc_disable(dev);
15029
15030 mutex_unlock(&dev->struct_mutex);
15031
15032 /* flush any delayed tasks or pending work */
15033 flush_scheduled_work();
15034
15035 /* destroy the backlight and sysfs files before encoders/connectors */
15036 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15037 struct intel_connector *intel_connector;
15038
15039 intel_connector = to_intel_connector(connector);
15040 intel_connector->unregister(intel_connector);
15041 }
15042
15043 drm_mode_config_cleanup(dev);
15044
15045 intel_cleanup_overlay(dev);
15046
15047 mutex_lock(&dev->struct_mutex);
15048 intel_cleanup_gt_powersave(dev);
15049 mutex_unlock(&dev->struct_mutex);
15050 }
15051
15052 /*
15053 * Return which encoder is currently attached for connector.
15054 */
15055 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15056 {
15057 return &intel_attached_encoder(connector)->base;
15058 }
15059
15060 void intel_connector_attach_encoder(struct intel_connector *connector,
15061 struct intel_encoder *encoder)
15062 {
15063 connector->encoder = encoder;
15064 drm_mode_connector_attach_encoder(&connector->base,
15065 &encoder->base);
15066 }
15067
15068 /*
15069 * set vga decode state - true == enable VGA decode
15070 */
15071 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15072 {
15073 struct drm_i915_private *dev_priv = dev->dev_private;
15074 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15075 u16 gmch_ctrl;
15076
15077 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15078 DRM_ERROR("failed to read control word\n");
15079 return -EIO;
15080 }
15081
15082 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15083 return 0;
15084
15085 if (state)
15086 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15087 else
15088 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15089
15090 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15091 DRM_ERROR("failed to write control word\n");
15092 return -EIO;
15093 }
15094
15095 return 0;
15096 }
15097
15098 struct intel_display_error_state {
15099
15100 u32 power_well_driver;
15101
15102 int num_transcoders;
15103
15104 struct intel_cursor_error_state {
15105 u32 control;
15106 u32 position;
15107 u32 base;
15108 u32 size;
15109 } cursor[I915_MAX_PIPES];
15110
15111 struct intel_pipe_error_state {
15112 bool power_domain_on;
15113 u32 source;
15114 u32 stat;
15115 } pipe[I915_MAX_PIPES];
15116
15117 struct intel_plane_error_state {
15118 u32 control;
15119 u32 stride;
15120 u32 size;
15121 u32 pos;
15122 u32 addr;
15123 u32 surface;
15124 u32 tile_offset;
15125 } plane[I915_MAX_PIPES];
15126
15127 struct intel_transcoder_error_state {
15128 bool power_domain_on;
15129 enum transcoder cpu_transcoder;
15130
15131 u32 conf;
15132
15133 u32 htotal;
15134 u32 hblank;
15135 u32 hsync;
15136 u32 vtotal;
15137 u32 vblank;
15138 u32 vsync;
15139 } transcoder[4];
15140 };
15141
15142 struct intel_display_error_state *
15143 intel_display_capture_error_state(struct drm_device *dev)
15144 {
15145 struct drm_i915_private *dev_priv = dev->dev_private;
15146 struct intel_display_error_state *error;
15147 int transcoders[] = {
15148 TRANSCODER_A,
15149 TRANSCODER_B,
15150 TRANSCODER_C,
15151 TRANSCODER_EDP,
15152 };
15153 int i;
15154
15155 if (INTEL_INFO(dev)->num_pipes == 0)
15156 return NULL;
15157
15158 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15159 if (error == NULL)
15160 return NULL;
15161
15162 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15163 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15164
15165 for_each_pipe(dev_priv, i) {
15166 error->pipe[i].power_domain_on =
15167 __intel_display_power_is_enabled(dev_priv,
15168 POWER_DOMAIN_PIPE(i));
15169 if (!error->pipe[i].power_domain_on)
15170 continue;
15171
15172 error->cursor[i].control = I915_READ(CURCNTR(i));
15173 error->cursor[i].position = I915_READ(CURPOS(i));
15174 error->cursor[i].base = I915_READ(CURBASE(i));
15175
15176 error->plane[i].control = I915_READ(DSPCNTR(i));
15177 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15178 if (INTEL_INFO(dev)->gen <= 3) {
15179 error->plane[i].size = I915_READ(DSPSIZE(i));
15180 error->plane[i].pos = I915_READ(DSPPOS(i));
15181 }
15182 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15183 error->plane[i].addr = I915_READ(DSPADDR(i));
15184 if (INTEL_INFO(dev)->gen >= 4) {
15185 error->plane[i].surface = I915_READ(DSPSURF(i));
15186 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15187 }
15188
15189 error->pipe[i].source = I915_READ(PIPESRC(i));
15190
15191 if (HAS_GMCH_DISPLAY(dev))
15192 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15193 }
15194
15195 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15196 if (HAS_DDI(dev_priv->dev))
15197 error->num_transcoders++; /* Account for eDP. */
15198
15199 for (i = 0; i < error->num_transcoders; i++) {
15200 enum transcoder cpu_transcoder = transcoders[i];
15201
15202 error->transcoder[i].power_domain_on =
15203 __intel_display_power_is_enabled(dev_priv,
15204 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15205 if (!error->transcoder[i].power_domain_on)
15206 continue;
15207
15208 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15209
15210 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15211 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15212 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15213 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15214 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15215 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15216 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15217 }
15218
15219 return error;
15220 }
15221
15222 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15223
15224 void
15225 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15226 struct drm_device *dev,
15227 struct intel_display_error_state *error)
15228 {
15229 struct drm_i915_private *dev_priv = dev->dev_private;
15230 int i;
15231
15232 if (!error)
15233 return;
15234
15235 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15236 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15237 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15238 error->power_well_driver);
15239 for_each_pipe(dev_priv, i) {
15240 err_printf(m, "Pipe [%d]:\n", i);
15241 err_printf(m, " Power: %s\n",
15242 error->pipe[i].power_domain_on ? "on" : "off");
15243 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15244 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15245
15246 err_printf(m, "Plane [%d]:\n", i);
15247 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15248 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15249 if (INTEL_INFO(dev)->gen <= 3) {
15250 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15251 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15252 }
15253 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15254 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15255 if (INTEL_INFO(dev)->gen >= 4) {
15256 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15257 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15258 }
15259
15260 err_printf(m, "Cursor [%d]:\n", i);
15261 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15262 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15263 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15264 }
15265
15266 for (i = 0; i < error->num_transcoders; i++) {
15267 err_printf(m, "CPU transcoder: %c\n",
15268 transcoder_name(error->transcoder[i].cpu_transcoder));
15269 err_printf(m, " Power: %s\n",
15270 error->transcoder[i].power_domain_on ? "on" : "off");
15271 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15272 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15273 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15274 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15275 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15276 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15277 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15278 }
15279 }
15280
15281 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15282 {
15283 struct intel_crtc *crtc;
15284
15285 for_each_intel_crtc(dev, crtc) {
15286 struct intel_unpin_work *work;
15287
15288 spin_lock_irq(&dev->event_lock);
15289
15290 work = crtc->unpin_work;
15291
15292 if (work && work->event &&
15293 work->event->base.file_priv == file) {
15294 kfree(work->event);
15295 work->event = NULL;
15296 }
15297
15298 spin_unlock_irq(&dev->event_lock);
15299 }
15300 }
Linux kernel - Deliverables
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