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drm/i915: Print the pipe on which the vblank wait times out
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_rect.h>
44 #include <linux/dma_remapping.h>
45
46 /* Primary plane formats supported by all gen */
47 #define COMMON_PRIMARY_FORMATS \
48 DRM_FORMAT_C8, \
49 DRM_FORMAT_RGB565, \
50 DRM_FORMAT_XRGB8888, \
51 DRM_FORMAT_ARGB8888
52
53 /* Primary plane formats for gen <= 3 */
54 static const uint32_t intel_primary_formats_gen2[] = {
55 COMMON_PRIMARY_FORMATS,
56 DRM_FORMAT_XRGB1555,
57 DRM_FORMAT_ARGB1555,
58 };
59
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t intel_primary_formats_gen4[] = {
62 COMMON_PRIMARY_FORMATS, \
63 DRM_FORMAT_XBGR8888,
64 DRM_FORMAT_ABGR8888,
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_ARGB2101010,
67 DRM_FORMAT_XBGR2101010,
68 DRM_FORMAT_ABGR2101010,
69 };
70
71 /* Cursor formats */
72 static const uint32_t intel_cursor_formats[] = {
73 DRM_FORMAT_ARGB8888,
74 };
75
76 #define DIV_ROUND_CLOSEST_ULL(ll, d) \
77 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
78
79 static void intel_increase_pllclock(struct drm_device *dev,
80 enum pipe pipe);
81 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
82
83 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
84 struct intel_crtc_config *pipe_config);
85 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
86 struct intel_crtc_config *pipe_config);
87
88 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
89 int x, int y, struct drm_framebuffer *old_fb);
90 static int intel_framebuffer_init(struct drm_device *dev,
91 struct intel_framebuffer *ifb,
92 struct drm_mode_fb_cmd2 *mode_cmd,
93 struct drm_i915_gem_object *obj);
94 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
95 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
96 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
97 struct intel_link_m_n *m_n,
98 struct intel_link_m_n *m2_n2);
99 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
100 static void haswell_set_pipeconf(struct drm_crtc *crtc);
101 static void intel_set_pipe_csc(struct drm_crtc *crtc);
102 static void vlv_prepare_pll(struct intel_crtc *crtc);
103 static void chv_prepare_pll(struct intel_crtc *crtc);
104
105 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
106 {
107 if (!connector->mst_port)
108 return connector->encoder;
109 else
110 return &connector->mst_port->mst_encoders[pipe]->base;
111 }
112
113 typedef struct {
114 int min, max;
115 } intel_range_t;
116
117 typedef struct {
118 int dot_limit;
119 int p2_slow, p2_fast;
120 } intel_p2_t;
121
122 typedef struct intel_limit intel_limit_t;
123 struct intel_limit {
124 intel_range_t dot, vco, n, m, m1, m2, p, p1;
125 intel_p2_t p2;
126 };
127
128 int
129 intel_pch_rawclk(struct drm_device *dev)
130 {
131 struct drm_i915_private *dev_priv = dev->dev_private;
132
133 WARN_ON(!HAS_PCH_SPLIT(dev));
134
135 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
136 }
137
138 static inline u32 /* units of 100MHz */
139 intel_fdi_link_freq(struct drm_device *dev)
140 {
141 if (IS_GEN5(dev)) {
142 struct drm_i915_private *dev_priv = dev->dev_private;
143 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
144 } else
145 return 27;
146 }
147
148 static const intel_limit_t intel_limits_i8xx_dac = {
149 .dot = { .min = 25000, .max = 350000 },
150 .vco = { .min = 908000, .max = 1512000 },
151 .n = { .min = 2, .max = 16 },
152 .m = { .min = 96, .max = 140 },
153 .m1 = { .min = 18, .max = 26 },
154 .m2 = { .min = 6, .max = 16 },
155 .p = { .min = 4, .max = 128 },
156 .p1 = { .min = 2, .max = 33 },
157 .p2 = { .dot_limit = 165000,
158 .p2_slow = 4, .p2_fast = 2 },
159 };
160
161 static const intel_limit_t intel_limits_i8xx_dvo = {
162 .dot = { .min = 25000, .max = 350000 },
163 .vco = { .min = 908000, .max = 1512000 },
164 .n = { .min = 2, .max = 16 },
165 .m = { .min = 96, .max = 140 },
166 .m1 = { .min = 18, .max = 26 },
167 .m2 = { .min = 6, .max = 16 },
168 .p = { .min = 4, .max = 128 },
169 .p1 = { .min = 2, .max = 33 },
170 .p2 = { .dot_limit = 165000,
171 .p2_slow = 4, .p2_fast = 4 },
172 };
173
174 static const intel_limit_t intel_limits_i8xx_lvds = {
175 .dot = { .min = 25000, .max = 350000 },
176 .vco = { .min = 908000, .max = 1512000 },
177 .n = { .min = 2, .max = 16 },
178 .m = { .min = 96, .max = 140 },
179 .m1 = { .min = 18, .max = 26 },
180 .m2 = { .min = 6, .max = 16 },
181 .p = { .min = 4, .max = 128 },
182 .p1 = { .min = 1, .max = 6 },
183 .p2 = { .dot_limit = 165000,
184 .p2_slow = 14, .p2_fast = 7 },
185 };
186
187 static const intel_limit_t intel_limits_i9xx_sdvo = {
188 .dot = { .min = 20000, .max = 400000 },
189 .vco = { .min = 1400000, .max = 2800000 },
190 .n = { .min = 1, .max = 6 },
191 .m = { .min = 70, .max = 120 },
192 .m1 = { .min = 8, .max = 18 },
193 .m2 = { .min = 3, .max = 7 },
194 .p = { .min = 5, .max = 80 },
195 .p1 = { .min = 1, .max = 8 },
196 .p2 = { .dot_limit = 200000,
197 .p2_slow = 10, .p2_fast = 5 },
198 };
199
200 static const intel_limit_t intel_limits_i9xx_lvds = {
201 .dot = { .min = 20000, .max = 400000 },
202 .vco = { .min = 1400000, .max = 2800000 },
203 .n = { .min = 1, .max = 6 },
204 .m = { .min = 70, .max = 120 },
205 .m1 = { .min = 8, .max = 18 },
206 .m2 = { .min = 3, .max = 7 },
207 .p = { .min = 7, .max = 98 },
208 .p1 = { .min = 1, .max = 8 },
209 .p2 = { .dot_limit = 112000,
210 .p2_slow = 14, .p2_fast = 7 },
211 };
212
213
214 static const intel_limit_t intel_limits_g4x_sdvo = {
215 .dot = { .min = 25000, .max = 270000 },
216 .vco = { .min = 1750000, .max = 3500000},
217 .n = { .min = 1, .max = 4 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 10, .max = 30 },
222 .p1 = { .min = 1, .max = 3},
223 .p2 = { .dot_limit = 270000,
224 .p2_slow = 10,
225 .p2_fast = 10
226 },
227 };
228
229 static const intel_limit_t intel_limits_g4x_hdmi = {
230 .dot = { .min = 22000, .max = 400000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 4 },
233 .m = { .min = 104, .max = 138 },
234 .m1 = { .min = 16, .max = 23 },
235 .m2 = { .min = 5, .max = 11 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8},
238 .p2 = { .dot_limit = 165000,
239 .p2_slow = 10, .p2_fast = 5 },
240 };
241
242 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
243 .dot = { .min = 20000, .max = 115000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 14, .p2_fast = 14
253 },
254 };
255
256 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
257 .dot = { .min = 80000, .max = 224000 },
258 .vco = { .min = 1750000, .max = 3500000 },
259 .n = { .min = 1, .max = 3 },
260 .m = { .min = 104, .max = 138 },
261 .m1 = { .min = 17, .max = 23 },
262 .m2 = { .min = 5, .max = 11 },
263 .p = { .min = 14, .max = 42 },
264 .p1 = { .min = 2, .max = 6 },
265 .p2 = { .dot_limit = 0,
266 .p2_slow = 7, .p2_fast = 7
267 },
268 };
269
270 static const intel_limit_t intel_limits_pineview_sdvo = {
271 .dot = { .min = 20000, .max = 400000},
272 .vco = { .min = 1700000, .max = 3500000 },
273 /* Pineview's Ncounter is a ring counter */
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 /* Pineview only has one combined m divider, which we treat as m2. */
277 .m1 = { .min = 0, .max = 0 },
278 .m2 = { .min = 0, .max = 254 },
279 .p = { .min = 5, .max = 80 },
280 .p1 = { .min = 1, .max = 8 },
281 .p2 = { .dot_limit = 200000,
282 .p2_slow = 10, .p2_fast = 5 },
283 };
284
285 static const intel_limit_t intel_limits_pineview_lvds = {
286 .dot = { .min = 20000, .max = 400000 },
287 .vco = { .min = 1700000, .max = 3500000 },
288 .n = { .min = 3, .max = 6 },
289 .m = { .min = 2, .max = 256 },
290 .m1 = { .min = 0, .max = 0 },
291 .m2 = { .min = 0, .max = 254 },
292 .p = { .min = 7, .max = 112 },
293 .p1 = { .min = 1, .max = 8 },
294 .p2 = { .dot_limit = 112000,
295 .p2_slow = 14, .p2_fast = 14 },
296 };
297
298 /* Ironlake / Sandybridge
299 *
300 * We calculate clock using (register_value + 2) for N/M1/M2, so here
301 * the range value for them is (actual_value - 2).
302 */
303 static const intel_limit_t intel_limits_ironlake_dac = {
304 .dot = { .min = 25000, .max = 350000 },
305 .vco = { .min = 1760000, .max = 3510000 },
306 .n = { .min = 1, .max = 5 },
307 .m = { .min = 79, .max = 127 },
308 .m1 = { .min = 12, .max = 22 },
309 .m2 = { .min = 5, .max = 9 },
310 .p = { .min = 5, .max = 80 },
311 .p1 = { .min = 1, .max = 8 },
312 .p2 = { .dot_limit = 225000,
313 .p2_slow = 10, .p2_fast = 5 },
314 };
315
316 static const intel_limit_t intel_limits_ironlake_single_lvds = {
317 .dot = { .min = 25000, .max = 350000 },
318 .vco = { .min = 1760000, .max = 3510000 },
319 .n = { .min = 1, .max = 3 },
320 .m = { .min = 79, .max = 118 },
321 .m1 = { .min = 12, .max = 22 },
322 .m2 = { .min = 5, .max = 9 },
323 .p = { .min = 28, .max = 112 },
324 .p1 = { .min = 2, .max = 8 },
325 .p2 = { .dot_limit = 225000,
326 .p2_slow = 14, .p2_fast = 14 },
327 };
328
329 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
330 .dot = { .min = 25000, .max = 350000 },
331 .vco = { .min = 1760000, .max = 3510000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 79, .max = 127 },
334 .m1 = { .min = 12, .max = 22 },
335 .m2 = { .min = 5, .max = 9 },
336 .p = { .min = 14, .max = 56 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 225000,
339 .p2_slow = 7, .p2_fast = 7 },
340 };
341
342 /* LVDS 100mhz refclk limits. */
343 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
344 .dot = { .min = 25000, .max = 350000 },
345 .vco = { .min = 1760000, .max = 3510000 },
346 .n = { .min = 1, .max = 2 },
347 .m = { .min = 79, .max = 126 },
348 .m1 = { .min = 12, .max = 22 },
349 .m2 = { .min = 5, .max = 9 },
350 .p = { .min = 28, .max = 112 },
351 .p1 = { .min = 2, .max = 8 },
352 .p2 = { .dot_limit = 225000,
353 .p2_slow = 14, .p2_fast = 14 },
354 };
355
356 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
357 .dot = { .min = 25000, .max = 350000 },
358 .vco = { .min = 1760000, .max = 3510000 },
359 .n = { .min = 1, .max = 3 },
360 .m = { .min = 79, .max = 126 },
361 .m1 = { .min = 12, .max = 22 },
362 .m2 = { .min = 5, .max = 9 },
363 .p = { .min = 14, .max = 42 },
364 .p1 = { .min = 2, .max = 6 },
365 .p2 = { .dot_limit = 225000,
366 .p2_slow = 7, .p2_fast = 7 },
367 };
368
369 static const intel_limit_t intel_limits_vlv = {
370 /*
371 * These are the data rate limits (measured in fast clocks)
372 * since those are the strictest limits we have. The fast
373 * clock and actual rate limits are more relaxed, so checking
374 * them would make no difference.
375 */
376 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m1 = { .min = 2, .max = 3 },
380 .m2 = { .min = 11, .max = 156 },
381 .p1 = { .min = 2, .max = 3 },
382 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
383 };
384
385 static const intel_limit_t intel_limits_chv = {
386 /*
387 * These are the data rate limits (measured in fast clocks)
388 * since those are the strictest limits we have. The fast
389 * clock and actual rate limits are more relaxed, so checking
390 * them would make no difference.
391 */
392 .dot = { .min = 25000 * 5, .max = 540000 * 5},
393 .vco = { .min = 4860000, .max = 6700000 },
394 .n = { .min = 1, .max = 1 },
395 .m1 = { .min = 2, .max = 2 },
396 .m2 = { .min = 24 << 22, .max = 175 << 22 },
397 .p1 = { .min = 2, .max = 4 },
398 .p2 = { .p2_slow = 1, .p2_fast = 14 },
399 };
400
401 static void vlv_clock(int refclk, intel_clock_t *clock)
402 {
403 clock->m = clock->m1 * clock->m2;
404 clock->p = clock->p1 * clock->p2;
405 if (WARN_ON(clock->n == 0 || clock->p == 0))
406 return;
407 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
408 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
409 }
410
411 /**
412 * Returns whether any output on the specified pipe is of the specified type
413 */
414 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
415 {
416 struct drm_device *dev = crtc->dev;
417 struct intel_encoder *encoder;
418
419 for_each_encoder_on_crtc(dev, crtc, encoder)
420 if (encoder->type == type)
421 return true;
422
423 return false;
424 }
425
426 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
427 int refclk)
428 {
429 struct drm_device *dev = crtc->dev;
430 const intel_limit_t *limit;
431
432 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
433 if (intel_is_dual_link_lvds(dev)) {
434 if (refclk == 100000)
435 limit = &intel_limits_ironlake_dual_lvds_100m;
436 else
437 limit = &intel_limits_ironlake_dual_lvds;
438 } else {
439 if (refclk == 100000)
440 limit = &intel_limits_ironlake_single_lvds_100m;
441 else
442 limit = &intel_limits_ironlake_single_lvds;
443 }
444 } else
445 limit = &intel_limits_ironlake_dac;
446
447 return limit;
448 }
449
450 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
451 {
452 struct drm_device *dev = crtc->dev;
453 const intel_limit_t *limit;
454
455 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
456 if (intel_is_dual_link_lvds(dev))
457 limit = &intel_limits_g4x_dual_channel_lvds;
458 else
459 limit = &intel_limits_g4x_single_channel_lvds;
460 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
461 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
462 limit = &intel_limits_g4x_hdmi;
463 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
464 limit = &intel_limits_g4x_sdvo;
465 } else /* The option is for other outputs */
466 limit = &intel_limits_i9xx_sdvo;
467
468 return limit;
469 }
470
471 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
472 {
473 struct drm_device *dev = crtc->dev;
474 const intel_limit_t *limit;
475
476 if (HAS_PCH_SPLIT(dev))
477 limit = intel_ironlake_limit(crtc, refclk);
478 else if (IS_G4X(dev)) {
479 limit = intel_g4x_limit(crtc);
480 } else if (IS_PINEVIEW(dev)) {
481 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
482 limit = &intel_limits_pineview_lvds;
483 else
484 limit = &intel_limits_pineview_sdvo;
485 } else if (IS_CHERRYVIEW(dev)) {
486 limit = &intel_limits_chv;
487 } else if (IS_VALLEYVIEW(dev)) {
488 limit = &intel_limits_vlv;
489 } else if (!IS_GEN2(dev)) {
490 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
491 limit = &intel_limits_i9xx_lvds;
492 else
493 limit = &intel_limits_i9xx_sdvo;
494 } else {
495 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
496 limit = &intel_limits_i8xx_lvds;
497 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
498 limit = &intel_limits_i8xx_dvo;
499 else
500 limit = &intel_limits_i8xx_dac;
501 }
502 return limit;
503 }
504
505 /* m1 is reserved as 0 in Pineview, n is a ring counter */
506 static void pineview_clock(int refclk, intel_clock_t *clock)
507 {
508 clock->m = clock->m2 + 2;
509 clock->p = clock->p1 * clock->p2;
510 if (WARN_ON(clock->n == 0 || clock->p == 0))
511 return;
512 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
513 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
514 }
515
516 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
517 {
518 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
519 }
520
521 static void i9xx_clock(int refclk, intel_clock_t *clock)
522 {
523 clock->m = i9xx_dpll_compute_m(clock);
524 clock->p = clock->p1 * clock->p2;
525 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
526 return;
527 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
528 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
529 }
530
531 static void chv_clock(int refclk, intel_clock_t *clock)
532 {
533 clock->m = clock->m1 * clock->m2;
534 clock->p = clock->p1 * clock->p2;
535 if (WARN_ON(clock->n == 0 || clock->p == 0))
536 return;
537 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
538 clock->n << 22);
539 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
540 }
541
542 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
543 /**
544 * Returns whether the given set of divisors are valid for a given refclk with
545 * the given connectors.
546 */
547
548 static bool intel_PLL_is_valid(struct drm_device *dev,
549 const intel_limit_t *limit,
550 const intel_clock_t *clock)
551 {
552 if (clock->n < limit->n.min || limit->n.max < clock->n)
553 INTELPllInvalid("n out of range\n");
554 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
555 INTELPllInvalid("p1 out of range\n");
556 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
557 INTELPllInvalid("m2 out of range\n");
558 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
559 INTELPllInvalid("m1 out of range\n");
560
561 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
562 if (clock->m1 <= clock->m2)
563 INTELPllInvalid("m1 <= m2\n");
564
565 if (!IS_VALLEYVIEW(dev)) {
566 if (clock->p < limit->p.min || limit->p.max < clock->p)
567 INTELPllInvalid("p out of range\n");
568 if (clock->m < limit->m.min || limit->m.max < clock->m)
569 INTELPllInvalid("m out of range\n");
570 }
571
572 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
573 INTELPllInvalid("vco out of range\n");
574 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
575 * connector, etc., rather than just a single range.
576 */
577 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
578 INTELPllInvalid("dot out of range\n");
579
580 return true;
581 }
582
583 static bool
584 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
585 int target, int refclk, intel_clock_t *match_clock,
586 intel_clock_t *best_clock)
587 {
588 struct drm_device *dev = crtc->dev;
589 intel_clock_t clock;
590 int err = target;
591
592 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
593 /*
594 * For LVDS just rely on its current settings for dual-channel.
595 * We haven't figured out how to reliably set up different
596 * single/dual channel state, if we even can.
597 */
598 if (intel_is_dual_link_lvds(dev))
599 clock.p2 = limit->p2.p2_fast;
600 else
601 clock.p2 = limit->p2.p2_slow;
602 } else {
603 if (target < limit->p2.dot_limit)
604 clock.p2 = limit->p2.p2_slow;
605 else
606 clock.p2 = limit->p2.p2_fast;
607 }
608
609 memset(best_clock, 0, sizeof(*best_clock));
610
611 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
612 clock.m1++) {
613 for (clock.m2 = limit->m2.min;
614 clock.m2 <= limit->m2.max; clock.m2++) {
615 if (clock.m2 >= clock.m1)
616 break;
617 for (clock.n = limit->n.min;
618 clock.n <= limit->n.max; clock.n++) {
619 for (clock.p1 = limit->p1.min;
620 clock.p1 <= limit->p1.max; clock.p1++) {
621 int this_err;
622
623 i9xx_clock(refclk, &clock);
624 if (!intel_PLL_is_valid(dev, limit,
625 &clock))
626 continue;
627 if (match_clock &&
628 clock.p != match_clock->p)
629 continue;
630
631 this_err = abs(clock.dot - target);
632 if (this_err < err) {
633 *best_clock = clock;
634 err = this_err;
635 }
636 }
637 }
638 }
639 }
640
641 return (err != target);
642 }
643
644 static bool
645 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
646 int target, int refclk, intel_clock_t *match_clock,
647 intel_clock_t *best_clock)
648 {
649 struct drm_device *dev = crtc->dev;
650 intel_clock_t clock;
651 int err = target;
652
653 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
654 /*
655 * For LVDS just rely on its current settings for dual-channel.
656 * We haven't figured out how to reliably set up different
657 * single/dual channel state, if we even can.
658 */
659 if (intel_is_dual_link_lvds(dev))
660 clock.p2 = limit->p2.p2_fast;
661 else
662 clock.p2 = limit->p2.p2_slow;
663 } else {
664 if (target < limit->p2.dot_limit)
665 clock.p2 = limit->p2.p2_slow;
666 else
667 clock.p2 = limit->p2.p2_fast;
668 }
669
670 memset(best_clock, 0, sizeof(*best_clock));
671
672 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
673 clock.m1++) {
674 for (clock.m2 = limit->m2.min;
675 clock.m2 <= limit->m2.max; clock.m2++) {
676 for (clock.n = limit->n.min;
677 clock.n <= limit->n.max; clock.n++) {
678 for (clock.p1 = limit->p1.min;
679 clock.p1 <= limit->p1.max; clock.p1++) {
680 int this_err;
681
682 pineview_clock(refclk, &clock);
683 if (!intel_PLL_is_valid(dev, limit,
684 &clock))
685 continue;
686 if (match_clock &&
687 clock.p != match_clock->p)
688 continue;
689
690 this_err = abs(clock.dot - target);
691 if (this_err < err) {
692 *best_clock = clock;
693 err = this_err;
694 }
695 }
696 }
697 }
698 }
699
700 return (err != target);
701 }
702
703 static bool
704 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
705 int target, int refclk, intel_clock_t *match_clock,
706 intel_clock_t *best_clock)
707 {
708 struct drm_device *dev = crtc->dev;
709 intel_clock_t clock;
710 int max_n;
711 bool found;
712 /* approximately equals target * 0.00585 */
713 int err_most = (target >> 8) + (target >> 9);
714 found = false;
715
716 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
717 if (intel_is_dual_link_lvds(dev))
718 clock.p2 = limit->p2.p2_fast;
719 else
720 clock.p2 = limit->p2.p2_slow;
721 } else {
722 if (target < limit->p2.dot_limit)
723 clock.p2 = limit->p2.p2_slow;
724 else
725 clock.p2 = limit->p2.p2_fast;
726 }
727
728 memset(best_clock, 0, sizeof(*best_clock));
729 max_n = limit->n.max;
730 /* based on hardware requirement, prefer smaller n to precision */
731 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
732 /* based on hardware requirement, prefere larger m1,m2 */
733 for (clock.m1 = limit->m1.max;
734 clock.m1 >= limit->m1.min; clock.m1--) {
735 for (clock.m2 = limit->m2.max;
736 clock.m2 >= limit->m2.min; clock.m2--) {
737 for (clock.p1 = limit->p1.max;
738 clock.p1 >= limit->p1.min; clock.p1--) {
739 int this_err;
740
741 i9xx_clock(refclk, &clock);
742 if (!intel_PLL_is_valid(dev, limit,
743 &clock))
744 continue;
745
746 this_err = abs(clock.dot - target);
747 if (this_err < err_most) {
748 *best_clock = clock;
749 err_most = this_err;
750 max_n = clock.n;
751 found = true;
752 }
753 }
754 }
755 }
756 }
757 return found;
758 }
759
760 static bool
761 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
762 int target, int refclk, intel_clock_t *match_clock,
763 intel_clock_t *best_clock)
764 {
765 struct drm_device *dev = crtc->dev;
766 intel_clock_t clock;
767 unsigned int bestppm = 1000000;
768 /* min update 19.2 MHz */
769 int max_n = min(limit->n.max, refclk / 19200);
770 bool found = false;
771
772 target *= 5; /* fast clock */
773
774 memset(best_clock, 0, sizeof(*best_clock));
775
776 /* based on hardware requirement, prefer smaller n to precision */
777 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
778 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
779 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
780 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
781 clock.p = clock.p1 * clock.p2;
782 /* based on hardware requirement, prefer bigger m1,m2 values */
783 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
784 unsigned int ppm, diff;
785
786 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
787 refclk * clock.m1);
788
789 vlv_clock(refclk, &clock);
790
791 if (!intel_PLL_is_valid(dev, limit,
792 &clock))
793 continue;
794
795 diff = abs(clock.dot - target);
796 ppm = div_u64(1000000ULL * diff, target);
797
798 if (ppm < 100 && clock.p > best_clock->p) {
799 bestppm = 0;
800 *best_clock = clock;
801 found = true;
802 }
803
804 if (bestppm >= 10 && ppm < bestppm - 10) {
805 bestppm = ppm;
806 *best_clock = clock;
807 found = true;
808 }
809 }
810 }
811 }
812 }
813
814 return found;
815 }
816
817 static bool
818 chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
819 int target, int refclk, intel_clock_t *match_clock,
820 intel_clock_t *best_clock)
821 {
822 struct drm_device *dev = crtc->dev;
823 intel_clock_t clock;
824 uint64_t m2;
825 int found = false;
826
827 memset(best_clock, 0, sizeof(*best_clock));
828
829 /*
830 * Based on hardware doc, the n always set to 1, and m1 always
831 * set to 2. If requires to support 200Mhz refclk, we need to
832 * revisit this because n may not 1 anymore.
833 */
834 clock.n = 1, clock.m1 = 2;
835 target *= 5; /* fast clock */
836
837 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
838 for (clock.p2 = limit->p2.p2_fast;
839 clock.p2 >= limit->p2.p2_slow;
840 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
841
842 clock.p = clock.p1 * clock.p2;
843
844 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
845 clock.n) << 22, refclk * clock.m1);
846
847 if (m2 > INT_MAX/clock.m1)
848 continue;
849
850 clock.m2 = m2;
851
852 chv_clock(refclk, &clock);
853
854 if (!intel_PLL_is_valid(dev, limit, &clock))
855 continue;
856
857 /* based on hardware requirement, prefer bigger p
858 */
859 if (clock.p > best_clock->p) {
860 *best_clock = clock;
861 found = true;
862 }
863 }
864 }
865
866 return found;
867 }
868
869 bool intel_crtc_active(struct drm_crtc *crtc)
870 {
871 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
872
873 /* Be paranoid as we can arrive here with only partial
874 * state retrieved from the hardware during setup.
875 *
876 * We can ditch the adjusted_mode.crtc_clock check as soon
877 * as Haswell has gained clock readout/fastboot support.
878 *
879 * We can ditch the crtc->primary->fb check as soon as we can
880 * properly reconstruct framebuffers.
881 */
882 return intel_crtc->active && crtc->primary->fb &&
883 intel_crtc->config.adjusted_mode.crtc_clock;
884 }
885
886 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
887 enum pipe pipe)
888 {
889 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
890 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
891
892 return intel_crtc->config.cpu_transcoder;
893 }
894
895 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
896 {
897 struct drm_i915_private *dev_priv = dev->dev_private;
898 u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
899
900 frame = I915_READ(frame_reg);
901
902 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
903 WARN(1, "vblank wait on pipe %c timed out\n",
904 pipe_name(pipe));
905 }
906
907 /**
908 * intel_wait_for_vblank - wait for vblank on a given pipe
909 * @dev: drm device
910 * @pipe: pipe to wait for
911 *
912 * Wait for vblank to occur on a given pipe. Needed for various bits of
913 * mode setting code.
914 */
915 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
916 {
917 struct drm_i915_private *dev_priv = dev->dev_private;
918 int pipestat_reg = PIPESTAT(pipe);
919
920 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
921 g4x_wait_for_vblank(dev, pipe);
922 return;
923 }
924
925 /* Clear existing vblank status. Note this will clear any other
926 * sticky status fields as well.
927 *
928 * This races with i915_driver_irq_handler() with the result
929 * that either function could miss a vblank event. Here it is not
930 * fatal, as we will either wait upon the next vblank interrupt or
931 * timeout. Generally speaking intel_wait_for_vblank() is only
932 * called during modeset at which time the GPU should be idle and
933 * should *not* be performing page flips and thus not waiting on
934 * vblanks...
935 * Currently, the result of us stealing a vblank from the irq
936 * handler is that a single frame will be skipped during swapbuffers.
937 */
938 I915_WRITE(pipestat_reg,
939 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
940
941 /* Wait for vblank interrupt bit to set */
942 if (wait_for(I915_READ(pipestat_reg) &
943 PIPE_VBLANK_INTERRUPT_STATUS,
944 50))
945 DRM_DEBUG_KMS("vblank wait on pipe %c timed out\n",
946 pipe_name(pipe));
947 }
948
949 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
950 {
951 struct drm_i915_private *dev_priv = dev->dev_private;
952 u32 reg = PIPEDSL(pipe);
953 u32 line1, line2;
954 u32 line_mask;
955
956 if (IS_GEN2(dev))
957 line_mask = DSL_LINEMASK_GEN2;
958 else
959 line_mask = DSL_LINEMASK_GEN3;
960
961 line1 = I915_READ(reg) & line_mask;
962 mdelay(5);
963 line2 = I915_READ(reg) & line_mask;
964
965 return line1 == line2;
966 }
967
968 /*
969 * intel_wait_for_pipe_off - wait for pipe to turn off
970 * @dev: drm device
971 * @pipe: pipe to wait for
972 *
973 * After disabling a pipe, we can't wait for vblank in the usual way,
974 * spinning on the vblank interrupt status bit, since we won't actually
975 * see an interrupt when the pipe is disabled.
976 *
977 * On Gen4 and above:
978 * wait for the pipe register state bit to turn off
979 *
980 * Otherwise:
981 * wait for the display line value to settle (it usually
982 * ends up stopping at the start of the next frame).
983 *
984 */
985 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
986 {
987 struct drm_i915_private *dev_priv = dev->dev_private;
988 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
989 pipe);
990
991 if (INTEL_INFO(dev)->gen >= 4) {
992 int reg = PIPECONF(cpu_transcoder);
993
994 /* Wait for the Pipe State to go off */
995 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
996 100))
997 WARN(1, "pipe_off wait timed out\n");
998 } else {
999 /* Wait for the display line to settle */
1000 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1001 WARN(1, "pipe_off wait timed out\n");
1002 }
1003 }
1004
1005 /*
1006 * ibx_digital_port_connected - is the specified port connected?
1007 * @dev_priv: i915 private structure
1008 * @port: the port to test
1009 *
1010 * Returns true if @port is connected, false otherwise.
1011 */
1012 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1013 struct intel_digital_port *port)
1014 {
1015 u32 bit;
1016
1017 if (HAS_PCH_IBX(dev_priv->dev)) {
1018 switch (port->port) {
1019 case PORT_B:
1020 bit = SDE_PORTB_HOTPLUG;
1021 break;
1022 case PORT_C:
1023 bit = SDE_PORTC_HOTPLUG;
1024 break;
1025 case PORT_D:
1026 bit = SDE_PORTD_HOTPLUG;
1027 break;
1028 default:
1029 return true;
1030 }
1031 } else {
1032 switch (port->port) {
1033 case PORT_B:
1034 bit = SDE_PORTB_HOTPLUG_CPT;
1035 break;
1036 case PORT_C:
1037 bit = SDE_PORTC_HOTPLUG_CPT;
1038 break;
1039 case PORT_D:
1040 bit = SDE_PORTD_HOTPLUG_CPT;
1041 break;
1042 default:
1043 return true;
1044 }
1045 }
1046
1047 return I915_READ(SDEISR) & bit;
1048 }
1049
1050 static const char *state_string(bool enabled)
1051 {
1052 return enabled ? "on" : "off";
1053 }
1054
1055 /* Only for pre-ILK configs */
1056 void assert_pll(struct drm_i915_private *dev_priv,
1057 enum pipe pipe, bool state)
1058 {
1059 int reg;
1060 u32 val;
1061 bool cur_state;
1062
1063 reg = DPLL(pipe);
1064 val = I915_READ(reg);
1065 cur_state = !!(val & DPLL_VCO_ENABLE);
1066 WARN(cur_state != state,
1067 "PLL state assertion failure (expected %s, current %s)\n",
1068 state_string(state), state_string(cur_state));
1069 }
1070
1071 /* XXX: the dsi pll is shared between MIPI DSI ports */
1072 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1073 {
1074 u32 val;
1075 bool cur_state;
1076
1077 mutex_lock(&dev_priv->dpio_lock);
1078 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1079 mutex_unlock(&dev_priv->dpio_lock);
1080
1081 cur_state = val & DSI_PLL_VCO_EN;
1082 WARN(cur_state != state,
1083 "DSI PLL state assertion failure (expected %s, current %s)\n",
1084 state_string(state), state_string(cur_state));
1085 }
1086 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1087 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1088
1089 struct intel_shared_dpll *
1090 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1091 {
1092 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1093
1094 if (crtc->config.shared_dpll < 0)
1095 return NULL;
1096
1097 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1098 }
1099
1100 /* For ILK+ */
1101 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1102 struct intel_shared_dpll *pll,
1103 bool state)
1104 {
1105 bool cur_state;
1106 struct intel_dpll_hw_state hw_state;
1107
1108 if (WARN (!pll,
1109 "asserting DPLL %s with no DPLL\n", state_string(state)))
1110 return;
1111
1112 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1113 WARN(cur_state != state,
1114 "%s assertion failure (expected %s, current %s)\n",
1115 pll->name, state_string(state), state_string(cur_state));
1116 }
1117
1118 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1119 enum pipe pipe, bool state)
1120 {
1121 int reg;
1122 u32 val;
1123 bool cur_state;
1124 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1125 pipe);
1126
1127 if (HAS_DDI(dev_priv->dev)) {
1128 /* DDI does not have a specific FDI_TX register */
1129 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1130 val = I915_READ(reg);
1131 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1132 } else {
1133 reg = FDI_TX_CTL(pipe);
1134 val = I915_READ(reg);
1135 cur_state = !!(val & FDI_TX_ENABLE);
1136 }
1137 WARN(cur_state != state,
1138 "FDI TX state assertion failure (expected %s, current %s)\n",
1139 state_string(state), state_string(cur_state));
1140 }
1141 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1142 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1143
1144 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1145 enum pipe pipe, bool state)
1146 {
1147 int reg;
1148 u32 val;
1149 bool cur_state;
1150
1151 reg = FDI_RX_CTL(pipe);
1152 val = I915_READ(reg);
1153 cur_state = !!(val & FDI_RX_ENABLE);
1154 WARN(cur_state != state,
1155 "FDI RX state assertion failure (expected %s, current %s)\n",
1156 state_string(state), state_string(cur_state));
1157 }
1158 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1159 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1160
1161 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1162 enum pipe pipe)
1163 {
1164 int reg;
1165 u32 val;
1166
1167 /* ILK FDI PLL is always enabled */
1168 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1169 return;
1170
1171 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1172 if (HAS_DDI(dev_priv->dev))
1173 return;
1174
1175 reg = FDI_TX_CTL(pipe);
1176 val = I915_READ(reg);
1177 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1178 }
1179
1180 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1181 enum pipe pipe, bool state)
1182 {
1183 int reg;
1184 u32 val;
1185 bool cur_state;
1186
1187 reg = FDI_RX_CTL(pipe);
1188 val = I915_READ(reg);
1189 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1190 WARN(cur_state != state,
1191 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1192 state_string(state), state_string(cur_state));
1193 }
1194
1195 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1196 enum pipe pipe)
1197 {
1198 int pp_reg, lvds_reg;
1199 u32 val;
1200 enum pipe panel_pipe = PIPE_A;
1201 bool locked = true;
1202
1203 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1204 pp_reg = PCH_PP_CONTROL;
1205 lvds_reg = PCH_LVDS;
1206 } else {
1207 pp_reg = PP_CONTROL;
1208 lvds_reg = LVDS;
1209 }
1210
1211 val = I915_READ(pp_reg);
1212 if (!(val & PANEL_POWER_ON) ||
1213 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1214 locked = false;
1215
1216 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1217 panel_pipe = PIPE_B;
1218
1219 WARN(panel_pipe == pipe && locked,
1220 "panel assertion failure, pipe %c regs locked\n",
1221 pipe_name(pipe));
1222 }
1223
1224 static void assert_cursor(struct drm_i915_private *dev_priv,
1225 enum pipe pipe, bool state)
1226 {
1227 struct drm_device *dev = dev_priv->dev;
1228 bool cur_state;
1229
1230 if (IS_845G(dev) || IS_I865G(dev))
1231 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1232 else
1233 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1234
1235 WARN(cur_state != state,
1236 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1237 pipe_name(pipe), state_string(state), state_string(cur_state));
1238 }
1239 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1240 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1241
1242 void assert_pipe(struct drm_i915_private *dev_priv,
1243 enum pipe pipe, bool state)
1244 {
1245 int reg;
1246 u32 val;
1247 bool cur_state;
1248 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1249 pipe);
1250
1251 /* if we need the pipe A quirk it must be always on */
1252 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1253 state = true;
1254
1255 if (!intel_display_power_enabled(dev_priv,
1256 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1257 cur_state = false;
1258 } else {
1259 reg = PIPECONF(cpu_transcoder);
1260 val = I915_READ(reg);
1261 cur_state = !!(val & PIPECONF_ENABLE);
1262 }
1263
1264 WARN(cur_state != state,
1265 "pipe %c assertion failure (expected %s, current %s)\n",
1266 pipe_name(pipe), state_string(state), state_string(cur_state));
1267 }
1268
1269 static void assert_plane(struct drm_i915_private *dev_priv,
1270 enum plane plane, bool state)
1271 {
1272 int reg;
1273 u32 val;
1274 bool cur_state;
1275
1276 reg = DSPCNTR(plane);
1277 val = I915_READ(reg);
1278 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1279 WARN(cur_state != state,
1280 "plane %c assertion failure (expected %s, current %s)\n",
1281 plane_name(plane), state_string(state), state_string(cur_state));
1282 }
1283
1284 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1285 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1286
1287 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1288 enum pipe pipe)
1289 {
1290 struct drm_device *dev = dev_priv->dev;
1291 int reg, i;
1292 u32 val;
1293 int cur_pipe;
1294
1295 /* Primary planes are fixed to pipes on gen4+ */
1296 if (INTEL_INFO(dev)->gen >= 4) {
1297 reg = DSPCNTR(pipe);
1298 val = I915_READ(reg);
1299 WARN(val & DISPLAY_PLANE_ENABLE,
1300 "plane %c assertion failure, should be disabled but not\n",
1301 plane_name(pipe));
1302 return;
1303 }
1304
1305 /* Need to check both planes against the pipe */
1306 for_each_pipe(dev_priv, i) {
1307 reg = DSPCNTR(i);
1308 val = I915_READ(reg);
1309 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1310 DISPPLANE_SEL_PIPE_SHIFT;
1311 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1312 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1313 plane_name(i), pipe_name(pipe));
1314 }
1315 }
1316
1317 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1318 enum pipe pipe)
1319 {
1320 struct drm_device *dev = dev_priv->dev;
1321 int reg, sprite;
1322 u32 val;
1323
1324 if (IS_VALLEYVIEW(dev)) {
1325 for_each_sprite(pipe, sprite) {
1326 reg = SPCNTR(pipe, sprite);
1327 val = I915_READ(reg);
1328 WARN(val & SP_ENABLE,
1329 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1330 sprite_name(pipe, sprite), pipe_name(pipe));
1331 }
1332 } else if (INTEL_INFO(dev)->gen >= 7) {
1333 reg = SPRCTL(pipe);
1334 val = I915_READ(reg);
1335 WARN(val & SPRITE_ENABLE,
1336 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1337 plane_name(pipe), pipe_name(pipe));
1338 } else if (INTEL_INFO(dev)->gen >= 5) {
1339 reg = DVSCNTR(pipe);
1340 val = I915_READ(reg);
1341 WARN(val & DVS_ENABLE,
1342 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1343 plane_name(pipe), pipe_name(pipe));
1344 }
1345 }
1346
1347 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1348 {
1349 u32 val;
1350 bool enabled;
1351
1352 WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1353
1354 val = I915_READ(PCH_DREF_CONTROL);
1355 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1356 DREF_SUPERSPREAD_SOURCE_MASK));
1357 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1358 }
1359
1360 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1361 enum pipe pipe)
1362 {
1363 int reg;
1364 u32 val;
1365 bool enabled;
1366
1367 reg = PCH_TRANSCONF(pipe);
1368 val = I915_READ(reg);
1369 enabled = !!(val & TRANS_ENABLE);
1370 WARN(enabled,
1371 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1372 pipe_name(pipe));
1373 }
1374
1375 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1376 enum pipe pipe, u32 port_sel, u32 val)
1377 {
1378 if ((val & DP_PORT_EN) == 0)
1379 return false;
1380
1381 if (HAS_PCH_CPT(dev_priv->dev)) {
1382 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1383 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1384 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1385 return false;
1386 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1387 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1388 return false;
1389 } else {
1390 if ((val & DP_PIPE_MASK) != (pipe << 30))
1391 return false;
1392 }
1393 return true;
1394 }
1395
1396 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1397 enum pipe pipe, u32 val)
1398 {
1399 if ((val & SDVO_ENABLE) == 0)
1400 return false;
1401
1402 if (HAS_PCH_CPT(dev_priv->dev)) {
1403 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1404 return false;
1405 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1406 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1407 return false;
1408 } else {
1409 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1410 return false;
1411 }
1412 return true;
1413 }
1414
1415 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1416 enum pipe pipe, u32 val)
1417 {
1418 if ((val & LVDS_PORT_EN) == 0)
1419 return false;
1420
1421 if (HAS_PCH_CPT(dev_priv->dev)) {
1422 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1423 return false;
1424 } else {
1425 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1426 return false;
1427 }
1428 return true;
1429 }
1430
1431 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1432 enum pipe pipe, u32 val)
1433 {
1434 if ((val & ADPA_DAC_ENABLE) == 0)
1435 return false;
1436 if (HAS_PCH_CPT(dev_priv->dev)) {
1437 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1438 return false;
1439 } else {
1440 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1441 return false;
1442 }
1443 return true;
1444 }
1445
1446 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1447 enum pipe pipe, int reg, u32 port_sel)
1448 {
1449 u32 val = I915_READ(reg);
1450 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1451 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1452 reg, pipe_name(pipe));
1453
1454 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1455 && (val & DP_PIPEB_SELECT),
1456 "IBX PCH dp port still using transcoder B\n");
1457 }
1458
1459 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1460 enum pipe pipe, int reg)
1461 {
1462 u32 val = I915_READ(reg);
1463 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1464 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1465 reg, pipe_name(pipe));
1466
1467 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1468 && (val & SDVO_PIPE_B_SELECT),
1469 "IBX PCH hdmi port still using transcoder B\n");
1470 }
1471
1472 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1473 enum pipe pipe)
1474 {
1475 int reg;
1476 u32 val;
1477
1478 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1479 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1480 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1481
1482 reg = PCH_ADPA;
1483 val = I915_READ(reg);
1484 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1485 "PCH VGA enabled on transcoder %c, should be disabled\n",
1486 pipe_name(pipe));
1487
1488 reg = PCH_LVDS;
1489 val = I915_READ(reg);
1490 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1491 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1492 pipe_name(pipe));
1493
1494 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1495 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1496 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1497 }
1498
1499 static void intel_init_dpio(struct drm_device *dev)
1500 {
1501 struct drm_i915_private *dev_priv = dev->dev_private;
1502
1503 if (!IS_VALLEYVIEW(dev))
1504 return;
1505
1506 /*
1507 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1508 * CHV x1 PHY (DP/HDMI D)
1509 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1510 */
1511 if (IS_CHERRYVIEW(dev)) {
1512 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1513 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1514 } else {
1515 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1516 }
1517 }
1518
1519 static void vlv_enable_pll(struct intel_crtc *crtc)
1520 {
1521 struct drm_device *dev = crtc->base.dev;
1522 struct drm_i915_private *dev_priv = dev->dev_private;
1523 int reg = DPLL(crtc->pipe);
1524 u32 dpll = crtc->config.dpll_hw_state.dpll;
1525
1526 assert_pipe_disabled(dev_priv, crtc->pipe);
1527
1528 /* No really, not for ILK+ */
1529 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1530
1531 /* PLL is protected by panel, make sure we can write it */
1532 if (IS_MOBILE(dev_priv->dev))
1533 assert_panel_unlocked(dev_priv, crtc->pipe);
1534
1535 I915_WRITE(reg, dpll);
1536 POSTING_READ(reg);
1537 udelay(150);
1538
1539 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1540 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1541
1542 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1543 POSTING_READ(DPLL_MD(crtc->pipe));
1544
1545 /* We do this three times for luck */
1546 I915_WRITE(reg, dpll);
1547 POSTING_READ(reg);
1548 udelay(150); /* wait for warmup */
1549 I915_WRITE(reg, dpll);
1550 POSTING_READ(reg);
1551 udelay(150); /* wait for warmup */
1552 I915_WRITE(reg, dpll);
1553 POSTING_READ(reg);
1554 udelay(150); /* wait for warmup */
1555 }
1556
1557 static void chv_enable_pll(struct intel_crtc *crtc)
1558 {
1559 struct drm_device *dev = crtc->base.dev;
1560 struct drm_i915_private *dev_priv = dev->dev_private;
1561 int pipe = crtc->pipe;
1562 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1563 u32 tmp;
1564
1565 assert_pipe_disabled(dev_priv, crtc->pipe);
1566
1567 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1568
1569 mutex_lock(&dev_priv->dpio_lock);
1570
1571 /* Enable back the 10bit clock to display controller */
1572 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1573 tmp |= DPIO_DCLKP_EN;
1574 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1575
1576 /*
1577 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1578 */
1579 udelay(1);
1580
1581 /* Enable PLL */
1582 I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll);
1583
1584 /* Check PLL is locked */
1585 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1586 DRM_ERROR("PLL %d failed to lock\n", pipe);
1587
1588 /* not sure when this should be written */
1589 I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
1590 POSTING_READ(DPLL_MD(pipe));
1591
1592 mutex_unlock(&dev_priv->dpio_lock);
1593 }
1594
1595 static void i9xx_enable_pll(struct intel_crtc *crtc)
1596 {
1597 struct drm_device *dev = crtc->base.dev;
1598 struct drm_i915_private *dev_priv = dev->dev_private;
1599 int reg = DPLL(crtc->pipe);
1600 u32 dpll = crtc->config.dpll_hw_state.dpll;
1601
1602 assert_pipe_disabled(dev_priv, crtc->pipe);
1603
1604 /* No really, not for ILK+ */
1605 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1606
1607 /* PLL is protected by panel, make sure we can write it */
1608 if (IS_MOBILE(dev) && !IS_I830(dev))
1609 assert_panel_unlocked(dev_priv, crtc->pipe);
1610
1611 I915_WRITE(reg, dpll);
1612
1613 /* Wait for the clocks to stabilize. */
1614 POSTING_READ(reg);
1615 udelay(150);
1616
1617 if (INTEL_INFO(dev)->gen >= 4) {
1618 I915_WRITE(DPLL_MD(crtc->pipe),
1619 crtc->config.dpll_hw_state.dpll_md);
1620 } else {
1621 /* The pixel multiplier can only be updated once the
1622 * DPLL is enabled and the clocks are stable.
1623 *
1624 * So write it again.
1625 */
1626 I915_WRITE(reg, dpll);
1627 }
1628
1629 /* We do this three times for luck */
1630 I915_WRITE(reg, dpll);
1631 POSTING_READ(reg);
1632 udelay(150); /* wait for warmup */
1633 I915_WRITE(reg, dpll);
1634 POSTING_READ(reg);
1635 udelay(150); /* wait for warmup */
1636 I915_WRITE(reg, dpll);
1637 POSTING_READ(reg);
1638 udelay(150); /* wait for warmup */
1639 }
1640
1641 /**
1642 * i9xx_disable_pll - disable a PLL
1643 * @dev_priv: i915 private structure
1644 * @pipe: pipe PLL to disable
1645 *
1646 * Disable the PLL for @pipe, making sure the pipe is off first.
1647 *
1648 * Note! This is for pre-ILK only.
1649 */
1650 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1651 {
1652 /* Don't disable pipe A or pipe A PLLs if needed */
1653 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1654 return;
1655
1656 /* Make sure the pipe isn't still relying on us */
1657 assert_pipe_disabled(dev_priv, pipe);
1658
1659 I915_WRITE(DPLL(pipe), 0);
1660 POSTING_READ(DPLL(pipe));
1661 }
1662
1663 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1664 {
1665 u32 val = 0;
1666
1667 /* Make sure the pipe isn't still relying on us */
1668 assert_pipe_disabled(dev_priv, pipe);
1669
1670 /*
1671 * Leave integrated clock source and reference clock enabled for pipe B.
1672 * The latter is needed for VGA hotplug / manual detection.
1673 */
1674 if (pipe == PIPE_B)
1675 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1676 I915_WRITE(DPLL(pipe), val);
1677 POSTING_READ(DPLL(pipe));
1678
1679 }
1680
1681 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1682 {
1683 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1684 u32 val;
1685
1686 /* Make sure the pipe isn't still relying on us */
1687 assert_pipe_disabled(dev_priv, pipe);
1688
1689 /* Set PLL en = 0 */
1690 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1691 if (pipe != PIPE_A)
1692 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1693 I915_WRITE(DPLL(pipe), val);
1694 POSTING_READ(DPLL(pipe));
1695
1696 mutex_lock(&dev_priv->dpio_lock);
1697
1698 /* Disable 10bit clock to display controller */
1699 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1700 val &= ~DPIO_DCLKP_EN;
1701 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1702
1703 /* disable left/right clock distribution */
1704 if (pipe != PIPE_B) {
1705 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1706 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1707 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1708 } else {
1709 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1710 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1711 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1712 }
1713
1714 mutex_unlock(&dev_priv->dpio_lock);
1715 }
1716
1717 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1718 struct intel_digital_port *dport)
1719 {
1720 u32 port_mask;
1721 int dpll_reg;
1722
1723 switch (dport->port) {
1724 case PORT_B:
1725 port_mask = DPLL_PORTB_READY_MASK;
1726 dpll_reg = DPLL(0);
1727 break;
1728 case PORT_C:
1729 port_mask = DPLL_PORTC_READY_MASK;
1730 dpll_reg = DPLL(0);
1731 break;
1732 case PORT_D:
1733 port_mask = DPLL_PORTD_READY_MASK;
1734 dpll_reg = DPIO_PHY_STATUS;
1735 break;
1736 default:
1737 BUG();
1738 }
1739
1740 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1741 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1742 port_name(dport->port), I915_READ(dpll_reg));
1743 }
1744
1745 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1746 {
1747 struct drm_device *dev = crtc->base.dev;
1748 struct drm_i915_private *dev_priv = dev->dev_private;
1749 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1750
1751 if (WARN_ON(pll == NULL))
1752 return;
1753
1754 WARN_ON(!pll->refcount);
1755 if (pll->active == 0) {
1756 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1757 WARN_ON(pll->on);
1758 assert_shared_dpll_disabled(dev_priv, pll);
1759
1760 pll->mode_set(dev_priv, pll);
1761 }
1762 }
1763
1764 /**
1765 * intel_enable_shared_dpll - enable PCH PLL
1766 * @dev_priv: i915 private structure
1767 * @pipe: pipe PLL to enable
1768 *
1769 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1770 * drives the transcoder clock.
1771 */
1772 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1773 {
1774 struct drm_device *dev = crtc->base.dev;
1775 struct drm_i915_private *dev_priv = dev->dev_private;
1776 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1777
1778 if (WARN_ON(pll == NULL))
1779 return;
1780
1781 if (WARN_ON(pll->refcount == 0))
1782 return;
1783
1784 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1785 pll->name, pll->active, pll->on,
1786 crtc->base.base.id);
1787
1788 if (pll->active++) {
1789 WARN_ON(!pll->on);
1790 assert_shared_dpll_enabled(dev_priv, pll);
1791 return;
1792 }
1793 WARN_ON(pll->on);
1794
1795 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1796
1797 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1798 pll->enable(dev_priv, pll);
1799 pll->on = true;
1800 }
1801
1802 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1803 {
1804 struct drm_device *dev = crtc->base.dev;
1805 struct drm_i915_private *dev_priv = dev->dev_private;
1806 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1807
1808 /* PCH only available on ILK+ */
1809 BUG_ON(INTEL_INFO(dev)->gen < 5);
1810 if (WARN_ON(pll == NULL))
1811 return;
1812
1813 if (WARN_ON(pll->refcount == 0))
1814 return;
1815
1816 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1817 pll->name, pll->active, pll->on,
1818 crtc->base.base.id);
1819
1820 if (WARN_ON(pll->active == 0)) {
1821 assert_shared_dpll_disabled(dev_priv, pll);
1822 return;
1823 }
1824
1825 assert_shared_dpll_enabled(dev_priv, pll);
1826 WARN_ON(!pll->on);
1827 if (--pll->active)
1828 return;
1829
1830 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1831 pll->disable(dev_priv, pll);
1832 pll->on = false;
1833
1834 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1835 }
1836
1837 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1838 enum pipe pipe)
1839 {
1840 struct drm_device *dev = dev_priv->dev;
1841 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1842 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1843 uint32_t reg, val, pipeconf_val;
1844
1845 /* PCH only available on ILK+ */
1846 BUG_ON(INTEL_INFO(dev)->gen < 5);
1847
1848 /* Make sure PCH DPLL is enabled */
1849 assert_shared_dpll_enabled(dev_priv,
1850 intel_crtc_to_shared_dpll(intel_crtc));
1851
1852 /* FDI must be feeding us bits for PCH ports */
1853 assert_fdi_tx_enabled(dev_priv, pipe);
1854 assert_fdi_rx_enabled(dev_priv, pipe);
1855
1856 if (HAS_PCH_CPT(dev)) {
1857 /* Workaround: Set the timing override bit before enabling the
1858 * pch transcoder. */
1859 reg = TRANS_CHICKEN2(pipe);
1860 val = I915_READ(reg);
1861 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1862 I915_WRITE(reg, val);
1863 }
1864
1865 reg = PCH_TRANSCONF(pipe);
1866 val = I915_READ(reg);
1867 pipeconf_val = I915_READ(PIPECONF(pipe));
1868
1869 if (HAS_PCH_IBX(dev_priv->dev)) {
1870 /*
1871 * make the BPC in transcoder be consistent with
1872 * that in pipeconf reg.
1873 */
1874 val &= ~PIPECONF_BPC_MASK;
1875 val |= pipeconf_val & PIPECONF_BPC_MASK;
1876 }
1877
1878 val &= ~TRANS_INTERLACE_MASK;
1879 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1880 if (HAS_PCH_IBX(dev_priv->dev) &&
1881 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1882 val |= TRANS_LEGACY_INTERLACED_ILK;
1883 else
1884 val |= TRANS_INTERLACED;
1885 else
1886 val |= TRANS_PROGRESSIVE;
1887
1888 I915_WRITE(reg, val | TRANS_ENABLE);
1889 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1890 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1891 }
1892
1893 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1894 enum transcoder cpu_transcoder)
1895 {
1896 u32 val, pipeconf_val;
1897
1898 /* PCH only available on ILK+ */
1899 BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
1900
1901 /* FDI must be feeding us bits for PCH ports */
1902 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1903 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1904
1905 /* Workaround: set timing override bit. */
1906 val = I915_READ(_TRANSA_CHICKEN2);
1907 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1908 I915_WRITE(_TRANSA_CHICKEN2, val);
1909
1910 val = TRANS_ENABLE;
1911 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1912
1913 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1914 PIPECONF_INTERLACED_ILK)
1915 val |= TRANS_INTERLACED;
1916 else
1917 val |= TRANS_PROGRESSIVE;
1918
1919 I915_WRITE(LPT_TRANSCONF, val);
1920 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1921 DRM_ERROR("Failed to enable PCH transcoder\n");
1922 }
1923
1924 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1925 enum pipe pipe)
1926 {
1927 struct drm_device *dev = dev_priv->dev;
1928 uint32_t reg, val;
1929
1930 /* FDI relies on the transcoder */
1931 assert_fdi_tx_disabled(dev_priv, pipe);
1932 assert_fdi_rx_disabled(dev_priv, pipe);
1933
1934 /* Ports must be off as well */
1935 assert_pch_ports_disabled(dev_priv, pipe);
1936
1937 reg = PCH_TRANSCONF(pipe);
1938 val = I915_READ(reg);
1939 val &= ~TRANS_ENABLE;
1940 I915_WRITE(reg, val);
1941 /* wait for PCH transcoder off, transcoder state */
1942 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1943 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1944
1945 if (!HAS_PCH_IBX(dev)) {
1946 /* Workaround: Clear the timing override chicken bit again. */
1947 reg = TRANS_CHICKEN2(pipe);
1948 val = I915_READ(reg);
1949 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1950 I915_WRITE(reg, val);
1951 }
1952 }
1953
1954 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1955 {
1956 u32 val;
1957
1958 val = I915_READ(LPT_TRANSCONF);
1959 val &= ~TRANS_ENABLE;
1960 I915_WRITE(LPT_TRANSCONF, val);
1961 /* wait for PCH transcoder off, transcoder state */
1962 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1963 DRM_ERROR("Failed to disable PCH transcoder\n");
1964
1965 /* Workaround: clear timing override bit. */
1966 val = I915_READ(_TRANSA_CHICKEN2);
1967 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1968 I915_WRITE(_TRANSA_CHICKEN2, val);
1969 }
1970
1971 /**
1972 * intel_enable_pipe - enable a pipe, asserting requirements
1973 * @crtc: crtc responsible for the pipe
1974 *
1975 * Enable @crtc's pipe, making sure that various hardware specific requirements
1976 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1977 */
1978 static void intel_enable_pipe(struct intel_crtc *crtc)
1979 {
1980 struct drm_device *dev = crtc->base.dev;
1981 struct drm_i915_private *dev_priv = dev->dev_private;
1982 enum pipe pipe = crtc->pipe;
1983 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1984 pipe);
1985 enum pipe pch_transcoder;
1986 int reg;
1987 u32 val;
1988
1989 assert_planes_disabled(dev_priv, pipe);
1990 assert_cursor_disabled(dev_priv, pipe);
1991 assert_sprites_disabled(dev_priv, pipe);
1992
1993 if (HAS_PCH_LPT(dev_priv->dev))
1994 pch_transcoder = TRANSCODER_A;
1995 else
1996 pch_transcoder = pipe;
1997
1998 /*
1999 * A pipe without a PLL won't actually be able to drive bits from
2000 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2001 * need the check.
2002 */
2003 if (!HAS_PCH_SPLIT(dev_priv->dev))
2004 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
2005 assert_dsi_pll_enabled(dev_priv);
2006 else
2007 assert_pll_enabled(dev_priv, pipe);
2008 else {
2009 if (crtc->config.has_pch_encoder) {
2010 /* if driving the PCH, we need FDI enabled */
2011 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2012 assert_fdi_tx_pll_enabled(dev_priv,
2013 (enum pipe) cpu_transcoder);
2014 }
2015 /* FIXME: assert CPU port conditions for SNB+ */
2016 }
2017
2018 reg = PIPECONF(cpu_transcoder);
2019 val = I915_READ(reg);
2020 if (val & PIPECONF_ENABLE) {
2021 WARN_ON(!(pipe == PIPE_A &&
2022 dev_priv->quirks & QUIRK_PIPEA_FORCE));
2023 return;
2024 }
2025
2026 I915_WRITE(reg, val | PIPECONF_ENABLE);
2027 POSTING_READ(reg);
2028 }
2029
2030 /**
2031 * intel_disable_pipe - disable a pipe, asserting requirements
2032 * @dev_priv: i915 private structure
2033 * @pipe: pipe to disable
2034 *
2035 * Disable @pipe, making sure that various hardware specific requirements
2036 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
2037 *
2038 * @pipe should be %PIPE_A or %PIPE_B.
2039 *
2040 * Will wait until the pipe has shut down before returning.
2041 */
2042 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
2043 enum pipe pipe)
2044 {
2045 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2046 pipe);
2047 int reg;
2048 u32 val;
2049
2050 /*
2051 * Make sure planes won't keep trying to pump pixels to us,
2052 * or we might hang the display.
2053 */
2054 assert_planes_disabled(dev_priv, pipe);
2055 assert_cursor_disabled(dev_priv, pipe);
2056 assert_sprites_disabled(dev_priv, pipe);
2057
2058 /* Don't disable pipe A or pipe A PLLs if needed */
2059 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2060 return;
2061
2062 reg = PIPECONF(cpu_transcoder);
2063 val = I915_READ(reg);
2064 if ((val & PIPECONF_ENABLE) == 0)
2065 return;
2066
2067 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
2068 intel_wait_for_pipe_off(dev_priv->dev, pipe);
2069 }
2070
2071 /*
2072 * Plane regs are double buffered, going from enabled->disabled needs a
2073 * trigger in order to latch. The display address reg provides this.
2074 */
2075 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2076 enum plane plane)
2077 {
2078 struct drm_device *dev = dev_priv->dev;
2079 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2080
2081 I915_WRITE(reg, I915_READ(reg));
2082 POSTING_READ(reg);
2083 }
2084
2085 /**
2086 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2087 * @plane: plane to be enabled
2088 * @crtc: crtc for the plane
2089 *
2090 * Enable @plane on @crtc, making sure that the pipe is running first.
2091 */
2092 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2093 struct drm_crtc *crtc)
2094 {
2095 struct drm_device *dev = plane->dev;
2096 struct drm_i915_private *dev_priv = dev->dev_private;
2097 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2098
2099 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2100 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2101
2102 if (intel_crtc->primary_enabled)
2103 return;
2104
2105 intel_crtc->primary_enabled = true;
2106
2107 dev_priv->display.update_primary_plane(crtc, plane->fb,
2108 crtc->x, crtc->y);
2109
2110 /*
2111 * BDW signals flip done immediately if the plane
2112 * is disabled, even if the plane enable is already
2113 * armed to occur at the next vblank :(
2114 */
2115 if (IS_BROADWELL(dev))
2116 intel_wait_for_vblank(dev, intel_crtc->pipe);
2117 }
2118
2119 /**
2120 * intel_disable_primary_hw_plane - disable the primary hardware plane
2121 * @plane: plane to be disabled
2122 * @crtc: crtc for the plane
2123 *
2124 * Disable @plane on @crtc, making sure that the pipe is running first.
2125 */
2126 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2127 struct drm_crtc *crtc)
2128 {
2129 struct drm_device *dev = plane->dev;
2130 struct drm_i915_private *dev_priv = dev->dev_private;
2131 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2132
2133 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2134
2135 if (!intel_crtc->primary_enabled)
2136 return;
2137
2138 intel_crtc->primary_enabled = false;
2139
2140 dev_priv->display.update_primary_plane(crtc, plane->fb,
2141 crtc->x, crtc->y);
2142 }
2143
2144 static bool need_vtd_wa(struct drm_device *dev)
2145 {
2146 #ifdef CONFIG_INTEL_IOMMU
2147 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2148 return true;
2149 #endif
2150 return false;
2151 }
2152
2153 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2154 {
2155 int tile_height;
2156
2157 tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2158 return ALIGN(height, tile_height);
2159 }
2160
2161 int
2162 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2163 struct drm_i915_gem_object *obj,
2164 struct intel_engine_cs *pipelined)
2165 {
2166 struct drm_i915_private *dev_priv = dev->dev_private;
2167 u32 alignment;
2168 int ret;
2169
2170 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2171
2172 switch (obj->tiling_mode) {
2173 case I915_TILING_NONE:
2174 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2175 alignment = 128 * 1024;
2176 else if (INTEL_INFO(dev)->gen >= 4)
2177 alignment = 4 * 1024;
2178 else
2179 alignment = 64 * 1024;
2180 break;
2181 case I915_TILING_X:
2182 /* pin() will align the object as required by fence */
2183 alignment = 0;
2184 break;
2185 case I915_TILING_Y:
2186 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2187 return -EINVAL;
2188 default:
2189 BUG();
2190 }
2191
2192 /* Note that the w/a also requires 64 PTE of padding following the
2193 * bo. We currently fill all unused PTE with the shadow page and so
2194 * we should always have valid PTE following the scanout preventing
2195 * the VT-d warning.
2196 */
2197 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2198 alignment = 256 * 1024;
2199
2200 dev_priv->mm.interruptible = false;
2201 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2202 if (ret)
2203 goto err_interruptible;
2204
2205 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2206 * fence, whereas 965+ only requires a fence if using
2207 * framebuffer compression. For simplicity, we always install
2208 * a fence as the cost is not that onerous.
2209 */
2210 ret = i915_gem_object_get_fence(obj);
2211 if (ret)
2212 goto err_unpin;
2213
2214 i915_gem_object_pin_fence(obj);
2215
2216 dev_priv->mm.interruptible = true;
2217 return 0;
2218
2219 err_unpin:
2220 i915_gem_object_unpin_from_display_plane(obj);
2221 err_interruptible:
2222 dev_priv->mm.interruptible = true;
2223 return ret;
2224 }
2225
2226 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2227 {
2228 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2229
2230 i915_gem_object_unpin_fence(obj);
2231 i915_gem_object_unpin_from_display_plane(obj);
2232 }
2233
2234 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2235 * is assumed to be a power-of-two. */
2236 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2237 unsigned int tiling_mode,
2238 unsigned int cpp,
2239 unsigned int pitch)
2240 {
2241 if (tiling_mode != I915_TILING_NONE) {
2242 unsigned int tile_rows, tiles;
2243
2244 tile_rows = *y / 8;
2245 *y %= 8;
2246
2247 tiles = *x / (512/cpp);
2248 *x %= 512/cpp;
2249
2250 return tile_rows * pitch * 8 + tiles * 4096;
2251 } else {
2252 unsigned int offset;
2253
2254 offset = *y * pitch + *x * cpp;
2255 *y = 0;
2256 *x = (offset & 4095) / cpp;
2257 return offset & -4096;
2258 }
2259 }
2260
2261 int intel_format_to_fourcc(int format)
2262 {
2263 switch (format) {
2264 case DISPPLANE_8BPP:
2265 return DRM_FORMAT_C8;
2266 case DISPPLANE_BGRX555:
2267 return DRM_FORMAT_XRGB1555;
2268 case DISPPLANE_BGRX565:
2269 return DRM_FORMAT_RGB565;
2270 default:
2271 case DISPPLANE_BGRX888:
2272 return DRM_FORMAT_XRGB8888;
2273 case DISPPLANE_RGBX888:
2274 return DRM_FORMAT_XBGR8888;
2275 case DISPPLANE_BGRX101010:
2276 return DRM_FORMAT_XRGB2101010;
2277 case DISPPLANE_RGBX101010:
2278 return DRM_FORMAT_XBGR2101010;
2279 }
2280 }
2281
2282 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2283 struct intel_plane_config *plane_config)
2284 {
2285 struct drm_device *dev = crtc->base.dev;
2286 struct drm_i915_gem_object *obj = NULL;
2287 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2288 u32 base = plane_config->base;
2289
2290 if (plane_config->size == 0)
2291 return false;
2292
2293 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2294 plane_config->size);
2295 if (!obj)
2296 return false;
2297
2298 if (plane_config->tiled) {
2299 obj->tiling_mode = I915_TILING_X;
2300 obj->stride = crtc->base.primary->fb->pitches[0];
2301 }
2302
2303 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2304 mode_cmd.width = crtc->base.primary->fb->width;
2305 mode_cmd.height = crtc->base.primary->fb->height;
2306 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2307
2308 mutex_lock(&dev->struct_mutex);
2309
2310 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2311 &mode_cmd, obj)) {
2312 DRM_DEBUG_KMS("intel fb init failed\n");
2313 goto out_unref_obj;
2314 }
2315
2316 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2317 mutex_unlock(&dev->struct_mutex);
2318
2319 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2320 return true;
2321
2322 out_unref_obj:
2323 drm_gem_object_unreference(&obj->base);
2324 mutex_unlock(&dev->struct_mutex);
2325 return false;
2326 }
2327
2328 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2329 struct intel_plane_config *plane_config)
2330 {
2331 struct drm_device *dev = intel_crtc->base.dev;
2332 struct drm_crtc *c;
2333 struct intel_crtc *i;
2334 struct drm_i915_gem_object *obj;
2335
2336 if (!intel_crtc->base.primary->fb)
2337 return;
2338
2339 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2340 return;
2341
2342 kfree(intel_crtc->base.primary->fb);
2343 intel_crtc->base.primary->fb = NULL;
2344
2345 /*
2346 * Failed to alloc the obj, check to see if we should share
2347 * an fb with another CRTC instead
2348 */
2349 for_each_crtc(dev, c) {
2350 i = to_intel_crtc(c);
2351
2352 if (c == &intel_crtc->base)
2353 continue;
2354
2355 if (!i->active)
2356 continue;
2357
2358 obj = intel_fb_obj(c->primary->fb);
2359 if (obj == NULL)
2360 continue;
2361
2362 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2363 drm_framebuffer_reference(c->primary->fb);
2364 intel_crtc->base.primary->fb = c->primary->fb;
2365 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2366 break;
2367 }
2368 }
2369 }
2370
2371 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2372 struct drm_framebuffer *fb,
2373 int x, int y)
2374 {
2375 struct drm_device *dev = crtc->dev;
2376 struct drm_i915_private *dev_priv = dev->dev_private;
2377 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2378 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2379 int plane = intel_crtc->plane;
2380 unsigned long linear_offset;
2381 u32 dspcntr;
2382 u32 reg = DSPCNTR(plane);
2383 int pixel_size;
2384
2385 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2386
2387 if (!intel_crtc->primary_enabled) {
2388 I915_WRITE(reg, 0);
2389 if (INTEL_INFO(dev)->gen >= 4)
2390 I915_WRITE(DSPSURF(plane), 0);
2391 else
2392 I915_WRITE(DSPADDR(plane), 0);
2393 POSTING_READ(reg);
2394 return;
2395 }
2396
2397 dspcntr = DISPPLANE_GAMMA_ENABLE;
2398
2399 dspcntr |= DISPLAY_PLANE_ENABLE;
2400
2401 if (INTEL_INFO(dev)->gen < 4) {
2402 if (intel_crtc->pipe == PIPE_B)
2403 dspcntr |= DISPPLANE_SEL_PIPE_B;
2404
2405 /* pipesrc and dspsize control the size that is scaled from,
2406 * which should always be the user's requested size.
2407 */
2408 I915_WRITE(DSPSIZE(plane),
2409 ((intel_crtc->config.pipe_src_h - 1) << 16) |
2410 (intel_crtc->config.pipe_src_w - 1));
2411 I915_WRITE(DSPPOS(plane), 0);
2412 }
2413
2414 switch (fb->pixel_format) {
2415 case DRM_FORMAT_C8:
2416 dspcntr |= DISPPLANE_8BPP;
2417 break;
2418 case DRM_FORMAT_XRGB1555:
2419 case DRM_FORMAT_ARGB1555:
2420 dspcntr |= DISPPLANE_BGRX555;
2421 break;
2422 case DRM_FORMAT_RGB565:
2423 dspcntr |= DISPPLANE_BGRX565;
2424 break;
2425 case DRM_FORMAT_XRGB8888:
2426 case DRM_FORMAT_ARGB8888:
2427 dspcntr |= DISPPLANE_BGRX888;
2428 break;
2429 case DRM_FORMAT_XBGR8888:
2430 case DRM_FORMAT_ABGR8888:
2431 dspcntr |= DISPPLANE_RGBX888;
2432 break;
2433 case DRM_FORMAT_XRGB2101010:
2434 case DRM_FORMAT_ARGB2101010:
2435 dspcntr |= DISPPLANE_BGRX101010;
2436 break;
2437 case DRM_FORMAT_XBGR2101010:
2438 case DRM_FORMAT_ABGR2101010:
2439 dspcntr |= DISPPLANE_RGBX101010;
2440 break;
2441 default:
2442 BUG();
2443 }
2444
2445 if (INTEL_INFO(dev)->gen >= 4 &&
2446 obj->tiling_mode != I915_TILING_NONE)
2447 dspcntr |= DISPPLANE_TILED;
2448
2449 if (IS_G4X(dev))
2450 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2451
2452 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2453
2454 if (INTEL_INFO(dev)->gen >= 4) {
2455 intel_crtc->dspaddr_offset =
2456 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2457 fb->bits_per_pixel / 8,
2458 fb->pitches[0]);
2459 linear_offset -= intel_crtc->dspaddr_offset;
2460 } else {
2461 intel_crtc->dspaddr_offset = linear_offset;
2462 }
2463
2464 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2465 dspcntr |= DISPPLANE_ROTATE_180;
2466
2467 x += (intel_crtc->config.pipe_src_w - 1);
2468 y += (intel_crtc->config.pipe_src_h - 1);
2469
2470 /* Finding the last pixel of the last line of the display
2471 data and adding to linear_offset*/
2472 linear_offset +=
2473 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2474 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2475 }
2476
2477 I915_WRITE(reg, dspcntr);
2478
2479 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2480 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2481 fb->pitches[0]);
2482 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2483 if (INTEL_INFO(dev)->gen >= 4) {
2484 I915_WRITE(DSPSURF(plane),
2485 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2486 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2487 I915_WRITE(DSPLINOFF(plane), linear_offset);
2488 } else
2489 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2490 POSTING_READ(reg);
2491 }
2492
2493 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2494 struct drm_framebuffer *fb,
2495 int x, int y)
2496 {
2497 struct drm_device *dev = crtc->dev;
2498 struct drm_i915_private *dev_priv = dev->dev_private;
2499 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2500 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2501 int plane = intel_crtc->plane;
2502 unsigned long linear_offset;
2503 u32 dspcntr;
2504 u32 reg = DSPCNTR(plane);
2505 int pixel_size;
2506
2507 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2508
2509 if (!intel_crtc->primary_enabled) {
2510 I915_WRITE(reg, 0);
2511 I915_WRITE(DSPSURF(plane), 0);
2512 POSTING_READ(reg);
2513 return;
2514 }
2515
2516 dspcntr = DISPPLANE_GAMMA_ENABLE;
2517
2518 dspcntr |= DISPLAY_PLANE_ENABLE;
2519
2520 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2521 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2522
2523 switch (fb->pixel_format) {
2524 case DRM_FORMAT_C8:
2525 dspcntr |= DISPPLANE_8BPP;
2526 break;
2527 case DRM_FORMAT_RGB565:
2528 dspcntr |= DISPPLANE_BGRX565;
2529 break;
2530 case DRM_FORMAT_XRGB8888:
2531 case DRM_FORMAT_ARGB8888:
2532 dspcntr |= DISPPLANE_BGRX888;
2533 break;
2534 case DRM_FORMAT_XBGR8888:
2535 case DRM_FORMAT_ABGR8888:
2536 dspcntr |= DISPPLANE_RGBX888;
2537 break;
2538 case DRM_FORMAT_XRGB2101010:
2539 case DRM_FORMAT_ARGB2101010:
2540 dspcntr |= DISPPLANE_BGRX101010;
2541 break;
2542 case DRM_FORMAT_XBGR2101010:
2543 case DRM_FORMAT_ABGR2101010:
2544 dspcntr |= DISPPLANE_RGBX101010;
2545 break;
2546 default:
2547 BUG();
2548 }
2549
2550 if (obj->tiling_mode != I915_TILING_NONE)
2551 dspcntr |= DISPPLANE_TILED;
2552
2553 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2554 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2555
2556 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2557 intel_crtc->dspaddr_offset =
2558 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2559 fb->bits_per_pixel / 8,
2560 fb->pitches[0]);
2561 linear_offset -= intel_crtc->dspaddr_offset;
2562 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2563 dspcntr |= DISPPLANE_ROTATE_180;
2564
2565 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2566 x += (intel_crtc->config.pipe_src_w - 1);
2567 y += (intel_crtc->config.pipe_src_h - 1);
2568
2569 /* Finding the last pixel of the last line of the display
2570 data and adding to linear_offset*/
2571 linear_offset +=
2572 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2573 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2574 }
2575 }
2576
2577 I915_WRITE(reg, dspcntr);
2578
2579 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2580 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2581 fb->pitches[0]);
2582 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2583 I915_WRITE(DSPSURF(plane),
2584 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2585 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2586 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2587 } else {
2588 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2589 I915_WRITE(DSPLINOFF(plane), linear_offset);
2590 }
2591 POSTING_READ(reg);
2592 }
2593
2594 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2595 static int
2596 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2597 int x, int y, enum mode_set_atomic state)
2598 {
2599 struct drm_device *dev = crtc->dev;
2600 struct drm_i915_private *dev_priv = dev->dev_private;
2601
2602 if (dev_priv->display.disable_fbc)
2603 dev_priv->display.disable_fbc(dev);
2604 intel_increase_pllclock(dev, to_intel_crtc(crtc)->pipe);
2605
2606 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2607
2608 return 0;
2609 }
2610
2611 void intel_display_handle_reset(struct drm_device *dev)
2612 {
2613 struct drm_i915_private *dev_priv = dev->dev_private;
2614 struct drm_crtc *crtc;
2615
2616 /*
2617 * Flips in the rings have been nuked by the reset,
2618 * so complete all pending flips so that user space
2619 * will get its events and not get stuck.
2620 *
2621 * Also update the base address of all primary
2622 * planes to the the last fb to make sure we're
2623 * showing the correct fb after a reset.
2624 *
2625 * Need to make two loops over the crtcs so that we
2626 * don't try to grab a crtc mutex before the
2627 * pending_flip_queue really got woken up.
2628 */
2629
2630 for_each_crtc(dev, crtc) {
2631 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2632 enum plane plane = intel_crtc->plane;
2633
2634 intel_prepare_page_flip(dev, plane);
2635 intel_finish_page_flip_plane(dev, plane);
2636 }
2637
2638 for_each_crtc(dev, crtc) {
2639 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2640
2641 drm_modeset_lock(&crtc->mutex, NULL);
2642 /*
2643 * FIXME: Once we have proper support for primary planes (and
2644 * disabling them without disabling the entire crtc) allow again
2645 * a NULL crtc->primary->fb.
2646 */
2647 if (intel_crtc->active && crtc->primary->fb)
2648 dev_priv->display.update_primary_plane(crtc,
2649 crtc->primary->fb,
2650 crtc->x,
2651 crtc->y);
2652 drm_modeset_unlock(&crtc->mutex);
2653 }
2654 }
2655
2656 static int
2657 intel_finish_fb(struct drm_framebuffer *old_fb)
2658 {
2659 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2660 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2661 bool was_interruptible = dev_priv->mm.interruptible;
2662 int ret;
2663
2664 /* Big Hammer, we also need to ensure that any pending
2665 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2666 * current scanout is retired before unpinning the old
2667 * framebuffer.
2668 *
2669 * This should only fail upon a hung GPU, in which case we
2670 * can safely continue.
2671 */
2672 dev_priv->mm.interruptible = false;
2673 ret = i915_gem_object_finish_gpu(obj);
2674 dev_priv->mm.interruptible = was_interruptible;
2675
2676 return ret;
2677 }
2678
2679 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2680 {
2681 struct drm_device *dev = crtc->dev;
2682 struct drm_i915_private *dev_priv = dev->dev_private;
2683 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2684 unsigned long flags;
2685 bool pending;
2686
2687 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2688 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2689 return false;
2690
2691 spin_lock_irqsave(&dev->event_lock, flags);
2692 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2693 spin_unlock_irqrestore(&dev->event_lock, flags);
2694
2695 return pending;
2696 }
2697
2698 static int
2699 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2700 struct drm_framebuffer *fb)
2701 {
2702 struct drm_device *dev = crtc->dev;
2703 struct drm_i915_private *dev_priv = dev->dev_private;
2704 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2705 enum pipe pipe = intel_crtc->pipe;
2706 struct drm_framebuffer *old_fb = crtc->primary->fb;
2707 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2708 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
2709 int ret;
2710
2711 if (intel_crtc_has_pending_flip(crtc)) {
2712 DRM_ERROR("pipe is still busy with an old pageflip\n");
2713 return -EBUSY;
2714 }
2715
2716 /* no fb bound */
2717 if (!fb) {
2718 DRM_ERROR("No FB bound\n");
2719 return 0;
2720 }
2721
2722 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2723 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2724 plane_name(intel_crtc->plane),
2725 INTEL_INFO(dev)->num_pipes);
2726 return -EINVAL;
2727 }
2728
2729 mutex_lock(&dev->struct_mutex);
2730 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
2731 if (ret == 0)
2732 i915_gem_track_fb(old_obj, obj,
2733 INTEL_FRONTBUFFER_PRIMARY(pipe));
2734 mutex_unlock(&dev->struct_mutex);
2735 if (ret != 0) {
2736 DRM_ERROR("pin & fence failed\n");
2737 return ret;
2738 }
2739
2740 /*
2741 * Update pipe size and adjust fitter if needed: the reason for this is
2742 * that in compute_mode_changes we check the native mode (not the pfit
2743 * mode) to see if we can flip rather than do a full mode set. In the
2744 * fastboot case, we'll flip, but if we don't update the pipesrc and
2745 * pfit state, we'll end up with a big fb scanned out into the wrong
2746 * sized surface.
2747 *
2748 * To fix this properly, we need to hoist the checks up into
2749 * compute_mode_changes (or above), check the actual pfit state and
2750 * whether the platform allows pfit disable with pipe active, and only
2751 * then update the pipesrc and pfit state, even on the flip path.
2752 */
2753 if (i915.fastboot) {
2754 const struct drm_display_mode *adjusted_mode =
2755 &intel_crtc->config.adjusted_mode;
2756
2757 I915_WRITE(PIPESRC(intel_crtc->pipe),
2758 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2759 (adjusted_mode->crtc_vdisplay - 1));
2760 if (!intel_crtc->config.pch_pfit.enabled &&
2761 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2762 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2763 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2764 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2765 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2766 }
2767 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2768 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2769 }
2770
2771 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2772
2773 if (intel_crtc->active)
2774 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
2775
2776 crtc->primary->fb = fb;
2777 crtc->x = x;
2778 crtc->y = y;
2779
2780 if (old_fb) {
2781 if (intel_crtc->active && old_fb != fb)
2782 intel_wait_for_vblank(dev, intel_crtc->pipe);
2783 mutex_lock(&dev->struct_mutex);
2784 intel_unpin_fb_obj(old_obj);
2785 mutex_unlock(&dev->struct_mutex);
2786 }
2787
2788 mutex_lock(&dev->struct_mutex);
2789 intel_update_fbc(dev);
2790 mutex_unlock(&dev->struct_mutex);
2791
2792 return 0;
2793 }
2794
2795 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2796 {
2797 struct drm_device *dev = crtc->dev;
2798 struct drm_i915_private *dev_priv = dev->dev_private;
2799 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2800 int pipe = intel_crtc->pipe;
2801 u32 reg, temp;
2802
2803 /* enable normal train */
2804 reg = FDI_TX_CTL(pipe);
2805 temp = I915_READ(reg);
2806 if (IS_IVYBRIDGE(dev)) {
2807 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2808 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2809 } else {
2810 temp &= ~FDI_LINK_TRAIN_NONE;
2811 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2812 }
2813 I915_WRITE(reg, temp);
2814
2815 reg = FDI_RX_CTL(pipe);
2816 temp = I915_READ(reg);
2817 if (HAS_PCH_CPT(dev)) {
2818 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2819 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2820 } else {
2821 temp &= ~FDI_LINK_TRAIN_NONE;
2822 temp |= FDI_LINK_TRAIN_NONE;
2823 }
2824 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2825
2826 /* wait one idle pattern time */
2827 POSTING_READ(reg);
2828 udelay(1000);
2829
2830 /* IVB wants error correction enabled */
2831 if (IS_IVYBRIDGE(dev))
2832 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2833 FDI_FE_ERRC_ENABLE);
2834 }
2835
2836 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2837 {
2838 return crtc->base.enabled && crtc->active &&
2839 crtc->config.has_pch_encoder;
2840 }
2841
2842 static void ivb_modeset_global_resources(struct drm_device *dev)
2843 {
2844 struct drm_i915_private *dev_priv = dev->dev_private;
2845 struct intel_crtc *pipe_B_crtc =
2846 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2847 struct intel_crtc *pipe_C_crtc =
2848 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2849 uint32_t temp;
2850
2851 /*
2852 * When everything is off disable fdi C so that we could enable fdi B
2853 * with all lanes. Note that we don't care about enabled pipes without
2854 * an enabled pch encoder.
2855 */
2856 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2857 !pipe_has_enabled_pch(pipe_C_crtc)) {
2858 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2859 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2860
2861 temp = I915_READ(SOUTH_CHICKEN1);
2862 temp &= ~FDI_BC_BIFURCATION_SELECT;
2863 DRM_DEBUG_KMS("disabling fdi C rx\n");
2864 I915_WRITE(SOUTH_CHICKEN1, temp);
2865 }
2866 }
2867
2868 /* The FDI link training functions for ILK/Ibexpeak. */
2869 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2870 {
2871 struct drm_device *dev = crtc->dev;
2872 struct drm_i915_private *dev_priv = dev->dev_private;
2873 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2874 int pipe = intel_crtc->pipe;
2875 u32 reg, temp, tries;
2876
2877 /* FDI needs bits from pipe first */
2878 assert_pipe_enabled(dev_priv, pipe);
2879
2880 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2881 for train result */
2882 reg = FDI_RX_IMR(pipe);
2883 temp = I915_READ(reg);
2884 temp &= ~FDI_RX_SYMBOL_LOCK;
2885 temp &= ~FDI_RX_BIT_LOCK;
2886 I915_WRITE(reg, temp);
2887 I915_READ(reg);
2888 udelay(150);
2889
2890 /* enable CPU FDI TX and PCH FDI RX */
2891 reg = FDI_TX_CTL(pipe);
2892 temp = I915_READ(reg);
2893 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2894 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2895 temp &= ~FDI_LINK_TRAIN_NONE;
2896 temp |= FDI_LINK_TRAIN_PATTERN_1;
2897 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2898
2899 reg = FDI_RX_CTL(pipe);
2900 temp = I915_READ(reg);
2901 temp &= ~FDI_LINK_TRAIN_NONE;
2902 temp |= FDI_LINK_TRAIN_PATTERN_1;
2903 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2904
2905 POSTING_READ(reg);
2906 udelay(150);
2907
2908 /* Ironlake workaround, enable clock pointer after FDI enable*/
2909 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2910 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2911 FDI_RX_PHASE_SYNC_POINTER_EN);
2912
2913 reg = FDI_RX_IIR(pipe);
2914 for (tries = 0; tries < 5; tries++) {
2915 temp = I915_READ(reg);
2916 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2917
2918 if ((temp & FDI_RX_BIT_LOCK)) {
2919 DRM_DEBUG_KMS("FDI train 1 done.\n");
2920 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2921 break;
2922 }
2923 }
2924 if (tries == 5)
2925 DRM_ERROR("FDI train 1 fail!\n");
2926
2927 /* Train 2 */
2928 reg = FDI_TX_CTL(pipe);
2929 temp = I915_READ(reg);
2930 temp &= ~FDI_LINK_TRAIN_NONE;
2931 temp |= FDI_LINK_TRAIN_PATTERN_2;
2932 I915_WRITE(reg, temp);
2933
2934 reg = FDI_RX_CTL(pipe);
2935 temp = I915_READ(reg);
2936 temp &= ~FDI_LINK_TRAIN_NONE;
2937 temp |= FDI_LINK_TRAIN_PATTERN_2;
2938 I915_WRITE(reg, temp);
2939
2940 POSTING_READ(reg);
2941 udelay(150);
2942
2943 reg = FDI_RX_IIR(pipe);
2944 for (tries = 0; tries < 5; tries++) {
2945 temp = I915_READ(reg);
2946 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2947
2948 if (temp & FDI_RX_SYMBOL_LOCK) {
2949 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2950 DRM_DEBUG_KMS("FDI train 2 done.\n");
2951 break;
2952 }
2953 }
2954 if (tries == 5)
2955 DRM_ERROR("FDI train 2 fail!\n");
2956
2957 DRM_DEBUG_KMS("FDI train done\n");
2958
2959 }
2960
2961 static const int snb_b_fdi_train_param[] = {
2962 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2963 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2964 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2965 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2966 };
2967
2968 /* The FDI link training functions for SNB/Cougarpoint. */
2969 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2970 {
2971 struct drm_device *dev = crtc->dev;
2972 struct drm_i915_private *dev_priv = dev->dev_private;
2973 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2974 int pipe = intel_crtc->pipe;
2975 u32 reg, temp, i, retry;
2976
2977 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2978 for train result */
2979 reg = FDI_RX_IMR(pipe);
2980 temp = I915_READ(reg);
2981 temp &= ~FDI_RX_SYMBOL_LOCK;
2982 temp &= ~FDI_RX_BIT_LOCK;
2983 I915_WRITE(reg, temp);
2984
2985 POSTING_READ(reg);
2986 udelay(150);
2987
2988 /* enable CPU FDI TX and PCH FDI RX */
2989 reg = FDI_TX_CTL(pipe);
2990 temp = I915_READ(reg);
2991 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2992 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2993 temp &= ~FDI_LINK_TRAIN_NONE;
2994 temp |= FDI_LINK_TRAIN_PATTERN_1;
2995 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2996 /* SNB-B */
2997 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2998 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2999
3000 I915_WRITE(FDI_RX_MISC(pipe),
3001 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3002
3003 reg = FDI_RX_CTL(pipe);
3004 temp = I915_READ(reg);
3005 if (HAS_PCH_CPT(dev)) {
3006 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3007 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3008 } else {
3009 temp &= ~FDI_LINK_TRAIN_NONE;
3010 temp |= FDI_LINK_TRAIN_PATTERN_1;
3011 }
3012 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3013
3014 POSTING_READ(reg);
3015 udelay(150);
3016
3017 for (i = 0; i < 4; i++) {
3018 reg = FDI_TX_CTL(pipe);
3019 temp = I915_READ(reg);
3020 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3021 temp |= snb_b_fdi_train_param[i];
3022 I915_WRITE(reg, temp);
3023
3024 POSTING_READ(reg);
3025 udelay(500);
3026
3027 for (retry = 0; retry < 5; retry++) {
3028 reg = FDI_RX_IIR(pipe);
3029 temp = I915_READ(reg);
3030 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3031 if (temp & FDI_RX_BIT_LOCK) {
3032 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3033 DRM_DEBUG_KMS("FDI train 1 done.\n");
3034 break;
3035 }
3036 udelay(50);
3037 }
3038 if (retry < 5)
3039 break;
3040 }
3041 if (i == 4)
3042 DRM_ERROR("FDI train 1 fail!\n");
3043
3044 /* Train 2 */
3045 reg = FDI_TX_CTL(pipe);
3046 temp = I915_READ(reg);
3047 temp &= ~FDI_LINK_TRAIN_NONE;
3048 temp |= FDI_LINK_TRAIN_PATTERN_2;
3049 if (IS_GEN6(dev)) {
3050 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3051 /* SNB-B */
3052 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3053 }
3054 I915_WRITE(reg, temp);
3055
3056 reg = FDI_RX_CTL(pipe);
3057 temp = I915_READ(reg);
3058 if (HAS_PCH_CPT(dev)) {
3059 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3060 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3061 } else {
3062 temp &= ~FDI_LINK_TRAIN_NONE;
3063 temp |= FDI_LINK_TRAIN_PATTERN_2;
3064 }
3065 I915_WRITE(reg, temp);
3066
3067 POSTING_READ(reg);
3068 udelay(150);
3069
3070 for (i = 0; i < 4; i++) {
3071 reg = FDI_TX_CTL(pipe);
3072 temp = I915_READ(reg);
3073 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3074 temp |= snb_b_fdi_train_param[i];
3075 I915_WRITE(reg, temp);
3076
3077 POSTING_READ(reg);
3078 udelay(500);
3079
3080 for (retry = 0; retry < 5; retry++) {
3081 reg = FDI_RX_IIR(pipe);
3082 temp = I915_READ(reg);
3083 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3084 if (temp & FDI_RX_SYMBOL_LOCK) {
3085 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3086 DRM_DEBUG_KMS("FDI train 2 done.\n");
3087 break;
3088 }
3089 udelay(50);
3090 }
3091 if (retry < 5)
3092 break;
3093 }
3094 if (i == 4)
3095 DRM_ERROR("FDI train 2 fail!\n");
3096
3097 DRM_DEBUG_KMS("FDI train done.\n");
3098 }
3099
3100 /* Manual link training for Ivy Bridge A0 parts */
3101 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3102 {
3103 struct drm_device *dev = crtc->dev;
3104 struct drm_i915_private *dev_priv = dev->dev_private;
3105 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3106 int pipe = intel_crtc->pipe;
3107 u32 reg, temp, i, j;
3108
3109 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3110 for train result */
3111 reg = FDI_RX_IMR(pipe);
3112 temp = I915_READ(reg);
3113 temp &= ~FDI_RX_SYMBOL_LOCK;
3114 temp &= ~FDI_RX_BIT_LOCK;
3115 I915_WRITE(reg, temp);
3116
3117 POSTING_READ(reg);
3118 udelay(150);
3119
3120 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3121 I915_READ(FDI_RX_IIR(pipe)));
3122
3123 /* Try each vswing and preemphasis setting twice before moving on */
3124 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3125 /* disable first in case we need to retry */
3126 reg = FDI_TX_CTL(pipe);
3127 temp = I915_READ(reg);
3128 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3129 temp &= ~FDI_TX_ENABLE;
3130 I915_WRITE(reg, temp);
3131
3132 reg = FDI_RX_CTL(pipe);
3133 temp = I915_READ(reg);
3134 temp &= ~FDI_LINK_TRAIN_AUTO;
3135 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3136 temp &= ~FDI_RX_ENABLE;
3137 I915_WRITE(reg, temp);
3138
3139 /* enable CPU FDI TX and PCH FDI RX */
3140 reg = FDI_TX_CTL(pipe);
3141 temp = I915_READ(reg);
3142 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3143 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3144 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3145 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3146 temp |= snb_b_fdi_train_param[j/2];
3147 temp |= FDI_COMPOSITE_SYNC;
3148 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3149
3150 I915_WRITE(FDI_RX_MISC(pipe),
3151 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3152
3153 reg = FDI_RX_CTL(pipe);
3154 temp = I915_READ(reg);
3155 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3156 temp |= FDI_COMPOSITE_SYNC;
3157 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3158
3159 POSTING_READ(reg);
3160 udelay(1); /* should be 0.5us */
3161
3162 for (i = 0; i < 4; i++) {
3163 reg = FDI_RX_IIR(pipe);
3164 temp = I915_READ(reg);
3165 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3166
3167 if (temp & FDI_RX_BIT_LOCK ||
3168 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3169 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3170 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3171 i);
3172 break;
3173 }
3174 udelay(1); /* should be 0.5us */
3175 }
3176 if (i == 4) {
3177 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3178 continue;
3179 }
3180
3181 /* Train 2 */
3182 reg = FDI_TX_CTL(pipe);
3183 temp = I915_READ(reg);
3184 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3185 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3186 I915_WRITE(reg, temp);
3187
3188 reg = FDI_RX_CTL(pipe);
3189 temp = I915_READ(reg);
3190 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3191 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3192 I915_WRITE(reg, temp);
3193
3194 POSTING_READ(reg);
3195 udelay(2); /* should be 1.5us */
3196
3197 for (i = 0; i < 4; i++) {
3198 reg = FDI_RX_IIR(pipe);
3199 temp = I915_READ(reg);
3200 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3201
3202 if (temp & FDI_RX_SYMBOL_LOCK ||
3203 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3204 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3205 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3206 i);
3207 goto train_done;
3208 }
3209 udelay(2); /* should be 1.5us */
3210 }
3211 if (i == 4)
3212 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3213 }
3214
3215 train_done:
3216 DRM_DEBUG_KMS("FDI train done.\n");
3217 }
3218
3219 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3220 {
3221 struct drm_device *dev = intel_crtc->base.dev;
3222 struct drm_i915_private *dev_priv = dev->dev_private;
3223 int pipe = intel_crtc->pipe;
3224 u32 reg, temp;
3225
3226
3227 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3228 reg = FDI_RX_CTL(pipe);
3229 temp = I915_READ(reg);
3230 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3231 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3232 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3233 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3234
3235 POSTING_READ(reg);
3236 udelay(200);
3237
3238 /* Switch from Rawclk to PCDclk */
3239 temp = I915_READ(reg);
3240 I915_WRITE(reg, temp | FDI_PCDCLK);
3241
3242 POSTING_READ(reg);
3243 udelay(200);
3244
3245 /* Enable CPU FDI TX PLL, always on for Ironlake */
3246 reg = FDI_TX_CTL(pipe);
3247 temp = I915_READ(reg);
3248 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3249 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3250
3251 POSTING_READ(reg);
3252 udelay(100);
3253 }
3254 }
3255
3256 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3257 {
3258 struct drm_device *dev = intel_crtc->base.dev;
3259 struct drm_i915_private *dev_priv = dev->dev_private;
3260 int pipe = intel_crtc->pipe;
3261 u32 reg, temp;
3262
3263 /* Switch from PCDclk to Rawclk */
3264 reg = FDI_RX_CTL(pipe);
3265 temp = I915_READ(reg);
3266 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3267
3268 /* Disable CPU FDI TX PLL */
3269 reg = FDI_TX_CTL(pipe);
3270 temp = I915_READ(reg);
3271 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3272
3273 POSTING_READ(reg);
3274 udelay(100);
3275
3276 reg = FDI_RX_CTL(pipe);
3277 temp = I915_READ(reg);
3278 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3279
3280 /* Wait for the clocks to turn off. */
3281 POSTING_READ(reg);
3282 udelay(100);
3283 }
3284
3285 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3286 {
3287 struct drm_device *dev = crtc->dev;
3288 struct drm_i915_private *dev_priv = dev->dev_private;
3289 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3290 int pipe = intel_crtc->pipe;
3291 u32 reg, temp;
3292
3293 /* disable CPU FDI tx and PCH FDI rx */
3294 reg = FDI_TX_CTL(pipe);
3295 temp = I915_READ(reg);
3296 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3297 POSTING_READ(reg);
3298
3299 reg = FDI_RX_CTL(pipe);
3300 temp = I915_READ(reg);
3301 temp &= ~(0x7 << 16);
3302 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3303 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3304
3305 POSTING_READ(reg);
3306 udelay(100);
3307
3308 /* Ironlake workaround, disable clock pointer after downing FDI */
3309 if (HAS_PCH_IBX(dev))
3310 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3311
3312 /* still set train pattern 1 */
3313 reg = FDI_TX_CTL(pipe);
3314 temp = I915_READ(reg);
3315 temp &= ~FDI_LINK_TRAIN_NONE;
3316 temp |= FDI_LINK_TRAIN_PATTERN_1;
3317 I915_WRITE(reg, temp);
3318
3319 reg = FDI_RX_CTL(pipe);
3320 temp = I915_READ(reg);
3321 if (HAS_PCH_CPT(dev)) {
3322 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3323 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3324 } else {
3325 temp &= ~FDI_LINK_TRAIN_NONE;
3326 temp |= FDI_LINK_TRAIN_PATTERN_1;
3327 }
3328 /* BPC in FDI rx is consistent with that in PIPECONF */
3329 temp &= ~(0x07 << 16);
3330 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3331 I915_WRITE(reg, temp);
3332
3333 POSTING_READ(reg);
3334 udelay(100);
3335 }
3336
3337 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3338 {
3339 struct intel_crtc *crtc;
3340
3341 /* Note that we don't need to be called with mode_config.lock here
3342 * as our list of CRTC objects is static for the lifetime of the
3343 * device and so cannot disappear as we iterate. Similarly, we can
3344 * happily treat the predicates as racy, atomic checks as userspace
3345 * cannot claim and pin a new fb without at least acquring the
3346 * struct_mutex and so serialising with us.
3347 */
3348 for_each_intel_crtc(dev, crtc) {
3349 if (atomic_read(&crtc->unpin_work_count) == 0)
3350 continue;
3351
3352 if (crtc->unpin_work)
3353 intel_wait_for_vblank(dev, crtc->pipe);
3354
3355 return true;
3356 }
3357
3358 return false;
3359 }
3360
3361 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3362 {
3363 struct drm_device *dev = crtc->dev;
3364 struct drm_i915_private *dev_priv = dev->dev_private;
3365
3366 if (crtc->primary->fb == NULL)
3367 return;
3368
3369 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3370
3371 WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3372 !intel_crtc_has_pending_flip(crtc),
3373 60*HZ) == 0);
3374
3375 mutex_lock(&dev->struct_mutex);
3376 intel_finish_fb(crtc->primary->fb);
3377 mutex_unlock(&dev->struct_mutex);
3378 }
3379
3380 /* Program iCLKIP clock to the desired frequency */
3381 static void lpt_program_iclkip(struct drm_crtc *crtc)
3382 {
3383 struct drm_device *dev = crtc->dev;
3384 struct drm_i915_private *dev_priv = dev->dev_private;
3385 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3386 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3387 u32 temp;
3388
3389 mutex_lock(&dev_priv->dpio_lock);
3390
3391 /* It is necessary to ungate the pixclk gate prior to programming
3392 * the divisors, and gate it back when it is done.
3393 */
3394 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3395
3396 /* Disable SSCCTL */
3397 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3398 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3399 SBI_SSCCTL_DISABLE,
3400 SBI_ICLK);
3401
3402 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3403 if (clock == 20000) {
3404 auxdiv = 1;
3405 divsel = 0x41;
3406 phaseinc = 0x20;
3407 } else {
3408 /* The iCLK virtual clock root frequency is in MHz,
3409 * but the adjusted_mode->crtc_clock in in KHz. To get the
3410 * divisors, it is necessary to divide one by another, so we
3411 * convert the virtual clock precision to KHz here for higher
3412 * precision.
3413 */
3414 u32 iclk_virtual_root_freq = 172800 * 1000;
3415 u32 iclk_pi_range = 64;
3416 u32 desired_divisor, msb_divisor_value, pi_value;
3417
3418 desired_divisor = (iclk_virtual_root_freq / clock);
3419 msb_divisor_value = desired_divisor / iclk_pi_range;
3420 pi_value = desired_divisor % iclk_pi_range;
3421
3422 auxdiv = 0;
3423 divsel = msb_divisor_value - 2;
3424 phaseinc = pi_value;
3425 }
3426
3427 /* This should not happen with any sane values */
3428 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3429 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3430 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3431 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3432
3433 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3434 clock,
3435 auxdiv,
3436 divsel,
3437 phasedir,
3438 phaseinc);
3439
3440 /* Program SSCDIVINTPHASE6 */
3441 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3442 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3443 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3444 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3445 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3446 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3447 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3448 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3449
3450 /* Program SSCAUXDIV */
3451 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3452 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3453 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3454 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3455
3456 /* Enable modulator and associated divider */
3457 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3458 temp &= ~SBI_SSCCTL_DISABLE;
3459 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3460
3461 /* Wait for initialization time */
3462 udelay(24);
3463
3464 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3465
3466 mutex_unlock(&dev_priv->dpio_lock);
3467 }
3468
3469 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3470 enum pipe pch_transcoder)
3471 {
3472 struct drm_device *dev = crtc->base.dev;
3473 struct drm_i915_private *dev_priv = dev->dev_private;
3474 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3475
3476 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3477 I915_READ(HTOTAL(cpu_transcoder)));
3478 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3479 I915_READ(HBLANK(cpu_transcoder)));
3480 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3481 I915_READ(HSYNC(cpu_transcoder)));
3482
3483 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3484 I915_READ(VTOTAL(cpu_transcoder)));
3485 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3486 I915_READ(VBLANK(cpu_transcoder)));
3487 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3488 I915_READ(VSYNC(cpu_transcoder)));
3489 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3490 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3491 }
3492
3493 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3494 {
3495 struct drm_i915_private *dev_priv = dev->dev_private;
3496 uint32_t temp;
3497
3498 temp = I915_READ(SOUTH_CHICKEN1);
3499 if (temp & FDI_BC_BIFURCATION_SELECT)
3500 return;
3501
3502 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3503 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3504
3505 temp |= FDI_BC_BIFURCATION_SELECT;
3506 DRM_DEBUG_KMS("enabling fdi C rx\n");
3507 I915_WRITE(SOUTH_CHICKEN1, temp);
3508 POSTING_READ(SOUTH_CHICKEN1);
3509 }
3510
3511 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3512 {
3513 struct drm_device *dev = intel_crtc->base.dev;
3514 struct drm_i915_private *dev_priv = dev->dev_private;
3515
3516 switch (intel_crtc->pipe) {
3517 case PIPE_A:
3518 break;
3519 case PIPE_B:
3520 if (intel_crtc->config.fdi_lanes > 2)
3521 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3522 else
3523 cpt_enable_fdi_bc_bifurcation(dev);
3524
3525 break;
3526 case PIPE_C:
3527 cpt_enable_fdi_bc_bifurcation(dev);
3528
3529 break;
3530 default:
3531 BUG();
3532 }
3533 }
3534
3535 /*
3536 * Enable PCH resources required for PCH ports:
3537 * - PCH PLLs
3538 * - FDI training & RX/TX
3539 * - update transcoder timings
3540 * - DP transcoding bits
3541 * - transcoder
3542 */
3543 static void ironlake_pch_enable(struct drm_crtc *crtc)
3544 {
3545 struct drm_device *dev = crtc->dev;
3546 struct drm_i915_private *dev_priv = dev->dev_private;
3547 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3548 int pipe = intel_crtc->pipe;
3549 u32 reg, temp;
3550
3551 assert_pch_transcoder_disabled(dev_priv, pipe);
3552
3553 if (IS_IVYBRIDGE(dev))
3554 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3555
3556 /* Write the TU size bits before fdi link training, so that error
3557 * detection works. */
3558 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3559 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3560
3561 /* For PCH output, training FDI link */
3562 dev_priv->display.fdi_link_train(crtc);
3563
3564 /* We need to program the right clock selection before writing the pixel
3565 * mutliplier into the DPLL. */
3566 if (HAS_PCH_CPT(dev)) {
3567 u32 sel;
3568
3569 temp = I915_READ(PCH_DPLL_SEL);
3570 temp |= TRANS_DPLL_ENABLE(pipe);
3571 sel = TRANS_DPLLB_SEL(pipe);
3572 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3573 temp |= sel;
3574 else
3575 temp &= ~sel;
3576 I915_WRITE(PCH_DPLL_SEL, temp);
3577 }
3578
3579 /* XXX: pch pll's can be enabled any time before we enable the PCH
3580 * transcoder, and we actually should do this to not upset any PCH
3581 * transcoder that already use the clock when we share it.
3582 *
3583 * Note that enable_shared_dpll tries to do the right thing, but
3584 * get_shared_dpll unconditionally resets the pll - we need that to have
3585 * the right LVDS enable sequence. */
3586 intel_enable_shared_dpll(intel_crtc);
3587
3588 /* set transcoder timing, panel must allow it */
3589 assert_panel_unlocked(dev_priv, pipe);
3590 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3591
3592 intel_fdi_normal_train(crtc);
3593
3594 /* For PCH DP, enable TRANS_DP_CTL */
3595 if (HAS_PCH_CPT(dev) &&
3596 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3597 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3598 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3599 reg = TRANS_DP_CTL(pipe);
3600 temp = I915_READ(reg);
3601 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3602 TRANS_DP_SYNC_MASK |
3603 TRANS_DP_BPC_MASK);
3604 temp |= (TRANS_DP_OUTPUT_ENABLE |
3605 TRANS_DP_ENH_FRAMING);
3606 temp |= bpc << 9; /* same format but at 11:9 */
3607
3608 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3609 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3610 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3611 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3612
3613 switch (intel_trans_dp_port_sel(crtc)) {
3614 case PCH_DP_B:
3615 temp |= TRANS_DP_PORT_SEL_B;
3616 break;
3617 case PCH_DP_C:
3618 temp |= TRANS_DP_PORT_SEL_C;
3619 break;
3620 case PCH_DP_D:
3621 temp |= TRANS_DP_PORT_SEL_D;
3622 break;
3623 default:
3624 BUG();
3625 }
3626
3627 I915_WRITE(reg, temp);
3628 }
3629
3630 ironlake_enable_pch_transcoder(dev_priv, pipe);
3631 }
3632
3633 static void lpt_pch_enable(struct drm_crtc *crtc)
3634 {
3635 struct drm_device *dev = crtc->dev;
3636 struct drm_i915_private *dev_priv = dev->dev_private;
3637 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3638 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3639
3640 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3641
3642 lpt_program_iclkip(crtc);
3643
3644 /* Set transcoder timing. */
3645 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3646
3647 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3648 }
3649
3650 void intel_put_shared_dpll(struct intel_crtc *crtc)
3651 {
3652 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3653
3654 if (pll == NULL)
3655 return;
3656
3657 if (pll->refcount == 0) {
3658 WARN(1, "bad %s refcount\n", pll->name);
3659 return;
3660 }
3661
3662 if (--pll->refcount == 0) {
3663 WARN_ON(pll->on);
3664 WARN_ON(pll->active);
3665 }
3666
3667 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3668 }
3669
3670 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3671 {
3672 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3673 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3674 enum intel_dpll_id i;
3675
3676 if (pll) {
3677 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3678 crtc->base.base.id, pll->name);
3679 intel_put_shared_dpll(crtc);
3680 }
3681
3682 if (HAS_PCH_IBX(dev_priv->dev)) {
3683 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3684 i = (enum intel_dpll_id) crtc->pipe;
3685 pll = &dev_priv->shared_dplls[i];
3686
3687 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3688 crtc->base.base.id, pll->name);
3689
3690 WARN_ON(pll->refcount);
3691
3692 goto found;
3693 }
3694
3695 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3696 pll = &dev_priv->shared_dplls[i];
3697
3698 /* Only want to check enabled timings first */
3699 if (pll->refcount == 0)
3700 continue;
3701
3702 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3703 sizeof(pll->hw_state)) == 0) {
3704 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3705 crtc->base.base.id,
3706 pll->name, pll->refcount, pll->active);
3707
3708 goto found;
3709 }
3710 }
3711
3712 /* Ok no matching timings, maybe there's a free one? */
3713 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3714 pll = &dev_priv->shared_dplls[i];
3715 if (pll->refcount == 0) {
3716 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3717 crtc->base.base.id, pll->name);
3718 goto found;
3719 }
3720 }
3721
3722 return NULL;
3723
3724 found:
3725 if (pll->refcount == 0)
3726 pll->hw_state = crtc->config.dpll_hw_state;
3727
3728 crtc->config.shared_dpll = i;
3729 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3730 pipe_name(crtc->pipe));
3731
3732 pll->refcount++;
3733
3734 return pll;
3735 }
3736
3737 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3738 {
3739 struct drm_i915_private *dev_priv = dev->dev_private;
3740 int dslreg = PIPEDSL(pipe);
3741 u32 temp;
3742
3743 temp = I915_READ(dslreg);
3744 udelay(500);
3745 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3746 if (wait_for(I915_READ(dslreg) != temp, 5))
3747 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3748 }
3749 }
3750
3751 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3752 {
3753 struct drm_device *dev = crtc->base.dev;
3754 struct drm_i915_private *dev_priv = dev->dev_private;
3755 int pipe = crtc->pipe;
3756
3757 if (crtc->config.pch_pfit.enabled) {
3758 /* Force use of hard-coded filter coefficients
3759 * as some pre-programmed values are broken,
3760 * e.g. x201.
3761 */
3762 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3763 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3764 PF_PIPE_SEL_IVB(pipe));
3765 else
3766 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3767 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3768 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3769 }
3770 }
3771
3772 static void intel_enable_planes(struct drm_crtc *crtc)
3773 {
3774 struct drm_device *dev = crtc->dev;
3775 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3776 struct drm_plane *plane;
3777 struct intel_plane *intel_plane;
3778
3779 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3780 intel_plane = to_intel_plane(plane);
3781 if (intel_plane->pipe == pipe)
3782 intel_plane_restore(&intel_plane->base);
3783 }
3784 }
3785
3786 static void intel_disable_planes(struct drm_crtc *crtc)
3787 {
3788 struct drm_device *dev = crtc->dev;
3789 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3790 struct drm_plane *plane;
3791 struct intel_plane *intel_plane;
3792
3793 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3794 intel_plane = to_intel_plane(plane);
3795 if (intel_plane->pipe == pipe)
3796 intel_plane_disable(&intel_plane->base);
3797 }
3798 }
3799
3800 void hsw_enable_ips(struct intel_crtc *crtc)
3801 {
3802 struct drm_device *dev = crtc->base.dev;
3803 struct drm_i915_private *dev_priv = dev->dev_private;
3804
3805 if (!crtc->config.ips_enabled)
3806 return;
3807
3808 /* We can only enable IPS after we enable a plane and wait for a vblank */
3809 intel_wait_for_vblank(dev, crtc->pipe);
3810
3811 assert_plane_enabled(dev_priv, crtc->plane);
3812 if (IS_BROADWELL(dev)) {
3813 mutex_lock(&dev_priv->rps.hw_lock);
3814 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3815 mutex_unlock(&dev_priv->rps.hw_lock);
3816 /* Quoting Art Runyan: "its not safe to expect any particular
3817 * value in IPS_CTL bit 31 after enabling IPS through the
3818 * mailbox." Moreover, the mailbox may return a bogus state,
3819 * so we need to just enable it and continue on.
3820 */
3821 } else {
3822 I915_WRITE(IPS_CTL, IPS_ENABLE);
3823 /* The bit only becomes 1 in the next vblank, so this wait here
3824 * is essentially intel_wait_for_vblank. If we don't have this
3825 * and don't wait for vblanks until the end of crtc_enable, then
3826 * the HW state readout code will complain that the expected
3827 * IPS_CTL value is not the one we read. */
3828 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3829 DRM_ERROR("Timed out waiting for IPS enable\n");
3830 }
3831 }
3832
3833 void hsw_disable_ips(struct intel_crtc *crtc)
3834 {
3835 struct drm_device *dev = crtc->base.dev;
3836 struct drm_i915_private *dev_priv = dev->dev_private;
3837
3838 if (!crtc->config.ips_enabled)
3839 return;
3840
3841 assert_plane_enabled(dev_priv, crtc->plane);
3842 if (IS_BROADWELL(dev)) {
3843 mutex_lock(&dev_priv->rps.hw_lock);
3844 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3845 mutex_unlock(&dev_priv->rps.hw_lock);
3846 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3847 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3848 DRM_ERROR("Timed out waiting for IPS disable\n");
3849 } else {
3850 I915_WRITE(IPS_CTL, 0);
3851 POSTING_READ(IPS_CTL);
3852 }
3853
3854 /* We need to wait for a vblank before we can disable the plane. */
3855 intel_wait_for_vblank(dev, crtc->pipe);
3856 }
3857
3858 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3859 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3860 {
3861 struct drm_device *dev = crtc->dev;
3862 struct drm_i915_private *dev_priv = dev->dev_private;
3863 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3864 enum pipe pipe = intel_crtc->pipe;
3865 int palreg = PALETTE(pipe);
3866 int i;
3867 bool reenable_ips = false;
3868
3869 /* The clocks have to be on to load the palette. */
3870 if (!crtc->enabled || !intel_crtc->active)
3871 return;
3872
3873 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3874 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3875 assert_dsi_pll_enabled(dev_priv);
3876 else
3877 assert_pll_enabled(dev_priv, pipe);
3878 }
3879
3880 /* use legacy palette for Ironlake */
3881 if (!HAS_GMCH_DISPLAY(dev))
3882 palreg = LGC_PALETTE(pipe);
3883
3884 /* Workaround : Do not read or write the pipe palette/gamma data while
3885 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3886 */
3887 if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3888 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3889 GAMMA_MODE_MODE_SPLIT)) {
3890 hsw_disable_ips(intel_crtc);
3891 reenable_ips = true;
3892 }
3893
3894 for (i = 0; i < 256; i++) {
3895 I915_WRITE(palreg + 4 * i,
3896 (intel_crtc->lut_r[i] << 16) |
3897 (intel_crtc->lut_g[i] << 8) |
3898 intel_crtc->lut_b[i]);
3899 }
3900
3901 if (reenable_ips)
3902 hsw_enable_ips(intel_crtc);
3903 }
3904
3905 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3906 {
3907 if (!enable && intel_crtc->overlay) {
3908 struct drm_device *dev = intel_crtc->base.dev;
3909 struct drm_i915_private *dev_priv = dev->dev_private;
3910
3911 mutex_lock(&dev->struct_mutex);
3912 dev_priv->mm.interruptible = false;
3913 (void) intel_overlay_switch_off(intel_crtc->overlay);
3914 dev_priv->mm.interruptible = true;
3915 mutex_unlock(&dev->struct_mutex);
3916 }
3917
3918 /* Let userspace switch the overlay on again. In most cases userspace
3919 * has to recompute where to put it anyway.
3920 */
3921 }
3922
3923 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
3924 {
3925 struct drm_device *dev = crtc->dev;
3926 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3927 int pipe = intel_crtc->pipe;
3928
3929 drm_vblank_on(dev, pipe);
3930
3931 intel_enable_primary_hw_plane(crtc->primary, crtc);
3932 intel_enable_planes(crtc);
3933 intel_crtc_update_cursor(crtc, true);
3934 intel_crtc_dpms_overlay(intel_crtc, true);
3935
3936 hsw_enable_ips(intel_crtc);
3937
3938 mutex_lock(&dev->struct_mutex);
3939 intel_update_fbc(dev);
3940 mutex_unlock(&dev->struct_mutex);
3941
3942 /*
3943 * FIXME: Once we grow proper nuclear flip support out of this we need
3944 * to compute the mask of flip planes precisely. For the time being
3945 * consider this a flip from a NULL plane.
3946 */
3947 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
3948 }
3949
3950 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
3951 {
3952 struct drm_device *dev = crtc->dev;
3953 struct drm_i915_private *dev_priv = dev->dev_private;
3954 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3955 int pipe = intel_crtc->pipe;
3956 int plane = intel_crtc->plane;
3957
3958 intel_crtc_wait_for_pending_flips(crtc);
3959
3960 if (dev_priv->fbc.plane == plane)
3961 intel_disable_fbc(dev);
3962
3963 hsw_disable_ips(intel_crtc);
3964
3965 intel_crtc_dpms_overlay(intel_crtc, false);
3966 intel_crtc_update_cursor(crtc, false);
3967 intel_disable_planes(crtc);
3968 intel_disable_primary_hw_plane(crtc->primary, crtc);
3969
3970 /*
3971 * FIXME: Once we grow proper nuclear flip support out of this we need
3972 * to compute the mask of flip planes precisely. For the time being
3973 * consider this a flip to a NULL plane.
3974 */
3975 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
3976
3977 drm_vblank_off(dev, pipe);
3978 }
3979
3980 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3981 {
3982 struct drm_device *dev = crtc->dev;
3983 struct drm_i915_private *dev_priv = dev->dev_private;
3984 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3985 struct intel_encoder *encoder;
3986 int pipe = intel_crtc->pipe;
3987
3988 WARN_ON(!crtc->enabled);
3989
3990 if (intel_crtc->active)
3991 return;
3992
3993 if (intel_crtc->config.has_pch_encoder)
3994 intel_prepare_shared_dpll(intel_crtc);
3995
3996 if (intel_crtc->config.has_dp_encoder)
3997 intel_dp_set_m_n(intel_crtc);
3998
3999 intel_set_pipe_timings(intel_crtc);
4000
4001 if (intel_crtc->config.has_pch_encoder) {
4002 intel_cpu_transcoder_set_m_n(intel_crtc,
4003 &intel_crtc->config.fdi_m_n, NULL);
4004 }
4005
4006 ironlake_set_pipeconf(crtc);
4007
4008 intel_crtc->active = true;
4009
4010 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4011 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4012
4013 for_each_encoder_on_crtc(dev, crtc, encoder)
4014 if (encoder->pre_enable)
4015 encoder->pre_enable(encoder);
4016
4017 if (intel_crtc->config.has_pch_encoder) {
4018 /* Note: FDI PLL enabling _must_ be done before we enable the
4019 * cpu pipes, hence this is separate from all the other fdi/pch
4020 * enabling. */
4021 ironlake_fdi_pll_enable(intel_crtc);
4022 } else {
4023 assert_fdi_tx_disabled(dev_priv, pipe);
4024 assert_fdi_rx_disabled(dev_priv, pipe);
4025 }
4026
4027 ironlake_pfit_enable(intel_crtc);
4028
4029 /*
4030 * On ILK+ LUT must be loaded before the pipe is running but with
4031 * clocks enabled
4032 */
4033 intel_crtc_load_lut(crtc);
4034
4035 intel_update_watermarks(crtc);
4036 intel_enable_pipe(intel_crtc);
4037
4038 if (intel_crtc->config.has_pch_encoder)
4039 ironlake_pch_enable(crtc);
4040
4041 for_each_encoder_on_crtc(dev, crtc, encoder)
4042 encoder->enable(encoder);
4043
4044 if (HAS_PCH_CPT(dev))
4045 cpt_verify_modeset(dev, intel_crtc->pipe);
4046
4047 intel_crtc_enable_planes(crtc);
4048 }
4049
4050 /* IPS only exists on ULT machines and is tied to pipe A. */
4051 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4052 {
4053 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4054 }
4055
4056 /*
4057 * This implements the workaround described in the "notes" section of the mode
4058 * set sequence documentation. When going from no pipes or single pipe to
4059 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4060 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4061 */
4062 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4063 {
4064 struct drm_device *dev = crtc->base.dev;
4065 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4066
4067 /* We want to get the other_active_crtc only if there's only 1 other
4068 * active crtc. */
4069 for_each_intel_crtc(dev, crtc_it) {
4070 if (!crtc_it->active || crtc_it == crtc)
4071 continue;
4072
4073 if (other_active_crtc)
4074 return;
4075
4076 other_active_crtc = crtc_it;
4077 }
4078 if (!other_active_crtc)
4079 return;
4080
4081 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4082 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4083 }
4084
4085 static void haswell_crtc_enable(struct drm_crtc *crtc)
4086 {
4087 struct drm_device *dev = crtc->dev;
4088 struct drm_i915_private *dev_priv = dev->dev_private;
4089 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4090 struct intel_encoder *encoder;
4091 int pipe = intel_crtc->pipe;
4092
4093 WARN_ON(!crtc->enabled);
4094
4095 if (intel_crtc->active)
4096 return;
4097
4098 if (intel_crtc_to_shared_dpll(intel_crtc))
4099 intel_enable_shared_dpll(intel_crtc);
4100
4101 if (intel_crtc->config.has_dp_encoder)
4102 intel_dp_set_m_n(intel_crtc);
4103
4104 intel_set_pipe_timings(intel_crtc);
4105
4106 if (intel_crtc->config.has_pch_encoder) {
4107 intel_cpu_transcoder_set_m_n(intel_crtc,
4108 &intel_crtc->config.fdi_m_n, NULL);
4109 }
4110
4111 haswell_set_pipeconf(crtc);
4112
4113 intel_set_pipe_csc(crtc);
4114
4115 intel_crtc->active = true;
4116
4117 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4118 for_each_encoder_on_crtc(dev, crtc, encoder)
4119 if (encoder->pre_enable)
4120 encoder->pre_enable(encoder);
4121
4122 if (intel_crtc->config.has_pch_encoder) {
4123 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4124 dev_priv->display.fdi_link_train(crtc);
4125 }
4126
4127 intel_ddi_enable_pipe_clock(intel_crtc);
4128
4129 ironlake_pfit_enable(intel_crtc);
4130
4131 /*
4132 * On ILK+ LUT must be loaded before the pipe is running but with
4133 * clocks enabled
4134 */
4135 intel_crtc_load_lut(crtc);
4136
4137 intel_ddi_set_pipe_settings(crtc);
4138 intel_ddi_enable_transcoder_func(crtc);
4139
4140 intel_update_watermarks(crtc);
4141 intel_enable_pipe(intel_crtc);
4142
4143 if (intel_crtc->config.has_pch_encoder)
4144 lpt_pch_enable(crtc);
4145
4146 if (intel_crtc->config.dp_encoder_is_mst)
4147 intel_ddi_set_vc_payload_alloc(crtc, true);
4148
4149 for_each_encoder_on_crtc(dev, crtc, encoder) {
4150 encoder->enable(encoder);
4151 intel_opregion_notify_encoder(encoder, true);
4152 }
4153
4154 /* If we change the relative order between pipe/planes enabling, we need
4155 * to change the workaround. */
4156 haswell_mode_set_planes_workaround(intel_crtc);
4157 intel_crtc_enable_planes(crtc);
4158 }
4159
4160 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4161 {
4162 struct drm_device *dev = crtc->base.dev;
4163 struct drm_i915_private *dev_priv = dev->dev_private;
4164 int pipe = crtc->pipe;
4165
4166 /* To avoid upsetting the power well on haswell only disable the pfit if
4167 * it's in use. The hw state code will make sure we get this right. */
4168 if (crtc->config.pch_pfit.enabled) {
4169 I915_WRITE(PF_CTL(pipe), 0);
4170 I915_WRITE(PF_WIN_POS(pipe), 0);
4171 I915_WRITE(PF_WIN_SZ(pipe), 0);
4172 }
4173 }
4174
4175 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4176 {
4177 struct drm_device *dev = crtc->dev;
4178 struct drm_i915_private *dev_priv = dev->dev_private;
4179 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4180 struct intel_encoder *encoder;
4181 int pipe = intel_crtc->pipe;
4182 u32 reg, temp;
4183
4184 if (!intel_crtc->active)
4185 return;
4186
4187 intel_crtc_disable_planes(crtc);
4188
4189 for_each_encoder_on_crtc(dev, crtc, encoder)
4190 encoder->disable(encoder);
4191
4192 if (intel_crtc->config.has_pch_encoder)
4193 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
4194
4195 intel_disable_pipe(dev_priv, pipe);
4196
4197 if (intel_crtc->config.dp_encoder_is_mst)
4198 intel_ddi_set_vc_payload_alloc(crtc, false);
4199
4200 ironlake_pfit_disable(intel_crtc);
4201
4202 for_each_encoder_on_crtc(dev, crtc, encoder)
4203 if (encoder->post_disable)
4204 encoder->post_disable(encoder);
4205
4206 if (intel_crtc->config.has_pch_encoder) {
4207 ironlake_fdi_disable(crtc);
4208
4209 ironlake_disable_pch_transcoder(dev_priv, pipe);
4210 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4211
4212 if (HAS_PCH_CPT(dev)) {
4213 /* disable TRANS_DP_CTL */
4214 reg = TRANS_DP_CTL(pipe);
4215 temp = I915_READ(reg);
4216 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4217 TRANS_DP_PORT_SEL_MASK);
4218 temp |= TRANS_DP_PORT_SEL_NONE;
4219 I915_WRITE(reg, temp);
4220
4221 /* disable DPLL_SEL */
4222 temp = I915_READ(PCH_DPLL_SEL);
4223 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4224 I915_WRITE(PCH_DPLL_SEL, temp);
4225 }
4226
4227 /* disable PCH DPLL */
4228 intel_disable_shared_dpll(intel_crtc);
4229
4230 ironlake_fdi_pll_disable(intel_crtc);
4231 }
4232
4233 intel_crtc->active = false;
4234 intel_update_watermarks(crtc);
4235
4236 mutex_lock(&dev->struct_mutex);
4237 intel_update_fbc(dev);
4238 mutex_unlock(&dev->struct_mutex);
4239 }
4240
4241 static void haswell_crtc_disable(struct drm_crtc *crtc)
4242 {
4243 struct drm_device *dev = crtc->dev;
4244 struct drm_i915_private *dev_priv = dev->dev_private;
4245 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4246 struct intel_encoder *encoder;
4247 int pipe = intel_crtc->pipe;
4248 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4249
4250 if (!intel_crtc->active)
4251 return;
4252
4253 intel_crtc_disable_planes(crtc);
4254
4255 for_each_encoder_on_crtc(dev, crtc, encoder) {
4256 intel_opregion_notify_encoder(encoder, false);
4257 encoder->disable(encoder);
4258 }
4259
4260 if (intel_crtc->config.has_pch_encoder)
4261 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4262 intel_disable_pipe(dev_priv, pipe);
4263
4264 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4265
4266 ironlake_pfit_disable(intel_crtc);
4267
4268 intel_ddi_disable_pipe_clock(intel_crtc);
4269
4270 if (intel_crtc->config.has_pch_encoder) {
4271 lpt_disable_pch_transcoder(dev_priv);
4272 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4273 intel_ddi_fdi_disable(crtc);
4274 }
4275
4276 for_each_encoder_on_crtc(dev, crtc, encoder)
4277 if (encoder->post_disable)
4278 encoder->post_disable(encoder);
4279
4280 intel_crtc->active = false;
4281 intel_update_watermarks(crtc);
4282
4283 mutex_lock(&dev->struct_mutex);
4284 intel_update_fbc(dev);
4285 mutex_unlock(&dev->struct_mutex);
4286
4287 if (intel_crtc_to_shared_dpll(intel_crtc))
4288 intel_disable_shared_dpll(intel_crtc);
4289 }
4290
4291 static void ironlake_crtc_off(struct drm_crtc *crtc)
4292 {
4293 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4294 intel_put_shared_dpll(intel_crtc);
4295 }
4296
4297
4298 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4299 {
4300 struct drm_device *dev = crtc->base.dev;
4301 struct drm_i915_private *dev_priv = dev->dev_private;
4302 struct intel_crtc_config *pipe_config = &crtc->config;
4303
4304 if (!crtc->config.gmch_pfit.control)
4305 return;
4306
4307 /*
4308 * The panel fitter should only be adjusted whilst the pipe is disabled,
4309 * according to register description and PRM.
4310 */
4311 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4312 assert_pipe_disabled(dev_priv, crtc->pipe);
4313
4314 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4315 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4316
4317 /* Border color in case we don't scale up to the full screen. Black by
4318 * default, change to something else for debugging. */
4319 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4320 }
4321
4322 static enum intel_display_power_domain port_to_power_domain(enum port port)
4323 {
4324 switch (port) {
4325 case PORT_A:
4326 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4327 case PORT_B:
4328 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4329 case PORT_C:
4330 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4331 case PORT_D:
4332 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4333 default:
4334 WARN_ON_ONCE(1);
4335 return POWER_DOMAIN_PORT_OTHER;
4336 }
4337 }
4338
4339 #define for_each_power_domain(domain, mask) \
4340 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4341 if ((1 << (domain)) & (mask))
4342
4343 enum intel_display_power_domain
4344 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4345 {
4346 struct drm_device *dev = intel_encoder->base.dev;
4347 struct intel_digital_port *intel_dig_port;
4348
4349 switch (intel_encoder->type) {
4350 case INTEL_OUTPUT_UNKNOWN:
4351 /* Only DDI platforms should ever use this output type */
4352 WARN_ON_ONCE(!HAS_DDI(dev));
4353 case INTEL_OUTPUT_DISPLAYPORT:
4354 case INTEL_OUTPUT_HDMI:
4355 case INTEL_OUTPUT_EDP:
4356 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4357 return port_to_power_domain(intel_dig_port->port);
4358 case INTEL_OUTPUT_DP_MST:
4359 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4360 return port_to_power_domain(intel_dig_port->port);
4361 case INTEL_OUTPUT_ANALOG:
4362 return POWER_DOMAIN_PORT_CRT;
4363 case INTEL_OUTPUT_DSI:
4364 return POWER_DOMAIN_PORT_DSI;
4365 default:
4366 return POWER_DOMAIN_PORT_OTHER;
4367 }
4368 }
4369
4370 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4371 {
4372 struct drm_device *dev = crtc->dev;
4373 struct intel_encoder *intel_encoder;
4374 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4375 enum pipe pipe = intel_crtc->pipe;
4376 unsigned long mask;
4377 enum transcoder transcoder;
4378
4379 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4380
4381 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4382 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4383 if (intel_crtc->config.pch_pfit.enabled ||
4384 intel_crtc->config.pch_pfit.force_thru)
4385 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4386
4387 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4388 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4389
4390 return mask;
4391 }
4392
4393 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4394 bool enable)
4395 {
4396 if (dev_priv->power_domains.init_power_on == enable)
4397 return;
4398
4399 if (enable)
4400 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4401 else
4402 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4403
4404 dev_priv->power_domains.init_power_on = enable;
4405 }
4406
4407 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4408 {
4409 struct drm_i915_private *dev_priv = dev->dev_private;
4410 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4411 struct intel_crtc *crtc;
4412
4413 /*
4414 * First get all needed power domains, then put all unneeded, to avoid
4415 * any unnecessary toggling of the power wells.
4416 */
4417 for_each_intel_crtc(dev, crtc) {
4418 enum intel_display_power_domain domain;
4419
4420 if (!crtc->base.enabled)
4421 continue;
4422
4423 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4424
4425 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4426 intel_display_power_get(dev_priv, domain);
4427 }
4428
4429 for_each_intel_crtc(dev, crtc) {
4430 enum intel_display_power_domain domain;
4431
4432 for_each_power_domain(domain, crtc->enabled_power_domains)
4433 intel_display_power_put(dev_priv, domain);
4434
4435 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4436 }
4437
4438 intel_display_set_init_power(dev_priv, false);
4439 }
4440
4441 /* returns HPLL frequency in kHz */
4442 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4443 {
4444 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4445
4446 /* Obtain SKU information */
4447 mutex_lock(&dev_priv->dpio_lock);
4448 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4449 CCK_FUSE_HPLL_FREQ_MASK;
4450 mutex_unlock(&dev_priv->dpio_lock);
4451
4452 return vco_freq[hpll_freq] * 1000;
4453 }
4454
4455 static void vlv_update_cdclk(struct drm_device *dev)
4456 {
4457 struct drm_i915_private *dev_priv = dev->dev_private;
4458
4459 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4460 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz",
4461 dev_priv->vlv_cdclk_freq);
4462
4463 /*
4464 * Program the gmbus_freq based on the cdclk frequency.
4465 * BSpec erroneously claims we should aim for 4MHz, but
4466 * in fact 1MHz is the correct frequency.
4467 */
4468 I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq);
4469 }
4470
4471 /* Adjust CDclk dividers to allow high res or save power if possible */
4472 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4473 {
4474 struct drm_i915_private *dev_priv = dev->dev_private;
4475 u32 val, cmd;
4476
4477 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4478
4479 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4480 cmd = 2;
4481 else if (cdclk == 266667)
4482 cmd = 1;
4483 else
4484 cmd = 0;
4485
4486 mutex_lock(&dev_priv->rps.hw_lock);
4487 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4488 val &= ~DSPFREQGUAR_MASK;
4489 val |= (cmd << DSPFREQGUAR_SHIFT);
4490 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4491 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4492 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4493 50)) {
4494 DRM_ERROR("timed out waiting for CDclk change\n");
4495 }
4496 mutex_unlock(&dev_priv->rps.hw_lock);
4497
4498 if (cdclk == 400000) {
4499 u32 divider, vco;
4500
4501 vco = valleyview_get_vco(dev_priv);
4502 divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1;
4503
4504 mutex_lock(&dev_priv->dpio_lock);
4505 /* adjust cdclk divider */
4506 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4507 val &= ~DISPLAY_FREQUENCY_VALUES;
4508 val |= divider;
4509 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4510
4511 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4512 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4513 50))
4514 DRM_ERROR("timed out waiting for CDclk change\n");
4515 mutex_unlock(&dev_priv->dpio_lock);
4516 }
4517
4518 mutex_lock(&dev_priv->dpio_lock);
4519 /* adjust self-refresh exit latency value */
4520 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4521 val &= ~0x7f;
4522
4523 /*
4524 * For high bandwidth configs, we set a higher latency in the bunit
4525 * so that the core display fetch happens in time to avoid underruns.
4526 */
4527 if (cdclk == 400000)
4528 val |= 4500 / 250; /* 4.5 usec */
4529 else
4530 val |= 3000 / 250; /* 3.0 usec */
4531 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4532 mutex_unlock(&dev_priv->dpio_lock);
4533
4534 vlv_update_cdclk(dev);
4535 }
4536
4537 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4538 {
4539 struct drm_i915_private *dev_priv = dev->dev_private;
4540 u32 val, cmd;
4541
4542 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4543
4544 switch (cdclk) {
4545 case 400000:
4546 cmd = 3;
4547 break;
4548 case 333333:
4549 case 320000:
4550 cmd = 2;
4551 break;
4552 case 266667:
4553 cmd = 1;
4554 break;
4555 case 200000:
4556 cmd = 0;
4557 break;
4558 default:
4559 WARN_ON(1);
4560 return;
4561 }
4562
4563 mutex_lock(&dev_priv->rps.hw_lock);
4564 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4565 val &= ~DSPFREQGUAR_MASK_CHV;
4566 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4567 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4568 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4569 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4570 50)) {
4571 DRM_ERROR("timed out waiting for CDclk change\n");
4572 }
4573 mutex_unlock(&dev_priv->rps.hw_lock);
4574
4575 vlv_update_cdclk(dev);
4576 }
4577
4578 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4579 int max_pixclk)
4580 {
4581 int vco = valleyview_get_vco(dev_priv);
4582 int freq_320 = (vco << 1) % 320000 != 0 ? 333333 : 320000;
4583
4584 /* FIXME: Punit isn't quite ready yet */
4585 if (IS_CHERRYVIEW(dev_priv->dev))
4586 return 400000;
4587
4588 /*
4589 * Really only a few cases to deal with, as only 4 CDclks are supported:
4590 * 200MHz
4591 * 267MHz
4592 * 320/333MHz (depends on HPLL freq)
4593 * 400MHz
4594 * So we check to see whether we're above 90% of the lower bin and
4595 * adjust if needed.
4596 *
4597 * We seem to get an unstable or solid color picture at 200MHz.
4598 * Not sure what's wrong. For now use 200MHz only when all pipes
4599 * are off.
4600 */
4601 if (max_pixclk > freq_320*9/10)
4602 return 400000;
4603 else if (max_pixclk > 266667*9/10)
4604 return freq_320;
4605 else if (max_pixclk > 0)
4606 return 266667;
4607 else
4608 return 200000;
4609 }
4610
4611 /* compute the max pixel clock for new configuration */
4612 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4613 {
4614 struct drm_device *dev = dev_priv->dev;
4615 struct intel_crtc *intel_crtc;
4616 int max_pixclk = 0;
4617
4618 for_each_intel_crtc(dev, intel_crtc) {
4619 if (intel_crtc->new_enabled)
4620 max_pixclk = max(max_pixclk,
4621 intel_crtc->new_config->adjusted_mode.crtc_clock);
4622 }
4623
4624 return max_pixclk;
4625 }
4626
4627 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4628 unsigned *prepare_pipes)
4629 {
4630 struct drm_i915_private *dev_priv = dev->dev_private;
4631 struct intel_crtc *intel_crtc;
4632 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4633
4634 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4635 dev_priv->vlv_cdclk_freq)
4636 return;
4637
4638 /* disable/enable all currently active pipes while we change cdclk */
4639 for_each_intel_crtc(dev, intel_crtc)
4640 if (intel_crtc->base.enabled)
4641 *prepare_pipes |= (1 << intel_crtc->pipe);
4642 }
4643
4644 static void valleyview_modeset_global_resources(struct drm_device *dev)
4645 {
4646 struct drm_i915_private *dev_priv = dev->dev_private;
4647 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4648 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4649
4650 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
4651 if (IS_CHERRYVIEW(dev))
4652 cherryview_set_cdclk(dev, req_cdclk);
4653 else
4654 valleyview_set_cdclk(dev, req_cdclk);
4655 }
4656
4657 modeset_update_crtc_power_domains(dev);
4658 }
4659
4660 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4661 {
4662 struct drm_device *dev = crtc->dev;
4663 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4664 struct intel_encoder *encoder;
4665 int pipe = intel_crtc->pipe;
4666 bool is_dsi;
4667
4668 WARN_ON(!crtc->enabled);
4669
4670 if (intel_crtc->active)
4671 return;
4672
4673 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4674
4675 if (!is_dsi) {
4676 if (IS_CHERRYVIEW(dev))
4677 chv_prepare_pll(intel_crtc);
4678 else
4679 vlv_prepare_pll(intel_crtc);
4680 }
4681
4682 if (intel_crtc->config.has_dp_encoder)
4683 intel_dp_set_m_n(intel_crtc);
4684
4685 intel_set_pipe_timings(intel_crtc);
4686
4687 i9xx_set_pipeconf(intel_crtc);
4688
4689 intel_crtc->active = true;
4690
4691 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4692
4693 for_each_encoder_on_crtc(dev, crtc, encoder)
4694 if (encoder->pre_pll_enable)
4695 encoder->pre_pll_enable(encoder);
4696
4697 if (!is_dsi) {
4698 if (IS_CHERRYVIEW(dev))
4699 chv_enable_pll(intel_crtc);
4700 else
4701 vlv_enable_pll(intel_crtc);
4702 }
4703
4704 for_each_encoder_on_crtc(dev, crtc, encoder)
4705 if (encoder->pre_enable)
4706 encoder->pre_enable(encoder);
4707
4708 i9xx_pfit_enable(intel_crtc);
4709
4710 intel_crtc_load_lut(crtc);
4711
4712 intel_update_watermarks(crtc);
4713 intel_enable_pipe(intel_crtc);
4714
4715 for_each_encoder_on_crtc(dev, crtc, encoder)
4716 encoder->enable(encoder);
4717
4718 intel_crtc_enable_planes(crtc);
4719
4720 /* Underruns don't raise interrupts, so check manually. */
4721 i9xx_check_fifo_underruns(dev);
4722 }
4723
4724 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4725 {
4726 struct drm_device *dev = crtc->base.dev;
4727 struct drm_i915_private *dev_priv = dev->dev_private;
4728
4729 I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4730 I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4731 }
4732
4733 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4734 {
4735 struct drm_device *dev = crtc->dev;
4736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4737 struct intel_encoder *encoder;
4738 int pipe = intel_crtc->pipe;
4739
4740 WARN_ON(!crtc->enabled);
4741
4742 if (intel_crtc->active)
4743 return;
4744
4745 i9xx_set_pll_dividers(intel_crtc);
4746
4747 if (intel_crtc->config.has_dp_encoder)
4748 intel_dp_set_m_n(intel_crtc);
4749
4750 intel_set_pipe_timings(intel_crtc);
4751
4752 i9xx_set_pipeconf(intel_crtc);
4753
4754 intel_crtc->active = true;
4755
4756 if (!IS_GEN2(dev))
4757 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4758
4759 for_each_encoder_on_crtc(dev, crtc, encoder)
4760 if (encoder->pre_enable)
4761 encoder->pre_enable(encoder);
4762
4763 i9xx_enable_pll(intel_crtc);
4764
4765 i9xx_pfit_enable(intel_crtc);
4766
4767 intel_crtc_load_lut(crtc);
4768
4769 intel_update_watermarks(crtc);
4770 intel_enable_pipe(intel_crtc);
4771
4772 for_each_encoder_on_crtc(dev, crtc, encoder)
4773 encoder->enable(encoder);
4774
4775 intel_crtc_enable_planes(crtc);
4776
4777 /*
4778 * Gen2 reports pipe underruns whenever all planes are disabled.
4779 * So don't enable underrun reporting before at least some planes
4780 * are enabled.
4781 * FIXME: Need to fix the logic to work when we turn off all planes
4782 * but leave the pipe running.
4783 */
4784 if (IS_GEN2(dev))
4785 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4786
4787 /* Underruns don't raise interrupts, so check manually. */
4788 i9xx_check_fifo_underruns(dev);
4789 }
4790
4791 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4792 {
4793 struct drm_device *dev = crtc->base.dev;
4794 struct drm_i915_private *dev_priv = dev->dev_private;
4795
4796 if (!crtc->config.gmch_pfit.control)
4797 return;
4798
4799 assert_pipe_disabled(dev_priv, crtc->pipe);
4800
4801 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4802 I915_READ(PFIT_CONTROL));
4803 I915_WRITE(PFIT_CONTROL, 0);
4804 }
4805
4806 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4807 {
4808 struct drm_device *dev = crtc->dev;
4809 struct drm_i915_private *dev_priv = dev->dev_private;
4810 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4811 struct intel_encoder *encoder;
4812 int pipe = intel_crtc->pipe;
4813
4814 if (!intel_crtc->active)
4815 return;
4816
4817 /*
4818 * Gen2 reports pipe underruns whenever all planes are disabled.
4819 * So diasble underrun reporting before all the planes get disabled.
4820 * FIXME: Need to fix the logic to work when we turn off all planes
4821 * but leave the pipe running.
4822 */
4823 if (IS_GEN2(dev))
4824 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4825
4826 /*
4827 * Vblank time updates from the shadow to live plane control register
4828 * are blocked if the memory self-refresh mode is active at that
4829 * moment. So to make sure the plane gets truly disabled, disable
4830 * first the self-refresh mode. The self-refresh enable bit in turn
4831 * will be checked/applied by the HW only at the next frame start
4832 * event which is after the vblank start event, so we need to have a
4833 * wait-for-vblank between disabling the plane and the pipe.
4834 */
4835 intel_set_memory_cxsr(dev_priv, false);
4836 intel_crtc_disable_planes(crtc);
4837
4838 for_each_encoder_on_crtc(dev, crtc, encoder)
4839 encoder->disable(encoder);
4840
4841 /*
4842 * On gen2 planes are double buffered but the pipe isn't, so we must
4843 * wait for planes to fully turn off before disabling the pipe.
4844 * We also need to wait on all gmch platforms because of the
4845 * self-refresh mode constraint explained above.
4846 */
4847 intel_wait_for_vblank(dev, pipe);
4848
4849 intel_disable_pipe(dev_priv, pipe);
4850
4851 i9xx_pfit_disable(intel_crtc);
4852
4853 for_each_encoder_on_crtc(dev, crtc, encoder)
4854 if (encoder->post_disable)
4855 encoder->post_disable(encoder);
4856
4857 if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
4858 if (IS_CHERRYVIEW(dev))
4859 chv_disable_pll(dev_priv, pipe);
4860 else if (IS_VALLEYVIEW(dev))
4861 vlv_disable_pll(dev_priv, pipe);
4862 else
4863 i9xx_disable_pll(dev_priv, pipe);
4864 }
4865
4866 if (!IS_GEN2(dev))
4867 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4868
4869 intel_crtc->active = false;
4870 intel_update_watermarks(crtc);
4871
4872 mutex_lock(&dev->struct_mutex);
4873 intel_update_fbc(dev);
4874 mutex_unlock(&dev->struct_mutex);
4875 }
4876
4877 static void i9xx_crtc_off(struct drm_crtc *crtc)
4878 {
4879 }
4880
4881 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4882 bool enabled)
4883 {
4884 struct drm_device *dev = crtc->dev;
4885 struct drm_i915_master_private *master_priv;
4886 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4887 int pipe = intel_crtc->pipe;
4888
4889 if (!dev->primary->master)
4890 return;
4891
4892 master_priv = dev->primary->master->driver_priv;
4893 if (!master_priv->sarea_priv)
4894 return;
4895
4896 switch (pipe) {
4897 case 0:
4898 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4899 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4900 break;
4901 case 1:
4902 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4903 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4904 break;
4905 default:
4906 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4907 break;
4908 }
4909 }
4910
4911 /* Master function to enable/disable CRTC and corresponding power wells */
4912 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
4913 {
4914 struct drm_device *dev = crtc->dev;
4915 struct drm_i915_private *dev_priv = dev->dev_private;
4916 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4917 enum intel_display_power_domain domain;
4918 unsigned long domains;
4919
4920 if (enable) {
4921 if (!intel_crtc->active) {
4922 domains = get_crtc_power_domains(crtc);
4923 for_each_power_domain(domain, domains)
4924 intel_display_power_get(dev_priv, domain);
4925 intel_crtc->enabled_power_domains = domains;
4926
4927 dev_priv->display.crtc_enable(crtc);
4928 }
4929 } else {
4930 if (intel_crtc->active) {
4931 dev_priv->display.crtc_disable(crtc);
4932
4933 domains = intel_crtc->enabled_power_domains;
4934 for_each_power_domain(domain, domains)
4935 intel_display_power_put(dev_priv, domain);
4936 intel_crtc->enabled_power_domains = 0;
4937 }
4938 }
4939 }
4940
4941 /**
4942 * Sets the power management mode of the pipe and plane.
4943 */
4944 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4945 {
4946 struct drm_device *dev = crtc->dev;
4947 struct intel_encoder *intel_encoder;
4948 bool enable = false;
4949
4950 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4951 enable |= intel_encoder->connectors_active;
4952
4953 intel_crtc_control(crtc, enable);
4954
4955 intel_crtc_update_sarea(crtc, enable);
4956 }
4957
4958 static void intel_crtc_disable(struct drm_crtc *crtc)
4959 {
4960 struct drm_device *dev = crtc->dev;
4961 struct drm_connector *connector;
4962 struct drm_i915_private *dev_priv = dev->dev_private;
4963 struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
4964 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4965
4966 /* crtc should still be enabled when we disable it. */
4967 WARN_ON(!crtc->enabled);
4968
4969 dev_priv->display.crtc_disable(crtc);
4970 intel_crtc_update_sarea(crtc, false);
4971 dev_priv->display.off(crtc);
4972
4973 if (crtc->primary->fb) {
4974 mutex_lock(&dev->struct_mutex);
4975 intel_unpin_fb_obj(old_obj);
4976 i915_gem_track_fb(old_obj, NULL,
4977 INTEL_FRONTBUFFER_PRIMARY(pipe));
4978 mutex_unlock(&dev->struct_mutex);
4979 crtc->primary->fb = NULL;
4980 }
4981
4982 /* Update computed state. */
4983 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4984 if (!connector->encoder || !connector->encoder->crtc)
4985 continue;
4986
4987 if (connector->encoder->crtc != crtc)
4988 continue;
4989
4990 connector->dpms = DRM_MODE_DPMS_OFF;
4991 to_intel_encoder(connector->encoder)->connectors_active = false;
4992 }
4993 }
4994
4995 void intel_encoder_destroy(struct drm_encoder *encoder)
4996 {
4997 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4998
4999 drm_encoder_cleanup(encoder);
5000 kfree(intel_encoder);
5001 }
5002
5003 /* Simple dpms helper for encoders with just one connector, no cloning and only
5004 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5005 * state of the entire output pipe. */
5006 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5007 {
5008 if (mode == DRM_MODE_DPMS_ON) {
5009 encoder->connectors_active = true;
5010
5011 intel_crtc_update_dpms(encoder->base.crtc);
5012 } else {
5013 encoder->connectors_active = false;
5014
5015 intel_crtc_update_dpms(encoder->base.crtc);
5016 }
5017 }
5018
5019 /* Cross check the actual hw state with our own modeset state tracking (and it's
5020 * internal consistency). */
5021 static void intel_connector_check_state(struct intel_connector *connector)
5022 {
5023 if (connector->get_hw_state(connector)) {
5024 struct intel_encoder *encoder = connector->encoder;
5025 struct drm_crtc *crtc;
5026 bool encoder_enabled;
5027 enum pipe pipe;
5028
5029 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5030 connector->base.base.id,
5031 connector->base.name);
5032
5033 /* there is no real hw state for MST connectors */
5034 if (connector->mst_port)
5035 return;
5036
5037 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5038 "wrong connector dpms state\n");
5039 WARN(connector->base.encoder != &encoder->base,
5040 "active connector not linked to encoder\n");
5041
5042 if (encoder) {
5043 WARN(!encoder->connectors_active,
5044 "encoder->connectors_active not set\n");
5045
5046 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5047 WARN(!encoder_enabled, "encoder not enabled\n");
5048 if (WARN_ON(!encoder->base.crtc))
5049 return;
5050
5051 crtc = encoder->base.crtc;
5052
5053 WARN(!crtc->enabled, "crtc not enabled\n");
5054 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5055 WARN(pipe != to_intel_crtc(crtc)->pipe,
5056 "encoder active on the wrong pipe\n");
5057 }
5058 }
5059 }
5060
5061 /* Even simpler default implementation, if there's really no special case to
5062 * consider. */
5063 void intel_connector_dpms(struct drm_connector *connector, int mode)
5064 {
5065 /* All the simple cases only support two dpms states. */
5066 if (mode != DRM_MODE_DPMS_ON)
5067 mode = DRM_MODE_DPMS_OFF;
5068
5069 if (mode == connector->dpms)
5070 return;
5071
5072 connector->dpms = mode;
5073
5074 /* Only need to change hw state when actually enabled */
5075 if (connector->encoder)
5076 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5077
5078 intel_modeset_check_state(connector->dev);
5079 }
5080
5081 /* Simple connector->get_hw_state implementation for encoders that support only
5082 * one connector and no cloning and hence the encoder state determines the state
5083 * of the connector. */
5084 bool intel_connector_get_hw_state(struct intel_connector *connector)
5085 {
5086 enum pipe pipe = 0;
5087 struct intel_encoder *encoder = connector->encoder;
5088
5089 return encoder->get_hw_state(encoder, &pipe);
5090 }
5091
5092 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5093 struct intel_crtc_config *pipe_config)
5094 {
5095 struct drm_i915_private *dev_priv = dev->dev_private;
5096 struct intel_crtc *pipe_B_crtc =
5097 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5098
5099 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5100 pipe_name(pipe), pipe_config->fdi_lanes);
5101 if (pipe_config->fdi_lanes > 4) {
5102 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5103 pipe_name(pipe), pipe_config->fdi_lanes);
5104 return false;
5105 }
5106
5107 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5108 if (pipe_config->fdi_lanes > 2) {
5109 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5110 pipe_config->fdi_lanes);
5111 return false;
5112 } else {
5113 return true;
5114 }
5115 }
5116
5117 if (INTEL_INFO(dev)->num_pipes == 2)
5118 return true;
5119
5120 /* Ivybridge 3 pipe is really complicated */
5121 switch (pipe) {
5122 case PIPE_A:
5123 return true;
5124 case PIPE_B:
5125 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5126 pipe_config->fdi_lanes > 2) {
5127 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5128 pipe_name(pipe), pipe_config->fdi_lanes);
5129 return false;
5130 }
5131 return true;
5132 case PIPE_C:
5133 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5134 pipe_B_crtc->config.fdi_lanes <= 2) {
5135 if (pipe_config->fdi_lanes > 2) {
5136 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5137 pipe_name(pipe), pipe_config->fdi_lanes);
5138 return false;
5139 }
5140 } else {
5141 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5142 return false;
5143 }
5144 return true;
5145 default:
5146 BUG();
5147 }
5148 }
5149
5150 #define RETRY 1
5151 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5152 struct intel_crtc_config *pipe_config)
5153 {
5154 struct drm_device *dev = intel_crtc->base.dev;
5155 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5156 int lane, link_bw, fdi_dotclock;
5157 bool setup_ok, needs_recompute = false;
5158
5159 retry:
5160 /* FDI is a binary signal running at ~2.7GHz, encoding
5161 * each output octet as 10 bits. The actual frequency
5162 * is stored as a divider into a 100MHz clock, and the
5163 * mode pixel clock is stored in units of 1KHz.
5164 * Hence the bw of each lane in terms of the mode signal
5165 * is:
5166 */
5167 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5168
5169 fdi_dotclock = adjusted_mode->crtc_clock;
5170
5171 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5172 pipe_config->pipe_bpp);
5173
5174 pipe_config->fdi_lanes = lane;
5175
5176 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5177 link_bw, &pipe_config->fdi_m_n);
5178
5179 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5180 intel_crtc->pipe, pipe_config);
5181 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5182 pipe_config->pipe_bpp -= 2*3;
5183 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5184 pipe_config->pipe_bpp);
5185 needs_recompute = true;
5186 pipe_config->bw_constrained = true;
5187
5188 goto retry;
5189 }
5190
5191 if (needs_recompute)
5192 return RETRY;
5193
5194 return setup_ok ? 0 : -EINVAL;
5195 }
5196
5197 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5198 struct intel_crtc_config *pipe_config)
5199 {
5200 pipe_config->ips_enabled = i915.enable_ips &&
5201 hsw_crtc_supports_ips(crtc) &&
5202 pipe_config->pipe_bpp <= 24;
5203 }
5204
5205 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5206 struct intel_crtc_config *pipe_config)
5207 {
5208 struct drm_device *dev = crtc->base.dev;
5209 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5210
5211 /* FIXME should check pixel clock limits on all platforms */
5212 if (INTEL_INFO(dev)->gen < 4) {
5213 struct drm_i915_private *dev_priv = dev->dev_private;
5214 int clock_limit =
5215 dev_priv->display.get_display_clock_speed(dev);
5216
5217 /*
5218 * Enable pixel doubling when the dot clock
5219 * is > 90% of the (display) core speed.
5220 *
5221 * GDG double wide on either pipe,
5222 * otherwise pipe A only.
5223 */
5224 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5225 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5226 clock_limit *= 2;
5227 pipe_config->double_wide = true;
5228 }
5229
5230 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5231 return -EINVAL;
5232 }
5233
5234 /*
5235 * Pipe horizontal size must be even in:
5236 * - DVO ganged mode
5237 * - LVDS dual channel mode
5238 * - Double wide pipe
5239 */
5240 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5241 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5242 pipe_config->pipe_src_w &= ~1;
5243
5244 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5245 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5246 */
5247 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5248 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5249 return -EINVAL;
5250
5251 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5252 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5253 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5254 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5255 * for lvds. */
5256 pipe_config->pipe_bpp = 8*3;
5257 }
5258
5259 if (HAS_IPS(dev))
5260 hsw_compute_ips_config(crtc, pipe_config);
5261
5262 /*
5263 * XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the
5264 * old clock survives for now.
5265 */
5266 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev) || HAS_DDI(dev))
5267 pipe_config->shared_dpll = crtc->config.shared_dpll;
5268
5269 if (pipe_config->has_pch_encoder)
5270 return ironlake_fdi_compute_config(crtc, pipe_config);
5271
5272 return 0;
5273 }
5274
5275 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5276 {
5277 struct drm_i915_private *dev_priv = dev->dev_private;
5278 int vco = valleyview_get_vco(dev_priv);
5279 u32 val;
5280 int divider;
5281
5282 /* FIXME: Punit isn't quite ready yet */
5283 if (IS_CHERRYVIEW(dev))
5284 return 400000;
5285
5286 mutex_lock(&dev_priv->dpio_lock);
5287 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5288 mutex_unlock(&dev_priv->dpio_lock);
5289
5290 divider = val & DISPLAY_FREQUENCY_VALUES;
5291
5292 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5293 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5294 "cdclk change in progress\n");
5295
5296 return DIV_ROUND_CLOSEST(vco << 1, divider + 1);
5297 }
5298
5299 static int i945_get_display_clock_speed(struct drm_device *dev)
5300 {
5301 return 400000;
5302 }
5303
5304 static int i915_get_display_clock_speed(struct drm_device *dev)
5305 {
5306 return 333000;
5307 }
5308
5309 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5310 {
5311 return 200000;
5312 }
5313
5314 static int pnv_get_display_clock_speed(struct drm_device *dev)
5315 {
5316 u16 gcfgc = 0;
5317
5318 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5319
5320 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5321 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5322 return 267000;
5323 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5324 return 333000;
5325 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5326 return 444000;
5327 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5328 return 200000;
5329 default:
5330 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5331 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5332 return 133000;
5333 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5334 return 167000;
5335 }
5336 }
5337
5338 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5339 {
5340 u16 gcfgc = 0;
5341
5342 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5343
5344 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5345 return 133000;
5346 else {
5347 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5348 case GC_DISPLAY_CLOCK_333_MHZ:
5349 return 333000;
5350 default:
5351 case GC_DISPLAY_CLOCK_190_200_MHZ:
5352 return 190000;
5353 }
5354 }
5355 }
5356
5357 static int i865_get_display_clock_speed(struct drm_device *dev)
5358 {
5359 return 266000;
5360 }
5361
5362 static int i855_get_display_clock_speed(struct drm_device *dev)
5363 {
5364 u16 hpllcc = 0;
5365 /* Assume that the hardware is in the high speed state. This
5366 * should be the default.
5367 */
5368 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5369 case GC_CLOCK_133_200:
5370 case GC_CLOCK_100_200:
5371 return 200000;
5372 case GC_CLOCK_166_250:
5373 return 250000;
5374 case GC_CLOCK_100_133:
5375 return 133000;
5376 }
5377
5378 /* Shouldn't happen */
5379 return 0;
5380 }
5381
5382 static int i830_get_display_clock_speed(struct drm_device *dev)
5383 {
5384 return 133000;
5385 }
5386
5387 static void
5388 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5389 {
5390 while (*num > DATA_LINK_M_N_MASK ||
5391 *den > DATA_LINK_M_N_MASK) {
5392 *num >>= 1;
5393 *den >>= 1;
5394 }
5395 }
5396
5397 static void compute_m_n(unsigned int m, unsigned int n,
5398 uint32_t *ret_m, uint32_t *ret_n)
5399 {
5400 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5401 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5402 intel_reduce_m_n_ratio(ret_m, ret_n);
5403 }
5404
5405 void
5406 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5407 int pixel_clock, int link_clock,
5408 struct intel_link_m_n *m_n)
5409 {
5410 m_n->tu = 64;
5411
5412 compute_m_n(bits_per_pixel * pixel_clock,
5413 link_clock * nlanes * 8,
5414 &m_n->gmch_m, &m_n->gmch_n);
5415
5416 compute_m_n(pixel_clock, link_clock,
5417 &m_n->link_m, &m_n->link_n);
5418 }
5419
5420 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5421 {
5422 if (i915.panel_use_ssc >= 0)
5423 return i915.panel_use_ssc != 0;
5424 return dev_priv->vbt.lvds_use_ssc
5425 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5426 }
5427
5428 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5429 {
5430 struct drm_device *dev = crtc->dev;
5431 struct drm_i915_private *dev_priv = dev->dev_private;
5432 int refclk;
5433
5434 if (IS_VALLEYVIEW(dev)) {
5435 refclk = 100000;
5436 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5437 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5438 refclk = dev_priv->vbt.lvds_ssc_freq;
5439 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5440 } else if (!IS_GEN2(dev)) {
5441 refclk = 96000;
5442 } else {
5443 refclk = 48000;
5444 }
5445
5446 return refclk;
5447 }
5448
5449 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5450 {
5451 return (1 << dpll->n) << 16 | dpll->m2;
5452 }
5453
5454 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5455 {
5456 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5457 }
5458
5459 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5460 intel_clock_t *reduced_clock)
5461 {
5462 struct drm_device *dev = crtc->base.dev;
5463 u32 fp, fp2 = 0;
5464
5465 if (IS_PINEVIEW(dev)) {
5466 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5467 if (reduced_clock)
5468 fp2 = pnv_dpll_compute_fp(reduced_clock);
5469 } else {
5470 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5471 if (reduced_clock)
5472 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5473 }
5474
5475 crtc->config.dpll_hw_state.fp0 = fp;
5476
5477 crtc->lowfreq_avail = false;
5478 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5479 reduced_clock && i915.powersave) {
5480 crtc->config.dpll_hw_state.fp1 = fp2;
5481 crtc->lowfreq_avail = true;
5482 } else {
5483 crtc->config.dpll_hw_state.fp1 = fp;
5484 }
5485 }
5486
5487 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5488 pipe)
5489 {
5490 u32 reg_val;
5491
5492 /*
5493 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5494 * and set it to a reasonable value instead.
5495 */
5496 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5497 reg_val &= 0xffffff00;
5498 reg_val |= 0x00000030;
5499 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5500
5501 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5502 reg_val &= 0x8cffffff;
5503 reg_val = 0x8c000000;
5504 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5505
5506 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5507 reg_val &= 0xffffff00;
5508 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5509
5510 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5511 reg_val &= 0x00ffffff;
5512 reg_val |= 0xb0000000;
5513 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5514 }
5515
5516 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5517 struct intel_link_m_n *m_n)
5518 {
5519 struct drm_device *dev = crtc->base.dev;
5520 struct drm_i915_private *dev_priv = dev->dev_private;
5521 int pipe = crtc->pipe;
5522
5523 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5524 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5525 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5526 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5527 }
5528
5529 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5530 struct intel_link_m_n *m_n,
5531 struct intel_link_m_n *m2_n2)
5532 {
5533 struct drm_device *dev = crtc->base.dev;
5534 struct drm_i915_private *dev_priv = dev->dev_private;
5535 int pipe = crtc->pipe;
5536 enum transcoder transcoder = crtc->config.cpu_transcoder;
5537
5538 if (INTEL_INFO(dev)->gen >= 5) {
5539 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5540 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5541 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5542 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5543 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5544 * for gen < 8) and if DRRS is supported (to make sure the
5545 * registers are not unnecessarily accessed).
5546 */
5547 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5548 crtc->config.has_drrs) {
5549 I915_WRITE(PIPE_DATA_M2(transcoder),
5550 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5551 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5552 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5553 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5554 }
5555 } else {
5556 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5557 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5558 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5559 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5560 }
5561 }
5562
5563 void intel_dp_set_m_n(struct intel_crtc *crtc)
5564 {
5565 if (crtc->config.has_pch_encoder)
5566 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5567 else
5568 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n,
5569 &crtc->config.dp_m2_n2);
5570 }
5571
5572 static void vlv_update_pll(struct intel_crtc *crtc)
5573 {
5574 u32 dpll, dpll_md;
5575
5576 /*
5577 * Enable DPIO clock input. We should never disable the reference
5578 * clock for pipe B, since VGA hotplug / manual detection depends
5579 * on it.
5580 */
5581 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5582 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5583 /* We should never disable this, set it here for state tracking */
5584 if (crtc->pipe == PIPE_B)
5585 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5586 dpll |= DPLL_VCO_ENABLE;
5587 crtc->config.dpll_hw_state.dpll = dpll;
5588
5589 dpll_md = (crtc->config.pixel_multiplier - 1)
5590 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5591 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5592 }
5593
5594 static void vlv_prepare_pll(struct intel_crtc *crtc)
5595 {
5596 struct drm_device *dev = crtc->base.dev;
5597 struct drm_i915_private *dev_priv = dev->dev_private;
5598 int pipe = crtc->pipe;
5599 u32 mdiv;
5600 u32 bestn, bestm1, bestm2, bestp1, bestp2;
5601 u32 coreclk, reg_val;
5602
5603 mutex_lock(&dev_priv->dpio_lock);
5604
5605 bestn = crtc->config.dpll.n;
5606 bestm1 = crtc->config.dpll.m1;
5607 bestm2 = crtc->config.dpll.m2;
5608 bestp1 = crtc->config.dpll.p1;
5609 bestp2 = crtc->config.dpll.p2;
5610
5611 /* See eDP HDMI DPIO driver vbios notes doc */
5612
5613 /* PLL B needs special handling */
5614 if (pipe == PIPE_B)
5615 vlv_pllb_recal_opamp(dev_priv, pipe);
5616
5617 /* Set up Tx target for periodic Rcomp update */
5618 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5619
5620 /* Disable target IRef on PLL */
5621 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5622 reg_val &= 0x00ffffff;
5623 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5624
5625 /* Disable fast lock */
5626 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5627
5628 /* Set idtafcrecal before PLL is enabled */
5629 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5630 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5631 mdiv |= ((bestn << DPIO_N_SHIFT));
5632 mdiv |= (1 << DPIO_K_SHIFT);
5633
5634 /*
5635 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5636 * but we don't support that).
5637 * Note: don't use the DAC post divider as it seems unstable.
5638 */
5639 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5640 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5641
5642 mdiv |= DPIO_ENABLE_CALIBRATION;
5643 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5644
5645 /* Set HBR and RBR LPF coefficients */
5646 if (crtc->config.port_clock == 162000 ||
5647 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5648 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5649 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5650 0x009f0003);
5651 else
5652 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5653 0x00d0000f);
5654
5655 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5656 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5657 /* Use SSC source */
5658 if (pipe == PIPE_A)
5659 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5660 0x0df40000);
5661 else
5662 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5663 0x0df70000);
5664 } else { /* HDMI or VGA */
5665 /* Use bend source */
5666 if (pipe == PIPE_A)
5667 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5668 0x0df70000);
5669 else
5670 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5671 0x0df40000);
5672 }
5673
5674 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5675 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5676 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5677 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5678 coreclk |= 0x01000000;
5679 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5680
5681 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5682 mutex_unlock(&dev_priv->dpio_lock);
5683 }
5684
5685 static void chv_update_pll(struct intel_crtc *crtc)
5686 {
5687 crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5688 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5689 DPLL_VCO_ENABLE;
5690 if (crtc->pipe != PIPE_A)
5691 crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5692
5693 crtc->config.dpll_hw_state.dpll_md =
5694 (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5695 }
5696
5697 static void chv_prepare_pll(struct intel_crtc *crtc)
5698 {
5699 struct drm_device *dev = crtc->base.dev;
5700 struct drm_i915_private *dev_priv = dev->dev_private;
5701 int pipe = crtc->pipe;
5702 int dpll_reg = DPLL(crtc->pipe);
5703 enum dpio_channel port = vlv_pipe_to_channel(pipe);
5704 u32 loopfilter, intcoeff;
5705 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5706 int refclk;
5707
5708 bestn = crtc->config.dpll.n;
5709 bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5710 bestm1 = crtc->config.dpll.m1;
5711 bestm2 = crtc->config.dpll.m2 >> 22;
5712 bestp1 = crtc->config.dpll.p1;
5713 bestp2 = crtc->config.dpll.p2;
5714
5715 /*
5716 * Enable Refclk and SSC
5717 */
5718 I915_WRITE(dpll_reg,
5719 crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5720
5721 mutex_lock(&dev_priv->dpio_lock);
5722
5723 /* p1 and p2 divider */
5724 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5725 5 << DPIO_CHV_S1_DIV_SHIFT |
5726 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5727 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5728 1 << DPIO_CHV_K_DIV_SHIFT);
5729
5730 /* Feedback post-divider - m2 */
5731 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5732
5733 /* Feedback refclk divider - n and m1 */
5734 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5735 DPIO_CHV_M1_DIV_BY_2 |
5736 1 << DPIO_CHV_N_DIV_SHIFT);
5737
5738 /* M2 fraction division */
5739 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5740
5741 /* M2 fraction division enable */
5742 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5743 DPIO_CHV_FRAC_DIV_EN |
5744 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5745
5746 /* Loop filter */
5747 refclk = i9xx_get_refclk(&crtc->base, 0);
5748 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5749 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5750 if (refclk == 100000)
5751 intcoeff = 11;
5752 else if (refclk == 38400)
5753 intcoeff = 10;
5754 else
5755 intcoeff = 9;
5756 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5757 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5758
5759 /* AFC Recal */
5760 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5761 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5762 DPIO_AFC_RECAL);
5763
5764 mutex_unlock(&dev_priv->dpio_lock);
5765 }
5766
5767 static void i9xx_update_pll(struct intel_crtc *crtc,
5768 intel_clock_t *reduced_clock,
5769 int num_connectors)
5770 {
5771 struct drm_device *dev = crtc->base.dev;
5772 struct drm_i915_private *dev_priv = dev->dev_private;
5773 u32 dpll;
5774 bool is_sdvo;
5775 struct dpll *clock = &crtc->config.dpll;
5776
5777 i9xx_update_pll_dividers(crtc, reduced_clock);
5778
5779 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5780 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5781
5782 dpll = DPLL_VGA_MODE_DIS;
5783
5784 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5785 dpll |= DPLLB_MODE_LVDS;
5786 else
5787 dpll |= DPLLB_MODE_DAC_SERIAL;
5788
5789 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5790 dpll |= (crtc->config.pixel_multiplier - 1)
5791 << SDVO_MULTIPLIER_SHIFT_HIRES;
5792 }
5793
5794 if (is_sdvo)
5795 dpll |= DPLL_SDVO_HIGH_SPEED;
5796
5797 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5798 dpll |= DPLL_SDVO_HIGH_SPEED;
5799
5800 /* compute bitmask from p1 value */
5801 if (IS_PINEVIEW(dev))
5802 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5803 else {
5804 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5805 if (IS_G4X(dev) && reduced_clock)
5806 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5807 }
5808 switch (clock->p2) {
5809 case 5:
5810 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5811 break;
5812 case 7:
5813 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5814 break;
5815 case 10:
5816 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5817 break;
5818 case 14:
5819 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5820 break;
5821 }
5822 if (INTEL_INFO(dev)->gen >= 4)
5823 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5824
5825 if (crtc->config.sdvo_tv_clock)
5826 dpll |= PLL_REF_INPUT_TVCLKINBC;
5827 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5828 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5829 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5830 else
5831 dpll |= PLL_REF_INPUT_DREFCLK;
5832
5833 dpll |= DPLL_VCO_ENABLE;
5834 crtc->config.dpll_hw_state.dpll = dpll;
5835
5836 if (INTEL_INFO(dev)->gen >= 4) {
5837 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5838 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5839 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5840 }
5841 }
5842
5843 static void i8xx_update_pll(struct intel_crtc *crtc,
5844 intel_clock_t *reduced_clock,
5845 int num_connectors)
5846 {
5847 struct drm_device *dev = crtc->base.dev;
5848 struct drm_i915_private *dev_priv = dev->dev_private;
5849 u32 dpll;
5850 struct dpll *clock = &crtc->config.dpll;
5851
5852 i9xx_update_pll_dividers(crtc, reduced_clock);
5853
5854 dpll = DPLL_VGA_MODE_DIS;
5855
5856 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5857 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5858 } else {
5859 if (clock->p1 == 2)
5860 dpll |= PLL_P1_DIVIDE_BY_TWO;
5861 else
5862 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5863 if (clock->p2 == 4)
5864 dpll |= PLL_P2_DIVIDE_BY_4;
5865 }
5866
5867 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5868 dpll |= DPLL_DVO_2X_MODE;
5869
5870 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5871 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5872 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5873 else
5874 dpll |= PLL_REF_INPUT_DREFCLK;
5875
5876 dpll |= DPLL_VCO_ENABLE;
5877 crtc->config.dpll_hw_state.dpll = dpll;
5878 }
5879
5880 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5881 {
5882 struct drm_device *dev = intel_crtc->base.dev;
5883 struct drm_i915_private *dev_priv = dev->dev_private;
5884 enum pipe pipe = intel_crtc->pipe;
5885 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5886 struct drm_display_mode *adjusted_mode =
5887 &intel_crtc->config.adjusted_mode;
5888 uint32_t crtc_vtotal, crtc_vblank_end;
5889 int vsyncshift = 0;
5890
5891 /* We need to be careful not to changed the adjusted mode, for otherwise
5892 * the hw state checker will get angry at the mismatch. */
5893 crtc_vtotal = adjusted_mode->crtc_vtotal;
5894 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5895
5896 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5897 /* the chip adds 2 halflines automatically */
5898 crtc_vtotal -= 1;
5899 crtc_vblank_end -= 1;
5900
5901 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5902 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5903 else
5904 vsyncshift = adjusted_mode->crtc_hsync_start -
5905 adjusted_mode->crtc_htotal / 2;
5906 if (vsyncshift < 0)
5907 vsyncshift += adjusted_mode->crtc_htotal;
5908 }
5909
5910 if (INTEL_INFO(dev)->gen > 3)
5911 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5912
5913 I915_WRITE(HTOTAL(cpu_transcoder),
5914 (adjusted_mode->crtc_hdisplay - 1) |
5915 ((adjusted_mode->crtc_htotal - 1) << 16));
5916 I915_WRITE(HBLANK(cpu_transcoder),
5917 (adjusted_mode->crtc_hblank_start - 1) |
5918 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5919 I915_WRITE(HSYNC(cpu_transcoder),
5920 (adjusted_mode->crtc_hsync_start - 1) |
5921 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5922
5923 I915_WRITE(VTOTAL(cpu_transcoder),
5924 (adjusted_mode->crtc_vdisplay - 1) |
5925 ((crtc_vtotal - 1) << 16));
5926 I915_WRITE(VBLANK(cpu_transcoder),
5927 (adjusted_mode->crtc_vblank_start - 1) |
5928 ((crtc_vblank_end - 1) << 16));
5929 I915_WRITE(VSYNC(cpu_transcoder),
5930 (adjusted_mode->crtc_vsync_start - 1) |
5931 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5932
5933 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5934 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5935 * documented on the DDI_FUNC_CTL register description, EDP Input Select
5936 * bits. */
5937 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5938 (pipe == PIPE_B || pipe == PIPE_C))
5939 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5940
5941 /* pipesrc controls the size that is scaled from, which should
5942 * always be the user's requested size.
5943 */
5944 I915_WRITE(PIPESRC(pipe),
5945 ((intel_crtc->config.pipe_src_w - 1) << 16) |
5946 (intel_crtc->config.pipe_src_h - 1));
5947 }
5948
5949 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5950 struct intel_crtc_config *pipe_config)
5951 {
5952 struct drm_device *dev = crtc->base.dev;
5953 struct drm_i915_private *dev_priv = dev->dev_private;
5954 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5955 uint32_t tmp;
5956
5957 tmp = I915_READ(HTOTAL(cpu_transcoder));
5958 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5959 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5960 tmp = I915_READ(HBLANK(cpu_transcoder));
5961 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5962 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5963 tmp = I915_READ(HSYNC(cpu_transcoder));
5964 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5965 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5966
5967 tmp = I915_READ(VTOTAL(cpu_transcoder));
5968 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5969 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5970 tmp = I915_READ(VBLANK(cpu_transcoder));
5971 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5972 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5973 tmp = I915_READ(VSYNC(cpu_transcoder));
5974 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5975 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5976
5977 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5978 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5979 pipe_config->adjusted_mode.crtc_vtotal += 1;
5980 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5981 }
5982
5983 tmp = I915_READ(PIPESRC(crtc->pipe));
5984 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5985 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5986
5987 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5988 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5989 }
5990
5991 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5992 struct intel_crtc_config *pipe_config)
5993 {
5994 mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5995 mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
5996 mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5997 mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5998
5999 mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
6000 mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
6001 mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
6002 mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
6003
6004 mode->flags = pipe_config->adjusted_mode.flags;
6005
6006 mode->clock = pipe_config->adjusted_mode.crtc_clock;
6007 mode->flags |= pipe_config->adjusted_mode.flags;
6008 }
6009
6010 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6011 {
6012 struct drm_device *dev = intel_crtc->base.dev;
6013 struct drm_i915_private *dev_priv = dev->dev_private;
6014 uint32_t pipeconf;
6015
6016 pipeconf = 0;
6017
6018 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
6019 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
6020 pipeconf |= PIPECONF_ENABLE;
6021
6022 if (intel_crtc->config.double_wide)
6023 pipeconf |= PIPECONF_DOUBLE_WIDE;
6024
6025 /* only g4x and later have fancy bpc/dither controls */
6026 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6027 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6028 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
6029 pipeconf |= PIPECONF_DITHER_EN |
6030 PIPECONF_DITHER_TYPE_SP;
6031
6032 switch (intel_crtc->config.pipe_bpp) {
6033 case 18:
6034 pipeconf |= PIPECONF_6BPC;
6035 break;
6036 case 24:
6037 pipeconf |= PIPECONF_8BPC;
6038 break;
6039 case 30:
6040 pipeconf |= PIPECONF_10BPC;
6041 break;
6042 default:
6043 /* Case prevented by intel_choose_pipe_bpp_dither. */
6044 BUG();
6045 }
6046 }
6047
6048 if (HAS_PIPE_CXSR(dev)) {
6049 if (intel_crtc->lowfreq_avail) {
6050 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6051 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6052 } else {
6053 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6054 }
6055 }
6056
6057 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6058 if (INTEL_INFO(dev)->gen < 4 ||
6059 intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
6060 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6061 else
6062 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6063 } else
6064 pipeconf |= PIPECONF_PROGRESSIVE;
6065
6066 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6067 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6068
6069 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6070 POSTING_READ(PIPECONF(intel_crtc->pipe));
6071 }
6072
6073 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
6074 int x, int y,
6075 struct drm_framebuffer *fb)
6076 {
6077 struct drm_device *dev = crtc->dev;
6078 struct drm_i915_private *dev_priv = dev->dev_private;
6079 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6080 int refclk, num_connectors = 0;
6081 intel_clock_t clock, reduced_clock;
6082 bool ok, has_reduced_clock = false;
6083 bool is_lvds = false, is_dsi = false;
6084 struct intel_encoder *encoder;
6085 const intel_limit_t *limit;
6086
6087 for_each_encoder_on_crtc(dev, crtc, encoder) {
6088 switch (encoder->type) {
6089 case INTEL_OUTPUT_LVDS:
6090 is_lvds = true;
6091 break;
6092 case INTEL_OUTPUT_DSI:
6093 is_dsi = true;
6094 break;
6095 }
6096
6097 num_connectors++;
6098 }
6099
6100 if (is_dsi)
6101 return 0;
6102
6103 if (!intel_crtc->config.clock_set) {
6104 refclk = i9xx_get_refclk(crtc, num_connectors);
6105
6106 /*
6107 * Returns a set of divisors for the desired target clock with
6108 * the given refclk, or FALSE. The returned values represent
6109 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6110 * 2) / p1 / p2.
6111 */
6112 limit = intel_limit(crtc, refclk);
6113 ok = dev_priv->display.find_dpll(limit, crtc,
6114 intel_crtc->config.port_clock,
6115 refclk, NULL, &clock);
6116 if (!ok) {
6117 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6118 return -EINVAL;
6119 }
6120
6121 if (is_lvds && dev_priv->lvds_downclock_avail) {
6122 /*
6123 * Ensure we match the reduced clock's P to the target
6124 * clock. If the clocks don't match, we can't switch
6125 * the display clock by using the FP0/FP1. In such case
6126 * we will disable the LVDS downclock feature.
6127 */
6128 has_reduced_clock =
6129 dev_priv->display.find_dpll(limit, crtc,
6130 dev_priv->lvds_downclock,
6131 refclk, &clock,
6132 &reduced_clock);
6133 }
6134 /* Compat-code for transition, will disappear. */
6135 intel_crtc->config.dpll.n = clock.n;
6136 intel_crtc->config.dpll.m1 = clock.m1;
6137 intel_crtc->config.dpll.m2 = clock.m2;
6138 intel_crtc->config.dpll.p1 = clock.p1;
6139 intel_crtc->config.dpll.p2 = clock.p2;
6140 }
6141
6142 if (IS_GEN2(dev)) {
6143 i8xx_update_pll(intel_crtc,
6144 has_reduced_clock ? &reduced_clock : NULL,
6145 num_connectors);
6146 } else if (IS_CHERRYVIEW(dev)) {
6147 chv_update_pll(intel_crtc);
6148 } else if (IS_VALLEYVIEW(dev)) {
6149 vlv_update_pll(intel_crtc);
6150 } else {
6151 i9xx_update_pll(intel_crtc,
6152 has_reduced_clock ? &reduced_clock : NULL,
6153 num_connectors);
6154 }
6155
6156 return 0;
6157 }
6158
6159 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6160 struct intel_crtc_config *pipe_config)
6161 {
6162 struct drm_device *dev = crtc->base.dev;
6163 struct drm_i915_private *dev_priv = dev->dev_private;
6164 uint32_t tmp;
6165
6166 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6167 return;
6168
6169 tmp = I915_READ(PFIT_CONTROL);
6170 if (!(tmp & PFIT_ENABLE))
6171 return;
6172
6173 /* Check whether the pfit is attached to our pipe. */
6174 if (INTEL_INFO(dev)->gen < 4) {
6175 if (crtc->pipe != PIPE_B)
6176 return;
6177 } else {
6178 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6179 return;
6180 }
6181
6182 pipe_config->gmch_pfit.control = tmp;
6183 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6184 if (INTEL_INFO(dev)->gen < 5)
6185 pipe_config->gmch_pfit.lvds_border_bits =
6186 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6187 }
6188
6189 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6190 struct intel_crtc_config *pipe_config)
6191 {
6192 struct drm_device *dev = crtc->base.dev;
6193 struct drm_i915_private *dev_priv = dev->dev_private;
6194 int pipe = pipe_config->cpu_transcoder;
6195 intel_clock_t clock;
6196 u32 mdiv;
6197 int refclk = 100000;
6198
6199 /* In case of MIPI DPLL will not even be used */
6200 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6201 return;
6202
6203 mutex_lock(&dev_priv->dpio_lock);
6204 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6205 mutex_unlock(&dev_priv->dpio_lock);
6206
6207 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6208 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6209 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6210 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6211 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6212
6213 vlv_clock(refclk, &clock);
6214
6215 /* clock.dot is the fast clock */
6216 pipe_config->port_clock = clock.dot / 5;
6217 }
6218
6219 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6220 struct intel_plane_config *plane_config)
6221 {
6222 struct drm_device *dev = crtc->base.dev;
6223 struct drm_i915_private *dev_priv = dev->dev_private;
6224 u32 val, base, offset;
6225 int pipe = crtc->pipe, plane = crtc->plane;
6226 int fourcc, pixel_format;
6227 int aligned_height;
6228
6229 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6230 if (!crtc->base.primary->fb) {
6231 DRM_DEBUG_KMS("failed to alloc fb\n");
6232 return;
6233 }
6234
6235 val = I915_READ(DSPCNTR(plane));
6236
6237 if (INTEL_INFO(dev)->gen >= 4)
6238 if (val & DISPPLANE_TILED)
6239 plane_config->tiled = true;
6240
6241 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6242 fourcc = intel_format_to_fourcc(pixel_format);
6243 crtc->base.primary->fb->pixel_format = fourcc;
6244 crtc->base.primary->fb->bits_per_pixel =
6245 drm_format_plane_cpp(fourcc, 0) * 8;
6246
6247 if (INTEL_INFO(dev)->gen >= 4) {
6248 if (plane_config->tiled)
6249 offset = I915_READ(DSPTILEOFF(plane));
6250 else
6251 offset = I915_READ(DSPLINOFF(plane));
6252 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6253 } else {
6254 base = I915_READ(DSPADDR(plane));
6255 }
6256 plane_config->base = base;
6257
6258 val = I915_READ(PIPESRC(pipe));
6259 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6260 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6261
6262 val = I915_READ(DSPSTRIDE(pipe));
6263 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
6264
6265 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6266 plane_config->tiled);
6267
6268 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6269 aligned_height);
6270
6271 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6272 pipe, plane, crtc->base.primary->fb->width,
6273 crtc->base.primary->fb->height,
6274 crtc->base.primary->fb->bits_per_pixel, base,
6275 crtc->base.primary->fb->pitches[0],
6276 plane_config->size);
6277
6278 }
6279
6280 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6281 struct intel_crtc_config *pipe_config)
6282 {
6283 struct drm_device *dev = crtc->base.dev;
6284 struct drm_i915_private *dev_priv = dev->dev_private;
6285 int pipe = pipe_config->cpu_transcoder;
6286 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6287 intel_clock_t clock;
6288 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6289 int refclk = 100000;
6290
6291 mutex_lock(&dev_priv->dpio_lock);
6292 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6293 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6294 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6295 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6296 mutex_unlock(&dev_priv->dpio_lock);
6297
6298 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6299 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6300 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6301 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6302 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6303
6304 chv_clock(refclk, &clock);
6305
6306 /* clock.dot is the fast clock */
6307 pipe_config->port_clock = clock.dot / 5;
6308 }
6309
6310 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6311 struct intel_crtc_config *pipe_config)
6312 {
6313 struct drm_device *dev = crtc->base.dev;
6314 struct drm_i915_private *dev_priv = dev->dev_private;
6315 uint32_t tmp;
6316
6317 if (!intel_display_power_enabled(dev_priv,
6318 POWER_DOMAIN_PIPE(crtc->pipe)))
6319 return false;
6320
6321 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6322 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6323
6324 tmp = I915_READ(PIPECONF(crtc->pipe));
6325 if (!(tmp & PIPECONF_ENABLE))
6326 return false;
6327
6328 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6329 switch (tmp & PIPECONF_BPC_MASK) {
6330 case PIPECONF_6BPC:
6331 pipe_config->pipe_bpp = 18;
6332 break;
6333 case PIPECONF_8BPC:
6334 pipe_config->pipe_bpp = 24;
6335 break;
6336 case PIPECONF_10BPC:
6337 pipe_config->pipe_bpp = 30;
6338 break;
6339 default:
6340 break;
6341 }
6342 }
6343
6344 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6345 pipe_config->limited_color_range = true;
6346
6347 if (INTEL_INFO(dev)->gen < 4)
6348 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6349
6350 intel_get_pipe_timings(crtc, pipe_config);
6351
6352 i9xx_get_pfit_config(crtc, pipe_config);
6353
6354 if (INTEL_INFO(dev)->gen >= 4) {
6355 tmp = I915_READ(DPLL_MD(crtc->pipe));
6356 pipe_config->pixel_multiplier =
6357 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6358 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6359 pipe_config->dpll_hw_state.dpll_md = tmp;
6360 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6361 tmp = I915_READ(DPLL(crtc->pipe));
6362 pipe_config->pixel_multiplier =
6363 ((tmp & SDVO_MULTIPLIER_MASK)
6364 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6365 } else {
6366 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6367 * port and will be fixed up in the encoder->get_config
6368 * function. */
6369 pipe_config->pixel_multiplier = 1;
6370 }
6371 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6372 if (!IS_VALLEYVIEW(dev)) {
6373 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6374 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6375 } else {
6376 /* Mask out read-only status bits. */
6377 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6378 DPLL_PORTC_READY_MASK |
6379 DPLL_PORTB_READY_MASK);
6380 }
6381
6382 if (IS_CHERRYVIEW(dev))
6383 chv_crtc_clock_get(crtc, pipe_config);
6384 else if (IS_VALLEYVIEW(dev))
6385 vlv_crtc_clock_get(crtc, pipe_config);
6386 else
6387 i9xx_crtc_clock_get(crtc, pipe_config);
6388
6389 return true;
6390 }
6391
6392 static void ironlake_init_pch_refclk(struct drm_device *dev)
6393 {
6394 struct drm_i915_private *dev_priv = dev->dev_private;
6395 struct intel_encoder *encoder;
6396 u32 val, final;
6397 bool has_lvds = false;
6398 bool has_cpu_edp = false;
6399 bool has_panel = false;
6400 bool has_ck505 = false;
6401 bool can_ssc = false;
6402
6403 /* We need to take the global config into account */
6404 for_each_intel_encoder(dev, encoder) {
6405 switch (encoder->type) {
6406 case INTEL_OUTPUT_LVDS:
6407 has_panel = true;
6408 has_lvds = true;
6409 break;
6410 case INTEL_OUTPUT_EDP:
6411 has_panel = true;
6412 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6413 has_cpu_edp = true;
6414 break;
6415 }
6416 }
6417
6418 if (HAS_PCH_IBX(dev)) {
6419 has_ck505 = dev_priv->vbt.display_clock_mode;
6420 can_ssc = has_ck505;
6421 } else {
6422 has_ck505 = false;
6423 can_ssc = true;
6424 }
6425
6426 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6427 has_panel, has_lvds, has_ck505);
6428
6429 /* Ironlake: try to setup display ref clock before DPLL
6430 * enabling. This is only under driver's control after
6431 * PCH B stepping, previous chipset stepping should be
6432 * ignoring this setting.
6433 */
6434 val = I915_READ(PCH_DREF_CONTROL);
6435
6436 /* As we must carefully and slowly disable/enable each source in turn,
6437 * compute the final state we want first and check if we need to
6438 * make any changes at all.
6439 */
6440 final = val;
6441 final &= ~DREF_NONSPREAD_SOURCE_MASK;
6442 if (has_ck505)
6443 final |= DREF_NONSPREAD_CK505_ENABLE;
6444 else
6445 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6446
6447 final &= ~DREF_SSC_SOURCE_MASK;
6448 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6449 final &= ~DREF_SSC1_ENABLE;
6450
6451 if (has_panel) {
6452 final |= DREF_SSC_SOURCE_ENABLE;
6453
6454 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6455 final |= DREF_SSC1_ENABLE;
6456
6457 if (has_cpu_edp) {
6458 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6459 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6460 else
6461 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6462 } else
6463 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6464 } else {
6465 final |= DREF_SSC_SOURCE_DISABLE;
6466 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6467 }
6468
6469 if (final == val)
6470 return;
6471
6472 /* Always enable nonspread source */
6473 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6474
6475 if (has_ck505)
6476 val |= DREF_NONSPREAD_CK505_ENABLE;
6477 else
6478 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6479
6480 if (has_panel) {
6481 val &= ~DREF_SSC_SOURCE_MASK;
6482 val |= DREF_SSC_SOURCE_ENABLE;
6483
6484 /* SSC must be turned on before enabling the CPU output */
6485 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6486 DRM_DEBUG_KMS("Using SSC on panel\n");
6487 val |= DREF_SSC1_ENABLE;
6488 } else
6489 val &= ~DREF_SSC1_ENABLE;
6490
6491 /* Get SSC going before enabling the outputs */
6492 I915_WRITE(PCH_DREF_CONTROL, val);
6493 POSTING_READ(PCH_DREF_CONTROL);
6494 udelay(200);
6495
6496 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6497
6498 /* Enable CPU source on CPU attached eDP */
6499 if (has_cpu_edp) {
6500 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6501 DRM_DEBUG_KMS("Using SSC on eDP\n");
6502 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6503 } else
6504 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6505 } else
6506 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6507
6508 I915_WRITE(PCH_DREF_CONTROL, val);
6509 POSTING_READ(PCH_DREF_CONTROL);
6510 udelay(200);
6511 } else {
6512 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6513
6514 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6515
6516 /* Turn off CPU output */
6517 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6518
6519 I915_WRITE(PCH_DREF_CONTROL, val);
6520 POSTING_READ(PCH_DREF_CONTROL);
6521 udelay(200);
6522
6523 /* Turn off the SSC source */
6524 val &= ~DREF_SSC_SOURCE_MASK;
6525 val |= DREF_SSC_SOURCE_DISABLE;
6526
6527 /* Turn off SSC1 */
6528 val &= ~DREF_SSC1_ENABLE;
6529
6530 I915_WRITE(PCH_DREF_CONTROL, val);
6531 POSTING_READ(PCH_DREF_CONTROL);
6532 udelay(200);
6533 }
6534
6535 BUG_ON(val != final);
6536 }
6537
6538 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6539 {
6540 uint32_t tmp;
6541
6542 tmp = I915_READ(SOUTH_CHICKEN2);
6543 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6544 I915_WRITE(SOUTH_CHICKEN2, tmp);
6545
6546 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6547 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6548 DRM_ERROR("FDI mPHY reset assert timeout\n");
6549
6550 tmp = I915_READ(SOUTH_CHICKEN2);
6551 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6552 I915_WRITE(SOUTH_CHICKEN2, tmp);
6553
6554 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6555 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6556 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6557 }
6558
6559 /* WaMPhyProgramming:hsw */
6560 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6561 {
6562 uint32_t tmp;
6563
6564 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6565 tmp &= ~(0xFF << 24);
6566 tmp |= (0x12 << 24);
6567 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6568
6569 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6570 tmp |= (1 << 11);
6571 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6572
6573 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6574 tmp |= (1 << 11);
6575 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6576
6577 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6578 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6579 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6580
6581 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6582 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6583 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6584
6585 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6586 tmp &= ~(7 << 13);
6587 tmp |= (5 << 13);
6588 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6589
6590 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6591 tmp &= ~(7 << 13);
6592 tmp |= (5 << 13);
6593 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6594
6595 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6596 tmp &= ~0xFF;
6597 tmp |= 0x1C;
6598 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6599
6600 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6601 tmp &= ~0xFF;
6602 tmp |= 0x1C;
6603 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6604
6605 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6606 tmp &= ~(0xFF << 16);
6607 tmp |= (0x1C << 16);
6608 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6609
6610 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6611 tmp &= ~(0xFF << 16);
6612 tmp |= (0x1C << 16);
6613 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6614
6615 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6616 tmp |= (1 << 27);
6617 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6618
6619 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6620 tmp |= (1 << 27);
6621 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6622
6623 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6624 tmp &= ~(0xF << 28);
6625 tmp |= (4 << 28);
6626 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6627
6628 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6629 tmp &= ~(0xF << 28);
6630 tmp |= (4 << 28);
6631 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6632 }
6633
6634 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6635 * Programming" based on the parameters passed:
6636 * - Sequence to enable CLKOUT_DP
6637 * - Sequence to enable CLKOUT_DP without spread
6638 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6639 */
6640 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6641 bool with_fdi)
6642 {
6643 struct drm_i915_private *dev_priv = dev->dev_private;
6644 uint32_t reg, tmp;
6645
6646 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6647 with_spread = true;
6648 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6649 with_fdi, "LP PCH doesn't have FDI\n"))
6650 with_fdi = false;
6651
6652 mutex_lock(&dev_priv->dpio_lock);
6653
6654 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6655 tmp &= ~SBI_SSCCTL_DISABLE;
6656 tmp |= SBI_SSCCTL_PATHALT;
6657 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6658
6659 udelay(24);
6660
6661 if (with_spread) {
6662 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6663 tmp &= ~SBI_SSCCTL_PATHALT;
6664 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6665
6666 if (with_fdi) {
6667 lpt_reset_fdi_mphy(dev_priv);
6668 lpt_program_fdi_mphy(dev_priv);
6669 }
6670 }
6671
6672 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6673 SBI_GEN0 : SBI_DBUFF0;
6674 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6675 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6676 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6677
6678 mutex_unlock(&dev_priv->dpio_lock);
6679 }
6680
6681 /* Sequence to disable CLKOUT_DP */
6682 static void lpt_disable_clkout_dp(struct drm_device *dev)
6683 {
6684 struct drm_i915_private *dev_priv = dev->dev_private;
6685 uint32_t reg, tmp;
6686
6687 mutex_lock(&dev_priv->dpio_lock);
6688
6689 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6690 SBI_GEN0 : SBI_DBUFF0;
6691 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6692 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6693 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6694
6695 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6696 if (!(tmp & SBI_SSCCTL_DISABLE)) {
6697 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6698 tmp |= SBI_SSCCTL_PATHALT;
6699 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6700 udelay(32);
6701 }
6702 tmp |= SBI_SSCCTL_DISABLE;
6703 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6704 }
6705
6706 mutex_unlock(&dev_priv->dpio_lock);
6707 }
6708
6709 static void lpt_init_pch_refclk(struct drm_device *dev)
6710 {
6711 struct intel_encoder *encoder;
6712 bool has_vga = false;
6713
6714 for_each_intel_encoder(dev, encoder) {
6715 switch (encoder->type) {
6716 case INTEL_OUTPUT_ANALOG:
6717 has_vga = true;
6718 break;
6719 }
6720 }
6721
6722 if (has_vga)
6723 lpt_enable_clkout_dp(dev, true, true);
6724 else
6725 lpt_disable_clkout_dp(dev);
6726 }
6727
6728 /*
6729 * Initialize reference clocks when the driver loads
6730 */
6731 void intel_init_pch_refclk(struct drm_device *dev)
6732 {
6733 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6734 ironlake_init_pch_refclk(dev);
6735 else if (HAS_PCH_LPT(dev))
6736 lpt_init_pch_refclk(dev);
6737 }
6738
6739 static int ironlake_get_refclk(struct drm_crtc *crtc)
6740 {
6741 struct drm_device *dev = crtc->dev;
6742 struct drm_i915_private *dev_priv = dev->dev_private;
6743 struct intel_encoder *encoder;
6744 int num_connectors = 0;
6745 bool is_lvds = false;
6746
6747 for_each_encoder_on_crtc(dev, crtc, encoder) {
6748 switch (encoder->type) {
6749 case INTEL_OUTPUT_LVDS:
6750 is_lvds = true;
6751 break;
6752 }
6753 num_connectors++;
6754 }
6755
6756 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6757 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6758 dev_priv->vbt.lvds_ssc_freq);
6759 return dev_priv->vbt.lvds_ssc_freq;
6760 }
6761
6762 return 120000;
6763 }
6764
6765 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6766 {
6767 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6768 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6769 int pipe = intel_crtc->pipe;
6770 uint32_t val;
6771
6772 val = 0;
6773
6774 switch (intel_crtc->config.pipe_bpp) {
6775 case 18:
6776 val |= PIPECONF_6BPC;
6777 break;
6778 case 24:
6779 val |= PIPECONF_8BPC;
6780 break;
6781 case 30:
6782 val |= PIPECONF_10BPC;
6783 break;
6784 case 36:
6785 val |= PIPECONF_12BPC;
6786 break;
6787 default:
6788 /* Case prevented by intel_choose_pipe_bpp_dither. */
6789 BUG();
6790 }
6791
6792 if (intel_crtc->config.dither)
6793 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6794
6795 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6796 val |= PIPECONF_INTERLACED_ILK;
6797 else
6798 val |= PIPECONF_PROGRESSIVE;
6799
6800 if (intel_crtc->config.limited_color_range)
6801 val |= PIPECONF_COLOR_RANGE_SELECT;
6802
6803 I915_WRITE(PIPECONF(pipe), val);
6804 POSTING_READ(PIPECONF(pipe));
6805 }
6806
6807 /*
6808 * Set up the pipe CSC unit.
6809 *
6810 * Currently only full range RGB to limited range RGB conversion
6811 * is supported, but eventually this should handle various
6812 * RGB<->YCbCr scenarios as well.
6813 */
6814 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6815 {
6816 struct drm_device *dev = crtc->dev;
6817 struct drm_i915_private *dev_priv = dev->dev_private;
6818 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6819 int pipe = intel_crtc->pipe;
6820 uint16_t coeff = 0x7800; /* 1.0 */
6821
6822 /*
6823 * TODO: Check what kind of values actually come out of the pipe
6824 * with these coeff/postoff values and adjust to get the best
6825 * accuracy. Perhaps we even need to take the bpc value into
6826 * consideration.
6827 */
6828
6829 if (intel_crtc->config.limited_color_range)
6830 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6831
6832 /*
6833 * GY/GU and RY/RU should be the other way around according
6834 * to BSpec, but reality doesn't agree. Just set them up in
6835 * a way that results in the correct picture.
6836 */
6837 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6838 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6839
6840 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6841 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6842
6843 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6844 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6845
6846 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6847 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6848 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6849
6850 if (INTEL_INFO(dev)->gen > 6) {
6851 uint16_t postoff = 0;
6852
6853 if (intel_crtc->config.limited_color_range)
6854 postoff = (16 * (1 << 12) / 255) & 0x1fff;
6855
6856 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6857 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6858 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6859
6860 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6861 } else {
6862 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6863
6864 if (intel_crtc->config.limited_color_range)
6865 mode |= CSC_BLACK_SCREEN_OFFSET;
6866
6867 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6868 }
6869 }
6870
6871 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6872 {
6873 struct drm_device *dev = crtc->dev;
6874 struct drm_i915_private *dev_priv = dev->dev_private;
6875 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6876 enum pipe pipe = intel_crtc->pipe;
6877 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6878 uint32_t val;
6879
6880 val = 0;
6881
6882 if (IS_HASWELL(dev) && intel_crtc->config.dither)
6883 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6884
6885 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6886 val |= PIPECONF_INTERLACED_ILK;
6887 else
6888 val |= PIPECONF_PROGRESSIVE;
6889
6890 I915_WRITE(PIPECONF(cpu_transcoder), val);
6891 POSTING_READ(PIPECONF(cpu_transcoder));
6892
6893 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6894 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6895
6896 if (IS_BROADWELL(dev)) {
6897 val = 0;
6898
6899 switch (intel_crtc->config.pipe_bpp) {
6900 case 18:
6901 val |= PIPEMISC_DITHER_6_BPC;
6902 break;
6903 case 24:
6904 val |= PIPEMISC_DITHER_8_BPC;
6905 break;
6906 case 30:
6907 val |= PIPEMISC_DITHER_10_BPC;
6908 break;
6909 case 36:
6910 val |= PIPEMISC_DITHER_12_BPC;
6911 break;
6912 default:
6913 /* Case prevented by pipe_config_set_bpp. */
6914 BUG();
6915 }
6916
6917 if (intel_crtc->config.dither)
6918 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6919
6920 I915_WRITE(PIPEMISC(pipe), val);
6921 }
6922 }
6923
6924 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6925 intel_clock_t *clock,
6926 bool *has_reduced_clock,
6927 intel_clock_t *reduced_clock)
6928 {
6929 struct drm_device *dev = crtc->dev;
6930 struct drm_i915_private *dev_priv = dev->dev_private;
6931 struct intel_encoder *intel_encoder;
6932 int refclk;
6933 const intel_limit_t *limit;
6934 bool ret, is_lvds = false;
6935
6936 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6937 switch (intel_encoder->type) {
6938 case INTEL_OUTPUT_LVDS:
6939 is_lvds = true;
6940 break;
6941 }
6942 }
6943
6944 refclk = ironlake_get_refclk(crtc);
6945
6946 /*
6947 * Returns a set of divisors for the desired target clock with the given
6948 * refclk, or FALSE. The returned values represent the clock equation:
6949 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6950 */
6951 limit = intel_limit(crtc, refclk);
6952 ret = dev_priv->display.find_dpll(limit, crtc,
6953 to_intel_crtc(crtc)->config.port_clock,
6954 refclk, NULL, clock);
6955 if (!ret)
6956 return false;
6957
6958 if (is_lvds && dev_priv->lvds_downclock_avail) {
6959 /*
6960 * Ensure we match the reduced clock's P to the target clock.
6961 * If the clocks don't match, we can't switch the display clock
6962 * by using the FP0/FP1. In such case we will disable the LVDS
6963 * downclock feature.
6964 */
6965 *has_reduced_clock =
6966 dev_priv->display.find_dpll(limit, crtc,
6967 dev_priv->lvds_downclock,
6968 refclk, clock,
6969 reduced_clock);
6970 }
6971
6972 return true;
6973 }
6974
6975 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6976 {
6977 /*
6978 * Account for spread spectrum to avoid
6979 * oversubscribing the link. Max center spread
6980 * is 2.5%; use 5% for safety's sake.
6981 */
6982 u32 bps = target_clock * bpp * 21 / 20;
6983 return DIV_ROUND_UP(bps, link_bw * 8);
6984 }
6985
6986 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6987 {
6988 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6989 }
6990
6991 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6992 u32 *fp,
6993 intel_clock_t *reduced_clock, u32 *fp2)
6994 {
6995 struct drm_crtc *crtc = &intel_crtc->base;
6996 struct drm_device *dev = crtc->dev;
6997 struct drm_i915_private *dev_priv = dev->dev_private;
6998 struct intel_encoder *intel_encoder;
6999 uint32_t dpll;
7000 int factor, num_connectors = 0;
7001 bool is_lvds = false, is_sdvo = false;
7002
7003 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
7004 switch (intel_encoder->type) {
7005 case INTEL_OUTPUT_LVDS:
7006 is_lvds = true;
7007 break;
7008 case INTEL_OUTPUT_SDVO:
7009 case INTEL_OUTPUT_HDMI:
7010 is_sdvo = true;
7011 break;
7012 }
7013
7014 num_connectors++;
7015 }
7016
7017 /* Enable autotuning of the PLL clock (if permissible) */
7018 factor = 21;
7019 if (is_lvds) {
7020 if ((intel_panel_use_ssc(dev_priv) &&
7021 dev_priv->vbt.lvds_ssc_freq == 100000) ||
7022 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7023 factor = 25;
7024 } else if (intel_crtc->config.sdvo_tv_clock)
7025 factor = 20;
7026
7027 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7028 *fp |= FP_CB_TUNE;
7029
7030 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7031 *fp2 |= FP_CB_TUNE;
7032
7033 dpll = 0;
7034
7035 if (is_lvds)
7036 dpll |= DPLLB_MODE_LVDS;
7037 else
7038 dpll |= DPLLB_MODE_DAC_SERIAL;
7039
7040 dpll |= (intel_crtc->config.pixel_multiplier - 1)
7041 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7042
7043 if (is_sdvo)
7044 dpll |= DPLL_SDVO_HIGH_SPEED;
7045 if (intel_crtc->config.has_dp_encoder)
7046 dpll |= DPLL_SDVO_HIGH_SPEED;
7047
7048 /* compute bitmask from p1 value */
7049 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7050 /* also FPA1 */
7051 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7052
7053 switch (intel_crtc->config.dpll.p2) {
7054 case 5:
7055 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7056 break;
7057 case 7:
7058 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7059 break;
7060 case 10:
7061 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7062 break;
7063 case 14:
7064 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7065 break;
7066 }
7067
7068 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7069 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7070 else
7071 dpll |= PLL_REF_INPUT_DREFCLK;
7072
7073 return dpll | DPLL_VCO_ENABLE;
7074 }
7075
7076 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
7077 int x, int y,
7078 struct drm_framebuffer *fb)
7079 {
7080 struct drm_device *dev = crtc->dev;
7081 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7082 int num_connectors = 0;
7083 intel_clock_t clock, reduced_clock;
7084 u32 dpll = 0, fp = 0, fp2 = 0;
7085 bool ok, has_reduced_clock = false;
7086 bool is_lvds = false;
7087 struct intel_encoder *encoder;
7088 struct intel_shared_dpll *pll;
7089
7090 for_each_encoder_on_crtc(dev, crtc, encoder) {
7091 switch (encoder->type) {
7092 case INTEL_OUTPUT_LVDS:
7093 is_lvds = true;
7094 break;
7095 }
7096
7097 num_connectors++;
7098 }
7099
7100 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7101 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7102
7103 ok = ironlake_compute_clocks(crtc, &clock,
7104 &has_reduced_clock, &reduced_clock);
7105 if (!ok && !intel_crtc->config.clock_set) {
7106 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7107 return -EINVAL;
7108 }
7109 /* Compat-code for transition, will disappear. */
7110 if (!intel_crtc->config.clock_set) {
7111 intel_crtc->config.dpll.n = clock.n;
7112 intel_crtc->config.dpll.m1 = clock.m1;
7113 intel_crtc->config.dpll.m2 = clock.m2;
7114 intel_crtc->config.dpll.p1 = clock.p1;
7115 intel_crtc->config.dpll.p2 = clock.p2;
7116 }
7117
7118 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7119 if (intel_crtc->config.has_pch_encoder) {
7120 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
7121 if (has_reduced_clock)
7122 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7123
7124 dpll = ironlake_compute_dpll(intel_crtc,
7125 &fp, &reduced_clock,
7126 has_reduced_clock ? &fp2 : NULL);
7127
7128 intel_crtc->config.dpll_hw_state.dpll = dpll;
7129 intel_crtc->config.dpll_hw_state.fp0 = fp;
7130 if (has_reduced_clock)
7131 intel_crtc->config.dpll_hw_state.fp1 = fp2;
7132 else
7133 intel_crtc->config.dpll_hw_state.fp1 = fp;
7134
7135 pll = intel_get_shared_dpll(intel_crtc);
7136 if (pll == NULL) {
7137 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7138 pipe_name(intel_crtc->pipe));
7139 return -EINVAL;
7140 }
7141 } else
7142 intel_put_shared_dpll(intel_crtc);
7143
7144 if (is_lvds && has_reduced_clock && i915.powersave)
7145 intel_crtc->lowfreq_avail = true;
7146 else
7147 intel_crtc->lowfreq_avail = false;
7148
7149 return 0;
7150 }
7151
7152 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7153 struct intel_link_m_n *m_n)
7154 {
7155 struct drm_device *dev = crtc->base.dev;
7156 struct drm_i915_private *dev_priv = dev->dev_private;
7157 enum pipe pipe = crtc->pipe;
7158
7159 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7160 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7161 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7162 & ~TU_SIZE_MASK;
7163 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7164 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7165 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7166 }
7167
7168 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7169 enum transcoder transcoder,
7170 struct intel_link_m_n *m_n,
7171 struct intel_link_m_n *m2_n2)
7172 {
7173 struct drm_device *dev = crtc->base.dev;
7174 struct drm_i915_private *dev_priv = dev->dev_private;
7175 enum pipe pipe = crtc->pipe;
7176
7177 if (INTEL_INFO(dev)->gen >= 5) {
7178 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7179 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7180 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7181 & ~TU_SIZE_MASK;
7182 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7183 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7184 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7185 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7186 * gen < 8) and if DRRS is supported (to make sure the
7187 * registers are not unnecessarily read).
7188 */
7189 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7190 crtc->config.has_drrs) {
7191 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7192 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7193 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7194 & ~TU_SIZE_MASK;
7195 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7196 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7197 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7198 }
7199 } else {
7200 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7201 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7202 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7203 & ~TU_SIZE_MASK;
7204 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7205 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7206 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7207 }
7208 }
7209
7210 void intel_dp_get_m_n(struct intel_crtc *crtc,
7211 struct intel_crtc_config *pipe_config)
7212 {
7213 if (crtc->config.has_pch_encoder)
7214 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7215 else
7216 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7217 &pipe_config->dp_m_n,
7218 &pipe_config->dp_m2_n2);
7219 }
7220
7221 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7222 struct intel_crtc_config *pipe_config)
7223 {
7224 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7225 &pipe_config->fdi_m_n, NULL);
7226 }
7227
7228 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7229 struct intel_crtc_config *pipe_config)
7230 {
7231 struct drm_device *dev = crtc->base.dev;
7232 struct drm_i915_private *dev_priv = dev->dev_private;
7233 uint32_t tmp;
7234
7235 tmp = I915_READ(PF_CTL(crtc->pipe));
7236
7237 if (tmp & PF_ENABLE) {
7238 pipe_config->pch_pfit.enabled = true;
7239 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7240 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7241
7242 /* We currently do not free assignements of panel fitters on
7243 * ivb/hsw (since we don't use the higher upscaling modes which
7244 * differentiates them) so just WARN about this case for now. */
7245 if (IS_GEN7(dev)) {
7246 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7247 PF_PIPE_SEL_IVB(crtc->pipe));
7248 }
7249 }
7250 }
7251
7252 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7253 struct intel_plane_config *plane_config)
7254 {
7255 struct drm_device *dev = crtc->base.dev;
7256 struct drm_i915_private *dev_priv = dev->dev_private;
7257 u32 val, base, offset;
7258 int pipe = crtc->pipe, plane = crtc->plane;
7259 int fourcc, pixel_format;
7260 int aligned_height;
7261
7262 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7263 if (!crtc->base.primary->fb) {
7264 DRM_DEBUG_KMS("failed to alloc fb\n");
7265 return;
7266 }
7267
7268 val = I915_READ(DSPCNTR(plane));
7269
7270 if (INTEL_INFO(dev)->gen >= 4)
7271 if (val & DISPPLANE_TILED)
7272 plane_config->tiled = true;
7273
7274 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7275 fourcc = intel_format_to_fourcc(pixel_format);
7276 crtc->base.primary->fb->pixel_format = fourcc;
7277 crtc->base.primary->fb->bits_per_pixel =
7278 drm_format_plane_cpp(fourcc, 0) * 8;
7279
7280 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7281 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7282 offset = I915_READ(DSPOFFSET(plane));
7283 } else {
7284 if (plane_config->tiled)
7285 offset = I915_READ(DSPTILEOFF(plane));
7286 else
7287 offset = I915_READ(DSPLINOFF(plane));
7288 }
7289 plane_config->base = base;
7290
7291 val = I915_READ(PIPESRC(pipe));
7292 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7293 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7294
7295 val = I915_READ(DSPSTRIDE(pipe));
7296 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
7297
7298 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7299 plane_config->tiled);
7300
7301 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7302 aligned_height);
7303
7304 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7305 pipe, plane, crtc->base.primary->fb->width,
7306 crtc->base.primary->fb->height,
7307 crtc->base.primary->fb->bits_per_pixel, base,
7308 crtc->base.primary->fb->pitches[0],
7309 plane_config->size);
7310 }
7311
7312 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7313 struct intel_crtc_config *pipe_config)
7314 {
7315 struct drm_device *dev = crtc->base.dev;
7316 struct drm_i915_private *dev_priv = dev->dev_private;
7317 uint32_t tmp;
7318
7319 if (!intel_display_power_enabled(dev_priv,
7320 POWER_DOMAIN_PIPE(crtc->pipe)))
7321 return false;
7322
7323 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7324 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7325
7326 tmp = I915_READ(PIPECONF(crtc->pipe));
7327 if (!(tmp & PIPECONF_ENABLE))
7328 return false;
7329
7330 switch (tmp & PIPECONF_BPC_MASK) {
7331 case PIPECONF_6BPC:
7332 pipe_config->pipe_bpp = 18;
7333 break;
7334 case PIPECONF_8BPC:
7335 pipe_config->pipe_bpp = 24;
7336 break;
7337 case PIPECONF_10BPC:
7338 pipe_config->pipe_bpp = 30;
7339 break;
7340 case PIPECONF_12BPC:
7341 pipe_config->pipe_bpp = 36;
7342 break;
7343 default:
7344 break;
7345 }
7346
7347 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7348 pipe_config->limited_color_range = true;
7349
7350 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7351 struct intel_shared_dpll *pll;
7352
7353 pipe_config->has_pch_encoder = true;
7354
7355 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7356 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7357 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7358
7359 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7360
7361 if (HAS_PCH_IBX(dev_priv->dev)) {
7362 pipe_config->shared_dpll =
7363 (enum intel_dpll_id) crtc->pipe;
7364 } else {
7365 tmp = I915_READ(PCH_DPLL_SEL);
7366 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7367 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7368 else
7369 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7370 }
7371
7372 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7373
7374 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7375 &pipe_config->dpll_hw_state));
7376
7377 tmp = pipe_config->dpll_hw_state.dpll;
7378 pipe_config->pixel_multiplier =
7379 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7380 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7381
7382 ironlake_pch_clock_get(crtc, pipe_config);
7383 } else {
7384 pipe_config->pixel_multiplier = 1;
7385 }
7386
7387 intel_get_pipe_timings(crtc, pipe_config);
7388
7389 ironlake_get_pfit_config(crtc, pipe_config);
7390
7391 return true;
7392 }
7393
7394 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7395 {
7396 struct drm_device *dev = dev_priv->dev;
7397 struct intel_crtc *crtc;
7398
7399 for_each_intel_crtc(dev, crtc)
7400 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7401 pipe_name(crtc->pipe));
7402
7403 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7404 WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7405 WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7406 WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7407 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7408 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7409 "CPU PWM1 enabled\n");
7410 if (IS_HASWELL(dev))
7411 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7412 "CPU PWM2 enabled\n");
7413 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7414 "PCH PWM1 enabled\n");
7415 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7416 "Utility pin enabled\n");
7417 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7418
7419 /*
7420 * In theory we can still leave IRQs enabled, as long as only the HPD
7421 * interrupts remain enabled. We used to check for that, but since it's
7422 * gen-specific and since we only disable LCPLL after we fully disable
7423 * the interrupts, the check below should be enough.
7424 */
7425 WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7426 }
7427
7428 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7429 {
7430 struct drm_device *dev = dev_priv->dev;
7431
7432 if (IS_HASWELL(dev))
7433 return I915_READ(D_COMP_HSW);
7434 else
7435 return I915_READ(D_COMP_BDW);
7436 }
7437
7438 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7439 {
7440 struct drm_device *dev = dev_priv->dev;
7441
7442 if (IS_HASWELL(dev)) {
7443 mutex_lock(&dev_priv->rps.hw_lock);
7444 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7445 val))
7446 DRM_ERROR("Failed to write to D_COMP\n");
7447 mutex_unlock(&dev_priv->rps.hw_lock);
7448 } else {
7449 I915_WRITE(D_COMP_BDW, val);
7450 POSTING_READ(D_COMP_BDW);
7451 }
7452 }
7453
7454 /*
7455 * This function implements pieces of two sequences from BSpec:
7456 * - Sequence for display software to disable LCPLL
7457 * - Sequence for display software to allow package C8+
7458 * The steps implemented here are just the steps that actually touch the LCPLL
7459 * register. Callers should take care of disabling all the display engine
7460 * functions, doing the mode unset, fixing interrupts, etc.
7461 */
7462 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7463 bool switch_to_fclk, bool allow_power_down)
7464 {
7465 uint32_t val;
7466
7467 assert_can_disable_lcpll(dev_priv);
7468
7469 val = I915_READ(LCPLL_CTL);
7470
7471 if (switch_to_fclk) {
7472 val |= LCPLL_CD_SOURCE_FCLK;
7473 I915_WRITE(LCPLL_CTL, val);
7474
7475 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7476 LCPLL_CD_SOURCE_FCLK_DONE, 1))
7477 DRM_ERROR("Switching to FCLK failed\n");
7478
7479 val = I915_READ(LCPLL_CTL);
7480 }
7481
7482 val |= LCPLL_PLL_DISABLE;
7483 I915_WRITE(LCPLL_CTL, val);
7484 POSTING_READ(LCPLL_CTL);
7485
7486 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7487 DRM_ERROR("LCPLL still locked\n");
7488
7489 val = hsw_read_dcomp(dev_priv);
7490 val |= D_COMP_COMP_DISABLE;
7491 hsw_write_dcomp(dev_priv, val);
7492 ndelay(100);
7493
7494 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7495 1))
7496 DRM_ERROR("D_COMP RCOMP still in progress\n");
7497
7498 if (allow_power_down) {
7499 val = I915_READ(LCPLL_CTL);
7500 val |= LCPLL_POWER_DOWN_ALLOW;
7501 I915_WRITE(LCPLL_CTL, val);
7502 POSTING_READ(LCPLL_CTL);
7503 }
7504 }
7505
7506 /*
7507 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7508 * source.
7509 */
7510 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7511 {
7512 uint32_t val;
7513 unsigned long irqflags;
7514
7515 val = I915_READ(LCPLL_CTL);
7516
7517 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7518 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7519 return;
7520
7521 /*
7522 * Make sure we're not on PC8 state before disabling PC8, otherwise
7523 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7524 *
7525 * The other problem is that hsw_restore_lcpll() is called as part of
7526 * the runtime PM resume sequence, so we can't just call
7527 * gen6_gt_force_wake_get() because that function calls
7528 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7529 * while we are on the resume sequence. So to solve this problem we have
7530 * to call special forcewake code that doesn't touch runtime PM and
7531 * doesn't enable the forcewake delayed work.
7532 */
7533 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7534 if (dev_priv->uncore.forcewake_count++ == 0)
7535 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7536 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7537
7538 if (val & LCPLL_POWER_DOWN_ALLOW) {
7539 val &= ~LCPLL_POWER_DOWN_ALLOW;
7540 I915_WRITE(LCPLL_CTL, val);
7541 POSTING_READ(LCPLL_CTL);
7542 }
7543
7544 val = hsw_read_dcomp(dev_priv);
7545 val |= D_COMP_COMP_FORCE;
7546 val &= ~D_COMP_COMP_DISABLE;
7547 hsw_write_dcomp(dev_priv, val);
7548
7549 val = I915_READ(LCPLL_CTL);
7550 val &= ~LCPLL_PLL_DISABLE;
7551 I915_WRITE(LCPLL_CTL, val);
7552
7553 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7554 DRM_ERROR("LCPLL not locked yet\n");
7555
7556 if (val & LCPLL_CD_SOURCE_FCLK) {
7557 val = I915_READ(LCPLL_CTL);
7558 val &= ~LCPLL_CD_SOURCE_FCLK;
7559 I915_WRITE(LCPLL_CTL, val);
7560
7561 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7562 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7563 DRM_ERROR("Switching back to LCPLL failed\n");
7564 }
7565
7566 /* See the big comment above. */
7567 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7568 if (--dev_priv->uncore.forcewake_count == 0)
7569 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7570 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7571 }
7572
7573 /*
7574 * Package states C8 and deeper are really deep PC states that can only be
7575 * reached when all the devices on the system allow it, so even if the graphics
7576 * device allows PC8+, it doesn't mean the system will actually get to these
7577 * states. Our driver only allows PC8+ when going into runtime PM.
7578 *
7579 * The requirements for PC8+ are that all the outputs are disabled, the power
7580 * well is disabled and most interrupts are disabled, and these are also
7581 * requirements for runtime PM. When these conditions are met, we manually do
7582 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7583 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7584 * hang the machine.
7585 *
7586 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7587 * the state of some registers, so when we come back from PC8+ we need to
7588 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7589 * need to take care of the registers kept by RC6. Notice that this happens even
7590 * if we don't put the device in PCI D3 state (which is what currently happens
7591 * because of the runtime PM support).
7592 *
7593 * For more, read "Display Sequences for Package C8" on the hardware
7594 * documentation.
7595 */
7596 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7597 {
7598 struct drm_device *dev = dev_priv->dev;
7599 uint32_t val;
7600
7601 DRM_DEBUG_KMS("Enabling package C8+\n");
7602
7603 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7604 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7605 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7606 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7607 }
7608
7609 lpt_disable_clkout_dp(dev);
7610 hsw_disable_lcpll(dev_priv, true, true);
7611 }
7612
7613 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7614 {
7615 struct drm_device *dev = dev_priv->dev;
7616 uint32_t val;
7617
7618 DRM_DEBUG_KMS("Disabling package C8+\n");
7619
7620 hsw_restore_lcpll(dev_priv);
7621 lpt_init_pch_refclk(dev);
7622
7623 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7624 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7625 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7626 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7627 }
7628
7629 intel_prepare_ddi(dev);
7630 }
7631
7632 static void snb_modeset_global_resources(struct drm_device *dev)
7633 {
7634 modeset_update_crtc_power_domains(dev);
7635 }
7636
7637 static void haswell_modeset_global_resources(struct drm_device *dev)
7638 {
7639 modeset_update_crtc_power_domains(dev);
7640 }
7641
7642 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7643 int x, int y,
7644 struct drm_framebuffer *fb)
7645 {
7646 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7647
7648 if (!intel_ddi_pll_select(intel_crtc))
7649 return -EINVAL;
7650
7651 intel_crtc->lowfreq_avail = false;
7652
7653 return 0;
7654 }
7655
7656 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
7657 enum port port,
7658 struct intel_crtc_config *pipe_config)
7659 {
7660 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
7661
7662 switch (pipe_config->ddi_pll_sel) {
7663 case PORT_CLK_SEL_WRPLL1:
7664 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
7665 break;
7666 case PORT_CLK_SEL_WRPLL2:
7667 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
7668 break;
7669 }
7670 }
7671
7672 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
7673 struct intel_crtc_config *pipe_config)
7674 {
7675 struct drm_device *dev = crtc->base.dev;
7676 struct drm_i915_private *dev_priv = dev->dev_private;
7677 struct intel_shared_dpll *pll;
7678 enum port port;
7679 uint32_t tmp;
7680
7681 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7682
7683 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
7684
7685 haswell_get_ddi_pll(dev_priv, port, pipe_config);
7686
7687 if (pipe_config->shared_dpll >= 0) {
7688 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7689
7690 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7691 &pipe_config->dpll_hw_state));
7692 }
7693
7694 /*
7695 * Haswell has only FDI/PCH transcoder A. It is which is connected to
7696 * DDI E. So just check whether this pipe is wired to DDI E and whether
7697 * the PCH transcoder is on.
7698 */
7699 if ((port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7700 pipe_config->has_pch_encoder = true;
7701
7702 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7703 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7704 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7705
7706 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7707 }
7708 }
7709
7710 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7711 struct intel_crtc_config *pipe_config)
7712 {
7713 struct drm_device *dev = crtc->base.dev;
7714 struct drm_i915_private *dev_priv = dev->dev_private;
7715 enum intel_display_power_domain pfit_domain;
7716 uint32_t tmp;
7717
7718 if (!intel_display_power_enabled(dev_priv,
7719 POWER_DOMAIN_PIPE(crtc->pipe)))
7720 return false;
7721
7722 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7723 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7724
7725 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7726 if (tmp & TRANS_DDI_FUNC_ENABLE) {
7727 enum pipe trans_edp_pipe;
7728 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7729 default:
7730 WARN(1, "unknown pipe linked to edp transcoder\n");
7731 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7732 case TRANS_DDI_EDP_INPUT_A_ON:
7733 trans_edp_pipe = PIPE_A;
7734 break;
7735 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7736 trans_edp_pipe = PIPE_B;
7737 break;
7738 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7739 trans_edp_pipe = PIPE_C;
7740 break;
7741 }
7742
7743 if (trans_edp_pipe == crtc->pipe)
7744 pipe_config->cpu_transcoder = TRANSCODER_EDP;
7745 }
7746
7747 if (!intel_display_power_enabled(dev_priv,
7748 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7749 return false;
7750
7751 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7752 if (!(tmp & PIPECONF_ENABLE))
7753 return false;
7754
7755 haswell_get_ddi_port_state(crtc, pipe_config);
7756
7757 intel_get_pipe_timings(crtc, pipe_config);
7758
7759 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7760 if (intel_display_power_enabled(dev_priv, pfit_domain))
7761 ironlake_get_pfit_config(crtc, pipe_config);
7762
7763 if (IS_HASWELL(dev))
7764 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7765 (I915_READ(IPS_CTL) & IPS_ENABLE);
7766
7767 pipe_config->pixel_multiplier = 1;
7768
7769 return true;
7770 }
7771
7772 static struct {
7773 int clock;
7774 u32 config;
7775 } hdmi_audio_clock[] = {
7776 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7777 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7778 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7779 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7780 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7781 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7782 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7783 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7784 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7785 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7786 };
7787
7788 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7789 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7790 {
7791 int i;
7792
7793 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7794 if (mode->clock == hdmi_audio_clock[i].clock)
7795 break;
7796 }
7797
7798 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7799 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7800 i = 1;
7801 }
7802
7803 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7804 hdmi_audio_clock[i].clock,
7805 hdmi_audio_clock[i].config);
7806
7807 return hdmi_audio_clock[i].config;
7808 }
7809
7810 static bool intel_eld_uptodate(struct drm_connector *connector,
7811 int reg_eldv, uint32_t bits_eldv,
7812 int reg_elda, uint32_t bits_elda,
7813 int reg_edid)
7814 {
7815 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7816 uint8_t *eld = connector->eld;
7817 uint32_t i;
7818
7819 i = I915_READ(reg_eldv);
7820 i &= bits_eldv;
7821
7822 if (!eld[0])
7823 return !i;
7824
7825 if (!i)
7826 return false;
7827
7828 i = I915_READ(reg_elda);
7829 i &= ~bits_elda;
7830 I915_WRITE(reg_elda, i);
7831
7832 for (i = 0; i < eld[2]; i++)
7833 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7834 return false;
7835
7836 return true;
7837 }
7838
7839 static void g4x_write_eld(struct drm_connector *connector,
7840 struct drm_crtc *crtc,
7841 struct drm_display_mode *mode)
7842 {
7843 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7844 uint8_t *eld = connector->eld;
7845 uint32_t eldv;
7846 uint32_t len;
7847 uint32_t i;
7848
7849 i = I915_READ(G4X_AUD_VID_DID);
7850
7851 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7852 eldv = G4X_ELDV_DEVCL_DEVBLC;
7853 else
7854 eldv = G4X_ELDV_DEVCTG;
7855
7856 if (intel_eld_uptodate(connector,
7857 G4X_AUD_CNTL_ST, eldv,
7858 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7859 G4X_HDMIW_HDMIEDID))
7860 return;
7861
7862 i = I915_READ(G4X_AUD_CNTL_ST);
7863 i &= ~(eldv | G4X_ELD_ADDR);
7864 len = (i >> 9) & 0x1f; /* ELD buffer size */
7865 I915_WRITE(G4X_AUD_CNTL_ST, i);
7866
7867 if (!eld[0])
7868 return;
7869
7870 len = min_t(uint8_t, eld[2], len);
7871 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7872 for (i = 0; i < len; i++)
7873 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7874
7875 i = I915_READ(G4X_AUD_CNTL_ST);
7876 i |= eldv;
7877 I915_WRITE(G4X_AUD_CNTL_ST, i);
7878 }
7879
7880 static void haswell_write_eld(struct drm_connector *connector,
7881 struct drm_crtc *crtc,
7882 struct drm_display_mode *mode)
7883 {
7884 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7885 uint8_t *eld = connector->eld;
7886 uint32_t eldv;
7887 uint32_t i;
7888 int len;
7889 int pipe = to_intel_crtc(crtc)->pipe;
7890 int tmp;
7891
7892 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7893 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7894 int aud_config = HSW_AUD_CFG(pipe);
7895 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7896
7897 /* Audio output enable */
7898 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7899 tmp = I915_READ(aud_cntrl_st2);
7900 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7901 I915_WRITE(aud_cntrl_st2, tmp);
7902 POSTING_READ(aud_cntrl_st2);
7903
7904 assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
7905
7906 /* Set ELD valid state */
7907 tmp = I915_READ(aud_cntrl_st2);
7908 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7909 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7910 I915_WRITE(aud_cntrl_st2, tmp);
7911 tmp = I915_READ(aud_cntrl_st2);
7912 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7913
7914 /* Enable HDMI mode */
7915 tmp = I915_READ(aud_config);
7916 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7917 /* clear N_programing_enable and N_value_index */
7918 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7919 I915_WRITE(aud_config, tmp);
7920
7921 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7922
7923 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7924
7925 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7926 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7927 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7928 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7929 } else {
7930 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7931 }
7932
7933 if (intel_eld_uptodate(connector,
7934 aud_cntrl_st2, eldv,
7935 aud_cntl_st, IBX_ELD_ADDRESS,
7936 hdmiw_hdmiedid))
7937 return;
7938
7939 i = I915_READ(aud_cntrl_st2);
7940 i &= ~eldv;
7941 I915_WRITE(aud_cntrl_st2, i);
7942
7943 if (!eld[0])
7944 return;
7945
7946 i = I915_READ(aud_cntl_st);
7947 i &= ~IBX_ELD_ADDRESS;
7948 I915_WRITE(aud_cntl_st, i);
7949 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
7950 DRM_DEBUG_DRIVER("port num:%d\n", i);
7951
7952 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7953 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7954 for (i = 0; i < len; i++)
7955 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7956
7957 i = I915_READ(aud_cntrl_st2);
7958 i |= eldv;
7959 I915_WRITE(aud_cntrl_st2, i);
7960
7961 }
7962
7963 static void ironlake_write_eld(struct drm_connector *connector,
7964 struct drm_crtc *crtc,
7965 struct drm_display_mode *mode)
7966 {
7967 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7968 uint8_t *eld = connector->eld;
7969 uint32_t eldv;
7970 uint32_t i;
7971 int len;
7972 int hdmiw_hdmiedid;
7973 int aud_config;
7974 int aud_cntl_st;
7975 int aud_cntrl_st2;
7976 int pipe = to_intel_crtc(crtc)->pipe;
7977
7978 if (HAS_PCH_IBX(connector->dev)) {
7979 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7980 aud_config = IBX_AUD_CFG(pipe);
7981 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7982 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7983 } else if (IS_VALLEYVIEW(connector->dev)) {
7984 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7985 aud_config = VLV_AUD_CFG(pipe);
7986 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7987 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7988 } else {
7989 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7990 aud_config = CPT_AUD_CFG(pipe);
7991 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7992 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7993 }
7994
7995 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7996
7997 if (IS_VALLEYVIEW(connector->dev)) {
7998 struct intel_encoder *intel_encoder;
7999 struct intel_digital_port *intel_dig_port;
8000
8001 intel_encoder = intel_attached_encoder(connector);
8002 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
8003 i = intel_dig_port->port;
8004 } else {
8005 i = I915_READ(aud_cntl_st);
8006 i = (i >> 29) & DIP_PORT_SEL_MASK;
8007 /* DIP_Port_Select, 0x1 = PortB */
8008 }
8009
8010 if (!i) {
8011 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
8012 /* operate blindly on all ports */
8013 eldv = IBX_ELD_VALIDB;
8014 eldv |= IBX_ELD_VALIDB << 4;
8015 eldv |= IBX_ELD_VALIDB << 8;
8016 } else {
8017 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
8018 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
8019 }
8020
8021 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
8022 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
8023 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
8024 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
8025 } else {
8026 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
8027 }
8028
8029 if (intel_eld_uptodate(connector,
8030 aud_cntrl_st2, eldv,
8031 aud_cntl_st, IBX_ELD_ADDRESS,
8032 hdmiw_hdmiedid))
8033 return;
8034
8035 i = I915_READ(aud_cntrl_st2);
8036 i &= ~eldv;
8037 I915_WRITE(aud_cntrl_st2, i);
8038
8039 if (!eld[0])
8040 return;
8041
8042 i = I915_READ(aud_cntl_st);
8043 i &= ~IBX_ELD_ADDRESS;
8044 I915_WRITE(aud_cntl_st, i);
8045
8046 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
8047 DRM_DEBUG_DRIVER("ELD size %d\n", len);
8048 for (i = 0; i < len; i++)
8049 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
8050
8051 i = I915_READ(aud_cntrl_st2);
8052 i |= eldv;
8053 I915_WRITE(aud_cntrl_st2, i);
8054 }
8055
8056 void intel_write_eld(struct drm_encoder *encoder,
8057 struct drm_display_mode *mode)
8058 {
8059 struct drm_crtc *crtc = encoder->crtc;
8060 struct drm_connector *connector;
8061 struct drm_device *dev = encoder->dev;
8062 struct drm_i915_private *dev_priv = dev->dev_private;
8063
8064 connector = drm_select_eld(encoder, mode);
8065 if (!connector)
8066 return;
8067
8068 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8069 connector->base.id,
8070 connector->name,
8071 connector->encoder->base.id,
8072 connector->encoder->name);
8073
8074 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
8075
8076 if (dev_priv->display.write_eld)
8077 dev_priv->display.write_eld(connector, crtc, mode);
8078 }
8079
8080 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8081 {
8082 struct drm_device *dev = crtc->dev;
8083 struct drm_i915_private *dev_priv = dev->dev_private;
8084 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8085 uint32_t cntl = 0, size = 0;
8086
8087 if (base) {
8088 unsigned int width = intel_crtc->cursor_width;
8089 unsigned int height = intel_crtc->cursor_height;
8090 unsigned int stride = roundup_pow_of_two(width) * 4;
8091
8092 switch (stride) {
8093 default:
8094 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8095 width, stride);
8096 stride = 256;
8097 /* fallthrough */
8098 case 256:
8099 case 512:
8100 case 1024:
8101 case 2048:
8102 break;
8103 }
8104
8105 cntl |= CURSOR_ENABLE |
8106 CURSOR_GAMMA_ENABLE |
8107 CURSOR_FORMAT_ARGB |
8108 CURSOR_STRIDE(stride);
8109
8110 size = (height << 12) | width;
8111 }
8112
8113 if (intel_crtc->cursor_cntl != 0 &&
8114 (intel_crtc->cursor_base != base ||
8115 intel_crtc->cursor_size != size ||
8116 intel_crtc->cursor_cntl != cntl)) {
8117 /* On these chipsets we can only modify the base/size/stride
8118 * whilst the cursor is disabled.
8119 */
8120 I915_WRITE(_CURACNTR, 0);
8121 POSTING_READ(_CURACNTR);
8122 intel_crtc->cursor_cntl = 0;
8123 }
8124
8125 if (intel_crtc->cursor_base != base)
8126 I915_WRITE(_CURABASE, base);
8127
8128 if (intel_crtc->cursor_size != size) {
8129 I915_WRITE(CURSIZE, size);
8130 intel_crtc->cursor_size = size;
8131 }
8132
8133 if (intel_crtc->cursor_cntl != cntl) {
8134 I915_WRITE(_CURACNTR, cntl);
8135 POSTING_READ(_CURACNTR);
8136 intel_crtc->cursor_cntl = cntl;
8137 }
8138 }
8139
8140 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8141 {
8142 struct drm_device *dev = crtc->dev;
8143 struct drm_i915_private *dev_priv = dev->dev_private;
8144 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8145 int pipe = intel_crtc->pipe;
8146 uint32_t cntl;
8147
8148 cntl = 0;
8149 if (base) {
8150 cntl = MCURSOR_GAMMA_ENABLE;
8151 switch (intel_crtc->cursor_width) {
8152 case 64:
8153 cntl |= CURSOR_MODE_64_ARGB_AX;
8154 break;
8155 case 128:
8156 cntl |= CURSOR_MODE_128_ARGB_AX;
8157 break;
8158 case 256:
8159 cntl |= CURSOR_MODE_256_ARGB_AX;
8160 break;
8161 default:
8162 WARN_ON(1);
8163 return;
8164 }
8165 cntl |= pipe << 28; /* Connect to correct pipe */
8166 }
8167 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8168 cntl |= CURSOR_PIPE_CSC_ENABLE;
8169
8170 if (intel_crtc->cursor_cntl != cntl) {
8171 I915_WRITE(CURCNTR(pipe), cntl);
8172 POSTING_READ(CURCNTR(pipe));
8173 intel_crtc->cursor_cntl = cntl;
8174 }
8175
8176 /* and commit changes on next vblank */
8177 I915_WRITE(CURBASE(pipe), base);
8178 POSTING_READ(CURBASE(pipe));
8179 }
8180
8181 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8182 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8183 bool on)
8184 {
8185 struct drm_device *dev = crtc->dev;
8186 struct drm_i915_private *dev_priv = dev->dev_private;
8187 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8188 int pipe = intel_crtc->pipe;
8189 int x = crtc->cursor_x;
8190 int y = crtc->cursor_y;
8191 u32 base = 0, pos = 0;
8192
8193 if (on)
8194 base = intel_crtc->cursor_addr;
8195
8196 if (x >= intel_crtc->config.pipe_src_w)
8197 base = 0;
8198
8199 if (y >= intel_crtc->config.pipe_src_h)
8200 base = 0;
8201
8202 if (x < 0) {
8203 if (x + intel_crtc->cursor_width <= 0)
8204 base = 0;
8205
8206 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8207 x = -x;
8208 }
8209 pos |= x << CURSOR_X_SHIFT;
8210
8211 if (y < 0) {
8212 if (y + intel_crtc->cursor_height <= 0)
8213 base = 0;
8214
8215 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8216 y = -y;
8217 }
8218 pos |= y << CURSOR_Y_SHIFT;
8219
8220 if (base == 0 && intel_crtc->cursor_base == 0)
8221 return;
8222
8223 I915_WRITE(CURPOS(pipe), pos);
8224
8225 if (IS_845G(dev) || IS_I865G(dev))
8226 i845_update_cursor(crtc, base);
8227 else
8228 i9xx_update_cursor(crtc, base);
8229 intel_crtc->cursor_base = base;
8230 }
8231
8232 static bool cursor_size_ok(struct drm_device *dev,
8233 uint32_t width, uint32_t height)
8234 {
8235 if (width == 0 || height == 0)
8236 return false;
8237
8238 /*
8239 * 845g/865g are special in that they are only limited by
8240 * the width of their cursors, the height is arbitrary up to
8241 * the precision of the register. Everything else requires
8242 * square cursors, limited to a few power-of-two sizes.
8243 */
8244 if (IS_845G(dev) || IS_I865G(dev)) {
8245 if ((width & 63) != 0)
8246 return false;
8247
8248 if (width > (IS_845G(dev) ? 64 : 512))
8249 return false;
8250
8251 if (height > 1023)
8252 return false;
8253 } else {
8254 switch (width | height) {
8255 case 256:
8256 case 128:
8257 if (IS_GEN2(dev))
8258 return false;
8259 case 64:
8260 break;
8261 default:
8262 return false;
8263 }
8264 }
8265
8266 return true;
8267 }
8268
8269 /*
8270 * intel_crtc_cursor_set_obj - Set cursor to specified GEM object
8271 *
8272 * Note that the object's reference will be consumed if the update fails. If
8273 * the update succeeds, the reference of the old object (if any) will be
8274 * consumed.
8275 */
8276 static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8277 struct drm_i915_gem_object *obj,
8278 uint32_t width, uint32_t height)
8279 {
8280 struct drm_device *dev = crtc->dev;
8281 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8282 enum pipe pipe = intel_crtc->pipe;
8283 unsigned old_width, stride;
8284 uint32_t addr;
8285 int ret;
8286
8287 /* if we want to turn off the cursor ignore width and height */
8288 if (!obj) {
8289 DRM_DEBUG_KMS("cursor off\n");
8290 addr = 0;
8291 obj = NULL;
8292 mutex_lock(&dev->struct_mutex);
8293 goto finish;
8294 }
8295
8296 /* Check for which cursor types we support */
8297 if (!cursor_size_ok(dev, width, height)) {
8298 DRM_DEBUG("Cursor dimension not supported\n");
8299 return -EINVAL;
8300 }
8301
8302 stride = roundup_pow_of_two(width) * 4;
8303 if (obj->base.size < stride * height) {
8304 DRM_DEBUG_KMS("buffer is too small\n");
8305 ret = -ENOMEM;
8306 goto fail;
8307 }
8308
8309 /* we only need to pin inside GTT if cursor is non-phy */
8310 mutex_lock(&dev->struct_mutex);
8311 if (!INTEL_INFO(dev)->cursor_needs_physical) {
8312 unsigned alignment;
8313
8314 if (obj->tiling_mode) {
8315 DRM_DEBUG_KMS("cursor cannot be tiled\n");
8316 ret = -EINVAL;
8317 goto fail_locked;
8318 }
8319
8320 /* Note that the w/a also requires 2 PTE of padding following
8321 * the bo. We currently fill all unused PTE with the shadow
8322 * page and so we should always have valid PTE following the
8323 * cursor preventing the VT-d warning.
8324 */
8325 alignment = 0;
8326 if (need_vtd_wa(dev))
8327 alignment = 64*1024;
8328
8329 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8330 if (ret) {
8331 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8332 goto fail_locked;
8333 }
8334
8335 ret = i915_gem_object_put_fence(obj);
8336 if (ret) {
8337 DRM_DEBUG_KMS("failed to release fence for cursor");
8338 goto fail_unpin;
8339 }
8340
8341 addr = i915_gem_obj_ggtt_offset(obj);
8342 } else {
8343 int align = IS_I830(dev) ? 16 * 1024 : 256;
8344 ret = i915_gem_object_attach_phys(obj, align);
8345 if (ret) {
8346 DRM_DEBUG_KMS("failed to attach phys object\n");
8347 goto fail_locked;
8348 }
8349 addr = obj->phys_handle->busaddr;
8350 }
8351
8352 finish:
8353 if (intel_crtc->cursor_bo) {
8354 if (!INTEL_INFO(dev)->cursor_needs_physical)
8355 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8356 }
8357
8358 i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8359 INTEL_FRONTBUFFER_CURSOR(pipe));
8360 mutex_unlock(&dev->struct_mutex);
8361
8362 old_width = intel_crtc->cursor_width;
8363
8364 intel_crtc->cursor_addr = addr;
8365 intel_crtc->cursor_bo = obj;
8366 intel_crtc->cursor_width = width;
8367 intel_crtc->cursor_height = height;
8368
8369 if (intel_crtc->active) {
8370 if (old_width != width)
8371 intel_update_watermarks(crtc);
8372 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8373 }
8374
8375 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
8376
8377 return 0;
8378 fail_unpin:
8379 i915_gem_object_unpin_from_display_plane(obj);
8380 fail_locked:
8381 mutex_unlock(&dev->struct_mutex);
8382 fail:
8383 drm_gem_object_unreference_unlocked(&obj->base);
8384 return ret;
8385 }
8386
8387 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8388 u16 *blue, uint32_t start, uint32_t size)
8389 {
8390 int end = (start + size > 256) ? 256 : start + size, i;
8391 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8392
8393 for (i = start; i < end; i++) {
8394 intel_crtc->lut_r[i] = red[i] >> 8;
8395 intel_crtc->lut_g[i] = green[i] >> 8;
8396 intel_crtc->lut_b[i] = blue[i] >> 8;
8397 }
8398
8399 intel_crtc_load_lut(crtc);
8400 }
8401
8402 /* VESA 640x480x72Hz mode to set on the pipe */
8403 static struct drm_display_mode load_detect_mode = {
8404 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8405 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8406 };
8407
8408 struct drm_framebuffer *
8409 __intel_framebuffer_create(struct drm_device *dev,
8410 struct drm_mode_fb_cmd2 *mode_cmd,
8411 struct drm_i915_gem_object *obj)
8412 {
8413 struct intel_framebuffer *intel_fb;
8414 int ret;
8415
8416 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8417 if (!intel_fb) {
8418 drm_gem_object_unreference_unlocked(&obj->base);
8419 return ERR_PTR(-ENOMEM);
8420 }
8421
8422 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8423 if (ret)
8424 goto err;
8425
8426 return &intel_fb->base;
8427 err:
8428 drm_gem_object_unreference_unlocked(&obj->base);
8429 kfree(intel_fb);
8430
8431 return ERR_PTR(ret);
8432 }
8433
8434 static struct drm_framebuffer *
8435 intel_framebuffer_create(struct drm_device *dev,
8436 struct drm_mode_fb_cmd2 *mode_cmd,
8437 struct drm_i915_gem_object *obj)
8438 {
8439 struct drm_framebuffer *fb;
8440 int ret;
8441
8442 ret = i915_mutex_lock_interruptible(dev);
8443 if (ret)
8444 return ERR_PTR(ret);
8445 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8446 mutex_unlock(&dev->struct_mutex);
8447
8448 return fb;
8449 }
8450
8451 static u32
8452 intel_framebuffer_pitch_for_width(int width, int bpp)
8453 {
8454 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8455 return ALIGN(pitch, 64);
8456 }
8457
8458 static u32
8459 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8460 {
8461 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8462 return PAGE_ALIGN(pitch * mode->vdisplay);
8463 }
8464
8465 static struct drm_framebuffer *
8466 intel_framebuffer_create_for_mode(struct drm_device *dev,
8467 struct drm_display_mode *mode,
8468 int depth, int bpp)
8469 {
8470 struct drm_i915_gem_object *obj;
8471 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8472
8473 obj = i915_gem_alloc_object(dev,
8474 intel_framebuffer_size_for_mode(mode, bpp));
8475 if (obj == NULL)
8476 return ERR_PTR(-ENOMEM);
8477
8478 mode_cmd.width = mode->hdisplay;
8479 mode_cmd.height = mode->vdisplay;
8480 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8481 bpp);
8482 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8483
8484 return intel_framebuffer_create(dev, &mode_cmd, obj);
8485 }
8486
8487 static struct drm_framebuffer *
8488 mode_fits_in_fbdev(struct drm_device *dev,
8489 struct drm_display_mode *mode)
8490 {
8491 #ifdef CONFIG_DRM_I915_FBDEV
8492 struct drm_i915_private *dev_priv = dev->dev_private;
8493 struct drm_i915_gem_object *obj;
8494 struct drm_framebuffer *fb;
8495
8496 if (!dev_priv->fbdev)
8497 return NULL;
8498
8499 if (!dev_priv->fbdev->fb)
8500 return NULL;
8501
8502 obj = dev_priv->fbdev->fb->obj;
8503 BUG_ON(!obj);
8504
8505 fb = &dev_priv->fbdev->fb->base;
8506 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8507 fb->bits_per_pixel))
8508 return NULL;
8509
8510 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8511 return NULL;
8512
8513 return fb;
8514 #else
8515 return NULL;
8516 #endif
8517 }
8518
8519 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8520 struct drm_display_mode *mode,
8521 struct intel_load_detect_pipe *old,
8522 struct drm_modeset_acquire_ctx *ctx)
8523 {
8524 struct intel_crtc *intel_crtc;
8525 struct intel_encoder *intel_encoder =
8526 intel_attached_encoder(connector);
8527 struct drm_crtc *possible_crtc;
8528 struct drm_encoder *encoder = &intel_encoder->base;
8529 struct drm_crtc *crtc = NULL;
8530 struct drm_device *dev = encoder->dev;
8531 struct drm_framebuffer *fb;
8532 struct drm_mode_config *config = &dev->mode_config;
8533 int ret, i = -1;
8534
8535 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8536 connector->base.id, connector->name,
8537 encoder->base.id, encoder->name);
8538
8539 retry:
8540 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8541 if (ret)
8542 goto fail_unlock;
8543
8544 /*
8545 * Algorithm gets a little messy:
8546 *
8547 * - if the connector already has an assigned crtc, use it (but make
8548 * sure it's on first)
8549 *
8550 * - try to find the first unused crtc that can drive this connector,
8551 * and use that if we find one
8552 */
8553
8554 /* See if we already have a CRTC for this connector */
8555 if (encoder->crtc) {
8556 crtc = encoder->crtc;
8557
8558 ret = drm_modeset_lock(&crtc->mutex, ctx);
8559 if (ret)
8560 goto fail_unlock;
8561
8562 old->dpms_mode = connector->dpms;
8563 old->load_detect_temp = false;
8564
8565 /* Make sure the crtc and connector are running */
8566 if (connector->dpms != DRM_MODE_DPMS_ON)
8567 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8568
8569 return true;
8570 }
8571
8572 /* Find an unused one (if possible) */
8573 for_each_crtc(dev, possible_crtc) {
8574 i++;
8575 if (!(encoder->possible_crtcs & (1 << i)))
8576 continue;
8577 if (possible_crtc->enabled)
8578 continue;
8579 /* This can occur when applying the pipe A quirk on resume. */
8580 if (to_intel_crtc(possible_crtc)->new_enabled)
8581 continue;
8582
8583 crtc = possible_crtc;
8584 break;
8585 }
8586
8587 /*
8588 * If we didn't find an unused CRTC, don't use any.
8589 */
8590 if (!crtc) {
8591 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8592 goto fail_unlock;
8593 }
8594
8595 ret = drm_modeset_lock(&crtc->mutex, ctx);
8596 if (ret)
8597 goto fail_unlock;
8598 intel_encoder->new_crtc = to_intel_crtc(crtc);
8599 to_intel_connector(connector)->new_encoder = intel_encoder;
8600
8601 intel_crtc = to_intel_crtc(crtc);
8602 intel_crtc->new_enabled = true;
8603 intel_crtc->new_config = &intel_crtc->config;
8604 old->dpms_mode = connector->dpms;
8605 old->load_detect_temp = true;
8606 old->release_fb = NULL;
8607
8608 if (!mode)
8609 mode = &load_detect_mode;
8610
8611 /* We need a framebuffer large enough to accommodate all accesses
8612 * that the plane may generate whilst we perform load detection.
8613 * We can not rely on the fbcon either being present (we get called
8614 * during its initialisation to detect all boot displays, or it may
8615 * not even exist) or that it is large enough to satisfy the
8616 * requested mode.
8617 */
8618 fb = mode_fits_in_fbdev(dev, mode);
8619 if (fb == NULL) {
8620 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8621 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8622 old->release_fb = fb;
8623 } else
8624 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8625 if (IS_ERR(fb)) {
8626 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8627 goto fail;
8628 }
8629
8630 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8631 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8632 if (old->release_fb)
8633 old->release_fb->funcs->destroy(old->release_fb);
8634 goto fail;
8635 }
8636
8637 /* let the connector get through one full cycle before testing */
8638 intel_wait_for_vblank(dev, intel_crtc->pipe);
8639 return true;
8640
8641 fail:
8642 intel_crtc->new_enabled = crtc->enabled;
8643 if (intel_crtc->new_enabled)
8644 intel_crtc->new_config = &intel_crtc->config;
8645 else
8646 intel_crtc->new_config = NULL;
8647 fail_unlock:
8648 if (ret == -EDEADLK) {
8649 drm_modeset_backoff(ctx);
8650 goto retry;
8651 }
8652
8653 return false;
8654 }
8655
8656 void intel_release_load_detect_pipe(struct drm_connector *connector,
8657 struct intel_load_detect_pipe *old)
8658 {
8659 struct intel_encoder *intel_encoder =
8660 intel_attached_encoder(connector);
8661 struct drm_encoder *encoder = &intel_encoder->base;
8662 struct drm_crtc *crtc = encoder->crtc;
8663 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8664
8665 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8666 connector->base.id, connector->name,
8667 encoder->base.id, encoder->name);
8668
8669 if (old->load_detect_temp) {
8670 to_intel_connector(connector)->new_encoder = NULL;
8671 intel_encoder->new_crtc = NULL;
8672 intel_crtc->new_enabled = false;
8673 intel_crtc->new_config = NULL;
8674 intel_set_mode(crtc, NULL, 0, 0, NULL);
8675
8676 if (old->release_fb) {
8677 drm_framebuffer_unregister_private(old->release_fb);
8678 drm_framebuffer_unreference(old->release_fb);
8679 }
8680
8681 return;
8682 }
8683
8684 /* Switch crtc and encoder back off if necessary */
8685 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8686 connector->funcs->dpms(connector, old->dpms_mode);
8687 }
8688
8689 static int i9xx_pll_refclk(struct drm_device *dev,
8690 const struct intel_crtc_config *pipe_config)
8691 {
8692 struct drm_i915_private *dev_priv = dev->dev_private;
8693 u32 dpll = pipe_config->dpll_hw_state.dpll;
8694
8695 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8696 return dev_priv->vbt.lvds_ssc_freq;
8697 else if (HAS_PCH_SPLIT(dev))
8698 return 120000;
8699 else if (!IS_GEN2(dev))
8700 return 96000;
8701 else
8702 return 48000;
8703 }
8704
8705 /* Returns the clock of the currently programmed mode of the given pipe. */
8706 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8707 struct intel_crtc_config *pipe_config)
8708 {
8709 struct drm_device *dev = crtc->base.dev;
8710 struct drm_i915_private *dev_priv = dev->dev_private;
8711 int pipe = pipe_config->cpu_transcoder;
8712 u32 dpll = pipe_config->dpll_hw_state.dpll;
8713 u32 fp;
8714 intel_clock_t clock;
8715 int refclk = i9xx_pll_refclk(dev, pipe_config);
8716
8717 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8718 fp = pipe_config->dpll_hw_state.fp0;
8719 else
8720 fp = pipe_config->dpll_hw_state.fp1;
8721
8722 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8723 if (IS_PINEVIEW(dev)) {
8724 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8725 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8726 } else {
8727 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8728 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8729 }
8730
8731 if (!IS_GEN2(dev)) {
8732 if (IS_PINEVIEW(dev))
8733 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8734 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8735 else
8736 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8737 DPLL_FPA01_P1_POST_DIV_SHIFT);
8738
8739 switch (dpll & DPLL_MODE_MASK) {
8740 case DPLLB_MODE_DAC_SERIAL:
8741 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8742 5 : 10;
8743 break;
8744 case DPLLB_MODE_LVDS:
8745 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8746 7 : 14;
8747 break;
8748 default:
8749 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8750 "mode\n", (int)(dpll & DPLL_MODE_MASK));
8751 return;
8752 }
8753
8754 if (IS_PINEVIEW(dev))
8755 pineview_clock(refclk, &clock);
8756 else
8757 i9xx_clock(refclk, &clock);
8758 } else {
8759 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8760 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8761
8762 if (is_lvds) {
8763 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8764 DPLL_FPA01_P1_POST_DIV_SHIFT);
8765
8766 if (lvds & LVDS_CLKB_POWER_UP)
8767 clock.p2 = 7;
8768 else
8769 clock.p2 = 14;
8770 } else {
8771 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8772 clock.p1 = 2;
8773 else {
8774 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8775 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8776 }
8777 if (dpll & PLL_P2_DIVIDE_BY_4)
8778 clock.p2 = 4;
8779 else
8780 clock.p2 = 2;
8781 }
8782
8783 i9xx_clock(refclk, &clock);
8784 }
8785
8786 /*
8787 * This value includes pixel_multiplier. We will use
8788 * port_clock to compute adjusted_mode.crtc_clock in the
8789 * encoder's get_config() function.
8790 */
8791 pipe_config->port_clock = clock.dot;
8792 }
8793
8794 int intel_dotclock_calculate(int link_freq,
8795 const struct intel_link_m_n *m_n)
8796 {
8797 /*
8798 * The calculation for the data clock is:
8799 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8800 * But we want to avoid losing precison if possible, so:
8801 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8802 *
8803 * and the link clock is simpler:
8804 * link_clock = (m * link_clock) / n
8805 */
8806
8807 if (!m_n->link_n)
8808 return 0;
8809
8810 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8811 }
8812
8813 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8814 struct intel_crtc_config *pipe_config)
8815 {
8816 struct drm_device *dev = crtc->base.dev;
8817
8818 /* read out port_clock from the DPLL */
8819 i9xx_crtc_clock_get(crtc, pipe_config);
8820
8821 /*
8822 * This value does not include pixel_multiplier.
8823 * We will check that port_clock and adjusted_mode.crtc_clock
8824 * agree once we know their relationship in the encoder's
8825 * get_config() function.
8826 */
8827 pipe_config->adjusted_mode.crtc_clock =
8828 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8829 &pipe_config->fdi_m_n);
8830 }
8831
8832 /** Returns the currently programmed mode of the given pipe. */
8833 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8834 struct drm_crtc *crtc)
8835 {
8836 struct drm_i915_private *dev_priv = dev->dev_private;
8837 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8838 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8839 struct drm_display_mode *mode;
8840 struct intel_crtc_config pipe_config;
8841 int htot = I915_READ(HTOTAL(cpu_transcoder));
8842 int hsync = I915_READ(HSYNC(cpu_transcoder));
8843 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8844 int vsync = I915_READ(VSYNC(cpu_transcoder));
8845 enum pipe pipe = intel_crtc->pipe;
8846
8847 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8848 if (!mode)
8849 return NULL;
8850
8851 /*
8852 * Construct a pipe_config sufficient for getting the clock info
8853 * back out of crtc_clock_get.
8854 *
8855 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8856 * to use a real value here instead.
8857 */
8858 pipe_config.cpu_transcoder = (enum transcoder) pipe;
8859 pipe_config.pixel_multiplier = 1;
8860 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8861 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8862 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8863 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8864
8865 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8866 mode->hdisplay = (htot & 0xffff) + 1;
8867 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8868 mode->hsync_start = (hsync & 0xffff) + 1;
8869 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8870 mode->vdisplay = (vtot & 0xffff) + 1;
8871 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8872 mode->vsync_start = (vsync & 0xffff) + 1;
8873 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8874
8875 drm_mode_set_name(mode);
8876
8877 return mode;
8878 }
8879
8880 static void intel_increase_pllclock(struct drm_device *dev,
8881 enum pipe pipe)
8882 {
8883 struct drm_i915_private *dev_priv = dev->dev_private;
8884 int dpll_reg = DPLL(pipe);
8885 int dpll;
8886
8887 if (!HAS_GMCH_DISPLAY(dev))
8888 return;
8889
8890 if (!dev_priv->lvds_downclock_avail)
8891 return;
8892
8893 dpll = I915_READ(dpll_reg);
8894 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8895 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8896
8897 assert_panel_unlocked(dev_priv, pipe);
8898
8899 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8900 I915_WRITE(dpll_reg, dpll);
8901 intel_wait_for_vblank(dev, pipe);
8902
8903 dpll = I915_READ(dpll_reg);
8904 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8905 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8906 }
8907 }
8908
8909 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8910 {
8911 struct drm_device *dev = crtc->dev;
8912 struct drm_i915_private *dev_priv = dev->dev_private;
8913 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8914
8915 if (!HAS_GMCH_DISPLAY(dev))
8916 return;
8917
8918 if (!dev_priv->lvds_downclock_avail)
8919 return;
8920
8921 /*
8922 * Since this is called by a timer, we should never get here in
8923 * the manual case.
8924 */
8925 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8926 int pipe = intel_crtc->pipe;
8927 int dpll_reg = DPLL(pipe);
8928 int dpll;
8929
8930 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8931
8932 assert_panel_unlocked(dev_priv, pipe);
8933
8934 dpll = I915_READ(dpll_reg);
8935 dpll |= DISPLAY_RATE_SELECT_FPA1;
8936 I915_WRITE(dpll_reg, dpll);
8937 intel_wait_for_vblank(dev, pipe);
8938 dpll = I915_READ(dpll_reg);
8939 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8940 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8941 }
8942
8943 }
8944
8945 void intel_mark_busy(struct drm_device *dev)
8946 {
8947 struct drm_i915_private *dev_priv = dev->dev_private;
8948
8949 if (dev_priv->mm.busy)
8950 return;
8951
8952 intel_runtime_pm_get(dev_priv);
8953 i915_update_gfx_val(dev_priv);
8954 dev_priv->mm.busy = true;
8955 }
8956
8957 void intel_mark_idle(struct drm_device *dev)
8958 {
8959 struct drm_i915_private *dev_priv = dev->dev_private;
8960 struct drm_crtc *crtc;
8961
8962 if (!dev_priv->mm.busy)
8963 return;
8964
8965 dev_priv->mm.busy = false;
8966
8967 if (!i915.powersave)
8968 goto out;
8969
8970 for_each_crtc(dev, crtc) {
8971 if (!crtc->primary->fb)
8972 continue;
8973
8974 intel_decrease_pllclock(crtc);
8975 }
8976
8977 if (INTEL_INFO(dev)->gen >= 6)
8978 gen6_rps_idle(dev->dev_private);
8979
8980 out:
8981 intel_runtime_pm_put(dev_priv);
8982 }
8983
8984
8985 /**
8986 * intel_mark_fb_busy - mark given planes as busy
8987 * @dev: DRM device
8988 * @frontbuffer_bits: bits for the affected planes
8989 * @ring: optional ring for asynchronous commands
8990 *
8991 * This function gets called every time the screen contents change. It can be
8992 * used to keep e.g. the update rate at the nominal refresh rate with DRRS.
8993 */
8994 static void intel_mark_fb_busy(struct drm_device *dev,
8995 unsigned frontbuffer_bits,
8996 struct intel_engine_cs *ring)
8997 {
8998 struct drm_i915_private *dev_priv = dev->dev_private;
8999 enum pipe pipe;
9000
9001 if (!i915.powersave)
9002 return;
9003
9004 for_each_pipe(dev_priv, pipe) {
9005 if (!(frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe)))
9006 continue;
9007
9008 intel_increase_pllclock(dev, pipe);
9009 if (ring && intel_fbc_enabled(dev))
9010 ring->fbc_dirty = true;
9011 }
9012 }
9013
9014 /**
9015 * intel_fb_obj_invalidate - invalidate frontbuffer object
9016 * @obj: GEM object to invalidate
9017 * @ring: set for asynchronous rendering
9018 *
9019 * This function gets called every time rendering on the given object starts and
9020 * frontbuffer caching (fbc, low refresh rate for DRRS, panel self refresh) must
9021 * be invalidated. If @ring is non-NULL any subsequent invalidation will be delayed
9022 * until the rendering completes or a flip on this frontbuffer plane is
9023 * scheduled.
9024 */
9025 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
9026 struct intel_engine_cs *ring)
9027 {
9028 struct drm_device *dev = obj->base.dev;
9029 struct drm_i915_private *dev_priv = dev->dev_private;
9030
9031 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
9032
9033 if (!obj->frontbuffer_bits)
9034 return;
9035
9036 if (ring) {
9037 mutex_lock(&dev_priv->fb_tracking.lock);
9038 dev_priv->fb_tracking.busy_bits
9039 |= obj->frontbuffer_bits;
9040 dev_priv->fb_tracking.flip_bits
9041 &= ~obj->frontbuffer_bits;
9042 mutex_unlock(&dev_priv->fb_tracking.lock);
9043 }
9044
9045 intel_mark_fb_busy(dev, obj->frontbuffer_bits, ring);
9046
9047 intel_edp_psr_invalidate(dev, obj->frontbuffer_bits);
9048 }
9049
9050 /**
9051 * intel_frontbuffer_flush - flush frontbuffer
9052 * @dev: DRM device
9053 * @frontbuffer_bits: frontbuffer plane tracking bits
9054 *
9055 * This function gets called every time rendering on the given planes has
9056 * completed and frontbuffer caching can be started again. Flushes will get
9057 * delayed if they're blocked by some oustanding asynchronous rendering.
9058 *
9059 * Can be called without any locks held.
9060 */
9061 void intel_frontbuffer_flush(struct drm_device *dev,
9062 unsigned frontbuffer_bits)
9063 {
9064 struct drm_i915_private *dev_priv = dev->dev_private;
9065
9066 /* Delay flushing when rings are still busy.*/
9067 mutex_lock(&dev_priv->fb_tracking.lock);
9068 frontbuffer_bits &= ~dev_priv->fb_tracking.busy_bits;
9069 mutex_unlock(&dev_priv->fb_tracking.lock);
9070
9071 intel_mark_fb_busy(dev, frontbuffer_bits, NULL);
9072
9073 intel_edp_psr_flush(dev, frontbuffer_bits);
9074 }
9075
9076 /**
9077 * intel_fb_obj_flush - flush frontbuffer object
9078 * @obj: GEM object to flush
9079 * @retire: set when retiring asynchronous rendering
9080 *
9081 * This function gets called every time rendering on the given object has
9082 * completed and frontbuffer caching can be started again. If @retire is true
9083 * then any delayed flushes will be unblocked.
9084 */
9085 void intel_fb_obj_flush(struct drm_i915_gem_object *obj,
9086 bool retire)
9087 {
9088 struct drm_device *dev = obj->base.dev;
9089 struct drm_i915_private *dev_priv = dev->dev_private;
9090 unsigned frontbuffer_bits;
9091
9092 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
9093
9094 if (!obj->frontbuffer_bits)
9095 return;
9096
9097 frontbuffer_bits = obj->frontbuffer_bits;
9098
9099 if (retire) {
9100 mutex_lock(&dev_priv->fb_tracking.lock);
9101 /* Filter out new bits since rendering started. */
9102 frontbuffer_bits &= dev_priv->fb_tracking.busy_bits;
9103
9104 dev_priv->fb_tracking.busy_bits &= ~frontbuffer_bits;
9105 mutex_unlock(&dev_priv->fb_tracking.lock);
9106 }
9107
9108 intel_frontbuffer_flush(dev, frontbuffer_bits);
9109 }
9110
9111 /**
9112 * intel_frontbuffer_flip_prepare - prepare asnychronous frontbuffer flip
9113 * @dev: DRM device
9114 * @frontbuffer_bits: frontbuffer plane tracking bits
9115 *
9116 * This function gets called after scheduling a flip on @obj. The actual
9117 * frontbuffer flushing will be delayed until completion is signalled with
9118 * intel_frontbuffer_flip_complete. If an invalidate happens in between this
9119 * flush will be cancelled.
9120 *
9121 * Can be called without any locks held.
9122 */
9123 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
9124 unsigned frontbuffer_bits)
9125 {
9126 struct drm_i915_private *dev_priv = dev->dev_private;
9127
9128 mutex_lock(&dev_priv->fb_tracking.lock);
9129 dev_priv->fb_tracking.flip_bits
9130 |= frontbuffer_bits;
9131 mutex_unlock(&dev_priv->fb_tracking.lock);
9132 }
9133
9134 /**
9135 * intel_frontbuffer_flip_complete - complete asynchronous frontbuffer flush
9136 * @dev: DRM device
9137 * @frontbuffer_bits: frontbuffer plane tracking bits
9138 *
9139 * This function gets called after the flip has been latched and will complete
9140 * on the next vblank. It will execute the fush if it hasn't been cancalled yet.
9141 *
9142 * Can be called without any locks held.
9143 */
9144 void intel_frontbuffer_flip_complete(struct drm_device *dev,
9145 unsigned frontbuffer_bits)
9146 {
9147 struct drm_i915_private *dev_priv = dev->dev_private;
9148
9149 mutex_lock(&dev_priv->fb_tracking.lock);
9150 /* Mask any cancelled flips. */
9151 frontbuffer_bits &= dev_priv->fb_tracking.flip_bits;
9152 dev_priv->fb_tracking.flip_bits &= ~frontbuffer_bits;
9153 mutex_unlock(&dev_priv->fb_tracking.lock);
9154
9155 intel_frontbuffer_flush(dev, frontbuffer_bits);
9156 }
9157
9158 static void intel_crtc_destroy(struct drm_crtc *crtc)
9159 {
9160 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9161 struct drm_device *dev = crtc->dev;
9162 struct intel_unpin_work *work;
9163 unsigned long flags;
9164
9165 spin_lock_irqsave(&dev->event_lock, flags);
9166 work = intel_crtc->unpin_work;
9167 intel_crtc->unpin_work = NULL;
9168 spin_unlock_irqrestore(&dev->event_lock, flags);
9169
9170 if (work) {
9171 cancel_work_sync(&work->work);
9172 kfree(work);
9173 }
9174
9175 drm_crtc_cleanup(crtc);
9176
9177 kfree(intel_crtc);
9178 }
9179
9180 static void intel_unpin_work_fn(struct work_struct *__work)
9181 {
9182 struct intel_unpin_work *work =
9183 container_of(__work, struct intel_unpin_work, work);
9184 struct drm_device *dev = work->crtc->dev;
9185 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9186
9187 mutex_lock(&dev->struct_mutex);
9188 intel_unpin_fb_obj(work->old_fb_obj);
9189 drm_gem_object_unreference(&work->pending_flip_obj->base);
9190 drm_gem_object_unreference(&work->old_fb_obj->base);
9191
9192 intel_update_fbc(dev);
9193 mutex_unlock(&dev->struct_mutex);
9194
9195 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9196
9197 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9198 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9199
9200 kfree(work);
9201 }
9202
9203 static void do_intel_finish_page_flip(struct drm_device *dev,
9204 struct drm_crtc *crtc)
9205 {
9206 struct drm_i915_private *dev_priv = dev->dev_private;
9207 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9208 struct intel_unpin_work *work;
9209 unsigned long flags;
9210
9211 /* Ignore early vblank irqs */
9212 if (intel_crtc == NULL)
9213 return;
9214
9215 spin_lock_irqsave(&dev->event_lock, flags);
9216 work = intel_crtc->unpin_work;
9217
9218 /* Ensure we don't miss a work->pending update ... */
9219 smp_rmb();
9220
9221 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9222 spin_unlock_irqrestore(&dev->event_lock, flags);
9223 return;
9224 }
9225
9226 /* and that the unpin work is consistent wrt ->pending. */
9227 smp_rmb();
9228
9229 intel_crtc->unpin_work = NULL;
9230
9231 if (work->event)
9232 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
9233
9234 drm_crtc_vblank_put(crtc);
9235
9236 spin_unlock_irqrestore(&dev->event_lock, flags);
9237
9238 wake_up_all(&dev_priv->pending_flip_queue);
9239
9240 queue_work(dev_priv->wq, &work->work);
9241
9242 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
9243 }
9244
9245 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9246 {
9247 struct drm_i915_private *dev_priv = dev->dev_private;
9248 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9249
9250 do_intel_finish_page_flip(dev, crtc);
9251 }
9252
9253 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9254 {
9255 struct drm_i915_private *dev_priv = dev->dev_private;
9256 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9257
9258 do_intel_finish_page_flip(dev, crtc);
9259 }
9260
9261 /* Is 'a' after or equal to 'b'? */
9262 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9263 {
9264 return !((a - b) & 0x80000000);
9265 }
9266
9267 static bool page_flip_finished(struct intel_crtc *crtc)
9268 {
9269 struct drm_device *dev = crtc->base.dev;
9270 struct drm_i915_private *dev_priv = dev->dev_private;
9271
9272 /*
9273 * The relevant registers doen't exist on pre-ctg.
9274 * As the flip done interrupt doesn't trigger for mmio
9275 * flips on gmch platforms, a flip count check isn't
9276 * really needed there. But since ctg has the registers,
9277 * include it in the check anyway.
9278 */
9279 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9280 return true;
9281
9282 /*
9283 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9284 * used the same base address. In that case the mmio flip might
9285 * have completed, but the CS hasn't even executed the flip yet.
9286 *
9287 * A flip count check isn't enough as the CS might have updated
9288 * the base address just after start of vblank, but before we
9289 * managed to process the interrupt. This means we'd complete the
9290 * CS flip too soon.
9291 *
9292 * Combining both checks should get us a good enough result. It may
9293 * still happen that the CS flip has been executed, but has not
9294 * yet actually completed. But in case the base address is the same
9295 * anyway, we don't really care.
9296 */
9297 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9298 crtc->unpin_work->gtt_offset &&
9299 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9300 crtc->unpin_work->flip_count);
9301 }
9302
9303 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9304 {
9305 struct drm_i915_private *dev_priv = dev->dev_private;
9306 struct intel_crtc *intel_crtc =
9307 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9308 unsigned long flags;
9309
9310 /* NB: An MMIO update of the plane base pointer will also
9311 * generate a page-flip completion irq, i.e. every modeset
9312 * is also accompanied by a spurious intel_prepare_page_flip().
9313 */
9314 spin_lock_irqsave(&dev->event_lock, flags);
9315 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9316 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9317 spin_unlock_irqrestore(&dev->event_lock, flags);
9318 }
9319
9320 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9321 {
9322 /* Ensure that the work item is consistent when activating it ... */
9323 smp_wmb();
9324 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9325 /* and that it is marked active as soon as the irq could fire. */
9326 smp_wmb();
9327 }
9328
9329 static int intel_gen2_queue_flip(struct drm_device *dev,
9330 struct drm_crtc *crtc,
9331 struct drm_framebuffer *fb,
9332 struct drm_i915_gem_object *obj,
9333 struct intel_engine_cs *ring,
9334 uint32_t flags)
9335 {
9336 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9337 u32 flip_mask;
9338 int ret;
9339
9340 ret = intel_ring_begin(ring, 6);
9341 if (ret)
9342 return ret;
9343
9344 /* Can't queue multiple flips, so wait for the previous
9345 * one to finish before executing the next.
9346 */
9347 if (intel_crtc->plane)
9348 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9349 else
9350 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9351 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9352 intel_ring_emit(ring, MI_NOOP);
9353 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9354 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9355 intel_ring_emit(ring, fb->pitches[0]);
9356 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9357 intel_ring_emit(ring, 0); /* aux display base address, unused */
9358
9359 intel_mark_page_flip_active(intel_crtc);
9360 __intel_ring_advance(ring);
9361 return 0;
9362 }
9363
9364 static int intel_gen3_queue_flip(struct drm_device *dev,
9365 struct drm_crtc *crtc,
9366 struct drm_framebuffer *fb,
9367 struct drm_i915_gem_object *obj,
9368 struct intel_engine_cs *ring,
9369 uint32_t flags)
9370 {
9371 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9372 u32 flip_mask;
9373 int ret;
9374
9375 ret = intel_ring_begin(ring, 6);
9376 if (ret)
9377 return ret;
9378
9379 if (intel_crtc->plane)
9380 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9381 else
9382 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9383 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9384 intel_ring_emit(ring, MI_NOOP);
9385 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9386 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9387 intel_ring_emit(ring, fb->pitches[0]);
9388 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9389 intel_ring_emit(ring, MI_NOOP);
9390
9391 intel_mark_page_flip_active(intel_crtc);
9392 __intel_ring_advance(ring);
9393 return 0;
9394 }
9395
9396 static int intel_gen4_queue_flip(struct drm_device *dev,
9397 struct drm_crtc *crtc,
9398 struct drm_framebuffer *fb,
9399 struct drm_i915_gem_object *obj,
9400 struct intel_engine_cs *ring,
9401 uint32_t flags)
9402 {
9403 struct drm_i915_private *dev_priv = dev->dev_private;
9404 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9405 uint32_t pf, pipesrc;
9406 int ret;
9407
9408 ret = intel_ring_begin(ring, 4);
9409 if (ret)
9410 return ret;
9411
9412 /* i965+ uses the linear or tiled offsets from the
9413 * Display Registers (which do not change across a page-flip)
9414 * so we need only reprogram the base address.
9415 */
9416 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9417 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9418 intel_ring_emit(ring, fb->pitches[0]);
9419 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9420 obj->tiling_mode);
9421
9422 /* XXX Enabling the panel-fitter across page-flip is so far
9423 * untested on non-native modes, so ignore it for now.
9424 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9425 */
9426 pf = 0;
9427 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9428 intel_ring_emit(ring, pf | pipesrc);
9429
9430 intel_mark_page_flip_active(intel_crtc);
9431 __intel_ring_advance(ring);
9432 return 0;
9433 }
9434
9435 static int intel_gen6_queue_flip(struct drm_device *dev,
9436 struct drm_crtc *crtc,
9437 struct drm_framebuffer *fb,
9438 struct drm_i915_gem_object *obj,
9439 struct intel_engine_cs *ring,
9440 uint32_t flags)
9441 {
9442 struct drm_i915_private *dev_priv = dev->dev_private;
9443 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9444 uint32_t pf, pipesrc;
9445 int ret;
9446
9447 ret = intel_ring_begin(ring, 4);
9448 if (ret)
9449 return ret;
9450
9451 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9452 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9453 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9454 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9455
9456 /* Contrary to the suggestions in the documentation,
9457 * "Enable Panel Fitter" does not seem to be required when page
9458 * flipping with a non-native mode, and worse causes a normal
9459 * modeset to fail.
9460 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9461 */
9462 pf = 0;
9463 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9464 intel_ring_emit(ring, pf | pipesrc);
9465
9466 intel_mark_page_flip_active(intel_crtc);
9467 __intel_ring_advance(ring);
9468 return 0;
9469 }
9470
9471 static int intel_gen7_queue_flip(struct drm_device *dev,
9472 struct drm_crtc *crtc,
9473 struct drm_framebuffer *fb,
9474 struct drm_i915_gem_object *obj,
9475 struct intel_engine_cs *ring,
9476 uint32_t flags)
9477 {
9478 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9479 uint32_t plane_bit = 0;
9480 int len, ret;
9481
9482 switch (intel_crtc->plane) {
9483 case PLANE_A:
9484 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9485 break;
9486 case PLANE_B:
9487 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9488 break;
9489 case PLANE_C:
9490 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9491 break;
9492 default:
9493 WARN_ONCE(1, "unknown plane in flip command\n");
9494 return -ENODEV;
9495 }
9496
9497 len = 4;
9498 if (ring->id == RCS) {
9499 len += 6;
9500 /*
9501 * On Gen 8, SRM is now taking an extra dword to accommodate
9502 * 48bits addresses, and we need a NOOP for the batch size to
9503 * stay even.
9504 */
9505 if (IS_GEN8(dev))
9506 len += 2;
9507 }
9508
9509 /*
9510 * BSpec MI_DISPLAY_FLIP for IVB:
9511 * "The full packet must be contained within the same cache line."
9512 *
9513 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9514 * cacheline, if we ever start emitting more commands before
9515 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9516 * then do the cacheline alignment, and finally emit the
9517 * MI_DISPLAY_FLIP.
9518 */
9519 ret = intel_ring_cacheline_align(ring);
9520 if (ret)
9521 return ret;
9522
9523 ret = intel_ring_begin(ring, len);
9524 if (ret)
9525 return ret;
9526
9527 /* Unmask the flip-done completion message. Note that the bspec says that
9528 * we should do this for both the BCS and RCS, and that we must not unmask
9529 * more than one flip event at any time (or ensure that one flip message
9530 * can be sent by waiting for flip-done prior to queueing new flips).
9531 * Experimentation says that BCS works despite DERRMR masking all
9532 * flip-done completion events and that unmasking all planes at once
9533 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9534 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9535 */
9536 if (ring->id == RCS) {
9537 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9538 intel_ring_emit(ring, DERRMR);
9539 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9540 DERRMR_PIPEB_PRI_FLIP_DONE |
9541 DERRMR_PIPEC_PRI_FLIP_DONE));
9542 if (IS_GEN8(dev))
9543 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9544 MI_SRM_LRM_GLOBAL_GTT);
9545 else
9546 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9547 MI_SRM_LRM_GLOBAL_GTT);
9548 intel_ring_emit(ring, DERRMR);
9549 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9550 if (IS_GEN8(dev)) {
9551 intel_ring_emit(ring, 0);
9552 intel_ring_emit(ring, MI_NOOP);
9553 }
9554 }
9555
9556 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9557 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9558 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9559 intel_ring_emit(ring, (MI_NOOP));
9560
9561 intel_mark_page_flip_active(intel_crtc);
9562 __intel_ring_advance(ring);
9563 return 0;
9564 }
9565
9566 static bool use_mmio_flip(struct intel_engine_cs *ring,
9567 struct drm_i915_gem_object *obj)
9568 {
9569 /*
9570 * This is not being used for older platforms, because
9571 * non-availability of flip done interrupt forces us to use
9572 * CS flips. Older platforms derive flip done using some clever
9573 * tricks involving the flip_pending status bits and vblank irqs.
9574 * So using MMIO flips there would disrupt this mechanism.
9575 */
9576
9577 if (ring == NULL)
9578 return true;
9579
9580 if (INTEL_INFO(ring->dev)->gen < 5)
9581 return false;
9582
9583 if (i915.use_mmio_flip < 0)
9584 return false;
9585 else if (i915.use_mmio_flip > 0)
9586 return true;
9587 else if (i915.enable_execlists)
9588 return true;
9589 else
9590 return ring != obj->ring;
9591 }
9592
9593 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9594 {
9595 struct drm_device *dev = intel_crtc->base.dev;
9596 struct drm_i915_private *dev_priv = dev->dev_private;
9597 struct intel_framebuffer *intel_fb =
9598 to_intel_framebuffer(intel_crtc->base.primary->fb);
9599 struct drm_i915_gem_object *obj = intel_fb->obj;
9600 u32 dspcntr;
9601 u32 reg;
9602
9603 intel_mark_page_flip_active(intel_crtc);
9604
9605 reg = DSPCNTR(intel_crtc->plane);
9606 dspcntr = I915_READ(reg);
9607
9608 if (INTEL_INFO(dev)->gen >= 4) {
9609 if (obj->tiling_mode != I915_TILING_NONE)
9610 dspcntr |= DISPPLANE_TILED;
9611 else
9612 dspcntr &= ~DISPPLANE_TILED;
9613 }
9614 I915_WRITE(reg, dspcntr);
9615
9616 I915_WRITE(DSPSURF(intel_crtc->plane),
9617 intel_crtc->unpin_work->gtt_offset);
9618 POSTING_READ(DSPSURF(intel_crtc->plane));
9619 }
9620
9621 static int intel_postpone_flip(struct drm_i915_gem_object *obj)
9622 {
9623 struct intel_engine_cs *ring;
9624 int ret;
9625
9626 lockdep_assert_held(&obj->base.dev->struct_mutex);
9627
9628 if (!obj->last_write_seqno)
9629 return 0;
9630
9631 ring = obj->ring;
9632
9633 if (i915_seqno_passed(ring->get_seqno(ring, true),
9634 obj->last_write_seqno))
9635 return 0;
9636
9637 ret = i915_gem_check_olr(ring, obj->last_write_seqno);
9638 if (ret)
9639 return ret;
9640
9641 if (WARN_ON(!ring->irq_get(ring)))
9642 return 0;
9643
9644 return 1;
9645 }
9646
9647 void intel_notify_mmio_flip(struct intel_engine_cs *ring)
9648 {
9649 struct drm_i915_private *dev_priv = to_i915(ring->dev);
9650 struct intel_crtc *intel_crtc;
9651 unsigned long irq_flags;
9652 u32 seqno;
9653
9654 seqno = ring->get_seqno(ring, false);
9655
9656 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9657 for_each_intel_crtc(ring->dev, intel_crtc) {
9658 struct intel_mmio_flip *mmio_flip;
9659
9660 mmio_flip = &intel_crtc->mmio_flip;
9661 if (mmio_flip->seqno == 0)
9662 continue;
9663
9664 if (ring->id != mmio_flip->ring_id)
9665 continue;
9666
9667 if (i915_seqno_passed(seqno, mmio_flip->seqno)) {
9668 intel_do_mmio_flip(intel_crtc);
9669 mmio_flip->seqno = 0;
9670 ring->irq_put(ring);
9671 }
9672 }
9673 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9674 }
9675
9676 static int intel_queue_mmio_flip(struct drm_device *dev,
9677 struct drm_crtc *crtc,
9678 struct drm_framebuffer *fb,
9679 struct drm_i915_gem_object *obj,
9680 struct intel_engine_cs *ring,
9681 uint32_t flags)
9682 {
9683 struct drm_i915_private *dev_priv = dev->dev_private;
9684 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9685 unsigned long irq_flags;
9686 int ret;
9687
9688 if (WARN_ON(intel_crtc->mmio_flip.seqno))
9689 return -EBUSY;
9690
9691 ret = intel_postpone_flip(obj);
9692 if (ret < 0)
9693 return ret;
9694 if (ret == 0) {
9695 intel_do_mmio_flip(intel_crtc);
9696 return 0;
9697 }
9698
9699 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9700 intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
9701 intel_crtc->mmio_flip.ring_id = obj->ring->id;
9702 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9703
9704 /*
9705 * Double check to catch cases where irq fired before
9706 * mmio flip data was ready
9707 */
9708 intel_notify_mmio_flip(obj->ring);
9709 return 0;
9710 }
9711
9712 static int intel_default_queue_flip(struct drm_device *dev,
9713 struct drm_crtc *crtc,
9714 struct drm_framebuffer *fb,
9715 struct drm_i915_gem_object *obj,
9716 struct intel_engine_cs *ring,
9717 uint32_t flags)
9718 {
9719 return -ENODEV;
9720 }
9721
9722 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9723 struct drm_framebuffer *fb,
9724 struct drm_pending_vblank_event *event,
9725 uint32_t page_flip_flags)
9726 {
9727 struct drm_device *dev = crtc->dev;
9728 struct drm_i915_private *dev_priv = dev->dev_private;
9729 struct drm_framebuffer *old_fb = crtc->primary->fb;
9730 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9731 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9732 enum pipe pipe = intel_crtc->pipe;
9733 struct intel_unpin_work *work;
9734 struct intel_engine_cs *ring;
9735 unsigned long flags;
9736 int ret;
9737
9738 /*
9739 * drm_mode_page_flip_ioctl() should already catch this, but double
9740 * check to be safe. In the future we may enable pageflipping from
9741 * a disabled primary plane.
9742 */
9743 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9744 return -EBUSY;
9745
9746 /* Can't change pixel format via MI display flips. */
9747 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9748 return -EINVAL;
9749
9750 /*
9751 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9752 * Note that pitch changes could also affect these register.
9753 */
9754 if (INTEL_INFO(dev)->gen > 3 &&
9755 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9756 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9757 return -EINVAL;
9758
9759 if (i915_terminally_wedged(&dev_priv->gpu_error))
9760 goto out_hang;
9761
9762 work = kzalloc(sizeof(*work), GFP_KERNEL);
9763 if (work == NULL)
9764 return -ENOMEM;
9765
9766 work->event = event;
9767 work->crtc = crtc;
9768 work->old_fb_obj = intel_fb_obj(old_fb);
9769 INIT_WORK(&work->work, intel_unpin_work_fn);
9770
9771 ret = drm_crtc_vblank_get(crtc);
9772 if (ret)
9773 goto free_work;
9774
9775 /* We borrow the event spin lock for protecting unpin_work */
9776 spin_lock_irqsave(&dev->event_lock, flags);
9777 if (intel_crtc->unpin_work) {
9778 spin_unlock_irqrestore(&dev->event_lock, flags);
9779 kfree(work);
9780 drm_crtc_vblank_put(crtc);
9781
9782 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9783 return -EBUSY;
9784 }
9785 intel_crtc->unpin_work = work;
9786 spin_unlock_irqrestore(&dev->event_lock, flags);
9787
9788 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9789 flush_workqueue(dev_priv->wq);
9790
9791 ret = i915_mutex_lock_interruptible(dev);
9792 if (ret)
9793 goto cleanup;
9794
9795 /* Reference the objects for the scheduled work. */
9796 drm_gem_object_reference(&work->old_fb_obj->base);
9797 drm_gem_object_reference(&obj->base);
9798
9799 crtc->primary->fb = fb;
9800
9801 work->pending_flip_obj = obj;
9802
9803 work->enable_stall_check = true;
9804
9805 atomic_inc(&intel_crtc->unpin_work_count);
9806 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9807
9808 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9809 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9810
9811 if (IS_VALLEYVIEW(dev)) {
9812 ring = &dev_priv->ring[BCS];
9813 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9814 /* vlv: DISPLAY_FLIP fails to change tiling */
9815 ring = NULL;
9816 } else if (IS_IVYBRIDGE(dev)) {
9817 ring = &dev_priv->ring[BCS];
9818 } else if (INTEL_INFO(dev)->gen >= 7) {
9819 ring = obj->ring;
9820 if (ring == NULL || ring->id != RCS)
9821 ring = &dev_priv->ring[BCS];
9822 } else {
9823 ring = &dev_priv->ring[RCS];
9824 }
9825
9826 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9827 if (ret)
9828 goto cleanup_pending;
9829
9830 work->gtt_offset =
9831 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9832
9833 if (use_mmio_flip(ring, obj))
9834 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9835 page_flip_flags);
9836 else
9837 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9838 page_flip_flags);
9839 if (ret)
9840 goto cleanup_unpin;
9841
9842 i915_gem_track_fb(work->old_fb_obj, obj,
9843 INTEL_FRONTBUFFER_PRIMARY(pipe));
9844
9845 intel_disable_fbc(dev);
9846 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9847 mutex_unlock(&dev->struct_mutex);
9848
9849 trace_i915_flip_request(intel_crtc->plane, obj);
9850
9851 return 0;
9852
9853 cleanup_unpin:
9854 intel_unpin_fb_obj(obj);
9855 cleanup_pending:
9856 atomic_dec(&intel_crtc->unpin_work_count);
9857 crtc->primary->fb = old_fb;
9858 drm_gem_object_unreference(&work->old_fb_obj->base);
9859 drm_gem_object_unreference(&obj->base);
9860 mutex_unlock(&dev->struct_mutex);
9861
9862 cleanup:
9863 spin_lock_irqsave(&dev->event_lock, flags);
9864 intel_crtc->unpin_work = NULL;
9865 spin_unlock_irqrestore(&dev->event_lock, flags);
9866
9867 drm_crtc_vblank_put(crtc);
9868 free_work:
9869 kfree(work);
9870
9871 if (ret == -EIO) {
9872 out_hang:
9873 intel_crtc_wait_for_pending_flips(crtc);
9874 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9875 if (ret == 0 && event)
9876 drm_send_vblank_event(dev, pipe, event);
9877 }
9878 return ret;
9879 }
9880
9881 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9882 .mode_set_base_atomic = intel_pipe_set_base_atomic,
9883 .load_lut = intel_crtc_load_lut,
9884 };
9885
9886 /**
9887 * intel_modeset_update_staged_output_state
9888 *
9889 * Updates the staged output configuration state, e.g. after we've read out the
9890 * current hw state.
9891 */
9892 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9893 {
9894 struct intel_crtc *crtc;
9895 struct intel_encoder *encoder;
9896 struct intel_connector *connector;
9897
9898 list_for_each_entry(connector, &dev->mode_config.connector_list,
9899 base.head) {
9900 connector->new_encoder =
9901 to_intel_encoder(connector->base.encoder);
9902 }
9903
9904 for_each_intel_encoder(dev, encoder) {
9905 encoder->new_crtc =
9906 to_intel_crtc(encoder->base.crtc);
9907 }
9908
9909 for_each_intel_crtc(dev, crtc) {
9910 crtc->new_enabled = crtc->base.enabled;
9911
9912 if (crtc->new_enabled)
9913 crtc->new_config = &crtc->config;
9914 else
9915 crtc->new_config = NULL;
9916 }
9917 }
9918
9919 /**
9920 * intel_modeset_commit_output_state
9921 *
9922 * This function copies the stage display pipe configuration to the real one.
9923 */
9924 static void intel_modeset_commit_output_state(struct drm_device *dev)
9925 {
9926 struct intel_crtc *crtc;
9927 struct intel_encoder *encoder;
9928 struct intel_connector *connector;
9929
9930 list_for_each_entry(connector, &dev->mode_config.connector_list,
9931 base.head) {
9932 connector->base.encoder = &connector->new_encoder->base;
9933 }
9934
9935 for_each_intel_encoder(dev, encoder) {
9936 encoder->base.crtc = &encoder->new_crtc->base;
9937 }
9938
9939 for_each_intel_crtc(dev, crtc) {
9940 crtc->base.enabled = crtc->new_enabled;
9941 }
9942 }
9943
9944 static void
9945 connected_sink_compute_bpp(struct intel_connector *connector,
9946 struct intel_crtc_config *pipe_config)
9947 {
9948 int bpp = pipe_config->pipe_bpp;
9949
9950 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9951 connector->base.base.id,
9952 connector->base.name);
9953
9954 /* Don't use an invalid EDID bpc value */
9955 if (connector->base.display_info.bpc &&
9956 connector->base.display_info.bpc * 3 < bpp) {
9957 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9958 bpp, connector->base.display_info.bpc*3);
9959 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9960 }
9961
9962 /* Clamp bpp to 8 on screens without EDID 1.4 */
9963 if (connector->base.display_info.bpc == 0 && bpp > 24) {
9964 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9965 bpp);
9966 pipe_config->pipe_bpp = 24;
9967 }
9968 }
9969
9970 static int
9971 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9972 struct drm_framebuffer *fb,
9973 struct intel_crtc_config *pipe_config)
9974 {
9975 struct drm_device *dev = crtc->base.dev;
9976 struct intel_connector *connector;
9977 int bpp;
9978
9979 switch (fb->pixel_format) {
9980 case DRM_FORMAT_C8:
9981 bpp = 8*3; /* since we go through a colormap */
9982 break;
9983 case DRM_FORMAT_XRGB1555:
9984 case DRM_FORMAT_ARGB1555:
9985 /* checked in intel_framebuffer_init already */
9986 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9987 return -EINVAL;
9988 case DRM_FORMAT_RGB565:
9989 bpp = 6*3; /* min is 18bpp */
9990 break;
9991 case DRM_FORMAT_XBGR8888:
9992 case DRM_FORMAT_ABGR8888:
9993 /* checked in intel_framebuffer_init already */
9994 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9995 return -EINVAL;
9996 case DRM_FORMAT_XRGB8888:
9997 case DRM_FORMAT_ARGB8888:
9998 bpp = 8*3;
9999 break;
10000 case DRM_FORMAT_XRGB2101010:
10001 case DRM_FORMAT_ARGB2101010:
10002 case DRM_FORMAT_XBGR2101010:
10003 case DRM_FORMAT_ABGR2101010:
10004 /* checked in intel_framebuffer_init already */
10005 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10006 return -EINVAL;
10007 bpp = 10*3;
10008 break;
10009 /* TODO: gen4+ supports 16 bpc floating point, too. */
10010 default:
10011 DRM_DEBUG_KMS("unsupported depth\n");
10012 return -EINVAL;
10013 }
10014
10015 pipe_config->pipe_bpp = bpp;
10016
10017 /* Clamp display bpp to EDID value */
10018 list_for_each_entry(connector, &dev->mode_config.connector_list,
10019 base.head) {
10020 if (!connector->new_encoder ||
10021 connector->new_encoder->new_crtc != crtc)
10022 continue;
10023
10024 connected_sink_compute_bpp(connector, pipe_config);
10025 }
10026
10027 return bpp;
10028 }
10029
10030 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10031 {
10032 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10033 "type: 0x%x flags: 0x%x\n",
10034 mode->crtc_clock,
10035 mode->crtc_hdisplay, mode->crtc_hsync_start,
10036 mode->crtc_hsync_end, mode->crtc_htotal,
10037 mode->crtc_vdisplay, mode->crtc_vsync_start,
10038 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10039 }
10040
10041 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10042 struct intel_crtc_config *pipe_config,
10043 const char *context)
10044 {
10045 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10046 context, pipe_name(crtc->pipe));
10047
10048 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10049 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10050 pipe_config->pipe_bpp, pipe_config->dither);
10051 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10052 pipe_config->has_pch_encoder,
10053 pipe_config->fdi_lanes,
10054 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10055 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10056 pipe_config->fdi_m_n.tu);
10057 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10058 pipe_config->has_dp_encoder,
10059 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10060 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10061 pipe_config->dp_m_n.tu);
10062
10063 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10064 pipe_config->has_dp_encoder,
10065 pipe_config->dp_m2_n2.gmch_m,
10066 pipe_config->dp_m2_n2.gmch_n,
10067 pipe_config->dp_m2_n2.link_m,
10068 pipe_config->dp_m2_n2.link_n,
10069 pipe_config->dp_m2_n2.tu);
10070
10071 DRM_DEBUG_KMS("requested mode:\n");
10072 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
10073 DRM_DEBUG_KMS("adjusted mode:\n");
10074 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
10075 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
10076 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10077 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10078 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10079 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10080 pipe_config->gmch_pfit.control,
10081 pipe_config->gmch_pfit.pgm_ratios,
10082 pipe_config->gmch_pfit.lvds_border_bits);
10083 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10084 pipe_config->pch_pfit.pos,
10085 pipe_config->pch_pfit.size,
10086 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10087 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10088 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10089 }
10090
10091 static bool encoders_cloneable(const struct intel_encoder *a,
10092 const struct intel_encoder *b)
10093 {
10094 /* masks could be asymmetric, so check both ways */
10095 return a == b || (a->cloneable & (1 << b->type) &&
10096 b->cloneable & (1 << a->type));
10097 }
10098
10099 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10100 struct intel_encoder *encoder)
10101 {
10102 struct drm_device *dev = crtc->base.dev;
10103 struct intel_encoder *source_encoder;
10104
10105 for_each_intel_encoder(dev, source_encoder) {
10106 if (source_encoder->new_crtc != crtc)
10107 continue;
10108
10109 if (!encoders_cloneable(encoder, source_encoder))
10110 return false;
10111 }
10112
10113 return true;
10114 }
10115
10116 static bool check_encoder_cloning(struct intel_crtc *crtc)
10117 {
10118 struct drm_device *dev = crtc->base.dev;
10119 struct intel_encoder *encoder;
10120
10121 for_each_intel_encoder(dev, encoder) {
10122 if (encoder->new_crtc != crtc)
10123 continue;
10124
10125 if (!check_single_encoder_cloning(crtc, encoder))
10126 return false;
10127 }
10128
10129 return true;
10130 }
10131
10132 static struct intel_crtc_config *
10133 intel_modeset_pipe_config(struct drm_crtc *crtc,
10134 struct drm_framebuffer *fb,
10135 struct drm_display_mode *mode)
10136 {
10137 struct drm_device *dev = crtc->dev;
10138 struct intel_encoder *encoder;
10139 struct intel_crtc_config *pipe_config;
10140 int plane_bpp, ret = -EINVAL;
10141 bool retry = true;
10142
10143 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10144 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10145 return ERR_PTR(-EINVAL);
10146 }
10147
10148 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10149 if (!pipe_config)
10150 return ERR_PTR(-ENOMEM);
10151
10152 drm_mode_copy(&pipe_config->adjusted_mode, mode);
10153 drm_mode_copy(&pipe_config->requested_mode, mode);
10154
10155 pipe_config->cpu_transcoder =
10156 (enum transcoder) to_intel_crtc(crtc)->pipe;
10157 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10158
10159 /*
10160 * Sanitize sync polarity flags based on requested ones. If neither
10161 * positive or negative polarity is requested, treat this as meaning
10162 * negative polarity.
10163 */
10164 if (!(pipe_config->adjusted_mode.flags &
10165 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10166 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10167
10168 if (!(pipe_config->adjusted_mode.flags &
10169 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10170 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10171
10172 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10173 * plane pixel format and any sink constraints into account. Returns the
10174 * source plane bpp so that dithering can be selected on mismatches
10175 * after encoders and crtc also have had their say. */
10176 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10177 fb, pipe_config);
10178 if (plane_bpp < 0)
10179 goto fail;
10180
10181 /*
10182 * Determine the real pipe dimensions. Note that stereo modes can
10183 * increase the actual pipe size due to the frame doubling and
10184 * insertion of additional space for blanks between the frame. This
10185 * is stored in the crtc timings. We use the requested mode to do this
10186 * computation to clearly distinguish it from the adjusted mode, which
10187 * can be changed by the connectors in the below retry loop.
10188 */
10189 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
10190 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
10191 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
10192
10193 encoder_retry:
10194 /* Ensure the port clock defaults are reset when retrying. */
10195 pipe_config->port_clock = 0;
10196 pipe_config->pixel_multiplier = 1;
10197
10198 /* Fill in default crtc timings, allow encoders to overwrite them. */
10199 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
10200
10201 /* Pass our mode to the connectors and the CRTC to give them a chance to
10202 * adjust it according to limitations or connector properties, and also
10203 * a chance to reject the mode entirely.
10204 */
10205 for_each_intel_encoder(dev, encoder) {
10206
10207 if (&encoder->new_crtc->base != crtc)
10208 continue;
10209
10210 if (!(encoder->compute_config(encoder, pipe_config))) {
10211 DRM_DEBUG_KMS("Encoder config failure\n");
10212 goto fail;
10213 }
10214 }
10215
10216 /* Set default port clock if not overwritten by the encoder. Needs to be
10217 * done afterwards in case the encoder adjusts the mode. */
10218 if (!pipe_config->port_clock)
10219 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10220 * pipe_config->pixel_multiplier;
10221
10222 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10223 if (ret < 0) {
10224 DRM_DEBUG_KMS("CRTC fixup failed\n");
10225 goto fail;
10226 }
10227
10228 if (ret == RETRY) {
10229 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10230 ret = -EINVAL;
10231 goto fail;
10232 }
10233
10234 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10235 retry = false;
10236 goto encoder_retry;
10237 }
10238
10239 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10240 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10241 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10242
10243 return pipe_config;
10244 fail:
10245 kfree(pipe_config);
10246 return ERR_PTR(ret);
10247 }
10248
10249 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10250 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10251 static void
10252 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10253 unsigned *prepare_pipes, unsigned *disable_pipes)
10254 {
10255 struct intel_crtc *intel_crtc;
10256 struct drm_device *dev = crtc->dev;
10257 struct intel_encoder *encoder;
10258 struct intel_connector *connector;
10259 struct drm_crtc *tmp_crtc;
10260
10261 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10262
10263 /* Check which crtcs have changed outputs connected to them, these need
10264 * to be part of the prepare_pipes mask. We don't (yet) support global
10265 * modeset across multiple crtcs, so modeset_pipes will only have one
10266 * bit set at most. */
10267 list_for_each_entry(connector, &dev->mode_config.connector_list,
10268 base.head) {
10269 if (connector->base.encoder == &connector->new_encoder->base)
10270 continue;
10271
10272 if (connector->base.encoder) {
10273 tmp_crtc = connector->base.encoder->crtc;
10274
10275 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10276 }
10277
10278 if (connector->new_encoder)
10279 *prepare_pipes |=
10280 1 << connector->new_encoder->new_crtc->pipe;
10281 }
10282
10283 for_each_intel_encoder(dev, encoder) {
10284 if (encoder->base.crtc == &encoder->new_crtc->base)
10285 continue;
10286
10287 if (encoder->base.crtc) {
10288 tmp_crtc = encoder->base.crtc;
10289
10290 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10291 }
10292
10293 if (encoder->new_crtc)
10294 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10295 }
10296
10297 /* Check for pipes that will be enabled/disabled ... */
10298 for_each_intel_crtc(dev, intel_crtc) {
10299 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10300 continue;
10301
10302 if (!intel_crtc->new_enabled)
10303 *disable_pipes |= 1 << intel_crtc->pipe;
10304 else
10305 *prepare_pipes |= 1 << intel_crtc->pipe;
10306 }
10307
10308
10309 /* set_mode is also used to update properties on life display pipes. */
10310 intel_crtc = to_intel_crtc(crtc);
10311 if (intel_crtc->new_enabled)
10312 *prepare_pipes |= 1 << intel_crtc->pipe;
10313
10314 /*
10315 * For simplicity do a full modeset on any pipe where the output routing
10316 * changed. We could be more clever, but that would require us to be
10317 * more careful with calling the relevant encoder->mode_set functions.
10318 */
10319 if (*prepare_pipes)
10320 *modeset_pipes = *prepare_pipes;
10321
10322 /* ... and mask these out. */
10323 *modeset_pipes &= ~(*disable_pipes);
10324 *prepare_pipes &= ~(*disable_pipes);
10325
10326 /*
10327 * HACK: We don't (yet) fully support global modesets. intel_set_config
10328 * obies this rule, but the modeset restore mode of
10329 * intel_modeset_setup_hw_state does not.
10330 */
10331 *modeset_pipes &= 1 << intel_crtc->pipe;
10332 *prepare_pipes &= 1 << intel_crtc->pipe;
10333
10334 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10335 *modeset_pipes, *prepare_pipes, *disable_pipes);
10336 }
10337
10338 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10339 {
10340 struct drm_encoder *encoder;
10341 struct drm_device *dev = crtc->dev;
10342
10343 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10344 if (encoder->crtc == crtc)
10345 return true;
10346
10347 return false;
10348 }
10349
10350 static void
10351 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10352 {
10353 struct intel_encoder *intel_encoder;
10354 struct intel_crtc *intel_crtc;
10355 struct drm_connector *connector;
10356
10357 for_each_intel_encoder(dev, intel_encoder) {
10358 if (!intel_encoder->base.crtc)
10359 continue;
10360
10361 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10362
10363 if (prepare_pipes & (1 << intel_crtc->pipe))
10364 intel_encoder->connectors_active = false;
10365 }
10366
10367 intel_modeset_commit_output_state(dev);
10368
10369 /* Double check state. */
10370 for_each_intel_crtc(dev, intel_crtc) {
10371 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10372 WARN_ON(intel_crtc->new_config &&
10373 intel_crtc->new_config != &intel_crtc->config);
10374 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10375 }
10376
10377 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10378 if (!connector->encoder || !connector->encoder->crtc)
10379 continue;
10380
10381 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10382
10383 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10384 struct drm_property *dpms_property =
10385 dev->mode_config.dpms_property;
10386
10387 connector->dpms = DRM_MODE_DPMS_ON;
10388 drm_object_property_set_value(&connector->base,
10389 dpms_property,
10390 DRM_MODE_DPMS_ON);
10391
10392 intel_encoder = to_intel_encoder(connector->encoder);
10393 intel_encoder->connectors_active = true;
10394 }
10395 }
10396
10397 }
10398
10399 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10400 {
10401 int diff;
10402
10403 if (clock1 == clock2)
10404 return true;
10405
10406 if (!clock1 || !clock2)
10407 return false;
10408
10409 diff = abs(clock1 - clock2);
10410
10411 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10412 return true;
10413
10414 return false;
10415 }
10416
10417 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10418 list_for_each_entry((intel_crtc), \
10419 &(dev)->mode_config.crtc_list, \
10420 base.head) \
10421 if (mask & (1 <<(intel_crtc)->pipe))
10422
10423 static bool
10424 intel_pipe_config_compare(struct drm_device *dev,
10425 struct intel_crtc_config *current_config,
10426 struct intel_crtc_config *pipe_config)
10427 {
10428 #define PIPE_CONF_CHECK_X(name) \
10429 if (current_config->name != pipe_config->name) { \
10430 DRM_ERROR("mismatch in " #name " " \
10431 "(expected 0x%08x, found 0x%08x)\n", \
10432 current_config->name, \
10433 pipe_config->name); \
10434 return false; \
10435 }
10436
10437 #define PIPE_CONF_CHECK_I(name) \
10438 if (current_config->name != pipe_config->name) { \
10439 DRM_ERROR("mismatch in " #name " " \
10440 "(expected %i, found %i)\n", \
10441 current_config->name, \
10442 pipe_config->name); \
10443 return false; \
10444 }
10445
10446 /* This is required for BDW+ where there is only one set of registers for
10447 * switching between high and low RR.
10448 * This macro can be used whenever a comparison has to be made between one
10449 * hw state and multiple sw state variables.
10450 */
10451 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10452 if ((current_config->name != pipe_config->name) && \
10453 (current_config->alt_name != pipe_config->name)) { \
10454 DRM_ERROR("mismatch in " #name " " \
10455 "(expected %i or %i, found %i)\n", \
10456 current_config->name, \
10457 current_config->alt_name, \
10458 pipe_config->name); \
10459 return false; \
10460 }
10461
10462 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10463 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10464 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10465 "(expected %i, found %i)\n", \
10466 current_config->name & (mask), \
10467 pipe_config->name & (mask)); \
10468 return false; \
10469 }
10470
10471 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10472 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10473 DRM_ERROR("mismatch in " #name " " \
10474 "(expected %i, found %i)\n", \
10475 current_config->name, \
10476 pipe_config->name); \
10477 return false; \
10478 }
10479
10480 #define PIPE_CONF_QUIRK(quirk) \
10481 ((current_config->quirks | pipe_config->quirks) & (quirk))
10482
10483 PIPE_CONF_CHECK_I(cpu_transcoder);
10484
10485 PIPE_CONF_CHECK_I(has_pch_encoder);
10486 PIPE_CONF_CHECK_I(fdi_lanes);
10487 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10488 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10489 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10490 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10491 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10492
10493 PIPE_CONF_CHECK_I(has_dp_encoder);
10494
10495 if (INTEL_INFO(dev)->gen < 8) {
10496 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10497 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10498 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10499 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10500 PIPE_CONF_CHECK_I(dp_m_n.tu);
10501
10502 if (current_config->has_drrs) {
10503 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10504 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10505 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10506 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10507 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10508 }
10509 } else {
10510 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10511 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10512 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10513 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10514 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10515 }
10516
10517 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10518 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10519 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10520 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10521 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10522 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10523
10524 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10525 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10526 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10527 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10528 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10529 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10530
10531 PIPE_CONF_CHECK_I(pixel_multiplier);
10532 PIPE_CONF_CHECK_I(has_hdmi_sink);
10533 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10534 IS_VALLEYVIEW(dev))
10535 PIPE_CONF_CHECK_I(limited_color_range);
10536
10537 PIPE_CONF_CHECK_I(has_audio);
10538
10539 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10540 DRM_MODE_FLAG_INTERLACE);
10541
10542 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10543 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10544 DRM_MODE_FLAG_PHSYNC);
10545 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10546 DRM_MODE_FLAG_NHSYNC);
10547 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10548 DRM_MODE_FLAG_PVSYNC);
10549 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10550 DRM_MODE_FLAG_NVSYNC);
10551 }
10552
10553 PIPE_CONF_CHECK_I(pipe_src_w);
10554 PIPE_CONF_CHECK_I(pipe_src_h);
10555
10556 /*
10557 * FIXME: BIOS likes to set up a cloned config with lvds+external
10558 * screen. Since we don't yet re-compute the pipe config when moving
10559 * just the lvds port away to another pipe the sw tracking won't match.
10560 *
10561 * Proper atomic modesets with recomputed global state will fix this.
10562 * Until then just don't check gmch state for inherited modes.
10563 */
10564 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10565 PIPE_CONF_CHECK_I(gmch_pfit.control);
10566 /* pfit ratios are autocomputed by the hw on gen4+ */
10567 if (INTEL_INFO(dev)->gen < 4)
10568 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10569 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10570 }
10571
10572 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10573 if (current_config->pch_pfit.enabled) {
10574 PIPE_CONF_CHECK_I(pch_pfit.pos);
10575 PIPE_CONF_CHECK_I(pch_pfit.size);
10576 }
10577
10578 /* BDW+ don't expose a synchronous way to read the state */
10579 if (IS_HASWELL(dev))
10580 PIPE_CONF_CHECK_I(ips_enabled);
10581
10582 PIPE_CONF_CHECK_I(double_wide);
10583
10584 PIPE_CONF_CHECK_X(ddi_pll_sel);
10585
10586 PIPE_CONF_CHECK_I(shared_dpll);
10587 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10588 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10589 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10590 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10591 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10592
10593 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10594 PIPE_CONF_CHECK_I(pipe_bpp);
10595
10596 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10597 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10598
10599 #undef PIPE_CONF_CHECK_X
10600 #undef PIPE_CONF_CHECK_I
10601 #undef PIPE_CONF_CHECK_I_ALT
10602 #undef PIPE_CONF_CHECK_FLAGS
10603 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10604 #undef PIPE_CONF_QUIRK
10605
10606 return true;
10607 }
10608
10609 static void
10610 check_connector_state(struct drm_device *dev)
10611 {
10612 struct intel_connector *connector;
10613
10614 list_for_each_entry(connector, &dev->mode_config.connector_list,
10615 base.head) {
10616 /* This also checks the encoder/connector hw state with the
10617 * ->get_hw_state callbacks. */
10618 intel_connector_check_state(connector);
10619
10620 WARN(&connector->new_encoder->base != connector->base.encoder,
10621 "connector's staged encoder doesn't match current encoder\n");
10622 }
10623 }
10624
10625 static void
10626 check_encoder_state(struct drm_device *dev)
10627 {
10628 struct intel_encoder *encoder;
10629 struct intel_connector *connector;
10630
10631 for_each_intel_encoder(dev, encoder) {
10632 bool enabled = false;
10633 bool active = false;
10634 enum pipe pipe, tracked_pipe;
10635
10636 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10637 encoder->base.base.id,
10638 encoder->base.name);
10639
10640 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10641 "encoder's stage crtc doesn't match current crtc\n");
10642 WARN(encoder->connectors_active && !encoder->base.crtc,
10643 "encoder's active_connectors set, but no crtc\n");
10644
10645 list_for_each_entry(connector, &dev->mode_config.connector_list,
10646 base.head) {
10647 if (connector->base.encoder != &encoder->base)
10648 continue;
10649 enabled = true;
10650 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10651 active = true;
10652 }
10653 /*
10654 * for MST connectors if we unplug the connector is gone
10655 * away but the encoder is still connected to a crtc
10656 * until a modeset happens in response to the hotplug.
10657 */
10658 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10659 continue;
10660
10661 WARN(!!encoder->base.crtc != enabled,
10662 "encoder's enabled state mismatch "
10663 "(expected %i, found %i)\n",
10664 !!encoder->base.crtc, enabled);
10665 WARN(active && !encoder->base.crtc,
10666 "active encoder with no crtc\n");
10667
10668 WARN(encoder->connectors_active != active,
10669 "encoder's computed active state doesn't match tracked active state "
10670 "(expected %i, found %i)\n", active, encoder->connectors_active);
10671
10672 active = encoder->get_hw_state(encoder, &pipe);
10673 WARN(active != encoder->connectors_active,
10674 "encoder's hw state doesn't match sw tracking "
10675 "(expected %i, found %i)\n",
10676 encoder->connectors_active, active);
10677
10678 if (!encoder->base.crtc)
10679 continue;
10680
10681 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10682 WARN(active && pipe != tracked_pipe,
10683 "active encoder's pipe doesn't match"
10684 "(expected %i, found %i)\n",
10685 tracked_pipe, pipe);
10686
10687 }
10688 }
10689
10690 static void
10691 check_crtc_state(struct drm_device *dev)
10692 {
10693 struct drm_i915_private *dev_priv = dev->dev_private;
10694 struct intel_crtc *crtc;
10695 struct intel_encoder *encoder;
10696 struct intel_crtc_config pipe_config;
10697
10698 for_each_intel_crtc(dev, crtc) {
10699 bool enabled = false;
10700 bool active = false;
10701
10702 memset(&pipe_config, 0, sizeof(pipe_config));
10703
10704 DRM_DEBUG_KMS("[CRTC:%d]\n",
10705 crtc->base.base.id);
10706
10707 WARN(crtc->active && !crtc->base.enabled,
10708 "active crtc, but not enabled in sw tracking\n");
10709
10710 for_each_intel_encoder(dev, encoder) {
10711 if (encoder->base.crtc != &crtc->base)
10712 continue;
10713 enabled = true;
10714 if (encoder->connectors_active)
10715 active = true;
10716 }
10717
10718 WARN(active != crtc->active,
10719 "crtc's computed active state doesn't match tracked active state "
10720 "(expected %i, found %i)\n", active, crtc->active);
10721 WARN(enabled != crtc->base.enabled,
10722 "crtc's computed enabled state doesn't match tracked enabled state "
10723 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10724
10725 active = dev_priv->display.get_pipe_config(crtc,
10726 &pipe_config);
10727
10728 /* hw state is inconsistent with the pipe A quirk */
10729 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
10730 active = crtc->active;
10731
10732 for_each_intel_encoder(dev, encoder) {
10733 enum pipe pipe;
10734 if (encoder->base.crtc != &crtc->base)
10735 continue;
10736 if (encoder->get_hw_state(encoder, &pipe))
10737 encoder->get_config(encoder, &pipe_config);
10738 }
10739
10740 WARN(crtc->active != active,
10741 "crtc active state doesn't match with hw state "
10742 "(expected %i, found %i)\n", crtc->active, active);
10743
10744 if (active &&
10745 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10746 WARN(1, "pipe state doesn't match!\n");
10747 intel_dump_pipe_config(crtc, &pipe_config,
10748 "[hw state]");
10749 intel_dump_pipe_config(crtc, &crtc->config,
10750 "[sw state]");
10751 }
10752 }
10753 }
10754
10755 static void
10756 check_shared_dpll_state(struct drm_device *dev)
10757 {
10758 struct drm_i915_private *dev_priv = dev->dev_private;
10759 struct intel_crtc *crtc;
10760 struct intel_dpll_hw_state dpll_hw_state;
10761 int i;
10762
10763 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10764 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10765 int enabled_crtcs = 0, active_crtcs = 0;
10766 bool active;
10767
10768 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10769
10770 DRM_DEBUG_KMS("%s\n", pll->name);
10771
10772 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10773
10774 WARN(pll->active > pll->refcount,
10775 "more active pll users than references: %i vs %i\n",
10776 pll->active, pll->refcount);
10777 WARN(pll->active && !pll->on,
10778 "pll in active use but not on in sw tracking\n");
10779 WARN(pll->on && !pll->active,
10780 "pll in on but not on in use in sw tracking\n");
10781 WARN(pll->on != active,
10782 "pll on state mismatch (expected %i, found %i)\n",
10783 pll->on, active);
10784
10785 for_each_intel_crtc(dev, crtc) {
10786 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10787 enabled_crtcs++;
10788 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10789 active_crtcs++;
10790 }
10791 WARN(pll->active != active_crtcs,
10792 "pll active crtcs mismatch (expected %i, found %i)\n",
10793 pll->active, active_crtcs);
10794 WARN(pll->refcount != enabled_crtcs,
10795 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10796 pll->refcount, enabled_crtcs);
10797
10798 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
10799 sizeof(dpll_hw_state)),
10800 "pll hw state mismatch\n");
10801 }
10802 }
10803
10804 void
10805 intel_modeset_check_state(struct drm_device *dev)
10806 {
10807 check_connector_state(dev);
10808 check_encoder_state(dev);
10809 check_crtc_state(dev);
10810 check_shared_dpll_state(dev);
10811 }
10812
10813 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10814 int dotclock)
10815 {
10816 /*
10817 * FDI already provided one idea for the dotclock.
10818 * Yell if the encoder disagrees.
10819 */
10820 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10821 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10822 pipe_config->adjusted_mode.crtc_clock, dotclock);
10823 }
10824
10825 static void update_scanline_offset(struct intel_crtc *crtc)
10826 {
10827 struct drm_device *dev = crtc->base.dev;
10828
10829 /*
10830 * The scanline counter increments at the leading edge of hsync.
10831 *
10832 * On most platforms it starts counting from vtotal-1 on the
10833 * first active line. That means the scanline counter value is
10834 * always one less than what we would expect. Ie. just after
10835 * start of vblank, which also occurs at start of hsync (on the
10836 * last active line), the scanline counter will read vblank_start-1.
10837 *
10838 * On gen2 the scanline counter starts counting from 1 instead
10839 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10840 * to keep the value positive), instead of adding one.
10841 *
10842 * On HSW+ the behaviour of the scanline counter depends on the output
10843 * type. For DP ports it behaves like most other platforms, but on HDMI
10844 * there's an extra 1 line difference. So we need to add two instead of
10845 * one to the value.
10846 */
10847 if (IS_GEN2(dev)) {
10848 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
10849 int vtotal;
10850
10851 vtotal = mode->crtc_vtotal;
10852 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10853 vtotal /= 2;
10854
10855 crtc->scanline_offset = vtotal - 1;
10856 } else if (HAS_DDI(dev) &&
10857 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {
10858 crtc->scanline_offset = 2;
10859 } else
10860 crtc->scanline_offset = 1;
10861 }
10862
10863 static int __intel_set_mode(struct drm_crtc *crtc,
10864 struct drm_display_mode *mode,
10865 int x, int y, struct drm_framebuffer *fb)
10866 {
10867 struct drm_device *dev = crtc->dev;
10868 struct drm_i915_private *dev_priv = dev->dev_private;
10869 struct drm_display_mode *saved_mode;
10870 struct intel_crtc_config *pipe_config = NULL;
10871 struct intel_crtc *intel_crtc;
10872 unsigned disable_pipes, prepare_pipes, modeset_pipes;
10873 int ret = 0;
10874
10875 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10876 if (!saved_mode)
10877 return -ENOMEM;
10878
10879 intel_modeset_affected_pipes(crtc, &modeset_pipes,
10880 &prepare_pipes, &disable_pipes);
10881
10882 *saved_mode = crtc->mode;
10883
10884 /* Hack: Because we don't (yet) support global modeset on multiple
10885 * crtcs, we don't keep track of the new mode for more than one crtc.
10886 * Hence simply check whether any bit is set in modeset_pipes in all the
10887 * pieces of code that are not yet converted to deal with mutliple crtcs
10888 * changing their mode at the same time. */
10889 if (modeset_pipes) {
10890 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10891 if (IS_ERR(pipe_config)) {
10892 ret = PTR_ERR(pipe_config);
10893 pipe_config = NULL;
10894
10895 goto out;
10896 }
10897 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10898 "[modeset]");
10899 to_intel_crtc(crtc)->new_config = pipe_config;
10900 }
10901
10902 /*
10903 * See if the config requires any additional preparation, e.g.
10904 * to adjust global state with pipes off. We need to do this
10905 * here so we can get the modeset_pipe updated config for the new
10906 * mode set on this crtc. For other crtcs we need to use the
10907 * adjusted_mode bits in the crtc directly.
10908 */
10909 if (IS_VALLEYVIEW(dev)) {
10910 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10911
10912 /* may have added more to prepare_pipes than we should */
10913 prepare_pipes &= ~disable_pipes;
10914 }
10915
10916 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10917 intel_crtc_disable(&intel_crtc->base);
10918
10919 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10920 if (intel_crtc->base.enabled)
10921 dev_priv->display.crtc_disable(&intel_crtc->base);
10922 }
10923
10924 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10925 * to set it here already despite that we pass it down the callchain.
10926 */
10927 if (modeset_pipes) {
10928 crtc->mode = *mode;
10929 /* mode_set/enable/disable functions rely on a correct pipe
10930 * config. */
10931 to_intel_crtc(crtc)->config = *pipe_config;
10932 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10933
10934 /*
10935 * Calculate and store various constants which
10936 * are later needed by vblank and swap-completion
10937 * timestamping. They are derived from true hwmode.
10938 */
10939 drm_calc_timestamping_constants(crtc,
10940 &pipe_config->adjusted_mode);
10941 }
10942
10943 /* Only after disabling all output pipelines that will be changed can we
10944 * update the the output configuration. */
10945 intel_modeset_update_state(dev, prepare_pipes);
10946
10947 if (dev_priv->display.modeset_global_resources)
10948 dev_priv->display.modeset_global_resources(dev);
10949
10950 /* Set up the DPLL and any encoders state that needs to adjust or depend
10951 * on the DPLL.
10952 */
10953 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10954 struct drm_framebuffer *old_fb = crtc->primary->fb;
10955 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
10956 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10957
10958 mutex_lock(&dev->struct_mutex);
10959 ret = intel_pin_and_fence_fb_obj(dev,
10960 obj,
10961 NULL);
10962 if (ret != 0) {
10963 DRM_ERROR("pin & fence failed\n");
10964 mutex_unlock(&dev->struct_mutex);
10965 goto done;
10966 }
10967 if (old_fb)
10968 intel_unpin_fb_obj(old_obj);
10969 i915_gem_track_fb(old_obj, obj,
10970 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
10971 mutex_unlock(&dev->struct_mutex);
10972
10973 crtc->primary->fb = fb;
10974 crtc->x = x;
10975 crtc->y = y;
10976
10977 ret = dev_priv->display.crtc_mode_set(&intel_crtc->base,
10978 x, y, fb);
10979 if (ret)
10980 goto done;
10981 }
10982
10983 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10984 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10985 update_scanline_offset(intel_crtc);
10986
10987 dev_priv->display.crtc_enable(&intel_crtc->base);
10988 }
10989
10990 /* FIXME: add subpixel order */
10991 done:
10992 if (ret && crtc->enabled)
10993 crtc->mode = *saved_mode;
10994
10995 out:
10996 kfree(pipe_config);
10997 kfree(saved_mode);
10998 return ret;
10999 }
11000
11001 static int intel_set_mode(struct drm_crtc *crtc,
11002 struct drm_display_mode *mode,
11003 int x, int y, struct drm_framebuffer *fb)
11004 {
11005 int ret;
11006
11007 ret = __intel_set_mode(crtc, mode, x, y, fb);
11008
11009 if (ret == 0)
11010 intel_modeset_check_state(crtc->dev);
11011
11012 return ret;
11013 }
11014
11015 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11016 {
11017 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
11018 }
11019
11020 #undef for_each_intel_crtc_masked
11021
11022 static void intel_set_config_free(struct intel_set_config *config)
11023 {
11024 if (!config)
11025 return;
11026
11027 kfree(config->save_connector_encoders);
11028 kfree(config->save_encoder_crtcs);
11029 kfree(config->save_crtc_enabled);
11030 kfree(config);
11031 }
11032
11033 static int intel_set_config_save_state(struct drm_device *dev,
11034 struct intel_set_config *config)
11035 {
11036 struct drm_crtc *crtc;
11037 struct drm_encoder *encoder;
11038 struct drm_connector *connector;
11039 int count;
11040
11041 config->save_crtc_enabled =
11042 kcalloc(dev->mode_config.num_crtc,
11043 sizeof(bool), GFP_KERNEL);
11044 if (!config->save_crtc_enabled)
11045 return -ENOMEM;
11046
11047 config->save_encoder_crtcs =
11048 kcalloc(dev->mode_config.num_encoder,
11049 sizeof(struct drm_crtc *), GFP_KERNEL);
11050 if (!config->save_encoder_crtcs)
11051 return -ENOMEM;
11052
11053 config->save_connector_encoders =
11054 kcalloc(dev->mode_config.num_connector,
11055 sizeof(struct drm_encoder *), GFP_KERNEL);
11056 if (!config->save_connector_encoders)
11057 return -ENOMEM;
11058
11059 /* Copy data. Note that driver private data is not affected.
11060 * Should anything bad happen only the expected state is
11061 * restored, not the drivers personal bookkeeping.
11062 */
11063 count = 0;
11064 for_each_crtc(dev, crtc) {
11065 config->save_crtc_enabled[count++] = crtc->enabled;
11066 }
11067
11068 count = 0;
11069 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11070 config->save_encoder_crtcs[count++] = encoder->crtc;
11071 }
11072
11073 count = 0;
11074 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11075 config->save_connector_encoders[count++] = connector->encoder;
11076 }
11077
11078 return 0;
11079 }
11080
11081 static void intel_set_config_restore_state(struct drm_device *dev,
11082 struct intel_set_config *config)
11083 {
11084 struct intel_crtc *crtc;
11085 struct intel_encoder *encoder;
11086 struct intel_connector *connector;
11087 int count;
11088
11089 count = 0;
11090 for_each_intel_crtc(dev, crtc) {
11091 crtc->new_enabled = config->save_crtc_enabled[count++];
11092
11093 if (crtc->new_enabled)
11094 crtc->new_config = &crtc->config;
11095 else
11096 crtc->new_config = NULL;
11097 }
11098
11099 count = 0;
11100 for_each_intel_encoder(dev, encoder) {
11101 encoder->new_crtc =
11102 to_intel_crtc(config->save_encoder_crtcs[count++]);
11103 }
11104
11105 count = 0;
11106 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11107 connector->new_encoder =
11108 to_intel_encoder(config->save_connector_encoders[count++]);
11109 }
11110 }
11111
11112 static bool
11113 is_crtc_connector_off(struct drm_mode_set *set)
11114 {
11115 int i;
11116
11117 if (set->num_connectors == 0)
11118 return false;
11119
11120 if (WARN_ON(set->connectors == NULL))
11121 return false;
11122
11123 for (i = 0; i < set->num_connectors; i++)
11124 if (set->connectors[i]->encoder &&
11125 set->connectors[i]->encoder->crtc == set->crtc &&
11126 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11127 return true;
11128
11129 return false;
11130 }
11131
11132 static void
11133 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11134 struct intel_set_config *config)
11135 {
11136
11137 /* We should be able to check here if the fb has the same properties
11138 * and then just flip_or_move it */
11139 if (is_crtc_connector_off(set)) {
11140 config->mode_changed = true;
11141 } else if (set->crtc->primary->fb != set->fb) {
11142 /*
11143 * If we have no fb, we can only flip as long as the crtc is
11144 * active, otherwise we need a full mode set. The crtc may
11145 * be active if we've only disabled the primary plane, or
11146 * in fastboot situations.
11147 */
11148 if (set->crtc->primary->fb == NULL) {
11149 struct intel_crtc *intel_crtc =
11150 to_intel_crtc(set->crtc);
11151
11152 if (intel_crtc->active) {
11153 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11154 config->fb_changed = true;
11155 } else {
11156 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11157 config->mode_changed = true;
11158 }
11159 } else if (set->fb == NULL) {
11160 config->mode_changed = true;
11161 } else if (set->fb->pixel_format !=
11162 set->crtc->primary->fb->pixel_format) {
11163 config->mode_changed = true;
11164 } else {
11165 config->fb_changed = true;
11166 }
11167 }
11168
11169 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11170 config->fb_changed = true;
11171
11172 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11173 DRM_DEBUG_KMS("modes are different, full mode set\n");
11174 drm_mode_debug_printmodeline(&set->crtc->mode);
11175 drm_mode_debug_printmodeline(set->mode);
11176 config->mode_changed = true;
11177 }
11178
11179 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11180 set->crtc->base.id, config->mode_changed, config->fb_changed);
11181 }
11182
11183 static int
11184 intel_modeset_stage_output_state(struct drm_device *dev,
11185 struct drm_mode_set *set,
11186 struct intel_set_config *config)
11187 {
11188 struct intel_connector *connector;
11189 struct intel_encoder *encoder;
11190 struct intel_crtc *crtc;
11191 int ro;
11192
11193 /* The upper layers ensure that we either disable a crtc or have a list
11194 * of connectors. For paranoia, double-check this. */
11195 WARN_ON(!set->fb && (set->num_connectors != 0));
11196 WARN_ON(set->fb && (set->num_connectors == 0));
11197
11198 list_for_each_entry(connector, &dev->mode_config.connector_list,
11199 base.head) {
11200 /* Otherwise traverse passed in connector list and get encoders
11201 * for them. */
11202 for (ro = 0; ro < set->num_connectors; ro++) {
11203 if (set->connectors[ro] == &connector->base) {
11204 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11205 break;
11206 }
11207 }
11208
11209 /* If we disable the crtc, disable all its connectors. Also, if
11210 * the connector is on the changing crtc but not on the new
11211 * connector list, disable it. */
11212 if ((!set->fb || ro == set->num_connectors) &&
11213 connector->base.encoder &&
11214 connector->base.encoder->crtc == set->crtc) {
11215 connector->new_encoder = NULL;
11216
11217 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11218 connector->base.base.id,
11219 connector->base.name);
11220 }
11221
11222
11223 if (&connector->new_encoder->base != connector->base.encoder) {
11224 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11225 config->mode_changed = true;
11226 }
11227 }
11228 /* connector->new_encoder is now updated for all connectors. */
11229
11230 /* Update crtc of enabled connectors. */
11231 list_for_each_entry(connector, &dev->mode_config.connector_list,
11232 base.head) {
11233 struct drm_crtc *new_crtc;
11234
11235 if (!connector->new_encoder)
11236 continue;
11237
11238 new_crtc = connector->new_encoder->base.crtc;
11239
11240 for (ro = 0; ro < set->num_connectors; ro++) {
11241 if (set->connectors[ro] == &connector->base)
11242 new_crtc = set->crtc;
11243 }
11244
11245 /* Make sure the new CRTC will work with the encoder */
11246 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11247 new_crtc)) {
11248 return -EINVAL;
11249 }
11250 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11251
11252 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11253 connector->base.base.id,
11254 connector->base.name,
11255 new_crtc->base.id);
11256 }
11257
11258 /* Check for any encoders that needs to be disabled. */
11259 for_each_intel_encoder(dev, encoder) {
11260 int num_connectors = 0;
11261 list_for_each_entry(connector,
11262 &dev->mode_config.connector_list,
11263 base.head) {
11264 if (connector->new_encoder == encoder) {
11265 WARN_ON(!connector->new_encoder->new_crtc);
11266 num_connectors++;
11267 }
11268 }
11269
11270 if (num_connectors == 0)
11271 encoder->new_crtc = NULL;
11272 else if (num_connectors > 1)
11273 return -EINVAL;
11274
11275 /* Only now check for crtc changes so we don't miss encoders
11276 * that will be disabled. */
11277 if (&encoder->new_crtc->base != encoder->base.crtc) {
11278 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11279 config->mode_changed = true;
11280 }
11281 }
11282 /* Now we've also updated encoder->new_crtc for all encoders. */
11283 list_for_each_entry(connector, &dev->mode_config.connector_list,
11284 base.head) {
11285 if (connector->new_encoder)
11286 if (connector->new_encoder != connector->encoder)
11287 connector->encoder = connector->new_encoder;
11288 }
11289 for_each_intel_crtc(dev, crtc) {
11290 crtc->new_enabled = false;
11291
11292 for_each_intel_encoder(dev, encoder) {
11293 if (encoder->new_crtc == crtc) {
11294 crtc->new_enabled = true;
11295 break;
11296 }
11297 }
11298
11299 if (crtc->new_enabled != crtc->base.enabled) {
11300 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11301 crtc->new_enabled ? "en" : "dis");
11302 config->mode_changed = true;
11303 }
11304
11305 if (crtc->new_enabled)
11306 crtc->new_config = &crtc->config;
11307 else
11308 crtc->new_config = NULL;
11309 }
11310
11311 return 0;
11312 }
11313
11314 static void disable_crtc_nofb(struct intel_crtc *crtc)
11315 {
11316 struct drm_device *dev = crtc->base.dev;
11317 struct intel_encoder *encoder;
11318 struct intel_connector *connector;
11319
11320 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11321 pipe_name(crtc->pipe));
11322
11323 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11324 if (connector->new_encoder &&
11325 connector->new_encoder->new_crtc == crtc)
11326 connector->new_encoder = NULL;
11327 }
11328
11329 for_each_intel_encoder(dev, encoder) {
11330 if (encoder->new_crtc == crtc)
11331 encoder->new_crtc = NULL;
11332 }
11333
11334 crtc->new_enabled = false;
11335 crtc->new_config = NULL;
11336 }
11337
11338 static int intel_crtc_set_config(struct drm_mode_set *set)
11339 {
11340 struct drm_device *dev;
11341 struct drm_mode_set save_set;
11342 struct intel_set_config *config;
11343 int ret;
11344
11345 BUG_ON(!set);
11346 BUG_ON(!set->crtc);
11347 BUG_ON(!set->crtc->helper_private);
11348
11349 /* Enforce sane interface api - has been abused by the fb helper. */
11350 BUG_ON(!set->mode && set->fb);
11351 BUG_ON(set->fb && set->num_connectors == 0);
11352
11353 if (set->fb) {
11354 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11355 set->crtc->base.id, set->fb->base.id,
11356 (int)set->num_connectors, set->x, set->y);
11357 } else {
11358 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11359 }
11360
11361 dev = set->crtc->dev;
11362
11363 ret = -ENOMEM;
11364 config = kzalloc(sizeof(*config), GFP_KERNEL);
11365 if (!config)
11366 goto out_config;
11367
11368 ret = intel_set_config_save_state(dev, config);
11369 if (ret)
11370 goto out_config;
11371
11372 save_set.crtc = set->crtc;
11373 save_set.mode = &set->crtc->mode;
11374 save_set.x = set->crtc->x;
11375 save_set.y = set->crtc->y;
11376 save_set.fb = set->crtc->primary->fb;
11377
11378 /* Compute whether we need a full modeset, only an fb base update or no
11379 * change at all. In the future we might also check whether only the
11380 * mode changed, e.g. for LVDS where we only change the panel fitter in
11381 * such cases. */
11382 intel_set_config_compute_mode_changes(set, config);
11383
11384 ret = intel_modeset_stage_output_state(dev, set, config);
11385 if (ret)
11386 goto fail;
11387
11388 if (config->mode_changed) {
11389 ret = intel_set_mode(set->crtc, set->mode,
11390 set->x, set->y, set->fb);
11391 } else if (config->fb_changed) {
11392 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11393
11394 intel_crtc_wait_for_pending_flips(set->crtc);
11395
11396 ret = intel_pipe_set_base(set->crtc,
11397 set->x, set->y, set->fb);
11398
11399 /*
11400 * We need to make sure the primary plane is re-enabled if it
11401 * has previously been turned off.
11402 */
11403 if (!intel_crtc->primary_enabled && ret == 0) {
11404 WARN_ON(!intel_crtc->active);
11405 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11406 }
11407
11408 /*
11409 * In the fastboot case this may be our only check of the
11410 * state after boot. It would be better to only do it on
11411 * the first update, but we don't have a nice way of doing that
11412 * (and really, set_config isn't used much for high freq page
11413 * flipping, so increasing its cost here shouldn't be a big
11414 * deal).
11415 */
11416 if (i915.fastboot && ret == 0)
11417 intel_modeset_check_state(set->crtc->dev);
11418 }
11419
11420 if (ret) {
11421 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11422 set->crtc->base.id, ret);
11423 fail:
11424 intel_set_config_restore_state(dev, config);
11425
11426 /*
11427 * HACK: if the pipe was on, but we didn't have a framebuffer,
11428 * force the pipe off to avoid oopsing in the modeset code
11429 * due to fb==NULL. This should only happen during boot since
11430 * we don't yet reconstruct the FB from the hardware state.
11431 */
11432 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11433 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11434
11435 /* Try to restore the config */
11436 if (config->mode_changed &&
11437 intel_set_mode(save_set.crtc, save_set.mode,
11438 save_set.x, save_set.y, save_set.fb))
11439 DRM_ERROR("failed to restore config after modeset failure\n");
11440 }
11441
11442 out_config:
11443 intel_set_config_free(config);
11444 return ret;
11445 }
11446
11447 static const struct drm_crtc_funcs intel_crtc_funcs = {
11448 .gamma_set = intel_crtc_gamma_set,
11449 .set_config = intel_crtc_set_config,
11450 .destroy = intel_crtc_destroy,
11451 .page_flip = intel_crtc_page_flip,
11452 };
11453
11454 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11455 struct intel_shared_dpll *pll,
11456 struct intel_dpll_hw_state *hw_state)
11457 {
11458 uint32_t val;
11459
11460 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_PLLS))
11461 return false;
11462
11463 val = I915_READ(PCH_DPLL(pll->id));
11464 hw_state->dpll = val;
11465 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11466 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11467
11468 return val & DPLL_VCO_ENABLE;
11469 }
11470
11471 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11472 struct intel_shared_dpll *pll)
11473 {
11474 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
11475 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
11476 }
11477
11478 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11479 struct intel_shared_dpll *pll)
11480 {
11481 /* PCH refclock must be enabled first */
11482 ibx_assert_pch_refclk_enabled(dev_priv);
11483
11484 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11485
11486 /* Wait for the clocks to stabilize. */
11487 POSTING_READ(PCH_DPLL(pll->id));
11488 udelay(150);
11489
11490 /* The pixel multiplier can only be updated once the
11491 * DPLL is enabled and the clocks are stable.
11492 *
11493 * So write it again.
11494 */
11495 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11496 POSTING_READ(PCH_DPLL(pll->id));
11497 udelay(200);
11498 }
11499
11500 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11501 struct intel_shared_dpll *pll)
11502 {
11503 struct drm_device *dev = dev_priv->dev;
11504 struct intel_crtc *crtc;
11505
11506 /* Make sure no transcoder isn't still depending on us. */
11507 for_each_intel_crtc(dev, crtc) {
11508 if (intel_crtc_to_shared_dpll(crtc) == pll)
11509 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11510 }
11511
11512 I915_WRITE(PCH_DPLL(pll->id), 0);
11513 POSTING_READ(PCH_DPLL(pll->id));
11514 udelay(200);
11515 }
11516
11517 static char *ibx_pch_dpll_names[] = {
11518 "PCH DPLL A",
11519 "PCH DPLL B",
11520 };
11521
11522 static void ibx_pch_dpll_init(struct drm_device *dev)
11523 {
11524 struct drm_i915_private *dev_priv = dev->dev_private;
11525 int i;
11526
11527 dev_priv->num_shared_dpll = 2;
11528
11529 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11530 dev_priv->shared_dplls[i].id = i;
11531 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11532 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11533 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11534 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11535 dev_priv->shared_dplls[i].get_hw_state =
11536 ibx_pch_dpll_get_hw_state;
11537 }
11538 }
11539
11540 static void intel_shared_dpll_init(struct drm_device *dev)
11541 {
11542 struct drm_i915_private *dev_priv = dev->dev_private;
11543
11544 if (HAS_DDI(dev))
11545 intel_ddi_pll_init(dev);
11546 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11547 ibx_pch_dpll_init(dev);
11548 else
11549 dev_priv->num_shared_dpll = 0;
11550
11551 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11552 }
11553
11554 static int
11555 intel_primary_plane_disable(struct drm_plane *plane)
11556 {
11557 struct drm_device *dev = plane->dev;
11558 struct intel_crtc *intel_crtc;
11559
11560 if (!plane->fb)
11561 return 0;
11562
11563 BUG_ON(!plane->crtc);
11564
11565 intel_crtc = to_intel_crtc(plane->crtc);
11566
11567 /*
11568 * Even though we checked plane->fb above, it's still possible that
11569 * the primary plane has been implicitly disabled because the crtc
11570 * coordinates given weren't visible, or because we detected
11571 * that it was 100% covered by a sprite plane. Or, the CRTC may be
11572 * off and we've set a fb, but haven't actually turned on the CRTC yet.
11573 * In either case, we need to unpin the FB and let the fb pointer get
11574 * updated, but otherwise we don't need to touch the hardware.
11575 */
11576 if (!intel_crtc->primary_enabled)
11577 goto disable_unpin;
11578
11579 intel_crtc_wait_for_pending_flips(plane->crtc);
11580 intel_disable_primary_hw_plane(plane, plane->crtc);
11581
11582 disable_unpin:
11583 mutex_lock(&dev->struct_mutex);
11584 i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
11585 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11586 intel_unpin_fb_obj(intel_fb_obj(plane->fb));
11587 mutex_unlock(&dev->struct_mutex);
11588 plane->fb = NULL;
11589
11590 return 0;
11591 }
11592
11593 static int
11594 intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11595 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11596 unsigned int crtc_w, unsigned int crtc_h,
11597 uint32_t src_x, uint32_t src_y,
11598 uint32_t src_w, uint32_t src_h)
11599 {
11600 struct drm_device *dev = crtc->dev;
11601 struct drm_i915_private *dev_priv = dev->dev_private;
11602 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11603 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11604 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11605 struct drm_rect dest = {
11606 /* integer pixels */
11607 .x1 = crtc_x,
11608 .y1 = crtc_y,
11609 .x2 = crtc_x + crtc_w,
11610 .y2 = crtc_y + crtc_h,
11611 };
11612 struct drm_rect src = {
11613 /* 16.16 fixed point */
11614 .x1 = src_x,
11615 .y1 = src_y,
11616 .x2 = src_x + src_w,
11617 .y2 = src_y + src_h,
11618 };
11619 const struct drm_rect clip = {
11620 /* integer pixels */
11621 .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
11622 .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
11623 };
11624 const struct {
11625 int crtc_x, crtc_y;
11626 unsigned int crtc_w, crtc_h;
11627 uint32_t src_x, src_y, src_w, src_h;
11628 } orig = {
11629 .crtc_x = crtc_x,
11630 .crtc_y = crtc_y,
11631 .crtc_w = crtc_w,
11632 .crtc_h = crtc_h,
11633 .src_x = src_x,
11634 .src_y = src_y,
11635 .src_w = src_w,
11636 .src_h = src_h,
11637 };
11638 struct intel_plane *intel_plane = to_intel_plane(plane);
11639 bool visible;
11640 int ret;
11641
11642 ret = drm_plane_helper_check_update(plane, crtc, fb,
11643 &src, &dest, &clip,
11644 DRM_PLANE_HELPER_NO_SCALING,
11645 DRM_PLANE_HELPER_NO_SCALING,
11646 false, true, &visible);
11647
11648 if (ret)
11649 return ret;
11650
11651 /*
11652 * If the CRTC isn't enabled, we're just pinning the framebuffer,
11653 * updating the fb pointer, and returning without touching the
11654 * hardware. This allows us to later do a drmModeSetCrtc with fb=-1 to
11655 * turn on the display with all planes setup as desired.
11656 */
11657 if (!crtc->enabled) {
11658 mutex_lock(&dev->struct_mutex);
11659
11660 /*
11661 * If we already called setplane while the crtc was disabled,
11662 * we may have an fb pinned; unpin it.
11663 */
11664 if (plane->fb)
11665 intel_unpin_fb_obj(old_obj);
11666
11667 i915_gem_track_fb(old_obj, obj,
11668 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11669
11670 /* Pin and return without programming hardware */
11671 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11672 mutex_unlock(&dev->struct_mutex);
11673
11674 return ret;
11675 }
11676
11677 intel_crtc_wait_for_pending_flips(crtc);
11678
11679 /*
11680 * If clipping results in a non-visible primary plane, we'll disable
11681 * the primary plane. Note that this is a bit different than what
11682 * happens if userspace explicitly disables the plane by passing fb=0
11683 * because plane->fb still gets set and pinned.
11684 */
11685 if (!visible) {
11686 mutex_lock(&dev->struct_mutex);
11687
11688 /*
11689 * Try to pin the new fb first so that we can bail out if we
11690 * fail.
11691 */
11692 if (plane->fb != fb) {
11693 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11694 if (ret) {
11695 mutex_unlock(&dev->struct_mutex);
11696 return ret;
11697 }
11698 }
11699
11700 i915_gem_track_fb(old_obj, obj,
11701 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11702
11703 if (intel_crtc->primary_enabled)
11704 intel_disable_primary_hw_plane(plane, crtc);
11705
11706
11707 if (plane->fb != fb)
11708 if (plane->fb)
11709 intel_unpin_fb_obj(old_obj);
11710
11711 mutex_unlock(&dev->struct_mutex);
11712
11713 } else {
11714 if (intel_crtc && intel_crtc->active &&
11715 intel_crtc->primary_enabled) {
11716 /*
11717 * FBC does not work on some platforms for rotated
11718 * planes, so disable it when rotation is not 0 and
11719 * update it when rotation is set back to 0.
11720 *
11721 * FIXME: This is redundant with the fbc update done in
11722 * the primary plane enable function except that that
11723 * one is done too late. We eventually need to unify
11724 * this.
11725 */
11726 if (INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11727 dev_priv->fbc.plane == intel_crtc->plane &&
11728 intel_plane->rotation != BIT(DRM_ROTATE_0)) {
11729 intel_disable_fbc(dev);
11730 }
11731 }
11732 ret = intel_pipe_set_base(crtc, src.x1, src.y1, fb);
11733 if (ret)
11734 return ret;
11735
11736 if (!intel_crtc->primary_enabled)
11737 intel_enable_primary_hw_plane(plane, crtc);
11738 }
11739
11740 intel_plane->crtc_x = orig.crtc_x;
11741 intel_plane->crtc_y = orig.crtc_y;
11742 intel_plane->crtc_w = orig.crtc_w;
11743 intel_plane->crtc_h = orig.crtc_h;
11744 intel_plane->src_x = orig.src_x;
11745 intel_plane->src_y = orig.src_y;
11746 intel_plane->src_w = orig.src_w;
11747 intel_plane->src_h = orig.src_h;
11748 intel_plane->obj = obj;
11749
11750 return 0;
11751 }
11752
11753 /* Common destruction function for both primary and cursor planes */
11754 static void intel_plane_destroy(struct drm_plane *plane)
11755 {
11756 struct intel_plane *intel_plane = to_intel_plane(plane);
11757 drm_plane_cleanup(plane);
11758 kfree(intel_plane);
11759 }
11760
11761 static const struct drm_plane_funcs intel_primary_plane_funcs = {
11762 .update_plane = intel_primary_plane_setplane,
11763 .disable_plane = intel_primary_plane_disable,
11764 .destroy = intel_plane_destroy,
11765 .set_property = intel_plane_set_property
11766 };
11767
11768 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11769 int pipe)
11770 {
11771 struct intel_plane *primary;
11772 const uint32_t *intel_primary_formats;
11773 int num_formats;
11774
11775 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11776 if (primary == NULL)
11777 return NULL;
11778
11779 primary->can_scale = false;
11780 primary->max_downscale = 1;
11781 primary->pipe = pipe;
11782 primary->plane = pipe;
11783 primary->rotation = BIT(DRM_ROTATE_0);
11784 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11785 primary->plane = !pipe;
11786
11787 if (INTEL_INFO(dev)->gen <= 3) {
11788 intel_primary_formats = intel_primary_formats_gen2;
11789 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
11790 } else {
11791 intel_primary_formats = intel_primary_formats_gen4;
11792 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
11793 }
11794
11795 drm_universal_plane_init(dev, &primary->base, 0,
11796 &intel_primary_plane_funcs,
11797 intel_primary_formats, num_formats,
11798 DRM_PLANE_TYPE_PRIMARY);
11799
11800 if (INTEL_INFO(dev)->gen >= 4) {
11801 if (!dev->mode_config.rotation_property)
11802 dev->mode_config.rotation_property =
11803 drm_mode_create_rotation_property(dev,
11804 BIT(DRM_ROTATE_0) |
11805 BIT(DRM_ROTATE_180));
11806 if (dev->mode_config.rotation_property)
11807 drm_object_attach_property(&primary->base.base,
11808 dev->mode_config.rotation_property,
11809 primary->rotation);
11810 }
11811
11812 return &primary->base;
11813 }
11814
11815 static int
11816 intel_cursor_plane_disable(struct drm_plane *plane)
11817 {
11818 if (!plane->fb)
11819 return 0;
11820
11821 BUG_ON(!plane->crtc);
11822
11823 return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
11824 }
11825
11826 static int
11827 intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
11828 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11829 unsigned int crtc_w, unsigned int crtc_h,
11830 uint32_t src_x, uint32_t src_y,
11831 uint32_t src_w, uint32_t src_h)
11832 {
11833 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11834 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11835 struct drm_i915_gem_object *obj = intel_fb->obj;
11836 struct drm_rect dest = {
11837 /* integer pixels */
11838 .x1 = crtc_x,
11839 .y1 = crtc_y,
11840 .x2 = crtc_x + crtc_w,
11841 .y2 = crtc_y + crtc_h,
11842 };
11843 struct drm_rect src = {
11844 /* 16.16 fixed point */
11845 .x1 = src_x,
11846 .y1 = src_y,
11847 .x2 = src_x + src_w,
11848 .y2 = src_y + src_h,
11849 };
11850 const struct drm_rect clip = {
11851 /* integer pixels */
11852 .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
11853 .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
11854 };
11855 bool visible;
11856 int ret;
11857
11858 ret = drm_plane_helper_check_update(plane, crtc, fb,
11859 &src, &dest, &clip,
11860 DRM_PLANE_HELPER_NO_SCALING,
11861 DRM_PLANE_HELPER_NO_SCALING,
11862 true, true, &visible);
11863 if (ret)
11864 return ret;
11865
11866 crtc->cursor_x = crtc_x;
11867 crtc->cursor_y = crtc_y;
11868 if (fb != crtc->cursor->fb) {
11869 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
11870 } else {
11871 intel_crtc_update_cursor(crtc, visible);
11872
11873 intel_frontbuffer_flip(crtc->dev,
11874 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe));
11875
11876 return 0;
11877 }
11878 }
11879 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
11880 .update_plane = intel_cursor_plane_update,
11881 .disable_plane = intel_cursor_plane_disable,
11882 .destroy = intel_plane_destroy,
11883 };
11884
11885 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
11886 int pipe)
11887 {
11888 struct intel_plane *cursor;
11889
11890 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
11891 if (cursor == NULL)
11892 return NULL;
11893
11894 cursor->can_scale = false;
11895 cursor->max_downscale = 1;
11896 cursor->pipe = pipe;
11897 cursor->plane = pipe;
11898
11899 drm_universal_plane_init(dev, &cursor->base, 0,
11900 &intel_cursor_plane_funcs,
11901 intel_cursor_formats,
11902 ARRAY_SIZE(intel_cursor_formats),
11903 DRM_PLANE_TYPE_CURSOR);
11904 return &cursor->base;
11905 }
11906
11907 static void intel_crtc_init(struct drm_device *dev, int pipe)
11908 {
11909 struct drm_i915_private *dev_priv = dev->dev_private;
11910 struct intel_crtc *intel_crtc;
11911 struct drm_plane *primary = NULL;
11912 struct drm_plane *cursor = NULL;
11913 int i, ret;
11914
11915 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
11916 if (intel_crtc == NULL)
11917 return;
11918
11919 primary = intel_primary_plane_create(dev, pipe);
11920 if (!primary)
11921 goto fail;
11922
11923 cursor = intel_cursor_plane_create(dev, pipe);
11924 if (!cursor)
11925 goto fail;
11926
11927 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
11928 cursor, &intel_crtc_funcs);
11929 if (ret)
11930 goto fail;
11931
11932 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
11933 for (i = 0; i < 256; i++) {
11934 intel_crtc->lut_r[i] = i;
11935 intel_crtc->lut_g[i] = i;
11936 intel_crtc->lut_b[i] = i;
11937 }
11938
11939 /*
11940 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
11941 * is hooked to pipe B. Hence we want plane A feeding pipe B.
11942 */
11943 intel_crtc->pipe = pipe;
11944 intel_crtc->plane = pipe;
11945 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
11946 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
11947 intel_crtc->plane = !pipe;
11948 }
11949
11950 intel_crtc->cursor_base = ~0;
11951 intel_crtc->cursor_cntl = ~0;
11952 intel_crtc->cursor_size = ~0;
11953
11954 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
11955 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
11956 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
11957 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
11958
11959 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
11960
11961 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
11962 return;
11963
11964 fail:
11965 if (primary)
11966 drm_plane_cleanup(primary);
11967 if (cursor)
11968 drm_plane_cleanup(cursor);
11969 kfree(intel_crtc);
11970 }
11971
11972 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
11973 {
11974 struct drm_encoder *encoder = connector->base.encoder;
11975 struct drm_device *dev = connector->base.dev;
11976
11977 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
11978
11979 if (!encoder)
11980 return INVALID_PIPE;
11981
11982 return to_intel_crtc(encoder->crtc)->pipe;
11983 }
11984
11985 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
11986 struct drm_file *file)
11987 {
11988 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
11989 struct drm_crtc *drmmode_crtc;
11990 struct intel_crtc *crtc;
11991
11992 if (!drm_core_check_feature(dev, DRIVER_MODESET))
11993 return -ENODEV;
11994
11995 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
11996
11997 if (!drmmode_crtc) {
11998 DRM_ERROR("no such CRTC id\n");
11999 return -ENOENT;
12000 }
12001
12002 crtc = to_intel_crtc(drmmode_crtc);
12003 pipe_from_crtc_id->pipe = crtc->pipe;
12004
12005 return 0;
12006 }
12007
12008 static int intel_encoder_clones(struct intel_encoder *encoder)
12009 {
12010 struct drm_device *dev = encoder->base.dev;
12011 struct intel_encoder *source_encoder;
12012 int index_mask = 0;
12013 int entry = 0;
12014
12015 for_each_intel_encoder(dev, source_encoder) {
12016 if (encoders_cloneable(encoder, source_encoder))
12017 index_mask |= (1 << entry);
12018
12019 entry++;
12020 }
12021
12022 return index_mask;
12023 }
12024
12025 static bool has_edp_a(struct drm_device *dev)
12026 {
12027 struct drm_i915_private *dev_priv = dev->dev_private;
12028
12029 if (!IS_MOBILE(dev))
12030 return false;
12031
12032 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12033 return false;
12034
12035 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12036 return false;
12037
12038 return true;
12039 }
12040
12041 const char *intel_output_name(int output)
12042 {
12043 static const char *names[] = {
12044 [INTEL_OUTPUT_UNUSED] = "Unused",
12045 [INTEL_OUTPUT_ANALOG] = "Analog",
12046 [INTEL_OUTPUT_DVO] = "DVO",
12047 [INTEL_OUTPUT_SDVO] = "SDVO",
12048 [INTEL_OUTPUT_LVDS] = "LVDS",
12049 [INTEL_OUTPUT_TVOUT] = "TV",
12050 [INTEL_OUTPUT_HDMI] = "HDMI",
12051 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
12052 [INTEL_OUTPUT_EDP] = "eDP",
12053 [INTEL_OUTPUT_DSI] = "DSI",
12054 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
12055 };
12056
12057 if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
12058 return "Invalid";
12059
12060 return names[output];
12061 }
12062
12063 static bool intel_crt_present(struct drm_device *dev)
12064 {
12065 struct drm_i915_private *dev_priv = dev->dev_private;
12066
12067 if (IS_ULT(dev))
12068 return false;
12069
12070 if (IS_CHERRYVIEW(dev))
12071 return false;
12072
12073 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12074 return false;
12075
12076 return true;
12077 }
12078
12079 static void intel_setup_outputs(struct drm_device *dev)
12080 {
12081 struct drm_i915_private *dev_priv = dev->dev_private;
12082 struct intel_encoder *encoder;
12083 bool dpd_is_edp = false;
12084
12085 intel_lvds_init(dev);
12086
12087 if (intel_crt_present(dev))
12088 intel_crt_init(dev);
12089
12090 if (HAS_DDI(dev)) {
12091 int found;
12092
12093 /* Haswell uses DDI functions to detect digital outputs */
12094 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12095 /* DDI A only supports eDP */
12096 if (found)
12097 intel_ddi_init(dev, PORT_A);
12098
12099 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12100 * register */
12101 found = I915_READ(SFUSE_STRAP);
12102
12103 if (found & SFUSE_STRAP_DDIB_DETECTED)
12104 intel_ddi_init(dev, PORT_B);
12105 if (found & SFUSE_STRAP_DDIC_DETECTED)
12106 intel_ddi_init(dev, PORT_C);
12107 if (found & SFUSE_STRAP_DDID_DETECTED)
12108 intel_ddi_init(dev, PORT_D);
12109 } else if (HAS_PCH_SPLIT(dev)) {
12110 int found;
12111 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12112
12113 if (has_edp_a(dev))
12114 intel_dp_init(dev, DP_A, PORT_A);
12115
12116 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12117 /* PCH SDVOB multiplex with HDMIB */
12118 found = intel_sdvo_init(dev, PCH_SDVOB, true);
12119 if (!found)
12120 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12121 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12122 intel_dp_init(dev, PCH_DP_B, PORT_B);
12123 }
12124
12125 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12126 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12127
12128 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12129 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12130
12131 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12132 intel_dp_init(dev, PCH_DP_C, PORT_C);
12133
12134 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12135 intel_dp_init(dev, PCH_DP_D, PORT_D);
12136 } else if (IS_VALLEYVIEW(dev)) {
12137 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
12138 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12139 PORT_B);
12140 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
12141 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12142 }
12143
12144 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
12145 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12146 PORT_C);
12147 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
12148 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12149 }
12150
12151 if (IS_CHERRYVIEW(dev)) {
12152 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) {
12153 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12154 PORT_D);
12155 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12156 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12157 }
12158 }
12159
12160 intel_dsi_init(dev);
12161 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12162 bool found = false;
12163
12164 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12165 DRM_DEBUG_KMS("probing SDVOB\n");
12166 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12167 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12168 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12169 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12170 }
12171
12172 if (!found && SUPPORTS_INTEGRATED_DP(dev))
12173 intel_dp_init(dev, DP_B, PORT_B);
12174 }
12175
12176 /* Before G4X SDVOC doesn't have its own detect register */
12177
12178 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12179 DRM_DEBUG_KMS("probing SDVOC\n");
12180 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12181 }
12182
12183 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12184
12185 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12186 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12187 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12188 }
12189 if (SUPPORTS_INTEGRATED_DP(dev))
12190 intel_dp_init(dev, DP_C, PORT_C);
12191 }
12192
12193 if (SUPPORTS_INTEGRATED_DP(dev) &&
12194 (I915_READ(DP_D) & DP_DETECTED))
12195 intel_dp_init(dev, DP_D, PORT_D);
12196 } else if (IS_GEN2(dev))
12197 intel_dvo_init(dev);
12198
12199 if (SUPPORTS_TV(dev))
12200 intel_tv_init(dev);
12201
12202 intel_edp_psr_init(dev);
12203
12204 for_each_intel_encoder(dev, encoder) {
12205 encoder->base.possible_crtcs = encoder->crtc_mask;
12206 encoder->base.possible_clones =
12207 intel_encoder_clones(encoder);
12208 }
12209
12210 intel_init_pch_refclk(dev);
12211
12212 drm_helper_move_panel_connectors_to_head(dev);
12213 }
12214
12215 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12216 {
12217 struct drm_device *dev = fb->dev;
12218 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12219
12220 drm_framebuffer_cleanup(fb);
12221 mutex_lock(&dev->struct_mutex);
12222 WARN_ON(!intel_fb->obj->framebuffer_references--);
12223 drm_gem_object_unreference(&intel_fb->obj->base);
12224 mutex_unlock(&dev->struct_mutex);
12225 kfree(intel_fb);
12226 }
12227
12228 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12229 struct drm_file *file,
12230 unsigned int *handle)
12231 {
12232 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12233 struct drm_i915_gem_object *obj = intel_fb->obj;
12234
12235 return drm_gem_handle_create(file, &obj->base, handle);
12236 }
12237
12238 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12239 .destroy = intel_user_framebuffer_destroy,
12240 .create_handle = intel_user_framebuffer_create_handle,
12241 };
12242
12243 static int intel_framebuffer_init(struct drm_device *dev,
12244 struct intel_framebuffer *intel_fb,
12245 struct drm_mode_fb_cmd2 *mode_cmd,
12246 struct drm_i915_gem_object *obj)
12247 {
12248 int aligned_height;
12249 int pitch_limit;
12250 int ret;
12251
12252 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12253
12254 if (obj->tiling_mode == I915_TILING_Y) {
12255 DRM_DEBUG("hardware does not support tiling Y\n");
12256 return -EINVAL;
12257 }
12258
12259 if (mode_cmd->pitches[0] & 63) {
12260 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12261 mode_cmd->pitches[0]);
12262 return -EINVAL;
12263 }
12264
12265 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12266 pitch_limit = 32*1024;
12267 } else if (INTEL_INFO(dev)->gen >= 4) {
12268 if (obj->tiling_mode)
12269 pitch_limit = 16*1024;
12270 else
12271 pitch_limit = 32*1024;
12272 } else if (INTEL_INFO(dev)->gen >= 3) {
12273 if (obj->tiling_mode)
12274 pitch_limit = 8*1024;
12275 else
12276 pitch_limit = 16*1024;
12277 } else
12278 /* XXX DSPC is limited to 4k tiled */
12279 pitch_limit = 8*1024;
12280
12281 if (mode_cmd->pitches[0] > pitch_limit) {
12282 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12283 obj->tiling_mode ? "tiled" : "linear",
12284 mode_cmd->pitches[0], pitch_limit);
12285 return -EINVAL;
12286 }
12287
12288 if (obj->tiling_mode != I915_TILING_NONE &&
12289 mode_cmd->pitches[0] != obj->stride) {
12290 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12291 mode_cmd->pitches[0], obj->stride);
12292 return -EINVAL;
12293 }
12294
12295 /* Reject formats not supported by any plane early. */
12296 switch (mode_cmd->pixel_format) {
12297 case DRM_FORMAT_C8:
12298 case DRM_FORMAT_RGB565:
12299 case DRM_FORMAT_XRGB8888:
12300 case DRM_FORMAT_ARGB8888:
12301 break;
12302 case DRM_FORMAT_XRGB1555:
12303 case DRM_FORMAT_ARGB1555:
12304 if (INTEL_INFO(dev)->gen > 3) {
12305 DRM_DEBUG("unsupported pixel format: %s\n",
12306 drm_get_format_name(mode_cmd->pixel_format));
12307 return -EINVAL;
12308 }
12309 break;
12310 case DRM_FORMAT_XBGR8888:
12311 case DRM_FORMAT_ABGR8888:
12312 case DRM_FORMAT_XRGB2101010:
12313 case DRM_FORMAT_ARGB2101010:
12314 case DRM_FORMAT_XBGR2101010:
12315 case DRM_FORMAT_ABGR2101010:
12316 if (INTEL_INFO(dev)->gen < 4) {
12317 DRM_DEBUG("unsupported pixel format: %s\n",
12318 drm_get_format_name(mode_cmd->pixel_format));
12319 return -EINVAL;
12320 }
12321 break;
12322 case DRM_FORMAT_YUYV:
12323 case DRM_FORMAT_UYVY:
12324 case DRM_FORMAT_YVYU:
12325 case DRM_FORMAT_VYUY:
12326 if (INTEL_INFO(dev)->gen < 5) {
12327 DRM_DEBUG("unsupported pixel format: %s\n",
12328 drm_get_format_name(mode_cmd->pixel_format));
12329 return -EINVAL;
12330 }
12331 break;
12332 default:
12333 DRM_DEBUG("unsupported pixel format: %s\n",
12334 drm_get_format_name(mode_cmd->pixel_format));
12335 return -EINVAL;
12336 }
12337
12338 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12339 if (mode_cmd->offsets[0] != 0)
12340 return -EINVAL;
12341
12342 aligned_height = intel_align_height(dev, mode_cmd->height,
12343 obj->tiling_mode);
12344 /* FIXME drm helper for size checks (especially planar formats)? */
12345 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12346 return -EINVAL;
12347
12348 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12349 intel_fb->obj = obj;
12350 intel_fb->obj->framebuffer_references++;
12351
12352 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12353 if (ret) {
12354 DRM_ERROR("framebuffer init failed %d\n", ret);
12355 return ret;
12356 }
12357
12358 return 0;
12359 }
12360
12361 static struct drm_framebuffer *
12362 intel_user_framebuffer_create(struct drm_device *dev,
12363 struct drm_file *filp,
12364 struct drm_mode_fb_cmd2 *mode_cmd)
12365 {
12366 struct drm_i915_gem_object *obj;
12367
12368 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12369 mode_cmd->handles[0]));
12370 if (&obj->base == NULL)
12371 return ERR_PTR(-ENOENT);
12372
12373 return intel_framebuffer_create(dev, mode_cmd, obj);
12374 }
12375
12376 #ifndef CONFIG_DRM_I915_FBDEV
12377 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12378 {
12379 }
12380 #endif
12381
12382 static const struct drm_mode_config_funcs intel_mode_funcs = {
12383 .fb_create = intel_user_framebuffer_create,
12384 .output_poll_changed = intel_fbdev_output_poll_changed,
12385 };
12386
12387 /* Set up chip specific display functions */
12388 static void intel_init_display(struct drm_device *dev)
12389 {
12390 struct drm_i915_private *dev_priv = dev->dev_private;
12391
12392 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12393 dev_priv->display.find_dpll = g4x_find_best_dpll;
12394 else if (IS_CHERRYVIEW(dev))
12395 dev_priv->display.find_dpll = chv_find_best_dpll;
12396 else if (IS_VALLEYVIEW(dev))
12397 dev_priv->display.find_dpll = vlv_find_best_dpll;
12398 else if (IS_PINEVIEW(dev))
12399 dev_priv->display.find_dpll = pnv_find_best_dpll;
12400 else
12401 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12402
12403 if (HAS_DDI(dev)) {
12404 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12405 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12406 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
12407 dev_priv->display.crtc_enable = haswell_crtc_enable;
12408 dev_priv->display.crtc_disable = haswell_crtc_disable;
12409 dev_priv->display.off = ironlake_crtc_off;
12410 dev_priv->display.update_primary_plane =
12411 ironlake_update_primary_plane;
12412 } else if (HAS_PCH_SPLIT(dev)) {
12413 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12414 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12415 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
12416 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12417 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12418 dev_priv->display.off = ironlake_crtc_off;
12419 dev_priv->display.update_primary_plane =
12420 ironlake_update_primary_plane;
12421 } else if (IS_VALLEYVIEW(dev)) {
12422 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12423 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12424 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12425 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12426 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12427 dev_priv->display.off = i9xx_crtc_off;
12428 dev_priv->display.update_primary_plane =
12429 i9xx_update_primary_plane;
12430 } else {
12431 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12432 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12433 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12434 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12435 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12436 dev_priv->display.off = i9xx_crtc_off;
12437 dev_priv->display.update_primary_plane =
12438 i9xx_update_primary_plane;
12439 }
12440
12441 /* Returns the core display clock speed */
12442 if (IS_VALLEYVIEW(dev))
12443 dev_priv->display.get_display_clock_speed =
12444 valleyview_get_display_clock_speed;
12445 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12446 dev_priv->display.get_display_clock_speed =
12447 i945_get_display_clock_speed;
12448 else if (IS_I915G(dev))
12449 dev_priv->display.get_display_clock_speed =
12450 i915_get_display_clock_speed;
12451 else if (IS_I945GM(dev) || IS_845G(dev))
12452 dev_priv->display.get_display_clock_speed =
12453 i9xx_misc_get_display_clock_speed;
12454 else if (IS_PINEVIEW(dev))
12455 dev_priv->display.get_display_clock_speed =
12456 pnv_get_display_clock_speed;
12457 else if (IS_I915GM(dev))
12458 dev_priv->display.get_display_clock_speed =
12459 i915gm_get_display_clock_speed;
12460 else if (IS_I865G(dev))
12461 dev_priv->display.get_display_clock_speed =
12462 i865_get_display_clock_speed;
12463 else if (IS_I85X(dev))
12464 dev_priv->display.get_display_clock_speed =
12465 i855_get_display_clock_speed;
12466 else /* 852, 830 */
12467 dev_priv->display.get_display_clock_speed =
12468 i830_get_display_clock_speed;
12469
12470 if (IS_G4X(dev)) {
12471 dev_priv->display.write_eld = g4x_write_eld;
12472 } else if (IS_GEN5(dev)) {
12473 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12474 dev_priv->display.write_eld = ironlake_write_eld;
12475 } else if (IS_GEN6(dev)) {
12476 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12477 dev_priv->display.write_eld = ironlake_write_eld;
12478 dev_priv->display.modeset_global_resources =
12479 snb_modeset_global_resources;
12480 } else if (IS_IVYBRIDGE(dev)) {
12481 /* FIXME: detect B0+ stepping and use auto training */
12482 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12483 dev_priv->display.write_eld = ironlake_write_eld;
12484 dev_priv->display.modeset_global_resources =
12485 ivb_modeset_global_resources;
12486 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
12487 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12488 dev_priv->display.write_eld = haswell_write_eld;
12489 dev_priv->display.modeset_global_resources =
12490 haswell_modeset_global_resources;
12491 } else if (IS_VALLEYVIEW(dev)) {
12492 dev_priv->display.modeset_global_resources =
12493 valleyview_modeset_global_resources;
12494 dev_priv->display.write_eld = ironlake_write_eld;
12495 }
12496
12497 /* Default just returns -ENODEV to indicate unsupported */
12498 dev_priv->display.queue_flip = intel_default_queue_flip;
12499
12500 switch (INTEL_INFO(dev)->gen) {
12501 case 2:
12502 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12503 break;
12504
12505 case 3:
12506 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12507 break;
12508
12509 case 4:
12510 case 5:
12511 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12512 break;
12513
12514 case 6:
12515 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12516 break;
12517 case 7:
12518 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12519 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12520 break;
12521 }
12522
12523 intel_panel_init_backlight_funcs(dev);
12524 }
12525
12526 /*
12527 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12528 * resume, or other times. This quirk makes sure that's the case for
12529 * affected systems.
12530 */
12531 static void quirk_pipea_force(struct drm_device *dev)
12532 {
12533 struct drm_i915_private *dev_priv = dev->dev_private;
12534
12535 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12536 DRM_INFO("applying pipe a force quirk\n");
12537 }
12538
12539 /*
12540 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12541 */
12542 static void quirk_ssc_force_disable(struct drm_device *dev)
12543 {
12544 struct drm_i915_private *dev_priv = dev->dev_private;
12545 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12546 DRM_INFO("applying lvds SSC disable quirk\n");
12547 }
12548
12549 /*
12550 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12551 * brightness value
12552 */
12553 static void quirk_invert_brightness(struct drm_device *dev)
12554 {
12555 struct drm_i915_private *dev_priv = dev->dev_private;
12556 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
12557 DRM_INFO("applying inverted panel brightness quirk\n");
12558 }
12559
12560 /* Some VBT's incorrectly indicate no backlight is present */
12561 static void quirk_backlight_present(struct drm_device *dev)
12562 {
12563 struct drm_i915_private *dev_priv = dev->dev_private;
12564 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
12565 DRM_INFO("applying backlight present quirk\n");
12566 }
12567
12568 struct intel_quirk {
12569 int device;
12570 int subsystem_vendor;
12571 int subsystem_device;
12572 void (*hook)(struct drm_device *dev);
12573 };
12574
12575 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12576 struct intel_dmi_quirk {
12577 void (*hook)(struct drm_device *dev);
12578 const struct dmi_system_id (*dmi_id_list)[];
12579 };
12580
12581 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12582 {
12583 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12584 return 1;
12585 }
12586
12587 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12588 {
12589 .dmi_id_list = &(const struct dmi_system_id[]) {
12590 {
12591 .callback = intel_dmi_reverse_brightness,
12592 .ident = "NCR Corporation",
12593 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12594 DMI_MATCH(DMI_PRODUCT_NAME, ""),
12595 },
12596 },
12597 { } /* terminating entry */
12598 },
12599 .hook = quirk_invert_brightness,
12600 },
12601 };
12602
12603 static struct intel_quirk intel_quirks[] = {
12604 /* HP Mini needs pipe A force quirk (LP: #322104) */
12605 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
12606
12607 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12608 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12609
12610 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12611 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12612
12613 /* Lenovo U160 cannot use SSC on LVDS */
12614 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
12615
12616 /* Sony Vaio Y cannot use SSC on LVDS */
12617 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
12618
12619 /* Acer Aspire 5734Z must invert backlight brightness */
12620 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12621
12622 /* Acer/eMachines G725 */
12623 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12624
12625 /* Acer/eMachines e725 */
12626 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12627
12628 /* Acer/Packard Bell NCL20 */
12629 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12630
12631 /* Acer Aspire 4736Z */
12632 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
12633
12634 /* Acer Aspire 5336 */
12635 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
12636
12637 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12638 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
12639
12640 /* Toshiba CB35 Chromebook (Celeron 2955U) */
12641 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
12642
12643 /* HP Chromebook 14 (Celeron 2955U) */
12644 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
12645 };
12646
12647 static void intel_init_quirks(struct drm_device *dev)
12648 {
12649 struct pci_dev *d = dev->pdev;
12650 int i;
12651
12652 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12653 struct intel_quirk *q = &intel_quirks[i];
12654
12655 if (d->device == q->device &&
12656 (d->subsystem_vendor == q->subsystem_vendor ||
12657 q->subsystem_vendor == PCI_ANY_ID) &&
12658 (d->subsystem_device == q->subsystem_device ||
12659 q->subsystem_device == PCI_ANY_ID))
12660 q->hook(dev);
12661 }
12662 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12663 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12664 intel_dmi_quirks[i].hook(dev);
12665 }
12666 }
12667
12668 /* Disable the VGA plane that we never use */
12669 static void i915_disable_vga(struct drm_device *dev)
12670 {
12671 struct drm_i915_private *dev_priv = dev->dev_private;
12672 u8 sr1;
12673 u32 vga_reg = i915_vgacntrl_reg(dev);
12674
12675 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12676 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
12677 outb(SR01, VGA_SR_INDEX);
12678 sr1 = inb(VGA_SR_DATA);
12679 outb(sr1 | 1<<5, VGA_SR_DATA);
12680 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12681 udelay(300);
12682
12683 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
12684 POSTING_READ(vga_reg);
12685 }
12686
12687 void intel_modeset_init_hw(struct drm_device *dev)
12688 {
12689 intel_prepare_ddi(dev);
12690
12691 if (IS_VALLEYVIEW(dev))
12692 vlv_update_cdclk(dev);
12693
12694 intel_init_clock_gating(dev);
12695
12696 intel_enable_gt_powersave(dev);
12697 }
12698
12699 void intel_modeset_suspend_hw(struct drm_device *dev)
12700 {
12701 intel_suspend_hw(dev);
12702 }
12703
12704 void intel_modeset_init(struct drm_device *dev)
12705 {
12706 struct drm_i915_private *dev_priv = dev->dev_private;
12707 int sprite, ret;
12708 enum pipe pipe;
12709 struct intel_crtc *crtc;
12710
12711 drm_mode_config_init(dev);
12712
12713 dev->mode_config.min_width = 0;
12714 dev->mode_config.min_height = 0;
12715
12716 dev->mode_config.preferred_depth = 24;
12717 dev->mode_config.prefer_shadow = 1;
12718
12719 dev->mode_config.funcs = &intel_mode_funcs;
12720
12721 intel_init_quirks(dev);
12722
12723 intel_init_pm(dev);
12724
12725 if (INTEL_INFO(dev)->num_pipes == 0)
12726 return;
12727
12728 intel_init_display(dev);
12729
12730 if (IS_GEN2(dev)) {
12731 dev->mode_config.max_width = 2048;
12732 dev->mode_config.max_height = 2048;
12733 } else if (IS_GEN3(dev)) {
12734 dev->mode_config.max_width = 4096;
12735 dev->mode_config.max_height = 4096;
12736 } else {
12737 dev->mode_config.max_width = 8192;
12738 dev->mode_config.max_height = 8192;
12739 }
12740
12741 if (IS_845G(dev) || IS_I865G(dev)) {
12742 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
12743 dev->mode_config.cursor_height = 1023;
12744 } else if (IS_GEN2(dev)) {
12745 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
12746 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
12747 } else {
12748 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
12749 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
12750 }
12751
12752 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
12753
12754 DRM_DEBUG_KMS("%d display pipe%s available.\n",
12755 INTEL_INFO(dev)->num_pipes,
12756 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
12757
12758 for_each_pipe(dev_priv, pipe) {
12759 intel_crtc_init(dev, pipe);
12760 for_each_sprite(pipe, sprite) {
12761 ret = intel_plane_init(dev, pipe, sprite);
12762 if (ret)
12763 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
12764 pipe_name(pipe), sprite_name(pipe, sprite), ret);
12765 }
12766 }
12767
12768 intel_init_dpio(dev);
12769
12770 intel_shared_dpll_init(dev);
12771
12772 /* Just disable it once at startup */
12773 i915_disable_vga(dev);
12774 intel_setup_outputs(dev);
12775
12776 /* Just in case the BIOS is doing something questionable. */
12777 intel_disable_fbc(dev);
12778
12779 drm_modeset_lock_all(dev);
12780 intel_modeset_setup_hw_state(dev, false);
12781 drm_modeset_unlock_all(dev);
12782
12783 for_each_intel_crtc(dev, crtc) {
12784 if (!crtc->active)
12785 continue;
12786
12787 /*
12788 * Note that reserving the BIOS fb up front prevents us
12789 * from stuffing other stolen allocations like the ring
12790 * on top. This prevents some ugliness at boot time, and
12791 * can even allow for smooth boot transitions if the BIOS
12792 * fb is large enough for the active pipe configuration.
12793 */
12794 if (dev_priv->display.get_plane_config) {
12795 dev_priv->display.get_plane_config(crtc,
12796 &crtc->plane_config);
12797 /*
12798 * If the fb is shared between multiple heads, we'll
12799 * just get the first one.
12800 */
12801 intel_find_plane_obj(crtc, &crtc->plane_config);
12802 }
12803 }
12804 }
12805
12806 static void intel_enable_pipe_a(struct drm_device *dev)
12807 {
12808 struct intel_connector *connector;
12809 struct drm_connector *crt = NULL;
12810 struct intel_load_detect_pipe load_detect_temp;
12811 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
12812
12813 /* We can't just switch on the pipe A, we need to set things up with a
12814 * proper mode and output configuration. As a gross hack, enable pipe A
12815 * by enabling the load detect pipe once. */
12816 list_for_each_entry(connector,
12817 &dev->mode_config.connector_list,
12818 base.head) {
12819 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
12820 crt = &connector->base;
12821 break;
12822 }
12823 }
12824
12825 if (!crt)
12826 return;
12827
12828 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
12829 intel_release_load_detect_pipe(crt, &load_detect_temp);
12830 }
12831
12832 static bool
12833 intel_check_plane_mapping(struct intel_crtc *crtc)
12834 {
12835 struct drm_device *dev = crtc->base.dev;
12836 struct drm_i915_private *dev_priv = dev->dev_private;
12837 u32 reg, val;
12838
12839 if (INTEL_INFO(dev)->num_pipes == 1)
12840 return true;
12841
12842 reg = DSPCNTR(!crtc->plane);
12843 val = I915_READ(reg);
12844
12845 if ((val & DISPLAY_PLANE_ENABLE) &&
12846 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
12847 return false;
12848
12849 return true;
12850 }
12851
12852 static void intel_sanitize_crtc(struct intel_crtc *crtc)
12853 {
12854 struct drm_device *dev = crtc->base.dev;
12855 struct drm_i915_private *dev_priv = dev->dev_private;
12856 u32 reg;
12857
12858 /* Clear any frame start delays used for debugging left by the BIOS */
12859 reg = PIPECONF(crtc->config.cpu_transcoder);
12860 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
12861
12862 /* restore vblank interrupts to correct state */
12863 if (crtc->active)
12864 drm_vblank_on(dev, crtc->pipe);
12865 else
12866 drm_vblank_off(dev, crtc->pipe);
12867
12868 /* We need to sanitize the plane -> pipe mapping first because this will
12869 * disable the crtc (and hence change the state) if it is wrong. Note
12870 * that gen4+ has a fixed plane -> pipe mapping. */
12871 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
12872 struct intel_connector *connector;
12873 bool plane;
12874
12875 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
12876 crtc->base.base.id);
12877
12878 /* Pipe has the wrong plane attached and the plane is active.
12879 * Temporarily change the plane mapping and disable everything
12880 * ... */
12881 plane = crtc->plane;
12882 crtc->plane = !plane;
12883 crtc->primary_enabled = true;
12884 dev_priv->display.crtc_disable(&crtc->base);
12885 crtc->plane = plane;
12886
12887 /* ... and break all links. */
12888 list_for_each_entry(connector, &dev->mode_config.connector_list,
12889 base.head) {
12890 if (connector->encoder->base.crtc != &crtc->base)
12891 continue;
12892
12893 connector->base.dpms = DRM_MODE_DPMS_OFF;
12894 connector->base.encoder = NULL;
12895 }
12896 /* multiple connectors may have the same encoder:
12897 * handle them and break crtc link separately */
12898 list_for_each_entry(connector, &dev->mode_config.connector_list,
12899 base.head)
12900 if (connector->encoder->base.crtc == &crtc->base) {
12901 connector->encoder->base.crtc = NULL;
12902 connector->encoder->connectors_active = false;
12903 }
12904
12905 WARN_ON(crtc->active);
12906 crtc->base.enabled = false;
12907 }
12908
12909 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
12910 crtc->pipe == PIPE_A && !crtc->active) {
12911 /* BIOS forgot to enable pipe A, this mostly happens after
12912 * resume. Force-enable the pipe to fix this, the update_dpms
12913 * call below we restore the pipe to the right state, but leave
12914 * the required bits on. */
12915 intel_enable_pipe_a(dev);
12916 }
12917
12918 /* Adjust the state of the output pipe according to whether we
12919 * have active connectors/encoders. */
12920 intel_crtc_update_dpms(&crtc->base);
12921
12922 if (crtc->active != crtc->base.enabled) {
12923 struct intel_encoder *encoder;
12924
12925 /* This can happen either due to bugs in the get_hw_state
12926 * functions or because the pipe is force-enabled due to the
12927 * pipe A quirk. */
12928 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
12929 crtc->base.base.id,
12930 crtc->base.enabled ? "enabled" : "disabled",
12931 crtc->active ? "enabled" : "disabled");
12932
12933 crtc->base.enabled = crtc->active;
12934
12935 /* Because we only establish the connector -> encoder ->
12936 * crtc links if something is active, this means the
12937 * crtc is now deactivated. Break the links. connector
12938 * -> encoder links are only establish when things are
12939 * actually up, hence no need to break them. */
12940 WARN_ON(crtc->active);
12941
12942 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
12943 WARN_ON(encoder->connectors_active);
12944 encoder->base.crtc = NULL;
12945 }
12946 }
12947
12948 if (crtc->active || IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen < 5) {
12949 /*
12950 * We start out with underrun reporting disabled to avoid races.
12951 * For correct bookkeeping mark this on active crtcs.
12952 *
12953 * Also on gmch platforms we dont have any hardware bits to
12954 * disable the underrun reporting. Which means we need to start
12955 * out with underrun reporting disabled also on inactive pipes,
12956 * since otherwise we'll complain about the garbage we read when
12957 * e.g. coming up after runtime pm.
12958 *
12959 * No protection against concurrent access is required - at
12960 * worst a fifo underrun happens which also sets this to false.
12961 */
12962 crtc->cpu_fifo_underrun_disabled = true;
12963 crtc->pch_fifo_underrun_disabled = true;
12964
12965 update_scanline_offset(crtc);
12966 }
12967 }
12968
12969 static void intel_sanitize_encoder(struct intel_encoder *encoder)
12970 {
12971 struct intel_connector *connector;
12972 struct drm_device *dev = encoder->base.dev;
12973
12974 /* We need to check both for a crtc link (meaning that the
12975 * encoder is active and trying to read from a pipe) and the
12976 * pipe itself being active. */
12977 bool has_active_crtc = encoder->base.crtc &&
12978 to_intel_crtc(encoder->base.crtc)->active;
12979
12980 if (encoder->connectors_active && !has_active_crtc) {
12981 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
12982 encoder->base.base.id,
12983 encoder->base.name);
12984
12985 /* Connector is active, but has no active pipe. This is
12986 * fallout from our resume register restoring. Disable
12987 * the encoder manually again. */
12988 if (encoder->base.crtc) {
12989 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
12990 encoder->base.base.id,
12991 encoder->base.name);
12992 encoder->disable(encoder);
12993 if (encoder->post_disable)
12994 encoder->post_disable(encoder);
12995 }
12996 encoder->base.crtc = NULL;
12997 encoder->connectors_active = false;
12998
12999 /* Inconsistent output/port/pipe state happens presumably due to
13000 * a bug in one of the get_hw_state functions. Or someplace else
13001 * in our code, like the register restore mess on resume. Clamp
13002 * things to off as a safer default. */
13003 list_for_each_entry(connector,
13004 &dev->mode_config.connector_list,
13005 base.head) {
13006 if (connector->encoder != encoder)
13007 continue;
13008 connector->base.dpms = DRM_MODE_DPMS_OFF;
13009 connector->base.encoder = NULL;
13010 }
13011 }
13012 /* Enabled encoders without active connectors will be fixed in
13013 * the crtc fixup. */
13014 }
13015
13016 void i915_redisable_vga_power_on(struct drm_device *dev)
13017 {
13018 struct drm_i915_private *dev_priv = dev->dev_private;
13019 u32 vga_reg = i915_vgacntrl_reg(dev);
13020
13021 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13022 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13023 i915_disable_vga(dev);
13024 }
13025 }
13026
13027 void i915_redisable_vga(struct drm_device *dev)
13028 {
13029 struct drm_i915_private *dev_priv = dev->dev_private;
13030
13031 /* This function can be called both from intel_modeset_setup_hw_state or
13032 * at a very early point in our resume sequence, where the power well
13033 * structures are not yet restored. Since this function is at a very
13034 * paranoid "someone might have enabled VGA while we were not looking"
13035 * level, just check if the power well is enabled instead of trying to
13036 * follow the "don't touch the power well if we don't need it" policy
13037 * the rest of the driver uses. */
13038 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
13039 return;
13040
13041 i915_redisable_vga_power_on(dev);
13042 }
13043
13044 static bool primary_get_hw_state(struct intel_crtc *crtc)
13045 {
13046 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13047
13048 if (!crtc->active)
13049 return false;
13050
13051 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13052 }
13053
13054 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13055 {
13056 struct drm_i915_private *dev_priv = dev->dev_private;
13057 enum pipe pipe;
13058 struct intel_crtc *crtc;
13059 struct intel_encoder *encoder;
13060 struct intel_connector *connector;
13061 int i;
13062
13063 for_each_intel_crtc(dev, crtc) {
13064 memset(&crtc->config, 0, sizeof(crtc->config));
13065
13066 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13067
13068 crtc->active = dev_priv->display.get_pipe_config(crtc,
13069 &crtc->config);
13070
13071 crtc->base.enabled = crtc->active;
13072 crtc->primary_enabled = primary_get_hw_state(crtc);
13073
13074 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13075 crtc->base.base.id,
13076 crtc->active ? "enabled" : "disabled");
13077 }
13078
13079 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13080 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13081
13082 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
13083 pll->active = 0;
13084 for_each_intel_crtc(dev, crtc) {
13085 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
13086 pll->active++;
13087 }
13088 pll->refcount = pll->active;
13089
13090 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
13091 pll->name, pll->refcount, pll->on);
13092
13093 if (pll->refcount)
13094 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13095 }
13096
13097 for_each_intel_encoder(dev, encoder) {
13098 pipe = 0;
13099
13100 if (encoder->get_hw_state(encoder, &pipe)) {
13101 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13102 encoder->base.crtc = &crtc->base;
13103 encoder->get_config(encoder, &crtc->config);
13104 } else {
13105 encoder->base.crtc = NULL;
13106 }
13107
13108 encoder->connectors_active = false;
13109 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13110 encoder->base.base.id,
13111 encoder->base.name,
13112 encoder->base.crtc ? "enabled" : "disabled",
13113 pipe_name(pipe));
13114 }
13115
13116 list_for_each_entry(connector, &dev->mode_config.connector_list,
13117 base.head) {
13118 if (connector->get_hw_state(connector)) {
13119 connector->base.dpms = DRM_MODE_DPMS_ON;
13120 connector->encoder->connectors_active = true;
13121 connector->base.encoder = &connector->encoder->base;
13122 } else {
13123 connector->base.dpms = DRM_MODE_DPMS_OFF;
13124 connector->base.encoder = NULL;
13125 }
13126 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13127 connector->base.base.id,
13128 connector->base.name,
13129 connector->base.encoder ? "enabled" : "disabled");
13130 }
13131 }
13132
13133 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13134 * and i915 state tracking structures. */
13135 void intel_modeset_setup_hw_state(struct drm_device *dev,
13136 bool force_restore)
13137 {
13138 struct drm_i915_private *dev_priv = dev->dev_private;
13139 enum pipe pipe;
13140 struct intel_crtc *crtc;
13141 struct intel_encoder *encoder;
13142 int i;
13143
13144 intel_modeset_readout_hw_state(dev);
13145
13146 /*
13147 * Now that we have the config, copy it to each CRTC struct
13148 * Note that this could go away if we move to using crtc_config
13149 * checking everywhere.
13150 */
13151 for_each_intel_crtc(dev, crtc) {
13152 if (crtc->active && i915.fastboot) {
13153 intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
13154 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13155 crtc->base.base.id);
13156 drm_mode_debug_printmodeline(&crtc->base.mode);
13157 }
13158 }
13159
13160 /* HW state is read out, now we need to sanitize this mess. */
13161 for_each_intel_encoder(dev, encoder) {
13162 intel_sanitize_encoder(encoder);
13163 }
13164
13165 for_each_pipe(dev_priv, pipe) {
13166 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13167 intel_sanitize_crtc(crtc);
13168 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
13169 }
13170
13171 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13172 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13173
13174 if (!pll->on || pll->active)
13175 continue;
13176
13177 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13178
13179 pll->disable(dev_priv, pll);
13180 pll->on = false;
13181 }
13182
13183 if (HAS_PCH_SPLIT(dev))
13184 ilk_wm_get_hw_state(dev);
13185
13186 if (force_restore) {
13187 i915_redisable_vga(dev);
13188
13189 /*
13190 * We need to use raw interfaces for restoring state to avoid
13191 * checking (bogus) intermediate states.
13192 */
13193 for_each_pipe(dev_priv, pipe) {
13194 struct drm_crtc *crtc =
13195 dev_priv->pipe_to_crtc_mapping[pipe];
13196
13197 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13198 crtc->primary->fb);
13199 }
13200 } else {
13201 intel_modeset_update_staged_output_state(dev);
13202 }
13203
13204 intel_modeset_check_state(dev);
13205 }
13206
13207 void intel_modeset_gem_init(struct drm_device *dev)
13208 {
13209 struct drm_crtc *c;
13210 struct drm_i915_gem_object *obj;
13211
13212 mutex_lock(&dev->struct_mutex);
13213 intel_init_gt_powersave(dev);
13214 mutex_unlock(&dev->struct_mutex);
13215
13216 intel_modeset_init_hw(dev);
13217
13218 intel_setup_overlay(dev);
13219
13220 /*
13221 * Make sure any fbs we allocated at startup are properly
13222 * pinned & fenced. When we do the allocation it's too early
13223 * for this.
13224 */
13225 mutex_lock(&dev->struct_mutex);
13226 for_each_crtc(dev, c) {
13227 obj = intel_fb_obj(c->primary->fb);
13228 if (obj == NULL)
13229 continue;
13230
13231 if (intel_pin_and_fence_fb_obj(dev, obj, NULL)) {
13232 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13233 to_intel_crtc(c)->pipe);
13234 drm_framebuffer_unreference(c->primary->fb);
13235 c->primary->fb = NULL;
13236 }
13237 }
13238 mutex_unlock(&dev->struct_mutex);
13239 }
13240
13241 void intel_connector_unregister(struct intel_connector *intel_connector)
13242 {
13243 struct drm_connector *connector = &intel_connector->base;
13244
13245 intel_panel_destroy_backlight(connector);
13246 drm_connector_unregister(connector);
13247 }
13248
13249 void intel_modeset_cleanup(struct drm_device *dev)
13250 {
13251 struct drm_i915_private *dev_priv = dev->dev_private;
13252 struct drm_connector *connector;
13253
13254 /*
13255 * Interrupts and polling as the first thing to avoid creating havoc.
13256 * Too much stuff here (turning of rps, connectors, ...) would
13257 * experience fancy races otherwise.
13258 */
13259 drm_irq_uninstall(dev);
13260 intel_hpd_cancel_work(dev_priv);
13261 dev_priv->pm._irqs_disabled = true;
13262
13263 /*
13264 * Due to the hpd irq storm handling the hotplug work can re-arm the
13265 * poll handlers. Hence disable polling after hpd handling is shut down.
13266 */
13267 drm_kms_helper_poll_fini(dev);
13268
13269 mutex_lock(&dev->struct_mutex);
13270
13271 intel_unregister_dsm_handler();
13272
13273 intel_disable_fbc(dev);
13274
13275 intel_disable_gt_powersave(dev);
13276
13277 ironlake_teardown_rc6(dev);
13278
13279 mutex_unlock(&dev->struct_mutex);
13280
13281 /* flush any delayed tasks or pending work */
13282 flush_scheduled_work();
13283
13284 /* destroy the backlight and sysfs files before encoders/connectors */
13285 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13286 struct intel_connector *intel_connector;
13287
13288 intel_connector = to_intel_connector(connector);
13289 intel_connector->unregister(intel_connector);
13290 }
13291
13292 drm_mode_config_cleanup(dev);
13293
13294 intel_cleanup_overlay(dev);
13295
13296 mutex_lock(&dev->struct_mutex);
13297 intel_cleanup_gt_powersave(dev);
13298 mutex_unlock(&dev->struct_mutex);
13299 }
13300
13301 /*
13302 * Return which encoder is currently attached for connector.
13303 */
13304 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13305 {
13306 return &intel_attached_encoder(connector)->base;
13307 }
13308
13309 void intel_connector_attach_encoder(struct intel_connector *connector,
13310 struct intel_encoder *encoder)
13311 {
13312 connector->encoder = encoder;
13313 drm_mode_connector_attach_encoder(&connector->base,
13314 &encoder->base);
13315 }
13316
13317 /*
13318 * set vga decode state - true == enable VGA decode
13319 */
13320 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13321 {
13322 struct drm_i915_private *dev_priv = dev->dev_private;
13323 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13324 u16 gmch_ctrl;
13325
13326 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13327 DRM_ERROR("failed to read control word\n");
13328 return -EIO;
13329 }
13330
13331 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13332 return 0;
13333
13334 if (state)
13335 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13336 else
13337 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13338
13339 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13340 DRM_ERROR("failed to write control word\n");
13341 return -EIO;
13342 }
13343
13344 return 0;
13345 }
13346
13347 struct intel_display_error_state {
13348
13349 u32 power_well_driver;
13350
13351 int num_transcoders;
13352
13353 struct intel_cursor_error_state {
13354 u32 control;
13355 u32 position;
13356 u32 base;
13357 u32 size;
13358 } cursor[I915_MAX_PIPES];
13359
13360 struct intel_pipe_error_state {
13361 bool power_domain_on;
13362 u32 source;
13363 u32 stat;
13364 } pipe[I915_MAX_PIPES];
13365
13366 struct intel_plane_error_state {
13367 u32 control;
13368 u32 stride;
13369 u32 size;
13370 u32 pos;
13371 u32 addr;
13372 u32 surface;
13373 u32 tile_offset;
13374 } plane[I915_MAX_PIPES];
13375
13376 struct intel_transcoder_error_state {
13377 bool power_domain_on;
13378 enum transcoder cpu_transcoder;
13379
13380 u32 conf;
13381
13382 u32 htotal;
13383 u32 hblank;
13384 u32 hsync;
13385 u32 vtotal;
13386 u32 vblank;
13387 u32 vsync;
13388 } transcoder[4];
13389 };
13390
13391 struct intel_display_error_state *
13392 intel_display_capture_error_state(struct drm_device *dev)
13393 {
13394 struct drm_i915_private *dev_priv = dev->dev_private;
13395 struct intel_display_error_state *error;
13396 int transcoders[] = {
13397 TRANSCODER_A,
13398 TRANSCODER_B,
13399 TRANSCODER_C,
13400 TRANSCODER_EDP,
13401 };
13402 int i;
13403
13404 if (INTEL_INFO(dev)->num_pipes == 0)
13405 return NULL;
13406
13407 error = kzalloc(sizeof(*error), GFP_ATOMIC);
13408 if (error == NULL)
13409 return NULL;
13410
13411 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13412 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13413
13414 for_each_pipe(dev_priv, i) {
13415 error->pipe[i].power_domain_on =
13416 intel_display_power_enabled_unlocked(dev_priv,
13417 POWER_DOMAIN_PIPE(i));
13418 if (!error->pipe[i].power_domain_on)
13419 continue;
13420
13421 error->cursor[i].control = I915_READ(CURCNTR(i));
13422 error->cursor[i].position = I915_READ(CURPOS(i));
13423 error->cursor[i].base = I915_READ(CURBASE(i));
13424
13425 error->plane[i].control = I915_READ(DSPCNTR(i));
13426 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13427 if (INTEL_INFO(dev)->gen <= 3) {
13428 error->plane[i].size = I915_READ(DSPSIZE(i));
13429 error->plane[i].pos = I915_READ(DSPPOS(i));
13430 }
13431 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13432 error->plane[i].addr = I915_READ(DSPADDR(i));
13433 if (INTEL_INFO(dev)->gen >= 4) {
13434 error->plane[i].surface = I915_READ(DSPSURF(i));
13435 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13436 }
13437
13438 error->pipe[i].source = I915_READ(PIPESRC(i));
13439
13440 if (HAS_GMCH_DISPLAY(dev))
13441 error->pipe[i].stat = I915_READ(PIPESTAT(i));
13442 }
13443
13444 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13445 if (HAS_DDI(dev_priv->dev))
13446 error->num_transcoders++; /* Account for eDP. */
13447
13448 for (i = 0; i < error->num_transcoders; i++) {
13449 enum transcoder cpu_transcoder = transcoders[i];
13450
13451 error->transcoder[i].power_domain_on =
13452 intel_display_power_enabled_unlocked(dev_priv,
13453 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13454 if (!error->transcoder[i].power_domain_on)
13455 continue;
13456
13457 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13458
13459 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13460 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13461 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13462 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13463 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13464 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13465 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13466 }
13467
13468 return error;
13469 }
13470
13471 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13472
13473 void
13474 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13475 struct drm_device *dev,
13476 struct intel_display_error_state *error)
13477 {
13478 struct drm_i915_private *dev_priv = dev->dev_private;
13479 int i;
13480
13481 if (!error)
13482 return;
13483
13484 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13485 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13486 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13487 error->power_well_driver);
13488 for_each_pipe(dev_priv, i) {
13489 err_printf(m, "Pipe [%d]:\n", i);
13490 err_printf(m, " Power: %s\n",
13491 error->pipe[i].power_domain_on ? "on" : "off");
13492 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
13493 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
13494
13495 err_printf(m, "Plane [%d]:\n", i);
13496 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
13497 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
13498 if (INTEL_INFO(dev)->gen <= 3) {
13499 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
13500 err_printf(m, " POS: %08x\n", error->plane[i].pos);
13501 }
13502 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13503 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
13504 if (INTEL_INFO(dev)->gen >= 4) {
13505 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
13506 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
13507 }
13508
13509 err_printf(m, "Cursor [%d]:\n", i);
13510 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
13511 err_printf(m, " POS: %08x\n", error->cursor[i].position);
13512 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
13513 }
13514
13515 for (i = 0; i < error->num_transcoders; i++) {
13516 err_printf(m, "CPU transcoder: %c\n",
13517 transcoder_name(error->transcoder[i].cpu_transcoder));
13518 err_printf(m, " Power: %s\n",
13519 error->transcoder[i].power_domain_on ? "on" : "off");
13520 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
13521 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
13522 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
13523 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
13524 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
13525 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
13526 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
13527 }
13528 }
13529
13530 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
13531 {
13532 struct intel_crtc *crtc;
13533
13534 for_each_intel_crtc(dev, crtc) {
13535 struct intel_unpin_work *work;
13536 unsigned long irqflags;
13537
13538 spin_lock_irqsave(&dev->event_lock, irqflags);
13539
13540 work = crtc->unpin_work;
13541
13542 if (work && work->event &&
13543 work->event->base.file_priv == file) {
13544 kfree(work->event);
13545 work->event = NULL;
13546 }
13547
13548 spin_unlock_irqrestore(&dev->event_lock, irqflags);
13549 }
13550 }
Linux kernel - Deliverables
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