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drm/i915: Sanitize shared dpll state
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
43
44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
45 static void intel_increase_pllclock(struct drm_crtc *crtc);
46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
47
48 typedef struct {
49 int min, max;
50 } intel_range_t;
51
52 typedef struct {
53 int dot_limit;
54 int p2_slow, p2_fast;
55 } intel_p2_t;
56
57 #define INTEL_P2_NUM 2
58 typedef struct intel_limit intel_limit_t;
59 struct intel_limit {
60 intel_range_t dot, vco, n, m, m1, m2, p, p1;
61 intel_p2_t p2;
62 };
63
64 /* FDI */
65 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
66
67 int
68 intel_pch_rawclk(struct drm_device *dev)
69 {
70 struct drm_i915_private *dev_priv = dev->dev_private;
71
72 WARN_ON(!HAS_PCH_SPLIT(dev));
73
74 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
75 }
76
77 static inline u32 /* units of 100MHz */
78 intel_fdi_link_freq(struct drm_device *dev)
79 {
80 if (IS_GEN5(dev)) {
81 struct drm_i915_private *dev_priv = dev->dev_private;
82 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
83 } else
84 return 27;
85 }
86
87 static const intel_limit_t intel_limits_i8xx_dvo = {
88 .dot = { .min = 25000, .max = 350000 },
89 .vco = { .min = 930000, .max = 1400000 },
90 .n = { .min = 3, .max = 16 },
91 .m = { .min = 96, .max = 140 },
92 .m1 = { .min = 18, .max = 26 },
93 .m2 = { .min = 6, .max = 16 },
94 .p = { .min = 4, .max = 128 },
95 .p1 = { .min = 2, .max = 33 },
96 .p2 = { .dot_limit = 165000,
97 .p2_slow = 4, .p2_fast = 2 },
98 };
99
100 static const intel_limit_t intel_limits_i8xx_lvds = {
101 .dot = { .min = 25000, .max = 350000 },
102 .vco = { .min = 930000, .max = 1400000 },
103 .n = { .min = 3, .max = 16 },
104 .m = { .min = 96, .max = 140 },
105 .m1 = { .min = 18, .max = 26 },
106 .m2 = { .min = 6, .max = 16 },
107 .p = { .min = 4, .max = 128 },
108 .p1 = { .min = 1, .max = 6 },
109 .p2 = { .dot_limit = 165000,
110 .p2_slow = 14, .p2_fast = 7 },
111 };
112
113 static const intel_limit_t intel_limits_i9xx_sdvo = {
114 .dot = { .min = 20000, .max = 400000 },
115 .vco = { .min = 1400000, .max = 2800000 },
116 .n = { .min = 1, .max = 6 },
117 .m = { .min = 70, .max = 120 },
118 .m1 = { .min = 8, .max = 18 },
119 .m2 = { .min = 3, .max = 7 },
120 .p = { .min = 5, .max = 80 },
121 .p1 = { .min = 1, .max = 8 },
122 .p2 = { .dot_limit = 200000,
123 .p2_slow = 10, .p2_fast = 5 },
124 };
125
126 static const intel_limit_t intel_limits_i9xx_lvds = {
127 .dot = { .min = 20000, .max = 400000 },
128 .vco = { .min = 1400000, .max = 2800000 },
129 .n = { .min = 1, .max = 6 },
130 .m = { .min = 70, .max = 120 },
131 .m1 = { .min = 8, .max = 18 },
132 .m2 = { .min = 3, .max = 7 },
133 .p = { .min = 7, .max = 98 },
134 .p1 = { .min = 1, .max = 8 },
135 .p2 = { .dot_limit = 112000,
136 .p2_slow = 14, .p2_fast = 7 },
137 };
138
139
140 static const intel_limit_t intel_limits_g4x_sdvo = {
141 .dot = { .min = 25000, .max = 270000 },
142 .vco = { .min = 1750000, .max = 3500000},
143 .n = { .min = 1, .max = 4 },
144 .m = { .min = 104, .max = 138 },
145 .m1 = { .min = 17, .max = 23 },
146 .m2 = { .min = 5, .max = 11 },
147 .p = { .min = 10, .max = 30 },
148 .p1 = { .min = 1, .max = 3},
149 .p2 = { .dot_limit = 270000,
150 .p2_slow = 10,
151 .p2_fast = 10
152 },
153 };
154
155 static const intel_limit_t intel_limits_g4x_hdmi = {
156 .dot = { .min = 22000, .max = 400000 },
157 .vco = { .min = 1750000, .max = 3500000},
158 .n = { .min = 1, .max = 4 },
159 .m = { .min = 104, .max = 138 },
160 .m1 = { .min = 16, .max = 23 },
161 .m2 = { .min = 5, .max = 11 },
162 .p = { .min = 5, .max = 80 },
163 .p1 = { .min = 1, .max = 8},
164 .p2 = { .dot_limit = 165000,
165 .p2_slow = 10, .p2_fast = 5 },
166 };
167
168 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
169 .dot = { .min = 20000, .max = 115000 },
170 .vco = { .min = 1750000, .max = 3500000 },
171 .n = { .min = 1, .max = 3 },
172 .m = { .min = 104, .max = 138 },
173 .m1 = { .min = 17, .max = 23 },
174 .m2 = { .min = 5, .max = 11 },
175 .p = { .min = 28, .max = 112 },
176 .p1 = { .min = 2, .max = 8 },
177 .p2 = { .dot_limit = 0,
178 .p2_slow = 14, .p2_fast = 14
179 },
180 };
181
182 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
183 .dot = { .min = 80000, .max = 224000 },
184 .vco = { .min = 1750000, .max = 3500000 },
185 .n = { .min = 1, .max = 3 },
186 .m = { .min = 104, .max = 138 },
187 .m1 = { .min = 17, .max = 23 },
188 .m2 = { .min = 5, .max = 11 },
189 .p = { .min = 14, .max = 42 },
190 .p1 = { .min = 2, .max = 6 },
191 .p2 = { .dot_limit = 0,
192 .p2_slow = 7, .p2_fast = 7
193 },
194 };
195
196 static const intel_limit_t intel_limits_pineview_sdvo = {
197 .dot = { .min = 20000, .max = 400000},
198 .vco = { .min = 1700000, .max = 3500000 },
199 /* Pineview's Ncounter is a ring counter */
200 .n = { .min = 3, .max = 6 },
201 .m = { .min = 2, .max = 256 },
202 /* Pineview only has one combined m divider, which we treat as m2. */
203 .m1 = { .min = 0, .max = 0 },
204 .m2 = { .min = 0, .max = 254 },
205 .p = { .min = 5, .max = 80 },
206 .p1 = { .min = 1, .max = 8 },
207 .p2 = { .dot_limit = 200000,
208 .p2_slow = 10, .p2_fast = 5 },
209 };
210
211 static const intel_limit_t intel_limits_pineview_lvds = {
212 .dot = { .min = 20000, .max = 400000 },
213 .vco = { .min = 1700000, .max = 3500000 },
214 .n = { .min = 3, .max = 6 },
215 .m = { .min = 2, .max = 256 },
216 .m1 = { .min = 0, .max = 0 },
217 .m2 = { .min = 0, .max = 254 },
218 .p = { .min = 7, .max = 112 },
219 .p1 = { .min = 1, .max = 8 },
220 .p2 = { .dot_limit = 112000,
221 .p2_slow = 14, .p2_fast = 14 },
222 };
223
224 /* Ironlake / Sandybridge
225 *
226 * We calculate clock using (register_value + 2) for N/M1/M2, so here
227 * the range value for them is (actual_value - 2).
228 */
229 static const intel_limit_t intel_limits_ironlake_dac = {
230 .dot = { .min = 25000, .max = 350000 },
231 .vco = { .min = 1760000, .max = 3510000 },
232 .n = { .min = 1, .max = 5 },
233 .m = { .min = 79, .max = 127 },
234 .m1 = { .min = 12, .max = 22 },
235 .m2 = { .min = 5, .max = 9 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8 },
238 .p2 = { .dot_limit = 225000,
239 .p2_slow = 10, .p2_fast = 5 },
240 };
241
242 static const intel_limit_t intel_limits_ironlake_single_lvds = {
243 .dot = { .min = 25000, .max = 350000 },
244 .vco = { .min = 1760000, .max = 3510000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 79, .max = 118 },
247 .m1 = { .min = 12, .max = 22 },
248 .m2 = { .min = 5, .max = 9 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 225000,
252 .p2_slow = 14, .p2_fast = 14 },
253 };
254
255 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
256 .dot = { .min = 25000, .max = 350000 },
257 .vco = { .min = 1760000, .max = 3510000 },
258 .n = { .min = 1, .max = 3 },
259 .m = { .min = 79, .max = 127 },
260 .m1 = { .min = 12, .max = 22 },
261 .m2 = { .min = 5, .max = 9 },
262 .p = { .min = 14, .max = 56 },
263 .p1 = { .min = 2, .max = 8 },
264 .p2 = { .dot_limit = 225000,
265 .p2_slow = 7, .p2_fast = 7 },
266 };
267
268 /* LVDS 100mhz refclk limits. */
269 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
270 .dot = { .min = 25000, .max = 350000 },
271 .vco = { .min = 1760000, .max = 3510000 },
272 .n = { .min = 1, .max = 2 },
273 .m = { .min = 79, .max = 126 },
274 .m1 = { .min = 12, .max = 22 },
275 .m2 = { .min = 5, .max = 9 },
276 .p = { .min = 28, .max = 112 },
277 .p1 = { .min = 2, .max = 8 },
278 .p2 = { .dot_limit = 225000,
279 .p2_slow = 14, .p2_fast = 14 },
280 };
281
282 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
283 .dot = { .min = 25000, .max = 350000 },
284 .vco = { .min = 1760000, .max = 3510000 },
285 .n = { .min = 1, .max = 3 },
286 .m = { .min = 79, .max = 126 },
287 .m1 = { .min = 12, .max = 22 },
288 .m2 = { .min = 5, .max = 9 },
289 .p = { .min = 14, .max = 42 },
290 .p1 = { .min = 2, .max = 6 },
291 .p2 = { .dot_limit = 225000,
292 .p2_slow = 7, .p2_fast = 7 },
293 };
294
295 static const intel_limit_t intel_limits_vlv_dac = {
296 .dot = { .min = 25000, .max = 270000 },
297 .vco = { .min = 4000000, .max = 6000000 },
298 .n = { .min = 1, .max = 7 },
299 .m = { .min = 22, .max = 450 }, /* guess */
300 .m1 = { .min = 2, .max = 3 },
301 .m2 = { .min = 11, .max = 156 },
302 .p = { .min = 10, .max = 30 },
303 .p1 = { .min = 1, .max = 3 },
304 .p2 = { .dot_limit = 270000,
305 .p2_slow = 2, .p2_fast = 20 },
306 };
307
308 static const intel_limit_t intel_limits_vlv_hdmi = {
309 .dot = { .min = 25000, .max = 270000 },
310 .vco = { .min = 4000000, .max = 6000000 },
311 .n = { .min = 1, .max = 7 },
312 .m = { .min = 60, .max = 300 }, /* guess */
313 .m1 = { .min = 2, .max = 3 },
314 .m2 = { .min = 11, .max = 156 },
315 .p = { .min = 10, .max = 30 },
316 .p1 = { .min = 2, .max = 3 },
317 .p2 = { .dot_limit = 270000,
318 .p2_slow = 2, .p2_fast = 20 },
319 };
320
321 static const intel_limit_t intel_limits_vlv_dp = {
322 .dot = { .min = 25000, .max = 270000 },
323 .vco = { .min = 4000000, .max = 6000000 },
324 .n = { .min = 1, .max = 7 },
325 .m = { .min = 22, .max = 450 },
326 .m1 = { .min = 2, .max = 3 },
327 .m2 = { .min = 11, .max = 156 },
328 .p = { .min = 10, .max = 30 },
329 .p1 = { .min = 1, .max = 3 },
330 .p2 = { .dot_limit = 270000,
331 .p2_slow = 2, .p2_fast = 20 },
332 };
333
334 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
335 int refclk)
336 {
337 struct drm_device *dev = crtc->dev;
338 const intel_limit_t *limit;
339
340 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
341 if (intel_is_dual_link_lvds(dev)) {
342 if (refclk == 100000)
343 limit = &intel_limits_ironlake_dual_lvds_100m;
344 else
345 limit = &intel_limits_ironlake_dual_lvds;
346 } else {
347 if (refclk == 100000)
348 limit = &intel_limits_ironlake_single_lvds_100m;
349 else
350 limit = &intel_limits_ironlake_single_lvds;
351 }
352 } else
353 limit = &intel_limits_ironlake_dac;
354
355 return limit;
356 }
357
358 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
359 {
360 struct drm_device *dev = crtc->dev;
361 const intel_limit_t *limit;
362
363 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
364 if (intel_is_dual_link_lvds(dev))
365 limit = &intel_limits_g4x_dual_channel_lvds;
366 else
367 limit = &intel_limits_g4x_single_channel_lvds;
368 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
369 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
370 limit = &intel_limits_g4x_hdmi;
371 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
372 limit = &intel_limits_g4x_sdvo;
373 } else /* The option is for other outputs */
374 limit = &intel_limits_i9xx_sdvo;
375
376 return limit;
377 }
378
379 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
380 {
381 struct drm_device *dev = crtc->dev;
382 const intel_limit_t *limit;
383
384 if (HAS_PCH_SPLIT(dev))
385 limit = intel_ironlake_limit(crtc, refclk);
386 else if (IS_G4X(dev)) {
387 limit = intel_g4x_limit(crtc);
388 } else if (IS_PINEVIEW(dev)) {
389 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
390 limit = &intel_limits_pineview_lvds;
391 else
392 limit = &intel_limits_pineview_sdvo;
393 } else if (IS_VALLEYVIEW(dev)) {
394 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
395 limit = &intel_limits_vlv_dac;
396 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
397 limit = &intel_limits_vlv_hdmi;
398 else
399 limit = &intel_limits_vlv_dp;
400 } else if (!IS_GEN2(dev)) {
401 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
402 limit = &intel_limits_i9xx_lvds;
403 else
404 limit = &intel_limits_i9xx_sdvo;
405 } else {
406 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
407 limit = &intel_limits_i8xx_lvds;
408 else
409 limit = &intel_limits_i8xx_dvo;
410 }
411 return limit;
412 }
413
414 /* m1 is reserved as 0 in Pineview, n is a ring counter */
415 static void pineview_clock(int refclk, intel_clock_t *clock)
416 {
417 clock->m = clock->m2 + 2;
418 clock->p = clock->p1 * clock->p2;
419 clock->vco = refclk * clock->m / clock->n;
420 clock->dot = clock->vco / clock->p;
421 }
422
423 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
424 {
425 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
426 }
427
428 static void i9xx_clock(int refclk, intel_clock_t *clock)
429 {
430 clock->m = i9xx_dpll_compute_m(clock);
431 clock->p = clock->p1 * clock->p2;
432 clock->vco = refclk * clock->m / (clock->n + 2);
433 clock->dot = clock->vco / clock->p;
434 }
435
436 /**
437 * Returns whether any output on the specified pipe is of the specified type
438 */
439 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
440 {
441 struct drm_device *dev = crtc->dev;
442 struct intel_encoder *encoder;
443
444 for_each_encoder_on_crtc(dev, crtc, encoder)
445 if (encoder->type == type)
446 return true;
447
448 return false;
449 }
450
451 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
452 /**
453 * Returns whether the given set of divisors are valid for a given refclk with
454 * the given connectors.
455 */
456
457 static bool intel_PLL_is_valid(struct drm_device *dev,
458 const intel_limit_t *limit,
459 const intel_clock_t *clock)
460 {
461 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
462 INTELPllInvalid("p1 out of range\n");
463 if (clock->p < limit->p.min || limit->p.max < clock->p)
464 INTELPllInvalid("p out of range\n");
465 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
466 INTELPllInvalid("m2 out of range\n");
467 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
468 INTELPllInvalid("m1 out of range\n");
469 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
470 INTELPllInvalid("m1 <= m2\n");
471 if (clock->m < limit->m.min || limit->m.max < clock->m)
472 INTELPllInvalid("m out of range\n");
473 if (clock->n < limit->n.min || limit->n.max < clock->n)
474 INTELPllInvalid("n out of range\n");
475 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
476 INTELPllInvalid("vco out of range\n");
477 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
478 * connector, etc., rather than just a single range.
479 */
480 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
481 INTELPllInvalid("dot out of range\n");
482
483 return true;
484 }
485
486 static bool
487 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
488 int target, int refclk, intel_clock_t *match_clock,
489 intel_clock_t *best_clock)
490 {
491 struct drm_device *dev = crtc->dev;
492 intel_clock_t clock;
493 int err = target;
494
495 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
496 /*
497 * For LVDS just rely on its current settings for dual-channel.
498 * We haven't figured out how to reliably set up different
499 * single/dual channel state, if we even can.
500 */
501 if (intel_is_dual_link_lvds(dev))
502 clock.p2 = limit->p2.p2_fast;
503 else
504 clock.p2 = limit->p2.p2_slow;
505 } else {
506 if (target < limit->p2.dot_limit)
507 clock.p2 = limit->p2.p2_slow;
508 else
509 clock.p2 = limit->p2.p2_fast;
510 }
511
512 memset(best_clock, 0, sizeof(*best_clock));
513
514 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
515 clock.m1++) {
516 for (clock.m2 = limit->m2.min;
517 clock.m2 <= limit->m2.max; clock.m2++) {
518 if (clock.m2 >= clock.m1)
519 break;
520 for (clock.n = limit->n.min;
521 clock.n <= limit->n.max; clock.n++) {
522 for (clock.p1 = limit->p1.min;
523 clock.p1 <= limit->p1.max; clock.p1++) {
524 int this_err;
525
526 i9xx_clock(refclk, &clock);
527 if (!intel_PLL_is_valid(dev, limit,
528 &clock))
529 continue;
530 if (match_clock &&
531 clock.p != match_clock->p)
532 continue;
533
534 this_err = abs(clock.dot - target);
535 if (this_err < err) {
536 *best_clock = clock;
537 err = this_err;
538 }
539 }
540 }
541 }
542 }
543
544 return (err != target);
545 }
546
547 static bool
548 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
549 int target, int refclk, intel_clock_t *match_clock,
550 intel_clock_t *best_clock)
551 {
552 struct drm_device *dev = crtc->dev;
553 intel_clock_t clock;
554 int err = target;
555
556 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
557 /*
558 * For LVDS just rely on its current settings for dual-channel.
559 * We haven't figured out how to reliably set up different
560 * single/dual channel state, if we even can.
561 */
562 if (intel_is_dual_link_lvds(dev))
563 clock.p2 = limit->p2.p2_fast;
564 else
565 clock.p2 = limit->p2.p2_slow;
566 } else {
567 if (target < limit->p2.dot_limit)
568 clock.p2 = limit->p2.p2_slow;
569 else
570 clock.p2 = limit->p2.p2_fast;
571 }
572
573 memset(best_clock, 0, sizeof(*best_clock));
574
575 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
576 clock.m1++) {
577 for (clock.m2 = limit->m2.min;
578 clock.m2 <= limit->m2.max; clock.m2++) {
579 for (clock.n = limit->n.min;
580 clock.n <= limit->n.max; clock.n++) {
581 for (clock.p1 = limit->p1.min;
582 clock.p1 <= limit->p1.max; clock.p1++) {
583 int this_err;
584
585 pineview_clock(refclk, &clock);
586 if (!intel_PLL_is_valid(dev, limit,
587 &clock))
588 continue;
589 if (match_clock &&
590 clock.p != match_clock->p)
591 continue;
592
593 this_err = abs(clock.dot - target);
594 if (this_err < err) {
595 *best_clock = clock;
596 err = this_err;
597 }
598 }
599 }
600 }
601 }
602
603 return (err != target);
604 }
605
606 static bool
607 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
608 int target, int refclk, intel_clock_t *match_clock,
609 intel_clock_t *best_clock)
610 {
611 struct drm_device *dev = crtc->dev;
612 intel_clock_t clock;
613 int max_n;
614 bool found;
615 /* approximately equals target * 0.00585 */
616 int err_most = (target >> 8) + (target >> 9);
617 found = false;
618
619 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
620 if (intel_is_dual_link_lvds(dev))
621 clock.p2 = limit->p2.p2_fast;
622 else
623 clock.p2 = limit->p2.p2_slow;
624 } else {
625 if (target < limit->p2.dot_limit)
626 clock.p2 = limit->p2.p2_slow;
627 else
628 clock.p2 = limit->p2.p2_fast;
629 }
630
631 memset(best_clock, 0, sizeof(*best_clock));
632 max_n = limit->n.max;
633 /* based on hardware requirement, prefer smaller n to precision */
634 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
635 /* based on hardware requirement, prefere larger m1,m2 */
636 for (clock.m1 = limit->m1.max;
637 clock.m1 >= limit->m1.min; clock.m1--) {
638 for (clock.m2 = limit->m2.max;
639 clock.m2 >= limit->m2.min; clock.m2--) {
640 for (clock.p1 = limit->p1.max;
641 clock.p1 >= limit->p1.min; clock.p1--) {
642 int this_err;
643
644 i9xx_clock(refclk, &clock);
645 if (!intel_PLL_is_valid(dev, limit,
646 &clock))
647 continue;
648
649 this_err = abs(clock.dot - target);
650 if (this_err < err_most) {
651 *best_clock = clock;
652 err_most = this_err;
653 max_n = clock.n;
654 found = true;
655 }
656 }
657 }
658 }
659 }
660 return found;
661 }
662
663 static bool
664 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
665 int target, int refclk, intel_clock_t *match_clock,
666 intel_clock_t *best_clock)
667 {
668 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
669 u32 m, n, fastclk;
670 u32 updrate, minupdate, fracbits, p;
671 unsigned long bestppm, ppm, absppm;
672 int dotclk, flag;
673
674 flag = 0;
675 dotclk = target * 1000;
676 bestppm = 1000000;
677 ppm = absppm = 0;
678 fastclk = dotclk / (2*100);
679 updrate = 0;
680 minupdate = 19200;
681 fracbits = 1;
682 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
683 bestm1 = bestm2 = bestp1 = bestp2 = 0;
684
685 /* based on hardware requirement, prefer smaller n to precision */
686 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
687 updrate = refclk / n;
688 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
689 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
690 if (p2 > 10)
691 p2 = p2 - 1;
692 p = p1 * p2;
693 /* based on hardware requirement, prefer bigger m1,m2 values */
694 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
695 m2 = (((2*(fastclk * p * n / m1 )) +
696 refclk) / (2*refclk));
697 m = m1 * m2;
698 vco = updrate * m;
699 if (vco >= limit->vco.min && vco < limit->vco.max) {
700 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
701 absppm = (ppm > 0) ? ppm : (-ppm);
702 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
703 bestppm = 0;
704 flag = 1;
705 }
706 if (absppm < bestppm - 10) {
707 bestppm = absppm;
708 flag = 1;
709 }
710 if (flag) {
711 bestn = n;
712 bestm1 = m1;
713 bestm2 = m2;
714 bestp1 = p1;
715 bestp2 = p2;
716 flag = 0;
717 }
718 }
719 }
720 }
721 }
722 }
723 best_clock->n = bestn;
724 best_clock->m1 = bestm1;
725 best_clock->m2 = bestm2;
726 best_clock->p1 = bestp1;
727 best_clock->p2 = bestp2;
728
729 return true;
730 }
731
732 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
733 enum pipe pipe)
734 {
735 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
737
738 return intel_crtc->config.cpu_transcoder;
739 }
740
741 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
742 {
743 struct drm_i915_private *dev_priv = dev->dev_private;
744 u32 frame, frame_reg = PIPEFRAME(pipe);
745
746 frame = I915_READ(frame_reg);
747
748 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
749 DRM_DEBUG_KMS("vblank wait timed out\n");
750 }
751
752 /**
753 * intel_wait_for_vblank - wait for vblank on a given pipe
754 * @dev: drm device
755 * @pipe: pipe to wait for
756 *
757 * Wait for vblank to occur on a given pipe. Needed for various bits of
758 * mode setting code.
759 */
760 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
761 {
762 struct drm_i915_private *dev_priv = dev->dev_private;
763 int pipestat_reg = PIPESTAT(pipe);
764
765 if (INTEL_INFO(dev)->gen >= 5) {
766 ironlake_wait_for_vblank(dev, pipe);
767 return;
768 }
769
770 /* Clear existing vblank status. Note this will clear any other
771 * sticky status fields as well.
772 *
773 * This races with i915_driver_irq_handler() with the result
774 * that either function could miss a vblank event. Here it is not
775 * fatal, as we will either wait upon the next vblank interrupt or
776 * timeout. Generally speaking intel_wait_for_vblank() is only
777 * called during modeset at which time the GPU should be idle and
778 * should *not* be performing page flips and thus not waiting on
779 * vblanks...
780 * Currently, the result of us stealing a vblank from the irq
781 * handler is that a single frame will be skipped during swapbuffers.
782 */
783 I915_WRITE(pipestat_reg,
784 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
785
786 /* Wait for vblank interrupt bit to set */
787 if (wait_for(I915_READ(pipestat_reg) &
788 PIPE_VBLANK_INTERRUPT_STATUS,
789 50))
790 DRM_DEBUG_KMS("vblank wait timed out\n");
791 }
792
793 /*
794 * intel_wait_for_pipe_off - wait for pipe to turn off
795 * @dev: drm device
796 * @pipe: pipe to wait for
797 *
798 * After disabling a pipe, we can't wait for vblank in the usual way,
799 * spinning on the vblank interrupt status bit, since we won't actually
800 * see an interrupt when the pipe is disabled.
801 *
802 * On Gen4 and above:
803 * wait for the pipe register state bit to turn off
804 *
805 * Otherwise:
806 * wait for the display line value to settle (it usually
807 * ends up stopping at the start of the next frame).
808 *
809 */
810 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
811 {
812 struct drm_i915_private *dev_priv = dev->dev_private;
813 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
814 pipe);
815
816 if (INTEL_INFO(dev)->gen >= 4) {
817 int reg = PIPECONF(cpu_transcoder);
818
819 /* Wait for the Pipe State to go off */
820 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
821 100))
822 WARN(1, "pipe_off wait timed out\n");
823 } else {
824 u32 last_line, line_mask;
825 int reg = PIPEDSL(pipe);
826 unsigned long timeout = jiffies + msecs_to_jiffies(100);
827
828 if (IS_GEN2(dev))
829 line_mask = DSL_LINEMASK_GEN2;
830 else
831 line_mask = DSL_LINEMASK_GEN3;
832
833 /* Wait for the display line to settle */
834 do {
835 last_line = I915_READ(reg) & line_mask;
836 mdelay(5);
837 } while (((I915_READ(reg) & line_mask) != last_line) &&
838 time_after(timeout, jiffies));
839 if (time_after(jiffies, timeout))
840 WARN(1, "pipe_off wait timed out\n");
841 }
842 }
843
844 /*
845 * ibx_digital_port_connected - is the specified port connected?
846 * @dev_priv: i915 private structure
847 * @port: the port to test
848 *
849 * Returns true if @port is connected, false otherwise.
850 */
851 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
852 struct intel_digital_port *port)
853 {
854 u32 bit;
855
856 if (HAS_PCH_IBX(dev_priv->dev)) {
857 switch(port->port) {
858 case PORT_B:
859 bit = SDE_PORTB_HOTPLUG;
860 break;
861 case PORT_C:
862 bit = SDE_PORTC_HOTPLUG;
863 break;
864 case PORT_D:
865 bit = SDE_PORTD_HOTPLUG;
866 break;
867 default:
868 return true;
869 }
870 } else {
871 switch(port->port) {
872 case PORT_B:
873 bit = SDE_PORTB_HOTPLUG_CPT;
874 break;
875 case PORT_C:
876 bit = SDE_PORTC_HOTPLUG_CPT;
877 break;
878 case PORT_D:
879 bit = SDE_PORTD_HOTPLUG_CPT;
880 break;
881 default:
882 return true;
883 }
884 }
885
886 return I915_READ(SDEISR) & bit;
887 }
888
889 static const char *state_string(bool enabled)
890 {
891 return enabled ? "on" : "off";
892 }
893
894 /* Only for pre-ILK configs */
895 static void assert_pll(struct drm_i915_private *dev_priv,
896 enum pipe pipe, bool state)
897 {
898 int reg;
899 u32 val;
900 bool cur_state;
901
902 reg = DPLL(pipe);
903 val = I915_READ(reg);
904 cur_state = !!(val & DPLL_VCO_ENABLE);
905 WARN(cur_state != state,
906 "PLL state assertion failure (expected %s, current %s)\n",
907 state_string(state), state_string(cur_state));
908 }
909 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
910 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
911
912 static struct intel_shared_dpll *
913 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
914 {
915 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
916
917 if (crtc->config.shared_dpll < 0)
918 return NULL;
919
920 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
921 }
922
923 /* For ILK+ */
924 static void assert_shared_dpll(struct drm_i915_private *dev_priv,
925 struct intel_shared_dpll *pll,
926 bool state)
927 {
928 bool cur_state;
929 struct intel_dpll_hw_state hw_state;
930
931 if (HAS_PCH_LPT(dev_priv->dev)) {
932 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
933 return;
934 }
935
936 if (WARN (!pll,
937 "asserting DPLL %s with no DPLL\n", state_string(state)))
938 return;
939
940 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
941 WARN(cur_state != state,
942 "%s assertion failure (expected %s, current %s)\n",
943 pll->name, state_string(state), state_string(cur_state));
944 }
945 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
946 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
947
948 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
949 enum pipe pipe, bool state)
950 {
951 int reg;
952 u32 val;
953 bool cur_state;
954 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
955 pipe);
956
957 if (HAS_DDI(dev_priv->dev)) {
958 /* DDI does not have a specific FDI_TX register */
959 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
960 val = I915_READ(reg);
961 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
962 } else {
963 reg = FDI_TX_CTL(pipe);
964 val = I915_READ(reg);
965 cur_state = !!(val & FDI_TX_ENABLE);
966 }
967 WARN(cur_state != state,
968 "FDI TX state assertion failure (expected %s, current %s)\n",
969 state_string(state), state_string(cur_state));
970 }
971 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
972 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
973
974 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
975 enum pipe pipe, bool state)
976 {
977 int reg;
978 u32 val;
979 bool cur_state;
980
981 reg = FDI_RX_CTL(pipe);
982 val = I915_READ(reg);
983 cur_state = !!(val & FDI_RX_ENABLE);
984 WARN(cur_state != state,
985 "FDI RX state assertion failure (expected %s, current %s)\n",
986 state_string(state), state_string(cur_state));
987 }
988 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
989 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
990
991 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
992 enum pipe pipe)
993 {
994 int reg;
995 u32 val;
996
997 /* ILK FDI PLL is always enabled */
998 if (dev_priv->info->gen == 5)
999 return;
1000
1001 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1002 if (HAS_DDI(dev_priv->dev))
1003 return;
1004
1005 reg = FDI_TX_CTL(pipe);
1006 val = I915_READ(reg);
1007 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1008 }
1009
1010 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1011 enum pipe pipe)
1012 {
1013 int reg;
1014 u32 val;
1015
1016 reg = FDI_RX_CTL(pipe);
1017 val = I915_READ(reg);
1018 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1019 }
1020
1021 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1022 enum pipe pipe)
1023 {
1024 int pp_reg, lvds_reg;
1025 u32 val;
1026 enum pipe panel_pipe = PIPE_A;
1027 bool locked = true;
1028
1029 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1030 pp_reg = PCH_PP_CONTROL;
1031 lvds_reg = PCH_LVDS;
1032 } else {
1033 pp_reg = PP_CONTROL;
1034 lvds_reg = LVDS;
1035 }
1036
1037 val = I915_READ(pp_reg);
1038 if (!(val & PANEL_POWER_ON) ||
1039 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1040 locked = false;
1041
1042 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1043 panel_pipe = PIPE_B;
1044
1045 WARN(panel_pipe == pipe && locked,
1046 "panel assertion failure, pipe %c regs locked\n",
1047 pipe_name(pipe));
1048 }
1049
1050 void assert_pipe(struct drm_i915_private *dev_priv,
1051 enum pipe pipe, bool state)
1052 {
1053 int reg;
1054 u32 val;
1055 bool cur_state;
1056 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1057 pipe);
1058
1059 /* if we need the pipe A quirk it must be always on */
1060 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1061 state = true;
1062
1063 if (!intel_display_power_enabled(dev_priv->dev,
1064 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1065 cur_state = false;
1066 } else {
1067 reg = PIPECONF(cpu_transcoder);
1068 val = I915_READ(reg);
1069 cur_state = !!(val & PIPECONF_ENABLE);
1070 }
1071
1072 WARN(cur_state != state,
1073 "pipe %c assertion failure (expected %s, current %s)\n",
1074 pipe_name(pipe), state_string(state), state_string(cur_state));
1075 }
1076
1077 static void assert_plane(struct drm_i915_private *dev_priv,
1078 enum plane plane, bool state)
1079 {
1080 int reg;
1081 u32 val;
1082 bool cur_state;
1083
1084 reg = DSPCNTR(plane);
1085 val = I915_READ(reg);
1086 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1087 WARN(cur_state != state,
1088 "plane %c assertion failure (expected %s, current %s)\n",
1089 plane_name(plane), state_string(state), state_string(cur_state));
1090 }
1091
1092 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1093 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1094
1095 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1096 enum pipe pipe)
1097 {
1098 struct drm_device *dev = dev_priv->dev;
1099 int reg, i;
1100 u32 val;
1101 int cur_pipe;
1102
1103 /* Primary planes are fixed to pipes on gen4+ */
1104 if (INTEL_INFO(dev)->gen >= 4) {
1105 reg = DSPCNTR(pipe);
1106 val = I915_READ(reg);
1107 WARN((val & DISPLAY_PLANE_ENABLE),
1108 "plane %c assertion failure, should be disabled but not\n",
1109 plane_name(pipe));
1110 return;
1111 }
1112
1113 /* Need to check both planes against the pipe */
1114 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
1115 reg = DSPCNTR(i);
1116 val = I915_READ(reg);
1117 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1118 DISPPLANE_SEL_PIPE_SHIFT;
1119 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1120 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1121 plane_name(i), pipe_name(pipe));
1122 }
1123 }
1124
1125 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1126 enum pipe pipe)
1127 {
1128 struct drm_device *dev = dev_priv->dev;
1129 int reg, i;
1130 u32 val;
1131
1132 if (IS_VALLEYVIEW(dev)) {
1133 for (i = 0; i < dev_priv->num_plane; i++) {
1134 reg = SPCNTR(pipe, i);
1135 val = I915_READ(reg);
1136 WARN((val & SP_ENABLE),
1137 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1138 sprite_name(pipe, i), pipe_name(pipe));
1139 }
1140 } else if (INTEL_INFO(dev)->gen >= 7) {
1141 reg = SPRCTL(pipe);
1142 val = I915_READ(reg);
1143 WARN((val & SPRITE_ENABLE),
1144 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1145 plane_name(pipe), pipe_name(pipe));
1146 } else if (INTEL_INFO(dev)->gen >= 5) {
1147 reg = DVSCNTR(pipe);
1148 val = I915_READ(reg);
1149 WARN((val & DVS_ENABLE),
1150 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1151 plane_name(pipe), pipe_name(pipe));
1152 }
1153 }
1154
1155 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1156 {
1157 u32 val;
1158 bool enabled;
1159
1160 if (HAS_PCH_LPT(dev_priv->dev)) {
1161 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1162 return;
1163 }
1164
1165 val = I915_READ(PCH_DREF_CONTROL);
1166 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1167 DREF_SUPERSPREAD_SOURCE_MASK));
1168 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1169 }
1170
1171 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1172 enum pipe pipe)
1173 {
1174 int reg;
1175 u32 val;
1176 bool enabled;
1177
1178 reg = PCH_TRANSCONF(pipe);
1179 val = I915_READ(reg);
1180 enabled = !!(val & TRANS_ENABLE);
1181 WARN(enabled,
1182 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1183 pipe_name(pipe));
1184 }
1185
1186 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1187 enum pipe pipe, u32 port_sel, u32 val)
1188 {
1189 if ((val & DP_PORT_EN) == 0)
1190 return false;
1191
1192 if (HAS_PCH_CPT(dev_priv->dev)) {
1193 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1194 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1195 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1196 return false;
1197 } else {
1198 if ((val & DP_PIPE_MASK) != (pipe << 30))
1199 return false;
1200 }
1201 return true;
1202 }
1203
1204 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1205 enum pipe pipe, u32 val)
1206 {
1207 if ((val & SDVO_ENABLE) == 0)
1208 return false;
1209
1210 if (HAS_PCH_CPT(dev_priv->dev)) {
1211 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1212 return false;
1213 } else {
1214 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1215 return false;
1216 }
1217 return true;
1218 }
1219
1220 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1221 enum pipe pipe, u32 val)
1222 {
1223 if ((val & LVDS_PORT_EN) == 0)
1224 return false;
1225
1226 if (HAS_PCH_CPT(dev_priv->dev)) {
1227 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1228 return false;
1229 } else {
1230 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1231 return false;
1232 }
1233 return true;
1234 }
1235
1236 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1237 enum pipe pipe, u32 val)
1238 {
1239 if ((val & ADPA_DAC_ENABLE) == 0)
1240 return false;
1241 if (HAS_PCH_CPT(dev_priv->dev)) {
1242 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1243 return false;
1244 } else {
1245 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1246 return false;
1247 }
1248 return true;
1249 }
1250
1251 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1252 enum pipe pipe, int reg, u32 port_sel)
1253 {
1254 u32 val = I915_READ(reg);
1255 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1256 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1257 reg, pipe_name(pipe));
1258
1259 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1260 && (val & DP_PIPEB_SELECT),
1261 "IBX PCH dp port still using transcoder B\n");
1262 }
1263
1264 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1265 enum pipe pipe, int reg)
1266 {
1267 u32 val = I915_READ(reg);
1268 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1269 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1270 reg, pipe_name(pipe));
1271
1272 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1273 && (val & SDVO_PIPE_B_SELECT),
1274 "IBX PCH hdmi port still using transcoder B\n");
1275 }
1276
1277 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1278 enum pipe pipe)
1279 {
1280 int reg;
1281 u32 val;
1282
1283 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1284 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1285 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1286
1287 reg = PCH_ADPA;
1288 val = I915_READ(reg);
1289 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1290 "PCH VGA enabled on transcoder %c, should be disabled\n",
1291 pipe_name(pipe));
1292
1293 reg = PCH_LVDS;
1294 val = I915_READ(reg);
1295 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1296 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1297 pipe_name(pipe));
1298
1299 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1300 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1301 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1302 }
1303
1304 /**
1305 * intel_enable_pll - enable a PLL
1306 * @dev_priv: i915 private structure
1307 * @pipe: pipe PLL to enable
1308 *
1309 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1310 * make sure the PLL reg is writable first though, since the panel write
1311 * protect mechanism may be enabled.
1312 *
1313 * Note! This is for pre-ILK only.
1314 *
1315 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1316 */
1317 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1318 {
1319 int reg;
1320 u32 val;
1321
1322 assert_pipe_disabled(dev_priv, pipe);
1323
1324 /* No really, not for ILK+ */
1325 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1326
1327 /* PLL is protected by panel, make sure we can write it */
1328 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1329 assert_panel_unlocked(dev_priv, pipe);
1330
1331 reg = DPLL(pipe);
1332 val = I915_READ(reg);
1333 val |= DPLL_VCO_ENABLE;
1334
1335 /* We do this three times for luck */
1336 I915_WRITE(reg, val);
1337 POSTING_READ(reg);
1338 udelay(150); /* wait for warmup */
1339 I915_WRITE(reg, val);
1340 POSTING_READ(reg);
1341 udelay(150); /* wait for warmup */
1342 I915_WRITE(reg, val);
1343 POSTING_READ(reg);
1344 udelay(150); /* wait for warmup */
1345 }
1346
1347 /**
1348 * intel_disable_pll - disable a PLL
1349 * @dev_priv: i915 private structure
1350 * @pipe: pipe PLL to disable
1351 *
1352 * Disable the PLL for @pipe, making sure the pipe is off first.
1353 *
1354 * Note! This is for pre-ILK only.
1355 */
1356 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1357 {
1358 int reg;
1359 u32 val;
1360
1361 /* Don't disable pipe A or pipe A PLLs if needed */
1362 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1363 return;
1364
1365 /* Make sure the pipe isn't still relying on us */
1366 assert_pipe_disabled(dev_priv, pipe);
1367
1368 reg = DPLL(pipe);
1369 val = I915_READ(reg);
1370 val &= ~DPLL_VCO_ENABLE;
1371 I915_WRITE(reg, val);
1372 POSTING_READ(reg);
1373 }
1374
1375 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1376 {
1377 u32 port_mask;
1378
1379 if (!port)
1380 port_mask = DPLL_PORTB_READY_MASK;
1381 else
1382 port_mask = DPLL_PORTC_READY_MASK;
1383
1384 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1385 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1386 'B' + port, I915_READ(DPLL(0)));
1387 }
1388
1389 /**
1390 * ironlake_enable_shared_dpll - enable PCH PLL
1391 * @dev_priv: i915 private structure
1392 * @pipe: pipe PLL to enable
1393 *
1394 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1395 * drives the transcoder clock.
1396 */
1397 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1398 {
1399 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1400 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1401
1402 /* PCH PLLs only available on ILK, SNB and IVB */
1403 BUG_ON(dev_priv->info->gen < 5);
1404 if (WARN_ON(pll == NULL))
1405 return;
1406
1407 if (WARN_ON(pll->refcount == 0))
1408 return;
1409
1410 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1411 pll->name, pll->active, pll->on,
1412 crtc->base.base.id);
1413
1414 if (pll->active++) {
1415 WARN_ON(!pll->on);
1416 assert_shared_dpll_enabled(dev_priv, pll);
1417 return;
1418 }
1419 WARN_ON(pll->on);
1420
1421 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1422 pll->enable(dev_priv, pll);
1423 pll->on = true;
1424 }
1425
1426 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1427 {
1428 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1429 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1430
1431 /* PCH only available on ILK+ */
1432 BUG_ON(dev_priv->info->gen < 5);
1433 if (WARN_ON(pll == NULL))
1434 return;
1435
1436 if (WARN_ON(pll->refcount == 0))
1437 return;
1438
1439 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1440 pll->name, pll->active, pll->on,
1441 crtc->base.base.id);
1442
1443 if (WARN_ON(pll->active == 0)) {
1444 assert_shared_dpll_disabled(dev_priv, pll);
1445 return;
1446 }
1447
1448 assert_shared_dpll_enabled(dev_priv, pll);
1449 WARN_ON(!pll->on);
1450 if (--pll->active)
1451 return;
1452
1453 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1454 pll->disable(dev_priv, pll);
1455 pll->on = false;
1456 }
1457
1458 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1459 enum pipe pipe)
1460 {
1461 struct drm_device *dev = dev_priv->dev;
1462 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1463 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1464 uint32_t reg, val, pipeconf_val;
1465
1466 /* PCH only available on ILK+ */
1467 BUG_ON(dev_priv->info->gen < 5);
1468
1469 /* Make sure PCH DPLL is enabled */
1470 assert_shared_dpll_enabled(dev_priv,
1471 intel_crtc_to_shared_dpll(intel_crtc));
1472
1473 /* FDI must be feeding us bits for PCH ports */
1474 assert_fdi_tx_enabled(dev_priv, pipe);
1475 assert_fdi_rx_enabled(dev_priv, pipe);
1476
1477 if (HAS_PCH_CPT(dev)) {
1478 /* Workaround: Set the timing override bit before enabling the
1479 * pch transcoder. */
1480 reg = TRANS_CHICKEN2(pipe);
1481 val = I915_READ(reg);
1482 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1483 I915_WRITE(reg, val);
1484 }
1485
1486 reg = PCH_TRANSCONF(pipe);
1487 val = I915_READ(reg);
1488 pipeconf_val = I915_READ(PIPECONF(pipe));
1489
1490 if (HAS_PCH_IBX(dev_priv->dev)) {
1491 /*
1492 * make the BPC in transcoder be consistent with
1493 * that in pipeconf reg.
1494 */
1495 val &= ~PIPECONF_BPC_MASK;
1496 val |= pipeconf_val & PIPECONF_BPC_MASK;
1497 }
1498
1499 val &= ~TRANS_INTERLACE_MASK;
1500 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1501 if (HAS_PCH_IBX(dev_priv->dev) &&
1502 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1503 val |= TRANS_LEGACY_INTERLACED_ILK;
1504 else
1505 val |= TRANS_INTERLACED;
1506 else
1507 val |= TRANS_PROGRESSIVE;
1508
1509 I915_WRITE(reg, val | TRANS_ENABLE);
1510 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1511 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1512 }
1513
1514 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1515 enum transcoder cpu_transcoder)
1516 {
1517 u32 val, pipeconf_val;
1518
1519 /* PCH only available on ILK+ */
1520 BUG_ON(dev_priv->info->gen < 5);
1521
1522 /* FDI must be feeding us bits for PCH ports */
1523 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1524 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1525
1526 /* Workaround: set timing override bit. */
1527 val = I915_READ(_TRANSA_CHICKEN2);
1528 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1529 I915_WRITE(_TRANSA_CHICKEN2, val);
1530
1531 val = TRANS_ENABLE;
1532 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1533
1534 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1535 PIPECONF_INTERLACED_ILK)
1536 val |= TRANS_INTERLACED;
1537 else
1538 val |= TRANS_PROGRESSIVE;
1539
1540 I915_WRITE(LPT_TRANSCONF, val);
1541 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1542 DRM_ERROR("Failed to enable PCH transcoder\n");
1543 }
1544
1545 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1546 enum pipe pipe)
1547 {
1548 struct drm_device *dev = dev_priv->dev;
1549 uint32_t reg, val;
1550
1551 /* FDI relies on the transcoder */
1552 assert_fdi_tx_disabled(dev_priv, pipe);
1553 assert_fdi_rx_disabled(dev_priv, pipe);
1554
1555 /* Ports must be off as well */
1556 assert_pch_ports_disabled(dev_priv, pipe);
1557
1558 reg = PCH_TRANSCONF(pipe);
1559 val = I915_READ(reg);
1560 val &= ~TRANS_ENABLE;
1561 I915_WRITE(reg, val);
1562 /* wait for PCH transcoder off, transcoder state */
1563 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1564 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1565
1566 if (!HAS_PCH_IBX(dev)) {
1567 /* Workaround: Clear the timing override chicken bit again. */
1568 reg = TRANS_CHICKEN2(pipe);
1569 val = I915_READ(reg);
1570 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1571 I915_WRITE(reg, val);
1572 }
1573 }
1574
1575 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1576 {
1577 u32 val;
1578
1579 val = I915_READ(LPT_TRANSCONF);
1580 val &= ~TRANS_ENABLE;
1581 I915_WRITE(LPT_TRANSCONF, val);
1582 /* wait for PCH transcoder off, transcoder state */
1583 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1584 DRM_ERROR("Failed to disable PCH transcoder\n");
1585
1586 /* Workaround: clear timing override bit. */
1587 val = I915_READ(_TRANSA_CHICKEN2);
1588 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1589 I915_WRITE(_TRANSA_CHICKEN2, val);
1590 }
1591
1592 /**
1593 * intel_enable_pipe - enable a pipe, asserting requirements
1594 * @dev_priv: i915 private structure
1595 * @pipe: pipe to enable
1596 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1597 *
1598 * Enable @pipe, making sure that various hardware specific requirements
1599 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1600 *
1601 * @pipe should be %PIPE_A or %PIPE_B.
1602 *
1603 * Will wait until the pipe is actually running (i.e. first vblank) before
1604 * returning.
1605 */
1606 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1607 bool pch_port)
1608 {
1609 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1610 pipe);
1611 enum pipe pch_transcoder;
1612 int reg;
1613 u32 val;
1614
1615 assert_planes_disabled(dev_priv, pipe);
1616 assert_sprites_disabled(dev_priv, pipe);
1617
1618 if (HAS_PCH_LPT(dev_priv->dev))
1619 pch_transcoder = TRANSCODER_A;
1620 else
1621 pch_transcoder = pipe;
1622
1623 /*
1624 * A pipe without a PLL won't actually be able to drive bits from
1625 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1626 * need the check.
1627 */
1628 if (!HAS_PCH_SPLIT(dev_priv->dev))
1629 assert_pll_enabled(dev_priv, pipe);
1630 else {
1631 if (pch_port) {
1632 /* if driving the PCH, we need FDI enabled */
1633 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1634 assert_fdi_tx_pll_enabled(dev_priv,
1635 (enum pipe) cpu_transcoder);
1636 }
1637 /* FIXME: assert CPU port conditions for SNB+ */
1638 }
1639
1640 reg = PIPECONF(cpu_transcoder);
1641 val = I915_READ(reg);
1642 if (val & PIPECONF_ENABLE)
1643 return;
1644
1645 I915_WRITE(reg, val | PIPECONF_ENABLE);
1646 intel_wait_for_vblank(dev_priv->dev, pipe);
1647 }
1648
1649 /**
1650 * intel_disable_pipe - disable a pipe, asserting requirements
1651 * @dev_priv: i915 private structure
1652 * @pipe: pipe to disable
1653 *
1654 * Disable @pipe, making sure that various hardware specific requirements
1655 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1656 *
1657 * @pipe should be %PIPE_A or %PIPE_B.
1658 *
1659 * Will wait until the pipe has shut down before returning.
1660 */
1661 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1662 enum pipe pipe)
1663 {
1664 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1665 pipe);
1666 int reg;
1667 u32 val;
1668
1669 /*
1670 * Make sure planes won't keep trying to pump pixels to us,
1671 * or we might hang the display.
1672 */
1673 assert_planes_disabled(dev_priv, pipe);
1674 assert_sprites_disabled(dev_priv, pipe);
1675
1676 /* Don't disable pipe A or pipe A PLLs if needed */
1677 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1678 return;
1679
1680 reg = PIPECONF(cpu_transcoder);
1681 val = I915_READ(reg);
1682 if ((val & PIPECONF_ENABLE) == 0)
1683 return;
1684
1685 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1686 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1687 }
1688
1689 /*
1690 * Plane regs are double buffered, going from enabled->disabled needs a
1691 * trigger in order to latch. The display address reg provides this.
1692 */
1693 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1694 enum plane plane)
1695 {
1696 if (dev_priv->info->gen >= 4)
1697 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1698 else
1699 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1700 }
1701
1702 /**
1703 * intel_enable_plane - enable a display plane on a given pipe
1704 * @dev_priv: i915 private structure
1705 * @plane: plane to enable
1706 * @pipe: pipe being fed
1707 *
1708 * Enable @plane on @pipe, making sure that @pipe is running first.
1709 */
1710 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1711 enum plane plane, enum pipe pipe)
1712 {
1713 int reg;
1714 u32 val;
1715
1716 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1717 assert_pipe_enabled(dev_priv, pipe);
1718
1719 reg = DSPCNTR(plane);
1720 val = I915_READ(reg);
1721 if (val & DISPLAY_PLANE_ENABLE)
1722 return;
1723
1724 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1725 intel_flush_display_plane(dev_priv, plane);
1726 intel_wait_for_vblank(dev_priv->dev, pipe);
1727 }
1728
1729 /**
1730 * intel_disable_plane - disable a display plane
1731 * @dev_priv: i915 private structure
1732 * @plane: plane to disable
1733 * @pipe: pipe consuming the data
1734 *
1735 * Disable @plane; should be an independent operation.
1736 */
1737 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1738 enum plane plane, enum pipe pipe)
1739 {
1740 int reg;
1741 u32 val;
1742
1743 reg = DSPCNTR(plane);
1744 val = I915_READ(reg);
1745 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1746 return;
1747
1748 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1749 intel_flush_display_plane(dev_priv, plane);
1750 intel_wait_for_vblank(dev_priv->dev, pipe);
1751 }
1752
1753 static bool need_vtd_wa(struct drm_device *dev)
1754 {
1755 #ifdef CONFIG_INTEL_IOMMU
1756 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1757 return true;
1758 #endif
1759 return false;
1760 }
1761
1762 int
1763 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1764 struct drm_i915_gem_object *obj,
1765 struct intel_ring_buffer *pipelined)
1766 {
1767 struct drm_i915_private *dev_priv = dev->dev_private;
1768 u32 alignment;
1769 int ret;
1770
1771 switch (obj->tiling_mode) {
1772 case I915_TILING_NONE:
1773 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1774 alignment = 128 * 1024;
1775 else if (INTEL_INFO(dev)->gen >= 4)
1776 alignment = 4 * 1024;
1777 else
1778 alignment = 64 * 1024;
1779 break;
1780 case I915_TILING_X:
1781 /* pin() will align the object as required by fence */
1782 alignment = 0;
1783 break;
1784 case I915_TILING_Y:
1785 /* Despite that we check this in framebuffer_init userspace can
1786 * screw us over and change the tiling after the fact. Only
1787 * pinned buffers can't change their tiling. */
1788 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1789 return -EINVAL;
1790 default:
1791 BUG();
1792 }
1793
1794 /* Note that the w/a also requires 64 PTE of padding following the
1795 * bo. We currently fill all unused PTE with the shadow page and so
1796 * we should always have valid PTE following the scanout preventing
1797 * the VT-d warning.
1798 */
1799 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1800 alignment = 256 * 1024;
1801
1802 dev_priv->mm.interruptible = false;
1803 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1804 if (ret)
1805 goto err_interruptible;
1806
1807 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1808 * fence, whereas 965+ only requires a fence if using
1809 * framebuffer compression. For simplicity, we always install
1810 * a fence as the cost is not that onerous.
1811 */
1812 ret = i915_gem_object_get_fence(obj);
1813 if (ret)
1814 goto err_unpin;
1815
1816 i915_gem_object_pin_fence(obj);
1817
1818 dev_priv->mm.interruptible = true;
1819 return 0;
1820
1821 err_unpin:
1822 i915_gem_object_unpin(obj);
1823 err_interruptible:
1824 dev_priv->mm.interruptible = true;
1825 return ret;
1826 }
1827
1828 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1829 {
1830 i915_gem_object_unpin_fence(obj);
1831 i915_gem_object_unpin(obj);
1832 }
1833
1834 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1835 * is assumed to be a power-of-two. */
1836 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1837 unsigned int tiling_mode,
1838 unsigned int cpp,
1839 unsigned int pitch)
1840 {
1841 if (tiling_mode != I915_TILING_NONE) {
1842 unsigned int tile_rows, tiles;
1843
1844 tile_rows = *y / 8;
1845 *y %= 8;
1846
1847 tiles = *x / (512/cpp);
1848 *x %= 512/cpp;
1849
1850 return tile_rows * pitch * 8 + tiles * 4096;
1851 } else {
1852 unsigned int offset;
1853
1854 offset = *y * pitch + *x * cpp;
1855 *y = 0;
1856 *x = (offset & 4095) / cpp;
1857 return offset & -4096;
1858 }
1859 }
1860
1861 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1862 int x, int y)
1863 {
1864 struct drm_device *dev = crtc->dev;
1865 struct drm_i915_private *dev_priv = dev->dev_private;
1866 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1867 struct intel_framebuffer *intel_fb;
1868 struct drm_i915_gem_object *obj;
1869 int plane = intel_crtc->plane;
1870 unsigned long linear_offset;
1871 u32 dspcntr;
1872 u32 reg;
1873
1874 switch (plane) {
1875 case 0:
1876 case 1:
1877 break;
1878 default:
1879 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1880 return -EINVAL;
1881 }
1882
1883 intel_fb = to_intel_framebuffer(fb);
1884 obj = intel_fb->obj;
1885
1886 reg = DSPCNTR(plane);
1887 dspcntr = I915_READ(reg);
1888 /* Mask out pixel format bits in case we change it */
1889 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1890 switch (fb->pixel_format) {
1891 case DRM_FORMAT_C8:
1892 dspcntr |= DISPPLANE_8BPP;
1893 break;
1894 case DRM_FORMAT_XRGB1555:
1895 case DRM_FORMAT_ARGB1555:
1896 dspcntr |= DISPPLANE_BGRX555;
1897 break;
1898 case DRM_FORMAT_RGB565:
1899 dspcntr |= DISPPLANE_BGRX565;
1900 break;
1901 case DRM_FORMAT_XRGB8888:
1902 case DRM_FORMAT_ARGB8888:
1903 dspcntr |= DISPPLANE_BGRX888;
1904 break;
1905 case DRM_FORMAT_XBGR8888:
1906 case DRM_FORMAT_ABGR8888:
1907 dspcntr |= DISPPLANE_RGBX888;
1908 break;
1909 case DRM_FORMAT_XRGB2101010:
1910 case DRM_FORMAT_ARGB2101010:
1911 dspcntr |= DISPPLANE_BGRX101010;
1912 break;
1913 case DRM_FORMAT_XBGR2101010:
1914 case DRM_FORMAT_ABGR2101010:
1915 dspcntr |= DISPPLANE_RGBX101010;
1916 break;
1917 default:
1918 BUG();
1919 }
1920
1921 if (INTEL_INFO(dev)->gen >= 4) {
1922 if (obj->tiling_mode != I915_TILING_NONE)
1923 dspcntr |= DISPPLANE_TILED;
1924 else
1925 dspcntr &= ~DISPPLANE_TILED;
1926 }
1927
1928 if (IS_G4X(dev))
1929 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1930
1931 I915_WRITE(reg, dspcntr);
1932
1933 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1934
1935 if (INTEL_INFO(dev)->gen >= 4) {
1936 intel_crtc->dspaddr_offset =
1937 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1938 fb->bits_per_pixel / 8,
1939 fb->pitches[0]);
1940 linear_offset -= intel_crtc->dspaddr_offset;
1941 } else {
1942 intel_crtc->dspaddr_offset = linear_offset;
1943 }
1944
1945 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
1946 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
1947 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1948 if (INTEL_INFO(dev)->gen >= 4) {
1949 I915_MODIFY_DISPBASE(DSPSURF(plane),
1950 obj->gtt_offset + intel_crtc->dspaddr_offset);
1951 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1952 I915_WRITE(DSPLINOFF(plane), linear_offset);
1953 } else
1954 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
1955 POSTING_READ(reg);
1956
1957 return 0;
1958 }
1959
1960 static int ironlake_update_plane(struct drm_crtc *crtc,
1961 struct drm_framebuffer *fb, int x, int y)
1962 {
1963 struct drm_device *dev = crtc->dev;
1964 struct drm_i915_private *dev_priv = dev->dev_private;
1965 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1966 struct intel_framebuffer *intel_fb;
1967 struct drm_i915_gem_object *obj;
1968 int plane = intel_crtc->plane;
1969 unsigned long linear_offset;
1970 u32 dspcntr;
1971 u32 reg;
1972
1973 switch (plane) {
1974 case 0:
1975 case 1:
1976 case 2:
1977 break;
1978 default:
1979 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1980 return -EINVAL;
1981 }
1982
1983 intel_fb = to_intel_framebuffer(fb);
1984 obj = intel_fb->obj;
1985
1986 reg = DSPCNTR(plane);
1987 dspcntr = I915_READ(reg);
1988 /* Mask out pixel format bits in case we change it */
1989 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1990 switch (fb->pixel_format) {
1991 case DRM_FORMAT_C8:
1992 dspcntr |= DISPPLANE_8BPP;
1993 break;
1994 case DRM_FORMAT_RGB565:
1995 dspcntr |= DISPPLANE_BGRX565;
1996 break;
1997 case DRM_FORMAT_XRGB8888:
1998 case DRM_FORMAT_ARGB8888:
1999 dspcntr |= DISPPLANE_BGRX888;
2000 break;
2001 case DRM_FORMAT_XBGR8888:
2002 case DRM_FORMAT_ABGR8888:
2003 dspcntr |= DISPPLANE_RGBX888;
2004 break;
2005 case DRM_FORMAT_XRGB2101010:
2006 case DRM_FORMAT_ARGB2101010:
2007 dspcntr |= DISPPLANE_BGRX101010;
2008 break;
2009 case DRM_FORMAT_XBGR2101010:
2010 case DRM_FORMAT_ABGR2101010:
2011 dspcntr |= DISPPLANE_RGBX101010;
2012 break;
2013 default:
2014 BUG();
2015 }
2016
2017 if (obj->tiling_mode != I915_TILING_NONE)
2018 dspcntr |= DISPPLANE_TILED;
2019 else
2020 dspcntr &= ~DISPPLANE_TILED;
2021
2022 /* must disable */
2023 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2024
2025 I915_WRITE(reg, dspcntr);
2026
2027 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2028 intel_crtc->dspaddr_offset =
2029 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2030 fb->bits_per_pixel / 8,
2031 fb->pitches[0]);
2032 linear_offset -= intel_crtc->dspaddr_offset;
2033
2034 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2035 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2036 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2037 I915_MODIFY_DISPBASE(DSPSURF(plane),
2038 obj->gtt_offset + intel_crtc->dspaddr_offset);
2039 if (IS_HASWELL(dev)) {
2040 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2041 } else {
2042 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2043 I915_WRITE(DSPLINOFF(plane), linear_offset);
2044 }
2045 POSTING_READ(reg);
2046
2047 return 0;
2048 }
2049
2050 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2051 static int
2052 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2053 int x, int y, enum mode_set_atomic state)
2054 {
2055 struct drm_device *dev = crtc->dev;
2056 struct drm_i915_private *dev_priv = dev->dev_private;
2057
2058 if (dev_priv->display.disable_fbc)
2059 dev_priv->display.disable_fbc(dev);
2060 intel_increase_pllclock(crtc);
2061
2062 return dev_priv->display.update_plane(crtc, fb, x, y);
2063 }
2064
2065 void intel_display_handle_reset(struct drm_device *dev)
2066 {
2067 struct drm_i915_private *dev_priv = dev->dev_private;
2068 struct drm_crtc *crtc;
2069
2070 /*
2071 * Flips in the rings have been nuked by the reset,
2072 * so complete all pending flips so that user space
2073 * will get its events and not get stuck.
2074 *
2075 * Also update the base address of all primary
2076 * planes to the the last fb to make sure we're
2077 * showing the correct fb after a reset.
2078 *
2079 * Need to make two loops over the crtcs so that we
2080 * don't try to grab a crtc mutex before the
2081 * pending_flip_queue really got woken up.
2082 */
2083
2084 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2085 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2086 enum plane plane = intel_crtc->plane;
2087
2088 intel_prepare_page_flip(dev, plane);
2089 intel_finish_page_flip_plane(dev, plane);
2090 }
2091
2092 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2093 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2094
2095 mutex_lock(&crtc->mutex);
2096 if (intel_crtc->active)
2097 dev_priv->display.update_plane(crtc, crtc->fb,
2098 crtc->x, crtc->y);
2099 mutex_unlock(&crtc->mutex);
2100 }
2101 }
2102
2103 static int
2104 intel_finish_fb(struct drm_framebuffer *old_fb)
2105 {
2106 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2107 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2108 bool was_interruptible = dev_priv->mm.interruptible;
2109 int ret;
2110
2111 /* Big Hammer, we also need to ensure that any pending
2112 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2113 * current scanout is retired before unpinning the old
2114 * framebuffer.
2115 *
2116 * This should only fail upon a hung GPU, in which case we
2117 * can safely continue.
2118 */
2119 dev_priv->mm.interruptible = false;
2120 ret = i915_gem_object_finish_gpu(obj);
2121 dev_priv->mm.interruptible = was_interruptible;
2122
2123 return ret;
2124 }
2125
2126 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2127 {
2128 struct drm_device *dev = crtc->dev;
2129 struct drm_i915_master_private *master_priv;
2130 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2131
2132 if (!dev->primary->master)
2133 return;
2134
2135 master_priv = dev->primary->master->driver_priv;
2136 if (!master_priv->sarea_priv)
2137 return;
2138
2139 switch (intel_crtc->pipe) {
2140 case 0:
2141 master_priv->sarea_priv->pipeA_x = x;
2142 master_priv->sarea_priv->pipeA_y = y;
2143 break;
2144 case 1:
2145 master_priv->sarea_priv->pipeB_x = x;
2146 master_priv->sarea_priv->pipeB_y = y;
2147 break;
2148 default:
2149 break;
2150 }
2151 }
2152
2153 static int
2154 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2155 struct drm_framebuffer *fb)
2156 {
2157 struct drm_device *dev = crtc->dev;
2158 struct drm_i915_private *dev_priv = dev->dev_private;
2159 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2160 struct drm_framebuffer *old_fb;
2161 int ret;
2162
2163 /* no fb bound */
2164 if (!fb) {
2165 DRM_ERROR("No FB bound\n");
2166 return 0;
2167 }
2168
2169 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2170 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2171 plane_name(intel_crtc->plane),
2172 INTEL_INFO(dev)->num_pipes);
2173 return -EINVAL;
2174 }
2175
2176 mutex_lock(&dev->struct_mutex);
2177 ret = intel_pin_and_fence_fb_obj(dev,
2178 to_intel_framebuffer(fb)->obj,
2179 NULL);
2180 if (ret != 0) {
2181 mutex_unlock(&dev->struct_mutex);
2182 DRM_ERROR("pin & fence failed\n");
2183 return ret;
2184 }
2185
2186 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2187 if (ret) {
2188 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2189 mutex_unlock(&dev->struct_mutex);
2190 DRM_ERROR("failed to update base address\n");
2191 return ret;
2192 }
2193
2194 old_fb = crtc->fb;
2195 crtc->fb = fb;
2196 crtc->x = x;
2197 crtc->y = y;
2198
2199 if (old_fb) {
2200 if (intel_crtc->active && old_fb != fb)
2201 intel_wait_for_vblank(dev, intel_crtc->pipe);
2202 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2203 }
2204
2205 intel_update_fbc(dev);
2206 mutex_unlock(&dev->struct_mutex);
2207
2208 intel_crtc_update_sarea_pos(crtc, x, y);
2209
2210 return 0;
2211 }
2212
2213 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2214 {
2215 struct drm_device *dev = crtc->dev;
2216 struct drm_i915_private *dev_priv = dev->dev_private;
2217 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2218 int pipe = intel_crtc->pipe;
2219 u32 reg, temp;
2220
2221 /* enable normal train */
2222 reg = FDI_TX_CTL(pipe);
2223 temp = I915_READ(reg);
2224 if (IS_IVYBRIDGE(dev)) {
2225 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2226 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2227 } else {
2228 temp &= ~FDI_LINK_TRAIN_NONE;
2229 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2230 }
2231 I915_WRITE(reg, temp);
2232
2233 reg = FDI_RX_CTL(pipe);
2234 temp = I915_READ(reg);
2235 if (HAS_PCH_CPT(dev)) {
2236 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2237 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2238 } else {
2239 temp &= ~FDI_LINK_TRAIN_NONE;
2240 temp |= FDI_LINK_TRAIN_NONE;
2241 }
2242 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2243
2244 /* wait one idle pattern time */
2245 POSTING_READ(reg);
2246 udelay(1000);
2247
2248 /* IVB wants error correction enabled */
2249 if (IS_IVYBRIDGE(dev))
2250 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2251 FDI_FE_ERRC_ENABLE);
2252 }
2253
2254 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2255 {
2256 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2257 }
2258
2259 static void ivb_modeset_global_resources(struct drm_device *dev)
2260 {
2261 struct drm_i915_private *dev_priv = dev->dev_private;
2262 struct intel_crtc *pipe_B_crtc =
2263 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2264 struct intel_crtc *pipe_C_crtc =
2265 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2266 uint32_t temp;
2267
2268 /*
2269 * When everything is off disable fdi C so that we could enable fdi B
2270 * with all lanes. Note that we don't care about enabled pipes without
2271 * an enabled pch encoder.
2272 */
2273 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2274 !pipe_has_enabled_pch(pipe_C_crtc)) {
2275 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2276 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2277
2278 temp = I915_READ(SOUTH_CHICKEN1);
2279 temp &= ~FDI_BC_BIFURCATION_SELECT;
2280 DRM_DEBUG_KMS("disabling fdi C rx\n");
2281 I915_WRITE(SOUTH_CHICKEN1, temp);
2282 }
2283 }
2284
2285 /* The FDI link training functions for ILK/Ibexpeak. */
2286 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2287 {
2288 struct drm_device *dev = crtc->dev;
2289 struct drm_i915_private *dev_priv = dev->dev_private;
2290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2291 int pipe = intel_crtc->pipe;
2292 int plane = intel_crtc->plane;
2293 u32 reg, temp, tries;
2294
2295 /* FDI needs bits from pipe & plane first */
2296 assert_pipe_enabled(dev_priv, pipe);
2297 assert_plane_enabled(dev_priv, plane);
2298
2299 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2300 for train result */
2301 reg = FDI_RX_IMR(pipe);
2302 temp = I915_READ(reg);
2303 temp &= ~FDI_RX_SYMBOL_LOCK;
2304 temp &= ~FDI_RX_BIT_LOCK;
2305 I915_WRITE(reg, temp);
2306 I915_READ(reg);
2307 udelay(150);
2308
2309 /* enable CPU FDI TX and PCH FDI RX */
2310 reg = FDI_TX_CTL(pipe);
2311 temp = I915_READ(reg);
2312 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2313 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2314 temp &= ~FDI_LINK_TRAIN_NONE;
2315 temp |= FDI_LINK_TRAIN_PATTERN_1;
2316 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2317
2318 reg = FDI_RX_CTL(pipe);
2319 temp = I915_READ(reg);
2320 temp &= ~FDI_LINK_TRAIN_NONE;
2321 temp |= FDI_LINK_TRAIN_PATTERN_1;
2322 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2323
2324 POSTING_READ(reg);
2325 udelay(150);
2326
2327 /* Ironlake workaround, enable clock pointer after FDI enable*/
2328 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2329 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2330 FDI_RX_PHASE_SYNC_POINTER_EN);
2331
2332 reg = FDI_RX_IIR(pipe);
2333 for (tries = 0; tries < 5; tries++) {
2334 temp = I915_READ(reg);
2335 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2336
2337 if ((temp & FDI_RX_BIT_LOCK)) {
2338 DRM_DEBUG_KMS("FDI train 1 done.\n");
2339 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2340 break;
2341 }
2342 }
2343 if (tries == 5)
2344 DRM_ERROR("FDI train 1 fail!\n");
2345
2346 /* Train 2 */
2347 reg = FDI_TX_CTL(pipe);
2348 temp = I915_READ(reg);
2349 temp &= ~FDI_LINK_TRAIN_NONE;
2350 temp |= FDI_LINK_TRAIN_PATTERN_2;
2351 I915_WRITE(reg, temp);
2352
2353 reg = FDI_RX_CTL(pipe);
2354 temp = I915_READ(reg);
2355 temp &= ~FDI_LINK_TRAIN_NONE;
2356 temp |= FDI_LINK_TRAIN_PATTERN_2;
2357 I915_WRITE(reg, temp);
2358
2359 POSTING_READ(reg);
2360 udelay(150);
2361
2362 reg = FDI_RX_IIR(pipe);
2363 for (tries = 0; tries < 5; tries++) {
2364 temp = I915_READ(reg);
2365 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2366
2367 if (temp & FDI_RX_SYMBOL_LOCK) {
2368 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2369 DRM_DEBUG_KMS("FDI train 2 done.\n");
2370 break;
2371 }
2372 }
2373 if (tries == 5)
2374 DRM_ERROR("FDI train 2 fail!\n");
2375
2376 DRM_DEBUG_KMS("FDI train done\n");
2377
2378 }
2379
2380 static const int snb_b_fdi_train_param[] = {
2381 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2382 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2383 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2384 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2385 };
2386
2387 /* The FDI link training functions for SNB/Cougarpoint. */
2388 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2389 {
2390 struct drm_device *dev = crtc->dev;
2391 struct drm_i915_private *dev_priv = dev->dev_private;
2392 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2393 int pipe = intel_crtc->pipe;
2394 u32 reg, temp, i, retry;
2395
2396 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2397 for train result */
2398 reg = FDI_RX_IMR(pipe);
2399 temp = I915_READ(reg);
2400 temp &= ~FDI_RX_SYMBOL_LOCK;
2401 temp &= ~FDI_RX_BIT_LOCK;
2402 I915_WRITE(reg, temp);
2403
2404 POSTING_READ(reg);
2405 udelay(150);
2406
2407 /* enable CPU FDI TX and PCH FDI RX */
2408 reg = FDI_TX_CTL(pipe);
2409 temp = I915_READ(reg);
2410 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2411 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2412 temp &= ~FDI_LINK_TRAIN_NONE;
2413 temp |= FDI_LINK_TRAIN_PATTERN_1;
2414 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2415 /* SNB-B */
2416 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2417 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2418
2419 I915_WRITE(FDI_RX_MISC(pipe),
2420 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2421
2422 reg = FDI_RX_CTL(pipe);
2423 temp = I915_READ(reg);
2424 if (HAS_PCH_CPT(dev)) {
2425 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2426 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2427 } else {
2428 temp &= ~FDI_LINK_TRAIN_NONE;
2429 temp |= FDI_LINK_TRAIN_PATTERN_1;
2430 }
2431 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2432
2433 POSTING_READ(reg);
2434 udelay(150);
2435
2436 for (i = 0; i < 4; i++) {
2437 reg = FDI_TX_CTL(pipe);
2438 temp = I915_READ(reg);
2439 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2440 temp |= snb_b_fdi_train_param[i];
2441 I915_WRITE(reg, temp);
2442
2443 POSTING_READ(reg);
2444 udelay(500);
2445
2446 for (retry = 0; retry < 5; retry++) {
2447 reg = FDI_RX_IIR(pipe);
2448 temp = I915_READ(reg);
2449 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2450 if (temp & FDI_RX_BIT_LOCK) {
2451 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2452 DRM_DEBUG_KMS("FDI train 1 done.\n");
2453 break;
2454 }
2455 udelay(50);
2456 }
2457 if (retry < 5)
2458 break;
2459 }
2460 if (i == 4)
2461 DRM_ERROR("FDI train 1 fail!\n");
2462
2463 /* Train 2 */
2464 reg = FDI_TX_CTL(pipe);
2465 temp = I915_READ(reg);
2466 temp &= ~FDI_LINK_TRAIN_NONE;
2467 temp |= FDI_LINK_TRAIN_PATTERN_2;
2468 if (IS_GEN6(dev)) {
2469 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2470 /* SNB-B */
2471 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2472 }
2473 I915_WRITE(reg, temp);
2474
2475 reg = FDI_RX_CTL(pipe);
2476 temp = I915_READ(reg);
2477 if (HAS_PCH_CPT(dev)) {
2478 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2479 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2480 } else {
2481 temp &= ~FDI_LINK_TRAIN_NONE;
2482 temp |= FDI_LINK_TRAIN_PATTERN_2;
2483 }
2484 I915_WRITE(reg, temp);
2485
2486 POSTING_READ(reg);
2487 udelay(150);
2488
2489 for (i = 0; i < 4; i++) {
2490 reg = FDI_TX_CTL(pipe);
2491 temp = I915_READ(reg);
2492 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2493 temp |= snb_b_fdi_train_param[i];
2494 I915_WRITE(reg, temp);
2495
2496 POSTING_READ(reg);
2497 udelay(500);
2498
2499 for (retry = 0; retry < 5; retry++) {
2500 reg = FDI_RX_IIR(pipe);
2501 temp = I915_READ(reg);
2502 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2503 if (temp & FDI_RX_SYMBOL_LOCK) {
2504 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2505 DRM_DEBUG_KMS("FDI train 2 done.\n");
2506 break;
2507 }
2508 udelay(50);
2509 }
2510 if (retry < 5)
2511 break;
2512 }
2513 if (i == 4)
2514 DRM_ERROR("FDI train 2 fail!\n");
2515
2516 DRM_DEBUG_KMS("FDI train done.\n");
2517 }
2518
2519 /* Manual link training for Ivy Bridge A0 parts */
2520 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2521 {
2522 struct drm_device *dev = crtc->dev;
2523 struct drm_i915_private *dev_priv = dev->dev_private;
2524 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2525 int pipe = intel_crtc->pipe;
2526 u32 reg, temp, i;
2527
2528 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2529 for train result */
2530 reg = FDI_RX_IMR(pipe);
2531 temp = I915_READ(reg);
2532 temp &= ~FDI_RX_SYMBOL_LOCK;
2533 temp &= ~FDI_RX_BIT_LOCK;
2534 I915_WRITE(reg, temp);
2535
2536 POSTING_READ(reg);
2537 udelay(150);
2538
2539 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2540 I915_READ(FDI_RX_IIR(pipe)));
2541
2542 /* enable CPU FDI TX and PCH FDI RX */
2543 reg = FDI_TX_CTL(pipe);
2544 temp = I915_READ(reg);
2545 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2546 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2547 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2548 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2549 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2550 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2551 temp |= FDI_COMPOSITE_SYNC;
2552 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2553
2554 I915_WRITE(FDI_RX_MISC(pipe),
2555 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2556
2557 reg = FDI_RX_CTL(pipe);
2558 temp = I915_READ(reg);
2559 temp &= ~FDI_LINK_TRAIN_AUTO;
2560 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2561 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2562 temp |= FDI_COMPOSITE_SYNC;
2563 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2564
2565 POSTING_READ(reg);
2566 udelay(150);
2567
2568 for (i = 0; i < 4; i++) {
2569 reg = FDI_TX_CTL(pipe);
2570 temp = I915_READ(reg);
2571 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2572 temp |= snb_b_fdi_train_param[i];
2573 I915_WRITE(reg, temp);
2574
2575 POSTING_READ(reg);
2576 udelay(500);
2577
2578 reg = FDI_RX_IIR(pipe);
2579 temp = I915_READ(reg);
2580 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2581
2582 if (temp & FDI_RX_BIT_LOCK ||
2583 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2584 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2585 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2586 break;
2587 }
2588 }
2589 if (i == 4)
2590 DRM_ERROR("FDI train 1 fail!\n");
2591
2592 /* Train 2 */
2593 reg = FDI_TX_CTL(pipe);
2594 temp = I915_READ(reg);
2595 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2596 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2597 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2598 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2599 I915_WRITE(reg, temp);
2600
2601 reg = FDI_RX_CTL(pipe);
2602 temp = I915_READ(reg);
2603 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2604 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2605 I915_WRITE(reg, temp);
2606
2607 POSTING_READ(reg);
2608 udelay(150);
2609
2610 for (i = 0; i < 4; i++) {
2611 reg = FDI_TX_CTL(pipe);
2612 temp = I915_READ(reg);
2613 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2614 temp |= snb_b_fdi_train_param[i];
2615 I915_WRITE(reg, temp);
2616
2617 POSTING_READ(reg);
2618 udelay(500);
2619
2620 reg = FDI_RX_IIR(pipe);
2621 temp = I915_READ(reg);
2622 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2623
2624 if (temp & FDI_RX_SYMBOL_LOCK) {
2625 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2626 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2627 break;
2628 }
2629 }
2630 if (i == 4)
2631 DRM_ERROR("FDI train 2 fail!\n");
2632
2633 DRM_DEBUG_KMS("FDI train done.\n");
2634 }
2635
2636 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2637 {
2638 struct drm_device *dev = intel_crtc->base.dev;
2639 struct drm_i915_private *dev_priv = dev->dev_private;
2640 int pipe = intel_crtc->pipe;
2641 u32 reg, temp;
2642
2643
2644 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2645 reg = FDI_RX_CTL(pipe);
2646 temp = I915_READ(reg);
2647 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2648 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2649 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2650 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2651
2652 POSTING_READ(reg);
2653 udelay(200);
2654
2655 /* Switch from Rawclk to PCDclk */
2656 temp = I915_READ(reg);
2657 I915_WRITE(reg, temp | FDI_PCDCLK);
2658
2659 POSTING_READ(reg);
2660 udelay(200);
2661
2662 /* Enable CPU FDI TX PLL, always on for Ironlake */
2663 reg = FDI_TX_CTL(pipe);
2664 temp = I915_READ(reg);
2665 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2666 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2667
2668 POSTING_READ(reg);
2669 udelay(100);
2670 }
2671 }
2672
2673 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2674 {
2675 struct drm_device *dev = intel_crtc->base.dev;
2676 struct drm_i915_private *dev_priv = dev->dev_private;
2677 int pipe = intel_crtc->pipe;
2678 u32 reg, temp;
2679
2680 /* Switch from PCDclk to Rawclk */
2681 reg = FDI_RX_CTL(pipe);
2682 temp = I915_READ(reg);
2683 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2684
2685 /* Disable CPU FDI TX PLL */
2686 reg = FDI_TX_CTL(pipe);
2687 temp = I915_READ(reg);
2688 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2689
2690 POSTING_READ(reg);
2691 udelay(100);
2692
2693 reg = FDI_RX_CTL(pipe);
2694 temp = I915_READ(reg);
2695 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2696
2697 /* Wait for the clocks to turn off. */
2698 POSTING_READ(reg);
2699 udelay(100);
2700 }
2701
2702 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2703 {
2704 struct drm_device *dev = crtc->dev;
2705 struct drm_i915_private *dev_priv = dev->dev_private;
2706 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2707 int pipe = intel_crtc->pipe;
2708 u32 reg, temp;
2709
2710 /* disable CPU FDI tx and PCH FDI rx */
2711 reg = FDI_TX_CTL(pipe);
2712 temp = I915_READ(reg);
2713 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2714 POSTING_READ(reg);
2715
2716 reg = FDI_RX_CTL(pipe);
2717 temp = I915_READ(reg);
2718 temp &= ~(0x7 << 16);
2719 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2720 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2721
2722 POSTING_READ(reg);
2723 udelay(100);
2724
2725 /* Ironlake workaround, disable clock pointer after downing FDI */
2726 if (HAS_PCH_IBX(dev)) {
2727 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2728 }
2729
2730 /* still set train pattern 1 */
2731 reg = FDI_TX_CTL(pipe);
2732 temp = I915_READ(reg);
2733 temp &= ~FDI_LINK_TRAIN_NONE;
2734 temp |= FDI_LINK_TRAIN_PATTERN_1;
2735 I915_WRITE(reg, temp);
2736
2737 reg = FDI_RX_CTL(pipe);
2738 temp = I915_READ(reg);
2739 if (HAS_PCH_CPT(dev)) {
2740 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2741 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2742 } else {
2743 temp &= ~FDI_LINK_TRAIN_NONE;
2744 temp |= FDI_LINK_TRAIN_PATTERN_1;
2745 }
2746 /* BPC in FDI rx is consistent with that in PIPECONF */
2747 temp &= ~(0x07 << 16);
2748 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2749 I915_WRITE(reg, temp);
2750
2751 POSTING_READ(reg);
2752 udelay(100);
2753 }
2754
2755 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2756 {
2757 struct drm_device *dev = crtc->dev;
2758 struct drm_i915_private *dev_priv = dev->dev_private;
2759 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2760 unsigned long flags;
2761 bool pending;
2762
2763 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2764 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2765 return false;
2766
2767 spin_lock_irqsave(&dev->event_lock, flags);
2768 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2769 spin_unlock_irqrestore(&dev->event_lock, flags);
2770
2771 return pending;
2772 }
2773
2774 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2775 {
2776 struct drm_device *dev = crtc->dev;
2777 struct drm_i915_private *dev_priv = dev->dev_private;
2778
2779 if (crtc->fb == NULL)
2780 return;
2781
2782 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2783
2784 wait_event(dev_priv->pending_flip_queue,
2785 !intel_crtc_has_pending_flip(crtc));
2786
2787 mutex_lock(&dev->struct_mutex);
2788 intel_finish_fb(crtc->fb);
2789 mutex_unlock(&dev->struct_mutex);
2790 }
2791
2792 /* Program iCLKIP clock to the desired frequency */
2793 static void lpt_program_iclkip(struct drm_crtc *crtc)
2794 {
2795 struct drm_device *dev = crtc->dev;
2796 struct drm_i915_private *dev_priv = dev->dev_private;
2797 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2798 u32 temp;
2799
2800 mutex_lock(&dev_priv->dpio_lock);
2801
2802 /* It is necessary to ungate the pixclk gate prior to programming
2803 * the divisors, and gate it back when it is done.
2804 */
2805 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2806
2807 /* Disable SSCCTL */
2808 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2809 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2810 SBI_SSCCTL_DISABLE,
2811 SBI_ICLK);
2812
2813 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2814 if (crtc->mode.clock == 20000) {
2815 auxdiv = 1;
2816 divsel = 0x41;
2817 phaseinc = 0x20;
2818 } else {
2819 /* The iCLK virtual clock root frequency is in MHz,
2820 * but the crtc->mode.clock in in KHz. To get the divisors,
2821 * it is necessary to divide one by another, so we
2822 * convert the virtual clock precision to KHz here for higher
2823 * precision.
2824 */
2825 u32 iclk_virtual_root_freq = 172800 * 1000;
2826 u32 iclk_pi_range = 64;
2827 u32 desired_divisor, msb_divisor_value, pi_value;
2828
2829 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2830 msb_divisor_value = desired_divisor / iclk_pi_range;
2831 pi_value = desired_divisor % iclk_pi_range;
2832
2833 auxdiv = 0;
2834 divsel = msb_divisor_value - 2;
2835 phaseinc = pi_value;
2836 }
2837
2838 /* This should not happen with any sane values */
2839 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2840 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2841 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2842 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2843
2844 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2845 crtc->mode.clock,
2846 auxdiv,
2847 divsel,
2848 phasedir,
2849 phaseinc);
2850
2851 /* Program SSCDIVINTPHASE6 */
2852 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2853 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2854 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2855 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2856 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2857 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2858 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2859 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2860
2861 /* Program SSCAUXDIV */
2862 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2863 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2864 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2865 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2866
2867 /* Enable modulator and associated divider */
2868 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2869 temp &= ~SBI_SSCCTL_DISABLE;
2870 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2871
2872 /* Wait for initialization time */
2873 udelay(24);
2874
2875 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2876
2877 mutex_unlock(&dev_priv->dpio_lock);
2878 }
2879
2880 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2881 enum pipe pch_transcoder)
2882 {
2883 struct drm_device *dev = crtc->base.dev;
2884 struct drm_i915_private *dev_priv = dev->dev_private;
2885 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2886
2887 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2888 I915_READ(HTOTAL(cpu_transcoder)));
2889 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2890 I915_READ(HBLANK(cpu_transcoder)));
2891 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2892 I915_READ(HSYNC(cpu_transcoder)));
2893
2894 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2895 I915_READ(VTOTAL(cpu_transcoder)));
2896 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2897 I915_READ(VBLANK(cpu_transcoder)));
2898 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2899 I915_READ(VSYNC(cpu_transcoder)));
2900 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2901 I915_READ(VSYNCSHIFT(cpu_transcoder)));
2902 }
2903
2904 /*
2905 * Enable PCH resources required for PCH ports:
2906 * - PCH PLLs
2907 * - FDI training & RX/TX
2908 * - update transcoder timings
2909 * - DP transcoding bits
2910 * - transcoder
2911 */
2912 static void ironlake_pch_enable(struct drm_crtc *crtc)
2913 {
2914 struct drm_device *dev = crtc->dev;
2915 struct drm_i915_private *dev_priv = dev->dev_private;
2916 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2917 int pipe = intel_crtc->pipe;
2918 u32 reg, temp;
2919
2920 assert_pch_transcoder_disabled(dev_priv, pipe);
2921
2922 /* Write the TU size bits before fdi link training, so that error
2923 * detection works. */
2924 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2925 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2926
2927 /* For PCH output, training FDI link */
2928 dev_priv->display.fdi_link_train(crtc);
2929
2930 /* XXX: pch pll's can be enabled any time before we enable the PCH
2931 * transcoder, and we actually should do this to not upset any PCH
2932 * transcoder that already use the clock when we share it.
2933 *
2934 * Note that enable_shared_dpll tries to do the right thing, but
2935 * get_shared_dpll unconditionally resets the pll - we need that to have
2936 * the right LVDS enable sequence. */
2937 ironlake_enable_shared_dpll(intel_crtc);
2938
2939 if (HAS_PCH_CPT(dev)) {
2940 u32 sel;
2941
2942 temp = I915_READ(PCH_DPLL_SEL);
2943 temp |= TRANS_DPLL_ENABLE(pipe);
2944 sel = TRANS_DPLLB_SEL(pipe);
2945 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
2946 temp |= sel;
2947 else
2948 temp &= ~sel;
2949 I915_WRITE(PCH_DPLL_SEL, temp);
2950 }
2951
2952 /* set transcoder timing, panel must allow it */
2953 assert_panel_unlocked(dev_priv, pipe);
2954 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
2955
2956 intel_fdi_normal_train(crtc);
2957
2958 /* For PCH DP, enable TRANS_DP_CTL */
2959 if (HAS_PCH_CPT(dev) &&
2960 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2961 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2962 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
2963 reg = TRANS_DP_CTL(pipe);
2964 temp = I915_READ(reg);
2965 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2966 TRANS_DP_SYNC_MASK |
2967 TRANS_DP_BPC_MASK);
2968 temp |= (TRANS_DP_OUTPUT_ENABLE |
2969 TRANS_DP_ENH_FRAMING);
2970 temp |= bpc << 9; /* same format but at 11:9 */
2971
2972 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2973 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2974 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2975 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2976
2977 switch (intel_trans_dp_port_sel(crtc)) {
2978 case PCH_DP_B:
2979 temp |= TRANS_DP_PORT_SEL_B;
2980 break;
2981 case PCH_DP_C:
2982 temp |= TRANS_DP_PORT_SEL_C;
2983 break;
2984 case PCH_DP_D:
2985 temp |= TRANS_DP_PORT_SEL_D;
2986 break;
2987 default:
2988 BUG();
2989 }
2990
2991 I915_WRITE(reg, temp);
2992 }
2993
2994 ironlake_enable_pch_transcoder(dev_priv, pipe);
2995 }
2996
2997 static void lpt_pch_enable(struct drm_crtc *crtc)
2998 {
2999 struct drm_device *dev = crtc->dev;
3000 struct drm_i915_private *dev_priv = dev->dev_private;
3001 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3002 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3003
3004 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3005
3006 lpt_program_iclkip(crtc);
3007
3008 /* Set transcoder timing. */
3009 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3010
3011 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3012 }
3013
3014 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3015 {
3016 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3017
3018 if (pll == NULL)
3019 return;
3020
3021 if (pll->refcount == 0) {
3022 WARN(1, "bad %s refcount\n", pll->name);
3023 return;
3024 }
3025
3026 if (--pll->refcount == 0) {
3027 WARN_ON(pll->on);
3028 WARN_ON(pll->active);
3029 }
3030
3031 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3032 }
3033
3034 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, u32 dpll, u32 fp)
3035 {
3036 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3037 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3038 enum intel_dpll_id i;
3039
3040 if (pll) {
3041 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3042 crtc->base.base.id, pll->name);
3043 intel_put_shared_dpll(crtc);
3044 }
3045
3046 if (HAS_PCH_IBX(dev_priv->dev)) {
3047 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3048 i = crtc->pipe;
3049 pll = &dev_priv->shared_dplls[i];
3050
3051 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3052 crtc->base.base.id, pll->name);
3053
3054 goto found;
3055 }
3056
3057 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3058 pll = &dev_priv->shared_dplls[i];
3059
3060 /* Only want to check enabled timings first */
3061 if (pll->refcount == 0)
3062 continue;
3063
3064 if (dpll == (I915_READ(PCH_DPLL(pll->id)) & 0x7fffffff) &&
3065 fp == I915_READ(PCH_FP0(pll->id))) {
3066 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3067 crtc->base.base.id,
3068 pll->name, pll->refcount, pll->active);
3069
3070 goto found;
3071 }
3072 }
3073
3074 /* Ok no matching timings, maybe there's a free one? */
3075 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3076 pll = &dev_priv->shared_dplls[i];
3077 if (pll->refcount == 0) {
3078 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3079 crtc->base.base.id, pll->name);
3080 goto found;
3081 }
3082 }
3083
3084 return NULL;
3085
3086 found:
3087 crtc->config.shared_dpll = i;
3088 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3089 pipe_name(crtc->pipe));
3090
3091 if (pll->active == 0) {
3092 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3093 sizeof(pll->hw_state));
3094
3095 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3096 WARN_ON(pll->on);
3097 assert_shared_dpll_disabled(dev_priv, pll);
3098
3099 /* Wait for the clocks to stabilize before rewriting the regs */
3100 I915_WRITE(PCH_DPLL(pll->id), dpll & ~DPLL_VCO_ENABLE);
3101 POSTING_READ(PCH_DPLL(pll->id));
3102 udelay(150);
3103
3104 I915_WRITE(PCH_FP0(pll->id), fp);
3105 I915_WRITE(PCH_DPLL(pll->id), dpll & ~DPLL_VCO_ENABLE);
3106 }
3107 pll->refcount++;
3108
3109 return pll;
3110 }
3111
3112 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3113 {
3114 struct drm_i915_private *dev_priv = dev->dev_private;
3115 int dslreg = PIPEDSL(pipe);
3116 u32 temp;
3117
3118 temp = I915_READ(dslreg);
3119 udelay(500);
3120 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3121 if (wait_for(I915_READ(dslreg) != temp, 5))
3122 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3123 }
3124 }
3125
3126 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3127 {
3128 struct drm_device *dev = crtc->base.dev;
3129 struct drm_i915_private *dev_priv = dev->dev_private;
3130 int pipe = crtc->pipe;
3131
3132 if (crtc->config.pch_pfit.size) {
3133 /* Force use of hard-coded filter coefficients
3134 * as some pre-programmed values are broken,
3135 * e.g. x201.
3136 */
3137 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3138 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3139 PF_PIPE_SEL_IVB(pipe));
3140 else
3141 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3142 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3143 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3144 }
3145 }
3146
3147 static void intel_enable_planes(struct drm_crtc *crtc)
3148 {
3149 struct drm_device *dev = crtc->dev;
3150 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3151 struct intel_plane *intel_plane;
3152
3153 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3154 if (intel_plane->pipe == pipe)
3155 intel_plane_restore(&intel_plane->base);
3156 }
3157
3158 static void intel_disable_planes(struct drm_crtc *crtc)
3159 {
3160 struct drm_device *dev = crtc->dev;
3161 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3162 struct intel_plane *intel_plane;
3163
3164 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3165 if (intel_plane->pipe == pipe)
3166 intel_plane_disable(&intel_plane->base);
3167 }
3168
3169 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3170 {
3171 struct drm_device *dev = crtc->dev;
3172 struct drm_i915_private *dev_priv = dev->dev_private;
3173 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3174 struct intel_encoder *encoder;
3175 int pipe = intel_crtc->pipe;
3176 int plane = intel_crtc->plane;
3177 u32 temp;
3178
3179 WARN_ON(!crtc->enabled);
3180
3181 if (intel_crtc->active)
3182 return;
3183
3184 intel_crtc->active = true;
3185
3186 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3187 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3188
3189 intel_update_watermarks(dev);
3190
3191 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3192 temp = I915_READ(PCH_LVDS);
3193 if ((temp & LVDS_PORT_EN) == 0)
3194 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3195 }
3196
3197
3198 if (intel_crtc->config.has_pch_encoder) {
3199 /* Note: FDI PLL enabling _must_ be done before we enable the
3200 * cpu pipes, hence this is separate from all the other fdi/pch
3201 * enabling. */
3202 ironlake_fdi_pll_enable(intel_crtc);
3203 } else {
3204 assert_fdi_tx_disabled(dev_priv, pipe);
3205 assert_fdi_rx_disabled(dev_priv, pipe);
3206 }
3207
3208 for_each_encoder_on_crtc(dev, crtc, encoder)
3209 if (encoder->pre_enable)
3210 encoder->pre_enable(encoder);
3211
3212 ironlake_pfit_enable(intel_crtc);
3213
3214 /*
3215 * On ILK+ LUT must be loaded before the pipe is running but with
3216 * clocks enabled
3217 */
3218 intel_crtc_load_lut(crtc);
3219
3220 intel_enable_pipe(dev_priv, pipe,
3221 intel_crtc->config.has_pch_encoder);
3222 intel_enable_plane(dev_priv, plane, pipe);
3223 intel_enable_planes(crtc);
3224 intel_crtc_update_cursor(crtc, true);
3225
3226 if (intel_crtc->config.has_pch_encoder)
3227 ironlake_pch_enable(crtc);
3228
3229 mutex_lock(&dev->struct_mutex);
3230 intel_update_fbc(dev);
3231 mutex_unlock(&dev->struct_mutex);
3232
3233 for_each_encoder_on_crtc(dev, crtc, encoder)
3234 encoder->enable(encoder);
3235
3236 if (HAS_PCH_CPT(dev))
3237 cpt_verify_modeset(dev, intel_crtc->pipe);
3238
3239 /*
3240 * There seems to be a race in PCH platform hw (at least on some
3241 * outputs) where an enabled pipe still completes any pageflip right
3242 * away (as if the pipe is off) instead of waiting for vblank. As soon
3243 * as the first vblank happend, everything works as expected. Hence just
3244 * wait for one vblank before returning to avoid strange things
3245 * happening.
3246 */
3247 intel_wait_for_vblank(dev, intel_crtc->pipe);
3248 }
3249
3250 /* IPS only exists on ULT machines and is tied to pipe A. */
3251 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3252 {
3253 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3254 }
3255
3256 static void hsw_enable_ips(struct intel_crtc *crtc)
3257 {
3258 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3259
3260 if (!crtc->config.ips_enabled)
3261 return;
3262
3263 /* We can only enable IPS after we enable a plane and wait for a vblank.
3264 * We guarantee that the plane is enabled by calling intel_enable_ips
3265 * only after intel_enable_plane. And intel_enable_plane already waits
3266 * for a vblank, so all we need to do here is to enable the IPS bit. */
3267 assert_plane_enabled(dev_priv, crtc->plane);
3268 I915_WRITE(IPS_CTL, IPS_ENABLE);
3269 }
3270
3271 static void hsw_disable_ips(struct intel_crtc *crtc)
3272 {
3273 struct drm_device *dev = crtc->base.dev;
3274 struct drm_i915_private *dev_priv = dev->dev_private;
3275
3276 if (!crtc->config.ips_enabled)
3277 return;
3278
3279 assert_plane_enabled(dev_priv, crtc->plane);
3280 I915_WRITE(IPS_CTL, 0);
3281
3282 /* We need to wait for a vblank before we can disable the plane. */
3283 intel_wait_for_vblank(dev, crtc->pipe);
3284 }
3285
3286 static void haswell_crtc_enable(struct drm_crtc *crtc)
3287 {
3288 struct drm_device *dev = crtc->dev;
3289 struct drm_i915_private *dev_priv = dev->dev_private;
3290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3291 struct intel_encoder *encoder;
3292 int pipe = intel_crtc->pipe;
3293 int plane = intel_crtc->plane;
3294
3295 WARN_ON(!crtc->enabled);
3296
3297 if (intel_crtc->active)
3298 return;
3299
3300 intel_crtc->active = true;
3301
3302 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3303 if (intel_crtc->config.has_pch_encoder)
3304 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3305
3306 intel_update_watermarks(dev);
3307
3308 if (intel_crtc->config.has_pch_encoder)
3309 dev_priv->display.fdi_link_train(crtc);
3310
3311 for_each_encoder_on_crtc(dev, crtc, encoder)
3312 if (encoder->pre_enable)
3313 encoder->pre_enable(encoder);
3314
3315 intel_ddi_enable_pipe_clock(intel_crtc);
3316
3317 ironlake_pfit_enable(intel_crtc);
3318
3319 /*
3320 * On ILK+ LUT must be loaded before the pipe is running but with
3321 * clocks enabled
3322 */
3323 intel_crtc_load_lut(crtc);
3324
3325 intel_ddi_set_pipe_settings(crtc);
3326 intel_ddi_enable_transcoder_func(crtc);
3327
3328 intel_enable_pipe(dev_priv, pipe,
3329 intel_crtc->config.has_pch_encoder);
3330 intel_enable_plane(dev_priv, plane, pipe);
3331 intel_enable_planes(crtc);
3332 intel_crtc_update_cursor(crtc, true);
3333
3334 hsw_enable_ips(intel_crtc);
3335
3336 if (intel_crtc->config.has_pch_encoder)
3337 lpt_pch_enable(crtc);
3338
3339 mutex_lock(&dev->struct_mutex);
3340 intel_update_fbc(dev);
3341 mutex_unlock(&dev->struct_mutex);
3342
3343 for_each_encoder_on_crtc(dev, crtc, encoder)
3344 encoder->enable(encoder);
3345
3346 /*
3347 * There seems to be a race in PCH platform hw (at least on some
3348 * outputs) where an enabled pipe still completes any pageflip right
3349 * away (as if the pipe is off) instead of waiting for vblank. As soon
3350 * as the first vblank happend, everything works as expected. Hence just
3351 * wait for one vblank before returning to avoid strange things
3352 * happening.
3353 */
3354 intel_wait_for_vblank(dev, intel_crtc->pipe);
3355 }
3356
3357 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3358 {
3359 struct drm_device *dev = crtc->base.dev;
3360 struct drm_i915_private *dev_priv = dev->dev_private;
3361 int pipe = crtc->pipe;
3362
3363 /* To avoid upsetting the power well on haswell only disable the pfit if
3364 * it's in use. The hw state code will make sure we get this right. */
3365 if (crtc->config.pch_pfit.size) {
3366 I915_WRITE(PF_CTL(pipe), 0);
3367 I915_WRITE(PF_WIN_POS(pipe), 0);
3368 I915_WRITE(PF_WIN_SZ(pipe), 0);
3369 }
3370 }
3371
3372 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3373 {
3374 struct drm_device *dev = crtc->dev;
3375 struct drm_i915_private *dev_priv = dev->dev_private;
3376 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3377 struct intel_encoder *encoder;
3378 int pipe = intel_crtc->pipe;
3379 int plane = intel_crtc->plane;
3380 u32 reg, temp;
3381
3382
3383 if (!intel_crtc->active)
3384 return;
3385
3386 for_each_encoder_on_crtc(dev, crtc, encoder)
3387 encoder->disable(encoder);
3388
3389 intel_crtc_wait_for_pending_flips(crtc);
3390 drm_vblank_off(dev, pipe);
3391
3392 if (dev_priv->cfb_plane == plane)
3393 intel_disable_fbc(dev);
3394
3395 intel_crtc_update_cursor(crtc, false);
3396 intel_disable_planes(crtc);
3397 intel_disable_plane(dev_priv, plane, pipe);
3398
3399 if (intel_crtc->config.has_pch_encoder)
3400 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3401
3402 intel_disable_pipe(dev_priv, pipe);
3403
3404 ironlake_pfit_disable(intel_crtc);
3405
3406 for_each_encoder_on_crtc(dev, crtc, encoder)
3407 if (encoder->post_disable)
3408 encoder->post_disable(encoder);
3409
3410 if (intel_crtc->config.has_pch_encoder) {
3411 ironlake_fdi_disable(crtc);
3412
3413 ironlake_disable_pch_transcoder(dev_priv, pipe);
3414 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3415
3416 if (HAS_PCH_CPT(dev)) {
3417 /* disable TRANS_DP_CTL */
3418 reg = TRANS_DP_CTL(pipe);
3419 temp = I915_READ(reg);
3420 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3421 TRANS_DP_PORT_SEL_MASK);
3422 temp |= TRANS_DP_PORT_SEL_NONE;
3423 I915_WRITE(reg, temp);
3424
3425 /* disable DPLL_SEL */
3426 temp = I915_READ(PCH_DPLL_SEL);
3427 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3428 I915_WRITE(PCH_DPLL_SEL, temp);
3429 }
3430
3431 /* disable PCH DPLL */
3432 intel_disable_shared_dpll(intel_crtc);
3433
3434 ironlake_fdi_pll_disable(intel_crtc);
3435 }
3436
3437 intel_crtc->active = false;
3438 intel_update_watermarks(dev);
3439
3440 mutex_lock(&dev->struct_mutex);
3441 intel_update_fbc(dev);
3442 mutex_unlock(&dev->struct_mutex);
3443 }
3444
3445 static void haswell_crtc_disable(struct drm_crtc *crtc)
3446 {
3447 struct drm_device *dev = crtc->dev;
3448 struct drm_i915_private *dev_priv = dev->dev_private;
3449 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3450 struct intel_encoder *encoder;
3451 int pipe = intel_crtc->pipe;
3452 int plane = intel_crtc->plane;
3453 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3454
3455 if (!intel_crtc->active)
3456 return;
3457
3458 for_each_encoder_on_crtc(dev, crtc, encoder)
3459 encoder->disable(encoder);
3460
3461 intel_crtc_wait_for_pending_flips(crtc);
3462 drm_vblank_off(dev, pipe);
3463
3464 /* FBC must be disabled before disabling the plane on HSW. */
3465 if (dev_priv->cfb_plane == plane)
3466 intel_disable_fbc(dev);
3467
3468 hsw_disable_ips(intel_crtc);
3469
3470 intel_crtc_update_cursor(crtc, false);
3471 intel_disable_planes(crtc);
3472 intel_disable_plane(dev_priv, plane, pipe);
3473
3474 if (intel_crtc->config.has_pch_encoder)
3475 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3476 intel_disable_pipe(dev_priv, pipe);
3477
3478 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3479
3480 ironlake_pfit_disable(intel_crtc);
3481
3482 intel_ddi_disable_pipe_clock(intel_crtc);
3483
3484 for_each_encoder_on_crtc(dev, crtc, encoder)
3485 if (encoder->post_disable)
3486 encoder->post_disable(encoder);
3487
3488 if (intel_crtc->config.has_pch_encoder) {
3489 lpt_disable_pch_transcoder(dev_priv);
3490 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3491 intel_ddi_fdi_disable(crtc);
3492 }
3493
3494 intel_crtc->active = false;
3495 intel_update_watermarks(dev);
3496
3497 mutex_lock(&dev->struct_mutex);
3498 intel_update_fbc(dev);
3499 mutex_unlock(&dev->struct_mutex);
3500 }
3501
3502 static void ironlake_crtc_off(struct drm_crtc *crtc)
3503 {
3504 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3505 intel_put_shared_dpll(intel_crtc);
3506 }
3507
3508 static void haswell_crtc_off(struct drm_crtc *crtc)
3509 {
3510 intel_ddi_put_crtc_pll(crtc);
3511 }
3512
3513 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3514 {
3515 if (!enable && intel_crtc->overlay) {
3516 struct drm_device *dev = intel_crtc->base.dev;
3517 struct drm_i915_private *dev_priv = dev->dev_private;
3518
3519 mutex_lock(&dev->struct_mutex);
3520 dev_priv->mm.interruptible = false;
3521 (void) intel_overlay_switch_off(intel_crtc->overlay);
3522 dev_priv->mm.interruptible = true;
3523 mutex_unlock(&dev->struct_mutex);
3524 }
3525
3526 /* Let userspace switch the overlay on again. In most cases userspace
3527 * has to recompute where to put it anyway.
3528 */
3529 }
3530
3531 /**
3532 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3533 * cursor plane briefly if not already running after enabling the display
3534 * plane.
3535 * This workaround avoids occasional blank screens when self refresh is
3536 * enabled.
3537 */
3538 static void
3539 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3540 {
3541 u32 cntl = I915_READ(CURCNTR(pipe));
3542
3543 if ((cntl & CURSOR_MODE) == 0) {
3544 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3545
3546 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3547 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3548 intel_wait_for_vblank(dev_priv->dev, pipe);
3549 I915_WRITE(CURCNTR(pipe), cntl);
3550 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3551 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3552 }
3553 }
3554
3555 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3556 {
3557 struct drm_device *dev = crtc->base.dev;
3558 struct drm_i915_private *dev_priv = dev->dev_private;
3559 struct intel_crtc_config *pipe_config = &crtc->config;
3560
3561 if (!crtc->config.gmch_pfit.control)
3562 return;
3563
3564 /*
3565 * The panel fitter should only be adjusted whilst the pipe is disabled,
3566 * according to register description and PRM.
3567 */
3568 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3569 assert_pipe_disabled(dev_priv, crtc->pipe);
3570
3571 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3572 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3573
3574 /* Border color in case we don't scale up to the full screen. Black by
3575 * default, change to something else for debugging. */
3576 I915_WRITE(BCLRPAT(crtc->pipe), 0);
3577 }
3578
3579 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3580 {
3581 struct drm_device *dev = crtc->dev;
3582 struct drm_i915_private *dev_priv = dev->dev_private;
3583 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3584 struct intel_encoder *encoder;
3585 int pipe = intel_crtc->pipe;
3586 int plane = intel_crtc->plane;
3587
3588 WARN_ON(!crtc->enabled);
3589
3590 if (intel_crtc->active)
3591 return;
3592
3593 intel_crtc->active = true;
3594 intel_update_watermarks(dev);
3595
3596 mutex_lock(&dev_priv->dpio_lock);
3597
3598 for_each_encoder_on_crtc(dev, crtc, encoder)
3599 if (encoder->pre_pll_enable)
3600 encoder->pre_pll_enable(encoder);
3601
3602 intel_enable_pll(dev_priv, pipe);
3603
3604 for_each_encoder_on_crtc(dev, crtc, encoder)
3605 if (encoder->pre_enable)
3606 encoder->pre_enable(encoder);
3607
3608 /* VLV wants encoder enabling _before_ the pipe is up. */
3609 for_each_encoder_on_crtc(dev, crtc, encoder)
3610 encoder->enable(encoder);
3611
3612 i9xx_pfit_enable(intel_crtc);
3613
3614 intel_crtc_load_lut(crtc);
3615
3616 intel_enable_pipe(dev_priv, pipe, false);
3617 intel_enable_plane(dev_priv, plane, pipe);
3618 intel_enable_planes(crtc);
3619 intel_crtc_update_cursor(crtc, true);
3620
3621 intel_update_fbc(dev);
3622
3623 mutex_unlock(&dev_priv->dpio_lock);
3624 }
3625
3626 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3627 {
3628 struct drm_device *dev = crtc->dev;
3629 struct drm_i915_private *dev_priv = dev->dev_private;
3630 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3631 struct intel_encoder *encoder;
3632 int pipe = intel_crtc->pipe;
3633 int plane = intel_crtc->plane;
3634
3635 WARN_ON(!crtc->enabled);
3636
3637 if (intel_crtc->active)
3638 return;
3639
3640 intel_crtc->active = true;
3641 intel_update_watermarks(dev);
3642
3643 intel_enable_pll(dev_priv, pipe);
3644
3645 for_each_encoder_on_crtc(dev, crtc, encoder)
3646 if (encoder->pre_enable)
3647 encoder->pre_enable(encoder);
3648
3649 i9xx_pfit_enable(intel_crtc);
3650
3651 intel_crtc_load_lut(crtc);
3652
3653 intel_enable_pipe(dev_priv, pipe, false);
3654 intel_enable_plane(dev_priv, plane, pipe);
3655 intel_enable_planes(crtc);
3656 /* The fixup needs to happen before cursor is enabled */
3657 if (IS_G4X(dev))
3658 g4x_fixup_plane(dev_priv, pipe);
3659 intel_crtc_update_cursor(crtc, true);
3660
3661 /* Give the overlay scaler a chance to enable if it's on this pipe */
3662 intel_crtc_dpms_overlay(intel_crtc, true);
3663
3664 intel_update_fbc(dev);
3665
3666 for_each_encoder_on_crtc(dev, crtc, encoder)
3667 encoder->enable(encoder);
3668 }
3669
3670 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3671 {
3672 struct drm_device *dev = crtc->base.dev;
3673 struct drm_i915_private *dev_priv = dev->dev_private;
3674
3675 if (!crtc->config.gmch_pfit.control)
3676 return;
3677
3678 assert_pipe_disabled(dev_priv, crtc->pipe);
3679
3680 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3681 I915_READ(PFIT_CONTROL));
3682 I915_WRITE(PFIT_CONTROL, 0);
3683 }
3684
3685 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3686 {
3687 struct drm_device *dev = crtc->dev;
3688 struct drm_i915_private *dev_priv = dev->dev_private;
3689 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3690 struct intel_encoder *encoder;
3691 int pipe = intel_crtc->pipe;
3692 int plane = intel_crtc->plane;
3693
3694 if (!intel_crtc->active)
3695 return;
3696
3697 for_each_encoder_on_crtc(dev, crtc, encoder)
3698 encoder->disable(encoder);
3699
3700 /* Give the overlay scaler a chance to disable if it's on this pipe */
3701 intel_crtc_wait_for_pending_flips(crtc);
3702 drm_vblank_off(dev, pipe);
3703
3704 if (dev_priv->cfb_plane == plane)
3705 intel_disable_fbc(dev);
3706
3707 intel_crtc_dpms_overlay(intel_crtc, false);
3708 intel_crtc_update_cursor(crtc, false);
3709 intel_disable_planes(crtc);
3710 intel_disable_plane(dev_priv, plane, pipe);
3711
3712 intel_disable_pipe(dev_priv, pipe);
3713
3714 i9xx_pfit_disable(intel_crtc);
3715
3716 for_each_encoder_on_crtc(dev, crtc, encoder)
3717 if (encoder->post_disable)
3718 encoder->post_disable(encoder);
3719
3720 intel_disable_pll(dev_priv, pipe);
3721
3722 intel_crtc->active = false;
3723 intel_update_fbc(dev);
3724 intel_update_watermarks(dev);
3725 }
3726
3727 static void i9xx_crtc_off(struct drm_crtc *crtc)
3728 {
3729 }
3730
3731 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3732 bool enabled)
3733 {
3734 struct drm_device *dev = crtc->dev;
3735 struct drm_i915_master_private *master_priv;
3736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3737 int pipe = intel_crtc->pipe;
3738
3739 if (!dev->primary->master)
3740 return;
3741
3742 master_priv = dev->primary->master->driver_priv;
3743 if (!master_priv->sarea_priv)
3744 return;
3745
3746 switch (pipe) {
3747 case 0:
3748 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3749 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3750 break;
3751 case 1:
3752 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3753 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3754 break;
3755 default:
3756 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3757 break;
3758 }
3759 }
3760
3761 /**
3762 * Sets the power management mode of the pipe and plane.
3763 */
3764 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3765 {
3766 struct drm_device *dev = crtc->dev;
3767 struct drm_i915_private *dev_priv = dev->dev_private;
3768 struct intel_encoder *intel_encoder;
3769 bool enable = false;
3770
3771 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3772 enable |= intel_encoder->connectors_active;
3773
3774 if (enable)
3775 dev_priv->display.crtc_enable(crtc);
3776 else
3777 dev_priv->display.crtc_disable(crtc);
3778
3779 intel_crtc_update_sarea(crtc, enable);
3780 }
3781
3782 static void intel_crtc_disable(struct drm_crtc *crtc)
3783 {
3784 struct drm_device *dev = crtc->dev;
3785 struct drm_connector *connector;
3786 struct drm_i915_private *dev_priv = dev->dev_private;
3787 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3788
3789 /* crtc should still be enabled when we disable it. */
3790 WARN_ON(!crtc->enabled);
3791
3792 dev_priv->display.crtc_disable(crtc);
3793 intel_crtc->eld_vld = false;
3794 intel_crtc_update_sarea(crtc, false);
3795 dev_priv->display.off(crtc);
3796
3797 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3798 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3799
3800 if (crtc->fb) {
3801 mutex_lock(&dev->struct_mutex);
3802 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3803 mutex_unlock(&dev->struct_mutex);
3804 crtc->fb = NULL;
3805 }
3806
3807 /* Update computed state. */
3808 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3809 if (!connector->encoder || !connector->encoder->crtc)
3810 continue;
3811
3812 if (connector->encoder->crtc != crtc)
3813 continue;
3814
3815 connector->dpms = DRM_MODE_DPMS_OFF;
3816 to_intel_encoder(connector->encoder)->connectors_active = false;
3817 }
3818 }
3819
3820 void intel_modeset_disable(struct drm_device *dev)
3821 {
3822 struct drm_crtc *crtc;
3823
3824 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3825 if (crtc->enabled)
3826 intel_crtc_disable(crtc);
3827 }
3828 }
3829
3830 void intel_encoder_destroy(struct drm_encoder *encoder)
3831 {
3832 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3833
3834 drm_encoder_cleanup(encoder);
3835 kfree(intel_encoder);
3836 }
3837
3838 /* Simple dpms helper for encodres with just one connector, no cloning and only
3839 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3840 * state of the entire output pipe. */
3841 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3842 {
3843 if (mode == DRM_MODE_DPMS_ON) {
3844 encoder->connectors_active = true;
3845
3846 intel_crtc_update_dpms(encoder->base.crtc);
3847 } else {
3848 encoder->connectors_active = false;
3849
3850 intel_crtc_update_dpms(encoder->base.crtc);
3851 }
3852 }
3853
3854 /* Cross check the actual hw state with our own modeset state tracking (and it's
3855 * internal consistency). */
3856 static void intel_connector_check_state(struct intel_connector *connector)
3857 {
3858 if (connector->get_hw_state(connector)) {
3859 struct intel_encoder *encoder = connector->encoder;
3860 struct drm_crtc *crtc;
3861 bool encoder_enabled;
3862 enum pipe pipe;
3863
3864 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3865 connector->base.base.id,
3866 drm_get_connector_name(&connector->base));
3867
3868 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3869 "wrong connector dpms state\n");
3870 WARN(connector->base.encoder != &encoder->base,
3871 "active connector not linked to encoder\n");
3872 WARN(!encoder->connectors_active,
3873 "encoder->connectors_active not set\n");
3874
3875 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3876 WARN(!encoder_enabled, "encoder not enabled\n");
3877 if (WARN_ON(!encoder->base.crtc))
3878 return;
3879
3880 crtc = encoder->base.crtc;
3881
3882 WARN(!crtc->enabled, "crtc not enabled\n");
3883 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3884 WARN(pipe != to_intel_crtc(crtc)->pipe,
3885 "encoder active on the wrong pipe\n");
3886 }
3887 }
3888
3889 /* Even simpler default implementation, if there's really no special case to
3890 * consider. */
3891 void intel_connector_dpms(struct drm_connector *connector, int mode)
3892 {
3893 struct intel_encoder *encoder = intel_attached_encoder(connector);
3894
3895 /* All the simple cases only support two dpms states. */
3896 if (mode != DRM_MODE_DPMS_ON)
3897 mode = DRM_MODE_DPMS_OFF;
3898
3899 if (mode == connector->dpms)
3900 return;
3901
3902 connector->dpms = mode;
3903
3904 /* Only need to change hw state when actually enabled */
3905 if (encoder->base.crtc)
3906 intel_encoder_dpms(encoder, mode);
3907 else
3908 WARN_ON(encoder->connectors_active != false);
3909
3910 intel_modeset_check_state(connector->dev);
3911 }
3912
3913 /* Simple connector->get_hw_state implementation for encoders that support only
3914 * one connector and no cloning and hence the encoder state determines the state
3915 * of the connector. */
3916 bool intel_connector_get_hw_state(struct intel_connector *connector)
3917 {
3918 enum pipe pipe = 0;
3919 struct intel_encoder *encoder = connector->encoder;
3920
3921 return encoder->get_hw_state(encoder, &pipe);
3922 }
3923
3924 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3925 struct intel_crtc_config *pipe_config)
3926 {
3927 struct drm_i915_private *dev_priv = dev->dev_private;
3928 struct intel_crtc *pipe_B_crtc =
3929 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3930
3931 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3932 pipe_name(pipe), pipe_config->fdi_lanes);
3933 if (pipe_config->fdi_lanes > 4) {
3934 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3935 pipe_name(pipe), pipe_config->fdi_lanes);
3936 return false;
3937 }
3938
3939 if (IS_HASWELL(dev)) {
3940 if (pipe_config->fdi_lanes > 2) {
3941 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3942 pipe_config->fdi_lanes);
3943 return false;
3944 } else {
3945 return true;
3946 }
3947 }
3948
3949 if (INTEL_INFO(dev)->num_pipes == 2)
3950 return true;
3951
3952 /* Ivybridge 3 pipe is really complicated */
3953 switch (pipe) {
3954 case PIPE_A:
3955 return true;
3956 case PIPE_B:
3957 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
3958 pipe_config->fdi_lanes > 2) {
3959 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3960 pipe_name(pipe), pipe_config->fdi_lanes);
3961 return false;
3962 }
3963 return true;
3964 case PIPE_C:
3965 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
3966 pipe_B_crtc->config.fdi_lanes <= 2) {
3967 if (pipe_config->fdi_lanes > 2) {
3968 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3969 pipe_name(pipe), pipe_config->fdi_lanes);
3970 return false;
3971 }
3972 } else {
3973 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
3974 return false;
3975 }
3976 return true;
3977 default:
3978 BUG();
3979 }
3980 }
3981
3982 #define RETRY 1
3983 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
3984 struct intel_crtc_config *pipe_config)
3985 {
3986 struct drm_device *dev = intel_crtc->base.dev;
3987 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
3988 int lane, link_bw, fdi_dotclock;
3989 bool setup_ok, needs_recompute = false;
3990
3991 retry:
3992 /* FDI is a binary signal running at ~2.7GHz, encoding
3993 * each output octet as 10 bits. The actual frequency
3994 * is stored as a divider into a 100MHz clock, and the
3995 * mode pixel clock is stored in units of 1KHz.
3996 * Hence the bw of each lane in terms of the mode signal
3997 * is:
3998 */
3999 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4000
4001 fdi_dotclock = adjusted_mode->clock;
4002 fdi_dotclock /= pipe_config->pixel_multiplier;
4003
4004 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4005 pipe_config->pipe_bpp);
4006
4007 pipe_config->fdi_lanes = lane;
4008
4009 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4010 link_bw, &pipe_config->fdi_m_n);
4011
4012 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4013 intel_crtc->pipe, pipe_config);
4014 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4015 pipe_config->pipe_bpp -= 2*3;
4016 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4017 pipe_config->pipe_bpp);
4018 needs_recompute = true;
4019 pipe_config->bw_constrained = true;
4020
4021 goto retry;
4022 }
4023
4024 if (needs_recompute)
4025 return RETRY;
4026
4027 return setup_ok ? 0 : -EINVAL;
4028 }
4029
4030 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4031 struct intel_crtc_config *pipe_config)
4032 {
4033 pipe_config->ips_enabled = i915_enable_ips &&
4034 hsw_crtc_supports_ips(crtc) &&
4035 pipe_config->pipe_bpp == 24;
4036 }
4037
4038 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4039 struct intel_crtc_config *pipe_config)
4040 {
4041 struct drm_device *dev = crtc->base.dev;
4042 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4043
4044 if (HAS_PCH_SPLIT(dev)) {
4045 /* FDI link clock is fixed at 2.7G */
4046 if (pipe_config->requested_mode.clock * 3
4047 > IRONLAKE_FDI_FREQ * 4)
4048 return -EINVAL;
4049 }
4050
4051 /* All interlaced capable intel hw wants timings in frames. Note though
4052 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4053 * timings, so we need to be careful not to clobber these.*/
4054 if (!pipe_config->timings_set)
4055 drm_mode_set_crtcinfo(adjusted_mode, 0);
4056
4057 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4058 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4059 */
4060 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4061 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4062 return -EINVAL;
4063
4064 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4065 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4066 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4067 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4068 * for lvds. */
4069 pipe_config->pipe_bpp = 8*3;
4070 }
4071
4072 if (HAS_IPS(dev))
4073 hsw_compute_ips_config(crtc, pipe_config);
4074
4075 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4076 * clock survives for now. */
4077 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4078 pipe_config->shared_dpll = crtc->config.shared_dpll;
4079
4080 if (pipe_config->has_pch_encoder)
4081 return ironlake_fdi_compute_config(crtc, pipe_config);
4082
4083 return 0;
4084 }
4085
4086 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4087 {
4088 return 400000; /* FIXME */
4089 }
4090
4091 static int i945_get_display_clock_speed(struct drm_device *dev)
4092 {
4093 return 400000;
4094 }
4095
4096 static int i915_get_display_clock_speed(struct drm_device *dev)
4097 {
4098 return 333000;
4099 }
4100
4101 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4102 {
4103 return 200000;
4104 }
4105
4106 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4107 {
4108 u16 gcfgc = 0;
4109
4110 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4111
4112 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4113 return 133000;
4114 else {
4115 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4116 case GC_DISPLAY_CLOCK_333_MHZ:
4117 return 333000;
4118 default:
4119 case GC_DISPLAY_CLOCK_190_200_MHZ:
4120 return 190000;
4121 }
4122 }
4123 }
4124
4125 static int i865_get_display_clock_speed(struct drm_device *dev)
4126 {
4127 return 266000;
4128 }
4129
4130 static int i855_get_display_clock_speed(struct drm_device *dev)
4131 {
4132 u16 hpllcc = 0;
4133 /* Assume that the hardware is in the high speed state. This
4134 * should be the default.
4135 */
4136 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4137 case GC_CLOCK_133_200:
4138 case GC_CLOCK_100_200:
4139 return 200000;
4140 case GC_CLOCK_166_250:
4141 return 250000;
4142 case GC_CLOCK_100_133:
4143 return 133000;
4144 }
4145
4146 /* Shouldn't happen */
4147 return 0;
4148 }
4149
4150 static int i830_get_display_clock_speed(struct drm_device *dev)
4151 {
4152 return 133000;
4153 }
4154
4155 static void
4156 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4157 {
4158 while (*num > DATA_LINK_M_N_MASK ||
4159 *den > DATA_LINK_M_N_MASK) {
4160 *num >>= 1;
4161 *den >>= 1;
4162 }
4163 }
4164
4165 static void compute_m_n(unsigned int m, unsigned int n,
4166 uint32_t *ret_m, uint32_t *ret_n)
4167 {
4168 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4169 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4170 intel_reduce_m_n_ratio(ret_m, ret_n);
4171 }
4172
4173 void
4174 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4175 int pixel_clock, int link_clock,
4176 struct intel_link_m_n *m_n)
4177 {
4178 m_n->tu = 64;
4179
4180 compute_m_n(bits_per_pixel * pixel_clock,
4181 link_clock * nlanes * 8,
4182 &m_n->gmch_m, &m_n->gmch_n);
4183
4184 compute_m_n(pixel_clock, link_clock,
4185 &m_n->link_m, &m_n->link_n);
4186 }
4187
4188 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4189 {
4190 if (i915_panel_use_ssc >= 0)
4191 return i915_panel_use_ssc != 0;
4192 return dev_priv->vbt.lvds_use_ssc
4193 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4194 }
4195
4196 static int vlv_get_refclk(struct drm_crtc *crtc)
4197 {
4198 struct drm_device *dev = crtc->dev;
4199 struct drm_i915_private *dev_priv = dev->dev_private;
4200 int refclk = 27000; /* for DP & HDMI */
4201
4202 return 100000; /* only one validated so far */
4203
4204 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4205 refclk = 96000;
4206 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4207 if (intel_panel_use_ssc(dev_priv))
4208 refclk = 100000;
4209 else
4210 refclk = 96000;
4211 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4212 refclk = 100000;
4213 }
4214
4215 return refclk;
4216 }
4217
4218 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4219 {
4220 struct drm_device *dev = crtc->dev;
4221 struct drm_i915_private *dev_priv = dev->dev_private;
4222 int refclk;
4223
4224 if (IS_VALLEYVIEW(dev)) {
4225 refclk = vlv_get_refclk(crtc);
4226 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4227 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4228 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4229 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4230 refclk / 1000);
4231 } else if (!IS_GEN2(dev)) {
4232 refclk = 96000;
4233 } else {
4234 refclk = 48000;
4235 }
4236
4237 return refclk;
4238 }
4239
4240 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4241 {
4242 return (1 << dpll->n) << 16 | dpll->m2;
4243 }
4244
4245 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4246 {
4247 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4248 }
4249
4250 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4251 intel_clock_t *reduced_clock)
4252 {
4253 struct drm_device *dev = crtc->base.dev;
4254 struct drm_i915_private *dev_priv = dev->dev_private;
4255 int pipe = crtc->pipe;
4256 u32 fp, fp2 = 0;
4257
4258 if (IS_PINEVIEW(dev)) {
4259 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4260 if (reduced_clock)
4261 fp2 = pnv_dpll_compute_fp(reduced_clock);
4262 } else {
4263 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4264 if (reduced_clock)
4265 fp2 = i9xx_dpll_compute_fp(reduced_clock);
4266 }
4267
4268 I915_WRITE(FP0(pipe), fp);
4269
4270 crtc->lowfreq_avail = false;
4271 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4272 reduced_clock && i915_powersave) {
4273 I915_WRITE(FP1(pipe), fp2);
4274 crtc->lowfreq_avail = true;
4275 } else {
4276 I915_WRITE(FP1(pipe), fp);
4277 }
4278 }
4279
4280 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4281 {
4282 u32 reg_val;
4283
4284 /*
4285 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4286 * and set it to a reasonable value instead.
4287 */
4288 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4289 reg_val &= 0xffffff00;
4290 reg_val |= 0x00000030;
4291 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4292
4293 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4294 reg_val &= 0x8cffffff;
4295 reg_val = 0x8c000000;
4296 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4297
4298 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4299 reg_val &= 0xffffff00;
4300 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4301
4302 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4303 reg_val &= 0x00ffffff;
4304 reg_val |= 0xb0000000;
4305 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4306 }
4307
4308 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4309 struct intel_link_m_n *m_n)
4310 {
4311 struct drm_device *dev = crtc->base.dev;
4312 struct drm_i915_private *dev_priv = dev->dev_private;
4313 int pipe = crtc->pipe;
4314
4315 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4316 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4317 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4318 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4319 }
4320
4321 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4322 struct intel_link_m_n *m_n)
4323 {
4324 struct drm_device *dev = crtc->base.dev;
4325 struct drm_i915_private *dev_priv = dev->dev_private;
4326 int pipe = crtc->pipe;
4327 enum transcoder transcoder = crtc->config.cpu_transcoder;
4328
4329 if (INTEL_INFO(dev)->gen >= 5) {
4330 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4331 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4332 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4333 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4334 } else {
4335 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4336 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4337 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4338 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4339 }
4340 }
4341
4342 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4343 {
4344 if (crtc->config.has_pch_encoder)
4345 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4346 else
4347 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4348 }
4349
4350 static void vlv_update_pll(struct intel_crtc *crtc)
4351 {
4352 struct drm_device *dev = crtc->base.dev;
4353 struct drm_i915_private *dev_priv = dev->dev_private;
4354 struct intel_encoder *encoder;
4355 int pipe = crtc->pipe;
4356 u32 dpll, mdiv;
4357 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4358 bool is_hdmi;
4359 u32 coreclk, reg_val, dpll_md;
4360
4361 mutex_lock(&dev_priv->dpio_lock);
4362
4363 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4364
4365 bestn = crtc->config.dpll.n;
4366 bestm1 = crtc->config.dpll.m1;
4367 bestm2 = crtc->config.dpll.m2;
4368 bestp1 = crtc->config.dpll.p1;
4369 bestp2 = crtc->config.dpll.p2;
4370
4371 /* See eDP HDMI DPIO driver vbios notes doc */
4372
4373 /* PLL B needs special handling */
4374 if (pipe)
4375 vlv_pllb_recal_opamp(dev_priv);
4376
4377 /* Set up Tx target for periodic Rcomp update */
4378 vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4379
4380 /* Disable target IRef on PLL */
4381 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4382 reg_val &= 0x00ffffff;
4383 vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4384
4385 /* Disable fast lock */
4386 vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4387
4388 /* Set idtafcrecal before PLL is enabled */
4389 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4390 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4391 mdiv |= ((bestn << DPIO_N_SHIFT));
4392 mdiv |= (1 << DPIO_K_SHIFT);
4393
4394 /*
4395 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4396 * but we don't support that).
4397 * Note: don't use the DAC post divider as it seems unstable.
4398 */
4399 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4400 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4401
4402 mdiv |= DPIO_ENABLE_CALIBRATION;
4403 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4404
4405 /* Set HBR and RBR LPF coefficients */
4406 if (crtc->config.port_clock == 162000 ||
4407 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4408 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4409 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
4410 0x005f0021);
4411 else
4412 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
4413 0x00d0000f);
4414
4415 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4416 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4417 /* Use SSC source */
4418 if (!pipe)
4419 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4420 0x0df40000);
4421 else
4422 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4423 0x0df70000);
4424 } else { /* HDMI or VGA */
4425 /* Use bend source */
4426 if (!pipe)
4427 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4428 0x0df70000);
4429 else
4430 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4431 0x0df40000);
4432 }
4433
4434 coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4435 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4436 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4437 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4438 coreclk |= 0x01000000;
4439 vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
4440
4441 vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
4442
4443 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4444 if (encoder->pre_pll_enable)
4445 encoder->pre_pll_enable(encoder);
4446
4447 /* Enable DPIO clock input */
4448 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4449 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4450 if (pipe)
4451 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4452
4453 dpll |= DPLL_VCO_ENABLE;
4454 I915_WRITE(DPLL(pipe), dpll);
4455 POSTING_READ(DPLL(pipe));
4456 udelay(150);
4457
4458 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4459 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4460
4461 dpll_md = (crtc->config.pixel_multiplier - 1)
4462 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4463 I915_WRITE(DPLL_MD(pipe), dpll_md);
4464 POSTING_READ(DPLL_MD(pipe));
4465
4466 if (crtc->config.has_dp_encoder)
4467 intel_dp_set_m_n(crtc);
4468
4469 mutex_unlock(&dev_priv->dpio_lock);
4470 }
4471
4472 static void i9xx_update_pll(struct intel_crtc *crtc,
4473 intel_clock_t *reduced_clock,
4474 int num_connectors)
4475 {
4476 struct drm_device *dev = crtc->base.dev;
4477 struct drm_i915_private *dev_priv = dev->dev_private;
4478 struct intel_encoder *encoder;
4479 int pipe = crtc->pipe;
4480 u32 dpll;
4481 bool is_sdvo;
4482 struct dpll *clock = &crtc->config.dpll;
4483
4484 i9xx_update_pll_dividers(crtc, reduced_clock);
4485
4486 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4487 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4488
4489 dpll = DPLL_VGA_MODE_DIS;
4490
4491 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4492 dpll |= DPLLB_MODE_LVDS;
4493 else
4494 dpll |= DPLLB_MODE_DAC_SERIAL;
4495
4496 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4497 dpll |= (crtc->config.pixel_multiplier - 1)
4498 << SDVO_MULTIPLIER_SHIFT_HIRES;
4499 }
4500
4501 if (is_sdvo)
4502 dpll |= DPLL_DVO_HIGH_SPEED;
4503
4504 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4505 dpll |= DPLL_DVO_HIGH_SPEED;
4506
4507 /* compute bitmask from p1 value */
4508 if (IS_PINEVIEW(dev))
4509 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4510 else {
4511 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4512 if (IS_G4X(dev) && reduced_clock)
4513 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4514 }
4515 switch (clock->p2) {
4516 case 5:
4517 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4518 break;
4519 case 7:
4520 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4521 break;
4522 case 10:
4523 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4524 break;
4525 case 14:
4526 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4527 break;
4528 }
4529 if (INTEL_INFO(dev)->gen >= 4)
4530 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4531
4532 if (crtc->config.sdvo_tv_clock)
4533 dpll |= PLL_REF_INPUT_TVCLKINBC;
4534 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4535 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4536 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4537 else
4538 dpll |= PLL_REF_INPUT_DREFCLK;
4539
4540 dpll |= DPLL_VCO_ENABLE;
4541 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4542 POSTING_READ(DPLL(pipe));
4543 udelay(150);
4544
4545 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4546 if (encoder->pre_pll_enable)
4547 encoder->pre_pll_enable(encoder);
4548
4549 if (crtc->config.has_dp_encoder)
4550 intel_dp_set_m_n(crtc);
4551
4552 I915_WRITE(DPLL(pipe), dpll);
4553
4554 /* Wait for the clocks to stabilize. */
4555 POSTING_READ(DPLL(pipe));
4556 udelay(150);
4557
4558 if (INTEL_INFO(dev)->gen >= 4) {
4559 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4560 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4561 I915_WRITE(DPLL_MD(pipe), dpll_md);
4562 } else {
4563 /* The pixel multiplier can only be updated once the
4564 * DPLL is enabled and the clocks are stable.
4565 *
4566 * So write it again.
4567 */
4568 I915_WRITE(DPLL(pipe), dpll);
4569 }
4570 }
4571
4572 static void i8xx_update_pll(struct intel_crtc *crtc,
4573 intel_clock_t *reduced_clock,
4574 int num_connectors)
4575 {
4576 struct drm_device *dev = crtc->base.dev;
4577 struct drm_i915_private *dev_priv = dev->dev_private;
4578 struct intel_encoder *encoder;
4579 int pipe = crtc->pipe;
4580 u32 dpll;
4581 struct dpll *clock = &crtc->config.dpll;
4582
4583 i9xx_update_pll_dividers(crtc, reduced_clock);
4584
4585 dpll = DPLL_VGA_MODE_DIS;
4586
4587 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4588 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4589 } else {
4590 if (clock->p1 == 2)
4591 dpll |= PLL_P1_DIVIDE_BY_TWO;
4592 else
4593 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4594 if (clock->p2 == 4)
4595 dpll |= PLL_P2_DIVIDE_BY_4;
4596 }
4597
4598 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4599 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4600 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4601 else
4602 dpll |= PLL_REF_INPUT_DREFCLK;
4603
4604 dpll |= DPLL_VCO_ENABLE;
4605 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4606 POSTING_READ(DPLL(pipe));
4607 udelay(150);
4608
4609 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4610 if (encoder->pre_pll_enable)
4611 encoder->pre_pll_enable(encoder);
4612
4613 I915_WRITE(DPLL(pipe), dpll);
4614
4615 /* Wait for the clocks to stabilize. */
4616 POSTING_READ(DPLL(pipe));
4617 udelay(150);
4618
4619 /* The pixel multiplier can only be updated once the
4620 * DPLL is enabled and the clocks are stable.
4621 *
4622 * So write it again.
4623 */
4624 I915_WRITE(DPLL(pipe), dpll);
4625 }
4626
4627 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
4628 {
4629 struct drm_device *dev = intel_crtc->base.dev;
4630 struct drm_i915_private *dev_priv = dev->dev_private;
4631 enum pipe pipe = intel_crtc->pipe;
4632 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4633 struct drm_display_mode *adjusted_mode =
4634 &intel_crtc->config.adjusted_mode;
4635 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4636 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4637
4638 /* We need to be careful not to changed the adjusted mode, for otherwise
4639 * the hw state checker will get angry at the mismatch. */
4640 crtc_vtotal = adjusted_mode->crtc_vtotal;
4641 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4642
4643 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4644 /* the chip adds 2 halflines automatically */
4645 crtc_vtotal -= 1;
4646 crtc_vblank_end -= 1;
4647 vsyncshift = adjusted_mode->crtc_hsync_start
4648 - adjusted_mode->crtc_htotal / 2;
4649 } else {
4650 vsyncshift = 0;
4651 }
4652
4653 if (INTEL_INFO(dev)->gen > 3)
4654 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4655
4656 I915_WRITE(HTOTAL(cpu_transcoder),
4657 (adjusted_mode->crtc_hdisplay - 1) |
4658 ((adjusted_mode->crtc_htotal - 1) << 16));
4659 I915_WRITE(HBLANK(cpu_transcoder),
4660 (adjusted_mode->crtc_hblank_start - 1) |
4661 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4662 I915_WRITE(HSYNC(cpu_transcoder),
4663 (adjusted_mode->crtc_hsync_start - 1) |
4664 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4665
4666 I915_WRITE(VTOTAL(cpu_transcoder),
4667 (adjusted_mode->crtc_vdisplay - 1) |
4668 ((crtc_vtotal - 1) << 16));
4669 I915_WRITE(VBLANK(cpu_transcoder),
4670 (adjusted_mode->crtc_vblank_start - 1) |
4671 ((crtc_vblank_end - 1) << 16));
4672 I915_WRITE(VSYNC(cpu_transcoder),
4673 (adjusted_mode->crtc_vsync_start - 1) |
4674 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4675
4676 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4677 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4678 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4679 * bits. */
4680 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4681 (pipe == PIPE_B || pipe == PIPE_C))
4682 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4683
4684 /* pipesrc controls the size that is scaled from, which should
4685 * always be the user's requested size.
4686 */
4687 I915_WRITE(PIPESRC(pipe),
4688 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4689 }
4690
4691 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4692 struct intel_crtc_config *pipe_config)
4693 {
4694 struct drm_device *dev = crtc->base.dev;
4695 struct drm_i915_private *dev_priv = dev->dev_private;
4696 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4697 uint32_t tmp;
4698
4699 tmp = I915_READ(HTOTAL(cpu_transcoder));
4700 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4701 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4702 tmp = I915_READ(HBLANK(cpu_transcoder));
4703 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4704 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4705 tmp = I915_READ(HSYNC(cpu_transcoder));
4706 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4707 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4708
4709 tmp = I915_READ(VTOTAL(cpu_transcoder));
4710 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4711 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4712 tmp = I915_READ(VBLANK(cpu_transcoder));
4713 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4714 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4715 tmp = I915_READ(VSYNC(cpu_transcoder));
4716 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4717 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4718
4719 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4720 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4721 pipe_config->adjusted_mode.crtc_vtotal += 1;
4722 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4723 }
4724
4725 tmp = I915_READ(PIPESRC(crtc->pipe));
4726 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4727 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4728 }
4729
4730 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4731 {
4732 struct drm_device *dev = intel_crtc->base.dev;
4733 struct drm_i915_private *dev_priv = dev->dev_private;
4734 uint32_t pipeconf;
4735
4736 pipeconf = 0;
4737
4738 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4739 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4740 * core speed.
4741 *
4742 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4743 * pipe == 0 check?
4744 */
4745 if (intel_crtc->config.requested_mode.clock >
4746 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4747 pipeconf |= PIPECONF_DOUBLE_WIDE;
4748 }
4749
4750 /* only g4x and later have fancy bpc/dither controls */
4751 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4752 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4753 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4754 pipeconf |= PIPECONF_DITHER_EN |
4755 PIPECONF_DITHER_TYPE_SP;
4756
4757 switch (intel_crtc->config.pipe_bpp) {
4758 case 18:
4759 pipeconf |= PIPECONF_6BPC;
4760 break;
4761 case 24:
4762 pipeconf |= PIPECONF_8BPC;
4763 break;
4764 case 30:
4765 pipeconf |= PIPECONF_10BPC;
4766 break;
4767 default:
4768 /* Case prevented by intel_choose_pipe_bpp_dither. */
4769 BUG();
4770 }
4771 }
4772
4773 if (HAS_PIPE_CXSR(dev)) {
4774 if (intel_crtc->lowfreq_avail) {
4775 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4776 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4777 } else {
4778 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4779 }
4780 }
4781
4782 if (!IS_GEN2(dev) &&
4783 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4784 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4785 else
4786 pipeconf |= PIPECONF_PROGRESSIVE;
4787
4788 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4789 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4790
4791 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4792 POSTING_READ(PIPECONF(intel_crtc->pipe));
4793 }
4794
4795 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4796 int x, int y,
4797 struct drm_framebuffer *fb)
4798 {
4799 struct drm_device *dev = crtc->dev;
4800 struct drm_i915_private *dev_priv = dev->dev_private;
4801 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4802 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4803 int pipe = intel_crtc->pipe;
4804 int plane = intel_crtc->plane;
4805 int refclk, num_connectors = 0;
4806 intel_clock_t clock, reduced_clock;
4807 u32 dspcntr;
4808 bool ok, has_reduced_clock = false;
4809 bool is_lvds = false;
4810 struct intel_encoder *encoder;
4811 const intel_limit_t *limit;
4812 int ret;
4813
4814 for_each_encoder_on_crtc(dev, crtc, encoder) {
4815 switch (encoder->type) {
4816 case INTEL_OUTPUT_LVDS:
4817 is_lvds = true;
4818 break;
4819 }
4820
4821 num_connectors++;
4822 }
4823
4824 refclk = i9xx_get_refclk(crtc, num_connectors);
4825
4826 /*
4827 * Returns a set of divisors for the desired target clock with the given
4828 * refclk, or FALSE. The returned values represent the clock equation:
4829 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4830 */
4831 limit = intel_limit(crtc, refclk);
4832 ok = dev_priv->display.find_dpll(limit, crtc,
4833 intel_crtc->config.port_clock,
4834 refclk, NULL, &clock);
4835 if (!ok && !intel_crtc->config.clock_set) {
4836 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4837 return -EINVAL;
4838 }
4839
4840 /* Ensure that the cursor is valid for the new mode before changing... */
4841 intel_crtc_update_cursor(crtc, true);
4842
4843 if (is_lvds && dev_priv->lvds_downclock_avail) {
4844 /*
4845 * Ensure we match the reduced clock's P to the target clock.
4846 * If the clocks don't match, we can't switch the display clock
4847 * by using the FP0/FP1. In such case we will disable the LVDS
4848 * downclock feature.
4849 */
4850 has_reduced_clock =
4851 dev_priv->display.find_dpll(limit, crtc,
4852 dev_priv->lvds_downclock,
4853 refclk, &clock,
4854 &reduced_clock);
4855 }
4856 /* Compat-code for transition, will disappear. */
4857 if (!intel_crtc->config.clock_set) {
4858 intel_crtc->config.dpll.n = clock.n;
4859 intel_crtc->config.dpll.m1 = clock.m1;
4860 intel_crtc->config.dpll.m2 = clock.m2;
4861 intel_crtc->config.dpll.p1 = clock.p1;
4862 intel_crtc->config.dpll.p2 = clock.p2;
4863 }
4864
4865 if (IS_GEN2(dev))
4866 i8xx_update_pll(intel_crtc,
4867 has_reduced_clock ? &reduced_clock : NULL,
4868 num_connectors);
4869 else if (IS_VALLEYVIEW(dev))
4870 vlv_update_pll(intel_crtc);
4871 else
4872 i9xx_update_pll(intel_crtc,
4873 has_reduced_clock ? &reduced_clock : NULL,
4874 num_connectors);
4875
4876 /* Set up the display plane register */
4877 dspcntr = DISPPLANE_GAMMA_ENABLE;
4878
4879 if (!IS_VALLEYVIEW(dev)) {
4880 if (pipe == 0)
4881 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4882 else
4883 dspcntr |= DISPPLANE_SEL_PIPE_B;
4884 }
4885
4886 intel_set_pipe_timings(intel_crtc);
4887
4888 /* pipesrc and dspsize control the size that is scaled from,
4889 * which should always be the user's requested size.
4890 */
4891 I915_WRITE(DSPSIZE(plane),
4892 ((mode->vdisplay - 1) << 16) |
4893 (mode->hdisplay - 1));
4894 I915_WRITE(DSPPOS(plane), 0);
4895
4896 i9xx_set_pipeconf(intel_crtc);
4897
4898 I915_WRITE(DSPCNTR(plane), dspcntr);
4899 POSTING_READ(DSPCNTR(plane));
4900
4901 ret = intel_pipe_set_base(crtc, x, y, fb);
4902
4903 intel_update_watermarks(dev);
4904
4905 return ret;
4906 }
4907
4908 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4909 struct intel_crtc_config *pipe_config)
4910 {
4911 struct drm_device *dev = crtc->base.dev;
4912 struct drm_i915_private *dev_priv = dev->dev_private;
4913 uint32_t tmp;
4914
4915 tmp = I915_READ(PFIT_CONTROL);
4916 if (!(tmp & PFIT_ENABLE))
4917 return;
4918
4919 /* Check whether the pfit is attached to our pipe. */
4920 if (INTEL_INFO(dev)->gen < 4) {
4921 if (crtc->pipe != PIPE_B)
4922 return;
4923 } else {
4924 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4925 return;
4926 }
4927
4928 pipe_config->gmch_pfit.control = tmp;
4929 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4930 if (INTEL_INFO(dev)->gen < 5)
4931 pipe_config->gmch_pfit.lvds_border_bits =
4932 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4933 }
4934
4935 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4936 struct intel_crtc_config *pipe_config)
4937 {
4938 struct drm_device *dev = crtc->base.dev;
4939 struct drm_i915_private *dev_priv = dev->dev_private;
4940 uint32_t tmp;
4941
4942 pipe_config->cpu_transcoder = crtc->pipe;
4943 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
4944
4945 tmp = I915_READ(PIPECONF(crtc->pipe));
4946 if (!(tmp & PIPECONF_ENABLE))
4947 return false;
4948
4949 intel_get_pipe_timings(crtc, pipe_config);
4950
4951 i9xx_get_pfit_config(crtc, pipe_config);
4952
4953 if (INTEL_INFO(dev)->gen >= 4) {
4954 tmp = I915_READ(DPLL_MD(crtc->pipe));
4955 pipe_config->pixel_multiplier =
4956 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
4957 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
4958 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4959 tmp = I915_READ(DPLL(crtc->pipe));
4960 pipe_config->pixel_multiplier =
4961 ((tmp & SDVO_MULTIPLIER_MASK)
4962 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
4963 } else {
4964 /* Note that on i915G/GM the pixel multiplier is in the sdvo
4965 * port and will be fixed up in the encoder->get_config
4966 * function. */
4967 pipe_config->pixel_multiplier = 1;
4968 }
4969
4970 return true;
4971 }
4972
4973 static void ironlake_init_pch_refclk(struct drm_device *dev)
4974 {
4975 struct drm_i915_private *dev_priv = dev->dev_private;
4976 struct drm_mode_config *mode_config = &dev->mode_config;
4977 struct intel_encoder *encoder;
4978 u32 val, final;
4979 bool has_lvds = false;
4980 bool has_cpu_edp = false;
4981 bool has_panel = false;
4982 bool has_ck505 = false;
4983 bool can_ssc = false;
4984
4985 /* We need to take the global config into account */
4986 list_for_each_entry(encoder, &mode_config->encoder_list,
4987 base.head) {
4988 switch (encoder->type) {
4989 case INTEL_OUTPUT_LVDS:
4990 has_panel = true;
4991 has_lvds = true;
4992 break;
4993 case INTEL_OUTPUT_EDP:
4994 has_panel = true;
4995 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
4996 has_cpu_edp = true;
4997 break;
4998 }
4999 }
5000
5001 if (HAS_PCH_IBX(dev)) {
5002 has_ck505 = dev_priv->vbt.display_clock_mode;
5003 can_ssc = has_ck505;
5004 } else {
5005 has_ck505 = false;
5006 can_ssc = true;
5007 }
5008
5009 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5010 has_panel, has_lvds, has_ck505);
5011
5012 /* Ironlake: try to setup display ref clock before DPLL
5013 * enabling. This is only under driver's control after
5014 * PCH B stepping, previous chipset stepping should be
5015 * ignoring this setting.
5016 */
5017 val = I915_READ(PCH_DREF_CONTROL);
5018
5019 /* As we must carefully and slowly disable/enable each source in turn,
5020 * compute the final state we want first and check if we need to
5021 * make any changes at all.
5022 */
5023 final = val;
5024 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5025 if (has_ck505)
5026 final |= DREF_NONSPREAD_CK505_ENABLE;
5027 else
5028 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5029
5030 final &= ~DREF_SSC_SOURCE_MASK;
5031 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5032 final &= ~DREF_SSC1_ENABLE;
5033
5034 if (has_panel) {
5035 final |= DREF_SSC_SOURCE_ENABLE;
5036
5037 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5038 final |= DREF_SSC1_ENABLE;
5039
5040 if (has_cpu_edp) {
5041 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5042 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5043 else
5044 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5045 } else
5046 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5047 } else {
5048 final |= DREF_SSC_SOURCE_DISABLE;
5049 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5050 }
5051
5052 if (final == val)
5053 return;
5054
5055 /* Always enable nonspread source */
5056 val &= ~DREF_NONSPREAD_SOURCE_MASK;
5057
5058 if (has_ck505)
5059 val |= DREF_NONSPREAD_CK505_ENABLE;
5060 else
5061 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5062
5063 if (has_panel) {
5064 val &= ~DREF_SSC_SOURCE_MASK;
5065 val |= DREF_SSC_SOURCE_ENABLE;
5066
5067 /* SSC must be turned on before enabling the CPU output */
5068 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5069 DRM_DEBUG_KMS("Using SSC on panel\n");
5070 val |= DREF_SSC1_ENABLE;
5071 } else
5072 val &= ~DREF_SSC1_ENABLE;
5073
5074 /* Get SSC going before enabling the outputs */
5075 I915_WRITE(PCH_DREF_CONTROL, val);
5076 POSTING_READ(PCH_DREF_CONTROL);
5077 udelay(200);
5078
5079 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5080
5081 /* Enable CPU source on CPU attached eDP */
5082 if (has_cpu_edp) {
5083 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5084 DRM_DEBUG_KMS("Using SSC on eDP\n");
5085 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5086 }
5087 else
5088 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5089 } else
5090 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5091
5092 I915_WRITE(PCH_DREF_CONTROL, val);
5093 POSTING_READ(PCH_DREF_CONTROL);
5094 udelay(200);
5095 } else {
5096 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5097
5098 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5099
5100 /* Turn off CPU output */
5101 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5102
5103 I915_WRITE(PCH_DREF_CONTROL, val);
5104 POSTING_READ(PCH_DREF_CONTROL);
5105 udelay(200);
5106
5107 /* Turn off the SSC source */
5108 val &= ~DREF_SSC_SOURCE_MASK;
5109 val |= DREF_SSC_SOURCE_DISABLE;
5110
5111 /* Turn off SSC1 */
5112 val &= ~DREF_SSC1_ENABLE;
5113
5114 I915_WRITE(PCH_DREF_CONTROL, val);
5115 POSTING_READ(PCH_DREF_CONTROL);
5116 udelay(200);
5117 }
5118
5119 BUG_ON(val != final);
5120 }
5121
5122 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5123 static void lpt_init_pch_refclk(struct drm_device *dev)
5124 {
5125 struct drm_i915_private *dev_priv = dev->dev_private;
5126 struct drm_mode_config *mode_config = &dev->mode_config;
5127 struct intel_encoder *encoder;
5128 bool has_vga = false;
5129 bool is_sdv = false;
5130 u32 tmp;
5131
5132 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5133 switch (encoder->type) {
5134 case INTEL_OUTPUT_ANALOG:
5135 has_vga = true;
5136 break;
5137 }
5138 }
5139
5140 if (!has_vga)
5141 return;
5142
5143 mutex_lock(&dev_priv->dpio_lock);
5144
5145 /* XXX: Rip out SDV support once Haswell ships for real. */
5146 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5147 is_sdv = true;
5148
5149 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5150 tmp &= ~SBI_SSCCTL_DISABLE;
5151 tmp |= SBI_SSCCTL_PATHALT;
5152 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5153
5154 udelay(24);
5155
5156 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5157 tmp &= ~SBI_SSCCTL_PATHALT;
5158 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5159
5160 if (!is_sdv) {
5161 tmp = I915_READ(SOUTH_CHICKEN2);
5162 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5163 I915_WRITE(SOUTH_CHICKEN2, tmp);
5164
5165 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5166 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5167 DRM_ERROR("FDI mPHY reset assert timeout\n");
5168
5169 tmp = I915_READ(SOUTH_CHICKEN2);
5170 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5171 I915_WRITE(SOUTH_CHICKEN2, tmp);
5172
5173 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5174 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5175 100))
5176 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5177 }
5178
5179 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5180 tmp &= ~(0xFF << 24);
5181 tmp |= (0x12 << 24);
5182 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5183
5184 if (is_sdv) {
5185 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5186 tmp |= 0x7FFF;
5187 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5188 }
5189
5190 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5191 tmp |= (1 << 11);
5192 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5193
5194 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5195 tmp |= (1 << 11);
5196 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5197
5198 if (is_sdv) {
5199 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5200 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5201 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5202
5203 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5204 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5205 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5206
5207 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5208 tmp |= (0x3F << 8);
5209 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5210
5211 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5212 tmp |= (0x3F << 8);
5213 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5214 }
5215
5216 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5217 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5218 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5219
5220 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5221 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5222 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5223
5224 if (!is_sdv) {
5225 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5226 tmp &= ~(7 << 13);
5227 tmp |= (5 << 13);
5228 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5229
5230 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5231 tmp &= ~(7 << 13);
5232 tmp |= (5 << 13);
5233 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5234 }
5235
5236 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5237 tmp &= ~0xFF;
5238 tmp |= 0x1C;
5239 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5240
5241 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5242 tmp &= ~0xFF;
5243 tmp |= 0x1C;
5244 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5245
5246 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5247 tmp &= ~(0xFF << 16);
5248 tmp |= (0x1C << 16);
5249 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5250
5251 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5252 tmp &= ~(0xFF << 16);
5253 tmp |= (0x1C << 16);
5254 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5255
5256 if (!is_sdv) {
5257 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5258 tmp |= (1 << 27);
5259 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5260
5261 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5262 tmp |= (1 << 27);
5263 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5264
5265 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5266 tmp &= ~(0xF << 28);
5267 tmp |= (4 << 28);
5268 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5269
5270 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5271 tmp &= ~(0xF << 28);
5272 tmp |= (4 << 28);
5273 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5274 }
5275
5276 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5277 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5278 tmp |= SBI_DBUFF0_ENABLE;
5279 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5280
5281 mutex_unlock(&dev_priv->dpio_lock);
5282 }
5283
5284 /*
5285 * Initialize reference clocks when the driver loads
5286 */
5287 void intel_init_pch_refclk(struct drm_device *dev)
5288 {
5289 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5290 ironlake_init_pch_refclk(dev);
5291 else if (HAS_PCH_LPT(dev))
5292 lpt_init_pch_refclk(dev);
5293 }
5294
5295 static int ironlake_get_refclk(struct drm_crtc *crtc)
5296 {
5297 struct drm_device *dev = crtc->dev;
5298 struct drm_i915_private *dev_priv = dev->dev_private;
5299 struct intel_encoder *encoder;
5300 int num_connectors = 0;
5301 bool is_lvds = false;
5302
5303 for_each_encoder_on_crtc(dev, crtc, encoder) {
5304 switch (encoder->type) {
5305 case INTEL_OUTPUT_LVDS:
5306 is_lvds = true;
5307 break;
5308 }
5309 num_connectors++;
5310 }
5311
5312 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5313 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5314 dev_priv->vbt.lvds_ssc_freq);
5315 return dev_priv->vbt.lvds_ssc_freq * 1000;
5316 }
5317
5318 return 120000;
5319 }
5320
5321 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5322 {
5323 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5324 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5325 int pipe = intel_crtc->pipe;
5326 uint32_t val;
5327
5328 val = 0;
5329
5330 switch (intel_crtc->config.pipe_bpp) {
5331 case 18:
5332 val |= PIPECONF_6BPC;
5333 break;
5334 case 24:
5335 val |= PIPECONF_8BPC;
5336 break;
5337 case 30:
5338 val |= PIPECONF_10BPC;
5339 break;
5340 case 36:
5341 val |= PIPECONF_12BPC;
5342 break;
5343 default:
5344 /* Case prevented by intel_choose_pipe_bpp_dither. */
5345 BUG();
5346 }
5347
5348 if (intel_crtc->config.dither)
5349 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5350
5351 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5352 val |= PIPECONF_INTERLACED_ILK;
5353 else
5354 val |= PIPECONF_PROGRESSIVE;
5355
5356 if (intel_crtc->config.limited_color_range)
5357 val |= PIPECONF_COLOR_RANGE_SELECT;
5358
5359 I915_WRITE(PIPECONF(pipe), val);
5360 POSTING_READ(PIPECONF(pipe));
5361 }
5362
5363 /*
5364 * Set up the pipe CSC unit.
5365 *
5366 * Currently only full range RGB to limited range RGB conversion
5367 * is supported, but eventually this should handle various
5368 * RGB<->YCbCr scenarios as well.
5369 */
5370 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5371 {
5372 struct drm_device *dev = crtc->dev;
5373 struct drm_i915_private *dev_priv = dev->dev_private;
5374 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5375 int pipe = intel_crtc->pipe;
5376 uint16_t coeff = 0x7800; /* 1.0 */
5377
5378 /*
5379 * TODO: Check what kind of values actually come out of the pipe
5380 * with these coeff/postoff values and adjust to get the best
5381 * accuracy. Perhaps we even need to take the bpc value into
5382 * consideration.
5383 */
5384
5385 if (intel_crtc->config.limited_color_range)
5386 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5387
5388 /*
5389 * GY/GU and RY/RU should be the other way around according
5390 * to BSpec, but reality doesn't agree. Just set them up in
5391 * a way that results in the correct picture.
5392 */
5393 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5394 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5395
5396 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5397 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5398
5399 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5400 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5401
5402 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5403 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5404 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5405
5406 if (INTEL_INFO(dev)->gen > 6) {
5407 uint16_t postoff = 0;
5408
5409 if (intel_crtc->config.limited_color_range)
5410 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5411
5412 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5413 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5414 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5415
5416 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5417 } else {
5418 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5419
5420 if (intel_crtc->config.limited_color_range)
5421 mode |= CSC_BLACK_SCREEN_OFFSET;
5422
5423 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5424 }
5425 }
5426
5427 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5428 {
5429 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5430 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5431 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5432 uint32_t val;
5433
5434 val = 0;
5435
5436 if (intel_crtc->config.dither)
5437 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5438
5439 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5440 val |= PIPECONF_INTERLACED_ILK;
5441 else
5442 val |= PIPECONF_PROGRESSIVE;
5443
5444 I915_WRITE(PIPECONF(cpu_transcoder), val);
5445 POSTING_READ(PIPECONF(cpu_transcoder));
5446
5447 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5448 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
5449 }
5450
5451 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5452 intel_clock_t *clock,
5453 bool *has_reduced_clock,
5454 intel_clock_t *reduced_clock)
5455 {
5456 struct drm_device *dev = crtc->dev;
5457 struct drm_i915_private *dev_priv = dev->dev_private;
5458 struct intel_encoder *intel_encoder;
5459 int refclk;
5460 const intel_limit_t *limit;
5461 bool ret, is_lvds = false;
5462
5463 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5464 switch (intel_encoder->type) {
5465 case INTEL_OUTPUT_LVDS:
5466 is_lvds = true;
5467 break;
5468 }
5469 }
5470
5471 refclk = ironlake_get_refclk(crtc);
5472
5473 /*
5474 * Returns a set of divisors for the desired target clock with the given
5475 * refclk, or FALSE. The returned values represent the clock equation:
5476 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5477 */
5478 limit = intel_limit(crtc, refclk);
5479 ret = dev_priv->display.find_dpll(limit, crtc,
5480 to_intel_crtc(crtc)->config.port_clock,
5481 refclk, NULL, clock);
5482 if (!ret)
5483 return false;
5484
5485 if (is_lvds && dev_priv->lvds_downclock_avail) {
5486 /*
5487 * Ensure we match the reduced clock's P to the target clock.
5488 * If the clocks don't match, we can't switch the display clock
5489 * by using the FP0/FP1. In such case we will disable the LVDS
5490 * downclock feature.
5491 */
5492 *has_reduced_clock =
5493 dev_priv->display.find_dpll(limit, crtc,
5494 dev_priv->lvds_downclock,
5495 refclk, clock,
5496 reduced_clock);
5497 }
5498
5499 return true;
5500 }
5501
5502 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5503 {
5504 struct drm_i915_private *dev_priv = dev->dev_private;
5505 uint32_t temp;
5506
5507 temp = I915_READ(SOUTH_CHICKEN1);
5508 if (temp & FDI_BC_BIFURCATION_SELECT)
5509 return;
5510
5511 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5512 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5513
5514 temp |= FDI_BC_BIFURCATION_SELECT;
5515 DRM_DEBUG_KMS("enabling fdi C rx\n");
5516 I915_WRITE(SOUTH_CHICKEN1, temp);
5517 POSTING_READ(SOUTH_CHICKEN1);
5518 }
5519
5520 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5521 {
5522 struct drm_device *dev = intel_crtc->base.dev;
5523 struct drm_i915_private *dev_priv = dev->dev_private;
5524
5525 switch (intel_crtc->pipe) {
5526 case PIPE_A:
5527 break;
5528 case PIPE_B:
5529 if (intel_crtc->config.fdi_lanes > 2)
5530 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5531 else
5532 cpt_enable_fdi_bc_bifurcation(dev);
5533
5534 break;
5535 case PIPE_C:
5536 cpt_enable_fdi_bc_bifurcation(dev);
5537
5538 break;
5539 default:
5540 BUG();
5541 }
5542 }
5543
5544 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5545 {
5546 /*
5547 * Account for spread spectrum to avoid
5548 * oversubscribing the link. Max center spread
5549 * is 2.5%; use 5% for safety's sake.
5550 */
5551 u32 bps = target_clock * bpp * 21 / 20;
5552 return bps / (link_bw * 8) + 1;
5553 }
5554
5555 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5556 {
5557 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5558 }
5559
5560 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5561 u32 *fp,
5562 intel_clock_t *reduced_clock, u32 *fp2)
5563 {
5564 struct drm_crtc *crtc = &intel_crtc->base;
5565 struct drm_device *dev = crtc->dev;
5566 struct drm_i915_private *dev_priv = dev->dev_private;
5567 struct intel_encoder *intel_encoder;
5568 uint32_t dpll;
5569 int factor, num_connectors = 0;
5570 bool is_lvds = false, is_sdvo = false;
5571
5572 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5573 switch (intel_encoder->type) {
5574 case INTEL_OUTPUT_LVDS:
5575 is_lvds = true;
5576 break;
5577 case INTEL_OUTPUT_SDVO:
5578 case INTEL_OUTPUT_HDMI:
5579 is_sdvo = true;
5580 break;
5581 }
5582
5583 num_connectors++;
5584 }
5585
5586 /* Enable autotuning of the PLL clock (if permissible) */
5587 factor = 21;
5588 if (is_lvds) {
5589 if ((intel_panel_use_ssc(dev_priv) &&
5590 dev_priv->vbt.lvds_ssc_freq == 100) ||
5591 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5592 factor = 25;
5593 } else if (intel_crtc->config.sdvo_tv_clock)
5594 factor = 20;
5595
5596 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5597 *fp |= FP_CB_TUNE;
5598
5599 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5600 *fp2 |= FP_CB_TUNE;
5601
5602 dpll = 0;
5603
5604 if (is_lvds)
5605 dpll |= DPLLB_MODE_LVDS;
5606 else
5607 dpll |= DPLLB_MODE_DAC_SERIAL;
5608
5609 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5610 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5611
5612 if (is_sdvo)
5613 dpll |= DPLL_DVO_HIGH_SPEED;
5614 if (intel_crtc->config.has_dp_encoder)
5615 dpll |= DPLL_DVO_HIGH_SPEED;
5616
5617 /* compute bitmask from p1 value */
5618 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5619 /* also FPA1 */
5620 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5621
5622 switch (intel_crtc->config.dpll.p2) {
5623 case 5:
5624 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5625 break;
5626 case 7:
5627 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5628 break;
5629 case 10:
5630 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5631 break;
5632 case 14:
5633 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5634 break;
5635 }
5636
5637 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5638 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5639 else
5640 dpll |= PLL_REF_INPUT_DREFCLK;
5641
5642 return dpll | DPLL_VCO_ENABLE;
5643 }
5644
5645 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5646 int x, int y,
5647 struct drm_framebuffer *fb)
5648 {
5649 struct drm_device *dev = crtc->dev;
5650 struct drm_i915_private *dev_priv = dev->dev_private;
5651 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5652 int pipe = intel_crtc->pipe;
5653 int plane = intel_crtc->plane;
5654 int num_connectors = 0;
5655 intel_clock_t clock, reduced_clock;
5656 u32 dpll = 0, fp = 0, fp2 = 0;
5657 bool ok, has_reduced_clock = false;
5658 bool is_lvds = false;
5659 struct intel_encoder *encoder;
5660 struct intel_shared_dpll *pll;
5661 int ret;
5662
5663 for_each_encoder_on_crtc(dev, crtc, encoder) {
5664 switch (encoder->type) {
5665 case INTEL_OUTPUT_LVDS:
5666 is_lvds = true;
5667 break;
5668 }
5669
5670 num_connectors++;
5671 }
5672
5673 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5674 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5675
5676 ok = ironlake_compute_clocks(crtc, &clock,
5677 &has_reduced_clock, &reduced_clock);
5678 if (!ok && !intel_crtc->config.clock_set) {
5679 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5680 return -EINVAL;
5681 }
5682 /* Compat-code for transition, will disappear. */
5683 if (!intel_crtc->config.clock_set) {
5684 intel_crtc->config.dpll.n = clock.n;
5685 intel_crtc->config.dpll.m1 = clock.m1;
5686 intel_crtc->config.dpll.m2 = clock.m2;
5687 intel_crtc->config.dpll.p1 = clock.p1;
5688 intel_crtc->config.dpll.p2 = clock.p2;
5689 }
5690
5691 /* Ensure that the cursor is valid for the new mode before changing... */
5692 intel_crtc_update_cursor(crtc, true);
5693
5694 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5695 if (intel_crtc->config.has_pch_encoder) {
5696 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5697 if (has_reduced_clock)
5698 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
5699
5700 dpll = ironlake_compute_dpll(intel_crtc,
5701 &fp, &reduced_clock,
5702 has_reduced_clock ? &fp2 : NULL);
5703
5704 intel_crtc->config.dpll_hw_state.dpll = dpll;
5705 intel_crtc->config.dpll_hw_state.fp0 = fp;
5706 if (has_reduced_clock)
5707 intel_crtc->config.dpll_hw_state.fp1 = fp2;
5708 else
5709 intel_crtc->config.dpll_hw_state.fp1 = fp;
5710
5711 pll = intel_get_shared_dpll(intel_crtc, dpll, fp);
5712 if (pll == NULL) {
5713 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5714 pipe_name(pipe));
5715 return -EINVAL;
5716 }
5717 } else
5718 intel_put_shared_dpll(intel_crtc);
5719
5720 if (intel_crtc->config.has_dp_encoder)
5721 intel_dp_set_m_n(intel_crtc);
5722
5723 for_each_encoder_on_crtc(dev, crtc, encoder)
5724 if (encoder->pre_pll_enable)
5725 encoder->pre_pll_enable(encoder);
5726
5727 if (is_lvds && has_reduced_clock && i915_powersave)
5728 intel_crtc->lowfreq_avail = true;
5729 else
5730 intel_crtc->lowfreq_avail = false;
5731
5732 if (intel_crtc->config.has_pch_encoder) {
5733 pll = intel_crtc_to_shared_dpll(intel_crtc);
5734
5735 I915_WRITE(PCH_DPLL(pll->id), dpll);
5736
5737 /* Wait for the clocks to stabilize. */
5738 POSTING_READ(PCH_DPLL(pll->id));
5739 udelay(150);
5740
5741 /* The pixel multiplier can only be updated once the
5742 * DPLL is enabled and the clocks are stable.
5743 *
5744 * So write it again.
5745 */
5746 I915_WRITE(PCH_DPLL(pll->id), dpll);
5747
5748 if (has_reduced_clock)
5749 I915_WRITE(PCH_FP1(pll->id), fp2);
5750 else
5751 I915_WRITE(PCH_FP1(pll->id), fp);
5752 }
5753
5754 intel_set_pipe_timings(intel_crtc);
5755
5756 if (intel_crtc->config.has_pch_encoder) {
5757 intel_cpu_transcoder_set_m_n(intel_crtc,
5758 &intel_crtc->config.fdi_m_n);
5759 }
5760
5761 if (IS_IVYBRIDGE(dev))
5762 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
5763
5764 ironlake_set_pipeconf(crtc);
5765
5766 /* Set up the display plane register */
5767 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5768 POSTING_READ(DSPCNTR(plane));
5769
5770 ret = intel_pipe_set_base(crtc, x, y, fb);
5771
5772 intel_update_watermarks(dev);
5773
5774 return ret;
5775 }
5776
5777 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5778 struct intel_crtc_config *pipe_config)
5779 {
5780 struct drm_device *dev = crtc->base.dev;
5781 struct drm_i915_private *dev_priv = dev->dev_private;
5782 enum transcoder transcoder = pipe_config->cpu_transcoder;
5783
5784 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5785 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5786 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5787 & ~TU_SIZE_MASK;
5788 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5789 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5790 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5791 }
5792
5793 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5794 struct intel_crtc_config *pipe_config)
5795 {
5796 struct drm_device *dev = crtc->base.dev;
5797 struct drm_i915_private *dev_priv = dev->dev_private;
5798 uint32_t tmp;
5799
5800 tmp = I915_READ(PF_CTL(crtc->pipe));
5801
5802 if (tmp & PF_ENABLE) {
5803 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5804 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5805
5806 /* We currently do not free assignements of panel fitters on
5807 * ivb/hsw (since we don't use the higher upscaling modes which
5808 * differentiates them) so just WARN about this case for now. */
5809 if (IS_GEN7(dev)) {
5810 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5811 PF_PIPE_SEL_IVB(crtc->pipe));
5812 }
5813 }
5814 }
5815
5816 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5817 struct intel_crtc_config *pipe_config)
5818 {
5819 struct drm_device *dev = crtc->base.dev;
5820 struct drm_i915_private *dev_priv = dev->dev_private;
5821 uint32_t tmp;
5822
5823 pipe_config->cpu_transcoder = crtc->pipe;
5824 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5825
5826 tmp = I915_READ(PIPECONF(crtc->pipe));
5827 if (!(tmp & PIPECONF_ENABLE))
5828 return false;
5829
5830 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
5831 struct intel_shared_dpll *pll;
5832
5833 pipe_config->has_pch_encoder = true;
5834
5835 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5836 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5837 FDI_DP_PORT_WIDTH_SHIFT) + 1;
5838
5839 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5840
5841 /* XXX: Can't properly read out the pch dpll pixel multiplier
5842 * since we don't have state tracking for pch clocks yet. */
5843 pipe_config->pixel_multiplier = 1;
5844
5845 if (HAS_PCH_IBX(dev_priv->dev)) {
5846 pipe_config->shared_dpll = crtc->pipe;
5847 } else {
5848 tmp = I915_READ(PCH_DPLL_SEL);
5849 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5850 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
5851 else
5852 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
5853 }
5854
5855 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
5856
5857 WARN_ON(!pll->get_hw_state(dev_priv, pll,
5858 &pipe_config->dpll_hw_state));
5859 } else {
5860 pipe_config->pixel_multiplier = 1;
5861 }
5862
5863 intel_get_pipe_timings(crtc, pipe_config);
5864
5865 ironlake_get_pfit_config(crtc, pipe_config);
5866
5867 return true;
5868 }
5869
5870 static void haswell_modeset_global_resources(struct drm_device *dev)
5871 {
5872 bool enable = false;
5873 struct intel_crtc *crtc;
5874
5875 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5876 if (!crtc->base.enabled)
5877 continue;
5878
5879 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
5880 crtc->config.cpu_transcoder != TRANSCODER_EDP)
5881 enable = true;
5882 }
5883
5884 intel_set_power_well(dev, enable);
5885 }
5886
5887 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5888 int x, int y,
5889 struct drm_framebuffer *fb)
5890 {
5891 struct drm_device *dev = crtc->dev;
5892 struct drm_i915_private *dev_priv = dev->dev_private;
5893 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5894 int plane = intel_crtc->plane;
5895 int ret;
5896
5897 if (!intel_ddi_pll_mode_set(crtc))
5898 return -EINVAL;
5899
5900 /* Ensure that the cursor is valid for the new mode before changing... */
5901 intel_crtc_update_cursor(crtc, true);
5902
5903 if (intel_crtc->config.has_dp_encoder)
5904 intel_dp_set_m_n(intel_crtc);
5905
5906 intel_crtc->lowfreq_avail = false;
5907
5908 intel_set_pipe_timings(intel_crtc);
5909
5910 if (intel_crtc->config.has_pch_encoder) {
5911 intel_cpu_transcoder_set_m_n(intel_crtc,
5912 &intel_crtc->config.fdi_m_n);
5913 }
5914
5915 haswell_set_pipeconf(crtc);
5916
5917 intel_set_pipe_csc(crtc);
5918
5919 /* Set up the display plane register */
5920 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
5921 POSTING_READ(DSPCNTR(plane));
5922
5923 ret = intel_pipe_set_base(crtc, x, y, fb);
5924
5925 intel_update_watermarks(dev);
5926
5927 return ret;
5928 }
5929
5930 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5931 struct intel_crtc_config *pipe_config)
5932 {
5933 struct drm_device *dev = crtc->base.dev;
5934 struct drm_i915_private *dev_priv = dev->dev_private;
5935 enum intel_display_power_domain pfit_domain;
5936 uint32_t tmp;
5937
5938 pipe_config->cpu_transcoder = crtc->pipe;
5939 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5940
5941 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
5942 if (tmp & TRANS_DDI_FUNC_ENABLE) {
5943 enum pipe trans_edp_pipe;
5944 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
5945 default:
5946 WARN(1, "unknown pipe linked to edp transcoder\n");
5947 case TRANS_DDI_EDP_INPUT_A_ONOFF:
5948 case TRANS_DDI_EDP_INPUT_A_ON:
5949 trans_edp_pipe = PIPE_A;
5950 break;
5951 case TRANS_DDI_EDP_INPUT_B_ONOFF:
5952 trans_edp_pipe = PIPE_B;
5953 break;
5954 case TRANS_DDI_EDP_INPUT_C_ONOFF:
5955 trans_edp_pipe = PIPE_C;
5956 break;
5957 }
5958
5959 if (trans_edp_pipe == crtc->pipe)
5960 pipe_config->cpu_transcoder = TRANSCODER_EDP;
5961 }
5962
5963 if (!intel_display_power_enabled(dev,
5964 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
5965 return false;
5966
5967 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
5968 if (!(tmp & PIPECONF_ENABLE))
5969 return false;
5970
5971 /*
5972 * Haswell has only FDI/PCH transcoder A. It is which is connected to
5973 * DDI E. So just check whether this pipe is wired to DDI E and whether
5974 * the PCH transcoder is on.
5975 */
5976 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
5977 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
5978 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
5979 pipe_config->has_pch_encoder = true;
5980
5981 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
5982 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5983 FDI_DP_PORT_WIDTH_SHIFT) + 1;
5984
5985 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5986 }
5987
5988 intel_get_pipe_timings(crtc, pipe_config);
5989
5990 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
5991 if (intel_display_power_enabled(dev, pfit_domain))
5992 ironlake_get_pfit_config(crtc, pipe_config);
5993
5994 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
5995 (I915_READ(IPS_CTL) & IPS_ENABLE);
5996
5997 pipe_config->pixel_multiplier = 1;
5998
5999 return true;
6000 }
6001
6002 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6003 int x, int y,
6004 struct drm_framebuffer *fb)
6005 {
6006 struct drm_device *dev = crtc->dev;
6007 struct drm_i915_private *dev_priv = dev->dev_private;
6008 struct drm_encoder_helper_funcs *encoder_funcs;
6009 struct intel_encoder *encoder;
6010 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6011 struct drm_display_mode *adjusted_mode =
6012 &intel_crtc->config.adjusted_mode;
6013 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6014 int pipe = intel_crtc->pipe;
6015 int ret;
6016
6017 drm_vblank_pre_modeset(dev, pipe);
6018
6019 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6020
6021 drm_vblank_post_modeset(dev, pipe);
6022
6023 if (ret != 0)
6024 return ret;
6025
6026 for_each_encoder_on_crtc(dev, crtc, encoder) {
6027 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6028 encoder->base.base.id,
6029 drm_get_encoder_name(&encoder->base),
6030 mode->base.id, mode->name);
6031 if (encoder->mode_set) {
6032 encoder->mode_set(encoder);
6033 } else {
6034 encoder_funcs = encoder->base.helper_private;
6035 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6036 }
6037 }
6038
6039 return 0;
6040 }
6041
6042 static bool intel_eld_uptodate(struct drm_connector *connector,
6043 int reg_eldv, uint32_t bits_eldv,
6044 int reg_elda, uint32_t bits_elda,
6045 int reg_edid)
6046 {
6047 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6048 uint8_t *eld = connector->eld;
6049 uint32_t i;
6050
6051 i = I915_READ(reg_eldv);
6052 i &= bits_eldv;
6053
6054 if (!eld[0])
6055 return !i;
6056
6057 if (!i)
6058 return false;
6059
6060 i = I915_READ(reg_elda);
6061 i &= ~bits_elda;
6062 I915_WRITE(reg_elda, i);
6063
6064 for (i = 0; i < eld[2]; i++)
6065 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6066 return false;
6067
6068 return true;
6069 }
6070
6071 static void g4x_write_eld(struct drm_connector *connector,
6072 struct drm_crtc *crtc)
6073 {
6074 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6075 uint8_t *eld = connector->eld;
6076 uint32_t eldv;
6077 uint32_t len;
6078 uint32_t i;
6079
6080 i = I915_READ(G4X_AUD_VID_DID);
6081
6082 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6083 eldv = G4X_ELDV_DEVCL_DEVBLC;
6084 else
6085 eldv = G4X_ELDV_DEVCTG;
6086
6087 if (intel_eld_uptodate(connector,
6088 G4X_AUD_CNTL_ST, eldv,
6089 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6090 G4X_HDMIW_HDMIEDID))
6091 return;
6092
6093 i = I915_READ(G4X_AUD_CNTL_ST);
6094 i &= ~(eldv | G4X_ELD_ADDR);
6095 len = (i >> 9) & 0x1f; /* ELD buffer size */
6096 I915_WRITE(G4X_AUD_CNTL_ST, i);
6097
6098 if (!eld[0])
6099 return;
6100
6101 len = min_t(uint8_t, eld[2], len);
6102 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6103 for (i = 0; i < len; i++)
6104 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6105
6106 i = I915_READ(G4X_AUD_CNTL_ST);
6107 i |= eldv;
6108 I915_WRITE(G4X_AUD_CNTL_ST, i);
6109 }
6110
6111 static void haswell_write_eld(struct drm_connector *connector,
6112 struct drm_crtc *crtc)
6113 {
6114 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6115 uint8_t *eld = connector->eld;
6116 struct drm_device *dev = crtc->dev;
6117 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6118 uint32_t eldv;
6119 uint32_t i;
6120 int len;
6121 int pipe = to_intel_crtc(crtc)->pipe;
6122 int tmp;
6123
6124 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6125 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6126 int aud_config = HSW_AUD_CFG(pipe);
6127 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6128
6129
6130 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6131
6132 /* Audio output enable */
6133 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6134 tmp = I915_READ(aud_cntrl_st2);
6135 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6136 I915_WRITE(aud_cntrl_st2, tmp);
6137
6138 /* Wait for 1 vertical blank */
6139 intel_wait_for_vblank(dev, pipe);
6140
6141 /* Set ELD valid state */
6142 tmp = I915_READ(aud_cntrl_st2);
6143 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6144 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6145 I915_WRITE(aud_cntrl_st2, tmp);
6146 tmp = I915_READ(aud_cntrl_st2);
6147 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6148
6149 /* Enable HDMI mode */
6150 tmp = I915_READ(aud_config);
6151 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6152 /* clear N_programing_enable and N_value_index */
6153 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6154 I915_WRITE(aud_config, tmp);
6155
6156 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6157
6158 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6159 intel_crtc->eld_vld = true;
6160
6161 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6162 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6163 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6164 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6165 } else
6166 I915_WRITE(aud_config, 0);
6167
6168 if (intel_eld_uptodate(connector,
6169 aud_cntrl_st2, eldv,
6170 aud_cntl_st, IBX_ELD_ADDRESS,
6171 hdmiw_hdmiedid))
6172 return;
6173
6174 i = I915_READ(aud_cntrl_st2);
6175 i &= ~eldv;
6176 I915_WRITE(aud_cntrl_st2, i);
6177
6178 if (!eld[0])
6179 return;
6180
6181 i = I915_READ(aud_cntl_st);
6182 i &= ~IBX_ELD_ADDRESS;
6183 I915_WRITE(aud_cntl_st, i);
6184 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6185 DRM_DEBUG_DRIVER("port num:%d\n", i);
6186
6187 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6188 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6189 for (i = 0; i < len; i++)
6190 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6191
6192 i = I915_READ(aud_cntrl_st2);
6193 i |= eldv;
6194 I915_WRITE(aud_cntrl_st2, i);
6195
6196 }
6197
6198 static void ironlake_write_eld(struct drm_connector *connector,
6199 struct drm_crtc *crtc)
6200 {
6201 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6202 uint8_t *eld = connector->eld;
6203 uint32_t eldv;
6204 uint32_t i;
6205 int len;
6206 int hdmiw_hdmiedid;
6207 int aud_config;
6208 int aud_cntl_st;
6209 int aud_cntrl_st2;
6210 int pipe = to_intel_crtc(crtc)->pipe;
6211
6212 if (HAS_PCH_IBX(connector->dev)) {
6213 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6214 aud_config = IBX_AUD_CFG(pipe);
6215 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6216 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6217 } else {
6218 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6219 aud_config = CPT_AUD_CFG(pipe);
6220 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6221 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6222 }
6223
6224 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6225
6226 i = I915_READ(aud_cntl_st);
6227 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6228 if (!i) {
6229 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6230 /* operate blindly on all ports */
6231 eldv = IBX_ELD_VALIDB;
6232 eldv |= IBX_ELD_VALIDB << 4;
6233 eldv |= IBX_ELD_VALIDB << 8;
6234 } else {
6235 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6236 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6237 }
6238
6239 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6240 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6241 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6242 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6243 } else
6244 I915_WRITE(aud_config, 0);
6245
6246 if (intel_eld_uptodate(connector,
6247 aud_cntrl_st2, eldv,
6248 aud_cntl_st, IBX_ELD_ADDRESS,
6249 hdmiw_hdmiedid))
6250 return;
6251
6252 i = I915_READ(aud_cntrl_st2);
6253 i &= ~eldv;
6254 I915_WRITE(aud_cntrl_st2, i);
6255
6256 if (!eld[0])
6257 return;
6258
6259 i = I915_READ(aud_cntl_st);
6260 i &= ~IBX_ELD_ADDRESS;
6261 I915_WRITE(aud_cntl_st, i);
6262
6263 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6264 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6265 for (i = 0; i < len; i++)
6266 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6267
6268 i = I915_READ(aud_cntrl_st2);
6269 i |= eldv;
6270 I915_WRITE(aud_cntrl_st2, i);
6271 }
6272
6273 void intel_write_eld(struct drm_encoder *encoder,
6274 struct drm_display_mode *mode)
6275 {
6276 struct drm_crtc *crtc = encoder->crtc;
6277 struct drm_connector *connector;
6278 struct drm_device *dev = encoder->dev;
6279 struct drm_i915_private *dev_priv = dev->dev_private;
6280
6281 connector = drm_select_eld(encoder, mode);
6282 if (!connector)
6283 return;
6284
6285 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6286 connector->base.id,
6287 drm_get_connector_name(connector),
6288 connector->encoder->base.id,
6289 drm_get_encoder_name(connector->encoder));
6290
6291 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6292
6293 if (dev_priv->display.write_eld)
6294 dev_priv->display.write_eld(connector, crtc);
6295 }
6296
6297 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6298 void intel_crtc_load_lut(struct drm_crtc *crtc)
6299 {
6300 struct drm_device *dev = crtc->dev;
6301 struct drm_i915_private *dev_priv = dev->dev_private;
6302 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6303 enum pipe pipe = intel_crtc->pipe;
6304 int palreg = PALETTE(pipe);
6305 int i;
6306 bool reenable_ips = false;
6307
6308 /* The clocks have to be on to load the palette. */
6309 if (!crtc->enabled || !intel_crtc->active)
6310 return;
6311
6312 if (!HAS_PCH_SPLIT(dev_priv->dev))
6313 assert_pll_enabled(dev_priv, pipe);
6314
6315 /* use legacy palette for Ironlake */
6316 if (HAS_PCH_SPLIT(dev))
6317 palreg = LGC_PALETTE(pipe);
6318
6319 /* Workaround : Do not read or write the pipe palette/gamma data while
6320 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6321 */
6322 if (intel_crtc->config.ips_enabled &&
6323 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6324 GAMMA_MODE_MODE_SPLIT)) {
6325 hsw_disable_ips(intel_crtc);
6326 reenable_ips = true;
6327 }
6328
6329 for (i = 0; i < 256; i++) {
6330 I915_WRITE(palreg + 4 * i,
6331 (intel_crtc->lut_r[i] << 16) |
6332 (intel_crtc->lut_g[i] << 8) |
6333 intel_crtc->lut_b[i]);
6334 }
6335
6336 if (reenable_ips)
6337 hsw_enable_ips(intel_crtc);
6338 }
6339
6340 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6341 {
6342 struct drm_device *dev = crtc->dev;
6343 struct drm_i915_private *dev_priv = dev->dev_private;
6344 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6345 bool visible = base != 0;
6346 u32 cntl;
6347
6348 if (intel_crtc->cursor_visible == visible)
6349 return;
6350
6351 cntl = I915_READ(_CURACNTR);
6352 if (visible) {
6353 /* On these chipsets we can only modify the base whilst
6354 * the cursor is disabled.
6355 */
6356 I915_WRITE(_CURABASE, base);
6357
6358 cntl &= ~(CURSOR_FORMAT_MASK);
6359 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6360 cntl |= CURSOR_ENABLE |
6361 CURSOR_GAMMA_ENABLE |
6362 CURSOR_FORMAT_ARGB;
6363 } else
6364 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6365 I915_WRITE(_CURACNTR, cntl);
6366
6367 intel_crtc->cursor_visible = visible;
6368 }
6369
6370 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6371 {
6372 struct drm_device *dev = crtc->dev;
6373 struct drm_i915_private *dev_priv = dev->dev_private;
6374 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6375 int pipe = intel_crtc->pipe;
6376 bool visible = base != 0;
6377
6378 if (intel_crtc->cursor_visible != visible) {
6379 uint32_t cntl = I915_READ(CURCNTR(pipe));
6380 if (base) {
6381 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6382 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6383 cntl |= pipe << 28; /* Connect to correct pipe */
6384 } else {
6385 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6386 cntl |= CURSOR_MODE_DISABLE;
6387 }
6388 I915_WRITE(CURCNTR(pipe), cntl);
6389
6390 intel_crtc->cursor_visible = visible;
6391 }
6392 /* and commit changes on next vblank */
6393 I915_WRITE(CURBASE(pipe), base);
6394 }
6395
6396 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6397 {
6398 struct drm_device *dev = crtc->dev;
6399 struct drm_i915_private *dev_priv = dev->dev_private;
6400 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6401 int pipe = intel_crtc->pipe;
6402 bool visible = base != 0;
6403
6404 if (intel_crtc->cursor_visible != visible) {
6405 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6406 if (base) {
6407 cntl &= ~CURSOR_MODE;
6408 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6409 } else {
6410 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6411 cntl |= CURSOR_MODE_DISABLE;
6412 }
6413 if (IS_HASWELL(dev))
6414 cntl |= CURSOR_PIPE_CSC_ENABLE;
6415 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6416
6417 intel_crtc->cursor_visible = visible;
6418 }
6419 /* and commit changes on next vblank */
6420 I915_WRITE(CURBASE_IVB(pipe), base);
6421 }
6422
6423 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6424 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6425 bool on)
6426 {
6427 struct drm_device *dev = crtc->dev;
6428 struct drm_i915_private *dev_priv = dev->dev_private;
6429 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6430 int pipe = intel_crtc->pipe;
6431 int x = intel_crtc->cursor_x;
6432 int y = intel_crtc->cursor_y;
6433 u32 base, pos;
6434 bool visible;
6435
6436 pos = 0;
6437
6438 if (on && crtc->enabled && crtc->fb) {
6439 base = intel_crtc->cursor_addr;
6440 if (x > (int) crtc->fb->width)
6441 base = 0;
6442
6443 if (y > (int) crtc->fb->height)
6444 base = 0;
6445 } else
6446 base = 0;
6447
6448 if (x < 0) {
6449 if (x + intel_crtc->cursor_width < 0)
6450 base = 0;
6451
6452 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6453 x = -x;
6454 }
6455 pos |= x << CURSOR_X_SHIFT;
6456
6457 if (y < 0) {
6458 if (y + intel_crtc->cursor_height < 0)
6459 base = 0;
6460
6461 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6462 y = -y;
6463 }
6464 pos |= y << CURSOR_Y_SHIFT;
6465
6466 visible = base != 0;
6467 if (!visible && !intel_crtc->cursor_visible)
6468 return;
6469
6470 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6471 I915_WRITE(CURPOS_IVB(pipe), pos);
6472 ivb_update_cursor(crtc, base);
6473 } else {
6474 I915_WRITE(CURPOS(pipe), pos);
6475 if (IS_845G(dev) || IS_I865G(dev))
6476 i845_update_cursor(crtc, base);
6477 else
6478 i9xx_update_cursor(crtc, base);
6479 }
6480 }
6481
6482 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6483 struct drm_file *file,
6484 uint32_t handle,
6485 uint32_t width, uint32_t height)
6486 {
6487 struct drm_device *dev = crtc->dev;
6488 struct drm_i915_private *dev_priv = dev->dev_private;
6489 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6490 struct drm_i915_gem_object *obj;
6491 uint32_t addr;
6492 int ret;
6493
6494 /* if we want to turn off the cursor ignore width and height */
6495 if (!handle) {
6496 DRM_DEBUG_KMS("cursor off\n");
6497 addr = 0;
6498 obj = NULL;
6499 mutex_lock(&dev->struct_mutex);
6500 goto finish;
6501 }
6502
6503 /* Currently we only support 64x64 cursors */
6504 if (width != 64 || height != 64) {
6505 DRM_ERROR("we currently only support 64x64 cursors\n");
6506 return -EINVAL;
6507 }
6508
6509 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6510 if (&obj->base == NULL)
6511 return -ENOENT;
6512
6513 if (obj->base.size < width * height * 4) {
6514 DRM_ERROR("buffer is to small\n");
6515 ret = -ENOMEM;
6516 goto fail;
6517 }
6518
6519 /* we only need to pin inside GTT if cursor is non-phy */
6520 mutex_lock(&dev->struct_mutex);
6521 if (!dev_priv->info->cursor_needs_physical) {
6522 unsigned alignment;
6523
6524 if (obj->tiling_mode) {
6525 DRM_ERROR("cursor cannot be tiled\n");
6526 ret = -EINVAL;
6527 goto fail_locked;
6528 }
6529
6530 /* Note that the w/a also requires 2 PTE of padding following
6531 * the bo. We currently fill all unused PTE with the shadow
6532 * page and so we should always have valid PTE following the
6533 * cursor preventing the VT-d warning.
6534 */
6535 alignment = 0;
6536 if (need_vtd_wa(dev))
6537 alignment = 64*1024;
6538
6539 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6540 if (ret) {
6541 DRM_ERROR("failed to move cursor bo into the GTT\n");
6542 goto fail_locked;
6543 }
6544
6545 ret = i915_gem_object_put_fence(obj);
6546 if (ret) {
6547 DRM_ERROR("failed to release fence for cursor");
6548 goto fail_unpin;
6549 }
6550
6551 addr = obj->gtt_offset;
6552 } else {
6553 int align = IS_I830(dev) ? 16 * 1024 : 256;
6554 ret = i915_gem_attach_phys_object(dev, obj,
6555 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6556 align);
6557 if (ret) {
6558 DRM_ERROR("failed to attach phys object\n");
6559 goto fail_locked;
6560 }
6561 addr = obj->phys_obj->handle->busaddr;
6562 }
6563
6564 if (IS_GEN2(dev))
6565 I915_WRITE(CURSIZE, (height << 12) | width);
6566
6567 finish:
6568 if (intel_crtc->cursor_bo) {
6569 if (dev_priv->info->cursor_needs_physical) {
6570 if (intel_crtc->cursor_bo != obj)
6571 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6572 } else
6573 i915_gem_object_unpin(intel_crtc->cursor_bo);
6574 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6575 }
6576
6577 mutex_unlock(&dev->struct_mutex);
6578
6579 intel_crtc->cursor_addr = addr;
6580 intel_crtc->cursor_bo = obj;
6581 intel_crtc->cursor_width = width;
6582 intel_crtc->cursor_height = height;
6583
6584 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6585
6586 return 0;
6587 fail_unpin:
6588 i915_gem_object_unpin(obj);
6589 fail_locked:
6590 mutex_unlock(&dev->struct_mutex);
6591 fail:
6592 drm_gem_object_unreference_unlocked(&obj->base);
6593 return ret;
6594 }
6595
6596 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6597 {
6598 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6599
6600 intel_crtc->cursor_x = x;
6601 intel_crtc->cursor_y = y;
6602
6603 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6604
6605 return 0;
6606 }
6607
6608 /** Sets the color ramps on behalf of RandR */
6609 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6610 u16 blue, int regno)
6611 {
6612 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6613
6614 intel_crtc->lut_r[regno] = red >> 8;
6615 intel_crtc->lut_g[regno] = green >> 8;
6616 intel_crtc->lut_b[regno] = blue >> 8;
6617 }
6618
6619 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6620 u16 *blue, int regno)
6621 {
6622 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6623
6624 *red = intel_crtc->lut_r[regno] << 8;
6625 *green = intel_crtc->lut_g[regno] << 8;
6626 *blue = intel_crtc->lut_b[regno] << 8;
6627 }
6628
6629 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6630 u16 *blue, uint32_t start, uint32_t size)
6631 {
6632 int end = (start + size > 256) ? 256 : start + size, i;
6633 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6634
6635 for (i = start; i < end; i++) {
6636 intel_crtc->lut_r[i] = red[i] >> 8;
6637 intel_crtc->lut_g[i] = green[i] >> 8;
6638 intel_crtc->lut_b[i] = blue[i] >> 8;
6639 }
6640
6641 intel_crtc_load_lut(crtc);
6642 }
6643
6644 /* VESA 640x480x72Hz mode to set on the pipe */
6645 static struct drm_display_mode load_detect_mode = {
6646 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6647 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6648 };
6649
6650 static struct drm_framebuffer *
6651 intel_framebuffer_create(struct drm_device *dev,
6652 struct drm_mode_fb_cmd2 *mode_cmd,
6653 struct drm_i915_gem_object *obj)
6654 {
6655 struct intel_framebuffer *intel_fb;
6656 int ret;
6657
6658 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6659 if (!intel_fb) {
6660 drm_gem_object_unreference_unlocked(&obj->base);
6661 return ERR_PTR(-ENOMEM);
6662 }
6663
6664 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6665 if (ret) {
6666 drm_gem_object_unreference_unlocked(&obj->base);
6667 kfree(intel_fb);
6668 return ERR_PTR(ret);
6669 }
6670
6671 return &intel_fb->base;
6672 }
6673
6674 static u32
6675 intel_framebuffer_pitch_for_width(int width, int bpp)
6676 {
6677 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6678 return ALIGN(pitch, 64);
6679 }
6680
6681 static u32
6682 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6683 {
6684 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6685 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6686 }
6687
6688 static struct drm_framebuffer *
6689 intel_framebuffer_create_for_mode(struct drm_device *dev,
6690 struct drm_display_mode *mode,
6691 int depth, int bpp)
6692 {
6693 struct drm_i915_gem_object *obj;
6694 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6695
6696 obj = i915_gem_alloc_object(dev,
6697 intel_framebuffer_size_for_mode(mode, bpp));
6698 if (obj == NULL)
6699 return ERR_PTR(-ENOMEM);
6700
6701 mode_cmd.width = mode->hdisplay;
6702 mode_cmd.height = mode->vdisplay;
6703 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6704 bpp);
6705 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6706
6707 return intel_framebuffer_create(dev, &mode_cmd, obj);
6708 }
6709
6710 static struct drm_framebuffer *
6711 mode_fits_in_fbdev(struct drm_device *dev,
6712 struct drm_display_mode *mode)
6713 {
6714 struct drm_i915_private *dev_priv = dev->dev_private;
6715 struct drm_i915_gem_object *obj;
6716 struct drm_framebuffer *fb;
6717
6718 if (dev_priv->fbdev == NULL)
6719 return NULL;
6720
6721 obj = dev_priv->fbdev->ifb.obj;
6722 if (obj == NULL)
6723 return NULL;
6724
6725 fb = &dev_priv->fbdev->ifb.base;
6726 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6727 fb->bits_per_pixel))
6728 return NULL;
6729
6730 if (obj->base.size < mode->vdisplay * fb->pitches[0])
6731 return NULL;
6732
6733 return fb;
6734 }
6735
6736 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6737 struct drm_display_mode *mode,
6738 struct intel_load_detect_pipe *old)
6739 {
6740 struct intel_crtc *intel_crtc;
6741 struct intel_encoder *intel_encoder =
6742 intel_attached_encoder(connector);
6743 struct drm_crtc *possible_crtc;
6744 struct drm_encoder *encoder = &intel_encoder->base;
6745 struct drm_crtc *crtc = NULL;
6746 struct drm_device *dev = encoder->dev;
6747 struct drm_framebuffer *fb;
6748 int i = -1;
6749
6750 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6751 connector->base.id, drm_get_connector_name(connector),
6752 encoder->base.id, drm_get_encoder_name(encoder));
6753
6754 /*
6755 * Algorithm gets a little messy:
6756 *
6757 * - if the connector already has an assigned crtc, use it (but make
6758 * sure it's on first)
6759 *
6760 * - try to find the first unused crtc that can drive this connector,
6761 * and use that if we find one
6762 */
6763
6764 /* See if we already have a CRTC for this connector */
6765 if (encoder->crtc) {
6766 crtc = encoder->crtc;
6767
6768 mutex_lock(&crtc->mutex);
6769
6770 old->dpms_mode = connector->dpms;
6771 old->load_detect_temp = false;
6772
6773 /* Make sure the crtc and connector are running */
6774 if (connector->dpms != DRM_MODE_DPMS_ON)
6775 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6776
6777 return true;
6778 }
6779
6780 /* Find an unused one (if possible) */
6781 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6782 i++;
6783 if (!(encoder->possible_crtcs & (1 << i)))
6784 continue;
6785 if (!possible_crtc->enabled) {
6786 crtc = possible_crtc;
6787 break;
6788 }
6789 }
6790
6791 /*
6792 * If we didn't find an unused CRTC, don't use any.
6793 */
6794 if (!crtc) {
6795 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6796 return false;
6797 }
6798
6799 mutex_lock(&crtc->mutex);
6800 intel_encoder->new_crtc = to_intel_crtc(crtc);
6801 to_intel_connector(connector)->new_encoder = intel_encoder;
6802
6803 intel_crtc = to_intel_crtc(crtc);
6804 old->dpms_mode = connector->dpms;
6805 old->load_detect_temp = true;
6806 old->release_fb = NULL;
6807
6808 if (!mode)
6809 mode = &load_detect_mode;
6810
6811 /* We need a framebuffer large enough to accommodate all accesses
6812 * that the plane may generate whilst we perform load detection.
6813 * We can not rely on the fbcon either being present (we get called
6814 * during its initialisation to detect all boot displays, or it may
6815 * not even exist) or that it is large enough to satisfy the
6816 * requested mode.
6817 */
6818 fb = mode_fits_in_fbdev(dev, mode);
6819 if (fb == NULL) {
6820 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6821 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6822 old->release_fb = fb;
6823 } else
6824 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6825 if (IS_ERR(fb)) {
6826 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6827 mutex_unlock(&crtc->mutex);
6828 return false;
6829 }
6830
6831 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6832 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6833 if (old->release_fb)
6834 old->release_fb->funcs->destroy(old->release_fb);
6835 mutex_unlock(&crtc->mutex);
6836 return false;
6837 }
6838
6839 /* let the connector get through one full cycle before testing */
6840 intel_wait_for_vblank(dev, intel_crtc->pipe);
6841 return true;
6842 }
6843
6844 void intel_release_load_detect_pipe(struct drm_connector *connector,
6845 struct intel_load_detect_pipe *old)
6846 {
6847 struct intel_encoder *intel_encoder =
6848 intel_attached_encoder(connector);
6849 struct drm_encoder *encoder = &intel_encoder->base;
6850 struct drm_crtc *crtc = encoder->crtc;
6851
6852 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6853 connector->base.id, drm_get_connector_name(connector),
6854 encoder->base.id, drm_get_encoder_name(encoder));
6855
6856 if (old->load_detect_temp) {
6857 to_intel_connector(connector)->new_encoder = NULL;
6858 intel_encoder->new_crtc = NULL;
6859 intel_set_mode(crtc, NULL, 0, 0, NULL);
6860
6861 if (old->release_fb) {
6862 drm_framebuffer_unregister_private(old->release_fb);
6863 drm_framebuffer_unreference(old->release_fb);
6864 }
6865
6866 mutex_unlock(&crtc->mutex);
6867 return;
6868 }
6869
6870 /* Switch crtc and encoder back off if necessary */
6871 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6872 connector->funcs->dpms(connector, old->dpms_mode);
6873
6874 mutex_unlock(&crtc->mutex);
6875 }
6876
6877 /* Returns the clock of the currently programmed mode of the given pipe. */
6878 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6879 {
6880 struct drm_i915_private *dev_priv = dev->dev_private;
6881 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6882 int pipe = intel_crtc->pipe;
6883 u32 dpll = I915_READ(DPLL(pipe));
6884 u32 fp;
6885 intel_clock_t clock;
6886
6887 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6888 fp = I915_READ(FP0(pipe));
6889 else
6890 fp = I915_READ(FP1(pipe));
6891
6892 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6893 if (IS_PINEVIEW(dev)) {
6894 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6895 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6896 } else {
6897 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6898 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6899 }
6900
6901 if (!IS_GEN2(dev)) {
6902 if (IS_PINEVIEW(dev))
6903 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6904 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6905 else
6906 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6907 DPLL_FPA01_P1_POST_DIV_SHIFT);
6908
6909 switch (dpll & DPLL_MODE_MASK) {
6910 case DPLLB_MODE_DAC_SERIAL:
6911 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6912 5 : 10;
6913 break;
6914 case DPLLB_MODE_LVDS:
6915 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6916 7 : 14;
6917 break;
6918 default:
6919 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6920 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6921 return 0;
6922 }
6923
6924 if (IS_PINEVIEW(dev))
6925 pineview_clock(96000, &clock);
6926 else
6927 i9xx_clock(96000, &clock);
6928 } else {
6929 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6930
6931 if (is_lvds) {
6932 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6933 DPLL_FPA01_P1_POST_DIV_SHIFT);
6934 clock.p2 = 14;
6935
6936 if ((dpll & PLL_REF_INPUT_MASK) ==
6937 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6938 /* XXX: might not be 66MHz */
6939 i9xx_clock(66000, &clock);
6940 } else
6941 i9xx_clock(48000, &clock);
6942 } else {
6943 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6944 clock.p1 = 2;
6945 else {
6946 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6947 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6948 }
6949 if (dpll & PLL_P2_DIVIDE_BY_4)
6950 clock.p2 = 4;
6951 else
6952 clock.p2 = 2;
6953
6954 i9xx_clock(48000, &clock);
6955 }
6956 }
6957
6958 /* XXX: It would be nice to validate the clocks, but we can't reuse
6959 * i830PllIsValid() because it relies on the xf86_config connector
6960 * configuration being accurate, which it isn't necessarily.
6961 */
6962
6963 return clock.dot;
6964 }
6965
6966 /** Returns the currently programmed mode of the given pipe. */
6967 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6968 struct drm_crtc *crtc)
6969 {
6970 struct drm_i915_private *dev_priv = dev->dev_private;
6971 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6972 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6973 struct drm_display_mode *mode;
6974 int htot = I915_READ(HTOTAL(cpu_transcoder));
6975 int hsync = I915_READ(HSYNC(cpu_transcoder));
6976 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6977 int vsync = I915_READ(VSYNC(cpu_transcoder));
6978
6979 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6980 if (!mode)
6981 return NULL;
6982
6983 mode->clock = intel_crtc_clock_get(dev, crtc);
6984 mode->hdisplay = (htot & 0xffff) + 1;
6985 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6986 mode->hsync_start = (hsync & 0xffff) + 1;
6987 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6988 mode->vdisplay = (vtot & 0xffff) + 1;
6989 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6990 mode->vsync_start = (vsync & 0xffff) + 1;
6991 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6992
6993 drm_mode_set_name(mode);
6994
6995 return mode;
6996 }
6997
6998 static void intel_increase_pllclock(struct drm_crtc *crtc)
6999 {
7000 struct drm_device *dev = crtc->dev;
7001 drm_i915_private_t *dev_priv = dev->dev_private;
7002 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7003 int pipe = intel_crtc->pipe;
7004 int dpll_reg = DPLL(pipe);
7005 int dpll;
7006
7007 if (HAS_PCH_SPLIT(dev))
7008 return;
7009
7010 if (!dev_priv->lvds_downclock_avail)
7011 return;
7012
7013 dpll = I915_READ(dpll_reg);
7014 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7015 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7016
7017 assert_panel_unlocked(dev_priv, pipe);
7018
7019 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7020 I915_WRITE(dpll_reg, dpll);
7021 intel_wait_for_vblank(dev, pipe);
7022
7023 dpll = I915_READ(dpll_reg);
7024 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7025 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7026 }
7027 }
7028
7029 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7030 {
7031 struct drm_device *dev = crtc->dev;
7032 drm_i915_private_t *dev_priv = dev->dev_private;
7033 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7034
7035 if (HAS_PCH_SPLIT(dev))
7036 return;
7037
7038 if (!dev_priv->lvds_downclock_avail)
7039 return;
7040
7041 /*
7042 * Since this is called by a timer, we should never get here in
7043 * the manual case.
7044 */
7045 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7046 int pipe = intel_crtc->pipe;
7047 int dpll_reg = DPLL(pipe);
7048 int dpll;
7049
7050 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7051
7052 assert_panel_unlocked(dev_priv, pipe);
7053
7054 dpll = I915_READ(dpll_reg);
7055 dpll |= DISPLAY_RATE_SELECT_FPA1;
7056 I915_WRITE(dpll_reg, dpll);
7057 intel_wait_for_vblank(dev, pipe);
7058 dpll = I915_READ(dpll_reg);
7059 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7060 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7061 }
7062
7063 }
7064
7065 void intel_mark_busy(struct drm_device *dev)
7066 {
7067 i915_update_gfx_val(dev->dev_private);
7068 }
7069
7070 void intel_mark_idle(struct drm_device *dev)
7071 {
7072 struct drm_crtc *crtc;
7073
7074 if (!i915_powersave)
7075 return;
7076
7077 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7078 if (!crtc->fb)
7079 continue;
7080
7081 intel_decrease_pllclock(crtc);
7082 }
7083 }
7084
7085 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7086 struct intel_ring_buffer *ring)
7087 {
7088 struct drm_device *dev = obj->base.dev;
7089 struct drm_crtc *crtc;
7090
7091 if (!i915_powersave)
7092 return;
7093
7094 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7095 if (!crtc->fb)
7096 continue;
7097
7098 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7099 continue;
7100
7101 intel_increase_pllclock(crtc);
7102 if (ring && intel_fbc_enabled(dev))
7103 ring->fbc_dirty = true;
7104 }
7105 }
7106
7107 static void intel_crtc_destroy(struct drm_crtc *crtc)
7108 {
7109 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7110 struct drm_device *dev = crtc->dev;
7111 struct intel_unpin_work *work;
7112 unsigned long flags;
7113
7114 spin_lock_irqsave(&dev->event_lock, flags);
7115 work = intel_crtc->unpin_work;
7116 intel_crtc->unpin_work = NULL;
7117 spin_unlock_irqrestore(&dev->event_lock, flags);
7118
7119 if (work) {
7120 cancel_work_sync(&work->work);
7121 kfree(work);
7122 }
7123
7124 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7125
7126 drm_crtc_cleanup(crtc);
7127
7128 kfree(intel_crtc);
7129 }
7130
7131 static void intel_unpin_work_fn(struct work_struct *__work)
7132 {
7133 struct intel_unpin_work *work =
7134 container_of(__work, struct intel_unpin_work, work);
7135 struct drm_device *dev = work->crtc->dev;
7136
7137 mutex_lock(&dev->struct_mutex);
7138 intel_unpin_fb_obj(work->old_fb_obj);
7139 drm_gem_object_unreference(&work->pending_flip_obj->base);
7140 drm_gem_object_unreference(&work->old_fb_obj->base);
7141
7142 intel_update_fbc(dev);
7143 mutex_unlock(&dev->struct_mutex);
7144
7145 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7146 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7147
7148 kfree(work);
7149 }
7150
7151 static void do_intel_finish_page_flip(struct drm_device *dev,
7152 struct drm_crtc *crtc)
7153 {
7154 drm_i915_private_t *dev_priv = dev->dev_private;
7155 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7156 struct intel_unpin_work *work;
7157 unsigned long flags;
7158
7159 /* Ignore early vblank irqs */
7160 if (intel_crtc == NULL)
7161 return;
7162
7163 spin_lock_irqsave(&dev->event_lock, flags);
7164 work = intel_crtc->unpin_work;
7165
7166 /* Ensure we don't miss a work->pending update ... */
7167 smp_rmb();
7168
7169 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7170 spin_unlock_irqrestore(&dev->event_lock, flags);
7171 return;
7172 }
7173
7174 /* and that the unpin work is consistent wrt ->pending. */
7175 smp_rmb();
7176
7177 intel_crtc->unpin_work = NULL;
7178
7179 if (work->event)
7180 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7181
7182 drm_vblank_put(dev, intel_crtc->pipe);
7183
7184 spin_unlock_irqrestore(&dev->event_lock, flags);
7185
7186 wake_up_all(&dev_priv->pending_flip_queue);
7187
7188 queue_work(dev_priv->wq, &work->work);
7189
7190 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7191 }
7192
7193 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7194 {
7195 drm_i915_private_t *dev_priv = dev->dev_private;
7196 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7197
7198 do_intel_finish_page_flip(dev, crtc);
7199 }
7200
7201 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7202 {
7203 drm_i915_private_t *dev_priv = dev->dev_private;
7204 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7205
7206 do_intel_finish_page_flip(dev, crtc);
7207 }
7208
7209 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7210 {
7211 drm_i915_private_t *dev_priv = dev->dev_private;
7212 struct intel_crtc *intel_crtc =
7213 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7214 unsigned long flags;
7215
7216 /* NB: An MMIO update of the plane base pointer will also
7217 * generate a page-flip completion irq, i.e. every modeset
7218 * is also accompanied by a spurious intel_prepare_page_flip().
7219 */
7220 spin_lock_irqsave(&dev->event_lock, flags);
7221 if (intel_crtc->unpin_work)
7222 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7223 spin_unlock_irqrestore(&dev->event_lock, flags);
7224 }
7225
7226 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7227 {
7228 /* Ensure that the work item is consistent when activating it ... */
7229 smp_wmb();
7230 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7231 /* and that it is marked active as soon as the irq could fire. */
7232 smp_wmb();
7233 }
7234
7235 static int intel_gen2_queue_flip(struct drm_device *dev,
7236 struct drm_crtc *crtc,
7237 struct drm_framebuffer *fb,
7238 struct drm_i915_gem_object *obj)
7239 {
7240 struct drm_i915_private *dev_priv = dev->dev_private;
7241 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7242 u32 flip_mask;
7243 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7244 int ret;
7245
7246 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7247 if (ret)
7248 goto err;
7249
7250 ret = intel_ring_begin(ring, 6);
7251 if (ret)
7252 goto err_unpin;
7253
7254 /* Can't queue multiple flips, so wait for the previous
7255 * one to finish before executing the next.
7256 */
7257 if (intel_crtc->plane)
7258 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7259 else
7260 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7261 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7262 intel_ring_emit(ring, MI_NOOP);
7263 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7264 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7265 intel_ring_emit(ring, fb->pitches[0]);
7266 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7267 intel_ring_emit(ring, 0); /* aux display base address, unused */
7268
7269 intel_mark_page_flip_active(intel_crtc);
7270 intel_ring_advance(ring);
7271 return 0;
7272
7273 err_unpin:
7274 intel_unpin_fb_obj(obj);
7275 err:
7276 return ret;
7277 }
7278
7279 static int intel_gen3_queue_flip(struct drm_device *dev,
7280 struct drm_crtc *crtc,
7281 struct drm_framebuffer *fb,
7282 struct drm_i915_gem_object *obj)
7283 {
7284 struct drm_i915_private *dev_priv = dev->dev_private;
7285 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7286 u32 flip_mask;
7287 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7288 int ret;
7289
7290 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7291 if (ret)
7292 goto err;
7293
7294 ret = intel_ring_begin(ring, 6);
7295 if (ret)
7296 goto err_unpin;
7297
7298 if (intel_crtc->plane)
7299 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7300 else
7301 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7302 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7303 intel_ring_emit(ring, MI_NOOP);
7304 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7305 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7306 intel_ring_emit(ring, fb->pitches[0]);
7307 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7308 intel_ring_emit(ring, MI_NOOP);
7309
7310 intel_mark_page_flip_active(intel_crtc);
7311 intel_ring_advance(ring);
7312 return 0;
7313
7314 err_unpin:
7315 intel_unpin_fb_obj(obj);
7316 err:
7317 return ret;
7318 }
7319
7320 static int intel_gen4_queue_flip(struct drm_device *dev,
7321 struct drm_crtc *crtc,
7322 struct drm_framebuffer *fb,
7323 struct drm_i915_gem_object *obj)
7324 {
7325 struct drm_i915_private *dev_priv = dev->dev_private;
7326 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7327 uint32_t pf, pipesrc;
7328 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7329 int ret;
7330
7331 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7332 if (ret)
7333 goto err;
7334
7335 ret = intel_ring_begin(ring, 4);
7336 if (ret)
7337 goto err_unpin;
7338
7339 /* i965+ uses the linear or tiled offsets from the
7340 * Display Registers (which do not change across a page-flip)
7341 * so we need only reprogram the base address.
7342 */
7343 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7344 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7345 intel_ring_emit(ring, fb->pitches[0]);
7346 intel_ring_emit(ring,
7347 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7348 obj->tiling_mode);
7349
7350 /* XXX Enabling the panel-fitter across page-flip is so far
7351 * untested on non-native modes, so ignore it for now.
7352 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7353 */
7354 pf = 0;
7355 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7356 intel_ring_emit(ring, pf | pipesrc);
7357
7358 intel_mark_page_flip_active(intel_crtc);
7359 intel_ring_advance(ring);
7360 return 0;
7361
7362 err_unpin:
7363 intel_unpin_fb_obj(obj);
7364 err:
7365 return ret;
7366 }
7367
7368 static int intel_gen6_queue_flip(struct drm_device *dev,
7369 struct drm_crtc *crtc,
7370 struct drm_framebuffer *fb,
7371 struct drm_i915_gem_object *obj)
7372 {
7373 struct drm_i915_private *dev_priv = dev->dev_private;
7374 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7375 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7376 uint32_t pf, pipesrc;
7377 int ret;
7378
7379 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7380 if (ret)
7381 goto err;
7382
7383 ret = intel_ring_begin(ring, 4);
7384 if (ret)
7385 goto err_unpin;
7386
7387 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7388 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7389 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7390 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7391
7392 /* Contrary to the suggestions in the documentation,
7393 * "Enable Panel Fitter" does not seem to be required when page
7394 * flipping with a non-native mode, and worse causes a normal
7395 * modeset to fail.
7396 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7397 */
7398 pf = 0;
7399 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7400 intel_ring_emit(ring, pf | pipesrc);
7401
7402 intel_mark_page_flip_active(intel_crtc);
7403 intel_ring_advance(ring);
7404 return 0;
7405
7406 err_unpin:
7407 intel_unpin_fb_obj(obj);
7408 err:
7409 return ret;
7410 }
7411
7412 /*
7413 * On gen7 we currently use the blit ring because (in early silicon at least)
7414 * the render ring doesn't give us interrpts for page flip completion, which
7415 * means clients will hang after the first flip is queued. Fortunately the
7416 * blit ring generates interrupts properly, so use it instead.
7417 */
7418 static int intel_gen7_queue_flip(struct drm_device *dev,
7419 struct drm_crtc *crtc,
7420 struct drm_framebuffer *fb,
7421 struct drm_i915_gem_object *obj)
7422 {
7423 struct drm_i915_private *dev_priv = dev->dev_private;
7424 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7425 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7426 uint32_t plane_bit = 0;
7427 int ret;
7428
7429 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7430 if (ret)
7431 goto err;
7432
7433 switch(intel_crtc->plane) {
7434 case PLANE_A:
7435 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7436 break;
7437 case PLANE_B:
7438 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7439 break;
7440 case PLANE_C:
7441 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7442 break;
7443 default:
7444 WARN_ONCE(1, "unknown plane in flip command\n");
7445 ret = -ENODEV;
7446 goto err_unpin;
7447 }
7448
7449 ret = intel_ring_begin(ring, 4);
7450 if (ret)
7451 goto err_unpin;
7452
7453 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7454 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7455 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7456 intel_ring_emit(ring, (MI_NOOP));
7457
7458 intel_mark_page_flip_active(intel_crtc);
7459 intel_ring_advance(ring);
7460 return 0;
7461
7462 err_unpin:
7463 intel_unpin_fb_obj(obj);
7464 err:
7465 return ret;
7466 }
7467
7468 static int intel_default_queue_flip(struct drm_device *dev,
7469 struct drm_crtc *crtc,
7470 struct drm_framebuffer *fb,
7471 struct drm_i915_gem_object *obj)
7472 {
7473 return -ENODEV;
7474 }
7475
7476 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7477 struct drm_framebuffer *fb,
7478 struct drm_pending_vblank_event *event)
7479 {
7480 struct drm_device *dev = crtc->dev;
7481 struct drm_i915_private *dev_priv = dev->dev_private;
7482 struct drm_framebuffer *old_fb = crtc->fb;
7483 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7484 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7485 struct intel_unpin_work *work;
7486 unsigned long flags;
7487 int ret;
7488
7489 /* Can't change pixel format via MI display flips. */
7490 if (fb->pixel_format != crtc->fb->pixel_format)
7491 return -EINVAL;
7492
7493 /*
7494 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7495 * Note that pitch changes could also affect these register.
7496 */
7497 if (INTEL_INFO(dev)->gen > 3 &&
7498 (fb->offsets[0] != crtc->fb->offsets[0] ||
7499 fb->pitches[0] != crtc->fb->pitches[0]))
7500 return -EINVAL;
7501
7502 work = kzalloc(sizeof *work, GFP_KERNEL);
7503 if (work == NULL)
7504 return -ENOMEM;
7505
7506 work->event = event;
7507 work->crtc = crtc;
7508 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7509 INIT_WORK(&work->work, intel_unpin_work_fn);
7510
7511 ret = drm_vblank_get(dev, intel_crtc->pipe);
7512 if (ret)
7513 goto free_work;
7514
7515 /* We borrow the event spin lock for protecting unpin_work */
7516 spin_lock_irqsave(&dev->event_lock, flags);
7517 if (intel_crtc->unpin_work) {
7518 spin_unlock_irqrestore(&dev->event_lock, flags);
7519 kfree(work);
7520 drm_vblank_put(dev, intel_crtc->pipe);
7521
7522 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7523 return -EBUSY;
7524 }
7525 intel_crtc->unpin_work = work;
7526 spin_unlock_irqrestore(&dev->event_lock, flags);
7527
7528 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7529 flush_workqueue(dev_priv->wq);
7530
7531 ret = i915_mutex_lock_interruptible(dev);
7532 if (ret)
7533 goto cleanup;
7534
7535 /* Reference the objects for the scheduled work. */
7536 drm_gem_object_reference(&work->old_fb_obj->base);
7537 drm_gem_object_reference(&obj->base);
7538
7539 crtc->fb = fb;
7540
7541 work->pending_flip_obj = obj;
7542
7543 work->enable_stall_check = true;
7544
7545 atomic_inc(&intel_crtc->unpin_work_count);
7546 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7547
7548 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7549 if (ret)
7550 goto cleanup_pending;
7551
7552 intel_disable_fbc(dev);
7553 intel_mark_fb_busy(obj, NULL);
7554 mutex_unlock(&dev->struct_mutex);
7555
7556 trace_i915_flip_request(intel_crtc->plane, obj);
7557
7558 return 0;
7559
7560 cleanup_pending:
7561 atomic_dec(&intel_crtc->unpin_work_count);
7562 crtc->fb = old_fb;
7563 drm_gem_object_unreference(&work->old_fb_obj->base);
7564 drm_gem_object_unreference(&obj->base);
7565 mutex_unlock(&dev->struct_mutex);
7566
7567 cleanup:
7568 spin_lock_irqsave(&dev->event_lock, flags);
7569 intel_crtc->unpin_work = NULL;
7570 spin_unlock_irqrestore(&dev->event_lock, flags);
7571
7572 drm_vblank_put(dev, intel_crtc->pipe);
7573 free_work:
7574 kfree(work);
7575
7576 return ret;
7577 }
7578
7579 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7580 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7581 .load_lut = intel_crtc_load_lut,
7582 };
7583
7584 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7585 struct drm_crtc *crtc)
7586 {
7587 struct drm_device *dev;
7588 struct drm_crtc *tmp;
7589 int crtc_mask = 1;
7590
7591 WARN(!crtc, "checking null crtc?\n");
7592
7593 dev = crtc->dev;
7594
7595 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7596 if (tmp == crtc)
7597 break;
7598 crtc_mask <<= 1;
7599 }
7600
7601 if (encoder->possible_crtcs & crtc_mask)
7602 return true;
7603 return false;
7604 }
7605
7606 /**
7607 * intel_modeset_update_staged_output_state
7608 *
7609 * Updates the staged output configuration state, e.g. after we've read out the
7610 * current hw state.
7611 */
7612 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7613 {
7614 struct intel_encoder *encoder;
7615 struct intel_connector *connector;
7616
7617 list_for_each_entry(connector, &dev->mode_config.connector_list,
7618 base.head) {
7619 connector->new_encoder =
7620 to_intel_encoder(connector->base.encoder);
7621 }
7622
7623 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7624 base.head) {
7625 encoder->new_crtc =
7626 to_intel_crtc(encoder->base.crtc);
7627 }
7628 }
7629
7630 /**
7631 * intel_modeset_commit_output_state
7632 *
7633 * This function copies the stage display pipe configuration to the real one.
7634 */
7635 static void intel_modeset_commit_output_state(struct drm_device *dev)
7636 {
7637 struct intel_encoder *encoder;
7638 struct intel_connector *connector;
7639
7640 list_for_each_entry(connector, &dev->mode_config.connector_list,
7641 base.head) {
7642 connector->base.encoder = &connector->new_encoder->base;
7643 }
7644
7645 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7646 base.head) {
7647 encoder->base.crtc = &encoder->new_crtc->base;
7648 }
7649 }
7650
7651 static void
7652 connected_sink_compute_bpp(struct intel_connector * connector,
7653 struct intel_crtc_config *pipe_config)
7654 {
7655 int bpp = pipe_config->pipe_bpp;
7656
7657 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7658 connector->base.base.id,
7659 drm_get_connector_name(&connector->base));
7660
7661 /* Don't use an invalid EDID bpc value */
7662 if (connector->base.display_info.bpc &&
7663 connector->base.display_info.bpc * 3 < bpp) {
7664 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7665 bpp, connector->base.display_info.bpc*3);
7666 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7667 }
7668
7669 /* Clamp bpp to 8 on screens without EDID 1.4 */
7670 if (connector->base.display_info.bpc == 0 && bpp > 24) {
7671 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7672 bpp);
7673 pipe_config->pipe_bpp = 24;
7674 }
7675 }
7676
7677 static int
7678 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7679 struct drm_framebuffer *fb,
7680 struct intel_crtc_config *pipe_config)
7681 {
7682 struct drm_device *dev = crtc->base.dev;
7683 struct intel_connector *connector;
7684 int bpp;
7685
7686 switch (fb->pixel_format) {
7687 case DRM_FORMAT_C8:
7688 bpp = 8*3; /* since we go through a colormap */
7689 break;
7690 case DRM_FORMAT_XRGB1555:
7691 case DRM_FORMAT_ARGB1555:
7692 /* checked in intel_framebuffer_init already */
7693 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7694 return -EINVAL;
7695 case DRM_FORMAT_RGB565:
7696 bpp = 6*3; /* min is 18bpp */
7697 break;
7698 case DRM_FORMAT_XBGR8888:
7699 case DRM_FORMAT_ABGR8888:
7700 /* checked in intel_framebuffer_init already */
7701 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7702 return -EINVAL;
7703 case DRM_FORMAT_XRGB8888:
7704 case DRM_FORMAT_ARGB8888:
7705 bpp = 8*3;
7706 break;
7707 case DRM_FORMAT_XRGB2101010:
7708 case DRM_FORMAT_ARGB2101010:
7709 case DRM_FORMAT_XBGR2101010:
7710 case DRM_FORMAT_ABGR2101010:
7711 /* checked in intel_framebuffer_init already */
7712 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7713 return -EINVAL;
7714 bpp = 10*3;
7715 break;
7716 /* TODO: gen4+ supports 16 bpc floating point, too. */
7717 default:
7718 DRM_DEBUG_KMS("unsupported depth\n");
7719 return -EINVAL;
7720 }
7721
7722 pipe_config->pipe_bpp = bpp;
7723
7724 /* Clamp display bpp to EDID value */
7725 list_for_each_entry(connector, &dev->mode_config.connector_list,
7726 base.head) {
7727 if (!connector->new_encoder ||
7728 connector->new_encoder->new_crtc != crtc)
7729 continue;
7730
7731 connected_sink_compute_bpp(connector, pipe_config);
7732 }
7733
7734 return bpp;
7735 }
7736
7737 static void intel_dump_pipe_config(struct intel_crtc *crtc,
7738 struct intel_crtc_config *pipe_config,
7739 const char *context)
7740 {
7741 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7742 context, pipe_name(crtc->pipe));
7743
7744 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
7745 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7746 pipe_config->pipe_bpp, pipe_config->dither);
7747 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7748 pipe_config->has_pch_encoder,
7749 pipe_config->fdi_lanes,
7750 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
7751 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
7752 pipe_config->fdi_m_n.tu);
7753 DRM_DEBUG_KMS("requested mode:\n");
7754 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
7755 DRM_DEBUG_KMS("adjusted mode:\n");
7756 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
7757 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7758 pipe_config->gmch_pfit.control,
7759 pipe_config->gmch_pfit.pgm_ratios,
7760 pipe_config->gmch_pfit.lvds_border_bits);
7761 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
7762 pipe_config->pch_pfit.pos,
7763 pipe_config->pch_pfit.size);
7764 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
7765 }
7766
7767 static bool check_encoder_cloning(struct drm_crtc *crtc)
7768 {
7769 int num_encoders = 0;
7770 bool uncloneable_encoders = false;
7771 struct intel_encoder *encoder;
7772
7773 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
7774 base.head) {
7775 if (&encoder->new_crtc->base != crtc)
7776 continue;
7777
7778 num_encoders++;
7779 if (!encoder->cloneable)
7780 uncloneable_encoders = true;
7781 }
7782
7783 return !(num_encoders > 1 && uncloneable_encoders);
7784 }
7785
7786 static struct intel_crtc_config *
7787 intel_modeset_pipe_config(struct drm_crtc *crtc,
7788 struct drm_framebuffer *fb,
7789 struct drm_display_mode *mode)
7790 {
7791 struct drm_device *dev = crtc->dev;
7792 struct drm_encoder_helper_funcs *encoder_funcs;
7793 struct intel_encoder *encoder;
7794 struct intel_crtc_config *pipe_config;
7795 int plane_bpp, ret = -EINVAL;
7796 bool retry = true;
7797
7798 if (!check_encoder_cloning(crtc)) {
7799 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
7800 return ERR_PTR(-EINVAL);
7801 }
7802
7803 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7804 if (!pipe_config)
7805 return ERR_PTR(-ENOMEM);
7806
7807 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7808 drm_mode_copy(&pipe_config->requested_mode, mode);
7809 pipe_config->cpu_transcoder = to_intel_crtc(crtc)->pipe;
7810 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7811
7812 /* Compute a starting value for pipe_config->pipe_bpp taking the source
7813 * plane pixel format and any sink constraints into account. Returns the
7814 * source plane bpp so that dithering can be selected on mismatches
7815 * after encoders and crtc also have had their say. */
7816 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
7817 fb, pipe_config);
7818 if (plane_bpp < 0)
7819 goto fail;
7820
7821 encoder_retry:
7822 /* Ensure the port clock defaults are reset when retrying. */
7823 pipe_config->port_clock = 0;
7824 pipe_config->pixel_multiplier = 1;
7825
7826 /* Pass our mode to the connectors and the CRTC to give them a chance to
7827 * adjust it according to limitations or connector properties, and also
7828 * a chance to reject the mode entirely.
7829 */
7830 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7831 base.head) {
7832
7833 if (&encoder->new_crtc->base != crtc)
7834 continue;
7835
7836 if (encoder->compute_config) {
7837 if (!(encoder->compute_config(encoder, pipe_config))) {
7838 DRM_DEBUG_KMS("Encoder config failure\n");
7839 goto fail;
7840 }
7841
7842 continue;
7843 }
7844
7845 encoder_funcs = encoder->base.helper_private;
7846 if (!(encoder_funcs->mode_fixup(&encoder->base,
7847 &pipe_config->requested_mode,
7848 &pipe_config->adjusted_mode))) {
7849 DRM_DEBUG_KMS("Encoder fixup failed\n");
7850 goto fail;
7851 }
7852 }
7853
7854 /* Set default port clock if not overwritten by the encoder. Needs to be
7855 * done afterwards in case the encoder adjusts the mode. */
7856 if (!pipe_config->port_clock)
7857 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
7858
7859 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
7860 if (ret < 0) {
7861 DRM_DEBUG_KMS("CRTC fixup failed\n");
7862 goto fail;
7863 }
7864
7865 if (ret == RETRY) {
7866 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7867 ret = -EINVAL;
7868 goto fail;
7869 }
7870
7871 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7872 retry = false;
7873 goto encoder_retry;
7874 }
7875
7876 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7877 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7878 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7879
7880 return pipe_config;
7881 fail:
7882 kfree(pipe_config);
7883 return ERR_PTR(ret);
7884 }
7885
7886 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7887 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7888 static void
7889 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7890 unsigned *prepare_pipes, unsigned *disable_pipes)
7891 {
7892 struct intel_crtc *intel_crtc;
7893 struct drm_device *dev = crtc->dev;
7894 struct intel_encoder *encoder;
7895 struct intel_connector *connector;
7896 struct drm_crtc *tmp_crtc;
7897
7898 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7899
7900 /* Check which crtcs have changed outputs connected to them, these need
7901 * to be part of the prepare_pipes mask. We don't (yet) support global
7902 * modeset across multiple crtcs, so modeset_pipes will only have one
7903 * bit set at most. */
7904 list_for_each_entry(connector, &dev->mode_config.connector_list,
7905 base.head) {
7906 if (connector->base.encoder == &connector->new_encoder->base)
7907 continue;
7908
7909 if (connector->base.encoder) {
7910 tmp_crtc = connector->base.encoder->crtc;
7911
7912 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7913 }
7914
7915 if (connector->new_encoder)
7916 *prepare_pipes |=
7917 1 << connector->new_encoder->new_crtc->pipe;
7918 }
7919
7920 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7921 base.head) {
7922 if (encoder->base.crtc == &encoder->new_crtc->base)
7923 continue;
7924
7925 if (encoder->base.crtc) {
7926 tmp_crtc = encoder->base.crtc;
7927
7928 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7929 }
7930
7931 if (encoder->new_crtc)
7932 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7933 }
7934
7935 /* Check for any pipes that will be fully disabled ... */
7936 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7937 base.head) {
7938 bool used = false;
7939
7940 /* Don't try to disable disabled crtcs. */
7941 if (!intel_crtc->base.enabled)
7942 continue;
7943
7944 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7945 base.head) {
7946 if (encoder->new_crtc == intel_crtc)
7947 used = true;
7948 }
7949
7950 if (!used)
7951 *disable_pipes |= 1 << intel_crtc->pipe;
7952 }
7953
7954
7955 /* set_mode is also used to update properties on life display pipes. */
7956 intel_crtc = to_intel_crtc(crtc);
7957 if (crtc->enabled)
7958 *prepare_pipes |= 1 << intel_crtc->pipe;
7959
7960 /*
7961 * For simplicity do a full modeset on any pipe where the output routing
7962 * changed. We could be more clever, but that would require us to be
7963 * more careful with calling the relevant encoder->mode_set functions.
7964 */
7965 if (*prepare_pipes)
7966 *modeset_pipes = *prepare_pipes;
7967
7968 /* ... and mask these out. */
7969 *modeset_pipes &= ~(*disable_pipes);
7970 *prepare_pipes &= ~(*disable_pipes);
7971
7972 /*
7973 * HACK: We don't (yet) fully support global modesets. intel_set_config
7974 * obies this rule, but the modeset restore mode of
7975 * intel_modeset_setup_hw_state does not.
7976 */
7977 *modeset_pipes &= 1 << intel_crtc->pipe;
7978 *prepare_pipes &= 1 << intel_crtc->pipe;
7979
7980 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7981 *modeset_pipes, *prepare_pipes, *disable_pipes);
7982 }
7983
7984 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7985 {
7986 struct drm_encoder *encoder;
7987 struct drm_device *dev = crtc->dev;
7988
7989 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7990 if (encoder->crtc == crtc)
7991 return true;
7992
7993 return false;
7994 }
7995
7996 static void
7997 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7998 {
7999 struct intel_encoder *intel_encoder;
8000 struct intel_crtc *intel_crtc;
8001 struct drm_connector *connector;
8002
8003 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8004 base.head) {
8005 if (!intel_encoder->base.crtc)
8006 continue;
8007
8008 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8009
8010 if (prepare_pipes & (1 << intel_crtc->pipe))
8011 intel_encoder->connectors_active = false;
8012 }
8013
8014 intel_modeset_commit_output_state(dev);
8015
8016 /* Update computed state. */
8017 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8018 base.head) {
8019 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8020 }
8021
8022 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8023 if (!connector->encoder || !connector->encoder->crtc)
8024 continue;
8025
8026 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8027
8028 if (prepare_pipes & (1 << intel_crtc->pipe)) {
8029 struct drm_property *dpms_property =
8030 dev->mode_config.dpms_property;
8031
8032 connector->dpms = DRM_MODE_DPMS_ON;
8033 drm_object_property_set_value(&connector->base,
8034 dpms_property,
8035 DRM_MODE_DPMS_ON);
8036
8037 intel_encoder = to_intel_encoder(connector->encoder);
8038 intel_encoder->connectors_active = true;
8039 }
8040 }
8041
8042 }
8043
8044 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8045 list_for_each_entry((intel_crtc), \
8046 &(dev)->mode_config.crtc_list, \
8047 base.head) \
8048 if (mask & (1 <<(intel_crtc)->pipe))
8049
8050 static bool
8051 intel_pipe_config_compare(struct drm_device *dev,
8052 struct intel_crtc_config *current_config,
8053 struct intel_crtc_config *pipe_config)
8054 {
8055 #define PIPE_CONF_CHECK_X(name) \
8056 if (current_config->name != pipe_config->name) { \
8057 DRM_ERROR("mismatch in " #name " " \
8058 "(expected 0x%08x, found 0x%08x)\n", \
8059 current_config->name, \
8060 pipe_config->name); \
8061 return false; \
8062 }
8063
8064 #define PIPE_CONF_CHECK_I(name) \
8065 if (current_config->name != pipe_config->name) { \
8066 DRM_ERROR("mismatch in " #name " " \
8067 "(expected %i, found %i)\n", \
8068 current_config->name, \
8069 pipe_config->name); \
8070 return false; \
8071 }
8072
8073 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
8074 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8075 DRM_ERROR("mismatch in " #name " " \
8076 "(expected %i, found %i)\n", \
8077 current_config->name & (mask), \
8078 pipe_config->name & (mask)); \
8079 return false; \
8080 }
8081
8082 #define PIPE_CONF_QUIRK(quirk) \
8083 ((current_config->quirks | pipe_config->quirks) & (quirk))
8084
8085 PIPE_CONF_CHECK_I(cpu_transcoder);
8086
8087 PIPE_CONF_CHECK_I(has_pch_encoder);
8088 PIPE_CONF_CHECK_I(fdi_lanes);
8089 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8090 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8091 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8092 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8093 PIPE_CONF_CHECK_I(fdi_m_n.tu);
8094
8095 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8096 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8097 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8098 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8099 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8100 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8101
8102 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8103 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8104 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8105 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8106 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8107 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8108
8109 if (!HAS_PCH_SPLIT(dev))
8110 PIPE_CONF_CHECK_I(pixel_multiplier);
8111
8112 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8113 DRM_MODE_FLAG_INTERLACE);
8114
8115 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8116 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8117 DRM_MODE_FLAG_PHSYNC);
8118 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8119 DRM_MODE_FLAG_NHSYNC);
8120 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8121 DRM_MODE_FLAG_PVSYNC);
8122 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8123 DRM_MODE_FLAG_NVSYNC);
8124 }
8125
8126 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8127 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8128
8129 PIPE_CONF_CHECK_I(gmch_pfit.control);
8130 /* pfit ratios are autocomputed by the hw on gen4+ */
8131 if (INTEL_INFO(dev)->gen < 4)
8132 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8133 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8134 PIPE_CONF_CHECK_I(pch_pfit.pos);
8135 PIPE_CONF_CHECK_I(pch_pfit.size);
8136
8137 PIPE_CONF_CHECK_I(ips_enabled);
8138
8139 PIPE_CONF_CHECK_I(shared_dpll);
8140 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8141 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8142 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
8143
8144 #undef PIPE_CONF_CHECK_X
8145 #undef PIPE_CONF_CHECK_I
8146 #undef PIPE_CONF_CHECK_FLAGS
8147 #undef PIPE_CONF_QUIRK
8148
8149 return true;
8150 }
8151
8152 static void
8153 check_connector_state(struct drm_device *dev)
8154 {
8155 struct intel_connector *connector;
8156
8157 list_for_each_entry(connector, &dev->mode_config.connector_list,
8158 base.head) {
8159 /* This also checks the encoder/connector hw state with the
8160 * ->get_hw_state callbacks. */
8161 intel_connector_check_state(connector);
8162
8163 WARN(&connector->new_encoder->base != connector->base.encoder,
8164 "connector's staged encoder doesn't match current encoder\n");
8165 }
8166 }
8167
8168 static void
8169 check_encoder_state(struct drm_device *dev)
8170 {
8171 struct intel_encoder *encoder;
8172 struct intel_connector *connector;
8173
8174 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8175 base.head) {
8176 bool enabled = false;
8177 bool active = false;
8178 enum pipe pipe, tracked_pipe;
8179
8180 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8181 encoder->base.base.id,
8182 drm_get_encoder_name(&encoder->base));
8183
8184 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8185 "encoder's stage crtc doesn't match current crtc\n");
8186 WARN(encoder->connectors_active && !encoder->base.crtc,
8187 "encoder's active_connectors set, but no crtc\n");
8188
8189 list_for_each_entry(connector, &dev->mode_config.connector_list,
8190 base.head) {
8191 if (connector->base.encoder != &encoder->base)
8192 continue;
8193 enabled = true;
8194 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8195 active = true;
8196 }
8197 WARN(!!encoder->base.crtc != enabled,
8198 "encoder's enabled state mismatch "
8199 "(expected %i, found %i)\n",
8200 !!encoder->base.crtc, enabled);
8201 WARN(active && !encoder->base.crtc,
8202 "active encoder with no crtc\n");
8203
8204 WARN(encoder->connectors_active != active,
8205 "encoder's computed active state doesn't match tracked active state "
8206 "(expected %i, found %i)\n", active, encoder->connectors_active);
8207
8208 active = encoder->get_hw_state(encoder, &pipe);
8209 WARN(active != encoder->connectors_active,
8210 "encoder's hw state doesn't match sw tracking "
8211 "(expected %i, found %i)\n",
8212 encoder->connectors_active, active);
8213
8214 if (!encoder->base.crtc)
8215 continue;
8216
8217 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8218 WARN(active && pipe != tracked_pipe,
8219 "active encoder's pipe doesn't match"
8220 "(expected %i, found %i)\n",
8221 tracked_pipe, pipe);
8222
8223 }
8224 }
8225
8226 static void
8227 check_crtc_state(struct drm_device *dev)
8228 {
8229 drm_i915_private_t *dev_priv = dev->dev_private;
8230 struct intel_crtc *crtc;
8231 struct intel_encoder *encoder;
8232 struct intel_crtc_config pipe_config;
8233
8234 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8235 base.head) {
8236 bool enabled = false;
8237 bool active = false;
8238
8239 memset(&pipe_config, 0, sizeof(pipe_config));
8240
8241 DRM_DEBUG_KMS("[CRTC:%d]\n",
8242 crtc->base.base.id);
8243
8244 WARN(crtc->active && !crtc->base.enabled,
8245 "active crtc, but not enabled in sw tracking\n");
8246
8247 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8248 base.head) {
8249 if (encoder->base.crtc != &crtc->base)
8250 continue;
8251 enabled = true;
8252 if (encoder->connectors_active)
8253 active = true;
8254 }
8255
8256 WARN(active != crtc->active,
8257 "crtc's computed active state doesn't match tracked active state "
8258 "(expected %i, found %i)\n", active, crtc->active);
8259 WARN(enabled != crtc->base.enabled,
8260 "crtc's computed enabled state doesn't match tracked enabled state "
8261 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8262
8263 active = dev_priv->display.get_pipe_config(crtc,
8264 &pipe_config);
8265
8266 /* hw state is inconsistent with the pipe A quirk */
8267 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8268 active = crtc->active;
8269
8270 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8271 base.head) {
8272 if (encoder->base.crtc != &crtc->base)
8273 continue;
8274 if (encoder->get_config)
8275 encoder->get_config(encoder, &pipe_config);
8276 }
8277
8278 WARN(crtc->active != active,
8279 "crtc active state doesn't match with hw state "
8280 "(expected %i, found %i)\n", crtc->active, active);
8281
8282 if (active &&
8283 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8284 WARN(1, "pipe state doesn't match!\n");
8285 intel_dump_pipe_config(crtc, &pipe_config,
8286 "[hw state]");
8287 intel_dump_pipe_config(crtc, &crtc->config,
8288 "[sw state]");
8289 }
8290 }
8291 }
8292
8293 static void
8294 check_shared_dpll_state(struct drm_device *dev)
8295 {
8296 drm_i915_private_t *dev_priv = dev->dev_private;
8297 struct intel_crtc *crtc;
8298 struct intel_dpll_hw_state dpll_hw_state;
8299 int i;
8300
8301 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8302 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8303 int enabled_crtcs = 0, active_crtcs = 0;
8304 bool active;
8305
8306 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8307
8308 DRM_DEBUG_KMS("%s\n", pll->name);
8309
8310 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8311
8312 WARN(pll->active > pll->refcount,
8313 "more active pll users than references: %i vs %i\n",
8314 pll->active, pll->refcount);
8315 WARN(pll->active && !pll->on,
8316 "pll in active use but not on in sw tracking\n");
8317 WARN(pll->on && !pll->active,
8318 "pll in on but not on in use in sw tracking\n");
8319 WARN(pll->on != active,
8320 "pll on state mismatch (expected %i, found %i)\n",
8321 pll->on, active);
8322
8323 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8324 base.head) {
8325 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8326 enabled_crtcs++;
8327 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8328 active_crtcs++;
8329 }
8330 WARN(pll->active != active_crtcs,
8331 "pll active crtcs mismatch (expected %i, found %i)\n",
8332 pll->active, active_crtcs);
8333 WARN(pll->refcount != enabled_crtcs,
8334 "pll enabled crtcs mismatch (expected %i, found %i)\n",
8335 pll->refcount, enabled_crtcs);
8336
8337 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8338 sizeof(dpll_hw_state)),
8339 "pll hw state mismatch\n");
8340 }
8341 }
8342
8343 void
8344 intel_modeset_check_state(struct drm_device *dev)
8345 {
8346 check_connector_state(dev);
8347 check_encoder_state(dev);
8348 check_crtc_state(dev);
8349 check_shared_dpll_state(dev);
8350 }
8351
8352 static int __intel_set_mode(struct drm_crtc *crtc,
8353 struct drm_display_mode *mode,
8354 int x, int y, struct drm_framebuffer *fb)
8355 {
8356 struct drm_device *dev = crtc->dev;
8357 drm_i915_private_t *dev_priv = dev->dev_private;
8358 struct drm_display_mode *saved_mode, *saved_hwmode;
8359 struct intel_crtc_config *pipe_config = NULL;
8360 struct intel_crtc *intel_crtc;
8361 unsigned disable_pipes, prepare_pipes, modeset_pipes;
8362 int ret = 0;
8363
8364 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
8365 if (!saved_mode)
8366 return -ENOMEM;
8367 saved_hwmode = saved_mode + 1;
8368
8369 intel_modeset_affected_pipes(crtc, &modeset_pipes,
8370 &prepare_pipes, &disable_pipes);
8371
8372 *saved_hwmode = crtc->hwmode;
8373 *saved_mode = crtc->mode;
8374
8375 /* Hack: Because we don't (yet) support global modeset on multiple
8376 * crtcs, we don't keep track of the new mode for more than one crtc.
8377 * Hence simply check whether any bit is set in modeset_pipes in all the
8378 * pieces of code that are not yet converted to deal with mutliple crtcs
8379 * changing their mode at the same time. */
8380 if (modeset_pipes) {
8381 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
8382 if (IS_ERR(pipe_config)) {
8383 ret = PTR_ERR(pipe_config);
8384 pipe_config = NULL;
8385
8386 goto out;
8387 }
8388 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8389 "[modeset]");
8390 }
8391
8392 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8393 intel_crtc_disable(&intel_crtc->base);
8394
8395 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8396 if (intel_crtc->base.enabled)
8397 dev_priv->display.crtc_disable(&intel_crtc->base);
8398 }
8399
8400 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8401 * to set it here already despite that we pass it down the callchain.
8402 */
8403 if (modeset_pipes) {
8404 crtc->mode = *mode;
8405 /* mode_set/enable/disable functions rely on a correct pipe
8406 * config. */
8407 to_intel_crtc(crtc)->config = *pipe_config;
8408 }
8409
8410 /* Only after disabling all output pipelines that will be changed can we
8411 * update the the output configuration. */
8412 intel_modeset_update_state(dev, prepare_pipes);
8413
8414 if (dev_priv->display.modeset_global_resources)
8415 dev_priv->display.modeset_global_resources(dev);
8416
8417 /* Set up the DPLL and any encoders state that needs to adjust or depend
8418 * on the DPLL.
8419 */
8420 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
8421 ret = intel_crtc_mode_set(&intel_crtc->base,
8422 x, y, fb);
8423 if (ret)
8424 goto done;
8425 }
8426
8427 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8428 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8429 dev_priv->display.crtc_enable(&intel_crtc->base);
8430
8431 if (modeset_pipes) {
8432 /* Store real post-adjustment hardware mode. */
8433 crtc->hwmode = pipe_config->adjusted_mode;
8434
8435 /* Calculate and store various constants which
8436 * are later needed by vblank and swap-completion
8437 * timestamping. They are derived from true hwmode.
8438 */
8439 drm_calc_timestamping_constants(crtc);
8440 }
8441
8442 /* FIXME: add subpixel order */
8443 done:
8444 if (ret && crtc->enabled) {
8445 crtc->hwmode = *saved_hwmode;
8446 crtc->mode = *saved_mode;
8447 }
8448
8449 out:
8450 kfree(pipe_config);
8451 kfree(saved_mode);
8452 return ret;
8453 }
8454
8455 int intel_set_mode(struct drm_crtc *crtc,
8456 struct drm_display_mode *mode,
8457 int x, int y, struct drm_framebuffer *fb)
8458 {
8459 int ret;
8460
8461 ret = __intel_set_mode(crtc, mode, x, y, fb);
8462
8463 if (ret == 0)
8464 intel_modeset_check_state(crtc->dev);
8465
8466 return ret;
8467 }
8468
8469 void intel_crtc_restore_mode(struct drm_crtc *crtc)
8470 {
8471 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8472 }
8473
8474 #undef for_each_intel_crtc_masked
8475
8476 static void intel_set_config_free(struct intel_set_config *config)
8477 {
8478 if (!config)
8479 return;
8480
8481 kfree(config->save_connector_encoders);
8482 kfree(config->save_encoder_crtcs);
8483 kfree(config);
8484 }
8485
8486 static int intel_set_config_save_state(struct drm_device *dev,
8487 struct intel_set_config *config)
8488 {
8489 struct drm_encoder *encoder;
8490 struct drm_connector *connector;
8491 int count;
8492
8493 config->save_encoder_crtcs =
8494 kcalloc(dev->mode_config.num_encoder,
8495 sizeof(struct drm_crtc *), GFP_KERNEL);
8496 if (!config->save_encoder_crtcs)
8497 return -ENOMEM;
8498
8499 config->save_connector_encoders =
8500 kcalloc(dev->mode_config.num_connector,
8501 sizeof(struct drm_encoder *), GFP_KERNEL);
8502 if (!config->save_connector_encoders)
8503 return -ENOMEM;
8504
8505 /* Copy data. Note that driver private data is not affected.
8506 * Should anything bad happen only the expected state is
8507 * restored, not the drivers personal bookkeeping.
8508 */
8509 count = 0;
8510 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
8511 config->save_encoder_crtcs[count++] = encoder->crtc;
8512 }
8513
8514 count = 0;
8515 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8516 config->save_connector_encoders[count++] = connector->encoder;
8517 }
8518
8519 return 0;
8520 }
8521
8522 static void intel_set_config_restore_state(struct drm_device *dev,
8523 struct intel_set_config *config)
8524 {
8525 struct intel_encoder *encoder;
8526 struct intel_connector *connector;
8527 int count;
8528
8529 count = 0;
8530 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8531 encoder->new_crtc =
8532 to_intel_crtc(config->save_encoder_crtcs[count++]);
8533 }
8534
8535 count = 0;
8536 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8537 connector->new_encoder =
8538 to_intel_encoder(config->save_connector_encoders[count++]);
8539 }
8540 }
8541
8542 static bool
8543 is_crtc_connector_off(struct drm_crtc *crtc, struct drm_connector *connectors,
8544 int num_connectors)
8545 {
8546 int i;
8547
8548 for (i = 0; i < num_connectors; i++)
8549 if (connectors[i].encoder &&
8550 connectors[i].encoder->crtc == crtc &&
8551 connectors[i].dpms != DRM_MODE_DPMS_ON)
8552 return true;
8553
8554 return false;
8555 }
8556
8557 static void
8558 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8559 struct intel_set_config *config)
8560 {
8561
8562 /* We should be able to check here if the fb has the same properties
8563 * and then just flip_or_move it */
8564 if (set->connectors != NULL &&
8565 is_crtc_connector_off(set->crtc, *set->connectors,
8566 set->num_connectors)) {
8567 config->mode_changed = true;
8568 } else if (set->crtc->fb != set->fb) {
8569 /* If we have no fb then treat it as a full mode set */
8570 if (set->crtc->fb == NULL) {
8571 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8572 config->mode_changed = true;
8573 } else if (set->fb == NULL) {
8574 config->mode_changed = true;
8575 } else if (set->fb->pixel_format !=
8576 set->crtc->fb->pixel_format) {
8577 config->mode_changed = true;
8578 } else {
8579 config->fb_changed = true;
8580 }
8581 }
8582
8583 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8584 config->fb_changed = true;
8585
8586 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8587 DRM_DEBUG_KMS("modes are different, full mode set\n");
8588 drm_mode_debug_printmodeline(&set->crtc->mode);
8589 drm_mode_debug_printmodeline(set->mode);
8590 config->mode_changed = true;
8591 }
8592 }
8593
8594 static int
8595 intel_modeset_stage_output_state(struct drm_device *dev,
8596 struct drm_mode_set *set,
8597 struct intel_set_config *config)
8598 {
8599 struct drm_crtc *new_crtc;
8600 struct intel_connector *connector;
8601 struct intel_encoder *encoder;
8602 int count, ro;
8603
8604 /* The upper layers ensure that we either disable a crtc or have a list
8605 * of connectors. For paranoia, double-check this. */
8606 WARN_ON(!set->fb && (set->num_connectors != 0));
8607 WARN_ON(set->fb && (set->num_connectors == 0));
8608
8609 count = 0;
8610 list_for_each_entry(connector, &dev->mode_config.connector_list,
8611 base.head) {
8612 /* Otherwise traverse passed in connector list and get encoders
8613 * for them. */
8614 for (ro = 0; ro < set->num_connectors; ro++) {
8615 if (set->connectors[ro] == &connector->base) {
8616 connector->new_encoder = connector->encoder;
8617 break;
8618 }
8619 }
8620
8621 /* If we disable the crtc, disable all its connectors. Also, if
8622 * the connector is on the changing crtc but not on the new
8623 * connector list, disable it. */
8624 if ((!set->fb || ro == set->num_connectors) &&
8625 connector->base.encoder &&
8626 connector->base.encoder->crtc == set->crtc) {
8627 connector->new_encoder = NULL;
8628
8629 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8630 connector->base.base.id,
8631 drm_get_connector_name(&connector->base));
8632 }
8633
8634
8635 if (&connector->new_encoder->base != connector->base.encoder) {
8636 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8637 config->mode_changed = true;
8638 }
8639 }
8640 /* connector->new_encoder is now updated for all connectors. */
8641
8642 /* Update crtc of enabled connectors. */
8643 count = 0;
8644 list_for_each_entry(connector, &dev->mode_config.connector_list,
8645 base.head) {
8646 if (!connector->new_encoder)
8647 continue;
8648
8649 new_crtc = connector->new_encoder->base.crtc;
8650
8651 for (ro = 0; ro < set->num_connectors; ro++) {
8652 if (set->connectors[ro] == &connector->base)
8653 new_crtc = set->crtc;
8654 }
8655
8656 /* Make sure the new CRTC will work with the encoder */
8657 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8658 new_crtc)) {
8659 return -EINVAL;
8660 }
8661 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8662
8663 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8664 connector->base.base.id,
8665 drm_get_connector_name(&connector->base),
8666 new_crtc->base.id);
8667 }
8668
8669 /* Check for any encoders that needs to be disabled. */
8670 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8671 base.head) {
8672 list_for_each_entry(connector,
8673 &dev->mode_config.connector_list,
8674 base.head) {
8675 if (connector->new_encoder == encoder) {
8676 WARN_ON(!connector->new_encoder->new_crtc);
8677
8678 goto next_encoder;
8679 }
8680 }
8681 encoder->new_crtc = NULL;
8682 next_encoder:
8683 /* Only now check for crtc changes so we don't miss encoders
8684 * that will be disabled. */
8685 if (&encoder->new_crtc->base != encoder->base.crtc) {
8686 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8687 config->mode_changed = true;
8688 }
8689 }
8690 /* Now we've also updated encoder->new_crtc for all encoders. */
8691
8692 return 0;
8693 }
8694
8695 static int intel_crtc_set_config(struct drm_mode_set *set)
8696 {
8697 struct drm_device *dev;
8698 struct drm_mode_set save_set;
8699 struct intel_set_config *config;
8700 int ret;
8701
8702 BUG_ON(!set);
8703 BUG_ON(!set->crtc);
8704 BUG_ON(!set->crtc->helper_private);
8705
8706 /* Enforce sane interface api - has been abused by the fb helper. */
8707 BUG_ON(!set->mode && set->fb);
8708 BUG_ON(set->fb && set->num_connectors == 0);
8709
8710 if (set->fb) {
8711 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8712 set->crtc->base.id, set->fb->base.id,
8713 (int)set->num_connectors, set->x, set->y);
8714 } else {
8715 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8716 }
8717
8718 dev = set->crtc->dev;
8719
8720 ret = -ENOMEM;
8721 config = kzalloc(sizeof(*config), GFP_KERNEL);
8722 if (!config)
8723 goto out_config;
8724
8725 ret = intel_set_config_save_state(dev, config);
8726 if (ret)
8727 goto out_config;
8728
8729 save_set.crtc = set->crtc;
8730 save_set.mode = &set->crtc->mode;
8731 save_set.x = set->crtc->x;
8732 save_set.y = set->crtc->y;
8733 save_set.fb = set->crtc->fb;
8734
8735 /* Compute whether we need a full modeset, only an fb base update or no
8736 * change at all. In the future we might also check whether only the
8737 * mode changed, e.g. for LVDS where we only change the panel fitter in
8738 * such cases. */
8739 intel_set_config_compute_mode_changes(set, config);
8740
8741 ret = intel_modeset_stage_output_state(dev, set, config);
8742 if (ret)
8743 goto fail;
8744
8745 if (config->mode_changed) {
8746 ret = intel_set_mode(set->crtc, set->mode,
8747 set->x, set->y, set->fb);
8748 } else if (config->fb_changed) {
8749 intel_crtc_wait_for_pending_flips(set->crtc);
8750
8751 ret = intel_pipe_set_base(set->crtc,
8752 set->x, set->y, set->fb);
8753 }
8754
8755 if (ret) {
8756 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
8757 set->crtc->base.id, ret);
8758 fail:
8759 intel_set_config_restore_state(dev, config);
8760
8761 /* Try to restore the config */
8762 if (config->mode_changed &&
8763 intel_set_mode(save_set.crtc, save_set.mode,
8764 save_set.x, save_set.y, save_set.fb))
8765 DRM_ERROR("failed to restore config after modeset failure\n");
8766 }
8767
8768 out_config:
8769 intel_set_config_free(config);
8770 return ret;
8771 }
8772
8773 static const struct drm_crtc_funcs intel_crtc_funcs = {
8774 .cursor_set = intel_crtc_cursor_set,
8775 .cursor_move = intel_crtc_cursor_move,
8776 .gamma_set = intel_crtc_gamma_set,
8777 .set_config = intel_crtc_set_config,
8778 .destroy = intel_crtc_destroy,
8779 .page_flip = intel_crtc_page_flip,
8780 };
8781
8782 static void intel_cpu_pll_init(struct drm_device *dev)
8783 {
8784 if (HAS_DDI(dev))
8785 intel_ddi_pll_init(dev);
8786 }
8787
8788 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
8789 struct intel_shared_dpll *pll,
8790 struct intel_dpll_hw_state *hw_state)
8791 {
8792 uint32_t val;
8793
8794 val = I915_READ(PCH_DPLL(pll->id));
8795 hw_state->dpll = val;
8796 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
8797 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
8798
8799 return val & DPLL_VCO_ENABLE;
8800 }
8801
8802 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
8803 struct intel_shared_dpll *pll)
8804 {
8805 uint32_t reg, val;
8806
8807 /* PCH refclock must be enabled first */
8808 assert_pch_refclk_enabled(dev_priv);
8809
8810 reg = PCH_DPLL(pll->id);
8811 val = I915_READ(reg);
8812 val |= DPLL_VCO_ENABLE;
8813 I915_WRITE(reg, val);
8814 POSTING_READ(reg);
8815 udelay(200);
8816 }
8817
8818 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
8819 struct intel_shared_dpll *pll)
8820 {
8821 struct drm_device *dev = dev_priv->dev;
8822 struct intel_crtc *crtc;
8823 uint32_t reg, val;
8824
8825 /* Make sure no transcoder isn't still depending on us. */
8826 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
8827 if (intel_crtc_to_shared_dpll(crtc) == pll)
8828 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
8829 }
8830
8831 reg = PCH_DPLL(pll->id);
8832 val = I915_READ(reg);
8833 val &= ~DPLL_VCO_ENABLE;
8834 I915_WRITE(reg, val);
8835 POSTING_READ(reg);
8836 udelay(200);
8837 }
8838
8839 static char *ibx_pch_dpll_names[] = {
8840 "PCH DPLL A",
8841 "PCH DPLL B",
8842 };
8843
8844 static void ibx_pch_dpll_init(struct drm_device *dev)
8845 {
8846 struct drm_i915_private *dev_priv = dev->dev_private;
8847 int i;
8848
8849 dev_priv->num_shared_dpll = 2;
8850
8851 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8852 dev_priv->shared_dplls[i].id = i;
8853 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
8854 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
8855 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
8856 dev_priv->shared_dplls[i].get_hw_state =
8857 ibx_pch_dpll_get_hw_state;
8858 }
8859 }
8860
8861 static void intel_shared_dpll_init(struct drm_device *dev)
8862 {
8863 struct drm_i915_private *dev_priv = dev->dev_private;
8864
8865 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8866 ibx_pch_dpll_init(dev);
8867 else
8868 dev_priv->num_shared_dpll = 0;
8869
8870 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
8871 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
8872 dev_priv->num_shared_dpll);
8873 }
8874
8875 static void intel_crtc_init(struct drm_device *dev, int pipe)
8876 {
8877 drm_i915_private_t *dev_priv = dev->dev_private;
8878 struct intel_crtc *intel_crtc;
8879 int i;
8880
8881 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8882 if (intel_crtc == NULL)
8883 return;
8884
8885 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8886
8887 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8888 for (i = 0; i < 256; i++) {
8889 intel_crtc->lut_r[i] = i;
8890 intel_crtc->lut_g[i] = i;
8891 intel_crtc->lut_b[i] = i;
8892 }
8893
8894 /* Swap pipes & planes for FBC on pre-965 */
8895 intel_crtc->pipe = pipe;
8896 intel_crtc->plane = pipe;
8897 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8898 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8899 intel_crtc->plane = !pipe;
8900 }
8901
8902 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8903 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8904 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8905 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8906
8907 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8908 }
8909
8910 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8911 struct drm_file *file)
8912 {
8913 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8914 struct drm_mode_object *drmmode_obj;
8915 struct intel_crtc *crtc;
8916
8917 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8918 return -ENODEV;
8919
8920 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8921 DRM_MODE_OBJECT_CRTC);
8922
8923 if (!drmmode_obj) {
8924 DRM_ERROR("no such CRTC id\n");
8925 return -EINVAL;
8926 }
8927
8928 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8929 pipe_from_crtc_id->pipe = crtc->pipe;
8930
8931 return 0;
8932 }
8933
8934 static int intel_encoder_clones(struct intel_encoder *encoder)
8935 {
8936 struct drm_device *dev = encoder->base.dev;
8937 struct intel_encoder *source_encoder;
8938 int index_mask = 0;
8939 int entry = 0;
8940
8941 list_for_each_entry(source_encoder,
8942 &dev->mode_config.encoder_list, base.head) {
8943
8944 if (encoder == source_encoder)
8945 index_mask |= (1 << entry);
8946
8947 /* Intel hw has only one MUX where enocoders could be cloned. */
8948 if (encoder->cloneable && source_encoder->cloneable)
8949 index_mask |= (1 << entry);
8950
8951 entry++;
8952 }
8953
8954 return index_mask;
8955 }
8956
8957 static bool has_edp_a(struct drm_device *dev)
8958 {
8959 struct drm_i915_private *dev_priv = dev->dev_private;
8960
8961 if (!IS_MOBILE(dev))
8962 return false;
8963
8964 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8965 return false;
8966
8967 if (IS_GEN5(dev) &&
8968 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8969 return false;
8970
8971 return true;
8972 }
8973
8974 static void intel_setup_outputs(struct drm_device *dev)
8975 {
8976 struct drm_i915_private *dev_priv = dev->dev_private;
8977 struct intel_encoder *encoder;
8978 bool dpd_is_edp = false;
8979
8980 intel_lvds_init(dev);
8981
8982 if (!IS_ULT(dev))
8983 intel_crt_init(dev);
8984
8985 if (HAS_DDI(dev)) {
8986 int found;
8987
8988 /* Haswell uses DDI functions to detect digital outputs */
8989 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8990 /* DDI A only supports eDP */
8991 if (found)
8992 intel_ddi_init(dev, PORT_A);
8993
8994 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8995 * register */
8996 found = I915_READ(SFUSE_STRAP);
8997
8998 if (found & SFUSE_STRAP_DDIB_DETECTED)
8999 intel_ddi_init(dev, PORT_B);
9000 if (found & SFUSE_STRAP_DDIC_DETECTED)
9001 intel_ddi_init(dev, PORT_C);
9002 if (found & SFUSE_STRAP_DDID_DETECTED)
9003 intel_ddi_init(dev, PORT_D);
9004 } else if (HAS_PCH_SPLIT(dev)) {
9005 int found;
9006 dpd_is_edp = intel_dpd_is_edp(dev);
9007
9008 if (has_edp_a(dev))
9009 intel_dp_init(dev, DP_A, PORT_A);
9010
9011 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
9012 /* PCH SDVOB multiplex with HDMIB */
9013 found = intel_sdvo_init(dev, PCH_SDVOB, true);
9014 if (!found)
9015 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
9016 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
9017 intel_dp_init(dev, PCH_DP_B, PORT_B);
9018 }
9019
9020 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
9021 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
9022
9023 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
9024 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
9025
9026 if (I915_READ(PCH_DP_C) & DP_DETECTED)
9027 intel_dp_init(dev, PCH_DP_C, PORT_C);
9028
9029 if (I915_READ(PCH_DP_D) & DP_DETECTED)
9030 intel_dp_init(dev, PCH_DP_D, PORT_D);
9031 } else if (IS_VALLEYVIEW(dev)) {
9032 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
9033 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9034 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
9035
9036 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
9037 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9038 PORT_B);
9039 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9040 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
9041 }
9042 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
9043 bool found = false;
9044
9045 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9046 DRM_DEBUG_KMS("probing SDVOB\n");
9047 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
9048 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9049 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
9050 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
9051 }
9052
9053 if (!found && SUPPORTS_INTEGRATED_DP(dev))
9054 intel_dp_init(dev, DP_B, PORT_B);
9055 }
9056
9057 /* Before G4X SDVOC doesn't have its own detect register */
9058
9059 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9060 DRM_DEBUG_KMS("probing SDVOC\n");
9061 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
9062 }
9063
9064 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
9065
9066 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9067 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
9068 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
9069 }
9070 if (SUPPORTS_INTEGRATED_DP(dev))
9071 intel_dp_init(dev, DP_C, PORT_C);
9072 }
9073
9074 if (SUPPORTS_INTEGRATED_DP(dev) &&
9075 (I915_READ(DP_D) & DP_DETECTED))
9076 intel_dp_init(dev, DP_D, PORT_D);
9077 } else if (IS_GEN2(dev))
9078 intel_dvo_init(dev);
9079
9080 if (SUPPORTS_TV(dev))
9081 intel_tv_init(dev);
9082
9083 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9084 encoder->base.possible_crtcs = encoder->crtc_mask;
9085 encoder->base.possible_clones =
9086 intel_encoder_clones(encoder);
9087 }
9088
9089 intel_init_pch_refclk(dev);
9090
9091 drm_helper_move_panel_connectors_to_head(dev);
9092 }
9093
9094 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9095 {
9096 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9097
9098 drm_framebuffer_cleanup(fb);
9099 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
9100
9101 kfree(intel_fb);
9102 }
9103
9104 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
9105 struct drm_file *file,
9106 unsigned int *handle)
9107 {
9108 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9109 struct drm_i915_gem_object *obj = intel_fb->obj;
9110
9111 return drm_gem_handle_create(file, &obj->base, handle);
9112 }
9113
9114 static const struct drm_framebuffer_funcs intel_fb_funcs = {
9115 .destroy = intel_user_framebuffer_destroy,
9116 .create_handle = intel_user_framebuffer_create_handle,
9117 };
9118
9119 int intel_framebuffer_init(struct drm_device *dev,
9120 struct intel_framebuffer *intel_fb,
9121 struct drm_mode_fb_cmd2 *mode_cmd,
9122 struct drm_i915_gem_object *obj)
9123 {
9124 int pitch_limit;
9125 int ret;
9126
9127 if (obj->tiling_mode == I915_TILING_Y) {
9128 DRM_DEBUG("hardware does not support tiling Y\n");
9129 return -EINVAL;
9130 }
9131
9132 if (mode_cmd->pitches[0] & 63) {
9133 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9134 mode_cmd->pitches[0]);
9135 return -EINVAL;
9136 }
9137
9138 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9139 pitch_limit = 32*1024;
9140 } else if (INTEL_INFO(dev)->gen >= 4) {
9141 if (obj->tiling_mode)
9142 pitch_limit = 16*1024;
9143 else
9144 pitch_limit = 32*1024;
9145 } else if (INTEL_INFO(dev)->gen >= 3) {
9146 if (obj->tiling_mode)
9147 pitch_limit = 8*1024;
9148 else
9149 pitch_limit = 16*1024;
9150 } else
9151 /* XXX DSPC is limited to 4k tiled */
9152 pitch_limit = 8*1024;
9153
9154 if (mode_cmd->pitches[0] > pitch_limit) {
9155 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9156 obj->tiling_mode ? "tiled" : "linear",
9157 mode_cmd->pitches[0], pitch_limit);
9158 return -EINVAL;
9159 }
9160
9161 if (obj->tiling_mode != I915_TILING_NONE &&
9162 mode_cmd->pitches[0] != obj->stride) {
9163 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9164 mode_cmd->pitches[0], obj->stride);
9165 return -EINVAL;
9166 }
9167
9168 /* Reject formats not supported by any plane early. */
9169 switch (mode_cmd->pixel_format) {
9170 case DRM_FORMAT_C8:
9171 case DRM_FORMAT_RGB565:
9172 case DRM_FORMAT_XRGB8888:
9173 case DRM_FORMAT_ARGB8888:
9174 break;
9175 case DRM_FORMAT_XRGB1555:
9176 case DRM_FORMAT_ARGB1555:
9177 if (INTEL_INFO(dev)->gen > 3) {
9178 DRM_DEBUG("unsupported pixel format: %s\n",
9179 drm_get_format_name(mode_cmd->pixel_format));
9180 return -EINVAL;
9181 }
9182 break;
9183 case DRM_FORMAT_XBGR8888:
9184 case DRM_FORMAT_ABGR8888:
9185 case DRM_FORMAT_XRGB2101010:
9186 case DRM_FORMAT_ARGB2101010:
9187 case DRM_FORMAT_XBGR2101010:
9188 case DRM_FORMAT_ABGR2101010:
9189 if (INTEL_INFO(dev)->gen < 4) {
9190 DRM_DEBUG("unsupported pixel format: %s\n",
9191 drm_get_format_name(mode_cmd->pixel_format));
9192 return -EINVAL;
9193 }
9194 break;
9195 case DRM_FORMAT_YUYV:
9196 case DRM_FORMAT_UYVY:
9197 case DRM_FORMAT_YVYU:
9198 case DRM_FORMAT_VYUY:
9199 if (INTEL_INFO(dev)->gen < 5) {
9200 DRM_DEBUG("unsupported pixel format: %s\n",
9201 drm_get_format_name(mode_cmd->pixel_format));
9202 return -EINVAL;
9203 }
9204 break;
9205 default:
9206 DRM_DEBUG("unsupported pixel format: %s\n",
9207 drm_get_format_name(mode_cmd->pixel_format));
9208 return -EINVAL;
9209 }
9210
9211 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9212 if (mode_cmd->offsets[0] != 0)
9213 return -EINVAL;
9214
9215 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9216 intel_fb->obj = obj;
9217
9218 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9219 if (ret) {
9220 DRM_ERROR("framebuffer init failed %d\n", ret);
9221 return ret;
9222 }
9223
9224 return 0;
9225 }
9226
9227 static struct drm_framebuffer *
9228 intel_user_framebuffer_create(struct drm_device *dev,
9229 struct drm_file *filp,
9230 struct drm_mode_fb_cmd2 *mode_cmd)
9231 {
9232 struct drm_i915_gem_object *obj;
9233
9234 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9235 mode_cmd->handles[0]));
9236 if (&obj->base == NULL)
9237 return ERR_PTR(-ENOENT);
9238
9239 return intel_framebuffer_create(dev, mode_cmd, obj);
9240 }
9241
9242 static const struct drm_mode_config_funcs intel_mode_funcs = {
9243 .fb_create = intel_user_framebuffer_create,
9244 .output_poll_changed = intel_fb_output_poll_changed,
9245 };
9246
9247 /* Set up chip specific display functions */
9248 static void intel_init_display(struct drm_device *dev)
9249 {
9250 struct drm_i915_private *dev_priv = dev->dev_private;
9251
9252 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9253 dev_priv->display.find_dpll = g4x_find_best_dpll;
9254 else if (IS_VALLEYVIEW(dev))
9255 dev_priv->display.find_dpll = vlv_find_best_dpll;
9256 else if (IS_PINEVIEW(dev))
9257 dev_priv->display.find_dpll = pnv_find_best_dpll;
9258 else
9259 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9260
9261 if (HAS_DDI(dev)) {
9262 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
9263 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
9264 dev_priv->display.crtc_enable = haswell_crtc_enable;
9265 dev_priv->display.crtc_disable = haswell_crtc_disable;
9266 dev_priv->display.off = haswell_crtc_off;
9267 dev_priv->display.update_plane = ironlake_update_plane;
9268 } else if (HAS_PCH_SPLIT(dev)) {
9269 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
9270 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
9271 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9272 dev_priv->display.crtc_disable = ironlake_crtc_disable;
9273 dev_priv->display.off = ironlake_crtc_off;
9274 dev_priv->display.update_plane = ironlake_update_plane;
9275 } else if (IS_VALLEYVIEW(dev)) {
9276 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9277 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9278 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9279 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9280 dev_priv->display.off = i9xx_crtc_off;
9281 dev_priv->display.update_plane = i9xx_update_plane;
9282 } else {
9283 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9284 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9285 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9286 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9287 dev_priv->display.off = i9xx_crtc_off;
9288 dev_priv->display.update_plane = i9xx_update_plane;
9289 }
9290
9291 /* Returns the core display clock speed */
9292 if (IS_VALLEYVIEW(dev))
9293 dev_priv->display.get_display_clock_speed =
9294 valleyview_get_display_clock_speed;
9295 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
9296 dev_priv->display.get_display_clock_speed =
9297 i945_get_display_clock_speed;
9298 else if (IS_I915G(dev))
9299 dev_priv->display.get_display_clock_speed =
9300 i915_get_display_clock_speed;
9301 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
9302 dev_priv->display.get_display_clock_speed =
9303 i9xx_misc_get_display_clock_speed;
9304 else if (IS_I915GM(dev))
9305 dev_priv->display.get_display_clock_speed =
9306 i915gm_get_display_clock_speed;
9307 else if (IS_I865G(dev))
9308 dev_priv->display.get_display_clock_speed =
9309 i865_get_display_clock_speed;
9310 else if (IS_I85X(dev))
9311 dev_priv->display.get_display_clock_speed =
9312 i855_get_display_clock_speed;
9313 else /* 852, 830 */
9314 dev_priv->display.get_display_clock_speed =
9315 i830_get_display_clock_speed;
9316
9317 if (HAS_PCH_SPLIT(dev)) {
9318 if (IS_GEN5(dev)) {
9319 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
9320 dev_priv->display.write_eld = ironlake_write_eld;
9321 } else if (IS_GEN6(dev)) {
9322 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
9323 dev_priv->display.write_eld = ironlake_write_eld;
9324 } else if (IS_IVYBRIDGE(dev)) {
9325 /* FIXME: detect B0+ stepping and use auto training */
9326 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
9327 dev_priv->display.write_eld = ironlake_write_eld;
9328 dev_priv->display.modeset_global_resources =
9329 ivb_modeset_global_resources;
9330 } else if (IS_HASWELL(dev)) {
9331 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
9332 dev_priv->display.write_eld = haswell_write_eld;
9333 dev_priv->display.modeset_global_resources =
9334 haswell_modeset_global_resources;
9335 }
9336 } else if (IS_G4X(dev)) {
9337 dev_priv->display.write_eld = g4x_write_eld;
9338 }
9339
9340 /* Default just returns -ENODEV to indicate unsupported */
9341 dev_priv->display.queue_flip = intel_default_queue_flip;
9342
9343 switch (INTEL_INFO(dev)->gen) {
9344 case 2:
9345 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9346 break;
9347
9348 case 3:
9349 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9350 break;
9351
9352 case 4:
9353 case 5:
9354 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9355 break;
9356
9357 case 6:
9358 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9359 break;
9360 case 7:
9361 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9362 break;
9363 }
9364 }
9365
9366 /*
9367 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9368 * resume, or other times. This quirk makes sure that's the case for
9369 * affected systems.
9370 */
9371 static void quirk_pipea_force(struct drm_device *dev)
9372 {
9373 struct drm_i915_private *dev_priv = dev->dev_private;
9374
9375 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9376 DRM_INFO("applying pipe a force quirk\n");
9377 }
9378
9379 /*
9380 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9381 */
9382 static void quirk_ssc_force_disable(struct drm_device *dev)
9383 {
9384 struct drm_i915_private *dev_priv = dev->dev_private;
9385 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9386 DRM_INFO("applying lvds SSC disable quirk\n");
9387 }
9388
9389 /*
9390 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9391 * brightness value
9392 */
9393 static void quirk_invert_brightness(struct drm_device *dev)
9394 {
9395 struct drm_i915_private *dev_priv = dev->dev_private;
9396 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
9397 DRM_INFO("applying inverted panel brightness quirk\n");
9398 }
9399
9400 struct intel_quirk {
9401 int device;
9402 int subsystem_vendor;
9403 int subsystem_device;
9404 void (*hook)(struct drm_device *dev);
9405 };
9406
9407 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9408 struct intel_dmi_quirk {
9409 void (*hook)(struct drm_device *dev);
9410 const struct dmi_system_id (*dmi_id_list)[];
9411 };
9412
9413 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9414 {
9415 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9416 return 1;
9417 }
9418
9419 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9420 {
9421 .dmi_id_list = &(const struct dmi_system_id[]) {
9422 {
9423 .callback = intel_dmi_reverse_brightness,
9424 .ident = "NCR Corporation",
9425 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9426 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9427 },
9428 },
9429 { } /* terminating entry */
9430 },
9431 .hook = quirk_invert_brightness,
9432 },
9433 };
9434
9435 static struct intel_quirk intel_quirks[] = {
9436 /* HP Mini needs pipe A force quirk (LP: #322104) */
9437 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9438
9439 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9440 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9441
9442 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9443 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9444
9445 /* 830/845 need to leave pipe A & dpll A up */
9446 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9447 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9448
9449 /* Lenovo U160 cannot use SSC on LVDS */
9450 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9451
9452 /* Sony Vaio Y cannot use SSC on LVDS */
9453 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9454
9455 /* Acer Aspire 5734Z must invert backlight brightness */
9456 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
9457
9458 /* Acer/eMachines G725 */
9459 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
9460
9461 /* Acer/eMachines e725 */
9462 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
9463
9464 /* Acer/Packard Bell NCL20 */
9465 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
9466
9467 /* Acer Aspire 4736Z */
9468 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
9469 };
9470
9471 static void intel_init_quirks(struct drm_device *dev)
9472 {
9473 struct pci_dev *d = dev->pdev;
9474 int i;
9475
9476 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9477 struct intel_quirk *q = &intel_quirks[i];
9478
9479 if (d->device == q->device &&
9480 (d->subsystem_vendor == q->subsystem_vendor ||
9481 q->subsystem_vendor == PCI_ANY_ID) &&
9482 (d->subsystem_device == q->subsystem_device ||
9483 q->subsystem_device == PCI_ANY_ID))
9484 q->hook(dev);
9485 }
9486 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9487 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9488 intel_dmi_quirks[i].hook(dev);
9489 }
9490 }
9491
9492 /* Disable the VGA plane that we never use */
9493 static void i915_disable_vga(struct drm_device *dev)
9494 {
9495 struct drm_i915_private *dev_priv = dev->dev_private;
9496 u8 sr1;
9497 u32 vga_reg = i915_vgacntrl_reg(dev);
9498
9499 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9500 outb(SR01, VGA_SR_INDEX);
9501 sr1 = inb(VGA_SR_DATA);
9502 outb(sr1 | 1<<5, VGA_SR_DATA);
9503 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9504 udelay(300);
9505
9506 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9507 POSTING_READ(vga_reg);
9508 }
9509
9510 void intel_modeset_init_hw(struct drm_device *dev)
9511 {
9512 intel_init_power_well(dev);
9513
9514 intel_prepare_ddi(dev);
9515
9516 intel_init_clock_gating(dev);
9517
9518 mutex_lock(&dev->struct_mutex);
9519 intel_enable_gt_powersave(dev);
9520 mutex_unlock(&dev->struct_mutex);
9521 }
9522
9523 void intel_modeset_suspend_hw(struct drm_device *dev)
9524 {
9525 intel_suspend_hw(dev);
9526 }
9527
9528 void intel_modeset_init(struct drm_device *dev)
9529 {
9530 struct drm_i915_private *dev_priv = dev->dev_private;
9531 int i, j, ret;
9532
9533 drm_mode_config_init(dev);
9534
9535 dev->mode_config.min_width = 0;
9536 dev->mode_config.min_height = 0;
9537
9538 dev->mode_config.preferred_depth = 24;
9539 dev->mode_config.prefer_shadow = 1;
9540
9541 dev->mode_config.funcs = &intel_mode_funcs;
9542
9543 intel_init_quirks(dev);
9544
9545 intel_init_pm(dev);
9546
9547 if (INTEL_INFO(dev)->num_pipes == 0)
9548 return;
9549
9550 intel_init_display(dev);
9551
9552 if (IS_GEN2(dev)) {
9553 dev->mode_config.max_width = 2048;
9554 dev->mode_config.max_height = 2048;
9555 } else if (IS_GEN3(dev)) {
9556 dev->mode_config.max_width = 4096;
9557 dev->mode_config.max_height = 4096;
9558 } else {
9559 dev->mode_config.max_width = 8192;
9560 dev->mode_config.max_height = 8192;
9561 }
9562 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
9563
9564 DRM_DEBUG_KMS("%d display pipe%s available.\n",
9565 INTEL_INFO(dev)->num_pipes,
9566 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
9567
9568 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
9569 intel_crtc_init(dev, i);
9570 for (j = 0; j < dev_priv->num_plane; j++) {
9571 ret = intel_plane_init(dev, i, j);
9572 if (ret)
9573 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9574 pipe_name(i), sprite_name(i, j), ret);
9575 }
9576 }
9577
9578 intel_cpu_pll_init(dev);
9579 intel_shared_dpll_init(dev);
9580
9581 /* Just disable it once at startup */
9582 i915_disable_vga(dev);
9583 intel_setup_outputs(dev);
9584
9585 /* Just in case the BIOS is doing something questionable. */
9586 intel_disable_fbc(dev);
9587 }
9588
9589 static void
9590 intel_connector_break_all_links(struct intel_connector *connector)
9591 {
9592 connector->base.dpms = DRM_MODE_DPMS_OFF;
9593 connector->base.encoder = NULL;
9594 connector->encoder->connectors_active = false;
9595 connector->encoder->base.crtc = NULL;
9596 }
9597
9598 static void intel_enable_pipe_a(struct drm_device *dev)
9599 {
9600 struct intel_connector *connector;
9601 struct drm_connector *crt = NULL;
9602 struct intel_load_detect_pipe load_detect_temp;
9603
9604 /* We can't just switch on the pipe A, we need to set things up with a
9605 * proper mode and output configuration. As a gross hack, enable pipe A
9606 * by enabling the load detect pipe once. */
9607 list_for_each_entry(connector,
9608 &dev->mode_config.connector_list,
9609 base.head) {
9610 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9611 crt = &connector->base;
9612 break;
9613 }
9614 }
9615
9616 if (!crt)
9617 return;
9618
9619 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9620 intel_release_load_detect_pipe(crt, &load_detect_temp);
9621
9622
9623 }
9624
9625 static bool
9626 intel_check_plane_mapping(struct intel_crtc *crtc)
9627 {
9628 struct drm_device *dev = crtc->base.dev;
9629 struct drm_i915_private *dev_priv = dev->dev_private;
9630 u32 reg, val;
9631
9632 if (INTEL_INFO(dev)->num_pipes == 1)
9633 return true;
9634
9635 reg = DSPCNTR(!crtc->plane);
9636 val = I915_READ(reg);
9637
9638 if ((val & DISPLAY_PLANE_ENABLE) &&
9639 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9640 return false;
9641
9642 return true;
9643 }
9644
9645 static void intel_sanitize_crtc(struct intel_crtc *crtc)
9646 {
9647 struct drm_device *dev = crtc->base.dev;
9648 struct drm_i915_private *dev_priv = dev->dev_private;
9649 u32 reg;
9650
9651 /* Clear any frame start delays used for debugging left by the BIOS */
9652 reg = PIPECONF(crtc->config.cpu_transcoder);
9653 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9654
9655 /* We need to sanitize the plane -> pipe mapping first because this will
9656 * disable the crtc (and hence change the state) if it is wrong. Note
9657 * that gen4+ has a fixed plane -> pipe mapping. */
9658 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
9659 struct intel_connector *connector;
9660 bool plane;
9661
9662 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9663 crtc->base.base.id);
9664
9665 /* Pipe has the wrong plane attached and the plane is active.
9666 * Temporarily change the plane mapping and disable everything
9667 * ... */
9668 plane = crtc->plane;
9669 crtc->plane = !plane;
9670 dev_priv->display.crtc_disable(&crtc->base);
9671 crtc->plane = plane;
9672
9673 /* ... and break all links. */
9674 list_for_each_entry(connector, &dev->mode_config.connector_list,
9675 base.head) {
9676 if (connector->encoder->base.crtc != &crtc->base)
9677 continue;
9678
9679 intel_connector_break_all_links(connector);
9680 }
9681
9682 WARN_ON(crtc->active);
9683 crtc->base.enabled = false;
9684 }
9685
9686 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9687 crtc->pipe == PIPE_A && !crtc->active) {
9688 /* BIOS forgot to enable pipe A, this mostly happens after
9689 * resume. Force-enable the pipe to fix this, the update_dpms
9690 * call below we restore the pipe to the right state, but leave
9691 * the required bits on. */
9692 intel_enable_pipe_a(dev);
9693 }
9694
9695 /* Adjust the state of the output pipe according to whether we
9696 * have active connectors/encoders. */
9697 intel_crtc_update_dpms(&crtc->base);
9698
9699 if (crtc->active != crtc->base.enabled) {
9700 struct intel_encoder *encoder;
9701
9702 /* This can happen either due to bugs in the get_hw_state
9703 * functions or because the pipe is force-enabled due to the
9704 * pipe A quirk. */
9705 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9706 crtc->base.base.id,
9707 crtc->base.enabled ? "enabled" : "disabled",
9708 crtc->active ? "enabled" : "disabled");
9709
9710 crtc->base.enabled = crtc->active;
9711
9712 /* Because we only establish the connector -> encoder ->
9713 * crtc links if something is active, this means the
9714 * crtc is now deactivated. Break the links. connector
9715 * -> encoder links are only establish when things are
9716 * actually up, hence no need to break them. */
9717 WARN_ON(crtc->active);
9718
9719 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9720 WARN_ON(encoder->connectors_active);
9721 encoder->base.crtc = NULL;
9722 }
9723 }
9724 }
9725
9726 static void intel_sanitize_encoder(struct intel_encoder *encoder)
9727 {
9728 struct intel_connector *connector;
9729 struct drm_device *dev = encoder->base.dev;
9730
9731 /* We need to check both for a crtc link (meaning that the
9732 * encoder is active and trying to read from a pipe) and the
9733 * pipe itself being active. */
9734 bool has_active_crtc = encoder->base.crtc &&
9735 to_intel_crtc(encoder->base.crtc)->active;
9736
9737 if (encoder->connectors_active && !has_active_crtc) {
9738 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9739 encoder->base.base.id,
9740 drm_get_encoder_name(&encoder->base));
9741
9742 /* Connector is active, but has no active pipe. This is
9743 * fallout from our resume register restoring. Disable
9744 * the encoder manually again. */
9745 if (encoder->base.crtc) {
9746 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9747 encoder->base.base.id,
9748 drm_get_encoder_name(&encoder->base));
9749 encoder->disable(encoder);
9750 }
9751
9752 /* Inconsistent output/port/pipe state happens presumably due to
9753 * a bug in one of the get_hw_state functions. Or someplace else
9754 * in our code, like the register restore mess on resume. Clamp
9755 * things to off as a safer default. */
9756 list_for_each_entry(connector,
9757 &dev->mode_config.connector_list,
9758 base.head) {
9759 if (connector->encoder != encoder)
9760 continue;
9761
9762 intel_connector_break_all_links(connector);
9763 }
9764 }
9765 /* Enabled encoders without active connectors will be fixed in
9766 * the crtc fixup. */
9767 }
9768
9769 void i915_redisable_vga(struct drm_device *dev)
9770 {
9771 struct drm_i915_private *dev_priv = dev->dev_private;
9772 u32 vga_reg = i915_vgacntrl_reg(dev);
9773
9774 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9775 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9776 i915_disable_vga(dev);
9777 }
9778 }
9779
9780 static void intel_modeset_readout_hw_state(struct drm_device *dev)
9781 {
9782 struct drm_i915_private *dev_priv = dev->dev_private;
9783 enum pipe pipe;
9784 struct intel_crtc *crtc;
9785 struct intel_encoder *encoder;
9786 struct intel_connector *connector;
9787 int i;
9788
9789 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9790 base.head) {
9791 memset(&crtc->config, 0, sizeof(crtc->config));
9792
9793 crtc->active = dev_priv->display.get_pipe_config(crtc,
9794 &crtc->config);
9795
9796 crtc->base.enabled = crtc->active;
9797
9798 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9799 crtc->base.base.id,
9800 crtc->active ? "enabled" : "disabled");
9801 }
9802
9803 /* FIXME: Smash this into the new shared dpll infrastructure. */
9804 if (HAS_DDI(dev))
9805 intel_ddi_setup_hw_pll_state(dev);
9806
9807 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9808 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9809
9810 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
9811 pll->active = 0;
9812 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9813 base.head) {
9814 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9815 pll->active++;
9816 }
9817 pll->refcount = pll->active;
9818
9819 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
9820 pll->name, pll->refcount, pll->on);
9821 }
9822
9823 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9824 base.head) {
9825 pipe = 0;
9826
9827 if (encoder->get_hw_state(encoder, &pipe)) {
9828 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9829 encoder->base.crtc = &crtc->base;
9830 if (encoder->get_config)
9831 encoder->get_config(encoder, &crtc->config);
9832 } else {
9833 encoder->base.crtc = NULL;
9834 }
9835
9836 encoder->connectors_active = false;
9837 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9838 encoder->base.base.id,
9839 drm_get_encoder_name(&encoder->base),
9840 encoder->base.crtc ? "enabled" : "disabled",
9841 pipe);
9842 }
9843
9844 list_for_each_entry(connector, &dev->mode_config.connector_list,
9845 base.head) {
9846 if (connector->get_hw_state(connector)) {
9847 connector->base.dpms = DRM_MODE_DPMS_ON;
9848 connector->encoder->connectors_active = true;
9849 connector->base.encoder = &connector->encoder->base;
9850 } else {
9851 connector->base.dpms = DRM_MODE_DPMS_OFF;
9852 connector->base.encoder = NULL;
9853 }
9854 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9855 connector->base.base.id,
9856 drm_get_connector_name(&connector->base),
9857 connector->base.encoder ? "enabled" : "disabled");
9858 }
9859 }
9860
9861 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9862 * and i915 state tracking structures. */
9863 void intel_modeset_setup_hw_state(struct drm_device *dev,
9864 bool force_restore)
9865 {
9866 struct drm_i915_private *dev_priv = dev->dev_private;
9867 enum pipe pipe;
9868 struct drm_plane *plane;
9869 struct intel_crtc *crtc;
9870 struct intel_encoder *encoder;
9871 int i;
9872
9873 intel_modeset_readout_hw_state(dev);
9874
9875 /* HW state is read out, now we need to sanitize this mess. */
9876 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9877 base.head) {
9878 intel_sanitize_encoder(encoder);
9879 }
9880
9881 for_each_pipe(pipe) {
9882 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9883 intel_sanitize_crtc(crtc);
9884 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
9885 }
9886
9887 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9888 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9889
9890 if (!pll->on || pll->active)
9891 continue;
9892
9893 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
9894
9895 pll->disable(dev_priv, pll);
9896 pll->on = false;
9897 }
9898
9899 if (force_restore) {
9900 /*
9901 * We need to use raw interfaces for restoring state to avoid
9902 * checking (bogus) intermediate states.
9903 */
9904 for_each_pipe(pipe) {
9905 struct drm_crtc *crtc =
9906 dev_priv->pipe_to_crtc_mapping[pipe];
9907
9908 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9909 crtc->fb);
9910 }
9911 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9912 intel_plane_restore(plane);
9913
9914 i915_redisable_vga(dev);
9915 } else {
9916 intel_modeset_update_staged_output_state(dev);
9917 }
9918
9919 intel_modeset_check_state(dev);
9920
9921 drm_mode_config_reset(dev);
9922 }
9923
9924 void intel_modeset_gem_init(struct drm_device *dev)
9925 {
9926 intel_modeset_init_hw(dev);
9927
9928 intel_setup_overlay(dev);
9929
9930 intel_modeset_setup_hw_state(dev, false);
9931 }
9932
9933 void intel_modeset_cleanup(struct drm_device *dev)
9934 {
9935 struct drm_i915_private *dev_priv = dev->dev_private;
9936 struct drm_crtc *crtc;
9937 struct intel_crtc *intel_crtc;
9938
9939 /*
9940 * Interrupts and polling as the first thing to avoid creating havoc.
9941 * Too much stuff here (turning of rps, connectors, ...) would
9942 * experience fancy races otherwise.
9943 */
9944 drm_irq_uninstall(dev);
9945 cancel_work_sync(&dev_priv->hotplug_work);
9946 /*
9947 * Due to the hpd irq storm handling the hotplug work can re-arm the
9948 * poll handlers. Hence disable polling after hpd handling is shut down.
9949 */
9950 drm_kms_helper_poll_fini(dev);
9951
9952 mutex_lock(&dev->struct_mutex);
9953
9954 intel_unregister_dsm_handler();
9955
9956 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9957 /* Skip inactive CRTCs */
9958 if (!crtc->fb)
9959 continue;
9960
9961 intel_crtc = to_intel_crtc(crtc);
9962 intel_increase_pllclock(crtc);
9963 }
9964
9965 intel_disable_fbc(dev);
9966
9967 intel_disable_gt_powersave(dev);
9968
9969 ironlake_teardown_rc6(dev);
9970
9971 mutex_unlock(&dev->struct_mutex);
9972
9973 /* flush any delayed tasks or pending work */
9974 flush_scheduled_work();
9975
9976 /* destroy backlight, if any, before the connectors */
9977 intel_panel_destroy_backlight(dev);
9978
9979 drm_mode_config_cleanup(dev);
9980
9981 intel_cleanup_overlay(dev);
9982 }
9983
9984 /*
9985 * Return which encoder is currently attached for connector.
9986 */
9987 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9988 {
9989 return &intel_attached_encoder(connector)->base;
9990 }
9991
9992 void intel_connector_attach_encoder(struct intel_connector *connector,
9993 struct intel_encoder *encoder)
9994 {
9995 connector->encoder = encoder;
9996 drm_mode_connector_attach_encoder(&connector->base,
9997 &encoder->base);
9998 }
9999
10000 /*
10001 * set vga decode state - true == enable VGA decode
10002 */
10003 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10004 {
10005 struct drm_i915_private *dev_priv = dev->dev_private;
10006 u16 gmch_ctrl;
10007
10008 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10009 if (state)
10010 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10011 else
10012 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10013 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10014 return 0;
10015 }
10016
10017 #ifdef CONFIG_DEBUG_FS
10018 #include <linux/seq_file.h>
10019
10020 struct intel_display_error_state {
10021
10022 u32 power_well_driver;
10023
10024 struct intel_cursor_error_state {
10025 u32 control;
10026 u32 position;
10027 u32 base;
10028 u32 size;
10029 } cursor[I915_MAX_PIPES];
10030
10031 struct intel_pipe_error_state {
10032 enum transcoder cpu_transcoder;
10033 u32 conf;
10034 u32 source;
10035
10036 u32 htotal;
10037 u32 hblank;
10038 u32 hsync;
10039 u32 vtotal;
10040 u32 vblank;
10041 u32 vsync;
10042 } pipe[I915_MAX_PIPES];
10043
10044 struct intel_plane_error_state {
10045 u32 control;
10046 u32 stride;
10047 u32 size;
10048 u32 pos;
10049 u32 addr;
10050 u32 surface;
10051 u32 tile_offset;
10052 } plane[I915_MAX_PIPES];
10053 };
10054
10055 struct intel_display_error_state *
10056 intel_display_capture_error_state(struct drm_device *dev)
10057 {
10058 drm_i915_private_t *dev_priv = dev->dev_private;
10059 struct intel_display_error_state *error;
10060 enum transcoder cpu_transcoder;
10061 int i;
10062
10063 error = kmalloc(sizeof(*error), GFP_ATOMIC);
10064 if (error == NULL)
10065 return NULL;
10066
10067 if (HAS_POWER_WELL(dev))
10068 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10069
10070 for_each_pipe(i) {
10071 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
10072 error->pipe[i].cpu_transcoder = cpu_transcoder;
10073
10074 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10075 error->cursor[i].control = I915_READ(CURCNTR(i));
10076 error->cursor[i].position = I915_READ(CURPOS(i));
10077 error->cursor[i].base = I915_READ(CURBASE(i));
10078 } else {
10079 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10080 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10081 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10082 }
10083
10084 error->plane[i].control = I915_READ(DSPCNTR(i));
10085 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
10086 if (INTEL_INFO(dev)->gen <= 3) {
10087 error->plane[i].size = I915_READ(DSPSIZE(i));
10088 error->plane[i].pos = I915_READ(DSPPOS(i));
10089 }
10090 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10091 error->plane[i].addr = I915_READ(DSPADDR(i));
10092 if (INTEL_INFO(dev)->gen >= 4) {
10093 error->plane[i].surface = I915_READ(DSPSURF(i));
10094 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10095 }
10096
10097 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
10098 error->pipe[i].source = I915_READ(PIPESRC(i));
10099 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10100 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10101 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10102 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10103 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10104 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
10105 }
10106
10107 /* In the code above we read the registers without checking if the power
10108 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10109 * prevent the next I915_WRITE from detecting it and printing an error
10110 * message. */
10111 if (HAS_POWER_WELL(dev))
10112 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
10113
10114 return error;
10115 }
10116
10117 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10118
10119 void
10120 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
10121 struct drm_device *dev,
10122 struct intel_display_error_state *error)
10123 {
10124 int i;
10125
10126 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
10127 if (HAS_POWER_WELL(dev))
10128 err_printf(m, "PWR_WELL_CTL2: %08x\n",
10129 error->power_well_driver);
10130 for_each_pipe(i) {
10131 err_printf(m, "Pipe [%d]:\n", i);
10132 err_printf(m, " CPU transcoder: %c\n",
10133 transcoder_name(error->pipe[i].cpu_transcoder));
10134 err_printf(m, " CONF: %08x\n", error->pipe[i].conf);
10135 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
10136 err_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
10137 err_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
10138 err_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
10139 err_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
10140 err_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
10141 err_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
10142
10143 err_printf(m, "Plane [%d]:\n", i);
10144 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
10145 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
10146 if (INTEL_INFO(dev)->gen <= 3) {
10147 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
10148 err_printf(m, " POS: %08x\n", error->plane[i].pos);
10149 }
10150 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10151 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
10152 if (INTEL_INFO(dev)->gen >= 4) {
10153 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
10154 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
10155 }
10156
10157 err_printf(m, "Cursor [%d]:\n", i);
10158 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
10159 err_printf(m, " POS: %08x\n", error->cursor[i].position);
10160 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
10161 }
10162 }
10163 #endif
Linux kernel - Deliverables
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