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drm/i915: Reduce clutter by using the local plane pointer
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_atomic_helper.h>
41 #include <drm/drm_dp_helper.h>
42 #include <drm/drm_crtc_helper.h>
43 #include <drm/drm_plane_helper.h>
44 #include <drm/drm_rect.h>
45 #include <linux/dma_remapping.h>
46
47 /* Primary plane formats supported by all gen */
48 #define COMMON_PRIMARY_FORMATS \
49 DRM_FORMAT_C8, \
50 DRM_FORMAT_RGB565, \
51 DRM_FORMAT_XRGB8888, \
52 DRM_FORMAT_ARGB8888
53
54 /* Primary plane formats for gen <= 3 */
55 static const uint32_t intel_primary_formats_gen2[] = {
56 COMMON_PRIMARY_FORMATS,
57 DRM_FORMAT_XRGB1555,
58 DRM_FORMAT_ARGB1555,
59 };
60
61 /* Primary plane formats for gen >= 4 */
62 static const uint32_t intel_primary_formats_gen4[] = {
63 COMMON_PRIMARY_FORMATS, \
64 DRM_FORMAT_XBGR8888,
65 DRM_FORMAT_ABGR8888,
66 DRM_FORMAT_XRGB2101010,
67 DRM_FORMAT_ARGB2101010,
68 DRM_FORMAT_XBGR2101010,
69 DRM_FORMAT_ABGR2101010,
70 };
71
72 /* Cursor formats */
73 static const uint32_t intel_cursor_formats[] = {
74 DRM_FORMAT_ARGB8888,
75 };
76
77 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
78
79 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
80 struct intel_crtc_state *pipe_config);
81 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
82 struct intel_crtc_state *pipe_config);
83
84 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
85 int x, int y, struct drm_framebuffer *old_fb);
86 static int intel_framebuffer_init(struct drm_device *dev,
87 struct intel_framebuffer *ifb,
88 struct drm_mode_fb_cmd2 *mode_cmd,
89 struct drm_i915_gem_object *obj);
90 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
91 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
92 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
93 struct intel_link_m_n *m_n,
94 struct intel_link_m_n *m2_n2);
95 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
96 static void haswell_set_pipeconf(struct drm_crtc *crtc);
97 static void intel_set_pipe_csc(struct drm_crtc *crtc);
98 static void vlv_prepare_pll(struct intel_crtc *crtc,
99 const struct intel_crtc_state *pipe_config);
100 static void chv_prepare_pll(struct intel_crtc *crtc,
101 const struct intel_crtc_state *pipe_config);
102 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
103 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
104
105 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
106 {
107 if (!connector->mst_port)
108 return connector->encoder;
109 else
110 return &connector->mst_port->mst_encoders[pipe]->base;
111 }
112
113 typedef struct {
114 int min, max;
115 } intel_range_t;
116
117 typedef struct {
118 int dot_limit;
119 int p2_slow, p2_fast;
120 } intel_p2_t;
121
122 typedef struct intel_limit intel_limit_t;
123 struct intel_limit {
124 intel_range_t dot, vco, n, m, m1, m2, p, p1;
125 intel_p2_t p2;
126 };
127
128 int
129 intel_pch_rawclk(struct drm_device *dev)
130 {
131 struct drm_i915_private *dev_priv = dev->dev_private;
132
133 WARN_ON(!HAS_PCH_SPLIT(dev));
134
135 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
136 }
137
138 static inline u32 /* units of 100MHz */
139 intel_fdi_link_freq(struct drm_device *dev)
140 {
141 if (IS_GEN5(dev)) {
142 struct drm_i915_private *dev_priv = dev->dev_private;
143 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
144 } else
145 return 27;
146 }
147
148 static const intel_limit_t intel_limits_i8xx_dac = {
149 .dot = { .min = 25000, .max = 350000 },
150 .vco = { .min = 908000, .max = 1512000 },
151 .n = { .min = 2, .max = 16 },
152 .m = { .min = 96, .max = 140 },
153 .m1 = { .min = 18, .max = 26 },
154 .m2 = { .min = 6, .max = 16 },
155 .p = { .min = 4, .max = 128 },
156 .p1 = { .min = 2, .max = 33 },
157 .p2 = { .dot_limit = 165000,
158 .p2_slow = 4, .p2_fast = 2 },
159 };
160
161 static const intel_limit_t intel_limits_i8xx_dvo = {
162 .dot = { .min = 25000, .max = 350000 },
163 .vco = { .min = 908000, .max = 1512000 },
164 .n = { .min = 2, .max = 16 },
165 .m = { .min = 96, .max = 140 },
166 .m1 = { .min = 18, .max = 26 },
167 .m2 = { .min = 6, .max = 16 },
168 .p = { .min = 4, .max = 128 },
169 .p1 = { .min = 2, .max = 33 },
170 .p2 = { .dot_limit = 165000,
171 .p2_slow = 4, .p2_fast = 4 },
172 };
173
174 static const intel_limit_t intel_limits_i8xx_lvds = {
175 .dot = { .min = 25000, .max = 350000 },
176 .vco = { .min = 908000, .max = 1512000 },
177 .n = { .min = 2, .max = 16 },
178 .m = { .min = 96, .max = 140 },
179 .m1 = { .min = 18, .max = 26 },
180 .m2 = { .min = 6, .max = 16 },
181 .p = { .min = 4, .max = 128 },
182 .p1 = { .min = 1, .max = 6 },
183 .p2 = { .dot_limit = 165000,
184 .p2_slow = 14, .p2_fast = 7 },
185 };
186
187 static const intel_limit_t intel_limits_i9xx_sdvo = {
188 .dot = { .min = 20000, .max = 400000 },
189 .vco = { .min = 1400000, .max = 2800000 },
190 .n = { .min = 1, .max = 6 },
191 .m = { .min = 70, .max = 120 },
192 .m1 = { .min = 8, .max = 18 },
193 .m2 = { .min = 3, .max = 7 },
194 .p = { .min = 5, .max = 80 },
195 .p1 = { .min = 1, .max = 8 },
196 .p2 = { .dot_limit = 200000,
197 .p2_slow = 10, .p2_fast = 5 },
198 };
199
200 static const intel_limit_t intel_limits_i9xx_lvds = {
201 .dot = { .min = 20000, .max = 400000 },
202 .vco = { .min = 1400000, .max = 2800000 },
203 .n = { .min = 1, .max = 6 },
204 .m = { .min = 70, .max = 120 },
205 .m1 = { .min = 8, .max = 18 },
206 .m2 = { .min = 3, .max = 7 },
207 .p = { .min = 7, .max = 98 },
208 .p1 = { .min = 1, .max = 8 },
209 .p2 = { .dot_limit = 112000,
210 .p2_slow = 14, .p2_fast = 7 },
211 };
212
213
214 static const intel_limit_t intel_limits_g4x_sdvo = {
215 .dot = { .min = 25000, .max = 270000 },
216 .vco = { .min = 1750000, .max = 3500000},
217 .n = { .min = 1, .max = 4 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 10, .max = 30 },
222 .p1 = { .min = 1, .max = 3},
223 .p2 = { .dot_limit = 270000,
224 .p2_slow = 10,
225 .p2_fast = 10
226 },
227 };
228
229 static const intel_limit_t intel_limits_g4x_hdmi = {
230 .dot = { .min = 22000, .max = 400000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 4 },
233 .m = { .min = 104, .max = 138 },
234 .m1 = { .min = 16, .max = 23 },
235 .m2 = { .min = 5, .max = 11 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8},
238 .p2 = { .dot_limit = 165000,
239 .p2_slow = 10, .p2_fast = 5 },
240 };
241
242 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
243 .dot = { .min = 20000, .max = 115000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 14, .p2_fast = 14
253 },
254 };
255
256 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
257 .dot = { .min = 80000, .max = 224000 },
258 .vco = { .min = 1750000, .max = 3500000 },
259 .n = { .min = 1, .max = 3 },
260 .m = { .min = 104, .max = 138 },
261 .m1 = { .min = 17, .max = 23 },
262 .m2 = { .min = 5, .max = 11 },
263 .p = { .min = 14, .max = 42 },
264 .p1 = { .min = 2, .max = 6 },
265 .p2 = { .dot_limit = 0,
266 .p2_slow = 7, .p2_fast = 7
267 },
268 };
269
270 static const intel_limit_t intel_limits_pineview_sdvo = {
271 .dot = { .min = 20000, .max = 400000},
272 .vco = { .min = 1700000, .max = 3500000 },
273 /* Pineview's Ncounter is a ring counter */
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 /* Pineview only has one combined m divider, which we treat as m2. */
277 .m1 = { .min = 0, .max = 0 },
278 .m2 = { .min = 0, .max = 254 },
279 .p = { .min = 5, .max = 80 },
280 .p1 = { .min = 1, .max = 8 },
281 .p2 = { .dot_limit = 200000,
282 .p2_slow = 10, .p2_fast = 5 },
283 };
284
285 static const intel_limit_t intel_limits_pineview_lvds = {
286 .dot = { .min = 20000, .max = 400000 },
287 .vco = { .min = 1700000, .max = 3500000 },
288 .n = { .min = 3, .max = 6 },
289 .m = { .min = 2, .max = 256 },
290 .m1 = { .min = 0, .max = 0 },
291 .m2 = { .min = 0, .max = 254 },
292 .p = { .min = 7, .max = 112 },
293 .p1 = { .min = 1, .max = 8 },
294 .p2 = { .dot_limit = 112000,
295 .p2_slow = 14, .p2_fast = 14 },
296 };
297
298 /* Ironlake / Sandybridge
299 *
300 * We calculate clock using (register_value + 2) for N/M1/M2, so here
301 * the range value for them is (actual_value - 2).
302 */
303 static const intel_limit_t intel_limits_ironlake_dac = {
304 .dot = { .min = 25000, .max = 350000 },
305 .vco = { .min = 1760000, .max = 3510000 },
306 .n = { .min = 1, .max = 5 },
307 .m = { .min = 79, .max = 127 },
308 .m1 = { .min = 12, .max = 22 },
309 .m2 = { .min = 5, .max = 9 },
310 .p = { .min = 5, .max = 80 },
311 .p1 = { .min = 1, .max = 8 },
312 .p2 = { .dot_limit = 225000,
313 .p2_slow = 10, .p2_fast = 5 },
314 };
315
316 static const intel_limit_t intel_limits_ironlake_single_lvds = {
317 .dot = { .min = 25000, .max = 350000 },
318 .vco = { .min = 1760000, .max = 3510000 },
319 .n = { .min = 1, .max = 3 },
320 .m = { .min = 79, .max = 118 },
321 .m1 = { .min = 12, .max = 22 },
322 .m2 = { .min = 5, .max = 9 },
323 .p = { .min = 28, .max = 112 },
324 .p1 = { .min = 2, .max = 8 },
325 .p2 = { .dot_limit = 225000,
326 .p2_slow = 14, .p2_fast = 14 },
327 };
328
329 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
330 .dot = { .min = 25000, .max = 350000 },
331 .vco = { .min = 1760000, .max = 3510000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 79, .max = 127 },
334 .m1 = { .min = 12, .max = 22 },
335 .m2 = { .min = 5, .max = 9 },
336 .p = { .min = 14, .max = 56 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 225000,
339 .p2_slow = 7, .p2_fast = 7 },
340 };
341
342 /* LVDS 100mhz refclk limits. */
343 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
344 .dot = { .min = 25000, .max = 350000 },
345 .vco = { .min = 1760000, .max = 3510000 },
346 .n = { .min = 1, .max = 2 },
347 .m = { .min = 79, .max = 126 },
348 .m1 = { .min = 12, .max = 22 },
349 .m2 = { .min = 5, .max = 9 },
350 .p = { .min = 28, .max = 112 },
351 .p1 = { .min = 2, .max = 8 },
352 .p2 = { .dot_limit = 225000,
353 .p2_slow = 14, .p2_fast = 14 },
354 };
355
356 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
357 .dot = { .min = 25000, .max = 350000 },
358 .vco = { .min = 1760000, .max = 3510000 },
359 .n = { .min = 1, .max = 3 },
360 .m = { .min = 79, .max = 126 },
361 .m1 = { .min = 12, .max = 22 },
362 .m2 = { .min = 5, .max = 9 },
363 .p = { .min = 14, .max = 42 },
364 .p1 = { .min = 2, .max = 6 },
365 .p2 = { .dot_limit = 225000,
366 .p2_slow = 7, .p2_fast = 7 },
367 };
368
369 static const intel_limit_t intel_limits_vlv = {
370 /*
371 * These are the data rate limits (measured in fast clocks)
372 * since those are the strictest limits we have. The fast
373 * clock and actual rate limits are more relaxed, so checking
374 * them would make no difference.
375 */
376 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m1 = { .min = 2, .max = 3 },
380 .m2 = { .min = 11, .max = 156 },
381 .p1 = { .min = 2, .max = 3 },
382 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
383 };
384
385 static const intel_limit_t intel_limits_chv = {
386 /*
387 * These are the data rate limits (measured in fast clocks)
388 * since those are the strictest limits we have. The fast
389 * clock and actual rate limits are more relaxed, so checking
390 * them would make no difference.
391 */
392 .dot = { .min = 25000 * 5, .max = 540000 * 5},
393 .vco = { .min = 4800000, .max = 6480000 },
394 .n = { .min = 1, .max = 1 },
395 .m1 = { .min = 2, .max = 2 },
396 .m2 = { .min = 24 << 22, .max = 175 << 22 },
397 .p1 = { .min = 2, .max = 4 },
398 .p2 = { .p2_slow = 1, .p2_fast = 14 },
399 };
400
401 static void vlv_clock(int refclk, intel_clock_t *clock)
402 {
403 clock->m = clock->m1 * clock->m2;
404 clock->p = clock->p1 * clock->p2;
405 if (WARN_ON(clock->n == 0 || clock->p == 0))
406 return;
407 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
408 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
409 }
410
411 /**
412 * Returns whether any output on the specified pipe is of the specified type
413 */
414 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
415 {
416 struct drm_device *dev = crtc->base.dev;
417 struct intel_encoder *encoder;
418
419 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
420 if (encoder->type == type)
421 return true;
422
423 return false;
424 }
425
426 /**
427 * Returns whether any output on the specified pipe will have the specified
428 * type after a staged modeset is complete, i.e., the same as
429 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
430 * encoder->crtc.
431 */
432 static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
433 {
434 struct drm_device *dev = crtc->base.dev;
435 struct intel_encoder *encoder;
436
437 for_each_intel_encoder(dev, encoder)
438 if (encoder->new_crtc == crtc && encoder->type == type)
439 return true;
440
441 return false;
442 }
443
444 static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
445 int refclk)
446 {
447 struct drm_device *dev = crtc->base.dev;
448 const intel_limit_t *limit;
449
450 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
451 if (intel_is_dual_link_lvds(dev)) {
452 if (refclk == 100000)
453 limit = &intel_limits_ironlake_dual_lvds_100m;
454 else
455 limit = &intel_limits_ironlake_dual_lvds;
456 } else {
457 if (refclk == 100000)
458 limit = &intel_limits_ironlake_single_lvds_100m;
459 else
460 limit = &intel_limits_ironlake_single_lvds;
461 }
462 } else
463 limit = &intel_limits_ironlake_dac;
464
465 return limit;
466 }
467
468 static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
469 {
470 struct drm_device *dev = crtc->base.dev;
471 const intel_limit_t *limit;
472
473 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
474 if (intel_is_dual_link_lvds(dev))
475 limit = &intel_limits_g4x_dual_channel_lvds;
476 else
477 limit = &intel_limits_g4x_single_channel_lvds;
478 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
479 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
480 limit = &intel_limits_g4x_hdmi;
481 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
482 limit = &intel_limits_g4x_sdvo;
483 } else /* The option is for other outputs */
484 limit = &intel_limits_i9xx_sdvo;
485
486 return limit;
487 }
488
489 static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
490 {
491 struct drm_device *dev = crtc->base.dev;
492 const intel_limit_t *limit;
493
494 if (HAS_PCH_SPLIT(dev))
495 limit = intel_ironlake_limit(crtc, refclk);
496 else if (IS_G4X(dev)) {
497 limit = intel_g4x_limit(crtc);
498 } else if (IS_PINEVIEW(dev)) {
499 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
500 limit = &intel_limits_pineview_lvds;
501 else
502 limit = &intel_limits_pineview_sdvo;
503 } else if (IS_CHERRYVIEW(dev)) {
504 limit = &intel_limits_chv;
505 } else if (IS_VALLEYVIEW(dev)) {
506 limit = &intel_limits_vlv;
507 } else if (!IS_GEN2(dev)) {
508 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
509 limit = &intel_limits_i9xx_lvds;
510 else
511 limit = &intel_limits_i9xx_sdvo;
512 } else {
513 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
514 limit = &intel_limits_i8xx_lvds;
515 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
516 limit = &intel_limits_i8xx_dvo;
517 else
518 limit = &intel_limits_i8xx_dac;
519 }
520 return limit;
521 }
522
523 /* m1 is reserved as 0 in Pineview, n is a ring counter */
524 static void pineview_clock(int refclk, intel_clock_t *clock)
525 {
526 clock->m = clock->m2 + 2;
527 clock->p = clock->p1 * clock->p2;
528 if (WARN_ON(clock->n == 0 || clock->p == 0))
529 return;
530 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
531 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
532 }
533
534 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
535 {
536 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
537 }
538
539 static void i9xx_clock(int refclk, intel_clock_t *clock)
540 {
541 clock->m = i9xx_dpll_compute_m(clock);
542 clock->p = clock->p1 * clock->p2;
543 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
544 return;
545 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
546 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
547 }
548
549 static void chv_clock(int refclk, intel_clock_t *clock)
550 {
551 clock->m = clock->m1 * clock->m2;
552 clock->p = clock->p1 * clock->p2;
553 if (WARN_ON(clock->n == 0 || clock->p == 0))
554 return;
555 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
556 clock->n << 22);
557 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
558 }
559
560 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
561 /**
562 * Returns whether the given set of divisors are valid for a given refclk with
563 * the given connectors.
564 */
565
566 static bool intel_PLL_is_valid(struct drm_device *dev,
567 const intel_limit_t *limit,
568 const intel_clock_t *clock)
569 {
570 if (clock->n < limit->n.min || limit->n.max < clock->n)
571 INTELPllInvalid("n out of range\n");
572 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
573 INTELPllInvalid("p1 out of range\n");
574 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
575 INTELPllInvalid("m2 out of range\n");
576 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
577 INTELPllInvalid("m1 out of range\n");
578
579 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
580 if (clock->m1 <= clock->m2)
581 INTELPllInvalid("m1 <= m2\n");
582
583 if (!IS_VALLEYVIEW(dev)) {
584 if (clock->p < limit->p.min || limit->p.max < clock->p)
585 INTELPllInvalid("p out of range\n");
586 if (clock->m < limit->m.min || limit->m.max < clock->m)
587 INTELPllInvalid("m out of range\n");
588 }
589
590 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
591 INTELPllInvalid("vco out of range\n");
592 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
593 * connector, etc., rather than just a single range.
594 */
595 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
596 INTELPllInvalid("dot out of range\n");
597
598 return true;
599 }
600
601 static bool
602 i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
603 int target, int refclk, intel_clock_t *match_clock,
604 intel_clock_t *best_clock)
605 {
606 struct drm_device *dev = crtc->base.dev;
607 intel_clock_t clock;
608 int err = target;
609
610 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
611 /*
612 * For LVDS just rely on its current settings for dual-channel.
613 * We haven't figured out how to reliably set up different
614 * single/dual channel state, if we even can.
615 */
616 if (intel_is_dual_link_lvds(dev))
617 clock.p2 = limit->p2.p2_fast;
618 else
619 clock.p2 = limit->p2.p2_slow;
620 } else {
621 if (target < limit->p2.dot_limit)
622 clock.p2 = limit->p2.p2_slow;
623 else
624 clock.p2 = limit->p2.p2_fast;
625 }
626
627 memset(best_clock, 0, sizeof(*best_clock));
628
629 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
630 clock.m1++) {
631 for (clock.m2 = limit->m2.min;
632 clock.m2 <= limit->m2.max; clock.m2++) {
633 if (clock.m2 >= clock.m1)
634 break;
635 for (clock.n = limit->n.min;
636 clock.n <= limit->n.max; clock.n++) {
637 for (clock.p1 = limit->p1.min;
638 clock.p1 <= limit->p1.max; clock.p1++) {
639 int this_err;
640
641 i9xx_clock(refclk, &clock);
642 if (!intel_PLL_is_valid(dev, limit,
643 &clock))
644 continue;
645 if (match_clock &&
646 clock.p != match_clock->p)
647 continue;
648
649 this_err = abs(clock.dot - target);
650 if (this_err < err) {
651 *best_clock = clock;
652 err = this_err;
653 }
654 }
655 }
656 }
657 }
658
659 return (err != target);
660 }
661
662 static bool
663 pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
664 int target, int refclk, intel_clock_t *match_clock,
665 intel_clock_t *best_clock)
666 {
667 struct drm_device *dev = crtc->base.dev;
668 intel_clock_t clock;
669 int err = target;
670
671 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
672 /*
673 * For LVDS just rely on its current settings for dual-channel.
674 * We haven't figured out how to reliably set up different
675 * single/dual channel state, if we even can.
676 */
677 if (intel_is_dual_link_lvds(dev))
678 clock.p2 = limit->p2.p2_fast;
679 else
680 clock.p2 = limit->p2.p2_slow;
681 } else {
682 if (target < limit->p2.dot_limit)
683 clock.p2 = limit->p2.p2_slow;
684 else
685 clock.p2 = limit->p2.p2_fast;
686 }
687
688 memset(best_clock, 0, sizeof(*best_clock));
689
690 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
691 clock.m1++) {
692 for (clock.m2 = limit->m2.min;
693 clock.m2 <= limit->m2.max; clock.m2++) {
694 for (clock.n = limit->n.min;
695 clock.n <= limit->n.max; clock.n++) {
696 for (clock.p1 = limit->p1.min;
697 clock.p1 <= limit->p1.max; clock.p1++) {
698 int this_err;
699
700 pineview_clock(refclk, &clock);
701 if (!intel_PLL_is_valid(dev, limit,
702 &clock))
703 continue;
704 if (match_clock &&
705 clock.p != match_clock->p)
706 continue;
707
708 this_err = abs(clock.dot - target);
709 if (this_err < err) {
710 *best_clock = clock;
711 err = this_err;
712 }
713 }
714 }
715 }
716 }
717
718 return (err != target);
719 }
720
721 static bool
722 g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
723 int target, int refclk, intel_clock_t *match_clock,
724 intel_clock_t *best_clock)
725 {
726 struct drm_device *dev = crtc->base.dev;
727 intel_clock_t clock;
728 int max_n;
729 bool found;
730 /* approximately equals target * 0.00585 */
731 int err_most = (target >> 8) + (target >> 9);
732 found = false;
733
734 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
735 if (intel_is_dual_link_lvds(dev))
736 clock.p2 = limit->p2.p2_fast;
737 else
738 clock.p2 = limit->p2.p2_slow;
739 } else {
740 if (target < limit->p2.dot_limit)
741 clock.p2 = limit->p2.p2_slow;
742 else
743 clock.p2 = limit->p2.p2_fast;
744 }
745
746 memset(best_clock, 0, sizeof(*best_clock));
747 max_n = limit->n.max;
748 /* based on hardware requirement, prefer smaller n to precision */
749 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
750 /* based on hardware requirement, prefere larger m1,m2 */
751 for (clock.m1 = limit->m1.max;
752 clock.m1 >= limit->m1.min; clock.m1--) {
753 for (clock.m2 = limit->m2.max;
754 clock.m2 >= limit->m2.min; clock.m2--) {
755 for (clock.p1 = limit->p1.max;
756 clock.p1 >= limit->p1.min; clock.p1--) {
757 int this_err;
758
759 i9xx_clock(refclk, &clock);
760 if (!intel_PLL_is_valid(dev, limit,
761 &clock))
762 continue;
763
764 this_err = abs(clock.dot - target);
765 if (this_err < err_most) {
766 *best_clock = clock;
767 err_most = this_err;
768 max_n = clock.n;
769 found = true;
770 }
771 }
772 }
773 }
774 }
775 return found;
776 }
777
778 static bool
779 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
780 int target, int refclk, intel_clock_t *match_clock,
781 intel_clock_t *best_clock)
782 {
783 struct drm_device *dev = crtc->base.dev;
784 intel_clock_t clock;
785 unsigned int bestppm = 1000000;
786 /* min update 19.2 MHz */
787 int max_n = min(limit->n.max, refclk / 19200);
788 bool found = false;
789
790 target *= 5; /* fast clock */
791
792 memset(best_clock, 0, sizeof(*best_clock));
793
794 /* based on hardware requirement, prefer smaller n to precision */
795 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
796 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
797 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
798 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
799 clock.p = clock.p1 * clock.p2;
800 /* based on hardware requirement, prefer bigger m1,m2 values */
801 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
802 unsigned int ppm, diff;
803
804 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
805 refclk * clock.m1);
806
807 vlv_clock(refclk, &clock);
808
809 if (!intel_PLL_is_valid(dev, limit,
810 &clock))
811 continue;
812
813 diff = abs(clock.dot - target);
814 ppm = div_u64(1000000ULL * diff, target);
815
816 if (ppm < 100 && clock.p > best_clock->p) {
817 bestppm = 0;
818 *best_clock = clock;
819 found = true;
820 }
821
822 if (bestppm >= 10 && ppm < bestppm - 10) {
823 bestppm = ppm;
824 *best_clock = clock;
825 found = true;
826 }
827 }
828 }
829 }
830 }
831
832 return found;
833 }
834
835 static bool
836 chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
837 int target, int refclk, intel_clock_t *match_clock,
838 intel_clock_t *best_clock)
839 {
840 struct drm_device *dev = crtc->base.dev;
841 intel_clock_t clock;
842 uint64_t m2;
843 int found = false;
844
845 memset(best_clock, 0, sizeof(*best_clock));
846
847 /*
848 * Based on hardware doc, the n always set to 1, and m1 always
849 * set to 2. If requires to support 200Mhz refclk, we need to
850 * revisit this because n may not 1 anymore.
851 */
852 clock.n = 1, clock.m1 = 2;
853 target *= 5; /* fast clock */
854
855 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
856 for (clock.p2 = limit->p2.p2_fast;
857 clock.p2 >= limit->p2.p2_slow;
858 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
859
860 clock.p = clock.p1 * clock.p2;
861
862 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
863 clock.n) << 22, refclk * clock.m1);
864
865 if (m2 > INT_MAX/clock.m1)
866 continue;
867
868 clock.m2 = m2;
869
870 chv_clock(refclk, &clock);
871
872 if (!intel_PLL_is_valid(dev, limit, &clock))
873 continue;
874
875 /* based on hardware requirement, prefer bigger p
876 */
877 if (clock.p > best_clock->p) {
878 *best_clock = clock;
879 found = true;
880 }
881 }
882 }
883
884 return found;
885 }
886
887 bool intel_crtc_active(struct drm_crtc *crtc)
888 {
889 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
890
891 /* Be paranoid as we can arrive here with only partial
892 * state retrieved from the hardware during setup.
893 *
894 * We can ditch the adjusted_mode.crtc_clock check as soon
895 * as Haswell has gained clock readout/fastboot support.
896 *
897 * We can ditch the crtc->primary->fb check as soon as we can
898 * properly reconstruct framebuffers.
899 *
900 * FIXME: The intel_crtc->active here should be switched to
901 * crtc->state->active once we have proper CRTC states wired up
902 * for atomic.
903 */
904 return intel_crtc->active && crtc->primary->state->fb &&
905 intel_crtc->config->base.adjusted_mode.crtc_clock;
906 }
907
908 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
909 enum pipe pipe)
910 {
911 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
912 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
913
914 return intel_crtc->config->cpu_transcoder;
915 }
916
917 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
918 {
919 struct drm_i915_private *dev_priv = dev->dev_private;
920 u32 reg = PIPEDSL(pipe);
921 u32 line1, line2;
922 u32 line_mask;
923
924 if (IS_GEN2(dev))
925 line_mask = DSL_LINEMASK_GEN2;
926 else
927 line_mask = DSL_LINEMASK_GEN3;
928
929 line1 = I915_READ(reg) & line_mask;
930 mdelay(5);
931 line2 = I915_READ(reg) & line_mask;
932
933 return line1 == line2;
934 }
935
936 /*
937 * intel_wait_for_pipe_off - wait for pipe to turn off
938 * @crtc: crtc whose pipe to wait for
939 *
940 * After disabling a pipe, we can't wait for vblank in the usual way,
941 * spinning on the vblank interrupt status bit, since we won't actually
942 * see an interrupt when the pipe is disabled.
943 *
944 * On Gen4 and above:
945 * wait for the pipe register state bit to turn off
946 *
947 * Otherwise:
948 * wait for the display line value to settle (it usually
949 * ends up stopping at the start of the next frame).
950 *
951 */
952 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
953 {
954 struct drm_device *dev = crtc->base.dev;
955 struct drm_i915_private *dev_priv = dev->dev_private;
956 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
957 enum pipe pipe = crtc->pipe;
958
959 if (INTEL_INFO(dev)->gen >= 4) {
960 int reg = PIPECONF(cpu_transcoder);
961
962 /* Wait for the Pipe State to go off */
963 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
964 100))
965 WARN(1, "pipe_off wait timed out\n");
966 } else {
967 /* Wait for the display line to settle */
968 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
969 WARN(1, "pipe_off wait timed out\n");
970 }
971 }
972
973 /*
974 * ibx_digital_port_connected - is the specified port connected?
975 * @dev_priv: i915 private structure
976 * @port: the port to test
977 *
978 * Returns true if @port is connected, false otherwise.
979 */
980 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
981 struct intel_digital_port *port)
982 {
983 u32 bit;
984
985 if (HAS_PCH_IBX(dev_priv->dev)) {
986 switch (port->port) {
987 case PORT_B:
988 bit = SDE_PORTB_HOTPLUG;
989 break;
990 case PORT_C:
991 bit = SDE_PORTC_HOTPLUG;
992 break;
993 case PORT_D:
994 bit = SDE_PORTD_HOTPLUG;
995 break;
996 default:
997 return true;
998 }
999 } else {
1000 switch (port->port) {
1001 case PORT_B:
1002 bit = SDE_PORTB_HOTPLUG_CPT;
1003 break;
1004 case PORT_C:
1005 bit = SDE_PORTC_HOTPLUG_CPT;
1006 break;
1007 case PORT_D:
1008 bit = SDE_PORTD_HOTPLUG_CPT;
1009 break;
1010 default:
1011 return true;
1012 }
1013 }
1014
1015 return I915_READ(SDEISR) & bit;
1016 }
1017
1018 static const char *state_string(bool enabled)
1019 {
1020 return enabled ? "on" : "off";
1021 }
1022
1023 /* Only for pre-ILK configs */
1024 void assert_pll(struct drm_i915_private *dev_priv,
1025 enum pipe pipe, bool state)
1026 {
1027 int reg;
1028 u32 val;
1029 bool cur_state;
1030
1031 reg = DPLL(pipe);
1032 val = I915_READ(reg);
1033 cur_state = !!(val & DPLL_VCO_ENABLE);
1034 I915_STATE_WARN(cur_state != state,
1035 "PLL state assertion failure (expected %s, current %s)\n",
1036 state_string(state), state_string(cur_state));
1037 }
1038
1039 /* XXX: the dsi pll is shared between MIPI DSI ports */
1040 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1041 {
1042 u32 val;
1043 bool cur_state;
1044
1045 mutex_lock(&dev_priv->dpio_lock);
1046 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1047 mutex_unlock(&dev_priv->dpio_lock);
1048
1049 cur_state = val & DSI_PLL_VCO_EN;
1050 I915_STATE_WARN(cur_state != state,
1051 "DSI PLL state assertion failure (expected %s, current %s)\n",
1052 state_string(state), state_string(cur_state));
1053 }
1054 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1055 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1056
1057 struct intel_shared_dpll *
1058 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1059 {
1060 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1061
1062 if (crtc->config->shared_dpll < 0)
1063 return NULL;
1064
1065 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1066 }
1067
1068 /* For ILK+ */
1069 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1070 struct intel_shared_dpll *pll,
1071 bool state)
1072 {
1073 bool cur_state;
1074 struct intel_dpll_hw_state hw_state;
1075
1076 if (WARN (!pll,
1077 "asserting DPLL %s with no DPLL\n", state_string(state)))
1078 return;
1079
1080 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1081 I915_STATE_WARN(cur_state != state,
1082 "%s assertion failure (expected %s, current %s)\n",
1083 pll->name, state_string(state), state_string(cur_state));
1084 }
1085
1086 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1087 enum pipe pipe, bool state)
1088 {
1089 int reg;
1090 u32 val;
1091 bool cur_state;
1092 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1093 pipe);
1094
1095 if (HAS_DDI(dev_priv->dev)) {
1096 /* DDI does not have a specific FDI_TX register */
1097 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1098 val = I915_READ(reg);
1099 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1100 } else {
1101 reg = FDI_TX_CTL(pipe);
1102 val = I915_READ(reg);
1103 cur_state = !!(val & FDI_TX_ENABLE);
1104 }
1105 I915_STATE_WARN(cur_state != state,
1106 "FDI TX state assertion failure (expected %s, current %s)\n",
1107 state_string(state), state_string(cur_state));
1108 }
1109 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1110 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1111
1112 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1113 enum pipe pipe, bool state)
1114 {
1115 int reg;
1116 u32 val;
1117 bool cur_state;
1118
1119 reg = FDI_RX_CTL(pipe);
1120 val = I915_READ(reg);
1121 cur_state = !!(val & FDI_RX_ENABLE);
1122 I915_STATE_WARN(cur_state != state,
1123 "FDI RX state assertion failure (expected %s, current %s)\n",
1124 state_string(state), state_string(cur_state));
1125 }
1126 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1127 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1128
1129 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1130 enum pipe pipe)
1131 {
1132 int reg;
1133 u32 val;
1134
1135 /* ILK FDI PLL is always enabled */
1136 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1137 return;
1138
1139 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1140 if (HAS_DDI(dev_priv->dev))
1141 return;
1142
1143 reg = FDI_TX_CTL(pipe);
1144 val = I915_READ(reg);
1145 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1146 }
1147
1148 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1149 enum pipe pipe, bool state)
1150 {
1151 int reg;
1152 u32 val;
1153 bool cur_state;
1154
1155 reg = FDI_RX_CTL(pipe);
1156 val = I915_READ(reg);
1157 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1158 I915_STATE_WARN(cur_state != state,
1159 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1160 state_string(state), state_string(cur_state));
1161 }
1162
1163 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1164 enum pipe pipe)
1165 {
1166 struct drm_device *dev = dev_priv->dev;
1167 int pp_reg;
1168 u32 val;
1169 enum pipe panel_pipe = PIPE_A;
1170 bool locked = true;
1171
1172 if (WARN_ON(HAS_DDI(dev)))
1173 return;
1174
1175 if (HAS_PCH_SPLIT(dev)) {
1176 u32 port_sel;
1177
1178 pp_reg = PCH_PP_CONTROL;
1179 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1180
1181 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1182 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1183 panel_pipe = PIPE_B;
1184 /* XXX: else fix for eDP */
1185 } else if (IS_VALLEYVIEW(dev)) {
1186 /* presumably write lock depends on pipe, not port select */
1187 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1188 panel_pipe = pipe;
1189 } else {
1190 pp_reg = PP_CONTROL;
1191 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1192 panel_pipe = PIPE_B;
1193 }
1194
1195 val = I915_READ(pp_reg);
1196 if (!(val & PANEL_POWER_ON) ||
1197 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1198 locked = false;
1199
1200 I915_STATE_WARN(panel_pipe == pipe && locked,
1201 "panel assertion failure, pipe %c regs locked\n",
1202 pipe_name(pipe));
1203 }
1204
1205 static void assert_cursor(struct drm_i915_private *dev_priv,
1206 enum pipe pipe, bool state)
1207 {
1208 struct drm_device *dev = dev_priv->dev;
1209 bool cur_state;
1210
1211 if (IS_845G(dev) || IS_I865G(dev))
1212 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1213 else
1214 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1215
1216 I915_STATE_WARN(cur_state != state,
1217 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1218 pipe_name(pipe), state_string(state), state_string(cur_state));
1219 }
1220 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1221 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1222
1223 void assert_pipe(struct drm_i915_private *dev_priv,
1224 enum pipe pipe, bool state)
1225 {
1226 int reg;
1227 u32 val;
1228 bool cur_state;
1229 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1230 pipe);
1231
1232 /* if we need the pipe quirk it must be always on */
1233 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1234 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1235 state = true;
1236
1237 if (!intel_display_power_is_enabled(dev_priv,
1238 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1239 cur_state = false;
1240 } else {
1241 reg = PIPECONF(cpu_transcoder);
1242 val = I915_READ(reg);
1243 cur_state = !!(val & PIPECONF_ENABLE);
1244 }
1245
1246 I915_STATE_WARN(cur_state != state,
1247 "pipe %c assertion failure (expected %s, current %s)\n",
1248 pipe_name(pipe), state_string(state), state_string(cur_state));
1249 }
1250
1251 static void assert_plane(struct drm_i915_private *dev_priv,
1252 enum plane plane, bool state)
1253 {
1254 int reg;
1255 u32 val;
1256 bool cur_state;
1257
1258 reg = DSPCNTR(plane);
1259 val = I915_READ(reg);
1260 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1261 I915_STATE_WARN(cur_state != state,
1262 "plane %c assertion failure (expected %s, current %s)\n",
1263 plane_name(plane), state_string(state), state_string(cur_state));
1264 }
1265
1266 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1267 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1268
1269 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1270 enum pipe pipe)
1271 {
1272 struct drm_device *dev = dev_priv->dev;
1273 int reg, i;
1274 u32 val;
1275 int cur_pipe;
1276
1277 /* Primary planes are fixed to pipes on gen4+ */
1278 if (INTEL_INFO(dev)->gen >= 4) {
1279 reg = DSPCNTR(pipe);
1280 val = I915_READ(reg);
1281 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1282 "plane %c assertion failure, should be disabled but not\n",
1283 plane_name(pipe));
1284 return;
1285 }
1286
1287 /* Need to check both planes against the pipe */
1288 for_each_pipe(dev_priv, i) {
1289 reg = DSPCNTR(i);
1290 val = I915_READ(reg);
1291 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1292 DISPPLANE_SEL_PIPE_SHIFT;
1293 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1294 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1295 plane_name(i), pipe_name(pipe));
1296 }
1297 }
1298
1299 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1300 enum pipe pipe)
1301 {
1302 struct drm_device *dev = dev_priv->dev;
1303 int reg, sprite;
1304 u32 val;
1305
1306 if (INTEL_INFO(dev)->gen >= 9) {
1307 for_each_sprite(dev_priv, pipe, sprite) {
1308 val = I915_READ(PLANE_CTL(pipe, sprite));
1309 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1310 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1311 sprite, pipe_name(pipe));
1312 }
1313 } else if (IS_VALLEYVIEW(dev)) {
1314 for_each_sprite(dev_priv, pipe, sprite) {
1315 reg = SPCNTR(pipe, sprite);
1316 val = I915_READ(reg);
1317 I915_STATE_WARN(val & SP_ENABLE,
1318 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1319 sprite_name(pipe, sprite), pipe_name(pipe));
1320 }
1321 } else if (INTEL_INFO(dev)->gen >= 7) {
1322 reg = SPRCTL(pipe);
1323 val = I915_READ(reg);
1324 I915_STATE_WARN(val & SPRITE_ENABLE,
1325 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1326 plane_name(pipe), pipe_name(pipe));
1327 } else if (INTEL_INFO(dev)->gen >= 5) {
1328 reg = DVSCNTR(pipe);
1329 val = I915_READ(reg);
1330 I915_STATE_WARN(val & DVS_ENABLE,
1331 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1332 plane_name(pipe), pipe_name(pipe));
1333 }
1334 }
1335
1336 static void assert_vblank_disabled(struct drm_crtc *crtc)
1337 {
1338 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1339 drm_crtc_vblank_put(crtc);
1340 }
1341
1342 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1343 {
1344 u32 val;
1345 bool enabled;
1346
1347 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1348
1349 val = I915_READ(PCH_DREF_CONTROL);
1350 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1351 DREF_SUPERSPREAD_SOURCE_MASK));
1352 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1353 }
1354
1355 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1356 enum pipe pipe)
1357 {
1358 int reg;
1359 u32 val;
1360 bool enabled;
1361
1362 reg = PCH_TRANSCONF(pipe);
1363 val = I915_READ(reg);
1364 enabled = !!(val & TRANS_ENABLE);
1365 I915_STATE_WARN(enabled,
1366 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1367 pipe_name(pipe));
1368 }
1369
1370 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1371 enum pipe pipe, u32 port_sel, u32 val)
1372 {
1373 if ((val & DP_PORT_EN) == 0)
1374 return false;
1375
1376 if (HAS_PCH_CPT(dev_priv->dev)) {
1377 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1378 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1379 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1380 return false;
1381 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1382 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1383 return false;
1384 } else {
1385 if ((val & DP_PIPE_MASK) != (pipe << 30))
1386 return false;
1387 }
1388 return true;
1389 }
1390
1391 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1392 enum pipe pipe, u32 val)
1393 {
1394 if ((val & SDVO_ENABLE) == 0)
1395 return false;
1396
1397 if (HAS_PCH_CPT(dev_priv->dev)) {
1398 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1399 return false;
1400 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1401 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1402 return false;
1403 } else {
1404 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1405 return false;
1406 }
1407 return true;
1408 }
1409
1410 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1411 enum pipe pipe, u32 val)
1412 {
1413 if ((val & LVDS_PORT_EN) == 0)
1414 return false;
1415
1416 if (HAS_PCH_CPT(dev_priv->dev)) {
1417 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1418 return false;
1419 } else {
1420 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1421 return false;
1422 }
1423 return true;
1424 }
1425
1426 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1427 enum pipe pipe, u32 val)
1428 {
1429 if ((val & ADPA_DAC_ENABLE) == 0)
1430 return false;
1431 if (HAS_PCH_CPT(dev_priv->dev)) {
1432 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1433 return false;
1434 } else {
1435 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1436 return false;
1437 }
1438 return true;
1439 }
1440
1441 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1442 enum pipe pipe, int reg, u32 port_sel)
1443 {
1444 u32 val = I915_READ(reg);
1445 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1446 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1447 reg, pipe_name(pipe));
1448
1449 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1450 && (val & DP_PIPEB_SELECT),
1451 "IBX PCH dp port still using transcoder B\n");
1452 }
1453
1454 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1455 enum pipe pipe, int reg)
1456 {
1457 u32 val = I915_READ(reg);
1458 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1459 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1460 reg, pipe_name(pipe));
1461
1462 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1463 && (val & SDVO_PIPE_B_SELECT),
1464 "IBX PCH hdmi port still using transcoder B\n");
1465 }
1466
1467 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1468 enum pipe pipe)
1469 {
1470 int reg;
1471 u32 val;
1472
1473 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1474 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1475 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1476
1477 reg = PCH_ADPA;
1478 val = I915_READ(reg);
1479 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1480 "PCH VGA enabled on transcoder %c, should be disabled\n",
1481 pipe_name(pipe));
1482
1483 reg = PCH_LVDS;
1484 val = I915_READ(reg);
1485 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1486 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1487 pipe_name(pipe));
1488
1489 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1490 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1491 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1492 }
1493
1494 static void intel_init_dpio(struct drm_device *dev)
1495 {
1496 struct drm_i915_private *dev_priv = dev->dev_private;
1497
1498 if (!IS_VALLEYVIEW(dev))
1499 return;
1500
1501 /*
1502 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1503 * CHV x1 PHY (DP/HDMI D)
1504 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1505 */
1506 if (IS_CHERRYVIEW(dev)) {
1507 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1508 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1509 } else {
1510 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1511 }
1512 }
1513
1514 static void vlv_enable_pll(struct intel_crtc *crtc,
1515 const struct intel_crtc_state *pipe_config)
1516 {
1517 struct drm_device *dev = crtc->base.dev;
1518 struct drm_i915_private *dev_priv = dev->dev_private;
1519 int reg = DPLL(crtc->pipe);
1520 u32 dpll = pipe_config->dpll_hw_state.dpll;
1521
1522 assert_pipe_disabled(dev_priv, crtc->pipe);
1523
1524 /* No really, not for ILK+ */
1525 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1526
1527 /* PLL is protected by panel, make sure we can write it */
1528 if (IS_MOBILE(dev_priv->dev))
1529 assert_panel_unlocked(dev_priv, crtc->pipe);
1530
1531 I915_WRITE(reg, dpll);
1532 POSTING_READ(reg);
1533 udelay(150);
1534
1535 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1536 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1537
1538 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1539 POSTING_READ(DPLL_MD(crtc->pipe));
1540
1541 /* We do this three times for luck */
1542 I915_WRITE(reg, dpll);
1543 POSTING_READ(reg);
1544 udelay(150); /* wait for warmup */
1545 I915_WRITE(reg, dpll);
1546 POSTING_READ(reg);
1547 udelay(150); /* wait for warmup */
1548 I915_WRITE(reg, dpll);
1549 POSTING_READ(reg);
1550 udelay(150); /* wait for warmup */
1551 }
1552
1553 static void chv_enable_pll(struct intel_crtc *crtc,
1554 const struct intel_crtc_state *pipe_config)
1555 {
1556 struct drm_device *dev = crtc->base.dev;
1557 struct drm_i915_private *dev_priv = dev->dev_private;
1558 int pipe = crtc->pipe;
1559 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1560 u32 tmp;
1561
1562 assert_pipe_disabled(dev_priv, crtc->pipe);
1563
1564 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1565
1566 mutex_lock(&dev_priv->dpio_lock);
1567
1568 /* Enable back the 10bit clock to display controller */
1569 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1570 tmp |= DPIO_DCLKP_EN;
1571 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1572
1573 /*
1574 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1575 */
1576 udelay(1);
1577
1578 /* Enable PLL */
1579 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1580
1581 /* Check PLL is locked */
1582 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1583 DRM_ERROR("PLL %d failed to lock\n", pipe);
1584
1585 /* not sure when this should be written */
1586 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1587 POSTING_READ(DPLL_MD(pipe));
1588
1589 mutex_unlock(&dev_priv->dpio_lock);
1590 }
1591
1592 static int intel_num_dvo_pipes(struct drm_device *dev)
1593 {
1594 struct intel_crtc *crtc;
1595 int count = 0;
1596
1597 for_each_intel_crtc(dev, crtc)
1598 count += crtc->active &&
1599 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1600
1601 return count;
1602 }
1603
1604 static void i9xx_enable_pll(struct intel_crtc *crtc)
1605 {
1606 struct drm_device *dev = crtc->base.dev;
1607 struct drm_i915_private *dev_priv = dev->dev_private;
1608 int reg = DPLL(crtc->pipe);
1609 u32 dpll = crtc->config->dpll_hw_state.dpll;
1610
1611 assert_pipe_disabled(dev_priv, crtc->pipe);
1612
1613 /* No really, not for ILK+ */
1614 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1615
1616 /* PLL is protected by panel, make sure we can write it */
1617 if (IS_MOBILE(dev) && !IS_I830(dev))
1618 assert_panel_unlocked(dev_priv, crtc->pipe);
1619
1620 /* Enable DVO 2x clock on both PLLs if necessary */
1621 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1622 /*
1623 * It appears to be important that we don't enable this
1624 * for the current pipe before otherwise configuring the
1625 * PLL. No idea how this should be handled if multiple
1626 * DVO outputs are enabled simultaneosly.
1627 */
1628 dpll |= DPLL_DVO_2X_MODE;
1629 I915_WRITE(DPLL(!crtc->pipe),
1630 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1631 }
1632
1633 /* Wait for the clocks to stabilize. */
1634 POSTING_READ(reg);
1635 udelay(150);
1636
1637 if (INTEL_INFO(dev)->gen >= 4) {
1638 I915_WRITE(DPLL_MD(crtc->pipe),
1639 crtc->config->dpll_hw_state.dpll_md);
1640 } else {
1641 /* The pixel multiplier can only be updated once the
1642 * DPLL is enabled and the clocks are stable.
1643 *
1644 * So write it again.
1645 */
1646 I915_WRITE(reg, dpll);
1647 }
1648
1649 /* We do this three times for luck */
1650 I915_WRITE(reg, dpll);
1651 POSTING_READ(reg);
1652 udelay(150); /* wait for warmup */
1653 I915_WRITE(reg, dpll);
1654 POSTING_READ(reg);
1655 udelay(150); /* wait for warmup */
1656 I915_WRITE(reg, dpll);
1657 POSTING_READ(reg);
1658 udelay(150); /* wait for warmup */
1659 }
1660
1661 /**
1662 * i9xx_disable_pll - disable a PLL
1663 * @dev_priv: i915 private structure
1664 * @pipe: pipe PLL to disable
1665 *
1666 * Disable the PLL for @pipe, making sure the pipe is off first.
1667 *
1668 * Note! This is for pre-ILK only.
1669 */
1670 static void i9xx_disable_pll(struct intel_crtc *crtc)
1671 {
1672 struct drm_device *dev = crtc->base.dev;
1673 struct drm_i915_private *dev_priv = dev->dev_private;
1674 enum pipe pipe = crtc->pipe;
1675
1676 /* Disable DVO 2x clock on both PLLs if necessary */
1677 if (IS_I830(dev) &&
1678 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1679 intel_num_dvo_pipes(dev) == 1) {
1680 I915_WRITE(DPLL(PIPE_B),
1681 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1682 I915_WRITE(DPLL(PIPE_A),
1683 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1684 }
1685
1686 /* Don't disable pipe or pipe PLLs if needed */
1687 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1688 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1689 return;
1690
1691 /* Make sure the pipe isn't still relying on us */
1692 assert_pipe_disabled(dev_priv, pipe);
1693
1694 I915_WRITE(DPLL(pipe), 0);
1695 POSTING_READ(DPLL(pipe));
1696 }
1697
1698 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1699 {
1700 u32 val = 0;
1701
1702 /* Make sure the pipe isn't still relying on us */
1703 assert_pipe_disabled(dev_priv, pipe);
1704
1705 /*
1706 * Leave integrated clock source and reference clock enabled for pipe B.
1707 * The latter is needed for VGA hotplug / manual detection.
1708 */
1709 if (pipe == PIPE_B)
1710 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1711 I915_WRITE(DPLL(pipe), val);
1712 POSTING_READ(DPLL(pipe));
1713
1714 }
1715
1716 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1717 {
1718 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1719 u32 val;
1720
1721 /* Make sure the pipe isn't still relying on us */
1722 assert_pipe_disabled(dev_priv, pipe);
1723
1724 /* Set PLL en = 0 */
1725 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1726 if (pipe != PIPE_A)
1727 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1728 I915_WRITE(DPLL(pipe), val);
1729 POSTING_READ(DPLL(pipe));
1730
1731 mutex_lock(&dev_priv->dpio_lock);
1732
1733 /* Disable 10bit clock to display controller */
1734 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1735 val &= ~DPIO_DCLKP_EN;
1736 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1737
1738 /* disable left/right clock distribution */
1739 if (pipe != PIPE_B) {
1740 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1741 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1742 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1743 } else {
1744 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1745 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1746 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1747 }
1748
1749 mutex_unlock(&dev_priv->dpio_lock);
1750 }
1751
1752 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1753 struct intel_digital_port *dport)
1754 {
1755 u32 port_mask;
1756 int dpll_reg;
1757
1758 switch (dport->port) {
1759 case PORT_B:
1760 port_mask = DPLL_PORTB_READY_MASK;
1761 dpll_reg = DPLL(0);
1762 break;
1763 case PORT_C:
1764 port_mask = DPLL_PORTC_READY_MASK;
1765 dpll_reg = DPLL(0);
1766 break;
1767 case PORT_D:
1768 port_mask = DPLL_PORTD_READY_MASK;
1769 dpll_reg = DPIO_PHY_STATUS;
1770 break;
1771 default:
1772 BUG();
1773 }
1774
1775 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1776 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1777 port_name(dport->port), I915_READ(dpll_reg));
1778 }
1779
1780 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1781 {
1782 struct drm_device *dev = crtc->base.dev;
1783 struct drm_i915_private *dev_priv = dev->dev_private;
1784 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1785
1786 if (WARN_ON(pll == NULL))
1787 return;
1788
1789 WARN_ON(!pll->config.crtc_mask);
1790 if (pll->active == 0) {
1791 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1792 WARN_ON(pll->on);
1793 assert_shared_dpll_disabled(dev_priv, pll);
1794
1795 pll->mode_set(dev_priv, pll);
1796 }
1797 }
1798
1799 /**
1800 * intel_enable_shared_dpll - enable PCH PLL
1801 * @dev_priv: i915 private structure
1802 * @pipe: pipe PLL to enable
1803 *
1804 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1805 * drives the transcoder clock.
1806 */
1807 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1808 {
1809 struct drm_device *dev = crtc->base.dev;
1810 struct drm_i915_private *dev_priv = dev->dev_private;
1811 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1812
1813 if (WARN_ON(pll == NULL))
1814 return;
1815
1816 if (WARN_ON(pll->config.crtc_mask == 0))
1817 return;
1818
1819 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1820 pll->name, pll->active, pll->on,
1821 crtc->base.base.id);
1822
1823 if (pll->active++) {
1824 WARN_ON(!pll->on);
1825 assert_shared_dpll_enabled(dev_priv, pll);
1826 return;
1827 }
1828 WARN_ON(pll->on);
1829
1830 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1831
1832 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1833 pll->enable(dev_priv, pll);
1834 pll->on = true;
1835 }
1836
1837 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1838 {
1839 struct drm_device *dev = crtc->base.dev;
1840 struct drm_i915_private *dev_priv = dev->dev_private;
1841 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1842
1843 /* PCH only available on ILK+ */
1844 BUG_ON(INTEL_INFO(dev)->gen < 5);
1845 if (WARN_ON(pll == NULL))
1846 return;
1847
1848 if (WARN_ON(pll->config.crtc_mask == 0))
1849 return;
1850
1851 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1852 pll->name, pll->active, pll->on,
1853 crtc->base.base.id);
1854
1855 if (WARN_ON(pll->active == 0)) {
1856 assert_shared_dpll_disabled(dev_priv, pll);
1857 return;
1858 }
1859
1860 assert_shared_dpll_enabled(dev_priv, pll);
1861 WARN_ON(!pll->on);
1862 if (--pll->active)
1863 return;
1864
1865 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1866 pll->disable(dev_priv, pll);
1867 pll->on = false;
1868
1869 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1870 }
1871
1872 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1873 enum pipe pipe)
1874 {
1875 struct drm_device *dev = dev_priv->dev;
1876 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1877 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1878 uint32_t reg, val, pipeconf_val;
1879
1880 /* PCH only available on ILK+ */
1881 BUG_ON(!HAS_PCH_SPLIT(dev));
1882
1883 /* Make sure PCH DPLL is enabled */
1884 assert_shared_dpll_enabled(dev_priv,
1885 intel_crtc_to_shared_dpll(intel_crtc));
1886
1887 /* FDI must be feeding us bits for PCH ports */
1888 assert_fdi_tx_enabled(dev_priv, pipe);
1889 assert_fdi_rx_enabled(dev_priv, pipe);
1890
1891 if (HAS_PCH_CPT(dev)) {
1892 /* Workaround: Set the timing override bit before enabling the
1893 * pch transcoder. */
1894 reg = TRANS_CHICKEN2(pipe);
1895 val = I915_READ(reg);
1896 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1897 I915_WRITE(reg, val);
1898 }
1899
1900 reg = PCH_TRANSCONF(pipe);
1901 val = I915_READ(reg);
1902 pipeconf_val = I915_READ(PIPECONF(pipe));
1903
1904 if (HAS_PCH_IBX(dev_priv->dev)) {
1905 /*
1906 * make the BPC in transcoder be consistent with
1907 * that in pipeconf reg.
1908 */
1909 val &= ~PIPECONF_BPC_MASK;
1910 val |= pipeconf_val & PIPECONF_BPC_MASK;
1911 }
1912
1913 val &= ~TRANS_INTERLACE_MASK;
1914 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1915 if (HAS_PCH_IBX(dev_priv->dev) &&
1916 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1917 val |= TRANS_LEGACY_INTERLACED_ILK;
1918 else
1919 val |= TRANS_INTERLACED;
1920 else
1921 val |= TRANS_PROGRESSIVE;
1922
1923 I915_WRITE(reg, val | TRANS_ENABLE);
1924 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1925 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1926 }
1927
1928 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1929 enum transcoder cpu_transcoder)
1930 {
1931 u32 val, pipeconf_val;
1932
1933 /* PCH only available on ILK+ */
1934 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1935
1936 /* FDI must be feeding us bits for PCH ports */
1937 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1938 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1939
1940 /* Workaround: set timing override bit. */
1941 val = I915_READ(_TRANSA_CHICKEN2);
1942 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1943 I915_WRITE(_TRANSA_CHICKEN2, val);
1944
1945 val = TRANS_ENABLE;
1946 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1947
1948 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1949 PIPECONF_INTERLACED_ILK)
1950 val |= TRANS_INTERLACED;
1951 else
1952 val |= TRANS_PROGRESSIVE;
1953
1954 I915_WRITE(LPT_TRANSCONF, val);
1955 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1956 DRM_ERROR("Failed to enable PCH transcoder\n");
1957 }
1958
1959 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1960 enum pipe pipe)
1961 {
1962 struct drm_device *dev = dev_priv->dev;
1963 uint32_t reg, val;
1964
1965 /* FDI relies on the transcoder */
1966 assert_fdi_tx_disabled(dev_priv, pipe);
1967 assert_fdi_rx_disabled(dev_priv, pipe);
1968
1969 /* Ports must be off as well */
1970 assert_pch_ports_disabled(dev_priv, pipe);
1971
1972 reg = PCH_TRANSCONF(pipe);
1973 val = I915_READ(reg);
1974 val &= ~TRANS_ENABLE;
1975 I915_WRITE(reg, val);
1976 /* wait for PCH transcoder off, transcoder state */
1977 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1978 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1979
1980 if (!HAS_PCH_IBX(dev)) {
1981 /* Workaround: Clear the timing override chicken bit again. */
1982 reg = TRANS_CHICKEN2(pipe);
1983 val = I915_READ(reg);
1984 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1985 I915_WRITE(reg, val);
1986 }
1987 }
1988
1989 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1990 {
1991 u32 val;
1992
1993 val = I915_READ(LPT_TRANSCONF);
1994 val &= ~TRANS_ENABLE;
1995 I915_WRITE(LPT_TRANSCONF, val);
1996 /* wait for PCH transcoder off, transcoder state */
1997 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1998 DRM_ERROR("Failed to disable PCH transcoder\n");
1999
2000 /* Workaround: clear timing override bit. */
2001 val = I915_READ(_TRANSA_CHICKEN2);
2002 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2003 I915_WRITE(_TRANSA_CHICKEN2, val);
2004 }
2005
2006 /**
2007 * intel_enable_pipe - enable a pipe, asserting requirements
2008 * @crtc: crtc responsible for the pipe
2009 *
2010 * Enable @crtc's pipe, making sure that various hardware specific requirements
2011 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2012 */
2013 static void intel_enable_pipe(struct intel_crtc *crtc)
2014 {
2015 struct drm_device *dev = crtc->base.dev;
2016 struct drm_i915_private *dev_priv = dev->dev_private;
2017 enum pipe pipe = crtc->pipe;
2018 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2019 pipe);
2020 enum pipe pch_transcoder;
2021 int reg;
2022 u32 val;
2023
2024 assert_planes_disabled(dev_priv, pipe);
2025 assert_cursor_disabled(dev_priv, pipe);
2026 assert_sprites_disabled(dev_priv, pipe);
2027
2028 if (HAS_PCH_LPT(dev_priv->dev))
2029 pch_transcoder = TRANSCODER_A;
2030 else
2031 pch_transcoder = pipe;
2032
2033 /*
2034 * A pipe without a PLL won't actually be able to drive bits from
2035 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2036 * need the check.
2037 */
2038 if (!HAS_PCH_SPLIT(dev_priv->dev))
2039 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2040 assert_dsi_pll_enabled(dev_priv);
2041 else
2042 assert_pll_enabled(dev_priv, pipe);
2043 else {
2044 if (crtc->config->has_pch_encoder) {
2045 /* if driving the PCH, we need FDI enabled */
2046 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2047 assert_fdi_tx_pll_enabled(dev_priv,
2048 (enum pipe) cpu_transcoder);
2049 }
2050 /* FIXME: assert CPU port conditions for SNB+ */
2051 }
2052
2053 reg = PIPECONF(cpu_transcoder);
2054 val = I915_READ(reg);
2055 if (val & PIPECONF_ENABLE) {
2056 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2057 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2058 return;
2059 }
2060
2061 I915_WRITE(reg, val | PIPECONF_ENABLE);
2062 POSTING_READ(reg);
2063 }
2064
2065 /**
2066 * intel_disable_pipe - disable a pipe, asserting requirements
2067 * @crtc: crtc whose pipes is to be disabled
2068 *
2069 * Disable the pipe of @crtc, making sure that various hardware
2070 * specific requirements are met, if applicable, e.g. plane
2071 * disabled, panel fitter off, etc.
2072 *
2073 * Will wait until the pipe has shut down before returning.
2074 */
2075 static void intel_disable_pipe(struct intel_crtc *crtc)
2076 {
2077 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2078 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2079 enum pipe pipe = crtc->pipe;
2080 int reg;
2081 u32 val;
2082
2083 /*
2084 * Make sure planes won't keep trying to pump pixels to us,
2085 * or we might hang the display.
2086 */
2087 assert_planes_disabled(dev_priv, pipe);
2088 assert_cursor_disabled(dev_priv, pipe);
2089 assert_sprites_disabled(dev_priv, pipe);
2090
2091 reg = PIPECONF(cpu_transcoder);
2092 val = I915_READ(reg);
2093 if ((val & PIPECONF_ENABLE) == 0)
2094 return;
2095
2096 /*
2097 * Double wide has implications for planes
2098 * so best keep it disabled when not needed.
2099 */
2100 if (crtc->config->double_wide)
2101 val &= ~PIPECONF_DOUBLE_WIDE;
2102
2103 /* Don't disable pipe or pipe PLLs if needed */
2104 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2105 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2106 val &= ~PIPECONF_ENABLE;
2107
2108 I915_WRITE(reg, val);
2109 if ((val & PIPECONF_ENABLE) == 0)
2110 intel_wait_for_pipe_off(crtc);
2111 }
2112
2113 /*
2114 * Plane regs are double buffered, going from enabled->disabled needs a
2115 * trigger in order to latch. The display address reg provides this.
2116 */
2117 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2118 enum plane plane)
2119 {
2120 struct drm_device *dev = dev_priv->dev;
2121 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2122
2123 I915_WRITE(reg, I915_READ(reg));
2124 POSTING_READ(reg);
2125 }
2126
2127 /**
2128 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2129 * @plane: plane to be enabled
2130 * @crtc: crtc for the plane
2131 *
2132 * Enable @plane on @crtc, making sure that the pipe is running first.
2133 */
2134 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2135 struct drm_crtc *crtc)
2136 {
2137 struct drm_device *dev = plane->dev;
2138 struct drm_i915_private *dev_priv = dev->dev_private;
2139 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2140
2141 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2142 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2143
2144 if (intel_crtc->primary_enabled)
2145 return;
2146
2147 intel_crtc->primary_enabled = true;
2148
2149 dev_priv->display.update_primary_plane(crtc, plane->fb,
2150 crtc->x, crtc->y);
2151
2152 /*
2153 * BDW signals flip done immediately if the plane
2154 * is disabled, even if the plane enable is already
2155 * armed to occur at the next vblank :(
2156 */
2157 if (IS_BROADWELL(dev))
2158 intel_wait_for_vblank(dev, intel_crtc->pipe);
2159 }
2160
2161 /**
2162 * intel_disable_primary_hw_plane - disable the primary hardware plane
2163 * @plane: plane to be disabled
2164 * @crtc: crtc for the plane
2165 *
2166 * Disable @plane on @crtc, making sure that the pipe is running first.
2167 */
2168 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2169 struct drm_crtc *crtc)
2170 {
2171 struct drm_device *dev = plane->dev;
2172 struct drm_i915_private *dev_priv = dev->dev_private;
2173 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2174
2175 if (WARN_ON(!intel_crtc->active))
2176 return;
2177
2178 if (!intel_crtc->primary_enabled)
2179 return;
2180
2181 intel_crtc->primary_enabled = false;
2182
2183 dev_priv->display.update_primary_plane(crtc, plane->fb,
2184 crtc->x, crtc->y);
2185 }
2186
2187 static bool need_vtd_wa(struct drm_device *dev)
2188 {
2189 #ifdef CONFIG_INTEL_IOMMU
2190 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2191 return true;
2192 #endif
2193 return false;
2194 }
2195
2196 int
2197 intel_fb_align_height(struct drm_device *dev, int height,
2198 uint32_t pixel_format,
2199 uint64_t fb_format_modifier)
2200 {
2201 int tile_height;
2202 uint32_t bits_per_pixel;
2203
2204 switch (fb_format_modifier) {
2205 case DRM_FORMAT_MOD_NONE:
2206 tile_height = 1;
2207 break;
2208 case I915_FORMAT_MOD_X_TILED:
2209 tile_height = IS_GEN2(dev) ? 16 : 8;
2210 break;
2211 case I915_FORMAT_MOD_Y_TILED:
2212 tile_height = 32;
2213 break;
2214 case I915_FORMAT_MOD_Yf_TILED:
2215 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2216 switch (bits_per_pixel) {
2217 default:
2218 case 8:
2219 tile_height = 64;
2220 break;
2221 case 16:
2222 case 32:
2223 tile_height = 32;
2224 break;
2225 case 64:
2226 tile_height = 16;
2227 break;
2228 case 128:
2229 WARN_ONCE(1,
2230 "128-bit pixels are not supported for display!");
2231 tile_height = 16;
2232 break;
2233 }
2234 break;
2235 default:
2236 MISSING_CASE(fb_format_modifier);
2237 tile_height = 1;
2238 break;
2239 }
2240
2241 return ALIGN(height, tile_height);
2242 }
2243
2244 int
2245 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2246 struct drm_framebuffer *fb,
2247 struct intel_engine_cs *pipelined)
2248 {
2249 struct drm_device *dev = fb->dev;
2250 struct drm_i915_private *dev_priv = dev->dev_private;
2251 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2252 u32 alignment;
2253 int ret;
2254
2255 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2256
2257 switch (fb->modifier[0]) {
2258 case DRM_FORMAT_MOD_NONE:
2259 if (INTEL_INFO(dev)->gen >= 9)
2260 alignment = 256 * 1024;
2261 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2262 alignment = 128 * 1024;
2263 else if (INTEL_INFO(dev)->gen >= 4)
2264 alignment = 4 * 1024;
2265 else
2266 alignment = 64 * 1024;
2267 break;
2268 case I915_FORMAT_MOD_X_TILED:
2269 if (INTEL_INFO(dev)->gen >= 9)
2270 alignment = 256 * 1024;
2271 else {
2272 /* pin() will align the object as required by fence */
2273 alignment = 0;
2274 }
2275 break;
2276 case I915_FORMAT_MOD_Y_TILED:
2277 case I915_FORMAT_MOD_Yf_TILED:
2278 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2279 "Y tiling bo slipped through, driver bug!\n"))
2280 return -EINVAL;
2281 alignment = 1 * 1024 * 1024;
2282 break;
2283 default:
2284 MISSING_CASE(fb->modifier[0]);
2285 return -EINVAL;
2286 }
2287
2288 /* Note that the w/a also requires 64 PTE of padding following the
2289 * bo. We currently fill all unused PTE with the shadow page and so
2290 * we should always have valid PTE following the scanout preventing
2291 * the VT-d warning.
2292 */
2293 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2294 alignment = 256 * 1024;
2295
2296 /*
2297 * Global gtt pte registers are special registers which actually forward
2298 * writes to a chunk of system memory. Which means that there is no risk
2299 * that the register values disappear as soon as we call
2300 * intel_runtime_pm_put(), so it is correct to wrap only the
2301 * pin/unpin/fence and not more.
2302 */
2303 intel_runtime_pm_get(dev_priv);
2304
2305 dev_priv->mm.interruptible = false;
2306 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2307 if (ret)
2308 goto err_interruptible;
2309
2310 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2311 * fence, whereas 965+ only requires a fence if using
2312 * framebuffer compression. For simplicity, we always install
2313 * a fence as the cost is not that onerous.
2314 */
2315 ret = i915_gem_object_get_fence(obj);
2316 if (ret)
2317 goto err_unpin;
2318
2319 i915_gem_object_pin_fence(obj);
2320
2321 dev_priv->mm.interruptible = true;
2322 intel_runtime_pm_put(dev_priv);
2323 return 0;
2324
2325 err_unpin:
2326 i915_gem_object_unpin_from_display_plane(obj);
2327 err_interruptible:
2328 dev_priv->mm.interruptible = true;
2329 intel_runtime_pm_put(dev_priv);
2330 return ret;
2331 }
2332
2333 static void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2334 {
2335 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2336
2337 i915_gem_object_unpin_fence(obj);
2338 i915_gem_object_unpin_from_display_plane(obj);
2339 }
2340
2341 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2342 * is assumed to be a power-of-two. */
2343 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2344 unsigned int tiling_mode,
2345 unsigned int cpp,
2346 unsigned int pitch)
2347 {
2348 if (tiling_mode != I915_TILING_NONE) {
2349 unsigned int tile_rows, tiles;
2350
2351 tile_rows = *y / 8;
2352 *y %= 8;
2353
2354 tiles = *x / (512/cpp);
2355 *x %= 512/cpp;
2356
2357 return tile_rows * pitch * 8 + tiles * 4096;
2358 } else {
2359 unsigned int offset;
2360
2361 offset = *y * pitch + *x * cpp;
2362 *y = 0;
2363 *x = (offset & 4095) / cpp;
2364 return offset & -4096;
2365 }
2366 }
2367
2368 static int i9xx_format_to_fourcc(int format)
2369 {
2370 switch (format) {
2371 case DISPPLANE_8BPP:
2372 return DRM_FORMAT_C8;
2373 case DISPPLANE_BGRX555:
2374 return DRM_FORMAT_XRGB1555;
2375 case DISPPLANE_BGRX565:
2376 return DRM_FORMAT_RGB565;
2377 default:
2378 case DISPPLANE_BGRX888:
2379 return DRM_FORMAT_XRGB8888;
2380 case DISPPLANE_RGBX888:
2381 return DRM_FORMAT_XBGR8888;
2382 case DISPPLANE_BGRX101010:
2383 return DRM_FORMAT_XRGB2101010;
2384 case DISPPLANE_RGBX101010:
2385 return DRM_FORMAT_XBGR2101010;
2386 }
2387 }
2388
2389 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2390 {
2391 switch (format) {
2392 case PLANE_CTL_FORMAT_RGB_565:
2393 return DRM_FORMAT_RGB565;
2394 default:
2395 case PLANE_CTL_FORMAT_XRGB_8888:
2396 if (rgb_order) {
2397 if (alpha)
2398 return DRM_FORMAT_ABGR8888;
2399 else
2400 return DRM_FORMAT_XBGR8888;
2401 } else {
2402 if (alpha)
2403 return DRM_FORMAT_ARGB8888;
2404 else
2405 return DRM_FORMAT_XRGB8888;
2406 }
2407 case PLANE_CTL_FORMAT_XRGB_2101010:
2408 if (rgb_order)
2409 return DRM_FORMAT_XBGR2101010;
2410 else
2411 return DRM_FORMAT_XRGB2101010;
2412 }
2413 }
2414
2415 static bool
2416 intel_alloc_plane_obj(struct intel_crtc *crtc,
2417 struct intel_initial_plane_config *plane_config)
2418 {
2419 struct drm_device *dev = crtc->base.dev;
2420 struct drm_i915_gem_object *obj = NULL;
2421 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2422 struct drm_framebuffer *fb = &plane_config->fb->base;
2423 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2424 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2425 PAGE_SIZE);
2426
2427 size_aligned -= base_aligned;
2428
2429 if (plane_config->size == 0)
2430 return false;
2431
2432 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2433 base_aligned,
2434 base_aligned,
2435 size_aligned);
2436 if (!obj)
2437 return false;
2438
2439 obj->tiling_mode = plane_config->tiling;
2440 if (obj->tiling_mode == I915_TILING_X)
2441 obj->stride = fb->pitches[0];
2442
2443 mode_cmd.pixel_format = fb->pixel_format;
2444 mode_cmd.width = fb->width;
2445 mode_cmd.height = fb->height;
2446 mode_cmd.pitches[0] = fb->pitches[0];
2447 mode_cmd.modifier[0] = fb->modifier[0];
2448 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2449
2450 mutex_lock(&dev->struct_mutex);
2451
2452 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2453 &mode_cmd, obj)) {
2454 DRM_DEBUG_KMS("intel fb init failed\n");
2455 goto out_unref_obj;
2456 }
2457
2458 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2459 mutex_unlock(&dev->struct_mutex);
2460
2461 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2462 return true;
2463
2464 out_unref_obj:
2465 drm_gem_object_unreference(&obj->base);
2466 mutex_unlock(&dev->struct_mutex);
2467 return false;
2468 }
2469
2470 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2471 static void
2472 update_state_fb(struct drm_plane *plane)
2473 {
2474 if (plane->fb == plane->state->fb)
2475 return;
2476
2477 if (plane->state->fb)
2478 drm_framebuffer_unreference(plane->state->fb);
2479 plane->state->fb = plane->fb;
2480 if (plane->state->fb)
2481 drm_framebuffer_reference(plane->state->fb);
2482 }
2483
2484 static void
2485 intel_find_plane_obj(struct intel_crtc *intel_crtc,
2486 struct intel_initial_plane_config *plane_config)
2487 {
2488 struct drm_device *dev = intel_crtc->base.dev;
2489 struct drm_i915_private *dev_priv = dev->dev_private;
2490 struct drm_crtc *c;
2491 struct intel_crtc *i;
2492 struct drm_i915_gem_object *obj;
2493
2494 if (!plane_config->fb)
2495 return;
2496
2497 if (intel_alloc_plane_obj(intel_crtc, plane_config)) {
2498 struct drm_plane *primary = intel_crtc->base.primary;
2499
2500 primary->fb = &plane_config->fb->base;
2501 primary->state->crtc = &intel_crtc->base;
2502 update_state_fb(primary);
2503
2504 return;
2505 }
2506
2507 kfree(plane_config->fb);
2508
2509 /*
2510 * Failed to alloc the obj, check to see if we should share
2511 * an fb with another CRTC instead
2512 */
2513 for_each_crtc(dev, c) {
2514 i = to_intel_crtc(c);
2515
2516 if (c == &intel_crtc->base)
2517 continue;
2518
2519 if (!i->active)
2520 continue;
2521
2522 obj = intel_fb_obj(c->primary->fb);
2523 if (obj == NULL)
2524 continue;
2525
2526 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2527 struct drm_plane *primary = intel_crtc->base.primary;
2528
2529 if (obj->tiling_mode != I915_TILING_NONE)
2530 dev_priv->preserve_bios_swizzle = true;
2531
2532 drm_framebuffer_reference(c->primary->fb);
2533 primary->fb = c->primary->fb;
2534 primary->state->crtc = &intel_crtc->base;
2535 update_state_fb(intel_crtc->base.primary);
2536 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2537 break;
2538 }
2539 }
2540
2541 }
2542
2543 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2544 struct drm_framebuffer *fb,
2545 int x, int y)
2546 {
2547 struct drm_device *dev = crtc->dev;
2548 struct drm_i915_private *dev_priv = dev->dev_private;
2549 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2550 struct drm_i915_gem_object *obj;
2551 int plane = intel_crtc->plane;
2552 unsigned long linear_offset;
2553 u32 dspcntr;
2554 u32 reg = DSPCNTR(plane);
2555 int pixel_size;
2556
2557 if (!intel_crtc->primary_enabled) {
2558 I915_WRITE(reg, 0);
2559 if (INTEL_INFO(dev)->gen >= 4)
2560 I915_WRITE(DSPSURF(plane), 0);
2561 else
2562 I915_WRITE(DSPADDR(plane), 0);
2563 POSTING_READ(reg);
2564 return;
2565 }
2566
2567 obj = intel_fb_obj(fb);
2568 if (WARN_ON(obj == NULL))
2569 return;
2570
2571 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2572
2573 dspcntr = DISPPLANE_GAMMA_ENABLE;
2574
2575 dspcntr |= DISPLAY_PLANE_ENABLE;
2576
2577 if (INTEL_INFO(dev)->gen < 4) {
2578 if (intel_crtc->pipe == PIPE_B)
2579 dspcntr |= DISPPLANE_SEL_PIPE_B;
2580
2581 /* pipesrc and dspsize control the size that is scaled from,
2582 * which should always be the user's requested size.
2583 */
2584 I915_WRITE(DSPSIZE(plane),
2585 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2586 (intel_crtc->config->pipe_src_w - 1));
2587 I915_WRITE(DSPPOS(plane), 0);
2588 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2589 I915_WRITE(PRIMSIZE(plane),
2590 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2591 (intel_crtc->config->pipe_src_w - 1));
2592 I915_WRITE(PRIMPOS(plane), 0);
2593 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2594 }
2595
2596 switch (fb->pixel_format) {
2597 case DRM_FORMAT_C8:
2598 dspcntr |= DISPPLANE_8BPP;
2599 break;
2600 case DRM_FORMAT_XRGB1555:
2601 case DRM_FORMAT_ARGB1555:
2602 dspcntr |= DISPPLANE_BGRX555;
2603 break;
2604 case DRM_FORMAT_RGB565:
2605 dspcntr |= DISPPLANE_BGRX565;
2606 break;
2607 case DRM_FORMAT_XRGB8888:
2608 case DRM_FORMAT_ARGB8888:
2609 dspcntr |= DISPPLANE_BGRX888;
2610 break;
2611 case DRM_FORMAT_XBGR8888:
2612 case DRM_FORMAT_ABGR8888:
2613 dspcntr |= DISPPLANE_RGBX888;
2614 break;
2615 case DRM_FORMAT_XRGB2101010:
2616 case DRM_FORMAT_ARGB2101010:
2617 dspcntr |= DISPPLANE_BGRX101010;
2618 break;
2619 case DRM_FORMAT_XBGR2101010:
2620 case DRM_FORMAT_ABGR2101010:
2621 dspcntr |= DISPPLANE_RGBX101010;
2622 break;
2623 default:
2624 BUG();
2625 }
2626
2627 if (INTEL_INFO(dev)->gen >= 4 &&
2628 obj->tiling_mode != I915_TILING_NONE)
2629 dspcntr |= DISPPLANE_TILED;
2630
2631 if (IS_G4X(dev))
2632 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2633
2634 linear_offset = y * fb->pitches[0] + x * pixel_size;
2635
2636 if (INTEL_INFO(dev)->gen >= 4) {
2637 intel_crtc->dspaddr_offset =
2638 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2639 pixel_size,
2640 fb->pitches[0]);
2641 linear_offset -= intel_crtc->dspaddr_offset;
2642 } else {
2643 intel_crtc->dspaddr_offset = linear_offset;
2644 }
2645
2646 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2647 dspcntr |= DISPPLANE_ROTATE_180;
2648
2649 x += (intel_crtc->config->pipe_src_w - 1);
2650 y += (intel_crtc->config->pipe_src_h - 1);
2651
2652 /* Finding the last pixel of the last line of the display
2653 data and adding to linear_offset*/
2654 linear_offset +=
2655 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2656 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2657 }
2658
2659 I915_WRITE(reg, dspcntr);
2660
2661 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2662 if (INTEL_INFO(dev)->gen >= 4) {
2663 I915_WRITE(DSPSURF(plane),
2664 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2665 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2666 I915_WRITE(DSPLINOFF(plane), linear_offset);
2667 } else
2668 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2669 POSTING_READ(reg);
2670 }
2671
2672 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2673 struct drm_framebuffer *fb,
2674 int x, int y)
2675 {
2676 struct drm_device *dev = crtc->dev;
2677 struct drm_i915_private *dev_priv = dev->dev_private;
2678 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2679 struct drm_i915_gem_object *obj;
2680 int plane = intel_crtc->plane;
2681 unsigned long linear_offset;
2682 u32 dspcntr;
2683 u32 reg = DSPCNTR(plane);
2684 int pixel_size;
2685
2686 if (!intel_crtc->primary_enabled) {
2687 I915_WRITE(reg, 0);
2688 I915_WRITE(DSPSURF(plane), 0);
2689 POSTING_READ(reg);
2690 return;
2691 }
2692
2693 obj = intel_fb_obj(fb);
2694 if (WARN_ON(obj == NULL))
2695 return;
2696
2697 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2698
2699 dspcntr = DISPPLANE_GAMMA_ENABLE;
2700
2701 dspcntr |= DISPLAY_PLANE_ENABLE;
2702
2703 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2704 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2705
2706 switch (fb->pixel_format) {
2707 case DRM_FORMAT_C8:
2708 dspcntr |= DISPPLANE_8BPP;
2709 break;
2710 case DRM_FORMAT_RGB565:
2711 dspcntr |= DISPPLANE_BGRX565;
2712 break;
2713 case DRM_FORMAT_XRGB8888:
2714 case DRM_FORMAT_ARGB8888:
2715 dspcntr |= DISPPLANE_BGRX888;
2716 break;
2717 case DRM_FORMAT_XBGR8888:
2718 case DRM_FORMAT_ABGR8888:
2719 dspcntr |= DISPPLANE_RGBX888;
2720 break;
2721 case DRM_FORMAT_XRGB2101010:
2722 case DRM_FORMAT_ARGB2101010:
2723 dspcntr |= DISPPLANE_BGRX101010;
2724 break;
2725 case DRM_FORMAT_XBGR2101010:
2726 case DRM_FORMAT_ABGR2101010:
2727 dspcntr |= DISPPLANE_RGBX101010;
2728 break;
2729 default:
2730 BUG();
2731 }
2732
2733 if (obj->tiling_mode != I915_TILING_NONE)
2734 dspcntr |= DISPPLANE_TILED;
2735
2736 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2737 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2738
2739 linear_offset = y * fb->pitches[0] + x * pixel_size;
2740 intel_crtc->dspaddr_offset =
2741 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2742 pixel_size,
2743 fb->pitches[0]);
2744 linear_offset -= intel_crtc->dspaddr_offset;
2745 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2746 dspcntr |= DISPPLANE_ROTATE_180;
2747
2748 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2749 x += (intel_crtc->config->pipe_src_w - 1);
2750 y += (intel_crtc->config->pipe_src_h - 1);
2751
2752 /* Finding the last pixel of the last line of the display
2753 data and adding to linear_offset*/
2754 linear_offset +=
2755 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2756 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2757 }
2758 }
2759
2760 I915_WRITE(reg, dspcntr);
2761
2762 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2763 I915_WRITE(DSPSURF(plane),
2764 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2765 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2766 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2767 } else {
2768 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2769 I915_WRITE(DSPLINOFF(plane), linear_offset);
2770 }
2771 POSTING_READ(reg);
2772 }
2773
2774 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2775 uint32_t pixel_format)
2776 {
2777 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2778
2779 /*
2780 * The stride is either expressed as a multiple of 64 bytes
2781 * chunks for linear buffers or in number of tiles for tiled
2782 * buffers.
2783 */
2784 switch (fb_modifier) {
2785 case DRM_FORMAT_MOD_NONE:
2786 return 64;
2787 case I915_FORMAT_MOD_X_TILED:
2788 if (INTEL_INFO(dev)->gen == 2)
2789 return 128;
2790 return 512;
2791 case I915_FORMAT_MOD_Y_TILED:
2792 /* No need to check for old gens and Y tiling since this is
2793 * about the display engine and those will be blocked before
2794 * we get here.
2795 */
2796 return 128;
2797 case I915_FORMAT_MOD_Yf_TILED:
2798 if (bits_per_pixel == 8)
2799 return 64;
2800 else
2801 return 128;
2802 default:
2803 MISSING_CASE(fb_modifier);
2804 return 64;
2805 }
2806 }
2807
2808 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2809 struct drm_framebuffer *fb,
2810 int x, int y)
2811 {
2812 struct drm_device *dev = crtc->dev;
2813 struct drm_i915_private *dev_priv = dev->dev_private;
2814 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2815 struct drm_i915_gem_object *obj;
2816 int pipe = intel_crtc->pipe;
2817 u32 plane_ctl, stride_div;
2818
2819 if (!intel_crtc->primary_enabled) {
2820 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2821 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2822 POSTING_READ(PLANE_CTL(pipe, 0));
2823 return;
2824 }
2825
2826 plane_ctl = PLANE_CTL_ENABLE |
2827 PLANE_CTL_PIPE_GAMMA_ENABLE |
2828 PLANE_CTL_PIPE_CSC_ENABLE;
2829
2830 switch (fb->pixel_format) {
2831 case DRM_FORMAT_RGB565:
2832 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2833 break;
2834 case DRM_FORMAT_XRGB8888:
2835 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2836 break;
2837 case DRM_FORMAT_ARGB8888:
2838 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2839 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2840 break;
2841 case DRM_FORMAT_XBGR8888:
2842 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2843 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2844 break;
2845 case DRM_FORMAT_ABGR8888:
2846 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2847 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2848 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2849 break;
2850 case DRM_FORMAT_XRGB2101010:
2851 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2852 break;
2853 case DRM_FORMAT_XBGR2101010:
2854 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2855 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2856 break;
2857 default:
2858 BUG();
2859 }
2860
2861 switch (fb->modifier[0]) {
2862 case DRM_FORMAT_MOD_NONE:
2863 break;
2864 case I915_FORMAT_MOD_X_TILED:
2865 plane_ctl |= PLANE_CTL_TILED_X;
2866 break;
2867 case I915_FORMAT_MOD_Y_TILED:
2868 plane_ctl |= PLANE_CTL_TILED_Y;
2869 break;
2870 case I915_FORMAT_MOD_Yf_TILED:
2871 plane_ctl |= PLANE_CTL_TILED_YF;
2872 break;
2873 default:
2874 MISSING_CASE(fb->modifier[0]);
2875 }
2876
2877 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2878 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180))
2879 plane_ctl |= PLANE_CTL_ROTATE_180;
2880
2881 obj = intel_fb_obj(fb);
2882 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
2883 fb->pixel_format);
2884
2885 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2886
2887 I915_WRITE(PLANE_POS(pipe, 0), 0);
2888 I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2889 I915_WRITE(PLANE_SIZE(pipe, 0),
2890 (intel_crtc->config->pipe_src_h - 1) << 16 |
2891 (intel_crtc->config->pipe_src_w - 1));
2892 I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div);
2893 I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2894
2895 POSTING_READ(PLANE_SURF(pipe, 0));
2896 }
2897
2898 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2899 static int
2900 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2901 int x, int y, enum mode_set_atomic state)
2902 {
2903 struct drm_device *dev = crtc->dev;
2904 struct drm_i915_private *dev_priv = dev->dev_private;
2905
2906 if (dev_priv->display.disable_fbc)
2907 dev_priv->display.disable_fbc(dev);
2908
2909 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2910
2911 return 0;
2912 }
2913
2914 static void intel_complete_page_flips(struct drm_device *dev)
2915 {
2916 struct drm_crtc *crtc;
2917
2918 for_each_crtc(dev, crtc) {
2919 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2920 enum plane plane = intel_crtc->plane;
2921
2922 intel_prepare_page_flip(dev, plane);
2923 intel_finish_page_flip_plane(dev, plane);
2924 }
2925 }
2926
2927 static void intel_update_primary_planes(struct drm_device *dev)
2928 {
2929 struct drm_i915_private *dev_priv = dev->dev_private;
2930 struct drm_crtc *crtc;
2931
2932 for_each_crtc(dev, crtc) {
2933 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2934
2935 drm_modeset_lock(&crtc->mutex, NULL);
2936 /*
2937 * FIXME: Once we have proper support for primary planes (and
2938 * disabling them without disabling the entire crtc) allow again
2939 * a NULL crtc->primary->fb.
2940 */
2941 if (intel_crtc->active && crtc->primary->fb)
2942 dev_priv->display.update_primary_plane(crtc,
2943 crtc->primary->fb,
2944 crtc->x,
2945 crtc->y);
2946 drm_modeset_unlock(&crtc->mutex);
2947 }
2948 }
2949
2950 void intel_prepare_reset(struct drm_device *dev)
2951 {
2952 struct drm_i915_private *dev_priv = to_i915(dev);
2953 struct intel_crtc *crtc;
2954
2955 /* no reset support for gen2 */
2956 if (IS_GEN2(dev))
2957 return;
2958
2959 /* reset doesn't touch the display */
2960 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
2961 return;
2962
2963 drm_modeset_lock_all(dev);
2964
2965 /*
2966 * Disabling the crtcs gracefully seems nicer. Also the
2967 * g33 docs say we should at least disable all the planes.
2968 */
2969 for_each_intel_crtc(dev, crtc) {
2970 if (crtc->active)
2971 dev_priv->display.crtc_disable(&crtc->base);
2972 }
2973 }
2974
2975 void intel_finish_reset(struct drm_device *dev)
2976 {
2977 struct drm_i915_private *dev_priv = to_i915(dev);
2978
2979 /*
2980 * Flips in the rings will be nuked by the reset,
2981 * so complete all pending flips so that user space
2982 * will get its events and not get stuck.
2983 */
2984 intel_complete_page_flips(dev);
2985
2986 /* no reset support for gen2 */
2987 if (IS_GEN2(dev))
2988 return;
2989
2990 /* reset doesn't touch the display */
2991 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
2992 /*
2993 * Flips in the rings have been nuked by the reset,
2994 * so update the base address of all primary
2995 * planes to the the last fb to make sure we're
2996 * showing the correct fb after a reset.
2997 */
2998 intel_update_primary_planes(dev);
2999 return;
3000 }
3001
3002 /*
3003 * The display has been reset as well,
3004 * so need a full re-initialization.
3005 */
3006 intel_runtime_pm_disable_interrupts(dev_priv);
3007 intel_runtime_pm_enable_interrupts(dev_priv);
3008
3009 intel_modeset_init_hw(dev);
3010
3011 spin_lock_irq(&dev_priv->irq_lock);
3012 if (dev_priv->display.hpd_irq_setup)
3013 dev_priv->display.hpd_irq_setup(dev);
3014 spin_unlock_irq(&dev_priv->irq_lock);
3015
3016 intel_modeset_setup_hw_state(dev, true);
3017
3018 intel_hpd_init(dev_priv);
3019
3020 drm_modeset_unlock_all(dev);
3021 }
3022
3023 static int
3024 intel_finish_fb(struct drm_framebuffer *old_fb)
3025 {
3026 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3027 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3028 bool was_interruptible = dev_priv->mm.interruptible;
3029 int ret;
3030
3031 /* Big Hammer, we also need to ensure that any pending
3032 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3033 * current scanout is retired before unpinning the old
3034 * framebuffer.
3035 *
3036 * This should only fail upon a hung GPU, in which case we
3037 * can safely continue.
3038 */
3039 dev_priv->mm.interruptible = false;
3040 ret = i915_gem_object_finish_gpu(obj);
3041 dev_priv->mm.interruptible = was_interruptible;
3042
3043 return ret;
3044 }
3045
3046 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3047 {
3048 struct drm_device *dev = crtc->dev;
3049 struct drm_i915_private *dev_priv = dev->dev_private;
3050 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3051 bool pending;
3052
3053 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3054 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3055 return false;
3056
3057 spin_lock_irq(&dev->event_lock);
3058 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3059 spin_unlock_irq(&dev->event_lock);
3060
3061 return pending;
3062 }
3063
3064 static void intel_update_pipe_size(struct intel_crtc *crtc)
3065 {
3066 struct drm_device *dev = crtc->base.dev;
3067 struct drm_i915_private *dev_priv = dev->dev_private;
3068 const struct drm_display_mode *adjusted_mode;
3069
3070 if (!i915.fastboot)
3071 return;
3072
3073 /*
3074 * Update pipe size and adjust fitter if needed: the reason for this is
3075 * that in compute_mode_changes we check the native mode (not the pfit
3076 * mode) to see if we can flip rather than do a full mode set. In the
3077 * fastboot case, we'll flip, but if we don't update the pipesrc and
3078 * pfit state, we'll end up with a big fb scanned out into the wrong
3079 * sized surface.
3080 *
3081 * To fix this properly, we need to hoist the checks up into
3082 * compute_mode_changes (or above), check the actual pfit state and
3083 * whether the platform allows pfit disable with pipe active, and only
3084 * then update the pipesrc and pfit state, even on the flip path.
3085 */
3086
3087 adjusted_mode = &crtc->config->base.adjusted_mode;
3088
3089 I915_WRITE(PIPESRC(crtc->pipe),
3090 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3091 (adjusted_mode->crtc_vdisplay - 1));
3092 if (!crtc->config->pch_pfit.enabled &&
3093 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3094 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3095 I915_WRITE(PF_CTL(crtc->pipe), 0);
3096 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3097 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3098 }
3099 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3100 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3101 }
3102
3103 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3104 {
3105 struct drm_device *dev = crtc->dev;
3106 struct drm_i915_private *dev_priv = dev->dev_private;
3107 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3108 int pipe = intel_crtc->pipe;
3109 u32 reg, temp;
3110
3111 /* enable normal train */
3112 reg = FDI_TX_CTL(pipe);
3113 temp = I915_READ(reg);
3114 if (IS_IVYBRIDGE(dev)) {
3115 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3116 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3117 } else {
3118 temp &= ~FDI_LINK_TRAIN_NONE;
3119 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3120 }
3121 I915_WRITE(reg, temp);
3122
3123 reg = FDI_RX_CTL(pipe);
3124 temp = I915_READ(reg);
3125 if (HAS_PCH_CPT(dev)) {
3126 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3127 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3128 } else {
3129 temp &= ~FDI_LINK_TRAIN_NONE;
3130 temp |= FDI_LINK_TRAIN_NONE;
3131 }
3132 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3133
3134 /* wait one idle pattern time */
3135 POSTING_READ(reg);
3136 udelay(1000);
3137
3138 /* IVB wants error correction enabled */
3139 if (IS_IVYBRIDGE(dev))
3140 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3141 FDI_FE_ERRC_ENABLE);
3142 }
3143
3144 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
3145 {
3146 return crtc->base.state->enable && crtc->active &&
3147 crtc->config->has_pch_encoder;
3148 }
3149
3150 static void ivb_modeset_global_resources(struct drm_device *dev)
3151 {
3152 struct drm_i915_private *dev_priv = dev->dev_private;
3153 struct intel_crtc *pipe_B_crtc =
3154 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3155 struct intel_crtc *pipe_C_crtc =
3156 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
3157 uint32_t temp;
3158
3159 /*
3160 * When everything is off disable fdi C so that we could enable fdi B
3161 * with all lanes. Note that we don't care about enabled pipes without
3162 * an enabled pch encoder.
3163 */
3164 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
3165 !pipe_has_enabled_pch(pipe_C_crtc)) {
3166 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3167 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3168
3169 temp = I915_READ(SOUTH_CHICKEN1);
3170 temp &= ~FDI_BC_BIFURCATION_SELECT;
3171 DRM_DEBUG_KMS("disabling fdi C rx\n");
3172 I915_WRITE(SOUTH_CHICKEN1, temp);
3173 }
3174 }
3175
3176 /* The FDI link training functions for ILK/Ibexpeak. */
3177 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3178 {
3179 struct drm_device *dev = crtc->dev;
3180 struct drm_i915_private *dev_priv = dev->dev_private;
3181 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3182 int pipe = intel_crtc->pipe;
3183 u32 reg, temp, tries;
3184
3185 /* FDI needs bits from pipe first */
3186 assert_pipe_enabled(dev_priv, pipe);
3187
3188 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3189 for train result */
3190 reg = FDI_RX_IMR(pipe);
3191 temp = I915_READ(reg);
3192 temp &= ~FDI_RX_SYMBOL_LOCK;
3193 temp &= ~FDI_RX_BIT_LOCK;
3194 I915_WRITE(reg, temp);
3195 I915_READ(reg);
3196 udelay(150);
3197
3198 /* enable CPU FDI TX and PCH FDI RX */
3199 reg = FDI_TX_CTL(pipe);
3200 temp = I915_READ(reg);
3201 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3202 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3203 temp &= ~FDI_LINK_TRAIN_NONE;
3204 temp |= FDI_LINK_TRAIN_PATTERN_1;
3205 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3206
3207 reg = FDI_RX_CTL(pipe);
3208 temp = I915_READ(reg);
3209 temp &= ~FDI_LINK_TRAIN_NONE;
3210 temp |= FDI_LINK_TRAIN_PATTERN_1;
3211 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3212
3213 POSTING_READ(reg);
3214 udelay(150);
3215
3216 /* Ironlake workaround, enable clock pointer after FDI enable*/
3217 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3218 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3219 FDI_RX_PHASE_SYNC_POINTER_EN);
3220
3221 reg = FDI_RX_IIR(pipe);
3222 for (tries = 0; tries < 5; tries++) {
3223 temp = I915_READ(reg);
3224 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3225
3226 if ((temp & FDI_RX_BIT_LOCK)) {
3227 DRM_DEBUG_KMS("FDI train 1 done.\n");
3228 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3229 break;
3230 }
3231 }
3232 if (tries == 5)
3233 DRM_ERROR("FDI train 1 fail!\n");
3234
3235 /* Train 2 */
3236 reg = FDI_TX_CTL(pipe);
3237 temp = I915_READ(reg);
3238 temp &= ~FDI_LINK_TRAIN_NONE;
3239 temp |= FDI_LINK_TRAIN_PATTERN_2;
3240 I915_WRITE(reg, temp);
3241
3242 reg = FDI_RX_CTL(pipe);
3243 temp = I915_READ(reg);
3244 temp &= ~FDI_LINK_TRAIN_NONE;
3245 temp |= FDI_LINK_TRAIN_PATTERN_2;
3246 I915_WRITE(reg, temp);
3247
3248 POSTING_READ(reg);
3249 udelay(150);
3250
3251 reg = FDI_RX_IIR(pipe);
3252 for (tries = 0; tries < 5; tries++) {
3253 temp = I915_READ(reg);
3254 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3255
3256 if (temp & FDI_RX_SYMBOL_LOCK) {
3257 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3258 DRM_DEBUG_KMS("FDI train 2 done.\n");
3259 break;
3260 }
3261 }
3262 if (tries == 5)
3263 DRM_ERROR("FDI train 2 fail!\n");
3264
3265 DRM_DEBUG_KMS("FDI train done\n");
3266
3267 }
3268
3269 static const int snb_b_fdi_train_param[] = {
3270 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3271 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3272 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3273 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3274 };
3275
3276 /* The FDI link training functions for SNB/Cougarpoint. */
3277 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3278 {
3279 struct drm_device *dev = crtc->dev;
3280 struct drm_i915_private *dev_priv = dev->dev_private;
3281 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3282 int pipe = intel_crtc->pipe;
3283 u32 reg, temp, i, retry;
3284
3285 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3286 for train result */
3287 reg = FDI_RX_IMR(pipe);
3288 temp = I915_READ(reg);
3289 temp &= ~FDI_RX_SYMBOL_LOCK;
3290 temp &= ~FDI_RX_BIT_LOCK;
3291 I915_WRITE(reg, temp);
3292
3293 POSTING_READ(reg);
3294 udelay(150);
3295
3296 /* enable CPU FDI TX and PCH FDI RX */
3297 reg = FDI_TX_CTL(pipe);
3298 temp = I915_READ(reg);
3299 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3300 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3301 temp &= ~FDI_LINK_TRAIN_NONE;
3302 temp |= FDI_LINK_TRAIN_PATTERN_1;
3303 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3304 /* SNB-B */
3305 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3306 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3307
3308 I915_WRITE(FDI_RX_MISC(pipe),
3309 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3310
3311 reg = FDI_RX_CTL(pipe);
3312 temp = I915_READ(reg);
3313 if (HAS_PCH_CPT(dev)) {
3314 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3315 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3316 } else {
3317 temp &= ~FDI_LINK_TRAIN_NONE;
3318 temp |= FDI_LINK_TRAIN_PATTERN_1;
3319 }
3320 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3321
3322 POSTING_READ(reg);
3323 udelay(150);
3324
3325 for (i = 0; i < 4; i++) {
3326 reg = FDI_TX_CTL(pipe);
3327 temp = I915_READ(reg);
3328 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3329 temp |= snb_b_fdi_train_param[i];
3330 I915_WRITE(reg, temp);
3331
3332 POSTING_READ(reg);
3333 udelay(500);
3334
3335 for (retry = 0; retry < 5; retry++) {
3336 reg = FDI_RX_IIR(pipe);
3337 temp = I915_READ(reg);
3338 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3339 if (temp & FDI_RX_BIT_LOCK) {
3340 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3341 DRM_DEBUG_KMS("FDI train 1 done.\n");
3342 break;
3343 }
3344 udelay(50);
3345 }
3346 if (retry < 5)
3347 break;
3348 }
3349 if (i == 4)
3350 DRM_ERROR("FDI train 1 fail!\n");
3351
3352 /* Train 2 */
3353 reg = FDI_TX_CTL(pipe);
3354 temp = I915_READ(reg);
3355 temp &= ~FDI_LINK_TRAIN_NONE;
3356 temp |= FDI_LINK_TRAIN_PATTERN_2;
3357 if (IS_GEN6(dev)) {
3358 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3359 /* SNB-B */
3360 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3361 }
3362 I915_WRITE(reg, temp);
3363
3364 reg = FDI_RX_CTL(pipe);
3365 temp = I915_READ(reg);
3366 if (HAS_PCH_CPT(dev)) {
3367 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3368 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3369 } else {
3370 temp &= ~FDI_LINK_TRAIN_NONE;
3371 temp |= FDI_LINK_TRAIN_PATTERN_2;
3372 }
3373 I915_WRITE(reg, temp);
3374
3375 POSTING_READ(reg);
3376 udelay(150);
3377
3378 for (i = 0; i < 4; i++) {
3379 reg = FDI_TX_CTL(pipe);
3380 temp = I915_READ(reg);
3381 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3382 temp |= snb_b_fdi_train_param[i];
3383 I915_WRITE(reg, temp);
3384
3385 POSTING_READ(reg);
3386 udelay(500);
3387
3388 for (retry = 0; retry < 5; retry++) {
3389 reg = FDI_RX_IIR(pipe);
3390 temp = I915_READ(reg);
3391 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3392 if (temp & FDI_RX_SYMBOL_LOCK) {
3393 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3394 DRM_DEBUG_KMS("FDI train 2 done.\n");
3395 break;
3396 }
3397 udelay(50);
3398 }
3399 if (retry < 5)
3400 break;
3401 }
3402 if (i == 4)
3403 DRM_ERROR("FDI train 2 fail!\n");
3404
3405 DRM_DEBUG_KMS("FDI train done.\n");
3406 }
3407
3408 /* Manual link training for Ivy Bridge A0 parts */
3409 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3410 {
3411 struct drm_device *dev = crtc->dev;
3412 struct drm_i915_private *dev_priv = dev->dev_private;
3413 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3414 int pipe = intel_crtc->pipe;
3415 u32 reg, temp, i, j;
3416
3417 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3418 for train result */
3419 reg = FDI_RX_IMR(pipe);
3420 temp = I915_READ(reg);
3421 temp &= ~FDI_RX_SYMBOL_LOCK;
3422 temp &= ~FDI_RX_BIT_LOCK;
3423 I915_WRITE(reg, temp);
3424
3425 POSTING_READ(reg);
3426 udelay(150);
3427
3428 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3429 I915_READ(FDI_RX_IIR(pipe)));
3430
3431 /* Try each vswing and preemphasis setting twice before moving on */
3432 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3433 /* disable first in case we need to retry */
3434 reg = FDI_TX_CTL(pipe);
3435 temp = I915_READ(reg);
3436 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3437 temp &= ~FDI_TX_ENABLE;
3438 I915_WRITE(reg, temp);
3439
3440 reg = FDI_RX_CTL(pipe);
3441 temp = I915_READ(reg);
3442 temp &= ~FDI_LINK_TRAIN_AUTO;
3443 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3444 temp &= ~FDI_RX_ENABLE;
3445 I915_WRITE(reg, temp);
3446
3447 /* enable CPU FDI TX and PCH FDI RX */
3448 reg = FDI_TX_CTL(pipe);
3449 temp = I915_READ(reg);
3450 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3451 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3452 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3453 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3454 temp |= snb_b_fdi_train_param[j/2];
3455 temp |= FDI_COMPOSITE_SYNC;
3456 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3457
3458 I915_WRITE(FDI_RX_MISC(pipe),
3459 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3460
3461 reg = FDI_RX_CTL(pipe);
3462 temp = I915_READ(reg);
3463 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3464 temp |= FDI_COMPOSITE_SYNC;
3465 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3466
3467 POSTING_READ(reg);
3468 udelay(1); /* should be 0.5us */
3469
3470 for (i = 0; i < 4; i++) {
3471 reg = FDI_RX_IIR(pipe);
3472 temp = I915_READ(reg);
3473 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3474
3475 if (temp & FDI_RX_BIT_LOCK ||
3476 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3477 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3478 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3479 i);
3480 break;
3481 }
3482 udelay(1); /* should be 0.5us */
3483 }
3484 if (i == 4) {
3485 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3486 continue;
3487 }
3488
3489 /* Train 2 */
3490 reg = FDI_TX_CTL(pipe);
3491 temp = I915_READ(reg);
3492 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3493 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3494 I915_WRITE(reg, temp);
3495
3496 reg = FDI_RX_CTL(pipe);
3497 temp = I915_READ(reg);
3498 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3499 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3500 I915_WRITE(reg, temp);
3501
3502 POSTING_READ(reg);
3503 udelay(2); /* should be 1.5us */
3504
3505 for (i = 0; i < 4; i++) {
3506 reg = FDI_RX_IIR(pipe);
3507 temp = I915_READ(reg);
3508 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3509
3510 if (temp & FDI_RX_SYMBOL_LOCK ||
3511 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3512 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3513 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3514 i);
3515 goto train_done;
3516 }
3517 udelay(2); /* should be 1.5us */
3518 }
3519 if (i == 4)
3520 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3521 }
3522
3523 train_done:
3524 DRM_DEBUG_KMS("FDI train done.\n");
3525 }
3526
3527 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3528 {
3529 struct drm_device *dev = intel_crtc->base.dev;
3530 struct drm_i915_private *dev_priv = dev->dev_private;
3531 int pipe = intel_crtc->pipe;
3532 u32 reg, temp;
3533
3534
3535 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3536 reg = FDI_RX_CTL(pipe);
3537 temp = I915_READ(reg);
3538 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3539 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3540 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3541 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3542
3543 POSTING_READ(reg);
3544 udelay(200);
3545
3546 /* Switch from Rawclk to PCDclk */
3547 temp = I915_READ(reg);
3548 I915_WRITE(reg, temp | FDI_PCDCLK);
3549
3550 POSTING_READ(reg);
3551 udelay(200);
3552
3553 /* Enable CPU FDI TX PLL, always on for Ironlake */
3554 reg = FDI_TX_CTL(pipe);
3555 temp = I915_READ(reg);
3556 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3557 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3558
3559 POSTING_READ(reg);
3560 udelay(100);
3561 }
3562 }
3563
3564 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3565 {
3566 struct drm_device *dev = intel_crtc->base.dev;
3567 struct drm_i915_private *dev_priv = dev->dev_private;
3568 int pipe = intel_crtc->pipe;
3569 u32 reg, temp;
3570
3571 /* Switch from PCDclk to Rawclk */
3572 reg = FDI_RX_CTL(pipe);
3573 temp = I915_READ(reg);
3574 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3575
3576 /* Disable CPU FDI TX PLL */
3577 reg = FDI_TX_CTL(pipe);
3578 temp = I915_READ(reg);
3579 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3580
3581 POSTING_READ(reg);
3582 udelay(100);
3583
3584 reg = FDI_RX_CTL(pipe);
3585 temp = I915_READ(reg);
3586 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3587
3588 /* Wait for the clocks to turn off. */
3589 POSTING_READ(reg);
3590 udelay(100);
3591 }
3592
3593 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3594 {
3595 struct drm_device *dev = crtc->dev;
3596 struct drm_i915_private *dev_priv = dev->dev_private;
3597 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3598 int pipe = intel_crtc->pipe;
3599 u32 reg, temp;
3600
3601 /* disable CPU FDI tx and PCH FDI rx */
3602 reg = FDI_TX_CTL(pipe);
3603 temp = I915_READ(reg);
3604 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3605 POSTING_READ(reg);
3606
3607 reg = FDI_RX_CTL(pipe);
3608 temp = I915_READ(reg);
3609 temp &= ~(0x7 << 16);
3610 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3611 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3612
3613 POSTING_READ(reg);
3614 udelay(100);
3615
3616 /* Ironlake workaround, disable clock pointer after downing FDI */
3617 if (HAS_PCH_IBX(dev))
3618 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3619
3620 /* still set train pattern 1 */
3621 reg = FDI_TX_CTL(pipe);
3622 temp = I915_READ(reg);
3623 temp &= ~FDI_LINK_TRAIN_NONE;
3624 temp |= FDI_LINK_TRAIN_PATTERN_1;
3625 I915_WRITE(reg, temp);
3626
3627 reg = FDI_RX_CTL(pipe);
3628 temp = I915_READ(reg);
3629 if (HAS_PCH_CPT(dev)) {
3630 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3631 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3632 } else {
3633 temp &= ~FDI_LINK_TRAIN_NONE;
3634 temp |= FDI_LINK_TRAIN_PATTERN_1;
3635 }
3636 /* BPC in FDI rx is consistent with that in PIPECONF */
3637 temp &= ~(0x07 << 16);
3638 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3639 I915_WRITE(reg, temp);
3640
3641 POSTING_READ(reg);
3642 udelay(100);
3643 }
3644
3645 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3646 {
3647 struct intel_crtc *crtc;
3648
3649 /* Note that we don't need to be called with mode_config.lock here
3650 * as our list of CRTC objects is static for the lifetime of the
3651 * device and so cannot disappear as we iterate. Similarly, we can
3652 * happily treat the predicates as racy, atomic checks as userspace
3653 * cannot claim and pin a new fb without at least acquring the
3654 * struct_mutex and so serialising with us.
3655 */
3656 for_each_intel_crtc(dev, crtc) {
3657 if (atomic_read(&crtc->unpin_work_count) == 0)
3658 continue;
3659
3660 if (crtc->unpin_work)
3661 intel_wait_for_vblank(dev, crtc->pipe);
3662
3663 return true;
3664 }
3665
3666 return false;
3667 }
3668
3669 static void page_flip_completed(struct intel_crtc *intel_crtc)
3670 {
3671 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3672 struct intel_unpin_work *work = intel_crtc->unpin_work;
3673
3674 /* ensure that the unpin work is consistent wrt ->pending. */
3675 smp_rmb();
3676 intel_crtc->unpin_work = NULL;
3677
3678 if (work->event)
3679 drm_send_vblank_event(intel_crtc->base.dev,
3680 intel_crtc->pipe,
3681 work->event);
3682
3683 drm_crtc_vblank_put(&intel_crtc->base);
3684
3685 wake_up_all(&dev_priv->pending_flip_queue);
3686 queue_work(dev_priv->wq, &work->work);
3687
3688 trace_i915_flip_complete(intel_crtc->plane,
3689 work->pending_flip_obj);
3690 }
3691
3692 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3693 {
3694 struct drm_device *dev = crtc->dev;
3695 struct drm_i915_private *dev_priv = dev->dev_private;
3696
3697 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3698 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3699 !intel_crtc_has_pending_flip(crtc),
3700 60*HZ) == 0)) {
3701 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3702
3703 spin_lock_irq(&dev->event_lock);
3704 if (intel_crtc->unpin_work) {
3705 WARN_ONCE(1, "Removing stuck page flip\n");
3706 page_flip_completed(intel_crtc);
3707 }
3708 spin_unlock_irq(&dev->event_lock);
3709 }
3710
3711 if (crtc->primary->fb) {
3712 mutex_lock(&dev->struct_mutex);
3713 intel_finish_fb(crtc->primary->fb);
3714 mutex_unlock(&dev->struct_mutex);
3715 }
3716 }
3717
3718 /* Program iCLKIP clock to the desired frequency */
3719 static void lpt_program_iclkip(struct drm_crtc *crtc)
3720 {
3721 struct drm_device *dev = crtc->dev;
3722 struct drm_i915_private *dev_priv = dev->dev_private;
3723 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3724 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3725 u32 temp;
3726
3727 mutex_lock(&dev_priv->dpio_lock);
3728
3729 /* It is necessary to ungate the pixclk gate prior to programming
3730 * the divisors, and gate it back when it is done.
3731 */
3732 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3733
3734 /* Disable SSCCTL */
3735 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3736 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3737 SBI_SSCCTL_DISABLE,
3738 SBI_ICLK);
3739
3740 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3741 if (clock == 20000) {
3742 auxdiv = 1;
3743 divsel = 0x41;
3744 phaseinc = 0x20;
3745 } else {
3746 /* The iCLK virtual clock root frequency is in MHz,
3747 * but the adjusted_mode->crtc_clock in in KHz. To get the
3748 * divisors, it is necessary to divide one by another, so we
3749 * convert the virtual clock precision to KHz here for higher
3750 * precision.
3751 */
3752 u32 iclk_virtual_root_freq = 172800 * 1000;
3753 u32 iclk_pi_range = 64;
3754 u32 desired_divisor, msb_divisor_value, pi_value;
3755
3756 desired_divisor = (iclk_virtual_root_freq / clock);
3757 msb_divisor_value = desired_divisor / iclk_pi_range;
3758 pi_value = desired_divisor % iclk_pi_range;
3759
3760 auxdiv = 0;
3761 divsel = msb_divisor_value - 2;
3762 phaseinc = pi_value;
3763 }
3764
3765 /* This should not happen with any sane values */
3766 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3767 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3768 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3769 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3770
3771 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3772 clock,
3773 auxdiv,
3774 divsel,
3775 phasedir,
3776 phaseinc);
3777
3778 /* Program SSCDIVINTPHASE6 */
3779 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3780 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3781 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3782 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3783 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3784 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3785 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3786 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3787
3788 /* Program SSCAUXDIV */
3789 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3790 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3791 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3792 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3793
3794 /* Enable modulator and associated divider */
3795 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3796 temp &= ~SBI_SSCCTL_DISABLE;
3797 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3798
3799 /* Wait for initialization time */
3800 udelay(24);
3801
3802 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3803
3804 mutex_unlock(&dev_priv->dpio_lock);
3805 }
3806
3807 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3808 enum pipe pch_transcoder)
3809 {
3810 struct drm_device *dev = crtc->base.dev;
3811 struct drm_i915_private *dev_priv = dev->dev_private;
3812 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3813
3814 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3815 I915_READ(HTOTAL(cpu_transcoder)));
3816 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3817 I915_READ(HBLANK(cpu_transcoder)));
3818 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3819 I915_READ(HSYNC(cpu_transcoder)));
3820
3821 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3822 I915_READ(VTOTAL(cpu_transcoder)));
3823 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3824 I915_READ(VBLANK(cpu_transcoder)));
3825 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3826 I915_READ(VSYNC(cpu_transcoder)));
3827 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3828 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3829 }
3830
3831 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3832 {
3833 struct drm_i915_private *dev_priv = dev->dev_private;
3834 uint32_t temp;
3835
3836 temp = I915_READ(SOUTH_CHICKEN1);
3837 if (temp & FDI_BC_BIFURCATION_SELECT)
3838 return;
3839
3840 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3841 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3842
3843 temp |= FDI_BC_BIFURCATION_SELECT;
3844 DRM_DEBUG_KMS("enabling fdi C rx\n");
3845 I915_WRITE(SOUTH_CHICKEN1, temp);
3846 POSTING_READ(SOUTH_CHICKEN1);
3847 }
3848
3849 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3850 {
3851 struct drm_device *dev = intel_crtc->base.dev;
3852 struct drm_i915_private *dev_priv = dev->dev_private;
3853
3854 switch (intel_crtc->pipe) {
3855 case PIPE_A:
3856 break;
3857 case PIPE_B:
3858 if (intel_crtc->config->fdi_lanes > 2)
3859 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3860 else
3861 cpt_enable_fdi_bc_bifurcation(dev);
3862
3863 break;
3864 case PIPE_C:
3865 cpt_enable_fdi_bc_bifurcation(dev);
3866
3867 break;
3868 default:
3869 BUG();
3870 }
3871 }
3872
3873 /*
3874 * Enable PCH resources required for PCH ports:
3875 * - PCH PLLs
3876 * - FDI training & RX/TX
3877 * - update transcoder timings
3878 * - DP transcoding bits
3879 * - transcoder
3880 */
3881 static void ironlake_pch_enable(struct drm_crtc *crtc)
3882 {
3883 struct drm_device *dev = crtc->dev;
3884 struct drm_i915_private *dev_priv = dev->dev_private;
3885 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3886 int pipe = intel_crtc->pipe;
3887 u32 reg, temp;
3888
3889 assert_pch_transcoder_disabled(dev_priv, pipe);
3890
3891 if (IS_IVYBRIDGE(dev))
3892 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3893
3894 /* Write the TU size bits before fdi link training, so that error
3895 * detection works. */
3896 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3897 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3898
3899 /* For PCH output, training FDI link */
3900 dev_priv->display.fdi_link_train(crtc);
3901
3902 /* We need to program the right clock selection before writing the pixel
3903 * mutliplier into the DPLL. */
3904 if (HAS_PCH_CPT(dev)) {
3905 u32 sel;
3906
3907 temp = I915_READ(PCH_DPLL_SEL);
3908 temp |= TRANS_DPLL_ENABLE(pipe);
3909 sel = TRANS_DPLLB_SEL(pipe);
3910 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
3911 temp |= sel;
3912 else
3913 temp &= ~sel;
3914 I915_WRITE(PCH_DPLL_SEL, temp);
3915 }
3916
3917 /* XXX: pch pll's can be enabled any time before we enable the PCH
3918 * transcoder, and we actually should do this to not upset any PCH
3919 * transcoder that already use the clock when we share it.
3920 *
3921 * Note that enable_shared_dpll tries to do the right thing, but
3922 * get_shared_dpll unconditionally resets the pll - we need that to have
3923 * the right LVDS enable sequence. */
3924 intel_enable_shared_dpll(intel_crtc);
3925
3926 /* set transcoder timing, panel must allow it */
3927 assert_panel_unlocked(dev_priv, pipe);
3928 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3929
3930 intel_fdi_normal_train(crtc);
3931
3932 /* For PCH DP, enable TRANS_DP_CTL */
3933 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
3934 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3935 reg = TRANS_DP_CTL(pipe);
3936 temp = I915_READ(reg);
3937 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3938 TRANS_DP_SYNC_MASK |
3939 TRANS_DP_BPC_MASK);
3940 temp |= (TRANS_DP_OUTPUT_ENABLE |
3941 TRANS_DP_ENH_FRAMING);
3942 temp |= bpc << 9; /* same format but at 11:9 */
3943
3944 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3945 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3946 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3947 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3948
3949 switch (intel_trans_dp_port_sel(crtc)) {
3950 case PCH_DP_B:
3951 temp |= TRANS_DP_PORT_SEL_B;
3952 break;
3953 case PCH_DP_C:
3954 temp |= TRANS_DP_PORT_SEL_C;
3955 break;
3956 case PCH_DP_D:
3957 temp |= TRANS_DP_PORT_SEL_D;
3958 break;
3959 default:
3960 BUG();
3961 }
3962
3963 I915_WRITE(reg, temp);
3964 }
3965
3966 ironlake_enable_pch_transcoder(dev_priv, pipe);
3967 }
3968
3969 static void lpt_pch_enable(struct drm_crtc *crtc)
3970 {
3971 struct drm_device *dev = crtc->dev;
3972 struct drm_i915_private *dev_priv = dev->dev_private;
3973 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3974 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
3975
3976 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3977
3978 lpt_program_iclkip(crtc);
3979
3980 /* Set transcoder timing. */
3981 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3982
3983 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3984 }
3985
3986 void intel_put_shared_dpll(struct intel_crtc *crtc)
3987 {
3988 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3989
3990 if (pll == NULL)
3991 return;
3992
3993 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
3994 WARN(1, "bad %s crtc mask\n", pll->name);
3995 return;
3996 }
3997
3998 pll->config.crtc_mask &= ~(1 << crtc->pipe);
3999 if (pll->config.crtc_mask == 0) {
4000 WARN_ON(pll->on);
4001 WARN_ON(pll->active);
4002 }
4003
4004 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
4005 }
4006
4007 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4008 struct intel_crtc_state *crtc_state)
4009 {
4010 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4011 struct intel_shared_dpll *pll;
4012 enum intel_dpll_id i;
4013
4014 if (HAS_PCH_IBX(dev_priv->dev)) {
4015 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4016 i = (enum intel_dpll_id) crtc->pipe;
4017 pll = &dev_priv->shared_dplls[i];
4018
4019 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4020 crtc->base.base.id, pll->name);
4021
4022 WARN_ON(pll->new_config->crtc_mask);
4023
4024 goto found;
4025 }
4026
4027 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4028 pll = &dev_priv->shared_dplls[i];
4029
4030 /* Only want to check enabled timings first */
4031 if (pll->new_config->crtc_mask == 0)
4032 continue;
4033
4034 if (memcmp(&crtc_state->dpll_hw_state,
4035 &pll->new_config->hw_state,
4036 sizeof(pll->new_config->hw_state)) == 0) {
4037 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4038 crtc->base.base.id, pll->name,
4039 pll->new_config->crtc_mask,
4040 pll->active);
4041 goto found;
4042 }
4043 }
4044
4045 /* Ok no matching timings, maybe there's a free one? */
4046 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4047 pll = &dev_priv->shared_dplls[i];
4048 if (pll->new_config->crtc_mask == 0) {
4049 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4050 crtc->base.base.id, pll->name);
4051 goto found;
4052 }
4053 }
4054
4055 return NULL;
4056
4057 found:
4058 if (pll->new_config->crtc_mask == 0)
4059 pll->new_config->hw_state = crtc_state->dpll_hw_state;
4060
4061 crtc_state->shared_dpll = i;
4062 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4063 pipe_name(crtc->pipe));
4064
4065 pll->new_config->crtc_mask |= 1 << crtc->pipe;
4066
4067 return pll;
4068 }
4069
4070 /**
4071 * intel_shared_dpll_start_config - start a new PLL staged config
4072 * @dev_priv: DRM device
4073 * @clear_pipes: mask of pipes that will have their PLLs freed
4074 *
4075 * Starts a new PLL staged config, copying the current config but
4076 * releasing the references of pipes specified in clear_pipes.
4077 */
4078 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4079 unsigned clear_pipes)
4080 {
4081 struct intel_shared_dpll *pll;
4082 enum intel_dpll_id i;
4083
4084 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4085 pll = &dev_priv->shared_dplls[i];
4086
4087 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4088 GFP_KERNEL);
4089 if (!pll->new_config)
4090 goto cleanup;
4091
4092 pll->new_config->crtc_mask &= ~clear_pipes;
4093 }
4094
4095 return 0;
4096
4097 cleanup:
4098 while (--i >= 0) {
4099 pll = &dev_priv->shared_dplls[i];
4100 kfree(pll->new_config);
4101 pll->new_config = NULL;
4102 }
4103
4104 return -ENOMEM;
4105 }
4106
4107 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4108 {
4109 struct intel_shared_dpll *pll;
4110 enum intel_dpll_id i;
4111
4112 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4113 pll = &dev_priv->shared_dplls[i];
4114
4115 WARN_ON(pll->new_config == &pll->config);
4116
4117 pll->config = *pll->new_config;
4118 kfree(pll->new_config);
4119 pll->new_config = NULL;
4120 }
4121 }
4122
4123 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4124 {
4125 struct intel_shared_dpll *pll;
4126 enum intel_dpll_id i;
4127
4128 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4129 pll = &dev_priv->shared_dplls[i];
4130
4131 WARN_ON(pll->new_config == &pll->config);
4132
4133 kfree(pll->new_config);
4134 pll->new_config = NULL;
4135 }
4136 }
4137
4138 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4139 {
4140 struct drm_i915_private *dev_priv = dev->dev_private;
4141 int dslreg = PIPEDSL(pipe);
4142 u32 temp;
4143
4144 temp = I915_READ(dslreg);
4145 udelay(500);
4146 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4147 if (wait_for(I915_READ(dslreg) != temp, 5))
4148 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4149 }
4150 }
4151
4152 static void skylake_pfit_enable(struct intel_crtc *crtc)
4153 {
4154 struct drm_device *dev = crtc->base.dev;
4155 struct drm_i915_private *dev_priv = dev->dev_private;
4156 int pipe = crtc->pipe;
4157
4158 if (crtc->config->pch_pfit.enabled) {
4159 I915_WRITE(PS_CTL(pipe), PS_ENABLE);
4160 I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4161 I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4162 }
4163 }
4164
4165 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4166 {
4167 struct drm_device *dev = crtc->base.dev;
4168 struct drm_i915_private *dev_priv = dev->dev_private;
4169 int pipe = crtc->pipe;
4170
4171 if (crtc->config->pch_pfit.enabled) {
4172 /* Force use of hard-coded filter coefficients
4173 * as some pre-programmed values are broken,
4174 * e.g. x201.
4175 */
4176 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4177 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4178 PF_PIPE_SEL_IVB(pipe));
4179 else
4180 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4181 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4182 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4183 }
4184 }
4185
4186 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4187 {
4188 struct drm_device *dev = crtc->dev;
4189 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4190 struct drm_plane *plane;
4191 struct intel_plane *intel_plane;
4192
4193 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4194 intel_plane = to_intel_plane(plane);
4195 if (intel_plane->pipe == pipe)
4196 intel_plane_restore(&intel_plane->base);
4197 }
4198 }
4199
4200 /*
4201 * Disable a plane internally without actually modifying the plane's state.
4202 * This will allow us to easily restore the plane later by just reprogramming
4203 * its state.
4204 */
4205 static void disable_plane_internal(struct drm_plane *plane)
4206 {
4207 struct intel_plane *intel_plane = to_intel_plane(plane);
4208 struct drm_plane_state *state =
4209 plane->funcs->atomic_duplicate_state(plane);
4210 struct intel_plane_state *intel_state = to_intel_plane_state(state);
4211
4212 intel_state->visible = false;
4213 intel_plane->commit_plane(plane, intel_state);
4214
4215 intel_plane_destroy_state(plane, state);
4216 }
4217
4218 static void intel_disable_sprite_planes(struct drm_crtc *crtc)
4219 {
4220 struct drm_device *dev = crtc->dev;
4221 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4222 struct drm_plane *plane;
4223 struct intel_plane *intel_plane;
4224
4225 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4226 intel_plane = to_intel_plane(plane);
4227 if (plane->fb && intel_plane->pipe == pipe)
4228 disable_plane_internal(plane);
4229 }
4230 }
4231
4232 void hsw_enable_ips(struct intel_crtc *crtc)
4233 {
4234 struct drm_device *dev = crtc->base.dev;
4235 struct drm_i915_private *dev_priv = dev->dev_private;
4236
4237 if (!crtc->config->ips_enabled)
4238 return;
4239
4240 /* We can only enable IPS after we enable a plane and wait for a vblank */
4241 intel_wait_for_vblank(dev, crtc->pipe);
4242
4243 assert_plane_enabled(dev_priv, crtc->plane);
4244 if (IS_BROADWELL(dev)) {
4245 mutex_lock(&dev_priv->rps.hw_lock);
4246 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4247 mutex_unlock(&dev_priv->rps.hw_lock);
4248 /* Quoting Art Runyan: "its not safe to expect any particular
4249 * value in IPS_CTL bit 31 after enabling IPS through the
4250 * mailbox." Moreover, the mailbox may return a bogus state,
4251 * so we need to just enable it and continue on.
4252 */
4253 } else {
4254 I915_WRITE(IPS_CTL, IPS_ENABLE);
4255 /* The bit only becomes 1 in the next vblank, so this wait here
4256 * is essentially intel_wait_for_vblank. If we don't have this
4257 * and don't wait for vblanks until the end of crtc_enable, then
4258 * the HW state readout code will complain that the expected
4259 * IPS_CTL value is not the one we read. */
4260 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4261 DRM_ERROR("Timed out waiting for IPS enable\n");
4262 }
4263 }
4264
4265 void hsw_disable_ips(struct intel_crtc *crtc)
4266 {
4267 struct drm_device *dev = crtc->base.dev;
4268 struct drm_i915_private *dev_priv = dev->dev_private;
4269
4270 if (!crtc->config->ips_enabled)
4271 return;
4272
4273 assert_plane_enabled(dev_priv, crtc->plane);
4274 if (IS_BROADWELL(dev)) {
4275 mutex_lock(&dev_priv->rps.hw_lock);
4276 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4277 mutex_unlock(&dev_priv->rps.hw_lock);
4278 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4279 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4280 DRM_ERROR("Timed out waiting for IPS disable\n");
4281 } else {
4282 I915_WRITE(IPS_CTL, 0);
4283 POSTING_READ(IPS_CTL);
4284 }
4285
4286 /* We need to wait for a vblank before we can disable the plane. */
4287 intel_wait_for_vblank(dev, crtc->pipe);
4288 }
4289
4290 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4291 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4292 {
4293 struct drm_device *dev = crtc->dev;
4294 struct drm_i915_private *dev_priv = dev->dev_private;
4295 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4296 enum pipe pipe = intel_crtc->pipe;
4297 int palreg = PALETTE(pipe);
4298 int i;
4299 bool reenable_ips = false;
4300
4301 /* The clocks have to be on to load the palette. */
4302 if (!crtc->state->enable || !intel_crtc->active)
4303 return;
4304
4305 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4306 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4307 assert_dsi_pll_enabled(dev_priv);
4308 else
4309 assert_pll_enabled(dev_priv, pipe);
4310 }
4311
4312 /* use legacy palette for Ironlake */
4313 if (!HAS_GMCH_DISPLAY(dev))
4314 palreg = LGC_PALETTE(pipe);
4315
4316 /* Workaround : Do not read or write the pipe palette/gamma data while
4317 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4318 */
4319 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4320 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4321 GAMMA_MODE_MODE_SPLIT)) {
4322 hsw_disable_ips(intel_crtc);
4323 reenable_ips = true;
4324 }
4325
4326 for (i = 0; i < 256; i++) {
4327 I915_WRITE(palreg + 4 * i,
4328 (intel_crtc->lut_r[i] << 16) |
4329 (intel_crtc->lut_g[i] << 8) |
4330 intel_crtc->lut_b[i]);
4331 }
4332
4333 if (reenable_ips)
4334 hsw_enable_ips(intel_crtc);
4335 }
4336
4337 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4338 {
4339 if (!enable && intel_crtc->overlay) {
4340 struct drm_device *dev = intel_crtc->base.dev;
4341 struct drm_i915_private *dev_priv = dev->dev_private;
4342
4343 mutex_lock(&dev->struct_mutex);
4344 dev_priv->mm.interruptible = false;
4345 (void) intel_overlay_switch_off(intel_crtc->overlay);
4346 dev_priv->mm.interruptible = true;
4347 mutex_unlock(&dev->struct_mutex);
4348 }
4349
4350 /* Let userspace switch the overlay on again. In most cases userspace
4351 * has to recompute where to put it anyway.
4352 */
4353 }
4354
4355 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4356 {
4357 struct drm_device *dev = crtc->dev;
4358 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4359 int pipe = intel_crtc->pipe;
4360
4361 intel_enable_primary_hw_plane(crtc->primary, crtc);
4362 intel_enable_sprite_planes(crtc);
4363 intel_crtc_update_cursor(crtc, true);
4364 intel_crtc_dpms_overlay(intel_crtc, true);
4365
4366 hsw_enable_ips(intel_crtc);
4367
4368 mutex_lock(&dev->struct_mutex);
4369 intel_fbc_update(dev);
4370 mutex_unlock(&dev->struct_mutex);
4371
4372 /*
4373 * FIXME: Once we grow proper nuclear flip support out of this we need
4374 * to compute the mask of flip planes precisely. For the time being
4375 * consider this a flip from a NULL plane.
4376 */
4377 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4378 }
4379
4380 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4381 {
4382 struct drm_device *dev = crtc->dev;
4383 struct drm_i915_private *dev_priv = dev->dev_private;
4384 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4385 int pipe = intel_crtc->pipe;
4386
4387 intel_crtc_wait_for_pending_flips(crtc);
4388
4389 if (dev_priv->fbc.crtc == intel_crtc)
4390 intel_fbc_disable(dev);
4391
4392 hsw_disable_ips(intel_crtc);
4393
4394 intel_crtc_dpms_overlay(intel_crtc, false);
4395 intel_crtc_update_cursor(crtc, false);
4396 intel_disable_sprite_planes(crtc);
4397 intel_disable_primary_hw_plane(crtc->primary, crtc);
4398
4399 /*
4400 * FIXME: Once we grow proper nuclear flip support out of this we need
4401 * to compute the mask of flip planes precisely. For the time being
4402 * consider this a flip to a NULL plane.
4403 */
4404 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4405 }
4406
4407 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4408 {
4409 struct drm_device *dev = crtc->dev;
4410 struct drm_i915_private *dev_priv = dev->dev_private;
4411 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4412 struct intel_encoder *encoder;
4413 int pipe = intel_crtc->pipe;
4414
4415 WARN_ON(!crtc->state->enable);
4416
4417 if (intel_crtc->active)
4418 return;
4419
4420 if (intel_crtc->config->has_pch_encoder)
4421 intel_prepare_shared_dpll(intel_crtc);
4422
4423 if (intel_crtc->config->has_dp_encoder)
4424 intel_dp_set_m_n(intel_crtc, M1_N1);
4425
4426 intel_set_pipe_timings(intel_crtc);
4427
4428 if (intel_crtc->config->has_pch_encoder) {
4429 intel_cpu_transcoder_set_m_n(intel_crtc,
4430 &intel_crtc->config->fdi_m_n, NULL);
4431 }
4432
4433 ironlake_set_pipeconf(crtc);
4434
4435 intel_crtc->active = true;
4436
4437 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4438 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4439
4440 for_each_encoder_on_crtc(dev, crtc, encoder)
4441 if (encoder->pre_enable)
4442 encoder->pre_enable(encoder);
4443
4444 if (intel_crtc->config->has_pch_encoder) {
4445 /* Note: FDI PLL enabling _must_ be done before we enable the
4446 * cpu pipes, hence this is separate from all the other fdi/pch
4447 * enabling. */
4448 ironlake_fdi_pll_enable(intel_crtc);
4449 } else {
4450 assert_fdi_tx_disabled(dev_priv, pipe);
4451 assert_fdi_rx_disabled(dev_priv, pipe);
4452 }
4453
4454 ironlake_pfit_enable(intel_crtc);
4455
4456 /*
4457 * On ILK+ LUT must be loaded before the pipe is running but with
4458 * clocks enabled
4459 */
4460 intel_crtc_load_lut(crtc);
4461
4462 intel_update_watermarks(crtc);
4463 intel_enable_pipe(intel_crtc);
4464
4465 if (intel_crtc->config->has_pch_encoder)
4466 ironlake_pch_enable(crtc);
4467
4468 assert_vblank_disabled(crtc);
4469 drm_crtc_vblank_on(crtc);
4470
4471 for_each_encoder_on_crtc(dev, crtc, encoder)
4472 encoder->enable(encoder);
4473
4474 if (HAS_PCH_CPT(dev))
4475 cpt_verify_modeset(dev, intel_crtc->pipe);
4476
4477 intel_crtc_enable_planes(crtc);
4478 }
4479
4480 /* IPS only exists on ULT machines and is tied to pipe A. */
4481 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4482 {
4483 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4484 }
4485
4486 /*
4487 * This implements the workaround described in the "notes" section of the mode
4488 * set sequence documentation. When going from no pipes or single pipe to
4489 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4490 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4491 */
4492 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4493 {
4494 struct drm_device *dev = crtc->base.dev;
4495 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4496
4497 /* We want to get the other_active_crtc only if there's only 1 other
4498 * active crtc. */
4499 for_each_intel_crtc(dev, crtc_it) {
4500 if (!crtc_it->active || crtc_it == crtc)
4501 continue;
4502
4503 if (other_active_crtc)
4504 return;
4505
4506 other_active_crtc = crtc_it;
4507 }
4508 if (!other_active_crtc)
4509 return;
4510
4511 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4512 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4513 }
4514
4515 static void haswell_crtc_enable(struct drm_crtc *crtc)
4516 {
4517 struct drm_device *dev = crtc->dev;
4518 struct drm_i915_private *dev_priv = dev->dev_private;
4519 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4520 struct intel_encoder *encoder;
4521 int pipe = intel_crtc->pipe;
4522
4523 WARN_ON(!crtc->state->enable);
4524
4525 if (intel_crtc->active)
4526 return;
4527
4528 if (intel_crtc_to_shared_dpll(intel_crtc))
4529 intel_enable_shared_dpll(intel_crtc);
4530
4531 if (intel_crtc->config->has_dp_encoder)
4532 intel_dp_set_m_n(intel_crtc, M1_N1);
4533
4534 intel_set_pipe_timings(intel_crtc);
4535
4536 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4537 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4538 intel_crtc->config->pixel_multiplier - 1);
4539 }
4540
4541 if (intel_crtc->config->has_pch_encoder) {
4542 intel_cpu_transcoder_set_m_n(intel_crtc,
4543 &intel_crtc->config->fdi_m_n, NULL);
4544 }
4545
4546 haswell_set_pipeconf(crtc);
4547
4548 intel_set_pipe_csc(crtc);
4549
4550 intel_crtc->active = true;
4551
4552 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4553 for_each_encoder_on_crtc(dev, crtc, encoder)
4554 if (encoder->pre_enable)
4555 encoder->pre_enable(encoder);
4556
4557 if (intel_crtc->config->has_pch_encoder) {
4558 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4559 true);
4560 dev_priv->display.fdi_link_train(crtc);
4561 }
4562
4563 intel_ddi_enable_pipe_clock(intel_crtc);
4564
4565 if (IS_SKYLAKE(dev))
4566 skylake_pfit_enable(intel_crtc);
4567 else
4568 ironlake_pfit_enable(intel_crtc);
4569
4570 /*
4571 * On ILK+ LUT must be loaded before the pipe is running but with
4572 * clocks enabled
4573 */
4574 intel_crtc_load_lut(crtc);
4575
4576 intel_ddi_set_pipe_settings(crtc);
4577 intel_ddi_enable_transcoder_func(crtc);
4578
4579 intel_update_watermarks(crtc);
4580 intel_enable_pipe(intel_crtc);
4581
4582 if (intel_crtc->config->has_pch_encoder)
4583 lpt_pch_enable(crtc);
4584
4585 if (intel_crtc->config->dp_encoder_is_mst)
4586 intel_ddi_set_vc_payload_alloc(crtc, true);
4587
4588 assert_vblank_disabled(crtc);
4589 drm_crtc_vblank_on(crtc);
4590
4591 for_each_encoder_on_crtc(dev, crtc, encoder) {
4592 encoder->enable(encoder);
4593 intel_opregion_notify_encoder(encoder, true);
4594 }
4595
4596 /* If we change the relative order between pipe/planes enabling, we need
4597 * to change the workaround. */
4598 haswell_mode_set_planes_workaround(intel_crtc);
4599 intel_crtc_enable_planes(crtc);
4600 }
4601
4602 static void skylake_pfit_disable(struct intel_crtc *crtc)
4603 {
4604 struct drm_device *dev = crtc->base.dev;
4605 struct drm_i915_private *dev_priv = dev->dev_private;
4606 int pipe = crtc->pipe;
4607
4608 /* To avoid upsetting the power well on haswell only disable the pfit if
4609 * it's in use. The hw state code will make sure we get this right. */
4610 if (crtc->config->pch_pfit.enabled) {
4611 I915_WRITE(PS_CTL(pipe), 0);
4612 I915_WRITE(PS_WIN_POS(pipe), 0);
4613 I915_WRITE(PS_WIN_SZ(pipe), 0);
4614 }
4615 }
4616
4617 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4618 {
4619 struct drm_device *dev = crtc->base.dev;
4620 struct drm_i915_private *dev_priv = dev->dev_private;
4621 int pipe = crtc->pipe;
4622
4623 /* To avoid upsetting the power well on haswell only disable the pfit if
4624 * it's in use. The hw state code will make sure we get this right. */
4625 if (crtc->config->pch_pfit.enabled) {
4626 I915_WRITE(PF_CTL(pipe), 0);
4627 I915_WRITE(PF_WIN_POS(pipe), 0);
4628 I915_WRITE(PF_WIN_SZ(pipe), 0);
4629 }
4630 }
4631
4632 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4633 {
4634 struct drm_device *dev = crtc->dev;
4635 struct drm_i915_private *dev_priv = dev->dev_private;
4636 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4637 struct intel_encoder *encoder;
4638 int pipe = intel_crtc->pipe;
4639 u32 reg, temp;
4640
4641 if (!intel_crtc->active)
4642 return;
4643
4644 intel_crtc_disable_planes(crtc);
4645
4646 for_each_encoder_on_crtc(dev, crtc, encoder)
4647 encoder->disable(encoder);
4648
4649 drm_crtc_vblank_off(crtc);
4650 assert_vblank_disabled(crtc);
4651
4652 if (intel_crtc->config->has_pch_encoder)
4653 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4654
4655 intel_disable_pipe(intel_crtc);
4656
4657 ironlake_pfit_disable(intel_crtc);
4658
4659 for_each_encoder_on_crtc(dev, crtc, encoder)
4660 if (encoder->post_disable)
4661 encoder->post_disable(encoder);
4662
4663 if (intel_crtc->config->has_pch_encoder) {
4664 ironlake_fdi_disable(crtc);
4665
4666 ironlake_disable_pch_transcoder(dev_priv, pipe);
4667
4668 if (HAS_PCH_CPT(dev)) {
4669 /* disable TRANS_DP_CTL */
4670 reg = TRANS_DP_CTL(pipe);
4671 temp = I915_READ(reg);
4672 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4673 TRANS_DP_PORT_SEL_MASK);
4674 temp |= TRANS_DP_PORT_SEL_NONE;
4675 I915_WRITE(reg, temp);
4676
4677 /* disable DPLL_SEL */
4678 temp = I915_READ(PCH_DPLL_SEL);
4679 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4680 I915_WRITE(PCH_DPLL_SEL, temp);
4681 }
4682
4683 /* disable PCH DPLL */
4684 intel_disable_shared_dpll(intel_crtc);
4685
4686 ironlake_fdi_pll_disable(intel_crtc);
4687 }
4688
4689 intel_crtc->active = false;
4690 intel_update_watermarks(crtc);
4691
4692 mutex_lock(&dev->struct_mutex);
4693 intel_fbc_update(dev);
4694 mutex_unlock(&dev->struct_mutex);
4695 }
4696
4697 static void haswell_crtc_disable(struct drm_crtc *crtc)
4698 {
4699 struct drm_device *dev = crtc->dev;
4700 struct drm_i915_private *dev_priv = dev->dev_private;
4701 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4702 struct intel_encoder *encoder;
4703 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4704
4705 if (!intel_crtc->active)
4706 return;
4707
4708 intel_crtc_disable_planes(crtc);
4709
4710 for_each_encoder_on_crtc(dev, crtc, encoder) {
4711 intel_opregion_notify_encoder(encoder, false);
4712 encoder->disable(encoder);
4713 }
4714
4715 drm_crtc_vblank_off(crtc);
4716 assert_vblank_disabled(crtc);
4717
4718 if (intel_crtc->config->has_pch_encoder)
4719 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4720 false);
4721 intel_disable_pipe(intel_crtc);
4722
4723 if (intel_crtc->config->dp_encoder_is_mst)
4724 intel_ddi_set_vc_payload_alloc(crtc, false);
4725
4726 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4727
4728 if (IS_SKYLAKE(dev))
4729 skylake_pfit_disable(intel_crtc);
4730 else
4731 ironlake_pfit_disable(intel_crtc);
4732
4733 intel_ddi_disable_pipe_clock(intel_crtc);
4734
4735 if (intel_crtc->config->has_pch_encoder) {
4736 lpt_disable_pch_transcoder(dev_priv);
4737 intel_ddi_fdi_disable(crtc);
4738 }
4739
4740 for_each_encoder_on_crtc(dev, crtc, encoder)
4741 if (encoder->post_disable)
4742 encoder->post_disable(encoder);
4743
4744 intel_crtc->active = false;
4745 intel_update_watermarks(crtc);
4746
4747 mutex_lock(&dev->struct_mutex);
4748 intel_fbc_update(dev);
4749 mutex_unlock(&dev->struct_mutex);
4750
4751 if (intel_crtc_to_shared_dpll(intel_crtc))
4752 intel_disable_shared_dpll(intel_crtc);
4753 }
4754
4755 static void ironlake_crtc_off(struct drm_crtc *crtc)
4756 {
4757 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4758 intel_put_shared_dpll(intel_crtc);
4759 }
4760
4761
4762 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4763 {
4764 struct drm_device *dev = crtc->base.dev;
4765 struct drm_i915_private *dev_priv = dev->dev_private;
4766 struct intel_crtc_state *pipe_config = crtc->config;
4767
4768 if (!pipe_config->gmch_pfit.control)
4769 return;
4770
4771 /*
4772 * The panel fitter should only be adjusted whilst the pipe is disabled,
4773 * according to register description and PRM.
4774 */
4775 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4776 assert_pipe_disabled(dev_priv, crtc->pipe);
4777
4778 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4779 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4780
4781 /* Border color in case we don't scale up to the full screen. Black by
4782 * default, change to something else for debugging. */
4783 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4784 }
4785
4786 static enum intel_display_power_domain port_to_power_domain(enum port port)
4787 {
4788 switch (port) {
4789 case PORT_A:
4790 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4791 case PORT_B:
4792 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4793 case PORT_C:
4794 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4795 case PORT_D:
4796 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4797 default:
4798 WARN_ON_ONCE(1);
4799 return POWER_DOMAIN_PORT_OTHER;
4800 }
4801 }
4802
4803 #define for_each_power_domain(domain, mask) \
4804 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4805 if ((1 << (domain)) & (mask))
4806
4807 enum intel_display_power_domain
4808 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4809 {
4810 struct drm_device *dev = intel_encoder->base.dev;
4811 struct intel_digital_port *intel_dig_port;
4812
4813 switch (intel_encoder->type) {
4814 case INTEL_OUTPUT_UNKNOWN:
4815 /* Only DDI platforms should ever use this output type */
4816 WARN_ON_ONCE(!HAS_DDI(dev));
4817 case INTEL_OUTPUT_DISPLAYPORT:
4818 case INTEL_OUTPUT_HDMI:
4819 case INTEL_OUTPUT_EDP:
4820 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4821 return port_to_power_domain(intel_dig_port->port);
4822 case INTEL_OUTPUT_DP_MST:
4823 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4824 return port_to_power_domain(intel_dig_port->port);
4825 case INTEL_OUTPUT_ANALOG:
4826 return POWER_DOMAIN_PORT_CRT;
4827 case INTEL_OUTPUT_DSI:
4828 return POWER_DOMAIN_PORT_DSI;
4829 default:
4830 return POWER_DOMAIN_PORT_OTHER;
4831 }
4832 }
4833
4834 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4835 {
4836 struct drm_device *dev = crtc->dev;
4837 struct intel_encoder *intel_encoder;
4838 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4839 enum pipe pipe = intel_crtc->pipe;
4840 unsigned long mask;
4841 enum transcoder transcoder;
4842
4843 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4844
4845 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4846 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4847 if (intel_crtc->config->pch_pfit.enabled ||
4848 intel_crtc->config->pch_pfit.force_thru)
4849 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4850
4851 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4852 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4853
4854 return mask;
4855 }
4856
4857 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4858 {
4859 struct drm_i915_private *dev_priv = dev->dev_private;
4860 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4861 struct intel_crtc *crtc;
4862
4863 /*
4864 * First get all needed power domains, then put all unneeded, to avoid
4865 * any unnecessary toggling of the power wells.
4866 */
4867 for_each_intel_crtc(dev, crtc) {
4868 enum intel_display_power_domain domain;
4869
4870 if (!crtc->base.state->enable)
4871 continue;
4872
4873 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4874
4875 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4876 intel_display_power_get(dev_priv, domain);
4877 }
4878
4879 if (dev_priv->display.modeset_global_resources)
4880 dev_priv->display.modeset_global_resources(dev);
4881
4882 for_each_intel_crtc(dev, crtc) {
4883 enum intel_display_power_domain domain;
4884
4885 for_each_power_domain(domain, crtc->enabled_power_domains)
4886 intel_display_power_put(dev_priv, domain);
4887
4888 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4889 }
4890
4891 intel_display_set_init_power(dev_priv, false);
4892 }
4893
4894 /* returns HPLL frequency in kHz */
4895 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4896 {
4897 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4898
4899 /* Obtain SKU information */
4900 mutex_lock(&dev_priv->dpio_lock);
4901 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4902 CCK_FUSE_HPLL_FREQ_MASK;
4903 mutex_unlock(&dev_priv->dpio_lock);
4904
4905 return vco_freq[hpll_freq] * 1000;
4906 }
4907
4908 static void vlv_update_cdclk(struct drm_device *dev)
4909 {
4910 struct drm_i915_private *dev_priv = dev->dev_private;
4911
4912 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4913 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4914 dev_priv->vlv_cdclk_freq);
4915
4916 /*
4917 * Program the gmbus_freq based on the cdclk frequency.
4918 * BSpec erroneously claims we should aim for 4MHz, but
4919 * in fact 1MHz is the correct frequency.
4920 */
4921 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
4922 }
4923
4924 /* Adjust CDclk dividers to allow high res or save power if possible */
4925 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4926 {
4927 struct drm_i915_private *dev_priv = dev->dev_private;
4928 u32 val, cmd;
4929
4930 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4931
4932 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4933 cmd = 2;
4934 else if (cdclk == 266667)
4935 cmd = 1;
4936 else
4937 cmd = 0;
4938
4939 mutex_lock(&dev_priv->rps.hw_lock);
4940 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4941 val &= ~DSPFREQGUAR_MASK;
4942 val |= (cmd << DSPFREQGUAR_SHIFT);
4943 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4944 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4945 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4946 50)) {
4947 DRM_ERROR("timed out waiting for CDclk change\n");
4948 }
4949 mutex_unlock(&dev_priv->rps.hw_lock);
4950
4951 if (cdclk == 400000) {
4952 u32 divider;
4953
4954 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
4955
4956 mutex_lock(&dev_priv->dpio_lock);
4957 /* adjust cdclk divider */
4958 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4959 val &= ~DISPLAY_FREQUENCY_VALUES;
4960 val |= divider;
4961 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4962
4963 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4964 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4965 50))
4966 DRM_ERROR("timed out waiting for CDclk change\n");
4967 mutex_unlock(&dev_priv->dpio_lock);
4968 }
4969
4970 mutex_lock(&dev_priv->dpio_lock);
4971 /* adjust self-refresh exit latency value */
4972 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4973 val &= ~0x7f;
4974
4975 /*
4976 * For high bandwidth configs, we set a higher latency in the bunit
4977 * so that the core display fetch happens in time to avoid underruns.
4978 */
4979 if (cdclk == 400000)
4980 val |= 4500 / 250; /* 4.5 usec */
4981 else
4982 val |= 3000 / 250; /* 3.0 usec */
4983 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4984 mutex_unlock(&dev_priv->dpio_lock);
4985
4986 vlv_update_cdclk(dev);
4987 }
4988
4989 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4990 {
4991 struct drm_i915_private *dev_priv = dev->dev_private;
4992 u32 val, cmd;
4993
4994 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4995
4996 switch (cdclk) {
4997 case 333333:
4998 case 320000:
4999 case 266667:
5000 case 200000:
5001 break;
5002 default:
5003 MISSING_CASE(cdclk);
5004 return;
5005 }
5006
5007 /*
5008 * Specs are full of misinformation, but testing on actual
5009 * hardware has shown that we just need to write the desired
5010 * CCK divider into the Punit register.
5011 */
5012 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5013
5014 mutex_lock(&dev_priv->rps.hw_lock);
5015 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5016 val &= ~DSPFREQGUAR_MASK_CHV;
5017 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5018 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5019 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5020 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5021 50)) {
5022 DRM_ERROR("timed out waiting for CDclk change\n");
5023 }
5024 mutex_unlock(&dev_priv->rps.hw_lock);
5025
5026 vlv_update_cdclk(dev);
5027 }
5028
5029 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5030 int max_pixclk)
5031 {
5032 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5033 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5034
5035 /*
5036 * Really only a few cases to deal with, as only 4 CDclks are supported:
5037 * 200MHz
5038 * 267MHz
5039 * 320/333MHz (depends on HPLL freq)
5040 * 400MHz (VLV only)
5041 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5042 * of the lower bin and adjust if needed.
5043 *
5044 * We seem to get an unstable or solid color picture at 200MHz.
5045 * Not sure what's wrong. For now use 200MHz only when all pipes
5046 * are off.
5047 */
5048 if (!IS_CHERRYVIEW(dev_priv) &&
5049 max_pixclk > freq_320*limit/100)
5050 return 400000;
5051 else if (max_pixclk > 266667*limit/100)
5052 return freq_320;
5053 else if (max_pixclk > 0)
5054 return 266667;
5055 else
5056 return 200000;
5057 }
5058
5059 /* compute the max pixel clock for new configuration */
5060 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
5061 {
5062 struct drm_device *dev = dev_priv->dev;
5063 struct intel_crtc *intel_crtc;
5064 int max_pixclk = 0;
5065
5066 for_each_intel_crtc(dev, intel_crtc) {
5067 if (intel_crtc->new_enabled)
5068 max_pixclk = max(max_pixclk,
5069 intel_crtc->new_config->base.adjusted_mode.crtc_clock);
5070 }
5071
5072 return max_pixclk;
5073 }
5074
5075 static void valleyview_modeset_global_pipes(struct drm_device *dev,
5076 unsigned *prepare_pipes)
5077 {
5078 struct drm_i915_private *dev_priv = dev->dev_private;
5079 struct intel_crtc *intel_crtc;
5080 int max_pixclk = intel_mode_max_pixclk(dev_priv);
5081
5082 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
5083 dev_priv->vlv_cdclk_freq)
5084 return;
5085
5086 /* disable/enable all currently active pipes while we change cdclk */
5087 for_each_intel_crtc(dev, intel_crtc)
5088 if (intel_crtc->base.state->enable)
5089 *prepare_pipes |= (1 << intel_crtc->pipe);
5090 }
5091
5092 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5093 {
5094 unsigned int credits, default_credits;
5095
5096 if (IS_CHERRYVIEW(dev_priv))
5097 default_credits = PFI_CREDIT(12);
5098 else
5099 default_credits = PFI_CREDIT(8);
5100
5101 if (DIV_ROUND_CLOSEST(dev_priv->vlv_cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5102 /* CHV suggested value is 31 or 63 */
5103 if (IS_CHERRYVIEW(dev_priv))
5104 credits = PFI_CREDIT_31;
5105 else
5106 credits = PFI_CREDIT(15);
5107 } else {
5108 credits = default_credits;
5109 }
5110
5111 /*
5112 * WA - write default credits before re-programming
5113 * FIXME: should we also set the resend bit here?
5114 */
5115 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5116 default_credits);
5117
5118 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5119 credits | PFI_CREDIT_RESEND);
5120
5121 /*
5122 * FIXME is this guaranteed to clear
5123 * immediately or should we poll for it?
5124 */
5125 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5126 }
5127
5128 static void valleyview_modeset_global_resources(struct drm_device *dev)
5129 {
5130 struct drm_i915_private *dev_priv = dev->dev_private;
5131 int max_pixclk = intel_mode_max_pixclk(dev_priv);
5132 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5133
5134 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
5135 /*
5136 * FIXME: We can end up here with all power domains off, yet
5137 * with a CDCLK frequency other than the minimum. To account
5138 * for this take the PIPE-A power domain, which covers the HW
5139 * blocks needed for the following programming. This can be
5140 * removed once it's guaranteed that we get here either with
5141 * the minimum CDCLK set, or the required power domains
5142 * enabled.
5143 */
5144 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5145
5146 if (IS_CHERRYVIEW(dev))
5147 cherryview_set_cdclk(dev, req_cdclk);
5148 else
5149 valleyview_set_cdclk(dev, req_cdclk);
5150
5151 vlv_program_pfi_credits(dev_priv);
5152
5153 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5154 }
5155 }
5156
5157 static void valleyview_crtc_enable(struct drm_crtc *crtc)
5158 {
5159 struct drm_device *dev = crtc->dev;
5160 struct drm_i915_private *dev_priv = to_i915(dev);
5161 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5162 struct intel_encoder *encoder;
5163 int pipe = intel_crtc->pipe;
5164 bool is_dsi;
5165
5166 WARN_ON(!crtc->state->enable);
5167
5168 if (intel_crtc->active)
5169 return;
5170
5171 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5172
5173 if (!is_dsi) {
5174 if (IS_CHERRYVIEW(dev))
5175 chv_prepare_pll(intel_crtc, intel_crtc->config);
5176 else
5177 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5178 }
5179
5180 if (intel_crtc->config->has_dp_encoder)
5181 intel_dp_set_m_n(intel_crtc, M1_N1);
5182
5183 intel_set_pipe_timings(intel_crtc);
5184
5185 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5186 struct drm_i915_private *dev_priv = dev->dev_private;
5187
5188 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5189 I915_WRITE(CHV_CANVAS(pipe), 0);
5190 }
5191
5192 i9xx_set_pipeconf(intel_crtc);
5193
5194 intel_crtc->active = true;
5195
5196 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5197
5198 for_each_encoder_on_crtc(dev, crtc, encoder)
5199 if (encoder->pre_pll_enable)
5200 encoder->pre_pll_enable(encoder);
5201
5202 if (!is_dsi) {
5203 if (IS_CHERRYVIEW(dev))
5204 chv_enable_pll(intel_crtc, intel_crtc->config);
5205 else
5206 vlv_enable_pll(intel_crtc, intel_crtc->config);
5207 }
5208
5209 for_each_encoder_on_crtc(dev, crtc, encoder)
5210 if (encoder->pre_enable)
5211 encoder->pre_enable(encoder);
5212
5213 i9xx_pfit_enable(intel_crtc);
5214
5215 intel_crtc_load_lut(crtc);
5216
5217 intel_update_watermarks(crtc);
5218 intel_enable_pipe(intel_crtc);
5219
5220 assert_vblank_disabled(crtc);
5221 drm_crtc_vblank_on(crtc);
5222
5223 for_each_encoder_on_crtc(dev, crtc, encoder)
5224 encoder->enable(encoder);
5225
5226 intel_crtc_enable_planes(crtc);
5227
5228 /* Underruns don't raise interrupts, so check manually. */
5229 i9xx_check_fifo_underruns(dev_priv);
5230 }
5231
5232 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5233 {
5234 struct drm_device *dev = crtc->base.dev;
5235 struct drm_i915_private *dev_priv = dev->dev_private;
5236
5237 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5238 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5239 }
5240
5241 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5242 {
5243 struct drm_device *dev = crtc->dev;
5244 struct drm_i915_private *dev_priv = to_i915(dev);
5245 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5246 struct intel_encoder *encoder;
5247 int pipe = intel_crtc->pipe;
5248
5249 WARN_ON(!crtc->state->enable);
5250
5251 if (intel_crtc->active)
5252 return;
5253
5254 i9xx_set_pll_dividers(intel_crtc);
5255
5256 if (intel_crtc->config->has_dp_encoder)
5257 intel_dp_set_m_n(intel_crtc, M1_N1);
5258
5259 intel_set_pipe_timings(intel_crtc);
5260
5261 i9xx_set_pipeconf(intel_crtc);
5262
5263 intel_crtc->active = true;
5264
5265 if (!IS_GEN2(dev))
5266 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5267
5268 for_each_encoder_on_crtc(dev, crtc, encoder)
5269 if (encoder->pre_enable)
5270 encoder->pre_enable(encoder);
5271
5272 i9xx_enable_pll(intel_crtc);
5273
5274 i9xx_pfit_enable(intel_crtc);
5275
5276 intel_crtc_load_lut(crtc);
5277
5278 intel_update_watermarks(crtc);
5279 intel_enable_pipe(intel_crtc);
5280
5281 assert_vblank_disabled(crtc);
5282 drm_crtc_vblank_on(crtc);
5283
5284 for_each_encoder_on_crtc(dev, crtc, encoder)
5285 encoder->enable(encoder);
5286
5287 intel_crtc_enable_planes(crtc);
5288
5289 /*
5290 * Gen2 reports pipe underruns whenever all planes are disabled.
5291 * So don't enable underrun reporting before at least some planes
5292 * are enabled.
5293 * FIXME: Need to fix the logic to work when we turn off all planes
5294 * but leave the pipe running.
5295 */
5296 if (IS_GEN2(dev))
5297 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5298
5299 /* Underruns don't raise interrupts, so check manually. */
5300 i9xx_check_fifo_underruns(dev_priv);
5301 }
5302
5303 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5304 {
5305 struct drm_device *dev = crtc->base.dev;
5306 struct drm_i915_private *dev_priv = dev->dev_private;
5307
5308 if (!crtc->config->gmch_pfit.control)
5309 return;
5310
5311 assert_pipe_disabled(dev_priv, crtc->pipe);
5312
5313 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5314 I915_READ(PFIT_CONTROL));
5315 I915_WRITE(PFIT_CONTROL, 0);
5316 }
5317
5318 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5319 {
5320 struct drm_device *dev = crtc->dev;
5321 struct drm_i915_private *dev_priv = dev->dev_private;
5322 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5323 struct intel_encoder *encoder;
5324 int pipe = intel_crtc->pipe;
5325
5326 if (!intel_crtc->active)
5327 return;
5328
5329 /*
5330 * Gen2 reports pipe underruns whenever all planes are disabled.
5331 * So diasble underrun reporting before all the planes get disabled.
5332 * FIXME: Need to fix the logic to work when we turn off all planes
5333 * but leave the pipe running.
5334 */
5335 if (IS_GEN2(dev))
5336 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5337
5338 /*
5339 * Vblank time updates from the shadow to live plane control register
5340 * are blocked if the memory self-refresh mode is active at that
5341 * moment. So to make sure the plane gets truly disabled, disable
5342 * first the self-refresh mode. The self-refresh enable bit in turn
5343 * will be checked/applied by the HW only at the next frame start
5344 * event which is after the vblank start event, so we need to have a
5345 * wait-for-vblank between disabling the plane and the pipe.
5346 */
5347 intel_set_memory_cxsr(dev_priv, false);
5348 intel_crtc_disable_planes(crtc);
5349
5350 /*
5351 * On gen2 planes are double buffered but the pipe isn't, so we must
5352 * wait for planes to fully turn off before disabling the pipe.
5353 * We also need to wait on all gmch platforms because of the
5354 * self-refresh mode constraint explained above.
5355 */
5356 intel_wait_for_vblank(dev, pipe);
5357
5358 for_each_encoder_on_crtc(dev, crtc, encoder)
5359 encoder->disable(encoder);
5360
5361 drm_crtc_vblank_off(crtc);
5362 assert_vblank_disabled(crtc);
5363
5364 intel_disable_pipe(intel_crtc);
5365
5366 i9xx_pfit_disable(intel_crtc);
5367
5368 for_each_encoder_on_crtc(dev, crtc, encoder)
5369 if (encoder->post_disable)
5370 encoder->post_disable(encoder);
5371
5372 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5373 if (IS_CHERRYVIEW(dev))
5374 chv_disable_pll(dev_priv, pipe);
5375 else if (IS_VALLEYVIEW(dev))
5376 vlv_disable_pll(dev_priv, pipe);
5377 else
5378 i9xx_disable_pll(intel_crtc);
5379 }
5380
5381 if (!IS_GEN2(dev))
5382 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5383
5384 intel_crtc->active = false;
5385 intel_update_watermarks(crtc);
5386
5387 mutex_lock(&dev->struct_mutex);
5388 intel_fbc_update(dev);
5389 mutex_unlock(&dev->struct_mutex);
5390 }
5391
5392 static void i9xx_crtc_off(struct drm_crtc *crtc)
5393 {
5394 }
5395
5396 /* Master function to enable/disable CRTC and corresponding power wells */
5397 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5398 {
5399 struct drm_device *dev = crtc->dev;
5400 struct drm_i915_private *dev_priv = dev->dev_private;
5401 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5402 enum intel_display_power_domain domain;
5403 unsigned long domains;
5404
5405 if (enable) {
5406 if (!intel_crtc->active) {
5407 domains = get_crtc_power_domains(crtc);
5408 for_each_power_domain(domain, domains)
5409 intel_display_power_get(dev_priv, domain);
5410 intel_crtc->enabled_power_domains = domains;
5411
5412 dev_priv->display.crtc_enable(crtc);
5413 }
5414 } else {
5415 if (intel_crtc->active) {
5416 dev_priv->display.crtc_disable(crtc);
5417
5418 domains = intel_crtc->enabled_power_domains;
5419 for_each_power_domain(domain, domains)
5420 intel_display_power_put(dev_priv, domain);
5421 intel_crtc->enabled_power_domains = 0;
5422 }
5423 }
5424 }
5425
5426 /**
5427 * Sets the power management mode of the pipe and plane.
5428 */
5429 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5430 {
5431 struct drm_device *dev = crtc->dev;
5432 struct intel_encoder *intel_encoder;
5433 bool enable = false;
5434
5435 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5436 enable |= intel_encoder->connectors_active;
5437
5438 intel_crtc_control(crtc, enable);
5439 }
5440
5441 static void intel_crtc_disable(struct drm_crtc *crtc)
5442 {
5443 struct drm_device *dev = crtc->dev;
5444 struct drm_connector *connector;
5445 struct drm_i915_private *dev_priv = dev->dev_private;
5446
5447 /* crtc should still be enabled when we disable it. */
5448 WARN_ON(!crtc->state->enable);
5449
5450 dev_priv->display.crtc_disable(crtc);
5451 dev_priv->display.off(crtc);
5452
5453 crtc->primary->funcs->disable_plane(crtc->primary);
5454
5455 /* Update computed state. */
5456 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5457 if (!connector->encoder || !connector->encoder->crtc)
5458 continue;
5459
5460 if (connector->encoder->crtc != crtc)
5461 continue;
5462
5463 connector->dpms = DRM_MODE_DPMS_OFF;
5464 to_intel_encoder(connector->encoder)->connectors_active = false;
5465 }
5466 }
5467
5468 void intel_encoder_destroy(struct drm_encoder *encoder)
5469 {
5470 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5471
5472 drm_encoder_cleanup(encoder);
5473 kfree(intel_encoder);
5474 }
5475
5476 /* Simple dpms helper for encoders with just one connector, no cloning and only
5477 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5478 * state of the entire output pipe. */
5479 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5480 {
5481 if (mode == DRM_MODE_DPMS_ON) {
5482 encoder->connectors_active = true;
5483
5484 intel_crtc_update_dpms(encoder->base.crtc);
5485 } else {
5486 encoder->connectors_active = false;
5487
5488 intel_crtc_update_dpms(encoder->base.crtc);
5489 }
5490 }
5491
5492 /* Cross check the actual hw state with our own modeset state tracking (and it's
5493 * internal consistency). */
5494 static void intel_connector_check_state(struct intel_connector *connector)
5495 {
5496 if (connector->get_hw_state(connector)) {
5497 struct intel_encoder *encoder = connector->encoder;
5498 struct drm_crtc *crtc;
5499 bool encoder_enabled;
5500 enum pipe pipe;
5501
5502 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5503 connector->base.base.id,
5504 connector->base.name);
5505
5506 /* there is no real hw state for MST connectors */
5507 if (connector->mst_port)
5508 return;
5509
5510 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5511 "wrong connector dpms state\n");
5512 I915_STATE_WARN(connector->base.encoder != &encoder->base,
5513 "active connector not linked to encoder\n");
5514
5515 if (encoder) {
5516 I915_STATE_WARN(!encoder->connectors_active,
5517 "encoder->connectors_active not set\n");
5518
5519 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5520 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
5521 if (I915_STATE_WARN_ON(!encoder->base.crtc))
5522 return;
5523
5524 crtc = encoder->base.crtc;
5525
5526 I915_STATE_WARN(!crtc->state->enable,
5527 "crtc not enabled\n");
5528 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5529 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
5530 "encoder active on the wrong pipe\n");
5531 }
5532 }
5533 }
5534
5535 /* Even simpler default implementation, if there's really no special case to
5536 * consider. */
5537 void intel_connector_dpms(struct drm_connector *connector, int mode)
5538 {
5539 /* All the simple cases only support two dpms states. */
5540 if (mode != DRM_MODE_DPMS_ON)
5541 mode = DRM_MODE_DPMS_OFF;
5542
5543 if (mode == connector->dpms)
5544 return;
5545
5546 connector->dpms = mode;
5547
5548 /* Only need to change hw state when actually enabled */
5549 if (connector->encoder)
5550 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5551
5552 intel_modeset_check_state(connector->dev);
5553 }
5554
5555 /* Simple connector->get_hw_state implementation for encoders that support only
5556 * one connector and no cloning and hence the encoder state determines the state
5557 * of the connector. */
5558 bool intel_connector_get_hw_state(struct intel_connector *connector)
5559 {
5560 enum pipe pipe = 0;
5561 struct intel_encoder *encoder = connector->encoder;
5562
5563 return encoder->get_hw_state(encoder, &pipe);
5564 }
5565
5566 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5567 struct intel_crtc_state *pipe_config)
5568 {
5569 struct drm_i915_private *dev_priv = dev->dev_private;
5570 struct intel_crtc *pipe_B_crtc =
5571 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5572
5573 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5574 pipe_name(pipe), pipe_config->fdi_lanes);
5575 if (pipe_config->fdi_lanes > 4) {
5576 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5577 pipe_name(pipe), pipe_config->fdi_lanes);
5578 return false;
5579 }
5580
5581 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5582 if (pipe_config->fdi_lanes > 2) {
5583 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5584 pipe_config->fdi_lanes);
5585 return false;
5586 } else {
5587 return true;
5588 }
5589 }
5590
5591 if (INTEL_INFO(dev)->num_pipes == 2)
5592 return true;
5593
5594 /* Ivybridge 3 pipe is really complicated */
5595 switch (pipe) {
5596 case PIPE_A:
5597 return true;
5598 case PIPE_B:
5599 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5600 pipe_config->fdi_lanes > 2) {
5601 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5602 pipe_name(pipe), pipe_config->fdi_lanes);
5603 return false;
5604 }
5605 return true;
5606 case PIPE_C:
5607 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5608 pipe_B_crtc->config->fdi_lanes <= 2) {
5609 if (pipe_config->fdi_lanes > 2) {
5610 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5611 pipe_name(pipe), pipe_config->fdi_lanes);
5612 return false;
5613 }
5614 } else {
5615 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5616 return false;
5617 }
5618 return true;
5619 default:
5620 BUG();
5621 }
5622 }
5623
5624 #define RETRY 1
5625 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5626 struct intel_crtc_state *pipe_config)
5627 {
5628 struct drm_device *dev = intel_crtc->base.dev;
5629 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5630 int lane, link_bw, fdi_dotclock;
5631 bool setup_ok, needs_recompute = false;
5632
5633 retry:
5634 /* FDI is a binary signal running at ~2.7GHz, encoding
5635 * each output octet as 10 bits. The actual frequency
5636 * is stored as a divider into a 100MHz clock, and the
5637 * mode pixel clock is stored in units of 1KHz.
5638 * Hence the bw of each lane in terms of the mode signal
5639 * is:
5640 */
5641 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5642
5643 fdi_dotclock = adjusted_mode->crtc_clock;
5644
5645 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5646 pipe_config->pipe_bpp);
5647
5648 pipe_config->fdi_lanes = lane;
5649
5650 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5651 link_bw, &pipe_config->fdi_m_n);
5652
5653 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5654 intel_crtc->pipe, pipe_config);
5655 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5656 pipe_config->pipe_bpp -= 2*3;
5657 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5658 pipe_config->pipe_bpp);
5659 needs_recompute = true;
5660 pipe_config->bw_constrained = true;
5661
5662 goto retry;
5663 }
5664
5665 if (needs_recompute)
5666 return RETRY;
5667
5668 return setup_ok ? 0 : -EINVAL;
5669 }
5670
5671 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5672 struct intel_crtc_state *pipe_config)
5673 {
5674 pipe_config->ips_enabled = i915.enable_ips &&
5675 hsw_crtc_supports_ips(crtc) &&
5676 pipe_config->pipe_bpp <= 24;
5677 }
5678
5679 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5680 struct intel_crtc_state *pipe_config)
5681 {
5682 struct drm_device *dev = crtc->base.dev;
5683 struct drm_i915_private *dev_priv = dev->dev_private;
5684 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5685
5686 /* FIXME should check pixel clock limits on all platforms */
5687 if (INTEL_INFO(dev)->gen < 4) {
5688 int clock_limit =
5689 dev_priv->display.get_display_clock_speed(dev);
5690
5691 /*
5692 * Enable pixel doubling when the dot clock
5693 * is > 90% of the (display) core speed.
5694 *
5695 * GDG double wide on either pipe,
5696 * otherwise pipe A only.
5697 */
5698 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5699 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5700 clock_limit *= 2;
5701 pipe_config->double_wide = true;
5702 }
5703
5704 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5705 return -EINVAL;
5706 }
5707
5708 /*
5709 * Pipe horizontal size must be even in:
5710 * - DVO ganged mode
5711 * - LVDS dual channel mode
5712 * - Double wide pipe
5713 */
5714 if ((intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5715 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5716 pipe_config->pipe_src_w &= ~1;
5717
5718 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5719 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5720 */
5721 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5722 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5723 return -EINVAL;
5724
5725 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5726 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5727 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5728 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5729 * for lvds. */
5730 pipe_config->pipe_bpp = 8*3;
5731 }
5732
5733 if (HAS_IPS(dev))
5734 hsw_compute_ips_config(crtc, pipe_config);
5735
5736 if (pipe_config->has_pch_encoder)
5737 return ironlake_fdi_compute_config(crtc, pipe_config);
5738
5739 return 0;
5740 }
5741
5742 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5743 {
5744 struct drm_i915_private *dev_priv = dev->dev_private;
5745 u32 val;
5746 int divider;
5747
5748 if (dev_priv->hpll_freq == 0)
5749 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5750
5751 mutex_lock(&dev_priv->dpio_lock);
5752 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5753 mutex_unlock(&dev_priv->dpio_lock);
5754
5755 divider = val & DISPLAY_FREQUENCY_VALUES;
5756
5757 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5758 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5759 "cdclk change in progress\n");
5760
5761 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
5762 }
5763
5764 static int i945_get_display_clock_speed(struct drm_device *dev)
5765 {
5766 return 400000;
5767 }
5768
5769 static int i915_get_display_clock_speed(struct drm_device *dev)
5770 {
5771 return 333000;
5772 }
5773
5774 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5775 {
5776 return 200000;
5777 }
5778
5779 static int pnv_get_display_clock_speed(struct drm_device *dev)
5780 {
5781 u16 gcfgc = 0;
5782
5783 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5784
5785 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5786 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5787 return 267000;
5788 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5789 return 333000;
5790 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5791 return 444000;
5792 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5793 return 200000;
5794 default:
5795 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5796 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5797 return 133000;
5798 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5799 return 167000;
5800 }
5801 }
5802
5803 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5804 {
5805 u16 gcfgc = 0;
5806
5807 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5808
5809 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5810 return 133000;
5811 else {
5812 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5813 case GC_DISPLAY_CLOCK_333_MHZ:
5814 return 333000;
5815 default:
5816 case GC_DISPLAY_CLOCK_190_200_MHZ:
5817 return 190000;
5818 }
5819 }
5820 }
5821
5822 static int i865_get_display_clock_speed(struct drm_device *dev)
5823 {
5824 return 266000;
5825 }
5826
5827 static int i855_get_display_clock_speed(struct drm_device *dev)
5828 {
5829 u16 hpllcc = 0;
5830 /* Assume that the hardware is in the high speed state. This
5831 * should be the default.
5832 */
5833 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5834 case GC_CLOCK_133_200:
5835 case GC_CLOCK_100_200:
5836 return 200000;
5837 case GC_CLOCK_166_250:
5838 return 250000;
5839 case GC_CLOCK_100_133:
5840 return 133000;
5841 }
5842
5843 /* Shouldn't happen */
5844 return 0;
5845 }
5846
5847 static int i830_get_display_clock_speed(struct drm_device *dev)
5848 {
5849 return 133000;
5850 }
5851
5852 static void
5853 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5854 {
5855 while (*num > DATA_LINK_M_N_MASK ||
5856 *den > DATA_LINK_M_N_MASK) {
5857 *num >>= 1;
5858 *den >>= 1;
5859 }
5860 }
5861
5862 static void compute_m_n(unsigned int m, unsigned int n,
5863 uint32_t *ret_m, uint32_t *ret_n)
5864 {
5865 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5866 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5867 intel_reduce_m_n_ratio(ret_m, ret_n);
5868 }
5869
5870 void
5871 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5872 int pixel_clock, int link_clock,
5873 struct intel_link_m_n *m_n)
5874 {
5875 m_n->tu = 64;
5876
5877 compute_m_n(bits_per_pixel * pixel_clock,
5878 link_clock * nlanes * 8,
5879 &m_n->gmch_m, &m_n->gmch_n);
5880
5881 compute_m_n(pixel_clock, link_clock,
5882 &m_n->link_m, &m_n->link_n);
5883 }
5884
5885 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5886 {
5887 if (i915.panel_use_ssc >= 0)
5888 return i915.panel_use_ssc != 0;
5889 return dev_priv->vbt.lvds_use_ssc
5890 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5891 }
5892
5893 static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5894 {
5895 struct drm_device *dev = crtc->base.dev;
5896 struct drm_i915_private *dev_priv = dev->dev_private;
5897 int refclk;
5898
5899 if (IS_VALLEYVIEW(dev)) {
5900 refclk = 100000;
5901 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5902 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5903 refclk = dev_priv->vbt.lvds_ssc_freq;
5904 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5905 } else if (!IS_GEN2(dev)) {
5906 refclk = 96000;
5907 } else {
5908 refclk = 48000;
5909 }
5910
5911 return refclk;
5912 }
5913
5914 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5915 {
5916 return (1 << dpll->n) << 16 | dpll->m2;
5917 }
5918
5919 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5920 {
5921 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5922 }
5923
5924 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5925 struct intel_crtc_state *crtc_state,
5926 intel_clock_t *reduced_clock)
5927 {
5928 struct drm_device *dev = crtc->base.dev;
5929 u32 fp, fp2 = 0;
5930
5931 if (IS_PINEVIEW(dev)) {
5932 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
5933 if (reduced_clock)
5934 fp2 = pnv_dpll_compute_fp(reduced_clock);
5935 } else {
5936 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
5937 if (reduced_clock)
5938 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5939 }
5940
5941 crtc_state->dpll_hw_state.fp0 = fp;
5942
5943 crtc->lowfreq_avail = false;
5944 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5945 reduced_clock && i915.powersave) {
5946 crtc_state->dpll_hw_state.fp1 = fp2;
5947 crtc->lowfreq_avail = true;
5948 } else {
5949 crtc_state->dpll_hw_state.fp1 = fp;
5950 }
5951 }
5952
5953 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5954 pipe)
5955 {
5956 u32 reg_val;
5957
5958 /*
5959 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5960 * and set it to a reasonable value instead.
5961 */
5962 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5963 reg_val &= 0xffffff00;
5964 reg_val |= 0x00000030;
5965 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5966
5967 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5968 reg_val &= 0x8cffffff;
5969 reg_val = 0x8c000000;
5970 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5971
5972 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5973 reg_val &= 0xffffff00;
5974 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5975
5976 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5977 reg_val &= 0x00ffffff;
5978 reg_val |= 0xb0000000;
5979 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5980 }
5981
5982 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5983 struct intel_link_m_n *m_n)
5984 {
5985 struct drm_device *dev = crtc->base.dev;
5986 struct drm_i915_private *dev_priv = dev->dev_private;
5987 int pipe = crtc->pipe;
5988
5989 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5990 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5991 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5992 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5993 }
5994
5995 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5996 struct intel_link_m_n *m_n,
5997 struct intel_link_m_n *m2_n2)
5998 {
5999 struct drm_device *dev = crtc->base.dev;
6000 struct drm_i915_private *dev_priv = dev->dev_private;
6001 int pipe = crtc->pipe;
6002 enum transcoder transcoder = crtc->config->cpu_transcoder;
6003
6004 if (INTEL_INFO(dev)->gen >= 5) {
6005 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6006 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6007 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6008 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6009 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6010 * for gen < 8) and if DRRS is supported (to make sure the
6011 * registers are not unnecessarily accessed).
6012 */
6013 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6014 crtc->config->has_drrs) {
6015 I915_WRITE(PIPE_DATA_M2(transcoder),
6016 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6017 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6018 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6019 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6020 }
6021 } else {
6022 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6023 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6024 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6025 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6026 }
6027 }
6028
6029 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6030 {
6031 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6032
6033 if (m_n == M1_N1) {
6034 dp_m_n = &crtc->config->dp_m_n;
6035 dp_m2_n2 = &crtc->config->dp_m2_n2;
6036 } else if (m_n == M2_N2) {
6037
6038 /*
6039 * M2_N2 registers are not supported. Hence m2_n2 divider value
6040 * needs to be programmed into M1_N1.
6041 */
6042 dp_m_n = &crtc->config->dp_m2_n2;
6043 } else {
6044 DRM_ERROR("Unsupported divider value\n");
6045 return;
6046 }
6047
6048 if (crtc->config->has_pch_encoder)
6049 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6050 else
6051 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6052 }
6053
6054 static void vlv_update_pll(struct intel_crtc *crtc,
6055 struct intel_crtc_state *pipe_config)
6056 {
6057 u32 dpll, dpll_md;
6058
6059 /*
6060 * Enable DPIO clock input. We should never disable the reference
6061 * clock for pipe B, since VGA hotplug / manual detection depends
6062 * on it.
6063 */
6064 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
6065 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
6066 /* We should never disable this, set it here for state tracking */
6067 if (crtc->pipe == PIPE_B)
6068 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6069 dpll |= DPLL_VCO_ENABLE;
6070 pipe_config->dpll_hw_state.dpll = dpll;
6071
6072 dpll_md = (pipe_config->pixel_multiplier - 1)
6073 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6074 pipe_config->dpll_hw_state.dpll_md = dpll_md;
6075 }
6076
6077 static void vlv_prepare_pll(struct intel_crtc *crtc,
6078 const struct intel_crtc_state *pipe_config)
6079 {
6080 struct drm_device *dev = crtc->base.dev;
6081 struct drm_i915_private *dev_priv = dev->dev_private;
6082 int pipe = crtc->pipe;
6083 u32 mdiv;
6084 u32 bestn, bestm1, bestm2, bestp1, bestp2;
6085 u32 coreclk, reg_val;
6086
6087 mutex_lock(&dev_priv->dpio_lock);
6088
6089 bestn = pipe_config->dpll.n;
6090 bestm1 = pipe_config->dpll.m1;
6091 bestm2 = pipe_config->dpll.m2;
6092 bestp1 = pipe_config->dpll.p1;
6093 bestp2 = pipe_config->dpll.p2;
6094
6095 /* See eDP HDMI DPIO driver vbios notes doc */
6096
6097 /* PLL B needs special handling */
6098 if (pipe == PIPE_B)
6099 vlv_pllb_recal_opamp(dev_priv, pipe);
6100
6101 /* Set up Tx target for periodic Rcomp update */
6102 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6103
6104 /* Disable target IRef on PLL */
6105 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6106 reg_val &= 0x00ffffff;
6107 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6108
6109 /* Disable fast lock */
6110 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6111
6112 /* Set idtafcrecal before PLL is enabled */
6113 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6114 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6115 mdiv |= ((bestn << DPIO_N_SHIFT));
6116 mdiv |= (1 << DPIO_K_SHIFT);
6117
6118 /*
6119 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6120 * but we don't support that).
6121 * Note: don't use the DAC post divider as it seems unstable.
6122 */
6123 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6124 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6125
6126 mdiv |= DPIO_ENABLE_CALIBRATION;
6127 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6128
6129 /* Set HBR and RBR LPF coefficients */
6130 if (pipe_config->port_clock == 162000 ||
6131 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
6132 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
6133 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6134 0x009f0003);
6135 else
6136 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6137 0x00d0000f);
6138
6139 if (pipe_config->has_dp_encoder) {
6140 /* Use SSC source */
6141 if (pipe == PIPE_A)
6142 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6143 0x0df40000);
6144 else
6145 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6146 0x0df70000);
6147 } else { /* HDMI or VGA */
6148 /* Use bend source */
6149 if (pipe == PIPE_A)
6150 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6151 0x0df70000);
6152 else
6153 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6154 0x0df40000);
6155 }
6156
6157 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6158 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6159 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6160 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
6161 coreclk |= 0x01000000;
6162 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6163
6164 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6165 mutex_unlock(&dev_priv->dpio_lock);
6166 }
6167
6168 static void chv_update_pll(struct intel_crtc *crtc,
6169 struct intel_crtc_state *pipe_config)
6170 {
6171 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
6172 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6173 DPLL_VCO_ENABLE;
6174 if (crtc->pipe != PIPE_A)
6175 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6176
6177 pipe_config->dpll_hw_state.dpll_md =
6178 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6179 }
6180
6181 static void chv_prepare_pll(struct intel_crtc *crtc,
6182 const struct intel_crtc_state *pipe_config)
6183 {
6184 struct drm_device *dev = crtc->base.dev;
6185 struct drm_i915_private *dev_priv = dev->dev_private;
6186 int pipe = crtc->pipe;
6187 int dpll_reg = DPLL(crtc->pipe);
6188 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6189 u32 loopfilter, tribuf_calcntr;
6190 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6191 u32 dpio_val;
6192 int vco;
6193
6194 bestn = pipe_config->dpll.n;
6195 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6196 bestm1 = pipe_config->dpll.m1;
6197 bestm2 = pipe_config->dpll.m2 >> 22;
6198 bestp1 = pipe_config->dpll.p1;
6199 bestp2 = pipe_config->dpll.p2;
6200 vco = pipe_config->dpll.vco;
6201 dpio_val = 0;
6202 loopfilter = 0;
6203
6204 /*
6205 * Enable Refclk and SSC
6206 */
6207 I915_WRITE(dpll_reg,
6208 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6209
6210 mutex_lock(&dev_priv->dpio_lock);
6211
6212 /* p1 and p2 divider */
6213 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6214 5 << DPIO_CHV_S1_DIV_SHIFT |
6215 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6216 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6217 1 << DPIO_CHV_K_DIV_SHIFT);
6218
6219 /* Feedback post-divider - m2 */
6220 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6221
6222 /* Feedback refclk divider - n and m1 */
6223 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6224 DPIO_CHV_M1_DIV_BY_2 |
6225 1 << DPIO_CHV_N_DIV_SHIFT);
6226
6227 /* M2 fraction division */
6228 if (bestm2_frac)
6229 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6230
6231 /* M2 fraction division enable */
6232 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6233 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6234 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6235 if (bestm2_frac)
6236 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6237 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
6238
6239 /* Program digital lock detect threshold */
6240 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6241 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6242 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6243 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6244 if (!bestm2_frac)
6245 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6246 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6247
6248 /* Loop filter */
6249 if (vco == 5400000) {
6250 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6251 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6252 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6253 tribuf_calcntr = 0x9;
6254 } else if (vco <= 6200000) {
6255 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6256 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6257 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6258 tribuf_calcntr = 0x9;
6259 } else if (vco <= 6480000) {
6260 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6261 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6262 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6263 tribuf_calcntr = 0x8;
6264 } else {
6265 /* Not supported. Apply the same limits as in the max case */
6266 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6267 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6268 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6269 tribuf_calcntr = 0;
6270 }
6271 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6272
6273 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(pipe));
6274 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6275 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6276 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6277
6278 /* AFC Recal */
6279 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6280 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6281 DPIO_AFC_RECAL);
6282
6283 mutex_unlock(&dev_priv->dpio_lock);
6284 }
6285
6286 /**
6287 * vlv_force_pll_on - forcibly enable just the PLL
6288 * @dev_priv: i915 private structure
6289 * @pipe: pipe PLL to enable
6290 * @dpll: PLL configuration
6291 *
6292 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6293 * in cases where we need the PLL enabled even when @pipe is not going to
6294 * be enabled.
6295 */
6296 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6297 const struct dpll *dpll)
6298 {
6299 struct intel_crtc *crtc =
6300 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6301 struct intel_crtc_state pipe_config = {
6302 .pixel_multiplier = 1,
6303 .dpll = *dpll,
6304 };
6305
6306 if (IS_CHERRYVIEW(dev)) {
6307 chv_update_pll(crtc, &pipe_config);
6308 chv_prepare_pll(crtc, &pipe_config);
6309 chv_enable_pll(crtc, &pipe_config);
6310 } else {
6311 vlv_update_pll(crtc, &pipe_config);
6312 vlv_prepare_pll(crtc, &pipe_config);
6313 vlv_enable_pll(crtc, &pipe_config);
6314 }
6315 }
6316
6317 /**
6318 * vlv_force_pll_off - forcibly disable just the PLL
6319 * @dev_priv: i915 private structure
6320 * @pipe: pipe PLL to disable
6321 *
6322 * Disable the PLL for @pipe. To be used in cases where we need
6323 * the PLL enabled even when @pipe is not going to be enabled.
6324 */
6325 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6326 {
6327 if (IS_CHERRYVIEW(dev))
6328 chv_disable_pll(to_i915(dev), pipe);
6329 else
6330 vlv_disable_pll(to_i915(dev), pipe);
6331 }
6332
6333 static void i9xx_update_pll(struct intel_crtc *crtc,
6334 struct intel_crtc_state *crtc_state,
6335 intel_clock_t *reduced_clock,
6336 int num_connectors)
6337 {
6338 struct drm_device *dev = crtc->base.dev;
6339 struct drm_i915_private *dev_priv = dev->dev_private;
6340 u32 dpll;
6341 bool is_sdvo;
6342 struct dpll *clock = &crtc_state->dpll;
6343
6344 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6345
6346 is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6347 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
6348
6349 dpll = DPLL_VGA_MODE_DIS;
6350
6351 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
6352 dpll |= DPLLB_MODE_LVDS;
6353 else
6354 dpll |= DPLLB_MODE_DAC_SERIAL;
6355
6356 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6357 dpll |= (crtc_state->pixel_multiplier - 1)
6358 << SDVO_MULTIPLIER_SHIFT_HIRES;
6359 }
6360
6361 if (is_sdvo)
6362 dpll |= DPLL_SDVO_HIGH_SPEED;
6363
6364 if (crtc_state->has_dp_encoder)
6365 dpll |= DPLL_SDVO_HIGH_SPEED;
6366
6367 /* compute bitmask from p1 value */
6368 if (IS_PINEVIEW(dev))
6369 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6370 else {
6371 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6372 if (IS_G4X(dev) && reduced_clock)
6373 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6374 }
6375 switch (clock->p2) {
6376 case 5:
6377 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6378 break;
6379 case 7:
6380 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6381 break;
6382 case 10:
6383 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6384 break;
6385 case 14:
6386 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6387 break;
6388 }
6389 if (INTEL_INFO(dev)->gen >= 4)
6390 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6391
6392 if (crtc_state->sdvo_tv_clock)
6393 dpll |= PLL_REF_INPUT_TVCLKINBC;
6394 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6395 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6396 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6397 else
6398 dpll |= PLL_REF_INPUT_DREFCLK;
6399
6400 dpll |= DPLL_VCO_ENABLE;
6401 crtc_state->dpll_hw_state.dpll = dpll;
6402
6403 if (INTEL_INFO(dev)->gen >= 4) {
6404 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6405 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6406 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6407 }
6408 }
6409
6410 static void i8xx_update_pll(struct intel_crtc *crtc,
6411 struct intel_crtc_state *crtc_state,
6412 intel_clock_t *reduced_clock,
6413 int num_connectors)
6414 {
6415 struct drm_device *dev = crtc->base.dev;
6416 struct drm_i915_private *dev_priv = dev->dev_private;
6417 u32 dpll;
6418 struct dpll *clock = &crtc_state->dpll;
6419
6420 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6421
6422 dpll = DPLL_VGA_MODE_DIS;
6423
6424 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
6425 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6426 } else {
6427 if (clock->p1 == 2)
6428 dpll |= PLL_P1_DIVIDE_BY_TWO;
6429 else
6430 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6431 if (clock->p2 == 4)
6432 dpll |= PLL_P2_DIVIDE_BY_4;
6433 }
6434
6435 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
6436 dpll |= DPLL_DVO_2X_MODE;
6437
6438 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6439 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6440 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6441 else
6442 dpll |= PLL_REF_INPUT_DREFCLK;
6443
6444 dpll |= DPLL_VCO_ENABLE;
6445 crtc_state->dpll_hw_state.dpll = dpll;
6446 }
6447
6448 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6449 {
6450 struct drm_device *dev = intel_crtc->base.dev;
6451 struct drm_i915_private *dev_priv = dev->dev_private;
6452 enum pipe pipe = intel_crtc->pipe;
6453 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6454 struct drm_display_mode *adjusted_mode =
6455 &intel_crtc->config->base.adjusted_mode;
6456 uint32_t crtc_vtotal, crtc_vblank_end;
6457 int vsyncshift = 0;
6458
6459 /* We need to be careful not to changed the adjusted mode, for otherwise
6460 * the hw state checker will get angry at the mismatch. */
6461 crtc_vtotal = adjusted_mode->crtc_vtotal;
6462 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6463
6464 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6465 /* the chip adds 2 halflines automatically */
6466 crtc_vtotal -= 1;
6467 crtc_vblank_end -= 1;
6468
6469 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6470 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6471 else
6472 vsyncshift = adjusted_mode->crtc_hsync_start -
6473 adjusted_mode->crtc_htotal / 2;
6474 if (vsyncshift < 0)
6475 vsyncshift += adjusted_mode->crtc_htotal;
6476 }
6477
6478 if (INTEL_INFO(dev)->gen > 3)
6479 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6480
6481 I915_WRITE(HTOTAL(cpu_transcoder),
6482 (adjusted_mode->crtc_hdisplay - 1) |
6483 ((adjusted_mode->crtc_htotal - 1) << 16));
6484 I915_WRITE(HBLANK(cpu_transcoder),
6485 (adjusted_mode->crtc_hblank_start - 1) |
6486 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6487 I915_WRITE(HSYNC(cpu_transcoder),
6488 (adjusted_mode->crtc_hsync_start - 1) |
6489 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6490
6491 I915_WRITE(VTOTAL(cpu_transcoder),
6492 (adjusted_mode->crtc_vdisplay - 1) |
6493 ((crtc_vtotal - 1) << 16));
6494 I915_WRITE(VBLANK(cpu_transcoder),
6495 (adjusted_mode->crtc_vblank_start - 1) |
6496 ((crtc_vblank_end - 1) << 16));
6497 I915_WRITE(VSYNC(cpu_transcoder),
6498 (adjusted_mode->crtc_vsync_start - 1) |
6499 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6500
6501 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6502 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6503 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6504 * bits. */
6505 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6506 (pipe == PIPE_B || pipe == PIPE_C))
6507 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6508
6509 /* pipesrc controls the size that is scaled from, which should
6510 * always be the user's requested size.
6511 */
6512 I915_WRITE(PIPESRC(pipe),
6513 ((intel_crtc->config->pipe_src_w - 1) << 16) |
6514 (intel_crtc->config->pipe_src_h - 1));
6515 }
6516
6517 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6518 struct intel_crtc_state *pipe_config)
6519 {
6520 struct drm_device *dev = crtc->base.dev;
6521 struct drm_i915_private *dev_priv = dev->dev_private;
6522 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6523 uint32_t tmp;
6524
6525 tmp = I915_READ(HTOTAL(cpu_transcoder));
6526 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6527 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6528 tmp = I915_READ(HBLANK(cpu_transcoder));
6529 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6530 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6531 tmp = I915_READ(HSYNC(cpu_transcoder));
6532 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6533 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6534
6535 tmp = I915_READ(VTOTAL(cpu_transcoder));
6536 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6537 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6538 tmp = I915_READ(VBLANK(cpu_transcoder));
6539 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6540 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6541 tmp = I915_READ(VSYNC(cpu_transcoder));
6542 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6543 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6544
6545 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6546 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6547 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6548 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
6549 }
6550
6551 tmp = I915_READ(PIPESRC(crtc->pipe));
6552 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6553 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6554
6555 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
6556 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
6557 }
6558
6559 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6560 struct intel_crtc_state *pipe_config)
6561 {
6562 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
6563 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
6564 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
6565 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
6566
6567 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
6568 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
6569 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
6570 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
6571
6572 mode->flags = pipe_config->base.adjusted_mode.flags;
6573
6574 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
6575 mode->flags |= pipe_config->base.adjusted_mode.flags;
6576 }
6577
6578 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6579 {
6580 struct drm_device *dev = intel_crtc->base.dev;
6581 struct drm_i915_private *dev_priv = dev->dev_private;
6582 uint32_t pipeconf;
6583
6584 pipeconf = 0;
6585
6586 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6587 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6588 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6589
6590 if (intel_crtc->config->double_wide)
6591 pipeconf |= PIPECONF_DOUBLE_WIDE;
6592
6593 /* only g4x and later have fancy bpc/dither controls */
6594 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6595 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6596 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
6597 pipeconf |= PIPECONF_DITHER_EN |
6598 PIPECONF_DITHER_TYPE_SP;
6599
6600 switch (intel_crtc->config->pipe_bpp) {
6601 case 18:
6602 pipeconf |= PIPECONF_6BPC;
6603 break;
6604 case 24:
6605 pipeconf |= PIPECONF_8BPC;
6606 break;
6607 case 30:
6608 pipeconf |= PIPECONF_10BPC;
6609 break;
6610 default:
6611 /* Case prevented by intel_choose_pipe_bpp_dither. */
6612 BUG();
6613 }
6614 }
6615
6616 if (HAS_PIPE_CXSR(dev)) {
6617 if (intel_crtc->lowfreq_avail) {
6618 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6619 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6620 } else {
6621 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6622 }
6623 }
6624
6625 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6626 if (INTEL_INFO(dev)->gen < 4 ||
6627 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6628 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6629 else
6630 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6631 } else
6632 pipeconf |= PIPECONF_PROGRESSIVE;
6633
6634 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
6635 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6636
6637 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6638 POSTING_READ(PIPECONF(intel_crtc->pipe));
6639 }
6640
6641 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
6642 struct intel_crtc_state *crtc_state)
6643 {
6644 struct drm_device *dev = crtc->base.dev;
6645 struct drm_i915_private *dev_priv = dev->dev_private;
6646 int refclk, num_connectors = 0;
6647 intel_clock_t clock, reduced_clock;
6648 bool ok, has_reduced_clock = false;
6649 bool is_lvds = false, is_dsi = false;
6650 struct intel_encoder *encoder;
6651 const intel_limit_t *limit;
6652
6653 for_each_intel_encoder(dev, encoder) {
6654 if (encoder->new_crtc != crtc)
6655 continue;
6656
6657 switch (encoder->type) {
6658 case INTEL_OUTPUT_LVDS:
6659 is_lvds = true;
6660 break;
6661 case INTEL_OUTPUT_DSI:
6662 is_dsi = true;
6663 break;
6664 default:
6665 break;
6666 }
6667
6668 num_connectors++;
6669 }
6670
6671 if (is_dsi)
6672 return 0;
6673
6674 if (!crtc_state->clock_set) {
6675 refclk = i9xx_get_refclk(crtc, num_connectors);
6676
6677 /*
6678 * Returns a set of divisors for the desired target clock with
6679 * the given refclk, or FALSE. The returned values represent
6680 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6681 * 2) / p1 / p2.
6682 */
6683 limit = intel_limit(crtc, refclk);
6684 ok = dev_priv->display.find_dpll(limit, crtc,
6685 crtc_state->port_clock,
6686 refclk, NULL, &clock);
6687 if (!ok) {
6688 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6689 return -EINVAL;
6690 }
6691
6692 if (is_lvds && dev_priv->lvds_downclock_avail) {
6693 /*
6694 * Ensure we match the reduced clock's P to the target
6695 * clock. If the clocks don't match, we can't switch
6696 * the display clock by using the FP0/FP1. In such case
6697 * we will disable the LVDS downclock feature.
6698 */
6699 has_reduced_clock =
6700 dev_priv->display.find_dpll(limit, crtc,
6701 dev_priv->lvds_downclock,
6702 refclk, &clock,
6703 &reduced_clock);
6704 }
6705 /* Compat-code for transition, will disappear. */
6706 crtc_state->dpll.n = clock.n;
6707 crtc_state->dpll.m1 = clock.m1;
6708 crtc_state->dpll.m2 = clock.m2;
6709 crtc_state->dpll.p1 = clock.p1;
6710 crtc_state->dpll.p2 = clock.p2;
6711 }
6712
6713 if (IS_GEN2(dev)) {
6714 i8xx_update_pll(crtc, crtc_state,
6715 has_reduced_clock ? &reduced_clock : NULL,
6716 num_connectors);
6717 } else if (IS_CHERRYVIEW(dev)) {
6718 chv_update_pll(crtc, crtc_state);
6719 } else if (IS_VALLEYVIEW(dev)) {
6720 vlv_update_pll(crtc, crtc_state);
6721 } else {
6722 i9xx_update_pll(crtc, crtc_state,
6723 has_reduced_clock ? &reduced_clock : NULL,
6724 num_connectors);
6725 }
6726
6727 return 0;
6728 }
6729
6730 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6731 struct intel_crtc_state *pipe_config)
6732 {
6733 struct drm_device *dev = crtc->base.dev;
6734 struct drm_i915_private *dev_priv = dev->dev_private;
6735 uint32_t tmp;
6736
6737 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6738 return;
6739
6740 tmp = I915_READ(PFIT_CONTROL);
6741 if (!(tmp & PFIT_ENABLE))
6742 return;
6743
6744 /* Check whether the pfit is attached to our pipe. */
6745 if (INTEL_INFO(dev)->gen < 4) {
6746 if (crtc->pipe != PIPE_B)
6747 return;
6748 } else {
6749 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6750 return;
6751 }
6752
6753 pipe_config->gmch_pfit.control = tmp;
6754 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6755 if (INTEL_INFO(dev)->gen < 5)
6756 pipe_config->gmch_pfit.lvds_border_bits =
6757 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6758 }
6759
6760 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6761 struct intel_crtc_state *pipe_config)
6762 {
6763 struct drm_device *dev = crtc->base.dev;
6764 struct drm_i915_private *dev_priv = dev->dev_private;
6765 int pipe = pipe_config->cpu_transcoder;
6766 intel_clock_t clock;
6767 u32 mdiv;
6768 int refclk = 100000;
6769
6770 /* In case of MIPI DPLL will not even be used */
6771 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6772 return;
6773
6774 mutex_lock(&dev_priv->dpio_lock);
6775 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6776 mutex_unlock(&dev_priv->dpio_lock);
6777
6778 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6779 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6780 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6781 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6782 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6783
6784 vlv_clock(refclk, &clock);
6785
6786 /* clock.dot is the fast clock */
6787 pipe_config->port_clock = clock.dot / 5;
6788 }
6789
6790 static void
6791 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
6792 struct intel_initial_plane_config *plane_config)
6793 {
6794 struct drm_device *dev = crtc->base.dev;
6795 struct drm_i915_private *dev_priv = dev->dev_private;
6796 u32 val, base, offset;
6797 int pipe = crtc->pipe, plane = crtc->plane;
6798 int fourcc, pixel_format;
6799 int aligned_height;
6800 struct drm_framebuffer *fb;
6801 struct intel_framebuffer *intel_fb;
6802
6803 val = I915_READ(DSPCNTR(plane));
6804 if (!(val & DISPLAY_PLANE_ENABLE))
6805 return;
6806
6807 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6808 if (!intel_fb) {
6809 DRM_DEBUG_KMS("failed to alloc fb\n");
6810 return;
6811 }
6812
6813 fb = &intel_fb->base;
6814
6815 if (INTEL_INFO(dev)->gen >= 4) {
6816 if (val & DISPPLANE_TILED) {
6817 plane_config->tiling = I915_TILING_X;
6818 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
6819 }
6820 }
6821
6822 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6823 fourcc = i9xx_format_to_fourcc(pixel_format);
6824 fb->pixel_format = fourcc;
6825 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
6826
6827 if (INTEL_INFO(dev)->gen >= 4) {
6828 if (plane_config->tiling)
6829 offset = I915_READ(DSPTILEOFF(plane));
6830 else
6831 offset = I915_READ(DSPLINOFF(plane));
6832 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6833 } else {
6834 base = I915_READ(DSPADDR(plane));
6835 }
6836 plane_config->base = base;
6837
6838 val = I915_READ(PIPESRC(pipe));
6839 fb->width = ((val >> 16) & 0xfff) + 1;
6840 fb->height = ((val >> 0) & 0xfff) + 1;
6841
6842 val = I915_READ(DSPSTRIDE(pipe));
6843 fb->pitches[0] = val & 0xffffffc0;
6844
6845 aligned_height = intel_fb_align_height(dev, fb->height,
6846 fb->pixel_format,
6847 fb->modifier[0]);
6848
6849 plane_config->size = fb->pitches[0] * aligned_height;
6850
6851 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6852 pipe_name(pipe), plane, fb->width, fb->height,
6853 fb->bits_per_pixel, base, fb->pitches[0],
6854 plane_config->size);
6855
6856 plane_config->fb = intel_fb;
6857 }
6858
6859 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6860 struct intel_crtc_state *pipe_config)
6861 {
6862 struct drm_device *dev = crtc->base.dev;
6863 struct drm_i915_private *dev_priv = dev->dev_private;
6864 int pipe = pipe_config->cpu_transcoder;
6865 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6866 intel_clock_t clock;
6867 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6868 int refclk = 100000;
6869
6870 mutex_lock(&dev_priv->dpio_lock);
6871 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6872 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6873 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6874 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6875 mutex_unlock(&dev_priv->dpio_lock);
6876
6877 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6878 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6879 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6880 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6881 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6882
6883 chv_clock(refclk, &clock);
6884
6885 /* clock.dot is the fast clock */
6886 pipe_config->port_clock = clock.dot / 5;
6887 }
6888
6889 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6890 struct intel_crtc_state *pipe_config)
6891 {
6892 struct drm_device *dev = crtc->base.dev;
6893 struct drm_i915_private *dev_priv = dev->dev_private;
6894 uint32_t tmp;
6895
6896 if (!intel_display_power_is_enabled(dev_priv,
6897 POWER_DOMAIN_PIPE(crtc->pipe)))
6898 return false;
6899
6900 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6901 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6902
6903 tmp = I915_READ(PIPECONF(crtc->pipe));
6904 if (!(tmp & PIPECONF_ENABLE))
6905 return false;
6906
6907 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6908 switch (tmp & PIPECONF_BPC_MASK) {
6909 case PIPECONF_6BPC:
6910 pipe_config->pipe_bpp = 18;
6911 break;
6912 case PIPECONF_8BPC:
6913 pipe_config->pipe_bpp = 24;
6914 break;
6915 case PIPECONF_10BPC:
6916 pipe_config->pipe_bpp = 30;
6917 break;
6918 default:
6919 break;
6920 }
6921 }
6922
6923 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6924 pipe_config->limited_color_range = true;
6925
6926 if (INTEL_INFO(dev)->gen < 4)
6927 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6928
6929 intel_get_pipe_timings(crtc, pipe_config);
6930
6931 i9xx_get_pfit_config(crtc, pipe_config);
6932
6933 if (INTEL_INFO(dev)->gen >= 4) {
6934 tmp = I915_READ(DPLL_MD(crtc->pipe));
6935 pipe_config->pixel_multiplier =
6936 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6937 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6938 pipe_config->dpll_hw_state.dpll_md = tmp;
6939 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6940 tmp = I915_READ(DPLL(crtc->pipe));
6941 pipe_config->pixel_multiplier =
6942 ((tmp & SDVO_MULTIPLIER_MASK)
6943 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6944 } else {
6945 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6946 * port and will be fixed up in the encoder->get_config
6947 * function. */
6948 pipe_config->pixel_multiplier = 1;
6949 }
6950 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6951 if (!IS_VALLEYVIEW(dev)) {
6952 /*
6953 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6954 * on 830. Filter it out here so that we don't
6955 * report errors due to that.
6956 */
6957 if (IS_I830(dev))
6958 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6959
6960 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6961 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6962 } else {
6963 /* Mask out read-only status bits. */
6964 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6965 DPLL_PORTC_READY_MASK |
6966 DPLL_PORTB_READY_MASK);
6967 }
6968
6969 if (IS_CHERRYVIEW(dev))
6970 chv_crtc_clock_get(crtc, pipe_config);
6971 else if (IS_VALLEYVIEW(dev))
6972 vlv_crtc_clock_get(crtc, pipe_config);
6973 else
6974 i9xx_crtc_clock_get(crtc, pipe_config);
6975
6976 return true;
6977 }
6978
6979 static void ironlake_init_pch_refclk(struct drm_device *dev)
6980 {
6981 struct drm_i915_private *dev_priv = dev->dev_private;
6982 struct intel_encoder *encoder;
6983 u32 val, final;
6984 bool has_lvds = false;
6985 bool has_cpu_edp = false;
6986 bool has_panel = false;
6987 bool has_ck505 = false;
6988 bool can_ssc = false;
6989
6990 /* We need to take the global config into account */
6991 for_each_intel_encoder(dev, encoder) {
6992 switch (encoder->type) {
6993 case INTEL_OUTPUT_LVDS:
6994 has_panel = true;
6995 has_lvds = true;
6996 break;
6997 case INTEL_OUTPUT_EDP:
6998 has_panel = true;
6999 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
7000 has_cpu_edp = true;
7001 break;
7002 default:
7003 break;
7004 }
7005 }
7006
7007 if (HAS_PCH_IBX(dev)) {
7008 has_ck505 = dev_priv->vbt.display_clock_mode;
7009 can_ssc = has_ck505;
7010 } else {
7011 has_ck505 = false;
7012 can_ssc = true;
7013 }
7014
7015 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
7016 has_panel, has_lvds, has_ck505);
7017
7018 /* Ironlake: try to setup display ref clock before DPLL
7019 * enabling. This is only under driver's control after
7020 * PCH B stepping, previous chipset stepping should be
7021 * ignoring this setting.
7022 */
7023 val = I915_READ(PCH_DREF_CONTROL);
7024
7025 /* As we must carefully and slowly disable/enable each source in turn,
7026 * compute the final state we want first and check if we need to
7027 * make any changes at all.
7028 */
7029 final = val;
7030 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7031 if (has_ck505)
7032 final |= DREF_NONSPREAD_CK505_ENABLE;
7033 else
7034 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7035
7036 final &= ~DREF_SSC_SOURCE_MASK;
7037 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7038 final &= ~DREF_SSC1_ENABLE;
7039
7040 if (has_panel) {
7041 final |= DREF_SSC_SOURCE_ENABLE;
7042
7043 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7044 final |= DREF_SSC1_ENABLE;
7045
7046 if (has_cpu_edp) {
7047 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7048 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7049 else
7050 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7051 } else
7052 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7053 } else {
7054 final |= DREF_SSC_SOURCE_DISABLE;
7055 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7056 }
7057
7058 if (final == val)
7059 return;
7060
7061 /* Always enable nonspread source */
7062 val &= ~DREF_NONSPREAD_SOURCE_MASK;
7063
7064 if (has_ck505)
7065 val |= DREF_NONSPREAD_CK505_ENABLE;
7066 else
7067 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7068
7069 if (has_panel) {
7070 val &= ~DREF_SSC_SOURCE_MASK;
7071 val |= DREF_SSC_SOURCE_ENABLE;
7072
7073 /* SSC must be turned on before enabling the CPU output */
7074 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7075 DRM_DEBUG_KMS("Using SSC on panel\n");
7076 val |= DREF_SSC1_ENABLE;
7077 } else
7078 val &= ~DREF_SSC1_ENABLE;
7079
7080 /* Get SSC going before enabling the outputs */
7081 I915_WRITE(PCH_DREF_CONTROL, val);
7082 POSTING_READ(PCH_DREF_CONTROL);
7083 udelay(200);
7084
7085 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7086
7087 /* Enable CPU source on CPU attached eDP */
7088 if (has_cpu_edp) {
7089 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7090 DRM_DEBUG_KMS("Using SSC on eDP\n");
7091 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7092 } else
7093 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7094 } else
7095 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7096
7097 I915_WRITE(PCH_DREF_CONTROL, val);
7098 POSTING_READ(PCH_DREF_CONTROL);
7099 udelay(200);
7100 } else {
7101 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7102
7103 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7104
7105 /* Turn off CPU output */
7106 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7107
7108 I915_WRITE(PCH_DREF_CONTROL, val);
7109 POSTING_READ(PCH_DREF_CONTROL);
7110 udelay(200);
7111
7112 /* Turn off the SSC source */
7113 val &= ~DREF_SSC_SOURCE_MASK;
7114 val |= DREF_SSC_SOURCE_DISABLE;
7115
7116 /* Turn off SSC1 */
7117 val &= ~DREF_SSC1_ENABLE;
7118
7119 I915_WRITE(PCH_DREF_CONTROL, val);
7120 POSTING_READ(PCH_DREF_CONTROL);
7121 udelay(200);
7122 }
7123
7124 BUG_ON(val != final);
7125 }
7126
7127 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7128 {
7129 uint32_t tmp;
7130
7131 tmp = I915_READ(SOUTH_CHICKEN2);
7132 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7133 I915_WRITE(SOUTH_CHICKEN2, tmp);
7134
7135 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
7136 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7137 DRM_ERROR("FDI mPHY reset assert timeout\n");
7138
7139 tmp = I915_READ(SOUTH_CHICKEN2);
7140 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7141 I915_WRITE(SOUTH_CHICKEN2, tmp);
7142
7143 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
7144 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7145 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7146 }
7147
7148 /* WaMPhyProgramming:hsw */
7149 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7150 {
7151 uint32_t tmp;
7152
7153 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7154 tmp &= ~(0xFF << 24);
7155 tmp |= (0x12 << 24);
7156 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7157
7158 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7159 tmp |= (1 << 11);
7160 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7161
7162 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7163 tmp |= (1 << 11);
7164 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7165
7166 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7167 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7168 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7169
7170 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7171 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7172 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7173
7174 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7175 tmp &= ~(7 << 13);
7176 tmp |= (5 << 13);
7177 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7178
7179 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7180 tmp &= ~(7 << 13);
7181 tmp |= (5 << 13);
7182 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7183
7184 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7185 tmp &= ~0xFF;
7186 tmp |= 0x1C;
7187 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7188
7189 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7190 tmp &= ~0xFF;
7191 tmp |= 0x1C;
7192 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7193
7194 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7195 tmp &= ~(0xFF << 16);
7196 tmp |= (0x1C << 16);
7197 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7198
7199 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7200 tmp &= ~(0xFF << 16);
7201 tmp |= (0x1C << 16);
7202 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7203
7204 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7205 tmp |= (1 << 27);
7206 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7207
7208 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7209 tmp |= (1 << 27);
7210 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7211
7212 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7213 tmp &= ~(0xF << 28);
7214 tmp |= (4 << 28);
7215 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7216
7217 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7218 tmp &= ~(0xF << 28);
7219 tmp |= (4 << 28);
7220 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7221 }
7222
7223 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7224 * Programming" based on the parameters passed:
7225 * - Sequence to enable CLKOUT_DP
7226 * - Sequence to enable CLKOUT_DP without spread
7227 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7228 */
7229 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
7230 bool with_fdi)
7231 {
7232 struct drm_i915_private *dev_priv = dev->dev_private;
7233 uint32_t reg, tmp;
7234
7235 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7236 with_spread = true;
7237 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
7238 with_fdi, "LP PCH doesn't have FDI\n"))
7239 with_fdi = false;
7240
7241 mutex_lock(&dev_priv->dpio_lock);
7242
7243 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7244 tmp &= ~SBI_SSCCTL_DISABLE;
7245 tmp |= SBI_SSCCTL_PATHALT;
7246 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7247
7248 udelay(24);
7249
7250 if (with_spread) {
7251 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7252 tmp &= ~SBI_SSCCTL_PATHALT;
7253 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7254
7255 if (with_fdi) {
7256 lpt_reset_fdi_mphy(dev_priv);
7257 lpt_program_fdi_mphy(dev_priv);
7258 }
7259 }
7260
7261 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7262 SBI_GEN0 : SBI_DBUFF0;
7263 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7264 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7265 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7266
7267 mutex_unlock(&dev_priv->dpio_lock);
7268 }
7269
7270 /* Sequence to disable CLKOUT_DP */
7271 static void lpt_disable_clkout_dp(struct drm_device *dev)
7272 {
7273 struct drm_i915_private *dev_priv = dev->dev_private;
7274 uint32_t reg, tmp;
7275
7276 mutex_lock(&dev_priv->dpio_lock);
7277
7278 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7279 SBI_GEN0 : SBI_DBUFF0;
7280 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7281 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7282 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7283
7284 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7285 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7286 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7287 tmp |= SBI_SSCCTL_PATHALT;
7288 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7289 udelay(32);
7290 }
7291 tmp |= SBI_SSCCTL_DISABLE;
7292 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7293 }
7294
7295 mutex_unlock(&dev_priv->dpio_lock);
7296 }
7297
7298 static void lpt_init_pch_refclk(struct drm_device *dev)
7299 {
7300 struct intel_encoder *encoder;
7301 bool has_vga = false;
7302
7303 for_each_intel_encoder(dev, encoder) {
7304 switch (encoder->type) {
7305 case INTEL_OUTPUT_ANALOG:
7306 has_vga = true;
7307 break;
7308 default:
7309 break;
7310 }
7311 }
7312
7313 if (has_vga)
7314 lpt_enable_clkout_dp(dev, true, true);
7315 else
7316 lpt_disable_clkout_dp(dev);
7317 }
7318
7319 /*
7320 * Initialize reference clocks when the driver loads
7321 */
7322 void intel_init_pch_refclk(struct drm_device *dev)
7323 {
7324 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7325 ironlake_init_pch_refclk(dev);
7326 else if (HAS_PCH_LPT(dev))
7327 lpt_init_pch_refclk(dev);
7328 }
7329
7330 static int ironlake_get_refclk(struct drm_crtc *crtc)
7331 {
7332 struct drm_device *dev = crtc->dev;
7333 struct drm_i915_private *dev_priv = dev->dev_private;
7334 struct intel_encoder *encoder;
7335 int num_connectors = 0;
7336 bool is_lvds = false;
7337
7338 for_each_intel_encoder(dev, encoder) {
7339 if (encoder->new_crtc != to_intel_crtc(crtc))
7340 continue;
7341
7342 switch (encoder->type) {
7343 case INTEL_OUTPUT_LVDS:
7344 is_lvds = true;
7345 break;
7346 default:
7347 break;
7348 }
7349 num_connectors++;
7350 }
7351
7352 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7353 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7354 dev_priv->vbt.lvds_ssc_freq);
7355 return dev_priv->vbt.lvds_ssc_freq;
7356 }
7357
7358 return 120000;
7359 }
7360
7361 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7362 {
7363 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7364 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7365 int pipe = intel_crtc->pipe;
7366 uint32_t val;
7367
7368 val = 0;
7369
7370 switch (intel_crtc->config->pipe_bpp) {
7371 case 18:
7372 val |= PIPECONF_6BPC;
7373 break;
7374 case 24:
7375 val |= PIPECONF_8BPC;
7376 break;
7377 case 30:
7378 val |= PIPECONF_10BPC;
7379 break;
7380 case 36:
7381 val |= PIPECONF_12BPC;
7382 break;
7383 default:
7384 /* Case prevented by intel_choose_pipe_bpp_dither. */
7385 BUG();
7386 }
7387
7388 if (intel_crtc->config->dither)
7389 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7390
7391 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7392 val |= PIPECONF_INTERLACED_ILK;
7393 else
7394 val |= PIPECONF_PROGRESSIVE;
7395
7396 if (intel_crtc->config->limited_color_range)
7397 val |= PIPECONF_COLOR_RANGE_SELECT;
7398
7399 I915_WRITE(PIPECONF(pipe), val);
7400 POSTING_READ(PIPECONF(pipe));
7401 }
7402
7403 /*
7404 * Set up the pipe CSC unit.
7405 *
7406 * Currently only full range RGB to limited range RGB conversion
7407 * is supported, but eventually this should handle various
7408 * RGB<->YCbCr scenarios as well.
7409 */
7410 static void intel_set_pipe_csc(struct drm_crtc *crtc)
7411 {
7412 struct drm_device *dev = crtc->dev;
7413 struct drm_i915_private *dev_priv = dev->dev_private;
7414 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7415 int pipe = intel_crtc->pipe;
7416 uint16_t coeff = 0x7800; /* 1.0 */
7417
7418 /*
7419 * TODO: Check what kind of values actually come out of the pipe
7420 * with these coeff/postoff values and adjust to get the best
7421 * accuracy. Perhaps we even need to take the bpc value into
7422 * consideration.
7423 */
7424
7425 if (intel_crtc->config->limited_color_range)
7426 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7427
7428 /*
7429 * GY/GU and RY/RU should be the other way around according
7430 * to BSpec, but reality doesn't agree. Just set them up in
7431 * a way that results in the correct picture.
7432 */
7433 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7434 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7435
7436 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7437 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7438
7439 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7440 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7441
7442 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7443 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7444 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7445
7446 if (INTEL_INFO(dev)->gen > 6) {
7447 uint16_t postoff = 0;
7448
7449 if (intel_crtc->config->limited_color_range)
7450 postoff = (16 * (1 << 12) / 255) & 0x1fff;
7451
7452 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7453 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7454 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7455
7456 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7457 } else {
7458 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7459
7460 if (intel_crtc->config->limited_color_range)
7461 mode |= CSC_BLACK_SCREEN_OFFSET;
7462
7463 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7464 }
7465 }
7466
7467 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7468 {
7469 struct drm_device *dev = crtc->dev;
7470 struct drm_i915_private *dev_priv = dev->dev_private;
7471 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7472 enum pipe pipe = intel_crtc->pipe;
7473 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7474 uint32_t val;
7475
7476 val = 0;
7477
7478 if (IS_HASWELL(dev) && intel_crtc->config->dither)
7479 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7480
7481 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7482 val |= PIPECONF_INTERLACED_ILK;
7483 else
7484 val |= PIPECONF_PROGRESSIVE;
7485
7486 I915_WRITE(PIPECONF(cpu_transcoder), val);
7487 POSTING_READ(PIPECONF(cpu_transcoder));
7488
7489 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7490 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7491
7492 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7493 val = 0;
7494
7495 switch (intel_crtc->config->pipe_bpp) {
7496 case 18:
7497 val |= PIPEMISC_DITHER_6_BPC;
7498 break;
7499 case 24:
7500 val |= PIPEMISC_DITHER_8_BPC;
7501 break;
7502 case 30:
7503 val |= PIPEMISC_DITHER_10_BPC;
7504 break;
7505 case 36:
7506 val |= PIPEMISC_DITHER_12_BPC;
7507 break;
7508 default:
7509 /* Case prevented by pipe_config_set_bpp. */
7510 BUG();
7511 }
7512
7513 if (intel_crtc->config->dither)
7514 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7515
7516 I915_WRITE(PIPEMISC(pipe), val);
7517 }
7518 }
7519
7520 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7521 struct intel_crtc_state *crtc_state,
7522 intel_clock_t *clock,
7523 bool *has_reduced_clock,
7524 intel_clock_t *reduced_clock)
7525 {
7526 struct drm_device *dev = crtc->dev;
7527 struct drm_i915_private *dev_priv = dev->dev_private;
7528 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7529 int refclk;
7530 const intel_limit_t *limit;
7531 bool ret, is_lvds = false;
7532
7533 is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
7534
7535 refclk = ironlake_get_refclk(crtc);
7536
7537 /*
7538 * Returns a set of divisors for the desired target clock with the given
7539 * refclk, or FALSE. The returned values represent the clock equation:
7540 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7541 */
7542 limit = intel_limit(intel_crtc, refclk);
7543 ret = dev_priv->display.find_dpll(limit, intel_crtc,
7544 crtc_state->port_clock,
7545 refclk, NULL, clock);
7546 if (!ret)
7547 return false;
7548
7549 if (is_lvds && dev_priv->lvds_downclock_avail) {
7550 /*
7551 * Ensure we match the reduced clock's P to the target clock.
7552 * If the clocks don't match, we can't switch the display clock
7553 * by using the FP0/FP1. In such case we will disable the LVDS
7554 * downclock feature.
7555 */
7556 *has_reduced_clock =
7557 dev_priv->display.find_dpll(limit, intel_crtc,
7558 dev_priv->lvds_downclock,
7559 refclk, clock,
7560 reduced_clock);
7561 }
7562
7563 return true;
7564 }
7565
7566 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7567 {
7568 /*
7569 * Account for spread spectrum to avoid
7570 * oversubscribing the link. Max center spread
7571 * is 2.5%; use 5% for safety's sake.
7572 */
7573 u32 bps = target_clock * bpp * 21 / 20;
7574 return DIV_ROUND_UP(bps, link_bw * 8);
7575 }
7576
7577 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7578 {
7579 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7580 }
7581
7582 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7583 struct intel_crtc_state *crtc_state,
7584 u32 *fp,
7585 intel_clock_t *reduced_clock, u32 *fp2)
7586 {
7587 struct drm_crtc *crtc = &intel_crtc->base;
7588 struct drm_device *dev = crtc->dev;
7589 struct drm_i915_private *dev_priv = dev->dev_private;
7590 struct intel_encoder *intel_encoder;
7591 uint32_t dpll;
7592 int factor, num_connectors = 0;
7593 bool is_lvds = false, is_sdvo = false;
7594
7595 for_each_intel_encoder(dev, intel_encoder) {
7596 if (intel_encoder->new_crtc != to_intel_crtc(crtc))
7597 continue;
7598
7599 switch (intel_encoder->type) {
7600 case INTEL_OUTPUT_LVDS:
7601 is_lvds = true;
7602 break;
7603 case INTEL_OUTPUT_SDVO:
7604 case INTEL_OUTPUT_HDMI:
7605 is_sdvo = true;
7606 break;
7607 default:
7608 break;
7609 }
7610
7611 num_connectors++;
7612 }
7613
7614 /* Enable autotuning of the PLL clock (if permissible) */
7615 factor = 21;
7616 if (is_lvds) {
7617 if ((intel_panel_use_ssc(dev_priv) &&
7618 dev_priv->vbt.lvds_ssc_freq == 100000) ||
7619 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7620 factor = 25;
7621 } else if (crtc_state->sdvo_tv_clock)
7622 factor = 20;
7623
7624 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7625 *fp |= FP_CB_TUNE;
7626
7627 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7628 *fp2 |= FP_CB_TUNE;
7629
7630 dpll = 0;
7631
7632 if (is_lvds)
7633 dpll |= DPLLB_MODE_LVDS;
7634 else
7635 dpll |= DPLLB_MODE_DAC_SERIAL;
7636
7637 dpll |= (crtc_state->pixel_multiplier - 1)
7638 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7639
7640 if (is_sdvo)
7641 dpll |= DPLL_SDVO_HIGH_SPEED;
7642 if (crtc_state->has_dp_encoder)
7643 dpll |= DPLL_SDVO_HIGH_SPEED;
7644
7645 /* compute bitmask from p1 value */
7646 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7647 /* also FPA1 */
7648 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7649
7650 switch (crtc_state->dpll.p2) {
7651 case 5:
7652 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7653 break;
7654 case 7:
7655 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7656 break;
7657 case 10:
7658 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7659 break;
7660 case 14:
7661 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7662 break;
7663 }
7664
7665 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7666 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7667 else
7668 dpll |= PLL_REF_INPUT_DREFCLK;
7669
7670 return dpll | DPLL_VCO_ENABLE;
7671 }
7672
7673 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
7674 struct intel_crtc_state *crtc_state)
7675 {
7676 struct drm_device *dev = crtc->base.dev;
7677 intel_clock_t clock, reduced_clock;
7678 u32 dpll = 0, fp = 0, fp2 = 0;
7679 bool ok, has_reduced_clock = false;
7680 bool is_lvds = false;
7681 struct intel_shared_dpll *pll;
7682
7683 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7684
7685 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7686 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7687
7688 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
7689 &has_reduced_clock, &reduced_clock);
7690 if (!ok && !crtc_state->clock_set) {
7691 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7692 return -EINVAL;
7693 }
7694 /* Compat-code for transition, will disappear. */
7695 if (!crtc_state->clock_set) {
7696 crtc_state->dpll.n = clock.n;
7697 crtc_state->dpll.m1 = clock.m1;
7698 crtc_state->dpll.m2 = clock.m2;
7699 crtc_state->dpll.p1 = clock.p1;
7700 crtc_state->dpll.p2 = clock.p2;
7701 }
7702
7703 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7704 if (crtc_state->has_pch_encoder) {
7705 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7706 if (has_reduced_clock)
7707 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7708
7709 dpll = ironlake_compute_dpll(crtc, crtc_state,
7710 &fp, &reduced_clock,
7711 has_reduced_clock ? &fp2 : NULL);
7712
7713 crtc_state->dpll_hw_state.dpll = dpll;
7714 crtc_state->dpll_hw_state.fp0 = fp;
7715 if (has_reduced_clock)
7716 crtc_state->dpll_hw_state.fp1 = fp2;
7717 else
7718 crtc_state->dpll_hw_state.fp1 = fp;
7719
7720 pll = intel_get_shared_dpll(crtc, crtc_state);
7721 if (pll == NULL) {
7722 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7723 pipe_name(crtc->pipe));
7724 return -EINVAL;
7725 }
7726 }
7727
7728 if (is_lvds && has_reduced_clock && i915.powersave)
7729 crtc->lowfreq_avail = true;
7730 else
7731 crtc->lowfreq_avail = false;
7732
7733 return 0;
7734 }
7735
7736 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7737 struct intel_link_m_n *m_n)
7738 {
7739 struct drm_device *dev = crtc->base.dev;
7740 struct drm_i915_private *dev_priv = dev->dev_private;
7741 enum pipe pipe = crtc->pipe;
7742
7743 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7744 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7745 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7746 & ~TU_SIZE_MASK;
7747 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7748 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7749 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7750 }
7751
7752 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7753 enum transcoder transcoder,
7754 struct intel_link_m_n *m_n,
7755 struct intel_link_m_n *m2_n2)
7756 {
7757 struct drm_device *dev = crtc->base.dev;
7758 struct drm_i915_private *dev_priv = dev->dev_private;
7759 enum pipe pipe = crtc->pipe;
7760
7761 if (INTEL_INFO(dev)->gen >= 5) {
7762 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7763 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7764 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7765 & ~TU_SIZE_MASK;
7766 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7767 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7768 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7769 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7770 * gen < 8) and if DRRS is supported (to make sure the
7771 * registers are not unnecessarily read).
7772 */
7773 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7774 crtc->config->has_drrs) {
7775 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7776 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7777 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7778 & ~TU_SIZE_MASK;
7779 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7780 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7781 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7782 }
7783 } else {
7784 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7785 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7786 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7787 & ~TU_SIZE_MASK;
7788 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7789 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7790 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7791 }
7792 }
7793
7794 void intel_dp_get_m_n(struct intel_crtc *crtc,
7795 struct intel_crtc_state *pipe_config)
7796 {
7797 if (pipe_config->has_pch_encoder)
7798 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7799 else
7800 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7801 &pipe_config->dp_m_n,
7802 &pipe_config->dp_m2_n2);
7803 }
7804
7805 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7806 struct intel_crtc_state *pipe_config)
7807 {
7808 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7809 &pipe_config->fdi_m_n, NULL);
7810 }
7811
7812 static void skylake_get_pfit_config(struct intel_crtc *crtc,
7813 struct intel_crtc_state *pipe_config)
7814 {
7815 struct drm_device *dev = crtc->base.dev;
7816 struct drm_i915_private *dev_priv = dev->dev_private;
7817 uint32_t tmp;
7818
7819 tmp = I915_READ(PS_CTL(crtc->pipe));
7820
7821 if (tmp & PS_ENABLE) {
7822 pipe_config->pch_pfit.enabled = true;
7823 pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe));
7824 pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe));
7825 }
7826 }
7827
7828 static void
7829 skylake_get_initial_plane_config(struct intel_crtc *crtc,
7830 struct intel_initial_plane_config *plane_config)
7831 {
7832 struct drm_device *dev = crtc->base.dev;
7833 struct drm_i915_private *dev_priv = dev->dev_private;
7834 u32 val, base, offset, stride_mult, tiling;
7835 int pipe = crtc->pipe;
7836 int fourcc, pixel_format;
7837 int aligned_height;
7838 struct drm_framebuffer *fb;
7839 struct intel_framebuffer *intel_fb;
7840
7841 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7842 if (!intel_fb) {
7843 DRM_DEBUG_KMS("failed to alloc fb\n");
7844 return;
7845 }
7846
7847 fb = &intel_fb->base;
7848
7849 val = I915_READ(PLANE_CTL(pipe, 0));
7850 if (!(val & PLANE_CTL_ENABLE))
7851 goto error;
7852
7853 pixel_format = val & PLANE_CTL_FORMAT_MASK;
7854 fourcc = skl_format_to_fourcc(pixel_format,
7855 val & PLANE_CTL_ORDER_RGBX,
7856 val & PLANE_CTL_ALPHA_MASK);
7857 fb->pixel_format = fourcc;
7858 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7859
7860 tiling = val & PLANE_CTL_TILED_MASK;
7861 switch (tiling) {
7862 case PLANE_CTL_TILED_LINEAR:
7863 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
7864 break;
7865 case PLANE_CTL_TILED_X:
7866 plane_config->tiling = I915_TILING_X;
7867 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7868 break;
7869 case PLANE_CTL_TILED_Y:
7870 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
7871 break;
7872 case PLANE_CTL_TILED_YF:
7873 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
7874 break;
7875 default:
7876 MISSING_CASE(tiling);
7877 goto error;
7878 }
7879
7880 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
7881 plane_config->base = base;
7882
7883 offset = I915_READ(PLANE_OFFSET(pipe, 0));
7884
7885 val = I915_READ(PLANE_SIZE(pipe, 0));
7886 fb->height = ((val >> 16) & 0xfff) + 1;
7887 fb->width = ((val >> 0) & 0x1fff) + 1;
7888
7889 val = I915_READ(PLANE_STRIDE(pipe, 0));
7890 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
7891 fb->pixel_format);
7892 fb->pitches[0] = (val & 0x3ff) * stride_mult;
7893
7894 aligned_height = intel_fb_align_height(dev, fb->height,
7895 fb->pixel_format,
7896 fb->modifier[0]);
7897
7898 plane_config->size = fb->pitches[0] * aligned_height;
7899
7900 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7901 pipe_name(pipe), fb->width, fb->height,
7902 fb->bits_per_pixel, base, fb->pitches[0],
7903 plane_config->size);
7904
7905 plane_config->fb = intel_fb;
7906 return;
7907
7908 error:
7909 kfree(fb);
7910 }
7911
7912 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7913 struct intel_crtc_state *pipe_config)
7914 {
7915 struct drm_device *dev = crtc->base.dev;
7916 struct drm_i915_private *dev_priv = dev->dev_private;
7917 uint32_t tmp;
7918
7919 tmp = I915_READ(PF_CTL(crtc->pipe));
7920
7921 if (tmp & PF_ENABLE) {
7922 pipe_config->pch_pfit.enabled = true;
7923 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7924 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7925
7926 /* We currently do not free assignements of panel fitters on
7927 * ivb/hsw (since we don't use the higher upscaling modes which
7928 * differentiates them) so just WARN about this case for now. */
7929 if (IS_GEN7(dev)) {
7930 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7931 PF_PIPE_SEL_IVB(crtc->pipe));
7932 }
7933 }
7934 }
7935
7936 static void
7937 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
7938 struct intel_initial_plane_config *plane_config)
7939 {
7940 struct drm_device *dev = crtc->base.dev;
7941 struct drm_i915_private *dev_priv = dev->dev_private;
7942 u32 val, base, offset;
7943 int pipe = crtc->pipe;
7944 int fourcc, pixel_format;
7945 int aligned_height;
7946 struct drm_framebuffer *fb;
7947 struct intel_framebuffer *intel_fb;
7948
7949 val = I915_READ(DSPCNTR(pipe));
7950 if (!(val & DISPLAY_PLANE_ENABLE))
7951 return;
7952
7953 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7954 if (!intel_fb) {
7955 DRM_DEBUG_KMS("failed to alloc fb\n");
7956 return;
7957 }
7958
7959 fb = &intel_fb->base;
7960
7961 if (INTEL_INFO(dev)->gen >= 4) {
7962 if (val & DISPPLANE_TILED) {
7963 plane_config->tiling = I915_TILING_X;
7964 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7965 }
7966 }
7967
7968 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7969 fourcc = i9xx_format_to_fourcc(pixel_format);
7970 fb->pixel_format = fourcc;
7971 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7972
7973 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
7974 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7975 offset = I915_READ(DSPOFFSET(pipe));
7976 } else {
7977 if (plane_config->tiling)
7978 offset = I915_READ(DSPTILEOFF(pipe));
7979 else
7980 offset = I915_READ(DSPLINOFF(pipe));
7981 }
7982 plane_config->base = base;
7983
7984 val = I915_READ(PIPESRC(pipe));
7985 fb->width = ((val >> 16) & 0xfff) + 1;
7986 fb->height = ((val >> 0) & 0xfff) + 1;
7987
7988 val = I915_READ(DSPSTRIDE(pipe));
7989 fb->pitches[0] = val & 0xffffffc0;
7990
7991 aligned_height = intel_fb_align_height(dev, fb->height,
7992 fb->pixel_format,
7993 fb->modifier[0]);
7994
7995 plane_config->size = fb->pitches[0] * aligned_height;
7996
7997 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7998 pipe_name(pipe), fb->width, fb->height,
7999 fb->bits_per_pixel, base, fb->pitches[0],
8000 plane_config->size);
8001
8002 plane_config->fb = intel_fb;
8003 }
8004
8005 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8006 struct intel_crtc_state *pipe_config)
8007 {
8008 struct drm_device *dev = crtc->base.dev;
8009 struct drm_i915_private *dev_priv = dev->dev_private;
8010 uint32_t tmp;
8011
8012 if (!intel_display_power_is_enabled(dev_priv,
8013 POWER_DOMAIN_PIPE(crtc->pipe)))
8014 return false;
8015
8016 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8017 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8018
8019 tmp = I915_READ(PIPECONF(crtc->pipe));
8020 if (!(tmp & PIPECONF_ENABLE))
8021 return false;
8022
8023 switch (tmp & PIPECONF_BPC_MASK) {
8024 case PIPECONF_6BPC:
8025 pipe_config->pipe_bpp = 18;
8026 break;
8027 case PIPECONF_8BPC:
8028 pipe_config->pipe_bpp = 24;
8029 break;
8030 case PIPECONF_10BPC:
8031 pipe_config->pipe_bpp = 30;
8032 break;
8033 case PIPECONF_12BPC:
8034 pipe_config->pipe_bpp = 36;
8035 break;
8036 default:
8037 break;
8038 }
8039
8040 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8041 pipe_config->limited_color_range = true;
8042
8043 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8044 struct intel_shared_dpll *pll;
8045
8046 pipe_config->has_pch_encoder = true;
8047
8048 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8049 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8050 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8051
8052 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8053
8054 if (HAS_PCH_IBX(dev_priv->dev)) {
8055 pipe_config->shared_dpll =
8056 (enum intel_dpll_id) crtc->pipe;
8057 } else {
8058 tmp = I915_READ(PCH_DPLL_SEL);
8059 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8060 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
8061 else
8062 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
8063 }
8064
8065 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8066
8067 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8068 &pipe_config->dpll_hw_state));
8069
8070 tmp = pipe_config->dpll_hw_state.dpll;
8071 pipe_config->pixel_multiplier =
8072 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8073 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8074
8075 ironlake_pch_clock_get(crtc, pipe_config);
8076 } else {
8077 pipe_config->pixel_multiplier = 1;
8078 }
8079
8080 intel_get_pipe_timings(crtc, pipe_config);
8081
8082 ironlake_get_pfit_config(crtc, pipe_config);
8083
8084 return true;
8085 }
8086
8087 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8088 {
8089 struct drm_device *dev = dev_priv->dev;
8090 struct intel_crtc *crtc;
8091
8092 for_each_intel_crtc(dev, crtc)
8093 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8094 pipe_name(crtc->pipe));
8095
8096 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8097 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8098 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8099 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8100 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
8101 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8102 "CPU PWM1 enabled\n");
8103 if (IS_HASWELL(dev))
8104 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8105 "CPU PWM2 enabled\n");
8106 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8107 "PCH PWM1 enabled\n");
8108 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8109 "Utility pin enabled\n");
8110 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8111
8112 /*
8113 * In theory we can still leave IRQs enabled, as long as only the HPD
8114 * interrupts remain enabled. We used to check for that, but since it's
8115 * gen-specific and since we only disable LCPLL after we fully disable
8116 * the interrupts, the check below should be enough.
8117 */
8118 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8119 }
8120
8121 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8122 {
8123 struct drm_device *dev = dev_priv->dev;
8124
8125 if (IS_HASWELL(dev))
8126 return I915_READ(D_COMP_HSW);
8127 else
8128 return I915_READ(D_COMP_BDW);
8129 }
8130
8131 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8132 {
8133 struct drm_device *dev = dev_priv->dev;
8134
8135 if (IS_HASWELL(dev)) {
8136 mutex_lock(&dev_priv->rps.hw_lock);
8137 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8138 val))
8139 DRM_ERROR("Failed to write to D_COMP\n");
8140 mutex_unlock(&dev_priv->rps.hw_lock);
8141 } else {
8142 I915_WRITE(D_COMP_BDW, val);
8143 POSTING_READ(D_COMP_BDW);
8144 }
8145 }
8146
8147 /*
8148 * This function implements pieces of two sequences from BSpec:
8149 * - Sequence for display software to disable LCPLL
8150 * - Sequence for display software to allow package C8+
8151 * The steps implemented here are just the steps that actually touch the LCPLL
8152 * register. Callers should take care of disabling all the display engine
8153 * functions, doing the mode unset, fixing interrupts, etc.
8154 */
8155 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8156 bool switch_to_fclk, bool allow_power_down)
8157 {
8158 uint32_t val;
8159
8160 assert_can_disable_lcpll(dev_priv);
8161
8162 val = I915_READ(LCPLL_CTL);
8163
8164 if (switch_to_fclk) {
8165 val |= LCPLL_CD_SOURCE_FCLK;
8166 I915_WRITE(LCPLL_CTL, val);
8167
8168 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
8169 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8170 DRM_ERROR("Switching to FCLK failed\n");
8171
8172 val = I915_READ(LCPLL_CTL);
8173 }
8174
8175 val |= LCPLL_PLL_DISABLE;
8176 I915_WRITE(LCPLL_CTL, val);
8177 POSTING_READ(LCPLL_CTL);
8178
8179 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
8180 DRM_ERROR("LCPLL still locked\n");
8181
8182 val = hsw_read_dcomp(dev_priv);
8183 val |= D_COMP_COMP_DISABLE;
8184 hsw_write_dcomp(dev_priv, val);
8185 ndelay(100);
8186
8187 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8188 1))
8189 DRM_ERROR("D_COMP RCOMP still in progress\n");
8190
8191 if (allow_power_down) {
8192 val = I915_READ(LCPLL_CTL);
8193 val |= LCPLL_POWER_DOWN_ALLOW;
8194 I915_WRITE(LCPLL_CTL, val);
8195 POSTING_READ(LCPLL_CTL);
8196 }
8197 }
8198
8199 /*
8200 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8201 * source.
8202 */
8203 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8204 {
8205 uint32_t val;
8206
8207 val = I915_READ(LCPLL_CTL);
8208
8209 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8210 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8211 return;
8212
8213 /*
8214 * Make sure we're not on PC8 state before disabling PC8, otherwise
8215 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8216 */
8217 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8218
8219 if (val & LCPLL_POWER_DOWN_ALLOW) {
8220 val &= ~LCPLL_POWER_DOWN_ALLOW;
8221 I915_WRITE(LCPLL_CTL, val);
8222 POSTING_READ(LCPLL_CTL);
8223 }
8224
8225 val = hsw_read_dcomp(dev_priv);
8226 val |= D_COMP_COMP_FORCE;
8227 val &= ~D_COMP_COMP_DISABLE;
8228 hsw_write_dcomp(dev_priv, val);
8229
8230 val = I915_READ(LCPLL_CTL);
8231 val &= ~LCPLL_PLL_DISABLE;
8232 I915_WRITE(LCPLL_CTL, val);
8233
8234 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
8235 DRM_ERROR("LCPLL not locked yet\n");
8236
8237 if (val & LCPLL_CD_SOURCE_FCLK) {
8238 val = I915_READ(LCPLL_CTL);
8239 val &= ~LCPLL_CD_SOURCE_FCLK;
8240 I915_WRITE(LCPLL_CTL, val);
8241
8242 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
8243 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8244 DRM_ERROR("Switching back to LCPLL failed\n");
8245 }
8246
8247 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8248 }
8249
8250 /*
8251 * Package states C8 and deeper are really deep PC states that can only be
8252 * reached when all the devices on the system allow it, so even if the graphics
8253 * device allows PC8+, it doesn't mean the system will actually get to these
8254 * states. Our driver only allows PC8+ when going into runtime PM.
8255 *
8256 * The requirements for PC8+ are that all the outputs are disabled, the power
8257 * well is disabled and most interrupts are disabled, and these are also
8258 * requirements for runtime PM. When these conditions are met, we manually do
8259 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8260 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8261 * hang the machine.
8262 *
8263 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8264 * the state of some registers, so when we come back from PC8+ we need to
8265 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8266 * need to take care of the registers kept by RC6. Notice that this happens even
8267 * if we don't put the device in PCI D3 state (which is what currently happens
8268 * because of the runtime PM support).
8269 *
8270 * For more, read "Display Sequences for Package C8" on the hardware
8271 * documentation.
8272 */
8273 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8274 {
8275 struct drm_device *dev = dev_priv->dev;
8276 uint32_t val;
8277
8278 DRM_DEBUG_KMS("Enabling package C8+\n");
8279
8280 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8281 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8282 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8283 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8284 }
8285
8286 lpt_disable_clkout_dp(dev);
8287 hsw_disable_lcpll(dev_priv, true, true);
8288 }
8289
8290 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8291 {
8292 struct drm_device *dev = dev_priv->dev;
8293 uint32_t val;
8294
8295 DRM_DEBUG_KMS("Disabling package C8+\n");
8296
8297 hsw_restore_lcpll(dev_priv);
8298 lpt_init_pch_refclk(dev);
8299
8300 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8301 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8302 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8303 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8304 }
8305
8306 intel_prepare_ddi(dev);
8307 }
8308
8309 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8310 struct intel_crtc_state *crtc_state)
8311 {
8312 if (!intel_ddi_pll_select(crtc, crtc_state))
8313 return -EINVAL;
8314
8315 crtc->lowfreq_avail = false;
8316
8317 return 0;
8318 }
8319
8320 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8321 enum port port,
8322 struct intel_crtc_state *pipe_config)
8323 {
8324 u32 temp, dpll_ctl1;
8325
8326 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8327 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
8328
8329 switch (pipe_config->ddi_pll_sel) {
8330 case SKL_DPLL0:
8331 /*
8332 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
8333 * of the shared DPLL framework and thus needs to be read out
8334 * separately
8335 */
8336 dpll_ctl1 = I915_READ(DPLL_CTRL1);
8337 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
8338 break;
8339 case SKL_DPLL1:
8340 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
8341 break;
8342 case SKL_DPLL2:
8343 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
8344 break;
8345 case SKL_DPLL3:
8346 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
8347 break;
8348 }
8349 }
8350
8351 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8352 enum port port,
8353 struct intel_crtc_state *pipe_config)
8354 {
8355 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8356
8357 switch (pipe_config->ddi_pll_sel) {
8358 case PORT_CLK_SEL_WRPLL1:
8359 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
8360 break;
8361 case PORT_CLK_SEL_WRPLL2:
8362 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
8363 break;
8364 }
8365 }
8366
8367 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
8368 struct intel_crtc_state *pipe_config)
8369 {
8370 struct drm_device *dev = crtc->base.dev;
8371 struct drm_i915_private *dev_priv = dev->dev_private;
8372 struct intel_shared_dpll *pll;
8373 enum port port;
8374 uint32_t tmp;
8375
8376 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
8377
8378 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8379
8380 if (IS_SKYLAKE(dev))
8381 skylake_get_ddi_pll(dev_priv, port, pipe_config);
8382 else
8383 haswell_get_ddi_pll(dev_priv, port, pipe_config);
8384
8385 if (pipe_config->shared_dpll >= 0) {
8386 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8387
8388 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8389 &pipe_config->dpll_hw_state));
8390 }
8391
8392 /*
8393 * Haswell has only FDI/PCH transcoder A. It is which is connected to
8394 * DDI E. So just check whether this pipe is wired to DDI E and whether
8395 * the PCH transcoder is on.
8396 */
8397 if (INTEL_INFO(dev)->gen < 9 &&
8398 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
8399 pipe_config->has_pch_encoder = true;
8400
8401 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8402 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8403 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8404
8405 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8406 }
8407 }
8408
8409 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
8410 struct intel_crtc_state *pipe_config)
8411 {
8412 struct drm_device *dev = crtc->base.dev;
8413 struct drm_i915_private *dev_priv = dev->dev_private;
8414 enum intel_display_power_domain pfit_domain;
8415 uint32_t tmp;
8416
8417 if (!intel_display_power_is_enabled(dev_priv,
8418 POWER_DOMAIN_PIPE(crtc->pipe)))
8419 return false;
8420
8421 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8422 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8423
8424 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8425 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8426 enum pipe trans_edp_pipe;
8427 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8428 default:
8429 WARN(1, "unknown pipe linked to edp transcoder\n");
8430 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8431 case TRANS_DDI_EDP_INPUT_A_ON:
8432 trans_edp_pipe = PIPE_A;
8433 break;
8434 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8435 trans_edp_pipe = PIPE_B;
8436 break;
8437 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8438 trans_edp_pipe = PIPE_C;
8439 break;
8440 }
8441
8442 if (trans_edp_pipe == crtc->pipe)
8443 pipe_config->cpu_transcoder = TRANSCODER_EDP;
8444 }
8445
8446 if (!intel_display_power_is_enabled(dev_priv,
8447 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
8448 return false;
8449
8450 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8451 if (!(tmp & PIPECONF_ENABLE))
8452 return false;
8453
8454 haswell_get_ddi_port_state(crtc, pipe_config);
8455
8456 intel_get_pipe_timings(crtc, pipe_config);
8457
8458 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
8459 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
8460 if (IS_SKYLAKE(dev))
8461 skylake_get_pfit_config(crtc, pipe_config);
8462 else
8463 ironlake_get_pfit_config(crtc, pipe_config);
8464 }
8465
8466 if (IS_HASWELL(dev))
8467 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8468 (I915_READ(IPS_CTL) & IPS_ENABLE);
8469
8470 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8471 pipe_config->pixel_multiplier =
8472 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8473 } else {
8474 pipe_config->pixel_multiplier = 1;
8475 }
8476
8477 return true;
8478 }
8479
8480 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8481 {
8482 struct drm_device *dev = crtc->dev;
8483 struct drm_i915_private *dev_priv = dev->dev_private;
8484 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8485 uint32_t cntl = 0, size = 0;
8486
8487 if (base) {
8488 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
8489 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
8490 unsigned int stride = roundup_pow_of_two(width) * 4;
8491
8492 switch (stride) {
8493 default:
8494 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8495 width, stride);
8496 stride = 256;
8497 /* fallthrough */
8498 case 256:
8499 case 512:
8500 case 1024:
8501 case 2048:
8502 break;
8503 }
8504
8505 cntl |= CURSOR_ENABLE |
8506 CURSOR_GAMMA_ENABLE |
8507 CURSOR_FORMAT_ARGB |
8508 CURSOR_STRIDE(stride);
8509
8510 size = (height << 12) | width;
8511 }
8512
8513 if (intel_crtc->cursor_cntl != 0 &&
8514 (intel_crtc->cursor_base != base ||
8515 intel_crtc->cursor_size != size ||
8516 intel_crtc->cursor_cntl != cntl)) {
8517 /* On these chipsets we can only modify the base/size/stride
8518 * whilst the cursor is disabled.
8519 */
8520 I915_WRITE(_CURACNTR, 0);
8521 POSTING_READ(_CURACNTR);
8522 intel_crtc->cursor_cntl = 0;
8523 }
8524
8525 if (intel_crtc->cursor_base != base) {
8526 I915_WRITE(_CURABASE, base);
8527 intel_crtc->cursor_base = base;
8528 }
8529
8530 if (intel_crtc->cursor_size != size) {
8531 I915_WRITE(CURSIZE, size);
8532 intel_crtc->cursor_size = size;
8533 }
8534
8535 if (intel_crtc->cursor_cntl != cntl) {
8536 I915_WRITE(_CURACNTR, cntl);
8537 POSTING_READ(_CURACNTR);
8538 intel_crtc->cursor_cntl = cntl;
8539 }
8540 }
8541
8542 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8543 {
8544 struct drm_device *dev = crtc->dev;
8545 struct drm_i915_private *dev_priv = dev->dev_private;
8546 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8547 int pipe = intel_crtc->pipe;
8548 uint32_t cntl;
8549
8550 cntl = 0;
8551 if (base) {
8552 cntl = MCURSOR_GAMMA_ENABLE;
8553 switch (intel_crtc->base.cursor->state->crtc_w) {
8554 case 64:
8555 cntl |= CURSOR_MODE_64_ARGB_AX;
8556 break;
8557 case 128:
8558 cntl |= CURSOR_MODE_128_ARGB_AX;
8559 break;
8560 case 256:
8561 cntl |= CURSOR_MODE_256_ARGB_AX;
8562 break;
8563 default:
8564 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
8565 return;
8566 }
8567 cntl |= pipe << 28; /* Connect to correct pipe */
8568
8569 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8570 cntl |= CURSOR_PIPE_CSC_ENABLE;
8571 }
8572
8573 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
8574 cntl |= CURSOR_ROTATE_180;
8575
8576 if (intel_crtc->cursor_cntl != cntl) {
8577 I915_WRITE(CURCNTR(pipe), cntl);
8578 POSTING_READ(CURCNTR(pipe));
8579 intel_crtc->cursor_cntl = cntl;
8580 }
8581
8582 /* and commit changes on next vblank */
8583 I915_WRITE(CURBASE(pipe), base);
8584 POSTING_READ(CURBASE(pipe));
8585
8586 intel_crtc->cursor_base = base;
8587 }
8588
8589 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8590 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8591 bool on)
8592 {
8593 struct drm_device *dev = crtc->dev;
8594 struct drm_i915_private *dev_priv = dev->dev_private;
8595 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8596 int pipe = intel_crtc->pipe;
8597 int x = crtc->cursor_x;
8598 int y = crtc->cursor_y;
8599 u32 base = 0, pos = 0;
8600
8601 if (on)
8602 base = intel_crtc->cursor_addr;
8603
8604 if (x >= intel_crtc->config->pipe_src_w)
8605 base = 0;
8606
8607 if (y >= intel_crtc->config->pipe_src_h)
8608 base = 0;
8609
8610 if (x < 0) {
8611 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
8612 base = 0;
8613
8614 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8615 x = -x;
8616 }
8617 pos |= x << CURSOR_X_SHIFT;
8618
8619 if (y < 0) {
8620 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
8621 base = 0;
8622
8623 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8624 y = -y;
8625 }
8626 pos |= y << CURSOR_Y_SHIFT;
8627
8628 if (base == 0 && intel_crtc->cursor_base == 0)
8629 return;
8630
8631 I915_WRITE(CURPOS(pipe), pos);
8632
8633 /* ILK+ do this automagically */
8634 if (HAS_GMCH_DISPLAY(dev) &&
8635 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
8636 base += (intel_crtc->base.cursor->state->crtc_h *
8637 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
8638 }
8639
8640 if (IS_845G(dev) || IS_I865G(dev))
8641 i845_update_cursor(crtc, base);
8642 else
8643 i9xx_update_cursor(crtc, base);
8644 }
8645
8646 static bool cursor_size_ok(struct drm_device *dev,
8647 uint32_t width, uint32_t height)
8648 {
8649 if (width == 0 || height == 0)
8650 return false;
8651
8652 /*
8653 * 845g/865g are special in that they are only limited by
8654 * the width of their cursors, the height is arbitrary up to
8655 * the precision of the register. Everything else requires
8656 * square cursors, limited to a few power-of-two sizes.
8657 */
8658 if (IS_845G(dev) || IS_I865G(dev)) {
8659 if ((width & 63) != 0)
8660 return false;
8661
8662 if (width > (IS_845G(dev) ? 64 : 512))
8663 return false;
8664
8665 if (height > 1023)
8666 return false;
8667 } else {
8668 switch (width | height) {
8669 case 256:
8670 case 128:
8671 if (IS_GEN2(dev))
8672 return false;
8673 case 64:
8674 break;
8675 default:
8676 return false;
8677 }
8678 }
8679
8680 return true;
8681 }
8682
8683 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8684 u16 *blue, uint32_t start, uint32_t size)
8685 {
8686 int end = (start + size > 256) ? 256 : start + size, i;
8687 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8688
8689 for (i = start; i < end; i++) {
8690 intel_crtc->lut_r[i] = red[i] >> 8;
8691 intel_crtc->lut_g[i] = green[i] >> 8;
8692 intel_crtc->lut_b[i] = blue[i] >> 8;
8693 }
8694
8695 intel_crtc_load_lut(crtc);
8696 }
8697
8698 /* VESA 640x480x72Hz mode to set on the pipe */
8699 static struct drm_display_mode load_detect_mode = {
8700 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8701 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8702 };
8703
8704 struct drm_framebuffer *
8705 __intel_framebuffer_create(struct drm_device *dev,
8706 struct drm_mode_fb_cmd2 *mode_cmd,
8707 struct drm_i915_gem_object *obj)
8708 {
8709 struct intel_framebuffer *intel_fb;
8710 int ret;
8711
8712 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8713 if (!intel_fb) {
8714 drm_gem_object_unreference(&obj->base);
8715 return ERR_PTR(-ENOMEM);
8716 }
8717
8718 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8719 if (ret)
8720 goto err;
8721
8722 return &intel_fb->base;
8723 err:
8724 drm_gem_object_unreference(&obj->base);
8725 kfree(intel_fb);
8726
8727 return ERR_PTR(ret);
8728 }
8729
8730 static struct drm_framebuffer *
8731 intel_framebuffer_create(struct drm_device *dev,
8732 struct drm_mode_fb_cmd2 *mode_cmd,
8733 struct drm_i915_gem_object *obj)
8734 {
8735 struct drm_framebuffer *fb;
8736 int ret;
8737
8738 ret = i915_mutex_lock_interruptible(dev);
8739 if (ret)
8740 return ERR_PTR(ret);
8741 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8742 mutex_unlock(&dev->struct_mutex);
8743
8744 return fb;
8745 }
8746
8747 static u32
8748 intel_framebuffer_pitch_for_width(int width, int bpp)
8749 {
8750 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8751 return ALIGN(pitch, 64);
8752 }
8753
8754 static u32
8755 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8756 {
8757 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8758 return PAGE_ALIGN(pitch * mode->vdisplay);
8759 }
8760
8761 static struct drm_framebuffer *
8762 intel_framebuffer_create_for_mode(struct drm_device *dev,
8763 struct drm_display_mode *mode,
8764 int depth, int bpp)
8765 {
8766 struct drm_i915_gem_object *obj;
8767 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8768
8769 obj = i915_gem_alloc_object(dev,
8770 intel_framebuffer_size_for_mode(mode, bpp));
8771 if (obj == NULL)
8772 return ERR_PTR(-ENOMEM);
8773
8774 mode_cmd.width = mode->hdisplay;
8775 mode_cmd.height = mode->vdisplay;
8776 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8777 bpp);
8778 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8779
8780 return intel_framebuffer_create(dev, &mode_cmd, obj);
8781 }
8782
8783 static struct drm_framebuffer *
8784 mode_fits_in_fbdev(struct drm_device *dev,
8785 struct drm_display_mode *mode)
8786 {
8787 #ifdef CONFIG_DRM_I915_FBDEV
8788 struct drm_i915_private *dev_priv = dev->dev_private;
8789 struct drm_i915_gem_object *obj;
8790 struct drm_framebuffer *fb;
8791
8792 if (!dev_priv->fbdev)
8793 return NULL;
8794
8795 if (!dev_priv->fbdev->fb)
8796 return NULL;
8797
8798 obj = dev_priv->fbdev->fb->obj;
8799 BUG_ON(!obj);
8800
8801 fb = &dev_priv->fbdev->fb->base;
8802 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8803 fb->bits_per_pixel))
8804 return NULL;
8805
8806 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8807 return NULL;
8808
8809 return fb;
8810 #else
8811 return NULL;
8812 #endif
8813 }
8814
8815 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8816 struct drm_display_mode *mode,
8817 struct intel_load_detect_pipe *old,
8818 struct drm_modeset_acquire_ctx *ctx)
8819 {
8820 struct intel_crtc *intel_crtc;
8821 struct intel_encoder *intel_encoder =
8822 intel_attached_encoder(connector);
8823 struct drm_crtc *possible_crtc;
8824 struct drm_encoder *encoder = &intel_encoder->base;
8825 struct drm_crtc *crtc = NULL;
8826 struct drm_device *dev = encoder->dev;
8827 struct drm_framebuffer *fb;
8828 struct drm_mode_config *config = &dev->mode_config;
8829 int ret, i = -1;
8830
8831 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8832 connector->base.id, connector->name,
8833 encoder->base.id, encoder->name);
8834
8835 retry:
8836 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8837 if (ret)
8838 goto fail_unlock;
8839
8840 /*
8841 * Algorithm gets a little messy:
8842 *
8843 * - if the connector already has an assigned crtc, use it (but make
8844 * sure it's on first)
8845 *
8846 * - try to find the first unused crtc that can drive this connector,
8847 * and use that if we find one
8848 */
8849
8850 /* See if we already have a CRTC for this connector */
8851 if (encoder->crtc) {
8852 crtc = encoder->crtc;
8853
8854 ret = drm_modeset_lock(&crtc->mutex, ctx);
8855 if (ret)
8856 goto fail_unlock;
8857 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8858 if (ret)
8859 goto fail_unlock;
8860
8861 old->dpms_mode = connector->dpms;
8862 old->load_detect_temp = false;
8863
8864 /* Make sure the crtc and connector are running */
8865 if (connector->dpms != DRM_MODE_DPMS_ON)
8866 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8867
8868 return true;
8869 }
8870
8871 /* Find an unused one (if possible) */
8872 for_each_crtc(dev, possible_crtc) {
8873 i++;
8874 if (!(encoder->possible_crtcs & (1 << i)))
8875 continue;
8876 if (possible_crtc->state->enable)
8877 continue;
8878 /* This can occur when applying the pipe A quirk on resume. */
8879 if (to_intel_crtc(possible_crtc)->new_enabled)
8880 continue;
8881
8882 crtc = possible_crtc;
8883 break;
8884 }
8885
8886 /*
8887 * If we didn't find an unused CRTC, don't use any.
8888 */
8889 if (!crtc) {
8890 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8891 goto fail_unlock;
8892 }
8893
8894 ret = drm_modeset_lock(&crtc->mutex, ctx);
8895 if (ret)
8896 goto fail_unlock;
8897 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8898 if (ret)
8899 goto fail_unlock;
8900 intel_encoder->new_crtc = to_intel_crtc(crtc);
8901 to_intel_connector(connector)->new_encoder = intel_encoder;
8902
8903 intel_crtc = to_intel_crtc(crtc);
8904 intel_crtc->new_enabled = true;
8905 intel_crtc->new_config = intel_crtc->config;
8906 old->dpms_mode = connector->dpms;
8907 old->load_detect_temp = true;
8908 old->release_fb = NULL;
8909
8910 if (!mode)
8911 mode = &load_detect_mode;
8912
8913 /* We need a framebuffer large enough to accommodate all accesses
8914 * that the plane may generate whilst we perform load detection.
8915 * We can not rely on the fbcon either being present (we get called
8916 * during its initialisation to detect all boot displays, or it may
8917 * not even exist) or that it is large enough to satisfy the
8918 * requested mode.
8919 */
8920 fb = mode_fits_in_fbdev(dev, mode);
8921 if (fb == NULL) {
8922 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8923 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8924 old->release_fb = fb;
8925 } else
8926 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8927 if (IS_ERR(fb)) {
8928 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8929 goto fail;
8930 }
8931
8932 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8933 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8934 if (old->release_fb)
8935 old->release_fb->funcs->destroy(old->release_fb);
8936 goto fail;
8937 }
8938 crtc->primary->crtc = crtc;
8939
8940 /* let the connector get through one full cycle before testing */
8941 intel_wait_for_vblank(dev, intel_crtc->pipe);
8942 return true;
8943
8944 fail:
8945 intel_crtc->new_enabled = crtc->state->enable;
8946 if (intel_crtc->new_enabled)
8947 intel_crtc->new_config = intel_crtc->config;
8948 else
8949 intel_crtc->new_config = NULL;
8950 fail_unlock:
8951 if (ret == -EDEADLK) {
8952 drm_modeset_backoff(ctx);
8953 goto retry;
8954 }
8955
8956 return false;
8957 }
8958
8959 void intel_release_load_detect_pipe(struct drm_connector *connector,
8960 struct intel_load_detect_pipe *old)
8961 {
8962 struct intel_encoder *intel_encoder =
8963 intel_attached_encoder(connector);
8964 struct drm_encoder *encoder = &intel_encoder->base;
8965 struct drm_crtc *crtc = encoder->crtc;
8966 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8967
8968 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8969 connector->base.id, connector->name,
8970 encoder->base.id, encoder->name);
8971
8972 if (old->load_detect_temp) {
8973 to_intel_connector(connector)->new_encoder = NULL;
8974 intel_encoder->new_crtc = NULL;
8975 intel_crtc->new_enabled = false;
8976 intel_crtc->new_config = NULL;
8977 intel_set_mode(crtc, NULL, 0, 0, NULL);
8978
8979 if (old->release_fb) {
8980 drm_framebuffer_unregister_private(old->release_fb);
8981 drm_framebuffer_unreference(old->release_fb);
8982 }
8983
8984 return;
8985 }
8986
8987 /* Switch crtc and encoder back off if necessary */
8988 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8989 connector->funcs->dpms(connector, old->dpms_mode);
8990 }
8991
8992 static int i9xx_pll_refclk(struct drm_device *dev,
8993 const struct intel_crtc_state *pipe_config)
8994 {
8995 struct drm_i915_private *dev_priv = dev->dev_private;
8996 u32 dpll = pipe_config->dpll_hw_state.dpll;
8997
8998 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8999 return dev_priv->vbt.lvds_ssc_freq;
9000 else if (HAS_PCH_SPLIT(dev))
9001 return 120000;
9002 else if (!IS_GEN2(dev))
9003 return 96000;
9004 else
9005 return 48000;
9006 }
9007
9008 /* Returns the clock of the currently programmed mode of the given pipe. */
9009 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
9010 struct intel_crtc_state *pipe_config)
9011 {
9012 struct drm_device *dev = crtc->base.dev;
9013 struct drm_i915_private *dev_priv = dev->dev_private;
9014 int pipe = pipe_config->cpu_transcoder;
9015 u32 dpll = pipe_config->dpll_hw_state.dpll;
9016 u32 fp;
9017 intel_clock_t clock;
9018 int refclk = i9xx_pll_refclk(dev, pipe_config);
9019
9020 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
9021 fp = pipe_config->dpll_hw_state.fp0;
9022 else
9023 fp = pipe_config->dpll_hw_state.fp1;
9024
9025 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
9026 if (IS_PINEVIEW(dev)) {
9027 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
9028 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
9029 } else {
9030 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
9031 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
9032 }
9033
9034 if (!IS_GEN2(dev)) {
9035 if (IS_PINEVIEW(dev))
9036 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
9037 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
9038 else
9039 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
9040 DPLL_FPA01_P1_POST_DIV_SHIFT);
9041
9042 switch (dpll & DPLL_MODE_MASK) {
9043 case DPLLB_MODE_DAC_SERIAL:
9044 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
9045 5 : 10;
9046 break;
9047 case DPLLB_MODE_LVDS:
9048 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
9049 7 : 14;
9050 break;
9051 default:
9052 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
9053 "mode\n", (int)(dpll & DPLL_MODE_MASK));
9054 return;
9055 }
9056
9057 if (IS_PINEVIEW(dev))
9058 pineview_clock(refclk, &clock);
9059 else
9060 i9xx_clock(refclk, &clock);
9061 } else {
9062 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
9063 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
9064
9065 if (is_lvds) {
9066 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
9067 DPLL_FPA01_P1_POST_DIV_SHIFT);
9068
9069 if (lvds & LVDS_CLKB_POWER_UP)
9070 clock.p2 = 7;
9071 else
9072 clock.p2 = 14;
9073 } else {
9074 if (dpll & PLL_P1_DIVIDE_BY_TWO)
9075 clock.p1 = 2;
9076 else {
9077 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
9078 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
9079 }
9080 if (dpll & PLL_P2_DIVIDE_BY_4)
9081 clock.p2 = 4;
9082 else
9083 clock.p2 = 2;
9084 }
9085
9086 i9xx_clock(refclk, &clock);
9087 }
9088
9089 /*
9090 * This value includes pixel_multiplier. We will use
9091 * port_clock to compute adjusted_mode.crtc_clock in the
9092 * encoder's get_config() function.
9093 */
9094 pipe_config->port_clock = clock.dot;
9095 }
9096
9097 int intel_dotclock_calculate(int link_freq,
9098 const struct intel_link_m_n *m_n)
9099 {
9100 /*
9101 * The calculation for the data clock is:
9102 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
9103 * But we want to avoid losing precison if possible, so:
9104 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
9105 *
9106 * and the link clock is simpler:
9107 * link_clock = (m * link_clock) / n
9108 */
9109
9110 if (!m_n->link_n)
9111 return 0;
9112
9113 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
9114 }
9115
9116 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
9117 struct intel_crtc_state *pipe_config)
9118 {
9119 struct drm_device *dev = crtc->base.dev;
9120
9121 /* read out port_clock from the DPLL */
9122 i9xx_crtc_clock_get(crtc, pipe_config);
9123
9124 /*
9125 * This value does not include pixel_multiplier.
9126 * We will check that port_clock and adjusted_mode.crtc_clock
9127 * agree once we know their relationship in the encoder's
9128 * get_config() function.
9129 */
9130 pipe_config->base.adjusted_mode.crtc_clock =
9131 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
9132 &pipe_config->fdi_m_n);
9133 }
9134
9135 /** Returns the currently programmed mode of the given pipe. */
9136 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
9137 struct drm_crtc *crtc)
9138 {
9139 struct drm_i915_private *dev_priv = dev->dev_private;
9140 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9141 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9142 struct drm_display_mode *mode;
9143 struct intel_crtc_state pipe_config;
9144 int htot = I915_READ(HTOTAL(cpu_transcoder));
9145 int hsync = I915_READ(HSYNC(cpu_transcoder));
9146 int vtot = I915_READ(VTOTAL(cpu_transcoder));
9147 int vsync = I915_READ(VSYNC(cpu_transcoder));
9148 enum pipe pipe = intel_crtc->pipe;
9149
9150 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
9151 if (!mode)
9152 return NULL;
9153
9154 /*
9155 * Construct a pipe_config sufficient for getting the clock info
9156 * back out of crtc_clock_get.
9157 *
9158 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9159 * to use a real value here instead.
9160 */
9161 pipe_config.cpu_transcoder = (enum transcoder) pipe;
9162 pipe_config.pixel_multiplier = 1;
9163 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9164 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9165 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
9166 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
9167
9168 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
9169 mode->hdisplay = (htot & 0xffff) + 1;
9170 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9171 mode->hsync_start = (hsync & 0xffff) + 1;
9172 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9173 mode->vdisplay = (vtot & 0xffff) + 1;
9174 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9175 mode->vsync_start = (vsync & 0xffff) + 1;
9176 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9177
9178 drm_mode_set_name(mode);
9179
9180 return mode;
9181 }
9182
9183 static void intel_decrease_pllclock(struct drm_crtc *crtc)
9184 {
9185 struct drm_device *dev = crtc->dev;
9186 struct drm_i915_private *dev_priv = dev->dev_private;
9187 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9188
9189 if (!HAS_GMCH_DISPLAY(dev))
9190 return;
9191
9192 if (!dev_priv->lvds_downclock_avail)
9193 return;
9194
9195 /*
9196 * Since this is called by a timer, we should never get here in
9197 * the manual case.
9198 */
9199 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
9200 int pipe = intel_crtc->pipe;
9201 int dpll_reg = DPLL(pipe);
9202 int dpll;
9203
9204 DRM_DEBUG_DRIVER("downclocking LVDS\n");
9205
9206 assert_panel_unlocked(dev_priv, pipe);
9207
9208 dpll = I915_READ(dpll_reg);
9209 dpll |= DISPLAY_RATE_SELECT_FPA1;
9210 I915_WRITE(dpll_reg, dpll);
9211 intel_wait_for_vblank(dev, pipe);
9212 dpll = I915_READ(dpll_reg);
9213 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
9214 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
9215 }
9216
9217 }
9218
9219 void intel_mark_busy(struct drm_device *dev)
9220 {
9221 struct drm_i915_private *dev_priv = dev->dev_private;
9222
9223 if (dev_priv->mm.busy)
9224 return;
9225
9226 intel_runtime_pm_get(dev_priv);
9227 i915_update_gfx_val(dev_priv);
9228 dev_priv->mm.busy = true;
9229 }
9230
9231 void intel_mark_idle(struct drm_device *dev)
9232 {
9233 struct drm_i915_private *dev_priv = dev->dev_private;
9234 struct drm_crtc *crtc;
9235
9236 if (!dev_priv->mm.busy)
9237 return;
9238
9239 dev_priv->mm.busy = false;
9240
9241 if (!i915.powersave)
9242 goto out;
9243
9244 for_each_crtc(dev, crtc) {
9245 if (!crtc->primary->fb)
9246 continue;
9247
9248 intel_decrease_pllclock(crtc);
9249 }
9250
9251 if (INTEL_INFO(dev)->gen >= 6)
9252 gen6_rps_idle(dev->dev_private);
9253
9254 out:
9255 intel_runtime_pm_put(dev_priv);
9256 }
9257
9258 static void intel_crtc_set_state(struct intel_crtc *crtc,
9259 struct intel_crtc_state *crtc_state)
9260 {
9261 kfree(crtc->config);
9262 crtc->config = crtc_state;
9263 crtc->base.state = &crtc_state->base;
9264 }
9265
9266 static void intel_crtc_destroy(struct drm_crtc *crtc)
9267 {
9268 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9269 struct drm_device *dev = crtc->dev;
9270 struct intel_unpin_work *work;
9271
9272 spin_lock_irq(&dev->event_lock);
9273 work = intel_crtc->unpin_work;
9274 intel_crtc->unpin_work = NULL;
9275 spin_unlock_irq(&dev->event_lock);
9276
9277 if (work) {
9278 cancel_work_sync(&work->work);
9279 kfree(work);
9280 }
9281
9282 intel_crtc_set_state(intel_crtc, NULL);
9283 drm_crtc_cleanup(crtc);
9284
9285 kfree(intel_crtc);
9286 }
9287
9288 static void intel_unpin_work_fn(struct work_struct *__work)
9289 {
9290 struct intel_unpin_work *work =
9291 container_of(__work, struct intel_unpin_work, work);
9292 struct drm_device *dev = work->crtc->dev;
9293 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9294
9295 mutex_lock(&dev->struct_mutex);
9296 intel_unpin_fb_obj(intel_fb_obj(work->old_fb));
9297 drm_gem_object_unreference(&work->pending_flip_obj->base);
9298
9299 intel_fbc_update(dev);
9300
9301 if (work->flip_queued_req)
9302 i915_gem_request_assign(&work->flip_queued_req, NULL);
9303 mutex_unlock(&dev->struct_mutex);
9304
9305 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9306 drm_framebuffer_unreference(work->old_fb);
9307
9308 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9309 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9310
9311 kfree(work);
9312 }
9313
9314 static void do_intel_finish_page_flip(struct drm_device *dev,
9315 struct drm_crtc *crtc)
9316 {
9317 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9318 struct intel_unpin_work *work;
9319 unsigned long flags;
9320
9321 /* Ignore early vblank irqs */
9322 if (intel_crtc == NULL)
9323 return;
9324
9325 /*
9326 * This is called both by irq handlers and the reset code (to complete
9327 * lost pageflips) so needs the full irqsave spinlocks.
9328 */
9329 spin_lock_irqsave(&dev->event_lock, flags);
9330 work = intel_crtc->unpin_work;
9331
9332 /* Ensure we don't miss a work->pending update ... */
9333 smp_rmb();
9334
9335 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9336 spin_unlock_irqrestore(&dev->event_lock, flags);
9337 return;
9338 }
9339
9340 page_flip_completed(intel_crtc);
9341
9342 spin_unlock_irqrestore(&dev->event_lock, flags);
9343 }
9344
9345 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9346 {
9347 struct drm_i915_private *dev_priv = dev->dev_private;
9348 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9349
9350 do_intel_finish_page_flip(dev, crtc);
9351 }
9352
9353 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9354 {
9355 struct drm_i915_private *dev_priv = dev->dev_private;
9356 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9357
9358 do_intel_finish_page_flip(dev, crtc);
9359 }
9360
9361 /* Is 'a' after or equal to 'b'? */
9362 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9363 {
9364 return !((a - b) & 0x80000000);
9365 }
9366
9367 static bool page_flip_finished(struct intel_crtc *crtc)
9368 {
9369 struct drm_device *dev = crtc->base.dev;
9370 struct drm_i915_private *dev_priv = dev->dev_private;
9371
9372 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
9373 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
9374 return true;
9375
9376 /*
9377 * The relevant registers doen't exist on pre-ctg.
9378 * As the flip done interrupt doesn't trigger for mmio
9379 * flips on gmch platforms, a flip count check isn't
9380 * really needed there. But since ctg has the registers,
9381 * include it in the check anyway.
9382 */
9383 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9384 return true;
9385
9386 /*
9387 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9388 * used the same base address. In that case the mmio flip might
9389 * have completed, but the CS hasn't even executed the flip yet.
9390 *
9391 * A flip count check isn't enough as the CS might have updated
9392 * the base address just after start of vblank, but before we
9393 * managed to process the interrupt. This means we'd complete the
9394 * CS flip too soon.
9395 *
9396 * Combining both checks should get us a good enough result. It may
9397 * still happen that the CS flip has been executed, but has not
9398 * yet actually completed. But in case the base address is the same
9399 * anyway, we don't really care.
9400 */
9401 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9402 crtc->unpin_work->gtt_offset &&
9403 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9404 crtc->unpin_work->flip_count);
9405 }
9406
9407 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9408 {
9409 struct drm_i915_private *dev_priv = dev->dev_private;
9410 struct intel_crtc *intel_crtc =
9411 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9412 unsigned long flags;
9413
9414
9415 /*
9416 * This is called both by irq handlers and the reset code (to complete
9417 * lost pageflips) so needs the full irqsave spinlocks.
9418 *
9419 * NB: An MMIO update of the plane base pointer will also
9420 * generate a page-flip completion irq, i.e. every modeset
9421 * is also accompanied by a spurious intel_prepare_page_flip().
9422 */
9423 spin_lock_irqsave(&dev->event_lock, flags);
9424 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9425 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9426 spin_unlock_irqrestore(&dev->event_lock, flags);
9427 }
9428
9429 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9430 {
9431 /* Ensure that the work item is consistent when activating it ... */
9432 smp_wmb();
9433 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9434 /* and that it is marked active as soon as the irq could fire. */
9435 smp_wmb();
9436 }
9437
9438 static int intel_gen2_queue_flip(struct drm_device *dev,
9439 struct drm_crtc *crtc,
9440 struct drm_framebuffer *fb,
9441 struct drm_i915_gem_object *obj,
9442 struct intel_engine_cs *ring,
9443 uint32_t flags)
9444 {
9445 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9446 u32 flip_mask;
9447 int ret;
9448
9449 ret = intel_ring_begin(ring, 6);
9450 if (ret)
9451 return ret;
9452
9453 /* Can't queue multiple flips, so wait for the previous
9454 * one to finish before executing the next.
9455 */
9456 if (intel_crtc->plane)
9457 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9458 else
9459 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9460 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9461 intel_ring_emit(ring, MI_NOOP);
9462 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9463 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9464 intel_ring_emit(ring, fb->pitches[0]);
9465 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9466 intel_ring_emit(ring, 0); /* aux display base address, unused */
9467
9468 intel_mark_page_flip_active(intel_crtc);
9469 __intel_ring_advance(ring);
9470 return 0;
9471 }
9472
9473 static int intel_gen3_queue_flip(struct drm_device *dev,
9474 struct drm_crtc *crtc,
9475 struct drm_framebuffer *fb,
9476 struct drm_i915_gem_object *obj,
9477 struct intel_engine_cs *ring,
9478 uint32_t flags)
9479 {
9480 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9481 u32 flip_mask;
9482 int ret;
9483
9484 ret = intel_ring_begin(ring, 6);
9485 if (ret)
9486 return ret;
9487
9488 if (intel_crtc->plane)
9489 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9490 else
9491 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9492 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9493 intel_ring_emit(ring, MI_NOOP);
9494 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9495 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9496 intel_ring_emit(ring, fb->pitches[0]);
9497 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9498 intel_ring_emit(ring, MI_NOOP);
9499
9500 intel_mark_page_flip_active(intel_crtc);
9501 __intel_ring_advance(ring);
9502 return 0;
9503 }
9504
9505 static int intel_gen4_queue_flip(struct drm_device *dev,
9506 struct drm_crtc *crtc,
9507 struct drm_framebuffer *fb,
9508 struct drm_i915_gem_object *obj,
9509 struct intel_engine_cs *ring,
9510 uint32_t flags)
9511 {
9512 struct drm_i915_private *dev_priv = dev->dev_private;
9513 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9514 uint32_t pf, pipesrc;
9515 int ret;
9516
9517 ret = intel_ring_begin(ring, 4);
9518 if (ret)
9519 return ret;
9520
9521 /* i965+ uses the linear or tiled offsets from the
9522 * Display Registers (which do not change across a page-flip)
9523 * so we need only reprogram the base address.
9524 */
9525 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9526 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9527 intel_ring_emit(ring, fb->pitches[0]);
9528 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9529 obj->tiling_mode);
9530
9531 /* XXX Enabling the panel-fitter across page-flip is so far
9532 * untested on non-native modes, so ignore it for now.
9533 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9534 */
9535 pf = 0;
9536 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9537 intel_ring_emit(ring, pf | pipesrc);
9538
9539 intel_mark_page_flip_active(intel_crtc);
9540 __intel_ring_advance(ring);
9541 return 0;
9542 }
9543
9544 static int intel_gen6_queue_flip(struct drm_device *dev,
9545 struct drm_crtc *crtc,
9546 struct drm_framebuffer *fb,
9547 struct drm_i915_gem_object *obj,
9548 struct intel_engine_cs *ring,
9549 uint32_t flags)
9550 {
9551 struct drm_i915_private *dev_priv = dev->dev_private;
9552 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9553 uint32_t pf, pipesrc;
9554 int ret;
9555
9556 ret = intel_ring_begin(ring, 4);
9557 if (ret)
9558 return ret;
9559
9560 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9561 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9562 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9563 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9564
9565 /* Contrary to the suggestions in the documentation,
9566 * "Enable Panel Fitter" does not seem to be required when page
9567 * flipping with a non-native mode, and worse causes a normal
9568 * modeset to fail.
9569 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9570 */
9571 pf = 0;
9572 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9573 intel_ring_emit(ring, pf | pipesrc);
9574
9575 intel_mark_page_flip_active(intel_crtc);
9576 __intel_ring_advance(ring);
9577 return 0;
9578 }
9579
9580 static int intel_gen7_queue_flip(struct drm_device *dev,
9581 struct drm_crtc *crtc,
9582 struct drm_framebuffer *fb,
9583 struct drm_i915_gem_object *obj,
9584 struct intel_engine_cs *ring,
9585 uint32_t flags)
9586 {
9587 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9588 uint32_t plane_bit = 0;
9589 int len, ret;
9590
9591 switch (intel_crtc->plane) {
9592 case PLANE_A:
9593 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9594 break;
9595 case PLANE_B:
9596 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9597 break;
9598 case PLANE_C:
9599 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9600 break;
9601 default:
9602 WARN_ONCE(1, "unknown plane in flip command\n");
9603 return -ENODEV;
9604 }
9605
9606 len = 4;
9607 if (ring->id == RCS) {
9608 len += 6;
9609 /*
9610 * On Gen 8, SRM is now taking an extra dword to accommodate
9611 * 48bits addresses, and we need a NOOP for the batch size to
9612 * stay even.
9613 */
9614 if (IS_GEN8(dev))
9615 len += 2;
9616 }
9617
9618 /*
9619 * BSpec MI_DISPLAY_FLIP for IVB:
9620 * "The full packet must be contained within the same cache line."
9621 *
9622 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9623 * cacheline, if we ever start emitting more commands before
9624 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9625 * then do the cacheline alignment, and finally emit the
9626 * MI_DISPLAY_FLIP.
9627 */
9628 ret = intel_ring_cacheline_align(ring);
9629 if (ret)
9630 return ret;
9631
9632 ret = intel_ring_begin(ring, len);
9633 if (ret)
9634 return ret;
9635
9636 /* Unmask the flip-done completion message. Note that the bspec says that
9637 * we should do this for both the BCS and RCS, and that we must not unmask
9638 * more than one flip event at any time (or ensure that one flip message
9639 * can be sent by waiting for flip-done prior to queueing new flips).
9640 * Experimentation says that BCS works despite DERRMR masking all
9641 * flip-done completion events and that unmasking all planes at once
9642 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9643 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9644 */
9645 if (ring->id == RCS) {
9646 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9647 intel_ring_emit(ring, DERRMR);
9648 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9649 DERRMR_PIPEB_PRI_FLIP_DONE |
9650 DERRMR_PIPEC_PRI_FLIP_DONE));
9651 if (IS_GEN8(dev))
9652 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9653 MI_SRM_LRM_GLOBAL_GTT);
9654 else
9655 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9656 MI_SRM_LRM_GLOBAL_GTT);
9657 intel_ring_emit(ring, DERRMR);
9658 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9659 if (IS_GEN8(dev)) {
9660 intel_ring_emit(ring, 0);
9661 intel_ring_emit(ring, MI_NOOP);
9662 }
9663 }
9664
9665 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9666 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9667 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9668 intel_ring_emit(ring, (MI_NOOP));
9669
9670 intel_mark_page_flip_active(intel_crtc);
9671 __intel_ring_advance(ring);
9672 return 0;
9673 }
9674
9675 static bool use_mmio_flip(struct intel_engine_cs *ring,
9676 struct drm_i915_gem_object *obj)
9677 {
9678 /*
9679 * This is not being used for older platforms, because
9680 * non-availability of flip done interrupt forces us to use
9681 * CS flips. Older platforms derive flip done using some clever
9682 * tricks involving the flip_pending status bits and vblank irqs.
9683 * So using MMIO flips there would disrupt this mechanism.
9684 */
9685
9686 if (ring == NULL)
9687 return true;
9688
9689 if (INTEL_INFO(ring->dev)->gen < 5)
9690 return false;
9691
9692 if (i915.use_mmio_flip < 0)
9693 return false;
9694 else if (i915.use_mmio_flip > 0)
9695 return true;
9696 else if (i915.enable_execlists)
9697 return true;
9698 else
9699 return ring != i915_gem_request_get_ring(obj->last_read_req);
9700 }
9701
9702 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
9703 {
9704 struct drm_device *dev = intel_crtc->base.dev;
9705 struct drm_i915_private *dev_priv = dev->dev_private;
9706 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
9707 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9708 struct drm_i915_gem_object *obj = intel_fb->obj;
9709 const enum pipe pipe = intel_crtc->pipe;
9710 u32 ctl, stride;
9711
9712 ctl = I915_READ(PLANE_CTL(pipe, 0));
9713 ctl &= ~PLANE_CTL_TILED_MASK;
9714 if (obj->tiling_mode == I915_TILING_X)
9715 ctl |= PLANE_CTL_TILED_X;
9716
9717 /*
9718 * The stride is either expressed as a multiple of 64 bytes chunks for
9719 * linear buffers or in number of tiles for tiled buffers.
9720 */
9721 stride = fb->pitches[0] >> 6;
9722 if (obj->tiling_mode == I915_TILING_X)
9723 stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
9724
9725 /*
9726 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
9727 * PLANE_SURF updates, the update is then guaranteed to be atomic.
9728 */
9729 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
9730 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
9731
9732 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
9733 POSTING_READ(PLANE_SURF(pipe, 0));
9734 }
9735
9736 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
9737 {
9738 struct drm_device *dev = intel_crtc->base.dev;
9739 struct drm_i915_private *dev_priv = dev->dev_private;
9740 struct intel_framebuffer *intel_fb =
9741 to_intel_framebuffer(intel_crtc->base.primary->fb);
9742 struct drm_i915_gem_object *obj = intel_fb->obj;
9743 u32 dspcntr;
9744 u32 reg;
9745
9746 reg = DSPCNTR(intel_crtc->plane);
9747 dspcntr = I915_READ(reg);
9748
9749 if (obj->tiling_mode != I915_TILING_NONE)
9750 dspcntr |= DISPPLANE_TILED;
9751 else
9752 dspcntr &= ~DISPPLANE_TILED;
9753
9754 I915_WRITE(reg, dspcntr);
9755
9756 I915_WRITE(DSPSURF(intel_crtc->plane),
9757 intel_crtc->unpin_work->gtt_offset);
9758 POSTING_READ(DSPSURF(intel_crtc->plane));
9759
9760 }
9761
9762 /*
9763 * XXX: This is the temporary way to update the plane registers until we get
9764 * around to using the usual plane update functions for MMIO flips
9765 */
9766 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9767 {
9768 struct drm_device *dev = intel_crtc->base.dev;
9769 bool atomic_update;
9770 u32 start_vbl_count;
9771
9772 intel_mark_page_flip_active(intel_crtc);
9773
9774 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
9775
9776 if (INTEL_INFO(dev)->gen >= 9)
9777 skl_do_mmio_flip(intel_crtc);
9778 else
9779 /* use_mmio_flip() retricts MMIO flips to ilk+ */
9780 ilk_do_mmio_flip(intel_crtc);
9781
9782 if (atomic_update)
9783 intel_pipe_update_end(intel_crtc, start_vbl_count);
9784 }
9785
9786 static void intel_mmio_flip_work_func(struct work_struct *work)
9787 {
9788 struct intel_crtc *crtc =
9789 container_of(work, struct intel_crtc, mmio_flip.work);
9790 struct intel_mmio_flip *mmio_flip;
9791
9792 mmio_flip = &crtc->mmio_flip;
9793 if (mmio_flip->req)
9794 WARN_ON(__i915_wait_request(mmio_flip->req,
9795 crtc->reset_counter,
9796 false, NULL, NULL) != 0);
9797
9798 intel_do_mmio_flip(crtc);
9799 if (mmio_flip->req) {
9800 mutex_lock(&crtc->base.dev->struct_mutex);
9801 i915_gem_request_assign(&mmio_flip->req, NULL);
9802 mutex_unlock(&crtc->base.dev->struct_mutex);
9803 }
9804 }
9805
9806 static int intel_queue_mmio_flip(struct drm_device *dev,
9807 struct drm_crtc *crtc,
9808 struct drm_framebuffer *fb,
9809 struct drm_i915_gem_object *obj,
9810 struct intel_engine_cs *ring,
9811 uint32_t flags)
9812 {
9813 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9814
9815 i915_gem_request_assign(&intel_crtc->mmio_flip.req,
9816 obj->last_write_req);
9817
9818 schedule_work(&intel_crtc->mmio_flip.work);
9819
9820 return 0;
9821 }
9822
9823 static int intel_default_queue_flip(struct drm_device *dev,
9824 struct drm_crtc *crtc,
9825 struct drm_framebuffer *fb,
9826 struct drm_i915_gem_object *obj,
9827 struct intel_engine_cs *ring,
9828 uint32_t flags)
9829 {
9830 return -ENODEV;
9831 }
9832
9833 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9834 struct drm_crtc *crtc)
9835 {
9836 struct drm_i915_private *dev_priv = dev->dev_private;
9837 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9838 struct intel_unpin_work *work = intel_crtc->unpin_work;
9839 u32 addr;
9840
9841 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9842 return true;
9843
9844 if (!work->enable_stall_check)
9845 return false;
9846
9847 if (work->flip_ready_vblank == 0) {
9848 if (work->flip_queued_req &&
9849 !i915_gem_request_completed(work->flip_queued_req, true))
9850 return false;
9851
9852 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
9853 }
9854
9855 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
9856 return false;
9857
9858 /* Potential stall - if we see that the flip has happened,
9859 * assume a missed interrupt. */
9860 if (INTEL_INFO(dev)->gen >= 4)
9861 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9862 else
9863 addr = I915_READ(DSPADDR(intel_crtc->plane));
9864
9865 /* There is a potential issue here with a false positive after a flip
9866 * to the same address. We could address this by checking for a
9867 * non-incrementing frame counter.
9868 */
9869 return addr == work->gtt_offset;
9870 }
9871
9872 void intel_check_page_flip(struct drm_device *dev, int pipe)
9873 {
9874 struct drm_i915_private *dev_priv = dev->dev_private;
9875 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9876 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9877
9878 WARN_ON(!in_irq());
9879
9880 if (crtc == NULL)
9881 return;
9882
9883 spin_lock(&dev->event_lock);
9884 if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9885 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9886 intel_crtc->unpin_work->flip_queued_vblank,
9887 drm_vblank_count(dev, pipe));
9888 page_flip_completed(intel_crtc);
9889 }
9890 spin_unlock(&dev->event_lock);
9891 }
9892
9893 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9894 struct drm_framebuffer *fb,
9895 struct drm_pending_vblank_event *event,
9896 uint32_t page_flip_flags)
9897 {
9898 struct drm_device *dev = crtc->dev;
9899 struct drm_i915_private *dev_priv = dev->dev_private;
9900 struct drm_framebuffer *old_fb = crtc->primary->fb;
9901 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9902 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9903 struct drm_plane *primary = crtc->primary;
9904 enum pipe pipe = intel_crtc->pipe;
9905 struct intel_unpin_work *work;
9906 struct intel_engine_cs *ring;
9907 int ret;
9908
9909 /*
9910 * drm_mode_page_flip_ioctl() should already catch this, but double
9911 * check to be safe. In the future we may enable pageflipping from
9912 * a disabled primary plane.
9913 */
9914 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9915 return -EBUSY;
9916
9917 /* Can't change pixel format via MI display flips. */
9918 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9919 return -EINVAL;
9920
9921 /*
9922 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9923 * Note that pitch changes could also affect these register.
9924 */
9925 if (INTEL_INFO(dev)->gen > 3 &&
9926 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9927 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9928 return -EINVAL;
9929
9930 if (i915_terminally_wedged(&dev_priv->gpu_error))
9931 goto out_hang;
9932
9933 work = kzalloc(sizeof(*work), GFP_KERNEL);
9934 if (work == NULL)
9935 return -ENOMEM;
9936
9937 work->event = event;
9938 work->crtc = crtc;
9939 work->old_fb = old_fb;
9940 INIT_WORK(&work->work, intel_unpin_work_fn);
9941
9942 ret = drm_crtc_vblank_get(crtc);
9943 if (ret)
9944 goto free_work;
9945
9946 /* We borrow the event spin lock for protecting unpin_work */
9947 spin_lock_irq(&dev->event_lock);
9948 if (intel_crtc->unpin_work) {
9949 /* Before declaring the flip queue wedged, check if
9950 * the hardware completed the operation behind our backs.
9951 */
9952 if (__intel_pageflip_stall_check(dev, crtc)) {
9953 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9954 page_flip_completed(intel_crtc);
9955 } else {
9956 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9957 spin_unlock_irq(&dev->event_lock);
9958
9959 drm_crtc_vblank_put(crtc);
9960 kfree(work);
9961 return -EBUSY;
9962 }
9963 }
9964 intel_crtc->unpin_work = work;
9965 spin_unlock_irq(&dev->event_lock);
9966
9967 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9968 flush_workqueue(dev_priv->wq);
9969
9970 /* Reference the objects for the scheduled work. */
9971 drm_framebuffer_reference(work->old_fb);
9972 drm_gem_object_reference(&obj->base);
9973
9974 crtc->primary->fb = fb;
9975 update_state_fb(crtc->primary);
9976
9977 work->pending_flip_obj = obj;
9978
9979 ret = i915_mutex_lock_interruptible(dev);
9980 if (ret)
9981 goto cleanup;
9982
9983 atomic_inc(&intel_crtc->unpin_work_count);
9984 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9985
9986 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9987 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9988
9989 if (IS_VALLEYVIEW(dev)) {
9990 ring = &dev_priv->ring[BCS];
9991 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
9992 /* vlv: DISPLAY_FLIP fails to change tiling */
9993 ring = NULL;
9994 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
9995 ring = &dev_priv->ring[BCS];
9996 } else if (INTEL_INFO(dev)->gen >= 7) {
9997 ring = i915_gem_request_get_ring(obj->last_read_req);
9998 if (ring == NULL || ring->id != RCS)
9999 ring = &dev_priv->ring[BCS];
10000 } else {
10001 ring = &dev_priv->ring[RCS];
10002 }
10003
10004 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, ring);
10005 if (ret)
10006 goto cleanup_pending;
10007
10008 work->gtt_offset =
10009 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
10010
10011 if (use_mmio_flip(ring, obj)) {
10012 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
10013 page_flip_flags);
10014 if (ret)
10015 goto cleanup_unpin;
10016
10017 i915_gem_request_assign(&work->flip_queued_req,
10018 obj->last_write_req);
10019 } else {
10020 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
10021 page_flip_flags);
10022 if (ret)
10023 goto cleanup_unpin;
10024
10025 i915_gem_request_assign(&work->flip_queued_req,
10026 intel_ring_get_request(ring));
10027 }
10028
10029 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
10030 work->enable_stall_check = true;
10031
10032 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
10033 INTEL_FRONTBUFFER_PRIMARY(pipe));
10034
10035 intel_fbc_disable(dev);
10036 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
10037 mutex_unlock(&dev->struct_mutex);
10038
10039 trace_i915_flip_request(intel_crtc->plane, obj);
10040
10041 return 0;
10042
10043 cleanup_unpin:
10044 intel_unpin_fb_obj(obj);
10045 cleanup_pending:
10046 atomic_dec(&intel_crtc->unpin_work_count);
10047 mutex_unlock(&dev->struct_mutex);
10048 cleanup:
10049 crtc->primary->fb = old_fb;
10050 update_state_fb(crtc->primary);
10051
10052 drm_gem_object_unreference_unlocked(&obj->base);
10053 drm_framebuffer_unreference(work->old_fb);
10054
10055 spin_lock_irq(&dev->event_lock);
10056 intel_crtc->unpin_work = NULL;
10057 spin_unlock_irq(&dev->event_lock);
10058
10059 drm_crtc_vblank_put(crtc);
10060 free_work:
10061 kfree(work);
10062
10063 if (ret == -EIO) {
10064 out_hang:
10065 ret = intel_plane_restore(primary);
10066 if (ret == 0 && event) {
10067 spin_lock_irq(&dev->event_lock);
10068 drm_send_vblank_event(dev, pipe, event);
10069 spin_unlock_irq(&dev->event_lock);
10070 }
10071 }
10072 return ret;
10073 }
10074
10075 static struct drm_crtc_helper_funcs intel_helper_funcs = {
10076 .mode_set_base_atomic = intel_pipe_set_base_atomic,
10077 .load_lut = intel_crtc_load_lut,
10078 .atomic_begin = intel_begin_crtc_commit,
10079 .atomic_flush = intel_finish_crtc_commit,
10080 };
10081
10082 /**
10083 * intel_modeset_update_staged_output_state
10084 *
10085 * Updates the staged output configuration state, e.g. after we've read out the
10086 * current hw state.
10087 */
10088 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
10089 {
10090 struct intel_crtc *crtc;
10091 struct intel_encoder *encoder;
10092 struct intel_connector *connector;
10093
10094 for_each_intel_connector(dev, connector) {
10095 connector->new_encoder =
10096 to_intel_encoder(connector->base.encoder);
10097 }
10098
10099 for_each_intel_encoder(dev, encoder) {
10100 encoder->new_crtc =
10101 to_intel_crtc(encoder->base.crtc);
10102 }
10103
10104 for_each_intel_crtc(dev, crtc) {
10105 crtc->new_enabled = crtc->base.state->enable;
10106
10107 if (crtc->new_enabled)
10108 crtc->new_config = crtc->config;
10109 else
10110 crtc->new_config = NULL;
10111 }
10112 }
10113
10114 /**
10115 * intel_modeset_commit_output_state
10116 *
10117 * This function copies the stage display pipe configuration to the real one.
10118 */
10119 static void intel_modeset_commit_output_state(struct drm_device *dev)
10120 {
10121 struct intel_crtc *crtc;
10122 struct intel_encoder *encoder;
10123 struct intel_connector *connector;
10124
10125 for_each_intel_connector(dev, connector) {
10126 connector->base.encoder = &connector->new_encoder->base;
10127 }
10128
10129 for_each_intel_encoder(dev, encoder) {
10130 encoder->base.crtc = &encoder->new_crtc->base;
10131 }
10132
10133 for_each_intel_crtc(dev, crtc) {
10134 crtc->base.state->enable = crtc->new_enabled;
10135 crtc->base.enabled = crtc->new_enabled;
10136 }
10137 }
10138
10139 static void
10140 connected_sink_compute_bpp(struct intel_connector *connector,
10141 struct intel_crtc_state *pipe_config)
10142 {
10143 int bpp = pipe_config->pipe_bpp;
10144
10145 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10146 connector->base.base.id,
10147 connector->base.name);
10148
10149 /* Don't use an invalid EDID bpc value */
10150 if (connector->base.display_info.bpc &&
10151 connector->base.display_info.bpc * 3 < bpp) {
10152 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10153 bpp, connector->base.display_info.bpc*3);
10154 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
10155 }
10156
10157 /* Clamp bpp to 8 on screens without EDID 1.4 */
10158 if (connector->base.display_info.bpc == 0 && bpp > 24) {
10159 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10160 bpp);
10161 pipe_config->pipe_bpp = 24;
10162 }
10163 }
10164
10165 static int
10166 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10167 struct drm_framebuffer *fb,
10168 struct intel_crtc_state *pipe_config)
10169 {
10170 struct drm_device *dev = crtc->base.dev;
10171 struct intel_connector *connector;
10172 int bpp;
10173
10174 switch (fb->pixel_format) {
10175 case DRM_FORMAT_C8:
10176 bpp = 8*3; /* since we go through a colormap */
10177 break;
10178 case DRM_FORMAT_XRGB1555:
10179 case DRM_FORMAT_ARGB1555:
10180 /* checked in intel_framebuffer_init already */
10181 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10182 return -EINVAL;
10183 case DRM_FORMAT_RGB565:
10184 bpp = 6*3; /* min is 18bpp */
10185 break;
10186 case DRM_FORMAT_XBGR8888:
10187 case DRM_FORMAT_ABGR8888:
10188 /* checked in intel_framebuffer_init already */
10189 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10190 return -EINVAL;
10191 case DRM_FORMAT_XRGB8888:
10192 case DRM_FORMAT_ARGB8888:
10193 bpp = 8*3;
10194 break;
10195 case DRM_FORMAT_XRGB2101010:
10196 case DRM_FORMAT_ARGB2101010:
10197 case DRM_FORMAT_XBGR2101010:
10198 case DRM_FORMAT_ABGR2101010:
10199 /* checked in intel_framebuffer_init already */
10200 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10201 return -EINVAL;
10202 bpp = 10*3;
10203 break;
10204 /* TODO: gen4+ supports 16 bpc floating point, too. */
10205 default:
10206 DRM_DEBUG_KMS("unsupported depth\n");
10207 return -EINVAL;
10208 }
10209
10210 pipe_config->pipe_bpp = bpp;
10211
10212 /* Clamp display bpp to EDID value */
10213 for_each_intel_connector(dev, connector) {
10214 if (!connector->new_encoder ||
10215 connector->new_encoder->new_crtc != crtc)
10216 continue;
10217
10218 connected_sink_compute_bpp(connector, pipe_config);
10219 }
10220
10221 return bpp;
10222 }
10223
10224 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10225 {
10226 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10227 "type: 0x%x flags: 0x%x\n",
10228 mode->crtc_clock,
10229 mode->crtc_hdisplay, mode->crtc_hsync_start,
10230 mode->crtc_hsync_end, mode->crtc_htotal,
10231 mode->crtc_vdisplay, mode->crtc_vsync_start,
10232 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10233 }
10234
10235 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10236 struct intel_crtc_state *pipe_config,
10237 const char *context)
10238 {
10239 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10240 context, pipe_name(crtc->pipe));
10241
10242 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10243 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10244 pipe_config->pipe_bpp, pipe_config->dither);
10245 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10246 pipe_config->has_pch_encoder,
10247 pipe_config->fdi_lanes,
10248 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10249 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10250 pipe_config->fdi_m_n.tu);
10251 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10252 pipe_config->has_dp_encoder,
10253 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10254 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10255 pipe_config->dp_m_n.tu);
10256
10257 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10258 pipe_config->has_dp_encoder,
10259 pipe_config->dp_m2_n2.gmch_m,
10260 pipe_config->dp_m2_n2.gmch_n,
10261 pipe_config->dp_m2_n2.link_m,
10262 pipe_config->dp_m2_n2.link_n,
10263 pipe_config->dp_m2_n2.tu);
10264
10265 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10266 pipe_config->has_audio,
10267 pipe_config->has_infoframe);
10268
10269 DRM_DEBUG_KMS("requested mode:\n");
10270 drm_mode_debug_printmodeline(&pipe_config->base.mode);
10271 DRM_DEBUG_KMS("adjusted mode:\n");
10272 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10273 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10274 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10275 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10276 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10277 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10278 pipe_config->gmch_pfit.control,
10279 pipe_config->gmch_pfit.pgm_ratios,
10280 pipe_config->gmch_pfit.lvds_border_bits);
10281 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10282 pipe_config->pch_pfit.pos,
10283 pipe_config->pch_pfit.size,
10284 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10285 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10286 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10287 }
10288
10289 static bool encoders_cloneable(const struct intel_encoder *a,
10290 const struct intel_encoder *b)
10291 {
10292 /* masks could be asymmetric, so check both ways */
10293 return a == b || (a->cloneable & (1 << b->type) &&
10294 b->cloneable & (1 << a->type));
10295 }
10296
10297 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10298 struct intel_encoder *encoder)
10299 {
10300 struct drm_device *dev = crtc->base.dev;
10301 struct intel_encoder *source_encoder;
10302
10303 for_each_intel_encoder(dev, source_encoder) {
10304 if (source_encoder->new_crtc != crtc)
10305 continue;
10306
10307 if (!encoders_cloneable(encoder, source_encoder))
10308 return false;
10309 }
10310
10311 return true;
10312 }
10313
10314 static bool check_encoder_cloning(struct intel_crtc *crtc)
10315 {
10316 struct drm_device *dev = crtc->base.dev;
10317 struct intel_encoder *encoder;
10318
10319 for_each_intel_encoder(dev, encoder) {
10320 if (encoder->new_crtc != crtc)
10321 continue;
10322
10323 if (!check_single_encoder_cloning(crtc, encoder))
10324 return false;
10325 }
10326
10327 return true;
10328 }
10329
10330 static bool check_digital_port_conflicts(struct drm_device *dev)
10331 {
10332 struct intel_connector *connector;
10333 unsigned int used_ports = 0;
10334
10335 /*
10336 * Walk the connector list instead of the encoder
10337 * list to detect the problem on ddi platforms
10338 * where there's just one encoder per digital port.
10339 */
10340 for_each_intel_connector(dev, connector) {
10341 struct intel_encoder *encoder = connector->new_encoder;
10342
10343 if (!encoder)
10344 continue;
10345
10346 WARN_ON(!encoder->new_crtc);
10347
10348 switch (encoder->type) {
10349 unsigned int port_mask;
10350 case INTEL_OUTPUT_UNKNOWN:
10351 if (WARN_ON(!HAS_DDI(dev)))
10352 break;
10353 case INTEL_OUTPUT_DISPLAYPORT:
10354 case INTEL_OUTPUT_HDMI:
10355 case INTEL_OUTPUT_EDP:
10356 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10357
10358 /* the same port mustn't appear more than once */
10359 if (used_ports & port_mask)
10360 return false;
10361
10362 used_ports |= port_mask;
10363 default:
10364 break;
10365 }
10366 }
10367
10368 return true;
10369 }
10370
10371 static struct intel_crtc_state *
10372 intel_modeset_pipe_config(struct drm_crtc *crtc,
10373 struct drm_framebuffer *fb,
10374 struct drm_display_mode *mode)
10375 {
10376 struct drm_device *dev = crtc->dev;
10377 struct intel_encoder *encoder;
10378 struct intel_crtc_state *pipe_config;
10379 int plane_bpp, ret = -EINVAL;
10380 bool retry = true;
10381
10382 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10383 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10384 return ERR_PTR(-EINVAL);
10385 }
10386
10387 if (!check_digital_port_conflicts(dev)) {
10388 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
10389 return ERR_PTR(-EINVAL);
10390 }
10391
10392 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10393 if (!pipe_config)
10394 return ERR_PTR(-ENOMEM);
10395
10396 pipe_config->base.crtc = crtc;
10397 drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
10398 drm_mode_copy(&pipe_config->base.mode, mode);
10399
10400 pipe_config->cpu_transcoder =
10401 (enum transcoder) to_intel_crtc(crtc)->pipe;
10402 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10403
10404 /*
10405 * Sanitize sync polarity flags based on requested ones. If neither
10406 * positive or negative polarity is requested, treat this as meaning
10407 * negative polarity.
10408 */
10409 if (!(pipe_config->base.adjusted_mode.flags &
10410 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10411 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10412
10413 if (!(pipe_config->base.adjusted_mode.flags &
10414 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10415 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10416
10417 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10418 * plane pixel format and any sink constraints into account. Returns the
10419 * source plane bpp so that dithering can be selected on mismatches
10420 * after encoders and crtc also have had their say. */
10421 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10422 fb, pipe_config);
10423 if (plane_bpp < 0)
10424 goto fail;
10425
10426 /*
10427 * Determine the real pipe dimensions. Note that stereo modes can
10428 * increase the actual pipe size due to the frame doubling and
10429 * insertion of additional space for blanks between the frame. This
10430 * is stored in the crtc timings. We use the requested mode to do this
10431 * computation to clearly distinguish it from the adjusted mode, which
10432 * can be changed by the connectors in the below retry loop.
10433 */
10434 drm_crtc_get_hv_timing(&pipe_config->base.mode,
10435 &pipe_config->pipe_src_w,
10436 &pipe_config->pipe_src_h);
10437
10438 encoder_retry:
10439 /* Ensure the port clock defaults are reset when retrying. */
10440 pipe_config->port_clock = 0;
10441 pipe_config->pixel_multiplier = 1;
10442
10443 /* Fill in default crtc timings, allow encoders to overwrite them. */
10444 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10445 CRTC_STEREO_DOUBLE);
10446
10447 /* Pass our mode to the connectors and the CRTC to give them a chance to
10448 * adjust it according to limitations or connector properties, and also
10449 * a chance to reject the mode entirely.
10450 */
10451 for_each_intel_encoder(dev, encoder) {
10452
10453 if (&encoder->new_crtc->base != crtc)
10454 continue;
10455
10456 if (!(encoder->compute_config(encoder, pipe_config))) {
10457 DRM_DEBUG_KMS("Encoder config failure\n");
10458 goto fail;
10459 }
10460 }
10461
10462 /* Set default port clock if not overwritten by the encoder. Needs to be
10463 * done afterwards in case the encoder adjusts the mode. */
10464 if (!pipe_config->port_clock)
10465 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
10466 * pipe_config->pixel_multiplier;
10467
10468 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10469 if (ret < 0) {
10470 DRM_DEBUG_KMS("CRTC fixup failed\n");
10471 goto fail;
10472 }
10473
10474 if (ret == RETRY) {
10475 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10476 ret = -EINVAL;
10477 goto fail;
10478 }
10479
10480 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10481 retry = false;
10482 goto encoder_retry;
10483 }
10484
10485 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10486 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10487 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10488
10489 return pipe_config;
10490 fail:
10491 kfree(pipe_config);
10492 return ERR_PTR(ret);
10493 }
10494
10495 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10496 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10497 static void
10498 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10499 unsigned *prepare_pipes, unsigned *disable_pipes)
10500 {
10501 struct intel_crtc *intel_crtc;
10502 struct drm_device *dev = crtc->dev;
10503 struct intel_encoder *encoder;
10504 struct intel_connector *connector;
10505 struct drm_crtc *tmp_crtc;
10506
10507 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10508
10509 /* Check which crtcs have changed outputs connected to them, these need
10510 * to be part of the prepare_pipes mask. We don't (yet) support global
10511 * modeset across multiple crtcs, so modeset_pipes will only have one
10512 * bit set at most. */
10513 for_each_intel_connector(dev, connector) {
10514 if (connector->base.encoder == &connector->new_encoder->base)
10515 continue;
10516
10517 if (connector->base.encoder) {
10518 tmp_crtc = connector->base.encoder->crtc;
10519
10520 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10521 }
10522
10523 if (connector->new_encoder)
10524 *prepare_pipes |=
10525 1 << connector->new_encoder->new_crtc->pipe;
10526 }
10527
10528 for_each_intel_encoder(dev, encoder) {
10529 if (encoder->base.crtc == &encoder->new_crtc->base)
10530 continue;
10531
10532 if (encoder->base.crtc) {
10533 tmp_crtc = encoder->base.crtc;
10534
10535 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10536 }
10537
10538 if (encoder->new_crtc)
10539 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10540 }
10541
10542 /* Check for pipes that will be enabled/disabled ... */
10543 for_each_intel_crtc(dev, intel_crtc) {
10544 if (intel_crtc->base.state->enable == intel_crtc->new_enabled)
10545 continue;
10546
10547 if (!intel_crtc->new_enabled)
10548 *disable_pipes |= 1 << intel_crtc->pipe;
10549 else
10550 *prepare_pipes |= 1 << intel_crtc->pipe;
10551 }
10552
10553
10554 /* set_mode is also used to update properties on life display pipes. */
10555 intel_crtc = to_intel_crtc(crtc);
10556 if (intel_crtc->new_enabled)
10557 *prepare_pipes |= 1 << intel_crtc->pipe;
10558
10559 /*
10560 * For simplicity do a full modeset on any pipe where the output routing
10561 * changed. We could be more clever, but that would require us to be
10562 * more careful with calling the relevant encoder->mode_set functions.
10563 */
10564 if (*prepare_pipes)
10565 *modeset_pipes = *prepare_pipes;
10566
10567 /* ... and mask these out. */
10568 *modeset_pipes &= ~(*disable_pipes);
10569 *prepare_pipes &= ~(*disable_pipes);
10570
10571 /*
10572 * HACK: We don't (yet) fully support global modesets. intel_set_config
10573 * obies this rule, but the modeset restore mode of
10574 * intel_modeset_setup_hw_state does not.
10575 */
10576 *modeset_pipes &= 1 << intel_crtc->pipe;
10577 *prepare_pipes &= 1 << intel_crtc->pipe;
10578
10579 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10580 *modeset_pipes, *prepare_pipes, *disable_pipes);
10581 }
10582
10583 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10584 {
10585 struct drm_encoder *encoder;
10586 struct drm_device *dev = crtc->dev;
10587
10588 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10589 if (encoder->crtc == crtc)
10590 return true;
10591
10592 return false;
10593 }
10594
10595 static void
10596 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10597 {
10598 struct drm_i915_private *dev_priv = dev->dev_private;
10599 struct intel_encoder *intel_encoder;
10600 struct intel_crtc *intel_crtc;
10601 struct drm_connector *connector;
10602
10603 intel_shared_dpll_commit(dev_priv);
10604
10605 for_each_intel_encoder(dev, intel_encoder) {
10606 if (!intel_encoder->base.crtc)
10607 continue;
10608
10609 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10610
10611 if (prepare_pipes & (1 << intel_crtc->pipe))
10612 intel_encoder->connectors_active = false;
10613 }
10614
10615 intel_modeset_commit_output_state(dev);
10616
10617 /* Double check state. */
10618 for_each_intel_crtc(dev, intel_crtc) {
10619 WARN_ON(intel_crtc->base.state->enable != intel_crtc_in_use(&intel_crtc->base));
10620 WARN_ON(intel_crtc->new_config &&
10621 intel_crtc->new_config != intel_crtc->config);
10622 WARN_ON(intel_crtc->base.state->enable != !!intel_crtc->new_config);
10623 }
10624
10625 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10626 if (!connector->encoder || !connector->encoder->crtc)
10627 continue;
10628
10629 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10630
10631 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10632 struct drm_property *dpms_property =
10633 dev->mode_config.dpms_property;
10634
10635 connector->dpms = DRM_MODE_DPMS_ON;
10636 drm_object_property_set_value(&connector->base,
10637 dpms_property,
10638 DRM_MODE_DPMS_ON);
10639
10640 intel_encoder = to_intel_encoder(connector->encoder);
10641 intel_encoder->connectors_active = true;
10642 }
10643 }
10644
10645 }
10646
10647 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10648 {
10649 int diff;
10650
10651 if (clock1 == clock2)
10652 return true;
10653
10654 if (!clock1 || !clock2)
10655 return false;
10656
10657 diff = abs(clock1 - clock2);
10658
10659 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10660 return true;
10661
10662 return false;
10663 }
10664
10665 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10666 list_for_each_entry((intel_crtc), \
10667 &(dev)->mode_config.crtc_list, \
10668 base.head) \
10669 if (mask & (1 <<(intel_crtc)->pipe))
10670
10671 static bool
10672 intel_pipe_config_compare(struct drm_device *dev,
10673 struct intel_crtc_state *current_config,
10674 struct intel_crtc_state *pipe_config)
10675 {
10676 #define PIPE_CONF_CHECK_X(name) \
10677 if (current_config->name != pipe_config->name) { \
10678 DRM_ERROR("mismatch in " #name " " \
10679 "(expected 0x%08x, found 0x%08x)\n", \
10680 current_config->name, \
10681 pipe_config->name); \
10682 return false; \
10683 }
10684
10685 #define PIPE_CONF_CHECK_I(name) \
10686 if (current_config->name != pipe_config->name) { \
10687 DRM_ERROR("mismatch in " #name " " \
10688 "(expected %i, found %i)\n", \
10689 current_config->name, \
10690 pipe_config->name); \
10691 return false; \
10692 }
10693
10694 /* This is required for BDW+ where there is only one set of registers for
10695 * switching between high and low RR.
10696 * This macro can be used whenever a comparison has to be made between one
10697 * hw state and multiple sw state variables.
10698 */
10699 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10700 if ((current_config->name != pipe_config->name) && \
10701 (current_config->alt_name != pipe_config->name)) { \
10702 DRM_ERROR("mismatch in " #name " " \
10703 "(expected %i or %i, found %i)\n", \
10704 current_config->name, \
10705 current_config->alt_name, \
10706 pipe_config->name); \
10707 return false; \
10708 }
10709
10710 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10711 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10712 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10713 "(expected %i, found %i)\n", \
10714 current_config->name & (mask), \
10715 pipe_config->name & (mask)); \
10716 return false; \
10717 }
10718
10719 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10720 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10721 DRM_ERROR("mismatch in " #name " " \
10722 "(expected %i, found %i)\n", \
10723 current_config->name, \
10724 pipe_config->name); \
10725 return false; \
10726 }
10727
10728 #define PIPE_CONF_QUIRK(quirk) \
10729 ((current_config->quirks | pipe_config->quirks) & (quirk))
10730
10731 PIPE_CONF_CHECK_I(cpu_transcoder);
10732
10733 PIPE_CONF_CHECK_I(has_pch_encoder);
10734 PIPE_CONF_CHECK_I(fdi_lanes);
10735 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10736 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10737 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10738 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10739 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10740
10741 PIPE_CONF_CHECK_I(has_dp_encoder);
10742
10743 if (INTEL_INFO(dev)->gen < 8) {
10744 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10745 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10746 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10747 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10748 PIPE_CONF_CHECK_I(dp_m_n.tu);
10749
10750 if (current_config->has_drrs) {
10751 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10752 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10753 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10754 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10755 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10756 }
10757 } else {
10758 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10759 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10760 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10761 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10762 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10763 }
10764
10765 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
10766 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
10767 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
10768 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
10769 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
10770 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
10771
10772 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
10773 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
10774 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
10775 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
10776 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
10777 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
10778
10779 PIPE_CONF_CHECK_I(pixel_multiplier);
10780 PIPE_CONF_CHECK_I(has_hdmi_sink);
10781 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10782 IS_VALLEYVIEW(dev))
10783 PIPE_CONF_CHECK_I(limited_color_range);
10784 PIPE_CONF_CHECK_I(has_infoframe);
10785
10786 PIPE_CONF_CHECK_I(has_audio);
10787
10788 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10789 DRM_MODE_FLAG_INTERLACE);
10790
10791 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10792 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10793 DRM_MODE_FLAG_PHSYNC);
10794 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10795 DRM_MODE_FLAG_NHSYNC);
10796 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10797 DRM_MODE_FLAG_PVSYNC);
10798 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10799 DRM_MODE_FLAG_NVSYNC);
10800 }
10801
10802 PIPE_CONF_CHECK_I(pipe_src_w);
10803 PIPE_CONF_CHECK_I(pipe_src_h);
10804
10805 /*
10806 * FIXME: BIOS likes to set up a cloned config with lvds+external
10807 * screen. Since we don't yet re-compute the pipe config when moving
10808 * just the lvds port away to another pipe the sw tracking won't match.
10809 *
10810 * Proper atomic modesets with recomputed global state will fix this.
10811 * Until then just don't check gmch state for inherited modes.
10812 */
10813 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10814 PIPE_CONF_CHECK_I(gmch_pfit.control);
10815 /* pfit ratios are autocomputed by the hw on gen4+ */
10816 if (INTEL_INFO(dev)->gen < 4)
10817 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10818 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10819 }
10820
10821 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10822 if (current_config->pch_pfit.enabled) {
10823 PIPE_CONF_CHECK_I(pch_pfit.pos);
10824 PIPE_CONF_CHECK_I(pch_pfit.size);
10825 }
10826
10827 /* BDW+ don't expose a synchronous way to read the state */
10828 if (IS_HASWELL(dev))
10829 PIPE_CONF_CHECK_I(ips_enabled);
10830
10831 PIPE_CONF_CHECK_I(double_wide);
10832
10833 PIPE_CONF_CHECK_X(ddi_pll_sel);
10834
10835 PIPE_CONF_CHECK_I(shared_dpll);
10836 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10837 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10838 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10839 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10840 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10841 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
10842 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
10843 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
10844
10845 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10846 PIPE_CONF_CHECK_I(pipe_bpp);
10847
10848 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
10849 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10850
10851 #undef PIPE_CONF_CHECK_X
10852 #undef PIPE_CONF_CHECK_I
10853 #undef PIPE_CONF_CHECK_I_ALT
10854 #undef PIPE_CONF_CHECK_FLAGS
10855 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10856 #undef PIPE_CONF_QUIRK
10857
10858 return true;
10859 }
10860
10861 static void check_wm_state(struct drm_device *dev)
10862 {
10863 struct drm_i915_private *dev_priv = dev->dev_private;
10864 struct skl_ddb_allocation hw_ddb, *sw_ddb;
10865 struct intel_crtc *intel_crtc;
10866 int plane;
10867
10868 if (INTEL_INFO(dev)->gen < 9)
10869 return;
10870
10871 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
10872 sw_ddb = &dev_priv->wm.skl_hw.ddb;
10873
10874 for_each_intel_crtc(dev, intel_crtc) {
10875 struct skl_ddb_entry *hw_entry, *sw_entry;
10876 const enum pipe pipe = intel_crtc->pipe;
10877
10878 if (!intel_crtc->active)
10879 continue;
10880
10881 /* planes */
10882 for_each_plane(dev_priv, pipe, plane) {
10883 hw_entry = &hw_ddb.plane[pipe][plane];
10884 sw_entry = &sw_ddb->plane[pipe][plane];
10885
10886 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10887 continue;
10888
10889 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
10890 "(expected (%u,%u), found (%u,%u))\n",
10891 pipe_name(pipe), plane + 1,
10892 sw_entry->start, sw_entry->end,
10893 hw_entry->start, hw_entry->end);
10894 }
10895
10896 /* cursor */
10897 hw_entry = &hw_ddb.cursor[pipe];
10898 sw_entry = &sw_ddb->cursor[pipe];
10899
10900 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10901 continue;
10902
10903 DRM_ERROR("mismatch in DDB state pipe %c cursor "
10904 "(expected (%u,%u), found (%u,%u))\n",
10905 pipe_name(pipe),
10906 sw_entry->start, sw_entry->end,
10907 hw_entry->start, hw_entry->end);
10908 }
10909 }
10910
10911 static void
10912 check_connector_state(struct drm_device *dev)
10913 {
10914 struct intel_connector *connector;
10915
10916 for_each_intel_connector(dev, connector) {
10917 /* This also checks the encoder/connector hw state with the
10918 * ->get_hw_state callbacks. */
10919 intel_connector_check_state(connector);
10920
10921 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
10922 "connector's staged encoder doesn't match current encoder\n");
10923 }
10924 }
10925
10926 static void
10927 check_encoder_state(struct drm_device *dev)
10928 {
10929 struct intel_encoder *encoder;
10930 struct intel_connector *connector;
10931
10932 for_each_intel_encoder(dev, encoder) {
10933 bool enabled = false;
10934 bool active = false;
10935 enum pipe pipe, tracked_pipe;
10936
10937 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10938 encoder->base.base.id,
10939 encoder->base.name);
10940
10941 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
10942 "encoder's stage crtc doesn't match current crtc\n");
10943 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
10944 "encoder's active_connectors set, but no crtc\n");
10945
10946 for_each_intel_connector(dev, connector) {
10947 if (connector->base.encoder != &encoder->base)
10948 continue;
10949 enabled = true;
10950 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10951 active = true;
10952 }
10953 /*
10954 * for MST connectors if we unplug the connector is gone
10955 * away but the encoder is still connected to a crtc
10956 * until a modeset happens in response to the hotplug.
10957 */
10958 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10959 continue;
10960
10961 I915_STATE_WARN(!!encoder->base.crtc != enabled,
10962 "encoder's enabled state mismatch "
10963 "(expected %i, found %i)\n",
10964 !!encoder->base.crtc, enabled);
10965 I915_STATE_WARN(active && !encoder->base.crtc,
10966 "active encoder with no crtc\n");
10967
10968 I915_STATE_WARN(encoder->connectors_active != active,
10969 "encoder's computed active state doesn't match tracked active state "
10970 "(expected %i, found %i)\n", active, encoder->connectors_active);
10971
10972 active = encoder->get_hw_state(encoder, &pipe);
10973 I915_STATE_WARN(active != encoder->connectors_active,
10974 "encoder's hw state doesn't match sw tracking "
10975 "(expected %i, found %i)\n",
10976 encoder->connectors_active, active);
10977
10978 if (!encoder->base.crtc)
10979 continue;
10980
10981 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10982 I915_STATE_WARN(active && pipe != tracked_pipe,
10983 "active encoder's pipe doesn't match"
10984 "(expected %i, found %i)\n",
10985 tracked_pipe, pipe);
10986
10987 }
10988 }
10989
10990 static void
10991 check_crtc_state(struct drm_device *dev)
10992 {
10993 struct drm_i915_private *dev_priv = dev->dev_private;
10994 struct intel_crtc *crtc;
10995 struct intel_encoder *encoder;
10996 struct intel_crtc_state pipe_config;
10997
10998 for_each_intel_crtc(dev, crtc) {
10999 bool enabled = false;
11000 bool active = false;
11001
11002 memset(&pipe_config, 0, sizeof(pipe_config));
11003
11004 DRM_DEBUG_KMS("[CRTC:%d]\n",
11005 crtc->base.base.id);
11006
11007 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
11008 "active crtc, but not enabled in sw tracking\n");
11009
11010 for_each_intel_encoder(dev, encoder) {
11011 if (encoder->base.crtc != &crtc->base)
11012 continue;
11013 enabled = true;
11014 if (encoder->connectors_active)
11015 active = true;
11016 }
11017
11018 I915_STATE_WARN(active != crtc->active,
11019 "crtc's computed active state doesn't match tracked active state "
11020 "(expected %i, found %i)\n", active, crtc->active);
11021 I915_STATE_WARN(enabled != crtc->base.state->enable,
11022 "crtc's computed enabled state doesn't match tracked enabled state "
11023 "(expected %i, found %i)\n", enabled,
11024 crtc->base.state->enable);
11025
11026 active = dev_priv->display.get_pipe_config(crtc,
11027 &pipe_config);
11028
11029 /* hw state is inconsistent with the pipe quirk */
11030 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
11031 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
11032 active = crtc->active;
11033
11034 for_each_intel_encoder(dev, encoder) {
11035 enum pipe pipe;
11036 if (encoder->base.crtc != &crtc->base)
11037 continue;
11038 if (encoder->get_hw_state(encoder, &pipe))
11039 encoder->get_config(encoder, &pipe_config);
11040 }
11041
11042 I915_STATE_WARN(crtc->active != active,
11043 "crtc active state doesn't match with hw state "
11044 "(expected %i, found %i)\n", crtc->active, active);
11045
11046 if (active &&
11047 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
11048 I915_STATE_WARN(1, "pipe state doesn't match!\n");
11049 intel_dump_pipe_config(crtc, &pipe_config,
11050 "[hw state]");
11051 intel_dump_pipe_config(crtc, crtc->config,
11052 "[sw state]");
11053 }
11054 }
11055 }
11056
11057 static void
11058 check_shared_dpll_state(struct drm_device *dev)
11059 {
11060 struct drm_i915_private *dev_priv = dev->dev_private;
11061 struct intel_crtc *crtc;
11062 struct intel_dpll_hw_state dpll_hw_state;
11063 int i;
11064
11065 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11066 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11067 int enabled_crtcs = 0, active_crtcs = 0;
11068 bool active;
11069
11070 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11071
11072 DRM_DEBUG_KMS("%s\n", pll->name);
11073
11074 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
11075
11076 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
11077 "more active pll users than references: %i vs %i\n",
11078 pll->active, hweight32(pll->config.crtc_mask));
11079 I915_STATE_WARN(pll->active && !pll->on,
11080 "pll in active use but not on in sw tracking\n");
11081 I915_STATE_WARN(pll->on && !pll->active,
11082 "pll in on but not on in use in sw tracking\n");
11083 I915_STATE_WARN(pll->on != active,
11084 "pll on state mismatch (expected %i, found %i)\n",
11085 pll->on, active);
11086
11087 for_each_intel_crtc(dev, crtc) {
11088 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
11089 enabled_crtcs++;
11090 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11091 active_crtcs++;
11092 }
11093 I915_STATE_WARN(pll->active != active_crtcs,
11094 "pll active crtcs mismatch (expected %i, found %i)\n",
11095 pll->active, active_crtcs);
11096 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
11097 "pll enabled crtcs mismatch (expected %i, found %i)\n",
11098 hweight32(pll->config.crtc_mask), enabled_crtcs);
11099
11100 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
11101 sizeof(dpll_hw_state)),
11102 "pll hw state mismatch\n");
11103 }
11104 }
11105
11106 void
11107 intel_modeset_check_state(struct drm_device *dev)
11108 {
11109 check_wm_state(dev);
11110 check_connector_state(dev);
11111 check_encoder_state(dev);
11112 check_crtc_state(dev);
11113 check_shared_dpll_state(dev);
11114 }
11115
11116 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
11117 int dotclock)
11118 {
11119 /*
11120 * FDI already provided one idea for the dotclock.
11121 * Yell if the encoder disagrees.
11122 */
11123 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
11124 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11125 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
11126 }
11127
11128 static void update_scanline_offset(struct intel_crtc *crtc)
11129 {
11130 struct drm_device *dev = crtc->base.dev;
11131
11132 /*
11133 * The scanline counter increments at the leading edge of hsync.
11134 *
11135 * On most platforms it starts counting from vtotal-1 on the
11136 * first active line. That means the scanline counter value is
11137 * always one less than what we would expect. Ie. just after
11138 * start of vblank, which also occurs at start of hsync (on the
11139 * last active line), the scanline counter will read vblank_start-1.
11140 *
11141 * On gen2 the scanline counter starts counting from 1 instead
11142 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11143 * to keep the value positive), instead of adding one.
11144 *
11145 * On HSW+ the behaviour of the scanline counter depends on the output
11146 * type. For DP ports it behaves like most other platforms, but on HDMI
11147 * there's an extra 1 line difference. So we need to add two instead of
11148 * one to the value.
11149 */
11150 if (IS_GEN2(dev)) {
11151 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
11152 int vtotal;
11153
11154 vtotal = mode->crtc_vtotal;
11155 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
11156 vtotal /= 2;
11157
11158 crtc->scanline_offset = vtotal - 1;
11159 } else if (HAS_DDI(dev) &&
11160 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
11161 crtc->scanline_offset = 2;
11162 } else
11163 crtc->scanline_offset = 1;
11164 }
11165
11166 static struct intel_crtc_state *
11167 intel_modeset_compute_config(struct drm_crtc *crtc,
11168 struct drm_display_mode *mode,
11169 struct drm_framebuffer *fb,
11170 unsigned *modeset_pipes,
11171 unsigned *prepare_pipes,
11172 unsigned *disable_pipes)
11173 {
11174 struct intel_crtc_state *pipe_config = NULL;
11175
11176 intel_modeset_affected_pipes(crtc, modeset_pipes,
11177 prepare_pipes, disable_pipes);
11178
11179 if ((*modeset_pipes) == 0)
11180 goto out;
11181
11182 /*
11183 * Note this needs changes when we start tracking multiple modes
11184 * and crtcs. At that point we'll need to compute the whole config
11185 * (i.e. one pipe_config for each crtc) rather than just the one
11186 * for this crtc.
11187 */
11188 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
11189 if (IS_ERR(pipe_config)) {
11190 goto out;
11191 }
11192 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11193 "[modeset]");
11194
11195 out:
11196 return pipe_config;
11197 }
11198
11199 static int __intel_set_mode_setup_plls(struct drm_device *dev,
11200 unsigned modeset_pipes,
11201 unsigned disable_pipes)
11202 {
11203 struct drm_i915_private *dev_priv = to_i915(dev);
11204 unsigned clear_pipes = modeset_pipes | disable_pipes;
11205 struct intel_crtc *intel_crtc;
11206 int ret = 0;
11207
11208 if (!dev_priv->display.crtc_compute_clock)
11209 return 0;
11210
11211 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
11212 if (ret)
11213 goto done;
11214
11215 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11216 struct intel_crtc_state *state = intel_crtc->new_config;
11217 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11218 state);
11219 if (ret) {
11220 intel_shared_dpll_abort_config(dev_priv);
11221 goto done;
11222 }
11223 }
11224
11225 done:
11226 return ret;
11227 }
11228
11229 static int __intel_set_mode(struct drm_crtc *crtc,
11230 struct drm_display_mode *mode,
11231 int x, int y, struct drm_framebuffer *fb,
11232 struct intel_crtc_state *pipe_config,
11233 unsigned modeset_pipes,
11234 unsigned prepare_pipes,
11235 unsigned disable_pipes)
11236 {
11237 struct drm_device *dev = crtc->dev;
11238 struct drm_i915_private *dev_priv = dev->dev_private;
11239 struct drm_display_mode *saved_mode;
11240 struct intel_crtc *intel_crtc;
11241 int ret = 0;
11242
11243 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
11244 if (!saved_mode)
11245 return -ENOMEM;
11246
11247 *saved_mode = crtc->mode;
11248
11249 if (modeset_pipes)
11250 to_intel_crtc(crtc)->new_config = pipe_config;
11251
11252 /*
11253 * See if the config requires any additional preparation, e.g.
11254 * to adjust global state with pipes off. We need to do this
11255 * here so we can get the modeset_pipe updated config for the new
11256 * mode set on this crtc. For other crtcs we need to use the
11257 * adjusted_mode bits in the crtc directly.
11258 */
11259 if (IS_VALLEYVIEW(dev)) {
11260 valleyview_modeset_global_pipes(dev, &prepare_pipes);
11261
11262 /* may have added more to prepare_pipes than we should */
11263 prepare_pipes &= ~disable_pipes;
11264 }
11265
11266 ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes);
11267 if (ret)
11268 goto done;
11269
11270 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
11271 intel_crtc_disable(&intel_crtc->base);
11272
11273 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11274 if (intel_crtc->base.state->enable)
11275 dev_priv->display.crtc_disable(&intel_crtc->base);
11276 }
11277
11278 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11279 * to set it here already despite that we pass it down the callchain.
11280 *
11281 * Note we'll need to fix this up when we start tracking multiple
11282 * pipes; here we assume a single modeset_pipe and only track the
11283 * single crtc and mode.
11284 */
11285 if (modeset_pipes) {
11286 crtc->mode = *mode;
11287 /* mode_set/enable/disable functions rely on a correct pipe
11288 * config. */
11289 intel_crtc_set_state(to_intel_crtc(crtc), pipe_config);
11290
11291 /*
11292 * Calculate and store various constants which
11293 * are later needed by vblank and swap-completion
11294 * timestamping. They are derived from true hwmode.
11295 */
11296 drm_calc_timestamping_constants(crtc,
11297 &pipe_config->base.adjusted_mode);
11298 }
11299
11300 /* Only after disabling all output pipelines that will be changed can we
11301 * update the the output configuration. */
11302 intel_modeset_update_state(dev, prepare_pipes);
11303
11304 modeset_update_crtc_power_domains(dev);
11305
11306 /* Set up the DPLL and any encoders state that needs to adjust or depend
11307 * on the DPLL.
11308 */
11309 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11310 struct drm_plane *primary = intel_crtc->base.primary;
11311 int vdisplay, hdisplay;
11312
11313 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11314 ret = primary->funcs->update_plane(primary, &intel_crtc->base,
11315 fb, 0, 0,
11316 hdisplay, vdisplay,
11317 x << 16, y << 16,
11318 hdisplay << 16, vdisplay << 16);
11319 }
11320
11321 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11322 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11323 update_scanline_offset(intel_crtc);
11324
11325 dev_priv->display.crtc_enable(&intel_crtc->base);
11326 }
11327
11328 /* FIXME: add subpixel order */
11329 done:
11330 if (ret && crtc->state->enable)
11331 crtc->mode = *saved_mode;
11332
11333 kfree(saved_mode);
11334 return ret;
11335 }
11336
11337 static int intel_set_mode_pipes(struct drm_crtc *crtc,
11338 struct drm_display_mode *mode,
11339 int x, int y, struct drm_framebuffer *fb,
11340 struct intel_crtc_state *pipe_config,
11341 unsigned modeset_pipes,
11342 unsigned prepare_pipes,
11343 unsigned disable_pipes)
11344 {
11345 int ret;
11346
11347 ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
11348 prepare_pipes, disable_pipes);
11349
11350 if (ret == 0)
11351 intel_modeset_check_state(crtc->dev);
11352
11353 return ret;
11354 }
11355
11356 static int intel_set_mode(struct drm_crtc *crtc,
11357 struct drm_display_mode *mode,
11358 int x, int y, struct drm_framebuffer *fb)
11359 {
11360 struct intel_crtc_state *pipe_config;
11361 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11362
11363 pipe_config = intel_modeset_compute_config(crtc, mode, fb,
11364 &modeset_pipes,
11365 &prepare_pipes,
11366 &disable_pipes);
11367
11368 if (IS_ERR(pipe_config))
11369 return PTR_ERR(pipe_config);
11370
11371 return intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
11372 modeset_pipes, prepare_pipes,
11373 disable_pipes);
11374 }
11375
11376 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11377 {
11378 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
11379 }
11380
11381 #undef for_each_intel_crtc_masked
11382
11383 static void intel_set_config_free(struct intel_set_config *config)
11384 {
11385 if (!config)
11386 return;
11387
11388 kfree(config->save_connector_encoders);
11389 kfree(config->save_encoder_crtcs);
11390 kfree(config->save_crtc_enabled);
11391 kfree(config);
11392 }
11393
11394 static int intel_set_config_save_state(struct drm_device *dev,
11395 struct intel_set_config *config)
11396 {
11397 struct drm_crtc *crtc;
11398 struct drm_encoder *encoder;
11399 struct drm_connector *connector;
11400 int count;
11401
11402 config->save_crtc_enabled =
11403 kcalloc(dev->mode_config.num_crtc,
11404 sizeof(bool), GFP_KERNEL);
11405 if (!config->save_crtc_enabled)
11406 return -ENOMEM;
11407
11408 config->save_encoder_crtcs =
11409 kcalloc(dev->mode_config.num_encoder,
11410 sizeof(struct drm_crtc *), GFP_KERNEL);
11411 if (!config->save_encoder_crtcs)
11412 return -ENOMEM;
11413
11414 config->save_connector_encoders =
11415 kcalloc(dev->mode_config.num_connector,
11416 sizeof(struct drm_encoder *), GFP_KERNEL);
11417 if (!config->save_connector_encoders)
11418 return -ENOMEM;
11419
11420 /* Copy data. Note that driver private data is not affected.
11421 * Should anything bad happen only the expected state is
11422 * restored, not the drivers personal bookkeeping.
11423 */
11424 count = 0;
11425 for_each_crtc(dev, crtc) {
11426 config->save_crtc_enabled[count++] = crtc->state->enable;
11427 }
11428
11429 count = 0;
11430 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11431 config->save_encoder_crtcs[count++] = encoder->crtc;
11432 }
11433
11434 count = 0;
11435 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11436 config->save_connector_encoders[count++] = connector->encoder;
11437 }
11438
11439 return 0;
11440 }
11441
11442 static void intel_set_config_restore_state(struct drm_device *dev,
11443 struct intel_set_config *config)
11444 {
11445 struct intel_crtc *crtc;
11446 struct intel_encoder *encoder;
11447 struct intel_connector *connector;
11448 int count;
11449
11450 count = 0;
11451 for_each_intel_crtc(dev, crtc) {
11452 crtc->new_enabled = config->save_crtc_enabled[count++];
11453
11454 if (crtc->new_enabled)
11455 crtc->new_config = crtc->config;
11456 else
11457 crtc->new_config = NULL;
11458 }
11459
11460 count = 0;
11461 for_each_intel_encoder(dev, encoder) {
11462 encoder->new_crtc =
11463 to_intel_crtc(config->save_encoder_crtcs[count++]);
11464 }
11465
11466 count = 0;
11467 for_each_intel_connector(dev, connector) {
11468 connector->new_encoder =
11469 to_intel_encoder(config->save_connector_encoders[count++]);
11470 }
11471 }
11472
11473 static bool
11474 is_crtc_connector_off(struct drm_mode_set *set)
11475 {
11476 int i;
11477
11478 if (set->num_connectors == 0)
11479 return false;
11480
11481 if (WARN_ON(set->connectors == NULL))
11482 return false;
11483
11484 for (i = 0; i < set->num_connectors; i++)
11485 if (set->connectors[i]->encoder &&
11486 set->connectors[i]->encoder->crtc == set->crtc &&
11487 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11488 return true;
11489
11490 return false;
11491 }
11492
11493 static void
11494 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11495 struct intel_set_config *config)
11496 {
11497
11498 /* We should be able to check here if the fb has the same properties
11499 * and then just flip_or_move it */
11500 if (is_crtc_connector_off(set)) {
11501 config->mode_changed = true;
11502 } else if (set->crtc->primary->fb != set->fb) {
11503 /*
11504 * If we have no fb, we can only flip as long as the crtc is
11505 * active, otherwise we need a full mode set. The crtc may
11506 * be active if we've only disabled the primary plane, or
11507 * in fastboot situations.
11508 */
11509 if (set->crtc->primary->fb == NULL) {
11510 struct intel_crtc *intel_crtc =
11511 to_intel_crtc(set->crtc);
11512
11513 if (intel_crtc->active) {
11514 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11515 config->fb_changed = true;
11516 } else {
11517 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11518 config->mode_changed = true;
11519 }
11520 } else if (set->fb == NULL) {
11521 config->mode_changed = true;
11522 } else if (set->fb->pixel_format !=
11523 set->crtc->primary->fb->pixel_format) {
11524 config->mode_changed = true;
11525 } else {
11526 config->fb_changed = true;
11527 }
11528 }
11529
11530 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11531 config->fb_changed = true;
11532
11533 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11534 DRM_DEBUG_KMS("modes are different, full mode set\n");
11535 drm_mode_debug_printmodeline(&set->crtc->mode);
11536 drm_mode_debug_printmodeline(set->mode);
11537 config->mode_changed = true;
11538 }
11539
11540 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11541 set->crtc->base.id, config->mode_changed, config->fb_changed);
11542 }
11543
11544 static int
11545 intel_modeset_stage_output_state(struct drm_device *dev,
11546 struct drm_mode_set *set,
11547 struct intel_set_config *config)
11548 {
11549 struct intel_connector *connector;
11550 struct intel_encoder *encoder;
11551 struct intel_crtc *crtc;
11552 int ro;
11553
11554 /* The upper layers ensure that we either disable a crtc or have a list
11555 * of connectors. For paranoia, double-check this. */
11556 WARN_ON(!set->fb && (set->num_connectors != 0));
11557 WARN_ON(set->fb && (set->num_connectors == 0));
11558
11559 for_each_intel_connector(dev, connector) {
11560 /* Otherwise traverse passed in connector list and get encoders
11561 * for them. */
11562 for (ro = 0; ro < set->num_connectors; ro++) {
11563 if (set->connectors[ro] == &connector->base) {
11564 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11565 break;
11566 }
11567 }
11568
11569 /* If we disable the crtc, disable all its connectors. Also, if
11570 * the connector is on the changing crtc but not on the new
11571 * connector list, disable it. */
11572 if ((!set->fb || ro == set->num_connectors) &&
11573 connector->base.encoder &&
11574 connector->base.encoder->crtc == set->crtc) {
11575 connector->new_encoder = NULL;
11576
11577 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11578 connector->base.base.id,
11579 connector->base.name);
11580 }
11581
11582
11583 if (&connector->new_encoder->base != connector->base.encoder) {
11584 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full mode switch\n",
11585 connector->base.base.id,
11586 connector->base.name);
11587 config->mode_changed = true;
11588 }
11589 }
11590 /* connector->new_encoder is now updated for all connectors. */
11591
11592 /* Update crtc of enabled connectors. */
11593 for_each_intel_connector(dev, connector) {
11594 struct drm_crtc *new_crtc;
11595
11596 if (!connector->new_encoder)
11597 continue;
11598
11599 new_crtc = connector->new_encoder->base.crtc;
11600
11601 for (ro = 0; ro < set->num_connectors; ro++) {
11602 if (set->connectors[ro] == &connector->base)
11603 new_crtc = set->crtc;
11604 }
11605
11606 /* Make sure the new CRTC will work with the encoder */
11607 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11608 new_crtc)) {
11609 return -EINVAL;
11610 }
11611 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11612
11613 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11614 connector->base.base.id,
11615 connector->base.name,
11616 new_crtc->base.id);
11617 }
11618
11619 /* Check for any encoders that needs to be disabled. */
11620 for_each_intel_encoder(dev, encoder) {
11621 int num_connectors = 0;
11622 for_each_intel_connector(dev, connector) {
11623 if (connector->new_encoder == encoder) {
11624 WARN_ON(!connector->new_encoder->new_crtc);
11625 num_connectors++;
11626 }
11627 }
11628
11629 if (num_connectors == 0)
11630 encoder->new_crtc = NULL;
11631 else if (num_connectors > 1)
11632 return -EINVAL;
11633
11634 /* Only now check for crtc changes so we don't miss encoders
11635 * that will be disabled. */
11636 if (&encoder->new_crtc->base != encoder->base.crtc) {
11637 DRM_DEBUG_KMS("[ENCODER:%d:%s] crtc changed, full mode switch\n",
11638 encoder->base.base.id,
11639 encoder->base.name);
11640 config->mode_changed = true;
11641 }
11642 }
11643 /* Now we've also updated encoder->new_crtc for all encoders. */
11644 for_each_intel_connector(dev, connector) {
11645 if (connector->new_encoder)
11646 if (connector->new_encoder != connector->encoder)
11647 connector->encoder = connector->new_encoder;
11648 }
11649 for_each_intel_crtc(dev, crtc) {
11650 crtc->new_enabled = false;
11651
11652 for_each_intel_encoder(dev, encoder) {
11653 if (encoder->new_crtc == crtc) {
11654 crtc->new_enabled = true;
11655 break;
11656 }
11657 }
11658
11659 if (crtc->new_enabled != crtc->base.state->enable) {
11660 DRM_DEBUG_KMS("[CRTC:%d] %sabled, full mode switch\n",
11661 crtc->base.base.id,
11662 crtc->new_enabled ? "en" : "dis");
11663 config->mode_changed = true;
11664 }
11665
11666 if (crtc->new_enabled)
11667 crtc->new_config = crtc->config;
11668 else
11669 crtc->new_config = NULL;
11670 }
11671
11672 return 0;
11673 }
11674
11675 static void disable_crtc_nofb(struct intel_crtc *crtc)
11676 {
11677 struct drm_device *dev = crtc->base.dev;
11678 struct intel_encoder *encoder;
11679 struct intel_connector *connector;
11680
11681 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11682 pipe_name(crtc->pipe));
11683
11684 for_each_intel_connector(dev, connector) {
11685 if (connector->new_encoder &&
11686 connector->new_encoder->new_crtc == crtc)
11687 connector->new_encoder = NULL;
11688 }
11689
11690 for_each_intel_encoder(dev, encoder) {
11691 if (encoder->new_crtc == crtc)
11692 encoder->new_crtc = NULL;
11693 }
11694
11695 crtc->new_enabled = false;
11696 crtc->new_config = NULL;
11697 }
11698
11699 static int intel_crtc_set_config(struct drm_mode_set *set)
11700 {
11701 struct drm_device *dev;
11702 struct drm_mode_set save_set;
11703 struct intel_set_config *config;
11704 struct intel_crtc_state *pipe_config;
11705 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11706 int ret;
11707
11708 BUG_ON(!set);
11709 BUG_ON(!set->crtc);
11710 BUG_ON(!set->crtc->helper_private);
11711
11712 /* Enforce sane interface api - has been abused by the fb helper. */
11713 BUG_ON(!set->mode && set->fb);
11714 BUG_ON(set->fb && set->num_connectors == 0);
11715
11716 if (set->fb) {
11717 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11718 set->crtc->base.id, set->fb->base.id,
11719 (int)set->num_connectors, set->x, set->y);
11720 } else {
11721 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11722 }
11723
11724 dev = set->crtc->dev;
11725
11726 ret = -ENOMEM;
11727 config = kzalloc(sizeof(*config), GFP_KERNEL);
11728 if (!config)
11729 goto out_config;
11730
11731 ret = intel_set_config_save_state(dev, config);
11732 if (ret)
11733 goto out_config;
11734
11735 save_set.crtc = set->crtc;
11736 save_set.mode = &set->crtc->mode;
11737 save_set.x = set->crtc->x;
11738 save_set.y = set->crtc->y;
11739 save_set.fb = set->crtc->primary->fb;
11740
11741 /* Compute whether we need a full modeset, only an fb base update or no
11742 * change at all. In the future we might also check whether only the
11743 * mode changed, e.g. for LVDS where we only change the panel fitter in
11744 * such cases. */
11745 intel_set_config_compute_mode_changes(set, config);
11746
11747 ret = intel_modeset_stage_output_state(dev, set, config);
11748 if (ret)
11749 goto fail;
11750
11751 pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
11752 set->fb,
11753 &modeset_pipes,
11754 &prepare_pipes,
11755 &disable_pipes);
11756 if (IS_ERR(pipe_config)) {
11757 ret = PTR_ERR(pipe_config);
11758 goto fail;
11759 } else if (pipe_config) {
11760 if (pipe_config->has_audio !=
11761 to_intel_crtc(set->crtc)->config->has_audio)
11762 config->mode_changed = true;
11763
11764 /*
11765 * Note we have an issue here with infoframes: current code
11766 * only updates them on the full mode set path per hw
11767 * requirements. So here we should be checking for any
11768 * required changes and forcing a mode set.
11769 */
11770 }
11771
11772 /* set_mode will free it in the mode_changed case */
11773 if (!config->mode_changed)
11774 kfree(pipe_config);
11775
11776 intel_update_pipe_size(to_intel_crtc(set->crtc));
11777
11778 if (config->mode_changed) {
11779 ret = intel_set_mode_pipes(set->crtc, set->mode,
11780 set->x, set->y, set->fb, pipe_config,
11781 modeset_pipes, prepare_pipes,
11782 disable_pipes);
11783 } else if (config->fb_changed) {
11784 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11785 struct drm_plane *primary = set->crtc->primary;
11786 int vdisplay, hdisplay;
11787
11788 drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay);
11789 ret = primary->funcs->update_plane(primary, set->crtc, set->fb,
11790 0, 0, hdisplay, vdisplay,
11791 set->x << 16, set->y << 16,
11792 hdisplay << 16, vdisplay << 16);
11793
11794 /*
11795 * We need to make sure the primary plane is re-enabled if it
11796 * has previously been turned off.
11797 */
11798 if (!intel_crtc->primary_enabled && ret == 0) {
11799 WARN_ON(!intel_crtc->active);
11800 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11801 }
11802
11803 /*
11804 * In the fastboot case this may be our only check of the
11805 * state after boot. It would be better to only do it on
11806 * the first update, but we don't have a nice way of doing that
11807 * (and really, set_config isn't used much for high freq page
11808 * flipping, so increasing its cost here shouldn't be a big
11809 * deal).
11810 */
11811 if (i915.fastboot && ret == 0)
11812 intel_modeset_check_state(set->crtc->dev);
11813 }
11814
11815 if (ret) {
11816 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11817 set->crtc->base.id, ret);
11818 fail:
11819 intel_set_config_restore_state(dev, config);
11820
11821 /*
11822 * HACK: if the pipe was on, but we didn't have a framebuffer,
11823 * force the pipe off to avoid oopsing in the modeset code
11824 * due to fb==NULL. This should only happen during boot since
11825 * we don't yet reconstruct the FB from the hardware state.
11826 */
11827 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11828 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11829
11830 /* Try to restore the config */
11831 if (config->mode_changed &&
11832 intel_set_mode(save_set.crtc, save_set.mode,
11833 save_set.x, save_set.y, save_set.fb))
11834 DRM_ERROR("failed to restore config after modeset failure\n");
11835 }
11836
11837 out_config:
11838 intel_set_config_free(config);
11839 return ret;
11840 }
11841
11842 static const struct drm_crtc_funcs intel_crtc_funcs = {
11843 .gamma_set = intel_crtc_gamma_set,
11844 .set_config = intel_crtc_set_config,
11845 .destroy = intel_crtc_destroy,
11846 .page_flip = intel_crtc_page_flip,
11847 .atomic_duplicate_state = intel_crtc_duplicate_state,
11848 .atomic_destroy_state = intel_crtc_destroy_state,
11849 };
11850
11851 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11852 struct intel_shared_dpll *pll,
11853 struct intel_dpll_hw_state *hw_state)
11854 {
11855 uint32_t val;
11856
11857 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
11858 return false;
11859
11860 val = I915_READ(PCH_DPLL(pll->id));
11861 hw_state->dpll = val;
11862 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11863 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11864
11865 return val & DPLL_VCO_ENABLE;
11866 }
11867
11868 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11869 struct intel_shared_dpll *pll)
11870 {
11871 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
11872 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
11873 }
11874
11875 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11876 struct intel_shared_dpll *pll)
11877 {
11878 /* PCH refclock must be enabled first */
11879 ibx_assert_pch_refclk_enabled(dev_priv);
11880
11881 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11882
11883 /* Wait for the clocks to stabilize. */
11884 POSTING_READ(PCH_DPLL(pll->id));
11885 udelay(150);
11886
11887 /* The pixel multiplier can only be updated once the
11888 * DPLL is enabled and the clocks are stable.
11889 *
11890 * So write it again.
11891 */
11892 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11893 POSTING_READ(PCH_DPLL(pll->id));
11894 udelay(200);
11895 }
11896
11897 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11898 struct intel_shared_dpll *pll)
11899 {
11900 struct drm_device *dev = dev_priv->dev;
11901 struct intel_crtc *crtc;
11902
11903 /* Make sure no transcoder isn't still depending on us. */
11904 for_each_intel_crtc(dev, crtc) {
11905 if (intel_crtc_to_shared_dpll(crtc) == pll)
11906 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11907 }
11908
11909 I915_WRITE(PCH_DPLL(pll->id), 0);
11910 POSTING_READ(PCH_DPLL(pll->id));
11911 udelay(200);
11912 }
11913
11914 static char *ibx_pch_dpll_names[] = {
11915 "PCH DPLL A",
11916 "PCH DPLL B",
11917 };
11918
11919 static void ibx_pch_dpll_init(struct drm_device *dev)
11920 {
11921 struct drm_i915_private *dev_priv = dev->dev_private;
11922 int i;
11923
11924 dev_priv->num_shared_dpll = 2;
11925
11926 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11927 dev_priv->shared_dplls[i].id = i;
11928 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11929 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11930 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11931 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11932 dev_priv->shared_dplls[i].get_hw_state =
11933 ibx_pch_dpll_get_hw_state;
11934 }
11935 }
11936
11937 static void intel_shared_dpll_init(struct drm_device *dev)
11938 {
11939 struct drm_i915_private *dev_priv = dev->dev_private;
11940
11941 if (HAS_DDI(dev))
11942 intel_ddi_pll_init(dev);
11943 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11944 ibx_pch_dpll_init(dev);
11945 else
11946 dev_priv->num_shared_dpll = 0;
11947
11948 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11949 }
11950
11951 /**
11952 * intel_prepare_plane_fb - Prepare fb for usage on plane
11953 * @plane: drm plane to prepare for
11954 * @fb: framebuffer to prepare for presentation
11955 *
11956 * Prepares a framebuffer for usage on a display plane. Generally this
11957 * involves pinning the underlying object and updating the frontbuffer tracking
11958 * bits. Some older platforms need special physical address handling for
11959 * cursor planes.
11960 *
11961 * Returns 0 on success, negative error code on failure.
11962 */
11963 int
11964 intel_prepare_plane_fb(struct drm_plane *plane,
11965 struct drm_framebuffer *fb,
11966 const struct drm_plane_state *new_state)
11967 {
11968 struct drm_device *dev = plane->dev;
11969 struct intel_plane *intel_plane = to_intel_plane(plane);
11970 enum pipe pipe = intel_plane->pipe;
11971 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11972 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11973 unsigned frontbuffer_bits = 0;
11974 int ret = 0;
11975
11976 if (!obj)
11977 return 0;
11978
11979 switch (plane->type) {
11980 case DRM_PLANE_TYPE_PRIMARY:
11981 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
11982 break;
11983 case DRM_PLANE_TYPE_CURSOR:
11984 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
11985 break;
11986 case DRM_PLANE_TYPE_OVERLAY:
11987 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
11988 break;
11989 }
11990
11991 mutex_lock(&dev->struct_mutex);
11992
11993 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
11994 INTEL_INFO(dev)->cursor_needs_physical) {
11995 int align = IS_I830(dev) ? 16 * 1024 : 256;
11996 ret = i915_gem_object_attach_phys(obj, align);
11997 if (ret)
11998 DRM_DEBUG_KMS("failed to attach phys object\n");
11999 } else {
12000 ret = intel_pin_and_fence_fb_obj(plane, fb, NULL);
12001 }
12002
12003 if (ret == 0)
12004 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
12005
12006 mutex_unlock(&dev->struct_mutex);
12007
12008 return ret;
12009 }
12010
12011 /**
12012 * intel_cleanup_plane_fb - Cleans up an fb after plane use
12013 * @plane: drm plane to clean up for
12014 * @fb: old framebuffer that was on plane
12015 *
12016 * Cleans up a framebuffer that has just been removed from a plane.
12017 */
12018 void
12019 intel_cleanup_plane_fb(struct drm_plane *plane,
12020 struct drm_framebuffer *fb,
12021 const struct drm_plane_state *old_state)
12022 {
12023 struct drm_device *dev = plane->dev;
12024 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12025
12026 if (WARN_ON(!obj))
12027 return;
12028
12029 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
12030 !INTEL_INFO(dev)->cursor_needs_physical) {
12031 mutex_lock(&dev->struct_mutex);
12032 intel_unpin_fb_obj(obj);
12033 mutex_unlock(&dev->struct_mutex);
12034 }
12035 }
12036
12037 static int
12038 intel_check_primary_plane(struct drm_plane *plane,
12039 struct intel_plane_state *state)
12040 {
12041 struct drm_device *dev = plane->dev;
12042 struct drm_i915_private *dev_priv = dev->dev_private;
12043 struct drm_crtc *crtc = state->base.crtc;
12044 struct intel_crtc *intel_crtc;
12045 struct drm_framebuffer *fb = state->base.fb;
12046 struct drm_rect *dest = &state->dst;
12047 struct drm_rect *src = &state->src;
12048 const struct drm_rect *clip = &state->clip;
12049 int ret;
12050
12051 crtc = crtc ? crtc : plane->crtc;
12052 intel_crtc = to_intel_crtc(crtc);
12053
12054 ret = drm_plane_helper_check_update(plane, crtc, fb,
12055 src, dest, clip,
12056 DRM_PLANE_HELPER_NO_SCALING,
12057 DRM_PLANE_HELPER_NO_SCALING,
12058 false, true, &state->visible);
12059 if (ret)
12060 return ret;
12061
12062 if (intel_crtc->active) {
12063 intel_crtc->atomic.wait_for_flips = true;
12064
12065 /*
12066 * FBC does not work on some platforms for rotated
12067 * planes, so disable it when rotation is not 0 and
12068 * update it when rotation is set back to 0.
12069 *
12070 * FIXME: This is redundant with the fbc update done in
12071 * the primary plane enable function except that that
12072 * one is done too late. We eventually need to unify
12073 * this.
12074 */
12075 if (intel_crtc->primary_enabled &&
12076 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
12077 dev_priv->fbc.crtc == intel_crtc &&
12078 state->base.rotation != BIT(DRM_ROTATE_0)) {
12079 intel_crtc->atomic.disable_fbc = true;
12080 }
12081
12082 if (state->visible) {
12083 /*
12084 * BDW signals flip done immediately if the plane
12085 * is disabled, even if the plane enable is already
12086 * armed to occur at the next vblank :(
12087 */
12088 if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled)
12089 intel_crtc->atomic.wait_vblank = true;
12090 }
12091
12092 intel_crtc->atomic.fb_bits |=
12093 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
12094
12095 intel_crtc->atomic.update_fbc = true;
12096
12097 /* Update watermarks on tiling changes. */
12098 if (!plane->state->fb || !state->base.fb ||
12099 plane->state->fb->modifier[0] !=
12100 state->base.fb->modifier[0])
12101 intel_crtc->atomic.update_wm = true;
12102 }
12103
12104 return 0;
12105 }
12106
12107 static void
12108 intel_commit_primary_plane(struct drm_plane *plane,
12109 struct intel_plane_state *state)
12110 {
12111 struct drm_crtc *crtc = state->base.crtc;
12112 struct drm_framebuffer *fb = state->base.fb;
12113 struct drm_device *dev = plane->dev;
12114 struct drm_i915_private *dev_priv = dev->dev_private;
12115 struct intel_crtc *intel_crtc;
12116 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12117 struct intel_plane *intel_plane = to_intel_plane(plane);
12118 struct drm_rect *src = &state->src;
12119
12120 crtc = crtc ? crtc : plane->crtc;
12121 intel_crtc = to_intel_crtc(crtc);
12122
12123 plane->fb = fb;
12124 crtc->x = src->x1 >> 16;
12125 crtc->y = src->y1 >> 16;
12126
12127 intel_plane->obj = obj;
12128
12129 if (intel_crtc->active) {
12130 if (state->visible) {
12131 /* FIXME: kill this fastboot hack */
12132 intel_update_pipe_size(intel_crtc);
12133
12134 intel_crtc->primary_enabled = true;
12135
12136 dev_priv->display.update_primary_plane(crtc, plane->fb,
12137 crtc->x, crtc->y);
12138 } else {
12139 /*
12140 * If clipping results in a non-visible primary plane,
12141 * we'll disable the primary plane. Note that this is
12142 * a bit different than what happens if userspace
12143 * explicitly disables the plane by passing fb=0
12144 * because plane->fb still gets set and pinned.
12145 */
12146 intel_disable_primary_hw_plane(plane, crtc);
12147 }
12148 }
12149 }
12150
12151 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
12152 {
12153 struct drm_device *dev = crtc->dev;
12154 struct drm_i915_private *dev_priv = dev->dev_private;
12155 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12156 struct intel_plane *intel_plane;
12157 struct drm_plane *p;
12158 unsigned fb_bits = 0;
12159
12160 /* Track fb's for any planes being disabled */
12161 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
12162 intel_plane = to_intel_plane(p);
12163
12164 if (intel_crtc->atomic.disabled_planes &
12165 (1 << drm_plane_index(p))) {
12166 switch (p->type) {
12167 case DRM_PLANE_TYPE_PRIMARY:
12168 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
12169 break;
12170 case DRM_PLANE_TYPE_CURSOR:
12171 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
12172 break;
12173 case DRM_PLANE_TYPE_OVERLAY:
12174 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
12175 break;
12176 }
12177
12178 mutex_lock(&dev->struct_mutex);
12179 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
12180 mutex_unlock(&dev->struct_mutex);
12181 }
12182 }
12183
12184 if (intel_crtc->atomic.wait_for_flips)
12185 intel_crtc_wait_for_pending_flips(crtc);
12186
12187 if (intel_crtc->atomic.disable_fbc)
12188 intel_fbc_disable(dev);
12189
12190 if (intel_crtc->atomic.pre_disable_primary)
12191 intel_pre_disable_primary(crtc);
12192
12193 if (intel_crtc->atomic.update_wm)
12194 intel_update_watermarks(crtc);
12195
12196 intel_runtime_pm_get(dev_priv);
12197
12198 /* Perform vblank evasion around commit operation */
12199 if (intel_crtc->active)
12200 intel_crtc->atomic.evade =
12201 intel_pipe_update_start(intel_crtc,
12202 &intel_crtc->atomic.start_vbl_count);
12203 }
12204
12205 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
12206 {
12207 struct drm_device *dev = crtc->dev;
12208 struct drm_i915_private *dev_priv = dev->dev_private;
12209 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12210 struct drm_plane *p;
12211
12212 if (intel_crtc->atomic.evade)
12213 intel_pipe_update_end(intel_crtc,
12214 intel_crtc->atomic.start_vbl_count);
12215
12216 intel_runtime_pm_put(dev_priv);
12217
12218 if (intel_crtc->atomic.wait_vblank)
12219 intel_wait_for_vblank(dev, intel_crtc->pipe);
12220
12221 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
12222
12223 if (intel_crtc->atomic.update_fbc) {
12224 mutex_lock(&dev->struct_mutex);
12225 intel_fbc_update(dev);
12226 mutex_unlock(&dev->struct_mutex);
12227 }
12228
12229 if (intel_crtc->atomic.post_enable_primary)
12230 intel_post_enable_primary(crtc);
12231
12232 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
12233 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
12234 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
12235 false, false);
12236
12237 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
12238 }
12239
12240 /**
12241 * intel_plane_destroy - destroy a plane
12242 * @plane: plane to destroy
12243 *
12244 * Common destruction function for all types of planes (primary, cursor,
12245 * sprite).
12246 */
12247 void intel_plane_destroy(struct drm_plane *plane)
12248 {
12249 struct intel_plane *intel_plane = to_intel_plane(plane);
12250 drm_plane_cleanup(plane);
12251 kfree(intel_plane);
12252 }
12253
12254 const struct drm_plane_funcs intel_plane_funcs = {
12255 .update_plane = drm_plane_helper_update,
12256 .disable_plane = drm_plane_helper_disable,
12257 .destroy = intel_plane_destroy,
12258 .set_property = drm_atomic_helper_plane_set_property,
12259 .atomic_get_property = intel_plane_atomic_get_property,
12260 .atomic_set_property = intel_plane_atomic_set_property,
12261 .atomic_duplicate_state = intel_plane_duplicate_state,
12262 .atomic_destroy_state = intel_plane_destroy_state,
12263
12264 };
12265
12266 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
12267 int pipe)
12268 {
12269 struct intel_plane *primary;
12270 struct intel_plane_state *state;
12271 const uint32_t *intel_primary_formats;
12272 int num_formats;
12273
12274 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
12275 if (primary == NULL)
12276 return NULL;
12277
12278 state = intel_create_plane_state(&primary->base);
12279 if (!state) {
12280 kfree(primary);
12281 return NULL;
12282 }
12283 primary->base.state = &state->base;
12284
12285 primary->can_scale = false;
12286 primary->max_downscale = 1;
12287 primary->pipe = pipe;
12288 primary->plane = pipe;
12289 primary->check_plane = intel_check_primary_plane;
12290 primary->commit_plane = intel_commit_primary_plane;
12291 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
12292 primary->plane = !pipe;
12293
12294 if (INTEL_INFO(dev)->gen <= 3) {
12295 intel_primary_formats = intel_primary_formats_gen2;
12296 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
12297 } else {
12298 intel_primary_formats = intel_primary_formats_gen4;
12299 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
12300 }
12301
12302 drm_universal_plane_init(dev, &primary->base, 0,
12303 &intel_plane_funcs,
12304 intel_primary_formats, num_formats,
12305 DRM_PLANE_TYPE_PRIMARY);
12306
12307 if (INTEL_INFO(dev)->gen >= 4) {
12308 if (!dev->mode_config.rotation_property)
12309 dev->mode_config.rotation_property =
12310 drm_mode_create_rotation_property(dev,
12311 BIT(DRM_ROTATE_0) |
12312 BIT(DRM_ROTATE_180));
12313 if (dev->mode_config.rotation_property)
12314 drm_object_attach_property(&primary->base.base,
12315 dev->mode_config.rotation_property,
12316 state->base.rotation);
12317 }
12318
12319 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
12320
12321 return &primary->base;
12322 }
12323
12324 static int
12325 intel_check_cursor_plane(struct drm_plane *plane,
12326 struct intel_plane_state *state)
12327 {
12328 struct drm_crtc *crtc = state->base.crtc;
12329 struct drm_device *dev = plane->dev;
12330 struct drm_framebuffer *fb = state->base.fb;
12331 struct drm_rect *dest = &state->dst;
12332 struct drm_rect *src = &state->src;
12333 const struct drm_rect *clip = &state->clip;
12334 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12335 struct intel_crtc *intel_crtc;
12336 unsigned stride;
12337 int ret;
12338
12339 crtc = crtc ? crtc : plane->crtc;
12340 intel_crtc = to_intel_crtc(crtc);
12341
12342 ret = drm_plane_helper_check_update(plane, crtc, fb,
12343 src, dest, clip,
12344 DRM_PLANE_HELPER_NO_SCALING,
12345 DRM_PLANE_HELPER_NO_SCALING,
12346 true, true, &state->visible);
12347 if (ret)
12348 return ret;
12349
12350
12351 /* if we want to turn off the cursor ignore width and height */
12352 if (!obj)
12353 goto finish;
12354
12355 /* Check for which cursor types we support */
12356 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
12357 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
12358 state->base.crtc_w, state->base.crtc_h);
12359 return -EINVAL;
12360 }
12361
12362 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
12363 if (obj->base.size < stride * state->base.crtc_h) {
12364 DRM_DEBUG_KMS("buffer is too small\n");
12365 return -ENOMEM;
12366 }
12367
12368 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
12369 DRM_DEBUG_KMS("cursor cannot be tiled\n");
12370 ret = -EINVAL;
12371 }
12372
12373 finish:
12374 if (intel_crtc->active) {
12375 if (plane->state->crtc_w != state->base.crtc_w)
12376 intel_crtc->atomic.update_wm = true;
12377
12378 intel_crtc->atomic.fb_bits |=
12379 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
12380 }
12381
12382 return ret;
12383 }
12384
12385 static void
12386 intel_commit_cursor_plane(struct drm_plane *plane,
12387 struct intel_plane_state *state)
12388 {
12389 struct drm_crtc *crtc = state->base.crtc;
12390 struct drm_device *dev = plane->dev;
12391 struct intel_crtc *intel_crtc;
12392 struct intel_plane *intel_plane = to_intel_plane(plane);
12393 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
12394 uint32_t addr;
12395
12396 crtc = crtc ? crtc : plane->crtc;
12397 intel_crtc = to_intel_crtc(crtc);
12398
12399 plane->fb = state->base.fb;
12400 crtc->cursor_x = state->base.crtc_x;
12401 crtc->cursor_y = state->base.crtc_y;
12402
12403 intel_plane->obj = obj;
12404
12405 if (intel_crtc->cursor_bo == obj)
12406 goto update;
12407
12408 if (!obj)
12409 addr = 0;
12410 else if (!INTEL_INFO(dev)->cursor_needs_physical)
12411 addr = i915_gem_obj_ggtt_offset(obj);
12412 else
12413 addr = obj->phys_handle->busaddr;
12414
12415 intel_crtc->cursor_addr = addr;
12416 intel_crtc->cursor_bo = obj;
12417 update:
12418
12419 if (intel_crtc->active)
12420 intel_crtc_update_cursor(crtc, state->visible);
12421 }
12422
12423 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12424 int pipe)
12425 {
12426 struct intel_plane *cursor;
12427 struct intel_plane_state *state;
12428
12429 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12430 if (cursor == NULL)
12431 return NULL;
12432
12433 state = intel_create_plane_state(&cursor->base);
12434 if (!state) {
12435 kfree(cursor);
12436 return NULL;
12437 }
12438 cursor->base.state = &state->base;
12439
12440 cursor->can_scale = false;
12441 cursor->max_downscale = 1;
12442 cursor->pipe = pipe;
12443 cursor->plane = pipe;
12444 cursor->check_plane = intel_check_cursor_plane;
12445 cursor->commit_plane = intel_commit_cursor_plane;
12446
12447 drm_universal_plane_init(dev, &cursor->base, 0,
12448 &intel_plane_funcs,
12449 intel_cursor_formats,
12450 ARRAY_SIZE(intel_cursor_formats),
12451 DRM_PLANE_TYPE_CURSOR);
12452
12453 if (INTEL_INFO(dev)->gen >= 4) {
12454 if (!dev->mode_config.rotation_property)
12455 dev->mode_config.rotation_property =
12456 drm_mode_create_rotation_property(dev,
12457 BIT(DRM_ROTATE_0) |
12458 BIT(DRM_ROTATE_180));
12459 if (dev->mode_config.rotation_property)
12460 drm_object_attach_property(&cursor->base.base,
12461 dev->mode_config.rotation_property,
12462 state->base.rotation);
12463 }
12464
12465 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
12466
12467 return &cursor->base;
12468 }
12469
12470 static void intel_crtc_init(struct drm_device *dev, int pipe)
12471 {
12472 struct drm_i915_private *dev_priv = dev->dev_private;
12473 struct intel_crtc *intel_crtc;
12474 struct intel_crtc_state *crtc_state = NULL;
12475 struct drm_plane *primary = NULL;
12476 struct drm_plane *cursor = NULL;
12477 int i, ret;
12478
12479 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12480 if (intel_crtc == NULL)
12481 return;
12482
12483 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
12484 if (!crtc_state)
12485 goto fail;
12486 intel_crtc_set_state(intel_crtc, crtc_state);
12487 crtc_state->base.crtc = &intel_crtc->base;
12488
12489 primary = intel_primary_plane_create(dev, pipe);
12490 if (!primary)
12491 goto fail;
12492
12493 cursor = intel_cursor_plane_create(dev, pipe);
12494 if (!cursor)
12495 goto fail;
12496
12497 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12498 cursor, &intel_crtc_funcs);
12499 if (ret)
12500 goto fail;
12501
12502 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12503 for (i = 0; i < 256; i++) {
12504 intel_crtc->lut_r[i] = i;
12505 intel_crtc->lut_g[i] = i;
12506 intel_crtc->lut_b[i] = i;
12507 }
12508
12509 /*
12510 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12511 * is hooked to pipe B. Hence we want plane A feeding pipe B.
12512 */
12513 intel_crtc->pipe = pipe;
12514 intel_crtc->plane = pipe;
12515 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12516 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12517 intel_crtc->plane = !pipe;
12518 }
12519
12520 intel_crtc->cursor_base = ~0;
12521 intel_crtc->cursor_cntl = ~0;
12522 intel_crtc->cursor_size = ~0;
12523
12524 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12525 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12526 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12527 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12528
12529 INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
12530
12531 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12532
12533 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12534 return;
12535
12536 fail:
12537 if (primary)
12538 drm_plane_cleanup(primary);
12539 if (cursor)
12540 drm_plane_cleanup(cursor);
12541 kfree(crtc_state);
12542 kfree(intel_crtc);
12543 }
12544
12545 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12546 {
12547 struct drm_encoder *encoder = connector->base.encoder;
12548 struct drm_device *dev = connector->base.dev;
12549
12550 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12551
12552 if (!encoder || WARN_ON(!encoder->crtc))
12553 return INVALID_PIPE;
12554
12555 return to_intel_crtc(encoder->crtc)->pipe;
12556 }
12557
12558 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12559 struct drm_file *file)
12560 {
12561 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12562 struct drm_crtc *drmmode_crtc;
12563 struct intel_crtc *crtc;
12564
12565 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12566
12567 if (!drmmode_crtc) {
12568 DRM_ERROR("no such CRTC id\n");
12569 return -ENOENT;
12570 }
12571
12572 crtc = to_intel_crtc(drmmode_crtc);
12573 pipe_from_crtc_id->pipe = crtc->pipe;
12574
12575 return 0;
12576 }
12577
12578 static int intel_encoder_clones(struct intel_encoder *encoder)
12579 {
12580 struct drm_device *dev = encoder->base.dev;
12581 struct intel_encoder *source_encoder;
12582 int index_mask = 0;
12583 int entry = 0;
12584
12585 for_each_intel_encoder(dev, source_encoder) {
12586 if (encoders_cloneable(encoder, source_encoder))
12587 index_mask |= (1 << entry);
12588
12589 entry++;
12590 }
12591
12592 return index_mask;
12593 }
12594
12595 static bool has_edp_a(struct drm_device *dev)
12596 {
12597 struct drm_i915_private *dev_priv = dev->dev_private;
12598
12599 if (!IS_MOBILE(dev))
12600 return false;
12601
12602 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12603 return false;
12604
12605 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12606 return false;
12607
12608 return true;
12609 }
12610
12611 static bool intel_crt_present(struct drm_device *dev)
12612 {
12613 struct drm_i915_private *dev_priv = dev->dev_private;
12614
12615 if (INTEL_INFO(dev)->gen >= 9)
12616 return false;
12617
12618 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12619 return false;
12620
12621 if (IS_CHERRYVIEW(dev))
12622 return false;
12623
12624 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12625 return false;
12626
12627 return true;
12628 }
12629
12630 static void intel_setup_outputs(struct drm_device *dev)
12631 {
12632 struct drm_i915_private *dev_priv = dev->dev_private;
12633 struct intel_encoder *encoder;
12634 struct drm_connector *connector;
12635 bool dpd_is_edp = false;
12636
12637 intel_lvds_init(dev);
12638
12639 if (intel_crt_present(dev))
12640 intel_crt_init(dev);
12641
12642 if (HAS_DDI(dev)) {
12643 int found;
12644
12645 /*
12646 * Haswell uses DDI functions to detect digital outputs.
12647 * On SKL pre-D0 the strap isn't connected, so we assume
12648 * it's there.
12649 */
12650 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12651 /* WaIgnoreDDIAStrap: skl */
12652 if (found ||
12653 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
12654 intel_ddi_init(dev, PORT_A);
12655
12656 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12657 * register */
12658 found = I915_READ(SFUSE_STRAP);
12659
12660 if (found & SFUSE_STRAP_DDIB_DETECTED)
12661 intel_ddi_init(dev, PORT_B);
12662 if (found & SFUSE_STRAP_DDIC_DETECTED)
12663 intel_ddi_init(dev, PORT_C);
12664 if (found & SFUSE_STRAP_DDID_DETECTED)
12665 intel_ddi_init(dev, PORT_D);
12666 } else if (HAS_PCH_SPLIT(dev)) {
12667 int found;
12668 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12669
12670 if (has_edp_a(dev))
12671 intel_dp_init(dev, DP_A, PORT_A);
12672
12673 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12674 /* PCH SDVOB multiplex with HDMIB */
12675 found = intel_sdvo_init(dev, PCH_SDVOB, true);
12676 if (!found)
12677 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12678 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12679 intel_dp_init(dev, PCH_DP_B, PORT_B);
12680 }
12681
12682 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12683 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12684
12685 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12686 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12687
12688 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12689 intel_dp_init(dev, PCH_DP_C, PORT_C);
12690
12691 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12692 intel_dp_init(dev, PCH_DP_D, PORT_D);
12693 } else if (IS_VALLEYVIEW(dev)) {
12694 /*
12695 * The DP_DETECTED bit is the latched state of the DDC
12696 * SDA pin at boot. However since eDP doesn't require DDC
12697 * (no way to plug in a DP->HDMI dongle) the DDC pins for
12698 * eDP ports may have been muxed to an alternate function.
12699 * Thus we can't rely on the DP_DETECTED bit alone to detect
12700 * eDP ports. Consult the VBT as well as DP_DETECTED to
12701 * detect eDP ports.
12702 */
12703 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
12704 !intel_dp_is_edp(dev, PORT_B))
12705 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12706 PORT_B);
12707 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12708 intel_dp_is_edp(dev, PORT_B))
12709 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12710
12711 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
12712 !intel_dp_is_edp(dev, PORT_C))
12713 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12714 PORT_C);
12715 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12716 intel_dp_is_edp(dev, PORT_C))
12717 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12718
12719 if (IS_CHERRYVIEW(dev)) {
12720 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12721 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12722 PORT_D);
12723 /* eDP not supported on port D, so don't check VBT */
12724 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12725 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12726 }
12727
12728 intel_dsi_init(dev);
12729 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12730 bool found = false;
12731
12732 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12733 DRM_DEBUG_KMS("probing SDVOB\n");
12734 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12735 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12736 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12737 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12738 }
12739
12740 if (!found && SUPPORTS_INTEGRATED_DP(dev))
12741 intel_dp_init(dev, DP_B, PORT_B);
12742 }
12743
12744 /* Before G4X SDVOC doesn't have its own detect register */
12745
12746 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12747 DRM_DEBUG_KMS("probing SDVOC\n");
12748 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12749 }
12750
12751 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12752
12753 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12754 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12755 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12756 }
12757 if (SUPPORTS_INTEGRATED_DP(dev))
12758 intel_dp_init(dev, DP_C, PORT_C);
12759 }
12760
12761 if (SUPPORTS_INTEGRATED_DP(dev) &&
12762 (I915_READ(DP_D) & DP_DETECTED))
12763 intel_dp_init(dev, DP_D, PORT_D);
12764 } else if (IS_GEN2(dev))
12765 intel_dvo_init(dev);
12766
12767 if (SUPPORTS_TV(dev))
12768 intel_tv_init(dev);
12769
12770 /*
12771 * FIXME: We don't have full atomic support yet, but we want to be
12772 * able to enable/test plane updates via the atomic interface in the
12773 * meantime. However as soon as we flip DRIVER_ATOMIC on, the DRM core
12774 * will take some atomic codepaths to lookup properties during
12775 * drmModeGetConnector() that unconditionally dereference
12776 * connector->state.
12777 *
12778 * We create a dummy connector state here for each connector to ensure
12779 * the DRM core doesn't try to dereference a NULL connector->state.
12780 * The actual connector properties will never be updated or contain
12781 * useful information, but since we're doing this specifically for
12782 * testing/debug of the plane operations (and only when a specific
12783 * kernel module option is given), that shouldn't really matter.
12784 *
12785 * Once atomic support for crtc's + connectors lands, this loop should
12786 * be removed since we'll be setting up real connector state, which
12787 * will contain Intel-specific properties.
12788 */
12789 if (drm_core_check_feature(dev, DRIVER_ATOMIC)) {
12790 list_for_each_entry(connector,
12791 &dev->mode_config.connector_list,
12792 head) {
12793 if (!WARN_ON(connector->state)) {
12794 connector->state =
12795 kzalloc(sizeof(*connector->state),
12796 GFP_KERNEL);
12797 }
12798 }
12799 }
12800
12801 intel_psr_init(dev);
12802
12803 for_each_intel_encoder(dev, encoder) {
12804 encoder->base.possible_crtcs = encoder->crtc_mask;
12805 encoder->base.possible_clones =
12806 intel_encoder_clones(encoder);
12807 }
12808
12809 intel_init_pch_refclk(dev);
12810
12811 drm_helper_move_panel_connectors_to_head(dev);
12812 }
12813
12814 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12815 {
12816 struct drm_device *dev = fb->dev;
12817 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12818
12819 drm_framebuffer_cleanup(fb);
12820 mutex_lock(&dev->struct_mutex);
12821 WARN_ON(!intel_fb->obj->framebuffer_references--);
12822 drm_gem_object_unreference(&intel_fb->obj->base);
12823 mutex_unlock(&dev->struct_mutex);
12824 kfree(intel_fb);
12825 }
12826
12827 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12828 struct drm_file *file,
12829 unsigned int *handle)
12830 {
12831 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12832 struct drm_i915_gem_object *obj = intel_fb->obj;
12833
12834 return drm_gem_handle_create(file, &obj->base, handle);
12835 }
12836
12837 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12838 .destroy = intel_user_framebuffer_destroy,
12839 .create_handle = intel_user_framebuffer_create_handle,
12840 };
12841
12842 static
12843 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
12844 uint32_t pixel_format)
12845 {
12846 u32 gen = INTEL_INFO(dev)->gen;
12847
12848 if (gen >= 9) {
12849 /* "The stride in bytes must not exceed the of the size of 8K
12850 * pixels and 32K bytes."
12851 */
12852 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
12853 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
12854 return 32*1024;
12855 } else if (gen >= 4) {
12856 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
12857 return 16*1024;
12858 else
12859 return 32*1024;
12860 } else if (gen >= 3) {
12861 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
12862 return 8*1024;
12863 else
12864 return 16*1024;
12865 } else {
12866 /* XXX DSPC is limited to 4k tiled */
12867 return 8*1024;
12868 }
12869 }
12870
12871 static int intel_framebuffer_init(struct drm_device *dev,
12872 struct intel_framebuffer *intel_fb,
12873 struct drm_mode_fb_cmd2 *mode_cmd,
12874 struct drm_i915_gem_object *obj)
12875 {
12876 int aligned_height;
12877 int ret;
12878 u32 pitch_limit, stride_alignment;
12879
12880 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12881
12882 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
12883 /* Enforce that fb modifier and tiling mode match, but only for
12884 * X-tiled. This is needed for FBC. */
12885 if (!!(obj->tiling_mode == I915_TILING_X) !=
12886 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
12887 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
12888 return -EINVAL;
12889 }
12890 } else {
12891 if (obj->tiling_mode == I915_TILING_X)
12892 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
12893 else if (obj->tiling_mode == I915_TILING_Y) {
12894 DRM_DEBUG("No Y tiling for legacy addfb\n");
12895 return -EINVAL;
12896 }
12897 }
12898
12899 /* Passed in modifier sanity checking. */
12900 switch (mode_cmd->modifier[0]) {
12901 case I915_FORMAT_MOD_Y_TILED:
12902 case I915_FORMAT_MOD_Yf_TILED:
12903 if (INTEL_INFO(dev)->gen < 9) {
12904 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
12905 mode_cmd->modifier[0]);
12906 return -EINVAL;
12907 }
12908 case DRM_FORMAT_MOD_NONE:
12909 case I915_FORMAT_MOD_X_TILED:
12910 break;
12911 default:
12912 DRM_ERROR("Unsupported fb modifier 0x%llx!\n",
12913 mode_cmd->modifier[0]);
12914 return -EINVAL;
12915 }
12916
12917 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
12918 mode_cmd->pixel_format);
12919 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
12920 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
12921 mode_cmd->pitches[0], stride_alignment);
12922 return -EINVAL;
12923 }
12924
12925 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
12926 mode_cmd->pixel_format);
12927 if (mode_cmd->pitches[0] > pitch_limit) {
12928 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
12929 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
12930 "tiled" : "linear",
12931 mode_cmd->pitches[0], pitch_limit);
12932 return -EINVAL;
12933 }
12934
12935 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
12936 mode_cmd->pitches[0] != obj->stride) {
12937 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12938 mode_cmd->pitches[0], obj->stride);
12939 return -EINVAL;
12940 }
12941
12942 /* Reject formats not supported by any plane early. */
12943 switch (mode_cmd->pixel_format) {
12944 case DRM_FORMAT_C8:
12945 case DRM_FORMAT_RGB565:
12946 case DRM_FORMAT_XRGB8888:
12947 case DRM_FORMAT_ARGB8888:
12948 break;
12949 case DRM_FORMAT_XRGB1555:
12950 case DRM_FORMAT_ARGB1555:
12951 if (INTEL_INFO(dev)->gen > 3) {
12952 DRM_DEBUG("unsupported pixel format: %s\n",
12953 drm_get_format_name(mode_cmd->pixel_format));
12954 return -EINVAL;
12955 }
12956 break;
12957 case DRM_FORMAT_XBGR8888:
12958 case DRM_FORMAT_ABGR8888:
12959 case DRM_FORMAT_XRGB2101010:
12960 case DRM_FORMAT_ARGB2101010:
12961 case DRM_FORMAT_XBGR2101010:
12962 case DRM_FORMAT_ABGR2101010:
12963 if (INTEL_INFO(dev)->gen < 4) {
12964 DRM_DEBUG("unsupported pixel format: %s\n",
12965 drm_get_format_name(mode_cmd->pixel_format));
12966 return -EINVAL;
12967 }
12968 break;
12969 case DRM_FORMAT_YUYV:
12970 case DRM_FORMAT_UYVY:
12971 case DRM_FORMAT_YVYU:
12972 case DRM_FORMAT_VYUY:
12973 if (INTEL_INFO(dev)->gen < 5) {
12974 DRM_DEBUG("unsupported pixel format: %s\n",
12975 drm_get_format_name(mode_cmd->pixel_format));
12976 return -EINVAL;
12977 }
12978 break;
12979 default:
12980 DRM_DEBUG("unsupported pixel format: %s\n",
12981 drm_get_format_name(mode_cmd->pixel_format));
12982 return -EINVAL;
12983 }
12984
12985 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12986 if (mode_cmd->offsets[0] != 0)
12987 return -EINVAL;
12988
12989 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
12990 mode_cmd->pixel_format,
12991 mode_cmd->modifier[0]);
12992 /* FIXME drm helper for size checks (especially planar formats)? */
12993 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12994 return -EINVAL;
12995
12996 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12997 intel_fb->obj = obj;
12998 intel_fb->obj->framebuffer_references++;
12999
13000 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
13001 if (ret) {
13002 DRM_ERROR("framebuffer init failed %d\n", ret);
13003 return ret;
13004 }
13005
13006 return 0;
13007 }
13008
13009 static struct drm_framebuffer *
13010 intel_user_framebuffer_create(struct drm_device *dev,
13011 struct drm_file *filp,
13012 struct drm_mode_fb_cmd2 *mode_cmd)
13013 {
13014 struct drm_i915_gem_object *obj;
13015
13016 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
13017 mode_cmd->handles[0]));
13018 if (&obj->base == NULL)
13019 return ERR_PTR(-ENOENT);
13020
13021 return intel_framebuffer_create(dev, mode_cmd, obj);
13022 }
13023
13024 #ifndef CONFIG_DRM_I915_FBDEV
13025 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
13026 {
13027 }
13028 #endif
13029
13030 static const struct drm_mode_config_funcs intel_mode_funcs = {
13031 .fb_create = intel_user_framebuffer_create,
13032 .output_poll_changed = intel_fbdev_output_poll_changed,
13033 .atomic_check = intel_atomic_check,
13034 .atomic_commit = intel_atomic_commit,
13035 };
13036
13037 /* Set up chip specific display functions */
13038 static void intel_init_display(struct drm_device *dev)
13039 {
13040 struct drm_i915_private *dev_priv = dev->dev_private;
13041
13042 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
13043 dev_priv->display.find_dpll = g4x_find_best_dpll;
13044 else if (IS_CHERRYVIEW(dev))
13045 dev_priv->display.find_dpll = chv_find_best_dpll;
13046 else if (IS_VALLEYVIEW(dev))
13047 dev_priv->display.find_dpll = vlv_find_best_dpll;
13048 else if (IS_PINEVIEW(dev))
13049 dev_priv->display.find_dpll = pnv_find_best_dpll;
13050 else
13051 dev_priv->display.find_dpll = i9xx_find_best_dpll;
13052
13053 if (INTEL_INFO(dev)->gen >= 9) {
13054 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
13055 dev_priv->display.get_initial_plane_config =
13056 skylake_get_initial_plane_config;
13057 dev_priv->display.crtc_compute_clock =
13058 haswell_crtc_compute_clock;
13059 dev_priv->display.crtc_enable = haswell_crtc_enable;
13060 dev_priv->display.crtc_disable = haswell_crtc_disable;
13061 dev_priv->display.off = ironlake_crtc_off;
13062 dev_priv->display.update_primary_plane =
13063 skylake_update_primary_plane;
13064 } else if (HAS_DDI(dev)) {
13065 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
13066 dev_priv->display.get_initial_plane_config =
13067 ironlake_get_initial_plane_config;
13068 dev_priv->display.crtc_compute_clock =
13069 haswell_crtc_compute_clock;
13070 dev_priv->display.crtc_enable = haswell_crtc_enable;
13071 dev_priv->display.crtc_disable = haswell_crtc_disable;
13072 dev_priv->display.off = ironlake_crtc_off;
13073 dev_priv->display.update_primary_plane =
13074 ironlake_update_primary_plane;
13075 } else if (HAS_PCH_SPLIT(dev)) {
13076 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
13077 dev_priv->display.get_initial_plane_config =
13078 ironlake_get_initial_plane_config;
13079 dev_priv->display.crtc_compute_clock =
13080 ironlake_crtc_compute_clock;
13081 dev_priv->display.crtc_enable = ironlake_crtc_enable;
13082 dev_priv->display.crtc_disable = ironlake_crtc_disable;
13083 dev_priv->display.off = ironlake_crtc_off;
13084 dev_priv->display.update_primary_plane =
13085 ironlake_update_primary_plane;
13086 } else if (IS_VALLEYVIEW(dev)) {
13087 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13088 dev_priv->display.get_initial_plane_config =
13089 i9xx_get_initial_plane_config;
13090 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
13091 dev_priv->display.crtc_enable = valleyview_crtc_enable;
13092 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13093 dev_priv->display.off = i9xx_crtc_off;
13094 dev_priv->display.update_primary_plane =
13095 i9xx_update_primary_plane;
13096 } else {
13097 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13098 dev_priv->display.get_initial_plane_config =
13099 i9xx_get_initial_plane_config;
13100 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
13101 dev_priv->display.crtc_enable = i9xx_crtc_enable;
13102 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13103 dev_priv->display.off = i9xx_crtc_off;
13104 dev_priv->display.update_primary_plane =
13105 i9xx_update_primary_plane;
13106 }
13107
13108 /* Returns the core display clock speed */
13109 if (IS_VALLEYVIEW(dev))
13110 dev_priv->display.get_display_clock_speed =
13111 valleyview_get_display_clock_speed;
13112 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
13113 dev_priv->display.get_display_clock_speed =
13114 i945_get_display_clock_speed;
13115 else if (IS_I915G(dev))
13116 dev_priv->display.get_display_clock_speed =
13117 i915_get_display_clock_speed;
13118 else if (IS_I945GM(dev) || IS_845G(dev))
13119 dev_priv->display.get_display_clock_speed =
13120 i9xx_misc_get_display_clock_speed;
13121 else if (IS_PINEVIEW(dev))
13122 dev_priv->display.get_display_clock_speed =
13123 pnv_get_display_clock_speed;
13124 else if (IS_I915GM(dev))
13125 dev_priv->display.get_display_clock_speed =
13126 i915gm_get_display_clock_speed;
13127 else if (IS_I865G(dev))
13128 dev_priv->display.get_display_clock_speed =
13129 i865_get_display_clock_speed;
13130 else if (IS_I85X(dev))
13131 dev_priv->display.get_display_clock_speed =
13132 i855_get_display_clock_speed;
13133 else /* 852, 830 */
13134 dev_priv->display.get_display_clock_speed =
13135 i830_get_display_clock_speed;
13136
13137 if (IS_GEN5(dev)) {
13138 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
13139 } else if (IS_GEN6(dev)) {
13140 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
13141 } else if (IS_IVYBRIDGE(dev)) {
13142 /* FIXME: detect B0+ stepping and use auto training */
13143 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
13144 dev_priv->display.modeset_global_resources =
13145 ivb_modeset_global_resources;
13146 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
13147 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
13148 } else if (IS_VALLEYVIEW(dev)) {
13149 dev_priv->display.modeset_global_resources =
13150 valleyview_modeset_global_resources;
13151 }
13152
13153 switch (INTEL_INFO(dev)->gen) {
13154 case 2:
13155 dev_priv->display.queue_flip = intel_gen2_queue_flip;
13156 break;
13157
13158 case 3:
13159 dev_priv->display.queue_flip = intel_gen3_queue_flip;
13160 break;
13161
13162 case 4:
13163 case 5:
13164 dev_priv->display.queue_flip = intel_gen4_queue_flip;
13165 break;
13166
13167 case 6:
13168 dev_priv->display.queue_flip = intel_gen6_queue_flip;
13169 break;
13170 case 7:
13171 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
13172 dev_priv->display.queue_flip = intel_gen7_queue_flip;
13173 break;
13174 case 9:
13175 /* Drop through - unsupported since execlist only. */
13176 default:
13177 /* Default just returns -ENODEV to indicate unsupported */
13178 dev_priv->display.queue_flip = intel_default_queue_flip;
13179 }
13180
13181 intel_panel_init_backlight_funcs(dev);
13182
13183 mutex_init(&dev_priv->pps_mutex);
13184 }
13185
13186 /*
13187 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
13188 * resume, or other times. This quirk makes sure that's the case for
13189 * affected systems.
13190 */
13191 static void quirk_pipea_force(struct drm_device *dev)
13192 {
13193 struct drm_i915_private *dev_priv = dev->dev_private;
13194
13195 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
13196 DRM_INFO("applying pipe a force quirk\n");
13197 }
13198
13199 static void quirk_pipeb_force(struct drm_device *dev)
13200 {
13201 struct drm_i915_private *dev_priv = dev->dev_private;
13202
13203 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
13204 DRM_INFO("applying pipe b force quirk\n");
13205 }
13206
13207 /*
13208 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
13209 */
13210 static void quirk_ssc_force_disable(struct drm_device *dev)
13211 {
13212 struct drm_i915_private *dev_priv = dev->dev_private;
13213 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
13214 DRM_INFO("applying lvds SSC disable quirk\n");
13215 }
13216
13217 /*
13218 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
13219 * brightness value
13220 */
13221 static void quirk_invert_brightness(struct drm_device *dev)
13222 {
13223 struct drm_i915_private *dev_priv = dev->dev_private;
13224 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
13225 DRM_INFO("applying inverted panel brightness quirk\n");
13226 }
13227
13228 /* Some VBT's incorrectly indicate no backlight is present */
13229 static void quirk_backlight_present(struct drm_device *dev)
13230 {
13231 struct drm_i915_private *dev_priv = dev->dev_private;
13232 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
13233 DRM_INFO("applying backlight present quirk\n");
13234 }
13235
13236 struct intel_quirk {
13237 int device;
13238 int subsystem_vendor;
13239 int subsystem_device;
13240 void (*hook)(struct drm_device *dev);
13241 };
13242
13243 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
13244 struct intel_dmi_quirk {
13245 void (*hook)(struct drm_device *dev);
13246 const struct dmi_system_id (*dmi_id_list)[];
13247 };
13248
13249 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
13250 {
13251 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
13252 return 1;
13253 }
13254
13255 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
13256 {
13257 .dmi_id_list = &(const struct dmi_system_id[]) {
13258 {
13259 .callback = intel_dmi_reverse_brightness,
13260 .ident = "NCR Corporation",
13261 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
13262 DMI_MATCH(DMI_PRODUCT_NAME, ""),
13263 },
13264 },
13265 { } /* terminating entry */
13266 },
13267 .hook = quirk_invert_brightness,
13268 },
13269 };
13270
13271 static struct intel_quirk intel_quirks[] = {
13272 /* HP Mini needs pipe A force quirk (LP: #322104) */
13273 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
13274
13275 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
13276 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
13277
13278 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
13279 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
13280
13281 /* 830 needs to leave pipe A & dpll A up */
13282 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
13283
13284 /* 830 needs to leave pipe B & dpll B up */
13285 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
13286
13287 /* Lenovo U160 cannot use SSC on LVDS */
13288 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
13289
13290 /* Sony Vaio Y cannot use SSC on LVDS */
13291 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
13292
13293 /* Acer Aspire 5734Z must invert backlight brightness */
13294 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
13295
13296 /* Acer/eMachines G725 */
13297 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
13298
13299 /* Acer/eMachines e725 */
13300 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
13301
13302 /* Acer/Packard Bell NCL20 */
13303 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
13304
13305 /* Acer Aspire 4736Z */
13306 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
13307
13308 /* Acer Aspire 5336 */
13309 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
13310
13311 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
13312 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
13313
13314 /* Acer C720 Chromebook (Core i3 4005U) */
13315 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
13316
13317 /* Apple Macbook 2,1 (Core 2 T7400) */
13318 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
13319
13320 /* Toshiba CB35 Chromebook (Celeron 2955U) */
13321 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
13322
13323 /* HP Chromebook 14 (Celeron 2955U) */
13324 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
13325
13326 /* Dell Chromebook 11 */
13327 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
13328 };
13329
13330 static void intel_init_quirks(struct drm_device *dev)
13331 {
13332 struct pci_dev *d = dev->pdev;
13333 int i;
13334
13335 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
13336 struct intel_quirk *q = &intel_quirks[i];
13337
13338 if (d->device == q->device &&
13339 (d->subsystem_vendor == q->subsystem_vendor ||
13340 q->subsystem_vendor == PCI_ANY_ID) &&
13341 (d->subsystem_device == q->subsystem_device ||
13342 q->subsystem_device == PCI_ANY_ID))
13343 q->hook(dev);
13344 }
13345 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
13346 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
13347 intel_dmi_quirks[i].hook(dev);
13348 }
13349 }
13350
13351 /* Disable the VGA plane that we never use */
13352 static void i915_disable_vga(struct drm_device *dev)
13353 {
13354 struct drm_i915_private *dev_priv = dev->dev_private;
13355 u8 sr1;
13356 u32 vga_reg = i915_vgacntrl_reg(dev);
13357
13358 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
13359 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
13360 outb(SR01, VGA_SR_INDEX);
13361 sr1 = inb(VGA_SR_DATA);
13362 outb(sr1 | 1<<5, VGA_SR_DATA);
13363 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
13364 udelay(300);
13365
13366 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
13367 POSTING_READ(vga_reg);
13368 }
13369
13370 void intel_modeset_init_hw(struct drm_device *dev)
13371 {
13372 intel_prepare_ddi(dev);
13373
13374 if (IS_VALLEYVIEW(dev))
13375 vlv_update_cdclk(dev);
13376
13377 intel_init_clock_gating(dev);
13378
13379 intel_enable_gt_powersave(dev);
13380 }
13381
13382 void intel_modeset_init(struct drm_device *dev)
13383 {
13384 struct drm_i915_private *dev_priv = dev->dev_private;
13385 int sprite, ret;
13386 enum pipe pipe;
13387 struct intel_crtc *crtc;
13388
13389 drm_mode_config_init(dev);
13390
13391 dev->mode_config.min_width = 0;
13392 dev->mode_config.min_height = 0;
13393
13394 dev->mode_config.preferred_depth = 24;
13395 dev->mode_config.prefer_shadow = 1;
13396
13397 dev->mode_config.allow_fb_modifiers = true;
13398
13399 dev->mode_config.funcs = &intel_mode_funcs;
13400
13401 intel_init_quirks(dev);
13402
13403 intel_init_pm(dev);
13404
13405 if (INTEL_INFO(dev)->num_pipes == 0)
13406 return;
13407
13408 intel_init_display(dev);
13409 intel_init_audio(dev);
13410
13411 if (IS_GEN2(dev)) {
13412 dev->mode_config.max_width = 2048;
13413 dev->mode_config.max_height = 2048;
13414 } else if (IS_GEN3(dev)) {
13415 dev->mode_config.max_width = 4096;
13416 dev->mode_config.max_height = 4096;
13417 } else {
13418 dev->mode_config.max_width = 8192;
13419 dev->mode_config.max_height = 8192;
13420 }
13421
13422 if (IS_845G(dev) || IS_I865G(dev)) {
13423 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
13424 dev->mode_config.cursor_height = 1023;
13425 } else if (IS_GEN2(dev)) {
13426 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
13427 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
13428 } else {
13429 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
13430 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
13431 }
13432
13433 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
13434
13435 DRM_DEBUG_KMS("%d display pipe%s available.\n",
13436 INTEL_INFO(dev)->num_pipes,
13437 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
13438
13439 for_each_pipe(dev_priv, pipe) {
13440 intel_crtc_init(dev, pipe);
13441 for_each_sprite(dev_priv, pipe, sprite) {
13442 ret = intel_plane_init(dev, pipe, sprite);
13443 if (ret)
13444 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
13445 pipe_name(pipe), sprite_name(pipe, sprite), ret);
13446 }
13447 }
13448
13449 intel_init_dpio(dev);
13450
13451 intel_shared_dpll_init(dev);
13452
13453 /* Just disable it once at startup */
13454 i915_disable_vga(dev);
13455 intel_setup_outputs(dev);
13456
13457 /* Just in case the BIOS is doing something questionable. */
13458 intel_fbc_disable(dev);
13459
13460 drm_modeset_lock_all(dev);
13461 intel_modeset_setup_hw_state(dev, false);
13462 drm_modeset_unlock_all(dev);
13463
13464 for_each_intel_crtc(dev, crtc) {
13465 if (!crtc->active)
13466 continue;
13467
13468 /*
13469 * Note that reserving the BIOS fb up front prevents us
13470 * from stuffing other stolen allocations like the ring
13471 * on top. This prevents some ugliness at boot time, and
13472 * can even allow for smooth boot transitions if the BIOS
13473 * fb is large enough for the active pipe configuration.
13474 */
13475 if (dev_priv->display.get_initial_plane_config) {
13476 dev_priv->display.get_initial_plane_config(crtc,
13477 &crtc->plane_config);
13478 /*
13479 * If the fb is shared between multiple heads, we'll
13480 * just get the first one.
13481 */
13482 intel_find_plane_obj(crtc, &crtc->plane_config);
13483 }
13484 }
13485 }
13486
13487 static void intel_enable_pipe_a(struct drm_device *dev)
13488 {
13489 struct intel_connector *connector;
13490 struct drm_connector *crt = NULL;
13491 struct intel_load_detect_pipe load_detect_temp;
13492 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
13493
13494 /* We can't just switch on the pipe A, we need to set things up with a
13495 * proper mode and output configuration. As a gross hack, enable pipe A
13496 * by enabling the load detect pipe once. */
13497 for_each_intel_connector(dev, connector) {
13498 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13499 crt = &connector->base;
13500 break;
13501 }
13502 }
13503
13504 if (!crt)
13505 return;
13506
13507 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13508 intel_release_load_detect_pipe(crt, &load_detect_temp);
13509 }
13510
13511 static bool
13512 intel_check_plane_mapping(struct intel_crtc *crtc)
13513 {
13514 struct drm_device *dev = crtc->base.dev;
13515 struct drm_i915_private *dev_priv = dev->dev_private;
13516 u32 reg, val;
13517
13518 if (INTEL_INFO(dev)->num_pipes == 1)
13519 return true;
13520
13521 reg = DSPCNTR(!crtc->plane);
13522 val = I915_READ(reg);
13523
13524 if ((val & DISPLAY_PLANE_ENABLE) &&
13525 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13526 return false;
13527
13528 return true;
13529 }
13530
13531 static void intel_sanitize_crtc(struct intel_crtc *crtc)
13532 {
13533 struct drm_device *dev = crtc->base.dev;
13534 struct drm_i915_private *dev_priv = dev->dev_private;
13535 u32 reg;
13536
13537 /* Clear any frame start delays used for debugging left by the BIOS */
13538 reg = PIPECONF(crtc->config->cpu_transcoder);
13539 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13540
13541 /* restore vblank interrupts to correct state */
13542 drm_crtc_vblank_reset(&crtc->base);
13543 if (crtc->active) {
13544 update_scanline_offset(crtc);
13545 drm_crtc_vblank_on(&crtc->base);
13546 }
13547
13548 /* We need to sanitize the plane -> pipe mapping first because this will
13549 * disable the crtc (and hence change the state) if it is wrong. Note
13550 * that gen4+ has a fixed plane -> pipe mapping. */
13551 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13552 struct intel_connector *connector;
13553 bool plane;
13554
13555 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13556 crtc->base.base.id);
13557
13558 /* Pipe has the wrong plane attached and the plane is active.
13559 * Temporarily change the plane mapping and disable everything
13560 * ... */
13561 plane = crtc->plane;
13562 crtc->plane = !plane;
13563 crtc->primary_enabled = true;
13564 dev_priv->display.crtc_disable(&crtc->base);
13565 crtc->plane = plane;
13566
13567 /* ... and break all links. */
13568 for_each_intel_connector(dev, connector) {
13569 if (connector->encoder->base.crtc != &crtc->base)
13570 continue;
13571
13572 connector->base.dpms = DRM_MODE_DPMS_OFF;
13573 connector->base.encoder = NULL;
13574 }
13575 /* multiple connectors may have the same encoder:
13576 * handle them and break crtc link separately */
13577 for_each_intel_connector(dev, connector)
13578 if (connector->encoder->base.crtc == &crtc->base) {
13579 connector->encoder->base.crtc = NULL;
13580 connector->encoder->connectors_active = false;
13581 }
13582
13583 WARN_ON(crtc->active);
13584 crtc->base.state->enable = false;
13585 crtc->base.enabled = false;
13586 }
13587
13588 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13589 crtc->pipe == PIPE_A && !crtc->active) {
13590 /* BIOS forgot to enable pipe A, this mostly happens after
13591 * resume. Force-enable the pipe to fix this, the update_dpms
13592 * call below we restore the pipe to the right state, but leave
13593 * the required bits on. */
13594 intel_enable_pipe_a(dev);
13595 }
13596
13597 /* Adjust the state of the output pipe according to whether we
13598 * have active connectors/encoders. */
13599 intel_crtc_update_dpms(&crtc->base);
13600
13601 if (crtc->active != crtc->base.state->enable) {
13602 struct intel_encoder *encoder;
13603
13604 /* This can happen either due to bugs in the get_hw_state
13605 * functions or because the pipe is force-enabled due to the
13606 * pipe A quirk. */
13607 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13608 crtc->base.base.id,
13609 crtc->base.state->enable ? "enabled" : "disabled",
13610 crtc->active ? "enabled" : "disabled");
13611
13612 crtc->base.state->enable = crtc->active;
13613 crtc->base.enabled = crtc->active;
13614
13615 /* Because we only establish the connector -> encoder ->
13616 * crtc links if something is active, this means the
13617 * crtc is now deactivated. Break the links. connector
13618 * -> encoder links are only establish when things are
13619 * actually up, hence no need to break them. */
13620 WARN_ON(crtc->active);
13621
13622 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13623 WARN_ON(encoder->connectors_active);
13624 encoder->base.crtc = NULL;
13625 }
13626 }
13627
13628 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13629 /*
13630 * We start out with underrun reporting disabled to avoid races.
13631 * For correct bookkeeping mark this on active crtcs.
13632 *
13633 * Also on gmch platforms we dont have any hardware bits to
13634 * disable the underrun reporting. Which means we need to start
13635 * out with underrun reporting disabled also on inactive pipes,
13636 * since otherwise we'll complain about the garbage we read when
13637 * e.g. coming up after runtime pm.
13638 *
13639 * No protection against concurrent access is required - at
13640 * worst a fifo underrun happens which also sets this to false.
13641 */
13642 crtc->cpu_fifo_underrun_disabled = true;
13643 crtc->pch_fifo_underrun_disabled = true;
13644 }
13645 }
13646
13647 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13648 {
13649 struct intel_connector *connector;
13650 struct drm_device *dev = encoder->base.dev;
13651
13652 /* We need to check both for a crtc link (meaning that the
13653 * encoder is active and trying to read from a pipe) and the
13654 * pipe itself being active. */
13655 bool has_active_crtc = encoder->base.crtc &&
13656 to_intel_crtc(encoder->base.crtc)->active;
13657
13658 if (encoder->connectors_active && !has_active_crtc) {
13659 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13660 encoder->base.base.id,
13661 encoder->base.name);
13662
13663 /* Connector is active, but has no active pipe. This is
13664 * fallout from our resume register restoring. Disable
13665 * the encoder manually again. */
13666 if (encoder->base.crtc) {
13667 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13668 encoder->base.base.id,
13669 encoder->base.name);
13670 encoder->disable(encoder);
13671 if (encoder->post_disable)
13672 encoder->post_disable(encoder);
13673 }
13674 encoder->base.crtc = NULL;
13675 encoder->connectors_active = false;
13676
13677 /* Inconsistent output/port/pipe state happens presumably due to
13678 * a bug in one of the get_hw_state functions. Or someplace else
13679 * in our code, like the register restore mess on resume. Clamp
13680 * things to off as a safer default. */
13681 for_each_intel_connector(dev, connector) {
13682 if (connector->encoder != encoder)
13683 continue;
13684 connector->base.dpms = DRM_MODE_DPMS_OFF;
13685 connector->base.encoder = NULL;
13686 }
13687 }
13688 /* Enabled encoders without active connectors will be fixed in
13689 * the crtc fixup. */
13690 }
13691
13692 void i915_redisable_vga_power_on(struct drm_device *dev)
13693 {
13694 struct drm_i915_private *dev_priv = dev->dev_private;
13695 u32 vga_reg = i915_vgacntrl_reg(dev);
13696
13697 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13698 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13699 i915_disable_vga(dev);
13700 }
13701 }
13702
13703 void i915_redisable_vga(struct drm_device *dev)
13704 {
13705 struct drm_i915_private *dev_priv = dev->dev_private;
13706
13707 /* This function can be called both from intel_modeset_setup_hw_state or
13708 * at a very early point in our resume sequence, where the power well
13709 * structures are not yet restored. Since this function is at a very
13710 * paranoid "someone might have enabled VGA while we were not looking"
13711 * level, just check if the power well is enabled instead of trying to
13712 * follow the "don't touch the power well if we don't need it" policy
13713 * the rest of the driver uses. */
13714 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
13715 return;
13716
13717 i915_redisable_vga_power_on(dev);
13718 }
13719
13720 static bool primary_get_hw_state(struct intel_crtc *crtc)
13721 {
13722 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13723
13724 if (!crtc->active)
13725 return false;
13726
13727 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13728 }
13729
13730 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13731 {
13732 struct drm_i915_private *dev_priv = dev->dev_private;
13733 enum pipe pipe;
13734 struct intel_crtc *crtc;
13735 struct intel_encoder *encoder;
13736 struct intel_connector *connector;
13737 int i;
13738
13739 for_each_intel_crtc(dev, crtc) {
13740 memset(crtc->config, 0, sizeof(*crtc->config));
13741
13742 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13743
13744 crtc->active = dev_priv->display.get_pipe_config(crtc,
13745 crtc->config);
13746
13747 crtc->base.state->enable = crtc->active;
13748 crtc->base.enabled = crtc->active;
13749 crtc->primary_enabled = primary_get_hw_state(crtc);
13750
13751 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13752 crtc->base.base.id,
13753 crtc->active ? "enabled" : "disabled");
13754 }
13755
13756 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13757 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13758
13759 pll->on = pll->get_hw_state(dev_priv, pll,
13760 &pll->config.hw_state);
13761 pll->active = 0;
13762 pll->config.crtc_mask = 0;
13763 for_each_intel_crtc(dev, crtc) {
13764 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
13765 pll->active++;
13766 pll->config.crtc_mask |= 1 << crtc->pipe;
13767 }
13768 }
13769
13770 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
13771 pll->name, pll->config.crtc_mask, pll->on);
13772
13773 if (pll->config.crtc_mask)
13774 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13775 }
13776
13777 for_each_intel_encoder(dev, encoder) {
13778 pipe = 0;
13779
13780 if (encoder->get_hw_state(encoder, &pipe)) {
13781 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13782 encoder->base.crtc = &crtc->base;
13783 encoder->get_config(encoder, crtc->config);
13784 } else {
13785 encoder->base.crtc = NULL;
13786 }
13787
13788 encoder->connectors_active = false;
13789 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13790 encoder->base.base.id,
13791 encoder->base.name,
13792 encoder->base.crtc ? "enabled" : "disabled",
13793 pipe_name(pipe));
13794 }
13795
13796 for_each_intel_connector(dev, connector) {
13797 if (connector->get_hw_state(connector)) {
13798 connector->base.dpms = DRM_MODE_DPMS_ON;
13799 connector->encoder->connectors_active = true;
13800 connector->base.encoder = &connector->encoder->base;
13801 } else {
13802 connector->base.dpms = DRM_MODE_DPMS_OFF;
13803 connector->base.encoder = NULL;
13804 }
13805 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13806 connector->base.base.id,
13807 connector->base.name,
13808 connector->base.encoder ? "enabled" : "disabled");
13809 }
13810 }
13811
13812 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13813 * and i915 state tracking structures. */
13814 void intel_modeset_setup_hw_state(struct drm_device *dev,
13815 bool force_restore)
13816 {
13817 struct drm_i915_private *dev_priv = dev->dev_private;
13818 enum pipe pipe;
13819 struct intel_crtc *crtc;
13820 struct intel_encoder *encoder;
13821 int i;
13822
13823 intel_modeset_readout_hw_state(dev);
13824
13825 /*
13826 * Now that we have the config, copy it to each CRTC struct
13827 * Note that this could go away if we move to using crtc_config
13828 * checking everywhere.
13829 */
13830 for_each_intel_crtc(dev, crtc) {
13831 if (crtc->active && i915.fastboot) {
13832 intel_mode_from_pipe_config(&crtc->base.mode,
13833 crtc->config);
13834 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13835 crtc->base.base.id);
13836 drm_mode_debug_printmodeline(&crtc->base.mode);
13837 }
13838 }
13839
13840 /* HW state is read out, now we need to sanitize this mess. */
13841 for_each_intel_encoder(dev, encoder) {
13842 intel_sanitize_encoder(encoder);
13843 }
13844
13845 for_each_pipe(dev_priv, pipe) {
13846 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13847 intel_sanitize_crtc(crtc);
13848 intel_dump_pipe_config(crtc, crtc->config,
13849 "[setup_hw_state]");
13850 }
13851
13852 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13853 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13854
13855 if (!pll->on || pll->active)
13856 continue;
13857
13858 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13859
13860 pll->disable(dev_priv, pll);
13861 pll->on = false;
13862 }
13863
13864 if (IS_GEN9(dev))
13865 skl_wm_get_hw_state(dev);
13866 else if (HAS_PCH_SPLIT(dev))
13867 ilk_wm_get_hw_state(dev);
13868
13869 if (force_restore) {
13870 i915_redisable_vga(dev);
13871
13872 /*
13873 * We need to use raw interfaces for restoring state to avoid
13874 * checking (bogus) intermediate states.
13875 */
13876 for_each_pipe(dev_priv, pipe) {
13877 struct drm_crtc *crtc =
13878 dev_priv->pipe_to_crtc_mapping[pipe];
13879
13880 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13881 crtc->primary->fb);
13882 }
13883 } else {
13884 intel_modeset_update_staged_output_state(dev);
13885 }
13886
13887 intel_modeset_check_state(dev);
13888 }
13889
13890 void intel_modeset_gem_init(struct drm_device *dev)
13891 {
13892 struct drm_i915_private *dev_priv = dev->dev_private;
13893 struct drm_crtc *c;
13894 struct drm_i915_gem_object *obj;
13895
13896 mutex_lock(&dev->struct_mutex);
13897 intel_init_gt_powersave(dev);
13898 mutex_unlock(&dev->struct_mutex);
13899
13900 /*
13901 * There may be no VBT; and if the BIOS enabled SSC we can
13902 * just keep using it to avoid unnecessary flicker. Whereas if the
13903 * BIOS isn't using it, don't assume it will work even if the VBT
13904 * indicates as much.
13905 */
13906 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13907 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
13908 DREF_SSC1_ENABLE);
13909
13910 intel_modeset_init_hw(dev);
13911
13912 intel_setup_overlay(dev);
13913
13914 /*
13915 * Make sure any fbs we allocated at startup are properly
13916 * pinned & fenced. When we do the allocation it's too early
13917 * for this.
13918 */
13919 mutex_lock(&dev->struct_mutex);
13920 for_each_crtc(dev, c) {
13921 obj = intel_fb_obj(c->primary->fb);
13922 if (obj == NULL)
13923 continue;
13924
13925 if (intel_pin_and_fence_fb_obj(c->primary,
13926 c->primary->fb,
13927 NULL)) {
13928 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13929 to_intel_crtc(c)->pipe);
13930 drm_framebuffer_unreference(c->primary->fb);
13931 c->primary->fb = NULL;
13932 update_state_fb(c->primary);
13933 }
13934 }
13935 mutex_unlock(&dev->struct_mutex);
13936
13937 intel_backlight_register(dev);
13938 }
13939
13940 void intel_connector_unregister(struct intel_connector *intel_connector)
13941 {
13942 struct drm_connector *connector = &intel_connector->base;
13943
13944 intel_panel_destroy_backlight(connector);
13945 drm_connector_unregister(connector);
13946 }
13947
13948 void intel_modeset_cleanup(struct drm_device *dev)
13949 {
13950 struct drm_i915_private *dev_priv = dev->dev_private;
13951 struct drm_connector *connector;
13952
13953 intel_disable_gt_powersave(dev);
13954
13955 intel_backlight_unregister(dev);
13956
13957 /*
13958 * Interrupts and polling as the first thing to avoid creating havoc.
13959 * Too much stuff here (turning of connectors, ...) would
13960 * experience fancy races otherwise.
13961 */
13962 intel_irq_uninstall(dev_priv);
13963
13964 /*
13965 * Due to the hpd irq storm handling the hotplug work can re-arm the
13966 * poll handlers. Hence disable polling after hpd handling is shut down.
13967 */
13968 drm_kms_helper_poll_fini(dev);
13969
13970 mutex_lock(&dev->struct_mutex);
13971
13972 intel_unregister_dsm_handler();
13973
13974 intel_fbc_disable(dev);
13975
13976 mutex_unlock(&dev->struct_mutex);
13977
13978 /* flush any delayed tasks or pending work */
13979 flush_scheduled_work();
13980
13981 /* destroy the backlight and sysfs files before encoders/connectors */
13982 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13983 struct intel_connector *intel_connector;
13984
13985 intel_connector = to_intel_connector(connector);
13986 intel_connector->unregister(intel_connector);
13987 }
13988
13989 drm_mode_config_cleanup(dev);
13990
13991 intel_cleanup_overlay(dev);
13992
13993 mutex_lock(&dev->struct_mutex);
13994 intel_cleanup_gt_powersave(dev);
13995 mutex_unlock(&dev->struct_mutex);
13996 }
13997
13998 /*
13999 * Return which encoder is currently attached for connector.
14000 */
14001 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
14002 {
14003 return &intel_attached_encoder(connector)->base;
14004 }
14005
14006 void intel_connector_attach_encoder(struct intel_connector *connector,
14007 struct intel_encoder *encoder)
14008 {
14009 connector->encoder = encoder;
14010 drm_mode_connector_attach_encoder(&connector->base,
14011 &encoder->base);
14012 }
14013
14014 /*
14015 * set vga decode state - true == enable VGA decode
14016 */
14017 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
14018 {
14019 struct drm_i915_private *dev_priv = dev->dev_private;
14020 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
14021 u16 gmch_ctrl;
14022
14023 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
14024 DRM_ERROR("failed to read control word\n");
14025 return -EIO;
14026 }
14027
14028 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
14029 return 0;
14030
14031 if (state)
14032 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
14033 else
14034 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
14035
14036 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
14037 DRM_ERROR("failed to write control word\n");
14038 return -EIO;
14039 }
14040
14041 return 0;
14042 }
14043
14044 struct intel_display_error_state {
14045
14046 u32 power_well_driver;
14047
14048 int num_transcoders;
14049
14050 struct intel_cursor_error_state {
14051 u32 control;
14052 u32 position;
14053 u32 base;
14054 u32 size;
14055 } cursor[I915_MAX_PIPES];
14056
14057 struct intel_pipe_error_state {
14058 bool power_domain_on;
14059 u32 source;
14060 u32 stat;
14061 } pipe[I915_MAX_PIPES];
14062
14063 struct intel_plane_error_state {
14064 u32 control;
14065 u32 stride;
14066 u32 size;
14067 u32 pos;
14068 u32 addr;
14069 u32 surface;
14070 u32 tile_offset;
14071 } plane[I915_MAX_PIPES];
14072
14073 struct intel_transcoder_error_state {
14074 bool power_domain_on;
14075 enum transcoder cpu_transcoder;
14076
14077 u32 conf;
14078
14079 u32 htotal;
14080 u32 hblank;
14081 u32 hsync;
14082 u32 vtotal;
14083 u32 vblank;
14084 u32 vsync;
14085 } transcoder[4];
14086 };
14087
14088 struct intel_display_error_state *
14089 intel_display_capture_error_state(struct drm_device *dev)
14090 {
14091 struct drm_i915_private *dev_priv = dev->dev_private;
14092 struct intel_display_error_state *error;
14093 int transcoders[] = {
14094 TRANSCODER_A,
14095 TRANSCODER_B,
14096 TRANSCODER_C,
14097 TRANSCODER_EDP,
14098 };
14099 int i;
14100
14101 if (INTEL_INFO(dev)->num_pipes == 0)
14102 return NULL;
14103
14104 error = kzalloc(sizeof(*error), GFP_ATOMIC);
14105 if (error == NULL)
14106 return NULL;
14107
14108 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
14109 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
14110
14111 for_each_pipe(dev_priv, i) {
14112 error->pipe[i].power_domain_on =
14113 __intel_display_power_is_enabled(dev_priv,
14114 POWER_DOMAIN_PIPE(i));
14115 if (!error->pipe[i].power_domain_on)
14116 continue;
14117
14118 error->cursor[i].control = I915_READ(CURCNTR(i));
14119 error->cursor[i].position = I915_READ(CURPOS(i));
14120 error->cursor[i].base = I915_READ(CURBASE(i));
14121
14122 error->plane[i].control = I915_READ(DSPCNTR(i));
14123 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
14124 if (INTEL_INFO(dev)->gen <= 3) {
14125 error->plane[i].size = I915_READ(DSPSIZE(i));
14126 error->plane[i].pos = I915_READ(DSPPOS(i));
14127 }
14128 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14129 error->plane[i].addr = I915_READ(DSPADDR(i));
14130 if (INTEL_INFO(dev)->gen >= 4) {
14131 error->plane[i].surface = I915_READ(DSPSURF(i));
14132 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
14133 }
14134
14135 error->pipe[i].source = I915_READ(PIPESRC(i));
14136
14137 if (HAS_GMCH_DISPLAY(dev))
14138 error->pipe[i].stat = I915_READ(PIPESTAT(i));
14139 }
14140
14141 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
14142 if (HAS_DDI(dev_priv->dev))
14143 error->num_transcoders++; /* Account for eDP. */
14144
14145 for (i = 0; i < error->num_transcoders; i++) {
14146 enum transcoder cpu_transcoder = transcoders[i];
14147
14148 error->transcoder[i].power_domain_on =
14149 __intel_display_power_is_enabled(dev_priv,
14150 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
14151 if (!error->transcoder[i].power_domain_on)
14152 continue;
14153
14154 error->transcoder[i].cpu_transcoder = cpu_transcoder;
14155
14156 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
14157 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
14158 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
14159 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
14160 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
14161 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
14162 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
14163 }
14164
14165 return error;
14166 }
14167
14168 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
14169
14170 void
14171 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
14172 struct drm_device *dev,
14173 struct intel_display_error_state *error)
14174 {
14175 struct drm_i915_private *dev_priv = dev->dev_private;
14176 int i;
14177
14178 if (!error)
14179 return;
14180
14181 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
14182 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
14183 err_printf(m, "PWR_WELL_CTL2: %08x\n",
14184 error->power_well_driver);
14185 for_each_pipe(dev_priv, i) {
14186 err_printf(m, "Pipe [%d]:\n", i);
14187 err_printf(m, " Power: %s\n",
14188 error->pipe[i].power_domain_on ? "on" : "off");
14189 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
14190 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
14191
14192 err_printf(m, "Plane [%d]:\n", i);
14193 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
14194 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
14195 if (INTEL_INFO(dev)->gen <= 3) {
14196 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
14197 err_printf(m, " POS: %08x\n", error->plane[i].pos);
14198 }
14199 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14200 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
14201 if (INTEL_INFO(dev)->gen >= 4) {
14202 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
14203 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
14204 }
14205
14206 err_printf(m, "Cursor [%d]:\n", i);
14207 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
14208 err_printf(m, " POS: %08x\n", error->cursor[i].position);
14209 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
14210 }
14211
14212 for (i = 0; i < error->num_transcoders; i++) {
14213 err_printf(m, "CPU transcoder: %c\n",
14214 transcoder_name(error->transcoder[i].cpu_transcoder));
14215 err_printf(m, " Power: %s\n",
14216 error->transcoder[i].power_domain_on ? "on" : "off");
14217 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
14218 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
14219 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
14220 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
14221 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
14222 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
14223 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
14224 }
14225 }
14226
14227 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
14228 {
14229 struct intel_crtc *crtc;
14230
14231 for_each_intel_crtc(dev, crtc) {
14232 struct intel_unpin_work *work;
14233
14234 spin_lock_irq(&dev->event_lock);
14235
14236 work = crtc->unpin_work;
14237
14238 if (work && work->event &&
14239 work->event->base.file_priv == file) {
14240 kfree(work->event);
14241 work->event = NULL;
14242 }
14243
14244 spin_unlock_irq(&dev->event_lock);
14245 }
14246 }
Linux kernel - Deliverables
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