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Merge tag 'asoc-v3.18-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie...
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_rect.h>
44 #include <linux/dma_remapping.h>
45
46 /* Primary plane formats supported by all gen */
47 #define COMMON_PRIMARY_FORMATS \
48 DRM_FORMAT_C8, \
49 DRM_FORMAT_RGB565, \
50 DRM_FORMAT_XRGB8888, \
51 DRM_FORMAT_ARGB8888
52
53 /* Primary plane formats for gen <= 3 */
54 static const uint32_t intel_primary_formats_gen2[] = {
55 COMMON_PRIMARY_FORMATS,
56 DRM_FORMAT_XRGB1555,
57 DRM_FORMAT_ARGB1555,
58 };
59
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t intel_primary_formats_gen4[] = {
62 COMMON_PRIMARY_FORMATS, \
63 DRM_FORMAT_XBGR8888,
64 DRM_FORMAT_ABGR8888,
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_ARGB2101010,
67 DRM_FORMAT_XBGR2101010,
68 DRM_FORMAT_ABGR2101010,
69 };
70
71 /* Cursor formats */
72 static const uint32_t intel_cursor_formats[] = {
73 DRM_FORMAT_ARGB8888,
74 };
75
76 static void intel_increase_pllclock(struct drm_device *dev,
77 enum pipe pipe);
78 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79
80 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
81 struct intel_crtc_config *pipe_config);
82 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
83 struct intel_crtc_config *pipe_config);
84
85 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
86 int x, int y, struct drm_framebuffer *old_fb);
87 static int intel_framebuffer_init(struct drm_device *dev,
88 struct intel_framebuffer *ifb,
89 struct drm_mode_fb_cmd2 *mode_cmd,
90 struct drm_i915_gem_object *obj);
91 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
92 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
93 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
94 struct intel_link_m_n *m_n,
95 struct intel_link_m_n *m2_n2);
96 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
97 static void haswell_set_pipeconf(struct drm_crtc *crtc);
98 static void intel_set_pipe_csc(struct drm_crtc *crtc);
99 static void vlv_prepare_pll(struct intel_crtc *crtc);
100 static void chv_prepare_pll(struct intel_crtc *crtc);
101
102 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
103 {
104 if (!connector->mst_port)
105 return connector->encoder;
106 else
107 return &connector->mst_port->mst_encoders[pipe]->base;
108 }
109
110 typedef struct {
111 int min, max;
112 } intel_range_t;
113
114 typedef struct {
115 int dot_limit;
116 int p2_slow, p2_fast;
117 } intel_p2_t;
118
119 typedef struct intel_limit intel_limit_t;
120 struct intel_limit {
121 intel_range_t dot, vco, n, m, m1, m2, p, p1;
122 intel_p2_t p2;
123 };
124
125 int
126 intel_pch_rawclk(struct drm_device *dev)
127 {
128 struct drm_i915_private *dev_priv = dev->dev_private;
129
130 WARN_ON(!HAS_PCH_SPLIT(dev));
131
132 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
133 }
134
135 static inline u32 /* units of 100MHz */
136 intel_fdi_link_freq(struct drm_device *dev)
137 {
138 if (IS_GEN5(dev)) {
139 struct drm_i915_private *dev_priv = dev->dev_private;
140 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
141 } else
142 return 27;
143 }
144
145 static const intel_limit_t intel_limits_i8xx_dac = {
146 .dot = { .min = 25000, .max = 350000 },
147 .vco = { .min = 908000, .max = 1512000 },
148 .n = { .min = 2, .max = 16 },
149 .m = { .min = 96, .max = 140 },
150 .m1 = { .min = 18, .max = 26 },
151 .m2 = { .min = 6, .max = 16 },
152 .p = { .min = 4, .max = 128 },
153 .p1 = { .min = 2, .max = 33 },
154 .p2 = { .dot_limit = 165000,
155 .p2_slow = 4, .p2_fast = 2 },
156 };
157
158 static const intel_limit_t intel_limits_i8xx_dvo = {
159 .dot = { .min = 25000, .max = 350000 },
160 .vco = { .min = 908000, .max = 1512000 },
161 .n = { .min = 2, .max = 16 },
162 .m = { .min = 96, .max = 140 },
163 .m1 = { .min = 18, .max = 26 },
164 .m2 = { .min = 6, .max = 16 },
165 .p = { .min = 4, .max = 128 },
166 .p1 = { .min = 2, .max = 33 },
167 .p2 = { .dot_limit = 165000,
168 .p2_slow = 4, .p2_fast = 4 },
169 };
170
171 static const intel_limit_t intel_limits_i8xx_lvds = {
172 .dot = { .min = 25000, .max = 350000 },
173 .vco = { .min = 908000, .max = 1512000 },
174 .n = { .min = 2, .max = 16 },
175 .m = { .min = 96, .max = 140 },
176 .m1 = { .min = 18, .max = 26 },
177 .m2 = { .min = 6, .max = 16 },
178 .p = { .min = 4, .max = 128 },
179 .p1 = { .min = 1, .max = 6 },
180 .p2 = { .dot_limit = 165000,
181 .p2_slow = 14, .p2_fast = 7 },
182 };
183
184 static const intel_limit_t intel_limits_i9xx_sdvo = {
185 .dot = { .min = 20000, .max = 400000 },
186 .vco = { .min = 1400000, .max = 2800000 },
187 .n = { .min = 1, .max = 6 },
188 .m = { .min = 70, .max = 120 },
189 .m1 = { .min = 8, .max = 18 },
190 .m2 = { .min = 3, .max = 7 },
191 .p = { .min = 5, .max = 80 },
192 .p1 = { .min = 1, .max = 8 },
193 .p2 = { .dot_limit = 200000,
194 .p2_slow = 10, .p2_fast = 5 },
195 };
196
197 static const intel_limit_t intel_limits_i9xx_lvds = {
198 .dot = { .min = 20000, .max = 400000 },
199 .vco = { .min = 1400000, .max = 2800000 },
200 .n = { .min = 1, .max = 6 },
201 .m = { .min = 70, .max = 120 },
202 .m1 = { .min = 8, .max = 18 },
203 .m2 = { .min = 3, .max = 7 },
204 .p = { .min = 7, .max = 98 },
205 .p1 = { .min = 1, .max = 8 },
206 .p2 = { .dot_limit = 112000,
207 .p2_slow = 14, .p2_fast = 7 },
208 };
209
210
211 static const intel_limit_t intel_limits_g4x_sdvo = {
212 .dot = { .min = 25000, .max = 270000 },
213 .vco = { .min = 1750000, .max = 3500000},
214 .n = { .min = 1, .max = 4 },
215 .m = { .min = 104, .max = 138 },
216 .m1 = { .min = 17, .max = 23 },
217 .m2 = { .min = 5, .max = 11 },
218 .p = { .min = 10, .max = 30 },
219 .p1 = { .min = 1, .max = 3},
220 .p2 = { .dot_limit = 270000,
221 .p2_slow = 10,
222 .p2_fast = 10
223 },
224 };
225
226 static const intel_limit_t intel_limits_g4x_hdmi = {
227 .dot = { .min = 22000, .max = 400000 },
228 .vco = { .min = 1750000, .max = 3500000},
229 .n = { .min = 1, .max = 4 },
230 .m = { .min = 104, .max = 138 },
231 .m1 = { .min = 16, .max = 23 },
232 .m2 = { .min = 5, .max = 11 },
233 .p = { .min = 5, .max = 80 },
234 .p1 = { .min = 1, .max = 8},
235 .p2 = { .dot_limit = 165000,
236 .p2_slow = 10, .p2_fast = 5 },
237 };
238
239 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
240 .dot = { .min = 20000, .max = 115000 },
241 .vco = { .min = 1750000, .max = 3500000 },
242 .n = { .min = 1, .max = 3 },
243 .m = { .min = 104, .max = 138 },
244 .m1 = { .min = 17, .max = 23 },
245 .m2 = { .min = 5, .max = 11 },
246 .p = { .min = 28, .max = 112 },
247 .p1 = { .min = 2, .max = 8 },
248 .p2 = { .dot_limit = 0,
249 .p2_slow = 14, .p2_fast = 14
250 },
251 };
252
253 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
254 .dot = { .min = 80000, .max = 224000 },
255 .vco = { .min = 1750000, .max = 3500000 },
256 .n = { .min = 1, .max = 3 },
257 .m = { .min = 104, .max = 138 },
258 .m1 = { .min = 17, .max = 23 },
259 .m2 = { .min = 5, .max = 11 },
260 .p = { .min = 14, .max = 42 },
261 .p1 = { .min = 2, .max = 6 },
262 .p2 = { .dot_limit = 0,
263 .p2_slow = 7, .p2_fast = 7
264 },
265 };
266
267 static const intel_limit_t intel_limits_pineview_sdvo = {
268 .dot = { .min = 20000, .max = 400000},
269 .vco = { .min = 1700000, .max = 3500000 },
270 /* Pineview's Ncounter is a ring counter */
271 .n = { .min = 3, .max = 6 },
272 .m = { .min = 2, .max = 256 },
273 /* Pineview only has one combined m divider, which we treat as m2. */
274 .m1 = { .min = 0, .max = 0 },
275 .m2 = { .min = 0, .max = 254 },
276 .p = { .min = 5, .max = 80 },
277 .p1 = { .min = 1, .max = 8 },
278 .p2 = { .dot_limit = 200000,
279 .p2_slow = 10, .p2_fast = 5 },
280 };
281
282 static const intel_limit_t intel_limits_pineview_lvds = {
283 .dot = { .min = 20000, .max = 400000 },
284 .vco = { .min = 1700000, .max = 3500000 },
285 .n = { .min = 3, .max = 6 },
286 .m = { .min = 2, .max = 256 },
287 .m1 = { .min = 0, .max = 0 },
288 .m2 = { .min = 0, .max = 254 },
289 .p = { .min = 7, .max = 112 },
290 .p1 = { .min = 1, .max = 8 },
291 .p2 = { .dot_limit = 112000,
292 .p2_slow = 14, .p2_fast = 14 },
293 };
294
295 /* Ironlake / Sandybridge
296 *
297 * We calculate clock using (register_value + 2) for N/M1/M2, so here
298 * the range value for them is (actual_value - 2).
299 */
300 static const intel_limit_t intel_limits_ironlake_dac = {
301 .dot = { .min = 25000, .max = 350000 },
302 .vco = { .min = 1760000, .max = 3510000 },
303 .n = { .min = 1, .max = 5 },
304 .m = { .min = 79, .max = 127 },
305 .m1 = { .min = 12, .max = 22 },
306 .m2 = { .min = 5, .max = 9 },
307 .p = { .min = 5, .max = 80 },
308 .p1 = { .min = 1, .max = 8 },
309 .p2 = { .dot_limit = 225000,
310 .p2_slow = 10, .p2_fast = 5 },
311 };
312
313 static const intel_limit_t intel_limits_ironlake_single_lvds = {
314 .dot = { .min = 25000, .max = 350000 },
315 .vco = { .min = 1760000, .max = 3510000 },
316 .n = { .min = 1, .max = 3 },
317 .m = { .min = 79, .max = 118 },
318 .m1 = { .min = 12, .max = 22 },
319 .m2 = { .min = 5, .max = 9 },
320 .p = { .min = 28, .max = 112 },
321 .p1 = { .min = 2, .max = 8 },
322 .p2 = { .dot_limit = 225000,
323 .p2_slow = 14, .p2_fast = 14 },
324 };
325
326 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
327 .dot = { .min = 25000, .max = 350000 },
328 .vco = { .min = 1760000, .max = 3510000 },
329 .n = { .min = 1, .max = 3 },
330 .m = { .min = 79, .max = 127 },
331 .m1 = { .min = 12, .max = 22 },
332 .m2 = { .min = 5, .max = 9 },
333 .p = { .min = 14, .max = 56 },
334 .p1 = { .min = 2, .max = 8 },
335 .p2 = { .dot_limit = 225000,
336 .p2_slow = 7, .p2_fast = 7 },
337 };
338
339 /* LVDS 100mhz refclk limits. */
340 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
341 .dot = { .min = 25000, .max = 350000 },
342 .vco = { .min = 1760000, .max = 3510000 },
343 .n = { .min = 1, .max = 2 },
344 .m = { .min = 79, .max = 126 },
345 .m1 = { .min = 12, .max = 22 },
346 .m2 = { .min = 5, .max = 9 },
347 .p = { .min = 28, .max = 112 },
348 .p1 = { .min = 2, .max = 8 },
349 .p2 = { .dot_limit = 225000,
350 .p2_slow = 14, .p2_fast = 14 },
351 };
352
353 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
354 .dot = { .min = 25000, .max = 350000 },
355 .vco = { .min = 1760000, .max = 3510000 },
356 .n = { .min = 1, .max = 3 },
357 .m = { .min = 79, .max = 126 },
358 .m1 = { .min = 12, .max = 22 },
359 .m2 = { .min = 5, .max = 9 },
360 .p = { .min = 14, .max = 42 },
361 .p1 = { .min = 2, .max = 6 },
362 .p2 = { .dot_limit = 225000,
363 .p2_slow = 7, .p2_fast = 7 },
364 };
365
366 static const intel_limit_t intel_limits_vlv = {
367 /*
368 * These are the data rate limits (measured in fast clocks)
369 * since those are the strictest limits we have. The fast
370 * clock and actual rate limits are more relaxed, so checking
371 * them would make no difference.
372 */
373 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
374 .vco = { .min = 4000000, .max = 6000000 },
375 .n = { .min = 1, .max = 7 },
376 .m1 = { .min = 2, .max = 3 },
377 .m2 = { .min = 11, .max = 156 },
378 .p1 = { .min = 2, .max = 3 },
379 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
380 };
381
382 static const intel_limit_t intel_limits_chv = {
383 /*
384 * These are the data rate limits (measured in fast clocks)
385 * since those are the strictest limits we have. The fast
386 * clock and actual rate limits are more relaxed, so checking
387 * them would make no difference.
388 */
389 .dot = { .min = 25000 * 5, .max = 540000 * 5},
390 .vco = { .min = 4860000, .max = 6700000 },
391 .n = { .min = 1, .max = 1 },
392 .m1 = { .min = 2, .max = 2 },
393 .m2 = { .min = 24 << 22, .max = 175 << 22 },
394 .p1 = { .min = 2, .max = 4 },
395 .p2 = { .p2_slow = 1, .p2_fast = 14 },
396 };
397
398 static void vlv_clock(int refclk, intel_clock_t *clock)
399 {
400 clock->m = clock->m1 * clock->m2;
401 clock->p = clock->p1 * clock->p2;
402 if (WARN_ON(clock->n == 0 || clock->p == 0))
403 return;
404 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
405 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
406 }
407
408 /**
409 * Returns whether any output on the specified pipe is of the specified type
410 */
411 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
412 {
413 struct drm_device *dev = crtc->dev;
414 struct intel_encoder *encoder;
415
416 for_each_encoder_on_crtc(dev, crtc, encoder)
417 if (encoder->type == type)
418 return true;
419
420 return false;
421 }
422
423 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
424 int refclk)
425 {
426 struct drm_device *dev = crtc->dev;
427 const intel_limit_t *limit;
428
429 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
430 if (intel_is_dual_link_lvds(dev)) {
431 if (refclk == 100000)
432 limit = &intel_limits_ironlake_dual_lvds_100m;
433 else
434 limit = &intel_limits_ironlake_dual_lvds;
435 } else {
436 if (refclk == 100000)
437 limit = &intel_limits_ironlake_single_lvds_100m;
438 else
439 limit = &intel_limits_ironlake_single_lvds;
440 }
441 } else
442 limit = &intel_limits_ironlake_dac;
443
444 return limit;
445 }
446
447 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
448 {
449 struct drm_device *dev = crtc->dev;
450 const intel_limit_t *limit;
451
452 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
453 if (intel_is_dual_link_lvds(dev))
454 limit = &intel_limits_g4x_dual_channel_lvds;
455 else
456 limit = &intel_limits_g4x_single_channel_lvds;
457 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
458 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
459 limit = &intel_limits_g4x_hdmi;
460 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
461 limit = &intel_limits_g4x_sdvo;
462 } else /* The option is for other outputs */
463 limit = &intel_limits_i9xx_sdvo;
464
465 return limit;
466 }
467
468 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
469 {
470 struct drm_device *dev = crtc->dev;
471 const intel_limit_t *limit;
472
473 if (HAS_PCH_SPLIT(dev))
474 limit = intel_ironlake_limit(crtc, refclk);
475 else if (IS_G4X(dev)) {
476 limit = intel_g4x_limit(crtc);
477 } else if (IS_PINEVIEW(dev)) {
478 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
479 limit = &intel_limits_pineview_lvds;
480 else
481 limit = &intel_limits_pineview_sdvo;
482 } else if (IS_CHERRYVIEW(dev)) {
483 limit = &intel_limits_chv;
484 } else if (IS_VALLEYVIEW(dev)) {
485 limit = &intel_limits_vlv;
486 } else if (!IS_GEN2(dev)) {
487 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
488 limit = &intel_limits_i9xx_lvds;
489 else
490 limit = &intel_limits_i9xx_sdvo;
491 } else {
492 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
493 limit = &intel_limits_i8xx_lvds;
494 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
495 limit = &intel_limits_i8xx_dvo;
496 else
497 limit = &intel_limits_i8xx_dac;
498 }
499 return limit;
500 }
501
502 /* m1 is reserved as 0 in Pineview, n is a ring counter */
503 static void pineview_clock(int refclk, intel_clock_t *clock)
504 {
505 clock->m = clock->m2 + 2;
506 clock->p = clock->p1 * clock->p2;
507 if (WARN_ON(clock->n == 0 || clock->p == 0))
508 return;
509 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
510 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
511 }
512
513 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
514 {
515 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
516 }
517
518 static void i9xx_clock(int refclk, intel_clock_t *clock)
519 {
520 clock->m = i9xx_dpll_compute_m(clock);
521 clock->p = clock->p1 * clock->p2;
522 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
523 return;
524 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
525 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
526 }
527
528 static void chv_clock(int refclk, intel_clock_t *clock)
529 {
530 clock->m = clock->m1 * clock->m2;
531 clock->p = clock->p1 * clock->p2;
532 if (WARN_ON(clock->n == 0 || clock->p == 0))
533 return;
534 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
535 clock->n << 22);
536 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
537 }
538
539 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
540 /**
541 * Returns whether the given set of divisors are valid for a given refclk with
542 * the given connectors.
543 */
544
545 static bool intel_PLL_is_valid(struct drm_device *dev,
546 const intel_limit_t *limit,
547 const intel_clock_t *clock)
548 {
549 if (clock->n < limit->n.min || limit->n.max < clock->n)
550 INTELPllInvalid("n out of range\n");
551 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
552 INTELPllInvalid("p1 out of range\n");
553 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
554 INTELPllInvalid("m2 out of range\n");
555 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
556 INTELPllInvalid("m1 out of range\n");
557
558 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
559 if (clock->m1 <= clock->m2)
560 INTELPllInvalid("m1 <= m2\n");
561
562 if (!IS_VALLEYVIEW(dev)) {
563 if (clock->p < limit->p.min || limit->p.max < clock->p)
564 INTELPllInvalid("p out of range\n");
565 if (clock->m < limit->m.min || limit->m.max < clock->m)
566 INTELPllInvalid("m out of range\n");
567 }
568
569 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
570 INTELPllInvalid("vco out of range\n");
571 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
572 * connector, etc., rather than just a single range.
573 */
574 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
575 INTELPllInvalid("dot out of range\n");
576
577 return true;
578 }
579
580 static bool
581 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
582 int target, int refclk, intel_clock_t *match_clock,
583 intel_clock_t *best_clock)
584 {
585 struct drm_device *dev = crtc->dev;
586 intel_clock_t clock;
587 int err = target;
588
589 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
590 /*
591 * For LVDS just rely on its current settings for dual-channel.
592 * We haven't figured out how to reliably set up different
593 * single/dual channel state, if we even can.
594 */
595 if (intel_is_dual_link_lvds(dev))
596 clock.p2 = limit->p2.p2_fast;
597 else
598 clock.p2 = limit->p2.p2_slow;
599 } else {
600 if (target < limit->p2.dot_limit)
601 clock.p2 = limit->p2.p2_slow;
602 else
603 clock.p2 = limit->p2.p2_fast;
604 }
605
606 memset(best_clock, 0, sizeof(*best_clock));
607
608 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
609 clock.m1++) {
610 for (clock.m2 = limit->m2.min;
611 clock.m2 <= limit->m2.max; clock.m2++) {
612 if (clock.m2 >= clock.m1)
613 break;
614 for (clock.n = limit->n.min;
615 clock.n <= limit->n.max; clock.n++) {
616 for (clock.p1 = limit->p1.min;
617 clock.p1 <= limit->p1.max; clock.p1++) {
618 int this_err;
619
620 i9xx_clock(refclk, &clock);
621 if (!intel_PLL_is_valid(dev, limit,
622 &clock))
623 continue;
624 if (match_clock &&
625 clock.p != match_clock->p)
626 continue;
627
628 this_err = abs(clock.dot - target);
629 if (this_err < err) {
630 *best_clock = clock;
631 err = this_err;
632 }
633 }
634 }
635 }
636 }
637
638 return (err != target);
639 }
640
641 static bool
642 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
643 int target, int refclk, intel_clock_t *match_clock,
644 intel_clock_t *best_clock)
645 {
646 struct drm_device *dev = crtc->dev;
647 intel_clock_t clock;
648 int err = target;
649
650 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
651 /*
652 * For LVDS just rely on its current settings for dual-channel.
653 * We haven't figured out how to reliably set up different
654 * single/dual channel state, if we even can.
655 */
656 if (intel_is_dual_link_lvds(dev))
657 clock.p2 = limit->p2.p2_fast;
658 else
659 clock.p2 = limit->p2.p2_slow;
660 } else {
661 if (target < limit->p2.dot_limit)
662 clock.p2 = limit->p2.p2_slow;
663 else
664 clock.p2 = limit->p2.p2_fast;
665 }
666
667 memset(best_clock, 0, sizeof(*best_clock));
668
669 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
670 clock.m1++) {
671 for (clock.m2 = limit->m2.min;
672 clock.m2 <= limit->m2.max; clock.m2++) {
673 for (clock.n = limit->n.min;
674 clock.n <= limit->n.max; clock.n++) {
675 for (clock.p1 = limit->p1.min;
676 clock.p1 <= limit->p1.max; clock.p1++) {
677 int this_err;
678
679 pineview_clock(refclk, &clock);
680 if (!intel_PLL_is_valid(dev, limit,
681 &clock))
682 continue;
683 if (match_clock &&
684 clock.p != match_clock->p)
685 continue;
686
687 this_err = abs(clock.dot - target);
688 if (this_err < err) {
689 *best_clock = clock;
690 err = this_err;
691 }
692 }
693 }
694 }
695 }
696
697 return (err != target);
698 }
699
700 static bool
701 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
702 int target, int refclk, intel_clock_t *match_clock,
703 intel_clock_t *best_clock)
704 {
705 struct drm_device *dev = crtc->dev;
706 intel_clock_t clock;
707 int max_n;
708 bool found;
709 /* approximately equals target * 0.00585 */
710 int err_most = (target >> 8) + (target >> 9);
711 found = false;
712
713 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
714 if (intel_is_dual_link_lvds(dev))
715 clock.p2 = limit->p2.p2_fast;
716 else
717 clock.p2 = limit->p2.p2_slow;
718 } else {
719 if (target < limit->p2.dot_limit)
720 clock.p2 = limit->p2.p2_slow;
721 else
722 clock.p2 = limit->p2.p2_fast;
723 }
724
725 memset(best_clock, 0, sizeof(*best_clock));
726 max_n = limit->n.max;
727 /* based on hardware requirement, prefer smaller n to precision */
728 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
729 /* based on hardware requirement, prefere larger m1,m2 */
730 for (clock.m1 = limit->m1.max;
731 clock.m1 >= limit->m1.min; clock.m1--) {
732 for (clock.m2 = limit->m2.max;
733 clock.m2 >= limit->m2.min; clock.m2--) {
734 for (clock.p1 = limit->p1.max;
735 clock.p1 >= limit->p1.min; clock.p1--) {
736 int this_err;
737
738 i9xx_clock(refclk, &clock);
739 if (!intel_PLL_is_valid(dev, limit,
740 &clock))
741 continue;
742
743 this_err = abs(clock.dot - target);
744 if (this_err < err_most) {
745 *best_clock = clock;
746 err_most = this_err;
747 max_n = clock.n;
748 found = true;
749 }
750 }
751 }
752 }
753 }
754 return found;
755 }
756
757 static bool
758 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
759 int target, int refclk, intel_clock_t *match_clock,
760 intel_clock_t *best_clock)
761 {
762 struct drm_device *dev = crtc->dev;
763 intel_clock_t clock;
764 unsigned int bestppm = 1000000;
765 /* min update 19.2 MHz */
766 int max_n = min(limit->n.max, refclk / 19200);
767 bool found = false;
768
769 target *= 5; /* fast clock */
770
771 memset(best_clock, 0, sizeof(*best_clock));
772
773 /* based on hardware requirement, prefer smaller n to precision */
774 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
775 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
776 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
777 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
778 clock.p = clock.p1 * clock.p2;
779 /* based on hardware requirement, prefer bigger m1,m2 values */
780 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
781 unsigned int ppm, diff;
782
783 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
784 refclk * clock.m1);
785
786 vlv_clock(refclk, &clock);
787
788 if (!intel_PLL_is_valid(dev, limit,
789 &clock))
790 continue;
791
792 diff = abs(clock.dot - target);
793 ppm = div_u64(1000000ULL * diff, target);
794
795 if (ppm < 100 && clock.p > best_clock->p) {
796 bestppm = 0;
797 *best_clock = clock;
798 found = true;
799 }
800
801 if (bestppm >= 10 && ppm < bestppm - 10) {
802 bestppm = ppm;
803 *best_clock = clock;
804 found = true;
805 }
806 }
807 }
808 }
809 }
810
811 return found;
812 }
813
814 static bool
815 chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
816 int target, int refclk, intel_clock_t *match_clock,
817 intel_clock_t *best_clock)
818 {
819 struct drm_device *dev = crtc->dev;
820 intel_clock_t clock;
821 uint64_t m2;
822 int found = false;
823
824 memset(best_clock, 0, sizeof(*best_clock));
825
826 /*
827 * Based on hardware doc, the n always set to 1, and m1 always
828 * set to 2. If requires to support 200Mhz refclk, we need to
829 * revisit this because n may not 1 anymore.
830 */
831 clock.n = 1, clock.m1 = 2;
832 target *= 5; /* fast clock */
833
834 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
835 for (clock.p2 = limit->p2.p2_fast;
836 clock.p2 >= limit->p2.p2_slow;
837 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
838
839 clock.p = clock.p1 * clock.p2;
840
841 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
842 clock.n) << 22, refclk * clock.m1);
843
844 if (m2 > INT_MAX/clock.m1)
845 continue;
846
847 clock.m2 = m2;
848
849 chv_clock(refclk, &clock);
850
851 if (!intel_PLL_is_valid(dev, limit, &clock))
852 continue;
853
854 /* based on hardware requirement, prefer bigger p
855 */
856 if (clock.p > best_clock->p) {
857 *best_clock = clock;
858 found = true;
859 }
860 }
861 }
862
863 return found;
864 }
865
866 bool intel_crtc_active(struct drm_crtc *crtc)
867 {
868 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
869
870 /* Be paranoid as we can arrive here with only partial
871 * state retrieved from the hardware during setup.
872 *
873 * We can ditch the adjusted_mode.crtc_clock check as soon
874 * as Haswell has gained clock readout/fastboot support.
875 *
876 * We can ditch the crtc->primary->fb check as soon as we can
877 * properly reconstruct framebuffers.
878 */
879 return intel_crtc->active && crtc->primary->fb &&
880 intel_crtc->config.adjusted_mode.crtc_clock;
881 }
882
883 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
884 enum pipe pipe)
885 {
886 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
887 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
888
889 return intel_crtc->config.cpu_transcoder;
890 }
891
892 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
893 {
894 struct drm_i915_private *dev_priv = dev->dev_private;
895 u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
896
897 frame = I915_READ(frame_reg);
898
899 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
900 WARN(1, "vblank wait on pipe %c timed out\n",
901 pipe_name(pipe));
902 }
903
904 /**
905 * intel_wait_for_vblank - wait for vblank on a given pipe
906 * @dev: drm device
907 * @pipe: pipe to wait for
908 *
909 * Wait for vblank to occur on a given pipe. Needed for various bits of
910 * mode setting code.
911 */
912 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
913 {
914 struct drm_i915_private *dev_priv = dev->dev_private;
915 int pipestat_reg = PIPESTAT(pipe);
916
917 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
918 g4x_wait_for_vblank(dev, pipe);
919 return;
920 }
921
922 /* Clear existing vblank status. Note this will clear any other
923 * sticky status fields as well.
924 *
925 * This races with i915_driver_irq_handler() with the result
926 * that either function could miss a vblank event. Here it is not
927 * fatal, as we will either wait upon the next vblank interrupt or
928 * timeout. Generally speaking intel_wait_for_vblank() is only
929 * called during modeset at which time the GPU should be idle and
930 * should *not* be performing page flips and thus not waiting on
931 * vblanks...
932 * Currently, the result of us stealing a vblank from the irq
933 * handler is that a single frame will be skipped during swapbuffers.
934 */
935 I915_WRITE(pipestat_reg,
936 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
937
938 /* Wait for vblank interrupt bit to set */
939 if (wait_for(I915_READ(pipestat_reg) &
940 PIPE_VBLANK_INTERRUPT_STATUS,
941 50))
942 DRM_DEBUG_KMS("vblank wait on pipe %c timed out\n",
943 pipe_name(pipe));
944 }
945
946 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
947 {
948 struct drm_i915_private *dev_priv = dev->dev_private;
949 u32 reg = PIPEDSL(pipe);
950 u32 line1, line2;
951 u32 line_mask;
952
953 if (IS_GEN2(dev))
954 line_mask = DSL_LINEMASK_GEN2;
955 else
956 line_mask = DSL_LINEMASK_GEN3;
957
958 line1 = I915_READ(reg) & line_mask;
959 mdelay(5);
960 line2 = I915_READ(reg) & line_mask;
961
962 return line1 == line2;
963 }
964
965 /*
966 * intel_wait_for_pipe_off - wait for pipe to turn off
967 * @crtc: crtc whose pipe to wait for
968 *
969 * After disabling a pipe, we can't wait for vblank in the usual way,
970 * spinning on the vblank interrupt status bit, since we won't actually
971 * see an interrupt when the pipe is disabled.
972 *
973 * On Gen4 and above:
974 * wait for the pipe register state bit to turn off
975 *
976 * Otherwise:
977 * wait for the display line value to settle (it usually
978 * ends up stopping at the start of the next frame).
979 *
980 */
981 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
982 {
983 struct drm_device *dev = crtc->base.dev;
984 struct drm_i915_private *dev_priv = dev->dev_private;
985 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
986 enum pipe pipe = crtc->pipe;
987
988 if (INTEL_INFO(dev)->gen >= 4) {
989 int reg = PIPECONF(cpu_transcoder);
990
991 /* Wait for the Pipe State to go off */
992 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
993 100))
994 WARN(1, "pipe_off wait timed out\n");
995 } else {
996 /* Wait for the display line to settle */
997 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
998 WARN(1, "pipe_off wait timed out\n");
999 }
1000 }
1001
1002 /*
1003 * ibx_digital_port_connected - is the specified port connected?
1004 * @dev_priv: i915 private structure
1005 * @port: the port to test
1006 *
1007 * Returns true if @port is connected, false otherwise.
1008 */
1009 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1010 struct intel_digital_port *port)
1011 {
1012 u32 bit;
1013
1014 if (HAS_PCH_IBX(dev_priv->dev)) {
1015 switch (port->port) {
1016 case PORT_B:
1017 bit = SDE_PORTB_HOTPLUG;
1018 break;
1019 case PORT_C:
1020 bit = SDE_PORTC_HOTPLUG;
1021 break;
1022 case PORT_D:
1023 bit = SDE_PORTD_HOTPLUG;
1024 break;
1025 default:
1026 return true;
1027 }
1028 } else {
1029 switch (port->port) {
1030 case PORT_B:
1031 bit = SDE_PORTB_HOTPLUG_CPT;
1032 break;
1033 case PORT_C:
1034 bit = SDE_PORTC_HOTPLUG_CPT;
1035 break;
1036 case PORT_D:
1037 bit = SDE_PORTD_HOTPLUG_CPT;
1038 break;
1039 default:
1040 return true;
1041 }
1042 }
1043
1044 return I915_READ(SDEISR) & bit;
1045 }
1046
1047 static const char *state_string(bool enabled)
1048 {
1049 return enabled ? "on" : "off";
1050 }
1051
1052 /* Only for pre-ILK configs */
1053 void assert_pll(struct drm_i915_private *dev_priv,
1054 enum pipe pipe, bool state)
1055 {
1056 int reg;
1057 u32 val;
1058 bool cur_state;
1059
1060 reg = DPLL(pipe);
1061 val = I915_READ(reg);
1062 cur_state = !!(val & DPLL_VCO_ENABLE);
1063 WARN(cur_state != state,
1064 "PLL state assertion failure (expected %s, current %s)\n",
1065 state_string(state), state_string(cur_state));
1066 }
1067
1068 /* XXX: the dsi pll is shared between MIPI DSI ports */
1069 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1070 {
1071 u32 val;
1072 bool cur_state;
1073
1074 mutex_lock(&dev_priv->dpio_lock);
1075 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1076 mutex_unlock(&dev_priv->dpio_lock);
1077
1078 cur_state = val & DSI_PLL_VCO_EN;
1079 WARN(cur_state != state,
1080 "DSI PLL state assertion failure (expected %s, current %s)\n",
1081 state_string(state), state_string(cur_state));
1082 }
1083 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1084 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1085
1086 struct intel_shared_dpll *
1087 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1088 {
1089 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1090
1091 if (crtc->config.shared_dpll < 0)
1092 return NULL;
1093
1094 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1095 }
1096
1097 /* For ILK+ */
1098 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1099 struct intel_shared_dpll *pll,
1100 bool state)
1101 {
1102 bool cur_state;
1103 struct intel_dpll_hw_state hw_state;
1104
1105 if (WARN (!pll,
1106 "asserting DPLL %s with no DPLL\n", state_string(state)))
1107 return;
1108
1109 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1110 WARN(cur_state != state,
1111 "%s assertion failure (expected %s, current %s)\n",
1112 pll->name, state_string(state), state_string(cur_state));
1113 }
1114
1115 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1116 enum pipe pipe, bool state)
1117 {
1118 int reg;
1119 u32 val;
1120 bool cur_state;
1121 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1122 pipe);
1123
1124 if (HAS_DDI(dev_priv->dev)) {
1125 /* DDI does not have a specific FDI_TX register */
1126 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1127 val = I915_READ(reg);
1128 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1129 } else {
1130 reg = FDI_TX_CTL(pipe);
1131 val = I915_READ(reg);
1132 cur_state = !!(val & FDI_TX_ENABLE);
1133 }
1134 WARN(cur_state != state,
1135 "FDI TX state assertion failure (expected %s, current %s)\n",
1136 state_string(state), state_string(cur_state));
1137 }
1138 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1139 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1140
1141 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1142 enum pipe pipe, bool state)
1143 {
1144 int reg;
1145 u32 val;
1146 bool cur_state;
1147
1148 reg = FDI_RX_CTL(pipe);
1149 val = I915_READ(reg);
1150 cur_state = !!(val & FDI_RX_ENABLE);
1151 WARN(cur_state != state,
1152 "FDI RX state assertion failure (expected %s, current %s)\n",
1153 state_string(state), state_string(cur_state));
1154 }
1155 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1156 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1157
1158 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1159 enum pipe pipe)
1160 {
1161 int reg;
1162 u32 val;
1163
1164 /* ILK FDI PLL is always enabled */
1165 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1166 return;
1167
1168 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1169 if (HAS_DDI(dev_priv->dev))
1170 return;
1171
1172 reg = FDI_TX_CTL(pipe);
1173 val = I915_READ(reg);
1174 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1175 }
1176
1177 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1178 enum pipe pipe, bool state)
1179 {
1180 int reg;
1181 u32 val;
1182 bool cur_state;
1183
1184 reg = FDI_RX_CTL(pipe);
1185 val = I915_READ(reg);
1186 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1187 WARN(cur_state != state,
1188 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1189 state_string(state), state_string(cur_state));
1190 }
1191
1192 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1193 enum pipe pipe)
1194 {
1195 struct drm_device *dev = dev_priv->dev;
1196 int pp_reg;
1197 u32 val;
1198 enum pipe panel_pipe = PIPE_A;
1199 bool locked = true;
1200
1201 if (WARN_ON(HAS_DDI(dev)))
1202 return;
1203
1204 if (HAS_PCH_SPLIT(dev)) {
1205 u32 port_sel;
1206
1207 pp_reg = PCH_PP_CONTROL;
1208 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1209
1210 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1211 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1212 panel_pipe = PIPE_B;
1213 /* XXX: else fix for eDP */
1214 } else if (IS_VALLEYVIEW(dev)) {
1215 /* presumably write lock depends on pipe, not port select */
1216 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1217 panel_pipe = pipe;
1218 } else {
1219 pp_reg = PP_CONTROL;
1220 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1221 panel_pipe = PIPE_B;
1222 }
1223
1224 val = I915_READ(pp_reg);
1225 if (!(val & PANEL_POWER_ON) ||
1226 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1227 locked = false;
1228
1229 WARN(panel_pipe == pipe && locked,
1230 "panel assertion failure, pipe %c regs locked\n",
1231 pipe_name(pipe));
1232 }
1233
1234 static void assert_cursor(struct drm_i915_private *dev_priv,
1235 enum pipe pipe, bool state)
1236 {
1237 struct drm_device *dev = dev_priv->dev;
1238 bool cur_state;
1239
1240 if (IS_845G(dev) || IS_I865G(dev))
1241 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1242 else
1243 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1244
1245 WARN(cur_state != state,
1246 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1247 pipe_name(pipe), state_string(state), state_string(cur_state));
1248 }
1249 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1250 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1251
1252 void assert_pipe(struct drm_i915_private *dev_priv,
1253 enum pipe pipe, bool state)
1254 {
1255 int reg;
1256 u32 val;
1257 bool cur_state;
1258 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1259 pipe);
1260
1261 /* if we need the pipe quirk it must be always on */
1262 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1263 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1264 state = true;
1265
1266 if (!intel_display_power_enabled(dev_priv,
1267 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1268 cur_state = false;
1269 } else {
1270 reg = PIPECONF(cpu_transcoder);
1271 val = I915_READ(reg);
1272 cur_state = !!(val & PIPECONF_ENABLE);
1273 }
1274
1275 WARN(cur_state != state,
1276 "pipe %c assertion failure (expected %s, current %s)\n",
1277 pipe_name(pipe), state_string(state), state_string(cur_state));
1278 }
1279
1280 static void assert_plane(struct drm_i915_private *dev_priv,
1281 enum plane plane, bool state)
1282 {
1283 int reg;
1284 u32 val;
1285 bool cur_state;
1286
1287 reg = DSPCNTR(plane);
1288 val = I915_READ(reg);
1289 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1290 WARN(cur_state != state,
1291 "plane %c assertion failure (expected %s, current %s)\n",
1292 plane_name(plane), state_string(state), state_string(cur_state));
1293 }
1294
1295 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1296 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1297
1298 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1299 enum pipe pipe)
1300 {
1301 struct drm_device *dev = dev_priv->dev;
1302 int reg, i;
1303 u32 val;
1304 int cur_pipe;
1305
1306 /* Primary planes are fixed to pipes on gen4+ */
1307 if (INTEL_INFO(dev)->gen >= 4) {
1308 reg = DSPCNTR(pipe);
1309 val = I915_READ(reg);
1310 WARN(val & DISPLAY_PLANE_ENABLE,
1311 "plane %c assertion failure, should be disabled but not\n",
1312 plane_name(pipe));
1313 return;
1314 }
1315
1316 /* Need to check both planes against the pipe */
1317 for_each_pipe(dev_priv, i) {
1318 reg = DSPCNTR(i);
1319 val = I915_READ(reg);
1320 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1321 DISPPLANE_SEL_PIPE_SHIFT;
1322 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1323 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1324 plane_name(i), pipe_name(pipe));
1325 }
1326 }
1327
1328 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1329 enum pipe pipe)
1330 {
1331 struct drm_device *dev = dev_priv->dev;
1332 int reg, sprite;
1333 u32 val;
1334
1335 if (IS_VALLEYVIEW(dev)) {
1336 for_each_sprite(pipe, sprite) {
1337 reg = SPCNTR(pipe, sprite);
1338 val = I915_READ(reg);
1339 WARN(val & SP_ENABLE,
1340 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1341 sprite_name(pipe, sprite), pipe_name(pipe));
1342 }
1343 } else if (INTEL_INFO(dev)->gen >= 7) {
1344 reg = SPRCTL(pipe);
1345 val = I915_READ(reg);
1346 WARN(val & SPRITE_ENABLE,
1347 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1348 plane_name(pipe), pipe_name(pipe));
1349 } else if (INTEL_INFO(dev)->gen >= 5) {
1350 reg = DVSCNTR(pipe);
1351 val = I915_READ(reg);
1352 WARN(val & DVS_ENABLE,
1353 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1354 plane_name(pipe), pipe_name(pipe));
1355 }
1356 }
1357
1358 static void assert_vblank_disabled(struct drm_crtc *crtc)
1359 {
1360 if (WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1361 drm_crtc_vblank_put(crtc);
1362 }
1363
1364 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1365 {
1366 u32 val;
1367 bool enabled;
1368
1369 WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1370
1371 val = I915_READ(PCH_DREF_CONTROL);
1372 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1373 DREF_SUPERSPREAD_SOURCE_MASK));
1374 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1375 }
1376
1377 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1378 enum pipe pipe)
1379 {
1380 int reg;
1381 u32 val;
1382 bool enabled;
1383
1384 reg = PCH_TRANSCONF(pipe);
1385 val = I915_READ(reg);
1386 enabled = !!(val & TRANS_ENABLE);
1387 WARN(enabled,
1388 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1389 pipe_name(pipe));
1390 }
1391
1392 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1393 enum pipe pipe, u32 port_sel, u32 val)
1394 {
1395 if ((val & DP_PORT_EN) == 0)
1396 return false;
1397
1398 if (HAS_PCH_CPT(dev_priv->dev)) {
1399 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1400 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1401 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1402 return false;
1403 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1404 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1405 return false;
1406 } else {
1407 if ((val & DP_PIPE_MASK) != (pipe << 30))
1408 return false;
1409 }
1410 return true;
1411 }
1412
1413 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1414 enum pipe pipe, u32 val)
1415 {
1416 if ((val & SDVO_ENABLE) == 0)
1417 return false;
1418
1419 if (HAS_PCH_CPT(dev_priv->dev)) {
1420 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1421 return false;
1422 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1423 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1424 return false;
1425 } else {
1426 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1427 return false;
1428 }
1429 return true;
1430 }
1431
1432 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1433 enum pipe pipe, u32 val)
1434 {
1435 if ((val & LVDS_PORT_EN) == 0)
1436 return false;
1437
1438 if (HAS_PCH_CPT(dev_priv->dev)) {
1439 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1440 return false;
1441 } else {
1442 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1443 return false;
1444 }
1445 return true;
1446 }
1447
1448 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1449 enum pipe pipe, u32 val)
1450 {
1451 if ((val & ADPA_DAC_ENABLE) == 0)
1452 return false;
1453 if (HAS_PCH_CPT(dev_priv->dev)) {
1454 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1455 return false;
1456 } else {
1457 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1458 return false;
1459 }
1460 return true;
1461 }
1462
1463 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1464 enum pipe pipe, int reg, u32 port_sel)
1465 {
1466 u32 val = I915_READ(reg);
1467 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1468 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1469 reg, pipe_name(pipe));
1470
1471 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1472 && (val & DP_PIPEB_SELECT),
1473 "IBX PCH dp port still using transcoder B\n");
1474 }
1475
1476 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1477 enum pipe pipe, int reg)
1478 {
1479 u32 val = I915_READ(reg);
1480 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1481 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1482 reg, pipe_name(pipe));
1483
1484 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1485 && (val & SDVO_PIPE_B_SELECT),
1486 "IBX PCH hdmi port still using transcoder B\n");
1487 }
1488
1489 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1490 enum pipe pipe)
1491 {
1492 int reg;
1493 u32 val;
1494
1495 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1496 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1497 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1498
1499 reg = PCH_ADPA;
1500 val = I915_READ(reg);
1501 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1502 "PCH VGA enabled on transcoder %c, should be disabled\n",
1503 pipe_name(pipe));
1504
1505 reg = PCH_LVDS;
1506 val = I915_READ(reg);
1507 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1508 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1509 pipe_name(pipe));
1510
1511 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1512 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1513 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1514 }
1515
1516 static void intel_init_dpio(struct drm_device *dev)
1517 {
1518 struct drm_i915_private *dev_priv = dev->dev_private;
1519
1520 if (!IS_VALLEYVIEW(dev))
1521 return;
1522
1523 /*
1524 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1525 * CHV x1 PHY (DP/HDMI D)
1526 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1527 */
1528 if (IS_CHERRYVIEW(dev)) {
1529 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1530 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1531 } else {
1532 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1533 }
1534 }
1535
1536 static void vlv_enable_pll(struct intel_crtc *crtc)
1537 {
1538 struct drm_device *dev = crtc->base.dev;
1539 struct drm_i915_private *dev_priv = dev->dev_private;
1540 int reg = DPLL(crtc->pipe);
1541 u32 dpll = crtc->config.dpll_hw_state.dpll;
1542
1543 assert_pipe_disabled(dev_priv, crtc->pipe);
1544
1545 /* No really, not for ILK+ */
1546 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1547
1548 /* PLL is protected by panel, make sure we can write it */
1549 if (IS_MOBILE(dev_priv->dev))
1550 assert_panel_unlocked(dev_priv, crtc->pipe);
1551
1552 I915_WRITE(reg, dpll);
1553 POSTING_READ(reg);
1554 udelay(150);
1555
1556 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1557 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1558
1559 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1560 POSTING_READ(DPLL_MD(crtc->pipe));
1561
1562 /* We do this three times for luck */
1563 I915_WRITE(reg, dpll);
1564 POSTING_READ(reg);
1565 udelay(150); /* wait for warmup */
1566 I915_WRITE(reg, dpll);
1567 POSTING_READ(reg);
1568 udelay(150); /* wait for warmup */
1569 I915_WRITE(reg, dpll);
1570 POSTING_READ(reg);
1571 udelay(150); /* wait for warmup */
1572 }
1573
1574 static void chv_enable_pll(struct intel_crtc *crtc)
1575 {
1576 struct drm_device *dev = crtc->base.dev;
1577 struct drm_i915_private *dev_priv = dev->dev_private;
1578 int pipe = crtc->pipe;
1579 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1580 u32 tmp;
1581
1582 assert_pipe_disabled(dev_priv, crtc->pipe);
1583
1584 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1585
1586 mutex_lock(&dev_priv->dpio_lock);
1587
1588 /* Enable back the 10bit clock to display controller */
1589 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1590 tmp |= DPIO_DCLKP_EN;
1591 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1592
1593 /*
1594 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1595 */
1596 udelay(1);
1597
1598 /* Enable PLL */
1599 I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll);
1600
1601 /* Check PLL is locked */
1602 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1603 DRM_ERROR("PLL %d failed to lock\n", pipe);
1604
1605 /* not sure when this should be written */
1606 I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
1607 POSTING_READ(DPLL_MD(pipe));
1608
1609 mutex_unlock(&dev_priv->dpio_lock);
1610 }
1611
1612 static int intel_num_dvo_pipes(struct drm_device *dev)
1613 {
1614 struct intel_crtc *crtc;
1615 int count = 0;
1616
1617 for_each_intel_crtc(dev, crtc)
1618 count += crtc->active &&
1619 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO);
1620
1621 return count;
1622 }
1623
1624 static void i9xx_enable_pll(struct intel_crtc *crtc)
1625 {
1626 struct drm_device *dev = crtc->base.dev;
1627 struct drm_i915_private *dev_priv = dev->dev_private;
1628 int reg = DPLL(crtc->pipe);
1629 u32 dpll = crtc->config.dpll_hw_state.dpll;
1630
1631 assert_pipe_disabled(dev_priv, crtc->pipe);
1632
1633 /* No really, not for ILK+ */
1634 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1635
1636 /* PLL is protected by panel, make sure we can write it */
1637 if (IS_MOBILE(dev) && !IS_I830(dev))
1638 assert_panel_unlocked(dev_priv, crtc->pipe);
1639
1640 /* Enable DVO 2x clock on both PLLs if necessary */
1641 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1642 /*
1643 * It appears to be important that we don't enable this
1644 * for the current pipe before otherwise configuring the
1645 * PLL. No idea how this should be handled if multiple
1646 * DVO outputs are enabled simultaneosly.
1647 */
1648 dpll |= DPLL_DVO_2X_MODE;
1649 I915_WRITE(DPLL(!crtc->pipe),
1650 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1651 }
1652
1653 /* Wait for the clocks to stabilize. */
1654 POSTING_READ(reg);
1655 udelay(150);
1656
1657 if (INTEL_INFO(dev)->gen >= 4) {
1658 I915_WRITE(DPLL_MD(crtc->pipe),
1659 crtc->config.dpll_hw_state.dpll_md);
1660 } else {
1661 /* The pixel multiplier can only be updated once the
1662 * DPLL is enabled and the clocks are stable.
1663 *
1664 * So write it again.
1665 */
1666 I915_WRITE(reg, dpll);
1667 }
1668
1669 /* We do this three times for luck */
1670 I915_WRITE(reg, dpll);
1671 POSTING_READ(reg);
1672 udelay(150); /* wait for warmup */
1673 I915_WRITE(reg, dpll);
1674 POSTING_READ(reg);
1675 udelay(150); /* wait for warmup */
1676 I915_WRITE(reg, dpll);
1677 POSTING_READ(reg);
1678 udelay(150); /* wait for warmup */
1679 }
1680
1681 /**
1682 * i9xx_disable_pll - disable a PLL
1683 * @dev_priv: i915 private structure
1684 * @pipe: pipe PLL to disable
1685 *
1686 * Disable the PLL for @pipe, making sure the pipe is off first.
1687 *
1688 * Note! This is for pre-ILK only.
1689 */
1690 static void i9xx_disable_pll(struct intel_crtc *crtc)
1691 {
1692 struct drm_device *dev = crtc->base.dev;
1693 struct drm_i915_private *dev_priv = dev->dev_private;
1694 enum pipe pipe = crtc->pipe;
1695
1696 /* Disable DVO 2x clock on both PLLs if necessary */
1697 if (IS_I830(dev) &&
1698 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO) &&
1699 intel_num_dvo_pipes(dev) == 1) {
1700 I915_WRITE(DPLL(PIPE_B),
1701 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1702 I915_WRITE(DPLL(PIPE_A),
1703 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1704 }
1705
1706 /* Don't disable pipe or pipe PLLs if needed */
1707 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1708 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1709 return;
1710
1711 /* Make sure the pipe isn't still relying on us */
1712 assert_pipe_disabled(dev_priv, pipe);
1713
1714 I915_WRITE(DPLL(pipe), 0);
1715 POSTING_READ(DPLL(pipe));
1716 }
1717
1718 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1719 {
1720 u32 val = 0;
1721
1722 /* Make sure the pipe isn't still relying on us */
1723 assert_pipe_disabled(dev_priv, pipe);
1724
1725 /*
1726 * Leave integrated clock source and reference clock enabled for pipe B.
1727 * The latter is needed for VGA hotplug / manual detection.
1728 */
1729 if (pipe == PIPE_B)
1730 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1731 I915_WRITE(DPLL(pipe), val);
1732 POSTING_READ(DPLL(pipe));
1733
1734 }
1735
1736 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1737 {
1738 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1739 u32 val;
1740
1741 /* Make sure the pipe isn't still relying on us */
1742 assert_pipe_disabled(dev_priv, pipe);
1743
1744 /* Set PLL en = 0 */
1745 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1746 if (pipe != PIPE_A)
1747 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1748 I915_WRITE(DPLL(pipe), val);
1749 POSTING_READ(DPLL(pipe));
1750
1751 mutex_lock(&dev_priv->dpio_lock);
1752
1753 /* Disable 10bit clock to display controller */
1754 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1755 val &= ~DPIO_DCLKP_EN;
1756 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1757
1758 /* disable left/right clock distribution */
1759 if (pipe != PIPE_B) {
1760 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1761 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1762 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1763 } else {
1764 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1765 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1766 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1767 }
1768
1769 mutex_unlock(&dev_priv->dpio_lock);
1770 }
1771
1772 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1773 struct intel_digital_port *dport)
1774 {
1775 u32 port_mask;
1776 int dpll_reg;
1777
1778 switch (dport->port) {
1779 case PORT_B:
1780 port_mask = DPLL_PORTB_READY_MASK;
1781 dpll_reg = DPLL(0);
1782 break;
1783 case PORT_C:
1784 port_mask = DPLL_PORTC_READY_MASK;
1785 dpll_reg = DPLL(0);
1786 break;
1787 case PORT_D:
1788 port_mask = DPLL_PORTD_READY_MASK;
1789 dpll_reg = DPIO_PHY_STATUS;
1790 break;
1791 default:
1792 BUG();
1793 }
1794
1795 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1796 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1797 port_name(dport->port), I915_READ(dpll_reg));
1798 }
1799
1800 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1801 {
1802 struct drm_device *dev = crtc->base.dev;
1803 struct drm_i915_private *dev_priv = dev->dev_private;
1804 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1805
1806 if (WARN_ON(pll == NULL))
1807 return;
1808
1809 WARN_ON(!pll->refcount);
1810 if (pll->active == 0) {
1811 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1812 WARN_ON(pll->on);
1813 assert_shared_dpll_disabled(dev_priv, pll);
1814
1815 pll->mode_set(dev_priv, pll);
1816 }
1817 }
1818
1819 /**
1820 * intel_enable_shared_dpll - enable PCH PLL
1821 * @dev_priv: i915 private structure
1822 * @pipe: pipe PLL to enable
1823 *
1824 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1825 * drives the transcoder clock.
1826 */
1827 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1828 {
1829 struct drm_device *dev = crtc->base.dev;
1830 struct drm_i915_private *dev_priv = dev->dev_private;
1831 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1832
1833 if (WARN_ON(pll == NULL))
1834 return;
1835
1836 if (WARN_ON(pll->refcount == 0))
1837 return;
1838
1839 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1840 pll->name, pll->active, pll->on,
1841 crtc->base.base.id);
1842
1843 if (pll->active++) {
1844 WARN_ON(!pll->on);
1845 assert_shared_dpll_enabled(dev_priv, pll);
1846 return;
1847 }
1848 WARN_ON(pll->on);
1849
1850 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1851
1852 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1853 pll->enable(dev_priv, pll);
1854 pll->on = true;
1855 }
1856
1857 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1858 {
1859 struct drm_device *dev = crtc->base.dev;
1860 struct drm_i915_private *dev_priv = dev->dev_private;
1861 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1862
1863 /* PCH only available on ILK+ */
1864 BUG_ON(INTEL_INFO(dev)->gen < 5);
1865 if (WARN_ON(pll == NULL))
1866 return;
1867
1868 if (WARN_ON(pll->refcount == 0))
1869 return;
1870
1871 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1872 pll->name, pll->active, pll->on,
1873 crtc->base.base.id);
1874
1875 if (WARN_ON(pll->active == 0)) {
1876 assert_shared_dpll_disabled(dev_priv, pll);
1877 return;
1878 }
1879
1880 assert_shared_dpll_enabled(dev_priv, pll);
1881 WARN_ON(!pll->on);
1882 if (--pll->active)
1883 return;
1884
1885 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1886 pll->disable(dev_priv, pll);
1887 pll->on = false;
1888
1889 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1890 }
1891
1892 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1893 enum pipe pipe)
1894 {
1895 struct drm_device *dev = dev_priv->dev;
1896 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1897 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1898 uint32_t reg, val, pipeconf_val;
1899
1900 /* PCH only available on ILK+ */
1901 BUG_ON(!HAS_PCH_SPLIT(dev));
1902
1903 /* Make sure PCH DPLL is enabled */
1904 assert_shared_dpll_enabled(dev_priv,
1905 intel_crtc_to_shared_dpll(intel_crtc));
1906
1907 /* FDI must be feeding us bits for PCH ports */
1908 assert_fdi_tx_enabled(dev_priv, pipe);
1909 assert_fdi_rx_enabled(dev_priv, pipe);
1910
1911 if (HAS_PCH_CPT(dev)) {
1912 /* Workaround: Set the timing override bit before enabling the
1913 * pch transcoder. */
1914 reg = TRANS_CHICKEN2(pipe);
1915 val = I915_READ(reg);
1916 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1917 I915_WRITE(reg, val);
1918 }
1919
1920 reg = PCH_TRANSCONF(pipe);
1921 val = I915_READ(reg);
1922 pipeconf_val = I915_READ(PIPECONF(pipe));
1923
1924 if (HAS_PCH_IBX(dev_priv->dev)) {
1925 /*
1926 * make the BPC in transcoder be consistent with
1927 * that in pipeconf reg.
1928 */
1929 val &= ~PIPECONF_BPC_MASK;
1930 val |= pipeconf_val & PIPECONF_BPC_MASK;
1931 }
1932
1933 val &= ~TRANS_INTERLACE_MASK;
1934 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1935 if (HAS_PCH_IBX(dev_priv->dev) &&
1936 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1937 val |= TRANS_LEGACY_INTERLACED_ILK;
1938 else
1939 val |= TRANS_INTERLACED;
1940 else
1941 val |= TRANS_PROGRESSIVE;
1942
1943 I915_WRITE(reg, val | TRANS_ENABLE);
1944 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1945 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1946 }
1947
1948 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1949 enum transcoder cpu_transcoder)
1950 {
1951 u32 val, pipeconf_val;
1952
1953 /* PCH only available on ILK+ */
1954 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1955
1956 /* FDI must be feeding us bits for PCH ports */
1957 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1958 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1959
1960 /* Workaround: set timing override bit. */
1961 val = I915_READ(_TRANSA_CHICKEN2);
1962 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1963 I915_WRITE(_TRANSA_CHICKEN2, val);
1964
1965 val = TRANS_ENABLE;
1966 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1967
1968 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1969 PIPECONF_INTERLACED_ILK)
1970 val |= TRANS_INTERLACED;
1971 else
1972 val |= TRANS_PROGRESSIVE;
1973
1974 I915_WRITE(LPT_TRANSCONF, val);
1975 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1976 DRM_ERROR("Failed to enable PCH transcoder\n");
1977 }
1978
1979 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1980 enum pipe pipe)
1981 {
1982 struct drm_device *dev = dev_priv->dev;
1983 uint32_t reg, val;
1984
1985 /* FDI relies on the transcoder */
1986 assert_fdi_tx_disabled(dev_priv, pipe);
1987 assert_fdi_rx_disabled(dev_priv, pipe);
1988
1989 /* Ports must be off as well */
1990 assert_pch_ports_disabled(dev_priv, pipe);
1991
1992 reg = PCH_TRANSCONF(pipe);
1993 val = I915_READ(reg);
1994 val &= ~TRANS_ENABLE;
1995 I915_WRITE(reg, val);
1996 /* wait for PCH transcoder off, transcoder state */
1997 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1998 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1999
2000 if (!HAS_PCH_IBX(dev)) {
2001 /* Workaround: Clear the timing override chicken bit again. */
2002 reg = TRANS_CHICKEN2(pipe);
2003 val = I915_READ(reg);
2004 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2005 I915_WRITE(reg, val);
2006 }
2007 }
2008
2009 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2010 {
2011 u32 val;
2012
2013 val = I915_READ(LPT_TRANSCONF);
2014 val &= ~TRANS_ENABLE;
2015 I915_WRITE(LPT_TRANSCONF, val);
2016 /* wait for PCH transcoder off, transcoder state */
2017 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2018 DRM_ERROR("Failed to disable PCH transcoder\n");
2019
2020 /* Workaround: clear timing override bit. */
2021 val = I915_READ(_TRANSA_CHICKEN2);
2022 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2023 I915_WRITE(_TRANSA_CHICKEN2, val);
2024 }
2025
2026 /**
2027 * intel_enable_pipe - enable a pipe, asserting requirements
2028 * @crtc: crtc responsible for the pipe
2029 *
2030 * Enable @crtc's pipe, making sure that various hardware specific requirements
2031 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2032 */
2033 static void intel_enable_pipe(struct intel_crtc *crtc)
2034 {
2035 struct drm_device *dev = crtc->base.dev;
2036 struct drm_i915_private *dev_priv = dev->dev_private;
2037 enum pipe pipe = crtc->pipe;
2038 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2039 pipe);
2040 enum pipe pch_transcoder;
2041 int reg;
2042 u32 val;
2043
2044 assert_planes_disabled(dev_priv, pipe);
2045 assert_cursor_disabled(dev_priv, pipe);
2046 assert_sprites_disabled(dev_priv, pipe);
2047
2048 if (HAS_PCH_LPT(dev_priv->dev))
2049 pch_transcoder = TRANSCODER_A;
2050 else
2051 pch_transcoder = pipe;
2052
2053 /*
2054 * A pipe without a PLL won't actually be able to drive bits from
2055 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2056 * need the check.
2057 */
2058 if (!HAS_PCH_SPLIT(dev_priv->dev))
2059 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
2060 assert_dsi_pll_enabled(dev_priv);
2061 else
2062 assert_pll_enabled(dev_priv, pipe);
2063 else {
2064 if (crtc->config.has_pch_encoder) {
2065 /* if driving the PCH, we need FDI enabled */
2066 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2067 assert_fdi_tx_pll_enabled(dev_priv,
2068 (enum pipe) cpu_transcoder);
2069 }
2070 /* FIXME: assert CPU port conditions for SNB+ */
2071 }
2072
2073 reg = PIPECONF(cpu_transcoder);
2074 val = I915_READ(reg);
2075 if (val & PIPECONF_ENABLE) {
2076 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2077 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2078 return;
2079 }
2080
2081 I915_WRITE(reg, val | PIPECONF_ENABLE);
2082 POSTING_READ(reg);
2083 }
2084
2085 /**
2086 * intel_disable_pipe - disable a pipe, asserting requirements
2087 * @crtc: crtc whose pipes is to be disabled
2088 *
2089 * Disable the pipe of @crtc, making sure that various hardware
2090 * specific requirements are met, if applicable, e.g. plane
2091 * disabled, panel fitter off, etc.
2092 *
2093 * Will wait until the pipe has shut down before returning.
2094 */
2095 static void intel_disable_pipe(struct intel_crtc *crtc)
2096 {
2097 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2098 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2099 enum pipe pipe = crtc->pipe;
2100 int reg;
2101 u32 val;
2102
2103 /*
2104 * Make sure planes won't keep trying to pump pixels to us,
2105 * or we might hang the display.
2106 */
2107 assert_planes_disabled(dev_priv, pipe);
2108 assert_cursor_disabled(dev_priv, pipe);
2109 assert_sprites_disabled(dev_priv, pipe);
2110
2111 reg = PIPECONF(cpu_transcoder);
2112 val = I915_READ(reg);
2113 if ((val & PIPECONF_ENABLE) == 0)
2114 return;
2115
2116 /*
2117 * Double wide has implications for planes
2118 * so best keep it disabled when not needed.
2119 */
2120 if (crtc->config.double_wide)
2121 val &= ~PIPECONF_DOUBLE_WIDE;
2122
2123 /* Don't disable pipe or pipe PLLs if needed */
2124 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2125 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2126 val &= ~PIPECONF_ENABLE;
2127
2128 I915_WRITE(reg, val);
2129 if ((val & PIPECONF_ENABLE) == 0)
2130 intel_wait_for_pipe_off(crtc);
2131 }
2132
2133 /*
2134 * Plane regs are double buffered, going from enabled->disabled needs a
2135 * trigger in order to latch. The display address reg provides this.
2136 */
2137 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2138 enum plane plane)
2139 {
2140 struct drm_device *dev = dev_priv->dev;
2141 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2142
2143 I915_WRITE(reg, I915_READ(reg));
2144 POSTING_READ(reg);
2145 }
2146
2147 /**
2148 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2149 * @plane: plane to be enabled
2150 * @crtc: crtc for the plane
2151 *
2152 * Enable @plane on @crtc, making sure that the pipe is running first.
2153 */
2154 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2155 struct drm_crtc *crtc)
2156 {
2157 struct drm_device *dev = plane->dev;
2158 struct drm_i915_private *dev_priv = dev->dev_private;
2159 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2160
2161 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2162 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2163
2164 if (intel_crtc->primary_enabled)
2165 return;
2166
2167 intel_crtc->primary_enabled = true;
2168
2169 dev_priv->display.update_primary_plane(crtc, plane->fb,
2170 crtc->x, crtc->y);
2171
2172 /*
2173 * BDW signals flip done immediately if the plane
2174 * is disabled, even if the plane enable is already
2175 * armed to occur at the next vblank :(
2176 */
2177 if (IS_BROADWELL(dev))
2178 intel_wait_for_vblank(dev, intel_crtc->pipe);
2179 }
2180
2181 /**
2182 * intel_disable_primary_hw_plane - disable the primary hardware plane
2183 * @plane: plane to be disabled
2184 * @crtc: crtc for the plane
2185 *
2186 * Disable @plane on @crtc, making sure that the pipe is running first.
2187 */
2188 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2189 struct drm_crtc *crtc)
2190 {
2191 struct drm_device *dev = plane->dev;
2192 struct drm_i915_private *dev_priv = dev->dev_private;
2193 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2194
2195 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2196
2197 if (!intel_crtc->primary_enabled)
2198 return;
2199
2200 intel_crtc->primary_enabled = false;
2201
2202 dev_priv->display.update_primary_plane(crtc, plane->fb,
2203 crtc->x, crtc->y);
2204 }
2205
2206 static bool need_vtd_wa(struct drm_device *dev)
2207 {
2208 #ifdef CONFIG_INTEL_IOMMU
2209 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2210 return true;
2211 #endif
2212 return false;
2213 }
2214
2215 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2216 {
2217 int tile_height;
2218
2219 tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2220 return ALIGN(height, tile_height);
2221 }
2222
2223 int
2224 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2225 struct drm_i915_gem_object *obj,
2226 struct intel_engine_cs *pipelined)
2227 {
2228 struct drm_i915_private *dev_priv = dev->dev_private;
2229 u32 alignment;
2230 int ret;
2231
2232 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2233
2234 switch (obj->tiling_mode) {
2235 case I915_TILING_NONE:
2236 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2237 alignment = 128 * 1024;
2238 else if (INTEL_INFO(dev)->gen >= 4)
2239 alignment = 4 * 1024;
2240 else
2241 alignment = 64 * 1024;
2242 break;
2243 case I915_TILING_X:
2244 /* pin() will align the object as required by fence */
2245 alignment = 0;
2246 break;
2247 case I915_TILING_Y:
2248 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2249 return -EINVAL;
2250 default:
2251 BUG();
2252 }
2253
2254 /* Note that the w/a also requires 64 PTE of padding following the
2255 * bo. We currently fill all unused PTE with the shadow page and so
2256 * we should always have valid PTE following the scanout preventing
2257 * the VT-d warning.
2258 */
2259 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2260 alignment = 256 * 1024;
2261
2262 /*
2263 * Global gtt pte registers are special registers which actually forward
2264 * writes to a chunk of system memory. Which means that there is no risk
2265 * that the register values disappear as soon as we call
2266 * intel_runtime_pm_put(), so it is correct to wrap only the
2267 * pin/unpin/fence and not more.
2268 */
2269 intel_runtime_pm_get(dev_priv);
2270
2271 dev_priv->mm.interruptible = false;
2272 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2273 if (ret)
2274 goto err_interruptible;
2275
2276 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2277 * fence, whereas 965+ only requires a fence if using
2278 * framebuffer compression. For simplicity, we always install
2279 * a fence as the cost is not that onerous.
2280 */
2281 ret = i915_gem_object_get_fence(obj);
2282 if (ret)
2283 goto err_unpin;
2284
2285 i915_gem_object_pin_fence(obj);
2286
2287 dev_priv->mm.interruptible = true;
2288 intel_runtime_pm_put(dev_priv);
2289 return 0;
2290
2291 err_unpin:
2292 i915_gem_object_unpin_from_display_plane(obj);
2293 err_interruptible:
2294 dev_priv->mm.interruptible = true;
2295 intel_runtime_pm_put(dev_priv);
2296 return ret;
2297 }
2298
2299 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2300 {
2301 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2302
2303 i915_gem_object_unpin_fence(obj);
2304 i915_gem_object_unpin_from_display_plane(obj);
2305 }
2306
2307 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2308 * is assumed to be a power-of-two. */
2309 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2310 unsigned int tiling_mode,
2311 unsigned int cpp,
2312 unsigned int pitch)
2313 {
2314 if (tiling_mode != I915_TILING_NONE) {
2315 unsigned int tile_rows, tiles;
2316
2317 tile_rows = *y / 8;
2318 *y %= 8;
2319
2320 tiles = *x / (512/cpp);
2321 *x %= 512/cpp;
2322
2323 return tile_rows * pitch * 8 + tiles * 4096;
2324 } else {
2325 unsigned int offset;
2326
2327 offset = *y * pitch + *x * cpp;
2328 *y = 0;
2329 *x = (offset & 4095) / cpp;
2330 return offset & -4096;
2331 }
2332 }
2333
2334 int intel_format_to_fourcc(int format)
2335 {
2336 switch (format) {
2337 case DISPPLANE_8BPP:
2338 return DRM_FORMAT_C8;
2339 case DISPPLANE_BGRX555:
2340 return DRM_FORMAT_XRGB1555;
2341 case DISPPLANE_BGRX565:
2342 return DRM_FORMAT_RGB565;
2343 default:
2344 case DISPPLANE_BGRX888:
2345 return DRM_FORMAT_XRGB8888;
2346 case DISPPLANE_RGBX888:
2347 return DRM_FORMAT_XBGR8888;
2348 case DISPPLANE_BGRX101010:
2349 return DRM_FORMAT_XRGB2101010;
2350 case DISPPLANE_RGBX101010:
2351 return DRM_FORMAT_XBGR2101010;
2352 }
2353 }
2354
2355 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2356 struct intel_plane_config *plane_config)
2357 {
2358 struct drm_device *dev = crtc->base.dev;
2359 struct drm_i915_gem_object *obj = NULL;
2360 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2361 u32 base = plane_config->base;
2362
2363 if (plane_config->size == 0)
2364 return false;
2365
2366 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2367 plane_config->size);
2368 if (!obj)
2369 return false;
2370
2371 if (plane_config->tiled) {
2372 obj->tiling_mode = I915_TILING_X;
2373 obj->stride = crtc->base.primary->fb->pitches[0];
2374 }
2375
2376 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2377 mode_cmd.width = crtc->base.primary->fb->width;
2378 mode_cmd.height = crtc->base.primary->fb->height;
2379 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2380
2381 mutex_lock(&dev->struct_mutex);
2382
2383 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2384 &mode_cmd, obj)) {
2385 DRM_DEBUG_KMS("intel fb init failed\n");
2386 goto out_unref_obj;
2387 }
2388
2389 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2390 mutex_unlock(&dev->struct_mutex);
2391
2392 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2393 return true;
2394
2395 out_unref_obj:
2396 drm_gem_object_unreference(&obj->base);
2397 mutex_unlock(&dev->struct_mutex);
2398 return false;
2399 }
2400
2401 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2402 struct intel_plane_config *plane_config)
2403 {
2404 struct drm_device *dev = intel_crtc->base.dev;
2405 struct drm_crtc *c;
2406 struct intel_crtc *i;
2407 struct drm_i915_gem_object *obj;
2408
2409 if (!intel_crtc->base.primary->fb)
2410 return;
2411
2412 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2413 return;
2414
2415 kfree(intel_crtc->base.primary->fb);
2416 intel_crtc->base.primary->fb = NULL;
2417
2418 /*
2419 * Failed to alloc the obj, check to see if we should share
2420 * an fb with another CRTC instead
2421 */
2422 for_each_crtc(dev, c) {
2423 i = to_intel_crtc(c);
2424
2425 if (c == &intel_crtc->base)
2426 continue;
2427
2428 if (!i->active)
2429 continue;
2430
2431 obj = intel_fb_obj(c->primary->fb);
2432 if (obj == NULL)
2433 continue;
2434
2435 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2436 drm_framebuffer_reference(c->primary->fb);
2437 intel_crtc->base.primary->fb = c->primary->fb;
2438 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2439 break;
2440 }
2441 }
2442 }
2443
2444 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2445 struct drm_framebuffer *fb,
2446 int x, int y)
2447 {
2448 struct drm_device *dev = crtc->dev;
2449 struct drm_i915_private *dev_priv = dev->dev_private;
2450 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2451 struct drm_i915_gem_object *obj;
2452 int plane = intel_crtc->plane;
2453 unsigned long linear_offset;
2454 u32 dspcntr;
2455 u32 reg = DSPCNTR(plane);
2456 int pixel_size;
2457
2458 if (!intel_crtc->primary_enabled) {
2459 I915_WRITE(reg, 0);
2460 if (INTEL_INFO(dev)->gen >= 4)
2461 I915_WRITE(DSPSURF(plane), 0);
2462 else
2463 I915_WRITE(DSPADDR(plane), 0);
2464 POSTING_READ(reg);
2465 return;
2466 }
2467
2468 obj = intel_fb_obj(fb);
2469 if (WARN_ON(obj == NULL))
2470 return;
2471
2472 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2473
2474 dspcntr = DISPPLANE_GAMMA_ENABLE;
2475
2476 dspcntr |= DISPLAY_PLANE_ENABLE;
2477
2478 if (INTEL_INFO(dev)->gen < 4) {
2479 if (intel_crtc->pipe == PIPE_B)
2480 dspcntr |= DISPPLANE_SEL_PIPE_B;
2481
2482 /* pipesrc and dspsize control the size that is scaled from,
2483 * which should always be the user's requested size.
2484 */
2485 I915_WRITE(DSPSIZE(plane),
2486 ((intel_crtc->config.pipe_src_h - 1) << 16) |
2487 (intel_crtc->config.pipe_src_w - 1));
2488 I915_WRITE(DSPPOS(plane), 0);
2489 }
2490
2491 switch (fb->pixel_format) {
2492 case DRM_FORMAT_C8:
2493 dspcntr |= DISPPLANE_8BPP;
2494 break;
2495 case DRM_FORMAT_XRGB1555:
2496 case DRM_FORMAT_ARGB1555:
2497 dspcntr |= DISPPLANE_BGRX555;
2498 break;
2499 case DRM_FORMAT_RGB565:
2500 dspcntr |= DISPPLANE_BGRX565;
2501 break;
2502 case DRM_FORMAT_XRGB8888:
2503 case DRM_FORMAT_ARGB8888:
2504 dspcntr |= DISPPLANE_BGRX888;
2505 break;
2506 case DRM_FORMAT_XBGR8888:
2507 case DRM_FORMAT_ABGR8888:
2508 dspcntr |= DISPPLANE_RGBX888;
2509 break;
2510 case DRM_FORMAT_XRGB2101010:
2511 case DRM_FORMAT_ARGB2101010:
2512 dspcntr |= DISPPLANE_BGRX101010;
2513 break;
2514 case DRM_FORMAT_XBGR2101010:
2515 case DRM_FORMAT_ABGR2101010:
2516 dspcntr |= DISPPLANE_RGBX101010;
2517 break;
2518 default:
2519 BUG();
2520 }
2521
2522 if (INTEL_INFO(dev)->gen >= 4 &&
2523 obj->tiling_mode != I915_TILING_NONE)
2524 dspcntr |= DISPPLANE_TILED;
2525
2526 if (IS_G4X(dev))
2527 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2528
2529 linear_offset = y * fb->pitches[0] + x * pixel_size;
2530
2531 if (INTEL_INFO(dev)->gen >= 4) {
2532 intel_crtc->dspaddr_offset =
2533 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2534 pixel_size,
2535 fb->pitches[0]);
2536 linear_offset -= intel_crtc->dspaddr_offset;
2537 } else {
2538 intel_crtc->dspaddr_offset = linear_offset;
2539 }
2540
2541 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2542 dspcntr |= DISPPLANE_ROTATE_180;
2543
2544 x += (intel_crtc->config.pipe_src_w - 1);
2545 y += (intel_crtc->config.pipe_src_h - 1);
2546
2547 /* Finding the last pixel of the last line of the display
2548 data and adding to linear_offset*/
2549 linear_offset +=
2550 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2551 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2552 }
2553
2554 I915_WRITE(reg, dspcntr);
2555
2556 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2557 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2558 fb->pitches[0]);
2559 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2560 if (INTEL_INFO(dev)->gen >= 4) {
2561 I915_WRITE(DSPSURF(plane),
2562 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2563 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2564 I915_WRITE(DSPLINOFF(plane), linear_offset);
2565 } else
2566 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2567 POSTING_READ(reg);
2568 }
2569
2570 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2571 struct drm_framebuffer *fb,
2572 int x, int y)
2573 {
2574 struct drm_device *dev = crtc->dev;
2575 struct drm_i915_private *dev_priv = dev->dev_private;
2576 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2577 struct drm_i915_gem_object *obj;
2578 int plane = intel_crtc->plane;
2579 unsigned long linear_offset;
2580 u32 dspcntr;
2581 u32 reg = DSPCNTR(plane);
2582 int pixel_size;
2583
2584 if (!intel_crtc->primary_enabled) {
2585 I915_WRITE(reg, 0);
2586 I915_WRITE(DSPSURF(plane), 0);
2587 POSTING_READ(reg);
2588 return;
2589 }
2590
2591 obj = intel_fb_obj(fb);
2592 if (WARN_ON(obj == NULL))
2593 return;
2594
2595 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2596
2597 dspcntr = DISPPLANE_GAMMA_ENABLE;
2598
2599 dspcntr |= DISPLAY_PLANE_ENABLE;
2600
2601 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2602 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2603
2604 switch (fb->pixel_format) {
2605 case DRM_FORMAT_C8:
2606 dspcntr |= DISPPLANE_8BPP;
2607 break;
2608 case DRM_FORMAT_RGB565:
2609 dspcntr |= DISPPLANE_BGRX565;
2610 break;
2611 case DRM_FORMAT_XRGB8888:
2612 case DRM_FORMAT_ARGB8888:
2613 dspcntr |= DISPPLANE_BGRX888;
2614 break;
2615 case DRM_FORMAT_XBGR8888:
2616 case DRM_FORMAT_ABGR8888:
2617 dspcntr |= DISPPLANE_RGBX888;
2618 break;
2619 case DRM_FORMAT_XRGB2101010:
2620 case DRM_FORMAT_ARGB2101010:
2621 dspcntr |= DISPPLANE_BGRX101010;
2622 break;
2623 case DRM_FORMAT_XBGR2101010:
2624 case DRM_FORMAT_ABGR2101010:
2625 dspcntr |= DISPPLANE_RGBX101010;
2626 break;
2627 default:
2628 BUG();
2629 }
2630
2631 if (obj->tiling_mode != I915_TILING_NONE)
2632 dspcntr |= DISPPLANE_TILED;
2633
2634 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2635 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2636
2637 linear_offset = y * fb->pitches[0] + x * pixel_size;
2638 intel_crtc->dspaddr_offset =
2639 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2640 pixel_size,
2641 fb->pitches[0]);
2642 linear_offset -= intel_crtc->dspaddr_offset;
2643 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2644 dspcntr |= DISPPLANE_ROTATE_180;
2645
2646 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2647 x += (intel_crtc->config.pipe_src_w - 1);
2648 y += (intel_crtc->config.pipe_src_h - 1);
2649
2650 /* Finding the last pixel of the last line of the display
2651 data and adding to linear_offset*/
2652 linear_offset +=
2653 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2654 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2655 }
2656 }
2657
2658 I915_WRITE(reg, dspcntr);
2659
2660 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2661 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2662 fb->pitches[0]);
2663 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2664 I915_WRITE(DSPSURF(plane),
2665 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2666 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2667 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2668 } else {
2669 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2670 I915_WRITE(DSPLINOFF(plane), linear_offset);
2671 }
2672 POSTING_READ(reg);
2673 }
2674
2675 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2676 static int
2677 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2678 int x, int y, enum mode_set_atomic state)
2679 {
2680 struct drm_device *dev = crtc->dev;
2681 struct drm_i915_private *dev_priv = dev->dev_private;
2682
2683 if (dev_priv->display.disable_fbc)
2684 dev_priv->display.disable_fbc(dev);
2685 intel_increase_pllclock(dev, to_intel_crtc(crtc)->pipe);
2686
2687 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2688
2689 return 0;
2690 }
2691
2692 void intel_display_handle_reset(struct drm_device *dev)
2693 {
2694 struct drm_i915_private *dev_priv = dev->dev_private;
2695 struct drm_crtc *crtc;
2696
2697 /*
2698 * Flips in the rings have been nuked by the reset,
2699 * so complete all pending flips so that user space
2700 * will get its events and not get stuck.
2701 *
2702 * Also update the base address of all primary
2703 * planes to the the last fb to make sure we're
2704 * showing the correct fb after a reset.
2705 *
2706 * Need to make two loops over the crtcs so that we
2707 * don't try to grab a crtc mutex before the
2708 * pending_flip_queue really got woken up.
2709 */
2710
2711 for_each_crtc(dev, crtc) {
2712 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2713 enum plane plane = intel_crtc->plane;
2714
2715 intel_prepare_page_flip(dev, plane);
2716 intel_finish_page_flip_plane(dev, plane);
2717 }
2718
2719 for_each_crtc(dev, crtc) {
2720 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2721
2722 drm_modeset_lock(&crtc->mutex, NULL);
2723 /*
2724 * FIXME: Once we have proper support for primary planes (and
2725 * disabling them without disabling the entire crtc) allow again
2726 * a NULL crtc->primary->fb.
2727 */
2728 if (intel_crtc->active && crtc->primary->fb)
2729 dev_priv->display.update_primary_plane(crtc,
2730 crtc->primary->fb,
2731 crtc->x,
2732 crtc->y);
2733 drm_modeset_unlock(&crtc->mutex);
2734 }
2735 }
2736
2737 static int
2738 intel_finish_fb(struct drm_framebuffer *old_fb)
2739 {
2740 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2741 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2742 bool was_interruptible = dev_priv->mm.interruptible;
2743 int ret;
2744
2745 /* Big Hammer, we also need to ensure that any pending
2746 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2747 * current scanout is retired before unpinning the old
2748 * framebuffer.
2749 *
2750 * This should only fail upon a hung GPU, in which case we
2751 * can safely continue.
2752 */
2753 dev_priv->mm.interruptible = false;
2754 ret = i915_gem_object_finish_gpu(obj);
2755 dev_priv->mm.interruptible = was_interruptible;
2756
2757 return ret;
2758 }
2759
2760 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2761 {
2762 struct drm_device *dev = crtc->dev;
2763 struct drm_i915_private *dev_priv = dev->dev_private;
2764 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2765 unsigned long flags;
2766 bool pending;
2767
2768 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2769 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2770 return false;
2771
2772 spin_lock_irqsave(&dev->event_lock, flags);
2773 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2774 spin_unlock_irqrestore(&dev->event_lock, flags);
2775
2776 return pending;
2777 }
2778
2779 static int
2780 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2781 struct drm_framebuffer *fb)
2782 {
2783 struct drm_device *dev = crtc->dev;
2784 struct drm_i915_private *dev_priv = dev->dev_private;
2785 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2786 enum pipe pipe = intel_crtc->pipe;
2787 struct drm_framebuffer *old_fb = crtc->primary->fb;
2788 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2789 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
2790 int ret;
2791
2792 if (intel_crtc_has_pending_flip(crtc)) {
2793 DRM_ERROR("pipe is still busy with an old pageflip\n");
2794 return -EBUSY;
2795 }
2796
2797 /* no fb bound */
2798 if (!fb) {
2799 DRM_ERROR("No FB bound\n");
2800 return 0;
2801 }
2802
2803 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2804 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2805 plane_name(intel_crtc->plane),
2806 INTEL_INFO(dev)->num_pipes);
2807 return -EINVAL;
2808 }
2809
2810 mutex_lock(&dev->struct_mutex);
2811 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
2812 if (ret == 0)
2813 i915_gem_track_fb(old_obj, obj,
2814 INTEL_FRONTBUFFER_PRIMARY(pipe));
2815 mutex_unlock(&dev->struct_mutex);
2816 if (ret != 0) {
2817 DRM_ERROR("pin & fence failed\n");
2818 return ret;
2819 }
2820
2821 /*
2822 * Update pipe size and adjust fitter if needed: the reason for this is
2823 * that in compute_mode_changes we check the native mode (not the pfit
2824 * mode) to see if we can flip rather than do a full mode set. In the
2825 * fastboot case, we'll flip, but if we don't update the pipesrc and
2826 * pfit state, we'll end up with a big fb scanned out into the wrong
2827 * sized surface.
2828 *
2829 * To fix this properly, we need to hoist the checks up into
2830 * compute_mode_changes (or above), check the actual pfit state and
2831 * whether the platform allows pfit disable with pipe active, and only
2832 * then update the pipesrc and pfit state, even on the flip path.
2833 */
2834 if (i915.fastboot) {
2835 const struct drm_display_mode *adjusted_mode =
2836 &intel_crtc->config.adjusted_mode;
2837
2838 I915_WRITE(PIPESRC(intel_crtc->pipe),
2839 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2840 (adjusted_mode->crtc_vdisplay - 1));
2841 if (!intel_crtc->config.pch_pfit.enabled &&
2842 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2843 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2844 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2845 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2846 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2847 }
2848 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2849 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2850 }
2851
2852 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2853
2854 if (intel_crtc->active)
2855 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
2856
2857 crtc->primary->fb = fb;
2858 crtc->x = x;
2859 crtc->y = y;
2860
2861 if (old_fb) {
2862 if (intel_crtc->active && old_fb != fb)
2863 intel_wait_for_vblank(dev, intel_crtc->pipe);
2864 mutex_lock(&dev->struct_mutex);
2865 intel_unpin_fb_obj(old_obj);
2866 mutex_unlock(&dev->struct_mutex);
2867 }
2868
2869 mutex_lock(&dev->struct_mutex);
2870 intel_update_fbc(dev);
2871 mutex_unlock(&dev->struct_mutex);
2872
2873 return 0;
2874 }
2875
2876 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2877 {
2878 struct drm_device *dev = crtc->dev;
2879 struct drm_i915_private *dev_priv = dev->dev_private;
2880 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2881 int pipe = intel_crtc->pipe;
2882 u32 reg, temp;
2883
2884 /* enable normal train */
2885 reg = FDI_TX_CTL(pipe);
2886 temp = I915_READ(reg);
2887 if (IS_IVYBRIDGE(dev)) {
2888 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2889 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2890 } else {
2891 temp &= ~FDI_LINK_TRAIN_NONE;
2892 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2893 }
2894 I915_WRITE(reg, temp);
2895
2896 reg = FDI_RX_CTL(pipe);
2897 temp = I915_READ(reg);
2898 if (HAS_PCH_CPT(dev)) {
2899 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2900 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2901 } else {
2902 temp &= ~FDI_LINK_TRAIN_NONE;
2903 temp |= FDI_LINK_TRAIN_NONE;
2904 }
2905 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2906
2907 /* wait one idle pattern time */
2908 POSTING_READ(reg);
2909 udelay(1000);
2910
2911 /* IVB wants error correction enabled */
2912 if (IS_IVYBRIDGE(dev))
2913 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2914 FDI_FE_ERRC_ENABLE);
2915 }
2916
2917 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2918 {
2919 return crtc->base.enabled && crtc->active &&
2920 crtc->config.has_pch_encoder;
2921 }
2922
2923 static void ivb_modeset_global_resources(struct drm_device *dev)
2924 {
2925 struct drm_i915_private *dev_priv = dev->dev_private;
2926 struct intel_crtc *pipe_B_crtc =
2927 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2928 struct intel_crtc *pipe_C_crtc =
2929 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2930 uint32_t temp;
2931
2932 /*
2933 * When everything is off disable fdi C so that we could enable fdi B
2934 * with all lanes. Note that we don't care about enabled pipes without
2935 * an enabled pch encoder.
2936 */
2937 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2938 !pipe_has_enabled_pch(pipe_C_crtc)) {
2939 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2940 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2941
2942 temp = I915_READ(SOUTH_CHICKEN1);
2943 temp &= ~FDI_BC_BIFURCATION_SELECT;
2944 DRM_DEBUG_KMS("disabling fdi C rx\n");
2945 I915_WRITE(SOUTH_CHICKEN1, temp);
2946 }
2947 }
2948
2949 /* The FDI link training functions for ILK/Ibexpeak. */
2950 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2951 {
2952 struct drm_device *dev = crtc->dev;
2953 struct drm_i915_private *dev_priv = dev->dev_private;
2954 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2955 int pipe = intel_crtc->pipe;
2956 u32 reg, temp, tries;
2957
2958 /* FDI needs bits from pipe first */
2959 assert_pipe_enabled(dev_priv, pipe);
2960
2961 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2962 for train result */
2963 reg = FDI_RX_IMR(pipe);
2964 temp = I915_READ(reg);
2965 temp &= ~FDI_RX_SYMBOL_LOCK;
2966 temp &= ~FDI_RX_BIT_LOCK;
2967 I915_WRITE(reg, temp);
2968 I915_READ(reg);
2969 udelay(150);
2970
2971 /* enable CPU FDI TX and PCH FDI RX */
2972 reg = FDI_TX_CTL(pipe);
2973 temp = I915_READ(reg);
2974 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2975 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2976 temp &= ~FDI_LINK_TRAIN_NONE;
2977 temp |= FDI_LINK_TRAIN_PATTERN_1;
2978 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2979
2980 reg = FDI_RX_CTL(pipe);
2981 temp = I915_READ(reg);
2982 temp &= ~FDI_LINK_TRAIN_NONE;
2983 temp |= FDI_LINK_TRAIN_PATTERN_1;
2984 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2985
2986 POSTING_READ(reg);
2987 udelay(150);
2988
2989 /* Ironlake workaround, enable clock pointer after FDI enable*/
2990 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2991 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2992 FDI_RX_PHASE_SYNC_POINTER_EN);
2993
2994 reg = FDI_RX_IIR(pipe);
2995 for (tries = 0; tries < 5; tries++) {
2996 temp = I915_READ(reg);
2997 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2998
2999 if ((temp & FDI_RX_BIT_LOCK)) {
3000 DRM_DEBUG_KMS("FDI train 1 done.\n");
3001 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3002 break;
3003 }
3004 }
3005 if (tries == 5)
3006 DRM_ERROR("FDI train 1 fail!\n");
3007
3008 /* Train 2 */
3009 reg = FDI_TX_CTL(pipe);
3010 temp = I915_READ(reg);
3011 temp &= ~FDI_LINK_TRAIN_NONE;
3012 temp |= FDI_LINK_TRAIN_PATTERN_2;
3013 I915_WRITE(reg, temp);
3014
3015 reg = FDI_RX_CTL(pipe);
3016 temp = I915_READ(reg);
3017 temp &= ~FDI_LINK_TRAIN_NONE;
3018 temp |= FDI_LINK_TRAIN_PATTERN_2;
3019 I915_WRITE(reg, temp);
3020
3021 POSTING_READ(reg);
3022 udelay(150);
3023
3024 reg = FDI_RX_IIR(pipe);
3025 for (tries = 0; tries < 5; tries++) {
3026 temp = I915_READ(reg);
3027 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3028
3029 if (temp & FDI_RX_SYMBOL_LOCK) {
3030 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3031 DRM_DEBUG_KMS("FDI train 2 done.\n");
3032 break;
3033 }
3034 }
3035 if (tries == 5)
3036 DRM_ERROR("FDI train 2 fail!\n");
3037
3038 DRM_DEBUG_KMS("FDI train done\n");
3039
3040 }
3041
3042 static const int snb_b_fdi_train_param[] = {
3043 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3044 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3045 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3046 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3047 };
3048
3049 /* The FDI link training functions for SNB/Cougarpoint. */
3050 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3051 {
3052 struct drm_device *dev = crtc->dev;
3053 struct drm_i915_private *dev_priv = dev->dev_private;
3054 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3055 int pipe = intel_crtc->pipe;
3056 u32 reg, temp, i, retry;
3057
3058 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3059 for train result */
3060 reg = FDI_RX_IMR(pipe);
3061 temp = I915_READ(reg);
3062 temp &= ~FDI_RX_SYMBOL_LOCK;
3063 temp &= ~FDI_RX_BIT_LOCK;
3064 I915_WRITE(reg, temp);
3065
3066 POSTING_READ(reg);
3067 udelay(150);
3068
3069 /* enable CPU FDI TX and PCH FDI RX */
3070 reg = FDI_TX_CTL(pipe);
3071 temp = I915_READ(reg);
3072 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3073 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3074 temp &= ~FDI_LINK_TRAIN_NONE;
3075 temp |= FDI_LINK_TRAIN_PATTERN_1;
3076 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3077 /* SNB-B */
3078 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3079 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3080
3081 I915_WRITE(FDI_RX_MISC(pipe),
3082 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3083
3084 reg = FDI_RX_CTL(pipe);
3085 temp = I915_READ(reg);
3086 if (HAS_PCH_CPT(dev)) {
3087 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3088 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3089 } else {
3090 temp &= ~FDI_LINK_TRAIN_NONE;
3091 temp |= FDI_LINK_TRAIN_PATTERN_1;
3092 }
3093 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3094
3095 POSTING_READ(reg);
3096 udelay(150);
3097
3098 for (i = 0; i < 4; i++) {
3099 reg = FDI_TX_CTL(pipe);
3100 temp = I915_READ(reg);
3101 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3102 temp |= snb_b_fdi_train_param[i];
3103 I915_WRITE(reg, temp);
3104
3105 POSTING_READ(reg);
3106 udelay(500);
3107
3108 for (retry = 0; retry < 5; retry++) {
3109 reg = FDI_RX_IIR(pipe);
3110 temp = I915_READ(reg);
3111 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3112 if (temp & FDI_RX_BIT_LOCK) {
3113 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3114 DRM_DEBUG_KMS("FDI train 1 done.\n");
3115 break;
3116 }
3117 udelay(50);
3118 }
3119 if (retry < 5)
3120 break;
3121 }
3122 if (i == 4)
3123 DRM_ERROR("FDI train 1 fail!\n");
3124
3125 /* Train 2 */
3126 reg = FDI_TX_CTL(pipe);
3127 temp = I915_READ(reg);
3128 temp &= ~FDI_LINK_TRAIN_NONE;
3129 temp |= FDI_LINK_TRAIN_PATTERN_2;
3130 if (IS_GEN6(dev)) {
3131 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3132 /* SNB-B */
3133 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3134 }
3135 I915_WRITE(reg, temp);
3136
3137 reg = FDI_RX_CTL(pipe);
3138 temp = I915_READ(reg);
3139 if (HAS_PCH_CPT(dev)) {
3140 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3141 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3142 } else {
3143 temp &= ~FDI_LINK_TRAIN_NONE;
3144 temp |= FDI_LINK_TRAIN_PATTERN_2;
3145 }
3146 I915_WRITE(reg, temp);
3147
3148 POSTING_READ(reg);
3149 udelay(150);
3150
3151 for (i = 0; i < 4; i++) {
3152 reg = FDI_TX_CTL(pipe);
3153 temp = I915_READ(reg);
3154 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3155 temp |= snb_b_fdi_train_param[i];
3156 I915_WRITE(reg, temp);
3157
3158 POSTING_READ(reg);
3159 udelay(500);
3160
3161 for (retry = 0; retry < 5; retry++) {
3162 reg = FDI_RX_IIR(pipe);
3163 temp = I915_READ(reg);
3164 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3165 if (temp & FDI_RX_SYMBOL_LOCK) {
3166 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3167 DRM_DEBUG_KMS("FDI train 2 done.\n");
3168 break;
3169 }
3170 udelay(50);
3171 }
3172 if (retry < 5)
3173 break;
3174 }
3175 if (i == 4)
3176 DRM_ERROR("FDI train 2 fail!\n");
3177
3178 DRM_DEBUG_KMS("FDI train done.\n");
3179 }
3180
3181 /* Manual link training for Ivy Bridge A0 parts */
3182 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3183 {
3184 struct drm_device *dev = crtc->dev;
3185 struct drm_i915_private *dev_priv = dev->dev_private;
3186 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3187 int pipe = intel_crtc->pipe;
3188 u32 reg, temp, i, j;
3189
3190 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3191 for train result */
3192 reg = FDI_RX_IMR(pipe);
3193 temp = I915_READ(reg);
3194 temp &= ~FDI_RX_SYMBOL_LOCK;
3195 temp &= ~FDI_RX_BIT_LOCK;
3196 I915_WRITE(reg, temp);
3197
3198 POSTING_READ(reg);
3199 udelay(150);
3200
3201 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3202 I915_READ(FDI_RX_IIR(pipe)));
3203
3204 /* Try each vswing and preemphasis setting twice before moving on */
3205 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3206 /* disable first in case we need to retry */
3207 reg = FDI_TX_CTL(pipe);
3208 temp = I915_READ(reg);
3209 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3210 temp &= ~FDI_TX_ENABLE;
3211 I915_WRITE(reg, temp);
3212
3213 reg = FDI_RX_CTL(pipe);
3214 temp = I915_READ(reg);
3215 temp &= ~FDI_LINK_TRAIN_AUTO;
3216 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3217 temp &= ~FDI_RX_ENABLE;
3218 I915_WRITE(reg, temp);
3219
3220 /* enable CPU FDI TX and PCH FDI RX */
3221 reg = FDI_TX_CTL(pipe);
3222 temp = I915_READ(reg);
3223 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3224 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3225 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3226 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3227 temp |= snb_b_fdi_train_param[j/2];
3228 temp |= FDI_COMPOSITE_SYNC;
3229 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3230
3231 I915_WRITE(FDI_RX_MISC(pipe),
3232 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3233
3234 reg = FDI_RX_CTL(pipe);
3235 temp = I915_READ(reg);
3236 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3237 temp |= FDI_COMPOSITE_SYNC;
3238 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3239
3240 POSTING_READ(reg);
3241 udelay(1); /* should be 0.5us */
3242
3243 for (i = 0; i < 4; i++) {
3244 reg = FDI_RX_IIR(pipe);
3245 temp = I915_READ(reg);
3246 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3247
3248 if (temp & FDI_RX_BIT_LOCK ||
3249 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3250 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3251 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3252 i);
3253 break;
3254 }
3255 udelay(1); /* should be 0.5us */
3256 }
3257 if (i == 4) {
3258 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3259 continue;
3260 }
3261
3262 /* Train 2 */
3263 reg = FDI_TX_CTL(pipe);
3264 temp = I915_READ(reg);
3265 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3266 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3267 I915_WRITE(reg, temp);
3268
3269 reg = FDI_RX_CTL(pipe);
3270 temp = I915_READ(reg);
3271 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3272 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3273 I915_WRITE(reg, temp);
3274
3275 POSTING_READ(reg);
3276 udelay(2); /* should be 1.5us */
3277
3278 for (i = 0; i < 4; i++) {
3279 reg = FDI_RX_IIR(pipe);
3280 temp = I915_READ(reg);
3281 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3282
3283 if (temp & FDI_RX_SYMBOL_LOCK ||
3284 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3285 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3286 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3287 i);
3288 goto train_done;
3289 }
3290 udelay(2); /* should be 1.5us */
3291 }
3292 if (i == 4)
3293 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3294 }
3295
3296 train_done:
3297 DRM_DEBUG_KMS("FDI train done.\n");
3298 }
3299
3300 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3301 {
3302 struct drm_device *dev = intel_crtc->base.dev;
3303 struct drm_i915_private *dev_priv = dev->dev_private;
3304 int pipe = intel_crtc->pipe;
3305 u32 reg, temp;
3306
3307
3308 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3309 reg = FDI_RX_CTL(pipe);
3310 temp = I915_READ(reg);
3311 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3312 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3313 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3314 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3315
3316 POSTING_READ(reg);
3317 udelay(200);
3318
3319 /* Switch from Rawclk to PCDclk */
3320 temp = I915_READ(reg);
3321 I915_WRITE(reg, temp | FDI_PCDCLK);
3322
3323 POSTING_READ(reg);
3324 udelay(200);
3325
3326 /* Enable CPU FDI TX PLL, always on for Ironlake */
3327 reg = FDI_TX_CTL(pipe);
3328 temp = I915_READ(reg);
3329 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3330 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3331
3332 POSTING_READ(reg);
3333 udelay(100);
3334 }
3335 }
3336
3337 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3338 {
3339 struct drm_device *dev = intel_crtc->base.dev;
3340 struct drm_i915_private *dev_priv = dev->dev_private;
3341 int pipe = intel_crtc->pipe;
3342 u32 reg, temp;
3343
3344 /* Switch from PCDclk to Rawclk */
3345 reg = FDI_RX_CTL(pipe);
3346 temp = I915_READ(reg);
3347 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3348
3349 /* Disable CPU FDI TX PLL */
3350 reg = FDI_TX_CTL(pipe);
3351 temp = I915_READ(reg);
3352 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3353
3354 POSTING_READ(reg);
3355 udelay(100);
3356
3357 reg = FDI_RX_CTL(pipe);
3358 temp = I915_READ(reg);
3359 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3360
3361 /* Wait for the clocks to turn off. */
3362 POSTING_READ(reg);
3363 udelay(100);
3364 }
3365
3366 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3367 {
3368 struct drm_device *dev = crtc->dev;
3369 struct drm_i915_private *dev_priv = dev->dev_private;
3370 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3371 int pipe = intel_crtc->pipe;
3372 u32 reg, temp;
3373
3374 /* disable CPU FDI tx and PCH FDI rx */
3375 reg = FDI_TX_CTL(pipe);
3376 temp = I915_READ(reg);
3377 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3378 POSTING_READ(reg);
3379
3380 reg = FDI_RX_CTL(pipe);
3381 temp = I915_READ(reg);
3382 temp &= ~(0x7 << 16);
3383 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3384 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3385
3386 POSTING_READ(reg);
3387 udelay(100);
3388
3389 /* Ironlake workaround, disable clock pointer after downing FDI */
3390 if (HAS_PCH_IBX(dev))
3391 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3392
3393 /* still set train pattern 1 */
3394 reg = FDI_TX_CTL(pipe);
3395 temp = I915_READ(reg);
3396 temp &= ~FDI_LINK_TRAIN_NONE;
3397 temp |= FDI_LINK_TRAIN_PATTERN_1;
3398 I915_WRITE(reg, temp);
3399
3400 reg = FDI_RX_CTL(pipe);
3401 temp = I915_READ(reg);
3402 if (HAS_PCH_CPT(dev)) {
3403 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3404 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3405 } else {
3406 temp &= ~FDI_LINK_TRAIN_NONE;
3407 temp |= FDI_LINK_TRAIN_PATTERN_1;
3408 }
3409 /* BPC in FDI rx is consistent with that in PIPECONF */
3410 temp &= ~(0x07 << 16);
3411 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3412 I915_WRITE(reg, temp);
3413
3414 POSTING_READ(reg);
3415 udelay(100);
3416 }
3417
3418 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3419 {
3420 struct intel_crtc *crtc;
3421
3422 /* Note that we don't need to be called with mode_config.lock here
3423 * as our list of CRTC objects is static for the lifetime of the
3424 * device and so cannot disappear as we iterate. Similarly, we can
3425 * happily treat the predicates as racy, atomic checks as userspace
3426 * cannot claim and pin a new fb without at least acquring the
3427 * struct_mutex and so serialising with us.
3428 */
3429 for_each_intel_crtc(dev, crtc) {
3430 if (atomic_read(&crtc->unpin_work_count) == 0)
3431 continue;
3432
3433 if (crtc->unpin_work)
3434 intel_wait_for_vblank(dev, crtc->pipe);
3435
3436 return true;
3437 }
3438
3439 return false;
3440 }
3441
3442 static void page_flip_completed(struct intel_crtc *intel_crtc)
3443 {
3444 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3445 struct intel_unpin_work *work = intel_crtc->unpin_work;
3446
3447 /* ensure that the unpin work is consistent wrt ->pending. */
3448 smp_rmb();
3449 intel_crtc->unpin_work = NULL;
3450
3451 if (work->event)
3452 drm_send_vblank_event(intel_crtc->base.dev,
3453 intel_crtc->pipe,
3454 work->event);
3455
3456 drm_crtc_vblank_put(&intel_crtc->base);
3457
3458 wake_up_all(&dev_priv->pending_flip_queue);
3459 queue_work(dev_priv->wq, &work->work);
3460
3461 trace_i915_flip_complete(intel_crtc->plane,
3462 work->pending_flip_obj);
3463 }
3464
3465 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3466 {
3467 struct drm_device *dev = crtc->dev;
3468 struct drm_i915_private *dev_priv = dev->dev_private;
3469
3470 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3471 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3472 !intel_crtc_has_pending_flip(crtc),
3473 60*HZ) == 0)) {
3474 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3475 unsigned long flags;
3476
3477 spin_lock_irqsave(&dev->event_lock, flags);
3478 if (intel_crtc->unpin_work) {
3479 WARN_ONCE(1, "Removing stuck page flip\n");
3480 page_flip_completed(intel_crtc);
3481 }
3482 spin_unlock_irqrestore(&dev->event_lock, flags);
3483 }
3484
3485 if (crtc->primary->fb) {
3486 mutex_lock(&dev->struct_mutex);
3487 intel_finish_fb(crtc->primary->fb);
3488 mutex_unlock(&dev->struct_mutex);
3489 }
3490 }
3491
3492 /* Program iCLKIP clock to the desired frequency */
3493 static void lpt_program_iclkip(struct drm_crtc *crtc)
3494 {
3495 struct drm_device *dev = crtc->dev;
3496 struct drm_i915_private *dev_priv = dev->dev_private;
3497 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3498 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3499 u32 temp;
3500
3501 mutex_lock(&dev_priv->dpio_lock);
3502
3503 /* It is necessary to ungate the pixclk gate prior to programming
3504 * the divisors, and gate it back when it is done.
3505 */
3506 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3507
3508 /* Disable SSCCTL */
3509 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3510 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3511 SBI_SSCCTL_DISABLE,
3512 SBI_ICLK);
3513
3514 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3515 if (clock == 20000) {
3516 auxdiv = 1;
3517 divsel = 0x41;
3518 phaseinc = 0x20;
3519 } else {
3520 /* The iCLK virtual clock root frequency is in MHz,
3521 * but the adjusted_mode->crtc_clock in in KHz. To get the
3522 * divisors, it is necessary to divide one by another, so we
3523 * convert the virtual clock precision to KHz here for higher
3524 * precision.
3525 */
3526 u32 iclk_virtual_root_freq = 172800 * 1000;
3527 u32 iclk_pi_range = 64;
3528 u32 desired_divisor, msb_divisor_value, pi_value;
3529
3530 desired_divisor = (iclk_virtual_root_freq / clock);
3531 msb_divisor_value = desired_divisor / iclk_pi_range;
3532 pi_value = desired_divisor % iclk_pi_range;
3533
3534 auxdiv = 0;
3535 divsel = msb_divisor_value - 2;
3536 phaseinc = pi_value;
3537 }
3538
3539 /* This should not happen with any sane values */
3540 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3541 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3542 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3543 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3544
3545 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3546 clock,
3547 auxdiv,
3548 divsel,
3549 phasedir,
3550 phaseinc);
3551
3552 /* Program SSCDIVINTPHASE6 */
3553 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3554 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3555 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3556 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3557 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3558 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3559 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3560 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3561
3562 /* Program SSCAUXDIV */
3563 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3564 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3565 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3566 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3567
3568 /* Enable modulator and associated divider */
3569 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3570 temp &= ~SBI_SSCCTL_DISABLE;
3571 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3572
3573 /* Wait for initialization time */
3574 udelay(24);
3575
3576 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3577
3578 mutex_unlock(&dev_priv->dpio_lock);
3579 }
3580
3581 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3582 enum pipe pch_transcoder)
3583 {
3584 struct drm_device *dev = crtc->base.dev;
3585 struct drm_i915_private *dev_priv = dev->dev_private;
3586 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3587
3588 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3589 I915_READ(HTOTAL(cpu_transcoder)));
3590 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3591 I915_READ(HBLANK(cpu_transcoder)));
3592 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3593 I915_READ(HSYNC(cpu_transcoder)));
3594
3595 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3596 I915_READ(VTOTAL(cpu_transcoder)));
3597 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3598 I915_READ(VBLANK(cpu_transcoder)));
3599 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3600 I915_READ(VSYNC(cpu_transcoder)));
3601 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3602 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3603 }
3604
3605 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3606 {
3607 struct drm_i915_private *dev_priv = dev->dev_private;
3608 uint32_t temp;
3609
3610 temp = I915_READ(SOUTH_CHICKEN1);
3611 if (temp & FDI_BC_BIFURCATION_SELECT)
3612 return;
3613
3614 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3615 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3616
3617 temp |= FDI_BC_BIFURCATION_SELECT;
3618 DRM_DEBUG_KMS("enabling fdi C rx\n");
3619 I915_WRITE(SOUTH_CHICKEN1, temp);
3620 POSTING_READ(SOUTH_CHICKEN1);
3621 }
3622
3623 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3624 {
3625 struct drm_device *dev = intel_crtc->base.dev;
3626 struct drm_i915_private *dev_priv = dev->dev_private;
3627
3628 switch (intel_crtc->pipe) {
3629 case PIPE_A:
3630 break;
3631 case PIPE_B:
3632 if (intel_crtc->config.fdi_lanes > 2)
3633 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3634 else
3635 cpt_enable_fdi_bc_bifurcation(dev);
3636
3637 break;
3638 case PIPE_C:
3639 cpt_enable_fdi_bc_bifurcation(dev);
3640
3641 break;
3642 default:
3643 BUG();
3644 }
3645 }
3646
3647 /*
3648 * Enable PCH resources required for PCH ports:
3649 * - PCH PLLs
3650 * - FDI training & RX/TX
3651 * - update transcoder timings
3652 * - DP transcoding bits
3653 * - transcoder
3654 */
3655 static void ironlake_pch_enable(struct drm_crtc *crtc)
3656 {
3657 struct drm_device *dev = crtc->dev;
3658 struct drm_i915_private *dev_priv = dev->dev_private;
3659 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3660 int pipe = intel_crtc->pipe;
3661 u32 reg, temp;
3662
3663 assert_pch_transcoder_disabled(dev_priv, pipe);
3664
3665 if (IS_IVYBRIDGE(dev))
3666 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3667
3668 /* Write the TU size bits before fdi link training, so that error
3669 * detection works. */
3670 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3671 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3672
3673 /* For PCH output, training FDI link */
3674 dev_priv->display.fdi_link_train(crtc);
3675
3676 /* We need to program the right clock selection before writing the pixel
3677 * mutliplier into the DPLL. */
3678 if (HAS_PCH_CPT(dev)) {
3679 u32 sel;
3680
3681 temp = I915_READ(PCH_DPLL_SEL);
3682 temp |= TRANS_DPLL_ENABLE(pipe);
3683 sel = TRANS_DPLLB_SEL(pipe);
3684 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3685 temp |= sel;
3686 else
3687 temp &= ~sel;
3688 I915_WRITE(PCH_DPLL_SEL, temp);
3689 }
3690
3691 /* XXX: pch pll's can be enabled any time before we enable the PCH
3692 * transcoder, and we actually should do this to not upset any PCH
3693 * transcoder that already use the clock when we share it.
3694 *
3695 * Note that enable_shared_dpll tries to do the right thing, but
3696 * get_shared_dpll unconditionally resets the pll - we need that to have
3697 * the right LVDS enable sequence. */
3698 intel_enable_shared_dpll(intel_crtc);
3699
3700 /* set transcoder timing, panel must allow it */
3701 assert_panel_unlocked(dev_priv, pipe);
3702 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3703
3704 intel_fdi_normal_train(crtc);
3705
3706 /* For PCH DP, enable TRANS_DP_CTL */
3707 if (HAS_PCH_CPT(dev) &&
3708 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3709 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3710 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3711 reg = TRANS_DP_CTL(pipe);
3712 temp = I915_READ(reg);
3713 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3714 TRANS_DP_SYNC_MASK |
3715 TRANS_DP_BPC_MASK);
3716 temp |= (TRANS_DP_OUTPUT_ENABLE |
3717 TRANS_DP_ENH_FRAMING);
3718 temp |= bpc << 9; /* same format but at 11:9 */
3719
3720 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3721 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3722 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3723 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3724
3725 switch (intel_trans_dp_port_sel(crtc)) {
3726 case PCH_DP_B:
3727 temp |= TRANS_DP_PORT_SEL_B;
3728 break;
3729 case PCH_DP_C:
3730 temp |= TRANS_DP_PORT_SEL_C;
3731 break;
3732 case PCH_DP_D:
3733 temp |= TRANS_DP_PORT_SEL_D;
3734 break;
3735 default:
3736 BUG();
3737 }
3738
3739 I915_WRITE(reg, temp);
3740 }
3741
3742 ironlake_enable_pch_transcoder(dev_priv, pipe);
3743 }
3744
3745 static void lpt_pch_enable(struct drm_crtc *crtc)
3746 {
3747 struct drm_device *dev = crtc->dev;
3748 struct drm_i915_private *dev_priv = dev->dev_private;
3749 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3750 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3751
3752 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3753
3754 lpt_program_iclkip(crtc);
3755
3756 /* Set transcoder timing. */
3757 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3758
3759 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3760 }
3761
3762 void intel_put_shared_dpll(struct intel_crtc *crtc)
3763 {
3764 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3765
3766 if (pll == NULL)
3767 return;
3768
3769 if (pll->refcount == 0) {
3770 WARN(1, "bad %s refcount\n", pll->name);
3771 return;
3772 }
3773
3774 if (--pll->refcount == 0) {
3775 WARN_ON(pll->on);
3776 WARN_ON(pll->active);
3777 }
3778
3779 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3780 }
3781
3782 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3783 {
3784 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3785 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3786 enum intel_dpll_id i;
3787
3788 if (pll) {
3789 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3790 crtc->base.base.id, pll->name);
3791 intel_put_shared_dpll(crtc);
3792 }
3793
3794 if (HAS_PCH_IBX(dev_priv->dev)) {
3795 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3796 i = (enum intel_dpll_id) crtc->pipe;
3797 pll = &dev_priv->shared_dplls[i];
3798
3799 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3800 crtc->base.base.id, pll->name);
3801
3802 WARN_ON(pll->refcount);
3803
3804 goto found;
3805 }
3806
3807 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3808 pll = &dev_priv->shared_dplls[i];
3809
3810 /* Only want to check enabled timings first */
3811 if (pll->refcount == 0)
3812 continue;
3813
3814 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3815 sizeof(pll->hw_state)) == 0) {
3816 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3817 crtc->base.base.id,
3818 pll->name, pll->refcount, pll->active);
3819
3820 goto found;
3821 }
3822 }
3823
3824 /* Ok no matching timings, maybe there's a free one? */
3825 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3826 pll = &dev_priv->shared_dplls[i];
3827 if (pll->refcount == 0) {
3828 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3829 crtc->base.base.id, pll->name);
3830 goto found;
3831 }
3832 }
3833
3834 return NULL;
3835
3836 found:
3837 if (pll->refcount == 0)
3838 pll->hw_state = crtc->config.dpll_hw_state;
3839
3840 crtc->config.shared_dpll = i;
3841 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3842 pipe_name(crtc->pipe));
3843
3844 pll->refcount++;
3845
3846 return pll;
3847 }
3848
3849 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3850 {
3851 struct drm_i915_private *dev_priv = dev->dev_private;
3852 int dslreg = PIPEDSL(pipe);
3853 u32 temp;
3854
3855 temp = I915_READ(dslreg);
3856 udelay(500);
3857 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3858 if (wait_for(I915_READ(dslreg) != temp, 5))
3859 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3860 }
3861 }
3862
3863 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3864 {
3865 struct drm_device *dev = crtc->base.dev;
3866 struct drm_i915_private *dev_priv = dev->dev_private;
3867 int pipe = crtc->pipe;
3868
3869 if (crtc->config.pch_pfit.enabled) {
3870 /* Force use of hard-coded filter coefficients
3871 * as some pre-programmed values are broken,
3872 * e.g. x201.
3873 */
3874 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3875 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3876 PF_PIPE_SEL_IVB(pipe));
3877 else
3878 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3879 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3880 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3881 }
3882 }
3883
3884 static void intel_enable_planes(struct drm_crtc *crtc)
3885 {
3886 struct drm_device *dev = crtc->dev;
3887 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3888 struct drm_plane *plane;
3889 struct intel_plane *intel_plane;
3890
3891 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3892 intel_plane = to_intel_plane(plane);
3893 if (intel_plane->pipe == pipe)
3894 intel_plane_restore(&intel_plane->base);
3895 }
3896 }
3897
3898 static void intel_disable_planes(struct drm_crtc *crtc)
3899 {
3900 struct drm_device *dev = crtc->dev;
3901 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3902 struct drm_plane *plane;
3903 struct intel_plane *intel_plane;
3904
3905 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3906 intel_plane = to_intel_plane(plane);
3907 if (intel_plane->pipe == pipe)
3908 intel_plane_disable(&intel_plane->base);
3909 }
3910 }
3911
3912 void hsw_enable_ips(struct intel_crtc *crtc)
3913 {
3914 struct drm_device *dev = crtc->base.dev;
3915 struct drm_i915_private *dev_priv = dev->dev_private;
3916
3917 if (!crtc->config.ips_enabled)
3918 return;
3919
3920 /* We can only enable IPS after we enable a plane and wait for a vblank */
3921 intel_wait_for_vblank(dev, crtc->pipe);
3922
3923 assert_plane_enabled(dev_priv, crtc->plane);
3924 if (IS_BROADWELL(dev)) {
3925 mutex_lock(&dev_priv->rps.hw_lock);
3926 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3927 mutex_unlock(&dev_priv->rps.hw_lock);
3928 /* Quoting Art Runyan: "its not safe to expect any particular
3929 * value in IPS_CTL bit 31 after enabling IPS through the
3930 * mailbox." Moreover, the mailbox may return a bogus state,
3931 * so we need to just enable it and continue on.
3932 */
3933 } else {
3934 I915_WRITE(IPS_CTL, IPS_ENABLE);
3935 /* The bit only becomes 1 in the next vblank, so this wait here
3936 * is essentially intel_wait_for_vblank. If we don't have this
3937 * and don't wait for vblanks until the end of crtc_enable, then
3938 * the HW state readout code will complain that the expected
3939 * IPS_CTL value is not the one we read. */
3940 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3941 DRM_ERROR("Timed out waiting for IPS enable\n");
3942 }
3943 }
3944
3945 void hsw_disable_ips(struct intel_crtc *crtc)
3946 {
3947 struct drm_device *dev = crtc->base.dev;
3948 struct drm_i915_private *dev_priv = dev->dev_private;
3949
3950 if (!crtc->config.ips_enabled)
3951 return;
3952
3953 assert_plane_enabled(dev_priv, crtc->plane);
3954 if (IS_BROADWELL(dev)) {
3955 mutex_lock(&dev_priv->rps.hw_lock);
3956 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3957 mutex_unlock(&dev_priv->rps.hw_lock);
3958 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3959 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3960 DRM_ERROR("Timed out waiting for IPS disable\n");
3961 } else {
3962 I915_WRITE(IPS_CTL, 0);
3963 POSTING_READ(IPS_CTL);
3964 }
3965
3966 /* We need to wait for a vblank before we can disable the plane. */
3967 intel_wait_for_vblank(dev, crtc->pipe);
3968 }
3969
3970 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3971 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3972 {
3973 struct drm_device *dev = crtc->dev;
3974 struct drm_i915_private *dev_priv = dev->dev_private;
3975 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3976 enum pipe pipe = intel_crtc->pipe;
3977 int palreg = PALETTE(pipe);
3978 int i;
3979 bool reenable_ips = false;
3980
3981 /* The clocks have to be on to load the palette. */
3982 if (!crtc->enabled || !intel_crtc->active)
3983 return;
3984
3985 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3986 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3987 assert_dsi_pll_enabled(dev_priv);
3988 else
3989 assert_pll_enabled(dev_priv, pipe);
3990 }
3991
3992 /* use legacy palette for Ironlake */
3993 if (!HAS_GMCH_DISPLAY(dev))
3994 palreg = LGC_PALETTE(pipe);
3995
3996 /* Workaround : Do not read or write the pipe palette/gamma data while
3997 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3998 */
3999 if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
4000 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4001 GAMMA_MODE_MODE_SPLIT)) {
4002 hsw_disable_ips(intel_crtc);
4003 reenable_ips = true;
4004 }
4005
4006 for (i = 0; i < 256; i++) {
4007 I915_WRITE(palreg + 4 * i,
4008 (intel_crtc->lut_r[i] << 16) |
4009 (intel_crtc->lut_g[i] << 8) |
4010 intel_crtc->lut_b[i]);
4011 }
4012
4013 if (reenable_ips)
4014 hsw_enable_ips(intel_crtc);
4015 }
4016
4017 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4018 {
4019 if (!enable && intel_crtc->overlay) {
4020 struct drm_device *dev = intel_crtc->base.dev;
4021 struct drm_i915_private *dev_priv = dev->dev_private;
4022
4023 mutex_lock(&dev->struct_mutex);
4024 dev_priv->mm.interruptible = false;
4025 (void) intel_overlay_switch_off(intel_crtc->overlay);
4026 dev_priv->mm.interruptible = true;
4027 mutex_unlock(&dev->struct_mutex);
4028 }
4029
4030 /* Let userspace switch the overlay on again. In most cases userspace
4031 * has to recompute where to put it anyway.
4032 */
4033 }
4034
4035 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4036 {
4037 struct drm_device *dev = crtc->dev;
4038 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4039 int pipe = intel_crtc->pipe;
4040
4041 assert_vblank_disabled(crtc);
4042
4043 drm_vblank_on(dev, pipe);
4044
4045 intel_enable_primary_hw_plane(crtc->primary, crtc);
4046 intel_enable_planes(crtc);
4047 intel_crtc_update_cursor(crtc, true);
4048 intel_crtc_dpms_overlay(intel_crtc, true);
4049
4050 hsw_enable_ips(intel_crtc);
4051
4052 mutex_lock(&dev->struct_mutex);
4053 intel_update_fbc(dev);
4054 mutex_unlock(&dev->struct_mutex);
4055
4056 /*
4057 * FIXME: Once we grow proper nuclear flip support out of this we need
4058 * to compute the mask of flip planes precisely. For the time being
4059 * consider this a flip from a NULL plane.
4060 */
4061 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4062 }
4063
4064 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4065 {
4066 struct drm_device *dev = crtc->dev;
4067 struct drm_i915_private *dev_priv = dev->dev_private;
4068 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4069 int pipe = intel_crtc->pipe;
4070 int plane = intel_crtc->plane;
4071
4072 intel_crtc_wait_for_pending_flips(crtc);
4073
4074 if (dev_priv->fbc.plane == plane)
4075 intel_disable_fbc(dev);
4076
4077 hsw_disable_ips(intel_crtc);
4078
4079 intel_crtc_dpms_overlay(intel_crtc, false);
4080 intel_crtc_update_cursor(crtc, false);
4081 intel_disable_planes(crtc);
4082 intel_disable_primary_hw_plane(crtc->primary, crtc);
4083
4084 /*
4085 * FIXME: Once we grow proper nuclear flip support out of this we need
4086 * to compute the mask of flip planes precisely. For the time being
4087 * consider this a flip to a NULL plane.
4088 */
4089 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4090
4091 drm_vblank_off(dev, pipe);
4092
4093 assert_vblank_disabled(crtc);
4094 }
4095
4096 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4097 {
4098 struct drm_device *dev = crtc->dev;
4099 struct drm_i915_private *dev_priv = dev->dev_private;
4100 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4101 struct intel_encoder *encoder;
4102 int pipe = intel_crtc->pipe;
4103
4104 WARN_ON(!crtc->enabled);
4105
4106 if (intel_crtc->active)
4107 return;
4108
4109 if (intel_crtc->config.has_pch_encoder)
4110 intel_prepare_shared_dpll(intel_crtc);
4111
4112 if (intel_crtc->config.has_dp_encoder)
4113 intel_dp_set_m_n(intel_crtc);
4114
4115 intel_set_pipe_timings(intel_crtc);
4116
4117 if (intel_crtc->config.has_pch_encoder) {
4118 intel_cpu_transcoder_set_m_n(intel_crtc,
4119 &intel_crtc->config.fdi_m_n, NULL);
4120 }
4121
4122 ironlake_set_pipeconf(crtc);
4123
4124 intel_crtc->active = true;
4125
4126 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4127 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4128
4129 for_each_encoder_on_crtc(dev, crtc, encoder)
4130 if (encoder->pre_enable)
4131 encoder->pre_enable(encoder);
4132
4133 if (intel_crtc->config.has_pch_encoder) {
4134 /* Note: FDI PLL enabling _must_ be done before we enable the
4135 * cpu pipes, hence this is separate from all the other fdi/pch
4136 * enabling. */
4137 ironlake_fdi_pll_enable(intel_crtc);
4138 } else {
4139 assert_fdi_tx_disabled(dev_priv, pipe);
4140 assert_fdi_rx_disabled(dev_priv, pipe);
4141 }
4142
4143 ironlake_pfit_enable(intel_crtc);
4144
4145 /*
4146 * On ILK+ LUT must be loaded before the pipe is running but with
4147 * clocks enabled
4148 */
4149 intel_crtc_load_lut(crtc);
4150
4151 intel_update_watermarks(crtc);
4152 intel_enable_pipe(intel_crtc);
4153
4154 if (intel_crtc->config.has_pch_encoder)
4155 ironlake_pch_enable(crtc);
4156
4157 for_each_encoder_on_crtc(dev, crtc, encoder)
4158 encoder->enable(encoder);
4159
4160 if (HAS_PCH_CPT(dev))
4161 cpt_verify_modeset(dev, intel_crtc->pipe);
4162
4163 intel_crtc_enable_planes(crtc);
4164 }
4165
4166 /* IPS only exists on ULT machines and is tied to pipe A. */
4167 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4168 {
4169 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4170 }
4171
4172 /*
4173 * This implements the workaround described in the "notes" section of the mode
4174 * set sequence documentation. When going from no pipes or single pipe to
4175 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4176 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4177 */
4178 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4179 {
4180 struct drm_device *dev = crtc->base.dev;
4181 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4182
4183 /* We want to get the other_active_crtc only if there's only 1 other
4184 * active crtc. */
4185 for_each_intel_crtc(dev, crtc_it) {
4186 if (!crtc_it->active || crtc_it == crtc)
4187 continue;
4188
4189 if (other_active_crtc)
4190 return;
4191
4192 other_active_crtc = crtc_it;
4193 }
4194 if (!other_active_crtc)
4195 return;
4196
4197 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4198 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4199 }
4200
4201 static void haswell_crtc_enable(struct drm_crtc *crtc)
4202 {
4203 struct drm_device *dev = crtc->dev;
4204 struct drm_i915_private *dev_priv = dev->dev_private;
4205 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4206 struct intel_encoder *encoder;
4207 int pipe = intel_crtc->pipe;
4208
4209 WARN_ON(!crtc->enabled);
4210
4211 if (intel_crtc->active)
4212 return;
4213
4214 if (intel_crtc_to_shared_dpll(intel_crtc))
4215 intel_enable_shared_dpll(intel_crtc);
4216
4217 if (intel_crtc->config.has_dp_encoder)
4218 intel_dp_set_m_n(intel_crtc);
4219
4220 intel_set_pipe_timings(intel_crtc);
4221
4222 if (intel_crtc->config.cpu_transcoder != TRANSCODER_EDP) {
4223 I915_WRITE(PIPE_MULT(intel_crtc->config.cpu_transcoder),
4224 intel_crtc->config.pixel_multiplier - 1);
4225 }
4226
4227 if (intel_crtc->config.has_pch_encoder) {
4228 intel_cpu_transcoder_set_m_n(intel_crtc,
4229 &intel_crtc->config.fdi_m_n, NULL);
4230 }
4231
4232 haswell_set_pipeconf(crtc);
4233
4234 intel_set_pipe_csc(crtc);
4235
4236 intel_crtc->active = true;
4237
4238 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4239 for_each_encoder_on_crtc(dev, crtc, encoder)
4240 if (encoder->pre_enable)
4241 encoder->pre_enable(encoder);
4242
4243 if (intel_crtc->config.has_pch_encoder) {
4244 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4245 dev_priv->display.fdi_link_train(crtc);
4246 }
4247
4248 intel_ddi_enable_pipe_clock(intel_crtc);
4249
4250 ironlake_pfit_enable(intel_crtc);
4251
4252 /*
4253 * On ILK+ LUT must be loaded before the pipe is running but with
4254 * clocks enabled
4255 */
4256 intel_crtc_load_lut(crtc);
4257
4258 intel_ddi_set_pipe_settings(crtc);
4259 intel_ddi_enable_transcoder_func(crtc);
4260
4261 intel_update_watermarks(crtc);
4262 intel_enable_pipe(intel_crtc);
4263
4264 if (intel_crtc->config.has_pch_encoder)
4265 lpt_pch_enable(crtc);
4266
4267 if (intel_crtc->config.dp_encoder_is_mst)
4268 intel_ddi_set_vc_payload_alloc(crtc, true);
4269
4270 for_each_encoder_on_crtc(dev, crtc, encoder) {
4271 encoder->enable(encoder);
4272 intel_opregion_notify_encoder(encoder, true);
4273 }
4274
4275 /* If we change the relative order between pipe/planes enabling, we need
4276 * to change the workaround. */
4277 haswell_mode_set_planes_workaround(intel_crtc);
4278 intel_crtc_enable_planes(crtc);
4279 }
4280
4281 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4282 {
4283 struct drm_device *dev = crtc->base.dev;
4284 struct drm_i915_private *dev_priv = dev->dev_private;
4285 int pipe = crtc->pipe;
4286
4287 /* To avoid upsetting the power well on haswell only disable the pfit if
4288 * it's in use. The hw state code will make sure we get this right. */
4289 if (crtc->config.pch_pfit.enabled) {
4290 I915_WRITE(PF_CTL(pipe), 0);
4291 I915_WRITE(PF_WIN_POS(pipe), 0);
4292 I915_WRITE(PF_WIN_SZ(pipe), 0);
4293 }
4294 }
4295
4296 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4297 {
4298 struct drm_device *dev = crtc->dev;
4299 struct drm_i915_private *dev_priv = dev->dev_private;
4300 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4301 struct intel_encoder *encoder;
4302 int pipe = intel_crtc->pipe;
4303 u32 reg, temp;
4304
4305 if (!intel_crtc->active)
4306 return;
4307
4308 intel_crtc_disable_planes(crtc);
4309
4310 for_each_encoder_on_crtc(dev, crtc, encoder)
4311 encoder->disable(encoder);
4312
4313 if (intel_crtc->config.has_pch_encoder)
4314 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
4315
4316 intel_disable_pipe(intel_crtc);
4317
4318 ironlake_pfit_disable(intel_crtc);
4319
4320 for_each_encoder_on_crtc(dev, crtc, encoder)
4321 if (encoder->post_disable)
4322 encoder->post_disable(encoder);
4323
4324 if (intel_crtc->config.has_pch_encoder) {
4325 ironlake_fdi_disable(crtc);
4326
4327 ironlake_disable_pch_transcoder(dev_priv, pipe);
4328 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4329
4330 if (HAS_PCH_CPT(dev)) {
4331 /* disable TRANS_DP_CTL */
4332 reg = TRANS_DP_CTL(pipe);
4333 temp = I915_READ(reg);
4334 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4335 TRANS_DP_PORT_SEL_MASK);
4336 temp |= TRANS_DP_PORT_SEL_NONE;
4337 I915_WRITE(reg, temp);
4338
4339 /* disable DPLL_SEL */
4340 temp = I915_READ(PCH_DPLL_SEL);
4341 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4342 I915_WRITE(PCH_DPLL_SEL, temp);
4343 }
4344
4345 /* disable PCH DPLL */
4346 intel_disable_shared_dpll(intel_crtc);
4347
4348 ironlake_fdi_pll_disable(intel_crtc);
4349 }
4350
4351 intel_crtc->active = false;
4352 intel_update_watermarks(crtc);
4353
4354 mutex_lock(&dev->struct_mutex);
4355 intel_update_fbc(dev);
4356 mutex_unlock(&dev->struct_mutex);
4357 }
4358
4359 static void haswell_crtc_disable(struct drm_crtc *crtc)
4360 {
4361 struct drm_device *dev = crtc->dev;
4362 struct drm_i915_private *dev_priv = dev->dev_private;
4363 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4364 struct intel_encoder *encoder;
4365 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4366
4367 if (!intel_crtc->active)
4368 return;
4369
4370 intel_crtc_disable_planes(crtc);
4371
4372 for_each_encoder_on_crtc(dev, crtc, encoder) {
4373 intel_opregion_notify_encoder(encoder, false);
4374 encoder->disable(encoder);
4375 }
4376
4377 if (intel_crtc->config.has_pch_encoder)
4378 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4379 intel_disable_pipe(intel_crtc);
4380
4381 if (intel_crtc->config.dp_encoder_is_mst)
4382 intel_ddi_set_vc_payload_alloc(crtc, false);
4383
4384 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4385
4386 ironlake_pfit_disable(intel_crtc);
4387
4388 intel_ddi_disable_pipe_clock(intel_crtc);
4389
4390 if (intel_crtc->config.has_pch_encoder) {
4391 lpt_disable_pch_transcoder(dev_priv);
4392 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4393 intel_ddi_fdi_disable(crtc);
4394 }
4395
4396 for_each_encoder_on_crtc(dev, crtc, encoder)
4397 if (encoder->post_disable)
4398 encoder->post_disable(encoder);
4399
4400 intel_crtc->active = false;
4401 intel_update_watermarks(crtc);
4402
4403 mutex_lock(&dev->struct_mutex);
4404 intel_update_fbc(dev);
4405 mutex_unlock(&dev->struct_mutex);
4406
4407 if (intel_crtc_to_shared_dpll(intel_crtc))
4408 intel_disable_shared_dpll(intel_crtc);
4409 }
4410
4411 static void ironlake_crtc_off(struct drm_crtc *crtc)
4412 {
4413 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4414 intel_put_shared_dpll(intel_crtc);
4415 }
4416
4417
4418 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4419 {
4420 struct drm_device *dev = crtc->base.dev;
4421 struct drm_i915_private *dev_priv = dev->dev_private;
4422 struct intel_crtc_config *pipe_config = &crtc->config;
4423
4424 if (!crtc->config.gmch_pfit.control)
4425 return;
4426
4427 /*
4428 * The panel fitter should only be adjusted whilst the pipe is disabled,
4429 * according to register description and PRM.
4430 */
4431 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4432 assert_pipe_disabled(dev_priv, crtc->pipe);
4433
4434 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4435 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4436
4437 /* Border color in case we don't scale up to the full screen. Black by
4438 * default, change to something else for debugging. */
4439 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4440 }
4441
4442 static enum intel_display_power_domain port_to_power_domain(enum port port)
4443 {
4444 switch (port) {
4445 case PORT_A:
4446 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4447 case PORT_B:
4448 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4449 case PORT_C:
4450 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4451 case PORT_D:
4452 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4453 default:
4454 WARN_ON_ONCE(1);
4455 return POWER_DOMAIN_PORT_OTHER;
4456 }
4457 }
4458
4459 #define for_each_power_domain(domain, mask) \
4460 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4461 if ((1 << (domain)) & (mask))
4462
4463 enum intel_display_power_domain
4464 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4465 {
4466 struct drm_device *dev = intel_encoder->base.dev;
4467 struct intel_digital_port *intel_dig_port;
4468
4469 switch (intel_encoder->type) {
4470 case INTEL_OUTPUT_UNKNOWN:
4471 /* Only DDI platforms should ever use this output type */
4472 WARN_ON_ONCE(!HAS_DDI(dev));
4473 case INTEL_OUTPUT_DISPLAYPORT:
4474 case INTEL_OUTPUT_HDMI:
4475 case INTEL_OUTPUT_EDP:
4476 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4477 return port_to_power_domain(intel_dig_port->port);
4478 case INTEL_OUTPUT_DP_MST:
4479 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4480 return port_to_power_domain(intel_dig_port->port);
4481 case INTEL_OUTPUT_ANALOG:
4482 return POWER_DOMAIN_PORT_CRT;
4483 case INTEL_OUTPUT_DSI:
4484 return POWER_DOMAIN_PORT_DSI;
4485 default:
4486 return POWER_DOMAIN_PORT_OTHER;
4487 }
4488 }
4489
4490 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4491 {
4492 struct drm_device *dev = crtc->dev;
4493 struct intel_encoder *intel_encoder;
4494 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4495 enum pipe pipe = intel_crtc->pipe;
4496 unsigned long mask;
4497 enum transcoder transcoder;
4498
4499 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4500
4501 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4502 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4503 if (intel_crtc->config.pch_pfit.enabled ||
4504 intel_crtc->config.pch_pfit.force_thru)
4505 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4506
4507 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4508 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4509
4510 return mask;
4511 }
4512
4513 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4514 bool enable)
4515 {
4516 if (dev_priv->power_domains.init_power_on == enable)
4517 return;
4518
4519 if (enable)
4520 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4521 else
4522 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4523
4524 dev_priv->power_domains.init_power_on = enable;
4525 }
4526
4527 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4528 {
4529 struct drm_i915_private *dev_priv = dev->dev_private;
4530 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4531 struct intel_crtc *crtc;
4532
4533 /*
4534 * First get all needed power domains, then put all unneeded, to avoid
4535 * any unnecessary toggling of the power wells.
4536 */
4537 for_each_intel_crtc(dev, crtc) {
4538 enum intel_display_power_domain domain;
4539
4540 if (!crtc->base.enabled)
4541 continue;
4542
4543 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4544
4545 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4546 intel_display_power_get(dev_priv, domain);
4547 }
4548
4549 for_each_intel_crtc(dev, crtc) {
4550 enum intel_display_power_domain domain;
4551
4552 for_each_power_domain(domain, crtc->enabled_power_domains)
4553 intel_display_power_put(dev_priv, domain);
4554
4555 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4556 }
4557
4558 intel_display_set_init_power(dev_priv, false);
4559 }
4560
4561 /* returns HPLL frequency in kHz */
4562 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4563 {
4564 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4565
4566 /* Obtain SKU information */
4567 mutex_lock(&dev_priv->dpio_lock);
4568 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4569 CCK_FUSE_HPLL_FREQ_MASK;
4570 mutex_unlock(&dev_priv->dpio_lock);
4571
4572 return vco_freq[hpll_freq] * 1000;
4573 }
4574
4575 static void vlv_update_cdclk(struct drm_device *dev)
4576 {
4577 struct drm_i915_private *dev_priv = dev->dev_private;
4578
4579 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4580 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz",
4581 dev_priv->vlv_cdclk_freq);
4582
4583 /*
4584 * Program the gmbus_freq based on the cdclk frequency.
4585 * BSpec erroneously claims we should aim for 4MHz, but
4586 * in fact 1MHz is the correct frequency.
4587 */
4588 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
4589 }
4590
4591 /* Adjust CDclk dividers to allow high res or save power if possible */
4592 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4593 {
4594 struct drm_i915_private *dev_priv = dev->dev_private;
4595 u32 val, cmd;
4596
4597 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4598
4599 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4600 cmd = 2;
4601 else if (cdclk == 266667)
4602 cmd = 1;
4603 else
4604 cmd = 0;
4605
4606 mutex_lock(&dev_priv->rps.hw_lock);
4607 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4608 val &= ~DSPFREQGUAR_MASK;
4609 val |= (cmd << DSPFREQGUAR_SHIFT);
4610 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4611 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4612 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4613 50)) {
4614 DRM_ERROR("timed out waiting for CDclk change\n");
4615 }
4616 mutex_unlock(&dev_priv->rps.hw_lock);
4617
4618 if (cdclk == 400000) {
4619 u32 divider, vco;
4620
4621 vco = valleyview_get_vco(dev_priv);
4622 divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1;
4623
4624 mutex_lock(&dev_priv->dpio_lock);
4625 /* adjust cdclk divider */
4626 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4627 val &= ~DISPLAY_FREQUENCY_VALUES;
4628 val |= divider;
4629 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4630
4631 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4632 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4633 50))
4634 DRM_ERROR("timed out waiting for CDclk change\n");
4635 mutex_unlock(&dev_priv->dpio_lock);
4636 }
4637
4638 mutex_lock(&dev_priv->dpio_lock);
4639 /* adjust self-refresh exit latency value */
4640 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4641 val &= ~0x7f;
4642
4643 /*
4644 * For high bandwidth configs, we set a higher latency in the bunit
4645 * so that the core display fetch happens in time to avoid underruns.
4646 */
4647 if (cdclk == 400000)
4648 val |= 4500 / 250; /* 4.5 usec */
4649 else
4650 val |= 3000 / 250; /* 3.0 usec */
4651 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4652 mutex_unlock(&dev_priv->dpio_lock);
4653
4654 vlv_update_cdclk(dev);
4655 }
4656
4657 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4658 {
4659 struct drm_i915_private *dev_priv = dev->dev_private;
4660 u32 val, cmd;
4661
4662 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4663
4664 switch (cdclk) {
4665 case 400000:
4666 cmd = 3;
4667 break;
4668 case 333333:
4669 case 320000:
4670 cmd = 2;
4671 break;
4672 case 266667:
4673 cmd = 1;
4674 break;
4675 case 200000:
4676 cmd = 0;
4677 break;
4678 default:
4679 WARN_ON(1);
4680 return;
4681 }
4682
4683 mutex_lock(&dev_priv->rps.hw_lock);
4684 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4685 val &= ~DSPFREQGUAR_MASK_CHV;
4686 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4687 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4688 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4689 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4690 50)) {
4691 DRM_ERROR("timed out waiting for CDclk change\n");
4692 }
4693 mutex_unlock(&dev_priv->rps.hw_lock);
4694
4695 vlv_update_cdclk(dev);
4696 }
4697
4698 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4699 int max_pixclk)
4700 {
4701 int vco = valleyview_get_vco(dev_priv);
4702 int freq_320 = (vco << 1) % 320000 != 0 ? 333333 : 320000;
4703
4704 /* FIXME: Punit isn't quite ready yet */
4705 if (IS_CHERRYVIEW(dev_priv->dev))
4706 return 400000;
4707
4708 /*
4709 * Really only a few cases to deal with, as only 4 CDclks are supported:
4710 * 200MHz
4711 * 267MHz
4712 * 320/333MHz (depends on HPLL freq)
4713 * 400MHz
4714 * So we check to see whether we're above 90% of the lower bin and
4715 * adjust if needed.
4716 *
4717 * We seem to get an unstable or solid color picture at 200MHz.
4718 * Not sure what's wrong. For now use 200MHz only when all pipes
4719 * are off.
4720 */
4721 if (max_pixclk > freq_320*9/10)
4722 return 400000;
4723 else if (max_pixclk > 266667*9/10)
4724 return freq_320;
4725 else if (max_pixclk > 0)
4726 return 266667;
4727 else
4728 return 200000;
4729 }
4730
4731 /* compute the max pixel clock for new configuration */
4732 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4733 {
4734 struct drm_device *dev = dev_priv->dev;
4735 struct intel_crtc *intel_crtc;
4736 int max_pixclk = 0;
4737
4738 for_each_intel_crtc(dev, intel_crtc) {
4739 if (intel_crtc->new_enabled)
4740 max_pixclk = max(max_pixclk,
4741 intel_crtc->new_config->adjusted_mode.crtc_clock);
4742 }
4743
4744 return max_pixclk;
4745 }
4746
4747 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4748 unsigned *prepare_pipes)
4749 {
4750 struct drm_i915_private *dev_priv = dev->dev_private;
4751 struct intel_crtc *intel_crtc;
4752 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4753
4754 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4755 dev_priv->vlv_cdclk_freq)
4756 return;
4757
4758 /* disable/enable all currently active pipes while we change cdclk */
4759 for_each_intel_crtc(dev, intel_crtc)
4760 if (intel_crtc->base.enabled)
4761 *prepare_pipes |= (1 << intel_crtc->pipe);
4762 }
4763
4764 static void valleyview_modeset_global_resources(struct drm_device *dev)
4765 {
4766 struct drm_i915_private *dev_priv = dev->dev_private;
4767 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4768 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4769
4770 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
4771 if (IS_CHERRYVIEW(dev))
4772 cherryview_set_cdclk(dev, req_cdclk);
4773 else
4774 valleyview_set_cdclk(dev, req_cdclk);
4775 }
4776
4777 modeset_update_crtc_power_domains(dev);
4778 }
4779
4780 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4781 {
4782 struct drm_device *dev = crtc->dev;
4783 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4784 struct intel_encoder *encoder;
4785 int pipe = intel_crtc->pipe;
4786 bool is_dsi;
4787
4788 WARN_ON(!crtc->enabled);
4789
4790 if (intel_crtc->active)
4791 return;
4792
4793 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4794
4795 if (!is_dsi) {
4796 if (IS_CHERRYVIEW(dev))
4797 chv_prepare_pll(intel_crtc);
4798 else
4799 vlv_prepare_pll(intel_crtc);
4800 }
4801
4802 if (intel_crtc->config.has_dp_encoder)
4803 intel_dp_set_m_n(intel_crtc);
4804
4805 intel_set_pipe_timings(intel_crtc);
4806
4807 i9xx_set_pipeconf(intel_crtc);
4808
4809 intel_crtc->active = true;
4810
4811 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4812
4813 for_each_encoder_on_crtc(dev, crtc, encoder)
4814 if (encoder->pre_pll_enable)
4815 encoder->pre_pll_enable(encoder);
4816
4817 if (!is_dsi) {
4818 if (IS_CHERRYVIEW(dev))
4819 chv_enable_pll(intel_crtc);
4820 else
4821 vlv_enable_pll(intel_crtc);
4822 }
4823
4824 for_each_encoder_on_crtc(dev, crtc, encoder)
4825 if (encoder->pre_enable)
4826 encoder->pre_enable(encoder);
4827
4828 i9xx_pfit_enable(intel_crtc);
4829
4830 intel_crtc_load_lut(crtc);
4831
4832 intel_update_watermarks(crtc);
4833 intel_enable_pipe(intel_crtc);
4834
4835 for_each_encoder_on_crtc(dev, crtc, encoder)
4836 encoder->enable(encoder);
4837
4838 intel_crtc_enable_planes(crtc);
4839
4840 /* Underruns don't raise interrupts, so check manually. */
4841 i9xx_check_fifo_underruns(dev);
4842 }
4843
4844 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4845 {
4846 struct drm_device *dev = crtc->base.dev;
4847 struct drm_i915_private *dev_priv = dev->dev_private;
4848
4849 I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4850 I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4851 }
4852
4853 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4854 {
4855 struct drm_device *dev = crtc->dev;
4856 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4857 struct intel_encoder *encoder;
4858 int pipe = intel_crtc->pipe;
4859
4860 WARN_ON(!crtc->enabled);
4861
4862 if (intel_crtc->active)
4863 return;
4864
4865 i9xx_set_pll_dividers(intel_crtc);
4866
4867 if (intel_crtc->config.has_dp_encoder)
4868 intel_dp_set_m_n(intel_crtc);
4869
4870 intel_set_pipe_timings(intel_crtc);
4871
4872 i9xx_set_pipeconf(intel_crtc);
4873
4874 intel_crtc->active = true;
4875
4876 if (!IS_GEN2(dev))
4877 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4878
4879 for_each_encoder_on_crtc(dev, crtc, encoder)
4880 if (encoder->pre_enable)
4881 encoder->pre_enable(encoder);
4882
4883 i9xx_enable_pll(intel_crtc);
4884
4885 i9xx_pfit_enable(intel_crtc);
4886
4887 intel_crtc_load_lut(crtc);
4888
4889 intel_update_watermarks(crtc);
4890 intel_enable_pipe(intel_crtc);
4891
4892 for_each_encoder_on_crtc(dev, crtc, encoder)
4893 encoder->enable(encoder);
4894
4895 intel_crtc_enable_planes(crtc);
4896
4897 /*
4898 * Gen2 reports pipe underruns whenever all planes are disabled.
4899 * So don't enable underrun reporting before at least some planes
4900 * are enabled.
4901 * FIXME: Need to fix the logic to work when we turn off all planes
4902 * but leave the pipe running.
4903 */
4904 if (IS_GEN2(dev))
4905 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4906
4907 /* Underruns don't raise interrupts, so check manually. */
4908 i9xx_check_fifo_underruns(dev);
4909 }
4910
4911 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4912 {
4913 struct drm_device *dev = crtc->base.dev;
4914 struct drm_i915_private *dev_priv = dev->dev_private;
4915
4916 if (!crtc->config.gmch_pfit.control)
4917 return;
4918
4919 assert_pipe_disabled(dev_priv, crtc->pipe);
4920
4921 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4922 I915_READ(PFIT_CONTROL));
4923 I915_WRITE(PFIT_CONTROL, 0);
4924 }
4925
4926 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4927 {
4928 struct drm_device *dev = crtc->dev;
4929 struct drm_i915_private *dev_priv = dev->dev_private;
4930 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4931 struct intel_encoder *encoder;
4932 int pipe = intel_crtc->pipe;
4933
4934 if (!intel_crtc->active)
4935 return;
4936
4937 /*
4938 * Gen2 reports pipe underruns whenever all planes are disabled.
4939 * So diasble underrun reporting before all the planes get disabled.
4940 * FIXME: Need to fix the logic to work when we turn off all planes
4941 * but leave the pipe running.
4942 */
4943 if (IS_GEN2(dev))
4944 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4945
4946 /*
4947 * Vblank time updates from the shadow to live plane control register
4948 * are blocked if the memory self-refresh mode is active at that
4949 * moment. So to make sure the plane gets truly disabled, disable
4950 * first the self-refresh mode. The self-refresh enable bit in turn
4951 * will be checked/applied by the HW only at the next frame start
4952 * event which is after the vblank start event, so we need to have a
4953 * wait-for-vblank between disabling the plane and the pipe.
4954 */
4955 intel_set_memory_cxsr(dev_priv, false);
4956 intel_crtc_disable_planes(crtc);
4957
4958 for_each_encoder_on_crtc(dev, crtc, encoder)
4959 encoder->disable(encoder);
4960
4961 /*
4962 * On gen2 planes are double buffered but the pipe isn't, so we must
4963 * wait for planes to fully turn off before disabling the pipe.
4964 * We also need to wait on all gmch platforms because of the
4965 * self-refresh mode constraint explained above.
4966 */
4967 intel_wait_for_vblank(dev, pipe);
4968
4969 intel_disable_pipe(intel_crtc);
4970
4971 i9xx_pfit_disable(intel_crtc);
4972
4973 for_each_encoder_on_crtc(dev, crtc, encoder)
4974 if (encoder->post_disable)
4975 encoder->post_disable(encoder);
4976
4977 if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
4978 if (IS_CHERRYVIEW(dev))
4979 chv_disable_pll(dev_priv, pipe);
4980 else if (IS_VALLEYVIEW(dev))
4981 vlv_disable_pll(dev_priv, pipe);
4982 else
4983 i9xx_disable_pll(intel_crtc);
4984 }
4985
4986 if (!IS_GEN2(dev))
4987 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4988
4989 intel_crtc->active = false;
4990 intel_update_watermarks(crtc);
4991
4992 mutex_lock(&dev->struct_mutex);
4993 intel_update_fbc(dev);
4994 mutex_unlock(&dev->struct_mutex);
4995 }
4996
4997 static void i9xx_crtc_off(struct drm_crtc *crtc)
4998 {
4999 }
5000
5001 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
5002 bool enabled)
5003 {
5004 struct drm_device *dev = crtc->dev;
5005 struct drm_i915_master_private *master_priv;
5006 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5007 int pipe = intel_crtc->pipe;
5008
5009 if (!dev->primary->master)
5010 return;
5011
5012 master_priv = dev->primary->master->driver_priv;
5013 if (!master_priv->sarea_priv)
5014 return;
5015
5016 switch (pipe) {
5017 case 0:
5018 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
5019 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
5020 break;
5021 case 1:
5022 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
5023 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
5024 break;
5025 default:
5026 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
5027 break;
5028 }
5029 }
5030
5031 /* Master function to enable/disable CRTC and corresponding power wells */
5032 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5033 {
5034 struct drm_device *dev = crtc->dev;
5035 struct drm_i915_private *dev_priv = dev->dev_private;
5036 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5037 enum intel_display_power_domain domain;
5038 unsigned long domains;
5039
5040 if (enable) {
5041 if (!intel_crtc->active) {
5042 domains = get_crtc_power_domains(crtc);
5043 for_each_power_domain(domain, domains)
5044 intel_display_power_get(dev_priv, domain);
5045 intel_crtc->enabled_power_domains = domains;
5046
5047 dev_priv->display.crtc_enable(crtc);
5048 }
5049 } else {
5050 if (intel_crtc->active) {
5051 dev_priv->display.crtc_disable(crtc);
5052
5053 domains = intel_crtc->enabled_power_domains;
5054 for_each_power_domain(domain, domains)
5055 intel_display_power_put(dev_priv, domain);
5056 intel_crtc->enabled_power_domains = 0;
5057 }
5058 }
5059 }
5060
5061 /**
5062 * Sets the power management mode of the pipe and plane.
5063 */
5064 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5065 {
5066 struct drm_device *dev = crtc->dev;
5067 struct intel_encoder *intel_encoder;
5068 bool enable = false;
5069
5070 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5071 enable |= intel_encoder->connectors_active;
5072
5073 intel_crtc_control(crtc, enable);
5074
5075 intel_crtc_update_sarea(crtc, enable);
5076 }
5077
5078 static void intel_crtc_disable(struct drm_crtc *crtc)
5079 {
5080 struct drm_device *dev = crtc->dev;
5081 struct drm_connector *connector;
5082 struct drm_i915_private *dev_priv = dev->dev_private;
5083 struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
5084 enum pipe pipe = to_intel_crtc(crtc)->pipe;
5085
5086 /* crtc should still be enabled when we disable it. */
5087 WARN_ON(!crtc->enabled);
5088
5089 dev_priv->display.crtc_disable(crtc);
5090 intel_crtc_update_sarea(crtc, false);
5091 dev_priv->display.off(crtc);
5092
5093 if (crtc->primary->fb) {
5094 mutex_lock(&dev->struct_mutex);
5095 intel_unpin_fb_obj(old_obj);
5096 i915_gem_track_fb(old_obj, NULL,
5097 INTEL_FRONTBUFFER_PRIMARY(pipe));
5098 mutex_unlock(&dev->struct_mutex);
5099 crtc->primary->fb = NULL;
5100 }
5101
5102 /* Update computed state. */
5103 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5104 if (!connector->encoder || !connector->encoder->crtc)
5105 continue;
5106
5107 if (connector->encoder->crtc != crtc)
5108 continue;
5109
5110 connector->dpms = DRM_MODE_DPMS_OFF;
5111 to_intel_encoder(connector->encoder)->connectors_active = false;
5112 }
5113 }
5114
5115 void intel_encoder_destroy(struct drm_encoder *encoder)
5116 {
5117 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5118
5119 drm_encoder_cleanup(encoder);
5120 kfree(intel_encoder);
5121 }
5122
5123 /* Simple dpms helper for encoders with just one connector, no cloning and only
5124 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5125 * state of the entire output pipe. */
5126 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5127 {
5128 if (mode == DRM_MODE_DPMS_ON) {
5129 encoder->connectors_active = true;
5130
5131 intel_crtc_update_dpms(encoder->base.crtc);
5132 } else {
5133 encoder->connectors_active = false;
5134
5135 intel_crtc_update_dpms(encoder->base.crtc);
5136 }
5137 }
5138
5139 /* Cross check the actual hw state with our own modeset state tracking (and it's
5140 * internal consistency). */
5141 static void intel_connector_check_state(struct intel_connector *connector)
5142 {
5143 if (connector->get_hw_state(connector)) {
5144 struct intel_encoder *encoder = connector->encoder;
5145 struct drm_crtc *crtc;
5146 bool encoder_enabled;
5147 enum pipe pipe;
5148
5149 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5150 connector->base.base.id,
5151 connector->base.name);
5152
5153 /* there is no real hw state for MST connectors */
5154 if (connector->mst_port)
5155 return;
5156
5157 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5158 "wrong connector dpms state\n");
5159 WARN(connector->base.encoder != &encoder->base,
5160 "active connector not linked to encoder\n");
5161
5162 if (encoder) {
5163 WARN(!encoder->connectors_active,
5164 "encoder->connectors_active not set\n");
5165
5166 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5167 WARN(!encoder_enabled, "encoder not enabled\n");
5168 if (WARN_ON(!encoder->base.crtc))
5169 return;
5170
5171 crtc = encoder->base.crtc;
5172
5173 WARN(!crtc->enabled, "crtc not enabled\n");
5174 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5175 WARN(pipe != to_intel_crtc(crtc)->pipe,
5176 "encoder active on the wrong pipe\n");
5177 }
5178 }
5179 }
5180
5181 /* Even simpler default implementation, if there's really no special case to
5182 * consider. */
5183 void intel_connector_dpms(struct drm_connector *connector, int mode)
5184 {
5185 /* All the simple cases only support two dpms states. */
5186 if (mode != DRM_MODE_DPMS_ON)
5187 mode = DRM_MODE_DPMS_OFF;
5188
5189 if (mode == connector->dpms)
5190 return;
5191
5192 connector->dpms = mode;
5193
5194 /* Only need to change hw state when actually enabled */
5195 if (connector->encoder)
5196 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5197
5198 intel_modeset_check_state(connector->dev);
5199 }
5200
5201 /* Simple connector->get_hw_state implementation for encoders that support only
5202 * one connector and no cloning and hence the encoder state determines the state
5203 * of the connector. */
5204 bool intel_connector_get_hw_state(struct intel_connector *connector)
5205 {
5206 enum pipe pipe = 0;
5207 struct intel_encoder *encoder = connector->encoder;
5208
5209 return encoder->get_hw_state(encoder, &pipe);
5210 }
5211
5212 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5213 struct intel_crtc_config *pipe_config)
5214 {
5215 struct drm_i915_private *dev_priv = dev->dev_private;
5216 struct intel_crtc *pipe_B_crtc =
5217 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5218
5219 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5220 pipe_name(pipe), pipe_config->fdi_lanes);
5221 if (pipe_config->fdi_lanes > 4) {
5222 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5223 pipe_name(pipe), pipe_config->fdi_lanes);
5224 return false;
5225 }
5226
5227 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5228 if (pipe_config->fdi_lanes > 2) {
5229 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5230 pipe_config->fdi_lanes);
5231 return false;
5232 } else {
5233 return true;
5234 }
5235 }
5236
5237 if (INTEL_INFO(dev)->num_pipes == 2)
5238 return true;
5239
5240 /* Ivybridge 3 pipe is really complicated */
5241 switch (pipe) {
5242 case PIPE_A:
5243 return true;
5244 case PIPE_B:
5245 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5246 pipe_config->fdi_lanes > 2) {
5247 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5248 pipe_name(pipe), pipe_config->fdi_lanes);
5249 return false;
5250 }
5251 return true;
5252 case PIPE_C:
5253 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5254 pipe_B_crtc->config.fdi_lanes <= 2) {
5255 if (pipe_config->fdi_lanes > 2) {
5256 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5257 pipe_name(pipe), pipe_config->fdi_lanes);
5258 return false;
5259 }
5260 } else {
5261 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5262 return false;
5263 }
5264 return true;
5265 default:
5266 BUG();
5267 }
5268 }
5269
5270 #define RETRY 1
5271 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5272 struct intel_crtc_config *pipe_config)
5273 {
5274 struct drm_device *dev = intel_crtc->base.dev;
5275 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5276 int lane, link_bw, fdi_dotclock;
5277 bool setup_ok, needs_recompute = false;
5278
5279 retry:
5280 /* FDI is a binary signal running at ~2.7GHz, encoding
5281 * each output octet as 10 bits. The actual frequency
5282 * is stored as a divider into a 100MHz clock, and the
5283 * mode pixel clock is stored in units of 1KHz.
5284 * Hence the bw of each lane in terms of the mode signal
5285 * is:
5286 */
5287 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5288
5289 fdi_dotclock = adjusted_mode->crtc_clock;
5290
5291 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5292 pipe_config->pipe_bpp);
5293
5294 pipe_config->fdi_lanes = lane;
5295
5296 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5297 link_bw, &pipe_config->fdi_m_n);
5298
5299 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5300 intel_crtc->pipe, pipe_config);
5301 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5302 pipe_config->pipe_bpp -= 2*3;
5303 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5304 pipe_config->pipe_bpp);
5305 needs_recompute = true;
5306 pipe_config->bw_constrained = true;
5307
5308 goto retry;
5309 }
5310
5311 if (needs_recompute)
5312 return RETRY;
5313
5314 return setup_ok ? 0 : -EINVAL;
5315 }
5316
5317 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5318 struct intel_crtc_config *pipe_config)
5319 {
5320 pipe_config->ips_enabled = i915.enable_ips &&
5321 hsw_crtc_supports_ips(crtc) &&
5322 pipe_config->pipe_bpp <= 24;
5323 }
5324
5325 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5326 struct intel_crtc_config *pipe_config)
5327 {
5328 struct drm_device *dev = crtc->base.dev;
5329 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5330
5331 /* FIXME should check pixel clock limits on all platforms */
5332 if (INTEL_INFO(dev)->gen < 4) {
5333 struct drm_i915_private *dev_priv = dev->dev_private;
5334 int clock_limit =
5335 dev_priv->display.get_display_clock_speed(dev);
5336
5337 /*
5338 * Enable pixel doubling when the dot clock
5339 * is > 90% of the (display) core speed.
5340 *
5341 * GDG double wide on either pipe,
5342 * otherwise pipe A only.
5343 */
5344 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5345 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5346 clock_limit *= 2;
5347 pipe_config->double_wide = true;
5348 }
5349
5350 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5351 return -EINVAL;
5352 }
5353
5354 /*
5355 * Pipe horizontal size must be even in:
5356 * - DVO ganged mode
5357 * - LVDS dual channel mode
5358 * - Double wide pipe
5359 */
5360 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5361 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5362 pipe_config->pipe_src_w &= ~1;
5363
5364 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5365 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5366 */
5367 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5368 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5369 return -EINVAL;
5370
5371 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5372 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5373 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5374 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5375 * for lvds. */
5376 pipe_config->pipe_bpp = 8*3;
5377 }
5378
5379 if (HAS_IPS(dev))
5380 hsw_compute_ips_config(crtc, pipe_config);
5381
5382 /*
5383 * XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the
5384 * old clock survives for now.
5385 */
5386 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev) || HAS_DDI(dev))
5387 pipe_config->shared_dpll = crtc->config.shared_dpll;
5388
5389 if (pipe_config->has_pch_encoder)
5390 return ironlake_fdi_compute_config(crtc, pipe_config);
5391
5392 return 0;
5393 }
5394
5395 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5396 {
5397 struct drm_i915_private *dev_priv = dev->dev_private;
5398 int vco = valleyview_get_vco(dev_priv);
5399 u32 val;
5400 int divider;
5401
5402 /* FIXME: Punit isn't quite ready yet */
5403 if (IS_CHERRYVIEW(dev))
5404 return 400000;
5405
5406 mutex_lock(&dev_priv->dpio_lock);
5407 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5408 mutex_unlock(&dev_priv->dpio_lock);
5409
5410 divider = val & DISPLAY_FREQUENCY_VALUES;
5411
5412 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5413 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5414 "cdclk change in progress\n");
5415
5416 return DIV_ROUND_CLOSEST(vco << 1, divider + 1);
5417 }
5418
5419 static int i945_get_display_clock_speed(struct drm_device *dev)
5420 {
5421 return 400000;
5422 }
5423
5424 static int i915_get_display_clock_speed(struct drm_device *dev)
5425 {
5426 return 333000;
5427 }
5428
5429 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5430 {
5431 return 200000;
5432 }
5433
5434 static int pnv_get_display_clock_speed(struct drm_device *dev)
5435 {
5436 u16 gcfgc = 0;
5437
5438 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5439
5440 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5441 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5442 return 267000;
5443 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5444 return 333000;
5445 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5446 return 444000;
5447 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5448 return 200000;
5449 default:
5450 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5451 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5452 return 133000;
5453 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5454 return 167000;
5455 }
5456 }
5457
5458 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5459 {
5460 u16 gcfgc = 0;
5461
5462 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5463
5464 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5465 return 133000;
5466 else {
5467 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5468 case GC_DISPLAY_CLOCK_333_MHZ:
5469 return 333000;
5470 default:
5471 case GC_DISPLAY_CLOCK_190_200_MHZ:
5472 return 190000;
5473 }
5474 }
5475 }
5476
5477 static int i865_get_display_clock_speed(struct drm_device *dev)
5478 {
5479 return 266000;
5480 }
5481
5482 static int i855_get_display_clock_speed(struct drm_device *dev)
5483 {
5484 u16 hpllcc = 0;
5485 /* Assume that the hardware is in the high speed state. This
5486 * should be the default.
5487 */
5488 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5489 case GC_CLOCK_133_200:
5490 case GC_CLOCK_100_200:
5491 return 200000;
5492 case GC_CLOCK_166_250:
5493 return 250000;
5494 case GC_CLOCK_100_133:
5495 return 133000;
5496 }
5497
5498 /* Shouldn't happen */
5499 return 0;
5500 }
5501
5502 static int i830_get_display_clock_speed(struct drm_device *dev)
5503 {
5504 return 133000;
5505 }
5506
5507 static void
5508 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5509 {
5510 while (*num > DATA_LINK_M_N_MASK ||
5511 *den > DATA_LINK_M_N_MASK) {
5512 *num >>= 1;
5513 *den >>= 1;
5514 }
5515 }
5516
5517 static void compute_m_n(unsigned int m, unsigned int n,
5518 uint32_t *ret_m, uint32_t *ret_n)
5519 {
5520 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5521 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5522 intel_reduce_m_n_ratio(ret_m, ret_n);
5523 }
5524
5525 void
5526 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5527 int pixel_clock, int link_clock,
5528 struct intel_link_m_n *m_n)
5529 {
5530 m_n->tu = 64;
5531
5532 compute_m_n(bits_per_pixel * pixel_clock,
5533 link_clock * nlanes * 8,
5534 &m_n->gmch_m, &m_n->gmch_n);
5535
5536 compute_m_n(pixel_clock, link_clock,
5537 &m_n->link_m, &m_n->link_n);
5538 }
5539
5540 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5541 {
5542 if (i915.panel_use_ssc >= 0)
5543 return i915.panel_use_ssc != 0;
5544 return dev_priv->vbt.lvds_use_ssc
5545 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5546 }
5547
5548 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5549 {
5550 struct drm_device *dev = crtc->dev;
5551 struct drm_i915_private *dev_priv = dev->dev_private;
5552 int refclk;
5553
5554 if (IS_VALLEYVIEW(dev)) {
5555 refclk = 100000;
5556 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5557 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5558 refclk = dev_priv->vbt.lvds_ssc_freq;
5559 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5560 } else if (!IS_GEN2(dev)) {
5561 refclk = 96000;
5562 } else {
5563 refclk = 48000;
5564 }
5565
5566 return refclk;
5567 }
5568
5569 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5570 {
5571 return (1 << dpll->n) << 16 | dpll->m2;
5572 }
5573
5574 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5575 {
5576 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5577 }
5578
5579 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5580 intel_clock_t *reduced_clock)
5581 {
5582 struct drm_device *dev = crtc->base.dev;
5583 u32 fp, fp2 = 0;
5584
5585 if (IS_PINEVIEW(dev)) {
5586 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5587 if (reduced_clock)
5588 fp2 = pnv_dpll_compute_fp(reduced_clock);
5589 } else {
5590 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5591 if (reduced_clock)
5592 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5593 }
5594
5595 crtc->config.dpll_hw_state.fp0 = fp;
5596
5597 crtc->lowfreq_avail = false;
5598 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5599 reduced_clock && i915.powersave) {
5600 crtc->config.dpll_hw_state.fp1 = fp2;
5601 crtc->lowfreq_avail = true;
5602 } else {
5603 crtc->config.dpll_hw_state.fp1 = fp;
5604 }
5605 }
5606
5607 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5608 pipe)
5609 {
5610 u32 reg_val;
5611
5612 /*
5613 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5614 * and set it to a reasonable value instead.
5615 */
5616 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5617 reg_val &= 0xffffff00;
5618 reg_val |= 0x00000030;
5619 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5620
5621 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5622 reg_val &= 0x8cffffff;
5623 reg_val = 0x8c000000;
5624 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5625
5626 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5627 reg_val &= 0xffffff00;
5628 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5629
5630 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5631 reg_val &= 0x00ffffff;
5632 reg_val |= 0xb0000000;
5633 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5634 }
5635
5636 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5637 struct intel_link_m_n *m_n)
5638 {
5639 struct drm_device *dev = crtc->base.dev;
5640 struct drm_i915_private *dev_priv = dev->dev_private;
5641 int pipe = crtc->pipe;
5642
5643 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5644 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5645 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5646 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5647 }
5648
5649 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5650 struct intel_link_m_n *m_n,
5651 struct intel_link_m_n *m2_n2)
5652 {
5653 struct drm_device *dev = crtc->base.dev;
5654 struct drm_i915_private *dev_priv = dev->dev_private;
5655 int pipe = crtc->pipe;
5656 enum transcoder transcoder = crtc->config.cpu_transcoder;
5657
5658 if (INTEL_INFO(dev)->gen >= 5) {
5659 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5660 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5661 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5662 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5663 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5664 * for gen < 8) and if DRRS is supported (to make sure the
5665 * registers are not unnecessarily accessed).
5666 */
5667 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5668 crtc->config.has_drrs) {
5669 I915_WRITE(PIPE_DATA_M2(transcoder),
5670 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5671 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5672 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5673 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5674 }
5675 } else {
5676 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5677 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5678 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5679 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5680 }
5681 }
5682
5683 void intel_dp_set_m_n(struct intel_crtc *crtc)
5684 {
5685 if (crtc->config.has_pch_encoder)
5686 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5687 else
5688 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n,
5689 &crtc->config.dp_m2_n2);
5690 }
5691
5692 static void vlv_update_pll(struct intel_crtc *crtc)
5693 {
5694 u32 dpll, dpll_md;
5695
5696 /*
5697 * Enable DPIO clock input. We should never disable the reference
5698 * clock for pipe B, since VGA hotplug / manual detection depends
5699 * on it.
5700 */
5701 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5702 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5703 /* We should never disable this, set it here for state tracking */
5704 if (crtc->pipe == PIPE_B)
5705 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5706 dpll |= DPLL_VCO_ENABLE;
5707 crtc->config.dpll_hw_state.dpll = dpll;
5708
5709 dpll_md = (crtc->config.pixel_multiplier - 1)
5710 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5711 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5712 }
5713
5714 static void vlv_prepare_pll(struct intel_crtc *crtc)
5715 {
5716 struct drm_device *dev = crtc->base.dev;
5717 struct drm_i915_private *dev_priv = dev->dev_private;
5718 int pipe = crtc->pipe;
5719 u32 mdiv;
5720 u32 bestn, bestm1, bestm2, bestp1, bestp2;
5721 u32 coreclk, reg_val;
5722
5723 mutex_lock(&dev_priv->dpio_lock);
5724
5725 bestn = crtc->config.dpll.n;
5726 bestm1 = crtc->config.dpll.m1;
5727 bestm2 = crtc->config.dpll.m2;
5728 bestp1 = crtc->config.dpll.p1;
5729 bestp2 = crtc->config.dpll.p2;
5730
5731 /* See eDP HDMI DPIO driver vbios notes doc */
5732
5733 /* PLL B needs special handling */
5734 if (pipe == PIPE_B)
5735 vlv_pllb_recal_opamp(dev_priv, pipe);
5736
5737 /* Set up Tx target for periodic Rcomp update */
5738 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5739
5740 /* Disable target IRef on PLL */
5741 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5742 reg_val &= 0x00ffffff;
5743 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5744
5745 /* Disable fast lock */
5746 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5747
5748 /* Set idtafcrecal before PLL is enabled */
5749 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5750 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5751 mdiv |= ((bestn << DPIO_N_SHIFT));
5752 mdiv |= (1 << DPIO_K_SHIFT);
5753
5754 /*
5755 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5756 * but we don't support that).
5757 * Note: don't use the DAC post divider as it seems unstable.
5758 */
5759 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5760 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5761
5762 mdiv |= DPIO_ENABLE_CALIBRATION;
5763 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5764
5765 /* Set HBR and RBR LPF coefficients */
5766 if (crtc->config.port_clock == 162000 ||
5767 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5768 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5769 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5770 0x009f0003);
5771 else
5772 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5773 0x00d0000f);
5774
5775 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5776 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5777 /* Use SSC source */
5778 if (pipe == PIPE_A)
5779 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5780 0x0df40000);
5781 else
5782 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5783 0x0df70000);
5784 } else { /* HDMI or VGA */
5785 /* Use bend source */
5786 if (pipe == PIPE_A)
5787 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5788 0x0df70000);
5789 else
5790 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5791 0x0df40000);
5792 }
5793
5794 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5795 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5796 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5797 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5798 coreclk |= 0x01000000;
5799 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5800
5801 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5802 mutex_unlock(&dev_priv->dpio_lock);
5803 }
5804
5805 static void chv_update_pll(struct intel_crtc *crtc)
5806 {
5807 crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5808 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5809 DPLL_VCO_ENABLE;
5810 if (crtc->pipe != PIPE_A)
5811 crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5812
5813 crtc->config.dpll_hw_state.dpll_md =
5814 (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5815 }
5816
5817 static void chv_prepare_pll(struct intel_crtc *crtc)
5818 {
5819 struct drm_device *dev = crtc->base.dev;
5820 struct drm_i915_private *dev_priv = dev->dev_private;
5821 int pipe = crtc->pipe;
5822 int dpll_reg = DPLL(crtc->pipe);
5823 enum dpio_channel port = vlv_pipe_to_channel(pipe);
5824 u32 loopfilter, intcoeff;
5825 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5826 int refclk;
5827
5828 bestn = crtc->config.dpll.n;
5829 bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5830 bestm1 = crtc->config.dpll.m1;
5831 bestm2 = crtc->config.dpll.m2 >> 22;
5832 bestp1 = crtc->config.dpll.p1;
5833 bestp2 = crtc->config.dpll.p2;
5834
5835 /*
5836 * Enable Refclk and SSC
5837 */
5838 I915_WRITE(dpll_reg,
5839 crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5840
5841 mutex_lock(&dev_priv->dpio_lock);
5842
5843 /* p1 and p2 divider */
5844 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5845 5 << DPIO_CHV_S1_DIV_SHIFT |
5846 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5847 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5848 1 << DPIO_CHV_K_DIV_SHIFT);
5849
5850 /* Feedback post-divider - m2 */
5851 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5852
5853 /* Feedback refclk divider - n and m1 */
5854 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5855 DPIO_CHV_M1_DIV_BY_2 |
5856 1 << DPIO_CHV_N_DIV_SHIFT);
5857
5858 /* M2 fraction division */
5859 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5860
5861 /* M2 fraction division enable */
5862 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5863 DPIO_CHV_FRAC_DIV_EN |
5864 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5865
5866 /* Loop filter */
5867 refclk = i9xx_get_refclk(&crtc->base, 0);
5868 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5869 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5870 if (refclk == 100000)
5871 intcoeff = 11;
5872 else if (refclk == 38400)
5873 intcoeff = 10;
5874 else
5875 intcoeff = 9;
5876 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5877 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5878
5879 /* AFC Recal */
5880 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5881 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5882 DPIO_AFC_RECAL);
5883
5884 mutex_unlock(&dev_priv->dpio_lock);
5885 }
5886
5887 static void i9xx_update_pll(struct intel_crtc *crtc,
5888 intel_clock_t *reduced_clock,
5889 int num_connectors)
5890 {
5891 struct drm_device *dev = crtc->base.dev;
5892 struct drm_i915_private *dev_priv = dev->dev_private;
5893 u32 dpll;
5894 bool is_sdvo;
5895 struct dpll *clock = &crtc->config.dpll;
5896
5897 i9xx_update_pll_dividers(crtc, reduced_clock);
5898
5899 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5900 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5901
5902 dpll = DPLL_VGA_MODE_DIS;
5903
5904 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5905 dpll |= DPLLB_MODE_LVDS;
5906 else
5907 dpll |= DPLLB_MODE_DAC_SERIAL;
5908
5909 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5910 dpll |= (crtc->config.pixel_multiplier - 1)
5911 << SDVO_MULTIPLIER_SHIFT_HIRES;
5912 }
5913
5914 if (is_sdvo)
5915 dpll |= DPLL_SDVO_HIGH_SPEED;
5916
5917 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5918 dpll |= DPLL_SDVO_HIGH_SPEED;
5919
5920 /* compute bitmask from p1 value */
5921 if (IS_PINEVIEW(dev))
5922 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5923 else {
5924 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5925 if (IS_G4X(dev) && reduced_clock)
5926 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5927 }
5928 switch (clock->p2) {
5929 case 5:
5930 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5931 break;
5932 case 7:
5933 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5934 break;
5935 case 10:
5936 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5937 break;
5938 case 14:
5939 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5940 break;
5941 }
5942 if (INTEL_INFO(dev)->gen >= 4)
5943 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5944
5945 if (crtc->config.sdvo_tv_clock)
5946 dpll |= PLL_REF_INPUT_TVCLKINBC;
5947 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5948 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5949 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5950 else
5951 dpll |= PLL_REF_INPUT_DREFCLK;
5952
5953 dpll |= DPLL_VCO_ENABLE;
5954 crtc->config.dpll_hw_state.dpll = dpll;
5955
5956 if (INTEL_INFO(dev)->gen >= 4) {
5957 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5958 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5959 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5960 }
5961 }
5962
5963 static void i8xx_update_pll(struct intel_crtc *crtc,
5964 intel_clock_t *reduced_clock,
5965 int num_connectors)
5966 {
5967 struct drm_device *dev = crtc->base.dev;
5968 struct drm_i915_private *dev_priv = dev->dev_private;
5969 u32 dpll;
5970 struct dpll *clock = &crtc->config.dpll;
5971
5972 i9xx_update_pll_dividers(crtc, reduced_clock);
5973
5974 dpll = DPLL_VGA_MODE_DIS;
5975
5976 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5977 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5978 } else {
5979 if (clock->p1 == 2)
5980 dpll |= PLL_P1_DIVIDE_BY_TWO;
5981 else
5982 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5983 if (clock->p2 == 4)
5984 dpll |= PLL_P2_DIVIDE_BY_4;
5985 }
5986
5987 if (!IS_I830(dev) && intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5988 dpll |= DPLL_DVO_2X_MODE;
5989
5990 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5991 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5992 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5993 else
5994 dpll |= PLL_REF_INPUT_DREFCLK;
5995
5996 dpll |= DPLL_VCO_ENABLE;
5997 crtc->config.dpll_hw_state.dpll = dpll;
5998 }
5999
6000 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6001 {
6002 struct drm_device *dev = intel_crtc->base.dev;
6003 struct drm_i915_private *dev_priv = dev->dev_private;
6004 enum pipe pipe = intel_crtc->pipe;
6005 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6006 struct drm_display_mode *adjusted_mode =
6007 &intel_crtc->config.adjusted_mode;
6008 uint32_t crtc_vtotal, crtc_vblank_end;
6009 int vsyncshift = 0;
6010
6011 /* We need to be careful not to changed the adjusted mode, for otherwise
6012 * the hw state checker will get angry at the mismatch. */
6013 crtc_vtotal = adjusted_mode->crtc_vtotal;
6014 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6015
6016 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6017 /* the chip adds 2 halflines automatically */
6018 crtc_vtotal -= 1;
6019 crtc_vblank_end -= 1;
6020
6021 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
6022 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6023 else
6024 vsyncshift = adjusted_mode->crtc_hsync_start -
6025 adjusted_mode->crtc_htotal / 2;
6026 if (vsyncshift < 0)
6027 vsyncshift += adjusted_mode->crtc_htotal;
6028 }
6029
6030 if (INTEL_INFO(dev)->gen > 3)
6031 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6032
6033 I915_WRITE(HTOTAL(cpu_transcoder),
6034 (adjusted_mode->crtc_hdisplay - 1) |
6035 ((adjusted_mode->crtc_htotal - 1) << 16));
6036 I915_WRITE(HBLANK(cpu_transcoder),
6037 (adjusted_mode->crtc_hblank_start - 1) |
6038 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6039 I915_WRITE(HSYNC(cpu_transcoder),
6040 (adjusted_mode->crtc_hsync_start - 1) |
6041 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6042
6043 I915_WRITE(VTOTAL(cpu_transcoder),
6044 (adjusted_mode->crtc_vdisplay - 1) |
6045 ((crtc_vtotal - 1) << 16));
6046 I915_WRITE(VBLANK(cpu_transcoder),
6047 (adjusted_mode->crtc_vblank_start - 1) |
6048 ((crtc_vblank_end - 1) << 16));
6049 I915_WRITE(VSYNC(cpu_transcoder),
6050 (adjusted_mode->crtc_vsync_start - 1) |
6051 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6052
6053 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6054 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6055 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6056 * bits. */
6057 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6058 (pipe == PIPE_B || pipe == PIPE_C))
6059 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6060
6061 /* pipesrc controls the size that is scaled from, which should
6062 * always be the user's requested size.
6063 */
6064 I915_WRITE(PIPESRC(pipe),
6065 ((intel_crtc->config.pipe_src_w - 1) << 16) |
6066 (intel_crtc->config.pipe_src_h - 1));
6067 }
6068
6069 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6070 struct intel_crtc_config *pipe_config)
6071 {
6072 struct drm_device *dev = crtc->base.dev;
6073 struct drm_i915_private *dev_priv = dev->dev_private;
6074 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6075 uint32_t tmp;
6076
6077 tmp = I915_READ(HTOTAL(cpu_transcoder));
6078 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6079 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6080 tmp = I915_READ(HBLANK(cpu_transcoder));
6081 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6082 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6083 tmp = I915_READ(HSYNC(cpu_transcoder));
6084 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6085 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6086
6087 tmp = I915_READ(VTOTAL(cpu_transcoder));
6088 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6089 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6090 tmp = I915_READ(VBLANK(cpu_transcoder));
6091 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6092 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6093 tmp = I915_READ(VSYNC(cpu_transcoder));
6094 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6095 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6096
6097 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6098 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6099 pipe_config->adjusted_mode.crtc_vtotal += 1;
6100 pipe_config->adjusted_mode.crtc_vblank_end += 1;
6101 }
6102
6103 tmp = I915_READ(PIPESRC(crtc->pipe));
6104 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6105 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6106
6107 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
6108 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
6109 }
6110
6111 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6112 struct intel_crtc_config *pipe_config)
6113 {
6114 mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
6115 mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
6116 mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
6117 mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
6118
6119 mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
6120 mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
6121 mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
6122 mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
6123
6124 mode->flags = pipe_config->adjusted_mode.flags;
6125
6126 mode->clock = pipe_config->adjusted_mode.crtc_clock;
6127 mode->flags |= pipe_config->adjusted_mode.flags;
6128 }
6129
6130 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6131 {
6132 struct drm_device *dev = intel_crtc->base.dev;
6133 struct drm_i915_private *dev_priv = dev->dev_private;
6134 uint32_t pipeconf;
6135
6136 pipeconf = 0;
6137
6138 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6139 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6140 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6141
6142 if (intel_crtc->config.double_wide)
6143 pipeconf |= PIPECONF_DOUBLE_WIDE;
6144
6145 /* only g4x and later have fancy bpc/dither controls */
6146 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6147 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6148 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
6149 pipeconf |= PIPECONF_DITHER_EN |
6150 PIPECONF_DITHER_TYPE_SP;
6151
6152 switch (intel_crtc->config.pipe_bpp) {
6153 case 18:
6154 pipeconf |= PIPECONF_6BPC;
6155 break;
6156 case 24:
6157 pipeconf |= PIPECONF_8BPC;
6158 break;
6159 case 30:
6160 pipeconf |= PIPECONF_10BPC;
6161 break;
6162 default:
6163 /* Case prevented by intel_choose_pipe_bpp_dither. */
6164 BUG();
6165 }
6166 }
6167
6168 if (HAS_PIPE_CXSR(dev)) {
6169 if (intel_crtc->lowfreq_avail) {
6170 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6171 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6172 } else {
6173 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6174 }
6175 }
6176
6177 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6178 if (INTEL_INFO(dev)->gen < 4 ||
6179 intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
6180 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6181 else
6182 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6183 } else
6184 pipeconf |= PIPECONF_PROGRESSIVE;
6185
6186 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6187 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6188
6189 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6190 POSTING_READ(PIPECONF(intel_crtc->pipe));
6191 }
6192
6193 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
6194 int x, int y,
6195 struct drm_framebuffer *fb)
6196 {
6197 struct drm_device *dev = crtc->dev;
6198 struct drm_i915_private *dev_priv = dev->dev_private;
6199 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6200 int refclk, num_connectors = 0;
6201 intel_clock_t clock, reduced_clock;
6202 bool ok, has_reduced_clock = false;
6203 bool is_lvds = false, is_dsi = false;
6204 struct intel_encoder *encoder;
6205 const intel_limit_t *limit;
6206
6207 for_each_encoder_on_crtc(dev, crtc, encoder) {
6208 switch (encoder->type) {
6209 case INTEL_OUTPUT_LVDS:
6210 is_lvds = true;
6211 break;
6212 case INTEL_OUTPUT_DSI:
6213 is_dsi = true;
6214 break;
6215 }
6216
6217 num_connectors++;
6218 }
6219
6220 if (is_dsi)
6221 return 0;
6222
6223 if (!intel_crtc->config.clock_set) {
6224 refclk = i9xx_get_refclk(crtc, num_connectors);
6225
6226 /*
6227 * Returns a set of divisors for the desired target clock with
6228 * the given refclk, or FALSE. The returned values represent
6229 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6230 * 2) / p1 / p2.
6231 */
6232 limit = intel_limit(crtc, refclk);
6233 ok = dev_priv->display.find_dpll(limit, crtc,
6234 intel_crtc->config.port_clock,
6235 refclk, NULL, &clock);
6236 if (!ok) {
6237 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6238 return -EINVAL;
6239 }
6240
6241 if (is_lvds && dev_priv->lvds_downclock_avail) {
6242 /*
6243 * Ensure we match the reduced clock's P to the target
6244 * clock. If the clocks don't match, we can't switch
6245 * the display clock by using the FP0/FP1. In such case
6246 * we will disable the LVDS downclock feature.
6247 */
6248 has_reduced_clock =
6249 dev_priv->display.find_dpll(limit, crtc,
6250 dev_priv->lvds_downclock,
6251 refclk, &clock,
6252 &reduced_clock);
6253 }
6254 /* Compat-code for transition, will disappear. */
6255 intel_crtc->config.dpll.n = clock.n;
6256 intel_crtc->config.dpll.m1 = clock.m1;
6257 intel_crtc->config.dpll.m2 = clock.m2;
6258 intel_crtc->config.dpll.p1 = clock.p1;
6259 intel_crtc->config.dpll.p2 = clock.p2;
6260 }
6261
6262 if (IS_GEN2(dev)) {
6263 i8xx_update_pll(intel_crtc,
6264 has_reduced_clock ? &reduced_clock : NULL,
6265 num_connectors);
6266 } else if (IS_CHERRYVIEW(dev)) {
6267 chv_update_pll(intel_crtc);
6268 } else if (IS_VALLEYVIEW(dev)) {
6269 vlv_update_pll(intel_crtc);
6270 } else {
6271 i9xx_update_pll(intel_crtc,
6272 has_reduced_clock ? &reduced_clock : NULL,
6273 num_connectors);
6274 }
6275
6276 return 0;
6277 }
6278
6279 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6280 struct intel_crtc_config *pipe_config)
6281 {
6282 struct drm_device *dev = crtc->base.dev;
6283 struct drm_i915_private *dev_priv = dev->dev_private;
6284 uint32_t tmp;
6285
6286 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6287 return;
6288
6289 tmp = I915_READ(PFIT_CONTROL);
6290 if (!(tmp & PFIT_ENABLE))
6291 return;
6292
6293 /* Check whether the pfit is attached to our pipe. */
6294 if (INTEL_INFO(dev)->gen < 4) {
6295 if (crtc->pipe != PIPE_B)
6296 return;
6297 } else {
6298 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6299 return;
6300 }
6301
6302 pipe_config->gmch_pfit.control = tmp;
6303 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6304 if (INTEL_INFO(dev)->gen < 5)
6305 pipe_config->gmch_pfit.lvds_border_bits =
6306 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6307 }
6308
6309 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6310 struct intel_crtc_config *pipe_config)
6311 {
6312 struct drm_device *dev = crtc->base.dev;
6313 struct drm_i915_private *dev_priv = dev->dev_private;
6314 int pipe = pipe_config->cpu_transcoder;
6315 intel_clock_t clock;
6316 u32 mdiv;
6317 int refclk = 100000;
6318
6319 /* In case of MIPI DPLL will not even be used */
6320 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6321 return;
6322
6323 mutex_lock(&dev_priv->dpio_lock);
6324 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6325 mutex_unlock(&dev_priv->dpio_lock);
6326
6327 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6328 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6329 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6330 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6331 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6332
6333 vlv_clock(refclk, &clock);
6334
6335 /* clock.dot is the fast clock */
6336 pipe_config->port_clock = clock.dot / 5;
6337 }
6338
6339 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6340 struct intel_plane_config *plane_config)
6341 {
6342 struct drm_device *dev = crtc->base.dev;
6343 struct drm_i915_private *dev_priv = dev->dev_private;
6344 u32 val, base, offset;
6345 int pipe = crtc->pipe, plane = crtc->plane;
6346 int fourcc, pixel_format;
6347 int aligned_height;
6348
6349 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6350 if (!crtc->base.primary->fb) {
6351 DRM_DEBUG_KMS("failed to alloc fb\n");
6352 return;
6353 }
6354
6355 val = I915_READ(DSPCNTR(plane));
6356
6357 if (INTEL_INFO(dev)->gen >= 4)
6358 if (val & DISPPLANE_TILED)
6359 plane_config->tiled = true;
6360
6361 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6362 fourcc = intel_format_to_fourcc(pixel_format);
6363 crtc->base.primary->fb->pixel_format = fourcc;
6364 crtc->base.primary->fb->bits_per_pixel =
6365 drm_format_plane_cpp(fourcc, 0) * 8;
6366
6367 if (INTEL_INFO(dev)->gen >= 4) {
6368 if (plane_config->tiled)
6369 offset = I915_READ(DSPTILEOFF(plane));
6370 else
6371 offset = I915_READ(DSPLINOFF(plane));
6372 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6373 } else {
6374 base = I915_READ(DSPADDR(plane));
6375 }
6376 plane_config->base = base;
6377
6378 val = I915_READ(PIPESRC(pipe));
6379 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6380 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6381
6382 val = I915_READ(DSPSTRIDE(pipe));
6383 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
6384
6385 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6386 plane_config->tiled);
6387
6388 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6389 aligned_height);
6390
6391 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6392 pipe, plane, crtc->base.primary->fb->width,
6393 crtc->base.primary->fb->height,
6394 crtc->base.primary->fb->bits_per_pixel, base,
6395 crtc->base.primary->fb->pitches[0],
6396 plane_config->size);
6397
6398 }
6399
6400 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6401 struct intel_crtc_config *pipe_config)
6402 {
6403 struct drm_device *dev = crtc->base.dev;
6404 struct drm_i915_private *dev_priv = dev->dev_private;
6405 int pipe = pipe_config->cpu_transcoder;
6406 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6407 intel_clock_t clock;
6408 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6409 int refclk = 100000;
6410
6411 mutex_lock(&dev_priv->dpio_lock);
6412 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6413 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6414 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6415 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6416 mutex_unlock(&dev_priv->dpio_lock);
6417
6418 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6419 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6420 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6421 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6422 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6423
6424 chv_clock(refclk, &clock);
6425
6426 /* clock.dot is the fast clock */
6427 pipe_config->port_clock = clock.dot / 5;
6428 }
6429
6430 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6431 struct intel_crtc_config *pipe_config)
6432 {
6433 struct drm_device *dev = crtc->base.dev;
6434 struct drm_i915_private *dev_priv = dev->dev_private;
6435 uint32_t tmp;
6436
6437 if (!intel_display_power_enabled(dev_priv,
6438 POWER_DOMAIN_PIPE(crtc->pipe)))
6439 return false;
6440
6441 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6442 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6443
6444 tmp = I915_READ(PIPECONF(crtc->pipe));
6445 if (!(tmp & PIPECONF_ENABLE))
6446 return false;
6447
6448 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6449 switch (tmp & PIPECONF_BPC_MASK) {
6450 case PIPECONF_6BPC:
6451 pipe_config->pipe_bpp = 18;
6452 break;
6453 case PIPECONF_8BPC:
6454 pipe_config->pipe_bpp = 24;
6455 break;
6456 case PIPECONF_10BPC:
6457 pipe_config->pipe_bpp = 30;
6458 break;
6459 default:
6460 break;
6461 }
6462 }
6463
6464 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6465 pipe_config->limited_color_range = true;
6466
6467 if (INTEL_INFO(dev)->gen < 4)
6468 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6469
6470 intel_get_pipe_timings(crtc, pipe_config);
6471
6472 i9xx_get_pfit_config(crtc, pipe_config);
6473
6474 if (INTEL_INFO(dev)->gen >= 4) {
6475 tmp = I915_READ(DPLL_MD(crtc->pipe));
6476 pipe_config->pixel_multiplier =
6477 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6478 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6479 pipe_config->dpll_hw_state.dpll_md = tmp;
6480 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6481 tmp = I915_READ(DPLL(crtc->pipe));
6482 pipe_config->pixel_multiplier =
6483 ((tmp & SDVO_MULTIPLIER_MASK)
6484 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6485 } else {
6486 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6487 * port and will be fixed up in the encoder->get_config
6488 * function. */
6489 pipe_config->pixel_multiplier = 1;
6490 }
6491 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6492 if (!IS_VALLEYVIEW(dev)) {
6493 /*
6494 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6495 * on 830. Filter it out here so that we don't
6496 * report errors due to that.
6497 */
6498 if (IS_I830(dev))
6499 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6500
6501 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6502 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6503 } else {
6504 /* Mask out read-only status bits. */
6505 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6506 DPLL_PORTC_READY_MASK |
6507 DPLL_PORTB_READY_MASK);
6508 }
6509
6510 if (IS_CHERRYVIEW(dev))
6511 chv_crtc_clock_get(crtc, pipe_config);
6512 else if (IS_VALLEYVIEW(dev))
6513 vlv_crtc_clock_get(crtc, pipe_config);
6514 else
6515 i9xx_crtc_clock_get(crtc, pipe_config);
6516
6517 return true;
6518 }
6519
6520 static void ironlake_init_pch_refclk(struct drm_device *dev)
6521 {
6522 struct drm_i915_private *dev_priv = dev->dev_private;
6523 struct intel_encoder *encoder;
6524 u32 val, final;
6525 bool has_lvds = false;
6526 bool has_cpu_edp = false;
6527 bool has_panel = false;
6528 bool has_ck505 = false;
6529 bool can_ssc = false;
6530
6531 /* We need to take the global config into account */
6532 for_each_intel_encoder(dev, encoder) {
6533 switch (encoder->type) {
6534 case INTEL_OUTPUT_LVDS:
6535 has_panel = true;
6536 has_lvds = true;
6537 break;
6538 case INTEL_OUTPUT_EDP:
6539 has_panel = true;
6540 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6541 has_cpu_edp = true;
6542 break;
6543 }
6544 }
6545
6546 if (HAS_PCH_IBX(dev)) {
6547 has_ck505 = dev_priv->vbt.display_clock_mode;
6548 can_ssc = has_ck505;
6549 } else {
6550 has_ck505 = false;
6551 can_ssc = true;
6552 }
6553
6554 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6555 has_panel, has_lvds, has_ck505);
6556
6557 /* Ironlake: try to setup display ref clock before DPLL
6558 * enabling. This is only under driver's control after
6559 * PCH B stepping, previous chipset stepping should be
6560 * ignoring this setting.
6561 */
6562 val = I915_READ(PCH_DREF_CONTROL);
6563
6564 /* As we must carefully and slowly disable/enable each source in turn,
6565 * compute the final state we want first and check if we need to
6566 * make any changes at all.
6567 */
6568 final = val;
6569 final &= ~DREF_NONSPREAD_SOURCE_MASK;
6570 if (has_ck505)
6571 final |= DREF_NONSPREAD_CK505_ENABLE;
6572 else
6573 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6574
6575 final &= ~DREF_SSC_SOURCE_MASK;
6576 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6577 final &= ~DREF_SSC1_ENABLE;
6578
6579 if (has_panel) {
6580 final |= DREF_SSC_SOURCE_ENABLE;
6581
6582 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6583 final |= DREF_SSC1_ENABLE;
6584
6585 if (has_cpu_edp) {
6586 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6587 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6588 else
6589 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6590 } else
6591 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6592 } else {
6593 final |= DREF_SSC_SOURCE_DISABLE;
6594 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6595 }
6596
6597 if (final == val)
6598 return;
6599
6600 /* Always enable nonspread source */
6601 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6602
6603 if (has_ck505)
6604 val |= DREF_NONSPREAD_CK505_ENABLE;
6605 else
6606 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6607
6608 if (has_panel) {
6609 val &= ~DREF_SSC_SOURCE_MASK;
6610 val |= DREF_SSC_SOURCE_ENABLE;
6611
6612 /* SSC must be turned on before enabling the CPU output */
6613 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6614 DRM_DEBUG_KMS("Using SSC on panel\n");
6615 val |= DREF_SSC1_ENABLE;
6616 } else
6617 val &= ~DREF_SSC1_ENABLE;
6618
6619 /* Get SSC going before enabling the outputs */
6620 I915_WRITE(PCH_DREF_CONTROL, val);
6621 POSTING_READ(PCH_DREF_CONTROL);
6622 udelay(200);
6623
6624 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6625
6626 /* Enable CPU source on CPU attached eDP */
6627 if (has_cpu_edp) {
6628 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6629 DRM_DEBUG_KMS("Using SSC on eDP\n");
6630 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6631 } else
6632 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6633 } else
6634 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6635
6636 I915_WRITE(PCH_DREF_CONTROL, val);
6637 POSTING_READ(PCH_DREF_CONTROL);
6638 udelay(200);
6639 } else {
6640 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6641
6642 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6643
6644 /* Turn off CPU output */
6645 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6646
6647 I915_WRITE(PCH_DREF_CONTROL, val);
6648 POSTING_READ(PCH_DREF_CONTROL);
6649 udelay(200);
6650
6651 /* Turn off the SSC source */
6652 val &= ~DREF_SSC_SOURCE_MASK;
6653 val |= DREF_SSC_SOURCE_DISABLE;
6654
6655 /* Turn off SSC1 */
6656 val &= ~DREF_SSC1_ENABLE;
6657
6658 I915_WRITE(PCH_DREF_CONTROL, val);
6659 POSTING_READ(PCH_DREF_CONTROL);
6660 udelay(200);
6661 }
6662
6663 BUG_ON(val != final);
6664 }
6665
6666 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6667 {
6668 uint32_t tmp;
6669
6670 tmp = I915_READ(SOUTH_CHICKEN2);
6671 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6672 I915_WRITE(SOUTH_CHICKEN2, tmp);
6673
6674 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6675 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6676 DRM_ERROR("FDI mPHY reset assert timeout\n");
6677
6678 tmp = I915_READ(SOUTH_CHICKEN2);
6679 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6680 I915_WRITE(SOUTH_CHICKEN2, tmp);
6681
6682 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6683 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6684 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6685 }
6686
6687 /* WaMPhyProgramming:hsw */
6688 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6689 {
6690 uint32_t tmp;
6691
6692 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6693 tmp &= ~(0xFF << 24);
6694 tmp |= (0x12 << 24);
6695 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6696
6697 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6698 tmp |= (1 << 11);
6699 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6700
6701 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6702 tmp |= (1 << 11);
6703 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6704
6705 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6706 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6707 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6708
6709 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6710 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6711 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6712
6713 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6714 tmp &= ~(7 << 13);
6715 tmp |= (5 << 13);
6716 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6717
6718 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6719 tmp &= ~(7 << 13);
6720 tmp |= (5 << 13);
6721 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6722
6723 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6724 tmp &= ~0xFF;
6725 tmp |= 0x1C;
6726 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6727
6728 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6729 tmp &= ~0xFF;
6730 tmp |= 0x1C;
6731 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6732
6733 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6734 tmp &= ~(0xFF << 16);
6735 tmp |= (0x1C << 16);
6736 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6737
6738 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6739 tmp &= ~(0xFF << 16);
6740 tmp |= (0x1C << 16);
6741 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6742
6743 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6744 tmp |= (1 << 27);
6745 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6746
6747 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6748 tmp |= (1 << 27);
6749 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6750
6751 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6752 tmp &= ~(0xF << 28);
6753 tmp |= (4 << 28);
6754 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6755
6756 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6757 tmp &= ~(0xF << 28);
6758 tmp |= (4 << 28);
6759 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6760 }
6761
6762 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6763 * Programming" based on the parameters passed:
6764 * - Sequence to enable CLKOUT_DP
6765 * - Sequence to enable CLKOUT_DP without spread
6766 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6767 */
6768 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6769 bool with_fdi)
6770 {
6771 struct drm_i915_private *dev_priv = dev->dev_private;
6772 uint32_t reg, tmp;
6773
6774 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6775 with_spread = true;
6776 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6777 with_fdi, "LP PCH doesn't have FDI\n"))
6778 with_fdi = false;
6779
6780 mutex_lock(&dev_priv->dpio_lock);
6781
6782 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6783 tmp &= ~SBI_SSCCTL_DISABLE;
6784 tmp |= SBI_SSCCTL_PATHALT;
6785 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6786
6787 udelay(24);
6788
6789 if (with_spread) {
6790 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6791 tmp &= ~SBI_SSCCTL_PATHALT;
6792 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6793
6794 if (with_fdi) {
6795 lpt_reset_fdi_mphy(dev_priv);
6796 lpt_program_fdi_mphy(dev_priv);
6797 }
6798 }
6799
6800 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6801 SBI_GEN0 : SBI_DBUFF0;
6802 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6803 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6804 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6805
6806 mutex_unlock(&dev_priv->dpio_lock);
6807 }
6808
6809 /* Sequence to disable CLKOUT_DP */
6810 static void lpt_disable_clkout_dp(struct drm_device *dev)
6811 {
6812 struct drm_i915_private *dev_priv = dev->dev_private;
6813 uint32_t reg, tmp;
6814
6815 mutex_lock(&dev_priv->dpio_lock);
6816
6817 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6818 SBI_GEN0 : SBI_DBUFF0;
6819 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6820 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6821 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6822
6823 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6824 if (!(tmp & SBI_SSCCTL_DISABLE)) {
6825 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6826 tmp |= SBI_SSCCTL_PATHALT;
6827 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6828 udelay(32);
6829 }
6830 tmp |= SBI_SSCCTL_DISABLE;
6831 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6832 }
6833
6834 mutex_unlock(&dev_priv->dpio_lock);
6835 }
6836
6837 static void lpt_init_pch_refclk(struct drm_device *dev)
6838 {
6839 struct intel_encoder *encoder;
6840 bool has_vga = false;
6841
6842 for_each_intel_encoder(dev, encoder) {
6843 switch (encoder->type) {
6844 case INTEL_OUTPUT_ANALOG:
6845 has_vga = true;
6846 break;
6847 }
6848 }
6849
6850 if (has_vga)
6851 lpt_enable_clkout_dp(dev, true, true);
6852 else
6853 lpt_disable_clkout_dp(dev);
6854 }
6855
6856 /*
6857 * Initialize reference clocks when the driver loads
6858 */
6859 void intel_init_pch_refclk(struct drm_device *dev)
6860 {
6861 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6862 ironlake_init_pch_refclk(dev);
6863 else if (HAS_PCH_LPT(dev))
6864 lpt_init_pch_refclk(dev);
6865 }
6866
6867 static int ironlake_get_refclk(struct drm_crtc *crtc)
6868 {
6869 struct drm_device *dev = crtc->dev;
6870 struct drm_i915_private *dev_priv = dev->dev_private;
6871 struct intel_encoder *encoder;
6872 int num_connectors = 0;
6873 bool is_lvds = false;
6874
6875 for_each_encoder_on_crtc(dev, crtc, encoder) {
6876 switch (encoder->type) {
6877 case INTEL_OUTPUT_LVDS:
6878 is_lvds = true;
6879 break;
6880 }
6881 num_connectors++;
6882 }
6883
6884 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6885 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6886 dev_priv->vbt.lvds_ssc_freq);
6887 return dev_priv->vbt.lvds_ssc_freq;
6888 }
6889
6890 return 120000;
6891 }
6892
6893 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6894 {
6895 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6896 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6897 int pipe = intel_crtc->pipe;
6898 uint32_t val;
6899
6900 val = 0;
6901
6902 switch (intel_crtc->config.pipe_bpp) {
6903 case 18:
6904 val |= PIPECONF_6BPC;
6905 break;
6906 case 24:
6907 val |= PIPECONF_8BPC;
6908 break;
6909 case 30:
6910 val |= PIPECONF_10BPC;
6911 break;
6912 case 36:
6913 val |= PIPECONF_12BPC;
6914 break;
6915 default:
6916 /* Case prevented by intel_choose_pipe_bpp_dither. */
6917 BUG();
6918 }
6919
6920 if (intel_crtc->config.dither)
6921 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6922
6923 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6924 val |= PIPECONF_INTERLACED_ILK;
6925 else
6926 val |= PIPECONF_PROGRESSIVE;
6927
6928 if (intel_crtc->config.limited_color_range)
6929 val |= PIPECONF_COLOR_RANGE_SELECT;
6930
6931 I915_WRITE(PIPECONF(pipe), val);
6932 POSTING_READ(PIPECONF(pipe));
6933 }
6934
6935 /*
6936 * Set up the pipe CSC unit.
6937 *
6938 * Currently only full range RGB to limited range RGB conversion
6939 * is supported, but eventually this should handle various
6940 * RGB<->YCbCr scenarios as well.
6941 */
6942 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6943 {
6944 struct drm_device *dev = crtc->dev;
6945 struct drm_i915_private *dev_priv = dev->dev_private;
6946 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6947 int pipe = intel_crtc->pipe;
6948 uint16_t coeff = 0x7800; /* 1.0 */
6949
6950 /*
6951 * TODO: Check what kind of values actually come out of the pipe
6952 * with these coeff/postoff values and adjust to get the best
6953 * accuracy. Perhaps we even need to take the bpc value into
6954 * consideration.
6955 */
6956
6957 if (intel_crtc->config.limited_color_range)
6958 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6959
6960 /*
6961 * GY/GU and RY/RU should be the other way around according
6962 * to BSpec, but reality doesn't agree. Just set them up in
6963 * a way that results in the correct picture.
6964 */
6965 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6966 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6967
6968 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6969 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6970
6971 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6972 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6973
6974 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6975 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6976 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6977
6978 if (INTEL_INFO(dev)->gen > 6) {
6979 uint16_t postoff = 0;
6980
6981 if (intel_crtc->config.limited_color_range)
6982 postoff = (16 * (1 << 12) / 255) & 0x1fff;
6983
6984 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6985 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6986 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6987
6988 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6989 } else {
6990 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6991
6992 if (intel_crtc->config.limited_color_range)
6993 mode |= CSC_BLACK_SCREEN_OFFSET;
6994
6995 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6996 }
6997 }
6998
6999 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7000 {
7001 struct drm_device *dev = crtc->dev;
7002 struct drm_i915_private *dev_priv = dev->dev_private;
7003 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7004 enum pipe pipe = intel_crtc->pipe;
7005 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7006 uint32_t val;
7007
7008 val = 0;
7009
7010 if (IS_HASWELL(dev) && intel_crtc->config.dither)
7011 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7012
7013 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7014 val |= PIPECONF_INTERLACED_ILK;
7015 else
7016 val |= PIPECONF_PROGRESSIVE;
7017
7018 I915_WRITE(PIPECONF(cpu_transcoder), val);
7019 POSTING_READ(PIPECONF(cpu_transcoder));
7020
7021 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7022 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7023
7024 if (IS_BROADWELL(dev)) {
7025 val = 0;
7026
7027 switch (intel_crtc->config.pipe_bpp) {
7028 case 18:
7029 val |= PIPEMISC_DITHER_6_BPC;
7030 break;
7031 case 24:
7032 val |= PIPEMISC_DITHER_8_BPC;
7033 break;
7034 case 30:
7035 val |= PIPEMISC_DITHER_10_BPC;
7036 break;
7037 case 36:
7038 val |= PIPEMISC_DITHER_12_BPC;
7039 break;
7040 default:
7041 /* Case prevented by pipe_config_set_bpp. */
7042 BUG();
7043 }
7044
7045 if (intel_crtc->config.dither)
7046 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7047
7048 I915_WRITE(PIPEMISC(pipe), val);
7049 }
7050 }
7051
7052 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7053 intel_clock_t *clock,
7054 bool *has_reduced_clock,
7055 intel_clock_t *reduced_clock)
7056 {
7057 struct drm_device *dev = crtc->dev;
7058 struct drm_i915_private *dev_priv = dev->dev_private;
7059 struct intel_encoder *intel_encoder;
7060 int refclk;
7061 const intel_limit_t *limit;
7062 bool ret, is_lvds = false;
7063
7064 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
7065 switch (intel_encoder->type) {
7066 case INTEL_OUTPUT_LVDS:
7067 is_lvds = true;
7068 break;
7069 }
7070 }
7071
7072 refclk = ironlake_get_refclk(crtc);
7073
7074 /*
7075 * Returns a set of divisors for the desired target clock with the given
7076 * refclk, or FALSE. The returned values represent the clock equation:
7077 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7078 */
7079 limit = intel_limit(crtc, refclk);
7080 ret = dev_priv->display.find_dpll(limit, crtc,
7081 to_intel_crtc(crtc)->config.port_clock,
7082 refclk, NULL, clock);
7083 if (!ret)
7084 return false;
7085
7086 if (is_lvds && dev_priv->lvds_downclock_avail) {
7087 /*
7088 * Ensure we match the reduced clock's P to the target clock.
7089 * If the clocks don't match, we can't switch the display clock
7090 * by using the FP0/FP1. In such case we will disable the LVDS
7091 * downclock feature.
7092 */
7093 *has_reduced_clock =
7094 dev_priv->display.find_dpll(limit, crtc,
7095 dev_priv->lvds_downclock,
7096 refclk, clock,
7097 reduced_clock);
7098 }
7099
7100 return true;
7101 }
7102
7103 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7104 {
7105 /*
7106 * Account for spread spectrum to avoid
7107 * oversubscribing the link. Max center spread
7108 * is 2.5%; use 5% for safety's sake.
7109 */
7110 u32 bps = target_clock * bpp * 21 / 20;
7111 return DIV_ROUND_UP(bps, link_bw * 8);
7112 }
7113
7114 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7115 {
7116 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7117 }
7118
7119 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7120 u32 *fp,
7121 intel_clock_t *reduced_clock, u32 *fp2)
7122 {
7123 struct drm_crtc *crtc = &intel_crtc->base;
7124 struct drm_device *dev = crtc->dev;
7125 struct drm_i915_private *dev_priv = dev->dev_private;
7126 struct intel_encoder *intel_encoder;
7127 uint32_t dpll;
7128 int factor, num_connectors = 0;
7129 bool is_lvds = false, is_sdvo = false;
7130
7131 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
7132 switch (intel_encoder->type) {
7133 case INTEL_OUTPUT_LVDS:
7134 is_lvds = true;
7135 break;
7136 case INTEL_OUTPUT_SDVO:
7137 case INTEL_OUTPUT_HDMI:
7138 is_sdvo = true;
7139 break;
7140 }
7141
7142 num_connectors++;
7143 }
7144
7145 /* Enable autotuning of the PLL clock (if permissible) */
7146 factor = 21;
7147 if (is_lvds) {
7148 if ((intel_panel_use_ssc(dev_priv) &&
7149 dev_priv->vbt.lvds_ssc_freq == 100000) ||
7150 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7151 factor = 25;
7152 } else if (intel_crtc->config.sdvo_tv_clock)
7153 factor = 20;
7154
7155 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7156 *fp |= FP_CB_TUNE;
7157
7158 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7159 *fp2 |= FP_CB_TUNE;
7160
7161 dpll = 0;
7162
7163 if (is_lvds)
7164 dpll |= DPLLB_MODE_LVDS;
7165 else
7166 dpll |= DPLLB_MODE_DAC_SERIAL;
7167
7168 dpll |= (intel_crtc->config.pixel_multiplier - 1)
7169 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7170
7171 if (is_sdvo)
7172 dpll |= DPLL_SDVO_HIGH_SPEED;
7173 if (intel_crtc->config.has_dp_encoder)
7174 dpll |= DPLL_SDVO_HIGH_SPEED;
7175
7176 /* compute bitmask from p1 value */
7177 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7178 /* also FPA1 */
7179 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7180
7181 switch (intel_crtc->config.dpll.p2) {
7182 case 5:
7183 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7184 break;
7185 case 7:
7186 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7187 break;
7188 case 10:
7189 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7190 break;
7191 case 14:
7192 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7193 break;
7194 }
7195
7196 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7197 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7198 else
7199 dpll |= PLL_REF_INPUT_DREFCLK;
7200
7201 return dpll | DPLL_VCO_ENABLE;
7202 }
7203
7204 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
7205 int x, int y,
7206 struct drm_framebuffer *fb)
7207 {
7208 struct drm_device *dev = crtc->dev;
7209 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7210 int num_connectors = 0;
7211 intel_clock_t clock, reduced_clock;
7212 u32 dpll = 0, fp = 0, fp2 = 0;
7213 bool ok, has_reduced_clock = false;
7214 bool is_lvds = false;
7215 struct intel_encoder *encoder;
7216 struct intel_shared_dpll *pll;
7217
7218 for_each_encoder_on_crtc(dev, crtc, encoder) {
7219 switch (encoder->type) {
7220 case INTEL_OUTPUT_LVDS:
7221 is_lvds = true;
7222 break;
7223 }
7224
7225 num_connectors++;
7226 }
7227
7228 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7229 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7230
7231 ok = ironlake_compute_clocks(crtc, &clock,
7232 &has_reduced_clock, &reduced_clock);
7233 if (!ok && !intel_crtc->config.clock_set) {
7234 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7235 return -EINVAL;
7236 }
7237 /* Compat-code for transition, will disappear. */
7238 if (!intel_crtc->config.clock_set) {
7239 intel_crtc->config.dpll.n = clock.n;
7240 intel_crtc->config.dpll.m1 = clock.m1;
7241 intel_crtc->config.dpll.m2 = clock.m2;
7242 intel_crtc->config.dpll.p1 = clock.p1;
7243 intel_crtc->config.dpll.p2 = clock.p2;
7244 }
7245
7246 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7247 if (intel_crtc->config.has_pch_encoder) {
7248 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
7249 if (has_reduced_clock)
7250 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7251
7252 dpll = ironlake_compute_dpll(intel_crtc,
7253 &fp, &reduced_clock,
7254 has_reduced_clock ? &fp2 : NULL);
7255
7256 intel_crtc->config.dpll_hw_state.dpll = dpll;
7257 intel_crtc->config.dpll_hw_state.fp0 = fp;
7258 if (has_reduced_clock)
7259 intel_crtc->config.dpll_hw_state.fp1 = fp2;
7260 else
7261 intel_crtc->config.dpll_hw_state.fp1 = fp;
7262
7263 pll = intel_get_shared_dpll(intel_crtc);
7264 if (pll == NULL) {
7265 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7266 pipe_name(intel_crtc->pipe));
7267 return -EINVAL;
7268 }
7269 } else
7270 intel_put_shared_dpll(intel_crtc);
7271
7272 if (is_lvds && has_reduced_clock && i915.powersave)
7273 intel_crtc->lowfreq_avail = true;
7274 else
7275 intel_crtc->lowfreq_avail = false;
7276
7277 return 0;
7278 }
7279
7280 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7281 struct intel_link_m_n *m_n)
7282 {
7283 struct drm_device *dev = crtc->base.dev;
7284 struct drm_i915_private *dev_priv = dev->dev_private;
7285 enum pipe pipe = crtc->pipe;
7286
7287 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7288 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7289 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7290 & ~TU_SIZE_MASK;
7291 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7292 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7293 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7294 }
7295
7296 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7297 enum transcoder transcoder,
7298 struct intel_link_m_n *m_n,
7299 struct intel_link_m_n *m2_n2)
7300 {
7301 struct drm_device *dev = crtc->base.dev;
7302 struct drm_i915_private *dev_priv = dev->dev_private;
7303 enum pipe pipe = crtc->pipe;
7304
7305 if (INTEL_INFO(dev)->gen >= 5) {
7306 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7307 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7308 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7309 & ~TU_SIZE_MASK;
7310 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7311 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7312 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7313 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7314 * gen < 8) and if DRRS is supported (to make sure the
7315 * registers are not unnecessarily read).
7316 */
7317 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7318 crtc->config.has_drrs) {
7319 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7320 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7321 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7322 & ~TU_SIZE_MASK;
7323 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7324 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7325 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7326 }
7327 } else {
7328 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7329 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7330 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7331 & ~TU_SIZE_MASK;
7332 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7333 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7334 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7335 }
7336 }
7337
7338 void intel_dp_get_m_n(struct intel_crtc *crtc,
7339 struct intel_crtc_config *pipe_config)
7340 {
7341 if (crtc->config.has_pch_encoder)
7342 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7343 else
7344 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7345 &pipe_config->dp_m_n,
7346 &pipe_config->dp_m2_n2);
7347 }
7348
7349 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7350 struct intel_crtc_config *pipe_config)
7351 {
7352 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7353 &pipe_config->fdi_m_n, NULL);
7354 }
7355
7356 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7357 struct intel_crtc_config *pipe_config)
7358 {
7359 struct drm_device *dev = crtc->base.dev;
7360 struct drm_i915_private *dev_priv = dev->dev_private;
7361 uint32_t tmp;
7362
7363 tmp = I915_READ(PF_CTL(crtc->pipe));
7364
7365 if (tmp & PF_ENABLE) {
7366 pipe_config->pch_pfit.enabled = true;
7367 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7368 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7369
7370 /* We currently do not free assignements of panel fitters on
7371 * ivb/hsw (since we don't use the higher upscaling modes which
7372 * differentiates them) so just WARN about this case for now. */
7373 if (IS_GEN7(dev)) {
7374 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7375 PF_PIPE_SEL_IVB(crtc->pipe));
7376 }
7377 }
7378 }
7379
7380 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7381 struct intel_plane_config *plane_config)
7382 {
7383 struct drm_device *dev = crtc->base.dev;
7384 struct drm_i915_private *dev_priv = dev->dev_private;
7385 u32 val, base, offset;
7386 int pipe = crtc->pipe, plane = crtc->plane;
7387 int fourcc, pixel_format;
7388 int aligned_height;
7389
7390 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7391 if (!crtc->base.primary->fb) {
7392 DRM_DEBUG_KMS("failed to alloc fb\n");
7393 return;
7394 }
7395
7396 val = I915_READ(DSPCNTR(plane));
7397
7398 if (INTEL_INFO(dev)->gen >= 4)
7399 if (val & DISPPLANE_TILED)
7400 plane_config->tiled = true;
7401
7402 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7403 fourcc = intel_format_to_fourcc(pixel_format);
7404 crtc->base.primary->fb->pixel_format = fourcc;
7405 crtc->base.primary->fb->bits_per_pixel =
7406 drm_format_plane_cpp(fourcc, 0) * 8;
7407
7408 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7409 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7410 offset = I915_READ(DSPOFFSET(plane));
7411 } else {
7412 if (plane_config->tiled)
7413 offset = I915_READ(DSPTILEOFF(plane));
7414 else
7415 offset = I915_READ(DSPLINOFF(plane));
7416 }
7417 plane_config->base = base;
7418
7419 val = I915_READ(PIPESRC(pipe));
7420 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7421 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7422
7423 val = I915_READ(DSPSTRIDE(pipe));
7424 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
7425
7426 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7427 plane_config->tiled);
7428
7429 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7430 aligned_height);
7431
7432 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7433 pipe, plane, crtc->base.primary->fb->width,
7434 crtc->base.primary->fb->height,
7435 crtc->base.primary->fb->bits_per_pixel, base,
7436 crtc->base.primary->fb->pitches[0],
7437 plane_config->size);
7438 }
7439
7440 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7441 struct intel_crtc_config *pipe_config)
7442 {
7443 struct drm_device *dev = crtc->base.dev;
7444 struct drm_i915_private *dev_priv = dev->dev_private;
7445 uint32_t tmp;
7446
7447 if (!intel_display_power_enabled(dev_priv,
7448 POWER_DOMAIN_PIPE(crtc->pipe)))
7449 return false;
7450
7451 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7452 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7453
7454 tmp = I915_READ(PIPECONF(crtc->pipe));
7455 if (!(tmp & PIPECONF_ENABLE))
7456 return false;
7457
7458 switch (tmp & PIPECONF_BPC_MASK) {
7459 case PIPECONF_6BPC:
7460 pipe_config->pipe_bpp = 18;
7461 break;
7462 case PIPECONF_8BPC:
7463 pipe_config->pipe_bpp = 24;
7464 break;
7465 case PIPECONF_10BPC:
7466 pipe_config->pipe_bpp = 30;
7467 break;
7468 case PIPECONF_12BPC:
7469 pipe_config->pipe_bpp = 36;
7470 break;
7471 default:
7472 break;
7473 }
7474
7475 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7476 pipe_config->limited_color_range = true;
7477
7478 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7479 struct intel_shared_dpll *pll;
7480
7481 pipe_config->has_pch_encoder = true;
7482
7483 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7484 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7485 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7486
7487 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7488
7489 if (HAS_PCH_IBX(dev_priv->dev)) {
7490 pipe_config->shared_dpll =
7491 (enum intel_dpll_id) crtc->pipe;
7492 } else {
7493 tmp = I915_READ(PCH_DPLL_SEL);
7494 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7495 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7496 else
7497 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7498 }
7499
7500 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7501
7502 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7503 &pipe_config->dpll_hw_state));
7504
7505 tmp = pipe_config->dpll_hw_state.dpll;
7506 pipe_config->pixel_multiplier =
7507 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7508 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7509
7510 ironlake_pch_clock_get(crtc, pipe_config);
7511 } else {
7512 pipe_config->pixel_multiplier = 1;
7513 }
7514
7515 intel_get_pipe_timings(crtc, pipe_config);
7516
7517 ironlake_get_pfit_config(crtc, pipe_config);
7518
7519 return true;
7520 }
7521
7522 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7523 {
7524 struct drm_device *dev = dev_priv->dev;
7525 struct intel_crtc *crtc;
7526
7527 for_each_intel_crtc(dev, crtc)
7528 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7529 pipe_name(crtc->pipe));
7530
7531 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7532 WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7533 WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7534 WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7535 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7536 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7537 "CPU PWM1 enabled\n");
7538 if (IS_HASWELL(dev))
7539 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7540 "CPU PWM2 enabled\n");
7541 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7542 "PCH PWM1 enabled\n");
7543 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7544 "Utility pin enabled\n");
7545 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7546
7547 /*
7548 * In theory we can still leave IRQs enabled, as long as only the HPD
7549 * interrupts remain enabled. We used to check for that, but since it's
7550 * gen-specific and since we only disable LCPLL after we fully disable
7551 * the interrupts, the check below should be enough.
7552 */
7553 WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7554 }
7555
7556 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7557 {
7558 struct drm_device *dev = dev_priv->dev;
7559
7560 if (IS_HASWELL(dev))
7561 return I915_READ(D_COMP_HSW);
7562 else
7563 return I915_READ(D_COMP_BDW);
7564 }
7565
7566 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7567 {
7568 struct drm_device *dev = dev_priv->dev;
7569
7570 if (IS_HASWELL(dev)) {
7571 mutex_lock(&dev_priv->rps.hw_lock);
7572 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7573 val))
7574 DRM_ERROR("Failed to write to D_COMP\n");
7575 mutex_unlock(&dev_priv->rps.hw_lock);
7576 } else {
7577 I915_WRITE(D_COMP_BDW, val);
7578 POSTING_READ(D_COMP_BDW);
7579 }
7580 }
7581
7582 /*
7583 * This function implements pieces of two sequences from BSpec:
7584 * - Sequence for display software to disable LCPLL
7585 * - Sequence for display software to allow package C8+
7586 * The steps implemented here are just the steps that actually touch the LCPLL
7587 * register. Callers should take care of disabling all the display engine
7588 * functions, doing the mode unset, fixing interrupts, etc.
7589 */
7590 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7591 bool switch_to_fclk, bool allow_power_down)
7592 {
7593 uint32_t val;
7594
7595 assert_can_disable_lcpll(dev_priv);
7596
7597 val = I915_READ(LCPLL_CTL);
7598
7599 if (switch_to_fclk) {
7600 val |= LCPLL_CD_SOURCE_FCLK;
7601 I915_WRITE(LCPLL_CTL, val);
7602
7603 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7604 LCPLL_CD_SOURCE_FCLK_DONE, 1))
7605 DRM_ERROR("Switching to FCLK failed\n");
7606
7607 val = I915_READ(LCPLL_CTL);
7608 }
7609
7610 val |= LCPLL_PLL_DISABLE;
7611 I915_WRITE(LCPLL_CTL, val);
7612 POSTING_READ(LCPLL_CTL);
7613
7614 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7615 DRM_ERROR("LCPLL still locked\n");
7616
7617 val = hsw_read_dcomp(dev_priv);
7618 val |= D_COMP_COMP_DISABLE;
7619 hsw_write_dcomp(dev_priv, val);
7620 ndelay(100);
7621
7622 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7623 1))
7624 DRM_ERROR("D_COMP RCOMP still in progress\n");
7625
7626 if (allow_power_down) {
7627 val = I915_READ(LCPLL_CTL);
7628 val |= LCPLL_POWER_DOWN_ALLOW;
7629 I915_WRITE(LCPLL_CTL, val);
7630 POSTING_READ(LCPLL_CTL);
7631 }
7632 }
7633
7634 /*
7635 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7636 * source.
7637 */
7638 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7639 {
7640 uint32_t val;
7641 unsigned long irqflags;
7642
7643 val = I915_READ(LCPLL_CTL);
7644
7645 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7646 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7647 return;
7648
7649 /*
7650 * Make sure we're not on PC8 state before disabling PC8, otherwise
7651 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7652 *
7653 * The other problem is that hsw_restore_lcpll() is called as part of
7654 * the runtime PM resume sequence, so we can't just call
7655 * gen6_gt_force_wake_get() because that function calls
7656 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7657 * while we are on the resume sequence. So to solve this problem we have
7658 * to call special forcewake code that doesn't touch runtime PM and
7659 * doesn't enable the forcewake delayed work.
7660 */
7661 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7662 if (dev_priv->uncore.forcewake_count++ == 0)
7663 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7664 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7665
7666 if (val & LCPLL_POWER_DOWN_ALLOW) {
7667 val &= ~LCPLL_POWER_DOWN_ALLOW;
7668 I915_WRITE(LCPLL_CTL, val);
7669 POSTING_READ(LCPLL_CTL);
7670 }
7671
7672 val = hsw_read_dcomp(dev_priv);
7673 val |= D_COMP_COMP_FORCE;
7674 val &= ~D_COMP_COMP_DISABLE;
7675 hsw_write_dcomp(dev_priv, val);
7676
7677 val = I915_READ(LCPLL_CTL);
7678 val &= ~LCPLL_PLL_DISABLE;
7679 I915_WRITE(LCPLL_CTL, val);
7680
7681 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7682 DRM_ERROR("LCPLL not locked yet\n");
7683
7684 if (val & LCPLL_CD_SOURCE_FCLK) {
7685 val = I915_READ(LCPLL_CTL);
7686 val &= ~LCPLL_CD_SOURCE_FCLK;
7687 I915_WRITE(LCPLL_CTL, val);
7688
7689 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7690 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7691 DRM_ERROR("Switching back to LCPLL failed\n");
7692 }
7693
7694 /* See the big comment above. */
7695 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7696 if (--dev_priv->uncore.forcewake_count == 0)
7697 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7698 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7699 }
7700
7701 /*
7702 * Package states C8 and deeper are really deep PC states that can only be
7703 * reached when all the devices on the system allow it, so even if the graphics
7704 * device allows PC8+, it doesn't mean the system will actually get to these
7705 * states. Our driver only allows PC8+ when going into runtime PM.
7706 *
7707 * The requirements for PC8+ are that all the outputs are disabled, the power
7708 * well is disabled and most interrupts are disabled, and these are also
7709 * requirements for runtime PM. When these conditions are met, we manually do
7710 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7711 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7712 * hang the machine.
7713 *
7714 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7715 * the state of some registers, so when we come back from PC8+ we need to
7716 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7717 * need to take care of the registers kept by RC6. Notice that this happens even
7718 * if we don't put the device in PCI D3 state (which is what currently happens
7719 * because of the runtime PM support).
7720 *
7721 * For more, read "Display Sequences for Package C8" on the hardware
7722 * documentation.
7723 */
7724 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7725 {
7726 struct drm_device *dev = dev_priv->dev;
7727 uint32_t val;
7728
7729 DRM_DEBUG_KMS("Enabling package C8+\n");
7730
7731 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7732 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7733 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7734 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7735 }
7736
7737 lpt_disable_clkout_dp(dev);
7738 hsw_disable_lcpll(dev_priv, true, true);
7739 }
7740
7741 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7742 {
7743 struct drm_device *dev = dev_priv->dev;
7744 uint32_t val;
7745
7746 DRM_DEBUG_KMS("Disabling package C8+\n");
7747
7748 hsw_restore_lcpll(dev_priv);
7749 lpt_init_pch_refclk(dev);
7750
7751 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7752 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7753 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7754 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7755 }
7756
7757 intel_prepare_ddi(dev);
7758 }
7759
7760 static void snb_modeset_global_resources(struct drm_device *dev)
7761 {
7762 modeset_update_crtc_power_domains(dev);
7763 }
7764
7765 static void haswell_modeset_global_resources(struct drm_device *dev)
7766 {
7767 modeset_update_crtc_power_domains(dev);
7768 }
7769
7770 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7771 int x, int y,
7772 struct drm_framebuffer *fb)
7773 {
7774 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7775
7776 if (!intel_ddi_pll_select(intel_crtc))
7777 return -EINVAL;
7778
7779 intel_crtc->lowfreq_avail = false;
7780
7781 return 0;
7782 }
7783
7784 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
7785 enum port port,
7786 struct intel_crtc_config *pipe_config)
7787 {
7788 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
7789
7790 switch (pipe_config->ddi_pll_sel) {
7791 case PORT_CLK_SEL_WRPLL1:
7792 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
7793 break;
7794 case PORT_CLK_SEL_WRPLL2:
7795 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
7796 break;
7797 }
7798 }
7799
7800 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
7801 struct intel_crtc_config *pipe_config)
7802 {
7803 struct drm_device *dev = crtc->base.dev;
7804 struct drm_i915_private *dev_priv = dev->dev_private;
7805 struct intel_shared_dpll *pll;
7806 enum port port;
7807 uint32_t tmp;
7808
7809 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7810
7811 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
7812
7813 haswell_get_ddi_pll(dev_priv, port, pipe_config);
7814
7815 if (pipe_config->shared_dpll >= 0) {
7816 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7817
7818 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7819 &pipe_config->dpll_hw_state));
7820 }
7821
7822 /*
7823 * Haswell has only FDI/PCH transcoder A. It is which is connected to
7824 * DDI E. So just check whether this pipe is wired to DDI E and whether
7825 * the PCH transcoder is on.
7826 */
7827 if ((port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7828 pipe_config->has_pch_encoder = true;
7829
7830 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7831 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7832 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7833
7834 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7835 }
7836 }
7837
7838 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7839 struct intel_crtc_config *pipe_config)
7840 {
7841 struct drm_device *dev = crtc->base.dev;
7842 struct drm_i915_private *dev_priv = dev->dev_private;
7843 enum intel_display_power_domain pfit_domain;
7844 uint32_t tmp;
7845
7846 if (!intel_display_power_enabled(dev_priv,
7847 POWER_DOMAIN_PIPE(crtc->pipe)))
7848 return false;
7849
7850 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7851 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7852
7853 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7854 if (tmp & TRANS_DDI_FUNC_ENABLE) {
7855 enum pipe trans_edp_pipe;
7856 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7857 default:
7858 WARN(1, "unknown pipe linked to edp transcoder\n");
7859 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7860 case TRANS_DDI_EDP_INPUT_A_ON:
7861 trans_edp_pipe = PIPE_A;
7862 break;
7863 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7864 trans_edp_pipe = PIPE_B;
7865 break;
7866 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7867 trans_edp_pipe = PIPE_C;
7868 break;
7869 }
7870
7871 if (trans_edp_pipe == crtc->pipe)
7872 pipe_config->cpu_transcoder = TRANSCODER_EDP;
7873 }
7874
7875 if (!intel_display_power_enabled(dev_priv,
7876 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7877 return false;
7878
7879 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7880 if (!(tmp & PIPECONF_ENABLE))
7881 return false;
7882
7883 haswell_get_ddi_port_state(crtc, pipe_config);
7884
7885 intel_get_pipe_timings(crtc, pipe_config);
7886
7887 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7888 if (intel_display_power_enabled(dev_priv, pfit_domain))
7889 ironlake_get_pfit_config(crtc, pipe_config);
7890
7891 if (IS_HASWELL(dev))
7892 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7893 (I915_READ(IPS_CTL) & IPS_ENABLE);
7894
7895 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
7896 pipe_config->pixel_multiplier =
7897 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
7898 } else {
7899 pipe_config->pixel_multiplier = 1;
7900 }
7901
7902 return true;
7903 }
7904
7905 static struct {
7906 int clock;
7907 u32 config;
7908 } hdmi_audio_clock[] = {
7909 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7910 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7911 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7912 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7913 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7914 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7915 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7916 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7917 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7918 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7919 };
7920
7921 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7922 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7923 {
7924 int i;
7925
7926 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7927 if (mode->clock == hdmi_audio_clock[i].clock)
7928 break;
7929 }
7930
7931 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7932 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7933 i = 1;
7934 }
7935
7936 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7937 hdmi_audio_clock[i].clock,
7938 hdmi_audio_clock[i].config);
7939
7940 return hdmi_audio_clock[i].config;
7941 }
7942
7943 static bool intel_eld_uptodate(struct drm_connector *connector,
7944 int reg_eldv, uint32_t bits_eldv,
7945 int reg_elda, uint32_t bits_elda,
7946 int reg_edid)
7947 {
7948 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7949 uint8_t *eld = connector->eld;
7950 uint32_t i;
7951
7952 i = I915_READ(reg_eldv);
7953 i &= bits_eldv;
7954
7955 if (!eld[0])
7956 return !i;
7957
7958 if (!i)
7959 return false;
7960
7961 i = I915_READ(reg_elda);
7962 i &= ~bits_elda;
7963 I915_WRITE(reg_elda, i);
7964
7965 for (i = 0; i < eld[2]; i++)
7966 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7967 return false;
7968
7969 return true;
7970 }
7971
7972 static void g4x_write_eld(struct drm_connector *connector,
7973 struct drm_crtc *crtc,
7974 struct drm_display_mode *mode)
7975 {
7976 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7977 uint8_t *eld = connector->eld;
7978 uint32_t eldv;
7979 uint32_t len;
7980 uint32_t i;
7981
7982 i = I915_READ(G4X_AUD_VID_DID);
7983
7984 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7985 eldv = G4X_ELDV_DEVCL_DEVBLC;
7986 else
7987 eldv = G4X_ELDV_DEVCTG;
7988
7989 if (intel_eld_uptodate(connector,
7990 G4X_AUD_CNTL_ST, eldv,
7991 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7992 G4X_HDMIW_HDMIEDID))
7993 return;
7994
7995 i = I915_READ(G4X_AUD_CNTL_ST);
7996 i &= ~(eldv | G4X_ELD_ADDR);
7997 len = (i >> 9) & 0x1f; /* ELD buffer size */
7998 I915_WRITE(G4X_AUD_CNTL_ST, i);
7999
8000 if (!eld[0])
8001 return;
8002
8003 len = min_t(uint8_t, eld[2], len);
8004 DRM_DEBUG_DRIVER("ELD size %d\n", len);
8005 for (i = 0; i < len; i++)
8006 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
8007
8008 i = I915_READ(G4X_AUD_CNTL_ST);
8009 i |= eldv;
8010 I915_WRITE(G4X_AUD_CNTL_ST, i);
8011 }
8012
8013 static void haswell_write_eld(struct drm_connector *connector,
8014 struct drm_crtc *crtc,
8015 struct drm_display_mode *mode)
8016 {
8017 struct drm_i915_private *dev_priv = connector->dev->dev_private;
8018 uint8_t *eld = connector->eld;
8019 uint32_t eldv;
8020 uint32_t i;
8021 int len;
8022 int pipe = to_intel_crtc(crtc)->pipe;
8023 int tmp;
8024
8025 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
8026 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
8027 int aud_config = HSW_AUD_CFG(pipe);
8028 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
8029
8030 /* Audio output enable */
8031 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
8032 tmp = I915_READ(aud_cntrl_st2);
8033 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
8034 I915_WRITE(aud_cntrl_st2, tmp);
8035 POSTING_READ(aud_cntrl_st2);
8036
8037 assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
8038
8039 /* Set ELD valid state */
8040 tmp = I915_READ(aud_cntrl_st2);
8041 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
8042 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
8043 I915_WRITE(aud_cntrl_st2, tmp);
8044 tmp = I915_READ(aud_cntrl_st2);
8045 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
8046
8047 /* Enable HDMI mode */
8048 tmp = I915_READ(aud_config);
8049 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
8050 /* clear N_programing_enable and N_value_index */
8051 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
8052 I915_WRITE(aud_config, tmp);
8053
8054 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
8055
8056 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
8057
8058 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
8059 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
8060 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
8061 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
8062 } else {
8063 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
8064 }
8065
8066 if (intel_eld_uptodate(connector,
8067 aud_cntrl_st2, eldv,
8068 aud_cntl_st, IBX_ELD_ADDRESS,
8069 hdmiw_hdmiedid))
8070 return;
8071
8072 i = I915_READ(aud_cntrl_st2);
8073 i &= ~eldv;
8074 I915_WRITE(aud_cntrl_st2, i);
8075
8076 if (!eld[0])
8077 return;
8078
8079 i = I915_READ(aud_cntl_st);
8080 i &= ~IBX_ELD_ADDRESS;
8081 I915_WRITE(aud_cntl_st, i);
8082 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
8083 DRM_DEBUG_DRIVER("port num:%d\n", i);
8084
8085 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
8086 DRM_DEBUG_DRIVER("ELD size %d\n", len);
8087 for (i = 0; i < len; i++)
8088 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
8089
8090 i = I915_READ(aud_cntrl_st2);
8091 i |= eldv;
8092 I915_WRITE(aud_cntrl_st2, i);
8093
8094 }
8095
8096 static void ironlake_write_eld(struct drm_connector *connector,
8097 struct drm_crtc *crtc,
8098 struct drm_display_mode *mode)
8099 {
8100 struct drm_i915_private *dev_priv = connector->dev->dev_private;
8101 uint8_t *eld = connector->eld;
8102 uint32_t eldv;
8103 uint32_t i;
8104 int len;
8105 int hdmiw_hdmiedid;
8106 int aud_config;
8107 int aud_cntl_st;
8108 int aud_cntrl_st2;
8109 int pipe = to_intel_crtc(crtc)->pipe;
8110
8111 if (HAS_PCH_IBX(connector->dev)) {
8112 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
8113 aud_config = IBX_AUD_CFG(pipe);
8114 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
8115 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
8116 } else if (IS_VALLEYVIEW(connector->dev)) {
8117 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
8118 aud_config = VLV_AUD_CFG(pipe);
8119 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
8120 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
8121 } else {
8122 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
8123 aud_config = CPT_AUD_CFG(pipe);
8124 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
8125 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
8126 }
8127
8128 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
8129
8130 if (IS_VALLEYVIEW(connector->dev)) {
8131 struct intel_encoder *intel_encoder;
8132 struct intel_digital_port *intel_dig_port;
8133
8134 intel_encoder = intel_attached_encoder(connector);
8135 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
8136 i = intel_dig_port->port;
8137 } else {
8138 i = I915_READ(aud_cntl_st);
8139 i = (i >> 29) & DIP_PORT_SEL_MASK;
8140 /* DIP_Port_Select, 0x1 = PortB */
8141 }
8142
8143 if (!i) {
8144 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
8145 /* operate blindly on all ports */
8146 eldv = IBX_ELD_VALIDB;
8147 eldv |= IBX_ELD_VALIDB << 4;
8148 eldv |= IBX_ELD_VALIDB << 8;
8149 } else {
8150 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
8151 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
8152 }
8153
8154 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
8155 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
8156 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
8157 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
8158 } else {
8159 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
8160 }
8161
8162 if (intel_eld_uptodate(connector,
8163 aud_cntrl_st2, eldv,
8164 aud_cntl_st, IBX_ELD_ADDRESS,
8165 hdmiw_hdmiedid))
8166 return;
8167
8168 i = I915_READ(aud_cntrl_st2);
8169 i &= ~eldv;
8170 I915_WRITE(aud_cntrl_st2, i);
8171
8172 if (!eld[0])
8173 return;
8174
8175 i = I915_READ(aud_cntl_st);
8176 i &= ~IBX_ELD_ADDRESS;
8177 I915_WRITE(aud_cntl_st, i);
8178
8179 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
8180 DRM_DEBUG_DRIVER("ELD size %d\n", len);
8181 for (i = 0; i < len; i++)
8182 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
8183
8184 i = I915_READ(aud_cntrl_st2);
8185 i |= eldv;
8186 I915_WRITE(aud_cntrl_st2, i);
8187 }
8188
8189 void intel_write_eld(struct drm_encoder *encoder,
8190 struct drm_display_mode *mode)
8191 {
8192 struct drm_crtc *crtc = encoder->crtc;
8193 struct drm_connector *connector;
8194 struct drm_device *dev = encoder->dev;
8195 struct drm_i915_private *dev_priv = dev->dev_private;
8196
8197 connector = drm_select_eld(encoder, mode);
8198 if (!connector)
8199 return;
8200
8201 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8202 connector->base.id,
8203 connector->name,
8204 connector->encoder->base.id,
8205 connector->encoder->name);
8206
8207 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
8208
8209 if (dev_priv->display.write_eld)
8210 dev_priv->display.write_eld(connector, crtc, mode);
8211 }
8212
8213 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8214 {
8215 struct drm_device *dev = crtc->dev;
8216 struct drm_i915_private *dev_priv = dev->dev_private;
8217 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8218 uint32_t cntl = 0, size = 0;
8219
8220 if (base) {
8221 unsigned int width = intel_crtc->cursor_width;
8222 unsigned int height = intel_crtc->cursor_height;
8223 unsigned int stride = roundup_pow_of_two(width) * 4;
8224
8225 switch (stride) {
8226 default:
8227 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8228 width, stride);
8229 stride = 256;
8230 /* fallthrough */
8231 case 256:
8232 case 512:
8233 case 1024:
8234 case 2048:
8235 break;
8236 }
8237
8238 cntl |= CURSOR_ENABLE |
8239 CURSOR_GAMMA_ENABLE |
8240 CURSOR_FORMAT_ARGB |
8241 CURSOR_STRIDE(stride);
8242
8243 size = (height << 12) | width;
8244 }
8245
8246 if (intel_crtc->cursor_cntl != 0 &&
8247 (intel_crtc->cursor_base != base ||
8248 intel_crtc->cursor_size != size ||
8249 intel_crtc->cursor_cntl != cntl)) {
8250 /* On these chipsets we can only modify the base/size/stride
8251 * whilst the cursor is disabled.
8252 */
8253 I915_WRITE(_CURACNTR, 0);
8254 POSTING_READ(_CURACNTR);
8255 intel_crtc->cursor_cntl = 0;
8256 }
8257
8258 if (intel_crtc->cursor_base != base)
8259 I915_WRITE(_CURABASE, base);
8260
8261 if (intel_crtc->cursor_size != size) {
8262 I915_WRITE(CURSIZE, size);
8263 intel_crtc->cursor_size = size;
8264 }
8265
8266 if (intel_crtc->cursor_cntl != cntl) {
8267 I915_WRITE(_CURACNTR, cntl);
8268 POSTING_READ(_CURACNTR);
8269 intel_crtc->cursor_cntl = cntl;
8270 }
8271 }
8272
8273 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8274 {
8275 struct drm_device *dev = crtc->dev;
8276 struct drm_i915_private *dev_priv = dev->dev_private;
8277 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8278 int pipe = intel_crtc->pipe;
8279 uint32_t cntl;
8280
8281 cntl = 0;
8282 if (base) {
8283 cntl = MCURSOR_GAMMA_ENABLE;
8284 switch (intel_crtc->cursor_width) {
8285 case 64:
8286 cntl |= CURSOR_MODE_64_ARGB_AX;
8287 break;
8288 case 128:
8289 cntl |= CURSOR_MODE_128_ARGB_AX;
8290 break;
8291 case 256:
8292 cntl |= CURSOR_MODE_256_ARGB_AX;
8293 break;
8294 default:
8295 WARN_ON(1);
8296 return;
8297 }
8298 cntl |= pipe << 28; /* Connect to correct pipe */
8299 }
8300 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8301 cntl |= CURSOR_PIPE_CSC_ENABLE;
8302
8303 if (intel_crtc->cursor_cntl != cntl) {
8304 I915_WRITE(CURCNTR(pipe), cntl);
8305 POSTING_READ(CURCNTR(pipe));
8306 intel_crtc->cursor_cntl = cntl;
8307 }
8308
8309 /* and commit changes on next vblank */
8310 I915_WRITE(CURBASE(pipe), base);
8311 POSTING_READ(CURBASE(pipe));
8312 }
8313
8314 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8315 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8316 bool on)
8317 {
8318 struct drm_device *dev = crtc->dev;
8319 struct drm_i915_private *dev_priv = dev->dev_private;
8320 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8321 int pipe = intel_crtc->pipe;
8322 int x = crtc->cursor_x;
8323 int y = crtc->cursor_y;
8324 u32 base = 0, pos = 0;
8325
8326 if (on)
8327 base = intel_crtc->cursor_addr;
8328
8329 if (x >= intel_crtc->config.pipe_src_w)
8330 base = 0;
8331
8332 if (y >= intel_crtc->config.pipe_src_h)
8333 base = 0;
8334
8335 if (x < 0) {
8336 if (x + intel_crtc->cursor_width <= 0)
8337 base = 0;
8338
8339 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8340 x = -x;
8341 }
8342 pos |= x << CURSOR_X_SHIFT;
8343
8344 if (y < 0) {
8345 if (y + intel_crtc->cursor_height <= 0)
8346 base = 0;
8347
8348 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8349 y = -y;
8350 }
8351 pos |= y << CURSOR_Y_SHIFT;
8352
8353 if (base == 0 && intel_crtc->cursor_base == 0)
8354 return;
8355
8356 I915_WRITE(CURPOS(pipe), pos);
8357
8358 if (IS_845G(dev) || IS_I865G(dev))
8359 i845_update_cursor(crtc, base);
8360 else
8361 i9xx_update_cursor(crtc, base);
8362 intel_crtc->cursor_base = base;
8363 }
8364
8365 static bool cursor_size_ok(struct drm_device *dev,
8366 uint32_t width, uint32_t height)
8367 {
8368 if (width == 0 || height == 0)
8369 return false;
8370
8371 /*
8372 * 845g/865g are special in that they are only limited by
8373 * the width of their cursors, the height is arbitrary up to
8374 * the precision of the register. Everything else requires
8375 * square cursors, limited to a few power-of-two sizes.
8376 */
8377 if (IS_845G(dev) || IS_I865G(dev)) {
8378 if ((width & 63) != 0)
8379 return false;
8380
8381 if (width > (IS_845G(dev) ? 64 : 512))
8382 return false;
8383
8384 if (height > 1023)
8385 return false;
8386 } else {
8387 switch (width | height) {
8388 case 256:
8389 case 128:
8390 if (IS_GEN2(dev))
8391 return false;
8392 case 64:
8393 break;
8394 default:
8395 return false;
8396 }
8397 }
8398
8399 return true;
8400 }
8401
8402 /*
8403 * intel_crtc_cursor_set_obj - Set cursor to specified GEM object
8404 *
8405 * Note that the object's reference will be consumed if the update fails. If
8406 * the update succeeds, the reference of the old object (if any) will be
8407 * consumed.
8408 */
8409 static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8410 struct drm_i915_gem_object *obj,
8411 uint32_t width, uint32_t height)
8412 {
8413 struct drm_device *dev = crtc->dev;
8414 struct drm_i915_private *dev_priv = dev->dev_private;
8415 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8416 enum pipe pipe = intel_crtc->pipe;
8417 unsigned old_width, stride;
8418 uint32_t addr;
8419 int ret;
8420
8421 /* if we want to turn off the cursor ignore width and height */
8422 if (!obj) {
8423 DRM_DEBUG_KMS("cursor off\n");
8424 addr = 0;
8425 mutex_lock(&dev->struct_mutex);
8426 goto finish;
8427 }
8428
8429 /* Check for which cursor types we support */
8430 if (!cursor_size_ok(dev, width, height)) {
8431 DRM_DEBUG("Cursor dimension not supported\n");
8432 return -EINVAL;
8433 }
8434
8435 stride = roundup_pow_of_two(width) * 4;
8436 if (obj->base.size < stride * height) {
8437 DRM_DEBUG_KMS("buffer is too small\n");
8438 ret = -ENOMEM;
8439 goto fail;
8440 }
8441
8442 /* we only need to pin inside GTT if cursor is non-phy */
8443 mutex_lock(&dev->struct_mutex);
8444 if (!INTEL_INFO(dev)->cursor_needs_physical) {
8445 unsigned alignment;
8446
8447 if (obj->tiling_mode) {
8448 DRM_DEBUG_KMS("cursor cannot be tiled\n");
8449 ret = -EINVAL;
8450 goto fail_locked;
8451 }
8452
8453 /*
8454 * Global gtt pte registers are special registers which actually
8455 * forward writes to a chunk of system memory. Which means that
8456 * there is no risk that the register values disappear as soon
8457 * as we call intel_runtime_pm_put(), so it is correct to wrap
8458 * only the pin/unpin/fence and not more.
8459 */
8460 intel_runtime_pm_get(dev_priv);
8461
8462 /* Note that the w/a also requires 2 PTE of padding following
8463 * the bo. We currently fill all unused PTE with the shadow
8464 * page and so we should always have valid PTE following the
8465 * cursor preventing the VT-d warning.
8466 */
8467 alignment = 0;
8468 if (need_vtd_wa(dev))
8469 alignment = 64*1024;
8470
8471 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8472 if (ret) {
8473 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8474 intel_runtime_pm_put(dev_priv);
8475 goto fail_locked;
8476 }
8477
8478 ret = i915_gem_object_put_fence(obj);
8479 if (ret) {
8480 DRM_DEBUG_KMS("failed to release fence for cursor");
8481 intel_runtime_pm_put(dev_priv);
8482 goto fail_unpin;
8483 }
8484
8485 addr = i915_gem_obj_ggtt_offset(obj);
8486
8487 intel_runtime_pm_put(dev_priv);
8488 } else {
8489 int align = IS_I830(dev) ? 16 * 1024 : 256;
8490 ret = i915_gem_object_attach_phys(obj, align);
8491 if (ret) {
8492 DRM_DEBUG_KMS("failed to attach phys object\n");
8493 goto fail_locked;
8494 }
8495 addr = obj->phys_handle->busaddr;
8496 }
8497
8498 finish:
8499 if (intel_crtc->cursor_bo) {
8500 if (!INTEL_INFO(dev)->cursor_needs_physical)
8501 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8502 }
8503
8504 i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8505 INTEL_FRONTBUFFER_CURSOR(pipe));
8506 mutex_unlock(&dev->struct_mutex);
8507
8508 old_width = intel_crtc->cursor_width;
8509
8510 intel_crtc->cursor_addr = addr;
8511 intel_crtc->cursor_bo = obj;
8512 intel_crtc->cursor_width = width;
8513 intel_crtc->cursor_height = height;
8514
8515 if (intel_crtc->active) {
8516 if (old_width != width)
8517 intel_update_watermarks(crtc);
8518 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8519 }
8520
8521 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
8522
8523 return 0;
8524 fail_unpin:
8525 i915_gem_object_unpin_from_display_plane(obj);
8526 fail_locked:
8527 mutex_unlock(&dev->struct_mutex);
8528 fail:
8529 drm_gem_object_unreference_unlocked(&obj->base);
8530 return ret;
8531 }
8532
8533 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8534 u16 *blue, uint32_t start, uint32_t size)
8535 {
8536 int end = (start + size > 256) ? 256 : start + size, i;
8537 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8538
8539 for (i = start; i < end; i++) {
8540 intel_crtc->lut_r[i] = red[i] >> 8;
8541 intel_crtc->lut_g[i] = green[i] >> 8;
8542 intel_crtc->lut_b[i] = blue[i] >> 8;
8543 }
8544
8545 intel_crtc_load_lut(crtc);
8546 }
8547
8548 /* VESA 640x480x72Hz mode to set on the pipe */
8549 static struct drm_display_mode load_detect_mode = {
8550 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8551 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8552 };
8553
8554 struct drm_framebuffer *
8555 __intel_framebuffer_create(struct drm_device *dev,
8556 struct drm_mode_fb_cmd2 *mode_cmd,
8557 struct drm_i915_gem_object *obj)
8558 {
8559 struct intel_framebuffer *intel_fb;
8560 int ret;
8561
8562 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8563 if (!intel_fb) {
8564 drm_gem_object_unreference_unlocked(&obj->base);
8565 return ERR_PTR(-ENOMEM);
8566 }
8567
8568 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8569 if (ret)
8570 goto err;
8571
8572 return &intel_fb->base;
8573 err:
8574 drm_gem_object_unreference_unlocked(&obj->base);
8575 kfree(intel_fb);
8576
8577 return ERR_PTR(ret);
8578 }
8579
8580 static struct drm_framebuffer *
8581 intel_framebuffer_create(struct drm_device *dev,
8582 struct drm_mode_fb_cmd2 *mode_cmd,
8583 struct drm_i915_gem_object *obj)
8584 {
8585 struct drm_framebuffer *fb;
8586 int ret;
8587
8588 ret = i915_mutex_lock_interruptible(dev);
8589 if (ret)
8590 return ERR_PTR(ret);
8591 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8592 mutex_unlock(&dev->struct_mutex);
8593
8594 return fb;
8595 }
8596
8597 static u32
8598 intel_framebuffer_pitch_for_width(int width, int bpp)
8599 {
8600 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8601 return ALIGN(pitch, 64);
8602 }
8603
8604 static u32
8605 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8606 {
8607 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8608 return PAGE_ALIGN(pitch * mode->vdisplay);
8609 }
8610
8611 static struct drm_framebuffer *
8612 intel_framebuffer_create_for_mode(struct drm_device *dev,
8613 struct drm_display_mode *mode,
8614 int depth, int bpp)
8615 {
8616 struct drm_i915_gem_object *obj;
8617 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8618
8619 obj = i915_gem_alloc_object(dev,
8620 intel_framebuffer_size_for_mode(mode, bpp));
8621 if (obj == NULL)
8622 return ERR_PTR(-ENOMEM);
8623
8624 mode_cmd.width = mode->hdisplay;
8625 mode_cmd.height = mode->vdisplay;
8626 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8627 bpp);
8628 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8629
8630 return intel_framebuffer_create(dev, &mode_cmd, obj);
8631 }
8632
8633 static struct drm_framebuffer *
8634 mode_fits_in_fbdev(struct drm_device *dev,
8635 struct drm_display_mode *mode)
8636 {
8637 #ifdef CONFIG_DRM_I915_FBDEV
8638 struct drm_i915_private *dev_priv = dev->dev_private;
8639 struct drm_i915_gem_object *obj;
8640 struct drm_framebuffer *fb;
8641
8642 if (!dev_priv->fbdev)
8643 return NULL;
8644
8645 if (!dev_priv->fbdev->fb)
8646 return NULL;
8647
8648 obj = dev_priv->fbdev->fb->obj;
8649 BUG_ON(!obj);
8650
8651 fb = &dev_priv->fbdev->fb->base;
8652 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8653 fb->bits_per_pixel))
8654 return NULL;
8655
8656 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8657 return NULL;
8658
8659 return fb;
8660 #else
8661 return NULL;
8662 #endif
8663 }
8664
8665 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8666 struct drm_display_mode *mode,
8667 struct intel_load_detect_pipe *old,
8668 struct drm_modeset_acquire_ctx *ctx)
8669 {
8670 struct intel_crtc *intel_crtc;
8671 struct intel_encoder *intel_encoder =
8672 intel_attached_encoder(connector);
8673 struct drm_crtc *possible_crtc;
8674 struct drm_encoder *encoder = &intel_encoder->base;
8675 struct drm_crtc *crtc = NULL;
8676 struct drm_device *dev = encoder->dev;
8677 struct drm_framebuffer *fb;
8678 struct drm_mode_config *config = &dev->mode_config;
8679 int ret, i = -1;
8680
8681 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8682 connector->base.id, connector->name,
8683 encoder->base.id, encoder->name);
8684
8685 retry:
8686 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8687 if (ret)
8688 goto fail_unlock;
8689
8690 /*
8691 * Algorithm gets a little messy:
8692 *
8693 * - if the connector already has an assigned crtc, use it (but make
8694 * sure it's on first)
8695 *
8696 * - try to find the first unused crtc that can drive this connector,
8697 * and use that if we find one
8698 */
8699
8700 /* See if we already have a CRTC for this connector */
8701 if (encoder->crtc) {
8702 crtc = encoder->crtc;
8703
8704 ret = drm_modeset_lock(&crtc->mutex, ctx);
8705 if (ret)
8706 goto fail_unlock;
8707
8708 old->dpms_mode = connector->dpms;
8709 old->load_detect_temp = false;
8710
8711 /* Make sure the crtc and connector are running */
8712 if (connector->dpms != DRM_MODE_DPMS_ON)
8713 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8714
8715 return true;
8716 }
8717
8718 /* Find an unused one (if possible) */
8719 for_each_crtc(dev, possible_crtc) {
8720 i++;
8721 if (!(encoder->possible_crtcs & (1 << i)))
8722 continue;
8723 if (possible_crtc->enabled)
8724 continue;
8725 /* This can occur when applying the pipe A quirk on resume. */
8726 if (to_intel_crtc(possible_crtc)->new_enabled)
8727 continue;
8728
8729 crtc = possible_crtc;
8730 break;
8731 }
8732
8733 /*
8734 * If we didn't find an unused CRTC, don't use any.
8735 */
8736 if (!crtc) {
8737 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8738 goto fail_unlock;
8739 }
8740
8741 ret = drm_modeset_lock(&crtc->mutex, ctx);
8742 if (ret)
8743 goto fail_unlock;
8744 intel_encoder->new_crtc = to_intel_crtc(crtc);
8745 to_intel_connector(connector)->new_encoder = intel_encoder;
8746
8747 intel_crtc = to_intel_crtc(crtc);
8748 intel_crtc->new_enabled = true;
8749 intel_crtc->new_config = &intel_crtc->config;
8750 old->dpms_mode = connector->dpms;
8751 old->load_detect_temp = true;
8752 old->release_fb = NULL;
8753
8754 if (!mode)
8755 mode = &load_detect_mode;
8756
8757 /* We need a framebuffer large enough to accommodate all accesses
8758 * that the plane may generate whilst we perform load detection.
8759 * We can not rely on the fbcon either being present (we get called
8760 * during its initialisation to detect all boot displays, or it may
8761 * not even exist) or that it is large enough to satisfy the
8762 * requested mode.
8763 */
8764 fb = mode_fits_in_fbdev(dev, mode);
8765 if (fb == NULL) {
8766 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8767 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8768 old->release_fb = fb;
8769 } else
8770 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8771 if (IS_ERR(fb)) {
8772 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8773 goto fail;
8774 }
8775
8776 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8777 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8778 if (old->release_fb)
8779 old->release_fb->funcs->destroy(old->release_fb);
8780 goto fail;
8781 }
8782
8783 /* let the connector get through one full cycle before testing */
8784 intel_wait_for_vblank(dev, intel_crtc->pipe);
8785 return true;
8786
8787 fail:
8788 intel_crtc->new_enabled = crtc->enabled;
8789 if (intel_crtc->new_enabled)
8790 intel_crtc->new_config = &intel_crtc->config;
8791 else
8792 intel_crtc->new_config = NULL;
8793 fail_unlock:
8794 if (ret == -EDEADLK) {
8795 drm_modeset_backoff(ctx);
8796 goto retry;
8797 }
8798
8799 return false;
8800 }
8801
8802 void intel_release_load_detect_pipe(struct drm_connector *connector,
8803 struct intel_load_detect_pipe *old)
8804 {
8805 struct intel_encoder *intel_encoder =
8806 intel_attached_encoder(connector);
8807 struct drm_encoder *encoder = &intel_encoder->base;
8808 struct drm_crtc *crtc = encoder->crtc;
8809 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8810
8811 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8812 connector->base.id, connector->name,
8813 encoder->base.id, encoder->name);
8814
8815 if (old->load_detect_temp) {
8816 to_intel_connector(connector)->new_encoder = NULL;
8817 intel_encoder->new_crtc = NULL;
8818 intel_crtc->new_enabled = false;
8819 intel_crtc->new_config = NULL;
8820 intel_set_mode(crtc, NULL, 0, 0, NULL);
8821
8822 if (old->release_fb) {
8823 drm_framebuffer_unregister_private(old->release_fb);
8824 drm_framebuffer_unreference(old->release_fb);
8825 }
8826
8827 return;
8828 }
8829
8830 /* Switch crtc and encoder back off if necessary */
8831 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8832 connector->funcs->dpms(connector, old->dpms_mode);
8833 }
8834
8835 static int i9xx_pll_refclk(struct drm_device *dev,
8836 const struct intel_crtc_config *pipe_config)
8837 {
8838 struct drm_i915_private *dev_priv = dev->dev_private;
8839 u32 dpll = pipe_config->dpll_hw_state.dpll;
8840
8841 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8842 return dev_priv->vbt.lvds_ssc_freq;
8843 else if (HAS_PCH_SPLIT(dev))
8844 return 120000;
8845 else if (!IS_GEN2(dev))
8846 return 96000;
8847 else
8848 return 48000;
8849 }
8850
8851 /* Returns the clock of the currently programmed mode of the given pipe. */
8852 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8853 struct intel_crtc_config *pipe_config)
8854 {
8855 struct drm_device *dev = crtc->base.dev;
8856 struct drm_i915_private *dev_priv = dev->dev_private;
8857 int pipe = pipe_config->cpu_transcoder;
8858 u32 dpll = pipe_config->dpll_hw_state.dpll;
8859 u32 fp;
8860 intel_clock_t clock;
8861 int refclk = i9xx_pll_refclk(dev, pipe_config);
8862
8863 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8864 fp = pipe_config->dpll_hw_state.fp0;
8865 else
8866 fp = pipe_config->dpll_hw_state.fp1;
8867
8868 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8869 if (IS_PINEVIEW(dev)) {
8870 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8871 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8872 } else {
8873 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8874 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8875 }
8876
8877 if (!IS_GEN2(dev)) {
8878 if (IS_PINEVIEW(dev))
8879 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8880 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8881 else
8882 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8883 DPLL_FPA01_P1_POST_DIV_SHIFT);
8884
8885 switch (dpll & DPLL_MODE_MASK) {
8886 case DPLLB_MODE_DAC_SERIAL:
8887 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8888 5 : 10;
8889 break;
8890 case DPLLB_MODE_LVDS:
8891 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8892 7 : 14;
8893 break;
8894 default:
8895 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8896 "mode\n", (int)(dpll & DPLL_MODE_MASK));
8897 return;
8898 }
8899
8900 if (IS_PINEVIEW(dev))
8901 pineview_clock(refclk, &clock);
8902 else
8903 i9xx_clock(refclk, &clock);
8904 } else {
8905 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8906 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8907
8908 if (is_lvds) {
8909 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8910 DPLL_FPA01_P1_POST_DIV_SHIFT);
8911
8912 if (lvds & LVDS_CLKB_POWER_UP)
8913 clock.p2 = 7;
8914 else
8915 clock.p2 = 14;
8916 } else {
8917 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8918 clock.p1 = 2;
8919 else {
8920 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8921 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8922 }
8923 if (dpll & PLL_P2_DIVIDE_BY_4)
8924 clock.p2 = 4;
8925 else
8926 clock.p2 = 2;
8927 }
8928
8929 i9xx_clock(refclk, &clock);
8930 }
8931
8932 /*
8933 * This value includes pixel_multiplier. We will use
8934 * port_clock to compute adjusted_mode.crtc_clock in the
8935 * encoder's get_config() function.
8936 */
8937 pipe_config->port_clock = clock.dot;
8938 }
8939
8940 int intel_dotclock_calculate(int link_freq,
8941 const struct intel_link_m_n *m_n)
8942 {
8943 /*
8944 * The calculation for the data clock is:
8945 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8946 * But we want to avoid losing precison if possible, so:
8947 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8948 *
8949 * and the link clock is simpler:
8950 * link_clock = (m * link_clock) / n
8951 */
8952
8953 if (!m_n->link_n)
8954 return 0;
8955
8956 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8957 }
8958
8959 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8960 struct intel_crtc_config *pipe_config)
8961 {
8962 struct drm_device *dev = crtc->base.dev;
8963
8964 /* read out port_clock from the DPLL */
8965 i9xx_crtc_clock_get(crtc, pipe_config);
8966
8967 /*
8968 * This value does not include pixel_multiplier.
8969 * We will check that port_clock and adjusted_mode.crtc_clock
8970 * agree once we know their relationship in the encoder's
8971 * get_config() function.
8972 */
8973 pipe_config->adjusted_mode.crtc_clock =
8974 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8975 &pipe_config->fdi_m_n);
8976 }
8977
8978 /** Returns the currently programmed mode of the given pipe. */
8979 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8980 struct drm_crtc *crtc)
8981 {
8982 struct drm_i915_private *dev_priv = dev->dev_private;
8983 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8984 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8985 struct drm_display_mode *mode;
8986 struct intel_crtc_config pipe_config;
8987 int htot = I915_READ(HTOTAL(cpu_transcoder));
8988 int hsync = I915_READ(HSYNC(cpu_transcoder));
8989 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8990 int vsync = I915_READ(VSYNC(cpu_transcoder));
8991 enum pipe pipe = intel_crtc->pipe;
8992
8993 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8994 if (!mode)
8995 return NULL;
8996
8997 /*
8998 * Construct a pipe_config sufficient for getting the clock info
8999 * back out of crtc_clock_get.
9000 *
9001 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9002 * to use a real value here instead.
9003 */
9004 pipe_config.cpu_transcoder = (enum transcoder) pipe;
9005 pipe_config.pixel_multiplier = 1;
9006 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9007 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9008 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
9009 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
9010
9011 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
9012 mode->hdisplay = (htot & 0xffff) + 1;
9013 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9014 mode->hsync_start = (hsync & 0xffff) + 1;
9015 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9016 mode->vdisplay = (vtot & 0xffff) + 1;
9017 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9018 mode->vsync_start = (vsync & 0xffff) + 1;
9019 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9020
9021 drm_mode_set_name(mode);
9022
9023 return mode;
9024 }
9025
9026 static void intel_increase_pllclock(struct drm_device *dev,
9027 enum pipe pipe)
9028 {
9029 struct drm_i915_private *dev_priv = dev->dev_private;
9030 int dpll_reg = DPLL(pipe);
9031 int dpll;
9032
9033 if (!HAS_GMCH_DISPLAY(dev))
9034 return;
9035
9036 if (!dev_priv->lvds_downclock_avail)
9037 return;
9038
9039 dpll = I915_READ(dpll_reg);
9040 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
9041 DRM_DEBUG_DRIVER("upclocking LVDS\n");
9042
9043 assert_panel_unlocked(dev_priv, pipe);
9044
9045 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
9046 I915_WRITE(dpll_reg, dpll);
9047 intel_wait_for_vblank(dev, pipe);
9048
9049 dpll = I915_READ(dpll_reg);
9050 if (dpll & DISPLAY_RATE_SELECT_FPA1)
9051 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
9052 }
9053 }
9054
9055 static void intel_decrease_pllclock(struct drm_crtc *crtc)
9056 {
9057 struct drm_device *dev = crtc->dev;
9058 struct drm_i915_private *dev_priv = dev->dev_private;
9059 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9060
9061 if (!HAS_GMCH_DISPLAY(dev))
9062 return;
9063
9064 if (!dev_priv->lvds_downclock_avail)
9065 return;
9066
9067 /*
9068 * Since this is called by a timer, we should never get here in
9069 * the manual case.
9070 */
9071 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
9072 int pipe = intel_crtc->pipe;
9073 int dpll_reg = DPLL(pipe);
9074 int dpll;
9075
9076 DRM_DEBUG_DRIVER("downclocking LVDS\n");
9077
9078 assert_panel_unlocked(dev_priv, pipe);
9079
9080 dpll = I915_READ(dpll_reg);
9081 dpll |= DISPLAY_RATE_SELECT_FPA1;
9082 I915_WRITE(dpll_reg, dpll);
9083 intel_wait_for_vblank(dev, pipe);
9084 dpll = I915_READ(dpll_reg);
9085 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
9086 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
9087 }
9088
9089 }
9090
9091 void intel_mark_busy(struct drm_device *dev)
9092 {
9093 struct drm_i915_private *dev_priv = dev->dev_private;
9094
9095 if (dev_priv->mm.busy)
9096 return;
9097
9098 intel_runtime_pm_get(dev_priv);
9099 i915_update_gfx_val(dev_priv);
9100 dev_priv->mm.busy = true;
9101 }
9102
9103 void intel_mark_idle(struct drm_device *dev)
9104 {
9105 struct drm_i915_private *dev_priv = dev->dev_private;
9106 struct drm_crtc *crtc;
9107
9108 if (!dev_priv->mm.busy)
9109 return;
9110
9111 dev_priv->mm.busy = false;
9112
9113 if (!i915.powersave)
9114 goto out;
9115
9116 for_each_crtc(dev, crtc) {
9117 if (!crtc->primary->fb)
9118 continue;
9119
9120 intel_decrease_pllclock(crtc);
9121 }
9122
9123 if (INTEL_INFO(dev)->gen >= 6)
9124 gen6_rps_idle(dev->dev_private);
9125
9126 out:
9127 intel_runtime_pm_put(dev_priv);
9128 }
9129
9130
9131 /**
9132 * intel_mark_fb_busy - mark given planes as busy
9133 * @dev: DRM device
9134 * @frontbuffer_bits: bits for the affected planes
9135 * @ring: optional ring for asynchronous commands
9136 *
9137 * This function gets called every time the screen contents change. It can be
9138 * used to keep e.g. the update rate at the nominal refresh rate with DRRS.
9139 */
9140 static void intel_mark_fb_busy(struct drm_device *dev,
9141 unsigned frontbuffer_bits,
9142 struct intel_engine_cs *ring)
9143 {
9144 struct drm_i915_private *dev_priv = dev->dev_private;
9145 enum pipe pipe;
9146
9147 if (!i915.powersave)
9148 return;
9149
9150 for_each_pipe(dev_priv, pipe) {
9151 if (!(frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe)))
9152 continue;
9153
9154 intel_increase_pllclock(dev, pipe);
9155 if (ring && intel_fbc_enabled(dev))
9156 ring->fbc_dirty = true;
9157 }
9158 }
9159
9160 /**
9161 * intel_fb_obj_invalidate - invalidate frontbuffer object
9162 * @obj: GEM object to invalidate
9163 * @ring: set for asynchronous rendering
9164 *
9165 * This function gets called every time rendering on the given object starts and
9166 * frontbuffer caching (fbc, low refresh rate for DRRS, panel self refresh) must
9167 * be invalidated. If @ring is non-NULL any subsequent invalidation will be delayed
9168 * until the rendering completes or a flip on this frontbuffer plane is
9169 * scheduled.
9170 */
9171 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
9172 struct intel_engine_cs *ring)
9173 {
9174 struct drm_device *dev = obj->base.dev;
9175 struct drm_i915_private *dev_priv = dev->dev_private;
9176
9177 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
9178
9179 if (!obj->frontbuffer_bits)
9180 return;
9181
9182 if (ring) {
9183 mutex_lock(&dev_priv->fb_tracking.lock);
9184 dev_priv->fb_tracking.busy_bits
9185 |= obj->frontbuffer_bits;
9186 dev_priv->fb_tracking.flip_bits
9187 &= ~obj->frontbuffer_bits;
9188 mutex_unlock(&dev_priv->fb_tracking.lock);
9189 }
9190
9191 intel_mark_fb_busy(dev, obj->frontbuffer_bits, ring);
9192
9193 intel_edp_psr_invalidate(dev, obj->frontbuffer_bits);
9194 }
9195
9196 /**
9197 * intel_frontbuffer_flush - flush frontbuffer
9198 * @dev: DRM device
9199 * @frontbuffer_bits: frontbuffer plane tracking bits
9200 *
9201 * This function gets called every time rendering on the given planes has
9202 * completed and frontbuffer caching can be started again. Flushes will get
9203 * delayed if they're blocked by some oustanding asynchronous rendering.
9204 *
9205 * Can be called without any locks held.
9206 */
9207 void intel_frontbuffer_flush(struct drm_device *dev,
9208 unsigned frontbuffer_bits)
9209 {
9210 struct drm_i915_private *dev_priv = dev->dev_private;
9211
9212 /* Delay flushing when rings are still busy.*/
9213 mutex_lock(&dev_priv->fb_tracking.lock);
9214 frontbuffer_bits &= ~dev_priv->fb_tracking.busy_bits;
9215 mutex_unlock(&dev_priv->fb_tracking.lock);
9216
9217 intel_mark_fb_busy(dev, frontbuffer_bits, NULL);
9218
9219 intel_edp_psr_flush(dev, frontbuffer_bits);
9220
9221 /*
9222 * FIXME: Unconditional fbc flushing here is a rather gross hack and
9223 * needs to be reworked into a proper frontbuffer tracking scheme like
9224 * psr employs.
9225 */
9226 if (IS_BROADWELL(dev))
9227 gen8_fbc_sw_flush(dev, FBC_REND_CACHE_CLEAN);
9228 }
9229
9230 /**
9231 * intel_fb_obj_flush - flush frontbuffer object
9232 * @obj: GEM object to flush
9233 * @retire: set when retiring asynchronous rendering
9234 *
9235 * This function gets called every time rendering on the given object has
9236 * completed and frontbuffer caching can be started again. If @retire is true
9237 * then any delayed flushes will be unblocked.
9238 */
9239 void intel_fb_obj_flush(struct drm_i915_gem_object *obj,
9240 bool retire)
9241 {
9242 struct drm_device *dev = obj->base.dev;
9243 struct drm_i915_private *dev_priv = dev->dev_private;
9244 unsigned frontbuffer_bits;
9245
9246 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
9247
9248 if (!obj->frontbuffer_bits)
9249 return;
9250
9251 frontbuffer_bits = obj->frontbuffer_bits;
9252
9253 if (retire) {
9254 mutex_lock(&dev_priv->fb_tracking.lock);
9255 /* Filter out new bits since rendering started. */
9256 frontbuffer_bits &= dev_priv->fb_tracking.busy_bits;
9257
9258 dev_priv->fb_tracking.busy_bits &= ~frontbuffer_bits;
9259 mutex_unlock(&dev_priv->fb_tracking.lock);
9260 }
9261
9262 intel_frontbuffer_flush(dev, frontbuffer_bits);
9263 }
9264
9265 /**
9266 * intel_frontbuffer_flip_prepare - prepare asnychronous frontbuffer flip
9267 * @dev: DRM device
9268 * @frontbuffer_bits: frontbuffer plane tracking bits
9269 *
9270 * This function gets called after scheduling a flip on @obj. The actual
9271 * frontbuffer flushing will be delayed until completion is signalled with
9272 * intel_frontbuffer_flip_complete. If an invalidate happens in between this
9273 * flush will be cancelled.
9274 *
9275 * Can be called without any locks held.
9276 */
9277 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
9278 unsigned frontbuffer_bits)
9279 {
9280 struct drm_i915_private *dev_priv = dev->dev_private;
9281
9282 mutex_lock(&dev_priv->fb_tracking.lock);
9283 dev_priv->fb_tracking.flip_bits
9284 |= frontbuffer_bits;
9285 mutex_unlock(&dev_priv->fb_tracking.lock);
9286 }
9287
9288 /**
9289 * intel_frontbuffer_flip_complete - complete asynchronous frontbuffer flush
9290 * @dev: DRM device
9291 * @frontbuffer_bits: frontbuffer plane tracking bits
9292 *
9293 * This function gets called after the flip has been latched and will complete
9294 * on the next vblank. It will execute the fush if it hasn't been cancalled yet.
9295 *
9296 * Can be called without any locks held.
9297 */
9298 void intel_frontbuffer_flip_complete(struct drm_device *dev,
9299 unsigned frontbuffer_bits)
9300 {
9301 struct drm_i915_private *dev_priv = dev->dev_private;
9302
9303 mutex_lock(&dev_priv->fb_tracking.lock);
9304 /* Mask any cancelled flips. */
9305 frontbuffer_bits &= dev_priv->fb_tracking.flip_bits;
9306 dev_priv->fb_tracking.flip_bits &= ~frontbuffer_bits;
9307 mutex_unlock(&dev_priv->fb_tracking.lock);
9308
9309 intel_frontbuffer_flush(dev, frontbuffer_bits);
9310 }
9311
9312 static void intel_crtc_destroy(struct drm_crtc *crtc)
9313 {
9314 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9315 struct drm_device *dev = crtc->dev;
9316 struct intel_unpin_work *work;
9317 unsigned long flags;
9318
9319 spin_lock_irqsave(&dev->event_lock, flags);
9320 work = intel_crtc->unpin_work;
9321 intel_crtc->unpin_work = NULL;
9322 spin_unlock_irqrestore(&dev->event_lock, flags);
9323
9324 if (work) {
9325 cancel_work_sync(&work->work);
9326 kfree(work);
9327 }
9328
9329 drm_crtc_cleanup(crtc);
9330
9331 kfree(intel_crtc);
9332 }
9333
9334 static void intel_unpin_work_fn(struct work_struct *__work)
9335 {
9336 struct intel_unpin_work *work =
9337 container_of(__work, struct intel_unpin_work, work);
9338 struct drm_device *dev = work->crtc->dev;
9339 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9340
9341 mutex_lock(&dev->struct_mutex);
9342 intel_unpin_fb_obj(work->old_fb_obj);
9343 drm_gem_object_unreference(&work->pending_flip_obj->base);
9344 drm_gem_object_unreference(&work->old_fb_obj->base);
9345
9346 intel_update_fbc(dev);
9347 mutex_unlock(&dev->struct_mutex);
9348
9349 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9350
9351 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9352 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9353
9354 kfree(work);
9355 }
9356
9357 static void do_intel_finish_page_flip(struct drm_device *dev,
9358 struct drm_crtc *crtc)
9359 {
9360 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9361 struct intel_unpin_work *work;
9362 unsigned long flags;
9363
9364 /* Ignore early vblank irqs */
9365 if (intel_crtc == NULL)
9366 return;
9367
9368 spin_lock_irqsave(&dev->event_lock, flags);
9369 work = intel_crtc->unpin_work;
9370
9371 /* Ensure we don't miss a work->pending update ... */
9372 smp_rmb();
9373
9374 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9375 spin_unlock_irqrestore(&dev->event_lock, flags);
9376 return;
9377 }
9378
9379 page_flip_completed(intel_crtc);
9380
9381 spin_unlock_irqrestore(&dev->event_lock, flags);
9382 }
9383
9384 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9385 {
9386 struct drm_i915_private *dev_priv = dev->dev_private;
9387 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9388
9389 do_intel_finish_page_flip(dev, crtc);
9390 }
9391
9392 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9393 {
9394 struct drm_i915_private *dev_priv = dev->dev_private;
9395 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9396
9397 do_intel_finish_page_flip(dev, crtc);
9398 }
9399
9400 /* Is 'a' after or equal to 'b'? */
9401 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9402 {
9403 return !((a - b) & 0x80000000);
9404 }
9405
9406 static bool page_flip_finished(struct intel_crtc *crtc)
9407 {
9408 struct drm_device *dev = crtc->base.dev;
9409 struct drm_i915_private *dev_priv = dev->dev_private;
9410
9411 /*
9412 * The relevant registers doen't exist on pre-ctg.
9413 * As the flip done interrupt doesn't trigger for mmio
9414 * flips on gmch platforms, a flip count check isn't
9415 * really needed there. But since ctg has the registers,
9416 * include it in the check anyway.
9417 */
9418 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9419 return true;
9420
9421 /*
9422 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9423 * used the same base address. In that case the mmio flip might
9424 * have completed, but the CS hasn't even executed the flip yet.
9425 *
9426 * A flip count check isn't enough as the CS might have updated
9427 * the base address just after start of vblank, but before we
9428 * managed to process the interrupt. This means we'd complete the
9429 * CS flip too soon.
9430 *
9431 * Combining both checks should get us a good enough result. It may
9432 * still happen that the CS flip has been executed, but has not
9433 * yet actually completed. But in case the base address is the same
9434 * anyway, we don't really care.
9435 */
9436 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9437 crtc->unpin_work->gtt_offset &&
9438 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9439 crtc->unpin_work->flip_count);
9440 }
9441
9442 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9443 {
9444 struct drm_i915_private *dev_priv = dev->dev_private;
9445 struct intel_crtc *intel_crtc =
9446 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9447 unsigned long flags;
9448
9449 /* NB: An MMIO update of the plane base pointer will also
9450 * generate a page-flip completion irq, i.e. every modeset
9451 * is also accompanied by a spurious intel_prepare_page_flip().
9452 */
9453 spin_lock_irqsave(&dev->event_lock, flags);
9454 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9455 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9456 spin_unlock_irqrestore(&dev->event_lock, flags);
9457 }
9458
9459 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9460 {
9461 /* Ensure that the work item is consistent when activating it ... */
9462 smp_wmb();
9463 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9464 /* and that it is marked active as soon as the irq could fire. */
9465 smp_wmb();
9466 }
9467
9468 static int intel_gen2_queue_flip(struct drm_device *dev,
9469 struct drm_crtc *crtc,
9470 struct drm_framebuffer *fb,
9471 struct drm_i915_gem_object *obj,
9472 struct intel_engine_cs *ring,
9473 uint32_t flags)
9474 {
9475 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9476 u32 flip_mask;
9477 int ret;
9478
9479 ret = intel_ring_begin(ring, 6);
9480 if (ret)
9481 return ret;
9482
9483 /* Can't queue multiple flips, so wait for the previous
9484 * one to finish before executing the next.
9485 */
9486 if (intel_crtc->plane)
9487 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9488 else
9489 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9490 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9491 intel_ring_emit(ring, MI_NOOP);
9492 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9493 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9494 intel_ring_emit(ring, fb->pitches[0]);
9495 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9496 intel_ring_emit(ring, 0); /* aux display base address, unused */
9497
9498 intel_mark_page_flip_active(intel_crtc);
9499 __intel_ring_advance(ring);
9500 return 0;
9501 }
9502
9503 static int intel_gen3_queue_flip(struct drm_device *dev,
9504 struct drm_crtc *crtc,
9505 struct drm_framebuffer *fb,
9506 struct drm_i915_gem_object *obj,
9507 struct intel_engine_cs *ring,
9508 uint32_t flags)
9509 {
9510 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9511 u32 flip_mask;
9512 int ret;
9513
9514 ret = intel_ring_begin(ring, 6);
9515 if (ret)
9516 return ret;
9517
9518 if (intel_crtc->plane)
9519 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9520 else
9521 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9522 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9523 intel_ring_emit(ring, MI_NOOP);
9524 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9525 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9526 intel_ring_emit(ring, fb->pitches[0]);
9527 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9528 intel_ring_emit(ring, MI_NOOP);
9529
9530 intel_mark_page_flip_active(intel_crtc);
9531 __intel_ring_advance(ring);
9532 return 0;
9533 }
9534
9535 static int intel_gen4_queue_flip(struct drm_device *dev,
9536 struct drm_crtc *crtc,
9537 struct drm_framebuffer *fb,
9538 struct drm_i915_gem_object *obj,
9539 struct intel_engine_cs *ring,
9540 uint32_t flags)
9541 {
9542 struct drm_i915_private *dev_priv = dev->dev_private;
9543 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9544 uint32_t pf, pipesrc;
9545 int ret;
9546
9547 ret = intel_ring_begin(ring, 4);
9548 if (ret)
9549 return ret;
9550
9551 /* i965+ uses the linear or tiled offsets from the
9552 * Display Registers (which do not change across a page-flip)
9553 * so we need only reprogram the base address.
9554 */
9555 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9556 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9557 intel_ring_emit(ring, fb->pitches[0]);
9558 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9559 obj->tiling_mode);
9560
9561 /* XXX Enabling the panel-fitter across page-flip is so far
9562 * untested on non-native modes, so ignore it for now.
9563 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9564 */
9565 pf = 0;
9566 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9567 intel_ring_emit(ring, pf | pipesrc);
9568
9569 intel_mark_page_flip_active(intel_crtc);
9570 __intel_ring_advance(ring);
9571 return 0;
9572 }
9573
9574 static int intel_gen6_queue_flip(struct drm_device *dev,
9575 struct drm_crtc *crtc,
9576 struct drm_framebuffer *fb,
9577 struct drm_i915_gem_object *obj,
9578 struct intel_engine_cs *ring,
9579 uint32_t flags)
9580 {
9581 struct drm_i915_private *dev_priv = dev->dev_private;
9582 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9583 uint32_t pf, pipesrc;
9584 int ret;
9585
9586 ret = intel_ring_begin(ring, 4);
9587 if (ret)
9588 return ret;
9589
9590 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9591 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9592 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9593 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9594
9595 /* Contrary to the suggestions in the documentation,
9596 * "Enable Panel Fitter" does not seem to be required when page
9597 * flipping with a non-native mode, and worse causes a normal
9598 * modeset to fail.
9599 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9600 */
9601 pf = 0;
9602 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9603 intel_ring_emit(ring, pf | pipesrc);
9604
9605 intel_mark_page_flip_active(intel_crtc);
9606 __intel_ring_advance(ring);
9607 return 0;
9608 }
9609
9610 static int intel_gen7_queue_flip(struct drm_device *dev,
9611 struct drm_crtc *crtc,
9612 struct drm_framebuffer *fb,
9613 struct drm_i915_gem_object *obj,
9614 struct intel_engine_cs *ring,
9615 uint32_t flags)
9616 {
9617 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9618 uint32_t plane_bit = 0;
9619 int len, ret;
9620
9621 switch (intel_crtc->plane) {
9622 case PLANE_A:
9623 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9624 break;
9625 case PLANE_B:
9626 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9627 break;
9628 case PLANE_C:
9629 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9630 break;
9631 default:
9632 WARN_ONCE(1, "unknown plane in flip command\n");
9633 return -ENODEV;
9634 }
9635
9636 len = 4;
9637 if (ring->id == RCS) {
9638 len += 6;
9639 /*
9640 * On Gen 8, SRM is now taking an extra dword to accommodate
9641 * 48bits addresses, and we need a NOOP for the batch size to
9642 * stay even.
9643 */
9644 if (IS_GEN8(dev))
9645 len += 2;
9646 }
9647
9648 /*
9649 * BSpec MI_DISPLAY_FLIP for IVB:
9650 * "The full packet must be contained within the same cache line."
9651 *
9652 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9653 * cacheline, if we ever start emitting more commands before
9654 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9655 * then do the cacheline alignment, and finally emit the
9656 * MI_DISPLAY_FLIP.
9657 */
9658 ret = intel_ring_cacheline_align(ring);
9659 if (ret)
9660 return ret;
9661
9662 ret = intel_ring_begin(ring, len);
9663 if (ret)
9664 return ret;
9665
9666 /* Unmask the flip-done completion message. Note that the bspec says that
9667 * we should do this for both the BCS and RCS, and that we must not unmask
9668 * more than one flip event at any time (or ensure that one flip message
9669 * can be sent by waiting for flip-done prior to queueing new flips).
9670 * Experimentation says that BCS works despite DERRMR masking all
9671 * flip-done completion events and that unmasking all planes at once
9672 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9673 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9674 */
9675 if (ring->id == RCS) {
9676 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9677 intel_ring_emit(ring, DERRMR);
9678 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9679 DERRMR_PIPEB_PRI_FLIP_DONE |
9680 DERRMR_PIPEC_PRI_FLIP_DONE));
9681 if (IS_GEN8(dev))
9682 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9683 MI_SRM_LRM_GLOBAL_GTT);
9684 else
9685 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9686 MI_SRM_LRM_GLOBAL_GTT);
9687 intel_ring_emit(ring, DERRMR);
9688 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9689 if (IS_GEN8(dev)) {
9690 intel_ring_emit(ring, 0);
9691 intel_ring_emit(ring, MI_NOOP);
9692 }
9693 }
9694
9695 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9696 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9697 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9698 intel_ring_emit(ring, (MI_NOOP));
9699
9700 intel_mark_page_flip_active(intel_crtc);
9701 __intel_ring_advance(ring);
9702 return 0;
9703 }
9704
9705 static bool use_mmio_flip(struct intel_engine_cs *ring,
9706 struct drm_i915_gem_object *obj)
9707 {
9708 /*
9709 * This is not being used for older platforms, because
9710 * non-availability of flip done interrupt forces us to use
9711 * CS flips. Older platforms derive flip done using some clever
9712 * tricks involving the flip_pending status bits and vblank irqs.
9713 * So using MMIO flips there would disrupt this mechanism.
9714 */
9715
9716 if (ring == NULL)
9717 return true;
9718
9719 if (INTEL_INFO(ring->dev)->gen < 5)
9720 return false;
9721
9722 if (i915.use_mmio_flip < 0)
9723 return false;
9724 else if (i915.use_mmio_flip > 0)
9725 return true;
9726 else if (i915.enable_execlists)
9727 return true;
9728 else
9729 return ring != obj->ring;
9730 }
9731
9732 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9733 {
9734 struct drm_device *dev = intel_crtc->base.dev;
9735 struct drm_i915_private *dev_priv = dev->dev_private;
9736 struct intel_framebuffer *intel_fb =
9737 to_intel_framebuffer(intel_crtc->base.primary->fb);
9738 struct drm_i915_gem_object *obj = intel_fb->obj;
9739 u32 dspcntr;
9740 u32 reg;
9741
9742 intel_mark_page_flip_active(intel_crtc);
9743
9744 reg = DSPCNTR(intel_crtc->plane);
9745 dspcntr = I915_READ(reg);
9746
9747 if (INTEL_INFO(dev)->gen >= 4) {
9748 if (obj->tiling_mode != I915_TILING_NONE)
9749 dspcntr |= DISPPLANE_TILED;
9750 else
9751 dspcntr &= ~DISPPLANE_TILED;
9752 }
9753 I915_WRITE(reg, dspcntr);
9754
9755 I915_WRITE(DSPSURF(intel_crtc->plane),
9756 intel_crtc->unpin_work->gtt_offset);
9757 POSTING_READ(DSPSURF(intel_crtc->plane));
9758 }
9759
9760 static int intel_postpone_flip(struct drm_i915_gem_object *obj)
9761 {
9762 struct intel_engine_cs *ring;
9763 int ret;
9764
9765 lockdep_assert_held(&obj->base.dev->struct_mutex);
9766
9767 if (!obj->last_write_seqno)
9768 return 0;
9769
9770 ring = obj->ring;
9771
9772 if (i915_seqno_passed(ring->get_seqno(ring, true),
9773 obj->last_write_seqno))
9774 return 0;
9775
9776 ret = i915_gem_check_olr(ring, obj->last_write_seqno);
9777 if (ret)
9778 return ret;
9779
9780 if (WARN_ON(!ring->irq_get(ring)))
9781 return 0;
9782
9783 return 1;
9784 }
9785
9786 void intel_notify_mmio_flip(struct intel_engine_cs *ring)
9787 {
9788 struct drm_i915_private *dev_priv = to_i915(ring->dev);
9789 struct intel_crtc *intel_crtc;
9790 unsigned long irq_flags;
9791 u32 seqno;
9792
9793 seqno = ring->get_seqno(ring, false);
9794
9795 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9796 for_each_intel_crtc(ring->dev, intel_crtc) {
9797 struct intel_mmio_flip *mmio_flip;
9798
9799 mmio_flip = &intel_crtc->mmio_flip;
9800 if (mmio_flip->seqno == 0)
9801 continue;
9802
9803 if (ring->id != mmio_flip->ring_id)
9804 continue;
9805
9806 if (i915_seqno_passed(seqno, mmio_flip->seqno)) {
9807 intel_do_mmio_flip(intel_crtc);
9808 mmio_flip->seqno = 0;
9809 ring->irq_put(ring);
9810 }
9811 }
9812 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9813 }
9814
9815 static int intel_queue_mmio_flip(struct drm_device *dev,
9816 struct drm_crtc *crtc,
9817 struct drm_framebuffer *fb,
9818 struct drm_i915_gem_object *obj,
9819 struct intel_engine_cs *ring,
9820 uint32_t flags)
9821 {
9822 struct drm_i915_private *dev_priv = dev->dev_private;
9823 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9824 unsigned long irq_flags;
9825 int ret;
9826
9827 if (WARN_ON(intel_crtc->mmio_flip.seqno))
9828 return -EBUSY;
9829
9830 ret = intel_postpone_flip(obj);
9831 if (ret < 0)
9832 return ret;
9833 if (ret == 0) {
9834 intel_do_mmio_flip(intel_crtc);
9835 return 0;
9836 }
9837
9838 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9839 intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
9840 intel_crtc->mmio_flip.ring_id = obj->ring->id;
9841 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9842
9843 /*
9844 * Double check to catch cases where irq fired before
9845 * mmio flip data was ready
9846 */
9847 intel_notify_mmio_flip(obj->ring);
9848 return 0;
9849 }
9850
9851 static int intel_default_queue_flip(struct drm_device *dev,
9852 struct drm_crtc *crtc,
9853 struct drm_framebuffer *fb,
9854 struct drm_i915_gem_object *obj,
9855 struct intel_engine_cs *ring,
9856 uint32_t flags)
9857 {
9858 return -ENODEV;
9859 }
9860
9861 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9862 struct drm_crtc *crtc)
9863 {
9864 struct drm_i915_private *dev_priv = dev->dev_private;
9865 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9866 struct intel_unpin_work *work = intel_crtc->unpin_work;
9867 u32 addr;
9868
9869 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9870 return true;
9871
9872 if (!work->enable_stall_check)
9873 return false;
9874
9875 if (work->flip_ready_vblank == 0) {
9876 if (work->flip_queued_ring &&
9877 !i915_seqno_passed(work->flip_queued_ring->get_seqno(work->flip_queued_ring, true),
9878 work->flip_queued_seqno))
9879 return false;
9880
9881 work->flip_ready_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9882 }
9883
9884 if (drm_vblank_count(dev, intel_crtc->pipe) - work->flip_ready_vblank < 3)
9885 return false;
9886
9887 /* Potential stall - if we see that the flip has happened,
9888 * assume a missed interrupt. */
9889 if (INTEL_INFO(dev)->gen >= 4)
9890 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9891 else
9892 addr = I915_READ(DSPADDR(intel_crtc->plane));
9893
9894 /* There is a potential issue here with a false positive after a flip
9895 * to the same address. We could address this by checking for a
9896 * non-incrementing frame counter.
9897 */
9898 return addr == work->gtt_offset;
9899 }
9900
9901 void intel_check_page_flip(struct drm_device *dev, int pipe)
9902 {
9903 struct drm_i915_private *dev_priv = dev->dev_private;
9904 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9905 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9906 unsigned long flags;
9907
9908 if (crtc == NULL)
9909 return;
9910
9911 spin_lock_irqsave(&dev->event_lock, flags);
9912 if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9913 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9914 intel_crtc->unpin_work->flip_queued_vblank, drm_vblank_count(dev, pipe));
9915 page_flip_completed(intel_crtc);
9916 }
9917 spin_unlock_irqrestore(&dev->event_lock, flags);
9918 }
9919
9920 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9921 struct drm_framebuffer *fb,
9922 struct drm_pending_vblank_event *event,
9923 uint32_t page_flip_flags)
9924 {
9925 struct drm_device *dev = crtc->dev;
9926 struct drm_i915_private *dev_priv = dev->dev_private;
9927 struct drm_framebuffer *old_fb = crtc->primary->fb;
9928 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9929 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9930 enum pipe pipe = intel_crtc->pipe;
9931 struct intel_unpin_work *work;
9932 struct intel_engine_cs *ring;
9933 unsigned long flags;
9934 int ret;
9935
9936 /*
9937 * drm_mode_page_flip_ioctl() should already catch this, but double
9938 * check to be safe. In the future we may enable pageflipping from
9939 * a disabled primary plane.
9940 */
9941 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9942 return -EBUSY;
9943
9944 /* Can't change pixel format via MI display flips. */
9945 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9946 return -EINVAL;
9947
9948 /*
9949 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9950 * Note that pitch changes could also affect these register.
9951 */
9952 if (INTEL_INFO(dev)->gen > 3 &&
9953 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9954 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9955 return -EINVAL;
9956
9957 if (i915_terminally_wedged(&dev_priv->gpu_error))
9958 goto out_hang;
9959
9960 work = kzalloc(sizeof(*work), GFP_KERNEL);
9961 if (work == NULL)
9962 return -ENOMEM;
9963
9964 work->event = event;
9965 work->crtc = crtc;
9966 work->old_fb_obj = intel_fb_obj(old_fb);
9967 INIT_WORK(&work->work, intel_unpin_work_fn);
9968
9969 ret = drm_crtc_vblank_get(crtc);
9970 if (ret)
9971 goto free_work;
9972
9973 /* We borrow the event spin lock for protecting unpin_work */
9974 spin_lock_irqsave(&dev->event_lock, flags);
9975 if (intel_crtc->unpin_work) {
9976 /* Before declaring the flip queue wedged, check if
9977 * the hardware completed the operation behind our backs.
9978 */
9979 if (__intel_pageflip_stall_check(dev, crtc)) {
9980 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9981 page_flip_completed(intel_crtc);
9982 } else {
9983 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9984 spin_unlock_irqrestore(&dev->event_lock, flags);
9985
9986 drm_crtc_vblank_put(crtc);
9987 kfree(work);
9988 return -EBUSY;
9989 }
9990 }
9991 intel_crtc->unpin_work = work;
9992 spin_unlock_irqrestore(&dev->event_lock, flags);
9993
9994 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9995 flush_workqueue(dev_priv->wq);
9996
9997 ret = i915_mutex_lock_interruptible(dev);
9998 if (ret)
9999 goto cleanup;
10000
10001 /* Reference the objects for the scheduled work. */
10002 drm_gem_object_reference(&work->old_fb_obj->base);
10003 drm_gem_object_reference(&obj->base);
10004
10005 crtc->primary->fb = fb;
10006
10007 work->pending_flip_obj = obj;
10008
10009 atomic_inc(&intel_crtc->unpin_work_count);
10010 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
10011
10012 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
10013 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
10014
10015 if (IS_VALLEYVIEW(dev)) {
10016 ring = &dev_priv->ring[BCS];
10017 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
10018 /* vlv: DISPLAY_FLIP fails to change tiling */
10019 ring = NULL;
10020 } else if (IS_IVYBRIDGE(dev)) {
10021 ring = &dev_priv->ring[BCS];
10022 } else if (INTEL_INFO(dev)->gen >= 7) {
10023 ring = obj->ring;
10024 if (ring == NULL || ring->id != RCS)
10025 ring = &dev_priv->ring[BCS];
10026 } else {
10027 ring = &dev_priv->ring[RCS];
10028 }
10029
10030 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
10031 if (ret)
10032 goto cleanup_pending;
10033
10034 work->gtt_offset =
10035 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
10036
10037 if (use_mmio_flip(ring, obj)) {
10038 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
10039 page_flip_flags);
10040 if (ret)
10041 goto cleanup_unpin;
10042
10043 work->flip_queued_seqno = obj->last_write_seqno;
10044 work->flip_queued_ring = obj->ring;
10045 } else {
10046 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
10047 page_flip_flags);
10048 if (ret)
10049 goto cleanup_unpin;
10050
10051 work->flip_queued_seqno = intel_ring_get_seqno(ring);
10052 work->flip_queued_ring = ring;
10053 }
10054
10055 work->flip_queued_vblank = drm_vblank_count(dev, intel_crtc->pipe);
10056 work->enable_stall_check = true;
10057
10058 i915_gem_track_fb(work->old_fb_obj, obj,
10059 INTEL_FRONTBUFFER_PRIMARY(pipe));
10060
10061 intel_disable_fbc(dev);
10062 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
10063 mutex_unlock(&dev->struct_mutex);
10064
10065 trace_i915_flip_request(intel_crtc->plane, obj);
10066
10067 return 0;
10068
10069 cleanup_unpin:
10070 intel_unpin_fb_obj(obj);
10071 cleanup_pending:
10072 atomic_dec(&intel_crtc->unpin_work_count);
10073 crtc->primary->fb = old_fb;
10074 drm_gem_object_unreference(&work->old_fb_obj->base);
10075 drm_gem_object_unreference(&obj->base);
10076 mutex_unlock(&dev->struct_mutex);
10077
10078 cleanup:
10079 spin_lock_irqsave(&dev->event_lock, flags);
10080 intel_crtc->unpin_work = NULL;
10081 spin_unlock_irqrestore(&dev->event_lock, flags);
10082
10083 drm_crtc_vblank_put(crtc);
10084 free_work:
10085 kfree(work);
10086
10087 if (ret == -EIO) {
10088 out_hang:
10089 intel_crtc_wait_for_pending_flips(crtc);
10090 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
10091 if (ret == 0 && event) {
10092 spin_lock_irqsave(&dev->event_lock, flags);
10093 drm_send_vblank_event(dev, pipe, event);
10094 spin_unlock_irqrestore(&dev->event_lock, flags);
10095 }
10096 }
10097 return ret;
10098 }
10099
10100 static struct drm_crtc_helper_funcs intel_helper_funcs = {
10101 .mode_set_base_atomic = intel_pipe_set_base_atomic,
10102 .load_lut = intel_crtc_load_lut,
10103 };
10104
10105 /**
10106 * intel_modeset_update_staged_output_state
10107 *
10108 * Updates the staged output configuration state, e.g. after we've read out the
10109 * current hw state.
10110 */
10111 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
10112 {
10113 struct intel_crtc *crtc;
10114 struct intel_encoder *encoder;
10115 struct intel_connector *connector;
10116
10117 list_for_each_entry(connector, &dev->mode_config.connector_list,
10118 base.head) {
10119 connector->new_encoder =
10120 to_intel_encoder(connector->base.encoder);
10121 }
10122
10123 for_each_intel_encoder(dev, encoder) {
10124 encoder->new_crtc =
10125 to_intel_crtc(encoder->base.crtc);
10126 }
10127
10128 for_each_intel_crtc(dev, crtc) {
10129 crtc->new_enabled = crtc->base.enabled;
10130
10131 if (crtc->new_enabled)
10132 crtc->new_config = &crtc->config;
10133 else
10134 crtc->new_config = NULL;
10135 }
10136 }
10137
10138 /**
10139 * intel_modeset_commit_output_state
10140 *
10141 * This function copies the stage display pipe configuration to the real one.
10142 */
10143 static void intel_modeset_commit_output_state(struct drm_device *dev)
10144 {
10145 struct intel_crtc *crtc;
10146 struct intel_encoder *encoder;
10147 struct intel_connector *connector;
10148
10149 list_for_each_entry(connector, &dev->mode_config.connector_list,
10150 base.head) {
10151 connector->base.encoder = &connector->new_encoder->base;
10152 }
10153
10154 for_each_intel_encoder(dev, encoder) {
10155 encoder->base.crtc = &encoder->new_crtc->base;
10156 }
10157
10158 for_each_intel_crtc(dev, crtc) {
10159 crtc->base.enabled = crtc->new_enabled;
10160 }
10161 }
10162
10163 static void
10164 connected_sink_compute_bpp(struct intel_connector *connector,
10165 struct intel_crtc_config *pipe_config)
10166 {
10167 int bpp = pipe_config->pipe_bpp;
10168
10169 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10170 connector->base.base.id,
10171 connector->base.name);
10172
10173 /* Don't use an invalid EDID bpc value */
10174 if (connector->base.display_info.bpc &&
10175 connector->base.display_info.bpc * 3 < bpp) {
10176 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10177 bpp, connector->base.display_info.bpc*3);
10178 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
10179 }
10180
10181 /* Clamp bpp to 8 on screens without EDID 1.4 */
10182 if (connector->base.display_info.bpc == 0 && bpp > 24) {
10183 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10184 bpp);
10185 pipe_config->pipe_bpp = 24;
10186 }
10187 }
10188
10189 static int
10190 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10191 struct drm_framebuffer *fb,
10192 struct intel_crtc_config *pipe_config)
10193 {
10194 struct drm_device *dev = crtc->base.dev;
10195 struct intel_connector *connector;
10196 int bpp;
10197
10198 switch (fb->pixel_format) {
10199 case DRM_FORMAT_C8:
10200 bpp = 8*3; /* since we go through a colormap */
10201 break;
10202 case DRM_FORMAT_XRGB1555:
10203 case DRM_FORMAT_ARGB1555:
10204 /* checked in intel_framebuffer_init already */
10205 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10206 return -EINVAL;
10207 case DRM_FORMAT_RGB565:
10208 bpp = 6*3; /* min is 18bpp */
10209 break;
10210 case DRM_FORMAT_XBGR8888:
10211 case DRM_FORMAT_ABGR8888:
10212 /* checked in intel_framebuffer_init already */
10213 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10214 return -EINVAL;
10215 case DRM_FORMAT_XRGB8888:
10216 case DRM_FORMAT_ARGB8888:
10217 bpp = 8*3;
10218 break;
10219 case DRM_FORMAT_XRGB2101010:
10220 case DRM_FORMAT_ARGB2101010:
10221 case DRM_FORMAT_XBGR2101010:
10222 case DRM_FORMAT_ABGR2101010:
10223 /* checked in intel_framebuffer_init already */
10224 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10225 return -EINVAL;
10226 bpp = 10*3;
10227 break;
10228 /* TODO: gen4+ supports 16 bpc floating point, too. */
10229 default:
10230 DRM_DEBUG_KMS("unsupported depth\n");
10231 return -EINVAL;
10232 }
10233
10234 pipe_config->pipe_bpp = bpp;
10235
10236 /* Clamp display bpp to EDID value */
10237 list_for_each_entry(connector, &dev->mode_config.connector_list,
10238 base.head) {
10239 if (!connector->new_encoder ||
10240 connector->new_encoder->new_crtc != crtc)
10241 continue;
10242
10243 connected_sink_compute_bpp(connector, pipe_config);
10244 }
10245
10246 return bpp;
10247 }
10248
10249 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10250 {
10251 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10252 "type: 0x%x flags: 0x%x\n",
10253 mode->crtc_clock,
10254 mode->crtc_hdisplay, mode->crtc_hsync_start,
10255 mode->crtc_hsync_end, mode->crtc_htotal,
10256 mode->crtc_vdisplay, mode->crtc_vsync_start,
10257 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10258 }
10259
10260 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10261 struct intel_crtc_config *pipe_config,
10262 const char *context)
10263 {
10264 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10265 context, pipe_name(crtc->pipe));
10266
10267 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10268 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10269 pipe_config->pipe_bpp, pipe_config->dither);
10270 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10271 pipe_config->has_pch_encoder,
10272 pipe_config->fdi_lanes,
10273 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10274 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10275 pipe_config->fdi_m_n.tu);
10276 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10277 pipe_config->has_dp_encoder,
10278 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10279 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10280 pipe_config->dp_m_n.tu);
10281
10282 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10283 pipe_config->has_dp_encoder,
10284 pipe_config->dp_m2_n2.gmch_m,
10285 pipe_config->dp_m2_n2.gmch_n,
10286 pipe_config->dp_m2_n2.link_m,
10287 pipe_config->dp_m2_n2.link_n,
10288 pipe_config->dp_m2_n2.tu);
10289
10290 DRM_DEBUG_KMS("requested mode:\n");
10291 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
10292 DRM_DEBUG_KMS("adjusted mode:\n");
10293 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
10294 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
10295 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10296 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10297 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10298 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10299 pipe_config->gmch_pfit.control,
10300 pipe_config->gmch_pfit.pgm_ratios,
10301 pipe_config->gmch_pfit.lvds_border_bits);
10302 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10303 pipe_config->pch_pfit.pos,
10304 pipe_config->pch_pfit.size,
10305 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10306 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10307 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10308 }
10309
10310 static bool encoders_cloneable(const struct intel_encoder *a,
10311 const struct intel_encoder *b)
10312 {
10313 /* masks could be asymmetric, so check both ways */
10314 return a == b || (a->cloneable & (1 << b->type) &&
10315 b->cloneable & (1 << a->type));
10316 }
10317
10318 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10319 struct intel_encoder *encoder)
10320 {
10321 struct drm_device *dev = crtc->base.dev;
10322 struct intel_encoder *source_encoder;
10323
10324 for_each_intel_encoder(dev, source_encoder) {
10325 if (source_encoder->new_crtc != crtc)
10326 continue;
10327
10328 if (!encoders_cloneable(encoder, source_encoder))
10329 return false;
10330 }
10331
10332 return true;
10333 }
10334
10335 static bool check_encoder_cloning(struct intel_crtc *crtc)
10336 {
10337 struct drm_device *dev = crtc->base.dev;
10338 struct intel_encoder *encoder;
10339
10340 for_each_intel_encoder(dev, encoder) {
10341 if (encoder->new_crtc != crtc)
10342 continue;
10343
10344 if (!check_single_encoder_cloning(crtc, encoder))
10345 return false;
10346 }
10347
10348 return true;
10349 }
10350
10351 static struct intel_crtc_config *
10352 intel_modeset_pipe_config(struct drm_crtc *crtc,
10353 struct drm_framebuffer *fb,
10354 struct drm_display_mode *mode)
10355 {
10356 struct drm_device *dev = crtc->dev;
10357 struct intel_encoder *encoder;
10358 struct intel_crtc_config *pipe_config;
10359 int plane_bpp, ret = -EINVAL;
10360 bool retry = true;
10361
10362 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10363 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10364 return ERR_PTR(-EINVAL);
10365 }
10366
10367 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10368 if (!pipe_config)
10369 return ERR_PTR(-ENOMEM);
10370
10371 drm_mode_copy(&pipe_config->adjusted_mode, mode);
10372 drm_mode_copy(&pipe_config->requested_mode, mode);
10373
10374 pipe_config->cpu_transcoder =
10375 (enum transcoder) to_intel_crtc(crtc)->pipe;
10376 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10377
10378 /*
10379 * Sanitize sync polarity flags based on requested ones. If neither
10380 * positive or negative polarity is requested, treat this as meaning
10381 * negative polarity.
10382 */
10383 if (!(pipe_config->adjusted_mode.flags &
10384 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10385 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10386
10387 if (!(pipe_config->adjusted_mode.flags &
10388 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10389 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10390
10391 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10392 * plane pixel format and any sink constraints into account. Returns the
10393 * source plane bpp so that dithering can be selected on mismatches
10394 * after encoders and crtc also have had their say. */
10395 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10396 fb, pipe_config);
10397 if (plane_bpp < 0)
10398 goto fail;
10399
10400 /*
10401 * Determine the real pipe dimensions. Note that stereo modes can
10402 * increase the actual pipe size due to the frame doubling and
10403 * insertion of additional space for blanks between the frame. This
10404 * is stored in the crtc timings. We use the requested mode to do this
10405 * computation to clearly distinguish it from the adjusted mode, which
10406 * can be changed by the connectors in the below retry loop.
10407 */
10408 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
10409 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
10410 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
10411
10412 encoder_retry:
10413 /* Ensure the port clock defaults are reset when retrying. */
10414 pipe_config->port_clock = 0;
10415 pipe_config->pixel_multiplier = 1;
10416
10417 /* Fill in default crtc timings, allow encoders to overwrite them. */
10418 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
10419
10420 /* Pass our mode to the connectors and the CRTC to give them a chance to
10421 * adjust it according to limitations or connector properties, and also
10422 * a chance to reject the mode entirely.
10423 */
10424 for_each_intel_encoder(dev, encoder) {
10425
10426 if (&encoder->new_crtc->base != crtc)
10427 continue;
10428
10429 if (!(encoder->compute_config(encoder, pipe_config))) {
10430 DRM_DEBUG_KMS("Encoder config failure\n");
10431 goto fail;
10432 }
10433 }
10434
10435 /* Set default port clock if not overwritten by the encoder. Needs to be
10436 * done afterwards in case the encoder adjusts the mode. */
10437 if (!pipe_config->port_clock)
10438 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10439 * pipe_config->pixel_multiplier;
10440
10441 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10442 if (ret < 0) {
10443 DRM_DEBUG_KMS("CRTC fixup failed\n");
10444 goto fail;
10445 }
10446
10447 if (ret == RETRY) {
10448 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10449 ret = -EINVAL;
10450 goto fail;
10451 }
10452
10453 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10454 retry = false;
10455 goto encoder_retry;
10456 }
10457
10458 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10459 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10460 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10461
10462 return pipe_config;
10463 fail:
10464 kfree(pipe_config);
10465 return ERR_PTR(ret);
10466 }
10467
10468 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10469 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10470 static void
10471 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10472 unsigned *prepare_pipes, unsigned *disable_pipes)
10473 {
10474 struct intel_crtc *intel_crtc;
10475 struct drm_device *dev = crtc->dev;
10476 struct intel_encoder *encoder;
10477 struct intel_connector *connector;
10478 struct drm_crtc *tmp_crtc;
10479
10480 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10481
10482 /* Check which crtcs have changed outputs connected to them, these need
10483 * to be part of the prepare_pipes mask. We don't (yet) support global
10484 * modeset across multiple crtcs, so modeset_pipes will only have one
10485 * bit set at most. */
10486 list_for_each_entry(connector, &dev->mode_config.connector_list,
10487 base.head) {
10488 if (connector->base.encoder == &connector->new_encoder->base)
10489 continue;
10490
10491 if (connector->base.encoder) {
10492 tmp_crtc = connector->base.encoder->crtc;
10493
10494 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10495 }
10496
10497 if (connector->new_encoder)
10498 *prepare_pipes |=
10499 1 << connector->new_encoder->new_crtc->pipe;
10500 }
10501
10502 for_each_intel_encoder(dev, encoder) {
10503 if (encoder->base.crtc == &encoder->new_crtc->base)
10504 continue;
10505
10506 if (encoder->base.crtc) {
10507 tmp_crtc = encoder->base.crtc;
10508
10509 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10510 }
10511
10512 if (encoder->new_crtc)
10513 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10514 }
10515
10516 /* Check for pipes that will be enabled/disabled ... */
10517 for_each_intel_crtc(dev, intel_crtc) {
10518 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10519 continue;
10520
10521 if (!intel_crtc->new_enabled)
10522 *disable_pipes |= 1 << intel_crtc->pipe;
10523 else
10524 *prepare_pipes |= 1 << intel_crtc->pipe;
10525 }
10526
10527
10528 /* set_mode is also used to update properties on life display pipes. */
10529 intel_crtc = to_intel_crtc(crtc);
10530 if (intel_crtc->new_enabled)
10531 *prepare_pipes |= 1 << intel_crtc->pipe;
10532
10533 /*
10534 * For simplicity do a full modeset on any pipe where the output routing
10535 * changed. We could be more clever, but that would require us to be
10536 * more careful with calling the relevant encoder->mode_set functions.
10537 */
10538 if (*prepare_pipes)
10539 *modeset_pipes = *prepare_pipes;
10540
10541 /* ... and mask these out. */
10542 *modeset_pipes &= ~(*disable_pipes);
10543 *prepare_pipes &= ~(*disable_pipes);
10544
10545 /*
10546 * HACK: We don't (yet) fully support global modesets. intel_set_config
10547 * obies this rule, but the modeset restore mode of
10548 * intel_modeset_setup_hw_state does not.
10549 */
10550 *modeset_pipes &= 1 << intel_crtc->pipe;
10551 *prepare_pipes &= 1 << intel_crtc->pipe;
10552
10553 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10554 *modeset_pipes, *prepare_pipes, *disable_pipes);
10555 }
10556
10557 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10558 {
10559 struct drm_encoder *encoder;
10560 struct drm_device *dev = crtc->dev;
10561
10562 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10563 if (encoder->crtc == crtc)
10564 return true;
10565
10566 return false;
10567 }
10568
10569 static void
10570 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10571 {
10572 struct intel_encoder *intel_encoder;
10573 struct intel_crtc *intel_crtc;
10574 struct drm_connector *connector;
10575
10576 for_each_intel_encoder(dev, intel_encoder) {
10577 if (!intel_encoder->base.crtc)
10578 continue;
10579
10580 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10581
10582 if (prepare_pipes & (1 << intel_crtc->pipe))
10583 intel_encoder->connectors_active = false;
10584 }
10585
10586 intel_modeset_commit_output_state(dev);
10587
10588 /* Double check state. */
10589 for_each_intel_crtc(dev, intel_crtc) {
10590 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10591 WARN_ON(intel_crtc->new_config &&
10592 intel_crtc->new_config != &intel_crtc->config);
10593 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10594 }
10595
10596 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10597 if (!connector->encoder || !connector->encoder->crtc)
10598 continue;
10599
10600 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10601
10602 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10603 struct drm_property *dpms_property =
10604 dev->mode_config.dpms_property;
10605
10606 connector->dpms = DRM_MODE_DPMS_ON;
10607 drm_object_property_set_value(&connector->base,
10608 dpms_property,
10609 DRM_MODE_DPMS_ON);
10610
10611 intel_encoder = to_intel_encoder(connector->encoder);
10612 intel_encoder->connectors_active = true;
10613 }
10614 }
10615
10616 }
10617
10618 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10619 {
10620 int diff;
10621
10622 if (clock1 == clock2)
10623 return true;
10624
10625 if (!clock1 || !clock2)
10626 return false;
10627
10628 diff = abs(clock1 - clock2);
10629
10630 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10631 return true;
10632
10633 return false;
10634 }
10635
10636 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10637 list_for_each_entry((intel_crtc), \
10638 &(dev)->mode_config.crtc_list, \
10639 base.head) \
10640 if (mask & (1 <<(intel_crtc)->pipe))
10641
10642 static bool
10643 intel_pipe_config_compare(struct drm_device *dev,
10644 struct intel_crtc_config *current_config,
10645 struct intel_crtc_config *pipe_config)
10646 {
10647 #define PIPE_CONF_CHECK_X(name) \
10648 if (current_config->name != pipe_config->name) { \
10649 DRM_ERROR("mismatch in " #name " " \
10650 "(expected 0x%08x, found 0x%08x)\n", \
10651 current_config->name, \
10652 pipe_config->name); \
10653 return false; \
10654 }
10655
10656 #define PIPE_CONF_CHECK_I(name) \
10657 if (current_config->name != pipe_config->name) { \
10658 DRM_ERROR("mismatch in " #name " " \
10659 "(expected %i, found %i)\n", \
10660 current_config->name, \
10661 pipe_config->name); \
10662 return false; \
10663 }
10664
10665 /* This is required for BDW+ where there is only one set of registers for
10666 * switching between high and low RR.
10667 * This macro can be used whenever a comparison has to be made between one
10668 * hw state and multiple sw state variables.
10669 */
10670 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10671 if ((current_config->name != pipe_config->name) && \
10672 (current_config->alt_name != pipe_config->name)) { \
10673 DRM_ERROR("mismatch in " #name " " \
10674 "(expected %i or %i, found %i)\n", \
10675 current_config->name, \
10676 current_config->alt_name, \
10677 pipe_config->name); \
10678 return false; \
10679 }
10680
10681 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10682 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10683 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10684 "(expected %i, found %i)\n", \
10685 current_config->name & (mask), \
10686 pipe_config->name & (mask)); \
10687 return false; \
10688 }
10689
10690 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10691 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10692 DRM_ERROR("mismatch in " #name " " \
10693 "(expected %i, found %i)\n", \
10694 current_config->name, \
10695 pipe_config->name); \
10696 return false; \
10697 }
10698
10699 #define PIPE_CONF_QUIRK(quirk) \
10700 ((current_config->quirks | pipe_config->quirks) & (quirk))
10701
10702 PIPE_CONF_CHECK_I(cpu_transcoder);
10703
10704 PIPE_CONF_CHECK_I(has_pch_encoder);
10705 PIPE_CONF_CHECK_I(fdi_lanes);
10706 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10707 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10708 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10709 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10710 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10711
10712 PIPE_CONF_CHECK_I(has_dp_encoder);
10713
10714 if (INTEL_INFO(dev)->gen < 8) {
10715 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10716 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10717 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10718 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10719 PIPE_CONF_CHECK_I(dp_m_n.tu);
10720
10721 if (current_config->has_drrs) {
10722 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10723 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10724 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10725 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10726 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10727 }
10728 } else {
10729 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10730 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10731 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10732 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10733 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10734 }
10735
10736 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10737 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10738 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10739 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10740 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10741 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10742
10743 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10744 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10745 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10746 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10747 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10748 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10749
10750 PIPE_CONF_CHECK_I(pixel_multiplier);
10751 PIPE_CONF_CHECK_I(has_hdmi_sink);
10752 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10753 IS_VALLEYVIEW(dev))
10754 PIPE_CONF_CHECK_I(limited_color_range);
10755
10756 PIPE_CONF_CHECK_I(has_audio);
10757
10758 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10759 DRM_MODE_FLAG_INTERLACE);
10760
10761 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10762 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10763 DRM_MODE_FLAG_PHSYNC);
10764 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10765 DRM_MODE_FLAG_NHSYNC);
10766 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10767 DRM_MODE_FLAG_PVSYNC);
10768 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10769 DRM_MODE_FLAG_NVSYNC);
10770 }
10771
10772 PIPE_CONF_CHECK_I(pipe_src_w);
10773 PIPE_CONF_CHECK_I(pipe_src_h);
10774
10775 /*
10776 * FIXME: BIOS likes to set up a cloned config with lvds+external
10777 * screen. Since we don't yet re-compute the pipe config when moving
10778 * just the lvds port away to another pipe the sw tracking won't match.
10779 *
10780 * Proper atomic modesets with recomputed global state will fix this.
10781 * Until then just don't check gmch state for inherited modes.
10782 */
10783 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10784 PIPE_CONF_CHECK_I(gmch_pfit.control);
10785 /* pfit ratios are autocomputed by the hw on gen4+ */
10786 if (INTEL_INFO(dev)->gen < 4)
10787 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10788 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10789 }
10790
10791 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10792 if (current_config->pch_pfit.enabled) {
10793 PIPE_CONF_CHECK_I(pch_pfit.pos);
10794 PIPE_CONF_CHECK_I(pch_pfit.size);
10795 }
10796
10797 /* BDW+ don't expose a synchronous way to read the state */
10798 if (IS_HASWELL(dev))
10799 PIPE_CONF_CHECK_I(ips_enabled);
10800
10801 PIPE_CONF_CHECK_I(double_wide);
10802
10803 PIPE_CONF_CHECK_X(ddi_pll_sel);
10804
10805 PIPE_CONF_CHECK_I(shared_dpll);
10806 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10807 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10808 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10809 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10810 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10811
10812 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10813 PIPE_CONF_CHECK_I(pipe_bpp);
10814
10815 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10816 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10817
10818 #undef PIPE_CONF_CHECK_X
10819 #undef PIPE_CONF_CHECK_I
10820 #undef PIPE_CONF_CHECK_I_ALT
10821 #undef PIPE_CONF_CHECK_FLAGS
10822 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10823 #undef PIPE_CONF_QUIRK
10824
10825 return true;
10826 }
10827
10828 static void
10829 check_connector_state(struct drm_device *dev)
10830 {
10831 struct intel_connector *connector;
10832
10833 list_for_each_entry(connector, &dev->mode_config.connector_list,
10834 base.head) {
10835 /* This also checks the encoder/connector hw state with the
10836 * ->get_hw_state callbacks. */
10837 intel_connector_check_state(connector);
10838
10839 WARN(&connector->new_encoder->base != connector->base.encoder,
10840 "connector's staged encoder doesn't match current encoder\n");
10841 }
10842 }
10843
10844 static void
10845 check_encoder_state(struct drm_device *dev)
10846 {
10847 struct intel_encoder *encoder;
10848 struct intel_connector *connector;
10849
10850 for_each_intel_encoder(dev, encoder) {
10851 bool enabled = false;
10852 bool active = false;
10853 enum pipe pipe, tracked_pipe;
10854
10855 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10856 encoder->base.base.id,
10857 encoder->base.name);
10858
10859 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10860 "encoder's stage crtc doesn't match current crtc\n");
10861 WARN(encoder->connectors_active && !encoder->base.crtc,
10862 "encoder's active_connectors set, but no crtc\n");
10863
10864 list_for_each_entry(connector, &dev->mode_config.connector_list,
10865 base.head) {
10866 if (connector->base.encoder != &encoder->base)
10867 continue;
10868 enabled = true;
10869 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10870 active = true;
10871 }
10872 /*
10873 * for MST connectors if we unplug the connector is gone
10874 * away but the encoder is still connected to a crtc
10875 * until a modeset happens in response to the hotplug.
10876 */
10877 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10878 continue;
10879
10880 WARN(!!encoder->base.crtc != enabled,
10881 "encoder's enabled state mismatch "
10882 "(expected %i, found %i)\n",
10883 !!encoder->base.crtc, enabled);
10884 WARN(active && !encoder->base.crtc,
10885 "active encoder with no crtc\n");
10886
10887 WARN(encoder->connectors_active != active,
10888 "encoder's computed active state doesn't match tracked active state "
10889 "(expected %i, found %i)\n", active, encoder->connectors_active);
10890
10891 active = encoder->get_hw_state(encoder, &pipe);
10892 WARN(active != encoder->connectors_active,
10893 "encoder's hw state doesn't match sw tracking "
10894 "(expected %i, found %i)\n",
10895 encoder->connectors_active, active);
10896
10897 if (!encoder->base.crtc)
10898 continue;
10899
10900 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10901 WARN(active && pipe != tracked_pipe,
10902 "active encoder's pipe doesn't match"
10903 "(expected %i, found %i)\n",
10904 tracked_pipe, pipe);
10905
10906 }
10907 }
10908
10909 static void
10910 check_crtc_state(struct drm_device *dev)
10911 {
10912 struct drm_i915_private *dev_priv = dev->dev_private;
10913 struct intel_crtc *crtc;
10914 struct intel_encoder *encoder;
10915 struct intel_crtc_config pipe_config;
10916
10917 for_each_intel_crtc(dev, crtc) {
10918 bool enabled = false;
10919 bool active = false;
10920
10921 memset(&pipe_config, 0, sizeof(pipe_config));
10922
10923 DRM_DEBUG_KMS("[CRTC:%d]\n",
10924 crtc->base.base.id);
10925
10926 WARN(crtc->active && !crtc->base.enabled,
10927 "active crtc, but not enabled in sw tracking\n");
10928
10929 for_each_intel_encoder(dev, encoder) {
10930 if (encoder->base.crtc != &crtc->base)
10931 continue;
10932 enabled = true;
10933 if (encoder->connectors_active)
10934 active = true;
10935 }
10936
10937 WARN(active != crtc->active,
10938 "crtc's computed active state doesn't match tracked active state "
10939 "(expected %i, found %i)\n", active, crtc->active);
10940 WARN(enabled != crtc->base.enabled,
10941 "crtc's computed enabled state doesn't match tracked enabled state "
10942 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10943
10944 active = dev_priv->display.get_pipe_config(crtc,
10945 &pipe_config);
10946
10947 /* hw state is inconsistent with the pipe quirk */
10948 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10949 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
10950 active = crtc->active;
10951
10952 for_each_intel_encoder(dev, encoder) {
10953 enum pipe pipe;
10954 if (encoder->base.crtc != &crtc->base)
10955 continue;
10956 if (encoder->get_hw_state(encoder, &pipe))
10957 encoder->get_config(encoder, &pipe_config);
10958 }
10959
10960 WARN(crtc->active != active,
10961 "crtc active state doesn't match with hw state "
10962 "(expected %i, found %i)\n", crtc->active, active);
10963
10964 if (active &&
10965 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10966 WARN(1, "pipe state doesn't match!\n");
10967 intel_dump_pipe_config(crtc, &pipe_config,
10968 "[hw state]");
10969 intel_dump_pipe_config(crtc, &crtc->config,
10970 "[sw state]");
10971 }
10972 }
10973 }
10974
10975 static void
10976 check_shared_dpll_state(struct drm_device *dev)
10977 {
10978 struct drm_i915_private *dev_priv = dev->dev_private;
10979 struct intel_crtc *crtc;
10980 struct intel_dpll_hw_state dpll_hw_state;
10981 int i;
10982
10983 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10984 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10985 int enabled_crtcs = 0, active_crtcs = 0;
10986 bool active;
10987
10988 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10989
10990 DRM_DEBUG_KMS("%s\n", pll->name);
10991
10992 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10993
10994 WARN(pll->active > pll->refcount,
10995 "more active pll users than references: %i vs %i\n",
10996 pll->active, pll->refcount);
10997 WARN(pll->active && !pll->on,
10998 "pll in active use but not on in sw tracking\n");
10999 WARN(pll->on && !pll->active,
11000 "pll in on but not on in use in sw tracking\n");
11001 WARN(pll->on != active,
11002 "pll on state mismatch (expected %i, found %i)\n",
11003 pll->on, active);
11004
11005 for_each_intel_crtc(dev, crtc) {
11006 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
11007 enabled_crtcs++;
11008 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11009 active_crtcs++;
11010 }
11011 WARN(pll->active != active_crtcs,
11012 "pll active crtcs mismatch (expected %i, found %i)\n",
11013 pll->active, active_crtcs);
11014 WARN(pll->refcount != enabled_crtcs,
11015 "pll enabled crtcs mismatch (expected %i, found %i)\n",
11016 pll->refcount, enabled_crtcs);
11017
11018 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
11019 sizeof(dpll_hw_state)),
11020 "pll hw state mismatch\n");
11021 }
11022 }
11023
11024 void
11025 intel_modeset_check_state(struct drm_device *dev)
11026 {
11027 check_connector_state(dev);
11028 check_encoder_state(dev);
11029 check_crtc_state(dev);
11030 check_shared_dpll_state(dev);
11031 }
11032
11033 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
11034 int dotclock)
11035 {
11036 /*
11037 * FDI already provided one idea for the dotclock.
11038 * Yell if the encoder disagrees.
11039 */
11040 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
11041 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11042 pipe_config->adjusted_mode.crtc_clock, dotclock);
11043 }
11044
11045 static void update_scanline_offset(struct intel_crtc *crtc)
11046 {
11047 struct drm_device *dev = crtc->base.dev;
11048
11049 /*
11050 * The scanline counter increments at the leading edge of hsync.
11051 *
11052 * On most platforms it starts counting from vtotal-1 on the
11053 * first active line. That means the scanline counter value is
11054 * always one less than what we would expect. Ie. just after
11055 * start of vblank, which also occurs at start of hsync (on the
11056 * last active line), the scanline counter will read vblank_start-1.
11057 *
11058 * On gen2 the scanline counter starts counting from 1 instead
11059 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11060 * to keep the value positive), instead of adding one.
11061 *
11062 * On HSW+ the behaviour of the scanline counter depends on the output
11063 * type. For DP ports it behaves like most other platforms, but on HDMI
11064 * there's an extra 1 line difference. So we need to add two instead of
11065 * one to the value.
11066 */
11067 if (IS_GEN2(dev)) {
11068 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
11069 int vtotal;
11070
11071 vtotal = mode->crtc_vtotal;
11072 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
11073 vtotal /= 2;
11074
11075 crtc->scanline_offset = vtotal - 1;
11076 } else if (HAS_DDI(dev) &&
11077 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {
11078 crtc->scanline_offset = 2;
11079 } else
11080 crtc->scanline_offset = 1;
11081 }
11082
11083 static int __intel_set_mode(struct drm_crtc *crtc,
11084 struct drm_display_mode *mode,
11085 int x, int y, struct drm_framebuffer *fb)
11086 {
11087 struct drm_device *dev = crtc->dev;
11088 struct drm_i915_private *dev_priv = dev->dev_private;
11089 struct drm_display_mode *saved_mode;
11090 struct intel_crtc_config *pipe_config = NULL;
11091 struct intel_crtc *intel_crtc;
11092 unsigned disable_pipes, prepare_pipes, modeset_pipes;
11093 int ret = 0;
11094
11095 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
11096 if (!saved_mode)
11097 return -ENOMEM;
11098
11099 intel_modeset_affected_pipes(crtc, &modeset_pipes,
11100 &prepare_pipes, &disable_pipes);
11101
11102 *saved_mode = crtc->mode;
11103
11104 /* Hack: Because we don't (yet) support global modeset on multiple
11105 * crtcs, we don't keep track of the new mode for more than one crtc.
11106 * Hence simply check whether any bit is set in modeset_pipes in all the
11107 * pieces of code that are not yet converted to deal with mutliple crtcs
11108 * changing their mode at the same time. */
11109 if (modeset_pipes) {
11110 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
11111 if (IS_ERR(pipe_config)) {
11112 ret = PTR_ERR(pipe_config);
11113 pipe_config = NULL;
11114
11115 goto out;
11116 }
11117 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11118 "[modeset]");
11119 to_intel_crtc(crtc)->new_config = pipe_config;
11120 }
11121
11122 /*
11123 * See if the config requires any additional preparation, e.g.
11124 * to adjust global state with pipes off. We need to do this
11125 * here so we can get the modeset_pipe updated config for the new
11126 * mode set on this crtc. For other crtcs we need to use the
11127 * adjusted_mode bits in the crtc directly.
11128 */
11129 if (IS_VALLEYVIEW(dev)) {
11130 valleyview_modeset_global_pipes(dev, &prepare_pipes);
11131
11132 /* may have added more to prepare_pipes than we should */
11133 prepare_pipes &= ~disable_pipes;
11134 }
11135
11136 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
11137 intel_crtc_disable(&intel_crtc->base);
11138
11139 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11140 if (intel_crtc->base.enabled)
11141 dev_priv->display.crtc_disable(&intel_crtc->base);
11142 }
11143
11144 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11145 * to set it here already despite that we pass it down the callchain.
11146 */
11147 if (modeset_pipes) {
11148 crtc->mode = *mode;
11149 /* mode_set/enable/disable functions rely on a correct pipe
11150 * config. */
11151 to_intel_crtc(crtc)->config = *pipe_config;
11152 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
11153
11154 /*
11155 * Calculate and store various constants which
11156 * are later needed by vblank and swap-completion
11157 * timestamping. They are derived from true hwmode.
11158 */
11159 drm_calc_timestamping_constants(crtc,
11160 &pipe_config->adjusted_mode);
11161 }
11162
11163 /* Only after disabling all output pipelines that will be changed can we
11164 * update the the output configuration. */
11165 intel_modeset_update_state(dev, prepare_pipes);
11166
11167 if (dev_priv->display.modeset_global_resources)
11168 dev_priv->display.modeset_global_resources(dev);
11169
11170 /* Set up the DPLL and any encoders state that needs to adjust or depend
11171 * on the DPLL.
11172 */
11173 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11174 struct drm_framebuffer *old_fb = crtc->primary->fb;
11175 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
11176 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11177
11178 mutex_lock(&dev->struct_mutex);
11179 ret = intel_pin_and_fence_fb_obj(dev,
11180 obj,
11181 NULL);
11182 if (ret != 0) {
11183 DRM_ERROR("pin & fence failed\n");
11184 mutex_unlock(&dev->struct_mutex);
11185 goto done;
11186 }
11187 if (old_fb)
11188 intel_unpin_fb_obj(old_obj);
11189 i915_gem_track_fb(old_obj, obj,
11190 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11191 mutex_unlock(&dev->struct_mutex);
11192
11193 crtc->primary->fb = fb;
11194 crtc->x = x;
11195 crtc->y = y;
11196
11197 ret = dev_priv->display.crtc_mode_set(&intel_crtc->base,
11198 x, y, fb);
11199 if (ret)
11200 goto done;
11201 }
11202
11203 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11204 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11205 update_scanline_offset(intel_crtc);
11206
11207 dev_priv->display.crtc_enable(&intel_crtc->base);
11208 }
11209
11210 /* FIXME: add subpixel order */
11211 done:
11212 if (ret && crtc->enabled)
11213 crtc->mode = *saved_mode;
11214
11215 out:
11216 kfree(pipe_config);
11217 kfree(saved_mode);
11218 return ret;
11219 }
11220
11221 static int intel_set_mode(struct drm_crtc *crtc,
11222 struct drm_display_mode *mode,
11223 int x, int y, struct drm_framebuffer *fb)
11224 {
11225 int ret;
11226
11227 ret = __intel_set_mode(crtc, mode, x, y, fb);
11228
11229 if (ret == 0)
11230 intel_modeset_check_state(crtc->dev);
11231
11232 return ret;
11233 }
11234
11235 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11236 {
11237 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
11238 }
11239
11240 #undef for_each_intel_crtc_masked
11241
11242 static void intel_set_config_free(struct intel_set_config *config)
11243 {
11244 if (!config)
11245 return;
11246
11247 kfree(config->save_connector_encoders);
11248 kfree(config->save_encoder_crtcs);
11249 kfree(config->save_crtc_enabled);
11250 kfree(config);
11251 }
11252
11253 static int intel_set_config_save_state(struct drm_device *dev,
11254 struct intel_set_config *config)
11255 {
11256 struct drm_crtc *crtc;
11257 struct drm_encoder *encoder;
11258 struct drm_connector *connector;
11259 int count;
11260
11261 config->save_crtc_enabled =
11262 kcalloc(dev->mode_config.num_crtc,
11263 sizeof(bool), GFP_KERNEL);
11264 if (!config->save_crtc_enabled)
11265 return -ENOMEM;
11266
11267 config->save_encoder_crtcs =
11268 kcalloc(dev->mode_config.num_encoder,
11269 sizeof(struct drm_crtc *), GFP_KERNEL);
11270 if (!config->save_encoder_crtcs)
11271 return -ENOMEM;
11272
11273 config->save_connector_encoders =
11274 kcalloc(dev->mode_config.num_connector,
11275 sizeof(struct drm_encoder *), GFP_KERNEL);
11276 if (!config->save_connector_encoders)
11277 return -ENOMEM;
11278
11279 /* Copy data. Note that driver private data is not affected.
11280 * Should anything bad happen only the expected state is
11281 * restored, not the drivers personal bookkeeping.
11282 */
11283 count = 0;
11284 for_each_crtc(dev, crtc) {
11285 config->save_crtc_enabled[count++] = crtc->enabled;
11286 }
11287
11288 count = 0;
11289 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11290 config->save_encoder_crtcs[count++] = encoder->crtc;
11291 }
11292
11293 count = 0;
11294 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11295 config->save_connector_encoders[count++] = connector->encoder;
11296 }
11297
11298 return 0;
11299 }
11300
11301 static void intel_set_config_restore_state(struct drm_device *dev,
11302 struct intel_set_config *config)
11303 {
11304 struct intel_crtc *crtc;
11305 struct intel_encoder *encoder;
11306 struct intel_connector *connector;
11307 int count;
11308
11309 count = 0;
11310 for_each_intel_crtc(dev, crtc) {
11311 crtc->new_enabled = config->save_crtc_enabled[count++];
11312
11313 if (crtc->new_enabled)
11314 crtc->new_config = &crtc->config;
11315 else
11316 crtc->new_config = NULL;
11317 }
11318
11319 count = 0;
11320 for_each_intel_encoder(dev, encoder) {
11321 encoder->new_crtc =
11322 to_intel_crtc(config->save_encoder_crtcs[count++]);
11323 }
11324
11325 count = 0;
11326 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11327 connector->new_encoder =
11328 to_intel_encoder(config->save_connector_encoders[count++]);
11329 }
11330 }
11331
11332 static bool
11333 is_crtc_connector_off(struct drm_mode_set *set)
11334 {
11335 int i;
11336
11337 if (set->num_connectors == 0)
11338 return false;
11339
11340 if (WARN_ON(set->connectors == NULL))
11341 return false;
11342
11343 for (i = 0; i < set->num_connectors; i++)
11344 if (set->connectors[i]->encoder &&
11345 set->connectors[i]->encoder->crtc == set->crtc &&
11346 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11347 return true;
11348
11349 return false;
11350 }
11351
11352 static void
11353 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11354 struct intel_set_config *config)
11355 {
11356
11357 /* We should be able to check here if the fb has the same properties
11358 * and then just flip_or_move it */
11359 if (is_crtc_connector_off(set)) {
11360 config->mode_changed = true;
11361 } else if (set->crtc->primary->fb != set->fb) {
11362 /*
11363 * If we have no fb, we can only flip as long as the crtc is
11364 * active, otherwise we need a full mode set. The crtc may
11365 * be active if we've only disabled the primary plane, or
11366 * in fastboot situations.
11367 */
11368 if (set->crtc->primary->fb == NULL) {
11369 struct intel_crtc *intel_crtc =
11370 to_intel_crtc(set->crtc);
11371
11372 if (intel_crtc->active) {
11373 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11374 config->fb_changed = true;
11375 } else {
11376 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11377 config->mode_changed = true;
11378 }
11379 } else if (set->fb == NULL) {
11380 config->mode_changed = true;
11381 } else if (set->fb->pixel_format !=
11382 set->crtc->primary->fb->pixel_format) {
11383 config->mode_changed = true;
11384 } else {
11385 config->fb_changed = true;
11386 }
11387 }
11388
11389 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11390 config->fb_changed = true;
11391
11392 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11393 DRM_DEBUG_KMS("modes are different, full mode set\n");
11394 drm_mode_debug_printmodeline(&set->crtc->mode);
11395 drm_mode_debug_printmodeline(set->mode);
11396 config->mode_changed = true;
11397 }
11398
11399 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11400 set->crtc->base.id, config->mode_changed, config->fb_changed);
11401 }
11402
11403 static int
11404 intel_modeset_stage_output_state(struct drm_device *dev,
11405 struct drm_mode_set *set,
11406 struct intel_set_config *config)
11407 {
11408 struct intel_connector *connector;
11409 struct intel_encoder *encoder;
11410 struct intel_crtc *crtc;
11411 int ro;
11412
11413 /* The upper layers ensure that we either disable a crtc or have a list
11414 * of connectors. For paranoia, double-check this. */
11415 WARN_ON(!set->fb && (set->num_connectors != 0));
11416 WARN_ON(set->fb && (set->num_connectors == 0));
11417
11418 list_for_each_entry(connector, &dev->mode_config.connector_list,
11419 base.head) {
11420 /* Otherwise traverse passed in connector list and get encoders
11421 * for them. */
11422 for (ro = 0; ro < set->num_connectors; ro++) {
11423 if (set->connectors[ro] == &connector->base) {
11424 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11425 break;
11426 }
11427 }
11428
11429 /* If we disable the crtc, disable all its connectors. Also, if
11430 * the connector is on the changing crtc but not on the new
11431 * connector list, disable it. */
11432 if ((!set->fb || ro == set->num_connectors) &&
11433 connector->base.encoder &&
11434 connector->base.encoder->crtc == set->crtc) {
11435 connector->new_encoder = NULL;
11436
11437 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11438 connector->base.base.id,
11439 connector->base.name);
11440 }
11441
11442
11443 if (&connector->new_encoder->base != connector->base.encoder) {
11444 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11445 config->mode_changed = true;
11446 }
11447 }
11448 /* connector->new_encoder is now updated for all connectors. */
11449
11450 /* Update crtc of enabled connectors. */
11451 list_for_each_entry(connector, &dev->mode_config.connector_list,
11452 base.head) {
11453 struct drm_crtc *new_crtc;
11454
11455 if (!connector->new_encoder)
11456 continue;
11457
11458 new_crtc = connector->new_encoder->base.crtc;
11459
11460 for (ro = 0; ro < set->num_connectors; ro++) {
11461 if (set->connectors[ro] == &connector->base)
11462 new_crtc = set->crtc;
11463 }
11464
11465 /* Make sure the new CRTC will work with the encoder */
11466 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11467 new_crtc)) {
11468 return -EINVAL;
11469 }
11470 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11471
11472 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11473 connector->base.base.id,
11474 connector->base.name,
11475 new_crtc->base.id);
11476 }
11477
11478 /* Check for any encoders that needs to be disabled. */
11479 for_each_intel_encoder(dev, encoder) {
11480 int num_connectors = 0;
11481 list_for_each_entry(connector,
11482 &dev->mode_config.connector_list,
11483 base.head) {
11484 if (connector->new_encoder == encoder) {
11485 WARN_ON(!connector->new_encoder->new_crtc);
11486 num_connectors++;
11487 }
11488 }
11489
11490 if (num_connectors == 0)
11491 encoder->new_crtc = NULL;
11492 else if (num_connectors > 1)
11493 return -EINVAL;
11494
11495 /* Only now check for crtc changes so we don't miss encoders
11496 * that will be disabled. */
11497 if (&encoder->new_crtc->base != encoder->base.crtc) {
11498 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11499 config->mode_changed = true;
11500 }
11501 }
11502 /* Now we've also updated encoder->new_crtc for all encoders. */
11503 list_for_each_entry(connector, &dev->mode_config.connector_list,
11504 base.head) {
11505 if (connector->new_encoder)
11506 if (connector->new_encoder != connector->encoder)
11507 connector->encoder = connector->new_encoder;
11508 }
11509 for_each_intel_crtc(dev, crtc) {
11510 crtc->new_enabled = false;
11511
11512 for_each_intel_encoder(dev, encoder) {
11513 if (encoder->new_crtc == crtc) {
11514 crtc->new_enabled = true;
11515 break;
11516 }
11517 }
11518
11519 if (crtc->new_enabled != crtc->base.enabled) {
11520 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11521 crtc->new_enabled ? "en" : "dis");
11522 config->mode_changed = true;
11523 }
11524
11525 if (crtc->new_enabled)
11526 crtc->new_config = &crtc->config;
11527 else
11528 crtc->new_config = NULL;
11529 }
11530
11531 return 0;
11532 }
11533
11534 static void disable_crtc_nofb(struct intel_crtc *crtc)
11535 {
11536 struct drm_device *dev = crtc->base.dev;
11537 struct intel_encoder *encoder;
11538 struct intel_connector *connector;
11539
11540 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11541 pipe_name(crtc->pipe));
11542
11543 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11544 if (connector->new_encoder &&
11545 connector->new_encoder->new_crtc == crtc)
11546 connector->new_encoder = NULL;
11547 }
11548
11549 for_each_intel_encoder(dev, encoder) {
11550 if (encoder->new_crtc == crtc)
11551 encoder->new_crtc = NULL;
11552 }
11553
11554 crtc->new_enabled = false;
11555 crtc->new_config = NULL;
11556 }
11557
11558 static int intel_crtc_set_config(struct drm_mode_set *set)
11559 {
11560 struct drm_device *dev;
11561 struct drm_mode_set save_set;
11562 struct intel_set_config *config;
11563 int ret;
11564
11565 BUG_ON(!set);
11566 BUG_ON(!set->crtc);
11567 BUG_ON(!set->crtc->helper_private);
11568
11569 /* Enforce sane interface api - has been abused by the fb helper. */
11570 BUG_ON(!set->mode && set->fb);
11571 BUG_ON(set->fb && set->num_connectors == 0);
11572
11573 if (set->fb) {
11574 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11575 set->crtc->base.id, set->fb->base.id,
11576 (int)set->num_connectors, set->x, set->y);
11577 } else {
11578 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11579 }
11580
11581 dev = set->crtc->dev;
11582
11583 ret = -ENOMEM;
11584 config = kzalloc(sizeof(*config), GFP_KERNEL);
11585 if (!config)
11586 goto out_config;
11587
11588 ret = intel_set_config_save_state(dev, config);
11589 if (ret)
11590 goto out_config;
11591
11592 save_set.crtc = set->crtc;
11593 save_set.mode = &set->crtc->mode;
11594 save_set.x = set->crtc->x;
11595 save_set.y = set->crtc->y;
11596 save_set.fb = set->crtc->primary->fb;
11597
11598 /* Compute whether we need a full modeset, only an fb base update or no
11599 * change at all. In the future we might also check whether only the
11600 * mode changed, e.g. for LVDS where we only change the panel fitter in
11601 * such cases. */
11602 intel_set_config_compute_mode_changes(set, config);
11603
11604 ret = intel_modeset_stage_output_state(dev, set, config);
11605 if (ret)
11606 goto fail;
11607
11608 if (config->mode_changed) {
11609 ret = intel_set_mode(set->crtc, set->mode,
11610 set->x, set->y, set->fb);
11611 } else if (config->fb_changed) {
11612 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11613
11614 intel_crtc_wait_for_pending_flips(set->crtc);
11615
11616 ret = intel_pipe_set_base(set->crtc,
11617 set->x, set->y, set->fb);
11618
11619 /*
11620 * We need to make sure the primary plane is re-enabled if it
11621 * has previously been turned off.
11622 */
11623 if (!intel_crtc->primary_enabled && ret == 0) {
11624 WARN_ON(!intel_crtc->active);
11625 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11626 }
11627
11628 /*
11629 * In the fastboot case this may be our only check of the
11630 * state after boot. It would be better to only do it on
11631 * the first update, but we don't have a nice way of doing that
11632 * (and really, set_config isn't used much for high freq page
11633 * flipping, so increasing its cost here shouldn't be a big
11634 * deal).
11635 */
11636 if (i915.fastboot && ret == 0)
11637 intel_modeset_check_state(set->crtc->dev);
11638 }
11639
11640 if (ret) {
11641 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11642 set->crtc->base.id, ret);
11643 fail:
11644 intel_set_config_restore_state(dev, config);
11645
11646 /*
11647 * HACK: if the pipe was on, but we didn't have a framebuffer,
11648 * force the pipe off to avoid oopsing in the modeset code
11649 * due to fb==NULL. This should only happen during boot since
11650 * we don't yet reconstruct the FB from the hardware state.
11651 */
11652 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11653 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11654
11655 /* Try to restore the config */
11656 if (config->mode_changed &&
11657 intel_set_mode(save_set.crtc, save_set.mode,
11658 save_set.x, save_set.y, save_set.fb))
11659 DRM_ERROR("failed to restore config after modeset failure\n");
11660 }
11661
11662 out_config:
11663 intel_set_config_free(config);
11664 return ret;
11665 }
11666
11667 static const struct drm_crtc_funcs intel_crtc_funcs = {
11668 .gamma_set = intel_crtc_gamma_set,
11669 .set_config = intel_crtc_set_config,
11670 .destroy = intel_crtc_destroy,
11671 .page_flip = intel_crtc_page_flip,
11672 };
11673
11674 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11675 struct intel_shared_dpll *pll,
11676 struct intel_dpll_hw_state *hw_state)
11677 {
11678 uint32_t val;
11679
11680 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_PLLS))
11681 return false;
11682
11683 val = I915_READ(PCH_DPLL(pll->id));
11684 hw_state->dpll = val;
11685 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11686 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11687
11688 return val & DPLL_VCO_ENABLE;
11689 }
11690
11691 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11692 struct intel_shared_dpll *pll)
11693 {
11694 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
11695 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
11696 }
11697
11698 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11699 struct intel_shared_dpll *pll)
11700 {
11701 /* PCH refclock must be enabled first */
11702 ibx_assert_pch_refclk_enabled(dev_priv);
11703
11704 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11705
11706 /* Wait for the clocks to stabilize. */
11707 POSTING_READ(PCH_DPLL(pll->id));
11708 udelay(150);
11709
11710 /* The pixel multiplier can only be updated once the
11711 * DPLL is enabled and the clocks are stable.
11712 *
11713 * So write it again.
11714 */
11715 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11716 POSTING_READ(PCH_DPLL(pll->id));
11717 udelay(200);
11718 }
11719
11720 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11721 struct intel_shared_dpll *pll)
11722 {
11723 struct drm_device *dev = dev_priv->dev;
11724 struct intel_crtc *crtc;
11725
11726 /* Make sure no transcoder isn't still depending on us. */
11727 for_each_intel_crtc(dev, crtc) {
11728 if (intel_crtc_to_shared_dpll(crtc) == pll)
11729 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11730 }
11731
11732 I915_WRITE(PCH_DPLL(pll->id), 0);
11733 POSTING_READ(PCH_DPLL(pll->id));
11734 udelay(200);
11735 }
11736
11737 static char *ibx_pch_dpll_names[] = {
11738 "PCH DPLL A",
11739 "PCH DPLL B",
11740 };
11741
11742 static void ibx_pch_dpll_init(struct drm_device *dev)
11743 {
11744 struct drm_i915_private *dev_priv = dev->dev_private;
11745 int i;
11746
11747 dev_priv->num_shared_dpll = 2;
11748
11749 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11750 dev_priv->shared_dplls[i].id = i;
11751 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11752 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11753 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11754 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11755 dev_priv->shared_dplls[i].get_hw_state =
11756 ibx_pch_dpll_get_hw_state;
11757 }
11758 }
11759
11760 static void intel_shared_dpll_init(struct drm_device *dev)
11761 {
11762 struct drm_i915_private *dev_priv = dev->dev_private;
11763
11764 if (HAS_DDI(dev))
11765 intel_ddi_pll_init(dev);
11766 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11767 ibx_pch_dpll_init(dev);
11768 else
11769 dev_priv->num_shared_dpll = 0;
11770
11771 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11772 }
11773
11774 static int
11775 intel_primary_plane_disable(struct drm_plane *plane)
11776 {
11777 struct drm_device *dev = plane->dev;
11778 struct intel_crtc *intel_crtc;
11779
11780 if (!plane->fb)
11781 return 0;
11782
11783 BUG_ON(!plane->crtc);
11784
11785 intel_crtc = to_intel_crtc(plane->crtc);
11786
11787 /*
11788 * Even though we checked plane->fb above, it's still possible that
11789 * the primary plane has been implicitly disabled because the crtc
11790 * coordinates given weren't visible, or because we detected
11791 * that it was 100% covered by a sprite plane. Or, the CRTC may be
11792 * off and we've set a fb, but haven't actually turned on the CRTC yet.
11793 * In either case, we need to unpin the FB and let the fb pointer get
11794 * updated, but otherwise we don't need to touch the hardware.
11795 */
11796 if (!intel_crtc->primary_enabled)
11797 goto disable_unpin;
11798
11799 intel_crtc_wait_for_pending_flips(plane->crtc);
11800 intel_disable_primary_hw_plane(plane, plane->crtc);
11801
11802 disable_unpin:
11803 mutex_lock(&dev->struct_mutex);
11804 i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
11805 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11806 intel_unpin_fb_obj(intel_fb_obj(plane->fb));
11807 mutex_unlock(&dev->struct_mutex);
11808 plane->fb = NULL;
11809
11810 return 0;
11811 }
11812
11813 static int
11814 intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11815 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11816 unsigned int crtc_w, unsigned int crtc_h,
11817 uint32_t src_x, uint32_t src_y,
11818 uint32_t src_w, uint32_t src_h)
11819 {
11820 struct drm_device *dev = crtc->dev;
11821 struct drm_i915_private *dev_priv = dev->dev_private;
11822 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11823 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11824 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11825 struct drm_rect dest = {
11826 /* integer pixels */
11827 .x1 = crtc_x,
11828 .y1 = crtc_y,
11829 .x2 = crtc_x + crtc_w,
11830 .y2 = crtc_y + crtc_h,
11831 };
11832 struct drm_rect src = {
11833 /* 16.16 fixed point */
11834 .x1 = src_x,
11835 .y1 = src_y,
11836 .x2 = src_x + src_w,
11837 .y2 = src_y + src_h,
11838 };
11839 const struct drm_rect clip = {
11840 /* integer pixels */
11841 .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
11842 .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
11843 };
11844 const struct {
11845 int crtc_x, crtc_y;
11846 unsigned int crtc_w, crtc_h;
11847 uint32_t src_x, src_y, src_w, src_h;
11848 } orig = {
11849 .crtc_x = crtc_x,
11850 .crtc_y = crtc_y,
11851 .crtc_w = crtc_w,
11852 .crtc_h = crtc_h,
11853 .src_x = src_x,
11854 .src_y = src_y,
11855 .src_w = src_w,
11856 .src_h = src_h,
11857 };
11858 struct intel_plane *intel_plane = to_intel_plane(plane);
11859 bool visible;
11860 int ret;
11861
11862 ret = drm_plane_helper_check_update(plane, crtc, fb,
11863 &src, &dest, &clip,
11864 DRM_PLANE_HELPER_NO_SCALING,
11865 DRM_PLANE_HELPER_NO_SCALING,
11866 false, true, &visible);
11867
11868 if (ret)
11869 return ret;
11870
11871 /*
11872 * If the CRTC isn't enabled, we're just pinning the framebuffer,
11873 * updating the fb pointer, and returning without touching the
11874 * hardware. This allows us to later do a drmModeSetCrtc with fb=-1 to
11875 * turn on the display with all planes setup as desired.
11876 */
11877 if (!crtc->enabled) {
11878 mutex_lock(&dev->struct_mutex);
11879
11880 /*
11881 * If we already called setplane while the crtc was disabled,
11882 * we may have an fb pinned; unpin it.
11883 */
11884 if (plane->fb)
11885 intel_unpin_fb_obj(old_obj);
11886
11887 i915_gem_track_fb(old_obj, obj,
11888 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11889
11890 /* Pin and return without programming hardware */
11891 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11892 mutex_unlock(&dev->struct_mutex);
11893
11894 return ret;
11895 }
11896
11897 intel_crtc_wait_for_pending_flips(crtc);
11898
11899 /*
11900 * If clipping results in a non-visible primary plane, we'll disable
11901 * the primary plane. Note that this is a bit different than what
11902 * happens if userspace explicitly disables the plane by passing fb=0
11903 * because plane->fb still gets set and pinned.
11904 */
11905 if (!visible) {
11906 mutex_lock(&dev->struct_mutex);
11907
11908 /*
11909 * Try to pin the new fb first so that we can bail out if we
11910 * fail.
11911 */
11912 if (plane->fb != fb) {
11913 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11914 if (ret) {
11915 mutex_unlock(&dev->struct_mutex);
11916 return ret;
11917 }
11918 }
11919
11920 i915_gem_track_fb(old_obj, obj,
11921 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11922
11923 if (intel_crtc->primary_enabled)
11924 intel_disable_primary_hw_plane(plane, crtc);
11925
11926
11927 if (plane->fb != fb)
11928 if (plane->fb)
11929 intel_unpin_fb_obj(old_obj);
11930
11931 mutex_unlock(&dev->struct_mutex);
11932
11933 } else {
11934 if (intel_crtc && intel_crtc->active &&
11935 intel_crtc->primary_enabled) {
11936 /*
11937 * FBC does not work on some platforms for rotated
11938 * planes, so disable it when rotation is not 0 and
11939 * update it when rotation is set back to 0.
11940 *
11941 * FIXME: This is redundant with the fbc update done in
11942 * the primary plane enable function except that that
11943 * one is done too late. We eventually need to unify
11944 * this.
11945 */
11946 if (INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11947 dev_priv->fbc.plane == intel_crtc->plane &&
11948 intel_plane->rotation != BIT(DRM_ROTATE_0)) {
11949 intel_disable_fbc(dev);
11950 }
11951 }
11952 ret = intel_pipe_set_base(crtc, src.x1, src.y1, fb);
11953 if (ret)
11954 return ret;
11955
11956 if (!intel_crtc->primary_enabled)
11957 intel_enable_primary_hw_plane(plane, crtc);
11958 }
11959
11960 intel_plane->crtc_x = orig.crtc_x;
11961 intel_plane->crtc_y = orig.crtc_y;
11962 intel_plane->crtc_w = orig.crtc_w;
11963 intel_plane->crtc_h = orig.crtc_h;
11964 intel_plane->src_x = orig.src_x;
11965 intel_plane->src_y = orig.src_y;
11966 intel_plane->src_w = orig.src_w;
11967 intel_plane->src_h = orig.src_h;
11968 intel_plane->obj = obj;
11969
11970 return 0;
11971 }
11972
11973 /* Common destruction function for both primary and cursor planes */
11974 static void intel_plane_destroy(struct drm_plane *plane)
11975 {
11976 struct intel_plane *intel_plane = to_intel_plane(plane);
11977 drm_plane_cleanup(plane);
11978 kfree(intel_plane);
11979 }
11980
11981 static const struct drm_plane_funcs intel_primary_plane_funcs = {
11982 .update_plane = intel_primary_plane_setplane,
11983 .disable_plane = intel_primary_plane_disable,
11984 .destroy = intel_plane_destroy,
11985 .set_property = intel_plane_set_property
11986 };
11987
11988 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11989 int pipe)
11990 {
11991 struct intel_plane *primary;
11992 const uint32_t *intel_primary_formats;
11993 int num_formats;
11994
11995 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11996 if (primary == NULL)
11997 return NULL;
11998
11999 primary->can_scale = false;
12000 primary->max_downscale = 1;
12001 primary->pipe = pipe;
12002 primary->plane = pipe;
12003 primary->rotation = BIT(DRM_ROTATE_0);
12004 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
12005 primary->plane = !pipe;
12006
12007 if (INTEL_INFO(dev)->gen <= 3) {
12008 intel_primary_formats = intel_primary_formats_gen2;
12009 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
12010 } else {
12011 intel_primary_formats = intel_primary_formats_gen4;
12012 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
12013 }
12014
12015 drm_universal_plane_init(dev, &primary->base, 0,
12016 &intel_primary_plane_funcs,
12017 intel_primary_formats, num_formats,
12018 DRM_PLANE_TYPE_PRIMARY);
12019
12020 if (INTEL_INFO(dev)->gen >= 4) {
12021 if (!dev->mode_config.rotation_property)
12022 dev->mode_config.rotation_property =
12023 drm_mode_create_rotation_property(dev,
12024 BIT(DRM_ROTATE_0) |
12025 BIT(DRM_ROTATE_180));
12026 if (dev->mode_config.rotation_property)
12027 drm_object_attach_property(&primary->base.base,
12028 dev->mode_config.rotation_property,
12029 primary->rotation);
12030 }
12031
12032 return &primary->base;
12033 }
12034
12035 static int
12036 intel_cursor_plane_disable(struct drm_plane *plane)
12037 {
12038 if (!plane->fb)
12039 return 0;
12040
12041 BUG_ON(!plane->crtc);
12042
12043 return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
12044 }
12045
12046 static int
12047 intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
12048 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
12049 unsigned int crtc_w, unsigned int crtc_h,
12050 uint32_t src_x, uint32_t src_y,
12051 uint32_t src_w, uint32_t src_h)
12052 {
12053 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12054 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12055 struct drm_i915_gem_object *obj = intel_fb->obj;
12056 struct drm_rect dest = {
12057 /* integer pixels */
12058 .x1 = crtc_x,
12059 .y1 = crtc_y,
12060 .x2 = crtc_x + crtc_w,
12061 .y2 = crtc_y + crtc_h,
12062 };
12063 struct drm_rect src = {
12064 /* 16.16 fixed point */
12065 .x1 = src_x,
12066 .y1 = src_y,
12067 .x2 = src_x + src_w,
12068 .y2 = src_y + src_h,
12069 };
12070 const struct drm_rect clip = {
12071 /* integer pixels */
12072 .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
12073 .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
12074 };
12075 bool visible;
12076 int ret;
12077
12078 ret = drm_plane_helper_check_update(plane, crtc, fb,
12079 &src, &dest, &clip,
12080 DRM_PLANE_HELPER_NO_SCALING,
12081 DRM_PLANE_HELPER_NO_SCALING,
12082 true, true, &visible);
12083 if (ret)
12084 return ret;
12085
12086 crtc->cursor_x = crtc_x;
12087 crtc->cursor_y = crtc_y;
12088 if (fb != crtc->cursor->fb) {
12089 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
12090 } else {
12091 intel_crtc_update_cursor(crtc, visible);
12092
12093 intel_frontbuffer_flip(crtc->dev,
12094 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe));
12095
12096 return 0;
12097 }
12098 }
12099 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
12100 .update_plane = intel_cursor_plane_update,
12101 .disable_plane = intel_cursor_plane_disable,
12102 .destroy = intel_plane_destroy,
12103 };
12104
12105 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12106 int pipe)
12107 {
12108 struct intel_plane *cursor;
12109
12110 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12111 if (cursor == NULL)
12112 return NULL;
12113
12114 cursor->can_scale = false;
12115 cursor->max_downscale = 1;
12116 cursor->pipe = pipe;
12117 cursor->plane = pipe;
12118
12119 drm_universal_plane_init(dev, &cursor->base, 0,
12120 &intel_cursor_plane_funcs,
12121 intel_cursor_formats,
12122 ARRAY_SIZE(intel_cursor_formats),
12123 DRM_PLANE_TYPE_CURSOR);
12124 return &cursor->base;
12125 }
12126
12127 static void intel_crtc_init(struct drm_device *dev, int pipe)
12128 {
12129 struct drm_i915_private *dev_priv = dev->dev_private;
12130 struct intel_crtc *intel_crtc;
12131 struct drm_plane *primary = NULL;
12132 struct drm_plane *cursor = NULL;
12133 int i, ret;
12134
12135 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12136 if (intel_crtc == NULL)
12137 return;
12138
12139 primary = intel_primary_plane_create(dev, pipe);
12140 if (!primary)
12141 goto fail;
12142
12143 cursor = intel_cursor_plane_create(dev, pipe);
12144 if (!cursor)
12145 goto fail;
12146
12147 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12148 cursor, &intel_crtc_funcs);
12149 if (ret)
12150 goto fail;
12151
12152 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12153 for (i = 0; i < 256; i++) {
12154 intel_crtc->lut_r[i] = i;
12155 intel_crtc->lut_g[i] = i;
12156 intel_crtc->lut_b[i] = i;
12157 }
12158
12159 /*
12160 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12161 * is hooked to pipe B. Hence we want plane A feeding pipe B.
12162 */
12163 intel_crtc->pipe = pipe;
12164 intel_crtc->plane = pipe;
12165 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12166 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12167 intel_crtc->plane = !pipe;
12168 }
12169
12170 intel_crtc->cursor_base = ~0;
12171 intel_crtc->cursor_cntl = ~0;
12172 intel_crtc->cursor_size = ~0;
12173
12174 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12175 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12176 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12177 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12178
12179 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12180
12181 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12182 return;
12183
12184 fail:
12185 if (primary)
12186 drm_plane_cleanup(primary);
12187 if (cursor)
12188 drm_plane_cleanup(cursor);
12189 kfree(intel_crtc);
12190 }
12191
12192 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12193 {
12194 struct drm_encoder *encoder = connector->base.encoder;
12195 struct drm_device *dev = connector->base.dev;
12196
12197 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12198
12199 if (!encoder)
12200 return INVALID_PIPE;
12201
12202 return to_intel_crtc(encoder->crtc)->pipe;
12203 }
12204
12205 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12206 struct drm_file *file)
12207 {
12208 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12209 struct drm_crtc *drmmode_crtc;
12210 struct intel_crtc *crtc;
12211
12212 if (!drm_core_check_feature(dev, DRIVER_MODESET))
12213 return -ENODEV;
12214
12215 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12216
12217 if (!drmmode_crtc) {
12218 DRM_ERROR("no such CRTC id\n");
12219 return -ENOENT;
12220 }
12221
12222 crtc = to_intel_crtc(drmmode_crtc);
12223 pipe_from_crtc_id->pipe = crtc->pipe;
12224
12225 return 0;
12226 }
12227
12228 static int intel_encoder_clones(struct intel_encoder *encoder)
12229 {
12230 struct drm_device *dev = encoder->base.dev;
12231 struct intel_encoder *source_encoder;
12232 int index_mask = 0;
12233 int entry = 0;
12234
12235 for_each_intel_encoder(dev, source_encoder) {
12236 if (encoders_cloneable(encoder, source_encoder))
12237 index_mask |= (1 << entry);
12238
12239 entry++;
12240 }
12241
12242 return index_mask;
12243 }
12244
12245 static bool has_edp_a(struct drm_device *dev)
12246 {
12247 struct drm_i915_private *dev_priv = dev->dev_private;
12248
12249 if (!IS_MOBILE(dev))
12250 return false;
12251
12252 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12253 return false;
12254
12255 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12256 return false;
12257
12258 return true;
12259 }
12260
12261 const char *intel_output_name(int output)
12262 {
12263 static const char *names[] = {
12264 [INTEL_OUTPUT_UNUSED] = "Unused",
12265 [INTEL_OUTPUT_ANALOG] = "Analog",
12266 [INTEL_OUTPUT_DVO] = "DVO",
12267 [INTEL_OUTPUT_SDVO] = "SDVO",
12268 [INTEL_OUTPUT_LVDS] = "LVDS",
12269 [INTEL_OUTPUT_TVOUT] = "TV",
12270 [INTEL_OUTPUT_HDMI] = "HDMI",
12271 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
12272 [INTEL_OUTPUT_EDP] = "eDP",
12273 [INTEL_OUTPUT_DSI] = "DSI",
12274 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
12275 };
12276
12277 if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
12278 return "Invalid";
12279
12280 return names[output];
12281 }
12282
12283 static bool intel_crt_present(struct drm_device *dev)
12284 {
12285 struct drm_i915_private *dev_priv = dev->dev_private;
12286
12287 if (IS_ULT(dev))
12288 return false;
12289
12290 if (IS_CHERRYVIEW(dev))
12291 return false;
12292
12293 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12294 return false;
12295
12296 return true;
12297 }
12298
12299 static void intel_setup_outputs(struct drm_device *dev)
12300 {
12301 struct drm_i915_private *dev_priv = dev->dev_private;
12302 struct intel_encoder *encoder;
12303 bool dpd_is_edp = false;
12304
12305 intel_lvds_init(dev);
12306
12307 if (intel_crt_present(dev))
12308 intel_crt_init(dev);
12309
12310 if (HAS_DDI(dev)) {
12311 int found;
12312
12313 /* Haswell uses DDI functions to detect digital outputs */
12314 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12315 /* DDI A only supports eDP */
12316 if (found)
12317 intel_ddi_init(dev, PORT_A);
12318
12319 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12320 * register */
12321 found = I915_READ(SFUSE_STRAP);
12322
12323 if (found & SFUSE_STRAP_DDIB_DETECTED)
12324 intel_ddi_init(dev, PORT_B);
12325 if (found & SFUSE_STRAP_DDIC_DETECTED)
12326 intel_ddi_init(dev, PORT_C);
12327 if (found & SFUSE_STRAP_DDID_DETECTED)
12328 intel_ddi_init(dev, PORT_D);
12329 } else if (HAS_PCH_SPLIT(dev)) {
12330 int found;
12331 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12332
12333 if (has_edp_a(dev))
12334 intel_dp_init(dev, DP_A, PORT_A);
12335
12336 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12337 /* PCH SDVOB multiplex with HDMIB */
12338 found = intel_sdvo_init(dev, PCH_SDVOB, true);
12339 if (!found)
12340 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12341 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12342 intel_dp_init(dev, PCH_DP_B, PORT_B);
12343 }
12344
12345 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12346 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12347
12348 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12349 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12350
12351 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12352 intel_dp_init(dev, PCH_DP_C, PORT_C);
12353
12354 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12355 intel_dp_init(dev, PCH_DP_D, PORT_D);
12356 } else if (IS_VALLEYVIEW(dev)) {
12357 /*
12358 * The DP_DETECTED bit is the latched state of the DDC
12359 * SDA pin at boot. However since eDP doesn't require DDC
12360 * (no way to plug in a DP->HDMI dongle) the DDC pins for
12361 * eDP ports may have been muxed to an alternate function.
12362 * Thus we can't rely on the DP_DETECTED bit alone to detect
12363 * eDP ports. Consult the VBT as well as DP_DETECTED to
12364 * detect eDP ports.
12365 */
12366 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED)
12367 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12368 PORT_B);
12369 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12370 intel_dp_is_edp(dev, PORT_B))
12371 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12372
12373 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED)
12374 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12375 PORT_C);
12376 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12377 intel_dp_is_edp(dev, PORT_C))
12378 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12379
12380 if (IS_CHERRYVIEW(dev)) {
12381 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12382 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12383 PORT_D);
12384 /* eDP not supported on port D, so don't check VBT */
12385 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12386 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12387 }
12388
12389 intel_dsi_init(dev);
12390 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12391 bool found = false;
12392
12393 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12394 DRM_DEBUG_KMS("probing SDVOB\n");
12395 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12396 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12397 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12398 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12399 }
12400
12401 if (!found && SUPPORTS_INTEGRATED_DP(dev))
12402 intel_dp_init(dev, DP_B, PORT_B);
12403 }
12404
12405 /* Before G4X SDVOC doesn't have its own detect register */
12406
12407 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12408 DRM_DEBUG_KMS("probing SDVOC\n");
12409 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12410 }
12411
12412 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12413
12414 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12415 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12416 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12417 }
12418 if (SUPPORTS_INTEGRATED_DP(dev))
12419 intel_dp_init(dev, DP_C, PORT_C);
12420 }
12421
12422 if (SUPPORTS_INTEGRATED_DP(dev) &&
12423 (I915_READ(DP_D) & DP_DETECTED))
12424 intel_dp_init(dev, DP_D, PORT_D);
12425 } else if (IS_GEN2(dev))
12426 intel_dvo_init(dev);
12427
12428 if (SUPPORTS_TV(dev))
12429 intel_tv_init(dev);
12430
12431 intel_edp_psr_init(dev);
12432
12433 for_each_intel_encoder(dev, encoder) {
12434 encoder->base.possible_crtcs = encoder->crtc_mask;
12435 encoder->base.possible_clones =
12436 intel_encoder_clones(encoder);
12437 }
12438
12439 intel_init_pch_refclk(dev);
12440
12441 drm_helper_move_panel_connectors_to_head(dev);
12442 }
12443
12444 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12445 {
12446 struct drm_device *dev = fb->dev;
12447 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12448
12449 drm_framebuffer_cleanup(fb);
12450 mutex_lock(&dev->struct_mutex);
12451 WARN_ON(!intel_fb->obj->framebuffer_references--);
12452 drm_gem_object_unreference(&intel_fb->obj->base);
12453 mutex_unlock(&dev->struct_mutex);
12454 kfree(intel_fb);
12455 }
12456
12457 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12458 struct drm_file *file,
12459 unsigned int *handle)
12460 {
12461 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12462 struct drm_i915_gem_object *obj = intel_fb->obj;
12463
12464 return drm_gem_handle_create(file, &obj->base, handle);
12465 }
12466
12467 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12468 .destroy = intel_user_framebuffer_destroy,
12469 .create_handle = intel_user_framebuffer_create_handle,
12470 };
12471
12472 static int intel_framebuffer_init(struct drm_device *dev,
12473 struct intel_framebuffer *intel_fb,
12474 struct drm_mode_fb_cmd2 *mode_cmd,
12475 struct drm_i915_gem_object *obj)
12476 {
12477 int aligned_height;
12478 int pitch_limit;
12479 int ret;
12480
12481 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12482
12483 if (obj->tiling_mode == I915_TILING_Y) {
12484 DRM_DEBUG("hardware does not support tiling Y\n");
12485 return -EINVAL;
12486 }
12487
12488 if (mode_cmd->pitches[0] & 63) {
12489 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12490 mode_cmd->pitches[0]);
12491 return -EINVAL;
12492 }
12493
12494 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12495 pitch_limit = 32*1024;
12496 } else if (INTEL_INFO(dev)->gen >= 4) {
12497 if (obj->tiling_mode)
12498 pitch_limit = 16*1024;
12499 else
12500 pitch_limit = 32*1024;
12501 } else if (INTEL_INFO(dev)->gen >= 3) {
12502 if (obj->tiling_mode)
12503 pitch_limit = 8*1024;
12504 else
12505 pitch_limit = 16*1024;
12506 } else
12507 /* XXX DSPC is limited to 4k tiled */
12508 pitch_limit = 8*1024;
12509
12510 if (mode_cmd->pitches[0] > pitch_limit) {
12511 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12512 obj->tiling_mode ? "tiled" : "linear",
12513 mode_cmd->pitches[0], pitch_limit);
12514 return -EINVAL;
12515 }
12516
12517 if (obj->tiling_mode != I915_TILING_NONE &&
12518 mode_cmd->pitches[0] != obj->stride) {
12519 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12520 mode_cmd->pitches[0], obj->stride);
12521 return -EINVAL;
12522 }
12523
12524 /* Reject formats not supported by any plane early. */
12525 switch (mode_cmd->pixel_format) {
12526 case DRM_FORMAT_C8:
12527 case DRM_FORMAT_RGB565:
12528 case DRM_FORMAT_XRGB8888:
12529 case DRM_FORMAT_ARGB8888:
12530 break;
12531 case DRM_FORMAT_XRGB1555:
12532 case DRM_FORMAT_ARGB1555:
12533 if (INTEL_INFO(dev)->gen > 3) {
12534 DRM_DEBUG("unsupported pixel format: %s\n",
12535 drm_get_format_name(mode_cmd->pixel_format));
12536 return -EINVAL;
12537 }
12538 break;
12539 case DRM_FORMAT_XBGR8888:
12540 case DRM_FORMAT_ABGR8888:
12541 case DRM_FORMAT_XRGB2101010:
12542 case DRM_FORMAT_ARGB2101010:
12543 case DRM_FORMAT_XBGR2101010:
12544 case DRM_FORMAT_ABGR2101010:
12545 if (INTEL_INFO(dev)->gen < 4) {
12546 DRM_DEBUG("unsupported pixel format: %s\n",
12547 drm_get_format_name(mode_cmd->pixel_format));
12548 return -EINVAL;
12549 }
12550 break;
12551 case DRM_FORMAT_YUYV:
12552 case DRM_FORMAT_UYVY:
12553 case DRM_FORMAT_YVYU:
12554 case DRM_FORMAT_VYUY:
12555 if (INTEL_INFO(dev)->gen < 5) {
12556 DRM_DEBUG("unsupported pixel format: %s\n",
12557 drm_get_format_name(mode_cmd->pixel_format));
12558 return -EINVAL;
12559 }
12560 break;
12561 default:
12562 DRM_DEBUG("unsupported pixel format: %s\n",
12563 drm_get_format_name(mode_cmd->pixel_format));
12564 return -EINVAL;
12565 }
12566
12567 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12568 if (mode_cmd->offsets[0] != 0)
12569 return -EINVAL;
12570
12571 aligned_height = intel_align_height(dev, mode_cmd->height,
12572 obj->tiling_mode);
12573 /* FIXME drm helper for size checks (especially planar formats)? */
12574 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12575 return -EINVAL;
12576
12577 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12578 intel_fb->obj = obj;
12579 intel_fb->obj->framebuffer_references++;
12580
12581 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12582 if (ret) {
12583 DRM_ERROR("framebuffer init failed %d\n", ret);
12584 return ret;
12585 }
12586
12587 return 0;
12588 }
12589
12590 static struct drm_framebuffer *
12591 intel_user_framebuffer_create(struct drm_device *dev,
12592 struct drm_file *filp,
12593 struct drm_mode_fb_cmd2 *mode_cmd)
12594 {
12595 struct drm_i915_gem_object *obj;
12596
12597 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12598 mode_cmd->handles[0]));
12599 if (&obj->base == NULL)
12600 return ERR_PTR(-ENOENT);
12601
12602 return intel_framebuffer_create(dev, mode_cmd, obj);
12603 }
12604
12605 #ifndef CONFIG_DRM_I915_FBDEV
12606 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12607 {
12608 }
12609 #endif
12610
12611 static const struct drm_mode_config_funcs intel_mode_funcs = {
12612 .fb_create = intel_user_framebuffer_create,
12613 .output_poll_changed = intel_fbdev_output_poll_changed,
12614 };
12615
12616 /* Set up chip specific display functions */
12617 static void intel_init_display(struct drm_device *dev)
12618 {
12619 struct drm_i915_private *dev_priv = dev->dev_private;
12620
12621 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12622 dev_priv->display.find_dpll = g4x_find_best_dpll;
12623 else if (IS_CHERRYVIEW(dev))
12624 dev_priv->display.find_dpll = chv_find_best_dpll;
12625 else if (IS_VALLEYVIEW(dev))
12626 dev_priv->display.find_dpll = vlv_find_best_dpll;
12627 else if (IS_PINEVIEW(dev))
12628 dev_priv->display.find_dpll = pnv_find_best_dpll;
12629 else
12630 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12631
12632 if (HAS_DDI(dev)) {
12633 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12634 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12635 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
12636 dev_priv->display.crtc_enable = haswell_crtc_enable;
12637 dev_priv->display.crtc_disable = haswell_crtc_disable;
12638 dev_priv->display.off = ironlake_crtc_off;
12639 dev_priv->display.update_primary_plane =
12640 ironlake_update_primary_plane;
12641 } else if (HAS_PCH_SPLIT(dev)) {
12642 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12643 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12644 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
12645 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12646 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12647 dev_priv->display.off = ironlake_crtc_off;
12648 dev_priv->display.update_primary_plane =
12649 ironlake_update_primary_plane;
12650 } else if (IS_VALLEYVIEW(dev)) {
12651 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12652 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12653 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12654 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12655 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12656 dev_priv->display.off = i9xx_crtc_off;
12657 dev_priv->display.update_primary_plane =
12658 i9xx_update_primary_plane;
12659 } else {
12660 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12661 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12662 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12663 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12664 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12665 dev_priv->display.off = i9xx_crtc_off;
12666 dev_priv->display.update_primary_plane =
12667 i9xx_update_primary_plane;
12668 }
12669
12670 /* Returns the core display clock speed */
12671 if (IS_VALLEYVIEW(dev))
12672 dev_priv->display.get_display_clock_speed =
12673 valleyview_get_display_clock_speed;
12674 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12675 dev_priv->display.get_display_clock_speed =
12676 i945_get_display_clock_speed;
12677 else if (IS_I915G(dev))
12678 dev_priv->display.get_display_clock_speed =
12679 i915_get_display_clock_speed;
12680 else if (IS_I945GM(dev) || IS_845G(dev))
12681 dev_priv->display.get_display_clock_speed =
12682 i9xx_misc_get_display_clock_speed;
12683 else if (IS_PINEVIEW(dev))
12684 dev_priv->display.get_display_clock_speed =
12685 pnv_get_display_clock_speed;
12686 else if (IS_I915GM(dev))
12687 dev_priv->display.get_display_clock_speed =
12688 i915gm_get_display_clock_speed;
12689 else if (IS_I865G(dev))
12690 dev_priv->display.get_display_clock_speed =
12691 i865_get_display_clock_speed;
12692 else if (IS_I85X(dev))
12693 dev_priv->display.get_display_clock_speed =
12694 i855_get_display_clock_speed;
12695 else /* 852, 830 */
12696 dev_priv->display.get_display_clock_speed =
12697 i830_get_display_clock_speed;
12698
12699 if (IS_G4X(dev)) {
12700 dev_priv->display.write_eld = g4x_write_eld;
12701 } else if (IS_GEN5(dev)) {
12702 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12703 dev_priv->display.write_eld = ironlake_write_eld;
12704 } else if (IS_GEN6(dev)) {
12705 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12706 dev_priv->display.write_eld = ironlake_write_eld;
12707 dev_priv->display.modeset_global_resources =
12708 snb_modeset_global_resources;
12709 } else if (IS_IVYBRIDGE(dev)) {
12710 /* FIXME: detect B0+ stepping and use auto training */
12711 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12712 dev_priv->display.write_eld = ironlake_write_eld;
12713 dev_priv->display.modeset_global_resources =
12714 ivb_modeset_global_resources;
12715 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12716 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12717 dev_priv->display.write_eld = haswell_write_eld;
12718 dev_priv->display.modeset_global_resources =
12719 haswell_modeset_global_resources;
12720 } else if (IS_VALLEYVIEW(dev)) {
12721 dev_priv->display.modeset_global_resources =
12722 valleyview_modeset_global_resources;
12723 dev_priv->display.write_eld = ironlake_write_eld;
12724 }
12725
12726 /* Default just returns -ENODEV to indicate unsupported */
12727 dev_priv->display.queue_flip = intel_default_queue_flip;
12728
12729 switch (INTEL_INFO(dev)->gen) {
12730 case 2:
12731 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12732 break;
12733
12734 case 3:
12735 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12736 break;
12737
12738 case 4:
12739 case 5:
12740 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12741 break;
12742
12743 case 6:
12744 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12745 break;
12746 case 7:
12747 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12748 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12749 break;
12750 }
12751
12752 intel_panel_init_backlight_funcs(dev);
12753
12754 mutex_init(&dev_priv->pps_mutex);
12755 }
12756
12757 /*
12758 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12759 * resume, or other times. This quirk makes sure that's the case for
12760 * affected systems.
12761 */
12762 static void quirk_pipea_force(struct drm_device *dev)
12763 {
12764 struct drm_i915_private *dev_priv = dev->dev_private;
12765
12766 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12767 DRM_INFO("applying pipe a force quirk\n");
12768 }
12769
12770 static void quirk_pipeb_force(struct drm_device *dev)
12771 {
12772 struct drm_i915_private *dev_priv = dev->dev_private;
12773
12774 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
12775 DRM_INFO("applying pipe b force quirk\n");
12776 }
12777
12778 /*
12779 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12780 */
12781 static void quirk_ssc_force_disable(struct drm_device *dev)
12782 {
12783 struct drm_i915_private *dev_priv = dev->dev_private;
12784 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12785 DRM_INFO("applying lvds SSC disable quirk\n");
12786 }
12787
12788 /*
12789 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12790 * brightness value
12791 */
12792 static void quirk_invert_brightness(struct drm_device *dev)
12793 {
12794 struct drm_i915_private *dev_priv = dev->dev_private;
12795 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
12796 DRM_INFO("applying inverted panel brightness quirk\n");
12797 }
12798
12799 /* Some VBT's incorrectly indicate no backlight is present */
12800 static void quirk_backlight_present(struct drm_device *dev)
12801 {
12802 struct drm_i915_private *dev_priv = dev->dev_private;
12803 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
12804 DRM_INFO("applying backlight present quirk\n");
12805 }
12806
12807 struct intel_quirk {
12808 int device;
12809 int subsystem_vendor;
12810 int subsystem_device;
12811 void (*hook)(struct drm_device *dev);
12812 };
12813
12814 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12815 struct intel_dmi_quirk {
12816 void (*hook)(struct drm_device *dev);
12817 const struct dmi_system_id (*dmi_id_list)[];
12818 };
12819
12820 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12821 {
12822 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12823 return 1;
12824 }
12825
12826 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12827 {
12828 .dmi_id_list = &(const struct dmi_system_id[]) {
12829 {
12830 .callback = intel_dmi_reverse_brightness,
12831 .ident = "NCR Corporation",
12832 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12833 DMI_MATCH(DMI_PRODUCT_NAME, ""),
12834 },
12835 },
12836 { } /* terminating entry */
12837 },
12838 .hook = quirk_invert_brightness,
12839 },
12840 };
12841
12842 static struct intel_quirk intel_quirks[] = {
12843 /* HP Mini needs pipe A force quirk (LP: #322104) */
12844 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
12845
12846 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12847 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12848
12849 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12850 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12851
12852 /* 830 needs to leave pipe A & dpll A up */
12853 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
12854
12855 /* 830 needs to leave pipe B & dpll B up */
12856 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
12857
12858 /* Lenovo U160 cannot use SSC on LVDS */
12859 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
12860
12861 /* Sony Vaio Y cannot use SSC on LVDS */
12862 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
12863
12864 /* Acer Aspire 5734Z must invert backlight brightness */
12865 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12866
12867 /* Acer/eMachines G725 */
12868 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12869
12870 /* Acer/eMachines e725 */
12871 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12872
12873 /* Acer/Packard Bell NCL20 */
12874 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12875
12876 /* Acer Aspire 4736Z */
12877 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
12878
12879 /* Acer Aspire 5336 */
12880 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
12881
12882 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12883 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
12884
12885 /* Acer C720 Chromebook (Core i3 4005U) */
12886 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
12887
12888 /* Apple Macbook 2,1 (Core 2 T7400) */
12889 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
12890
12891 /* Toshiba CB35 Chromebook (Celeron 2955U) */
12892 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
12893
12894 /* HP Chromebook 14 (Celeron 2955U) */
12895 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
12896 };
12897
12898 static void intel_init_quirks(struct drm_device *dev)
12899 {
12900 struct pci_dev *d = dev->pdev;
12901 int i;
12902
12903 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12904 struct intel_quirk *q = &intel_quirks[i];
12905
12906 if (d->device == q->device &&
12907 (d->subsystem_vendor == q->subsystem_vendor ||
12908 q->subsystem_vendor == PCI_ANY_ID) &&
12909 (d->subsystem_device == q->subsystem_device ||
12910 q->subsystem_device == PCI_ANY_ID))
12911 q->hook(dev);
12912 }
12913 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12914 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12915 intel_dmi_quirks[i].hook(dev);
12916 }
12917 }
12918
12919 /* Disable the VGA plane that we never use */
12920 static void i915_disable_vga(struct drm_device *dev)
12921 {
12922 struct drm_i915_private *dev_priv = dev->dev_private;
12923 u8 sr1;
12924 u32 vga_reg = i915_vgacntrl_reg(dev);
12925
12926 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12927 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
12928 outb(SR01, VGA_SR_INDEX);
12929 sr1 = inb(VGA_SR_DATA);
12930 outb(sr1 | 1<<5, VGA_SR_DATA);
12931 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12932 udelay(300);
12933
12934 /*
12935 * Fujitsu-Siemens Lifebook S6010 (830) has problems resuming
12936 * from S3 without preserving (some of?) the other bits.
12937 */
12938 I915_WRITE(vga_reg, dev_priv->bios_vgacntr | VGA_DISP_DISABLE);
12939 POSTING_READ(vga_reg);
12940 }
12941
12942 void intel_modeset_init_hw(struct drm_device *dev)
12943 {
12944 intel_prepare_ddi(dev);
12945
12946 if (IS_VALLEYVIEW(dev))
12947 vlv_update_cdclk(dev);
12948
12949 intel_init_clock_gating(dev);
12950
12951 intel_enable_gt_powersave(dev);
12952 }
12953
12954 void intel_modeset_suspend_hw(struct drm_device *dev)
12955 {
12956 intel_suspend_hw(dev);
12957 }
12958
12959 void intel_modeset_init(struct drm_device *dev)
12960 {
12961 struct drm_i915_private *dev_priv = dev->dev_private;
12962 int sprite, ret;
12963 enum pipe pipe;
12964 struct intel_crtc *crtc;
12965
12966 drm_mode_config_init(dev);
12967
12968 dev->mode_config.min_width = 0;
12969 dev->mode_config.min_height = 0;
12970
12971 dev->mode_config.preferred_depth = 24;
12972 dev->mode_config.prefer_shadow = 1;
12973
12974 dev->mode_config.funcs = &intel_mode_funcs;
12975
12976 intel_init_quirks(dev);
12977
12978 intel_init_pm(dev);
12979
12980 if (INTEL_INFO(dev)->num_pipes == 0)
12981 return;
12982
12983 intel_init_display(dev);
12984
12985 if (IS_GEN2(dev)) {
12986 dev->mode_config.max_width = 2048;
12987 dev->mode_config.max_height = 2048;
12988 } else if (IS_GEN3(dev)) {
12989 dev->mode_config.max_width = 4096;
12990 dev->mode_config.max_height = 4096;
12991 } else {
12992 dev->mode_config.max_width = 8192;
12993 dev->mode_config.max_height = 8192;
12994 }
12995
12996 if (IS_845G(dev) || IS_I865G(dev)) {
12997 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
12998 dev->mode_config.cursor_height = 1023;
12999 } else if (IS_GEN2(dev)) {
13000 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
13001 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
13002 } else {
13003 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
13004 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
13005 }
13006
13007 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
13008
13009 DRM_DEBUG_KMS("%d display pipe%s available.\n",
13010 INTEL_INFO(dev)->num_pipes,
13011 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
13012
13013 for_each_pipe(dev_priv, pipe) {
13014 intel_crtc_init(dev, pipe);
13015 for_each_sprite(pipe, sprite) {
13016 ret = intel_plane_init(dev, pipe, sprite);
13017 if (ret)
13018 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
13019 pipe_name(pipe), sprite_name(pipe, sprite), ret);
13020 }
13021 }
13022
13023 intel_init_dpio(dev);
13024
13025 intel_shared_dpll_init(dev);
13026
13027 /* save the BIOS value before clobbering it */
13028 dev_priv->bios_vgacntr = I915_READ(i915_vgacntrl_reg(dev));
13029 /* Just disable it once at startup */
13030 i915_disable_vga(dev);
13031 intel_setup_outputs(dev);
13032
13033 /* Just in case the BIOS is doing something questionable. */
13034 intel_disable_fbc(dev);
13035
13036 drm_modeset_lock_all(dev);
13037 intel_modeset_setup_hw_state(dev, false);
13038 drm_modeset_unlock_all(dev);
13039
13040 for_each_intel_crtc(dev, crtc) {
13041 if (!crtc->active)
13042 continue;
13043
13044 /*
13045 * Note that reserving the BIOS fb up front prevents us
13046 * from stuffing other stolen allocations like the ring
13047 * on top. This prevents some ugliness at boot time, and
13048 * can even allow for smooth boot transitions if the BIOS
13049 * fb is large enough for the active pipe configuration.
13050 */
13051 if (dev_priv->display.get_plane_config) {
13052 dev_priv->display.get_plane_config(crtc,
13053 &crtc->plane_config);
13054 /*
13055 * If the fb is shared between multiple heads, we'll
13056 * just get the first one.
13057 */
13058 intel_find_plane_obj(crtc, &crtc->plane_config);
13059 }
13060 }
13061 }
13062
13063 static void intel_enable_pipe_a(struct drm_device *dev)
13064 {
13065 struct intel_connector *connector;
13066 struct drm_connector *crt = NULL;
13067 struct intel_load_detect_pipe load_detect_temp;
13068 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
13069
13070 /* We can't just switch on the pipe A, we need to set things up with a
13071 * proper mode and output configuration. As a gross hack, enable pipe A
13072 * by enabling the load detect pipe once. */
13073 list_for_each_entry(connector,
13074 &dev->mode_config.connector_list,
13075 base.head) {
13076 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13077 crt = &connector->base;
13078 break;
13079 }
13080 }
13081
13082 if (!crt)
13083 return;
13084
13085 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13086 intel_release_load_detect_pipe(crt, &load_detect_temp);
13087 }
13088
13089 static bool
13090 intel_check_plane_mapping(struct intel_crtc *crtc)
13091 {
13092 struct drm_device *dev = crtc->base.dev;
13093 struct drm_i915_private *dev_priv = dev->dev_private;
13094 u32 reg, val;
13095
13096 if (INTEL_INFO(dev)->num_pipes == 1)
13097 return true;
13098
13099 reg = DSPCNTR(!crtc->plane);
13100 val = I915_READ(reg);
13101
13102 if ((val & DISPLAY_PLANE_ENABLE) &&
13103 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13104 return false;
13105
13106 return true;
13107 }
13108
13109 static void intel_sanitize_crtc(struct intel_crtc *crtc)
13110 {
13111 struct drm_device *dev = crtc->base.dev;
13112 struct drm_i915_private *dev_priv = dev->dev_private;
13113 u32 reg;
13114
13115 /* Clear any frame start delays used for debugging left by the BIOS */
13116 reg = PIPECONF(crtc->config.cpu_transcoder);
13117 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13118
13119 /* restore vblank interrupts to correct state */
13120 if (crtc->active) {
13121 update_scanline_offset(crtc);
13122 drm_vblank_on(dev, crtc->pipe);
13123 } else
13124 drm_vblank_off(dev, crtc->pipe);
13125
13126 /* We need to sanitize the plane -> pipe mapping first because this will
13127 * disable the crtc (and hence change the state) if it is wrong. Note
13128 * that gen4+ has a fixed plane -> pipe mapping. */
13129 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13130 struct intel_connector *connector;
13131 bool plane;
13132
13133 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13134 crtc->base.base.id);
13135
13136 /* Pipe has the wrong plane attached and the plane is active.
13137 * Temporarily change the plane mapping and disable everything
13138 * ... */
13139 plane = crtc->plane;
13140 crtc->plane = !plane;
13141 crtc->primary_enabled = true;
13142 dev_priv->display.crtc_disable(&crtc->base);
13143 crtc->plane = plane;
13144
13145 /* ... and break all links. */
13146 list_for_each_entry(connector, &dev->mode_config.connector_list,
13147 base.head) {
13148 if (connector->encoder->base.crtc != &crtc->base)
13149 continue;
13150
13151 connector->base.dpms = DRM_MODE_DPMS_OFF;
13152 connector->base.encoder = NULL;
13153 }
13154 /* multiple connectors may have the same encoder:
13155 * handle them and break crtc link separately */
13156 list_for_each_entry(connector, &dev->mode_config.connector_list,
13157 base.head)
13158 if (connector->encoder->base.crtc == &crtc->base) {
13159 connector->encoder->base.crtc = NULL;
13160 connector->encoder->connectors_active = false;
13161 }
13162
13163 WARN_ON(crtc->active);
13164 crtc->base.enabled = false;
13165 }
13166
13167 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13168 crtc->pipe == PIPE_A && !crtc->active) {
13169 /* BIOS forgot to enable pipe A, this mostly happens after
13170 * resume. Force-enable the pipe to fix this, the update_dpms
13171 * call below we restore the pipe to the right state, but leave
13172 * the required bits on. */
13173 intel_enable_pipe_a(dev);
13174 }
13175
13176 /* Adjust the state of the output pipe according to whether we
13177 * have active connectors/encoders. */
13178 intel_crtc_update_dpms(&crtc->base);
13179
13180 if (crtc->active != crtc->base.enabled) {
13181 struct intel_encoder *encoder;
13182
13183 /* This can happen either due to bugs in the get_hw_state
13184 * functions or because the pipe is force-enabled due to the
13185 * pipe A quirk. */
13186 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13187 crtc->base.base.id,
13188 crtc->base.enabled ? "enabled" : "disabled",
13189 crtc->active ? "enabled" : "disabled");
13190
13191 crtc->base.enabled = crtc->active;
13192
13193 /* Because we only establish the connector -> encoder ->
13194 * crtc links if something is active, this means the
13195 * crtc is now deactivated. Break the links. connector
13196 * -> encoder links are only establish when things are
13197 * actually up, hence no need to break them. */
13198 WARN_ON(crtc->active);
13199
13200 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13201 WARN_ON(encoder->connectors_active);
13202 encoder->base.crtc = NULL;
13203 }
13204 }
13205
13206 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13207 /*
13208 * We start out with underrun reporting disabled to avoid races.
13209 * For correct bookkeeping mark this on active crtcs.
13210 *
13211 * Also on gmch platforms we dont have any hardware bits to
13212 * disable the underrun reporting. Which means we need to start
13213 * out with underrun reporting disabled also on inactive pipes,
13214 * since otherwise we'll complain about the garbage we read when
13215 * e.g. coming up after runtime pm.
13216 *
13217 * No protection against concurrent access is required - at
13218 * worst a fifo underrun happens which also sets this to false.
13219 */
13220 crtc->cpu_fifo_underrun_disabled = true;
13221 crtc->pch_fifo_underrun_disabled = true;
13222 }
13223 }
13224
13225 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13226 {
13227 struct intel_connector *connector;
13228 struct drm_device *dev = encoder->base.dev;
13229
13230 /* We need to check both for a crtc link (meaning that the
13231 * encoder is active and trying to read from a pipe) and the
13232 * pipe itself being active. */
13233 bool has_active_crtc = encoder->base.crtc &&
13234 to_intel_crtc(encoder->base.crtc)->active;
13235
13236 if (encoder->connectors_active && !has_active_crtc) {
13237 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13238 encoder->base.base.id,
13239 encoder->base.name);
13240
13241 /* Connector is active, but has no active pipe. This is
13242 * fallout from our resume register restoring. Disable
13243 * the encoder manually again. */
13244 if (encoder->base.crtc) {
13245 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13246 encoder->base.base.id,
13247 encoder->base.name);
13248 encoder->disable(encoder);
13249 if (encoder->post_disable)
13250 encoder->post_disable(encoder);
13251 }
13252 encoder->base.crtc = NULL;
13253 encoder->connectors_active = false;
13254
13255 /* Inconsistent output/port/pipe state happens presumably due to
13256 * a bug in one of the get_hw_state functions. Or someplace else
13257 * in our code, like the register restore mess on resume. Clamp
13258 * things to off as a safer default. */
13259 list_for_each_entry(connector,
13260 &dev->mode_config.connector_list,
13261 base.head) {
13262 if (connector->encoder != encoder)
13263 continue;
13264 connector->base.dpms = DRM_MODE_DPMS_OFF;
13265 connector->base.encoder = NULL;
13266 }
13267 }
13268 /* Enabled encoders without active connectors will be fixed in
13269 * the crtc fixup. */
13270 }
13271
13272 void i915_redisable_vga_power_on(struct drm_device *dev)
13273 {
13274 struct drm_i915_private *dev_priv = dev->dev_private;
13275 u32 vga_reg = i915_vgacntrl_reg(dev);
13276
13277 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13278 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13279 i915_disable_vga(dev);
13280 }
13281 }
13282
13283 void i915_redisable_vga(struct drm_device *dev)
13284 {
13285 struct drm_i915_private *dev_priv = dev->dev_private;
13286
13287 /* This function can be called both from intel_modeset_setup_hw_state or
13288 * at a very early point in our resume sequence, where the power well
13289 * structures are not yet restored. Since this function is at a very
13290 * paranoid "someone might have enabled VGA while we were not looking"
13291 * level, just check if the power well is enabled instead of trying to
13292 * follow the "don't touch the power well if we don't need it" policy
13293 * the rest of the driver uses. */
13294 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
13295 return;
13296
13297 i915_redisable_vga_power_on(dev);
13298 }
13299
13300 static bool primary_get_hw_state(struct intel_crtc *crtc)
13301 {
13302 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13303
13304 if (!crtc->active)
13305 return false;
13306
13307 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13308 }
13309
13310 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13311 {
13312 struct drm_i915_private *dev_priv = dev->dev_private;
13313 enum pipe pipe;
13314 struct intel_crtc *crtc;
13315 struct intel_encoder *encoder;
13316 struct intel_connector *connector;
13317 int i;
13318
13319 for_each_intel_crtc(dev, crtc) {
13320 memset(&crtc->config, 0, sizeof(crtc->config));
13321
13322 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13323
13324 crtc->active = dev_priv->display.get_pipe_config(crtc,
13325 &crtc->config);
13326
13327 crtc->base.enabled = crtc->active;
13328 crtc->primary_enabled = primary_get_hw_state(crtc);
13329
13330 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13331 crtc->base.base.id,
13332 crtc->active ? "enabled" : "disabled");
13333 }
13334
13335 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13336 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13337
13338 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
13339 pll->active = 0;
13340 for_each_intel_crtc(dev, crtc) {
13341 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
13342 pll->active++;
13343 }
13344 pll->refcount = pll->active;
13345
13346 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
13347 pll->name, pll->refcount, pll->on);
13348
13349 if (pll->refcount)
13350 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13351 }
13352
13353 for_each_intel_encoder(dev, encoder) {
13354 pipe = 0;
13355
13356 if (encoder->get_hw_state(encoder, &pipe)) {
13357 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13358 encoder->base.crtc = &crtc->base;
13359 encoder->get_config(encoder, &crtc->config);
13360 } else {
13361 encoder->base.crtc = NULL;
13362 }
13363
13364 encoder->connectors_active = false;
13365 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13366 encoder->base.base.id,
13367 encoder->base.name,
13368 encoder->base.crtc ? "enabled" : "disabled",
13369 pipe_name(pipe));
13370 }
13371
13372 list_for_each_entry(connector, &dev->mode_config.connector_list,
13373 base.head) {
13374 if (connector->get_hw_state(connector)) {
13375 connector->base.dpms = DRM_MODE_DPMS_ON;
13376 connector->encoder->connectors_active = true;
13377 connector->base.encoder = &connector->encoder->base;
13378 } else {
13379 connector->base.dpms = DRM_MODE_DPMS_OFF;
13380 connector->base.encoder = NULL;
13381 }
13382 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13383 connector->base.base.id,
13384 connector->base.name,
13385 connector->base.encoder ? "enabled" : "disabled");
13386 }
13387 }
13388
13389 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13390 * and i915 state tracking structures. */
13391 void intel_modeset_setup_hw_state(struct drm_device *dev,
13392 bool force_restore)
13393 {
13394 struct drm_i915_private *dev_priv = dev->dev_private;
13395 enum pipe pipe;
13396 struct intel_crtc *crtc;
13397 struct intel_encoder *encoder;
13398 int i;
13399
13400 intel_modeset_readout_hw_state(dev);
13401
13402 /*
13403 * Now that we have the config, copy it to each CRTC struct
13404 * Note that this could go away if we move to using crtc_config
13405 * checking everywhere.
13406 */
13407 for_each_intel_crtc(dev, crtc) {
13408 if (crtc->active && i915.fastboot) {
13409 intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
13410 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13411 crtc->base.base.id);
13412 drm_mode_debug_printmodeline(&crtc->base.mode);
13413 }
13414 }
13415
13416 /* HW state is read out, now we need to sanitize this mess. */
13417 for_each_intel_encoder(dev, encoder) {
13418 intel_sanitize_encoder(encoder);
13419 }
13420
13421 for_each_pipe(dev_priv, pipe) {
13422 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13423 intel_sanitize_crtc(crtc);
13424 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
13425 }
13426
13427 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13428 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13429
13430 if (!pll->on || pll->active)
13431 continue;
13432
13433 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13434
13435 pll->disable(dev_priv, pll);
13436 pll->on = false;
13437 }
13438
13439 if (HAS_PCH_SPLIT(dev))
13440 ilk_wm_get_hw_state(dev);
13441
13442 if (force_restore) {
13443 i915_redisable_vga(dev);
13444
13445 /*
13446 * We need to use raw interfaces for restoring state to avoid
13447 * checking (bogus) intermediate states.
13448 */
13449 for_each_pipe(dev_priv, pipe) {
13450 struct drm_crtc *crtc =
13451 dev_priv->pipe_to_crtc_mapping[pipe];
13452
13453 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13454 crtc->primary->fb);
13455 }
13456 } else {
13457 intel_modeset_update_staged_output_state(dev);
13458 }
13459
13460 intel_modeset_check_state(dev);
13461 }
13462
13463 void intel_modeset_gem_init(struct drm_device *dev)
13464 {
13465 struct drm_crtc *c;
13466 struct drm_i915_gem_object *obj;
13467
13468 mutex_lock(&dev->struct_mutex);
13469 intel_init_gt_powersave(dev);
13470 mutex_unlock(&dev->struct_mutex);
13471
13472 intel_modeset_init_hw(dev);
13473
13474 intel_setup_overlay(dev);
13475
13476 /*
13477 * Make sure any fbs we allocated at startup are properly
13478 * pinned & fenced. When we do the allocation it's too early
13479 * for this.
13480 */
13481 mutex_lock(&dev->struct_mutex);
13482 for_each_crtc(dev, c) {
13483 obj = intel_fb_obj(c->primary->fb);
13484 if (obj == NULL)
13485 continue;
13486
13487 if (intel_pin_and_fence_fb_obj(dev, obj, NULL)) {
13488 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13489 to_intel_crtc(c)->pipe);
13490 drm_framebuffer_unreference(c->primary->fb);
13491 c->primary->fb = NULL;
13492 }
13493 }
13494 mutex_unlock(&dev->struct_mutex);
13495 }
13496
13497 void intel_connector_unregister(struct intel_connector *intel_connector)
13498 {
13499 struct drm_connector *connector = &intel_connector->base;
13500
13501 intel_panel_destroy_backlight(connector);
13502 drm_connector_unregister(connector);
13503 }
13504
13505 void intel_modeset_cleanup(struct drm_device *dev)
13506 {
13507 struct drm_i915_private *dev_priv = dev->dev_private;
13508 struct drm_connector *connector;
13509
13510 /*
13511 * Interrupts and polling as the first thing to avoid creating havoc.
13512 * Too much stuff here (turning of rps, connectors, ...) would
13513 * experience fancy races otherwise.
13514 */
13515 drm_irq_uninstall(dev);
13516 intel_hpd_cancel_work(dev_priv);
13517 dev_priv->pm._irqs_disabled = true;
13518
13519 /*
13520 * Due to the hpd irq storm handling the hotplug work can re-arm the
13521 * poll handlers. Hence disable polling after hpd handling is shut down.
13522 */
13523 drm_kms_helper_poll_fini(dev);
13524
13525 mutex_lock(&dev->struct_mutex);
13526
13527 intel_unregister_dsm_handler();
13528
13529 intel_disable_fbc(dev);
13530
13531 intel_disable_gt_powersave(dev);
13532
13533 ironlake_teardown_rc6(dev);
13534
13535 mutex_unlock(&dev->struct_mutex);
13536
13537 /* flush any delayed tasks or pending work */
13538 flush_scheduled_work();
13539
13540 /* destroy the backlight and sysfs files before encoders/connectors */
13541 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13542 struct intel_connector *intel_connector;
13543
13544 intel_connector = to_intel_connector(connector);
13545 intel_connector->unregister(intel_connector);
13546 }
13547
13548 drm_mode_config_cleanup(dev);
13549
13550 intel_cleanup_overlay(dev);
13551
13552 mutex_lock(&dev->struct_mutex);
13553 intel_cleanup_gt_powersave(dev);
13554 mutex_unlock(&dev->struct_mutex);
13555 }
13556
13557 /*
13558 * Return which encoder is currently attached for connector.
13559 */
13560 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13561 {
13562 return &intel_attached_encoder(connector)->base;
13563 }
13564
13565 void intel_connector_attach_encoder(struct intel_connector *connector,
13566 struct intel_encoder *encoder)
13567 {
13568 connector->encoder = encoder;
13569 drm_mode_connector_attach_encoder(&connector->base,
13570 &encoder->base);
13571 }
13572
13573 /*
13574 * set vga decode state - true == enable VGA decode
13575 */
13576 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13577 {
13578 struct drm_i915_private *dev_priv = dev->dev_private;
13579 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13580 u16 gmch_ctrl;
13581
13582 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13583 DRM_ERROR("failed to read control word\n");
13584 return -EIO;
13585 }
13586
13587 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13588 return 0;
13589
13590 if (state)
13591 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13592 else
13593 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13594
13595 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13596 DRM_ERROR("failed to write control word\n");
13597 return -EIO;
13598 }
13599
13600 return 0;
13601 }
13602
13603 struct intel_display_error_state {
13604
13605 u32 power_well_driver;
13606
13607 int num_transcoders;
13608
13609 struct intel_cursor_error_state {
13610 u32 control;
13611 u32 position;
13612 u32 base;
13613 u32 size;
13614 } cursor[I915_MAX_PIPES];
13615
13616 struct intel_pipe_error_state {
13617 bool power_domain_on;
13618 u32 source;
13619 u32 stat;
13620 } pipe[I915_MAX_PIPES];
13621
13622 struct intel_plane_error_state {
13623 u32 control;
13624 u32 stride;
13625 u32 size;
13626 u32 pos;
13627 u32 addr;
13628 u32 surface;
13629 u32 tile_offset;
13630 } plane[I915_MAX_PIPES];
13631
13632 struct intel_transcoder_error_state {
13633 bool power_domain_on;
13634 enum transcoder cpu_transcoder;
13635
13636 u32 conf;
13637
13638 u32 htotal;
13639 u32 hblank;
13640 u32 hsync;
13641 u32 vtotal;
13642 u32 vblank;
13643 u32 vsync;
13644 } transcoder[4];
13645 };
13646
13647 struct intel_display_error_state *
13648 intel_display_capture_error_state(struct drm_device *dev)
13649 {
13650 struct drm_i915_private *dev_priv = dev->dev_private;
13651 struct intel_display_error_state *error;
13652 int transcoders[] = {
13653 TRANSCODER_A,
13654 TRANSCODER_B,
13655 TRANSCODER_C,
13656 TRANSCODER_EDP,
13657 };
13658 int i;
13659
13660 if (INTEL_INFO(dev)->num_pipes == 0)
13661 return NULL;
13662
13663 error = kzalloc(sizeof(*error), GFP_ATOMIC);
13664 if (error == NULL)
13665 return NULL;
13666
13667 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13668 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13669
13670 for_each_pipe(dev_priv, i) {
13671 error->pipe[i].power_domain_on =
13672 intel_display_power_enabled_unlocked(dev_priv,
13673 POWER_DOMAIN_PIPE(i));
13674 if (!error->pipe[i].power_domain_on)
13675 continue;
13676
13677 error->cursor[i].control = I915_READ(CURCNTR(i));
13678 error->cursor[i].position = I915_READ(CURPOS(i));
13679 error->cursor[i].base = I915_READ(CURBASE(i));
13680
13681 error->plane[i].control = I915_READ(DSPCNTR(i));
13682 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13683 if (INTEL_INFO(dev)->gen <= 3) {
13684 error->plane[i].size = I915_READ(DSPSIZE(i));
13685 error->plane[i].pos = I915_READ(DSPPOS(i));
13686 }
13687 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13688 error->plane[i].addr = I915_READ(DSPADDR(i));
13689 if (INTEL_INFO(dev)->gen >= 4) {
13690 error->plane[i].surface = I915_READ(DSPSURF(i));
13691 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13692 }
13693
13694 error->pipe[i].source = I915_READ(PIPESRC(i));
13695
13696 if (HAS_GMCH_DISPLAY(dev))
13697 error->pipe[i].stat = I915_READ(PIPESTAT(i));
13698 }
13699
13700 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13701 if (HAS_DDI(dev_priv->dev))
13702 error->num_transcoders++; /* Account for eDP. */
13703
13704 for (i = 0; i < error->num_transcoders; i++) {
13705 enum transcoder cpu_transcoder = transcoders[i];
13706
13707 error->transcoder[i].power_domain_on =
13708 intel_display_power_enabled_unlocked(dev_priv,
13709 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13710 if (!error->transcoder[i].power_domain_on)
13711 continue;
13712
13713 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13714
13715 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13716 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13717 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13718 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13719 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13720 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13721 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13722 }
13723
13724 return error;
13725 }
13726
13727 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13728
13729 void
13730 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13731 struct drm_device *dev,
13732 struct intel_display_error_state *error)
13733 {
13734 struct drm_i915_private *dev_priv = dev->dev_private;
13735 int i;
13736
13737 if (!error)
13738 return;
13739
13740 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13741 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13742 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13743 error->power_well_driver);
13744 for_each_pipe(dev_priv, i) {
13745 err_printf(m, "Pipe [%d]:\n", i);
13746 err_printf(m, " Power: %s\n",
13747 error->pipe[i].power_domain_on ? "on" : "off");
13748 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
13749 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
13750
13751 err_printf(m, "Plane [%d]:\n", i);
13752 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
13753 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
13754 if (INTEL_INFO(dev)->gen <= 3) {
13755 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
13756 err_printf(m, " POS: %08x\n", error->plane[i].pos);
13757 }
13758 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13759 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
13760 if (INTEL_INFO(dev)->gen >= 4) {
13761 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
13762 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
13763 }
13764
13765 err_printf(m, "Cursor [%d]:\n", i);
13766 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
13767 err_printf(m, " POS: %08x\n", error->cursor[i].position);
13768 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
13769 }
13770
13771 for (i = 0; i < error->num_transcoders; i++) {
13772 err_printf(m, "CPU transcoder: %c\n",
13773 transcoder_name(error->transcoder[i].cpu_transcoder));
13774 err_printf(m, " Power: %s\n",
13775 error->transcoder[i].power_domain_on ? "on" : "off");
13776 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
13777 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
13778 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
13779 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
13780 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
13781 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
13782 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
13783 }
13784 }
13785
13786 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
13787 {
13788 struct intel_crtc *crtc;
13789
13790 for_each_intel_crtc(dev, crtc) {
13791 struct intel_unpin_work *work;
13792 unsigned long irqflags;
13793
13794 spin_lock_irqsave(&dev->event_lock, irqflags);
13795
13796 work = crtc->unpin_work;
13797
13798 if (work && work->event &&
13799 work->event->base.file_priv == file) {
13800 kfree(work->event);
13801 work->event = NULL;
13802 }
13803
13804 spin_unlock_irqrestore(&dev->event_lock, irqflags);
13805 }
13806 }
Linux kernel - Deliverables
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