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drm/i915: Continuation of future readiness series
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_rect.h>
44 #include <linux/dma_remapping.h>
45
46 /* Primary plane formats supported by all gen */
47 #define COMMON_PRIMARY_FORMATS \
48 DRM_FORMAT_C8, \
49 DRM_FORMAT_RGB565, \
50 DRM_FORMAT_XRGB8888, \
51 DRM_FORMAT_ARGB8888
52
53 /* Primary plane formats for gen <= 3 */
54 static const uint32_t intel_primary_formats_gen2[] = {
55 COMMON_PRIMARY_FORMATS,
56 DRM_FORMAT_XRGB1555,
57 DRM_FORMAT_ARGB1555,
58 };
59
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t intel_primary_formats_gen4[] = {
62 COMMON_PRIMARY_FORMATS, \
63 DRM_FORMAT_XBGR8888,
64 DRM_FORMAT_ABGR8888,
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_ARGB2101010,
67 DRM_FORMAT_XBGR2101010,
68 DRM_FORMAT_ABGR2101010,
69 };
70
71 /* Cursor formats */
72 static const uint32_t intel_cursor_formats[] = {
73 DRM_FORMAT_ARGB8888,
74 };
75
76 #define DIV_ROUND_CLOSEST_ULL(ll, d) \
77 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
78
79 static void intel_increase_pllclock(struct drm_device *dev,
80 enum pipe pipe);
81 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
82
83 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
84 struct intel_crtc_config *pipe_config);
85 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
86 struct intel_crtc_config *pipe_config);
87
88 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
89 int x, int y, struct drm_framebuffer *old_fb);
90 static int intel_framebuffer_init(struct drm_device *dev,
91 struct intel_framebuffer *ifb,
92 struct drm_mode_fb_cmd2 *mode_cmd,
93 struct drm_i915_gem_object *obj);
94 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
95 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
96 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
97 struct intel_link_m_n *m_n,
98 struct intel_link_m_n *m2_n2);
99 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
100 static void haswell_set_pipeconf(struct drm_crtc *crtc);
101 static void intel_set_pipe_csc(struct drm_crtc *crtc);
102 static void vlv_prepare_pll(struct intel_crtc *crtc);
103 static void chv_prepare_pll(struct intel_crtc *crtc);
104
105 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
106 {
107 if (!connector->mst_port)
108 return connector->encoder;
109 else
110 return &connector->mst_port->mst_encoders[pipe]->base;
111 }
112
113 typedef struct {
114 int min, max;
115 } intel_range_t;
116
117 typedef struct {
118 int dot_limit;
119 int p2_slow, p2_fast;
120 } intel_p2_t;
121
122 typedef struct intel_limit intel_limit_t;
123 struct intel_limit {
124 intel_range_t dot, vco, n, m, m1, m2, p, p1;
125 intel_p2_t p2;
126 };
127
128 int
129 intel_pch_rawclk(struct drm_device *dev)
130 {
131 struct drm_i915_private *dev_priv = dev->dev_private;
132
133 WARN_ON(!HAS_PCH_SPLIT(dev));
134
135 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
136 }
137
138 static inline u32 /* units of 100MHz */
139 intel_fdi_link_freq(struct drm_device *dev)
140 {
141 if (IS_GEN5(dev)) {
142 struct drm_i915_private *dev_priv = dev->dev_private;
143 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
144 } else
145 return 27;
146 }
147
148 static const intel_limit_t intel_limits_i8xx_dac = {
149 .dot = { .min = 25000, .max = 350000 },
150 .vco = { .min = 908000, .max = 1512000 },
151 .n = { .min = 2, .max = 16 },
152 .m = { .min = 96, .max = 140 },
153 .m1 = { .min = 18, .max = 26 },
154 .m2 = { .min = 6, .max = 16 },
155 .p = { .min = 4, .max = 128 },
156 .p1 = { .min = 2, .max = 33 },
157 .p2 = { .dot_limit = 165000,
158 .p2_slow = 4, .p2_fast = 2 },
159 };
160
161 static const intel_limit_t intel_limits_i8xx_dvo = {
162 .dot = { .min = 25000, .max = 350000 },
163 .vco = { .min = 908000, .max = 1512000 },
164 .n = { .min = 2, .max = 16 },
165 .m = { .min = 96, .max = 140 },
166 .m1 = { .min = 18, .max = 26 },
167 .m2 = { .min = 6, .max = 16 },
168 .p = { .min = 4, .max = 128 },
169 .p1 = { .min = 2, .max = 33 },
170 .p2 = { .dot_limit = 165000,
171 .p2_slow = 4, .p2_fast = 4 },
172 };
173
174 static const intel_limit_t intel_limits_i8xx_lvds = {
175 .dot = { .min = 25000, .max = 350000 },
176 .vco = { .min = 908000, .max = 1512000 },
177 .n = { .min = 2, .max = 16 },
178 .m = { .min = 96, .max = 140 },
179 .m1 = { .min = 18, .max = 26 },
180 .m2 = { .min = 6, .max = 16 },
181 .p = { .min = 4, .max = 128 },
182 .p1 = { .min = 1, .max = 6 },
183 .p2 = { .dot_limit = 165000,
184 .p2_slow = 14, .p2_fast = 7 },
185 };
186
187 static const intel_limit_t intel_limits_i9xx_sdvo = {
188 .dot = { .min = 20000, .max = 400000 },
189 .vco = { .min = 1400000, .max = 2800000 },
190 .n = { .min = 1, .max = 6 },
191 .m = { .min = 70, .max = 120 },
192 .m1 = { .min = 8, .max = 18 },
193 .m2 = { .min = 3, .max = 7 },
194 .p = { .min = 5, .max = 80 },
195 .p1 = { .min = 1, .max = 8 },
196 .p2 = { .dot_limit = 200000,
197 .p2_slow = 10, .p2_fast = 5 },
198 };
199
200 static const intel_limit_t intel_limits_i9xx_lvds = {
201 .dot = { .min = 20000, .max = 400000 },
202 .vco = { .min = 1400000, .max = 2800000 },
203 .n = { .min = 1, .max = 6 },
204 .m = { .min = 70, .max = 120 },
205 .m1 = { .min = 8, .max = 18 },
206 .m2 = { .min = 3, .max = 7 },
207 .p = { .min = 7, .max = 98 },
208 .p1 = { .min = 1, .max = 8 },
209 .p2 = { .dot_limit = 112000,
210 .p2_slow = 14, .p2_fast = 7 },
211 };
212
213
214 static const intel_limit_t intel_limits_g4x_sdvo = {
215 .dot = { .min = 25000, .max = 270000 },
216 .vco = { .min = 1750000, .max = 3500000},
217 .n = { .min = 1, .max = 4 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 10, .max = 30 },
222 .p1 = { .min = 1, .max = 3},
223 .p2 = { .dot_limit = 270000,
224 .p2_slow = 10,
225 .p2_fast = 10
226 },
227 };
228
229 static const intel_limit_t intel_limits_g4x_hdmi = {
230 .dot = { .min = 22000, .max = 400000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 4 },
233 .m = { .min = 104, .max = 138 },
234 .m1 = { .min = 16, .max = 23 },
235 .m2 = { .min = 5, .max = 11 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8},
238 .p2 = { .dot_limit = 165000,
239 .p2_slow = 10, .p2_fast = 5 },
240 };
241
242 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
243 .dot = { .min = 20000, .max = 115000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 14, .p2_fast = 14
253 },
254 };
255
256 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
257 .dot = { .min = 80000, .max = 224000 },
258 .vco = { .min = 1750000, .max = 3500000 },
259 .n = { .min = 1, .max = 3 },
260 .m = { .min = 104, .max = 138 },
261 .m1 = { .min = 17, .max = 23 },
262 .m2 = { .min = 5, .max = 11 },
263 .p = { .min = 14, .max = 42 },
264 .p1 = { .min = 2, .max = 6 },
265 .p2 = { .dot_limit = 0,
266 .p2_slow = 7, .p2_fast = 7
267 },
268 };
269
270 static const intel_limit_t intel_limits_pineview_sdvo = {
271 .dot = { .min = 20000, .max = 400000},
272 .vco = { .min = 1700000, .max = 3500000 },
273 /* Pineview's Ncounter is a ring counter */
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 /* Pineview only has one combined m divider, which we treat as m2. */
277 .m1 = { .min = 0, .max = 0 },
278 .m2 = { .min = 0, .max = 254 },
279 .p = { .min = 5, .max = 80 },
280 .p1 = { .min = 1, .max = 8 },
281 .p2 = { .dot_limit = 200000,
282 .p2_slow = 10, .p2_fast = 5 },
283 };
284
285 static const intel_limit_t intel_limits_pineview_lvds = {
286 .dot = { .min = 20000, .max = 400000 },
287 .vco = { .min = 1700000, .max = 3500000 },
288 .n = { .min = 3, .max = 6 },
289 .m = { .min = 2, .max = 256 },
290 .m1 = { .min = 0, .max = 0 },
291 .m2 = { .min = 0, .max = 254 },
292 .p = { .min = 7, .max = 112 },
293 .p1 = { .min = 1, .max = 8 },
294 .p2 = { .dot_limit = 112000,
295 .p2_slow = 14, .p2_fast = 14 },
296 };
297
298 /* Ironlake / Sandybridge
299 *
300 * We calculate clock using (register_value + 2) for N/M1/M2, so here
301 * the range value for them is (actual_value - 2).
302 */
303 static const intel_limit_t intel_limits_ironlake_dac = {
304 .dot = { .min = 25000, .max = 350000 },
305 .vco = { .min = 1760000, .max = 3510000 },
306 .n = { .min = 1, .max = 5 },
307 .m = { .min = 79, .max = 127 },
308 .m1 = { .min = 12, .max = 22 },
309 .m2 = { .min = 5, .max = 9 },
310 .p = { .min = 5, .max = 80 },
311 .p1 = { .min = 1, .max = 8 },
312 .p2 = { .dot_limit = 225000,
313 .p2_slow = 10, .p2_fast = 5 },
314 };
315
316 static const intel_limit_t intel_limits_ironlake_single_lvds = {
317 .dot = { .min = 25000, .max = 350000 },
318 .vco = { .min = 1760000, .max = 3510000 },
319 .n = { .min = 1, .max = 3 },
320 .m = { .min = 79, .max = 118 },
321 .m1 = { .min = 12, .max = 22 },
322 .m2 = { .min = 5, .max = 9 },
323 .p = { .min = 28, .max = 112 },
324 .p1 = { .min = 2, .max = 8 },
325 .p2 = { .dot_limit = 225000,
326 .p2_slow = 14, .p2_fast = 14 },
327 };
328
329 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
330 .dot = { .min = 25000, .max = 350000 },
331 .vco = { .min = 1760000, .max = 3510000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 79, .max = 127 },
334 .m1 = { .min = 12, .max = 22 },
335 .m2 = { .min = 5, .max = 9 },
336 .p = { .min = 14, .max = 56 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 225000,
339 .p2_slow = 7, .p2_fast = 7 },
340 };
341
342 /* LVDS 100mhz refclk limits. */
343 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
344 .dot = { .min = 25000, .max = 350000 },
345 .vco = { .min = 1760000, .max = 3510000 },
346 .n = { .min = 1, .max = 2 },
347 .m = { .min = 79, .max = 126 },
348 .m1 = { .min = 12, .max = 22 },
349 .m2 = { .min = 5, .max = 9 },
350 .p = { .min = 28, .max = 112 },
351 .p1 = { .min = 2, .max = 8 },
352 .p2 = { .dot_limit = 225000,
353 .p2_slow = 14, .p2_fast = 14 },
354 };
355
356 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
357 .dot = { .min = 25000, .max = 350000 },
358 .vco = { .min = 1760000, .max = 3510000 },
359 .n = { .min = 1, .max = 3 },
360 .m = { .min = 79, .max = 126 },
361 .m1 = { .min = 12, .max = 22 },
362 .m2 = { .min = 5, .max = 9 },
363 .p = { .min = 14, .max = 42 },
364 .p1 = { .min = 2, .max = 6 },
365 .p2 = { .dot_limit = 225000,
366 .p2_slow = 7, .p2_fast = 7 },
367 };
368
369 static const intel_limit_t intel_limits_vlv = {
370 /*
371 * These are the data rate limits (measured in fast clocks)
372 * since those are the strictest limits we have. The fast
373 * clock and actual rate limits are more relaxed, so checking
374 * them would make no difference.
375 */
376 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m1 = { .min = 2, .max = 3 },
380 .m2 = { .min = 11, .max = 156 },
381 .p1 = { .min = 2, .max = 3 },
382 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
383 };
384
385 static const intel_limit_t intel_limits_chv = {
386 /*
387 * These are the data rate limits (measured in fast clocks)
388 * since those are the strictest limits we have. The fast
389 * clock and actual rate limits are more relaxed, so checking
390 * them would make no difference.
391 */
392 .dot = { .min = 25000 * 5, .max = 540000 * 5},
393 .vco = { .min = 4860000, .max = 6700000 },
394 .n = { .min = 1, .max = 1 },
395 .m1 = { .min = 2, .max = 2 },
396 .m2 = { .min = 24 << 22, .max = 175 << 22 },
397 .p1 = { .min = 2, .max = 4 },
398 .p2 = { .p2_slow = 1, .p2_fast = 14 },
399 };
400
401 static void vlv_clock(int refclk, intel_clock_t *clock)
402 {
403 clock->m = clock->m1 * clock->m2;
404 clock->p = clock->p1 * clock->p2;
405 if (WARN_ON(clock->n == 0 || clock->p == 0))
406 return;
407 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
408 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
409 }
410
411 /**
412 * Returns whether any output on the specified pipe is of the specified type
413 */
414 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
415 {
416 struct drm_device *dev = crtc->dev;
417 struct intel_encoder *encoder;
418
419 for_each_encoder_on_crtc(dev, crtc, encoder)
420 if (encoder->type == type)
421 return true;
422
423 return false;
424 }
425
426 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
427 int refclk)
428 {
429 struct drm_device *dev = crtc->dev;
430 const intel_limit_t *limit;
431
432 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
433 if (intel_is_dual_link_lvds(dev)) {
434 if (refclk == 100000)
435 limit = &intel_limits_ironlake_dual_lvds_100m;
436 else
437 limit = &intel_limits_ironlake_dual_lvds;
438 } else {
439 if (refclk == 100000)
440 limit = &intel_limits_ironlake_single_lvds_100m;
441 else
442 limit = &intel_limits_ironlake_single_lvds;
443 }
444 } else
445 limit = &intel_limits_ironlake_dac;
446
447 return limit;
448 }
449
450 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
451 {
452 struct drm_device *dev = crtc->dev;
453 const intel_limit_t *limit;
454
455 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
456 if (intel_is_dual_link_lvds(dev))
457 limit = &intel_limits_g4x_dual_channel_lvds;
458 else
459 limit = &intel_limits_g4x_single_channel_lvds;
460 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
461 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
462 limit = &intel_limits_g4x_hdmi;
463 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
464 limit = &intel_limits_g4x_sdvo;
465 } else /* The option is for other outputs */
466 limit = &intel_limits_i9xx_sdvo;
467
468 return limit;
469 }
470
471 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
472 {
473 struct drm_device *dev = crtc->dev;
474 const intel_limit_t *limit;
475
476 if (HAS_PCH_SPLIT(dev))
477 limit = intel_ironlake_limit(crtc, refclk);
478 else if (IS_G4X(dev)) {
479 limit = intel_g4x_limit(crtc);
480 } else if (IS_PINEVIEW(dev)) {
481 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
482 limit = &intel_limits_pineview_lvds;
483 else
484 limit = &intel_limits_pineview_sdvo;
485 } else if (IS_CHERRYVIEW(dev)) {
486 limit = &intel_limits_chv;
487 } else if (IS_VALLEYVIEW(dev)) {
488 limit = &intel_limits_vlv;
489 } else if (!IS_GEN2(dev)) {
490 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
491 limit = &intel_limits_i9xx_lvds;
492 else
493 limit = &intel_limits_i9xx_sdvo;
494 } else {
495 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
496 limit = &intel_limits_i8xx_lvds;
497 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
498 limit = &intel_limits_i8xx_dvo;
499 else
500 limit = &intel_limits_i8xx_dac;
501 }
502 return limit;
503 }
504
505 /* m1 is reserved as 0 in Pineview, n is a ring counter */
506 static void pineview_clock(int refclk, intel_clock_t *clock)
507 {
508 clock->m = clock->m2 + 2;
509 clock->p = clock->p1 * clock->p2;
510 if (WARN_ON(clock->n == 0 || clock->p == 0))
511 return;
512 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
513 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
514 }
515
516 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
517 {
518 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
519 }
520
521 static void i9xx_clock(int refclk, intel_clock_t *clock)
522 {
523 clock->m = i9xx_dpll_compute_m(clock);
524 clock->p = clock->p1 * clock->p2;
525 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
526 return;
527 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
528 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
529 }
530
531 static void chv_clock(int refclk, intel_clock_t *clock)
532 {
533 clock->m = clock->m1 * clock->m2;
534 clock->p = clock->p1 * clock->p2;
535 if (WARN_ON(clock->n == 0 || clock->p == 0))
536 return;
537 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
538 clock->n << 22);
539 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
540 }
541
542 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
543 /**
544 * Returns whether the given set of divisors are valid for a given refclk with
545 * the given connectors.
546 */
547
548 static bool intel_PLL_is_valid(struct drm_device *dev,
549 const intel_limit_t *limit,
550 const intel_clock_t *clock)
551 {
552 if (clock->n < limit->n.min || limit->n.max < clock->n)
553 INTELPllInvalid("n out of range\n");
554 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
555 INTELPllInvalid("p1 out of range\n");
556 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
557 INTELPllInvalid("m2 out of range\n");
558 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
559 INTELPllInvalid("m1 out of range\n");
560
561 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
562 if (clock->m1 <= clock->m2)
563 INTELPllInvalid("m1 <= m2\n");
564
565 if (!IS_VALLEYVIEW(dev)) {
566 if (clock->p < limit->p.min || limit->p.max < clock->p)
567 INTELPllInvalid("p out of range\n");
568 if (clock->m < limit->m.min || limit->m.max < clock->m)
569 INTELPllInvalid("m out of range\n");
570 }
571
572 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
573 INTELPllInvalid("vco out of range\n");
574 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
575 * connector, etc., rather than just a single range.
576 */
577 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
578 INTELPllInvalid("dot out of range\n");
579
580 return true;
581 }
582
583 static bool
584 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
585 int target, int refclk, intel_clock_t *match_clock,
586 intel_clock_t *best_clock)
587 {
588 struct drm_device *dev = crtc->dev;
589 intel_clock_t clock;
590 int err = target;
591
592 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
593 /*
594 * For LVDS just rely on its current settings for dual-channel.
595 * We haven't figured out how to reliably set up different
596 * single/dual channel state, if we even can.
597 */
598 if (intel_is_dual_link_lvds(dev))
599 clock.p2 = limit->p2.p2_fast;
600 else
601 clock.p2 = limit->p2.p2_slow;
602 } else {
603 if (target < limit->p2.dot_limit)
604 clock.p2 = limit->p2.p2_slow;
605 else
606 clock.p2 = limit->p2.p2_fast;
607 }
608
609 memset(best_clock, 0, sizeof(*best_clock));
610
611 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
612 clock.m1++) {
613 for (clock.m2 = limit->m2.min;
614 clock.m2 <= limit->m2.max; clock.m2++) {
615 if (clock.m2 >= clock.m1)
616 break;
617 for (clock.n = limit->n.min;
618 clock.n <= limit->n.max; clock.n++) {
619 for (clock.p1 = limit->p1.min;
620 clock.p1 <= limit->p1.max; clock.p1++) {
621 int this_err;
622
623 i9xx_clock(refclk, &clock);
624 if (!intel_PLL_is_valid(dev, limit,
625 &clock))
626 continue;
627 if (match_clock &&
628 clock.p != match_clock->p)
629 continue;
630
631 this_err = abs(clock.dot - target);
632 if (this_err < err) {
633 *best_clock = clock;
634 err = this_err;
635 }
636 }
637 }
638 }
639 }
640
641 return (err != target);
642 }
643
644 static bool
645 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
646 int target, int refclk, intel_clock_t *match_clock,
647 intel_clock_t *best_clock)
648 {
649 struct drm_device *dev = crtc->dev;
650 intel_clock_t clock;
651 int err = target;
652
653 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
654 /*
655 * For LVDS just rely on its current settings for dual-channel.
656 * We haven't figured out how to reliably set up different
657 * single/dual channel state, if we even can.
658 */
659 if (intel_is_dual_link_lvds(dev))
660 clock.p2 = limit->p2.p2_fast;
661 else
662 clock.p2 = limit->p2.p2_slow;
663 } else {
664 if (target < limit->p2.dot_limit)
665 clock.p2 = limit->p2.p2_slow;
666 else
667 clock.p2 = limit->p2.p2_fast;
668 }
669
670 memset(best_clock, 0, sizeof(*best_clock));
671
672 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
673 clock.m1++) {
674 for (clock.m2 = limit->m2.min;
675 clock.m2 <= limit->m2.max; clock.m2++) {
676 for (clock.n = limit->n.min;
677 clock.n <= limit->n.max; clock.n++) {
678 for (clock.p1 = limit->p1.min;
679 clock.p1 <= limit->p1.max; clock.p1++) {
680 int this_err;
681
682 pineview_clock(refclk, &clock);
683 if (!intel_PLL_is_valid(dev, limit,
684 &clock))
685 continue;
686 if (match_clock &&
687 clock.p != match_clock->p)
688 continue;
689
690 this_err = abs(clock.dot - target);
691 if (this_err < err) {
692 *best_clock = clock;
693 err = this_err;
694 }
695 }
696 }
697 }
698 }
699
700 return (err != target);
701 }
702
703 static bool
704 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
705 int target, int refclk, intel_clock_t *match_clock,
706 intel_clock_t *best_clock)
707 {
708 struct drm_device *dev = crtc->dev;
709 intel_clock_t clock;
710 int max_n;
711 bool found;
712 /* approximately equals target * 0.00585 */
713 int err_most = (target >> 8) + (target >> 9);
714 found = false;
715
716 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
717 if (intel_is_dual_link_lvds(dev))
718 clock.p2 = limit->p2.p2_fast;
719 else
720 clock.p2 = limit->p2.p2_slow;
721 } else {
722 if (target < limit->p2.dot_limit)
723 clock.p2 = limit->p2.p2_slow;
724 else
725 clock.p2 = limit->p2.p2_fast;
726 }
727
728 memset(best_clock, 0, sizeof(*best_clock));
729 max_n = limit->n.max;
730 /* based on hardware requirement, prefer smaller n to precision */
731 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
732 /* based on hardware requirement, prefere larger m1,m2 */
733 for (clock.m1 = limit->m1.max;
734 clock.m1 >= limit->m1.min; clock.m1--) {
735 for (clock.m2 = limit->m2.max;
736 clock.m2 >= limit->m2.min; clock.m2--) {
737 for (clock.p1 = limit->p1.max;
738 clock.p1 >= limit->p1.min; clock.p1--) {
739 int this_err;
740
741 i9xx_clock(refclk, &clock);
742 if (!intel_PLL_is_valid(dev, limit,
743 &clock))
744 continue;
745
746 this_err = abs(clock.dot - target);
747 if (this_err < err_most) {
748 *best_clock = clock;
749 err_most = this_err;
750 max_n = clock.n;
751 found = true;
752 }
753 }
754 }
755 }
756 }
757 return found;
758 }
759
760 static bool
761 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
762 int target, int refclk, intel_clock_t *match_clock,
763 intel_clock_t *best_clock)
764 {
765 struct drm_device *dev = crtc->dev;
766 intel_clock_t clock;
767 unsigned int bestppm = 1000000;
768 /* min update 19.2 MHz */
769 int max_n = min(limit->n.max, refclk / 19200);
770 bool found = false;
771
772 target *= 5; /* fast clock */
773
774 memset(best_clock, 0, sizeof(*best_clock));
775
776 /* based on hardware requirement, prefer smaller n to precision */
777 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
778 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
779 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
780 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
781 clock.p = clock.p1 * clock.p2;
782 /* based on hardware requirement, prefer bigger m1,m2 values */
783 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
784 unsigned int ppm, diff;
785
786 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
787 refclk * clock.m1);
788
789 vlv_clock(refclk, &clock);
790
791 if (!intel_PLL_is_valid(dev, limit,
792 &clock))
793 continue;
794
795 diff = abs(clock.dot - target);
796 ppm = div_u64(1000000ULL * diff, target);
797
798 if (ppm < 100 && clock.p > best_clock->p) {
799 bestppm = 0;
800 *best_clock = clock;
801 found = true;
802 }
803
804 if (bestppm >= 10 && ppm < bestppm - 10) {
805 bestppm = ppm;
806 *best_clock = clock;
807 found = true;
808 }
809 }
810 }
811 }
812 }
813
814 return found;
815 }
816
817 static bool
818 chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
819 int target, int refclk, intel_clock_t *match_clock,
820 intel_clock_t *best_clock)
821 {
822 struct drm_device *dev = crtc->dev;
823 intel_clock_t clock;
824 uint64_t m2;
825 int found = false;
826
827 memset(best_clock, 0, sizeof(*best_clock));
828
829 /*
830 * Based on hardware doc, the n always set to 1, and m1 always
831 * set to 2. If requires to support 200Mhz refclk, we need to
832 * revisit this because n may not 1 anymore.
833 */
834 clock.n = 1, clock.m1 = 2;
835 target *= 5; /* fast clock */
836
837 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
838 for (clock.p2 = limit->p2.p2_fast;
839 clock.p2 >= limit->p2.p2_slow;
840 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
841
842 clock.p = clock.p1 * clock.p2;
843
844 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
845 clock.n) << 22, refclk * clock.m1);
846
847 if (m2 > INT_MAX/clock.m1)
848 continue;
849
850 clock.m2 = m2;
851
852 chv_clock(refclk, &clock);
853
854 if (!intel_PLL_is_valid(dev, limit, &clock))
855 continue;
856
857 /* based on hardware requirement, prefer bigger p
858 */
859 if (clock.p > best_clock->p) {
860 *best_clock = clock;
861 found = true;
862 }
863 }
864 }
865
866 return found;
867 }
868
869 bool intel_crtc_active(struct drm_crtc *crtc)
870 {
871 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
872
873 /* Be paranoid as we can arrive here with only partial
874 * state retrieved from the hardware during setup.
875 *
876 * We can ditch the adjusted_mode.crtc_clock check as soon
877 * as Haswell has gained clock readout/fastboot support.
878 *
879 * We can ditch the crtc->primary->fb check as soon as we can
880 * properly reconstruct framebuffers.
881 */
882 return intel_crtc->active && crtc->primary->fb &&
883 intel_crtc->config.adjusted_mode.crtc_clock;
884 }
885
886 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
887 enum pipe pipe)
888 {
889 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
890 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
891
892 return intel_crtc->config.cpu_transcoder;
893 }
894
895 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
896 {
897 struct drm_i915_private *dev_priv = dev->dev_private;
898 u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
899
900 frame = I915_READ(frame_reg);
901
902 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
903 WARN(1, "vblank wait timed out\n");
904 }
905
906 /**
907 * intel_wait_for_vblank - wait for vblank on a given pipe
908 * @dev: drm device
909 * @pipe: pipe to wait for
910 *
911 * Wait for vblank to occur on a given pipe. Needed for various bits of
912 * mode setting code.
913 */
914 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
915 {
916 struct drm_i915_private *dev_priv = dev->dev_private;
917 int pipestat_reg = PIPESTAT(pipe);
918
919 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
920 g4x_wait_for_vblank(dev, pipe);
921 return;
922 }
923
924 /* Clear existing vblank status. Note this will clear any other
925 * sticky status fields as well.
926 *
927 * This races with i915_driver_irq_handler() with the result
928 * that either function could miss a vblank event. Here it is not
929 * fatal, as we will either wait upon the next vblank interrupt or
930 * timeout. Generally speaking intel_wait_for_vblank() is only
931 * called during modeset at which time the GPU should be idle and
932 * should *not* be performing page flips and thus not waiting on
933 * vblanks...
934 * Currently, the result of us stealing a vblank from the irq
935 * handler is that a single frame will be skipped during swapbuffers.
936 */
937 I915_WRITE(pipestat_reg,
938 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
939
940 /* Wait for vblank interrupt bit to set */
941 if (wait_for(I915_READ(pipestat_reg) &
942 PIPE_VBLANK_INTERRUPT_STATUS,
943 50))
944 DRM_DEBUG_KMS("vblank wait timed out\n");
945 }
946
947 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
948 {
949 struct drm_i915_private *dev_priv = dev->dev_private;
950 u32 reg = PIPEDSL(pipe);
951 u32 line1, line2;
952 u32 line_mask;
953
954 if (IS_GEN2(dev))
955 line_mask = DSL_LINEMASK_GEN2;
956 else
957 line_mask = DSL_LINEMASK_GEN3;
958
959 line1 = I915_READ(reg) & line_mask;
960 mdelay(5);
961 line2 = I915_READ(reg) & line_mask;
962
963 return line1 == line2;
964 }
965
966 /*
967 * intel_wait_for_pipe_off - wait for pipe to turn off
968 * @dev: drm device
969 * @pipe: pipe to wait for
970 *
971 * After disabling a pipe, we can't wait for vblank in the usual way,
972 * spinning on the vblank interrupt status bit, since we won't actually
973 * see an interrupt when the pipe is disabled.
974 *
975 * On Gen4 and above:
976 * wait for the pipe register state bit to turn off
977 *
978 * Otherwise:
979 * wait for the display line value to settle (it usually
980 * ends up stopping at the start of the next frame).
981 *
982 */
983 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
984 {
985 struct drm_i915_private *dev_priv = dev->dev_private;
986 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
987 pipe);
988
989 if (INTEL_INFO(dev)->gen >= 4) {
990 int reg = PIPECONF(cpu_transcoder);
991
992 /* Wait for the Pipe State to go off */
993 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
994 100))
995 WARN(1, "pipe_off wait timed out\n");
996 } else {
997 /* Wait for the display line to settle */
998 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
999 WARN(1, "pipe_off wait timed out\n");
1000 }
1001 }
1002
1003 /*
1004 * ibx_digital_port_connected - is the specified port connected?
1005 * @dev_priv: i915 private structure
1006 * @port: the port to test
1007 *
1008 * Returns true if @port is connected, false otherwise.
1009 */
1010 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1011 struct intel_digital_port *port)
1012 {
1013 u32 bit;
1014
1015 if (HAS_PCH_IBX(dev_priv->dev)) {
1016 switch (port->port) {
1017 case PORT_B:
1018 bit = SDE_PORTB_HOTPLUG;
1019 break;
1020 case PORT_C:
1021 bit = SDE_PORTC_HOTPLUG;
1022 break;
1023 case PORT_D:
1024 bit = SDE_PORTD_HOTPLUG;
1025 break;
1026 default:
1027 return true;
1028 }
1029 } else {
1030 switch (port->port) {
1031 case PORT_B:
1032 bit = SDE_PORTB_HOTPLUG_CPT;
1033 break;
1034 case PORT_C:
1035 bit = SDE_PORTC_HOTPLUG_CPT;
1036 break;
1037 case PORT_D:
1038 bit = SDE_PORTD_HOTPLUG_CPT;
1039 break;
1040 default:
1041 return true;
1042 }
1043 }
1044
1045 return I915_READ(SDEISR) & bit;
1046 }
1047
1048 static const char *state_string(bool enabled)
1049 {
1050 return enabled ? "on" : "off";
1051 }
1052
1053 /* Only for pre-ILK configs */
1054 void assert_pll(struct drm_i915_private *dev_priv,
1055 enum pipe pipe, bool state)
1056 {
1057 int reg;
1058 u32 val;
1059 bool cur_state;
1060
1061 reg = DPLL(pipe);
1062 val = I915_READ(reg);
1063 cur_state = !!(val & DPLL_VCO_ENABLE);
1064 WARN(cur_state != state,
1065 "PLL state assertion failure (expected %s, current %s)\n",
1066 state_string(state), state_string(cur_state));
1067 }
1068
1069 /* XXX: the dsi pll is shared between MIPI DSI ports */
1070 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1071 {
1072 u32 val;
1073 bool cur_state;
1074
1075 mutex_lock(&dev_priv->dpio_lock);
1076 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1077 mutex_unlock(&dev_priv->dpio_lock);
1078
1079 cur_state = val & DSI_PLL_VCO_EN;
1080 WARN(cur_state != state,
1081 "DSI PLL state assertion failure (expected %s, current %s)\n",
1082 state_string(state), state_string(cur_state));
1083 }
1084 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1085 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1086
1087 struct intel_shared_dpll *
1088 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1089 {
1090 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1091
1092 if (crtc->config.shared_dpll < 0)
1093 return NULL;
1094
1095 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1096 }
1097
1098 /* For ILK+ */
1099 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1100 struct intel_shared_dpll *pll,
1101 bool state)
1102 {
1103 bool cur_state;
1104 struct intel_dpll_hw_state hw_state;
1105
1106 if (WARN (!pll,
1107 "asserting DPLL %s with no DPLL\n", state_string(state)))
1108 return;
1109
1110 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1111 WARN(cur_state != state,
1112 "%s assertion failure (expected %s, current %s)\n",
1113 pll->name, state_string(state), state_string(cur_state));
1114 }
1115
1116 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1117 enum pipe pipe, bool state)
1118 {
1119 int reg;
1120 u32 val;
1121 bool cur_state;
1122 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1123 pipe);
1124
1125 if (HAS_DDI(dev_priv->dev)) {
1126 /* DDI does not have a specific FDI_TX register */
1127 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1128 val = I915_READ(reg);
1129 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1130 } else {
1131 reg = FDI_TX_CTL(pipe);
1132 val = I915_READ(reg);
1133 cur_state = !!(val & FDI_TX_ENABLE);
1134 }
1135 WARN(cur_state != state,
1136 "FDI TX state assertion failure (expected %s, current %s)\n",
1137 state_string(state), state_string(cur_state));
1138 }
1139 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1140 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1141
1142 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1143 enum pipe pipe, bool state)
1144 {
1145 int reg;
1146 u32 val;
1147 bool cur_state;
1148
1149 reg = FDI_RX_CTL(pipe);
1150 val = I915_READ(reg);
1151 cur_state = !!(val & FDI_RX_ENABLE);
1152 WARN(cur_state != state,
1153 "FDI RX state assertion failure (expected %s, current %s)\n",
1154 state_string(state), state_string(cur_state));
1155 }
1156 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1157 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1158
1159 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1160 enum pipe pipe)
1161 {
1162 int reg;
1163 u32 val;
1164
1165 /* ILK FDI PLL is always enabled */
1166 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1167 return;
1168
1169 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1170 if (HAS_DDI(dev_priv->dev))
1171 return;
1172
1173 reg = FDI_TX_CTL(pipe);
1174 val = I915_READ(reg);
1175 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1176 }
1177
1178 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1179 enum pipe pipe, bool state)
1180 {
1181 int reg;
1182 u32 val;
1183 bool cur_state;
1184
1185 reg = FDI_RX_CTL(pipe);
1186 val = I915_READ(reg);
1187 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1188 WARN(cur_state != state,
1189 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1190 state_string(state), state_string(cur_state));
1191 }
1192
1193 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1194 enum pipe pipe)
1195 {
1196 int pp_reg, lvds_reg;
1197 u32 val;
1198 enum pipe panel_pipe = PIPE_A;
1199 bool locked = true;
1200
1201 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1202 pp_reg = PCH_PP_CONTROL;
1203 lvds_reg = PCH_LVDS;
1204 } else {
1205 pp_reg = PP_CONTROL;
1206 lvds_reg = LVDS;
1207 }
1208
1209 val = I915_READ(pp_reg);
1210 if (!(val & PANEL_POWER_ON) ||
1211 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1212 locked = false;
1213
1214 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1215 panel_pipe = PIPE_B;
1216
1217 WARN(panel_pipe == pipe && locked,
1218 "panel assertion failure, pipe %c regs locked\n",
1219 pipe_name(pipe));
1220 }
1221
1222 static void assert_cursor(struct drm_i915_private *dev_priv,
1223 enum pipe pipe, bool state)
1224 {
1225 struct drm_device *dev = dev_priv->dev;
1226 bool cur_state;
1227
1228 if (IS_845G(dev) || IS_I865G(dev))
1229 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1230 else
1231 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1232
1233 WARN(cur_state != state,
1234 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1235 pipe_name(pipe), state_string(state), state_string(cur_state));
1236 }
1237 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1238 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1239
1240 void assert_pipe(struct drm_i915_private *dev_priv,
1241 enum pipe pipe, bool state)
1242 {
1243 int reg;
1244 u32 val;
1245 bool cur_state;
1246 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1247 pipe);
1248
1249 /* if we need the pipe A quirk it must be always on */
1250 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1251 state = true;
1252
1253 if (!intel_display_power_enabled(dev_priv,
1254 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1255 cur_state = false;
1256 } else {
1257 reg = PIPECONF(cpu_transcoder);
1258 val = I915_READ(reg);
1259 cur_state = !!(val & PIPECONF_ENABLE);
1260 }
1261
1262 WARN(cur_state != state,
1263 "pipe %c assertion failure (expected %s, current %s)\n",
1264 pipe_name(pipe), state_string(state), state_string(cur_state));
1265 }
1266
1267 static void assert_plane(struct drm_i915_private *dev_priv,
1268 enum plane plane, bool state)
1269 {
1270 int reg;
1271 u32 val;
1272 bool cur_state;
1273
1274 reg = DSPCNTR(plane);
1275 val = I915_READ(reg);
1276 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1277 WARN(cur_state != state,
1278 "plane %c assertion failure (expected %s, current %s)\n",
1279 plane_name(plane), state_string(state), state_string(cur_state));
1280 }
1281
1282 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1283 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1284
1285 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1286 enum pipe pipe)
1287 {
1288 struct drm_device *dev = dev_priv->dev;
1289 int reg, i;
1290 u32 val;
1291 int cur_pipe;
1292
1293 /* Primary planes are fixed to pipes on gen4+ */
1294 if (INTEL_INFO(dev)->gen >= 4) {
1295 reg = DSPCNTR(pipe);
1296 val = I915_READ(reg);
1297 WARN(val & DISPLAY_PLANE_ENABLE,
1298 "plane %c assertion failure, should be disabled but not\n",
1299 plane_name(pipe));
1300 return;
1301 }
1302
1303 /* Need to check both planes against the pipe */
1304 for_each_pipe(i) {
1305 reg = DSPCNTR(i);
1306 val = I915_READ(reg);
1307 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1308 DISPPLANE_SEL_PIPE_SHIFT;
1309 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1310 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1311 plane_name(i), pipe_name(pipe));
1312 }
1313 }
1314
1315 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1316 enum pipe pipe)
1317 {
1318 struct drm_device *dev = dev_priv->dev;
1319 int reg, sprite;
1320 u32 val;
1321
1322 if (IS_VALLEYVIEW(dev)) {
1323 for_each_sprite(pipe, sprite) {
1324 reg = SPCNTR(pipe, sprite);
1325 val = I915_READ(reg);
1326 WARN(val & SP_ENABLE,
1327 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1328 sprite_name(pipe, sprite), pipe_name(pipe));
1329 }
1330 } else if (INTEL_INFO(dev)->gen >= 7) {
1331 reg = SPRCTL(pipe);
1332 val = I915_READ(reg);
1333 WARN(val & SPRITE_ENABLE,
1334 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1335 plane_name(pipe), pipe_name(pipe));
1336 } else if (INTEL_INFO(dev)->gen >= 5) {
1337 reg = DVSCNTR(pipe);
1338 val = I915_READ(reg);
1339 WARN(val & DVS_ENABLE,
1340 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1341 plane_name(pipe), pipe_name(pipe));
1342 }
1343 }
1344
1345 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1346 {
1347 u32 val;
1348 bool enabled;
1349
1350 WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1351
1352 val = I915_READ(PCH_DREF_CONTROL);
1353 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1354 DREF_SUPERSPREAD_SOURCE_MASK));
1355 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1356 }
1357
1358 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1359 enum pipe pipe)
1360 {
1361 int reg;
1362 u32 val;
1363 bool enabled;
1364
1365 reg = PCH_TRANSCONF(pipe);
1366 val = I915_READ(reg);
1367 enabled = !!(val & TRANS_ENABLE);
1368 WARN(enabled,
1369 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1370 pipe_name(pipe));
1371 }
1372
1373 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1374 enum pipe pipe, u32 port_sel, u32 val)
1375 {
1376 if ((val & DP_PORT_EN) == 0)
1377 return false;
1378
1379 if (HAS_PCH_CPT(dev_priv->dev)) {
1380 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1381 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1382 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1383 return false;
1384 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1385 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1386 return false;
1387 } else {
1388 if ((val & DP_PIPE_MASK) != (pipe << 30))
1389 return false;
1390 }
1391 return true;
1392 }
1393
1394 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1395 enum pipe pipe, u32 val)
1396 {
1397 if ((val & SDVO_ENABLE) == 0)
1398 return false;
1399
1400 if (HAS_PCH_CPT(dev_priv->dev)) {
1401 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1402 return false;
1403 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1404 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1405 return false;
1406 } else {
1407 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1408 return false;
1409 }
1410 return true;
1411 }
1412
1413 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1414 enum pipe pipe, u32 val)
1415 {
1416 if ((val & LVDS_PORT_EN) == 0)
1417 return false;
1418
1419 if (HAS_PCH_CPT(dev_priv->dev)) {
1420 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1421 return false;
1422 } else {
1423 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1424 return false;
1425 }
1426 return true;
1427 }
1428
1429 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1430 enum pipe pipe, u32 val)
1431 {
1432 if ((val & ADPA_DAC_ENABLE) == 0)
1433 return false;
1434 if (HAS_PCH_CPT(dev_priv->dev)) {
1435 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1436 return false;
1437 } else {
1438 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1439 return false;
1440 }
1441 return true;
1442 }
1443
1444 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1445 enum pipe pipe, int reg, u32 port_sel)
1446 {
1447 u32 val = I915_READ(reg);
1448 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1449 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1450 reg, pipe_name(pipe));
1451
1452 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1453 && (val & DP_PIPEB_SELECT),
1454 "IBX PCH dp port still using transcoder B\n");
1455 }
1456
1457 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1458 enum pipe pipe, int reg)
1459 {
1460 u32 val = I915_READ(reg);
1461 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1462 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1463 reg, pipe_name(pipe));
1464
1465 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1466 && (val & SDVO_PIPE_B_SELECT),
1467 "IBX PCH hdmi port still using transcoder B\n");
1468 }
1469
1470 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1471 enum pipe pipe)
1472 {
1473 int reg;
1474 u32 val;
1475
1476 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1477 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1478 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1479
1480 reg = PCH_ADPA;
1481 val = I915_READ(reg);
1482 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1483 "PCH VGA enabled on transcoder %c, should be disabled\n",
1484 pipe_name(pipe));
1485
1486 reg = PCH_LVDS;
1487 val = I915_READ(reg);
1488 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1489 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1490 pipe_name(pipe));
1491
1492 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1493 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1494 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1495 }
1496
1497 static void intel_init_dpio(struct drm_device *dev)
1498 {
1499 struct drm_i915_private *dev_priv = dev->dev_private;
1500
1501 if (!IS_VALLEYVIEW(dev))
1502 return;
1503
1504 /*
1505 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1506 * CHV x1 PHY (DP/HDMI D)
1507 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1508 */
1509 if (IS_CHERRYVIEW(dev)) {
1510 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1511 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1512 } else {
1513 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1514 }
1515 }
1516
1517 static void vlv_enable_pll(struct intel_crtc *crtc)
1518 {
1519 struct drm_device *dev = crtc->base.dev;
1520 struct drm_i915_private *dev_priv = dev->dev_private;
1521 int reg = DPLL(crtc->pipe);
1522 u32 dpll = crtc->config.dpll_hw_state.dpll;
1523
1524 assert_pipe_disabled(dev_priv, crtc->pipe);
1525
1526 /* No really, not for ILK+ */
1527 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1528
1529 /* PLL is protected by panel, make sure we can write it */
1530 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1531 assert_panel_unlocked(dev_priv, crtc->pipe);
1532
1533 I915_WRITE(reg, dpll);
1534 POSTING_READ(reg);
1535 udelay(150);
1536
1537 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1538 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1539
1540 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1541 POSTING_READ(DPLL_MD(crtc->pipe));
1542
1543 /* We do this three times for luck */
1544 I915_WRITE(reg, dpll);
1545 POSTING_READ(reg);
1546 udelay(150); /* wait for warmup */
1547 I915_WRITE(reg, dpll);
1548 POSTING_READ(reg);
1549 udelay(150); /* wait for warmup */
1550 I915_WRITE(reg, dpll);
1551 POSTING_READ(reg);
1552 udelay(150); /* wait for warmup */
1553 }
1554
1555 static void chv_enable_pll(struct intel_crtc *crtc)
1556 {
1557 struct drm_device *dev = crtc->base.dev;
1558 struct drm_i915_private *dev_priv = dev->dev_private;
1559 int pipe = crtc->pipe;
1560 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1561 u32 tmp;
1562
1563 assert_pipe_disabled(dev_priv, crtc->pipe);
1564
1565 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1566
1567 mutex_lock(&dev_priv->dpio_lock);
1568
1569 /* Enable back the 10bit clock to display controller */
1570 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1571 tmp |= DPIO_DCLKP_EN;
1572 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1573
1574 /*
1575 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1576 */
1577 udelay(1);
1578
1579 /* Enable PLL */
1580 I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll);
1581
1582 /* Check PLL is locked */
1583 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1584 DRM_ERROR("PLL %d failed to lock\n", pipe);
1585
1586 /* not sure when this should be written */
1587 I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
1588 POSTING_READ(DPLL_MD(pipe));
1589
1590 mutex_unlock(&dev_priv->dpio_lock);
1591 }
1592
1593 static void i9xx_enable_pll(struct intel_crtc *crtc)
1594 {
1595 struct drm_device *dev = crtc->base.dev;
1596 struct drm_i915_private *dev_priv = dev->dev_private;
1597 int reg = DPLL(crtc->pipe);
1598 u32 dpll = crtc->config.dpll_hw_state.dpll;
1599
1600 assert_pipe_disabled(dev_priv, crtc->pipe);
1601
1602 /* No really, not for ILK+ */
1603 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1604
1605 /* PLL is protected by panel, make sure we can write it */
1606 if (IS_MOBILE(dev) && !IS_I830(dev))
1607 assert_panel_unlocked(dev_priv, crtc->pipe);
1608
1609 I915_WRITE(reg, dpll);
1610
1611 /* Wait for the clocks to stabilize. */
1612 POSTING_READ(reg);
1613 udelay(150);
1614
1615 if (INTEL_INFO(dev)->gen >= 4) {
1616 I915_WRITE(DPLL_MD(crtc->pipe),
1617 crtc->config.dpll_hw_state.dpll_md);
1618 } else {
1619 /* The pixel multiplier can only be updated once the
1620 * DPLL is enabled and the clocks are stable.
1621 *
1622 * So write it again.
1623 */
1624 I915_WRITE(reg, dpll);
1625 }
1626
1627 /* We do this three times for luck */
1628 I915_WRITE(reg, dpll);
1629 POSTING_READ(reg);
1630 udelay(150); /* wait for warmup */
1631 I915_WRITE(reg, dpll);
1632 POSTING_READ(reg);
1633 udelay(150); /* wait for warmup */
1634 I915_WRITE(reg, dpll);
1635 POSTING_READ(reg);
1636 udelay(150); /* wait for warmup */
1637 }
1638
1639 /**
1640 * i9xx_disable_pll - disable a PLL
1641 * @dev_priv: i915 private structure
1642 * @pipe: pipe PLL to disable
1643 *
1644 * Disable the PLL for @pipe, making sure the pipe is off first.
1645 *
1646 * Note! This is for pre-ILK only.
1647 */
1648 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1649 {
1650 /* Don't disable pipe A or pipe A PLLs if needed */
1651 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1652 return;
1653
1654 /* Make sure the pipe isn't still relying on us */
1655 assert_pipe_disabled(dev_priv, pipe);
1656
1657 I915_WRITE(DPLL(pipe), 0);
1658 POSTING_READ(DPLL(pipe));
1659 }
1660
1661 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1662 {
1663 u32 val = 0;
1664
1665 /* Make sure the pipe isn't still relying on us */
1666 assert_pipe_disabled(dev_priv, pipe);
1667
1668 /*
1669 * Leave integrated clock source and reference clock enabled for pipe B.
1670 * The latter is needed for VGA hotplug / manual detection.
1671 */
1672 if (pipe == PIPE_B)
1673 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1674 I915_WRITE(DPLL(pipe), val);
1675 POSTING_READ(DPLL(pipe));
1676
1677 }
1678
1679 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1680 {
1681 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1682 u32 val;
1683
1684 /* Make sure the pipe isn't still relying on us */
1685 assert_pipe_disabled(dev_priv, pipe);
1686
1687 /* Set PLL en = 0 */
1688 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1689 if (pipe != PIPE_A)
1690 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1691 I915_WRITE(DPLL(pipe), val);
1692 POSTING_READ(DPLL(pipe));
1693
1694 mutex_lock(&dev_priv->dpio_lock);
1695
1696 /* Disable 10bit clock to display controller */
1697 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1698 val &= ~DPIO_DCLKP_EN;
1699 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1700
1701 /* disable left/right clock distribution */
1702 if (pipe != PIPE_B) {
1703 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1704 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1705 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1706 } else {
1707 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1708 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1709 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1710 }
1711
1712 mutex_unlock(&dev_priv->dpio_lock);
1713 }
1714
1715 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1716 struct intel_digital_port *dport)
1717 {
1718 u32 port_mask;
1719 int dpll_reg;
1720
1721 switch (dport->port) {
1722 case PORT_B:
1723 port_mask = DPLL_PORTB_READY_MASK;
1724 dpll_reg = DPLL(0);
1725 break;
1726 case PORT_C:
1727 port_mask = DPLL_PORTC_READY_MASK;
1728 dpll_reg = DPLL(0);
1729 break;
1730 case PORT_D:
1731 port_mask = DPLL_PORTD_READY_MASK;
1732 dpll_reg = DPIO_PHY_STATUS;
1733 break;
1734 default:
1735 BUG();
1736 }
1737
1738 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1739 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1740 port_name(dport->port), I915_READ(dpll_reg));
1741 }
1742
1743 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1744 {
1745 struct drm_device *dev = crtc->base.dev;
1746 struct drm_i915_private *dev_priv = dev->dev_private;
1747 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1748
1749 if (WARN_ON(pll == NULL))
1750 return;
1751
1752 WARN_ON(!pll->refcount);
1753 if (pll->active == 0) {
1754 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1755 WARN_ON(pll->on);
1756 assert_shared_dpll_disabled(dev_priv, pll);
1757
1758 pll->mode_set(dev_priv, pll);
1759 }
1760 }
1761
1762 /**
1763 * intel_enable_shared_dpll - enable PCH PLL
1764 * @dev_priv: i915 private structure
1765 * @pipe: pipe PLL to enable
1766 *
1767 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1768 * drives the transcoder clock.
1769 */
1770 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1771 {
1772 struct drm_device *dev = crtc->base.dev;
1773 struct drm_i915_private *dev_priv = dev->dev_private;
1774 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1775
1776 if (WARN_ON(pll == NULL))
1777 return;
1778
1779 if (WARN_ON(pll->refcount == 0))
1780 return;
1781
1782 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1783 pll->name, pll->active, pll->on,
1784 crtc->base.base.id);
1785
1786 if (pll->active++) {
1787 WARN_ON(!pll->on);
1788 assert_shared_dpll_enabled(dev_priv, pll);
1789 return;
1790 }
1791 WARN_ON(pll->on);
1792
1793 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1794
1795 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1796 pll->enable(dev_priv, pll);
1797 pll->on = true;
1798 }
1799
1800 void intel_disable_shared_dpll(struct intel_crtc *crtc)
1801 {
1802 struct drm_device *dev = crtc->base.dev;
1803 struct drm_i915_private *dev_priv = dev->dev_private;
1804 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1805
1806 /* PCH only available on ILK+ */
1807 BUG_ON(INTEL_INFO(dev)->gen < 5);
1808 if (WARN_ON(pll == NULL))
1809 return;
1810
1811 if (WARN_ON(pll->refcount == 0))
1812 return;
1813
1814 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1815 pll->name, pll->active, pll->on,
1816 crtc->base.base.id);
1817
1818 if (WARN_ON(pll->active == 0)) {
1819 assert_shared_dpll_disabled(dev_priv, pll);
1820 return;
1821 }
1822
1823 assert_shared_dpll_enabled(dev_priv, pll);
1824 WARN_ON(!pll->on);
1825 if (--pll->active)
1826 return;
1827
1828 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1829 pll->disable(dev_priv, pll);
1830 pll->on = false;
1831
1832 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1833 }
1834
1835 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1836 enum pipe pipe)
1837 {
1838 struct drm_device *dev = dev_priv->dev;
1839 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1840 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1841 uint32_t reg, val, pipeconf_val;
1842
1843 /* PCH only available on ILK+ */
1844 BUG_ON(INTEL_INFO(dev)->gen < 5);
1845
1846 /* Make sure PCH DPLL is enabled */
1847 assert_shared_dpll_enabled(dev_priv,
1848 intel_crtc_to_shared_dpll(intel_crtc));
1849
1850 /* FDI must be feeding us bits for PCH ports */
1851 assert_fdi_tx_enabled(dev_priv, pipe);
1852 assert_fdi_rx_enabled(dev_priv, pipe);
1853
1854 if (HAS_PCH_CPT(dev)) {
1855 /* Workaround: Set the timing override bit before enabling the
1856 * pch transcoder. */
1857 reg = TRANS_CHICKEN2(pipe);
1858 val = I915_READ(reg);
1859 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1860 I915_WRITE(reg, val);
1861 }
1862
1863 reg = PCH_TRANSCONF(pipe);
1864 val = I915_READ(reg);
1865 pipeconf_val = I915_READ(PIPECONF(pipe));
1866
1867 if (HAS_PCH_IBX(dev_priv->dev)) {
1868 /*
1869 * make the BPC in transcoder be consistent with
1870 * that in pipeconf reg.
1871 */
1872 val &= ~PIPECONF_BPC_MASK;
1873 val |= pipeconf_val & PIPECONF_BPC_MASK;
1874 }
1875
1876 val &= ~TRANS_INTERLACE_MASK;
1877 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1878 if (HAS_PCH_IBX(dev_priv->dev) &&
1879 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1880 val |= TRANS_LEGACY_INTERLACED_ILK;
1881 else
1882 val |= TRANS_INTERLACED;
1883 else
1884 val |= TRANS_PROGRESSIVE;
1885
1886 I915_WRITE(reg, val | TRANS_ENABLE);
1887 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1888 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1889 }
1890
1891 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1892 enum transcoder cpu_transcoder)
1893 {
1894 u32 val, pipeconf_val;
1895
1896 /* PCH only available on ILK+ */
1897 BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
1898
1899 /* FDI must be feeding us bits for PCH ports */
1900 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1901 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1902
1903 /* Workaround: set timing override bit. */
1904 val = I915_READ(_TRANSA_CHICKEN2);
1905 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1906 I915_WRITE(_TRANSA_CHICKEN2, val);
1907
1908 val = TRANS_ENABLE;
1909 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1910
1911 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1912 PIPECONF_INTERLACED_ILK)
1913 val |= TRANS_INTERLACED;
1914 else
1915 val |= TRANS_PROGRESSIVE;
1916
1917 I915_WRITE(LPT_TRANSCONF, val);
1918 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1919 DRM_ERROR("Failed to enable PCH transcoder\n");
1920 }
1921
1922 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1923 enum pipe pipe)
1924 {
1925 struct drm_device *dev = dev_priv->dev;
1926 uint32_t reg, val;
1927
1928 /* FDI relies on the transcoder */
1929 assert_fdi_tx_disabled(dev_priv, pipe);
1930 assert_fdi_rx_disabled(dev_priv, pipe);
1931
1932 /* Ports must be off as well */
1933 assert_pch_ports_disabled(dev_priv, pipe);
1934
1935 reg = PCH_TRANSCONF(pipe);
1936 val = I915_READ(reg);
1937 val &= ~TRANS_ENABLE;
1938 I915_WRITE(reg, val);
1939 /* wait for PCH transcoder off, transcoder state */
1940 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1941 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1942
1943 if (!HAS_PCH_IBX(dev)) {
1944 /* Workaround: Clear the timing override chicken bit again. */
1945 reg = TRANS_CHICKEN2(pipe);
1946 val = I915_READ(reg);
1947 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1948 I915_WRITE(reg, val);
1949 }
1950 }
1951
1952 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1953 {
1954 u32 val;
1955
1956 val = I915_READ(LPT_TRANSCONF);
1957 val &= ~TRANS_ENABLE;
1958 I915_WRITE(LPT_TRANSCONF, val);
1959 /* wait for PCH transcoder off, transcoder state */
1960 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1961 DRM_ERROR("Failed to disable PCH transcoder\n");
1962
1963 /* Workaround: clear timing override bit. */
1964 val = I915_READ(_TRANSA_CHICKEN2);
1965 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1966 I915_WRITE(_TRANSA_CHICKEN2, val);
1967 }
1968
1969 /**
1970 * intel_enable_pipe - enable a pipe, asserting requirements
1971 * @crtc: crtc responsible for the pipe
1972 *
1973 * Enable @crtc's pipe, making sure that various hardware specific requirements
1974 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1975 */
1976 static void intel_enable_pipe(struct intel_crtc *crtc)
1977 {
1978 struct drm_device *dev = crtc->base.dev;
1979 struct drm_i915_private *dev_priv = dev->dev_private;
1980 enum pipe pipe = crtc->pipe;
1981 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1982 pipe);
1983 enum pipe pch_transcoder;
1984 int reg;
1985 u32 val;
1986
1987 assert_planes_disabled(dev_priv, pipe);
1988 assert_cursor_disabled(dev_priv, pipe);
1989 assert_sprites_disabled(dev_priv, pipe);
1990
1991 if (HAS_PCH_LPT(dev_priv->dev))
1992 pch_transcoder = TRANSCODER_A;
1993 else
1994 pch_transcoder = pipe;
1995
1996 /*
1997 * A pipe without a PLL won't actually be able to drive bits from
1998 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1999 * need the check.
2000 */
2001 if (!HAS_PCH_SPLIT(dev_priv->dev))
2002 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
2003 assert_dsi_pll_enabled(dev_priv);
2004 else
2005 assert_pll_enabled(dev_priv, pipe);
2006 else {
2007 if (crtc->config.has_pch_encoder) {
2008 /* if driving the PCH, we need FDI enabled */
2009 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2010 assert_fdi_tx_pll_enabled(dev_priv,
2011 (enum pipe) cpu_transcoder);
2012 }
2013 /* FIXME: assert CPU port conditions for SNB+ */
2014 }
2015
2016 reg = PIPECONF(cpu_transcoder);
2017 val = I915_READ(reg);
2018 if (val & PIPECONF_ENABLE) {
2019 WARN_ON(!(pipe == PIPE_A &&
2020 dev_priv->quirks & QUIRK_PIPEA_FORCE));
2021 return;
2022 }
2023
2024 I915_WRITE(reg, val | PIPECONF_ENABLE);
2025 POSTING_READ(reg);
2026 }
2027
2028 /**
2029 * intel_disable_pipe - disable a pipe, asserting requirements
2030 * @dev_priv: i915 private structure
2031 * @pipe: pipe to disable
2032 *
2033 * Disable @pipe, making sure that various hardware specific requirements
2034 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
2035 *
2036 * @pipe should be %PIPE_A or %PIPE_B.
2037 *
2038 * Will wait until the pipe has shut down before returning.
2039 */
2040 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
2041 enum pipe pipe)
2042 {
2043 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2044 pipe);
2045 int reg;
2046 u32 val;
2047
2048 /*
2049 * Make sure planes won't keep trying to pump pixels to us,
2050 * or we might hang the display.
2051 */
2052 assert_planes_disabled(dev_priv, pipe);
2053 assert_cursor_disabled(dev_priv, pipe);
2054 assert_sprites_disabled(dev_priv, pipe);
2055
2056 /* Don't disable pipe A or pipe A PLLs if needed */
2057 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2058 return;
2059
2060 reg = PIPECONF(cpu_transcoder);
2061 val = I915_READ(reg);
2062 if ((val & PIPECONF_ENABLE) == 0)
2063 return;
2064
2065 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
2066 intel_wait_for_pipe_off(dev_priv->dev, pipe);
2067 }
2068
2069 /*
2070 * Plane regs are double buffered, going from enabled->disabled needs a
2071 * trigger in order to latch. The display address reg provides this.
2072 */
2073 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2074 enum plane plane)
2075 {
2076 struct drm_device *dev = dev_priv->dev;
2077 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2078
2079 I915_WRITE(reg, I915_READ(reg));
2080 POSTING_READ(reg);
2081 }
2082
2083 /**
2084 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2085 * @plane: plane to be enabled
2086 * @crtc: crtc for the plane
2087 *
2088 * Enable @plane on @crtc, making sure that the pipe is running first.
2089 */
2090 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2091 struct drm_crtc *crtc)
2092 {
2093 struct drm_device *dev = plane->dev;
2094 struct drm_i915_private *dev_priv = dev->dev_private;
2095 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2096
2097 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2098 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2099
2100 if (intel_crtc->primary_enabled)
2101 return;
2102
2103 intel_crtc->primary_enabled = true;
2104
2105 dev_priv->display.update_primary_plane(crtc, plane->fb,
2106 crtc->x, crtc->y);
2107
2108 /*
2109 * BDW signals flip done immediately if the plane
2110 * is disabled, even if the plane enable is already
2111 * armed to occur at the next vblank :(
2112 */
2113 if (IS_BROADWELL(dev))
2114 intel_wait_for_vblank(dev, intel_crtc->pipe);
2115 }
2116
2117 /**
2118 * intel_disable_primary_hw_plane - disable the primary hardware plane
2119 * @plane: plane to be disabled
2120 * @crtc: crtc for the plane
2121 *
2122 * Disable @plane on @crtc, making sure that the pipe is running first.
2123 */
2124 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2125 struct drm_crtc *crtc)
2126 {
2127 struct drm_device *dev = plane->dev;
2128 struct drm_i915_private *dev_priv = dev->dev_private;
2129 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2130
2131 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2132
2133 if (!intel_crtc->primary_enabled)
2134 return;
2135
2136 intel_crtc->primary_enabled = false;
2137
2138 dev_priv->display.update_primary_plane(crtc, plane->fb,
2139 crtc->x, crtc->y);
2140 }
2141
2142 static bool need_vtd_wa(struct drm_device *dev)
2143 {
2144 #ifdef CONFIG_INTEL_IOMMU
2145 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2146 return true;
2147 #endif
2148 return false;
2149 }
2150
2151 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2152 {
2153 int tile_height;
2154
2155 tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2156 return ALIGN(height, tile_height);
2157 }
2158
2159 int
2160 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2161 struct drm_i915_gem_object *obj,
2162 struct intel_engine_cs *pipelined)
2163 {
2164 struct drm_i915_private *dev_priv = dev->dev_private;
2165 u32 alignment;
2166 int ret;
2167
2168 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2169
2170 switch (obj->tiling_mode) {
2171 case I915_TILING_NONE:
2172 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2173 alignment = 128 * 1024;
2174 else if (INTEL_INFO(dev)->gen >= 4)
2175 alignment = 4 * 1024;
2176 else
2177 alignment = 64 * 1024;
2178 break;
2179 case I915_TILING_X:
2180 /* pin() will align the object as required by fence */
2181 alignment = 0;
2182 break;
2183 case I915_TILING_Y:
2184 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2185 return -EINVAL;
2186 default:
2187 BUG();
2188 }
2189
2190 /* Note that the w/a also requires 64 PTE of padding following the
2191 * bo. We currently fill all unused PTE with the shadow page and so
2192 * we should always have valid PTE following the scanout preventing
2193 * the VT-d warning.
2194 */
2195 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2196 alignment = 256 * 1024;
2197
2198 dev_priv->mm.interruptible = false;
2199 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2200 if (ret)
2201 goto err_interruptible;
2202
2203 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2204 * fence, whereas 965+ only requires a fence if using
2205 * framebuffer compression. For simplicity, we always install
2206 * a fence as the cost is not that onerous.
2207 */
2208 ret = i915_gem_object_get_fence(obj);
2209 if (ret)
2210 goto err_unpin;
2211
2212 i915_gem_object_pin_fence(obj);
2213
2214 dev_priv->mm.interruptible = true;
2215 return 0;
2216
2217 err_unpin:
2218 i915_gem_object_unpin_from_display_plane(obj);
2219 err_interruptible:
2220 dev_priv->mm.interruptible = true;
2221 return ret;
2222 }
2223
2224 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2225 {
2226 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2227
2228 i915_gem_object_unpin_fence(obj);
2229 i915_gem_object_unpin_from_display_plane(obj);
2230 }
2231
2232 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2233 * is assumed to be a power-of-two. */
2234 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2235 unsigned int tiling_mode,
2236 unsigned int cpp,
2237 unsigned int pitch)
2238 {
2239 if (tiling_mode != I915_TILING_NONE) {
2240 unsigned int tile_rows, tiles;
2241
2242 tile_rows = *y / 8;
2243 *y %= 8;
2244
2245 tiles = *x / (512/cpp);
2246 *x %= 512/cpp;
2247
2248 return tile_rows * pitch * 8 + tiles * 4096;
2249 } else {
2250 unsigned int offset;
2251
2252 offset = *y * pitch + *x * cpp;
2253 *y = 0;
2254 *x = (offset & 4095) / cpp;
2255 return offset & -4096;
2256 }
2257 }
2258
2259 int intel_format_to_fourcc(int format)
2260 {
2261 switch (format) {
2262 case DISPPLANE_8BPP:
2263 return DRM_FORMAT_C8;
2264 case DISPPLANE_BGRX555:
2265 return DRM_FORMAT_XRGB1555;
2266 case DISPPLANE_BGRX565:
2267 return DRM_FORMAT_RGB565;
2268 default:
2269 case DISPPLANE_BGRX888:
2270 return DRM_FORMAT_XRGB8888;
2271 case DISPPLANE_RGBX888:
2272 return DRM_FORMAT_XBGR8888;
2273 case DISPPLANE_BGRX101010:
2274 return DRM_FORMAT_XRGB2101010;
2275 case DISPPLANE_RGBX101010:
2276 return DRM_FORMAT_XBGR2101010;
2277 }
2278 }
2279
2280 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2281 struct intel_plane_config *plane_config)
2282 {
2283 struct drm_device *dev = crtc->base.dev;
2284 struct drm_i915_gem_object *obj = NULL;
2285 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2286 u32 base = plane_config->base;
2287
2288 if (plane_config->size == 0)
2289 return false;
2290
2291 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2292 plane_config->size);
2293 if (!obj)
2294 return false;
2295
2296 if (plane_config->tiled) {
2297 obj->tiling_mode = I915_TILING_X;
2298 obj->stride = crtc->base.primary->fb->pitches[0];
2299 }
2300
2301 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2302 mode_cmd.width = crtc->base.primary->fb->width;
2303 mode_cmd.height = crtc->base.primary->fb->height;
2304 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2305
2306 mutex_lock(&dev->struct_mutex);
2307
2308 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2309 &mode_cmd, obj)) {
2310 DRM_DEBUG_KMS("intel fb init failed\n");
2311 goto out_unref_obj;
2312 }
2313
2314 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2315 mutex_unlock(&dev->struct_mutex);
2316
2317 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2318 return true;
2319
2320 out_unref_obj:
2321 drm_gem_object_unreference(&obj->base);
2322 mutex_unlock(&dev->struct_mutex);
2323 return false;
2324 }
2325
2326 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2327 struct intel_plane_config *plane_config)
2328 {
2329 struct drm_device *dev = intel_crtc->base.dev;
2330 struct drm_crtc *c;
2331 struct intel_crtc *i;
2332 struct drm_i915_gem_object *obj;
2333
2334 if (!intel_crtc->base.primary->fb)
2335 return;
2336
2337 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2338 return;
2339
2340 kfree(intel_crtc->base.primary->fb);
2341 intel_crtc->base.primary->fb = NULL;
2342
2343 /*
2344 * Failed to alloc the obj, check to see if we should share
2345 * an fb with another CRTC instead
2346 */
2347 for_each_crtc(dev, c) {
2348 i = to_intel_crtc(c);
2349
2350 if (c == &intel_crtc->base)
2351 continue;
2352
2353 if (!i->active)
2354 continue;
2355
2356 obj = intel_fb_obj(c->primary->fb);
2357 if (obj == NULL)
2358 continue;
2359
2360 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2361 drm_framebuffer_reference(c->primary->fb);
2362 intel_crtc->base.primary->fb = c->primary->fb;
2363 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2364 break;
2365 }
2366 }
2367 }
2368
2369 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2370 struct drm_framebuffer *fb,
2371 int x, int y)
2372 {
2373 struct drm_device *dev = crtc->dev;
2374 struct drm_i915_private *dev_priv = dev->dev_private;
2375 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2376 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2377 int plane = intel_crtc->plane;
2378 unsigned long linear_offset;
2379 u32 dspcntr;
2380 u32 reg = DSPCNTR(plane);
2381
2382 if (!intel_crtc->primary_enabled) {
2383 I915_WRITE(reg, 0);
2384 if (INTEL_INFO(dev)->gen >= 4)
2385 I915_WRITE(DSPSURF(plane), 0);
2386 else
2387 I915_WRITE(DSPADDR(plane), 0);
2388 POSTING_READ(reg);
2389 return;
2390 }
2391
2392 dspcntr = DISPPLANE_GAMMA_ENABLE;
2393
2394 dspcntr |= DISPLAY_PLANE_ENABLE;
2395
2396 if (INTEL_INFO(dev)->gen < 4) {
2397 if (intel_crtc->pipe == PIPE_B)
2398 dspcntr |= DISPPLANE_SEL_PIPE_B;
2399
2400 /* pipesrc and dspsize control the size that is scaled from,
2401 * which should always be the user's requested size.
2402 */
2403 I915_WRITE(DSPSIZE(plane),
2404 ((intel_crtc->config.pipe_src_h - 1) << 16) |
2405 (intel_crtc->config.pipe_src_w - 1));
2406 I915_WRITE(DSPPOS(plane), 0);
2407 }
2408
2409 switch (fb->pixel_format) {
2410 case DRM_FORMAT_C8:
2411 dspcntr |= DISPPLANE_8BPP;
2412 break;
2413 case DRM_FORMAT_XRGB1555:
2414 case DRM_FORMAT_ARGB1555:
2415 dspcntr |= DISPPLANE_BGRX555;
2416 break;
2417 case DRM_FORMAT_RGB565:
2418 dspcntr |= DISPPLANE_BGRX565;
2419 break;
2420 case DRM_FORMAT_XRGB8888:
2421 case DRM_FORMAT_ARGB8888:
2422 dspcntr |= DISPPLANE_BGRX888;
2423 break;
2424 case DRM_FORMAT_XBGR8888:
2425 case DRM_FORMAT_ABGR8888:
2426 dspcntr |= DISPPLANE_RGBX888;
2427 break;
2428 case DRM_FORMAT_XRGB2101010:
2429 case DRM_FORMAT_ARGB2101010:
2430 dspcntr |= DISPPLANE_BGRX101010;
2431 break;
2432 case DRM_FORMAT_XBGR2101010:
2433 case DRM_FORMAT_ABGR2101010:
2434 dspcntr |= DISPPLANE_RGBX101010;
2435 break;
2436 default:
2437 BUG();
2438 }
2439
2440 if (INTEL_INFO(dev)->gen >= 4 &&
2441 obj->tiling_mode != I915_TILING_NONE)
2442 dspcntr |= DISPPLANE_TILED;
2443
2444 if (IS_G4X(dev))
2445 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2446
2447 I915_WRITE(reg, dspcntr);
2448
2449 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2450
2451 if (INTEL_INFO(dev)->gen >= 4) {
2452 intel_crtc->dspaddr_offset =
2453 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2454 fb->bits_per_pixel / 8,
2455 fb->pitches[0]);
2456 linear_offset -= intel_crtc->dspaddr_offset;
2457 } else {
2458 intel_crtc->dspaddr_offset = linear_offset;
2459 }
2460
2461 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2462 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2463 fb->pitches[0]);
2464 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2465 if (INTEL_INFO(dev)->gen >= 4) {
2466 I915_WRITE(DSPSURF(plane),
2467 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2468 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2469 I915_WRITE(DSPLINOFF(plane), linear_offset);
2470 } else
2471 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2472 POSTING_READ(reg);
2473 }
2474
2475 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2476 struct drm_framebuffer *fb,
2477 int x, int y)
2478 {
2479 struct drm_device *dev = crtc->dev;
2480 struct drm_i915_private *dev_priv = dev->dev_private;
2481 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2482 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2483 int plane = intel_crtc->plane;
2484 unsigned long linear_offset;
2485 u32 dspcntr;
2486 u32 reg = DSPCNTR(plane);
2487
2488 if (!intel_crtc->primary_enabled) {
2489 I915_WRITE(reg, 0);
2490 I915_WRITE(DSPSURF(plane), 0);
2491 POSTING_READ(reg);
2492 return;
2493 }
2494
2495 dspcntr = DISPPLANE_GAMMA_ENABLE;
2496
2497 dspcntr |= DISPLAY_PLANE_ENABLE;
2498
2499 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2500 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2501
2502 switch (fb->pixel_format) {
2503 case DRM_FORMAT_C8:
2504 dspcntr |= DISPPLANE_8BPP;
2505 break;
2506 case DRM_FORMAT_RGB565:
2507 dspcntr |= DISPPLANE_BGRX565;
2508 break;
2509 case DRM_FORMAT_XRGB8888:
2510 case DRM_FORMAT_ARGB8888:
2511 dspcntr |= DISPPLANE_BGRX888;
2512 break;
2513 case DRM_FORMAT_XBGR8888:
2514 case DRM_FORMAT_ABGR8888:
2515 dspcntr |= DISPPLANE_RGBX888;
2516 break;
2517 case DRM_FORMAT_XRGB2101010:
2518 case DRM_FORMAT_ARGB2101010:
2519 dspcntr |= DISPPLANE_BGRX101010;
2520 break;
2521 case DRM_FORMAT_XBGR2101010:
2522 case DRM_FORMAT_ABGR2101010:
2523 dspcntr |= DISPPLANE_RGBX101010;
2524 break;
2525 default:
2526 BUG();
2527 }
2528
2529 if (obj->tiling_mode != I915_TILING_NONE)
2530 dspcntr |= DISPPLANE_TILED;
2531
2532 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2533 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2534
2535 I915_WRITE(reg, dspcntr);
2536
2537 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2538 intel_crtc->dspaddr_offset =
2539 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2540 fb->bits_per_pixel / 8,
2541 fb->pitches[0]);
2542 linear_offset -= intel_crtc->dspaddr_offset;
2543
2544 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2545 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2546 fb->pitches[0]);
2547 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2548 I915_WRITE(DSPSURF(plane),
2549 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2550 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2551 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2552 } else {
2553 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2554 I915_WRITE(DSPLINOFF(plane), linear_offset);
2555 }
2556 POSTING_READ(reg);
2557 }
2558
2559 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2560 static int
2561 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2562 int x, int y, enum mode_set_atomic state)
2563 {
2564 struct drm_device *dev = crtc->dev;
2565 struct drm_i915_private *dev_priv = dev->dev_private;
2566
2567 if (dev_priv->display.disable_fbc)
2568 dev_priv->display.disable_fbc(dev);
2569 intel_increase_pllclock(dev, to_intel_crtc(crtc)->pipe);
2570
2571 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2572
2573 return 0;
2574 }
2575
2576 void intel_display_handle_reset(struct drm_device *dev)
2577 {
2578 struct drm_i915_private *dev_priv = dev->dev_private;
2579 struct drm_crtc *crtc;
2580
2581 /*
2582 * Flips in the rings have been nuked by the reset,
2583 * so complete all pending flips so that user space
2584 * will get its events and not get stuck.
2585 *
2586 * Also update the base address of all primary
2587 * planes to the the last fb to make sure we're
2588 * showing the correct fb after a reset.
2589 *
2590 * Need to make two loops over the crtcs so that we
2591 * don't try to grab a crtc mutex before the
2592 * pending_flip_queue really got woken up.
2593 */
2594
2595 for_each_crtc(dev, crtc) {
2596 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2597 enum plane plane = intel_crtc->plane;
2598
2599 intel_prepare_page_flip(dev, plane);
2600 intel_finish_page_flip_plane(dev, plane);
2601 }
2602
2603 for_each_crtc(dev, crtc) {
2604 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2605
2606 drm_modeset_lock(&crtc->mutex, NULL);
2607 /*
2608 * FIXME: Once we have proper support for primary planes (and
2609 * disabling them without disabling the entire crtc) allow again
2610 * a NULL crtc->primary->fb.
2611 */
2612 if (intel_crtc->active && crtc->primary->fb)
2613 dev_priv->display.update_primary_plane(crtc,
2614 crtc->primary->fb,
2615 crtc->x,
2616 crtc->y);
2617 drm_modeset_unlock(&crtc->mutex);
2618 }
2619 }
2620
2621 static int
2622 intel_finish_fb(struct drm_framebuffer *old_fb)
2623 {
2624 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2625 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2626 bool was_interruptible = dev_priv->mm.interruptible;
2627 int ret;
2628
2629 /* Big Hammer, we also need to ensure that any pending
2630 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2631 * current scanout is retired before unpinning the old
2632 * framebuffer.
2633 *
2634 * This should only fail upon a hung GPU, in which case we
2635 * can safely continue.
2636 */
2637 dev_priv->mm.interruptible = false;
2638 ret = i915_gem_object_finish_gpu(obj);
2639 dev_priv->mm.interruptible = was_interruptible;
2640
2641 return ret;
2642 }
2643
2644 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2645 {
2646 struct drm_device *dev = crtc->dev;
2647 struct drm_i915_private *dev_priv = dev->dev_private;
2648 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2649 unsigned long flags;
2650 bool pending;
2651
2652 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2653 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2654 return false;
2655
2656 spin_lock_irqsave(&dev->event_lock, flags);
2657 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2658 spin_unlock_irqrestore(&dev->event_lock, flags);
2659
2660 return pending;
2661 }
2662
2663 static int
2664 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2665 struct drm_framebuffer *fb)
2666 {
2667 struct drm_device *dev = crtc->dev;
2668 struct drm_i915_private *dev_priv = dev->dev_private;
2669 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2670 enum pipe pipe = intel_crtc->pipe;
2671 struct drm_framebuffer *old_fb = crtc->primary->fb;
2672 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2673 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
2674 int ret;
2675
2676 if (intel_crtc_has_pending_flip(crtc)) {
2677 DRM_ERROR("pipe is still busy with an old pageflip\n");
2678 return -EBUSY;
2679 }
2680
2681 /* no fb bound */
2682 if (!fb) {
2683 DRM_ERROR("No FB bound\n");
2684 return 0;
2685 }
2686
2687 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2688 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2689 plane_name(intel_crtc->plane),
2690 INTEL_INFO(dev)->num_pipes);
2691 return -EINVAL;
2692 }
2693
2694 mutex_lock(&dev->struct_mutex);
2695 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
2696 if (ret == 0)
2697 i915_gem_track_fb(old_obj, obj,
2698 INTEL_FRONTBUFFER_PRIMARY(pipe));
2699 mutex_unlock(&dev->struct_mutex);
2700 if (ret != 0) {
2701 DRM_ERROR("pin & fence failed\n");
2702 return ret;
2703 }
2704
2705 /*
2706 * Update pipe size and adjust fitter if needed: the reason for this is
2707 * that in compute_mode_changes we check the native mode (not the pfit
2708 * mode) to see if we can flip rather than do a full mode set. In the
2709 * fastboot case, we'll flip, but if we don't update the pipesrc and
2710 * pfit state, we'll end up with a big fb scanned out into the wrong
2711 * sized surface.
2712 *
2713 * To fix this properly, we need to hoist the checks up into
2714 * compute_mode_changes (or above), check the actual pfit state and
2715 * whether the platform allows pfit disable with pipe active, and only
2716 * then update the pipesrc and pfit state, even on the flip path.
2717 */
2718 if (i915.fastboot) {
2719 const struct drm_display_mode *adjusted_mode =
2720 &intel_crtc->config.adjusted_mode;
2721
2722 I915_WRITE(PIPESRC(intel_crtc->pipe),
2723 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2724 (adjusted_mode->crtc_vdisplay - 1));
2725 if (!intel_crtc->config.pch_pfit.enabled &&
2726 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2727 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2728 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2729 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2730 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2731 }
2732 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2733 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2734 }
2735
2736 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2737
2738 if (intel_crtc->active)
2739 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
2740
2741 crtc->primary->fb = fb;
2742 crtc->x = x;
2743 crtc->y = y;
2744
2745 if (old_fb) {
2746 if (intel_crtc->active && old_fb != fb)
2747 intel_wait_for_vblank(dev, intel_crtc->pipe);
2748 mutex_lock(&dev->struct_mutex);
2749 intel_unpin_fb_obj(old_obj);
2750 mutex_unlock(&dev->struct_mutex);
2751 }
2752
2753 mutex_lock(&dev->struct_mutex);
2754 intel_update_fbc(dev);
2755 mutex_unlock(&dev->struct_mutex);
2756
2757 return 0;
2758 }
2759
2760 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2761 {
2762 struct drm_device *dev = crtc->dev;
2763 struct drm_i915_private *dev_priv = dev->dev_private;
2764 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2765 int pipe = intel_crtc->pipe;
2766 u32 reg, temp;
2767
2768 /* enable normal train */
2769 reg = FDI_TX_CTL(pipe);
2770 temp = I915_READ(reg);
2771 if (IS_IVYBRIDGE(dev)) {
2772 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2773 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2774 } else {
2775 temp &= ~FDI_LINK_TRAIN_NONE;
2776 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2777 }
2778 I915_WRITE(reg, temp);
2779
2780 reg = FDI_RX_CTL(pipe);
2781 temp = I915_READ(reg);
2782 if (HAS_PCH_CPT(dev)) {
2783 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2784 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2785 } else {
2786 temp &= ~FDI_LINK_TRAIN_NONE;
2787 temp |= FDI_LINK_TRAIN_NONE;
2788 }
2789 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2790
2791 /* wait one idle pattern time */
2792 POSTING_READ(reg);
2793 udelay(1000);
2794
2795 /* IVB wants error correction enabled */
2796 if (IS_IVYBRIDGE(dev))
2797 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2798 FDI_FE_ERRC_ENABLE);
2799 }
2800
2801 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2802 {
2803 return crtc->base.enabled && crtc->active &&
2804 crtc->config.has_pch_encoder;
2805 }
2806
2807 static void ivb_modeset_global_resources(struct drm_device *dev)
2808 {
2809 struct drm_i915_private *dev_priv = dev->dev_private;
2810 struct intel_crtc *pipe_B_crtc =
2811 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2812 struct intel_crtc *pipe_C_crtc =
2813 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2814 uint32_t temp;
2815
2816 /*
2817 * When everything is off disable fdi C so that we could enable fdi B
2818 * with all lanes. Note that we don't care about enabled pipes without
2819 * an enabled pch encoder.
2820 */
2821 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2822 !pipe_has_enabled_pch(pipe_C_crtc)) {
2823 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2824 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2825
2826 temp = I915_READ(SOUTH_CHICKEN1);
2827 temp &= ~FDI_BC_BIFURCATION_SELECT;
2828 DRM_DEBUG_KMS("disabling fdi C rx\n");
2829 I915_WRITE(SOUTH_CHICKEN1, temp);
2830 }
2831 }
2832
2833 /* The FDI link training functions for ILK/Ibexpeak. */
2834 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2835 {
2836 struct drm_device *dev = crtc->dev;
2837 struct drm_i915_private *dev_priv = dev->dev_private;
2838 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2839 int pipe = intel_crtc->pipe;
2840 u32 reg, temp, tries;
2841
2842 /* FDI needs bits from pipe first */
2843 assert_pipe_enabled(dev_priv, pipe);
2844
2845 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2846 for train result */
2847 reg = FDI_RX_IMR(pipe);
2848 temp = I915_READ(reg);
2849 temp &= ~FDI_RX_SYMBOL_LOCK;
2850 temp &= ~FDI_RX_BIT_LOCK;
2851 I915_WRITE(reg, temp);
2852 I915_READ(reg);
2853 udelay(150);
2854
2855 /* enable CPU FDI TX and PCH FDI RX */
2856 reg = FDI_TX_CTL(pipe);
2857 temp = I915_READ(reg);
2858 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2859 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2860 temp &= ~FDI_LINK_TRAIN_NONE;
2861 temp |= FDI_LINK_TRAIN_PATTERN_1;
2862 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2863
2864 reg = FDI_RX_CTL(pipe);
2865 temp = I915_READ(reg);
2866 temp &= ~FDI_LINK_TRAIN_NONE;
2867 temp |= FDI_LINK_TRAIN_PATTERN_1;
2868 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2869
2870 POSTING_READ(reg);
2871 udelay(150);
2872
2873 /* Ironlake workaround, enable clock pointer after FDI enable*/
2874 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2875 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2876 FDI_RX_PHASE_SYNC_POINTER_EN);
2877
2878 reg = FDI_RX_IIR(pipe);
2879 for (tries = 0; tries < 5; tries++) {
2880 temp = I915_READ(reg);
2881 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2882
2883 if ((temp & FDI_RX_BIT_LOCK)) {
2884 DRM_DEBUG_KMS("FDI train 1 done.\n");
2885 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2886 break;
2887 }
2888 }
2889 if (tries == 5)
2890 DRM_ERROR("FDI train 1 fail!\n");
2891
2892 /* Train 2 */
2893 reg = FDI_TX_CTL(pipe);
2894 temp = I915_READ(reg);
2895 temp &= ~FDI_LINK_TRAIN_NONE;
2896 temp |= FDI_LINK_TRAIN_PATTERN_2;
2897 I915_WRITE(reg, temp);
2898
2899 reg = FDI_RX_CTL(pipe);
2900 temp = I915_READ(reg);
2901 temp &= ~FDI_LINK_TRAIN_NONE;
2902 temp |= FDI_LINK_TRAIN_PATTERN_2;
2903 I915_WRITE(reg, temp);
2904
2905 POSTING_READ(reg);
2906 udelay(150);
2907
2908 reg = FDI_RX_IIR(pipe);
2909 for (tries = 0; tries < 5; tries++) {
2910 temp = I915_READ(reg);
2911 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2912
2913 if (temp & FDI_RX_SYMBOL_LOCK) {
2914 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2915 DRM_DEBUG_KMS("FDI train 2 done.\n");
2916 break;
2917 }
2918 }
2919 if (tries == 5)
2920 DRM_ERROR("FDI train 2 fail!\n");
2921
2922 DRM_DEBUG_KMS("FDI train done\n");
2923
2924 }
2925
2926 static const int snb_b_fdi_train_param[] = {
2927 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2928 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2929 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2930 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2931 };
2932
2933 /* The FDI link training functions for SNB/Cougarpoint. */
2934 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2935 {
2936 struct drm_device *dev = crtc->dev;
2937 struct drm_i915_private *dev_priv = dev->dev_private;
2938 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2939 int pipe = intel_crtc->pipe;
2940 u32 reg, temp, i, retry;
2941
2942 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2943 for train result */
2944 reg = FDI_RX_IMR(pipe);
2945 temp = I915_READ(reg);
2946 temp &= ~FDI_RX_SYMBOL_LOCK;
2947 temp &= ~FDI_RX_BIT_LOCK;
2948 I915_WRITE(reg, temp);
2949
2950 POSTING_READ(reg);
2951 udelay(150);
2952
2953 /* enable CPU FDI TX and PCH FDI RX */
2954 reg = FDI_TX_CTL(pipe);
2955 temp = I915_READ(reg);
2956 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2957 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2958 temp &= ~FDI_LINK_TRAIN_NONE;
2959 temp |= FDI_LINK_TRAIN_PATTERN_1;
2960 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2961 /* SNB-B */
2962 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2963 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2964
2965 I915_WRITE(FDI_RX_MISC(pipe),
2966 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2967
2968 reg = FDI_RX_CTL(pipe);
2969 temp = I915_READ(reg);
2970 if (HAS_PCH_CPT(dev)) {
2971 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2972 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2973 } else {
2974 temp &= ~FDI_LINK_TRAIN_NONE;
2975 temp |= FDI_LINK_TRAIN_PATTERN_1;
2976 }
2977 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2978
2979 POSTING_READ(reg);
2980 udelay(150);
2981
2982 for (i = 0; i < 4; i++) {
2983 reg = FDI_TX_CTL(pipe);
2984 temp = I915_READ(reg);
2985 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2986 temp |= snb_b_fdi_train_param[i];
2987 I915_WRITE(reg, temp);
2988
2989 POSTING_READ(reg);
2990 udelay(500);
2991
2992 for (retry = 0; retry < 5; retry++) {
2993 reg = FDI_RX_IIR(pipe);
2994 temp = I915_READ(reg);
2995 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2996 if (temp & FDI_RX_BIT_LOCK) {
2997 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2998 DRM_DEBUG_KMS("FDI train 1 done.\n");
2999 break;
3000 }
3001 udelay(50);
3002 }
3003 if (retry < 5)
3004 break;
3005 }
3006 if (i == 4)
3007 DRM_ERROR("FDI train 1 fail!\n");
3008
3009 /* Train 2 */
3010 reg = FDI_TX_CTL(pipe);
3011 temp = I915_READ(reg);
3012 temp &= ~FDI_LINK_TRAIN_NONE;
3013 temp |= FDI_LINK_TRAIN_PATTERN_2;
3014 if (IS_GEN6(dev)) {
3015 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3016 /* SNB-B */
3017 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3018 }
3019 I915_WRITE(reg, temp);
3020
3021 reg = FDI_RX_CTL(pipe);
3022 temp = I915_READ(reg);
3023 if (HAS_PCH_CPT(dev)) {
3024 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3025 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3026 } else {
3027 temp &= ~FDI_LINK_TRAIN_NONE;
3028 temp |= FDI_LINK_TRAIN_PATTERN_2;
3029 }
3030 I915_WRITE(reg, temp);
3031
3032 POSTING_READ(reg);
3033 udelay(150);
3034
3035 for (i = 0; i < 4; i++) {
3036 reg = FDI_TX_CTL(pipe);
3037 temp = I915_READ(reg);
3038 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3039 temp |= snb_b_fdi_train_param[i];
3040 I915_WRITE(reg, temp);
3041
3042 POSTING_READ(reg);
3043 udelay(500);
3044
3045 for (retry = 0; retry < 5; retry++) {
3046 reg = FDI_RX_IIR(pipe);
3047 temp = I915_READ(reg);
3048 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3049 if (temp & FDI_RX_SYMBOL_LOCK) {
3050 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3051 DRM_DEBUG_KMS("FDI train 2 done.\n");
3052 break;
3053 }
3054 udelay(50);
3055 }
3056 if (retry < 5)
3057 break;
3058 }
3059 if (i == 4)
3060 DRM_ERROR("FDI train 2 fail!\n");
3061
3062 DRM_DEBUG_KMS("FDI train done.\n");
3063 }
3064
3065 /* Manual link training for Ivy Bridge A0 parts */
3066 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3067 {
3068 struct drm_device *dev = crtc->dev;
3069 struct drm_i915_private *dev_priv = dev->dev_private;
3070 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3071 int pipe = intel_crtc->pipe;
3072 u32 reg, temp, i, j;
3073
3074 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3075 for train result */
3076 reg = FDI_RX_IMR(pipe);
3077 temp = I915_READ(reg);
3078 temp &= ~FDI_RX_SYMBOL_LOCK;
3079 temp &= ~FDI_RX_BIT_LOCK;
3080 I915_WRITE(reg, temp);
3081
3082 POSTING_READ(reg);
3083 udelay(150);
3084
3085 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3086 I915_READ(FDI_RX_IIR(pipe)));
3087
3088 /* Try each vswing and preemphasis setting twice before moving on */
3089 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3090 /* disable first in case we need to retry */
3091 reg = FDI_TX_CTL(pipe);
3092 temp = I915_READ(reg);
3093 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3094 temp &= ~FDI_TX_ENABLE;
3095 I915_WRITE(reg, temp);
3096
3097 reg = FDI_RX_CTL(pipe);
3098 temp = I915_READ(reg);
3099 temp &= ~FDI_LINK_TRAIN_AUTO;
3100 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3101 temp &= ~FDI_RX_ENABLE;
3102 I915_WRITE(reg, temp);
3103
3104 /* enable CPU FDI TX and PCH FDI RX */
3105 reg = FDI_TX_CTL(pipe);
3106 temp = I915_READ(reg);
3107 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3108 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3109 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3110 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3111 temp |= snb_b_fdi_train_param[j/2];
3112 temp |= FDI_COMPOSITE_SYNC;
3113 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3114
3115 I915_WRITE(FDI_RX_MISC(pipe),
3116 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3117
3118 reg = FDI_RX_CTL(pipe);
3119 temp = I915_READ(reg);
3120 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3121 temp |= FDI_COMPOSITE_SYNC;
3122 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3123
3124 POSTING_READ(reg);
3125 udelay(1); /* should be 0.5us */
3126
3127 for (i = 0; i < 4; i++) {
3128 reg = FDI_RX_IIR(pipe);
3129 temp = I915_READ(reg);
3130 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3131
3132 if (temp & FDI_RX_BIT_LOCK ||
3133 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3134 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3135 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3136 i);
3137 break;
3138 }
3139 udelay(1); /* should be 0.5us */
3140 }
3141 if (i == 4) {
3142 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3143 continue;
3144 }
3145
3146 /* Train 2 */
3147 reg = FDI_TX_CTL(pipe);
3148 temp = I915_READ(reg);
3149 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3150 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3151 I915_WRITE(reg, temp);
3152
3153 reg = FDI_RX_CTL(pipe);
3154 temp = I915_READ(reg);
3155 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3156 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3157 I915_WRITE(reg, temp);
3158
3159 POSTING_READ(reg);
3160 udelay(2); /* should be 1.5us */
3161
3162 for (i = 0; i < 4; i++) {
3163 reg = FDI_RX_IIR(pipe);
3164 temp = I915_READ(reg);
3165 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3166
3167 if (temp & FDI_RX_SYMBOL_LOCK ||
3168 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3169 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3170 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3171 i);
3172 goto train_done;
3173 }
3174 udelay(2); /* should be 1.5us */
3175 }
3176 if (i == 4)
3177 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3178 }
3179
3180 train_done:
3181 DRM_DEBUG_KMS("FDI train done.\n");
3182 }
3183
3184 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3185 {
3186 struct drm_device *dev = intel_crtc->base.dev;
3187 struct drm_i915_private *dev_priv = dev->dev_private;
3188 int pipe = intel_crtc->pipe;
3189 u32 reg, temp;
3190
3191
3192 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3193 reg = FDI_RX_CTL(pipe);
3194 temp = I915_READ(reg);
3195 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3196 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3197 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3198 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3199
3200 POSTING_READ(reg);
3201 udelay(200);
3202
3203 /* Switch from Rawclk to PCDclk */
3204 temp = I915_READ(reg);
3205 I915_WRITE(reg, temp | FDI_PCDCLK);
3206
3207 POSTING_READ(reg);
3208 udelay(200);
3209
3210 /* Enable CPU FDI TX PLL, always on for Ironlake */
3211 reg = FDI_TX_CTL(pipe);
3212 temp = I915_READ(reg);
3213 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3214 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3215
3216 POSTING_READ(reg);
3217 udelay(100);
3218 }
3219 }
3220
3221 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3222 {
3223 struct drm_device *dev = intel_crtc->base.dev;
3224 struct drm_i915_private *dev_priv = dev->dev_private;
3225 int pipe = intel_crtc->pipe;
3226 u32 reg, temp;
3227
3228 /* Switch from PCDclk to Rawclk */
3229 reg = FDI_RX_CTL(pipe);
3230 temp = I915_READ(reg);
3231 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3232
3233 /* Disable CPU FDI TX PLL */
3234 reg = FDI_TX_CTL(pipe);
3235 temp = I915_READ(reg);
3236 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3237
3238 POSTING_READ(reg);
3239 udelay(100);
3240
3241 reg = FDI_RX_CTL(pipe);
3242 temp = I915_READ(reg);
3243 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3244
3245 /* Wait for the clocks to turn off. */
3246 POSTING_READ(reg);
3247 udelay(100);
3248 }
3249
3250 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3251 {
3252 struct drm_device *dev = crtc->dev;
3253 struct drm_i915_private *dev_priv = dev->dev_private;
3254 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3255 int pipe = intel_crtc->pipe;
3256 u32 reg, temp;
3257
3258 /* disable CPU FDI tx and PCH FDI rx */
3259 reg = FDI_TX_CTL(pipe);
3260 temp = I915_READ(reg);
3261 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3262 POSTING_READ(reg);
3263
3264 reg = FDI_RX_CTL(pipe);
3265 temp = I915_READ(reg);
3266 temp &= ~(0x7 << 16);
3267 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3268 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3269
3270 POSTING_READ(reg);
3271 udelay(100);
3272
3273 /* Ironlake workaround, disable clock pointer after downing FDI */
3274 if (HAS_PCH_IBX(dev))
3275 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3276
3277 /* still set train pattern 1 */
3278 reg = FDI_TX_CTL(pipe);
3279 temp = I915_READ(reg);
3280 temp &= ~FDI_LINK_TRAIN_NONE;
3281 temp |= FDI_LINK_TRAIN_PATTERN_1;
3282 I915_WRITE(reg, temp);
3283
3284 reg = FDI_RX_CTL(pipe);
3285 temp = I915_READ(reg);
3286 if (HAS_PCH_CPT(dev)) {
3287 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3288 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3289 } else {
3290 temp &= ~FDI_LINK_TRAIN_NONE;
3291 temp |= FDI_LINK_TRAIN_PATTERN_1;
3292 }
3293 /* BPC in FDI rx is consistent with that in PIPECONF */
3294 temp &= ~(0x07 << 16);
3295 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3296 I915_WRITE(reg, temp);
3297
3298 POSTING_READ(reg);
3299 udelay(100);
3300 }
3301
3302 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3303 {
3304 struct intel_crtc *crtc;
3305
3306 /* Note that we don't need to be called with mode_config.lock here
3307 * as our list of CRTC objects is static for the lifetime of the
3308 * device and so cannot disappear as we iterate. Similarly, we can
3309 * happily treat the predicates as racy, atomic checks as userspace
3310 * cannot claim and pin a new fb without at least acquring the
3311 * struct_mutex and so serialising with us.
3312 */
3313 for_each_intel_crtc(dev, crtc) {
3314 if (atomic_read(&crtc->unpin_work_count) == 0)
3315 continue;
3316
3317 if (crtc->unpin_work)
3318 intel_wait_for_vblank(dev, crtc->pipe);
3319
3320 return true;
3321 }
3322
3323 return false;
3324 }
3325
3326 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3327 {
3328 struct drm_device *dev = crtc->dev;
3329 struct drm_i915_private *dev_priv = dev->dev_private;
3330
3331 if (crtc->primary->fb == NULL)
3332 return;
3333
3334 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3335
3336 WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3337 !intel_crtc_has_pending_flip(crtc),
3338 60*HZ) == 0);
3339
3340 mutex_lock(&dev->struct_mutex);
3341 intel_finish_fb(crtc->primary->fb);
3342 mutex_unlock(&dev->struct_mutex);
3343 }
3344
3345 /* Program iCLKIP clock to the desired frequency */
3346 static void lpt_program_iclkip(struct drm_crtc *crtc)
3347 {
3348 struct drm_device *dev = crtc->dev;
3349 struct drm_i915_private *dev_priv = dev->dev_private;
3350 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3351 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3352 u32 temp;
3353
3354 mutex_lock(&dev_priv->dpio_lock);
3355
3356 /* It is necessary to ungate the pixclk gate prior to programming
3357 * the divisors, and gate it back when it is done.
3358 */
3359 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3360
3361 /* Disable SSCCTL */
3362 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3363 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3364 SBI_SSCCTL_DISABLE,
3365 SBI_ICLK);
3366
3367 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3368 if (clock == 20000) {
3369 auxdiv = 1;
3370 divsel = 0x41;
3371 phaseinc = 0x20;
3372 } else {
3373 /* The iCLK virtual clock root frequency is in MHz,
3374 * but the adjusted_mode->crtc_clock in in KHz. To get the
3375 * divisors, it is necessary to divide one by another, so we
3376 * convert the virtual clock precision to KHz here for higher
3377 * precision.
3378 */
3379 u32 iclk_virtual_root_freq = 172800 * 1000;
3380 u32 iclk_pi_range = 64;
3381 u32 desired_divisor, msb_divisor_value, pi_value;
3382
3383 desired_divisor = (iclk_virtual_root_freq / clock);
3384 msb_divisor_value = desired_divisor / iclk_pi_range;
3385 pi_value = desired_divisor % iclk_pi_range;
3386
3387 auxdiv = 0;
3388 divsel = msb_divisor_value - 2;
3389 phaseinc = pi_value;
3390 }
3391
3392 /* This should not happen with any sane values */
3393 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3394 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3395 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3396 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3397
3398 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3399 clock,
3400 auxdiv,
3401 divsel,
3402 phasedir,
3403 phaseinc);
3404
3405 /* Program SSCDIVINTPHASE6 */
3406 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3407 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3408 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3409 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3410 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3411 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3412 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3413 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3414
3415 /* Program SSCAUXDIV */
3416 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3417 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3418 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3419 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3420
3421 /* Enable modulator and associated divider */
3422 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3423 temp &= ~SBI_SSCCTL_DISABLE;
3424 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3425
3426 /* Wait for initialization time */
3427 udelay(24);
3428
3429 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3430
3431 mutex_unlock(&dev_priv->dpio_lock);
3432 }
3433
3434 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3435 enum pipe pch_transcoder)
3436 {
3437 struct drm_device *dev = crtc->base.dev;
3438 struct drm_i915_private *dev_priv = dev->dev_private;
3439 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3440
3441 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3442 I915_READ(HTOTAL(cpu_transcoder)));
3443 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3444 I915_READ(HBLANK(cpu_transcoder)));
3445 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3446 I915_READ(HSYNC(cpu_transcoder)));
3447
3448 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3449 I915_READ(VTOTAL(cpu_transcoder)));
3450 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3451 I915_READ(VBLANK(cpu_transcoder)));
3452 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3453 I915_READ(VSYNC(cpu_transcoder)));
3454 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3455 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3456 }
3457
3458 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3459 {
3460 struct drm_i915_private *dev_priv = dev->dev_private;
3461 uint32_t temp;
3462
3463 temp = I915_READ(SOUTH_CHICKEN1);
3464 if (temp & FDI_BC_BIFURCATION_SELECT)
3465 return;
3466
3467 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3468 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3469
3470 temp |= FDI_BC_BIFURCATION_SELECT;
3471 DRM_DEBUG_KMS("enabling fdi C rx\n");
3472 I915_WRITE(SOUTH_CHICKEN1, temp);
3473 POSTING_READ(SOUTH_CHICKEN1);
3474 }
3475
3476 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3477 {
3478 struct drm_device *dev = intel_crtc->base.dev;
3479 struct drm_i915_private *dev_priv = dev->dev_private;
3480
3481 switch (intel_crtc->pipe) {
3482 case PIPE_A:
3483 break;
3484 case PIPE_B:
3485 if (intel_crtc->config.fdi_lanes > 2)
3486 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3487 else
3488 cpt_enable_fdi_bc_bifurcation(dev);
3489
3490 break;
3491 case PIPE_C:
3492 cpt_enable_fdi_bc_bifurcation(dev);
3493
3494 break;
3495 default:
3496 BUG();
3497 }
3498 }
3499
3500 /*
3501 * Enable PCH resources required for PCH ports:
3502 * - PCH PLLs
3503 * - FDI training & RX/TX
3504 * - update transcoder timings
3505 * - DP transcoding bits
3506 * - transcoder
3507 */
3508 static void ironlake_pch_enable(struct drm_crtc *crtc)
3509 {
3510 struct drm_device *dev = crtc->dev;
3511 struct drm_i915_private *dev_priv = dev->dev_private;
3512 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3513 int pipe = intel_crtc->pipe;
3514 u32 reg, temp;
3515
3516 assert_pch_transcoder_disabled(dev_priv, pipe);
3517
3518 if (IS_IVYBRIDGE(dev))
3519 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3520
3521 /* Write the TU size bits before fdi link training, so that error
3522 * detection works. */
3523 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3524 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3525
3526 /* For PCH output, training FDI link */
3527 dev_priv->display.fdi_link_train(crtc);
3528
3529 /* We need to program the right clock selection before writing the pixel
3530 * mutliplier into the DPLL. */
3531 if (HAS_PCH_CPT(dev)) {
3532 u32 sel;
3533
3534 temp = I915_READ(PCH_DPLL_SEL);
3535 temp |= TRANS_DPLL_ENABLE(pipe);
3536 sel = TRANS_DPLLB_SEL(pipe);
3537 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3538 temp |= sel;
3539 else
3540 temp &= ~sel;
3541 I915_WRITE(PCH_DPLL_SEL, temp);
3542 }
3543
3544 /* XXX: pch pll's can be enabled any time before we enable the PCH
3545 * transcoder, and we actually should do this to not upset any PCH
3546 * transcoder that already use the clock when we share it.
3547 *
3548 * Note that enable_shared_dpll tries to do the right thing, but
3549 * get_shared_dpll unconditionally resets the pll - we need that to have
3550 * the right LVDS enable sequence. */
3551 intel_enable_shared_dpll(intel_crtc);
3552
3553 /* set transcoder timing, panel must allow it */
3554 assert_panel_unlocked(dev_priv, pipe);
3555 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3556
3557 intel_fdi_normal_train(crtc);
3558
3559 /* For PCH DP, enable TRANS_DP_CTL */
3560 if (HAS_PCH_CPT(dev) &&
3561 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3562 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3563 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3564 reg = TRANS_DP_CTL(pipe);
3565 temp = I915_READ(reg);
3566 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3567 TRANS_DP_SYNC_MASK |
3568 TRANS_DP_BPC_MASK);
3569 temp |= (TRANS_DP_OUTPUT_ENABLE |
3570 TRANS_DP_ENH_FRAMING);
3571 temp |= bpc << 9; /* same format but at 11:9 */
3572
3573 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3574 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3575 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3576 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3577
3578 switch (intel_trans_dp_port_sel(crtc)) {
3579 case PCH_DP_B:
3580 temp |= TRANS_DP_PORT_SEL_B;
3581 break;
3582 case PCH_DP_C:
3583 temp |= TRANS_DP_PORT_SEL_C;
3584 break;
3585 case PCH_DP_D:
3586 temp |= TRANS_DP_PORT_SEL_D;
3587 break;
3588 default:
3589 BUG();
3590 }
3591
3592 I915_WRITE(reg, temp);
3593 }
3594
3595 ironlake_enable_pch_transcoder(dev_priv, pipe);
3596 }
3597
3598 static void lpt_pch_enable(struct drm_crtc *crtc)
3599 {
3600 struct drm_device *dev = crtc->dev;
3601 struct drm_i915_private *dev_priv = dev->dev_private;
3602 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3603 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3604
3605 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3606
3607 lpt_program_iclkip(crtc);
3608
3609 /* Set transcoder timing. */
3610 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3611
3612 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3613 }
3614
3615 void intel_put_shared_dpll(struct intel_crtc *crtc)
3616 {
3617 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3618
3619 if (pll == NULL)
3620 return;
3621
3622 if (pll->refcount == 0) {
3623 WARN(1, "bad %s refcount\n", pll->name);
3624 return;
3625 }
3626
3627 if (--pll->refcount == 0) {
3628 WARN_ON(pll->on);
3629 WARN_ON(pll->active);
3630 }
3631
3632 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3633 }
3634
3635 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3636 {
3637 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3638 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3639 enum intel_dpll_id i;
3640
3641 if (pll) {
3642 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3643 crtc->base.base.id, pll->name);
3644 intel_put_shared_dpll(crtc);
3645 }
3646
3647 if (HAS_PCH_IBX(dev_priv->dev)) {
3648 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3649 i = (enum intel_dpll_id) crtc->pipe;
3650 pll = &dev_priv->shared_dplls[i];
3651
3652 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3653 crtc->base.base.id, pll->name);
3654
3655 WARN_ON(pll->refcount);
3656
3657 goto found;
3658 }
3659
3660 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3661 pll = &dev_priv->shared_dplls[i];
3662
3663 /* Only want to check enabled timings first */
3664 if (pll->refcount == 0)
3665 continue;
3666
3667 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3668 sizeof(pll->hw_state)) == 0) {
3669 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3670 crtc->base.base.id,
3671 pll->name, pll->refcount, pll->active);
3672
3673 goto found;
3674 }
3675 }
3676
3677 /* Ok no matching timings, maybe there's a free one? */
3678 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3679 pll = &dev_priv->shared_dplls[i];
3680 if (pll->refcount == 0) {
3681 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3682 crtc->base.base.id, pll->name);
3683 goto found;
3684 }
3685 }
3686
3687 return NULL;
3688
3689 found:
3690 if (pll->refcount == 0)
3691 pll->hw_state = crtc->config.dpll_hw_state;
3692
3693 crtc->config.shared_dpll = i;
3694 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3695 pipe_name(crtc->pipe));
3696
3697 pll->refcount++;
3698
3699 return pll;
3700 }
3701
3702 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3703 {
3704 struct drm_i915_private *dev_priv = dev->dev_private;
3705 int dslreg = PIPEDSL(pipe);
3706 u32 temp;
3707
3708 temp = I915_READ(dslreg);
3709 udelay(500);
3710 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3711 if (wait_for(I915_READ(dslreg) != temp, 5))
3712 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3713 }
3714 }
3715
3716 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3717 {
3718 struct drm_device *dev = crtc->base.dev;
3719 struct drm_i915_private *dev_priv = dev->dev_private;
3720 int pipe = crtc->pipe;
3721
3722 if (crtc->config.pch_pfit.enabled) {
3723 /* Force use of hard-coded filter coefficients
3724 * as some pre-programmed values are broken,
3725 * e.g. x201.
3726 */
3727 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3728 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3729 PF_PIPE_SEL_IVB(pipe));
3730 else
3731 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3732 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3733 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3734 }
3735 }
3736
3737 static void intel_enable_planes(struct drm_crtc *crtc)
3738 {
3739 struct drm_device *dev = crtc->dev;
3740 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3741 struct drm_plane *plane;
3742 struct intel_plane *intel_plane;
3743
3744 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3745 intel_plane = to_intel_plane(plane);
3746 if (intel_plane->pipe == pipe)
3747 intel_plane_restore(&intel_plane->base);
3748 }
3749 }
3750
3751 static void intel_disable_planes(struct drm_crtc *crtc)
3752 {
3753 struct drm_device *dev = crtc->dev;
3754 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3755 struct drm_plane *plane;
3756 struct intel_plane *intel_plane;
3757
3758 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3759 intel_plane = to_intel_plane(plane);
3760 if (intel_plane->pipe == pipe)
3761 intel_plane_disable(&intel_plane->base);
3762 }
3763 }
3764
3765 void hsw_enable_ips(struct intel_crtc *crtc)
3766 {
3767 struct drm_device *dev = crtc->base.dev;
3768 struct drm_i915_private *dev_priv = dev->dev_private;
3769
3770 if (!crtc->config.ips_enabled)
3771 return;
3772
3773 /* We can only enable IPS after we enable a plane and wait for a vblank */
3774 intel_wait_for_vblank(dev, crtc->pipe);
3775
3776 assert_plane_enabled(dev_priv, crtc->plane);
3777 if (IS_BROADWELL(dev)) {
3778 mutex_lock(&dev_priv->rps.hw_lock);
3779 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3780 mutex_unlock(&dev_priv->rps.hw_lock);
3781 /* Quoting Art Runyan: "its not safe to expect any particular
3782 * value in IPS_CTL bit 31 after enabling IPS through the
3783 * mailbox." Moreover, the mailbox may return a bogus state,
3784 * so we need to just enable it and continue on.
3785 */
3786 } else {
3787 I915_WRITE(IPS_CTL, IPS_ENABLE);
3788 /* The bit only becomes 1 in the next vblank, so this wait here
3789 * is essentially intel_wait_for_vblank. If we don't have this
3790 * and don't wait for vblanks until the end of crtc_enable, then
3791 * the HW state readout code will complain that the expected
3792 * IPS_CTL value is not the one we read. */
3793 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3794 DRM_ERROR("Timed out waiting for IPS enable\n");
3795 }
3796 }
3797
3798 void hsw_disable_ips(struct intel_crtc *crtc)
3799 {
3800 struct drm_device *dev = crtc->base.dev;
3801 struct drm_i915_private *dev_priv = dev->dev_private;
3802
3803 if (!crtc->config.ips_enabled)
3804 return;
3805
3806 assert_plane_enabled(dev_priv, crtc->plane);
3807 if (IS_BROADWELL(dev)) {
3808 mutex_lock(&dev_priv->rps.hw_lock);
3809 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3810 mutex_unlock(&dev_priv->rps.hw_lock);
3811 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3812 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3813 DRM_ERROR("Timed out waiting for IPS disable\n");
3814 } else {
3815 I915_WRITE(IPS_CTL, 0);
3816 POSTING_READ(IPS_CTL);
3817 }
3818
3819 /* We need to wait for a vblank before we can disable the plane. */
3820 intel_wait_for_vblank(dev, crtc->pipe);
3821 }
3822
3823 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3824 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3825 {
3826 struct drm_device *dev = crtc->dev;
3827 struct drm_i915_private *dev_priv = dev->dev_private;
3828 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3829 enum pipe pipe = intel_crtc->pipe;
3830 int palreg = PALETTE(pipe);
3831 int i;
3832 bool reenable_ips = false;
3833
3834 /* The clocks have to be on to load the palette. */
3835 if (!crtc->enabled || !intel_crtc->active)
3836 return;
3837
3838 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3839 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3840 assert_dsi_pll_enabled(dev_priv);
3841 else
3842 assert_pll_enabled(dev_priv, pipe);
3843 }
3844
3845 /* use legacy palette for Ironlake */
3846 if (!HAS_GMCH_DISPLAY(dev))
3847 palreg = LGC_PALETTE(pipe);
3848
3849 /* Workaround : Do not read or write the pipe palette/gamma data while
3850 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3851 */
3852 if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3853 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3854 GAMMA_MODE_MODE_SPLIT)) {
3855 hsw_disable_ips(intel_crtc);
3856 reenable_ips = true;
3857 }
3858
3859 for (i = 0; i < 256; i++) {
3860 I915_WRITE(palreg + 4 * i,
3861 (intel_crtc->lut_r[i] << 16) |
3862 (intel_crtc->lut_g[i] << 8) |
3863 intel_crtc->lut_b[i]);
3864 }
3865
3866 if (reenable_ips)
3867 hsw_enable_ips(intel_crtc);
3868 }
3869
3870 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3871 {
3872 if (!enable && intel_crtc->overlay) {
3873 struct drm_device *dev = intel_crtc->base.dev;
3874 struct drm_i915_private *dev_priv = dev->dev_private;
3875
3876 mutex_lock(&dev->struct_mutex);
3877 dev_priv->mm.interruptible = false;
3878 (void) intel_overlay_switch_off(intel_crtc->overlay);
3879 dev_priv->mm.interruptible = true;
3880 mutex_unlock(&dev->struct_mutex);
3881 }
3882
3883 /* Let userspace switch the overlay on again. In most cases userspace
3884 * has to recompute where to put it anyway.
3885 */
3886 }
3887
3888 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
3889 {
3890 struct drm_device *dev = crtc->dev;
3891 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3892 int pipe = intel_crtc->pipe;
3893
3894 drm_vblank_on(dev, pipe);
3895
3896 intel_enable_primary_hw_plane(crtc->primary, crtc);
3897 intel_enable_planes(crtc);
3898 intel_crtc_update_cursor(crtc, true);
3899 intel_crtc_dpms_overlay(intel_crtc, true);
3900
3901 hsw_enable_ips(intel_crtc);
3902
3903 mutex_lock(&dev->struct_mutex);
3904 intel_update_fbc(dev);
3905 mutex_unlock(&dev->struct_mutex);
3906
3907 /*
3908 * FIXME: Once we grow proper nuclear flip support out of this we need
3909 * to compute the mask of flip planes precisely. For the time being
3910 * consider this a flip from a NULL plane.
3911 */
3912 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
3913 }
3914
3915 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
3916 {
3917 struct drm_device *dev = crtc->dev;
3918 struct drm_i915_private *dev_priv = dev->dev_private;
3919 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3920 int pipe = intel_crtc->pipe;
3921 int plane = intel_crtc->plane;
3922
3923 intel_crtc_wait_for_pending_flips(crtc);
3924
3925 if (dev_priv->fbc.plane == plane)
3926 intel_disable_fbc(dev);
3927
3928 hsw_disable_ips(intel_crtc);
3929
3930 intel_crtc_dpms_overlay(intel_crtc, false);
3931 intel_crtc_update_cursor(crtc, false);
3932 intel_disable_planes(crtc);
3933 intel_disable_primary_hw_plane(crtc->primary, crtc);
3934
3935 /*
3936 * FIXME: Once we grow proper nuclear flip support out of this we need
3937 * to compute the mask of flip planes precisely. For the time being
3938 * consider this a flip to a NULL plane.
3939 */
3940 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
3941
3942 drm_vblank_off(dev, pipe);
3943 }
3944
3945 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3946 {
3947 struct drm_device *dev = crtc->dev;
3948 struct drm_i915_private *dev_priv = dev->dev_private;
3949 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3950 struct intel_encoder *encoder;
3951 int pipe = intel_crtc->pipe;
3952
3953 WARN_ON(!crtc->enabled);
3954
3955 if (intel_crtc->active)
3956 return;
3957
3958 if (intel_crtc->config.has_pch_encoder)
3959 intel_prepare_shared_dpll(intel_crtc);
3960
3961 if (intel_crtc->config.has_dp_encoder)
3962 intel_dp_set_m_n(intel_crtc);
3963
3964 intel_set_pipe_timings(intel_crtc);
3965
3966 if (intel_crtc->config.has_pch_encoder) {
3967 intel_cpu_transcoder_set_m_n(intel_crtc,
3968 &intel_crtc->config.fdi_m_n, NULL);
3969 }
3970
3971 ironlake_set_pipeconf(crtc);
3972
3973 intel_crtc->active = true;
3974
3975 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3976 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3977
3978 for_each_encoder_on_crtc(dev, crtc, encoder)
3979 if (encoder->pre_enable)
3980 encoder->pre_enable(encoder);
3981
3982 if (intel_crtc->config.has_pch_encoder) {
3983 /* Note: FDI PLL enabling _must_ be done before we enable the
3984 * cpu pipes, hence this is separate from all the other fdi/pch
3985 * enabling. */
3986 ironlake_fdi_pll_enable(intel_crtc);
3987 } else {
3988 assert_fdi_tx_disabled(dev_priv, pipe);
3989 assert_fdi_rx_disabled(dev_priv, pipe);
3990 }
3991
3992 ironlake_pfit_enable(intel_crtc);
3993
3994 /*
3995 * On ILK+ LUT must be loaded before the pipe is running but with
3996 * clocks enabled
3997 */
3998 intel_crtc_load_lut(crtc);
3999
4000 intel_update_watermarks(crtc);
4001 intel_enable_pipe(intel_crtc);
4002
4003 if (intel_crtc->config.has_pch_encoder)
4004 ironlake_pch_enable(crtc);
4005
4006 for_each_encoder_on_crtc(dev, crtc, encoder)
4007 encoder->enable(encoder);
4008
4009 if (HAS_PCH_CPT(dev))
4010 cpt_verify_modeset(dev, intel_crtc->pipe);
4011
4012 intel_crtc_enable_planes(crtc);
4013 }
4014
4015 /* IPS only exists on ULT machines and is tied to pipe A. */
4016 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4017 {
4018 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4019 }
4020
4021 /*
4022 * This implements the workaround described in the "notes" section of the mode
4023 * set sequence documentation. When going from no pipes or single pipe to
4024 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4025 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4026 */
4027 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4028 {
4029 struct drm_device *dev = crtc->base.dev;
4030 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4031
4032 /* We want to get the other_active_crtc only if there's only 1 other
4033 * active crtc. */
4034 for_each_intel_crtc(dev, crtc_it) {
4035 if (!crtc_it->active || crtc_it == crtc)
4036 continue;
4037
4038 if (other_active_crtc)
4039 return;
4040
4041 other_active_crtc = crtc_it;
4042 }
4043 if (!other_active_crtc)
4044 return;
4045
4046 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4047 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4048 }
4049
4050 static void haswell_crtc_enable(struct drm_crtc *crtc)
4051 {
4052 struct drm_device *dev = crtc->dev;
4053 struct drm_i915_private *dev_priv = dev->dev_private;
4054 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4055 struct intel_encoder *encoder;
4056 int pipe = intel_crtc->pipe;
4057
4058 WARN_ON(!crtc->enabled);
4059
4060 if (intel_crtc->active)
4061 return;
4062
4063 if (intel_crtc_to_shared_dpll(intel_crtc))
4064 intel_enable_shared_dpll(intel_crtc);
4065
4066 if (intel_crtc->config.has_dp_encoder)
4067 intel_dp_set_m_n(intel_crtc);
4068
4069 intel_set_pipe_timings(intel_crtc);
4070
4071 if (intel_crtc->config.has_pch_encoder) {
4072 intel_cpu_transcoder_set_m_n(intel_crtc,
4073 &intel_crtc->config.fdi_m_n, NULL);
4074 }
4075
4076 haswell_set_pipeconf(crtc);
4077
4078 intel_set_pipe_csc(crtc);
4079
4080 intel_crtc->active = true;
4081
4082 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4083 for_each_encoder_on_crtc(dev, crtc, encoder)
4084 if (encoder->pre_enable)
4085 encoder->pre_enable(encoder);
4086
4087 if (intel_crtc->config.has_pch_encoder) {
4088 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4089 dev_priv->display.fdi_link_train(crtc);
4090 }
4091
4092 intel_ddi_enable_pipe_clock(intel_crtc);
4093
4094 ironlake_pfit_enable(intel_crtc);
4095
4096 /*
4097 * On ILK+ LUT must be loaded before the pipe is running but with
4098 * clocks enabled
4099 */
4100 intel_crtc_load_lut(crtc);
4101
4102 intel_ddi_set_pipe_settings(crtc);
4103 intel_ddi_enable_transcoder_func(crtc);
4104
4105 intel_update_watermarks(crtc);
4106 intel_enable_pipe(intel_crtc);
4107
4108 if (intel_crtc->config.has_pch_encoder)
4109 lpt_pch_enable(crtc);
4110
4111 if (intel_crtc->config.dp_encoder_is_mst)
4112 intel_ddi_set_vc_payload_alloc(crtc, true);
4113
4114 for_each_encoder_on_crtc(dev, crtc, encoder) {
4115 encoder->enable(encoder);
4116 intel_opregion_notify_encoder(encoder, true);
4117 }
4118
4119 /* If we change the relative order between pipe/planes enabling, we need
4120 * to change the workaround. */
4121 haswell_mode_set_planes_workaround(intel_crtc);
4122 intel_crtc_enable_planes(crtc);
4123 }
4124
4125 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4126 {
4127 struct drm_device *dev = crtc->base.dev;
4128 struct drm_i915_private *dev_priv = dev->dev_private;
4129 int pipe = crtc->pipe;
4130
4131 /* To avoid upsetting the power well on haswell only disable the pfit if
4132 * it's in use. The hw state code will make sure we get this right. */
4133 if (crtc->config.pch_pfit.enabled) {
4134 I915_WRITE(PF_CTL(pipe), 0);
4135 I915_WRITE(PF_WIN_POS(pipe), 0);
4136 I915_WRITE(PF_WIN_SZ(pipe), 0);
4137 }
4138 }
4139
4140 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4141 {
4142 struct drm_device *dev = crtc->dev;
4143 struct drm_i915_private *dev_priv = dev->dev_private;
4144 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4145 struct intel_encoder *encoder;
4146 int pipe = intel_crtc->pipe;
4147 u32 reg, temp;
4148
4149 if (!intel_crtc->active)
4150 return;
4151
4152 intel_crtc_disable_planes(crtc);
4153
4154 for_each_encoder_on_crtc(dev, crtc, encoder)
4155 encoder->disable(encoder);
4156
4157 if (intel_crtc->config.has_pch_encoder)
4158 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
4159
4160 intel_disable_pipe(dev_priv, pipe);
4161
4162 if (intel_crtc->config.dp_encoder_is_mst)
4163 intel_ddi_set_vc_payload_alloc(crtc, false);
4164
4165 ironlake_pfit_disable(intel_crtc);
4166
4167 for_each_encoder_on_crtc(dev, crtc, encoder)
4168 if (encoder->post_disable)
4169 encoder->post_disable(encoder);
4170
4171 if (intel_crtc->config.has_pch_encoder) {
4172 ironlake_fdi_disable(crtc);
4173
4174 ironlake_disable_pch_transcoder(dev_priv, pipe);
4175 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4176
4177 if (HAS_PCH_CPT(dev)) {
4178 /* disable TRANS_DP_CTL */
4179 reg = TRANS_DP_CTL(pipe);
4180 temp = I915_READ(reg);
4181 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4182 TRANS_DP_PORT_SEL_MASK);
4183 temp |= TRANS_DP_PORT_SEL_NONE;
4184 I915_WRITE(reg, temp);
4185
4186 /* disable DPLL_SEL */
4187 temp = I915_READ(PCH_DPLL_SEL);
4188 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4189 I915_WRITE(PCH_DPLL_SEL, temp);
4190 }
4191
4192 /* disable PCH DPLL */
4193 intel_disable_shared_dpll(intel_crtc);
4194
4195 ironlake_fdi_pll_disable(intel_crtc);
4196 }
4197
4198 intel_crtc->active = false;
4199 intel_update_watermarks(crtc);
4200
4201 mutex_lock(&dev->struct_mutex);
4202 intel_update_fbc(dev);
4203 mutex_unlock(&dev->struct_mutex);
4204 }
4205
4206 static void haswell_crtc_disable(struct drm_crtc *crtc)
4207 {
4208 struct drm_device *dev = crtc->dev;
4209 struct drm_i915_private *dev_priv = dev->dev_private;
4210 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4211 struct intel_encoder *encoder;
4212 int pipe = intel_crtc->pipe;
4213 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4214
4215 if (!intel_crtc->active)
4216 return;
4217
4218 intel_crtc_disable_planes(crtc);
4219
4220 for_each_encoder_on_crtc(dev, crtc, encoder) {
4221 intel_opregion_notify_encoder(encoder, false);
4222 encoder->disable(encoder);
4223 }
4224
4225 if (intel_crtc->config.has_pch_encoder)
4226 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4227 intel_disable_pipe(dev_priv, pipe);
4228
4229 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4230
4231 ironlake_pfit_disable(intel_crtc);
4232
4233 intel_ddi_disable_pipe_clock(intel_crtc);
4234
4235 if (intel_crtc->config.has_pch_encoder) {
4236 lpt_disable_pch_transcoder(dev_priv);
4237 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4238 intel_ddi_fdi_disable(crtc);
4239 }
4240
4241 for_each_encoder_on_crtc(dev, crtc, encoder)
4242 if (encoder->post_disable)
4243 encoder->post_disable(encoder);
4244
4245 intel_crtc->active = false;
4246 intel_update_watermarks(crtc);
4247
4248 mutex_lock(&dev->struct_mutex);
4249 intel_update_fbc(dev);
4250 mutex_unlock(&dev->struct_mutex);
4251
4252 if (intel_crtc_to_shared_dpll(intel_crtc))
4253 intel_disable_shared_dpll(intel_crtc);
4254 }
4255
4256 static void ironlake_crtc_off(struct drm_crtc *crtc)
4257 {
4258 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4259 intel_put_shared_dpll(intel_crtc);
4260 }
4261
4262
4263 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4264 {
4265 struct drm_device *dev = crtc->base.dev;
4266 struct drm_i915_private *dev_priv = dev->dev_private;
4267 struct intel_crtc_config *pipe_config = &crtc->config;
4268
4269 if (!crtc->config.gmch_pfit.control)
4270 return;
4271
4272 /*
4273 * The panel fitter should only be adjusted whilst the pipe is disabled,
4274 * according to register description and PRM.
4275 */
4276 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4277 assert_pipe_disabled(dev_priv, crtc->pipe);
4278
4279 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4280 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4281
4282 /* Border color in case we don't scale up to the full screen. Black by
4283 * default, change to something else for debugging. */
4284 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4285 }
4286
4287 static enum intel_display_power_domain port_to_power_domain(enum port port)
4288 {
4289 switch (port) {
4290 case PORT_A:
4291 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4292 case PORT_B:
4293 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4294 case PORT_C:
4295 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4296 case PORT_D:
4297 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4298 default:
4299 WARN_ON_ONCE(1);
4300 return POWER_DOMAIN_PORT_OTHER;
4301 }
4302 }
4303
4304 #define for_each_power_domain(domain, mask) \
4305 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4306 if ((1 << (domain)) & (mask))
4307
4308 enum intel_display_power_domain
4309 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4310 {
4311 struct drm_device *dev = intel_encoder->base.dev;
4312 struct intel_digital_port *intel_dig_port;
4313
4314 switch (intel_encoder->type) {
4315 case INTEL_OUTPUT_UNKNOWN:
4316 /* Only DDI platforms should ever use this output type */
4317 WARN_ON_ONCE(!HAS_DDI(dev));
4318 case INTEL_OUTPUT_DISPLAYPORT:
4319 case INTEL_OUTPUT_HDMI:
4320 case INTEL_OUTPUT_EDP:
4321 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4322 return port_to_power_domain(intel_dig_port->port);
4323 case INTEL_OUTPUT_DP_MST:
4324 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4325 return port_to_power_domain(intel_dig_port->port);
4326 case INTEL_OUTPUT_ANALOG:
4327 return POWER_DOMAIN_PORT_CRT;
4328 case INTEL_OUTPUT_DSI:
4329 return POWER_DOMAIN_PORT_DSI;
4330 default:
4331 return POWER_DOMAIN_PORT_OTHER;
4332 }
4333 }
4334
4335 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4336 {
4337 struct drm_device *dev = crtc->dev;
4338 struct intel_encoder *intel_encoder;
4339 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4340 enum pipe pipe = intel_crtc->pipe;
4341 unsigned long mask;
4342 enum transcoder transcoder;
4343
4344 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4345
4346 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4347 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4348 if (intel_crtc->config.pch_pfit.enabled ||
4349 intel_crtc->config.pch_pfit.force_thru)
4350 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4351
4352 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4353 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4354
4355 return mask;
4356 }
4357
4358 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4359 bool enable)
4360 {
4361 if (dev_priv->power_domains.init_power_on == enable)
4362 return;
4363
4364 if (enable)
4365 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4366 else
4367 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4368
4369 dev_priv->power_domains.init_power_on = enable;
4370 }
4371
4372 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4373 {
4374 struct drm_i915_private *dev_priv = dev->dev_private;
4375 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4376 struct intel_crtc *crtc;
4377
4378 /*
4379 * First get all needed power domains, then put all unneeded, to avoid
4380 * any unnecessary toggling of the power wells.
4381 */
4382 for_each_intel_crtc(dev, crtc) {
4383 enum intel_display_power_domain domain;
4384
4385 if (!crtc->base.enabled)
4386 continue;
4387
4388 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4389
4390 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4391 intel_display_power_get(dev_priv, domain);
4392 }
4393
4394 for_each_intel_crtc(dev, crtc) {
4395 enum intel_display_power_domain domain;
4396
4397 for_each_power_domain(domain, crtc->enabled_power_domains)
4398 intel_display_power_put(dev_priv, domain);
4399
4400 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4401 }
4402
4403 intel_display_set_init_power(dev_priv, false);
4404 }
4405
4406 /* returns HPLL frequency in kHz */
4407 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4408 {
4409 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4410
4411 /* Obtain SKU information */
4412 mutex_lock(&dev_priv->dpio_lock);
4413 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4414 CCK_FUSE_HPLL_FREQ_MASK;
4415 mutex_unlock(&dev_priv->dpio_lock);
4416
4417 return vco_freq[hpll_freq] * 1000;
4418 }
4419
4420 static void vlv_update_cdclk(struct drm_device *dev)
4421 {
4422 struct drm_i915_private *dev_priv = dev->dev_private;
4423
4424 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4425 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz",
4426 dev_priv->vlv_cdclk_freq);
4427
4428 /*
4429 * Program the gmbus_freq based on the cdclk frequency.
4430 * BSpec erroneously claims we should aim for 4MHz, but
4431 * in fact 1MHz is the correct frequency.
4432 */
4433 I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq);
4434 }
4435
4436 /* Adjust CDclk dividers to allow high res or save power if possible */
4437 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4438 {
4439 struct drm_i915_private *dev_priv = dev->dev_private;
4440 u32 val, cmd;
4441
4442 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4443
4444 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4445 cmd = 2;
4446 else if (cdclk == 266667)
4447 cmd = 1;
4448 else
4449 cmd = 0;
4450
4451 mutex_lock(&dev_priv->rps.hw_lock);
4452 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4453 val &= ~DSPFREQGUAR_MASK;
4454 val |= (cmd << DSPFREQGUAR_SHIFT);
4455 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4456 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4457 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4458 50)) {
4459 DRM_ERROR("timed out waiting for CDclk change\n");
4460 }
4461 mutex_unlock(&dev_priv->rps.hw_lock);
4462
4463 if (cdclk == 400000) {
4464 u32 divider, vco;
4465
4466 vco = valleyview_get_vco(dev_priv);
4467 divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1;
4468
4469 mutex_lock(&dev_priv->dpio_lock);
4470 /* adjust cdclk divider */
4471 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4472 val &= ~DISPLAY_FREQUENCY_VALUES;
4473 val |= divider;
4474 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4475
4476 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4477 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4478 50))
4479 DRM_ERROR("timed out waiting for CDclk change\n");
4480 mutex_unlock(&dev_priv->dpio_lock);
4481 }
4482
4483 mutex_lock(&dev_priv->dpio_lock);
4484 /* adjust self-refresh exit latency value */
4485 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4486 val &= ~0x7f;
4487
4488 /*
4489 * For high bandwidth configs, we set a higher latency in the bunit
4490 * so that the core display fetch happens in time to avoid underruns.
4491 */
4492 if (cdclk == 400000)
4493 val |= 4500 / 250; /* 4.5 usec */
4494 else
4495 val |= 3000 / 250; /* 3.0 usec */
4496 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4497 mutex_unlock(&dev_priv->dpio_lock);
4498
4499 vlv_update_cdclk(dev);
4500 }
4501
4502 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4503 {
4504 struct drm_i915_private *dev_priv = dev->dev_private;
4505 u32 val, cmd;
4506
4507 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4508
4509 switch (cdclk) {
4510 case 400000:
4511 cmd = 3;
4512 break;
4513 case 333333:
4514 case 320000:
4515 cmd = 2;
4516 break;
4517 case 266667:
4518 cmd = 1;
4519 break;
4520 case 200000:
4521 cmd = 0;
4522 break;
4523 default:
4524 WARN_ON(1);
4525 return;
4526 }
4527
4528 mutex_lock(&dev_priv->rps.hw_lock);
4529 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4530 val &= ~DSPFREQGUAR_MASK_CHV;
4531 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4532 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4533 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4534 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4535 50)) {
4536 DRM_ERROR("timed out waiting for CDclk change\n");
4537 }
4538 mutex_unlock(&dev_priv->rps.hw_lock);
4539
4540 vlv_update_cdclk(dev);
4541 }
4542
4543 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4544 int max_pixclk)
4545 {
4546 int vco = valleyview_get_vco(dev_priv);
4547 int freq_320 = (vco << 1) % 320000 != 0 ? 333333 : 320000;
4548
4549 /* FIXME: Punit isn't quite ready yet */
4550 if (IS_CHERRYVIEW(dev_priv->dev))
4551 return 400000;
4552
4553 /*
4554 * Really only a few cases to deal with, as only 4 CDclks are supported:
4555 * 200MHz
4556 * 267MHz
4557 * 320/333MHz (depends on HPLL freq)
4558 * 400MHz
4559 * So we check to see whether we're above 90% of the lower bin and
4560 * adjust if needed.
4561 *
4562 * We seem to get an unstable or solid color picture at 200MHz.
4563 * Not sure what's wrong. For now use 200MHz only when all pipes
4564 * are off.
4565 */
4566 if (max_pixclk > freq_320*9/10)
4567 return 400000;
4568 else if (max_pixclk > 266667*9/10)
4569 return freq_320;
4570 else if (max_pixclk > 0)
4571 return 266667;
4572 else
4573 return 200000;
4574 }
4575
4576 /* compute the max pixel clock for new configuration */
4577 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4578 {
4579 struct drm_device *dev = dev_priv->dev;
4580 struct intel_crtc *intel_crtc;
4581 int max_pixclk = 0;
4582
4583 for_each_intel_crtc(dev, intel_crtc) {
4584 if (intel_crtc->new_enabled)
4585 max_pixclk = max(max_pixclk,
4586 intel_crtc->new_config->adjusted_mode.crtc_clock);
4587 }
4588
4589 return max_pixclk;
4590 }
4591
4592 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4593 unsigned *prepare_pipes)
4594 {
4595 struct drm_i915_private *dev_priv = dev->dev_private;
4596 struct intel_crtc *intel_crtc;
4597 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4598
4599 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4600 dev_priv->vlv_cdclk_freq)
4601 return;
4602
4603 /* disable/enable all currently active pipes while we change cdclk */
4604 for_each_intel_crtc(dev, intel_crtc)
4605 if (intel_crtc->base.enabled)
4606 *prepare_pipes |= (1 << intel_crtc->pipe);
4607 }
4608
4609 static void valleyview_modeset_global_resources(struct drm_device *dev)
4610 {
4611 struct drm_i915_private *dev_priv = dev->dev_private;
4612 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4613 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4614
4615 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
4616 if (IS_CHERRYVIEW(dev))
4617 cherryview_set_cdclk(dev, req_cdclk);
4618 else
4619 valleyview_set_cdclk(dev, req_cdclk);
4620 }
4621
4622 modeset_update_crtc_power_domains(dev);
4623 }
4624
4625 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4626 {
4627 struct drm_device *dev = crtc->dev;
4628 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4629 struct intel_encoder *encoder;
4630 int pipe = intel_crtc->pipe;
4631 bool is_dsi;
4632
4633 WARN_ON(!crtc->enabled);
4634
4635 if (intel_crtc->active)
4636 return;
4637
4638 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4639
4640 if (!is_dsi) {
4641 if (IS_CHERRYVIEW(dev))
4642 chv_prepare_pll(intel_crtc);
4643 else
4644 vlv_prepare_pll(intel_crtc);
4645 }
4646
4647 if (intel_crtc->config.has_dp_encoder)
4648 intel_dp_set_m_n(intel_crtc);
4649
4650 intel_set_pipe_timings(intel_crtc);
4651
4652 i9xx_set_pipeconf(intel_crtc);
4653
4654 intel_crtc->active = true;
4655
4656 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4657
4658 for_each_encoder_on_crtc(dev, crtc, encoder)
4659 if (encoder->pre_pll_enable)
4660 encoder->pre_pll_enable(encoder);
4661
4662 if (!is_dsi) {
4663 if (IS_CHERRYVIEW(dev))
4664 chv_enable_pll(intel_crtc);
4665 else
4666 vlv_enable_pll(intel_crtc);
4667 }
4668
4669 for_each_encoder_on_crtc(dev, crtc, encoder)
4670 if (encoder->pre_enable)
4671 encoder->pre_enable(encoder);
4672
4673 i9xx_pfit_enable(intel_crtc);
4674
4675 intel_crtc_load_lut(crtc);
4676
4677 intel_update_watermarks(crtc);
4678 intel_enable_pipe(intel_crtc);
4679
4680 for_each_encoder_on_crtc(dev, crtc, encoder)
4681 encoder->enable(encoder);
4682
4683 intel_crtc_enable_planes(crtc);
4684
4685 /* Underruns don't raise interrupts, so check manually. */
4686 i9xx_check_fifo_underruns(dev);
4687 }
4688
4689 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4690 {
4691 struct drm_device *dev = crtc->base.dev;
4692 struct drm_i915_private *dev_priv = dev->dev_private;
4693
4694 I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4695 I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4696 }
4697
4698 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4699 {
4700 struct drm_device *dev = crtc->dev;
4701 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4702 struct intel_encoder *encoder;
4703 int pipe = intel_crtc->pipe;
4704
4705 WARN_ON(!crtc->enabled);
4706
4707 if (intel_crtc->active)
4708 return;
4709
4710 i9xx_set_pll_dividers(intel_crtc);
4711
4712 if (intel_crtc->config.has_dp_encoder)
4713 intel_dp_set_m_n(intel_crtc);
4714
4715 intel_set_pipe_timings(intel_crtc);
4716
4717 i9xx_set_pipeconf(intel_crtc);
4718
4719 intel_crtc->active = true;
4720
4721 if (!IS_GEN2(dev))
4722 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4723
4724 for_each_encoder_on_crtc(dev, crtc, encoder)
4725 if (encoder->pre_enable)
4726 encoder->pre_enable(encoder);
4727
4728 i9xx_enable_pll(intel_crtc);
4729
4730 i9xx_pfit_enable(intel_crtc);
4731
4732 intel_crtc_load_lut(crtc);
4733
4734 intel_update_watermarks(crtc);
4735 intel_enable_pipe(intel_crtc);
4736
4737 for_each_encoder_on_crtc(dev, crtc, encoder)
4738 encoder->enable(encoder);
4739
4740 intel_crtc_enable_planes(crtc);
4741
4742 /*
4743 * Gen2 reports pipe underruns whenever all planes are disabled.
4744 * So don't enable underrun reporting before at least some planes
4745 * are enabled.
4746 * FIXME: Need to fix the logic to work when we turn off all planes
4747 * but leave the pipe running.
4748 */
4749 if (IS_GEN2(dev))
4750 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4751
4752 /* Underruns don't raise interrupts, so check manually. */
4753 i9xx_check_fifo_underruns(dev);
4754 }
4755
4756 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4757 {
4758 struct drm_device *dev = crtc->base.dev;
4759 struct drm_i915_private *dev_priv = dev->dev_private;
4760
4761 if (!crtc->config.gmch_pfit.control)
4762 return;
4763
4764 assert_pipe_disabled(dev_priv, crtc->pipe);
4765
4766 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4767 I915_READ(PFIT_CONTROL));
4768 I915_WRITE(PFIT_CONTROL, 0);
4769 }
4770
4771 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4772 {
4773 struct drm_device *dev = crtc->dev;
4774 struct drm_i915_private *dev_priv = dev->dev_private;
4775 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4776 struct intel_encoder *encoder;
4777 int pipe = intel_crtc->pipe;
4778
4779 if (!intel_crtc->active)
4780 return;
4781
4782 /*
4783 * Gen2 reports pipe underruns whenever all planes are disabled.
4784 * So diasble underrun reporting before all the planes get disabled.
4785 * FIXME: Need to fix the logic to work when we turn off all planes
4786 * but leave the pipe running.
4787 */
4788 if (IS_GEN2(dev))
4789 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4790
4791 /*
4792 * Vblank time updates from the shadow to live plane control register
4793 * are blocked if the memory self-refresh mode is active at that
4794 * moment. So to make sure the plane gets truly disabled, disable
4795 * first the self-refresh mode. The self-refresh enable bit in turn
4796 * will be checked/applied by the HW only at the next frame start
4797 * event which is after the vblank start event, so we need to have a
4798 * wait-for-vblank between disabling the plane and the pipe.
4799 */
4800 intel_set_memory_cxsr(dev_priv, false);
4801 intel_crtc_disable_planes(crtc);
4802
4803 for_each_encoder_on_crtc(dev, crtc, encoder)
4804 encoder->disable(encoder);
4805
4806 /*
4807 * On gen2 planes are double buffered but the pipe isn't, so we must
4808 * wait for planes to fully turn off before disabling the pipe.
4809 * We also need to wait on all gmch platforms because of the
4810 * self-refresh mode constraint explained above.
4811 */
4812 intel_wait_for_vblank(dev, pipe);
4813
4814 intel_disable_pipe(dev_priv, pipe);
4815
4816 i9xx_pfit_disable(intel_crtc);
4817
4818 for_each_encoder_on_crtc(dev, crtc, encoder)
4819 if (encoder->post_disable)
4820 encoder->post_disable(encoder);
4821
4822 if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
4823 if (IS_CHERRYVIEW(dev))
4824 chv_disable_pll(dev_priv, pipe);
4825 else if (IS_VALLEYVIEW(dev))
4826 vlv_disable_pll(dev_priv, pipe);
4827 else
4828 i9xx_disable_pll(dev_priv, pipe);
4829 }
4830
4831 if (!IS_GEN2(dev))
4832 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4833
4834 intel_crtc->active = false;
4835 intel_update_watermarks(crtc);
4836
4837 mutex_lock(&dev->struct_mutex);
4838 intel_update_fbc(dev);
4839 mutex_unlock(&dev->struct_mutex);
4840 }
4841
4842 static void i9xx_crtc_off(struct drm_crtc *crtc)
4843 {
4844 }
4845
4846 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4847 bool enabled)
4848 {
4849 struct drm_device *dev = crtc->dev;
4850 struct drm_i915_master_private *master_priv;
4851 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4852 int pipe = intel_crtc->pipe;
4853
4854 if (!dev->primary->master)
4855 return;
4856
4857 master_priv = dev->primary->master->driver_priv;
4858 if (!master_priv->sarea_priv)
4859 return;
4860
4861 switch (pipe) {
4862 case 0:
4863 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4864 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4865 break;
4866 case 1:
4867 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4868 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4869 break;
4870 default:
4871 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4872 break;
4873 }
4874 }
4875
4876 /* Master function to enable/disable CRTC and corresponding power wells */
4877 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
4878 {
4879 struct drm_device *dev = crtc->dev;
4880 struct drm_i915_private *dev_priv = dev->dev_private;
4881 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4882 enum intel_display_power_domain domain;
4883 unsigned long domains;
4884
4885 if (enable) {
4886 if (!intel_crtc->active) {
4887 domains = get_crtc_power_domains(crtc);
4888 for_each_power_domain(domain, domains)
4889 intel_display_power_get(dev_priv, domain);
4890 intel_crtc->enabled_power_domains = domains;
4891
4892 dev_priv->display.crtc_enable(crtc);
4893 }
4894 } else {
4895 if (intel_crtc->active) {
4896 dev_priv->display.crtc_disable(crtc);
4897
4898 domains = intel_crtc->enabled_power_domains;
4899 for_each_power_domain(domain, domains)
4900 intel_display_power_put(dev_priv, domain);
4901 intel_crtc->enabled_power_domains = 0;
4902 }
4903 }
4904 }
4905
4906 /**
4907 * Sets the power management mode of the pipe and plane.
4908 */
4909 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4910 {
4911 struct drm_device *dev = crtc->dev;
4912 struct intel_encoder *intel_encoder;
4913 bool enable = false;
4914
4915 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4916 enable |= intel_encoder->connectors_active;
4917
4918 intel_crtc_control(crtc, enable);
4919
4920 intel_crtc_update_sarea(crtc, enable);
4921 }
4922
4923 static void intel_crtc_disable(struct drm_crtc *crtc)
4924 {
4925 struct drm_device *dev = crtc->dev;
4926 struct drm_connector *connector;
4927 struct drm_i915_private *dev_priv = dev->dev_private;
4928 struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
4929 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4930
4931 /* crtc should still be enabled when we disable it. */
4932 WARN_ON(!crtc->enabled);
4933
4934 dev_priv->display.crtc_disable(crtc);
4935 intel_crtc_update_sarea(crtc, false);
4936 dev_priv->display.off(crtc);
4937
4938 if (crtc->primary->fb) {
4939 mutex_lock(&dev->struct_mutex);
4940 intel_unpin_fb_obj(old_obj);
4941 i915_gem_track_fb(old_obj, NULL,
4942 INTEL_FRONTBUFFER_PRIMARY(pipe));
4943 mutex_unlock(&dev->struct_mutex);
4944 crtc->primary->fb = NULL;
4945 }
4946
4947 /* Update computed state. */
4948 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4949 if (!connector->encoder || !connector->encoder->crtc)
4950 continue;
4951
4952 if (connector->encoder->crtc != crtc)
4953 continue;
4954
4955 connector->dpms = DRM_MODE_DPMS_OFF;
4956 to_intel_encoder(connector->encoder)->connectors_active = false;
4957 }
4958 }
4959
4960 void intel_encoder_destroy(struct drm_encoder *encoder)
4961 {
4962 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4963
4964 drm_encoder_cleanup(encoder);
4965 kfree(intel_encoder);
4966 }
4967
4968 /* Simple dpms helper for encoders with just one connector, no cloning and only
4969 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4970 * state of the entire output pipe. */
4971 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4972 {
4973 if (mode == DRM_MODE_DPMS_ON) {
4974 encoder->connectors_active = true;
4975
4976 intel_crtc_update_dpms(encoder->base.crtc);
4977 } else {
4978 encoder->connectors_active = false;
4979
4980 intel_crtc_update_dpms(encoder->base.crtc);
4981 }
4982 }
4983
4984 /* Cross check the actual hw state with our own modeset state tracking (and it's
4985 * internal consistency). */
4986 static void intel_connector_check_state(struct intel_connector *connector)
4987 {
4988 if (connector->get_hw_state(connector)) {
4989 struct intel_encoder *encoder = connector->encoder;
4990 struct drm_crtc *crtc;
4991 bool encoder_enabled;
4992 enum pipe pipe;
4993
4994 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4995 connector->base.base.id,
4996 connector->base.name);
4997
4998 /* there is no real hw state for MST connectors */
4999 if (connector->mst_port)
5000 return;
5001
5002 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5003 "wrong connector dpms state\n");
5004 WARN(connector->base.encoder != &encoder->base,
5005 "active connector not linked to encoder\n");
5006
5007 if (encoder) {
5008 WARN(!encoder->connectors_active,
5009 "encoder->connectors_active not set\n");
5010
5011 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5012 WARN(!encoder_enabled, "encoder not enabled\n");
5013 if (WARN_ON(!encoder->base.crtc))
5014 return;
5015
5016 crtc = encoder->base.crtc;
5017
5018 WARN(!crtc->enabled, "crtc not enabled\n");
5019 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5020 WARN(pipe != to_intel_crtc(crtc)->pipe,
5021 "encoder active on the wrong pipe\n");
5022 }
5023 }
5024 }
5025
5026 /* Even simpler default implementation, if there's really no special case to
5027 * consider. */
5028 void intel_connector_dpms(struct drm_connector *connector, int mode)
5029 {
5030 /* All the simple cases only support two dpms states. */
5031 if (mode != DRM_MODE_DPMS_ON)
5032 mode = DRM_MODE_DPMS_OFF;
5033
5034 if (mode == connector->dpms)
5035 return;
5036
5037 connector->dpms = mode;
5038
5039 /* Only need to change hw state when actually enabled */
5040 if (connector->encoder)
5041 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5042
5043 intel_modeset_check_state(connector->dev);
5044 }
5045
5046 /* Simple connector->get_hw_state implementation for encoders that support only
5047 * one connector and no cloning and hence the encoder state determines the state
5048 * of the connector. */
5049 bool intel_connector_get_hw_state(struct intel_connector *connector)
5050 {
5051 enum pipe pipe = 0;
5052 struct intel_encoder *encoder = connector->encoder;
5053
5054 return encoder->get_hw_state(encoder, &pipe);
5055 }
5056
5057 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5058 struct intel_crtc_config *pipe_config)
5059 {
5060 struct drm_i915_private *dev_priv = dev->dev_private;
5061 struct intel_crtc *pipe_B_crtc =
5062 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5063
5064 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5065 pipe_name(pipe), pipe_config->fdi_lanes);
5066 if (pipe_config->fdi_lanes > 4) {
5067 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5068 pipe_name(pipe), pipe_config->fdi_lanes);
5069 return false;
5070 }
5071
5072 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5073 if (pipe_config->fdi_lanes > 2) {
5074 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5075 pipe_config->fdi_lanes);
5076 return false;
5077 } else {
5078 return true;
5079 }
5080 }
5081
5082 if (INTEL_INFO(dev)->num_pipes == 2)
5083 return true;
5084
5085 /* Ivybridge 3 pipe is really complicated */
5086 switch (pipe) {
5087 case PIPE_A:
5088 return true;
5089 case PIPE_B:
5090 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5091 pipe_config->fdi_lanes > 2) {
5092 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5093 pipe_name(pipe), pipe_config->fdi_lanes);
5094 return false;
5095 }
5096 return true;
5097 case PIPE_C:
5098 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5099 pipe_B_crtc->config.fdi_lanes <= 2) {
5100 if (pipe_config->fdi_lanes > 2) {
5101 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5102 pipe_name(pipe), pipe_config->fdi_lanes);
5103 return false;
5104 }
5105 } else {
5106 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5107 return false;
5108 }
5109 return true;
5110 default:
5111 BUG();
5112 }
5113 }
5114
5115 #define RETRY 1
5116 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5117 struct intel_crtc_config *pipe_config)
5118 {
5119 struct drm_device *dev = intel_crtc->base.dev;
5120 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5121 int lane, link_bw, fdi_dotclock;
5122 bool setup_ok, needs_recompute = false;
5123
5124 retry:
5125 /* FDI is a binary signal running at ~2.7GHz, encoding
5126 * each output octet as 10 bits. The actual frequency
5127 * is stored as a divider into a 100MHz clock, and the
5128 * mode pixel clock is stored in units of 1KHz.
5129 * Hence the bw of each lane in terms of the mode signal
5130 * is:
5131 */
5132 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5133
5134 fdi_dotclock = adjusted_mode->crtc_clock;
5135
5136 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5137 pipe_config->pipe_bpp);
5138
5139 pipe_config->fdi_lanes = lane;
5140
5141 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5142 link_bw, &pipe_config->fdi_m_n);
5143
5144 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5145 intel_crtc->pipe, pipe_config);
5146 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5147 pipe_config->pipe_bpp -= 2*3;
5148 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5149 pipe_config->pipe_bpp);
5150 needs_recompute = true;
5151 pipe_config->bw_constrained = true;
5152
5153 goto retry;
5154 }
5155
5156 if (needs_recompute)
5157 return RETRY;
5158
5159 return setup_ok ? 0 : -EINVAL;
5160 }
5161
5162 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5163 struct intel_crtc_config *pipe_config)
5164 {
5165 pipe_config->ips_enabled = i915.enable_ips &&
5166 hsw_crtc_supports_ips(crtc) &&
5167 pipe_config->pipe_bpp <= 24;
5168 }
5169
5170 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5171 struct intel_crtc_config *pipe_config)
5172 {
5173 struct drm_device *dev = crtc->base.dev;
5174 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5175
5176 /* FIXME should check pixel clock limits on all platforms */
5177 if (INTEL_INFO(dev)->gen < 4) {
5178 struct drm_i915_private *dev_priv = dev->dev_private;
5179 int clock_limit =
5180 dev_priv->display.get_display_clock_speed(dev);
5181
5182 /*
5183 * Enable pixel doubling when the dot clock
5184 * is > 90% of the (display) core speed.
5185 *
5186 * GDG double wide on either pipe,
5187 * otherwise pipe A only.
5188 */
5189 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5190 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5191 clock_limit *= 2;
5192 pipe_config->double_wide = true;
5193 }
5194
5195 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5196 return -EINVAL;
5197 }
5198
5199 /*
5200 * Pipe horizontal size must be even in:
5201 * - DVO ganged mode
5202 * - LVDS dual channel mode
5203 * - Double wide pipe
5204 */
5205 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5206 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5207 pipe_config->pipe_src_w &= ~1;
5208
5209 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5210 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5211 */
5212 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5213 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5214 return -EINVAL;
5215
5216 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5217 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5218 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5219 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5220 * for lvds. */
5221 pipe_config->pipe_bpp = 8*3;
5222 }
5223
5224 if (HAS_IPS(dev))
5225 hsw_compute_ips_config(crtc, pipe_config);
5226
5227 /*
5228 * XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the
5229 * old clock survives for now.
5230 */
5231 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev) || HAS_DDI(dev))
5232 pipe_config->shared_dpll = crtc->config.shared_dpll;
5233
5234 if (pipe_config->has_pch_encoder)
5235 return ironlake_fdi_compute_config(crtc, pipe_config);
5236
5237 return 0;
5238 }
5239
5240 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5241 {
5242 struct drm_i915_private *dev_priv = dev->dev_private;
5243 int vco = valleyview_get_vco(dev_priv);
5244 u32 val;
5245 int divider;
5246
5247 /* FIXME: Punit isn't quite ready yet */
5248 if (IS_CHERRYVIEW(dev))
5249 return 400000;
5250
5251 mutex_lock(&dev_priv->dpio_lock);
5252 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5253 mutex_unlock(&dev_priv->dpio_lock);
5254
5255 divider = val & DISPLAY_FREQUENCY_VALUES;
5256
5257 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5258 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5259 "cdclk change in progress\n");
5260
5261 return DIV_ROUND_CLOSEST(vco << 1, divider + 1);
5262 }
5263
5264 static int i945_get_display_clock_speed(struct drm_device *dev)
5265 {
5266 return 400000;
5267 }
5268
5269 static int i915_get_display_clock_speed(struct drm_device *dev)
5270 {
5271 return 333000;
5272 }
5273
5274 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5275 {
5276 return 200000;
5277 }
5278
5279 static int pnv_get_display_clock_speed(struct drm_device *dev)
5280 {
5281 u16 gcfgc = 0;
5282
5283 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5284
5285 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5286 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5287 return 267000;
5288 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5289 return 333000;
5290 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5291 return 444000;
5292 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5293 return 200000;
5294 default:
5295 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5296 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5297 return 133000;
5298 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5299 return 167000;
5300 }
5301 }
5302
5303 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5304 {
5305 u16 gcfgc = 0;
5306
5307 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5308
5309 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5310 return 133000;
5311 else {
5312 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5313 case GC_DISPLAY_CLOCK_333_MHZ:
5314 return 333000;
5315 default:
5316 case GC_DISPLAY_CLOCK_190_200_MHZ:
5317 return 190000;
5318 }
5319 }
5320 }
5321
5322 static int i865_get_display_clock_speed(struct drm_device *dev)
5323 {
5324 return 266000;
5325 }
5326
5327 static int i855_get_display_clock_speed(struct drm_device *dev)
5328 {
5329 u16 hpllcc = 0;
5330 /* Assume that the hardware is in the high speed state. This
5331 * should be the default.
5332 */
5333 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5334 case GC_CLOCK_133_200:
5335 case GC_CLOCK_100_200:
5336 return 200000;
5337 case GC_CLOCK_166_250:
5338 return 250000;
5339 case GC_CLOCK_100_133:
5340 return 133000;
5341 }
5342
5343 /* Shouldn't happen */
5344 return 0;
5345 }
5346
5347 static int i830_get_display_clock_speed(struct drm_device *dev)
5348 {
5349 return 133000;
5350 }
5351
5352 static void
5353 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5354 {
5355 while (*num > DATA_LINK_M_N_MASK ||
5356 *den > DATA_LINK_M_N_MASK) {
5357 *num >>= 1;
5358 *den >>= 1;
5359 }
5360 }
5361
5362 static void compute_m_n(unsigned int m, unsigned int n,
5363 uint32_t *ret_m, uint32_t *ret_n)
5364 {
5365 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5366 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5367 intel_reduce_m_n_ratio(ret_m, ret_n);
5368 }
5369
5370 void
5371 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5372 int pixel_clock, int link_clock,
5373 struct intel_link_m_n *m_n)
5374 {
5375 m_n->tu = 64;
5376
5377 compute_m_n(bits_per_pixel * pixel_clock,
5378 link_clock * nlanes * 8,
5379 &m_n->gmch_m, &m_n->gmch_n);
5380
5381 compute_m_n(pixel_clock, link_clock,
5382 &m_n->link_m, &m_n->link_n);
5383 }
5384
5385 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5386 {
5387 if (i915.panel_use_ssc >= 0)
5388 return i915.panel_use_ssc != 0;
5389 return dev_priv->vbt.lvds_use_ssc
5390 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5391 }
5392
5393 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5394 {
5395 struct drm_device *dev = crtc->dev;
5396 struct drm_i915_private *dev_priv = dev->dev_private;
5397 int refclk;
5398
5399 if (IS_VALLEYVIEW(dev)) {
5400 refclk = 100000;
5401 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5402 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5403 refclk = dev_priv->vbt.lvds_ssc_freq;
5404 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5405 } else if (!IS_GEN2(dev)) {
5406 refclk = 96000;
5407 } else {
5408 refclk = 48000;
5409 }
5410
5411 return refclk;
5412 }
5413
5414 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5415 {
5416 return (1 << dpll->n) << 16 | dpll->m2;
5417 }
5418
5419 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5420 {
5421 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5422 }
5423
5424 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5425 intel_clock_t *reduced_clock)
5426 {
5427 struct drm_device *dev = crtc->base.dev;
5428 u32 fp, fp2 = 0;
5429
5430 if (IS_PINEVIEW(dev)) {
5431 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5432 if (reduced_clock)
5433 fp2 = pnv_dpll_compute_fp(reduced_clock);
5434 } else {
5435 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5436 if (reduced_clock)
5437 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5438 }
5439
5440 crtc->config.dpll_hw_state.fp0 = fp;
5441
5442 crtc->lowfreq_avail = false;
5443 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5444 reduced_clock && i915.powersave) {
5445 crtc->config.dpll_hw_state.fp1 = fp2;
5446 crtc->lowfreq_avail = true;
5447 } else {
5448 crtc->config.dpll_hw_state.fp1 = fp;
5449 }
5450 }
5451
5452 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5453 pipe)
5454 {
5455 u32 reg_val;
5456
5457 /*
5458 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5459 * and set it to a reasonable value instead.
5460 */
5461 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5462 reg_val &= 0xffffff00;
5463 reg_val |= 0x00000030;
5464 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5465
5466 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5467 reg_val &= 0x8cffffff;
5468 reg_val = 0x8c000000;
5469 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5470
5471 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5472 reg_val &= 0xffffff00;
5473 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5474
5475 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5476 reg_val &= 0x00ffffff;
5477 reg_val |= 0xb0000000;
5478 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5479 }
5480
5481 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5482 struct intel_link_m_n *m_n)
5483 {
5484 struct drm_device *dev = crtc->base.dev;
5485 struct drm_i915_private *dev_priv = dev->dev_private;
5486 int pipe = crtc->pipe;
5487
5488 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5489 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5490 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5491 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5492 }
5493
5494 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5495 struct intel_link_m_n *m_n,
5496 struct intel_link_m_n *m2_n2)
5497 {
5498 struct drm_device *dev = crtc->base.dev;
5499 struct drm_i915_private *dev_priv = dev->dev_private;
5500 int pipe = crtc->pipe;
5501 enum transcoder transcoder = crtc->config.cpu_transcoder;
5502
5503 if (INTEL_INFO(dev)->gen >= 5) {
5504 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5505 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5506 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5507 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5508 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5509 * for gen < 8) and if DRRS is supported (to make sure the
5510 * registers are not unnecessarily accessed).
5511 */
5512 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5513 crtc->config.has_drrs) {
5514 I915_WRITE(PIPE_DATA_M2(transcoder),
5515 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5516 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5517 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5518 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5519 }
5520 } else {
5521 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5522 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5523 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5524 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5525 }
5526 }
5527
5528 void intel_dp_set_m_n(struct intel_crtc *crtc)
5529 {
5530 if (crtc->config.has_pch_encoder)
5531 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5532 else
5533 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n,
5534 &crtc->config.dp_m2_n2);
5535 }
5536
5537 static void vlv_update_pll(struct intel_crtc *crtc)
5538 {
5539 u32 dpll, dpll_md;
5540
5541 /*
5542 * Enable DPIO clock input. We should never disable the reference
5543 * clock for pipe B, since VGA hotplug / manual detection depends
5544 * on it.
5545 */
5546 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5547 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5548 /* We should never disable this, set it here for state tracking */
5549 if (crtc->pipe == PIPE_B)
5550 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5551 dpll |= DPLL_VCO_ENABLE;
5552 crtc->config.dpll_hw_state.dpll = dpll;
5553
5554 dpll_md = (crtc->config.pixel_multiplier - 1)
5555 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5556 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5557 }
5558
5559 static void vlv_prepare_pll(struct intel_crtc *crtc)
5560 {
5561 struct drm_device *dev = crtc->base.dev;
5562 struct drm_i915_private *dev_priv = dev->dev_private;
5563 int pipe = crtc->pipe;
5564 u32 mdiv;
5565 u32 bestn, bestm1, bestm2, bestp1, bestp2;
5566 u32 coreclk, reg_val;
5567
5568 mutex_lock(&dev_priv->dpio_lock);
5569
5570 bestn = crtc->config.dpll.n;
5571 bestm1 = crtc->config.dpll.m1;
5572 bestm2 = crtc->config.dpll.m2;
5573 bestp1 = crtc->config.dpll.p1;
5574 bestp2 = crtc->config.dpll.p2;
5575
5576 /* See eDP HDMI DPIO driver vbios notes doc */
5577
5578 /* PLL B needs special handling */
5579 if (pipe == PIPE_B)
5580 vlv_pllb_recal_opamp(dev_priv, pipe);
5581
5582 /* Set up Tx target for periodic Rcomp update */
5583 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5584
5585 /* Disable target IRef on PLL */
5586 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5587 reg_val &= 0x00ffffff;
5588 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5589
5590 /* Disable fast lock */
5591 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5592
5593 /* Set idtafcrecal before PLL is enabled */
5594 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5595 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5596 mdiv |= ((bestn << DPIO_N_SHIFT));
5597 mdiv |= (1 << DPIO_K_SHIFT);
5598
5599 /*
5600 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5601 * but we don't support that).
5602 * Note: don't use the DAC post divider as it seems unstable.
5603 */
5604 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5605 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5606
5607 mdiv |= DPIO_ENABLE_CALIBRATION;
5608 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5609
5610 /* Set HBR and RBR LPF coefficients */
5611 if (crtc->config.port_clock == 162000 ||
5612 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5613 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5614 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5615 0x009f0003);
5616 else
5617 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5618 0x00d0000f);
5619
5620 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5621 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5622 /* Use SSC source */
5623 if (pipe == PIPE_A)
5624 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5625 0x0df40000);
5626 else
5627 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5628 0x0df70000);
5629 } else { /* HDMI or VGA */
5630 /* Use bend source */
5631 if (pipe == PIPE_A)
5632 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5633 0x0df70000);
5634 else
5635 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5636 0x0df40000);
5637 }
5638
5639 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5640 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5641 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5642 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5643 coreclk |= 0x01000000;
5644 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5645
5646 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5647 mutex_unlock(&dev_priv->dpio_lock);
5648 }
5649
5650 static void chv_update_pll(struct intel_crtc *crtc)
5651 {
5652 crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5653 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5654 DPLL_VCO_ENABLE;
5655 if (crtc->pipe != PIPE_A)
5656 crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5657
5658 crtc->config.dpll_hw_state.dpll_md =
5659 (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5660 }
5661
5662 static void chv_prepare_pll(struct intel_crtc *crtc)
5663 {
5664 struct drm_device *dev = crtc->base.dev;
5665 struct drm_i915_private *dev_priv = dev->dev_private;
5666 int pipe = crtc->pipe;
5667 int dpll_reg = DPLL(crtc->pipe);
5668 enum dpio_channel port = vlv_pipe_to_channel(pipe);
5669 u32 loopfilter, intcoeff;
5670 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5671 int refclk;
5672
5673 bestn = crtc->config.dpll.n;
5674 bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5675 bestm1 = crtc->config.dpll.m1;
5676 bestm2 = crtc->config.dpll.m2 >> 22;
5677 bestp1 = crtc->config.dpll.p1;
5678 bestp2 = crtc->config.dpll.p2;
5679
5680 /*
5681 * Enable Refclk and SSC
5682 */
5683 I915_WRITE(dpll_reg,
5684 crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5685
5686 mutex_lock(&dev_priv->dpio_lock);
5687
5688 /* p1 and p2 divider */
5689 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5690 5 << DPIO_CHV_S1_DIV_SHIFT |
5691 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5692 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5693 1 << DPIO_CHV_K_DIV_SHIFT);
5694
5695 /* Feedback post-divider - m2 */
5696 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5697
5698 /* Feedback refclk divider - n and m1 */
5699 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5700 DPIO_CHV_M1_DIV_BY_2 |
5701 1 << DPIO_CHV_N_DIV_SHIFT);
5702
5703 /* M2 fraction division */
5704 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5705
5706 /* M2 fraction division enable */
5707 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5708 DPIO_CHV_FRAC_DIV_EN |
5709 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5710
5711 /* Loop filter */
5712 refclk = i9xx_get_refclk(&crtc->base, 0);
5713 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5714 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5715 if (refclk == 100000)
5716 intcoeff = 11;
5717 else if (refclk == 38400)
5718 intcoeff = 10;
5719 else
5720 intcoeff = 9;
5721 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5722 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5723
5724 /* AFC Recal */
5725 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5726 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5727 DPIO_AFC_RECAL);
5728
5729 mutex_unlock(&dev_priv->dpio_lock);
5730 }
5731
5732 static void i9xx_update_pll(struct intel_crtc *crtc,
5733 intel_clock_t *reduced_clock,
5734 int num_connectors)
5735 {
5736 struct drm_device *dev = crtc->base.dev;
5737 struct drm_i915_private *dev_priv = dev->dev_private;
5738 u32 dpll;
5739 bool is_sdvo;
5740 struct dpll *clock = &crtc->config.dpll;
5741
5742 i9xx_update_pll_dividers(crtc, reduced_clock);
5743
5744 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5745 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5746
5747 dpll = DPLL_VGA_MODE_DIS;
5748
5749 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5750 dpll |= DPLLB_MODE_LVDS;
5751 else
5752 dpll |= DPLLB_MODE_DAC_SERIAL;
5753
5754 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5755 dpll |= (crtc->config.pixel_multiplier - 1)
5756 << SDVO_MULTIPLIER_SHIFT_HIRES;
5757 }
5758
5759 if (is_sdvo)
5760 dpll |= DPLL_SDVO_HIGH_SPEED;
5761
5762 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5763 dpll |= DPLL_SDVO_HIGH_SPEED;
5764
5765 /* compute bitmask from p1 value */
5766 if (IS_PINEVIEW(dev))
5767 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5768 else {
5769 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5770 if (IS_G4X(dev) && reduced_clock)
5771 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5772 }
5773 switch (clock->p2) {
5774 case 5:
5775 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5776 break;
5777 case 7:
5778 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5779 break;
5780 case 10:
5781 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5782 break;
5783 case 14:
5784 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5785 break;
5786 }
5787 if (INTEL_INFO(dev)->gen >= 4)
5788 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5789
5790 if (crtc->config.sdvo_tv_clock)
5791 dpll |= PLL_REF_INPUT_TVCLKINBC;
5792 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5793 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5794 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5795 else
5796 dpll |= PLL_REF_INPUT_DREFCLK;
5797
5798 dpll |= DPLL_VCO_ENABLE;
5799 crtc->config.dpll_hw_state.dpll = dpll;
5800
5801 if (INTEL_INFO(dev)->gen >= 4) {
5802 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5803 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5804 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5805 }
5806 }
5807
5808 static void i8xx_update_pll(struct intel_crtc *crtc,
5809 intel_clock_t *reduced_clock,
5810 int num_connectors)
5811 {
5812 struct drm_device *dev = crtc->base.dev;
5813 struct drm_i915_private *dev_priv = dev->dev_private;
5814 u32 dpll;
5815 struct dpll *clock = &crtc->config.dpll;
5816
5817 i9xx_update_pll_dividers(crtc, reduced_clock);
5818
5819 dpll = DPLL_VGA_MODE_DIS;
5820
5821 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5822 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5823 } else {
5824 if (clock->p1 == 2)
5825 dpll |= PLL_P1_DIVIDE_BY_TWO;
5826 else
5827 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5828 if (clock->p2 == 4)
5829 dpll |= PLL_P2_DIVIDE_BY_4;
5830 }
5831
5832 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5833 dpll |= DPLL_DVO_2X_MODE;
5834
5835 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5836 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5837 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5838 else
5839 dpll |= PLL_REF_INPUT_DREFCLK;
5840
5841 dpll |= DPLL_VCO_ENABLE;
5842 crtc->config.dpll_hw_state.dpll = dpll;
5843 }
5844
5845 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5846 {
5847 struct drm_device *dev = intel_crtc->base.dev;
5848 struct drm_i915_private *dev_priv = dev->dev_private;
5849 enum pipe pipe = intel_crtc->pipe;
5850 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5851 struct drm_display_mode *adjusted_mode =
5852 &intel_crtc->config.adjusted_mode;
5853 uint32_t crtc_vtotal, crtc_vblank_end;
5854 int vsyncshift = 0;
5855
5856 /* We need to be careful not to changed the adjusted mode, for otherwise
5857 * the hw state checker will get angry at the mismatch. */
5858 crtc_vtotal = adjusted_mode->crtc_vtotal;
5859 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5860
5861 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5862 /* the chip adds 2 halflines automatically */
5863 crtc_vtotal -= 1;
5864 crtc_vblank_end -= 1;
5865
5866 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5867 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5868 else
5869 vsyncshift = adjusted_mode->crtc_hsync_start -
5870 adjusted_mode->crtc_htotal / 2;
5871 if (vsyncshift < 0)
5872 vsyncshift += adjusted_mode->crtc_htotal;
5873 }
5874
5875 if (INTEL_INFO(dev)->gen > 3)
5876 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5877
5878 I915_WRITE(HTOTAL(cpu_transcoder),
5879 (adjusted_mode->crtc_hdisplay - 1) |
5880 ((adjusted_mode->crtc_htotal - 1) << 16));
5881 I915_WRITE(HBLANK(cpu_transcoder),
5882 (adjusted_mode->crtc_hblank_start - 1) |
5883 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5884 I915_WRITE(HSYNC(cpu_transcoder),
5885 (adjusted_mode->crtc_hsync_start - 1) |
5886 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5887
5888 I915_WRITE(VTOTAL(cpu_transcoder),
5889 (adjusted_mode->crtc_vdisplay - 1) |
5890 ((crtc_vtotal - 1) << 16));
5891 I915_WRITE(VBLANK(cpu_transcoder),
5892 (adjusted_mode->crtc_vblank_start - 1) |
5893 ((crtc_vblank_end - 1) << 16));
5894 I915_WRITE(VSYNC(cpu_transcoder),
5895 (adjusted_mode->crtc_vsync_start - 1) |
5896 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5897
5898 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5899 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5900 * documented on the DDI_FUNC_CTL register description, EDP Input Select
5901 * bits. */
5902 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5903 (pipe == PIPE_B || pipe == PIPE_C))
5904 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5905
5906 /* pipesrc controls the size that is scaled from, which should
5907 * always be the user's requested size.
5908 */
5909 I915_WRITE(PIPESRC(pipe),
5910 ((intel_crtc->config.pipe_src_w - 1) << 16) |
5911 (intel_crtc->config.pipe_src_h - 1));
5912 }
5913
5914 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5915 struct intel_crtc_config *pipe_config)
5916 {
5917 struct drm_device *dev = crtc->base.dev;
5918 struct drm_i915_private *dev_priv = dev->dev_private;
5919 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5920 uint32_t tmp;
5921
5922 tmp = I915_READ(HTOTAL(cpu_transcoder));
5923 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5924 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5925 tmp = I915_READ(HBLANK(cpu_transcoder));
5926 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5927 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5928 tmp = I915_READ(HSYNC(cpu_transcoder));
5929 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5930 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5931
5932 tmp = I915_READ(VTOTAL(cpu_transcoder));
5933 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5934 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5935 tmp = I915_READ(VBLANK(cpu_transcoder));
5936 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5937 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5938 tmp = I915_READ(VSYNC(cpu_transcoder));
5939 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5940 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5941
5942 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5943 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5944 pipe_config->adjusted_mode.crtc_vtotal += 1;
5945 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5946 }
5947
5948 tmp = I915_READ(PIPESRC(crtc->pipe));
5949 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5950 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5951
5952 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5953 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5954 }
5955
5956 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5957 struct intel_crtc_config *pipe_config)
5958 {
5959 mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5960 mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
5961 mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5962 mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5963
5964 mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5965 mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5966 mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5967 mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5968
5969 mode->flags = pipe_config->adjusted_mode.flags;
5970
5971 mode->clock = pipe_config->adjusted_mode.crtc_clock;
5972 mode->flags |= pipe_config->adjusted_mode.flags;
5973 }
5974
5975 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5976 {
5977 struct drm_device *dev = intel_crtc->base.dev;
5978 struct drm_i915_private *dev_priv = dev->dev_private;
5979 uint32_t pipeconf;
5980
5981 pipeconf = 0;
5982
5983 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5984 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5985 pipeconf |= PIPECONF_ENABLE;
5986
5987 if (intel_crtc->config.double_wide)
5988 pipeconf |= PIPECONF_DOUBLE_WIDE;
5989
5990 /* only g4x and later have fancy bpc/dither controls */
5991 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5992 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5993 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5994 pipeconf |= PIPECONF_DITHER_EN |
5995 PIPECONF_DITHER_TYPE_SP;
5996
5997 switch (intel_crtc->config.pipe_bpp) {
5998 case 18:
5999 pipeconf |= PIPECONF_6BPC;
6000 break;
6001 case 24:
6002 pipeconf |= PIPECONF_8BPC;
6003 break;
6004 case 30:
6005 pipeconf |= PIPECONF_10BPC;
6006 break;
6007 default:
6008 /* Case prevented by intel_choose_pipe_bpp_dither. */
6009 BUG();
6010 }
6011 }
6012
6013 if (HAS_PIPE_CXSR(dev)) {
6014 if (intel_crtc->lowfreq_avail) {
6015 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6016 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6017 } else {
6018 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6019 }
6020 }
6021
6022 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6023 if (INTEL_INFO(dev)->gen < 4 ||
6024 intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
6025 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6026 else
6027 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6028 } else
6029 pipeconf |= PIPECONF_PROGRESSIVE;
6030
6031 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6032 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6033
6034 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6035 POSTING_READ(PIPECONF(intel_crtc->pipe));
6036 }
6037
6038 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
6039 int x, int y,
6040 struct drm_framebuffer *fb)
6041 {
6042 struct drm_device *dev = crtc->dev;
6043 struct drm_i915_private *dev_priv = dev->dev_private;
6044 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6045 int refclk, num_connectors = 0;
6046 intel_clock_t clock, reduced_clock;
6047 bool ok, has_reduced_clock = false;
6048 bool is_lvds = false, is_dsi = false;
6049 struct intel_encoder *encoder;
6050 const intel_limit_t *limit;
6051
6052 for_each_encoder_on_crtc(dev, crtc, encoder) {
6053 switch (encoder->type) {
6054 case INTEL_OUTPUT_LVDS:
6055 is_lvds = true;
6056 break;
6057 case INTEL_OUTPUT_DSI:
6058 is_dsi = true;
6059 break;
6060 }
6061
6062 num_connectors++;
6063 }
6064
6065 if (is_dsi)
6066 return 0;
6067
6068 if (!intel_crtc->config.clock_set) {
6069 refclk = i9xx_get_refclk(crtc, num_connectors);
6070
6071 /*
6072 * Returns a set of divisors for the desired target clock with
6073 * the given refclk, or FALSE. The returned values represent
6074 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6075 * 2) / p1 / p2.
6076 */
6077 limit = intel_limit(crtc, refclk);
6078 ok = dev_priv->display.find_dpll(limit, crtc,
6079 intel_crtc->config.port_clock,
6080 refclk, NULL, &clock);
6081 if (!ok) {
6082 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6083 return -EINVAL;
6084 }
6085
6086 if (is_lvds && dev_priv->lvds_downclock_avail) {
6087 /*
6088 * Ensure we match the reduced clock's P to the target
6089 * clock. If the clocks don't match, we can't switch
6090 * the display clock by using the FP0/FP1. In such case
6091 * we will disable the LVDS downclock feature.
6092 */
6093 has_reduced_clock =
6094 dev_priv->display.find_dpll(limit, crtc,
6095 dev_priv->lvds_downclock,
6096 refclk, &clock,
6097 &reduced_clock);
6098 }
6099 /* Compat-code for transition, will disappear. */
6100 intel_crtc->config.dpll.n = clock.n;
6101 intel_crtc->config.dpll.m1 = clock.m1;
6102 intel_crtc->config.dpll.m2 = clock.m2;
6103 intel_crtc->config.dpll.p1 = clock.p1;
6104 intel_crtc->config.dpll.p2 = clock.p2;
6105 }
6106
6107 if (IS_GEN2(dev)) {
6108 i8xx_update_pll(intel_crtc,
6109 has_reduced_clock ? &reduced_clock : NULL,
6110 num_connectors);
6111 } else if (IS_CHERRYVIEW(dev)) {
6112 chv_update_pll(intel_crtc);
6113 } else if (IS_VALLEYVIEW(dev)) {
6114 vlv_update_pll(intel_crtc);
6115 } else {
6116 i9xx_update_pll(intel_crtc,
6117 has_reduced_clock ? &reduced_clock : NULL,
6118 num_connectors);
6119 }
6120
6121 return 0;
6122 }
6123
6124 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6125 struct intel_crtc_config *pipe_config)
6126 {
6127 struct drm_device *dev = crtc->base.dev;
6128 struct drm_i915_private *dev_priv = dev->dev_private;
6129 uint32_t tmp;
6130
6131 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6132 return;
6133
6134 tmp = I915_READ(PFIT_CONTROL);
6135 if (!(tmp & PFIT_ENABLE))
6136 return;
6137
6138 /* Check whether the pfit is attached to our pipe. */
6139 if (INTEL_INFO(dev)->gen < 4) {
6140 if (crtc->pipe != PIPE_B)
6141 return;
6142 } else {
6143 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6144 return;
6145 }
6146
6147 pipe_config->gmch_pfit.control = tmp;
6148 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6149 if (INTEL_INFO(dev)->gen < 5)
6150 pipe_config->gmch_pfit.lvds_border_bits =
6151 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6152 }
6153
6154 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6155 struct intel_crtc_config *pipe_config)
6156 {
6157 struct drm_device *dev = crtc->base.dev;
6158 struct drm_i915_private *dev_priv = dev->dev_private;
6159 int pipe = pipe_config->cpu_transcoder;
6160 intel_clock_t clock;
6161 u32 mdiv;
6162 int refclk = 100000;
6163
6164 /* In case of MIPI DPLL will not even be used */
6165 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6166 return;
6167
6168 mutex_lock(&dev_priv->dpio_lock);
6169 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6170 mutex_unlock(&dev_priv->dpio_lock);
6171
6172 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6173 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6174 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6175 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6176 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6177
6178 vlv_clock(refclk, &clock);
6179
6180 /* clock.dot is the fast clock */
6181 pipe_config->port_clock = clock.dot / 5;
6182 }
6183
6184 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6185 struct intel_plane_config *plane_config)
6186 {
6187 struct drm_device *dev = crtc->base.dev;
6188 struct drm_i915_private *dev_priv = dev->dev_private;
6189 u32 val, base, offset;
6190 int pipe = crtc->pipe, plane = crtc->plane;
6191 int fourcc, pixel_format;
6192 int aligned_height;
6193
6194 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6195 if (!crtc->base.primary->fb) {
6196 DRM_DEBUG_KMS("failed to alloc fb\n");
6197 return;
6198 }
6199
6200 val = I915_READ(DSPCNTR(plane));
6201
6202 if (INTEL_INFO(dev)->gen >= 4)
6203 if (val & DISPPLANE_TILED)
6204 plane_config->tiled = true;
6205
6206 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6207 fourcc = intel_format_to_fourcc(pixel_format);
6208 crtc->base.primary->fb->pixel_format = fourcc;
6209 crtc->base.primary->fb->bits_per_pixel =
6210 drm_format_plane_cpp(fourcc, 0) * 8;
6211
6212 if (INTEL_INFO(dev)->gen >= 4) {
6213 if (plane_config->tiled)
6214 offset = I915_READ(DSPTILEOFF(plane));
6215 else
6216 offset = I915_READ(DSPLINOFF(plane));
6217 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6218 } else {
6219 base = I915_READ(DSPADDR(plane));
6220 }
6221 plane_config->base = base;
6222
6223 val = I915_READ(PIPESRC(pipe));
6224 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6225 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6226
6227 val = I915_READ(DSPSTRIDE(pipe));
6228 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
6229
6230 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6231 plane_config->tiled);
6232
6233 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6234 aligned_height);
6235
6236 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6237 pipe, plane, crtc->base.primary->fb->width,
6238 crtc->base.primary->fb->height,
6239 crtc->base.primary->fb->bits_per_pixel, base,
6240 crtc->base.primary->fb->pitches[0],
6241 plane_config->size);
6242
6243 }
6244
6245 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6246 struct intel_crtc_config *pipe_config)
6247 {
6248 struct drm_device *dev = crtc->base.dev;
6249 struct drm_i915_private *dev_priv = dev->dev_private;
6250 int pipe = pipe_config->cpu_transcoder;
6251 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6252 intel_clock_t clock;
6253 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6254 int refclk = 100000;
6255
6256 mutex_lock(&dev_priv->dpio_lock);
6257 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6258 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6259 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6260 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6261 mutex_unlock(&dev_priv->dpio_lock);
6262
6263 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6264 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6265 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6266 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6267 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6268
6269 chv_clock(refclk, &clock);
6270
6271 /* clock.dot is the fast clock */
6272 pipe_config->port_clock = clock.dot / 5;
6273 }
6274
6275 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6276 struct intel_crtc_config *pipe_config)
6277 {
6278 struct drm_device *dev = crtc->base.dev;
6279 struct drm_i915_private *dev_priv = dev->dev_private;
6280 uint32_t tmp;
6281
6282 if (!intel_display_power_enabled(dev_priv,
6283 POWER_DOMAIN_PIPE(crtc->pipe)))
6284 return false;
6285
6286 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6287 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6288
6289 tmp = I915_READ(PIPECONF(crtc->pipe));
6290 if (!(tmp & PIPECONF_ENABLE))
6291 return false;
6292
6293 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6294 switch (tmp & PIPECONF_BPC_MASK) {
6295 case PIPECONF_6BPC:
6296 pipe_config->pipe_bpp = 18;
6297 break;
6298 case PIPECONF_8BPC:
6299 pipe_config->pipe_bpp = 24;
6300 break;
6301 case PIPECONF_10BPC:
6302 pipe_config->pipe_bpp = 30;
6303 break;
6304 default:
6305 break;
6306 }
6307 }
6308
6309 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6310 pipe_config->limited_color_range = true;
6311
6312 if (INTEL_INFO(dev)->gen < 4)
6313 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6314
6315 intel_get_pipe_timings(crtc, pipe_config);
6316
6317 i9xx_get_pfit_config(crtc, pipe_config);
6318
6319 if (INTEL_INFO(dev)->gen >= 4) {
6320 tmp = I915_READ(DPLL_MD(crtc->pipe));
6321 pipe_config->pixel_multiplier =
6322 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6323 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6324 pipe_config->dpll_hw_state.dpll_md = tmp;
6325 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6326 tmp = I915_READ(DPLL(crtc->pipe));
6327 pipe_config->pixel_multiplier =
6328 ((tmp & SDVO_MULTIPLIER_MASK)
6329 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6330 } else {
6331 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6332 * port and will be fixed up in the encoder->get_config
6333 * function. */
6334 pipe_config->pixel_multiplier = 1;
6335 }
6336 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6337 if (!IS_VALLEYVIEW(dev)) {
6338 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6339 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6340 } else {
6341 /* Mask out read-only status bits. */
6342 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6343 DPLL_PORTC_READY_MASK |
6344 DPLL_PORTB_READY_MASK);
6345 }
6346
6347 if (IS_CHERRYVIEW(dev))
6348 chv_crtc_clock_get(crtc, pipe_config);
6349 else if (IS_VALLEYVIEW(dev))
6350 vlv_crtc_clock_get(crtc, pipe_config);
6351 else
6352 i9xx_crtc_clock_get(crtc, pipe_config);
6353
6354 return true;
6355 }
6356
6357 static void ironlake_init_pch_refclk(struct drm_device *dev)
6358 {
6359 struct drm_i915_private *dev_priv = dev->dev_private;
6360 struct intel_encoder *encoder;
6361 u32 val, final;
6362 bool has_lvds = false;
6363 bool has_cpu_edp = false;
6364 bool has_panel = false;
6365 bool has_ck505 = false;
6366 bool can_ssc = false;
6367
6368 /* We need to take the global config into account */
6369 for_each_intel_encoder(dev, encoder) {
6370 switch (encoder->type) {
6371 case INTEL_OUTPUT_LVDS:
6372 has_panel = true;
6373 has_lvds = true;
6374 break;
6375 case INTEL_OUTPUT_EDP:
6376 has_panel = true;
6377 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6378 has_cpu_edp = true;
6379 break;
6380 }
6381 }
6382
6383 if (HAS_PCH_IBX(dev)) {
6384 has_ck505 = dev_priv->vbt.display_clock_mode;
6385 can_ssc = has_ck505;
6386 } else {
6387 has_ck505 = false;
6388 can_ssc = true;
6389 }
6390
6391 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6392 has_panel, has_lvds, has_ck505);
6393
6394 /* Ironlake: try to setup display ref clock before DPLL
6395 * enabling. This is only under driver's control after
6396 * PCH B stepping, previous chipset stepping should be
6397 * ignoring this setting.
6398 */
6399 val = I915_READ(PCH_DREF_CONTROL);
6400
6401 /* As we must carefully and slowly disable/enable each source in turn,
6402 * compute the final state we want first and check if we need to
6403 * make any changes at all.
6404 */
6405 final = val;
6406 final &= ~DREF_NONSPREAD_SOURCE_MASK;
6407 if (has_ck505)
6408 final |= DREF_NONSPREAD_CK505_ENABLE;
6409 else
6410 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6411
6412 final &= ~DREF_SSC_SOURCE_MASK;
6413 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6414 final &= ~DREF_SSC1_ENABLE;
6415
6416 if (has_panel) {
6417 final |= DREF_SSC_SOURCE_ENABLE;
6418
6419 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6420 final |= DREF_SSC1_ENABLE;
6421
6422 if (has_cpu_edp) {
6423 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6424 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6425 else
6426 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6427 } else
6428 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6429 } else {
6430 final |= DREF_SSC_SOURCE_DISABLE;
6431 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6432 }
6433
6434 if (final == val)
6435 return;
6436
6437 /* Always enable nonspread source */
6438 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6439
6440 if (has_ck505)
6441 val |= DREF_NONSPREAD_CK505_ENABLE;
6442 else
6443 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6444
6445 if (has_panel) {
6446 val &= ~DREF_SSC_SOURCE_MASK;
6447 val |= DREF_SSC_SOURCE_ENABLE;
6448
6449 /* SSC must be turned on before enabling the CPU output */
6450 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6451 DRM_DEBUG_KMS("Using SSC on panel\n");
6452 val |= DREF_SSC1_ENABLE;
6453 } else
6454 val &= ~DREF_SSC1_ENABLE;
6455
6456 /* Get SSC going before enabling the outputs */
6457 I915_WRITE(PCH_DREF_CONTROL, val);
6458 POSTING_READ(PCH_DREF_CONTROL);
6459 udelay(200);
6460
6461 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6462
6463 /* Enable CPU source on CPU attached eDP */
6464 if (has_cpu_edp) {
6465 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6466 DRM_DEBUG_KMS("Using SSC on eDP\n");
6467 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6468 } else
6469 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6470 } else
6471 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6472
6473 I915_WRITE(PCH_DREF_CONTROL, val);
6474 POSTING_READ(PCH_DREF_CONTROL);
6475 udelay(200);
6476 } else {
6477 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6478
6479 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6480
6481 /* Turn off CPU output */
6482 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6483
6484 I915_WRITE(PCH_DREF_CONTROL, val);
6485 POSTING_READ(PCH_DREF_CONTROL);
6486 udelay(200);
6487
6488 /* Turn off the SSC source */
6489 val &= ~DREF_SSC_SOURCE_MASK;
6490 val |= DREF_SSC_SOURCE_DISABLE;
6491
6492 /* Turn off SSC1 */
6493 val &= ~DREF_SSC1_ENABLE;
6494
6495 I915_WRITE(PCH_DREF_CONTROL, val);
6496 POSTING_READ(PCH_DREF_CONTROL);
6497 udelay(200);
6498 }
6499
6500 BUG_ON(val != final);
6501 }
6502
6503 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6504 {
6505 uint32_t tmp;
6506
6507 tmp = I915_READ(SOUTH_CHICKEN2);
6508 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6509 I915_WRITE(SOUTH_CHICKEN2, tmp);
6510
6511 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6512 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6513 DRM_ERROR("FDI mPHY reset assert timeout\n");
6514
6515 tmp = I915_READ(SOUTH_CHICKEN2);
6516 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6517 I915_WRITE(SOUTH_CHICKEN2, tmp);
6518
6519 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6520 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6521 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6522 }
6523
6524 /* WaMPhyProgramming:hsw */
6525 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6526 {
6527 uint32_t tmp;
6528
6529 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6530 tmp &= ~(0xFF << 24);
6531 tmp |= (0x12 << 24);
6532 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6533
6534 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6535 tmp |= (1 << 11);
6536 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6537
6538 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6539 tmp |= (1 << 11);
6540 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6541
6542 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6543 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6544 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6545
6546 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6547 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6548 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6549
6550 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6551 tmp &= ~(7 << 13);
6552 tmp |= (5 << 13);
6553 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6554
6555 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6556 tmp &= ~(7 << 13);
6557 tmp |= (5 << 13);
6558 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6559
6560 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6561 tmp &= ~0xFF;
6562 tmp |= 0x1C;
6563 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6564
6565 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6566 tmp &= ~0xFF;
6567 tmp |= 0x1C;
6568 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6569
6570 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6571 tmp &= ~(0xFF << 16);
6572 tmp |= (0x1C << 16);
6573 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6574
6575 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6576 tmp &= ~(0xFF << 16);
6577 tmp |= (0x1C << 16);
6578 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6579
6580 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6581 tmp |= (1 << 27);
6582 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6583
6584 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6585 tmp |= (1 << 27);
6586 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6587
6588 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6589 tmp &= ~(0xF << 28);
6590 tmp |= (4 << 28);
6591 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6592
6593 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6594 tmp &= ~(0xF << 28);
6595 tmp |= (4 << 28);
6596 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6597 }
6598
6599 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6600 * Programming" based on the parameters passed:
6601 * - Sequence to enable CLKOUT_DP
6602 * - Sequence to enable CLKOUT_DP without spread
6603 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6604 */
6605 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6606 bool with_fdi)
6607 {
6608 struct drm_i915_private *dev_priv = dev->dev_private;
6609 uint32_t reg, tmp;
6610
6611 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6612 with_spread = true;
6613 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6614 with_fdi, "LP PCH doesn't have FDI\n"))
6615 with_fdi = false;
6616
6617 mutex_lock(&dev_priv->dpio_lock);
6618
6619 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6620 tmp &= ~SBI_SSCCTL_DISABLE;
6621 tmp |= SBI_SSCCTL_PATHALT;
6622 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6623
6624 udelay(24);
6625
6626 if (with_spread) {
6627 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6628 tmp &= ~SBI_SSCCTL_PATHALT;
6629 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6630
6631 if (with_fdi) {
6632 lpt_reset_fdi_mphy(dev_priv);
6633 lpt_program_fdi_mphy(dev_priv);
6634 }
6635 }
6636
6637 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6638 SBI_GEN0 : SBI_DBUFF0;
6639 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6640 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6641 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6642
6643 mutex_unlock(&dev_priv->dpio_lock);
6644 }
6645
6646 /* Sequence to disable CLKOUT_DP */
6647 static void lpt_disable_clkout_dp(struct drm_device *dev)
6648 {
6649 struct drm_i915_private *dev_priv = dev->dev_private;
6650 uint32_t reg, tmp;
6651
6652 mutex_lock(&dev_priv->dpio_lock);
6653
6654 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6655 SBI_GEN0 : SBI_DBUFF0;
6656 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6657 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6658 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6659
6660 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6661 if (!(tmp & SBI_SSCCTL_DISABLE)) {
6662 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6663 tmp |= SBI_SSCCTL_PATHALT;
6664 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6665 udelay(32);
6666 }
6667 tmp |= SBI_SSCCTL_DISABLE;
6668 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6669 }
6670
6671 mutex_unlock(&dev_priv->dpio_lock);
6672 }
6673
6674 static void lpt_init_pch_refclk(struct drm_device *dev)
6675 {
6676 struct intel_encoder *encoder;
6677 bool has_vga = false;
6678
6679 for_each_intel_encoder(dev, encoder) {
6680 switch (encoder->type) {
6681 case INTEL_OUTPUT_ANALOG:
6682 has_vga = true;
6683 break;
6684 }
6685 }
6686
6687 if (has_vga)
6688 lpt_enable_clkout_dp(dev, true, true);
6689 else
6690 lpt_disable_clkout_dp(dev);
6691 }
6692
6693 /*
6694 * Initialize reference clocks when the driver loads
6695 */
6696 void intel_init_pch_refclk(struct drm_device *dev)
6697 {
6698 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6699 ironlake_init_pch_refclk(dev);
6700 else if (HAS_PCH_LPT(dev))
6701 lpt_init_pch_refclk(dev);
6702 }
6703
6704 static int ironlake_get_refclk(struct drm_crtc *crtc)
6705 {
6706 struct drm_device *dev = crtc->dev;
6707 struct drm_i915_private *dev_priv = dev->dev_private;
6708 struct intel_encoder *encoder;
6709 int num_connectors = 0;
6710 bool is_lvds = false;
6711
6712 for_each_encoder_on_crtc(dev, crtc, encoder) {
6713 switch (encoder->type) {
6714 case INTEL_OUTPUT_LVDS:
6715 is_lvds = true;
6716 break;
6717 }
6718 num_connectors++;
6719 }
6720
6721 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6722 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6723 dev_priv->vbt.lvds_ssc_freq);
6724 return dev_priv->vbt.lvds_ssc_freq;
6725 }
6726
6727 return 120000;
6728 }
6729
6730 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6731 {
6732 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6733 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6734 int pipe = intel_crtc->pipe;
6735 uint32_t val;
6736
6737 val = 0;
6738
6739 switch (intel_crtc->config.pipe_bpp) {
6740 case 18:
6741 val |= PIPECONF_6BPC;
6742 break;
6743 case 24:
6744 val |= PIPECONF_8BPC;
6745 break;
6746 case 30:
6747 val |= PIPECONF_10BPC;
6748 break;
6749 case 36:
6750 val |= PIPECONF_12BPC;
6751 break;
6752 default:
6753 /* Case prevented by intel_choose_pipe_bpp_dither. */
6754 BUG();
6755 }
6756
6757 if (intel_crtc->config.dither)
6758 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6759
6760 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6761 val |= PIPECONF_INTERLACED_ILK;
6762 else
6763 val |= PIPECONF_PROGRESSIVE;
6764
6765 if (intel_crtc->config.limited_color_range)
6766 val |= PIPECONF_COLOR_RANGE_SELECT;
6767
6768 I915_WRITE(PIPECONF(pipe), val);
6769 POSTING_READ(PIPECONF(pipe));
6770 }
6771
6772 /*
6773 * Set up the pipe CSC unit.
6774 *
6775 * Currently only full range RGB to limited range RGB conversion
6776 * is supported, but eventually this should handle various
6777 * RGB<->YCbCr scenarios as well.
6778 */
6779 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6780 {
6781 struct drm_device *dev = crtc->dev;
6782 struct drm_i915_private *dev_priv = dev->dev_private;
6783 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6784 int pipe = intel_crtc->pipe;
6785 uint16_t coeff = 0x7800; /* 1.0 */
6786
6787 /*
6788 * TODO: Check what kind of values actually come out of the pipe
6789 * with these coeff/postoff values and adjust to get the best
6790 * accuracy. Perhaps we even need to take the bpc value into
6791 * consideration.
6792 */
6793
6794 if (intel_crtc->config.limited_color_range)
6795 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6796
6797 /*
6798 * GY/GU and RY/RU should be the other way around according
6799 * to BSpec, but reality doesn't agree. Just set them up in
6800 * a way that results in the correct picture.
6801 */
6802 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6803 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6804
6805 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6806 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6807
6808 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6809 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6810
6811 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6812 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6813 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6814
6815 if (INTEL_INFO(dev)->gen > 6) {
6816 uint16_t postoff = 0;
6817
6818 if (intel_crtc->config.limited_color_range)
6819 postoff = (16 * (1 << 12) / 255) & 0x1fff;
6820
6821 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6822 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6823 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6824
6825 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6826 } else {
6827 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6828
6829 if (intel_crtc->config.limited_color_range)
6830 mode |= CSC_BLACK_SCREEN_OFFSET;
6831
6832 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6833 }
6834 }
6835
6836 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6837 {
6838 struct drm_device *dev = crtc->dev;
6839 struct drm_i915_private *dev_priv = dev->dev_private;
6840 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6841 enum pipe pipe = intel_crtc->pipe;
6842 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6843 uint32_t val;
6844
6845 val = 0;
6846
6847 if (IS_HASWELL(dev) && intel_crtc->config.dither)
6848 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6849
6850 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6851 val |= PIPECONF_INTERLACED_ILK;
6852 else
6853 val |= PIPECONF_PROGRESSIVE;
6854
6855 I915_WRITE(PIPECONF(cpu_transcoder), val);
6856 POSTING_READ(PIPECONF(cpu_transcoder));
6857
6858 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6859 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6860
6861 if (IS_BROADWELL(dev)) {
6862 val = 0;
6863
6864 switch (intel_crtc->config.pipe_bpp) {
6865 case 18:
6866 val |= PIPEMISC_DITHER_6_BPC;
6867 break;
6868 case 24:
6869 val |= PIPEMISC_DITHER_8_BPC;
6870 break;
6871 case 30:
6872 val |= PIPEMISC_DITHER_10_BPC;
6873 break;
6874 case 36:
6875 val |= PIPEMISC_DITHER_12_BPC;
6876 break;
6877 default:
6878 /* Case prevented by pipe_config_set_bpp. */
6879 BUG();
6880 }
6881
6882 if (intel_crtc->config.dither)
6883 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6884
6885 I915_WRITE(PIPEMISC(pipe), val);
6886 }
6887 }
6888
6889 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6890 intel_clock_t *clock,
6891 bool *has_reduced_clock,
6892 intel_clock_t *reduced_clock)
6893 {
6894 struct drm_device *dev = crtc->dev;
6895 struct drm_i915_private *dev_priv = dev->dev_private;
6896 struct intel_encoder *intel_encoder;
6897 int refclk;
6898 const intel_limit_t *limit;
6899 bool ret, is_lvds = false;
6900
6901 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6902 switch (intel_encoder->type) {
6903 case INTEL_OUTPUT_LVDS:
6904 is_lvds = true;
6905 break;
6906 }
6907 }
6908
6909 refclk = ironlake_get_refclk(crtc);
6910
6911 /*
6912 * Returns a set of divisors for the desired target clock with the given
6913 * refclk, or FALSE. The returned values represent the clock equation:
6914 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6915 */
6916 limit = intel_limit(crtc, refclk);
6917 ret = dev_priv->display.find_dpll(limit, crtc,
6918 to_intel_crtc(crtc)->config.port_clock,
6919 refclk, NULL, clock);
6920 if (!ret)
6921 return false;
6922
6923 if (is_lvds && dev_priv->lvds_downclock_avail) {
6924 /*
6925 * Ensure we match the reduced clock's P to the target clock.
6926 * If the clocks don't match, we can't switch the display clock
6927 * by using the FP0/FP1. In such case we will disable the LVDS
6928 * downclock feature.
6929 */
6930 *has_reduced_clock =
6931 dev_priv->display.find_dpll(limit, crtc,
6932 dev_priv->lvds_downclock,
6933 refclk, clock,
6934 reduced_clock);
6935 }
6936
6937 return true;
6938 }
6939
6940 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6941 {
6942 /*
6943 * Account for spread spectrum to avoid
6944 * oversubscribing the link. Max center spread
6945 * is 2.5%; use 5% for safety's sake.
6946 */
6947 u32 bps = target_clock * bpp * 21 / 20;
6948 return DIV_ROUND_UP(bps, link_bw * 8);
6949 }
6950
6951 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6952 {
6953 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6954 }
6955
6956 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6957 u32 *fp,
6958 intel_clock_t *reduced_clock, u32 *fp2)
6959 {
6960 struct drm_crtc *crtc = &intel_crtc->base;
6961 struct drm_device *dev = crtc->dev;
6962 struct drm_i915_private *dev_priv = dev->dev_private;
6963 struct intel_encoder *intel_encoder;
6964 uint32_t dpll;
6965 int factor, num_connectors = 0;
6966 bool is_lvds = false, is_sdvo = false;
6967
6968 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6969 switch (intel_encoder->type) {
6970 case INTEL_OUTPUT_LVDS:
6971 is_lvds = true;
6972 break;
6973 case INTEL_OUTPUT_SDVO:
6974 case INTEL_OUTPUT_HDMI:
6975 is_sdvo = true;
6976 break;
6977 }
6978
6979 num_connectors++;
6980 }
6981
6982 /* Enable autotuning of the PLL clock (if permissible) */
6983 factor = 21;
6984 if (is_lvds) {
6985 if ((intel_panel_use_ssc(dev_priv) &&
6986 dev_priv->vbt.lvds_ssc_freq == 100000) ||
6987 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6988 factor = 25;
6989 } else if (intel_crtc->config.sdvo_tv_clock)
6990 factor = 20;
6991
6992 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
6993 *fp |= FP_CB_TUNE;
6994
6995 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6996 *fp2 |= FP_CB_TUNE;
6997
6998 dpll = 0;
6999
7000 if (is_lvds)
7001 dpll |= DPLLB_MODE_LVDS;
7002 else
7003 dpll |= DPLLB_MODE_DAC_SERIAL;
7004
7005 dpll |= (intel_crtc->config.pixel_multiplier - 1)
7006 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7007
7008 if (is_sdvo)
7009 dpll |= DPLL_SDVO_HIGH_SPEED;
7010 if (intel_crtc->config.has_dp_encoder)
7011 dpll |= DPLL_SDVO_HIGH_SPEED;
7012
7013 /* compute bitmask from p1 value */
7014 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7015 /* also FPA1 */
7016 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7017
7018 switch (intel_crtc->config.dpll.p2) {
7019 case 5:
7020 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7021 break;
7022 case 7:
7023 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7024 break;
7025 case 10:
7026 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7027 break;
7028 case 14:
7029 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7030 break;
7031 }
7032
7033 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7034 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7035 else
7036 dpll |= PLL_REF_INPUT_DREFCLK;
7037
7038 return dpll | DPLL_VCO_ENABLE;
7039 }
7040
7041 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
7042 int x, int y,
7043 struct drm_framebuffer *fb)
7044 {
7045 struct drm_device *dev = crtc->dev;
7046 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7047 int num_connectors = 0;
7048 intel_clock_t clock, reduced_clock;
7049 u32 dpll = 0, fp = 0, fp2 = 0;
7050 bool ok, has_reduced_clock = false;
7051 bool is_lvds = false;
7052 struct intel_encoder *encoder;
7053 struct intel_shared_dpll *pll;
7054
7055 for_each_encoder_on_crtc(dev, crtc, encoder) {
7056 switch (encoder->type) {
7057 case INTEL_OUTPUT_LVDS:
7058 is_lvds = true;
7059 break;
7060 }
7061
7062 num_connectors++;
7063 }
7064
7065 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7066 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7067
7068 ok = ironlake_compute_clocks(crtc, &clock,
7069 &has_reduced_clock, &reduced_clock);
7070 if (!ok && !intel_crtc->config.clock_set) {
7071 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7072 return -EINVAL;
7073 }
7074 /* Compat-code for transition, will disappear. */
7075 if (!intel_crtc->config.clock_set) {
7076 intel_crtc->config.dpll.n = clock.n;
7077 intel_crtc->config.dpll.m1 = clock.m1;
7078 intel_crtc->config.dpll.m2 = clock.m2;
7079 intel_crtc->config.dpll.p1 = clock.p1;
7080 intel_crtc->config.dpll.p2 = clock.p2;
7081 }
7082
7083 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7084 if (intel_crtc->config.has_pch_encoder) {
7085 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
7086 if (has_reduced_clock)
7087 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7088
7089 dpll = ironlake_compute_dpll(intel_crtc,
7090 &fp, &reduced_clock,
7091 has_reduced_clock ? &fp2 : NULL);
7092
7093 intel_crtc->config.dpll_hw_state.dpll = dpll;
7094 intel_crtc->config.dpll_hw_state.fp0 = fp;
7095 if (has_reduced_clock)
7096 intel_crtc->config.dpll_hw_state.fp1 = fp2;
7097 else
7098 intel_crtc->config.dpll_hw_state.fp1 = fp;
7099
7100 pll = intel_get_shared_dpll(intel_crtc);
7101 if (pll == NULL) {
7102 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7103 pipe_name(intel_crtc->pipe));
7104 return -EINVAL;
7105 }
7106 } else
7107 intel_put_shared_dpll(intel_crtc);
7108
7109 if (is_lvds && has_reduced_clock && i915.powersave)
7110 intel_crtc->lowfreq_avail = true;
7111 else
7112 intel_crtc->lowfreq_avail = false;
7113
7114 return 0;
7115 }
7116
7117 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7118 struct intel_link_m_n *m_n)
7119 {
7120 struct drm_device *dev = crtc->base.dev;
7121 struct drm_i915_private *dev_priv = dev->dev_private;
7122 enum pipe pipe = crtc->pipe;
7123
7124 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7125 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7126 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7127 & ~TU_SIZE_MASK;
7128 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7129 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7130 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7131 }
7132
7133 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7134 enum transcoder transcoder,
7135 struct intel_link_m_n *m_n,
7136 struct intel_link_m_n *m2_n2)
7137 {
7138 struct drm_device *dev = crtc->base.dev;
7139 struct drm_i915_private *dev_priv = dev->dev_private;
7140 enum pipe pipe = crtc->pipe;
7141
7142 if (INTEL_INFO(dev)->gen >= 5) {
7143 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7144 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7145 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7146 & ~TU_SIZE_MASK;
7147 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7148 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7149 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7150 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7151 * gen < 8) and if DRRS is supported (to make sure the
7152 * registers are not unnecessarily read).
7153 */
7154 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7155 crtc->config.has_drrs) {
7156 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7157 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7158 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7159 & ~TU_SIZE_MASK;
7160 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7161 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7162 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7163 }
7164 } else {
7165 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7166 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7167 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7168 & ~TU_SIZE_MASK;
7169 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7170 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7171 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7172 }
7173 }
7174
7175 void intel_dp_get_m_n(struct intel_crtc *crtc,
7176 struct intel_crtc_config *pipe_config)
7177 {
7178 if (crtc->config.has_pch_encoder)
7179 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7180 else
7181 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7182 &pipe_config->dp_m_n,
7183 &pipe_config->dp_m2_n2);
7184 }
7185
7186 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7187 struct intel_crtc_config *pipe_config)
7188 {
7189 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7190 &pipe_config->fdi_m_n, NULL);
7191 }
7192
7193 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7194 struct intel_crtc_config *pipe_config)
7195 {
7196 struct drm_device *dev = crtc->base.dev;
7197 struct drm_i915_private *dev_priv = dev->dev_private;
7198 uint32_t tmp;
7199
7200 tmp = I915_READ(PF_CTL(crtc->pipe));
7201
7202 if (tmp & PF_ENABLE) {
7203 pipe_config->pch_pfit.enabled = true;
7204 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7205 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7206
7207 /* We currently do not free assignements of panel fitters on
7208 * ivb/hsw (since we don't use the higher upscaling modes which
7209 * differentiates them) so just WARN about this case for now. */
7210 if (IS_GEN7(dev)) {
7211 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7212 PF_PIPE_SEL_IVB(crtc->pipe));
7213 }
7214 }
7215 }
7216
7217 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7218 struct intel_plane_config *plane_config)
7219 {
7220 struct drm_device *dev = crtc->base.dev;
7221 struct drm_i915_private *dev_priv = dev->dev_private;
7222 u32 val, base, offset;
7223 int pipe = crtc->pipe, plane = crtc->plane;
7224 int fourcc, pixel_format;
7225 int aligned_height;
7226
7227 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7228 if (!crtc->base.primary->fb) {
7229 DRM_DEBUG_KMS("failed to alloc fb\n");
7230 return;
7231 }
7232
7233 val = I915_READ(DSPCNTR(plane));
7234
7235 if (INTEL_INFO(dev)->gen >= 4)
7236 if (val & DISPPLANE_TILED)
7237 plane_config->tiled = true;
7238
7239 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7240 fourcc = intel_format_to_fourcc(pixel_format);
7241 crtc->base.primary->fb->pixel_format = fourcc;
7242 crtc->base.primary->fb->bits_per_pixel =
7243 drm_format_plane_cpp(fourcc, 0) * 8;
7244
7245 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7246 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7247 offset = I915_READ(DSPOFFSET(plane));
7248 } else {
7249 if (plane_config->tiled)
7250 offset = I915_READ(DSPTILEOFF(plane));
7251 else
7252 offset = I915_READ(DSPLINOFF(plane));
7253 }
7254 plane_config->base = base;
7255
7256 val = I915_READ(PIPESRC(pipe));
7257 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7258 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7259
7260 val = I915_READ(DSPSTRIDE(pipe));
7261 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
7262
7263 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7264 plane_config->tiled);
7265
7266 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7267 aligned_height);
7268
7269 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7270 pipe, plane, crtc->base.primary->fb->width,
7271 crtc->base.primary->fb->height,
7272 crtc->base.primary->fb->bits_per_pixel, base,
7273 crtc->base.primary->fb->pitches[0],
7274 plane_config->size);
7275 }
7276
7277 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7278 struct intel_crtc_config *pipe_config)
7279 {
7280 struct drm_device *dev = crtc->base.dev;
7281 struct drm_i915_private *dev_priv = dev->dev_private;
7282 uint32_t tmp;
7283
7284 if (!intel_display_power_enabled(dev_priv,
7285 POWER_DOMAIN_PIPE(crtc->pipe)))
7286 return false;
7287
7288 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7289 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7290
7291 tmp = I915_READ(PIPECONF(crtc->pipe));
7292 if (!(tmp & PIPECONF_ENABLE))
7293 return false;
7294
7295 switch (tmp & PIPECONF_BPC_MASK) {
7296 case PIPECONF_6BPC:
7297 pipe_config->pipe_bpp = 18;
7298 break;
7299 case PIPECONF_8BPC:
7300 pipe_config->pipe_bpp = 24;
7301 break;
7302 case PIPECONF_10BPC:
7303 pipe_config->pipe_bpp = 30;
7304 break;
7305 case PIPECONF_12BPC:
7306 pipe_config->pipe_bpp = 36;
7307 break;
7308 default:
7309 break;
7310 }
7311
7312 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7313 pipe_config->limited_color_range = true;
7314
7315 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7316 struct intel_shared_dpll *pll;
7317
7318 pipe_config->has_pch_encoder = true;
7319
7320 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7321 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7322 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7323
7324 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7325
7326 if (HAS_PCH_IBX(dev_priv->dev)) {
7327 pipe_config->shared_dpll =
7328 (enum intel_dpll_id) crtc->pipe;
7329 } else {
7330 tmp = I915_READ(PCH_DPLL_SEL);
7331 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7332 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7333 else
7334 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7335 }
7336
7337 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7338
7339 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7340 &pipe_config->dpll_hw_state));
7341
7342 tmp = pipe_config->dpll_hw_state.dpll;
7343 pipe_config->pixel_multiplier =
7344 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7345 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7346
7347 ironlake_pch_clock_get(crtc, pipe_config);
7348 } else {
7349 pipe_config->pixel_multiplier = 1;
7350 }
7351
7352 intel_get_pipe_timings(crtc, pipe_config);
7353
7354 ironlake_get_pfit_config(crtc, pipe_config);
7355
7356 return true;
7357 }
7358
7359 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7360 {
7361 struct drm_device *dev = dev_priv->dev;
7362 struct intel_crtc *crtc;
7363
7364 for_each_intel_crtc(dev, crtc)
7365 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7366 pipe_name(crtc->pipe));
7367
7368 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7369 WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7370 WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7371 WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7372 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7373 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7374 "CPU PWM1 enabled\n");
7375 if (IS_HASWELL(dev))
7376 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7377 "CPU PWM2 enabled\n");
7378 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7379 "PCH PWM1 enabled\n");
7380 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7381 "Utility pin enabled\n");
7382 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7383
7384 /*
7385 * In theory we can still leave IRQs enabled, as long as only the HPD
7386 * interrupts remain enabled. We used to check for that, but since it's
7387 * gen-specific and since we only disable LCPLL after we fully disable
7388 * the interrupts, the check below should be enough.
7389 */
7390 WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7391 }
7392
7393 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7394 {
7395 struct drm_device *dev = dev_priv->dev;
7396
7397 if (IS_HASWELL(dev))
7398 return I915_READ(D_COMP_HSW);
7399 else
7400 return I915_READ(D_COMP_BDW);
7401 }
7402
7403 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7404 {
7405 struct drm_device *dev = dev_priv->dev;
7406
7407 if (IS_HASWELL(dev)) {
7408 mutex_lock(&dev_priv->rps.hw_lock);
7409 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7410 val))
7411 DRM_ERROR("Failed to write to D_COMP\n");
7412 mutex_unlock(&dev_priv->rps.hw_lock);
7413 } else {
7414 I915_WRITE(D_COMP_BDW, val);
7415 POSTING_READ(D_COMP_BDW);
7416 }
7417 }
7418
7419 /*
7420 * This function implements pieces of two sequences from BSpec:
7421 * - Sequence for display software to disable LCPLL
7422 * - Sequence for display software to allow package C8+
7423 * The steps implemented here are just the steps that actually touch the LCPLL
7424 * register. Callers should take care of disabling all the display engine
7425 * functions, doing the mode unset, fixing interrupts, etc.
7426 */
7427 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7428 bool switch_to_fclk, bool allow_power_down)
7429 {
7430 uint32_t val;
7431
7432 assert_can_disable_lcpll(dev_priv);
7433
7434 val = I915_READ(LCPLL_CTL);
7435
7436 if (switch_to_fclk) {
7437 val |= LCPLL_CD_SOURCE_FCLK;
7438 I915_WRITE(LCPLL_CTL, val);
7439
7440 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7441 LCPLL_CD_SOURCE_FCLK_DONE, 1))
7442 DRM_ERROR("Switching to FCLK failed\n");
7443
7444 val = I915_READ(LCPLL_CTL);
7445 }
7446
7447 val |= LCPLL_PLL_DISABLE;
7448 I915_WRITE(LCPLL_CTL, val);
7449 POSTING_READ(LCPLL_CTL);
7450
7451 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7452 DRM_ERROR("LCPLL still locked\n");
7453
7454 val = hsw_read_dcomp(dev_priv);
7455 val |= D_COMP_COMP_DISABLE;
7456 hsw_write_dcomp(dev_priv, val);
7457 ndelay(100);
7458
7459 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7460 1))
7461 DRM_ERROR("D_COMP RCOMP still in progress\n");
7462
7463 if (allow_power_down) {
7464 val = I915_READ(LCPLL_CTL);
7465 val |= LCPLL_POWER_DOWN_ALLOW;
7466 I915_WRITE(LCPLL_CTL, val);
7467 POSTING_READ(LCPLL_CTL);
7468 }
7469 }
7470
7471 /*
7472 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7473 * source.
7474 */
7475 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7476 {
7477 uint32_t val;
7478 unsigned long irqflags;
7479
7480 val = I915_READ(LCPLL_CTL);
7481
7482 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7483 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7484 return;
7485
7486 /*
7487 * Make sure we're not on PC8 state before disabling PC8, otherwise
7488 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7489 *
7490 * The other problem is that hsw_restore_lcpll() is called as part of
7491 * the runtime PM resume sequence, so we can't just call
7492 * gen6_gt_force_wake_get() because that function calls
7493 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7494 * while we are on the resume sequence. So to solve this problem we have
7495 * to call special forcewake code that doesn't touch runtime PM and
7496 * doesn't enable the forcewake delayed work.
7497 */
7498 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7499 if (dev_priv->uncore.forcewake_count++ == 0)
7500 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7501 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7502
7503 if (val & LCPLL_POWER_DOWN_ALLOW) {
7504 val &= ~LCPLL_POWER_DOWN_ALLOW;
7505 I915_WRITE(LCPLL_CTL, val);
7506 POSTING_READ(LCPLL_CTL);
7507 }
7508
7509 val = hsw_read_dcomp(dev_priv);
7510 val |= D_COMP_COMP_FORCE;
7511 val &= ~D_COMP_COMP_DISABLE;
7512 hsw_write_dcomp(dev_priv, val);
7513
7514 val = I915_READ(LCPLL_CTL);
7515 val &= ~LCPLL_PLL_DISABLE;
7516 I915_WRITE(LCPLL_CTL, val);
7517
7518 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7519 DRM_ERROR("LCPLL not locked yet\n");
7520
7521 if (val & LCPLL_CD_SOURCE_FCLK) {
7522 val = I915_READ(LCPLL_CTL);
7523 val &= ~LCPLL_CD_SOURCE_FCLK;
7524 I915_WRITE(LCPLL_CTL, val);
7525
7526 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7527 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7528 DRM_ERROR("Switching back to LCPLL failed\n");
7529 }
7530
7531 /* See the big comment above. */
7532 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7533 if (--dev_priv->uncore.forcewake_count == 0)
7534 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7535 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7536 }
7537
7538 /*
7539 * Package states C8 and deeper are really deep PC states that can only be
7540 * reached when all the devices on the system allow it, so even if the graphics
7541 * device allows PC8+, it doesn't mean the system will actually get to these
7542 * states. Our driver only allows PC8+ when going into runtime PM.
7543 *
7544 * The requirements for PC8+ are that all the outputs are disabled, the power
7545 * well is disabled and most interrupts are disabled, and these are also
7546 * requirements for runtime PM. When these conditions are met, we manually do
7547 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7548 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7549 * hang the machine.
7550 *
7551 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7552 * the state of some registers, so when we come back from PC8+ we need to
7553 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7554 * need to take care of the registers kept by RC6. Notice that this happens even
7555 * if we don't put the device in PCI D3 state (which is what currently happens
7556 * because of the runtime PM support).
7557 *
7558 * For more, read "Display Sequences for Package C8" on the hardware
7559 * documentation.
7560 */
7561 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7562 {
7563 struct drm_device *dev = dev_priv->dev;
7564 uint32_t val;
7565
7566 DRM_DEBUG_KMS("Enabling package C8+\n");
7567
7568 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7569 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7570 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7571 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7572 }
7573
7574 lpt_disable_clkout_dp(dev);
7575 hsw_disable_lcpll(dev_priv, true, true);
7576 }
7577
7578 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7579 {
7580 struct drm_device *dev = dev_priv->dev;
7581 uint32_t val;
7582
7583 DRM_DEBUG_KMS("Disabling package C8+\n");
7584
7585 hsw_restore_lcpll(dev_priv);
7586 lpt_init_pch_refclk(dev);
7587
7588 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7589 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7590 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7591 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7592 }
7593
7594 intel_prepare_ddi(dev);
7595 }
7596
7597 static void snb_modeset_global_resources(struct drm_device *dev)
7598 {
7599 modeset_update_crtc_power_domains(dev);
7600 }
7601
7602 static void haswell_modeset_global_resources(struct drm_device *dev)
7603 {
7604 modeset_update_crtc_power_domains(dev);
7605 }
7606
7607 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7608 int x, int y,
7609 struct drm_framebuffer *fb)
7610 {
7611 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7612
7613 if (!intel_ddi_pll_select(intel_crtc))
7614 return -EINVAL;
7615
7616 intel_crtc->lowfreq_avail = false;
7617
7618 return 0;
7619 }
7620
7621 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
7622 enum port port,
7623 struct intel_crtc_config *pipe_config)
7624 {
7625 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
7626
7627 switch (pipe_config->ddi_pll_sel) {
7628 case PORT_CLK_SEL_WRPLL1:
7629 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
7630 break;
7631 case PORT_CLK_SEL_WRPLL2:
7632 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
7633 break;
7634 }
7635 }
7636
7637 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
7638 struct intel_crtc_config *pipe_config)
7639 {
7640 struct drm_device *dev = crtc->base.dev;
7641 struct drm_i915_private *dev_priv = dev->dev_private;
7642 struct intel_shared_dpll *pll;
7643 enum port port;
7644 uint32_t tmp;
7645
7646 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7647
7648 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
7649
7650 haswell_get_ddi_pll(dev_priv, port, pipe_config);
7651
7652 if (pipe_config->shared_dpll >= 0) {
7653 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7654
7655 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7656 &pipe_config->dpll_hw_state));
7657 }
7658
7659 /*
7660 * Haswell has only FDI/PCH transcoder A. It is which is connected to
7661 * DDI E. So just check whether this pipe is wired to DDI E and whether
7662 * the PCH transcoder is on.
7663 */
7664 if ((port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7665 pipe_config->has_pch_encoder = true;
7666
7667 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7668 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7669 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7670
7671 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7672 }
7673 }
7674
7675 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7676 struct intel_crtc_config *pipe_config)
7677 {
7678 struct drm_device *dev = crtc->base.dev;
7679 struct drm_i915_private *dev_priv = dev->dev_private;
7680 enum intel_display_power_domain pfit_domain;
7681 uint32_t tmp;
7682
7683 if (!intel_display_power_enabled(dev_priv,
7684 POWER_DOMAIN_PIPE(crtc->pipe)))
7685 return false;
7686
7687 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7688 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7689
7690 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7691 if (tmp & TRANS_DDI_FUNC_ENABLE) {
7692 enum pipe trans_edp_pipe;
7693 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7694 default:
7695 WARN(1, "unknown pipe linked to edp transcoder\n");
7696 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7697 case TRANS_DDI_EDP_INPUT_A_ON:
7698 trans_edp_pipe = PIPE_A;
7699 break;
7700 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7701 trans_edp_pipe = PIPE_B;
7702 break;
7703 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7704 trans_edp_pipe = PIPE_C;
7705 break;
7706 }
7707
7708 if (trans_edp_pipe == crtc->pipe)
7709 pipe_config->cpu_transcoder = TRANSCODER_EDP;
7710 }
7711
7712 if (!intel_display_power_enabled(dev_priv,
7713 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7714 return false;
7715
7716 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7717 if (!(tmp & PIPECONF_ENABLE))
7718 return false;
7719
7720 haswell_get_ddi_port_state(crtc, pipe_config);
7721
7722 intel_get_pipe_timings(crtc, pipe_config);
7723
7724 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7725 if (intel_display_power_enabled(dev_priv, pfit_domain))
7726 ironlake_get_pfit_config(crtc, pipe_config);
7727
7728 if (IS_HASWELL(dev))
7729 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7730 (I915_READ(IPS_CTL) & IPS_ENABLE);
7731
7732 pipe_config->pixel_multiplier = 1;
7733
7734 return true;
7735 }
7736
7737 static struct {
7738 int clock;
7739 u32 config;
7740 } hdmi_audio_clock[] = {
7741 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7742 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7743 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7744 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7745 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7746 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7747 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7748 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7749 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7750 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7751 };
7752
7753 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7754 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7755 {
7756 int i;
7757
7758 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7759 if (mode->clock == hdmi_audio_clock[i].clock)
7760 break;
7761 }
7762
7763 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7764 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7765 i = 1;
7766 }
7767
7768 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7769 hdmi_audio_clock[i].clock,
7770 hdmi_audio_clock[i].config);
7771
7772 return hdmi_audio_clock[i].config;
7773 }
7774
7775 static bool intel_eld_uptodate(struct drm_connector *connector,
7776 int reg_eldv, uint32_t bits_eldv,
7777 int reg_elda, uint32_t bits_elda,
7778 int reg_edid)
7779 {
7780 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7781 uint8_t *eld = connector->eld;
7782 uint32_t i;
7783
7784 i = I915_READ(reg_eldv);
7785 i &= bits_eldv;
7786
7787 if (!eld[0])
7788 return !i;
7789
7790 if (!i)
7791 return false;
7792
7793 i = I915_READ(reg_elda);
7794 i &= ~bits_elda;
7795 I915_WRITE(reg_elda, i);
7796
7797 for (i = 0; i < eld[2]; i++)
7798 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7799 return false;
7800
7801 return true;
7802 }
7803
7804 static void g4x_write_eld(struct drm_connector *connector,
7805 struct drm_crtc *crtc,
7806 struct drm_display_mode *mode)
7807 {
7808 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7809 uint8_t *eld = connector->eld;
7810 uint32_t eldv;
7811 uint32_t len;
7812 uint32_t i;
7813
7814 i = I915_READ(G4X_AUD_VID_DID);
7815
7816 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7817 eldv = G4X_ELDV_DEVCL_DEVBLC;
7818 else
7819 eldv = G4X_ELDV_DEVCTG;
7820
7821 if (intel_eld_uptodate(connector,
7822 G4X_AUD_CNTL_ST, eldv,
7823 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7824 G4X_HDMIW_HDMIEDID))
7825 return;
7826
7827 i = I915_READ(G4X_AUD_CNTL_ST);
7828 i &= ~(eldv | G4X_ELD_ADDR);
7829 len = (i >> 9) & 0x1f; /* ELD buffer size */
7830 I915_WRITE(G4X_AUD_CNTL_ST, i);
7831
7832 if (!eld[0])
7833 return;
7834
7835 len = min_t(uint8_t, eld[2], len);
7836 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7837 for (i = 0; i < len; i++)
7838 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7839
7840 i = I915_READ(G4X_AUD_CNTL_ST);
7841 i |= eldv;
7842 I915_WRITE(G4X_AUD_CNTL_ST, i);
7843 }
7844
7845 static void haswell_write_eld(struct drm_connector *connector,
7846 struct drm_crtc *crtc,
7847 struct drm_display_mode *mode)
7848 {
7849 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7850 uint8_t *eld = connector->eld;
7851 uint32_t eldv;
7852 uint32_t i;
7853 int len;
7854 int pipe = to_intel_crtc(crtc)->pipe;
7855 int tmp;
7856
7857 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7858 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7859 int aud_config = HSW_AUD_CFG(pipe);
7860 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7861
7862 /* Audio output enable */
7863 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7864 tmp = I915_READ(aud_cntrl_st2);
7865 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7866 I915_WRITE(aud_cntrl_st2, tmp);
7867 POSTING_READ(aud_cntrl_st2);
7868
7869 assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
7870
7871 /* Set ELD valid state */
7872 tmp = I915_READ(aud_cntrl_st2);
7873 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7874 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7875 I915_WRITE(aud_cntrl_st2, tmp);
7876 tmp = I915_READ(aud_cntrl_st2);
7877 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7878
7879 /* Enable HDMI mode */
7880 tmp = I915_READ(aud_config);
7881 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7882 /* clear N_programing_enable and N_value_index */
7883 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7884 I915_WRITE(aud_config, tmp);
7885
7886 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7887
7888 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7889
7890 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7891 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7892 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7893 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7894 } else {
7895 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7896 }
7897
7898 if (intel_eld_uptodate(connector,
7899 aud_cntrl_st2, eldv,
7900 aud_cntl_st, IBX_ELD_ADDRESS,
7901 hdmiw_hdmiedid))
7902 return;
7903
7904 i = I915_READ(aud_cntrl_st2);
7905 i &= ~eldv;
7906 I915_WRITE(aud_cntrl_st2, i);
7907
7908 if (!eld[0])
7909 return;
7910
7911 i = I915_READ(aud_cntl_st);
7912 i &= ~IBX_ELD_ADDRESS;
7913 I915_WRITE(aud_cntl_st, i);
7914 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
7915 DRM_DEBUG_DRIVER("port num:%d\n", i);
7916
7917 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7918 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7919 for (i = 0; i < len; i++)
7920 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7921
7922 i = I915_READ(aud_cntrl_st2);
7923 i |= eldv;
7924 I915_WRITE(aud_cntrl_st2, i);
7925
7926 }
7927
7928 static void ironlake_write_eld(struct drm_connector *connector,
7929 struct drm_crtc *crtc,
7930 struct drm_display_mode *mode)
7931 {
7932 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7933 uint8_t *eld = connector->eld;
7934 uint32_t eldv;
7935 uint32_t i;
7936 int len;
7937 int hdmiw_hdmiedid;
7938 int aud_config;
7939 int aud_cntl_st;
7940 int aud_cntrl_st2;
7941 int pipe = to_intel_crtc(crtc)->pipe;
7942
7943 if (HAS_PCH_IBX(connector->dev)) {
7944 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7945 aud_config = IBX_AUD_CFG(pipe);
7946 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7947 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7948 } else if (IS_VALLEYVIEW(connector->dev)) {
7949 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7950 aud_config = VLV_AUD_CFG(pipe);
7951 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7952 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7953 } else {
7954 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7955 aud_config = CPT_AUD_CFG(pipe);
7956 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7957 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7958 }
7959
7960 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7961
7962 if (IS_VALLEYVIEW(connector->dev)) {
7963 struct intel_encoder *intel_encoder;
7964 struct intel_digital_port *intel_dig_port;
7965
7966 intel_encoder = intel_attached_encoder(connector);
7967 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7968 i = intel_dig_port->port;
7969 } else {
7970 i = I915_READ(aud_cntl_st);
7971 i = (i >> 29) & DIP_PORT_SEL_MASK;
7972 /* DIP_Port_Select, 0x1 = PortB */
7973 }
7974
7975 if (!i) {
7976 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7977 /* operate blindly on all ports */
7978 eldv = IBX_ELD_VALIDB;
7979 eldv |= IBX_ELD_VALIDB << 4;
7980 eldv |= IBX_ELD_VALIDB << 8;
7981 } else {
7982 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7983 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7984 }
7985
7986 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7987 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7988 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7989 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7990 } else {
7991 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7992 }
7993
7994 if (intel_eld_uptodate(connector,
7995 aud_cntrl_st2, eldv,
7996 aud_cntl_st, IBX_ELD_ADDRESS,
7997 hdmiw_hdmiedid))
7998 return;
7999
8000 i = I915_READ(aud_cntrl_st2);
8001 i &= ~eldv;
8002 I915_WRITE(aud_cntrl_st2, i);
8003
8004 if (!eld[0])
8005 return;
8006
8007 i = I915_READ(aud_cntl_st);
8008 i &= ~IBX_ELD_ADDRESS;
8009 I915_WRITE(aud_cntl_st, i);
8010
8011 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
8012 DRM_DEBUG_DRIVER("ELD size %d\n", len);
8013 for (i = 0; i < len; i++)
8014 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
8015
8016 i = I915_READ(aud_cntrl_st2);
8017 i |= eldv;
8018 I915_WRITE(aud_cntrl_st2, i);
8019 }
8020
8021 void intel_write_eld(struct drm_encoder *encoder,
8022 struct drm_display_mode *mode)
8023 {
8024 struct drm_crtc *crtc = encoder->crtc;
8025 struct drm_connector *connector;
8026 struct drm_device *dev = encoder->dev;
8027 struct drm_i915_private *dev_priv = dev->dev_private;
8028
8029 connector = drm_select_eld(encoder, mode);
8030 if (!connector)
8031 return;
8032
8033 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8034 connector->base.id,
8035 connector->name,
8036 connector->encoder->base.id,
8037 connector->encoder->name);
8038
8039 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
8040
8041 if (dev_priv->display.write_eld)
8042 dev_priv->display.write_eld(connector, crtc, mode);
8043 }
8044
8045 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8046 {
8047 struct drm_device *dev = crtc->dev;
8048 struct drm_i915_private *dev_priv = dev->dev_private;
8049 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8050 uint32_t cntl;
8051
8052 if (base != intel_crtc->cursor_base) {
8053 /* On these chipsets we can only modify the base whilst
8054 * the cursor is disabled.
8055 */
8056 if (intel_crtc->cursor_cntl) {
8057 I915_WRITE(_CURACNTR, 0);
8058 POSTING_READ(_CURACNTR);
8059 intel_crtc->cursor_cntl = 0;
8060 }
8061
8062 I915_WRITE(_CURABASE, base);
8063 POSTING_READ(_CURABASE);
8064 }
8065
8066 /* XXX width must be 64, stride 256 => 0x00 << 28 */
8067 cntl = 0;
8068 if (base)
8069 cntl = (CURSOR_ENABLE |
8070 CURSOR_GAMMA_ENABLE |
8071 CURSOR_FORMAT_ARGB);
8072 if (intel_crtc->cursor_cntl != cntl) {
8073 I915_WRITE(_CURACNTR, cntl);
8074 POSTING_READ(_CURACNTR);
8075 intel_crtc->cursor_cntl = cntl;
8076 }
8077 }
8078
8079 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8080 {
8081 struct drm_device *dev = crtc->dev;
8082 struct drm_i915_private *dev_priv = dev->dev_private;
8083 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8084 int pipe = intel_crtc->pipe;
8085 uint32_t cntl;
8086
8087 cntl = 0;
8088 if (base) {
8089 cntl = MCURSOR_GAMMA_ENABLE;
8090 switch (intel_crtc->cursor_width) {
8091 case 64:
8092 cntl |= CURSOR_MODE_64_ARGB_AX;
8093 break;
8094 case 128:
8095 cntl |= CURSOR_MODE_128_ARGB_AX;
8096 break;
8097 case 256:
8098 cntl |= CURSOR_MODE_256_ARGB_AX;
8099 break;
8100 default:
8101 WARN_ON(1);
8102 return;
8103 }
8104 cntl |= pipe << 28; /* Connect to correct pipe */
8105 }
8106 if (intel_crtc->cursor_cntl != cntl) {
8107 I915_WRITE(CURCNTR(pipe), cntl);
8108 POSTING_READ(CURCNTR(pipe));
8109 intel_crtc->cursor_cntl = cntl;
8110 }
8111
8112 /* and commit changes on next vblank */
8113 I915_WRITE(CURBASE(pipe), base);
8114 POSTING_READ(CURBASE(pipe));
8115 }
8116
8117 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
8118 {
8119 struct drm_device *dev = crtc->dev;
8120 struct drm_i915_private *dev_priv = dev->dev_private;
8121 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8122 int pipe = intel_crtc->pipe;
8123 uint32_t cntl;
8124
8125 cntl = 0;
8126 if (base) {
8127 cntl = MCURSOR_GAMMA_ENABLE;
8128 switch (intel_crtc->cursor_width) {
8129 case 64:
8130 cntl |= CURSOR_MODE_64_ARGB_AX;
8131 break;
8132 case 128:
8133 cntl |= CURSOR_MODE_128_ARGB_AX;
8134 break;
8135 case 256:
8136 cntl |= CURSOR_MODE_256_ARGB_AX;
8137 break;
8138 default:
8139 WARN_ON(1);
8140 return;
8141 }
8142 }
8143 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8144 cntl |= CURSOR_PIPE_CSC_ENABLE;
8145
8146 if (intel_crtc->cursor_cntl != cntl) {
8147 I915_WRITE(CURCNTR(pipe), cntl);
8148 POSTING_READ(CURCNTR(pipe));
8149 intel_crtc->cursor_cntl = cntl;
8150 }
8151
8152 /* and commit changes on next vblank */
8153 I915_WRITE(CURBASE(pipe), base);
8154 POSTING_READ(CURBASE(pipe));
8155 }
8156
8157 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8158 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8159 bool on)
8160 {
8161 struct drm_device *dev = crtc->dev;
8162 struct drm_i915_private *dev_priv = dev->dev_private;
8163 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8164 int pipe = intel_crtc->pipe;
8165 int x = crtc->cursor_x;
8166 int y = crtc->cursor_y;
8167 u32 base = 0, pos = 0;
8168
8169 if (on)
8170 base = intel_crtc->cursor_addr;
8171
8172 if (x >= intel_crtc->config.pipe_src_w)
8173 base = 0;
8174
8175 if (y >= intel_crtc->config.pipe_src_h)
8176 base = 0;
8177
8178 if (x < 0) {
8179 if (x + intel_crtc->cursor_width <= 0)
8180 base = 0;
8181
8182 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8183 x = -x;
8184 }
8185 pos |= x << CURSOR_X_SHIFT;
8186
8187 if (y < 0) {
8188 if (y + intel_crtc->cursor_height <= 0)
8189 base = 0;
8190
8191 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8192 y = -y;
8193 }
8194 pos |= y << CURSOR_Y_SHIFT;
8195
8196 if (base == 0 && intel_crtc->cursor_base == 0)
8197 return;
8198
8199 I915_WRITE(CURPOS(pipe), pos);
8200
8201 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev))
8202 ivb_update_cursor(crtc, base);
8203 else if (IS_845G(dev) || IS_I865G(dev))
8204 i845_update_cursor(crtc, base);
8205 else
8206 i9xx_update_cursor(crtc, base);
8207 intel_crtc->cursor_base = base;
8208 }
8209
8210 /*
8211 * intel_crtc_cursor_set_obj - Set cursor to specified GEM object
8212 *
8213 * Note that the object's reference will be consumed if the update fails. If
8214 * the update succeeds, the reference of the old object (if any) will be
8215 * consumed.
8216 */
8217 static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8218 struct drm_i915_gem_object *obj,
8219 uint32_t width, uint32_t height)
8220 {
8221 struct drm_device *dev = crtc->dev;
8222 struct drm_i915_private *dev_priv = dev->dev_private;
8223 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8224 enum pipe pipe = intel_crtc->pipe;
8225 unsigned old_width;
8226 uint32_t addr;
8227 int ret;
8228
8229 /* if we want to turn off the cursor ignore width and height */
8230 if (!obj) {
8231 DRM_DEBUG_KMS("cursor off\n");
8232 addr = 0;
8233 obj = NULL;
8234 mutex_lock(&dev->struct_mutex);
8235 goto finish;
8236 }
8237
8238 /* Check for which cursor types we support */
8239 if (!((width == 64 && height == 64) ||
8240 (width == 128 && height == 128 && !IS_GEN2(dev)) ||
8241 (width == 256 && height == 256 && !IS_GEN2(dev)))) {
8242 DRM_DEBUG("Cursor dimension not supported\n");
8243 return -EINVAL;
8244 }
8245
8246 if (obj->base.size < width * height * 4) {
8247 DRM_DEBUG_KMS("buffer is too small\n");
8248 ret = -ENOMEM;
8249 goto fail;
8250 }
8251
8252 /* we only need to pin inside GTT if cursor is non-phy */
8253 mutex_lock(&dev->struct_mutex);
8254 if (!INTEL_INFO(dev)->cursor_needs_physical) {
8255 unsigned alignment;
8256
8257 if (obj->tiling_mode) {
8258 DRM_DEBUG_KMS("cursor cannot be tiled\n");
8259 ret = -EINVAL;
8260 goto fail_locked;
8261 }
8262
8263 /* Note that the w/a also requires 2 PTE of padding following
8264 * the bo. We currently fill all unused PTE with the shadow
8265 * page and so we should always have valid PTE following the
8266 * cursor preventing the VT-d warning.
8267 */
8268 alignment = 0;
8269 if (need_vtd_wa(dev))
8270 alignment = 64*1024;
8271
8272 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8273 if (ret) {
8274 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8275 goto fail_locked;
8276 }
8277
8278 ret = i915_gem_object_put_fence(obj);
8279 if (ret) {
8280 DRM_DEBUG_KMS("failed to release fence for cursor");
8281 goto fail_unpin;
8282 }
8283
8284 addr = i915_gem_obj_ggtt_offset(obj);
8285 } else {
8286 int align = IS_I830(dev) ? 16 * 1024 : 256;
8287 ret = i915_gem_object_attach_phys(obj, align);
8288 if (ret) {
8289 DRM_DEBUG_KMS("failed to attach phys object\n");
8290 goto fail_locked;
8291 }
8292 addr = obj->phys_handle->busaddr;
8293 }
8294
8295 if (IS_GEN2(dev))
8296 I915_WRITE(CURSIZE, (height << 12) | width);
8297
8298 finish:
8299 if (intel_crtc->cursor_bo) {
8300 if (!INTEL_INFO(dev)->cursor_needs_physical)
8301 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8302 }
8303
8304 i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8305 INTEL_FRONTBUFFER_CURSOR(pipe));
8306 mutex_unlock(&dev->struct_mutex);
8307
8308 old_width = intel_crtc->cursor_width;
8309
8310 intel_crtc->cursor_addr = addr;
8311 intel_crtc->cursor_bo = obj;
8312 intel_crtc->cursor_width = width;
8313 intel_crtc->cursor_height = height;
8314
8315 if (intel_crtc->active) {
8316 if (old_width != width)
8317 intel_update_watermarks(crtc);
8318 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8319 }
8320
8321 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
8322
8323 return 0;
8324 fail_unpin:
8325 i915_gem_object_unpin_from_display_plane(obj);
8326 fail_locked:
8327 mutex_unlock(&dev->struct_mutex);
8328 fail:
8329 drm_gem_object_unreference_unlocked(&obj->base);
8330 return ret;
8331 }
8332
8333 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8334 u16 *blue, uint32_t start, uint32_t size)
8335 {
8336 int end = (start + size > 256) ? 256 : start + size, i;
8337 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8338
8339 for (i = start; i < end; i++) {
8340 intel_crtc->lut_r[i] = red[i] >> 8;
8341 intel_crtc->lut_g[i] = green[i] >> 8;
8342 intel_crtc->lut_b[i] = blue[i] >> 8;
8343 }
8344
8345 intel_crtc_load_lut(crtc);
8346 }
8347
8348 /* VESA 640x480x72Hz mode to set on the pipe */
8349 static struct drm_display_mode load_detect_mode = {
8350 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8351 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8352 };
8353
8354 struct drm_framebuffer *
8355 __intel_framebuffer_create(struct drm_device *dev,
8356 struct drm_mode_fb_cmd2 *mode_cmd,
8357 struct drm_i915_gem_object *obj)
8358 {
8359 struct intel_framebuffer *intel_fb;
8360 int ret;
8361
8362 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8363 if (!intel_fb) {
8364 drm_gem_object_unreference_unlocked(&obj->base);
8365 return ERR_PTR(-ENOMEM);
8366 }
8367
8368 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8369 if (ret)
8370 goto err;
8371
8372 return &intel_fb->base;
8373 err:
8374 drm_gem_object_unreference_unlocked(&obj->base);
8375 kfree(intel_fb);
8376
8377 return ERR_PTR(ret);
8378 }
8379
8380 static struct drm_framebuffer *
8381 intel_framebuffer_create(struct drm_device *dev,
8382 struct drm_mode_fb_cmd2 *mode_cmd,
8383 struct drm_i915_gem_object *obj)
8384 {
8385 struct drm_framebuffer *fb;
8386 int ret;
8387
8388 ret = i915_mutex_lock_interruptible(dev);
8389 if (ret)
8390 return ERR_PTR(ret);
8391 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8392 mutex_unlock(&dev->struct_mutex);
8393
8394 return fb;
8395 }
8396
8397 static u32
8398 intel_framebuffer_pitch_for_width(int width, int bpp)
8399 {
8400 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8401 return ALIGN(pitch, 64);
8402 }
8403
8404 static u32
8405 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8406 {
8407 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8408 return PAGE_ALIGN(pitch * mode->vdisplay);
8409 }
8410
8411 static struct drm_framebuffer *
8412 intel_framebuffer_create_for_mode(struct drm_device *dev,
8413 struct drm_display_mode *mode,
8414 int depth, int bpp)
8415 {
8416 struct drm_i915_gem_object *obj;
8417 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8418
8419 obj = i915_gem_alloc_object(dev,
8420 intel_framebuffer_size_for_mode(mode, bpp));
8421 if (obj == NULL)
8422 return ERR_PTR(-ENOMEM);
8423
8424 mode_cmd.width = mode->hdisplay;
8425 mode_cmd.height = mode->vdisplay;
8426 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8427 bpp);
8428 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8429
8430 return intel_framebuffer_create(dev, &mode_cmd, obj);
8431 }
8432
8433 static struct drm_framebuffer *
8434 mode_fits_in_fbdev(struct drm_device *dev,
8435 struct drm_display_mode *mode)
8436 {
8437 #ifdef CONFIG_DRM_I915_FBDEV
8438 struct drm_i915_private *dev_priv = dev->dev_private;
8439 struct drm_i915_gem_object *obj;
8440 struct drm_framebuffer *fb;
8441
8442 if (!dev_priv->fbdev)
8443 return NULL;
8444
8445 if (!dev_priv->fbdev->fb)
8446 return NULL;
8447
8448 obj = dev_priv->fbdev->fb->obj;
8449 BUG_ON(!obj);
8450
8451 fb = &dev_priv->fbdev->fb->base;
8452 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8453 fb->bits_per_pixel))
8454 return NULL;
8455
8456 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8457 return NULL;
8458
8459 return fb;
8460 #else
8461 return NULL;
8462 #endif
8463 }
8464
8465 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8466 struct drm_display_mode *mode,
8467 struct intel_load_detect_pipe *old,
8468 struct drm_modeset_acquire_ctx *ctx)
8469 {
8470 struct intel_crtc *intel_crtc;
8471 struct intel_encoder *intel_encoder =
8472 intel_attached_encoder(connector);
8473 struct drm_crtc *possible_crtc;
8474 struct drm_encoder *encoder = &intel_encoder->base;
8475 struct drm_crtc *crtc = NULL;
8476 struct drm_device *dev = encoder->dev;
8477 struct drm_framebuffer *fb;
8478 struct drm_mode_config *config = &dev->mode_config;
8479 int ret, i = -1;
8480
8481 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8482 connector->base.id, connector->name,
8483 encoder->base.id, encoder->name);
8484
8485 drm_modeset_acquire_init(ctx, 0);
8486
8487 retry:
8488 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8489 if (ret)
8490 goto fail_unlock;
8491
8492 /*
8493 * Algorithm gets a little messy:
8494 *
8495 * - if the connector already has an assigned crtc, use it (but make
8496 * sure it's on first)
8497 *
8498 * - try to find the first unused crtc that can drive this connector,
8499 * and use that if we find one
8500 */
8501
8502 /* See if we already have a CRTC for this connector */
8503 if (encoder->crtc) {
8504 crtc = encoder->crtc;
8505
8506 ret = drm_modeset_lock(&crtc->mutex, ctx);
8507 if (ret)
8508 goto fail_unlock;
8509
8510 old->dpms_mode = connector->dpms;
8511 old->load_detect_temp = false;
8512
8513 /* Make sure the crtc and connector are running */
8514 if (connector->dpms != DRM_MODE_DPMS_ON)
8515 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8516
8517 return true;
8518 }
8519
8520 /* Find an unused one (if possible) */
8521 for_each_crtc(dev, possible_crtc) {
8522 i++;
8523 if (!(encoder->possible_crtcs & (1 << i)))
8524 continue;
8525 if (!possible_crtc->enabled) {
8526 crtc = possible_crtc;
8527 break;
8528 }
8529 }
8530
8531 /*
8532 * If we didn't find an unused CRTC, don't use any.
8533 */
8534 if (!crtc) {
8535 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8536 goto fail_unlock;
8537 }
8538
8539 ret = drm_modeset_lock(&crtc->mutex, ctx);
8540 if (ret)
8541 goto fail_unlock;
8542 intel_encoder->new_crtc = to_intel_crtc(crtc);
8543 to_intel_connector(connector)->new_encoder = intel_encoder;
8544
8545 intel_crtc = to_intel_crtc(crtc);
8546 intel_crtc->new_enabled = true;
8547 intel_crtc->new_config = &intel_crtc->config;
8548 old->dpms_mode = connector->dpms;
8549 old->load_detect_temp = true;
8550 old->release_fb = NULL;
8551
8552 if (!mode)
8553 mode = &load_detect_mode;
8554
8555 /* We need a framebuffer large enough to accommodate all accesses
8556 * that the plane may generate whilst we perform load detection.
8557 * We can not rely on the fbcon either being present (we get called
8558 * during its initialisation to detect all boot displays, or it may
8559 * not even exist) or that it is large enough to satisfy the
8560 * requested mode.
8561 */
8562 fb = mode_fits_in_fbdev(dev, mode);
8563 if (fb == NULL) {
8564 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8565 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8566 old->release_fb = fb;
8567 } else
8568 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8569 if (IS_ERR(fb)) {
8570 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8571 goto fail;
8572 }
8573
8574 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8575 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8576 if (old->release_fb)
8577 old->release_fb->funcs->destroy(old->release_fb);
8578 goto fail;
8579 }
8580
8581 /* let the connector get through one full cycle before testing */
8582 intel_wait_for_vblank(dev, intel_crtc->pipe);
8583 return true;
8584
8585 fail:
8586 intel_crtc->new_enabled = crtc->enabled;
8587 if (intel_crtc->new_enabled)
8588 intel_crtc->new_config = &intel_crtc->config;
8589 else
8590 intel_crtc->new_config = NULL;
8591 fail_unlock:
8592 if (ret == -EDEADLK) {
8593 drm_modeset_backoff(ctx);
8594 goto retry;
8595 }
8596
8597 drm_modeset_drop_locks(ctx);
8598 drm_modeset_acquire_fini(ctx);
8599
8600 return false;
8601 }
8602
8603 void intel_release_load_detect_pipe(struct drm_connector *connector,
8604 struct intel_load_detect_pipe *old,
8605 struct drm_modeset_acquire_ctx *ctx)
8606 {
8607 struct intel_encoder *intel_encoder =
8608 intel_attached_encoder(connector);
8609 struct drm_encoder *encoder = &intel_encoder->base;
8610 struct drm_crtc *crtc = encoder->crtc;
8611 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8612
8613 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8614 connector->base.id, connector->name,
8615 encoder->base.id, encoder->name);
8616
8617 if (old->load_detect_temp) {
8618 to_intel_connector(connector)->new_encoder = NULL;
8619 intel_encoder->new_crtc = NULL;
8620 intel_crtc->new_enabled = false;
8621 intel_crtc->new_config = NULL;
8622 intel_set_mode(crtc, NULL, 0, 0, NULL);
8623
8624 if (old->release_fb) {
8625 drm_framebuffer_unregister_private(old->release_fb);
8626 drm_framebuffer_unreference(old->release_fb);
8627 }
8628
8629 goto unlock;
8630 return;
8631 }
8632
8633 /* Switch crtc and encoder back off if necessary */
8634 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8635 connector->funcs->dpms(connector, old->dpms_mode);
8636
8637 unlock:
8638 drm_modeset_drop_locks(ctx);
8639 drm_modeset_acquire_fini(ctx);
8640 }
8641
8642 static int i9xx_pll_refclk(struct drm_device *dev,
8643 const struct intel_crtc_config *pipe_config)
8644 {
8645 struct drm_i915_private *dev_priv = dev->dev_private;
8646 u32 dpll = pipe_config->dpll_hw_state.dpll;
8647
8648 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8649 return dev_priv->vbt.lvds_ssc_freq;
8650 else if (HAS_PCH_SPLIT(dev))
8651 return 120000;
8652 else if (!IS_GEN2(dev))
8653 return 96000;
8654 else
8655 return 48000;
8656 }
8657
8658 /* Returns the clock of the currently programmed mode of the given pipe. */
8659 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8660 struct intel_crtc_config *pipe_config)
8661 {
8662 struct drm_device *dev = crtc->base.dev;
8663 struct drm_i915_private *dev_priv = dev->dev_private;
8664 int pipe = pipe_config->cpu_transcoder;
8665 u32 dpll = pipe_config->dpll_hw_state.dpll;
8666 u32 fp;
8667 intel_clock_t clock;
8668 int refclk = i9xx_pll_refclk(dev, pipe_config);
8669
8670 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8671 fp = pipe_config->dpll_hw_state.fp0;
8672 else
8673 fp = pipe_config->dpll_hw_state.fp1;
8674
8675 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8676 if (IS_PINEVIEW(dev)) {
8677 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8678 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8679 } else {
8680 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8681 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8682 }
8683
8684 if (!IS_GEN2(dev)) {
8685 if (IS_PINEVIEW(dev))
8686 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8687 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8688 else
8689 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8690 DPLL_FPA01_P1_POST_DIV_SHIFT);
8691
8692 switch (dpll & DPLL_MODE_MASK) {
8693 case DPLLB_MODE_DAC_SERIAL:
8694 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8695 5 : 10;
8696 break;
8697 case DPLLB_MODE_LVDS:
8698 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8699 7 : 14;
8700 break;
8701 default:
8702 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8703 "mode\n", (int)(dpll & DPLL_MODE_MASK));
8704 return;
8705 }
8706
8707 if (IS_PINEVIEW(dev))
8708 pineview_clock(refclk, &clock);
8709 else
8710 i9xx_clock(refclk, &clock);
8711 } else {
8712 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8713 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8714
8715 if (is_lvds) {
8716 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8717 DPLL_FPA01_P1_POST_DIV_SHIFT);
8718
8719 if (lvds & LVDS_CLKB_POWER_UP)
8720 clock.p2 = 7;
8721 else
8722 clock.p2 = 14;
8723 } else {
8724 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8725 clock.p1 = 2;
8726 else {
8727 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8728 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8729 }
8730 if (dpll & PLL_P2_DIVIDE_BY_4)
8731 clock.p2 = 4;
8732 else
8733 clock.p2 = 2;
8734 }
8735
8736 i9xx_clock(refclk, &clock);
8737 }
8738
8739 /*
8740 * This value includes pixel_multiplier. We will use
8741 * port_clock to compute adjusted_mode.crtc_clock in the
8742 * encoder's get_config() function.
8743 */
8744 pipe_config->port_clock = clock.dot;
8745 }
8746
8747 int intel_dotclock_calculate(int link_freq,
8748 const struct intel_link_m_n *m_n)
8749 {
8750 /*
8751 * The calculation for the data clock is:
8752 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8753 * But we want to avoid losing precison if possible, so:
8754 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8755 *
8756 * and the link clock is simpler:
8757 * link_clock = (m * link_clock) / n
8758 */
8759
8760 if (!m_n->link_n)
8761 return 0;
8762
8763 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8764 }
8765
8766 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8767 struct intel_crtc_config *pipe_config)
8768 {
8769 struct drm_device *dev = crtc->base.dev;
8770
8771 /* read out port_clock from the DPLL */
8772 i9xx_crtc_clock_get(crtc, pipe_config);
8773
8774 /*
8775 * This value does not include pixel_multiplier.
8776 * We will check that port_clock and adjusted_mode.crtc_clock
8777 * agree once we know their relationship in the encoder's
8778 * get_config() function.
8779 */
8780 pipe_config->adjusted_mode.crtc_clock =
8781 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8782 &pipe_config->fdi_m_n);
8783 }
8784
8785 /** Returns the currently programmed mode of the given pipe. */
8786 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8787 struct drm_crtc *crtc)
8788 {
8789 struct drm_i915_private *dev_priv = dev->dev_private;
8790 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8791 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8792 struct drm_display_mode *mode;
8793 struct intel_crtc_config pipe_config;
8794 int htot = I915_READ(HTOTAL(cpu_transcoder));
8795 int hsync = I915_READ(HSYNC(cpu_transcoder));
8796 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8797 int vsync = I915_READ(VSYNC(cpu_transcoder));
8798 enum pipe pipe = intel_crtc->pipe;
8799
8800 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8801 if (!mode)
8802 return NULL;
8803
8804 /*
8805 * Construct a pipe_config sufficient for getting the clock info
8806 * back out of crtc_clock_get.
8807 *
8808 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8809 * to use a real value here instead.
8810 */
8811 pipe_config.cpu_transcoder = (enum transcoder) pipe;
8812 pipe_config.pixel_multiplier = 1;
8813 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8814 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8815 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8816 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8817
8818 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8819 mode->hdisplay = (htot & 0xffff) + 1;
8820 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8821 mode->hsync_start = (hsync & 0xffff) + 1;
8822 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8823 mode->vdisplay = (vtot & 0xffff) + 1;
8824 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8825 mode->vsync_start = (vsync & 0xffff) + 1;
8826 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8827
8828 drm_mode_set_name(mode);
8829
8830 return mode;
8831 }
8832
8833 static void intel_increase_pllclock(struct drm_device *dev,
8834 enum pipe pipe)
8835 {
8836 struct drm_i915_private *dev_priv = dev->dev_private;
8837 int dpll_reg = DPLL(pipe);
8838 int dpll;
8839
8840 if (!HAS_GMCH_DISPLAY(dev))
8841 return;
8842
8843 if (!dev_priv->lvds_downclock_avail)
8844 return;
8845
8846 dpll = I915_READ(dpll_reg);
8847 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8848 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8849
8850 assert_panel_unlocked(dev_priv, pipe);
8851
8852 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8853 I915_WRITE(dpll_reg, dpll);
8854 intel_wait_for_vblank(dev, pipe);
8855
8856 dpll = I915_READ(dpll_reg);
8857 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8858 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8859 }
8860 }
8861
8862 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8863 {
8864 struct drm_device *dev = crtc->dev;
8865 struct drm_i915_private *dev_priv = dev->dev_private;
8866 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8867
8868 if (!HAS_GMCH_DISPLAY(dev))
8869 return;
8870
8871 if (!dev_priv->lvds_downclock_avail)
8872 return;
8873
8874 /*
8875 * Since this is called by a timer, we should never get here in
8876 * the manual case.
8877 */
8878 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8879 int pipe = intel_crtc->pipe;
8880 int dpll_reg = DPLL(pipe);
8881 int dpll;
8882
8883 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8884
8885 assert_panel_unlocked(dev_priv, pipe);
8886
8887 dpll = I915_READ(dpll_reg);
8888 dpll |= DISPLAY_RATE_SELECT_FPA1;
8889 I915_WRITE(dpll_reg, dpll);
8890 intel_wait_for_vblank(dev, pipe);
8891 dpll = I915_READ(dpll_reg);
8892 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8893 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8894 }
8895
8896 }
8897
8898 void intel_mark_busy(struct drm_device *dev)
8899 {
8900 struct drm_i915_private *dev_priv = dev->dev_private;
8901
8902 if (dev_priv->mm.busy)
8903 return;
8904
8905 intel_runtime_pm_get(dev_priv);
8906 i915_update_gfx_val(dev_priv);
8907 dev_priv->mm.busy = true;
8908 }
8909
8910 void intel_mark_idle(struct drm_device *dev)
8911 {
8912 struct drm_i915_private *dev_priv = dev->dev_private;
8913 struct drm_crtc *crtc;
8914
8915 if (!dev_priv->mm.busy)
8916 return;
8917
8918 dev_priv->mm.busy = false;
8919
8920 if (!i915.powersave)
8921 goto out;
8922
8923 for_each_crtc(dev, crtc) {
8924 if (!crtc->primary->fb)
8925 continue;
8926
8927 intel_decrease_pllclock(crtc);
8928 }
8929
8930 if (INTEL_INFO(dev)->gen >= 6)
8931 gen6_rps_idle(dev->dev_private);
8932
8933 out:
8934 intel_runtime_pm_put(dev_priv);
8935 }
8936
8937
8938 /**
8939 * intel_mark_fb_busy - mark given planes as busy
8940 * @dev: DRM device
8941 * @frontbuffer_bits: bits for the affected planes
8942 * @ring: optional ring for asynchronous commands
8943 *
8944 * This function gets called every time the screen contents change. It can be
8945 * used to keep e.g. the update rate at the nominal refresh rate with DRRS.
8946 */
8947 static void intel_mark_fb_busy(struct drm_device *dev,
8948 unsigned frontbuffer_bits,
8949 struct intel_engine_cs *ring)
8950 {
8951 enum pipe pipe;
8952
8953 if (!i915.powersave)
8954 return;
8955
8956 for_each_pipe(pipe) {
8957 if (!(frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe)))
8958 continue;
8959
8960 intel_increase_pllclock(dev, pipe);
8961 if (ring && intel_fbc_enabled(dev))
8962 ring->fbc_dirty = true;
8963 }
8964 }
8965
8966 /**
8967 * intel_fb_obj_invalidate - invalidate frontbuffer object
8968 * @obj: GEM object to invalidate
8969 * @ring: set for asynchronous rendering
8970 *
8971 * This function gets called every time rendering on the given object starts and
8972 * frontbuffer caching (fbc, low refresh rate for DRRS, panel self refresh) must
8973 * be invalidated. If @ring is non-NULL any subsequent invalidation will be delayed
8974 * until the rendering completes or a flip on this frontbuffer plane is
8975 * scheduled.
8976 */
8977 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
8978 struct intel_engine_cs *ring)
8979 {
8980 struct drm_device *dev = obj->base.dev;
8981 struct drm_i915_private *dev_priv = dev->dev_private;
8982
8983 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
8984
8985 if (!obj->frontbuffer_bits)
8986 return;
8987
8988 if (ring) {
8989 mutex_lock(&dev_priv->fb_tracking.lock);
8990 dev_priv->fb_tracking.busy_bits
8991 |= obj->frontbuffer_bits;
8992 dev_priv->fb_tracking.flip_bits
8993 &= ~obj->frontbuffer_bits;
8994 mutex_unlock(&dev_priv->fb_tracking.lock);
8995 }
8996
8997 intel_mark_fb_busy(dev, obj->frontbuffer_bits, ring);
8998
8999 intel_edp_psr_invalidate(dev, obj->frontbuffer_bits);
9000 }
9001
9002 /**
9003 * intel_frontbuffer_flush - flush frontbuffer
9004 * @dev: DRM device
9005 * @frontbuffer_bits: frontbuffer plane tracking bits
9006 *
9007 * This function gets called every time rendering on the given planes has
9008 * completed and frontbuffer caching can be started again. Flushes will get
9009 * delayed if they're blocked by some oustanding asynchronous rendering.
9010 *
9011 * Can be called without any locks held.
9012 */
9013 void intel_frontbuffer_flush(struct drm_device *dev,
9014 unsigned frontbuffer_bits)
9015 {
9016 struct drm_i915_private *dev_priv = dev->dev_private;
9017
9018 /* Delay flushing when rings are still busy.*/
9019 mutex_lock(&dev_priv->fb_tracking.lock);
9020 frontbuffer_bits &= ~dev_priv->fb_tracking.busy_bits;
9021 mutex_unlock(&dev_priv->fb_tracking.lock);
9022
9023 intel_mark_fb_busy(dev, frontbuffer_bits, NULL);
9024
9025 intel_edp_psr_flush(dev, frontbuffer_bits);
9026 }
9027
9028 /**
9029 * intel_fb_obj_flush - flush frontbuffer object
9030 * @obj: GEM object to flush
9031 * @retire: set when retiring asynchronous rendering
9032 *
9033 * This function gets called every time rendering on the given object has
9034 * completed and frontbuffer caching can be started again. If @retire is true
9035 * then any delayed flushes will be unblocked.
9036 */
9037 void intel_fb_obj_flush(struct drm_i915_gem_object *obj,
9038 bool retire)
9039 {
9040 struct drm_device *dev = obj->base.dev;
9041 struct drm_i915_private *dev_priv = dev->dev_private;
9042 unsigned frontbuffer_bits;
9043
9044 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
9045
9046 if (!obj->frontbuffer_bits)
9047 return;
9048
9049 frontbuffer_bits = obj->frontbuffer_bits;
9050
9051 if (retire) {
9052 mutex_lock(&dev_priv->fb_tracking.lock);
9053 /* Filter out new bits since rendering started. */
9054 frontbuffer_bits &= dev_priv->fb_tracking.busy_bits;
9055
9056 dev_priv->fb_tracking.busy_bits &= ~frontbuffer_bits;
9057 mutex_unlock(&dev_priv->fb_tracking.lock);
9058 }
9059
9060 intel_frontbuffer_flush(dev, frontbuffer_bits);
9061 }
9062
9063 /**
9064 * intel_frontbuffer_flip_prepare - prepare asnychronous frontbuffer flip
9065 * @dev: DRM device
9066 * @frontbuffer_bits: frontbuffer plane tracking bits
9067 *
9068 * This function gets called after scheduling a flip on @obj. The actual
9069 * frontbuffer flushing will be delayed until completion is signalled with
9070 * intel_frontbuffer_flip_complete. If an invalidate happens in between this
9071 * flush will be cancelled.
9072 *
9073 * Can be called without any locks held.
9074 */
9075 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
9076 unsigned frontbuffer_bits)
9077 {
9078 struct drm_i915_private *dev_priv = dev->dev_private;
9079
9080 mutex_lock(&dev_priv->fb_tracking.lock);
9081 dev_priv->fb_tracking.flip_bits
9082 |= frontbuffer_bits;
9083 mutex_unlock(&dev_priv->fb_tracking.lock);
9084 }
9085
9086 /**
9087 * intel_frontbuffer_flip_complete - complete asynchronous frontbuffer flush
9088 * @dev: DRM device
9089 * @frontbuffer_bits: frontbuffer plane tracking bits
9090 *
9091 * This function gets called after the flip has been latched and will complete
9092 * on the next vblank. It will execute the fush if it hasn't been cancalled yet.
9093 *
9094 * Can be called without any locks held.
9095 */
9096 void intel_frontbuffer_flip_complete(struct drm_device *dev,
9097 unsigned frontbuffer_bits)
9098 {
9099 struct drm_i915_private *dev_priv = dev->dev_private;
9100
9101 mutex_lock(&dev_priv->fb_tracking.lock);
9102 /* Mask any cancelled flips. */
9103 frontbuffer_bits &= dev_priv->fb_tracking.flip_bits;
9104 dev_priv->fb_tracking.flip_bits &= ~frontbuffer_bits;
9105 mutex_unlock(&dev_priv->fb_tracking.lock);
9106
9107 intel_frontbuffer_flush(dev, frontbuffer_bits);
9108 }
9109
9110 static void intel_crtc_destroy(struct drm_crtc *crtc)
9111 {
9112 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9113 struct drm_device *dev = crtc->dev;
9114 struct intel_unpin_work *work;
9115 unsigned long flags;
9116
9117 spin_lock_irqsave(&dev->event_lock, flags);
9118 work = intel_crtc->unpin_work;
9119 intel_crtc->unpin_work = NULL;
9120 spin_unlock_irqrestore(&dev->event_lock, flags);
9121
9122 if (work) {
9123 cancel_work_sync(&work->work);
9124 kfree(work);
9125 }
9126
9127 drm_crtc_cleanup(crtc);
9128
9129 kfree(intel_crtc);
9130 }
9131
9132 static void intel_unpin_work_fn(struct work_struct *__work)
9133 {
9134 struct intel_unpin_work *work =
9135 container_of(__work, struct intel_unpin_work, work);
9136 struct drm_device *dev = work->crtc->dev;
9137 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9138
9139 mutex_lock(&dev->struct_mutex);
9140 intel_unpin_fb_obj(work->old_fb_obj);
9141 drm_gem_object_unreference(&work->pending_flip_obj->base);
9142 drm_gem_object_unreference(&work->old_fb_obj->base);
9143
9144 intel_update_fbc(dev);
9145 mutex_unlock(&dev->struct_mutex);
9146
9147 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9148
9149 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9150 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9151
9152 kfree(work);
9153 }
9154
9155 static void do_intel_finish_page_flip(struct drm_device *dev,
9156 struct drm_crtc *crtc)
9157 {
9158 struct drm_i915_private *dev_priv = dev->dev_private;
9159 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9160 struct intel_unpin_work *work;
9161 unsigned long flags;
9162
9163 /* Ignore early vblank irqs */
9164 if (intel_crtc == NULL)
9165 return;
9166
9167 spin_lock_irqsave(&dev->event_lock, flags);
9168 work = intel_crtc->unpin_work;
9169
9170 /* Ensure we don't miss a work->pending update ... */
9171 smp_rmb();
9172
9173 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9174 spin_unlock_irqrestore(&dev->event_lock, flags);
9175 return;
9176 }
9177
9178 /* and that the unpin work is consistent wrt ->pending. */
9179 smp_rmb();
9180
9181 intel_crtc->unpin_work = NULL;
9182
9183 if (work->event)
9184 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
9185
9186 drm_crtc_vblank_put(crtc);
9187
9188 spin_unlock_irqrestore(&dev->event_lock, flags);
9189
9190 wake_up_all(&dev_priv->pending_flip_queue);
9191
9192 queue_work(dev_priv->wq, &work->work);
9193
9194 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
9195 }
9196
9197 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9198 {
9199 struct drm_i915_private *dev_priv = dev->dev_private;
9200 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9201
9202 do_intel_finish_page_flip(dev, crtc);
9203 }
9204
9205 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9206 {
9207 struct drm_i915_private *dev_priv = dev->dev_private;
9208 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9209
9210 do_intel_finish_page_flip(dev, crtc);
9211 }
9212
9213 /* Is 'a' after or equal to 'b'? */
9214 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9215 {
9216 return !((a - b) & 0x80000000);
9217 }
9218
9219 static bool page_flip_finished(struct intel_crtc *crtc)
9220 {
9221 struct drm_device *dev = crtc->base.dev;
9222 struct drm_i915_private *dev_priv = dev->dev_private;
9223
9224 /*
9225 * The relevant registers doen't exist on pre-ctg.
9226 * As the flip done interrupt doesn't trigger for mmio
9227 * flips on gmch platforms, a flip count check isn't
9228 * really needed there. But since ctg has the registers,
9229 * include it in the check anyway.
9230 */
9231 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9232 return true;
9233
9234 /*
9235 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9236 * used the same base address. In that case the mmio flip might
9237 * have completed, but the CS hasn't even executed the flip yet.
9238 *
9239 * A flip count check isn't enough as the CS might have updated
9240 * the base address just after start of vblank, but before we
9241 * managed to process the interrupt. This means we'd complete the
9242 * CS flip too soon.
9243 *
9244 * Combining both checks should get us a good enough result. It may
9245 * still happen that the CS flip has been executed, but has not
9246 * yet actually completed. But in case the base address is the same
9247 * anyway, we don't really care.
9248 */
9249 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9250 crtc->unpin_work->gtt_offset &&
9251 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9252 crtc->unpin_work->flip_count);
9253 }
9254
9255 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9256 {
9257 struct drm_i915_private *dev_priv = dev->dev_private;
9258 struct intel_crtc *intel_crtc =
9259 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9260 unsigned long flags;
9261
9262 /* NB: An MMIO update of the plane base pointer will also
9263 * generate a page-flip completion irq, i.e. every modeset
9264 * is also accompanied by a spurious intel_prepare_page_flip().
9265 */
9266 spin_lock_irqsave(&dev->event_lock, flags);
9267 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9268 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9269 spin_unlock_irqrestore(&dev->event_lock, flags);
9270 }
9271
9272 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9273 {
9274 /* Ensure that the work item is consistent when activating it ... */
9275 smp_wmb();
9276 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9277 /* and that it is marked active as soon as the irq could fire. */
9278 smp_wmb();
9279 }
9280
9281 static int intel_gen2_queue_flip(struct drm_device *dev,
9282 struct drm_crtc *crtc,
9283 struct drm_framebuffer *fb,
9284 struct drm_i915_gem_object *obj,
9285 struct intel_engine_cs *ring,
9286 uint32_t flags)
9287 {
9288 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9289 u32 flip_mask;
9290 int ret;
9291
9292 ret = intel_ring_begin(ring, 6);
9293 if (ret)
9294 return ret;
9295
9296 /* Can't queue multiple flips, so wait for the previous
9297 * one to finish before executing the next.
9298 */
9299 if (intel_crtc->plane)
9300 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9301 else
9302 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9303 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9304 intel_ring_emit(ring, MI_NOOP);
9305 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9306 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9307 intel_ring_emit(ring, fb->pitches[0]);
9308 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9309 intel_ring_emit(ring, 0); /* aux display base address, unused */
9310
9311 intel_mark_page_flip_active(intel_crtc);
9312 __intel_ring_advance(ring);
9313 return 0;
9314 }
9315
9316 static int intel_gen3_queue_flip(struct drm_device *dev,
9317 struct drm_crtc *crtc,
9318 struct drm_framebuffer *fb,
9319 struct drm_i915_gem_object *obj,
9320 struct intel_engine_cs *ring,
9321 uint32_t flags)
9322 {
9323 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9324 u32 flip_mask;
9325 int ret;
9326
9327 ret = intel_ring_begin(ring, 6);
9328 if (ret)
9329 return ret;
9330
9331 if (intel_crtc->plane)
9332 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9333 else
9334 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9335 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9336 intel_ring_emit(ring, MI_NOOP);
9337 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9338 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9339 intel_ring_emit(ring, fb->pitches[0]);
9340 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9341 intel_ring_emit(ring, MI_NOOP);
9342
9343 intel_mark_page_flip_active(intel_crtc);
9344 __intel_ring_advance(ring);
9345 return 0;
9346 }
9347
9348 static int intel_gen4_queue_flip(struct drm_device *dev,
9349 struct drm_crtc *crtc,
9350 struct drm_framebuffer *fb,
9351 struct drm_i915_gem_object *obj,
9352 struct intel_engine_cs *ring,
9353 uint32_t flags)
9354 {
9355 struct drm_i915_private *dev_priv = dev->dev_private;
9356 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9357 uint32_t pf, pipesrc;
9358 int ret;
9359
9360 ret = intel_ring_begin(ring, 4);
9361 if (ret)
9362 return ret;
9363
9364 /* i965+ uses the linear or tiled offsets from the
9365 * Display Registers (which do not change across a page-flip)
9366 * so we need only reprogram the base address.
9367 */
9368 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9369 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9370 intel_ring_emit(ring, fb->pitches[0]);
9371 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9372 obj->tiling_mode);
9373
9374 /* XXX Enabling the panel-fitter across page-flip is so far
9375 * untested on non-native modes, so ignore it for now.
9376 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9377 */
9378 pf = 0;
9379 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9380 intel_ring_emit(ring, pf | pipesrc);
9381
9382 intel_mark_page_flip_active(intel_crtc);
9383 __intel_ring_advance(ring);
9384 return 0;
9385 }
9386
9387 static int intel_gen6_queue_flip(struct drm_device *dev,
9388 struct drm_crtc *crtc,
9389 struct drm_framebuffer *fb,
9390 struct drm_i915_gem_object *obj,
9391 struct intel_engine_cs *ring,
9392 uint32_t flags)
9393 {
9394 struct drm_i915_private *dev_priv = dev->dev_private;
9395 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9396 uint32_t pf, pipesrc;
9397 int ret;
9398
9399 ret = intel_ring_begin(ring, 4);
9400 if (ret)
9401 return ret;
9402
9403 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9404 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9405 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9406 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9407
9408 /* Contrary to the suggestions in the documentation,
9409 * "Enable Panel Fitter" does not seem to be required when page
9410 * flipping with a non-native mode, and worse causes a normal
9411 * modeset to fail.
9412 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9413 */
9414 pf = 0;
9415 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9416 intel_ring_emit(ring, pf | pipesrc);
9417
9418 intel_mark_page_flip_active(intel_crtc);
9419 __intel_ring_advance(ring);
9420 return 0;
9421 }
9422
9423 static int intel_gen7_queue_flip(struct drm_device *dev,
9424 struct drm_crtc *crtc,
9425 struct drm_framebuffer *fb,
9426 struct drm_i915_gem_object *obj,
9427 struct intel_engine_cs *ring,
9428 uint32_t flags)
9429 {
9430 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9431 uint32_t plane_bit = 0;
9432 int len, ret;
9433
9434 switch (intel_crtc->plane) {
9435 case PLANE_A:
9436 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9437 break;
9438 case PLANE_B:
9439 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9440 break;
9441 case PLANE_C:
9442 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9443 break;
9444 default:
9445 WARN_ONCE(1, "unknown plane in flip command\n");
9446 return -ENODEV;
9447 }
9448
9449 len = 4;
9450 if (ring->id == RCS) {
9451 len += 6;
9452 /*
9453 * On Gen 8, SRM is now taking an extra dword to accommodate
9454 * 48bits addresses, and we need a NOOP for the batch size to
9455 * stay even.
9456 */
9457 if (IS_GEN8(dev))
9458 len += 2;
9459 }
9460
9461 /*
9462 * BSpec MI_DISPLAY_FLIP for IVB:
9463 * "The full packet must be contained within the same cache line."
9464 *
9465 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9466 * cacheline, if we ever start emitting more commands before
9467 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9468 * then do the cacheline alignment, and finally emit the
9469 * MI_DISPLAY_FLIP.
9470 */
9471 ret = intel_ring_cacheline_align(ring);
9472 if (ret)
9473 return ret;
9474
9475 ret = intel_ring_begin(ring, len);
9476 if (ret)
9477 return ret;
9478
9479 /* Unmask the flip-done completion message. Note that the bspec says that
9480 * we should do this for both the BCS and RCS, and that we must not unmask
9481 * more than one flip event at any time (or ensure that one flip message
9482 * can be sent by waiting for flip-done prior to queueing new flips).
9483 * Experimentation says that BCS works despite DERRMR masking all
9484 * flip-done completion events and that unmasking all planes at once
9485 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9486 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9487 */
9488 if (ring->id == RCS) {
9489 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9490 intel_ring_emit(ring, DERRMR);
9491 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9492 DERRMR_PIPEB_PRI_FLIP_DONE |
9493 DERRMR_PIPEC_PRI_FLIP_DONE));
9494 if (IS_GEN8(dev))
9495 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9496 MI_SRM_LRM_GLOBAL_GTT);
9497 else
9498 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9499 MI_SRM_LRM_GLOBAL_GTT);
9500 intel_ring_emit(ring, DERRMR);
9501 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9502 if (IS_GEN8(dev)) {
9503 intel_ring_emit(ring, 0);
9504 intel_ring_emit(ring, MI_NOOP);
9505 }
9506 }
9507
9508 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9509 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9510 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9511 intel_ring_emit(ring, (MI_NOOP));
9512
9513 intel_mark_page_flip_active(intel_crtc);
9514 __intel_ring_advance(ring);
9515 return 0;
9516 }
9517
9518 static bool use_mmio_flip(struct intel_engine_cs *ring,
9519 struct drm_i915_gem_object *obj)
9520 {
9521 /*
9522 * This is not being used for older platforms, because
9523 * non-availability of flip done interrupt forces us to use
9524 * CS flips. Older platforms derive flip done using some clever
9525 * tricks involving the flip_pending status bits and vblank irqs.
9526 * So using MMIO flips there would disrupt this mechanism.
9527 */
9528
9529 if (ring == NULL)
9530 return true;
9531
9532 if (INTEL_INFO(ring->dev)->gen < 5)
9533 return false;
9534
9535 if (i915.use_mmio_flip < 0)
9536 return false;
9537 else if (i915.use_mmio_flip > 0)
9538 return true;
9539 else
9540 return ring != obj->ring;
9541 }
9542
9543 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9544 {
9545 struct drm_device *dev = intel_crtc->base.dev;
9546 struct drm_i915_private *dev_priv = dev->dev_private;
9547 struct intel_framebuffer *intel_fb =
9548 to_intel_framebuffer(intel_crtc->base.primary->fb);
9549 struct drm_i915_gem_object *obj = intel_fb->obj;
9550 u32 dspcntr;
9551 u32 reg;
9552
9553 intel_mark_page_flip_active(intel_crtc);
9554
9555 reg = DSPCNTR(intel_crtc->plane);
9556 dspcntr = I915_READ(reg);
9557
9558 if (INTEL_INFO(dev)->gen >= 4) {
9559 if (obj->tiling_mode != I915_TILING_NONE)
9560 dspcntr |= DISPPLANE_TILED;
9561 else
9562 dspcntr &= ~DISPPLANE_TILED;
9563 }
9564 I915_WRITE(reg, dspcntr);
9565
9566 I915_WRITE(DSPSURF(intel_crtc->plane),
9567 intel_crtc->unpin_work->gtt_offset);
9568 POSTING_READ(DSPSURF(intel_crtc->plane));
9569 }
9570
9571 static int intel_postpone_flip(struct drm_i915_gem_object *obj)
9572 {
9573 struct intel_engine_cs *ring;
9574 int ret;
9575
9576 lockdep_assert_held(&obj->base.dev->struct_mutex);
9577
9578 if (!obj->last_write_seqno)
9579 return 0;
9580
9581 ring = obj->ring;
9582
9583 if (i915_seqno_passed(ring->get_seqno(ring, true),
9584 obj->last_write_seqno))
9585 return 0;
9586
9587 ret = i915_gem_check_olr(ring, obj->last_write_seqno);
9588 if (ret)
9589 return ret;
9590
9591 if (WARN_ON(!ring->irq_get(ring)))
9592 return 0;
9593
9594 return 1;
9595 }
9596
9597 void intel_notify_mmio_flip(struct intel_engine_cs *ring)
9598 {
9599 struct drm_i915_private *dev_priv = to_i915(ring->dev);
9600 struct intel_crtc *intel_crtc;
9601 unsigned long irq_flags;
9602 u32 seqno;
9603
9604 seqno = ring->get_seqno(ring, false);
9605
9606 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9607 for_each_intel_crtc(ring->dev, intel_crtc) {
9608 struct intel_mmio_flip *mmio_flip;
9609
9610 mmio_flip = &intel_crtc->mmio_flip;
9611 if (mmio_flip->seqno == 0)
9612 continue;
9613
9614 if (ring->id != mmio_flip->ring_id)
9615 continue;
9616
9617 if (i915_seqno_passed(seqno, mmio_flip->seqno)) {
9618 intel_do_mmio_flip(intel_crtc);
9619 mmio_flip->seqno = 0;
9620 ring->irq_put(ring);
9621 }
9622 }
9623 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9624 }
9625
9626 static int intel_queue_mmio_flip(struct drm_device *dev,
9627 struct drm_crtc *crtc,
9628 struct drm_framebuffer *fb,
9629 struct drm_i915_gem_object *obj,
9630 struct intel_engine_cs *ring,
9631 uint32_t flags)
9632 {
9633 struct drm_i915_private *dev_priv = dev->dev_private;
9634 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9635 unsigned long irq_flags;
9636 int ret;
9637
9638 if (WARN_ON(intel_crtc->mmio_flip.seqno))
9639 return -EBUSY;
9640
9641 ret = intel_postpone_flip(obj);
9642 if (ret < 0)
9643 return ret;
9644 if (ret == 0) {
9645 intel_do_mmio_flip(intel_crtc);
9646 return 0;
9647 }
9648
9649 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9650 intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
9651 intel_crtc->mmio_flip.ring_id = obj->ring->id;
9652 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9653
9654 /*
9655 * Double check to catch cases where irq fired before
9656 * mmio flip data was ready
9657 */
9658 intel_notify_mmio_flip(obj->ring);
9659 return 0;
9660 }
9661
9662 static int intel_default_queue_flip(struct drm_device *dev,
9663 struct drm_crtc *crtc,
9664 struct drm_framebuffer *fb,
9665 struct drm_i915_gem_object *obj,
9666 struct intel_engine_cs *ring,
9667 uint32_t flags)
9668 {
9669 return -ENODEV;
9670 }
9671
9672 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9673 struct drm_framebuffer *fb,
9674 struct drm_pending_vblank_event *event,
9675 uint32_t page_flip_flags)
9676 {
9677 struct drm_device *dev = crtc->dev;
9678 struct drm_i915_private *dev_priv = dev->dev_private;
9679 struct drm_framebuffer *old_fb = crtc->primary->fb;
9680 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9681 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9682 enum pipe pipe = intel_crtc->pipe;
9683 struct intel_unpin_work *work;
9684 struct intel_engine_cs *ring;
9685 unsigned long flags;
9686 int ret;
9687
9688 /*
9689 * drm_mode_page_flip_ioctl() should already catch this, but double
9690 * check to be safe. In the future we may enable pageflipping from
9691 * a disabled primary plane.
9692 */
9693 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9694 return -EBUSY;
9695
9696 /* Can't change pixel format via MI display flips. */
9697 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9698 return -EINVAL;
9699
9700 /*
9701 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9702 * Note that pitch changes could also affect these register.
9703 */
9704 if (INTEL_INFO(dev)->gen > 3 &&
9705 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9706 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9707 return -EINVAL;
9708
9709 if (i915_terminally_wedged(&dev_priv->gpu_error))
9710 goto out_hang;
9711
9712 work = kzalloc(sizeof(*work), GFP_KERNEL);
9713 if (work == NULL)
9714 return -ENOMEM;
9715
9716 work->event = event;
9717 work->crtc = crtc;
9718 work->old_fb_obj = intel_fb_obj(old_fb);
9719 INIT_WORK(&work->work, intel_unpin_work_fn);
9720
9721 ret = drm_crtc_vblank_get(crtc);
9722 if (ret)
9723 goto free_work;
9724
9725 /* We borrow the event spin lock for protecting unpin_work */
9726 spin_lock_irqsave(&dev->event_lock, flags);
9727 if (intel_crtc->unpin_work) {
9728 spin_unlock_irqrestore(&dev->event_lock, flags);
9729 kfree(work);
9730 drm_crtc_vblank_put(crtc);
9731
9732 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9733 return -EBUSY;
9734 }
9735 intel_crtc->unpin_work = work;
9736 spin_unlock_irqrestore(&dev->event_lock, flags);
9737
9738 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9739 flush_workqueue(dev_priv->wq);
9740
9741 ret = i915_mutex_lock_interruptible(dev);
9742 if (ret)
9743 goto cleanup;
9744
9745 /* Reference the objects for the scheduled work. */
9746 drm_gem_object_reference(&work->old_fb_obj->base);
9747 drm_gem_object_reference(&obj->base);
9748
9749 crtc->primary->fb = fb;
9750
9751 work->pending_flip_obj = obj;
9752
9753 work->enable_stall_check = true;
9754
9755 atomic_inc(&intel_crtc->unpin_work_count);
9756 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9757
9758 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9759 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9760
9761 if (IS_VALLEYVIEW(dev)) {
9762 ring = &dev_priv->ring[BCS];
9763 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9764 /* vlv: DISPLAY_FLIP fails to change tiling */
9765 ring = NULL;
9766 } else if (IS_IVYBRIDGE(dev)) {
9767 ring = &dev_priv->ring[BCS];
9768 } else if (INTEL_INFO(dev)->gen >= 7) {
9769 ring = obj->ring;
9770 if (ring == NULL || ring->id != RCS)
9771 ring = &dev_priv->ring[BCS];
9772 } else {
9773 ring = &dev_priv->ring[RCS];
9774 }
9775
9776 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9777 if (ret)
9778 goto cleanup_pending;
9779
9780 work->gtt_offset =
9781 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9782
9783 if (use_mmio_flip(ring, obj))
9784 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9785 page_flip_flags);
9786 else
9787 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9788 page_flip_flags);
9789 if (ret)
9790 goto cleanup_unpin;
9791
9792 i915_gem_track_fb(work->old_fb_obj, obj,
9793 INTEL_FRONTBUFFER_PRIMARY(pipe));
9794
9795 intel_disable_fbc(dev);
9796 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9797 mutex_unlock(&dev->struct_mutex);
9798
9799 trace_i915_flip_request(intel_crtc->plane, obj);
9800
9801 return 0;
9802
9803 cleanup_unpin:
9804 intel_unpin_fb_obj(obj);
9805 cleanup_pending:
9806 atomic_dec(&intel_crtc->unpin_work_count);
9807 crtc->primary->fb = old_fb;
9808 drm_gem_object_unreference(&work->old_fb_obj->base);
9809 drm_gem_object_unreference(&obj->base);
9810 mutex_unlock(&dev->struct_mutex);
9811
9812 cleanup:
9813 spin_lock_irqsave(&dev->event_lock, flags);
9814 intel_crtc->unpin_work = NULL;
9815 spin_unlock_irqrestore(&dev->event_lock, flags);
9816
9817 drm_crtc_vblank_put(crtc);
9818 free_work:
9819 kfree(work);
9820
9821 if (ret == -EIO) {
9822 out_hang:
9823 intel_crtc_wait_for_pending_flips(crtc);
9824 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9825 if (ret == 0 && event)
9826 drm_send_vblank_event(dev, pipe, event);
9827 }
9828 return ret;
9829 }
9830
9831 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9832 .mode_set_base_atomic = intel_pipe_set_base_atomic,
9833 .load_lut = intel_crtc_load_lut,
9834 };
9835
9836 /**
9837 * intel_modeset_update_staged_output_state
9838 *
9839 * Updates the staged output configuration state, e.g. after we've read out the
9840 * current hw state.
9841 */
9842 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9843 {
9844 struct intel_crtc *crtc;
9845 struct intel_encoder *encoder;
9846 struct intel_connector *connector;
9847
9848 list_for_each_entry(connector, &dev->mode_config.connector_list,
9849 base.head) {
9850 connector->new_encoder =
9851 to_intel_encoder(connector->base.encoder);
9852 }
9853
9854 for_each_intel_encoder(dev, encoder) {
9855 encoder->new_crtc =
9856 to_intel_crtc(encoder->base.crtc);
9857 }
9858
9859 for_each_intel_crtc(dev, crtc) {
9860 crtc->new_enabled = crtc->base.enabled;
9861
9862 if (crtc->new_enabled)
9863 crtc->new_config = &crtc->config;
9864 else
9865 crtc->new_config = NULL;
9866 }
9867 }
9868
9869 /**
9870 * intel_modeset_commit_output_state
9871 *
9872 * This function copies the stage display pipe configuration to the real one.
9873 */
9874 static void intel_modeset_commit_output_state(struct drm_device *dev)
9875 {
9876 struct intel_crtc *crtc;
9877 struct intel_encoder *encoder;
9878 struct intel_connector *connector;
9879
9880 list_for_each_entry(connector, &dev->mode_config.connector_list,
9881 base.head) {
9882 connector->base.encoder = &connector->new_encoder->base;
9883 }
9884
9885 for_each_intel_encoder(dev, encoder) {
9886 encoder->base.crtc = &encoder->new_crtc->base;
9887 }
9888
9889 for_each_intel_crtc(dev, crtc) {
9890 crtc->base.enabled = crtc->new_enabled;
9891 }
9892 }
9893
9894 static void
9895 connected_sink_compute_bpp(struct intel_connector *connector,
9896 struct intel_crtc_config *pipe_config)
9897 {
9898 int bpp = pipe_config->pipe_bpp;
9899
9900 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9901 connector->base.base.id,
9902 connector->base.name);
9903
9904 /* Don't use an invalid EDID bpc value */
9905 if (connector->base.display_info.bpc &&
9906 connector->base.display_info.bpc * 3 < bpp) {
9907 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9908 bpp, connector->base.display_info.bpc*3);
9909 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9910 }
9911
9912 /* Clamp bpp to 8 on screens without EDID 1.4 */
9913 if (connector->base.display_info.bpc == 0 && bpp > 24) {
9914 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9915 bpp);
9916 pipe_config->pipe_bpp = 24;
9917 }
9918 }
9919
9920 static int
9921 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9922 struct drm_framebuffer *fb,
9923 struct intel_crtc_config *pipe_config)
9924 {
9925 struct drm_device *dev = crtc->base.dev;
9926 struct intel_connector *connector;
9927 int bpp;
9928
9929 switch (fb->pixel_format) {
9930 case DRM_FORMAT_C8:
9931 bpp = 8*3; /* since we go through a colormap */
9932 break;
9933 case DRM_FORMAT_XRGB1555:
9934 case DRM_FORMAT_ARGB1555:
9935 /* checked in intel_framebuffer_init already */
9936 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9937 return -EINVAL;
9938 case DRM_FORMAT_RGB565:
9939 bpp = 6*3; /* min is 18bpp */
9940 break;
9941 case DRM_FORMAT_XBGR8888:
9942 case DRM_FORMAT_ABGR8888:
9943 /* checked in intel_framebuffer_init already */
9944 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9945 return -EINVAL;
9946 case DRM_FORMAT_XRGB8888:
9947 case DRM_FORMAT_ARGB8888:
9948 bpp = 8*3;
9949 break;
9950 case DRM_FORMAT_XRGB2101010:
9951 case DRM_FORMAT_ARGB2101010:
9952 case DRM_FORMAT_XBGR2101010:
9953 case DRM_FORMAT_ABGR2101010:
9954 /* checked in intel_framebuffer_init already */
9955 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9956 return -EINVAL;
9957 bpp = 10*3;
9958 break;
9959 /* TODO: gen4+ supports 16 bpc floating point, too. */
9960 default:
9961 DRM_DEBUG_KMS("unsupported depth\n");
9962 return -EINVAL;
9963 }
9964
9965 pipe_config->pipe_bpp = bpp;
9966
9967 /* Clamp display bpp to EDID value */
9968 list_for_each_entry(connector, &dev->mode_config.connector_list,
9969 base.head) {
9970 if (!connector->new_encoder ||
9971 connector->new_encoder->new_crtc != crtc)
9972 continue;
9973
9974 connected_sink_compute_bpp(connector, pipe_config);
9975 }
9976
9977 return bpp;
9978 }
9979
9980 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9981 {
9982 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9983 "type: 0x%x flags: 0x%x\n",
9984 mode->crtc_clock,
9985 mode->crtc_hdisplay, mode->crtc_hsync_start,
9986 mode->crtc_hsync_end, mode->crtc_htotal,
9987 mode->crtc_vdisplay, mode->crtc_vsync_start,
9988 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9989 }
9990
9991 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9992 struct intel_crtc_config *pipe_config,
9993 const char *context)
9994 {
9995 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9996 context, pipe_name(crtc->pipe));
9997
9998 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9999 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10000 pipe_config->pipe_bpp, pipe_config->dither);
10001 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10002 pipe_config->has_pch_encoder,
10003 pipe_config->fdi_lanes,
10004 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10005 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10006 pipe_config->fdi_m_n.tu);
10007 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10008 pipe_config->has_dp_encoder,
10009 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10010 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10011 pipe_config->dp_m_n.tu);
10012
10013 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10014 pipe_config->has_dp_encoder,
10015 pipe_config->dp_m2_n2.gmch_m,
10016 pipe_config->dp_m2_n2.gmch_n,
10017 pipe_config->dp_m2_n2.link_m,
10018 pipe_config->dp_m2_n2.link_n,
10019 pipe_config->dp_m2_n2.tu);
10020
10021 DRM_DEBUG_KMS("requested mode:\n");
10022 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
10023 DRM_DEBUG_KMS("adjusted mode:\n");
10024 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
10025 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
10026 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10027 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10028 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10029 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10030 pipe_config->gmch_pfit.control,
10031 pipe_config->gmch_pfit.pgm_ratios,
10032 pipe_config->gmch_pfit.lvds_border_bits);
10033 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10034 pipe_config->pch_pfit.pos,
10035 pipe_config->pch_pfit.size,
10036 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10037 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10038 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10039 }
10040
10041 static bool encoders_cloneable(const struct intel_encoder *a,
10042 const struct intel_encoder *b)
10043 {
10044 /* masks could be asymmetric, so check both ways */
10045 return a == b || (a->cloneable & (1 << b->type) &&
10046 b->cloneable & (1 << a->type));
10047 }
10048
10049 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10050 struct intel_encoder *encoder)
10051 {
10052 struct drm_device *dev = crtc->base.dev;
10053 struct intel_encoder *source_encoder;
10054
10055 for_each_intel_encoder(dev, source_encoder) {
10056 if (source_encoder->new_crtc != crtc)
10057 continue;
10058
10059 if (!encoders_cloneable(encoder, source_encoder))
10060 return false;
10061 }
10062
10063 return true;
10064 }
10065
10066 static bool check_encoder_cloning(struct intel_crtc *crtc)
10067 {
10068 struct drm_device *dev = crtc->base.dev;
10069 struct intel_encoder *encoder;
10070
10071 for_each_intel_encoder(dev, encoder) {
10072 if (encoder->new_crtc != crtc)
10073 continue;
10074
10075 if (!check_single_encoder_cloning(crtc, encoder))
10076 return false;
10077 }
10078
10079 return true;
10080 }
10081
10082 static struct intel_crtc_config *
10083 intel_modeset_pipe_config(struct drm_crtc *crtc,
10084 struct drm_framebuffer *fb,
10085 struct drm_display_mode *mode)
10086 {
10087 struct drm_device *dev = crtc->dev;
10088 struct intel_encoder *encoder;
10089 struct intel_crtc_config *pipe_config;
10090 int plane_bpp, ret = -EINVAL;
10091 bool retry = true;
10092
10093 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10094 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10095 return ERR_PTR(-EINVAL);
10096 }
10097
10098 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10099 if (!pipe_config)
10100 return ERR_PTR(-ENOMEM);
10101
10102 drm_mode_copy(&pipe_config->adjusted_mode, mode);
10103 drm_mode_copy(&pipe_config->requested_mode, mode);
10104
10105 pipe_config->cpu_transcoder =
10106 (enum transcoder) to_intel_crtc(crtc)->pipe;
10107 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10108
10109 /*
10110 * Sanitize sync polarity flags based on requested ones. If neither
10111 * positive or negative polarity is requested, treat this as meaning
10112 * negative polarity.
10113 */
10114 if (!(pipe_config->adjusted_mode.flags &
10115 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10116 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10117
10118 if (!(pipe_config->adjusted_mode.flags &
10119 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10120 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10121
10122 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10123 * plane pixel format and any sink constraints into account. Returns the
10124 * source plane bpp so that dithering can be selected on mismatches
10125 * after encoders and crtc also have had their say. */
10126 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10127 fb, pipe_config);
10128 if (plane_bpp < 0)
10129 goto fail;
10130
10131 /*
10132 * Determine the real pipe dimensions. Note that stereo modes can
10133 * increase the actual pipe size due to the frame doubling and
10134 * insertion of additional space for blanks between the frame. This
10135 * is stored in the crtc timings. We use the requested mode to do this
10136 * computation to clearly distinguish it from the adjusted mode, which
10137 * can be changed by the connectors in the below retry loop.
10138 */
10139 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
10140 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
10141 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
10142
10143 encoder_retry:
10144 /* Ensure the port clock defaults are reset when retrying. */
10145 pipe_config->port_clock = 0;
10146 pipe_config->pixel_multiplier = 1;
10147
10148 /* Fill in default crtc timings, allow encoders to overwrite them. */
10149 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
10150
10151 /* Pass our mode to the connectors and the CRTC to give them a chance to
10152 * adjust it according to limitations or connector properties, and also
10153 * a chance to reject the mode entirely.
10154 */
10155 for_each_intel_encoder(dev, encoder) {
10156
10157 if (&encoder->new_crtc->base != crtc)
10158 continue;
10159
10160 if (!(encoder->compute_config(encoder, pipe_config))) {
10161 DRM_DEBUG_KMS("Encoder config failure\n");
10162 goto fail;
10163 }
10164 }
10165
10166 /* Set default port clock if not overwritten by the encoder. Needs to be
10167 * done afterwards in case the encoder adjusts the mode. */
10168 if (!pipe_config->port_clock)
10169 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10170 * pipe_config->pixel_multiplier;
10171
10172 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10173 if (ret < 0) {
10174 DRM_DEBUG_KMS("CRTC fixup failed\n");
10175 goto fail;
10176 }
10177
10178 if (ret == RETRY) {
10179 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10180 ret = -EINVAL;
10181 goto fail;
10182 }
10183
10184 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10185 retry = false;
10186 goto encoder_retry;
10187 }
10188
10189 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10190 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10191 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10192
10193 return pipe_config;
10194 fail:
10195 kfree(pipe_config);
10196 return ERR_PTR(ret);
10197 }
10198
10199 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10200 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10201 static void
10202 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10203 unsigned *prepare_pipes, unsigned *disable_pipes)
10204 {
10205 struct intel_crtc *intel_crtc;
10206 struct drm_device *dev = crtc->dev;
10207 struct intel_encoder *encoder;
10208 struct intel_connector *connector;
10209 struct drm_crtc *tmp_crtc;
10210
10211 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10212
10213 /* Check which crtcs have changed outputs connected to them, these need
10214 * to be part of the prepare_pipes mask. We don't (yet) support global
10215 * modeset across multiple crtcs, so modeset_pipes will only have one
10216 * bit set at most. */
10217 list_for_each_entry(connector, &dev->mode_config.connector_list,
10218 base.head) {
10219 if (connector->base.encoder == &connector->new_encoder->base)
10220 continue;
10221
10222 if (connector->base.encoder) {
10223 tmp_crtc = connector->base.encoder->crtc;
10224
10225 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10226 }
10227
10228 if (connector->new_encoder)
10229 *prepare_pipes |=
10230 1 << connector->new_encoder->new_crtc->pipe;
10231 }
10232
10233 for_each_intel_encoder(dev, encoder) {
10234 if (encoder->base.crtc == &encoder->new_crtc->base)
10235 continue;
10236
10237 if (encoder->base.crtc) {
10238 tmp_crtc = encoder->base.crtc;
10239
10240 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10241 }
10242
10243 if (encoder->new_crtc)
10244 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10245 }
10246
10247 /* Check for pipes that will be enabled/disabled ... */
10248 for_each_intel_crtc(dev, intel_crtc) {
10249 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10250 continue;
10251
10252 if (!intel_crtc->new_enabled)
10253 *disable_pipes |= 1 << intel_crtc->pipe;
10254 else
10255 *prepare_pipes |= 1 << intel_crtc->pipe;
10256 }
10257
10258
10259 /* set_mode is also used to update properties on life display pipes. */
10260 intel_crtc = to_intel_crtc(crtc);
10261 if (intel_crtc->new_enabled)
10262 *prepare_pipes |= 1 << intel_crtc->pipe;
10263
10264 /*
10265 * For simplicity do a full modeset on any pipe where the output routing
10266 * changed. We could be more clever, but that would require us to be
10267 * more careful with calling the relevant encoder->mode_set functions.
10268 */
10269 if (*prepare_pipes)
10270 *modeset_pipes = *prepare_pipes;
10271
10272 /* ... and mask these out. */
10273 *modeset_pipes &= ~(*disable_pipes);
10274 *prepare_pipes &= ~(*disable_pipes);
10275
10276 /*
10277 * HACK: We don't (yet) fully support global modesets. intel_set_config
10278 * obies this rule, but the modeset restore mode of
10279 * intel_modeset_setup_hw_state does not.
10280 */
10281 *modeset_pipes &= 1 << intel_crtc->pipe;
10282 *prepare_pipes &= 1 << intel_crtc->pipe;
10283
10284 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10285 *modeset_pipes, *prepare_pipes, *disable_pipes);
10286 }
10287
10288 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10289 {
10290 struct drm_encoder *encoder;
10291 struct drm_device *dev = crtc->dev;
10292
10293 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10294 if (encoder->crtc == crtc)
10295 return true;
10296
10297 return false;
10298 }
10299
10300 static void
10301 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10302 {
10303 struct intel_encoder *intel_encoder;
10304 struct intel_crtc *intel_crtc;
10305 struct drm_connector *connector;
10306
10307 for_each_intel_encoder(dev, intel_encoder) {
10308 if (!intel_encoder->base.crtc)
10309 continue;
10310
10311 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10312
10313 if (prepare_pipes & (1 << intel_crtc->pipe))
10314 intel_encoder->connectors_active = false;
10315 }
10316
10317 intel_modeset_commit_output_state(dev);
10318
10319 /* Double check state. */
10320 for_each_intel_crtc(dev, intel_crtc) {
10321 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10322 WARN_ON(intel_crtc->new_config &&
10323 intel_crtc->new_config != &intel_crtc->config);
10324 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10325 }
10326
10327 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10328 if (!connector->encoder || !connector->encoder->crtc)
10329 continue;
10330
10331 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10332
10333 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10334 struct drm_property *dpms_property =
10335 dev->mode_config.dpms_property;
10336
10337 connector->dpms = DRM_MODE_DPMS_ON;
10338 drm_object_property_set_value(&connector->base,
10339 dpms_property,
10340 DRM_MODE_DPMS_ON);
10341
10342 intel_encoder = to_intel_encoder(connector->encoder);
10343 intel_encoder->connectors_active = true;
10344 }
10345 }
10346
10347 }
10348
10349 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10350 {
10351 int diff;
10352
10353 if (clock1 == clock2)
10354 return true;
10355
10356 if (!clock1 || !clock2)
10357 return false;
10358
10359 diff = abs(clock1 - clock2);
10360
10361 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10362 return true;
10363
10364 return false;
10365 }
10366
10367 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10368 list_for_each_entry((intel_crtc), \
10369 &(dev)->mode_config.crtc_list, \
10370 base.head) \
10371 if (mask & (1 <<(intel_crtc)->pipe))
10372
10373 static bool
10374 intel_pipe_config_compare(struct drm_device *dev,
10375 struct intel_crtc_config *current_config,
10376 struct intel_crtc_config *pipe_config)
10377 {
10378 #define PIPE_CONF_CHECK_X(name) \
10379 if (current_config->name != pipe_config->name) { \
10380 DRM_ERROR("mismatch in " #name " " \
10381 "(expected 0x%08x, found 0x%08x)\n", \
10382 current_config->name, \
10383 pipe_config->name); \
10384 return false; \
10385 }
10386
10387 #define PIPE_CONF_CHECK_I(name) \
10388 if (current_config->name != pipe_config->name) { \
10389 DRM_ERROR("mismatch in " #name " " \
10390 "(expected %i, found %i)\n", \
10391 current_config->name, \
10392 pipe_config->name); \
10393 return false; \
10394 }
10395
10396 /* This is required for BDW+ where there is only one set of registers for
10397 * switching between high and low RR.
10398 * This macro can be used whenever a comparison has to be made between one
10399 * hw state and multiple sw state variables.
10400 */
10401 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10402 if ((current_config->name != pipe_config->name) && \
10403 (current_config->alt_name != pipe_config->name)) { \
10404 DRM_ERROR("mismatch in " #name " " \
10405 "(expected %i or %i, found %i)\n", \
10406 current_config->name, \
10407 current_config->alt_name, \
10408 pipe_config->name); \
10409 return false; \
10410 }
10411
10412 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10413 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10414 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10415 "(expected %i, found %i)\n", \
10416 current_config->name & (mask), \
10417 pipe_config->name & (mask)); \
10418 return false; \
10419 }
10420
10421 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10422 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10423 DRM_ERROR("mismatch in " #name " " \
10424 "(expected %i, found %i)\n", \
10425 current_config->name, \
10426 pipe_config->name); \
10427 return false; \
10428 }
10429
10430 #define PIPE_CONF_QUIRK(quirk) \
10431 ((current_config->quirks | pipe_config->quirks) & (quirk))
10432
10433 PIPE_CONF_CHECK_I(cpu_transcoder);
10434
10435 PIPE_CONF_CHECK_I(has_pch_encoder);
10436 PIPE_CONF_CHECK_I(fdi_lanes);
10437 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10438 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10439 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10440 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10441 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10442
10443 PIPE_CONF_CHECK_I(has_dp_encoder);
10444
10445 if (INTEL_INFO(dev)->gen < 8) {
10446 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10447 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10448 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10449 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10450 PIPE_CONF_CHECK_I(dp_m_n.tu);
10451
10452 if (current_config->has_drrs) {
10453 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10454 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10455 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10456 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10457 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10458 }
10459 } else {
10460 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10461 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10462 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10463 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10464 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10465 }
10466
10467 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10468 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10469 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10470 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10471 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10472 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10473
10474 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10475 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10476 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10477 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10478 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10479 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10480
10481 PIPE_CONF_CHECK_I(pixel_multiplier);
10482 PIPE_CONF_CHECK_I(has_hdmi_sink);
10483 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10484 IS_VALLEYVIEW(dev))
10485 PIPE_CONF_CHECK_I(limited_color_range);
10486
10487 PIPE_CONF_CHECK_I(has_audio);
10488
10489 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10490 DRM_MODE_FLAG_INTERLACE);
10491
10492 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10493 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10494 DRM_MODE_FLAG_PHSYNC);
10495 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10496 DRM_MODE_FLAG_NHSYNC);
10497 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10498 DRM_MODE_FLAG_PVSYNC);
10499 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10500 DRM_MODE_FLAG_NVSYNC);
10501 }
10502
10503 PIPE_CONF_CHECK_I(pipe_src_w);
10504 PIPE_CONF_CHECK_I(pipe_src_h);
10505
10506 /*
10507 * FIXME: BIOS likes to set up a cloned config with lvds+external
10508 * screen. Since we don't yet re-compute the pipe config when moving
10509 * just the lvds port away to another pipe the sw tracking won't match.
10510 *
10511 * Proper atomic modesets with recomputed global state will fix this.
10512 * Until then just don't check gmch state for inherited modes.
10513 */
10514 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10515 PIPE_CONF_CHECK_I(gmch_pfit.control);
10516 /* pfit ratios are autocomputed by the hw on gen4+ */
10517 if (INTEL_INFO(dev)->gen < 4)
10518 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10519 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10520 }
10521
10522 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10523 if (current_config->pch_pfit.enabled) {
10524 PIPE_CONF_CHECK_I(pch_pfit.pos);
10525 PIPE_CONF_CHECK_I(pch_pfit.size);
10526 }
10527
10528 /* BDW+ don't expose a synchronous way to read the state */
10529 if (IS_HASWELL(dev))
10530 PIPE_CONF_CHECK_I(ips_enabled);
10531
10532 PIPE_CONF_CHECK_I(double_wide);
10533
10534 PIPE_CONF_CHECK_X(ddi_pll_sel);
10535
10536 PIPE_CONF_CHECK_I(shared_dpll);
10537 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10538 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10539 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10540 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10541 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10542
10543 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10544 PIPE_CONF_CHECK_I(pipe_bpp);
10545
10546 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10547 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10548
10549 #undef PIPE_CONF_CHECK_X
10550 #undef PIPE_CONF_CHECK_I
10551 #undef PIPE_CONF_CHECK_I_ALT
10552 #undef PIPE_CONF_CHECK_FLAGS
10553 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10554 #undef PIPE_CONF_QUIRK
10555
10556 return true;
10557 }
10558
10559 static void
10560 check_connector_state(struct drm_device *dev)
10561 {
10562 struct intel_connector *connector;
10563
10564 list_for_each_entry(connector, &dev->mode_config.connector_list,
10565 base.head) {
10566 /* This also checks the encoder/connector hw state with the
10567 * ->get_hw_state callbacks. */
10568 intel_connector_check_state(connector);
10569
10570 WARN(&connector->new_encoder->base != connector->base.encoder,
10571 "connector's staged encoder doesn't match current encoder\n");
10572 }
10573 }
10574
10575 static void
10576 check_encoder_state(struct drm_device *dev)
10577 {
10578 struct intel_encoder *encoder;
10579 struct intel_connector *connector;
10580
10581 for_each_intel_encoder(dev, encoder) {
10582 bool enabled = false;
10583 bool active = false;
10584 enum pipe pipe, tracked_pipe;
10585
10586 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10587 encoder->base.base.id,
10588 encoder->base.name);
10589
10590 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10591 "encoder's stage crtc doesn't match current crtc\n");
10592 WARN(encoder->connectors_active && !encoder->base.crtc,
10593 "encoder's active_connectors set, but no crtc\n");
10594
10595 list_for_each_entry(connector, &dev->mode_config.connector_list,
10596 base.head) {
10597 if (connector->base.encoder != &encoder->base)
10598 continue;
10599 enabled = true;
10600 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10601 active = true;
10602 }
10603 /*
10604 * for MST connectors if we unplug the connector is gone
10605 * away but the encoder is still connected to a crtc
10606 * until a modeset happens in response to the hotplug.
10607 */
10608 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10609 continue;
10610
10611 WARN(!!encoder->base.crtc != enabled,
10612 "encoder's enabled state mismatch "
10613 "(expected %i, found %i)\n",
10614 !!encoder->base.crtc, enabled);
10615 WARN(active && !encoder->base.crtc,
10616 "active encoder with no crtc\n");
10617
10618 WARN(encoder->connectors_active != active,
10619 "encoder's computed active state doesn't match tracked active state "
10620 "(expected %i, found %i)\n", active, encoder->connectors_active);
10621
10622 active = encoder->get_hw_state(encoder, &pipe);
10623 WARN(active != encoder->connectors_active,
10624 "encoder's hw state doesn't match sw tracking "
10625 "(expected %i, found %i)\n",
10626 encoder->connectors_active, active);
10627
10628 if (!encoder->base.crtc)
10629 continue;
10630
10631 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10632 WARN(active && pipe != tracked_pipe,
10633 "active encoder's pipe doesn't match"
10634 "(expected %i, found %i)\n",
10635 tracked_pipe, pipe);
10636
10637 }
10638 }
10639
10640 static void
10641 check_crtc_state(struct drm_device *dev)
10642 {
10643 struct drm_i915_private *dev_priv = dev->dev_private;
10644 struct intel_crtc *crtc;
10645 struct intel_encoder *encoder;
10646 struct intel_crtc_config pipe_config;
10647
10648 for_each_intel_crtc(dev, crtc) {
10649 bool enabled = false;
10650 bool active = false;
10651
10652 memset(&pipe_config, 0, sizeof(pipe_config));
10653
10654 DRM_DEBUG_KMS("[CRTC:%d]\n",
10655 crtc->base.base.id);
10656
10657 WARN(crtc->active && !crtc->base.enabled,
10658 "active crtc, but not enabled in sw tracking\n");
10659
10660 for_each_intel_encoder(dev, encoder) {
10661 if (encoder->base.crtc != &crtc->base)
10662 continue;
10663 enabled = true;
10664 if (encoder->connectors_active)
10665 active = true;
10666 }
10667
10668 WARN(active != crtc->active,
10669 "crtc's computed active state doesn't match tracked active state "
10670 "(expected %i, found %i)\n", active, crtc->active);
10671 WARN(enabled != crtc->base.enabled,
10672 "crtc's computed enabled state doesn't match tracked enabled state "
10673 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10674
10675 active = dev_priv->display.get_pipe_config(crtc,
10676 &pipe_config);
10677
10678 /* hw state is inconsistent with the pipe A quirk */
10679 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
10680 active = crtc->active;
10681
10682 for_each_intel_encoder(dev, encoder) {
10683 enum pipe pipe;
10684 if (encoder->base.crtc != &crtc->base)
10685 continue;
10686 if (encoder->get_hw_state(encoder, &pipe))
10687 encoder->get_config(encoder, &pipe_config);
10688 }
10689
10690 WARN(crtc->active != active,
10691 "crtc active state doesn't match with hw state "
10692 "(expected %i, found %i)\n", crtc->active, active);
10693
10694 if (active &&
10695 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10696 WARN(1, "pipe state doesn't match!\n");
10697 intel_dump_pipe_config(crtc, &pipe_config,
10698 "[hw state]");
10699 intel_dump_pipe_config(crtc, &crtc->config,
10700 "[sw state]");
10701 }
10702 }
10703 }
10704
10705 static void
10706 check_shared_dpll_state(struct drm_device *dev)
10707 {
10708 struct drm_i915_private *dev_priv = dev->dev_private;
10709 struct intel_crtc *crtc;
10710 struct intel_dpll_hw_state dpll_hw_state;
10711 int i;
10712
10713 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10714 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10715 int enabled_crtcs = 0, active_crtcs = 0;
10716 bool active;
10717
10718 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10719
10720 DRM_DEBUG_KMS("%s\n", pll->name);
10721
10722 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10723
10724 WARN(pll->active > pll->refcount,
10725 "more active pll users than references: %i vs %i\n",
10726 pll->active, pll->refcount);
10727 WARN(pll->active && !pll->on,
10728 "pll in active use but not on in sw tracking\n");
10729 WARN(pll->on && !pll->active,
10730 "pll in on but not on in use in sw tracking\n");
10731 WARN(pll->on != active,
10732 "pll on state mismatch (expected %i, found %i)\n",
10733 pll->on, active);
10734
10735 for_each_intel_crtc(dev, crtc) {
10736 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10737 enabled_crtcs++;
10738 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10739 active_crtcs++;
10740 }
10741 WARN(pll->active != active_crtcs,
10742 "pll active crtcs mismatch (expected %i, found %i)\n",
10743 pll->active, active_crtcs);
10744 WARN(pll->refcount != enabled_crtcs,
10745 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10746 pll->refcount, enabled_crtcs);
10747
10748 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
10749 sizeof(dpll_hw_state)),
10750 "pll hw state mismatch\n");
10751 }
10752 }
10753
10754 void
10755 intel_modeset_check_state(struct drm_device *dev)
10756 {
10757 check_connector_state(dev);
10758 check_encoder_state(dev);
10759 check_crtc_state(dev);
10760 check_shared_dpll_state(dev);
10761 }
10762
10763 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10764 int dotclock)
10765 {
10766 /*
10767 * FDI already provided one idea for the dotclock.
10768 * Yell if the encoder disagrees.
10769 */
10770 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10771 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10772 pipe_config->adjusted_mode.crtc_clock, dotclock);
10773 }
10774
10775 static void update_scanline_offset(struct intel_crtc *crtc)
10776 {
10777 struct drm_device *dev = crtc->base.dev;
10778
10779 /*
10780 * The scanline counter increments at the leading edge of hsync.
10781 *
10782 * On most platforms it starts counting from vtotal-1 on the
10783 * first active line. That means the scanline counter value is
10784 * always one less than what we would expect. Ie. just after
10785 * start of vblank, which also occurs at start of hsync (on the
10786 * last active line), the scanline counter will read vblank_start-1.
10787 *
10788 * On gen2 the scanline counter starts counting from 1 instead
10789 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10790 * to keep the value positive), instead of adding one.
10791 *
10792 * On HSW+ the behaviour of the scanline counter depends on the output
10793 * type. For DP ports it behaves like most other platforms, but on HDMI
10794 * there's an extra 1 line difference. So we need to add two instead of
10795 * one to the value.
10796 */
10797 if (IS_GEN2(dev)) {
10798 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
10799 int vtotal;
10800
10801 vtotal = mode->crtc_vtotal;
10802 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10803 vtotal /= 2;
10804
10805 crtc->scanline_offset = vtotal - 1;
10806 } else if (HAS_DDI(dev) &&
10807 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {
10808 crtc->scanline_offset = 2;
10809 } else
10810 crtc->scanline_offset = 1;
10811 }
10812
10813 static int __intel_set_mode(struct drm_crtc *crtc,
10814 struct drm_display_mode *mode,
10815 int x, int y, struct drm_framebuffer *fb)
10816 {
10817 struct drm_device *dev = crtc->dev;
10818 struct drm_i915_private *dev_priv = dev->dev_private;
10819 struct drm_display_mode *saved_mode;
10820 struct intel_crtc_config *pipe_config = NULL;
10821 struct intel_crtc *intel_crtc;
10822 unsigned disable_pipes, prepare_pipes, modeset_pipes;
10823 int ret = 0;
10824
10825 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10826 if (!saved_mode)
10827 return -ENOMEM;
10828
10829 intel_modeset_affected_pipes(crtc, &modeset_pipes,
10830 &prepare_pipes, &disable_pipes);
10831
10832 *saved_mode = crtc->mode;
10833
10834 /* Hack: Because we don't (yet) support global modeset on multiple
10835 * crtcs, we don't keep track of the new mode for more than one crtc.
10836 * Hence simply check whether any bit is set in modeset_pipes in all the
10837 * pieces of code that are not yet converted to deal with mutliple crtcs
10838 * changing their mode at the same time. */
10839 if (modeset_pipes) {
10840 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10841 if (IS_ERR(pipe_config)) {
10842 ret = PTR_ERR(pipe_config);
10843 pipe_config = NULL;
10844
10845 goto out;
10846 }
10847 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10848 "[modeset]");
10849 to_intel_crtc(crtc)->new_config = pipe_config;
10850 }
10851
10852 /*
10853 * See if the config requires any additional preparation, e.g.
10854 * to adjust global state with pipes off. We need to do this
10855 * here so we can get the modeset_pipe updated config for the new
10856 * mode set on this crtc. For other crtcs we need to use the
10857 * adjusted_mode bits in the crtc directly.
10858 */
10859 if (IS_VALLEYVIEW(dev)) {
10860 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10861
10862 /* may have added more to prepare_pipes than we should */
10863 prepare_pipes &= ~disable_pipes;
10864 }
10865
10866 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10867 intel_crtc_disable(&intel_crtc->base);
10868
10869 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10870 if (intel_crtc->base.enabled)
10871 dev_priv->display.crtc_disable(&intel_crtc->base);
10872 }
10873
10874 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10875 * to set it here already despite that we pass it down the callchain.
10876 */
10877 if (modeset_pipes) {
10878 crtc->mode = *mode;
10879 /* mode_set/enable/disable functions rely on a correct pipe
10880 * config. */
10881 to_intel_crtc(crtc)->config = *pipe_config;
10882 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10883
10884 /*
10885 * Calculate and store various constants which
10886 * are later needed by vblank and swap-completion
10887 * timestamping. They are derived from true hwmode.
10888 */
10889 drm_calc_timestamping_constants(crtc,
10890 &pipe_config->adjusted_mode);
10891 }
10892
10893 /* Only after disabling all output pipelines that will be changed can we
10894 * update the the output configuration. */
10895 intel_modeset_update_state(dev, prepare_pipes);
10896
10897 if (dev_priv->display.modeset_global_resources)
10898 dev_priv->display.modeset_global_resources(dev);
10899
10900 /* Set up the DPLL and any encoders state that needs to adjust or depend
10901 * on the DPLL.
10902 */
10903 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10904 struct drm_framebuffer *old_fb = crtc->primary->fb;
10905 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
10906 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10907
10908 mutex_lock(&dev->struct_mutex);
10909 ret = intel_pin_and_fence_fb_obj(dev,
10910 obj,
10911 NULL);
10912 if (ret != 0) {
10913 DRM_ERROR("pin & fence failed\n");
10914 mutex_unlock(&dev->struct_mutex);
10915 goto done;
10916 }
10917 if (old_fb)
10918 intel_unpin_fb_obj(old_obj);
10919 i915_gem_track_fb(old_obj, obj,
10920 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
10921 mutex_unlock(&dev->struct_mutex);
10922
10923 crtc->primary->fb = fb;
10924 crtc->x = x;
10925 crtc->y = y;
10926
10927 ret = dev_priv->display.crtc_mode_set(&intel_crtc->base,
10928 x, y, fb);
10929 if (ret)
10930 goto done;
10931 }
10932
10933 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10934 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10935 update_scanline_offset(intel_crtc);
10936
10937 dev_priv->display.crtc_enable(&intel_crtc->base);
10938 }
10939
10940 /* FIXME: add subpixel order */
10941 done:
10942 if (ret && crtc->enabled)
10943 crtc->mode = *saved_mode;
10944
10945 out:
10946 kfree(pipe_config);
10947 kfree(saved_mode);
10948 return ret;
10949 }
10950
10951 static int intel_set_mode(struct drm_crtc *crtc,
10952 struct drm_display_mode *mode,
10953 int x, int y, struct drm_framebuffer *fb)
10954 {
10955 int ret;
10956
10957 ret = __intel_set_mode(crtc, mode, x, y, fb);
10958
10959 if (ret == 0)
10960 intel_modeset_check_state(crtc->dev);
10961
10962 return ret;
10963 }
10964
10965 void intel_crtc_restore_mode(struct drm_crtc *crtc)
10966 {
10967 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
10968 }
10969
10970 #undef for_each_intel_crtc_masked
10971
10972 static void intel_set_config_free(struct intel_set_config *config)
10973 {
10974 if (!config)
10975 return;
10976
10977 kfree(config->save_connector_encoders);
10978 kfree(config->save_encoder_crtcs);
10979 kfree(config->save_crtc_enabled);
10980 kfree(config);
10981 }
10982
10983 static int intel_set_config_save_state(struct drm_device *dev,
10984 struct intel_set_config *config)
10985 {
10986 struct drm_crtc *crtc;
10987 struct drm_encoder *encoder;
10988 struct drm_connector *connector;
10989 int count;
10990
10991 config->save_crtc_enabled =
10992 kcalloc(dev->mode_config.num_crtc,
10993 sizeof(bool), GFP_KERNEL);
10994 if (!config->save_crtc_enabled)
10995 return -ENOMEM;
10996
10997 config->save_encoder_crtcs =
10998 kcalloc(dev->mode_config.num_encoder,
10999 sizeof(struct drm_crtc *), GFP_KERNEL);
11000 if (!config->save_encoder_crtcs)
11001 return -ENOMEM;
11002
11003 config->save_connector_encoders =
11004 kcalloc(dev->mode_config.num_connector,
11005 sizeof(struct drm_encoder *), GFP_KERNEL);
11006 if (!config->save_connector_encoders)
11007 return -ENOMEM;
11008
11009 /* Copy data. Note that driver private data is not affected.
11010 * Should anything bad happen only the expected state is
11011 * restored, not the drivers personal bookkeeping.
11012 */
11013 count = 0;
11014 for_each_crtc(dev, crtc) {
11015 config->save_crtc_enabled[count++] = crtc->enabled;
11016 }
11017
11018 count = 0;
11019 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11020 config->save_encoder_crtcs[count++] = encoder->crtc;
11021 }
11022
11023 count = 0;
11024 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11025 config->save_connector_encoders[count++] = connector->encoder;
11026 }
11027
11028 return 0;
11029 }
11030
11031 static void intel_set_config_restore_state(struct drm_device *dev,
11032 struct intel_set_config *config)
11033 {
11034 struct intel_crtc *crtc;
11035 struct intel_encoder *encoder;
11036 struct intel_connector *connector;
11037 int count;
11038
11039 count = 0;
11040 for_each_intel_crtc(dev, crtc) {
11041 crtc->new_enabled = config->save_crtc_enabled[count++];
11042
11043 if (crtc->new_enabled)
11044 crtc->new_config = &crtc->config;
11045 else
11046 crtc->new_config = NULL;
11047 }
11048
11049 count = 0;
11050 for_each_intel_encoder(dev, encoder) {
11051 encoder->new_crtc =
11052 to_intel_crtc(config->save_encoder_crtcs[count++]);
11053 }
11054
11055 count = 0;
11056 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11057 connector->new_encoder =
11058 to_intel_encoder(config->save_connector_encoders[count++]);
11059 }
11060 }
11061
11062 static bool
11063 is_crtc_connector_off(struct drm_mode_set *set)
11064 {
11065 int i;
11066
11067 if (set->num_connectors == 0)
11068 return false;
11069
11070 if (WARN_ON(set->connectors == NULL))
11071 return false;
11072
11073 for (i = 0; i < set->num_connectors; i++)
11074 if (set->connectors[i]->encoder &&
11075 set->connectors[i]->encoder->crtc == set->crtc &&
11076 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11077 return true;
11078
11079 return false;
11080 }
11081
11082 static void
11083 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11084 struct intel_set_config *config)
11085 {
11086
11087 /* We should be able to check here if the fb has the same properties
11088 * and then just flip_or_move it */
11089 if (is_crtc_connector_off(set)) {
11090 config->mode_changed = true;
11091 } else if (set->crtc->primary->fb != set->fb) {
11092 /*
11093 * If we have no fb, we can only flip as long as the crtc is
11094 * active, otherwise we need a full mode set. The crtc may
11095 * be active if we've only disabled the primary plane, or
11096 * in fastboot situations.
11097 */
11098 if (set->crtc->primary->fb == NULL) {
11099 struct intel_crtc *intel_crtc =
11100 to_intel_crtc(set->crtc);
11101
11102 if (intel_crtc->active) {
11103 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11104 config->fb_changed = true;
11105 } else {
11106 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11107 config->mode_changed = true;
11108 }
11109 } else if (set->fb == NULL) {
11110 config->mode_changed = true;
11111 } else if (set->fb->pixel_format !=
11112 set->crtc->primary->fb->pixel_format) {
11113 config->mode_changed = true;
11114 } else {
11115 config->fb_changed = true;
11116 }
11117 }
11118
11119 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11120 config->fb_changed = true;
11121
11122 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11123 DRM_DEBUG_KMS("modes are different, full mode set\n");
11124 drm_mode_debug_printmodeline(&set->crtc->mode);
11125 drm_mode_debug_printmodeline(set->mode);
11126 config->mode_changed = true;
11127 }
11128
11129 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11130 set->crtc->base.id, config->mode_changed, config->fb_changed);
11131 }
11132
11133 static int
11134 intel_modeset_stage_output_state(struct drm_device *dev,
11135 struct drm_mode_set *set,
11136 struct intel_set_config *config)
11137 {
11138 struct intel_connector *connector;
11139 struct intel_encoder *encoder;
11140 struct intel_crtc *crtc;
11141 int ro;
11142
11143 /* The upper layers ensure that we either disable a crtc or have a list
11144 * of connectors. For paranoia, double-check this. */
11145 WARN_ON(!set->fb && (set->num_connectors != 0));
11146 WARN_ON(set->fb && (set->num_connectors == 0));
11147
11148 list_for_each_entry(connector, &dev->mode_config.connector_list,
11149 base.head) {
11150 /* Otherwise traverse passed in connector list and get encoders
11151 * for them. */
11152 for (ro = 0; ro < set->num_connectors; ro++) {
11153 if (set->connectors[ro] == &connector->base) {
11154 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11155 break;
11156 }
11157 }
11158
11159 /* If we disable the crtc, disable all its connectors. Also, if
11160 * the connector is on the changing crtc but not on the new
11161 * connector list, disable it. */
11162 if ((!set->fb || ro == set->num_connectors) &&
11163 connector->base.encoder &&
11164 connector->base.encoder->crtc == set->crtc) {
11165 connector->new_encoder = NULL;
11166
11167 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11168 connector->base.base.id,
11169 connector->base.name);
11170 }
11171
11172
11173 if (&connector->new_encoder->base != connector->base.encoder) {
11174 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11175 config->mode_changed = true;
11176 }
11177 }
11178 /* connector->new_encoder is now updated for all connectors. */
11179
11180 /* Update crtc of enabled connectors. */
11181 list_for_each_entry(connector, &dev->mode_config.connector_list,
11182 base.head) {
11183 struct drm_crtc *new_crtc;
11184
11185 if (!connector->new_encoder)
11186 continue;
11187
11188 new_crtc = connector->new_encoder->base.crtc;
11189
11190 for (ro = 0; ro < set->num_connectors; ro++) {
11191 if (set->connectors[ro] == &connector->base)
11192 new_crtc = set->crtc;
11193 }
11194
11195 /* Make sure the new CRTC will work with the encoder */
11196 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11197 new_crtc)) {
11198 return -EINVAL;
11199 }
11200 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11201
11202 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11203 connector->base.base.id,
11204 connector->base.name,
11205 new_crtc->base.id);
11206 }
11207
11208 /* Check for any encoders that needs to be disabled. */
11209 for_each_intel_encoder(dev, encoder) {
11210 int num_connectors = 0;
11211 list_for_each_entry(connector,
11212 &dev->mode_config.connector_list,
11213 base.head) {
11214 if (connector->new_encoder == encoder) {
11215 WARN_ON(!connector->new_encoder->new_crtc);
11216 num_connectors++;
11217 }
11218 }
11219
11220 if (num_connectors == 0)
11221 encoder->new_crtc = NULL;
11222 else if (num_connectors > 1)
11223 return -EINVAL;
11224
11225 /* Only now check for crtc changes so we don't miss encoders
11226 * that will be disabled. */
11227 if (&encoder->new_crtc->base != encoder->base.crtc) {
11228 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11229 config->mode_changed = true;
11230 }
11231 }
11232 /* Now we've also updated encoder->new_crtc for all encoders. */
11233 list_for_each_entry(connector, &dev->mode_config.connector_list,
11234 base.head) {
11235 if (connector->new_encoder)
11236 if (connector->new_encoder != connector->encoder)
11237 connector->encoder = connector->new_encoder;
11238 }
11239 for_each_intel_crtc(dev, crtc) {
11240 crtc->new_enabled = false;
11241
11242 for_each_intel_encoder(dev, encoder) {
11243 if (encoder->new_crtc == crtc) {
11244 crtc->new_enabled = true;
11245 break;
11246 }
11247 }
11248
11249 if (crtc->new_enabled != crtc->base.enabled) {
11250 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11251 crtc->new_enabled ? "en" : "dis");
11252 config->mode_changed = true;
11253 }
11254
11255 if (crtc->new_enabled)
11256 crtc->new_config = &crtc->config;
11257 else
11258 crtc->new_config = NULL;
11259 }
11260
11261 return 0;
11262 }
11263
11264 static void disable_crtc_nofb(struct intel_crtc *crtc)
11265 {
11266 struct drm_device *dev = crtc->base.dev;
11267 struct intel_encoder *encoder;
11268 struct intel_connector *connector;
11269
11270 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11271 pipe_name(crtc->pipe));
11272
11273 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11274 if (connector->new_encoder &&
11275 connector->new_encoder->new_crtc == crtc)
11276 connector->new_encoder = NULL;
11277 }
11278
11279 for_each_intel_encoder(dev, encoder) {
11280 if (encoder->new_crtc == crtc)
11281 encoder->new_crtc = NULL;
11282 }
11283
11284 crtc->new_enabled = false;
11285 crtc->new_config = NULL;
11286 }
11287
11288 static int intel_crtc_set_config(struct drm_mode_set *set)
11289 {
11290 struct drm_device *dev;
11291 struct drm_mode_set save_set;
11292 struct intel_set_config *config;
11293 int ret;
11294
11295 BUG_ON(!set);
11296 BUG_ON(!set->crtc);
11297 BUG_ON(!set->crtc->helper_private);
11298
11299 /* Enforce sane interface api - has been abused by the fb helper. */
11300 BUG_ON(!set->mode && set->fb);
11301 BUG_ON(set->fb && set->num_connectors == 0);
11302
11303 if (set->fb) {
11304 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11305 set->crtc->base.id, set->fb->base.id,
11306 (int)set->num_connectors, set->x, set->y);
11307 } else {
11308 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11309 }
11310
11311 dev = set->crtc->dev;
11312
11313 ret = -ENOMEM;
11314 config = kzalloc(sizeof(*config), GFP_KERNEL);
11315 if (!config)
11316 goto out_config;
11317
11318 ret = intel_set_config_save_state(dev, config);
11319 if (ret)
11320 goto out_config;
11321
11322 save_set.crtc = set->crtc;
11323 save_set.mode = &set->crtc->mode;
11324 save_set.x = set->crtc->x;
11325 save_set.y = set->crtc->y;
11326 save_set.fb = set->crtc->primary->fb;
11327
11328 /* Compute whether we need a full modeset, only an fb base update or no
11329 * change at all. In the future we might also check whether only the
11330 * mode changed, e.g. for LVDS where we only change the panel fitter in
11331 * such cases. */
11332 intel_set_config_compute_mode_changes(set, config);
11333
11334 ret = intel_modeset_stage_output_state(dev, set, config);
11335 if (ret)
11336 goto fail;
11337
11338 if (config->mode_changed) {
11339 ret = intel_set_mode(set->crtc, set->mode,
11340 set->x, set->y, set->fb);
11341 } else if (config->fb_changed) {
11342 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11343
11344 intel_crtc_wait_for_pending_flips(set->crtc);
11345
11346 ret = intel_pipe_set_base(set->crtc,
11347 set->x, set->y, set->fb);
11348
11349 /*
11350 * We need to make sure the primary plane is re-enabled if it
11351 * has previously been turned off.
11352 */
11353 if (!intel_crtc->primary_enabled && ret == 0) {
11354 WARN_ON(!intel_crtc->active);
11355 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11356 }
11357
11358 /*
11359 * In the fastboot case this may be our only check of the
11360 * state after boot. It would be better to only do it on
11361 * the first update, but we don't have a nice way of doing that
11362 * (and really, set_config isn't used much for high freq page
11363 * flipping, so increasing its cost here shouldn't be a big
11364 * deal).
11365 */
11366 if (i915.fastboot && ret == 0)
11367 intel_modeset_check_state(set->crtc->dev);
11368 }
11369
11370 if (ret) {
11371 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11372 set->crtc->base.id, ret);
11373 fail:
11374 intel_set_config_restore_state(dev, config);
11375
11376 /*
11377 * HACK: if the pipe was on, but we didn't have a framebuffer,
11378 * force the pipe off to avoid oopsing in the modeset code
11379 * due to fb==NULL. This should only happen during boot since
11380 * we don't yet reconstruct the FB from the hardware state.
11381 */
11382 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11383 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11384
11385 /* Try to restore the config */
11386 if (config->mode_changed &&
11387 intel_set_mode(save_set.crtc, save_set.mode,
11388 save_set.x, save_set.y, save_set.fb))
11389 DRM_ERROR("failed to restore config after modeset failure\n");
11390 }
11391
11392 out_config:
11393 intel_set_config_free(config);
11394 return ret;
11395 }
11396
11397 static const struct drm_crtc_funcs intel_crtc_funcs = {
11398 .gamma_set = intel_crtc_gamma_set,
11399 .set_config = intel_crtc_set_config,
11400 .destroy = intel_crtc_destroy,
11401 .page_flip = intel_crtc_page_flip,
11402 };
11403
11404 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11405 struct intel_shared_dpll *pll,
11406 struct intel_dpll_hw_state *hw_state)
11407 {
11408 uint32_t val;
11409
11410 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_PLLS))
11411 return false;
11412
11413 val = I915_READ(PCH_DPLL(pll->id));
11414 hw_state->dpll = val;
11415 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11416 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11417
11418 return val & DPLL_VCO_ENABLE;
11419 }
11420
11421 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11422 struct intel_shared_dpll *pll)
11423 {
11424 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
11425 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
11426 }
11427
11428 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11429 struct intel_shared_dpll *pll)
11430 {
11431 /* PCH refclock must be enabled first */
11432 ibx_assert_pch_refclk_enabled(dev_priv);
11433
11434 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11435
11436 /* Wait for the clocks to stabilize. */
11437 POSTING_READ(PCH_DPLL(pll->id));
11438 udelay(150);
11439
11440 /* The pixel multiplier can only be updated once the
11441 * DPLL is enabled and the clocks are stable.
11442 *
11443 * So write it again.
11444 */
11445 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11446 POSTING_READ(PCH_DPLL(pll->id));
11447 udelay(200);
11448 }
11449
11450 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11451 struct intel_shared_dpll *pll)
11452 {
11453 struct drm_device *dev = dev_priv->dev;
11454 struct intel_crtc *crtc;
11455
11456 /* Make sure no transcoder isn't still depending on us. */
11457 for_each_intel_crtc(dev, crtc) {
11458 if (intel_crtc_to_shared_dpll(crtc) == pll)
11459 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11460 }
11461
11462 I915_WRITE(PCH_DPLL(pll->id), 0);
11463 POSTING_READ(PCH_DPLL(pll->id));
11464 udelay(200);
11465 }
11466
11467 static char *ibx_pch_dpll_names[] = {
11468 "PCH DPLL A",
11469 "PCH DPLL B",
11470 };
11471
11472 static void ibx_pch_dpll_init(struct drm_device *dev)
11473 {
11474 struct drm_i915_private *dev_priv = dev->dev_private;
11475 int i;
11476
11477 dev_priv->num_shared_dpll = 2;
11478
11479 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11480 dev_priv->shared_dplls[i].id = i;
11481 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11482 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11483 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11484 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11485 dev_priv->shared_dplls[i].get_hw_state =
11486 ibx_pch_dpll_get_hw_state;
11487 }
11488 }
11489
11490 static void intel_shared_dpll_init(struct drm_device *dev)
11491 {
11492 struct drm_i915_private *dev_priv = dev->dev_private;
11493
11494 if (HAS_DDI(dev))
11495 intel_ddi_pll_init(dev);
11496 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11497 ibx_pch_dpll_init(dev);
11498 else
11499 dev_priv->num_shared_dpll = 0;
11500
11501 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11502 }
11503
11504 static int
11505 intel_primary_plane_disable(struct drm_plane *plane)
11506 {
11507 struct drm_device *dev = plane->dev;
11508 struct intel_crtc *intel_crtc;
11509
11510 if (!plane->fb)
11511 return 0;
11512
11513 BUG_ON(!plane->crtc);
11514
11515 intel_crtc = to_intel_crtc(plane->crtc);
11516
11517 /*
11518 * Even though we checked plane->fb above, it's still possible that
11519 * the primary plane has been implicitly disabled because the crtc
11520 * coordinates given weren't visible, or because we detected
11521 * that it was 100% covered by a sprite plane. Or, the CRTC may be
11522 * off and we've set a fb, but haven't actually turned on the CRTC yet.
11523 * In either case, we need to unpin the FB and let the fb pointer get
11524 * updated, but otherwise we don't need to touch the hardware.
11525 */
11526 if (!intel_crtc->primary_enabled)
11527 goto disable_unpin;
11528
11529 intel_crtc_wait_for_pending_flips(plane->crtc);
11530 intel_disable_primary_hw_plane(plane, plane->crtc);
11531
11532 disable_unpin:
11533 mutex_lock(&dev->struct_mutex);
11534 i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
11535 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11536 intel_unpin_fb_obj(intel_fb_obj(plane->fb));
11537 mutex_unlock(&dev->struct_mutex);
11538 plane->fb = NULL;
11539
11540 return 0;
11541 }
11542
11543 static int
11544 intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11545 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11546 unsigned int crtc_w, unsigned int crtc_h,
11547 uint32_t src_x, uint32_t src_y,
11548 uint32_t src_w, uint32_t src_h)
11549 {
11550 struct drm_device *dev = crtc->dev;
11551 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11552 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11553 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11554 struct drm_rect dest = {
11555 /* integer pixels */
11556 .x1 = crtc_x,
11557 .y1 = crtc_y,
11558 .x2 = crtc_x + crtc_w,
11559 .y2 = crtc_y + crtc_h,
11560 };
11561 struct drm_rect src = {
11562 /* 16.16 fixed point */
11563 .x1 = src_x,
11564 .y1 = src_y,
11565 .x2 = src_x + src_w,
11566 .y2 = src_y + src_h,
11567 };
11568 const struct drm_rect clip = {
11569 /* integer pixels */
11570 .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
11571 .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
11572 };
11573 bool visible;
11574 int ret;
11575
11576 ret = drm_plane_helper_check_update(plane, crtc, fb,
11577 &src, &dest, &clip,
11578 DRM_PLANE_HELPER_NO_SCALING,
11579 DRM_PLANE_HELPER_NO_SCALING,
11580 false, true, &visible);
11581
11582 if (ret)
11583 return ret;
11584
11585 /*
11586 * If the CRTC isn't enabled, we're just pinning the framebuffer,
11587 * updating the fb pointer, and returning without touching the
11588 * hardware. This allows us to later do a drmModeSetCrtc with fb=-1 to
11589 * turn on the display with all planes setup as desired.
11590 */
11591 if (!crtc->enabled) {
11592 mutex_lock(&dev->struct_mutex);
11593
11594 /*
11595 * If we already called setplane while the crtc was disabled,
11596 * we may have an fb pinned; unpin it.
11597 */
11598 if (plane->fb)
11599 intel_unpin_fb_obj(old_obj);
11600
11601 i915_gem_track_fb(old_obj, obj,
11602 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11603
11604 /* Pin and return without programming hardware */
11605 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11606 mutex_unlock(&dev->struct_mutex);
11607
11608 return ret;
11609 }
11610
11611 intel_crtc_wait_for_pending_flips(crtc);
11612
11613 /*
11614 * If clipping results in a non-visible primary plane, we'll disable
11615 * the primary plane. Note that this is a bit different than what
11616 * happens if userspace explicitly disables the plane by passing fb=0
11617 * because plane->fb still gets set and pinned.
11618 */
11619 if (!visible) {
11620 mutex_lock(&dev->struct_mutex);
11621
11622 /*
11623 * Try to pin the new fb first so that we can bail out if we
11624 * fail.
11625 */
11626 if (plane->fb != fb) {
11627 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11628 if (ret) {
11629 mutex_unlock(&dev->struct_mutex);
11630 return ret;
11631 }
11632 }
11633
11634 i915_gem_track_fb(old_obj, obj,
11635 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11636
11637 if (intel_crtc->primary_enabled)
11638 intel_disable_primary_hw_plane(plane, crtc);
11639
11640
11641 if (plane->fb != fb)
11642 if (plane->fb)
11643 intel_unpin_fb_obj(old_obj);
11644
11645 mutex_unlock(&dev->struct_mutex);
11646
11647 return 0;
11648 }
11649
11650 ret = intel_pipe_set_base(crtc, src.x1, src.y1, fb);
11651 if (ret)
11652 return ret;
11653
11654 if (!intel_crtc->primary_enabled)
11655 intel_enable_primary_hw_plane(plane, crtc);
11656
11657 return 0;
11658 }
11659
11660 /* Common destruction function for both primary and cursor planes */
11661 static void intel_plane_destroy(struct drm_plane *plane)
11662 {
11663 struct intel_plane *intel_plane = to_intel_plane(plane);
11664 drm_plane_cleanup(plane);
11665 kfree(intel_plane);
11666 }
11667
11668 static const struct drm_plane_funcs intel_primary_plane_funcs = {
11669 .update_plane = intel_primary_plane_setplane,
11670 .disable_plane = intel_primary_plane_disable,
11671 .destroy = intel_plane_destroy,
11672 };
11673
11674 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11675 int pipe)
11676 {
11677 struct intel_plane *primary;
11678 const uint32_t *intel_primary_formats;
11679 int num_formats;
11680
11681 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11682 if (primary == NULL)
11683 return NULL;
11684
11685 primary->can_scale = false;
11686 primary->max_downscale = 1;
11687 primary->pipe = pipe;
11688 primary->plane = pipe;
11689 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11690 primary->plane = !pipe;
11691
11692 if (INTEL_INFO(dev)->gen <= 3) {
11693 intel_primary_formats = intel_primary_formats_gen2;
11694 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
11695 } else {
11696 intel_primary_formats = intel_primary_formats_gen4;
11697 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
11698 }
11699
11700 drm_universal_plane_init(dev, &primary->base, 0,
11701 &intel_primary_plane_funcs,
11702 intel_primary_formats, num_formats,
11703 DRM_PLANE_TYPE_PRIMARY);
11704 return &primary->base;
11705 }
11706
11707 static int
11708 intel_cursor_plane_disable(struct drm_plane *plane)
11709 {
11710 if (!plane->fb)
11711 return 0;
11712
11713 BUG_ON(!plane->crtc);
11714
11715 return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
11716 }
11717
11718 static int
11719 intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
11720 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11721 unsigned int crtc_w, unsigned int crtc_h,
11722 uint32_t src_x, uint32_t src_y,
11723 uint32_t src_w, uint32_t src_h)
11724 {
11725 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11726 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11727 struct drm_i915_gem_object *obj = intel_fb->obj;
11728 struct drm_rect dest = {
11729 /* integer pixels */
11730 .x1 = crtc_x,
11731 .y1 = crtc_y,
11732 .x2 = crtc_x + crtc_w,
11733 .y2 = crtc_y + crtc_h,
11734 };
11735 struct drm_rect src = {
11736 /* 16.16 fixed point */
11737 .x1 = src_x,
11738 .y1 = src_y,
11739 .x2 = src_x + src_w,
11740 .y2 = src_y + src_h,
11741 };
11742 const struct drm_rect clip = {
11743 /* integer pixels */
11744 .x2 = intel_crtc->config.pipe_src_w,
11745 .y2 = intel_crtc->config.pipe_src_h,
11746 };
11747 bool visible;
11748 int ret;
11749
11750 ret = drm_plane_helper_check_update(plane, crtc, fb,
11751 &src, &dest, &clip,
11752 DRM_PLANE_HELPER_NO_SCALING,
11753 DRM_PLANE_HELPER_NO_SCALING,
11754 true, true, &visible);
11755 if (ret)
11756 return ret;
11757
11758 crtc->cursor_x = crtc_x;
11759 crtc->cursor_y = crtc_y;
11760 if (fb != crtc->cursor->fb) {
11761 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
11762 } else {
11763 intel_crtc_update_cursor(crtc, visible);
11764 return 0;
11765 }
11766 }
11767 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
11768 .update_plane = intel_cursor_plane_update,
11769 .disable_plane = intel_cursor_plane_disable,
11770 .destroy = intel_plane_destroy,
11771 };
11772
11773 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
11774 int pipe)
11775 {
11776 struct intel_plane *cursor;
11777
11778 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
11779 if (cursor == NULL)
11780 return NULL;
11781
11782 cursor->can_scale = false;
11783 cursor->max_downscale = 1;
11784 cursor->pipe = pipe;
11785 cursor->plane = pipe;
11786
11787 drm_universal_plane_init(dev, &cursor->base, 0,
11788 &intel_cursor_plane_funcs,
11789 intel_cursor_formats,
11790 ARRAY_SIZE(intel_cursor_formats),
11791 DRM_PLANE_TYPE_CURSOR);
11792 return &cursor->base;
11793 }
11794
11795 static void intel_crtc_init(struct drm_device *dev, int pipe)
11796 {
11797 struct drm_i915_private *dev_priv = dev->dev_private;
11798 struct intel_crtc *intel_crtc;
11799 struct drm_plane *primary = NULL;
11800 struct drm_plane *cursor = NULL;
11801 int i, ret;
11802
11803 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
11804 if (intel_crtc == NULL)
11805 return;
11806
11807 primary = intel_primary_plane_create(dev, pipe);
11808 if (!primary)
11809 goto fail;
11810
11811 cursor = intel_cursor_plane_create(dev, pipe);
11812 if (!cursor)
11813 goto fail;
11814
11815 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
11816 cursor, &intel_crtc_funcs);
11817 if (ret)
11818 goto fail;
11819
11820 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
11821 for (i = 0; i < 256; i++) {
11822 intel_crtc->lut_r[i] = i;
11823 intel_crtc->lut_g[i] = i;
11824 intel_crtc->lut_b[i] = i;
11825 }
11826
11827 /*
11828 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
11829 * is hooked to pipe B. Hence we want plane A feeding pipe B.
11830 */
11831 intel_crtc->pipe = pipe;
11832 intel_crtc->plane = pipe;
11833 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
11834 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
11835 intel_crtc->plane = !pipe;
11836 }
11837
11838 intel_crtc->cursor_base = ~0;
11839 intel_crtc->cursor_cntl = ~0;
11840
11841 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
11842 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
11843 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
11844 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
11845
11846 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
11847
11848 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
11849 return;
11850
11851 fail:
11852 if (primary)
11853 drm_plane_cleanup(primary);
11854 if (cursor)
11855 drm_plane_cleanup(cursor);
11856 kfree(intel_crtc);
11857 }
11858
11859 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
11860 {
11861 struct drm_encoder *encoder = connector->base.encoder;
11862 struct drm_device *dev = connector->base.dev;
11863
11864 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
11865
11866 if (!encoder)
11867 return INVALID_PIPE;
11868
11869 return to_intel_crtc(encoder->crtc)->pipe;
11870 }
11871
11872 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
11873 struct drm_file *file)
11874 {
11875 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
11876 struct drm_crtc *drmmode_crtc;
11877 struct intel_crtc *crtc;
11878
11879 if (!drm_core_check_feature(dev, DRIVER_MODESET))
11880 return -ENODEV;
11881
11882 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
11883
11884 if (!drmmode_crtc) {
11885 DRM_ERROR("no such CRTC id\n");
11886 return -ENOENT;
11887 }
11888
11889 crtc = to_intel_crtc(drmmode_crtc);
11890 pipe_from_crtc_id->pipe = crtc->pipe;
11891
11892 return 0;
11893 }
11894
11895 static int intel_encoder_clones(struct intel_encoder *encoder)
11896 {
11897 struct drm_device *dev = encoder->base.dev;
11898 struct intel_encoder *source_encoder;
11899 int index_mask = 0;
11900 int entry = 0;
11901
11902 for_each_intel_encoder(dev, source_encoder) {
11903 if (encoders_cloneable(encoder, source_encoder))
11904 index_mask |= (1 << entry);
11905
11906 entry++;
11907 }
11908
11909 return index_mask;
11910 }
11911
11912 static bool has_edp_a(struct drm_device *dev)
11913 {
11914 struct drm_i915_private *dev_priv = dev->dev_private;
11915
11916 if (!IS_MOBILE(dev))
11917 return false;
11918
11919 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
11920 return false;
11921
11922 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
11923 return false;
11924
11925 return true;
11926 }
11927
11928 const char *intel_output_name(int output)
11929 {
11930 static const char *names[] = {
11931 [INTEL_OUTPUT_UNUSED] = "Unused",
11932 [INTEL_OUTPUT_ANALOG] = "Analog",
11933 [INTEL_OUTPUT_DVO] = "DVO",
11934 [INTEL_OUTPUT_SDVO] = "SDVO",
11935 [INTEL_OUTPUT_LVDS] = "LVDS",
11936 [INTEL_OUTPUT_TVOUT] = "TV",
11937 [INTEL_OUTPUT_HDMI] = "HDMI",
11938 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
11939 [INTEL_OUTPUT_EDP] = "eDP",
11940 [INTEL_OUTPUT_DSI] = "DSI",
11941 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
11942 };
11943
11944 if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
11945 return "Invalid";
11946
11947 return names[output];
11948 }
11949
11950 static bool intel_crt_present(struct drm_device *dev)
11951 {
11952 struct drm_i915_private *dev_priv = dev->dev_private;
11953
11954 if (IS_ULT(dev))
11955 return false;
11956
11957 if (IS_CHERRYVIEW(dev))
11958 return false;
11959
11960 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
11961 return false;
11962
11963 return true;
11964 }
11965
11966 static void intel_setup_outputs(struct drm_device *dev)
11967 {
11968 struct drm_i915_private *dev_priv = dev->dev_private;
11969 struct intel_encoder *encoder;
11970 bool dpd_is_edp = false;
11971
11972 intel_lvds_init(dev);
11973
11974 if (intel_crt_present(dev))
11975 intel_crt_init(dev);
11976
11977 if (HAS_DDI(dev)) {
11978 int found;
11979
11980 /* Haswell uses DDI functions to detect digital outputs */
11981 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
11982 /* DDI A only supports eDP */
11983 if (found)
11984 intel_ddi_init(dev, PORT_A);
11985
11986 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
11987 * register */
11988 found = I915_READ(SFUSE_STRAP);
11989
11990 if (found & SFUSE_STRAP_DDIB_DETECTED)
11991 intel_ddi_init(dev, PORT_B);
11992 if (found & SFUSE_STRAP_DDIC_DETECTED)
11993 intel_ddi_init(dev, PORT_C);
11994 if (found & SFUSE_STRAP_DDID_DETECTED)
11995 intel_ddi_init(dev, PORT_D);
11996 } else if (HAS_PCH_SPLIT(dev)) {
11997 int found;
11998 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
11999
12000 if (has_edp_a(dev))
12001 intel_dp_init(dev, DP_A, PORT_A);
12002
12003 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12004 /* PCH SDVOB multiplex with HDMIB */
12005 found = intel_sdvo_init(dev, PCH_SDVOB, true);
12006 if (!found)
12007 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12008 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12009 intel_dp_init(dev, PCH_DP_B, PORT_B);
12010 }
12011
12012 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12013 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12014
12015 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12016 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12017
12018 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12019 intel_dp_init(dev, PCH_DP_C, PORT_C);
12020
12021 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12022 intel_dp_init(dev, PCH_DP_D, PORT_D);
12023 } else if (IS_VALLEYVIEW(dev)) {
12024 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
12025 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12026 PORT_B);
12027 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
12028 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12029 }
12030
12031 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
12032 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12033 PORT_C);
12034 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
12035 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12036 }
12037
12038 if (IS_CHERRYVIEW(dev)) {
12039 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) {
12040 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12041 PORT_D);
12042 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12043 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12044 }
12045 }
12046
12047 intel_dsi_init(dev);
12048 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12049 bool found = false;
12050
12051 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12052 DRM_DEBUG_KMS("probing SDVOB\n");
12053 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12054 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12055 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12056 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12057 }
12058
12059 if (!found && SUPPORTS_INTEGRATED_DP(dev))
12060 intel_dp_init(dev, DP_B, PORT_B);
12061 }
12062
12063 /* Before G4X SDVOC doesn't have its own detect register */
12064
12065 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12066 DRM_DEBUG_KMS("probing SDVOC\n");
12067 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12068 }
12069
12070 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12071
12072 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12073 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12074 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12075 }
12076 if (SUPPORTS_INTEGRATED_DP(dev))
12077 intel_dp_init(dev, DP_C, PORT_C);
12078 }
12079
12080 if (SUPPORTS_INTEGRATED_DP(dev) &&
12081 (I915_READ(DP_D) & DP_DETECTED))
12082 intel_dp_init(dev, DP_D, PORT_D);
12083 } else if (IS_GEN2(dev))
12084 intel_dvo_init(dev);
12085
12086 if (SUPPORTS_TV(dev))
12087 intel_tv_init(dev);
12088
12089 intel_edp_psr_init(dev);
12090
12091 for_each_intel_encoder(dev, encoder) {
12092 encoder->base.possible_crtcs = encoder->crtc_mask;
12093 encoder->base.possible_clones =
12094 intel_encoder_clones(encoder);
12095 }
12096
12097 intel_init_pch_refclk(dev);
12098
12099 drm_helper_move_panel_connectors_to_head(dev);
12100 }
12101
12102 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12103 {
12104 struct drm_device *dev = fb->dev;
12105 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12106
12107 drm_framebuffer_cleanup(fb);
12108 mutex_lock(&dev->struct_mutex);
12109 WARN_ON(!intel_fb->obj->framebuffer_references--);
12110 drm_gem_object_unreference(&intel_fb->obj->base);
12111 mutex_unlock(&dev->struct_mutex);
12112 kfree(intel_fb);
12113 }
12114
12115 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12116 struct drm_file *file,
12117 unsigned int *handle)
12118 {
12119 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12120 struct drm_i915_gem_object *obj = intel_fb->obj;
12121
12122 return drm_gem_handle_create(file, &obj->base, handle);
12123 }
12124
12125 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12126 .destroy = intel_user_framebuffer_destroy,
12127 .create_handle = intel_user_framebuffer_create_handle,
12128 };
12129
12130 static int intel_framebuffer_init(struct drm_device *dev,
12131 struct intel_framebuffer *intel_fb,
12132 struct drm_mode_fb_cmd2 *mode_cmd,
12133 struct drm_i915_gem_object *obj)
12134 {
12135 int aligned_height;
12136 int pitch_limit;
12137 int ret;
12138
12139 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12140
12141 if (obj->tiling_mode == I915_TILING_Y) {
12142 DRM_DEBUG("hardware does not support tiling Y\n");
12143 return -EINVAL;
12144 }
12145
12146 if (mode_cmd->pitches[0] & 63) {
12147 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12148 mode_cmd->pitches[0]);
12149 return -EINVAL;
12150 }
12151
12152 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12153 pitch_limit = 32*1024;
12154 } else if (INTEL_INFO(dev)->gen >= 4) {
12155 if (obj->tiling_mode)
12156 pitch_limit = 16*1024;
12157 else
12158 pitch_limit = 32*1024;
12159 } else if (INTEL_INFO(dev)->gen >= 3) {
12160 if (obj->tiling_mode)
12161 pitch_limit = 8*1024;
12162 else
12163 pitch_limit = 16*1024;
12164 } else
12165 /* XXX DSPC is limited to 4k tiled */
12166 pitch_limit = 8*1024;
12167
12168 if (mode_cmd->pitches[0] > pitch_limit) {
12169 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12170 obj->tiling_mode ? "tiled" : "linear",
12171 mode_cmd->pitches[0], pitch_limit);
12172 return -EINVAL;
12173 }
12174
12175 if (obj->tiling_mode != I915_TILING_NONE &&
12176 mode_cmd->pitches[0] != obj->stride) {
12177 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12178 mode_cmd->pitches[0], obj->stride);
12179 return -EINVAL;
12180 }
12181
12182 /* Reject formats not supported by any plane early. */
12183 switch (mode_cmd->pixel_format) {
12184 case DRM_FORMAT_C8:
12185 case DRM_FORMAT_RGB565:
12186 case DRM_FORMAT_XRGB8888:
12187 case DRM_FORMAT_ARGB8888:
12188 break;
12189 case DRM_FORMAT_XRGB1555:
12190 case DRM_FORMAT_ARGB1555:
12191 if (INTEL_INFO(dev)->gen > 3) {
12192 DRM_DEBUG("unsupported pixel format: %s\n",
12193 drm_get_format_name(mode_cmd->pixel_format));
12194 return -EINVAL;
12195 }
12196 break;
12197 case DRM_FORMAT_XBGR8888:
12198 case DRM_FORMAT_ABGR8888:
12199 case DRM_FORMAT_XRGB2101010:
12200 case DRM_FORMAT_ARGB2101010:
12201 case DRM_FORMAT_XBGR2101010:
12202 case DRM_FORMAT_ABGR2101010:
12203 if (INTEL_INFO(dev)->gen < 4) {
12204 DRM_DEBUG("unsupported pixel format: %s\n",
12205 drm_get_format_name(mode_cmd->pixel_format));
12206 return -EINVAL;
12207 }
12208 break;
12209 case DRM_FORMAT_YUYV:
12210 case DRM_FORMAT_UYVY:
12211 case DRM_FORMAT_YVYU:
12212 case DRM_FORMAT_VYUY:
12213 if (INTEL_INFO(dev)->gen < 5) {
12214 DRM_DEBUG("unsupported pixel format: %s\n",
12215 drm_get_format_name(mode_cmd->pixel_format));
12216 return -EINVAL;
12217 }
12218 break;
12219 default:
12220 DRM_DEBUG("unsupported pixel format: %s\n",
12221 drm_get_format_name(mode_cmd->pixel_format));
12222 return -EINVAL;
12223 }
12224
12225 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12226 if (mode_cmd->offsets[0] != 0)
12227 return -EINVAL;
12228
12229 aligned_height = intel_align_height(dev, mode_cmd->height,
12230 obj->tiling_mode);
12231 /* FIXME drm helper for size checks (especially planar formats)? */
12232 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12233 return -EINVAL;
12234
12235 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12236 intel_fb->obj = obj;
12237 intel_fb->obj->framebuffer_references++;
12238
12239 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12240 if (ret) {
12241 DRM_ERROR("framebuffer init failed %d\n", ret);
12242 return ret;
12243 }
12244
12245 return 0;
12246 }
12247
12248 static struct drm_framebuffer *
12249 intel_user_framebuffer_create(struct drm_device *dev,
12250 struct drm_file *filp,
12251 struct drm_mode_fb_cmd2 *mode_cmd)
12252 {
12253 struct drm_i915_gem_object *obj;
12254
12255 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12256 mode_cmd->handles[0]));
12257 if (&obj->base == NULL)
12258 return ERR_PTR(-ENOENT);
12259
12260 return intel_framebuffer_create(dev, mode_cmd, obj);
12261 }
12262
12263 #ifndef CONFIG_DRM_I915_FBDEV
12264 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12265 {
12266 }
12267 #endif
12268
12269 static const struct drm_mode_config_funcs intel_mode_funcs = {
12270 .fb_create = intel_user_framebuffer_create,
12271 .output_poll_changed = intel_fbdev_output_poll_changed,
12272 };
12273
12274 /* Set up chip specific display functions */
12275 static void intel_init_display(struct drm_device *dev)
12276 {
12277 struct drm_i915_private *dev_priv = dev->dev_private;
12278
12279 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12280 dev_priv->display.find_dpll = g4x_find_best_dpll;
12281 else if (IS_CHERRYVIEW(dev))
12282 dev_priv->display.find_dpll = chv_find_best_dpll;
12283 else if (IS_VALLEYVIEW(dev))
12284 dev_priv->display.find_dpll = vlv_find_best_dpll;
12285 else if (IS_PINEVIEW(dev))
12286 dev_priv->display.find_dpll = pnv_find_best_dpll;
12287 else
12288 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12289
12290 if (HAS_DDI(dev)) {
12291 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12292 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12293 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
12294 dev_priv->display.crtc_enable = haswell_crtc_enable;
12295 dev_priv->display.crtc_disable = haswell_crtc_disable;
12296 dev_priv->display.off = ironlake_crtc_off;
12297 dev_priv->display.update_primary_plane =
12298 ironlake_update_primary_plane;
12299 } else if (HAS_PCH_SPLIT(dev)) {
12300 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12301 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12302 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
12303 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12304 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12305 dev_priv->display.off = ironlake_crtc_off;
12306 dev_priv->display.update_primary_plane =
12307 ironlake_update_primary_plane;
12308 } else if (IS_VALLEYVIEW(dev)) {
12309 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12310 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12311 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12312 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12313 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12314 dev_priv->display.off = i9xx_crtc_off;
12315 dev_priv->display.update_primary_plane =
12316 i9xx_update_primary_plane;
12317 } else {
12318 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12319 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12320 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12321 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12322 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12323 dev_priv->display.off = i9xx_crtc_off;
12324 dev_priv->display.update_primary_plane =
12325 i9xx_update_primary_plane;
12326 }
12327
12328 /* Returns the core display clock speed */
12329 if (IS_VALLEYVIEW(dev))
12330 dev_priv->display.get_display_clock_speed =
12331 valleyview_get_display_clock_speed;
12332 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12333 dev_priv->display.get_display_clock_speed =
12334 i945_get_display_clock_speed;
12335 else if (IS_I915G(dev))
12336 dev_priv->display.get_display_clock_speed =
12337 i915_get_display_clock_speed;
12338 else if (IS_I945GM(dev) || IS_845G(dev))
12339 dev_priv->display.get_display_clock_speed =
12340 i9xx_misc_get_display_clock_speed;
12341 else if (IS_PINEVIEW(dev))
12342 dev_priv->display.get_display_clock_speed =
12343 pnv_get_display_clock_speed;
12344 else if (IS_I915GM(dev))
12345 dev_priv->display.get_display_clock_speed =
12346 i915gm_get_display_clock_speed;
12347 else if (IS_I865G(dev))
12348 dev_priv->display.get_display_clock_speed =
12349 i865_get_display_clock_speed;
12350 else if (IS_I85X(dev))
12351 dev_priv->display.get_display_clock_speed =
12352 i855_get_display_clock_speed;
12353 else /* 852, 830 */
12354 dev_priv->display.get_display_clock_speed =
12355 i830_get_display_clock_speed;
12356
12357 if (IS_G4X(dev)) {
12358 dev_priv->display.write_eld = g4x_write_eld;
12359 } else if (IS_GEN5(dev)) {
12360 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12361 dev_priv->display.write_eld = ironlake_write_eld;
12362 } else if (IS_GEN6(dev)) {
12363 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12364 dev_priv->display.write_eld = ironlake_write_eld;
12365 dev_priv->display.modeset_global_resources =
12366 snb_modeset_global_resources;
12367 } else if (IS_IVYBRIDGE(dev)) {
12368 /* FIXME: detect B0+ stepping and use auto training */
12369 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12370 dev_priv->display.write_eld = ironlake_write_eld;
12371 dev_priv->display.modeset_global_resources =
12372 ivb_modeset_global_resources;
12373 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
12374 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12375 dev_priv->display.write_eld = haswell_write_eld;
12376 dev_priv->display.modeset_global_resources =
12377 haswell_modeset_global_resources;
12378 } else if (IS_VALLEYVIEW(dev)) {
12379 dev_priv->display.modeset_global_resources =
12380 valleyview_modeset_global_resources;
12381 dev_priv->display.write_eld = ironlake_write_eld;
12382 }
12383
12384 /* Default just returns -ENODEV to indicate unsupported */
12385 dev_priv->display.queue_flip = intel_default_queue_flip;
12386
12387 switch (INTEL_INFO(dev)->gen) {
12388 case 2:
12389 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12390 break;
12391
12392 case 3:
12393 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12394 break;
12395
12396 case 4:
12397 case 5:
12398 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12399 break;
12400
12401 case 6:
12402 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12403 break;
12404 case 7:
12405 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12406 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12407 break;
12408 }
12409
12410 intel_panel_init_backlight_funcs(dev);
12411 }
12412
12413 /*
12414 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12415 * resume, or other times. This quirk makes sure that's the case for
12416 * affected systems.
12417 */
12418 static void quirk_pipea_force(struct drm_device *dev)
12419 {
12420 struct drm_i915_private *dev_priv = dev->dev_private;
12421
12422 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12423 DRM_INFO("applying pipe a force quirk\n");
12424 }
12425
12426 /*
12427 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12428 */
12429 static void quirk_ssc_force_disable(struct drm_device *dev)
12430 {
12431 struct drm_i915_private *dev_priv = dev->dev_private;
12432 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12433 DRM_INFO("applying lvds SSC disable quirk\n");
12434 }
12435
12436 /*
12437 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12438 * brightness value
12439 */
12440 static void quirk_invert_brightness(struct drm_device *dev)
12441 {
12442 struct drm_i915_private *dev_priv = dev->dev_private;
12443 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
12444 DRM_INFO("applying inverted panel brightness quirk\n");
12445 }
12446
12447 /* Some VBT's incorrectly indicate no backlight is present */
12448 static void quirk_backlight_present(struct drm_device *dev)
12449 {
12450 struct drm_i915_private *dev_priv = dev->dev_private;
12451 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
12452 DRM_INFO("applying backlight present quirk\n");
12453 }
12454
12455 struct intel_quirk {
12456 int device;
12457 int subsystem_vendor;
12458 int subsystem_device;
12459 void (*hook)(struct drm_device *dev);
12460 };
12461
12462 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12463 struct intel_dmi_quirk {
12464 void (*hook)(struct drm_device *dev);
12465 const struct dmi_system_id (*dmi_id_list)[];
12466 };
12467
12468 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12469 {
12470 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12471 return 1;
12472 }
12473
12474 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12475 {
12476 .dmi_id_list = &(const struct dmi_system_id[]) {
12477 {
12478 .callback = intel_dmi_reverse_brightness,
12479 .ident = "NCR Corporation",
12480 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12481 DMI_MATCH(DMI_PRODUCT_NAME, ""),
12482 },
12483 },
12484 { } /* terminating entry */
12485 },
12486 .hook = quirk_invert_brightness,
12487 },
12488 };
12489
12490 static struct intel_quirk intel_quirks[] = {
12491 /* HP Mini needs pipe A force quirk (LP: #322104) */
12492 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
12493
12494 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12495 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12496
12497 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12498 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12499
12500 /* Lenovo U160 cannot use SSC on LVDS */
12501 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
12502
12503 /* Sony Vaio Y cannot use SSC on LVDS */
12504 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
12505
12506 /* Acer Aspire 5734Z must invert backlight brightness */
12507 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12508
12509 /* Acer/eMachines G725 */
12510 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12511
12512 /* Acer/eMachines e725 */
12513 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12514
12515 /* Acer/Packard Bell NCL20 */
12516 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12517
12518 /* Acer Aspire 4736Z */
12519 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
12520
12521 /* Acer Aspire 5336 */
12522 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
12523
12524 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12525 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
12526
12527 /* Toshiba CB35 Chromebook (Celeron 2955U) */
12528 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
12529
12530 /* HP Chromebook 14 (Celeron 2955U) */
12531 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
12532 };
12533
12534 static void intel_init_quirks(struct drm_device *dev)
12535 {
12536 struct pci_dev *d = dev->pdev;
12537 int i;
12538
12539 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12540 struct intel_quirk *q = &intel_quirks[i];
12541
12542 if (d->device == q->device &&
12543 (d->subsystem_vendor == q->subsystem_vendor ||
12544 q->subsystem_vendor == PCI_ANY_ID) &&
12545 (d->subsystem_device == q->subsystem_device ||
12546 q->subsystem_device == PCI_ANY_ID))
12547 q->hook(dev);
12548 }
12549 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12550 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12551 intel_dmi_quirks[i].hook(dev);
12552 }
12553 }
12554
12555 /* Disable the VGA plane that we never use */
12556 static void i915_disable_vga(struct drm_device *dev)
12557 {
12558 struct drm_i915_private *dev_priv = dev->dev_private;
12559 u8 sr1;
12560 u32 vga_reg = i915_vgacntrl_reg(dev);
12561
12562 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12563 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
12564 outb(SR01, VGA_SR_INDEX);
12565 sr1 = inb(VGA_SR_DATA);
12566 outb(sr1 | 1<<5, VGA_SR_DATA);
12567 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12568 udelay(300);
12569
12570 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
12571 POSTING_READ(vga_reg);
12572 }
12573
12574 void intel_modeset_init_hw(struct drm_device *dev)
12575 {
12576 intel_prepare_ddi(dev);
12577
12578 if (IS_VALLEYVIEW(dev))
12579 vlv_update_cdclk(dev);
12580
12581 intel_init_clock_gating(dev);
12582
12583 intel_enable_gt_powersave(dev);
12584 }
12585
12586 void intel_modeset_suspend_hw(struct drm_device *dev)
12587 {
12588 intel_suspend_hw(dev);
12589 }
12590
12591 void intel_modeset_init(struct drm_device *dev)
12592 {
12593 struct drm_i915_private *dev_priv = dev->dev_private;
12594 int sprite, ret;
12595 enum pipe pipe;
12596 struct intel_crtc *crtc;
12597
12598 drm_mode_config_init(dev);
12599
12600 dev->mode_config.min_width = 0;
12601 dev->mode_config.min_height = 0;
12602
12603 dev->mode_config.preferred_depth = 24;
12604 dev->mode_config.prefer_shadow = 1;
12605
12606 dev->mode_config.funcs = &intel_mode_funcs;
12607
12608 intel_init_quirks(dev);
12609
12610 intel_init_pm(dev);
12611
12612 if (INTEL_INFO(dev)->num_pipes == 0)
12613 return;
12614
12615 intel_init_display(dev);
12616
12617 if (IS_GEN2(dev)) {
12618 dev->mode_config.max_width = 2048;
12619 dev->mode_config.max_height = 2048;
12620 } else if (IS_GEN3(dev)) {
12621 dev->mode_config.max_width = 4096;
12622 dev->mode_config.max_height = 4096;
12623 } else {
12624 dev->mode_config.max_width = 8192;
12625 dev->mode_config.max_height = 8192;
12626 }
12627
12628 if (IS_GEN2(dev)) {
12629 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
12630 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
12631 } else {
12632 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
12633 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
12634 }
12635
12636 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
12637
12638 DRM_DEBUG_KMS("%d display pipe%s available.\n",
12639 INTEL_INFO(dev)->num_pipes,
12640 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
12641
12642 for_each_pipe(pipe) {
12643 intel_crtc_init(dev, pipe);
12644 for_each_sprite(pipe, sprite) {
12645 ret = intel_plane_init(dev, pipe, sprite);
12646 if (ret)
12647 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
12648 pipe_name(pipe), sprite_name(pipe, sprite), ret);
12649 }
12650 }
12651
12652 intel_init_dpio(dev);
12653
12654 intel_shared_dpll_init(dev);
12655
12656 /* Just disable it once at startup */
12657 i915_disable_vga(dev);
12658 intel_setup_outputs(dev);
12659
12660 /* Just in case the BIOS is doing something questionable. */
12661 intel_disable_fbc(dev);
12662
12663 drm_modeset_lock_all(dev);
12664 intel_modeset_setup_hw_state(dev, false);
12665 drm_modeset_unlock_all(dev);
12666
12667 for_each_intel_crtc(dev, crtc) {
12668 if (!crtc->active)
12669 continue;
12670
12671 /*
12672 * Note that reserving the BIOS fb up front prevents us
12673 * from stuffing other stolen allocations like the ring
12674 * on top. This prevents some ugliness at boot time, and
12675 * can even allow for smooth boot transitions if the BIOS
12676 * fb is large enough for the active pipe configuration.
12677 */
12678 if (dev_priv->display.get_plane_config) {
12679 dev_priv->display.get_plane_config(crtc,
12680 &crtc->plane_config);
12681 /*
12682 * If the fb is shared between multiple heads, we'll
12683 * just get the first one.
12684 */
12685 intel_find_plane_obj(crtc, &crtc->plane_config);
12686 }
12687 }
12688 }
12689
12690 static void intel_enable_pipe_a(struct drm_device *dev)
12691 {
12692 struct intel_connector *connector;
12693 struct drm_connector *crt = NULL;
12694 struct intel_load_detect_pipe load_detect_temp;
12695 struct drm_modeset_acquire_ctx ctx;
12696
12697 /* We can't just switch on the pipe A, we need to set things up with a
12698 * proper mode and output configuration. As a gross hack, enable pipe A
12699 * by enabling the load detect pipe once. */
12700 list_for_each_entry(connector,
12701 &dev->mode_config.connector_list,
12702 base.head) {
12703 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
12704 crt = &connector->base;
12705 break;
12706 }
12707 }
12708
12709 if (!crt)
12710 return;
12711
12712 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, &ctx))
12713 intel_release_load_detect_pipe(crt, &load_detect_temp, &ctx);
12714
12715
12716 }
12717
12718 static bool
12719 intel_check_plane_mapping(struct intel_crtc *crtc)
12720 {
12721 struct drm_device *dev = crtc->base.dev;
12722 struct drm_i915_private *dev_priv = dev->dev_private;
12723 u32 reg, val;
12724
12725 if (INTEL_INFO(dev)->num_pipes == 1)
12726 return true;
12727
12728 reg = DSPCNTR(!crtc->plane);
12729 val = I915_READ(reg);
12730
12731 if ((val & DISPLAY_PLANE_ENABLE) &&
12732 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
12733 return false;
12734
12735 return true;
12736 }
12737
12738 static void intel_sanitize_crtc(struct intel_crtc *crtc)
12739 {
12740 struct drm_device *dev = crtc->base.dev;
12741 struct drm_i915_private *dev_priv = dev->dev_private;
12742 u32 reg;
12743
12744 /* Clear any frame start delays used for debugging left by the BIOS */
12745 reg = PIPECONF(crtc->config.cpu_transcoder);
12746 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
12747
12748 /* restore vblank interrupts to correct state */
12749 if (crtc->active)
12750 drm_vblank_on(dev, crtc->pipe);
12751 else
12752 drm_vblank_off(dev, crtc->pipe);
12753
12754 /* We need to sanitize the plane -> pipe mapping first because this will
12755 * disable the crtc (and hence change the state) if it is wrong. Note
12756 * that gen4+ has a fixed plane -> pipe mapping. */
12757 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
12758 struct intel_connector *connector;
12759 bool plane;
12760
12761 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
12762 crtc->base.base.id);
12763
12764 /* Pipe has the wrong plane attached and the plane is active.
12765 * Temporarily change the plane mapping and disable everything
12766 * ... */
12767 plane = crtc->plane;
12768 crtc->plane = !plane;
12769 crtc->primary_enabled = true;
12770 dev_priv->display.crtc_disable(&crtc->base);
12771 crtc->plane = plane;
12772
12773 /* ... and break all links. */
12774 list_for_each_entry(connector, &dev->mode_config.connector_list,
12775 base.head) {
12776 if (connector->encoder->base.crtc != &crtc->base)
12777 continue;
12778
12779 connector->base.dpms = DRM_MODE_DPMS_OFF;
12780 connector->base.encoder = NULL;
12781 }
12782 /* multiple connectors may have the same encoder:
12783 * handle them and break crtc link separately */
12784 list_for_each_entry(connector, &dev->mode_config.connector_list,
12785 base.head)
12786 if (connector->encoder->base.crtc == &crtc->base) {
12787 connector->encoder->base.crtc = NULL;
12788 connector->encoder->connectors_active = false;
12789 }
12790
12791 WARN_ON(crtc->active);
12792 crtc->base.enabled = false;
12793 }
12794
12795 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
12796 crtc->pipe == PIPE_A && !crtc->active) {
12797 /* BIOS forgot to enable pipe A, this mostly happens after
12798 * resume. Force-enable the pipe to fix this, the update_dpms
12799 * call below we restore the pipe to the right state, but leave
12800 * the required bits on. */
12801 intel_enable_pipe_a(dev);
12802 }
12803
12804 /* Adjust the state of the output pipe according to whether we
12805 * have active connectors/encoders. */
12806 intel_crtc_update_dpms(&crtc->base);
12807
12808 if (crtc->active != crtc->base.enabled) {
12809 struct intel_encoder *encoder;
12810
12811 /* This can happen either due to bugs in the get_hw_state
12812 * functions or because the pipe is force-enabled due to the
12813 * pipe A quirk. */
12814 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
12815 crtc->base.base.id,
12816 crtc->base.enabled ? "enabled" : "disabled",
12817 crtc->active ? "enabled" : "disabled");
12818
12819 crtc->base.enabled = crtc->active;
12820
12821 /* Because we only establish the connector -> encoder ->
12822 * crtc links if something is active, this means the
12823 * crtc is now deactivated. Break the links. connector
12824 * -> encoder links are only establish when things are
12825 * actually up, hence no need to break them. */
12826 WARN_ON(crtc->active);
12827
12828 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
12829 WARN_ON(encoder->connectors_active);
12830 encoder->base.crtc = NULL;
12831 }
12832 }
12833
12834 if (crtc->active || IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen < 5) {
12835 /*
12836 * We start out with underrun reporting disabled to avoid races.
12837 * For correct bookkeeping mark this on active crtcs.
12838 *
12839 * Also on gmch platforms we dont have any hardware bits to
12840 * disable the underrun reporting. Which means we need to start
12841 * out with underrun reporting disabled also on inactive pipes,
12842 * since otherwise we'll complain about the garbage we read when
12843 * e.g. coming up after runtime pm.
12844 *
12845 * No protection against concurrent access is required - at
12846 * worst a fifo underrun happens which also sets this to false.
12847 */
12848 crtc->cpu_fifo_underrun_disabled = true;
12849 crtc->pch_fifo_underrun_disabled = true;
12850
12851 update_scanline_offset(crtc);
12852 }
12853 }
12854
12855 static void intel_sanitize_encoder(struct intel_encoder *encoder)
12856 {
12857 struct intel_connector *connector;
12858 struct drm_device *dev = encoder->base.dev;
12859
12860 /* We need to check both for a crtc link (meaning that the
12861 * encoder is active and trying to read from a pipe) and the
12862 * pipe itself being active. */
12863 bool has_active_crtc = encoder->base.crtc &&
12864 to_intel_crtc(encoder->base.crtc)->active;
12865
12866 if (encoder->connectors_active && !has_active_crtc) {
12867 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
12868 encoder->base.base.id,
12869 encoder->base.name);
12870
12871 /* Connector is active, but has no active pipe. This is
12872 * fallout from our resume register restoring. Disable
12873 * the encoder manually again. */
12874 if (encoder->base.crtc) {
12875 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
12876 encoder->base.base.id,
12877 encoder->base.name);
12878 encoder->disable(encoder);
12879 if (encoder->post_disable)
12880 encoder->post_disable(encoder);
12881 }
12882 encoder->base.crtc = NULL;
12883 encoder->connectors_active = false;
12884
12885 /* Inconsistent output/port/pipe state happens presumably due to
12886 * a bug in one of the get_hw_state functions. Or someplace else
12887 * in our code, like the register restore mess on resume. Clamp
12888 * things to off as a safer default. */
12889 list_for_each_entry(connector,
12890 &dev->mode_config.connector_list,
12891 base.head) {
12892 if (connector->encoder != encoder)
12893 continue;
12894 connector->base.dpms = DRM_MODE_DPMS_OFF;
12895 connector->base.encoder = NULL;
12896 }
12897 }
12898 /* Enabled encoders without active connectors will be fixed in
12899 * the crtc fixup. */
12900 }
12901
12902 void i915_redisable_vga_power_on(struct drm_device *dev)
12903 {
12904 struct drm_i915_private *dev_priv = dev->dev_private;
12905 u32 vga_reg = i915_vgacntrl_reg(dev);
12906
12907 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
12908 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
12909 i915_disable_vga(dev);
12910 }
12911 }
12912
12913 void i915_redisable_vga(struct drm_device *dev)
12914 {
12915 struct drm_i915_private *dev_priv = dev->dev_private;
12916
12917 /* This function can be called both from intel_modeset_setup_hw_state or
12918 * at a very early point in our resume sequence, where the power well
12919 * structures are not yet restored. Since this function is at a very
12920 * paranoid "someone might have enabled VGA while we were not looking"
12921 * level, just check if the power well is enabled instead of trying to
12922 * follow the "don't touch the power well if we don't need it" policy
12923 * the rest of the driver uses. */
12924 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
12925 return;
12926
12927 i915_redisable_vga_power_on(dev);
12928 }
12929
12930 static bool primary_get_hw_state(struct intel_crtc *crtc)
12931 {
12932 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
12933
12934 if (!crtc->active)
12935 return false;
12936
12937 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
12938 }
12939
12940 static void intel_modeset_readout_hw_state(struct drm_device *dev)
12941 {
12942 struct drm_i915_private *dev_priv = dev->dev_private;
12943 enum pipe pipe;
12944 struct intel_crtc *crtc;
12945 struct intel_encoder *encoder;
12946 struct intel_connector *connector;
12947 int i;
12948
12949 for_each_intel_crtc(dev, crtc) {
12950 memset(&crtc->config, 0, sizeof(crtc->config));
12951
12952 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
12953
12954 crtc->active = dev_priv->display.get_pipe_config(crtc,
12955 &crtc->config);
12956
12957 crtc->base.enabled = crtc->active;
12958 crtc->primary_enabled = primary_get_hw_state(crtc);
12959
12960 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
12961 crtc->base.base.id,
12962 crtc->active ? "enabled" : "disabled");
12963 }
12964
12965 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12966 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12967
12968 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
12969 pll->active = 0;
12970 for_each_intel_crtc(dev, crtc) {
12971 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12972 pll->active++;
12973 }
12974 pll->refcount = pll->active;
12975
12976 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
12977 pll->name, pll->refcount, pll->on);
12978
12979 if (pll->refcount)
12980 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
12981 }
12982
12983 for_each_intel_encoder(dev, encoder) {
12984 pipe = 0;
12985
12986 if (encoder->get_hw_state(encoder, &pipe)) {
12987 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
12988 encoder->base.crtc = &crtc->base;
12989 encoder->get_config(encoder, &crtc->config);
12990 } else {
12991 encoder->base.crtc = NULL;
12992 }
12993
12994 encoder->connectors_active = false;
12995 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
12996 encoder->base.base.id,
12997 encoder->base.name,
12998 encoder->base.crtc ? "enabled" : "disabled",
12999 pipe_name(pipe));
13000 }
13001
13002 list_for_each_entry(connector, &dev->mode_config.connector_list,
13003 base.head) {
13004 if (connector->get_hw_state(connector)) {
13005 connector->base.dpms = DRM_MODE_DPMS_ON;
13006 connector->encoder->connectors_active = true;
13007 connector->base.encoder = &connector->encoder->base;
13008 } else {
13009 connector->base.dpms = DRM_MODE_DPMS_OFF;
13010 connector->base.encoder = NULL;
13011 }
13012 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13013 connector->base.base.id,
13014 connector->base.name,
13015 connector->base.encoder ? "enabled" : "disabled");
13016 }
13017 }
13018
13019 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13020 * and i915 state tracking structures. */
13021 void intel_modeset_setup_hw_state(struct drm_device *dev,
13022 bool force_restore)
13023 {
13024 struct drm_i915_private *dev_priv = dev->dev_private;
13025 enum pipe pipe;
13026 struct intel_crtc *crtc;
13027 struct intel_encoder *encoder;
13028 int i;
13029
13030 intel_modeset_readout_hw_state(dev);
13031
13032 /*
13033 * Now that we have the config, copy it to each CRTC struct
13034 * Note that this could go away if we move to using crtc_config
13035 * checking everywhere.
13036 */
13037 for_each_intel_crtc(dev, crtc) {
13038 if (crtc->active && i915.fastboot) {
13039 intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
13040 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13041 crtc->base.base.id);
13042 drm_mode_debug_printmodeline(&crtc->base.mode);
13043 }
13044 }
13045
13046 /* HW state is read out, now we need to sanitize this mess. */
13047 for_each_intel_encoder(dev, encoder) {
13048 intel_sanitize_encoder(encoder);
13049 }
13050
13051 for_each_pipe(pipe) {
13052 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13053 intel_sanitize_crtc(crtc);
13054 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
13055 }
13056
13057 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13058 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13059
13060 if (!pll->on || pll->active)
13061 continue;
13062
13063 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13064
13065 pll->disable(dev_priv, pll);
13066 pll->on = false;
13067 }
13068
13069 if (HAS_PCH_SPLIT(dev))
13070 ilk_wm_get_hw_state(dev);
13071
13072 if (force_restore) {
13073 i915_redisable_vga(dev);
13074
13075 /*
13076 * We need to use raw interfaces for restoring state to avoid
13077 * checking (bogus) intermediate states.
13078 */
13079 for_each_pipe(pipe) {
13080 struct drm_crtc *crtc =
13081 dev_priv->pipe_to_crtc_mapping[pipe];
13082
13083 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13084 crtc->primary->fb);
13085 }
13086 } else {
13087 intel_modeset_update_staged_output_state(dev);
13088 }
13089
13090 intel_modeset_check_state(dev);
13091 }
13092
13093 void intel_modeset_gem_init(struct drm_device *dev)
13094 {
13095 struct drm_crtc *c;
13096 struct drm_i915_gem_object *obj;
13097
13098 mutex_lock(&dev->struct_mutex);
13099 intel_init_gt_powersave(dev);
13100 mutex_unlock(&dev->struct_mutex);
13101
13102 intel_modeset_init_hw(dev);
13103
13104 intel_setup_overlay(dev);
13105
13106 /*
13107 * Make sure any fbs we allocated at startup are properly
13108 * pinned & fenced. When we do the allocation it's too early
13109 * for this.
13110 */
13111 mutex_lock(&dev->struct_mutex);
13112 for_each_crtc(dev, c) {
13113 obj = intel_fb_obj(c->primary->fb);
13114 if (obj == NULL)
13115 continue;
13116
13117 if (intel_pin_and_fence_fb_obj(dev, obj, NULL)) {
13118 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13119 to_intel_crtc(c)->pipe);
13120 drm_framebuffer_unreference(c->primary->fb);
13121 c->primary->fb = NULL;
13122 }
13123 }
13124 mutex_unlock(&dev->struct_mutex);
13125 }
13126
13127 void intel_connector_unregister(struct intel_connector *intel_connector)
13128 {
13129 struct drm_connector *connector = &intel_connector->base;
13130
13131 intel_panel_destroy_backlight(connector);
13132 drm_connector_unregister(connector);
13133 }
13134
13135 void intel_modeset_cleanup(struct drm_device *dev)
13136 {
13137 struct drm_i915_private *dev_priv = dev->dev_private;
13138 struct drm_connector *connector;
13139
13140 /*
13141 * Interrupts and polling as the first thing to avoid creating havoc.
13142 * Too much stuff here (turning of rps, connectors, ...) would
13143 * experience fancy races otherwise.
13144 */
13145 drm_irq_uninstall(dev);
13146 cancel_work_sync(&dev_priv->hotplug_work);
13147 dev_priv->pm._irqs_disabled = true;
13148
13149 /*
13150 * Due to the hpd irq storm handling the hotplug work can re-arm the
13151 * poll handlers. Hence disable polling after hpd handling is shut down.
13152 */
13153 drm_kms_helper_poll_fini(dev);
13154
13155 mutex_lock(&dev->struct_mutex);
13156
13157 intel_unregister_dsm_handler();
13158
13159 intel_disable_fbc(dev);
13160
13161 intel_disable_gt_powersave(dev);
13162
13163 ironlake_teardown_rc6(dev);
13164
13165 mutex_unlock(&dev->struct_mutex);
13166
13167 /* flush any delayed tasks or pending work */
13168 flush_scheduled_work();
13169
13170 /* destroy the backlight and sysfs files before encoders/connectors */
13171 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13172 struct intel_connector *intel_connector;
13173
13174 intel_connector = to_intel_connector(connector);
13175 intel_connector->unregister(intel_connector);
13176 }
13177
13178 drm_mode_config_cleanup(dev);
13179
13180 intel_cleanup_overlay(dev);
13181
13182 mutex_lock(&dev->struct_mutex);
13183 intel_cleanup_gt_powersave(dev);
13184 mutex_unlock(&dev->struct_mutex);
13185 }
13186
13187 /*
13188 * Return which encoder is currently attached for connector.
13189 */
13190 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13191 {
13192 return &intel_attached_encoder(connector)->base;
13193 }
13194
13195 void intel_connector_attach_encoder(struct intel_connector *connector,
13196 struct intel_encoder *encoder)
13197 {
13198 connector->encoder = encoder;
13199 drm_mode_connector_attach_encoder(&connector->base,
13200 &encoder->base);
13201 }
13202
13203 /*
13204 * set vga decode state - true == enable VGA decode
13205 */
13206 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13207 {
13208 struct drm_i915_private *dev_priv = dev->dev_private;
13209 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13210 u16 gmch_ctrl;
13211
13212 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13213 DRM_ERROR("failed to read control word\n");
13214 return -EIO;
13215 }
13216
13217 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13218 return 0;
13219
13220 if (state)
13221 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13222 else
13223 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13224
13225 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13226 DRM_ERROR("failed to write control word\n");
13227 return -EIO;
13228 }
13229
13230 return 0;
13231 }
13232
13233 struct intel_display_error_state {
13234
13235 u32 power_well_driver;
13236
13237 int num_transcoders;
13238
13239 struct intel_cursor_error_state {
13240 u32 control;
13241 u32 position;
13242 u32 base;
13243 u32 size;
13244 } cursor[I915_MAX_PIPES];
13245
13246 struct intel_pipe_error_state {
13247 bool power_domain_on;
13248 u32 source;
13249 u32 stat;
13250 } pipe[I915_MAX_PIPES];
13251
13252 struct intel_plane_error_state {
13253 u32 control;
13254 u32 stride;
13255 u32 size;
13256 u32 pos;
13257 u32 addr;
13258 u32 surface;
13259 u32 tile_offset;
13260 } plane[I915_MAX_PIPES];
13261
13262 struct intel_transcoder_error_state {
13263 bool power_domain_on;
13264 enum transcoder cpu_transcoder;
13265
13266 u32 conf;
13267
13268 u32 htotal;
13269 u32 hblank;
13270 u32 hsync;
13271 u32 vtotal;
13272 u32 vblank;
13273 u32 vsync;
13274 } transcoder[4];
13275 };
13276
13277 struct intel_display_error_state *
13278 intel_display_capture_error_state(struct drm_device *dev)
13279 {
13280 struct drm_i915_private *dev_priv = dev->dev_private;
13281 struct intel_display_error_state *error;
13282 int transcoders[] = {
13283 TRANSCODER_A,
13284 TRANSCODER_B,
13285 TRANSCODER_C,
13286 TRANSCODER_EDP,
13287 };
13288 int i;
13289
13290 if (INTEL_INFO(dev)->num_pipes == 0)
13291 return NULL;
13292
13293 error = kzalloc(sizeof(*error), GFP_ATOMIC);
13294 if (error == NULL)
13295 return NULL;
13296
13297 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13298 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13299
13300 for_each_pipe(i) {
13301 error->pipe[i].power_domain_on =
13302 intel_display_power_enabled_unlocked(dev_priv,
13303 POWER_DOMAIN_PIPE(i));
13304 if (!error->pipe[i].power_domain_on)
13305 continue;
13306
13307 error->cursor[i].control = I915_READ(CURCNTR(i));
13308 error->cursor[i].position = I915_READ(CURPOS(i));
13309 error->cursor[i].base = I915_READ(CURBASE(i));
13310
13311 error->plane[i].control = I915_READ(DSPCNTR(i));
13312 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13313 if (INTEL_INFO(dev)->gen <= 3) {
13314 error->plane[i].size = I915_READ(DSPSIZE(i));
13315 error->plane[i].pos = I915_READ(DSPPOS(i));
13316 }
13317 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13318 error->plane[i].addr = I915_READ(DSPADDR(i));
13319 if (INTEL_INFO(dev)->gen >= 4) {
13320 error->plane[i].surface = I915_READ(DSPSURF(i));
13321 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13322 }
13323
13324 error->pipe[i].source = I915_READ(PIPESRC(i));
13325
13326 if (HAS_GMCH_DISPLAY(dev))
13327 error->pipe[i].stat = I915_READ(PIPESTAT(i));
13328 }
13329
13330 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13331 if (HAS_DDI(dev_priv->dev))
13332 error->num_transcoders++; /* Account for eDP. */
13333
13334 for (i = 0; i < error->num_transcoders; i++) {
13335 enum transcoder cpu_transcoder = transcoders[i];
13336
13337 error->transcoder[i].power_domain_on =
13338 intel_display_power_enabled_unlocked(dev_priv,
13339 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13340 if (!error->transcoder[i].power_domain_on)
13341 continue;
13342
13343 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13344
13345 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13346 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13347 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13348 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13349 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13350 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13351 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13352 }
13353
13354 return error;
13355 }
13356
13357 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13358
13359 void
13360 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13361 struct drm_device *dev,
13362 struct intel_display_error_state *error)
13363 {
13364 int i;
13365
13366 if (!error)
13367 return;
13368
13369 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13370 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13371 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13372 error->power_well_driver);
13373 for_each_pipe(i) {
13374 err_printf(m, "Pipe [%d]:\n", i);
13375 err_printf(m, " Power: %s\n",
13376 error->pipe[i].power_domain_on ? "on" : "off");
13377 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
13378 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
13379
13380 err_printf(m, "Plane [%d]:\n", i);
13381 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
13382 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
13383 if (INTEL_INFO(dev)->gen <= 3) {
13384 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
13385 err_printf(m, " POS: %08x\n", error->plane[i].pos);
13386 }
13387 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13388 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
13389 if (INTEL_INFO(dev)->gen >= 4) {
13390 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
13391 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
13392 }
13393
13394 err_printf(m, "Cursor [%d]:\n", i);
13395 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
13396 err_printf(m, " POS: %08x\n", error->cursor[i].position);
13397 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
13398 }
13399
13400 for (i = 0; i < error->num_transcoders; i++) {
13401 err_printf(m, "CPU transcoder: %c\n",
13402 transcoder_name(error->transcoder[i].cpu_transcoder));
13403 err_printf(m, " Power: %s\n",
13404 error->transcoder[i].power_domain_on ? "on" : "off");
13405 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
13406 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
13407 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
13408 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
13409 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
13410 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
13411 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
13412 }
13413 }
13414
13415 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
13416 {
13417 struct intel_crtc *crtc;
13418
13419 for_each_intel_crtc(dev, crtc) {
13420 struct intel_unpin_work *work;
13421 unsigned long irqflags;
13422
13423 spin_lock_irqsave(&dev->event_lock, irqflags);
13424
13425 work = crtc->unpin_work;
13426
13427 if (work && work->event &&
13428 work->event->base.file_priv == file) {
13429 kfree(work->event);
13430 work->event = NULL;
13431 }
13432
13433 spin_unlock_irqrestore(&dev->event_lock, irqflags);
13434 }
13435 }
Linux kernel - Deliverables
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