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Merge tag 'iio-fixes-for-4.0c' of git://git.kernel.org/pub/scm/linux/kernel/git/jic23...
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
47
48 /* Primary plane formats supported by all gen */
49 #define COMMON_PRIMARY_FORMATS \
50 DRM_FORMAT_C8, \
51 DRM_FORMAT_RGB565, \
52 DRM_FORMAT_XRGB8888, \
53 DRM_FORMAT_ARGB8888
54
55 /* Primary plane formats for gen <= 3 */
56 static const uint32_t intel_primary_formats_gen2[] = {
57 COMMON_PRIMARY_FORMATS,
58 DRM_FORMAT_XRGB1555,
59 DRM_FORMAT_ARGB1555,
60 };
61
62 /* Primary plane formats for gen >= 4 */
63 static const uint32_t intel_primary_formats_gen4[] = {
64 COMMON_PRIMARY_FORMATS, \
65 DRM_FORMAT_XBGR8888,
66 DRM_FORMAT_ABGR8888,
67 DRM_FORMAT_XRGB2101010,
68 DRM_FORMAT_ARGB2101010,
69 DRM_FORMAT_XBGR2101010,
70 DRM_FORMAT_ABGR2101010,
71 };
72
73 /* Cursor formats */
74 static const uint32_t intel_cursor_formats[] = {
75 DRM_FORMAT_ARGB8888,
76 };
77
78 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79
80 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
81 struct intel_crtc_state *pipe_config);
82 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
83 struct intel_crtc_state *pipe_config);
84
85 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
86 int x, int y, struct drm_framebuffer *old_fb);
87 static int intel_framebuffer_init(struct drm_device *dev,
88 struct intel_framebuffer *ifb,
89 struct drm_mode_fb_cmd2 *mode_cmd,
90 struct drm_i915_gem_object *obj);
91 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
92 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
93 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
94 struct intel_link_m_n *m_n,
95 struct intel_link_m_n *m2_n2);
96 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
97 static void haswell_set_pipeconf(struct drm_crtc *crtc);
98 static void intel_set_pipe_csc(struct drm_crtc *crtc);
99 static void vlv_prepare_pll(struct intel_crtc *crtc,
100 const struct intel_crtc_state *pipe_config);
101 static void chv_prepare_pll(struct intel_crtc *crtc,
102 const struct intel_crtc_state *pipe_config);
103 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
104 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
105
106 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
107 {
108 if (!connector->mst_port)
109 return connector->encoder;
110 else
111 return &connector->mst_port->mst_encoders[pipe]->base;
112 }
113
114 typedef struct {
115 int min, max;
116 } intel_range_t;
117
118 typedef struct {
119 int dot_limit;
120 int p2_slow, p2_fast;
121 } intel_p2_t;
122
123 typedef struct intel_limit intel_limit_t;
124 struct intel_limit {
125 intel_range_t dot, vco, n, m, m1, m2, p, p1;
126 intel_p2_t p2;
127 };
128
129 int
130 intel_pch_rawclk(struct drm_device *dev)
131 {
132 struct drm_i915_private *dev_priv = dev->dev_private;
133
134 WARN_ON(!HAS_PCH_SPLIT(dev));
135
136 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
137 }
138
139 static inline u32 /* units of 100MHz */
140 intel_fdi_link_freq(struct drm_device *dev)
141 {
142 if (IS_GEN5(dev)) {
143 struct drm_i915_private *dev_priv = dev->dev_private;
144 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
145 } else
146 return 27;
147 }
148
149 static const intel_limit_t intel_limits_i8xx_dac = {
150 .dot = { .min = 25000, .max = 350000 },
151 .vco = { .min = 908000, .max = 1512000 },
152 .n = { .min = 2, .max = 16 },
153 .m = { .min = 96, .max = 140 },
154 .m1 = { .min = 18, .max = 26 },
155 .m2 = { .min = 6, .max = 16 },
156 .p = { .min = 4, .max = 128 },
157 .p1 = { .min = 2, .max = 33 },
158 .p2 = { .dot_limit = 165000,
159 .p2_slow = 4, .p2_fast = 2 },
160 };
161
162 static const intel_limit_t intel_limits_i8xx_dvo = {
163 .dot = { .min = 25000, .max = 350000 },
164 .vco = { .min = 908000, .max = 1512000 },
165 .n = { .min = 2, .max = 16 },
166 .m = { .min = 96, .max = 140 },
167 .m1 = { .min = 18, .max = 26 },
168 .m2 = { .min = 6, .max = 16 },
169 .p = { .min = 4, .max = 128 },
170 .p1 = { .min = 2, .max = 33 },
171 .p2 = { .dot_limit = 165000,
172 .p2_slow = 4, .p2_fast = 4 },
173 };
174
175 static const intel_limit_t intel_limits_i8xx_lvds = {
176 .dot = { .min = 25000, .max = 350000 },
177 .vco = { .min = 908000, .max = 1512000 },
178 .n = { .min = 2, .max = 16 },
179 .m = { .min = 96, .max = 140 },
180 .m1 = { .min = 18, .max = 26 },
181 .m2 = { .min = 6, .max = 16 },
182 .p = { .min = 4, .max = 128 },
183 .p1 = { .min = 1, .max = 6 },
184 .p2 = { .dot_limit = 165000,
185 .p2_slow = 14, .p2_fast = 7 },
186 };
187
188 static const intel_limit_t intel_limits_i9xx_sdvo = {
189 .dot = { .min = 20000, .max = 400000 },
190 .vco = { .min = 1400000, .max = 2800000 },
191 .n = { .min = 1, .max = 6 },
192 .m = { .min = 70, .max = 120 },
193 .m1 = { .min = 8, .max = 18 },
194 .m2 = { .min = 3, .max = 7 },
195 .p = { .min = 5, .max = 80 },
196 .p1 = { .min = 1, .max = 8 },
197 .p2 = { .dot_limit = 200000,
198 .p2_slow = 10, .p2_fast = 5 },
199 };
200
201 static const intel_limit_t intel_limits_i9xx_lvds = {
202 .dot = { .min = 20000, .max = 400000 },
203 .vco = { .min = 1400000, .max = 2800000 },
204 .n = { .min = 1, .max = 6 },
205 .m = { .min = 70, .max = 120 },
206 .m1 = { .min = 8, .max = 18 },
207 .m2 = { .min = 3, .max = 7 },
208 .p = { .min = 7, .max = 98 },
209 .p1 = { .min = 1, .max = 8 },
210 .p2 = { .dot_limit = 112000,
211 .p2_slow = 14, .p2_fast = 7 },
212 };
213
214
215 static const intel_limit_t intel_limits_g4x_sdvo = {
216 .dot = { .min = 25000, .max = 270000 },
217 .vco = { .min = 1750000, .max = 3500000},
218 .n = { .min = 1, .max = 4 },
219 .m = { .min = 104, .max = 138 },
220 .m1 = { .min = 17, .max = 23 },
221 .m2 = { .min = 5, .max = 11 },
222 .p = { .min = 10, .max = 30 },
223 .p1 = { .min = 1, .max = 3},
224 .p2 = { .dot_limit = 270000,
225 .p2_slow = 10,
226 .p2_fast = 10
227 },
228 };
229
230 static const intel_limit_t intel_limits_g4x_hdmi = {
231 .dot = { .min = 22000, .max = 400000 },
232 .vco = { .min = 1750000, .max = 3500000},
233 .n = { .min = 1, .max = 4 },
234 .m = { .min = 104, .max = 138 },
235 .m1 = { .min = 16, .max = 23 },
236 .m2 = { .min = 5, .max = 11 },
237 .p = { .min = 5, .max = 80 },
238 .p1 = { .min = 1, .max = 8},
239 .p2 = { .dot_limit = 165000,
240 .p2_slow = 10, .p2_fast = 5 },
241 };
242
243 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
244 .dot = { .min = 20000, .max = 115000 },
245 .vco = { .min = 1750000, .max = 3500000 },
246 .n = { .min = 1, .max = 3 },
247 .m = { .min = 104, .max = 138 },
248 .m1 = { .min = 17, .max = 23 },
249 .m2 = { .min = 5, .max = 11 },
250 .p = { .min = 28, .max = 112 },
251 .p1 = { .min = 2, .max = 8 },
252 .p2 = { .dot_limit = 0,
253 .p2_slow = 14, .p2_fast = 14
254 },
255 };
256
257 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
258 .dot = { .min = 80000, .max = 224000 },
259 .vco = { .min = 1750000, .max = 3500000 },
260 .n = { .min = 1, .max = 3 },
261 .m = { .min = 104, .max = 138 },
262 .m1 = { .min = 17, .max = 23 },
263 .m2 = { .min = 5, .max = 11 },
264 .p = { .min = 14, .max = 42 },
265 .p1 = { .min = 2, .max = 6 },
266 .p2 = { .dot_limit = 0,
267 .p2_slow = 7, .p2_fast = 7
268 },
269 };
270
271 static const intel_limit_t intel_limits_pineview_sdvo = {
272 .dot = { .min = 20000, .max = 400000},
273 .vco = { .min = 1700000, .max = 3500000 },
274 /* Pineview's Ncounter is a ring counter */
275 .n = { .min = 3, .max = 6 },
276 .m = { .min = 2, .max = 256 },
277 /* Pineview only has one combined m divider, which we treat as m2. */
278 .m1 = { .min = 0, .max = 0 },
279 .m2 = { .min = 0, .max = 254 },
280 .p = { .min = 5, .max = 80 },
281 .p1 = { .min = 1, .max = 8 },
282 .p2 = { .dot_limit = 200000,
283 .p2_slow = 10, .p2_fast = 5 },
284 };
285
286 static const intel_limit_t intel_limits_pineview_lvds = {
287 .dot = { .min = 20000, .max = 400000 },
288 .vco = { .min = 1700000, .max = 3500000 },
289 .n = { .min = 3, .max = 6 },
290 .m = { .min = 2, .max = 256 },
291 .m1 = { .min = 0, .max = 0 },
292 .m2 = { .min = 0, .max = 254 },
293 .p = { .min = 7, .max = 112 },
294 .p1 = { .min = 1, .max = 8 },
295 .p2 = { .dot_limit = 112000,
296 .p2_slow = 14, .p2_fast = 14 },
297 };
298
299 /* Ironlake / Sandybridge
300 *
301 * We calculate clock using (register_value + 2) for N/M1/M2, so here
302 * the range value for them is (actual_value - 2).
303 */
304 static const intel_limit_t intel_limits_ironlake_dac = {
305 .dot = { .min = 25000, .max = 350000 },
306 .vco = { .min = 1760000, .max = 3510000 },
307 .n = { .min = 1, .max = 5 },
308 .m = { .min = 79, .max = 127 },
309 .m1 = { .min = 12, .max = 22 },
310 .m2 = { .min = 5, .max = 9 },
311 .p = { .min = 5, .max = 80 },
312 .p1 = { .min = 1, .max = 8 },
313 .p2 = { .dot_limit = 225000,
314 .p2_slow = 10, .p2_fast = 5 },
315 };
316
317 static const intel_limit_t intel_limits_ironlake_single_lvds = {
318 .dot = { .min = 25000, .max = 350000 },
319 .vco = { .min = 1760000, .max = 3510000 },
320 .n = { .min = 1, .max = 3 },
321 .m = { .min = 79, .max = 118 },
322 .m1 = { .min = 12, .max = 22 },
323 .m2 = { .min = 5, .max = 9 },
324 .p = { .min = 28, .max = 112 },
325 .p1 = { .min = 2, .max = 8 },
326 .p2 = { .dot_limit = 225000,
327 .p2_slow = 14, .p2_fast = 14 },
328 };
329
330 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
331 .dot = { .min = 25000, .max = 350000 },
332 .vco = { .min = 1760000, .max = 3510000 },
333 .n = { .min = 1, .max = 3 },
334 .m = { .min = 79, .max = 127 },
335 .m1 = { .min = 12, .max = 22 },
336 .m2 = { .min = 5, .max = 9 },
337 .p = { .min = 14, .max = 56 },
338 .p1 = { .min = 2, .max = 8 },
339 .p2 = { .dot_limit = 225000,
340 .p2_slow = 7, .p2_fast = 7 },
341 };
342
343 /* LVDS 100mhz refclk limits. */
344 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
345 .dot = { .min = 25000, .max = 350000 },
346 .vco = { .min = 1760000, .max = 3510000 },
347 .n = { .min = 1, .max = 2 },
348 .m = { .min = 79, .max = 126 },
349 .m1 = { .min = 12, .max = 22 },
350 .m2 = { .min = 5, .max = 9 },
351 .p = { .min = 28, .max = 112 },
352 .p1 = { .min = 2, .max = 8 },
353 .p2 = { .dot_limit = 225000,
354 .p2_slow = 14, .p2_fast = 14 },
355 };
356
357 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
358 .dot = { .min = 25000, .max = 350000 },
359 .vco = { .min = 1760000, .max = 3510000 },
360 .n = { .min = 1, .max = 3 },
361 .m = { .min = 79, .max = 126 },
362 .m1 = { .min = 12, .max = 22 },
363 .m2 = { .min = 5, .max = 9 },
364 .p = { .min = 14, .max = 42 },
365 .p1 = { .min = 2, .max = 6 },
366 .p2 = { .dot_limit = 225000,
367 .p2_slow = 7, .p2_fast = 7 },
368 };
369
370 static const intel_limit_t intel_limits_vlv = {
371 /*
372 * These are the data rate limits (measured in fast clocks)
373 * since those are the strictest limits we have. The fast
374 * clock and actual rate limits are more relaxed, so checking
375 * them would make no difference.
376 */
377 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
378 .vco = { .min = 4000000, .max = 6000000 },
379 .n = { .min = 1, .max = 7 },
380 .m1 = { .min = 2, .max = 3 },
381 .m2 = { .min = 11, .max = 156 },
382 .p1 = { .min = 2, .max = 3 },
383 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
384 };
385
386 static const intel_limit_t intel_limits_chv = {
387 /*
388 * These are the data rate limits (measured in fast clocks)
389 * since those are the strictest limits we have. The fast
390 * clock and actual rate limits are more relaxed, so checking
391 * them would make no difference.
392 */
393 .dot = { .min = 25000 * 5, .max = 540000 * 5},
394 .vco = { .min = 4860000, .max = 6700000 },
395 .n = { .min = 1, .max = 1 },
396 .m1 = { .min = 2, .max = 2 },
397 .m2 = { .min = 24 << 22, .max = 175 << 22 },
398 .p1 = { .min = 2, .max = 4 },
399 .p2 = { .p2_slow = 1, .p2_fast = 14 },
400 };
401
402 static void vlv_clock(int refclk, intel_clock_t *clock)
403 {
404 clock->m = clock->m1 * clock->m2;
405 clock->p = clock->p1 * clock->p2;
406 if (WARN_ON(clock->n == 0 || clock->p == 0))
407 return;
408 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
409 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
410 }
411
412 /**
413 * Returns whether any output on the specified pipe is of the specified type
414 */
415 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
416 {
417 struct drm_device *dev = crtc->base.dev;
418 struct intel_encoder *encoder;
419
420 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
421 if (encoder->type == type)
422 return true;
423
424 return false;
425 }
426
427 /**
428 * Returns whether any output on the specified pipe will have the specified
429 * type after a staged modeset is complete, i.e., the same as
430 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
431 * encoder->crtc.
432 */
433 static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
434 {
435 struct drm_device *dev = crtc->base.dev;
436 struct intel_encoder *encoder;
437
438 for_each_intel_encoder(dev, encoder)
439 if (encoder->new_crtc == crtc && encoder->type == type)
440 return true;
441
442 return false;
443 }
444
445 static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
446 int refclk)
447 {
448 struct drm_device *dev = crtc->base.dev;
449 const intel_limit_t *limit;
450
451 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
452 if (intel_is_dual_link_lvds(dev)) {
453 if (refclk == 100000)
454 limit = &intel_limits_ironlake_dual_lvds_100m;
455 else
456 limit = &intel_limits_ironlake_dual_lvds;
457 } else {
458 if (refclk == 100000)
459 limit = &intel_limits_ironlake_single_lvds_100m;
460 else
461 limit = &intel_limits_ironlake_single_lvds;
462 }
463 } else
464 limit = &intel_limits_ironlake_dac;
465
466 return limit;
467 }
468
469 static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
470 {
471 struct drm_device *dev = crtc->base.dev;
472 const intel_limit_t *limit;
473
474 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
475 if (intel_is_dual_link_lvds(dev))
476 limit = &intel_limits_g4x_dual_channel_lvds;
477 else
478 limit = &intel_limits_g4x_single_channel_lvds;
479 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
480 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
481 limit = &intel_limits_g4x_hdmi;
482 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
483 limit = &intel_limits_g4x_sdvo;
484 } else /* The option is for other outputs */
485 limit = &intel_limits_i9xx_sdvo;
486
487 return limit;
488 }
489
490 static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
491 {
492 struct drm_device *dev = crtc->base.dev;
493 const intel_limit_t *limit;
494
495 if (HAS_PCH_SPLIT(dev))
496 limit = intel_ironlake_limit(crtc, refclk);
497 else if (IS_G4X(dev)) {
498 limit = intel_g4x_limit(crtc);
499 } else if (IS_PINEVIEW(dev)) {
500 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
501 limit = &intel_limits_pineview_lvds;
502 else
503 limit = &intel_limits_pineview_sdvo;
504 } else if (IS_CHERRYVIEW(dev)) {
505 limit = &intel_limits_chv;
506 } else if (IS_VALLEYVIEW(dev)) {
507 limit = &intel_limits_vlv;
508 } else if (!IS_GEN2(dev)) {
509 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
510 limit = &intel_limits_i9xx_lvds;
511 else
512 limit = &intel_limits_i9xx_sdvo;
513 } else {
514 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
515 limit = &intel_limits_i8xx_lvds;
516 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
517 limit = &intel_limits_i8xx_dvo;
518 else
519 limit = &intel_limits_i8xx_dac;
520 }
521 return limit;
522 }
523
524 /* m1 is reserved as 0 in Pineview, n is a ring counter */
525 static void pineview_clock(int refclk, intel_clock_t *clock)
526 {
527 clock->m = clock->m2 + 2;
528 clock->p = clock->p1 * clock->p2;
529 if (WARN_ON(clock->n == 0 || clock->p == 0))
530 return;
531 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
532 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
533 }
534
535 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
536 {
537 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
538 }
539
540 static void i9xx_clock(int refclk, intel_clock_t *clock)
541 {
542 clock->m = i9xx_dpll_compute_m(clock);
543 clock->p = clock->p1 * clock->p2;
544 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
545 return;
546 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
547 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
548 }
549
550 static void chv_clock(int refclk, intel_clock_t *clock)
551 {
552 clock->m = clock->m1 * clock->m2;
553 clock->p = clock->p1 * clock->p2;
554 if (WARN_ON(clock->n == 0 || clock->p == 0))
555 return;
556 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
557 clock->n << 22);
558 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
559 }
560
561 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
562 /**
563 * Returns whether the given set of divisors are valid for a given refclk with
564 * the given connectors.
565 */
566
567 static bool intel_PLL_is_valid(struct drm_device *dev,
568 const intel_limit_t *limit,
569 const intel_clock_t *clock)
570 {
571 if (clock->n < limit->n.min || limit->n.max < clock->n)
572 INTELPllInvalid("n out of range\n");
573 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
574 INTELPllInvalid("p1 out of range\n");
575 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
576 INTELPllInvalid("m2 out of range\n");
577 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
578 INTELPllInvalid("m1 out of range\n");
579
580 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
581 if (clock->m1 <= clock->m2)
582 INTELPllInvalid("m1 <= m2\n");
583
584 if (!IS_VALLEYVIEW(dev)) {
585 if (clock->p < limit->p.min || limit->p.max < clock->p)
586 INTELPllInvalid("p out of range\n");
587 if (clock->m < limit->m.min || limit->m.max < clock->m)
588 INTELPllInvalid("m out of range\n");
589 }
590
591 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
592 INTELPllInvalid("vco out of range\n");
593 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
594 * connector, etc., rather than just a single range.
595 */
596 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
597 INTELPllInvalid("dot out of range\n");
598
599 return true;
600 }
601
602 static bool
603 i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
604 int target, int refclk, intel_clock_t *match_clock,
605 intel_clock_t *best_clock)
606 {
607 struct drm_device *dev = crtc->base.dev;
608 intel_clock_t clock;
609 int err = target;
610
611 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
612 /*
613 * For LVDS just rely on its current settings for dual-channel.
614 * We haven't figured out how to reliably set up different
615 * single/dual channel state, if we even can.
616 */
617 if (intel_is_dual_link_lvds(dev))
618 clock.p2 = limit->p2.p2_fast;
619 else
620 clock.p2 = limit->p2.p2_slow;
621 } else {
622 if (target < limit->p2.dot_limit)
623 clock.p2 = limit->p2.p2_slow;
624 else
625 clock.p2 = limit->p2.p2_fast;
626 }
627
628 memset(best_clock, 0, sizeof(*best_clock));
629
630 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
631 clock.m1++) {
632 for (clock.m2 = limit->m2.min;
633 clock.m2 <= limit->m2.max; clock.m2++) {
634 if (clock.m2 >= clock.m1)
635 break;
636 for (clock.n = limit->n.min;
637 clock.n <= limit->n.max; clock.n++) {
638 for (clock.p1 = limit->p1.min;
639 clock.p1 <= limit->p1.max; clock.p1++) {
640 int this_err;
641
642 i9xx_clock(refclk, &clock);
643 if (!intel_PLL_is_valid(dev, limit,
644 &clock))
645 continue;
646 if (match_clock &&
647 clock.p != match_clock->p)
648 continue;
649
650 this_err = abs(clock.dot - target);
651 if (this_err < err) {
652 *best_clock = clock;
653 err = this_err;
654 }
655 }
656 }
657 }
658 }
659
660 return (err != target);
661 }
662
663 static bool
664 pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
665 int target, int refclk, intel_clock_t *match_clock,
666 intel_clock_t *best_clock)
667 {
668 struct drm_device *dev = crtc->base.dev;
669 intel_clock_t clock;
670 int err = target;
671
672 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
673 /*
674 * For LVDS just rely on its current settings for dual-channel.
675 * We haven't figured out how to reliably set up different
676 * single/dual channel state, if we even can.
677 */
678 if (intel_is_dual_link_lvds(dev))
679 clock.p2 = limit->p2.p2_fast;
680 else
681 clock.p2 = limit->p2.p2_slow;
682 } else {
683 if (target < limit->p2.dot_limit)
684 clock.p2 = limit->p2.p2_slow;
685 else
686 clock.p2 = limit->p2.p2_fast;
687 }
688
689 memset(best_clock, 0, sizeof(*best_clock));
690
691 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
692 clock.m1++) {
693 for (clock.m2 = limit->m2.min;
694 clock.m2 <= limit->m2.max; clock.m2++) {
695 for (clock.n = limit->n.min;
696 clock.n <= limit->n.max; clock.n++) {
697 for (clock.p1 = limit->p1.min;
698 clock.p1 <= limit->p1.max; clock.p1++) {
699 int this_err;
700
701 pineview_clock(refclk, &clock);
702 if (!intel_PLL_is_valid(dev, limit,
703 &clock))
704 continue;
705 if (match_clock &&
706 clock.p != match_clock->p)
707 continue;
708
709 this_err = abs(clock.dot - target);
710 if (this_err < err) {
711 *best_clock = clock;
712 err = this_err;
713 }
714 }
715 }
716 }
717 }
718
719 return (err != target);
720 }
721
722 static bool
723 g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
724 int target, int refclk, intel_clock_t *match_clock,
725 intel_clock_t *best_clock)
726 {
727 struct drm_device *dev = crtc->base.dev;
728 intel_clock_t clock;
729 int max_n;
730 bool found;
731 /* approximately equals target * 0.00585 */
732 int err_most = (target >> 8) + (target >> 9);
733 found = false;
734
735 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
736 if (intel_is_dual_link_lvds(dev))
737 clock.p2 = limit->p2.p2_fast;
738 else
739 clock.p2 = limit->p2.p2_slow;
740 } else {
741 if (target < limit->p2.dot_limit)
742 clock.p2 = limit->p2.p2_slow;
743 else
744 clock.p2 = limit->p2.p2_fast;
745 }
746
747 memset(best_clock, 0, sizeof(*best_clock));
748 max_n = limit->n.max;
749 /* based on hardware requirement, prefer smaller n to precision */
750 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
751 /* based on hardware requirement, prefere larger m1,m2 */
752 for (clock.m1 = limit->m1.max;
753 clock.m1 >= limit->m1.min; clock.m1--) {
754 for (clock.m2 = limit->m2.max;
755 clock.m2 >= limit->m2.min; clock.m2--) {
756 for (clock.p1 = limit->p1.max;
757 clock.p1 >= limit->p1.min; clock.p1--) {
758 int this_err;
759
760 i9xx_clock(refclk, &clock);
761 if (!intel_PLL_is_valid(dev, limit,
762 &clock))
763 continue;
764
765 this_err = abs(clock.dot - target);
766 if (this_err < err_most) {
767 *best_clock = clock;
768 err_most = this_err;
769 max_n = clock.n;
770 found = true;
771 }
772 }
773 }
774 }
775 }
776 return found;
777 }
778
779 static bool
780 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
781 int target, int refclk, intel_clock_t *match_clock,
782 intel_clock_t *best_clock)
783 {
784 struct drm_device *dev = crtc->base.dev;
785 intel_clock_t clock;
786 unsigned int bestppm = 1000000;
787 /* min update 19.2 MHz */
788 int max_n = min(limit->n.max, refclk / 19200);
789 bool found = false;
790
791 target *= 5; /* fast clock */
792
793 memset(best_clock, 0, sizeof(*best_clock));
794
795 /* based on hardware requirement, prefer smaller n to precision */
796 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
797 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
798 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
799 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
800 clock.p = clock.p1 * clock.p2;
801 /* based on hardware requirement, prefer bigger m1,m2 values */
802 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
803 unsigned int ppm, diff;
804
805 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
806 refclk * clock.m1);
807
808 vlv_clock(refclk, &clock);
809
810 if (!intel_PLL_is_valid(dev, limit,
811 &clock))
812 continue;
813
814 diff = abs(clock.dot - target);
815 ppm = div_u64(1000000ULL * diff, target);
816
817 if (ppm < 100 && clock.p > best_clock->p) {
818 bestppm = 0;
819 *best_clock = clock;
820 found = true;
821 }
822
823 if (bestppm >= 10 && ppm < bestppm - 10) {
824 bestppm = ppm;
825 *best_clock = clock;
826 found = true;
827 }
828 }
829 }
830 }
831 }
832
833 return found;
834 }
835
836 static bool
837 chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
838 int target, int refclk, intel_clock_t *match_clock,
839 intel_clock_t *best_clock)
840 {
841 struct drm_device *dev = crtc->base.dev;
842 intel_clock_t clock;
843 uint64_t m2;
844 int found = false;
845
846 memset(best_clock, 0, sizeof(*best_clock));
847
848 /*
849 * Based on hardware doc, the n always set to 1, and m1 always
850 * set to 2. If requires to support 200Mhz refclk, we need to
851 * revisit this because n may not 1 anymore.
852 */
853 clock.n = 1, clock.m1 = 2;
854 target *= 5; /* fast clock */
855
856 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
857 for (clock.p2 = limit->p2.p2_fast;
858 clock.p2 >= limit->p2.p2_slow;
859 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
860
861 clock.p = clock.p1 * clock.p2;
862
863 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
864 clock.n) << 22, refclk * clock.m1);
865
866 if (m2 > INT_MAX/clock.m1)
867 continue;
868
869 clock.m2 = m2;
870
871 chv_clock(refclk, &clock);
872
873 if (!intel_PLL_is_valid(dev, limit, &clock))
874 continue;
875
876 /* based on hardware requirement, prefer bigger p
877 */
878 if (clock.p > best_clock->p) {
879 *best_clock = clock;
880 found = true;
881 }
882 }
883 }
884
885 return found;
886 }
887
888 bool intel_crtc_active(struct drm_crtc *crtc)
889 {
890 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
891
892 /* Be paranoid as we can arrive here with only partial
893 * state retrieved from the hardware during setup.
894 *
895 * We can ditch the adjusted_mode.crtc_clock check as soon
896 * as Haswell has gained clock readout/fastboot support.
897 *
898 * We can ditch the crtc->primary->fb check as soon as we can
899 * properly reconstruct framebuffers.
900 */
901 return intel_crtc->active && crtc->primary->fb &&
902 intel_crtc->config->base.adjusted_mode.crtc_clock;
903 }
904
905 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
906 enum pipe pipe)
907 {
908 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
909 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
910
911 return intel_crtc->config->cpu_transcoder;
912 }
913
914 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
915 {
916 struct drm_i915_private *dev_priv = dev->dev_private;
917 u32 reg = PIPEDSL(pipe);
918 u32 line1, line2;
919 u32 line_mask;
920
921 if (IS_GEN2(dev))
922 line_mask = DSL_LINEMASK_GEN2;
923 else
924 line_mask = DSL_LINEMASK_GEN3;
925
926 line1 = I915_READ(reg) & line_mask;
927 mdelay(5);
928 line2 = I915_READ(reg) & line_mask;
929
930 return line1 == line2;
931 }
932
933 /*
934 * intel_wait_for_pipe_off - wait for pipe to turn off
935 * @crtc: crtc whose pipe to wait for
936 *
937 * After disabling a pipe, we can't wait for vblank in the usual way,
938 * spinning on the vblank interrupt status bit, since we won't actually
939 * see an interrupt when the pipe is disabled.
940 *
941 * On Gen4 and above:
942 * wait for the pipe register state bit to turn off
943 *
944 * Otherwise:
945 * wait for the display line value to settle (it usually
946 * ends up stopping at the start of the next frame).
947 *
948 */
949 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
950 {
951 struct drm_device *dev = crtc->base.dev;
952 struct drm_i915_private *dev_priv = dev->dev_private;
953 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
954 enum pipe pipe = crtc->pipe;
955
956 if (INTEL_INFO(dev)->gen >= 4) {
957 int reg = PIPECONF(cpu_transcoder);
958
959 /* Wait for the Pipe State to go off */
960 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
961 100))
962 WARN(1, "pipe_off wait timed out\n");
963 } else {
964 /* Wait for the display line to settle */
965 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
966 WARN(1, "pipe_off wait timed out\n");
967 }
968 }
969
970 /*
971 * ibx_digital_port_connected - is the specified port connected?
972 * @dev_priv: i915 private structure
973 * @port: the port to test
974 *
975 * Returns true if @port is connected, false otherwise.
976 */
977 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
978 struct intel_digital_port *port)
979 {
980 u32 bit;
981
982 if (HAS_PCH_IBX(dev_priv->dev)) {
983 switch (port->port) {
984 case PORT_B:
985 bit = SDE_PORTB_HOTPLUG;
986 break;
987 case PORT_C:
988 bit = SDE_PORTC_HOTPLUG;
989 break;
990 case PORT_D:
991 bit = SDE_PORTD_HOTPLUG;
992 break;
993 default:
994 return true;
995 }
996 } else {
997 switch (port->port) {
998 case PORT_B:
999 bit = SDE_PORTB_HOTPLUG_CPT;
1000 break;
1001 case PORT_C:
1002 bit = SDE_PORTC_HOTPLUG_CPT;
1003 break;
1004 case PORT_D:
1005 bit = SDE_PORTD_HOTPLUG_CPT;
1006 break;
1007 default:
1008 return true;
1009 }
1010 }
1011
1012 return I915_READ(SDEISR) & bit;
1013 }
1014
1015 static const char *state_string(bool enabled)
1016 {
1017 return enabled ? "on" : "off";
1018 }
1019
1020 /* Only for pre-ILK configs */
1021 void assert_pll(struct drm_i915_private *dev_priv,
1022 enum pipe pipe, bool state)
1023 {
1024 int reg;
1025 u32 val;
1026 bool cur_state;
1027
1028 reg = DPLL(pipe);
1029 val = I915_READ(reg);
1030 cur_state = !!(val & DPLL_VCO_ENABLE);
1031 I915_STATE_WARN(cur_state != state,
1032 "PLL state assertion failure (expected %s, current %s)\n",
1033 state_string(state), state_string(cur_state));
1034 }
1035
1036 /* XXX: the dsi pll is shared between MIPI DSI ports */
1037 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1038 {
1039 u32 val;
1040 bool cur_state;
1041
1042 mutex_lock(&dev_priv->dpio_lock);
1043 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1044 mutex_unlock(&dev_priv->dpio_lock);
1045
1046 cur_state = val & DSI_PLL_VCO_EN;
1047 I915_STATE_WARN(cur_state != state,
1048 "DSI PLL state assertion failure (expected %s, current %s)\n",
1049 state_string(state), state_string(cur_state));
1050 }
1051 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1052 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1053
1054 struct intel_shared_dpll *
1055 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1056 {
1057 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1058
1059 if (crtc->config->shared_dpll < 0)
1060 return NULL;
1061
1062 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1063 }
1064
1065 /* For ILK+ */
1066 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1067 struct intel_shared_dpll *pll,
1068 bool state)
1069 {
1070 bool cur_state;
1071 struct intel_dpll_hw_state hw_state;
1072
1073 if (WARN (!pll,
1074 "asserting DPLL %s with no DPLL\n", state_string(state)))
1075 return;
1076
1077 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1078 I915_STATE_WARN(cur_state != state,
1079 "%s assertion failure (expected %s, current %s)\n",
1080 pll->name, state_string(state), state_string(cur_state));
1081 }
1082
1083 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1084 enum pipe pipe, bool state)
1085 {
1086 int reg;
1087 u32 val;
1088 bool cur_state;
1089 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1090 pipe);
1091
1092 if (HAS_DDI(dev_priv->dev)) {
1093 /* DDI does not have a specific FDI_TX register */
1094 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1095 val = I915_READ(reg);
1096 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1097 } else {
1098 reg = FDI_TX_CTL(pipe);
1099 val = I915_READ(reg);
1100 cur_state = !!(val & FDI_TX_ENABLE);
1101 }
1102 I915_STATE_WARN(cur_state != state,
1103 "FDI TX state assertion failure (expected %s, current %s)\n",
1104 state_string(state), state_string(cur_state));
1105 }
1106 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1107 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1108
1109 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1110 enum pipe pipe, bool state)
1111 {
1112 int reg;
1113 u32 val;
1114 bool cur_state;
1115
1116 reg = FDI_RX_CTL(pipe);
1117 val = I915_READ(reg);
1118 cur_state = !!(val & FDI_RX_ENABLE);
1119 I915_STATE_WARN(cur_state != state,
1120 "FDI RX state assertion failure (expected %s, current %s)\n",
1121 state_string(state), state_string(cur_state));
1122 }
1123 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1124 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1125
1126 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1127 enum pipe pipe)
1128 {
1129 int reg;
1130 u32 val;
1131
1132 /* ILK FDI PLL is always enabled */
1133 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1134 return;
1135
1136 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1137 if (HAS_DDI(dev_priv->dev))
1138 return;
1139
1140 reg = FDI_TX_CTL(pipe);
1141 val = I915_READ(reg);
1142 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1143 }
1144
1145 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1146 enum pipe pipe, bool state)
1147 {
1148 int reg;
1149 u32 val;
1150 bool cur_state;
1151
1152 reg = FDI_RX_CTL(pipe);
1153 val = I915_READ(reg);
1154 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1155 I915_STATE_WARN(cur_state != state,
1156 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1157 state_string(state), state_string(cur_state));
1158 }
1159
1160 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1161 enum pipe pipe)
1162 {
1163 struct drm_device *dev = dev_priv->dev;
1164 int pp_reg;
1165 u32 val;
1166 enum pipe panel_pipe = PIPE_A;
1167 bool locked = true;
1168
1169 if (WARN_ON(HAS_DDI(dev)))
1170 return;
1171
1172 if (HAS_PCH_SPLIT(dev)) {
1173 u32 port_sel;
1174
1175 pp_reg = PCH_PP_CONTROL;
1176 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1177
1178 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1179 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1180 panel_pipe = PIPE_B;
1181 /* XXX: else fix for eDP */
1182 } else if (IS_VALLEYVIEW(dev)) {
1183 /* presumably write lock depends on pipe, not port select */
1184 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1185 panel_pipe = pipe;
1186 } else {
1187 pp_reg = PP_CONTROL;
1188 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1189 panel_pipe = PIPE_B;
1190 }
1191
1192 val = I915_READ(pp_reg);
1193 if (!(val & PANEL_POWER_ON) ||
1194 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1195 locked = false;
1196
1197 I915_STATE_WARN(panel_pipe == pipe && locked,
1198 "panel assertion failure, pipe %c regs locked\n",
1199 pipe_name(pipe));
1200 }
1201
1202 static void assert_cursor(struct drm_i915_private *dev_priv,
1203 enum pipe pipe, bool state)
1204 {
1205 struct drm_device *dev = dev_priv->dev;
1206 bool cur_state;
1207
1208 if (IS_845G(dev) || IS_I865G(dev))
1209 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1210 else
1211 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1212
1213 I915_STATE_WARN(cur_state != state,
1214 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1215 pipe_name(pipe), state_string(state), state_string(cur_state));
1216 }
1217 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1218 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1219
1220 void assert_pipe(struct drm_i915_private *dev_priv,
1221 enum pipe pipe, bool state)
1222 {
1223 int reg;
1224 u32 val;
1225 bool cur_state;
1226 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1227 pipe);
1228
1229 /* if we need the pipe quirk it must be always on */
1230 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1231 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1232 state = true;
1233
1234 if (!intel_display_power_is_enabled(dev_priv,
1235 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1236 cur_state = false;
1237 } else {
1238 reg = PIPECONF(cpu_transcoder);
1239 val = I915_READ(reg);
1240 cur_state = !!(val & PIPECONF_ENABLE);
1241 }
1242
1243 I915_STATE_WARN(cur_state != state,
1244 "pipe %c assertion failure (expected %s, current %s)\n",
1245 pipe_name(pipe), state_string(state), state_string(cur_state));
1246 }
1247
1248 static void assert_plane(struct drm_i915_private *dev_priv,
1249 enum plane plane, bool state)
1250 {
1251 int reg;
1252 u32 val;
1253 bool cur_state;
1254
1255 reg = DSPCNTR(plane);
1256 val = I915_READ(reg);
1257 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1258 I915_STATE_WARN(cur_state != state,
1259 "plane %c assertion failure (expected %s, current %s)\n",
1260 plane_name(plane), state_string(state), state_string(cur_state));
1261 }
1262
1263 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1264 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1265
1266 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1267 enum pipe pipe)
1268 {
1269 struct drm_device *dev = dev_priv->dev;
1270 int reg, i;
1271 u32 val;
1272 int cur_pipe;
1273
1274 /* Primary planes are fixed to pipes on gen4+ */
1275 if (INTEL_INFO(dev)->gen >= 4) {
1276 reg = DSPCNTR(pipe);
1277 val = I915_READ(reg);
1278 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1279 "plane %c assertion failure, should be disabled but not\n",
1280 plane_name(pipe));
1281 return;
1282 }
1283
1284 /* Need to check both planes against the pipe */
1285 for_each_pipe(dev_priv, i) {
1286 reg = DSPCNTR(i);
1287 val = I915_READ(reg);
1288 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1289 DISPPLANE_SEL_PIPE_SHIFT;
1290 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1291 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1292 plane_name(i), pipe_name(pipe));
1293 }
1294 }
1295
1296 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1297 enum pipe pipe)
1298 {
1299 struct drm_device *dev = dev_priv->dev;
1300 int reg, sprite;
1301 u32 val;
1302
1303 if (INTEL_INFO(dev)->gen >= 9) {
1304 for_each_sprite(pipe, sprite) {
1305 val = I915_READ(PLANE_CTL(pipe, sprite));
1306 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1307 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1308 sprite, pipe_name(pipe));
1309 }
1310 } else if (IS_VALLEYVIEW(dev)) {
1311 for_each_sprite(pipe, sprite) {
1312 reg = SPCNTR(pipe, sprite);
1313 val = I915_READ(reg);
1314 I915_STATE_WARN(val & SP_ENABLE,
1315 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1316 sprite_name(pipe, sprite), pipe_name(pipe));
1317 }
1318 } else if (INTEL_INFO(dev)->gen >= 7) {
1319 reg = SPRCTL(pipe);
1320 val = I915_READ(reg);
1321 I915_STATE_WARN(val & SPRITE_ENABLE,
1322 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1323 plane_name(pipe), pipe_name(pipe));
1324 } else if (INTEL_INFO(dev)->gen >= 5) {
1325 reg = DVSCNTR(pipe);
1326 val = I915_READ(reg);
1327 I915_STATE_WARN(val & DVS_ENABLE,
1328 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1329 plane_name(pipe), pipe_name(pipe));
1330 }
1331 }
1332
1333 static void assert_vblank_disabled(struct drm_crtc *crtc)
1334 {
1335 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1336 drm_crtc_vblank_put(crtc);
1337 }
1338
1339 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1340 {
1341 u32 val;
1342 bool enabled;
1343
1344 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1345
1346 val = I915_READ(PCH_DREF_CONTROL);
1347 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1348 DREF_SUPERSPREAD_SOURCE_MASK));
1349 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1350 }
1351
1352 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1353 enum pipe pipe)
1354 {
1355 int reg;
1356 u32 val;
1357 bool enabled;
1358
1359 reg = PCH_TRANSCONF(pipe);
1360 val = I915_READ(reg);
1361 enabled = !!(val & TRANS_ENABLE);
1362 I915_STATE_WARN(enabled,
1363 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1364 pipe_name(pipe));
1365 }
1366
1367 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1368 enum pipe pipe, u32 port_sel, u32 val)
1369 {
1370 if ((val & DP_PORT_EN) == 0)
1371 return false;
1372
1373 if (HAS_PCH_CPT(dev_priv->dev)) {
1374 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1375 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1376 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1377 return false;
1378 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1379 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1380 return false;
1381 } else {
1382 if ((val & DP_PIPE_MASK) != (pipe << 30))
1383 return false;
1384 }
1385 return true;
1386 }
1387
1388 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1389 enum pipe pipe, u32 val)
1390 {
1391 if ((val & SDVO_ENABLE) == 0)
1392 return false;
1393
1394 if (HAS_PCH_CPT(dev_priv->dev)) {
1395 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1396 return false;
1397 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1398 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1399 return false;
1400 } else {
1401 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1402 return false;
1403 }
1404 return true;
1405 }
1406
1407 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1408 enum pipe pipe, u32 val)
1409 {
1410 if ((val & LVDS_PORT_EN) == 0)
1411 return false;
1412
1413 if (HAS_PCH_CPT(dev_priv->dev)) {
1414 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1415 return false;
1416 } else {
1417 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1418 return false;
1419 }
1420 return true;
1421 }
1422
1423 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1424 enum pipe pipe, u32 val)
1425 {
1426 if ((val & ADPA_DAC_ENABLE) == 0)
1427 return false;
1428 if (HAS_PCH_CPT(dev_priv->dev)) {
1429 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1430 return false;
1431 } else {
1432 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1433 return false;
1434 }
1435 return true;
1436 }
1437
1438 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1439 enum pipe pipe, int reg, u32 port_sel)
1440 {
1441 u32 val = I915_READ(reg);
1442 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1443 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1444 reg, pipe_name(pipe));
1445
1446 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1447 && (val & DP_PIPEB_SELECT),
1448 "IBX PCH dp port still using transcoder B\n");
1449 }
1450
1451 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1452 enum pipe pipe, int reg)
1453 {
1454 u32 val = I915_READ(reg);
1455 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1456 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1457 reg, pipe_name(pipe));
1458
1459 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1460 && (val & SDVO_PIPE_B_SELECT),
1461 "IBX PCH hdmi port still using transcoder B\n");
1462 }
1463
1464 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1465 enum pipe pipe)
1466 {
1467 int reg;
1468 u32 val;
1469
1470 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1471 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1472 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1473
1474 reg = PCH_ADPA;
1475 val = I915_READ(reg);
1476 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1477 "PCH VGA enabled on transcoder %c, should be disabled\n",
1478 pipe_name(pipe));
1479
1480 reg = PCH_LVDS;
1481 val = I915_READ(reg);
1482 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1483 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1484 pipe_name(pipe));
1485
1486 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1487 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1488 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1489 }
1490
1491 static void intel_init_dpio(struct drm_device *dev)
1492 {
1493 struct drm_i915_private *dev_priv = dev->dev_private;
1494
1495 if (!IS_VALLEYVIEW(dev))
1496 return;
1497
1498 /*
1499 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1500 * CHV x1 PHY (DP/HDMI D)
1501 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1502 */
1503 if (IS_CHERRYVIEW(dev)) {
1504 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1505 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1506 } else {
1507 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1508 }
1509 }
1510
1511 static void vlv_enable_pll(struct intel_crtc *crtc,
1512 const struct intel_crtc_state *pipe_config)
1513 {
1514 struct drm_device *dev = crtc->base.dev;
1515 struct drm_i915_private *dev_priv = dev->dev_private;
1516 int reg = DPLL(crtc->pipe);
1517 u32 dpll = pipe_config->dpll_hw_state.dpll;
1518
1519 assert_pipe_disabled(dev_priv, crtc->pipe);
1520
1521 /* No really, not for ILK+ */
1522 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1523
1524 /* PLL is protected by panel, make sure we can write it */
1525 if (IS_MOBILE(dev_priv->dev))
1526 assert_panel_unlocked(dev_priv, crtc->pipe);
1527
1528 I915_WRITE(reg, dpll);
1529 POSTING_READ(reg);
1530 udelay(150);
1531
1532 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1533 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1534
1535 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1536 POSTING_READ(DPLL_MD(crtc->pipe));
1537
1538 /* We do this three times for luck */
1539 I915_WRITE(reg, dpll);
1540 POSTING_READ(reg);
1541 udelay(150); /* wait for warmup */
1542 I915_WRITE(reg, dpll);
1543 POSTING_READ(reg);
1544 udelay(150); /* wait for warmup */
1545 I915_WRITE(reg, dpll);
1546 POSTING_READ(reg);
1547 udelay(150); /* wait for warmup */
1548 }
1549
1550 static void chv_enable_pll(struct intel_crtc *crtc,
1551 const struct intel_crtc_state *pipe_config)
1552 {
1553 struct drm_device *dev = crtc->base.dev;
1554 struct drm_i915_private *dev_priv = dev->dev_private;
1555 int pipe = crtc->pipe;
1556 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1557 u32 tmp;
1558
1559 assert_pipe_disabled(dev_priv, crtc->pipe);
1560
1561 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1562
1563 mutex_lock(&dev_priv->dpio_lock);
1564
1565 /* Enable back the 10bit clock to display controller */
1566 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1567 tmp |= DPIO_DCLKP_EN;
1568 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1569
1570 /*
1571 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1572 */
1573 udelay(1);
1574
1575 /* Enable PLL */
1576 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1577
1578 /* Check PLL is locked */
1579 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1580 DRM_ERROR("PLL %d failed to lock\n", pipe);
1581
1582 /* not sure when this should be written */
1583 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1584 POSTING_READ(DPLL_MD(pipe));
1585
1586 mutex_unlock(&dev_priv->dpio_lock);
1587 }
1588
1589 static int intel_num_dvo_pipes(struct drm_device *dev)
1590 {
1591 struct intel_crtc *crtc;
1592 int count = 0;
1593
1594 for_each_intel_crtc(dev, crtc)
1595 count += crtc->active &&
1596 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1597
1598 return count;
1599 }
1600
1601 static void i9xx_enable_pll(struct intel_crtc *crtc)
1602 {
1603 struct drm_device *dev = crtc->base.dev;
1604 struct drm_i915_private *dev_priv = dev->dev_private;
1605 int reg = DPLL(crtc->pipe);
1606 u32 dpll = crtc->config->dpll_hw_state.dpll;
1607
1608 assert_pipe_disabled(dev_priv, crtc->pipe);
1609
1610 /* No really, not for ILK+ */
1611 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1612
1613 /* PLL is protected by panel, make sure we can write it */
1614 if (IS_MOBILE(dev) && !IS_I830(dev))
1615 assert_panel_unlocked(dev_priv, crtc->pipe);
1616
1617 /* Enable DVO 2x clock on both PLLs if necessary */
1618 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1619 /*
1620 * It appears to be important that we don't enable this
1621 * for the current pipe before otherwise configuring the
1622 * PLL. No idea how this should be handled if multiple
1623 * DVO outputs are enabled simultaneosly.
1624 */
1625 dpll |= DPLL_DVO_2X_MODE;
1626 I915_WRITE(DPLL(!crtc->pipe),
1627 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1628 }
1629
1630 /* Wait for the clocks to stabilize. */
1631 POSTING_READ(reg);
1632 udelay(150);
1633
1634 if (INTEL_INFO(dev)->gen >= 4) {
1635 I915_WRITE(DPLL_MD(crtc->pipe),
1636 crtc->config->dpll_hw_state.dpll_md);
1637 } else {
1638 /* The pixel multiplier can only be updated once the
1639 * DPLL is enabled and the clocks are stable.
1640 *
1641 * So write it again.
1642 */
1643 I915_WRITE(reg, dpll);
1644 }
1645
1646 /* We do this three times for luck */
1647 I915_WRITE(reg, dpll);
1648 POSTING_READ(reg);
1649 udelay(150); /* wait for warmup */
1650 I915_WRITE(reg, dpll);
1651 POSTING_READ(reg);
1652 udelay(150); /* wait for warmup */
1653 I915_WRITE(reg, dpll);
1654 POSTING_READ(reg);
1655 udelay(150); /* wait for warmup */
1656 }
1657
1658 /**
1659 * i9xx_disable_pll - disable a PLL
1660 * @dev_priv: i915 private structure
1661 * @pipe: pipe PLL to disable
1662 *
1663 * Disable the PLL for @pipe, making sure the pipe is off first.
1664 *
1665 * Note! This is for pre-ILK only.
1666 */
1667 static void i9xx_disable_pll(struct intel_crtc *crtc)
1668 {
1669 struct drm_device *dev = crtc->base.dev;
1670 struct drm_i915_private *dev_priv = dev->dev_private;
1671 enum pipe pipe = crtc->pipe;
1672
1673 /* Disable DVO 2x clock on both PLLs if necessary */
1674 if (IS_I830(dev) &&
1675 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1676 intel_num_dvo_pipes(dev) == 1) {
1677 I915_WRITE(DPLL(PIPE_B),
1678 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1679 I915_WRITE(DPLL(PIPE_A),
1680 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1681 }
1682
1683 /* Don't disable pipe or pipe PLLs if needed */
1684 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1685 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1686 return;
1687
1688 /* Make sure the pipe isn't still relying on us */
1689 assert_pipe_disabled(dev_priv, pipe);
1690
1691 I915_WRITE(DPLL(pipe), 0);
1692 POSTING_READ(DPLL(pipe));
1693 }
1694
1695 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1696 {
1697 u32 val = 0;
1698
1699 /* Make sure the pipe isn't still relying on us */
1700 assert_pipe_disabled(dev_priv, pipe);
1701
1702 /*
1703 * Leave integrated clock source and reference clock enabled for pipe B.
1704 * The latter is needed for VGA hotplug / manual detection.
1705 */
1706 if (pipe == PIPE_B)
1707 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1708 I915_WRITE(DPLL(pipe), val);
1709 POSTING_READ(DPLL(pipe));
1710
1711 }
1712
1713 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1714 {
1715 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1716 u32 val;
1717
1718 /* Make sure the pipe isn't still relying on us */
1719 assert_pipe_disabled(dev_priv, pipe);
1720
1721 /* Set PLL en = 0 */
1722 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1723 if (pipe != PIPE_A)
1724 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1725 I915_WRITE(DPLL(pipe), val);
1726 POSTING_READ(DPLL(pipe));
1727
1728 mutex_lock(&dev_priv->dpio_lock);
1729
1730 /* Disable 10bit clock to display controller */
1731 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1732 val &= ~DPIO_DCLKP_EN;
1733 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1734
1735 /* disable left/right clock distribution */
1736 if (pipe != PIPE_B) {
1737 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1738 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1739 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1740 } else {
1741 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1742 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1743 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1744 }
1745
1746 mutex_unlock(&dev_priv->dpio_lock);
1747 }
1748
1749 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1750 struct intel_digital_port *dport)
1751 {
1752 u32 port_mask;
1753 int dpll_reg;
1754
1755 switch (dport->port) {
1756 case PORT_B:
1757 port_mask = DPLL_PORTB_READY_MASK;
1758 dpll_reg = DPLL(0);
1759 break;
1760 case PORT_C:
1761 port_mask = DPLL_PORTC_READY_MASK;
1762 dpll_reg = DPLL(0);
1763 break;
1764 case PORT_D:
1765 port_mask = DPLL_PORTD_READY_MASK;
1766 dpll_reg = DPIO_PHY_STATUS;
1767 break;
1768 default:
1769 BUG();
1770 }
1771
1772 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1773 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1774 port_name(dport->port), I915_READ(dpll_reg));
1775 }
1776
1777 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1778 {
1779 struct drm_device *dev = crtc->base.dev;
1780 struct drm_i915_private *dev_priv = dev->dev_private;
1781 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1782
1783 if (WARN_ON(pll == NULL))
1784 return;
1785
1786 WARN_ON(!pll->config.crtc_mask);
1787 if (pll->active == 0) {
1788 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1789 WARN_ON(pll->on);
1790 assert_shared_dpll_disabled(dev_priv, pll);
1791
1792 pll->mode_set(dev_priv, pll);
1793 }
1794 }
1795
1796 /**
1797 * intel_enable_shared_dpll - enable PCH PLL
1798 * @dev_priv: i915 private structure
1799 * @pipe: pipe PLL to enable
1800 *
1801 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1802 * drives the transcoder clock.
1803 */
1804 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1805 {
1806 struct drm_device *dev = crtc->base.dev;
1807 struct drm_i915_private *dev_priv = dev->dev_private;
1808 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1809
1810 if (WARN_ON(pll == NULL))
1811 return;
1812
1813 if (WARN_ON(pll->config.crtc_mask == 0))
1814 return;
1815
1816 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1817 pll->name, pll->active, pll->on,
1818 crtc->base.base.id);
1819
1820 if (pll->active++) {
1821 WARN_ON(!pll->on);
1822 assert_shared_dpll_enabled(dev_priv, pll);
1823 return;
1824 }
1825 WARN_ON(pll->on);
1826
1827 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1828
1829 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1830 pll->enable(dev_priv, pll);
1831 pll->on = true;
1832 }
1833
1834 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1835 {
1836 struct drm_device *dev = crtc->base.dev;
1837 struct drm_i915_private *dev_priv = dev->dev_private;
1838 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1839
1840 /* PCH only available on ILK+ */
1841 BUG_ON(INTEL_INFO(dev)->gen < 5);
1842 if (WARN_ON(pll == NULL))
1843 return;
1844
1845 if (WARN_ON(pll->config.crtc_mask == 0))
1846 return;
1847
1848 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1849 pll->name, pll->active, pll->on,
1850 crtc->base.base.id);
1851
1852 if (WARN_ON(pll->active == 0)) {
1853 assert_shared_dpll_disabled(dev_priv, pll);
1854 return;
1855 }
1856
1857 assert_shared_dpll_enabled(dev_priv, pll);
1858 WARN_ON(!pll->on);
1859 if (--pll->active)
1860 return;
1861
1862 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1863 pll->disable(dev_priv, pll);
1864 pll->on = false;
1865
1866 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1867 }
1868
1869 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1870 enum pipe pipe)
1871 {
1872 struct drm_device *dev = dev_priv->dev;
1873 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1874 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1875 uint32_t reg, val, pipeconf_val;
1876
1877 /* PCH only available on ILK+ */
1878 BUG_ON(!HAS_PCH_SPLIT(dev));
1879
1880 /* Make sure PCH DPLL is enabled */
1881 assert_shared_dpll_enabled(dev_priv,
1882 intel_crtc_to_shared_dpll(intel_crtc));
1883
1884 /* FDI must be feeding us bits for PCH ports */
1885 assert_fdi_tx_enabled(dev_priv, pipe);
1886 assert_fdi_rx_enabled(dev_priv, pipe);
1887
1888 if (HAS_PCH_CPT(dev)) {
1889 /* Workaround: Set the timing override bit before enabling the
1890 * pch transcoder. */
1891 reg = TRANS_CHICKEN2(pipe);
1892 val = I915_READ(reg);
1893 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1894 I915_WRITE(reg, val);
1895 }
1896
1897 reg = PCH_TRANSCONF(pipe);
1898 val = I915_READ(reg);
1899 pipeconf_val = I915_READ(PIPECONF(pipe));
1900
1901 if (HAS_PCH_IBX(dev_priv->dev)) {
1902 /*
1903 * make the BPC in transcoder be consistent with
1904 * that in pipeconf reg.
1905 */
1906 val &= ~PIPECONF_BPC_MASK;
1907 val |= pipeconf_val & PIPECONF_BPC_MASK;
1908 }
1909
1910 val &= ~TRANS_INTERLACE_MASK;
1911 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1912 if (HAS_PCH_IBX(dev_priv->dev) &&
1913 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1914 val |= TRANS_LEGACY_INTERLACED_ILK;
1915 else
1916 val |= TRANS_INTERLACED;
1917 else
1918 val |= TRANS_PROGRESSIVE;
1919
1920 I915_WRITE(reg, val | TRANS_ENABLE);
1921 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1922 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1923 }
1924
1925 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1926 enum transcoder cpu_transcoder)
1927 {
1928 u32 val, pipeconf_val;
1929
1930 /* PCH only available on ILK+ */
1931 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1932
1933 /* FDI must be feeding us bits for PCH ports */
1934 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1935 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1936
1937 /* Workaround: set timing override bit. */
1938 val = I915_READ(_TRANSA_CHICKEN2);
1939 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1940 I915_WRITE(_TRANSA_CHICKEN2, val);
1941
1942 val = TRANS_ENABLE;
1943 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1944
1945 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1946 PIPECONF_INTERLACED_ILK)
1947 val |= TRANS_INTERLACED;
1948 else
1949 val |= TRANS_PROGRESSIVE;
1950
1951 I915_WRITE(LPT_TRANSCONF, val);
1952 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1953 DRM_ERROR("Failed to enable PCH transcoder\n");
1954 }
1955
1956 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1957 enum pipe pipe)
1958 {
1959 struct drm_device *dev = dev_priv->dev;
1960 uint32_t reg, val;
1961
1962 /* FDI relies on the transcoder */
1963 assert_fdi_tx_disabled(dev_priv, pipe);
1964 assert_fdi_rx_disabled(dev_priv, pipe);
1965
1966 /* Ports must be off as well */
1967 assert_pch_ports_disabled(dev_priv, pipe);
1968
1969 reg = PCH_TRANSCONF(pipe);
1970 val = I915_READ(reg);
1971 val &= ~TRANS_ENABLE;
1972 I915_WRITE(reg, val);
1973 /* wait for PCH transcoder off, transcoder state */
1974 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1975 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1976
1977 if (!HAS_PCH_IBX(dev)) {
1978 /* Workaround: Clear the timing override chicken bit again. */
1979 reg = TRANS_CHICKEN2(pipe);
1980 val = I915_READ(reg);
1981 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1982 I915_WRITE(reg, val);
1983 }
1984 }
1985
1986 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1987 {
1988 u32 val;
1989
1990 val = I915_READ(LPT_TRANSCONF);
1991 val &= ~TRANS_ENABLE;
1992 I915_WRITE(LPT_TRANSCONF, val);
1993 /* wait for PCH transcoder off, transcoder state */
1994 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1995 DRM_ERROR("Failed to disable PCH transcoder\n");
1996
1997 /* Workaround: clear timing override bit. */
1998 val = I915_READ(_TRANSA_CHICKEN2);
1999 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2000 I915_WRITE(_TRANSA_CHICKEN2, val);
2001 }
2002
2003 /**
2004 * intel_enable_pipe - enable a pipe, asserting requirements
2005 * @crtc: crtc responsible for the pipe
2006 *
2007 * Enable @crtc's pipe, making sure that various hardware specific requirements
2008 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2009 */
2010 static void intel_enable_pipe(struct intel_crtc *crtc)
2011 {
2012 struct drm_device *dev = crtc->base.dev;
2013 struct drm_i915_private *dev_priv = dev->dev_private;
2014 enum pipe pipe = crtc->pipe;
2015 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2016 pipe);
2017 enum pipe pch_transcoder;
2018 int reg;
2019 u32 val;
2020
2021 assert_planes_disabled(dev_priv, pipe);
2022 assert_cursor_disabled(dev_priv, pipe);
2023 assert_sprites_disabled(dev_priv, pipe);
2024
2025 if (HAS_PCH_LPT(dev_priv->dev))
2026 pch_transcoder = TRANSCODER_A;
2027 else
2028 pch_transcoder = pipe;
2029
2030 /*
2031 * A pipe without a PLL won't actually be able to drive bits from
2032 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2033 * need the check.
2034 */
2035 if (!HAS_PCH_SPLIT(dev_priv->dev))
2036 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2037 assert_dsi_pll_enabled(dev_priv);
2038 else
2039 assert_pll_enabled(dev_priv, pipe);
2040 else {
2041 if (crtc->config->has_pch_encoder) {
2042 /* if driving the PCH, we need FDI enabled */
2043 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2044 assert_fdi_tx_pll_enabled(dev_priv,
2045 (enum pipe) cpu_transcoder);
2046 }
2047 /* FIXME: assert CPU port conditions for SNB+ */
2048 }
2049
2050 reg = PIPECONF(cpu_transcoder);
2051 val = I915_READ(reg);
2052 if (val & PIPECONF_ENABLE) {
2053 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2054 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2055 return;
2056 }
2057
2058 I915_WRITE(reg, val | PIPECONF_ENABLE);
2059 POSTING_READ(reg);
2060 }
2061
2062 /**
2063 * intel_disable_pipe - disable a pipe, asserting requirements
2064 * @crtc: crtc whose pipes is to be disabled
2065 *
2066 * Disable the pipe of @crtc, making sure that various hardware
2067 * specific requirements are met, if applicable, e.g. plane
2068 * disabled, panel fitter off, etc.
2069 *
2070 * Will wait until the pipe has shut down before returning.
2071 */
2072 static void intel_disable_pipe(struct intel_crtc *crtc)
2073 {
2074 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2075 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2076 enum pipe pipe = crtc->pipe;
2077 int reg;
2078 u32 val;
2079
2080 /*
2081 * Make sure planes won't keep trying to pump pixels to us,
2082 * or we might hang the display.
2083 */
2084 assert_planes_disabled(dev_priv, pipe);
2085 assert_cursor_disabled(dev_priv, pipe);
2086 assert_sprites_disabled(dev_priv, pipe);
2087
2088 reg = PIPECONF(cpu_transcoder);
2089 val = I915_READ(reg);
2090 if ((val & PIPECONF_ENABLE) == 0)
2091 return;
2092
2093 /*
2094 * Double wide has implications for planes
2095 * so best keep it disabled when not needed.
2096 */
2097 if (crtc->config->double_wide)
2098 val &= ~PIPECONF_DOUBLE_WIDE;
2099
2100 /* Don't disable pipe or pipe PLLs if needed */
2101 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2102 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2103 val &= ~PIPECONF_ENABLE;
2104
2105 I915_WRITE(reg, val);
2106 if ((val & PIPECONF_ENABLE) == 0)
2107 intel_wait_for_pipe_off(crtc);
2108 }
2109
2110 /*
2111 * Plane regs are double buffered, going from enabled->disabled needs a
2112 * trigger in order to latch. The display address reg provides this.
2113 */
2114 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2115 enum plane plane)
2116 {
2117 struct drm_device *dev = dev_priv->dev;
2118 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2119
2120 I915_WRITE(reg, I915_READ(reg));
2121 POSTING_READ(reg);
2122 }
2123
2124 /**
2125 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2126 * @plane: plane to be enabled
2127 * @crtc: crtc for the plane
2128 *
2129 * Enable @plane on @crtc, making sure that the pipe is running first.
2130 */
2131 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2132 struct drm_crtc *crtc)
2133 {
2134 struct drm_device *dev = plane->dev;
2135 struct drm_i915_private *dev_priv = dev->dev_private;
2136 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2137
2138 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2139 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2140
2141 if (intel_crtc->primary_enabled)
2142 return;
2143
2144 intel_crtc->primary_enabled = true;
2145
2146 dev_priv->display.update_primary_plane(crtc, plane->fb,
2147 crtc->x, crtc->y);
2148
2149 /*
2150 * BDW signals flip done immediately if the plane
2151 * is disabled, even if the plane enable is already
2152 * armed to occur at the next vblank :(
2153 */
2154 if (IS_BROADWELL(dev))
2155 intel_wait_for_vblank(dev, intel_crtc->pipe);
2156 }
2157
2158 /**
2159 * intel_disable_primary_hw_plane - disable the primary hardware plane
2160 * @plane: plane to be disabled
2161 * @crtc: crtc for the plane
2162 *
2163 * Disable @plane on @crtc, making sure that the pipe is running first.
2164 */
2165 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2166 struct drm_crtc *crtc)
2167 {
2168 struct drm_device *dev = plane->dev;
2169 struct drm_i915_private *dev_priv = dev->dev_private;
2170 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2171
2172 if (WARN_ON(!intel_crtc->active))
2173 return;
2174
2175 if (!intel_crtc->primary_enabled)
2176 return;
2177
2178 intel_crtc->primary_enabled = false;
2179
2180 dev_priv->display.update_primary_plane(crtc, plane->fb,
2181 crtc->x, crtc->y);
2182 }
2183
2184 static bool need_vtd_wa(struct drm_device *dev)
2185 {
2186 #ifdef CONFIG_INTEL_IOMMU
2187 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2188 return true;
2189 #endif
2190 return false;
2191 }
2192
2193 int
2194 intel_fb_align_height(struct drm_device *dev, int height, unsigned int tiling)
2195 {
2196 int tile_height;
2197
2198 tile_height = tiling ? (IS_GEN2(dev) ? 16 : 8) : 1;
2199 return ALIGN(height, tile_height);
2200 }
2201
2202 int
2203 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2204 struct drm_framebuffer *fb,
2205 struct intel_engine_cs *pipelined)
2206 {
2207 struct drm_device *dev = fb->dev;
2208 struct drm_i915_private *dev_priv = dev->dev_private;
2209 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2210 u32 alignment;
2211 int ret;
2212
2213 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2214
2215 switch (obj->tiling_mode) {
2216 case I915_TILING_NONE:
2217 if (INTEL_INFO(dev)->gen >= 9)
2218 alignment = 256 * 1024;
2219 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2220 alignment = 128 * 1024;
2221 else if (INTEL_INFO(dev)->gen >= 4)
2222 alignment = 4 * 1024;
2223 else
2224 alignment = 64 * 1024;
2225 break;
2226 case I915_TILING_X:
2227 if (INTEL_INFO(dev)->gen >= 9)
2228 alignment = 256 * 1024;
2229 else {
2230 /* pin() will align the object as required by fence */
2231 alignment = 0;
2232 }
2233 break;
2234 case I915_TILING_Y:
2235 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2236 return -EINVAL;
2237 default:
2238 BUG();
2239 }
2240
2241 /* Note that the w/a also requires 64 PTE of padding following the
2242 * bo. We currently fill all unused PTE with the shadow page and so
2243 * we should always have valid PTE following the scanout preventing
2244 * the VT-d warning.
2245 */
2246 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2247 alignment = 256 * 1024;
2248
2249 /*
2250 * Global gtt pte registers are special registers which actually forward
2251 * writes to a chunk of system memory. Which means that there is no risk
2252 * that the register values disappear as soon as we call
2253 * intel_runtime_pm_put(), so it is correct to wrap only the
2254 * pin/unpin/fence and not more.
2255 */
2256 intel_runtime_pm_get(dev_priv);
2257
2258 dev_priv->mm.interruptible = false;
2259 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2260 if (ret)
2261 goto err_interruptible;
2262
2263 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2264 * fence, whereas 965+ only requires a fence if using
2265 * framebuffer compression. For simplicity, we always install
2266 * a fence as the cost is not that onerous.
2267 */
2268 ret = i915_gem_object_get_fence(obj);
2269 if (ret)
2270 goto err_unpin;
2271
2272 i915_gem_object_pin_fence(obj);
2273
2274 dev_priv->mm.interruptible = true;
2275 intel_runtime_pm_put(dev_priv);
2276 return 0;
2277
2278 err_unpin:
2279 i915_gem_object_unpin_from_display_plane(obj);
2280 err_interruptible:
2281 dev_priv->mm.interruptible = true;
2282 intel_runtime_pm_put(dev_priv);
2283 return ret;
2284 }
2285
2286 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2287 {
2288 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2289
2290 i915_gem_object_unpin_fence(obj);
2291 i915_gem_object_unpin_from_display_plane(obj);
2292 }
2293
2294 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2295 * is assumed to be a power-of-two. */
2296 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2297 unsigned int tiling_mode,
2298 unsigned int cpp,
2299 unsigned int pitch)
2300 {
2301 if (tiling_mode != I915_TILING_NONE) {
2302 unsigned int tile_rows, tiles;
2303
2304 tile_rows = *y / 8;
2305 *y %= 8;
2306
2307 tiles = *x / (512/cpp);
2308 *x %= 512/cpp;
2309
2310 return tile_rows * pitch * 8 + tiles * 4096;
2311 } else {
2312 unsigned int offset;
2313
2314 offset = *y * pitch + *x * cpp;
2315 *y = 0;
2316 *x = (offset & 4095) / cpp;
2317 return offset & -4096;
2318 }
2319 }
2320
2321 static int i9xx_format_to_fourcc(int format)
2322 {
2323 switch (format) {
2324 case DISPPLANE_8BPP:
2325 return DRM_FORMAT_C8;
2326 case DISPPLANE_BGRX555:
2327 return DRM_FORMAT_XRGB1555;
2328 case DISPPLANE_BGRX565:
2329 return DRM_FORMAT_RGB565;
2330 default:
2331 case DISPPLANE_BGRX888:
2332 return DRM_FORMAT_XRGB8888;
2333 case DISPPLANE_RGBX888:
2334 return DRM_FORMAT_XBGR8888;
2335 case DISPPLANE_BGRX101010:
2336 return DRM_FORMAT_XRGB2101010;
2337 case DISPPLANE_RGBX101010:
2338 return DRM_FORMAT_XBGR2101010;
2339 }
2340 }
2341
2342 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2343 {
2344 switch (format) {
2345 case PLANE_CTL_FORMAT_RGB_565:
2346 return DRM_FORMAT_RGB565;
2347 default:
2348 case PLANE_CTL_FORMAT_XRGB_8888:
2349 if (rgb_order) {
2350 if (alpha)
2351 return DRM_FORMAT_ABGR8888;
2352 else
2353 return DRM_FORMAT_XBGR8888;
2354 } else {
2355 if (alpha)
2356 return DRM_FORMAT_ARGB8888;
2357 else
2358 return DRM_FORMAT_XRGB8888;
2359 }
2360 case PLANE_CTL_FORMAT_XRGB_2101010:
2361 if (rgb_order)
2362 return DRM_FORMAT_XBGR2101010;
2363 else
2364 return DRM_FORMAT_XRGB2101010;
2365 }
2366 }
2367
2368 static bool
2369 intel_alloc_plane_obj(struct intel_crtc *crtc,
2370 struct intel_initial_plane_config *plane_config)
2371 {
2372 struct drm_device *dev = crtc->base.dev;
2373 struct drm_i915_gem_object *obj = NULL;
2374 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2375 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2376 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2377 PAGE_SIZE);
2378
2379 size_aligned -= base_aligned;
2380
2381 if (plane_config->size == 0)
2382 return false;
2383
2384 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2385 base_aligned,
2386 base_aligned,
2387 size_aligned);
2388 if (!obj)
2389 return false;
2390
2391 obj->tiling_mode = plane_config->tiling;
2392 if (obj->tiling_mode == I915_TILING_X)
2393 obj->stride = crtc->base.primary->fb->pitches[0];
2394
2395 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2396 mode_cmd.width = crtc->base.primary->fb->width;
2397 mode_cmd.height = crtc->base.primary->fb->height;
2398 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2399
2400 mutex_lock(&dev->struct_mutex);
2401
2402 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2403 &mode_cmd, obj)) {
2404 DRM_DEBUG_KMS("intel fb init failed\n");
2405 goto out_unref_obj;
2406 }
2407
2408 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2409 mutex_unlock(&dev->struct_mutex);
2410
2411 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2412 return true;
2413
2414 out_unref_obj:
2415 drm_gem_object_unreference(&obj->base);
2416 mutex_unlock(&dev->struct_mutex);
2417 return false;
2418 }
2419
2420 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2421 static void
2422 update_state_fb(struct drm_plane *plane)
2423 {
2424 if (plane->fb != plane->state->fb)
2425 drm_atomic_set_fb_for_plane(plane->state, plane->fb);
2426 }
2427
2428 static void
2429 intel_find_plane_obj(struct intel_crtc *intel_crtc,
2430 struct intel_initial_plane_config *plane_config)
2431 {
2432 struct drm_device *dev = intel_crtc->base.dev;
2433 struct drm_i915_private *dev_priv = dev->dev_private;
2434 struct drm_crtc *c;
2435 struct intel_crtc *i;
2436 struct drm_i915_gem_object *obj;
2437
2438 if (!intel_crtc->base.primary->fb)
2439 return;
2440
2441 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2442 return;
2443
2444 kfree(intel_crtc->base.primary->fb);
2445 intel_crtc->base.primary->fb = NULL;
2446
2447 /*
2448 * Failed to alloc the obj, check to see if we should share
2449 * an fb with another CRTC instead
2450 */
2451 for_each_crtc(dev, c) {
2452 i = to_intel_crtc(c);
2453
2454 if (c == &intel_crtc->base)
2455 continue;
2456
2457 if (!i->active)
2458 continue;
2459
2460 obj = intel_fb_obj(c->primary->fb);
2461 if (obj == NULL)
2462 continue;
2463
2464 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2465 if (obj->tiling_mode != I915_TILING_NONE)
2466 dev_priv->preserve_bios_swizzle = true;
2467
2468 drm_framebuffer_reference(c->primary->fb);
2469 intel_crtc->base.primary->fb = c->primary->fb;
2470 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2471 break;
2472 }
2473 }
2474
2475 update_state_fb(intel_crtc->base.primary);
2476 }
2477
2478 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2479 struct drm_framebuffer *fb,
2480 int x, int y)
2481 {
2482 struct drm_device *dev = crtc->dev;
2483 struct drm_i915_private *dev_priv = dev->dev_private;
2484 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2485 struct drm_i915_gem_object *obj;
2486 int plane = intel_crtc->plane;
2487 unsigned long linear_offset;
2488 u32 dspcntr;
2489 u32 reg = DSPCNTR(plane);
2490 int pixel_size;
2491
2492 if (!intel_crtc->primary_enabled) {
2493 I915_WRITE(reg, 0);
2494 if (INTEL_INFO(dev)->gen >= 4)
2495 I915_WRITE(DSPSURF(plane), 0);
2496 else
2497 I915_WRITE(DSPADDR(plane), 0);
2498 POSTING_READ(reg);
2499 return;
2500 }
2501
2502 obj = intel_fb_obj(fb);
2503 if (WARN_ON(obj == NULL))
2504 return;
2505
2506 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2507
2508 dspcntr = DISPPLANE_GAMMA_ENABLE;
2509
2510 dspcntr |= DISPLAY_PLANE_ENABLE;
2511
2512 if (INTEL_INFO(dev)->gen < 4) {
2513 if (intel_crtc->pipe == PIPE_B)
2514 dspcntr |= DISPPLANE_SEL_PIPE_B;
2515
2516 /* pipesrc and dspsize control the size that is scaled from,
2517 * which should always be the user's requested size.
2518 */
2519 I915_WRITE(DSPSIZE(plane),
2520 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2521 (intel_crtc->config->pipe_src_w - 1));
2522 I915_WRITE(DSPPOS(plane), 0);
2523 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2524 I915_WRITE(PRIMSIZE(plane),
2525 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2526 (intel_crtc->config->pipe_src_w - 1));
2527 I915_WRITE(PRIMPOS(plane), 0);
2528 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2529 }
2530
2531 switch (fb->pixel_format) {
2532 case DRM_FORMAT_C8:
2533 dspcntr |= DISPPLANE_8BPP;
2534 break;
2535 case DRM_FORMAT_XRGB1555:
2536 case DRM_FORMAT_ARGB1555:
2537 dspcntr |= DISPPLANE_BGRX555;
2538 break;
2539 case DRM_FORMAT_RGB565:
2540 dspcntr |= DISPPLANE_BGRX565;
2541 break;
2542 case DRM_FORMAT_XRGB8888:
2543 case DRM_FORMAT_ARGB8888:
2544 dspcntr |= DISPPLANE_BGRX888;
2545 break;
2546 case DRM_FORMAT_XBGR8888:
2547 case DRM_FORMAT_ABGR8888:
2548 dspcntr |= DISPPLANE_RGBX888;
2549 break;
2550 case DRM_FORMAT_XRGB2101010:
2551 case DRM_FORMAT_ARGB2101010:
2552 dspcntr |= DISPPLANE_BGRX101010;
2553 break;
2554 case DRM_FORMAT_XBGR2101010:
2555 case DRM_FORMAT_ABGR2101010:
2556 dspcntr |= DISPPLANE_RGBX101010;
2557 break;
2558 default:
2559 BUG();
2560 }
2561
2562 if (INTEL_INFO(dev)->gen >= 4 &&
2563 obj->tiling_mode != I915_TILING_NONE)
2564 dspcntr |= DISPPLANE_TILED;
2565
2566 if (IS_G4X(dev))
2567 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2568
2569 linear_offset = y * fb->pitches[0] + x * pixel_size;
2570
2571 if (INTEL_INFO(dev)->gen >= 4) {
2572 intel_crtc->dspaddr_offset =
2573 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2574 pixel_size,
2575 fb->pitches[0]);
2576 linear_offset -= intel_crtc->dspaddr_offset;
2577 } else {
2578 intel_crtc->dspaddr_offset = linear_offset;
2579 }
2580
2581 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2582 dspcntr |= DISPPLANE_ROTATE_180;
2583
2584 x += (intel_crtc->config->pipe_src_w - 1);
2585 y += (intel_crtc->config->pipe_src_h - 1);
2586
2587 /* Finding the last pixel of the last line of the display
2588 data and adding to linear_offset*/
2589 linear_offset +=
2590 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2591 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2592 }
2593
2594 I915_WRITE(reg, dspcntr);
2595
2596 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2597 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2598 fb->pitches[0]);
2599 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2600 if (INTEL_INFO(dev)->gen >= 4) {
2601 I915_WRITE(DSPSURF(plane),
2602 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2603 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2604 I915_WRITE(DSPLINOFF(plane), linear_offset);
2605 } else
2606 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2607 POSTING_READ(reg);
2608 }
2609
2610 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2611 struct drm_framebuffer *fb,
2612 int x, int y)
2613 {
2614 struct drm_device *dev = crtc->dev;
2615 struct drm_i915_private *dev_priv = dev->dev_private;
2616 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2617 struct drm_i915_gem_object *obj;
2618 int plane = intel_crtc->plane;
2619 unsigned long linear_offset;
2620 u32 dspcntr;
2621 u32 reg = DSPCNTR(plane);
2622 int pixel_size;
2623
2624 if (!intel_crtc->primary_enabled) {
2625 I915_WRITE(reg, 0);
2626 I915_WRITE(DSPSURF(plane), 0);
2627 POSTING_READ(reg);
2628 return;
2629 }
2630
2631 obj = intel_fb_obj(fb);
2632 if (WARN_ON(obj == NULL))
2633 return;
2634
2635 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2636
2637 dspcntr = DISPPLANE_GAMMA_ENABLE;
2638
2639 dspcntr |= DISPLAY_PLANE_ENABLE;
2640
2641 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2642 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2643
2644 switch (fb->pixel_format) {
2645 case DRM_FORMAT_C8:
2646 dspcntr |= DISPPLANE_8BPP;
2647 break;
2648 case DRM_FORMAT_RGB565:
2649 dspcntr |= DISPPLANE_BGRX565;
2650 break;
2651 case DRM_FORMAT_XRGB8888:
2652 case DRM_FORMAT_ARGB8888:
2653 dspcntr |= DISPPLANE_BGRX888;
2654 break;
2655 case DRM_FORMAT_XBGR8888:
2656 case DRM_FORMAT_ABGR8888:
2657 dspcntr |= DISPPLANE_RGBX888;
2658 break;
2659 case DRM_FORMAT_XRGB2101010:
2660 case DRM_FORMAT_ARGB2101010:
2661 dspcntr |= DISPPLANE_BGRX101010;
2662 break;
2663 case DRM_FORMAT_XBGR2101010:
2664 case DRM_FORMAT_ABGR2101010:
2665 dspcntr |= DISPPLANE_RGBX101010;
2666 break;
2667 default:
2668 BUG();
2669 }
2670
2671 if (obj->tiling_mode != I915_TILING_NONE)
2672 dspcntr |= DISPPLANE_TILED;
2673
2674 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2675 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2676
2677 linear_offset = y * fb->pitches[0] + x * pixel_size;
2678 intel_crtc->dspaddr_offset =
2679 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2680 pixel_size,
2681 fb->pitches[0]);
2682 linear_offset -= intel_crtc->dspaddr_offset;
2683 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2684 dspcntr |= DISPPLANE_ROTATE_180;
2685
2686 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2687 x += (intel_crtc->config->pipe_src_w - 1);
2688 y += (intel_crtc->config->pipe_src_h - 1);
2689
2690 /* Finding the last pixel of the last line of the display
2691 data and adding to linear_offset*/
2692 linear_offset +=
2693 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2694 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2695 }
2696 }
2697
2698 I915_WRITE(reg, dspcntr);
2699
2700 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2701 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2702 fb->pitches[0]);
2703 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2704 I915_WRITE(DSPSURF(plane),
2705 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2706 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2707 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2708 } else {
2709 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2710 I915_WRITE(DSPLINOFF(plane), linear_offset);
2711 }
2712 POSTING_READ(reg);
2713 }
2714
2715 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2716 struct drm_framebuffer *fb,
2717 int x, int y)
2718 {
2719 struct drm_device *dev = crtc->dev;
2720 struct drm_i915_private *dev_priv = dev->dev_private;
2721 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2722 struct intel_framebuffer *intel_fb;
2723 struct drm_i915_gem_object *obj;
2724 int pipe = intel_crtc->pipe;
2725 u32 plane_ctl, stride;
2726
2727 if (!intel_crtc->primary_enabled) {
2728 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2729 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2730 POSTING_READ(PLANE_CTL(pipe, 0));
2731 return;
2732 }
2733
2734 plane_ctl = PLANE_CTL_ENABLE |
2735 PLANE_CTL_PIPE_GAMMA_ENABLE |
2736 PLANE_CTL_PIPE_CSC_ENABLE;
2737
2738 switch (fb->pixel_format) {
2739 case DRM_FORMAT_RGB565:
2740 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2741 break;
2742 case DRM_FORMAT_XRGB8888:
2743 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2744 break;
2745 case DRM_FORMAT_ARGB8888:
2746 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2747 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2748 break;
2749 case DRM_FORMAT_XBGR8888:
2750 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2751 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2752 break;
2753 case DRM_FORMAT_ABGR8888:
2754 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2755 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2756 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2757 break;
2758 case DRM_FORMAT_XRGB2101010:
2759 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2760 break;
2761 case DRM_FORMAT_XBGR2101010:
2762 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2763 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2764 break;
2765 default:
2766 BUG();
2767 }
2768
2769 intel_fb = to_intel_framebuffer(fb);
2770 obj = intel_fb->obj;
2771
2772 /*
2773 * The stride is either expressed as a multiple of 64 bytes chunks for
2774 * linear buffers or in number of tiles for tiled buffers.
2775 */
2776 switch (obj->tiling_mode) {
2777 case I915_TILING_NONE:
2778 stride = fb->pitches[0] >> 6;
2779 break;
2780 case I915_TILING_X:
2781 plane_ctl |= PLANE_CTL_TILED_X;
2782 stride = fb->pitches[0] >> 9;
2783 break;
2784 default:
2785 BUG();
2786 }
2787
2788 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2789 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180))
2790 plane_ctl |= PLANE_CTL_ROTATE_180;
2791
2792 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2793
2794 DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2795 i915_gem_obj_ggtt_offset(obj),
2796 x, y, fb->width, fb->height,
2797 fb->pitches[0]);
2798
2799 I915_WRITE(PLANE_POS(pipe, 0), 0);
2800 I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2801 I915_WRITE(PLANE_SIZE(pipe, 0),
2802 (intel_crtc->config->pipe_src_h - 1) << 16 |
2803 (intel_crtc->config->pipe_src_w - 1));
2804 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
2805 I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2806
2807 POSTING_READ(PLANE_SURF(pipe, 0));
2808 }
2809
2810 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2811 static int
2812 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2813 int x, int y, enum mode_set_atomic state)
2814 {
2815 struct drm_device *dev = crtc->dev;
2816 struct drm_i915_private *dev_priv = dev->dev_private;
2817
2818 if (dev_priv->display.disable_fbc)
2819 dev_priv->display.disable_fbc(dev);
2820
2821 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2822
2823 return 0;
2824 }
2825
2826 static void intel_complete_page_flips(struct drm_device *dev)
2827 {
2828 struct drm_crtc *crtc;
2829
2830 for_each_crtc(dev, crtc) {
2831 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2832 enum plane plane = intel_crtc->plane;
2833
2834 intel_prepare_page_flip(dev, plane);
2835 intel_finish_page_flip_plane(dev, plane);
2836 }
2837 }
2838
2839 static void intel_update_primary_planes(struct drm_device *dev)
2840 {
2841 struct drm_i915_private *dev_priv = dev->dev_private;
2842 struct drm_crtc *crtc;
2843
2844 for_each_crtc(dev, crtc) {
2845 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2846
2847 drm_modeset_lock(&crtc->mutex, NULL);
2848 /*
2849 * FIXME: Once we have proper support for primary planes (and
2850 * disabling them without disabling the entire crtc) allow again
2851 * a NULL crtc->primary->fb.
2852 */
2853 if (intel_crtc->active && crtc->primary->fb)
2854 dev_priv->display.update_primary_plane(crtc,
2855 crtc->primary->fb,
2856 crtc->x,
2857 crtc->y);
2858 drm_modeset_unlock(&crtc->mutex);
2859 }
2860 }
2861
2862 void intel_prepare_reset(struct drm_device *dev)
2863 {
2864 struct drm_i915_private *dev_priv = to_i915(dev);
2865 struct intel_crtc *crtc;
2866
2867 /* no reset support for gen2 */
2868 if (IS_GEN2(dev))
2869 return;
2870
2871 /* reset doesn't touch the display */
2872 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
2873 return;
2874
2875 drm_modeset_lock_all(dev);
2876
2877 /*
2878 * Disabling the crtcs gracefully seems nicer. Also the
2879 * g33 docs say we should at least disable all the planes.
2880 */
2881 for_each_intel_crtc(dev, crtc) {
2882 if (crtc->active)
2883 dev_priv->display.crtc_disable(&crtc->base);
2884 }
2885 }
2886
2887 void intel_finish_reset(struct drm_device *dev)
2888 {
2889 struct drm_i915_private *dev_priv = to_i915(dev);
2890
2891 /*
2892 * Flips in the rings will be nuked by the reset,
2893 * so complete all pending flips so that user space
2894 * will get its events and not get stuck.
2895 */
2896 intel_complete_page_flips(dev);
2897
2898 /* no reset support for gen2 */
2899 if (IS_GEN2(dev))
2900 return;
2901
2902 /* reset doesn't touch the display */
2903 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
2904 /*
2905 * Flips in the rings have been nuked by the reset,
2906 * so update the base address of all primary
2907 * planes to the the last fb to make sure we're
2908 * showing the correct fb after a reset.
2909 */
2910 intel_update_primary_planes(dev);
2911 return;
2912 }
2913
2914 /*
2915 * The display has been reset as well,
2916 * so need a full re-initialization.
2917 */
2918 intel_runtime_pm_disable_interrupts(dev_priv);
2919 intel_runtime_pm_enable_interrupts(dev_priv);
2920
2921 intel_modeset_init_hw(dev);
2922
2923 spin_lock_irq(&dev_priv->irq_lock);
2924 if (dev_priv->display.hpd_irq_setup)
2925 dev_priv->display.hpd_irq_setup(dev);
2926 spin_unlock_irq(&dev_priv->irq_lock);
2927
2928 intel_modeset_setup_hw_state(dev, true);
2929
2930 intel_hpd_init(dev_priv);
2931
2932 drm_modeset_unlock_all(dev);
2933 }
2934
2935 static int
2936 intel_finish_fb(struct drm_framebuffer *old_fb)
2937 {
2938 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2939 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2940 bool was_interruptible = dev_priv->mm.interruptible;
2941 int ret;
2942
2943 /* Big Hammer, we also need to ensure that any pending
2944 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2945 * current scanout is retired before unpinning the old
2946 * framebuffer.
2947 *
2948 * This should only fail upon a hung GPU, in which case we
2949 * can safely continue.
2950 */
2951 dev_priv->mm.interruptible = false;
2952 ret = i915_gem_object_finish_gpu(obj);
2953 dev_priv->mm.interruptible = was_interruptible;
2954
2955 return ret;
2956 }
2957
2958 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2959 {
2960 struct drm_device *dev = crtc->dev;
2961 struct drm_i915_private *dev_priv = dev->dev_private;
2962 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2963 bool pending;
2964
2965 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2966 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2967 return false;
2968
2969 spin_lock_irq(&dev->event_lock);
2970 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2971 spin_unlock_irq(&dev->event_lock);
2972
2973 return pending;
2974 }
2975
2976 static void intel_update_pipe_size(struct intel_crtc *crtc)
2977 {
2978 struct drm_device *dev = crtc->base.dev;
2979 struct drm_i915_private *dev_priv = dev->dev_private;
2980 const struct drm_display_mode *adjusted_mode;
2981
2982 if (!i915.fastboot)
2983 return;
2984
2985 /*
2986 * Update pipe size and adjust fitter if needed: the reason for this is
2987 * that in compute_mode_changes we check the native mode (not the pfit
2988 * mode) to see if we can flip rather than do a full mode set. In the
2989 * fastboot case, we'll flip, but if we don't update the pipesrc and
2990 * pfit state, we'll end up with a big fb scanned out into the wrong
2991 * sized surface.
2992 *
2993 * To fix this properly, we need to hoist the checks up into
2994 * compute_mode_changes (or above), check the actual pfit state and
2995 * whether the platform allows pfit disable with pipe active, and only
2996 * then update the pipesrc and pfit state, even on the flip path.
2997 */
2998
2999 adjusted_mode = &crtc->config->base.adjusted_mode;
3000
3001 I915_WRITE(PIPESRC(crtc->pipe),
3002 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3003 (adjusted_mode->crtc_vdisplay - 1));
3004 if (!crtc->config->pch_pfit.enabled &&
3005 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3006 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3007 I915_WRITE(PF_CTL(crtc->pipe), 0);
3008 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3009 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3010 }
3011 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3012 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3013 }
3014
3015 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3016 {
3017 struct drm_device *dev = crtc->dev;
3018 struct drm_i915_private *dev_priv = dev->dev_private;
3019 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3020 int pipe = intel_crtc->pipe;
3021 u32 reg, temp;
3022
3023 /* enable normal train */
3024 reg = FDI_TX_CTL(pipe);
3025 temp = I915_READ(reg);
3026 if (IS_IVYBRIDGE(dev)) {
3027 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3028 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3029 } else {
3030 temp &= ~FDI_LINK_TRAIN_NONE;
3031 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3032 }
3033 I915_WRITE(reg, temp);
3034
3035 reg = FDI_RX_CTL(pipe);
3036 temp = I915_READ(reg);
3037 if (HAS_PCH_CPT(dev)) {
3038 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3039 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3040 } else {
3041 temp &= ~FDI_LINK_TRAIN_NONE;
3042 temp |= FDI_LINK_TRAIN_NONE;
3043 }
3044 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3045
3046 /* wait one idle pattern time */
3047 POSTING_READ(reg);
3048 udelay(1000);
3049
3050 /* IVB wants error correction enabled */
3051 if (IS_IVYBRIDGE(dev))
3052 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3053 FDI_FE_ERRC_ENABLE);
3054 }
3055
3056 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
3057 {
3058 return crtc->base.enabled && crtc->active &&
3059 crtc->config->has_pch_encoder;
3060 }
3061
3062 static void ivb_modeset_global_resources(struct drm_device *dev)
3063 {
3064 struct drm_i915_private *dev_priv = dev->dev_private;
3065 struct intel_crtc *pipe_B_crtc =
3066 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3067 struct intel_crtc *pipe_C_crtc =
3068 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
3069 uint32_t temp;
3070
3071 /*
3072 * When everything is off disable fdi C so that we could enable fdi B
3073 * with all lanes. Note that we don't care about enabled pipes without
3074 * an enabled pch encoder.
3075 */
3076 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
3077 !pipe_has_enabled_pch(pipe_C_crtc)) {
3078 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3079 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3080
3081 temp = I915_READ(SOUTH_CHICKEN1);
3082 temp &= ~FDI_BC_BIFURCATION_SELECT;
3083 DRM_DEBUG_KMS("disabling fdi C rx\n");
3084 I915_WRITE(SOUTH_CHICKEN1, temp);
3085 }
3086 }
3087
3088 /* The FDI link training functions for ILK/Ibexpeak. */
3089 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3090 {
3091 struct drm_device *dev = crtc->dev;
3092 struct drm_i915_private *dev_priv = dev->dev_private;
3093 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3094 int pipe = intel_crtc->pipe;
3095 u32 reg, temp, tries;
3096
3097 /* FDI needs bits from pipe first */
3098 assert_pipe_enabled(dev_priv, pipe);
3099
3100 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3101 for train result */
3102 reg = FDI_RX_IMR(pipe);
3103 temp = I915_READ(reg);
3104 temp &= ~FDI_RX_SYMBOL_LOCK;
3105 temp &= ~FDI_RX_BIT_LOCK;
3106 I915_WRITE(reg, temp);
3107 I915_READ(reg);
3108 udelay(150);
3109
3110 /* enable CPU FDI TX and PCH FDI RX */
3111 reg = FDI_TX_CTL(pipe);
3112 temp = I915_READ(reg);
3113 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3114 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3115 temp &= ~FDI_LINK_TRAIN_NONE;
3116 temp |= FDI_LINK_TRAIN_PATTERN_1;
3117 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3118
3119 reg = FDI_RX_CTL(pipe);
3120 temp = I915_READ(reg);
3121 temp &= ~FDI_LINK_TRAIN_NONE;
3122 temp |= FDI_LINK_TRAIN_PATTERN_1;
3123 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3124
3125 POSTING_READ(reg);
3126 udelay(150);
3127
3128 /* Ironlake workaround, enable clock pointer after FDI enable*/
3129 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3130 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3131 FDI_RX_PHASE_SYNC_POINTER_EN);
3132
3133 reg = FDI_RX_IIR(pipe);
3134 for (tries = 0; tries < 5; tries++) {
3135 temp = I915_READ(reg);
3136 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3137
3138 if ((temp & FDI_RX_BIT_LOCK)) {
3139 DRM_DEBUG_KMS("FDI train 1 done.\n");
3140 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3141 break;
3142 }
3143 }
3144 if (tries == 5)
3145 DRM_ERROR("FDI train 1 fail!\n");
3146
3147 /* Train 2 */
3148 reg = FDI_TX_CTL(pipe);
3149 temp = I915_READ(reg);
3150 temp &= ~FDI_LINK_TRAIN_NONE;
3151 temp |= FDI_LINK_TRAIN_PATTERN_2;
3152 I915_WRITE(reg, temp);
3153
3154 reg = FDI_RX_CTL(pipe);
3155 temp = I915_READ(reg);
3156 temp &= ~FDI_LINK_TRAIN_NONE;
3157 temp |= FDI_LINK_TRAIN_PATTERN_2;
3158 I915_WRITE(reg, temp);
3159
3160 POSTING_READ(reg);
3161 udelay(150);
3162
3163 reg = FDI_RX_IIR(pipe);
3164 for (tries = 0; tries < 5; tries++) {
3165 temp = I915_READ(reg);
3166 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3167
3168 if (temp & FDI_RX_SYMBOL_LOCK) {
3169 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3170 DRM_DEBUG_KMS("FDI train 2 done.\n");
3171 break;
3172 }
3173 }
3174 if (tries == 5)
3175 DRM_ERROR("FDI train 2 fail!\n");
3176
3177 DRM_DEBUG_KMS("FDI train done\n");
3178
3179 }
3180
3181 static const int snb_b_fdi_train_param[] = {
3182 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3183 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3184 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3185 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3186 };
3187
3188 /* The FDI link training functions for SNB/Cougarpoint. */
3189 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3190 {
3191 struct drm_device *dev = crtc->dev;
3192 struct drm_i915_private *dev_priv = dev->dev_private;
3193 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3194 int pipe = intel_crtc->pipe;
3195 u32 reg, temp, i, retry;
3196
3197 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3198 for train result */
3199 reg = FDI_RX_IMR(pipe);
3200 temp = I915_READ(reg);
3201 temp &= ~FDI_RX_SYMBOL_LOCK;
3202 temp &= ~FDI_RX_BIT_LOCK;
3203 I915_WRITE(reg, temp);
3204
3205 POSTING_READ(reg);
3206 udelay(150);
3207
3208 /* enable CPU FDI TX and PCH FDI RX */
3209 reg = FDI_TX_CTL(pipe);
3210 temp = I915_READ(reg);
3211 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3212 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3213 temp &= ~FDI_LINK_TRAIN_NONE;
3214 temp |= FDI_LINK_TRAIN_PATTERN_1;
3215 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3216 /* SNB-B */
3217 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3218 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3219
3220 I915_WRITE(FDI_RX_MISC(pipe),
3221 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3222
3223 reg = FDI_RX_CTL(pipe);
3224 temp = I915_READ(reg);
3225 if (HAS_PCH_CPT(dev)) {
3226 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3227 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3228 } else {
3229 temp &= ~FDI_LINK_TRAIN_NONE;
3230 temp |= FDI_LINK_TRAIN_PATTERN_1;
3231 }
3232 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3233
3234 POSTING_READ(reg);
3235 udelay(150);
3236
3237 for (i = 0; i < 4; i++) {
3238 reg = FDI_TX_CTL(pipe);
3239 temp = I915_READ(reg);
3240 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3241 temp |= snb_b_fdi_train_param[i];
3242 I915_WRITE(reg, temp);
3243
3244 POSTING_READ(reg);
3245 udelay(500);
3246
3247 for (retry = 0; retry < 5; retry++) {
3248 reg = FDI_RX_IIR(pipe);
3249 temp = I915_READ(reg);
3250 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3251 if (temp & FDI_RX_BIT_LOCK) {
3252 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3253 DRM_DEBUG_KMS("FDI train 1 done.\n");
3254 break;
3255 }
3256 udelay(50);
3257 }
3258 if (retry < 5)
3259 break;
3260 }
3261 if (i == 4)
3262 DRM_ERROR("FDI train 1 fail!\n");
3263
3264 /* Train 2 */
3265 reg = FDI_TX_CTL(pipe);
3266 temp = I915_READ(reg);
3267 temp &= ~FDI_LINK_TRAIN_NONE;
3268 temp |= FDI_LINK_TRAIN_PATTERN_2;
3269 if (IS_GEN6(dev)) {
3270 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3271 /* SNB-B */
3272 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3273 }
3274 I915_WRITE(reg, temp);
3275
3276 reg = FDI_RX_CTL(pipe);
3277 temp = I915_READ(reg);
3278 if (HAS_PCH_CPT(dev)) {
3279 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3280 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3281 } else {
3282 temp &= ~FDI_LINK_TRAIN_NONE;
3283 temp |= FDI_LINK_TRAIN_PATTERN_2;
3284 }
3285 I915_WRITE(reg, temp);
3286
3287 POSTING_READ(reg);
3288 udelay(150);
3289
3290 for (i = 0; i < 4; i++) {
3291 reg = FDI_TX_CTL(pipe);
3292 temp = I915_READ(reg);
3293 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3294 temp |= snb_b_fdi_train_param[i];
3295 I915_WRITE(reg, temp);
3296
3297 POSTING_READ(reg);
3298 udelay(500);
3299
3300 for (retry = 0; retry < 5; retry++) {
3301 reg = FDI_RX_IIR(pipe);
3302 temp = I915_READ(reg);
3303 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3304 if (temp & FDI_RX_SYMBOL_LOCK) {
3305 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3306 DRM_DEBUG_KMS("FDI train 2 done.\n");
3307 break;
3308 }
3309 udelay(50);
3310 }
3311 if (retry < 5)
3312 break;
3313 }
3314 if (i == 4)
3315 DRM_ERROR("FDI train 2 fail!\n");
3316
3317 DRM_DEBUG_KMS("FDI train done.\n");
3318 }
3319
3320 /* Manual link training for Ivy Bridge A0 parts */
3321 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3322 {
3323 struct drm_device *dev = crtc->dev;
3324 struct drm_i915_private *dev_priv = dev->dev_private;
3325 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3326 int pipe = intel_crtc->pipe;
3327 u32 reg, temp, i, j;
3328
3329 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3330 for train result */
3331 reg = FDI_RX_IMR(pipe);
3332 temp = I915_READ(reg);
3333 temp &= ~FDI_RX_SYMBOL_LOCK;
3334 temp &= ~FDI_RX_BIT_LOCK;
3335 I915_WRITE(reg, temp);
3336
3337 POSTING_READ(reg);
3338 udelay(150);
3339
3340 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3341 I915_READ(FDI_RX_IIR(pipe)));
3342
3343 /* Try each vswing and preemphasis setting twice before moving on */
3344 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3345 /* disable first in case we need to retry */
3346 reg = FDI_TX_CTL(pipe);
3347 temp = I915_READ(reg);
3348 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3349 temp &= ~FDI_TX_ENABLE;
3350 I915_WRITE(reg, temp);
3351
3352 reg = FDI_RX_CTL(pipe);
3353 temp = I915_READ(reg);
3354 temp &= ~FDI_LINK_TRAIN_AUTO;
3355 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3356 temp &= ~FDI_RX_ENABLE;
3357 I915_WRITE(reg, temp);
3358
3359 /* enable CPU FDI TX and PCH FDI RX */
3360 reg = FDI_TX_CTL(pipe);
3361 temp = I915_READ(reg);
3362 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3363 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3364 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3365 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3366 temp |= snb_b_fdi_train_param[j/2];
3367 temp |= FDI_COMPOSITE_SYNC;
3368 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3369
3370 I915_WRITE(FDI_RX_MISC(pipe),
3371 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3372
3373 reg = FDI_RX_CTL(pipe);
3374 temp = I915_READ(reg);
3375 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3376 temp |= FDI_COMPOSITE_SYNC;
3377 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3378
3379 POSTING_READ(reg);
3380 udelay(1); /* should be 0.5us */
3381
3382 for (i = 0; i < 4; i++) {
3383 reg = FDI_RX_IIR(pipe);
3384 temp = I915_READ(reg);
3385 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3386
3387 if (temp & FDI_RX_BIT_LOCK ||
3388 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3389 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3390 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3391 i);
3392 break;
3393 }
3394 udelay(1); /* should be 0.5us */
3395 }
3396 if (i == 4) {
3397 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3398 continue;
3399 }
3400
3401 /* Train 2 */
3402 reg = FDI_TX_CTL(pipe);
3403 temp = I915_READ(reg);
3404 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3405 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3406 I915_WRITE(reg, temp);
3407
3408 reg = FDI_RX_CTL(pipe);
3409 temp = I915_READ(reg);
3410 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3411 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3412 I915_WRITE(reg, temp);
3413
3414 POSTING_READ(reg);
3415 udelay(2); /* should be 1.5us */
3416
3417 for (i = 0; i < 4; i++) {
3418 reg = FDI_RX_IIR(pipe);
3419 temp = I915_READ(reg);
3420 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3421
3422 if (temp & FDI_RX_SYMBOL_LOCK ||
3423 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3424 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3425 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3426 i);
3427 goto train_done;
3428 }
3429 udelay(2); /* should be 1.5us */
3430 }
3431 if (i == 4)
3432 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3433 }
3434
3435 train_done:
3436 DRM_DEBUG_KMS("FDI train done.\n");
3437 }
3438
3439 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3440 {
3441 struct drm_device *dev = intel_crtc->base.dev;
3442 struct drm_i915_private *dev_priv = dev->dev_private;
3443 int pipe = intel_crtc->pipe;
3444 u32 reg, temp;
3445
3446
3447 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3448 reg = FDI_RX_CTL(pipe);
3449 temp = I915_READ(reg);
3450 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3451 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3452 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3453 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3454
3455 POSTING_READ(reg);
3456 udelay(200);
3457
3458 /* Switch from Rawclk to PCDclk */
3459 temp = I915_READ(reg);
3460 I915_WRITE(reg, temp | FDI_PCDCLK);
3461
3462 POSTING_READ(reg);
3463 udelay(200);
3464
3465 /* Enable CPU FDI TX PLL, always on for Ironlake */
3466 reg = FDI_TX_CTL(pipe);
3467 temp = I915_READ(reg);
3468 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3469 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3470
3471 POSTING_READ(reg);
3472 udelay(100);
3473 }
3474 }
3475
3476 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3477 {
3478 struct drm_device *dev = intel_crtc->base.dev;
3479 struct drm_i915_private *dev_priv = dev->dev_private;
3480 int pipe = intel_crtc->pipe;
3481 u32 reg, temp;
3482
3483 /* Switch from PCDclk to Rawclk */
3484 reg = FDI_RX_CTL(pipe);
3485 temp = I915_READ(reg);
3486 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3487
3488 /* Disable CPU FDI TX PLL */
3489 reg = FDI_TX_CTL(pipe);
3490 temp = I915_READ(reg);
3491 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3492
3493 POSTING_READ(reg);
3494 udelay(100);
3495
3496 reg = FDI_RX_CTL(pipe);
3497 temp = I915_READ(reg);
3498 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3499
3500 /* Wait for the clocks to turn off. */
3501 POSTING_READ(reg);
3502 udelay(100);
3503 }
3504
3505 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3506 {
3507 struct drm_device *dev = crtc->dev;
3508 struct drm_i915_private *dev_priv = dev->dev_private;
3509 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3510 int pipe = intel_crtc->pipe;
3511 u32 reg, temp;
3512
3513 /* disable CPU FDI tx and PCH FDI rx */
3514 reg = FDI_TX_CTL(pipe);
3515 temp = I915_READ(reg);
3516 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3517 POSTING_READ(reg);
3518
3519 reg = FDI_RX_CTL(pipe);
3520 temp = I915_READ(reg);
3521 temp &= ~(0x7 << 16);
3522 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3523 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3524
3525 POSTING_READ(reg);
3526 udelay(100);
3527
3528 /* Ironlake workaround, disable clock pointer after downing FDI */
3529 if (HAS_PCH_IBX(dev))
3530 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3531
3532 /* still set train pattern 1 */
3533 reg = FDI_TX_CTL(pipe);
3534 temp = I915_READ(reg);
3535 temp &= ~FDI_LINK_TRAIN_NONE;
3536 temp |= FDI_LINK_TRAIN_PATTERN_1;
3537 I915_WRITE(reg, temp);
3538
3539 reg = FDI_RX_CTL(pipe);
3540 temp = I915_READ(reg);
3541 if (HAS_PCH_CPT(dev)) {
3542 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3543 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3544 } else {
3545 temp &= ~FDI_LINK_TRAIN_NONE;
3546 temp |= FDI_LINK_TRAIN_PATTERN_1;
3547 }
3548 /* BPC in FDI rx is consistent with that in PIPECONF */
3549 temp &= ~(0x07 << 16);
3550 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3551 I915_WRITE(reg, temp);
3552
3553 POSTING_READ(reg);
3554 udelay(100);
3555 }
3556
3557 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3558 {
3559 struct intel_crtc *crtc;
3560
3561 /* Note that we don't need to be called with mode_config.lock here
3562 * as our list of CRTC objects is static for the lifetime of the
3563 * device and so cannot disappear as we iterate. Similarly, we can
3564 * happily treat the predicates as racy, atomic checks as userspace
3565 * cannot claim and pin a new fb without at least acquring the
3566 * struct_mutex and so serialising with us.
3567 */
3568 for_each_intel_crtc(dev, crtc) {
3569 if (atomic_read(&crtc->unpin_work_count) == 0)
3570 continue;
3571
3572 if (crtc->unpin_work)
3573 intel_wait_for_vblank(dev, crtc->pipe);
3574
3575 return true;
3576 }
3577
3578 return false;
3579 }
3580
3581 static void page_flip_completed(struct intel_crtc *intel_crtc)
3582 {
3583 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3584 struct intel_unpin_work *work = intel_crtc->unpin_work;
3585
3586 /* ensure that the unpin work is consistent wrt ->pending. */
3587 smp_rmb();
3588 intel_crtc->unpin_work = NULL;
3589
3590 if (work->event)
3591 drm_send_vblank_event(intel_crtc->base.dev,
3592 intel_crtc->pipe,
3593 work->event);
3594
3595 drm_crtc_vblank_put(&intel_crtc->base);
3596
3597 wake_up_all(&dev_priv->pending_flip_queue);
3598 queue_work(dev_priv->wq, &work->work);
3599
3600 trace_i915_flip_complete(intel_crtc->plane,
3601 work->pending_flip_obj);
3602 }
3603
3604 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3605 {
3606 struct drm_device *dev = crtc->dev;
3607 struct drm_i915_private *dev_priv = dev->dev_private;
3608
3609 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3610 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3611 !intel_crtc_has_pending_flip(crtc),
3612 60*HZ) == 0)) {
3613 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3614
3615 spin_lock_irq(&dev->event_lock);
3616 if (intel_crtc->unpin_work) {
3617 WARN_ONCE(1, "Removing stuck page flip\n");
3618 page_flip_completed(intel_crtc);
3619 }
3620 spin_unlock_irq(&dev->event_lock);
3621 }
3622
3623 if (crtc->primary->fb) {
3624 mutex_lock(&dev->struct_mutex);
3625 intel_finish_fb(crtc->primary->fb);
3626 mutex_unlock(&dev->struct_mutex);
3627 }
3628 }
3629
3630 /* Program iCLKIP clock to the desired frequency */
3631 static void lpt_program_iclkip(struct drm_crtc *crtc)
3632 {
3633 struct drm_device *dev = crtc->dev;
3634 struct drm_i915_private *dev_priv = dev->dev_private;
3635 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3636 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3637 u32 temp;
3638
3639 mutex_lock(&dev_priv->dpio_lock);
3640
3641 /* It is necessary to ungate the pixclk gate prior to programming
3642 * the divisors, and gate it back when it is done.
3643 */
3644 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3645
3646 /* Disable SSCCTL */
3647 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3648 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3649 SBI_SSCCTL_DISABLE,
3650 SBI_ICLK);
3651
3652 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3653 if (clock == 20000) {
3654 auxdiv = 1;
3655 divsel = 0x41;
3656 phaseinc = 0x20;
3657 } else {
3658 /* The iCLK virtual clock root frequency is in MHz,
3659 * but the adjusted_mode->crtc_clock in in KHz. To get the
3660 * divisors, it is necessary to divide one by another, so we
3661 * convert the virtual clock precision to KHz here for higher
3662 * precision.
3663 */
3664 u32 iclk_virtual_root_freq = 172800 * 1000;
3665 u32 iclk_pi_range = 64;
3666 u32 desired_divisor, msb_divisor_value, pi_value;
3667
3668 desired_divisor = (iclk_virtual_root_freq / clock);
3669 msb_divisor_value = desired_divisor / iclk_pi_range;
3670 pi_value = desired_divisor % iclk_pi_range;
3671
3672 auxdiv = 0;
3673 divsel = msb_divisor_value - 2;
3674 phaseinc = pi_value;
3675 }
3676
3677 /* This should not happen with any sane values */
3678 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3679 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3680 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3681 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3682
3683 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3684 clock,
3685 auxdiv,
3686 divsel,
3687 phasedir,
3688 phaseinc);
3689
3690 /* Program SSCDIVINTPHASE6 */
3691 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3692 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3693 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3694 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3695 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3696 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3697 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3698 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3699
3700 /* Program SSCAUXDIV */
3701 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3702 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3703 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3704 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3705
3706 /* Enable modulator and associated divider */
3707 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3708 temp &= ~SBI_SSCCTL_DISABLE;
3709 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3710
3711 /* Wait for initialization time */
3712 udelay(24);
3713
3714 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3715
3716 mutex_unlock(&dev_priv->dpio_lock);
3717 }
3718
3719 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3720 enum pipe pch_transcoder)
3721 {
3722 struct drm_device *dev = crtc->base.dev;
3723 struct drm_i915_private *dev_priv = dev->dev_private;
3724 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3725
3726 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3727 I915_READ(HTOTAL(cpu_transcoder)));
3728 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3729 I915_READ(HBLANK(cpu_transcoder)));
3730 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3731 I915_READ(HSYNC(cpu_transcoder)));
3732
3733 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3734 I915_READ(VTOTAL(cpu_transcoder)));
3735 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3736 I915_READ(VBLANK(cpu_transcoder)));
3737 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3738 I915_READ(VSYNC(cpu_transcoder)));
3739 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3740 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3741 }
3742
3743 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3744 {
3745 struct drm_i915_private *dev_priv = dev->dev_private;
3746 uint32_t temp;
3747
3748 temp = I915_READ(SOUTH_CHICKEN1);
3749 if (temp & FDI_BC_BIFURCATION_SELECT)
3750 return;
3751
3752 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3753 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3754
3755 temp |= FDI_BC_BIFURCATION_SELECT;
3756 DRM_DEBUG_KMS("enabling fdi C rx\n");
3757 I915_WRITE(SOUTH_CHICKEN1, temp);
3758 POSTING_READ(SOUTH_CHICKEN1);
3759 }
3760
3761 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3762 {
3763 struct drm_device *dev = intel_crtc->base.dev;
3764 struct drm_i915_private *dev_priv = dev->dev_private;
3765
3766 switch (intel_crtc->pipe) {
3767 case PIPE_A:
3768 break;
3769 case PIPE_B:
3770 if (intel_crtc->config->fdi_lanes > 2)
3771 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3772 else
3773 cpt_enable_fdi_bc_bifurcation(dev);
3774
3775 break;
3776 case PIPE_C:
3777 cpt_enable_fdi_bc_bifurcation(dev);
3778
3779 break;
3780 default:
3781 BUG();
3782 }
3783 }
3784
3785 /*
3786 * Enable PCH resources required for PCH ports:
3787 * - PCH PLLs
3788 * - FDI training & RX/TX
3789 * - update transcoder timings
3790 * - DP transcoding bits
3791 * - transcoder
3792 */
3793 static void ironlake_pch_enable(struct drm_crtc *crtc)
3794 {
3795 struct drm_device *dev = crtc->dev;
3796 struct drm_i915_private *dev_priv = dev->dev_private;
3797 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3798 int pipe = intel_crtc->pipe;
3799 u32 reg, temp;
3800
3801 assert_pch_transcoder_disabled(dev_priv, pipe);
3802
3803 if (IS_IVYBRIDGE(dev))
3804 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3805
3806 /* Write the TU size bits before fdi link training, so that error
3807 * detection works. */
3808 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3809 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3810
3811 /* For PCH output, training FDI link */
3812 dev_priv->display.fdi_link_train(crtc);
3813
3814 /* We need to program the right clock selection before writing the pixel
3815 * mutliplier into the DPLL. */
3816 if (HAS_PCH_CPT(dev)) {
3817 u32 sel;
3818
3819 temp = I915_READ(PCH_DPLL_SEL);
3820 temp |= TRANS_DPLL_ENABLE(pipe);
3821 sel = TRANS_DPLLB_SEL(pipe);
3822 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
3823 temp |= sel;
3824 else
3825 temp &= ~sel;
3826 I915_WRITE(PCH_DPLL_SEL, temp);
3827 }
3828
3829 /* XXX: pch pll's can be enabled any time before we enable the PCH
3830 * transcoder, and we actually should do this to not upset any PCH
3831 * transcoder that already use the clock when we share it.
3832 *
3833 * Note that enable_shared_dpll tries to do the right thing, but
3834 * get_shared_dpll unconditionally resets the pll - we need that to have
3835 * the right LVDS enable sequence. */
3836 intel_enable_shared_dpll(intel_crtc);
3837
3838 /* set transcoder timing, panel must allow it */
3839 assert_panel_unlocked(dev_priv, pipe);
3840 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3841
3842 intel_fdi_normal_train(crtc);
3843
3844 /* For PCH DP, enable TRANS_DP_CTL */
3845 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
3846 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3847 reg = TRANS_DP_CTL(pipe);
3848 temp = I915_READ(reg);
3849 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3850 TRANS_DP_SYNC_MASK |
3851 TRANS_DP_BPC_MASK);
3852 temp |= (TRANS_DP_OUTPUT_ENABLE |
3853 TRANS_DP_ENH_FRAMING);
3854 temp |= bpc << 9; /* same format but at 11:9 */
3855
3856 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3857 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3858 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3859 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3860
3861 switch (intel_trans_dp_port_sel(crtc)) {
3862 case PCH_DP_B:
3863 temp |= TRANS_DP_PORT_SEL_B;
3864 break;
3865 case PCH_DP_C:
3866 temp |= TRANS_DP_PORT_SEL_C;
3867 break;
3868 case PCH_DP_D:
3869 temp |= TRANS_DP_PORT_SEL_D;
3870 break;
3871 default:
3872 BUG();
3873 }
3874
3875 I915_WRITE(reg, temp);
3876 }
3877
3878 ironlake_enable_pch_transcoder(dev_priv, pipe);
3879 }
3880
3881 static void lpt_pch_enable(struct drm_crtc *crtc)
3882 {
3883 struct drm_device *dev = crtc->dev;
3884 struct drm_i915_private *dev_priv = dev->dev_private;
3885 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3886 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
3887
3888 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3889
3890 lpt_program_iclkip(crtc);
3891
3892 /* Set transcoder timing. */
3893 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3894
3895 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3896 }
3897
3898 void intel_put_shared_dpll(struct intel_crtc *crtc)
3899 {
3900 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3901
3902 if (pll == NULL)
3903 return;
3904
3905 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
3906 WARN(1, "bad %s crtc mask\n", pll->name);
3907 return;
3908 }
3909
3910 pll->config.crtc_mask &= ~(1 << crtc->pipe);
3911 if (pll->config.crtc_mask == 0) {
3912 WARN_ON(pll->on);
3913 WARN_ON(pll->active);
3914 }
3915
3916 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
3917 }
3918
3919 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
3920 struct intel_crtc_state *crtc_state)
3921 {
3922 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3923 struct intel_shared_dpll *pll;
3924 enum intel_dpll_id i;
3925
3926 if (HAS_PCH_IBX(dev_priv->dev)) {
3927 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3928 i = (enum intel_dpll_id) crtc->pipe;
3929 pll = &dev_priv->shared_dplls[i];
3930
3931 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3932 crtc->base.base.id, pll->name);
3933
3934 WARN_ON(pll->new_config->crtc_mask);
3935
3936 goto found;
3937 }
3938
3939 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3940 pll = &dev_priv->shared_dplls[i];
3941
3942 /* Only want to check enabled timings first */
3943 if (pll->new_config->crtc_mask == 0)
3944 continue;
3945
3946 if (memcmp(&crtc_state->dpll_hw_state,
3947 &pll->new_config->hw_state,
3948 sizeof(pll->new_config->hw_state)) == 0) {
3949 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
3950 crtc->base.base.id, pll->name,
3951 pll->new_config->crtc_mask,
3952 pll->active);
3953 goto found;
3954 }
3955 }
3956
3957 /* Ok no matching timings, maybe there's a free one? */
3958 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3959 pll = &dev_priv->shared_dplls[i];
3960 if (pll->new_config->crtc_mask == 0) {
3961 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3962 crtc->base.base.id, pll->name);
3963 goto found;
3964 }
3965 }
3966
3967 return NULL;
3968
3969 found:
3970 if (pll->new_config->crtc_mask == 0)
3971 pll->new_config->hw_state = crtc_state->dpll_hw_state;
3972
3973 crtc_state->shared_dpll = i;
3974 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3975 pipe_name(crtc->pipe));
3976
3977 pll->new_config->crtc_mask |= 1 << crtc->pipe;
3978
3979 return pll;
3980 }
3981
3982 /**
3983 * intel_shared_dpll_start_config - start a new PLL staged config
3984 * @dev_priv: DRM device
3985 * @clear_pipes: mask of pipes that will have their PLLs freed
3986 *
3987 * Starts a new PLL staged config, copying the current config but
3988 * releasing the references of pipes specified in clear_pipes.
3989 */
3990 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
3991 unsigned clear_pipes)
3992 {
3993 struct intel_shared_dpll *pll;
3994 enum intel_dpll_id i;
3995
3996 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3997 pll = &dev_priv->shared_dplls[i];
3998
3999 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4000 GFP_KERNEL);
4001 if (!pll->new_config)
4002 goto cleanup;
4003
4004 pll->new_config->crtc_mask &= ~clear_pipes;
4005 }
4006
4007 return 0;
4008
4009 cleanup:
4010 while (--i >= 0) {
4011 pll = &dev_priv->shared_dplls[i];
4012 kfree(pll->new_config);
4013 pll->new_config = NULL;
4014 }
4015
4016 return -ENOMEM;
4017 }
4018
4019 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4020 {
4021 struct intel_shared_dpll *pll;
4022 enum intel_dpll_id i;
4023
4024 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4025 pll = &dev_priv->shared_dplls[i];
4026
4027 WARN_ON(pll->new_config == &pll->config);
4028
4029 pll->config = *pll->new_config;
4030 kfree(pll->new_config);
4031 pll->new_config = NULL;
4032 }
4033 }
4034
4035 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4036 {
4037 struct intel_shared_dpll *pll;
4038 enum intel_dpll_id i;
4039
4040 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4041 pll = &dev_priv->shared_dplls[i];
4042
4043 WARN_ON(pll->new_config == &pll->config);
4044
4045 kfree(pll->new_config);
4046 pll->new_config = NULL;
4047 }
4048 }
4049
4050 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4051 {
4052 struct drm_i915_private *dev_priv = dev->dev_private;
4053 int dslreg = PIPEDSL(pipe);
4054 u32 temp;
4055
4056 temp = I915_READ(dslreg);
4057 udelay(500);
4058 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4059 if (wait_for(I915_READ(dslreg) != temp, 5))
4060 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4061 }
4062 }
4063
4064 static void skylake_pfit_enable(struct intel_crtc *crtc)
4065 {
4066 struct drm_device *dev = crtc->base.dev;
4067 struct drm_i915_private *dev_priv = dev->dev_private;
4068 int pipe = crtc->pipe;
4069
4070 if (crtc->config->pch_pfit.enabled) {
4071 I915_WRITE(PS_CTL(pipe), PS_ENABLE);
4072 I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4073 I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4074 }
4075 }
4076
4077 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4078 {
4079 struct drm_device *dev = crtc->base.dev;
4080 struct drm_i915_private *dev_priv = dev->dev_private;
4081 int pipe = crtc->pipe;
4082
4083 if (crtc->config->pch_pfit.enabled) {
4084 /* Force use of hard-coded filter coefficients
4085 * as some pre-programmed values are broken,
4086 * e.g. x201.
4087 */
4088 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4089 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4090 PF_PIPE_SEL_IVB(pipe));
4091 else
4092 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4093 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4094 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4095 }
4096 }
4097
4098 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4099 {
4100 struct drm_device *dev = crtc->dev;
4101 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4102 struct drm_plane *plane;
4103 struct intel_plane *intel_plane;
4104
4105 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4106 intel_plane = to_intel_plane(plane);
4107 if (intel_plane->pipe == pipe)
4108 intel_plane_restore(&intel_plane->base);
4109 }
4110 }
4111
4112 static void intel_disable_sprite_planes(struct drm_crtc *crtc)
4113 {
4114 struct drm_device *dev = crtc->dev;
4115 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4116 struct drm_plane *plane;
4117 struct intel_plane *intel_plane;
4118
4119 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4120 intel_plane = to_intel_plane(plane);
4121 if (intel_plane->pipe == pipe)
4122 plane->funcs->disable_plane(plane);
4123 }
4124 }
4125
4126 void hsw_enable_ips(struct intel_crtc *crtc)
4127 {
4128 struct drm_device *dev = crtc->base.dev;
4129 struct drm_i915_private *dev_priv = dev->dev_private;
4130
4131 if (!crtc->config->ips_enabled)
4132 return;
4133
4134 /* We can only enable IPS after we enable a plane and wait for a vblank */
4135 intel_wait_for_vblank(dev, crtc->pipe);
4136
4137 assert_plane_enabled(dev_priv, crtc->plane);
4138 if (IS_BROADWELL(dev)) {
4139 mutex_lock(&dev_priv->rps.hw_lock);
4140 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4141 mutex_unlock(&dev_priv->rps.hw_lock);
4142 /* Quoting Art Runyan: "its not safe to expect any particular
4143 * value in IPS_CTL bit 31 after enabling IPS through the
4144 * mailbox." Moreover, the mailbox may return a bogus state,
4145 * so we need to just enable it and continue on.
4146 */
4147 } else {
4148 I915_WRITE(IPS_CTL, IPS_ENABLE);
4149 /* The bit only becomes 1 in the next vblank, so this wait here
4150 * is essentially intel_wait_for_vblank. If we don't have this
4151 * and don't wait for vblanks until the end of crtc_enable, then
4152 * the HW state readout code will complain that the expected
4153 * IPS_CTL value is not the one we read. */
4154 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4155 DRM_ERROR("Timed out waiting for IPS enable\n");
4156 }
4157 }
4158
4159 void hsw_disable_ips(struct intel_crtc *crtc)
4160 {
4161 struct drm_device *dev = crtc->base.dev;
4162 struct drm_i915_private *dev_priv = dev->dev_private;
4163
4164 if (!crtc->config->ips_enabled)
4165 return;
4166
4167 assert_plane_enabled(dev_priv, crtc->plane);
4168 if (IS_BROADWELL(dev)) {
4169 mutex_lock(&dev_priv->rps.hw_lock);
4170 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4171 mutex_unlock(&dev_priv->rps.hw_lock);
4172 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4173 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4174 DRM_ERROR("Timed out waiting for IPS disable\n");
4175 } else {
4176 I915_WRITE(IPS_CTL, 0);
4177 POSTING_READ(IPS_CTL);
4178 }
4179
4180 /* We need to wait for a vblank before we can disable the plane. */
4181 intel_wait_for_vblank(dev, crtc->pipe);
4182 }
4183
4184 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4185 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4186 {
4187 struct drm_device *dev = crtc->dev;
4188 struct drm_i915_private *dev_priv = dev->dev_private;
4189 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4190 enum pipe pipe = intel_crtc->pipe;
4191 int palreg = PALETTE(pipe);
4192 int i;
4193 bool reenable_ips = false;
4194
4195 /* The clocks have to be on to load the palette. */
4196 if (!crtc->enabled || !intel_crtc->active)
4197 return;
4198
4199 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4200 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4201 assert_dsi_pll_enabled(dev_priv);
4202 else
4203 assert_pll_enabled(dev_priv, pipe);
4204 }
4205
4206 /* use legacy palette for Ironlake */
4207 if (!HAS_GMCH_DISPLAY(dev))
4208 palreg = LGC_PALETTE(pipe);
4209
4210 /* Workaround : Do not read or write the pipe palette/gamma data while
4211 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4212 */
4213 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4214 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4215 GAMMA_MODE_MODE_SPLIT)) {
4216 hsw_disable_ips(intel_crtc);
4217 reenable_ips = true;
4218 }
4219
4220 for (i = 0; i < 256; i++) {
4221 I915_WRITE(palreg + 4 * i,
4222 (intel_crtc->lut_r[i] << 16) |
4223 (intel_crtc->lut_g[i] << 8) |
4224 intel_crtc->lut_b[i]);
4225 }
4226
4227 if (reenable_ips)
4228 hsw_enable_ips(intel_crtc);
4229 }
4230
4231 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4232 {
4233 if (!enable && intel_crtc->overlay) {
4234 struct drm_device *dev = intel_crtc->base.dev;
4235 struct drm_i915_private *dev_priv = dev->dev_private;
4236
4237 mutex_lock(&dev->struct_mutex);
4238 dev_priv->mm.interruptible = false;
4239 (void) intel_overlay_switch_off(intel_crtc->overlay);
4240 dev_priv->mm.interruptible = true;
4241 mutex_unlock(&dev->struct_mutex);
4242 }
4243
4244 /* Let userspace switch the overlay on again. In most cases userspace
4245 * has to recompute where to put it anyway.
4246 */
4247 }
4248
4249 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4250 {
4251 struct drm_device *dev = crtc->dev;
4252 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4253 int pipe = intel_crtc->pipe;
4254
4255 intel_enable_primary_hw_plane(crtc->primary, crtc);
4256 intel_enable_sprite_planes(crtc);
4257 intel_crtc_update_cursor(crtc, true);
4258 intel_crtc_dpms_overlay(intel_crtc, true);
4259
4260 hsw_enable_ips(intel_crtc);
4261
4262 mutex_lock(&dev->struct_mutex);
4263 intel_fbc_update(dev);
4264 mutex_unlock(&dev->struct_mutex);
4265
4266 /*
4267 * FIXME: Once we grow proper nuclear flip support out of this we need
4268 * to compute the mask of flip planes precisely. For the time being
4269 * consider this a flip from a NULL plane.
4270 */
4271 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4272 }
4273
4274 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4275 {
4276 struct drm_device *dev = crtc->dev;
4277 struct drm_i915_private *dev_priv = dev->dev_private;
4278 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4279 int pipe = intel_crtc->pipe;
4280 int plane = intel_crtc->plane;
4281
4282 intel_crtc_wait_for_pending_flips(crtc);
4283
4284 if (dev_priv->fbc.plane == plane)
4285 intel_fbc_disable(dev);
4286
4287 hsw_disable_ips(intel_crtc);
4288
4289 intel_crtc_dpms_overlay(intel_crtc, false);
4290 intel_crtc_update_cursor(crtc, false);
4291 intel_disable_sprite_planes(crtc);
4292 intel_disable_primary_hw_plane(crtc->primary, crtc);
4293
4294 /*
4295 * FIXME: Once we grow proper nuclear flip support out of this we need
4296 * to compute the mask of flip planes precisely. For the time being
4297 * consider this a flip to a NULL plane.
4298 */
4299 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4300 }
4301
4302 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4303 {
4304 struct drm_device *dev = crtc->dev;
4305 struct drm_i915_private *dev_priv = dev->dev_private;
4306 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4307 struct intel_encoder *encoder;
4308 int pipe = intel_crtc->pipe;
4309
4310 WARN_ON(!crtc->enabled);
4311
4312 if (intel_crtc->active)
4313 return;
4314
4315 if (intel_crtc->config->has_pch_encoder)
4316 intel_prepare_shared_dpll(intel_crtc);
4317
4318 if (intel_crtc->config->has_dp_encoder)
4319 intel_dp_set_m_n(intel_crtc);
4320
4321 intel_set_pipe_timings(intel_crtc);
4322
4323 if (intel_crtc->config->has_pch_encoder) {
4324 intel_cpu_transcoder_set_m_n(intel_crtc,
4325 &intel_crtc->config->fdi_m_n, NULL);
4326 }
4327
4328 ironlake_set_pipeconf(crtc);
4329
4330 intel_crtc->active = true;
4331
4332 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4333 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4334
4335 for_each_encoder_on_crtc(dev, crtc, encoder)
4336 if (encoder->pre_enable)
4337 encoder->pre_enable(encoder);
4338
4339 if (intel_crtc->config->has_pch_encoder) {
4340 /* Note: FDI PLL enabling _must_ be done before we enable the
4341 * cpu pipes, hence this is separate from all the other fdi/pch
4342 * enabling. */
4343 ironlake_fdi_pll_enable(intel_crtc);
4344 } else {
4345 assert_fdi_tx_disabled(dev_priv, pipe);
4346 assert_fdi_rx_disabled(dev_priv, pipe);
4347 }
4348
4349 ironlake_pfit_enable(intel_crtc);
4350
4351 /*
4352 * On ILK+ LUT must be loaded before the pipe is running but with
4353 * clocks enabled
4354 */
4355 intel_crtc_load_lut(crtc);
4356
4357 intel_update_watermarks(crtc);
4358 intel_enable_pipe(intel_crtc);
4359
4360 if (intel_crtc->config->has_pch_encoder)
4361 ironlake_pch_enable(crtc);
4362
4363 assert_vblank_disabled(crtc);
4364 drm_crtc_vblank_on(crtc);
4365
4366 for_each_encoder_on_crtc(dev, crtc, encoder)
4367 encoder->enable(encoder);
4368
4369 if (HAS_PCH_CPT(dev))
4370 cpt_verify_modeset(dev, intel_crtc->pipe);
4371
4372 intel_crtc_enable_planes(crtc);
4373 }
4374
4375 /* IPS only exists on ULT machines and is tied to pipe A. */
4376 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4377 {
4378 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4379 }
4380
4381 /*
4382 * This implements the workaround described in the "notes" section of the mode
4383 * set sequence documentation. When going from no pipes or single pipe to
4384 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4385 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4386 */
4387 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4388 {
4389 struct drm_device *dev = crtc->base.dev;
4390 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4391
4392 /* We want to get the other_active_crtc only if there's only 1 other
4393 * active crtc. */
4394 for_each_intel_crtc(dev, crtc_it) {
4395 if (!crtc_it->active || crtc_it == crtc)
4396 continue;
4397
4398 if (other_active_crtc)
4399 return;
4400
4401 other_active_crtc = crtc_it;
4402 }
4403 if (!other_active_crtc)
4404 return;
4405
4406 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4407 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4408 }
4409
4410 static void haswell_crtc_enable(struct drm_crtc *crtc)
4411 {
4412 struct drm_device *dev = crtc->dev;
4413 struct drm_i915_private *dev_priv = dev->dev_private;
4414 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4415 struct intel_encoder *encoder;
4416 int pipe = intel_crtc->pipe;
4417
4418 WARN_ON(!crtc->enabled);
4419
4420 if (intel_crtc->active)
4421 return;
4422
4423 if (intel_crtc_to_shared_dpll(intel_crtc))
4424 intel_enable_shared_dpll(intel_crtc);
4425
4426 if (intel_crtc->config->has_dp_encoder)
4427 intel_dp_set_m_n(intel_crtc);
4428
4429 intel_set_pipe_timings(intel_crtc);
4430
4431 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4432 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4433 intel_crtc->config->pixel_multiplier - 1);
4434 }
4435
4436 if (intel_crtc->config->has_pch_encoder) {
4437 intel_cpu_transcoder_set_m_n(intel_crtc,
4438 &intel_crtc->config->fdi_m_n, NULL);
4439 }
4440
4441 haswell_set_pipeconf(crtc);
4442
4443 intel_set_pipe_csc(crtc);
4444
4445 intel_crtc->active = true;
4446
4447 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4448 for_each_encoder_on_crtc(dev, crtc, encoder)
4449 if (encoder->pre_enable)
4450 encoder->pre_enable(encoder);
4451
4452 if (intel_crtc->config->has_pch_encoder) {
4453 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4454 true);
4455 dev_priv->display.fdi_link_train(crtc);
4456 }
4457
4458 intel_ddi_enable_pipe_clock(intel_crtc);
4459
4460 if (IS_SKYLAKE(dev))
4461 skylake_pfit_enable(intel_crtc);
4462 else
4463 ironlake_pfit_enable(intel_crtc);
4464
4465 /*
4466 * On ILK+ LUT must be loaded before the pipe is running but with
4467 * clocks enabled
4468 */
4469 intel_crtc_load_lut(crtc);
4470
4471 intel_ddi_set_pipe_settings(crtc);
4472 intel_ddi_enable_transcoder_func(crtc);
4473
4474 intel_update_watermarks(crtc);
4475 intel_enable_pipe(intel_crtc);
4476
4477 if (intel_crtc->config->has_pch_encoder)
4478 lpt_pch_enable(crtc);
4479
4480 if (intel_crtc->config->dp_encoder_is_mst)
4481 intel_ddi_set_vc_payload_alloc(crtc, true);
4482
4483 assert_vblank_disabled(crtc);
4484 drm_crtc_vblank_on(crtc);
4485
4486 for_each_encoder_on_crtc(dev, crtc, encoder) {
4487 encoder->enable(encoder);
4488 intel_opregion_notify_encoder(encoder, true);
4489 }
4490
4491 /* If we change the relative order between pipe/planes enabling, we need
4492 * to change the workaround. */
4493 haswell_mode_set_planes_workaround(intel_crtc);
4494 intel_crtc_enable_planes(crtc);
4495 }
4496
4497 static void skylake_pfit_disable(struct intel_crtc *crtc)
4498 {
4499 struct drm_device *dev = crtc->base.dev;
4500 struct drm_i915_private *dev_priv = dev->dev_private;
4501 int pipe = crtc->pipe;
4502
4503 /* To avoid upsetting the power well on haswell only disable the pfit if
4504 * it's in use. The hw state code will make sure we get this right. */
4505 if (crtc->config->pch_pfit.enabled) {
4506 I915_WRITE(PS_CTL(pipe), 0);
4507 I915_WRITE(PS_WIN_POS(pipe), 0);
4508 I915_WRITE(PS_WIN_SZ(pipe), 0);
4509 }
4510 }
4511
4512 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4513 {
4514 struct drm_device *dev = crtc->base.dev;
4515 struct drm_i915_private *dev_priv = dev->dev_private;
4516 int pipe = crtc->pipe;
4517
4518 /* To avoid upsetting the power well on haswell only disable the pfit if
4519 * it's in use. The hw state code will make sure we get this right. */
4520 if (crtc->config->pch_pfit.enabled) {
4521 I915_WRITE(PF_CTL(pipe), 0);
4522 I915_WRITE(PF_WIN_POS(pipe), 0);
4523 I915_WRITE(PF_WIN_SZ(pipe), 0);
4524 }
4525 }
4526
4527 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4528 {
4529 struct drm_device *dev = crtc->dev;
4530 struct drm_i915_private *dev_priv = dev->dev_private;
4531 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4532 struct intel_encoder *encoder;
4533 int pipe = intel_crtc->pipe;
4534 u32 reg, temp;
4535
4536 if (!intel_crtc->active)
4537 return;
4538
4539 intel_crtc_disable_planes(crtc);
4540
4541 for_each_encoder_on_crtc(dev, crtc, encoder)
4542 encoder->disable(encoder);
4543
4544 drm_crtc_vblank_off(crtc);
4545 assert_vblank_disabled(crtc);
4546
4547 if (intel_crtc->config->has_pch_encoder)
4548 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4549
4550 intel_disable_pipe(intel_crtc);
4551
4552 ironlake_pfit_disable(intel_crtc);
4553
4554 for_each_encoder_on_crtc(dev, crtc, encoder)
4555 if (encoder->post_disable)
4556 encoder->post_disable(encoder);
4557
4558 if (intel_crtc->config->has_pch_encoder) {
4559 ironlake_fdi_disable(crtc);
4560
4561 ironlake_disable_pch_transcoder(dev_priv, pipe);
4562
4563 if (HAS_PCH_CPT(dev)) {
4564 /* disable TRANS_DP_CTL */
4565 reg = TRANS_DP_CTL(pipe);
4566 temp = I915_READ(reg);
4567 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4568 TRANS_DP_PORT_SEL_MASK);
4569 temp |= TRANS_DP_PORT_SEL_NONE;
4570 I915_WRITE(reg, temp);
4571
4572 /* disable DPLL_SEL */
4573 temp = I915_READ(PCH_DPLL_SEL);
4574 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4575 I915_WRITE(PCH_DPLL_SEL, temp);
4576 }
4577
4578 /* disable PCH DPLL */
4579 intel_disable_shared_dpll(intel_crtc);
4580
4581 ironlake_fdi_pll_disable(intel_crtc);
4582 }
4583
4584 intel_crtc->active = false;
4585 intel_update_watermarks(crtc);
4586
4587 mutex_lock(&dev->struct_mutex);
4588 intel_fbc_update(dev);
4589 mutex_unlock(&dev->struct_mutex);
4590 }
4591
4592 static void haswell_crtc_disable(struct drm_crtc *crtc)
4593 {
4594 struct drm_device *dev = crtc->dev;
4595 struct drm_i915_private *dev_priv = dev->dev_private;
4596 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4597 struct intel_encoder *encoder;
4598 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4599
4600 if (!intel_crtc->active)
4601 return;
4602
4603 intel_crtc_disable_planes(crtc);
4604
4605 for_each_encoder_on_crtc(dev, crtc, encoder) {
4606 intel_opregion_notify_encoder(encoder, false);
4607 encoder->disable(encoder);
4608 }
4609
4610 drm_crtc_vblank_off(crtc);
4611 assert_vblank_disabled(crtc);
4612
4613 if (intel_crtc->config->has_pch_encoder)
4614 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4615 false);
4616 intel_disable_pipe(intel_crtc);
4617
4618 if (intel_crtc->config->dp_encoder_is_mst)
4619 intel_ddi_set_vc_payload_alloc(crtc, false);
4620
4621 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4622
4623 if (IS_SKYLAKE(dev))
4624 skylake_pfit_disable(intel_crtc);
4625 else
4626 ironlake_pfit_disable(intel_crtc);
4627
4628 intel_ddi_disable_pipe_clock(intel_crtc);
4629
4630 if (intel_crtc->config->has_pch_encoder) {
4631 lpt_disable_pch_transcoder(dev_priv);
4632 intel_ddi_fdi_disable(crtc);
4633 }
4634
4635 for_each_encoder_on_crtc(dev, crtc, encoder)
4636 if (encoder->post_disable)
4637 encoder->post_disable(encoder);
4638
4639 intel_crtc->active = false;
4640 intel_update_watermarks(crtc);
4641
4642 mutex_lock(&dev->struct_mutex);
4643 intel_fbc_update(dev);
4644 mutex_unlock(&dev->struct_mutex);
4645
4646 if (intel_crtc_to_shared_dpll(intel_crtc))
4647 intel_disable_shared_dpll(intel_crtc);
4648 }
4649
4650 static void ironlake_crtc_off(struct drm_crtc *crtc)
4651 {
4652 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4653 intel_put_shared_dpll(intel_crtc);
4654 }
4655
4656
4657 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4658 {
4659 struct drm_device *dev = crtc->base.dev;
4660 struct drm_i915_private *dev_priv = dev->dev_private;
4661 struct intel_crtc_state *pipe_config = crtc->config;
4662
4663 if (!pipe_config->gmch_pfit.control)
4664 return;
4665
4666 /*
4667 * The panel fitter should only be adjusted whilst the pipe is disabled,
4668 * according to register description and PRM.
4669 */
4670 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4671 assert_pipe_disabled(dev_priv, crtc->pipe);
4672
4673 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4674 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4675
4676 /* Border color in case we don't scale up to the full screen. Black by
4677 * default, change to something else for debugging. */
4678 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4679 }
4680
4681 static enum intel_display_power_domain port_to_power_domain(enum port port)
4682 {
4683 switch (port) {
4684 case PORT_A:
4685 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4686 case PORT_B:
4687 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4688 case PORT_C:
4689 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4690 case PORT_D:
4691 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4692 default:
4693 WARN_ON_ONCE(1);
4694 return POWER_DOMAIN_PORT_OTHER;
4695 }
4696 }
4697
4698 #define for_each_power_domain(domain, mask) \
4699 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4700 if ((1 << (domain)) & (mask))
4701
4702 enum intel_display_power_domain
4703 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4704 {
4705 struct drm_device *dev = intel_encoder->base.dev;
4706 struct intel_digital_port *intel_dig_port;
4707
4708 switch (intel_encoder->type) {
4709 case INTEL_OUTPUT_UNKNOWN:
4710 /* Only DDI platforms should ever use this output type */
4711 WARN_ON_ONCE(!HAS_DDI(dev));
4712 case INTEL_OUTPUT_DISPLAYPORT:
4713 case INTEL_OUTPUT_HDMI:
4714 case INTEL_OUTPUT_EDP:
4715 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4716 return port_to_power_domain(intel_dig_port->port);
4717 case INTEL_OUTPUT_DP_MST:
4718 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4719 return port_to_power_domain(intel_dig_port->port);
4720 case INTEL_OUTPUT_ANALOG:
4721 return POWER_DOMAIN_PORT_CRT;
4722 case INTEL_OUTPUT_DSI:
4723 return POWER_DOMAIN_PORT_DSI;
4724 default:
4725 return POWER_DOMAIN_PORT_OTHER;
4726 }
4727 }
4728
4729 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4730 {
4731 struct drm_device *dev = crtc->dev;
4732 struct intel_encoder *intel_encoder;
4733 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4734 enum pipe pipe = intel_crtc->pipe;
4735 unsigned long mask;
4736 enum transcoder transcoder;
4737
4738 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4739
4740 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4741 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4742 if (intel_crtc->config->pch_pfit.enabled ||
4743 intel_crtc->config->pch_pfit.force_thru)
4744 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4745
4746 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4747 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4748
4749 return mask;
4750 }
4751
4752 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4753 {
4754 struct drm_i915_private *dev_priv = dev->dev_private;
4755 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4756 struct intel_crtc *crtc;
4757
4758 /*
4759 * First get all needed power domains, then put all unneeded, to avoid
4760 * any unnecessary toggling of the power wells.
4761 */
4762 for_each_intel_crtc(dev, crtc) {
4763 enum intel_display_power_domain domain;
4764
4765 if (!crtc->base.enabled)
4766 continue;
4767
4768 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4769
4770 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4771 intel_display_power_get(dev_priv, domain);
4772 }
4773
4774 if (dev_priv->display.modeset_global_resources)
4775 dev_priv->display.modeset_global_resources(dev);
4776
4777 for_each_intel_crtc(dev, crtc) {
4778 enum intel_display_power_domain domain;
4779
4780 for_each_power_domain(domain, crtc->enabled_power_domains)
4781 intel_display_power_put(dev_priv, domain);
4782
4783 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4784 }
4785
4786 intel_display_set_init_power(dev_priv, false);
4787 }
4788
4789 /* returns HPLL frequency in kHz */
4790 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4791 {
4792 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4793
4794 /* Obtain SKU information */
4795 mutex_lock(&dev_priv->dpio_lock);
4796 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4797 CCK_FUSE_HPLL_FREQ_MASK;
4798 mutex_unlock(&dev_priv->dpio_lock);
4799
4800 return vco_freq[hpll_freq] * 1000;
4801 }
4802
4803 static void vlv_update_cdclk(struct drm_device *dev)
4804 {
4805 struct drm_i915_private *dev_priv = dev->dev_private;
4806
4807 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4808 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4809 dev_priv->vlv_cdclk_freq);
4810
4811 /*
4812 * Program the gmbus_freq based on the cdclk frequency.
4813 * BSpec erroneously claims we should aim for 4MHz, but
4814 * in fact 1MHz is the correct frequency.
4815 */
4816 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
4817 }
4818
4819 /* Adjust CDclk dividers to allow high res or save power if possible */
4820 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4821 {
4822 struct drm_i915_private *dev_priv = dev->dev_private;
4823 u32 val, cmd;
4824
4825 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4826
4827 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4828 cmd = 2;
4829 else if (cdclk == 266667)
4830 cmd = 1;
4831 else
4832 cmd = 0;
4833
4834 mutex_lock(&dev_priv->rps.hw_lock);
4835 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4836 val &= ~DSPFREQGUAR_MASK;
4837 val |= (cmd << DSPFREQGUAR_SHIFT);
4838 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4839 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4840 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4841 50)) {
4842 DRM_ERROR("timed out waiting for CDclk change\n");
4843 }
4844 mutex_unlock(&dev_priv->rps.hw_lock);
4845
4846 if (cdclk == 400000) {
4847 u32 divider;
4848
4849 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
4850
4851 mutex_lock(&dev_priv->dpio_lock);
4852 /* adjust cdclk divider */
4853 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4854 val &= ~DISPLAY_FREQUENCY_VALUES;
4855 val |= divider;
4856 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4857
4858 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4859 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4860 50))
4861 DRM_ERROR("timed out waiting for CDclk change\n");
4862 mutex_unlock(&dev_priv->dpio_lock);
4863 }
4864
4865 mutex_lock(&dev_priv->dpio_lock);
4866 /* adjust self-refresh exit latency value */
4867 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4868 val &= ~0x7f;
4869
4870 /*
4871 * For high bandwidth configs, we set a higher latency in the bunit
4872 * so that the core display fetch happens in time to avoid underruns.
4873 */
4874 if (cdclk == 400000)
4875 val |= 4500 / 250; /* 4.5 usec */
4876 else
4877 val |= 3000 / 250; /* 3.0 usec */
4878 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4879 mutex_unlock(&dev_priv->dpio_lock);
4880
4881 vlv_update_cdclk(dev);
4882 }
4883
4884 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4885 {
4886 struct drm_i915_private *dev_priv = dev->dev_private;
4887 u32 val, cmd;
4888
4889 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4890
4891 switch (cdclk) {
4892 case 400000:
4893 cmd = 3;
4894 break;
4895 case 333333:
4896 case 320000:
4897 cmd = 2;
4898 break;
4899 case 266667:
4900 cmd = 1;
4901 break;
4902 case 200000:
4903 cmd = 0;
4904 break;
4905 default:
4906 MISSING_CASE(cdclk);
4907 return;
4908 }
4909
4910 mutex_lock(&dev_priv->rps.hw_lock);
4911 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4912 val &= ~DSPFREQGUAR_MASK_CHV;
4913 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4914 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4915 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4916 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4917 50)) {
4918 DRM_ERROR("timed out waiting for CDclk change\n");
4919 }
4920 mutex_unlock(&dev_priv->rps.hw_lock);
4921
4922 vlv_update_cdclk(dev);
4923 }
4924
4925 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4926 int max_pixclk)
4927 {
4928 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
4929
4930 /* FIXME: Punit isn't quite ready yet */
4931 if (IS_CHERRYVIEW(dev_priv->dev))
4932 return 400000;
4933
4934 /*
4935 * Really only a few cases to deal with, as only 4 CDclks are supported:
4936 * 200MHz
4937 * 267MHz
4938 * 320/333MHz (depends on HPLL freq)
4939 * 400MHz
4940 * So we check to see whether we're above 90% of the lower bin and
4941 * adjust if needed.
4942 *
4943 * We seem to get an unstable or solid color picture at 200MHz.
4944 * Not sure what's wrong. For now use 200MHz only when all pipes
4945 * are off.
4946 */
4947 if (max_pixclk > freq_320*9/10)
4948 return 400000;
4949 else if (max_pixclk > 266667*9/10)
4950 return freq_320;
4951 else if (max_pixclk > 0)
4952 return 266667;
4953 else
4954 return 200000;
4955 }
4956
4957 /* compute the max pixel clock for new configuration */
4958 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4959 {
4960 struct drm_device *dev = dev_priv->dev;
4961 struct intel_crtc *intel_crtc;
4962 int max_pixclk = 0;
4963
4964 for_each_intel_crtc(dev, intel_crtc) {
4965 if (intel_crtc->new_enabled)
4966 max_pixclk = max(max_pixclk,
4967 intel_crtc->new_config->base.adjusted_mode.crtc_clock);
4968 }
4969
4970 return max_pixclk;
4971 }
4972
4973 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4974 unsigned *prepare_pipes)
4975 {
4976 struct drm_i915_private *dev_priv = dev->dev_private;
4977 struct intel_crtc *intel_crtc;
4978 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4979
4980 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4981 dev_priv->vlv_cdclk_freq)
4982 return;
4983
4984 /* disable/enable all currently active pipes while we change cdclk */
4985 for_each_intel_crtc(dev, intel_crtc)
4986 if (intel_crtc->base.enabled)
4987 *prepare_pipes |= (1 << intel_crtc->pipe);
4988 }
4989
4990 static void valleyview_modeset_global_resources(struct drm_device *dev)
4991 {
4992 struct drm_i915_private *dev_priv = dev->dev_private;
4993 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4994 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4995
4996 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
4997 /*
4998 * FIXME: We can end up here with all power domains off, yet
4999 * with a CDCLK frequency other than the minimum. To account
5000 * for this take the PIPE-A power domain, which covers the HW
5001 * blocks needed for the following programming. This can be
5002 * removed once it's guaranteed that we get here either with
5003 * the minimum CDCLK set, or the required power domains
5004 * enabled.
5005 */
5006 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5007
5008 if (IS_CHERRYVIEW(dev))
5009 cherryview_set_cdclk(dev, req_cdclk);
5010 else
5011 valleyview_set_cdclk(dev, req_cdclk);
5012
5013 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5014 }
5015 }
5016
5017 static void valleyview_crtc_enable(struct drm_crtc *crtc)
5018 {
5019 struct drm_device *dev = crtc->dev;
5020 struct drm_i915_private *dev_priv = to_i915(dev);
5021 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5022 struct intel_encoder *encoder;
5023 int pipe = intel_crtc->pipe;
5024 bool is_dsi;
5025
5026 WARN_ON(!crtc->enabled);
5027
5028 if (intel_crtc->active)
5029 return;
5030
5031 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5032
5033 if (!is_dsi) {
5034 if (IS_CHERRYVIEW(dev))
5035 chv_prepare_pll(intel_crtc, intel_crtc->config);
5036 else
5037 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5038 }
5039
5040 if (intel_crtc->config->has_dp_encoder)
5041 intel_dp_set_m_n(intel_crtc);
5042
5043 intel_set_pipe_timings(intel_crtc);
5044
5045 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5046 struct drm_i915_private *dev_priv = dev->dev_private;
5047
5048 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5049 I915_WRITE(CHV_CANVAS(pipe), 0);
5050 }
5051
5052 i9xx_set_pipeconf(intel_crtc);
5053
5054 intel_crtc->active = true;
5055
5056 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5057
5058 for_each_encoder_on_crtc(dev, crtc, encoder)
5059 if (encoder->pre_pll_enable)
5060 encoder->pre_pll_enable(encoder);
5061
5062 if (!is_dsi) {
5063 if (IS_CHERRYVIEW(dev))
5064 chv_enable_pll(intel_crtc, intel_crtc->config);
5065 else
5066 vlv_enable_pll(intel_crtc, intel_crtc->config);
5067 }
5068
5069 for_each_encoder_on_crtc(dev, crtc, encoder)
5070 if (encoder->pre_enable)
5071 encoder->pre_enable(encoder);
5072
5073 i9xx_pfit_enable(intel_crtc);
5074
5075 intel_crtc_load_lut(crtc);
5076
5077 intel_update_watermarks(crtc);
5078 intel_enable_pipe(intel_crtc);
5079
5080 assert_vblank_disabled(crtc);
5081 drm_crtc_vblank_on(crtc);
5082
5083 for_each_encoder_on_crtc(dev, crtc, encoder)
5084 encoder->enable(encoder);
5085
5086 intel_crtc_enable_planes(crtc);
5087
5088 /* Underruns don't raise interrupts, so check manually. */
5089 i9xx_check_fifo_underruns(dev_priv);
5090 }
5091
5092 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5093 {
5094 struct drm_device *dev = crtc->base.dev;
5095 struct drm_i915_private *dev_priv = dev->dev_private;
5096
5097 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5098 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5099 }
5100
5101 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5102 {
5103 struct drm_device *dev = crtc->dev;
5104 struct drm_i915_private *dev_priv = to_i915(dev);
5105 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5106 struct intel_encoder *encoder;
5107 int pipe = intel_crtc->pipe;
5108
5109 WARN_ON(!crtc->enabled);
5110
5111 if (intel_crtc->active)
5112 return;
5113
5114 i9xx_set_pll_dividers(intel_crtc);
5115
5116 if (intel_crtc->config->has_dp_encoder)
5117 intel_dp_set_m_n(intel_crtc);
5118
5119 intel_set_pipe_timings(intel_crtc);
5120
5121 i9xx_set_pipeconf(intel_crtc);
5122
5123 intel_crtc->active = true;
5124
5125 if (!IS_GEN2(dev))
5126 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5127
5128 for_each_encoder_on_crtc(dev, crtc, encoder)
5129 if (encoder->pre_enable)
5130 encoder->pre_enable(encoder);
5131
5132 i9xx_enable_pll(intel_crtc);
5133
5134 i9xx_pfit_enable(intel_crtc);
5135
5136 intel_crtc_load_lut(crtc);
5137
5138 intel_update_watermarks(crtc);
5139 intel_enable_pipe(intel_crtc);
5140
5141 assert_vblank_disabled(crtc);
5142 drm_crtc_vblank_on(crtc);
5143
5144 for_each_encoder_on_crtc(dev, crtc, encoder)
5145 encoder->enable(encoder);
5146
5147 intel_crtc_enable_planes(crtc);
5148
5149 /*
5150 * Gen2 reports pipe underruns whenever all planes are disabled.
5151 * So don't enable underrun reporting before at least some planes
5152 * are enabled.
5153 * FIXME: Need to fix the logic to work when we turn off all planes
5154 * but leave the pipe running.
5155 */
5156 if (IS_GEN2(dev))
5157 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5158
5159 /* Underruns don't raise interrupts, so check manually. */
5160 i9xx_check_fifo_underruns(dev_priv);
5161 }
5162
5163 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5164 {
5165 struct drm_device *dev = crtc->base.dev;
5166 struct drm_i915_private *dev_priv = dev->dev_private;
5167
5168 if (!crtc->config->gmch_pfit.control)
5169 return;
5170
5171 assert_pipe_disabled(dev_priv, crtc->pipe);
5172
5173 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5174 I915_READ(PFIT_CONTROL));
5175 I915_WRITE(PFIT_CONTROL, 0);
5176 }
5177
5178 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5179 {
5180 struct drm_device *dev = crtc->dev;
5181 struct drm_i915_private *dev_priv = dev->dev_private;
5182 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5183 struct intel_encoder *encoder;
5184 int pipe = intel_crtc->pipe;
5185
5186 if (!intel_crtc->active)
5187 return;
5188
5189 /*
5190 * Gen2 reports pipe underruns whenever all planes are disabled.
5191 * So diasble underrun reporting before all the planes get disabled.
5192 * FIXME: Need to fix the logic to work when we turn off all planes
5193 * but leave the pipe running.
5194 */
5195 if (IS_GEN2(dev))
5196 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5197
5198 /*
5199 * Vblank time updates from the shadow to live plane control register
5200 * are blocked if the memory self-refresh mode is active at that
5201 * moment. So to make sure the plane gets truly disabled, disable
5202 * first the self-refresh mode. The self-refresh enable bit in turn
5203 * will be checked/applied by the HW only at the next frame start
5204 * event which is after the vblank start event, so we need to have a
5205 * wait-for-vblank between disabling the plane and the pipe.
5206 */
5207 intel_set_memory_cxsr(dev_priv, false);
5208 intel_crtc_disable_planes(crtc);
5209
5210 /*
5211 * On gen2 planes are double buffered but the pipe isn't, so we must
5212 * wait for planes to fully turn off before disabling the pipe.
5213 * We also need to wait on all gmch platforms because of the
5214 * self-refresh mode constraint explained above.
5215 */
5216 intel_wait_for_vblank(dev, pipe);
5217
5218 for_each_encoder_on_crtc(dev, crtc, encoder)
5219 encoder->disable(encoder);
5220
5221 drm_crtc_vblank_off(crtc);
5222 assert_vblank_disabled(crtc);
5223
5224 intel_disable_pipe(intel_crtc);
5225
5226 i9xx_pfit_disable(intel_crtc);
5227
5228 for_each_encoder_on_crtc(dev, crtc, encoder)
5229 if (encoder->post_disable)
5230 encoder->post_disable(encoder);
5231
5232 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5233 if (IS_CHERRYVIEW(dev))
5234 chv_disable_pll(dev_priv, pipe);
5235 else if (IS_VALLEYVIEW(dev))
5236 vlv_disable_pll(dev_priv, pipe);
5237 else
5238 i9xx_disable_pll(intel_crtc);
5239 }
5240
5241 if (!IS_GEN2(dev))
5242 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5243
5244 intel_crtc->active = false;
5245 intel_update_watermarks(crtc);
5246
5247 mutex_lock(&dev->struct_mutex);
5248 intel_fbc_update(dev);
5249 mutex_unlock(&dev->struct_mutex);
5250 }
5251
5252 static void i9xx_crtc_off(struct drm_crtc *crtc)
5253 {
5254 }
5255
5256 /* Master function to enable/disable CRTC and corresponding power wells */
5257 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5258 {
5259 struct drm_device *dev = crtc->dev;
5260 struct drm_i915_private *dev_priv = dev->dev_private;
5261 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5262 enum intel_display_power_domain domain;
5263 unsigned long domains;
5264
5265 if (enable) {
5266 if (!intel_crtc->active) {
5267 domains = get_crtc_power_domains(crtc);
5268 for_each_power_domain(domain, domains)
5269 intel_display_power_get(dev_priv, domain);
5270 intel_crtc->enabled_power_domains = domains;
5271
5272 dev_priv->display.crtc_enable(crtc);
5273 }
5274 } else {
5275 if (intel_crtc->active) {
5276 dev_priv->display.crtc_disable(crtc);
5277
5278 domains = intel_crtc->enabled_power_domains;
5279 for_each_power_domain(domain, domains)
5280 intel_display_power_put(dev_priv, domain);
5281 intel_crtc->enabled_power_domains = 0;
5282 }
5283 }
5284 }
5285
5286 /**
5287 * Sets the power management mode of the pipe and plane.
5288 */
5289 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5290 {
5291 struct drm_device *dev = crtc->dev;
5292 struct intel_encoder *intel_encoder;
5293 bool enable = false;
5294
5295 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5296 enable |= intel_encoder->connectors_active;
5297
5298 intel_crtc_control(crtc, enable);
5299 }
5300
5301 static void intel_crtc_disable(struct drm_crtc *crtc)
5302 {
5303 struct drm_device *dev = crtc->dev;
5304 struct drm_connector *connector;
5305 struct drm_i915_private *dev_priv = dev->dev_private;
5306
5307 /* crtc should still be enabled when we disable it. */
5308 WARN_ON(!crtc->enabled);
5309
5310 dev_priv->display.crtc_disable(crtc);
5311 dev_priv->display.off(crtc);
5312
5313 crtc->primary->funcs->disable_plane(crtc->primary);
5314
5315 /* Update computed state. */
5316 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5317 if (!connector->encoder || !connector->encoder->crtc)
5318 continue;
5319
5320 if (connector->encoder->crtc != crtc)
5321 continue;
5322
5323 connector->dpms = DRM_MODE_DPMS_OFF;
5324 to_intel_encoder(connector->encoder)->connectors_active = false;
5325 }
5326 }
5327
5328 void intel_encoder_destroy(struct drm_encoder *encoder)
5329 {
5330 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5331
5332 drm_encoder_cleanup(encoder);
5333 kfree(intel_encoder);
5334 }
5335
5336 /* Simple dpms helper for encoders with just one connector, no cloning and only
5337 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5338 * state of the entire output pipe. */
5339 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5340 {
5341 if (mode == DRM_MODE_DPMS_ON) {
5342 encoder->connectors_active = true;
5343
5344 intel_crtc_update_dpms(encoder->base.crtc);
5345 } else {
5346 encoder->connectors_active = false;
5347
5348 intel_crtc_update_dpms(encoder->base.crtc);
5349 }
5350 }
5351
5352 /* Cross check the actual hw state with our own modeset state tracking (and it's
5353 * internal consistency). */
5354 static void intel_connector_check_state(struct intel_connector *connector)
5355 {
5356 if (connector->get_hw_state(connector)) {
5357 struct intel_encoder *encoder = connector->encoder;
5358 struct drm_crtc *crtc;
5359 bool encoder_enabled;
5360 enum pipe pipe;
5361
5362 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5363 connector->base.base.id,
5364 connector->base.name);
5365
5366 /* there is no real hw state for MST connectors */
5367 if (connector->mst_port)
5368 return;
5369
5370 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5371 "wrong connector dpms state\n");
5372 I915_STATE_WARN(connector->base.encoder != &encoder->base,
5373 "active connector not linked to encoder\n");
5374
5375 if (encoder) {
5376 I915_STATE_WARN(!encoder->connectors_active,
5377 "encoder->connectors_active not set\n");
5378
5379 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5380 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
5381 if (I915_STATE_WARN_ON(!encoder->base.crtc))
5382 return;
5383
5384 crtc = encoder->base.crtc;
5385
5386 I915_STATE_WARN(!crtc->enabled, "crtc not enabled\n");
5387 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5388 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
5389 "encoder active on the wrong pipe\n");
5390 }
5391 }
5392 }
5393
5394 /* Even simpler default implementation, if there's really no special case to
5395 * consider. */
5396 void intel_connector_dpms(struct drm_connector *connector, int mode)
5397 {
5398 /* All the simple cases only support two dpms states. */
5399 if (mode != DRM_MODE_DPMS_ON)
5400 mode = DRM_MODE_DPMS_OFF;
5401
5402 if (mode == connector->dpms)
5403 return;
5404
5405 connector->dpms = mode;
5406
5407 /* Only need to change hw state when actually enabled */
5408 if (connector->encoder)
5409 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5410
5411 intel_modeset_check_state(connector->dev);
5412 }
5413
5414 /* Simple connector->get_hw_state implementation for encoders that support only
5415 * one connector and no cloning and hence the encoder state determines the state
5416 * of the connector. */
5417 bool intel_connector_get_hw_state(struct intel_connector *connector)
5418 {
5419 enum pipe pipe = 0;
5420 struct intel_encoder *encoder = connector->encoder;
5421
5422 return encoder->get_hw_state(encoder, &pipe);
5423 }
5424
5425 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5426 struct intel_crtc_state *pipe_config)
5427 {
5428 struct drm_i915_private *dev_priv = dev->dev_private;
5429 struct intel_crtc *pipe_B_crtc =
5430 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5431
5432 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5433 pipe_name(pipe), pipe_config->fdi_lanes);
5434 if (pipe_config->fdi_lanes > 4) {
5435 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5436 pipe_name(pipe), pipe_config->fdi_lanes);
5437 return false;
5438 }
5439
5440 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5441 if (pipe_config->fdi_lanes > 2) {
5442 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5443 pipe_config->fdi_lanes);
5444 return false;
5445 } else {
5446 return true;
5447 }
5448 }
5449
5450 if (INTEL_INFO(dev)->num_pipes == 2)
5451 return true;
5452
5453 /* Ivybridge 3 pipe is really complicated */
5454 switch (pipe) {
5455 case PIPE_A:
5456 return true;
5457 case PIPE_B:
5458 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5459 pipe_config->fdi_lanes > 2) {
5460 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5461 pipe_name(pipe), pipe_config->fdi_lanes);
5462 return false;
5463 }
5464 return true;
5465 case PIPE_C:
5466 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5467 pipe_B_crtc->config->fdi_lanes <= 2) {
5468 if (pipe_config->fdi_lanes > 2) {
5469 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5470 pipe_name(pipe), pipe_config->fdi_lanes);
5471 return false;
5472 }
5473 } else {
5474 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5475 return false;
5476 }
5477 return true;
5478 default:
5479 BUG();
5480 }
5481 }
5482
5483 #define RETRY 1
5484 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5485 struct intel_crtc_state *pipe_config)
5486 {
5487 struct drm_device *dev = intel_crtc->base.dev;
5488 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5489 int lane, link_bw, fdi_dotclock;
5490 bool setup_ok, needs_recompute = false;
5491
5492 retry:
5493 /* FDI is a binary signal running at ~2.7GHz, encoding
5494 * each output octet as 10 bits. The actual frequency
5495 * is stored as a divider into a 100MHz clock, and the
5496 * mode pixel clock is stored in units of 1KHz.
5497 * Hence the bw of each lane in terms of the mode signal
5498 * is:
5499 */
5500 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5501
5502 fdi_dotclock = adjusted_mode->crtc_clock;
5503
5504 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5505 pipe_config->pipe_bpp);
5506
5507 pipe_config->fdi_lanes = lane;
5508
5509 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5510 link_bw, &pipe_config->fdi_m_n);
5511
5512 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5513 intel_crtc->pipe, pipe_config);
5514 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5515 pipe_config->pipe_bpp -= 2*3;
5516 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5517 pipe_config->pipe_bpp);
5518 needs_recompute = true;
5519 pipe_config->bw_constrained = true;
5520
5521 goto retry;
5522 }
5523
5524 if (needs_recompute)
5525 return RETRY;
5526
5527 return setup_ok ? 0 : -EINVAL;
5528 }
5529
5530 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5531 struct intel_crtc_state *pipe_config)
5532 {
5533 pipe_config->ips_enabled = i915.enable_ips &&
5534 hsw_crtc_supports_ips(crtc) &&
5535 pipe_config->pipe_bpp <= 24;
5536 }
5537
5538 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5539 struct intel_crtc_state *pipe_config)
5540 {
5541 struct drm_device *dev = crtc->base.dev;
5542 struct drm_i915_private *dev_priv = dev->dev_private;
5543 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5544
5545 /* FIXME should check pixel clock limits on all platforms */
5546 if (INTEL_INFO(dev)->gen < 4) {
5547 int clock_limit =
5548 dev_priv->display.get_display_clock_speed(dev);
5549
5550 /*
5551 * Enable pixel doubling when the dot clock
5552 * is > 90% of the (display) core speed.
5553 *
5554 * GDG double wide on either pipe,
5555 * otherwise pipe A only.
5556 */
5557 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5558 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5559 clock_limit *= 2;
5560 pipe_config->double_wide = true;
5561 }
5562
5563 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5564 return -EINVAL;
5565 }
5566
5567 /*
5568 * Pipe horizontal size must be even in:
5569 * - DVO ganged mode
5570 * - LVDS dual channel mode
5571 * - Double wide pipe
5572 */
5573 if ((intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5574 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5575 pipe_config->pipe_src_w &= ~1;
5576
5577 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5578 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5579 */
5580 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5581 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5582 return -EINVAL;
5583
5584 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5585 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5586 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5587 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5588 * for lvds. */
5589 pipe_config->pipe_bpp = 8*3;
5590 }
5591
5592 if (HAS_IPS(dev))
5593 hsw_compute_ips_config(crtc, pipe_config);
5594
5595 if (pipe_config->has_pch_encoder)
5596 return ironlake_fdi_compute_config(crtc, pipe_config);
5597
5598 return 0;
5599 }
5600
5601 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5602 {
5603 struct drm_i915_private *dev_priv = dev->dev_private;
5604 u32 val;
5605 int divider;
5606
5607 /* FIXME: Punit isn't quite ready yet */
5608 if (IS_CHERRYVIEW(dev))
5609 return 400000;
5610
5611 if (dev_priv->hpll_freq == 0)
5612 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5613
5614 mutex_lock(&dev_priv->dpio_lock);
5615 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5616 mutex_unlock(&dev_priv->dpio_lock);
5617
5618 divider = val & DISPLAY_FREQUENCY_VALUES;
5619
5620 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5621 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5622 "cdclk change in progress\n");
5623
5624 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
5625 }
5626
5627 static int i945_get_display_clock_speed(struct drm_device *dev)
5628 {
5629 return 400000;
5630 }
5631
5632 static int i915_get_display_clock_speed(struct drm_device *dev)
5633 {
5634 return 333000;
5635 }
5636
5637 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5638 {
5639 return 200000;
5640 }
5641
5642 static int pnv_get_display_clock_speed(struct drm_device *dev)
5643 {
5644 u16 gcfgc = 0;
5645
5646 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5647
5648 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5649 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5650 return 267000;
5651 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5652 return 333000;
5653 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5654 return 444000;
5655 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5656 return 200000;
5657 default:
5658 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5659 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5660 return 133000;
5661 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5662 return 167000;
5663 }
5664 }
5665
5666 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5667 {
5668 u16 gcfgc = 0;
5669
5670 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5671
5672 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5673 return 133000;
5674 else {
5675 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5676 case GC_DISPLAY_CLOCK_333_MHZ:
5677 return 333000;
5678 default:
5679 case GC_DISPLAY_CLOCK_190_200_MHZ:
5680 return 190000;
5681 }
5682 }
5683 }
5684
5685 static int i865_get_display_clock_speed(struct drm_device *dev)
5686 {
5687 return 266000;
5688 }
5689
5690 static int i855_get_display_clock_speed(struct drm_device *dev)
5691 {
5692 u16 hpllcc = 0;
5693 /* Assume that the hardware is in the high speed state. This
5694 * should be the default.
5695 */
5696 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5697 case GC_CLOCK_133_200:
5698 case GC_CLOCK_100_200:
5699 return 200000;
5700 case GC_CLOCK_166_250:
5701 return 250000;
5702 case GC_CLOCK_100_133:
5703 return 133000;
5704 }
5705
5706 /* Shouldn't happen */
5707 return 0;
5708 }
5709
5710 static int i830_get_display_clock_speed(struct drm_device *dev)
5711 {
5712 return 133000;
5713 }
5714
5715 static void
5716 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5717 {
5718 while (*num > DATA_LINK_M_N_MASK ||
5719 *den > DATA_LINK_M_N_MASK) {
5720 *num >>= 1;
5721 *den >>= 1;
5722 }
5723 }
5724
5725 static void compute_m_n(unsigned int m, unsigned int n,
5726 uint32_t *ret_m, uint32_t *ret_n)
5727 {
5728 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5729 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5730 intel_reduce_m_n_ratio(ret_m, ret_n);
5731 }
5732
5733 void
5734 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5735 int pixel_clock, int link_clock,
5736 struct intel_link_m_n *m_n)
5737 {
5738 m_n->tu = 64;
5739
5740 compute_m_n(bits_per_pixel * pixel_clock,
5741 link_clock * nlanes * 8,
5742 &m_n->gmch_m, &m_n->gmch_n);
5743
5744 compute_m_n(pixel_clock, link_clock,
5745 &m_n->link_m, &m_n->link_n);
5746 }
5747
5748 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5749 {
5750 if (i915.panel_use_ssc >= 0)
5751 return i915.panel_use_ssc != 0;
5752 return dev_priv->vbt.lvds_use_ssc
5753 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5754 }
5755
5756 static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5757 {
5758 struct drm_device *dev = crtc->base.dev;
5759 struct drm_i915_private *dev_priv = dev->dev_private;
5760 int refclk;
5761
5762 if (IS_VALLEYVIEW(dev)) {
5763 refclk = 100000;
5764 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5765 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5766 refclk = dev_priv->vbt.lvds_ssc_freq;
5767 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5768 } else if (!IS_GEN2(dev)) {
5769 refclk = 96000;
5770 } else {
5771 refclk = 48000;
5772 }
5773
5774 return refclk;
5775 }
5776
5777 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5778 {
5779 return (1 << dpll->n) << 16 | dpll->m2;
5780 }
5781
5782 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5783 {
5784 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5785 }
5786
5787 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5788 struct intel_crtc_state *crtc_state,
5789 intel_clock_t *reduced_clock)
5790 {
5791 struct drm_device *dev = crtc->base.dev;
5792 u32 fp, fp2 = 0;
5793
5794 if (IS_PINEVIEW(dev)) {
5795 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
5796 if (reduced_clock)
5797 fp2 = pnv_dpll_compute_fp(reduced_clock);
5798 } else {
5799 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
5800 if (reduced_clock)
5801 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5802 }
5803
5804 crtc_state->dpll_hw_state.fp0 = fp;
5805
5806 crtc->lowfreq_avail = false;
5807 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5808 reduced_clock && i915.powersave) {
5809 crtc_state->dpll_hw_state.fp1 = fp2;
5810 crtc->lowfreq_avail = true;
5811 } else {
5812 crtc_state->dpll_hw_state.fp1 = fp;
5813 }
5814 }
5815
5816 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5817 pipe)
5818 {
5819 u32 reg_val;
5820
5821 /*
5822 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5823 * and set it to a reasonable value instead.
5824 */
5825 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5826 reg_val &= 0xffffff00;
5827 reg_val |= 0x00000030;
5828 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5829
5830 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5831 reg_val &= 0x8cffffff;
5832 reg_val = 0x8c000000;
5833 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5834
5835 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5836 reg_val &= 0xffffff00;
5837 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5838
5839 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5840 reg_val &= 0x00ffffff;
5841 reg_val |= 0xb0000000;
5842 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5843 }
5844
5845 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5846 struct intel_link_m_n *m_n)
5847 {
5848 struct drm_device *dev = crtc->base.dev;
5849 struct drm_i915_private *dev_priv = dev->dev_private;
5850 int pipe = crtc->pipe;
5851
5852 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5853 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5854 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5855 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5856 }
5857
5858 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5859 struct intel_link_m_n *m_n,
5860 struct intel_link_m_n *m2_n2)
5861 {
5862 struct drm_device *dev = crtc->base.dev;
5863 struct drm_i915_private *dev_priv = dev->dev_private;
5864 int pipe = crtc->pipe;
5865 enum transcoder transcoder = crtc->config->cpu_transcoder;
5866
5867 if (INTEL_INFO(dev)->gen >= 5) {
5868 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5869 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5870 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5871 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5872 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5873 * for gen < 8) and if DRRS is supported (to make sure the
5874 * registers are not unnecessarily accessed).
5875 */
5876 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5877 crtc->config->has_drrs) {
5878 I915_WRITE(PIPE_DATA_M2(transcoder),
5879 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5880 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5881 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5882 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5883 }
5884 } else {
5885 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5886 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5887 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5888 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5889 }
5890 }
5891
5892 void intel_dp_set_m_n(struct intel_crtc *crtc)
5893 {
5894 if (crtc->config->has_pch_encoder)
5895 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
5896 else
5897 intel_cpu_transcoder_set_m_n(crtc, &crtc->config->dp_m_n,
5898 &crtc->config->dp_m2_n2);
5899 }
5900
5901 static void vlv_update_pll(struct intel_crtc *crtc,
5902 struct intel_crtc_state *pipe_config)
5903 {
5904 u32 dpll, dpll_md;
5905
5906 /*
5907 * Enable DPIO clock input. We should never disable the reference
5908 * clock for pipe B, since VGA hotplug / manual detection depends
5909 * on it.
5910 */
5911 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5912 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5913 /* We should never disable this, set it here for state tracking */
5914 if (crtc->pipe == PIPE_B)
5915 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5916 dpll |= DPLL_VCO_ENABLE;
5917 pipe_config->dpll_hw_state.dpll = dpll;
5918
5919 dpll_md = (pipe_config->pixel_multiplier - 1)
5920 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5921 pipe_config->dpll_hw_state.dpll_md = dpll_md;
5922 }
5923
5924 static void vlv_prepare_pll(struct intel_crtc *crtc,
5925 const struct intel_crtc_state *pipe_config)
5926 {
5927 struct drm_device *dev = crtc->base.dev;
5928 struct drm_i915_private *dev_priv = dev->dev_private;
5929 int pipe = crtc->pipe;
5930 u32 mdiv;
5931 u32 bestn, bestm1, bestm2, bestp1, bestp2;
5932 u32 coreclk, reg_val;
5933
5934 mutex_lock(&dev_priv->dpio_lock);
5935
5936 bestn = pipe_config->dpll.n;
5937 bestm1 = pipe_config->dpll.m1;
5938 bestm2 = pipe_config->dpll.m2;
5939 bestp1 = pipe_config->dpll.p1;
5940 bestp2 = pipe_config->dpll.p2;
5941
5942 /* See eDP HDMI DPIO driver vbios notes doc */
5943
5944 /* PLL B needs special handling */
5945 if (pipe == PIPE_B)
5946 vlv_pllb_recal_opamp(dev_priv, pipe);
5947
5948 /* Set up Tx target for periodic Rcomp update */
5949 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5950
5951 /* Disable target IRef on PLL */
5952 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5953 reg_val &= 0x00ffffff;
5954 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5955
5956 /* Disable fast lock */
5957 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5958
5959 /* Set idtafcrecal before PLL is enabled */
5960 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5961 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5962 mdiv |= ((bestn << DPIO_N_SHIFT));
5963 mdiv |= (1 << DPIO_K_SHIFT);
5964
5965 /*
5966 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5967 * but we don't support that).
5968 * Note: don't use the DAC post divider as it seems unstable.
5969 */
5970 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5971 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5972
5973 mdiv |= DPIO_ENABLE_CALIBRATION;
5974 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5975
5976 /* Set HBR and RBR LPF coefficients */
5977 if (pipe_config->port_clock == 162000 ||
5978 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
5979 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
5980 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5981 0x009f0003);
5982 else
5983 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5984 0x00d0000f);
5985
5986 if (pipe_config->has_dp_encoder) {
5987 /* Use SSC source */
5988 if (pipe == PIPE_A)
5989 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5990 0x0df40000);
5991 else
5992 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5993 0x0df70000);
5994 } else { /* HDMI or VGA */
5995 /* Use bend source */
5996 if (pipe == PIPE_A)
5997 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5998 0x0df70000);
5999 else
6000 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6001 0x0df40000);
6002 }
6003
6004 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6005 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6006 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6007 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
6008 coreclk |= 0x01000000;
6009 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6010
6011 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6012 mutex_unlock(&dev_priv->dpio_lock);
6013 }
6014
6015 static void chv_update_pll(struct intel_crtc *crtc,
6016 struct intel_crtc_state *pipe_config)
6017 {
6018 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
6019 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6020 DPLL_VCO_ENABLE;
6021 if (crtc->pipe != PIPE_A)
6022 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6023
6024 pipe_config->dpll_hw_state.dpll_md =
6025 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6026 }
6027
6028 static void chv_prepare_pll(struct intel_crtc *crtc,
6029 const struct intel_crtc_state *pipe_config)
6030 {
6031 struct drm_device *dev = crtc->base.dev;
6032 struct drm_i915_private *dev_priv = dev->dev_private;
6033 int pipe = crtc->pipe;
6034 int dpll_reg = DPLL(crtc->pipe);
6035 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6036 u32 loopfilter, intcoeff;
6037 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6038 int refclk;
6039
6040 bestn = pipe_config->dpll.n;
6041 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6042 bestm1 = pipe_config->dpll.m1;
6043 bestm2 = pipe_config->dpll.m2 >> 22;
6044 bestp1 = pipe_config->dpll.p1;
6045 bestp2 = pipe_config->dpll.p2;
6046
6047 /*
6048 * Enable Refclk and SSC
6049 */
6050 I915_WRITE(dpll_reg,
6051 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6052
6053 mutex_lock(&dev_priv->dpio_lock);
6054
6055 /* p1 and p2 divider */
6056 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6057 5 << DPIO_CHV_S1_DIV_SHIFT |
6058 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6059 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6060 1 << DPIO_CHV_K_DIV_SHIFT);
6061
6062 /* Feedback post-divider - m2 */
6063 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6064
6065 /* Feedback refclk divider - n and m1 */
6066 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6067 DPIO_CHV_M1_DIV_BY_2 |
6068 1 << DPIO_CHV_N_DIV_SHIFT);
6069
6070 /* M2 fraction division */
6071 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6072
6073 /* M2 fraction division enable */
6074 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
6075 DPIO_CHV_FRAC_DIV_EN |
6076 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
6077
6078 /* Loop filter */
6079 refclk = i9xx_get_refclk(crtc, 0);
6080 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
6081 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
6082 if (refclk == 100000)
6083 intcoeff = 11;
6084 else if (refclk == 38400)
6085 intcoeff = 10;
6086 else
6087 intcoeff = 9;
6088 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
6089 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6090
6091 /* AFC Recal */
6092 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6093 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6094 DPIO_AFC_RECAL);
6095
6096 mutex_unlock(&dev_priv->dpio_lock);
6097 }
6098
6099 /**
6100 * vlv_force_pll_on - forcibly enable just the PLL
6101 * @dev_priv: i915 private structure
6102 * @pipe: pipe PLL to enable
6103 * @dpll: PLL configuration
6104 *
6105 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6106 * in cases where we need the PLL enabled even when @pipe is not going to
6107 * be enabled.
6108 */
6109 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6110 const struct dpll *dpll)
6111 {
6112 struct intel_crtc *crtc =
6113 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6114 struct intel_crtc_state pipe_config = {
6115 .pixel_multiplier = 1,
6116 .dpll = *dpll,
6117 };
6118
6119 if (IS_CHERRYVIEW(dev)) {
6120 chv_update_pll(crtc, &pipe_config);
6121 chv_prepare_pll(crtc, &pipe_config);
6122 chv_enable_pll(crtc, &pipe_config);
6123 } else {
6124 vlv_update_pll(crtc, &pipe_config);
6125 vlv_prepare_pll(crtc, &pipe_config);
6126 vlv_enable_pll(crtc, &pipe_config);
6127 }
6128 }
6129
6130 /**
6131 * vlv_force_pll_off - forcibly disable just the PLL
6132 * @dev_priv: i915 private structure
6133 * @pipe: pipe PLL to disable
6134 *
6135 * Disable the PLL for @pipe. To be used in cases where we need
6136 * the PLL enabled even when @pipe is not going to be enabled.
6137 */
6138 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6139 {
6140 if (IS_CHERRYVIEW(dev))
6141 chv_disable_pll(to_i915(dev), pipe);
6142 else
6143 vlv_disable_pll(to_i915(dev), pipe);
6144 }
6145
6146 static void i9xx_update_pll(struct intel_crtc *crtc,
6147 struct intel_crtc_state *crtc_state,
6148 intel_clock_t *reduced_clock,
6149 int num_connectors)
6150 {
6151 struct drm_device *dev = crtc->base.dev;
6152 struct drm_i915_private *dev_priv = dev->dev_private;
6153 u32 dpll;
6154 bool is_sdvo;
6155 struct dpll *clock = &crtc_state->dpll;
6156
6157 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6158
6159 is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6160 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
6161
6162 dpll = DPLL_VGA_MODE_DIS;
6163
6164 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
6165 dpll |= DPLLB_MODE_LVDS;
6166 else
6167 dpll |= DPLLB_MODE_DAC_SERIAL;
6168
6169 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6170 dpll |= (crtc_state->pixel_multiplier - 1)
6171 << SDVO_MULTIPLIER_SHIFT_HIRES;
6172 }
6173
6174 if (is_sdvo)
6175 dpll |= DPLL_SDVO_HIGH_SPEED;
6176
6177 if (crtc_state->has_dp_encoder)
6178 dpll |= DPLL_SDVO_HIGH_SPEED;
6179
6180 /* compute bitmask from p1 value */
6181 if (IS_PINEVIEW(dev))
6182 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6183 else {
6184 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6185 if (IS_G4X(dev) && reduced_clock)
6186 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6187 }
6188 switch (clock->p2) {
6189 case 5:
6190 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6191 break;
6192 case 7:
6193 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6194 break;
6195 case 10:
6196 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6197 break;
6198 case 14:
6199 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6200 break;
6201 }
6202 if (INTEL_INFO(dev)->gen >= 4)
6203 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6204
6205 if (crtc_state->sdvo_tv_clock)
6206 dpll |= PLL_REF_INPUT_TVCLKINBC;
6207 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6208 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6209 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6210 else
6211 dpll |= PLL_REF_INPUT_DREFCLK;
6212
6213 dpll |= DPLL_VCO_ENABLE;
6214 crtc_state->dpll_hw_state.dpll = dpll;
6215
6216 if (INTEL_INFO(dev)->gen >= 4) {
6217 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6218 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6219 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6220 }
6221 }
6222
6223 static void i8xx_update_pll(struct intel_crtc *crtc,
6224 struct intel_crtc_state *crtc_state,
6225 intel_clock_t *reduced_clock,
6226 int num_connectors)
6227 {
6228 struct drm_device *dev = crtc->base.dev;
6229 struct drm_i915_private *dev_priv = dev->dev_private;
6230 u32 dpll;
6231 struct dpll *clock = &crtc_state->dpll;
6232
6233 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6234
6235 dpll = DPLL_VGA_MODE_DIS;
6236
6237 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
6238 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6239 } else {
6240 if (clock->p1 == 2)
6241 dpll |= PLL_P1_DIVIDE_BY_TWO;
6242 else
6243 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6244 if (clock->p2 == 4)
6245 dpll |= PLL_P2_DIVIDE_BY_4;
6246 }
6247
6248 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
6249 dpll |= DPLL_DVO_2X_MODE;
6250
6251 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6252 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6253 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6254 else
6255 dpll |= PLL_REF_INPUT_DREFCLK;
6256
6257 dpll |= DPLL_VCO_ENABLE;
6258 crtc_state->dpll_hw_state.dpll = dpll;
6259 }
6260
6261 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6262 {
6263 struct drm_device *dev = intel_crtc->base.dev;
6264 struct drm_i915_private *dev_priv = dev->dev_private;
6265 enum pipe pipe = intel_crtc->pipe;
6266 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6267 struct drm_display_mode *adjusted_mode =
6268 &intel_crtc->config->base.adjusted_mode;
6269 uint32_t crtc_vtotal, crtc_vblank_end;
6270 int vsyncshift = 0;
6271
6272 /* We need to be careful not to changed the adjusted mode, for otherwise
6273 * the hw state checker will get angry at the mismatch. */
6274 crtc_vtotal = adjusted_mode->crtc_vtotal;
6275 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6276
6277 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6278 /* the chip adds 2 halflines automatically */
6279 crtc_vtotal -= 1;
6280 crtc_vblank_end -= 1;
6281
6282 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6283 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6284 else
6285 vsyncshift = adjusted_mode->crtc_hsync_start -
6286 adjusted_mode->crtc_htotal / 2;
6287 if (vsyncshift < 0)
6288 vsyncshift += adjusted_mode->crtc_htotal;
6289 }
6290
6291 if (INTEL_INFO(dev)->gen > 3)
6292 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6293
6294 I915_WRITE(HTOTAL(cpu_transcoder),
6295 (adjusted_mode->crtc_hdisplay - 1) |
6296 ((adjusted_mode->crtc_htotal - 1) << 16));
6297 I915_WRITE(HBLANK(cpu_transcoder),
6298 (adjusted_mode->crtc_hblank_start - 1) |
6299 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6300 I915_WRITE(HSYNC(cpu_transcoder),
6301 (adjusted_mode->crtc_hsync_start - 1) |
6302 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6303
6304 I915_WRITE(VTOTAL(cpu_transcoder),
6305 (adjusted_mode->crtc_vdisplay - 1) |
6306 ((crtc_vtotal - 1) << 16));
6307 I915_WRITE(VBLANK(cpu_transcoder),
6308 (adjusted_mode->crtc_vblank_start - 1) |
6309 ((crtc_vblank_end - 1) << 16));
6310 I915_WRITE(VSYNC(cpu_transcoder),
6311 (adjusted_mode->crtc_vsync_start - 1) |
6312 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6313
6314 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6315 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6316 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6317 * bits. */
6318 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6319 (pipe == PIPE_B || pipe == PIPE_C))
6320 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6321
6322 /* pipesrc controls the size that is scaled from, which should
6323 * always be the user's requested size.
6324 */
6325 I915_WRITE(PIPESRC(pipe),
6326 ((intel_crtc->config->pipe_src_w - 1) << 16) |
6327 (intel_crtc->config->pipe_src_h - 1));
6328 }
6329
6330 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6331 struct intel_crtc_state *pipe_config)
6332 {
6333 struct drm_device *dev = crtc->base.dev;
6334 struct drm_i915_private *dev_priv = dev->dev_private;
6335 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6336 uint32_t tmp;
6337
6338 tmp = I915_READ(HTOTAL(cpu_transcoder));
6339 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6340 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6341 tmp = I915_READ(HBLANK(cpu_transcoder));
6342 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6343 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6344 tmp = I915_READ(HSYNC(cpu_transcoder));
6345 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6346 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6347
6348 tmp = I915_READ(VTOTAL(cpu_transcoder));
6349 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6350 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6351 tmp = I915_READ(VBLANK(cpu_transcoder));
6352 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6353 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6354 tmp = I915_READ(VSYNC(cpu_transcoder));
6355 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6356 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6357
6358 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6359 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6360 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6361 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
6362 }
6363
6364 tmp = I915_READ(PIPESRC(crtc->pipe));
6365 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6366 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6367
6368 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
6369 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
6370 }
6371
6372 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6373 struct intel_crtc_state *pipe_config)
6374 {
6375 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
6376 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
6377 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
6378 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
6379
6380 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
6381 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
6382 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
6383 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
6384
6385 mode->flags = pipe_config->base.adjusted_mode.flags;
6386
6387 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
6388 mode->flags |= pipe_config->base.adjusted_mode.flags;
6389 }
6390
6391 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6392 {
6393 struct drm_device *dev = intel_crtc->base.dev;
6394 struct drm_i915_private *dev_priv = dev->dev_private;
6395 uint32_t pipeconf;
6396
6397 pipeconf = 0;
6398
6399 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6400 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6401 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6402
6403 if (intel_crtc->config->double_wide)
6404 pipeconf |= PIPECONF_DOUBLE_WIDE;
6405
6406 /* only g4x and later have fancy bpc/dither controls */
6407 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6408 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6409 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
6410 pipeconf |= PIPECONF_DITHER_EN |
6411 PIPECONF_DITHER_TYPE_SP;
6412
6413 switch (intel_crtc->config->pipe_bpp) {
6414 case 18:
6415 pipeconf |= PIPECONF_6BPC;
6416 break;
6417 case 24:
6418 pipeconf |= PIPECONF_8BPC;
6419 break;
6420 case 30:
6421 pipeconf |= PIPECONF_10BPC;
6422 break;
6423 default:
6424 /* Case prevented by intel_choose_pipe_bpp_dither. */
6425 BUG();
6426 }
6427 }
6428
6429 if (HAS_PIPE_CXSR(dev)) {
6430 if (intel_crtc->lowfreq_avail) {
6431 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6432 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6433 } else {
6434 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6435 }
6436 }
6437
6438 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6439 if (INTEL_INFO(dev)->gen < 4 ||
6440 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6441 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6442 else
6443 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6444 } else
6445 pipeconf |= PIPECONF_PROGRESSIVE;
6446
6447 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
6448 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6449
6450 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6451 POSTING_READ(PIPECONF(intel_crtc->pipe));
6452 }
6453
6454 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
6455 struct intel_crtc_state *crtc_state)
6456 {
6457 struct drm_device *dev = crtc->base.dev;
6458 struct drm_i915_private *dev_priv = dev->dev_private;
6459 int refclk, num_connectors = 0;
6460 intel_clock_t clock, reduced_clock;
6461 bool ok, has_reduced_clock = false;
6462 bool is_lvds = false, is_dsi = false;
6463 struct intel_encoder *encoder;
6464 const intel_limit_t *limit;
6465
6466 for_each_intel_encoder(dev, encoder) {
6467 if (encoder->new_crtc != crtc)
6468 continue;
6469
6470 switch (encoder->type) {
6471 case INTEL_OUTPUT_LVDS:
6472 is_lvds = true;
6473 break;
6474 case INTEL_OUTPUT_DSI:
6475 is_dsi = true;
6476 break;
6477 default:
6478 break;
6479 }
6480
6481 num_connectors++;
6482 }
6483
6484 if (is_dsi)
6485 return 0;
6486
6487 if (!crtc_state->clock_set) {
6488 refclk = i9xx_get_refclk(crtc, num_connectors);
6489
6490 /*
6491 * Returns a set of divisors for the desired target clock with
6492 * the given refclk, or FALSE. The returned values represent
6493 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6494 * 2) / p1 / p2.
6495 */
6496 limit = intel_limit(crtc, refclk);
6497 ok = dev_priv->display.find_dpll(limit, crtc,
6498 crtc_state->port_clock,
6499 refclk, NULL, &clock);
6500 if (!ok) {
6501 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6502 return -EINVAL;
6503 }
6504
6505 if (is_lvds && dev_priv->lvds_downclock_avail) {
6506 /*
6507 * Ensure we match the reduced clock's P to the target
6508 * clock. If the clocks don't match, we can't switch
6509 * the display clock by using the FP0/FP1. In such case
6510 * we will disable the LVDS downclock feature.
6511 */
6512 has_reduced_clock =
6513 dev_priv->display.find_dpll(limit, crtc,
6514 dev_priv->lvds_downclock,
6515 refclk, &clock,
6516 &reduced_clock);
6517 }
6518 /* Compat-code for transition, will disappear. */
6519 crtc_state->dpll.n = clock.n;
6520 crtc_state->dpll.m1 = clock.m1;
6521 crtc_state->dpll.m2 = clock.m2;
6522 crtc_state->dpll.p1 = clock.p1;
6523 crtc_state->dpll.p2 = clock.p2;
6524 }
6525
6526 if (IS_GEN2(dev)) {
6527 i8xx_update_pll(crtc, crtc_state,
6528 has_reduced_clock ? &reduced_clock : NULL,
6529 num_connectors);
6530 } else if (IS_CHERRYVIEW(dev)) {
6531 chv_update_pll(crtc, crtc_state);
6532 } else if (IS_VALLEYVIEW(dev)) {
6533 vlv_update_pll(crtc, crtc_state);
6534 } else {
6535 i9xx_update_pll(crtc, crtc_state,
6536 has_reduced_clock ? &reduced_clock : NULL,
6537 num_connectors);
6538 }
6539
6540 return 0;
6541 }
6542
6543 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6544 struct intel_crtc_state *pipe_config)
6545 {
6546 struct drm_device *dev = crtc->base.dev;
6547 struct drm_i915_private *dev_priv = dev->dev_private;
6548 uint32_t tmp;
6549
6550 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6551 return;
6552
6553 tmp = I915_READ(PFIT_CONTROL);
6554 if (!(tmp & PFIT_ENABLE))
6555 return;
6556
6557 /* Check whether the pfit is attached to our pipe. */
6558 if (INTEL_INFO(dev)->gen < 4) {
6559 if (crtc->pipe != PIPE_B)
6560 return;
6561 } else {
6562 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6563 return;
6564 }
6565
6566 pipe_config->gmch_pfit.control = tmp;
6567 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6568 if (INTEL_INFO(dev)->gen < 5)
6569 pipe_config->gmch_pfit.lvds_border_bits =
6570 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6571 }
6572
6573 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6574 struct intel_crtc_state *pipe_config)
6575 {
6576 struct drm_device *dev = crtc->base.dev;
6577 struct drm_i915_private *dev_priv = dev->dev_private;
6578 int pipe = pipe_config->cpu_transcoder;
6579 intel_clock_t clock;
6580 u32 mdiv;
6581 int refclk = 100000;
6582
6583 /* In case of MIPI DPLL will not even be used */
6584 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6585 return;
6586
6587 mutex_lock(&dev_priv->dpio_lock);
6588 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6589 mutex_unlock(&dev_priv->dpio_lock);
6590
6591 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6592 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6593 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6594 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6595 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6596
6597 vlv_clock(refclk, &clock);
6598
6599 /* clock.dot is the fast clock */
6600 pipe_config->port_clock = clock.dot / 5;
6601 }
6602
6603 static void
6604 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
6605 struct intel_initial_plane_config *plane_config)
6606 {
6607 struct drm_device *dev = crtc->base.dev;
6608 struct drm_i915_private *dev_priv = dev->dev_private;
6609 u32 val, base, offset;
6610 int pipe = crtc->pipe, plane = crtc->plane;
6611 int fourcc, pixel_format;
6612 int aligned_height;
6613 struct drm_framebuffer *fb;
6614 struct intel_framebuffer *intel_fb;
6615
6616 val = I915_READ(DSPCNTR(plane));
6617 if (!(val & DISPLAY_PLANE_ENABLE))
6618 return;
6619
6620 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6621 if (!intel_fb) {
6622 DRM_DEBUG_KMS("failed to alloc fb\n");
6623 return;
6624 }
6625
6626 fb = &intel_fb->base;
6627
6628 if (INTEL_INFO(dev)->gen >= 4)
6629 if (val & DISPPLANE_TILED)
6630 plane_config->tiling = I915_TILING_X;
6631
6632 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6633 fourcc = i9xx_format_to_fourcc(pixel_format);
6634 fb->pixel_format = fourcc;
6635 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
6636
6637 if (INTEL_INFO(dev)->gen >= 4) {
6638 if (plane_config->tiling)
6639 offset = I915_READ(DSPTILEOFF(plane));
6640 else
6641 offset = I915_READ(DSPLINOFF(plane));
6642 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6643 } else {
6644 base = I915_READ(DSPADDR(plane));
6645 }
6646 plane_config->base = base;
6647
6648 val = I915_READ(PIPESRC(pipe));
6649 fb->width = ((val >> 16) & 0xfff) + 1;
6650 fb->height = ((val >> 0) & 0xfff) + 1;
6651
6652 val = I915_READ(DSPSTRIDE(pipe));
6653 fb->pitches[0] = val & 0xffffffc0;
6654
6655 aligned_height = intel_fb_align_height(dev, fb->height,
6656 plane_config->tiling);
6657
6658 plane_config->size = fb->pitches[0] * aligned_height;
6659
6660 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6661 pipe_name(pipe), plane, fb->width, fb->height,
6662 fb->bits_per_pixel, base, fb->pitches[0],
6663 plane_config->size);
6664
6665 crtc->base.primary->fb = fb;
6666 update_state_fb(crtc->base.primary);
6667 }
6668
6669 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6670 struct intel_crtc_state *pipe_config)
6671 {
6672 struct drm_device *dev = crtc->base.dev;
6673 struct drm_i915_private *dev_priv = dev->dev_private;
6674 int pipe = pipe_config->cpu_transcoder;
6675 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6676 intel_clock_t clock;
6677 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6678 int refclk = 100000;
6679
6680 mutex_lock(&dev_priv->dpio_lock);
6681 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6682 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6683 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6684 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6685 mutex_unlock(&dev_priv->dpio_lock);
6686
6687 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6688 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6689 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6690 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6691 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6692
6693 chv_clock(refclk, &clock);
6694
6695 /* clock.dot is the fast clock */
6696 pipe_config->port_clock = clock.dot / 5;
6697 }
6698
6699 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6700 struct intel_crtc_state *pipe_config)
6701 {
6702 struct drm_device *dev = crtc->base.dev;
6703 struct drm_i915_private *dev_priv = dev->dev_private;
6704 uint32_t tmp;
6705
6706 if (!intel_display_power_is_enabled(dev_priv,
6707 POWER_DOMAIN_PIPE(crtc->pipe)))
6708 return false;
6709
6710 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6711 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6712
6713 tmp = I915_READ(PIPECONF(crtc->pipe));
6714 if (!(tmp & PIPECONF_ENABLE))
6715 return false;
6716
6717 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6718 switch (tmp & PIPECONF_BPC_MASK) {
6719 case PIPECONF_6BPC:
6720 pipe_config->pipe_bpp = 18;
6721 break;
6722 case PIPECONF_8BPC:
6723 pipe_config->pipe_bpp = 24;
6724 break;
6725 case PIPECONF_10BPC:
6726 pipe_config->pipe_bpp = 30;
6727 break;
6728 default:
6729 break;
6730 }
6731 }
6732
6733 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6734 pipe_config->limited_color_range = true;
6735
6736 if (INTEL_INFO(dev)->gen < 4)
6737 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6738
6739 intel_get_pipe_timings(crtc, pipe_config);
6740
6741 i9xx_get_pfit_config(crtc, pipe_config);
6742
6743 if (INTEL_INFO(dev)->gen >= 4) {
6744 tmp = I915_READ(DPLL_MD(crtc->pipe));
6745 pipe_config->pixel_multiplier =
6746 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6747 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6748 pipe_config->dpll_hw_state.dpll_md = tmp;
6749 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6750 tmp = I915_READ(DPLL(crtc->pipe));
6751 pipe_config->pixel_multiplier =
6752 ((tmp & SDVO_MULTIPLIER_MASK)
6753 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6754 } else {
6755 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6756 * port and will be fixed up in the encoder->get_config
6757 * function. */
6758 pipe_config->pixel_multiplier = 1;
6759 }
6760 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6761 if (!IS_VALLEYVIEW(dev)) {
6762 /*
6763 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6764 * on 830. Filter it out here so that we don't
6765 * report errors due to that.
6766 */
6767 if (IS_I830(dev))
6768 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6769
6770 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6771 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6772 } else {
6773 /* Mask out read-only status bits. */
6774 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6775 DPLL_PORTC_READY_MASK |
6776 DPLL_PORTB_READY_MASK);
6777 }
6778
6779 if (IS_CHERRYVIEW(dev))
6780 chv_crtc_clock_get(crtc, pipe_config);
6781 else if (IS_VALLEYVIEW(dev))
6782 vlv_crtc_clock_get(crtc, pipe_config);
6783 else
6784 i9xx_crtc_clock_get(crtc, pipe_config);
6785
6786 return true;
6787 }
6788
6789 static void ironlake_init_pch_refclk(struct drm_device *dev)
6790 {
6791 struct drm_i915_private *dev_priv = dev->dev_private;
6792 struct intel_encoder *encoder;
6793 u32 val, final;
6794 bool has_lvds = false;
6795 bool has_cpu_edp = false;
6796 bool has_panel = false;
6797 bool has_ck505 = false;
6798 bool can_ssc = false;
6799
6800 /* We need to take the global config into account */
6801 for_each_intel_encoder(dev, encoder) {
6802 switch (encoder->type) {
6803 case INTEL_OUTPUT_LVDS:
6804 has_panel = true;
6805 has_lvds = true;
6806 break;
6807 case INTEL_OUTPUT_EDP:
6808 has_panel = true;
6809 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6810 has_cpu_edp = true;
6811 break;
6812 default:
6813 break;
6814 }
6815 }
6816
6817 if (HAS_PCH_IBX(dev)) {
6818 has_ck505 = dev_priv->vbt.display_clock_mode;
6819 can_ssc = has_ck505;
6820 } else {
6821 has_ck505 = false;
6822 can_ssc = true;
6823 }
6824
6825 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6826 has_panel, has_lvds, has_ck505);
6827
6828 /* Ironlake: try to setup display ref clock before DPLL
6829 * enabling. This is only under driver's control after
6830 * PCH B stepping, previous chipset stepping should be
6831 * ignoring this setting.
6832 */
6833 val = I915_READ(PCH_DREF_CONTROL);
6834
6835 /* As we must carefully and slowly disable/enable each source in turn,
6836 * compute the final state we want first and check if we need to
6837 * make any changes at all.
6838 */
6839 final = val;
6840 final &= ~DREF_NONSPREAD_SOURCE_MASK;
6841 if (has_ck505)
6842 final |= DREF_NONSPREAD_CK505_ENABLE;
6843 else
6844 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6845
6846 final &= ~DREF_SSC_SOURCE_MASK;
6847 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6848 final &= ~DREF_SSC1_ENABLE;
6849
6850 if (has_panel) {
6851 final |= DREF_SSC_SOURCE_ENABLE;
6852
6853 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6854 final |= DREF_SSC1_ENABLE;
6855
6856 if (has_cpu_edp) {
6857 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6858 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6859 else
6860 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6861 } else
6862 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6863 } else {
6864 final |= DREF_SSC_SOURCE_DISABLE;
6865 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6866 }
6867
6868 if (final == val)
6869 return;
6870
6871 /* Always enable nonspread source */
6872 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6873
6874 if (has_ck505)
6875 val |= DREF_NONSPREAD_CK505_ENABLE;
6876 else
6877 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6878
6879 if (has_panel) {
6880 val &= ~DREF_SSC_SOURCE_MASK;
6881 val |= DREF_SSC_SOURCE_ENABLE;
6882
6883 /* SSC must be turned on before enabling the CPU output */
6884 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6885 DRM_DEBUG_KMS("Using SSC on panel\n");
6886 val |= DREF_SSC1_ENABLE;
6887 } else
6888 val &= ~DREF_SSC1_ENABLE;
6889
6890 /* Get SSC going before enabling the outputs */
6891 I915_WRITE(PCH_DREF_CONTROL, val);
6892 POSTING_READ(PCH_DREF_CONTROL);
6893 udelay(200);
6894
6895 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6896
6897 /* Enable CPU source on CPU attached eDP */
6898 if (has_cpu_edp) {
6899 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6900 DRM_DEBUG_KMS("Using SSC on eDP\n");
6901 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6902 } else
6903 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6904 } else
6905 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6906
6907 I915_WRITE(PCH_DREF_CONTROL, val);
6908 POSTING_READ(PCH_DREF_CONTROL);
6909 udelay(200);
6910 } else {
6911 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6912
6913 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6914
6915 /* Turn off CPU output */
6916 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6917
6918 I915_WRITE(PCH_DREF_CONTROL, val);
6919 POSTING_READ(PCH_DREF_CONTROL);
6920 udelay(200);
6921
6922 /* Turn off the SSC source */
6923 val &= ~DREF_SSC_SOURCE_MASK;
6924 val |= DREF_SSC_SOURCE_DISABLE;
6925
6926 /* Turn off SSC1 */
6927 val &= ~DREF_SSC1_ENABLE;
6928
6929 I915_WRITE(PCH_DREF_CONTROL, val);
6930 POSTING_READ(PCH_DREF_CONTROL);
6931 udelay(200);
6932 }
6933
6934 BUG_ON(val != final);
6935 }
6936
6937 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6938 {
6939 uint32_t tmp;
6940
6941 tmp = I915_READ(SOUTH_CHICKEN2);
6942 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6943 I915_WRITE(SOUTH_CHICKEN2, tmp);
6944
6945 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6946 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6947 DRM_ERROR("FDI mPHY reset assert timeout\n");
6948
6949 tmp = I915_READ(SOUTH_CHICKEN2);
6950 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6951 I915_WRITE(SOUTH_CHICKEN2, tmp);
6952
6953 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6954 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6955 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6956 }
6957
6958 /* WaMPhyProgramming:hsw */
6959 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6960 {
6961 uint32_t tmp;
6962
6963 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6964 tmp &= ~(0xFF << 24);
6965 tmp |= (0x12 << 24);
6966 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6967
6968 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6969 tmp |= (1 << 11);
6970 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6971
6972 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6973 tmp |= (1 << 11);
6974 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6975
6976 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6977 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6978 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6979
6980 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6981 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6982 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6983
6984 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6985 tmp &= ~(7 << 13);
6986 tmp |= (5 << 13);
6987 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6988
6989 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6990 tmp &= ~(7 << 13);
6991 tmp |= (5 << 13);
6992 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6993
6994 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6995 tmp &= ~0xFF;
6996 tmp |= 0x1C;
6997 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6998
6999 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7000 tmp &= ~0xFF;
7001 tmp |= 0x1C;
7002 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7003
7004 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7005 tmp &= ~(0xFF << 16);
7006 tmp |= (0x1C << 16);
7007 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7008
7009 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7010 tmp &= ~(0xFF << 16);
7011 tmp |= (0x1C << 16);
7012 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7013
7014 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7015 tmp |= (1 << 27);
7016 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7017
7018 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7019 tmp |= (1 << 27);
7020 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7021
7022 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7023 tmp &= ~(0xF << 28);
7024 tmp |= (4 << 28);
7025 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7026
7027 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7028 tmp &= ~(0xF << 28);
7029 tmp |= (4 << 28);
7030 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7031 }
7032
7033 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7034 * Programming" based on the parameters passed:
7035 * - Sequence to enable CLKOUT_DP
7036 * - Sequence to enable CLKOUT_DP without spread
7037 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7038 */
7039 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
7040 bool with_fdi)
7041 {
7042 struct drm_i915_private *dev_priv = dev->dev_private;
7043 uint32_t reg, tmp;
7044
7045 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7046 with_spread = true;
7047 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
7048 with_fdi, "LP PCH doesn't have FDI\n"))
7049 with_fdi = false;
7050
7051 mutex_lock(&dev_priv->dpio_lock);
7052
7053 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7054 tmp &= ~SBI_SSCCTL_DISABLE;
7055 tmp |= SBI_SSCCTL_PATHALT;
7056 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7057
7058 udelay(24);
7059
7060 if (with_spread) {
7061 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7062 tmp &= ~SBI_SSCCTL_PATHALT;
7063 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7064
7065 if (with_fdi) {
7066 lpt_reset_fdi_mphy(dev_priv);
7067 lpt_program_fdi_mphy(dev_priv);
7068 }
7069 }
7070
7071 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7072 SBI_GEN0 : SBI_DBUFF0;
7073 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7074 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7075 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7076
7077 mutex_unlock(&dev_priv->dpio_lock);
7078 }
7079
7080 /* Sequence to disable CLKOUT_DP */
7081 static void lpt_disable_clkout_dp(struct drm_device *dev)
7082 {
7083 struct drm_i915_private *dev_priv = dev->dev_private;
7084 uint32_t reg, tmp;
7085
7086 mutex_lock(&dev_priv->dpio_lock);
7087
7088 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7089 SBI_GEN0 : SBI_DBUFF0;
7090 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7091 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7092 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7093
7094 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7095 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7096 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7097 tmp |= SBI_SSCCTL_PATHALT;
7098 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7099 udelay(32);
7100 }
7101 tmp |= SBI_SSCCTL_DISABLE;
7102 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7103 }
7104
7105 mutex_unlock(&dev_priv->dpio_lock);
7106 }
7107
7108 static void lpt_init_pch_refclk(struct drm_device *dev)
7109 {
7110 struct intel_encoder *encoder;
7111 bool has_vga = false;
7112
7113 for_each_intel_encoder(dev, encoder) {
7114 switch (encoder->type) {
7115 case INTEL_OUTPUT_ANALOG:
7116 has_vga = true;
7117 break;
7118 default:
7119 break;
7120 }
7121 }
7122
7123 if (has_vga)
7124 lpt_enable_clkout_dp(dev, true, true);
7125 else
7126 lpt_disable_clkout_dp(dev);
7127 }
7128
7129 /*
7130 * Initialize reference clocks when the driver loads
7131 */
7132 void intel_init_pch_refclk(struct drm_device *dev)
7133 {
7134 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7135 ironlake_init_pch_refclk(dev);
7136 else if (HAS_PCH_LPT(dev))
7137 lpt_init_pch_refclk(dev);
7138 }
7139
7140 static int ironlake_get_refclk(struct drm_crtc *crtc)
7141 {
7142 struct drm_device *dev = crtc->dev;
7143 struct drm_i915_private *dev_priv = dev->dev_private;
7144 struct intel_encoder *encoder;
7145 int num_connectors = 0;
7146 bool is_lvds = false;
7147
7148 for_each_intel_encoder(dev, encoder) {
7149 if (encoder->new_crtc != to_intel_crtc(crtc))
7150 continue;
7151
7152 switch (encoder->type) {
7153 case INTEL_OUTPUT_LVDS:
7154 is_lvds = true;
7155 break;
7156 default:
7157 break;
7158 }
7159 num_connectors++;
7160 }
7161
7162 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7163 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7164 dev_priv->vbt.lvds_ssc_freq);
7165 return dev_priv->vbt.lvds_ssc_freq;
7166 }
7167
7168 return 120000;
7169 }
7170
7171 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7172 {
7173 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7174 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7175 int pipe = intel_crtc->pipe;
7176 uint32_t val;
7177
7178 val = 0;
7179
7180 switch (intel_crtc->config->pipe_bpp) {
7181 case 18:
7182 val |= PIPECONF_6BPC;
7183 break;
7184 case 24:
7185 val |= PIPECONF_8BPC;
7186 break;
7187 case 30:
7188 val |= PIPECONF_10BPC;
7189 break;
7190 case 36:
7191 val |= PIPECONF_12BPC;
7192 break;
7193 default:
7194 /* Case prevented by intel_choose_pipe_bpp_dither. */
7195 BUG();
7196 }
7197
7198 if (intel_crtc->config->dither)
7199 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7200
7201 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7202 val |= PIPECONF_INTERLACED_ILK;
7203 else
7204 val |= PIPECONF_PROGRESSIVE;
7205
7206 if (intel_crtc->config->limited_color_range)
7207 val |= PIPECONF_COLOR_RANGE_SELECT;
7208
7209 I915_WRITE(PIPECONF(pipe), val);
7210 POSTING_READ(PIPECONF(pipe));
7211 }
7212
7213 /*
7214 * Set up the pipe CSC unit.
7215 *
7216 * Currently only full range RGB to limited range RGB conversion
7217 * is supported, but eventually this should handle various
7218 * RGB<->YCbCr scenarios as well.
7219 */
7220 static void intel_set_pipe_csc(struct drm_crtc *crtc)
7221 {
7222 struct drm_device *dev = crtc->dev;
7223 struct drm_i915_private *dev_priv = dev->dev_private;
7224 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7225 int pipe = intel_crtc->pipe;
7226 uint16_t coeff = 0x7800; /* 1.0 */
7227
7228 /*
7229 * TODO: Check what kind of values actually come out of the pipe
7230 * with these coeff/postoff values and adjust to get the best
7231 * accuracy. Perhaps we even need to take the bpc value into
7232 * consideration.
7233 */
7234
7235 if (intel_crtc->config->limited_color_range)
7236 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7237
7238 /*
7239 * GY/GU and RY/RU should be the other way around according
7240 * to BSpec, but reality doesn't agree. Just set them up in
7241 * a way that results in the correct picture.
7242 */
7243 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7244 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7245
7246 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7247 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7248
7249 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7250 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7251
7252 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7253 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7254 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7255
7256 if (INTEL_INFO(dev)->gen > 6) {
7257 uint16_t postoff = 0;
7258
7259 if (intel_crtc->config->limited_color_range)
7260 postoff = (16 * (1 << 12) / 255) & 0x1fff;
7261
7262 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7263 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7264 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7265
7266 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7267 } else {
7268 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7269
7270 if (intel_crtc->config->limited_color_range)
7271 mode |= CSC_BLACK_SCREEN_OFFSET;
7272
7273 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7274 }
7275 }
7276
7277 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7278 {
7279 struct drm_device *dev = crtc->dev;
7280 struct drm_i915_private *dev_priv = dev->dev_private;
7281 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7282 enum pipe pipe = intel_crtc->pipe;
7283 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7284 uint32_t val;
7285
7286 val = 0;
7287
7288 if (IS_HASWELL(dev) && intel_crtc->config->dither)
7289 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7290
7291 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7292 val |= PIPECONF_INTERLACED_ILK;
7293 else
7294 val |= PIPECONF_PROGRESSIVE;
7295
7296 I915_WRITE(PIPECONF(cpu_transcoder), val);
7297 POSTING_READ(PIPECONF(cpu_transcoder));
7298
7299 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7300 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7301
7302 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7303 val = 0;
7304
7305 switch (intel_crtc->config->pipe_bpp) {
7306 case 18:
7307 val |= PIPEMISC_DITHER_6_BPC;
7308 break;
7309 case 24:
7310 val |= PIPEMISC_DITHER_8_BPC;
7311 break;
7312 case 30:
7313 val |= PIPEMISC_DITHER_10_BPC;
7314 break;
7315 case 36:
7316 val |= PIPEMISC_DITHER_12_BPC;
7317 break;
7318 default:
7319 /* Case prevented by pipe_config_set_bpp. */
7320 BUG();
7321 }
7322
7323 if (intel_crtc->config->dither)
7324 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7325
7326 I915_WRITE(PIPEMISC(pipe), val);
7327 }
7328 }
7329
7330 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7331 struct intel_crtc_state *crtc_state,
7332 intel_clock_t *clock,
7333 bool *has_reduced_clock,
7334 intel_clock_t *reduced_clock)
7335 {
7336 struct drm_device *dev = crtc->dev;
7337 struct drm_i915_private *dev_priv = dev->dev_private;
7338 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7339 int refclk;
7340 const intel_limit_t *limit;
7341 bool ret, is_lvds = false;
7342
7343 is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
7344
7345 refclk = ironlake_get_refclk(crtc);
7346
7347 /*
7348 * Returns a set of divisors for the desired target clock with the given
7349 * refclk, or FALSE. The returned values represent the clock equation:
7350 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7351 */
7352 limit = intel_limit(intel_crtc, refclk);
7353 ret = dev_priv->display.find_dpll(limit, intel_crtc,
7354 crtc_state->port_clock,
7355 refclk, NULL, clock);
7356 if (!ret)
7357 return false;
7358
7359 if (is_lvds && dev_priv->lvds_downclock_avail) {
7360 /*
7361 * Ensure we match the reduced clock's P to the target clock.
7362 * If the clocks don't match, we can't switch the display clock
7363 * by using the FP0/FP1. In such case we will disable the LVDS
7364 * downclock feature.
7365 */
7366 *has_reduced_clock =
7367 dev_priv->display.find_dpll(limit, intel_crtc,
7368 dev_priv->lvds_downclock,
7369 refclk, clock,
7370 reduced_clock);
7371 }
7372
7373 return true;
7374 }
7375
7376 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7377 {
7378 /*
7379 * Account for spread spectrum to avoid
7380 * oversubscribing the link. Max center spread
7381 * is 2.5%; use 5% for safety's sake.
7382 */
7383 u32 bps = target_clock * bpp * 21 / 20;
7384 return DIV_ROUND_UP(bps, link_bw * 8);
7385 }
7386
7387 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7388 {
7389 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7390 }
7391
7392 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7393 struct intel_crtc_state *crtc_state,
7394 u32 *fp,
7395 intel_clock_t *reduced_clock, u32 *fp2)
7396 {
7397 struct drm_crtc *crtc = &intel_crtc->base;
7398 struct drm_device *dev = crtc->dev;
7399 struct drm_i915_private *dev_priv = dev->dev_private;
7400 struct intel_encoder *intel_encoder;
7401 uint32_t dpll;
7402 int factor, num_connectors = 0;
7403 bool is_lvds = false, is_sdvo = false;
7404
7405 for_each_intel_encoder(dev, intel_encoder) {
7406 if (intel_encoder->new_crtc != to_intel_crtc(crtc))
7407 continue;
7408
7409 switch (intel_encoder->type) {
7410 case INTEL_OUTPUT_LVDS:
7411 is_lvds = true;
7412 break;
7413 case INTEL_OUTPUT_SDVO:
7414 case INTEL_OUTPUT_HDMI:
7415 is_sdvo = true;
7416 break;
7417 default:
7418 break;
7419 }
7420
7421 num_connectors++;
7422 }
7423
7424 /* Enable autotuning of the PLL clock (if permissible) */
7425 factor = 21;
7426 if (is_lvds) {
7427 if ((intel_panel_use_ssc(dev_priv) &&
7428 dev_priv->vbt.lvds_ssc_freq == 100000) ||
7429 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7430 factor = 25;
7431 } else if (crtc_state->sdvo_tv_clock)
7432 factor = 20;
7433
7434 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7435 *fp |= FP_CB_TUNE;
7436
7437 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7438 *fp2 |= FP_CB_TUNE;
7439
7440 dpll = 0;
7441
7442 if (is_lvds)
7443 dpll |= DPLLB_MODE_LVDS;
7444 else
7445 dpll |= DPLLB_MODE_DAC_SERIAL;
7446
7447 dpll |= (crtc_state->pixel_multiplier - 1)
7448 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7449
7450 if (is_sdvo)
7451 dpll |= DPLL_SDVO_HIGH_SPEED;
7452 if (crtc_state->has_dp_encoder)
7453 dpll |= DPLL_SDVO_HIGH_SPEED;
7454
7455 /* compute bitmask from p1 value */
7456 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7457 /* also FPA1 */
7458 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7459
7460 switch (crtc_state->dpll.p2) {
7461 case 5:
7462 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7463 break;
7464 case 7:
7465 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7466 break;
7467 case 10:
7468 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7469 break;
7470 case 14:
7471 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7472 break;
7473 }
7474
7475 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7476 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7477 else
7478 dpll |= PLL_REF_INPUT_DREFCLK;
7479
7480 return dpll | DPLL_VCO_ENABLE;
7481 }
7482
7483 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
7484 struct intel_crtc_state *crtc_state)
7485 {
7486 struct drm_device *dev = crtc->base.dev;
7487 intel_clock_t clock, reduced_clock;
7488 u32 dpll = 0, fp = 0, fp2 = 0;
7489 bool ok, has_reduced_clock = false;
7490 bool is_lvds = false;
7491 struct intel_shared_dpll *pll;
7492
7493 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7494
7495 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7496 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7497
7498 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
7499 &has_reduced_clock, &reduced_clock);
7500 if (!ok && !crtc_state->clock_set) {
7501 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7502 return -EINVAL;
7503 }
7504 /* Compat-code for transition, will disappear. */
7505 if (!crtc_state->clock_set) {
7506 crtc_state->dpll.n = clock.n;
7507 crtc_state->dpll.m1 = clock.m1;
7508 crtc_state->dpll.m2 = clock.m2;
7509 crtc_state->dpll.p1 = clock.p1;
7510 crtc_state->dpll.p2 = clock.p2;
7511 }
7512
7513 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7514 if (crtc_state->has_pch_encoder) {
7515 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7516 if (has_reduced_clock)
7517 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7518
7519 dpll = ironlake_compute_dpll(crtc, crtc_state,
7520 &fp, &reduced_clock,
7521 has_reduced_clock ? &fp2 : NULL);
7522
7523 crtc_state->dpll_hw_state.dpll = dpll;
7524 crtc_state->dpll_hw_state.fp0 = fp;
7525 if (has_reduced_clock)
7526 crtc_state->dpll_hw_state.fp1 = fp2;
7527 else
7528 crtc_state->dpll_hw_state.fp1 = fp;
7529
7530 pll = intel_get_shared_dpll(crtc, crtc_state);
7531 if (pll == NULL) {
7532 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7533 pipe_name(crtc->pipe));
7534 return -EINVAL;
7535 }
7536 }
7537
7538 if (is_lvds && has_reduced_clock && i915.powersave)
7539 crtc->lowfreq_avail = true;
7540 else
7541 crtc->lowfreq_avail = false;
7542
7543 return 0;
7544 }
7545
7546 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7547 struct intel_link_m_n *m_n)
7548 {
7549 struct drm_device *dev = crtc->base.dev;
7550 struct drm_i915_private *dev_priv = dev->dev_private;
7551 enum pipe pipe = crtc->pipe;
7552
7553 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7554 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7555 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7556 & ~TU_SIZE_MASK;
7557 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7558 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7559 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7560 }
7561
7562 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7563 enum transcoder transcoder,
7564 struct intel_link_m_n *m_n,
7565 struct intel_link_m_n *m2_n2)
7566 {
7567 struct drm_device *dev = crtc->base.dev;
7568 struct drm_i915_private *dev_priv = dev->dev_private;
7569 enum pipe pipe = crtc->pipe;
7570
7571 if (INTEL_INFO(dev)->gen >= 5) {
7572 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7573 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7574 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7575 & ~TU_SIZE_MASK;
7576 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7577 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7578 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7579 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7580 * gen < 8) and if DRRS is supported (to make sure the
7581 * registers are not unnecessarily read).
7582 */
7583 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7584 crtc->config->has_drrs) {
7585 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7586 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7587 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7588 & ~TU_SIZE_MASK;
7589 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7590 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7591 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7592 }
7593 } else {
7594 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7595 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7596 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7597 & ~TU_SIZE_MASK;
7598 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7599 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7600 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7601 }
7602 }
7603
7604 void intel_dp_get_m_n(struct intel_crtc *crtc,
7605 struct intel_crtc_state *pipe_config)
7606 {
7607 if (pipe_config->has_pch_encoder)
7608 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7609 else
7610 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7611 &pipe_config->dp_m_n,
7612 &pipe_config->dp_m2_n2);
7613 }
7614
7615 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7616 struct intel_crtc_state *pipe_config)
7617 {
7618 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7619 &pipe_config->fdi_m_n, NULL);
7620 }
7621
7622 static void skylake_get_pfit_config(struct intel_crtc *crtc,
7623 struct intel_crtc_state *pipe_config)
7624 {
7625 struct drm_device *dev = crtc->base.dev;
7626 struct drm_i915_private *dev_priv = dev->dev_private;
7627 uint32_t tmp;
7628
7629 tmp = I915_READ(PS_CTL(crtc->pipe));
7630
7631 if (tmp & PS_ENABLE) {
7632 pipe_config->pch_pfit.enabled = true;
7633 pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe));
7634 pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe));
7635 }
7636 }
7637
7638 static void
7639 skylake_get_initial_plane_config(struct intel_crtc *crtc,
7640 struct intel_initial_plane_config *plane_config)
7641 {
7642 struct drm_device *dev = crtc->base.dev;
7643 struct drm_i915_private *dev_priv = dev->dev_private;
7644 u32 val, base, offset, stride_mult;
7645 int pipe = crtc->pipe;
7646 int fourcc, pixel_format;
7647 int aligned_height;
7648 struct drm_framebuffer *fb;
7649 struct intel_framebuffer *intel_fb;
7650
7651 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7652 if (!intel_fb) {
7653 DRM_DEBUG_KMS("failed to alloc fb\n");
7654 return;
7655 }
7656
7657 fb = &intel_fb->base;
7658
7659 val = I915_READ(PLANE_CTL(pipe, 0));
7660 if (!(val & PLANE_CTL_ENABLE))
7661 goto error;
7662
7663 if (val & PLANE_CTL_TILED_MASK)
7664 plane_config->tiling = I915_TILING_X;
7665
7666 pixel_format = val & PLANE_CTL_FORMAT_MASK;
7667 fourcc = skl_format_to_fourcc(pixel_format,
7668 val & PLANE_CTL_ORDER_RGBX,
7669 val & PLANE_CTL_ALPHA_MASK);
7670 fb->pixel_format = fourcc;
7671 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7672
7673 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
7674 plane_config->base = base;
7675
7676 offset = I915_READ(PLANE_OFFSET(pipe, 0));
7677
7678 val = I915_READ(PLANE_SIZE(pipe, 0));
7679 fb->height = ((val >> 16) & 0xfff) + 1;
7680 fb->width = ((val >> 0) & 0x1fff) + 1;
7681
7682 val = I915_READ(PLANE_STRIDE(pipe, 0));
7683 switch (plane_config->tiling) {
7684 case I915_TILING_NONE:
7685 stride_mult = 64;
7686 break;
7687 case I915_TILING_X:
7688 stride_mult = 512;
7689 break;
7690 default:
7691 MISSING_CASE(plane_config->tiling);
7692 goto error;
7693 }
7694 fb->pitches[0] = (val & 0x3ff) * stride_mult;
7695
7696 aligned_height = intel_fb_align_height(dev, fb->height,
7697 plane_config->tiling);
7698
7699 plane_config->size = fb->pitches[0] * aligned_height;
7700
7701 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7702 pipe_name(pipe), fb->width, fb->height,
7703 fb->bits_per_pixel, base, fb->pitches[0],
7704 plane_config->size);
7705
7706 crtc->base.primary->fb = fb;
7707 update_state_fb(crtc->base.primary);
7708 return;
7709
7710 error:
7711 kfree(fb);
7712 }
7713
7714 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7715 struct intel_crtc_state *pipe_config)
7716 {
7717 struct drm_device *dev = crtc->base.dev;
7718 struct drm_i915_private *dev_priv = dev->dev_private;
7719 uint32_t tmp;
7720
7721 tmp = I915_READ(PF_CTL(crtc->pipe));
7722
7723 if (tmp & PF_ENABLE) {
7724 pipe_config->pch_pfit.enabled = true;
7725 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7726 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7727
7728 /* We currently do not free assignements of panel fitters on
7729 * ivb/hsw (since we don't use the higher upscaling modes which
7730 * differentiates them) so just WARN about this case for now. */
7731 if (IS_GEN7(dev)) {
7732 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7733 PF_PIPE_SEL_IVB(crtc->pipe));
7734 }
7735 }
7736 }
7737
7738 static void
7739 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
7740 struct intel_initial_plane_config *plane_config)
7741 {
7742 struct drm_device *dev = crtc->base.dev;
7743 struct drm_i915_private *dev_priv = dev->dev_private;
7744 u32 val, base, offset;
7745 int pipe = crtc->pipe;
7746 int fourcc, pixel_format;
7747 int aligned_height;
7748 struct drm_framebuffer *fb;
7749 struct intel_framebuffer *intel_fb;
7750
7751 val = I915_READ(DSPCNTR(pipe));
7752 if (!(val & DISPLAY_PLANE_ENABLE))
7753 return;
7754
7755 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7756 if (!intel_fb) {
7757 DRM_DEBUG_KMS("failed to alloc fb\n");
7758 return;
7759 }
7760
7761 fb = &intel_fb->base;
7762
7763 if (INTEL_INFO(dev)->gen >= 4)
7764 if (val & DISPPLANE_TILED)
7765 plane_config->tiling = I915_TILING_X;
7766
7767 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7768 fourcc = i9xx_format_to_fourcc(pixel_format);
7769 fb->pixel_format = fourcc;
7770 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7771
7772 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
7773 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7774 offset = I915_READ(DSPOFFSET(pipe));
7775 } else {
7776 if (plane_config->tiling)
7777 offset = I915_READ(DSPTILEOFF(pipe));
7778 else
7779 offset = I915_READ(DSPLINOFF(pipe));
7780 }
7781 plane_config->base = base;
7782
7783 val = I915_READ(PIPESRC(pipe));
7784 fb->width = ((val >> 16) & 0xfff) + 1;
7785 fb->height = ((val >> 0) & 0xfff) + 1;
7786
7787 val = I915_READ(DSPSTRIDE(pipe));
7788 fb->pitches[0] = val & 0xffffffc0;
7789
7790 aligned_height = intel_fb_align_height(dev, fb->height,
7791 plane_config->tiling);
7792
7793 plane_config->size = fb->pitches[0] * aligned_height;
7794
7795 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7796 pipe_name(pipe), fb->width, fb->height,
7797 fb->bits_per_pixel, base, fb->pitches[0],
7798 plane_config->size);
7799
7800 crtc->base.primary->fb = fb;
7801 update_state_fb(crtc->base.primary);
7802 }
7803
7804 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7805 struct intel_crtc_state *pipe_config)
7806 {
7807 struct drm_device *dev = crtc->base.dev;
7808 struct drm_i915_private *dev_priv = dev->dev_private;
7809 uint32_t tmp;
7810
7811 if (!intel_display_power_is_enabled(dev_priv,
7812 POWER_DOMAIN_PIPE(crtc->pipe)))
7813 return false;
7814
7815 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7816 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7817
7818 tmp = I915_READ(PIPECONF(crtc->pipe));
7819 if (!(tmp & PIPECONF_ENABLE))
7820 return false;
7821
7822 switch (tmp & PIPECONF_BPC_MASK) {
7823 case PIPECONF_6BPC:
7824 pipe_config->pipe_bpp = 18;
7825 break;
7826 case PIPECONF_8BPC:
7827 pipe_config->pipe_bpp = 24;
7828 break;
7829 case PIPECONF_10BPC:
7830 pipe_config->pipe_bpp = 30;
7831 break;
7832 case PIPECONF_12BPC:
7833 pipe_config->pipe_bpp = 36;
7834 break;
7835 default:
7836 break;
7837 }
7838
7839 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7840 pipe_config->limited_color_range = true;
7841
7842 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7843 struct intel_shared_dpll *pll;
7844
7845 pipe_config->has_pch_encoder = true;
7846
7847 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7848 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7849 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7850
7851 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7852
7853 if (HAS_PCH_IBX(dev_priv->dev)) {
7854 pipe_config->shared_dpll =
7855 (enum intel_dpll_id) crtc->pipe;
7856 } else {
7857 tmp = I915_READ(PCH_DPLL_SEL);
7858 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7859 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7860 else
7861 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7862 }
7863
7864 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7865
7866 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7867 &pipe_config->dpll_hw_state));
7868
7869 tmp = pipe_config->dpll_hw_state.dpll;
7870 pipe_config->pixel_multiplier =
7871 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7872 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7873
7874 ironlake_pch_clock_get(crtc, pipe_config);
7875 } else {
7876 pipe_config->pixel_multiplier = 1;
7877 }
7878
7879 intel_get_pipe_timings(crtc, pipe_config);
7880
7881 ironlake_get_pfit_config(crtc, pipe_config);
7882
7883 return true;
7884 }
7885
7886 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7887 {
7888 struct drm_device *dev = dev_priv->dev;
7889 struct intel_crtc *crtc;
7890
7891 for_each_intel_crtc(dev, crtc)
7892 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
7893 pipe_name(crtc->pipe));
7894
7895 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7896 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7897 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7898 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7899 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7900 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7901 "CPU PWM1 enabled\n");
7902 if (IS_HASWELL(dev))
7903 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7904 "CPU PWM2 enabled\n");
7905 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7906 "PCH PWM1 enabled\n");
7907 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7908 "Utility pin enabled\n");
7909 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7910
7911 /*
7912 * In theory we can still leave IRQs enabled, as long as only the HPD
7913 * interrupts remain enabled. We used to check for that, but since it's
7914 * gen-specific and since we only disable LCPLL after we fully disable
7915 * the interrupts, the check below should be enough.
7916 */
7917 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7918 }
7919
7920 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7921 {
7922 struct drm_device *dev = dev_priv->dev;
7923
7924 if (IS_HASWELL(dev))
7925 return I915_READ(D_COMP_HSW);
7926 else
7927 return I915_READ(D_COMP_BDW);
7928 }
7929
7930 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7931 {
7932 struct drm_device *dev = dev_priv->dev;
7933
7934 if (IS_HASWELL(dev)) {
7935 mutex_lock(&dev_priv->rps.hw_lock);
7936 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7937 val))
7938 DRM_ERROR("Failed to write to D_COMP\n");
7939 mutex_unlock(&dev_priv->rps.hw_lock);
7940 } else {
7941 I915_WRITE(D_COMP_BDW, val);
7942 POSTING_READ(D_COMP_BDW);
7943 }
7944 }
7945
7946 /*
7947 * This function implements pieces of two sequences from BSpec:
7948 * - Sequence for display software to disable LCPLL
7949 * - Sequence for display software to allow package C8+
7950 * The steps implemented here are just the steps that actually touch the LCPLL
7951 * register. Callers should take care of disabling all the display engine
7952 * functions, doing the mode unset, fixing interrupts, etc.
7953 */
7954 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7955 bool switch_to_fclk, bool allow_power_down)
7956 {
7957 uint32_t val;
7958
7959 assert_can_disable_lcpll(dev_priv);
7960
7961 val = I915_READ(LCPLL_CTL);
7962
7963 if (switch_to_fclk) {
7964 val |= LCPLL_CD_SOURCE_FCLK;
7965 I915_WRITE(LCPLL_CTL, val);
7966
7967 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7968 LCPLL_CD_SOURCE_FCLK_DONE, 1))
7969 DRM_ERROR("Switching to FCLK failed\n");
7970
7971 val = I915_READ(LCPLL_CTL);
7972 }
7973
7974 val |= LCPLL_PLL_DISABLE;
7975 I915_WRITE(LCPLL_CTL, val);
7976 POSTING_READ(LCPLL_CTL);
7977
7978 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7979 DRM_ERROR("LCPLL still locked\n");
7980
7981 val = hsw_read_dcomp(dev_priv);
7982 val |= D_COMP_COMP_DISABLE;
7983 hsw_write_dcomp(dev_priv, val);
7984 ndelay(100);
7985
7986 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7987 1))
7988 DRM_ERROR("D_COMP RCOMP still in progress\n");
7989
7990 if (allow_power_down) {
7991 val = I915_READ(LCPLL_CTL);
7992 val |= LCPLL_POWER_DOWN_ALLOW;
7993 I915_WRITE(LCPLL_CTL, val);
7994 POSTING_READ(LCPLL_CTL);
7995 }
7996 }
7997
7998 /*
7999 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8000 * source.
8001 */
8002 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8003 {
8004 uint32_t val;
8005
8006 val = I915_READ(LCPLL_CTL);
8007
8008 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8009 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8010 return;
8011
8012 /*
8013 * Make sure we're not on PC8 state before disabling PC8, otherwise
8014 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8015 */
8016 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8017
8018 if (val & LCPLL_POWER_DOWN_ALLOW) {
8019 val &= ~LCPLL_POWER_DOWN_ALLOW;
8020 I915_WRITE(LCPLL_CTL, val);
8021 POSTING_READ(LCPLL_CTL);
8022 }
8023
8024 val = hsw_read_dcomp(dev_priv);
8025 val |= D_COMP_COMP_FORCE;
8026 val &= ~D_COMP_COMP_DISABLE;
8027 hsw_write_dcomp(dev_priv, val);
8028
8029 val = I915_READ(LCPLL_CTL);
8030 val &= ~LCPLL_PLL_DISABLE;
8031 I915_WRITE(LCPLL_CTL, val);
8032
8033 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
8034 DRM_ERROR("LCPLL not locked yet\n");
8035
8036 if (val & LCPLL_CD_SOURCE_FCLK) {
8037 val = I915_READ(LCPLL_CTL);
8038 val &= ~LCPLL_CD_SOURCE_FCLK;
8039 I915_WRITE(LCPLL_CTL, val);
8040
8041 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
8042 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8043 DRM_ERROR("Switching back to LCPLL failed\n");
8044 }
8045
8046 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8047 }
8048
8049 /*
8050 * Package states C8 and deeper are really deep PC states that can only be
8051 * reached when all the devices on the system allow it, so even if the graphics
8052 * device allows PC8+, it doesn't mean the system will actually get to these
8053 * states. Our driver only allows PC8+ when going into runtime PM.
8054 *
8055 * The requirements for PC8+ are that all the outputs are disabled, the power
8056 * well is disabled and most interrupts are disabled, and these are also
8057 * requirements for runtime PM. When these conditions are met, we manually do
8058 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8059 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8060 * hang the machine.
8061 *
8062 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8063 * the state of some registers, so when we come back from PC8+ we need to
8064 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8065 * need to take care of the registers kept by RC6. Notice that this happens even
8066 * if we don't put the device in PCI D3 state (which is what currently happens
8067 * because of the runtime PM support).
8068 *
8069 * For more, read "Display Sequences for Package C8" on the hardware
8070 * documentation.
8071 */
8072 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8073 {
8074 struct drm_device *dev = dev_priv->dev;
8075 uint32_t val;
8076
8077 DRM_DEBUG_KMS("Enabling package C8+\n");
8078
8079 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8080 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8081 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8082 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8083 }
8084
8085 lpt_disable_clkout_dp(dev);
8086 hsw_disable_lcpll(dev_priv, true, true);
8087 }
8088
8089 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8090 {
8091 struct drm_device *dev = dev_priv->dev;
8092 uint32_t val;
8093
8094 DRM_DEBUG_KMS("Disabling package C8+\n");
8095
8096 hsw_restore_lcpll(dev_priv);
8097 lpt_init_pch_refclk(dev);
8098
8099 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8100 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8101 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8102 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8103 }
8104
8105 intel_prepare_ddi(dev);
8106 }
8107
8108 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8109 struct intel_crtc_state *crtc_state)
8110 {
8111 if (!intel_ddi_pll_select(crtc, crtc_state))
8112 return -EINVAL;
8113
8114 crtc->lowfreq_avail = false;
8115
8116 return 0;
8117 }
8118
8119 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8120 enum port port,
8121 struct intel_crtc_state *pipe_config)
8122 {
8123 u32 temp, dpll_ctl1;
8124
8125 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8126 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
8127
8128 switch (pipe_config->ddi_pll_sel) {
8129 case SKL_DPLL0:
8130 /*
8131 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
8132 * of the shared DPLL framework and thus needs to be read out
8133 * separately
8134 */
8135 dpll_ctl1 = I915_READ(DPLL_CTRL1);
8136 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
8137 break;
8138 case SKL_DPLL1:
8139 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
8140 break;
8141 case SKL_DPLL2:
8142 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
8143 break;
8144 case SKL_DPLL3:
8145 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
8146 break;
8147 }
8148 }
8149
8150 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8151 enum port port,
8152 struct intel_crtc_state *pipe_config)
8153 {
8154 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8155
8156 switch (pipe_config->ddi_pll_sel) {
8157 case PORT_CLK_SEL_WRPLL1:
8158 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
8159 break;
8160 case PORT_CLK_SEL_WRPLL2:
8161 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
8162 break;
8163 }
8164 }
8165
8166 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
8167 struct intel_crtc_state *pipe_config)
8168 {
8169 struct drm_device *dev = crtc->base.dev;
8170 struct drm_i915_private *dev_priv = dev->dev_private;
8171 struct intel_shared_dpll *pll;
8172 enum port port;
8173 uint32_t tmp;
8174
8175 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
8176
8177 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8178
8179 if (IS_SKYLAKE(dev))
8180 skylake_get_ddi_pll(dev_priv, port, pipe_config);
8181 else
8182 haswell_get_ddi_pll(dev_priv, port, pipe_config);
8183
8184 if (pipe_config->shared_dpll >= 0) {
8185 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8186
8187 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8188 &pipe_config->dpll_hw_state));
8189 }
8190
8191 /*
8192 * Haswell has only FDI/PCH transcoder A. It is which is connected to
8193 * DDI E. So just check whether this pipe is wired to DDI E and whether
8194 * the PCH transcoder is on.
8195 */
8196 if (INTEL_INFO(dev)->gen < 9 &&
8197 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
8198 pipe_config->has_pch_encoder = true;
8199
8200 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8201 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8202 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8203
8204 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8205 }
8206 }
8207
8208 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
8209 struct intel_crtc_state *pipe_config)
8210 {
8211 struct drm_device *dev = crtc->base.dev;
8212 struct drm_i915_private *dev_priv = dev->dev_private;
8213 enum intel_display_power_domain pfit_domain;
8214 uint32_t tmp;
8215
8216 if (!intel_display_power_is_enabled(dev_priv,
8217 POWER_DOMAIN_PIPE(crtc->pipe)))
8218 return false;
8219
8220 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8221 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8222
8223 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8224 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8225 enum pipe trans_edp_pipe;
8226 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8227 default:
8228 WARN(1, "unknown pipe linked to edp transcoder\n");
8229 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8230 case TRANS_DDI_EDP_INPUT_A_ON:
8231 trans_edp_pipe = PIPE_A;
8232 break;
8233 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8234 trans_edp_pipe = PIPE_B;
8235 break;
8236 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8237 trans_edp_pipe = PIPE_C;
8238 break;
8239 }
8240
8241 if (trans_edp_pipe == crtc->pipe)
8242 pipe_config->cpu_transcoder = TRANSCODER_EDP;
8243 }
8244
8245 if (!intel_display_power_is_enabled(dev_priv,
8246 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
8247 return false;
8248
8249 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8250 if (!(tmp & PIPECONF_ENABLE))
8251 return false;
8252
8253 haswell_get_ddi_port_state(crtc, pipe_config);
8254
8255 intel_get_pipe_timings(crtc, pipe_config);
8256
8257 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
8258 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
8259 if (IS_SKYLAKE(dev))
8260 skylake_get_pfit_config(crtc, pipe_config);
8261 else
8262 ironlake_get_pfit_config(crtc, pipe_config);
8263 }
8264
8265 if (IS_HASWELL(dev))
8266 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8267 (I915_READ(IPS_CTL) & IPS_ENABLE);
8268
8269 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8270 pipe_config->pixel_multiplier =
8271 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8272 } else {
8273 pipe_config->pixel_multiplier = 1;
8274 }
8275
8276 return true;
8277 }
8278
8279 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8280 {
8281 struct drm_device *dev = crtc->dev;
8282 struct drm_i915_private *dev_priv = dev->dev_private;
8283 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8284 uint32_t cntl = 0, size = 0;
8285
8286 if (base) {
8287 unsigned int width = intel_crtc->cursor_width;
8288 unsigned int height = intel_crtc->cursor_height;
8289 unsigned int stride = roundup_pow_of_two(width) * 4;
8290
8291 switch (stride) {
8292 default:
8293 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8294 width, stride);
8295 stride = 256;
8296 /* fallthrough */
8297 case 256:
8298 case 512:
8299 case 1024:
8300 case 2048:
8301 break;
8302 }
8303
8304 cntl |= CURSOR_ENABLE |
8305 CURSOR_GAMMA_ENABLE |
8306 CURSOR_FORMAT_ARGB |
8307 CURSOR_STRIDE(stride);
8308
8309 size = (height << 12) | width;
8310 }
8311
8312 if (intel_crtc->cursor_cntl != 0 &&
8313 (intel_crtc->cursor_base != base ||
8314 intel_crtc->cursor_size != size ||
8315 intel_crtc->cursor_cntl != cntl)) {
8316 /* On these chipsets we can only modify the base/size/stride
8317 * whilst the cursor is disabled.
8318 */
8319 I915_WRITE(_CURACNTR, 0);
8320 POSTING_READ(_CURACNTR);
8321 intel_crtc->cursor_cntl = 0;
8322 }
8323
8324 if (intel_crtc->cursor_base != base) {
8325 I915_WRITE(_CURABASE, base);
8326 intel_crtc->cursor_base = base;
8327 }
8328
8329 if (intel_crtc->cursor_size != size) {
8330 I915_WRITE(CURSIZE, size);
8331 intel_crtc->cursor_size = size;
8332 }
8333
8334 if (intel_crtc->cursor_cntl != cntl) {
8335 I915_WRITE(_CURACNTR, cntl);
8336 POSTING_READ(_CURACNTR);
8337 intel_crtc->cursor_cntl = cntl;
8338 }
8339 }
8340
8341 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8342 {
8343 struct drm_device *dev = crtc->dev;
8344 struct drm_i915_private *dev_priv = dev->dev_private;
8345 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8346 int pipe = intel_crtc->pipe;
8347 uint32_t cntl;
8348
8349 cntl = 0;
8350 if (base) {
8351 cntl = MCURSOR_GAMMA_ENABLE;
8352 switch (intel_crtc->cursor_width) {
8353 case 64:
8354 cntl |= CURSOR_MODE_64_ARGB_AX;
8355 break;
8356 case 128:
8357 cntl |= CURSOR_MODE_128_ARGB_AX;
8358 break;
8359 case 256:
8360 cntl |= CURSOR_MODE_256_ARGB_AX;
8361 break;
8362 default:
8363 MISSING_CASE(intel_crtc->cursor_width);
8364 return;
8365 }
8366 cntl |= pipe << 28; /* Connect to correct pipe */
8367
8368 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8369 cntl |= CURSOR_PIPE_CSC_ENABLE;
8370 }
8371
8372 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
8373 cntl |= CURSOR_ROTATE_180;
8374
8375 if (intel_crtc->cursor_cntl != cntl) {
8376 I915_WRITE(CURCNTR(pipe), cntl);
8377 POSTING_READ(CURCNTR(pipe));
8378 intel_crtc->cursor_cntl = cntl;
8379 }
8380
8381 /* and commit changes on next vblank */
8382 I915_WRITE(CURBASE(pipe), base);
8383 POSTING_READ(CURBASE(pipe));
8384
8385 intel_crtc->cursor_base = base;
8386 }
8387
8388 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8389 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8390 bool on)
8391 {
8392 struct drm_device *dev = crtc->dev;
8393 struct drm_i915_private *dev_priv = dev->dev_private;
8394 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8395 int pipe = intel_crtc->pipe;
8396 int x = crtc->cursor_x;
8397 int y = crtc->cursor_y;
8398 u32 base = 0, pos = 0;
8399
8400 if (on)
8401 base = intel_crtc->cursor_addr;
8402
8403 if (x >= intel_crtc->config->pipe_src_w)
8404 base = 0;
8405
8406 if (y >= intel_crtc->config->pipe_src_h)
8407 base = 0;
8408
8409 if (x < 0) {
8410 if (x + intel_crtc->cursor_width <= 0)
8411 base = 0;
8412
8413 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8414 x = -x;
8415 }
8416 pos |= x << CURSOR_X_SHIFT;
8417
8418 if (y < 0) {
8419 if (y + intel_crtc->cursor_height <= 0)
8420 base = 0;
8421
8422 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8423 y = -y;
8424 }
8425 pos |= y << CURSOR_Y_SHIFT;
8426
8427 if (base == 0 && intel_crtc->cursor_base == 0)
8428 return;
8429
8430 I915_WRITE(CURPOS(pipe), pos);
8431
8432 /* ILK+ do this automagically */
8433 if (HAS_GMCH_DISPLAY(dev) &&
8434 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
8435 base += (intel_crtc->cursor_height *
8436 intel_crtc->cursor_width - 1) * 4;
8437 }
8438
8439 if (IS_845G(dev) || IS_I865G(dev))
8440 i845_update_cursor(crtc, base);
8441 else
8442 i9xx_update_cursor(crtc, base);
8443 }
8444
8445 static bool cursor_size_ok(struct drm_device *dev,
8446 uint32_t width, uint32_t height)
8447 {
8448 if (width == 0 || height == 0)
8449 return false;
8450
8451 /*
8452 * 845g/865g are special in that they are only limited by
8453 * the width of their cursors, the height is arbitrary up to
8454 * the precision of the register. Everything else requires
8455 * square cursors, limited to a few power-of-two sizes.
8456 */
8457 if (IS_845G(dev) || IS_I865G(dev)) {
8458 if ((width & 63) != 0)
8459 return false;
8460
8461 if (width > (IS_845G(dev) ? 64 : 512))
8462 return false;
8463
8464 if (height > 1023)
8465 return false;
8466 } else {
8467 switch (width | height) {
8468 case 256:
8469 case 128:
8470 if (IS_GEN2(dev))
8471 return false;
8472 case 64:
8473 break;
8474 default:
8475 return false;
8476 }
8477 }
8478
8479 return true;
8480 }
8481
8482 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8483 u16 *blue, uint32_t start, uint32_t size)
8484 {
8485 int end = (start + size > 256) ? 256 : start + size, i;
8486 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8487
8488 for (i = start; i < end; i++) {
8489 intel_crtc->lut_r[i] = red[i] >> 8;
8490 intel_crtc->lut_g[i] = green[i] >> 8;
8491 intel_crtc->lut_b[i] = blue[i] >> 8;
8492 }
8493
8494 intel_crtc_load_lut(crtc);
8495 }
8496
8497 /* VESA 640x480x72Hz mode to set on the pipe */
8498 static struct drm_display_mode load_detect_mode = {
8499 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8500 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8501 };
8502
8503 struct drm_framebuffer *
8504 __intel_framebuffer_create(struct drm_device *dev,
8505 struct drm_mode_fb_cmd2 *mode_cmd,
8506 struct drm_i915_gem_object *obj)
8507 {
8508 struct intel_framebuffer *intel_fb;
8509 int ret;
8510
8511 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8512 if (!intel_fb) {
8513 drm_gem_object_unreference(&obj->base);
8514 return ERR_PTR(-ENOMEM);
8515 }
8516
8517 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8518 if (ret)
8519 goto err;
8520
8521 return &intel_fb->base;
8522 err:
8523 drm_gem_object_unreference(&obj->base);
8524 kfree(intel_fb);
8525
8526 return ERR_PTR(ret);
8527 }
8528
8529 static struct drm_framebuffer *
8530 intel_framebuffer_create(struct drm_device *dev,
8531 struct drm_mode_fb_cmd2 *mode_cmd,
8532 struct drm_i915_gem_object *obj)
8533 {
8534 struct drm_framebuffer *fb;
8535 int ret;
8536
8537 ret = i915_mutex_lock_interruptible(dev);
8538 if (ret)
8539 return ERR_PTR(ret);
8540 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8541 mutex_unlock(&dev->struct_mutex);
8542
8543 return fb;
8544 }
8545
8546 static u32
8547 intel_framebuffer_pitch_for_width(int width, int bpp)
8548 {
8549 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8550 return ALIGN(pitch, 64);
8551 }
8552
8553 static u32
8554 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8555 {
8556 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8557 return PAGE_ALIGN(pitch * mode->vdisplay);
8558 }
8559
8560 static struct drm_framebuffer *
8561 intel_framebuffer_create_for_mode(struct drm_device *dev,
8562 struct drm_display_mode *mode,
8563 int depth, int bpp)
8564 {
8565 struct drm_i915_gem_object *obj;
8566 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8567
8568 obj = i915_gem_alloc_object(dev,
8569 intel_framebuffer_size_for_mode(mode, bpp));
8570 if (obj == NULL)
8571 return ERR_PTR(-ENOMEM);
8572
8573 mode_cmd.width = mode->hdisplay;
8574 mode_cmd.height = mode->vdisplay;
8575 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8576 bpp);
8577 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8578
8579 return intel_framebuffer_create(dev, &mode_cmd, obj);
8580 }
8581
8582 static struct drm_framebuffer *
8583 mode_fits_in_fbdev(struct drm_device *dev,
8584 struct drm_display_mode *mode)
8585 {
8586 #ifdef CONFIG_DRM_I915_FBDEV
8587 struct drm_i915_private *dev_priv = dev->dev_private;
8588 struct drm_i915_gem_object *obj;
8589 struct drm_framebuffer *fb;
8590
8591 if (!dev_priv->fbdev)
8592 return NULL;
8593
8594 if (!dev_priv->fbdev->fb)
8595 return NULL;
8596
8597 obj = dev_priv->fbdev->fb->obj;
8598 BUG_ON(!obj);
8599
8600 fb = &dev_priv->fbdev->fb->base;
8601 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8602 fb->bits_per_pixel))
8603 return NULL;
8604
8605 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8606 return NULL;
8607
8608 return fb;
8609 #else
8610 return NULL;
8611 #endif
8612 }
8613
8614 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8615 struct drm_display_mode *mode,
8616 struct intel_load_detect_pipe *old,
8617 struct drm_modeset_acquire_ctx *ctx)
8618 {
8619 struct intel_crtc *intel_crtc;
8620 struct intel_encoder *intel_encoder =
8621 intel_attached_encoder(connector);
8622 struct drm_crtc *possible_crtc;
8623 struct drm_encoder *encoder = &intel_encoder->base;
8624 struct drm_crtc *crtc = NULL;
8625 struct drm_device *dev = encoder->dev;
8626 struct drm_framebuffer *fb;
8627 struct drm_mode_config *config = &dev->mode_config;
8628 int ret, i = -1;
8629
8630 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8631 connector->base.id, connector->name,
8632 encoder->base.id, encoder->name);
8633
8634 retry:
8635 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8636 if (ret)
8637 goto fail_unlock;
8638
8639 /*
8640 * Algorithm gets a little messy:
8641 *
8642 * - if the connector already has an assigned crtc, use it (but make
8643 * sure it's on first)
8644 *
8645 * - try to find the first unused crtc that can drive this connector,
8646 * and use that if we find one
8647 */
8648
8649 /* See if we already have a CRTC for this connector */
8650 if (encoder->crtc) {
8651 crtc = encoder->crtc;
8652
8653 ret = drm_modeset_lock(&crtc->mutex, ctx);
8654 if (ret)
8655 goto fail_unlock;
8656 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8657 if (ret)
8658 goto fail_unlock;
8659
8660 old->dpms_mode = connector->dpms;
8661 old->load_detect_temp = false;
8662
8663 /* Make sure the crtc and connector are running */
8664 if (connector->dpms != DRM_MODE_DPMS_ON)
8665 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8666
8667 return true;
8668 }
8669
8670 /* Find an unused one (if possible) */
8671 for_each_crtc(dev, possible_crtc) {
8672 i++;
8673 if (!(encoder->possible_crtcs & (1 << i)))
8674 continue;
8675 if (possible_crtc->enabled)
8676 continue;
8677 /* This can occur when applying the pipe A quirk on resume. */
8678 if (to_intel_crtc(possible_crtc)->new_enabled)
8679 continue;
8680
8681 crtc = possible_crtc;
8682 break;
8683 }
8684
8685 /*
8686 * If we didn't find an unused CRTC, don't use any.
8687 */
8688 if (!crtc) {
8689 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8690 goto fail_unlock;
8691 }
8692
8693 ret = drm_modeset_lock(&crtc->mutex, ctx);
8694 if (ret)
8695 goto fail_unlock;
8696 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8697 if (ret)
8698 goto fail_unlock;
8699 intel_encoder->new_crtc = to_intel_crtc(crtc);
8700 to_intel_connector(connector)->new_encoder = intel_encoder;
8701
8702 intel_crtc = to_intel_crtc(crtc);
8703 intel_crtc->new_enabled = true;
8704 intel_crtc->new_config = intel_crtc->config;
8705 old->dpms_mode = connector->dpms;
8706 old->load_detect_temp = true;
8707 old->release_fb = NULL;
8708
8709 if (!mode)
8710 mode = &load_detect_mode;
8711
8712 /* We need a framebuffer large enough to accommodate all accesses
8713 * that the plane may generate whilst we perform load detection.
8714 * We can not rely on the fbcon either being present (we get called
8715 * during its initialisation to detect all boot displays, or it may
8716 * not even exist) or that it is large enough to satisfy the
8717 * requested mode.
8718 */
8719 fb = mode_fits_in_fbdev(dev, mode);
8720 if (fb == NULL) {
8721 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8722 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8723 old->release_fb = fb;
8724 } else
8725 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8726 if (IS_ERR(fb)) {
8727 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8728 goto fail;
8729 }
8730
8731 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8732 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8733 if (old->release_fb)
8734 old->release_fb->funcs->destroy(old->release_fb);
8735 goto fail;
8736 }
8737 crtc->primary->crtc = crtc;
8738
8739 /* let the connector get through one full cycle before testing */
8740 intel_wait_for_vblank(dev, intel_crtc->pipe);
8741 return true;
8742
8743 fail:
8744 intel_crtc->new_enabled = crtc->enabled;
8745 if (intel_crtc->new_enabled)
8746 intel_crtc->new_config = intel_crtc->config;
8747 else
8748 intel_crtc->new_config = NULL;
8749 fail_unlock:
8750 if (ret == -EDEADLK) {
8751 drm_modeset_backoff(ctx);
8752 goto retry;
8753 }
8754
8755 return false;
8756 }
8757
8758 void intel_release_load_detect_pipe(struct drm_connector *connector,
8759 struct intel_load_detect_pipe *old)
8760 {
8761 struct intel_encoder *intel_encoder =
8762 intel_attached_encoder(connector);
8763 struct drm_encoder *encoder = &intel_encoder->base;
8764 struct drm_crtc *crtc = encoder->crtc;
8765 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8766
8767 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8768 connector->base.id, connector->name,
8769 encoder->base.id, encoder->name);
8770
8771 if (old->load_detect_temp) {
8772 to_intel_connector(connector)->new_encoder = NULL;
8773 intel_encoder->new_crtc = NULL;
8774 intel_crtc->new_enabled = false;
8775 intel_crtc->new_config = NULL;
8776 intel_set_mode(crtc, NULL, 0, 0, NULL);
8777
8778 if (old->release_fb) {
8779 drm_framebuffer_unregister_private(old->release_fb);
8780 drm_framebuffer_unreference(old->release_fb);
8781 }
8782
8783 return;
8784 }
8785
8786 /* Switch crtc and encoder back off if necessary */
8787 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8788 connector->funcs->dpms(connector, old->dpms_mode);
8789 }
8790
8791 static int i9xx_pll_refclk(struct drm_device *dev,
8792 const struct intel_crtc_state *pipe_config)
8793 {
8794 struct drm_i915_private *dev_priv = dev->dev_private;
8795 u32 dpll = pipe_config->dpll_hw_state.dpll;
8796
8797 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8798 return dev_priv->vbt.lvds_ssc_freq;
8799 else if (HAS_PCH_SPLIT(dev))
8800 return 120000;
8801 else if (!IS_GEN2(dev))
8802 return 96000;
8803 else
8804 return 48000;
8805 }
8806
8807 /* Returns the clock of the currently programmed mode of the given pipe. */
8808 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8809 struct intel_crtc_state *pipe_config)
8810 {
8811 struct drm_device *dev = crtc->base.dev;
8812 struct drm_i915_private *dev_priv = dev->dev_private;
8813 int pipe = pipe_config->cpu_transcoder;
8814 u32 dpll = pipe_config->dpll_hw_state.dpll;
8815 u32 fp;
8816 intel_clock_t clock;
8817 int refclk = i9xx_pll_refclk(dev, pipe_config);
8818
8819 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8820 fp = pipe_config->dpll_hw_state.fp0;
8821 else
8822 fp = pipe_config->dpll_hw_state.fp1;
8823
8824 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8825 if (IS_PINEVIEW(dev)) {
8826 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8827 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8828 } else {
8829 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8830 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8831 }
8832
8833 if (!IS_GEN2(dev)) {
8834 if (IS_PINEVIEW(dev))
8835 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8836 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8837 else
8838 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8839 DPLL_FPA01_P1_POST_DIV_SHIFT);
8840
8841 switch (dpll & DPLL_MODE_MASK) {
8842 case DPLLB_MODE_DAC_SERIAL:
8843 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8844 5 : 10;
8845 break;
8846 case DPLLB_MODE_LVDS:
8847 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8848 7 : 14;
8849 break;
8850 default:
8851 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8852 "mode\n", (int)(dpll & DPLL_MODE_MASK));
8853 return;
8854 }
8855
8856 if (IS_PINEVIEW(dev))
8857 pineview_clock(refclk, &clock);
8858 else
8859 i9xx_clock(refclk, &clock);
8860 } else {
8861 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8862 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8863
8864 if (is_lvds) {
8865 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8866 DPLL_FPA01_P1_POST_DIV_SHIFT);
8867
8868 if (lvds & LVDS_CLKB_POWER_UP)
8869 clock.p2 = 7;
8870 else
8871 clock.p2 = 14;
8872 } else {
8873 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8874 clock.p1 = 2;
8875 else {
8876 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8877 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8878 }
8879 if (dpll & PLL_P2_DIVIDE_BY_4)
8880 clock.p2 = 4;
8881 else
8882 clock.p2 = 2;
8883 }
8884
8885 i9xx_clock(refclk, &clock);
8886 }
8887
8888 /*
8889 * This value includes pixel_multiplier. We will use
8890 * port_clock to compute adjusted_mode.crtc_clock in the
8891 * encoder's get_config() function.
8892 */
8893 pipe_config->port_clock = clock.dot;
8894 }
8895
8896 int intel_dotclock_calculate(int link_freq,
8897 const struct intel_link_m_n *m_n)
8898 {
8899 /*
8900 * The calculation for the data clock is:
8901 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8902 * But we want to avoid losing precison if possible, so:
8903 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8904 *
8905 * and the link clock is simpler:
8906 * link_clock = (m * link_clock) / n
8907 */
8908
8909 if (!m_n->link_n)
8910 return 0;
8911
8912 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8913 }
8914
8915 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8916 struct intel_crtc_state *pipe_config)
8917 {
8918 struct drm_device *dev = crtc->base.dev;
8919
8920 /* read out port_clock from the DPLL */
8921 i9xx_crtc_clock_get(crtc, pipe_config);
8922
8923 /*
8924 * This value does not include pixel_multiplier.
8925 * We will check that port_clock and adjusted_mode.crtc_clock
8926 * agree once we know their relationship in the encoder's
8927 * get_config() function.
8928 */
8929 pipe_config->base.adjusted_mode.crtc_clock =
8930 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8931 &pipe_config->fdi_m_n);
8932 }
8933
8934 /** Returns the currently programmed mode of the given pipe. */
8935 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8936 struct drm_crtc *crtc)
8937 {
8938 struct drm_i915_private *dev_priv = dev->dev_private;
8939 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8940 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8941 struct drm_display_mode *mode;
8942 struct intel_crtc_state pipe_config;
8943 int htot = I915_READ(HTOTAL(cpu_transcoder));
8944 int hsync = I915_READ(HSYNC(cpu_transcoder));
8945 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8946 int vsync = I915_READ(VSYNC(cpu_transcoder));
8947 enum pipe pipe = intel_crtc->pipe;
8948
8949 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8950 if (!mode)
8951 return NULL;
8952
8953 /*
8954 * Construct a pipe_config sufficient for getting the clock info
8955 * back out of crtc_clock_get.
8956 *
8957 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8958 * to use a real value here instead.
8959 */
8960 pipe_config.cpu_transcoder = (enum transcoder) pipe;
8961 pipe_config.pixel_multiplier = 1;
8962 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8963 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8964 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8965 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8966
8967 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8968 mode->hdisplay = (htot & 0xffff) + 1;
8969 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8970 mode->hsync_start = (hsync & 0xffff) + 1;
8971 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8972 mode->vdisplay = (vtot & 0xffff) + 1;
8973 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8974 mode->vsync_start = (vsync & 0xffff) + 1;
8975 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8976
8977 drm_mode_set_name(mode);
8978
8979 return mode;
8980 }
8981
8982 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8983 {
8984 struct drm_device *dev = crtc->dev;
8985 struct drm_i915_private *dev_priv = dev->dev_private;
8986 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8987
8988 if (!HAS_GMCH_DISPLAY(dev))
8989 return;
8990
8991 if (!dev_priv->lvds_downclock_avail)
8992 return;
8993
8994 /*
8995 * Since this is called by a timer, we should never get here in
8996 * the manual case.
8997 */
8998 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8999 int pipe = intel_crtc->pipe;
9000 int dpll_reg = DPLL(pipe);
9001 int dpll;
9002
9003 DRM_DEBUG_DRIVER("downclocking LVDS\n");
9004
9005 assert_panel_unlocked(dev_priv, pipe);
9006
9007 dpll = I915_READ(dpll_reg);
9008 dpll |= DISPLAY_RATE_SELECT_FPA1;
9009 I915_WRITE(dpll_reg, dpll);
9010 intel_wait_for_vblank(dev, pipe);
9011 dpll = I915_READ(dpll_reg);
9012 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
9013 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
9014 }
9015
9016 }
9017
9018 void intel_mark_busy(struct drm_device *dev)
9019 {
9020 struct drm_i915_private *dev_priv = dev->dev_private;
9021
9022 if (dev_priv->mm.busy)
9023 return;
9024
9025 intel_runtime_pm_get(dev_priv);
9026 i915_update_gfx_val(dev_priv);
9027 dev_priv->mm.busy = true;
9028 }
9029
9030 void intel_mark_idle(struct drm_device *dev)
9031 {
9032 struct drm_i915_private *dev_priv = dev->dev_private;
9033 struct drm_crtc *crtc;
9034
9035 if (!dev_priv->mm.busy)
9036 return;
9037
9038 dev_priv->mm.busy = false;
9039
9040 if (!i915.powersave)
9041 goto out;
9042
9043 for_each_crtc(dev, crtc) {
9044 if (!crtc->primary->fb)
9045 continue;
9046
9047 intel_decrease_pllclock(crtc);
9048 }
9049
9050 if (INTEL_INFO(dev)->gen >= 6)
9051 gen6_rps_idle(dev->dev_private);
9052
9053 out:
9054 intel_runtime_pm_put(dev_priv);
9055 }
9056
9057 static void intel_crtc_set_state(struct intel_crtc *crtc,
9058 struct intel_crtc_state *crtc_state)
9059 {
9060 kfree(crtc->config);
9061 crtc->config = crtc_state;
9062 crtc->base.state = &crtc_state->base;
9063 }
9064
9065 static void intel_crtc_destroy(struct drm_crtc *crtc)
9066 {
9067 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9068 struct drm_device *dev = crtc->dev;
9069 struct intel_unpin_work *work;
9070
9071 spin_lock_irq(&dev->event_lock);
9072 work = intel_crtc->unpin_work;
9073 intel_crtc->unpin_work = NULL;
9074 spin_unlock_irq(&dev->event_lock);
9075
9076 if (work) {
9077 cancel_work_sync(&work->work);
9078 kfree(work);
9079 }
9080
9081 intel_crtc_set_state(intel_crtc, NULL);
9082 drm_crtc_cleanup(crtc);
9083
9084 kfree(intel_crtc);
9085 }
9086
9087 static void intel_unpin_work_fn(struct work_struct *__work)
9088 {
9089 struct intel_unpin_work *work =
9090 container_of(__work, struct intel_unpin_work, work);
9091 struct drm_device *dev = work->crtc->dev;
9092 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9093
9094 mutex_lock(&dev->struct_mutex);
9095 intel_unpin_fb_obj(work->old_fb_obj);
9096 drm_gem_object_unreference(&work->pending_flip_obj->base);
9097 drm_gem_object_unreference(&work->old_fb_obj->base);
9098
9099 intel_fbc_update(dev);
9100
9101 if (work->flip_queued_req)
9102 i915_gem_request_assign(&work->flip_queued_req, NULL);
9103 mutex_unlock(&dev->struct_mutex);
9104
9105 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9106
9107 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9108 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9109
9110 kfree(work);
9111 }
9112
9113 static void do_intel_finish_page_flip(struct drm_device *dev,
9114 struct drm_crtc *crtc)
9115 {
9116 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9117 struct intel_unpin_work *work;
9118 unsigned long flags;
9119
9120 /* Ignore early vblank irqs */
9121 if (intel_crtc == NULL)
9122 return;
9123
9124 /*
9125 * This is called both by irq handlers and the reset code (to complete
9126 * lost pageflips) so needs the full irqsave spinlocks.
9127 */
9128 spin_lock_irqsave(&dev->event_lock, flags);
9129 work = intel_crtc->unpin_work;
9130
9131 /* Ensure we don't miss a work->pending update ... */
9132 smp_rmb();
9133
9134 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9135 spin_unlock_irqrestore(&dev->event_lock, flags);
9136 return;
9137 }
9138
9139 page_flip_completed(intel_crtc);
9140
9141 spin_unlock_irqrestore(&dev->event_lock, flags);
9142 }
9143
9144 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9145 {
9146 struct drm_i915_private *dev_priv = dev->dev_private;
9147 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9148
9149 do_intel_finish_page_flip(dev, crtc);
9150 }
9151
9152 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9153 {
9154 struct drm_i915_private *dev_priv = dev->dev_private;
9155 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9156
9157 do_intel_finish_page_flip(dev, crtc);
9158 }
9159
9160 /* Is 'a' after or equal to 'b'? */
9161 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9162 {
9163 return !((a - b) & 0x80000000);
9164 }
9165
9166 static bool page_flip_finished(struct intel_crtc *crtc)
9167 {
9168 struct drm_device *dev = crtc->base.dev;
9169 struct drm_i915_private *dev_priv = dev->dev_private;
9170
9171 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
9172 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
9173 return true;
9174
9175 /*
9176 * The relevant registers doen't exist on pre-ctg.
9177 * As the flip done interrupt doesn't trigger for mmio
9178 * flips on gmch platforms, a flip count check isn't
9179 * really needed there. But since ctg has the registers,
9180 * include it in the check anyway.
9181 */
9182 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9183 return true;
9184
9185 /*
9186 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9187 * used the same base address. In that case the mmio flip might
9188 * have completed, but the CS hasn't even executed the flip yet.
9189 *
9190 * A flip count check isn't enough as the CS might have updated
9191 * the base address just after start of vblank, but before we
9192 * managed to process the interrupt. This means we'd complete the
9193 * CS flip too soon.
9194 *
9195 * Combining both checks should get us a good enough result. It may
9196 * still happen that the CS flip has been executed, but has not
9197 * yet actually completed. But in case the base address is the same
9198 * anyway, we don't really care.
9199 */
9200 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9201 crtc->unpin_work->gtt_offset &&
9202 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9203 crtc->unpin_work->flip_count);
9204 }
9205
9206 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9207 {
9208 struct drm_i915_private *dev_priv = dev->dev_private;
9209 struct intel_crtc *intel_crtc =
9210 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9211 unsigned long flags;
9212
9213
9214 /*
9215 * This is called both by irq handlers and the reset code (to complete
9216 * lost pageflips) so needs the full irqsave spinlocks.
9217 *
9218 * NB: An MMIO update of the plane base pointer will also
9219 * generate a page-flip completion irq, i.e. every modeset
9220 * is also accompanied by a spurious intel_prepare_page_flip().
9221 */
9222 spin_lock_irqsave(&dev->event_lock, flags);
9223 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9224 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9225 spin_unlock_irqrestore(&dev->event_lock, flags);
9226 }
9227
9228 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9229 {
9230 /* Ensure that the work item is consistent when activating it ... */
9231 smp_wmb();
9232 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9233 /* and that it is marked active as soon as the irq could fire. */
9234 smp_wmb();
9235 }
9236
9237 static int intel_gen2_queue_flip(struct drm_device *dev,
9238 struct drm_crtc *crtc,
9239 struct drm_framebuffer *fb,
9240 struct drm_i915_gem_object *obj,
9241 struct intel_engine_cs *ring,
9242 uint32_t flags)
9243 {
9244 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9245 u32 flip_mask;
9246 int ret;
9247
9248 ret = intel_ring_begin(ring, 6);
9249 if (ret)
9250 return ret;
9251
9252 /* Can't queue multiple flips, so wait for the previous
9253 * one to finish before executing the next.
9254 */
9255 if (intel_crtc->plane)
9256 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9257 else
9258 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9259 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9260 intel_ring_emit(ring, MI_NOOP);
9261 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9262 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9263 intel_ring_emit(ring, fb->pitches[0]);
9264 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9265 intel_ring_emit(ring, 0); /* aux display base address, unused */
9266
9267 intel_mark_page_flip_active(intel_crtc);
9268 __intel_ring_advance(ring);
9269 return 0;
9270 }
9271
9272 static int intel_gen3_queue_flip(struct drm_device *dev,
9273 struct drm_crtc *crtc,
9274 struct drm_framebuffer *fb,
9275 struct drm_i915_gem_object *obj,
9276 struct intel_engine_cs *ring,
9277 uint32_t flags)
9278 {
9279 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9280 u32 flip_mask;
9281 int ret;
9282
9283 ret = intel_ring_begin(ring, 6);
9284 if (ret)
9285 return ret;
9286
9287 if (intel_crtc->plane)
9288 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9289 else
9290 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9291 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9292 intel_ring_emit(ring, MI_NOOP);
9293 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9294 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9295 intel_ring_emit(ring, fb->pitches[0]);
9296 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9297 intel_ring_emit(ring, MI_NOOP);
9298
9299 intel_mark_page_flip_active(intel_crtc);
9300 __intel_ring_advance(ring);
9301 return 0;
9302 }
9303
9304 static int intel_gen4_queue_flip(struct drm_device *dev,
9305 struct drm_crtc *crtc,
9306 struct drm_framebuffer *fb,
9307 struct drm_i915_gem_object *obj,
9308 struct intel_engine_cs *ring,
9309 uint32_t flags)
9310 {
9311 struct drm_i915_private *dev_priv = dev->dev_private;
9312 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9313 uint32_t pf, pipesrc;
9314 int ret;
9315
9316 ret = intel_ring_begin(ring, 4);
9317 if (ret)
9318 return ret;
9319
9320 /* i965+ uses the linear or tiled offsets from the
9321 * Display Registers (which do not change across a page-flip)
9322 * so we need only reprogram the base address.
9323 */
9324 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9325 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9326 intel_ring_emit(ring, fb->pitches[0]);
9327 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9328 obj->tiling_mode);
9329
9330 /* XXX Enabling the panel-fitter across page-flip is so far
9331 * untested on non-native modes, so ignore it for now.
9332 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9333 */
9334 pf = 0;
9335 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9336 intel_ring_emit(ring, pf | pipesrc);
9337
9338 intel_mark_page_flip_active(intel_crtc);
9339 __intel_ring_advance(ring);
9340 return 0;
9341 }
9342
9343 static int intel_gen6_queue_flip(struct drm_device *dev,
9344 struct drm_crtc *crtc,
9345 struct drm_framebuffer *fb,
9346 struct drm_i915_gem_object *obj,
9347 struct intel_engine_cs *ring,
9348 uint32_t flags)
9349 {
9350 struct drm_i915_private *dev_priv = dev->dev_private;
9351 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9352 uint32_t pf, pipesrc;
9353 int ret;
9354
9355 ret = intel_ring_begin(ring, 4);
9356 if (ret)
9357 return ret;
9358
9359 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9360 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9361 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9362 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9363
9364 /* Contrary to the suggestions in the documentation,
9365 * "Enable Panel Fitter" does not seem to be required when page
9366 * flipping with a non-native mode, and worse causes a normal
9367 * modeset to fail.
9368 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9369 */
9370 pf = 0;
9371 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9372 intel_ring_emit(ring, pf | pipesrc);
9373
9374 intel_mark_page_flip_active(intel_crtc);
9375 __intel_ring_advance(ring);
9376 return 0;
9377 }
9378
9379 static int intel_gen7_queue_flip(struct drm_device *dev,
9380 struct drm_crtc *crtc,
9381 struct drm_framebuffer *fb,
9382 struct drm_i915_gem_object *obj,
9383 struct intel_engine_cs *ring,
9384 uint32_t flags)
9385 {
9386 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9387 uint32_t plane_bit = 0;
9388 int len, ret;
9389
9390 switch (intel_crtc->plane) {
9391 case PLANE_A:
9392 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9393 break;
9394 case PLANE_B:
9395 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9396 break;
9397 case PLANE_C:
9398 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9399 break;
9400 default:
9401 WARN_ONCE(1, "unknown plane in flip command\n");
9402 return -ENODEV;
9403 }
9404
9405 len = 4;
9406 if (ring->id == RCS) {
9407 len += 6;
9408 /*
9409 * On Gen 8, SRM is now taking an extra dword to accommodate
9410 * 48bits addresses, and we need a NOOP for the batch size to
9411 * stay even.
9412 */
9413 if (IS_GEN8(dev))
9414 len += 2;
9415 }
9416
9417 /*
9418 * BSpec MI_DISPLAY_FLIP for IVB:
9419 * "The full packet must be contained within the same cache line."
9420 *
9421 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9422 * cacheline, if we ever start emitting more commands before
9423 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9424 * then do the cacheline alignment, and finally emit the
9425 * MI_DISPLAY_FLIP.
9426 */
9427 ret = intel_ring_cacheline_align(ring);
9428 if (ret)
9429 return ret;
9430
9431 ret = intel_ring_begin(ring, len);
9432 if (ret)
9433 return ret;
9434
9435 /* Unmask the flip-done completion message. Note that the bspec says that
9436 * we should do this for both the BCS and RCS, and that we must not unmask
9437 * more than one flip event at any time (or ensure that one flip message
9438 * can be sent by waiting for flip-done prior to queueing new flips).
9439 * Experimentation says that BCS works despite DERRMR masking all
9440 * flip-done completion events and that unmasking all planes at once
9441 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9442 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9443 */
9444 if (ring->id == RCS) {
9445 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9446 intel_ring_emit(ring, DERRMR);
9447 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9448 DERRMR_PIPEB_PRI_FLIP_DONE |
9449 DERRMR_PIPEC_PRI_FLIP_DONE));
9450 if (IS_GEN8(dev))
9451 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9452 MI_SRM_LRM_GLOBAL_GTT);
9453 else
9454 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9455 MI_SRM_LRM_GLOBAL_GTT);
9456 intel_ring_emit(ring, DERRMR);
9457 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9458 if (IS_GEN8(dev)) {
9459 intel_ring_emit(ring, 0);
9460 intel_ring_emit(ring, MI_NOOP);
9461 }
9462 }
9463
9464 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9465 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9466 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9467 intel_ring_emit(ring, (MI_NOOP));
9468
9469 intel_mark_page_flip_active(intel_crtc);
9470 __intel_ring_advance(ring);
9471 return 0;
9472 }
9473
9474 static bool use_mmio_flip(struct intel_engine_cs *ring,
9475 struct drm_i915_gem_object *obj)
9476 {
9477 /*
9478 * This is not being used for older platforms, because
9479 * non-availability of flip done interrupt forces us to use
9480 * CS flips. Older platforms derive flip done using some clever
9481 * tricks involving the flip_pending status bits and vblank irqs.
9482 * So using MMIO flips there would disrupt this mechanism.
9483 */
9484
9485 if (ring == NULL)
9486 return true;
9487
9488 if (INTEL_INFO(ring->dev)->gen < 5)
9489 return false;
9490
9491 if (i915.use_mmio_flip < 0)
9492 return false;
9493 else if (i915.use_mmio_flip > 0)
9494 return true;
9495 else if (i915.enable_execlists)
9496 return true;
9497 else
9498 return ring != i915_gem_request_get_ring(obj->last_read_req);
9499 }
9500
9501 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
9502 {
9503 struct drm_device *dev = intel_crtc->base.dev;
9504 struct drm_i915_private *dev_priv = dev->dev_private;
9505 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
9506 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9507 struct drm_i915_gem_object *obj = intel_fb->obj;
9508 const enum pipe pipe = intel_crtc->pipe;
9509 u32 ctl, stride;
9510
9511 ctl = I915_READ(PLANE_CTL(pipe, 0));
9512 ctl &= ~PLANE_CTL_TILED_MASK;
9513 if (obj->tiling_mode == I915_TILING_X)
9514 ctl |= PLANE_CTL_TILED_X;
9515
9516 /*
9517 * The stride is either expressed as a multiple of 64 bytes chunks for
9518 * linear buffers or in number of tiles for tiled buffers.
9519 */
9520 stride = fb->pitches[0] >> 6;
9521 if (obj->tiling_mode == I915_TILING_X)
9522 stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
9523
9524 /*
9525 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
9526 * PLANE_SURF updates, the update is then guaranteed to be atomic.
9527 */
9528 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
9529 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
9530
9531 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
9532 POSTING_READ(PLANE_SURF(pipe, 0));
9533 }
9534
9535 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
9536 {
9537 struct drm_device *dev = intel_crtc->base.dev;
9538 struct drm_i915_private *dev_priv = dev->dev_private;
9539 struct intel_framebuffer *intel_fb =
9540 to_intel_framebuffer(intel_crtc->base.primary->fb);
9541 struct drm_i915_gem_object *obj = intel_fb->obj;
9542 u32 dspcntr;
9543 u32 reg;
9544
9545 reg = DSPCNTR(intel_crtc->plane);
9546 dspcntr = I915_READ(reg);
9547
9548 if (obj->tiling_mode != I915_TILING_NONE)
9549 dspcntr |= DISPPLANE_TILED;
9550 else
9551 dspcntr &= ~DISPPLANE_TILED;
9552
9553 I915_WRITE(reg, dspcntr);
9554
9555 I915_WRITE(DSPSURF(intel_crtc->plane),
9556 intel_crtc->unpin_work->gtt_offset);
9557 POSTING_READ(DSPSURF(intel_crtc->plane));
9558
9559 }
9560
9561 /*
9562 * XXX: This is the temporary way to update the plane registers until we get
9563 * around to using the usual plane update functions for MMIO flips
9564 */
9565 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9566 {
9567 struct drm_device *dev = intel_crtc->base.dev;
9568 bool atomic_update;
9569 u32 start_vbl_count;
9570
9571 intel_mark_page_flip_active(intel_crtc);
9572
9573 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
9574
9575 if (INTEL_INFO(dev)->gen >= 9)
9576 skl_do_mmio_flip(intel_crtc);
9577 else
9578 /* use_mmio_flip() retricts MMIO flips to ilk+ */
9579 ilk_do_mmio_flip(intel_crtc);
9580
9581 if (atomic_update)
9582 intel_pipe_update_end(intel_crtc, start_vbl_count);
9583 }
9584
9585 static void intel_mmio_flip_work_func(struct work_struct *work)
9586 {
9587 struct intel_crtc *crtc =
9588 container_of(work, struct intel_crtc, mmio_flip.work);
9589 struct intel_mmio_flip *mmio_flip;
9590
9591 mmio_flip = &crtc->mmio_flip;
9592 if (mmio_flip->req)
9593 WARN_ON(__i915_wait_request(mmio_flip->req,
9594 crtc->reset_counter,
9595 false, NULL, NULL) != 0);
9596
9597 intel_do_mmio_flip(crtc);
9598 if (mmio_flip->req) {
9599 mutex_lock(&crtc->base.dev->struct_mutex);
9600 i915_gem_request_assign(&mmio_flip->req, NULL);
9601 mutex_unlock(&crtc->base.dev->struct_mutex);
9602 }
9603 }
9604
9605 static int intel_queue_mmio_flip(struct drm_device *dev,
9606 struct drm_crtc *crtc,
9607 struct drm_framebuffer *fb,
9608 struct drm_i915_gem_object *obj,
9609 struct intel_engine_cs *ring,
9610 uint32_t flags)
9611 {
9612 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9613
9614 i915_gem_request_assign(&intel_crtc->mmio_flip.req,
9615 obj->last_write_req);
9616
9617 schedule_work(&intel_crtc->mmio_flip.work);
9618
9619 return 0;
9620 }
9621
9622 static int intel_gen9_queue_flip(struct drm_device *dev,
9623 struct drm_crtc *crtc,
9624 struct drm_framebuffer *fb,
9625 struct drm_i915_gem_object *obj,
9626 struct intel_engine_cs *ring,
9627 uint32_t flags)
9628 {
9629 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9630 uint32_t plane = 0, stride;
9631 int ret;
9632
9633 switch(intel_crtc->pipe) {
9634 case PIPE_A:
9635 plane = MI_DISPLAY_FLIP_SKL_PLANE_1_A;
9636 break;
9637 case PIPE_B:
9638 plane = MI_DISPLAY_FLIP_SKL_PLANE_1_B;
9639 break;
9640 case PIPE_C:
9641 plane = MI_DISPLAY_FLIP_SKL_PLANE_1_C;
9642 break;
9643 default:
9644 WARN_ONCE(1, "unknown plane in flip command\n");
9645 return -ENODEV;
9646 }
9647
9648 switch (obj->tiling_mode) {
9649 case I915_TILING_NONE:
9650 stride = fb->pitches[0] >> 6;
9651 break;
9652 case I915_TILING_X:
9653 stride = fb->pitches[0] >> 9;
9654 break;
9655 default:
9656 WARN_ONCE(1, "unknown tiling in flip command\n");
9657 return -ENODEV;
9658 }
9659
9660 ret = intel_ring_begin(ring, 10);
9661 if (ret)
9662 return ret;
9663
9664 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9665 intel_ring_emit(ring, DERRMR);
9666 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9667 DERRMR_PIPEB_PRI_FLIP_DONE |
9668 DERRMR_PIPEC_PRI_FLIP_DONE));
9669 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9670 MI_SRM_LRM_GLOBAL_GTT);
9671 intel_ring_emit(ring, DERRMR);
9672 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9673 intel_ring_emit(ring, 0);
9674
9675 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane);
9676 intel_ring_emit(ring, stride << 6 | obj->tiling_mode);
9677 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9678
9679 intel_mark_page_flip_active(intel_crtc);
9680 __intel_ring_advance(ring);
9681
9682 return 0;
9683 }
9684
9685 static int intel_default_queue_flip(struct drm_device *dev,
9686 struct drm_crtc *crtc,
9687 struct drm_framebuffer *fb,
9688 struct drm_i915_gem_object *obj,
9689 struct intel_engine_cs *ring,
9690 uint32_t flags)
9691 {
9692 return -ENODEV;
9693 }
9694
9695 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9696 struct drm_crtc *crtc)
9697 {
9698 struct drm_i915_private *dev_priv = dev->dev_private;
9699 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9700 struct intel_unpin_work *work = intel_crtc->unpin_work;
9701 u32 addr;
9702
9703 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9704 return true;
9705
9706 if (!work->enable_stall_check)
9707 return false;
9708
9709 if (work->flip_ready_vblank == 0) {
9710 if (work->flip_queued_req &&
9711 !i915_gem_request_completed(work->flip_queued_req, true))
9712 return false;
9713
9714 work->flip_ready_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9715 }
9716
9717 if (drm_vblank_count(dev, intel_crtc->pipe) - work->flip_ready_vblank < 3)
9718 return false;
9719
9720 /* Potential stall - if we see that the flip has happened,
9721 * assume a missed interrupt. */
9722 if (INTEL_INFO(dev)->gen >= 4)
9723 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9724 else
9725 addr = I915_READ(DSPADDR(intel_crtc->plane));
9726
9727 /* There is a potential issue here with a false positive after a flip
9728 * to the same address. We could address this by checking for a
9729 * non-incrementing frame counter.
9730 */
9731 return addr == work->gtt_offset;
9732 }
9733
9734 void intel_check_page_flip(struct drm_device *dev, int pipe)
9735 {
9736 struct drm_i915_private *dev_priv = dev->dev_private;
9737 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9738 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9739
9740 WARN_ON(!in_interrupt());
9741
9742 if (crtc == NULL)
9743 return;
9744
9745 spin_lock(&dev->event_lock);
9746 if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9747 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9748 intel_crtc->unpin_work->flip_queued_vblank, drm_vblank_count(dev, pipe));
9749 page_flip_completed(intel_crtc);
9750 }
9751 spin_unlock(&dev->event_lock);
9752 }
9753
9754 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9755 struct drm_framebuffer *fb,
9756 struct drm_pending_vblank_event *event,
9757 uint32_t page_flip_flags)
9758 {
9759 struct drm_device *dev = crtc->dev;
9760 struct drm_i915_private *dev_priv = dev->dev_private;
9761 struct drm_framebuffer *old_fb = crtc->primary->fb;
9762 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9763 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9764 struct drm_plane *primary = crtc->primary;
9765 enum pipe pipe = intel_crtc->pipe;
9766 struct intel_unpin_work *work;
9767 struct intel_engine_cs *ring;
9768 int ret;
9769
9770 /*
9771 * drm_mode_page_flip_ioctl() should already catch this, but double
9772 * check to be safe. In the future we may enable pageflipping from
9773 * a disabled primary plane.
9774 */
9775 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9776 return -EBUSY;
9777
9778 /* Can't change pixel format via MI display flips. */
9779 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9780 return -EINVAL;
9781
9782 /*
9783 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9784 * Note that pitch changes could also affect these register.
9785 */
9786 if (INTEL_INFO(dev)->gen > 3 &&
9787 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9788 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9789 return -EINVAL;
9790
9791 if (i915_terminally_wedged(&dev_priv->gpu_error))
9792 goto out_hang;
9793
9794 work = kzalloc(sizeof(*work), GFP_KERNEL);
9795 if (work == NULL)
9796 return -ENOMEM;
9797
9798 work->event = event;
9799 work->crtc = crtc;
9800 work->old_fb_obj = intel_fb_obj(old_fb);
9801 INIT_WORK(&work->work, intel_unpin_work_fn);
9802
9803 ret = drm_crtc_vblank_get(crtc);
9804 if (ret)
9805 goto free_work;
9806
9807 /* We borrow the event spin lock for protecting unpin_work */
9808 spin_lock_irq(&dev->event_lock);
9809 if (intel_crtc->unpin_work) {
9810 /* Before declaring the flip queue wedged, check if
9811 * the hardware completed the operation behind our backs.
9812 */
9813 if (__intel_pageflip_stall_check(dev, crtc)) {
9814 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9815 page_flip_completed(intel_crtc);
9816 } else {
9817 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9818 spin_unlock_irq(&dev->event_lock);
9819
9820 drm_crtc_vblank_put(crtc);
9821 kfree(work);
9822 return -EBUSY;
9823 }
9824 }
9825 intel_crtc->unpin_work = work;
9826 spin_unlock_irq(&dev->event_lock);
9827
9828 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9829 flush_workqueue(dev_priv->wq);
9830
9831 ret = i915_mutex_lock_interruptible(dev);
9832 if (ret)
9833 goto cleanup;
9834
9835 /* Reference the objects for the scheduled work. */
9836 drm_gem_object_reference(&work->old_fb_obj->base);
9837 drm_gem_object_reference(&obj->base);
9838
9839 crtc->primary->fb = fb;
9840 update_state_fb(crtc->primary);
9841
9842 work->pending_flip_obj = obj;
9843
9844 atomic_inc(&intel_crtc->unpin_work_count);
9845 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9846
9847 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9848 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9849
9850 if (IS_VALLEYVIEW(dev)) {
9851 ring = &dev_priv->ring[BCS];
9852 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9853 /* vlv: DISPLAY_FLIP fails to change tiling */
9854 ring = NULL;
9855 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
9856 ring = &dev_priv->ring[BCS];
9857 } else if (INTEL_INFO(dev)->gen >= 7) {
9858 ring = i915_gem_request_get_ring(obj->last_read_req);
9859 if (ring == NULL || ring->id != RCS)
9860 ring = &dev_priv->ring[BCS];
9861 } else {
9862 ring = &dev_priv->ring[RCS];
9863 }
9864
9865 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, ring);
9866 if (ret)
9867 goto cleanup_pending;
9868
9869 work->gtt_offset =
9870 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9871
9872 if (use_mmio_flip(ring, obj)) {
9873 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9874 page_flip_flags);
9875 if (ret)
9876 goto cleanup_unpin;
9877
9878 i915_gem_request_assign(&work->flip_queued_req,
9879 obj->last_write_req);
9880 } else {
9881 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9882 page_flip_flags);
9883 if (ret)
9884 goto cleanup_unpin;
9885
9886 i915_gem_request_assign(&work->flip_queued_req,
9887 intel_ring_get_request(ring));
9888 }
9889
9890 work->flip_queued_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9891 work->enable_stall_check = true;
9892
9893 i915_gem_track_fb(work->old_fb_obj, obj,
9894 INTEL_FRONTBUFFER_PRIMARY(pipe));
9895
9896 intel_fbc_disable(dev);
9897 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9898 mutex_unlock(&dev->struct_mutex);
9899
9900 trace_i915_flip_request(intel_crtc->plane, obj);
9901
9902 return 0;
9903
9904 cleanup_unpin:
9905 intel_unpin_fb_obj(obj);
9906 cleanup_pending:
9907 atomic_dec(&intel_crtc->unpin_work_count);
9908 crtc->primary->fb = old_fb;
9909 update_state_fb(crtc->primary);
9910 drm_gem_object_unreference(&work->old_fb_obj->base);
9911 drm_gem_object_unreference(&obj->base);
9912 mutex_unlock(&dev->struct_mutex);
9913
9914 cleanup:
9915 spin_lock_irq(&dev->event_lock);
9916 intel_crtc->unpin_work = NULL;
9917 spin_unlock_irq(&dev->event_lock);
9918
9919 drm_crtc_vblank_put(crtc);
9920 free_work:
9921 kfree(work);
9922
9923 if (ret == -EIO) {
9924 out_hang:
9925 ret = intel_plane_restore(primary);
9926 if (ret == 0 && event) {
9927 spin_lock_irq(&dev->event_lock);
9928 drm_send_vblank_event(dev, pipe, event);
9929 spin_unlock_irq(&dev->event_lock);
9930 }
9931 }
9932 return ret;
9933 }
9934
9935 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9936 .mode_set_base_atomic = intel_pipe_set_base_atomic,
9937 .load_lut = intel_crtc_load_lut,
9938 .atomic_begin = intel_begin_crtc_commit,
9939 .atomic_flush = intel_finish_crtc_commit,
9940 };
9941
9942 /**
9943 * intel_modeset_update_staged_output_state
9944 *
9945 * Updates the staged output configuration state, e.g. after we've read out the
9946 * current hw state.
9947 */
9948 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9949 {
9950 struct intel_crtc *crtc;
9951 struct intel_encoder *encoder;
9952 struct intel_connector *connector;
9953
9954 list_for_each_entry(connector, &dev->mode_config.connector_list,
9955 base.head) {
9956 connector->new_encoder =
9957 to_intel_encoder(connector->base.encoder);
9958 }
9959
9960 for_each_intel_encoder(dev, encoder) {
9961 encoder->new_crtc =
9962 to_intel_crtc(encoder->base.crtc);
9963 }
9964
9965 for_each_intel_crtc(dev, crtc) {
9966 crtc->new_enabled = crtc->base.enabled;
9967
9968 if (crtc->new_enabled)
9969 crtc->new_config = crtc->config;
9970 else
9971 crtc->new_config = NULL;
9972 }
9973 }
9974
9975 /**
9976 * intel_modeset_commit_output_state
9977 *
9978 * This function copies the stage display pipe configuration to the real one.
9979 */
9980 static void intel_modeset_commit_output_state(struct drm_device *dev)
9981 {
9982 struct intel_crtc *crtc;
9983 struct intel_encoder *encoder;
9984 struct intel_connector *connector;
9985
9986 list_for_each_entry(connector, &dev->mode_config.connector_list,
9987 base.head) {
9988 connector->base.encoder = &connector->new_encoder->base;
9989 }
9990
9991 for_each_intel_encoder(dev, encoder) {
9992 encoder->base.crtc = &encoder->new_crtc->base;
9993 }
9994
9995 for_each_intel_crtc(dev, crtc) {
9996 crtc->base.enabled = crtc->new_enabled;
9997 }
9998 }
9999
10000 static void
10001 connected_sink_compute_bpp(struct intel_connector *connector,
10002 struct intel_crtc_state *pipe_config)
10003 {
10004 int bpp = pipe_config->pipe_bpp;
10005
10006 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10007 connector->base.base.id,
10008 connector->base.name);
10009
10010 /* Don't use an invalid EDID bpc value */
10011 if (connector->base.display_info.bpc &&
10012 connector->base.display_info.bpc * 3 < bpp) {
10013 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10014 bpp, connector->base.display_info.bpc*3);
10015 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
10016 }
10017
10018 /* Clamp bpp to 8 on screens without EDID 1.4 */
10019 if (connector->base.display_info.bpc == 0 && bpp > 24) {
10020 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10021 bpp);
10022 pipe_config->pipe_bpp = 24;
10023 }
10024 }
10025
10026 static int
10027 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10028 struct drm_framebuffer *fb,
10029 struct intel_crtc_state *pipe_config)
10030 {
10031 struct drm_device *dev = crtc->base.dev;
10032 struct intel_connector *connector;
10033 int bpp;
10034
10035 switch (fb->pixel_format) {
10036 case DRM_FORMAT_C8:
10037 bpp = 8*3; /* since we go through a colormap */
10038 break;
10039 case DRM_FORMAT_XRGB1555:
10040 case DRM_FORMAT_ARGB1555:
10041 /* checked in intel_framebuffer_init already */
10042 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10043 return -EINVAL;
10044 case DRM_FORMAT_RGB565:
10045 bpp = 6*3; /* min is 18bpp */
10046 break;
10047 case DRM_FORMAT_XBGR8888:
10048 case DRM_FORMAT_ABGR8888:
10049 /* checked in intel_framebuffer_init already */
10050 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10051 return -EINVAL;
10052 case DRM_FORMAT_XRGB8888:
10053 case DRM_FORMAT_ARGB8888:
10054 bpp = 8*3;
10055 break;
10056 case DRM_FORMAT_XRGB2101010:
10057 case DRM_FORMAT_ARGB2101010:
10058 case DRM_FORMAT_XBGR2101010:
10059 case DRM_FORMAT_ABGR2101010:
10060 /* checked in intel_framebuffer_init already */
10061 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10062 return -EINVAL;
10063 bpp = 10*3;
10064 break;
10065 /* TODO: gen4+ supports 16 bpc floating point, too. */
10066 default:
10067 DRM_DEBUG_KMS("unsupported depth\n");
10068 return -EINVAL;
10069 }
10070
10071 pipe_config->pipe_bpp = bpp;
10072
10073 /* Clamp display bpp to EDID value */
10074 list_for_each_entry(connector, &dev->mode_config.connector_list,
10075 base.head) {
10076 if (!connector->new_encoder ||
10077 connector->new_encoder->new_crtc != crtc)
10078 continue;
10079
10080 connected_sink_compute_bpp(connector, pipe_config);
10081 }
10082
10083 return bpp;
10084 }
10085
10086 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10087 {
10088 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10089 "type: 0x%x flags: 0x%x\n",
10090 mode->crtc_clock,
10091 mode->crtc_hdisplay, mode->crtc_hsync_start,
10092 mode->crtc_hsync_end, mode->crtc_htotal,
10093 mode->crtc_vdisplay, mode->crtc_vsync_start,
10094 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10095 }
10096
10097 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10098 struct intel_crtc_state *pipe_config,
10099 const char *context)
10100 {
10101 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10102 context, pipe_name(crtc->pipe));
10103
10104 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10105 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10106 pipe_config->pipe_bpp, pipe_config->dither);
10107 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10108 pipe_config->has_pch_encoder,
10109 pipe_config->fdi_lanes,
10110 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10111 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10112 pipe_config->fdi_m_n.tu);
10113 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10114 pipe_config->has_dp_encoder,
10115 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10116 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10117 pipe_config->dp_m_n.tu);
10118
10119 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10120 pipe_config->has_dp_encoder,
10121 pipe_config->dp_m2_n2.gmch_m,
10122 pipe_config->dp_m2_n2.gmch_n,
10123 pipe_config->dp_m2_n2.link_m,
10124 pipe_config->dp_m2_n2.link_n,
10125 pipe_config->dp_m2_n2.tu);
10126
10127 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10128 pipe_config->has_audio,
10129 pipe_config->has_infoframe);
10130
10131 DRM_DEBUG_KMS("requested mode:\n");
10132 drm_mode_debug_printmodeline(&pipe_config->base.mode);
10133 DRM_DEBUG_KMS("adjusted mode:\n");
10134 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10135 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10136 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10137 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10138 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10139 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10140 pipe_config->gmch_pfit.control,
10141 pipe_config->gmch_pfit.pgm_ratios,
10142 pipe_config->gmch_pfit.lvds_border_bits);
10143 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10144 pipe_config->pch_pfit.pos,
10145 pipe_config->pch_pfit.size,
10146 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10147 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10148 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10149 }
10150
10151 static bool encoders_cloneable(const struct intel_encoder *a,
10152 const struct intel_encoder *b)
10153 {
10154 /* masks could be asymmetric, so check both ways */
10155 return a == b || (a->cloneable & (1 << b->type) &&
10156 b->cloneable & (1 << a->type));
10157 }
10158
10159 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10160 struct intel_encoder *encoder)
10161 {
10162 struct drm_device *dev = crtc->base.dev;
10163 struct intel_encoder *source_encoder;
10164
10165 for_each_intel_encoder(dev, source_encoder) {
10166 if (source_encoder->new_crtc != crtc)
10167 continue;
10168
10169 if (!encoders_cloneable(encoder, source_encoder))
10170 return false;
10171 }
10172
10173 return true;
10174 }
10175
10176 static bool check_encoder_cloning(struct intel_crtc *crtc)
10177 {
10178 struct drm_device *dev = crtc->base.dev;
10179 struct intel_encoder *encoder;
10180
10181 for_each_intel_encoder(dev, encoder) {
10182 if (encoder->new_crtc != crtc)
10183 continue;
10184
10185 if (!check_single_encoder_cloning(crtc, encoder))
10186 return false;
10187 }
10188
10189 return true;
10190 }
10191
10192 static bool check_digital_port_conflicts(struct drm_device *dev)
10193 {
10194 struct intel_connector *connector;
10195 unsigned int used_ports = 0;
10196
10197 /*
10198 * Walk the connector list instead of the encoder
10199 * list to detect the problem on ddi platforms
10200 * where there's just one encoder per digital port.
10201 */
10202 list_for_each_entry(connector,
10203 &dev->mode_config.connector_list, base.head) {
10204 struct intel_encoder *encoder = connector->new_encoder;
10205
10206 if (!encoder)
10207 continue;
10208
10209 WARN_ON(!encoder->new_crtc);
10210
10211 switch (encoder->type) {
10212 unsigned int port_mask;
10213 case INTEL_OUTPUT_UNKNOWN:
10214 if (WARN_ON(!HAS_DDI(dev)))
10215 break;
10216 case INTEL_OUTPUT_DISPLAYPORT:
10217 case INTEL_OUTPUT_HDMI:
10218 case INTEL_OUTPUT_EDP:
10219 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10220
10221 /* the same port mustn't appear more than once */
10222 if (used_ports & port_mask)
10223 return false;
10224
10225 used_ports |= port_mask;
10226 default:
10227 break;
10228 }
10229 }
10230
10231 return true;
10232 }
10233
10234 static struct intel_crtc_state *
10235 intel_modeset_pipe_config(struct drm_crtc *crtc,
10236 struct drm_framebuffer *fb,
10237 struct drm_display_mode *mode)
10238 {
10239 struct drm_device *dev = crtc->dev;
10240 struct intel_encoder *encoder;
10241 struct intel_crtc_state *pipe_config;
10242 int plane_bpp, ret = -EINVAL;
10243 bool retry = true;
10244
10245 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10246 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10247 return ERR_PTR(-EINVAL);
10248 }
10249
10250 if (!check_digital_port_conflicts(dev)) {
10251 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
10252 return ERR_PTR(-EINVAL);
10253 }
10254
10255 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10256 if (!pipe_config)
10257 return ERR_PTR(-ENOMEM);
10258
10259 drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
10260 drm_mode_copy(&pipe_config->base.mode, mode);
10261
10262 pipe_config->cpu_transcoder =
10263 (enum transcoder) to_intel_crtc(crtc)->pipe;
10264 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10265
10266 /*
10267 * Sanitize sync polarity flags based on requested ones. If neither
10268 * positive or negative polarity is requested, treat this as meaning
10269 * negative polarity.
10270 */
10271 if (!(pipe_config->base.adjusted_mode.flags &
10272 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10273 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10274
10275 if (!(pipe_config->base.adjusted_mode.flags &
10276 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10277 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10278
10279 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10280 * plane pixel format and any sink constraints into account. Returns the
10281 * source plane bpp so that dithering can be selected on mismatches
10282 * after encoders and crtc also have had their say. */
10283 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10284 fb, pipe_config);
10285 if (plane_bpp < 0)
10286 goto fail;
10287
10288 /*
10289 * Determine the real pipe dimensions. Note that stereo modes can
10290 * increase the actual pipe size due to the frame doubling and
10291 * insertion of additional space for blanks between the frame. This
10292 * is stored in the crtc timings. We use the requested mode to do this
10293 * computation to clearly distinguish it from the adjusted mode, which
10294 * can be changed by the connectors in the below retry loop.
10295 */
10296 drm_crtc_get_hv_timing(&pipe_config->base.mode,
10297 &pipe_config->pipe_src_w,
10298 &pipe_config->pipe_src_h);
10299
10300 encoder_retry:
10301 /* Ensure the port clock defaults are reset when retrying. */
10302 pipe_config->port_clock = 0;
10303 pipe_config->pixel_multiplier = 1;
10304
10305 /* Fill in default crtc timings, allow encoders to overwrite them. */
10306 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10307 CRTC_STEREO_DOUBLE);
10308
10309 /* Pass our mode to the connectors and the CRTC to give them a chance to
10310 * adjust it according to limitations or connector properties, and also
10311 * a chance to reject the mode entirely.
10312 */
10313 for_each_intel_encoder(dev, encoder) {
10314
10315 if (&encoder->new_crtc->base != crtc)
10316 continue;
10317
10318 if (!(encoder->compute_config(encoder, pipe_config))) {
10319 DRM_DEBUG_KMS("Encoder config failure\n");
10320 goto fail;
10321 }
10322 }
10323
10324 /* Set default port clock if not overwritten by the encoder. Needs to be
10325 * done afterwards in case the encoder adjusts the mode. */
10326 if (!pipe_config->port_clock)
10327 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
10328 * pipe_config->pixel_multiplier;
10329
10330 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10331 if (ret < 0) {
10332 DRM_DEBUG_KMS("CRTC fixup failed\n");
10333 goto fail;
10334 }
10335
10336 if (ret == RETRY) {
10337 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10338 ret = -EINVAL;
10339 goto fail;
10340 }
10341
10342 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10343 retry = false;
10344 goto encoder_retry;
10345 }
10346
10347 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10348 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10349 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10350
10351 return pipe_config;
10352 fail:
10353 kfree(pipe_config);
10354 return ERR_PTR(ret);
10355 }
10356
10357 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10358 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10359 static void
10360 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10361 unsigned *prepare_pipes, unsigned *disable_pipes)
10362 {
10363 struct intel_crtc *intel_crtc;
10364 struct drm_device *dev = crtc->dev;
10365 struct intel_encoder *encoder;
10366 struct intel_connector *connector;
10367 struct drm_crtc *tmp_crtc;
10368
10369 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10370
10371 /* Check which crtcs have changed outputs connected to them, these need
10372 * to be part of the prepare_pipes mask. We don't (yet) support global
10373 * modeset across multiple crtcs, so modeset_pipes will only have one
10374 * bit set at most. */
10375 list_for_each_entry(connector, &dev->mode_config.connector_list,
10376 base.head) {
10377 if (connector->base.encoder == &connector->new_encoder->base)
10378 continue;
10379
10380 if (connector->base.encoder) {
10381 tmp_crtc = connector->base.encoder->crtc;
10382
10383 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10384 }
10385
10386 if (connector->new_encoder)
10387 *prepare_pipes |=
10388 1 << connector->new_encoder->new_crtc->pipe;
10389 }
10390
10391 for_each_intel_encoder(dev, encoder) {
10392 if (encoder->base.crtc == &encoder->new_crtc->base)
10393 continue;
10394
10395 if (encoder->base.crtc) {
10396 tmp_crtc = encoder->base.crtc;
10397
10398 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10399 }
10400
10401 if (encoder->new_crtc)
10402 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10403 }
10404
10405 /* Check for pipes that will be enabled/disabled ... */
10406 for_each_intel_crtc(dev, intel_crtc) {
10407 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10408 continue;
10409
10410 if (!intel_crtc->new_enabled)
10411 *disable_pipes |= 1 << intel_crtc->pipe;
10412 else
10413 *prepare_pipes |= 1 << intel_crtc->pipe;
10414 }
10415
10416
10417 /* set_mode is also used to update properties on life display pipes. */
10418 intel_crtc = to_intel_crtc(crtc);
10419 if (intel_crtc->new_enabled)
10420 *prepare_pipes |= 1 << intel_crtc->pipe;
10421
10422 /*
10423 * For simplicity do a full modeset on any pipe where the output routing
10424 * changed. We could be more clever, but that would require us to be
10425 * more careful with calling the relevant encoder->mode_set functions.
10426 */
10427 if (*prepare_pipes)
10428 *modeset_pipes = *prepare_pipes;
10429
10430 /* ... and mask these out. */
10431 *modeset_pipes &= ~(*disable_pipes);
10432 *prepare_pipes &= ~(*disable_pipes);
10433
10434 /*
10435 * HACK: We don't (yet) fully support global modesets. intel_set_config
10436 * obies this rule, but the modeset restore mode of
10437 * intel_modeset_setup_hw_state does not.
10438 */
10439 *modeset_pipes &= 1 << intel_crtc->pipe;
10440 *prepare_pipes &= 1 << intel_crtc->pipe;
10441
10442 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10443 *modeset_pipes, *prepare_pipes, *disable_pipes);
10444 }
10445
10446 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10447 {
10448 struct drm_encoder *encoder;
10449 struct drm_device *dev = crtc->dev;
10450
10451 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10452 if (encoder->crtc == crtc)
10453 return true;
10454
10455 return false;
10456 }
10457
10458 static void
10459 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10460 {
10461 struct drm_i915_private *dev_priv = dev->dev_private;
10462 struct intel_encoder *intel_encoder;
10463 struct intel_crtc *intel_crtc;
10464 struct drm_connector *connector;
10465
10466 intel_shared_dpll_commit(dev_priv);
10467
10468 for_each_intel_encoder(dev, intel_encoder) {
10469 if (!intel_encoder->base.crtc)
10470 continue;
10471
10472 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10473
10474 if (prepare_pipes & (1 << intel_crtc->pipe))
10475 intel_encoder->connectors_active = false;
10476 }
10477
10478 intel_modeset_commit_output_state(dev);
10479
10480 /* Double check state. */
10481 for_each_intel_crtc(dev, intel_crtc) {
10482 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10483 WARN_ON(intel_crtc->new_config &&
10484 intel_crtc->new_config != intel_crtc->config);
10485 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10486 }
10487
10488 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10489 if (!connector->encoder || !connector->encoder->crtc)
10490 continue;
10491
10492 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10493
10494 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10495 struct drm_property *dpms_property =
10496 dev->mode_config.dpms_property;
10497
10498 connector->dpms = DRM_MODE_DPMS_ON;
10499 drm_object_property_set_value(&connector->base,
10500 dpms_property,
10501 DRM_MODE_DPMS_ON);
10502
10503 intel_encoder = to_intel_encoder(connector->encoder);
10504 intel_encoder->connectors_active = true;
10505 }
10506 }
10507
10508 }
10509
10510 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10511 {
10512 int diff;
10513
10514 if (clock1 == clock2)
10515 return true;
10516
10517 if (!clock1 || !clock2)
10518 return false;
10519
10520 diff = abs(clock1 - clock2);
10521
10522 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10523 return true;
10524
10525 return false;
10526 }
10527
10528 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10529 list_for_each_entry((intel_crtc), \
10530 &(dev)->mode_config.crtc_list, \
10531 base.head) \
10532 if (mask & (1 <<(intel_crtc)->pipe))
10533
10534 static bool
10535 intel_pipe_config_compare(struct drm_device *dev,
10536 struct intel_crtc_state *current_config,
10537 struct intel_crtc_state *pipe_config)
10538 {
10539 #define PIPE_CONF_CHECK_X(name) \
10540 if (current_config->name != pipe_config->name) { \
10541 DRM_ERROR("mismatch in " #name " " \
10542 "(expected 0x%08x, found 0x%08x)\n", \
10543 current_config->name, \
10544 pipe_config->name); \
10545 return false; \
10546 }
10547
10548 #define PIPE_CONF_CHECK_I(name) \
10549 if (current_config->name != pipe_config->name) { \
10550 DRM_ERROR("mismatch in " #name " " \
10551 "(expected %i, found %i)\n", \
10552 current_config->name, \
10553 pipe_config->name); \
10554 return false; \
10555 }
10556
10557 /* This is required for BDW+ where there is only one set of registers for
10558 * switching between high and low RR.
10559 * This macro can be used whenever a comparison has to be made between one
10560 * hw state and multiple sw state variables.
10561 */
10562 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10563 if ((current_config->name != pipe_config->name) && \
10564 (current_config->alt_name != pipe_config->name)) { \
10565 DRM_ERROR("mismatch in " #name " " \
10566 "(expected %i or %i, found %i)\n", \
10567 current_config->name, \
10568 current_config->alt_name, \
10569 pipe_config->name); \
10570 return false; \
10571 }
10572
10573 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10574 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10575 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10576 "(expected %i, found %i)\n", \
10577 current_config->name & (mask), \
10578 pipe_config->name & (mask)); \
10579 return false; \
10580 }
10581
10582 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10583 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10584 DRM_ERROR("mismatch in " #name " " \
10585 "(expected %i, found %i)\n", \
10586 current_config->name, \
10587 pipe_config->name); \
10588 return false; \
10589 }
10590
10591 #define PIPE_CONF_QUIRK(quirk) \
10592 ((current_config->quirks | pipe_config->quirks) & (quirk))
10593
10594 PIPE_CONF_CHECK_I(cpu_transcoder);
10595
10596 PIPE_CONF_CHECK_I(has_pch_encoder);
10597 PIPE_CONF_CHECK_I(fdi_lanes);
10598 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10599 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10600 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10601 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10602 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10603
10604 PIPE_CONF_CHECK_I(has_dp_encoder);
10605
10606 if (INTEL_INFO(dev)->gen < 8) {
10607 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10608 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10609 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10610 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10611 PIPE_CONF_CHECK_I(dp_m_n.tu);
10612
10613 if (current_config->has_drrs) {
10614 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10615 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10616 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10617 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10618 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10619 }
10620 } else {
10621 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10622 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10623 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10624 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10625 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10626 }
10627
10628 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
10629 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
10630 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
10631 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
10632 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
10633 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
10634
10635 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
10636 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
10637 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
10638 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
10639 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
10640 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
10641
10642 PIPE_CONF_CHECK_I(pixel_multiplier);
10643 PIPE_CONF_CHECK_I(has_hdmi_sink);
10644 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10645 IS_VALLEYVIEW(dev))
10646 PIPE_CONF_CHECK_I(limited_color_range);
10647 PIPE_CONF_CHECK_I(has_infoframe);
10648
10649 PIPE_CONF_CHECK_I(has_audio);
10650
10651 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10652 DRM_MODE_FLAG_INTERLACE);
10653
10654 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10655 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10656 DRM_MODE_FLAG_PHSYNC);
10657 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10658 DRM_MODE_FLAG_NHSYNC);
10659 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10660 DRM_MODE_FLAG_PVSYNC);
10661 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10662 DRM_MODE_FLAG_NVSYNC);
10663 }
10664
10665 PIPE_CONF_CHECK_I(pipe_src_w);
10666 PIPE_CONF_CHECK_I(pipe_src_h);
10667
10668 /*
10669 * FIXME: BIOS likes to set up a cloned config with lvds+external
10670 * screen. Since we don't yet re-compute the pipe config when moving
10671 * just the lvds port away to another pipe the sw tracking won't match.
10672 *
10673 * Proper atomic modesets with recomputed global state will fix this.
10674 * Until then just don't check gmch state for inherited modes.
10675 */
10676 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10677 PIPE_CONF_CHECK_I(gmch_pfit.control);
10678 /* pfit ratios are autocomputed by the hw on gen4+ */
10679 if (INTEL_INFO(dev)->gen < 4)
10680 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10681 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10682 }
10683
10684 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10685 if (current_config->pch_pfit.enabled) {
10686 PIPE_CONF_CHECK_I(pch_pfit.pos);
10687 PIPE_CONF_CHECK_I(pch_pfit.size);
10688 }
10689
10690 /* BDW+ don't expose a synchronous way to read the state */
10691 if (IS_HASWELL(dev))
10692 PIPE_CONF_CHECK_I(ips_enabled);
10693
10694 PIPE_CONF_CHECK_I(double_wide);
10695
10696 PIPE_CONF_CHECK_X(ddi_pll_sel);
10697
10698 PIPE_CONF_CHECK_I(shared_dpll);
10699 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10700 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10701 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10702 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10703 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10704 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
10705 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
10706 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
10707
10708 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10709 PIPE_CONF_CHECK_I(pipe_bpp);
10710
10711 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
10712 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10713
10714 #undef PIPE_CONF_CHECK_X
10715 #undef PIPE_CONF_CHECK_I
10716 #undef PIPE_CONF_CHECK_I_ALT
10717 #undef PIPE_CONF_CHECK_FLAGS
10718 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10719 #undef PIPE_CONF_QUIRK
10720
10721 return true;
10722 }
10723
10724 static void check_wm_state(struct drm_device *dev)
10725 {
10726 struct drm_i915_private *dev_priv = dev->dev_private;
10727 struct skl_ddb_allocation hw_ddb, *sw_ddb;
10728 struct intel_crtc *intel_crtc;
10729 int plane;
10730
10731 if (INTEL_INFO(dev)->gen < 9)
10732 return;
10733
10734 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
10735 sw_ddb = &dev_priv->wm.skl_hw.ddb;
10736
10737 for_each_intel_crtc(dev, intel_crtc) {
10738 struct skl_ddb_entry *hw_entry, *sw_entry;
10739 const enum pipe pipe = intel_crtc->pipe;
10740
10741 if (!intel_crtc->active)
10742 continue;
10743
10744 /* planes */
10745 for_each_plane(pipe, plane) {
10746 hw_entry = &hw_ddb.plane[pipe][plane];
10747 sw_entry = &sw_ddb->plane[pipe][plane];
10748
10749 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10750 continue;
10751
10752 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
10753 "(expected (%u,%u), found (%u,%u))\n",
10754 pipe_name(pipe), plane + 1,
10755 sw_entry->start, sw_entry->end,
10756 hw_entry->start, hw_entry->end);
10757 }
10758
10759 /* cursor */
10760 hw_entry = &hw_ddb.cursor[pipe];
10761 sw_entry = &sw_ddb->cursor[pipe];
10762
10763 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10764 continue;
10765
10766 DRM_ERROR("mismatch in DDB state pipe %c cursor "
10767 "(expected (%u,%u), found (%u,%u))\n",
10768 pipe_name(pipe),
10769 sw_entry->start, sw_entry->end,
10770 hw_entry->start, hw_entry->end);
10771 }
10772 }
10773
10774 static void
10775 check_connector_state(struct drm_device *dev)
10776 {
10777 struct intel_connector *connector;
10778
10779 list_for_each_entry(connector, &dev->mode_config.connector_list,
10780 base.head) {
10781 /* This also checks the encoder/connector hw state with the
10782 * ->get_hw_state callbacks. */
10783 intel_connector_check_state(connector);
10784
10785 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
10786 "connector's staged encoder doesn't match current encoder\n");
10787 }
10788 }
10789
10790 static void
10791 check_encoder_state(struct drm_device *dev)
10792 {
10793 struct intel_encoder *encoder;
10794 struct intel_connector *connector;
10795
10796 for_each_intel_encoder(dev, encoder) {
10797 bool enabled = false;
10798 bool active = false;
10799 enum pipe pipe, tracked_pipe;
10800
10801 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10802 encoder->base.base.id,
10803 encoder->base.name);
10804
10805 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
10806 "encoder's stage crtc doesn't match current crtc\n");
10807 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
10808 "encoder's active_connectors set, but no crtc\n");
10809
10810 list_for_each_entry(connector, &dev->mode_config.connector_list,
10811 base.head) {
10812 if (connector->base.encoder != &encoder->base)
10813 continue;
10814 enabled = true;
10815 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10816 active = true;
10817 }
10818 /*
10819 * for MST connectors if we unplug the connector is gone
10820 * away but the encoder is still connected to a crtc
10821 * until a modeset happens in response to the hotplug.
10822 */
10823 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10824 continue;
10825
10826 I915_STATE_WARN(!!encoder->base.crtc != enabled,
10827 "encoder's enabled state mismatch "
10828 "(expected %i, found %i)\n",
10829 !!encoder->base.crtc, enabled);
10830 I915_STATE_WARN(active && !encoder->base.crtc,
10831 "active encoder with no crtc\n");
10832
10833 I915_STATE_WARN(encoder->connectors_active != active,
10834 "encoder's computed active state doesn't match tracked active state "
10835 "(expected %i, found %i)\n", active, encoder->connectors_active);
10836
10837 active = encoder->get_hw_state(encoder, &pipe);
10838 I915_STATE_WARN(active != encoder->connectors_active,
10839 "encoder's hw state doesn't match sw tracking "
10840 "(expected %i, found %i)\n",
10841 encoder->connectors_active, active);
10842
10843 if (!encoder->base.crtc)
10844 continue;
10845
10846 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10847 I915_STATE_WARN(active && pipe != tracked_pipe,
10848 "active encoder's pipe doesn't match"
10849 "(expected %i, found %i)\n",
10850 tracked_pipe, pipe);
10851
10852 }
10853 }
10854
10855 static void
10856 check_crtc_state(struct drm_device *dev)
10857 {
10858 struct drm_i915_private *dev_priv = dev->dev_private;
10859 struct intel_crtc *crtc;
10860 struct intel_encoder *encoder;
10861 struct intel_crtc_state pipe_config;
10862
10863 for_each_intel_crtc(dev, crtc) {
10864 bool enabled = false;
10865 bool active = false;
10866
10867 memset(&pipe_config, 0, sizeof(pipe_config));
10868
10869 DRM_DEBUG_KMS("[CRTC:%d]\n",
10870 crtc->base.base.id);
10871
10872 I915_STATE_WARN(crtc->active && !crtc->base.enabled,
10873 "active crtc, but not enabled in sw tracking\n");
10874
10875 for_each_intel_encoder(dev, encoder) {
10876 if (encoder->base.crtc != &crtc->base)
10877 continue;
10878 enabled = true;
10879 if (encoder->connectors_active)
10880 active = true;
10881 }
10882
10883 I915_STATE_WARN(active != crtc->active,
10884 "crtc's computed active state doesn't match tracked active state "
10885 "(expected %i, found %i)\n", active, crtc->active);
10886 I915_STATE_WARN(enabled != crtc->base.enabled,
10887 "crtc's computed enabled state doesn't match tracked enabled state "
10888 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10889
10890 active = dev_priv->display.get_pipe_config(crtc,
10891 &pipe_config);
10892
10893 /* hw state is inconsistent with the pipe quirk */
10894 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10895 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
10896 active = crtc->active;
10897
10898 for_each_intel_encoder(dev, encoder) {
10899 enum pipe pipe;
10900 if (encoder->base.crtc != &crtc->base)
10901 continue;
10902 if (encoder->get_hw_state(encoder, &pipe))
10903 encoder->get_config(encoder, &pipe_config);
10904 }
10905
10906 I915_STATE_WARN(crtc->active != active,
10907 "crtc active state doesn't match with hw state "
10908 "(expected %i, found %i)\n", crtc->active, active);
10909
10910 if (active &&
10911 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
10912 I915_STATE_WARN(1, "pipe state doesn't match!\n");
10913 intel_dump_pipe_config(crtc, &pipe_config,
10914 "[hw state]");
10915 intel_dump_pipe_config(crtc, crtc->config,
10916 "[sw state]");
10917 }
10918 }
10919 }
10920
10921 static void
10922 check_shared_dpll_state(struct drm_device *dev)
10923 {
10924 struct drm_i915_private *dev_priv = dev->dev_private;
10925 struct intel_crtc *crtc;
10926 struct intel_dpll_hw_state dpll_hw_state;
10927 int i;
10928
10929 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10930 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10931 int enabled_crtcs = 0, active_crtcs = 0;
10932 bool active;
10933
10934 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10935
10936 DRM_DEBUG_KMS("%s\n", pll->name);
10937
10938 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10939
10940 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
10941 "more active pll users than references: %i vs %i\n",
10942 pll->active, hweight32(pll->config.crtc_mask));
10943 I915_STATE_WARN(pll->active && !pll->on,
10944 "pll in active use but not on in sw tracking\n");
10945 I915_STATE_WARN(pll->on && !pll->active,
10946 "pll in on but not on in use in sw tracking\n");
10947 I915_STATE_WARN(pll->on != active,
10948 "pll on state mismatch (expected %i, found %i)\n",
10949 pll->on, active);
10950
10951 for_each_intel_crtc(dev, crtc) {
10952 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10953 enabled_crtcs++;
10954 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10955 active_crtcs++;
10956 }
10957 I915_STATE_WARN(pll->active != active_crtcs,
10958 "pll active crtcs mismatch (expected %i, found %i)\n",
10959 pll->active, active_crtcs);
10960 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
10961 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10962 hweight32(pll->config.crtc_mask), enabled_crtcs);
10963
10964 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
10965 sizeof(dpll_hw_state)),
10966 "pll hw state mismatch\n");
10967 }
10968 }
10969
10970 void
10971 intel_modeset_check_state(struct drm_device *dev)
10972 {
10973 check_wm_state(dev);
10974 check_connector_state(dev);
10975 check_encoder_state(dev);
10976 check_crtc_state(dev);
10977 check_shared_dpll_state(dev);
10978 }
10979
10980 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
10981 int dotclock)
10982 {
10983 /*
10984 * FDI already provided one idea for the dotclock.
10985 * Yell if the encoder disagrees.
10986 */
10987 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
10988 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10989 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
10990 }
10991
10992 static void update_scanline_offset(struct intel_crtc *crtc)
10993 {
10994 struct drm_device *dev = crtc->base.dev;
10995
10996 /*
10997 * The scanline counter increments at the leading edge of hsync.
10998 *
10999 * On most platforms it starts counting from vtotal-1 on the
11000 * first active line. That means the scanline counter value is
11001 * always one less than what we would expect. Ie. just after
11002 * start of vblank, which also occurs at start of hsync (on the
11003 * last active line), the scanline counter will read vblank_start-1.
11004 *
11005 * On gen2 the scanline counter starts counting from 1 instead
11006 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11007 * to keep the value positive), instead of adding one.
11008 *
11009 * On HSW+ the behaviour of the scanline counter depends on the output
11010 * type. For DP ports it behaves like most other platforms, but on HDMI
11011 * there's an extra 1 line difference. So we need to add two instead of
11012 * one to the value.
11013 */
11014 if (IS_GEN2(dev)) {
11015 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
11016 int vtotal;
11017
11018 vtotal = mode->crtc_vtotal;
11019 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
11020 vtotal /= 2;
11021
11022 crtc->scanline_offset = vtotal - 1;
11023 } else if (HAS_DDI(dev) &&
11024 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
11025 crtc->scanline_offset = 2;
11026 } else
11027 crtc->scanline_offset = 1;
11028 }
11029
11030 static struct intel_crtc_state *
11031 intel_modeset_compute_config(struct drm_crtc *crtc,
11032 struct drm_display_mode *mode,
11033 struct drm_framebuffer *fb,
11034 unsigned *modeset_pipes,
11035 unsigned *prepare_pipes,
11036 unsigned *disable_pipes)
11037 {
11038 struct intel_crtc_state *pipe_config = NULL;
11039
11040 intel_modeset_affected_pipes(crtc, modeset_pipes,
11041 prepare_pipes, disable_pipes);
11042
11043 if ((*modeset_pipes) == 0)
11044 goto out;
11045
11046 /*
11047 * Note this needs changes when we start tracking multiple modes
11048 * and crtcs. At that point we'll need to compute the whole config
11049 * (i.e. one pipe_config for each crtc) rather than just the one
11050 * for this crtc.
11051 */
11052 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
11053 if (IS_ERR(pipe_config)) {
11054 goto out;
11055 }
11056 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11057 "[modeset]");
11058
11059 out:
11060 return pipe_config;
11061 }
11062
11063 static int __intel_set_mode_setup_plls(struct drm_device *dev,
11064 unsigned modeset_pipes,
11065 unsigned disable_pipes)
11066 {
11067 struct drm_i915_private *dev_priv = to_i915(dev);
11068 unsigned clear_pipes = modeset_pipes | disable_pipes;
11069 struct intel_crtc *intel_crtc;
11070 int ret = 0;
11071
11072 if (!dev_priv->display.crtc_compute_clock)
11073 return 0;
11074
11075 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
11076 if (ret)
11077 goto done;
11078
11079 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11080 struct intel_crtc_state *state = intel_crtc->new_config;
11081 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11082 state);
11083 if (ret) {
11084 intel_shared_dpll_abort_config(dev_priv);
11085 goto done;
11086 }
11087 }
11088
11089 done:
11090 return ret;
11091 }
11092
11093 static int __intel_set_mode(struct drm_crtc *crtc,
11094 struct drm_display_mode *mode,
11095 int x, int y, struct drm_framebuffer *fb,
11096 struct intel_crtc_state *pipe_config,
11097 unsigned modeset_pipes,
11098 unsigned prepare_pipes,
11099 unsigned disable_pipes)
11100 {
11101 struct drm_device *dev = crtc->dev;
11102 struct drm_i915_private *dev_priv = dev->dev_private;
11103 struct drm_display_mode *saved_mode;
11104 struct intel_crtc *intel_crtc;
11105 int ret = 0;
11106
11107 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
11108 if (!saved_mode)
11109 return -ENOMEM;
11110
11111 *saved_mode = crtc->mode;
11112
11113 if (modeset_pipes)
11114 to_intel_crtc(crtc)->new_config = pipe_config;
11115
11116 /*
11117 * See if the config requires any additional preparation, e.g.
11118 * to adjust global state with pipes off. We need to do this
11119 * here so we can get the modeset_pipe updated config for the new
11120 * mode set on this crtc. For other crtcs we need to use the
11121 * adjusted_mode bits in the crtc directly.
11122 */
11123 if (IS_VALLEYVIEW(dev)) {
11124 valleyview_modeset_global_pipes(dev, &prepare_pipes);
11125
11126 /* may have added more to prepare_pipes than we should */
11127 prepare_pipes &= ~disable_pipes;
11128 }
11129
11130 ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes);
11131 if (ret)
11132 goto done;
11133
11134 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
11135 intel_crtc_disable(&intel_crtc->base);
11136
11137 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11138 if (intel_crtc->base.enabled)
11139 dev_priv->display.crtc_disable(&intel_crtc->base);
11140 }
11141
11142 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11143 * to set it here already despite that we pass it down the callchain.
11144 *
11145 * Note we'll need to fix this up when we start tracking multiple
11146 * pipes; here we assume a single modeset_pipe and only track the
11147 * single crtc and mode.
11148 */
11149 if (modeset_pipes) {
11150 crtc->mode = *mode;
11151 /* mode_set/enable/disable functions rely on a correct pipe
11152 * config. */
11153 intel_crtc_set_state(to_intel_crtc(crtc), pipe_config);
11154
11155 /*
11156 * Calculate and store various constants which
11157 * are later needed by vblank and swap-completion
11158 * timestamping. They are derived from true hwmode.
11159 */
11160 drm_calc_timestamping_constants(crtc,
11161 &pipe_config->base.adjusted_mode);
11162 }
11163
11164 /* Only after disabling all output pipelines that will be changed can we
11165 * update the the output configuration. */
11166 intel_modeset_update_state(dev, prepare_pipes);
11167
11168 modeset_update_crtc_power_domains(dev);
11169
11170 /* Set up the DPLL and any encoders state that needs to adjust or depend
11171 * on the DPLL.
11172 */
11173 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11174 struct drm_plane *primary = intel_crtc->base.primary;
11175 int vdisplay, hdisplay;
11176
11177 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11178 ret = primary->funcs->update_plane(primary, &intel_crtc->base,
11179 fb, 0, 0,
11180 hdisplay, vdisplay,
11181 x << 16, y << 16,
11182 hdisplay << 16, vdisplay << 16);
11183 }
11184
11185 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11186 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11187 update_scanline_offset(intel_crtc);
11188
11189 dev_priv->display.crtc_enable(&intel_crtc->base);
11190 }
11191
11192 /* FIXME: add subpixel order */
11193 done:
11194 if (ret && crtc->enabled)
11195 crtc->mode = *saved_mode;
11196
11197 kfree(saved_mode);
11198 return ret;
11199 }
11200
11201 static int intel_set_mode_pipes(struct drm_crtc *crtc,
11202 struct drm_display_mode *mode,
11203 int x, int y, struct drm_framebuffer *fb,
11204 struct intel_crtc_state *pipe_config,
11205 unsigned modeset_pipes,
11206 unsigned prepare_pipes,
11207 unsigned disable_pipes)
11208 {
11209 int ret;
11210
11211 ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
11212 prepare_pipes, disable_pipes);
11213
11214 if (ret == 0)
11215 intel_modeset_check_state(crtc->dev);
11216
11217 return ret;
11218 }
11219
11220 static int intel_set_mode(struct drm_crtc *crtc,
11221 struct drm_display_mode *mode,
11222 int x, int y, struct drm_framebuffer *fb)
11223 {
11224 struct intel_crtc_state *pipe_config;
11225 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11226
11227 pipe_config = intel_modeset_compute_config(crtc, mode, fb,
11228 &modeset_pipes,
11229 &prepare_pipes,
11230 &disable_pipes);
11231
11232 if (IS_ERR(pipe_config))
11233 return PTR_ERR(pipe_config);
11234
11235 return intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
11236 modeset_pipes, prepare_pipes,
11237 disable_pipes);
11238 }
11239
11240 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11241 {
11242 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
11243 }
11244
11245 #undef for_each_intel_crtc_masked
11246
11247 static void intel_set_config_free(struct intel_set_config *config)
11248 {
11249 if (!config)
11250 return;
11251
11252 kfree(config->save_connector_encoders);
11253 kfree(config->save_encoder_crtcs);
11254 kfree(config->save_crtc_enabled);
11255 kfree(config);
11256 }
11257
11258 static int intel_set_config_save_state(struct drm_device *dev,
11259 struct intel_set_config *config)
11260 {
11261 struct drm_crtc *crtc;
11262 struct drm_encoder *encoder;
11263 struct drm_connector *connector;
11264 int count;
11265
11266 config->save_crtc_enabled =
11267 kcalloc(dev->mode_config.num_crtc,
11268 sizeof(bool), GFP_KERNEL);
11269 if (!config->save_crtc_enabled)
11270 return -ENOMEM;
11271
11272 config->save_encoder_crtcs =
11273 kcalloc(dev->mode_config.num_encoder,
11274 sizeof(struct drm_crtc *), GFP_KERNEL);
11275 if (!config->save_encoder_crtcs)
11276 return -ENOMEM;
11277
11278 config->save_connector_encoders =
11279 kcalloc(dev->mode_config.num_connector,
11280 sizeof(struct drm_encoder *), GFP_KERNEL);
11281 if (!config->save_connector_encoders)
11282 return -ENOMEM;
11283
11284 /* Copy data. Note that driver private data is not affected.
11285 * Should anything bad happen only the expected state is
11286 * restored, not the drivers personal bookkeeping.
11287 */
11288 count = 0;
11289 for_each_crtc(dev, crtc) {
11290 config->save_crtc_enabled[count++] = crtc->enabled;
11291 }
11292
11293 count = 0;
11294 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11295 config->save_encoder_crtcs[count++] = encoder->crtc;
11296 }
11297
11298 count = 0;
11299 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11300 config->save_connector_encoders[count++] = connector->encoder;
11301 }
11302
11303 return 0;
11304 }
11305
11306 static void intel_set_config_restore_state(struct drm_device *dev,
11307 struct intel_set_config *config)
11308 {
11309 struct intel_crtc *crtc;
11310 struct intel_encoder *encoder;
11311 struct intel_connector *connector;
11312 int count;
11313
11314 count = 0;
11315 for_each_intel_crtc(dev, crtc) {
11316 crtc->new_enabled = config->save_crtc_enabled[count++];
11317
11318 if (crtc->new_enabled)
11319 crtc->new_config = crtc->config;
11320 else
11321 crtc->new_config = NULL;
11322 }
11323
11324 count = 0;
11325 for_each_intel_encoder(dev, encoder) {
11326 encoder->new_crtc =
11327 to_intel_crtc(config->save_encoder_crtcs[count++]);
11328 }
11329
11330 count = 0;
11331 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11332 connector->new_encoder =
11333 to_intel_encoder(config->save_connector_encoders[count++]);
11334 }
11335 }
11336
11337 static bool
11338 is_crtc_connector_off(struct drm_mode_set *set)
11339 {
11340 int i;
11341
11342 if (set->num_connectors == 0)
11343 return false;
11344
11345 if (WARN_ON(set->connectors == NULL))
11346 return false;
11347
11348 for (i = 0; i < set->num_connectors; i++)
11349 if (set->connectors[i]->encoder &&
11350 set->connectors[i]->encoder->crtc == set->crtc &&
11351 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11352 return true;
11353
11354 return false;
11355 }
11356
11357 static void
11358 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11359 struct intel_set_config *config)
11360 {
11361
11362 /* We should be able to check here if the fb has the same properties
11363 * and then just flip_or_move it */
11364 if (is_crtc_connector_off(set)) {
11365 config->mode_changed = true;
11366 } else if (set->crtc->primary->fb != set->fb) {
11367 /*
11368 * If we have no fb, we can only flip as long as the crtc is
11369 * active, otherwise we need a full mode set. The crtc may
11370 * be active if we've only disabled the primary plane, or
11371 * in fastboot situations.
11372 */
11373 if (set->crtc->primary->fb == NULL) {
11374 struct intel_crtc *intel_crtc =
11375 to_intel_crtc(set->crtc);
11376
11377 if (intel_crtc->active) {
11378 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11379 config->fb_changed = true;
11380 } else {
11381 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11382 config->mode_changed = true;
11383 }
11384 } else if (set->fb == NULL) {
11385 config->mode_changed = true;
11386 } else if (set->fb->pixel_format !=
11387 set->crtc->primary->fb->pixel_format) {
11388 config->mode_changed = true;
11389 } else {
11390 config->fb_changed = true;
11391 }
11392 }
11393
11394 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11395 config->fb_changed = true;
11396
11397 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11398 DRM_DEBUG_KMS("modes are different, full mode set\n");
11399 drm_mode_debug_printmodeline(&set->crtc->mode);
11400 drm_mode_debug_printmodeline(set->mode);
11401 config->mode_changed = true;
11402 }
11403
11404 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11405 set->crtc->base.id, config->mode_changed, config->fb_changed);
11406 }
11407
11408 static int
11409 intel_modeset_stage_output_state(struct drm_device *dev,
11410 struct drm_mode_set *set,
11411 struct intel_set_config *config)
11412 {
11413 struct intel_connector *connector;
11414 struct intel_encoder *encoder;
11415 struct intel_crtc *crtc;
11416 int ro;
11417
11418 /* The upper layers ensure that we either disable a crtc or have a list
11419 * of connectors. For paranoia, double-check this. */
11420 WARN_ON(!set->fb && (set->num_connectors != 0));
11421 WARN_ON(set->fb && (set->num_connectors == 0));
11422
11423 list_for_each_entry(connector, &dev->mode_config.connector_list,
11424 base.head) {
11425 /* Otherwise traverse passed in connector list and get encoders
11426 * for them. */
11427 for (ro = 0; ro < set->num_connectors; ro++) {
11428 if (set->connectors[ro] == &connector->base) {
11429 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11430 break;
11431 }
11432 }
11433
11434 /* If we disable the crtc, disable all its connectors. Also, if
11435 * the connector is on the changing crtc but not on the new
11436 * connector list, disable it. */
11437 if ((!set->fb || ro == set->num_connectors) &&
11438 connector->base.encoder &&
11439 connector->base.encoder->crtc == set->crtc) {
11440 connector->new_encoder = NULL;
11441
11442 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11443 connector->base.base.id,
11444 connector->base.name);
11445 }
11446
11447
11448 if (&connector->new_encoder->base != connector->base.encoder) {
11449 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11450 config->mode_changed = true;
11451 }
11452 }
11453 /* connector->new_encoder is now updated for all connectors. */
11454
11455 /* Update crtc of enabled connectors. */
11456 list_for_each_entry(connector, &dev->mode_config.connector_list,
11457 base.head) {
11458 struct drm_crtc *new_crtc;
11459
11460 if (!connector->new_encoder)
11461 continue;
11462
11463 new_crtc = connector->new_encoder->base.crtc;
11464
11465 for (ro = 0; ro < set->num_connectors; ro++) {
11466 if (set->connectors[ro] == &connector->base)
11467 new_crtc = set->crtc;
11468 }
11469
11470 /* Make sure the new CRTC will work with the encoder */
11471 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11472 new_crtc)) {
11473 return -EINVAL;
11474 }
11475 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11476
11477 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11478 connector->base.base.id,
11479 connector->base.name,
11480 new_crtc->base.id);
11481 }
11482
11483 /* Check for any encoders that needs to be disabled. */
11484 for_each_intel_encoder(dev, encoder) {
11485 int num_connectors = 0;
11486 list_for_each_entry(connector,
11487 &dev->mode_config.connector_list,
11488 base.head) {
11489 if (connector->new_encoder == encoder) {
11490 WARN_ON(!connector->new_encoder->new_crtc);
11491 num_connectors++;
11492 }
11493 }
11494
11495 if (num_connectors == 0)
11496 encoder->new_crtc = NULL;
11497 else if (num_connectors > 1)
11498 return -EINVAL;
11499
11500 /* Only now check for crtc changes so we don't miss encoders
11501 * that will be disabled. */
11502 if (&encoder->new_crtc->base != encoder->base.crtc) {
11503 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11504 config->mode_changed = true;
11505 }
11506 }
11507 /* Now we've also updated encoder->new_crtc for all encoders. */
11508 list_for_each_entry(connector, &dev->mode_config.connector_list,
11509 base.head) {
11510 if (connector->new_encoder)
11511 if (connector->new_encoder != connector->encoder)
11512 connector->encoder = connector->new_encoder;
11513 }
11514 for_each_intel_crtc(dev, crtc) {
11515 crtc->new_enabled = false;
11516
11517 for_each_intel_encoder(dev, encoder) {
11518 if (encoder->new_crtc == crtc) {
11519 crtc->new_enabled = true;
11520 break;
11521 }
11522 }
11523
11524 if (crtc->new_enabled != crtc->base.enabled) {
11525 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11526 crtc->new_enabled ? "en" : "dis");
11527 config->mode_changed = true;
11528 }
11529
11530 if (crtc->new_enabled)
11531 crtc->new_config = crtc->config;
11532 else
11533 crtc->new_config = NULL;
11534 }
11535
11536 return 0;
11537 }
11538
11539 static void disable_crtc_nofb(struct intel_crtc *crtc)
11540 {
11541 struct drm_device *dev = crtc->base.dev;
11542 struct intel_encoder *encoder;
11543 struct intel_connector *connector;
11544
11545 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11546 pipe_name(crtc->pipe));
11547
11548 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11549 if (connector->new_encoder &&
11550 connector->new_encoder->new_crtc == crtc)
11551 connector->new_encoder = NULL;
11552 }
11553
11554 for_each_intel_encoder(dev, encoder) {
11555 if (encoder->new_crtc == crtc)
11556 encoder->new_crtc = NULL;
11557 }
11558
11559 crtc->new_enabled = false;
11560 crtc->new_config = NULL;
11561 }
11562
11563 static int intel_crtc_set_config(struct drm_mode_set *set)
11564 {
11565 struct drm_device *dev;
11566 struct drm_mode_set save_set;
11567 struct intel_set_config *config;
11568 struct intel_crtc_state *pipe_config;
11569 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11570 int ret;
11571
11572 BUG_ON(!set);
11573 BUG_ON(!set->crtc);
11574 BUG_ON(!set->crtc->helper_private);
11575
11576 /* Enforce sane interface api - has been abused by the fb helper. */
11577 BUG_ON(!set->mode && set->fb);
11578 BUG_ON(set->fb && set->num_connectors == 0);
11579
11580 if (set->fb) {
11581 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11582 set->crtc->base.id, set->fb->base.id,
11583 (int)set->num_connectors, set->x, set->y);
11584 } else {
11585 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11586 }
11587
11588 dev = set->crtc->dev;
11589
11590 ret = -ENOMEM;
11591 config = kzalloc(sizeof(*config), GFP_KERNEL);
11592 if (!config)
11593 goto out_config;
11594
11595 ret = intel_set_config_save_state(dev, config);
11596 if (ret)
11597 goto out_config;
11598
11599 save_set.crtc = set->crtc;
11600 save_set.mode = &set->crtc->mode;
11601 save_set.x = set->crtc->x;
11602 save_set.y = set->crtc->y;
11603 save_set.fb = set->crtc->primary->fb;
11604
11605 /* Compute whether we need a full modeset, only an fb base update or no
11606 * change at all. In the future we might also check whether only the
11607 * mode changed, e.g. for LVDS where we only change the panel fitter in
11608 * such cases. */
11609 intel_set_config_compute_mode_changes(set, config);
11610
11611 ret = intel_modeset_stage_output_state(dev, set, config);
11612 if (ret)
11613 goto fail;
11614
11615 pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
11616 set->fb,
11617 &modeset_pipes,
11618 &prepare_pipes,
11619 &disable_pipes);
11620 if (IS_ERR(pipe_config)) {
11621 ret = PTR_ERR(pipe_config);
11622 goto fail;
11623 } else if (pipe_config) {
11624 if (pipe_config->has_audio !=
11625 to_intel_crtc(set->crtc)->config->has_audio)
11626 config->mode_changed = true;
11627
11628 /*
11629 * Note we have an issue here with infoframes: current code
11630 * only updates them on the full mode set path per hw
11631 * requirements. So here we should be checking for any
11632 * required changes and forcing a mode set.
11633 */
11634 }
11635
11636 /* set_mode will free it in the mode_changed case */
11637 if (!config->mode_changed)
11638 kfree(pipe_config);
11639
11640 intel_update_pipe_size(to_intel_crtc(set->crtc));
11641
11642 if (config->mode_changed) {
11643 ret = intel_set_mode_pipes(set->crtc, set->mode,
11644 set->x, set->y, set->fb, pipe_config,
11645 modeset_pipes, prepare_pipes,
11646 disable_pipes);
11647 } else if (config->fb_changed) {
11648 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11649 struct drm_plane *primary = set->crtc->primary;
11650 int vdisplay, hdisplay;
11651
11652 drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay);
11653 ret = primary->funcs->update_plane(primary, set->crtc, set->fb,
11654 0, 0, hdisplay, vdisplay,
11655 set->x << 16, set->y << 16,
11656 hdisplay << 16, vdisplay << 16);
11657
11658 /*
11659 * We need to make sure the primary plane is re-enabled if it
11660 * has previously been turned off.
11661 */
11662 if (!intel_crtc->primary_enabled && ret == 0) {
11663 WARN_ON(!intel_crtc->active);
11664 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11665 }
11666
11667 /*
11668 * In the fastboot case this may be our only check of the
11669 * state after boot. It would be better to only do it on
11670 * the first update, but we don't have a nice way of doing that
11671 * (and really, set_config isn't used much for high freq page
11672 * flipping, so increasing its cost here shouldn't be a big
11673 * deal).
11674 */
11675 if (i915.fastboot && ret == 0)
11676 intel_modeset_check_state(set->crtc->dev);
11677 }
11678
11679 if (ret) {
11680 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11681 set->crtc->base.id, ret);
11682 fail:
11683 intel_set_config_restore_state(dev, config);
11684
11685 /*
11686 * HACK: if the pipe was on, but we didn't have a framebuffer,
11687 * force the pipe off to avoid oopsing in the modeset code
11688 * due to fb==NULL. This should only happen during boot since
11689 * we don't yet reconstruct the FB from the hardware state.
11690 */
11691 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11692 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11693
11694 /* Try to restore the config */
11695 if (config->mode_changed &&
11696 intel_set_mode(save_set.crtc, save_set.mode,
11697 save_set.x, save_set.y, save_set.fb))
11698 DRM_ERROR("failed to restore config after modeset failure\n");
11699 }
11700
11701 out_config:
11702 intel_set_config_free(config);
11703 return ret;
11704 }
11705
11706 static const struct drm_crtc_funcs intel_crtc_funcs = {
11707 .gamma_set = intel_crtc_gamma_set,
11708 .set_config = intel_crtc_set_config,
11709 .destroy = intel_crtc_destroy,
11710 .page_flip = intel_crtc_page_flip,
11711 .atomic_duplicate_state = intel_crtc_duplicate_state,
11712 .atomic_destroy_state = intel_crtc_destroy_state,
11713 };
11714
11715 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11716 struct intel_shared_dpll *pll,
11717 struct intel_dpll_hw_state *hw_state)
11718 {
11719 uint32_t val;
11720
11721 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
11722 return false;
11723
11724 val = I915_READ(PCH_DPLL(pll->id));
11725 hw_state->dpll = val;
11726 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11727 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11728
11729 return val & DPLL_VCO_ENABLE;
11730 }
11731
11732 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11733 struct intel_shared_dpll *pll)
11734 {
11735 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
11736 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
11737 }
11738
11739 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11740 struct intel_shared_dpll *pll)
11741 {
11742 /* PCH refclock must be enabled first */
11743 ibx_assert_pch_refclk_enabled(dev_priv);
11744
11745 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11746
11747 /* Wait for the clocks to stabilize. */
11748 POSTING_READ(PCH_DPLL(pll->id));
11749 udelay(150);
11750
11751 /* The pixel multiplier can only be updated once the
11752 * DPLL is enabled and the clocks are stable.
11753 *
11754 * So write it again.
11755 */
11756 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11757 POSTING_READ(PCH_DPLL(pll->id));
11758 udelay(200);
11759 }
11760
11761 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11762 struct intel_shared_dpll *pll)
11763 {
11764 struct drm_device *dev = dev_priv->dev;
11765 struct intel_crtc *crtc;
11766
11767 /* Make sure no transcoder isn't still depending on us. */
11768 for_each_intel_crtc(dev, crtc) {
11769 if (intel_crtc_to_shared_dpll(crtc) == pll)
11770 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11771 }
11772
11773 I915_WRITE(PCH_DPLL(pll->id), 0);
11774 POSTING_READ(PCH_DPLL(pll->id));
11775 udelay(200);
11776 }
11777
11778 static char *ibx_pch_dpll_names[] = {
11779 "PCH DPLL A",
11780 "PCH DPLL B",
11781 };
11782
11783 static void ibx_pch_dpll_init(struct drm_device *dev)
11784 {
11785 struct drm_i915_private *dev_priv = dev->dev_private;
11786 int i;
11787
11788 dev_priv->num_shared_dpll = 2;
11789
11790 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11791 dev_priv->shared_dplls[i].id = i;
11792 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11793 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11794 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11795 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11796 dev_priv->shared_dplls[i].get_hw_state =
11797 ibx_pch_dpll_get_hw_state;
11798 }
11799 }
11800
11801 static void intel_shared_dpll_init(struct drm_device *dev)
11802 {
11803 struct drm_i915_private *dev_priv = dev->dev_private;
11804
11805 if (HAS_DDI(dev))
11806 intel_ddi_pll_init(dev);
11807 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11808 ibx_pch_dpll_init(dev);
11809 else
11810 dev_priv->num_shared_dpll = 0;
11811
11812 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11813 }
11814
11815 /**
11816 * intel_prepare_plane_fb - Prepare fb for usage on plane
11817 * @plane: drm plane to prepare for
11818 * @fb: framebuffer to prepare for presentation
11819 *
11820 * Prepares a framebuffer for usage on a display plane. Generally this
11821 * involves pinning the underlying object and updating the frontbuffer tracking
11822 * bits. Some older platforms need special physical address handling for
11823 * cursor planes.
11824 *
11825 * Returns 0 on success, negative error code on failure.
11826 */
11827 int
11828 intel_prepare_plane_fb(struct drm_plane *plane,
11829 struct drm_framebuffer *fb)
11830 {
11831 struct drm_device *dev = plane->dev;
11832 struct intel_plane *intel_plane = to_intel_plane(plane);
11833 enum pipe pipe = intel_plane->pipe;
11834 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11835 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11836 unsigned frontbuffer_bits = 0;
11837 int ret = 0;
11838
11839 if (!obj)
11840 return 0;
11841
11842 switch (plane->type) {
11843 case DRM_PLANE_TYPE_PRIMARY:
11844 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
11845 break;
11846 case DRM_PLANE_TYPE_CURSOR:
11847 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
11848 break;
11849 case DRM_PLANE_TYPE_OVERLAY:
11850 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
11851 break;
11852 }
11853
11854 mutex_lock(&dev->struct_mutex);
11855
11856 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
11857 INTEL_INFO(dev)->cursor_needs_physical) {
11858 int align = IS_I830(dev) ? 16 * 1024 : 256;
11859 ret = i915_gem_object_attach_phys(obj, align);
11860 if (ret)
11861 DRM_DEBUG_KMS("failed to attach phys object\n");
11862 } else {
11863 ret = intel_pin_and_fence_fb_obj(plane, fb, NULL);
11864 }
11865
11866 if (ret == 0)
11867 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
11868
11869 mutex_unlock(&dev->struct_mutex);
11870
11871 return ret;
11872 }
11873
11874 /**
11875 * intel_cleanup_plane_fb - Cleans up an fb after plane use
11876 * @plane: drm plane to clean up for
11877 * @fb: old framebuffer that was on plane
11878 *
11879 * Cleans up a framebuffer that has just been removed from a plane.
11880 */
11881 void
11882 intel_cleanup_plane_fb(struct drm_plane *plane,
11883 struct drm_framebuffer *fb)
11884 {
11885 struct drm_device *dev = plane->dev;
11886 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11887
11888 if (WARN_ON(!obj))
11889 return;
11890
11891 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
11892 !INTEL_INFO(dev)->cursor_needs_physical) {
11893 mutex_lock(&dev->struct_mutex);
11894 intel_unpin_fb_obj(obj);
11895 mutex_unlock(&dev->struct_mutex);
11896 }
11897 }
11898
11899 static int
11900 intel_check_primary_plane(struct drm_plane *plane,
11901 struct intel_plane_state *state)
11902 {
11903 struct drm_device *dev = plane->dev;
11904 struct drm_i915_private *dev_priv = dev->dev_private;
11905 struct drm_crtc *crtc = state->base.crtc;
11906 struct intel_crtc *intel_crtc;
11907 struct drm_framebuffer *fb = state->base.fb;
11908 struct drm_rect *dest = &state->dst;
11909 struct drm_rect *src = &state->src;
11910 const struct drm_rect *clip = &state->clip;
11911 int ret;
11912
11913 crtc = crtc ? crtc : plane->crtc;
11914 intel_crtc = to_intel_crtc(crtc);
11915
11916 ret = drm_plane_helper_check_update(plane, crtc, fb,
11917 src, dest, clip,
11918 DRM_PLANE_HELPER_NO_SCALING,
11919 DRM_PLANE_HELPER_NO_SCALING,
11920 false, true, &state->visible);
11921 if (ret)
11922 return ret;
11923
11924 if (intel_crtc->active) {
11925 intel_crtc->atomic.wait_for_flips = true;
11926
11927 /*
11928 * FBC does not work on some platforms for rotated
11929 * planes, so disable it when rotation is not 0 and
11930 * update it when rotation is set back to 0.
11931 *
11932 * FIXME: This is redundant with the fbc update done in
11933 * the primary plane enable function except that that
11934 * one is done too late. We eventually need to unify
11935 * this.
11936 */
11937 if (intel_crtc->primary_enabled &&
11938 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11939 dev_priv->fbc.plane == intel_crtc->plane &&
11940 state->base.rotation != BIT(DRM_ROTATE_0)) {
11941 intel_crtc->atomic.disable_fbc = true;
11942 }
11943
11944 if (state->visible) {
11945 /*
11946 * BDW signals flip done immediately if the plane
11947 * is disabled, even if the plane enable is already
11948 * armed to occur at the next vblank :(
11949 */
11950 if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled)
11951 intel_crtc->atomic.wait_vblank = true;
11952 }
11953
11954 intel_crtc->atomic.fb_bits |=
11955 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
11956
11957 intel_crtc->atomic.update_fbc = true;
11958 }
11959
11960 return 0;
11961 }
11962
11963 static void
11964 intel_commit_primary_plane(struct drm_plane *plane,
11965 struct intel_plane_state *state)
11966 {
11967 struct drm_crtc *crtc = state->base.crtc;
11968 struct drm_framebuffer *fb = state->base.fb;
11969 struct drm_device *dev = plane->dev;
11970 struct drm_i915_private *dev_priv = dev->dev_private;
11971 struct intel_crtc *intel_crtc;
11972 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11973 struct intel_plane *intel_plane = to_intel_plane(plane);
11974 struct drm_rect *src = &state->src;
11975
11976 crtc = crtc ? crtc : plane->crtc;
11977 intel_crtc = to_intel_crtc(crtc);
11978
11979 plane->fb = fb;
11980 crtc->x = src->x1 >> 16;
11981 crtc->y = src->y1 >> 16;
11982
11983 intel_plane->obj = obj;
11984
11985 if (intel_crtc->active) {
11986 if (state->visible) {
11987 /* FIXME: kill this fastboot hack */
11988 intel_update_pipe_size(intel_crtc);
11989
11990 intel_crtc->primary_enabled = true;
11991
11992 dev_priv->display.update_primary_plane(crtc, plane->fb,
11993 crtc->x, crtc->y);
11994 } else {
11995 /*
11996 * If clipping results in a non-visible primary plane,
11997 * we'll disable the primary plane. Note that this is
11998 * a bit different than what happens if userspace
11999 * explicitly disables the plane by passing fb=0
12000 * because plane->fb still gets set and pinned.
12001 */
12002 intel_disable_primary_hw_plane(plane, crtc);
12003 }
12004 }
12005 }
12006
12007 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
12008 {
12009 struct drm_device *dev = crtc->dev;
12010 struct drm_i915_private *dev_priv = dev->dev_private;
12011 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12012 struct intel_plane *intel_plane;
12013 struct drm_plane *p;
12014 unsigned fb_bits = 0;
12015
12016 /* Track fb's for any planes being disabled */
12017 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
12018 intel_plane = to_intel_plane(p);
12019
12020 if (intel_crtc->atomic.disabled_planes &
12021 (1 << drm_plane_index(p))) {
12022 switch (p->type) {
12023 case DRM_PLANE_TYPE_PRIMARY:
12024 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
12025 break;
12026 case DRM_PLANE_TYPE_CURSOR:
12027 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
12028 break;
12029 case DRM_PLANE_TYPE_OVERLAY:
12030 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
12031 break;
12032 }
12033
12034 mutex_lock(&dev->struct_mutex);
12035 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
12036 mutex_unlock(&dev->struct_mutex);
12037 }
12038 }
12039
12040 if (intel_crtc->atomic.wait_for_flips)
12041 intel_crtc_wait_for_pending_flips(crtc);
12042
12043 if (intel_crtc->atomic.disable_fbc)
12044 intel_fbc_disable(dev);
12045
12046 if (intel_crtc->atomic.pre_disable_primary)
12047 intel_pre_disable_primary(crtc);
12048
12049 if (intel_crtc->atomic.update_wm)
12050 intel_update_watermarks(crtc);
12051
12052 intel_runtime_pm_get(dev_priv);
12053
12054 /* Perform vblank evasion around commit operation */
12055 if (intel_crtc->active)
12056 intel_crtc->atomic.evade =
12057 intel_pipe_update_start(intel_crtc,
12058 &intel_crtc->atomic.start_vbl_count);
12059 }
12060
12061 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
12062 {
12063 struct drm_device *dev = crtc->dev;
12064 struct drm_i915_private *dev_priv = dev->dev_private;
12065 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12066 struct drm_plane *p;
12067
12068 if (intel_crtc->atomic.evade)
12069 intel_pipe_update_end(intel_crtc,
12070 intel_crtc->atomic.start_vbl_count);
12071
12072 intel_runtime_pm_put(dev_priv);
12073
12074 if (intel_crtc->atomic.wait_vblank)
12075 intel_wait_for_vblank(dev, intel_crtc->pipe);
12076
12077 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
12078
12079 if (intel_crtc->atomic.update_fbc) {
12080 mutex_lock(&dev->struct_mutex);
12081 intel_fbc_update(dev);
12082 mutex_unlock(&dev->struct_mutex);
12083 }
12084
12085 if (intel_crtc->atomic.post_enable_primary)
12086 intel_post_enable_primary(crtc);
12087
12088 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
12089 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
12090 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
12091 false, false);
12092
12093 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
12094 }
12095
12096 /**
12097 * intel_plane_destroy - destroy a plane
12098 * @plane: plane to destroy
12099 *
12100 * Common destruction function for all types of planes (primary, cursor,
12101 * sprite).
12102 */
12103 void intel_plane_destroy(struct drm_plane *plane)
12104 {
12105 struct intel_plane *intel_plane = to_intel_plane(plane);
12106 drm_plane_cleanup(plane);
12107 kfree(intel_plane);
12108 }
12109
12110 const struct drm_plane_funcs intel_plane_funcs = {
12111 .update_plane = drm_plane_helper_update,
12112 .disable_plane = drm_plane_helper_disable,
12113 .destroy = intel_plane_destroy,
12114 .set_property = drm_atomic_helper_plane_set_property,
12115 .atomic_get_property = intel_plane_atomic_get_property,
12116 .atomic_set_property = intel_plane_atomic_set_property,
12117 .atomic_duplicate_state = intel_plane_duplicate_state,
12118 .atomic_destroy_state = intel_plane_destroy_state,
12119
12120 };
12121
12122 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
12123 int pipe)
12124 {
12125 struct intel_plane *primary;
12126 struct intel_plane_state *state;
12127 const uint32_t *intel_primary_formats;
12128 int num_formats;
12129
12130 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
12131 if (primary == NULL)
12132 return NULL;
12133
12134 state = intel_create_plane_state(&primary->base);
12135 if (!state) {
12136 kfree(primary);
12137 return NULL;
12138 }
12139 primary->base.state = &state->base;
12140
12141 primary->can_scale = false;
12142 primary->max_downscale = 1;
12143 primary->pipe = pipe;
12144 primary->plane = pipe;
12145 primary->check_plane = intel_check_primary_plane;
12146 primary->commit_plane = intel_commit_primary_plane;
12147 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
12148 primary->plane = !pipe;
12149
12150 if (INTEL_INFO(dev)->gen <= 3) {
12151 intel_primary_formats = intel_primary_formats_gen2;
12152 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
12153 } else {
12154 intel_primary_formats = intel_primary_formats_gen4;
12155 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
12156 }
12157
12158 drm_universal_plane_init(dev, &primary->base, 0,
12159 &intel_plane_funcs,
12160 intel_primary_formats, num_formats,
12161 DRM_PLANE_TYPE_PRIMARY);
12162
12163 if (INTEL_INFO(dev)->gen >= 4) {
12164 if (!dev->mode_config.rotation_property)
12165 dev->mode_config.rotation_property =
12166 drm_mode_create_rotation_property(dev,
12167 BIT(DRM_ROTATE_0) |
12168 BIT(DRM_ROTATE_180));
12169 if (dev->mode_config.rotation_property)
12170 drm_object_attach_property(&primary->base.base,
12171 dev->mode_config.rotation_property,
12172 state->base.rotation);
12173 }
12174
12175 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
12176
12177 return &primary->base;
12178 }
12179
12180 static int
12181 intel_check_cursor_plane(struct drm_plane *plane,
12182 struct intel_plane_state *state)
12183 {
12184 struct drm_crtc *crtc = state->base.crtc;
12185 struct drm_device *dev = plane->dev;
12186 struct drm_framebuffer *fb = state->base.fb;
12187 struct drm_rect *dest = &state->dst;
12188 struct drm_rect *src = &state->src;
12189 const struct drm_rect *clip = &state->clip;
12190 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12191 struct intel_crtc *intel_crtc;
12192 unsigned stride;
12193 int ret;
12194
12195 crtc = crtc ? crtc : plane->crtc;
12196 intel_crtc = to_intel_crtc(crtc);
12197
12198 ret = drm_plane_helper_check_update(plane, crtc, fb,
12199 src, dest, clip,
12200 DRM_PLANE_HELPER_NO_SCALING,
12201 DRM_PLANE_HELPER_NO_SCALING,
12202 true, true, &state->visible);
12203 if (ret)
12204 return ret;
12205
12206
12207 /* if we want to turn off the cursor ignore width and height */
12208 if (!obj)
12209 goto finish;
12210
12211 /* Check for which cursor types we support */
12212 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
12213 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
12214 state->base.crtc_w, state->base.crtc_h);
12215 return -EINVAL;
12216 }
12217
12218 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
12219 if (obj->base.size < stride * state->base.crtc_h) {
12220 DRM_DEBUG_KMS("buffer is too small\n");
12221 return -ENOMEM;
12222 }
12223
12224 /* we only need to pin inside GTT if cursor is non-phy */
12225 mutex_lock(&dev->struct_mutex);
12226 if (!INTEL_INFO(dev)->cursor_needs_physical && obj->tiling_mode) {
12227 DRM_DEBUG_KMS("cursor cannot be tiled\n");
12228 ret = -EINVAL;
12229 }
12230 mutex_unlock(&dev->struct_mutex);
12231
12232 finish:
12233 if (intel_crtc->active) {
12234 if (intel_crtc->cursor_width != state->base.crtc_w)
12235 intel_crtc->atomic.update_wm = true;
12236
12237 intel_crtc->atomic.fb_bits |=
12238 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
12239 }
12240
12241 return ret;
12242 }
12243
12244 static void
12245 intel_commit_cursor_plane(struct drm_plane *plane,
12246 struct intel_plane_state *state)
12247 {
12248 struct drm_crtc *crtc = state->base.crtc;
12249 struct drm_device *dev = plane->dev;
12250 struct intel_crtc *intel_crtc;
12251 struct intel_plane *intel_plane = to_intel_plane(plane);
12252 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
12253 uint32_t addr;
12254
12255 crtc = crtc ? crtc : plane->crtc;
12256 intel_crtc = to_intel_crtc(crtc);
12257
12258 plane->fb = state->base.fb;
12259 crtc->cursor_x = state->base.crtc_x;
12260 crtc->cursor_y = state->base.crtc_y;
12261
12262 intel_plane->obj = obj;
12263
12264 if (intel_crtc->cursor_bo == obj)
12265 goto update;
12266
12267 if (!obj)
12268 addr = 0;
12269 else if (!INTEL_INFO(dev)->cursor_needs_physical)
12270 addr = i915_gem_obj_ggtt_offset(obj);
12271 else
12272 addr = obj->phys_handle->busaddr;
12273
12274 intel_crtc->cursor_addr = addr;
12275 intel_crtc->cursor_bo = obj;
12276 update:
12277 intel_crtc->cursor_width = state->base.crtc_w;
12278 intel_crtc->cursor_height = state->base.crtc_h;
12279
12280 if (intel_crtc->active)
12281 intel_crtc_update_cursor(crtc, state->visible);
12282 }
12283
12284 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12285 int pipe)
12286 {
12287 struct intel_plane *cursor;
12288 struct intel_plane_state *state;
12289
12290 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12291 if (cursor == NULL)
12292 return NULL;
12293
12294 state = intel_create_plane_state(&cursor->base);
12295 if (!state) {
12296 kfree(cursor);
12297 return NULL;
12298 }
12299 cursor->base.state = &state->base;
12300
12301 cursor->can_scale = false;
12302 cursor->max_downscale = 1;
12303 cursor->pipe = pipe;
12304 cursor->plane = pipe;
12305 cursor->check_plane = intel_check_cursor_plane;
12306 cursor->commit_plane = intel_commit_cursor_plane;
12307
12308 drm_universal_plane_init(dev, &cursor->base, 0,
12309 &intel_plane_funcs,
12310 intel_cursor_formats,
12311 ARRAY_SIZE(intel_cursor_formats),
12312 DRM_PLANE_TYPE_CURSOR);
12313
12314 if (INTEL_INFO(dev)->gen >= 4) {
12315 if (!dev->mode_config.rotation_property)
12316 dev->mode_config.rotation_property =
12317 drm_mode_create_rotation_property(dev,
12318 BIT(DRM_ROTATE_0) |
12319 BIT(DRM_ROTATE_180));
12320 if (dev->mode_config.rotation_property)
12321 drm_object_attach_property(&cursor->base.base,
12322 dev->mode_config.rotation_property,
12323 state->base.rotation);
12324 }
12325
12326 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
12327
12328 return &cursor->base;
12329 }
12330
12331 static void intel_crtc_init(struct drm_device *dev, int pipe)
12332 {
12333 struct drm_i915_private *dev_priv = dev->dev_private;
12334 struct intel_crtc *intel_crtc;
12335 struct intel_crtc_state *crtc_state = NULL;
12336 struct drm_plane *primary = NULL;
12337 struct drm_plane *cursor = NULL;
12338 int i, ret;
12339
12340 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12341 if (intel_crtc == NULL)
12342 return;
12343
12344 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
12345 if (!crtc_state)
12346 goto fail;
12347 intel_crtc_set_state(intel_crtc, crtc_state);
12348
12349 primary = intel_primary_plane_create(dev, pipe);
12350 if (!primary)
12351 goto fail;
12352
12353 cursor = intel_cursor_plane_create(dev, pipe);
12354 if (!cursor)
12355 goto fail;
12356
12357 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12358 cursor, &intel_crtc_funcs);
12359 if (ret)
12360 goto fail;
12361
12362 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12363 for (i = 0; i < 256; i++) {
12364 intel_crtc->lut_r[i] = i;
12365 intel_crtc->lut_g[i] = i;
12366 intel_crtc->lut_b[i] = i;
12367 }
12368
12369 /*
12370 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12371 * is hooked to pipe B. Hence we want plane A feeding pipe B.
12372 */
12373 intel_crtc->pipe = pipe;
12374 intel_crtc->plane = pipe;
12375 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12376 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12377 intel_crtc->plane = !pipe;
12378 }
12379
12380 intel_crtc->cursor_base = ~0;
12381 intel_crtc->cursor_cntl = ~0;
12382 intel_crtc->cursor_size = ~0;
12383
12384 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12385 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12386 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12387 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12388
12389 INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
12390
12391 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12392
12393 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12394 return;
12395
12396 fail:
12397 if (primary)
12398 drm_plane_cleanup(primary);
12399 if (cursor)
12400 drm_plane_cleanup(cursor);
12401 kfree(crtc_state);
12402 kfree(intel_crtc);
12403 }
12404
12405 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12406 {
12407 struct drm_encoder *encoder = connector->base.encoder;
12408 struct drm_device *dev = connector->base.dev;
12409
12410 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12411
12412 if (!encoder || WARN_ON(!encoder->crtc))
12413 return INVALID_PIPE;
12414
12415 return to_intel_crtc(encoder->crtc)->pipe;
12416 }
12417
12418 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12419 struct drm_file *file)
12420 {
12421 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12422 struct drm_crtc *drmmode_crtc;
12423 struct intel_crtc *crtc;
12424
12425 if (!drm_core_check_feature(dev, DRIVER_MODESET))
12426 return -ENODEV;
12427
12428 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12429
12430 if (!drmmode_crtc) {
12431 DRM_ERROR("no such CRTC id\n");
12432 return -ENOENT;
12433 }
12434
12435 crtc = to_intel_crtc(drmmode_crtc);
12436 pipe_from_crtc_id->pipe = crtc->pipe;
12437
12438 return 0;
12439 }
12440
12441 static int intel_encoder_clones(struct intel_encoder *encoder)
12442 {
12443 struct drm_device *dev = encoder->base.dev;
12444 struct intel_encoder *source_encoder;
12445 int index_mask = 0;
12446 int entry = 0;
12447
12448 for_each_intel_encoder(dev, source_encoder) {
12449 if (encoders_cloneable(encoder, source_encoder))
12450 index_mask |= (1 << entry);
12451
12452 entry++;
12453 }
12454
12455 return index_mask;
12456 }
12457
12458 static bool has_edp_a(struct drm_device *dev)
12459 {
12460 struct drm_i915_private *dev_priv = dev->dev_private;
12461
12462 if (!IS_MOBILE(dev))
12463 return false;
12464
12465 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12466 return false;
12467
12468 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12469 return false;
12470
12471 return true;
12472 }
12473
12474 static bool intel_crt_present(struct drm_device *dev)
12475 {
12476 struct drm_i915_private *dev_priv = dev->dev_private;
12477
12478 if (INTEL_INFO(dev)->gen >= 9)
12479 return false;
12480
12481 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12482 return false;
12483
12484 if (IS_CHERRYVIEW(dev))
12485 return false;
12486
12487 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12488 return false;
12489
12490 return true;
12491 }
12492
12493 static void intel_setup_outputs(struct drm_device *dev)
12494 {
12495 struct drm_i915_private *dev_priv = dev->dev_private;
12496 struct intel_encoder *encoder;
12497 struct drm_connector *connector;
12498 bool dpd_is_edp = false;
12499
12500 intel_lvds_init(dev);
12501
12502 if (intel_crt_present(dev))
12503 intel_crt_init(dev);
12504
12505 if (HAS_DDI(dev)) {
12506 int found;
12507
12508 /* Haswell uses DDI functions to detect digital outputs */
12509 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12510 /* DDI A only supports eDP */
12511 if (found)
12512 intel_ddi_init(dev, PORT_A);
12513
12514 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12515 * register */
12516 found = I915_READ(SFUSE_STRAP);
12517
12518 if (found & SFUSE_STRAP_DDIB_DETECTED)
12519 intel_ddi_init(dev, PORT_B);
12520 if (found & SFUSE_STRAP_DDIC_DETECTED)
12521 intel_ddi_init(dev, PORT_C);
12522 if (found & SFUSE_STRAP_DDID_DETECTED)
12523 intel_ddi_init(dev, PORT_D);
12524 } else if (HAS_PCH_SPLIT(dev)) {
12525 int found;
12526 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12527
12528 if (has_edp_a(dev))
12529 intel_dp_init(dev, DP_A, PORT_A);
12530
12531 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12532 /* PCH SDVOB multiplex with HDMIB */
12533 found = intel_sdvo_init(dev, PCH_SDVOB, true);
12534 if (!found)
12535 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12536 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12537 intel_dp_init(dev, PCH_DP_B, PORT_B);
12538 }
12539
12540 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12541 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12542
12543 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12544 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12545
12546 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12547 intel_dp_init(dev, PCH_DP_C, PORT_C);
12548
12549 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12550 intel_dp_init(dev, PCH_DP_D, PORT_D);
12551 } else if (IS_VALLEYVIEW(dev)) {
12552 /*
12553 * The DP_DETECTED bit is the latched state of the DDC
12554 * SDA pin at boot. However since eDP doesn't require DDC
12555 * (no way to plug in a DP->HDMI dongle) the DDC pins for
12556 * eDP ports may have been muxed to an alternate function.
12557 * Thus we can't rely on the DP_DETECTED bit alone to detect
12558 * eDP ports. Consult the VBT as well as DP_DETECTED to
12559 * detect eDP ports.
12560 */
12561 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
12562 !intel_dp_is_edp(dev, PORT_B))
12563 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12564 PORT_B);
12565 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12566 intel_dp_is_edp(dev, PORT_B))
12567 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12568
12569 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
12570 !intel_dp_is_edp(dev, PORT_C))
12571 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12572 PORT_C);
12573 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12574 intel_dp_is_edp(dev, PORT_C))
12575 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12576
12577 if (IS_CHERRYVIEW(dev)) {
12578 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12579 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12580 PORT_D);
12581 /* eDP not supported on port D, so don't check VBT */
12582 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12583 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12584 }
12585
12586 intel_dsi_init(dev);
12587 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12588 bool found = false;
12589
12590 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12591 DRM_DEBUG_KMS("probing SDVOB\n");
12592 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12593 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12594 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12595 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12596 }
12597
12598 if (!found && SUPPORTS_INTEGRATED_DP(dev))
12599 intel_dp_init(dev, DP_B, PORT_B);
12600 }
12601
12602 /* Before G4X SDVOC doesn't have its own detect register */
12603
12604 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12605 DRM_DEBUG_KMS("probing SDVOC\n");
12606 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12607 }
12608
12609 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12610
12611 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12612 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12613 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12614 }
12615 if (SUPPORTS_INTEGRATED_DP(dev))
12616 intel_dp_init(dev, DP_C, PORT_C);
12617 }
12618
12619 if (SUPPORTS_INTEGRATED_DP(dev) &&
12620 (I915_READ(DP_D) & DP_DETECTED))
12621 intel_dp_init(dev, DP_D, PORT_D);
12622 } else if (IS_GEN2(dev))
12623 intel_dvo_init(dev);
12624
12625 if (SUPPORTS_TV(dev))
12626 intel_tv_init(dev);
12627
12628 /*
12629 * FIXME: We don't have full atomic support yet, but we want to be
12630 * able to enable/test plane updates via the atomic interface in the
12631 * meantime. However as soon as we flip DRIVER_ATOMIC on, the DRM core
12632 * will take some atomic codepaths to lookup properties during
12633 * drmModeGetConnector() that unconditionally dereference
12634 * connector->state.
12635 *
12636 * We create a dummy connector state here for each connector to ensure
12637 * the DRM core doesn't try to dereference a NULL connector->state.
12638 * The actual connector properties will never be updated or contain
12639 * useful information, but since we're doing this specifically for
12640 * testing/debug of the plane operations (and only when a specific
12641 * kernel module option is given), that shouldn't really matter.
12642 *
12643 * Once atomic support for crtc's + connectors lands, this loop should
12644 * be removed since we'll be setting up real connector state, which
12645 * will contain Intel-specific properties.
12646 */
12647 if (drm_core_check_feature(dev, DRIVER_ATOMIC)) {
12648 list_for_each_entry(connector,
12649 &dev->mode_config.connector_list,
12650 head) {
12651 if (!WARN_ON(connector->state)) {
12652 connector->state =
12653 kzalloc(sizeof(*connector->state),
12654 GFP_KERNEL);
12655 }
12656 }
12657 }
12658
12659 intel_psr_init(dev);
12660
12661 for_each_intel_encoder(dev, encoder) {
12662 encoder->base.possible_crtcs = encoder->crtc_mask;
12663 encoder->base.possible_clones =
12664 intel_encoder_clones(encoder);
12665 }
12666
12667 intel_init_pch_refclk(dev);
12668
12669 drm_helper_move_panel_connectors_to_head(dev);
12670 }
12671
12672 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12673 {
12674 struct drm_device *dev = fb->dev;
12675 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12676
12677 drm_framebuffer_cleanup(fb);
12678 mutex_lock(&dev->struct_mutex);
12679 WARN_ON(!intel_fb->obj->framebuffer_references--);
12680 drm_gem_object_unreference(&intel_fb->obj->base);
12681 mutex_unlock(&dev->struct_mutex);
12682 kfree(intel_fb);
12683 }
12684
12685 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12686 struct drm_file *file,
12687 unsigned int *handle)
12688 {
12689 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12690 struct drm_i915_gem_object *obj = intel_fb->obj;
12691
12692 return drm_gem_handle_create(file, &obj->base, handle);
12693 }
12694
12695 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12696 .destroy = intel_user_framebuffer_destroy,
12697 .create_handle = intel_user_framebuffer_create_handle,
12698 };
12699
12700 static int intel_framebuffer_init(struct drm_device *dev,
12701 struct intel_framebuffer *intel_fb,
12702 struct drm_mode_fb_cmd2 *mode_cmd,
12703 struct drm_i915_gem_object *obj)
12704 {
12705 int aligned_height;
12706 int pitch_limit;
12707 int ret;
12708
12709 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12710
12711 if (obj->tiling_mode == I915_TILING_Y) {
12712 DRM_DEBUG("hardware does not support tiling Y\n");
12713 return -EINVAL;
12714 }
12715
12716 if (mode_cmd->pitches[0] & 63) {
12717 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12718 mode_cmd->pitches[0]);
12719 return -EINVAL;
12720 }
12721
12722 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12723 pitch_limit = 32*1024;
12724 } else if (INTEL_INFO(dev)->gen >= 4) {
12725 if (obj->tiling_mode)
12726 pitch_limit = 16*1024;
12727 else
12728 pitch_limit = 32*1024;
12729 } else if (INTEL_INFO(dev)->gen >= 3) {
12730 if (obj->tiling_mode)
12731 pitch_limit = 8*1024;
12732 else
12733 pitch_limit = 16*1024;
12734 } else
12735 /* XXX DSPC is limited to 4k tiled */
12736 pitch_limit = 8*1024;
12737
12738 if (mode_cmd->pitches[0] > pitch_limit) {
12739 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12740 obj->tiling_mode ? "tiled" : "linear",
12741 mode_cmd->pitches[0], pitch_limit);
12742 return -EINVAL;
12743 }
12744
12745 if (obj->tiling_mode != I915_TILING_NONE &&
12746 mode_cmd->pitches[0] != obj->stride) {
12747 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12748 mode_cmd->pitches[0], obj->stride);
12749 return -EINVAL;
12750 }
12751
12752 /* Reject formats not supported by any plane early. */
12753 switch (mode_cmd->pixel_format) {
12754 case DRM_FORMAT_C8:
12755 case DRM_FORMAT_RGB565:
12756 case DRM_FORMAT_XRGB8888:
12757 case DRM_FORMAT_ARGB8888:
12758 break;
12759 case DRM_FORMAT_XRGB1555:
12760 case DRM_FORMAT_ARGB1555:
12761 if (INTEL_INFO(dev)->gen > 3) {
12762 DRM_DEBUG("unsupported pixel format: %s\n",
12763 drm_get_format_name(mode_cmd->pixel_format));
12764 return -EINVAL;
12765 }
12766 break;
12767 case DRM_FORMAT_XBGR8888:
12768 case DRM_FORMAT_ABGR8888:
12769 case DRM_FORMAT_XRGB2101010:
12770 case DRM_FORMAT_ARGB2101010:
12771 case DRM_FORMAT_XBGR2101010:
12772 case DRM_FORMAT_ABGR2101010:
12773 if (INTEL_INFO(dev)->gen < 4) {
12774 DRM_DEBUG("unsupported pixel format: %s\n",
12775 drm_get_format_name(mode_cmd->pixel_format));
12776 return -EINVAL;
12777 }
12778 break;
12779 case DRM_FORMAT_YUYV:
12780 case DRM_FORMAT_UYVY:
12781 case DRM_FORMAT_YVYU:
12782 case DRM_FORMAT_VYUY:
12783 if (INTEL_INFO(dev)->gen < 5) {
12784 DRM_DEBUG("unsupported pixel format: %s\n",
12785 drm_get_format_name(mode_cmd->pixel_format));
12786 return -EINVAL;
12787 }
12788 break;
12789 default:
12790 DRM_DEBUG("unsupported pixel format: %s\n",
12791 drm_get_format_name(mode_cmd->pixel_format));
12792 return -EINVAL;
12793 }
12794
12795 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12796 if (mode_cmd->offsets[0] != 0)
12797 return -EINVAL;
12798
12799 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
12800 obj->tiling_mode);
12801 /* FIXME drm helper for size checks (especially planar formats)? */
12802 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12803 return -EINVAL;
12804
12805 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12806 intel_fb->obj = obj;
12807 intel_fb->obj->framebuffer_references++;
12808
12809 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12810 if (ret) {
12811 DRM_ERROR("framebuffer init failed %d\n", ret);
12812 return ret;
12813 }
12814
12815 return 0;
12816 }
12817
12818 static struct drm_framebuffer *
12819 intel_user_framebuffer_create(struct drm_device *dev,
12820 struct drm_file *filp,
12821 struct drm_mode_fb_cmd2 *mode_cmd)
12822 {
12823 struct drm_i915_gem_object *obj;
12824
12825 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12826 mode_cmd->handles[0]));
12827 if (&obj->base == NULL)
12828 return ERR_PTR(-ENOENT);
12829
12830 return intel_framebuffer_create(dev, mode_cmd, obj);
12831 }
12832
12833 #ifndef CONFIG_DRM_I915_FBDEV
12834 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12835 {
12836 }
12837 #endif
12838
12839 static const struct drm_mode_config_funcs intel_mode_funcs = {
12840 .fb_create = intel_user_framebuffer_create,
12841 .output_poll_changed = intel_fbdev_output_poll_changed,
12842 .atomic_check = intel_atomic_check,
12843 .atomic_commit = intel_atomic_commit,
12844 };
12845
12846 /* Set up chip specific display functions */
12847 static void intel_init_display(struct drm_device *dev)
12848 {
12849 struct drm_i915_private *dev_priv = dev->dev_private;
12850
12851 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12852 dev_priv->display.find_dpll = g4x_find_best_dpll;
12853 else if (IS_CHERRYVIEW(dev))
12854 dev_priv->display.find_dpll = chv_find_best_dpll;
12855 else if (IS_VALLEYVIEW(dev))
12856 dev_priv->display.find_dpll = vlv_find_best_dpll;
12857 else if (IS_PINEVIEW(dev))
12858 dev_priv->display.find_dpll = pnv_find_best_dpll;
12859 else
12860 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12861
12862 if (INTEL_INFO(dev)->gen >= 9) {
12863 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12864 dev_priv->display.get_initial_plane_config =
12865 skylake_get_initial_plane_config;
12866 dev_priv->display.crtc_compute_clock =
12867 haswell_crtc_compute_clock;
12868 dev_priv->display.crtc_enable = haswell_crtc_enable;
12869 dev_priv->display.crtc_disable = haswell_crtc_disable;
12870 dev_priv->display.off = ironlake_crtc_off;
12871 dev_priv->display.update_primary_plane =
12872 skylake_update_primary_plane;
12873 } else if (HAS_DDI(dev)) {
12874 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12875 dev_priv->display.get_initial_plane_config =
12876 ironlake_get_initial_plane_config;
12877 dev_priv->display.crtc_compute_clock =
12878 haswell_crtc_compute_clock;
12879 dev_priv->display.crtc_enable = haswell_crtc_enable;
12880 dev_priv->display.crtc_disable = haswell_crtc_disable;
12881 dev_priv->display.off = ironlake_crtc_off;
12882 dev_priv->display.update_primary_plane =
12883 ironlake_update_primary_plane;
12884 } else if (HAS_PCH_SPLIT(dev)) {
12885 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12886 dev_priv->display.get_initial_plane_config =
12887 ironlake_get_initial_plane_config;
12888 dev_priv->display.crtc_compute_clock =
12889 ironlake_crtc_compute_clock;
12890 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12891 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12892 dev_priv->display.off = ironlake_crtc_off;
12893 dev_priv->display.update_primary_plane =
12894 ironlake_update_primary_plane;
12895 } else if (IS_VALLEYVIEW(dev)) {
12896 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12897 dev_priv->display.get_initial_plane_config =
12898 i9xx_get_initial_plane_config;
12899 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
12900 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12901 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12902 dev_priv->display.off = i9xx_crtc_off;
12903 dev_priv->display.update_primary_plane =
12904 i9xx_update_primary_plane;
12905 } else {
12906 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12907 dev_priv->display.get_initial_plane_config =
12908 i9xx_get_initial_plane_config;
12909 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
12910 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12911 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12912 dev_priv->display.off = i9xx_crtc_off;
12913 dev_priv->display.update_primary_plane =
12914 i9xx_update_primary_plane;
12915 }
12916
12917 /* Returns the core display clock speed */
12918 if (IS_VALLEYVIEW(dev))
12919 dev_priv->display.get_display_clock_speed =
12920 valleyview_get_display_clock_speed;
12921 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12922 dev_priv->display.get_display_clock_speed =
12923 i945_get_display_clock_speed;
12924 else if (IS_I915G(dev))
12925 dev_priv->display.get_display_clock_speed =
12926 i915_get_display_clock_speed;
12927 else if (IS_I945GM(dev) || IS_845G(dev))
12928 dev_priv->display.get_display_clock_speed =
12929 i9xx_misc_get_display_clock_speed;
12930 else if (IS_PINEVIEW(dev))
12931 dev_priv->display.get_display_clock_speed =
12932 pnv_get_display_clock_speed;
12933 else if (IS_I915GM(dev))
12934 dev_priv->display.get_display_clock_speed =
12935 i915gm_get_display_clock_speed;
12936 else if (IS_I865G(dev))
12937 dev_priv->display.get_display_clock_speed =
12938 i865_get_display_clock_speed;
12939 else if (IS_I85X(dev))
12940 dev_priv->display.get_display_clock_speed =
12941 i855_get_display_clock_speed;
12942 else /* 852, 830 */
12943 dev_priv->display.get_display_clock_speed =
12944 i830_get_display_clock_speed;
12945
12946 if (IS_GEN5(dev)) {
12947 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12948 } else if (IS_GEN6(dev)) {
12949 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12950 } else if (IS_IVYBRIDGE(dev)) {
12951 /* FIXME: detect B0+ stepping and use auto training */
12952 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12953 dev_priv->display.modeset_global_resources =
12954 ivb_modeset_global_resources;
12955 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12956 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12957 } else if (IS_VALLEYVIEW(dev)) {
12958 dev_priv->display.modeset_global_resources =
12959 valleyview_modeset_global_resources;
12960 }
12961
12962 /* Default just returns -ENODEV to indicate unsupported */
12963 dev_priv->display.queue_flip = intel_default_queue_flip;
12964
12965 switch (INTEL_INFO(dev)->gen) {
12966 case 2:
12967 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12968 break;
12969
12970 case 3:
12971 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12972 break;
12973
12974 case 4:
12975 case 5:
12976 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12977 break;
12978
12979 case 6:
12980 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12981 break;
12982 case 7:
12983 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12984 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12985 break;
12986 case 9:
12987 dev_priv->display.queue_flip = intel_gen9_queue_flip;
12988 break;
12989 }
12990
12991 intel_panel_init_backlight_funcs(dev);
12992
12993 mutex_init(&dev_priv->pps_mutex);
12994 }
12995
12996 /*
12997 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12998 * resume, or other times. This quirk makes sure that's the case for
12999 * affected systems.
13000 */
13001 static void quirk_pipea_force(struct drm_device *dev)
13002 {
13003 struct drm_i915_private *dev_priv = dev->dev_private;
13004
13005 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
13006 DRM_INFO("applying pipe a force quirk\n");
13007 }
13008
13009 static void quirk_pipeb_force(struct drm_device *dev)
13010 {
13011 struct drm_i915_private *dev_priv = dev->dev_private;
13012
13013 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
13014 DRM_INFO("applying pipe b force quirk\n");
13015 }
13016
13017 /*
13018 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
13019 */
13020 static void quirk_ssc_force_disable(struct drm_device *dev)
13021 {
13022 struct drm_i915_private *dev_priv = dev->dev_private;
13023 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
13024 DRM_INFO("applying lvds SSC disable quirk\n");
13025 }
13026
13027 /*
13028 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
13029 * brightness value
13030 */
13031 static void quirk_invert_brightness(struct drm_device *dev)
13032 {
13033 struct drm_i915_private *dev_priv = dev->dev_private;
13034 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
13035 DRM_INFO("applying inverted panel brightness quirk\n");
13036 }
13037
13038 /* Some VBT's incorrectly indicate no backlight is present */
13039 static void quirk_backlight_present(struct drm_device *dev)
13040 {
13041 struct drm_i915_private *dev_priv = dev->dev_private;
13042 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
13043 DRM_INFO("applying backlight present quirk\n");
13044 }
13045
13046 struct intel_quirk {
13047 int device;
13048 int subsystem_vendor;
13049 int subsystem_device;
13050 void (*hook)(struct drm_device *dev);
13051 };
13052
13053 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
13054 struct intel_dmi_quirk {
13055 void (*hook)(struct drm_device *dev);
13056 const struct dmi_system_id (*dmi_id_list)[];
13057 };
13058
13059 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
13060 {
13061 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
13062 return 1;
13063 }
13064
13065 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
13066 {
13067 .dmi_id_list = &(const struct dmi_system_id[]) {
13068 {
13069 .callback = intel_dmi_reverse_brightness,
13070 .ident = "NCR Corporation",
13071 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
13072 DMI_MATCH(DMI_PRODUCT_NAME, ""),
13073 },
13074 },
13075 { } /* terminating entry */
13076 },
13077 .hook = quirk_invert_brightness,
13078 },
13079 };
13080
13081 static struct intel_quirk intel_quirks[] = {
13082 /* HP Mini needs pipe A force quirk (LP: #322104) */
13083 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
13084
13085 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
13086 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
13087
13088 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
13089 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
13090
13091 /* 830 needs to leave pipe A & dpll A up */
13092 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
13093
13094 /* 830 needs to leave pipe B & dpll B up */
13095 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
13096
13097 /* Lenovo U160 cannot use SSC on LVDS */
13098 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
13099
13100 /* Sony Vaio Y cannot use SSC on LVDS */
13101 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
13102
13103 /* Acer Aspire 5734Z must invert backlight brightness */
13104 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
13105
13106 /* Acer/eMachines G725 */
13107 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
13108
13109 /* Acer/eMachines e725 */
13110 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
13111
13112 /* Acer/Packard Bell NCL20 */
13113 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
13114
13115 /* Acer Aspire 4736Z */
13116 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
13117
13118 /* Acer Aspire 5336 */
13119 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
13120
13121 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
13122 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
13123
13124 /* Acer C720 Chromebook (Core i3 4005U) */
13125 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
13126
13127 /* Apple Macbook 2,1 (Core 2 T7400) */
13128 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
13129
13130 /* Toshiba CB35 Chromebook (Celeron 2955U) */
13131 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
13132
13133 /* HP Chromebook 14 (Celeron 2955U) */
13134 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
13135
13136 /* Dell Chromebook 11 */
13137 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
13138 };
13139
13140 static void intel_init_quirks(struct drm_device *dev)
13141 {
13142 struct pci_dev *d = dev->pdev;
13143 int i;
13144
13145 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
13146 struct intel_quirk *q = &intel_quirks[i];
13147
13148 if (d->device == q->device &&
13149 (d->subsystem_vendor == q->subsystem_vendor ||
13150 q->subsystem_vendor == PCI_ANY_ID) &&
13151 (d->subsystem_device == q->subsystem_device ||
13152 q->subsystem_device == PCI_ANY_ID))
13153 q->hook(dev);
13154 }
13155 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
13156 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
13157 intel_dmi_quirks[i].hook(dev);
13158 }
13159 }
13160
13161 /* Disable the VGA plane that we never use */
13162 static void i915_disable_vga(struct drm_device *dev)
13163 {
13164 struct drm_i915_private *dev_priv = dev->dev_private;
13165 u8 sr1;
13166 u32 vga_reg = i915_vgacntrl_reg(dev);
13167
13168 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
13169 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
13170 outb(SR01, VGA_SR_INDEX);
13171 sr1 = inb(VGA_SR_DATA);
13172 outb(sr1 | 1<<5, VGA_SR_DATA);
13173 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
13174 udelay(300);
13175
13176 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
13177 POSTING_READ(vga_reg);
13178 }
13179
13180 void intel_modeset_init_hw(struct drm_device *dev)
13181 {
13182 intel_prepare_ddi(dev);
13183
13184 if (IS_VALLEYVIEW(dev))
13185 vlv_update_cdclk(dev);
13186
13187 intel_init_clock_gating(dev);
13188
13189 intel_enable_gt_powersave(dev);
13190 }
13191
13192 void intel_modeset_init(struct drm_device *dev)
13193 {
13194 struct drm_i915_private *dev_priv = dev->dev_private;
13195 int sprite, ret;
13196 enum pipe pipe;
13197 struct intel_crtc *crtc;
13198
13199 drm_mode_config_init(dev);
13200
13201 dev->mode_config.min_width = 0;
13202 dev->mode_config.min_height = 0;
13203
13204 dev->mode_config.preferred_depth = 24;
13205 dev->mode_config.prefer_shadow = 1;
13206
13207 dev->mode_config.funcs = &intel_mode_funcs;
13208
13209 intel_init_quirks(dev);
13210
13211 intel_init_pm(dev);
13212
13213 if (INTEL_INFO(dev)->num_pipes == 0)
13214 return;
13215
13216 intel_init_display(dev);
13217 intel_init_audio(dev);
13218
13219 if (IS_GEN2(dev)) {
13220 dev->mode_config.max_width = 2048;
13221 dev->mode_config.max_height = 2048;
13222 } else if (IS_GEN3(dev)) {
13223 dev->mode_config.max_width = 4096;
13224 dev->mode_config.max_height = 4096;
13225 } else {
13226 dev->mode_config.max_width = 8192;
13227 dev->mode_config.max_height = 8192;
13228 }
13229
13230 if (IS_845G(dev) || IS_I865G(dev)) {
13231 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
13232 dev->mode_config.cursor_height = 1023;
13233 } else if (IS_GEN2(dev)) {
13234 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
13235 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
13236 } else {
13237 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
13238 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
13239 }
13240
13241 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
13242
13243 DRM_DEBUG_KMS("%d display pipe%s available.\n",
13244 INTEL_INFO(dev)->num_pipes,
13245 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
13246
13247 for_each_pipe(dev_priv, pipe) {
13248 intel_crtc_init(dev, pipe);
13249 for_each_sprite(pipe, sprite) {
13250 ret = intel_plane_init(dev, pipe, sprite);
13251 if (ret)
13252 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
13253 pipe_name(pipe), sprite_name(pipe, sprite), ret);
13254 }
13255 }
13256
13257 intel_init_dpio(dev);
13258
13259 intel_shared_dpll_init(dev);
13260
13261 /* Just disable it once at startup */
13262 i915_disable_vga(dev);
13263 intel_setup_outputs(dev);
13264
13265 /* Just in case the BIOS is doing something questionable. */
13266 intel_fbc_disable(dev);
13267
13268 drm_modeset_lock_all(dev);
13269 intel_modeset_setup_hw_state(dev, false);
13270 drm_modeset_unlock_all(dev);
13271
13272 for_each_intel_crtc(dev, crtc) {
13273 if (!crtc->active)
13274 continue;
13275
13276 /*
13277 * Note that reserving the BIOS fb up front prevents us
13278 * from stuffing other stolen allocations like the ring
13279 * on top. This prevents some ugliness at boot time, and
13280 * can even allow for smooth boot transitions if the BIOS
13281 * fb is large enough for the active pipe configuration.
13282 */
13283 if (dev_priv->display.get_initial_plane_config) {
13284 dev_priv->display.get_initial_plane_config(crtc,
13285 &crtc->plane_config);
13286 /*
13287 * If the fb is shared between multiple heads, we'll
13288 * just get the first one.
13289 */
13290 intel_find_plane_obj(crtc, &crtc->plane_config);
13291 }
13292 }
13293 }
13294
13295 static void intel_enable_pipe_a(struct drm_device *dev)
13296 {
13297 struct intel_connector *connector;
13298 struct drm_connector *crt = NULL;
13299 struct intel_load_detect_pipe load_detect_temp;
13300 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
13301
13302 /* We can't just switch on the pipe A, we need to set things up with a
13303 * proper mode and output configuration. As a gross hack, enable pipe A
13304 * by enabling the load detect pipe once. */
13305 list_for_each_entry(connector,
13306 &dev->mode_config.connector_list,
13307 base.head) {
13308 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13309 crt = &connector->base;
13310 break;
13311 }
13312 }
13313
13314 if (!crt)
13315 return;
13316
13317 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13318 intel_release_load_detect_pipe(crt, &load_detect_temp);
13319 }
13320
13321 static bool
13322 intel_check_plane_mapping(struct intel_crtc *crtc)
13323 {
13324 struct drm_device *dev = crtc->base.dev;
13325 struct drm_i915_private *dev_priv = dev->dev_private;
13326 u32 reg, val;
13327
13328 if (INTEL_INFO(dev)->num_pipes == 1)
13329 return true;
13330
13331 reg = DSPCNTR(!crtc->plane);
13332 val = I915_READ(reg);
13333
13334 if ((val & DISPLAY_PLANE_ENABLE) &&
13335 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13336 return false;
13337
13338 return true;
13339 }
13340
13341 static void intel_sanitize_crtc(struct intel_crtc *crtc)
13342 {
13343 struct drm_device *dev = crtc->base.dev;
13344 struct drm_i915_private *dev_priv = dev->dev_private;
13345 u32 reg;
13346
13347 /* Clear any frame start delays used for debugging left by the BIOS */
13348 reg = PIPECONF(crtc->config->cpu_transcoder);
13349 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13350
13351 /* restore vblank interrupts to correct state */
13352 if (crtc->active) {
13353 update_scanline_offset(crtc);
13354 drm_vblank_on(dev, crtc->pipe);
13355 } else
13356 drm_vblank_off(dev, crtc->pipe);
13357
13358 /* We need to sanitize the plane -> pipe mapping first because this will
13359 * disable the crtc (and hence change the state) if it is wrong. Note
13360 * that gen4+ has a fixed plane -> pipe mapping. */
13361 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13362 struct intel_connector *connector;
13363 bool plane;
13364
13365 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13366 crtc->base.base.id);
13367
13368 /* Pipe has the wrong plane attached and the plane is active.
13369 * Temporarily change the plane mapping and disable everything
13370 * ... */
13371 plane = crtc->plane;
13372 crtc->plane = !plane;
13373 crtc->primary_enabled = true;
13374 dev_priv->display.crtc_disable(&crtc->base);
13375 crtc->plane = plane;
13376
13377 /* ... and break all links. */
13378 list_for_each_entry(connector, &dev->mode_config.connector_list,
13379 base.head) {
13380 if (connector->encoder->base.crtc != &crtc->base)
13381 continue;
13382
13383 connector->base.dpms = DRM_MODE_DPMS_OFF;
13384 connector->base.encoder = NULL;
13385 }
13386 /* multiple connectors may have the same encoder:
13387 * handle them and break crtc link separately */
13388 list_for_each_entry(connector, &dev->mode_config.connector_list,
13389 base.head)
13390 if (connector->encoder->base.crtc == &crtc->base) {
13391 connector->encoder->base.crtc = NULL;
13392 connector->encoder->connectors_active = false;
13393 }
13394
13395 WARN_ON(crtc->active);
13396 crtc->base.enabled = false;
13397 }
13398
13399 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13400 crtc->pipe == PIPE_A && !crtc->active) {
13401 /* BIOS forgot to enable pipe A, this mostly happens after
13402 * resume. Force-enable the pipe to fix this, the update_dpms
13403 * call below we restore the pipe to the right state, but leave
13404 * the required bits on. */
13405 intel_enable_pipe_a(dev);
13406 }
13407
13408 /* Adjust the state of the output pipe according to whether we
13409 * have active connectors/encoders. */
13410 intel_crtc_update_dpms(&crtc->base);
13411
13412 if (crtc->active != crtc->base.enabled) {
13413 struct intel_encoder *encoder;
13414
13415 /* This can happen either due to bugs in the get_hw_state
13416 * functions or because the pipe is force-enabled due to the
13417 * pipe A quirk. */
13418 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13419 crtc->base.base.id,
13420 crtc->base.enabled ? "enabled" : "disabled",
13421 crtc->active ? "enabled" : "disabled");
13422
13423 crtc->base.enabled = crtc->active;
13424
13425 /* Because we only establish the connector -> encoder ->
13426 * crtc links if something is active, this means the
13427 * crtc is now deactivated. Break the links. connector
13428 * -> encoder links are only establish when things are
13429 * actually up, hence no need to break them. */
13430 WARN_ON(crtc->active);
13431
13432 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13433 WARN_ON(encoder->connectors_active);
13434 encoder->base.crtc = NULL;
13435 }
13436 }
13437
13438 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13439 /*
13440 * We start out with underrun reporting disabled to avoid races.
13441 * For correct bookkeeping mark this on active crtcs.
13442 *
13443 * Also on gmch platforms we dont have any hardware bits to
13444 * disable the underrun reporting. Which means we need to start
13445 * out with underrun reporting disabled also on inactive pipes,
13446 * since otherwise we'll complain about the garbage we read when
13447 * e.g. coming up after runtime pm.
13448 *
13449 * No protection against concurrent access is required - at
13450 * worst a fifo underrun happens which also sets this to false.
13451 */
13452 crtc->cpu_fifo_underrun_disabled = true;
13453 crtc->pch_fifo_underrun_disabled = true;
13454 }
13455 }
13456
13457 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13458 {
13459 struct intel_connector *connector;
13460 struct drm_device *dev = encoder->base.dev;
13461
13462 /* We need to check both for a crtc link (meaning that the
13463 * encoder is active and trying to read from a pipe) and the
13464 * pipe itself being active. */
13465 bool has_active_crtc = encoder->base.crtc &&
13466 to_intel_crtc(encoder->base.crtc)->active;
13467
13468 if (encoder->connectors_active && !has_active_crtc) {
13469 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13470 encoder->base.base.id,
13471 encoder->base.name);
13472
13473 /* Connector is active, but has no active pipe. This is
13474 * fallout from our resume register restoring. Disable
13475 * the encoder manually again. */
13476 if (encoder->base.crtc) {
13477 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13478 encoder->base.base.id,
13479 encoder->base.name);
13480 encoder->disable(encoder);
13481 if (encoder->post_disable)
13482 encoder->post_disable(encoder);
13483 }
13484 encoder->base.crtc = NULL;
13485 encoder->connectors_active = false;
13486
13487 /* Inconsistent output/port/pipe state happens presumably due to
13488 * a bug in one of the get_hw_state functions. Or someplace else
13489 * in our code, like the register restore mess on resume. Clamp
13490 * things to off as a safer default. */
13491 list_for_each_entry(connector,
13492 &dev->mode_config.connector_list,
13493 base.head) {
13494 if (connector->encoder != encoder)
13495 continue;
13496 connector->base.dpms = DRM_MODE_DPMS_OFF;
13497 connector->base.encoder = NULL;
13498 }
13499 }
13500 /* Enabled encoders without active connectors will be fixed in
13501 * the crtc fixup. */
13502 }
13503
13504 void i915_redisable_vga_power_on(struct drm_device *dev)
13505 {
13506 struct drm_i915_private *dev_priv = dev->dev_private;
13507 u32 vga_reg = i915_vgacntrl_reg(dev);
13508
13509 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13510 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13511 i915_disable_vga(dev);
13512 }
13513 }
13514
13515 void i915_redisable_vga(struct drm_device *dev)
13516 {
13517 struct drm_i915_private *dev_priv = dev->dev_private;
13518
13519 /* This function can be called both from intel_modeset_setup_hw_state or
13520 * at a very early point in our resume sequence, where the power well
13521 * structures are not yet restored. Since this function is at a very
13522 * paranoid "someone might have enabled VGA while we were not looking"
13523 * level, just check if the power well is enabled instead of trying to
13524 * follow the "don't touch the power well if we don't need it" policy
13525 * the rest of the driver uses. */
13526 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
13527 return;
13528
13529 i915_redisable_vga_power_on(dev);
13530 }
13531
13532 static bool primary_get_hw_state(struct intel_crtc *crtc)
13533 {
13534 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13535
13536 if (!crtc->active)
13537 return false;
13538
13539 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13540 }
13541
13542 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13543 {
13544 struct drm_i915_private *dev_priv = dev->dev_private;
13545 enum pipe pipe;
13546 struct intel_crtc *crtc;
13547 struct intel_encoder *encoder;
13548 struct intel_connector *connector;
13549 int i;
13550
13551 for_each_intel_crtc(dev, crtc) {
13552 memset(crtc->config, 0, sizeof(*crtc->config));
13553
13554 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13555
13556 crtc->active = dev_priv->display.get_pipe_config(crtc,
13557 crtc->config);
13558
13559 crtc->base.enabled = crtc->active;
13560 crtc->primary_enabled = primary_get_hw_state(crtc);
13561
13562 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13563 crtc->base.base.id,
13564 crtc->active ? "enabled" : "disabled");
13565 }
13566
13567 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13568 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13569
13570 pll->on = pll->get_hw_state(dev_priv, pll,
13571 &pll->config.hw_state);
13572 pll->active = 0;
13573 pll->config.crtc_mask = 0;
13574 for_each_intel_crtc(dev, crtc) {
13575 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
13576 pll->active++;
13577 pll->config.crtc_mask |= 1 << crtc->pipe;
13578 }
13579 }
13580
13581 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
13582 pll->name, pll->config.crtc_mask, pll->on);
13583
13584 if (pll->config.crtc_mask)
13585 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13586 }
13587
13588 for_each_intel_encoder(dev, encoder) {
13589 pipe = 0;
13590
13591 if (encoder->get_hw_state(encoder, &pipe)) {
13592 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13593 encoder->base.crtc = &crtc->base;
13594 encoder->get_config(encoder, crtc->config);
13595 } else {
13596 encoder->base.crtc = NULL;
13597 }
13598
13599 encoder->connectors_active = false;
13600 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13601 encoder->base.base.id,
13602 encoder->base.name,
13603 encoder->base.crtc ? "enabled" : "disabled",
13604 pipe_name(pipe));
13605 }
13606
13607 list_for_each_entry(connector, &dev->mode_config.connector_list,
13608 base.head) {
13609 if (connector->get_hw_state(connector)) {
13610 connector->base.dpms = DRM_MODE_DPMS_ON;
13611 connector->encoder->connectors_active = true;
13612 connector->base.encoder = &connector->encoder->base;
13613 } else {
13614 connector->base.dpms = DRM_MODE_DPMS_OFF;
13615 connector->base.encoder = NULL;
13616 }
13617 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13618 connector->base.base.id,
13619 connector->base.name,
13620 connector->base.encoder ? "enabled" : "disabled");
13621 }
13622 }
13623
13624 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13625 * and i915 state tracking structures. */
13626 void intel_modeset_setup_hw_state(struct drm_device *dev,
13627 bool force_restore)
13628 {
13629 struct drm_i915_private *dev_priv = dev->dev_private;
13630 enum pipe pipe;
13631 struct intel_crtc *crtc;
13632 struct intel_encoder *encoder;
13633 int i;
13634
13635 intel_modeset_readout_hw_state(dev);
13636
13637 /*
13638 * Now that we have the config, copy it to each CRTC struct
13639 * Note that this could go away if we move to using crtc_config
13640 * checking everywhere.
13641 */
13642 for_each_intel_crtc(dev, crtc) {
13643 if (crtc->active && i915.fastboot) {
13644 intel_mode_from_pipe_config(&crtc->base.mode,
13645 crtc->config);
13646 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13647 crtc->base.base.id);
13648 drm_mode_debug_printmodeline(&crtc->base.mode);
13649 }
13650 }
13651
13652 /* HW state is read out, now we need to sanitize this mess. */
13653 for_each_intel_encoder(dev, encoder) {
13654 intel_sanitize_encoder(encoder);
13655 }
13656
13657 for_each_pipe(dev_priv, pipe) {
13658 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13659 intel_sanitize_crtc(crtc);
13660 intel_dump_pipe_config(crtc, crtc->config,
13661 "[setup_hw_state]");
13662 }
13663
13664 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13665 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13666
13667 if (!pll->on || pll->active)
13668 continue;
13669
13670 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13671
13672 pll->disable(dev_priv, pll);
13673 pll->on = false;
13674 }
13675
13676 if (IS_GEN9(dev))
13677 skl_wm_get_hw_state(dev);
13678 else if (HAS_PCH_SPLIT(dev))
13679 ilk_wm_get_hw_state(dev);
13680
13681 if (force_restore) {
13682 i915_redisable_vga(dev);
13683
13684 /*
13685 * We need to use raw interfaces for restoring state to avoid
13686 * checking (bogus) intermediate states.
13687 */
13688 for_each_pipe(dev_priv, pipe) {
13689 struct drm_crtc *crtc =
13690 dev_priv->pipe_to_crtc_mapping[pipe];
13691
13692 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13693 crtc->primary->fb);
13694 }
13695 } else {
13696 intel_modeset_update_staged_output_state(dev);
13697 }
13698
13699 intel_modeset_check_state(dev);
13700 }
13701
13702 void intel_modeset_gem_init(struct drm_device *dev)
13703 {
13704 struct drm_i915_private *dev_priv = dev->dev_private;
13705 struct drm_crtc *c;
13706 struct drm_i915_gem_object *obj;
13707
13708 mutex_lock(&dev->struct_mutex);
13709 intel_init_gt_powersave(dev);
13710 mutex_unlock(&dev->struct_mutex);
13711
13712 /*
13713 * There may be no VBT; and if the BIOS enabled SSC we can
13714 * just keep using it to avoid unnecessary flicker. Whereas if the
13715 * BIOS isn't using it, don't assume it will work even if the VBT
13716 * indicates as much.
13717 */
13718 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13719 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
13720 DREF_SSC1_ENABLE);
13721
13722 intel_modeset_init_hw(dev);
13723
13724 intel_setup_overlay(dev);
13725
13726 /*
13727 * Make sure any fbs we allocated at startup are properly
13728 * pinned & fenced. When we do the allocation it's too early
13729 * for this.
13730 */
13731 mutex_lock(&dev->struct_mutex);
13732 for_each_crtc(dev, c) {
13733 obj = intel_fb_obj(c->primary->fb);
13734 if (obj == NULL)
13735 continue;
13736
13737 if (intel_pin_and_fence_fb_obj(c->primary,
13738 c->primary->fb,
13739 NULL)) {
13740 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13741 to_intel_crtc(c)->pipe);
13742 drm_framebuffer_unreference(c->primary->fb);
13743 c->primary->fb = NULL;
13744 update_state_fb(c->primary);
13745 }
13746 }
13747 mutex_unlock(&dev->struct_mutex);
13748
13749 intel_backlight_register(dev);
13750 }
13751
13752 void intel_connector_unregister(struct intel_connector *intel_connector)
13753 {
13754 struct drm_connector *connector = &intel_connector->base;
13755
13756 intel_panel_destroy_backlight(connector);
13757 drm_connector_unregister(connector);
13758 }
13759
13760 void intel_modeset_cleanup(struct drm_device *dev)
13761 {
13762 struct drm_i915_private *dev_priv = dev->dev_private;
13763 struct drm_connector *connector;
13764
13765 intel_disable_gt_powersave(dev);
13766
13767 intel_backlight_unregister(dev);
13768
13769 /*
13770 * Interrupts and polling as the first thing to avoid creating havoc.
13771 * Too much stuff here (turning of connectors, ...) would
13772 * experience fancy races otherwise.
13773 */
13774 intel_irq_uninstall(dev_priv);
13775
13776 /*
13777 * Due to the hpd irq storm handling the hotplug work can re-arm the
13778 * poll handlers. Hence disable polling after hpd handling is shut down.
13779 */
13780 drm_kms_helper_poll_fini(dev);
13781
13782 mutex_lock(&dev->struct_mutex);
13783
13784 intel_unregister_dsm_handler();
13785
13786 intel_fbc_disable(dev);
13787
13788 ironlake_teardown_rc6(dev);
13789
13790 mutex_unlock(&dev->struct_mutex);
13791
13792 /* flush any delayed tasks or pending work */
13793 flush_scheduled_work();
13794
13795 /* destroy the backlight and sysfs files before encoders/connectors */
13796 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13797 struct intel_connector *intel_connector;
13798
13799 intel_connector = to_intel_connector(connector);
13800 intel_connector->unregister(intel_connector);
13801 }
13802
13803 drm_mode_config_cleanup(dev);
13804
13805 intel_cleanup_overlay(dev);
13806
13807 mutex_lock(&dev->struct_mutex);
13808 intel_cleanup_gt_powersave(dev);
13809 mutex_unlock(&dev->struct_mutex);
13810 }
13811
13812 /*
13813 * Return which encoder is currently attached for connector.
13814 */
13815 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13816 {
13817 return &intel_attached_encoder(connector)->base;
13818 }
13819
13820 void intel_connector_attach_encoder(struct intel_connector *connector,
13821 struct intel_encoder *encoder)
13822 {
13823 connector->encoder = encoder;
13824 drm_mode_connector_attach_encoder(&connector->base,
13825 &encoder->base);
13826 }
13827
13828 /*
13829 * set vga decode state - true == enable VGA decode
13830 */
13831 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13832 {
13833 struct drm_i915_private *dev_priv = dev->dev_private;
13834 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13835 u16 gmch_ctrl;
13836
13837 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13838 DRM_ERROR("failed to read control word\n");
13839 return -EIO;
13840 }
13841
13842 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13843 return 0;
13844
13845 if (state)
13846 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13847 else
13848 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13849
13850 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13851 DRM_ERROR("failed to write control word\n");
13852 return -EIO;
13853 }
13854
13855 return 0;
13856 }
13857
13858 struct intel_display_error_state {
13859
13860 u32 power_well_driver;
13861
13862 int num_transcoders;
13863
13864 struct intel_cursor_error_state {
13865 u32 control;
13866 u32 position;
13867 u32 base;
13868 u32 size;
13869 } cursor[I915_MAX_PIPES];
13870
13871 struct intel_pipe_error_state {
13872 bool power_domain_on;
13873 u32 source;
13874 u32 stat;
13875 } pipe[I915_MAX_PIPES];
13876
13877 struct intel_plane_error_state {
13878 u32 control;
13879 u32 stride;
13880 u32 size;
13881 u32 pos;
13882 u32 addr;
13883 u32 surface;
13884 u32 tile_offset;
13885 } plane[I915_MAX_PIPES];
13886
13887 struct intel_transcoder_error_state {
13888 bool power_domain_on;
13889 enum transcoder cpu_transcoder;
13890
13891 u32 conf;
13892
13893 u32 htotal;
13894 u32 hblank;
13895 u32 hsync;
13896 u32 vtotal;
13897 u32 vblank;
13898 u32 vsync;
13899 } transcoder[4];
13900 };
13901
13902 struct intel_display_error_state *
13903 intel_display_capture_error_state(struct drm_device *dev)
13904 {
13905 struct drm_i915_private *dev_priv = dev->dev_private;
13906 struct intel_display_error_state *error;
13907 int transcoders[] = {
13908 TRANSCODER_A,
13909 TRANSCODER_B,
13910 TRANSCODER_C,
13911 TRANSCODER_EDP,
13912 };
13913 int i;
13914
13915 if (INTEL_INFO(dev)->num_pipes == 0)
13916 return NULL;
13917
13918 error = kzalloc(sizeof(*error), GFP_ATOMIC);
13919 if (error == NULL)
13920 return NULL;
13921
13922 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13923 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13924
13925 for_each_pipe(dev_priv, i) {
13926 error->pipe[i].power_domain_on =
13927 __intel_display_power_is_enabled(dev_priv,
13928 POWER_DOMAIN_PIPE(i));
13929 if (!error->pipe[i].power_domain_on)
13930 continue;
13931
13932 error->cursor[i].control = I915_READ(CURCNTR(i));
13933 error->cursor[i].position = I915_READ(CURPOS(i));
13934 error->cursor[i].base = I915_READ(CURBASE(i));
13935
13936 error->plane[i].control = I915_READ(DSPCNTR(i));
13937 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13938 if (INTEL_INFO(dev)->gen <= 3) {
13939 error->plane[i].size = I915_READ(DSPSIZE(i));
13940 error->plane[i].pos = I915_READ(DSPPOS(i));
13941 }
13942 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13943 error->plane[i].addr = I915_READ(DSPADDR(i));
13944 if (INTEL_INFO(dev)->gen >= 4) {
13945 error->plane[i].surface = I915_READ(DSPSURF(i));
13946 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13947 }
13948
13949 error->pipe[i].source = I915_READ(PIPESRC(i));
13950
13951 if (HAS_GMCH_DISPLAY(dev))
13952 error->pipe[i].stat = I915_READ(PIPESTAT(i));
13953 }
13954
13955 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13956 if (HAS_DDI(dev_priv->dev))
13957 error->num_transcoders++; /* Account for eDP. */
13958
13959 for (i = 0; i < error->num_transcoders; i++) {
13960 enum transcoder cpu_transcoder = transcoders[i];
13961
13962 error->transcoder[i].power_domain_on =
13963 __intel_display_power_is_enabled(dev_priv,
13964 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13965 if (!error->transcoder[i].power_domain_on)
13966 continue;
13967
13968 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13969
13970 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13971 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13972 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13973 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13974 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13975 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13976 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13977 }
13978
13979 return error;
13980 }
13981
13982 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13983
13984 void
13985 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13986 struct drm_device *dev,
13987 struct intel_display_error_state *error)
13988 {
13989 struct drm_i915_private *dev_priv = dev->dev_private;
13990 int i;
13991
13992 if (!error)
13993 return;
13994
13995 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13996 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13997 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13998 error->power_well_driver);
13999 for_each_pipe(dev_priv, i) {
14000 err_printf(m, "Pipe [%d]:\n", i);
14001 err_printf(m, " Power: %s\n",
14002 error->pipe[i].power_domain_on ? "on" : "off");
14003 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
14004 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
14005
14006 err_printf(m, "Plane [%d]:\n", i);
14007 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
14008 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
14009 if (INTEL_INFO(dev)->gen <= 3) {
14010 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
14011 err_printf(m, " POS: %08x\n", error->plane[i].pos);
14012 }
14013 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14014 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
14015 if (INTEL_INFO(dev)->gen >= 4) {
14016 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
14017 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
14018 }
14019
14020 err_printf(m, "Cursor [%d]:\n", i);
14021 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
14022 err_printf(m, " POS: %08x\n", error->cursor[i].position);
14023 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
14024 }
14025
14026 for (i = 0; i < error->num_transcoders; i++) {
14027 err_printf(m, "CPU transcoder: %c\n",
14028 transcoder_name(error->transcoder[i].cpu_transcoder));
14029 err_printf(m, " Power: %s\n",
14030 error->transcoder[i].power_domain_on ? "on" : "off");
14031 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
14032 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
14033 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
14034 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
14035 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
14036 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
14037 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
14038 }
14039 }
14040
14041 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
14042 {
14043 struct intel_crtc *crtc;
14044
14045 for_each_intel_crtc(dev, crtc) {
14046 struct intel_unpin_work *work;
14047
14048 spin_lock_irq(&dev->event_lock);
14049
14050 work = crtc->unpin_work;
14051
14052 if (work && work->event &&
14053 work->event->base.file_priv == file) {
14054 kfree(work->event);
14055 work->event = NULL;
14056 }
14057
14058 spin_unlock_irq(&dev->event_lock);
14059 }
14060 }
Linux kernel - Deliverables
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