projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
drm/i915: Don't use staged config to calculate mode_changed flags
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
47
48 /* Primary plane formats supported by all gen */
49 #define COMMON_PRIMARY_FORMATS \
50 DRM_FORMAT_C8, \
51 DRM_FORMAT_RGB565, \
52 DRM_FORMAT_XRGB8888, \
53 DRM_FORMAT_ARGB8888
54
55 /* Primary plane formats for gen <= 3 */
56 static const uint32_t intel_primary_formats_gen2[] = {
57 COMMON_PRIMARY_FORMATS,
58 DRM_FORMAT_XRGB1555,
59 DRM_FORMAT_ARGB1555,
60 };
61
62 /* Primary plane formats for gen >= 4 */
63 static const uint32_t intel_primary_formats_gen4[] = {
64 COMMON_PRIMARY_FORMATS, \
65 DRM_FORMAT_XBGR8888,
66 DRM_FORMAT_ABGR8888,
67 DRM_FORMAT_XRGB2101010,
68 DRM_FORMAT_ARGB2101010,
69 DRM_FORMAT_XBGR2101010,
70 DRM_FORMAT_ABGR2101010,
71 };
72
73 /* Cursor formats */
74 static const uint32_t intel_cursor_formats[] = {
75 DRM_FORMAT_ARGB8888,
76 };
77
78 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79
80 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
81 struct intel_crtc_state *pipe_config);
82 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
83 struct intel_crtc_state *pipe_config);
84
85 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
86 struct drm_atomic_state *state);
87 static int intel_framebuffer_init(struct drm_device *dev,
88 struct intel_framebuffer *ifb,
89 struct drm_mode_fb_cmd2 *mode_cmd,
90 struct drm_i915_gem_object *obj);
91 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
92 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
93 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
94 struct intel_link_m_n *m_n,
95 struct intel_link_m_n *m2_n2);
96 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
97 static void haswell_set_pipeconf(struct drm_crtc *crtc);
98 static void intel_set_pipe_csc(struct drm_crtc *crtc);
99 static void vlv_prepare_pll(struct intel_crtc *crtc,
100 const struct intel_crtc_state *pipe_config);
101 static void chv_prepare_pll(struct intel_crtc *crtc,
102 const struct intel_crtc_state *pipe_config);
103 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
104 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
105 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
106 struct intel_crtc_state *crtc_state);
107 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
108 int num_connectors);
109 static void intel_crtc_enable_planes(struct drm_crtc *crtc);
110 static void intel_crtc_disable_planes(struct drm_crtc *crtc);
111
112 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
113 {
114 if (!connector->mst_port)
115 return connector->encoder;
116 else
117 return &connector->mst_port->mst_encoders[pipe]->base;
118 }
119
120 typedef struct {
121 int min, max;
122 } intel_range_t;
123
124 typedef struct {
125 int dot_limit;
126 int p2_slow, p2_fast;
127 } intel_p2_t;
128
129 typedef struct intel_limit intel_limit_t;
130 struct intel_limit {
131 intel_range_t dot, vco, n, m, m1, m2, p, p1;
132 intel_p2_t p2;
133 };
134
135 int
136 intel_pch_rawclk(struct drm_device *dev)
137 {
138 struct drm_i915_private *dev_priv = dev->dev_private;
139
140 WARN_ON(!HAS_PCH_SPLIT(dev));
141
142 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
143 }
144
145 static inline u32 /* units of 100MHz */
146 intel_fdi_link_freq(struct drm_device *dev)
147 {
148 if (IS_GEN5(dev)) {
149 struct drm_i915_private *dev_priv = dev->dev_private;
150 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
151 } else
152 return 27;
153 }
154
155 static const intel_limit_t intel_limits_i8xx_dac = {
156 .dot = { .min = 25000, .max = 350000 },
157 .vco = { .min = 908000, .max = 1512000 },
158 .n = { .min = 2, .max = 16 },
159 .m = { .min = 96, .max = 140 },
160 .m1 = { .min = 18, .max = 26 },
161 .m2 = { .min = 6, .max = 16 },
162 .p = { .min = 4, .max = 128 },
163 .p1 = { .min = 2, .max = 33 },
164 .p2 = { .dot_limit = 165000,
165 .p2_slow = 4, .p2_fast = 2 },
166 };
167
168 static const intel_limit_t intel_limits_i8xx_dvo = {
169 .dot = { .min = 25000, .max = 350000 },
170 .vco = { .min = 908000, .max = 1512000 },
171 .n = { .min = 2, .max = 16 },
172 .m = { .min = 96, .max = 140 },
173 .m1 = { .min = 18, .max = 26 },
174 .m2 = { .min = 6, .max = 16 },
175 .p = { .min = 4, .max = 128 },
176 .p1 = { .min = 2, .max = 33 },
177 .p2 = { .dot_limit = 165000,
178 .p2_slow = 4, .p2_fast = 4 },
179 };
180
181 static const intel_limit_t intel_limits_i8xx_lvds = {
182 .dot = { .min = 25000, .max = 350000 },
183 .vco = { .min = 908000, .max = 1512000 },
184 .n = { .min = 2, .max = 16 },
185 .m = { .min = 96, .max = 140 },
186 .m1 = { .min = 18, .max = 26 },
187 .m2 = { .min = 6, .max = 16 },
188 .p = { .min = 4, .max = 128 },
189 .p1 = { .min = 1, .max = 6 },
190 .p2 = { .dot_limit = 165000,
191 .p2_slow = 14, .p2_fast = 7 },
192 };
193
194 static const intel_limit_t intel_limits_i9xx_sdvo = {
195 .dot = { .min = 20000, .max = 400000 },
196 .vco = { .min = 1400000, .max = 2800000 },
197 .n = { .min = 1, .max = 6 },
198 .m = { .min = 70, .max = 120 },
199 .m1 = { .min = 8, .max = 18 },
200 .m2 = { .min = 3, .max = 7 },
201 .p = { .min = 5, .max = 80 },
202 .p1 = { .min = 1, .max = 8 },
203 .p2 = { .dot_limit = 200000,
204 .p2_slow = 10, .p2_fast = 5 },
205 };
206
207 static const intel_limit_t intel_limits_i9xx_lvds = {
208 .dot = { .min = 20000, .max = 400000 },
209 .vco = { .min = 1400000, .max = 2800000 },
210 .n = { .min = 1, .max = 6 },
211 .m = { .min = 70, .max = 120 },
212 .m1 = { .min = 8, .max = 18 },
213 .m2 = { .min = 3, .max = 7 },
214 .p = { .min = 7, .max = 98 },
215 .p1 = { .min = 1, .max = 8 },
216 .p2 = { .dot_limit = 112000,
217 .p2_slow = 14, .p2_fast = 7 },
218 };
219
220
221 static const intel_limit_t intel_limits_g4x_sdvo = {
222 .dot = { .min = 25000, .max = 270000 },
223 .vco = { .min = 1750000, .max = 3500000},
224 .n = { .min = 1, .max = 4 },
225 .m = { .min = 104, .max = 138 },
226 .m1 = { .min = 17, .max = 23 },
227 .m2 = { .min = 5, .max = 11 },
228 .p = { .min = 10, .max = 30 },
229 .p1 = { .min = 1, .max = 3},
230 .p2 = { .dot_limit = 270000,
231 .p2_slow = 10,
232 .p2_fast = 10
233 },
234 };
235
236 static const intel_limit_t intel_limits_g4x_hdmi = {
237 .dot = { .min = 22000, .max = 400000 },
238 .vco = { .min = 1750000, .max = 3500000},
239 .n = { .min = 1, .max = 4 },
240 .m = { .min = 104, .max = 138 },
241 .m1 = { .min = 16, .max = 23 },
242 .m2 = { .min = 5, .max = 11 },
243 .p = { .min = 5, .max = 80 },
244 .p1 = { .min = 1, .max = 8},
245 .p2 = { .dot_limit = 165000,
246 .p2_slow = 10, .p2_fast = 5 },
247 };
248
249 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
250 .dot = { .min = 20000, .max = 115000 },
251 .vco = { .min = 1750000, .max = 3500000 },
252 .n = { .min = 1, .max = 3 },
253 .m = { .min = 104, .max = 138 },
254 .m1 = { .min = 17, .max = 23 },
255 .m2 = { .min = 5, .max = 11 },
256 .p = { .min = 28, .max = 112 },
257 .p1 = { .min = 2, .max = 8 },
258 .p2 = { .dot_limit = 0,
259 .p2_slow = 14, .p2_fast = 14
260 },
261 };
262
263 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
264 .dot = { .min = 80000, .max = 224000 },
265 .vco = { .min = 1750000, .max = 3500000 },
266 .n = { .min = 1, .max = 3 },
267 .m = { .min = 104, .max = 138 },
268 .m1 = { .min = 17, .max = 23 },
269 .m2 = { .min = 5, .max = 11 },
270 .p = { .min = 14, .max = 42 },
271 .p1 = { .min = 2, .max = 6 },
272 .p2 = { .dot_limit = 0,
273 .p2_slow = 7, .p2_fast = 7
274 },
275 };
276
277 static const intel_limit_t intel_limits_pineview_sdvo = {
278 .dot = { .min = 20000, .max = 400000},
279 .vco = { .min = 1700000, .max = 3500000 },
280 /* Pineview's Ncounter is a ring counter */
281 .n = { .min = 3, .max = 6 },
282 .m = { .min = 2, .max = 256 },
283 /* Pineview only has one combined m divider, which we treat as m2. */
284 .m1 = { .min = 0, .max = 0 },
285 .m2 = { .min = 0, .max = 254 },
286 .p = { .min = 5, .max = 80 },
287 .p1 = { .min = 1, .max = 8 },
288 .p2 = { .dot_limit = 200000,
289 .p2_slow = 10, .p2_fast = 5 },
290 };
291
292 static const intel_limit_t intel_limits_pineview_lvds = {
293 .dot = { .min = 20000, .max = 400000 },
294 .vco = { .min = 1700000, .max = 3500000 },
295 .n = { .min = 3, .max = 6 },
296 .m = { .min = 2, .max = 256 },
297 .m1 = { .min = 0, .max = 0 },
298 .m2 = { .min = 0, .max = 254 },
299 .p = { .min = 7, .max = 112 },
300 .p1 = { .min = 1, .max = 8 },
301 .p2 = { .dot_limit = 112000,
302 .p2_slow = 14, .p2_fast = 14 },
303 };
304
305 /* Ironlake / Sandybridge
306 *
307 * We calculate clock using (register_value + 2) for N/M1/M2, so here
308 * the range value for them is (actual_value - 2).
309 */
310 static const intel_limit_t intel_limits_ironlake_dac = {
311 .dot = { .min = 25000, .max = 350000 },
312 .vco = { .min = 1760000, .max = 3510000 },
313 .n = { .min = 1, .max = 5 },
314 .m = { .min = 79, .max = 127 },
315 .m1 = { .min = 12, .max = 22 },
316 .m2 = { .min = 5, .max = 9 },
317 .p = { .min = 5, .max = 80 },
318 .p1 = { .min = 1, .max = 8 },
319 .p2 = { .dot_limit = 225000,
320 .p2_slow = 10, .p2_fast = 5 },
321 };
322
323 static const intel_limit_t intel_limits_ironlake_single_lvds = {
324 .dot = { .min = 25000, .max = 350000 },
325 .vco = { .min = 1760000, .max = 3510000 },
326 .n = { .min = 1, .max = 3 },
327 .m = { .min = 79, .max = 118 },
328 .m1 = { .min = 12, .max = 22 },
329 .m2 = { .min = 5, .max = 9 },
330 .p = { .min = 28, .max = 112 },
331 .p1 = { .min = 2, .max = 8 },
332 .p2 = { .dot_limit = 225000,
333 .p2_slow = 14, .p2_fast = 14 },
334 };
335
336 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
337 .dot = { .min = 25000, .max = 350000 },
338 .vco = { .min = 1760000, .max = 3510000 },
339 .n = { .min = 1, .max = 3 },
340 .m = { .min = 79, .max = 127 },
341 .m1 = { .min = 12, .max = 22 },
342 .m2 = { .min = 5, .max = 9 },
343 .p = { .min = 14, .max = 56 },
344 .p1 = { .min = 2, .max = 8 },
345 .p2 = { .dot_limit = 225000,
346 .p2_slow = 7, .p2_fast = 7 },
347 };
348
349 /* LVDS 100mhz refclk limits. */
350 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
351 .dot = { .min = 25000, .max = 350000 },
352 .vco = { .min = 1760000, .max = 3510000 },
353 .n = { .min = 1, .max = 2 },
354 .m = { .min = 79, .max = 126 },
355 .m1 = { .min = 12, .max = 22 },
356 .m2 = { .min = 5, .max = 9 },
357 .p = { .min = 28, .max = 112 },
358 .p1 = { .min = 2, .max = 8 },
359 .p2 = { .dot_limit = 225000,
360 .p2_slow = 14, .p2_fast = 14 },
361 };
362
363 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
364 .dot = { .min = 25000, .max = 350000 },
365 .vco = { .min = 1760000, .max = 3510000 },
366 .n = { .min = 1, .max = 3 },
367 .m = { .min = 79, .max = 126 },
368 .m1 = { .min = 12, .max = 22 },
369 .m2 = { .min = 5, .max = 9 },
370 .p = { .min = 14, .max = 42 },
371 .p1 = { .min = 2, .max = 6 },
372 .p2 = { .dot_limit = 225000,
373 .p2_slow = 7, .p2_fast = 7 },
374 };
375
376 static const intel_limit_t intel_limits_vlv = {
377 /*
378 * These are the data rate limits (measured in fast clocks)
379 * since those are the strictest limits we have. The fast
380 * clock and actual rate limits are more relaxed, so checking
381 * them would make no difference.
382 */
383 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
384 .vco = { .min = 4000000, .max = 6000000 },
385 .n = { .min = 1, .max = 7 },
386 .m1 = { .min = 2, .max = 3 },
387 .m2 = { .min = 11, .max = 156 },
388 .p1 = { .min = 2, .max = 3 },
389 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
390 };
391
392 static const intel_limit_t intel_limits_chv = {
393 /*
394 * These are the data rate limits (measured in fast clocks)
395 * since those are the strictest limits we have. The fast
396 * clock and actual rate limits are more relaxed, so checking
397 * them would make no difference.
398 */
399 .dot = { .min = 25000 * 5, .max = 540000 * 5},
400 .vco = { .min = 4800000, .max = 6480000 },
401 .n = { .min = 1, .max = 1 },
402 .m1 = { .min = 2, .max = 2 },
403 .m2 = { .min = 24 << 22, .max = 175 << 22 },
404 .p1 = { .min = 2, .max = 4 },
405 .p2 = { .p2_slow = 1, .p2_fast = 14 },
406 };
407
408 static const intel_limit_t intel_limits_bxt = {
409 /* FIXME: find real dot limits */
410 .dot = { .min = 0, .max = INT_MAX },
411 .vco = { .min = 4800000, .max = 6480000 },
412 .n = { .min = 1, .max = 1 },
413 .m1 = { .min = 2, .max = 2 },
414 /* FIXME: find real m2 limits */
415 .m2 = { .min = 2 << 22, .max = 255 << 22 },
416 .p1 = { .min = 2, .max = 4 },
417 .p2 = { .p2_slow = 1, .p2_fast = 20 },
418 };
419
420 static void vlv_clock(int refclk, intel_clock_t *clock)
421 {
422 clock->m = clock->m1 * clock->m2;
423 clock->p = clock->p1 * clock->p2;
424 if (WARN_ON(clock->n == 0 || clock->p == 0))
425 return;
426 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
427 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
428 }
429
430 /**
431 * Returns whether any output on the specified pipe is of the specified type
432 */
433 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
434 {
435 struct drm_device *dev = crtc->base.dev;
436 struct intel_encoder *encoder;
437
438 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
439 if (encoder->type == type)
440 return true;
441
442 return false;
443 }
444
445 /**
446 * Returns whether any output on the specified pipe will have the specified
447 * type after a staged modeset is complete, i.e., the same as
448 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
449 * encoder->crtc.
450 */
451 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
452 int type)
453 {
454 struct drm_atomic_state *state = crtc_state->base.state;
455 struct drm_connector *connector;
456 struct drm_connector_state *connector_state;
457 struct intel_encoder *encoder;
458 int i, num_connectors = 0;
459
460 for_each_connector_in_state(state, connector, connector_state, i) {
461 if (connector_state->crtc != crtc_state->base.crtc)
462 continue;
463
464 num_connectors++;
465
466 encoder = to_intel_encoder(connector_state->best_encoder);
467 if (encoder->type == type)
468 return true;
469 }
470
471 WARN_ON(num_connectors == 0);
472
473 return false;
474 }
475
476 static const intel_limit_t *
477 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
478 {
479 struct drm_device *dev = crtc_state->base.crtc->dev;
480 const intel_limit_t *limit;
481
482 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
483 if (intel_is_dual_link_lvds(dev)) {
484 if (refclk == 100000)
485 limit = &intel_limits_ironlake_dual_lvds_100m;
486 else
487 limit = &intel_limits_ironlake_dual_lvds;
488 } else {
489 if (refclk == 100000)
490 limit = &intel_limits_ironlake_single_lvds_100m;
491 else
492 limit = &intel_limits_ironlake_single_lvds;
493 }
494 } else
495 limit = &intel_limits_ironlake_dac;
496
497 return limit;
498 }
499
500 static const intel_limit_t *
501 intel_g4x_limit(struct intel_crtc_state *crtc_state)
502 {
503 struct drm_device *dev = crtc_state->base.crtc->dev;
504 const intel_limit_t *limit;
505
506 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
507 if (intel_is_dual_link_lvds(dev))
508 limit = &intel_limits_g4x_dual_channel_lvds;
509 else
510 limit = &intel_limits_g4x_single_channel_lvds;
511 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
512 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
513 limit = &intel_limits_g4x_hdmi;
514 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
515 limit = &intel_limits_g4x_sdvo;
516 } else /* The option is for other outputs */
517 limit = &intel_limits_i9xx_sdvo;
518
519 return limit;
520 }
521
522 static const intel_limit_t *
523 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
524 {
525 struct drm_device *dev = crtc_state->base.crtc->dev;
526 const intel_limit_t *limit;
527
528 if (IS_BROXTON(dev))
529 limit = &intel_limits_bxt;
530 else if (HAS_PCH_SPLIT(dev))
531 limit = intel_ironlake_limit(crtc_state, refclk);
532 else if (IS_G4X(dev)) {
533 limit = intel_g4x_limit(crtc_state);
534 } else if (IS_PINEVIEW(dev)) {
535 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
536 limit = &intel_limits_pineview_lvds;
537 else
538 limit = &intel_limits_pineview_sdvo;
539 } else if (IS_CHERRYVIEW(dev)) {
540 limit = &intel_limits_chv;
541 } else if (IS_VALLEYVIEW(dev)) {
542 limit = &intel_limits_vlv;
543 } else if (!IS_GEN2(dev)) {
544 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
545 limit = &intel_limits_i9xx_lvds;
546 else
547 limit = &intel_limits_i9xx_sdvo;
548 } else {
549 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
550 limit = &intel_limits_i8xx_lvds;
551 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
552 limit = &intel_limits_i8xx_dvo;
553 else
554 limit = &intel_limits_i8xx_dac;
555 }
556 return limit;
557 }
558
559 /* m1 is reserved as 0 in Pineview, n is a ring counter */
560 static void pineview_clock(int refclk, intel_clock_t *clock)
561 {
562 clock->m = clock->m2 + 2;
563 clock->p = clock->p1 * clock->p2;
564 if (WARN_ON(clock->n == 0 || clock->p == 0))
565 return;
566 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
567 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
568 }
569
570 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
571 {
572 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
573 }
574
575 static void i9xx_clock(int refclk, intel_clock_t *clock)
576 {
577 clock->m = i9xx_dpll_compute_m(clock);
578 clock->p = clock->p1 * clock->p2;
579 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
580 return;
581 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
582 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
583 }
584
585 static void chv_clock(int refclk, intel_clock_t *clock)
586 {
587 clock->m = clock->m1 * clock->m2;
588 clock->p = clock->p1 * clock->p2;
589 if (WARN_ON(clock->n == 0 || clock->p == 0))
590 return;
591 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
592 clock->n << 22);
593 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
594 }
595
596 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
597 /**
598 * Returns whether the given set of divisors are valid for a given refclk with
599 * the given connectors.
600 */
601
602 static bool intel_PLL_is_valid(struct drm_device *dev,
603 const intel_limit_t *limit,
604 const intel_clock_t *clock)
605 {
606 if (clock->n < limit->n.min || limit->n.max < clock->n)
607 INTELPllInvalid("n out of range\n");
608 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
609 INTELPllInvalid("p1 out of range\n");
610 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
611 INTELPllInvalid("m2 out of range\n");
612 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
613 INTELPllInvalid("m1 out of range\n");
614
615 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
616 if (clock->m1 <= clock->m2)
617 INTELPllInvalid("m1 <= m2\n");
618
619 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
620 if (clock->p < limit->p.min || limit->p.max < clock->p)
621 INTELPllInvalid("p out of range\n");
622 if (clock->m < limit->m.min || limit->m.max < clock->m)
623 INTELPllInvalid("m out of range\n");
624 }
625
626 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
627 INTELPllInvalid("vco out of range\n");
628 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
629 * connector, etc., rather than just a single range.
630 */
631 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
632 INTELPllInvalid("dot out of range\n");
633
634 return true;
635 }
636
637 static bool
638 i9xx_find_best_dpll(const intel_limit_t *limit,
639 struct intel_crtc_state *crtc_state,
640 int target, int refclk, intel_clock_t *match_clock,
641 intel_clock_t *best_clock)
642 {
643 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
644 struct drm_device *dev = crtc->base.dev;
645 intel_clock_t clock;
646 int err = target;
647
648 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
649 /*
650 * For LVDS just rely on its current settings for dual-channel.
651 * We haven't figured out how to reliably set up different
652 * single/dual channel state, if we even can.
653 */
654 if (intel_is_dual_link_lvds(dev))
655 clock.p2 = limit->p2.p2_fast;
656 else
657 clock.p2 = limit->p2.p2_slow;
658 } else {
659 if (target < limit->p2.dot_limit)
660 clock.p2 = limit->p2.p2_slow;
661 else
662 clock.p2 = limit->p2.p2_fast;
663 }
664
665 memset(best_clock, 0, sizeof(*best_clock));
666
667 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
668 clock.m1++) {
669 for (clock.m2 = limit->m2.min;
670 clock.m2 <= limit->m2.max; clock.m2++) {
671 if (clock.m2 >= clock.m1)
672 break;
673 for (clock.n = limit->n.min;
674 clock.n <= limit->n.max; clock.n++) {
675 for (clock.p1 = limit->p1.min;
676 clock.p1 <= limit->p1.max; clock.p1++) {
677 int this_err;
678
679 i9xx_clock(refclk, &clock);
680 if (!intel_PLL_is_valid(dev, limit,
681 &clock))
682 continue;
683 if (match_clock &&
684 clock.p != match_clock->p)
685 continue;
686
687 this_err = abs(clock.dot - target);
688 if (this_err < err) {
689 *best_clock = clock;
690 err = this_err;
691 }
692 }
693 }
694 }
695 }
696
697 return (err != target);
698 }
699
700 static bool
701 pnv_find_best_dpll(const intel_limit_t *limit,
702 struct intel_crtc_state *crtc_state,
703 int target, int refclk, intel_clock_t *match_clock,
704 intel_clock_t *best_clock)
705 {
706 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
707 struct drm_device *dev = crtc->base.dev;
708 intel_clock_t clock;
709 int err = target;
710
711 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
712 /*
713 * For LVDS just rely on its current settings for dual-channel.
714 * We haven't figured out how to reliably set up different
715 * single/dual channel state, if we even can.
716 */
717 if (intel_is_dual_link_lvds(dev))
718 clock.p2 = limit->p2.p2_fast;
719 else
720 clock.p2 = limit->p2.p2_slow;
721 } else {
722 if (target < limit->p2.dot_limit)
723 clock.p2 = limit->p2.p2_slow;
724 else
725 clock.p2 = limit->p2.p2_fast;
726 }
727
728 memset(best_clock, 0, sizeof(*best_clock));
729
730 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
731 clock.m1++) {
732 for (clock.m2 = limit->m2.min;
733 clock.m2 <= limit->m2.max; clock.m2++) {
734 for (clock.n = limit->n.min;
735 clock.n <= limit->n.max; clock.n++) {
736 for (clock.p1 = limit->p1.min;
737 clock.p1 <= limit->p1.max; clock.p1++) {
738 int this_err;
739
740 pineview_clock(refclk, &clock);
741 if (!intel_PLL_is_valid(dev, limit,
742 &clock))
743 continue;
744 if (match_clock &&
745 clock.p != match_clock->p)
746 continue;
747
748 this_err = abs(clock.dot - target);
749 if (this_err < err) {
750 *best_clock = clock;
751 err = this_err;
752 }
753 }
754 }
755 }
756 }
757
758 return (err != target);
759 }
760
761 static bool
762 g4x_find_best_dpll(const intel_limit_t *limit,
763 struct intel_crtc_state *crtc_state,
764 int target, int refclk, intel_clock_t *match_clock,
765 intel_clock_t *best_clock)
766 {
767 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
768 struct drm_device *dev = crtc->base.dev;
769 intel_clock_t clock;
770 int max_n;
771 bool found;
772 /* approximately equals target * 0.00585 */
773 int err_most = (target >> 8) + (target >> 9);
774 found = false;
775
776 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
777 if (intel_is_dual_link_lvds(dev))
778 clock.p2 = limit->p2.p2_fast;
779 else
780 clock.p2 = limit->p2.p2_slow;
781 } else {
782 if (target < limit->p2.dot_limit)
783 clock.p2 = limit->p2.p2_slow;
784 else
785 clock.p2 = limit->p2.p2_fast;
786 }
787
788 memset(best_clock, 0, sizeof(*best_clock));
789 max_n = limit->n.max;
790 /* based on hardware requirement, prefer smaller n to precision */
791 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
792 /* based on hardware requirement, prefere larger m1,m2 */
793 for (clock.m1 = limit->m1.max;
794 clock.m1 >= limit->m1.min; clock.m1--) {
795 for (clock.m2 = limit->m2.max;
796 clock.m2 >= limit->m2.min; clock.m2--) {
797 for (clock.p1 = limit->p1.max;
798 clock.p1 >= limit->p1.min; clock.p1--) {
799 int this_err;
800
801 i9xx_clock(refclk, &clock);
802 if (!intel_PLL_is_valid(dev, limit,
803 &clock))
804 continue;
805
806 this_err = abs(clock.dot - target);
807 if (this_err < err_most) {
808 *best_clock = clock;
809 err_most = this_err;
810 max_n = clock.n;
811 found = true;
812 }
813 }
814 }
815 }
816 }
817 return found;
818 }
819
820 /*
821 * Check if the calculated PLL configuration is more optimal compared to the
822 * best configuration and error found so far. Return the calculated error.
823 */
824 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
825 const intel_clock_t *calculated_clock,
826 const intel_clock_t *best_clock,
827 unsigned int best_error_ppm,
828 unsigned int *error_ppm)
829 {
830 /*
831 * For CHV ignore the error and consider only the P value.
832 * Prefer a bigger P value based on HW requirements.
833 */
834 if (IS_CHERRYVIEW(dev)) {
835 *error_ppm = 0;
836
837 return calculated_clock->p > best_clock->p;
838 }
839
840 if (WARN_ON_ONCE(!target_freq))
841 return false;
842
843 *error_ppm = div_u64(1000000ULL *
844 abs(target_freq - calculated_clock->dot),
845 target_freq);
846 /*
847 * Prefer a better P value over a better (smaller) error if the error
848 * is small. Ensure this preference for future configurations too by
849 * setting the error to 0.
850 */
851 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
852 *error_ppm = 0;
853
854 return true;
855 }
856
857 return *error_ppm + 10 < best_error_ppm;
858 }
859
860 static bool
861 vlv_find_best_dpll(const intel_limit_t *limit,
862 struct intel_crtc_state *crtc_state,
863 int target, int refclk, intel_clock_t *match_clock,
864 intel_clock_t *best_clock)
865 {
866 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
867 struct drm_device *dev = crtc->base.dev;
868 intel_clock_t clock;
869 unsigned int bestppm = 1000000;
870 /* min update 19.2 MHz */
871 int max_n = min(limit->n.max, refclk / 19200);
872 bool found = false;
873
874 target *= 5; /* fast clock */
875
876 memset(best_clock, 0, sizeof(*best_clock));
877
878 /* based on hardware requirement, prefer smaller n to precision */
879 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
880 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
881 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
882 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
883 clock.p = clock.p1 * clock.p2;
884 /* based on hardware requirement, prefer bigger m1,m2 values */
885 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
886 unsigned int ppm;
887
888 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
889 refclk * clock.m1);
890
891 vlv_clock(refclk, &clock);
892
893 if (!intel_PLL_is_valid(dev, limit,
894 &clock))
895 continue;
896
897 if (!vlv_PLL_is_optimal(dev, target,
898 &clock,
899 best_clock,
900 bestppm, &ppm))
901 continue;
902
903 *best_clock = clock;
904 bestppm = ppm;
905 found = true;
906 }
907 }
908 }
909 }
910
911 return found;
912 }
913
914 static bool
915 chv_find_best_dpll(const intel_limit_t *limit,
916 struct intel_crtc_state *crtc_state,
917 int target, int refclk, intel_clock_t *match_clock,
918 intel_clock_t *best_clock)
919 {
920 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
921 struct drm_device *dev = crtc->base.dev;
922 unsigned int best_error_ppm;
923 intel_clock_t clock;
924 uint64_t m2;
925 int found = false;
926
927 memset(best_clock, 0, sizeof(*best_clock));
928 best_error_ppm = 1000000;
929
930 /*
931 * Based on hardware doc, the n always set to 1, and m1 always
932 * set to 2. If requires to support 200Mhz refclk, we need to
933 * revisit this because n may not 1 anymore.
934 */
935 clock.n = 1, clock.m1 = 2;
936 target *= 5; /* fast clock */
937
938 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
939 for (clock.p2 = limit->p2.p2_fast;
940 clock.p2 >= limit->p2.p2_slow;
941 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
942 unsigned int error_ppm;
943
944 clock.p = clock.p1 * clock.p2;
945
946 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
947 clock.n) << 22, refclk * clock.m1);
948
949 if (m2 > INT_MAX/clock.m1)
950 continue;
951
952 clock.m2 = m2;
953
954 chv_clock(refclk, &clock);
955
956 if (!intel_PLL_is_valid(dev, limit, &clock))
957 continue;
958
959 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
960 best_error_ppm, &error_ppm))
961 continue;
962
963 *best_clock = clock;
964 best_error_ppm = error_ppm;
965 found = true;
966 }
967 }
968
969 return found;
970 }
971
972 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
973 intel_clock_t *best_clock)
974 {
975 int refclk = i9xx_get_refclk(crtc_state, 0);
976
977 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
978 target_clock, refclk, NULL, best_clock);
979 }
980
981 bool intel_crtc_active(struct drm_crtc *crtc)
982 {
983 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
984
985 /* Be paranoid as we can arrive here with only partial
986 * state retrieved from the hardware during setup.
987 *
988 * We can ditch the adjusted_mode.crtc_clock check as soon
989 * as Haswell has gained clock readout/fastboot support.
990 *
991 * We can ditch the crtc->primary->fb check as soon as we can
992 * properly reconstruct framebuffers.
993 *
994 * FIXME: The intel_crtc->active here should be switched to
995 * crtc->state->active once we have proper CRTC states wired up
996 * for atomic.
997 */
998 return intel_crtc->active && crtc->primary->state->fb &&
999 intel_crtc->config->base.adjusted_mode.crtc_clock;
1000 }
1001
1002 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1003 enum pipe pipe)
1004 {
1005 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1006 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1007
1008 return intel_crtc->config->cpu_transcoder;
1009 }
1010
1011 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1012 {
1013 struct drm_i915_private *dev_priv = dev->dev_private;
1014 u32 reg = PIPEDSL(pipe);
1015 u32 line1, line2;
1016 u32 line_mask;
1017
1018 if (IS_GEN2(dev))
1019 line_mask = DSL_LINEMASK_GEN2;
1020 else
1021 line_mask = DSL_LINEMASK_GEN3;
1022
1023 line1 = I915_READ(reg) & line_mask;
1024 mdelay(5);
1025 line2 = I915_READ(reg) & line_mask;
1026
1027 return line1 == line2;
1028 }
1029
1030 /*
1031 * intel_wait_for_pipe_off - wait for pipe to turn off
1032 * @crtc: crtc whose pipe to wait for
1033 *
1034 * After disabling a pipe, we can't wait for vblank in the usual way,
1035 * spinning on the vblank interrupt status bit, since we won't actually
1036 * see an interrupt when the pipe is disabled.
1037 *
1038 * On Gen4 and above:
1039 * wait for the pipe register state bit to turn off
1040 *
1041 * Otherwise:
1042 * wait for the display line value to settle (it usually
1043 * ends up stopping at the start of the next frame).
1044 *
1045 */
1046 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1047 {
1048 struct drm_device *dev = crtc->base.dev;
1049 struct drm_i915_private *dev_priv = dev->dev_private;
1050 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1051 enum pipe pipe = crtc->pipe;
1052
1053 if (INTEL_INFO(dev)->gen >= 4) {
1054 int reg = PIPECONF(cpu_transcoder);
1055
1056 /* Wait for the Pipe State to go off */
1057 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1058 100))
1059 WARN(1, "pipe_off wait timed out\n");
1060 } else {
1061 /* Wait for the display line to settle */
1062 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1063 WARN(1, "pipe_off wait timed out\n");
1064 }
1065 }
1066
1067 /*
1068 * ibx_digital_port_connected - is the specified port connected?
1069 * @dev_priv: i915 private structure
1070 * @port: the port to test
1071 *
1072 * Returns true if @port is connected, false otherwise.
1073 */
1074 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1075 struct intel_digital_port *port)
1076 {
1077 u32 bit;
1078
1079 if (HAS_PCH_IBX(dev_priv->dev)) {
1080 switch (port->port) {
1081 case PORT_B:
1082 bit = SDE_PORTB_HOTPLUG;
1083 break;
1084 case PORT_C:
1085 bit = SDE_PORTC_HOTPLUG;
1086 break;
1087 case PORT_D:
1088 bit = SDE_PORTD_HOTPLUG;
1089 break;
1090 default:
1091 return true;
1092 }
1093 } else {
1094 switch (port->port) {
1095 case PORT_B:
1096 bit = SDE_PORTB_HOTPLUG_CPT;
1097 break;
1098 case PORT_C:
1099 bit = SDE_PORTC_HOTPLUG_CPT;
1100 break;
1101 case PORT_D:
1102 bit = SDE_PORTD_HOTPLUG_CPT;
1103 break;
1104 default:
1105 return true;
1106 }
1107 }
1108
1109 return I915_READ(SDEISR) & bit;
1110 }
1111
1112 static const char *state_string(bool enabled)
1113 {
1114 return enabled ? "on" : "off";
1115 }
1116
1117 /* Only for pre-ILK configs */
1118 void assert_pll(struct drm_i915_private *dev_priv,
1119 enum pipe pipe, bool state)
1120 {
1121 int reg;
1122 u32 val;
1123 bool cur_state;
1124
1125 reg = DPLL(pipe);
1126 val = I915_READ(reg);
1127 cur_state = !!(val & DPLL_VCO_ENABLE);
1128 I915_STATE_WARN(cur_state != state,
1129 "PLL state assertion failure (expected %s, current %s)\n",
1130 state_string(state), state_string(cur_state));
1131 }
1132
1133 /* XXX: the dsi pll is shared between MIPI DSI ports */
1134 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1135 {
1136 u32 val;
1137 bool cur_state;
1138
1139 mutex_lock(&dev_priv->dpio_lock);
1140 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1141 mutex_unlock(&dev_priv->dpio_lock);
1142
1143 cur_state = val & DSI_PLL_VCO_EN;
1144 I915_STATE_WARN(cur_state != state,
1145 "DSI PLL state assertion failure (expected %s, current %s)\n",
1146 state_string(state), state_string(cur_state));
1147 }
1148 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1149 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1150
1151 struct intel_shared_dpll *
1152 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1153 {
1154 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1155
1156 if (crtc->config->shared_dpll < 0)
1157 return NULL;
1158
1159 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1160 }
1161
1162 /* For ILK+ */
1163 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1164 struct intel_shared_dpll *pll,
1165 bool state)
1166 {
1167 bool cur_state;
1168 struct intel_dpll_hw_state hw_state;
1169
1170 if (WARN (!pll,
1171 "asserting DPLL %s with no DPLL\n", state_string(state)))
1172 return;
1173
1174 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1175 I915_STATE_WARN(cur_state != state,
1176 "%s assertion failure (expected %s, current %s)\n",
1177 pll->name, state_string(state), state_string(cur_state));
1178 }
1179
1180 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1181 enum pipe pipe, bool state)
1182 {
1183 int reg;
1184 u32 val;
1185 bool cur_state;
1186 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1187 pipe);
1188
1189 if (HAS_DDI(dev_priv->dev)) {
1190 /* DDI does not have a specific FDI_TX register */
1191 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1192 val = I915_READ(reg);
1193 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1194 } else {
1195 reg = FDI_TX_CTL(pipe);
1196 val = I915_READ(reg);
1197 cur_state = !!(val & FDI_TX_ENABLE);
1198 }
1199 I915_STATE_WARN(cur_state != state,
1200 "FDI TX state assertion failure (expected %s, current %s)\n",
1201 state_string(state), state_string(cur_state));
1202 }
1203 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1204 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1205
1206 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1207 enum pipe pipe, bool state)
1208 {
1209 int reg;
1210 u32 val;
1211 bool cur_state;
1212
1213 reg = FDI_RX_CTL(pipe);
1214 val = I915_READ(reg);
1215 cur_state = !!(val & FDI_RX_ENABLE);
1216 I915_STATE_WARN(cur_state != state,
1217 "FDI RX state assertion failure (expected %s, current %s)\n",
1218 state_string(state), state_string(cur_state));
1219 }
1220 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1221 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1222
1223 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1224 enum pipe pipe)
1225 {
1226 int reg;
1227 u32 val;
1228
1229 /* ILK FDI PLL is always enabled */
1230 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1231 return;
1232
1233 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1234 if (HAS_DDI(dev_priv->dev))
1235 return;
1236
1237 reg = FDI_TX_CTL(pipe);
1238 val = I915_READ(reg);
1239 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1240 }
1241
1242 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1243 enum pipe pipe, bool state)
1244 {
1245 int reg;
1246 u32 val;
1247 bool cur_state;
1248
1249 reg = FDI_RX_CTL(pipe);
1250 val = I915_READ(reg);
1251 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1252 I915_STATE_WARN(cur_state != state,
1253 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1254 state_string(state), state_string(cur_state));
1255 }
1256
1257 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1258 enum pipe pipe)
1259 {
1260 struct drm_device *dev = dev_priv->dev;
1261 int pp_reg;
1262 u32 val;
1263 enum pipe panel_pipe = PIPE_A;
1264 bool locked = true;
1265
1266 if (WARN_ON(HAS_DDI(dev)))
1267 return;
1268
1269 if (HAS_PCH_SPLIT(dev)) {
1270 u32 port_sel;
1271
1272 pp_reg = PCH_PP_CONTROL;
1273 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1274
1275 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1276 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1277 panel_pipe = PIPE_B;
1278 /* XXX: else fix for eDP */
1279 } else if (IS_VALLEYVIEW(dev)) {
1280 /* presumably write lock depends on pipe, not port select */
1281 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1282 panel_pipe = pipe;
1283 } else {
1284 pp_reg = PP_CONTROL;
1285 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1286 panel_pipe = PIPE_B;
1287 }
1288
1289 val = I915_READ(pp_reg);
1290 if (!(val & PANEL_POWER_ON) ||
1291 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1292 locked = false;
1293
1294 I915_STATE_WARN(panel_pipe == pipe && locked,
1295 "panel assertion failure, pipe %c regs locked\n",
1296 pipe_name(pipe));
1297 }
1298
1299 static void assert_cursor(struct drm_i915_private *dev_priv,
1300 enum pipe pipe, bool state)
1301 {
1302 struct drm_device *dev = dev_priv->dev;
1303 bool cur_state;
1304
1305 if (IS_845G(dev) || IS_I865G(dev))
1306 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1307 else
1308 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1309
1310 I915_STATE_WARN(cur_state != state,
1311 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1312 pipe_name(pipe), state_string(state), state_string(cur_state));
1313 }
1314 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1315 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1316
1317 void assert_pipe(struct drm_i915_private *dev_priv,
1318 enum pipe pipe, bool state)
1319 {
1320 int reg;
1321 u32 val;
1322 bool cur_state;
1323 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1324 pipe);
1325
1326 /* if we need the pipe quirk it must be always on */
1327 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1328 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1329 state = true;
1330
1331 if (!intel_display_power_is_enabled(dev_priv,
1332 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1333 cur_state = false;
1334 } else {
1335 reg = PIPECONF(cpu_transcoder);
1336 val = I915_READ(reg);
1337 cur_state = !!(val & PIPECONF_ENABLE);
1338 }
1339
1340 I915_STATE_WARN(cur_state != state,
1341 "pipe %c assertion failure (expected %s, current %s)\n",
1342 pipe_name(pipe), state_string(state), state_string(cur_state));
1343 }
1344
1345 static void assert_plane(struct drm_i915_private *dev_priv,
1346 enum plane plane, bool state)
1347 {
1348 int reg;
1349 u32 val;
1350 bool cur_state;
1351
1352 reg = DSPCNTR(plane);
1353 val = I915_READ(reg);
1354 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1355 I915_STATE_WARN(cur_state != state,
1356 "plane %c assertion failure (expected %s, current %s)\n",
1357 plane_name(plane), state_string(state), state_string(cur_state));
1358 }
1359
1360 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1361 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1362
1363 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1364 enum pipe pipe)
1365 {
1366 struct drm_device *dev = dev_priv->dev;
1367 int reg, i;
1368 u32 val;
1369 int cur_pipe;
1370
1371 /* Primary planes are fixed to pipes on gen4+ */
1372 if (INTEL_INFO(dev)->gen >= 4) {
1373 reg = DSPCNTR(pipe);
1374 val = I915_READ(reg);
1375 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1376 "plane %c assertion failure, should be disabled but not\n",
1377 plane_name(pipe));
1378 return;
1379 }
1380
1381 /* Need to check both planes against the pipe */
1382 for_each_pipe(dev_priv, i) {
1383 reg = DSPCNTR(i);
1384 val = I915_READ(reg);
1385 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1386 DISPPLANE_SEL_PIPE_SHIFT;
1387 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1388 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1389 plane_name(i), pipe_name(pipe));
1390 }
1391 }
1392
1393 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1394 enum pipe pipe)
1395 {
1396 struct drm_device *dev = dev_priv->dev;
1397 int reg, sprite;
1398 u32 val;
1399
1400 if (INTEL_INFO(dev)->gen >= 9) {
1401 for_each_sprite(dev_priv, pipe, sprite) {
1402 val = I915_READ(PLANE_CTL(pipe, sprite));
1403 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1404 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1405 sprite, pipe_name(pipe));
1406 }
1407 } else if (IS_VALLEYVIEW(dev)) {
1408 for_each_sprite(dev_priv, pipe, sprite) {
1409 reg = SPCNTR(pipe, sprite);
1410 val = I915_READ(reg);
1411 I915_STATE_WARN(val & SP_ENABLE,
1412 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1413 sprite_name(pipe, sprite), pipe_name(pipe));
1414 }
1415 } else if (INTEL_INFO(dev)->gen >= 7) {
1416 reg = SPRCTL(pipe);
1417 val = I915_READ(reg);
1418 I915_STATE_WARN(val & SPRITE_ENABLE,
1419 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1420 plane_name(pipe), pipe_name(pipe));
1421 } else if (INTEL_INFO(dev)->gen >= 5) {
1422 reg = DVSCNTR(pipe);
1423 val = I915_READ(reg);
1424 I915_STATE_WARN(val & DVS_ENABLE,
1425 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1426 plane_name(pipe), pipe_name(pipe));
1427 }
1428 }
1429
1430 static void assert_vblank_disabled(struct drm_crtc *crtc)
1431 {
1432 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1433 drm_crtc_vblank_put(crtc);
1434 }
1435
1436 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1437 {
1438 u32 val;
1439 bool enabled;
1440
1441 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1442
1443 val = I915_READ(PCH_DREF_CONTROL);
1444 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1445 DREF_SUPERSPREAD_SOURCE_MASK));
1446 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1447 }
1448
1449 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1450 enum pipe pipe)
1451 {
1452 int reg;
1453 u32 val;
1454 bool enabled;
1455
1456 reg = PCH_TRANSCONF(pipe);
1457 val = I915_READ(reg);
1458 enabled = !!(val & TRANS_ENABLE);
1459 I915_STATE_WARN(enabled,
1460 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1461 pipe_name(pipe));
1462 }
1463
1464 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1465 enum pipe pipe, u32 port_sel, u32 val)
1466 {
1467 if ((val & DP_PORT_EN) == 0)
1468 return false;
1469
1470 if (HAS_PCH_CPT(dev_priv->dev)) {
1471 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1472 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1473 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1474 return false;
1475 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1476 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1477 return false;
1478 } else {
1479 if ((val & DP_PIPE_MASK) != (pipe << 30))
1480 return false;
1481 }
1482 return true;
1483 }
1484
1485 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1486 enum pipe pipe, u32 val)
1487 {
1488 if ((val & SDVO_ENABLE) == 0)
1489 return false;
1490
1491 if (HAS_PCH_CPT(dev_priv->dev)) {
1492 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1493 return false;
1494 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1495 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1496 return false;
1497 } else {
1498 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1499 return false;
1500 }
1501 return true;
1502 }
1503
1504 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1505 enum pipe pipe, u32 val)
1506 {
1507 if ((val & LVDS_PORT_EN) == 0)
1508 return false;
1509
1510 if (HAS_PCH_CPT(dev_priv->dev)) {
1511 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1512 return false;
1513 } else {
1514 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1515 return false;
1516 }
1517 return true;
1518 }
1519
1520 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1521 enum pipe pipe, u32 val)
1522 {
1523 if ((val & ADPA_DAC_ENABLE) == 0)
1524 return false;
1525 if (HAS_PCH_CPT(dev_priv->dev)) {
1526 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1527 return false;
1528 } else {
1529 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1530 return false;
1531 }
1532 return true;
1533 }
1534
1535 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1536 enum pipe pipe, int reg, u32 port_sel)
1537 {
1538 u32 val = I915_READ(reg);
1539 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1540 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1541 reg, pipe_name(pipe));
1542
1543 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1544 && (val & DP_PIPEB_SELECT),
1545 "IBX PCH dp port still using transcoder B\n");
1546 }
1547
1548 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1549 enum pipe pipe, int reg)
1550 {
1551 u32 val = I915_READ(reg);
1552 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1553 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1554 reg, pipe_name(pipe));
1555
1556 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1557 && (val & SDVO_PIPE_B_SELECT),
1558 "IBX PCH hdmi port still using transcoder B\n");
1559 }
1560
1561 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1562 enum pipe pipe)
1563 {
1564 int reg;
1565 u32 val;
1566
1567 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1568 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1569 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1570
1571 reg = PCH_ADPA;
1572 val = I915_READ(reg);
1573 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1574 "PCH VGA enabled on transcoder %c, should be disabled\n",
1575 pipe_name(pipe));
1576
1577 reg = PCH_LVDS;
1578 val = I915_READ(reg);
1579 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1580 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1581 pipe_name(pipe));
1582
1583 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1584 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1585 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1586 }
1587
1588 static void intel_init_dpio(struct drm_device *dev)
1589 {
1590 struct drm_i915_private *dev_priv = dev->dev_private;
1591
1592 if (!IS_VALLEYVIEW(dev))
1593 return;
1594
1595 /*
1596 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1597 * CHV x1 PHY (DP/HDMI D)
1598 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1599 */
1600 if (IS_CHERRYVIEW(dev)) {
1601 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1602 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1603 } else {
1604 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1605 }
1606 }
1607
1608 static void vlv_enable_pll(struct intel_crtc *crtc,
1609 const struct intel_crtc_state *pipe_config)
1610 {
1611 struct drm_device *dev = crtc->base.dev;
1612 struct drm_i915_private *dev_priv = dev->dev_private;
1613 int reg = DPLL(crtc->pipe);
1614 u32 dpll = pipe_config->dpll_hw_state.dpll;
1615
1616 assert_pipe_disabled(dev_priv, crtc->pipe);
1617
1618 /* No really, not for ILK+ */
1619 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1620
1621 /* PLL is protected by panel, make sure we can write it */
1622 if (IS_MOBILE(dev_priv->dev))
1623 assert_panel_unlocked(dev_priv, crtc->pipe);
1624
1625 I915_WRITE(reg, dpll);
1626 POSTING_READ(reg);
1627 udelay(150);
1628
1629 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1630 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1631
1632 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1633 POSTING_READ(DPLL_MD(crtc->pipe));
1634
1635 /* We do this three times for luck */
1636 I915_WRITE(reg, dpll);
1637 POSTING_READ(reg);
1638 udelay(150); /* wait for warmup */
1639 I915_WRITE(reg, dpll);
1640 POSTING_READ(reg);
1641 udelay(150); /* wait for warmup */
1642 I915_WRITE(reg, dpll);
1643 POSTING_READ(reg);
1644 udelay(150); /* wait for warmup */
1645 }
1646
1647 static void chv_enable_pll(struct intel_crtc *crtc,
1648 const struct intel_crtc_state *pipe_config)
1649 {
1650 struct drm_device *dev = crtc->base.dev;
1651 struct drm_i915_private *dev_priv = dev->dev_private;
1652 int pipe = crtc->pipe;
1653 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1654 u32 tmp;
1655
1656 assert_pipe_disabled(dev_priv, crtc->pipe);
1657
1658 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1659
1660 mutex_lock(&dev_priv->dpio_lock);
1661
1662 /* Enable back the 10bit clock to display controller */
1663 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1664 tmp |= DPIO_DCLKP_EN;
1665 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1666
1667 /*
1668 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1669 */
1670 udelay(1);
1671
1672 /* Enable PLL */
1673 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1674
1675 /* Check PLL is locked */
1676 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1677 DRM_ERROR("PLL %d failed to lock\n", pipe);
1678
1679 /* not sure when this should be written */
1680 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1681 POSTING_READ(DPLL_MD(pipe));
1682
1683 mutex_unlock(&dev_priv->dpio_lock);
1684 }
1685
1686 static int intel_num_dvo_pipes(struct drm_device *dev)
1687 {
1688 struct intel_crtc *crtc;
1689 int count = 0;
1690
1691 for_each_intel_crtc(dev, crtc)
1692 count += crtc->active &&
1693 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1694
1695 return count;
1696 }
1697
1698 static void i9xx_enable_pll(struct intel_crtc *crtc)
1699 {
1700 struct drm_device *dev = crtc->base.dev;
1701 struct drm_i915_private *dev_priv = dev->dev_private;
1702 int reg = DPLL(crtc->pipe);
1703 u32 dpll = crtc->config->dpll_hw_state.dpll;
1704
1705 assert_pipe_disabled(dev_priv, crtc->pipe);
1706
1707 /* No really, not for ILK+ */
1708 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1709
1710 /* PLL is protected by panel, make sure we can write it */
1711 if (IS_MOBILE(dev) && !IS_I830(dev))
1712 assert_panel_unlocked(dev_priv, crtc->pipe);
1713
1714 /* Enable DVO 2x clock on both PLLs if necessary */
1715 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1716 /*
1717 * It appears to be important that we don't enable this
1718 * for the current pipe before otherwise configuring the
1719 * PLL. No idea how this should be handled if multiple
1720 * DVO outputs are enabled simultaneosly.
1721 */
1722 dpll |= DPLL_DVO_2X_MODE;
1723 I915_WRITE(DPLL(!crtc->pipe),
1724 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1725 }
1726
1727 /* Wait for the clocks to stabilize. */
1728 POSTING_READ(reg);
1729 udelay(150);
1730
1731 if (INTEL_INFO(dev)->gen >= 4) {
1732 I915_WRITE(DPLL_MD(crtc->pipe),
1733 crtc->config->dpll_hw_state.dpll_md);
1734 } else {
1735 /* The pixel multiplier can only be updated once the
1736 * DPLL is enabled and the clocks are stable.
1737 *
1738 * So write it again.
1739 */
1740 I915_WRITE(reg, dpll);
1741 }
1742
1743 /* We do this three times for luck */
1744 I915_WRITE(reg, dpll);
1745 POSTING_READ(reg);
1746 udelay(150); /* wait for warmup */
1747 I915_WRITE(reg, dpll);
1748 POSTING_READ(reg);
1749 udelay(150); /* wait for warmup */
1750 I915_WRITE(reg, dpll);
1751 POSTING_READ(reg);
1752 udelay(150); /* wait for warmup */
1753 }
1754
1755 /**
1756 * i9xx_disable_pll - disable a PLL
1757 * @dev_priv: i915 private structure
1758 * @pipe: pipe PLL to disable
1759 *
1760 * Disable the PLL for @pipe, making sure the pipe is off first.
1761 *
1762 * Note! This is for pre-ILK only.
1763 */
1764 static void i9xx_disable_pll(struct intel_crtc *crtc)
1765 {
1766 struct drm_device *dev = crtc->base.dev;
1767 struct drm_i915_private *dev_priv = dev->dev_private;
1768 enum pipe pipe = crtc->pipe;
1769
1770 /* Disable DVO 2x clock on both PLLs if necessary */
1771 if (IS_I830(dev) &&
1772 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1773 intel_num_dvo_pipes(dev) == 1) {
1774 I915_WRITE(DPLL(PIPE_B),
1775 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1776 I915_WRITE(DPLL(PIPE_A),
1777 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1778 }
1779
1780 /* Don't disable pipe or pipe PLLs if needed */
1781 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1782 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1783 return;
1784
1785 /* Make sure the pipe isn't still relying on us */
1786 assert_pipe_disabled(dev_priv, pipe);
1787
1788 I915_WRITE(DPLL(pipe), 0);
1789 POSTING_READ(DPLL(pipe));
1790 }
1791
1792 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1793 {
1794 u32 val = 0;
1795
1796 /* Make sure the pipe isn't still relying on us */
1797 assert_pipe_disabled(dev_priv, pipe);
1798
1799 /*
1800 * Leave integrated clock source and reference clock enabled for pipe B.
1801 * The latter is needed for VGA hotplug / manual detection.
1802 */
1803 if (pipe == PIPE_B)
1804 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1805 I915_WRITE(DPLL(pipe), val);
1806 POSTING_READ(DPLL(pipe));
1807
1808 }
1809
1810 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1811 {
1812 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1813 u32 val;
1814
1815 /* Make sure the pipe isn't still relying on us */
1816 assert_pipe_disabled(dev_priv, pipe);
1817
1818 /* Set PLL en = 0 */
1819 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1820 if (pipe != PIPE_A)
1821 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1822 I915_WRITE(DPLL(pipe), val);
1823 POSTING_READ(DPLL(pipe));
1824
1825 mutex_lock(&dev_priv->dpio_lock);
1826
1827 /* Disable 10bit clock to display controller */
1828 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1829 val &= ~DPIO_DCLKP_EN;
1830 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1831
1832 /* disable left/right clock distribution */
1833 if (pipe != PIPE_B) {
1834 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1835 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1836 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1837 } else {
1838 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1839 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1840 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1841 }
1842
1843 mutex_unlock(&dev_priv->dpio_lock);
1844 }
1845
1846 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1847 struct intel_digital_port *dport)
1848 {
1849 u32 port_mask;
1850 int dpll_reg;
1851
1852 switch (dport->port) {
1853 case PORT_B:
1854 port_mask = DPLL_PORTB_READY_MASK;
1855 dpll_reg = DPLL(0);
1856 break;
1857 case PORT_C:
1858 port_mask = DPLL_PORTC_READY_MASK;
1859 dpll_reg = DPLL(0);
1860 break;
1861 case PORT_D:
1862 port_mask = DPLL_PORTD_READY_MASK;
1863 dpll_reg = DPIO_PHY_STATUS;
1864 break;
1865 default:
1866 BUG();
1867 }
1868
1869 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1870 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1871 port_name(dport->port), I915_READ(dpll_reg));
1872 }
1873
1874 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1875 {
1876 struct drm_device *dev = crtc->base.dev;
1877 struct drm_i915_private *dev_priv = dev->dev_private;
1878 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1879
1880 if (WARN_ON(pll == NULL))
1881 return;
1882
1883 WARN_ON(!pll->config.crtc_mask);
1884 if (pll->active == 0) {
1885 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1886 WARN_ON(pll->on);
1887 assert_shared_dpll_disabled(dev_priv, pll);
1888
1889 pll->mode_set(dev_priv, pll);
1890 }
1891 }
1892
1893 /**
1894 * intel_enable_shared_dpll - enable PCH PLL
1895 * @dev_priv: i915 private structure
1896 * @pipe: pipe PLL to enable
1897 *
1898 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1899 * drives the transcoder clock.
1900 */
1901 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1902 {
1903 struct drm_device *dev = crtc->base.dev;
1904 struct drm_i915_private *dev_priv = dev->dev_private;
1905 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1906
1907 if (WARN_ON(pll == NULL))
1908 return;
1909
1910 if (WARN_ON(pll->config.crtc_mask == 0))
1911 return;
1912
1913 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1914 pll->name, pll->active, pll->on,
1915 crtc->base.base.id);
1916
1917 if (pll->active++) {
1918 WARN_ON(!pll->on);
1919 assert_shared_dpll_enabled(dev_priv, pll);
1920 return;
1921 }
1922 WARN_ON(pll->on);
1923
1924 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1925
1926 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1927 pll->enable(dev_priv, pll);
1928 pll->on = true;
1929 }
1930
1931 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1932 {
1933 struct drm_device *dev = crtc->base.dev;
1934 struct drm_i915_private *dev_priv = dev->dev_private;
1935 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1936
1937 /* PCH only available on ILK+ */
1938 BUG_ON(INTEL_INFO(dev)->gen < 5);
1939 if (WARN_ON(pll == NULL))
1940 return;
1941
1942 if (WARN_ON(pll->config.crtc_mask == 0))
1943 return;
1944
1945 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1946 pll->name, pll->active, pll->on,
1947 crtc->base.base.id);
1948
1949 if (WARN_ON(pll->active == 0)) {
1950 assert_shared_dpll_disabled(dev_priv, pll);
1951 return;
1952 }
1953
1954 assert_shared_dpll_enabled(dev_priv, pll);
1955 WARN_ON(!pll->on);
1956 if (--pll->active)
1957 return;
1958
1959 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1960 pll->disable(dev_priv, pll);
1961 pll->on = false;
1962
1963 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1964 }
1965
1966 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1967 enum pipe pipe)
1968 {
1969 struct drm_device *dev = dev_priv->dev;
1970 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1971 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1972 uint32_t reg, val, pipeconf_val;
1973
1974 /* PCH only available on ILK+ */
1975 BUG_ON(!HAS_PCH_SPLIT(dev));
1976
1977 /* Make sure PCH DPLL is enabled */
1978 assert_shared_dpll_enabled(dev_priv,
1979 intel_crtc_to_shared_dpll(intel_crtc));
1980
1981 /* FDI must be feeding us bits for PCH ports */
1982 assert_fdi_tx_enabled(dev_priv, pipe);
1983 assert_fdi_rx_enabled(dev_priv, pipe);
1984
1985 if (HAS_PCH_CPT(dev)) {
1986 /* Workaround: Set the timing override bit before enabling the
1987 * pch transcoder. */
1988 reg = TRANS_CHICKEN2(pipe);
1989 val = I915_READ(reg);
1990 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1991 I915_WRITE(reg, val);
1992 }
1993
1994 reg = PCH_TRANSCONF(pipe);
1995 val = I915_READ(reg);
1996 pipeconf_val = I915_READ(PIPECONF(pipe));
1997
1998 if (HAS_PCH_IBX(dev_priv->dev)) {
1999 /*
2000 * make the BPC in transcoder be consistent with
2001 * that in pipeconf reg.
2002 */
2003 val &= ~PIPECONF_BPC_MASK;
2004 val |= pipeconf_val & PIPECONF_BPC_MASK;
2005 }
2006
2007 val &= ~TRANS_INTERLACE_MASK;
2008 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2009 if (HAS_PCH_IBX(dev_priv->dev) &&
2010 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2011 val |= TRANS_LEGACY_INTERLACED_ILK;
2012 else
2013 val |= TRANS_INTERLACED;
2014 else
2015 val |= TRANS_PROGRESSIVE;
2016
2017 I915_WRITE(reg, val | TRANS_ENABLE);
2018 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2019 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2020 }
2021
2022 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2023 enum transcoder cpu_transcoder)
2024 {
2025 u32 val, pipeconf_val;
2026
2027 /* PCH only available on ILK+ */
2028 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2029
2030 /* FDI must be feeding us bits for PCH ports */
2031 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2032 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2033
2034 /* Workaround: set timing override bit. */
2035 val = I915_READ(_TRANSA_CHICKEN2);
2036 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2037 I915_WRITE(_TRANSA_CHICKEN2, val);
2038
2039 val = TRANS_ENABLE;
2040 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2041
2042 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2043 PIPECONF_INTERLACED_ILK)
2044 val |= TRANS_INTERLACED;
2045 else
2046 val |= TRANS_PROGRESSIVE;
2047
2048 I915_WRITE(LPT_TRANSCONF, val);
2049 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2050 DRM_ERROR("Failed to enable PCH transcoder\n");
2051 }
2052
2053 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2054 enum pipe pipe)
2055 {
2056 struct drm_device *dev = dev_priv->dev;
2057 uint32_t reg, val;
2058
2059 /* FDI relies on the transcoder */
2060 assert_fdi_tx_disabled(dev_priv, pipe);
2061 assert_fdi_rx_disabled(dev_priv, pipe);
2062
2063 /* Ports must be off as well */
2064 assert_pch_ports_disabled(dev_priv, pipe);
2065
2066 reg = PCH_TRANSCONF(pipe);
2067 val = I915_READ(reg);
2068 val &= ~TRANS_ENABLE;
2069 I915_WRITE(reg, val);
2070 /* wait for PCH transcoder off, transcoder state */
2071 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2072 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2073
2074 if (!HAS_PCH_IBX(dev)) {
2075 /* Workaround: Clear the timing override chicken bit again. */
2076 reg = TRANS_CHICKEN2(pipe);
2077 val = I915_READ(reg);
2078 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2079 I915_WRITE(reg, val);
2080 }
2081 }
2082
2083 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2084 {
2085 u32 val;
2086
2087 val = I915_READ(LPT_TRANSCONF);
2088 val &= ~TRANS_ENABLE;
2089 I915_WRITE(LPT_TRANSCONF, val);
2090 /* wait for PCH transcoder off, transcoder state */
2091 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2092 DRM_ERROR("Failed to disable PCH transcoder\n");
2093
2094 /* Workaround: clear timing override bit. */
2095 val = I915_READ(_TRANSA_CHICKEN2);
2096 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2097 I915_WRITE(_TRANSA_CHICKEN2, val);
2098 }
2099
2100 /**
2101 * intel_enable_pipe - enable a pipe, asserting requirements
2102 * @crtc: crtc responsible for the pipe
2103 *
2104 * Enable @crtc's pipe, making sure that various hardware specific requirements
2105 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2106 */
2107 static void intel_enable_pipe(struct intel_crtc *crtc)
2108 {
2109 struct drm_device *dev = crtc->base.dev;
2110 struct drm_i915_private *dev_priv = dev->dev_private;
2111 enum pipe pipe = crtc->pipe;
2112 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2113 pipe);
2114 enum pipe pch_transcoder;
2115 int reg;
2116 u32 val;
2117
2118 assert_planes_disabled(dev_priv, pipe);
2119 assert_cursor_disabled(dev_priv, pipe);
2120 assert_sprites_disabled(dev_priv, pipe);
2121
2122 if (HAS_PCH_LPT(dev_priv->dev))
2123 pch_transcoder = TRANSCODER_A;
2124 else
2125 pch_transcoder = pipe;
2126
2127 /*
2128 * A pipe without a PLL won't actually be able to drive bits from
2129 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2130 * need the check.
2131 */
2132 if (HAS_GMCH_DISPLAY(dev_priv->dev))
2133 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2134 assert_dsi_pll_enabled(dev_priv);
2135 else
2136 assert_pll_enabled(dev_priv, pipe);
2137 else {
2138 if (crtc->config->has_pch_encoder) {
2139 /* if driving the PCH, we need FDI enabled */
2140 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2141 assert_fdi_tx_pll_enabled(dev_priv,
2142 (enum pipe) cpu_transcoder);
2143 }
2144 /* FIXME: assert CPU port conditions for SNB+ */
2145 }
2146
2147 reg = PIPECONF(cpu_transcoder);
2148 val = I915_READ(reg);
2149 if (val & PIPECONF_ENABLE) {
2150 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2151 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2152 return;
2153 }
2154
2155 I915_WRITE(reg, val | PIPECONF_ENABLE);
2156 POSTING_READ(reg);
2157 }
2158
2159 /**
2160 * intel_disable_pipe - disable a pipe, asserting requirements
2161 * @crtc: crtc whose pipes is to be disabled
2162 *
2163 * Disable the pipe of @crtc, making sure that various hardware
2164 * specific requirements are met, if applicable, e.g. plane
2165 * disabled, panel fitter off, etc.
2166 *
2167 * Will wait until the pipe has shut down before returning.
2168 */
2169 static void intel_disable_pipe(struct intel_crtc *crtc)
2170 {
2171 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2172 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2173 enum pipe pipe = crtc->pipe;
2174 int reg;
2175 u32 val;
2176
2177 /*
2178 * Make sure planes won't keep trying to pump pixels to us,
2179 * or we might hang the display.
2180 */
2181 assert_planes_disabled(dev_priv, pipe);
2182 assert_cursor_disabled(dev_priv, pipe);
2183 assert_sprites_disabled(dev_priv, pipe);
2184
2185 reg = PIPECONF(cpu_transcoder);
2186 val = I915_READ(reg);
2187 if ((val & PIPECONF_ENABLE) == 0)
2188 return;
2189
2190 /*
2191 * Double wide has implications for planes
2192 * so best keep it disabled when not needed.
2193 */
2194 if (crtc->config->double_wide)
2195 val &= ~PIPECONF_DOUBLE_WIDE;
2196
2197 /* Don't disable pipe or pipe PLLs if needed */
2198 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2199 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2200 val &= ~PIPECONF_ENABLE;
2201
2202 I915_WRITE(reg, val);
2203 if ((val & PIPECONF_ENABLE) == 0)
2204 intel_wait_for_pipe_off(crtc);
2205 }
2206
2207 /*
2208 * Plane regs are double buffered, going from enabled->disabled needs a
2209 * trigger in order to latch. The display address reg provides this.
2210 */
2211 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2212 enum plane plane)
2213 {
2214 struct drm_device *dev = dev_priv->dev;
2215 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2216
2217 I915_WRITE(reg, I915_READ(reg));
2218 POSTING_READ(reg);
2219 }
2220
2221 /**
2222 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2223 * @plane: plane to be enabled
2224 * @crtc: crtc for the plane
2225 *
2226 * Enable @plane on @crtc, making sure that the pipe is running first.
2227 */
2228 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2229 struct drm_crtc *crtc)
2230 {
2231 struct drm_device *dev = plane->dev;
2232 struct drm_i915_private *dev_priv = dev->dev_private;
2233 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2234
2235 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2236 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2237 to_intel_plane_state(plane->state)->visible = true;
2238
2239 dev_priv->display.update_primary_plane(crtc, plane->fb,
2240 crtc->x, crtc->y);
2241 }
2242
2243 static bool need_vtd_wa(struct drm_device *dev)
2244 {
2245 #ifdef CONFIG_INTEL_IOMMU
2246 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2247 return true;
2248 #endif
2249 return false;
2250 }
2251
2252 unsigned int
2253 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2254 uint64_t fb_format_modifier)
2255 {
2256 unsigned int tile_height;
2257 uint32_t pixel_bytes;
2258
2259 switch (fb_format_modifier) {
2260 case DRM_FORMAT_MOD_NONE:
2261 tile_height = 1;
2262 break;
2263 case I915_FORMAT_MOD_X_TILED:
2264 tile_height = IS_GEN2(dev) ? 16 : 8;
2265 break;
2266 case I915_FORMAT_MOD_Y_TILED:
2267 tile_height = 32;
2268 break;
2269 case I915_FORMAT_MOD_Yf_TILED:
2270 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2271 switch (pixel_bytes) {
2272 default:
2273 case 1:
2274 tile_height = 64;
2275 break;
2276 case 2:
2277 case 4:
2278 tile_height = 32;
2279 break;
2280 case 8:
2281 tile_height = 16;
2282 break;
2283 case 16:
2284 WARN_ONCE(1,
2285 "128-bit pixels are not supported for display!");
2286 tile_height = 16;
2287 break;
2288 }
2289 break;
2290 default:
2291 MISSING_CASE(fb_format_modifier);
2292 tile_height = 1;
2293 break;
2294 }
2295
2296 return tile_height;
2297 }
2298
2299 unsigned int
2300 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2301 uint32_t pixel_format, uint64_t fb_format_modifier)
2302 {
2303 return ALIGN(height, intel_tile_height(dev, pixel_format,
2304 fb_format_modifier));
2305 }
2306
2307 static int
2308 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2309 const struct drm_plane_state *plane_state)
2310 {
2311 struct intel_rotation_info *info = &view->rotation_info;
2312
2313 *view = i915_ggtt_view_normal;
2314
2315 if (!plane_state)
2316 return 0;
2317
2318 if (!intel_rotation_90_or_270(plane_state->rotation))
2319 return 0;
2320
2321 *view = i915_ggtt_view_rotated;
2322
2323 info->height = fb->height;
2324 info->pixel_format = fb->pixel_format;
2325 info->pitch = fb->pitches[0];
2326 info->fb_modifier = fb->modifier[0];
2327
2328 return 0;
2329 }
2330
2331 int
2332 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2333 struct drm_framebuffer *fb,
2334 const struct drm_plane_state *plane_state,
2335 struct intel_engine_cs *pipelined)
2336 {
2337 struct drm_device *dev = fb->dev;
2338 struct drm_i915_private *dev_priv = dev->dev_private;
2339 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2340 struct i915_ggtt_view view;
2341 u32 alignment;
2342 int ret;
2343
2344 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2345
2346 switch (fb->modifier[0]) {
2347 case DRM_FORMAT_MOD_NONE:
2348 if (INTEL_INFO(dev)->gen >= 9)
2349 alignment = 256 * 1024;
2350 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2351 alignment = 128 * 1024;
2352 else if (INTEL_INFO(dev)->gen >= 4)
2353 alignment = 4 * 1024;
2354 else
2355 alignment = 64 * 1024;
2356 break;
2357 case I915_FORMAT_MOD_X_TILED:
2358 if (INTEL_INFO(dev)->gen >= 9)
2359 alignment = 256 * 1024;
2360 else {
2361 /* pin() will align the object as required by fence */
2362 alignment = 0;
2363 }
2364 break;
2365 case I915_FORMAT_MOD_Y_TILED:
2366 case I915_FORMAT_MOD_Yf_TILED:
2367 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2368 "Y tiling bo slipped through, driver bug!\n"))
2369 return -EINVAL;
2370 alignment = 1 * 1024 * 1024;
2371 break;
2372 default:
2373 MISSING_CASE(fb->modifier[0]);
2374 return -EINVAL;
2375 }
2376
2377 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2378 if (ret)
2379 return ret;
2380
2381 /* Note that the w/a also requires 64 PTE of padding following the
2382 * bo. We currently fill all unused PTE with the shadow page and so
2383 * we should always have valid PTE following the scanout preventing
2384 * the VT-d warning.
2385 */
2386 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2387 alignment = 256 * 1024;
2388
2389 /*
2390 * Global gtt pte registers are special registers which actually forward
2391 * writes to a chunk of system memory. Which means that there is no risk
2392 * that the register values disappear as soon as we call
2393 * intel_runtime_pm_put(), so it is correct to wrap only the
2394 * pin/unpin/fence and not more.
2395 */
2396 intel_runtime_pm_get(dev_priv);
2397
2398 dev_priv->mm.interruptible = false;
2399 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2400 &view);
2401 if (ret)
2402 goto err_interruptible;
2403
2404 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2405 * fence, whereas 965+ only requires a fence if using
2406 * framebuffer compression. For simplicity, we always install
2407 * a fence as the cost is not that onerous.
2408 */
2409 ret = i915_gem_object_get_fence(obj);
2410 if (ret)
2411 goto err_unpin;
2412
2413 i915_gem_object_pin_fence(obj);
2414
2415 dev_priv->mm.interruptible = true;
2416 intel_runtime_pm_put(dev_priv);
2417 return 0;
2418
2419 err_unpin:
2420 i915_gem_object_unpin_from_display_plane(obj, &view);
2421 err_interruptible:
2422 dev_priv->mm.interruptible = true;
2423 intel_runtime_pm_put(dev_priv);
2424 return ret;
2425 }
2426
2427 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2428 const struct drm_plane_state *plane_state)
2429 {
2430 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2431 struct i915_ggtt_view view;
2432 int ret;
2433
2434 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2435
2436 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2437 WARN_ONCE(ret, "Couldn't get view from plane state!");
2438
2439 i915_gem_object_unpin_fence(obj);
2440 i915_gem_object_unpin_from_display_plane(obj, &view);
2441 }
2442
2443 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2444 * is assumed to be a power-of-two. */
2445 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2446 unsigned int tiling_mode,
2447 unsigned int cpp,
2448 unsigned int pitch)
2449 {
2450 if (tiling_mode != I915_TILING_NONE) {
2451 unsigned int tile_rows, tiles;
2452
2453 tile_rows = *y / 8;
2454 *y %= 8;
2455
2456 tiles = *x / (512/cpp);
2457 *x %= 512/cpp;
2458
2459 return tile_rows * pitch * 8 + tiles * 4096;
2460 } else {
2461 unsigned int offset;
2462
2463 offset = *y * pitch + *x * cpp;
2464 *y = 0;
2465 *x = (offset & 4095) / cpp;
2466 return offset & -4096;
2467 }
2468 }
2469
2470 static int i9xx_format_to_fourcc(int format)
2471 {
2472 switch (format) {
2473 case DISPPLANE_8BPP:
2474 return DRM_FORMAT_C8;
2475 case DISPPLANE_BGRX555:
2476 return DRM_FORMAT_XRGB1555;
2477 case DISPPLANE_BGRX565:
2478 return DRM_FORMAT_RGB565;
2479 default:
2480 case DISPPLANE_BGRX888:
2481 return DRM_FORMAT_XRGB8888;
2482 case DISPPLANE_RGBX888:
2483 return DRM_FORMAT_XBGR8888;
2484 case DISPPLANE_BGRX101010:
2485 return DRM_FORMAT_XRGB2101010;
2486 case DISPPLANE_RGBX101010:
2487 return DRM_FORMAT_XBGR2101010;
2488 }
2489 }
2490
2491 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2492 {
2493 switch (format) {
2494 case PLANE_CTL_FORMAT_RGB_565:
2495 return DRM_FORMAT_RGB565;
2496 default:
2497 case PLANE_CTL_FORMAT_XRGB_8888:
2498 if (rgb_order) {
2499 if (alpha)
2500 return DRM_FORMAT_ABGR8888;
2501 else
2502 return DRM_FORMAT_XBGR8888;
2503 } else {
2504 if (alpha)
2505 return DRM_FORMAT_ARGB8888;
2506 else
2507 return DRM_FORMAT_XRGB8888;
2508 }
2509 case PLANE_CTL_FORMAT_XRGB_2101010:
2510 if (rgb_order)
2511 return DRM_FORMAT_XBGR2101010;
2512 else
2513 return DRM_FORMAT_XRGB2101010;
2514 }
2515 }
2516
2517 static bool
2518 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2519 struct intel_initial_plane_config *plane_config)
2520 {
2521 struct drm_device *dev = crtc->base.dev;
2522 struct drm_i915_gem_object *obj = NULL;
2523 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2524 struct drm_framebuffer *fb = &plane_config->fb->base;
2525 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2526 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2527 PAGE_SIZE);
2528
2529 size_aligned -= base_aligned;
2530
2531 if (plane_config->size == 0)
2532 return false;
2533
2534 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2535 base_aligned,
2536 base_aligned,
2537 size_aligned);
2538 if (!obj)
2539 return false;
2540
2541 obj->tiling_mode = plane_config->tiling;
2542 if (obj->tiling_mode == I915_TILING_X)
2543 obj->stride = fb->pitches[0];
2544
2545 mode_cmd.pixel_format = fb->pixel_format;
2546 mode_cmd.width = fb->width;
2547 mode_cmd.height = fb->height;
2548 mode_cmd.pitches[0] = fb->pitches[0];
2549 mode_cmd.modifier[0] = fb->modifier[0];
2550 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2551
2552 mutex_lock(&dev->struct_mutex);
2553 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2554 &mode_cmd, obj)) {
2555 DRM_DEBUG_KMS("intel fb init failed\n");
2556 goto out_unref_obj;
2557 }
2558 mutex_unlock(&dev->struct_mutex);
2559
2560 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2561 return true;
2562
2563 out_unref_obj:
2564 drm_gem_object_unreference(&obj->base);
2565 mutex_unlock(&dev->struct_mutex);
2566 return false;
2567 }
2568
2569 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2570 static void
2571 update_state_fb(struct drm_plane *plane)
2572 {
2573 if (plane->fb == plane->state->fb)
2574 return;
2575
2576 if (plane->state->fb)
2577 drm_framebuffer_unreference(plane->state->fb);
2578 plane->state->fb = plane->fb;
2579 if (plane->state->fb)
2580 drm_framebuffer_reference(plane->state->fb);
2581 }
2582
2583 static void
2584 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2585 struct intel_initial_plane_config *plane_config)
2586 {
2587 struct drm_device *dev = intel_crtc->base.dev;
2588 struct drm_i915_private *dev_priv = dev->dev_private;
2589 struct drm_crtc *c;
2590 struct intel_crtc *i;
2591 struct drm_i915_gem_object *obj;
2592 struct drm_plane *primary = intel_crtc->base.primary;
2593 struct drm_framebuffer *fb;
2594
2595 if (!plane_config->fb)
2596 return;
2597
2598 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2599 fb = &plane_config->fb->base;
2600 goto valid_fb;
2601 }
2602
2603 kfree(plane_config->fb);
2604
2605 /*
2606 * Failed to alloc the obj, check to see if we should share
2607 * an fb with another CRTC instead
2608 */
2609 for_each_crtc(dev, c) {
2610 i = to_intel_crtc(c);
2611
2612 if (c == &intel_crtc->base)
2613 continue;
2614
2615 if (!i->active)
2616 continue;
2617
2618 fb = c->primary->fb;
2619 if (!fb)
2620 continue;
2621
2622 obj = intel_fb_obj(fb);
2623 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2624 drm_framebuffer_reference(fb);
2625 goto valid_fb;
2626 }
2627 }
2628
2629 return;
2630
2631 valid_fb:
2632 obj = intel_fb_obj(fb);
2633 if (obj->tiling_mode != I915_TILING_NONE)
2634 dev_priv->preserve_bios_swizzle = true;
2635
2636 primary->fb = fb;
2637 primary->state->crtc = &intel_crtc->base;
2638 primary->crtc = &intel_crtc->base;
2639 update_state_fb(primary);
2640 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2641 }
2642
2643 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2644 struct drm_framebuffer *fb,
2645 int x, int y)
2646 {
2647 struct drm_device *dev = crtc->dev;
2648 struct drm_i915_private *dev_priv = dev->dev_private;
2649 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2650 struct drm_plane *primary = crtc->primary;
2651 bool visible = to_intel_plane_state(primary->state)->visible;
2652 struct drm_i915_gem_object *obj;
2653 int plane = intel_crtc->plane;
2654 unsigned long linear_offset;
2655 u32 dspcntr;
2656 u32 reg = DSPCNTR(plane);
2657 int pixel_size;
2658
2659 if (!visible || !fb) {
2660 I915_WRITE(reg, 0);
2661 if (INTEL_INFO(dev)->gen >= 4)
2662 I915_WRITE(DSPSURF(plane), 0);
2663 else
2664 I915_WRITE(DSPADDR(plane), 0);
2665 POSTING_READ(reg);
2666 return;
2667 }
2668
2669 obj = intel_fb_obj(fb);
2670 if (WARN_ON(obj == NULL))
2671 return;
2672
2673 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2674
2675 dspcntr = DISPPLANE_GAMMA_ENABLE;
2676
2677 dspcntr |= DISPLAY_PLANE_ENABLE;
2678
2679 if (INTEL_INFO(dev)->gen < 4) {
2680 if (intel_crtc->pipe == PIPE_B)
2681 dspcntr |= DISPPLANE_SEL_PIPE_B;
2682
2683 /* pipesrc and dspsize control the size that is scaled from,
2684 * which should always be the user's requested size.
2685 */
2686 I915_WRITE(DSPSIZE(plane),
2687 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2688 (intel_crtc->config->pipe_src_w - 1));
2689 I915_WRITE(DSPPOS(plane), 0);
2690 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2691 I915_WRITE(PRIMSIZE(plane),
2692 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2693 (intel_crtc->config->pipe_src_w - 1));
2694 I915_WRITE(PRIMPOS(plane), 0);
2695 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2696 }
2697
2698 switch (fb->pixel_format) {
2699 case DRM_FORMAT_C8:
2700 dspcntr |= DISPPLANE_8BPP;
2701 break;
2702 case DRM_FORMAT_XRGB1555:
2703 case DRM_FORMAT_ARGB1555:
2704 dspcntr |= DISPPLANE_BGRX555;
2705 break;
2706 case DRM_FORMAT_RGB565:
2707 dspcntr |= DISPPLANE_BGRX565;
2708 break;
2709 case DRM_FORMAT_XRGB8888:
2710 case DRM_FORMAT_ARGB8888:
2711 dspcntr |= DISPPLANE_BGRX888;
2712 break;
2713 case DRM_FORMAT_XBGR8888:
2714 case DRM_FORMAT_ABGR8888:
2715 dspcntr |= DISPPLANE_RGBX888;
2716 break;
2717 case DRM_FORMAT_XRGB2101010:
2718 case DRM_FORMAT_ARGB2101010:
2719 dspcntr |= DISPPLANE_BGRX101010;
2720 break;
2721 case DRM_FORMAT_XBGR2101010:
2722 case DRM_FORMAT_ABGR2101010:
2723 dspcntr |= DISPPLANE_RGBX101010;
2724 break;
2725 default:
2726 BUG();
2727 }
2728
2729 if (INTEL_INFO(dev)->gen >= 4 &&
2730 obj->tiling_mode != I915_TILING_NONE)
2731 dspcntr |= DISPPLANE_TILED;
2732
2733 if (IS_G4X(dev))
2734 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2735
2736 linear_offset = y * fb->pitches[0] + x * pixel_size;
2737
2738 if (INTEL_INFO(dev)->gen >= 4) {
2739 intel_crtc->dspaddr_offset =
2740 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2741 pixel_size,
2742 fb->pitches[0]);
2743 linear_offset -= intel_crtc->dspaddr_offset;
2744 } else {
2745 intel_crtc->dspaddr_offset = linear_offset;
2746 }
2747
2748 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2749 dspcntr |= DISPPLANE_ROTATE_180;
2750
2751 x += (intel_crtc->config->pipe_src_w - 1);
2752 y += (intel_crtc->config->pipe_src_h - 1);
2753
2754 /* Finding the last pixel of the last line of the display
2755 data and adding to linear_offset*/
2756 linear_offset +=
2757 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2758 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2759 }
2760
2761 I915_WRITE(reg, dspcntr);
2762
2763 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2764 if (INTEL_INFO(dev)->gen >= 4) {
2765 I915_WRITE(DSPSURF(plane),
2766 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2767 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2768 I915_WRITE(DSPLINOFF(plane), linear_offset);
2769 } else
2770 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2771 POSTING_READ(reg);
2772 }
2773
2774 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2775 struct drm_framebuffer *fb,
2776 int x, int y)
2777 {
2778 struct drm_device *dev = crtc->dev;
2779 struct drm_i915_private *dev_priv = dev->dev_private;
2780 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2781 struct drm_plane *primary = crtc->primary;
2782 bool visible = to_intel_plane_state(primary->state)->visible;
2783 struct drm_i915_gem_object *obj;
2784 int plane = intel_crtc->plane;
2785 unsigned long linear_offset;
2786 u32 dspcntr;
2787 u32 reg = DSPCNTR(plane);
2788 int pixel_size;
2789
2790 if (!visible || !fb) {
2791 I915_WRITE(reg, 0);
2792 I915_WRITE(DSPSURF(plane), 0);
2793 POSTING_READ(reg);
2794 return;
2795 }
2796
2797 obj = intel_fb_obj(fb);
2798 if (WARN_ON(obj == NULL))
2799 return;
2800
2801 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2802
2803 dspcntr = DISPPLANE_GAMMA_ENABLE;
2804
2805 dspcntr |= DISPLAY_PLANE_ENABLE;
2806
2807 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2808 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2809
2810 switch (fb->pixel_format) {
2811 case DRM_FORMAT_C8:
2812 dspcntr |= DISPPLANE_8BPP;
2813 break;
2814 case DRM_FORMAT_RGB565:
2815 dspcntr |= DISPPLANE_BGRX565;
2816 break;
2817 case DRM_FORMAT_XRGB8888:
2818 case DRM_FORMAT_ARGB8888:
2819 dspcntr |= DISPPLANE_BGRX888;
2820 break;
2821 case DRM_FORMAT_XBGR8888:
2822 case DRM_FORMAT_ABGR8888:
2823 dspcntr |= DISPPLANE_RGBX888;
2824 break;
2825 case DRM_FORMAT_XRGB2101010:
2826 case DRM_FORMAT_ARGB2101010:
2827 dspcntr |= DISPPLANE_BGRX101010;
2828 break;
2829 case DRM_FORMAT_XBGR2101010:
2830 case DRM_FORMAT_ABGR2101010:
2831 dspcntr |= DISPPLANE_RGBX101010;
2832 break;
2833 default:
2834 BUG();
2835 }
2836
2837 if (obj->tiling_mode != I915_TILING_NONE)
2838 dspcntr |= DISPPLANE_TILED;
2839
2840 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2841 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2842
2843 linear_offset = y * fb->pitches[0] + x * pixel_size;
2844 intel_crtc->dspaddr_offset =
2845 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2846 pixel_size,
2847 fb->pitches[0]);
2848 linear_offset -= intel_crtc->dspaddr_offset;
2849 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2850 dspcntr |= DISPPLANE_ROTATE_180;
2851
2852 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2853 x += (intel_crtc->config->pipe_src_w - 1);
2854 y += (intel_crtc->config->pipe_src_h - 1);
2855
2856 /* Finding the last pixel of the last line of the display
2857 data and adding to linear_offset*/
2858 linear_offset +=
2859 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2860 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2861 }
2862 }
2863
2864 I915_WRITE(reg, dspcntr);
2865
2866 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2867 I915_WRITE(DSPSURF(plane),
2868 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2869 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2870 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2871 } else {
2872 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2873 I915_WRITE(DSPLINOFF(plane), linear_offset);
2874 }
2875 POSTING_READ(reg);
2876 }
2877
2878 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2879 uint32_t pixel_format)
2880 {
2881 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2882
2883 /*
2884 * The stride is either expressed as a multiple of 64 bytes
2885 * chunks for linear buffers or in number of tiles for tiled
2886 * buffers.
2887 */
2888 switch (fb_modifier) {
2889 case DRM_FORMAT_MOD_NONE:
2890 return 64;
2891 case I915_FORMAT_MOD_X_TILED:
2892 if (INTEL_INFO(dev)->gen == 2)
2893 return 128;
2894 return 512;
2895 case I915_FORMAT_MOD_Y_TILED:
2896 /* No need to check for old gens and Y tiling since this is
2897 * about the display engine and those will be blocked before
2898 * we get here.
2899 */
2900 return 128;
2901 case I915_FORMAT_MOD_Yf_TILED:
2902 if (bits_per_pixel == 8)
2903 return 64;
2904 else
2905 return 128;
2906 default:
2907 MISSING_CASE(fb_modifier);
2908 return 64;
2909 }
2910 }
2911
2912 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2913 struct drm_i915_gem_object *obj)
2914 {
2915 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2916
2917 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2918 view = &i915_ggtt_view_rotated;
2919
2920 return i915_gem_obj_ggtt_offset_view(obj, view);
2921 }
2922
2923 /*
2924 * This function detaches (aka. unbinds) unused scalers in hardware
2925 */
2926 void skl_detach_scalers(struct intel_crtc *intel_crtc)
2927 {
2928 struct drm_device *dev;
2929 struct drm_i915_private *dev_priv;
2930 struct intel_crtc_scaler_state *scaler_state;
2931 int i;
2932
2933 if (!intel_crtc || !intel_crtc->config)
2934 return;
2935
2936 dev = intel_crtc->base.dev;
2937 dev_priv = dev->dev_private;
2938 scaler_state = &intel_crtc->config->scaler_state;
2939
2940 /* loop through and disable scalers that aren't in use */
2941 for (i = 0; i < intel_crtc->num_scalers; i++) {
2942 if (!scaler_state->scalers[i].in_use) {
2943 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2944 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2945 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2946 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2947 intel_crtc->base.base.id, intel_crtc->pipe, i);
2948 }
2949 }
2950 }
2951
2952 u32 skl_plane_ctl_format(uint32_t pixel_format)
2953 {
2954 u32 plane_ctl_format = 0;
2955 switch (pixel_format) {
2956 case DRM_FORMAT_RGB565:
2957 plane_ctl_format = PLANE_CTL_FORMAT_RGB_565;
2958 break;
2959 case DRM_FORMAT_XBGR8888:
2960 plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2961 break;
2962 case DRM_FORMAT_XRGB8888:
2963 plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888;
2964 break;
2965 /*
2966 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2967 * to be already pre-multiplied. We need to add a knob (or a different
2968 * DRM_FORMAT) for user-space to configure that.
2969 */
2970 case DRM_FORMAT_ABGR8888:
2971 plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2972 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2973 break;
2974 case DRM_FORMAT_ARGB8888:
2975 plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888 |
2976 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2977 break;
2978 case DRM_FORMAT_XRGB2101010:
2979 plane_ctl_format = PLANE_CTL_FORMAT_XRGB_2101010;
2980 break;
2981 case DRM_FORMAT_XBGR2101010:
2982 plane_ctl_format = PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2983 break;
2984 case DRM_FORMAT_YUYV:
2985 plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2986 break;
2987 case DRM_FORMAT_YVYU:
2988 plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2989 break;
2990 case DRM_FORMAT_UYVY:
2991 plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2992 break;
2993 case DRM_FORMAT_VYUY:
2994 plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2995 break;
2996 default:
2997 BUG();
2998 }
2999 return plane_ctl_format;
3000 }
3001
3002 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3003 {
3004 u32 plane_ctl_tiling = 0;
3005 switch (fb_modifier) {
3006 case DRM_FORMAT_MOD_NONE:
3007 break;
3008 case I915_FORMAT_MOD_X_TILED:
3009 plane_ctl_tiling = PLANE_CTL_TILED_X;
3010 break;
3011 case I915_FORMAT_MOD_Y_TILED:
3012 plane_ctl_tiling = PLANE_CTL_TILED_Y;
3013 break;
3014 case I915_FORMAT_MOD_Yf_TILED:
3015 plane_ctl_tiling = PLANE_CTL_TILED_YF;
3016 break;
3017 default:
3018 MISSING_CASE(fb_modifier);
3019 }
3020 return plane_ctl_tiling;
3021 }
3022
3023 u32 skl_plane_ctl_rotation(unsigned int rotation)
3024 {
3025 u32 plane_ctl_rotation = 0;
3026 switch (rotation) {
3027 case BIT(DRM_ROTATE_0):
3028 break;
3029 case BIT(DRM_ROTATE_90):
3030 plane_ctl_rotation = PLANE_CTL_ROTATE_90;
3031 break;
3032 case BIT(DRM_ROTATE_180):
3033 plane_ctl_rotation = PLANE_CTL_ROTATE_180;
3034 break;
3035 case BIT(DRM_ROTATE_270):
3036 plane_ctl_rotation = PLANE_CTL_ROTATE_270;
3037 break;
3038 default:
3039 MISSING_CASE(rotation);
3040 }
3041
3042 return plane_ctl_rotation;
3043 }
3044
3045 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3046 struct drm_framebuffer *fb,
3047 int x, int y)
3048 {
3049 struct drm_device *dev = crtc->dev;
3050 struct drm_i915_private *dev_priv = dev->dev_private;
3051 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3052 struct drm_plane *plane = crtc->primary;
3053 bool visible = to_intel_plane_state(plane->state)->visible;
3054 struct drm_i915_gem_object *obj;
3055 int pipe = intel_crtc->pipe;
3056 u32 plane_ctl, stride_div, stride;
3057 u32 tile_height, plane_offset, plane_size;
3058 unsigned int rotation;
3059 int x_offset, y_offset;
3060 unsigned long surf_addr;
3061 struct intel_crtc_state *crtc_state = intel_crtc->config;
3062 struct intel_plane_state *plane_state;
3063 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3064 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3065 int scaler_id = -1;
3066
3067 plane_state = to_intel_plane_state(plane->state);
3068
3069 if (!visible || !fb) {
3070 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3071 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3072 POSTING_READ(PLANE_CTL(pipe, 0));
3073 return;
3074 }
3075
3076 plane_ctl = PLANE_CTL_ENABLE |
3077 PLANE_CTL_PIPE_GAMMA_ENABLE |
3078 PLANE_CTL_PIPE_CSC_ENABLE;
3079
3080 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3081 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3082 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3083
3084 rotation = plane->state->rotation;
3085 plane_ctl |= skl_plane_ctl_rotation(rotation);
3086
3087 obj = intel_fb_obj(fb);
3088 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3089 fb->pixel_format);
3090 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3091
3092 /*
3093 * FIXME: intel_plane_state->src, dst aren't set when transitional
3094 * update_plane helpers are called from legacy paths.
3095 * Once full atomic crtc is available, below check can be avoided.
3096 */
3097 if (drm_rect_width(&plane_state->src)) {
3098 scaler_id = plane_state->scaler_id;
3099 src_x = plane_state->src.x1 >> 16;
3100 src_y = plane_state->src.y1 >> 16;
3101 src_w = drm_rect_width(&plane_state->src) >> 16;
3102 src_h = drm_rect_height(&plane_state->src) >> 16;
3103 dst_x = plane_state->dst.x1;
3104 dst_y = plane_state->dst.y1;
3105 dst_w = drm_rect_width(&plane_state->dst);
3106 dst_h = drm_rect_height(&plane_state->dst);
3107
3108 WARN_ON(x != src_x || y != src_y);
3109 } else {
3110 src_w = intel_crtc->config->pipe_src_w;
3111 src_h = intel_crtc->config->pipe_src_h;
3112 }
3113
3114 if (intel_rotation_90_or_270(rotation)) {
3115 /* stride = Surface height in tiles */
3116 tile_height = intel_tile_height(dev, fb->bits_per_pixel,
3117 fb->modifier[0]);
3118 stride = DIV_ROUND_UP(fb->height, tile_height);
3119 x_offset = stride * tile_height - y - src_h;
3120 y_offset = x;
3121 plane_size = (src_w - 1) << 16 | (src_h - 1);
3122 } else {
3123 stride = fb->pitches[0] / stride_div;
3124 x_offset = x;
3125 y_offset = y;
3126 plane_size = (src_h - 1) << 16 | (src_w - 1);
3127 }
3128 plane_offset = y_offset << 16 | x_offset;
3129
3130 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3131 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3132 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3133 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3134
3135 if (scaler_id >= 0) {
3136 uint32_t ps_ctrl = 0;
3137
3138 WARN_ON(!dst_w || !dst_h);
3139 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3140 crtc_state->scaler_state.scalers[scaler_id].mode;
3141 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3142 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3143 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3144 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3145 I915_WRITE(PLANE_POS(pipe, 0), 0);
3146 } else {
3147 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3148 }
3149
3150 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3151
3152 POSTING_READ(PLANE_SURF(pipe, 0));
3153 }
3154
3155 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3156 static int
3157 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3158 int x, int y, enum mode_set_atomic state)
3159 {
3160 struct drm_device *dev = crtc->dev;
3161 struct drm_i915_private *dev_priv = dev->dev_private;
3162
3163 if (dev_priv->display.disable_fbc)
3164 dev_priv->display.disable_fbc(dev);
3165
3166 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3167
3168 return 0;
3169 }
3170
3171 static void intel_complete_page_flips(struct drm_device *dev)
3172 {
3173 struct drm_crtc *crtc;
3174
3175 for_each_crtc(dev, crtc) {
3176 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3177 enum plane plane = intel_crtc->plane;
3178
3179 intel_prepare_page_flip(dev, plane);
3180 intel_finish_page_flip_plane(dev, plane);
3181 }
3182 }
3183
3184 static void intel_update_primary_planes(struct drm_device *dev)
3185 {
3186 struct drm_i915_private *dev_priv = dev->dev_private;
3187 struct drm_crtc *crtc;
3188
3189 for_each_crtc(dev, crtc) {
3190 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3191
3192 drm_modeset_lock(&crtc->mutex, NULL);
3193 /*
3194 * FIXME: Once we have proper support for primary planes (and
3195 * disabling them without disabling the entire crtc) allow again
3196 * a NULL crtc->primary->fb.
3197 */
3198 if (intel_crtc->active && crtc->primary->fb)
3199 dev_priv->display.update_primary_plane(crtc,
3200 crtc->primary->fb,
3201 crtc->x,
3202 crtc->y);
3203 drm_modeset_unlock(&crtc->mutex);
3204 }
3205 }
3206
3207 void intel_crtc_reset(struct intel_crtc *crtc)
3208 {
3209 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3210
3211 if (!crtc->active)
3212 return;
3213
3214 intel_crtc_disable_planes(&crtc->base);
3215 dev_priv->display.crtc_disable(&crtc->base);
3216 dev_priv->display.crtc_enable(&crtc->base);
3217 intel_crtc_enable_planes(&crtc->base);
3218 }
3219
3220 void intel_prepare_reset(struct drm_device *dev)
3221 {
3222 struct drm_i915_private *dev_priv = to_i915(dev);
3223 struct intel_crtc *crtc;
3224
3225 /* no reset support for gen2 */
3226 if (IS_GEN2(dev))
3227 return;
3228
3229 /* reset doesn't touch the display */
3230 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3231 return;
3232
3233 drm_modeset_lock_all(dev);
3234
3235 /*
3236 * Disabling the crtcs gracefully seems nicer. Also the
3237 * g33 docs say we should at least disable all the planes.
3238 */
3239 for_each_intel_crtc(dev, crtc) {
3240 if (!crtc->active)
3241 continue;
3242
3243 intel_crtc_disable_planes(&crtc->base);
3244 dev_priv->display.crtc_disable(&crtc->base);
3245 }
3246 }
3247
3248 void intel_finish_reset(struct drm_device *dev)
3249 {
3250 struct drm_i915_private *dev_priv = to_i915(dev);
3251
3252 /*
3253 * Flips in the rings will be nuked by the reset,
3254 * so complete all pending flips so that user space
3255 * will get its events and not get stuck.
3256 */
3257 intel_complete_page_flips(dev);
3258
3259 /* no reset support for gen2 */
3260 if (IS_GEN2(dev))
3261 return;
3262
3263 /* reset doesn't touch the display */
3264 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3265 /*
3266 * Flips in the rings have been nuked by the reset,
3267 * so update the base address of all primary
3268 * planes to the the last fb to make sure we're
3269 * showing the correct fb after a reset.
3270 */
3271 intel_update_primary_planes(dev);
3272 return;
3273 }
3274
3275 /*
3276 * The display has been reset as well,
3277 * so need a full re-initialization.
3278 */
3279 intel_runtime_pm_disable_interrupts(dev_priv);
3280 intel_runtime_pm_enable_interrupts(dev_priv);
3281
3282 intel_modeset_init_hw(dev);
3283
3284 spin_lock_irq(&dev_priv->irq_lock);
3285 if (dev_priv->display.hpd_irq_setup)
3286 dev_priv->display.hpd_irq_setup(dev);
3287 spin_unlock_irq(&dev_priv->irq_lock);
3288
3289 intel_modeset_setup_hw_state(dev, true);
3290
3291 intel_hpd_init(dev_priv);
3292
3293 drm_modeset_unlock_all(dev);
3294 }
3295
3296 static int
3297 intel_finish_fb(struct drm_framebuffer *old_fb)
3298 {
3299 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3300 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3301 bool was_interruptible = dev_priv->mm.interruptible;
3302 int ret;
3303
3304 /* Big Hammer, we also need to ensure that any pending
3305 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3306 * current scanout is retired before unpinning the old
3307 * framebuffer.
3308 *
3309 * This should only fail upon a hung GPU, in which case we
3310 * can safely continue.
3311 */
3312 dev_priv->mm.interruptible = false;
3313 ret = i915_gem_object_finish_gpu(obj);
3314 dev_priv->mm.interruptible = was_interruptible;
3315
3316 return ret;
3317 }
3318
3319 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3320 {
3321 struct drm_device *dev = crtc->dev;
3322 struct drm_i915_private *dev_priv = dev->dev_private;
3323 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3324 bool pending;
3325
3326 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3327 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3328 return false;
3329
3330 spin_lock_irq(&dev->event_lock);
3331 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3332 spin_unlock_irq(&dev->event_lock);
3333
3334 return pending;
3335 }
3336
3337 static void intel_update_pipe_size(struct intel_crtc *crtc)
3338 {
3339 struct drm_device *dev = crtc->base.dev;
3340 struct drm_i915_private *dev_priv = dev->dev_private;
3341 const struct drm_display_mode *adjusted_mode;
3342
3343 if (!i915.fastboot)
3344 return;
3345
3346 /*
3347 * Update pipe size and adjust fitter if needed: the reason for this is
3348 * that in compute_mode_changes we check the native mode (not the pfit
3349 * mode) to see if we can flip rather than do a full mode set. In the
3350 * fastboot case, we'll flip, but if we don't update the pipesrc and
3351 * pfit state, we'll end up with a big fb scanned out into the wrong
3352 * sized surface.
3353 *
3354 * To fix this properly, we need to hoist the checks up into
3355 * compute_mode_changes (or above), check the actual pfit state and
3356 * whether the platform allows pfit disable with pipe active, and only
3357 * then update the pipesrc and pfit state, even on the flip path.
3358 */
3359
3360 adjusted_mode = &crtc->config->base.adjusted_mode;
3361
3362 I915_WRITE(PIPESRC(crtc->pipe),
3363 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3364 (adjusted_mode->crtc_vdisplay - 1));
3365 if (!crtc->config->pch_pfit.enabled &&
3366 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3367 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3368 I915_WRITE(PF_CTL(crtc->pipe), 0);
3369 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3370 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3371 }
3372 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3373 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3374 }
3375
3376 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3377 {
3378 struct drm_device *dev = crtc->dev;
3379 struct drm_i915_private *dev_priv = dev->dev_private;
3380 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3381 int pipe = intel_crtc->pipe;
3382 u32 reg, temp;
3383
3384 /* enable normal train */
3385 reg = FDI_TX_CTL(pipe);
3386 temp = I915_READ(reg);
3387 if (IS_IVYBRIDGE(dev)) {
3388 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3389 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3390 } else {
3391 temp &= ~FDI_LINK_TRAIN_NONE;
3392 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3393 }
3394 I915_WRITE(reg, temp);
3395
3396 reg = FDI_RX_CTL(pipe);
3397 temp = I915_READ(reg);
3398 if (HAS_PCH_CPT(dev)) {
3399 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3400 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3401 } else {
3402 temp &= ~FDI_LINK_TRAIN_NONE;
3403 temp |= FDI_LINK_TRAIN_NONE;
3404 }
3405 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3406
3407 /* wait one idle pattern time */
3408 POSTING_READ(reg);
3409 udelay(1000);
3410
3411 /* IVB wants error correction enabled */
3412 if (IS_IVYBRIDGE(dev))
3413 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3414 FDI_FE_ERRC_ENABLE);
3415 }
3416
3417 /* The FDI link training functions for ILK/Ibexpeak. */
3418 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3419 {
3420 struct drm_device *dev = crtc->dev;
3421 struct drm_i915_private *dev_priv = dev->dev_private;
3422 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3423 int pipe = intel_crtc->pipe;
3424 u32 reg, temp, tries;
3425
3426 /* FDI needs bits from pipe first */
3427 assert_pipe_enabled(dev_priv, pipe);
3428
3429 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3430 for train result */
3431 reg = FDI_RX_IMR(pipe);
3432 temp = I915_READ(reg);
3433 temp &= ~FDI_RX_SYMBOL_LOCK;
3434 temp &= ~FDI_RX_BIT_LOCK;
3435 I915_WRITE(reg, temp);
3436 I915_READ(reg);
3437 udelay(150);
3438
3439 /* enable CPU FDI TX and PCH FDI RX */
3440 reg = FDI_TX_CTL(pipe);
3441 temp = I915_READ(reg);
3442 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3443 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3444 temp &= ~FDI_LINK_TRAIN_NONE;
3445 temp |= FDI_LINK_TRAIN_PATTERN_1;
3446 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3447
3448 reg = FDI_RX_CTL(pipe);
3449 temp = I915_READ(reg);
3450 temp &= ~FDI_LINK_TRAIN_NONE;
3451 temp |= FDI_LINK_TRAIN_PATTERN_1;
3452 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3453
3454 POSTING_READ(reg);
3455 udelay(150);
3456
3457 /* Ironlake workaround, enable clock pointer after FDI enable*/
3458 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3459 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3460 FDI_RX_PHASE_SYNC_POINTER_EN);
3461
3462 reg = FDI_RX_IIR(pipe);
3463 for (tries = 0; tries < 5; tries++) {
3464 temp = I915_READ(reg);
3465 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3466
3467 if ((temp & FDI_RX_BIT_LOCK)) {
3468 DRM_DEBUG_KMS("FDI train 1 done.\n");
3469 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3470 break;
3471 }
3472 }
3473 if (tries == 5)
3474 DRM_ERROR("FDI train 1 fail!\n");
3475
3476 /* Train 2 */
3477 reg = FDI_TX_CTL(pipe);
3478 temp = I915_READ(reg);
3479 temp &= ~FDI_LINK_TRAIN_NONE;
3480 temp |= FDI_LINK_TRAIN_PATTERN_2;
3481 I915_WRITE(reg, temp);
3482
3483 reg = FDI_RX_CTL(pipe);
3484 temp = I915_READ(reg);
3485 temp &= ~FDI_LINK_TRAIN_NONE;
3486 temp |= FDI_LINK_TRAIN_PATTERN_2;
3487 I915_WRITE(reg, temp);
3488
3489 POSTING_READ(reg);
3490 udelay(150);
3491
3492 reg = FDI_RX_IIR(pipe);
3493 for (tries = 0; tries < 5; tries++) {
3494 temp = I915_READ(reg);
3495 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3496
3497 if (temp & FDI_RX_SYMBOL_LOCK) {
3498 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3499 DRM_DEBUG_KMS("FDI train 2 done.\n");
3500 break;
3501 }
3502 }
3503 if (tries == 5)
3504 DRM_ERROR("FDI train 2 fail!\n");
3505
3506 DRM_DEBUG_KMS("FDI train done\n");
3507
3508 }
3509
3510 static const int snb_b_fdi_train_param[] = {
3511 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3512 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3513 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3514 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3515 };
3516
3517 /* The FDI link training functions for SNB/Cougarpoint. */
3518 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3519 {
3520 struct drm_device *dev = crtc->dev;
3521 struct drm_i915_private *dev_priv = dev->dev_private;
3522 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3523 int pipe = intel_crtc->pipe;
3524 u32 reg, temp, i, retry;
3525
3526 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3527 for train result */
3528 reg = FDI_RX_IMR(pipe);
3529 temp = I915_READ(reg);
3530 temp &= ~FDI_RX_SYMBOL_LOCK;
3531 temp &= ~FDI_RX_BIT_LOCK;
3532 I915_WRITE(reg, temp);
3533
3534 POSTING_READ(reg);
3535 udelay(150);
3536
3537 /* enable CPU FDI TX and PCH FDI RX */
3538 reg = FDI_TX_CTL(pipe);
3539 temp = I915_READ(reg);
3540 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3541 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3542 temp &= ~FDI_LINK_TRAIN_NONE;
3543 temp |= FDI_LINK_TRAIN_PATTERN_1;
3544 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3545 /* SNB-B */
3546 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3547 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3548
3549 I915_WRITE(FDI_RX_MISC(pipe),
3550 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3551
3552 reg = FDI_RX_CTL(pipe);
3553 temp = I915_READ(reg);
3554 if (HAS_PCH_CPT(dev)) {
3555 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3556 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3557 } else {
3558 temp &= ~FDI_LINK_TRAIN_NONE;
3559 temp |= FDI_LINK_TRAIN_PATTERN_1;
3560 }
3561 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3562
3563 POSTING_READ(reg);
3564 udelay(150);
3565
3566 for (i = 0; i < 4; i++) {
3567 reg = FDI_TX_CTL(pipe);
3568 temp = I915_READ(reg);
3569 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3570 temp |= snb_b_fdi_train_param[i];
3571 I915_WRITE(reg, temp);
3572
3573 POSTING_READ(reg);
3574 udelay(500);
3575
3576 for (retry = 0; retry < 5; retry++) {
3577 reg = FDI_RX_IIR(pipe);
3578 temp = I915_READ(reg);
3579 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3580 if (temp & FDI_RX_BIT_LOCK) {
3581 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3582 DRM_DEBUG_KMS("FDI train 1 done.\n");
3583 break;
3584 }
3585 udelay(50);
3586 }
3587 if (retry < 5)
3588 break;
3589 }
3590 if (i == 4)
3591 DRM_ERROR("FDI train 1 fail!\n");
3592
3593 /* Train 2 */
3594 reg = FDI_TX_CTL(pipe);
3595 temp = I915_READ(reg);
3596 temp &= ~FDI_LINK_TRAIN_NONE;
3597 temp |= FDI_LINK_TRAIN_PATTERN_2;
3598 if (IS_GEN6(dev)) {
3599 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3600 /* SNB-B */
3601 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3602 }
3603 I915_WRITE(reg, temp);
3604
3605 reg = FDI_RX_CTL(pipe);
3606 temp = I915_READ(reg);
3607 if (HAS_PCH_CPT(dev)) {
3608 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3609 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3610 } else {
3611 temp &= ~FDI_LINK_TRAIN_NONE;
3612 temp |= FDI_LINK_TRAIN_PATTERN_2;
3613 }
3614 I915_WRITE(reg, temp);
3615
3616 POSTING_READ(reg);
3617 udelay(150);
3618
3619 for (i = 0; i < 4; i++) {
3620 reg = FDI_TX_CTL(pipe);
3621 temp = I915_READ(reg);
3622 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3623 temp |= snb_b_fdi_train_param[i];
3624 I915_WRITE(reg, temp);
3625
3626 POSTING_READ(reg);
3627 udelay(500);
3628
3629 for (retry = 0; retry < 5; retry++) {
3630 reg = FDI_RX_IIR(pipe);
3631 temp = I915_READ(reg);
3632 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3633 if (temp & FDI_RX_SYMBOL_LOCK) {
3634 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3635 DRM_DEBUG_KMS("FDI train 2 done.\n");
3636 break;
3637 }
3638 udelay(50);
3639 }
3640 if (retry < 5)
3641 break;
3642 }
3643 if (i == 4)
3644 DRM_ERROR("FDI train 2 fail!\n");
3645
3646 DRM_DEBUG_KMS("FDI train done.\n");
3647 }
3648
3649 /* Manual link training for Ivy Bridge A0 parts */
3650 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3651 {
3652 struct drm_device *dev = crtc->dev;
3653 struct drm_i915_private *dev_priv = dev->dev_private;
3654 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3655 int pipe = intel_crtc->pipe;
3656 u32 reg, temp, i, j;
3657
3658 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3659 for train result */
3660 reg = FDI_RX_IMR(pipe);
3661 temp = I915_READ(reg);
3662 temp &= ~FDI_RX_SYMBOL_LOCK;
3663 temp &= ~FDI_RX_BIT_LOCK;
3664 I915_WRITE(reg, temp);
3665
3666 POSTING_READ(reg);
3667 udelay(150);
3668
3669 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3670 I915_READ(FDI_RX_IIR(pipe)));
3671
3672 /* Try each vswing and preemphasis setting twice before moving on */
3673 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3674 /* disable first in case we need to retry */
3675 reg = FDI_TX_CTL(pipe);
3676 temp = I915_READ(reg);
3677 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3678 temp &= ~FDI_TX_ENABLE;
3679 I915_WRITE(reg, temp);
3680
3681 reg = FDI_RX_CTL(pipe);
3682 temp = I915_READ(reg);
3683 temp &= ~FDI_LINK_TRAIN_AUTO;
3684 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3685 temp &= ~FDI_RX_ENABLE;
3686 I915_WRITE(reg, temp);
3687
3688 /* enable CPU FDI TX and PCH FDI RX */
3689 reg = FDI_TX_CTL(pipe);
3690 temp = I915_READ(reg);
3691 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3692 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3693 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3694 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3695 temp |= snb_b_fdi_train_param[j/2];
3696 temp |= FDI_COMPOSITE_SYNC;
3697 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3698
3699 I915_WRITE(FDI_RX_MISC(pipe),
3700 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3701
3702 reg = FDI_RX_CTL(pipe);
3703 temp = I915_READ(reg);
3704 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3705 temp |= FDI_COMPOSITE_SYNC;
3706 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3707
3708 POSTING_READ(reg);
3709 udelay(1); /* should be 0.5us */
3710
3711 for (i = 0; i < 4; i++) {
3712 reg = FDI_RX_IIR(pipe);
3713 temp = I915_READ(reg);
3714 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3715
3716 if (temp & FDI_RX_BIT_LOCK ||
3717 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3718 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3719 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3720 i);
3721 break;
3722 }
3723 udelay(1); /* should be 0.5us */
3724 }
3725 if (i == 4) {
3726 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3727 continue;
3728 }
3729
3730 /* Train 2 */
3731 reg = FDI_TX_CTL(pipe);
3732 temp = I915_READ(reg);
3733 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3734 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3735 I915_WRITE(reg, temp);
3736
3737 reg = FDI_RX_CTL(pipe);
3738 temp = I915_READ(reg);
3739 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3740 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3741 I915_WRITE(reg, temp);
3742
3743 POSTING_READ(reg);
3744 udelay(2); /* should be 1.5us */
3745
3746 for (i = 0; i < 4; i++) {
3747 reg = FDI_RX_IIR(pipe);
3748 temp = I915_READ(reg);
3749 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3750
3751 if (temp & FDI_RX_SYMBOL_LOCK ||
3752 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3753 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3754 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3755 i);
3756 goto train_done;
3757 }
3758 udelay(2); /* should be 1.5us */
3759 }
3760 if (i == 4)
3761 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3762 }
3763
3764 train_done:
3765 DRM_DEBUG_KMS("FDI train done.\n");
3766 }
3767
3768 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3769 {
3770 struct drm_device *dev = intel_crtc->base.dev;
3771 struct drm_i915_private *dev_priv = dev->dev_private;
3772 int pipe = intel_crtc->pipe;
3773 u32 reg, temp;
3774
3775
3776 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3777 reg = FDI_RX_CTL(pipe);
3778 temp = I915_READ(reg);
3779 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3780 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3781 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3782 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3783
3784 POSTING_READ(reg);
3785 udelay(200);
3786
3787 /* Switch from Rawclk to PCDclk */
3788 temp = I915_READ(reg);
3789 I915_WRITE(reg, temp | FDI_PCDCLK);
3790
3791 POSTING_READ(reg);
3792 udelay(200);
3793
3794 /* Enable CPU FDI TX PLL, always on for Ironlake */
3795 reg = FDI_TX_CTL(pipe);
3796 temp = I915_READ(reg);
3797 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3798 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3799
3800 POSTING_READ(reg);
3801 udelay(100);
3802 }
3803 }
3804
3805 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3806 {
3807 struct drm_device *dev = intel_crtc->base.dev;
3808 struct drm_i915_private *dev_priv = dev->dev_private;
3809 int pipe = intel_crtc->pipe;
3810 u32 reg, temp;
3811
3812 /* Switch from PCDclk to Rawclk */
3813 reg = FDI_RX_CTL(pipe);
3814 temp = I915_READ(reg);
3815 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3816
3817 /* Disable CPU FDI TX PLL */
3818 reg = FDI_TX_CTL(pipe);
3819 temp = I915_READ(reg);
3820 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3821
3822 POSTING_READ(reg);
3823 udelay(100);
3824
3825 reg = FDI_RX_CTL(pipe);
3826 temp = I915_READ(reg);
3827 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3828
3829 /* Wait for the clocks to turn off. */
3830 POSTING_READ(reg);
3831 udelay(100);
3832 }
3833
3834 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3835 {
3836 struct drm_device *dev = crtc->dev;
3837 struct drm_i915_private *dev_priv = dev->dev_private;
3838 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3839 int pipe = intel_crtc->pipe;
3840 u32 reg, temp;
3841
3842 /* disable CPU FDI tx and PCH FDI rx */
3843 reg = FDI_TX_CTL(pipe);
3844 temp = I915_READ(reg);
3845 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3846 POSTING_READ(reg);
3847
3848 reg = FDI_RX_CTL(pipe);
3849 temp = I915_READ(reg);
3850 temp &= ~(0x7 << 16);
3851 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3852 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3853
3854 POSTING_READ(reg);
3855 udelay(100);
3856
3857 /* Ironlake workaround, disable clock pointer after downing FDI */
3858 if (HAS_PCH_IBX(dev))
3859 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3860
3861 /* still set train pattern 1 */
3862 reg = FDI_TX_CTL(pipe);
3863 temp = I915_READ(reg);
3864 temp &= ~FDI_LINK_TRAIN_NONE;
3865 temp |= FDI_LINK_TRAIN_PATTERN_1;
3866 I915_WRITE(reg, temp);
3867
3868 reg = FDI_RX_CTL(pipe);
3869 temp = I915_READ(reg);
3870 if (HAS_PCH_CPT(dev)) {
3871 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3872 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3873 } else {
3874 temp &= ~FDI_LINK_TRAIN_NONE;
3875 temp |= FDI_LINK_TRAIN_PATTERN_1;
3876 }
3877 /* BPC in FDI rx is consistent with that in PIPECONF */
3878 temp &= ~(0x07 << 16);
3879 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3880 I915_WRITE(reg, temp);
3881
3882 POSTING_READ(reg);
3883 udelay(100);
3884 }
3885
3886 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3887 {
3888 struct intel_crtc *crtc;
3889
3890 /* Note that we don't need to be called with mode_config.lock here
3891 * as our list of CRTC objects is static for the lifetime of the
3892 * device and so cannot disappear as we iterate. Similarly, we can
3893 * happily treat the predicates as racy, atomic checks as userspace
3894 * cannot claim and pin a new fb without at least acquring the
3895 * struct_mutex and so serialising with us.
3896 */
3897 for_each_intel_crtc(dev, crtc) {
3898 if (atomic_read(&crtc->unpin_work_count) == 0)
3899 continue;
3900
3901 if (crtc->unpin_work)
3902 intel_wait_for_vblank(dev, crtc->pipe);
3903
3904 return true;
3905 }
3906
3907 return false;
3908 }
3909
3910 static void page_flip_completed(struct intel_crtc *intel_crtc)
3911 {
3912 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3913 struct intel_unpin_work *work = intel_crtc->unpin_work;
3914
3915 /* ensure that the unpin work is consistent wrt ->pending. */
3916 smp_rmb();
3917 intel_crtc->unpin_work = NULL;
3918
3919 if (work->event)
3920 drm_send_vblank_event(intel_crtc->base.dev,
3921 intel_crtc->pipe,
3922 work->event);
3923
3924 drm_crtc_vblank_put(&intel_crtc->base);
3925
3926 wake_up_all(&dev_priv->pending_flip_queue);
3927 queue_work(dev_priv->wq, &work->work);
3928
3929 trace_i915_flip_complete(intel_crtc->plane,
3930 work->pending_flip_obj);
3931 }
3932
3933 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3934 {
3935 struct drm_device *dev = crtc->dev;
3936 struct drm_i915_private *dev_priv = dev->dev_private;
3937
3938 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3939 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3940 !intel_crtc_has_pending_flip(crtc),
3941 60*HZ) == 0)) {
3942 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3943
3944 spin_lock_irq(&dev->event_lock);
3945 if (intel_crtc->unpin_work) {
3946 WARN_ONCE(1, "Removing stuck page flip\n");
3947 page_flip_completed(intel_crtc);
3948 }
3949 spin_unlock_irq(&dev->event_lock);
3950 }
3951
3952 if (crtc->primary->fb) {
3953 mutex_lock(&dev->struct_mutex);
3954 intel_finish_fb(crtc->primary->fb);
3955 mutex_unlock(&dev->struct_mutex);
3956 }
3957 }
3958
3959 /* Program iCLKIP clock to the desired frequency */
3960 static void lpt_program_iclkip(struct drm_crtc *crtc)
3961 {
3962 struct drm_device *dev = crtc->dev;
3963 struct drm_i915_private *dev_priv = dev->dev_private;
3964 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3965 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3966 u32 temp;
3967
3968 mutex_lock(&dev_priv->dpio_lock);
3969
3970 /* It is necessary to ungate the pixclk gate prior to programming
3971 * the divisors, and gate it back when it is done.
3972 */
3973 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3974
3975 /* Disable SSCCTL */
3976 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3977 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3978 SBI_SSCCTL_DISABLE,
3979 SBI_ICLK);
3980
3981 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3982 if (clock == 20000) {
3983 auxdiv = 1;
3984 divsel = 0x41;
3985 phaseinc = 0x20;
3986 } else {
3987 /* The iCLK virtual clock root frequency is in MHz,
3988 * but the adjusted_mode->crtc_clock in in KHz. To get the
3989 * divisors, it is necessary to divide one by another, so we
3990 * convert the virtual clock precision to KHz here for higher
3991 * precision.
3992 */
3993 u32 iclk_virtual_root_freq = 172800 * 1000;
3994 u32 iclk_pi_range = 64;
3995 u32 desired_divisor, msb_divisor_value, pi_value;
3996
3997 desired_divisor = (iclk_virtual_root_freq / clock);
3998 msb_divisor_value = desired_divisor / iclk_pi_range;
3999 pi_value = desired_divisor % iclk_pi_range;
4000
4001 auxdiv = 0;
4002 divsel = msb_divisor_value - 2;
4003 phaseinc = pi_value;
4004 }
4005
4006 /* This should not happen with any sane values */
4007 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4008 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4009 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4010 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4011
4012 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4013 clock,
4014 auxdiv,
4015 divsel,
4016 phasedir,
4017 phaseinc);
4018
4019 /* Program SSCDIVINTPHASE6 */
4020 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4021 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4022 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4023 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4024 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4025 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4026 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4027 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4028
4029 /* Program SSCAUXDIV */
4030 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4031 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4032 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4033 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4034
4035 /* Enable modulator and associated divider */
4036 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4037 temp &= ~SBI_SSCCTL_DISABLE;
4038 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4039
4040 /* Wait for initialization time */
4041 udelay(24);
4042
4043 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4044
4045 mutex_unlock(&dev_priv->dpio_lock);
4046 }
4047
4048 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4049 enum pipe pch_transcoder)
4050 {
4051 struct drm_device *dev = crtc->base.dev;
4052 struct drm_i915_private *dev_priv = dev->dev_private;
4053 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4054
4055 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4056 I915_READ(HTOTAL(cpu_transcoder)));
4057 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4058 I915_READ(HBLANK(cpu_transcoder)));
4059 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4060 I915_READ(HSYNC(cpu_transcoder)));
4061
4062 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4063 I915_READ(VTOTAL(cpu_transcoder)));
4064 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4065 I915_READ(VBLANK(cpu_transcoder)));
4066 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4067 I915_READ(VSYNC(cpu_transcoder)));
4068 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4069 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4070 }
4071
4072 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4073 {
4074 struct drm_i915_private *dev_priv = dev->dev_private;
4075 uint32_t temp;
4076
4077 temp = I915_READ(SOUTH_CHICKEN1);
4078 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4079 return;
4080
4081 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4082 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4083
4084 temp &= ~FDI_BC_BIFURCATION_SELECT;
4085 if (enable)
4086 temp |= FDI_BC_BIFURCATION_SELECT;
4087
4088 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4089 I915_WRITE(SOUTH_CHICKEN1, temp);
4090 POSTING_READ(SOUTH_CHICKEN1);
4091 }
4092
4093 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4094 {
4095 struct drm_device *dev = intel_crtc->base.dev;
4096
4097 switch (intel_crtc->pipe) {
4098 case PIPE_A:
4099 break;
4100 case PIPE_B:
4101 if (intel_crtc->config->fdi_lanes > 2)
4102 cpt_set_fdi_bc_bifurcation(dev, false);
4103 else
4104 cpt_set_fdi_bc_bifurcation(dev, true);
4105
4106 break;
4107 case PIPE_C:
4108 cpt_set_fdi_bc_bifurcation(dev, true);
4109
4110 break;
4111 default:
4112 BUG();
4113 }
4114 }
4115
4116 /*
4117 * Enable PCH resources required for PCH ports:
4118 * - PCH PLLs
4119 * - FDI training & RX/TX
4120 * - update transcoder timings
4121 * - DP transcoding bits
4122 * - transcoder
4123 */
4124 static void ironlake_pch_enable(struct drm_crtc *crtc)
4125 {
4126 struct drm_device *dev = crtc->dev;
4127 struct drm_i915_private *dev_priv = dev->dev_private;
4128 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4129 int pipe = intel_crtc->pipe;
4130 u32 reg, temp;
4131
4132 assert_pch_transcoder_disabled(dev_priv, pipe);
4133
4134 if (IS_IVYBRIDGE(dev))
4135 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4136
4137 /* Write the TU size bits before fdi link training, so that error
4138 * detection works. */
4139 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4140 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4141
4142 /* For PCH output, training FDI link */
4143 dev_priv->display.fdi_link_train(crtc);
4144
4145 /* We need to program the right clock selection before writing the pixel
4146 * mutliplier into the DPLL. */
4147 if (HAS_PCH_CPT(dev)) {
4148 u32 sel;
4149
4150 temp = I915_READ(PCH_DPLL_SEL);
4151 temp |= TRANS_DPLL_ENABLE(pipe);
4152 sel = TRANS_DPLLB_SEL(pipe);
4153 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4154 temp |= sel;
4155 else
4156 temp &= ~sel;
4157 I915_WRITE(PCH_DPLL_SEL, temp);
4158 }
4159
4160 /* XXX: pch pll's can be enabled any time before we enable the PCH
4161 * transcoder, and we actually should do this to not upset any PCH
4162 * transcoder that already use the clock when we share it.
4163 *
4164 * Note that enable_shared_dpll tries to do the right thing, but
4165 * get_shared_dpll unconditionally resets the pll - we need that to have
4166 * the right LVDS enable sequence. */
4167 intel_enable_shared_dpll(intel_crtc);
4168
4169 /* set transcoder timing, panel must allow it */
4170 assert_panel_unlocked(dev_priv, pipe);
4171 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4172
4173 intel_fdi_normal_train(crtc);
4174
4175 /* For PCH DP, enable TRANS_DP_CTL */
4176 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4177 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4178 reg = TRANS_DP_CTL(pipe);
4179 temp = I915_READ(reg);
4180 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4181 TRANS_DP_SYNC_MASK |
4182 TRANS_DP_BPC_MASK);
4183 temp |= (TRANS_DP_OUTPUT_ENABLE |
4184 TRANS_DP_ENH_FRAMING);
4185 temp |= bpc << 9; /* same format but at 11:9 */
4186
4187 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4188 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4189 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4190 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4191
4192 switch (intel_trans_dp_port_sel(crtc)) {
4193 case PCH_DP_B:
4194 temp |= TRANS_DP_PORT_SEL_B;
4195 break;
4196 case PCH_DP_C:
4197 temp |= TRANS_DP_PORT_SEL_C;
4198 break;
4199 case PCH_DP_D:
4200 temp |= TRANS_DP_PORT_SEL_D;
4201 break;
4202 default:
4203 BUG();
4204 }
4205
4206 I915_WRITE(reg, temp);
4207 }
4208
4209 ironlake_enable_pch_transcoder(dev_priv, pipe);
4210 }
4211
4212 static void lpt_pch_enable(struct drm_crtc *crtc)
4213 {
4214 struct drm_device *dev = crtc->dev;
4215 struct drm_i915_private *dev_priv = dev->dev_private;
4216 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4217 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4218
4219 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4220
4221 lpt_program_iclkip(crtc);
4222
4223 /* Set transcoder timing. */
4224 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4225
4226 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4227 }
4228
4229 void intel_put_shared_dpll(struct intel_crtc *crtc)
4230 {
4231 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4232
4233 if (pll == NULL)
4234 return;
4235
4236 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
4237 WARN(1, "bad %s crtc mask\n", pll->name);
4238 return;
4239 }
4240
4241 pll->config.crtc_mask &= ~(1 << crtc->pipe);
4242 if (pll->config.crtc_mask == 0) {
4243 WARN_ON(pll->on);
4244 WARN_ON(pll->active);
4245 }
4246
4247 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
4248 }
4249
4250 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4251 struct intel_crtc_state *crtc_state)
4252 {
4253 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4254 struct intel_shared_dpll *pll;
4255 enum intel_dpll_id i;
4256
4257 if (HAS_PCH_IBX(dev_priv->dev)) {
4258 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4259 i = (enum intel_dpll_id) crtc->pipe;
4260 pll = &dev_priv->shared_dplls[i];
4261
4262 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4263 crtc->base.base.id, pll->name);
4264
4265 WARN_ON(pll->new_config->crtc_mask);
4266
4267 goto found;
4268 }
4269
4270 if (IS_BROXTON(dev_priv->dev)) {
4271 /* PLL is attached to port in bxt */
4272 struct intel_encoder *encoder;
4273 struct intel_digital_port *intel_dig_port;
4274
4275 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4276 if (WARN_ON(!encoder))
4277 return NULL;
4278
4279 intel_dig_port = enc_to_dig_port(&encoder->base);
4280 /* 1:1 mapping between ports and PLLs */
4281 i = (enum intel_dpll_id)intel_dig_port->port;
4282 pll = &dev_priv->shared_dplls[i];
4283 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4284 crtc->base.base.id, pll->name);
4285 WARN_ON(pll->new_config->crtc_mask);
4286
4287 goto found;
4288 }
4289
4290 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4291 pll = &dev_priv->shared_dplls[i];
4292
4293 /* Only want to check enabled timings first */
4294 if (pll->new_config->crtc_mask == 0)
4295 continue;
4296
4297 if (memcmp(&crtc_state->dpll_hw_state,
4298 &pll->new_config->hw_state,
4299 sizeof(pll->new_config->hw_state)) == 0) {
4300 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4301 crtc->base.base.id, pll->name,
4302 pll->new_config->crtc_mask,
4303 pll->active);
4304 goto found;
4305 }
4306 }
4307
4308 /* Ok no matching timings, maybe there's a free one? */
4309 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4310 pll = &dev_priv->shared_dplls[i];
4311 if (pll->new_config->crtc_mask == 0) {
4312 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4313 crtc->base.base.id, pll->name);
4314 goto found;
4315 }
4316 }
4317
4318 return NULL;
4319
4320 found:
4321 if (pll->new_config->crtc_mask == 0)
4322 pll->new_config->hw_state = crtc_state->dpll_hw_state;
4323
4324 crtc_state->shared_dpll = i;
4325 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4326 pipe_name(crtc->pipe));
4327
4328 pll->new_config->crtc_mask |= 1 << crtc->pipe;
4329
4330 return pll;
4331 }
4332
4333 /**
4334 * intel_shared_dpll_start_config - start a new PLL staged config
4335 * @dev_priv: DRM device
4336 * @clear_pipes: mask of pipes that will have their PLLs freed
4337 *
4338 * Starts a new PLL staged config, copying the current config but
4339 * releasing the references of pipes specified in clear_pipes.
4340 */
4341 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4342 unsigned clear_pipes)
4343 {
4344 struct intel_shared_dpll *pll;
4345 enum intel_dpll_id i;
4346
4347 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4348 pll = &dev_priv->shared_dplls[i];
4349
4350 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4351 GFP_KERNEL);
4352 if (!pll->new_config)
4353 goto cleanup;
4354
4355 pll->new_config->crtc_mask &= ~clear_pipes;
4356 }
4357
4358 return 0;
4359
4360 cleanup:
4361 while (--i >= 0) {
4362 pll = &dev_priv->shared_dplls[i];
4363 kfree(pll->new_config);
4364 pll->new_config = NULL;
4365 }
4366
4367 return -ENOMEM;
4368 }
4369
4370 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4371 {
4372 struct intel_shared_dpll *pll;
4373 enum intel_dpll_id i;
4374
4375 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4376 pll = &dev_priv->shared_dplls[i];
4377
4378 WARN_ON(pll->new_config == &pll->config);
4379
4380 pll->config = *pll->new_config;
4381 kfree(pll->new_config);
4382 pll->new_config = NULL;
4383 }
4384 }
4385
4386 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4387 {
4388 struct intel_shared_dpll *pll;
4389 enum intel_dpll_id i;
4390
4391 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4392 pll = &dev_priv->shared_dplls[i];
4393
4394 WARN_ON(pll->new_config == &pll->config);
4395
4396 kfree(pll->new_config);
4397 pll->new_config = NULL;
4398 }
4399 }
4400
4401 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4402 {
4403 struct drm_i915_private *dev_priv = dev->dev_private;
4404 int dslreg = PIPEDSL(pipe);
4405 u32 temp;
4406
4407 temp = I915_READ(dslreg);
4408 udelay(500);
4409 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4410 if (wait_for(I915_READ(dslreg) != temp, 5))
4411 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4412 }
4413 }
4414
4415 /**
4416 * skl_update_scaler_users - Stages update to crtc's scaler state
4417 * @intel_crtc: crtc
4418 * @crtc_state: crtc_state
4419 * @plane: plane (NULL indicates crtc is requesting update)
4420 * @plane_state: plane's state
4421 * @force_detach: request unconditional detachment of scaler
4422 *
4423 * This function updates scaler state for requested plane or crtc.
4424 * To request scaler usage update for a plane, caller shall pass plane pointer.
4425 * To request scaler usage update for crtc, caller shall pass plane pointer
4426 * as NULL.
4427 *
4428 * Return
4429 * 0 - scaler_usage updated successfully
4430 * error - requested scaling cannot be supported or other error condition
4431 */
4432 int
4433 skl_update_scaler_users(
4434 struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state,
4435 struct intel_plane *intel_plane, struct intel_plane_state *plane_state,
4436 int force_detach)
4437 {
4438 int need_scaling;
4439 int idx;
4440 int src_w, src_h, dst_w, dst_h;
4441 int *scaler_id;
4442 struct drm_framebuffer *fb;
4443 struct intel_crtc_scaler_state *scaler_state;
4444 unsigned int rotation;
4445
4446 if (!intel_crtc || !crtc_state)
4447 return 0;
4448
4449 scaler_state = &crtc_state->scaler_state;
4450
4451 idx = intel_plane ? drm_plane_index(&intel_plane->base) : SKL_CRTC_INDEX;
4452 fb = intel_plane ? plane_state->base.fb : NULL;
4453
4454 if (intel_plane) {
4455 src_w = drm_rect_width(&plane_state->src) >> 16;
4456 src_h = drm_rect_height(&plane_state->src) >> 16;
4457 dst_w = drm_rect_width(&plane_state->dst);
4458 dst_h = drm_rect_height(&plane_state->dst);
4459 scaler_id = &plane_state->scaler_id;
4460 rotation = plane_state->base.rotation;
4461 } else {
4462 struct drm_display_mode *adjusted_mode =
4463 &crtc_state->base.adjusted_mode;
4464 src_w = crtc_state->pipe_src_w;
4465 src_h = crtc_state->pipe_src_h;
4466 dst_w = adjusted_mode->hdisplay;
4467 dst_h = adjusted_mode->vdisplay;
4468 scaler_id = &scaler_state->scaler_id;
4469 rotation = DRM_ROTATE_0;
4470 }
4471
4472 need_scaling = intel_rotation_90_or_270(rotation) ?
4473 (src_h != dst_w || src_w != dst_h):
4474 (src_w != dst_w || src_h != dst_h);
4475
4476 /*
4477 * if plane is being disabled or scaler is no more required or force detach
4478 * - free scaler binded to this plane/crtc
4479 * - in order to do this, update crtc->scaler_usage
4480 *
4481 * Here scaler state in crtc_state is set free so that
4482 * scaler can be assigned to other user. Actual register
4483 * update to free the scaler is done in plane/panel-fit programming.
4484 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4485 */
4486 if (force_detach || !need_scaling || (intel_plane &&
4487 (!fb || !plane_state->visible))) {
4488 if (*scaler_id >= 0) {
4489 scaler_state->scaler_users &= ~(1 << idx);
4490 scaler_state->scalers[*scaler_id].in_use = 0;
4491
4492 DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d "
4493 "crtc_state = %p scaler_users = 0x%x\n",
4494 intel_crtc->pipe, *scaler_id, intel_plane ? "PLANE" : "CRTC",
4495 intel_plane ? intel_plane->base.base.id :
4496 intel_crtc->base.base.id, crtc_state,
4497 scaler_state->scaler_users);
4498 *scaler_id = -1;
4499 }
4500 return 0;
4501 }
4502
4503 /* range checks */
4504 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4505 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4506
4507 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4508 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4509 DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u "
4510 "size is out of scaler range\n",
4511 intel_plane ? "PLANE" : "CRTC",
4512 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4513 intel_crtc->pipe, idx, src_w, src_h, dst_w, dst_h);
4514 return -EINVAL;
4515 }
4516
4517 /* check colorkey */
4518 if (intel_plane && intel_plane->ckey.flags != I915_SET_COLORKEY_NONE) {
4519 DRM_DEBUG_KMS("PLANE:%d scaling with color key not allowed",
4520 intel_plane->base.base.id);
4521 return -EINVAL;
4522 }
4523
4524 /* Check src format */
4525 if (intel_plane) {
4526 switch (fb->pixel_format) {
4527 case DRM_FORMAT_RGB565:
4528 case DRM_FORMAT_XBGR8888:
4529 case DRM_FORMAT_XRGB8888:
4530 case DRM_FORMAT_ABGR8888:
4531 case DRM_FORMAT_ARGB8888:
4532 case DRM_FORMAT_XRGB2101010:
4533 case DRM_FORMAT_ARGB2101010:
4534 case DRM_FORMAT_XBGR2101010:
4535 case DRM_FORMAT_ABGR2101010:
4536 case DRM_FORMAT_YUYV:
4537 case DRM_FORMAT_YVYU:
4538 case DRM_FORMAT_UYVY:
4539 case DRM_FORMAT_VYUY:
4540 break;
4541 default:
4542 DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n",
4543 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4544 return -EINVAL;
4545 }
4546 }
4547
4548 /* mark this plane as a scaler user in crtc_state */
4549 scaler_state->scaler_users |= (1 << idx);
4550 DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u "
4551 "crtc_state = %p scaler_users = 0x%x\n",
4552 intel_plane ? "PLANE" : "CRTC",
4553 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4554 src_w, src_h, dst_w, dst_h, crtc_state, scaler_state->scaler_users);
4555 return 0;
4556 }
4557
4558 static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
4559 {
4560 struct drm_device *dev = crtc->base.dev;
4561 struct drm_i915_private *dev_priv = dev->dev_private;
4562 int pipe = crtc->pipe;
4563 struct intel_crtc_scaler_state *scaler_state =
4564 &crtc->config->scaler_state;
4565
4566 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4567
4568 /* To update pfit, first update scaler state */
4569 skl_update_scaler_users(crtc, crtc->config, NULL, NULL, !enable);
4570 intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4571 skl_detach_scalers(crtc);
4572 if (!enable)
4573 return;
4574
4575 if (crtc->config->pch_pfit.enabled) {
4576 int id;
4577
4578 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4579 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4580 return;
4581 }
4582
4583 id = scaler_state->scaler_id;
4584 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4585 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4586 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4587 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4588
4589 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4590 }
4591 }
4592
4593 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4594 {
4595 struct drm_device *dev = crtc->base.dev;
4596 struct drm_i915_private *dev_priv = dev->dev_private;
4597 int pipe = crtc->pipe;
4598
4599 if (crtc->config->pch_pfit.enabled) {
4600 /* Force use of hard-coded filter coefficients
4601 * as some pre-programmed values are broken,
4602 * e.g. x201.
4603 */
4604 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4605 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4606 PF_PIPE_SEL_IVB(pipe));
4607 else
4608 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4609 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4610 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4611 }
4612 }
4613
4614 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4615 {
4616 struct drm_device *dev = crtc->dev;
4617 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4618 struct drm_plane *plane;
4619 struct intel_plane *intel_plane;
4620
4621 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4622 intel_plane = to_intel_plane(plane);
4623 if (intel_plane->pipe == pipe)
4624 intel_plane_restore(&intel_plane->base);
4625 }
4626 }
4627
4628 void hsw_enable_ips(struct intel_crtc *crtc)
4629 {
4630 struct drm_device *dev = crtc->base.dev;
4631 struct drm_i915_private *dev_priv = dev->dev_private;
4632
4633 if (!crtc->config->ips_enabled)
4634 return;
4635
4636 /* We can only enable IPS after we enable a plane and wait for a vblank */
4637 intel_wait_for_vblank(dev, crtc->pipe);
4638
4639 assert_plane_enabled(dev_priv, crtc->plane);
4640 if (IS_BROADWELL(dev)) {
4641 mutex_lock(&dev_priv->rps.hw_lock);
4642 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4643 mutex_unlock(&dev_priv->rps.hw_lock);
4644 /* Quoting Art Runyan: "its not safe to expect any particular
4645 * value in IPS_CTL bit 31 after enabling IPS through the
4646 * mailbox." Moreover, the mailbox may return a bogus state,
4647 * so we need to just enable it and continue on.
4648 */
4649 } else {
4650 I915_WRITE(IPS_CTL, IPS_ENABLE);
4651 /* The bit only becomes 1 in the next vblank, so this wait here
4652 * is essentially intel_wait_for_vblank. If we don't have this
4653 * and don't wait for vblanks until the end of crtc_enable, then
4654 * the HW state readout code will complain that the expected
4655 * IPS_CTL value is not the one we read. */
4656 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4657 DRM_ERROR("Timed out waiting for IPS enable\n");
4658 }
4659 }
4660
4661 void hsw_disable_ips(struct intel_crtc *crtc)
4662 {
4663 struct drm_device *dev = crtc->base.dev;
4664 struct drm_i915_private *dev_priv = dev->dev_private;
4665
4666 if (!crtc->config->ips_enabled)
4667 return;
4668
4669 assert_plane_enabled(dev_priv, crtc->plane);
4670 if (IS_BROADWELL(dev)) {
4671 mutex_lock(&dev_priv->rps.hw_lock);
4672 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4673 mutex_unlock(&dev_priv->rps.hw_lock);
4674 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4675 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4676 DRM_ERROR("Timed out waiting for IPS disable\n");
4677 } else {
4678 I915_WRITE(IPS_CTL, 0);
4679 POSTING_READ(IPS_CTL);
4680 }
4681
4682 /* We need to wait for a vblank before we can disable the plane. */
4683 intel_wait_for_vblank(dev, crtc->pipe);
4684 }
4685
4686 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4687 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4688 {
4689 struct drm_device *dev = crtc->dev;
4690 struct drm_i915_private *dev_priv = dev->dev_private;
4691 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4692 enum pipe pipe = intel_crtc->pipe;
4693 int palreg = PALETTE(pipe);
4694 int i;
4695 bool reenable_ips = false;
4696
4697 /* The clocks have to be on to load the palette. */
4698 if (!crtc->state->enable || !intel_crtc->active)
4699 return;
4700
4701 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4702 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4703 assert_dsi_pll_enabled(dev_priv);
4704 else
4705 assert_pll_enabled(dev_priv, pipe);
4706 }
4707
4708 /* use legacy palette for Ironlake */
4709 if (!HAS_GMCH_DISPLAY(dev))
4710 palreg = LGC_PALETTE(pipe);
4711
4712 /* Workaround : Do not read or write the pipe palette/gamma data while
4713 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4714 */
4715 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4716 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4717 GAMMA_MODE_MODE_SPLIT)) {
4718 hsw_disable_ips(intel_crtc);
4719 reenable_ips = true;
4720 }
4721
4722 for (i = 0; i < 256; i++) {
4723 I915_WRITE(palreg + 4 * i,
4724 (intel_crtc->lut_r[i] << 16) |
4725 (intel_crtc->lut_g[i] << 8) |
4726 intel_crtc->lut_b[i]);
4727 }
4728
4729 if (reenable_ips)
4730 hsw_enable_ips(intel_crtc);
4731 }
4732
4733 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4734 {
4735 if (intel_crtc->overlay) {
4736 struct drm_device *dev = intel_crtc->base.dev;
4737 struct drm_i915_private *dev_priv = dev->dev_private;
4738
4739 mutex_lock(&dev->struct_mutex);
4740 dev_priv->mm.interruptible = false;
4741 (void) intel_overlay_switch_off(intel_crtc->overlay);
4742 dev_priv->mm.interruptible = true;
4743 mutex_unlock(&dev->struct_mutex);
4744 }
4745
4746 /* Let userspace switch the overlay on again. In most cases userspace
4747 * has to recompute where to put it anyway.
4748 */
4749 }
4750
4751 /**
4752 * intel_post_enable_primary - Perform operations after enabling primary plane
4753 * @crtc: the CRTC whose primary plane was just enabled
4754 *
4755 * Performs potentially sleeping operations that must be done after the primary
4756 * plane is enabled, such as updating FBC and IPS. Note that this may be
4757 * called due to an explicit primary plane update, or due to an implicit
4758 * re-enable that is caused when a sprite plane is updated to no longer
4759 * completely hide the primary plane.
4760 */
4761 static void
4762 intel_post_enable_primary(struct drm_crtc *crtc)
4763 {
4764 struct drm_device *dev = crtc->dev;
4765 struct drm_i915_private *dev_priv = dev->dev_private;
4766 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4767 int pipe = intel_crtc->pipe;
4768
4769 /*
4770 * BDW signals flip done immediately if the plane
4771 * is disabled, even if the plane enable is already
4772 * armed to occur at the next vblank :(
4773 */
4774 if (IS_BROADWELL(dev))
4775 intel_wait_for_vblank(dev, pipe);
4776
4777 /*
4778 * FIXME IPS should be fine as long as one plane is
4779 * enabled, but in practice it seems to have problems
4780 * when going from primary only to sprite only and vice
4781 * versa.
4782 */
4783 hsw_enable_ips(intel_crtc);
4784
4785 mutex_lock(&dev->struct_mutex);
4786 intel_fbc_update(dev);
4787 mutex_unlock(&dev->struct_mutex);
4788
4789 /*
4790 * Gen2 reports pipe underruns whenever all planes are disabled.
4791 * So don't enable underrun reporting before at least some planes
4792 * are enabled.
4793 * FIXME: Need to fix the logic to work when we turn off all planes
4794 * but leave the pipe running.
4795 */
4796 if (IS_GEN2(dev))
4797 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4798
4799 /* Underruns don't raise interrupts, so check manually. */
4800 if (HAS_GMCH_DISPLAY(dev))
4801 i9xx_check_fifo_underruns(dev_priv);
4802 }
4803
4804 /**
4805 * intel_pre_disable_primary - Perform operations before disabling primary plane
4806 * @crtc: the CRTC whose primary plane is to be disabled
4807 *
4808 * Performs potentially sleeping operations that must be done before the
4809 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4810 * be called due to an explicit primary plane update, or due to an implicit
4811 * disable that is caused when a sprite plane completely hides the primary
4812 * plane.
4813 */
4814 static void
4815 intel_pre_disable_primary(struct drm_crtc *crtc)
4816 {
4817 struct drm_device *dev = crtc->dev;
4818 struct drm_i915_private *dev_priv = dev->dev_private;
4819 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4820 int pipe = intel_crtc->pipe;
4821
4822 /*
4823 * Gen2 reports pipe underruns whenever all planes are disabled.
4824 * So diasble underrun reporting before all the planes get disabled.
4825 * FIXME: Need to fix the logic to work when we turn off all planes
4826 * but leave the pipe running.
4827 */
4828 if (IS_GEN2(dev))
4829 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4830
4831 /*
4832 * Vblank time updates from the shadow to live plane control register
4833 * are blocked if the memory self-refresh mode is active at that
4834 * moment. So to make sure the plane gets truly disabled, disable
4835 * first the self-refresh mode. The self-refresh enable bit in turn
4836 * will be checked/applied by the HW only at the next frame start
4837 * event which is after the vblank start event, so we need to have a
4838 * wait-for-vblank between disabling the plane and the pipe.
4839 */
4840 if (HAS_GMCH_DISPLAY(dev))
4841 intel_set_memory_cxsr(dev_priv, false);
4842
4843 mutex_lock(&dev->struct_mutex);
4844 if (dev_priv->fbc.crtc == intel_crtc)
4845 intel_fbc_disable(dev);
4846 mutex_unlock(&dev->struct_mutex);
4847
4848 /*
4849 * FIXME IPS should be fine as long as one plane is
4850 * enabled, but in practice it seems to have problems
4851 * when going from primary only to sprite only and vice
4852 * versa.
4853 */
4854 hsw_disable_ips(intel_crtc);
4855 }
4856
4857 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4858 {
4859 intel_enable_primary_hw_plane(crtc->primary, crtc);
4860 intel_enable_sprite_planes(crtc);
4861 intel_crtc_update_cursor(crtc, true);
4862
4863 intel_post_enable_primary(crtc);
4864 }
4865
4866 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4867 {
4868 struct drm_device *dev = crtc->dev;
4869 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4870 struct intel_plane *intel_plane;
4871 int pipe = intel_crtc->pipe;
4872
4873 intel_crtc_wait_for_pending_flips(crtc);
4874
4875 intel_pre_disable_primary(crtc);
4876
4877 intel_crtc_dpms_overlay_disable(intel_crtc);
4878 for_each_intel_plane(dev, intel_plane) {
4879 if (intel_plane->pipe == pipe) {
4880 struct drm_crtc *from = intel_plane->base.crtc;
4881
4882 intel_plane->disable_plane(&intel_plane->base,
4883 from ?: crtc, true);
4884 }
4885 }
4886
4887 /*
4888 * FIXME: Once we grow proper nuclear flip support out of this we need
4889 * to compute the mask of flip planes precisely. For the time being
4890 * consider this a flip to a NULL plane.
4891 */
4892 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4893 }
4894
4895 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4896 {
4897 struct drm_device *dev = crtc->dev;
4898 struct drm_i915_private *dev_priv = dev->dev_private;
4899 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4900 struct intel_encoder *encoder;
4901 int pipe = intel_crtc->pipe;
4902
4903 WARN_ON(!crtc->state->enable);
4904
4905 if (intel_crtc->active)
4906 return;
4907
4908 if (intel_crtc->config->has_pch_encoder)
4909 intel_prepare_shared_dpll(intel_crtc);
4910
4911 if (intel_crtc->config->has_dp_encoder)
4912 intel_dp_set_m_n(intel_crtc, M1_N1);
4913
4914 intel_set_pipe_timings(intel_crtc);
4915
4916 if (intel_crtc->config->has_pch_encoder) {
4917 intel_cpu_transcoder_set_m_n(intel_crtc,
4918 &intel_crtc->config->fdi_m_n, NULL);
4919 }
4920
4921 ironlake_set_pipeconf(crtc);
4922
4923 intel_crtc->active = true;
4924
4925 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4926 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4927
4928 for_each_encoder_on_crtc(dev, crtc, encoder)
4929 if (encoder->pre_enable)
4930 encoder->pre_enable(encoder);
4931
4932 if (intel_crtc->config->has_pch_encoder) {
4933 /* Note: FDI PLL enabling _must_ be done before we enable the
4934 * cpu pipes, hence this is separate from all the other fdi/pch
4935 * enabling. */
4936 ironlake_fdi_pll_enable(intel_crtc);
4937 } else {
4938 assert_fdi_tx_disabled(dev_priv, pipe);
4939 assert_fdi_rx_disabled(dev_priv, pipe);
4940 }
4941
4942 ironlake_pfit_enable(intel_crtc);
4943
4944 /*
4945 * On ILK+ LUT must be loaded before the pipe is running but with
4946 * clocks enabled
4947 */
4948 intel_crtc_load_lut(crtc);
4949
4950 intel_update_watermarks(crtc);
4951 intel_enable_pipe(intel_crtc);
4952
4953 if (intel_crtc->config->has_pch_encoder)
4954 ironlake_pch_enable(crtc);
4955
4956 assert_vblank_disabled(crtc);
4957 drm_crtc_vblank_on(crtc);
4958
4959 for_each_encoder_on_crtc(dev, crtc, encoder)
4960 encoder->enable(encoder);
4961
4962 if (HAS_PCH_CPT(dev))
4963 cpt_verify_modeset(dev, intel_crtc->pipe);
4964 }
4965
4966 /* IPS only exists on ULT machines and is tied to pipe A. */
4967 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4968 {
4969 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4970 }
4971
4972 /*
4973 * This implements the workaround described in the "notes" section of the mode
4974 * set sequence documentation. When going from no pipes or single pipe to
4975 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4976 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4977 */
4978 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4979 {
4980 struct drm_device *dev = crtc->base.dev;
4981 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4982
4983 /* We want to get the other_active_crtc only if there's only 1 other
4984 * active crtc. */
4985 for_each_intel_crtc(dev, crtc_it) {
4986 if (!crtc_it->active || crtc_it == crtc)
4987 continue;
4988
4989 if (other_active_crtc)
4990 return;
4991
4992 other_active_crtc = crtc_it;
4993 }
4994 if (!other_active_crtc)
4995 return;
4996
4997 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4998 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4999 }
5000
5001 static void haswell_crtc_enable(struct drm_crtc *crtc)
5002 {
5003 struct drm_device *dev = crtc->dev;
5004 struct drm_i915_private *dev_priv = dev->dev_private;
5005 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5006 struct intel_encoder *encoder;
5007 int pipe = intel_crtc->pipe;
5008
5009 WARN_ON(!crtc->state->enable);
5010
5011 if (intel_crtc->active)
5012 return;
5013
5014 if (intel_crtc_to_shared_dpll(intel_crtc))
5015 intel_enable_shared_dpll(intel_crtc);
5016
5017 if (intel_crtc->config->has_dp_encoder)
5018 intel_dp_set_m_n(intel_crtc, M1_N1);
5019
5020 intel_set_pipe_timings(intel_crtc);
5021
5022 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
5023 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
5024 intel_crtc->config->pixel_multiplier - 1);
5025 }
5026
5027 if (intel_crtc->config->has_pch_encoder) {
5028 intel_cpu_transcoder_set_m_n(intel_crtc,
5029 &intel_crtc->config->fdi_m_n, NULL);
5030 }
5031
5032 haswell_set_pipeconf(crtc);
5033
5034 intel_set_pipe_csc(crtc);
5035
5036 intel_crtc->active = true;
5037
5038 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5039 for_each_encoder_on_crtc(dev, crtc, encoder)
5040 if (encoder->pre_enable)
5041 encoder->pre_enable(encoder);
5042
5043 if (intel_crtc->config->has_pch_encoder) {
5044 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5045 true);
5046 dev_priv->display.fdi_link_train(crtc);
5047 }
5048
5049 intel_ddi_enable_pipe_clock(intel_crtc);
5050
5051 if (INTEL_INFO(dev)->gen == 9)
5052 skylake_pfit_update(intel_crtc, 1);
5053 else if (INTEL_INFO(dev)->gen < 9)
5054 ironlake_pfit_enable(intel_crtc);
5055 else
5056 MISSING_CASE(INTEL_INFO(dev)->gen);
5057
5058 /*
5059 * On ILK+ LUT must be loaded before the pipe is running but with
5060 * clocks enabled
5061 */
5062 intel_crtc_load_lut(crtc);
5063
5064 intel_ddi_set_pipe_settings(crtc);
5065 intel_ddi_enable_transcoder_func(crtc);
5066
5067 intel_update_watermarks(crtc);
5068 intel_enable_pipe(intel_crtc);
5069
5070 if (intel_crtc->config->has_pch_encoder)
5071 lpt_pch_enable(crtc);
5072
5073 if (intel_crtc->config->dp_encoder_is_mst)
5074 intel_ddi_set_vc_payload_alloc(crtc, true);
5075
5076 assert_vblank_disabled(crtc);
5077 drm_crtc_vblank_on(crtc);
5078
5079 for_each_encoder_on_crtc(dev, crtc, encoder) {
5080 encoder->enable(encoder);
5081 intel_opregion_notify_encoder(encoder, true);
5082 }
5083
5084 /* If we change the relative order between pipe/planes enabling, we need
5085 * to change the workaround. */
5086 haswell_mode_set_planes_workaround(intel_crtc);
5087 }
5088
5089 static void ironlake_pfit_disable(struct intel_crtc *crtc)
5090 {
5091 struct drm_device *dev = crtc->base.dev;
5092 struct drm_i915_private *dev_priv = dev->dev_private;
5093 int pipe = crtc->pipe;
5094
5095 /* To avoid upsetting the power well on haswell only disable the pfit if
5096 * it's in use. The hw state code will make sure we get this right. */
5097 if (crtc->config->pch_pfit.enabled) {
5098 I915_WRITE(PF_CTL(pipe), 0);
5099 I915_WRITE(PF_WIN_POS(pipe), 0);
5100 I915_WRITE(PF_WIN_SZ(pipe), 0);
5101 }
5102 }
5103
5104 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5105 {
5106 struct drm_device *dev = crtc->dev;
5107 struct drm_i915_private *dev_priv = dev->dev_private;
5108 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5109 struct intel_encoder *encoder;
5110 int pipe = intel_crtc->pipe;
5111 u32 reg, temp;
5112
5113 if (!intel_crtc->active)
5114 return;
5115
5116 for_each_encoder_on_crtc(dev, crtc, encoder)
5117 encoder->disable(encoder);
5118
5119 drm_crtc_vblank_off(crtc);
5120 assert_vblank_disabled(crtc);
5121
5122 if (intel_crtc->config->has_pch_encoder)
5123 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5124
5125 intel_disable_pipe(intel_crtc);
5126
5127 ironlake_pfit_disable(intel_crtc);
5128
5129 for_each_encoder_on_crtc(dev, crtc, encoder)
5130 if (encoder->post_disable)
5131 encoder->post_disable(encoder);
5132
5133 if (intel_crtc->config->has_pch_encoder) {
5134 ironlake_fdi_disable(crtc);
5135
5136 ironlake_disable_pch_transcoder(dev_priv, pipe);
5137
5138 if (HAS_PCH_CPT(dev)) {
5139 /* disable TRANS_DP_CTL */
5140 reg = TRANS_DP_CTL(pipe);
5141 temp = I915_READ(reg);
5142 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5143 TRANS_DP_PORT_SEL_MASK);
5144 temp |= TRANS_DP_PORT_SEL_NONE;
5145 I915_WRITE(reg, temp);
5146
5147 /* disable DPLL_SEL */
5148 temp = I915_READ(PCH_DPLL_SEL);
5149 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5150 I915_WRITE(PCH_DPLL_SEL, temp);
5151 }
5152
5153 /* disable PCH DPLL */
5154 intel_disable_shared_dpll(intel_crtc);
5155
5156 ironlake_fdi_pll_disable(intel_crtc);
5157 }
5158
5159 intel_crtc->active = false;
5160 intel_update_watermarks(crtc);
5161
5162 mutex_lock(&dev->struct_mutex);
5163 intel_fbc_update(dev);
5164 mutex_unlock(&dev->struct_mutex);
5165 }
5166
5167 static void haswell_crtc_disable(struct drm_crtc *crtc)
5168 {
5169 struct drm_device *dev = crtc->dev;
5170 struct drm_i915_private *dev_priv = dev->dev_private;
5171 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5172 struct intel_encoder *encoder;
5173 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5174
5175 if (!intel_crtc->active)
5176 return;
5177
5178 for_each_encoder_on_crtc(dev, crtc, encoder) {
5179 intel_opregion_notify_encoder(encoder, false);
5180 encoder->disable(encoder);
5181 }
5182
5183 drm_crtc_vblank_off(crtc);
5184 assert_vblank_disabled(crtc);
5185
5186 if (intel_crtc->config->has_pch_encoder)
5187 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5188 false);
5189 intel_disable_pipe(intel_crtc);
5190
5191 if (intel_crtc->config->dp_encoder_is_mst)
5192 intel_ddi_set_vc_payload_alloc(crtc, false);
5193
5194 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5195
5196 if (INTEL_INFO(dev)->gen == 9)
5197 skylake_pfit_update(intel_crtc, 0);
5198 else if (INTEL_INFO(dev)->gen < 9)
5199 ironlake_pfit_disable(intel_crtc);
5200 else
5201 MISSING_CASE(INTEL_INFO(dev)->gen);
5202
5203 intel_ddi_disable_pipe_clock(intel_crtc);
5204
5205 if (intel_crtc->config->has_pch_encoder) {
5206 lpt_disable_pch_transcoder(dev_priv);
5207 intel_ddi_fdi_disable(crtc);
5208 }
5209
5210 for_each_encoder_on_crtc(dev, crtc, encoder)
5211 if (encoder->post_disable)
5212 encoder->post_disable(encoder);
5213
5214 intel_crtc->active = false;
5215 intel_update_watermarks(crtc);
5216
5217 mutex_lock(&dev->struct_mutex);
5218 intel_fbc_update(dev);
5219 mutex_unlock(&dev->struct_mutex);
5220
5221 if (intel_crtc_to_shared_dpll(intel_crtc))
5222 intel_disable_shared_dpll(intel_crtc);
5223 }
5224
5225 static void ironlake_crtc_off(struct drm_crtc *crtc)
5226 {
5227 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5228 intel_put_shared_dpll(intel_crtc);
5229 }
5230
5231
5232 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5233 {
5234 struct drm_device *dev = crtc->base.dev;
5235 struct drm_i915_private *dev_priv = dev->dev_private;
5236 struct intel_crtc_state *pipe_config = crtc->config;
5237
5238 if (!pipe_config->gmch_pfit.control)
5239 return;
5240
5241 /*
5242 * The panel fitter should only be adjusted whilst the pipe is disabled,
5243 * according to register description and PRM.
5244 */
5245 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5246 assert_pipe_disabled(dev_priv, crtc->pipe);
5247
5248 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5249 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5250
5251 /* Border color in case we don't scale up to the full screen. Black by
5252 * default, change to something else for debugging. */
5253 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5254 }
5255
5256 static enum intel_display_power_domain port_to_power_domain(enum port port)
5257 {
5258 switch (port) {
5259 case PORT_A:
5260 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5261 case PORT_B:
5262 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5263 case PORT_C:
5264 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5265 case PORT_D:
5266 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5267 default:
5268 WARN_ON_ONCE(1);
5269 return POWER_DOMAIN_PORT_OTHER;
5270 }
5271 }
5272
5273 #define for_each_power_domain(domain, mask) \
5274 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5275 if ((1 << (domain)) & (mask))
5276
5277 enum intel_display_power_domain
5278 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5279 {
5280 struct drm_device *dev = intel_encoder->base.dev;
5281 struct intel_digital_port *intel_dig_port;
5282
5283 switch (intel_encoder->type) {
5284 case INTEL_OUTPUT_UNKNOWN:
5285 /* Only DDI platforms should ever use this output type */
5286 WARN_ON_ONCE(!HAS_DDI(dev));
5287 case INTEL_OUTPUT_DISPLAYPORT:
5288 case INTEL_OUTPUT_HDMI:
5289 case INTEL_OUTPUT_EDP:
5290 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5291 return port_to_power_domain(intel_dig_port->port);
5292 case INTEL_OUTPUT_DP_MST:
5293 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5294 return port_to_power_domain(intel_dig_port->port);
5295 case INTEL_OUTPUT_ANALOG:
5296 return POWER_DOMAIN_PORT_CRT;
5297 case INTEL_OUTPUT_DSI:
5298 return POWER_DOMAIN_PORT_DSI;
5299 default:
5300 return POWER_DOMAIN_PORT_OTHER;
5301 }
5302 }
5303
5304 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5305 {
5306 struct drm_device *dev = crtc->dev;
5307 struct intel_encoder *intel_encoder;
5308 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5309 enum pipe pipe = intel_crtc->pipe;
5310 unsigned long mask;
5311 enum transcoder transcoder;
5312
5313 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5314
5315 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5316 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5317 if (intel_crtc->config->pch_pfit.enabled ||
5318 intel_crtc->config->pch_pfit.force_thru)
5319 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5320
5321 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5322 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5323
5324 return mask;
5325 }
5326
5327 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5328 {
5329 struct drm_device *dev = state->dev;
5330 struct drm_i915_private *dev_priv = dev->dev_private;
5331 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5332 struct intel_crtc *crtc;
5333
5334 /*
5335 * First get all needed power domains, then put all unneeded, to avoid
5336 * any unnecessary toggling of the power wells.
5337 */
5338 for_each_intel_crtc(dev, crtc) {
5339 enum intel_display_power_domain domain;
5340
5341 if (!crtc->base.state->enable)
5342 continue;
5343
5344 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
5345
5346 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5347 intel_display_power_get(dev_priv, domain);
5348 }
5349
5350 if (dev_priv->display.modeset_global_resources)
5351 dev_priv->display.modeset_global_resources(state);
5352
5353 for_each_intel_crtc(dev, crtc) {
5354 enum intel_display_power_domain domain;
5355
5356 for_each_power_domain(domain, crtc->enabled_power_domains)
5357 intel_display_power_put(dev_priv, domain);
5358
5359 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5360 }
5361
5362 intel_display_set_init_power(dev_priv, false);
5363 }
5364
5365 void broxton_set_cdclk(struct drm_device *dev, int frequency)
5366 {
5367 struct drm_i915_private *dev_priv = dev->dev_private;
5368 uint32_t divider;
5369 uint32_t ratio;
5370 uint32_t current_freq;
5371 int ret;
5372
5373 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5374 switch (frequency) {
5375 case 144000:
5376 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5377 ratio = BXT_DE_PLL_RATIO(60);
5378 break;
5379 case 288000:
5380 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5381 ratio = BXT_DE_PLL_RATIO(60);
5382 break;
5383 case 384000:
5384 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5385 ratio = BXT_DE_PLL_RATIO(60);
5386 break;
5387 case 576000:
5388 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5389 ratio = BXT_DE_PLL_RATIO(60);
5390 break;
5391 case 624000:
5392 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5393 ratio = BXT_DE_PLL_RATIO(65);
5394 break;
5395 case 19200:
5396 /*
5397 * Bypass frequency with DE PLL disabled. Init ratio, divider
5398 * to suppress GCC warning.
5399 */
5400 ratio = 0;
5401 divider = 0;
5402 break;
5403 default:
5404 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5405
5406 return;
5407 }
5408
5409 mutex_lock(&dev_priv->rps.hw_lock);
5410 /* Inform power controller of upcoming frequency change */
5411 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5412 0x80000000);
5413 mutex_unlock(&dev_priv->rps.hw_lock);
5414
5415 if (ret) {
5416 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5417 ret, frequency);
5418 return;
5419 }
5420
5421 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5422 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5423 current_freq = current_freq * 500 + 1000;
5424
5425 /*
5426 * DE PLL has to be disabled when
5427 * - setting to 19.2MHz (bypass, PLL isn't used)
5428 * - before setting to 624MHz (PLL needs toggling)
5429 * - before setting to any frequency from 624MHz (PLL needs toggling)
5430 */
5431 if (frequency == 19200 || frequency == 624000 ||
5432 current_freq == 624000) {
5433 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5434 /* Timeout 200us */
5435 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5436 1))
5437 DRM_ERROR("timout waiting for DE PLL unlock\n");
5438 }
5439
5440 if (frequency != 19200) {
5441 uint32_t val;
5442
5443 val = I915_READ(BXT_DE_PLL_CTL);
5444 val &= ~BXT_DE_PLL_RATIO_MASK;
5445 val |= ratio;
5446 I915_WRITE(BXT_DE_PLL_CTL, val);
5447
5448 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5449 /* Timeout 200us */
5450 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5451 DRM_ERROR("timeout waiting for DE PLL lock\n");
5452
5453 val = I915_READ(CDCLK_CTL);
5454 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5455 val |= divider;
5456 /*
5457 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5458 * enable otherwise.
5459 */
5460 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5461 if (frequency >= 500000)
5462 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5463
5464 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5465 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5466 val |= (frequency - 1000) / 500;
5467 I915_WRITE(CDCLK_CTL, val);
5468 }
5469
5470 mutex_lock(&dev_priv->rps.hw_lock);
5471 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5472 DIV_ROUND_UP(frequency, 25000));
5473 mutex_unlock(&dev_priv->rps.hw_lock);
5474
5475 if (ret) {
5476 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5477 ret, frequency);
5478 return;
5479 }
5480
5481 dev_priv->cdclk_freq = frequency;
5482 }
5483
5484 void broxton_init_cdclk(struct drm_device *dev)
5485 {
5486 struct drm_i915_private *dev_priv = dev->dev_private;
5487 uint32_t val;
5488
5489 /*
5490 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5491 * or else the reset will hang because there is no PCH to respond.
5492 * Move the handshake programming to initialization sequence.
5493 * Previously was left up to BIOS.
5494 */
5495 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5496 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5497 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5498
5499 /* Enable PG1 for cdclk */
5500 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5501
5502 /* check if cd clock is enabled */
5503 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5504 DRM_DEBUG_KMS("Display already initialized\n");
5505 return;
5506 }
5507
5508 /*
5509 * FIXME:
5510 * - The initial CDCLK needs to be read from VBT.
5511 * Need to make this change after VBT has changes for BXT.
5512 * - check if setting the max (or any) cdclk freq is really necessary
5513 * here, it belongs to modeset time
5514 */
5515 broxton_set_cdclk(dev, 624000);
5516
5517 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5518 POSTING_READ(DBUF_CTL);
5519
5520 udelay(10);
5521
5522 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5523 DRM_ERROR("DBuf power enable timeout!\n");
5524 }
5525
5526 void broxton_uninit_cdclk(struct drm_device *dev)
5527 {
5528 struct drm_i915_private *dev_priv = dev->dev_private;
5529
5530 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5531 POSTING_READ(DBUF_CTL);
5532
5533 udelay(10);
5534
5535 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5536 DRM_ERROR("DBuf power disable timeout!\n");
5537
5538 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5539 broxton_set_cdclk(dev, 19200);
5540
5541 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5542 }
5543
5544 /* returns HPLL frequency in kHz */
5545 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
5546 {
5547 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
5548
5549 /* Obtain SKU information */
5550 mutex_lock(&dev_priv->dpio_lock);
5551 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5552 CCK_FUSE_HPLL_FREQ_MASK;
5553 mutex_unlock(&dev_priv->dpio_lock);
5554
5555 return vco_freq[hpll_freq] * 1000;
5556 }
5557
5558 static void vlv_update_cdclk(struct drm_device *dev)
5559 {
5560 struct drm_i915_private *dev_priv = dev->dev_private;
5561
5562 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5563 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5564 dev_priv->cdclk_freq);
5565
5566 /*
5567 * Program the gmbus_freq based on the cdclk frequency.
5568 * BSpec erroneously claims we should aim for 4MHz, but
5569 * in fact 1MHz is the correct frequency.
5570 */
5571 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5572 }
5573
5574 /* Adjust CDclk dividers to allow high res or save power if possible */
5575 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5576 {
5577 struct drm_i915_private *dev_priv = dev->dev_private;
5578 u32 val, cmd;
5579
5580 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5581 != dev_priv->cdclk_freq);
5582
5583 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5584 cmd = 2;
5585 else if (cdclk == 266667)
5586 cmd = 1;
5587 else
5588 cmd = 0;
5589
5590 mutex_lock(&dev_priv->rps.hw_lock);
5591 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5592 val &= ~DSPFREQGUAR_MASK;
5593 val |= (cmd << DSPFREQGUAR_SHIFT);
5594 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5595 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5596 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5597 50)) {
5598 DRM_ERROR("timed out waiting for CDclk change\n");
5599 }
5600 mutex_unlock(&dev_priv->rps.hw_lock);
5601
5602 if (cdclk == 400000) {
5603 u32 divider;
5604
5605 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5606
5607 mutex_lock(&dev_priv->dpio_lock);
5608 /* adjust cdclk divider */
5609 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5610 val &= ~DISPLAY_FREQUENCY_VALUES;
5611 val |= divider;
5612 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5613
5614 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5615 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5616 50))
5617 DRM_ERROR("timed out waiting for CDclk change\n");
5618 mutex_unlock(&dev_priv->dpio_lock);
5619 }
5620
5621 mutex_lock(&dev_priv->dpio_lock);
5622 /* adjust self-refresh exit latency value */
5623 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5624 val &= ~0x7f;
5625
5626 /*
5627 * For high bandwidth configs, we set a higher latency in the bunit
5628 * so that the core display fetch happens in time to avoid underruns.
5629 */
5630 if (cdclk == 400000)
5631 val |= 4500 / 250; /* 4.5 usec */
5632 else
5633 val |= 3000 / 250; /* 3.0 usec */
5634 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5635 mutex_unlock(&dev_priv->dpio_lock);
5636
5637 vlv_update_cdclk(dev);
5638 }
5639
5640 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5641 {
5642 struct drm_i915_private *dev_priv = dev->dev_private;
5643 u32 val, cmd;
5644
5645 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5646 != dev_priv->cdclk_freq);
5647
5648 switch (cdclk) {
5649 case 333333:
5650 case 320000:
5651 case 266667:
5652 case 200000:
5653 break;
5654 default:
5655 MISSING_CASE(cdclk);
5656 return;
5657 }
5658
5659 /*
5660 * Specs are full of misinformation, but testing on actual
5661 * hardware has shown that we just need to write the desired
5662 * CCK divider into the Punit register.
5663 */
5664 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5665
5666 mutex_lock(&dev_priv->rps.hw_lock);
5667 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5668 val &= ~DSPFREQGUAR_MASK_CHV;
5669 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5670 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5671 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5672 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5673 50)) {
5674 DRM_ERROR("timed out waiting for CDclk change\n");
5675 }
5676 mutex_unlock(&dev_priv->rps.hw_lock);
5677
5678 vlv_update_cdclk(dev);
5679 }
5680
5681 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5682 int max_pixclk)
5683 {
5684 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5685 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5686
5687 /*
5688 * Really only a few cases to deal with, as only 4 CDclks are supported:
5689 * 200MHz
5690 * 267MHz
5691 * 320/333MHz (depends on HPLL freq)
5692 * 400MHz (VLV only)
5693 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5694 * of the lower bin and adjust if needed.
5695 *
5696 * We seem to get an unstable or solid color picture at 200MHz.
5697 * Not sure what's wrong. For now use 200MHz only when all pipes
5698 * are off.
5699 */
5700 if (!IS_CHERRYVIEW(dev_priv) &&
5701 max_pixclk > freq_320*limit/100)
5702 return 400000;
5703 else if (max_pixclk > 266667*limit/100)
5704 return freq_320;
5705 else if (max_pixclk > 0)
5706 return 266667;
5707 else
5708 return 200000;
5709 }
5710
5711 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5712 int max_pixclk)
5713 {
5714 /*
5715 * FIXME:
5716 * - remove the guardband, it's not needed on BXT
5717 * - set 19.2MHz bypass frequency if there are no active pipes
5718 */
5719 if (max_pixclk > 576000*9/10)
5720 return 624000;
5721 else if (max_pixclk > 384000*9/10)
5722 return 576000;
5723 else if (max_pixclk > 288000*9/10)
5724 return 384000;
5725 else if (max_pixclk > 144000*9/10)
5726 return 288000;
5727 else
5728 return 144000;
5729 }
5730
5731 /* compute the max pixel clock for new configuration */
5732 static int intel_mode_max_pixclk(struct drm_atomic_state *state)
5733 {
5734 struct drm_device *dev = state->dev;
5735 struct intel_crtc *intel_crtc;
5736 struct intel_crtc_state *crtc_state;
5737 int max_pixclk = 0;
5738
5739 for_each_intel_crtc(dev, intel_crtc) {
5740 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5741 if (IS_ERR(crtc_state))
5742 return PTR_ERR(crtc_state);
5743
5744 if (!crtc_state->base.enable)
5745 continue;
5746
5747 max_pixclk = max(max_pixclk,
5748 crtc_state->base.adjusted_mode.crtc_clock);
5749 }
5750
5751 return max_pixclk;
5752 }
5753
5754 static int valleyview_modeset_global_pipes(struct drm_atomic_state *state)
5755 {
5756 struct drm_i915_private *dev_priv = to_i915(state->dev);
5757 struct drm_crtc *crtc;
5758 struct drm_crtc_state *crtc_state;
5759 int max_pixclk = intel_mode_max_pixclk(state);
5760 int cdclk, i;
5761
5762 if (max_pixclk < 0)
5763 return max_pixclk;
5764
5765 if (IS_VALLEYVIEW(dev_priv))
5766 cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5767 else
5768 cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
5769
5770 if (cdclk == dev_priv->cdclk_freq)
5771 return 0;
5772
5773 /* add all active pipes to the state */
5774 for_each_crtc(state->dev, crtc) {
5775 if (!crtc->state->enable)
5776 continue;
5777
5778 crtc_state = drm_atomic_get_crtc_state(state, crtc);
5779 if (IS_ERR(crtc_state))
5780 return PTR_ERR(crtc_state);
5781 }
5782
5783 /* disable/enable all currently active pipes while we change cdclk */
5784 for_each_crtc_in_state(state, crtc, crtc_state, i)
5785 if (crtc_state->enable)
5786 crtc_state->mode_changed = true;
5787
5788 return 0;
5789 }
5790
5791 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5792 {
5793 unsigned int credits, default_credits;
5794
5795 if (IS_CHERRYVIEW(dev_priv))
5796 default_credits = PFI_CREDIT(12);
5797 else
5798 default_credits = PFI_CREDIT(8);
5799
5800 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5801 /* CHV suggested value is 31 or 63 */
5802 if (IS_CHERRYVIEW(dev_priv))
5803 credits = PFI_CREDIT_31;
5804 else
5805 credits = PFI_CREDIT(15);
5806 } else {
5807 credits = default_credits;
5808 }
5809
5810 /*
5811 * WA - write default credits before re-programming
5812 * FIXME: should we also set the resend bit here?
5813 */
5814 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5815 default_credits);
5816
5817 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5818 credits | PFI_CREDIT_RESEND);
5819
5820 /*
5821 * FIXME is this guaranteed to clear
5822 * immediately or should we poll for it?
5823 */
5824 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5825 }
5826
5827 static void valleyview_modeset_global_resources(struct drm_atomic_state *state)
5828 {
5829 struct drm_device *dev = state->dev;
5830 struct drm_i915_private *dev_priv = dev->dev_private;
5831 int max_pixclk = intel_mode_max_pixclk(state);
5832 int req_cdclk;
5833
5834 /* The only reason this can fail is if we fail to add the crtc_state
5835 * to the atomic state. But that can't happen since the call to
5836 * intel_mode_max_pixclk() in valleyview_modeset_global_pipes() (which
5837 * can't have failed otherwise the mode set would be aborted) added all
5838 * the states already. */
5839 if (WARN_ON(max_pixclk < 0))
5840 return;
5841
5842 req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5843
5844 if (req_cdclk != dev_priv->cdclk_freq) {
5845 /*
5846 * FIXME: We can end up here with all power domains off, yet
5847 * with a CDCLK frequency other than the minimum. To account
5848 * for this take the PIPE-A power domain, which covers the HW
5849 * blocks needed for the following programming. This can be
5850 * removed once it's guaranteed that we get here either with
5851 * the minimum CDCLK set, or the required power domains
5852 * enabled.
5853 */
5854 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5855
5856 if (IS_CHERRYVIEW(dev))
5857 cherryview_set_cdclk(dev, req_cdclk);
5858 else
5859 valleyview_set_cdclk(dev, req_cdclk);
5860
5861 vlv_program_pfi_credits(dev_priv);
5862
5863 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5864 }
5865 }
5866
5867 static void valleyview_crtc_enable(struct drm_crtc *crtc)
5868 {
5869 struct drm_device *dev = crtc->dev;
5870 struct drm_i915_private *dev_priv = to_i915(dev);
5871 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5872 struct intel_encoder *encoder;
5873 int pipe = intel_crtc->pipe;
5874 bool is_dsi;
5875
5876 WARN_ON(!crtc->state->enable);
5877
5878 if (intel_crtc->active)
5879 return;
5880
5881 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5882
5883 if (!is_dsi) {
5884 if (IS_CHERRYVIEW(dev))
5885 chv_prepare_pll(intel_crtc, intel_crtc->config);
5886 else
5887 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5888 }
5889
5890 if (intel_crtc->config->has_dp_encoder)
5891 intel_dp_set_m_n(intel_crtc, M1_N1);
5892
5893 intel_set_pipe_timings(intel_crtc);
5894
5895 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5896 struct drm_i915_private *dev_priv = dev->dev_private;
5897
5898 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5899 I915_WRITE(CHV_CANVAS(pipe), 0);
5900 }
5901
5902 i9xx_set_pipeconf(intel_crtc);
5903
5904 intel_crtc->active = true;
5905
5906 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5907
5908 for_each_encoder_on_crtc(dev, crtc, encoder)
5909 if (encoder->pre_pll_enable)
5910 encoder->pre_pll_enable(encoder);
5911
5912 if (!is_dsi) {
5913 if (IS_CHERRYVIEW(dev))
5914 chv_enable_pll(intel_crtc, intel_crtc->config);
5915 else
5916 vlv_enable_pll(intel_crtc, intel_crtc->config);
5917 }
5918
5919 for_each_encoder_on_crtc(dev, crtc, encoder)
5920 if (encoder->pre_enable)
5921 encoder->pre_enable(encoder);
5922
5923 i9xx_pfit_enable(intel_crtc);
5924
5925 intel_crtc_load_lut(crtc);
5926
5927 intel_update_watermarks(crtc);
5928 intel_enable_pipe(intel_crtc);
5929
5930 assert_vblank_disabled(crtc);
5931 drm_crtc_vblank_on(crtc);
5932
5933 for_each_encoder_on_crtc(dev, crtc, encoder)
5934 encoder->enable(encoder);
5935 }
5936
5937 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5938 {
5939 struct drm_device *dev = crtc->base.dev;
5940 struct drm_i915_private *dev_priv = dev->dev_private;
5941
5942 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5943 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5944 }
5945
5946 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5947 {
5948 struct drm_device *dev = crtc->dev;
5949 struct drm_i915_private *dev_priv = to_i915(dev);
5950 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5951 struct intel_encoder *encoder;
5952 int pipe = intel_crtc->pipe;
5953
5954 WARN_ON(!crtc->state->enable);
5955
5956 if (intel_crtc->active)
5957 return;
5958
5959 i9xx_set_pll_dividers(intel_crtc);
5960
5961 if (intel_crtc->config->has_dp_encoder)
5962 intel_dp_set_m_n(intel_crtc, M1_N1);
5963
5964 intel_set_pipe_timings(intel_crtc);
5965
5966 i9xx_set_pipeconf(intel_crtc);
5967
5968 intel_crtc->active = true;
5969
5970 if (!IS_GEN2(dev))
5971 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5972
5973 for_each_encoder_on_crtc(dev, crtc, encoder)
5974 if (encoder->pre_enable)
5975 encoder->pre_enable(encoder);
5976
5977 i9xx_enable_pll(intel_crtc);
5978
5979 i9xx_pfit_enable(intel_crtc);
5980
5981 intel_crtc_load_lut(crtc);
5982
5983 intel_update_watermarks(crtc);
5984 intel_enable_pipe(intel_crtc);
5985
5986 assert_vblank_disabled(crtc);
5987 drm_crtc_vblank_on(crtc);
5988
5989 for_each_encoder_on_crtc(dev, crtc, encoder)
5990 encoder->enable(encoder);
5991 }
5992
5993 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5994 {
5995 struct drm_device *dev = crtc->base.dev;
5996 struct drm_i915_private *dev_priv = dev->dev_private;
5997
5998 if (!crtc->config->gmch_pfit.control)
5999 return;
6000
6001 assert_pipe_disabled(dev_priv, crtc->pipe);
6002
6003 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6004 I915_READ(PFIT_CONTROL));
6005 I915_WRITE(PFIT_CONTROL, 0);
6006 }
6007
6008 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6009 {
6010 struct drm_device *dev = crtc->dev;
6011 struct drm_i915_private *dev_priv = dev->dev_private;
6012 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6013 struct intel_encoder *encoder;
6014 int pipe = intel_crtc->pipe;
6015
6016 if (!intel_crtc->active)
6017 return;
6018
6019 /*
6020 * On gen2 planes are double buffered but the pipe isn't, so we must
6021 * wait for planes to fully turn off before disabling the pipe.
6022 * We also need to wait on all gmch platforms because of the
6023 * self-refresh mode constraint explained above.
6024 */
6025 intel_wait_for_vblank(dev, pipe);
6026
6027 for_each_encoder_on_crtc(dev, crtc, encoder)
6028 encoder->disable(encoder);
6029
6030 drm_crtc_vblank_off(crtc);
6031 assert_vblank_disabled(crtc);
6032
6033 intel_disable_pipe(intel_crtc);
6034
6035 i9xx_pfit_disable(intel_crtc);
6036
6037 for_each_encoder_on_crtc(dev, crtc, encoder)
6038 if (encoder->post_disable)
6039 encoder->post_disable(encoder);
6040
6041 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6042 if (IS_CHERRYVIEW(dev))
6043 chv_disable_pll(dev_priv, pipe);
6044 else if (IS_VALLEYVIEW(dev))
6045 vlv_disable_pll(dev_priv, pipe);
6046 else
6047 i9xx_disable_pll(intel_crtc);
6048 }
6049
6050 if (!IS_GEN2(dev))
6051 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6052
6053 intel_crtc->active = false;
6054 intel_update_watermarks(crtc);
6055
6056 mutex_lock(&dev->struct_mutex);
6057 intel_fbc_update(dev);
6058 mutex_unlock(&dev->struct_mutex);
6059 }
6060
6061 static void i9xx_crtc_off(struct drm_crtc *crtc)
6062 {
6063 }
6064
6065 /* Master function to enable/disable CRTC and corresponding power wells */
6066 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
6067 {
6068 struct drm_device *dev = crtc->dev;
6069 struct drm_i915_private *dev_priv = dev->dev_private;
6070 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6071 enum intel_display_power_domain domain;
6072 unsigned long domains;
6073
6074 if (enable) {
6075 if (!intel_crtc->active) {
6076 domains = get_crtc_power_domains(crtc);
6077 for_each_power_domain(domain, domains)
6078 intel_display_power_get(dev_priv, domain);
6079 intel_crtc->enabled_power_domains = domains;
6080
6081 dev_priv->display.crtc_enable(crtc);
6082 intel_crtc_enable_planes(crtc);
6083 }
6084 } else {
6085 if (intel_crtc->active) {
6086 intel_crtc_disable_planes(crtc);
6087 dev_priv->display.crtc_disable(crtc);
6088
6089 domains = intel_crtc->enabled_power_domains;
6090 for_each_power_domain(domain, domains)
6091 intel_display_power_put(dev_priv, domain);
6092 intel_crtc->enabled_power_domains = 0;
6093 }
6094 }
6095 }
6096
6097 /**
6098 * Sets the power management mode of the pipe and plane.
6099 */
6100 void intel_crtc_update_dpms(struct drm_crtc *crtc)
6101 {
6102 struct drm_device *dev = crtc->dev;
6103 struct intel_encoder *intel_encoder;
6104 bool enable = false;
6105
6106 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6107 enable |= intel_encoder->connectors_active;
6108
6109 intel_crtc_control(crtc, enable);
6110 }
6111
6112 static void intel_crtc_disable(struct drm_crtc *crtc)
6113 {
6114 struct drm_device *dev = crtc->dev;
6115 struct drm_connector *connector;
6116 struct drm_i915_private *dev_priv = dev->dev_private;
6117
6118 /* crtc should still be enabled when we disable it. */
6119 WARN_ON(!crtc->state->enable);
6120
6121 intel_crtc_disable_planes(crtc);
6122 dev_priv->display.crtc_disable(crtc);
6123 dev_priv->display.off(crtc);
6124
6125 drm_plane_helper_disable(crtc->primary);
6126
6127 /* Update computed state. */
6128 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6129 if (!connector->encoder || !connector->encoder->crtc)
6130 continue;
6131
6132 if (connector->encoder->crtc != crtc)
6133 continue;
6134
6135 connector->dpms = DRM_MODE_DPMS_OFF;
6136 to_intel_encoder(connector->encoder)->connectors_active = false;
6137 }
6138 }
6139
6140 void intel_encoder_destroy(struct drm_encoder *encoder)
6141 {
6142 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6143
6144 drm_encoder_cleanup(encoder);
6145 kfree(intel_encoder);
6146 }
6147
6148 /* Simple dpms helper for encoders with just one connector, no cloning and only
6149 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6150 * state of the entire output pipe. */
6151 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
6152 {
6153 if (mode == DRM_MODE_DPMS_ON) {
6154 encoder->connectors_active = true;
6155
6156 intel_crtc_update_dpms(encoder->base.crtc);
6157 } else {
6158 encoder->connectors_active = false;
6159
6160 intel_crtc_update_dpms(encoder->base.crtc);
6161 }
6162 }
6163
6164 /* Cross check the actual hw state with our own modeset state tracking (and it's
6165 * internal consistency). */
6166 static void intel_connector_check_state(struct intel_connector *connector)
6167 {
6168 if (connector->get_hw_state(connector)) {
6169 struct intel_encoder *encoder = connector->encoder;
6170 struct drm_crtc *crtc;
6171 bool encoder_enabled;
6172 enum pipe pipe;
6173
6174 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6175 connector->base.base.id,
6176 connector->base.name);
6177
6178 /* there is no real hw state for MST connectors */
6179 if (connector->mst_port)
6180 return;
6181
6182 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
6183 "wrong connector dpms state\n");
6184 I915_STATE_WARN(connector->base.encoder != &encoder->base,
6185 "active connector not linked to encoder\n");
6186
6187 if (encoder) {
6188 I915_STATE_WARN(!encoder->connectors_active,
6189 "encoder->connectors_active not set\n");
6190
6191 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
6192 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6193 if (I915_STATE_WARN_ON(!encoder->base.crtc))
6194 return;
6195
6196 crtc = encoder->base.crtc;
6197
6198 I915_STATE_WARN(!crtc->state->enable,
6199 "crtc not enabled\n");
6200 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6201 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
6202 "encoder active on the wrong pipe\n");
6203 }
6204 }
6205 }
6206
6207 int intel_connector_init(struct intel_connector *connector)
6208 {
6209 struct drm_connector_state *connector_state;
6210
6211 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6212 if (!connector_state)
6213 return -ENOMEM;
6214
6215 connector->base.state = connector_state;
6216 return 0;
6217 }
6218
6219 struct intel_connector *intel_connector_alloc(void)
6220 {
6221 struct intel_connector *connector;
6222
6223 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6224 if (!connector)
6225 return NULL;
6226
6227 if (intel_connector_init(connector) < 0) {
6228 kfree(connector);
6229 return NULL;
6230 }
6231
6232 return connector;
6233 }
6234
6235 /* Even simpler default implementation, if there's really no special case to
6236 * consider. */
6237 void intel_connector_dpms(struct drm_connector *connector, int mode)
6238 {
6239 /* All the simple cases only support two dpms states. */
6240 if (mode != DRM_MODE_DPMS_ON)
6241 mode = DRM_MODE_DPMS_OFF;
6242
6243 if (mode == connector->dpms)
6244 return;
6245
6246 connector->dpms = mode;
6247
6248 /* Only need to change hw state when actually enabled */
6249 if (connector->encoder)
6250 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
6251
6252 intel_modeset_check_state(connector->dev);
6253 }
6254
6255 /* Simple connector->get_hw_state implementation for encoders that support only
6256 * one connector and no cloning and hence the encoder state determines the state
6257 * of the connector. */
6258 bool intel_connector_get_hw_state(struct intel_connector *connector)
6259 {
6260 enum pipe pipe = 0;
6261 struct intel_encoder *encoder = connector->encoder;
6262
6263 return encoder->get_hw_state(encoder, &pipe);
6264 }
6265
6266 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6267 {
6268 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6269 return crtc_state->fdi_lanes;
6270
6271 return 0;
6272 }
6273
6274 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6275 struct intel_crtc_state *pipe_config)
6276 {
6277 struct drm_atomic_state *state = pipe_config->base.state;
6278 struct intel_crtc *other_crtc;
6279 struct intel_crtc_state *other_crtc_state;
6280
6281 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6282 pipe_name(pipe), pipe_config->fdi_lanes);
6283 if (pipe_config->fdi_lanes > 4) {
6284 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6285 pipe_name(pipe), pipe_config->fdi_lanes);
6286 return -EINVAL;
6287 }
6288
6289 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6290 if (pipe_config->fdi_lanes > 2) {
6291 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6292 pipe_config->fdi_lanes);
6293 return -EINVAL;
6294 } else {
6295 return 0;
6296 }
6297 }
6298
6299 if (INTEL_INFO(dev)->num_pipes == 2)
6300 return 0;
6301
6302 /* Ivybridge 3 pipe is really complicated */
6303 switch (pipe) {
6304 case PIPE_A:
6305 return 0;
6306 case PIPE_B:
6307 if (pipe_config->fdi_lanes <= 2)
6308 return 0;
6309
6310 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6311 other_crtc_state =
6312 intel_atomic_get_crtc_state(state, other_crtc);
6313 if (IS_ERR(other_crtc_state))
6314 return PTR_ERR(other_crtc_state);
6315
6316 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6317 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6318 pipe_name(pipe), pipe_config->fdi_lanes);
6319 return -EINVAL;
6320 }
6321 return 0;
6322 case PIPE_C:
6323 if (pipe_config->fdi_lanes > 2) {
6324 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6325 pipe_name(pipe), pipe_config->fdi_lanes);
6326 return -EINVAL;
6327 }
6328
6329 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6330 other_crtc_state =
6331 intel_atomic_get_crtc_state(state, other_crtc);
6332 if (IS_ERR(other_crtc_state))
6333 return PTR_ERR(other_crtc_state);
6334
6335 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6336 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6337 return -EINVAL;
6338 }
6339 return 0;
6340 default:
6341 BUG();
6342 }
6343 }
6344
6345 #define RETRY 1
6346 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6347 struct intel_crtc_state *pipe_config)
6348 {
6349 struct drm_device *dev = intel_crtc->base.dev;
6350 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6351 int lane, link_bw, fdi_dotclock, ret;
6352 bool needs_recompute = false;
6353
6354 retry:
6355 /* FDI is a binary signal running at ~2.7GHz, encoding
6356 * each output octet as 10 bits. The actual frequency
6357 * is stored as a divider into a 100MHz clock, and the
6358 * mode pixel clock is stored in units of 1KHz.
6359 * Hence the bw of each lane in terms of the mode signal
6360 * is:
6361 */
6362 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6363
6364 fdi_dotclock = adjusted_mode->crtc_clock;
6365
6366 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6367 pipe_config->pipe_bpp);
6368
6369 pipe_config->fdi_lanes = lane;
6370
6371 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6372 link_bw, &pipe_config->fdi_m_n);
6373
6374 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6375 intel_crtc->pipe, pipe_config);
6376 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6377 pipe_config->pipe_bpp -= 2*3;
6378 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6379 pipe_config->pipe_bpp);
6380 needs_recompute = true;
6381 pipe_config->bw_constrained = true;
6382
6383 goto retry;
6384 }
6385
6386 if (needs_recompute)
6387 return RETRY;
6388
6389 return ret;
6390 }
6391
6392 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6393 struct intel_crtc_state *pipe_config)
6394 {
6395 pipe_config->ips_enabled = i915.enable_ips &&
6396 hsw_crtc_supports_ips(crtc) &&
6397 pipe_config->pipe_bpp <= 24;
6398 }
6399
6400 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6401 struct intel_crtc_state *pipe_config)
6402 {
6403 struct drm_device *dev = crtc->base.dev;
6404 struct drm_i915_private *dev_priv = dev->dev_private;
6405 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6406 int ret;
6407
6408 /* FIXME should check pixel clock limits on all platforms */
6409 if (INTEL_INFO(dev)->gen < 4) {
6410 int clock_limit =
6411 dev_priv->display.get_display_clock_speed(dev);
6412
6413 /*
6414 * Enable pixel doubling when the dot clock
6415 * is > 90% of the (display) core speed.
6416 *
6417 * GDG double wide on either pipe,
6418 * otherwise pipe A only.
6419 */
6420 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6421 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6422 clock_limit *= 2;
6423 pipe_config->double_wide = true;
6424 }
6425
6426 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6427 return -EINVAL;
6428 }
6429
6430 /*
6431 * Pipe horizontal size must be even in:
6432 * - DVO ganged mode
6433 * - LVDS dual channel mode
6434 * - Double wide pipe
6435 */
6436 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6437 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6438 pipe_config->pipe_src_w &= ~1;
6439
6440 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6441 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6442 */
6443 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6444 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
6445 return -EINVAL;
6446
6447 if (HAS_IPS(dev))
6448 hsw_compute_ips_config(crtc, pipe_config);
6449
6450 if (pipe_config->has_pch_encoder)
6451 return ironlake_fdi_compute_config(crtc, pipe_config);
6452
6453 /* FIXME: remove below call once atomic mode set is place and all crtc
6454 * related checks called from atomic_crtc_check function */
6455 ret = 0;
6456 DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n",
6457 crtc, pipe_config->base.state);
6458 ret = intel_atomic_setup_scalers(dev, crtc, pipe_config);
6459
6460 return ret;
6461 }
6462
6463 static int skylake_get_display_clock_speed(struct drm_device *dev)
6464 {
6465 struct drm_i915_private *dev_priv = to_i915(dev);
6466 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6467 uint32_t cdctl = I915_READ(CDCLK_CTL);
6468 uint32_t linkrate;
6469
6470 if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
6471 WARN(1, "LCPLL1 not enabled\n");
6472 return 24000; /* 24MHz is the cd freq with NSSC ref */
6473 }
6474
6475 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6476 return 540000;
6477
6478 linkrate = (I915_READ(DPLL_CTRL1) &
6479 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6480
6481 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6482 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6483 /* vco 8640 */
6484 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6485 case CDCLK_FREQ_450_432:
6486 return 432000;
6487 case CDCLK_FREQ_337_308:
6488 return 308570;
6489 case CDCLK_FREQ_675_617:
6490 return 617140;
6491 default:
6492 WARN(1, "Unknown cd freq selection\n");
6493 }
6494 } else {
6495 /* vco 8100 */
6496 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6497 case CDCLK_FREQ_450_432:
6498 return 450000;
6499 case CDCLK_FREQ_337_308:
6500 return 337500;
6501 case CDCLK_FREQ_675_617:
6502 return 675000;
6503 default:
6504 WARN(1, "Unknown cd freq selection\n");
6505 }
6506 }
6507
6508 /* error case, do as if DPLL0 isn't enabled */
6509 return 24000;
6510 }
6511
6512 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6513 {
6514 struct drm_i915_private *dev_priv = dev->dev_private;
6515 uint32_t lcpll = I915_READ(LCPLL_CTL);
6516 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6517
6518 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6519 return 800000;
6520 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6521 return 450000;
6522 else if (freq == LCPLL_CLK_FREQ_450)
6523 return 450000;
6524 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6525 return 540000;
6526 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6527 return 337500;
6528 else
6529 return 675000;
6530 }
6531
6532 static int haswell_get_display_clock_speed(struct drm_device *dev)
6533 {
6534 struct drm_i915_private *dev_priv = dev->dev_private;
6535 uint32_t lcpll = I915_READ(LCPLL_CTL);
6536 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6537
6538 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6539 return 800000;
6540 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6541 return 450000;
6542 else if (freq == LCPLL_CLK_FREQ_450)
6543 return 450000;
6544 else if (IS_HSW_ULT(dev))
6545 return 337500;
6546 else
6547 return 540000;
6548 }
6549
6550 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6551 {
6552 struct drm_i915_private *dev_priv = dev->dev_private;
6553 u32 val;
6554 int divider;
6555
6556 if (dev_priv->hpll_freq == 0)
6557 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6558
6559 mutex_lock(&dev_priv->dpio_lock);
6560 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6561 mutex_unlock(&dev_priv->dpio_lock);
6562
6563 divider = val & DISPLAY_FREQUENCY_VALUES;
6564
6565 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6566 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6567 "cdclk change in progress\n");
6568
6569 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
6570 }
6571
6572 static int ilk_get_display_clock_speed(struct drm_device *dev)
6573 {
6574 return 450000;
6575 }
6576
6577 static int i945_get_display_clock_speed(struct drm_device *dev)
6578 {
6579 return 400000;
6580 }
6581
6582 static int i915_get_display_clock_speed(struct drm_device *dev)
6583 {
6584 return 333333;
6585 }
6586
6587 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6588 {
6589 return 200000;
6590 }
6591
6592 static int pnv_get_display_clock_speed(struct drm_device *dev)
6593 {
6594 u16 gcfgc = 0;
6595
6596 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6597
6598 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6599 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6600 return 266667;
6601 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6602 return 333333;
6603 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6604 return 444444;
6605 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6606 return 200000;
6607 default:
6608 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6609 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6610 return 133333;
6611 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6612 return 166667;
6613 }
6614 }
6615
6616 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6617 {
6618 u16 gcfgc = 0;
6619
6620 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6621
6622 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6623 return 133333;
6624 else {
6625 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6626 case GC_DISPLAY_CLOCK_333_MHZ:
6627 return 333333;
6628 default:
6629 case GC_DISPLAY_CLOCK_190_200_MHZ:
6630 return 190000;
6631 }
6632 }
6633 }
6634
6635 static int i865_get_display_clock_speed(struct drm_device *dev)
6636 {
6637 return 266667;
6638 }
6639
6640 static int i855_get_display_clock_speed(struct drm_device *dev)
6641 {
6642 u16 hpllcc = 0;
6643 /* Assume that the hardware is in the high speed state. This
6644 * should be the default.
6645 */
6646 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6647 case GC_CLOCK_133_200:
6648 case GC_CLOCK_100_200:
6649 return 200000;
6650 case GC_CLOCK_166_250:
6651 return 250000;
6652 case GC_CLOCK_100_133:
6653 return 133333;
6654 }
6655
6656 /* Shouldn't happen */
6657 return 0;
6658 }
6659
6660 static int i830_get_display_clock_speed(struct drm_device *dev)
6661 {
6662 return 133333;
6663 }
6664
6665 static void
6666 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6667 {
6668 while (*num > DATA_LINK_M_N_MASK ||
6669 *den > DATA_LINK_M_N_MASK) {
6670 *num >>= 1;
6671 *den >>= 1;
6672 }
6673 }
6674
6675 static void compute_m_n(unsigned int m, unsigned int n,
6676 uint32_t *ret_m, uint32_t *ret_n)
6677 {
6678 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6679 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6680 intel_reduce_m_n_ratio(ret_m, ret_n);
6681 }
6682
6683 void
6684 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6685 int pixel_clock, int link_clock,
6686 struct intel_link_m_n *m_n)
6687 {
6688 m_n->tu = 64;
6689
6690 compute_m_n(bits_per_pixel * pixel_clock,
6691 link_clock * nlanes * 8,
6692 &m_n->gmch_m, &m_n->gmch_n);
6693
6694 compute_m_n(pixel_clock, link_clock,
6695 &m_n->link_m, &m_n->link_n);
6696 }
6697
6698 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6699 {
6700 if (i915.panel_use_ssc >= 0)
6701 return i915.panel_use_ssc != 0;
6702 return dev_priv->vbt.lvds_use_ssc
6703 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6704 }
6705
6706 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
6707 int num_connectors)
6708 {
6709 struct drm_device *dev = crtc_state->base.crtc->dev;
6710 struct drm_i915_private *dev_priv = dev->dev_private;
6711 int refclk;
6712
6713 WARN_ON(!crtc_state->base.state);
6714
6715 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
6716 refclk = 100000;
6717 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6718 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6719 refclk = dev_priv->vbt.lvds_ssc_freq;
6720 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
6721 } else if (!IS_GEN2(dev)) {
6722 refclk = 96000;
6723 } else {
6724 refclk = 48000;
6725 }
6726
6727 return refclk;
6728 }
6729
6730 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6731 {
6732 return (1 << dpll->n) << 16 | dpll->m2;
6733 }
6734
6735 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6736 {
6737 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6738 }
6739
6740 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6741 struct intel_crtc_state *crtc_state,
6742 intel_clock_t *reduced_clock)
6743 {
6744 struct drm_device *dev = crtc->base.dev;
6745 u32 fp, fp2 = 0;
6746
6747 if (IS_PINEVIEW(dev)) {
6748 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6749 if (reduced_clock)
6750 fp2 = pnv_dpll_compute_fp(reduced_clock);
6751 } else {
6752 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6753 if (reduced_clock)
6754 fp2 = i9xx_dpll_compute_fp(reduced_clock);
6755 }
6756
6757 crtc_state->dpll_hw_state.fp0 = fp;
6758
6759 crtc->lowfreq_avail = false;
6760 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6761 reduced_clock) {
6762 crtc_state->dpll_hw_state.fp1 = fp2;
6763 crtc->lowfreq_avail = true;
6764 } else {
6765 crtc_state->dpll_hw_state.fp1 = fp;
6766 }
6767 }
6768
6769 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6770 pipe)
6771 {
6772 u32 reg_val;
6773
6774 /*
6775 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6776 * and set it to a reasonable value instead.
6777 */
6778 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6779 reg_val &= 0xffffff00;
6780 reg_val |= 0x00000030;
6781 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6782
6783 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6784 reg_val &= 0x8cffffff;
6785 reg_val = 0x8c000000;
6786 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6787
6788 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6789 reg_val &= 0xffffff00;
6790 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6791
6792 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6793 reg_val &= 0x00ffffff;
6794 reg_val |= 0xb0000000;
6795 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6796 }
6797
6798 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6799 struct intel_link_m_n *m_n)
6800 {
6801 struct drm_device *dev = crtc->base.dev;
6802 struct drm_i915_private *dev_priv = dev->dev_private;
6803 int pipe = crtc->pipe;
6804
6805 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6806 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6807 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6808 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6809 }
6810
6811 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6812 struct intel_link_m_n *m_n,
6813 struct intel_link_m_n *m2_n2)
6814 {
6815 struct drm_device *dev = crtc->base.dev;
6816 struct drm_i915_private *dev_priv = dev->dev_private;
6817 int pipe = crtc->pipe;
6818 enum transcoder transcoder = crtc->config->cpu_transcoder;
6819
6820 if (INTEL_INFO(dev)->gen >= 5) {
6821 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6822 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6823 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6824 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6825 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6826 * for gen < 8) and if DRRS is supported (to make sure the
6827 * registers are not unnecessarily accessed).
6828 */
6829 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6830 crtc->config->has_drrs) {
6831 I915_WRITE(PIPE_DATA_M2(transcoder),
6832 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6833 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6834 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6835 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6836 }
6837 } else {
6838 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6839 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6840 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6841 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6842 }
6843 }
6844
6845 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6846 {
6847 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6848
6849 if (m_n == M1_N1) {
6850 dp_m_n = &crtc->config->dp_m_n;
6851 dp_m2_n2 = &crtc->config->dp_m2_n2;
6852 } else if (m_n == M2_N2) {
6853
6854 /*
6855 * M2_N2 registers are not supported. Hence m2_n2 divider value
6856 * needs to be programmed into M1_N1.
6857 */
6858 dp_m_n = &crtc->config->dp_m2_n2;
6859 } else {
6860 DRM_ERROR("Unsupported divider value\n");
6861 return;
6862 }
6863
6864 if (crtc->config->has_pch_encoder)
6865 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6866 else
6867 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6868 }
6869
6870 static void vlv_update_pll(struct intel_crtc *crtc,
6871 struct intel_crtc_state *pipe_config)
6872 {
6873 u32 dpll, dpll_md;
6874
6875 /*
6876 * Enable DPIO clock input. We should never disable the reference
6877 * clock for pipe B, since VGA hotplug / manual detection depends
6878 * on it.
6879 */
6880 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
6881 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
6882 /* We should never disable this, set it here for state tracking */
6883 if (crtc->pipe == PIPE_B)
6884 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6885 dpll |= DPLL_VCO_ENABLE;
6886 pipe_config->dpll_hw_state.dpll = dpll;
6887
6888 dpll_md = (pipe_config->pixel_multiplier - 1)
6889 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6890 pipe_config->dpll_hw_state.dpll_md = dpll_md;
6891 }
6892
6893 static void vlv_prepare_pll(struct intel_crtc *crtc,
6894 const struct intel_crtc_state *pipe_config)
6895 {
6896 struct drm_device *dev = crtc->base.dev;
6897 struct drm_i915_private *dev_priv = dev->dev_private;
6898 int pipe = crtc->pipe;
6899 u32 mdiv;
6900 u32 bestn, bestm1, bestm2, bestp1, bestp2;
6901 u32 coreclk, reg_val;
6902
6903 mutex_lock(&dev_priv->dpio_lock);
6904
6905 bestn = pipe_config->dpll.n;
6906 bestm1 = pipe_config->dpll.m1;
6907 bestm2 = pipe_config->dpll.m2;
6908 bestp1 = pipe_config->dpll.p1;
6909 bestp2 = pipe_config->dpll.p2;
6910
6911 /* See eDP HDMI DPIO driver vbios notes doc */
6912
6913 /* PLL B needs special handling */
6914 if (pipe == PIPE_B)
6915 vlv_pllb_recal_opamp(dev_priv, pipe);
6916
6917 /* Set up Tx target for periodic Rcomp update */
6918 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6919
6920 /* Disable target IRef on PLL */
6921 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6922 reg_val &= 0x00ffffff;
6923 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6924
6925 /* Disable fast lock */
6926 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6927
6928 /* Set idtafcrecal before PLL is enabled */
6929 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6930 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6931 mdiv |= ((bestn << DPIO_N_SHIFT));
6932 mdiv |= (1 << DPIO_K_SHIFT);
6933
6934 /*
6935 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6936 * but we don't support that).
6937 * Note: don't use the DAC post divider as it seems unstable.
6938 */
6939 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6940 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6941
6942 mdiv |= DPIO_ENABLE_CALIBRATION;
6943 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6944
6945 /* Set HBR and RBR LPF coefficients */
6946 if (pipe_config->port_clock == 162000 ||
6947 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
6948 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
6949 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6950 0x009f0003);
6951 else
6952 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6953 0x00d0000f);
6954
6955 if (pipe_config->has_dp_encoder) {
6956 /* Use SSC source */
6957 if (pipe == PIPE_A)
6958 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6959 0x0df40000);
6960 else
6961 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6962 0x0df70000);
6963 } else { /* HDMI or VGA */
6964 /* Use bend source */
6965 if (pipe == PIPE_A)
6966 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6967 0x0df70000);
6968 else
6969 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6970 0x0df40000);
6971 }
6972
6973 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6974 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6975 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6976 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
6977 coreclk |= 0x01000000;
6978 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6979
6980 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6981 mutex_unlock(&dev_priv->dpio_lock);
6982 }
6983
6984 static void chv_update_pll(struct intel_crtc *crtc,
6985 struct intel_crtc_state *pipe_config)
6986 {
6987 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
6988 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6989 DPLL_VCO_ENABLE;
6990 if (crtc->pipe != PIPE_A)
6991 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6992
6993 pipe_config->dpll_hw_state.dpll_md =
6994 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6995 }
6996
6997 static void chv_prepare_pll(struct intel_crtc *crtc,
6998 const struct intel_crtc_state *pipe_config)
6999 {
7000 struct drm_device *dev = crtc->base.dev;
7001 struct drm_i915_private *dev_priv = dev->dev_private;
7002 int pipe = crtc->pipe;
7003 int dpll_reg = DPLL(crtc->pipe);
7004 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7005 u32 loopfilter, tribuf_calcntr;
7006 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7007 u32 dpio_val;
7008 int vco;
7009
7010 bestn = pipe_config->dpll.n;
7011 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7012 bestm1 = pipe_config->dpll.m1;
7013 bestm2 = pipe_config->dpll.m2 >> 22;
7014 bestp1 = pipe_config->dpll.p1;
7015 bestp2 = pipe_config->dpll.p2;
7016 vco = pipe_config->dpll.vco;
7017 dpio_val = 0;
7018 loopfilter = 0;
7019
7020 /*
7021 * Enable Refclk and SSC
7022 */
7023 I915_WRITE(dpll_reg,
7024 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7025
7026 mutex_lock(&dev_priv->dpio_lock);
7027
7028 /* p1 and p2 divider */
7029 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7030 5 << DPIO_CHV_S1_DIV_SHIFT |
7031 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7032 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7033 1 << DPIO_CHV_K_DIV_SHIFT);
7034
7035 /* Feedback post-divider - m2 */
7036 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7037
7038 /* Feedback refclk divider - n and m1 */
7039 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7040 DPIO_CHV_M1_DIV_BY_2 |
7041 1 << DPIO_CHV_N_DIV_SHIFT);
7042
7043 /* M2 fraction division */
7044 if (bestm2_frac)
7045 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7046
7047 /* M2 fraction division enable */
7048 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7049 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7050 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7051 if (bestm2_frac)
7052 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7053 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7054
7055 /* Program digital lock detect threshold */
7056 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7057 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7058 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7059 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7060 if (!bestm2_frac)
7061 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7062 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7063
7064 /* Loop filter */
7065 if (vco == 5400000) {
7066 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7067 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7068 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7069 tribuf_calcntr = 0x9;
7070 } else if (vco <= 6200000) {
7071 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7072 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7073 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7074 tribuf_calcntr = 0x9;
7075 } else if (vco <= 6480000) {
7076 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7077 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7078 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7079 tribuf_calcntr = 0x8;
7080 } else {
7081 /* Not supported. Apply the same limits as in the max case */
7082 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7083 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7084 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7085 tribuf_calcntr = 0;
7086 }
7087 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7088
7089 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7090 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7091 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7092 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7093
7094 /* AFC Recal */
7095 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7096 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7097 DPIO_AFC_RECAL);
7098
7099 mutex_unlock(&dev_priv->dpio_lock);
7100 }
7101
7102 /**
7103 * vlv_force_pll_on - forcibly enable just the PLL
7104 * @dev_priv: i915 private structure
7105 * @pipe: pipe PLL to enable
7106 * @dpll: PLL configuration
7107 *
7108 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7109 * in cases where we need the PLL enabled even when @pipe is not going to
7110 * be enabled.
7111 */
7112 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7113 const struct dpll *dpll)
7114 {
7115 struct intel_crtc *crtc =
7116 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7117 struct intel_crtc_state pipe_config = {
7118 .base.crtc = &crtc->base,
7119 .pixel_multiplier = 1,
7120 .dpll = *dpll,
7121 };
7122
7123 if (IS_CHERRYVIEW(dev)) {
7124 chv_update_pll(crtc, &pipe_config);
7125 chv_prepare_pll(crtc, &pipe_config);
7126 chv_enable_pll(crtc, &pipe_config);
7127 } else {
7128 vlv_update_pll(crtc, &pipe_config);
7129 vlv_prepare_pll(crtc, &pipe_config);
7130 vlv_enable_pll(crtc, &pipe_config);
7131 }
7132 }
7133
7134 /**
7135 * vlv_force_pll_off - forcibly disable just the PLL
7136 * @dev_priv: i915 private structure
7137 * @pipe: pipe PLL to disable
7138 *
7139 * Disable the PLL for @pipe. To be used in cases where we need
7140 * the PLL enabled even when @pipe is not going to be enabled.
7141 */
7142 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7143 {
7144 if (IS_CHERRYVIEW(dev))
7145 chv_disable_pll(to_i915(dev), pipe);
7146 else
7147 vlv_disable_pll(to_i915(dev), pipe);
7148 }
7149
7150 static void i9xx_update_pll(struct intel_crtc *crtc,
7151 struct intel_crtc_state *crtc_state,
7152 intel_clock_t *reduced_clock,
7153 int num_connectors)
7154 {
7155 struct drm_device *dev = crtc->base.dev;
7156 struct drm_i915_private *dev_priv = dev->dev_private;
7157 u32 dpll;
7158 bool is_sdvo;
7159 struct dpll *clock = &crtc_state->dpll;
7160
7161 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7162
7163 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7164 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7165
7166 dpll = DPLL_VGA_MODE_DIS;
7167
7168 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7169 dpll |= DPLLB_MODE_LVDS;
7170 else
7171 dpll |= DPLLB_MODE_DAC_SERIAL;
7172
7173 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7174 dpll |= (crtc_state->pixel_multiplier - 1)
7175 << SDVO_MULTIPLIER_SHIFT_HIRES;
7176 }
7177
7178 if (is_sdvo)
7179 dpll |= DPLL_SDVO_HIGH_SPEED;
7180
7181 if (crtc_state->has_dp_encoder)
7182 dpll |= DPLL_SDVO_HIGH_SPEED;
7183
7184 /* compute bitmask from p1 value */
7185 if (IS_PINEVIEW(dev))
7186 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7187 else {
7188 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7189 if (IS_G4X(dev) && reduced_clock)
7190 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7191 }
7192 switch (clock->p2) {
7193 case 5:
7194 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7195 break;
7196 case 7:
7197 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7198 break;
7199 case 10:
7200 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7201 break;
7202 case 14:
7203 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7204 break;
7205 }
7206 if (INTEL_INFO(dev)->gen >= 4)
7207 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7208
7209 if (crtc_state->sdvo_tv_clock)
7210 dpll |= PLL_REF_INPUT_TVCLKINBC;
7211 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7212 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7213 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7214 else
7215 dpll |= PLL_REF_INPUT_DREFCLK;
7216
7217 dpll |= DPLL_VCO_ENABLE;
7218 crtc_state->dpll_hw_state.dpll = dpll;
7219
7220 if (INTEL_INFO(dev)->gen >= 4) {
7221 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7222 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7223 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7224 }
7225 }
7226
7227 static void i8xx_update_pll(struct intel_crtc *crtc,
7228 struct intel_crtc_state *crtc_state,
7229 intel_clock_t *reduced_clock,
7230 int num_connectors)
7231 {
7232 struct drm_device *dev = crtc->base.dev;
7233 struct drm_i915_private *dev_priv = dev->dev_private;
7234 u32 dpll;
7235 struct dpll *clock = &crtc_state->dpll;
7236
7237 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7238
7239 dpll = DPLL_VGA_MODE_DIS;
7240
7241 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7242 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7243 } else {
7244 if (clock->p1 == 2)
7245 dpll |= PLL_P1_DIVIDE_BY_TWO;
7246 else
7247 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7248 if (clock->p2 == 4)
7249 dpll |= PLL_P2_DIVIDE_BY_4;
7250 }
7251
7252 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7253 dpll |= DPLL_DVO_2X_MODE;
7254
7255 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7256 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7257 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7258 else
7259 dpll |= PLL_REF_INPUT_DREFCLK;
7260
7261 dpll |= DPLL_VCO_ENABLE;
7262 crtc_state->dpll_hw_state.dpll = dpll;
7263 }
7264
7265 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7266 {
7267 struct drm_device *dev = intel_crtc->base.dev;
7268 struct drm_i915_private *dev_priv = dev->dev_private;
7269 enum pipe pipe = intel_crtc->pipe;
7270 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7271 struct drm_display_mode *adjusted_mode =
7272 &intel_crtc->config->base.adjusted_mode;
7273 uint32_t crtc_vtotal, crtc_vblank_end;
7274 int vsyncshift = 0;
7275
7276 /* We need to be careful not to changed the adjusted mode, for otherwise
7277 * the hw state checker will get angry at the mismatch. */
7278 crtc_vtotal = adjusted_mode->crtc_vtotal;
7279 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7280
7281 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7282 /* the chip adds 2 halflines automatically */
7283 crtc_vtotal -= 1;
7284 crtc_vblank_end -= 1;
7285
7286 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7287 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7288 else
7289 vsyncshift = adjusted_mode->crtc_hsync_start -
7290 adjusted_mode->crtc_htotal / 2;
7291 if (vsyncshift < 0)
7292 vsyncshift += adjusted_mode->crtc_htotal;
7293 }
7294
7295 if (INTEL_INFO(dev)->gen > 3)
7296 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7297
7298 I915_WRITE(HTOTAL(cpu_transcoder),
7299 (adjusted_mode->crtc_hdisplay - 1) |
7300 ((adjusted_mode->crtc_htotal - 1) << 16));
7301 I915_WRITE(HBLANK(cpu_transcoder),
7302 (adjusted_mode->crtc_hblank_start - 1) |
7303 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7304 I915_WRITE(HSYNC(cpu_transcoder),
7305 (adjusted_mode->crtc_hsync_start - 1) |
7306 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7307
7308 I915_WRITE(VTOTAL(cpu_transcoder),
7309 (adjusted_mode->crtc_vdisplay - 1) |
7310 ((crtc_vtotal - 1) << 16));
7311 I915_WRITE(VBLANK(cpu_transcoder),
7312 (adjusted_mode->crtc_vblank_start - 1) |
7313 ((crtc_vblank_end - 1) << 16));
7314 I915_WRITE(VSYNC(cpu_transcoder),
7315 (adjusted_mode->crtc_vsync_start - 1) |
7316 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7317
7318 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7319 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7320 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7321 * bits. */
7322 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7323 (pipe == PIPE_B || pipe == PIPE_C))
7324 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7325
7326 /* pipesrc controls the size that is scaled from, which should
7327 * always be the user's requested size.
7328 */
7329 I915_WRITE(PIPESRC(pipe),
7330 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7331 (intel_crtc->config->pipe_src_h - 1));
7332 }
7333
7334 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7335 struct intel_crtc_state *pipe_config)
7336 {
7337 struct drm_device *dev = crtc->base.dev;
7338 struct drm_i915_private *dev_priv = dev->dev_private;
7339 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7340 uint32_t tmp;
7341
7342 tmp = I915_READ(HTOTAL(cpu_transcoder));
7343 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7344 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7345 tmp = I915_READ(HBLANK(cpu_transcoder));
7346 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7347 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7348 tmp = I915_READ(HSYNC(cpu_transcoder));
7349 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7350 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7351
7352 tmp = I915_READ(VTOTAL(cpu_transcoder));
7353 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7354 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7355 tmp = I915_READ(VBLANK(cpu_transcoder));
7356 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7357 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7358 tmp = I915_READ(VSYNC(cpu_transcoder));
7359 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7360 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7361
7362 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7363 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7364 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7365 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7366 }
7367
7368 tmp = I915_READ(PIPESRC(crtc->pipe));
7369 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7370 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7371
7372 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7373 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7374 }
7375
7376 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7377 struct intel_crtc_state *pipe_config)
7378 {
7379 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7380 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7381 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7382 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7383
7384 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7385 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7386 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7387 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7388
7389 mode->flags = pipe_config->base.adjusted_mode.flags;
7390
7391 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7392 mode->flags |= pipe_config->base.adjusted_mode.flags;
7393 }
7394
7395 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7396 {
7397 struct drm_device *dev = intel_crtc->base.dev;
7398 struct drm_i915_private *dev_priv = dev->dev_private;
7399 uint32_t pipeconf;
7400
7401 pipeconf = 0;
7402
7403 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7404 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7405 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7406
7407 if (intel_crtc->config->double_wide)
7408 pipeconf |= PIPECONF_DOUBLE_WIDE;
7409
7410 /* only g4x and later have fancy bpc/dither controls */
7411 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7412 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7413 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7414 pipeconf |= PIPECONF_DITHER_EN |
7415 PIPECONF_DITHER_TYPE_SP;
7416
7417 switch (intel_crtc->config->pipe_bpp) {
7418 case 18:
7419 pipeconf |= PIPECONF_6BPC;
7420 break;
7421 case 24:
7422 pipeconf |= PIPECONF_8BPC;
7423 break;
7424 case 30:
7425 pipeconf |= PIPECONF_10BPC;
7426 break;
7427 default:
7428 /* Case prevented by intel_choose_pipe_bpp_dither. */
7429 BUG();
7430 }
7431 }
7432
7433 if (HAS_PIPE_CXSR(dev)) {
7434 if (intel_crtc->lowfreq_avail) {
7435 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7436 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7437 } else {
7438 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7439 }
7440 }
7441
7442 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7443 if (INTEL_INFO(dev)->gen < 4 ||
7444 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7445 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7446 else
7447 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7448 } else
7449 pipeconf |= PIPECONF_PROGRESSIVE;
7450
7451 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7452 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7453
7454 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7455 POSTING_READ(PIPECONF(intel_crtc->pipe));
7456 }
7457
7458 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7459 struct intel_crtc_state *crtc_state)
7460 {
7461 struct drm_device *dev = crtc->base.dev;
7462 struct drm_i915_private *dev_priv = dev->dev_private;
7463 int refclk, num_connectors = 0;
7464 intel_clock_t clock, reduced_clock;
7465 bool ok, has_reduced_clock = false;
7466 bool is_lvds = false, is_dsi = false;
7467 struct intel_encoder *encoder;
7468 const intel_limit_t *limit;
7469 struct drm_atomic_state *state = crtc_state->base.state;
7470 struct drm_connector *connector;
7471 struct drm_connector_state *connector_state;
7472 int i;
7473
7474 for_each_connector_in_state(state, connector, connector_state, i) {
7475 if (connector_state->crtc != &crtc->base)
7476 continue;
7477
7478 encoder = to_intel_encoder(connector_state->best_encoder);
7479
7480 switch (encoder->type) {
7481 case INTEL_OUTPUT_LVDS:
7482 is_lvds = true;
7483 break;
7484 case INTEL_OUTPUT_DSI:
7485 is_dsi = true;
7486 break;
7487 default:
7488 break;
7489 }
7490
7491 num_connectors++;
7492 }
7493
7494 if (is_dsi)
7495 return 0;
7496
7497 if (!crtc_state->clock_set) {
7498 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7499
7500 /*
7501 * Returns a set of divisors for the desired target clock with
7502 * the given refclk, or FALSE. The returned values represent
7503 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7504 * 2) / p1 / p2.
7505 */
7506 limit = intel_limit(crtc_state, refclk);
7507 ok = dev_priv->display.find_dpll(limit, crtc_state,
7508 crtc_state->port_clock,
7509 refclk, NULL, &clock);
7510 if (!ok) {
7511 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7512 return -EINVAL;
7513 }
7514
7515 if (is_lvds && dev_priv->lvds_downclock_avail) {
7516 /*
7517 * Ensure we match the reduced clock's P to the target
7518 * clock. If the clocks don't match, we can't switch
7519 * the display clock by using the FP0/FP1. In such case
7520 * we will disable the LVDS downclock feature.
7521 */
7522 has_reduced_clock =
7523 dev_priv->display.find_dpll(limit, crtc_state,
7524 dev_priv->lvds_downclock,
7525 refclk, &clock,
7526 &reduced_clock);
7527 }
7528 /* Compat-code for transition, will disappear. */
7529 crtc_state->dpll.n = clock.n;
7530 crtc_state->dpll.m1 = clock.m1;
7531 crtc_state->dpll.m2 = clock.m2;
7532 crtc_state->dpll.p1 = clock.p1;
7533 crtc_state->dpll.p2 = clock.p2;
7534 }
7535
7536 if (IS_GEN2(dev)) {
7537 i8xx_update_pll(crtc, crtc_state,
7538 has_reduced_clock ? &reduced_clock : NULL,
7539 num_connectors);
7540 } else if (IS_CHERRYVIEW(dev)) {
7541 chv_update_pll(crtc, crtc_state);
7542 } else if (IS_VALLEYVIEW(dev)) {
7543 vlv_update_pll(crtc, crtc_state);
7544 } else {
7545 i9xx_update_pll(crtc, crtc_state,
7546 has_reduced_clock ? &reduced_clock : NULL,
7547 num_connectors);
7548 }
7549
7550 return 0;
7551 }
7552
7553 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7554 struct intel_crtc_state *pipe_config)
7555 {
7556 struct drm_device *dev = crtc->base.dev;
7557 struct drm_i915_private *dev_priv = dev->dev_private;
7558 uint32_t tmp;
7559
7560 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7561 return;
7562
7563 tmp = I915_READ(PFIT_CONTROL);
7564 if (!(tmp & PFIT_ENABLE))
7565 return;
7566
7567 /* Check whether the pfit is attached to our pipe. */
7568 if (INTEL_INFO(dev)->gen < 4) {
7569 if (crtc->pipe != PIPE_B)
7570 return;
7571 } else {
7572 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7573 return;
7574 }
7575
7576 pipe_config->gmch_pfit.control = tmp;
7577 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7578 if (INTEL_INFO(dev)->gen < 5)
7579 pipe_config->gmch_pfit.lvds_border_bits =
7580 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7581 }
7582
7583 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7584 struct intel_crtc_state *pipe_config)
7585 {
7586 struct drm_device *dev = crtc->base.dev;
7587 struct drm_i915_private *dev_priv = dev->dev_private;
7588 int pipe = pipe_config->cpu_transcoder;
7589 intel_clock_t clock;
7590 u32 mdiv;
7591 int refclk = 100000;
7592
7593 /* In case of MIPI DPLL will not even be used */
7594 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7595 return;
7596
7597 mutex_lock(&dev_priv->dpio_lock);
7598 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7599 mutex_unlock(&dev_priv->dpio_lock);
7600
7601 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7602 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7603 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7604 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7605 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7606
7607 vlv_clock(refclk, &clock);
7608
7609 /* clock.dot is the fast clock */
7610 pipe_config->port_clock = clock.dot / 5;
7611 }
7612
7613 static void
7614 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7615 struct intel_initial_plane_config *plane_config)
7616 {
7617 struct drm_device *dev = crtc->base.dev;
7618 struct drm_i915_private *dev_priv = dev->dev_private;
7619 u32 val, base, offset;
7620 int pipe = crtc->pipe, plane = crtc->plane;
7621 int fourcc, pixel_format;
7622 unsigned int aligned_height;
7623 struct drm_framebuffer *fb;
7624 struct intel_framebuffer *intel_fb;
7625
7626 val = I915_READ(DSPCNTR(plane));
7627 if (!(val & DISPLAY_PLANE_ENABLE))
7628 return;
7629
7630 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7631 if (!intel_fb) {
7632 DRM_DEBUG_KMS("failed to alloc fb\n");
7633 return;
7634 }
7635
7636 fb = &intel_fb->base;
7637
7638 if (INTEL_INFO(dev)->gen >= 4) {
7639 if (val & DISPPLANE_TILED) {
7640 plane_config->tiling = I915_TILING_X;
7641 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7642 }
7643 }
7644
7645 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7646 fourcc = i9xx_format_to_fourcc(pixel_format);
7647 fb->pixel_format = fourcc;
7648 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7649
7650 if (INTEL_INFO(dev)->gen >= 4) {
7651 if (plane_config->tiling)
7652 offset = I915_READ(DSPTILEOFF(plane));
7653 else
7654 offset = I915_READ(DSPLINOFF(plane));
7655 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7656 } else {
7657 base = I915_READ(DSPADDR(plane));
7658 }
7659 plane_config->base = base;
7660
7661 val = I915_READ(PIPESRC(pipe));
7662 fb->width = ((val >> 16) & 0xfff) + 1;
7663 fb->height = ((val >> 0) & 0xfff) + 1;
7664
7665 val = I915_READ(DSPSTRIDE(pipe));
7666 fb->pitches[0] = val & 0xffffffc0;
7667
7668 aligned_height = intel_fb_align_height(dev, fb->height,
7669 fb->pixel_format,
7670 fb->modifier[0]);
7671
7672 plane_config->size = fb->pitches[0] * aligned_height;
7673
7674 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7675 pipe_name(pipe), plane, fb->width, fb->height,
7676 fb->bits_per_pixel, base, fb->pitches[0],
7677 plane_config->size);
7678
7679 plane_config->fb = intel_fb;
7680 }
7681
7682 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7683 struct intel_crtc_state *pipe_config)
7684 {
7685 struct drm_device *dev = crtc->base.dev;
7686 struct drm_i915_private *dev_priv = dev->dev_private;
7687 int pipe = pipe_config->cpu_transcoder;
7688 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7689 intel_clock_t clock;
7690 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
7691 int refclk = 100000;
7692
7693 mutex_lock(&dev_priv->dpio_lock);
7694 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7695 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7696 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7697 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7698 mutex_unlock(&dev_priv->dpio_lock);
7699
7700 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7701 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
7702 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7703 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7704 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7705
7706 chv_clock(refclk, &clock);
7707
7708 /* clock.dot is the fast clock */
7709 pipe_config->port_clock = clock.dot / 5;
7710 }
7711
7712 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7713 struct intel_crtc_state *pipe_config)
7714 {
7715 struct drm_device *dev = crtc->base.dev;
7716 struct drm_i915_private *dev_priv = dev->dev_private;
7717 uint32_t tmp;
7718
7719 if (!intel_display_power_is_enabled(dev_priv,
7720 POWER_DOMAIN_PIPE(crtc->pipe)))
7721 return false;
7722
7723 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7724 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7725
7726 tmp = I915_READ(PIPECONF(crtc->pipe));
7727 if (!(tmp & PIPECONF_ENABLE))
7728 return false;
7729
7730 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7731 switch (tmp & PIPECONF_BPC_MASK) {
7732 case PIPECONF_6BPC:
7733 pipe_config->pipe_bpp = 18;
7734 break;
7735 case PIPECONF_8BPC:
7736 pipe_config->pipe_bpp = 24;
7737 break;
7738 case PIPECONF_10BPC:
7739 pipe_config->pipe_bpp = 30;
7740 break;
7741 default:
7742 break;
7743 }
7744 }
7745
7746 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
7747 pipe_config->limited_color_range = true;
7748
7749 if (INTEL_INFO(dev)->gen < 4)
7750 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7751
7752 intel_get_pipe_timings(crtc, pipe_config);
7753
7754 i9xx_get_pfit_config(crtc, pipe_config);
7755
7756 if (INTEL_INFO(dev)->gen >= 4) {
7757 tmp = I915_READ(DPLL_MD(crtc->pipe));
7758 pipe_config->pixel_multiplier =
7759 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7760 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7761 pipe_config->dpll_hw_state.dpll_md = tmp;
7762 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7763 tmp = I915_READ(DPLL(crtc->pipe));
7764 pipe_config->pixel_multiplier =
7765 ((tmp & SDVO_MULTIPLIER_MASK)
7766 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7767 } else {
7768 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7769 * port and will be fixed up in the encoder->get_config
7770 * function. */
7771 pipe_config->pixel_multiplier = 1;
7772 }
7773 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7774 if (!IS_VALLEYVIEW(dev)) {
7775 /*
7776 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7777 * on 830. Filter it out here so that we don't
7778 * report errors due to that.
7779 */
7780 if (IS_I830(dev))
7781 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7782
7783 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7784 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7785 } else {
7786 /* Mask out read-only status bits. */
7787 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7788 DPLL_PORTC_READY_MASK |
7789 DPLL_PORTB_READY_MASK);
7790 }
7791
7792 if (IS_CHERRYVIEW(dev))
7793 chv_crtc_clock_get(crtc, pipe_config);
7794 else if (IS_VALLEYVIEW(dev))
7795 vlv_crtc_clock_get(crtc, pipe_config);
7796 else
7797 i9xx_crtc_clock_get(crtc, pipe_config);
7798
7799 return true;
7800 }
7801
7802 static void ironlake_init_pch_refclk(struct drm_device *dev)
7803 {
7804 struct drm_i915_private *dev_priv = dev->dev_private;
7805 struct intel_encoder *encoder;
7806 u32 val, final;
7807 bool has_lvds = false;
7808 bool has_cpu_edp = false;
7809 bool has_panel = false;
7810 bool has_ck505 = false;
7811 bool can_ssc = false;
7812
7813 /* We need to take the global config into account */
7814 for_each_intel_encoder(dev, encoder) {
7815 switch (encoder->type) {
7816 case INTEL_OUTPUT_LVDS:
7817 has_panel = true;
7818 has_lvds = true;
7819 break;
7820 case INTEL_OUTPUT_EDP:
7821 has_panel = true;
7822 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
7823 has_cpu_edp = true;
7824 break;
7825 default:
7826 break;
7827 }
7828 }
7829
7830 if (HAS_PCH_IBX(dev)) {
7831 has_ck505 = dev_priv->vbt.display_clock_mode;
7832 can_ssc = has_ck505;
7833 } else {
7834 has_ck505 = false;
7835 can_ssc = true;
7836 }
7837
7838 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
7839 has_panel, has_lvds, has_ck505);
7840
7841 /* Ironlake: try to setup display ref clock before DPLL
7842 * enabling. This is only under driver's control after
7843 * PCH B stepping, previous chipset stepping should be
7844 * ignoring this setting.
7845 */
7846 val = I915_READ(PCH_DREF_CONTROL);
7847
7848 /* As we must carefully and slowly disable/enable each source in turn,
7849 * compute the final state we want first and check if we need to
7850 * make any changes at all.
7851 */
7852 final = val;
7853 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7854 if (has_ck505)
7855 final |= DREF_NONSPREAD_CK505_ENABLE;
7856 else
7857 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7858
7859 final &= ~DREF_SSC_SOURCE_MASK;
7860 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7861 final &= ~DREF_SSC1_ENABLE;
7862
7863 if (has_panel) {
7864 final |= DREF_SSC_SOURCE_ENABLE;
7865
7866 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7867 final |= DREF_SSC1_ENABLE;
7868
7869 if (has_cpu_edp) {
7870 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7871 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7872 else
7873 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7874 } else
7875 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7876 } else {
7877 final |= DREF_SSC_SOURCE_DISABLE;
7878 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7879 }
7880
7881 if (final == val)
7882 return;
7883
7884 /* Always enable nonspread source */
7885 val &= ~DREF_NONSPREAD_SOURCE_MASK;
7886
7887 if (has_ck505)
7888 val |= DREF_NONSPREAD_CK505_ENABLE;
7889 else
7890 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7891
7892 if (has_panel) {
7893 val &= ~DREF_SSC_SOURCE_MASK;
7894 val |= DREF_SSC_SOURCE_ENABLE;
7895
7896 /* SSC must be turned on before enabling the CPU output */
7897 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7898 DRM_DEBUG_KMS("Using SSC on panel\n");
7899 val |= DREF_SSC1_ENABLE;
7900 } else
7901 val &= ~DREF_SSC1_ENABLE;
7902
7903 /* Get SSC going before enabling the outputs */
7904 I915_WRITE(PCH_DREF_CONTROL, val);
7905 POSTING_READ(PCH_DREF_CONTROL);
7906 udelay(200);
7907
7908 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7909
7910 /* Enable CPU source on CPU attached eDP */
7911 if (has_cpu_edp) {
7912 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7913 DRM_DEBUG_KMS("Using SSC on eDP\n");
7914 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7915 } else
7916 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7917 } else
7918 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7919
7920 I915_WRITE(PCH_DREF_CONTROL, val);
7921 POSTING_READ(PCH_DREF_CONTROL);
7922 udelay(200);
7923 } else {
7924 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7925
7926 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7927
7928 /* Turn off CPU output */
7929 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7930
7931 I915_WRITE(PCH_DREF_CONTROL, val);
7932 POSTING_READ(PCH_DREF_CONTROL);
7933 udelay(200);
7934
7935 /* Turn off the SSC source */
7936 val &= ~DREF_SSC_SOURCE_MASK;
7937 val |= DREF_SSC_SOURCE_DISABLE;
7938
7939 /* Turn off SSC1 */
7940 val &= ~DREF_SSC1_ENABLE;
7941
7942 I915_WRITE(PCH_DREF_CONTROL, val);
7943 POSTING_READ(PCH_DREF_CONTROL);
7944 udelay(200);
7945 }
7946
7947 BUG_ON(val != final);
7948 }
7949
7950 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7951 {
7952 uint32_t tmp;
7953
7954 tmp = I915_READ(SOUTH_CHICKEN2);
7955 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7956 I915_WRITE(SOUTH_CHICKEN2, tmp);
7957
7958 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
7959 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7960 DRM_ERROR("FDI mPHY reset assert timeout\n");
7961
7962 tmp = I915_READ(SOUTH_CHICKEN2);
7963 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7964 I915_WRITE(SOUTH_CHICKEN2, tmp);
7965
7966 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
7967 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7968 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7969 }
7970
7971 /* WaMPhyProgramming:hsw */
7972 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7973 {
7974 uint32_t tmp;
7975
7976 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7977 tmp &= ~(0xFF << 24);
7978 tmp |= (0x12 << 24);
7979 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7980
7981 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7982 tmp |= (1 << 11);
7983 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7984
7985 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7986 tmp |= (1 << 11);
7987 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7988
7989 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7990 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7991 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7992
7993 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7994 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7995 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7996
7997 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7998 tmp &= ~(7 << 13);
7999 tmp |= (5 << 13);
8000 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8001
8002 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8003 tmp &= ~(7 << 13);
8004 tmp |= (5 << 13);
8005 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8006
8007 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8008 tmp &= ~0xFF;
8009 tmp |= 0x1C;
8010 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8011
8012 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8013 tmp &= ~0xFF;
8014 tmp |= 0x1C;
8015 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8016
8017 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8018 tmp &= ~(0xFF << 16);
8019 tmp |= (0x1C << 16);
8020 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8021
8022 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8023 tmp &= ~(0xFF << 16);
8024 tmp |= (0x1C << 16);
8025 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8026
8027 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8028 tmp |= (1 << 27);
8029 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8030
8031 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8032 tmp |= (1 << 27);
8033 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8034
8035 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8036 tmp &= ~(0xF << 28);
8037 tmp |= (4 << 28);
8038 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8039
8040 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8041 tmp &= ~(0xF << 28);
8042 tmp |= (4 << 28);
8043 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8044 }
8045
8046 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8047 * Programming" based on the parameters passed:
8048 * - Sequence to enable CLKOUT_DP
8049 * - Sequence to enable CLKOUT_DP without spread
8050 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8051 */
8052 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8053 bool with_fdi)
8054 {
8055 struct drm_i915_private *dev_priv = dev->dev_private;
8056 uint32_t reg, tmp;
8057
8058 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8059 with_spread = true;
8060 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8061 with_fdi, "LP PCH doesn't have FDI\n"))
8062 with_fdi = false;
8063
8064 mutex_lock(&dev_priv->dpio_lock);
8065
8066 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8067 tmp &= ~SBI_SSCCTL_DISABLE;
8068 tmp |= SBI_SSCCTL_PATHALT;
8069 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8070
8071 udelay(24);
8072
8073 if (with_spread) {
8074 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8075 tmp &= ~SBI_SSCCTL_PATHALT;
8076 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8077
8078 if (with_fdi) {
8079 lpt_reset_fdi_mphy(dev_priv);
8080 lpt_program_fdi_mphy(dev_priv);
8081 }
8082 }
8083
8084 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8085 SBI_GEN0 : SBI_DBUFF0;
8086 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8087 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8088 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8089
8090 mutex_unlock(&dev_priv->dpio_lock);
8091 }
8092
8093 /* Sequence to disable CLKOUT_DP */
8094 static void lpt_disable_clkout_dp(struct drm_device *dev)
8095 {
8096 struct drm_i915_private *dev_priv = dev->dev_private;
8097 uint32_t reg, tmp;
8098
8099 mutex_lock(&dev_priv->dpio_lock);
8100
8101 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8102 SBI_GEN0 : SBI_DBUFF0;
8103 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8104 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8105 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8106
8107 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8108 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8109 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8110 tmp |= SBI_SSCCTL_PATHALT;
8111 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8112 udelay(32);
8113 }
8114 tmp |= SBI_SSCCTL_DISABLE;
8115 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8116 }
8117
8118 mutex_unlock(&dev_priv->dpio_lock);
8119 }
8120
8121 static void lpt_init_pch_refclk(struct drm_device *dev)
8122 {
8123 struct intel_encoder *encoder;
8124 bool has_vga = false;
8125
8126 for_each_intel_encoder(dev, encoder) {
8127 switch (encoder->type) {
8128 case INTEL_OUTPUT_ANALOG:
8129 has_vga = true;
8130 break;
8131 default:
8132 break;
8133 }
8134 }
8135
8136 if (has_vga)
8137 lpt_enable_clkout_dp(dev, true, true);
8138 else
8139 lpt_disable_clkout_dp(dev);
8140 }
8141
8142 /*
8143 * Initialize reference clocks when the driver loads
8144 */
8145 void intel_init_pch_refclk(struct drm_device *dev)
8146 {
8147 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8148 ironlake_init_pch_refclk(dev);
8149 else if (HAS_PCH_LPT(dev))
8150 lpt_init_pch_refclk(dev);
8151 }
8152
8153 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8154 {
8155 struct drm_device *dev = crtc_state->base.crtc->dev;
8156 struct drm_i915_private *dev_priv = dev->dev_private;
8157 struct drm_atomic_state *state = crtc_state->base.state;
8158 struct drm_connector *connector;
8159 struct drm_connector_state *connector_state;
8160 struct intel_encoder *encoder;
8161 int num_connectors = 0, i;
8162 bool is_lvds = false;
8163
8164 for_each_connector_in_state(state, connector, connector_state, i) {
8165 if (connector_state->crtc != crtc_state->base.crtc)
8166 continue;
8167
8168 encoder = to_intel_encoder(connector_state->best_encoder);
8169
8170 switch (encoder->type) {
8171 case INTEL_OUTPUT_LVDS:
8172 is_lvds = true;
8173 break;
8174 default:
8175 break;
8176 }
8177 num_connectors++;
8178 }
8179
8180 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8181 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8182 dev_priv->vbt.lvds_ssc_freq);
8183 return dev_priv->vbt.lvds_ssc_freq;
8184 }
8185
8186 return 120000;
8187 }
8188
8189 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8190 {
8191 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8192 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8193 int pipe = intel_crtc->pipe;
8194 uint32_t val;
8195
8196 val = 0;
8197
8198 switch (intel_crtc->config->pipe_bpp) {
8199 case 18:
8200 val |= PIPECONF_6BPC;
8201 break;
8202 case 24:
8203 val |= PIPECONF_8BPC;
8204 break;
8205 case 30:
8206 val |= PIPECONF_10BPC;
8207 break;
8208 case 36:
8209 val |= PIPECONF_12BPC;
8210 break;
8211 default:
8212 /* Case prevented by intel_choose_pipe_bpp_dither. */
8213 BUG();
8214 }
8215
8216 if (intel_crtc->config->dither)
8217 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8218
8219 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8220 val |= PIPECONF_INTERLACED_ILK;
8221 else
8222 val |= PIPECONF_PROGRESSIVE;
8223
8224 if (intel_crtc->config->limited_color_range)
8225 val |= PIPECONF_COLOR_RANGE_SELECT;
8226
8227 I915_WRITE(PIPECONF(pipe), val);
8228 POSTING_READ(PIPECONF(pipe));
8229 }
8230
8231 /*
8232 * Set up the pipe CSC unit.
8233 *
8234 * Currently only full range RGB to limited range RGB conversion
8235 * is supported, but eventually this should handle various
8236 * RGB<->YCbCr scenarios as well.
8237 */
8238 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8239 {
8240 struct drm_device *dev = crtc->dev;
8241 struct drm_i915_private *dev_priv = dev->dev_private;
8242 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8243 int pipe = intel_crtc->pipe;
8244 uint16_t coeff = 0x7800; /* 1.0 */
8245
8246 /*
8247 * TODO: Check what kind of values actually come out of the pipe
8248 * with these coeff/postoff values and adjust to get the best
8249 * accuracy. Perhaps we even need to take the bpc value into
8250 * consideration.
8251 */
8252
8253 if (intel_crtc->config->limited_color_range)
8254 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8255
8256 /*
8257 * GY/GU and RY/RU should be the other way around according
8258 * to BSpec, but reality doesn't agree. Just set them up in
8259 * a way that results in the correct picture.
8260 */
8261 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8262 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8263
8264 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8265 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8266
8267 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8268 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8269
8270 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8271 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8272 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8273
8274 if (INTEL_INFO(dev)->gen > 6) {
8275 uint16_t postoff = 0;
8276
8277 if (intel_crtc->config->limited_color_range)
8278 postoff = (16 * (1 << 12) / 255) & 0x1fff;
8279
8280 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8281 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8282 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8283
8284 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8285 } else {
8286 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8287
8288 if (intel_crtc->config->limited_color_range)
8289 mode |= CSC_BLACK_SCREEN_OFFSET;
8290
8291 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8292 }
8293 }
8294
8295 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8296 {
8297 struct drm_device *dev = crtc->dev;
8298 struct drm_i915_private *dev_priv = dev->dev_private;
8299 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8300 enum pipe pipe = intel_crtc->pipe;
8301 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8302 uint32_t val;
8303
8304 val = 0;
8305
8306 if (IS_HASWELL(dev) && intel_crtc->config->dither)
8307 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8308
8309 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8310 val |= PIPECONF_INTERLACED_ILK;
8311 else
8312 val |= PIPECONF_PROGRESSIVE;
8313
8314 I915_WRITE(PIPECONF(cpu_transcoder), val);
8315 POSTING_READ(PIPECONF(cpu_transcoder));
8316
8317 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8318 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8319
8320 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8321 val = 0;
8322
8323 switch (intel_crtc->config->pipe_bpp) {
8324 case 18:
8325 val |= PIPEMISC_DITHER_6_BPC;
8326 break;
8327 case 24:
8328 val |= PIPEMISC_DITHER_8_BPC;
8329 break;
8330 case 30:
8331 val |= PIPEMISC_DITHER_10_BPC;
8332 break;
8333 case 36:
8334 val |= PIPEMISC_DITHER_12_BPC;
8335 break;
8336 default:
8337 /* Case prevented by pipe_config_set_bpp. */
8338 BUG();
8339 }
8340
8341 if (intel_crtc->config->dither)
8342 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8343
8344 I915_WRITE(PIPEMISC(pipe), val);
8345 }
8346 }
8347
8348 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8349 struct intel_crtc_state *crtc_state,
8350 intel_clock_t *clock,
8351 bool *has_reduced_clock,
8352 intel_clock_t *reduced_clock)
8353 {
8354 struct drm_device *dev = crtc->dev;
8355 struct drm_i915_private *dev_priv = dev->dev_private;
8356 int refclk;
8357 const intel_limit_t *limit;
8358 bool ret, is_lvds = false;
8359
8360 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
8361
8362 refclk = ironlake_get_refclk(crtc_state);
8363
8364 /*
8365 * Returns a set of divisors for the desired target clock with the given
8366 * refclk, or FALSE. The returned values represent the clock equation:
8367 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8368 */
8369 limit = intel_limit(crtc_state, refclk);
8370 ret = dev_priv->display.find_dpll(limit, crtc_state,
8371 crtc_state->port_clock,
8372 refclk, NULL, clock);
8373 if (!ret)
8374 return false;
8375
8376 if (is_lvds && dev_priv->lvds_downclock_avail) {
8377 /*
8378 * Ensure we match the reduced clock's P to the target clock.
8379 * If the clocks don't match, we can't switch the display clock
8380 * by using the FP0/FP1. In such case we will disable the LVDS
8381 * downclock feature.
8382 */
8383 *has_reduced_clock =
8384 dev_priv->display.find_dpll(limit, crtc_state,
8385 dev_priv->lvds_downclock,
8386 refclk, clock,
8387 reduced_clock);
8388 }
8389
8390 return true;
8391 }
8392
8393 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8394 {
8395 /*
8396 * Account for spread spectrum to avoid
8397 * oversubscribing the link. Max center spread
8398 * is 2.5%; use 5% for safety's sake.
8399 */
8400 u32 bps = target_clock * bpp * 21 / 20;
8401 return DIV_ROUND_UP(bps, link_bw * 8);
8402 }
8403
8404 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8405 {
8406 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8407 }
8408
8409 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8410 struct intel_crtc_state *crtc_state,
8411 u32 *fp,
8412 intel_clock_t *reduced_clock, u32 *fp2)
8413 {
8414 struct drm_crtc *crtc = &intel_crtc->base;
8415 struct drm_device *dev = crtc->dev;
8416 struct drm_i915_private *dev_priv = dev->dev_private;
8417 struct drm_atomic_state *state = crtc_state->base.state;
8418 struct drm_connector *connector;
8419 struct drm_connector_state *connector_state;
8420 struct intel_encoder *encoder;
8421 uint32_t dpll;
8422 int factor, num_connectors = 0, i;
8423 bool is_lvds = false, is_sdvo = false;
8424
8425 for_each_connector_in_state(state, connector, connector_state, i) {
8426 if (connector_state->crtc != crtc_state->base.crtc)
8427 continue;
8428
8429 encoder = to_intel_encoder(connector_state->best_encoder);
8430
8431 switch (encoder->type) {
8432 case INTEL_OUTPUT_LVDS:
8433 is_lvds = true;
8434 break;
8435 case INTEL_OUTPUT_SDVO:
8436 case INTEL_OUTPUT_HDMI:
8437 is_sdvo = true;
8438 break;
8439 default:
8440 break;
8441 }
8442
8443 num_connectors++;
8444 }
8445
8446 /* Enable autotuning of the PLL clock (if permissible) */
8447 factor = 21;
8448 if (is_lvds) {
8449 if ((intel_panel_use_ssc(dev_priv) &&
8450 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8451 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8452 factor = 25;
8453 } else if (crtc_state->sdvo_tv_clock)
8454 factor = 20;
8455
8456 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8457 *fp |= FP_CB_TUNE;
8458
8459 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8460 *fp2 |= FP_CB_TUNE;
8461
8462 dpll = 0;
8463
8464 if (is_lvds)
8465 dpll |= DPLLB_MODE_LVDS;
8466 else
8467 dpll |= DPLLB_MODE_DAC_SERIAL;
8468
8469 dpll |= (crtc_state->pixel_multiplier - 1)
8470 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8471
8472 if (is_sdvo)
8473 dpll |= DPLL_SDVO_HIGH_SPEED;
8474 if (crtc_state->has_dp_encoder)
8475 dpll |= DPLL_SDVO_HIGH_SPEED;
8476
8477 /* compute bitmask from p1 value */
8478 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8479 /* also FPA1 */
8480 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8481
8482 switch (crtc_state->dpll.p2) {
8483 case 5:
8484 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8485 break;
8486 case 7:
8487 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8488 break;
8489 case 10:
8490 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8491 break;
8492 case 14:
8493 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8494 break;
8495 }
8496
8497 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8498 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8499 else
8500 dpll |= PLL_REF_INPUT_DREFCLK;
8501
8502 return dpll | DPLL_VCO_ENABLE;
8503 }
8504
8505 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8506 struct intel_crtc_state *crtc_state)
8507 {
8508 struct drm_device *dev = crtc->base.dev;
8509 intel_clock_t clock, reduced_clock;
8510 u32 dpll = 0, fp = 0, fp2 = 0;
8511 bool ok, has_reduced_clock = false;
8512 bool is_lvds = false;
8513 struct intel_shared_dpll *pll;
8514
8515 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8516
8517 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8518 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8519
8520 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8521 &has_reduced_clock, &reduced_clock);
8522 if (!ok && !crtc_state->clock_set) {
8523 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8524 return -EINVAL;
8525 }
8526 /* Compat-code for transition, will disappear. */
8527 if (!crtc_state->clock_set) {
8528 crtc_state->dpll.n = clock.n;
8529 crtc_state->dpll.m1 = clock.m1;
8530 crtc_state->dpll.m2 = clock.m2;
8531 crtc_state->dpll.p1 = clock.p1;
8532 crtc_state->dpll.p2 = clock.p2;
8533 }
8534
8535 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8536 if (crtc_state->has_pch_encoder) {
8537 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8538 if (has_reduced_clock)
8539 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8540
8541 dpll = ironlake_compute_dpll(crtc, crtc_state,
8542 &fp, &reduced_clock,
8543 has_reduced_clock ? &fp2 : NULL);
8544
8545 crtc_state->dpll_hw_state.dpll = dpll;
8546 crtc_state->dpll_hw_state.fp0 = fp;
8547 if (has_reduced_clock)
8548 crtc_state->dpll_hw_state.fp1 = fp2;
8549 else
8550 crtc_state->dpll_hw_state.fp1 = fp;
8551
8552 pll = intel_get_shared_dpll(crtc, crtc_state);
8553 if (pll == NULL) {
8554 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8555 pipe_name(crtc->pipe));
8556 return -EINVAL;
8557 }
8558 }
8559
8560 if (is_lvds && has_reduced_clock)
8561 crtc->lowfreq_avail = true;
8562 else
8563 crtc->lowfreq_avail = false;
8564
8565 return 0;
8566 }
8567
8568 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8569 struct intel_link_m_n *m_n)
8570 {
8571 struct drm_device *dev = crtc->base.dev;
8572 struct drm_i915_private *dev_priv = dev->dev_private;
8573 enum pipe pipe = crtc->pipe;
8574
8575 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8576 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8577 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8578 & ~TU_SIZE_MASK;
8579 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8580 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8581 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8582 }
8583
8584 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8585 enum transcoder transcoder,
8586 struct intel_link_m_n *m_n,
8587 struct intel_link_m_n *m2_n2)
8588 {
8589 struct drm_device *dev = crtc->base.dev;
8590 struct drm_i915_private *dev_priv = dev->dev_private;
8591 enum pipe pipe = crtc->pipe;
8592
8593 if (INTEL_INFO(dev)->gen >= 5) {
8594 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8595 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8596 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8597 & ~TU_SIZE_MASK;
8598 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8599 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8600 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8601 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8602 * gen < 8) and if DRRS is supported (to make sure the
8603 * registers are not unnecessarily read).
8604 */
8605 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8606 crtc->config->has_drrs) {
8607 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8608 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8609 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8610 & ~TU_SIZE_MASK;
8611 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8612 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8613 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8614 }
8615 } else {
8616 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8617 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8618 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8619 & ~TU_SIZE_MASK;
8620 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8621 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8622 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8623 }
8624 }
8625
8626 void intel_dp_get_m_n(struct intel_crtc *crtc,
8627 struct intel_crtc_state *pipe_config)
8628 {
8629 if (pipe_config->has_pch_encoder)
8630 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8631 else
8632 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8633 &pipe_config->dp_m_n,
8634 &pipe_config->dp_m2_n2);
8635 }
8636
8637 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8638 struct intel_crtc_state *pipe_config)
8639 {
8640 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8641 &pipe_config->fdi_m_n, NULL);
8642 }
8643
8644 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8645 struct intel_crtc_state *pipe_config)
8646 {
8647 struct drm_device *dev = crtc->base.dev;
8648 struct drm_i915_private *dev_priv = dev->dev_private;
8649 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8650 uint32_t ps_ctrl = 0;
8651 int id = -1;
8652 int i;
8653
8654 /* find scaler attached to this pipe */
8655 for (i = 0; i < crtc->num_scalers; i++) {
8656 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8657 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8658 id = i;
8659 pipe_config->pch_pfit.enabled = true;
8660 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8661 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8662 break;
8663 }
8664 }
8665
8666 scaler_state->scaler_id = id;
8667 if (id >= 0) {
8668 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8669 } else {
8670 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8671 }
8672 }
8673
8674 static void
8675 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8676 struct intel_initial_plane_config *plane_config)
8677 {
8678 struct drm_device *dev = crtc->base.dev;
8679 struct drm_i915_private *dev_priv = dev->dev_private;
8680 u32 val, base, offset, stride_mult, tiling;
8681 int pipe = crtc->pipe;
8682 int fourcc, pixel_format;
8683 unsigned int aligned_height;
8684 struct drm_framebuffer *fb;
8685 struct intel_framebuffer *intel_fb;
8686
8687 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8688 if (!intel_fb) {
8689 DRM_DEBUG_KMS("failed to alloc fb\n");
8690 return;
8691 }
8692
8693 fb = &intel_fb->base;
8694
8695 val = I915_READ(PLANE_CTL(pipe, 0));
8696 if (!(val & PLANE_CTL_ENABLE))
8697 goto error;
8698
8699 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8700 fourcc = skl_format_to_fourcc(pixel_format,
8701 val & PLANE_CTL_ORDER_RGBX,
8702 val & PLANE_CTL_ALPHA_MASK);
8703 fb->pixel_format = fourcc;
8704 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8705
8706 tiling = val & PLANE_CTL_TILED_MASK;
8707 switch (tiling) {
8708 case PLANE_CTL_TILED_LINEAR:
8709 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
8710 break;
8711 case PLANE_CTL_TILED_X:
8712 plane_config->tiling = I915_TILING_X;
8713 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8714 break;
8715 case PLANE_CTL_TILED_Y:
8716 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
8717 break;
8718 case PLANE_CTL_TILED_YF:
8719 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
8720 break;
8721 default:
8722 MISSING_CASE(tiling);
8723 goto error;
8724 }
8725
8726 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8727 plane_config->base = base;
8728
8729 offset = I915_READ(PLANE_OFFSET(pipe, 0));
8730
8731 val = I915_READ(PLANE_SIZE(pipe, 0));
8732 fb->height = ((val >> 16) & 0xfff) + 1;
8733 fb->width = ((val >> 0) & 0x1fff) + 1;
8734
8735 val = I915_READ(PLANE_STRIDE(pipe, 0));
8736 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
8737 fb->pixel_format);
8738 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8739
8740 aligned_height = intel_fb_align_height(dev, fb->height,
8741 fb->pixel_format,
8742 fb->modifier[0]);
8743
8744 plane_config->size = fb->pitches[0] * aligned_height;
8745
8746 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8747 pipe_name(pipe), fb->width, fb->height,
8748 fb->bits_per_pixel, base, fb->pitches[0],
8749 plane_config->size);
8750
8751 plane_config->fb = intel_fb;
8752 return;
8753
8754 error:
8755 kfree(fb);
8756 }
8757
8758 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8759 struct intel_crtc_state *pipe_config)
8760 {
8761 struct drm_device *dev = crtc->base.dev;
8762 struct drm_i915_private *dev_priv = dev->dev_private;
8763 uint32_t tmp;
8764
8765 tmp = I915_READ(PF_CTL(crtc->pipe));
8766
8767 if (tmp & PF_ENABLE) {
8768 pipe_config->pch_pfit.enabled = true;
8769 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8770 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8771
8772 /* We currently do not free assignements of panel fitters on
8773 * ivb/hsw (since we don't use the higher upscaling modes which
8774 * differentiates them) so just WARN about this case for now. */
8775 if (IS_GEN7(dev)) {
8776 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8777 PF_PIPE_SEL_IVB(crtc->pipe));
8778 }
8779 }
8780 }
8781
8782 static void
8783 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8784 struct intel_initial_plane_config *plane_config)
8785 {
8786 struct drm_device *dev = crtc->base.dev;
8787 struct drm_i915_private *dev_priv = dev->dev_private;
8788 u32 val, base, offset;
8789 int pipe = crtc->pipe;
8790 int fourcc, pixel_format;
8791 unsigned int aligned_height;
8792 struct drm_framebuffer *fb;
8793 struct intel_framebuffer *intel_fb;
8794
8795 val = I915_READ(DSPCNTR(pipe));
8796 if (!(val & DISPLAY_PLANE_ENABLE))
8797 return;
8798
8799 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8800 if (!intel_fb) {
8801 DRM_DEBUG_KMS("failed to alloc fb\n");
8802 return;
8803 }
8804
8805 fb = &intel_fb->base;
8806
8807 if (INTEL_INFO(dev)->gen >= 4) {
8808 if (val & DISPPLANE_TILED) {
8809 plane_config->tiling = I915_TILING_X;
8810 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8811 }
8812 }
8813
8814 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8815 fourcc = i9xx_format_to_fourcc(pixel_format);
8816 fb->pixel_format = fourcc;
8817 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8818
8819 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
8820 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
8821 offset = I915_READ(DSPOFFSET(pipe));
8822 } else {
8823 if (plane_config->tiling)
8824 offset = I915_READ(DSPTILEOFF(pipe));
8825 else
8826 offset = I915_READ(DSPLINOFF(pipe));
8827 }
8828 plane_config->base = base;
8829
8830 val = I915_READ(PIPESRC(pipe));
8831 fb->width = ((val >> 16) & 0xfff) + 1;
8832 fb->height = ((val >> 0) & 0xfff) + 1;
8833
8834 val = I915_READ(DSPSTRIDE(pipe));
8835 fb->pitches[0] = val & 0xffffffc0;
8836
8837 aligned_height = intel_fb_align_height(dev, fb->height,
8838 fb->pixel_format,
8839 fb->modifier[0]);
8840
8841 plane_config->size = fb->pitches[0] * aligned_height;
8842
8843 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8844 pipe_name(pipe), fb->width, fb->height,
8845 fb->bits_per_pixel, base, fb->pitches[0],
8846 plane_config->size);
8847
8848 plane_config->fb = intel_fb;
8849 }
8850
8851 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8852 struct intel_crtc_state *pipe_config)
8853 {
8854 struct drm_device *dev = crtc->base.dev;
8855 struct drm_i915_private *dev_priv = dev->dev_private;
8856 uint32_t tmp;
8857
8858 if (!intel_display_power_is_enabled(dev_priv,
8859 POWER_DOMAIN_PIPE(crtc->pipe)))
8860 return false;
8861
8862 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8863 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8864
8865 tmp = I915_READ(PIPECONF(crtc->pipe));
8866 if (!(tmp & PIPECONF_ENABLE))
8867 return false;
8868
8869 switch (tmp & PIPECONF_BPC_MASK) {
8870 case PIPECONF_6BPC:
8871 pipe_config->pipe_bpp = 18;
8872 break;
8873 case PIPECONF_8BPC:
8874 pipe_config->pipe_bpp = 24;
8875 break;
8876 case PIPECONF_10BPC:
8877 pipe_config->pipe_bpp = 30;
8878 break;
8879 case PIPECONF_12BPC:
8880 pipe_config->pipe_bpp = 36;
8881 break;
8882 default:
8883 break;
8884 }
8885
8886 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8887 pipe_config->limited_color_range = true;
8888
8889 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8890 struct intel_shared_dpll *pll;
8891
8892 pipe_config->has_pch_encoder = true;
8893
8894 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8895 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8896 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8897
8898 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8899
8900 if (HAS_PCH_IBX(dev_priv->dev)) {
8901 pipe_config->shared_dpll =
8902 (enum intel_dpll_id) crtc->pipe;
8903 } else {
8904 tmp = I915_READ(PCH_DPLL_SEL);
8905 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8906 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
8907 else
8908 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
8909 }
8910
8911 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8912
8913 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8914 &pipe_config->dpll_hw_state));
8915
8916 tmp = pipe_config->dpll_hw_state.dpll;
8917 pipe_config->pixel_multiplier =
8918 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8919 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8920
8921 ironlake_pch_clock_get(crtc, pipe_config);
8922 } else {
8923 pipe_config->pixel_multiplier = 1;
8924 }
8925
8926 intel_get_pipe_timings(crtc, pipe_config);
8927
8928 ironlake_get_pfit_config(crtc, pipe_config);
8929
8930 return true;
8931 }
8932
8933 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8934 {
8935 struct drm_device *dev = dev_priv->dev;
8936 struct intel_crtc *crtc;
8937
8938 for_each_intel_crtc(dev, crtc)
8939 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8940 pipe_name(crtc->pipe));
8941
8942 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8943 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8944 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8945 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8946 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
8947 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8948 "CPU PWM1 enabled\n");
8949 if (IS_HASWELL(dev))
8950 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8951 "CPU PWM2 enabled\n");
8952 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8953 "PCH PWM1 enabled\n");
8954 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8955 "Utility pin enabled\n");
8956 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8957
8958 /*
8959 * In theory we can still leave IRQs enabled, as long as only the HPD
8960 * interrupts remain enabled. We used to check for that, but since it's
8961 * gen-specific and since we only disable LCPLL after we fully disable
8962 * the interrupts, the check below should be enough.
8963 */
8964 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8965 }
8966
8967 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8968 {
8969 struct drm_device *dev = dev_priv->dev;
8970
8971 if (IS_HASWELL(dev))
8972 return I915_READ(D_COMP_HSW);
8973 else
8974 return I915_READ(D_COMP_BDW);
8975 }
8976
8977 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8978 {
8979 struct drm_device *dev = dev_priv->dev;
8980
8981 if (IS_HASWELL(dev)) {
8982 mutex_lock(&dev_priv->rps.hw_lock);
8983 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8984 val))
8985 DRM_ERROR("Failed to write to D_COMP\n");
8986 mutex_unlock(&dev_priv->rps.hw_lock);
8987 } else {
8988 I915_WRITE(D_COMP_BDW, val);
8989 POSTING_READ(D_COMP_BDW);
8990 }
8991 }
8992
8993 /*
8994 * This function implements pieces of two sequences from BSpec:
8995 * - Sequence for display software to disable LCPLL
8996 * - Sequence for display software to allow package C8+
8997 * The steps implemented here are just the steps that actually touch the LCPLL
8998 * register. Callers should take care of disabling all the display engine
8999 * functions, doing the mode unset, fixing interrupts, etc.
9000 */
9001 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9002 bool switch_to_fclk, bool allow_power_down)
9003 {
9004 uint32_t val;
9005
9006 assert_can_disable_lcpll(dev_priv);
9007
9008 val = I915_READ(LCPLL_CTL);
9009
9010 if (switch_to_fclk) {
9011 val |= LCPLL_CD_SOURCE_FCLK;
9012 I915_WRITE(LCPLL_CTL, val);
9013
9014 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9015 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9016 DRM_ERROR("Switching to FCLK failed\n");
9017
9018 val = I915_READ(LCPLL_CTL);
9019 }
9020
9021 val |= LCPLL_PLL_DISABLE;
9022 I915_WRITE(LCPLL_CTL, val);
9023 POSTING_READ(LCPLL_CTL);
9024
9025 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9026 DRM_ERROR("LCPLL still locked\n");
9027
9028 val = hsw_read_dcomp(dev_priv);
9029 val |= D_COMP_COMP_DISABLE;
9030 hsw_write_dcomp(dev_priv, val);
9031 ndelay(100);
9032
9033 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9034 1))
9035 DRM_ERROR("D_COMP RCOMP still in progress\n");
9036
9037 if (allow_power_down) {
9038 val = I915_READ(LCPLL_CTL);
9039 val |= LCPLL_POWER_DOWN_ALLOW;
9040 I915_WRITE(LCPLL_CTL, val);
9041 POSTING_READ(LCPLL_CTL);
9042 }
9043 }
9044
9045 /*
9046 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9047 * source.
9048 */
9049 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9050 {
9051 uint32_t val;
9052
9053 val = I915_READ(LCPLL_CTL);
9054
9055 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9056 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9057 return;
9058
9059 /*
9060 * Make sure we're not on PC8 state before disabling PC8, otherwise
9061 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9062 */
9063 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9064
9065 if (val & LCPLL_POWER_DOWN_ALLOW) {
9066 val &= ~LCPLL_POWER_DOWN_ALLOW;
9067 I915_WRITE(LCPLL_CTL, val);
9068 POSTING_READ(LCPLL_CTL);
9069 }
9070
9071 val = hsw_read_dcomp(dev_priv);
9072 val |= D_COMP_COMP_FORCE;
9073 val &= ~D_COMP_COMP_DISABLE;
9074 hsw_write_dcomp(dev_priv, val);
9075
9076 val = I915_READ(LCPLL_CTL);
9077 val &= ~LCPLL_PLL_DISABLE;
9078 I915_WRITE(LCPLL_CTL, val);
9079
9080 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9081 DRM_ERROR("LCPLL not locked yet\n");
9082
9083 if (val & LCPLL_CD_SOURCE_FCLK) {
9084 val = I915_READ(LCPLL_CTL);
9085 val &= ~LCPLL_CD_SOURCE_FCLK;
9086 I915_WRITE(LCPLL_CTL, val);
9087
9088 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9089 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9090 DRM_ERROR("Switching back to LCPLL failed\n");
9091 }
9092
9093 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9094 }
9095
9096 /*
9097 * Package states C8 and deeper are really deep PC states that can only be
9098 * reached when all the devices on the system allow it, so even if the graphics
9099 * device allows PC8+, it doesn't mean the system will actually get to these
9100 * states. Our driver only allows PC8+ when going into runtime PM.
9101 *
9102 * The requirements for PC8+ are that all the outputs are disabled, the power
9103 * well is disabled and most interrupts are disabled, and these are also
9104 * requirements for runtime PM. When these conditions are met, we manually do
9105 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9106 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9107 * hang the machine.
9108 *
9109 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9110 * the state of some registers, so when we come back from PC8+ we need to
9111 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9112 * need to take care of the registers kept by RC6. Notice that this happens even
9113 * if we don't put the device in PCI D3 state (which is what currently happens
9114 * because of the runtime PM support).
9115 *
9116 * For more, read "Display Sequences for Package C8" on the hardware
9117 * documentation.
9118 */
9119 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9120 {
9121 struct drm_device *dev = dev_priv->dev;
9122 uint32_t val;
9123
9124 DRM_DEBUG_KMS("Enabling package C8+\n");
9125
9126 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9127 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9128 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9129 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9130 }
9131
9132 lpt_disable_clkout_dp(dev);
9133 hsw_disable_lcpll(dev_priv, true, true);
9134 }
9135
9136 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9137 {
9138 struct drm_device *dev = dev_priv->dev;
9139 uint32_t val;
9140
9141 DRM_DEBUG_KMS("Disabling package C8+\n");
9142
9143 hsw_restore_lcpll(dev_priv);
9144 lpt_init_pch_refclk(dev);
9145
9146 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9147 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9148 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9149 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9150 }
9151
9152 intel_prepare_ddi(dev);
9153 }
9154
9155 static void broxton_modeset_global_resources(struct drm_atomic_state *state)
9156 {
9157 struct drm_device *dev = state->dev;
9158 struct drm_i915_private *dev_priv = dev->dev_private;
9159 int max_pixclk = intel_mode_max_pixclk(state);
9160 int req_cdclk;
9161
9162 /* see the comment in valleyview_modeset_global_resources */
9163 if (WARN_ON(max_pixclk < 0))
9164 return;
9165
9166 req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
9167
9168 if (req_cdclk != dev_priv->cdclk_freq)
9169 broxton_set_cdclk(dev, req_cdclk);
9170 }
9171
9172 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9173 struct intel_crtc_state *crtc_state)
9174 {
9175 if (!intel_ddi_pll_select(crtc, crtc_state))
9176 return -EINVAL;
9177
9178 crtc->lowfreq_avail = false;
9179
9180 return 0;
9181 }
9182
9183 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9184 enum port port,
9185 struct intel_crtc_state *pipe_config)
9186 {
9187 switch (port) {
9188 case PORT_A:
9189 pipe_config->ddi_pll_sel = SKL_DPLL0;
9190 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9191 break;
9192 case PORT_B:
9193 pipe_config->ddi_pll_sel = SKL_DPLL1;
9194 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9195 break;
9196 case PORT_C:
9197 pipe_config->ddi_pll_sel = SKL_DPLL2;
9198 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9199 break;
9200 default:
9201 DRM_ERROR("Incorrect port type\n");
9202 }
9203 }
9204
9205 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9206 enum port port,
9207 struct intel_crtc_state *pipe_config)
9208 {
9209 u32 temp, dpll_ctl1;
9210
9211 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9212 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9213
9214 switch (pipe_config->ddi_pll_sel) {
9215 case SKL_DPLL0:
9216 /*
9217 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9218 * of the shared DPLL framework and thus needs to be read out
9219 * separately
9220 */
9221 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9222 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9223 break;
9224 case SKL_DPLL1:
9225 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9226 break;
9227 case SKL_DPLL2:
9228 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9229 break;
9230 case SKL_DPLL3:
9231 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9232 break;
9233 }
9234 }
9235
9236 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9237 enum port port,
9238 struct intel_crtc_state *pipe_config)
9239 {
9240 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9241
9242 switch (pipe_config->ddi_pll_sel) {
9243 case PORT_CLK_SEL_WRPLL1:
9244 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9245 break;
9246 case PORT_CLK_SEL_WRPLL2:
9247 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9248 break;
9249 }
9250 }
9251
9252 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9253 struct intel_crtc_state *pipe_config)
9254 {
9255 struct drm_device *dev = crtc->base.dev;
9256 struct drm_i915_private *dev_priv = dev->dev_private;
9257 struct intel_shared_dpll *pll;
9258 enum port port;
9259 uint32_t tmp;
9260
9261 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9262
9263 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9264
9265 if (IS_SKYLAKE(dev))
9266 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9267 else if (IS_BROXTON(dev))
9268 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9269 else
9270 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9271
9272 if (pipe_config->shared_dpll >= 0) {
9273 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9274
9275 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9276 &pipe_config->dpll_hw_state));
9277 }
9278
9279 /*
9280 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9281 * DDI E. So just check whether this pipe is wired to DDI E and whether
9282 * the PCH transcoder is on.
9283 */
9284 if (INTEL_INFO(dev)->gen < 9 &&
9285 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9286 pipe_config->has_pch_encoder = true;
9287
9288 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9289 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9290 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9291
9292 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9293 }
9294 }
9295
9296 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9297 struct intel_crtc_state *pipe_config)
9298 {
9299 struct drm_device *dev = crtc->base.dev;
9300 struct drm_i915_private *dev_priv = dev->dev_private;
9301 enum intel_display_power_domain pfit_domain;
9302 uint32_t tmp;
9303
9304 if (!intel_display_power_is_enabled(dev_priv,
9305 POWER_DOMAIN_PIPE(crtc->pipe)))
9306 return false;
9307
9308 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9309 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9310
9311 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9312 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9313 enum pipe trans_edp_pipe;
9314 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9315 default:
9316 WARN(1, "unknown pipe linked to edp transcoder\n");
9317 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9318 case TRANS_DDI_EDP_INPUT_A_ON:
9319 trans_edp_pipe = PIPE_A;
9320 break;
9321 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9322 trans_edp_pipe = PIPE_B;
9323 break;
9324 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9325 trans_edp_pipe = PIPE_C;
9326 break;
9327 }
9328
9329 if (trans_edp_pipe == crtc->pipe)
9330 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9331 }
9332
9333 if (!intel_display_power_is_enabled(dev_priv,
9334 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9335 return false;
9336
9337 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9338 if (!(tmp & PIPECONF_ENABLE))
9339 return false;
9340
9341 haswell_get_ddi_port_state(crtc, pipe_config);
9342
9343 intel_get_pipe_timings(crtc, pipe_config);
9344
9345 if (INTEL_INFO(dev)->gen >= 9) {
9346 skl_init_scalers(dev, crtc, pipe_config);
9347 }
9348
9349 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9350 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9351 if (INTEL_INFO(dev)->gen == 9)
9352 skylake_get_pfit_config(crtc, pipe_config);
9353 else if (INTEL_INFO(dev)->gen < 9)
9354 ironlake_get_pfit_config(crtc, pipe_config);
9355 else
9356 MISSING_CASE(INTEL_INFO(dev)->gen);
9357
9358 } else {
9359 pipe_config->scaler_state.scaler_id = -1;
9360 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9361 }
9362
9363 if (IS_HASWELL(dev))
9364 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9365 (I915_READ(IPS_CTL) & IPS_ENABLE);
9366
9367 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9368 pipe_config->pixel_multiplier =
9369 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9370 } else {
9371 pipe_config->pixel_multiplier = 1;
9372 }
9373
9374 return true;
9375 }
9376
9377 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9378 {
9379 struct drm_device *dev = crtc->dev;
9380 struct drm_i915_private *dev_priv = dev->dev_private;
9381 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9382 uint32_t cntl = 0, size = 0;
9383
9384 if (base) {
9385 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9386 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9387 unsigned int stride = roundup_pow_of_two(width) * 4;
9388
9389 switch (stride) {
9390 default:
9391 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9392 width, stride);
9393 stride = 256;
9394 /* fallthrough */
9395 case 256:
9396 case 512:
9397 case 1024:
9398 case 2048:
9399 break;
9400 }
9401
9402 cntl |= CURSOR_ENABLE |
9403 CURSOR_GAMMA_ENABLE |
9404 CURSOR_FORMAT_ARGB |
9405 CURSOR_STRIDE(stride);
9406
9407 size = (height << 12) | width;
9408 }
9409
9410 if (intel_crtc->cursor_cntl != 0 &&
9411 (intel_crtc->cursor_base != base ||
9412 intel_crtc->cursor_size != size ||
9413 intel_crtc->cursor_cntl != cntl)) {
9414 /* On these chipsets we can only modify the base/size/stride
9415 * whilst the cursor is disabled.
9416 */
9417 I915_WRITE(_CURACNTR, 0);
9418 POSTING_READ(_CURACNTR);
9419 intel_crtc->cursor_cntl = 0;
9420 }
9421
9422 if (intel_crtc->cursor_base != base) {
9423 I915_WRITE(_CURABASE, base);
9424 intel_crtc->cursor_base = base;
9425 }
9426
9427 if (intel_crtc->cursor_size != size) {
9428 I915_WRITE(CURSIZE, size);
9429 intel_crtc->cursor_size = size;
9430 }
9431
9432 if (intel_crtc->cursor_cntl != cntl) {
9433 I915_WRITE(_CURACNTR, cntl);
9434 POSTING_READ(_CURACNTR);
9435 intel_crtc->cursor_cntl = cntl;
9436 }
9437 }
9438
9439 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9440 {
9441 struct drm_device *dev = crtc->dev;
9442 struct drm_i915_private *dev_priv = dev->dev_private;
9443 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9444 int pipe = intel_crtc->pipe;
9445 uint32_t cntl;
9446
9447 cntl = 0;
9448 if (base) {
9449 cntl = MCURSOR_GAMMA_ENABLE;
9450 switch (intel_crtc->base.cursor->state->crtc_w) {
9451 case 64:
9452 cntl |= CURSOR_MODE_64_ARGB_AX;
9453 break;
9454 case 128:
9455 cntl |= CURSOR_MODE_128_ARGB_AX;
9456 break;
9457 case 256:
9458 cntl |= CURSOR_MODE_256_ARGB_AX;
9459 break;
9460 default:
9461 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
9462 return;
9463 }
9464 cntl |= pipe << 28; /* Connect to correct pipe */
9465
9466 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9467 cntl |= CURSOR_PIPE_CSC_ENABLE;
9468 }
9469
9470 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
9471 cntl |= CURSOR_ROTATE_180;
9472
9473 if (intel_crtc->cursor_cntl != cntl) {
9474 I915_WRITE(CURCNTR(pipe), cntl);
9475 POSTING_READ(CURCNTR(pipe));
9476 intel_crtc->cursor_cntl = cntl;
9477 }
9478
9479 /* and commit changes on next vblank */
9480 I915_WRITE(CURBASE(pipe), base);
9481 POSTING_READ(CURBASE(pipe));
9482
9483 intel_crtc->cursor_base = base;
9484 }
9485
9486 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9487 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9488 bool on)
9489 {
9490 struct drm_device *dev = crtc->dev;
9491 struct drm_i915_private *dev_priv = dev->dev_private;
9492 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9493 int pipe = intel_crtc->pipe;
9494 int x = crtc->cursor_x;
9495 int y = crtc->cursor_y;
9496 u32 base = 0, pos = 0;
9497
9498 if (on)
9499 base = intel_crtc->cursor_addr;
9500
9501 if (x >= intel_crtc->config->pipe_src_w)
9502 base = 0;
9503
9504 if (y >= intel_crtc->config->pipe_src_h)
9505 base = 0;
9506
9507 if (x < 0) {
9508 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
9509 base = 0;
9510
9511 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9512 x = -x;
9513 }
9514 pos |= x << CURSOR_X_SHIFT;
9515
9516 if (y < 0) {
9517 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
9518 base = 0;
9519
9520 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9521 y = -y;
9522 }
9523 pos |= y << CURSOR_Y_SHIFT;
9524
9525 if (base == 0 && intel_crtc->cursor_base == 0)
9526 return;
9527
9528 I915_WRITE(CURPOS(pipe), pos);
9529
9530 /* ILK+ do this automagically */
9531 if (HAS_GMCH_DISPLAY(dev) &&
9532 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
9533 base += (intel_crtc->base.cursor->state->crtc_h *
9534 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
9535 }
9536
9537 if (IS_845G(dev) || IS_I865G(dev))
9538 i845_update_cursor(crtc, base);
9539 else
9540 i9xx_update_cursor(crtc, base);
9541 }
9542
9543 static bool cursor_size_ok(struct drm_device *dev,
9544 uint32_t width, uint32_t height)
9545 {
9546 if (width == 0 || height == 0)
9547 return false;
9548
9549 /*
9550 * 845g/865g are special in that they are only limited by
9551 * the width of their cursors, the height is arbitrary up to
9552 * the precision of the register. Everything else requires
9553 * square cursors, limited to a few power-of-two sizes.
9554 */
9555 if (IS_845G(dev) || IS_I865G(dev)) {
9556 if ((width & 63) != 0)
9557 return false;
9558
9559 if (width > (IS_845G(dev) ? 64 : 512))
9560 return false;
9561
9562 if (height > 1023)
9563 return false;
9564 } else {
9565 switch (width | height) {
9566 case 256:
9567 case 128:
9568 if (IS_GEN2(dev))
9569 return false;
9570 case 64:
9571 break;
9572 default:
9573 return false;
9574 }
9575 }
9576
9577 return true;
9578 }
9579
9580 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
9581 u16 *blue, uint32_t start, uint32_t size)
9582 {
9583 int end = (start + size > 256) ? 256 : start + size, i;
9584 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9585
9586 for (i = start; i < end; i++) {
9587 intel_crtc->lut_r[i] = red[i] >> 8;
9588 intel_crtc->lut_g[i] = green[i] >> 8;
9589 intel_crtc->lut_b[i] = blue[i] >> 8;
9590 }
9591
9592 intel_crtc_load_lut(crtc);
9593 }
9594
9595 /* VESA 640x480x72Hz mode to set on the pipe */
9596 static struct drm_display_mode load_detect_mode = {
9597 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9598 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9599 };
9600
9601 struct drm_framebuffer *
9602 __intel_framebuffer_create(struct drm_device *dev,
9603 struct drm_mode_fb_cmd2 *mode_cmd,
9604 struct drm_i915_gem_object *obj)
9605 {
9606 struct intel_framebuffer *intel_fb;
9607 int ret;
9608
9609 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9610 if (!intel_fb) {
9611 drm_gem_object_unreference(&obj->base);
9612 return ERR_PTR(-ENOMEM);
9613 }
9614
9615 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
9616 if (ret)
9617 goto err;
9618
9619 return &intel_fb->base;
9620 err:
9621 drm_gem_object_unreference(&obj->base);
9622 kfree(intel_fb);
9623
9624 return ERR_PTR(ret);
9625 }
9626
9627 static struct drm_framebuffer *
9628 intel_framebuffer_create(struct drm_device *dev,
9629 struct drm_mode_fb_cmd2 *mode_cmd,
9630 struct drm_i915_gem_object *obj)
9631 {
9632 struct drm_framebuffer *fb;
9633 int ret;
9634
9635 ret = i915_mutex_lock_interruptible(dev);
9636 if (ret)
9637 return ERR_PTR(ret);
9638 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
9639 mutex_unlock(&dev->struct_mutex);
9640
9641 return fb;
9642 }
9643
9644 static u32
9645 intel_framebuffer_pitch_for_width(int width, int bpp)
9646 {
9647 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9648 return ALIGN(pitch, 64);
9649 }
9650
9651 static u32
9652 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9653 {
9654 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
9655 return PAGE_ALIGN(pitch * mode->vdisplay);
9656 }
9657
9658 static struct drm_framebuffer *
9659 intel_framebuffer_create_for_mode(struct drm_device *dev,
9660 struct drm_display_mode *mode,
9661 int depth, int bpp)
9662 {
9663 struct drm_i915_gem_object *obj;
9664 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
9665
9666 obj = i915_gem_alloc_object(dev,
9667 intel_framebuffer_size_for_mode(mode, bpp));
9668 if (obj == NULL)
9669 return ERR_PTR(-ENOMEM);
9670
9671 mode_cmd.width = mode->hdisplay;
9672 mode_cmd.height = mode->vdisplay;
9673 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9674 bpp);
9675 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
9676
9677 return intel_framebuffer_create(dev, &mode_cmd, obj);
9678 }
9679
9680 static struct drm_framebuffer *
9681 mode_fits_in_fbdev(struct drm_device *dev,
9682 struct drm_display_mode *mode)
9683 {
9684 #ifdef CONFIG_DRM_I915_FBDEV
9685 struct drm_i915_private *dev_priv = dev->dev_private;
9686 struct drm_i915_gem_object *obj;
9687 struct drm_framebuffer *fb;
9688
9689 if (!dev_priv->fbdev)
9690 return NULL;
9691
9692 if (!dev_priv->fbdev->fb)
9693 return NULL;
9694
9695 obj = dev_priv->fbdev->fb->obj;
9696 BUG_ON(!obj);
9697
9698 fb = &dev_priv->fbdev->fb->base;
9699 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9700 fb->bits_per_pixel))
9701 return NULL;
9702
9703 if (obj->base.size < mode->vdisplay * fb->pitches[0])
9704 return NULL;
9705
9706 return fb;
9707 #else
9708 return NULL;
9709 #endif
9710 }
9711
9712 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9713 struct drm_crtc *crtc,
9714 struct drm_display_mode *mode,
9715 struct drm_framebuffer *fb,
9716 int x, int y)
9717 {
9718 struct drm_plane_state *plane_state;
9719 int hdisplay, vdisplay;
9720 int ret;
9721
9722 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
9723 if (IS_ERR(plane_state))
9724 return PTR_ERR(plane_state);
9725
9726 if (mode)
9727 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
9728 else
9729 hdisplay = vdisplay = 0;
9730
9731 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
9732 if (ret)
9733 return ret;
9734 drm_atomic_set_fb_for_plane(plane_state, fb);
9735 plane_state->crtc_x = 0;
9736 plane_state->crtc_y = 0;
9737 plane_state->crtc_w = hdisplay;
9738 plane_state->crtc_h = vdisplay;
9739 plane_state->src_x = x << 16;
9740 plane_state->src_y = y << 16;
9741 plane_state->src_w = hdisplay << 16;
9742 plane_state->src_h = vdisplay << 16;
9743
9744 return 0;
9745 }
9746
9747 bool intel_get_load_detect_pipe(struct drm_connector *connector,
9748 struct drm_display_mode *mode,
9749 struct intel_load_detect_pipe *old,
9750 struct drm_modeset_acquire_ctx *ctx)
9751 {
9752 struct intel_crtc *intel_crtc;
9753 struct intel_encoder *intel_encoder =
9754 intel_attached_encoder(connector);
9755 struct drm_crtc *possible_crtc;
9756 struct drm_encoder *encoder = &intel_encoder->base;
9757 struct drm_crtc *crtc = NULL;
9758 struct drm_device *dev = encoder->dev;
9759 struct drm_framebuffer *fb;
9760 struct drm_mode_config *config = &dev->mode_config;
9761 struct drm_atomic_state *state = NULL;
9762 struct drm_connector_state *connector_state;
9763 struct intel_crtc_state *crtc_state;
9764 int ret, i = -1;
9765
9766 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9767 connector->base.id, connector->name,
9768 encoder->base.id, encoder->name);
9769
9770 retry:
9771 ret = drm_modeset_lock(&config->connection_mutex, ctx);
9772 if (ret)
9773 goto fail_unlock;
9774
9775 /*
9776 * Algorithm gets a little messy:
9777 *
9778 * - if the connector already has an assigned crtc, use it (but make
9779 * sure it's on first)
9780 *
9781 * - try to find the first unused crtc that can drive this connector,
9782 * and use that if we find one
9783 */
9784
9785 /* See if we already have a CRTC for this connector */
9786 if (encoder->crtc) {
9787 crtc = encoder->crtc;
9788
9789 ret = drm_modeset_lock(&crtc->mutex, ctx);
9790 if (ret)
9791 goto fail_unlock;
9792 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9793 if (ret)
9794 goto fail_unlock;
9795
9796 old->dpms_mode = connector->dpms;
9797 old->load_detect_temp = false;
9798
9799 /* Make sure the crtc and connector are running */
9800 if (connector->dpms != DRM_MODE_DPMS_ON)
9801 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
9802
9803 return true;
9804 }
9805
9806 /* Find an unused one (if possible) */
9807 for_each_crtc(dev, possible_crtc) {
9808 i++;
9809 if (!(encoder->possible_crtcs & (1 << i)))
9810 continue;
9811 if (possible_crtc->state->enable)
9812 continue;
9813 /* This can occur when applying the pipe A quirk on resume. */
9814 if (to_intel_crtc(possible_crtc)->new_enabled)
9815 continue;
9816
9817 crtc = possible_crtc;
9818 break;
9819 }
9820
9821 /*
9822 * If we didn't find an unused CRTC, don't use any.
9823 */
9824 if (!crtc) {
9825 DRM_DEBUG_KMS("no pipe available for load-detect\n");
9826 goto fail_unlock;
9827 }
9828
9829 ret = drm_modeset_lock(&crtc->mutex, ctx);
9830 if (ret)
9831 goto fail_unlock;
9832 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9833 if (ret)
9834 goto fail_unlock;
9835 intel_encoder->new_crtc = to_intel_crtc(crtc);
9836 to_intel_connector(connector)->new_encoder = intel_encoder;
9837
9838 intel_crtc = to_intel_crtc(crtc);
9839 intel_crtc->new_enabled = true;
9840 old->dpms_mode = connector->dpms;
9841 old->load_detect_temp = true;
9842 old->release_fb = NULL;
9843
9844 state = drm_atomic_state_alloc(dev);
9845 if (!state)
9846 return false;
9847
9848 state->acquire_ctx = ctx;
9849
9850 connector_state = drm_atomic_get_connector_state(state, connector);
9851 if (IS_ERR(connector_state)) {
9852 ret = PTR_ERR(connector_state);
9853 goto fail;
9854 }
9855
9856 connector_state->crtc = crtc;
9857 connector_state->best_encoder = &intel_encoder->base;
9858
9859 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9860 if (IS_ERR(crtc_state)) {
9861 ret = PTR_ERR(crtc_state);
9862 goto fail;
9863 }
9864
9865 crtc_state->base.enable = true;
9866
9867 if (!mode)
9868 mode = &load_detect_mode;
9869
9870 /* We need a framebuffer large enough to accommodate all accesses
9871 * that the plane may generate whilst we perform load detection.
9872 * We can not rely on the fbcon either being present (we get called
9873 * during its initialisation to detect all boot displays, or it may
9874 * not even exist) or that it is large enough to satisfy the
9875 * requested mode.
9876 */
9877 fb = mode_fits_in_fbdev(dev, mode);
9878 if (fb == NULL) {
9879 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
9880 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9881 old->release_fb = fb;
9882 } else
9883 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
9884 if (IS_ERR(fb)) {
9885 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
9886 goto fail;
9887 }
9888
9889 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
9890 if (ret)
9891 goto fail;
9892
9893 if (intel_set_mode(crtc, mode, state)) {
9894 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
9895 if (old->release_fb)
9896 old->release_fb->funcs->destroy(old->release_fb);
9897 goto fail;
9898 }
9899 crtc->primary->crtc = crtc;
9900
9901 /* let the connector get through one full cycle before testing */
9902 intel_wait_for_vblank(dev, intel_crtc->pipe);
9903 return true;
9904
9905 fail:
9906 intel_crtc->new_enabled = crtc->state->enable;
9907 fail_unlock:
9908 drm_atomic_state_free(state);
9909 state = NULL;
9910
9911 if (ret == -EDEADLK) {
9912 drm_modeset_backoff(ctx);
9913 goto retry;
9914 }
9915
9916 return false;
9917 }
9918
9919 void intel_release_load_detect_pipe(struct drm_connector *connector,
9920 struct intel_load_detect_pipe *old,
9921 struct drm_modeset_acquire_ctx *ctx)
9922 {
9923 struct drm_device *dev = connector->dev;
9924 struct intel_encoder *intel_encoder =
9925 intel_attached_encoder(connector);
9926 struct drm_encoder *encoder = &intel_encoder->base;
9927 struct drm_crtc *crtc = encoder->crtc;
9928 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9929 struct drm_atomic_state *state;
9930 struct drm_connector_state *connector_state;
9931 struct intel_crtc_state *crtc_state;
9932 int ret;
9933
9934 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9935 connector->base.id, connector->name,
9936 encoder->base.id, encoder->name);
9937
9938 if (old->load_detect_temp) {
9939 state = drm_atomic_state_alloc(dev);
9940 if (!state)
9941 goto fail;
9942
9943 state->acquire_ctx = ctx;
9944
9945 connector_state = drm_atomic_get_connector_state(state, connector);
9946 if (IS_ERR(connector_state))
9947 goto fail;
9948
9949 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9950 if (IS_ERR(crtc_state))
9951 goto fail;
9952
9953 to_intel_connector(connector)->new_encoder = NULL;
9954 intel_encoder->new_crtc = NULL;
9955 intel_crtc->new_enabled = false;
9956
9957 connector_state->best_encoder = NULL;
9958 connector_state->crtc = NULL;
9959
9960 crtc_state->base.enable = false;
9961
9962 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
9963 0, 0);
9964 if (ret)
9965 goto fail;
9966
9967 intel_set_mode(crtc, NULL, state);
9968
9969 drm_atomic_state_free(state);
9970
9971 if (old->release_fb) {
9972 drm_framebuffer_unregister_private(old->release_fb);
9973 drm_framebuffer_unreference(old->release_fb);
9974 }
9975
9976 return;
9977 }
9978
9979 /* Switch crtc and encoder back off if necessary */
9980 if (old->dpms_mode != DRM_MODE_DPMS_ON)
9981 connector->funcs->dpms(connector, old->dpms_mode);
9982
9983 return;
9984 fail:
9985 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
9986 drm_atomic_state_free(state);
9987 }
9988
9989 static int i9xx_pll_refclk(struct drm_device *dev,
9990 const struct intel_crtc_state *pipe_config)
9991 {
9992 struct drm_i915_private *dev_priv = dev->dev_private;
9993 u32 dpll = pipe_config->dpll_hw_state.dpll;
9994
9995 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
9996 return dev_priv->vbt.lvds_ssc_freq;
9997 else if (HAS_PCH_SPLIT(dev))
9998 return 120000;
9999 else if (!IS_GEN2(dev))
10000 return 96000;
10001 else
10002 return 48000;
10003 }
10004
10005 /* Returns the clock of the currently programmed mode of the given pipe. */
10006 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10007 struct intel_crtc_state *pipe_config)
10008 {
10009 struct drm_device *dev = crtc->base.dev;
10010 struct drm_i915_private *dev_priv = dev->dev_private;
10011 int pipe = pipe_config->cpu_transcoder;
10012 u32 dpll = pipe_config->dpll_hw_state.dpll;
10013 u32 fp;
10014 intel_clock_t clock;
10015 int refclk = i9xx_pll_refclk(dev, pipe_config);
10016
10017 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10018 fp = pipe_config->dpll_hw_state.fp0;
10019 else
10020 fp = pipe_config->dpll_hw_state.fp1;
10021
10022 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10023 if (IS_PINEVIEW(dev)) {
10024 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10025 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10026 } else {
10027 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10028 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10029 }
10030
10031 if (!IS_GEN2(dev)) {
10032 if (IS_PINEVIEW(dev))
10033 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10034 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10035 else
10036 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10037 DPLL_FPA01_P1_POST_DIV_SHIFT);
10038
10039 switch (dpll & DPLL_MODE_MASK) {
10040 case DPLLB_MODE_DAC_SERIAL:
10041 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10042 5 : 10;
10043 break;
10044 case DPLLB_MODE_LVDS:
10045 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10046 7 : 14;
10047 break;
10048 default:
10049 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10050 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10051 return;
10052 }
10053
10054 if (IS_PINEVIEW(dev))
10055 pineview_clock(refclk, &clock);
10056 else
10057 i9xx_clock(refclk, &clock);
10058 } else {
10059 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10060 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10061
10062 if (is_lvds) {
10063 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10064 DPLL_FPA01_P1_POST_DIV_SHIFT);
10065
10066 if (lvds & LVDS_CLKB_POWER_UP)
10067 clock.p2 = 7;
10068 else
10069 clock.p2 = 14;
10070 } else {
10071 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10072 clock.p1 = 2;
10073 else {
10074 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10075 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10076 }
10077 if (dpll & PLL_P2_DIVIDE_BY_4)
10078 clock.p2 = 4;
10079 else
10080 clock.p2 = 2;
10081 }
10082
10083 i9xx_clock(refclk, &clock);
10084 }
10085
10086 /*
10087 * This value includes pixel_multiplier. We will use
10088 * port_clock to compute adjusted_mode.crtc_clock in the
10089 * encoder's get_config() function.
10090 */
10091 pipe_config->port_clock = clock.dot;
10092 }
10093
10094 int intel_dotclock_calculate(int link_freq,
10095 const struct intel_link_m_n *m_n)
10096 {
10097 /*
10098 * The calculation for the data clock is:
10099 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10100 * But we want to avoid losing precison if possible, so:
10101 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10102 *
10103 * and the link clock is simpler:
10104 * link_clock = (m * link_clock) / n
10105 */
10106
10107 if (!m_n->link_n)
10108 return 0;
10109
10110 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10111 }
10112
10113 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10114 struct intel_crtc_state *pipe_config)
10115 {
10116 struct drm_device *dev = crtc->base.dev;
10117
10118 /* read out port_clock from the DPLL */
10119 i9xx_crtc_clock_get(crtc, pipe_config);
10120
10121 /*
10122 * This value does not include pixel_multiplier.
10123 * We will check that port_clock and adjusted_mode.crtc_clock
10124 * agree once we know their relationship in the encoder's
10125 * get_config() function.
10126 */
10127 pipe_config->base.adjusted_mode.crtc_clock =
10128 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10129 &pipe_config->fdi_m_n);
10130 }
10131
10132 /** Returns the currently programmed mode of the given pipe. */
10133 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10134 struct drm_crtc *crtc)
10135 {
10136 struct drm_i915_private *dev_priv = dev->dev_private;
10137 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10138 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10139 struct drm_display_mode *mode;
10140 struct intel_crtc_state pipe_config;
10141 int htot = I915_READ(HTOTAL(cpu_transcoder));
10142 int hsync = I915_READ(HSYNC(cpu_transcoder));
10143 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10144 int vsync = I915_READ(VSYNC(cpu_transcoder));
10145 enum pipe pipe = intel_crtc->pipe;
10146
10147 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10148 if (!mode)
10149 return NULL;
10150
10151 /*
10152 * Construct a pipe_config sufficient for getting the clock info
10153 * back out of crtc_clock_get.
10154 *
10155 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10156 * to use a real value here instead.
10157 */
10158 pipe_config.cpu_transcoder = (enum transcoder) pipe;
10159 pipe_config.pixel_multiplier = 1;
10160 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10161 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10162 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10163 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10164
10165 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10166 mode->hdisplay = (htot & 0xffff) + 1;
10167 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10168 mode->hsync_start = (hsync & 0xffff) + 1;
10169 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10170 mode->vdisplay = (vtot & 0xffff) + 1;
10171 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10172 mode->vsync_start = (vsync & 0xffff) + 1;
10173 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10174
10175 drm_mode_set_name(mode);
10176
10177 return mode;
10178 }
10179
10180 static void intel_decrease_pllclock(struct drm_crtc *crtc)
10181 {
10182 struct drm_device *dev = crtc->dev;
10183 struct drm_i915_private *dev_priv = dev->dev_private;
10184 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10185
10186 if (!HAS_GMCH_DISPLAY(dev))
10187 return;
10188
10189 if (!dev_priv->lvds_downclock_avail)
10190 return;
10191
10192 /*
10193 * Since this is called by a timer, we should never get here in
10194 * the manual case.
10195 */
10196 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
10197 int pipe = intel_crtc->pipe;
10198 int dpll_reg = DPLL(pipe);
10199 int dpll;
10200
10201 DRM_DEBUG_DRIVER("downclocking LVDS\n");
10202
10203 assert_panel_unlocked(dev_priv, pipe);
10204
10205 dpll = I915_READ(dpll_reg);
10206 dpll |= DISPLAY_RATE_SELECT_FPA1;
10207 I915_WRITE(dpll_reg, dpll);
10208 intel_wait_for_vblank(dev, pipe);
10209 dpll = I915_READ(dpll_reg);
10210 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
10211 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
10212 }
10213
10214 }
10215
10216 void intel_mark_busy(struct drm_device *dev)
10217 {
10218 struct drm_i915_private *dev_priv = dev->dev_private;
10219
10220 if (dev_priv->mm.busy)
10221 return;
10222
10223 intel_runtime_pm_get(dev_priv);
10224 i915_update_gfx_val(dev_priv);
10225 if (INTEL_INFO(dev)->gen >= 6)
10226 gen6_rps_busy(dev_priv);
10227 dev_priv->mm.busy = true;
10228 }
10229
10230 void intel_mark_idle(struct drm_device *dev)
10231 {
10232 struct drm_i915_private *dev_priv = dev->dev_private;
10233 struct drm_crtc *crtc;
10234
10235 if (!dev_priv->mm.busy)
10236 return;
10237
10238 dev_priv->mm.busy = false;
10239
10240 for_each_crtc(dev, crtc) {
10241 if (!crtc->primary->fb)
10242 continue;
10243
10244 intel_decrease_pllclock(crtc);
10245 }
10246
10247 if (INTEL_INFO(dev)->gen >= 6)
10248 gen6_rps_idle(dev->dev_private);
10249
10250 intel_runtime_pm_put(dev_priv);
10251 }
10252
10253 static void intel_crtc_set_state(struct intel_crtc *crtc,
10254 struct intel_crtc_state *crtc_state)
10255 {
10256 kfree(crtc->config);
10257 crtc->config = crtc_state;
10258 crtc->base.state = &crtc_state->base;
10259 }
10260
10261 static void intel_crtc_destroy(struct drm_crtc *crtc)
10262 {
10263 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10264 struct drm_device *dev = crtc->dev;
10265 struct intel_unpin_work *work;
10266
10267 spin_lock_irq(&dev->event_lock);
10268 work = intel_crtc->unpin_work;
10269 intel_crtc->unpin_work = NULL;
10270 spin_unlock_irq(&dev->event_lock);
10271
10272 if (work) {
10273 cancel_work_sync(&work->work);
10274 kfree(work);
10275 }
10276
10277 intel_crtc_set_state(intel_crtc, NULL);
10278 drm_crtc_cleanup(crtc);
10279
10280 kfree(intel_crtc);
10281 }
10282
10283 static void intel_unpin_work_fn(struct work_struct *__work)
10284 {
10285 struct intel_unpin_work *work =
10286 container_of(__work, struct intel_unpin_work, work);
10287 struct drm_device *dev = work->crtc->dev;
10288 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
10289
10290 mutex_lock(&dev->struct_mutex);
10291 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
10292 drm_gem_object_unreference(&work->pending_flip_obj->base);
10293
10294 intel_fbc_update(dev);
10295
10296 if (work->flip_queued_req)
10297 i915_gem_request_assign(&work->flip_queued_req, NULL);
10298 mutex_unlock(&dev->struct_mutex);
10299
10300 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
10301 drm_framebuffer_unreference(work->old_fb);
10302
10303 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
10304 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
10305
10306 kfree(work);
10307 }
10308
10309 static void do_intel_finish_page_flip(struct drm_device *dev,
10310 struct drm_crtc *crtc)
10311 {
10312 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10313 struct intel_unpin_work *work;
10314 unsigned long flags;
10315
10316 /* Ignore early vblank irqs */
10317 if (intel_crtc == NULL)
10318 return;
10319
10320 /*
10321 * This is called both by irq handlers and the reset code (to complete
10322 * lost pageflips) so needs the full irqsave spinlocks.
10323 */
10324 spin_lock_irqsave(&dev->event_lock, flags);
10325 work = intel_crtc->unpin_work;
10326
10327 /* Ensure we don't miss a work->pending update ... */
10328 smp_rmb();
10329
10330 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10331 spin_unlock_irqrestore(&dev->event_lock, flags);
10332 return;
10333 }
10334
10335 page_flip_completed(intel_crtc);
10336
10337 spin_unlock_irqrestore(&dev->event_lock, flags);
10338 }
10339
10340 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10341 {
10342 struct drm_i915_private *dev_priv = dev->dev_private;
10343 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10344
10345 do_intel_finish_page_flip(dev, crtc);
10346 }
10347
10348 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10349 {
10350 struct drm_i915_private *dev_priv = dev->dev_private;
10351 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10352
10353 do_intel_finish_page_flip(dev, crtc);
10354 }
10355
10356 /* Is 'a' after or equal to 'b'? */
10357 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10358 {
10359 return !((a - b) & 0x80000000);
10360 }
10361
10362 static bool page_flip_finished(struct intel_crtc *crtc)
10363 {
10364 struct drm_device *dev = crtc->base.dev;
10365 struct drm_i915_private *dev_priv = dev->dev_private;
10366
10367 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10368 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10369 return true;
10370
10371 /*
10372 * The relevant registers doen't exist on pre-ctg.
10373 * As the flip done interrupt doesn't trigger for mmio
10374 * flips on gmch platforms, a flip count check isn't
10375 * really needed there. But since ctg has the registers,
10376 * include it in the check anyway.
10377 */
10378 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10379 return true;
10380
10381 /*
10382 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10383 * used the same base address. In that case the mmio flip might
10384 * have completed, but the CS hasn't even executed the flip yet.
10385 *
10386 * A flip count check isn't enough as the CS might have updated
10387 * the base address just after start of vblank, but before we
10388 * managed to process the interrupt. This means we'd complete the
10389 * CS flip too soon.
10390 *
10391 * Combining both checks should get us a good enough result. It may
10392 * still happen that the CS flip has been executed, but has not
10393 * yet actually completed. But in case the base address is the same
10394 * anyway, we don't really care.
10395 */
10396 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10397 crtc->unpin_work->gtt_offset &&
10398 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10399 crtc->unpin_work->flip_count);
10400 }
10401
10402 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10403 {
10404 struct drm_i915_private *dev_priv = dev->dev_private;
10405 struct intel_crtc *intel_crtc =
10406 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10407 unsigned long flags;
10408
10409
10410 /*
10411 * This is called both by irq handlers and the reset code (to complete
10412 * lost pageflips) so needs the full irqsave spinlocks.
10413 *
10414 * NB: An MMIO update of the plane base pointer will also
10415 * generate a page-flip completion irq, i.e. every modeset
10416 * is also accompanied by a spurious intel_prepare_page_flip().
10417 */
10418 spin_lock_irqsave(&dev->event_lock, flags);
10419 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10420 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10421 spin_unlock_irqrestore(&dev->event_lock, flags);
10422 }
10423
10424 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
10425 {
10426 /* Ensure that the work item is consistent when activating it ... */
10427 smp_wmb();
10428 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10429 /* and that it is marked active as soon as the irq could fire. */
10430 smp_wmb();
10431 }
10432
10433 static int intel_gen2_queue_flip(struct drm_device *dev,
10434 struct drm_crtc *crtc,
10435 struct drm_framebuffer *fb,
10436 struct drm_i915_gem_object *obj,
10437 struct intel_engine_cs *ring,
10438 uint32_t flags)
10439 {
10440 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10441 u32 flip_mask;
10442 int ret;
10443
10444 ret = intel_ring_begin(ring, 6);
10445 if (ret)
10446 return ret;
10447
10448 /* Can't queue multiple flips, so wait for the previous
10449 * one to finish before executing the next.
10450 */
10451 if (intel_crtc->plane)
10452 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10453 else
10454 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10455 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10456 intel_ring_emit(ring, MI_NOOP);
10457 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10458 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10459 intel_ring_emit(ring, fb->pitches[0]);
10460 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10461 intel_ring_emit(ring, 0); /* aux display base address, unused */
10462
10463 intel_mark_page_flip_active(intel_crtc);
10464 __intel_ring_advance(ring);
10465 return 0;
10466 }
10467
10468 static int intel_gen3_queue_flip(struct drm_device *dev,
10469 struct drm_crtc *crtc,
10470 struct drm_framebuffer *fb,
10471 struct drm_i915_gem_object *obj,
10472 struct intel_engine_cs *ring,
10473 uint32_t flags)
10474 {
10475 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10476 u32 flip_mask;
10477 int ret;
10478
10479 ret = intel_ring_begin(ring, 6);
10480 if (ret)
10481 return ret;
10482
10483 if (intel_crtc->plane)
10484 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10485 else
10486 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10487 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10488 intel_ring_emit(ring, MI_NOOP);
10489 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10490 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10491 intel_ring_emit(ring, fb->pitches[0]);
10492 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10493 intel_ring_emit(ring, MI_NOOP);
10494
10495 intel_mark_page_flip_active(intel_crtc);
10496 __intel_ring_advance(ring);
10497 return 0;
10498 }
10499
10500 static int intel_gen4_queue_flip(struct drm_device *dev,
10501 struct drm_crtc *crtc,
10502 struct drm_framebuffer *fb,
10503 struct drm_i915_gem_object *obj,
10504 struct intel_engine_cs *ring,
10505 uint32_t flags)
10506 {
10507 struct drm_i915_private *dev_priv = dev->dev_private;
10508 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10509 uint32_t pf, pipesrc;
10510 int ret;
10511
10512 ret = intel_ring_begin(ring, 4);
10513 if (ret)
10514 return ret;
10515
10516 /* i965+ uses the linear or tiled offsets from the
10517 * Display Registers (which do not change across a page-flip)
10518 * so we need only reprogram the base address.
10519 */
10520 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10521 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10522 intel_ring_emit(ring, fb->pitches[0]);
10523 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
10524 obj->tiling_mode);
10525
10526 /* XXX Enabling the panel-fitter across page-flip is so far
10527 * untested on non-native modes, so ignore it for now.
10528 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10529 */
10530 pf = 0;
10531 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10532 intel_ring_emit(ring, pf | pipesrc);
10533
10534 intel_mark_page_flip_active(intel_crtc);
10535 __intel_ring_advance(ring);
10536 return 0;
10537 }
10538
10539 static int intel_gen6_queue_flip(struct drm_device *dev,
10540 struct drm_crtc *crtc,
10541 struct drm_framebuffer *fb,
10542 struct drm_i915_gem_object *obj,
10543 struct intel_engine_cs *ring,
10544 uint32_t flags)
10545 {
10546 struct drm_i915_private *dev_priv = dev->dev_private;
10547 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10548 uint32_t pf, pipesrc;
10549 int ret;
10550
10551 ret = intel_ring_begin(ring, 4);
10552 if (ret)
10553 return ret;
10554
10555 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10556 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10557 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
10558 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10559
10560 /* Contrary to the suggestions in the documentation,
10561 * "Enable Panel Fitter" does not seem to be required when page
10562 * flipping with a non-native mode, and worse causes a normal
10563 * modeset to fail.
10564 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10565 */
10566 pf = 0;
10567 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10568 intel_ring_emit(ring, pf | pipesrc);
10569
10570 intel_mark_page_flip_active(intel_crtc);
10571 __intel_ring_advance(ring);
10572 return 0;
10573 }
10574
10575 static int intel_gen7_queue_flip(struct drm_device *dev,
10576 struct drm_crtc *crtc,
10577 struct drm_framebuffer *fb,
10578 struct drm_i915_gem_object *obj,
10579 struct intel_engine_cs *ring,
10580 uint32_t flags)
10581 {
10582 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10583 uint32_t plane_bit = 0;
10584 int len, ret;
10585
10586 switch (intel_crtc->plane) {
10587 case PLANE_A:
10588 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10589 break;
10590 case PLANE_B:
10591 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10592 break;
10593 case PLANE_C:
10594 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10595 break;
10596 default:
10597 WARN_ONCE(1, "unknown plane in flip command\n");
10598 return -ENODEV;
10599 }
10600
10601 len = 4;
10602 if (ring->id == RCS) {
10603 len += 6;
10604 /*
10605 * On Gen 8, SRM is now taking an extra dword to accommodate
10606 * 48bits addresses, and we need a NOOP for the batch size to
10607 * stay even.
10608 */
10609 if (IS_GEN8(dev))
10610 len += 2;
10611 }
10612
10613 /*
10614 * BSpec MI_DISPLAY_FLIP for IVB:
10615 * "The full packet must be contained within the same cache line."
10616 *
10617 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10618 * cacheline, if we ever start emitting more commands before
10619 * the MI_DISPLAY_FLIP we may need to first emit everything else,
10620 * then do the cacheline alignment, and finally emit the
10621 * MI_DISPLAY_FLIP.
10622 */
10623 ret = intel_ring_cacheline_align(ring);
10624 if (ret)
10625 return ret;
10626
10627 ret = intel_ring_begin(ring, len);
10628 if (ret)
10629 return ret;
10630
10631 /* Unmask the flip-done completion message. Note that the bspec says that
10632 * we should do this for both the BCS and RCS, and that we must not unmask
10633 * more than one flip event at any time (or ensure that one flip message
10634 * can be sent by waiting for flip-done prior to queueing new flips).
10635 * Experimentation says that BCS works despite DERRMR masking all
10636 * flip-done completion events and that unmasking all planes at once
10637 * for the RCS also doesn't appear to drop events. Setting the DERRMR
10638 * to zero does lead to lockups within MI_DISPLAY_FLIP.
10639 */
10640 if (ring->id == RCS) {
10641 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
10642 intel_ring_emit(ring, DERRMR);
10643 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
10644 DERRMR_PIPEB_PRI_FLIP_DONE |
10645 DERRMR_PIPEC_PRI_FLIP_DONE));
10646 if (IS_GEN8(dev))
10647 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
10648 MI_SRM_LRM_GLOBAL_GTT);
10649 else
10650 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
10651 MI_SRM_LRM_GLOBAL_GTT);
10652 intel_ring_emit(ring, DERRMR);
10653 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
10654 if (IS_GEN8(dev)) {
10655 intel_ring_emit(ring, 0);
10656 intel_ring_emit(ring, MI_NOOP);
10657 }
10658 }
10659
10660 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
10661 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
10662 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10663 intel_ring_emit(ring, (MI_NOOP));
10664
10665 intel_mark_page_flip_active(intel_crtc);
10666 __intel_ring_advance(ring);
10667 return 0;
10668 }
10669
10670 static bool use_mmio_flip(struct intel_engine_cs *ring,
10671 struct drm_i915_gem_object *obj)
10672 {
10673 /*
10674 * This is not being used for older platforms, because
10675 * non-availability of flip done interrupt forces us to use
10676 * CS flips. Older platforms derive flip done using some clever
10677 * tricks involving the flip_pending status bits and vblank irqs.
10678 * So using MMIO flips there would disrupt this mechanism.
10679 */
10680
10681 if (ring == NULL)
10682 return true;
10683
10684 if (INTEL_INFO(ring->dev)->gen < 5)
10685 return false;
10686
10687 if (i915.use_mmio_flip < 0)
10688 return false;
10689 else if (i915.use_mmio_flip > 0)
10690 return true;
10691 else if (i915.enable_execlists)
10692 return true;
10693 else
10694 return ring != i915_gem_request_get_ring(obj->last_read_req);
10695 }
10696
10697 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
10698 {
10699 struct drm_device *dev = intel_crtc->base.dev;
10700 struct drm_i915_private *dev_priv = dev->dev_private;
10701 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
10702 const enum pipe pipe = intel_crtc->pipe;
10703 u32 ctl, stride;
10704
10705 ctl = I915_READ(PLANE_CTL(pipe, 0));
10706 ctl &= ~PLANE_CTL_TILED_MASK;
10707 switch (fb->modifier[0]) {
10708 case DRM_FORMAT_MOD_NONE:
10709 break;
10710 case I915_FORMAT_MOD_X_TILED:
10711 ctl |= PLANE_CTL_TILED_X;
10712 break;
10713 case I915_FORMAT_MOD_Y_TILED:
10714 ctl |= PLANE_CTL_TILED_Y;
10715 break;
10716 case I915_FORMAT_MOD_Yf_TILED:
10717 ctl |= PLANE_CTL_TILED_YF;
10718 break;
10719 default:
10720 MISSING_CASE(fb->modifier[0]);
10721 }
10722
10723 /*
10724 * The stride is either expressed as a multiple of 64 bytes chunks for
10725 * linear buffers or in number of tiles for tiled buffers.
10726 */
10727 stride = fb->pitches[0] /
10728 intel_fb_stride_alignment(dev, fb->modifier[0],
10729 fb->pixel_format);
10730
10731 /*
10732 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10733 * PLANE_SURF updates, the update is then guaranteed to be atomic.
10734 */
10735 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
10736 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
10737
10738 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
10739 POSTING_READ(PLANE_SURF(pipe, 0));
10740 }
10741
10742 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
10743 {
10744 struct drm_device *dev = intel_crtc->base.dev;
10745 struct drm_i915_private *dev_priv = dev->dev_private;
10746 struct intel_framebuffer *intel_fb =
10747 to_intel_framebuffer(intel_crtc->base.primary->fb);
10748 struct drm_i915_gem_object *obj = intel_fb->obj;
10749 u32 dspcntr;
10750 u32 reg;
10751
10752 reg = DSPCNTR(intel_crtc->plane);
10753 dspcntr = I915_READ(reg);
10754
10755 if (obj->tiling_mode != I915_TILING_NONE)
10756 dspcntr |= DISPPLANE_TILED;
10757 else
10758 dspcntr &= ~DISPPLANE_TILED;
10759
10760 I915_WRITE(reg, dspcntr);
10761
10762 I915_WRITE(DSPSURF(intel_crtc->plane),
10763 intel_crtc->unpin_work->gtt_offset);
10764 POSTING_READ(DSPSURF(intel_crtc->plane));
10765
10766 }
10767
10768 /*
10769 * XXX: This is the temporary way to update the plane registers until we get
10770 * around to using the usual plane update functions for MMIO flips
10771 */
10772 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
10773 {
10774 struct drm_device *dev = intel_crtc->base.dev;
10775 bool atomic_update;
10776 u32 start_vbl_count;
10777
10778 intel_mark_page_flip_active(intel_crtc);
10779
10780 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
10781
10782 if (INTEL_INFO(dev)->gen >= 9)
10783 skl_do_mmio_flip(intel_crtc);
10784 else
10785 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10786 ilk_do_mmio_flip(intel_crtc);
10787
10788 if (atomic_update)
10789 intel_pipe_update_end(intel_crtc, start_vbl_count);
10790 }
10791
10792 static void intel_mmio_flip_work_func(struct work_struct *work)
10793 {
10794 struct intel_crtc *crtc =
10795 container_of(work, struct intel_crtc, mmio_flip.work);
10796 struct intel_mmio_flip *mmio_flip;
10797
10798 mmio_flip = &crtc->mmio_flip;
10799 if (mmio_flip->req)
10800 WARN_ON(__i915_wait_request(mmio_flip->req,
10801 crtc->reset_counter,
10802 false, NULL, NULL) != 0);
10803
10804 intel_do_mmio_flip(crtc);
10805 if (mmio_flip->req) {
10806 mutex_lock(&crtc->base.dev->struct_mutex);
10807 i915_gem_request_assign(&mmio_flip->req, NULL);
10808 mutex_unlock(&crtc->base.dev->struct_mutex);
10809 }
10810 }
10811
10812 static int intel_queue_mmio_flip(struct drm_device *dev,
10813 struct drm_crtc *crtc,
10814 struct drm_framebuffer *fb,
10815 struct drm_i915_gem_object *obj,
10816 struct intel_engine_cs *ring,
10817 uint32_t flags)
10818 {
10819 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10820
10821 i915_gem_request_assign(&intel_crtc->mmio_flip.req,
10822 obj->last_write_req);
10823
10824 schedule_work(&intel_crtc->mmio_flip.work);
10825
10826 return 0;
10827 }
10828
10829 static int intel_default_queue_flip(struct drm_device *dev,
10830 struct drm_crtc *crtc,
10831 struct drm_framebuffer *fb,
10832 struct drm_i915_gem_object *obj,
10833 struct intel_engine_cs *ring,
10834 uint32_t flags)
10835 {
10836 return -ENODEV;
10837 }
10838
10839 static bool __intel_pageflip_stall_check(struct drm_device *dev,
10840 struct drm_crtc *crtc)
10841 {
10842 struct drm_i915_private *dev_priv = dev->dev_private;
10843 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10844 struct intel_unpin_work *work = intel_crtc->unpin_work;
10845 u32 addr;
10846
10847 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
10848 return true;
10849
10850 if (!work->enable_stall_check)
10851 return false;
10852
10853 if (work->flip_ready_vblank == 0) {
10854 if (work->flip_queued_req &&
10855 !i915_gem_request_completed(work->flip_queued_req, true))
10856 return false;
10857
10858 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
10859 }
10860
10861 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
10862 return false;
10863
10864 /* Potential stall - if we see that the flip has happened,
10865 * assume a missed interrupt. */
10866 if (INTEL_INFO(dev)->gen >= 4)
10867 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
10868 else
10869 addr = I915_READ(DSPADDR(intel_crtc->plane));
10870
10871 /* There is a potential issue here with a false positive after a flip
10872 * to the same address. We could address this by checking for a
10873 * non-incrementing frame counter.
10874 */
10875 return addr == work->gtt_offset;
10876 }
10877
10878 void intel_check_page_flip(struct drm_device *dev, int pipe)
10879 {
10880 struct drm_i915_private *dev_priv = dev->dev_private;
10881 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10882 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10883 struct intel_unpin_work *work;
10884
10885 WARN_ON(!in_interrupt());
10886
10887 if (crtc == NULL)
10888 return;
10889
10890 spin_lock(&dev->event_lock);
10891 work = intel_crtc->unpin_work;
10892 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
10893 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
10894 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
10895 page_flip_completed(intel_crtc);
10896 work = NULL;
10897 }
10898 if (work != NULL &&
10899 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
10900 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
10901 spin_unlock(&dev->event_lock);
10902 }
10903
10904 static int intel_crtc_page_flip(struct drm_crtc *crtc,
10905 struct drm_framebuffer *fb,
10906 struct drm_pending_vblank_event *event,
10907 uint32_t page_flip_flags)
10908 {
10909 struct drm_device *dev = crtc->dev;
10910 struct drm_i915_private *dev_priv = dev->dev_private;
10911 struct drm_framebuffer *old_fb = crtc->primary->fb;
10912 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10913 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10914 struct drm_plane *primary = crtc->primary;
10915 enum pipe pipe = intel_crtc->pipe;
10916 struct intel_unpin_work *work;
10917 struct intel_engine_cs *ring;
10918 bool mmio_flip;
10919 int ret;
10920
10921 /*
10922 * drm_mode_page_flip_ioctl() should already catch this, but double
10923 * check to be safe. In the future we may enable pageflipping from
10924 * a disabled primary plane.
10925 */
10926 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
10927 return -EBUSY;
10928
10929 /* Can't change pixel format via MI display flips. */
10930 if (fb->pixel_format != crtc->primary->fb->pixel_format)
10931 return -EINVAL;
10932
10933 /*
10934 * TILEOFF/LINOFF registers can't be changed via MI display flips.
10935 * Note that pitch changes could also affect these register.
10936 */
10937 if (INTEL_INFO(dev)->gen > 3 &&
10938 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
10939 fb->pitches[0] != crtc->primary->fb->pitches[0]))
10940 return -EINVAL;
10941
10942 if (i915_terminally_wedged(&dev_priv->gpu_error))
10943 goto out_hang;
10944
10945 work = kzalloc(sizeof(*work), GFP_KERNEL);
10946 if (work == NULL)
10947 return -ENOMEM;
10948
10949 work->event = event;
10950 work->crtc = crtc;
10951 work->old_fb = old_fb;
10952 INIT_WORK(&work->work, intel_unpin_work_fn);
10953
10954 ret = drm_crtc_vblank_get(crtc);
10955 if (ret)
10956 goto free_work;
10957
10958 /* We borrow the event spin lock for protecting unpin_work */
10959 spin_lock_irq(&dev->event_lock);
10960 if (intel_crtc->unpin_work) {
10961 /* Before declaring the flip queue wedged, check if
10962 * the hardware completed the operation behind our backs.
10963 */
10964 if (__intel_pageflip_stall_check(dev, crtc)) {
10965 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10966 page_flip_completed(intel_crtc);
10967 } else {
10968 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
10969 spin_unlock_irq(&dev->event_lock);
10970
10971 drm_crtc_vblank_put(crtc);
10972 kfree(work);
10973 return -EBUSY;
10974 }
10975 }
10976 intel_crtc->unpin_work = work;
10977 spin_unlock_irq(&dev->event_lock);
10978
10979 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
10980 flush_workqueue(dev_priv->wq);
10981
10982 /* Reference the objects for the scheduled work. */
10983 drm_framebuffer_reference(work->old_fb);
10984 drm_gem_object_reference(&obj->base);
10985
10986 crtc->primary->fb = fb;
10987 update_state_fb(crtc->primary);
10988
10989 work->pending_flip_obj = obj;
10990
10991 ret = i915_mutex_lock_interruptible(dev);
10992 if (ret)
10993 goto cleanup;
10994
10995 atomic_inc(&intel_crtc->unpin_work_count);
10996 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
10997
10998 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
10999 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
11000
11001 if (IS_VALLEYVIEW(dev)) {
11002 ring = &dev_priv->ring[BCS];
11003 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11004 /* vlv: DISPLAY_FLIP fails to change tiling */
11005 ring = NULL;
11006 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11007 ring = &dev_priv->ring[BCS];
11008 } else if (INTEL_INFO(dev)->gen >= 7) {
11009 ring = i915_gem_request_get_ring(obj->last_read_req);
11010 if (ring == NULL || ring->id != RCS)
11011 ring = &dev_priv->ring[BCS];
11012 } else {
11013 ring = &dev_priv->ring[RCS];
11014 }
11015
11016 mmio_flip = use_mmio_flip(ring, obj);
11017
11018 /* When using CS flips, we want to emit semaphores between rings.
11019 * However, when using mmio flips we will create a task to do the
11020 * synchronisation, so all we want here is to pin the framebuffer
11021 * into the display plane and skip any waits.
11022 */
11023 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11024 crtc->primary->state,
11025 mmio_flip ? i915_gem_request_get_ring(obj->last_read_req) : ring);
11026 if (ret)
11027 goto cleanup_pending;
11028
11029 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11030 + intel_crtc->dspaddr_offset;
11031
11032 if (mmio_flip) {
11033 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11034 page_flip_flags);
11035 if (ret)
11036 goto cleanup_unpin;
11037
11038 i915_gem_request_assign(&work->flip_queued_req,
11039 obj->last_write_req);
11040 } else {
11041 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
11042 page_flip_flags);
11043 if (ret)
11044 goto cleanup_unpin;
11045
11046 i915_gem_request_assign(&work->flip_queued_req,
11047 intel_ring_get_request(ring));
11048 }
11049
11050 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11051 work->enable_stall_check = true;
11052
11053 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11054 INTEL_FRONTBUFFER_PRIMARY(pipe));
11055
11056 intel_fbc_disable(dev);
11057 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
11058 mutex_unlock(&dev->struct_mutex);
11059
11060 trace_i915_flip_request(intel_crtc->plane, obj);
11061
11062 return 0;
11063
11064 cleanup_unpin:
11065 intel_unpin_fb_obj(fb, crtc->primary->state);
11066 cleanup_pending:
11067 atomic_dec(&intel_crtc->unpin_work_count);
11068 mutex_unlock(&dev->struct_mutex);
11069 cleanup:
11070 crtc->primary->fb = old_fb;
11071 update_state_fb(crtc->primary);
11072
11073 drm_gem_object_unreference_unlocked(&obj->base);
11074 drm_framebuffer_unreference(work->old_fb);
11075
11076 spin_lock_irq(&dev->event_lock);
11077 intel_crtc->unpin_work = NULL;
11078 spin_unlock_irq(&dev->event_lock);
11079
11080 drm_crtc_vblank_put(crtc);
11081 free_work:
11082 kfree(work);
11083
11084 if (ret == -EIO) {
11085 out_hang:
11086 ret = intel_plane_restore(primary);
11087 if (ret == 0 && event) {
11088 spin_lock_irq(&dev->event_lock);
11089 drm_send_vblank_event(dev, pipe, event);
11090 spin_unlock_irq(&dev->event_lock);
11091 }
11092 }
11093 return ret;
11094 }
11095
11096 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11097 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11098 .load_lut = intel_crtc_load_lut,
11099 .atomic_begin = intel_begin_crtc_commit,
11100 .atomic_flush = intel_finish_crtc_commit,
11101 };
11102
11103 /**
11104 * intel_modeset_update_staged_output_state
11105 *
11106 * Updates the staged output configuration state, e.g. after we've read out the
11107 * current hw state.
11108 */
11109 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
11110 {
11111 struct intel_crtc *crtc;
11112 struct intel_encoder *encoder;
11113 struct intel_connector *connector;
11114
11115 for_each_intel_connector(dev, connector) {
11116 connector->new_encoder =
11117 to_intel_encoder(connector->base.encoder);
11118 }
11119
11120 for_each_intel_encoder(dev, encoder) {
11121 encoder->new_crtc =
11122 to_intel_crtc(encoder->base.crtc);
11123 }
11124
11125 for_each_intel_crtc(dev, crtc) {
11126 crtc->new_enabled = crtc->base.state->enable;
11127 }
11128 }
11129
11130 /* Transitional helper to copy current connector/encoder state to
11131 * connector->state. This is needed so that code that is partially
11132 * converted to atomic does the right thing.
11133 */
11134 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11135 {
11136 struct intel_connector *connector;
11137
11138 for_each_intel_connector(dev, connector) {
11139 if (connector->base.encoder) {
11140 connector->base.state->best_encoder =
11141 connector->base.encoder;
11142 connector->base.state->crtc =
11143 connector->base.encoder->crtc;
11144 } else {
11145 connector->base.state->best_encoder = NULL;
11146 connector->base.state->crtc = NULL;
11147 }
11148 }
11149 }
11150
11151 /**
11152 * intel_modeset_commit_output_state
11153 *
11154 * This function copies the stage display pipe configuration to the real one.
11155 */
11156 static void intel_modeset_commit_output_state(struct drm_device *dev)
11157 {
11158 struct intel_crtc *crtc;
11159 struct intel_encoder *encoder;
11160 struct intel_connector *connector;
11161
11162 for_each_intel_connector(dev, connector) {
11163 connector->base.encoder = &connector->new_encoder->base;
11164 }
11165
11166 for_each_intel_encoder(dev, encoder) {
11167 encoder->base.crtc = &encoder->new_crtc->base;
11168 }
11169
11170 for_each_intel_crtc(dev, crtc) {
11171 crtc->base.state->enable = crtc->new_enabled;
11172 crtc->base.enabled = crtc->new_enabled;
11173 }
11174
11175 intel_modeset_update_connector_atomic_state(dev);
11176 }
11177
11178 static void
11179 connected_sink_compute_bpp(struct intel_connector *connector,
11180 struct intel_crtc_state *pipe_config)
11181 {
11182 int bpp = pipe_config->pipe_bpp;
11183
11184 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11185 connector->base.base.id,
11186 connector->base.name);
11187
11188 /* Don't use an invalid EDID bpc value */
11189 if (connector->base.display_info.bpc &&
11190 connector->base.display_info.bpc * 3 < bpp) {
11191 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11192 bpp, connector->base.display_info.bpc*3);
11193 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11194 }
11195
11196 /* Clamp bpp to 8 on screens without EDID 1.4 */
11197 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11198 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11199 bpp);
11200 pipe_config->pipe_bpp = 24;
11201 }
11202 }
11203
11204 static int
11205 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11206 struct intel_crtc_state *pipe_config)
11207 {
11208 struct drm_device *dev = crtc->base.dev;
11209 struct drm_atomic_state *state;
11210 struct drm_connector *connector;
11211 struct drm_connector_state *connector_state;
11212 int bpp, i;
11213
11214 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11215 bpp = 10*3;
11216 else if (INTEL_INFO(dev)->gen >= 5)
11217 bpp = 12*3;
11218 else
11219 bpp = 8*3;
11220
11221
11222 pipe_config->pipe_bpp = bpp;
11223
11224 state = pipe_config->base.state;
11225
11226 /* Clamp display bpp to EDID value */
11227 for_each_connector_in_state(state, connector, connector_state, i) {
11228 if (connector_state->crtc != &crtc->base)
11229 continue;
11230
11231 connected_sink_compute_bpp(to_intel_connector(connector),
11232 pipe_config);
11233 }
11234
11235 return bpp;
11236 }
11237
11238 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11239 {
11240 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11241 "type: 0x%x flags: 0x%x\n",
11242 mode->crtc_clock,
11243 mode->crtc_hdisplay, mode->crtc_hsync_start,
11244 mode->crtc_hsync_end, mode->crtc_htotal,
11245 mode->crtc_vdisplay, mode->crtc_vsync_start,
11246 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11247 }
11248
11249 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11250 struct intel_crtc_state *pipe_config,
11251 const char *context)
11252 {
11253 struct drm_device *dev = crtc->base.dev;
11254 struct drm_plane *plane;
11255 struct intel_plane *intel_plane;
11256 struct intel_plane_state *state;
11257 struct drm_framebuffer *fb;
11258
11259 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11260 context, pipe_config, pipe_name(crtc->pipe));
11261
11262 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11263 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11264 pipe_config->pipe_bpp, pipe_config->dither);
11265 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11266 pipe_config->has_pch_encoder,
11267 pipe_config->fdi_lanes,
11268 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11269 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11270 pipe_config->fdi_m_n.tu);
11271 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11272 pipe_config->has_dp_encoder,
11273 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11274 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11275 pipe_config->dp_m_n.tu);
11276
11277 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11278 pipe_config->has_dp_encoder,
11279 pipe_config->dp_m2_n2.gmch_m,
11280 pipe_config->dp_m2_n2.gmch_n,
11281 pipe_config->dp_m2_n2.link_m,
11282 pipe_config->dp_m2_n2.link_n,
11283 pipe_config->dp_m2_n2.tu);
11284
11285 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11286 pipe_config->has_audio,
11287 pipe_config->has_infoframe);
11288
11289 DRM_DEBUG_KMS("requested mode:\n");
11290 drm_mode_debug_printmodeline(&pipe_config->base.mode);
11291 DRM_DEBUG_KMS("adjusted mode:\n");
11292 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11293 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11294 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
11295 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11296 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
11297 DRM_DEBUG_KMS("num_scalers: %d\n", crtc->num_scalers);
11298 DRM_DEBUG_KMS("scaler_users: 0x%x\n", pipe_config->scaler_state.scaler_users);
11299 DRM_DEBUG_KMS("scaler id: %d\n", pipe_config->scaler_state.scaler_id);
11300 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11301 pipe_config->gmch_pfit.control,
11302 pipe_config->gmch_pfit.pgm_ratios,
11303 pipe_config->gmch_pfit.lvds_border_bits);
11304 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11305 pipe_config->pch_pfit.pos,
11306 pipe_config->pch_pfit.size,
11307 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
11308 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
11309 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
11310
11311 DRM_DEBUG_KMS("planes on this crtc\n");
11312 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11313 intel_plane = to_intel_plane(plane);
11314 if (intel_plane->pipe != crtc->pipe)
11315 continue;
11316
11317 state = to_intel_plane_state(plane->state);
11318 fb = state->base.fb;
11319 if (!fb) {
11320 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11321 "disabled, scaler_id = %d\n",
11322 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11323 plane->base.id, intel_plane->pipe,
11324 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11325 drm_plane_index(plane), state->scaler_id);
11326 continue;
11327 }
11328
11329 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11330 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11331 plane->base.id, intel_plane->pipe,
11332 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
11333 drm_plane_index(plane));
11334 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11335 fb->base.id, fb->width, fb->height, fb->pixel_format);
11336 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11337 state->scaler_id,
11338 state->src.x1 >> 16, state->src.y1 >> 16,
11339 drm_rect_width(&state->src) >> 16,
11340 drm_rect_height(&state->src) >> 16,
11341 state->dst.x1, state->dst.y1,
11342 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
11343 }
11344 }
11345
11346 static bool encoders_cloneable(const struct intel_encoder *a,
11347 const struct intel_encoder *b)
11348 {
11349 /* masks could be asymmetric, so check both ways */
11350 return a == b || (a->cloneable & (1 << b->type) &&
11351 b->cloneable & (1 << a->type));
11352 }
11353
11354 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11355 struct intel_crtc *crtc,
11356 struct intel_encoder *encoder)
11357 {
11358 struct intel_encoder *source_encoder;
11359 struct drm_connector *connector;
11360 struct drm_connector_state *connector_state;
11361 int i;
11362
11363 for_each_connector_in_state(state, connector, connector_state, i) {
11364 if (connector_state->crtc != &crtc->base)
11365 continue;
11366
11367 source_encoder =
11368 to_intel_encoder(connector_state->best_encoder);
11369 if (!encoders_cloneable(encoder, source_encoder))
11370 return false;
11371 }
11372
11373 return true;
11374 }
11375
11376 static bool check_encoder_cloning(struct drm_atomic_state *state,
11377 struct intel_crtc *crtc)
11378 {
11379 struct intel_encoder *encoder;
11380 struct drm_connector *connector;
11381 struct drm_connector_state *connector_state;
11382 int i;
11383
11384 for_each_connector_in_state(state, connector, connector_state, i) {
11385 if (connector_state->crtc != &crtc->base)
11386 continue;
11387
11388 encoder = to_intel_encoder(connector_state->best_encoder);
11389 if (!check_single_encoder_cloning(state, crtc, encoder))
11390 return false;
11391 }
11392
11393 return true;
11394 }
11395
11396 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
11397 {
11398 struct drm_device *dev = state->dev;
11399 struct intel_encoder *encoder;
11400 struct drm_connector *connector;
11401 struct drm_connector_state *connector_state;
11402 unsigned int used_ports = 0;
11403 int i;
11404
11405 /*
11406 * Walk the connector list instead of the encoder
11407 * list to detect the problem on ddi platforms
11408 * where there's just one encoder per digital port.
11409 */
11410 for_each_connector_in_state(state, connector, connector_state, i) {
11411 if (!connector_state->best_encoder)
11412 continue;
11413
11414 encoder = to_intel_encoder(connector_state->best_encoder);
11415
11416 WARN_ON(!connector_state->crtc);
11417
11418 switch (encoder->type) {
11419 unsigned int port_mask;
11420 case INTEL_OUTPUT_UNKNOWN:
11421 if (WARN_ON(!HAS_DDI(dev)))
11422 break;
11423 case INTEL_OUTPUT_DISPLAYPORT:
11424 case INTEL_OUTPUT_HDMI:
11425 case INTEL_OUTPUT_EDP:
11426 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11427
11428 /* the same port mustn't appear more than once */
11429 if (used_ports & port_mask)
11430 return false;
11431
11432 used_ports |= port_mask;
11433 default:
11434 break;
11435 }
11436 }
11437
11438 return true;
11439 }
11440
11441 static void
11442 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11443 {
11444 struct drm_crtc_state tmp_state;
11445 struct intel_crtc_scaler_state scaler_state;
11446
11447 /* Clear only the intel specific part of the crtc state excluding scalers */
11448 tmp_state = crtc_state->base;
11449 scaler_state = crtc_state->scaler_state;
11450 memset(crtc_state, 0, sizeof *crtc_state);
11451 crtc_state->base = tmp_state;
11452 crtc_state->scaler_state = scaler_state;
11453 }
11454
11455 static int
11456 intel_modeset_pipe_config(struct drm_crtc *crtc,
11457 struct drm_display_mode *mode,
11458 struct drm_atomic_state *state,
11459 struct intel_crtc_state *pipe_config)
11460 {
11461 struct intel_encoder *encoder;
11462 struct drm_connector *connector;
11463 struct drm_connector_state *connector_state;
11464 int base_bpp, ret = -EINVAL;
11465 int i;
11466 bool retry = true;
11467
11468 if (!check_encoder_cloning(state, to_intel_crtc(crtc))) {
11469 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11470 return -EINVAL;
11471 }
11472
11473 if (!check_digital_port_conflicts(state)) {
11474 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
11475 return -EINVAL;
11476 }
11477
11478 clear_intel_crtc_state(pipe_config);
11479
11480 pipe_config->base.crtc = crtc;
11481 drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
11482 drm_mode_copy(&pipe_config->base.mode, mode);
11483
11484 pipe_config->cpu_transcoder =
11485 (enum transcoder) to_intel_crtc(crtc)->pipe;
11486 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
11487
11488 /*
11489 * Sanitize sync polarity flags based on requested ones. If neither
11490 * positive or negative polarity is requested, treat this as meaning
11491 * negative polarity.
11492 */
11493 if (!(pipe_config->base.adjusted_mode.flags &
11494 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
11495 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
11496
11497 if (!(pipe_config->base.adjusted_mode.flags &
11498 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
11499 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
11500
11501 /* Compute a starting value for pipe_config->pipe_bpp taking the source
11502 * plane pixel format and any sink constraints into account. Returns the
11503 * source plane bpp so that dithering can be selected on mismatches
11504 * after encoders and crtc also have had their say. */
11505 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11506 pipe_config);
11507 if (base_bpp < 0)
11508 goto fail;
11509
11510 /*
11511 * Determine the real pipe dimensions. Note that stereo modes can
11512 * increase the actual pipe size due to the frame doubling and
11513 * insertion of additional space for blanks between the frame. This
11514 * is stored in the crtc timings. We use the requested mode to do this
11515 * computation to clearly distinguish it from the adjusted mode, which
11516 * can be changed by the connectors in the below retry loop.
11517 */
11518 drm_crtc_get_hv_timing(&pipe_config->base.mode,
11519 &pipe_config->pipe_src_w,
11520 &pipe_config->pipe_src_h);
11521
11522 encoder_retry:
11523 /* Ensure the port clock defaults are reset when retrying. */
11524 pipe_config->port_clock = 0;
11525 pipe_config->pixel_multiplier = 1;
11526
11527 /* Fill in default crtc timings, allow encoders to overwrite them. */
11528 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11529 CRTC_STEREO_DOUBLE);
11530
11531 /* Pass our mode to the connectors and the CRTC to give them a chance to
11532 * adjust it according to limitations or connector properties, and also
11533 * a chance to reject the mode entirely.
11534 */
11535 for_each_connector_in_state(state, connector, connector_state, i) {
11536 if (connector_state->crtc != crtc)
11537 continue;
11538
11539 encoder = to_intel_encoder(connector_state->best_encoder);
11540
11541 if (!(encoder->compute_config(encoder, pipe_config))) {
11542 DRM_DEBUG_KMS("Encoder config failure\n");
11543 goto fail;
11544 }
11545 }
11546
11547 /* Set default port clock if not overwritten by the encoder. Needs to be
11548 * done afterwards in case the encoder adjusts the mode. */
11549 if (!pipe_config->port_clock)
11550 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
11551 * pipe_config->pixel_multiplier;
11552
11553 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
11554 if (ret < 0) {
11555 DRM_DEBUG_KMS("CRTC fixup failed\n");
11556 goto fail;
11557 }
11558
11559 if (ret == RETRY) {
11560 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11561 ret = -EINVAL;
11562 goto fail;
11563 }
11564
11565 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11566 retry = false;
11567 goto encoder_retry;
11568 }
11569
11570 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
11571 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
11572 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
11573
11574 return 0;
11575 fail:
11576 return ret;
11577 }
11578
11579 static bool intel_crtc_in_use(struct drm_crtc *crtc)
11580 {
11581 struct drm_encoder *encoder;
11582 struct drm_device *dev = crtc->dev;
11583
11584 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
11585 if (encoder->crtc == crtc)
11586 return true;
11587
11588 return false;
11589 }
11590
11591 static bool
11592 needs_modeset(struct drm_crtc_state *state)
11593 {
11594 return state->mode_changed || state->active_changed;
11595 }
11596
11597 static void
11598 intel_modeset_update_state(struct drm_atomic_state *state)
11599 {
11600 struct drm_device *dev = state->dev;
11601 struct drm_i915_private *dev_priv = dev->dev_private;
11602 struct intel_encoder *intel_encoder;
11603 struct drm_crtc *crtc;
11604 struct drm_crtc_state *crtc_state;
11605 struct drm_connector *connector;
11606 int i;
11607
11608 intel_shared_dpll_commit(dev_priv);
11609
11610 for_each_intel_encoder(dev, intel_encoder) {
11611 if (!intel_encoder->base.crtc)
11612 continue;
11613
11614 for_each_crtc_in_state(state, crtc, crtc_state, i)
11615 if (crtc == intel_encoder->base.crtc)
11616 break;
11617
11618 if (crtc != intel_encoder->base.crtc)
11619 continue;
11620
11621 if (crtc_state->enable && needs_modeset(crtc_state))
11622 intel_encoder->connectors_active = false;
11623 }
11624
11625 intel_modeset_commit_output_state(dev);
11626
11627 /* Double check state. */
11628 for_each_crtc(dev, crtc) {
11629 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
11630 }
11631
11632 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11633 if (!connector->encoder || !connector->encoder->crtc)
11634 continue;
11635
11636 for_each_crtc_in_state(state, crtc, crtc_state, i)
11637 if (crtc == connector->encoder->crtc)
11638 break;
11639
11640 if (crtc != connector->encoder->crtc)
11641 continue;
11642
11643 if (crtc_state->enable && needs_modeset(crtc_state)) {
11644 struct drm_property *dpms_property =
11645 dev->mode_config.dpms_property;
11646
11647 connector->dpms = DRM_MODE_DPMS_ON;
11648 drm_object_property_set_value(&connector->base,
11649 dpms_property,
11650 DRM_MODE_DPMS_ON);
11651
11652 intel_encoder = to_intel_encoder(connector->encoder);
11653 intel_encoder->connectors_active = true;
11654 }
11655 }
11656
11657 }
11658
11659 static bool intel_fuzzy_clock_check(int clock1, int clock2)
11660 {
11661 int diff;
11662
11663 if (clock1 == clock2)
11664 return true;
11665
11666 if (!clock1 || !clock2)
11667 return false;
11668
11669 diff = abs(clock1 - clock2);
11670
11671 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11672 return true;
11673
11674 return false;
11675 }
11676
11677 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
11678 list_for_each_entry((intel_crtc), \
11679 &(dev)->mode_config.crtc_list, \
11680 base.head) \
11681 if (mask & (1 <<(intel_crtc)->pipe))
11682
11683 static bool
11684 intel_pipe_config_compare(struct drm_device *dev,
11685 struct intel_crtc_state *current_config,
11686 struct intel_crtc_state *pipe_config)
11687 {
11688 #define PIPE_CONF_CHECK_X(name) \
11689 if (current_config->name != pipe_config->name) { \
11690 DRM_ERROR("mismatch in " #name " " \
11691 "(expected 0x%08x, found 0x%08x)\n", \
11692 current_config->name, \
11693 pipe_config->name); \
11694 return false; \
11695 }
11696
11697 #define PIPE_CONF_CHECK_I(name) \
11698 if (current_config->name != pipe_config->name) { \
11699 DRM_ERROR("mismatch in " #name " " \
11700 "(expected %i, found %i)\n", \
11701 current_config->name, \
11702 pipe_config->name); \
11703 return false; \
11704 }
11705
11706 /* This is required for BDW+ where there is only one set of registers for
11707 * switching between high and low RR.
11708 * This macro can be used whenever a comparison has to be made between one
11709 * hw state and multiple sw state variables.
11710 */
11711 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
11712 if ((current_config->name != pipe_config->name) && \
11713 (current_config->alt_name != pipe_config->name)) { \
11714 DRM_ERROR("mismatch in " #name " " \
11715 "(expected %i or %i, found %i)\n", \
11716 current_config->name, \
11717 current_config->alt_name, \
11718 pipe_config->name); \
11719 return false; \
11720 }
11721
11722 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
11723 if ((current_config->name ^ pipe_config->name) & (mask)) { \
11724 DRM_ERROR("mismatch in " #name "(" #mask ") " \
11725 "(expected %i, found %i)\n", \
11726 current_config->name & (mask), \
11727 pipe_config->name & (mask)); \
11728 return false; \
11729 }
11730
11731 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11732 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11733 DRM_ERROR("mismatch in " #name " " \
11734 "(expected %i, found %i)\n", \
11735 current_config->name, \
11736 pipe_config->name); \
11737 return false; \
11738 }
11739
11740 #define PIPE_CONF_QUIRK(quirk) \
11741 ((current_config->quirks | pipe_config->quirks) & (quirk))
11742
11743 PIPE_CONF_CHECK_I(cpu_transcoder);
11744
11745 PIPE_CONF_CHECK_I(has_pch_encoder);
11746 PIPE_CONF_CHECK_I(fdi_lanes);
11747 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
11748 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
11749 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
11750 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
11751 PIPE_CONF_CHECK_I(fdi_m_n.tu);
11752
11753 PIPE_CONF_CHECK_I(has_dp_encoder);
11754
11755 if (INTEL_INFO(dev)->gen < 8) {
11756 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
11757 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
11758 PIPE_CONF_CHECK_I(dp_m_n.link_m);
11759 PIPE_CONF_CHECK_I(dp_m_n.link_n);
11760 PIPE_CONF_CHECK_I(dp_m_n.tu);
11761
11762 if (current_config->has_drrs) {
11763 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
11764 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
11765 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
11766 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
11767 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
11768 }
11769 } else {
11770 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
11771 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
11772 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
11773 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
11774 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
11775 }
11776
11777 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11778 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11779 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11780 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11781 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11782 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
11783
11784 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11785 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11786 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11787 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11788 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11789 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
11790
11791 PIPE_CONF_CHECK_I(pixel_multiplier);
11792 PIPE_CONF_CHECK_I(has_hdmi_sink);
11793 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
11794 IS_VALLEYVIEW(dev))
11795 PIPE_CONF_CHECK_I(limited_color_range);
11796 PIPE_CONF_CHECK_I(has_infoframe);
11797
11798 PIPE_CONF_CHECK_I(has_audio);
11799
11800 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11801 DRM_MODE_FLAG_INTERLACE);
11802
11803 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
11804 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11805 DRM_MODE_FLAG_PHSYNC);
11806 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11807 DRM_MODE_FLAG_NHSYNC);
11808 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11809 DRM_MODE_FLAG_PVSYNC);
11810 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11811 DRM_MODE_FLAG_NVSYNC);
11812 }
11813
11814 PIPE_CONF_CHECK_I(pipe_src_w);
11815 PIPE_CONF_CHECK_I(pipe_src_h);
11816
11817 /*
11818 * FIXME: BIOS likes to set up a cloned config with lvds+external
11819 * screen. Since we don't yet re-compute the pipe config when moving
11820 * just the lvds port away to another pipe the sw tracking won't match.
11821 *
11822 * Proper atomic modesets with recomputed global state will fix this.
11823 * Until then just don't check gmch state for inherited modes.
11824 */
11825 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
11826 PIPE_CONF_CHECK_I(gmch_pfit.control);
11827 /* pfit ratios are autocomputed by the hw on gen4+ */
11828 if (INTEL_INFO(dev)->gen < 4)
11829 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
11830 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
11831 }
11832
11833 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11834 if (current_config->pch_pfit.enabled) {
11835 PIPE_CONF_CHECK_I(pch_pfit.pos);
11836 PIPE_CONF_CHECK_I(pch_pfit.size);
11837 }
11838
11839 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11840
11841 /* BDW+ don't expose a synchronous way to read the state */
11842 if (IS_HASWELL(dev))
11843 PIPE_CONF_CHECK_I(ips_enabled);
11844
11845 PIPE_CONF_CHECK_I(double_wide);
11846
11847 PIPE_CONF_CHECK_X(ddi_pll_sel);
11848
11849 PIPE_CONF_CHECK_I(shared_dpll);
11850 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
11851 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
11852 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11853 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
11854 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
11855 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11856 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11857 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
11858
11859 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
11860 PIPE_CONF_CHECK_I(pipe_bpp);
11861
11862 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
11863 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
11864
11865 #undef PIPE_CONF_CHECK_X
11866 #undef PIPE_CONF_CHECK_I
11867 #undef PIPE_CONF_CHECK_I_ALT
11868 #undef PIPE_CONF_CHECK_FLAGS
11869 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11870 #undef PIPE_CONF_QUIRK
11871
11872 return true;
11873 }
11874
11875 static void check_wm_state(struct drm_device *dev)
11876 {
11877 struct drm_i915_private *dev_priv = dev->dev_private;
11878 struct skl_ddb_allocation hw_ddb, *sw_ddb;
11879 struct intel_crtc *intel_crtc;
11880 int plane;
11881
11882 if (INTEL_INFO(dev)->gen < 9)
11883 return;
11884
11885 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11886 sw_ddb = &dev_priv->wm.skl_hw.ddb;
11887
11888 for_each_intel_crtc(dev, intel_crtc) {
11889 struct skl_ddb_entry *hw_entry, *sw_entry;
11890 const enum pipe pipe = intel_crtc->pipe;
11891
11892 if (!intel_crtc->active)
11893 continue;
11894
11895 /* planes */
11896 for_each_plane(dev_priv, pipe, plane) {
11897 hw_entry = &hw_ddb.plane[pipe][plane];
11898 sw_entry = &sw_ddb->plane[pipe][plane];
11899
11900 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11901 continue;
11902
11903 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
11904 "(expected (%u,%u), found (%u,%u))\n",
11905 pipe_name(pipe), plane + 1,
11906 sw_entry->start, sw_entry->end,
11907 hw_entry->start, hw_entry->end);
11908 }
11909
11910 /* cursor */
11911 hw_entry = &hw_ddb.cursor[pipe];
11912 sw_entry = &sw_ddb->cursor[pipe];
11913
11914 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11915 continue;
11916
11917 DRM_ERROR("mismatch in DDB state pipe %c cursor "
11918 "(expected (%u,%u), found (%u,%u))\n",
11919 pipe_name(pipe),
11920 sw_entry->start, sw_entry->end,
11921 hw_entry->start, hw_entry->end);
11922 }
11923 }
11924
11925 static void
11926 check_connector_state(struct drm_device *dev)
11927 {
11928 struct intel_connector *connector;
11929
11930 for_each_intel_connector(dev, connector) {
11931 /* This also checks the encoder/connector hw state with the
11932 * ->get_hw_state callbacks. */
11933 intel_connector_check_state(connector);
11934
11935 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
11936 "connector's staged encoder doesn't match current encoder\n");
11937 }
11938 }
11939
11940 static void
11941 check_encoder_state(struct drm_device *dev)
11942 {
11943 struct intel_encoder *encoder;
11944 struct intel_connector *connector;
11945
11946 for_each_intel_encoder(dev, encoder) {
11947 bool enabled = false;
11948 bool active = false;
11949 enum pipe pipe, tracked_pipe;
11950
11951 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11952 encoder->base.base.id,
11953 encoder->base.name);
11954
11955 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
11956 "encoder's stage crtc doesn't match current crtc\n");
11957 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
11958 "encoder's active_connectors set, but no crtc\n");
11959
11960 for_each_intel_connector(dev, connector) {
11961 if (connector->base.encoder != &encoder->base)
11962 continue;
11963 enabled = true;
11964 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
11965 active = true;
11966 }
11967 /*
11968 * for MST connectors if we unplug the connector is gone
11969 * away but the encoder is still connected to a crtc
11970 * until a modeset happens in response to the hotplug.
11971 */
11972 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
11973 continue;
11974
11975 I915_STATE_WARN(!!encoder->base.crtc != enabled,
11976 "encoder's enabled state mismatch "
11977 "(expected %i, found %i)\n",
11978 !!encoder->base.crtc, enabled);
11979 I915_STATE_WARN(active && !encoder->base.crtc,
11980 "active encoder with no crtc\n");
11981
11982 I915_STATE_WARN(encoder->connectors_active != active,
11983 "encoder's computed active state doesn't match tracked active state "
11984 "(expected %i, found %i)\n", active, encoder->connectors_active);
11985
11986 active = encoder->get_hw_state(encoder, &pipe);
11987 I915_STATE_WARN(active != encoder->connectors_active,
11988 "encoder's hw state doesn't match sw tracking "
11989 "(expected %i, found %i)\n",
11990 encoder->connectors_active, active);
11991
11992 if (!encoder->base.crtc)
11993 continue;
11994
11995 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
11996 I915_STATE_WARN(active && pipe != tracked_pipe,
11997 "active encoder's pipe doesn't match"
11998 "(expected %i, found %i)\n",
11999 tracked_pipe, pipe);
12000
12001 }
12002 }
12003
12004 static void
12005 check_crtc_state(struct drm_device *dev)
12006 {
12007 struct drm_i915_private *dev_priv = dev->dev_private;
12008 struct intel_crtc *crtc;
12009 struct intel_encoder *encoder;
12010 struct intel_crtc_state pipe_config;
12011
12012 for_each_intel_crtc(dev, crtc) {
12013 bool enabled = false;
12014 bool active = false;
12015
12016 memset(&pipe_config, 0, sizeof(pipe_config));
12017
12018 DRM_DEBUG_KMS("[CRTC:%d]\n",
12019 crtc->base.base.id);
12020
12021 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
12022 "active crtc, but not enabled in sw tracking\n");
12023
12024 for_each_intel_encoder(dev, encoder) {
12025 if (encoder->base.crtc != &crtc->base)
12026 continue;
12027 enabled = true;
12028 if (encoder->connectors_active)
12029 active = true;
12030 }
12031
12032 I915_STATE_WARN(active != crtc->active,
12033 "crtc's computed active state doesn't match tracked active state "
12034 "(expected %i, found %i)\n", active, crtc->active);
12035 I915_STATE_WARN(enabled != crtc->base.state->enable,
12036 "crtc's computed enabled state doesn't match tracked enabled state "
12037 "(expected %i, found %i)\n", enabled,
12038 crtc->base.state->enable);
12039
12040 active = dev_priv->display.get_pipe_config(crtc,
12041 &pipe_config);
12042
12043 /* hw state is inconsistent with the pipe quirk */
12044 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12045 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12046 active = crtc->active;
12047
12048 for_each_intel_encoder(dev, encoder) {
12049 enum pipe pipe;
12050 if (encoder->base.crtc != &crtc->base)
12051 continue;
12052 if (encoder->get_hw_state(encoder, &pipe))
12053 encoder->get_config(encoder, &pipe_config);
12054 }
12055
12056 I915_STATE_WARN(crtc->active != active,
12057 "crtc active state doesn't match with hw state "
12058 "(expected %i, found %i)\n", crtc->active, active);
12059
12060 if (active &&
12061 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
12062 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12063 intel_dump_pipe_config(crtc, &pipe_config,
12064 "[hw state]");
12065 intel_dump_pipe_config(crtc, crtc->config,
12066 "[sw state]");
12067 }
12068 }
12069 }
12070
12071 static void
12072 check_shared_dpll_state(struct drm_device *dev)
12073 {
12074 struct drm_i915_private *dev_priv = dev->dev_private;
12075 struct intel_crtc *crtc;
12076 struct intel_dpll_hw_state dpll_hw_state;
12077 int i;
12078
12079 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12080 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12081 int enabled_crtcs = 0, active_crtcs = 0;
12082 bool active;
12083
12084 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12085
12086 DRM_DEBUG_KMS("%s\n", pll->name);
12087
12088 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12089
12090 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12091 "more active pll users than references: %i vs %i\n",
12092 pll->active, hweight32(pll->config.crtc_mask));
12093 I915_STATE_WARN(pll->active && !pll->on,
12094 "pll in active use but not on in sw tracking\n");
12095 I915_STATE_WARN(pll->on && !pll->active,
12096 "pll in on but not on in use in sw tracking\n");
12097 I915_STATE_WARN(pll->on != active,
12098 "pll on state mismatch (expected %i, found %i)\n",
12099 pll->on, active);
12100
12101 for_each_intel_crtc(dev, crtc) {
12102 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12103 enabled_crtcs++;
12104 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12105 active_crtcs++;
12106 }
12107 I915_STATE_WARN(pll->active != active_crtcs,
12108 "pll active crtcs mismatch (expected %i, found %i)\n",
12109 pll->active, active_crtcs);
12110 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12111 "pll enabled crtcs mismatch (expected %i, found %i)\n",
12112 hweight32(pll->config.crtc_mask), enabled_crtcs);
12113
12114 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12115 sizeof(dpll_hw_state)),
12116 "pll hw state mismatch\n");
12117 }
12118 }
12119
12120 void
12121 intel_modeset_check_state(struct drm_device *dev)
12122 {
12123 check_wm_state(dev);
12124 check_connector_state(dev);
12125 check_encoder_state(dev);
12126 check_crtc_state(dev);
12127 check_shared_dpll_state(dev);
12128 }
12129
12130 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12131 int dotclock)
12132 {
12133 /*
12134 * FDI already provided one idea for the dotclock.
12135 * Yell if the encoder disagrees.
12136 */
12137 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12138 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12139 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12140 }
12141
12142 static void update_scanline_offset(struct intel_crtc *crtc)
12143 {
12144 struct drm_device *dev = crtc->base.dev;
12145
12146 /*
12147 * The scanline counter increments at the leading edge of hsync.
12148 *
12149 * On most platforms it starts counting from vtotal-1 on the
12150 * first active line. That means the scanline counter value is
12151 * always one less than what we would expect. Ie. just after
12152 * start of vblank, which also occurs at start of hsync (on the
12153 * last active line), the scanline counter will read vblank_start-1.
12154 *
12155 * On gen2 the scanline counter starts counting from 1 instead
12156 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12157 * to keep the value positive), instead of adding one.
12158 *
12159 * On HSW+ the behaviour of the scanline counter depends on the output
12160 * type. For DP ports it behaves like most other platforms, but on HDMI
12161 * there's an extra 1 line difference. So we need to add two instead of
12162 * one to the value.
12163 */
12164 if (IS_GEN2(dev)) {
12165 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
12166 int vtotal;
12167
12168 vtotal = mode->crtc_vtotal;
12169 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12170 vtotal /= 2;
12171
12172 crtc->scanline_offset = vtotal - 1;
12173 } else if (HAS_DDI(dev) &&
12174 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12175 crtc->scanline_offset = 2;
12176 } else
12177 crtc->scanline_offset = 1;
12178 }
12179
12180 static void
12181 intel_atomic_modeset_compute_changed_flags(struct drm_atomic_state *state,
12182 struct drm_crtc *modeset_crtc)
12183 {
12184 struct drm_crtc_state *crtc_state;
12185 struct drm_crtc *crtc;
12186 int i;
12187
12188 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12189 if (crtc_state->enable != crtc->state->enable)
12190 crtc_state->mode_changed = true;
12191
12192 /* FIXME: Do we need to always set mode_changed for
12193 * modeset_crtc if it is enabled? modeset_affect_pipes()
12194 * did that. */
12195 }
12196 }
12197
12198 static struct intel_crtc_state *
12199 intel_modeset_compute_config(struct drm_crtc *crtc,
12200 struct drm_display_mode *mode,
12201 struct drm_atomic_state *state)
12202 {
12203 struct intel_crtc_state *pipe_config;
12204 int ret = 0;
12205
12206 ret = drm_atomic_add_affected_connectors(state, crtc);
12207 if (ret)
12208 return ERR_PTR(ret);
12209
12210 intel_atomic_modeset_compute_changed_flags(state, crtc);
12211
12212 /*
12213 * Note this needs changes when we start tracking multiple modes
12214 * and crtcs. At that point we'll need to compute the whole config
12215 * (i.e. one pipe_config for each crtc) rather than just the one
12216 * for this crtc.
12217 */
12218 pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
12219 if (IS_ERR(pipe_config))
12220 return pipe_config;
12221
12222 if (!pipe_config->base.enable)
12223 return pipe_config;
12224
12225 ret = intel_modeset_pipe_config(crtc, mode, state, pipe_config);
12226 if (ret)
12227 return ERR_PTR(ret);
12228
12229 /* Check things that can only be changed through modeset */
12230 if (pipe_config->has_audio !=
12231 to_intel_crtc(crtc)->config->has_audio)
12232 pipe_config->base.mode_changed = true;
12233
12234 /*
12235 * Note we have an issue here with infoframes: current code
12236 * only updates them on the full mode set path per hw
12237 * requirements. So here we should be checking for any
12238 * required changes and forcing a mode set.
12239 */
12240
12241 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,"[modeset]");
12242
12243 return pipe_config;
12244 }
12245
12246 static int __intel_set_mode_setup_plls(struct drm_atomic_state *state)
12247 {
12248 struct drm_device *dev = state->dev;
12249 struct drm_i915_private *dev_priv = to_i915(dev);
12250 unsigned clear_pipes = 0;
12251 struct intel_crtc *intel_crtc;
12252 struct intel_crtc_state *intel_crtc_state;
12253 struct drm_crtc *crtc;
12254 struct drm_crtc_state *crtc_state;
12255 int ret = 0;
12256 int i;
12257
12258 if (!dev_priv->display.crtc_compute_clock)
12259 return 0;
12260
12261 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12262 intel_crtc = to_intel_crtc(crtc);
12263
12264 if (needs_modeset(crtc_state))
12265 clear_pipes |= 1 << intel_crtc->pipe;
12266 }
12267
12268 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
12269 if (ret)
12270 goto done;
12271
12272 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12273 if (!needs_modeset(crtc_state) || !crtc_state->enable)
12274 continue;
12275
12276 intel_crtc = to_intel_crtc(crtc);
12277 intel_crtc_state = to_intel_crtc_state(crtc_state);
12278
12279 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12280 intel_crtc_state);
12281 if (ret) {
12282 intel_shared_dpll_abort_config(dev_priv);
12283 goto done;
12284 }
12285 }
12286
12287 done:
12288 return ret;
12289 }
12290
12291 /* Code that should eventually be part of atomic_check() */
12292 static int __intel_set_mode_checks(struct drm_atomic_state *state)
12293 {
12294 struct drm_device *dev = state->dev;
12295 int ret;
12296
12297 /*
12298 * See if the config requires any additional preparation, e.g.
12299 * to adjust global state with pipes off. We need to do this
12300 * here so we can get the modeset_pipe updated config for the new
12301 * mode set on this crtc. For other crtcs we need to use the
12302 * adjusted_mode bits in the crtc directly.
12303 */
12304 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
12305 ret = valleyview_modeset_global_pipes(state);
12306 if (ret)
12307 return ret;
12308 }
12309
12310 ret = __intel_set_mode_setup_plls(state);
12311 if (ret)
12312 return ret;
12313
12314 return 0;
12315 }
12316
12317 static int __intel_set_mode(struct drm_crtc *modeset_crtc,
12318 struct drm_display_mode *mode,
12319 struct intel_crtc_state *pipe_config)
12320 {
12321 struct drm_device *dev = modeset_crtc->dev;
12322 struct drm_i915_private *dev_priv = dev->dev_private;
12323 struct drm_atomic_state *state = pipe_config->base.state;
12324 struct intel_crtc_state *crtc_state_copy = NULL;
12325 struct intel_crtc *intel_crtc;
12326 struct drm_crtc *crtc;
12327 struct drm_crtc_state *crtc_state;
12328 struct drm_plane *plane;
12329 struct drm_plane_state *plane_state;
12330 int ret = 0;
12331 int i;
12332
12333 ret = __intel_set_mode_checks(state);
12334 if (ret < 0)
12335 return ret;
12336
12337 crtc_state_copy = kmalloc(sizeof(*crtc_state_copy), GFP_KERNEL);
12338 if (!crtc_state_copy)
12339 return -ENOMEM;
12340
12341 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12342 if (!needs_modeset(crtc_state))
12343 continue;
12344
12345 if (!crtc_state->enable) {
12346 intel_crtc_disable(crtc);
12347 } else if (crtc->state->enable) {
12348 intel_crtc_disable_planes(crtc);
12349 dev_priv->display.crtc_disable(crtc);
12350 }
12351 }
12352
12353 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
12354 * to set it here already despite that we pass it down the callchain.
12355 *
12356 * Note we'll need to fix this up when we start tracking multiple
12357 * pipes; here we assume a single modeset_pipe and only track the
12358 * single crtc and mode.
12359 */
12360 if (pipe_config->base.enable && needs_modeset(&pipe_config->base)) {
12361 modeset_crtc->mode = *mode;
12362 /* mode_set/enable/disable functions rely on a correct pipe
12363 * config. */
12364 intel_crtc_set_state(to_intel_crtc(modeset_crtc), pipe_config);
12365
12366 /*
12367 * Calculate and store various constants which
12368 * are later needed by vblank and swap-completion
12369 * timestamping. They are derived from true hwmode.
12370 */
12371 drm_calc_timestamping_constants(modeset_crtc,
12372 &pipe_config->base.adjusted_mode);
12373 }
12374
12375 /* Only after disabling all output pipelines that will be changed can we
12376 * update the the output configuration. */
12377 intel_modeset_update_state(state);
12378
12379 modeset_update_crtc_power_domains(state);
12380
12381 for_each_plane_in_state(state, plane, plane_state, i) {
12382 if (WARN_ON(plane != modeset_crtc->primary))
12383 continue;
12384
12385 /* Primary plane is disabled in intel_crtc_disable() */
12386 if (!pipe_config->base.enable)
12387 continue;
12388
12389 ret = drm_plane_helper_update(plane, plane_state->crtc,
12390 plane_state->fb,
12391 plane_state->crtc_x,
12392 plane_state->crtc_y,
12393 plane_state->crtc_w,
12394 plane_state->crtc_h,
12395 plane_state->src_x,
12396 plane_state->src_y,
12397 plane_state->src_w,
12398 plane_state->src_h);
12399 WARN_ON(ret != 0);
12400 }
12401
12402 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12403 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12404 if (!needs_modeset(crtc_state) || !crtc_state->enable)
12405 continue;
12406
12407 update_scanline_offset(to_intel_crtc(crtc));
12408
12409 dev_priv->display.crtc_enable(crtc);
12410 intel_crtc_enable_planes(crtc);
12411 }
12412
12413 /* FIXME: add subpixel order */
12414
12415 intel_crtc = to_intel_crtc(modeset_crtc);
12416
12417 /* The pipe_config will be freed with the atomic state, so
12418 * make a copy. */
12419 memcpy(crtc_state_copy, intel_crtc->config, sizeof *crtc_state_copy);
12420 intel_crtc->config = crtc_state_copy;
12421 intel_crtc->base.state = &crtc_state_copy->base;
12422
12423 return 0;
12424 }
12425
12426 static int intel_set_mode_with_config(struct drm_crtc *crtc,
12427 struct drm_display_mode *mode,
12428 struct intel_crtc_state *pipe_config)
12429 {
12430 int ret;
12431
12432 ret = __intel_set_mode(crtc, mode, pipe_config);
12433
12434 if (ret == 0)
12435 intel_modeset_check_state(crtc->dev);
12436
12437 return ret;
12438 }
12439
12440 static int intel_set_mode(struct drm_crtc *crtc,
12441 struct drm_display_mode *mode,
12442 struct drm_atomic_state *state)
12443 {
12444 struct intel_crtc_state *pipe_config;
12445 int ret = 0;
12446
12447 pipe_config = intel_modeset_compute_config(crtc, mode, state);
12448 if (IS_ERR(pipe_config)) {
12449 ret = PTR_ERR(pipe_config);
12450 goto out;
12451 }
12452
12453 ret = intel_set_mode_with_config(crtc, mode, pipe_config);
12454 if (ret)
12455 goto out;
12456
12457 out:
12458 return ret;
12459 }
12460
12461 void intel_crtc_restore_mode(struct drm_crtc *crtc)
12462 {
12463 struct drm_device *dev = crtc->dev;
12464 struct drm_atomic_state *state;
12465 struct intel_crtc *intel_crtc;
12466 struct intel_encoder *encoder;
12467 struct intel_connector *connector;
12468 struct drm_connector_state *connector_state;
12469 struct intel_crtc_state *crtc_state;
12470
12471 state = drm_atomic_state_alloc(dev);
12472 if (!state) {
12473 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
12474 crtc->base.id);
12475 return;
12476 }
12477
12478 state->acquire_ctx = dev->mode_config.acquire_ctx;
12479
12480 /* The force restore path in the HW readout code relies on the staged
12481 * config still keeping the user requested config while the actual
12482 * state has been overwritten by the configuration read from HW. We
12483 * need to copy the staged config to the atomic state, otherwise the
12484 * mode set will just reapply the state the HW is already in. */
12485 for_each_intel_encoder(dev, encoder) {
12486 if (&encoder->new_crtc->base != crtc)
12487 continue;
12488
12489 for_each_intel_connector(dev, connector) {
12490 if (connector->new_encoder != encoder)
12491 continue;
12492
12493 connector_state = drm_atomic_get_connector_state(state, &connector->base);
12494 if (IS_ERR(connector_state)) {
12495 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
12496 connector->base.base.id,
12497 connector->base.name,
12498 PTR_ERR(connector_state));
12499 continue;
12500 }
12501
12502 connector_state->crtc = crtc;
12503 connector_state->best_encoder = &encoder->base;
12504 }
12505 }
12506
12507 for_each_intel_crtc(dev, intel_crtc) {
12508 if (intel_crtc->new_enabled == intel_crtc->base.enabled)
12509 continue;
12510
12511 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
12512 if (IS_ERR(crtc_state)) {
12513 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
12514 intel_crtc->base.base.id,
12515 PTR_ERR(crtc_state));
12516 continue;
12517 }
12518
12519 crtc_state->base.enable = intel_crtc->new_enabled;
12520 }
12521
12522 intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
12523 crtc->primary->fb, crtc->x, crtc->y);
12524
12525 intel_set_mode(crtc, &crtc->mode, state);
12526
12527 drm_atomic_state_free(state);
12528 }
12529
12530 #undef for_each_intel_crtc_masked
12531
12532 static void intel_set_config_free(struct intel_set_config *config)
12533 {
12534 if (!config)
12535 return;
12536
12537 kfree(config->save_connector_encoders);
12538 kfree(config->save_encoder_crtcs);
12539 kfree(config->save_crtc_enabled);
12540 kfree(config);
12541 }
12542
12543 static int intel_set_config_save_state(struct drm_device *dev,
12544 struct intel_set_config *config)
12545 {
12546 struct drm_crtc *crtc;
12547 struct drm_encoder *encoder;
12548 struct drm_connector *connector;
12549 int count;
12550
12551 config->save_crtc_enabled =
12552 kcalloc(dev->mode_config.num_crtc,
12553 sizeof(bool), GFP_KERNEL);
12554 if (!config->save_crtc_enabled)
12555 return -ENOMEM;
12556
12557 config->save_encoder_crtcs =
12558 kcalloc(dev->mode_config.num_encoder,
12559 sizeof(struct drm_crtc *), GFP_KERNEL);
12560 if (!config->save_encoder_crtcs)
12561 return -ENOMEM;
12562
12563 config->save_connector_encoders =
12564 kcalloc(dev->mode_config.num_connector,
12565 sizeof(struct drm_encoder *), GFP_KERNEL);
12566 if (!config->save_connector_encoders)
12567 return -ENOMEM;
12568
12569 /* Copy data. Note that driver private data is not affected.
12570 * Should anything bad happen only the expected state is
12571 * restored, not the drivers personal bookkeeping.
12572 */
12573 count = 0;
12574 for_each_crtc(dev, crtc) {
12575 config->save_crtc_enabled[count++] = crtc->state->enable;
12576 }
12577
12578 count = 0;
12579 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
12580 config->save_encoder_crtcs[count++] = encoder->crtc;
12581 }
12582
12583 count = 0;
12584 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12585 config->save_connector_encoders[count++] = connector->encoder;
12586 }
12587
12588 return 0;
12589 }
12590
12591 static void intel_set_config_restore_state(struct drm_device *dev,
12592 struct intel_set_config *config)
12593 {
12594 struct intel_crtc *crtc;
12595 struct intel_encoder *encoder;
12596 struct intel_connector *connector;
12597 int count;
12598
12599 count = 0;
12600 for_each_intel_crtc(dev, crtc) {
12601 crtc->new_enabled = config->save_crtc_enabled[count++];
12602 }
12603
12604 count = 0;
12605 for_each_intel_encoder(dev, encoder) {
12606 encoder->new_crtc =
12607 to_intel_crtc(config->save_encoder_crtcs[count++]);
12608 }
12609
12610 count = 0;
12611 for_each_intel_connector(dev, connector) {
12612 connector->new_encoder =
12613 to_intel_encoder(config->save_connector_encoders[count++]);
12614 }
12615 }
12616
12617 static bool
12618 is_crtc_connector_off(struct drm_mode_set *set)
12619 {
12620 int i;
12621
12622 if (set->num_connectors == 0)
12623 return false;
12624
12625 if (WARN_ON(set->connectors == NULL))
12626 return false;
12627
12628 for (i = 0; i < set->num_connectors; i++)
12629 if (set->connectors[i]->encoder &&
12630 set->connectors[i]->encoder->crtc == set->crtc &&
12631 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
12632 return true;
12633
12634 return false;
12635 }
12636
12637 static void
12638 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
12639 struct intel_crtc_state *pipe_config)
12640 {
12641 struct drm_atomic_state *state;
12642 struct drm_connector *connector;
12643 struct drm_connector_state *connector_state;
12644 struct drm_crtc *crtc;
12645 struct drm_crtc_state *crtc_state;
12646 int i;
12647
12648 /* We should be able to check here if the fb has the same properties
12649 * and then just flip_or_move it */
12650 if (is_crtc_connector_off(set)) {
12651 pipe_config->base.mode_changed = true;
12652 } else if (set->crtc->primary->fb != set->fb) {
12653 /*
12654 * If we have no fb, we can only flip as long as the crtc is
12655 * active, otherwise we need a full mode set. The crtc may
12656 * be active if we've only disabled the primary plane, or
12657 * in fastboot situations.
12658 */
12659 if (set->crtc->primary->fb == NULL) {
12660 struct intel_crtc *intel_crtc =
12661 to_intel_crtc(set->crtc);
12662
12663 if (intel_crtc->active) {
12664 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
12665 pipe_config->base.planes_changed = true;
12666 } else {
12667 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
12668 pipe_config->base.mode_changed = true;
12669 }
12670 } else if (set->fb == NULL) {
12671 pipe_config->base.mode_changed = true;
12672 } else if (set->fb->pixel_format !=
12673 set->crtc->primary->fb->pixel_format) {
12674 pipe_config->base.mode_changed = true;
12675 } else {
12676 pipe_config->base.planes_changed = true;
12677 }
12678 }
12679
12680 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
12681 pipe_config->base.planes_changed = true;
12682
12683 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
12684 DRM_DEBUG_KMS("modes are different, full mode set\n");
12685 drm_mode_debug_printmodeline(&set->crtc->mode);
12686 drm_mode_debug_printmodeline(set->mode);
12687 pipe_config->base.mode_changed = true;
12688 }
12689
12690 state = pipe_config->base.state;
12691
12692 for_each_connector_in_state(state, connector, connector_state, i) {
12693 if (connector_state->best_encoder !=
12694 connector->state->best_encoder) {
12695 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full mode switch\n",
12696 connector->base.id,
12697 connector->name);
12698 pipe_config->base.mode_changed = true;
12699 }
12700
12701 if (connector_state->crtc != connector->state->crtc) {
12702 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] crtc changed, full mode switch\n",
12703 connector->base.id,
12704 connector->name);
12705 pipe_config->base.mode_changed = true;
12706 }
12707 }
12708
12709 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12710 if (crtc_state->enable == crtc->state->enable)
12711 continue;
12712
12713 DRM_DEBUG_KMS("[CRTC:%d] %sabled, full mode switch\n",
12714 crtc->base.id,
12715 crtc_state->enable ? "en" : "dis");
12716 pipe_config->base.mode_changed = true;
12717 }
12718
12719 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
12720 set->crtc->base.id, pipe_config->base.mode_changed,
12721 pipe_config->base.planes_changed);
12722 }
12723
12724 static int
12725 intel_modeset_stage_output_state(struct drm_device *dev,
12726 struct drm_mode_set *set,
12727 struct drm_atomic_state *state)
12728 {
12729 struct intel_connector *connector;
12730 struct drm_connector_state *connector_state;
12731 struct intel_encoder *encoder;
12732 struct intel_crtc *crtc;
12733 struct intel_crtc_state *crtc_state;
12734 int ro;
12735
12736 /* The upper layers ensure that we either disable a crtc or have a list
12737 * of connectors. For paranoia, double-check this. */
12738 WARN_ON(!set->fb && (set->num_connectors != 0));
12739 WARN_ON(set->fb && (set->num_connectors == 0));
12740
12741 for_each_intel_connector(dev, connector) {
12742 /* Otherwise traverse passed in connector list and get encoders
12743 * for them. */
12744 for (ro = 0; ro < set->num_connectors; ro++) {
12745 if (set->connectors[ro] == &connector->base) {
12746 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
12747 break;
12748 }
12749 }
12750
12751 /* If we disable the crtc, disable all its connectors. Also, if
12752 * the connector is on the changing crtc but not on the new
12753 * connector list, disable it. */
12754 if ((!set->fb || ro == set->num_connectors) &&
12755 connector->base.encoder &&
12756 connector->base.encoder->crtc == set->crtc) {
12757 connector->new_encoder = NULL;
12758
12759 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
12760 connector->base.base.id,
12761 connector->base.name);
12762 }
12763 }
12764 /* connector->new_encoder is now updated for all connectors. */
12765
12766 /* Update crtc of enabled connectors. */
12767 for_each_intel_connector(dev, connector) {
12768 struct drm_crtc *new_crtc;
12769
12770 if (!connector->new_encoder)
12771 continue;
12772
12773 new_crtc = connector->new_encoder->base.crtc;
12774
12775 for (ro = 0; ro < set->num_connectors; ro++) {
12776 if (set->connectors[ro] == &connector->base)
12777 new_crtc = set->crtc;
12778 }
12779
12780 /* Make sure the new CRTC will work with the encoder */
12781 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
12782 new_crtc)) {
12783 return -EINVAL;
12784 }
12785 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
12786
12787 connector_state =
12788 drm_atomic_get_connector_state(state, &connector->base);
12789 if (IS_ERR(connector_state))
12790 return PTR_ERR(connector_state);
12791
12792 connector_state->crtc = new_crtc;
12793 connector_state->best_encoder = &connector->new_encoder->base;
12794
12795 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
12796 connector->base.base.id,
12797 connector->base.name,
12798 new_crtc->base.id);
12799 }
12800
12801 /* Check for any encoders that needs to be disabled. */
12802 for_each_intel_encoder(dev, encoder) {
12803 int num_connectors = 0;
12804 for_each_intel_connector(dev, connector) {
12805 if (connector->new_encoder == encoder) {
12806 WARN_ON(!connector->new_encoder->new_crtc);
12807 num_connectors++;
12808 }
12809 }
12810
12811 if (num_connectors == 0)
12812 encoder->new_crtc = NULL;
12813 else if (num_connectors > 1)
12814 return -EINVAL;
12815 }
12816 /* Now we've also updated encoder->new_crtc for all encoders. */
12817 for_each_intel_connector(dev, connector) {
12818 connector_state =
12819 drm_atomic_get_connector_state(state, &connector->base);
12820 if (IS_ERR(connector_state))
12821 return PTR_ERR(connector_state);
12822
12823 if (connector->new_encoder) {
12824 if (connector->new_encoder != connector->encoder)
12825 connector->encoder = connector->new_encoder;
12826 } else {
12827 connector_state->crtc = NULL;
12828 connector_state->best_encoder = NULL;
12829 }
12830 }
12831 for_each_intel_crtc(dev, crtc) {
12832 crtc->new_enabled = false;
12833
12834 for_each_intel_encoder(dev, encoder) {
12835 if (encoder->new_crtc == crtc) {
12836 crtc->new_enabled = true;
12837 break;
12838 }
12839 }
12840
12841 if (crtc->new_enabled != crtc->base.state->enable) {
12842 crtc_state = intel_atomic_get_crtc_state(state, crtc);
12843 if (IS_ERR(crtc_state))
12844 return PTR_ERR(crtc_state);
12845
12846 crtc_state->base.enable = crtc->new_enabled;
12847 }
12848 }
12849
12850 return 0;
12851 }
12852
12853 static int intel_crtc_set_config(struct drm_mode_set *set)
12854 {
12855 struct drm_device *dev;
12856 struct drm_atomic_state *state = NULL;
12857 struct intel_set_config *config;
12858 struct intel_crtc_state *pipe_config;
12859 int ret;
12860
12861 BUG_ON(!set);
12862 BUG_ON(!set->crtc);
12863 BUG_ON(!set->crtc->helper_private);
12864
12865 /* Enforce sane interface api - has been abused by the fb helper. */
12866 BUG_ON(!set->mode && set->fb);
12867 BUG_ON(set->fb && set->num_connectors == 0);
12868
12869 if (set->fb) {
12870 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
12871 set->crtc->base.id, set->fb->base.id,
12872 (int)set->num_connectors, set->x, set->y);
12873 } else {
12874 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
12875 }
12876
12877 dev = set->crtc->dev;
12878
12879 ret = -ENOMEM;
12880 config = kzalloc(sizeof(*config), GFP_KERNEL);
12881 if (!config)
12882 goto out_config;
12883
12884 ret = intel_set_config_save_state(dev, config);
12885 if (ret)
12886 goto out_config;
12887
12888 state = drm_atomic_state_alloc(dev);
12889 if (!state) {
12890 ret = -ENOMEM;
12891 goto out_config;
12892 }
12893
12894 state->acquire_ctx = dev->mode_config.acquire_ctx;
12895
12896 ret = intel_modeset_stage_output_state(dev, set, state);
12897 if (ret)
12898 goto fail;
12899
12900 ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode,
12901 set->fb, set->x, set->y);
12902 if (ret)
12903 goto fail;
12904
12905 pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
12906 state);
12907 if (IS_ERR(pipe_config)) {
12908 ret = PTR_ERR(pipe_config);
12909 goto fail;
12910 }
12911
12912 /* Compute whether we need a full modeset, only an fb base update or no
12913 * change at all. In the future we might also check whether only the
12914 * mode changed, e.g. for LVDS where we only change the panel fitter in
12915 * such cases. */
12916 intel_set_config_compute_mode_changes(set, pipe_config);
12917
12918 intel_update_pipe_size(to_intel_crtc(set->crtc));
12919
12920 if (pipe_config->base.mode_changed) {
12921 ret = intel_set_mode_with_config(set->crtc, set->mode,
12922 pipe_config);
12923 } else if (pipe_config->base.planes_changed) {
12924 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
12925 struct drm_plane *primary = set->crtc->primary;
12926 struct intel_plane_state *plane_state =
12927 to_intel_plane_state(primary->state);
12928 bool was_visible = plane_state->visible;
12929 int vdisplay, hdisplay;
12930
12931 drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay);
12932 ret = drm_plane_helper_update(primary, set->crtc, set->fb,
12933 0, 0, hdisplay, vdisplay,
12934 set->x << 16, set->y << 16,
12935 hdisplay << 16, vdisplay << 16);
12936
12937 /*
12938 * We need to make sure the primary plane is re-enabled if it
12939 * has previously been turned off.
12940 */
12941 plane_state = to_intel_plane_state(primary->state);
12942 if (ret == 0 && !was_visible && plane_state->visible) {
12943 WARN_ON(!intel_crtc->active);
12944 intel_post_enable_primary(set->crtc);
12945 }
12946
12947 /*
12948 * In the fastboot case this may be our only check of the
12949 * state after boot. It would be better to only do it on
12950 * the first update, but we don't have a nice way of doing that
12951 * (and really, set_config isn't used much for high freq page
12952 * flipping, so increasing its cost here shouldn't be a big
12953 * deal).
12954 */
12955 if (i915.fastboot && ret == 0)
12956 intel_modeset_check_state(set->crtc->dev);
12957 }
12958
12959 if (ret) {
12960 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
12961 set->crtc->base.id, ret);
12962 fail:
12963 intel_set_config_restore_state(dev, config);
12964 }
12965
12966 out_config:
12967 drm_atomic_state_free(state);
12968
12969 intel_set_config_free(config);
12970 return ret;
12971 }
12972
12973 static const struct drm_crtc_funcs intel_crtc_funcs = {
12974 .gamma_set = intel_crtc_gamma_set,
12975 .set_config = intel_crtc_set_config,
12976 .destroy = intel_crtc_destroy,
12977 .page_flip = intel_crtc_page_flip,
12978 .atomic_duplicate_state = intel_crtc_duplicate_state,
12979 .atomic_destroy_state = intel_crtc_destroy_state,
12980 };
12981
12982 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
12983 struct intel_shared_dpll *pll,
12984 struct intel_dpll_hw_state *hw_state)
12985 {
12986 uint32_t val;
12987
12988 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
12989 return false;
12990
12991 val = I915_READ(PCH_DPLL(pll->id));
12992 hw_state->dpll = val;
12993 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
12994 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
12995
12996 return val & DPLL_VCO_ENABLE;
12997 }
12998
12999 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13000 struct intel_shared_dpll *pll)
13001 {
13002 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13003 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13004 }
13005
13006 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13007 struct intel_shared_dpll *pll)
13008 {
13009 /* PCH refclock must be enabled first */
13010 ibx_assert_pch_refclk_enabled(dev_priv);
13011
13012 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13013
13014 /* Wait for the clocks to stabilize. */
13015 POSTING_READ(PCH_DPLL(pll->id));
13016 udelay(150);
13017
13018 /* The pixel multiplier can only be updated once the
13019 * DPLL is enabled and the clocks are stable.
13020 *
13021 * So write it again.
13022 */
13023 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13024 POSTING_READ(PCH_DPLL(pll->id));
13025 udelay(200);
13026 }
13027
13028 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13029 struct intel_shared_dpll *pll)
13030 {
13031 struct drm_device *dev = dev_priv->dev;
13032 struct intel_crtc *crtc;
13033
13034 /* Make sure no transcoder isn't still depending on us. */
13035 for_each_intel_crtc(dev, crtc) {
13036 if (intel_crtc_to_shared_dpll(crtc) == pll)
13037 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13038 }
13039
13040 I915_WRITE(PCH_DPLL(pll->id), 0);
13041 POSTING_READ(PCH_DPLL(pll->id));
13042 udelay(200);
13043 }
13044
13045 static char *ibx_pch_dpll_names[] = {
13046 "PCH DPLL A",
13047 "PCH DPLL B",
13048 };
13049
13050 static void ibx_pch_dpll_init(struct drm_device *dev)
13051 {
13052 struct drm_i915_private *dev_priv = dev->dev_private;
13053 int i;
13054
13055 dev_priv->num_shared_dpll = 2;
13056
13057 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13058 dev_priv->shared_dplls[i].id = i;
13059 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13060 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13061 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13062 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13063 dev_priv->shared_dplls[i].get_hw_state =
13064 ibx_pch_dpll_get_hw_state;
13065 }
13066 }
13067
13068 static void intel_shared_dpll_init(struct drm_device *dev)
13069 {
13070 struct drm_i915_private *dev_priv = dev->dev_private;
13071
13072 if (HAS_DDI(dev))
13073 intel_ddi_pll_init(dev);
13074 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13075 ibx_pch_dpll_init(dev);
13076 else
13077 dev_priv->num_shared_dpll = 0;
13078
13079 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13080 }
13081
13082 /**
13083 * intel_wm_need_update - Check whether watermarks need updating
13084 * @plane: drm plane
13085 * @state: new plane state
13086 *
13087 * Check current plane state versus the new one to determine whether
13088 * watermarks need to be recalculated.
13089 *
13090 * Returns true or false.
13091 */
13092 bool intel_wm_need_update(struct drm_plane *plane,
13093 struct drm_plane_state *state)
13094 {
13095 /* Update watermarks on tiling changes. */
13096 if (!plane->state->fb || !state->fb ||
13097 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
13098 plane->state->rotation != state->rotation)
13099 return true;
13100
13101 return false;
13102 }
13103
13104 /**
13105 * intel_prepare_plane_fb - Prepare fb for usage on plane
13106 * @plane: drm plane to prepare for
13107 * @fb: framebuffer to prepare for presentation
13108 *
13109 * Prepares a framebuffer for usage on a display plane. Generally this
13110 * involves pinning the underlying object and updating the frontbuffer tracking
13111 * bits. Some older platforms need special physical address handling for
13112 * cursor planes.
13113 *
13114 * Returns 0 on success, negative error code on failure.
13115 */
13116 int
13117 intel_prepare_plane_fb(struct drm_plane *plane,
13118 struct drm_framebuffer *fb,
13119 const struct drm_plane_state *new_state)
13120 {
13121 struct drm_device *dev = plane->dev;
13122 struct intel_plane *intel_plane = to_intel_plane(plane);
13123 enum pipe pipe = intel_plane->pipe;
13124 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13125 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13126 unsigned frontbuffer_bits = 0;
13127 int ret = 0;
13128
13129 if (!obj)
13130 return 0;
13131
13132 switch (plane->type) {
13133 case DRM_PLANE_TYPE_PRIMARY:
13134 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
13135 break;
13136 case DRM_PLANE_TYPE_CURSOR:
13137 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
13138 break;
13139 case DRM_PLANE_TYPE_OVERLAY:
13140 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
13141 break;
13142 }
13143
13144 mutex_lock(&dev->struct_mutex);
13145
13146 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13147 INTEL_INFO(dev)->cursor_needs_physical) {
13148 int align = IS_I830(dev) ? 16 * 1024 : 256;
13149 ret = i915_gem_object_attach_phys(obj, align);
13150 if (ret)
13151 DRM_DEBUG_KMS("failed to attach phys object\n");
13152 } else {
13153 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
13154 }
13155
13156 if (ret == 0)
13157 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
13158
13159 mutex_unlock(&dev->struct_mutex);
13160
13161 return ret;
13162 }
13163
13164 /**
13165 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13166 * @plane: drm plane to clean up for
13167 * @fb: old framebuffer that was on plane
13168 *
13169 * Cleans up a framebuffer that has just been removed from a plane.
13170 */
13171 void
13172 intel_cleanup_plane_fb(struct drm_plane *plane,
13173 struct drm_framebuffer *fb,
13174 const struct drm_plane_state *old_state)
13175 {
13176 struct drm_device *dev = plane->dev;
13177 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13178
13179 if (WARN_ON(!obj))
13180 return;
13181
13182 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13183 !INTEL_INFO(dev)->cursor_needs_physical) {
13184 mutex_lock(&dev->struct_mutex);
13185 intel_unpin_fb_obj(fb, old_state);
13186 mutex_unlock(&dev->struct_mutex);
13187 }
13188 }
13189
13190 int
13191 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13192 {
13193 int max_scale;
13194 struct drm_device *dev;
13195 struct drm_i915_private *dev_priv;
13196 int crtc_clock, cdclk;
13197
13198 if (!intel_crtc || !crtc_state)
13199 return DRM_PLANE_HELPER_NO_SCALING;
13200
13201 dev = intel_crtc->base.dev;
13202 dev_priv = dev->dev_private;
13203 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13204 cdclk = dev_priv->display.get_display_clock_speed(dev);
13205
13206 if (!crtc_clock || !cdclk)
13207 return DRM_PLANE_HELPER_NO_SCALING;
13208
13209 /*
13210 * skl max scale is lower of:
13211 * close to 3 but not 3, -1 is for that purpose
13212 * or
13213 * cdclk/crtc_clock
13214 */
13215 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13216
13217 return max_scale;
13218 }
13219
13220 static int
13221 intel_check_primary_plane(struct drm_plane *plane,
13222 struct intel_plane_state *state)
13223 {
13224 struct drm_device *dev = plane->dev;
13225 struct drm_i915_private *dev_priv = dev->dev_private;
13226 struct drm_crtc *crtc = state->base.crtc;
13227 struct intel_crtc *intel_crtc;
13228 struct intel_crtc_state *crtc_state;
13229 struct drm_framebuffer *fb = state->base.fb;
13230 struct drm_rect *dest = &state->dst;
13231 struct drm_rect *src = &state->src;
13232 const struct drm_rect *clip = &state->clip;
13233 bool can_position = false;
13234 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13235 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13236 int ret;
13237
13238 crtc = crtc ? crtc : plane->crtc;
13239 intel_crtc = to_intel_crtc(crtc);
13240 crtc_state = state->base.state ?
13241 intel_atomic_get_crtc_state(state->base.state, intel_crtc) : NULL;
13242
13243 if (INTEL_INFO(dev)->gen >= 9) {
13244 min_scale = 1;
13245 max_scale = skl_max_scale(intel_crtc, crtc_state);
13246 can_position = true;
13247 }
13248
13249 ret = drm_plane_helper_check_update(plane, crtc, fb,
13250 src, dest, clip,
13251 min_scale,
13252 max_scale,
13253 can_position, true,
13254 &state->visible);
13255 if (ret)
13256 return ret;
13257
13258 if (intel_crtc->active) {
13259 struct intel_plane_state *old_state =
13260 to_intel_plane_state(plane->state);
13261
13262 intel_crtc->atomic.wait_for_flips = true;
13263
13264 /*
13265 * FBC does not work on some platforms for rotated
13266 * planes, so disable it when rotation is not 0 and
13267 * update it when rotation is set back to 0.
13268 *
13269 * FIXME: This is redundant with the fbc update done in
13270 * the primary plane enable function except that that
13271 * one is done too late. We eventually need to unify
13272 * this.
13273 */
13274 if (state->visible &&
13275 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
13276 dev_priv->fbc.crtc == intel_crtc &&
13277 state->base.rotation != BIT(DRM_ROTATE_0)) {
13278 intel_crtc->atomic.disable_fbc = true;
13279 }
13280
13281 if (state->visible && !old_state->visible) {
13282 /*
13283 * BDW signals flip done immediately if the plane
13284 * is disabled, even if the plane enable is already
13285 * armed to occur at the next vblank :(
13286 */
13287 if (IS_BROADWELL(dev))
13288 intel_crtc->atomic.wait_vblank = true;
13289 }
13290
13291 intel_crtc->atomic.fb_bits |=
13292 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
13293
13294 intel_crtc->atomic.update_fbc = true;
13295
13296 if (intel_wm_need_update(plane, &state->base))
13297 intel_crtc->atomic.update_wm = true;
13298 }
13299
13300 if (INTEL_INFO(dev)->gen >= 9) {
13301 ret = skl_update_scaler_users(intel_crtc, crtc_state,
13302 to_intel_plane(plane), state, 0);
13303 if (ret)
13304 return ret;
13305 }
13306
13307 return 0;
13308 }
13309
13310 static void
13311 intel_commit_primary_plane(struct drm_plane *plane,
13312 struct intel_plane_state *state)
13313 {
13314 struct drm_crtc *crtc = state->base.crtc;
13315 struct drm_framebuffer *fb = state->base.fb;
13316 struct drm_device *dev = plane->dev;
13317 struct drm_i915_private *dev_priv = dev->dev_private;
13318 struct intel_crtc *intel_crtc;
13319 struct drm_rect *src = &state->src;
13320
13321 crtc = crtc ? crtc : plane->crtc;
13322 intel_crtc = to_intel_crtc(crtc);
13323
13324 plane->fb = fb;
13325 crtc->x = src->x1 >> 16;
13326 crtc->y = src->y1 >> 16;
13327
13328 if (intel_crtc->active) {
13329 if (state->visible)
13330 /* FIXME: kill this fastboot hack */
13331 intel_update_pipe_size(intel_crtc);
13332
13333 dev_priv->display.update_primary_plane(crtc, plane->fb,
13334 crtc->x, crtc->y);
13335 }
13336 }
13337
13338 static void
13339 intel_disable_primary_plane(struct drm_plane *plane,
13340 struct drm_crtc *crtc,
13341 bool force)
13342 {
13343 struct drm_device *dev = plane->dev;
13344 struct drm_i915_private *dev_priv = dev->dev_private;
13345
13346 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13347 }
13348
13349 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
13350 {
13351 struct drm_device *dev = crtc->dev;
13352 struct drm_i915_private *dev_priv = dev->dev_private;
13353 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13354 struct intel_plane *intel_plane;
13355 struct drm_plane *p;
13356 unsigned fb_bits = 0;
13357
13358 /* Track fb's for any planes being disabled */
13359 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
13360 intel_plane = to_intel_plane(p);
13361
13362 if (intel_crtc->atomic.disabled_planes &
13363 (1 << drm_plane_index(p))) {
13364 switch (p->type) {
13365 case DRM_PLANE_TYPE_PRIMARY:
13366 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
13367 break;
13368 case DRM_PLANE_TYPE_CURSOR:
13369 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
13370 break;
13371 case DRM_PLANE_TYPE_OVERLAY:
13372 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
13373 break;
13374 }
13375
13376 mutex_lock(&dev->struct_mutex);
13377 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
13378 mutex_unlock(&dev->struct_mutex);
13379 }
13380 }
13381
13382 if (intel_crtc->atomic.wait_for_flips)
13383 intel_crtc_wait_for_pending_flips(crtc);
13384
13385 if (intel_crtc->atomic.disable_fbc)
13386 intel_fbc_disable(dev);
13387
13388 if (intel_crtc->atomic.pre_disable_primary)
13389 intel_pre_disable_primary(crtc);
13390
13391 if (intel_crtc->atomic.update_wm)
13392 intel_update_watermarks(crtc);
13393
13394 intel_runtime_pm_get(dev_priv);
13395
13396 /* Perform vblank evasion around commit operation */
13397 if (intel_crtc->active)
13398 intel_crtc->atomic.evade =
13399 intel_pipe_update_start(intel_crtc,
13400 &intel_crtc->atomic.start_vbl_count);
13401 }
13402
13403 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13404 {
13405 struct drm_device *dev = crtc->dev;
13406 struct drm_i915_private *dev_priv = dev->dev_private;
13407 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13408 struct drm_plane *p;
13409
13410 if (intel_crtc->atomic.evade)
13411 intel_pipe_update_end(intel_crtc,
13412 intel_crtc->atomic.start_vbl_count);
13413
13414 intel_runtime_pm_put(dev_priv);
13415
13416 if (intel_crtc->atomic.wait_vblank)
13417 intel_wait_for_vblank(dev, intel_crtc->pipe);
13418
13419 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
13420
13421 if (intel_crtc->atomic.update_fbc) {
13422 mutex_lock(&dev->struct_mutex);
13423 intel_fbc_update(dev);
13424 mutex_unlock(&dev->struct_mutex);
13425 }
13426
13427 if (intel_crtc->atomic.post_enable_primary)
13428 intel_post_enable_primary(crtc);
13429
13430 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
13431 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
13432 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
13433 false, false);
13434
13435 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
13436 }
13437
13438 /**
13439 * intel_plane_destroy - destroy a plane
13440 * @plane: plane to destroy
13441 *
13442 * Common destruction function for all types of planes (primary, cursor,
13443 * sprite).
13444 */
13445 void intel_plane_destroy(struct drm_plane *plane)
13446 {
13447 struct intel_plane *intel_plane = to_intel_plane(plane);
13448 drm_plane_cleanup(plane);
13449 kfree(intel_plane);
13450 }
13451
13452 const struct drm_plane_funcs intel_plane_funcs = {
13453 .update_plane = drm_atomic_helper_update_plane,
13454 .disable_plane = drm_atomic_helper_disable_plane,
13455 .destroy = intel_plane_destroy,
13456 .set_property = drm_atomic_helper_plane_set_property,
13457 .atomic_get_property = intel_plane_atomic_get_property,
13458 .atomic_set_property = intel_plane_atomic_set_property,
13459 .atomic_duplicate_state = intel_plane_duplicate_state,
13460 .atomic_destroy_state = intel_plane_destroy_state,
13461
13462 };
13463
13464 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13465 int pipe)
13466 {
13467 struct intel_plane *primary;
13468 struct intel_plane_state *state;
13469 const uint32_t *intel_primary_formats;
13470 int num_formats;
13471
13472 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13473 if (primary == NULL)
13474 return NULL;
13475
13476 state = intel_create_plane_state(&primary->base);
13477 if (!state) {
13478 kfree(primary);
13479 return NULL;
13480 }
13481 primary->base.state = &state->base;
13482
13483 primary->can_scale = false;
13484 primary->max_downscale = 1;
13485 if (INTEL_INFO(dev)->gen >= 9) {
13486 primary->can_scale = true;
13487 }
13488 state->scaler_id = -1;
13489 primary->pipe = pipe;
13490 primary->plane = pipe;
13491 primary->check_plane = intel_check_primary_plane;
13492 primary->commit_plane = intel_commit_primary_plane;
13493 primary->disable_plane = intel_disable_primary_plane;
13494 primary->ckey.flags = I915_SET_COLORKEY_NONE;
13495 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13496 primary->plane = !pipe;
13497
13498 if (INTEL_INFO(dev)->gen <= 3) {
13499 intel_primary_formats = intel_primary_formats_gen2;
13500 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
13501 } else {
13502 intel_primary_formats = intel_primary_formats_gen4;
13503 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
13504 }
13505
13506 drm_universal_plane_init(dev, &primary->base, 0,
13507 &intel_plane_funcs,
13508 intel_primary_formats, num_formats,
13509 DRM_PLANE_TYPE_PRIMARY);
13510
13511 if (INTEL_INFO(dev)->gen >= 4)
13512 intel_create_rotation_property(dev, primary);
13513
13514 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13515
13516 return &primary->base;
13517 }
13518
13519 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13520 {
13521 if (!dev->mode_config.rotation_property) {
13522 unsigned long flags = BIT(DRM_ROTATE_0) |
13523 BIT(DRM_ROTATE_180);
13524
13525 if (INTEL_INFO(dev)->gen >= 9)
13526 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13527
13528 dev->mode_config.rotation_property =
13529 drm_mode_create_rotation_property(dev, flags);
13530 }
13531 if (dev->mode_config.rotation_property)
13532 drm_object_attach_property(&plane->base.base,
13533 dev->mode_config.rotation_property,
13534 plane->base.state->rotation);
13535 }
13536
13537 static int
13538 intel_check_cursor_plane(struct drm_plane *plane,
13539 struct intel_plane_state *state)
13540 {
13541 struct drm_crtc *crtc = state->base.crtc;
13542 struct drm_device *dev = plane->dev;
13543 struct drm_framebuffer *fb = state->base.fb;
13544 struct drm_rect *dest = &state->dst;
13545 struct drm_rect *src = &state->src;
13546 const struct drm_rect *clip = &state->clip;
13547 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13548 struct intel_crtc *intel_crtc;
13549 unsigned stride;
13550 int ret;
13551
13552 crtc = crtc ? crtc : plane->crtc;
13553 intel_crtc = to_intel_crtc(crtc);
13554
13555 ret = drm_plane_helper_check_update(plane, crtc, fb,
13556 src, dest, clip,
13557 DRM_PLANE_HELPER_NO_SCALING,
13558 DRM_PLANE_HELPER_NO_SCALING,
13559 true, true, &state->visible);
13560 if (ret)
13561 return ret;
13562
13563
13564 /* if we want to turn off the cursor ignore width and height */
13565 if (!obj)
13566 goto finish;
13567
13568 /* Check for which cursor types we support */
13569 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
13570 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13571 state->base.crtc_w, state->base.crtc_h);
13572 return -EINVAL;
13573 }
13574
13575 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13576 if (obj->base.size < stride * state->base.crtc_h) {
13577 DRM_DEBUG_KMS("buffer is too small\n");
13578 return -ENOMEM;
13579 }
13580
13581 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13582 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13583 ret = -EINVAL;
13584 }
13585
13586 finish:
13587 if (intel_crtc->active) {
13588 if (plane->state->crtc_w != state->base.crtc_w)
13589 intel_crtc->atomic.update_wm = true;
13590
13591 intel_crtc->atomic.fb_bits |=
13592 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
13593 }
13594
13595 return ret;
13596 }
13597
13598 static void
13599 intel_disable_cursor_plane(struct drm_plane *plane,
13600 struct drm_crtc *crtc,
13601 bool force)
13602 {
13603 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13604
13605 if (!force) {
13606 plane->fb = NULL;
13607 intel_crtc->cursor_bo = NULL;
13608 intel_crtc->cursor_addr = 0;
13609 }
13610
13611 intel_crtc_update_cursor(crtc, false);
13612 }
13613
13614 static void
13615 intel_commit_cursor_plane(struct drm_plane *plane,
13616 struct intel_plane_state *state)
13617 {
13618 struct drm_crtc *crtc = state->base.crtc;
13619 struct drm_device *dev = plane->dev;
13620 struct intel_crtc *intel_crtc;
13621 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13622 uint32_t addr;
13623
13624 crtc = crtc ? crtc : plane->crtc;
13625 intel_crtc = to_intel_crtc(crtc);
13626
13627 plane->fb = state->base.fb;
13628 crtc->cursor_x = state->base.crtc_x;
13629 crtc->cursor_y = state->base.crtc_y;
13630
13631 if (intel_crtc->cursor_bo == obj)
13632 goto update;
13633
13634 if (!obj)
13635 addr = 0;
13636 else if (!INTEL_INFO(dev)->cursor_needs_physical)
13637 addr = i915_gem_obj_ggtt_offset(obj);
13638 else
13639 addr = obj->phys_handle->busaddr;
13640
13641 intel_crtc->cursor_addr = addr;
13642 intel_crtc->cursor_bo = obj;
13643 update:
13644
13645 if (intel_crtc->active)
13646 intel_crtc_update_cursor(crtc, state->visible);
13647 }
13648
13649 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13650 int pipe)
13651 {
13652 struct intel_plane *cursor;
13653 struct intel_plane_state *state;
13654
13655 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13656 if (cursor == NULL)
13657 return NULL;
13658
13659 state = intel_create_plane_state(&cursor->base);
13660 if (!state) {
13661 kfree(cursor);
13662 return NULL;
13663 }
13664 cursor->base.state = &state->base;
13665
13666 cursor->can_scale = false;
13667 cursor->max_downscale = 1;
13668 cursor->pipe = pipe;
13669 cursor->plane = pipe;
13670 state->scaler_id = -1;
13671 cursor->check_plane = intel_check_cursor_plane;
13672 cursor->commit_plane = intel_commit_cursor_plane;
13673 cursor->disable_plane = intel_disable_cursor_plane;
13674
13675 drm_universal_plane_init(dev, &cursor->base, 0,
13676 &intel_plane_funcs,
13677 intel_cursor_formats,
13678 ARRAY_SIZE(intel_cursor_formats),
13679 DRM_PLANE_TYPE_CURSOR);
13680
13681 if (INTEL_INFO(dev)->gen >= 4) {
13682 if (!dev->mode_config.rotation_property)
13683 dev->mode_config.rotation_property =
13684 drm_mode_create_rotation_property(dev,
13685 BIT(DRM_ROTATE_0) |
13686 BIT(DRM_ROTATE_180));
13687 if (dev->mode_config.rotation_property)
13688 drm_object_attach_property(&cursor->base.base,
13689 dev->mode_config.rotation_property,
13690 state->base.rotation);
13691 }
13692
13693 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13694
13695 return &cursor->base;
13696 }
13697
13698 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13699 struct intel_crtc_state *crtc_state)
13700 {
13701 int i;
13702 struct intel_scaler *intel_scaler;
13703 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13704
13705 for (i = 0; i < intel_crtc->num_scalers; i++) {
13706 intel_scaler = &scaler_state->scalers[i];
13707 intel_scaler->in_use = 0;
13708 intel_scaler->id = i;
13709
13710 intel_scaler->mode = PS_SCALER_MODE_DYN;
13711 }
13712
13713 scaler_state->scaler_id = -1;
13714 }
13715
13716 static void intel_crtc_init(struct drm_device *dev, int pipe)
13717 {
13718 struct drm_i915_private *dev_priv = dev->dev_private;
13719 struct intel_crtc *intel_crtc;
13720 struct intel_crtc_state *crtc_state = NULL;
13721 struct drm_plane *primary = NULL;
13722 struct drm_plane *cursor = NULL;
13723 int i, ret;
13724
13725 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13726 if (intel_crtc == NULL)
13727 return;
13728
13729 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13730 if (!crtc_state)
13731 goto fail;
13732 intel_crtc_set_state(intel_crtc, crtc_state);
13733 crtc_state->base.crtc = &intel_crtc->base;
13734
13735 /* initialize shared scalers */
13736 if (INTEL_INFO(dev)->gen >= 9) {
13737 if (pipe == PIPE_C)
13738 intel_crtc->num_scalers = 1;
13739 else
13740 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13741
13742 skl_init_scalers(dev, intel_crtc, crtc_state);
13743 }
13744
13745 primary = intel_primary_plane_create(dev, pipe);
13746 if (!primary)
13747 goto fail;
13748
13749 cursor = intel_cursor_plane_create(dev, pipe);
13750 if (!cursor)
13751 goto fail;
13752
13753 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
13754 cursor, &intel_crtc_funcs);
13755 if (ret)
13756 goto fail;
13757
13758 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
13759 for (i = 0; i < 256; i++) {
13760 intel_crtc->lut_r[i] = i;
13761 intel_crtc->lut_g[i] = i;
13762 intel_crtc->lut_b[i] = i;
13763 }
13764
13765 /*
13766 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13767 * is hooked to pipe B. Hence we want plane A feeding pipe B.
13768 */
13769 intel_crtc->pipe = pipe;
13770 intel_crtc->plane = pipe;
13771 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
13772 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13773 intel_crtc->plane = !pipe;
13774 }
13775
13776 intel_crtc->cursor_base = ~0;
13777 intel_crtc->cursor_cntl = ~0;
13778 intel_crtc->cursor_size = ~0;
13779
13780 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13781 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13782 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13783 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13784
13785 INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
13786
13787 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13788
13789 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13790 return;
13791
13792 fail:
13793 if (primary)
13794 drm_plane_cleanup(primary);
13795 if (cursor)
13796 drm_plane_cleanup(cursor);
13797 kfree(crtc_state);
13798 kfree(intel_crtc);
13799 }
13800
13801 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13802 {
13803 struct drm_encoder *encoder = connector->base.encoder;
13804 struct drm_device *dev = connector->base.dev;
13805
13806 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13807
13808 if (!encoder || WARN_ON(!encoder->crtc))
13809 return INVALID_PIPE;
13810
13811 return to_intel_crtc(encoder->crtc)->pipe;
13812 }
13813
13814 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13815 struct drm_file *file)
13816 {
13817 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13818 struct drm_crtc *drmmode_crtc;
13819 struct intel_crtc *crtc;
13820
13821 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13822
13823 if (!drmmode_crtc) {
13824 DRM_ERROR("no such CRTC id\n");
13825 return -ENOENT;
13826 }
13827
13828 crtc = to_intel_crtc(drmmode_crtc);
13829 pipe_from_crtc_id->pipe = crtc->pipe;
13830
13831 return 0;
13832 }
13833
13834 static int intel_encoder_clones(struct intel_encoder *encoder)
13835 {
13836 struct drm_device *dev = encoder->base.dev;
13837 struct intel_encoder *source_encoder;
13838 int index_mask = 0;
13839 int entry = 0;
13840
13841 for_each_intel_encoder(dev, source_encoder) {
13842 if (encoders_cloneable(encoder, source_encoder))
13843 index_mask |= (1 << entry);
13844
13845 entry++;
13846 }
13847
13848 return index_mask;
13849 }
13850
13851 static bool has_edp_a(struct drm_device *dev)
13852 {
13853 struct drm_i915_private *dev_priv = dev->dev_private;
13854
13855 if (!IS_MOBILE(dev))
13856 return false;
13857
13858 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13859 return false;
13860
13861 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13862 return false;
13863
13864 return true;
13865 }
13866
13867 static bool intel_crt_present(struct drm_device *dev)
13868 {
13869 struct drm_i915_private *dev_priv = dev->dev_private;
13870
13871 if (INTEL_INFO(dev)->gen >= 9)
13872 return false;
13873
13874 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
13875 return false;
13876
13877 if (IS_CHERRYVIEW(dev))
13878 return false;
13879
13880 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13881 return false;
13882
13883 return true;
13884 }
13885
13886 static void intel_setup_outputs(struct drm_device *dev)
13887 {
13888 struct drm_i915_private *dev_priv = dev->dev_private;
13889 struct intel_encoder *encoder;
13890 bool dpd_is_edp = false;
13891
13892 intel_lvds_init(dev);
13893
13894 if (intel_crt_present(dev))
13895 intel_crt_init(dev);
13896
13897 if (IS_BROXTON(dev)) {
13898 /*
13899 * FIXME: Broxton doesn't support port detection via the
13900 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13901 * detect the ports.
13902 */
13903 intel_ddi_init(dev, PORT_A);
13904 intel_ddi_init(dev, PORT_B);
13905 intel_ddi_init(dev, PORT_C);
13906 } else if (HAS_DDI(dev)) {
13907 int found;
13908
13909 /*
13910 * Haswell uses DDI functions to detect digital outputs.
13911 * On SKL pre-D0 the strap isn't connected, so we assume
13912 * it's there.
13913 */
13914 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
13915 /* WaIgnoreDDIAStrap: skl */
13916 if (found ||
13917 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
13918 intel_ddi_init(dev, PORT_A);
13919
13920 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13921 * register */
13922 found = I915_READ(SFUSE_STRAP);
13923
13924 if (found & SFUSE_STRAP_DDIB_DETECTED)
13925 intel_ddi_init(dev, PORT_B);
13926 if (found & SFUSE_STRAP_DDIC_DETECTED)
13927 intel_ddi_init(dev, PORT_C);
13928 if (found & SFUSE_STRAP_DDID_DETECTED)
13929 intel_ddi_init(dev, PORT_D);
13930 } else if (HAS_PCH_SPLIT(dev)) {
13931 int found;
13932 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
13933
13934 if (has_edp_a(dev))
13935 intel_dp_init(dev, DP_A, PORT_A);
13936
13937 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
13938 /* PCH SDVOB multiplex with HDMIB */
13939 found = intel_sdvo_init(dev, PCH_SDVOB, true);
13940 if (!found)
13941 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
13942 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
13943 intel_dp_init(dev, PCH_DP_B, PORT_B);
13944 }
13945
13946 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
13947 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
13948
13949 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
13950 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
13951
13952 if (I915_READ(PCH_DP_C) & DP_DETECTED)
13953 intel_dp_init(dev, PCH_DP_C, PORT_C);
13954
13955 if (I915_READ(PCH_DP_D) & DP_DETECTED)
13956 intel_dp_init(dev, PCH_DP_D, PORT_D);
13957 } else if (IS_VALLEYVIEW(dev)) {
13958 /*
13959 * The DP_DETECTED bit is the latched state of the DDC
13960 * SDA pin at boot. However since eDP doesn't require DDC
13961 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13962 * eDP ports may have been muxed to an alternate function.
13963 * Thus we can't rely on the DP_DETECTED bit alone to detect
13964 * eDP ports. Consult the VBT as well as DP_DETECTED to
13965 * detect eDP ports.
13966 */
13967 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
13968 !intel_dp_is_edp(dev, PORT_B))
13969 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
13970 PORT_B);
13971 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
13972 intel_dp_is_edp(dev, PORT_B))
13973 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
13974
13975 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
13976 !intel_dp_is_edp(dev, PORT_C))
13977 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
13978 PORT_C);
13979 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
13980 intel_dp_is_edp(dev, PORT_C))
13981 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
13982
13983 if (IS_CHERRYVIEW(dev)) {
13984 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
13985 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
13986 PORT_D);
13987 /* eDP not supported on port D, so don't check VBT */
13988 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
13989 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
13990 }
13991
13992 intel_dsi_init(dev);
13993 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
13994 bool found = false;
13995
13996 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13997 DRM_DEBUG_KMS("probing SDVOB\n");
13998 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
13999 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
14000 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14001 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14002 }
14003
14004 if (!found && SUPPORTS_INTEGRATED_DP(dev))
14005 intel_dp_init(dev, DP_B, PORT_B);
14006 }
14007
14008 /* Before G4X SDVOC doesn't have its own detect register */
14009
14010 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14011 DRM_DEBUG_KMS("probing SDVOC\n");
14012 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
14013 }
14014
14015 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14016
14017 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
14018 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14019 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14020 }
14021 if (SUPPORTS_INTEGRATED_DP(dev))
14022 intel_dp_init(dev, DP_C, PORT_C);
14023 }
14024
14025 if (SUPPORTS_INTEGRATED_DP(dev) &&
14026 (I915_READ(DP_D) & DP_DETECTED))
14027 intel_dp_init(dev, DP_D, PORT_D);
14028 } else if (IS_GEN2(dev))
14029 intel_dvo_init(dev);
14030
14031 if (SUPPORTS_TV(dev))
14032 intel_tv_init(dev);
14033
14034 intel_psr_init(dev);
14035
14036 for_each_intel_encoder(dev, encoder) {
14037 encoder->base.possible_crtcs = encoder->crtc_mask;
14038 encoder->base.possible_clones =
14039 intel_encoder_clones(encoder);
14040 }
14041
14042 intel_init_pch_refclk(dev);
14043
14044 drm_helper_move_panel_connectors_to_head(dev);
14045 }
14046
14047 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14048 {
14049 struct drm_device *dev = fb->dev;
14050 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14051
14052 drm_framebuffer_cleanup(fb);
14053 mutex_lock(&dev->struct_mutex);
14054 WARN_ON(!intel_fb->obj->framebuffer_references--);
14055 drm_gem_object_unreference(&intel_fb->obj->base);
14056 mutex_unlock(&dev->struct_mutex);
14057 kfree(intel_fb);
14058 }
14059
14060 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14061 struct drm_file *file,
14062 unsigned int *handle)
14063 {
14064 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14065 struct drm_i915_gem_object *obj = intel_fb->obj;
14066
14067 return drm_gem_handle_create(file, &obj->base, handle);
14068 }
14069
14070 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14071 .destroy = intel_user_framebuffer_destroy,
14072 .create_handle = intel_user_framebuffer_create_handle,
14073 };
14074
14075 static
14076 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14077 uint32_t pixel_format)
14078 {
14079 u32 gen = INTEL_INFO(dev)->gen;
14080
14081 if (gen >= 9) {
14082 /* "The stride in bytes must not exceed the of the size of 8K
14083 * pixels and 32K bytes."
14084 */
14085 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14086 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14087 return 32*1024;
14088 } else if (gen >= 4) {
14089 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14090 return 16*1024;
14091 else
14092 return 32*1024;
14093 } else if (gen >= 3) {
14094 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14095 return 8*1024;
14096 else
14097 return 16*1024;
14098 } else {
14099 /* XXX DSPC is limited to 4k tiled */
14100 return 8*1024;
14101 }
14102 }
14103
14104 static int intel_framebuffer_init(struct drm_device *dev,
14105 struct intel_framebuffer *intel_fb,
14106 struct drm_mode_fb_cmd2 *mode_cmd,
14107 struct drm_i915_gem_object *obj)
14108 {
14109 unsigned int aligned_height;
14110 int ret;
14111 u32 pitch_limit, stride_alignment;
14112
14113 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14114
14115 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14116 /* Enforce that fb modifier and tiling mode match, but only for
14117 * X-tiled. This is needed for FBC. */
14118 if (!!(obj->tiling_mode == I915_TILING_X) !=
14119 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14120 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14121 return -EINVAL;
14122 }
14123 } else {
14124 if (obj->tiling_mode == I915_TILING_X)
14125 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14126 else if (obj->tiling_mode == I915_TILING_Y) {
14127 DRM_DEBUG("No Y tiling for legacy addfb\n");
14128 return -EINVAL;
14129 }
14130 }
14131
14132 /* Passed in modifier sanity checking. */
14133 switch (mode_cmd->modifier[0]) {
14134 case I915_FORMAT_MOD_Y_TILED:
14135 case I915_FORMAT_MOD_Yf_TILED:
14136 if (INTEL_INFO(dev)->gen < 9) {
14137 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14138 mode_cmd->modifier[0]);
14139 return -EINVAL;
14140 }
14141 case DRM_FORMAT_MOD_NONE:
14142 case I915_FORMAT_MOD_X_TILED:
14143 break;
14144 default:
14145 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14146 mode_cmd->modifier[0]);
14147 return -EINVAL;
14148 }
14149
14150 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14151 mode_cmd->pixel_format);
14152 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14153 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14154 mode_cmd->pitches[0], stride_alignment);
14155 return -EINVAL;
14156 }
14157
14158 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14159 mode_cmd->pixel_format);
14160 if (mode_cmd->pitches[0] > pitch_limit) {
14161 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14162 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14163 "tiled" : "linear",
14164 mode_cmd->pitches[0], pitch_limit);
14165 return -EINVAL;
14166 }
14167
14168 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14169 mode_cmd->pitches[0] != obj->stride) {
14170 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14171 mode_cmd->pitches[0], obj->stride);
14172 return -EINVAL;
14173 }
14174
14175 /* Reject formats not supported by any plane early. */
14176 switch (mode_cmd->pixel_format) {
14177 case DRM_FORMAT_C8:
14178 case DRM_FORMAT_RGB565:
14179 case DRM_FORMAT_XRGB8888:
14180 case DRM_FORMAT_ARGB8888:
14181 break;
14182 case DRM_FORMAT_XRGB1555:
14183 case DRM_FORMAT_ARGB1555:
14184 if (INTEL_INFO(dev)->gen > 3) {
14185 DRM_DEBUG("unsupported pixel format: %s\n",
14186 drm_get_format_name(mode_cmd->pixel_format));
14187 return -EINVAL;
14188 }
14189 break;
14190 case DRM_FORMAT_XBGR8888:
14191 case DRM_FORMAT_ABGR8888:
14192 case DRM_FORMAT_XRGB2101010:
14193 case DRM_FORMAT_ARGB2101010:
14194 case DRM_FORMAT_XBGR2101010:
14195 case DRM_FORMAT_ABGR2101010:
14196 if (INTEL_INFO(dev)->gen < 4) {
14197 DRM_DEBUG("unsupported pixel format: %s\n",
14198 drm_get_format_name(mode_cmd->pixel_format));
14199 return -EINVAL;
14200 }
14201 break;
14202 case DRM_FORMAT_YUYV:
14203 case DRM_FORMAT_UYVY:
14204 case DRM_FORMAT_YVYU:
14205 case DRM_FORMAT_VYUY:
14206 if (INTEL_INFO(dev)->gen < 5) {
14207 DRM_DEBUG("unsupported pixel format: %s\n",
14208 drm_get_format_name(mode_cmd->pixel_format));
14209 return -EINVAL;
14210 }
14211 break;
14212 default:
14213 DRM_DEBUG("unsupported pixel format: %s\n",
14214 drm_get_format_name(mode_cmd->pixel_format));
14215 return -EINVAL;
14216 }
14217
14218 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14219 if (mode_cmd->offsets[0] != 0)
14220 return -EINVAL;
14221
14222 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14223 mode_cmd->pixel_format,
14224 mode_cmd->modifier[0]);
14225 /* FIXME drm helper for size checks (especially planar formats)? */
14226 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14227 return -EINVAL;
14228
14229 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14230 intel_fb->obj = obj;
14231 intel_fb->obj->framebuffer_references++;
14232
14233 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14234 if (ret) {
14235 DRM_ERROR("framebuffer init failed %d\n", ret);
14236 return ret;
14237 }
14238
14239 return 0;
14240 }
14241
14242 static struct drm_framebuffer *
14243 intel_user_framebuffer_create(struct drm_device *dev,
14244 struct drm_file *filp,
14245 struct drm_mode_fb_cmd2 *mode_cmd)
14246 {
14247 struct drm_i915_gem_object *obj;
14248
14249 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14250 mode_cmd->handles[0]));
14251 if (&obj->base == NULL)
14252 return ERR_PTR(-ENOENT);
14253
14254 return intel_framebuffer_create(dev, mode_cmd, obj);
14255 }
14256
14257 #ifndef CONFIG_DRM_I915_FBDEV
14258 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14259 {
14260 }
14261 #endif
14262
14263 static const struct drm_mode_config_funcs intel_mode_funcs = {
14264 .fb_create = intel_user_framebuffer_create,
14265 .output_poll_changed = intel_fbdev_output_poll_changed,
14266 .atomic_check = intel_atomic_check,
14267 .atomic_commit = intel_atomic_commit,
14268 };
14269
14270 /* Set up chip specific display functions */
14271 static void intel_init_display(struct drm_device *dev)
14272 {
14273 struct drm_i915_private *dev_priv = dev->dev_private;
14274
14275 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14276 dev_priv->display.find_dpll = g4x_find_best_dpll;
14277 else if (IS_CHERRYVIEW(dev))
14278 dev_priv->display.find_dpll = chv_find_best_dpll;
14279 else if (IS_VALLEYVIEW(dev))
14280 dev_priv->display.find_dpll = vlv_find_best_dpll;
14281 else if (IS_PINEVIEW(dev))
14282 dev_priv->display.find_dpll = pnv_find_best_dpll;
14283 else
14284 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14285
14286 if (INTEL_INFO(dev)->gen >= 9) {
14287 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14288 dev_priv->display.get_initial_plane_config =
14289 skylake_get_initial_plane_config;
14290 dev_priv->display.crtc_compute_clock =
14291 haswell_crtc_compute_clock;
14292 dev_priv->display.crtc_enable = haswell_crtc_enable;
14293 dev_priv->display.crtc_disable = haswell_crtc_disable;
14294 dev_priv->display.off = ironlake_crtc_off;
14295 dev_priv->display.update_primary_plane =
14296 skylake_update_primary_plane;
14297 } else if (HAS_DDI(dev)) {
14298 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14299 dev_priv->display.get_initial_plane_config =
14300 ironlake_get_initial_plane_config;
14301 dev_priv->display.crtc_compute_clock =
14302 haswell_crtc_compute_clock;
14303 dev_priv->display.crtc_enable = haswell_crtc_enable;
14304 dev_priv->display.crtc_disable = haswell_crtc_disable;
14305 dev_priv->display.off = ironlake_crtc_off;
14306 dev_priv->display.update_primary_plane =
14307 ironlake_update_primary_plane;
14308 } else if (HAS_PCH_SPLIT(dev)) {
14309 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14310 dev_priv->display.get_initial_plane_config =
14311 ironlake_get_initial_plane_config;
14312 dev_priv->display.crtc_compute_clock =
14313 ironlake_crtc_compute_clock;
14314 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14315 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14316 dev_priv->display.off = ironlake_crtc_off;
14317 dev_priv->display.update_primary_plane =
14318 ironlake_update_primary_plane;
14319 } else if (IS_VALLEYVIEW(dev)) {
14320 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14321 dev_priv->display.get_initial_plane_config =
14322 i9xx_get_initial_plane_config;
14323 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14324 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14325 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14326 dev_priv->display.off = i9xx_crtc_off;
14327 dev_priv->display.update_primary_plane =
14328 i9xx_update_primary_plane;
14329 } else {
14330 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14331 dev_priv->display.get_initial_plane_config =
14332 i9xx_get_initial_plane_config;
14333 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14334 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14335 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14336 dev_priv->display.off = i9xx_crtc_off;
14337 dev_priv->display.update_primary_plane =
14338 i9xx_update_primary_plane;
14339 }
14340
14341 /* Returns the core display clock speed */
14342 if (IS_SKYLAKE(dev))
14343 dev_priv->display.get_display_clock_speed =
14344 skylake_get_display_clock_speed;
14345 else if (IS_BROADWELL(dev))
14346 dev_priv->display.get_display_clock_speed =
14347 broadwell_get_display_clock_speed;
14348 else if (IS_HASWELL(dev))
14349 dev_priv->display.get_display_clock_speed =
14350 haswell_get_display_clock_speed;
14351 else if (IS_VALLEYVIEW(dev))
14352 dev_priv->display.get_display_clock_speed =
14353 valleyview_get_display_clock_speed;
14354 else if (IS_GEN5(dev))
14355 dev_priv->display.get_display_clock_speed =
14356 ilk_get_display_clock_speed;
14357 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14358 IS_GEN6(dev) || IS_IVYBRIDGE(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
14359 dev_priv->display.get_display_clock_speed =
14360 i945_get_display_clock_speed;
14361 else if (IS_I915G(dev))
14362 dev_priv->display.get_display_clock_speed =
14363 i915_get_display_clock_speed;
14364 else if (IS_I945GM(dev) || IS_845G(dev))
14365 dev_priv->display.get_display_clock_speed =
14366 i9xx_misc_get_display_clock_speed;
14367 else if (IS_PINEVIEW(dev))
14368 dev_priv->display.get_display_clock_speed =
14369 pnv_get_display_clock_speed;
14370 else if (IS_I915GM(dev))
14371 dev_priv->display.get_display_clock_speed =
14372 i915gm_get_display_clock_speed;
14373 else if (IS_I865G(dev))
14374 dev_priv->display.get_display_clock_speed =
14375 i865_get_display_clock_speed;
14376 else if (IS_I85X(dev))
14377 dev_priv->display.get_display_clock_speed =
14378 i855_get_display_clock_speed;
14379 else /* 852, 830 */
14380 dev_priv->display.get_display_clock_speed =
14381 i830_get_display_clock_speed;
14382
14383 if (IS_GEN5(dev)) {
14384 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14385 } else if (IS_GEN6(dev)) {
14386 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14387 } else if (IS_IVYBRIDGE(dev)) {
14388 /* FIXME: detect B0+ stepping and use auto training */
14389 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14390 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14391 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14392 } else if (IS_VALLEYVIEW(dev)) {
14393 dev_priv->display.modeset_global_resources =
14394 valleyview_modeset_global_resources;
14395 } else if (IS_BROXTON(dev)) {
14396 dev_priv->display.modeset_global_resources =
14397 broxton_modeset_global_resources;
14398 }
14399
14400 switch (INTEL_INFO(dev)->gen) {
14401 case 2:
14402 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14403 break;
14404
14405 case 3:
14406 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14407 break;
14408
14409 case 4:
14410 case 5:
14411 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14412 break;
14413
14414 case 6:
14415 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14416 break;
14417 case 7:
14418 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14419 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14420 break;
14421 case 9:
14422 /* Drop through - unsupported since execlist only. */
14423 default:
14424 /* Default just returns -ENODEV to indicate unsupported */
14425 dev_priv->display.queue_flip = intel_default_queue_flip;
14426 }
14427
14428 intel_panel_init_backlight_funcs(dev);
14429
14430 mutex_init(&dev_priv->pps_mutex);
14431 }
14432
14433 /*
14434 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14435 * resume, or other times. This quirk makes sure that's the case for
14436 * affected systems.
14437 */
14438 static void quirk_pipea_force(struct drm_device *dev)
14439 {
14440 struct drm_i915_private *dev_priv = dev->dev_private;
14441
14442 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14443 DRM_INFO("applying pipe a force quirk\n");
14444 }
14445
14446 static void quirk_pipeb_force(struct drm_device *dev)
14447 {
14448 struct drm_i915_private *dev_priv = dev->dev_private;
14449
14450 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14451 DRM_INFO("applying pipe b force quirk\n");
14452 }
14453
14454 /*
14455 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14456 */
14457 static void quirk_ssc_force_disable(struct drm_device *dev)
14458 {
14459 struct drm_i915_private *dev_priv = dev->dev_private;
14460 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14461 DRM_INFO("applying lvds SSC disable quirk\n");
14462 }
14463
14464 /*
14465 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14466 * brightness value
14467 */
14468 static void quirk_invert_brightness(struct drm_device *dev)
14469 {
14470 struct drm_i915_private *dev_priv = dev->dev_private;
14471 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14472 DRM_INFO("applying inverted panel brightness quirk\n");
14473 }
14474
14475 /* Some VBT's incorrectly indicate no backlight is present */
14476 static void quirk_backlight_present(struct drm_device *dev)
14477 {
14478 struct drm_i915_private *dev_priv = dev->dev_private;
14479 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14480 DRM_INFO("applying backlight present quirk\n");
14481 }
14482
14483 struct intel_quirk {
14484 int device;
14485 int subsystem_vendor;
14486 int subsystem_device;
14487 void (*hook)(struct drm_device *dev);
14488 };
14489
14490 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14491 struct intel_dmi_quirk {
14492 void (*hook)(struct drm_device *dev);
14493 const struct dmi_system_id (*dmi_id_list)[];
14494 };
14495
14496 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14497 {
14498 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14499 return 1;
14500 }
14501
14502 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14503 {
14504 .dmi_id_list = &(const struct dmi_system_id[]) {
14505 {
14506 .callback = intel_dmi_reverse_brightness,
14507 .ident = "NCR Corporation",
14508 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14509 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14510 },
14511 },
14512 { } /* terminating entry */
14513 },
14514 .hook = quirk_invert_brightness,
14515 },
14516 };
14517
14518 static struct intel_quirk intel_quirks[] = {
14519 /* HP Mini needs pipe A force quirk (LP: #322104) */
14520 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
14521
14522 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14523 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14524
14525 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14526 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14527
14528 /* 830 needs to leave pipe A & dpll A up */
14529 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14530
14531 /* 830 needs to leave pipe B & dpll B up */
14532 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14533
14534 /* Lenovo U160 cannot use SSC on LVDS */
14535 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14536
14537 /* Sony Vaio Y cannot use SSC on LVDS */
14538 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14539
14540 /* Acer Aspire 5734Z must invert backlight brightness */
14541 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14542
14543 /* Acer/eMachines G725 */
14544 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14545
14546 /* Acer/eMachines e725 */
14547 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14548
14549 /* Acer/Packard Bell NCL20 */
14550 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14551
14552 /* Acer Aspire 4736Z */
14553 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14554
14555 /* Acer Aspire 5336 */
14556 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14557
14558 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14559 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14560
14561 /* Acer C720 Chromebook (Core i3 4005U) */
14562 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14563
14564 /* Apple Macbook 2,1 (Core 2 T7400) */
14565 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14566
14567 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14568 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14569
14570 /* HP Chromebook 14 (Celeron 2955U) */
14571 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14572
14573 /* Dell Chromebook 11 */
14574 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14575 };
14576
14577 static void intel_init_quirks(struct drm_device *dev)
14578 {
14579 struct pci_dev *d = dev->pdev;
14580 int i;
14581
14582 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14583 struct intel_quirk *q = &intel_quirks[i];
14584
14585 if (d->device == q->device &&
14586 (d->subsystem_vendor == q->subsystem_vendor ||
14587 q->subsystem_vendor == PCI_ANY_ID) &&
14588 (d->subsystem_device == q->subsystem_device ||
14589 q->subsystem_device == PCI_ANY_ID))
14590 q->hook(dev);
14591 }
14592 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14593 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14594 intel_dmi_quirks[i].hook(dev);
14595 }
14596 }
14597
14598 /* Disable the VGA plane that we never use */
14599 static void i915_disable_vga(struct drm_device *dev)
14600 {
14601 struct drm_i915_private *dev_priv = dev->dev_private;
14602 u8 sr1;
14603 u32 vga_reg = i915_vgacntrl_reg(dev);
14604
14605 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14606 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14607 outb(SR01, VGA_SR_INDEX);
14608 sr1 = inb(VGA_SR_DATA);
14609 outb(sr1 | 1<<5, VGA_SR_DATA);
14610 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14611 udelay(300);
14612
14613 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14614 POSTING_READ(vga_reg);
14615 }
14616
14617 void intel_modeset_init_hw(struct drm_device *dev)
14618 {
14619 intel_prepare_ddi(dev);
14620
14621 if (IS_VALLEYVIEW(dev))
14622 vlv_update_cdclk(dev);
14623
14624 intel_init_clock_gating(dev);
14625
14626 intel_enable_gt_powersave(dev);
14627 }
14628
14629 void intel_modeset_init(struct drm_device *dev)
14630 {
14631 struct drm_i915_private *dev_priv = dev->dev_private;
14632 int sprite, ret;
14633 enum pipe pipe;
14634 struct intel_crtc *crtc;
14635
14636 drm_mode_config_init(dev);
14637
14638 dev->mode_config.min_width = 0;
14639 dev->mode_config.min_height = 0;
14640
14641 dev->mode_config.preferred_depth = 24;
14642 dev->mode_config.prefer_shadow = 1;
14643
14644 dev->mode_config.allow_fb_modifiers = true;
14645
14646 dev->mode_config.funcs = &intel_mode_funcs;
14647
14648 intel_init_quirks(dev);
14649
14650 intel_init_pm(dev);
14651
14652 if (INTEL_INFO(dev)->num_pipes == 0)
14653 return;
14654
14655 intel_init_display(dev);
14656 intel_init_audio(dev);
14657
14658 if (IS_GEN2(dev)) {
14659 dev->mode_config.max_width = 2048;
14660 dev->mode_config.max_height = 2048;
14661 } else if (IS_GEN3(dev)) {
14662 dev->mode_config.max_width = 4096;
14663 dev->mode_config.max_height = 4096;
14664 } else {
14665 dev->mode_config.max_width = 8192;
14666 dev->mode_config.max_height = 8192;
14667 }
14668
14669 if (IS_845G(dev) || IS_I865G(dev)) {
14670 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14671 dev->mode_config.cursor_height = 1023;
14672 } else if (IS_GEN2(dev)) {
14673 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14674 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14675 } else {
14676 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14677 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14678 }
14679
14680 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
14681
14682 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14683 INTEL_INFO(dev)->num_pipes,
14684 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
14685
14686 for_each_pipe(dev_priv, pipe) {
14687 intel_crtc_init(dev, pipe);
14688 for_each_sprite(dev_priv, pipe, sprite) {
14689 ret = intel_plane_init(dev, pipe, sprite);
14690 if (ret)
14691 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14692 pipe_name(pipe), sprite_name(pipe, sprite), ret);
14693 }
14694 }
14695
14696 intel_init_dpio(dev);
14697
14698 intel_shared_dpll_init(dev);
14699
14700 /* Just disable it once at startup */
14701 i915_disable_vga(dev);
14702 intel_setup_outputs(dev);
14703
14704 /* Just in case the BIOS is doing something questionable. */
14705 intel_fbc_disable(dev);
14706
14707 drm_modeset_lock_all(dev);
14708 intel_modeset_setup_hw_state(dev, false);
14709 drm_modeset_unlock_all(dev);
14710
14711 for_each_intel_crtc(dev, crtc) {
14712 if (!crtc->active)
14713 continue;
14714
14715 /*
14716 * Note that reserving the BIOS fb up front prevents us
14717 * from stuffing other stolen allocations like the ring
14718 * on top. This prevents some ugliness at boot time, and
14719 * can even allow for smooth boot transitions if the BIOS
14720 * fb is large enough for the active pipe configuration.
14721 */
14722 if (dev_priv->display.get_initial_plane_config) {
14723 dev_priv->display.get_initial_plane_config(crtc,
14724 &crtc->plane_config);
14725 /*
14726 * If the fb is shared between multiple heads, we'll
14727 * just get the first one.
14728 */
14729 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
14730 }
14731 }
14732 }
14733
14734 static void intel_enable_pipe_a(struct drm_device *dev)
14735 {
14736 struct intel_connector *connector;
14737 struct drm_connector *crt = NULL;
14738 struct intel_load_detect_pipe load_detect_temp;
14739 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
14740
14741 /* We can't just switch on the pipe A, we need to set things up with a
14742 * proper mode and output configuration. As a gross hack, enable pipe A
14743 * by enabling the load detect pipe once. */
14744 for_each_intel_connector(dev, connector) {
14745 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14746 crt = &connector->base;
14747 break;
14748 }
14749 }
14750
14751 if (!crt)
14752 return;
14753
14754 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
14755 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
14756 }
14757
14758 static bool
14759 intel_check_plane_mapping(struct intel_crtc *crtc)
14760 {
14761 struct drm_device *dev = crtc->base.dev;
14762 struct drm_i915_private *dev_priv = dev->dev_private;
14763 u32 reg, val;
14764
14765 if (INTEL_INFO(dev)->num_pipes == 1)
14766 return true;
14767
14768 reg = DSPCNTR(!crtc->plane);
14769 val = I915_READ(reg);
14770
14771 if ((val & DISPLAY_PLANE_ENABLE) &&
14772 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14773 return false;
14774
14775 return true;
14776 }
14777
14778 static void intel_sanitize_crtc(struct intel_crtc *crtc)
14779 {
14780 struct drm_device *dev = crtc->base.dev;
14781 struct drm_i915_private *dev_priv = dev->dev_private;
14782 u32 reg;
14783
14784 /* Clear any frame start delays used for debugging left by the BIOS */
14785 reg = PIPECONF(crtc->config->cpu_transcoder);
14786 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14787
14788 /* restore vblank interrupts to correct state */
14789 drm_crtc_vblank_reset(&crtc->base);
14790 if (crtc->active) {
14791 update_scanline_offset(crtc);
14792 drm_crtc_vblank_on(&crtc->base);
14793 }
14794
14795 /* We need to sanitize the plane -> pipe mapping first because this will
14796 * disable the crtc (and hence change the state) if it is wrong. Note
14797 * that gen4+ has a fixed plane -> pipe mapping. */
14798 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
14799 struct intel_connector *connector;
14800 bool plane;
14801
14802 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14803 crtc->base.base.id);
14804
14805 /* Pipe has the wrong plane attached and the plane is active.
14806 * Temporarily change the plane mapping and disable everything
14807 * ... */
14808 plane = crtc->plane;
14809 to_intel_plane_state(crtc->base.primary->state)->visible = true;
14810 crtc->plane = !plane;
14811 intel_crtc_disable_planes(&crtc->base);
14812 dev_priv->display.crtc_disable(&crtc->base);
14813 crtc->plane = plane;
14814
14815 /* ... and break all links. */
14816 for_each_intel_connector(dev, connector) {
14817 if (connector->encoder->base.crtc != &crtc->base)
14818 continue;
14819
14820 connector->base.dpms = DRM_MODE_DPMS_OFF;
14821 connector->base.encoder = NULL;
14822 }
14823 /* multiple connectors may have the same encoder:
14824 * handle them and break crtc link separately */
14825 for_each_intel_connector(dev, connector)
14826 if (connector->encoder->base.crtc == &crtc->base) {
14827 connector->encoder->base.crtc = NULL;
14828 connector->encoder->connectors_active = false;
14829 }
14830
14831 WARN_ON(crtc->active);
14832 crtc->base.state->enable = false;
14833 crtc->base.enabled = false;
14834 }
14835
14836 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14837 crtc->pipe == PIPE_A && !crtc->active) {
14838 /* BIOS forgot to enable pipe A, this mostly happens after
14839 * resume. Force-enable the pipe to fix this, the update_dpms
14840 * call below we restore the pipe to the right state, but leave
14841 * the required bits on. */
14842 intel_enable_pipe_a(dev);
14843 }
14844
14845 /* Adjust the state of the output pipe according to whether we
14846 * have active connectors/encoders. */
14847 intel_crtc_update_dpms(&crtc->base);
14848
14849 if (crtc->active != crtc->base.state->enable) {
14850 struct intel_encoder *encoder;
14851
14852 /* This can happen either due to bugs in the get_hw_state
14853 * functions or because the pipe is force-enabled due to the
14854 * pipe A quirk. */
14855 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14856 crtc->base.base.id,
14857 crtc->base.state->enable ? "enabled" : "disabled",
14858 crtc->active ? "enabled" : "disabled");
14859
14860 crtc->base.state->enable = crtc->active;
14861 crtc->base.enabled = crtc->active;
14862
14863 /* Because we only establish the connector -> encoder ->
14864 * crtc links if something is active, this means the
14865 * crtc is now deactivated. Break the links. connector
14866 * -> encoder links are only establish when things are
14867 * actually up, hence no need to break them. */
14868 WARN_ON(crtc->active);
14869
14870 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
14871 WARN_ON(encoder->connectors_active);
14872 encoder->base.crtc = NULL;
14873 }
14874 }
14875
14876 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
14877 /*
14878 * We start out with underrun reporting disabled to avoid races.
14879 * For correct bookkeeping mark this on active crtcs.
14880 *
14881 * Also on gmch platforms we dont have any hardware bits to
14882 * disable the underrun reporting. Which means we need to start
14883 * out with underrun reporting disabled also on inactive pipes,
14884 * since otherwise we'll complain about the garbage we read when
14885 * e.g. coming up after runtime pm.
14886 *
14887 * No protection against concurrent access is required - at
14888 * worst a fifo underrun happens which also sets this to false.
14889 */
14890 crtc->cpu_fifo_underrun_disabled = true;
14891 crtc->pch_fifo_underrun_disabled = true;
14892 }
14893 }
14894
14895 static void intel_sanitize_encoder(struct intel_encoder *encoder)
14896 {
14897 struct intel_connector *connector;
14898 struct drm_device *dev = encoder->base.dev;
14899
14900 /* We need to check both for a crtc link (meaning that the
14901 * encoder is active and trying to read from a pipe) and the
14902 * pipe itself being active. */
14903 bool has_active_crtc = encoder->base.crtc &&
14904 to_intel_crtc(encoder->base.crtc)->active;
14905
14906 if (encoder->connectors_active && !has_active_crtc) {
14907 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14908 encoder->base.base.id,
14909 encoder->base.name);
14910
14911 /* Connector is active, but has no active pipe. This is
14912 * fallout from our resume register restoring. Disable
14913 * the encoder manually again. */
14914 if (encoder->base.crtc) {
14915 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14916 encoder->base.base.id,
14917 encoder->base.name);
14918 encoder->disable(encoder);
14919 if (encoder->post_disable)
14920 encoder->post_disable(encoder);
14921 }
14922 encoder->base.crtc = NULL;
14923 encoder->connectors_active = false;
14924
14925 /* Inconsistent output/port/pipe state happens presumably due to
14926 * a bug in one of the get_hw_state functions. Or someplace else
14927 * in our code, like the register restore mess on resume. Clamp
14928 * things to off as a safer default. */
14929 for_each_intel_connector(dev, connector) {
14930 if (connector->encoder != encoder)
14931 continue;
14932 connector->base.dpms = DRM_MODE_DPMS_OFF;
14933 connector->base.encoder = NULL;
14934 }
14935 }
14936 /* Enabled encoders without active connectors will be fixed in
14937 * the crtc fixup. */
14938 }
14939
14940 void i915_redisable_vga_power_on(struct drm_device *dev)
14941 {
14942 struct drm_i915_private *dev_priv = dev->dev_private;
14943 u32 vga_reg = i915_vgacntrl_reg(dev);
14944
14945 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
14946 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14947 i915_disable_vga(dev);
14948 }
14949 }
14950
14951 void i915_redisable_vga(struct drm_device *dev)
14952 {
14953 struct drm_i915_private *dev_priv = dev->dev_private;
14954
14955 /* This function can be called both from intel_modeset_setup_hw_state or
14956 * at a very early point in our resume sequence, where the power well
14957 * structures are not yet restored. Since this function is at a very
14958 * paranoid "someone might have enabled VGA while we were not looking"
14959 * level, just check if the power well is enabled instead of trying to
14960 * follow the "don't touch the power well if we don't need it" policy
14961 * the rest of the driver uses. */
14962 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
14963 return;
14964
14965 i915_redisable_vga_power_on(dev);
14966 }
14967
14968 static bool primary_get_hw_state(struct intel_crtc *crtc)
14969 {
14970 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
14971
14972 if (!crtc->active)
14973 return false;
14974
14975 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
14976 }
14977
14978 static void intel_modeset_readout_hw_state(struct drm_device *dev)
14979 {
14980 struct drm_i915_private *dev_priv = dev->dev_private;
14981 enum pipe pipe;
14982 struct intel_crtc *crtc;
14983 struct intel_encoder *encoder;
14984 struct intel_connector *connector;
14985 int i;
14986
14987 for_each_intel_crtc(dev, crtc) {
14988 struct drm_plane *primary = crtc->base.primary;
14989 struct intel_plane_state *plane_state;
14990
14991 memset(crtc->config, 0, sizeof(*crtc->config));
14992
14993 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
14994
14995 crtc->active = dev_priv->display.get_pipe_config(crtc,
14996 crtc->config);
14997
14998 crtc->base.state->enable = crtc->active;
14999 crtc->base.enabled = crtc->active;
15000
15001 plane_state = to_intel_plane_state(primary->state);
15002 plane_state->visible = primary_get_hw_state(crtc);
15003
15004 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15005 crtc->base.base.id,
15006 crtc->active ? "enabled" : "disabled");
15007 }
15008
15009 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15010 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15011
15012 pll->on = pll->get_hw_state(dev_priv, pll,
15013 &pll->config.hw_state);
15014 pll->active = 0;
15015 pll->config.crtc_mask = 0;
15016 for_each_intel_crtc(dev, crtc) {
15017 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15018 pll->active++;
15019 pll->config.crtc_mask |= 1 << crtc->pipe;
15020 }
15021 }
15022
15023 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15024 pll->name, pll->config.crtc_mask, pll->on);
15025
15026 if (pll->config.crtc_mask)
15027 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15028 }
15029
15030 for_each_intel_encoder(dev, encoder) {
15031 pipe = 0;
15032
15033 if (encoder->get_hw_state(encoder, &pipe)) {
15034 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15035 encoder->base.crtc = &crtc->base;
15036 encoder->get_config(encoder, crtc->config);
15037 } else {
15038 encoder->base.crtc = NULL;
15039 }
15040
15041 encoder->connectors_active = false;
15042 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15043 encoder->base.base.id,
15044 encoder->base.name,
15045 encoder->base.crtc ? "enabled" : "disabled",
15046 pipe_name(pipe));
15047 }
15048
15049 for_each_intel_connector(dev, connector) {
15050 if (connector->get_hw_state(connector)) {
15051 connector->base.dpms = DRM_MODE_DPMS_ON;
15052 connector->encoder->connectors_active = true;
15053 connector->base.encoder = &connector->encoder->base;
15054 } else {
15055 connector->base.dpms = DRM_MODE_DPMS_OFF;
15056 connector->base.encoder = NULL;
15057 }
15058 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15059 connector->base.base.id,
15060 connector->base.name,
15061 connector->base.encoder ? "enabled" : "disabled");
15062 }
15063 }
15064
15065 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
15066 * and i915 state tracking structures. */
15067 void intel_modeset_setup_hw_state(struct drm_device *dev,
15068 bool force_restore)
15069 {
15070 struct drm_i915_private *dev_priv = dev->dev_private;
15071 enum pipe pipe;
15072 struct intel_crtc *crtc;
15073 struct intel_encoder *encoder;
15074 int i;
15075
15076 intel_modeset_readout_hw_state(dev);
15077
15078 /*
15079 * Now that we have the config, copy it to each CRTC struct
15080 * Note that this could go away if we move to using crtc_config
15081 * checking everywhere.
15082 */
15083 for_each_intel_crtc(dev, crtc) {
15084 if (crtc->active && i915.fastboot) {
15085 intel_mode_from_pipe_config(&crtc->base.mode,
15086 crtc->config);
15087 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
15088 crtc->base.base.id);
15089 drm_mode_debug_printmodeline(&crtc->base.mode);
15090 }
15091 }
15092
15093 /* HW state is read out, now we need to sanitize this mess. */
15094 for_each_intel_encoder(dev, encoder) {
15095 intel_sanitize_encoder(encoder);
15096 }
15097
15098 for_each_pipe(dev_priv, pipe) {
15099 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15100 intel_sanitize_crtc(crtc);
15101 intel_dump_pipe_config(crtc, crtc->config,
15102 "[setup_hw_state]");
15103 }
15104
15105 intel_modeset_update_connector_atomic_state(dev);
15106
15107 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15108 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15109
15110 if (!pll->on || pll->active)
15111 continue;
15112
15113 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15114
15115 pll->disable(dev_priv, pll);
15116 pll->on = false;
15117 }
15118
15119 if (IS_GEN9(dev))
15120 skl_wm_get_hw_state(dev);
15121 else if (HAS_PCH_SPLIT(dev))
15122 ilk_wm_get_hw_state(dev);
15123
15124 if (force_restore) {
15125 i915_redisable_vga(dev);
15126
15127 /*
15128 * We need to use raw interfaces for restoring state to avoid
15129 * checking (bogus) intermediate states.
15130 */
15131 for_each_pipe(dev_priv, pipe) {
15132 struct drm_crtc *crtc =
15133 dev_priv->pipe_to_crtc_mapping[pipe];
15134
15135 intel_crtc_restore_mode(crtc);
15136 }
15137 } else {
15138 intel_modeset_update_staged_output_state(dev);
15139 }
15140
15141 intel_modeset_check_state(dev);
15142 }
15143
15144 void intel_modeset_gem_init(struct drm_device *dev)
15145 {
15146 struct drm_i915_private *dev_priv = dev->dev_private;
15147 struct drm_crtc *c;
15148 struct drm_i915_gem_object *obj;
15149 int ret;
15150
15151 mutex_lock(&dev->struct_mutex);
15152 intel_init_gt_powersave(dev);
15153 mutex_unlock(&dev->struct_mutex);
15154
15155 /*
15156 * There may be no VBT; and if the BIOS enabled SSC we can
15157 * just keep using it to avoid unnecessary flicker. Whereas if the
15158 * BIOS isn't using it, don't assume it will work even if the VBT
15159 * indicates as much.
15160 */
15161 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15162 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15163 DREF_SSC1_ENABLE);
15164
15165 intel_modeset_init_hw(dev);
15166
15167 intel_setup_overlay(dev);
15168
15169 /*
15170 * Make sure any fbs we allocated at startup are properly
15171 * pinned & fenced. When we do the allocation it's too early
15172 * for this.
15173 */
15174 for_each_crtc(dev, c) {
15175 obj = intel_fb_obj(c->primary->fb);
15176 if (obj == NULL)
15177 continue;
15178
15179 mutex_lock(&dev->struct_mutex);
15180 ret = intel_pin_and_fence_fb_obj(c->primary,
15181 c->primary->fb,
15182 c->primary->state,
15183 NULL);
15184 mutex_unlock(&dev->struct_mutex);
15185 if (ret) {
15186 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15187 to_intel_crtc(c)->pipe);
15188 drm_framebuffer_unreference(c->primary->fb);
15189 c->primary->fb = NULL;
15190 update_state_fb(c->primary);
15191 }
15192 }
15193
15194 intel_backlight_register(dev);
15195 }
15196
15197 void intel_connector_unregister(struct intel_connector *intel_connector)
15198 {
15199 struct drm_connector *connector = &intel_connector->base;
15200
15201 intel_panel_destroy_backlight(connector);
15202 drm_connector_unregister(connector);
15203 }
15204
15205 void intel_modeset_cleanup(struct drm_device *dev)
15206 {
15207 struct drm_i915_private *dev_priv = dev->dev_private;
15208 struct drm_connector *connector;
15209
15210 intel_disable_gt_powersave(dev);
15211
15212 intel_backlight_unregister(dev);
15213
15214 /*
15215 * Interrupts and polling as the first thing to avoid creating havoc.
15216 * Too much stuff here (turning of connectors, ...) would
15217 * experience fancy races otherwise.
15218 */
15219 intel_irq_uninstall(dev_priv);
15220
15221 /*
15222 * Due to the hpd irq storm handling the hotplug work can re-arm the
15223 * poll handlers. Hence disable polling after hpd handling is shut down.
15224 */
15225 drm_kms_helper_poll_fini(dev);
15226
15227 mutex_lock(&dev->struct_mutex);
15228
15229 intel_unregister_dsm_handler();
15230
15231 intel_fbc_disable(dev);
15232
15233 mutex_unlock(&dev->struct_mutex);
15234
15235 /* flush any delayed tasks or pending work */
15236 flush_scheduled_work();
15237
15238 /* destroy the backlight and sysfs files before encoders/connectors */
15239 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15240 struct intel_connector *intel_connector;
15241
15242 intel_connector = to_intel_connector(connector);
15243 intel_connector->unregister(intel_connector);
15244 }
15245
15246 drm_mode_config_cleanup(dev);
15247
15248 intel_cleanup_overlay(dev);
15249
15250 mutex_lock(&dev->struct_mutex);
15251 intel_cleanup_gt_powersave(dev);
15252 mutex_unlock(&dev->struct_mutex);
15253 }
15254
15255 /*
15256 * Return which encoder is currently attached for connector.
15257 */
15258 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15259 {
15260 return &intel_attached_encoder(connector)->base;
15261 }
15262
15263 void intel_connector_attach_encoder(struct intel_connector *connector,
15264 struct intel_encoder *encoder)
15265 {
15266 connector->encoder = encoder;
15267 drm_mode_connector_attach_encoder(&connector->base,
15268 &encoder->base);
15269 }
15270
15271 /*
15272 * set vga decode state - true == enable VGA decode
15273 */
15274 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15275 {
15276 struct drm_i915_private *dev_priv = dev->dev_private;
15277 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15278 u16 gmch_ctrl;
15279
15280 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15281 DRM_ERROR("failed to read control word\n");
15282 return -EIO;
15283 }
15284
15285 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15286 return 0;
15287
15288 if (state)
15289 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15290 else
15291 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15292
15293 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15294 DRM_ERROR("failed to write control word\n");
15295 return -EIO;
15296 }
15297
15298 return 0;
15299 }
15300
15301 struct intel_display_error_state {
15302
15303 u32 power_well_driver;
15304
15305 int num_transcoders;
15306
15307 struct intel_cursor_error_state {
15308 u32 control;
15309 u32 position;
15310 u32 base;
15311 u32 size;
15312 } cursor[I915_MAX_PIPES];
15313
15314 struct intel_pipe_error_state {
15315 bool power_domain_on;
15316 u32 source;
15317 u32 stat;
15318 } pipe[I915_MAX_PIPES];
15319
15320 struct intel_plane_error_state {
15321 u32 control;
15322 u32 stride;
15323 u32 size;
15324 u32 pos;
15325 u32 addr;
15326 u32 surface;
15327 u32 tile_offset;
15328 } plane[I915_MAX_PIPES];
15329
15330 struct intel_transcoder_error_state {
15331 bool power_domain_on;
15332 enum transcoder cpu_transcoder;
15333
15334 u32 conf;
15335
15336 u32 htotal;
15337 u32 hblank;
15338 u32 hsync;
15339 u32 vtotal;
15340 u32 vblank;
15341 u32 vsync;
15342 } transcoder[4];
15343 };
15344
15345 struct intel_display_error_state *
15346 intel_display_capture_error_state(struct drm_device *dev)
15347 {
15348 struct drm_i915_private *dev_priv = dev->dev_private;
15349 struct intel_display_error_state *error;
15350 int transcoders[] = {
15351 TRANSCODER_A,
15352 TRANSCODER_B,
15353 TRANSCODER_C,
15354 TRANSCODER_EDP,
15355 };
15356 int i;
15357
15358 if (INTEL_INFO(dev)->num_pipes == 0)
15359 return NULL;
15360
15361 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15362 if (error == NULL)
15363 return NULL;
15364
15365 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15366 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15367
15368 for_each_pipe(dev_priv, i) {
15369 error->pipe[i].power_domain_on =
15370 __intel_display_power_is_enabled(dev_priv,
15371 POWER_DOMAIN_PIPE(i));
15372 if (!error->pipe[i].power_domain_on)
15373 continue;
15374
15375 error->cursor[i].control = I915_READ(CURCNTR(i));
15376 error->cursor[i].position = I915_READ(CURPOS(i));
15377 error->cursor[i].base = I915_READ(CURBASE(i));
15378
15379 error->plane[i].control = I915_READ(DSPCNTR(i));
15380 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15381 if (INTEL_INFO(dev)->gen <= 3) {
15382 error->plane[i].size = I915_READ(DSPSIZE(i));
15383 error->plane[i].pos = I915_READ(DSPPOS(i));
15384 }
15385 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15386 error->plane[i].addr = I915_READ(DSPADDR(i));
15387 if (INTEL_INFO(dev)->gen >= 4) {
15388 error->plane[i].surface = I915_READ(DSPSURF(i));
15389 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15390 }
15391
15392 error->pipe[i].source = I915_READ(PIPESRC(i));
15393
15394 if (HAS_GMCH_DISPLAY(dev))
15395 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15396 }
15397
15398 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15399 if (HAS_DDI(dev_priv->dev))
15400 error->num_transcoders++; /* Account for eDP. */
15401
15402 for (i = 0; i < error->num_transcoders; i++) {
15403 enum transcoder cpu_transcoder = transcoders[i];
15404
15405 error->transcoder[i].power_domain_on =
15406 __intel_display_power_is_enabled(dev_priv,
15407 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15408 if (!error->transcoder[i].power_domain_on)
15409 continue;
15410
15411 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15412
15413 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15414 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15415 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15416 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15417 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15418 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15419 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15420 }
15421
15422 return error;
15423 }
15424
15425 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15426
15427 void
15428 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15429 struct drm_device *dev,
15430 struct intel_display_error_state *error)
15431 {
15432 struct drm_i915_private *dev_priv = dev->dev_private;
15433 int i;
15434
15435 if (!error)
15436 return;
15437
15438 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15439 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15440 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15441 error->power_well_driver);
15442 for_each_pipe(dev_priv, i) {
15443 err_printf(m, "Pipe [%d]:\n", i);
15444 err_printf(m, " Power: %s\n",
15445 error->pipe[i].power_domain_on ? "on" : "off");
15446 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15447 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15448
15449 err_printf(m, "Plane [%d]:\n", i);
15450 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15451 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15452 if (INTEL_INFO(dev)->gen <= 3) {
15453 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15454 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15455 }
15456 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15457 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15458 if (INTEL_INFO(dev)->gen >= 4) {
15459 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15460 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15461 }
15462
15463 err_printf(m, "Cursor [%d]:\n", i);
15464 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15465 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15466 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15467 }
15468
15469 for (i = 0; i < error->num_transcoders; i++) {
15470 err_printf(m, "CPU transcoder: %c\n",
15471 transcoder_name(error->transcoder[i].cpu_transcoder));
15472 err_printf(m, " Power: %s\n",
15473 error->transcoder[i].power_domain_on ? "on" : "off");
15474 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15475 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15476 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15477 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15478 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15479 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15480 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15481 }
15482 }
15483
15484 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15485 {
15486 struct intel_crtc *crtc;
15487
15488 for_each_intel_crtc(dev, crtc) {
15489 struct intel_unpin_work *work;
15490
15491 spin_lock_irq(&dev->event_lock);
15492
15493 work = crtc->unpin_work;
15494
15495 if (work && work->event &&
15496 work->event->base.file_priv == file) {
15497 kfree(work->event);
15498 work->event = NULL;
15499 }
15500
15501 spin_unlock_irq(&dev->event_lock);
15502 }
15503 }
Linux kernel - Deliverables
This page took 0.376481 seconds and 6 git commands to generate.