2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_rect.h>
44 #include <linux/dma_remapping.h>
46 /* Primary plane formats supported by all gen */
47 #define COMMON_PRIMARY_FORMATS \
50 DRM_FORMAT_XRGB8888, \
53 /* Primary plane formats for gen <= 3 */
54 static const uint32_t intel_primary_formats_gen2
[] = {
55 COMMON_PRIMARY_FORMATS
,
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t intel_primary_formats_gen4
[] = {
62 COMMON_PRIMARY_FORMATS
, \
65 DRM_FORMAT_XRGB2101010
,
66 DRM_FORMAT_ARGB2101010
,
67 DRM_FORMAT_XBGR2101010
,
68 DRM_FORMAT_ABGR2101010
,
72 static const uint32_t intel_cursor_formats
[] = {
76 #define DIV_ROUND_CLOSEST_ULL(ll, d) \
77 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
79 static void intel_increase_pllclock(struct drm_device
*dev
,
81 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
83 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
84 struct intel_crtc_config
*pipe_config
);
85 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
86 struct intel_crtc_config
*pipe_config
);
88 static int intel_set_mode(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
,
89 int x
, int y
, struct drm_framebuffer
*old_fb
);
90 static int intel_framebuffer_init(struct drm_device
*dev
,
91 struct intel_framebuffer
*ifb
,
92 struct drm_mode_fb_cmd2
*mode_cmd
,
93 struct drm_i915_gem_object
*obj
);
94 static void intel_dp_set_m_n(struct intel_crtc
*crtc
);
95 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
);
96 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
);
97 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
98 struct intel_link_m_n
*m_n
);
99 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
);
100 static void haswell_set_pipeconf(struct drm_crtc
*crtc
);
101 static void intel_set_pipe_csc(struct drm_crtc
*crtc
);
102 static void vlv_prepare_pll(struct intel_crtc
*crtc
);
104 static struct intel_encoder
*intel_find_encoder(struct intel_connector
*connector
, int pipe
)
106 if (!connector
->mst_port
)
107 return connector
->encoder
;
109 return &connector
->mst_port
->mst_encoders
[pipe
]->base
;
118 int p2_slow
, p2_fast
;
121 typedef struct intel_limit intel_limit_t
;
123 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
128 intel_pch_rawclk(struct drm_device
*dev
)
130 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
132 WARN_ON(!HAS_PCH_SPLIT(dev
));
134 return I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
;
137 static inline u32
/* units of 100MHz */
138 intel_fdi_link_freq(struct drm_device
*dev
)
141 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
142 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
147 static const intel_limit_t intel_limits_i8xx_dac
= {
148 .dot
= { .min
= 25000, .max
= 350000 },
149 .vco
= { .min
= 908000, .max
= 1512000 },
150 .n
= { .min
= 2, .max
= 16 },
151 .m
= { .min
= 96, .max
= 140 },
152 .m1
= { .min
= 18, .max
= 26 },
153 .m2
= { .min
= 6, .max
= 16 },
154 .p
= { .min
= 4, .max
= 128 },
155 .p1
= { .min
= 2, .max
= 33 },
156 .p2
= { .dot_limit
= 165000,
157 .p2_slow
= 4, .p2_fast
= 2 },
160 static const intel_limit_t intel_limits_i8xx_dvo
= {
161 .dot
= { .min
= 25000, .max
= 350000 },
162 .vco
= { .min
= 908000, .max
= 1512000 },
163 .n
= { .min
= 2, .max
= 16 },
164 .m
= { .min
= 96, .max
= 140 },
165 .m1
= { .min
= 18, .max
= 26 },
166 .m2
= { .min
= 6, .max
= 16 },
167 .p
= { .min
= 4, .max
= 128 },
168 .p1
= { .min
= 2, .max
= 33 },
169 .p2
= { .dot_limit
= 165000,
170 .p2_slow
= 4, .p2_fast
= 4 },
173 static const intel_limit_t intel_limits_i8xx_lvds
= {
174 .dot
= { .min
= 25000, .max
= 350000 },
175 .vco
= { .min
= 908000, .max
= 1512000 },
176 .n
= { .min
= 2, .max
= 16 },
177 .m
= { .min
= 96, .max
= 140 },
178 .m1
= { .min
= 18, .max
= 26 },
179 .m2
= { .min
= 6, .max
= 16 },
180 .p
= { .min
= 4, .max
= 128 },
181 .p1
= { .min
= 1, .max
= 6 },
182 .p2
= { .dot_limit
= 165000,
183 .p2_slow
= 14, .p2_fast
= 7 },
186 static const intel_limit_t intel_limits_i9xx_sdvo
= {
187 .dot
= { .min
= 20000, .max
= 400000 },
188 .vco
= { .min
= 1400000, .max
= 2800000 },
189 .n
= { .min
= 1, .max
= 6 },
190 .m
= { .min
= 70, .max
= 120 },
191 .m1
= { .min
= 8, .max
= 18 },
192 .m2
= { .min
= 3, .max
= 7 },
193 .p
= { .min
= 5, .max
= 80 },
194 .p1
= { .min
= 1, .max
= 8 },
195 .p2
= { .dot_limit
= 200000,
196 .p2_slow
= 10, .p2_fast
= 5 },
199 static const intel_limit_t intel_limits_i9xx_lvds
= {
200 .dot
= { .min
= 20000, .max
= 400000 },
201 .vco
= { .min
= 1400000, .max
= 2800000 },
202 .n
= { .min
= 1, .max
= 6 },
203 .m
= { .min
= 70, .max
= 120 },
204 .m1
= { .min
= 8, .max
= 18 },
205 .m2
= { .min
= 3, .max
= 7 },
206 .p
= { .min
= 7, .max
= 98 },
207 .p1
= { .min
= 1, .max
= 8 },
208 .p2
= { .dot_limit
= 112000,
209 .p2_slow
= 14, .p2_fast
= 7 },
213 static const intel_limit_t intel_limits_g4x_sdvo
= {
214 .dot
= { .min
= 25000, .max
= 270000 },
215 .vco
= { .min
= 1750000, .max
= 3500000},
216 .n
= { .min
= 1, .max
= 4 },
217 .m
= { .min
= 104, .max
= 138 },
218 .m1
= { .min
= 17, .max
= 23 },
219 .m2
= { .min
= 5, .max
= 11 },
220 .p
= { .min
= 10, .max
= 30 },
221 .p1
= { .min
= 1, .max
= 3},
222 .p2
= { .dot_limit
= 270000,
228 static const intel_limit_t intel_limits_g4x_hdmi
= {
229 .dot
= { .min
= 22000, .max
= 400000 },
230 .vco
= { .min
= 1750000, .max
= 3500000},
231 .n
= { .min
= 1, .max
= 4 },
232 .m
= { .min
= 104, .max
= 138 },
233 .m1
= { .min
= 16, .max
= 23 },
234 .m2
= { .min
= 5, .max
= 11 },
235 .p
= { .min
= 5, .max
= 80 },
236 .p1
= { .min
= 1, .max
= 8},
237 .p2
= { .dot_limit
= 165000,
238 .p2_slow
= 10, .p2_fast
= 5 },
241 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
242 .dot
= { .min
= 20000, .max
= 115000 },
243 .vco
= { .min
= 1750000, .max
= 3500000 },
244 .n
= { .min
= 1, .max
= 3 },
245 .m
= { .min
= 104, .max
= 138 },
246 .m1
= { .min
= 17, .max
= 23 },
247 .m2
= { .min
= 5, .max
= 11 },
248 .p
= { .min
= 28, .max
= 112 },
249 .p1
= { .min
= 2, .max
= 8 },
250 .p2
= { .dot_limit
= 0,
251 .p2_slow
= 14, .p2_fast
= 14
255 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
256 .dot
= { .min
= 80000, .max
= 224000 },
257 .vco
= { .min
= 1750000, .max
= 3500000 },
258 .n
= { .min
= 1, .max
= 3 },
259 .m
= { .min
= 104, .max
= 138 },
260 .m1
= { .min
= 17, .max
= 23 },
261 .m2
= { .min
= 5, .max
= 11 },
262 .p
= { .min
= 14, .max
= 42 },
263 .p1
= { .min
= 2, .max
= 6 },
264 .p2
= { .dot_limit
= 0,
265 .p2_slow
= 7, .p2_fast
= 7
269 static const intel_limit_t intel_limits_pineview_sdvo
= {
270 .dot
= { .min
= 20000, .max
= 400000},
271 .vco
= { .min
= 1700000, .max
= 3500000 },
272 /* Pineview's Ncounter is a ring counter */
273 .n
= { .min
= 3, .max
= 6 },
274 .m
= { .min
= 2, .max
= 256 },
275 /* Pineview only has one combined m divider, which we treat as m2. */
276 .m1
= { .min
= 0, .max
= 0 },
277 .m2
= { .min
= 0, .max
= 254 },
278 .p
= { .min
= 5, .max
= 80 },
279 .p1
= { .min
= 1, .max
= 8 },
280 .p2
= { .dot_limit
= 200000,
281 .p2_slow
= 10, .p2_fast
= 5 },
284 static const intel_limit_t intel_limits_pineview_lvds
= {
285 .dot
= { .min
= 20000, .max
= 400000 },
286 .vco
= { .min
= 1700000, .max
= 3500000 },
287 .n
= { .min
= 3, .max
= 6 },
288 .m
= { .min
= 2, .max
= 256 },
289 .m1
= { .min
= 0, .max
= 0 },
290 .m2
= { .min
= 0, .max
= 254 },
291 .p
= { .min
= 7, .max
= 112 },
292 .p1
= { .min
= 1, .max
= 8 },
293 .p2
= { .dot_limit
= 112000,
294 .p2_slow
= 14, .p2_fast
= 14 },
297 /* Ironlake / Sandybridge
299 * We calculate clock using (register_value + 2) for N/M1/M2, so here
300 * the range value for them is (actual_value - 2).
302 static const intel_limit_t intel_limits_ironlake_dac
= {
303 .dot
= { .min
= 25000, .max
= 350000 },
304 .vco
= { .min
= 1760000, .max
= 3510000 },
305 .n
= { .min
= 1, .max
= 5 },
306 .m
= { .min
= 79, .max
= 127 },
307 .m1
= { .min
= 12, .max
= 22 },
308 .m2
= { .min
= 5, .max
= 9 },
309 .p
= { .min
= 5, .max
= 80 },
310 .p1
= { .min
= 1, .max
= 8 },
311 .p2
= { .dot_limit
= 225000,
312 .p2_slow
= 10, .p2_fast
= 5 },
315 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
316 .dot
= { .min
= 25000, .max
= 350000 },
317 .vco
= { .min
= 1760000, .max
= 3510000 },
318 .n
= { .min
= 1, .max
= 3 },
319 .m
= { .min
= 79, .max
= 118 },
320 .m1
= { .min
= 12, .max
= 22 },
321 .m2
= { .min
= 5, .max
= 9 },
322 .p
= { .min
= 28, .max
= 112 },
323 .p1
= { .min
= 2, .max
= 8 },
324 .p2
= { .dot_limit
= 225000,
325 .p2_slow
= 14, .p2_fast
= 14 },
328 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
329 .dot
= { .min
= 25000, .max
= 350000 },
330 .vco
= { .min
= 1760000, .max
= 3510000 },
331 .n
= { .min
= 1, .max
= 3 },
332 .m
= { .min
= 79, .max
= 127 },
333 .m1
= { .min
= 12, .max
= 22 },
334 .m2
= { .min
= 5, .max
= 9 },
335 .p
= { .min
= 14, .max
= 56 },
336 .p1
= { .min
= 2, .max
= 8 },
337 .p2
= { .dot_limit
= 225000,
338 .p2_slow
= 7, .p2_fast
= 7 },
341 /* LVDS 100mhz refclk limits. */
342 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
343 .dot
= { .min
= 25000, .max
= 350000 },
344 .vco
= { .min
= 1760000, .max
= 3510000 },
345 .n
= { .min
= 1, .max
= 2 },
346 .m
= { .min
= 79, .max
= 126 },
347 .m1
= { .min
= 12, .max
= 22 },
348 .m2
= { .min
= 5, .max
= 9 },
349 .p
= { .min
= 28, .max
= 112 },
350 .p1
= { .min
= 2, .max
= 8 },
351 .p2
= { .dot_limit
= 225000,
352 .p2_slow
= 14, .p2_fast
= 14 },
355 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
356 .dot
= { .min
= 25000, .max
= 350000 },
357 .vco
= { .min
= 1760000, .max
= 3510000 },
358 .n
= { .min
= 1, .max
= 3 },
359 .m
= { .min
= 79, .max
= 126 },
360 .m1
= { .min
= 12, .max
= 22 },
361 .m2
= { .min
= 5, .max
= 9 },
362 .p
= { .min
= 14, .max
= 42 },
363 .p1
= { .min
= 2, .max
= 6 },
364 .p2
= { .dot_limit
= 225000,
365 .p2_slow
= 7, .p2_fast
= 7 },
368 static const intel_limit_t intel_limits_vlv
= {
370 * These are the data rate limits (measured in fast clocks)
371 * since those are the strictest limits we have. The fast
372 * clock and actual rate limits are more relaxed, so checking
373 * them would make no difference.
375 .dot
= { .min
= 25000 * 5, .max
= 270000 * 5 },
376 .vco
= { .min
= 4000000, .max
= 6000000 },
377 .n
= { .min
= 1, .max
= 7 },
378 .m1
= { .min
= 2, .max
= 3 },
379 .m2
= { .min
= 11, .max
= 156 },
380 .p1
= { .min
= 2, .max
= 3 },
381 .p2
= { .p2_slow
= 2, .p2_fast
= 20 }, /* slow=min, fast=max */
384 static const intel_limit_t intel_limits_chv
= {
386 * These are the data rate limits (measured in fast clocks)
387 * since those are the strictest limits we have. The fast
388 * clock and actual rate limits are more relaxed, so checking
389 * them would make no difference.
391 .dot
= { .min
= 25000 * 5, .max
= 540000 * 5},
392 .vco
= { .min
= 4860000, .max
= 6700000 },
393 .n
= { .min
= 1, .max
= 1 },
394 .m1
= { .min
= 2, .max
= 2 },
395 .m2
= { .min
= 24 << 22, .max
= 175 << 22 },
396 .p1
= { .min
= 2, .max
= 4 },
397 .p2
= { .p2_slow
= 1, .p2_fast
= 14 },
400 static void vlv_clock(int refclk
, intel_clock_t
*clock
)
402 clock
->m
= clock
->m1
* clock
->m2
;
403 clock
->p
= clock
->p1
* clock
->p2
;
404 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
406 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
407 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
411 * Returns whether any output on the specified pipe is of the specified type
413 static bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
)
415 struct drm_device
*dev
= crtc
->dev
;
416 struct intel_encoder
*encoder
;
418 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
419 if (encoder
->type
== type
)
425 static const intel_limit_t
*intel_ironlake_limit(struct drm_crtc
*crtc
,
428 struct drm_device
*dev
= crtc
->dev
;
429 const intel_limit_t
*limit
;
431 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
432 if (intel_is_dual_link_lvds(dev
)) {
433 if (refclk
== 100000)
434 limit
= &intel_limits_ironlake_dual_lvds_100m
;
436 limit
= &intel_limits_ironlake_dual_lvds
;
438 if (refclk
== 100000)
439 limit
= &intel_limits_ironlake_single_lvds_100m
;
441 limit
= &intel_limits_ironlake_single_lvds
;
444 limit
= &intel_limits_ironlake_dac
;
449 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
451 struct drm_device
*dev
= crtc
->dev
;
452 const intel_limit_t
*limit
;
454 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
455 if (intel_is_dual_link_lvds(dev
))
456 limit
= &intel_limits_g4x_dual_channel_lvds
;
458 limit
= &intel_limits_g4x_single_channel_lvds
;
459 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
460 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
461 limit
= &intel_limits_g4x_hdmi
;
462 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
463 limit
= &intel_limits_g4x_sdvo
;
464 } else /* The option is for other outputs */
465 limit
= &intel_limits_i9xx_sdvo
;
470 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
, int refclk
)
472 struct drm_device
*dev
= crtc
->dev
;
473 const intel_limit_t
*limit
;
475 if (HAS_PCH_SPLIT(dev
))
476 limit
= intel_ironlake_limit(crtc
, refclk
);
477 else if (IS_G4X(dev
)) {
478 limit
= intel_g4x_limit(crtc
);
479 } else if (IS_PINEVIEW(dev
)) {
480 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
481 limit
= &intel_limits_pineview_lvds
;
483 limit
= &intel_limits_pineview_sdvo
;
484 } else if (IS_CHERRYVIEW(dev
)) {
485 limit
= &intel_limits_chv
;
486 } else if (IS_VALLEYVIEW(dev
)) {
487 limit
= &intel_limits_vlv
;
488 } else if (!IS_GEN2(dev
)) {
489 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
490 limit
= &intel_limits_i9xx_lvds
;
492 limit
= &intel_limits_i9xx_sdvo
;
494 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
495 limit
= &intel_limits_i8xx_lvds
;
496 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
))
497 limit
= &intel_limits_i8xx_dvo
;
499 limit
= &intel_limits_i8xx_dac
;
504 /* m1 is reserved as 0 in Pineview, n is a ring counter */
505 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
507 clock
->m
= clock
->m2
+ 2;
508 clock
->p
= clock
->p1
* clock
->p2
;
509 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
511 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
512 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
515 static uint32_t i9xx_dpll_compute_m(struct dpll
*dpll
)
517 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
520 static void i9xx_clock(int refclk
, intel_clock_t
*clock
)
522 clock
->m
= i9xx_dpll_compute_m(clock
);
523 clock
->p
= clock
->p1
* clock
->p2
;
524 if (WARN_ON(clock
->n
+ 2 == 0 || clock
->p
== 0))
526 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
+ 2);
527 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
530 static void chv_clock(int refclk
, intel_clock_t
*clock
)
532 clock
->m
= clock
->m1
* clock
->m2
;
533 clock
->p
= clock
->p1
* clock
->p2
;
534 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
536 clock
->vco
= DIV_ROUND_CLOSEST_ULL((uint64_t)refclk
* clock
->m
,
538 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
541 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
543 * Returns whether the given set of divisors are valid for a given refclk with
544 * the given connectors.
547 static bool intel_PLL_is_valid(struct drm_device
*dev
,
548 const intel_limit_t
*limit
,
549 const intel_clock_t
*clock
)
551 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
552 INTELPllInvalid("n out of range\n");
553 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
554 INTELPllInvalid("p1 out of range\n");
555 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
556 INTELPllInvalid("m2 out of range\n");
557 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
558 INTELPllInvalid("m1 out of range\n");
560 if (!IS_PINEVIEW(dev
) && !IS_VALLEYVIEW(dev
))
561 if (clock
->m1
<= clock
->m2
)
562 INTELPllInvalid("m1 <= m2\n");
564 if (!IS_VALLEYVIEW(dev
)) {
565 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
566 INTELPllInvalid("p out of range\n");
567 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
568 INTELPllInvalid("m out of range\n");
571 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
572 INTELPllInvalid("vco out of range\n");
573 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
574 * connector, etc., rather than just a single range.
576 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
577 INTELPllInvalid("dot out of range\n");
583 i9xx_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
584 int target
, int refclk
, intel_clock_t
*match_clock
,
585 intel_clock_t
*best_clock
)
587 struct drm_device
*dev
= crtc
->dev
;
591 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
593 * For LVDS just rely on its current settings for dual-channel.
594 * We haven't figured out how to reliably set up different
595 * single/dual channel state, if we even can.
597 if (intel_is_dual_link_lvds(dev
))
598 clock
.p2
= limit
->p2
.p2_fast
;
600 clock
.p2
= limit
->p2
.p2_slow
;
602 if (target
< limit
->p2
.dot_limit
)
603 clock
.p2
= limit
->p2
.p2_slow
;
605 clock
.p2
= limit
->p2
.p2_fast
;
608 memset(best_clock
, 0, sizeof(*best_clock
));
610 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
612 for (clock
.m2
= limit
->m2
.min
;
613 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
614 if (clock
.m2
>= clock
.m1
)
616 for (clock
.n
= limit
->n
.min
;
617 clock
.n
<= limit
->n
.max
; clock
.n
++) {
618 for (clock
.p1
= limit
->p1
.min
;
619 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
622 i9xx_clock(refclk
, &clock
);
623 if (!intel_PLL_is_valid(dev
, limit
,
627 clock
.p
!= match_clock
->p
)
630 this_err
= abs(clock
.dot
- target
);
631 if (this_err
< err
) {
640 return (err
!= target
);
644 pnv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
645 int target
, int refclk
, intel_clock_t
*match_clock
,
646 intel_clock_t
*best_clock
)
648 struct drm_device
*dev
= crtc
->dev
;
652 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
654 * For LVDS just rely on its current settings for dual-channel.
655 * We haven't figured out how to reliably set up different
656 * single/dual channel state, if we even can.
658 if (intel_is_dual_link_lvds(dev
))
659 clock
.p2
= limit
->p2
.p2_fast
;
661 clock
.p2
= limit
->p2
.p2_slow
;
663 if (target
< limit
->p2
.dot_limit
)
664 clock
.p2
= limit
->p2
.p2_slow
;
666 clock
.p2
= limit
->p2
.p2_fast
;
669 memset(best_clock
, 0, sizeof(*best_clock
));
671 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
673 for (clock
.m2
= limit
->m2
.min
;
674 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
675 for (clock
.n
= limit
->n
.min
;
676 clock
.n
<= limit
->n
.max
; clock
.n
++) {
677 for (clock
.p1
= limit
->p1
.min
;
678 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
681 pineview_clock(refclk
, &clock
);
682 if (!intel_PLL_is_valid(dev
, limit
,
686 clock
.p
!= match_clock
->p
)
689 this_err
= abs(clock
.dot
- target
);
690 if (this_err
< err
) {
699 return (err
!= target
);
703 g4x_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
704 int target
, int refclk
, intel_clock_t
*match_clock
,
705 intel_clock_t
*best_clock
)
707 struct drm_device
*dev
= crtc
->dev
;
711 /* approximately equals target * 0.00585 */
712 int err_most
= (target
>> 8) + (target
>> 9);
715 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
716 if (intel_is_dual_link_lvds(dev
))
717 clock
.p2
= limit
->p2
.p2_fast
;
719 clock
.p2
= limit
->p2
.p2_slow
;
721 if (target
< limit
->p2
.dot_limit
)
722 clock
.p2
= limit
->p2
.p2_slow
;
724 clock
.p2
= limit
->p2
.p2_fast
;
727 memset(best_clock
, 0, sizeof(*best_clock
));
728 max_n
= limit
->n
.max
;
729 /* based on hardware requirement, prefer smaller n to precision */
730 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
731 /* based on hardware requirement, prefere larger m1,m2 */
732 for (clock
.m1
= limit
->m1
.max
;
733 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
734 for (clock
.m2
= limit
->m2
.max
;
735 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
736 for (clock
.p1
= limit
->p1
.max
;
737 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
740 i9xx_clock(refclk
, &clock
);
741 if (!intel_PLL_is_valid(dev
, limit
,
745 this_err
= abs(clock
.dot
- target
);
746 if (this_err
< err_most
) {
760 vlv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
761 int target
, int refclk
, intel_clock_t
*match_clock
,
762 intel_clock_t
*best_clock
)
764 struct drm_device
*dev
= crtc
->dev
;
766 unsigned int bestppm
= 1000000;
767 /* min update 19.2 MHz */
768 int max_n
= min(limit
->n
.max
, refclk
/ 19200);
771 target
*= 5; /* fast clock */
773 memset(best_clock
, 0, sizeof(*best_clock
));
775 /* based on hardware requirement, prefer smaller n to precision */
776 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
777 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
778 for (clock
.p2
= limit
->p2
.p2_fast
; clock
.p2
>= limit
->p2
.p2_slow
;
779 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
780 clock
.p
= clock
.p1
* clock
.p2
;
781 /* based on hardware requirement, prefer bigger m1,m2 values */
782 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
; clock
.m1
++) {
783 unsigned int ppm
, diff
;
785 clock
.m2
= DIV_ROUND_CLOSEST(target
* clock
.p
* clock
.n
,
788 vlv_clock(refclk
, &clock
);
790 if (!intel_PLL_is_valid(dev
, limit
,
794 diff
= abs(clock
.dot
- target
);
795 ppm
= div_u64(1000000ULL * diff
, target
);
797 if (ppm
< 100 && clock
.p
> best_clock
->p
) {
803 if (bestppm
>= 10 && ppm
< bestppm
- 10) {
817 chv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
818 int target
, int refclk
, intel_clock_t
*match_clock
,
819 intel_clock_t
*best_clock
)
821 struct drm_device
*dev
= crtc
->dev
;
826 memset(best_clock
, 0, sizeof(*best_clock
));
829 * Based on hardware doc, the n always set to 1, and m1 always
830 * set to 2. If requires to support 200Mhz refclk, we need to
831 * revisit this because n may not 1 anymore.
833 clock
.n
= 1, clock
.m1
= 2;
834 target
*= 5; /* fast clock */
836 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
837 for (clock
.p2
= limit
->p2
.p2_fast
;
838 clock
.p2
>= limit
->p2
.p2_slow
;
839 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
841 clock
.p
= clock
.p1
* clock
.p2
;
843 m2
= DIV_ROUND_CLOSEST_ULL(((uint64_t)target
* clock
.p
*
844 clock
.n
) << 22, refclk
* clock
.m1
);
846 if (m2
> INT_MAX
/clock
.m1
)
851 chv_clock(refclk
, &clock
);
853 if (!intel_PLL_is_valid(dev
, limit
, &clock
))
856 /* based on hardware requirement, prefer bigger p
858 if (clock
.p
> best_clock
->p
) {
868 bool intel_crtc_active(struct drm_crtc
*crtc
)
870 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
872 /* Be paranoid as we can arrive here with only partial
873 * state retrieved from the hardware during setup.
875 * We can ditch the adjusted_mode.crtc_clock check as soon
876 * as Haswell has gained clock readout/fastboot support.
878 * We can ditch the crtc->primary->fb check as soon as we can
879 * properly reconstruct framebuffers.
881 return intel_crtc
->active
&& crtc
->primary
->fb
&&
882 intel_crtc
->config
.adjusted_mode
.crtc_clock
;
885 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
888 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
889 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
891 return intel_crtc
->config
.cpu_transcoder
;
894 static void g4x_wait_for_vblank(struct drm_device
*dev
, int pipe
)
896 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
897 u32 frame
, frame_reg
= PIPE_FRMCOUNT_GM45(pipe
);
899 frame
= I915_READ(frame_reg
);
901 if (wait_for(I915_READ_NOTRACE(frame_reg
) != frame
, 50))
902 WARN(1, "vblank wait timed out\n");
906 * intel_wait_for_vblank - wait for vblank on a given pipe
908 * @pipe: pipe to wait for
910 * Wait for vblank to occur on a given pipe. Needed for various bits of
913 void intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
915 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
916 int pipestat_reg
= PIPESTAT(pipe
);
918 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
919 g4x_wait_for_vblank(dev
, pipe
);
923 /* Clear existing vblank status. Note this will clear any other
924 * sticky status fields as well.
926 * This races with i915_driver_irq_handler() with the result
927 * that either function could miss a vblank event. Here it is not
928 * fatal, as we will either wait upon the next vblank interrupt or
929 * timeout. Generally speaking intel_wait_for_vblank() is only
930 * called during modeset at which time the GPU should be idle and
931 * should *not* be performing page flips and thus not waiting on
933 * Currently, the result of us stealing a vblank from the irq
934 * handler is that a single frame will be skipped during swapbuffers.
936 I915_WRITE(pipestat_reg
,
937 I915_READ(pipestat_reg
) | PIPE_VBLANK_INTERRUPT_STATUS
);
939 /* Wait for vblank interrupt bit to set */
940 if (wait_for(I915_READ(pipestat_reg
) &
941 PIPE_VBLANK_INTERRUPT_STATUS
,
943 DRM_DEBUG_KMS("vblank wait timed out\n");
946 static bool pipe_dsl_stopped(struct drm_device
*dev
, enum pipe pipe
)
948 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
949 u32 reg
= PIPEDSL(pipe
);
954 line_mask
= DSL_LINEMASK_GEN2
;
956 line_mask
= DSL_LINEMASK_GEN3
;
958 line1
= I915_READ(reg
) & line_mask
;
960 line2
= I915_READ(reg
) & line_mask
;
962 return line1
== line2
;
966 * intel_wait_for_pipe_off - wait for pipe to turn off
968 * @pipe: pipe to wait for
970 * After disabling a pipe, we can't wait for vblank in the usual way,
971 * spinning on the vblank interrupt status bit, since we won't actually
972 * see an interrupt when the pipe is disabled.
975 * wait for the pipe register state bit to turn off
978 * wait for the display line value to settle (it usually
979 * ends up stopping at the start of the next frame).
982 void intel_wait_for_pipe_off(struct drm_device
*dev
, int pipe
)
984 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
985 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
988 if (INTEL_INFO(dev
)->gen
>= 4) {
989 int reg
= PIPECONF(cpu_transcoder
);
991 /* Wait for the Pipe State to go off */
992 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
994 WARN(1, "pipe_off wait timed out\n");
996 /* Wait for the display line to settle */
997 if (wait_for(pipe_dsl_stopped(dev
, pipe
), 100))
998 WARN(1, "pipe_off wait timed out\n");
1003 * ibx_digital_port_connected - is the specified port connected?
1004 * @dev_priv: i915 private structure
1005 * @port: the port to test
1007 * Returns true if @port is connected, false otherwise.
1009 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
1010 struct intel_digital_port
*port
)
1014 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1015 switch (port
->port
) {
1017 bit
= SDE_PORTB_HOTPLUG
;
1020 bit
= SDE_PORTC_HOTPLUG
;
1023 bit
= SDE_PORTD_HOTPLUG
;
1029 switch (port
->port
) {
1031 bit
= SDE_PORTB_HOTPLUG_CPT
;
1034 bit
= SDE_PORTC_HOTPLUG_CPT
;
1037 bit
= SDE_PORTD_HOTPLUG_CPT
;
1044 return I915_READ(SDEISR
) & bit
;
1047 static const char *state_string(bool enabled
)
1049 return enabled
? "on" : "off";
1052 /* Only for pre-ILK configs */
1053 void assert_pll(struct drm_i915_private
*dev_priv
,
1054 enum pipe pipe
, bool state
)
1061 val
= I915_READ(reg
);
1062 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1063 WARN(cur_state
!= state
,
1064 "PLL state assertion failure (expected %s, current %s)\n",
1065 state_string(state
), state_string(cur_state
));
1068 /* XXX: the dsi pll is shared between MIPI DSI ports */
1069 static void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
)
1074 mutex_lock(&dev_priv
->dpio_lock
);
1075 val
= vlv_cck_read(dev_priv
, CCK_REG_DSI_PLL_CONTROL
);
1076 mutex_unlock(&dev_priv
->dpio_lock
);
1078 cur_state
= val
& DSI_PLL_VCO_EN
;
1079 WARN(cur_state
!= state
,
1080 "DSI PLL state assertion failure (expected %s, current %s)\n",
1081 state_string(state
), state_string(cur_state
));
1083 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1084 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1086 struct intel_shared_dpll
*
1087 intel_crtc_to_shared_dpll(struct intel_crtc
*crtc
)
1089 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1091 if (crtc
->config
.shared_dpll
< 0)
1094 return &dev_priv
->shared_dplls
[crtc
->config
.shared_dpll
];
1098 void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
1099 struct intel_shared_dpll
*pll
,
1103 struct intel_dpll_hw_state hw_state
;
1106 "asserting DPLL %s with no DPLL\n", state_string(state
)))
1109 cur_state
= pll
->get_hw_state(dev_priv
, pll
, &hw_state
);
1110 WARN(cur_state
!= state
,
1111 "%s assertion failure (expected %s, current %s)\n",
1112 pll
->name
, state_string(state
), state_string(cur_state
));
1115 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1116 enum pipe pipe
, bool state
)
1121 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1124 if (HAS_DDI(dev_priv
->dev
)) {
1125 /* DDI does not have a specific FDI_TX register */
1126 reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1127 val
= I915_READ(reg
);
1128 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
1130 reg
= FDI_TX_CTL(pipe
);
1131 val
= I915_READ(reg
);
1132 cur_state
= !!(val
& FDI_TX_ENABLE
);
1134 WARN(cur_state
!= state
,
1135 "FDI TX state assertion failure (expected %s, current %s)\n",
1136 state_string(state
), state_string(cur_state
));
1138 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1139 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1141 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1142 enum pipe pipe
, bool state
)
1148 reg
= FDI_RX_CTL(pipe
);
1149 val
= I915_READ(reg
);
1150 cur_state
= !!(val
& FDI_RX_ENABLE
);
1151 WARN(cur_state
!= state
,
1152 "FDI RX state assertion failure (expected %s, current %s)\n",
1153 state_string(state
), state_string(cur_state
));
1155 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1156 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1158 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1164 /* ILK FDI PLL is always enabled */
1165 if (INTEL_INFO(dev_priv
->dev
)->gen
== 5)
1168 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1169 if (HAS_DDI(dev_priv
->dev
))
1172 reg
= FDI_TX_CTL(pipe
);
1173 val
= I915_READ(reg
);
1174 WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1177 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1178 enum pipe pipe
, bool state
)
1184 reg
= FDI_RX_CTL(pipe
);
1185 val
= I915_READ(reg
);
1186 cur_state
= !!(val
& FDI_RX_PLL_ENABLE
);
1187 WARN(cur_state
!= state
,
1188 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1189 state_string(state
), state_string(cur_state
));
1192 static void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1195 int pp_reg
, lvds_reg
;
1197 enum pipe panel_pipe
= PIPE_A
;
1200 if (HAS_PCH_SPLIT(dev_priv
->dev
)) {
1201 pp_reg
= PCH_PP_CONTROL
;
1202 lvds_reg
= PCH_LVDS
;
1204 pp_reg
= PP_CONTROL
;
1208 val
= I915_READ(pp_reg
);
1209 if (!(val
& PANEL_POWER_ON
) ||
1210 ((val
& PANEL_UNLOCK_REGS
) == PANEL_UNLOCK_REGS
))
1213 if (I915_READ(lvds_reg
) & LVDS_PIPEB_SELECT
)
1214 panel_pipe
= PIPE_B
;
1216 WARN(panel_pipe
== pipe
&& locked
,
1217 "panel assertion failure, pipe %c regs locked\n",
1221 static void assert_cursor(struct drm_i915_private
*dev_priv
,
1222 enum pipe pipe
, bool state
)
1224 struct drm_device
*dev
= dev_priv
->dev
;
1227 if (IS_845G(dev
) || IS_I865G(dev
))
1228 cur_state
= I915_READ(_CURACNTR
) & CURSOR_ENABLE
;
1230 cur_state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
1232 WARN(cur_state
!= state
,
1233 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1234 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1236 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1237 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1239 void assert_pipe(struct drm_i915_private
*dev_priv
,
1240 enum pipe pipe
, bool state
)
1245 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1248 /* if we need the pipe A quirk it must be always on */
1249 if (pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
1252 if (!intel_display_power_enabled(dev_priv
,
1253 POWER_DOMAIN_TRANSCODER(cpu_transcoder
))) {
1256 reg
= PIPECONF(cpu_transcoder
);
1257 val
= I915_READ(reg
);
1258 cur_state
= !!(val
& PIPECONF_ENABLE
);
1261 WARN(cur_state
!= state
,
1262 "pipe %c assertion failure (expected %s, current %s)\n",
1263 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1266 static void assert_plane(struct drm_i915_private
*dev_priv
,
1267 enum plane plane
, bool state
)
1273 reg
= DSPCNTR(plane
);
1274 val
= I915_READ(reg
);
1275 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1276 WARN(cur_state
!= state
,
1277 "plane %c assertion failure (expected %s, current %s)\n",
1278 plane_name(plane
), state_string(state
), state_string(cur_state
));
1281 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1282 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1284 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1287 struct drm_device
*dev
= dev_priv
->dev
;
1292 /* Primary planes are fixed to pipes on gen4+ */
1293 if (INTEL_INFO(dev
)->gen
>= 4) {
1294 reg
= DSPCNTR(pipe
);
1295 val
= I915_READ(reg
);
1296 WARN(val
& DISPLAY_PLANE_ENABLE
,
1297 "plane %c assertion failure, should be disabled but not\n",
1302 /* Need to check both planes against the pipe */
1305 val
= I915_READ(reg
);
1306 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1307 DISPPLANE_SEL_PIPE_SHIFT
;
1308 WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1309 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1310 plane_name(i
), pipe_name(pipe
));
1314 static void assert_sprites_disabled(struct drm_i915_private
*dev_priv
,
1317 struct drm_device
*dev
= dev_priv
->dev
;
1321 if (IS_VALLEYVIEW(dev
)) {
1322 for_each_sprite(pipe
, sprite
) {
1323 reg
= SPCNTR(pipe
, sprite
);
1324 val
= I915_READ(reg
);
1325 WARN(val
& SP_ENABLE
,
1326 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1327 sprite_name(pipe
, sprite
), pipe_name(pipe
));
1329 } else if (INTEL_INFO(dev
)->gen
>= 7) {
1331 val
= I915_READ(reg
);
1332 WARN(val
& SPRITE_ENABLE
,
1333 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1334 plane_name(pipe
), pipe_name(pipe
));
1335 } else if (INTEL_INFO(dev
)->gen
>= 5) {
1336 reg
= DVSCNTR(pipe
);
1337 val
= I915_READ(reg
);
1338 WARN(val
& DVS_ENABLE
,
1339 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1340 plane_name(pipe
), pipe_name(pipe
));
1344 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1349 WARN_ON(!(HAS_PCH_IBX(dev_priv
->dev
) || HAS_PCH_CPT(dev_priv
->dev
)));
1351 val
= I915_READ(PCH_DREF_CONTROL
);
1352 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1353 DREF_SUPERSPREAD_SOURCE_MASK
));
1354 WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1357 static void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1364 reg
= PCH_TRANSCONF(pipe
);
1365 val
= I915_READ(reg
);
1366 enabled
= !!(val
& TRANS_ENABLE
);
1368 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1372 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1373 enum pipe pipe
, u32 port_sel
, u32 val
)
1375 if ((val
& DP_PORT_EN
) == 0)
1378 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1379 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1380 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1381 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1383 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1384 if ((val
& DP_PIPE_MASK_CHV
) != DP_PIPE_SELECT_CHV(pipe
))
1387 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1393 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1394 enum pipe pipe
, u32 val
)
1396 if ((val
& SDVO_ENABLE
) == 0)
1399 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1400 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1402 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1403 if ((val
& SDVO_PIPE_SEL_MASK_CHV
) != SDVO_PIPE_SEL_CHV(pipe
))
1406 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1412 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1413 enum pipe pipe
, u32 val
)
1415 if ((val
& LVDS_PORT_EN
) == 0)
1418 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1419 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1422 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1428 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1429 enum pipe pipe
, u32 val
)
1431 if ((val
& ADPA_DAC_ENABLE
) == 0)
1433 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1434 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1437 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1443 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1444 enum pipe pipe
, int reg
, u32 port_sel
)
1446 u32 val
= I915_READ(reg
);
1447 WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1448 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1449 reg
, pipe_name(pipe
));
1451 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& DP_PORT_EN
) == 0
1452 && (val
& DP_PIPEB_SELECT
),
1453 "IBX PCH dp port still using transcoder B\n");
1456 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1457 enum pipe pipe
, int reg
)
1459 u32 val
= I915_READ(reg
);
1460 WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1461 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1462 reg
, pipe_name(pipe
));
1464 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& SDVO_ENABLE
) == 0
1465 && (val
& SDVO_PIPE_B_SELECT
),
1466 "IBX PCH hdmi port still using transcoder B\n");
1469 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1475 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1476 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1477 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1480 val
= I915_READ(reg
);
1481 WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1482 "PCH VGA enabled on transcoder %c, should be disabled\n",
1486 val
= I915_READ(reg
);
1487 WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1488 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1491 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1492 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1493 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1496 static void intel_init_dpio(struct drm_device
*dev
)
1498 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1500 if (!IS_VALLEYVIEW(dev
))
1504 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1505 * CHV x1 PHY (DP/HDMI D)
1506 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1508 if (IS_CHERRYVIEW(dev
)) {
1509 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO_2
;
1510 DPIO_PHY_IOSF_PORT(DPIO_PHY1
) = IOSF_PORT_DPIO
;
1512 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO
;
1516 static void intel_reset_dpio(struct drm_device
*dev
)
1518 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1520 if (IS_CHERRYVIEW(dev
)) {
1524 for (phy
= DPIO_PHY0
; phy
< I915_NUM_PHYS_VLV
; phy
++) {
1525 /* Poll for phypwrgood signal */
1526 if (wait_for(I915_READ(DISPLAY_PHY_STATUS
) &
1527 PHY_POWERGOOD(phy
), 1))
1528 DRM_ERROR("Display PHY %d is not power up\n", phy
);
1531 * Deassert common lane reset for PHY.
1533 * This should only be done on init and resume from S3
1534 * with both PLLs disabled, or we risk losing DPIO and
1535 * PLL synchronization.
1537 val
= I915_READ(DISPLAY_PHY_CONTROL
);
1538 I915_WRITE(DISPLAY_PHY_CONTROL
,
1539 PHY_COM_LANE_RESET_DEASSERT(phy
, val
));
1544 static void vlv_enable_pll(struct intel_crtc
*crtc
)
1546 struct drm_device
*dev
= crtc
->base
.dev
;
1547 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1548 int reg
= DPLL(crtc
->pipe
);
1549 u32 dpll
= crtc
->config
.dpll_hw_state
.dpll
;
1551 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1553 /* No really, not for ILK+ */
1554 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
));
1556 /* PLL is protected by panel, make sure we can write it */
1557 if (IS_MOBILE(dev_priv
->dev
) && !IS_I830(dev_priv
->dev
))
1558 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1560 I915_WRITE(reg
, dpll
);
1564 if (wait_for(((I915_READ(reg
) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1565 DRM_ERROR("DPLL %d failed to lock\n", crtc
->pipe
);
1567 I915_WRITE(DPLL_MD(crtc
->pipe
), crtc
->config
.dpll_hw_state
.dpll_md
);
1568 POSTING_READ(DPLL_MD(crtc
->pipe
));
1570 /* We do this three times for luck */
1571 I915_WRITE(reg
, dpll
);
1573 udelay(150); /* wait for warmup */
1574 I915_WRITE(reg
, dpll
);
1576 udelay(150); /* wait for warmup */
1577 I915_WRITE(reg
, dpll
);
1579 udelay(150); /* wait for warmup */
1582 static void chv_enable_pll(struct intel_crtc
*crtc
)
1584 struct drm_device
*dev
= crtc
->base
.dev
;
1585 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1586 int pipe
= crtc
->pipe
;
1587 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1590 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1592 BUG_ON(!IS_CHERRYVIEW(dev_priv
->dev
));
1594 mutex_lock(&dev_priv
->dpio_lock
);
1596 /* Enable back the 10bit clock to display controller */
1597 tmp
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1598 tmp
|= DPIO_DCLKP_EN
;
1599 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), tmp
);
1602 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1607 I915_WRITE(DPLL(pipe
), crtc
->config
.dpll_hw_state
.dpll
);
1609 /* Check PLL is locked */
1610 if (wait_for(((I915_READ(DPLL(pipe
)) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1611 DRM_ERROR("PLL %d failed to lock\n", pipe
);
1613 /* not sure when this should be written */
1614 I915_WRITE(DPLL_MD(pipe
), crtc
->config
.dpll_hw_state
.dpll_md
);
1615 POSTING_READ(DPLL_MD(pipe
));
1617 mutex_unlock(&dev_priv
->dpio_lock
);
1620 static void i9xx_enable_pll(struct intel_crtc
*crtc
)
1622 struct drm_device
*dev
= crtc
->base
.dev
;
1623 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1624 int reg
= DPLL(crtc
->pipe
);
1625 u32 dpll
= crtc
->config
.dpll_hw_state
.dpll
;
1627 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1629 /* No really, not for ILK+ */
1630 BUG_ON(INTEL_INFO(dev
)->gen
>= 5);
1632 /* PLL is protected by panel, make sure we can write it */
1633 if (IS_MOBILE(dev
) && !IS_I830(dev
))
1634 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1636 I915_WRITE(reg
, dpll
);
1638 /* Wait for the clocks to stabilize. */
1642 if (INTEL_INFO(dev
)->gen
>= 4) {
1643 I915_WRITE(DPLL_MD(crtc
->pipe
),
1644 crtc
->config
.dpll_hw_state
.dpll_md
);
1646 /* The pixel multiplier can only be updated once the
1647 * DPLL is enabled and the clocks are stable.
1649 * So write it again.
1651 I915_WRITE(reg
, dpll
);
1654 /* We do this three times for luck */
1655 I915_WRITE(reg
, dpll
);
1657 udelay(150); /* wait for warmup */
1658 I915_WRITE(reg
, dpll
);
1660 udelay(150); /* wait for warmup */
1661 I915_WRITE(reg
, dpll
);
1663 udelay(150); /* wait for warmup */
1667 * i9xx_disable_pll - disable a PLL
1668 * @dev_priv: i915 private structure
1669 * @pipe: pipe PLL to disable
1671 * Disable the PLL for @pipe, making sure the pipe is off first.
1673 * Note! This is for pre-ILK only.
1675 static void i9xx_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1677 /* Don't disable pipe A or pipe A PLLs if needed */
1678 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1681 /* Make sure the pipe isn't still relying on us */
1682 assert_pipe_disabled(dev_priv
, pipe
);
1684 I915_WRITE(DPLL(pipe
), 0);
1685 POSTING_READ(DPLL(pipe
));
1688 static void vlv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1692 /* Make sure the pipe isn't still relying on us */
1693 assert_pipe_disabled(dev_priv
, pipe
);
1696 * Leave integrated clock source and reference clock enabled for pipe B.
1697 * The latter is needed for VGA hotplug / manual detection.
1700 val
= DPLL_INTEGRATED_CRI_CLK_VLV
| DPLL_REFA_CLK_ENABLE_VLV
;
1701 I915_WRITE(DPLL(pipe
), val
);
1702 POSTING_READ(DPLL(pipe
));
1706 static void chv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1708 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1711 /* Make sure the pipe isn't still relying on us */
1712 assert_pipe_disabled(dev_priv
, pipe
);
1714 /* Set PLL en = 0 */
1715 val
= DPLL_SSC_REF_CLOCK_CHV
;
1717 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
1718 I915_WRITE(DPLL(pipe
), val
);
1719 POSTING_READ(DPLL(pipe
));
1721 mutex_lock(&dev_priv
->dpio_lock
);
1723 /* Disable 10bit clock to display controller */
1724 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1725 val
&= ~DPIO_DCLKP_EN
;
1726 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), val
);
1728 /* disable left/right clock distribution */
1729 if (pipe
!= PIPE_B
) {
1730 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
);
1731 val
&= ~(CHV_BUFLEFTENA1_MASK
| CHV_BUFRIGHTENA1_MASK
);
1732 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
, val
);
1734 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
);
1735 val
&= ~(CHV_BUFLEFTENA2_MASK
| CHV_BUFRIGHTENA2_MASK
);
1736 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
, val
);
1739 mutex_unlock(&dev_priv
->dpio_lock
);
1742 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1743 struct intel_digital_port
*dport
)
1748 switch (dport
->port
) {
1750 port_mask
= DPLL_PORTB_READY_MASK
;
1754 port_mask
= DPLL_PORTC_READY_MASK
;
1758 port_mask
= DPLL_PORTD_READY_MASK
;
1759 dpll_reg
= DPIO_PHY_STATUS
;
1765 if (wait_for((I915_READ(dpll_reg
) & port_mask
) == 0, 1000))
1766 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1767 port_name(dport
->port
), I915_READ(dpll_reg
));
1770 static void intel_prepare_shared_dpll(struct intel_crtc
*crtc
)
1772 struct drm_device
*dev
= crtc
->base
.dev
;
1773 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1774 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1776 if (WARN_ON(pll
== NULL
))
1779 WARN_ON(!pll
->refcount
);
1780 if (pll
->active
== 0) {
1781 DRM_DEBUG_DRIVER("setting up %s\n", pll
->name
);
1783 assert_shared_dpll_disabled(dev_priv
, pll
);
1785 pll
->mode_set(dev_priv
, pll
);
1790 * intel_enable_shared_dpll - enable PCH PLL
1791 * @dev_priv: i915 private structure
1792 * @pipe: pipe PLL to enable
1794 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1795 * drives the transcoder clock.
1797 static void intel_enable_shared_dpll(struct intel_crtc
*crtc
)
1799 struct drm_device
*dev
= crtc
->base
.dev
;
1800 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1801 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1803 if (WARN_ON(pll
== NULL
))
1806 if (WARN_ON(pll
->refcount
== 0))
1809 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1810 pll
->name
, pll
->active
, pll
->on
,
1811 crtc
->base
.base
.id
);
1813 if (pll
->active
++) {
1815 assert_shared_dpll_enabled(dev_priv
, pll
);
1820 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
1822 DRM_DEBUG_KMS("enabling %s\n", pll
->name
);
1823 pll
->enable(dev_priv
, pll
);
1827 void intel_disable_shared_dpll(struct intel_crtc
*crtc
)
1829 struct drm_device
*dev
= crtc
->base
.dev
;
1830 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1831 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1833 /* PCH only available on ILK+ */
1834 BUG_ON(INTEL_INFO(dev
)->gen
< 5);
1835 if (WARN_ON(pll
== NULL
))
1838 if (WARN_ON(pll
->refcount
== 0))
1841 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1842 pll
->name
, pll
->active
, pll
->on
,
1843 crtc
->base
.base
.id
);
1845 if (WARN_ON(pll
->active
== 0)) {
1846 assert_shared_dpll_disabled(dev_priv
, pll
);
1850 assert_shared_dpll_enabled(dev_priv
, pll
);
1855 DRM_DEBUG_KMS("disabling %s\n", pll
->name
);
1856 pll
->disable(dev_priv
, pll
);
1859 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
1862 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1865 struct drm_device
*dev
= dev_priv
->dev
;
1866 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1867 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1868 uint32_t reg
, val
, pipeconf_val
;
1870 /* PCH only available on ILK+ */
1871 BUG_ON(INTEL_INFO(dev
)->gen
< 5);
1873 /* Make sure PCH DPLL is enabled */
1874 assert_shared_dpll_enabled(dev_priv
,
1875 intel_crtc_to_shared_dpll(intel_crtc
));
1877 /* FDI must be feeding us bits for PCH ports */
1878 assert_fdi_tx_enabled(dev_priv
, pipe
);
1879 assert_fdi_rx_enabled(dev_priv
, pipe
);
1881 if (HAS_PCH_CPT(dev
)) {
1882 /* Workaround: Set the timing override bit before enabling the
1883 * pch transcoder. */
1884 reg
= TRANS_CHICKEN2(pipe
);
1885 val
= I915_READ(reg
);
1886 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1887 I915_WRITE(reg
, val
);
1890 reg
= PCH_TRANSCONF(pipe
);
1891 val
= I915_READ(reg
);
1892 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1894 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1896 * make the BPC in transcoder be consistent with
1897 * that in pipeconf reg.
1899 val
&= ~PIPECONF_BPC_MASK
;
1900 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
1903 val
&= ~TRANS_INTERLACE_MASK
;
1904 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1905 if (HAS_PCH_IBX(dev_priv
->dev
) &&
1906 intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
))
1907 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1909 val
|= TRANS_INTERLACED
;
1911 val
|= TRANS_PROGRESSIVE
;
1913 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1914 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1915 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
1918 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1919 enum transcoder cpu_transcoder
)
1921 u32 val
, pipeconf_val
;
1923 /* PCH only available on ILK+ */
1924 BUG_ON(INTEL_INFO(dev_priv
->dev
)->gen
< 5);
1926 /* FDI must be feeding us bits for PCH ports */
1927 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
1928 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
1930 /* Workaround: set timing override bit. */
1931 val
= I915_READ(_TRANSA_CHICKEN2
);
1932 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1933 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1936 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
1938 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
1939 PIPECONF_INTERLACED_ILK
)
1940 val
|= TRANS_INTERLACED
;
1942 val
|= TRANS_PROGRESSIVE
;
1944 I915_WRITE(LPT_TRANSCONF
, val
);
1945 if (wait_for(I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
, 100))
1946 DRM_ERROR("Failed to enable PCH transcoder\n");
1949 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1952 struct drm_device
*dev
= dev_priv
->dev
;
1955 /* FDI relies on the transcoder */
1956 assert_fdi_tx_disabled(dev_priv
, pipe
);
1957 assert_fdi_rx_disabled(dev_priv
, pipe
);
1959 /* Ports must be off as well */
1960 assert_pch_ports_disabled(dev_priv
, pipe
);
1962 reg
= PCH_TRANSCONF(pipe
);
1963 val
= I915_READ(reg
);
1964 val
&= ~TRANS_ENABLE
;
1965 I915_WRITE(reg
, val
);
1966 /* wait for PCH transcoder off, transcoder state */
1967 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
1968 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
1970 if (!HAS_PCH_IBX(dev
)) {
1971 /* Workaround: Clear the timing override chicken bit again. */
1972 reg
= TRANS_CHICKEN2(pipe
);
1973 val
= I915_READ(reg
);
1974 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1975 I915_WRITE(reg
, val
);
1979 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
1983 val
= I915_READ(LPT_TRANSCONF
);
1984 val
&= ~TRANS_ENABLE
;
1985 I915_WRITE(LPT_TRANSCONF
, val
);
1986 /* wait for PCH transcoder off, transcoder state */
1987 if (wait_for((I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
) == 0, 50))
1988 DRM_ERROR("Failed to disable PCH transcoder\n");
1990 /* Workaround: clear timing override bit. */
1991 val
= I915_READ(_TRANSA_CHICKEN2
);
1992 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1993 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1997 * intel_enable_pipe - enable a pipe, asserting requirements
1998 * @crtc: crtc responsible for the pipe
2000 * Enable @crtc's pipe, making sure that various hardware specific requirements
2001 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2003 static void intel_enable_pipe(struct intel_crtc
*crtc
)
2005 struct drm_device
*dev
= crtc
->base
.dev
;
2006 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2007 enum pipe pipe
= crtc
->pipe
;
2008 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
2010 enum pipe pch_transcoder
;
2014 assert_planes_disabled(dev_priv
, pipe
);
2015 assert_cursor_disabled(dev_priv
, pipe
);
2016 assert_sprites_disabled(dev_priv
, pipe
);
2018 if (HAS_PCH_LPT(dev_priv
->dev
))
2019 pch_transcoder
= TRANSCODER_A
;
2021 pch_transcoder
= pipe
;
2024 * A pipe without a PLL won't actually be able to drive bits from
2025 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2028 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
2029 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DSI
))
2030 assert_dsi_pll_enabled(dev_priv
);
2032 assert_pll_enabled(dev_priv
, pipe
);
2034 if (crtc
->config
.has_pch_encoder
) {
2035 /* if driving the PCH, we need FDI enabled */
2036 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
2037 assert_fdi_tx_pll_enabled(dev_priv
,
2038 (enum pipe
) cpu_transcoder
);
2040 /* FIXME: assert CPU port conditions for SNB+ */
2043 reg
= PIPECONF(cpu_transcoder
);
2044 val
= I915_READ(reg
);
2045 if (val
& PIPECONF_ENABLE
) {
2046 WARN_ON(!(pipe
== PIPE_A
&&
2047 dev_priv
->quirks
& QUIRK_PIPEA_FORCE
));
2051 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
2056 * intel_disable_pipe - disable a pipe, asserting requirements
2057 * @dev_priv: i915 private structure
2058 * @pipe: pipe to disable
2060 * Disable @pipe, making sure that various hardware specific requirements
2061 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
2063 * @pipe should be %PIPE_A or %PIPE_B.
2065 * Will wait until the pipe has shut down before returning.
2067 static void intel_disable_pipe(struct drm_i915_private
*dev_priv
,
2070 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
2076 * Make sure planes won't keep trying to pump pixels to us,
2077 * or we might hang the display.
2079 assert_planes_disabled(dev_priv
, pipe
);
2080 assert_cursor_disabled(dev_priv
, pipe
);
2081 assert_sprites_disabled(dev_priv
, pipe
);
2083 /* Don't disable pipe A or pipe A PLLs if needed */
2084 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
2087 reg
= PIPECONF(cpu_transcoder
);
2088 val
= I915_READ(reg
);
2089 if ((val
& PIPECONF_ENABLE
) == 0)
2092 I915_WRITE(reg
, val
& ~PIPECONF_ENABLE
);
2093 intel_wait_for_pipe_off(dev_priv
->dev
, pipe
);
2097 * Plane regs are double buffered, going from enabled->disabled needs a
2098 * trigger in order to latch. The display address reg provides this.
2100 void intel_flush_primary_plane(struct drm_i915_private
*dev_priv
,
2103 struct drm_device
*dev
= dev_priv
->dev
;
2104 u32 reg
= INTEL_INFO(dev
)->gen
>= 4 ? DSPSURF(plane
) : DSPADDR(plane
);
2106 I915_WRITE(reg
, I915_READ(reg
));
2111 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2112 * @dev_priv: i915 private structure
2113 * @plane: plane to enable
2114 * @pipe: pipe being fed
2116 * Enable @plane on @pipe, making sure that @pipe is running first.
2118 static void intel_enable_primary_hw_plane(struct drm_i915_private
*dev_priv
,
2119 enum plane plane
, enum pipe pipe
)
2121 struct drm_device
*dev
= dev_priv
->dev
;
2122 struct intel_crtc
*intel_crtc
=
2123 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
2127 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2128 assert_pipe_enabled(dev_priv
, pipe
);
2130 if (intel_crtc
->primary_enabled
)
2133 intel_crtc
->primary_enabled
= true;
2135 reg
= DSPCNTR(plane
);
2136 val
= I915_READ(reg
);
2137 WARN_ON(val
& DISPLAY_PLANE_ENABLE
);
2139 I915_WRITE(reg
, val
| DISPLAY_PLANE_ENABLE
);
2140 intel_flush_primary_plane(dev_priv
, plane
);
2143 * BDW signals flip done immediately if the plane
2144 * is disabled, even if the plane enable is already
2145 * armed to occur at the next vblank :(
2147 if (IS_BROADWELL(dev
))
2148 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2152 * intel_disable_primary_hw_plane - disable the primary hardware plane
2153 * @dev_priv: i915 private structure
2154 * @plane: plane to disable
2155 * @pipe: pipe consuming the data
2157 * Disable @plane; should be an independent operation.
2159 static void intel_disable_primary_hw_plane(struct drm_i915_private
*dev_priv
,
2160 enum plane plane
, enum pipe pipe
)
2162 struct intel_crtc
*intel_crtc
=
2163 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
2167 if (!intel_crtc
->primary_enabled
)
2170 intel_crtc
->primary_enabled
= false;
2172 reg
= DSPCNTR(plane
);
2173 val
= I915_READ(reg
);
2174 WARN_ON((val
& DISPLAY_PLANE_ENABLE
) == 0);
2176 I915_WRITE(reg
, val
& ~DISPLAY_PLANE_ENABLE
);
2177 intel_flush_primary_plane(dev_priv
, plane
);
2180 static bool need_vtd_wa(struct drm_device
*dev
)
2182 #ifdef CONFIG_INTEL_IOMMU
2183 if (INTEL_INFO(dev
)->gen
>= 6 && intel_iommu_gfx_mapped
)
2189 static int intel_align_height(struct drm_device
*dev
, int height
, bool tiled
)
2193 tile_height
= tiled
? (IS_GEN2(dev
) ? 16 : 8) : 1;
2194 return ALIGN(height
, tile_height
);
2198 intel_pin_and_fence_fb_obj(struct drm_device
*dev
,
2199 struct drm_i915_gem_object
*obj
,
2200 struct intel_engine_cs
*pipelined
)
2202 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2206 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
2208 switch (obj
->tiling_mode
) {
2209 case I915_TILING_NONE
:
2210 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
2211 alignment
= 128 * 1024;
2212 else if (INTEL_INFO(dev
)->gen
>= 4)
2213 alignment
= 4 * 1024;
2215 alignment
= 64 * 1024;
2218 /* pin() will align the object as required by fence */
2222 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2228 /* Note that the w/a also requires 64 PTE of padding following the
2229 * bo. We currently fill all unused PTE with the shadow page and so
2230 * we should always have valid PTE following the scanout preventing
2233 if (need_vtd_wa(dev
) && alignment
< 256 * 1024)
2234 alignment
= 256 * 1024;
2237 * Global gtt pte registers are special registers which actually forward
2238 * writes to a chunk of system memory. Which means that there is no risk
2239 * that the register values disappear as soon as we call
2240 * intel_runtime_pm_put(), so it is correct to wrap only the
2241 * pin/unpin/fence and not more.
2243 intel_runtime_pm_get(dev_priv
);
2245 dev_priv
->mm
.interruptible
= false;
2246 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
);
2248 goto err_interruptible
;
2250 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2251 * fence, whereas 965+ only requires a fence if using
2252 * framebuffer compression. For simplicity, we always install
2253 * a fence as the cost is not that onerous.
2255 ret
= i915_gem_object_get_fence(obj
);
2259 i915_gem_object_pin_fence(obj
);
2261 dev_priv
->mm
.interruptible
= true;
2262 intel_runtime_pm_put(dev_priv
);
2266 i915_gem_object_unpin_from_display_plane(obj
);
2268 dev_priv
->mm
.interruptible
= true;
2269 intel_runtime_pm_put(dev_priv
);
2273 void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
)
2275 WARN_ON(!mutex_is_locked(&obj
->base
.dev
->struct_mutex
));
2277 i915_gem_object_unpin_fence(obj
);
2278 i915_gem_object_unpin_from_display_plane(obj
);
2281 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2282 * is assumed to be a power-of-two. */
2283 unsigned long intel_gen4_compute_page_offset(int *x
, int *y
,
2284 unsigned int tiling_mode
,
2288 if (tiling_mode
!= I915_TILING_NONE
) {
2289 unsigned int tile_rows
, tiles
;
2294 tiles
= *x
/ (512/cpp
);
2297 return tile_rows
* pitch
* 8 + tiles
* 4096;
2299 unsigned int offset
;
2301 offset
= *y
* pitch
+ *x
* cpp
;
2303 *x
= (offset
& 4095) / cpp
;
2304 return offset
& -4096;
2308 int intel_format_to_fourcc(int format
)
2311 case DISPPLANE_8BPP
:
2312 return DRM_FORMAT_C8
;
2313 case DISPPLANE_BGRX555
:
2314 return DRM_FORMAT_XRGB1555
;
2315 case DISPPLANE_BGRX565
:
2316 return DRM_FORMAT_RGB565
;
2318 case DISPPLANE_BGRX888
:
2319 return DRM_FORMAT_XRGB8888
;
2320 case DISPPLANE_RGBX888
:
2321 return DRM_FORMAT_XBGR8888
;
2322 case DISPPLANE_BGRX101010
:
2323 return DRM_FORMAT_XRGB2101010
;
2324 case DISPPLANE_RGBX101010
:
2325 return DRM_FORMAT_XBGR2101010
;
2329 static bool intel_alloc_plane_obj(struct intel_crtc
*crtc
,
2330 struct intel_plane_config
*plane_config
)
2332 struct drm_device
*dev
= crtc
->base
.dev
;
2333 struct drm_i915_gem_object
*obj
= NULL
;
2334 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
2335 u32 base
= plane_config
->base
;
2337 if (plane_config
->size
== 0)
2340 obj
= i915_gem_object_create_stolen_for_preallocated(dev
, base
, base
,
2341 plane_config
->size
);
2345 if (plane_config
->tiled
) {
2346 obj
->tiling_mode
= I915_TILING_X
;
2347 obj
->stride
= crtc
->base
.primary
->fb
->pitches
[0];
2350 mode_cmd
.pixel_format
= crtc
->base
.primary
->fb
->pixel_format
;
2351 mode_cmd
.width
= crtc
->base
.primary
->fb
->width
;
2352 mode_cmd
.height
= crtc
->base
.primary
->fb
->height
;
2353 mode_cmd
.pitches
[0] = crtc
->base
.primary
->fb
->pitches
[0];
2355 mutex_lock(&dev
->struct_mutex
);
2357 if (intel_framebuffer_init(dev
, to_intel_framebuffer(crtc
->base
.primary
->fb
),
2359 DRM_DEBUG_KMS("intel fb init failed\n");
2363 obj
->frontbuffer_bits
= INTEL_FRONTBUFFER_PRIMARY(crtc
->pipe
);
2364 mutex_unlock(&dev
->struct_mutex
);
2366 DRM_DEBUG_KMS("plane fb obj %p\n", obj
);
2370 drm_gem_object_unreference(&obj
->base
);
2371 mutex_unlock(&dev
->struct_mutex
);
2375 static void intel_find_plane_obj(struct intel_crtc
*intel_crtc
,
2376 struct intel_plane_config
*plane_config
)
2378 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2380 struct intel_crtc
*i
;
2381 struct drm_i915_gem_object
*obj
;
2383 if (!intel_crtc
->base
.primary
->fb
)
2386 if (intel_alloc_plane_obj(intel_crtc
, plane_config
))
2389 kfree(intel_crtc
->base
.primary
->fb
);
2390 intel_crtc
->base
.primary
->fb
= NULL
;
2393 * Failed to alloc the obj, check to see if we should share
2394 * an fb with another CRTC instead
2396 for_each_crtc(dev
, c
) {
2397 i
= to_intel_crtc(c
);
2399 if (c
== &intel_crtc
->base
)
2405 obj
= intel_fb_obj(c
->primary
->fb
);
2409 if (i915_gem_obj_ggtt_offset(obj
) == plane_config
->base
) {
2410 drm_framebuffer_reference(c
->primary
->fb
);
2411 intel_crtc
->base
.primary
->fb
= c
->primary
->fb
;
2412 obj
->frontbuffer_bits
|= INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
);
2418 static void i9xx_update_primary_plane(struct drm_crtc
*crtc
,
2419 struct drm_framebuffer
*fb
,
2422 struct drm_device
*dev
= crtc
->dev
;
2423 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2424 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2425 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2426 int plane
= intel_crtc
->plane
;
2427 unsigned long linear_offset
;
2431 reg
= DSPCNTR(plane
);
2432 dspcntr
= I915_READ(reg
);
2433 /* Mask out pixel format bits in case we change it */
2434 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2435 switch (fb
->pixel_format
) {
2437 dspcntr
|= DISPPLANE_8BPP
;
2439 case DRM_FORMAT_XRGB1555
:
2440 case DRM_FORMAT_ARGB1555
:
2441 dspcntr
|= DISPPLANE_BGRX555
;
2443 case DRM_FORMAT_RGB565
:
2444 dspcntr
|= DISPPLANE_BGRX565
;
2446 case DRM_FORMAT_XRGB8888
:
2447 case DRM_FORMAT_ARGB8888
:
2448 dspcntr
|= DISPPLANE_BGRX888
;
2450 case DRM_FORMAT_XBGR8888
:
2451 case DRM_FORMAT_ABGR8888
:
2452 dspcntr
|= DISPPLANE_RGBX888
;
2454 case DRM_FORMAT_XRGB2101010
:
2455 case DRM_FORMAT_ARGB2101010
:
2456 dspcntr
|= DISPPLANE_BGRX101010
;
2458 case DRM_FORMAT_XBGR2101010
:
2459 case DRM_FORMAT_ABGR2101010
:
2460 dspcntr
|= DISPPLANE_RGBX101010
;
2466 if (INTEL_INFO(dev
)->gen
>= 4) {
2467 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2468 dspcntr
|= DISPPLANE_TILED
;
2470 dspcntr
&= ~DISPPLANE_TILED
;
2474 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2476 I915_WRITE(reg
, dspcntr
);
2478 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2480 if (INTEL_INFO(dev
)->gen
>= 4) {
2481 intel_crtc
->dspaddr_offset
=
2482 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2483 fb
->bits_per_pixel
/ 8,
2485 linear_offset
-= intel_crtc
->dspaddr_offset
;
2487 intel_crtc
->dspaddr_offset
= linear_offset
;
2490 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2491 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2493 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2494 if (INTEL_INFO(dev
)->gen
>= 4) {
2495 I915_WRITE(DSPSURF(plane
),
2496 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2497 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2498 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2500 I915_WRITE(DSPADDR(plane
), i915_gem_obj_ggtt_offset(obj
) + linear_offset
);
2504 static void ironlake_update_primary_plane(struct drm_crtc
*crtc
,
2505 struct drm_framebuffer
*fb
,
2508 struct drm_device
*dev
= crtc
->dev
;
2509 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2510 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2511 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2512 int plane
= intel_crtc
->plane
;
2513 unsigned long linear_offset
;
2517 reg
= DSPCNTR(plane
);
2518 dspcntr
= I915_READ(reg
);
2519 /* Mask out pixel format bits in case we change it */
2520 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2521 switch (fb
->pixel_format
) {
2523 dspcntr
|= DISPPLANE_8BPP
;
2525 case DRM_FORMAT_RGB565
:
2526 dspcntr
|= DISPPLANE_BGRX565
;
2528 case DRM_FORMAT_XRGB8888
:
2529 case DRM_FORMAT_ARGB8888
:
2530 dspcntr
|= DISPPLANE_BGRX888
;
2532 case DRM_FORMAT_XBGR8888
:
2533 case DRM_FORMAT_ABGR8888
:
2534 dspcntr
|= DISPPLANE_RGBX888
;
2536 case DRM_FORMAT_XRGB2101010
:
2537 case DRM_FORMAT_ARGB2101010
:
2538 dspcntr
|= DISPPLANE_BGRX101010
;
2540 case DRM_FORMAT_XBGR2101010
:
2541 case DRM_FORMAT_ABGR2101010
:
2542 dspcntr
|= DISPPLANE_RGBX101010
;
2548 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2549 dspcntr
|= DISPPLANE_TILED
;
2551 dspcntr
&= ~DISPPLANE_TILED
;
2553 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2554 dspcntr
&= ~DISPPLANE_TRICKLE_FEED_DISABLE
;
2556 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2558 I915_WRITE(reg
, dspcntr
);
2560 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2561 intel_crtc
->dspaddr_offset
=
2562 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2563 fb
->bits_per_pixel
/ 8,
2565 linear_offset
-= intel_crtc
->dspaddr_offset
;
2567 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2568 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2570 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2571 I915_WRITE(DSPSURF(plane
),
2572 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2573 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2574 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2576 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2577 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2582 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2584 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2585 int x
, int y
, enum mode_set_atomic state
)
2587 struct drm_device
*dev
= crtc
->dev
;
2588 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2590 if (dev_priv
->display
.disable_fbc
)
2591 dev_priv
->display
.disable_fbc(dev
);
2592 intel_increase_pllclock(dev
, to_intel_crtc(crtc
)->pipe
);
2594 dev_priv
->display
.update_primary_plane(crtc
, fb
, x
, y
);
2599 void intel_display_handle_reset(struct drm_device
*dev
)
2601 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2602 struct drm_crtc
*crtc
;
2605 * Flips in the rings have been nuked by the reset,
2606 * so complete all pending flips so that user space
2607 * will get its events and not get stuck.
2609 * Also update the base address of all primary
2610 * planes to the the last fb to make sure we're
2611 * showing the correct fb after a reset.
2613 * Need to make two loops over the crtcs so that we
2614 * don't try to grab a crtc mutex before the
2615 * pending_flip_queue really got woken up.
2618 for_each_crtc(dev
, crtc
) {
2619 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2620 enum plane plane
= intel_crtc
->plane
;
2622 intel_prepare_page_flip(dev
, plane
);
2623 intel_finish_page_flip_plane(dev
, plane
);
2626 for_each_crtc(dev
, crtc
) {
2627 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2629 drm_modeset_lock(&crtc
->mutex
, NULL
);
2631 * FIXME: Once we have proper support for primary planes (and
2632 * disabling them without disabling the entire crtc) allow again
2633 * a NULL crtc->primary->fb.
2635 if (intel_crtc
->active
&& crtc
->primary
->fb
)
2636 dev_priv
->display
.update_primary_plane(crtc
,
2640 drm_modeset_unlock(&crtc
->mutex
);
2645 intel_finish_fb(struct drm_framebuffer
*old_fb
)
2647 struct drm_i915_gem_object
*obj
= intel_fb_obj(old_fb
);
2648 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2649 bool was_interruptible
= dev_priv
->mm
.interruptible
;
2652 /* Big Hammer, we also need to ensure that any pending
2653 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2654 * current scanout is retired before unpinning the old
2657 * This should only fail upon a hung GPU, in which case we
2658 * can safely continue.
2660 dev_priv
->mm
.interruptible
= false;
2661 ret
= i915_gem_object_finish_gpu(obj
);
2662 dev_priv
->mm
.interruptible
= was_interruptible
;
2667 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
2669 struct drm_device
*dev
= crtc
->dev
;
2670 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2671 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2672 unsigned long flags
;
2675 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
2676 intel_crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
2679 spin_lock_irqsave(&dev
->event_lock
, flags
);
2680 pending
= to_intel_crtc(crtc
)->unpin_work
!= NULL
;
2681 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
2687 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2688 struct drm_framebuffer
*fb
)
2690 struct drm_device
*dev
= crtc
->dev
;
2691 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2692 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2693 enum pipe pipe
= intel_crtc
->pipe
;
2694 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
2695 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2696 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(old_fb
);
2699 if (intel_crtc_has_pending_flip(crtc
)) {
2700 DRM_ERROR("pipe is still busy with an old pageflip\n");
2706 DRM_ERROR("No FB bound\n");
2710 if (intel_crtc
->plane
> INTEL_INFO(dev
)->num_pipes
) {
2711 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2712 plane_name(intel_crtc
->plane
),
2713 INTEL_INFO(dev
)->num_pipes
);
2717 mutex_lock(&dev
->struct_mutex
);
2718 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, NULL
);
2720 i915_gem_track_fb(old_obj
, obj
,
2721 INTEL_FRONTBUFFER_PRIMARY(pipe
));
2722 mutex_unlock(&dev
->struct_mutex
);
2724 DRM_ERROR("pin & fence failed\n");
2729 * Update pipe size and adjust fitter if needed: the reason for this is
2730 * that in compute_mode_changes we check the native mode (not the pfit
2731 * mode) to see if we can flip rather than do a full mode set. In the
2732 * fastboot case, we'll flip, but if we don't update the pipesrc and
2733 * pfit state, we'll end up with a big fb scanned out into the wrong
2736 * To fix this properly, we need to hoist the checks up into
2737 * compute_mode_changes (or above), check the actual pfit state and
2738 * whether the platform allows pfit disable with pipe active, and only
2739 * then update the pipesrc and pfit state, even on the flip path.
2741 if (i915
.fastboot
) {
2742 const struct drm_display_mode
*adjusted_mode
=
2743 &intel_crtc
->config
.adjusted_mode
;
2745 I915_WRITE(PIPESRC(intel_crtc
->pipe
),
2746 ((adjusted_mode
->crtc_hdisplay
- 1) << 16) |
2747 (adjusted_mode
->crtc_vdisplay
- 1));
2748 if (!intel_crtc
->config
.pch_pfit
.enabled
&&
2749 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) ||
2750 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
2751 I915_WRITE(PF_CTL(intel_crtc
->pipe
), 0);
2752 I915_WRITE(PF_WIN_POS(intel_crtc
->pipe
), 0);
2753 I915_WRITE(PF_WIN_SZ(intel_crtc
->pipe
), 0);
2755 intel_crtc
->config
.pipe_src_w
= adjusted_mode
->crtc_hdisplay
;
2756 intel_crtc
->config
.pipe_src_h
= adjusted_mode
->crtc_vdisplay
;
2759 dev_priv
->display
.update_primary_plane(crtc
, fb
, x
, y
);
2761 if (intel_crtc
->active
)
2762 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
2764 crtc
->primary
->fb
= fb
;
2769 if (intel_crtc
->active
&& old_fb
!= fb
)
2770 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2771 mutex_lock(&dev
->struct_mutex
);
2772 intel_unpin_fb_obj(old_obj
);
2773 mutex_unlock(&dev
->struct_mutex
);
2776 mutex_lock(&dev
->struct_mutex
);
2777 intel_update_fbc(dev
);
2778 mutex_unlock(&dev
->struct_mutex
);
2783 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
2785 struct drm_device
*dev
= crtc
->dev
;
2786 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2787 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2788 int pipe
= intel_crtc
->pipe
;
2791 /* enable normal train */
2792 reg
= FDI_TX_CTL(pipe
);
2793 temp
= I915_READ(reg
);
2794 if (IS_IVYBRIDGE(dev
)) {
2795 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2796 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2798 temp
&= ~FDI_LINK_TRAIN_NONE
;
2799 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2801 I915_WRITE(reg
, temp
);
2803 reg
= FDI_RX_CTL(pipe
);
2804 temp
= I915_READ(reg
);
2805 if (HAS_PCH_CPT(dev
)) {
2806 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2807 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
2809 temp
&= ~FDI_LINK_TRAIN_NONE
;
2810 temp
|= FDI_LINK_TRAIN_NONE
;
2812 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
2814 /* wait one idle pattern time */
2818 /* IVB wants error correction enabled */
2819 if (IS_IVYBRIDGE(dev
))
2820 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
2821 FDI_FE_ERRC_ENABLE
);
2824 static bool pipe_has_enabled_pch(struct intel_crtc
*crtc
)
2826 return crtc
->base
.enabled
&& crtc
->active
&&
2827 crtc
->config
.has_pch_encoder
;
2830 static void ivb_modeset_global_resources(struct drm_device
*dev
)
2832 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2833 struct intel_crtc
*pipe_B_crtc
=
2834 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
2835 struct intel_crtc
*pipe_C_crtc
=
2836 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]);
2840 * When everything is off disable fdi C so that we could enable fdi B
2841 * with all lanes. Note that we don't care about enabled pipes without
2842 * an enabled pch encoder.
2844 if (!pipe_has_enabled_pch(pipe_B_crtc
) &&
2845 !pipe_has_enabled_pch(pipe_C_crtc
)) {
2846 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
2847 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
2849 temp
= I915_READ(SOUTH_CHICKEN1
);
2850 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
2851 DRM_DEBUG_KMS("disabling fdi C rx\n");
2852 I915_WRITE(SOUTH_CHICKEN1
, temp
);
2856 /* The FDI link training functions for ILK/Ibexpeak. */
2857 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
2859 struct drm_device
*dev
= crtc
->dev
;
2860 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2861 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2862 int pipe
= intel_crtc
->pipe
;
2863 u32 reg
, temp
, tries
;
2865 /* FDI needs bits from pipe first */
2866 assert_pipe_enabled(dev_priv
, pipe
);
2868 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2870 reg
= FDI_RX_IMR(pipe
);
2871 temp
= I915_READ(reg
);
2872 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2873 temp
&= ~FDI_RX_BIT_LOCK
;
2874 I915_WRITE(reg
, temp
);
2878 /* enable CPU FDI TX and PCH FDI RX */
2879 reg
= FDI_TX_CTL(pipe
);
2880 temp
= I915_READ(reg
);
2881 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
2882 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2883 temp
&= ~FDI_LINK_TRAIN_NONE
;
2884 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2885 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2887 reg
= FDI_RX_CTL(pipe
);
2888 temp
= I915_READ(reg
);
2889 temp
&= ~FDI_LINK_TRAIN_NONE
;
2890 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2891 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2896 /* Ironlake workaround, enable clock pointer after FDI enable*/
2897 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2898 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
2899 FDI_RX_PHASE_SYNC_POINTER_EN
);
2901 reg
= FDI_RX_IIR(pipe
);
2902 for (tries
= 0; tries
< 5; tries
++) {
2903 temp
= I915_READ(reg
);
2904 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2906 if ((temp
& FDI_RX_BIT_LOCK
)) {
2907 DRM_DEBUG_KMS("FDI train 1 done.\n");
2908 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2913 DRM_ERROR("FDI train 1 fail!\n");
2916 reg
= FDI_TX_CTL(pipe
);
2917 temp
= I915_READ(reg
);
2918 temp
&= ~FDI_LINK_TRAIN_NONE
;
2919 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2920 I915_WRITE(reg
, temp
);
2922 reg
= FDI_RX_CTL(pipe
);
2923 temp
= I915_READ(reg
);
2924 temp
&= ~FDI_LINK_TRAIN_NONE
;
2925 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2926 I915_WRITE(reg
, temp
);
2931 reg
= FDI_RX_IIR(pipe
);
2932 for (tries
= 0; tries
< 5; tries
++) {
2933 temp
= I915_READ(reg
);
2934 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2936 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2937 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2938 DRM_DEBUG_KMS("FDI train 2 done.\n");
2943 DRM_ERROR("FDI train 2 fail!\n");
2945 DRM_DEBUG_KMS("FDI train done\n");
2949 static const int snb_b_fdi_train_param
[] = {
2950 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
2951 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
2952 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
2953 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
2956 /* The FDI link training functions for SNB/Cougarpoint. */
2957 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
2959 struct drm_device
*dev
= crtc
->dev
;
2960 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2961 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2962 int pipe
= intel_crtc
->pipe
;
2963 u32 reg
, temp
, i
, retry
;
2965 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2967 reg
= FDI_RX_IMR(pipe
);
2968 temp
= I915_READ(reg
);
2969 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2970 temp
&= ~FDI_RX_BIT_LOCK
;
2971 I915_WRITE(reg
, temp
);
2976 /* enable CPU FDI TX and PCH FDI RX */
2977 reg
= FDI_TX_CTL(pipe
);
2978 temp
= I915_READ(reg
);
2979 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
2980 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2981 temp
&= ~FDI_LINK_TRAIN_NONE
;
2982 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2983 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2985 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2986 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2988 I915_WRITE(FDI_RX_MISC(pipe
),
2989 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
2991 reg
= FDI_RX_CTL(pipe
);
2992 temp
= I915_READ(reg
);
2993 if (HAS_PCH_CPT(dev
)) {
2994 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2995 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2997 temp
&= ~FDI_LINK_TRAIN_NONE
;
2998 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3000 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3005 for (i
= 0; i
< 4; i
++) {
3006 reg
= FDI_TX_CTL(pipe
);
3007 temp
= I915_READ(reg
);
3008 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3009 temp
|= snb_b_fdi_train_param
[i
];
3010 I915_WRITE(reg
, temp
);
3015 for (retry
= 0; retry
< 5; retry
++) {
3016 reg
= FDI_RX_IIR(pipe
);
3017 temp
= I915_READ(reg
);
3018 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3019 if (temp
& FDI_RX_BIT_LOCK
) {
3020 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3021 DRM_DEBUG_KMS("FDI train 1 done.\n");
3030 DRM_ERROR("FDI train 1 fail!\n");
3033 reg
= FDI_TX_CTL(pipe
);
3034 temp
= I915_READ(reg
);
3035 temp
&= ~FDI_LINK_TRAIN_NONE
;
3036 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3038 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3040 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3042 I915_WRITE(reg
, temp
);
3044 reg
= FDI_RX_CTL(pipe
);
3045 temp
= I915_READ(reg
);
3046 if (HAS_PCH_CPT(dev
)) {
3047 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3048 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3050 temp
&= ~FDI_LINK_TRAIN_NONE
;
3051 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3053 I915_WRITE(reg
, temp
);
3058 for (i
= 0; i
< 4; i
++) {
3059 reg
= FDI_TX_CTL(pipe
);
3060 temp
= I915_READ(reg
);
3061 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3062 temp
|= snb_b_fdi_train_param
[i
];
3063 I915_WRITE(reg
, temp
);
3068 for (retry
= 0; retry
< 5; retry
++) {
3069 reg
= FDI_RX_IIR(pipe
);
3070 temp
= I915_READ(reg
);
3071 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3072 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3073 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3074 DRM_DEBUG_KMS("FDI train 2 done.\n");
3083 DRM_ERROR("FDI train 2 fail!\n");
3085 DRM_DEBUG_KMS("FDI train done.\n");
3088 /* Manual link training for Ivy Bridge A0 parts */
3089 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
3091 struct drm_device
*dev
= crtc
->dev
;
3092 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3093 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3094 int pipe
= intel_crtc
->pipe
;
3095 u32 reg
, temp
, i
, j
;
3097 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3099 reg
= FDI_RX_IMR(pipe
);
3100 temp
= I915_READ(reg
);
3101 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3102 temp
&= ~FDI_RX_BIT_LOCK
;
3103 I915_WRITE(reg
, temp
);
3108 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3109 I915_READ(FDI_RX_IIR(pipe
)));
3111 /* Try each vswing and preemphasis setting twice before moving on */
3112 for (j
= 0; j
< ARRAY_SIZE(snb_b_fdi_train_param
) * 2; j
++) {
3113 /* disable first in case we need to retry */
3114 reg
= FDI_TX_CTL(pipe
);
3115 temp
= I915_READ(reg
);
3116 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
3117 temp
&= ~FDI_TX_ENABLE
;
3118 I915_WRITE(reg
, temp
);
3120 reg
= FDI_RX_CTL(pipe
);
3121 temp
= I915_READ(reg
);
3122 temp
&= ~FDI_LINK_TRAIN_AUTO
;
3123 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3124 temp
&= ~FDI_RX_ENABLE
;
3125 I915_WRITE(reg
, temp
);
3127 /* enable CPU FDI TX and PCH FDI RX */
3128 reg
= FDI_TX_CTL(pipe
);
3129 temp
= I915_READ(reg
);
3130 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3131 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
3132 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
3133 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3134 temp
|= snb_b_fdi_train_param
[j
/2];
3135 temp
|= FDI_COMPOSITE_SYNC
;
3136 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3138 I915_WRITE(FDI_RX_MISC(pipe
),
3139 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3141 reg
= FDI_RX_CTL(pipe
);
3142 temp
= I915_READ(reg
);
3143 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3144 temp
|= FDI_COMPOSITE_SYNC
;
3145 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3148 udelay(1); /* should be 0.5us */
3150 for (i
= 0; i
< 4; i
++) {
3151 reg
= FDI_RX_IIR(pipe
);
3152 temp
= I915_READ(reg
);
3153 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3155 if (temp
& FDI_RX_BIT_LOCK
||
3156 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
3157 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3158 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3162 udelay(1); /* should be 0.5us */
3165 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j
/ 2);
3170 reg
= FDI_TX_CTL(pipe
);
3171 temp
= I915_READ(reg
);
3172 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3173 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
3174 I915_WRITE(reg
, temp
);
3176 reg
= FDI_RX_CTL(pipe
);
3177 temp
= I915_READ(reg
);
3178 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3179 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3180 I915_WRITE(reg
, temp
);
3183 udelay(2); /* should be 1.5us */
3185 for (i
= 0; i
< 4; i
++) {
3186 reg
= FDI_RX_IIR(pipe
);
3187 temp
= I915_READ(reg
);
3188 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3190 if (temp
& FDI_RX_SYMBOL_LOCK
||
3191 (I915_READ(reg
) & FDI_RX_SYMBOL_LOCK
)) {
3192 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3193 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3197 udelay(2); /* should be 1.5us */
3200 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j
/ 2);
3204 DRM_DEBUG_KMS("FDI train done.\n");
3207 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
3209 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3210 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3211 int pipe
= intel_crtc
->pipe
;
3215 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3216 reg
= FDI_RX_CTL(pipe
);
3217 temp
= I915_READ(reg
);
3218 temp
&= ~(FDI_DP_PORT_WIDTH_MASK
| (0x7 << 16));
3219 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
3220 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3221 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
3226 /* Switch from Rawclk to PCDclk */
3227 temp
= I915_READ(reg
);
3228 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
3233 /* Enable CPU FDI TX PLL, always on for Ironlake */
3234 reg
= FDI_TX_CTL(pipe
);
3235 temp
= I915_READ(reg
);
3236 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
3237 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
3244 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
3246 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3247 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3248 int pipe
= intel_crtc
->pipe
;
3251 /* Switch from PCDclk to Rawclk */
3252 reg
= FDI_RX_CTL(pipe
);
3253 temp
= I915_READ(reg
);
3254 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
3256 /* Disable CPU FDI TX PLL */
3257 reg
= FDI_TX_CTL(pipe
);
3258 temp
= I915_READ(reg
);
3259 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
3264 reg
= FDI_RX_CTL(pipe
);
3265 temp
= I915_READ(reg
);
3266 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
3268 /* Wait for the clocks to turn off. */
3273 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
3275 struct drm_device
*dev
= crtc
->dev
;
3276 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3277 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3278 int pipe
= intel_crtc
->pipe
;
3281 /* disable CPU FDI tx and PCH FDI rx */
3282 reg
= FDI_TX_CTL(pipe
);
3283 temp
= I915_READ(reg
);
3284 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
3287 reg
= FDI_RX_CTL(pipe
);
3288 temp
= I915_READ(reg
);
3289 temp
&= ~(0x7 << 16);
3290 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3291 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
3296 /* Ironlake workaround, disable clock pointer after downing FDI */
3297 if (HAS_PCH_IBX(dev
))
3298 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3300 /* still set train pattern 1 */
3301 reg
= FDI_TX_CTL(pipe
);
3302 temp
= I915_READ(reg
);
3303 temp
&= ~FDI_LINK_TRAIN_NONE
;
3304 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3305 I915_WRITE(reg
, temp
);
3307 reg
= FDI_RX_CTL(pipe
);
3308 temp
= I915_READ(reg
);
3309 if (HAS_PCH_CPT(dev
)) {
3310 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3311 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3313 temp
&= ~FDI_LINK_TRAIN_NONE
;
3314 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3316 /* BPC in FDI rx is consistent with that in PIPECONF */
3317 temp
&= ~(0x07 << 16);
3318 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3319 I915_WRITE(reg
, temp
);
3325 bool intel_has_pending_fb_unpin(struct drm_device
*dev
)
3327 struct intel_crtc
*crtc
;
3329 /* Note that we don't need to be called with mode_config.lock here
3330 * as our list of CRTC objects is static for the lifetime of the
3331 * device and so cannot disappear as we iterate. Similarly, we can
3332 * happily treat the predicates as racy, atomic checks as userspace
3333 * cannot claim and pin a new fb without at least acquring the
3334 * struct_mutex and so serialising with us.
3336 for_each_intel_crtc(dev
, crtc
) {
3337 if (atomic_read(&crtc
->unpin_work_count
) == 0)
3340 if (crtc
->unpin_work
)
3341 intel_wait_for_vblank(dev
, crtc
->pipe
);
3349 void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
3351 struct drm_device
*dev
= crtc
->dev
;
3352 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3354 if (crtc
->primary
->fb
== NULL
)
3357 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
3359 WARN_ON(wait_event_timeout(dev_priv
->pending_flip_queue
,
3360 !intel_crtc_has_pending_flip(crtc
),
3363 mutex_lock(&dev
->struct_mutex
);
3364 intel_finish_fb(crtc
->primary
->fb
);
3365 mutex_unlock(&dev
->struct_mutex
);
3368 /* Program iCLKIP clock to the desired frequency */
3369 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
3371 struct drm_device
*dev
= crtc
->dev
;
3372 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3373 int clock
= to_intel_crtc(crtc
)->config
.adjusted_mode
.crtc_clock
;
3374 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
3377 mutex_lock(&dev_priv
->dpio_lock
);
3379 /* It is necessary to ungate the pixclk gate prior to programming
3380 * the divisors, and gate it back when it is done.
3382 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
3384 /* Disable SSCCTL */
3385 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
3386 intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
) |
3390 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3391 if (clock
== 20000) {
3396 /* The iCLK virtual clock root frequency is in MHz,
3397 * but the adjusted_mode->crtc_clock in in KHz. To get the
3398 * divisors, it is necessary to divide one by another, so we
3399 * convert the virtual clock precision to KHz here for higher
3402 u32 iclk_virtual_root_freq
= 172800 * 1000;
3403 u32 iclk_pi_range
= 64;
3404 u32 desired_divisor
, msb_divisor_value
, pi_value
;
3406 desired_divisor
= (iclk_virtual_root_freq
/ clock
);
3407 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
3408 pi_value
= desired_divisor
% iclk_pi_range
;
3411 divsel
= msb_divisor_value
- 2;
3412 phaseinc
= pi_value
;
3415 /* This should not happen with any sane values */
3416 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
3417 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
3418 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
3419 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
3421 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3428 /* Program SSCDIVINTPHASE6 */
3429 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
3430 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
3431 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
3432 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
3433 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
3434 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
3435 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
3436 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
3438 /* Program SSCAUXDIV */
3439 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
3440 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3441 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
3442 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
3444 /* Enable modulator and associated divider */
3445 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
3446 temp
&= ~SBI_SSCCTL_DISABLE
;
3447 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
3449 /* Wait for initialization time */
3452 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
3454 mutex_unlock(&dev_priv
->dpio_lock
);
3457 static void ironlake_pch_transcoder_set_timings(struct intel_crtc
*crtc
,
3458 enum pipe pch_transcoder
)
3460 struct drm_device
*dev
= crtc
->base
.dev
;
3461 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3462 enum transcoder cpu_transcoder
= crtc
->config
.cpu_transcoder
;
3464 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder
),
3465 I915_READ(HTOTAL(cpu_transcoder
)));
3466 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder
),
3467 I915_READ(HBLANK(cpu_transcoder
)));
3468 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder
),
3469 I915_READ(HSYNC(cpu_transcoder
)));
3471 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder
),
3472 I915_READ(VTOTAL(cpu_transcoder
)));
3473 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder
),
3474 I915_READ(VBLANK(cpu_transcoder
)));
3475 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder
),
3476 I915_READ(VSYNC(cpu_transcoder
)));
3477 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder
),
3478 I915_READ(VSYNCSHIFT(cpu_transcoder
)));
3481 static void cpt_enable_fdi_bc_bifurcation(struct drm_device
*dev
)
3483 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3486 temp
= I915_READ(SOUTH_CHICKEN1
);
3487 if (temp
& FDI_BC_BIFURCATION_SELECT
)
3490 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
3491 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
3493 temp
|= FDI_BC_BIFURCATION_SELECT
;
3494 DRM_DEBUG_KMS("enabling fdi C rx\n");
3495 I915_WRITE(SOUTH_CHICKEN1
, temp
);
3496 POSTING_READ(SOUTH_CHICKEN1
);
3499 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc
*intel_crtc
)
3501 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3502 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3504 switch (intel_crtc
->pipe
) {
3508 if (intel_crtc
->config
.fdi_lanes
> 2)
3509 WARN_ON(I915_READ(SOUTH_CHICKEN1
) & FDI_BC_BIFURCATION_SELECT
);
3511 cpt_enable_fdi_bc_bifurcation(dev
);
3515 cpt_enable_fdi_bc_bifurcation(dev
);
3524 * Enable PCH resources required for PCH ports:
3526 * - FDI training & RX/TX
3527 * - update transcoder timings
3528 * - DP transcoding bits
3531 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
3533 struct drm_device
*dev
= crtc
->dev
;
3534 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3535 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3536 int pipe
= intel_crtc
->pipe
;
3539 assert_pch_transcoder_disabled(dev_priv
, pipe
);
3541 if (IS_IVYBRIDGE(dev
))
3542 ivybridge_update_fdi_bc_bifurcation(intel_crtc
);
3544 /* Write the TU size bits before fdi link training, so that error
3545 * detection works. */
3546 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
3547 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
3549 /* For PCH output, training FDI link */
3550 dev_priv
->display
.fdi_link_train(crtc
);
3552 /* We need to program the right clock selection before writing the pixel
3553 * mutliplier into the DPLL. */
3554 if (HAS_PCH_CPT(dev
)) {
3557 temp
= I915_READ(PCH_DPLL_SEL
);
3558 temp
|= TRANS_DPLL_ENABLE(pipe
);
3559 sel
= TRANS_DPLLB_SEL(pipe
);
3560 if (intel_crtc
->config
.shared_dpll
== DPLL_ID_PCH_PLL_B
)
3564 I915_WRITE(PCH_DPLL_SEL
, temp
);
3567 /* XXX: pch pll's can be enabled any time before we enable the PCH
3568 * transcoder, and we actually should do this to not upset any PCH
3569 * transcoder that already use the clock when we share it.
3571 * Note that enable_shared_dpll tries to do the right thing, but
3572 * get_shared_dpll unconditionally resets the pll - we need that to have
3573 * the right LVDS enable sequence. */
3574 intel_enable_shared_dpll(intel_crtc
);
3576 /* set transcoder timing, panel must allow it */
3577 assert_panel_unlocked(dev_priv
, pipe
);
3578 ironlake_pch_transcoder_set_timings(intel_crtc
, pipe
);
3580 intel_fdi_normal_train(crtc
);
3582 /* For PCH DP, enable TRANS_DP_CTL */
3583 if (HAS_PCH_CPT(dev
) &&
3584 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
3585 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3586 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
3587 reg
= TRANS_DP_CTL(pipe
);
3588 temp
= I915_READ(reg
);
3589 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
3590 TRANS_DP_SYNC_MASK
|
3592 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
3593 TRANS_DP_ENH_FRAMING
);
3594 temp
|= bpc
<< 9; /* same format but at 11:9 */
3596 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
3597 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
3598 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
3599 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
3601 switch (intel_trans_dp_port_sel(crtc
)) {
3603 temp
|= TRANS_DP_PORT_SEL_B
;
3606 temp
|= TRANS_DP_PORT_SEL_C
;
3609 temp
|= TRANS_DP_PORT_SEL_D
;
3615 I915_WRITE(reg
, temp
);
3618 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
3621 static void lpt_pch_enable(struct drm_crtc
*crtc
)
3623 struct drm_device
*dev
= crtc
->dev
;
3624 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3625 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3626 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
3628 assert_pch_transcoder_disabled(dev_priv
, TRANSCODER_A
);
3630 lpt_program_iclkip(crtc
);
3632 /* Set transcoder timing. */
3633 ironlake_pch_transcoder_set_timings(intel_crtc
, PIPE_A
);
3635 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
3638 void intel_put_shared_dpll(struct intel_crtc
*crtc
)
3640 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
3645 if (pll
->refcount
== 0) {
3646 WARN(1, "bad %s refcount\n", pll
->name
);
3650 if (--pll
->refcount
== 0) {
3652 WARN_ON(pll
->active
);
3655 crtc
->config
.shared_dpll
= DPLL_ID_PRIVATE
;
3658 struct intel_shared_dpll
*intel_get_shared_dpll(struct intel_crtc
*crtc
)
3660 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
3661 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
3662 enum intel_dpll_id i
;
3665 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3666 crtc
->base
.base
.id
, pll
->name
);
3667 intel_put_shared_dpll(crtc
);
3670 if (HAS_PCH_IBX(dev_priv
->dev
)) {
3671 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3672 i
= (enum intel_dpll_id
) crtc
->pipe
;
3673 pll
= &dev_priv
->shared_dplls
[i
];
3675 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3676 crtc
->base
.base
.id
, pll
->name
);
3678 WARN_ON(pll
->refcount
);
3683 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3684 pll
= &dev_priv
->shared_dplls
[i
];
3686 /* Only want to check enabled timings first */
3687 if (pll
->refcount
== 0)
3690 if (memcmp(&crtc
->config
.dpll_hw_state
, &pll
->hw_state
,
3691 sizeof(pll
->hw_state
)) == 0) {
3692 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3694 pll
->name
, pll
->refcount
, pll
->active
);
3700 /* Ok no matching timings, maybe there's a free one? */
3701 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3702 pll
= &dev_priv
->shared_dplls
[i
];
3703 if (pll
->refcount
== 0) {
3704 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3705 crtc
->base
.base
.id
, pll
->name
);
3713 if (pll
->refcount
== 0)
3714 pll
->hw_state
= crtc
->config
.dpll_hw_state
;
3716 crtc
->config
.shared_dpll
= i
;
3717 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll
->name
,
3718 pipe_name(crtc
->pipe
));
3725 static void cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
3727 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3728 int dslreg
= PIPEDSL(pipe
);
3731 temp
= I915_READ(dslreg
);
3733 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
3734 if (wait_for(I915_READ(dslreg
) != temp
, 5))
3735 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
3739 static void ironlake_pfit_enable(struct intel_crtc
*crtc
)
3741 struct drm_device
*dev
= crtc
->base
.dev
;
3742 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3743 int pipe
= crtc
->pipe
;
3745 if (crtc
->config
.pch_pfit
.enabled
) {
3746 /* Force use of hard-coded filter coefficients
3747 * as some pre-programmed values are broken,
3750 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
3751 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
3752 PF_PIPE_SEL_IVB(pipe
));
3754 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
3755 I915_WRITE(PF_WIN_POS(pipe
), crtc
->config
.pch_pfit
.pos
);
3756 I915_WRITE(PF_WIN_SZ(pipe
), crtc
->config
.pch_pfit
.size
);
3760 static void intel_enable_planes(struct drm_crtc
*crtc
)
3762 struct drm_device
*dev
= crtc
->dev
;
3763 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
3764 struct drm_plane
*plane
;
3765 struct intel_plane
*intel_plane
;
3767 drm_for_each_legacy_plane(plane
, &dev
->mode_config
.plane_list
) {
3768 intel_plane
= to_intel_plane(plane
);
3769 if (intel_plane
->pipe
== pipe
)
3770 intel_plane_restore(&intel_plane
->base
);
3774 static void intel_disable_planes(struct drm_crtc
*crtc
)
3776 struct drm_device
*dev
= crtc
->dev
;
3777 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
3778 struct drm_plane
*plane
;
3779 struct intel_plane
*intel_plane
;
3781 drm_for_each_legacy_plane(plane
, &dev
->mode_config
.plane_list
) {
3782 intel_plane
= to_intel_plane(plane
);
3783 if (intel_plane
->pipe
== pipe
)
3784 intel_plane_disable(&intel_plane
->base
);
3788 void hsw_enable_ips(struct intel_crtc
*crtc
)
3790 struct drm_device
*dev
= crtc
->base
.dev
;
3791 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3793 if (!crtc
->config
.ips_enabled
)
3796 /* We can only enable IPS after we enable a plane and wait for a vblank */
3797 intel_wait_for_vblank(dev
, crtc
->pipe
);
3799 assert_plane_enabled(dev_priv
, crtc
->plane
);
3800 if (IS_BROADWELL(dev
)) {
3801 mutex_lock(&dev_priv
->rps
.hw_lock
);
3802 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0xc0000000));
3803 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3804 /* Quoting Art Runyan: "its not safe to expect any particular
3805 * value in IPS_CTL bit 31 after enabling IPS through the
3806 * mailbox." Moreover, the mailbox may return a bogus state,
3807 * so we need to just enable it and continue on.
3810 I915_WRITE(IPS_CTL
, IPS_ENABLE
);
3811 /* The bit only becomes 1 in the next vblank, so this wait here
3812 * is essentially intel_wait_for_vblank. If we don't have this
3813 * and don't wait for vblanks until the end of crtc_enable, then
3814 * the HW state readout code will complain that the expected
3815 * IPS_CTL value is not the one we read. */
3816 if (wait_for(I915_READ_NOTRACE(IPS_CTL
) & IPS_ENABLE
, 50))
3817 DRM_ERROR("Timed out waiting for IPS enable\n");
3821 void hsw_disable_ips(struct intel_crtc
*crtc
)
3823 struct drm_device
*dev
= crtc
->base
.dev
;
3824 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3826 if (!crtc
->config
.ips_enabled
)
3829 assert_plane_enabled(dev_priv
, crtc
->plane
);
3830 if (IS_BROADWELL(dev
)) {
3831 mutex_lock(&dev_priv
->rps
.hw_lock
);
3832 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0));
3833 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3834 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3835 if (wait_for((I915_READ(IPS_CTL
) & IPS_ENABLE
) == 0, 42))
3836 DRM_ERROR("Timed out waiting for IPS disable\n");
3838 I915_WRITE(IPS_CTL
, 0);
3839 POSTING_READ(IPS_CTL
);
3842 /* We need to wait for a vblank before we can disable the plane. */
3843 intel_wait_for_vblank(dev
, crtc
->pipe
);
3846 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3847 static void intel_crtc_load_lut(struct drm_crtc
*crtc
)
3849 struct drm_device
*dev
= crtc
->dev
;
3850 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3851 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3852 enum pipe pipe
= intel_crtc
->pipe
;
3853 int palreg
= PALETTE(pipe
);
3855 bool reenable_ips
= false;
3857 /* The clocks have to be on to load the palette. */
3858 if (!crtc
->enabled
|| !intel_crtc
->active
)
3861 if (!HAS_PCH_SPLIT(dev_priv
->dev
)) {
3862 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
))
3863 assert_dsi_pll_enabled(dev_priv
);
3865 assert_pll_enabled(dev_priv
, pipe
);
3868 /* use legacy palette for Ironlake */
3869 if (!HAS_GMCH_DISPLAY(dev
))
3870 palreg
= LGC_PALETTE(pipe
);
3872 /* Workaround : Do not read or write the pipe palette/gamma data while
3873 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3875 if (IS_HASWELL(dev
) && intel_crtc
->config
.ips_enabled
&&
3876 ((I915_READ(GAMMA_MODE(pipe
)) & GAMMA_MODE_MODE_MASK
) ==
3877 GAMMA_MODE_MODE_SPLIT
)) {
3878 hsw_disable_ips(intel_crtc
);
3879 reenable_ips
= true;
3882 for (i
= 0; i
< 256; i
++) {
3883 I915_WRITE(palreg
+ 4 * i
,
3884 (intel_crtc
->lut_r
[i
] << 16) |
3885 (intel_crtc
->lut_g
[i
] << 8) |
3886 intel_crtc
->lut_b
[i
]);
3890 hsw_enable_ips(intel_crtc
);
3893 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
3895 if (!enable
&& intel_crtc
->overlay
) {
3896 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3897 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3899 mutex_lock(&dev
->struct_mutex
);
3900 dev_priv
->mm
.interruptible
= false;
3901 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
3902 dev_priv
->mm
.interruptible
= true;
3903 mutex_unlock(&dev
->struct_mutex
);
3906 /* Let userspace switch the overlay on again. In most cases userspace
3907 * has to recompute where to put it anyway.
3911 static void intel_crtc_enable_planes(struct drm_crtc
*crtc
)
3913 struct drm_device
*dev
= crtc
->dev
;
3914 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3915 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3916 int pipe
= intel_crtc
->pipe
;
3917 int plane
= intel_crtc
->plane
;
3919 drm_vblank_on(dev
, pipe
);
3921 intel_enable_primary_hw_plane(dev_priv
, plane
, pipe
);
3922 intel_enable_planes(crtc
);
3923 intel_crtc_update_cursor(crtc
, true);
3924 intel_crtc_dpms_overlay(intel_crtc
, true);
3926 hsw_enable_ips(intel_crtc
);
3928 mutex_lock(&dev
->struct_mutex
);
3929 intel_update_fbc(dev
);
3930 mutex_unlock(&dev
->struct_mutex
);
3933 * FIXME: Once we grow proper nuclear flip support out of this we need
3934 * to compute the mask of flip planes precisely. For the time being
3935 * consider this a flip from a NULL plane.
3937 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_ALL_MASK(pipe
));
3940 static void intel_crtc_disable_planes(struct drm_crtc
*crtc
)
3942 struct drm_device
*dev
= crtc
->dev
;
3943 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3944 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3945 int pipe
= intel_crtc
->pipe
;
3946 int plane
= intel_crtc
->plane
;
3948 intel_crtc_wait_for_pending_flips(crtc
);
3950 if (dev_priv
->fbc
.plane
== plane
)
3951 intel_disable_fbc(dev
);
3953 hsw_disable_ips(intel_crtc
);
3955 intel_crtc_dpms_overlay(intel_crtc
, false);
3956 intel_crtc_update_cursor(crtc
, false);
3957 intel_disable_planes(crtc
);
3958 intel_disable_primary_hw_plane(dev_priv
, plane
, pipe
);
3961 * FIXME: Once we grow proper nuclear flip support out of this we need
3962 * to compute the mask of flip planes precisely. For the time being
3963 * consider this a flip to a NULL plane.
3965 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_ALL_MASK(pipe
));
3967 drm_vblank_off(dev
, pipe
);
3970 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
3972 struct drm_device
*dev
= crtc
->dev
;
3973 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3974 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3975 struct intel_encoder
*encoder
;
3976 int pipe
= intel_crtc
->pipe
;
3977 enum plane plane
= intel_crtc
->plane
;
3979 WARN_ON(!crtc
->enabled
);
3981 if (intel_crtc
->active
)
3984 if (intel_crtc
->config
.has_pch_encoder
)
3985 intel_prepare_shared_dpll(intel_crtc
);
3987 if (intel_crtc
->config
.has_dp_encoder
)
3988 intel_dp_set_m_n(intel_crtc
);
3990 intel_set_pipe_timings(intel_crtc
);
3992 if (intel_crtc
->config
.has_pch_encoder
) {
3993 intel_cpu_transcoder_set_m_n(intel_crtc
,
3994 &intel_crtc
->config
.fdi_m_n
);
3997 ironlake_set_pipeconf(crtc
);
3999 /* Set up the display plane register */
4000 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
);
4001 POSTING_READ(DSPCNTR(plane
));
4003 dev_priv
->display
.update_primary_plane(crtc
, crtc
->primary
->fb
,
4006 intel_crtc
->active
= true;
4008 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
4009 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, true);
4011 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4012 if (encoder
->pre_enable
)
4013 encoder
->pre_enable(encoder
);
4015 if (intel_crtc
->config
.has_pch_encoder
) {
4016 /* Note: FDI PLL enabling _must_ be done before we enable the
4017 * cpu pipes, hence this is separate from all the other fdi/pch
4019 ironlake_fdi_pll_enable(intel_crtc
);
4021 assert_fdi_tx_disabled(dev_priv
, pipe
);
4022 assert_fdi_rx_disabled(dev_priv
, pipe
);
4025 ironlake_pfit_enable(intel_crtc
);
4028 * On ILK+ LUT must be loaded before the pipe is running but with
4031 intel_crtc_load_lut(crtc
);
4033 intel_update_watermarks(crtc
);
4034 intel_enable_pipe(intel_crtc
);
4036 if (intel_crtc
->config
.has_pch_encoder
)
4037 ironlake_pch_enable(crtc
);
4039 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4040 encoder
->enable(encoder
);
4042 if (HAS_PCH_CPT(dev
))
4043 cpt_verify_modeset(dev
, intel_crtc
->pipe
);
4045 intel_crtc_enable_planes(crtc
);
4048 /* IPS only exists on ULT machines and is tied to pipe A. */
4049 static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc
)
4051 return HAS_IPS(crtc
->base
.dev
) && crtc
->pipe
== PIPE_A
;
4055 * This implements the workaround described in the "notes" section of the mode
4056 * set sequence documentation. When going from no pipes or single pipe to
4057 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4058 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4060 static void haswell_mode_set_planes_workaround(struct intel_crtc
*crtc
)
4062 struct drm_device
*dev
= crtc
->base
.dev
;
4063 struct intel_crtc
*crtc_it
, *other_active_crtc
= NULL
;
4065 /* We want to get the other_active_crtc only if there's only 1 other
4067 for_each_intel_crtc(dev
, crtc_it
) {
4068 if (!crtc_it
->active
|| crtc_it
== crtc
)
4071 if (other_active_crtc
)
4074 other_active_crtc
= crtc_it
;
4076 if (!other_active_crtc
)
4079 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
4080 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
4083 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
4085 struct drm_device
*dev
= crtc
->dev
;
4086 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4087 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4088 struct intel_encoder
*encoder
;
4089 int pipe
= intel_crtc
->pipe
;
4090 enum plane plane
= intel_crtc
->plane
;
4092 WARN_ON(!crtc
->enabled
);
4094 if (intel_crtc
->active
)
4097 if (intel_crtc_to_shared_dpll(intel_crtc
))
4098 intel_enable_shared_dpll(intel_crtc
);
4100 if (intel_crtc
->config
.has_dp_encoder
)
4101 intel_dp_set_m_n(intel_crtc
);
4103 intel_set_pipe_timings(intel_crtc
);
4105 if (intel_crtc
->config
.has_pch_encoder
) {
4106 intel_cpu_transcoder_set_m_n(intel_crtc
,
4107 &intel_crtc
->config
.fdi_m_n
);
4110 haswell_set_pipeconf(crtc
);
4112 intel_set_pipe_csc(crtc
);
4114 /* Set up the display plane register */
4115 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
| DISPPLANE_PIPE_CSC_ENABLE
);
4116 POSTING_READ(DSPCNTR(plane
));
4118 dev_priv
->display
.update_primary_plane(crtc
, crtc
->primary
->fb
,
4121 intel_crtc
->active
= true;
4123 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
4124 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4125 if (encoder
->pre_enable
)
4126 encoder
->pre_enable(encoder
);
4128 if (intel_crtc
->config
.has_pch_encoder
) {
4129 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, true);
4130 dev_priv
->display
.fdi_link_train(crtc
);
4133 intel_ddi_enable_pipe_clock(intel_crtc
);
4135 ironlake_pfit_enable(intel_crtc
);
4138 * On ILK+ LUT must be loaded before the pipe is running but with
4141 intel_crtc_load_lut(crtc
);
4143 intel_ddi_set_pipe_settings(crtc
);
4144 intel_ddi_enable_transcoder_func(crtc
);
4146 intel_update_watermarks(crtc
);
4147 intel_enable_pipe(intel_crtc
);
4149 if (intel_crtc
->config
.has_pch_encoder
)
4150 lpt_pch_enable(crtc
);
4152 if (intel_crtc
->config
.dp_encoder_is_mst
)
4153 intel_ddi_set_vc_payload_alloc(crtc
, true);
4155 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4156 encoder
->enable(encoder
);
4157 intel_opregion_notify_encoder(encoder
, true);
4160 /* If we change the relative order between pipe/planes enabling, we need
4161 * to change the workaround. */
4162 haswell_mode_set_planes_workaround(intel_crtc
);
4163 intel_crtc_enable_planes(crtc
);
4166 static void ironlake_pfit_disable(struct intel_crtc
*crtc
)
4168 struct drm_device
*dev
= crtc
->base
.dev
;
4169 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4170 int pipe
= crtc
->pipe
;
4172 /* To avoid upsetting the power well on haswell only disable the pfit if
4173 * it's in use. The hw state code will make sure we get this right. */
4174 if (crtc
->config
.pch_pfit
.enabled
) {
4175 I915_WRITE(PF_CTL(pipe
), 0);
4176 I915_WRITE(PF_WIN_POS(pipe
), 0);
4177 I915_WRITE(PF_WIN_SZ(pipe
), 0);
4181 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
4183 struct drm_device
*dev
= crtc
->dev
;
4184 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4185 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4186 struct intel_encoder
*encoder
;
4187 int pipe
= intel_crtc
->pipe
;
4190 if (!intel_crtc
->active
)
4193 intel_crtc_disable_planes(crtc
);
4195 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4196 encoder
->disable(encoder
);
4198 if (intel_crtc
->config
.has_pch_encoder
)
4199 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, false);
4201 intel_disable_pipe(dev_priv
, pipe
);
4202 ironlake_pfit_disable(intel_crtc
);
4204 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4205 if (encoder
->post_disable
)
4206 encoder
->post_disable(encoder
);
4208 if (intel_crtc
->config
.has_pch_encoder
) {
4209 ironlake_fdi_disable(crtc
);
4211 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
4212 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, true);
4214 if (HAS_PCH_CPT(dev
)) {
4215 /* disable TRANS_DP_CTL */
4216 reg
= TRANS_DP_CTL(pipe
);
4217 temp
= I915_READ(reg
);
4218 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
|
4219 TRANS_DP_PORT_SEL_MASK
);
4220 temp
|= TRANS_DP_PORT_SEL_NONE
;
4221 I915_WRITE(reg
, temp
);
4223 /* disable DPLL_SEL */
4224 temp
= I915_READ(PCH_DPLL_SEL
);
4225 temp
&= ~(TRANS_DPLL_ENABLE(pipe
) | TRANS_DPLLB_SEL(pipe
));
4226 I915_WRITE(PCH_DPLL_SEL
, temp
);
4229 /* disable PCH DPLL */
4230 intel_disable_shared_dpll(intel_crtc
);
4232 ironlake_fdi_pll_disable(intel_crtc
);
4235 intel_crtc
->active
= false;
4236 intel_update_watermarks(crtc
);
4238 mutex_lock(&dev
->struct_mutex
);
4239 intel_update_fbc(dev
);
4240 mutex_unlock(&dev
->struct_mutex
);
4243 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
4245 struct drm_device
*dev
= crtc
->dev
;
4246 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4247 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4248 struct intel_encoder
*encoder
;
4249 int pipe
= intel_crtc
->pipe
;
4250 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
4252 if (!intel_crtc
->active
)
4255 intel_crtc_disable_planes(crtc
);
4257 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4258 intel_opregion_notify_encoder(encoder
, false);
4259 encoder
->disable(encoder
);
4262 if (intel_crtc
->config
.has_pch_encoder
)
4263 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, false);
4264 intel_disable_pipe(dev_priv
, pipe
);
4266 if (intel_crtc
->config
.dp_encoder_is_mst
)
4267 intel_ddi_set_vc_payload_alloc(crtc
, false);
4269 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
4271 ironlake_pfit_disable(intel_crtc
);
4273 intel_ddi_disable_pipe_clock(intel_crtc
);
4275 if (intel_crtc
->config
.has_pch_encoder
) {
4276 lpt_disable_pch_transcoder(dev_priv
);
4277 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, true);
4278 intel_ddi_fdi_disable(crtc
);
4281 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4282 if (encoder
->post_disable
)
4283 encoder
->post_disable(encoder
);
4285 intel_crtc
->active
= false;
4286 intel_update_watermarks(crtc
);
4288 mutex_lock(&dev
->struct_mutex
);
4289 intel_update_fbc(dev
);
4290 mutex_unlock(&dev
->struct_mutex
);
4292 if (intel_crtc_to_shared_dpll(intel_crtc
))
4293 intel_disable_shared_dpll(intel_crtc
);
4296 static void ironlake_crtc_off(struct drm_crtc
*crtc
)
4298 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4299 intel_put_shared_dpll(intel_crtc
);
4303 static void i9xx_pfit_enable(struct intel_crtc
*crtc
)
4305 struct drm_device
*dev
= crtc
->base
.dev
;
4306 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4307 struct intel_crtc_config
*pipe_config
= &crtc
->config
;
4309 if (!crtc
->config
.gmch_pfit
.control
)
4313 * The panel fitter should only be adjusted whilst the pipe is disabled,
4314 * according to register description and PRM.
4316 WARN_ON(I915_READ(PFIT_CONTROL
) & PFIT_ENABLE
);
4317 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
4319 I915_WRITE(PFIT_PGM_RATIOS
, pipe_config
->gmch_pfit
.pgm_ratios
);
4320 I915_WRITE(PFIT_CONTROL
, pipe_config
->gmch_pfit
.control
);
4322 /* Border color in case we don't scale up to the full screen. Black by
4323 * default, change to something else for debugging. */
4324 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
4327 static enum intel_display_power_domain
port_to_power_domain(enum port port
)
4331 return POWER_DOMAIN_PORT_DDI_A_4_LANES
;
4333 return POWER_DOMAIN_PORT_DDI_B_4_LANES
;
4335 return POWER_DOMAIN_PORT_DDI_C_4_LANES
;
4337 return POWER_DOMAIN_PORT_DDI_D_4_LANES
;
4340 return POWER_DOMAIN_PORT_OTHER
;
4344 #define for_each_power_domain(domain, mask) \
4345 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4346 if ((1 << (domain)) & (mask))
4348 enum intel_display_power_domain
4349 intel_display_port_power_domain(struct intel_encoder
*intel_encoder
)
4351 struct drm_device
*dev
= intel_encoder
->base
.dev
;
4352 struct intel_digital_port
*intel_dig_port
;
4354 switch (intel_encoder
->type
) {
4355 case INTEL_OUTPUT_UNKNOWN
:
4356 /* Only DDI platforms should ever use this output type */
4357 WARN_ON_ONCE(!HAS_DDI(dev
));
4358 case INTEL_OUTPUT_DISPLAYPORT
:
4359 case INTEL_OUTPUT_HDMI
:
4360 case INTEL_OUTPUT_EDP
:
4361 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
4362 return port_to_power_domain(intel_dig_port
->port
);
4363 case INTEL_OUTPUT_DP_MST
:
4364 intel_dig_port
= enc_to_mst(&intel_encoder
->base
)->primary
;
4365 return port_to_power_domain(intel_dig_port
->port
);
4366 case INTEL_OUTPUT_ANALOG
:
4367 return POWER_DOMAIN_PORT_CRT
;
4368 case INTEL_OUTPUT_DSI
:
4369 return POWER_DOMAIN_PORT_DSI
;
4371 return POWER_DOMAIN_PORT_OTHER
;
4375 static unsigned long get_crtc_power_domains(struct drm_crtc
*crtc
)
4377 struct drm_device
*dev
= crtc
->dev
;
4378 struct intel_encoder
*intel_encoder
;
4379 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4380 enum pipe pipe
= intel_crtc
->pipe
;
4382 enum transcoder transcoder
;
4384 transcoder
= intel_pipe_to_cpu_transcoder(dev
->dev_private
, pipe
);
4386 mask
= BIT(POWER_DOMAIN_PIPE(pipe
));
4387 mask
|= BIT(POWER_DOMAIN_TRANSCODER(transcoder
));
4388 if (intel_crtc
->config
.pch_pfit
.enabled
||
4389 intel_crtc
->config
.pch_pfit
.force_thru
)
4390 mask
|= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe
));
4392 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
4393 mask
|= BIT(intel_display_port_power_domain(intel_encoder
));
4398 void intel_display_set_init_power(struct drm_i915_private
*dev_priv
,
4401 if (dev_priv
->power_domains
.init_power_on
== enable
)
4405 intel_display_power_get(dev_priv
, POWER_DOMAIN_INIT
);
4407 intel_display_power_put(dev_priv
, POWER_DOMAIN_INIT
);
4409 dev_priv
->power_domains
.init_power_on
= enable
;
4412 static void modeset_update_crtc_power_domains(struct drm_device
*dev
)
4414 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4415 unsigned long pipe_domains
[I915_MAX_PIPES
] = { 0, };
4416 struct intel_crtc
*crtc
;
4419 * First get all needed power domains, then put all unneeded, to avoid
4420 * any unnecessary toggling of the power wells.
4422 for_each_intel_crtc(dev
, crtc
) {
4423 enum intel_display_power_domain domain
;
4425 if (!crtc
->base
.enabled
)
4428 pipe_domains
[crtc
->pipe
] = get_crtc_power_domains(&crtc
->base
);
4430 for_each_power_domain(domain
, pipe_domains
[crtc
->pipe
])
4431 intel_display_power_get(dev_priv
, domain
);
4434 for_each_intel_crtc(dev
, crtc
) {
4435 enum intel_display_power_domain domain
;
4437 for_each_power_domain(domain
, crtc
->enabled_power_domains
)
4438 intel_display_power_put(dev_priv
, domain
);
4440 crtc
->enabled_power_domains
= pipe_domains
[crtc
->pipe
];
4443 intel_display_set_init_power(dev_priv
, false);
4446 /* returns HPLL frequency in kHz */
4447 static int valleyview_get_vco(struct drm_i915_private
*dev_priv
)
4449 int hpll_freq
, vco_freq
[] = { 800, 1600, 2000, 2400 };
4451 /* Obtain SKU information */
4452 mutex_lock(&dev_priv
->dpio_lock
);
4453 hpll_freq
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
) &
4454 CCK_FUSE_HPLL_FREQ_MASK
;
4455 mutex_unlock(&dev_priv
->dpio_lock
);
4457 return vco_freq
[hpll_freq
] * 1000;
4460 static void vlv_update_cdclk(struct drm_device
*dev
)
4462 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4464 dev_priv
->vlv_cdclk_freq
= dev_priv
->display
.get_display_clock_speed(dev
);
4465 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz",
4466 dev_priv
->vlv_cdclk_freq
);
4469 * Program the gmbus_freq based on the cdclk frequency.
4470 * BSpec erroneously claims we should aim for 4MHz, but
4471 * in fact 1MHz is the correct frequency.
4473 I915_WRITE(GMBUSFREQ_VLV
, dev_priv
->vlv_cdclk_freq
);
4476 /* Adjust CDclk dividers to allow high res or save power if possible */
4477 static void valleyview_set_cdclk(struct drm_device
*dev
, int cdclk
)
4479 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4482 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
) != dev_priv
->vlv_cdclk_freq
);
4484 if (cdclk
>= 320000) /* jump to highest voltage for 400MHz too */
4486 else if (cdclk
== 266667)
4491 mutex_lock(&dev_priv
->rps
.hw_lock
);
4492 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
4493 val
&= ~DSPFREQGUAR_MASK
;
4494 val
|= (cmd
<< DSPFREQGUAR_SHIFT
);
4495 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
4496 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
4497 DSPFREQSTAT_MASK
) == (cmd
<< DSPFREQSTAT_SHIFT
),
4499 DRM_ERROR("timed out waiting for CDclk change\n");
4501 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4503 if (cdclk
== 400000) {
4506 vco
= valleyview_get_vco(dev_priv
);
4507 divider
= DIV_ROUND_CLOSEST(vco
<< 1, cdclk
) - 1;
4509 mutex_lock(&dev_priv
->dpio_lock
);
4510 /* adjust cdclk divider */
4511 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
4512 val
&= ~DISPLAY_FREQUENCY_VALUES
;
4514 vlv_cck_write(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
, val
);
4516 if (wait_for((vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
) &
4517 DISPLAY_FREQUENCY_STATUS
) == (divider
<< DISPLAY_FREQUENCY_STATUS_SHIFT
),
4519 DRM_ERROR("timed out waiting for CDclk change\n");
4520 mutex_unlock(&dev_priv
->dpio_lock
);
4523 mutex_lock(&dev_priv
->dpio_lock
);
4524 /* adjust self-refresh exit latency value */
4525 val
= vlv_bunit_read(dev_priv
, BUNIT_REG_BISOC
);
4529 * For high bandwidth configs, we set a higher latency in the bunit
4530 * so that the core display fetch happens in time to avoid underruns.
4532 if (cdclk
== 400000)
4533 val
|= 4500 / 250; /* 4.5 usec */
4535 val
|= 3000 / 250; /* 3.0 usec */
4536 vlv_bunit_write(dev_priv
, BUNIT_REG_BISOC
, val
);
4537 mutex_unlock(&dev_priv
->dpio_lock
);
4539 vlv_update_cdclk(dev
);
4542 static int valleyview_calc_cdclk(struct drm_i915_private
*dev_priv
,
4545 int vco
= valleyview_get_vco(dev_priv
);
4546 int freq_320
= (vco
<< 1) % 320000 != 0 ? 333333 : 320000;
4549 * Really only a few cases to deal with, as only 4 CDclks are supported:
4552 * 320/333MHz (depends on HPLL freq)
4554 * So we check to see whether we're above 90% of the lower bin and
4557 * We seem to get an unstable or solid color picture at 200MHz.
4558 * Not sure what's wrong. For now use 200MHz only when all pipes
4561 if (max_pixclk
> freq_320
*9/10)
4563 else if (max_pixclk
> 266667*9/10)
4565 else if (max_pixclk
> 0)
4571 /* compute the max pixel clock for new configuration */
4572 static int intel_mode_max_pixclk(struct drm_i915_private
*dev_priv
)
4574 struct drm_device
*dev
= dev_priv
->dev
;
4575 struct intel_crtc
*intel_crtc
;
4578 for_each_intel_crtc(dev
, intel_crtc
) {
4579 if (intel_crtc
->new_enabled
)
4580 max_pixclk
= max(max_pixclk
,
4581 intel_crtc
->new_config
->adjusted_mode
.crtc_clock
);
4587 static void valleyview_modeset_global_pipes(struct drm_device
*dev
,
4588 unsigned *prepare_pipes
)
4590 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4591 struct intel_crtc
*intel_crtc
;
4592 int max_pixclk
= intel_mode_max_pixclk(dev_priv
);
4594 if (valleyview_calc_cdclk(dev_priv
, max_pixclk
) ==
4595 dev_priv
->vlv_cdclk_freq
)
4598 /* disable/enable all currently active pipes while we change cdclk */
4599 for_each_intel_crtc(dev
, intel_crtc
)
4600 if (intel_crtc
->base
.enabled
)
4601 *prepare_pipes
|= (1 << intel_crtc
->pipe
);
4604 static void valleyview_modeset_global_resources(struct drm_device
*dev
)
4606 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4607 int max_pixclk
= intel_mode_max_pixclk(dev_priv
);
4608 int req_cdclk
= valleyview_calc_cdclk(dev_priv
, max_pixclk
);
4610 if (req_cdclk
!= dev_priv
->vlv_cdclk_freq
)
4611 valleyview_set_cdclk(dev
, req_cdclk
);
4612 modeset_update_crtc_power_domains(dev
);
4615 static void valleyview_crtc_enable(struct drm_crtc
*crtc
)
4617 struct drm_device
*dev
= crtc
->dev
;
4618 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4619 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4620 struct intel_encoder
*encoder
;
4621 int pipe
= intel_crtc
->pipe
;
4622 int plane
= intel_crtc
->plane
;
4626 WARN_ON(!crtc
->enabled
);
4628 if (intel_crtc
->active
)
4631 is_dsi
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
);
4633 if (!is_dsi
&& !IS_CHERRYVIEW(dev
))
4634 vlv_prepare_pll(intel_crtc
);
4636 /* Set up the display plane register */
4637 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
4639 if (intel_crtc
->config
.has_dp_encoder
)
4640 intel_dp_set_m_n(intel_crtc
);
4642 intel_set_pipe_timings(intel_crtc
);
4644 /* pipesrc and dspsize control the size that is scaled from,
4645 * which should always be the user's requested size.
4647 I915_WRITE(DSPSIZE(plane
),
4648 ((intel_crtc
->config
.pipe_src_h
- 1) << 16) |
4649 (intel_crtc
->config
.pipe_src_w
- 1));
4650 I915_WRITE(DSPPOS(plane
), 0);
4652 i9xx_set_pipeconf(intel_crtc
);
4654 I915_WRITE(DSPCNTR(plane
), dspcntr
);
4655 POSTING_READ(DSPCNTR(plane
));
4657 dev_priv
->display
.update_primary_plane(crtc
, crtc
->primary
->fb
,
4660 intel_crtc
->active
= true;
4662 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
4664 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4665 if (encoder
->pre_pll_enable
)
4666 encoder
->pre_pll_enable(encoder
);
4669 if (IS_CHERRYVIEW(dev
))
4670 chv_enable_pll(intel_crtc
);
4672 vlv_enable_pll(intel_crtc
);
4675 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4676 if (encoder
->pre_enable
)
4677 encoder
->pre_enable(encoder
);
4679 i9xx_pfit_enable(intel_crtc
);
4681 intel_crtc_load_lut(crtc
);
4683 intel_update_watermarks(crtc
);
4684 intel_enable_pipe(intel_crtc
);
4686 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4687 encoder
->enable(encoder
);
4689 intel_crtc_enable_planes(crtc
);
4691 /* Underruns don't raise interrupts, so check manually. */
4692 i9xx_check_fifo_underruns(dev
);
4695 static void i9xx_set_pll_dividers(struct intel_crtc
*crtc
)
4697 struct drm_device
*dev
= crtc
->base
.dev
;
4698 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4700 I915_WRITE(FP0(crtc
->pipe
), crtc
->config
.dpll_hw_state
.fp0
);
4701 I915_WRITE(FP1(crtc
->pipe
), crtc
->config
.dpll_hw_state
.fp1
);
4704 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
4706 struct drm_device
*dev
= crtc
->dev
;
4707 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4708 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4709 struct intel_encoder
*encoder
;
4710 int pipe
= intel_crtc
->pipe
;
4711 int plane
= intel_crtc
->plane
;
4714 WARN_ON(!crtc
->enabled
);
4716 if (intel_crtc
->active
)
4719 i9xx_set_pll_dividers(intel_crtc
);
4721 /* Set up the display plane register */
4722 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
4725 dspcntr
&= ~DISPPLANE_SEL_PIPE_MASK
;
4727 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
4729 if (intel_crtc
->config
.has_dp_encoder
)
4730 intel_dp_set_m_n(intel_crtc
);
4732 intel_set_pipe_timings(intel_crtc
);
4734 /* pipesrc and dspsize control the size that is scaled from,
4735 * which should always be the user's requested size.
4737 I915_WRITE(DSPSIZE(plane
),
4738 ((intel_crtc
->config
.pipe_src_h
- 1) << 16) |
4739 (intel_crtc
->config
.pipe_src_w
- 1));
4740 I915_WRITE(DSPPOS(plane
), 0);
4742 i9xx_set_pipeconf(intel_crtc
);
4744 I915_WRITE(DSPCNTR(plane
), dspcntr
);
4745 POSTING_READ(DSPCNTR(plane
));
4747 dev_priv
->display
.update_primary_plane(crtc
, crtc
->primary
->fb
,
4750 intel_crtc
->active
= true;
4753 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
4755 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4756 if (encoder
->pre_enable
)
4757 encoder
->pre_enable(encoder
);
4759 i9xx_enable_pll(intel_crtc
);
4761 i9xx_pfit_enable(intel_crtc
);
4763 intel_crtc_load_lut(crtc
);
4765 intel_update_watermarks(crtc
);
4766 intel_enable_pipe(intel_crtc
);
4768 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4769 encoder
->enable(encoder
);
4771 intel_crtc_enable_planes(crtc
);
4774 * Gen2 reports pipe underruns whenever all planes are disabled.
4775 * So don't enable underrun reporting before at least some planes
4777 * FIXME: Need to fix the logic to work when we turn off all planes
4778 * but leave the pipe running.
4781 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
4783 /* Underruns don't raise interrupts, so check manually. */
4784 i9xx_check_fifo_underruns(dev
);
4787 static void i9xx_pfit_disable(struct intel_crtc
*crtc
)
4789 struct drm_device
*dev
= crtc
->base
.dev
;
4790 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4792 if (!crtc
->config
.gmch_pfit
.control
)
4795 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
4797 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4798 I915_READ(PFIT_CONTROL
));
4799 I915_WRITE(PFIT_CONTROL
, 0);
4802 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
4804 struct drm_device
*dev
= crtc
->dev
;
4805 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4806 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4807 struct intel_encoder
*encoder
;
4808 int pipe
= intel_crtc
->pipe
;
4810 if (!intel_crtc
->active
)
4814 * Gen2 reports pipe underruns whenever all planes are disabled.
4815 * So diasble underrun reporting before all the planes get disabled.
4816 * FIXME: Need to fix the logic to work when we turn off all planes
4817 * but leave the pipe running.
4820 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, false);
4823 * Vblank time updates from the shadow to live plane control register
4824 * are blocked if the memory self-refresh mode is active at that
4825 * moment. So to make sure the plane gets truly disabled, disable
4826 * first the self-refresh mode. The self-refresh enable bit in turn
4827 * will be checked/applied by the HW only at the next frame start
4828 * event which is after the vblank start event, so we need to have a
4829 * wait-for-vblank between disabling the plane and the pipe.
4831 intel_set_memory_cxsr(dev_priv
, false);
4832 intel_crtc_disable_planes(crtc
);
4834 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4835 encoder
->disable(encoder
);
4838 * On gen2 planes are double buffered but the pipe isn't, so we must
4839 * wait for planes to fully turn off before disabling the pipe.
4840 * We also need to wait on all gmch platforms because of the
4841 * self-refresh mode constraint explained above.
4843 intel_wait_for_vblank(dev
, pipe
);
4845 intel_disable_pipe(dev_priv
, pipe
);
4847 i9xx_pfit_disable(intel_crtc
);
4849 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4850 if (encoder
->post_disable
)
4851 encoder
->post_disable(encoder
);
4853 if (!intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
)) {
4854 if (IS_CHERRYVIEW(dev
))
4855 chv_disable_pll(dev_priv
, pipe
);
4856 else if (IS_VALLEYVIEW(dev
))
4857 vlv_disable_pll(dev_priv
, pipe
);
4859 i9xx_disable_pll(dev_priv
, pipe
);
4863 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, false);
4865 intel_crtc
->active
= false;
4866 intel_update_watermarks(crtc
);
4868 mutex_lock(&dev
->struct_mutex
);
4869 intel_update_fbc(dev
);
4870 mutex_unlock(&dev
->struct_mutex
);
4873 static void i9xx_crtc_off(struct drm_crtc
*crtc
)
4877 static void intel_crtc_update_sarea(struct drm_crtc
*crtc
,
4880 struct drm_device
*dev
= crtc
->dev
;
4881 struct drm_i915_master_private
*master_priv
;
4882 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4883 int pipe
= intel_crtc
->pipe
;
4885 if (!dev
->primary
->master
)
4888 master_priv
= dev
->primary
->master
->driver_priv
;
4889 if (!master_priv
->sarea_priv
)
4894 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
4895 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
4898 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
4899 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
4902 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe
));
4907 /* Master function to enable/disable CRTC and corresponding power wells */
4908 void intel_crtc_control(struct drm_crtc
*crtc
, bool enable
)
4910 struct drm_device
*dev
= crtc
->dev
;
4911 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4912 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4913 enum intel_display_power_domain domain
;
4914 unsigned long domains
;
4917 if (!intel_crtc
->active
) {
4918 domains
= get_crtc_power_domains(crtc
);
4919 for_each_power_domain(domain
, domains
)
4920 intel_display_power_get(dev_priv
, domain
);
4921 intel_crtc
->enabled_power_domains
= domains
;
4923 dev_priv
->display
.crtc_enable(crtc
);
4926 if (intel_crtc
->active
) {
4927 dev_priv
->display
.crtc_disable(crtc
);
4929 domains
= intel_crtc
->enabled_power_domains
;
4930 for_each_power_domain(domain
, domains
)
4931 intel_display_power_put(dev_priv
, domain
);
4932 intel_crtc
->enabled_power_domains
= 0;
4938 * Sets the power management mode of the pipe and plane.
4940 void intel_crtc_update_dpms(struct drm_crtc
*crtc
)
4942 struct drm_device
*dev
= crtc
->dev
;
4943 struct intel_encoder
*intel_encoder
;
4944 bool enable
= false;
4946 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
4947 enable
|= intel_encoder
->connectors_active
;
4949 intel_crtc_control(crtc
, enable
);
4951 intel_crtc_update_sarea(crtc
, enable
);
4954 static void intel_crtc_disable(struct drm_crtc
*crtc
)
4956 struct drm_device
*dev
= crtc
->dev
;
4957 struct drm_connector
*connector
;
4958 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4959 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(crtc
->primary
->fb
);
4960 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
4962 /* crtc should still be enabled when we disable it. */
4963 WARN_ON(!crtc
->enabled
);
4965 dev_priv
->display
.crtc_disable(crtc
);
4966 intel_crtc_update_sarea(crtc
, false);
4967 dev_priv
->display
.off(crtc
);
4969 if (crtc
->primary
->fb
) {
4970 mutex_lock(&dev
->struct_mutex
);
4971 intel_unpin_fb_obj(old_obj
);
4972 i915_gem_track_fb(old_obj
, NULL
,
4973 INTEL_FRONTBUFFER_PRIMARY(pipe
));
4974 mutex_unlock(&dev
->struct_mutex
);
4975 crtc
->primary
->fb
= NULL
;
4978 /* Update computed state. */
4979 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
4980 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
4983 if (connector
->encoder
->crtc
!= crtc
)
4986 connector
->dpms
= DRM_MODE_DPMS_OFF
;
4987 to_intel_encoder(connector
->encoder
)->connectors_active
= false;
4991 void intel_encoder_destroy(struct drm_encoder
*encoder
)
4993 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
4995 drm_encoder_cleanup(encoder
);
4996 kfree(intel_encoder
);
4999 /* Simple dpms helper for encoders with just one connector, no cloning and only
5000 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5001 * state of the entire output pipe. */
5002 static void intel_encoder_dpms(struct intel_encoder
*encoder
, int mode
)
5004 if (mode
== DRM_MODE_DPMS_ON
) {
5005 encoder
->connectors_active
= true;
5007 intel_crtc_update_dpms(encoder
->base
.crtc
);
5009 encoder
->connectors_active
= false;
5011 intel_crtc_update_dpms(encoder
->base
.crtc
);
5015 /* Cross check the actual hw state with our own modeset state tracking (and it's
5016 * internal consistency). */
5017 static void intel_connector_check_state(struct intel_connector
*connector
)
5019 if (connector
->get_hw_state(connector
)) {
5020 struct intel_encoder
*encoder
= connector
->encoder
;
5021 struct drm_crtc
*crtc
;
5022 bool encoder_enabled
;
5025 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5026 connector
->base
.base
.id
,
5027 connector
->base
.name
);
5029 /* there is no real hw state for MST connectors */
5030 if (connector
->mst_port
)
5033 WARN(connector
->base
.dpms
== DRM_MODE_DPMS_OFF
,
5034 "wrong connector dpms state\n");
5035 WARN(connector
->base
.encoder
!= &encoder
->base
,
5036 "active connector not linked to encoder\n");
5039 WARN(!encoder
->connectors_active
,
5040 "encoder->connectors_active not set\n");
5042 encoder_enabled
= encoder
->get_hw_state(encoder
, &pipe
);
5043 WARN(!encoder_enabled
, "encoder not enabled\n");
5044 if (WARN_ON(!encoder
->base
.crtc
))
5047 crtc
= encoder
->base
.crtc
;
5049 WARN(!crtc
->enabled
, "crtc not enabled\n");
5050 WARN(!to_intel_crtc(crtc
)->active
, "crtc not active\n");
5051 WARN(pipe
!= to_intel_crtc(crtc
)->pipe
,
5052 "encoder active on the wrong pipe\n");
5057 /* Even simpler default implementation, if there's really no special case to
5059 void intel_connector_dpms(struct drm_connector
*connector
, int mode
)
5061 /* All the simple cases only support two dpms states. */
5062 if (mode
!= DRM_MODE_DPMS_ON
)
5063 mode
= DRM_MODE_DPMS_OFF
;
5065 if (mode
== connector
->dpms
)
5068 connector
->dpms
= mode
;
5070 /* Only need to change hw state when actually enabled */
5071 if (connector
->encoder
)
5072 intel_encoder_dpms(to_intel_encoder(connector
->encoder
), mode
);
5074 intel_modeset_check_state(connector
->dev
);
5077 /* Simple connector->get_hw_state implementation for encoders that support only
5078 * one connector and no cloning and hence the encoder state determines the state
5079 * of the connector. */
5080 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
5083 struct intel_encoder
*encoder
= connector
->encoder
;
5085 return encoder
->get_hw_state(encoder
, &pipe
);
5088 static bool ironlake_check_fdi_lanes(struct drm_device
*dev
, enum pipe pipe
,
5089 struct intel_crtc_config
*pipe_config
)
5091 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5092 struct intel_crtc
*pipe_B_crtc
=
5093 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
5095 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5096 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5097 if (pipe_config
->fdi_lanes
> 4) {
5098 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5099 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5103 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
5104 if (pipe_config
->fdi_lanes
> 2) {
5105 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5106 pipe_config
->fdi_lanes
);
5113 if (INTEL_INFO(dev
)->num_pipes
== 2)
5116 /* Ivybridge 3 pipe is really complicated */
5121 if (dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]->enabled
&&
5122 pipe_config
->fdi_lanes
> 2) {
5123 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5124 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5129 if (!pipe_has_enabled_pch(pipe_B_crtc
) ||
5130 pipe_B_crtc
->config
.fdi_lanes
<= 2) {
5131 if (pipe_config
->fdi_lanes
> 2) {
5132 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5133 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5137 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5147 static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc
,
5148 struct intel_crtc_config
*pipe_config
)
5150 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5151 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
5152 int lane
, link_bw
, fdi_dotclock
;
5153 bool setup_ok
, needs_recompute
= false;
5156 /* FDI is a binary signal running at ~2.7GHz, encoding
5157 * each output octet as 10 bits. The actual frequency
5158 * is stored as a divider into a 100MHz clock, and the
5159 * mode pixel clock is stored in units of 1KHz.
5160 * Hence the bw of each lane in terms of the mode signal
5163 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
5165 fdi_dotclock
= adjusted_mode
->crtc_clock
;
5167 lane
= ironlake_get_lanes_required(fdi_dotclock
, link_bw
,
5168 pipe_config
->pipe_bpp
);
5170 pipe_config
->fdi_lanes
= lane
;
5172 intel_link_compute_m_n(pipe_config
->pipe_bpp
, lane
, fdi_dotclock
,
5173 link_bw
, &pipe_config
->fdi_m_n
);
5175 setup_ok
= ironlake_check_fdi_lanes(intel_crtc
->base
.dev
,
5176 intel_crtc
->pipe
, pipe_config
);
5177 if (!setup_ok
&& pipe_config
->pipe_bpp
> 6*3) {
5178 pipe_config
->pipe_bpp
-= 2*3;
5179 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5180 pipe_config
->pipe_bpp
);
5181 needs_recompute
= true;
5182 pipe_config
->bw_constrained
= true;
5187 if (needs_recompute
)
5190 return setup_ok
? 0 : -EINVAL
;
5193 static void hsw_compute_ips_config(struct intel_crtc
*crtc
,
5194 struct intel_crtc_config
*pipe_config
)
5196 pipe_config
->ips_enabled
= i915
.enable_ips
&&
5197 hsw_crtc_supports_ips(crtc
) &&
5198 pipe_config
->pipe_bpp
<= 24;
5201 static int intel_crtc_compute_config(struct intel_crtc
*crtc
,
5202 struct intel_crtc_config
*pipe_config
)
5204 struct drm_device
*dev
= crtc
->base
.dev
;
5205 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
5207 /* FIXME should check pixel clock limits on all platforms */
5208 if (INTEL_INFO(dev
)->gen
< 4) {
5209 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5211 dev_priv
->display
.get_display_clock_speed(dev
);
5214 * Enable pixel doubling when the dot clock
5215 * is > 90% of the (display) core speed.
5217 * GDG double wide on either pipe,
5218 * otherwise pipe A only.
5220 if ((crtc
->pipe
== PIPE_A
|| IS_I915G(dev
)) &&
5221 adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10) {
5223 pipe_config
->double_wide
= true;
5226 if (adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10)
5231 * Pipe horizontal size must be even in:
5233 * - LVDS dual channel mode
5234 * - Double wide pipe
5236 if ((intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
5237 intel_is_dual_link_lvds(dev
)) || pipe_config
->double_wide
)
5238 pipe_config
->pipe_src_w
&= ~1;
5240 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5241 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5243 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
5244 adjusted_mode
->hsync_start
== adjusted_mode
->hdisplay
)
5247 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) && pipe_config
->pipe_bpp
> 10*3) {
5248 pipe_config
->pipe_bpp
= 10*3; /* 12bpc is gen5+ */
5249 } else if (INTEL_INFO(dev
)->gen
<= 4 && pipe_config
->pipe_bpp
> 8*3) {
5250 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5252 pipe_config
->pipe_bpp
= 8*3;
5256 hsw_compute_ips_config(crtc
, pipe_config
);
5259 * XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the
5260 * old clock survives for now.
5262 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
) || HAS_DDI(dev
))
5263 pipe_config
->shared_dpll
= crtc
->config
.shared_dpll
;
5265 if (pipe_config
->has_pch_encoder
)
5266 return ironlake_fdi_compute_config(crtc
, pipe_config
);
5271 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
5273 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5274 int vco
= valleyview_get_vco(dev_priv
);
5278 mutex_lock(&dev_priv
->dpio_lock
);
5279 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
5280 mutex_unlock(&dev_priv
->dpio_lock
);
5282 divider
= val
& DISPLAY_FREQUENCY_VALUES
;
5284 WARN((val
& DISPLAY_FREQUENCY_STATUS
) !=
5285 (divider
<< DISPLAY_FREQUENCY_STATUS_SHIFT
),
5286 "cdclk change in progress\n");
5288 return DIV_ROUND_CLOSEST(vco
<< 1, divider
+ 1);
5291 static int i945_get_display_clock_speed(struct drm_device
*dev
)
5296 static int i915_get_display_clock_speed(struct drm_device
*dev
)
5301 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
5306 static int pnv_get_display_clock_speed(struct drm_device
*dev
)
5310 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
5312 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
5313 case GC_DISPLAY_CLOCK_267_MHZ_PNV
:
5315 case GC_DISPLAY_CLOCK_333_MHZ_PNV
:
5317 case GC_DISPLAY_CLOCK_444_MHZ_PNV
:
5319 case GC_DISPLAY_CLOCK_200_MHZ_PNV
:
5322 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc
);
5323 case GC_DISPLAY_CLOCK_133_MHZ_PNV
:
5325 case GC_DISPLAY_CLOCK_167_MHZ_PNV
:
5330 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
5334 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
5336 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
5339 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
5340 case GC_DISPLAY_CLOCK_333_MHZ
:
5343 case GC_DISPLAY_CLOCK_190_200_MHZ
:
5349 static int i865_get_display_clock_speed(struct drm_device
*dev
)
5354 static int i855_get_display_clock_speed(struct drm_device
*dev
)
5357 /* Assume that the hardware is in the high speed state. This
5358 * should be the default.
5360 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
5361 case GC_CLOCK_133_200
:
5362 case GC_CLOCK_100_200
:
5364 case GC_CLOCK_166_250
:
5366 case GC_CLOCK_100_133
:
5370 /* Shouldn't happen */
5374 static int i830_get_display_clock_speed(struct drm_device
*dev
)
5380 intel_reduce_m_n_ratio(uint32_t *num
, uint32_t *den
)
5382 while (*num
> DATA_LINK_M_N_MASK
||
5383 *den
> DATA_LINK_M_N_MASK
) {
5389 static void compute_m_n(unsigned int m
, unsigned int n
,
5390 uint32_t *ret_m
, uint32_t *ret_n
)
5392 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
5393 *ret_m
= div_u64((uint64_t) m
* *ret_n
, n
);
5394 intel_reduce_m_n_ratio(ret_m
, ret_n
);
5398 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
5399 int pixel_clock
, int link_clock
,
5400 struct intel_link_m_n
*m_n
)
5404 compute_m_n(bits_per_pixel
* pixel_clock
,
5405 link_clock
* nlanes
* 8,
5406 &m_n
->gmch_m
, &m_n
->gmch_n
);
5408 compute_m_n(pixel_clock
, link_clock
,
5409 &m_n
->link_m
, &m_n
->link_n
);
5412 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
5414 if (i915
.panel_use_ssc
>= 0)
5415 return i915
.panel_use_ssc
!= 0;
5416 return dev_priv
->vbt
.lvds_use_ssc
5417 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
5420 static int i9xx_get_refclk(struct drm_crtc
*crtc
, int num_connectors
)
5422 struct drm_device
*dev
= crtc
->dev
;
5423 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5426 if (IS_VALLEYVIEW(dev
)) {
5428 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
5429 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
5430 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
5431 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
5432 } else if (!IS_GEN2(dev
)) {
5441 static uint32_t pnv_dpll_compute_fp(struct dpll
*dpll
)
5443 return (1 << dpll
->n
) << 16 | dpll
->m2
;
5446 static uint32_t i9xx_dpll_compute_fp(struct dpll
*dpll
)
5448 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
5451 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
5452 intel_clock_t
*reduced_clock
)
5454 struct drm_device
*dev
= crtc
->base
.dev
;
5457 if (IS_PINEVIEW(dev
)) {
5458 fp
= pnv_dpll_compute_fp(&crtc
->config
.dpll
);
5460 fp2
= pnv_dpll_compute_fp(reduced_clock
);
5462 fp
= i9xx_dpll_compute_fp(&crtc
->config
.dpll
);
5464 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
5467 crtc
->config
.dpll_hw_state
.fp0
= fp
;
5469 crtc
->lowfreq_avail
= false;
5470 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
5471 reduced_clock
&& i915
.powersave
) {
5472 crtc
->config
.dpll_hw_state
.fp1
= fp2
;
5473 crtc
->lowfreq_avail
= true;
5475 crtc
->config
.dpll_hw_state
.fp1
= fp
;
5479 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
, enum pipe
5485 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5486 * and set it to a reasonable value instead.
5488 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
5489 reg_val
&= 0xffffff00;
5490 reg_val
|= 0x00000030;
5491 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
5493 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
5494 reg_val
&= 0x8cffffff;
5495 reg_val
= 0x8c000000;
5496 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
5498 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
5499 reg_val
&= 0xffffff00;
5500 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
5502 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
5503 reg_val
&= 0x00ffffff;
5504 reg_val
|= 0xb0000000;
5505 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
5508 static void intel_pch_transcoder_set_m_n(struct intel_crtc
*crtc
,
5509 struct intel_link_m_n
*m_n
)
5511 struct drm_device
*dev
= crtc
->base
.dev
;
5512 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5513 int pipe
= crtc
->pipe
;
5515 I915_WRITE(PCH_TRANS_DATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5516 I915_WRITE(PCH_TRANS_DATA_N1(pipe
), m_n
->gmch_n
);
5517 I915_WRITE(PCH_TRANS_LINK_M1(pipe
), m_n
->link_m
);
5518 I915_WRITE(PCH_TRANS_LINK_N1(pipe
), m_n
->link_n
);
5521 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
5522 struct intel_link_m_n
*m_n
)
5524 struct drm_device
*dev
= crtc
->base
.dev
;
5525 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5526 int pipe
= crtc
->pipe
;
5527 enum transcoder transcoder
= crtc
->config
.cpu_transcoder
;
5529 if (INTEL_INFO(dev
)->gen
>= 5) {
5530 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5531 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
5532 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
5533 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
5535 I915_WRITE(PIPE_DATA_M_G4X(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5536 I915_WRITE(PIPE_DATA_N_G4X(pipe
), m_n
->gmch_n
);
5537 I915_WRITE(PIPE_LINK_M_G4X(pipe
), m_n
->link_m
);
5538 I915_WRITE(PIPE_LINK_N_G4X(pipe
), m_n
->link_n
);
5542 static void intel_dp_set_m_n(struct intel_crtc
*crtc
)
5544 if (crtc
->config
.has_pch_encoder
)
5545 intel_pch_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
);
5547 intel_cpu_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
);
5550 static void vlv_update_pll(struct intel_crtc
*crtc
)
5555 * Enable DPIO clock input. We should never disable the reference
5556 * clock for pipe B, since VGA hotplug / manual detection depends
5559 dpll
= DPLL_EXT_BUFFER_ENABLE_VLV
| DPLL_REFA_CLK_ENABLE_VLV
|
5560 DPLL_VGA_MODE_DIS
| DPLL_INTEGRATED_CLOCK_VLV
;
5561 /* We should never disable this, set it here for state tracking */
5562 if (crtc
->pipe
== PIPE_B
)
5563 dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
5564 dpll
|= DPLL_VCO_ENABLE
;
5565 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
5567 dpll_md
= (crtc
->config
.pixel_multiplier
- 1)
5568 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
5569 crtc
->config
.dpll_hw_state
.dpll_md
= dpll_md
;
5572 static void vlv_prepare_pll(struct intel_crtc
*crtc
)
5574 struct drm_device
*dev
= crtc
->base
.dev
;
5575 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5576 int pipe
= crtc
->pipe
;
5578 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
5579 u32 coreclk
, reg_val
;
5581 mutex_lock(&dev_priv
->dpio_lock
);
5583 bestn
= crtc
->config
.dpll
.n
;
5584 bestm1
= crtc
->config
.dpll
.m1
;
5585 bestm2
= crtc
->config
.dpll
.m2
;
5586 bestp1
= crtc
->config
.dpll
.p1
;
5587 bestp2
= crtc
->config
.dpll
.p2
;
5589 /* See eDP HDMI DPIO driver vbios notes doc */
5591 /* PLL B needs special handling */
5593 vlv_pllb_recal_opamp(dev_priv
, pipe
);
5595 /* Set up Tx target for periodic Rcomp update */
5596 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9_BCAST
, 0x0100000f);
5598 /* Disable target IRef on PLL */
5599 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW8(pipe
));
5600 reg_val
&= 0x00ffffff;
5601 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW8(pipe
), reg_val
);
5603 /* Disable fast lock */
5604 vlv_dpio_write(dev_priv
, pipe
, VLV_CMN_DW0
, 0x610);
5606 /* Set idtafcrecal before PLL is enabled */
5607 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
5608 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
5609 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
5610 mdiv
|= (1 << DPIO_K_SHIFT
);
5613 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5614 * but we don't support that).
5615 * Note: don't use the DAC post divider as it seems unstable.
5617 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
5618 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
5620 mdiv
|= DPIO_ENABLE_CALIBRATION
;
5621 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
5623 /* Set HBR and RBR LPF coefficients */
5624 if (crtc
->config
.port_clock
== 162000 ||
5625 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_ANALOG
) ||
5626 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
))
5627 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
5630 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
5633 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
) ||
5634 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
)) {
5635 /* Use SSC source */
5637 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5640 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5642 } else { /* HDMI or VGA */
5643 /* Use bend source */
5645 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5648 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5652 coreclk
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW7(pipe
));
5653 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
5654 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
) ||
5655 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
))
5656 coreclk
|= 0x01000000;
5657 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW7(pipe
), coreclk
);
5659 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW11(pipe
), 0x87871000);
5660 mutex_unlock(&dev_priv
->dpio_lock
);
5663 static void chv_update_pll(struct intel_crtc
*crtc
)
5665 struct drm_device
*dev
= crtc
->base
.dev
;
5666 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5667 int pipe
= crtc
->pipe
;
5668 int dpll_reg
= DPLL(crtc
->pipe
);
5669 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
5670 u32 loopfilter
, intcoeff
;
5671 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
, bestm2_frac
;
5674 crtc
->config
.dpll_hw_state
.dpll
= DPLL_SSC_REF_CLOCK_CHV
|
5675 DPLL_REFA_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
|
5678 crtc
->config
.dpll_hw_state
.dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
5680 crtc
->config
.dpll_hw_state
.dpll_md
=
5681 (crtc
->config
.pixel_multiplier
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
5683 bestn
= crtc
->config
.dpll
.n
;
5684 bestm2_frac
= crtc
->config
.dpll
.m2
& 0x3fffff;
5685 bestm1
= crtc
->config
.dpll
.m1
;
5686 bestm2
= crtc
->config
.dpll
.m2
>> 22;
5687 bestp1
= crtc
->config
.dpll
.p1
;
5688 bestp2
= crtc
->config
.dpll
.p2
;
5691 * Enable Refclk and SSC
5693 I915_WRITE(dpll_reg
,
5694 crtc
->config
.dpll_hw_state
.dpll
& ~DPLL_VCO_ENABLE
);
5696 mutex_lock(&dev_priv
->dpio_lock
);
5698 /* p1 and p2 divider */
5699 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW13(port
),
5700 5 << DPIO_CHV_S1_DIV_SHIFT
|
5701 bestp1
<< DPIO_CHV_P1_DIV_SHIFT
|
5702 bestp2
<< DPIO_CHV_P2_DIV_SHIFT
|
5703 1 << DPIO_CHV_K_DIV_SHIFT
);
5705 /* Feedback post-divider - m2 */
5706 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW0(port
), bestm2
);
5708 /* Feedback refclk divider - n and m1 */
5709 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW1(port
),
5710 DPIO_CHV_M1_DIV_BY_2
|
5711 1 << DPIO_CHV_N_DIV_SHIFT
);
5713 /* M2 fraction division */
5714 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW2(port
), bestm2_frac
);
5716 /* M2 fraction division enable */
5717 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW3(port
),
5718 DPIO_CHV_FRAC_DIV_EN
|
5719 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT
));
5722 refclk
= i9xx_get_refclk(&crtc
->base
, 0);
5723 loopfilter
= 5 << DPIO_CHV_PROP_COEFF_SHIFT
|
5724 2 << DPIO_CHV_GAIN_CTRL_SHIFT
;
5725 if (refclk
== 100000)
5727 else if (refclk
== 38400)
5731 loopfilter
|= intcoeff
<< DPIO_CHV_INT_COEFF_SHIFT
;
5732 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW6(port
), loopfilter
);
5735 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
),
5736 vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
)) |
5739 mutex_unlock(&dev_priv
->dpio_lock
);
5742 static void i9xx_update_pll(struct intel_crtc
*crtc
,
5743 intel_clock_t
*reduced_clock
,
5746 struct drm_device
*dev
= crtc
->base
.dev
;
5747 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5750 struct dpll
*clock
= &crtc
->config
.dpll
;
5752 i9xx_update_pll_dividers(crtc
, reduced_clock
);
5754 is_sdvo
= intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_SDVO
) ||
5755 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
);
5757 dpll
= DPLL_VGA_MODE_DIS
;
5759 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
))
5760 dpll
|= DPLLB_MODE_LVDS
;
5762 dpll
|= DPLLB_MODE_DAC_SERIAL
;
5764 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
5765 dpll
|= (crtc
->config
.pixel_multiplier
- 1)
5766 << SDVO_MULTIPLIER_SHIFT_HIRES
;
5770 dpll
|= DPLL_SDVO_HIGH_SPEED
;
5772 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
))
5773 dpll
|= DPLL_SDVO_HIGH_SPEED
;
5775 /* compute bitmask from p1 value */
5776 if (IS_PINEVIEW(dev
))
5777 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
5779 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5780 if (IS_G4X(dev
) && reduced_clock
)
5781 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
5783 switch (clock
->p2
) {
5785 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
5788 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
5791 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
5794 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
5797 if (INTEL_INFO(dev
)->gen
>= 4)
5798 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
5800 if (crtc
->config
.sdvo_tv_clock
)
5801 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
5802 else if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
5803 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
5804 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
5806 dpll
|= PLL_REF_INPUT_DREFCLK
;
5808 dpll
|= DPLL_VCO_ENABLE
;
5809 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
5811 if (INTEL_INFO(dev
)->gen
>= 4) {
5812 u32 dpll_md
= (crtc
->config
.pixel_multiplier
- 1)
5813 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
5814 crtc
->config
.dpll_hw_state
.dpll_md
= dpll_md
;
5818 static void i8xx_update_pll(struct intel_crtc
*crtc
,
5819 intel_clock_t
*reduced_clock
,
5822 struct drm_device
*dev
= crtc
->base
.dev
;
5823 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5825 struct dpll
*clock
= &crtc
->config
.dpll
;
5827 i9xx_update_pll_dividers(crtc
, reduced_clock
);
5829 dpll
= DPLL_VGA_MODE_DIS
;
5831 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
)) {
5832 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5835 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
5837 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5839 dpll
|= PLL_P2_DIVIDE_BY_4
;
5842 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DVO
))
5843 dpll
|= DPLL_DVO_2X_MODE
;
5845 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
5846 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
5847 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
5849 dpll
|= PLL_REF_INPUT_DREFCLK
;
5851 dpll
|= DPLL_VCO_ENABLE
;
5852 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
5855 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
)
5857 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5858 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5859 enum pipe pipe
= intel_crtc
->pipe
;
5860 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
5861 struct drm_display_mode
*adjusted_mode
=
5862 &intel_crtc
->config
.adjusted_mode
;
5863 uint32_t crtc_vtotal
, crtc_vblank_end
;
5866 /* We need to be careful not to changed the adjusted mode, for otherwise
5867 * the hw state checker will get angry at the mismatch. */
5868 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
5869 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
5871 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
5872 /* the chip adds 2 halflines automatically */
5874 crtc_vblank_end
-= 1;
5876 if (intel_pipe_has_type(&intel_crtc
->base
, INTEL_OUTPUT_SDVO
))
5877 vsyncshift
= (adjusted_mode
->crtc_htotal
- 1) / 2;
5879 vsyncshift
= adjusted_mode
->crtc_hsync_start
-
5880 adjusted_mode
->crtc_htotal
/ 2;
5882 vsyncshift
+= adjusted_mode
->crtc_htotal
;
5885 if (INTEL_INFO(dev
)->gen
> 3)
5886 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
5888 I915_WRITE(HTOTAL(cpu_transcoder
),
5889 (adjusted_mode
->crtc_hdisplay
- 1) |
5890 ((adjusted_mode
->crtc_htotal
- 1) << 16));
5891 I915_WRITE(HBLANK(cpu_transcoder
),
5892 (adjusted_mode
->crtc_hblank_start
- 1) |
5893 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
5894 I915_WRITE(HSYNC(cpu_transcoder
),
5895 (adjusted_mode
->crtc_hsync_start
- 1) |
5896 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
5898 I915_WRITE(VTOTAL(cpu_transcoder
),
5899 (adjusted_mode
->crtc_vdisplay
- 1) |
5900 ((crtc_vtotal
- 1) << 16));
5901 I915_WRITE(VBLANK(cpu_transcoder
),
5902 (adjusted_mode
->crtc_vblank_start
- 1) |
5903 ((crtc_vblank_end
- 1) << 16));
5904 I915_WRITE(VSYNC(cpu_transcoder
),
5905 (adjusted_mode
->crtc_vsync_start
- 1) |
5906 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
5908 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5909 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5910 * documented on the DDI_FUNC_CTL register description, EDP Input Select
5912 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
5913 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
5914 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
5916 /* pipesrc controls the size that is scaled from, which should
5917 * always be the user's requested size.
5919 I915_WRITE(PIPESRC(pipe
),
5920 ((intel_crtc
->config
.pipe_src_w
- 1) << 16) |
5921 (intel_crtc
->config
.pipe_src_h
- 1));
5924 static void intel_get_pipe_timings(struct intel_crtc
*crtc
,
5925 struct intel_crtc_config
*pipe_config
)
5927 struct drm_device
*dev
= crtc
->base
.dev
;
5928 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5929 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
5932 tmp
= I915_READ(HTOTAL(cpu_transcoder
));
5933 pipe_config
->adjusted_mode
.crtc_hdisplay
= (tmp
& 0xffff) + 1;
5934 pipe_config
->adjusted_mode
.crtc_htotal
= ((tmp
>> 16) & 0xffff) + 1;
5935 tmp
= I915_READ(HBLANK(cpu_transcoder
));
5936 pipe_config
->adjusted_mode
.crtc_hblank_start
= (tmp
& 0xffff) + 1;
5937 pipe_config
->adjusted_mode
.crtc_hblank_end
= ((tmp
>> 16) & 0xffff) + 1;
5938 tmp
= I915_READ(HSYNC(cpu_transcoder
));
5939 pipe_config
->adjusted_mode
.crtc_hsync_start
= (tmp
& 0xffff) + 1;
5940 pipe_config
->adjusted_mode
.crtc_hsync_end
= ((tmp
>> 16) & 0xffff) + 1;
5942 tmp
= I915_READ(VTOTAL(cpu_transcoder
));
5943 pipe_config
->adjusted_mode
.crtc_vdisplay
= (tmp
& 0xffff) + 1;
5944 pipe_config
->adjusted_mode
.crtc_vtotal
= ((tmp
>> 16) & 0xffff) + 1;
5945 tmp
= I915_READ(VBLANK(cpu_transcoder
));
5946 pipe_config
->adjusted_mode
.crtc_vblank_start
= (tmp
& 0xffff) + 1;
5947 pipe_config
->adjusted_mode
.crtc_vblank_end
= ((tmp
>> 16) & 0xffff) + 1;
5948 tmp
= I915_READ(VSYNC(cpu_transcoder
));
5949 pipe_config
->adjusted_mode
.crtc_vsync_start
= (tmp
& 0xffff) + 1;
5950 pipe_config
->adjusted_mode
.crtc_vsync_end
= ((tmp
>> 16) & 0xffff) + 1;
5952 if (I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_INTERLACE_MASK
) {
5953 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
5954 pipe_config
->adjusted_mode
.crtc_vtotal
+= 1;
5955 pipe_config
->adjusted_mode
.crtc_vblank_end
+= 1;
5958 tmp
= I915_READ(PIPESRC(crtc
->pipe
));
5959 pipe_config
->pipe_src_h
= (tmp
& 0xffff) + 1;
5960 pipe_config
->pipe_src_w
= ((tmp
>> 16) & 0xffff) + 1;
5962 pipe_config
->requested_mode
.vdisplay
= pipe_config
->pipe_src_h
;
5963 pipe_config
->requested_mode
.hdisplay
= pipe_config
->pipe_src_w
;
5966 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
5967 struct intel_crtc_config
*pipe_config
)
5969 mode
->hdisplay
= pipe_config
->adjusted_mode
.crtc_hdisplay
;
5970 mode
->htotal
= pipe_config
->adjusted_mode
.crtc_htotal
;
5971 mode
->hsync_start
= pipe_config
->adjusted_mode
.crtc_hsync_start
;
5972 mode
->hsync_end
= pipe_config
->adjusted_mode
.crtc_hsync_end
;
5974 mode
->vdisplay
= pipe_config
->adjusted_mode
.crtc_vdisplay
;
5975 mode
->vtotal
= pipe_config
->adjusted_mode
.crtc_vtotal
;
5976 mode
->vsync_start
= pipe_config
->adjusted_mode
.crtc_vsync_start
;
5977 mode
->vsync_end
= pipe_config
->adjusted_mode
.crtc_vsync_end
;
5979 mode
->flags
= pipe_config
->adjusted_mode
.flags
;
5981 mode
->clock
= pipe_config
->adjusted_mode
.crtc_clock
;
5982 mode
->flags
|= pipe_config
->adjusted_mode
.flags
;
5985 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
)
5987 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5988 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5993 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
5994 I915_READ(PIPECONF(intel_crtc
->pipe
)) & PIPECONF_ENABLE
)
5995 pipeconf
|= PIPECONF_ENABLE
;
5997 if (intel_crtc
->config
.double_wide
)
5998 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
6000 /* only g4x and later have fancy bpc/dither controls */
6001 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
6002 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6003 if (intel_crtc
->config
.dither
&& intel_crtc
->config
.pipe_bpp
!= 30)
6004 pipeconf
|= PIPECONF_DITHER_EN
|
6005 PIPECONF_DITHER_TYPE_SP
;
6007 switch (intel_crtc
->config
.pipe_bpp
) {
6009 pipeconf
|= PIPECONF_6BPC
;
6012 pipeconf
|= PIPECONF_8BPC
;
6015 pipeconf
|= PIPECONF_10BPC
;
6018 /* Case prevented by intel_choose_pipe_bpp_dither. */
6023 if (HAS_PIPE_CXSR(dev
)) {
6024 if (intel_crtc
->lowfreq_avail
) {
6025 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6026 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
6028 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6032 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
6033 if (INTEL_INFO(dev
)->gen
< 4 ||
6034 intel_pipe_has_type(&intel_crtc
->base
, INTEL_OUTPUT_SDVO
))
6035 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
6037 pipeconf
|= PIPECONF_INTERLACE_W_SYNC_SHIFT
;
6039 pipeconf
|= PIPECONF_PROGRESSIVE
;
6041 if (IS_VALLEYVIEW(dev
) && intel_crtc
->config
.limited_color_range
)
6042 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
6044 I915_WRITE(PIPECONF(intel_crtc
->pipe
), pipeconf
);
6045 POSTING_READ(PIPECONF(intel_crtc
->pipe
));
6048 static int i9xx_crtc_mode_set(struct drm_crtc
*crtc
,
6050 struct drm_framebuffer
*fb
)
6052 struct drm_device
*dev
= crtc
->dev
;
6053 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6054 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6055 int refclk
, num_connectors
= 0;
6056 intel_clock_t clock
, reduced_clock
;
6057 bool ok
, has_reduced_clock
= false;
6058 bool is_lvds
= false, is_dsi
= false;
6059 struct intel_encoder
*encoder
;
6060 const intel_limit_t
*limit
;
6062 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
6063 switch (encoder
->type
) {
6064 case INTEL_OUTPUT_LVDS
:
6067 case INTEL_OUTPUT_DSI
:
6078 if (!intel_crtc
->config
.clock_set
) {
6079 refclk
= i9xx_get_refclk(crtc
, num_connectors
);
6082 * Returns a set of divisors for the desired target clock with
6083 * the given refclk, or FALSE. The returned values represent
6084 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6087 limit
= intel_limit(crtc
, refclk
);
6088 ok
= dev_priv
->display
.find_dpll(limit
, crtc
,
6089 intel_crtc
->config
.port_clock
,
6090 refclk
, NULL
, &clock
);
6092 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6096 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
6098 * Ensure we match the reduced clock's P to the target
6099 * clock. If the clocks don't match, we can't switch
6100 * the display clock by using the FP0/FP1. In such case
6101 * we will disable the LVDS downclock feature.
6104 dev_priv
->display
.find_dpll(limit
, crtc
,
6105 dev_priv
->lvds_downclock
,
6109 /* Compat-code for transition, will disappear. */
6110 intel_crtc
->config
.dpll
.n
= clock
.n
;
6111 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
6112 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
6113 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
6114 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
6118 i8xx_update_pll(intel_crtc
,
6119 has_reduced_clock
? &reduced_clock
: NULL
,
6121 } else if (IS_CHERRYVIEW(dev
)) {
6122 chv_update_pll(intel_crtc
);
6123 } else if (IS_VALLEYVIEW(dev
)) {
6124 vlv_update_pll(intel_crtc
);
6126 i9xx_update_pll(intel_crtc
,
6127 has_reduced_clock
? &reduced_clock
: NULL
,
6134 static void i9xx_get_pfit_config(struct intel_crtc
*crtc
,
6135 struct intel_crtc_config
*pipe_config
)
6137 struct drm_device
*dev
= crtc
->base
.dev
;
6138 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6141 if (INTEL_INFO(dev
)->gen
<= 3 && (IS_I830(dev
) || !IS_MOBILE(dev
)))
6144 tmp
= I915_READ(PFIT_CONTROL
);
6145 if (!(tmp
& PFIT_ENABLE
))
6148 /* Check whether the pfit is attached to our pipe. */
6149 if (INTEL_INFO(dev
)->gen
< 4) {
6150 if (crtc
->pipe
!= PIPE_B
)
6153 if ((tmp
& PFIT_PIPE_MASK
) != (crtc
->pipe
<< PFIT_PIPE_SHIFT
))
6157 pipe_config
->gmch_pfit
.control
= tmp
;
6158 pipe_config
->gmch_pfit
.pgm_ratios
= I915_READ(PFIT_PGM_RATIOS
);
6159 if (INTEL_INFO(dev
)->gen
< 5)
6160 pipe_config
->gmch_pfit
.lvds_border_bits
=
6161 I915_READ(LVDS
) & LVDS_BORDER_ENABLE
;
6164 static void vlv_crtc_clock_get(struct intel_crtc
*crtc
,
6165 struct intel_crtc_config
*pipe_config
)
6167 struct drm_device
*dev
= crtc
->base
.dev
;
6168 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6169 int pipe
= pipe_config
->cpu_transcoder
;
6170 intel_clock_t clock
;
6172 int refclk
= 100000;
6174 /* In case of MIPI DPLL will not even be used */
6175 if (!(pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
))
6178 mutex_lock(&dev_priv
->dpio_lock
);
6179 mdiv
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW3(pipe
));
6180 mutex_unlock(&dev_priv
->dpio_lock
);
6182 clock
.m1
= (mdiv
>> DPIO_M1DIV_SHIFT
) & 7;
6183 clock
.m2
= mdiv
& DPIO_M2DIV_MASK
;
6184 clock
.n
= (mdiv
>> DPIO_N_SHIFT
) & 0xf;
6185 clock
.p1
= (mdiv
>> DPIO_P1_SHIFT
) & 7;
6186 clock
.p2
= (mdiv
>> DPIO_P2_SHIFT
) & 0x1f;
6188 vlv_clock(refclk
, &clock
);
6190 /* clock.dot is the fast clock */
6191 pipe_config
->port_clock
= clock
.dot
/ 5;
6194 static void i9xx_get_plane_config(struct intel_crtc
*crtc
,
6195 struct intel_plane_config
*plane_config
)
6197 struct drm_device
*dev
= crtc
->base
.dev
;
6198 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6199 u32 val
, base
, offset
;
6200 int pipe
= crtc
->pipe
, plane
= crtc
->plane
;
6201 int fourcc
, pixel_format
;
6204 crtc
->base
.primary
->fb
= kzalloc(sizeof(struct intel_framebuffer
), GFP_KERNEL
);
6205 if (!crtc
->base
.primary
->fb
) {
6206 DRM_DEBUG_KMS("failed to alloc fb\n");
6210 val
= I915_READ(DSPCNTR(plane
));
6212 if (INTEL_INFO(dev
)->gen
>= 4)
6213 if (val
& DISPPLANE_TILED
)
6214 plane_config
->tiled
= true;
6216 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
6217 fourcc
= intel_format_to_fourcc(pixel_format
);
6218 crtc
->base
.primary
->fb
->pixel_format
= fourcc
;
6219 crtc
->base
.primary
->fb
->bits_per_pixel
=
6220 drm_format_plane_cpp(fourcc
, 0) * 8;
6222 if (INTEL_INFO(dev
)->gen
>= 4) {
6223 if (plane_config
->tiled
)
6224 offset
= I915_READ(DSPTILEOFF(plane
));
6226 offset
= I915_READ(DSPLINOFF(plane
));
6227 base
= I915_READ(DSPSURF(plane
)) & 0xfffff000;
6229 base
= I915_READ(DSPADDR(plane
));
6231 plane_config
->base
= base
;
6233 val
= I915_READ(PIPESRC(pipe
));
6234 crtc
->base
.primary
->fb
->width
= ((val
>> 16) & 0xfff) + 1;
6235 crtc
->base
.primary
->fb
->height
= ((val
>> 0) & 0xfff) + 1;
6237 val
= I915_READ(DSPSTRIDE(pipe
));
6238 crtc
->base
.primary
->fb
->pitches
[0] = val
& 0xffffff80;
6240 aligned_height
= intel_align_height(dev
, crtc
->base
.primary
->fb
->height
,
6241 plane_config
->tiled
);
6243 plane_config
->size
= PAGE_ALIGN(crtc
->base
.primary
->fb
->pitches
[0] *
6246 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6247 pipe
, plane
, crtc
->base
.primary
->fb
->width
,
6248 crtc
->base
.primary
->fb
->height
,
6249 crtc
->base
.primary
->fb
->bits_per_pixel
, base
,
6250 crtc
->base
.primary
->fb
->pitches
[0],
6251 plane_config
->size
);
6255 static void chv_crtc_clock_get(struct intel_crtc
*crtc
,
6256 struct intel_crtc_config
*pipe_config
)
6258 struct drm_device
*dev
= crtc
->base
.dev
;
6259 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6260 int pipe
= pipe_config
->cpu_transcoder
;
6261 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
6262 intel_clock_t clock
;
6263 u32 cmn_dw13
, pll_dw0
, pll_dw1
, pll_dw2
;
6264 int refclk
= 100000;
6266 mutex_lock(&dev_priv
->dpio_lock
);
6267 cmn_dw13
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW13(port
));
6268 pll_dw0
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW0(port
));
6269 pll_dw1
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW1(port
));
6270 pll_dw2
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW2(port
));
6271 mutex_unlock(&dev_priv
->dpio_lock
);
6273 clock
.m1
= (pll_dw1
& 0x7) == DPIO_CHV_M1_DIV_BY_2
? 2 : 0;
6274 clock
.m2
= ((pll_dw0
& 0xff) << 22) | (pll_dw2
& 0x3fffff);
6275 clock
.n
= (pll_dw1
>> DPIO_CHV_N_DIV_SHIFT
) & 0xf;
6276 clock
.p1
= (cmn_dw13
>> DPIO_CHV_P1_DIV_SHIFT
) & 0x7;
6277 clock
.p2
= (cmn_dw13
>> DPIO_CHV_P2_DIV_SHIFT
) & 0x1f;
6279 chv_clock(refclk
, &clock
);
6281 /* clock.dot is the fast clock */
6282 pipe_config
->port_clock
= clock
.dot
/ 5;
6285 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
6286 struct intel_crtc_config
*pipe_config
)
6288 struct drm_device
*dev
= crtc
->base
.dev
;
6289 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6292 if (!intel_display_power_enabled(dev_priv
,
6293 POWER_DOMAIN_PIPE(crtc
->pipe
)))
6296 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
6297 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
6299 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
6300 if (!(tmp
& PIPECONF_ENABLE
))
6303 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
6304 switch (tmp
& PIPECONF_BPC_MASK
) {
6306 pipe_config
->pipe_bpp
= 18;
6309 pipe_config
->pipe_bpp
= 24;
6311 case PIPECONF_10BPC
:
6312 pipe_config
->pipe_bpp
= 30;
6319 if (IS_VALLEYVIEW(dev
) && (tmp
& PIPECONF_COLOR_RANGE_SELECT
))
6320 pipe_config
->limited_color_range
= true;
6322 if (INTEL_INFO(dev
)->gen
< 4)
6323 pipe_config
->double_wide
= tmp
& PIPECONF_DOUBLE_WIDE
;
6325 intel_get_pipe_timings(crtc
, pipe_config
);
6327 i9xx_get_pfit_config(crtc
, pipe_config
);
6329 if (INTEL_INFO(dev
)->gen
>= 4) {
6330 tmp
= I915_READ(DPLL_MD(crtc
->pipe
));
6331 pipe_config
->pixel_multiplier
=
6332 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
6333 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
6334 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
6335 } else if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
6336 tmp
= I915_READ(DPLL(crtc
->pipe
));
6337 pipe_config
->pixel_multiplier
=
6338 ((tmp
& SDVO_MULTIPLIER_MASK
)
6339 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
6341 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6342 * port and will be fixed up in the encoder->get_config
6344 pipe_config
->pixel_multiplier
= 1;
6346 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(crtc
->pipe
));
6347 if (!IS_VALLEYVIEW(dev
)) {
6348 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(crtc
->pipe
));
6349 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(crtc
->pipe
));
6351 /* Mask out read-only status bits. */
6352 pipe_config
->dpll_hw_state
.dpll
&= ~(DPLL_LOCK_VLV
|
6353 DPLL_PORTC_READY_MASK
|
6354 DPLL_PORTB_READY_MASK
);
6357 if (IS_CHERRYVIEW(dev
))
6358 chv_crtc_clock_get(crtc
, pipe_config
);
6359 else if (IS_VALLEYVIEW(dev
))
6360 vlv_crtc_clock_get(crtc
, pipe_config
);
6362 i9xx_crtc_clock_get(crtc
, pipe_config
);
6367 static void ironlake_init_pch_refclk(struct drm_device
*dev
)
6369 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6370 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
6371 struct intel_encoder
*encoder
;
6373 bool has_lvds
= false;
6374 bool has_cpu_edp
= false;
6375 bool has_panel
= false;
6376 bool has_ck505
= false;
6377 bool can_ssc
= false;
6379 /* We need to take the global config into account */
6380 list_for_each_entry(encoder
, &mode_config
->encoder_list
,
6382 switch (encoder
->type
) {
6383 case INTEL_OUTPUT_LVDS
:
6387 case INTEL_OUTPUT_EDP
:
6389 if (enc_to_dig_port(&encoder
->base
)->port
== PORT_A
)
6395 if (HAS_PCH_IBX(dev
)) {
6396 has_ck505
= dev_priv
->vbt
.display_clock_mode
;
6397 can_ssc
= has_ck505
;
6403 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6404 has_panel
, has_lvds
, has_ck505
);
6406 /* Ironlake: try to setup display ref clock before DPLL
6407 * enabling. This is only under driver's control after
6408 * PCH B stepping, previous chipset stepping should be
6409 * ignoring this setting.
6411 val
= I915_READ(PCH_DREF_CONTROL
);
6413 /* As we must carefully and slowly disable/enable each source in turn,
6414 * compute the final state we want first and check if we need to
6415 * make any changes at all.
6418 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
6420 final
|= DREF_NONSPREAD_CK505_ENABLE
;
6422 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
6424 final
&= ~DREF_SSC_SOURCE_MASK
;
6425 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
6426 final
&= ~DREF_SSC1_ENABLE
;
6429 final
|= DREF_SSC_SOURCE_ENABLE
;
6431 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
6432 final
|= DREF_SSC1_ENABLE
;
6435 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
6436 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
6438 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
6440 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6442 final
|= DREF_SSC_SOURCE_DISABLE
;
6443 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6449 /* Always enable nonspread source */
6450 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
6453 val
|= DREF_NONSPREAD_CK505_ENABLE
;
6455 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
6458 val
&= ~DREF_SSC_SOURCE_MASK
;
6459 val
|= DREF_SSC_SOURCE_ENABLE
;
6461 /* SSC must be turned on before enabling the CPU output */
6462 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
6463 DRM_DEBUG_KMS("Using SSC on panel\n");
6464 val
|= DREF_SSC1_ENABLE
;
6466 val
&= ~DREF_SSC1_ENABLE
;
6468 /* Get SSC going before enabling the outputs */
6469 I915_WRITE(PCH_DREF_CONTROL
, val
);
6470 POSTING_READ(PCH_DREF_CONTROL
);
6473 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
6475 /* Enable CPU source on CPU attached eDP */
6477 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
6478 DRM_DEBUG_KMS("Using SSC on eDP\n");
6479 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
6481 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
6483 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6485 I915_WRITE(PCH_DREF_CONTROL
, val
);
6486 POSTING_READ(PCH_DREF_CONTROL
);
6489 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6491 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
6493 /* Turn off CPU output */
6494 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6496 I915_WRITE(PCH_DREF_CONTROL
, val
);
6497 POSTING_READ(PCH_DREF_CONTROL
);
6500 /* Turn off the SSC source */
6501 val
&= ~DREF_SSC_SOURCE_MASK
;
6502 val
|= DREF_SSC_SOURCE_DISABLE
;
6505 val
&= ~DREF_SSC1_ENABLE
;
6507 I915_WRITE(PCH_DREF_CONTROL
, val
);
6508 POSTING_READ(PCH_DREF_CONTROL
);
6512 BUG_ON(val
!= final
);
6515 static void lpt_reset_fdi_mphy(struct drm_i915_private
*dev_priv
)
6519 tmp
= I915_READ(SOUTH_CHICKEN2
);
6520 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
6521 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
6523 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2
) &
6524 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
6525 DRM_ERROR("FDI mPHY reset assert timeout\n");
6527 tmp
= I915_READ(SOUTH_CHICKEN2
);
6528 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
6529 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
6531 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2
) &
6532 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0, 100))
6533 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6536 /* WaMPhyProgramming:hsw */
6537 static void lpt_program_fdi_mphy(struct drm_i915_private
*dev_priv
)
6541 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
6542 tmp
&= ~(0xFF << 24);
6543 tmp
|= (0x12 << 24);
6544 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
6546 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
6548 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
6550 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
6552 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
6554 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
6555 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
6556 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
6558 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
6559 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
6560 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
6562 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
6565 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
6567 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
6570 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
6572 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
6575 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
6577 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
6580 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
6582 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
6583 tmp
&= ~(0xFF << 16);
6584 tmp
|= (0x1C << 16);
6585 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
6587 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
6588 tmp
&= ~(0xFF << 16);
6589 tmp
|= (0x1C << 16);
6590 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
6592 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
6594 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
6596 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
6598 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
6600 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
6601 tmp
&= ~(0xF << 28);
6603 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
6605 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
6606 tmp
&= ~(0xF << 28);
6608 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
6611 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6612 * Programming" based on the parameters passed:
6613 * - Sequence to enable CLKOUT_DP
6614 * - Sequence to enable CLKOUT_DP without spread
6615 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6617 static void lpt_enable_clkout_dp(struct drm_device
*dev
, bool with_spread
,
6620 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6623 if (WARN(with_fdi
&& !with_spread
, "FDI requires downspread\n"))
6625 if (WARN(dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
&&
6626 with_fdi
, "LP PCH doesn't have FDI\n"))
6629 mutex_lock(&dev_priv
->dpio_lock
);
6631 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
6632 tmp
&= ~SBI_SSCCTL_DISABLE
;
6633 tmp
|= SBI_SSCCTL_PATHALT
;
6634 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
6639 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
6640 tmp
&= ~SBI_SSCCTL_PATHALT
;
6641 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
6644 lpt_reset_fdi_mphy(dev_priv
);
6645 lpt_program_fdi_mphy(dev_priv
);
6649 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
6650 SBI_GEN0
: SBI_DBUFF0
;
6651 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
6652 tmp
|= SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
6653 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
6655 mutex_unlock(&dev_priv
->dpio_lock
);
6658 /* Sequence to disable CLKOUT_DP */
6659 static void lpt_disable_clkout_dp(struct drm_device
*dev
)
6661 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6664 mutex_lock(&dev_priv
->dpio_lock
);
6666 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
6667 SBI_GEN0
: SBI_DBUFF0
;
6668 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
6669 tmp
&= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
6670 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
6672 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
6673 if (!(tmp
& SBI_SSCCTL_DISABLE
)) {
6674 if (!(tmp
& SBI_SSCCTL_PATHALT
)) {
6675 tmp
|= SBI_SSCCTL_PATHALT
;
6676 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
6679 tmp
|= SBI_SSCCTL_DISABLE
;
6680 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
6683 mutex_unlock(&dev_priv
->dpio_lock
);
6686 static void lpt_init_pch_refclk(struct drm_device
*dev
)
6688 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
6689 struct intel_encoder
*encoder
;
6690 bool has_vga
= false;
6692 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
) {
6693 switch (encoder
->type
) {
6694 case INTEL_OUTPUT_ANALOG
:
6701 lpt_enable_clkout_dp(dev
, true, true);
6703 lpt_disable_clkout_dp(dev
);
6707 * Initialize reference clocks when the driver loads
6709 void intel_init_pch_refclk(struct drm_device
*dev
)
6711 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
6712 ironlake_init_pch_refclk(dev
);
6713 else if (HAS_PCH_LPT(dev
))
6714 lpt_init_pch_refclk(dev
);
6717 static int ironlake_get_refclk(struct drm_crtc
*crtc
)
6719 struct drm_device
*dev
= crtc
->dev
;
6720 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6721 struct intel_encoder
*encoder
;
6722 int num_connectors
= 0;
6723 bool is_lvds
= false;
6725 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
6726 switch (encoder
->type
) {
6727 case INTEL_OUTPUT_LVDS
:
6734 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
6735 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6736 dev_priv
->vbt
.lvds_ssc_freq
);
6737 return dev_priv
->vbt
.lvds_ssc_freq
;
6743 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
)
6745 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
6746 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6747 int pipe
= intel_crtc
->pipe
;
6752 switch (intel_crtc
->config
.pipe_bpp
) {
6754 val
|= PIPECONF_6BPC
;
6757 val
|= PIPECONF_8BPC
;
6760 val
|= PIPECONF_10BPC
;
6763 val
|= PIPECONF_12BPC
;
6766 /* Case prevented by intel_choose_pipe_bpp_dither. */
6770 if (intel_crtc
->config
.dither
)
6771 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
6773 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
6774 val
|= PIPECONF_INTERLACED_ILK
;
6776 val
|= PIPECONF_PROGRESSIVE
;
6778 if (intel_crtc
->config
.limited_color_range
)
6779 val
|= PIPECONF_COLOR_RANGE_SELECT
;
6781 I915_WRITE(PIPECONF(pipe
), val
);
6782 POSTING_READ(PIPECONF(pipe
));
6786 * Set up the pipe CSC unit.
6788 * Currently only full range RGB to limited range RGB conversion
6789 * is supported, but eventually this should handle various
6790 * RGB<->YCbCr scenarios as well.
6792 static void intel_set_pipe_csc(struct drm_crtc
*crtc
)
6794 struct drm_device
*dev
= crtc
->dev
;
6795 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6796 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6797 int pipe
= intel_crtc
->pipe
;
6798 uint16_t coeff
= 0x7800; /* 1.0 */
6801 * TODO: Check what kind of values actually come out of the pipe
6802 * with these coeff/postoff values and adjust to get the best
6803 * accuracy. Perhaps we even need to take the bpc value into
6807 if (intel_crtc
->config
.limited_color_range
)
6808 coeff
= ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6811 * GY/GU and RY/RU should be the other way around according
6812 * to BSpec, but reality doesn't agree. Just set them up in
6813 * a way that results in the correct picture.
6815 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe
), coeff
<< 16);
6816 I915_WRITE(PIPE_CSC_COEFF_BY(pipe
), 0);
6818 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe
), coeff
);
6819 I915_WRITE(PIPE_CSC_COEFF_BU(pipe
), 0);
6821 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe
), 0);
6822 I915_WRITE(PIPE_CSC_COEFF_BV(pipe
), coeff
<< 16);
6824 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe
), 0);
6825 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe
), 0);
6826 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe
), 0);
6828 if (INTEL_INFO(dev
)->gen
> 6) {
6829 uint16_t postoff
= 0;
6831 if (intel_crtc
->config
.limited_color_range
)
6832 postoff
= (16 * (1 << 12) / 255) & 0x1fff;
6834 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe
), postoff
);
6835 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe
), postoff
);
6836 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe
), postoff
);
6838 I915_WRITE(PIPE_CSC_MODE(pipe
), 0);
6840 uint32_t mode
= CSC_MODE_YUV_TO_RGB
;
6842 if (intel_crtc
->config
.limited_color_range
)
6843 mode
|= CSC_BLACK_SCREEN_OFFSET
;
6845 I915_WRITE(PIPE_CSC_MODE(pipe
), mode
);
6849 static void haswell_set_pipeconf(struct drm_crtc
*crtc
)
6851 struct drm_device
*dev
= crtc
->dev
;
6852 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6853 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6854 enum pipe pipe
= intel_crtc
->pipe
;
6855 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
6860 if (IS_HASWELL(dev
) && intel_crtc
->config
.dither
)
6861 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
6863 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
6864 val
|= PIPECONF_INTERLACED_ILK
;
6866 val
|= PIPECONF_PROGRESSIVE
;
6868 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
6869 POSTING_READ(PIPECONF(cpu_transcoder
));
6871 I915_WRITE(GAMMA_MODE(intel_crtc
->pipe
), GAMMA_MODE_MODE_8BIT
);
6872 POSTING_READ(GAMMA_MODE(intel_crtc
->pipe
));
6874 if (IS_BROADWELL(dev
)) {
6877 switch (intel_crtc
->config
.pipe_bpp
) {
6879 val
|= PIPEMISC_DITHER_6_BPC
;
6882 val
|= PIPEMISC_DITHER_8_BPC
;
6885 val
|= PIPEMISC_DITHER_10_BPC
;
6888 val
|= PIPEMISC_DITHER_12_BPC
;
6891 /* Case prevented by pipe_config_set_bpp. */
6895 if (intel_crtc
->config
.dither
)
6896 val
|= PIPEMISC_DITHER_ENABLE
| PIPEMISC_DITHER_TYPE_SP
;
6898 I915_WRITE(PIPEMISC(pipe
), val
);
6902 static bool ironlake_compute_clocks(struct drm_crtc
*crtc
,
6903 intel_clock_t
*clock
,
6904 bool *has_reduced_clock
,
6905 intel_clock_t
*reduced_clock
)
6907 struct drm_device
*dev
= crtc
->dev
;
6908 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6909 struct intel_encoder
*intel_encoder
;
6911 const intel_limit_t
*limit
;
6912 bool ret
, is_lvds
= false;
6914 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
6915 switch (intel_encoder
->type
) {
6916 case INTEL_OUTPUT_LVDS
:
6922 refclk
= ironlake_get_refclk(crtc
);
6925 * Returns a set of divisors for the desired target clock with the given
6926 * refclk, or FALSE. The returned values represent the clock equation:
6927 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6929 limit
= intel_limit(crtc
, refclk
);
6930 ret
= dev_priv
->display
.find_dpll(limit
, crtc
,
6931 to_intel_crtc(crtc
)->config
.port_clock
,
6932 refclk
, NULL
, clock
);
6936 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
6938 * Ensure we match the reduced clock's P to the target clock.
6939 * If the clocks don't match, we can't switch the display clock
6940 * by using the FP0/FP1. In such case we will disable the LVDS
6941 * downclock feature.
6943 *has_reduced_clock
=
6944 dev_priv
->display
.find_dpll(limit
, crtc
,
6945 dev_priv
->lvds_downclock
,
6953 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
6956 * Account for spread spectrum to avoid
6957 * oversubscribing the link. Max center spread
6958 * is 2.5%; use 5% for safety's sake.
6960 u32 bps
= target_clock
* bpp
* 21 / 20;
6961 return DIV_ROUND_UP(bps
, link_bw
* 8);
6964 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
6966 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
6969 static uint32_t ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
6971 intel_clock_t
*reduced_clock
, u32
*fp2
)
6973 struct drm_crtc
*crtc
= &intel_crtc
->base
;
6974 struct drm_device
*dev
= crtc
->dev
;
6975 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6976 struct intel_encoder
*intel_encoder
;
6978 int factor
, num_connectors
= 0;
6979 bool is_lvds
= false, is_sdvo
= false;
6981 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
6982 switch (intel_encoder
->type
) {
6983 case INTEL_OUTPUT_LVDS
:
6986 case INTEL_OUTPUT_SDVO
:
6987 case INTEL_OUTPUT_HDMI
:
6995 /* Enable autotuning of the PLL clock (if permissible) */
6998 if ((intel_panel_use_ssc(dev_priv
) &&
6999 dev_priv
->vbt
.lvds_ssc_freq
== 100000) ||
7000 (HAS_PCH_IBX(dev
) && intel_is_dual_link_lvds(dev
)))
7002 } else if (intel_crtc
->config
.sdvo_tv_clock
)
7005 if (ironlake_needs_fb_cb_tune(&intel_crtc
->config
.dpll
, factor
))
7008 if (fp2
&& (reduced_clock
->m
< factor
* reduced_clock
->n
))
7014 dpll
|= DPLLB_MODE_LVDS
;
7016 dpll
|= DPLLB_MODE_DAC_SERIAL
;
7018 dpll
|= (intel_crtc
->config
.pixel_multiplier
- 1)
7019 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
7022 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7023 if (intel_crtc
->config
.has_dp_encoder
)
7024 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7026 /* compute bitmask from p1 value */
7027 dpll
|= (1 << (intel_crtc
->config
.dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7029 dpll
|= (1 << (intel_crtc
->config
.dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
7031 switch (intel_crtc
->config
.dpll
.p2
) {
7033 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
7036 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
7039 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
7042 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
7046 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
7047 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
7049 dpll
|= PLL_REF_INPUT_DREFCLK
;
7051 return dpll
| DPLL_VCO_ENABLE
;
7054 static int ironlake_crtc_mode_set(struct drm_crtc
*crtc
,
7056 struct drm_framebuffer
*fb
)
7058 struct drm_device
*dev
= crtc
->dev
;
7059 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7060 int num_connectors
= 0;
7061 intel_clock_t clock
, reduced_clock
;
7062 u32 dpll
= 0, fp
= 0, fp2
= 0;
7063 bool ok
, has_reduced_clock
= false;
7064 bool is_lvds
= false;
7065 struct intel_encoder
*encoder
;
7066 struct intel_shared_dpll
*pll
;
7068 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
7069 switch (encoder
->type
) {
7070 case INTEL_OUTPUT_LVDS
:
7078 WARN(!(HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)),
7079 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev
));
7081 ok
= ironlake_compute_clocks(crtc
, &clock
,
7082 &has_reduced_clock
, &reduced_clock
);
7083 if (!ok
&& !intel_crtc
->config
.clock_set
) {
7084 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7087 /* Compat-code for transition, will disappear. */
7088 if (!intel_crtc
->config
.clock_set
) {
7089 intel_crtc
->config
.dpll
.n
= clock
.n
;
7090 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
7091 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
7092 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
7093 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
7096 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7097 if (intel_crtc
->config
.has_pch_encoder
) {
7098 fp
= i9xx_dpll_compute_fp(&intel_crtc
->config
.dpll
);
7099 if (has_reduced_clock
)
7100 fp2
= i9xx_dpll_compute_fp(&reduced_clock
);
7102 dpll
= ironlake_compute_dpll(intel_crtc
,
7103 &fp
, &reduced_clock
,
7104 has_reduced_clock
? &fp2
: NULL
);
7106 intel_crtc
->config
.dpll_hw_state
.dpll
= dpll
;
7107 intel_crtc
->config
.dpll_hw_state
.fp0
= fp
;
7108 if (has_reduced_clock
)
7109 intel_crtc
->config
.dpll_hw_state
.fp1
= fp2
;
7111 intel_crtc
->config
.dpll_hw_state
.fp1
= fp
;
7113 pll
= intel_get_shared_dpll(intel_crtc
);
7115 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7116 pipe_name(intel_crtc
->pipe
));
7120 intel_put_shared_dpll(intel_crtc
);
7122 if (is_lvds
&& has_reduced_clock
&& i915
.powersave
)
7123 intel_crtc
->lowfreq_avail
= true;
7125 intel_crtc
->lowfreq_avail
= false;
7130 static void intel_pch_transcoder_get_m_n(struct intel_crtc
*crtc
,
7131 struct intel_link_m_n
*m_n
)
7133 struct drm_device
*dev
= crtc
->base
.dev
;
7134 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7135 enum pipe pipe
= crtc
->pipe
;
7137 m_n
->link_m
= I915_READ(PCH_TRANS_LINK_M1(pipe
));
7138 m_n
->link_n
= I915_READ(PCH_TRANS_LINK_N1(pipe
));
7139 m_n
->gmch_m
= I915_READ(PCH_TRANS_DATA_M1(pipe
))
7141 m_n
->gmch_n
= I915_READ(PCH_TRANS_DATA_N1(pipe
));
7142 m_n
->tu
= ((I915_READ(PCH_TRANS_DATA_M1(pipe
))
7143 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7146 static void intel_cpu_transcoder_get_m_n(struct intel_crtc
*crtc
,
7147 enum transcoder transcoder
,
7148 struct intel_link_m_n
*m_n
)
7150 struct drm_device
*dev
= crtc
->base
.dev
;
7151 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7152 enum pipe pipe
= crtc
->pipe
;
7154 if (INTEL_INFO(dev
)->gen
>= 5) {
7155 m_n
->link_m
= I915_READ(PIPE_LINK_M1(transcoder
));
7156 m_n
->link_n
= I915_READ(PIPE_LINK_N1(transcoder
));
7157 m_n
->gmch_m
= I915_READ(PIPE_DATA_M1(transcoder
))
7159 m_n
->gmch_n
= I915_READ(PIPE_DATA_N1(transcoder
));
7160 m_n
->tu
= ((I915_READ(PIPE_DATA_M1(transcoder
))
7161 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7163 m_n
->link_m
= I915_READ(PIPE_LINK_M_G4X(pipe
));
7164 m_n
->link_n
= I915_READ(PIPE_LINK_N_G4X(pipe
));
7165 m_n
->gmch_m
= I915_READ(PIPE_DATA_M_G4X(pipe
))
7167 m_n
->gmch_n
= I915_READ(PIPE_DATA_N_G4X(pipe
));
7168 m_n
->tu
= ((I915_READ(PIPE_DATA_M_G4X(pipe
))
7169 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7173 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
7174 struct intel_crtc_config
*pipe_config
)
7176 if (crtc
->config
.has_pch_encoder
)
7177 intel_pch_transcoder_get_m_n(crtc
, &pipe_config
->dp_m_n
);
7179 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
7180 &pipe_config
->dp_m_n
);
7183 static void ironlake_get_fdi_m_n_config(struct intel_crtc
*crtc
,
7184 struct intel_crtc_config
*pipe_config
)
7186 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
7187 &pipe_config
->fdi_m_n
);
7190 static void ironlake_get_pfit_config(struct intel_crtc
*crtc
,
7191 struct intel_crtc_config
*pipe_config
)
7193 struct drm_device
*dev
= crtc
->base
.dev
;
7194 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7197 tmp
= I915_READ(PF_CTL(crtc
->pipe
));
7199 if (tmp
& PF_ENABLE
) {
7200 pipe_config
->pch_pfit
.enabled
= true;
7201 pipe_config
->pch_pfit
.pos
= I915_READ(PF_WIN_POS(crtc
->pipe
));
7202 pipe_config
->pch_pfit
.size
= I915_READ(PF_WIN_SZ(crtc
->pipe
));
7204 /* We currently do not free assignements of panel fitters on
7205 * ivb/hsw (since we don't use the higher upscaling modes which
7206 * differentiates them) so just WARN about this case for now. */
7208 WARN_ON((tmp
& PF_PIPE_SEL_MASK_IVB
) !=
7209 PF_PIPE_SEL_IVB(crtc
->pipe
));
7214 static void ironlake_get_plane_config(struct intel_crtc
*crtc
,
7215 struct intel_plane_config
*plane_config
)
7217 struct drm_device
*dev
= crtc
->base
.dev
;
7218 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7219 u32 val
, base
, offset
;
7220 int pipe
= crtc
->pipe
, plane
= crtc
->plane
;
7221 int fourcc
, pixel_format
;
7224 crtc
->base
.primary
->fb
= kzalloc(sizeof(struct intel_framebuffer
), GFP_KERNEL
);
7225 if (!crtc
->base
.primary
->fb
) {
7226 DRM_DEBUG_KMS("failed to alloc fb\n");
7230 val
= I915_READ(DSPCNTR(plane
));
7232 if (INTEL_INFO(dev
)->gen
>= 4)
7233 if (val
& DISPPLANE_TILED
)
7234 plane_config
->tiled
= true;
7236 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
7237 fourcc
= intel_format_to_fourcc(pixel_format
);
7238 crtc
->base
.primary
->fb
->pixel_format
= fourcc
;
7239 crtc
->base
.primary
->fb
->bits_per_pixel
=
7240 drm_format_plane_cpp(fourcc
, 0) * 8;
7242 base
= I915_READ(DSPSURF(plane
)) & 0xfffff000;
7243 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
7244 offset
= I915_READ(DSPOFFSET(plane
));
7246 if (plane_config
->tiled
)
7247 offset
= I915_READ(DSPTILEOFF(plane
));
7249 offset
= I915_READ(DSPLINOFF(plane
));
7251 plane_config
->base
= base
;
7253 val
= I915_READ(PIPESRC(pipe
));
7254 crtc
->base
.primary
->fb
->width
= ((val
>> 16) & 0xfff) + 1;
7255 crtc
->base
.primary
->fb
->height
= ((val
>> 0) & 0xfff) + 1;
7257 val
= I915_READ(DSPSTRIDE(pipe
));
7258 crtc
->base
.primary
->fb
->pitches
[0] = val
& 0xffffff80;
7260 aligned_height
= intel_align_height(dev
, crtc
->base
.primary
->fb
->height
,
7261 plane_config
->tiled
);
7263 plane_config
->size
= PAGE_ALIGN(crtc
->base
.primary
->fb
->pitches
[0] *
7266 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7267 pipe
, plane
, crtc
->base
.primary
->fb
->width
,
7268 crtc
->base
.primary
->fb
->height
,
7269 crtc
->base
.primary
->fb
->bits_per_pixel
, base
,
7270 crtc
->base
.primary
->fb
->pitches
[0],
7271 plane_config
->size
);
7274 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
7275 struct intel_crtc_config
*pipe_config
)
7277 struct drm_device
*dev
= crtc
->base
.dev
;
7278 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7281 if (!intel_display_power_enabled(dev_priv
,
7282 POWER_DOMAIN_PIPE(crtc
->pipe
)))
7285 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
7286 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
7288 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
7289 if (!(tmp
& PIPECONF_ENABLE
))
7292 switch (tmp
& PIPECONF_BPC_MASK
) {
7294 pipe_config
->pipe_bpp
= 18;
7297 pipe_config
->pipe_bpp
= 24;
7299 case PIPECONF_10BPC
:
7300 pipe_config
->pipe_bpp
= 30;
7302 case PIPECONF_12BPC
:
7303 pipe_config
->pipe_bpp
= 36;
7309 if (tmp
& PIPECONF_COLOR_RANGE_SELECT
)
7310 pipe_config
->limited_color_range
= true;
7312 if (I915_READ(PCH_TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
) {
7313 struct intel_shared_dpll
*pll
;
7315 pipe_config
->has_pch_encoder
= true;
7317 tmp
= I915_READ(FDI_RX_CTL(crtc
->pipe
));
7318 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
7319 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
7321 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
7323 if (HAS_PCH_IBX(dev_priv
->dev
)) {
7324 pipe_config
->shared_dpll
=
7325 (enum intel_dpll_id
) crtc
->pipe
;
7327 tmp
= I915_READ(PCH_DPLL_SEL
);
7328 if (tmp
& TRANS_DPLLB_SEL(crtc
->pipe
))
7329 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_B
;
7331 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_A
;
7334 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
7336 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
7337 &pipe_config
->dpll_hw_state
));
7339 tmp
= pipe_config
->dpll_hw_state
.dpll
;
7340 pipe_config
->pixel_multiplier
=
7341 ((tmp
& PLL_REF_SDVO_HDMI_MULTIPLIER_MASK
)
7342 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
) + 1;
7344 ironlake_pch_clock_get(crtc
, pipe_config
);
7346 pipe_config
->pixel_multiplier
= 1;
7349 intel_get_pipe_timings(crtc
, pipe_config
);
7351 ironlake_get_pfit_config(crtc
, pipe_config
);
7356 static void assert_can_disable_lcpll(struct drm_i915_private
*dev_priv
)
7358 struct drm_device
*dev
= dev_priv
->dev
;
7359 struct intel_crtc
*crtc
;
7361 for_each_intel_crtc(dev
, crtc
)
7362 WARN(crtc
->active
, "CRTC for pipe %c enabled\n",
7363 pipe_name(crtc
->pipe
));
7365 WARN(I915_READ(HSW_PWR_WELL_DRIVER
), "Power well on\n");
7366 WARN(I915_READ(SPLL_CTL
) & SPLL_PLL_ENABLE
, "SPLL enabled\n");
7367 WARN(I915_READ(WRPLL_CTL1
) & WRPLL_PLL_ENABLE
, "WRPLL1 enabled\n");
7368 WARN(I915_READ(WRPLL_CTL2
) & WRPLL_PLL_ENABLE
, "WRPLL2 enabled\n");
7369 WARN(I915_READ(PCH_PP_STATUS
) & PP_ON
, "Panel power on\n");
7370 WARN(I915_READ(BLC_PWM_CPU_CTL2
) & BLM_PWM_ENABLE
,
7371 "CPU PWM1 enabled\n");
7372 if (IS_HASWELL(dev
))
7373 WARN(I915_READ(HSW_BLC_PWM2_CTL
) & BLM_PWM_ENABLE
,
7374 "CPU PWM2 enabled\n");
7375 WARN(I915_READ(BLC_PWM_PCH_CTL1
) & BLM_PCH_PWM_ENABLE
,
7376 "PCH PWM1 enabled\n");
7377 WARN(I915_READ(UTIL_PIN_CTL
) & UTIL_PIN_ENABLE
,
7378 "Utility pin enabled\n");
7379 WARN(I915_READ(PCH_GTC_CTL
) & PCH_GTC_ENABLE
, "PCH GTC enabled\n");
7382 * In theory we can still leave IRQs enabled, as long as only the HPD
7383 * interrupts remain enabled. We used to check for that, but since it's
7384 * gen-specific and since we only disable LCPLL after we fully disable
7385 * the interrupts, the check below should be enough.
7387 WARN(intel_irqs_enabled(dev_priv
), "IRQs enabled\n");
7390 static uint32_t hsw_read_dcomp(struct drm_i915_private
*dev_priv
)
7392 struct drm_device
*dev
= dev_priv
->dev
;
7394 if (IS_HASWELL(dev
))
7395 return I915_READ(D_COMP_HSW
);
7397 return I915_READ(D_COMP_BDW
);
7400 static void hsw_write_dcomp(struct drm_i915_private
*dev_priv
, uint32_t val
)
7402 struct drm_device
*dev
= dev_priv
->dev
;
7404 if (IS_HASWELL(dev
)) {
7405 mutex_lock(&dev_priv
->rps
.hw_lock
);
7406 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
,
7408 DRM_ERROR("Failed to write to D_COMP\n");
7409 mutex_unlock(&dev_priv
->rps
.hw_lock
);
7411 I915_WRITE(D_COMP_BDW
, val
);
7412 POSTING_READ(D_COMP_BDW
);
7417 * This function implements pieces of two sequences from BSpec:
7418 * - Sequence for display software to disable LCPLL
7419 * - Sequence for display software to allow package C8+
7420 * The steps implemented here are just the steps that actually touch the LCPLL
7421 * register. Callers should take care of disabling all the display engine
7422 * functions, doing the mode unset, fixing interrupts, etc.
7424 static void hsw_disable_lcpll(struct drm_i915_private
*dev_priv
,
7425 bool switch_to_fclk
, bool allow_power_down
)
7429 assert_can_disable_lcpll(dev_priv
);
7431 val
= I915_READ(LCPLL_CTL
);
7433 if (switch_to_fclk
) {
7434 val
|= LCPLL_CD_SOURCE_FCLK
;
7435 I915_WRITE(LCPLL_CTL
, val
);
7437 if (wait_for_atomic_us(I915_READ(LCPLL_CTL
) &
7438 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
7439 DRM_ERROR("Switching to FCLK failed\n");
7441 val
= I915_READ(LCPLL_CTL
);
7444 val
|= LCPLL_PLL_DISABLE
;
7445 I915_WRITE(LCPLL_CTL
, val
);
7446 POSTING_READ(LCPLL_CTL
);
7448 if (wait_for((I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
) == 0, 1))
7449 DRM_ERROR("LCPLL still locked\n");
7451 val
= hsw_read_dcomp(dev_priv
);
7452 val
|= D_COMP_COMP_DISABLE
;
7453 hsw_write_dcomp(dev_priv
, val
);
7456 if (wait_for((hsw_read_dcomp(dev_priv
) & D_COMP_RCOMP_IN_PROGRESS
) == 0,
7458 DRM_ERROR("D_COMP RCOMP still in progress\n");
7460 if (allow_power_down
) {
7461 val
= I915_READ(LCPLL_CTL
);
7462 val
|= LCPLL_POWER_DOWN_ALLOW
;
7463 I915_WRITE(LCPLL_CTL
, val
);
7464 POSTING_READ(LCPLL_CTL
);
7469 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7472 static void hsw_restore_lcpll(struct drm_i915_private
*dev_priv
)
7475 unsigned long irqflags
;
7477 val
= I915_READ(LCPLL_CTL
);
7479 if ((val
& (LCPLL_PLL_LOCK
| LCPLL_PLL_DISABLE
| LCPLL_CD_SOURCE_FCLK
|
7480 LCPLL_POWER_DOWN_ALLOW
)) == LCPLL_PLL_LOCK
)
7484 * Make sure we're not on PC8 state before disabling PC8, otherwise
7485 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7487 * The other problem is that hsw_restore_lcpll() is called as part of
7488 * the runtime PM resume sequence, so we can't just call
7489 * gen6_gt_force_wake_get() because that function calls
7490 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7491 * while we are on the resume sequence. So to solve this problem we have
7492 * to call special forcewake code that doesn't touch runtime PM and
7493 * doesn't enable the forcewake delayed work.
7495 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
7496 if (dev_priv
->uncore
.forcewake_count
++ == 0)
7497 dev_priv
->uncore
.funcs
.force_wake_get(dev_priv
, FORCEWAKE_ALL
);
7498 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
7500 if (val
& LCPLL_POWER_DOWN_ALLOW
) {
7501 val
&= ~LCPLL_POWER_DOWN_ALLOW
;
7502 I915_WRITE(LCPLL_CTL
, val
);
7503 POSTING_READ(LCPLL_CTL
);
7506 val
= hsw_read_dcomp(dev_priv
);
7507 val
|= D_COMP_COMP_FORCE
;
7508 val
&= ~D_COMP_COMP_DISABLE
;
7509 hsw_write_dcomp(dev_priv
, val
);
7511 val
= I915_READ(LCPLL_CTL
);
7512 val
&= ~LCPLL_PLL_DISABLE
;
7513 I915_WRITE(LCPLL_CTL
, val
);
7515 if (wait_for(I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
, 5))
7516 DRM_ERROR("LCPLL not locked yet\n");
7518 if (val
& LCPLL_CD_SOURCE_FCLK
) {
7519 val
= I915_READ(LCPLL_CTL
);
7520 val
&= ~LCPLL_CD_SOURCE_FCLK
;
7521 I915_WRITE(LCPLL_CTL
, val
);
7523 if (wait_for_atomic_us((I915_READ(LCPLL_CTL
) &
7524 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
7525 DRM_ERROR("Switching back to LCPLL failed\n");
7528 /* See the big comment above. */
7529 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
7530 if (--dev_priv
->uncore
.forcewake_count
== 0)
7531 dev_priv
->uncore
.funcs
.force_wake_put(dev_priv
, FORCEWAKE_ALL
);
7532 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
7536 * Package states C8 and deeper are really deep PC states that can only be
7537 * reached when all the devices on the system allow it, so even if the graphics
7538 * device allows PC8+, it doesn't mean the system will actually get to these
7539 * states. Our driver only allows PC8+ when going into runtime PM.
7541 * The requirements for PC8+ are that all the outputs are disabled, the power
7542 * well is disabled and most interrupts are disabled, and these are also
7543 * requirements for runtime PM. When these conditions are met, we manually do
7544 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7545 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7548 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7549 * the state of some registers, so when we come back from PC8+ we need to
7550 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7551 * need to take care of the registers kept by RC6. Notice that this happens even
7552 * if we don't put the device in PCI D3 state (which is what currently happens
7553 * because of the runtime PM support).
7555 * For more, read "Display Sequences for Package C8" on the hardware
7558 void hsw_enable_pc8(struct drm_i915_private
*dev_priv
)
7560 struct drm_device
*dev
= dev_priv
->dev
;
7563 DRM_DEBUG_KMS("Enabling package C8+\n");
7565 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
7566 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
7567 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
7568 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
7571 lpt_disable_clkout_dp(dev
);
7572 hsw_disable_lcpll(dev_priv
, true, true);
7575 void hsw_disable_pc8(struct drm_i915_private
*dev_priv
)
7577 struct drm_device
*dev
= dev_priv
->dev
;
7580 DRM_DEBUG_KMS("Disabling package C8+\n");
7582 hsw_restore_lcpll(dev_priv
);
7583 lpt_init_pch_refclk(dev
);
7585 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
7586 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
7587 val
|= PCH_LP_PARTITION_LEVEL_DISABLE
;
7588 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
7591 intel_prepare_ddi(dev
);
7594 static void snb_modeset_global_resources(struct drm_device
*dev
)
7596 modeset_update_crtc_power_domains(dev
);
7599 static void haswell_modeset_global_resources(struct drm_device
*dev
)
7601 modeset_update_crtc_power_domains(dev
);
7604 static int haswell_crtc_mode_set(struct drm_crtc
*crtc
,
7606 struct drm_framebuffer
*fb
)
7608 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7610 if (!intel_ddi_pll_select(intel_crtc
))
7613 intel_crtc
->lowfreq_avail
= false;
7618 static void haswell_get_ddi_port_state(struct intel_crtc
*crtc
,
7619 struct intel_crtc_config
*pipe_config
)
7621 struct drm_device
*dev
= crtc
->base
.dev
;
7622 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7623 struct intel_shared_dpll
*pll
;
7627 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
7629 port
= (tmp
& TRANS_DDI_PORT_MASK
) >> TRANS_DDI_PORT_SHIFT
;
7631 pipe_config
->ddi_pll_sel
= I915_READ(PORT_CLK_SEL(port
));
7633 switch (pipe_config
->ddi_pll_sel
) {
7634 case PORT_CLK_SEL_WRPLL1
:
7635 pipe_config
->shared_dpll
= DPLL_ID_WRPLL1
;
7637 case PORT_CLK_SEL_WRPLL2
:
7638 pipe_config
->shared_dpll
= DPLL_ID_WRPLL2
;
7642 if (pipe_config
->shared_dpll
>= 0) {
7643 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
7645 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
7646 &pipe_config
->dpll_hw_state
));
7650 * Haswell has only FDI/PCH transcoder A. It is which is connected to
7651 * DDI E. So just check whether this pipe is wired to DDI E and whether
7652 * the PCH transcoder is on.
7654 if ((port
== PORT_E
) && I915_READ(LPT_TRANSCONF
) & TRANS_ENABLE
) {
7655 pipe_config
->has_pch_encoder
= true;
7657 tmp
= I915_READ(FDI_RX_CTL(PIPE_A
));
7658 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
7659 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
7661 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
7665 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
7666 struct intel_crtc_config
*pipe_config
)
7668 struct drm_device
*dev
= crtc
->base
.dev
;
7669 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7670 enum intel_display_power_domain pfit_domain
;
7673 if (!intel_display_power_enabled(dev_priv
,
7674 POWER_DOMAIN_PIPE(crtc
->pipe
)))
7677 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
7678 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
7680 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
7681 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
7682 enum pipe trans_edp_pipe
;
7683 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
7685 WARN(1, "unknown pipe linked to edp transcoder\n");
7686 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
7687 case TRANS_DDI_EDP_INPUT_A_ON
:
7688 trans_edp_pipe
= PIPE_A
;
7690 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
7691 trans_edp_pipe
= PIPE_B
;
7693 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
7694 trans_edp_pipe
= PIPE_C
;
7698 if (trans_edp_pipe
== crtc
->pipe
)
7699 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
7702 if (!intel_display_power_enabled(dev_priv
,
7703 POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
)))
7706 tmp
= I915_READ(PIPECONF(pipe_config
->cpu_transcoder
));
7707 if (!(tmp
& PIPECONF_ENABLE
))
7710 haswell_get_ddi_port_state(crtc
, pipe_config
);
7712 intel_get_pipe_timings(crtc
, pipe_config
);
7714 pfit_domain
= POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
);
7715 if (intel_display_power_enabled(dev_priv
, pfit_domain
))
7716 ironlake_get_pfit_config(crtc
, pipe_config
);
7718 if (IS_HASWELL(dev
))
7719 pipe_config
->ips_enabled
= hsw_crtc_supports_ips(crtc
) &&
7720 (I915_READ(IPS_CTL
) & IPS_ENABLE
);
7722 pipe_config
->pixel_multiplier
= 1;
7730 } hdmi_audio_clock
[] = {
7731 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175
},
7732 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200
}, /* default per bspec */
7733 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000
},
7734 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027
},
7735 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000
},
7736 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054
},
7737 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176
},
7738 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250
},
7739 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352
},
7740 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500
},
7743 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7744 static u32
audio_config_hdmi_pixel_clock(struct drm_display_mode
*mode
)
7748 for (i
= 0; i
< ARRAY_SIZE(hdmi_audio_clock
); i
++) {
7749 if (mode
->clock
== hdmi_audio_clock
[i
].clock
)
7753 if (i
== ARRAY_SIZE(hdmi_audio_clock
)) {
7754 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode
->clock
);
7758 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7759 hdmi_audio_clock
[i
].clock
,
7760 hdmi_audio_clock
[i
].config
);
7762 return hdmi_audio_clock
[i
].config
;
7765 static bool intel_eld_uptodate(struct drm_connector
*connector
,
7766 int reg_eldv
, uint32_t bits_eldv
,
7767 int reg_elda
, uint32_t bits_elda
,
7770 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
7771 uint8_t *eld
= connector
->eld
;
7774 i
= I915_READ(reg_eldv
);
7783 i
= I915_READ(reg_elda
);
7785 I915_WRITE(reg_elda
, i
);
7787 for (i
= 0; i
< eld
[2]; i
++)
7788 if (I915_READ(reg_edid
) != *((uint32_t *)eld
+ i
))
7794 static void g4x_write_eld(struct drm_connector
*connector
,
7795 struct drm_crtc
*crtc
,
7796 struct drm_display_mode
*mode
)
7798 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
7799 uint8_t *eld
= connector
->eld
;
7804 i
= I915_READ(G4X_AUD_VID_DID
);
7806 if (i
== INTEL_AUDIO_DEVBLC
|| i
== INTEL_AUDIO_DEVCL
)
7807 eldv
= G4X_ELDV_DEVCL_DEVBLC
;
7809 eldv
= G4X_ELDV_DEVCTG
;
7811 if (intel_eld_uptodate(connector
,
7812 G4X_AUD_CNTL_ST
, eldv
,
7813 G4X_AUD_CNTL_ST
, G4X_ELD_ADDR
,
7814 G4X_HDMIW_HDMIEDID
))
7817 i
= I915_READ(G4X_AUD_CNTL_ST
);
7818 i
&= ~(eldv
| G4X_ELD_ADDR
);
7819 len
= (i
>> 9) & 0x1f; /* ELD buffer size */
7820 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
7825 len
= min_t(uint8_t, eld
[2], len
);
7826 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
7827 for (i
= 0; i
< len
; i
++)
7828 I915_WRITE(G4X_HDMIW_HDMIEDID
, *((uint32_t *)eld
+ i
));
7830 i
= I915_READ(G4X_AUD_CNTL_ST
);
7832 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
7835 static void haswell_write_eld(struct drm_connector
*connector
,
7836 struct drm_crtc
*crtc
,
7837 struct drm_display_mode
*mode
)
7839 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
7840 uint8_t *eld
= connector
->eld
;
7844 int pipe
= to_intel_crtc(crtc
)->pipe
;
7847 int hdmiw_hdmiedid
= HSW_AUD_EDID_DATA(pipe
);
7848 int aud_cntl_st
= HSW_AUD_DIP_ELD_CTRL(pipe
);
7849 int aud_config
= HSW_AUD_CFG(pipe
);
7850 int aud_cntrl_st2
= HSW_AUD_PIN_ELD_CP_VLD
;
7852 /* Audio output enable */
7853 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7854 tmp
= I915_READ(aud_cntrl_st2
);
7855 tmp
|= (AUDIO_OUTPUT_ENABLE_A
<< (pipe
* 4));
7856 I915_WRITE(aud_cntrl_st2
, tmp
);
7857 POSTING_READ(aud_cntrl_st2
);
7859 assert_pipe_disabled(dev_priv
, to_intel_crtc(crtc
)->pipe
);
7861 /* Set ELD valid state */
7862 tmp
= I915_READ(aud_cntrl_st2
);
7863 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp
);
7864 tmp
|= (AUDIO_ELD_VALID_A
<< (pipe
* 4));
7865 I915_WRITE(aud_cntrl_st2
, tmp
);
7866 tmp
= I915_READ(aud_cntrl_st2
);
7867 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp
);
7869 /* Enable HDMI mode */
7870 tmp
= I915_READ(aud_config
);
7871 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp
);
7872 /* clear N_programing_enable and N_value_index */
7873 tmp
&= ~(AUD_CONFIG_N_VALUE_INDEX
| AUD_CONFIG_N_PROG_ENABLE
);
7874 I915_WRITE(aud_config
, tmp
);
7876 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
7878 eldv
= AUDIO_ELD_VALID_A
<< (pipe
* 4);
7880 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
7881 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7882 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7883 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
7885 I915_WRITE(aud_config
, audio_config_hdmi_pixel_clock(mode
));
7888 if (intel_eld_uptodate(connector
,
7889 aud_cntrl_st2
, eldv
,
7890 aud_cntl_st
, IBX_ELD_ADDRESS
,
7894 i
= I915_READ(aud_cntrl_st2
);
7896 I915_WRITE(aud_cntrl_st2
, i
);
7901 i
= I915_READ(aud_cntl_st
);
7902 i
&= ~IBX_ELD_ADDRESS
;
7903 I915_WRITE(aud_cntl_st
, i
);
7904 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
7905 DRM_DEBUG_DRIVER("port num:%d\n", i
);
7907 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
7908 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
7909 for (i
= 0; i
< len
; i
++)
7910 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
7912 i
= I915_READ(aud_cntrl_st2
);
7914 I915_WRITE(aud_cntrl_st2
, i
);
7918 static void ironlake_write_eld(struct drm_connector
*connector
,
7919 struct drm_crtc
*crtc
,
7920 struct drm_display_mode
*mode
)
7922 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
7923 uint8_t *eld
= connector
->eld
;
7931 int pipe
= to_intel_crtc(crtc
)->pipe
;
7933 if (HAS_PCH_IBX(connector
->dev
)) {
7934 hdmiw_hdmiedid
= IBX_HDMIW_HDMIEDID(pipe
);
7935 aud_config
= IBX_AUD_CFG(pipe
);
7936 aud_cntl_st
= IBX_AUD_CNTL_ST(pipe
);
7937 aud_cntrl_st2
= IBX_AUD_CNTL_ST2
;
7938 } else if (IS_VALLEYVIEW(connector
->dev
)) {
7939 hdmiw_hdmiedid
= VLV_HDMIW_HDMIEDID(pipe
);
7940 aud_config
= VLV_AUD_CFG(pipe
);
7941 aud_cntl_st
= VLV_AUD_CNTL_ST(pipe
);
7942 aud_cntrl_st2
= VLV_AUD_CNTL_ST2
;
7944 hdmiw_hdmiedid
= CPT_HDMIW_HDMIEDID(pipe
);
7945 aud_config
= CPT_AUD_CFG(pipe
);
7946 aud_cntl_st
= CPT_AUD_CNTL_ST(pipe
);
7947 aud_cntrl_st2
= CPT_AUD_CNTRL_ST2
;
7950 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
7952 if (IS_VALLEYVIEW(connector
->dev
)) {
7953 struct intel_encoder
*intel_encoder
;
7954 struct intel_digital_port
*intel_dig_port
;
7956 intel_encoder
= intel_attached_encoder(connector
);
7957 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
7958 i
= intel_dig_port
->port
;
7960 i
= I915_READ(aud_cntl_st
);
7961 i
= (i
>> 29) & DIP_PORT_SEL_MASK
;
7962 /* DIP_Port_Select, 0x1 = PortB */
7966 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7967 /* operate blindly on all ports */
7968 eldv
= IBX_ELD_VALIDB
;
7969 eldv
|= IBX_ELD_VALIDB
<< 4;
7970 eldv
|= IBX_ELD_VALIDB
<< 8;
7972 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i
));
7973 eldv
= IBX_ELD_VALIDB
<< ((i
- 1) * 4);
7976 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
7977 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7978 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7979 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
7981 I915_WRITE(aud_config
, audio_config_hdmi_pixel_clock(mode
));
7984 if (intel_eld_uptodate(connector
,
7985 aud_cntrl_st2
, eldv
,
7986 aud_cntl_st
, IBX_ELD_ADDRESS
,
7990 i
= I915_READ(aud_cntrl_st2
);
7992 I915_WRITE(aud_cntrl_st2
, i
);
7997 i
= I915_READ(aud_cntl_st
);
7998 i
&= ~IBX_ELD_ADDRESS
;
7999 I915_WRITE(aud_cntl_st
, i
);
8001 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
8002 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
8003 for (i
= 0; i
< len
; i
++)
8004 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
8006 i
= I915_READ(aud_cntrl_st2
);
8008 I915_WRITE(aud_cntrl_st2
, i
);
8011 void intel_write_eld(struct drm_encoder
*encoder
,
8012 struct drm_display_mode
*mode
)
8014 struct drm_crtc
*crtc
= encoder
->crtc
;
8015 struct drm_connector
*connector
;
8016 struct drm_device
*dev
= encoder
->dev
;
8017 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8019 connector
= drm_select_eld(encoder
, mode
);
8023 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8026 connector
->encoder
->base
.id
,
8027 connector
->encoder
->name
);
8029 connector
->eld
[6] = drm_av_sync_delay(connector
, mode
) / 2;
8031 if (dev_priv
->display
.write_eld
)
8032 dev_priv
->display
.write_eld(connector
, crtc
, mode
);
8035 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
8037 struct drm_device
*dev
= crtc
->dev
;
8038 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8039 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8042 if (base
!= intel_crtc
->cursor_base
) {
8043 /* On these chipsets we can only modify the base whilst
8044 * the cursor is disabled.
8046 if (intel_crtc
->cursor_cntl
) {
8047 I915_WRITE(_CURACNTR
, 0);
8048 POSTING_READ(_CURACNTR
);
8049 intel_crtc
->cursor_cntl
= 0;
8052 I915_WRITE(_CURABASE
, base
);
8053 POSTING_READ(_CURABASE
);
8056 /* XXX width must be 64, stride 256 => 0x00 << 28 */
8059 cntl
= (CURSOR_ENABLE
|
8060 CURSOR_GAMMA_ENABLE
|
8061 CURSOR_FORMAT_ARGB
);
8062 if (intel_crtc
->cursor_cntl
!= cntl
) {
8063 I915_WRITE(_CURACNTR
, cntl
);
8064 POSTING_READ(_CURACNTR
);
8065 intel_crtc
->cursor_cntl
= cntl
;
8069 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
8071 struct drm_device
*dev
= crtc
->dev
;
8072 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8073 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8074 int pipe
= intel_crtc
->pipe
;
8079 cntl
= MCURSOR_GAMMA_ENABLE
;
8080 switch (intel_crtc
->cursor_width
) {
8082 cntl
|= CURSOR_MODE_64_ARGB_AX
;
8085 cntl
|= CURSOR_MODE_128_ARGB_AX
;
8088 cntl
|= CURSOR_MODE_256_ARGB_AX
;
8094 cntl
|= pipe
<< 28; /* Connect to correct pipe */
8096 if (intel_crtc
->cursor_cntl
!= cntl
) {
8097 I915_WRITE(CURCNTR(pipe
), cntl
);
8098 POSTING_READ(CURCNTR(pipe
));
8099 intel_crtc
->cursor_cntl
= cntl
;
8102 /* and commit changes on next vblank */
8103 I915_WRITE(CURBASE(pipe
), base
);
8104 POSTING_READ(CURBASE(pipe
));
8107 static void ivb_update_cursor(struct drm_crtc
*crtc
, u32 base
)
8109 struct drm_device
*dev
= crtc
->dev
;
8110 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8111 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8112 int pipe
= intel_crtc
->pipe
;
8117 cntl
= MCURSOR_GAMMA_ENABLE
;
8118 switch (intel_crtc
->cursor_width
) {
8120 cntl
|= CURSOR_MODE_64_ARGB_AX
;
8123 cntl
|= CURSOR_MODE_128_ARGB_AX
;
8126 cntl
|= CURSOR_MODE_256_ARGB_AX
;
8133 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
8134 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
8136 if (intel_crtc
->cursor_cntl
!= cntl
) {
8137 I915_WRITE(CURCNTR(pipe
), cntl
);
8138 POSTING_READ(CURCNTR(pipe
));
8139 intel_crtc
->cursor_cntl
= cntl
;
8142 /* and commit changes on next vblank */
8143 I915_WRITE(CURBASE(pipe
), base
);
8144 POSTING_READ(CURBASE(pipe
));
8147 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8148 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
8151 struct drm_device
*dev
= crtc
->dev
;
8152 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8153 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8154 int pipe
= intel_crtc
->pipe
;
8155 int x
= crtc
->cursor_x
;
8156 int y
= crtc
->cursor_y
;
8157 u32 base
= 0, pos
= 0;
8160 base
= intel_crtc
->cursor_addr
;
8162 if (x
>= intel_crtc
->config
.pipe_src_w
)
8165 if (y
>= intel_crtc
->config
.pipe_src_h
)
8169 if (x
+ intel_crtc
->cursor_width
<= 0)
8172 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
8175 pos
|= x
<< CURSOR_X_SHIFT
;
8178 if (y
+ intel_crtc
->cursor_height
<= 0)
8181 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
8184 pos
|= y
<< CURSOR_Y_SHIFT
;
8186 if (base
== 0 && intel_crtc
->cursor_base
== 0)
8189 I915_WRITE(CURPOS(pipe
), pos
);
8191 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
) || IS_BROADWELL(dev
))
8192 ivb_update_cursor(crtc
, base
);
8193 else if (IS_845G(dev
) || IS_I865G(dev
))
8194 i845_update_cursor(crtc
, base
);
8196 i9xx_update_cursor(crtc
, base
);
8197 intel_crtc
->cursor_base
= base
;
8201 * intel_crtc_cursor_set_obj - Set cursor to specified GEM object
8203 * Note that the object's reference will be consumed if the update fails. If
8204 * the update succeeds, the reference of the old object (if any) will be
8207 static int intel_crtc_cursor_set_obj(struct drm_crtc
*crtc
,
8208 struct drm_i915_gem_object
*obj
,
8209 uint32_t width
, uint32_t height
)
8211 struct drm_device
*dev
= crtc
->dev
;
8212 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8213 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8214 enum pipe pipe
= intel_crtc
->pipe
;
8219 /* if we want to turn off the cursor ignore width and height */
8221 DRM_DEBUG_KMS("cursor off\n");
8224 mutex_lock(&dev
->struct_mutex
);
8228 /* Check for which cursor types we support */
8229 if (!((width
== 64 && height
== 64) ||
8230 (width
== 128 && height
== 128 && !IS_GEN2(dev
)) ||
8231 (width
== 256 && height
== 256 && !IS_GEN2(dev
)))) {
8232 DRM_DEBUG("Cursor dimension not supported\n");
8236 if (obj
->base
.size
< width
* height
* 4) {
8237 DRM_DEBUG_KMS("buffer is too small\n");
8242 /* we only need to pin inside GTT if cursor is non-phy */
8243 mutex_lock(&dev
->struct_mutex
);
8244 if (!INTEL_INFO(dev
)->cursor_needs_physical
) {
8247 if (obj
->tiling_mode
) {
8248 DRM_DEBUG_KMS("cursor cannot be tiled\n");
8254 * Global gtt pte registers are special registers which actually
8255 * forward writes to a chunk of system memory. Which means that
8256 * there is no risk that the register values disappear as soon
8257 * as we call intel_runtime_pm_put(), so it is correct to wrap
8258 * only the pin/unpin/fence and not more.
8260 intel_runtime_pm_get(dev_priv
);
8262 /* Note that the w/a also requires 2 PTE of padding following
8263 * the bo. We currently fill all unused PTE with the shadow
8264 * page and so we should always have valid PTE following the
8265 * cursor preventing the VT-d warning.
8268 if (need_vtd_wa(dev
))
8269 alignment
= 64*1024;
8271 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, NULL
);
8273 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8274 intel_runtime_pm_put(dev_priv
);
8278 ret
= i915_gem_object_put_fence(obj
);
8280 DRM_DEBUG_KMS("failed to release fence for cursor");
8281 intel_runtime_pm_put(dev_priv
);
8285 addr
= i915_gem_obj_ggtt_offset(obj
);
8287 intel_runtime_pm_put(dev_priv
);
8289 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
8290 ret
= i915_gem_object_attach_phys(obj
, align
);
8292 DRM_DEBUG_KMS("failed to attach phys object\n");
8295 addr
= obj
->phys_handle
->busaddr
;
8299 I915_WRITE(CURSIZE
, (height
<< 12) | width
);
8302 if (intel_crtc
->cursor_bo
) {
8303 if (!INTEL_INFO(dev
)->cursor_needs_physical
)
8304 i915_gem_object_unpin_from_display_plane(intel_crtc
->cursor_bo
);
8307 i915_gem_track_fb(intel_crtc
->cursor_bo
, obj
,
8308 INTEL_FRONTBUFFER_CURSOR(pipe
));
8309 mutex_unlock(&dev
->struct_mutex
);
8311 old_width
= intel_crtc
->cursor_width
;
8313 intel_crtc
->cursor_addr
= addr
;
8314 intel_crtc
->cursor_bo
= obj
;
8315 intel_crtc
->cursor_width
= width
;
8316 intel_crtc
->cursor_height
= height
;
8318 if (intel_crtc
->active
) {
8319 if (old_width
!= width
)
8320 intel_update_watermarks(crtc
);
8321 intel_crtc_update_cursor(crtc
, intel_crtc
->cursor_bo
!= NULL
);
8324 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_CURSOR(pipe
));
8328 i915_gem_object_unpin_from_display_plane(obj
);
8330 mutex_unlock(&dev
->struct_mutex
);
8332 drm_gem_object_unreference_unlocked(&obj
->base
);
8336 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
8337 u16
*blue
, uint32_t start
, uint32_t size
)
8339 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
8340 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8342 for (i
= start
; i
< end
; i
++) {
8343 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
8344 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
8345 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
8348 intel_crtc_load_lut(crtc
);
8351 /* VESA 640x480x72Hz mode to set on the pipe */
8352 static struct drm_display_mode load_detect_mode
= {
8353 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
8354 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
8357 struct drm_framebuffer
*
8358 __intel_framebuffer_create(struct drm_device
*dev
,
8359 struct drm_mode_fb_cmd2
*mode_cmd
,
8360 struct drm_i915_gem_object
*obj
)
8362 struct intel_framebuffer
*intel_fb
;
8365 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
8367 drm_gem_object_unreference_unlocked(&obj
->base
);
8368 return ERR_PTR(-ENOMEM
);
8371 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
8375 return &intel_fb
->base
;
8377 drm_gem_object_unreference_unlocked(&obj
->base
);
8380 return ERR_PTR(ret
);
8383 static struct drm_framebuffer
*
8384 intel_framebuffer_create(struct drm_device
*dev
,
8385 struct drm_mode_fb_cmd2
*mode_cmd
,
8386 struct drm_i915_gem_object
*obj
)
8388 struct drm_framebuffer
*fb
;
8391 ret
= i915_mutex_lock_interruptible(dev
);
8393 return ERR_PTR(ret
);
8394 fb
= __intel_framebuffer_create(dev
, mode_cmd
, obj
);
8395 mutex_unlock(&dev
->struct_mutex
);
8401 intel_framebuffer_pitch_for_width(int width
, int bpp
)
8403 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
8404 return ALIGN(pitch
, 64);
8408 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
8410 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
8411 return PAGE_ALIGN(pitch
* mode
->vdisplay
);
8414 static struct drm_framebuffer
*
8415 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
8416 struct drm_display_mode
*mode
,
8419 struct drm_i915_gem_object
*obj
;
8420 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
8422 obj
= i915_gem_alloc_object(dev
,
8423 intel_framebuffer_size_for_mode(mode
, bpp
));
8425 return ERR_PTR(-ENOMEM
);
8427 mode_cmd
.width
= mode
->hdisplay
;
8428 mode_cmd
.height
= mode
->vdisplay
;
8429 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
8431 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
8433 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
8436 static struct drm_framebuffer
*
8437 mode_fits_in_fbdev(struct drm_device
*dev
,
8438 struct drm_display_mode
*mode
)
8440 #ifdef CONFIG_DRM_I915_FBDEV
8441 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8442 struct drm_i915_gem_object
*obj
;
8443 struct drm_framebuffer
*fb
;
8445 if (!dev_priv
->fbdev
)
8448 if (!dev_priv
->fbdev
->fb
)
8451 obj
= dev_priv
->fbdev
->fb
->obj
;
8454 fb
= &dev_priv
->fbdev
->fb
->base
;
8455 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
8456 fb
->bits_per_pixel
))
8459 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
8468 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
8469 struct drm_display_mode
*mode
,
8470 struct intel_load_detect_pipe
*old
,
8471 struct drm_modeset_acquire_ctx
*ctx
)
8473 struct intel_crtc
*intel_crtc
;
8474 struct intel_encoder
*intel_encoder
=
8475 intel_attached_encoder(connector
);
8476 struct drm_crtc
*possible_crtc
;
8477 struct drm_encoder
*encoder
= &intel_encoder
->base
;
8478 struct drm_crtc
*crtc
= NULL
;
8479 struct drm_device
*dev
= encoder
->dev
;
8480 struct drm_framebuffer
*fb
;
8481 struct drm_mode_config
*config
= &dev
->mode_config
;
8484 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8485 connector
->base
.id
, connector
->name
,
8486 encoder
->base
.id
, encoder
->name
);
8489 ret
= drm_modeset_lock(&config
->connection_mutex
, ctx
);
8494 * Algorithm gets a little messy:
8496 * - if the connector already has an assigned crtc, use it (but make
8497 * sure it's on first)
8499 * - try to find the first unused crtc that can drive this connector,
8500 * and use that if we find one
8503 /* See if we already have a CRTC for this connector */
8504 if (encoder
->crtc
) {
8505 crtc
= encoder
->crtc
;
8507 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
8511 old
->dpms_mode
= connector
->dpms
;
8512 old
->load_detect_temp
= false;
8514 /* Make sure the crtc and connector are running */
8515 if (connector
->dpms
!= DRM_MODE_DPMS_ON
)
8516 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
8521 /* Find an unused one (if possible) */
8522 for_each_crtc(dev
, possible_crtc
) {
8524 if (!(encoder
->possible_crtcs
& (1 << i
)))
8526 if (possible_crtc
->enabled
)
8528 /* This can occur when applying the pipe A quirk on resume. */
8529 if (to_intel_crtc(possible_crtc
)->new_enabled
)
8532 crtc
= possible_crtc
;
8537 * If we didn't find an unused CRTC, don't use any.
8540 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8544 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
8547 intel_encoder
->new_crtc
= to_intel_crtc(crtc
);
8548 to_intel_connector(connector
)->new_encoder
= intel_encoder
;
8550 intel_crtc
= to_intel_crtc(crtc
);
8551 intel_crtc
->new_enabled
= true;
8552 intel_crtc
->new_config
= &intel_crtc
->config
;
8553 old
->dpms_mode
= connector
->dpms
;
8554 old
->load_detect_temp
= true;
8555 old
->release_fb
= NULL
;
8558 mode
= &load_detect_mode
;
8560 /* We need a framebuffer large enough to accommodate all accesses
8561 * that the plane may generate whilst we perform load detection.
8562 * We can not rely on the fbcon either being present (we get called
8563 * during its initialisation to detect all boot displays, or it may
8564 * not even exist) or that it is large enough to satisfy the
8567 fb
= mode_fits_in_fbdev(dev
, mode
);
8569 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8570 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
8571 old
->release_fb
= fb
;
8573 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8575 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8579 if (intel_set_mode(crtc
, mode
, 0, 0, fb
)) {
8580 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8581 if (old
->release_fb
)
8582 old
->release_fb
->funcs
->destroy(old
->release_fb
);
8586 /* let the connector get through one full cycle before testing */
8587 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
8591 intel_crtc
->new_enabled
= crtc
->enabled
;
8592 if (intel_crtc
->new_enabled
)
8593 intel_crtc
->new_config
= &intel_crtc
->config
;
8595 intel_crtc
->new_config
= NULL
;
8597 if (ret
== -EDEADLK
) {
8598 drm_modeset_backoff(ctx
);
8605 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
8606 struct intel_load_detect_pipe
*old
)
8608 struct intel_encoder
*intel_encoder
=
8609 intel_attached_encoder(connector
);
8610 struct drm_encoder
*encoder
= &intel_encoder
->base
;
8611 struct drm_crtc
*crtc
= encoder
->crtc
;
8612 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8614 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8615 connector
->base
.id
, connector
->name
,
8616 encoder
->base
.id
, encoder
->name
);
8618 if (old
->load_detect_temp
) {
8619 to_intel_connector(connector
)->new_encoder
= NULL
;
8620 intel_encoder
->new_crtc
= NULL
;
8621 intel_crtc
->new_enabled
= false;
8622 intel_crtc
->new_config
= NULL
;
8623 intel_set_mode(crtc
, NULL
, 0, 0, NULL
);
8625 if (old
->release_fb
) {
8626 drm_framebuffer_unregister_private(old
->release_fb
);
8627 drm_framebuffer_unreference(old
->release_fb
);
8633 /* Switch crtc and encoder back off if necessary */
8634 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
)
8635 connector
->funcs
->dpms(connector
, old
->dpms_mode
);
8638 static int i9xx_pll_refclk(struct drm_device
*dev
,
8639 const struct intel_crtc_config
*pipe_config
)
8641 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8642 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
8644 if ((dpll
& PLL_REF_INPUT_MASK
) == PLLB_REF_INPUT_SPREADSPECTRUMIN
)
8645 return dev_priv
->vbt
.lvds_ssc_freq
;
8646 else if (HAS_PCH_SPLIT(dev
))
8648 else if (!IS_GEN2(dev
))
8654 /* Returns the clock of the currently programmed mode of the given pipe. */
8655 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
8656 struct intel_crtc_config
*pipe_config
)
8658 struct drm_device
*dev
= crtc
->base
.dev
;
8659 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8660 int pipe
= pipe_config
->cpu_transcoder
;
8661 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
8663 intel_clock_t clock
;
8664 int refclk
= i9xx_pll_refclk(dev
, pipe_config
);
8666 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
8667 fp
= pipe_config
->dpll_hw_state
.fp0
;
8669 fp
= pipe_config
->dpll_hw_state
.fp1
;
8671 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
8672 if (IS_PINEVIEW(dev
)) {
8673 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
8674 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
8676 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
8677 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
8680 if (!IS_GEN2(dev
)) {
8681 if (IS_PINEVIEW(dev
))
8682 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
8683 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
8685 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
8686 DPLL_FPA01_P1_POST_DIV_SHIFT
);
8688 switch (dpll
& DPLL_MODE_MASK
) {
8689 case DPLLB_MODE_DAC_SERIAL
:
8690 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
8693 case DPLLB_MODE_LVDS
:
8694 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
8698 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8699 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
8703 if (IS_PINEVIEW(dev
))
8704 pineview_clock(refclk
, &clock
);
8706 i9xx_clock(refclk
, &clock
);
8708 u32 lvds
= IS_I830(dev
) ? 0 : I915_READ(LVDS
);
8709 bool is_lvds
= (pipe
== 1) && (lvds
& LVDS_PORT_EN
);
8712 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
8713 DPLL_FPA01_P1_POST_DIV_SHIFT
);
8715 if (lvds
& LVDS_CLKB_POWER_UP
)
8720 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
8723 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
8724 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
8726 if (dpll
& PLL_P2_DIVIDE_BY_4
)
8732 i9xx_clock(refclk
, &clock
);
8736 * This value includes pixel_multiplier. We will use
8737 * port_clock to compute adjusted_mode.crtc_clock in the
8738 * encoder's get_config() function.
8740 pipe_config
->port_clock
= clock
.dot
;
8743 int intel_dotclock_calculate(int link_freq
,
8744 const struct intel_link_m_n
*m_n
)
8747 * The calculation for the data clock is:
8748 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8749 * But we want to avoid losing precison if possible, so:
8750 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8752 * and the link clock is simpler:
8753 * link_clock = (m * link_clock) / n
8759 return div_u64((u64
)m_n
->link_m
* link_freq
, m_n
->link_n
);
8762 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
8763 struct intel_crtc_config
*pipe_config
)
8765 struct drm_device
*dev
= crtc
->base
.dev
;
8767 /* read out port_clock from the DPLL */
8768 i9xx_crtc_clock_get(crtc
, pipe_config
);
8771 * This value does not include pixel_multiplier.
8772 * We will check that port_clock and adjusted_mode.crtc_clock
8773 * agree once we know their relationship in the encoder's
8774 * get_config() function.
8776 pipe_config
->adjusted_mode
.crtc_clock
=
8777 intel_dotclock_calculate(intel_fdi_link_freq(dev
) * 10000,
8778 &pipe_config
->fdi_m_n
);
8781 /** Returns the currently programmed mode of the given pipe. */
8782 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
8783 struct drm_crtc
*crtc
)
8785 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8786 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8787 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
8788 struct drm_display_mode
*mode
;
8789 struct intel_crtc_config pipe_config
;
8790 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
8791 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
8792 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
8793 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
8794 enum pipe pipe
= intel_crtc
->pipe
;
8796 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
8801 * Construct a pipe_config sufficient for getting the clock info
8802 * back out of crtc_clock_get.
8804 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8805 * to use a real value here instead.
8807 pipe_config
.cpu_transcoder
= (enum transcoder
) pipe
;
8808 pipe_config
.pixel_multiplier
= 1;
8809 pipe_config
.dpll_hw_state
.dpll
= I915_READ(DPLL(pipe
));
8810 pipe_config
.dpll_hw_state
.fp0
= I915_READ(FP0(pipe
));
8811 pipe_config
.dpll_hw_state
.fp1
= I915_READ(FP1(pipe
));
8812 i9xx_crtc_clock_get(intel_crtc
, &pipe_config
);
8814 mode
->clock
= pipe_config
.port_clock
/ pipe_config
.pixel_multiplier
;
8815 mode
->hdisplay
= (htot
& 0xffff) + 1;
8816 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
8817 mode
->hsync_start
= (hsync
& 0xffff) + 1;
8818 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
8819 mode
->vdisplay
= (vtot
& 0xffff) + 1;
8820 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
8821 mode
->vsync_start
= (vsync
& 0xffff) + 1;
8822 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
8824 drm_mode_set_name(mode
);
8829 static void intel_increase_pllclock(struct drm_device
*dev
,
8832 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8833 int dpll_reg
= DPLL(pipe
);
8836 if (!HAS_GMCH_DISPLAY(dev
))
8839 if (!dev_priv
->lvds_downclock_avail
)
8842 dpll
= I915_READ(dpll_reg
);
8843 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
8844 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8846 assert_panel_unlocked(dev_priv
, pipe
);
8848 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
8849 I915_WRITE(dpll_reg
, dpll
);
8850 intel_wait_for_vblank(dev
, pipe
);
8852 dpll
= I915_READ(dpll_reg
);
8853 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
8854 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8858 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
8860 struct drm_device
*dev
= crtc
->dev
;
8861 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8862 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8864 if (!HAS_GMCH_DISPLAY(dev
))
8867 if (!dev_priv
->lvds_downclock_avail
)
8871 * Since this is called by a timer, we should never get here in
8874 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
8875 int pipe
= intel_crtc
->pipe
;
8876 int dpll_reg
= DPLL(pipe
);
8879 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8881 assert_panel_unlocked(dev_priv
, pipe
);
8883 dpll
= I915_READ(dpll_reg
);
8884 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
8885 I915_WRITE(dpll_reg
, dpll
);
8886 intel_wait_for_vblank(dev
, pipe
);
8887 dpll
= I915_READ(dpll_reg
);
8888 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
8889 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8894 void intel_mark_busy(struct drm_device
*dev
)
8896 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8898 if (dev_priv
->mm
.busy
)
8901 intel_runtime_pm_get(dev_priv
);
8902 i915_update_gfx_val(dev_priv
);
8903 dev_priv
->mm
.busy
= true;
8906 void intel_mark_idle(struct drm_device
*dev
)
8908 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8909 struct drm_crtc
*crtc
;
8911 if (!dev_priv
->mm
.busy
)
8914 dev_priv
->mm
.busy
= false;
8916 if (!i915
.powersave
)
8919 for_each_crtc(dev
, crtc
) {
8920 if (!crtc
->primary
->fb
)
8923 intel_decrease_pllclock(crtc
);
8926 if (INTEL_INFO(dev
)->gen
>= 6)
8927 gen6_rps_idle(dev
->dev_private
);
8930 intel_runtime_pm_put(dev_priv
);
8935 * intel_mark_fb_busy - mark given planes as busy
8937 * @frontbuffer_bits: bits for the affected planes
8938 * @ring: optional ring for asynchronous commands
8940 * This function gets called every time the screen contents change. It can be
8941 * used to keep e.g. the update rate at the nominal refresh rate with DRRS.
8943 static void intel_mark_fb_busy(struct drm_device
*dev
,
8944 unsigned frontbuffer_bits
,
8945 struct intel_engine_cs
*ring
)
8949 if (!i915
.powersave
)
8952 for_each_pipe(pipe
) {
8953 if (!(frontbuffer_bits
& INTEL_FRONTBUFFER_ALL_MASK(pipe
)))
8956 intel_increase_pllclock(dev
, pipe
);
8957 if (ring
&& intel_fbc_enabled(dev
))
8958 ring
->fbc_dirty
= true;
8963 * intel_fb_obj_invalidate - invalidate frontbuffer object
8964 * @obj: GEM object to invalidate
8965 * @ring: set for asynchronous rendering
8967 * This function gets called every time rendering on the given object starts and
8968 * frontbuffer caching (fbc, low refresh rate for DRRS, panel self refresh) must
8969 * be invalidated. If @ring is non-NULL any subsequent invalidation will be delayed
8970 * until the rendering completes or a flip on this frontbuffer plane is
8973 void intel_fb_obj_invalidate(struct drm_i915_gem_object
*obj
,
8974 struct intel_engine_cs
*ring
)
8976 struct drm_device
*dev
= obj
->base
.dev
;
8977 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8979 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
8981 if (!obj
->frontbuffer_bits
)
8985 mutex_lock(&dev_priv
->fb_tracking
.lock
);
8986 dev_priv
->fb_tracking
.busy_bits
8987 |= obj
->frontbuffer_bits
;
8988 dev_priv
->fb_tracking
.flip_bits
8989 &= ~obj
->frontbuffer_bits
;
8990 mutex_unlock(&dev_priv
->fb_tracking
.lock
);
8993 intel_mark_fb_busy(dev
, obj
->frontbuffer_bits
, ring
);
8995 intel_edp_psr_invalidate(dev
, obj
->frontbuffer_bits
);
8999 * intel_frontbuffer_flush - flush frontbuffer
9001 * @frontbuffer_bits: frontbuffer plane tracking bits
9003 * This function gets called every time rendering on the given planes has
9004 * completed and frontbuffer caching can be started again. Flushes will get
9005 * delayed if they're blocked by some oustanding asynchronous rendering.
9007 * Can be called without any locks held.
9009 void intel_frontbuffer_flush(struct drm_device
*dev
,
9010 unsigned frontbuffer_bits
)
9012 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9014 /* Delay flushing when rings are still busy.*/
9015 mutex_lock(&dev_priv
->fb_tracking
.lock
);
9016 frontbuffer_bits
&= ~dev_priv
->fb_tracking
.busy_bits
;
9017 mutex_unlock(&dev_priv
->fb_tracking
.lock
);
9019 intel_mark_fb_busy(dev
, frontbuffer_bits
, NULL
);
9021 intel_edp_psr_flush(dev
, frontbuffer_bits
);
9025 * intel_fb_obj_flush - flush frontbuffer object
9026 * @obj: GEM object to flush
9027 * @retire: set when retiring asynchronous rendering
9029 * This function gets called every time rendering on the given object has
9030 * completed and frontbuffer caching can be started again. If @retire is true
9031 * then any delayed flushes will be unblocked.
9033 void intel_fb_obj_flush(struct drm_i915_gem_object
*obj
,
9036 struct drm_device
*dev
= obj
->base
.dev
;
9037 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9038 unsigned frontbuffer_bits
;
9040 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
9042 if (!obj
->frontbuffer_bits
)
9045 frontbuffer_bits
= obj
->frontbuffer_bits
;
9048 mutex_lock(&dev_priv
->fb_tracking
.lock
);
9049 /* Filter out new bits since rendering started. */
9050 frontbuffer_bits
&= dev_priv
->fb_tracking
.busy_bits
;
9052 dev_priv
->fb_tracking
.busy_bits
&= ~frontbuffer_bits
;
9053 mutex_unlock(&dev_priv
->fb_tracking
.lock
);
9056 intel_frontbuffer_flush(dev
, frontbuffer_bits
);
9060 * intel_frontbuffer_flip_prepare - prepare asnychronous frontbuffer flip
9062 * @frontbuffer_bits: frontbuffer plane tracking bits
9064 * This function gets called after scheduling a flip on @obj. The actual
9065 * frontbuffer flushing will be delayed until completion is signalled with
9066 * intel_frontbuffer_flip_complete. If an invalidate happens in between this
9067 * flush will be cancelled.
9069 * Can be called without any locks held.
9071 void intel_frontbuffer_flip_prepare(struct drm_device
*dev
,
9072 unsigned frontbuffer_bits
)
9074 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9076 mutex_lock(&dev_priv
->fb_tracking
.lock
);
9077 dev_priv
->fb_tracking
.flip_bits
9078 |= frontbuffer_bits
;
9079 mutex_unlock(&dev_priv
->fb_tracking
.lock
);
9083 * intel_frontbuffer_flip_complete - complete asynchronous frontbuffer flush
9085 * @frontbuffer_bits: frontbuffer plane tracking bits
9087 * This function gets called after the flip has been latched and will complete
9088 * on the next vblank. It will execute the fush if it hasn't been cancalled yet.
9090 * Can be called without any locks held.
9092 void intel_frontbuffer_flip_complete(struct drm_device
*dev
,
9093 unsigned frontbuffer_bits
)
9095 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9097 mutex_lock(&dev_priv
->fb_tracking
.lock
);
9098 /* Mask any cancelled flips. */
9099 frontbuffer_bits
&= dev_priv
->fb_tracking
.flip_bits
;
9100 dev_priv
->fb_tracking
.flip_bits
&= ~frontbuffer_bits
;
9101 mutex_unlock(&dev_priv
->fb_tracking
.lock
);
9103 intel_frontbuffer_flush(dev
, frontbuffer_bits
);
9106 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
9108 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9109 struct drm_device
*dev
= crtc
->dev
;
9110 struct intel_unpin_work
*work
;
9111 unsigned long flags
;
9113 spin_lock_irqsave(&dev
->event_lock
, flags
);
9114 work
= intel_crtc
->unpin_work
;
9115 intel_crtc
->unpin_work
= NULL
;
9116 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9119 cancel_work_sync(&work
->work
);
9123 drm_crtc_cleanup(crtc
);
9128 static void intel_unpin_work_fn(struct work_struct
*__work
)
9130 struct intel_unpin_work
*work
=
9131 container_of(__work
, struct intel_unpin_work
, work
);
9132 struct drm_device
*dev
= work
->crtc
->dev
;
9133 enum pipe pipe
= to_intel_crtc(work
->crtc
)->pipe
;
9135 mutex_lock(&dev
->struct_mutex
);
9136 intel_unpin_fb_obj(work
->old_fb_obj
);
9137 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
9138 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
9140 intel_update_fbc(dev
);
9141 mutex_unlock(&dev
->struct_mutex
);
9143 intel_frontbuffer_flip_complete(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
9145 BUG_ON(atomic_read(&to_intel_crtc(work
->crtc
)->unpin_work_count
) == 0);
9146 atomic_dec(&to_intel_crtc(work
->crtc
)->unpin_work_count
);
9151 static void do_intel_finish_page_flip(struct drm_device
*dev
,
9152 struct drm_crtc
*crtc
)
9154 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9155 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9156 struct intel_unpin_work
*work
;
9157 unsigned long flags
;
9159 /* Ignore early vblank irqs */
9160 if (intel_crtc
== NULL
)
9163 spin_lock_irqsave(&dev
->event_lock
, flags
);
9164 work
= intel_crtc
->unpin_work
;
9166 /* Ensure we don't miss a work->pending update ... */
9169 if (work
== NULL
|| atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
9170 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9174 /* and that the unpin work is consistent wrt ->pending. */
9177 intel_crtc
->unpin_work
= NULL
;
9180 drm_send_vblank_event(dev
, intel_crtc
->pipe
, work
->event
);
9182 drm_crtc_vblank_put(crtc
);
9184 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9186 wake_up_all(&dev_priv
->pending_flip_queue
);
9188 queue_work(dev_priv
->wq
, &work
->work
);
9190 trace_i915_flip_complete(intel_crtc
->plane
, work
->pending_flip_obj
);
9193 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
9195 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9196 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
9198 do_intel_finish_page_flip(dev
, crtc
);
9201 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
9203 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9204 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
9206 do_intel_finish_page_flip(dev
, crtc
);
9209 /* Is 'a' after or equal to 'b'? */
9210 static bool g4x_flip_count_after_eq(u32 a
, u32 b
)
9212 return !((a
- b
) & 0x80000000);
9215 static bool page_flip_finished(struct intel_crtc
*crtc
)
9217 struct drm_device
*dev
= crtc
->base
.dev
;
9218 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9221 * The relevant registers doen't exist on pre-ctg.
9222 * As the flip done interrupt doesn't trigger for mmio
9223 * flips on gmch platforms, a flip count check isn't
9224 * really needed there. But since ctg has the registers,
9225 * include it in the check anyway.
9227 if (INTEL_INFO(dev
)->gen
< 5 && !IS_G4X(dev
))
9231 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9232 * used the same base address. In that case the mmio flip might
9233 * have completed, but the CS hasn't even executed the flip yet.
9235 * A flip count check isn't enough as the CS might have updated
9236 * the base address just after start of vblank, but before we
9237 * managed to process the interrupt. This means we'd complete the
9240 * Combining both checks should get us a good enough result. It may
9241 * still happen that the CS flip has been executed, but has not
9242 * yet actually completed. But in case the base address is the same
9243 * anyway, we don't really care.
9245 return (I915_READ(DSPSURFLIVE(crtc
->plane
)) & ~0xfff) ==
9246 crtc
->unpin_work
->gtt_offset
&&
9247 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc
->pipe
)),
9248 crtc
->unpin_work
->flip_count
);
9251 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
9253 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9254 struct intel_crtc
*intel_crtc
=
9255 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
9256 unsigned long flags
;
9258 /* NB: An MMIO update of the plane base pointer will also
9259 * generate a page-flip completion irq, i.e. every modeset
9260 * is also accompanied by a spurious intel_prepare_page_flip().
9262 spin_lock_irqsave(&dev
->event_lock
, flags
);
9263 if (intel_crtc
->unpin_work
&& page_flip_finished(intel_crtc
))
9264 atomic_inc_not_zero(&intel_crtc
->unpin_work
->pending
);
9265 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9268 static inline void intel_mark_page_flip_active(struct intel_crtc
*intel_crtc
)
9270 /* Ensure that the work item is consistent when activating it ... */
9272 atomic_set(&intel_crtc
->unpin_work
->pending
, INTEL_FLIP_PENDING
);
9273 /* and that it is marked active as soon as the irq could fire. */
9277 static int intel_gen2_queue_flip(struct drm_device
*dev
,
9278 struct drm_crtc
*crtc
,
9279 struct drm_framebuffer
*fb
,
9280 struct drm_i915_gem_object
*obj
,
9281 struct intel_engine_cs
*ring
,
9284 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9288 ret
= intel_ring_begin(ring
, 6);
9292 /* Can't queue multiple flips, so wait for the previous
9293 * one to finish before executing the next.
9295 if (intel_crtc
->plane
)
9296 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
9298 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
9299 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
9300 intel_ring_emit(ring
, MI_NOOP
);
9301 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
9302 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9303 intel_ring_emit(ring
, fb
->pitches
[0]);
9304 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9305 intel_ring_emit(ring
, 0); /* aux display base address, unused */
9307 intel_mark_page_flip_active(intel_crtc
);
9308 __intel_ring_advance(ring
);
9312 static int intel_gen3_queue_flip(struct drm_device
*dev
,
9313 struct drm_crtc
*crtc
,
9314 struct drm_framebuffer
*fb
,
9315 struct drm_i915_gem_object
*obj
,
9316 struct intel_engine_cs
*ring
,
9319 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9323 ret
= intel_ring_begin(ring
, 6);
9327 if (intel_crtc
->plane
)
9328 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
9330 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
9331 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
9332 intel_ring_emit(ring
, MI_NOOP
);
9333 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
9334 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9335 intel_ring_emit(ring
, fb
->pitches
[0]);
9336 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9337 intel_ring_emit(ring
, MI_NOOP
);
9339 intel_mark_page_flip_active(intel_crtc
);
9340 __intel_ring_advance(ring
);
9344 static int intel_gen4_queue_flip(struct drm_device
*dev
,
9345 struct drm_crtc
*crtc
,
9346 struct drm_framebuffer
*fb
,
9347 struct drm_i915_gem_object
*obj
,
9348 struct intel_engine_cs
*ring
,
9351 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9352 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9353 uint32_t pf
, pipesrc
;
9356 ret
= intel_ring_begin(ring
, 4);
9360 /* i965+ uses the linear or tiled offsets from the
9361 * Display Registers (which do not change across a page-flip)
9362 * so we need only reprogram the base address.
9364 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
9365 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9366 intel_ring_emit(ring
, fb
->pitches
[0]);
9367 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
|
9370 /* XXX Enabling the panel-fitter across page-flip is so far
9371 * untested on non-native modes, so ignore it for now.
9372 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9375 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
9376 intel_ring_emit(ring
, pf
| pipesrc
);
9378 intel_mark_page_flip_active(intel_crtc
);
9379 __intel_ring_advance(ring
);
9383 static int intel_gen6_queue_flip(struct drm_device
*dev
,
9384 struct drm_crtc
*crtc
,
9385 struct drm_framebuffer
*fb
,
9386 struct drm_i915_gem_object
*obj
,
9387 struct intel_engine_cs
*ring
,
9390 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9391 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9392 uint32_t pf
, pipesrc
;
9395 ret
= intel_ring_begin(ring
, 4);
9399 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
9400 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9401 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
9402 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9404 /* Contrary to the suggestions in the documentation,
9405 * "Enable Panel Fitter" does not seem to be required when page
9406 * flipping with a non-native mode, and worse causes a normal
9408 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9411 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
9412 intel_ring_emit(ring
, pf
| pipesrc
);
9414 intel_mark_page_flip_active(intel_crtc
);
9415 __intel_ring_advance(ring
);
9419 static int intel_gen7_queue_flip(struct drm_device
*dev
,
9420 struct drm_crtc
*crtc
,
9421 struct drm_framebuffer
*fb
,
9422 struct drm_i915_gem_object
*obj
,
9423 struct intel_engine_cs
*ring
,
9426 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9427 uint32_t plane_bit
= 0;
9430 switch (intel_crtc
->plane
) {
9432 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
9435 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
9438 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
9441 WARN_ONCE(1, "unknown plane in flip command\n");
9446 if (ring
->id
== RCS
) {
9449 * On Gen 8, SRM is now taking an extra dword to accommodate
9450 * 48bits addresses, and we need a NOOP for the batch size to
9458 * BSpec MI_DISPLAY_FLIP for IVB:
9459 * "The full packet must be contained within the same cache line."
9461 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9462 * cacheline, if we ever start emitting more commands before
9463 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9464 * then do the cacheline alignment, and finally emit the
9467 ret
= intel_ring_cacheline_align(ring
);
9471 ret
= intel_ring_begin(ring
, len
);
9475 /* Unmask the flip-done completion message. Note that the bspec says that
9476 * we should do this for both the BCS and RCS, and that we must not unmask
9477 * more than one flip event at any time (or ensure that one flip message
9478 * can be sent by waiting for flip-done prior to queueing new flips).
9479 * Experimentation says that BCS works despite DERRMR masking all
9480 * flip-done completion events and that unmasking all planes at once
9481 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9482 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9484 if (ring
->id
== RCS
) {
9485 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
9486 intel_ring_emit(ring
, DERRMR
);
9487 intel_ring_emit(ring
, ~(DERRMR_PIPEA_PRI_FLIP_DONE
|
9488 DERRMR_PIPEB_PRI_FLIP_DONE
|
9489 DERRMR_PIPEC_PRI_FLIP_DONE
));
9491 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM_GEN8(1) |
9492 MI_SRM_LRM_GLOBAL_GTT
);
9494 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM(1) |
9495 MI_SRM_LRM_GLOBAL_GTT
);
9496 intel_ring_emit(ring
, DERRMR
);
9497 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
+ 256);
9499 intel_ring_emit(ring
, 0);
9500 intel_ring_emit(ring
, MI_NOOP
);
9504 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
9505 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
9506 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9507 intel_ring_emit(ring
, (MI_NOOP
));
9509 intel_mark_page_flip_active(intel_crtc
);
9510 __intel_ring_advance(ring
);
9514 static bool use_mmio_flip(struct intel_engine_cs
*ring
,
9515 struct drm_i915_gem_object
*obj
)
9518 * This is not being used for older platforms, because
9519 * non-availability of flip done interrupt forces us to use
9520 * CS flips. Older platforms derive flip done using some clever
9521 * tricks involving the flip_pending status bits and vblank irqs.
9522 * So using MMIO flips there would disrupt this mechanism.
9528 if (INTEL_INFO(ring
->dev
)->gen
< 5)
9531 if (i915
.use_mmio_flip
< 0)
9533 else if (i915
.use_mmio_flip
> 0)
9536 return ring
!= obj
->ring
;
9539 static void intel_do_mmio_flip(struct intel_crtc
*intel_crtc
)
9541 struct drm_device
*dev
= intel_crtc
->base
.dev
;
9542 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9543 struct intel_framebuffer
*intel_fb
=
9544 to_intel_framebuffer(intel_crtc
->base
.primary
->fb
);
9545 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
9549 intel_mark_page_flip_active(intel_crtc
);
9551 reg
= DSPCNTR(intel_crtc
->plane
);
9552 dspcntr
= I915_READ(reg
);
9554 if (INTEL_INFO(dev
)->gen
>= 4) {
9555 if (obj
->tiling_mode
!= I915_TILING_NONE
)
9556 dspcntr
|= DISPPLANE_TILED
;
9558 dspcntr
&= ~DISPPLANE_TILED
;
9560 I915_WRITE(reg
, dspcntr
);
9562 I915_WRITE(DSPSURF(intel_crtc
->plane
),
9563 intel_crtc
->unpin_work
->gtt_offset
);
9564 POSTING_READ(DSPSURF(intel_crtc
->plane
));
9567 static int intel_postpone_flip(struct drm_i915_gem_object
*obj
)
9569 struct intel_engine_cs
*ring
;
9572 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
9574 if (!obj
->last_write_seqno
)
9579 if (i915_seqno_passed(ring
->get_seqno(ring
, true),
9580 obj
->last_write_seqno
))
9583 ret
= i915_gem_check_olr(ring
, obj
->last_write_seqno
);
9587 if (WARN_ON(!ring
->irq_get(ring
)))
9593 void intel_notify_mmio_flip(struct intel_engine_cs
*ring
)
9595 struct drm_i915_private
*dev_priv
= to_i915(ring
->dev
);
9596 struct intel_crtc
*intel_crtc
;
9597 unsigned long irq_flags
;
9600 seqno
= ring
->get_seqno(ring
, false);
9602 spin_lock_irqsave(&dev_priv
->mmio_flip_lock
, irq_flags
);
9603 for_each_intel_crtc(ring
->dev
, intel_crtc
) {
9604 struct intel_mmio_flip
*mmio_flip
;
9606 mmio_flip
= &intel_crtc
->mmio_flip
;
9607 if (mmio_flip
->seqno
== 0)
9610 if (ring
->id
!= mmio_flip
->ring_id
)
9613 if (i915_seqno_passed(seqno
, mmio_flip
->seqno
)) {
9614 intel_do_mmio_flip(intel_crtc
);
9615 mmio_flip
->seqno
= 0;
9616 ring
->irq_put(ring
);
9619 spin_unlock_irqrestore(&dev_priv
->mmio_flip_lock
, irq_flags
);
9622 static int intel_queue_mmio_flip(struct drm_device
*dev
,
9623 struct drm_crtc
*crtc
,
9624 struct drm_framebuffer
*fb
,
9625 struct drm_i915_gem_object
*obj
,
9626 struct intel_engine_cs
*ring
,
9629 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9630 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9631 unsigned long irq_flags
;
9634 if (WARN_ON(intel_crtc
->mmio_flip
.seqno
))
9637 ret
= intel_postpone_flip(obj
);
9641 intel_do_mmio_flip(intel_crtc
);
9645 spin_lock_irqsave(&dev_priv
->mmio_flip_lock
, irq_flags
);
9646 intel_crtc
->mmio_flip
.seqno
= obj
->last_write_seqno
;
9647 intel_crtc
->mmio_flip
.ring_id
= obj
->ring
->id
;
9648 spin_unlock_irqrestore(&dev_priv
->mmio_flip_lock
, irq_flags
);
9651 * Double check to catch cases where irq fired before
9652 * mmio flip data was ready
9654 intel_notify_mmio_flip(obj
->ring
);
9658 static int intel_default_queue_flip(struct drm_device
*dev
,
9659 struct drm_crtc
*crtc
,
9660 struct drm_framebuffer
*fb
,
9661 struct drm_i915_gem_object
*obj
,
9662 struct intel_engine_cs
*ring
,
9668 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
9669 struct drm_framebuffer
*fb
,
9670 struct drm_pending_vblank_event
*event
,
9671 uint32_t page_flip_flags
)
9673 struct drm_device
*dev
= crtc
->dev
;
9674 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9675 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
9676 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
9677 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9678 enum pipe pipe
= intel_crtc
->pipe
;
9679 struct intel_unpin_work
*work
;
9680 struct intel_engine_cs
*ring
;
9681 unsigned long flags
;
9685 * drm_mode_page_flip_ioctl() should already catch this, but double
9686 * check to be safe. In the future we may enable pageflipping from
9687 * a disabled primary plane.
9689 if (WARN_ON(intel_fb_obj(old_fb
) == NULL
))
9692 /* Can't change pixel format via MI display flips. */
9693 if (fb
->pixel_format
!= crtc
->primary
->fb
->pixel_format
)
9697 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9698 * Note that pitch changes could also affect these register.
9700 if (INTEL_INFO(dev
)->gen
> 3 &&
9701 (fb
->offsets
[0] != crtc
->primary
->fb
->offsets
[0] ||
9702 fb
->pitches
[0] != crtc
->primary
->fb
->pitches
[0]))
9705 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
9708 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
9712 work
->event
= event
;
9714 work
->old_fb_obj
= intel_fb_obj(old_fb
);
9715 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
9717 ret
= drm_crtc_vblank_get(crtc
);
9721 /* We borrow the event spin lock for protecting unpin_work */
9722 spin_lock_irqsave(&dev
->event_lock
, flags
);
9723 if (intel_crtc
->unpin_work
) {
9724 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9726 drm_crtc_vblank_put(crtc
);
9728 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9731 intel_crtc
->unpin_work
= work
;
9732 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9734 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
9735 flush_workqueue(dev_priv
->wq
);
9737 ret
= i915_mutex_lock_interruptible(dev
);
9741 /* Reference the objects for the scheduled work. */
9742 drm_gem_object_reference(&work
->old_fb_obj
->base
);
9743 drm_gem_object_reference(&obj
->base
);
9745 crtc
->primary
->fb
= fb
;
9747 work
->pending_flip_obj
= obj
;
9749 work
->enable_stall_check
= true;
9751 atomic_inc(&intel_crtc
->unpin_work_count
);
9752 intel_crtc
->reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
9754 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
9755 work
->flip_count
= I915_READ(PIPE_FLIPCOUNT_GM45(pipe
)) + 1;
9757 if (IS_VALLEYVIEW(dev
)) {
9758 ring
= &dev_priv
->ring
[BCS
];
9759 if (obj
->tiling_mode
!= work
->old_fb_obj
->tiling_mode
)
9760 /* vlv: DISPLAY_FLIP fails to change tiling */
9762 } else if (IS_IVYBRIDGE(dev
)) {
9763 ring
= &dev_priv
->ring
[BCS
];
9764 } else if (INTEL_INFO(dev
)->gen
>= 7) {
9766 if (ring
== NULL
|| ring
->id
!= RCS
)
9767 ring
= &dev_priv
->ring
[BCS
];
9769 ring
= &dev_priv
->ring
[RCS
];
9772 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
9774 goto cleanup_pending
;
9777 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
;
9779 if (use_mmio_flip(ring
, obj
))
9780 ret
= intel_queue_mmio_flip(dev
, crtc
, fb
, obj
, ring
,
9783 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
, ring
,
9788 i915_gem_track_fb(work
->old_fb_obj
, obj
,
9789 INTEL_FRONTBUFFER_PRIMARY(pipe
));
9791 intel_disable_fbc(dev
);
9792 intel_frontbuffer_flip_prepare(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
9793 mutex_unlock(&dev
->struct_mutex
);
9795 trace_i915_flip_request(intel_crtc
->plane
, obj
);
9800 intel_unpin_fb_obj(obj
);
9802 atomic_dec(&intel_crtc
->unpin_work_count
);
9803 crtc
->primary
->fb
= old_fb
;
9804 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
9805 drm_gem_object_unreference(&obj
->base
);
9806 mutex_unlock(&dev
->struct_mutex
);
9809 spin_lock_irqsave(&dev
->event_lock
, flags
);
9810 intel_crtc
->unpin_work
= NULL
;
9811 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9813 drm_crtc_vblank_put(crtc
);
9819 intel_crtc_wait_for_pending_flips(crtc
);
9820 ret
= intel_pipe_set_base(crtc
, crtc
->x
, crtc
->y
, fb
);
9821 if (ret
== 0 && event
)
9822 drm_send_vblank_event(dev
, pipe
, event
);
9827 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
9828 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
9829 .load_lut
= intel_crtc_load_lut
,
9833 * intel_modeset_update_staged_output_state
9835 * Updates the staged output configuration state, e.g. after we've read out the
9838 static void intel_modeset_update_staged_output_state(struct drm_device
*dev
)
9840 struct intel_crtc
*crtc
;
9841 struct intel_encoder
*encoder
;
9842 struct intel_connector
*connector
;
9844 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9846 connector
->new_encoder
=
9847 to_intel_encoder(connector
->base
.encoder
);
9850 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9853 to_intel_crtc(encoder
->base
.crtc
);
9856 for_each_intel_crtc(dev
, crtc
) {
9857 crtc
->new_enabled
= crtc
->base
.enabled
;
9859 if (crtc
->new_enabled
)
9860 crtc
->new_config
= &crtc
->config
;
9862 crtc
->new_config
= NULL
;
9867 * intel_modeset_commit_output_state
9869 * This function copies the stage display pipe configuration to the real one.
9871 static void intel_modeset_commit_output_state(struct drm_device
*dev
)
9873 struct intel_crtc
*crtc
;
9874 struct intel_encoder
*encoder
;
9875 struct intel_connector
*connector
;
9877 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9879 connector
->base
.encoder
= &connector
->new_encoder
->base
;
9882 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9884 encoder
->base
.crtc
= &encoder
->new_crtc
->base
;
9887 for_each_intel_crtc(dev
, crtc
) {
9888 crtc
->base
.enabled
= crtc
->new_enabled
;
9893 connected_sink_compute_bpp(struct intel_connector
*connector
,
9894 struct intel_crtc_config
*pipe_config
)
9896 int bpp
= pipe_config
->pipe_bpp
;
9898 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9899 connector
->base
.base
.id
,
9900 connector
->base
.name
);
9902 /* Don't use an invalid EDID bpc value */
9903 if (connector
->base
.display_info
.bpc
&&
9904 connector
->base
.display_info
.bpc
* 3 < bpp
) {
9905 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9906 bpp
, connector
->base
.display_info
.bpc
*3);
9907 pipe_config
->pipe_bpp
= connector
->base
.display_info
.bpc
*3;
9910 /* Clamp bpp to 8 on screens without EDID 1.4 */
9911 if (connector
->base
.display_info
.bpc
== 0 && bpp
> 24) {
9912 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9914 pipe_config
->pipe_bpp
= 24;
9919 compute_baseline_pipe_bpp(struct intel_crtc
*crtc
,
9920 struct drm_framebuffer
*fb
,
9921 struct intel_crtc_config
*pipe_config
)
9923 struct drm_device
*dev
= crtc
->base
.dev
;
9924 struct intel_connector
*connector
;
9927 switch (fb
->pixel_format
) {
9929 bpp
= 8*3; /* since we go through a colormap */
9931 case DRM_FORMAT_XRGB1555
:
9932 case DRM_FORMAT_ARGB1555
:
9933 /* checked in intel_framebuffer_init already */
9934 if (WARN_ON(INTEL_INFO(dev
)->gen
> 3))
9936 case DRM_FORMAT_RGB565
:
9937 bpp
= 6*3; /* min is 18bpp */
9939 case DRM_FORMAT_XBGR8888
:
9940 case DRM_FORMAT_ABGR8888
:
9941 /* checked in intel_framebuffer_init already */
9942 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
9944 case DRM_FORMAT_XRGB8888
:
9945 case DRM_FORMAT_ARGB8888
:
9948 case DRM_FORMAT_XRGB2101010
:
9949 case DRM_FORMAT_ARGB2101010
:
9950 case DRM_FORMAT_XBGR2101010
:
9951 case DRM_FORMAT_ABGR2101010
:
9952 /* checked in intel_framebuffer_init already */
9953 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
9957 /* TODO: gen4+ supports 16 bpc floating point, too. */
9959 DRM_DEBUG_KMS("unsupported depth\n");
9963 pipe_config
->pipe_bpp
= bpp
;
9965 /* Clamp display bpp to EDID value */
9966 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9968 if (!connector
->new_encoder
||
9969 connector
->new_encoder
->new_crtc
!= crtc
)
9972 connected_sink_compute_bpp(connector
, pipe_config
);
9978 static void intel_dump_crtc_timings(const struct drm_display_mode
*mode
)
9980 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9981 "type: 0x%x flags: 0x%x\n",
9983 mode
->crtc_hdisplay
, mode
->crtc_hsync_start
,
9984 mode
->crtc_hsync_end
, mode
->crtc_htotal
,
9985 mode
->crtc_vdisplay
, mode
->crtc_vsync_start
,
9986 mode
->crtc_vsync_end
, mode
->crtc_vtotal
, mode
->type
, mode
->flags
);
9989 static void intel_dump_pipe_config(struct intel_crtc
*crtc
,
9990 struct intel_crtc_config
*pipe_config
,
9991 const char *context
)
9993 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc
->base
.base
.id
,
9994 context
, pipe_name(crtc
->pipe
));
9996 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config
->cpu_transcoder
));
9997 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9998 pipe_config
->pipe_bpp
, pipe_config
->dither
);
9999 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10000 pipe_config
->has_pch_encoder
,
10001 pipe_config
->fdi_lanes
,
10002 pipe_config
->fdi_m_n
.gmch_m
, pipe_config
->fdi_m_n
.gmch_n
,
10003 pipe_config
->fdi_m_n
.link_m
, pipe_config
->fdi_m_n
.link_n
,
10004 pipe_config
->fdi_m_n
.tu
);
10005 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10006 pipe_config
->has_dp_encoder
,
10007 pipe_config
->dp_m_n
.gmch_m
, pipe_config
->dp_m_n
.gmch_n
,
10008 pipe_config
->dp_m_n
.link_m
, pipe_config
->dp_m_n
.link_n
,
10009 pipe_config
->dp_m_n
.tu
);
10010 DRM_DEBUG_KMS("requested mode:\n");
10011 drm_mode_debug_printmodeline(&pipe_config
->requested_mode
);
10012 DRM_DEBUG_KMS("adjusted mode:\n");
10013 drm_mode_debug_printmodeline(&pipe_config
->adjusted_mode
);
10014 intel_dump_crtc_timings(&pipe_config
->adjusted_mode
);
10015 DRM_DEBUG_KMS("port clock: %d\n", pipe_config
->port_clock
);
10016 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10017 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
);
10018 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10019 pipe_config
->gmch_pfit
.control
,
10020 pipe_config
->gmch_pfit
.pgm_ratios
,
10021 pipe_config
->gmch_pfit
.lvds_border_bits
);
10022 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10023 pipe_config
->pch_pfit
.pos
,
10024 pipe_config
->pch_pfit
.size
,
10025 pipe_config
->pch_pfit
.enabled
? "enabled" : "disabled");
10026 DRM_DEBUG_KMS("ips: %i\n", pipe_config
->ips_enabled
);
10027 DRM_DEBUG_KMS("double wide: %i\n", pipe_config
->double_wide
);
10030 static bool encoders_cloneable(const struct intel_encoder
*a
,
10031 const struct intel_encoder
*b
)
10033 /* masks could be asymmetric, so check both ways */
10034 return a
== b
|| (a
->cloneable
& (1 << b
->type
) &&
10035 b
->cloneable
& (1 << a
->type
));
10038 static bool check_single_encoder_cloning(struct intel_crtc
*crtc
,
10039 struct intel_encoder
*encoder
)
10041 struct drm_device
*dev
= crtc
->base
.dev
;
10042 struct intel_encoder
*source_encoder
;
10044 list_for_each_entry(source_encoder
,
10045 &dev
->mode_config
.encoder_list
, base
.head
) {
10046 if (source_encoder
->new_crtc
!= crtc
)
10049 if (!encoders_cloneable(encoder
, source_encoder
))
10056 static bool check_encoder_cloning(struct intel_crtc
*crtc
)
10058 struct drm_device
*dev
= crtc
->base
.dev
;
10059 struct intel_encoder
*encoder
;
10061 list_for_each_entry(encoder
,
10062 &dev
->mode_config
.encoder_list
, base
.head
) {
10063 if (encoder
->new_crtc
!= crtc
)
10066 if (!check_single_encoder_cloning(crtc
, encoder
))
10073 static struct intel_crtc_config
*
10074 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
10075 struct drm_framebuffer
*fb
,
10076 struct drm_display_mode
*mode
)
10078 struct drm_device
*dev
= crtc
->dev
;
10079 struct intel_encoder
*encoder
;
10080 struct intel_crtc_config
*pipe_config
;
10081 int plane_bpp
, ret
= -EINVAL
;
10084 if (!check_encoder_cloning(to_intel_crtc(crtc
))) {
10085 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10086 return ERR_PTR(-EINVAL
);
10089 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
10091 return ERR_PTR(-ENOMEM
);
10093 drm_mode_copy(&pipe_config
->adjusted_mode
, mode
);
10094 drm_mode_copy(&pipe_config
->requested_mode
, mode
);
10096 pipe_config
->cpu_transcoder
=
10097 (enum transcoder
) to_intel_crtc(crtc
)->pipe
;
10098 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
10101 * Sanitize sync polarity flags based on requested ones. If neither
10102 * positive or negative polarity is requested, treat this as meaning
10103 * negative polarity.
10105 if (!(pipe_config
->adjusted_mode
.flags
&
10106 (DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NHSYNC
)))
10107 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
10109 if (!(pipe_config
->adjusted_mode
.flags
&
10110 (DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_NVSYNC
)))
10111 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
10113 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10114 * plane pixel format and any sink constraints into account. Returns the
10115 * source plane bpp so that dithering can be selected on mismatches
10116 * after encoders and crtc also have had their say. */
10117 plane_bpp
= compute_baseline_pipe_bpp(to_intel_crtc(crtc
),
10123 * Determine the real pipe dimensions. Note that stereo modes can
10124 * increase the actual pipe size due to the frame doubling and
10125 * insertion of additional space for blanks between the frame. This
10126 * is stored in the crtc timings. We use the requested mode to do this
10127 * computation to clearly distinguish it from the adjusted mode, which
10128 * can be changed by the connectors in the below retry loop.
10130 drm_mode_set_crtcinfo(&pipe_config
->requested_mode
, CRTC_STEREO_DOUBLE
);
10131 pipe_config
->pipe_src_w
= pipe_config
->requested_mode
.crtc_hdisplay
;
10132 pipe_config
->pipe_src_h
= pipe_config
->requested_mode
.crtc_vdisplay
;
10135 /* Ensure the port clock defaults are reset when retrying. */
10136 pipe_config
->port_clock
= 0;
10137 pipe_config
->pixel_multiplier
= 1;
10139 /* Fill in default crtc timings, allow encoders to overwrite them. */
10140 drm_mode_set_crtcinfo(&pipe_config
->adjusted_mode
, CRTC_STEREO_DOUBLE
);
10142 /* Pass our mode to the connectors and the CRTC to give them a chance to
10143 * adjust it according to limitations or connector properties, and also
10144 * a chance to reject the mode entirely.
10146 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
10149 if (&encoder
->new_crtc
->base
!= crtc
)
10152 if (!(encoder
->compute_config(encoder
, pipe_config
))) {
10153 DRM_DEBUG_KMS("Encoder config failure\n");
10158 /* Set default port clock if not overwritten by the encoder. Needs to be
10159 * done afterwards in case the encoder adjusts the mode. */
10160 if (!pipe_config
->port_clock
)
10161 pipe_config
->port_clock
= pipe_config
->adjusted_mode
.crtc_clock
10162 * pipe_config
->pixel_multiplier
;
10164 ret
= intel_crtc_compute_config(to_intel_crtc(crtc
), pipe_config
);
10166 DRM_DEBUG_KMS("CRTC fixup failed\n");
10170 if (ret
== RETRY
) {
10171 if (WARN(!retry
, "loop in pipe configuration computation\n")) {
10176 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10178 goto encoder_retry
;
10181 pipe_config
->dither
= pipe_config
->pipe_bpp
!= plane_bpp
;
10182 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10183 plane_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
10185 return pipe_config
;
10187 kfree(pipe_config
);
10188 return ERR_PTR(ret
);
10191 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10192 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10194 intel_modeset_affected_pipes(struct drm_crtc
*crtc
, unsigned *modeset_pipes
,
10195 unsigned *prepare_pipes
, unsigned *disable_pipes
)
10197 struct intel_crtc
*intel_crtc
;
10198 struct drm_device
*dev
= crtc
->dev
;
10199 struct intel_encoder
*encoder
;
10200 struct intel_connector
*connector
;
10201 struct drm_crtc
*tmp_crtc
;
10203 *disable_pipes
= *modeset_pipes
= *prepare_pipes
= 0;
10205 /* Check which crtcs have changed outputs connected to them, these need
10206 * to be part of the prepare_pipes mask. We don't (yet) support global
10207 * modeset across multiple crtcs, so modeset_pipes will only have one
10208 * bit set at most. */
10209 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10211 if (connector
->base
.encoder
== &connector
->new_encoder
->base
)
10214 if (connector
->base
.encoder
) {
10215 tmp_crtc
= connector
->base
.encoder
->crtc
;
10217 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
10220 if (connector
->new_encoder
)
10222 1 << connector
->new_encoder
->new_crtc
->pipe
;
10225 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
10227 if (encoder
->base
.crtc
== &encoder
->new_crtc
->base
)
10230 if (encoder
->base
.crtc
) {
10231 tmp_crtc
= encoder
->base
.crtc
;
10233 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
10236 if (encoder
->new_crtc
)
10237 *prepare_pipes
|= 1 << encoder
->new_crtc
->pipe
;
10240 /* Check for pipes that will be enabled/disabled ... */
10241 for_each_intel_crtc(dev
, intel_crtc
) {
10242 if (intel_crtc
->base
.enabled
== intel_crtc
->new_enabled
)
10245 if (!intel_crtc
->new_enabled
)
10246 *disable_pipes
|= 1 << intel_crtc
->pipe
;
10248 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
10252 /* set_mode is also used to update properties on life display pipes. */
10253 intel_crtc
= to_intel_crtc(crtc
);
10254 if (intel_crtc
->new_enabled
)
10255 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
10258 * For simplicity do a full modeset on any pipe where the output routing
10259 * changed. We could be more clever, but that would require us to be
10260 * more careful with calling the relevant encoder->mode_set functions.
10262 if (*prepare_pipes
)
10263 *modeset_pipes
= *prepare_pipes
;
10265 /* ... and mask these out. */
10266 *modeset_pipes
&= ~(*disable_pipes
);
10267 *prepare_pipes
&= ~(*disable_pipes
);
10270 * HACK: We don't (yet) fully support global modesets. intel_set_config
10271 * obies this rule, but the modeset restore mode of
10272 * intel_modeset_setup_hw_state does not.
10274 *modeset_pipes
&= 1 << intel_crtc
->pipe
;
10275 *prepare_pipes
&= 1 << intel_crtc
->pipe
;
10277 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10278 *modeset_pipes
, *prepare_pipes
, *disable_pipes
);
10281 static bool intel_crtc_in_use(struct drm_crtc
*crtc
)
10283 struct drm_encoder
*encoder
;
10284 struct drm_device
*dev
= crtc
->dev
;
10286 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
)
10287 if (encoder
->crtc
== crtc
)
10294 intel_modeset_update_state(struct drm_device
*dev
, unsigned prepare_pipes
)
10296 struct intel_encoder
*intel_encoder
;
10297 struct intel_crtc
*intel_crtc
;
10298 struct drm_connector
*connector
;
10300 list_for_each_entry(intel_encoder
, &dev
->mode_config
.encoder_list
,
10302 if (!intel_encoder
->base
.crtc
)
10305 intel_crtc
= to_intel_crtc(intel_encoder
->base
.crtc
);
10307 if (prepare_pipes
& (1 << intel_crtc
->pipe
))
10308 intel_encoder
->connectors_active
= false;
10311 intel_modeset_commit_output_state(dev
);
10313 /* Double check state. */
10314 for_each_intel_crtc(dev
, intel_crtc
) {
10315 WARN_ON(intel_crtc
->base
.enabled
!= intel_crtc_in_use(&intel_crtc
->base
));
10316 WARN_ON(intel_crtc
->new_config
&&
10317 intel_crtc
->new_config
!= &intel_crtc
->config
);
10318 WARN_ON(intel_crtc
->base
.enabled
!= !!intel_crtc
->new_config
);
10321 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
10322 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
10325 intel_crtc
= to_intel_crtc(connector
->encoder
->crtc
);
10327 if (prepare_pipes
& (1 << intel_crtc
->pipe
)) {
10328 struct drm_property
*dpms_property
=
10329 dev
->mode_config
.dpms_property
;
10331 connector
->dpms
= DRM_MODE_DPMS_ON
;
10332 drm_object_property_set_value(&connector
->base
,
10336 intel_encoder
= to_intel_encoder(connector
->encoder
);
10337 intel_encoder
->connectors_active
= true;
10343 static bool intel_fuzzy_clock_check(int clock1
, int clock2
)
10347 if (clock1
== clock2
)
10350 if (!clock1
|| !clock2
)
10353 diff
= abs(clock1
- clock2
);
10355 if (((((diff
+ clock1
+ clock2
) * 100)) / (clock1
+ clock2
)) < 105)
10361 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10362 list_for_each_entry((intel_crtc), \
10363 &(dev)->mode_config.crtc_list, \
10365 if (mask & (1 <<(intel_crtc)->pipe))
10368 intel_pipe_config_compare(struct drm_device
*dev
,
10369 struct intel_crtc_config
*current_config
,
10370 struct intel_crtc_config
*pipe_config
)
10372 #define PIPE_CONF_CHECK_X(name) \
10373 if (current_config->name != pipe_config->name) { \
10374 DRM_ERROR("mismatch in " #name " " \
10375 "(expected 0x%08x, found 0x%08x)\n", \
10376 current_config->name, \
10377 pipe_config->name); \
10381 #define PIPE_CONF_CHECK_I(name) \
10382 if (current_config->name != pipe_config->name) { \
10383 DRM_ERROR("mismatch in " #name " " \
10384 "(expected %i, found %i)\n", \
10385 current_config->name, \
10386 pipe_config->name); \
10390 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10391 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10392 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10393 "(expected %i, found %i)\n", \
10394 current_config->name & (mask), \
10395 pipe_config->name & (mask)); \
10399 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10400 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10401 DRM_ERROR("mismatch in " #name " " \
10402 "(expected %i, found %i)\n", \
10403 current_config->name, \
10404 pipe_config->name); \
10408 #define PIPE_CONF_QUIRK(quirk) \
10409 ((current_config->quirks | pipe_config->quirks) & (quirk))
10411 PIPE_CONF_CHECK_I(cpu_transcoder
);
10413 PIPE_CONF_CHECK_I(has_pch_encoder
);
10414 PIPE_CONF_CHECK_I(fdi_lanes
);
10415 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_m
);
10416 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_n
);
10417 PIPE_CONF_CHECK_I(fdi_m_n
.link_m
);
10418 PIPE_CONF_CHECK_I(fdi_m_n
.link_n
);
10419 PIPE_CONF_CHECK_I(fdi_m_n
.tu
);
10421 PIPE_CONF_CHECK_I(has_dp_encoder
);
10422 PIPE_CONF_CHECK_I(dp_m_n
.gmch_m
);
10423 PIPE_CONF_CHECK_I(dp_m_n
.gmch_n
);
10424 PIPE_CONF_CHECK_I(dp_m_n
.link_m
);
10425 PIPE_CONF_CHECK_I(dp_m_n
.link_n
);
10426 PIPE_CONF_CHECK_I(dp_m_n
.tu
);
10428 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hdisplay
);
10429 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_htotal
);
10430 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hblank_start
);
10431 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hblank_end
);
10432 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hsync_start
);
10433 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hsync_end
);
10435 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vdisplay
);
10436 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vtotal
);
10437 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vblank_start
);
10438 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vblank_end
);
10439 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vsync_start
);
10440 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vsync_end
);
10442 PIPE_CONF_CHECK_I(pixel_multiplier
);
10443 PIPE_CONF_CHECK_I(has_hdmi_sink
);
10444 if ((INTEL_INFO(dev
)->gen
< 8 && !IS_HASWELL(dev
)) ||
10445 IS_VALLEYVIEW(dev
))
10446 PIPE_CONF_CHECK_I(limited_color_range
);
10448 PIPE_CONF_CHECK_I(has_audio
);
10450 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10451 DRM_MODE_FLAG_INTERLACE
);
10453 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
10454 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10455 DRM_MODE_FLAG_PHSYNC
);
10456 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10457 DRM_MODE_FLAG_NHSYNC
);
10458 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10459 DRM_MODE_FLAG_PVSYNC
);
10460 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10461 DRM_MODE_FLAG_NVSYNC
);
10464 PIPE_CONF_CHECK_I(pipe_src_w
);
10465 PIPE_CONF_CHECK_I(pipe_src_h
);
10468 * FIXME: BIOS likes to set up a cloned config with lvds+external
10469 * screen. Since we don't yet re-compute the pipe config when moving
10470 * just the lvds port away to another pipe the sw tracking won't match.
10472 * Proper atomic modesets with recomputed global state will fix this.
10473 * Until then just don't check gmch state for inherited modes.
10475 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE
)) {
10476 PIPE_CONF_CHECK_I(gmch_pfit
.control
);
10477 /* pfit ratios are autocomputed by the hw on gen4+ */
10478 if (INTEL_INFO(dev
)->gen
< 4)
10479 PIPE_CONF_CHECK_I(gmch_pfit
.pgm_ratios
);
10480 PIPE_CONF_CHECK_I(gmch_pfit
.lvds_border_bits
);
10483 PIPE_CONF_CHECK_I(pch_pfit
.enabled
);
10484 if (current_config
->pch_pfit
.enabled
) {
10485 PIPE_CONF_CHECK_I(pch_pfit
.pos
);
10486 PIPE_CONF_CHECK_I(pch_pfit
.size
);
10489 /* BDW+ don't expose a synchronous way to read the state */
10490 if (IS_HASWELL(dev
))
10491 PIPE_CONF_CHECK_I(ips_enabled
);
10493 PIPE_CONF_CHECK_I(double_wide
);
10495 PIPE_CONF_CHECK_X(ddi_pll_sel
);
10497 PIPE_CONF_CHECK_I(shared_dpll
);
10498 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll
);
10499 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll_md
);
10500 PIPE_CONF_CHECK_X(dpll_hw_state
.fp0
);
10501 PIPE_CONF_CHECK_X(dpll_hw_state
.fp1
);
10502 PIPE_CONF_CHECK_X(dpll_hw_state
.wrpll
);
10504 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5)
10505 PIPE_CONF_CHECK_I(pipe_bpp
);
10507 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode
.crtc_clock
);
10508 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock
);
10510 #undef PIPE_CONF_CHECK_X
10511 #undef PIPE_CONF_CHECK_I
10512 #undef PIPE_CONF_CHECK_FLAGS
10513 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10514 #undef PIPE_CONF_QUIRK
10520 check_connector_state(struct drm_device
*dev
)
10522 struct intel_connector
*connector
;
10524 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10526 /* This also checks the encoder/connector hw state with the
10527 * ->get_hw_state callbacks. */
10528 intel_connector_check_state(connector
);
10530 WARN(&connector
->new_encoder
->base
!= connector
->base
.encoder
,
10531 "connector's staged encoder doesn't match current encoder\n");
10536 check_encoder_state(struct drm_device
*dev
)
10538 struct intel_encoder
*encoder
;
10539 struct intel_connector
*connector
;
10541 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
10543 bool enabled
= false;
10544 bool active
= false;
10545 enum pipe pipe
, tracked_pipe
;
10547 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10548 encoder
->base
.base
.id
,
10549 encoder
->base
.name
);
10551 WARN(&encoder
->new_crtc
->base
!= encoder
->base
.crtc
,
10552 "encoder's stage crtc doesn't match current crtc\n");
10553 WARN(encoder
->connectors_active
&& !encoder
->base
.crtc
,
10554 "encoder's active_connectors set, but no crtc\n");
10556 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10558 if (connector
->base
.encoder
!= &encoder
->base
)
10561 if (connector
->base
.dpms
!= DRM_MODE_DPMS_OFF
)
10565 * for MST connectors if we unplug the connector is gone
10566 * away but the encoder is still connected to a crtc
10567 * until a modeset happens in response to the hotplug.
10569 if (!enabled
&& encoder
->base
.encoder_type
== DRM_MODE_ENCODER_DPMST
)
10572 WARN(!!encoder
->base
.crtc
!= enabled
,
10573 "encoder's enabled state mismatch "
10574 "(expected %i, found %i)\n",
10575 !!encoder
->base
.crtc
, enabled
);
10576 WARN(active
&& !encoder
->base
.crtc
,
10577 "active encoder with no crtc\n");
10579 WARN(encoder
->connectors_active
!= active
,
10580 "encoder's computed active state doesn't match tracked active state "
10581 "(expected %i, found %i)\n", active
, encoder
->connectors_active
);
10583 active
= encoder
->get_hw_state(encoder
, &pipe
);
10584 WARN(active
!= encoder
->connectors_active
,
10585 "encoder's hw state doesn't match sw tracking "
10586 "(expected %i, found %i)\n",
10587 encoder
->connectors_active
, active
);
10589 if (!encoder
->base
.crtc
)
10592 tracked_pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
10593 WARN(active
&& pipe
!= tracked_pipe
,
10594 "active encoder's pipe doesn't match"
10595 "(expected %i, found %i)\n",
10596 tracked_pipe
, pipe
);
10602 check_crtc_state(struct drm_device
*dev
)
10604 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10605 struct intel_crtc
*crtc
;
10606 struct intel_encoder
*encoder
;
10607 struct intel_crtc_config pipe_config
;
10609 for_each_intel_crtc(dev
, crtc
) {
10610 bool enabled
= false;
10611 bool active
= false;
10613 memset(&pipe_config
, 0, sizeof(pipe_config
));
10615 DRM_DEBUG_KMS("[CRTC:%d]\n",
10616 crtc
->base
.base
.id
);
10618 WARN(crtc
->active
&& !crtc
->base
.enabled
,
10619 "active crtc, but not enabled in sw tracking\n");
10621 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
10623 if (encoder
->base
.crtc
!= &crtc
->base
)
10626 if (encoder
->connectors_active
)
10630 WARN(active
!= crtc
->active
,
10631 "crtc's computed active state doesn't match tracked active state "
10632 "(expected %i, found %i)\n", active
, crtc
->active
);
10633 WARN(enabled
!= crtc
->base
.enabled
,
10634 "crtc's computed enabled state doesn't match tracked enabled state "
10635 "(expected %i, found %i)\n", enabled
, crtc
->base
.enabled
);
10637 active
= dev_priv
->display
.get_pipe_config(crtc
,
10640 /* hw state is inconsistent with the pipe A quirk */
10641 if (crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
10642 active
= crtc
->active
;
10644 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
10647 if (encoder
->base
.crtc
!= &crtc
->base
)
10649 if (encoder
->get_hw_state(encoder
, &pipe
))
10650 encoder
->get_config(encoder
, &pipe_config
);
10653 WARN(crtc
->active
!= active
,
10654 "crtc active state doesn't match with hw state "
10655 "(expected %i, found %i)\n", crtc
->active
, active
);
10658 !intel_pipe_config_compare(dev
, &crtc
->config
, &pipe_config
)) {
10659 WARN(1, "pipe state doesn't match!\n");
10660 intel_dump_pipe_config(crtc
, &pipe_config
,
10662 intel_dump_pipe_config(crtc
, &crtc
->config
,
10669 check_shared_dpll_state(struct drm_device
*dev
)
10671 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10672 struct intel_crtc
*crtc
;
10673 struct intel_dpll_hw_state dpll_hw_state
;
10676 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
10677 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
10678 int enabled_crtcs
= 0, active_crtcs
= 0;
10681 memset(&dpll_hw_state
, 0, sizeof(dpll_hw_state
));
10683 DRM_DEBUG_KMS("%s\n", pll
->name
);
10685 active
= pll
->get_hw_state(dev_priv
, pll
, &dpll_hw_state
);
10687 WARN(pll
->active
> pll
->refcount
,
10688 "more active pll users than references: %i vs %i\n",
10689 pll
->active
, pll
->refcount
);
10690 WARN(pll
->active
&& !pll
->on
,
10691 "pll in active use but not on in sw tracking\n");
10692 WARN(pll
->on
&& !pll
->active
,
10693 "pll in on but not on in use in sw tracking\n");
10694 WARN(pll
->on
!= active
,
10695 "pll on state mismatch (expected %i, found %i)\n",
10698 for_each_intel_crtc(dev
, crtc
) {
10699 if (crtc
->base
.enabled
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
10701 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
10704 WARN(pll
->active
!= active_crtcs
,
10705 "pll active crtcs mismatch (expected %i, found %i)\n",
10706 pll
->active
, active_crtcs
);
10707 WARN(pll
->refcount
!= enabled_crtcs
,
10708 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10709 pll
->refcount
, enabled_crtcs
);
10711 WARN(pll
->on
&& memcmp(&pll
->hw_state
, &dpll_hw_state
,
10712 sizeof(dpll_hw_state
)),
10713 "pll hw state mismatch\n");
10718 intel_modeset_check_state(struct drm_device
*dev
)
10720 check_connector_state(dev
);
10721 check_encoder_state(dev
);
10722 check_crtc_state(dev
);
10723 check_shared_dpll_state(dev
);
10726 void ironlake_check_encoder_dotclock(const struct intel_crtc_config
*pipe_config
,
10730 * FDI already provided one idea for the dotclock.
10731 * Yell if the encoder disagrees.
10733 WARN(!intel_fuzzy_clock_check(pipe_config
->adjusted_mode
.crtc_clock
, dotclock
),
10734 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10735 pipe_config
->adjusted_mode
.crtc_clock
, dotclock
);
10738 static void update_scanline_offset(struct intel_crtc
*crtc
)
10740 struct drm_device
*dev
= crtc
->base
.dev
;
10743 * The scanline counter increments at the leading edge of hsync.
10745 * On most platforms it starts counting from vtotal-1 on the
10746 * first active line. That means the scanline counter value is
10747 * always one less than what we would expect. Ie. just after
10748 * start of vblank, which also occurs at start of hsync (on the
10749 * last active line), the scanline counter will read vblank_start-1.
10751 * On gen2 the scanline counter starts counting from 1 instead
10752 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10753 * to keep the value positive), instead of adding one.
10755 * On HSW+ the behaviour of the scanline counter depends on the output
10756 * type. For DP ports it behaves like most other platforms, but on HDMI
10757 * there's an extra 1 line difference. So we need to add two instead of
10758 * one to the value.
10760 if (IS_GEN2(dev
)) {
10761 const struct drm_display_mode
*mode
= &crtc
->config
.adjusted_mode
;
10764 vtotal
= mode
->crtc_vtotal
;
10765 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
10768 crtc
->scanline_offset
= vtotal
- 1;
10769 } else if (HAS_DDI(dev
) &&
10770 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
)) {
10771 crtc
->scanline_offset
= 2;
10773 crtc
->scanline_offset
= 1;
10776 static int __intel_set_mode(struct drm_crtc
*crtc
,
10777 struct drm_display_mode
*mode
,
10778 int x
, int y
, struct drm_framebuffer
*fb
)
10780 struct drm_device
*dev
= crtc
->dev
;
10781 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10782 struct drm_display_mode
*saved_mode
;
10783 struct intel_crtc_config
*pipe_config
= NULL
;
10784 struct intel_crtc
*intel_crtc
;
10785 unsigned disable_pipes
, prepare_pipes
, modeset_pipes
;
10788 saved_mode
= kmalloc(sizeof(*saved_mode
), GFP_KERNEL
);
10792 intel_modeset_affected_pipes(crtc
, &modeset_pipes
,
10793 &prepare_pipes
, &disable_pipes
);
10795 *saved_mode
= crtc
->mode
;
10797 /* Hack: Because we don't (yet) support global modeset on multiple
10798 * crtcs, we don't keep track of the new mode for more than one crtc.
10799 * Hence simply check whether any bit is set in modeset_pipes in all the
10800 * pieces of code that are not yet converted to deal with mutliple crtcs
10801 * changing their mode at the same time. */
10802 if (modeset_pipes
) {
10803 pipe_config
= intel_modeset_pipe_config(crtc
, fb
, mode
);
10804 if (IS_ERR(pipe_config
)) {
10805 ret
= PTR_ERR(pipe_config
);
10806 pipe_config
= NULL
;
10810 intel_dump_pipe_config(to_intel_crtc(crtc
), pipe_config
,
10812 to_intel_crtc(crtc
)->new_config
= pipe_config
;
10816 * See if the config requires any additional preparation, e.g.
10817 * to adjust global state with pipes off. We need to do this
10818 * here so we can get the modeset_pipe updated config for the new
10819 * mode set on this crtc. For other crtcs we need to use the
10820 * adjusted_mode bits in the crtc directly.
10822 if (IS_VALLEYVIEW(dev
)) {
10823 valleyview_modeset_global_pipes(dev
, &prepare_pipes
);
10825 /* may have added more to prepare_pipes than we should */
10826 prepare_pipes
&= ~disable_pipes
;
10829 for_each_intel_crtc_masked(dev
, disable_pipes
, intel_crtc
)
10830 intel_crtc_disable(&intel_crtc
->base
);
10832 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
10833 if (intel_crtc
->base
.enabled
)
10834 dev_priv
->display
.crtc_disable(&intel_crtc
->base
);
10837 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10838 * to set it here already despite that we pass it down the callchain.
10840 if (modeset_pipes
) {
10841 crtc
->mode
= *mode
;
10842 /* mode_set/enable/disable functions rely on a correct pipe
10844 to_intel_crtc(crtc
)->config
= *pipe_config
;
10845 to_intel_crtc(crtc
)->new_config
= &to_intel_crtc(crtc
)->config
;
10848 * Calculate and store various constants which
10849 * are later needed by vblank and swap-completion
10850 * timestamping. They are derived from true hwmode.
10852 drm_calc_timestamping_constants(crtc
,
10853 &pipe_config
->adjusted_mode
);
10856 /* Only after disabling all output pipelines that will be changed can we
10857 * update the the output configuration. */
10858 intel_modeset_update_state(dev
, prepare_pipes
);
10860 if (dev_priv
->display
.modeset_global_resources
)
10861 dev_priv
->display
.modeset_global_resources(dev
);
10863 /* Set up the DPLL and any encoders state that needs to adjust or depend
10866 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
10867 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
10868 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(old_fb
);
10869 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
10871 mutex_lock(&dev
->struct_mutex
);
10872 ret
= intel_pin_and_fence_fb_obj(dev
,
10876 DRM_ERROR("pin & fence failed\n");
10877 mutex_unlock(&dev
->struct_mutex
);
10881 intel_unpin_fb_obj(old_obj
);
10882 i915_gem_track_fb(old_obj
, obj
,
10883 INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
));
10884 mutex_unlock(&dev
->struct_mutex
);
10886 crtc
->primary
->fb
= fb
;
10890 ret
= dev_priv
->display
.crtc_mode_set(&intel_crtc
->base
,
10896 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10897 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
10898 update_scanline_offset(intel_crtc
);
10900 dev_priv
->display
.crtc_enable(&intel_crtc
->base
);
10903 /* FIXME: add subpixel order */
10905 if (ret
&& crtc
->enabled
)
10906 crtc
->mode
= *saved_mode
;
10909 kfree(pipe_config
);
10914 static int intel_set_mode(struct drm_crtc
*crtc
,
10915 struct drm_display_mode
*mode
,
10916 int x
, int y
, struct drm_framebuffer
*fb
)
10920 ret
= __intel_set_mode(crtc
, mode
, x
, y
, fb
);
10923 intel_modeset_check_state(crtc
->dev
);
10928 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
10930 intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
, crtc
->primary
->fb
);
10933 #undef for_each_intel_crtc_masked
10935 static void intel_set_config_free(struct intel_set_config
*config
)
10940 kfree(config
->save_connector_encoders
);
10941 kfree(config
->save_encoder_crtcs
);
10942 kfree(config
->save_crtc_enabled
);
10946 static int intel_set_config_save_state(struct drm_device
*dev
,
10947 struct intel_set_config
*config
)
10949 struct drm_crtc
*crtc
;
10950 struct drm_encoder
*encoder
;
10951 struct drm_connector
*connector
;
10954 config
->save_crtc_enabled
=
10955 kcalloc(dev
->mode_config
.num_crtc
,
10956 sizeof(bool), GFP_KERNEL
);
10957 if (!config
->save_crtc_enabled
)
10960 config
->save_encoder_crtcs
=
10961 kcalloc(dev
->mode_config
.num_encoder
,
10962 sizeof(struct drm_crtc
*), GFP_KERNEL
);
10963 if (!config
->save_encoder_crtcs
)
10966 config
->save_connector_encoders
=
10967 kcalloc(dev
->mode_config
.num_connector
,
10968 sizeof(struct drm_encoder
*), GFP_KERNEL
);
10969 if (!config
->save_connector_encoders
)
10972 /* Copy data. Note that driver private data is not affected.
10973 * Should anything bad happen only the expected state is
10974 * restored, not the drivers personal bookkeeping.
10977 for_each_crtc(dev
, crtc
) {
10978 config
->save_crtc_enabled
[count
++] = crtc
->enabled
;
10982 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
10983 config
->save_encoder_crtcs
[count
++] = encoder
->crtc
;
10987 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
10988 config
->save_connector_encoders
[count
++] = connector
->encoder
;
10994 static void intel_set_config_restore_state(struct drm_device
*dev
,
10995 struct intel_set_config
*config
)
10997 struct intel_crtc
*crtc
;
10998 struct intel_encoder
*encoder
;
10999 struct intel_connector
*connector
;
11003 for_each_intel_crtc(dev
, crtc
) {
11004 crtc
->new_enabled
= config
->save_crtc_enabled
[count
++];
11006 if (crtc
->new_enabled
)
11007 crtc
->new_config
= &crtc
->config
;
11009 crtc
->new_config
= NULL
;
11013 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
11014 encoder
->new_crtc
=
11015 to_intel_crtc(config
->save_encoder_crtcs
[count
++]);
11019 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
11020 connector
->new_encoder
=
11021 to_intel_encoder(config
->save_connector_encoders
[count
++]);
11026 is_crtc_connector_off(struct drm_mode_set
*set
)
11030 if (set
->num_connectors
== 0)
11033 if (WARN_ON(set
->connectors
== NULL
))
11036 for (i
= 0; i
< set
->num_connectors
; i
++)
11037 if (set
->connectors
[i
]->encoder
&&
11038 set
->connectors
[i
]->encoder
->crtc
== set
->crtc
&&
11039 set
->connectors
[i
]->dpms
!= DRM_MODE_DPMS_ON
)
11046 intel_set_config_compute_mode_changes(struct drm_mode_set
*set
,
11047 struct intel_set_config
*config
)
11050 /* We should be able to check here if the fb has the same properties
11051 * and then just flip_or_move it */
11052 if (is_crtc_connector_off(set
)) {
11053 config
->mode_changed
= true;
11054 } else if (set
->crtc
->primary
->fb
!= set
->fb
) {
11056 * If we have no fb, we can only flip as long as the crtc is
11057 * active, otherwise we need a full mode set. The crtc may
11058 * be active if we've only disabled the primary plane, or
11059 * in fastboot situations.
11061 if (set
->crtc
->primary
->fb
== NULL
) {
11062 struct intel_crtc
*intel_crtc
=
11063 to_intel_crtc(set
->crtc
);
11065 if (intel_crtc
->active
) {
11066 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11067 config
->fb_changed
= true;
11069 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11070 config
->mode_changed
= true;
11072 } else if (set
->fb
== NULL
) {
11073 config
->mode_changed
= true;
11074 } else if (set
->fb
->pixel_format
!=
11075 set
->crtc
->primary
->fb
->pixel_format
) {
11076 config
->mode_changed
= true;
11078 config
->fb_changed
= true;
11082 if (set
->fb
&& (set
->x
!= set
->crtc
->x
|| set
->y
!= set
->crtc
->y
))
11083 config
->fb_changed
= true;
11085 if (set
->mode
&& !drm_mode_equal(set
->mode
, &set
->crtc
->mode
)) {
11086 DRM_DEBUG_KMS("modes are different, full mode set\n");
11087 drm_mode_debug_printmodeline(&set
->crtc
->mode
);
11088 drm_mode_debug_printmodeline(set
->mode
);
11089 config
->mode_changed
= true;
11092 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11093 set
->crtc
->base
.id
, config
->mode_changed
, config
->fb_changed
);
11097 intel_modeset_stage_output_state(struct drm_device
*dev
,
11098 struct drm_mode_set
*set
,
11099 struct intel_set_config
*config
)
11101 struct intel_connector
*connector
;
11102 struct intel_encoder
*encoder
;
11103 struct intel_crtc
*crtc
;
11106 /* The upper layers ensure that we either disable a crtc or have a list
11107 * of connectors. For paranoia, double-check this. */
11108 WARN_ON(!set
->fb
&& (set
->num_connectors
!= 0));
11109 WARN_ON(set
->fb
&& (set
->num_connectors
== 0));
11111 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
11113 /* Otherwise traverse passed in connector list and get encoders
11115 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
11116 if (set
->connectors
[ro
] == &connector
->base
) {
11117 connector
->new_encoder
= intel_find_encoder(connector
, to_intel_crtc(set
->crtc
)->pipe
);
11122 /* If we disable the crtc, disable all its connectors. Also, if
11123 * the connector is on the changing crtc but not on the new
11124 * connector list, disable it. */
11125 if ((!set
->fb
|| ro
== set
->num_connectors
) &&
11126 connector
->base
.encoder
&&
11127 connector
->base
.encoder
->crtc
== set
->crtc
) {
11128 connector
->new_encoder
= NULL
;
11130 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11131 connector
->base
.base
.id
,
11132 connector
->base
.name
);
11136 if (&connector
->new_encoder
->base
!= connector
->base
.encoder
) {
11137 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11138 config
->mode_changed
= true;
11141 /* connector->new_encoder is now updated for all connectors. */
11143 /* Update crtc of enabled connectors. */
11144 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
11146 struct drm_crtc
*new_crtc
;
11148 if (!connector
->new_encoder
)
11151 new_crtc
= connector
->new_encoder
->base
.crtc
;
11153 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
11154 if (set
->connectors
[ro
] == &connector
->base
)
11155 new_crtc
= set
->crtc
;
11158 /* Make sure the new CRTC will work with the encoder */
11159 if (!drm_encoder_crtc_ok(&connector
->new_encoder
->base
,
11163 connector
->new_encoder
->new_crtc
= to_intel_crtc(new_crtc
);
11165 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11166 connector
->base
.base
.id
,
11167 connector
->base
.name
,
11168 new_crtc
->base
.id
);
11171 /* Check for any encoders that needs to be disabled. */
11172 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
11174 int num_connectors
= 0;
11175 list_for_each_entry(connector
,
11176 &dev
->mode_config
.connector_list
,
11178 if (connector
->new_encoder
== encoder
) {
11179 WARN_ON(!connector
->new_encoder
->new_crtc
);
11184 if (num_connectors
== 0)
11185 encoder
->new_crtc
= NULL
;
11186 else if (num_connectors
> 1)
11189 /* Only now check for crtc changes so we don't miss encoders
11190 * that will be disabled. */
11191 if (&encoder
->new_crtc
->base
!= encoder
->base
.crtc
) {
11192 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11193 config
->mode_changed
= true;
11196 /* Now we've also updated encoder->new_crtc for all encoders. */
11197 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
11199 if (connector
->new_encoder
)
11200 if (connector
->new_encoder
!= connector
->encoder
)
11201 connector
->encoder
= connector
->new_encoder
;
11203 for_each_intel_crtc(dev
, crtc
) {
11204 crtc
->new_enabled
= false;
11206 list_for_each_entry(encoder
,
11207 &dev
->mode_config
.encoder_list
,
11209 if (encoder
->new_crtc
== crtc
) {
11210 crtc
->new_enabled
= true;
11215 if (crtc
->new_enabled
!= crtc
->base
.enabled
) {
11216 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11217 crtc
->new_enabled
? "en" : "dis");
11218 config
->mode_changed
= true;
11221 if (crtc
->new_enabled
)
11222 crtc
->new_config
= &crtc
->config
;
11224 crtc
->new_config
= NULL
;
11230 static void disable_crtc_nofb(struct intel_crtc
*crtc
)
11232 struct drm_device
*dev
= crtc
->base
.dev
;
11233 struct intel_encoder
*encoder
;
11234 struct intel_connector
*connector
;
11236 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11237 pipe_name(crtc
->pipe
));
11239 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
11240 if (connector
->new_encoder
&&
11241 connector
->new_encoder
->new_crtc
== crtc
)
11242 connector
->new_encoder
= NULL
;
11245 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
11246 if (encoder
->new_crtc
== crtc
)
11247 encoder
->new_crtc
= NULL
;
11250 crtc
->new_enabled
= false;
11251 crtc
->new_config
= NULL
;
11254 static int intel_crtc_set_config(struct drm_mode_set
*set
)
11256 struct drm_device
*dev
;
11257 struct drm_mode_set save_set
;
11258 struct intel_set_config
*config
;
11262 BUG_ON(!set
->crtc
);
11263 BUG_ON(!set
->crtc
->helper_private
);
11265 /* Enforce sane interface api - has been abused by the fb helper. */
11266 BUG_ON(!set
->mode
&& set
->fb
);
11267 BUG_ON(set
->fb
&& set
->num_connectors
== 0);
11270 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11271 set
->crtc
->base
.id
, set
->fb
->base
.id
,
11272 (int)set
->num_connectors
, set
->x
, set
->y
);
11274 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set
->crtc
->base
.id
);
11277 dev
= set
->crtc
->dev
;
11280 config
= kzalloc(sizeof(*config
), GFP_KERNEL
);
11284 ret
= intel_set_config_save_state(dev
, config
);
11288 save_set
.crtc
= set
->crtc
;
11289 save_set
.mode
= &set
->crtc
->mode
;
11290 save_set
.x
= set
->crtc
->x
;
11291 save_set
.y
= set
->crtc
->y
;
11292 save_set
.fb
= set
->crtc
->primary
->fb
;
11294 /* Compute whether we need a full modeset, only an fb base update or no
11295 * change at all. In the future we might also check whether only the
11296 * mode changed, e.g. for LVDS where we only change the panel fitter in
11298 intel_set_config_compute_mode_changes(set
, config
);
11300 ret
= intel_modeset_stage_output_state(dev
, set
, config
);
11304 if (config
->mode_changed
) {
11305 ret
= intel_set_mode(set
->crtc
, set
->mode
,
11306 set
->x
, set
->y
, set
->fb
);
11307 } else if (config
->fb_changed
) {
11308 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11309 struct intel_crtc
*intel_crtc
= to_intel_crtc(set
->crtc
);
11311 intel_crtc_wait_for_pending_flips(set
->crtc
);
11313 ret
= intel_pipe_set_base(set
->crtc
,
11314 set
->x
, set
->y
, set
->fb
);
11317 * We need to make sure the primary plane is re-enabled if it
11318 * has previously been turned off.
11320 if (!intel_crtc
->primary_enabled
&& ret
== 0) {
11321 WARN_ON(!intel_crtc
->active
);
11322 intel_enable_primary_hw_plane(dev_priv
, intel_crtc
->plane
,
11327 * In the fastboot case this may be our only check of the
11328 * state after boot. It would be better to only do it on
11329 * the first update, but we don't have a nice way of doing that
11330 * (and really, set_config isn't used much for high freq page
11331 * flipping, so increasing its cost here shouldn't be a big
11334 if (i915
.fastboot
&& ret
== 0)
11335 intel_modeset_check_state(set
->crtc
->dev
);
11339 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11340 set
->crtc
->base
.id
, ret
);
11342 intel_set_config_restore_state(dev
, config
);
11345 * HACK: if the pipe was on, but we didn't have a framebuffer,
11346 * force the pipe off to avoid oopsing in the modeset code
11347 * due to fb==NULL. This should only happen during boot since
11348 * we don't yet reconstruct the FB from the hardware state.
11350 if (to_intel_crtc(save_set
.crtc
)->new_enabled
&& !save_set
.fb
)
11351 disable_crtc_nofb(to_intel_crtc(save_set
.crtc
));
11353 /* Try to restore the config */
11354 if (config
->mode_changed
&&
11355 intel_set_mode(save_set
.crtc
, save_set
.mode
,
11356 save_set
.x
, save_set
.y
, save_set
.fb
))
11357 DRM_ERROR("failed to restore config after modeset failure\n");
11361 intel_set_config_free(config
);
11365 static const struct drm_crtc_funcs intel_crtc_funcs
= {
11366 .gamma_set
= intel_crtc_gamma_set
,
11367 .set_config
= intel_crtc_set_config
,
11368 .destroy
= intel_crtc_destroy
,
11369 .page_flip
= intel_crtc_page_flip
,
11372 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private
*dev_priv
,
11373 struct intel_shared_dpll
*pll
,
11374 struct intel_dpll_hw_state
*hw_state
)
11378 if (!intel_display_power_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
11381 val
= I915_READ(PCH_DPLL(pll
->id
));
11382 hw_state
->dpll
= val
;
11383 hw_state
->fp0
= I915_READ(PCH_FP0(pll
->id
));
11384 hw_state
->fp1
= I915_READ(PCH_FP1(pll
->id
));
11386 return val
& DPLL_VCO_ENABLE
;
11389 static void ibx_pch_dpll_mode_set(struct drm_i915_private
*dev_priv
,
11390 struct intel_shared_dpll
*pll
)
11392 I915_WRITE(PCH_FP0(pll
->id
), pll
->hw_state
.fp0
);
11393 I915_WRITE(PCH_FP1(pll
->id
), pll
->hw_state
.fp1
);
11396 static void ibx_pch_dpll_enable(struct drm_i915_private
*dev_priv
,
11397 struct intel_shared_dpll
*pll
)
11399 /* PCH refclock must be enabled first */
11400 ibx_assert_pch_refclk_enabled(dev_priv
);
11402 I915_WRITE(PCH_DPLL(pll
->id
), pll
->hw_state
.dpll
);
11404 /* Wait for the clocks to stabilize. */
11405 POSTING_READ(PCH_DPLL(pll
->id
));
11408 /* The pixel multiplier can only be updated once the
11409 * DPLL is enabled and the clocks are stable.
11411 * So write it again.
11413 I915_WRITE(PCH_DPLL(pll
->id
), pll
->hw_state
.dpll
);
11414 POSTING_READ(PCH_DPLL(pll
->id
));
11418 static void ibx_pch_dpll_disable(struct drm_i915_private
*dev_priv
,
11419 struct intel_shared_dpll
*pll
)
11421 struct drm_device
*dev
= dev_priv
->dev
;
11422 struct intel_crtc
*crtc
;
11424 /* Make sure no transcoder isn't still depending on us. */
11425 for_each_intel_crtc(dev
, crtc
) {
11426 if (intel_crtc_to_shared_dpll(crtc
) == pll
)
11427 assert_pch_transcoder_disabled(dev_priv
, crtc
->pipe
);
11430 I915_WRITE(PCH_DPLL(pll
->id
), 0);
11431 POSTING_READ(PCH_DPLL(pll
->id
));
11435 static char *ibx_pch_dpll_names
[] = {
11440 static void ibx_pch_dpll_init(struct drm_device
*dev
)
11442 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11445 dev_priv
->num_shared_dpll
= 2;
11447 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
11448 dev_priv
->shared_dplls
[i
].id
= i
;
11449 dev_priv
->shared_dplls
[i
].name
= ibx_pch_dpll_names
[i
];
11450 dev_priv
->shared_dplls
[i
].mode_set
= ibx_pch_dpll_mode_set
;
11451 dev_priv
->shared_dplls
[i
].enable
= ibx_pch_dpll_enable
;
11452 dev_priv
->shared_dplls
[i
].disable
= ibx_pch_dpll_disable
;
11453 dev_priv
->shared_dplls
[i
].get_hw_state
=
11454 ibx_pch_dpll_get_hw_state
;
11458 static void intel_shared_dpll_init(struct drm_device
*dev
)
11460 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11463 intel_ddi_pll_init(dev
);
11464 else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
11465 ibx_pch_dpll_init(dev
);
11467 dev_priv
->num_shared_dpll
= 0;
11469 BUG_ON(dev_priv
->num_shared_dpll
> I915_NUM_PLLS
);
11473 intel_primary_plane_disable(struct drm_plane
*plane
)
11475 struct drm_device
*dev
= plane
->dev
;
11476 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11477 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
11478 struct intel_crtc
*intel_crtc
;
11483 BUG_ON(!plane
->crtc
);
11485 intel_crtc
= to_intel_crtc(plane
->crtc
);
11488 * Even though we checked plane->fb above, it's still possible that
11489 * the primary plane has been implicitly disabled because the crtc
11490 * coordinates given weren't visible, or because we detected
11491 * that it was 100% covered by a sprite plane. Or, the CRTC may be
11492 * off and we've set a fb, but haven't actually turned on the CRTC yet.
11493 * In either case, we need to unpin the FB and let the fb pointer get
11494 * updated, but otherwise we don't need to touch the hardware.
11496 if (!intel_crtc
->primary_enabled
)
11497 goto disable_unpin
;
11499 intel_crtc_wait_for_pending_flips(plane
->crtc
);
11500 intel_disable_primary_hw_plane(dev_priv
, intel_plane
->plane
,
11501 intel_plane
->pipe
);
11503 mutex_lock(&dev
->struct_mutex
);
11504 i915_gem_track_fb(intel_fb_obj(plane
->fb
), NULL
,
11505 INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
));
11506 intel_unpin_fb_obj(intel_fb_obj(plane
->fb
));
11507 mutex_unlock(&dev
->struct_mutex
);
11514 intel_primary_plane_setplane(struct drm_plane
*plane
, struct drm_crtc
*crtc
,
11515 struct drm_framebuffer
*fb
, int crtc_x
, int crtc_y
,
11516 unsigned int crtc_w
, unsigned int crtc_h
,
11517 uint32_t src_x
, uint32_t src_y
,
11518 uint32_t src_w
, uint32_t src_h
)
11520 struct drm_device
*dev
= crtc
->dev
;
11521 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11522 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11523 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
11524 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
11525 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(plane
->fb
);
11526 struct drm_rect dest
= {
11527 /* integer pixels */
11530 .x2
= crtc_x
+ crtc_w
,
11531 .y2
= crtc_y
+ crtc_h
,
11533 struct drm_rect src
= {
11534 /* 16.16 fixed point */
11537 .x2
= src_x
+ src_w
,
11538 .y2
= src_y
+ src_h
,
11540 const struct drm_rect clip
= {
11541 /* integer pixels */
11542 .x2
= intel_crtc
->active
? intel_crtc
->config
.pipe_src_w
: 0,
11543 .y2
= intel_crtc
->active
? intel_crtc
->config
.pipe_src_h
: 0,
11548 ret
= drm_plane_helper_check_update(plane
, crtc
, fb
,
11549 &src
, &dest
, &clip
,
11550 DRM_PLANE_HELPER_NO_SCALING
,
11551 DRM_PLANE_HELPER_NO_SCALING
,
11552 false, true, &visible
);
11558 * If the CRTC isn't enabled, we're just pinning the framebuffer,
11559 * updating the fb pointer, and returning without touching the
11560 * hardware. This allows us to later do a drmModeSetCrtc with fb=-1 to
11561 * turn on the display with all planes setup as desired.
11563 if (!crtc
->enabled
) {
11564 mutex_lock(&dev
->struct_mutex
);
11567 * If we already called setplane while the crtc was disabled,
11568 * we may have an fb pinned; unpin it.
11571 intel_unpin_fb_obj(old_obj
);
11573 i915_gem_track_fb(old_obj
, obj
,
11574 INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
));
11576 /* Pin and return without programming hardware */
11577 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, NULL
);
11578 mutex_unlock(&dev
->struct_mutex
);
11583 intel_crtc_wait_for_pending_flips(crtc
);
11586 * If clipping results in a non-visible primary plane, we'll disable
11587 * the primary plane. Note that this is a bit different than what
11588 * happens if userspace explicitly disables the plane by passing fb=0
11589 * because plane->fb still gets set and pinned.
11592 mutex_lock(&dev
->struct_mutex
);
11595 * Try to pin the new fb first so that we can bail out if we
11598 if (plane
->fb
!= fb
) {
11599 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, NULL
);
11601 mutex_unlock(&dev
->struct_mutex
);
11606 i915_gem_track_fb(old_obj
, obj
,
11607 INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
));
11609 if (intel_crtc
->primary_enabled
)
11610 intel_disable_primary_hw_plane(dev_priv
,
11611 intel_plane
->plane
,
11612 intel_plane
->pipe
);
11615 if (plane
->fb
!= fb
)
11617 intel_unpin_fb_obj(old_obj
);
11619 mutex_unlock(&dev
->struct_mutex
);
11624 ret
= intel_pipe_set_base(crtc
, src
.x1
, src
.y1
, fb
);
11628 if (!intel_crtc
->primary_enabled
)
11629 intel_enable_primary_hw_plane(dev_priv
, intel_crtc
->plane
,
11635 /* Common destruction function for both primary and cursor planes */
11636 static void intel_plane_destroy(struct drm_plane
*plane
)
11638 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
11639 drm_plane_cleanup(plane
);
11640 kfree(intel_plane
);
11643 static const struct drm_plane_funcs intel_primary_plane_funcs
= {
11644 .update_plane
= intel_primary_plane_setplane
,
11645 .disable_plane
= intel_primary_plane_disable
,
11646 .destroy
= intel_plane_destroy
,
11649 static struct drm_plane
*intel_primary_plane_create(struct drm_device
*dev
,
11652 struct intel_plane
*primary
;
11653 const uint32_t *intel_primary_formats
;
11656 primary
= kzalloc(sizeof(*primary
), GFP_KERNEL
);
11657 if (primary
== NULL
)
11660 primary
->can_scale
= false;
11661 primary
->max_downscale
= 1;
11662 primary
->pipe
= pipe
;
11663 primary
->plane
= pipe
;
11664 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4)
11665 primary
->plane
= !pipe
;
11667 if (INTEL_INFO(dev
)->gen
<= 3) {
11668 intel_primary_formats
= intel_primary_formats_gen2
;
11669 num_formats
= ARRAY_SIZE(intel_primary_formats_gen2
);
11671 intel_primary_formats
= intel_primary_formats_gen4
;
11672 num_formats
= ARRAY_SIZE(intel_primary_formats_gen4
);
11675 drm_universal_plane_init(dev
, &primary
->base
, 0,
11676 &intel_primary_plane_funcs
,
11677 intel_primary_formats
, num_formats
,
11678 DRM_PLANE_TYPE_PRIMARY
);
11679 return &primary
->base
;
11683 intel_cursor_plane_disable(struct drm_plane
*plane
)
11688 BUG_ON(!plane
->crtc
);
11690 return intel_crtc_cursor_set_obj(plane
->crtc
, NULL
, 0, 0);
11694 intel_cursor_plane_update(struct drm_plane
*plane
, struct drm_crtc
*crtc
,
11695 struct drm_framebuffer
*fb
, int crtc_x
, int crtc_y
,
11696 unsigned int crtc_w
, unsigned int crtc_h
,
11697 uint32_t src_x
, uint32_t src_y
,
11698 uint32_t src_w
, uint32_t src_h
)
11700 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11701 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
11702 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
11703 struct drm_rect dest
= {
11704 /* integer pixels */
11707 .x2
= crtc_x
+ crtc_w
,
11708 .y2
= crtc_y
+ crtc_h
,
11710 struct drm_rect src
= {
11711 /* 16.16 fixed point */
11714 .x2
= src_x
+ src_w
,
11715 .y2
= src_y
+ src_h
,
11717 const struct drm_rect clip
= {
11718 /* integer pixels */
11719 .x2
= intel_crtc
->active
? intel_crtc
->config
.pipe_src_w
: 0,
11720 .y2
= intel_crtc
->active
? intel_crtc
->config
.pipe_src_h
: 0,
11725 ret
= drm_plane_helper_check_update(plane
, crtc
, fb
,
11726 &src
, &dest
, &clip
,
11727 DRM_PLANE_HELPER_NO_SCALING
,
11728 DRM_PLANE_HELPER_NO_SCALING
,
11729 true, true, &visible
);
11733 crtc
->cursor_x
= crtc_x
;
11734 crtc
->cursor_y
= crtc_y
;
11735 if (fb
!= crtc
->cursor
->fb
) {
11736 return intel_crtc_cursor_set_obj(crtc
, obj
, crtc_w
, crtc_h
);
11738 intel_crtc_update_cursor(crtc
, visible
);
11742 static const struct drm_plane_funcs intel_cursor_plane_funcs
= {
11743 .update_plane
= intel_cursor_plane_update
,
11744 .disable_plane
= intel_cursor_plane_disable
,
11745 .destroy
= intel_plane_destroy
,
11748 static struct drm_plane
*intel_cursor_plane_create(struct drm_device
*dev
,
11751 struct intel_plane
*cursor
;
11753 cursor
= kzalloc(sizeof(*cursor
), GFP_KERNEL
);
11754 if (cursor
== NULL
)
11757 cursor
->can_scale
= false;
11758 cursor
->max_downscale
= 1;
11759 cursor
->pipe
= pipe
;
11760 cursor
->plane
= pipe
;
11762 drm_universal_plane_init(dev
, &cursor
->base
, 0,
11763 &intel_cursor_plane_funcs
,
11764 intel_cursor_formats
,
11765 ARRAY_SIZE(intel_cursor_formats
),
11766 DRM_PLANE_TYPE_CURSOR
);
11767 return &cursor
->base
;
11770 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
11772 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11773 struct intel_crtc
*intel_crtc
;
11774 struct drm_plane
*primary
= NULL
;
11775 struct drm_plane
*cursor
= NULL
;
11778 intel_crtc
= kzalloc(sizeof(*intel_crtc
), GFP_KERNEL
);
11779 if (intel_crtc
== NULL
)
11782 primary
= intel_primary_plane_create(dev
, pipe
);
11786 cursor
= intel_cursor_plane_create(dev
, pipe
);
11790 ret
= drm_crtc_init_with_planes(dev
, &intel_crtc
->base
, primary
,
11791 cursor
, &intel_crtc_funcs
);
11795 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
11796 for (i
= 0; i
< 256; i
++) {
11797 intel_crtc
->lut_r
[i
] = i
;
11798 intel_crtc
->lut_g
[i
] = i
;
11799 intel_crtc
->lut_b
[i
] = i
;
11803 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
11804 * is hooked to pipe B. Hence we want plane A feeding pipe B.
11806 intel_crtc
->pipe
= pipe
;
11807 intel_crtc
->plane
= pipe
;
11808 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4) {
11809 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
11810 intel_crtc
->plane
= !pipe
;
11813 intel_crtc
->cursor_base
= ~0;
11814 intel_crtc
->cursor_cntl
= ~0;
11816 init_waitqueue_head(&intel_crtc
->vbl_wait
);
11818 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
11819 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
11820 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
11821 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
11823 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
11825 WARN_ON(drm_crtc_index(&intel_crtc
->base
) != intel_crtc
->pipe
);
11830 drm_plane_cleanup(primary
);
11832 drm_plane_cleanup(cursor
);
11836 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
)
11838 struct drm_encoder
*encoder
= connector
->base
.encoder
;
11839 struct drm_device
*dev
= connector
->base
.dev
;
11841 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
11844 return INVALID_PIPE
;
11846 return to_intel_crtc(encoder
->crtc
)->pipe
;
11849 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
11850 struct drm_file
*file
)
11852 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
11853 struct drm_crtc
*drmmode_crtc
;
11854 struct intel_crtc
*crtc
;
11856 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
11859 drmmode_crtc
= drm_crtc_find(dev
, pipe_from_crtc_id
->crtc_id
);
11861 if (!drmmode_crtc
) {
11862 DRM_ERROR("no such CRTC id\n");
11866 crtc
= to_intel_crtc(drmmode_crtc
);
11867 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
11872 static int intel_encoder_clones(struct intel_encoder
*encoder
)
11874 struct drm_device
*dev
= encoder
->base
.dev
;
11875 struct intel_encoder
*source_encoder
;
11876 int index_mask
= 0;
11879 list_for_each_entry(source_encoder
,
11880 &dev
->mode_config
.encoder_list
, base
.head
) {
11881 if (encoders_cloneable(encoder
, source_encoder
))
11882 index_mask
|= (1 << entry
);
11890 static bool has_edp_a(struct drm_device
*dev
)
11892 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11894 if (!IS_MOBILE(dev
))
11897 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
11900 if (IS_GEN5(dev
) && (I915_READ(FUSE_STRAP
) & ILK_eDP_A_DISABLE
))
11906 const char *intel_output_name(int output
)
11908 static const char *names
[] = {
11909 [INTEL_OUTPUT_UNUSED
] = "Unused",
11910 [INTEL_OUTPUT_ANALOG
] = "Analog",
11911 [INTEL_OUTPUT_DVO
] = "DVO",
11912 [INTEL_OUTPUT_SDVO
] = "SDVO",
11913 [INTEL_OUTPUT_LVDS
] = "LVDS",
11914 [INTEL_OUTPUT_TVOUT
] = "TV",
11915 [INTEL_OUTPUT_HDMI
] = "HDMI",
11916 [INTEL_OUTPUT_DISPLAYPORT
] = "DisplayPort",
11917 [INTEL_OUTPUT_EDP
] = "eDP",
11918 [INTEL_OUTPUT_DSI
] = "DSI",
11919 [INTEL_OUTPUT_UNKNOWN
] = "Unknown",
11922 if (output
< 0 || output
>= ARRAY_SIZE(names
) || !names
[output
])
11925 return names
[output
];
11928 static bool intel_crt_present(struct drm_device
*dev
)
11930 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11935 if (IS_CHERRYVIEW(dev
))
11938 if (IS_VALLEYVIEW(dev
) && !dev_priv
->vbt
.int_crt_support
)
11944 static void intel_setup_outputs(struct drm_device
*dev
)
11946 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11947 struct intel_encoder
*encoder
;
11948 bool dpd_is_edp
= false;
11950 intel_lvds_init(dev
);
11952 if (intel_crt_present(dev
))
11953 intel_crt_init(dev
);
11955 if (HAS_DDI(dev
)) {
11958 /* Haswell uses DDI functions to detect digital outputs */
11959 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
11960 /* DDI A only supports eDP */
11962 intel_ddi_init(dev
, PORT_A
);
11964 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
11966 found
= I915_READ(SFUSE_STRAP
);
11968 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
11969 intel_ddi_init(dev
, PORT_B
);
11970 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
11971 intel_ddi_init(dev
, PORT_C
);
11972 if (found
& SFUSE_STRAP_DDID_DETECTED
)
11973 intel_ddi_init(dev
, PORT_D
);
11974 } else if (HAS_PCH_SPLIT(dev
)) {
11976 dpd_is_edp
= intel_dp_is_edp(dev
, PORT_D
);
11978 if (has_edp_a(dev
))
11979 intel_dp_init(dev
, DP_A
, PORT_A
);
11981 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
11982 /* PCH SDVOB multiplex with HDMIB */
11983 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
11985 intel_hdmi_init(dev
, PCH_HDMIB
, PORT_B
);
11986 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
11987 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
11990 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
11991 intel_hdmi_init(dev
, PCH_HDMIC
, PORT_C
);
11993 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
11994 intel_hdmi_init(dev
, PCH_HDMID
, PORT_D
);
11996 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
11997 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
11999 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
12000 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
12001 } else if (IS_VALLEYVIEW(dev
)) {
12002 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIB
) & SDVO_DETECTED
) {
12003 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIB
,
12005 if (I915_READ(VLV_DISPLAY_BASE
+ DP_B
) & DP_DETECTED
)
12006 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_B
, PORT_B
);
12009 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIC
) & SDVO_DETECTED
) {
12010 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIC
,
12012 if (I915_READ(VLV_DISPLAY_BASE
+ DP_C
) & DP_DETECTED
)
12013 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_C
, PORT_C
);
12016 if (IS_CHERRYVIEW(dev
)) {
12017 if (I915_READ(VLV_DISPLAY_BASE
+ CHV_HDMID
) & SDVO_DETECTED
) {
12018 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ CHV_HDMID
,
12020 if (I915_READ(VLV_DISPLAY_BASE
+ DP_D
) & DP_DETECTED
)
12021 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_D
, PORT_D
);
12025 intel_dsi_init(dev
);
12026 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
12027 bool found
= false;
12029 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
12030 DRM_DEBUG_KMS("probing SDVOB\n");
12031 found
= intel_sdvo_init(dev
, GEN3_SDVOB
, true);
12032 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
12033 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12034 intel_hdmi_init(dev
, GEN4_HDMIB
, PORT_B
);
12037 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
))
12038 intel_dp_init(dev
, DP_B
, PORT_B
);
12041 /* Before G4X SDVOC doesn't have its own detect register */
12043 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
12044 DRM_DEBUG_KMS("probing SDVOC\n");
12045 found
= intel_sdvo_init(dev
, GEN3_SDVOC
, false);
12048 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
12050 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
12051 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12052 intel_hdmi_init(dev
, GEN4_HDMIC
, PORT_C
);
12054 if (SUPPORTS_INTEGRATED_DP(dev
))
12055 intel_dp_init(dev
, DP_C
, PORT_C
);
12058 if (SUPPORTS_INTEGRATED_DP(dev
) &&
12059 (I915_READ(DP_D
) & DP_DETECTED
))
12060 intel_dp_init(dev
, DP_D
, PORT_D
);
12061 } else if (IS_GEN2(dev
))
12062 intel_dvo_init(dev
);
12064 if (SUPPORTS_TV(dev
))
12065 intel_tv_init(dev
);
12067 intel_edp_psr_init(dev
);
12069 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
12070 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
12071 encoder
->base
.possible_clones
=
12072 intel_encoder_clones(encoder
);
12075 intel_init_pch_refclk(dev
);
12077 drm_helper_move_panel_connectors_to_head(dev
);
12080 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
12082 struct drm_device
*dev
= fb
->dev
;
12083 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
12085 drm_framebuffer_cleanup(fb
);
12086 mutex_lock(&dev
->struct_mutex
);
12087 WARN_ON(!intel_fb
->obj
->framebuffer_references
--);
12088 drm_gem_object_unreference(&intel_fb
->obj
->base
);
12089 mutex_unlock(&dev
->struct_mutex
);
12093 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
12094 struct drm_file
*file
,
12095 unsigned int *handle
)
12097 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
12098 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
12100 return drm_gem_handle_create(file
, &obj
->base
, handle
);
12103 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
12104 .destroy
= intel_user_framebuffer_destroy
,
12105 .create_handle
= intel_user_framebuffer_create_handle
,
12108 static int intel_framebuffer_init(struct drm_device
*dev
,
12109 struct intel_framebuffer
*intel_fb
,
12110 struct drm_mode_fb_cmd2
*mode_cmd
,
12111 struct drm_i915_gem_object
*obj
)
12113 int aligned_height
;
12117 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
12119 if (obj
->tiling_mode
== I915_TILING_Y
) {
12120 DRM_DEBUG("hardware does not support tiling Y\n");
12124 if (mode_cmd
->pitches
[0] & 63) {
12125 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12126 mode_cmd
->pitches
[0]);
12130 if (INTEL_INFO(dev
)->gen
>= 5 && !IS_VALLEYVIEW(dev
)) {
12131 pitch_limit
= 32*1024;
12132 } else if (INTEL_INFO(dev
)->gen
>= 4) {
12133 if (obj
->tiling_mode
)
12134 pitch_limit
= 16*1024;
12136 pitch_limit
= 32*1024;
12137 } else if (INTEL_INFO(dev
)->gen
>= 3) {
12138 if (obj
->tiling_mode
)
12139 pitch_limit
= 8*1024;
12141 pitch_limit
= 16*1024;
12143 /* XXX DSPC is limited to 4k tiled */
12144 pitch_limit
= 8*1024;
12146 if (mode_cmd
->pitches
[0] > pitch_limit
) {
12147 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12148 obj
->tiling_mode
? "tiled" : "linear",
12149 mode_cmd
->pitches
[0], pitch_limit
);
12153 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
12154 mode_cmd
->pitches
[0] != obj
->stride
) {
12155 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12156 mode_cmd
->pitches
[0], obj
->stride
);
12160 /* Reject formats not supported by any plane early. */
12161 switch (mode_cmd
->pixel_format
) {
12162 case DRM_FORMAT_C8
:
12163 case DRM_FORMAT_RGB565
:
12164 case DRM_FORMAT_XRGB8888
:
12165 case DRM_FORMAT_ARGB8888
:
12167 case DRM_FORMAT_XRGB1555
:
12168 case DRM_FORMAT_ARGB1555
:
12169 if (INTEL_INFO(dev
)->gen
> 3) {
12170 DRM_DEBUG("unsupported pixel format: %s\n",
12171 drm_get_format_name(mode_cmd
->pixel_format
));
12175 case DRM_FORMAT_XBGR8888
:
12176 case DRM_FORMAT_ABGR8888
:
12177 case DRM_FORMAT_XRGB2101010
:
12178 case DRM_FORMAT_ARGB2101010
:
12179 case DRM_FORMAT_XBGR2101010
:
12180 case DRM_FORMAT_ABGR2101010
:
12181 if (INTEL_INFO(dev
)->gen
< 4) {
12182 DRM_DEBUG("unsupported pixel format: %s\n",
12183 drm_get_format_name(mode_cmd
->pixel_format
));
12187 case DRM_FORMAT_YUYV
:
12188 case DRM_FORMAT_UYVY
:
12189 case DRM_FORMAT_YVYU
:
12190 case DRM_FORMAT_VYUY
:
12191 if (INTEL_INFO(dev
)->gen
< 5) {
12192 DRM_DEBUG("unsupported pixel format: %s\n",
12193 drm_get_format_name(mode_cmd
->pixel_format
));
12198 DRM_DEBUG("unsupported pixel format: %s\n",
12199 drm_get_format_name(mode_cmd
->pixel_format
));
12203 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12204 if (mode_cmd
->offsets
[0] != 0)
12207 aligned_height
= intel_align_height(dev
, mode_cmd
->height
,
12209 /* FIXME drm helper for size checks (especially planar formats)? */
12210 if (obj
->base
.size
< aligned_height
* mode_cmd
->pitches
[0])
12213 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
12214 intel_fb
->obj
= obj
;
12215 intel_fb
->obj
->framebuffer_references
++;
12217 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
12219 DRM_ERROR("framebuffer init failed %d\n", ret
);
12226 static struct drm_framebuffer
*
12227 intel_user_framebuffer_create(struct drm_device
*dev
,
12228 struct drm_file
*filp
,
12229 struct drm_mode_fb_cmd2
*mode_cmd
)
12231 struct drm_i915_gem_object
*obj
;
12233 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
12234 mode_cmd
->handles
[0]));
12235 if (&obj
->base
== NULL
)
12236 return ERR_PTR(-ENOENT
);
12238 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
12241 #ifndef CONFIG_DRM_I915_FBDEV
12242 static inline void intel_fbdev_output_poll_changed(struct drm_device
*dev
)
12247 static const struct drm_mode_config_funcs intel_mode_funcs
= {
12248 .fb_create
= intel_user_framebuffer_create
,
12249 .output_poll_changed
= intel_fbdev_output_poll_changed
,
12252 /* Set up chip specific display functions */
12253 static void intel_init_display(struct drm_device
*dev
)
12255 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12257 if (HAS_PCH_SPLIT(dev
) || IS_G4X(dev
))
12258 dev_priv
->display
.find_dpll
= g4x_find_best_dpll
;
12259 else if (IS_CHERRYVIEW(dev
))
12260 dev_priv
->display
.find_dpll
= chv_find_best_dpll
;
12261 else if (IS_VALLEYVIEW(dev
))
12262 dev_priv
->display
.find_dpll
= vlv_find_best_dpll
;
12263 else if (IS_PINEVIEW(dev
))
12264 dev_priv
->display
.find_dpll
= pnv_find_best_dpll
;
12266 dev_priv
->display
.find_dpll
= i9xx_find_best_dpll
;
12268 if (HAS_DDI(dev
)) {
12269 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
12270 dev_priv
->display
.get_plane_config
= ironlake_get_plane_config
;
12271 dev_priv
->display
.crtc_mode_set
= haswell_crtc_mode_set
;
12272 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
12273 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
12274 dev_priv
->display
.off
= ironlake_crtc_off
;
12275 dev_priv
->display
.update_primary_plane
=
12276 ironlake_update_primary_plane
;
12277 } else if (HAS_PCH_SPLIT(dev
)) {
12278 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
12279 dev_priv
->display
.get_plane_config
= ironlake_get_plane_config
;
12280 dev_priv
->display
.crtc_mode_set
= ironlake_crtc_mode_set
;
12281 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
12282 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
12283 dev_priv
->display
.off
= ironlake_crtc_off
;
12284 dev_priv
->display
.update_primary_plane
=
12285 ironlake_update_primary_plane
;
12286 } else if (IS_VALLEYVIEW(dev
)) {
12287 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
12288 dev_priv
->display
.get_plane_config
= i9xx_get_plane_config
;
12289 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
12290 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
12291 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
12292 dev_priv
->display
.off
= i9xx_crtc_off
;
12293 dev_priv
->display
.update_primary_plane
=
12294 i9xx_update_primary_plane
;
12296 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
12297 dev_priv
->display
.get_plane_config
= i9xx_get_plane_config
;
12298 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
12299 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
12300 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
12301 dev_priv
->display
.off
= i9xx_crtc_off
;
12302 dev_priv
->display
.update_primary_plane
=
12303 i9xx_update_primary_plane
;
12306 /* Returns the core display clock speed */
12307 if (IS_VALLEYVIEW(dev
))
12308 dev_priv
->display
.get_display_clock_speed
=
12309 valleyview_get_display_clock_speed
;
12310 else if (IS_I945G(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
12311 dev_priv
->display
.get_display_clock_speed
=
12312 i945_get_display_clock_speed
;
12313 else if (IS_I915G(dev
))
12314 dev_priv
->display
.get_display_clock_speed
=
12315 i915_get_display_clock_speed
;
12316 else if (IS_I945GM(dev
) || IS_845G(dev
))
12317 dev_priv
->display
.get_display_clock_speed
=
12318 i9xx_misc_get_display_clock_speed
;
12319 else if (IS_PINEVIEW(dev
))
12320 dev_priv
->display
.get_display_clock_speed
=
12321 pnv_get_display_clock_speed
;
12322 else if (IS_I915GM(dev
))
12323 dev_priv
->display
.get_display_clock_speed
=
12324 i915gm_get_display_clock_speed
;
12325 else if (IS_I865G(dev
))
12326 dev_priv
->display
.get_display_clock_speed
=
12327 i865_get_display_clock_speed
;
12328 else if (IS_I85X(dev
))
12329 dev_priv
->display
.get_display_clock_speed
=
12330 i855_get_display_clock_speed
;
12331 else /* 852, 830 */
12332 dev_priv
->display
.get_display_clock_speed
=
12333 i830_get_display_clock_speed
;
12335 if (HAS_PCH_SPLIT(dev
)) {
12336 if (IS_GEN5(dev
)) {
12337 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
12338 dev_priv
->display
.write_eld
= ironlake_write_eld
;
12339 } else if (IS_GEN6(dev
)) {
12340 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
12341 dev_priv
->display
.write_eld
= ironlake_write_eld
;
12342 dev_priv
->display
.modeset_global_resources
=
12343 snb_modeset_global_resources
;
12344 } else if (IS_IVYBRIDGE(dev
)) {
12345 /* FIXME: detect B0+ stepping and use auto training */
12346 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
12347 dev_priv
->display
.write_eld
= ironlake_write_eld
;
12348 dev_priv
->display
.modeset_global_resources
=
12349 ivb_modeset_global_resources
;
12350 } else if (IS_HASWELL(dev
) || IS_GEN8(dev
)) {
12351 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
12352 dev_priv
->display
.write_eld
= haswell_write_eld
;
12353 dev_priv
->display
.modeset_global_resources
=
12354 haswell_modeset_global_resources
;
12356 } else if (IS_G4X(dev
)) {
12357 dev_priv
->display
.write_eld
= g4x_write_eld
;
12358 } else if (IS_VALLEYVIEW(dev
)) {
12359 dev_priv
->display
.modeset_global_resources
=
12360 valleyview_modeset_global_resources
;
12361 dev_priv
->display
.write_eld
= ironlake_write_eld
;
12364 /* Default just returns -ENODEV to indicate unsupported */
12365 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
12367 switch (INTEL_INFO(dev
)->gen
) {
12369 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
12373 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
12378 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
12382 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
12385 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12386 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
12390 intel_panel_init_backlight_funcs(dev
);
12394 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12395 * resume, or other times. This quirk makes sure that's the case for
12396 * affected systems.
12398 static void quirk_pipea_force(struct drm_device
*dev
)
12400 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12402 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
12403 DRM_INFO("applying pipe a force quirk\n");
12407 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12409 static void quirk_ssc_force_disable(struct drm_device
*dev
)
12411 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12412 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
12413 DRM_INFO("applying lvds SSC disable quirk\n");
12417 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12420 static void quirk_invert_brightness(struct drm_device
*dev
)
12422 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12423 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
12424 DRM_INFO("applying inverted panel brightness quirk\n");
12427 /* Some VBT's incorrectly indicate no backlight is present */
12428 static void quirk_backlight_present(struct drm_device
*dev
)
12430 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12431 dev_priv
->quirks
|= QUIRK_BACKLIGHT_PRESENT
;
12432 DRM_INFO("applying backlight present quirk\n");
12435 struct intel_quirk
{
12437 int subsystem_vendor
;
12438 int subsystem_device
;
12439 void (*hook
)(struct drm_device
*dev
);
12442 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12443 struct intel_dmi_quirk
{
12444 void (*hook
)(struct drm_device
*dev
);
12445 const struct dmi_system_id (*dmi_id_list
)[];
12448 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
12450 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
12454 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
12456 .dmi_id_list
= &(const struct dmi_system_id
[]) {
12458 .callback
= intel_dmi_reverse_brightness
,
12459 .ident
= "NCR Corporation",
12460 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
12461 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
12464 { } /* terminating entry */
12466 .hook
= quirk_invert_brightness
,
12470 static struct intel_quirk intel_quirks
[] = {
12471 /* HP Mini needs pipe A force quirk (LP: #322104) */
12472 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force
},
12474 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12475 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
12477 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12478 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
12480 /* Lenovo U160 cannot use SSC on LVDS */
12481 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
12483 /* Sony Vaio Y cannot use SSC on LVDS */
12484 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
12486 /* Acer Aspire 5734Z must invert backlight brightness */
12487 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
12489 /* Acer/eMachines G725 */
12490 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness
},
12492 /* Acer/eMachines e725 */
12493 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness
},
12495 /* Acer/Packard Bell NCL20 */
12496 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness
},
12498 /* Acer Aspire 4736Z */
12499 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness
},
12501 /* Acer Aspire 5336 */
12502 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness
},
12504 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12505 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present
},
12507 /* Acer C720 Chromebook (Core i3 4005U) */
12508 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present
},
12510 /* Toshiba CB35 Chromebook (Celeron 2955U) */
12511 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present
},
12513 /* HP Chromebook 14 (Celeron 2955U) */
12514 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present
},
12517 static void intel_init_quirks(struct drm_device
*dev
)
12519 struct pci_dev
*d
= dev
->pdev
;
12522 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
12523 struct intel_quirk
*q
= &intel_quirks
[i
];
12525 if (d
->device
== q
->device
&&
12526 (d
->subsystem_vendor
== q
->subsystem_vendor
||
12527 q
->subsystem_vendor
== PCI_ANY_ID
) &&
12528 (d
->subsystem_device
== q
->subsystem_device
||
12529 q
->subsystem_device
== PCI_ANY_ID
))
12532 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
12533 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
12534 intel_dmi_quirks
[i
].hook(dev
);
12538 /* Disable the VGA plane that we never use */
12539 static void i915_disable_vga(struct drm_device
*dev
)
12541 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12543 u32 vga_reg
= i915_vgacntrl_reg(dev
);
12545 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12546 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
12547 outb(SR01
, VGA_SR_INDEX
);
12548 sr1
= inb(VGA_SR_DATA
);
12549 outb(sr1
| 1<<5, VGA_SR_DATA
);
12550 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
12553 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
12554 POSTING_READ(vga_reg
);
12557 void intel_modeset_init_hw(struct drm_device
*dev
)
12559 intel_prepare_ddi(dev
);
12561 if (IS_VALLEYVIEW(dev
))
12562 vlv_update_cdclk(dev
);
12564 intel_init_clock_gating(dev
);
12566 intel_reset_dpio(dev
);
12568 intel_enable_gt_powersave(dev
);
12571 void intel_modeset_suspend_hw(struct drm_device
*dev
)
12573 intel_suspend_hw(dev
);
12576 void intel_modeset_init(struct drm_device
*dev
)
12578 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12581 struct intel_crtc
*crtc
;
12583 drm_mode_config_init(dev
);
12585 dev
->mode_config
.min_width
= 0;
12586 dev
->mode_config
.min_height
= 0;
12588 dev
->mode_config
.preferred_depth
= 24;
12589 dev
->mode_config
.prefer_shadow
= 1;
12591 dev
->mode_config
.funcs
= &intel_mode_funcs
;
12593 intel_init_quirks(dev
);
12595 intel_init_pm(dev
);
12597 if (INTEL_INFO(dev
)->num_pipes
== 0)
12600 intel_init_display(dev
);
12602 if (IS_GEN2(dev
)) {
12603 dev
->mode_config
.max_width
= 2048;
12604 dev
->mode_config
.max_height
= 2048;
12605 } else if (IS_GEN3(dev
)) {
12606 dev
->mode_config
.max_width
= 4096;
12607 dev
->mode_config
.max_height
= 4096;
12609 dev
->mode_config
.max_width
= 8192;
12610 dev
->mode_config
.max_height
= 8192;
12613 if (IS_GEN2(dev
)) {
12614 dev
->mode_config
.cursor_width
= GEN2_CURSOR_WIDTH
;
12615 dev
->mode_config
.cursor_height
= GEN2_CURSOR_HEIGHT
;
12617 dev
->mode_config
.cursor_width
= MAX_CURSOR_WIDTH
;
12618 dev
->mode_config
.cursor_height
= MAX_CURSOR_HEIGHT
;
12621 dev
->mode_config
.fb_base
= dev_priv
->gtt
.mappable_base
;
12623 DRM_DEBUG_KMS("%d display pipe%s available.\n",
12624 INTEL_INFO(dev
)->num_pipes
,
12625 INTEL_INFO(dev
)->num_pipes
> 1 ? "s" : "");
12627 for_each_pipe(pipe
) {
12628 intel_crtc_init(dev
, pipe
);
12629 for_each_sprite(pipe
, sprite
) {
12630 ret
= intel_plane_init(dev
, pipe
, sprite
);
12632 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
12633 pipe_name(pipe
), sprite_name(pipe
, sprite
), ret
);
12637 intel_init_dpio(dev
);
12638 intel_reset_dpio(dev
);
12640 intel_shared_dpll_init(dev
);
12642 /* Just disable it once at startup */
12643 i915_disable_vga(dev
);
12644 intel_setup_outputs(dev
);
12646 /* Just in case the BIOS is doing something questionable. */
12647 intel_disable_fbc(dev
);
12649 drm_modeset_lock_all(dev
);
12650 intel_modeset_setup_hw_state(dev
, false);
12651 drm_modeset_unlock_all(dev
);
12653 for_each_intel_crtc(dev
, crtc
) {
12658 * Note that reserving the BIOS fb up front prevents us
12659 * from stuffing other stolen allocations like the ring
12660 * on top. This prevents some ugliness at boot time, and
12661 * can even allow for smooth boot transitions if the BIOS
12662 * fb is large enough for the active pipe configuration.
12664 if (dev_priv
->display
.get_plane_config
) {
12665 dev_priv
->display
.get_plane_config(crtc
,
12666 &crtc
->plane_config
);
12668 * If the fb is shared between multiple heads, we'll
12669 * just get the first one.
12671 intel_find_plane_obj(crtc
, &crtc
->plane_config
);
12676 static void intel_enable_pipe_a(struct drm_device
*dev
)
12678 struct intel_connector
*connector
;
12679 struct drm_connector
*crt
= NULL
;
12680 struct intel_load_detect_pipe load_detect_temp
;
12681 struct drm_modeset_acquire_ctx
*ctx
= dev
->mode_config
.acquire_ctx
;
12683 /* We can't just switch on the pipe A, we need to set things up with a
12684 * proper mode and output configuration. As a gross hack, enable pipe A
12685 * by enabling the load detect pipe once. */
12686 list_for_each_entry(connector
,
12687 &dev
->mode_config
.connector_list
,
12689 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
12690 crt
= &connector
->base
;
12698 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
, ctx
))
12699 intel_release_load_detect_pipe(crt
, &load_detect_temp
);
12703 intel_check_plane_mapping(struct intel_crtc
*crtc
)
12705 struct drm_device
*dev
= crtc
->base
.dev
;
12706 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12709 if (INTEL_INFO(dev
)->num_pipes
== 1)
12712 reg
= DSPCNTR(!crtc
->plane
);
12713 val
= I915_READ(reg
);
12715 if ((val
& DISPLAY_PLANE_ENABLE
) &&
12716 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
12722 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
12724 struct drm_device
*dev
= crtc
->base
.dev
;
12725 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12728 /* Clear any frame start delays used for debugging left by the BIOS */
12729 reg
= PIPECONF(crtc
->config
.cpu_transcoder
);
12730 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
12732 /* restore vblank interrupts to correct state */
12734 drm_vblank_on(dev
, crtc
->pipe
);
12736 drm_vblank_off(dev
, crtc
->pipe
);
12738 /* We need to sanitize the plane -> pipe mapping first because this will
12739 * disable the crtc (and hence change the state) if it is wrong. Note
12740 * that gen4+ has a fixed plane -> pipe mapping. */
12741 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
12742 struct intel_connector
*connector
;
12745 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
12746 crtc
->base
.base
.id
);
12748 /* Pipe has the wrong plane attached and the plane is active.
12749 * Temporarily change the plane mapping and disable everything
12751 plane
= crtc
->plane
;
12752 crtc
->plane
= !plane
;
12753 crtc
->primary_enabled
= true;
12754 dev_priv
->display
.crtc_disable(&crtc
->base
);
12755 crtc
->plane
= plane
;
12757 /* ... and break all links. */
12758 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
12760 if (connector
->encoder
->base
.crtc
!= &crtc
->base
)
12763 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
12764 connector
->base
.encoder
= NULL
;
12766 /* multiple connectors may have the same encoder:
12767 * handle them and break crtc link separately */
12768 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
12770 if (connector
->encoder
->base
.crtc
== &crtc
->base
) {
12771 connector
->encoder
->base
.crtc
= NULL
;
12772 connector
->encoder
->connectors_active
= false;
12775 WARN_ON(crtc
->active
);
12776 crtc
->base
.enabled
= false;
12779 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
12780 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
12781 /* BIOS forgot to enable pipe A, this mostly happens after
12782 * resume. Force-enable the pipe to fix this, the update_dpms
12783 * call below we restore the pipe to the right state, but leave
12784 * the required bits on. */
12785 intel_enable_pipe_a(dev
);
12788 /* Adjust the state of the output pipe according to whether we
12789 * have active connectors/encoders. */
12790 intel_crtc_update_dpms(&crtc
->base
);
12792 if (crtc
->active
!= crtc
->base
.enabled
) {
12793 struct intel_encoder
*encoder
;
12795 /* This can happen either due to bugs in the get_hw_state
12796 * functions or because the pipe is force-enabled due to the
12798 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
12799 crtc
->base
.base
.id
,
12800 crtc
->base
.enabled
? "enabled" : "disabled",
12801 crtc
->active
? "enabled" : "disabled");
12803 crtc
->base
.enabled
= crtc
->active
;
12805 /* Because we only establish the connector -> encoder ->
12806 * crtc links if something is active, this means the
12807 * crtc is now deactivated. Break the links. connector
12808 * -> encoder links are only establish when things are
12809 * actually up, hence no need to break them. */
12810 WARN_ON(crtc
->active
);
12812 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
12813 WARN_ON(encoder
->connectors_active
);
12814 encoder
->base
.crtc
= NULL
;
12818 if (crtc
->active
|| IS_VALLEYVIEW(dev
) || INTEL_INFO(dev
)->gen
< 5) {
12820 * We start out with underrun reporting disabled to avoid races.
12821 * For correct bookkeeping mark this on active crtcs.
12823 * Also on gmch platforms we dont have any hardware bits to
12824 * disable the underrun reporting. Which means we need to start
12825 * out with underrun reporting disabled also on inactive pipes,
12826 * since otherwise we'll complain about the garbage we read when
12827 * e.g. coming up after runtime pm.
12829 * No protection against concurrent access is required - at
12830 * worst a fifo underrun happens which also sets this to false.
12832 crtc
->cpu_fifo_underrun_disabled
= true;
12833 crtc
->pch_fifo_underrun_disabled
= true;
12835 update_scanline_offset(crtc
);
12839 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
12841 struct intel_connector
*connector
;
12842 struct drm_device
*dev
= encoder
->base
.dev
;
12844 /* We need to check both for a crtc link (meaning that the
12845 * encoder is active and trying to read from a pipe) and the
12846 * pipe itself being active. */
12847 bool has_active_crtc
= encoder
->base
.crtc
&&
12848 to_intel_crtc(encoder
->base
.crtc
)->active
;
12850 if (encoder
->connectors_active
&& !has_active_crtc
) {
12851 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
12852 encoder
->base
.base
.id
,
12853 encoder
->base
.name
);
12855 /* Connector is active, but has no active pipe. This is
12856 * fallout from our resume register restoring. Disable
12857 * the encoder manually again. */
12858 if (encoder
->base
.crtc
) {
12859 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
12860 encoder
->base
.base
.id
,
12861 encoder
->base
.name
);
12862 encoder
->disable(encoder
);
12863 if (encoder
->post_disable
)
12864 encoder
->post_disable(encoder
);
12866 encoder
->base
.crtc
= NULL
;
12867 encoder
->connectors_active
= false;
12869 /* Inconsistent output/port/pipe state happens presumably due to
12870 * a bug in one of the get_hw_state functions. Or someplace else
12871 * in our code, like the register restore mess on resume. Clamp
12872 * things to off as a safer default. */
12873 list_for_each_entry(connector
,
12874 &dev
->mode_config
.connector_list
,
12876 if (connector
->encoder
!= encoder
)
12878 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
12879 connector
->base
.encoder
= NULL
;
12882 /* Enabled encoders without active connectors will be fixed in
12883 * the crtc fixup. */
12886 void i915_redisable_vga_power_on(struct drm_device
*dev
)
12888 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12889 u32 vga_reg
= i915_vgacntrl_reg(dev
);
12891 if (!(I915_READ(vga_reg
) & VGA_DISP_DISABLE
)) {
12892 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
12893 i915_disable_vga(dev
);
12897 void i915_redisable_vga(struct drm_device
*dev
)
12899 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12901 /* This function can be called both from intel_modeset_setup_hw_state or
12902 * at a very early point in our resume sequence, where the power well
12903 * structures are not yet restored. Since this function is at a very
12904 * paranoid "someone might have enabled VGA while we were not looking"
12905 * level, just check if the power well is enabled instead of trying to
12906 * follow the "don't touch the power well if we don't need it" policy
12907 * the rest of the driver uses. */
12908 if (!intel_display_power_enabled(dev_priv
, POWER_DOMAIN_VGA
))
12911 i915_redisable_vga_power_on(dev
);
12914 static bool primary_get_hw_state(struct intel_crtc
*crtc
)
12916 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
12921 return I915_READ(DSPCNTR(crtc
->plane
)) & DISPLAY_PLANE_ENABLE
;
12924 static void intel_modeset_readout_hw_state(struct drm_device
*dev
)
12926 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12928 struct intel_crtc
*crtc
;
12929 struct intel_encoder
*encoder
;
12930 struct intel_connector
*connector
;
12933 for_each_intel_crtc(dev
, crtc
) {
12934 memset(&crtc
->config
, 0, sizeof(crtc
->config
));
12936 crtc
->config
.quirks
|= PIPE_CONFIG_QUIRK_INHERITED_MODE
;
12938 crtc
->active
= dev_priv
->display
.get_pipe_config(crtc
,
12941 crtc
->base
.enabled
= crtc
->active
;
12942 crtc
->primary_enabled
= primary_get_hw_state(crtc
);
12944 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
12945 crtc
->base
.base
.id
,
12946 crtc
->active
? "enabled" : "disabled");
12949 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
12950 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
12952 pll
->on
= pll
->get_hw_state(dev_priv
, pll
, &pll
->hw_state
);
12954 for_each_intel_crtc(dev
, crtc
) {
12955 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
12958 pll
->refcount
= pll
->active
;
12960 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
12961 pll
->name
, pll
->refcount
, pll
->on
);
12964 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
12967 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
12971 if (encoder
->get_hw_state(encoder
, &pipe
)) {
12972 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
12973 encoder
->base
.crtc
= &crtc
->base
;
12974 encoder
->get_config(encoder
, &crtc
->config
);
12976 encoder
->base
.crtc
= NULL
;
12979 encoder
->connectors_active
= false;
12980 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
12981 encoder
->base
.base
.id
,
12982 encoder
->base
.name
,
12983 encoder
->base
.crtc
? "enabled" : "disabled",
12987 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
12989 if (connector
->get_hw_state(connector
)) {
12990 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
12991 connector
->encoder
->connectors_active
= true;
12992 connector
->base
.encoder
= &connector
->encoder
->base
;
12994 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
12995 connector
->base
.encoder
= NULL
;
12997 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
12998 connector
->base
.base
.id
,
12999 connector
->base
.name
,
13000 connector
->base
.encoder
? "enabled" : "disabled");
13004 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13005 * and i915 state tracking structures. */
13006 void intel_modeset_setup_hw_state(struct drm_device
*dev
,
13007 bool force_restore
)
13009 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13011 struct intel_crtc
*crtc
;
13012 struct intel_encoder
*encoder
;
13015 intel_modeset_readout_hw_state(dev
);
13018 * Now that we have the config, copy it to each CRTC struct
13019 * Note that this could go away if we move to using crtc_config
13020 * checking everywhere.
13022 for_each_intel_crtc(dev
, crtc
) {
13023 if (crtc
->active
&& i915
.fastboot
) {
13024 intel_mode_from_pipe_config(&crtc
->base
.mode
, &crtc
->config
);
13025 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13026 crtc
->base
.base
.id
);
13027 drm_mode_debug_printmodeline(&crtc
->base
.mode
);
13031 /* HW state is read out, now we need to sanitize this mess. */
13032 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
13034 intel_sanitize_encoder(encoder
);
13037 for_each_pipe(pipe
) {
13038 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
13039 intel_sanitize_crtc(crtc
);
13040 intel_dump_pipe_config(crtc
, &crtc
->config
, "[setup_hw_state]");
13043 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
13044 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
13046 if (!pll
->on
|| pll
->active
)
13049 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll
->name
);
13051 pll
->disable(dev_priv
, pll
);
13055 if (HAS_PCH_SPLIT(dev
))
13056 ilk_wm_get_hw_state(dev
);
13058 if (force_restore
) {
13059 i915_redisable_vga(dev
);
13062 * We need to use raw interfaces for restoring state to avoid
13063 * checking (bogus) intermediate states.
13065 for_each_pipe(pipe
) {
13066 struct drm_crtc
*crtc
=
13067 dev_priv
->pipe_to_crtc_mapping
[pipe
];
13069 __intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
,
13070 crtc
->primary
->fb
);
13073 intel_modeset_update_staged_output_state(dev
);
13076 intel_modeset_check_state(dev
);
13079 void intel_modeset_gem_init(struct drm_device
*dev
)
13081 struct drm_crtc
*c
;
13082 struct drm_i915_gem_object
*obj
;
13084 mutex_lock(&dev
->struct_mutex
);
13085 intel_init_gt_powersave(dev
);
13086 mutex_unlock(&dev
->struct_mutex
);
13088 intel_modeset_init_hw(dev
);
13090 intel_setup_overlay(dev
);
13093 * Make sure any fbs we allocated at startup are properly
13094 * pinned & fenced. When we do the allocation it's too early
13097 mutex_lock(&dev
->struct_mutex
);
13098 for_each_crtc(dev
, c
) {
13099 obj
= intel_fb_obj(c
->primary
->fb
);
13103 if (intel_pin_and_fence_fb_obj(dev
, obj
, NULL
)) {
13104 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13105 to_intel_crtc(c
)->pipe
);
13106 drm_framebuffer_unreference(c
->primary
->fb
);
13107 c
->primary
->fb
= NULL
;
13110 mutex_unlock(&dev
->struct_mutex
);
13113 void intel_connector_unregister(struct intel_connector
*intel_connector
)
13115 struct drm_connector
*connector
= &intel_connector
->base
;
13117 intel_panel_destroy_backlight(connector
);
13118 drm_connector_unregister(connector
);
13121 void intel_modeset_cleanup(struct drm_device
*dev
)
13123 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13124 struct drm_connector
*connector
;
13127 * Interrupts and polling as the first thing to avoid creating havoc.
13128 * Too much stuff here (turning of rps, connectors, ...) would
13129 * experience fancy races otherwise.
13131 drm_irq_uninstall(dev
);
13132 intel_hpd_cancel_work(dev_priv
);
13133 dev_priv
->pm
._irqs_disabled
= true;
13136 * Due to the hpd irq storm handling the hotplug work can re-arm the
13137 * poll handlers. Hence disable polling after hpd handling is shut down.
13139 drm_kms_helper_poll_fini(dev
);
13141 mutex_lock(&dev
->struct_mutex
);
13143 intel_unregister_dsm_handler();
13145 intel_disable_fbc(dev
);
13147 intel_disable_gt_powersave(dev
);
13149 ironlake_teardown_rc6(dev
);
13151 mutex_unlock(&dev
->struct_mutex
);
13153 /* flush any delayed tasks or pending work */
13154 flush_scheduled_work();
13156 /* destroy the backlight and sysfs files before encoders/connectors */
13157 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
13158 struct intel_connector
*intel_connector
;
13160 intel_connector
= to_intel_connector(connector
);
13161 intel_connector
->unregister(intel_connector
);
13164 drm_mode_config_cleanup(dev
);
13166 intel_cleanup_overlay(dev
);
13168 mutex_lock(&dev
->struct_mutex
);
13169 intel_cleanup_gt_powersave(dev
);
13170 mutex_unlock(&dev
->struct_mutex
);
13174 * Return which encoder is currently attached for connector.
13176 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
13178 return &intel_attached_encoder(connector
)->base
;
13181 void intel_connector_attach_encoder(struct intel_connector
*connector
,
13182 struct intel_encoder
*encoder
)
13184 connector
->encoder
= encoder
;
13185 drm_mode_connector_attach_encoder(&connector
->base
,
13190 * set vga decode state - true == enable VGA decode
13192 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
13194 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13195 unsigned reg
= INTEL_INFO(dev
)->gen
>= 6 ? SNB_GMCH_CTRL
: INTEL_GMCH_CTRL
;
13198 if (pci_read_config_word(dev_priv
->bridge_dev
, reg
, &gmch_ctrl
)) {
13199 DRM_ERROR("failed to read control word\n");
13203 if (!!(gmch_ctrl
& INTEL_GMCH_VGA_DISABLE
) == !state
)
13207 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
13209 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
13211 if (pci_write_config_word(dev_priv
->bridge_dev
, reg
, gmch_ctrl
)) {
13212 DRM_ERROR("failed to write control word\n");
13219 struct intel_display_error_state
{
13221 u32 power_well_driver
;
13223 int num_transcoders
;
13225 struct intel_cursor_error_state
{
13230 } cursor
[I915_MAX_PIPES
];
13232 struct intel_pipe_error_state
{
13233 bool power_domain_on
;
13236 } pipe
[I915_MAX_PIPES
];
13238 struct intel_plane_error_state
{
13246 } plane
[I915_MAX_PIPES
];
13248 struct intel_transcoder_error_state
{
13249 bool power_domain_on
;
13250 enum transcoder cpu_transcoder
;
13263 struct intel_display_error_state
*
13264 intel_display_capture_error_state(struct drm_device
*dev
)
13266 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13267 struct intel_display_error_state
*error
;
13268 int transcoders
[] = {
13276 if (INTEL_INFO(dev
)->num_pipes
== 0)
13279 error
= kzalloc(sizeof(*error
), GFP_ATOMIC
);
13283 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
13284 error
->power_well_driver
= I915_READ(HSW_PWR_WELL_DRIVER
);
13287 error
->pipe
[i
].power_domain_on
=
13288 intel_display_power_enabled_unlocked(dev_priv
,
13289 POWER_DOMAIN_PIPE(i
));
13290 if (!error
->pipe
[i
].power_domain_on
)
13293 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
13294 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
13295 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
13297 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
13298 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
13299 if (INTEL_INFO(dev
)->gen
<= 3) {
13300 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
13301 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
13303 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
13304 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
13305 if (INTEL_INFO(dev
)->gen
>= 4) {
13306 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
13307 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
13310 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
13312 if (HAS_GMCH_DISPLAY(dev
))
13313 error
->pipe
[i
].stat
= I915_READ(PIPESTAT(i
));
13316 error
->num_transcoders
= INTEL_INFO(dev
)->num_pipes
;
13317 if (HAS_DDI(dev_priv
->dev
))
13318 error
->num_transcoders
++; /* Account for eDP. */
13320 for (i
= 0; i
< error
->num_transcoders
; i
++) {
13321 enum transcoder cpu_transcoder
= transcoders
[i
];
13323 error
->transcoder
[i
].power_domain_on
=
13324 intel_display_power_enabled_unlocked(dev_priv
,
13325 POWER_DOMAIN_TRANSCODER(cpu_transcoder
));
13326 if (!error
->transcoder
[i
].power_domain_on
)
13329 error
->transcoder
[i
].cpu_transcoder
= cpu_transcoder
;
13331 error
->transcoder
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
13332 error
->transcoder
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
13333 error
->transcoder
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
13334 error
->transcoder
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
13335 error
->transcoder
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
13336 error
->transcoder
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
13337 error
->transcoder
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
13343 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13346 intel_display_print_error_state(struct drm_i915_error_state_buf
*m
,
13347 struct drm_device
*dev
,
13348 struct intel_display_error_state
*error
)
13355 err_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev
)->num_pipes
);
13356 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
13357 err_printf(m
, "PWR_WELL_CTL2: %08x\n",
13358 error
->power_well_driver
);
13360 err_printf(m
, "Pipe [%d]:\n", i
);
13361 err_printf(m
, " Power: %s\n",
13362 error
->pipe
[i
].power_domain_on
? "on" : "off");
13363 err_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
13364 err_printf(m
, " STAT: %08x\n", error
->pipe
[i
].stat
);
13366 err_printf(m
, "Plane [%d]:\n", i
);
13367 err_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
13368 err_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
13369 if (INTEL_INFO(dev
)->gen
<= 3) {
13370 err_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
13371 err_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
13373 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
13374 err_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
13375 if (INTEL_INFO(dev
)->gen
>= 4) {
13376 err_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
13377 err_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
13380 err_printf(m
, "Cursor [%d]:\n", i
);
13381 err_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
13382 err_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
13383 err_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);
13386 for (i
= 0; i
< error
->num_transcoders
; i
++) {
13387 err_printf(m
, "CPU transcoder: %c\n",
13388 transcoder_name(error
->transcoder
[i
].cpu_transcoder
));
13389 err_printf(m
, " Power: %s\n",
13390 error
->transcoder
[i
].power_domain_on
? "on" : "off");
13391 err_printf(m
, " CONF: %08x\n", error
->transcoder
[i
].conf
);
13392 err_printf(m
, " HTOTAL: %08x\n", error
->transcoder
[i
].htotal
);
13393 err_printf(m
, " HBLANK: %08x\n", error
->transcoder
[i
].hblank
);
13394 err_printf(m
, " HSYNC: %08x\n", error
->transcoder
[i
].hsync
);
13395 err_printf(m
, " VTOTAL: %08x\n", error
->transcoder
[i
].vtotal
);
13396 err_printf(m
, " VBLANK: %08x\n", error
->transcoder
[i
].vblank
);
13397 err_printf(m
, " VSYNC: %08x\n", error
->transcoder
[i
].vsync
);