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drm/i915: Clean conflicting modesetting registers upon init
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/module.h>
28 #include <linux/input.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include <linux/vgaarb.h>
33 #include "drmP.h"
34 #include "intel_drv.h"
35 #include "i915_drm.h"
36 #include "i915_drv.h"
37 #include "i915_trace.h"
38 #include "drm_dp_helper.h"
39
40 #include "drm_crtc_helper.h"
41
42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
43
44 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
45 static void intel_update_watermarks(struct drm_device *dev);
46 static void intel_increase_pllclock(struct drm_crtc *crtc);
47 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
48
49 typedef struct {
50 /* given values */
51 int n;
52 int m1, m2;
53 int p1, p2;
54 /* derived values */
55 int dot;
56 int vco;
57 int m;
58 int p;
59 } intel_clock_t;
60
61 typedef struct {
62 int min, max;
63 } intel_range_t;
64
65 typedef struct {
66 int dot_limit;
67 int p2_slow, p2_fast;
68 } intel_p2_t;
69
70 #define INTEL_P2_NUM 2
71 typedef struct intel_limit intel_limit_t;
72 struct intel_limit {
73 intel_range_t dot, vco, n, m, m1, m2, p, p1;
74 intel_p2_t p2;
75 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
76 int, int, intel_clock_t *);
77 };
78
79 #define I8XX_DOT_MIN 25000
80 #define I8XX_DOT_MAX 350000
81 #define I8XX_VCO_MIN 930000
82 #define I8XX_VCO_MAX 1400000
83 #define I8XX_N_MIN 3
84 #define I8XX_N_MAX 16
85 #define I8XX_M_MIN 96
86 #define I8XX_M_MAX 140
87 #define I8XX_M1_MIN 18
88 #define I8XX_M1_MAX 26
89 #define I8XX_M2_MIN 6
90 #define I8XX_M2_MAX 16
91 #define I8XX_P_MIN 4
92 #define I8XX_P_MAX 128
93 #define I8XX_P1_MIN 2
94 #define I8XX_P1_MAX 33
95 #define I8XX_P1_LVDS_MIN 1
96 #define I8XX_P1_LVDS_MAX 6
97 #define I8XX_P2_SLOW 4
98 #define I8XX_P2_FAST 2
99 #define I8XX_P2_LVDS_SLOW 14
100 #define I8XX_P2_LVDS_FAST 7
101 #define I8XX_P2_SLOW_LIMIT 165000
102
103 #define I9XX_DOT_MIN 20000
104 #define I9XX_DOT_MAX 400000
105 #define I9XX_VCO_MIN 1400000
106 #define I9XX_VCO_MAX 2800000
107 #define PINEVIEW_VCO_MIN 1700000
108 #define PINEVIEW_VCO_MAX 3500000
109 #define I9XX_N_MIN 1
110 #define I9XX_N_MAX 6
111 /* Pineview's Ncounter is a ring counter */
112 #define PINEVIEW_N_MIN 3
113 #define PINEVIEW_N_MAX 6
114 #define I9XX_M_MIN 70
115 #define I9XX_M_MAX 120
116 #define PINEVIEW_M_MIN 2
117 #define PINEVIEW_M_MAX 256
118 #define I9XX_M1_MIN 10
119 #define I9XX_M1_MAX 22
120 #define I9XX_M2_MIN 5
121 #define I9XX_M2_MAX 9
122 /* Pineview M1 is reserved, and must be 0 */
123 #define PINEVIEW_M1_MIN 0
124 #define PINEVIEW_M1_MAX 0
125 #define PINEVIEW_M2_MIN 0
126 #define PINEVIEW_M2_MAX 254
127 #define I9XX_P_SDVO_DAC_MIN 5
128 #define I9XX_P_SDVO_DAC_MAX 80
129 #define I9XX_P_LVDS_MIN 7
130 #define I9XX_P_LVDS_MAX 98
131 #define PINEVIEW_P_LVDS_MIN 7
132 #define PINEVIEW_P_LVDS_MAX 112
133 #define I9XX_P1_MIN 1
134 #define I9XX_P1_MAX 8
135 #define I9XX_P2_SDVO_DAC_SLOW 10
136 #define I9XX_P2_SDVO_DAC_FAST 5
137 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
138 #define I9XX_P2_LVDS_SLOW 14
139 #define I9XX_P2_LVDS_FAST 7
140 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
141
142 /*The parameter is for SDVO on G4x platform*/
143 #define G4X_DOT_SDVO_MIN 25000
144 #define G4X_DOT_SDVO_MAX 270000
145 #define G4X_VCO_MIN 1750000
146 #define G4X_VCO_MAX 3500000
147 #define G4X_N_SDVO_MIN 1
148 #define G4X_N_SDVO_MAX 4
149 #define G4X_M_SDVO_MIN 104
150 #define G4X_M_SDVO_MAX 138
151 #define G4X_M1_SDVO_MIN 17
152 #define G4X_M1_SDVO_MAX 23
153 #define G4X_M2_SDVO_MIN 5
154 #define G4X_M2_SDVO_MAX 11
155 #define G4X_P_SDVO_MIN 10
156 #define G4X_P_SDVO_MAX 30
157 #define G4X_P1_SDVO_MIN 1
158 #define G4X_P1_SDVO_MAX 3
159 #define G4X_P2_SDVO_SLOW 10
160 #define G4X_P2_SDVO_FAST 10
161 #define G4X_P2_SDVO_LIMIT 270000
162
163 /*The parameter is for HDMI_DAC on G4x platform*/
164 #define G4X_DOT_HDMI_DAC_MIN 22000
165 #define G4X_DOT_HDMI_DAC_MAX 400000
166 #define G4X_N_HDMI_DAC_MIN 1
167 #define G4X_N_HDMI_DAC_MAX 4
168 #define G4X_M_HDMI_DAC_MIN 104
169 #define G4X_M_HDMI_DAC_MAX 138
170 #define G4X_M1_HDMI_DAC_MIN 16
171 #define G4X_M1_HDMI_DAC_MAX 23
172 #define G4X_M2_HDMI_DAC_MIN 5
173 #define G4X_M2_HDMI_DAC_MAX 11
174 #define G4X_P_HDMI_DAC_MIN 5
175 #define G4X_P_HDMI_DAC_MAX 80
176 #define G4X_P1_HDMI_DAC_MIN 1
177 #define G4X_P1_HDMI_DAC_MAX 8
178 #define G4X_P2_HDMI_DAC_SLOW 10
179 #define G4X_P2_HDMI_DAC_FAST 5
180 #define G4X_P2_HDMI_DAC_LIMIT 165000
181
182 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
184 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
185 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
186 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
187 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
188 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
190 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
192 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
193 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
194 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
196 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
197 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
198 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
199 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
200
201 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
203 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
204 #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
205 #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
206 #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
207 #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
208 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
209 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
210 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
211 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
212 #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
213 #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
214 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
215 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
216 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
217 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
218 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
219
220 /*The parameter is for DISPLAY PORT on G4x platform*/
221 #define G4X_DOT_DISPLAY_PORT_MIN 161670
222 #define G4X_DOT_DISPLAY_PORT_MAX 227000
223 #define G4X_N_DISPLAY_PORT_MIN 1
224 #define G4X_N_DISPLAY_PORT_MAX 2
225 #define G4X_M_DISPLAY_PORT_MIN 97
226 #define G4X_M_DISPLAY_PORT_MAX 108
227 #define G4X_M1_DISPLAY_PORT_MIN 0x10
228 #define G4X_M1_DISPLAY_PORT_MAX 0x12
229 #define G4X_M2_DISPLAY_PORT_MIN 0x05
230 #define G4X_M2_DISPLAY_PORT_MAX 0x06
231 #define G4X_P_DISPLAY_PORT_MIN 10
232 #define G4X_P_DISPLAY_PORT_MAX 20
233 #define G4X_P1_DISPLAY_PORT_MIN 1
234 #define G4X_P1_DISPLAY_PORT_MAX 2
235 #define G4X_P2_DISPLAY_PORT_SLOW 10
236 #define G4X_P2_DISPLAY_PORT_FAST 10
237 #define G4X_P2_DISPLAY_PORT_LIMIT 0
238
239 /* Ironlake / Sandybridge */
240 /* as we calculate clock using (register_value + 2) for
241 N/M1/M2, so here the range value for them is (actual_value-2).
242 */
243 #define IRONLAKE_DOT_MIN 25000
244 #define IRONLAKE_DOT_MAX 350000
245 #define IRONLAKE_VCO_MIN 1760000
246 #define IRONLAKE_VCO_MAX 3510000
247 #define IRONLAKE_M1_MIN 12
248 #define IRONLAKE_M1_MAX 22
249 #define IRONLAKE_M2_MIN 5
250 #define IRONLAKE_M2_MAX 9
251 #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
252
253 /* We have parameter ranges for different type of outputs. */
254
255 /* DAC & HDMI Refclk 120Mhz */
256 #define IRONLAKE_DAC_N_MIN 1
257 #define IRONLAKE_DAC_N_MAX 5
258 #define IRONLAKE_DAC_M_MIN 79
259 #define IRONLAKE_DAC_M_MAX 127
260 #define IRONLAKE_DAC_P_MIN 5
261 #define IRONLAKE_DAC_P_MAX 80
262 #define IRONLAKE_DAC_P1_MIN 1
263 #define IRONLAKE_DAC_P1_MAX 8
264 #define IRONLAKE_DAC_P2_SLOW 10
265 #define IRONLAKE_DAC_P2_FAST 5
266
267 /* LVDS single-channel 120Mhz refclk */
268 #define IRONLAKE_LVDS_S_N_MIN 1
269 #define IRONLAKE_LVDS_S_N_MAX 3
270 #define IRONLAKE_LVDS_S_M_MIN 79
271 #define IRONLAKE_LVDS_S_M_MAX 118
272 #define IRONLAKE_LVDS_S_P_MIN 28
273 #define IRONLAKE_LVDS_S_P_MAX 112
274 #define IRONLAKE_LVDS_S_P1_MIN 2
275 #define IRONLAKE_LVDS_S_P1_MAX 8
276 #define IRONLAKE_LVDS_S_P2_SLOW 14
277 #define IRONLAKE_LVDS_S_P2_FAST 14
278
279 /* LVDS dual-channel 120Mhz refclk */
280 #define IRONLAKE_LVDS_D_N_MIN 1
281 #define IRONLAKE_LVDS_D_N_MAX 3
282 #define IRONLAKE_LVDS_D_M_MIN 79
283 #define IRONLAKE_LVDS_D_M_MAX 127
284 #define IRONLAKE_LVDS_D_P_MIN 14
285 #define IRONLAKE_LVDS_D_P_MAX 56
286 #define IRONLAKE_LVDS_D_P1_MIN 2
287 #define IRONLAKE_LVDS_D_P1_MAX 8
288 #define IRONLAKE_LVDS_D_P2_SLOW 7
289 #define IRONLAKE_LVDS_D_P2_FAST 7
290
291 /* LVDS single-channel 100Mhz refclk */
292 #define IRONLAKE_LVDS_S_SSC_N_MIN 1
293 #define IRONLAKE_LVDS_S_SSC_N_MAX 2
294 #define IRONLAKE_LVDS_S_SSC_M_MIN 79
295 #define IRONLAKE_LVDS_S_SSC_M_MAX 126
296 #define IRONLAKE_LVDS_S_SSC_P_MIN 28
297 #define IRONLAKE_LVDS_S_SSC_P_MAX 112
298 #define IRONLAKE_LVDS_S_SSC_P1_MIN 2
299 #define IRONLAKE_LVDS_S_SSC_P1_MAX 8
300 #define IRONLAKE_LVDS_S_SSC_P2_SLOW 14
301 #define IRONLAKE_LVDS_S_SSC_P2_FAST 14
302
303 /* LVDS dual-channel 100Mhz refclk */
304 #define IRONLAKE_LVDS_D_SSC_N_MIN 1
305 #define IRONLAKE_LVDS_D_SSC_N_MAX 3
306 #define IRONLAKE_LVDS_D_SSC_M_MIN 79
307 #define IRONLAKE_LVDS_D_SSC_M_MAX 126
308 #define IRONLAKE_LVDS_D_SSC_P_MIN 14
309 #define IRONLAKE_LVDS_D_SSC_P_MAX 42
310 #define IRONLAKE_LVDS_D_SSC_P1_MIN 2
311 #define IRONLAKE_LVDS_D_SSC_P1_MAX 6
312 #define IRONLAKE_LVDS_D_SSC_P2_SLOW 7
313 #define IRONLAKE_LVDS_D_SSC_P2_FAST 7
314
315 /* DisplayPort */
316 #define IRONLAKE_DP_N_MIN 1
317 #define IRONLAKE_DP_N_MAX 2
318 #define IRONLAKE_DP_M_MIN 81
319 #define IRONLAKE_DP_M_MAX 90
320 #define IRONLAKE_DP_P_MIN 10
321 #define IRONLAKE_DP_P_MAX 20
322 #define IRONLAKE_DP_P2_FAST 10
323 #define IRONLAKE_DP_P2_SLOW 10
324 #define IRONLAKE_DP_P2_LIMIT 0
325 #define IRONLAKE_DP_P1_MIN 1
326 #define IRONLAKE_DP_P1_MAX 2
327
328 /* FDI */
329 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
330
331 static bool
332 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
333 int target, int refclk, intel_clock_t *best_clock);
334 static bool
335 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
336 int target, int refclk, intel_clock_t *best_clock);
337
338 static bool
339 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
340 int target, int refclk, intel_clock_t *best_clock);
341 static bool
342 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
343 int target, int refclk, intel_clock_t *best_clock);
344
345 static inline u32 /* units of 100MHz */
346 intel_fdi_link_freq(struct drm_device *dev)
347 {
348 if (IS_GEN5(dev)) {
349 struct drm_i915_private *dev_priv = dev->dev_private;
350 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
351 } else
352 return 27;
353 }
354
355 static const intel_limit_t intel_limits_i8xx_dvo = {
356 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
357 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
358 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
359 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
360 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
361 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
362 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
363 .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
364 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
365 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
366 .find_pll = intel_find_best_PLL,
367 };
368
369 static const intel_limit_t intel_limits_i8xx_lvds = {
370 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
371 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
372 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
373 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
374 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
375 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
376 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
377 .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
378 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
379 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
380 .find_pll = intel_find_best_PLL,
381 };
382
383 static const intel_limit_t intel_limits_i9xx_sdvo = {
384 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
385 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
386 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
387 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
388 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
389 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
390 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
391 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
392 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
393 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
394 .find_pll = intel_find_best_PLL,
395 };
396
397 static const intel_limit_t intel_limits_i9xx_lvds = {
398 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
399 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
400 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
401 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
402 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
403 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
404 .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
405 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
406 /* The single-channel range is 25-112Mhz, and dual-channel
407 * is 80-224Mhz. Prefer single channel as much as possible.
408 */
409 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
410 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
411 .find_pll = intel_find_best_PLL,
412 };
413
414 /* below parameter and function is for G4X Chipset Family*/
415 static const intel_limit_t intel_limits_g4x_sdvo = {
416 .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
417 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
418 .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },
419 .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },
420 .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },
421 .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },
422 .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },
423 .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
424 .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,
425 .p2_slow = G4X_P2_SDVO_SLOW,
426 .p2_fast = G4X_P2_SDVO_FAST
427 },
428 .find_pll = intel_g4x_find_best_PLL,
429 };
430
431 static const intel_limit_t intel_limits_g4x_hdmi = {
432 .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },
433 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
434 .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },
435 .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },
436 .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },
437 .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },
438 .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },
439 .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
440 .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
441 .p2_slow = G4X_P2_HDMI_DAC_SLOW,
442 .p2_fast = G4X_P2_HDMI_DAC_FAST
443 },
444 .find_pll = intel_g4x_find_best_PLL,
445 };
446
447 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
448 .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
449 .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
450 .vco = { .min = G4X_VCO_MIN,
451 .max = G4X_VCO_MAX },
452 .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
453 .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
454 .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
455 .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
456 .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
457 .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
458 .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
459 .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
460 .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
461 .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
462 .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
463 .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
464 .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
465 .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
466 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
467 },
468 .find_pll = intel_g4x_find_best_PLL,
469 };
470
471 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
472 .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
473 .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
474 .vco = { .min = G4X_VCO_MIN,
475 .max = G4X_VCO_MAX },
476 .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
477 .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
478 .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
479 .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
480 .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
481 .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
482 .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
483 .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
484 .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
485 .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
486 .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
487 .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
488 .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
489 .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
490 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
491 },
492 .find_pll = intel_g4x_find_best_PLL,
493 };
494
495 static const intel_limit_t intel_limits_g4x_display_port = {
496 .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
497 .max = G4X_DOT_DISPLAY_PORT_MAX },
498 .vco = { .min = G4X_VCO_MIN,
499 .max = G4X_VCO_MAX},
500 .n = { .min = G4X_N_DISPLAY_PORT_MIN,
501 .max = G4X_N_DISPLAY_PORT_MAX },
502 .m = { .min = G4X_M_DISPLAY_PORT_MIN,
503 .max = G4X_M_DISPLAY_PORT_MAX },
504 .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN,
505 .max = G4X_M1_DISPLAY_PORT_MAX },
506 .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,
507 .max = G4X_M2_DISPLAY_PORT_MAX },
508 .p = { .min = G4X_P_DISPLAY_PORT_MIN,
509 .max = G4X_P_DISPLAY_PORT_MAX },
510 .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
511 .max = G4X_P1_DISPLAY_PORT_MAX},
512 .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
513 .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
514 .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
515 .find_pll = intel_find_pll_g4x_dp,
516 };
517
518 static const intel_limit_t intel_limits_pineview_sdvo = {
519 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
520 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
521 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
522 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
523 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
524 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
525 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
526 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
527 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
528 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
529 .find_pll = intel_find_best_PLL,
530 };
531
532 static const intel_limit_t intel_limits_pineview_lvds = {
533 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
534 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
535 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
536 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
537 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
538 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
539 .p = { .min = PINEVIEW_P_LVDS_MIN, .max = PINEVIEW_P_LVDS_MAX },
540 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
541 /* Pineview only supports single-channel mode. */
542 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
543 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
544 .find_pll = intel_find_best_PLL,
545 };
546
547 static const intel_limit_t intel_limits_ironlake_dac = {
548 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
549 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
550 .n = { .min = IRONLAKE_DAC_N_MIN, .max = IRONLAKE_DAC_N_MAX },
551 .m = { .min = IRONLAKE_DAC_M_MIN, .max = IRONLAKE_DAC_M_MAX },
552 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
553 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
554 .p = { .min = IRONLAKE_DAC_P_MIN, .max = IRONLAKE_DAC_P_MAX },
555 .p1 = { .min = IRONLAKE_DAC_P1_MIN, .max = IRONLAKE_DAC_P1_MAX },
556 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
557 .p2_slow = IRONLAKE_DAC_P2_SLOW,
558 .p2_fast = IRONLAKE_DAC_P2_FAST },
559 .find_pll = intel_g4x_find_best_PLL,
560 };
561
562 static const intel_limit_t intel_limits_ironlake_single_lvds = {
563 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
564 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
565 .n = { .min = IRONLAKE_LVDS_S_N_MIN, .max = IRONLAKE_LVDS_S_N_MAX },
566 .m = { .min = IRONLAKE_LVDS_S_M_MIN, .max = IRONLAKE_LVDS_S_M_MAX },
567 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
568 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
569 .p = { .min = IRONLAKE_LVDS_S_P_MIN, .max = IRONLAKE_LVDS_S_P_MAX },
570 .p1 = { .min = IRONLAKE_LVDS_S_P1_MIN, .max = IRONLAKE_LVDS_S_P1_MAX },
571 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
572 .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
573 .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
574 .find_pll = intel_g4x_find_best_PLL,
575 };
576
577 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
578 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
579 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
580 .n = { .min = IRONLAKE_LVDS_D_N_MIN, .max = IRONLAKE_LVDS_D_N_MAX },
581 .m = { .min = IRONLAKE_LVDS_D_M_MIN, .max = IRONLAKE_LVDS_D_M_MAX },
582 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
583 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
584 .p = { .min = IRONLAKE_LVDS_D_P_MIN, .max = IRONLAKE_LVDS_D_P_MAX },
585 .p1 = { .min = IRONLAKE_LVDS_D_P1_MIN, .max = IRONLAKE_LVDS_D_P1_MAX },
586 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
587 .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
588 .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
589 .find_pll = intel_g4x_find_best_PLL,
590 };
591
592 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
593 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
594 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
595 .n = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
596 .m = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
597 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
598 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
599 .p = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
600 .p1 = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
601 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
602 .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
603 .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
604 .find_pll = intel_g4x_find_best_PLL,
605 };
606
607 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
608 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
609 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
610 .n = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
611 .m = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
612 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
613 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
614 .p = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
615 .p1 = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
616 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
617 .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
618 .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
619 .find_pll = intel_g4x_find_best_PLL,
620 };
621
622 static const intel_limit_t intel_limits_ironlake_display_port = {
623 .dot = { .min = IRONLAKE_DOT_MIN,
624 .max = IRONLAKE_DOT_MAX },
625 .vco = { .min = IRONLAKE_VCO_MIN,
626 .max = IRONLAKE_VCO_MAX},
627 .n = { .min = IRONLAKE_DP_N_MIN,
628 .max = IRONLAKE_DP_N_MAX },
629 .m = { .min = IRONLAKE_DP_M_MIN,
630 .max = IRONLAKE_DP_M_MAX },
631 .m1 = { .min = IRONLAKE_M1_MIN,
632 .max = IRONLAKE_M1_MAX },
633 .m2 = { .min = IRONLAKE_M2_MIN,
634 .max = IRONLAKE_M2_MAX },
635 .p = { .min = IRONLAKE_DP_P_MIN,
636 .max = IRONLAKE_DP_P_MAX },
637 .p1 = { .min = IRONLAKE_DP_P1_MIN,
638 .max = IRONLAKE_DP_P1_MAX},
639 .p2 = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
640 .p2_slow = IRONLAKE_DP_P2_SLOW,
641 .p2_fast = IRONLAKE_DP_P2_FAST },
642 .find_pll = intel_find_pll_ironlake_dp,
643 };
644
645 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
646 {
647 struct drm_device *dev = crtc->dev;
648 struct drm_i915_private *dev_priv = dev->dev_private;
649 const intel_limit_t *limit;
650 int refclk = 120;
651
652 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
653 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
654 refclk = 100;
655
656 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
657 LVDS_CLKB_POWER_UP) {
658 /* LVDS dual channel */
659 if (refclk == 100)
660 limit = &intel_limits_ironlake_dual_lvds_100m;
661 else
662 limit = &intel_limits_ironlake_dual_lvds;
663 } else {
664 if (refclk == 100)
665 limit = &intel_limits_ironlake_single_lvds_100m;
666 else
667 limit = &intel_limits_ironlake_single_lvds;
668 }
669 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
670 HAS_eDP)
671 limit = &intel_limits_ironlake_display_port;
672 else
673 limit = &intel_limits_ironlake_dac;
674
675 return limit;
676 }
677
678 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
679 {
680 struct drm_device *dev = crtc->dev;
681 struct drm_i915_private *dev_priv = dev->dev_private;
682 const intel_limit_t *limit;
683
684 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
685 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
686 LVDS_CLKB_POWER_UP)
687 /* LVDS with dual channel */
688 limit = &intel_limits_g4x_dual_channel_lvds;
689 else
690 /* LVDS with dual channel */
691 limit = &intel_limits_g4x_single_channel_lvds;
692 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
693 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
694 limit = &intel_limits_g4x_hdmi;
695 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
696 limit = &intel_limits_g4x_sdvo;
697 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
698 limit = &intel_limits_g4x_display_port;
699 } else /* The option is for other outputs */
700 limit = &intel_limits_i9xx_sdvo;
701
702 return limit;
703 }
704
705 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
706 {
707 struct drm_device *dev = crtc->dev;
708 const intel_limit_t *limit;
709
710 if (HAS_PCH_SPLIT(dev))
711 limit = intel_ironlake_limit(crtc);
712 else if (IS_G4X(dev)) {
713 limit = intel_g4x_limit(crtc);
714 } else if (IS_PINEVIEW(dev)) {
715 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
716 limit = &intel_limits_pineview_lvds;
717 else
718 limit = &intel_limits_pineview_sdvo;
719 } else if (!IS_GEN2(dev)) {
720 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
721 limit = &intel_limits_i9xx_lvds;
722 else
723 limit = &intel_limits_i9xx_sdvo;
724 } else {
725 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
726 limit = &intel_limits_i8xx_lvds;
727 else
728 limit = &intel_limits_i8xx_dvo;
729 }
730 return limit;
731 }
732
733 /* m1 is reserved as 0 in Pineview, n is a ring counter */
734 static void pineview_clock(int refclk, intel_clock_t *clock)
735 {
736 clock->m = clock->m2 + 2;
737 clock->p = clock->p1 * clock->p2;
738 clock->vco = refclk * clock->m / clock->n;
739 clock->dot = clock->vco / clock->p;
740 }
741
742 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
743 {
744 if (IS_PINEVIEW(dev)) {
745 pineview_clock(refclk, clock);
746 return;
747 }
748 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
749 clock->p = clock->p1 * clock->p2;
750 clock->vco = refclk * clock->m / (clock->n + 2);
751 clock->dot = clock->vco / clock->p;
752 }
753
754 /**
755 * Returns whether any output on the specified pipe is of the specified type
756 */
757 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
758 {
759 struct drm_device *dev = crtc->dev;
760 struct drm_mode_config *mode_config = &dev->mode_config;
761 struct intel_encoder *encoder;
762
763 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
764 if (encoder->base.crtc == crtc && encoder->type == type)
765 return true;
766
767 return false;
768 }
769
770 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
771 /**
772 * Returns whether the given set of divisors are valid for a given refclk with
773 * the given connectors.
774 */
775
776 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
777 {
778 const intel_limit_t *limit = intel_limit (crtc);
779 struct drm_device *dev = crtc->dev;
780
781 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
782 INTELPllInvalid ("p1 out of range\n");
783 if (clock->p < limit->p.min || limit->p.max < clock->p)
784 INTELPllInvalid ("p out of range\n");
785 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
786 INTELPllInvalid ("m2 out of range\n");
787 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
788 INTELPllInvalid ("m1 out of range\n");
789 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
790 INTELPllInvalid ("m1 <= m2\n");
791 if (clock->m < limit->m.min || limit->m.max < clock->m)
792 INTELPllInvalid ("m out of range\n");
793 if (clock->n < limit->n.min || limit->n.max < clock->n)
794 INTELPllInvalid ("n out of range\n");
795 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
796 INTELPllInvalid ("vco out of range\n");
797 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
798 * connector, etc., rather than just a single range.
799 */
800 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
801 INTELPllInvalid ("dot out of range\n");
802
803 return true;
804 }
805
806 static bool
807 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
808 int target, int refclk, intel_clock_t *best_clock)
809
810 {
811 struct drm_device *dev = crtc->dev;
812 struct drm_i915_private *dev_priv = dev->dev_private;
813 intel_clock_t clock;
814 int err = target;
815
816 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
817 (I915_READ(LVDS)) != 0) {
818 /*
819 * For LVDS, if the panel is on, just rely on its current
820 * settings for dual-channel. We haven't figured out how to
821 * reliably set up different single/dual channel state, if we
822 * even can.
823 */
824 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
825 LVDS_CLKB_POWER_UP)
826 clock.p2 = limit->p2.p2_fast;
827 else
828 clock.p2 = limit->p2.p2_slow;
829 } else {
830 if (target < limit->p2.dot_limit)
831 clock.p2 = limit->p2.p2_slow;
832 else
833 clock.p2 = limit->p2.p2_fast;
834 }
835
836 memset (best_clock, 0, sizeof (*best_clock));
837
838 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
839 clock.m1++) {
840 for (clock.m2 = limit->m2.min;
841 clock.m2 <= limit->m2.max; clock.m2++) {
842 /* m1 is always 0 in Pineview */
843 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
844 break;
845 for (clock.n = limit->n.min;
846 clock.n <= limit->n.max; clock.n++) {
847 for (clock.p1 = limit->p1.min;
848 clock.p1 <= limit->p1.max; clock.p1++) {
849 int this_err;
850
851 intel_clock(dev, refclk, &clock);
852
853 if (!intel_PLL_is_valid(crtc, &clock))
854 continue;
855
856 this_err = abs(clock.dot - target);
857 if (this_err < err) {
858 *best_clock = clock;
859 err = this_err;
860 }
861 }
862 }
863 }
864 }
865
866 return (err != target);
867 }
868
869 static bool
870 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
871 int target, int refclk, intel_clock_t *best_clock)
872 {
873 struct drm_device *dev = crtc->dev;
874 struct drm_i915_private *dev_priv = dev->dev_private;
875 intel_clock_t clock;
876 int max_n;
877 bool found;
878 /* approximately equals target * 0.00585 */
879 int err_most = (target >> 8) + (target >> 9);
880 found = false;
881
882 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
883 int lvds_reg;
884
885 if (HAS_PCH_SPLIT(dev))
886 lvds_reg = PCH_LVDS;
887 else
888 lvds_reg = LVDS;
889 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
890 LVDS_CLKB_POWER_UP)
891 clock.p2 = limit->p2.p2_fast;
892 else
893 clock.p2 = limit->p2.p2_slow;
894 } else {
895 if (target < limit->p2.dot_limit)
896 clock.p2 = limit->p2.p2_slow;
897 else
898 clock.p2 = limit->p2.p2_fast;
899 }
900
901 memset(best_clock, 0, sizeof(*best_clock));
902 max_n = limit->n.max;
903 /* based on hardware requirement, prefer smaller n to precision */
904 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
905 /* based on hardware requirement, prefere larger m1,m2 */
906 for (clock.m1 = limit->m1.max;
907 clock.m1 >= limit->m1.min; clock.m1--) {
908 for (clock.m2 = limit->m2.max;
909 clock.m2 >= limit->m2.min; clock.m2--) {
910 for (clock.p1 = limit->p1.max;
911 clock.p1 >= limit->p1.min; clock.p1--) {
912 int this_err;
913
914 intel_clock(dev, refclk, &clock);
915 if (!intel_PLL_is_valid(crtc, &clock))
916 continue;
917 this_err = abs(clock.dot - target) ;
918 if (this_err < err_most) {
919 *best_clock = clock;
920 err_most = this_err;
921 max_n = clock.n;
922 found = true;
923 }
924 }
925 }
926 }
927 }
928 return found;
929 }
930
931 static bool
932 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
933 int target, int refclk, intel_clock_t *best_clock)
934 {
935 struct drm_device *dev = crtc->dev;
936 intel_clock_t clock;
937
938 if (target < 200000) {
939 clock.n = 1;
940 clock.p1 = 2;
941 clock.p2 = 10;
942 clock.m1 = 12;
943 clock.m2 = 9;
944 } else {
945 clock.n = 2;
946 clock.p1 = 1;
947 clock.p2 = 10;
948 clock.m1 = 14;
949 clock.m2 = 8;
950 }
951 intel_clock(dev, refclk, &clock);
952 memcpy(best_clock, &clock, sizeof(intel_clock_t));
953 return true;
954 }
955
956 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
957 static bool
958 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
959 int target, int refclk, intel_clock_t *best_clock)
960 {
961 intel_clock_t clock;
962 if (target < 200000) {
963 clock.p1 = 2;
964 clock.p2 = 10;
965 clock.n = 2;
966 clock.m1 = 23;
967 clock.m2 = 8;
968 } else {
969 clock.p1 = 1;
970 clock.p2 = 10;
971 clock.n = 1;
972 clock.m1 = 14;
973 clock.m2 = 2;
974 }
975 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
976 clock.p = (clock.p1 * clock.p2);
977 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
978 clock.vco = 0;
979 memcpy(best_clock, &clock, sizeof(intel_clock_t));
980 return true;
981 }
982
983 /**
984 * intel_wait_for_vblank - wait for vblank on a given pipe
985 * @dev: drm device
986 * @pipe: pipe to wait for
987 *
988 * Wait for vblank to occur on a given pipe. Needed for various bits of
989 * mode setting code.
990 */
991 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
992 {
993 struct drm_i915_private *dev_priv = dev->dev_private;
994 int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT);
995
996 /* Clear existing vblank status. Note this will clear any other
997 * sticky status fields as well.
998 *
999 * This races with i915_driver_irq_handler() with the result
1000 * that either function could miss a vblank event. Here it is not
1001 * fatal, as we will either wait upon the next vblank interrupt or
1002 * timeout. Generally speaking intel_wait_for_vblank() is only
1003 * called during modeset at which time the GPU should be idle and
1004 * should *not* be performing page flips and thus not waiting on
1005 * vblanks...
1006 * Currently, the result of us stealing a vblank from the irq
1007 * handler is that a single frame will be skipped during swapbuffers.
1008 */
1009 I915_WRITE(pipestat_reg,
1010 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
1011
1012 /* Wait for vblank interrupt bit to set */
1013 if (wait_for(I915_READ(pipestat_reg) &
1014 PIPE_VBLANK_INTERRUPT_STATUS,
1015 50))
1016 DRM_DEBUG_KMS("vblank wait timed out\n");
1017 }
1018
1019 /*
1020 * intel_wait_for_pipe_off - wait for pipe to turn off
1021 * @dev: drm device
1022 * @pipe: pipe to wait for
1023 *
1024 * After disabling a pipe, we can't wait for vblank in the usual way,
1025 * spinning on the vblank interrupt status bit, since we won't actually
1026 * see an interrupt when the pipe is disabled.
1027 *
1028 * On Gen4 and above:
1029 * wait for the pipe register state bit to turn off
1030 *
1031 * Otherwise:
1032 * wait for the display line value to settle (it usually
1033 * ends up stopping at the start of the next frame).
1034 *
1035 */
1036 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1037 {
1038 struct drm_i915_private *dev_priv = dev->dev_private;
1039
1040 if (INTEL_INFO(dev)->gen >= 4) {
1041 int reg = PIPECONF(pipe);
1042
1043 /* Wait for the Pipe State to go off */
1044 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1045 100))
1046 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1047 } else {
1048 u32 last_line;
1049 int reg = PIPEDSL(pipe);
1050 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1051
1052 /* Wait for the display line to settle */
1053 do {
1054 last_line = I915_READ(reg) & DSL_LINEMASK;
1055 mdelay(5);
1056 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
1057 time_after(timeout, jiffies));
1058 if (time_after(jiffies, timeout))
1059 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1060 }
1061 }
1062
1063 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1064 {
1065 struct drm_device *dev = crtc->dev;
1066 struct drm_i915_private *dev_priv = dev->dev_private;
1067 struct drm_framebuffer *fb = crtc->fb;
1068 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1069 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1070 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1071 int plane, i;
1072 u32 fbc_ctl, fbc_ctl2;
1073
1074 if (fb->pitch == dev_priv->cfb_pitch &&
1075 obj_priv->fence_reg == dev_priv->cfb_fence &&
1076 intel_crtc->plane == dev_priv->cfb_plane &&
1077 I915_READ(FBC_CONTROL) & FBC_CTL_EN)
1078 return;
1079
1080 i8xx_disable_fbc(dev);
1081
1082 dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1083
1084 if (fb->pitch < dev_priv->cfb_pitch)
1085 dev_priv->cfb_pitch = fb->pitch;
1086
1087 /* FBC_CTL wants 64B units */
1088 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1089 dev_priv->cfb_fence = obj_priv->fence_reg;
1090 dev_priv->cfb_plane = intel_crtc->plane;
1091 plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1092
1093 /* Clear old tags */
1094 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1095 I915_WRITE(FBC_TAG + (i * 4), 0);
1096
1097 /* Set it up... */
1098 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1099 if (obj_priv->tiling_mode != I915_TILING_NONE)
1100 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1101 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1102 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1103
1104 /* enable it... */
1105 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1106 if (IS_I945GM(dev))
1107 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1108 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1109 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1110 if (obj_priv->tiling_mode != I915_TILING_NONE)
1111 fbc_ctl |= dev_priv->cfb_fence;
1112 I915_WRITE(FBC_CONTROL, fbc_ctl);
1113
1114 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1115 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1116 }
1117
1118 void i8xx_disable_fbc(struct drm_device *dev)
1119 {
1120 struct drm_i915_private *dev_priv = dev->dev_private;
1121 u32 fbc_ctl;
1122
1123 /* Disable compression */
1124 fbc_ctl = I915_READ(FBC_CONTROL);
1125 if ((fbc_ctl & FBC_CTL_EN) == 0)
1126 return;
1127
1128 fbc_ctl &= ~FBC_CTL_EN;
1129 I915_WRITE(FBC_CONTROL, fbc_ctl);
1130
1131 /* Wait for compressing bit to clear */
1132 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1133 DRM_DEBUG_KMS("FBC idle timed out\n");
1134 return;
1135 }
1136
1137 DRM_DEBUG_KMS("disabled FBC\n");
1138 }
1139
1140 static bool i8xx_fbc_enabled(struct drm_device *dev)
1141 {
1142 struct drm_i915_private *dev_priv = dev->dev_private;
1143
1144 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1145 }
1146
1147 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1148 {
1149 struct drm_device *dev = crtc->dev;
1150 struct drm_i915_private *dev_priv = dev->dev_private;
1151 struct drm_framebuffer *fb = crtc->fb;
1152 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1153 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1154 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1155 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1156 unsigned long stall_watermark = 200;
1157 u32 dpfc_ctl;
1158
1159 dpfc_ctl = I915_READ(DPFC_CONTROL);
1160 if (dpfc_ctl & DPFC_CTL_EN) {
1161 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1162 dev_priv->cfb_fence == obj_priv->fence_reg &&
1163 dev_priv->cfb_plane == intel_crtc->plane &&
1164 dev_priv->cfb_y == crtc->y)
1165 return;
1166
1167 I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1168 POSTING_READ(DPFC_CONTROL);
1169 intel_wait_for_vblank(dev, intel_crtc->pipe);
1170 }
1171
1172 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1173 dev_priv->cfb_fence = obj_priv->fence_reg;
1174 dev_priv->cfb_plane = intel_crtc->plane;
1175 dev_priv->cfb_y = crtc->y;
1176
1177 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1178 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1179 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1180 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1181 } else {
1182 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1183 }
1184
1185 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1186 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1187 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1188 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1189
1190 /* enable it... */
1191 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1192
1193 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1194 }
1195
1196 void g4x_disable_fbc(struct drm_device *dev)
1197 {
1198 struct drm_i915_private *dev_priv = dev->dev_private;
1199 u32 dpfc_ctl;
1200
1201 /* Disable compression */
1202 dpfc_ctl = I915_READ(DPFC_CONTROL);
1203 if (dpfc_ctl & DPFC_CTL_EN) {
1204 dpfc_ctl &= ~DPFC_CTL_EN;
1205 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1206
1207 DRM_DEBUG_KMS("disabled FBC\n");
1208 }
1209 }
1210
1211 static bool g4x_fbc_enabled(struct drm_device *dev)
1212 {
1213 struct drm_i915_private *dev_priv = dev->dev_private;
1214
1215 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1216 }
1217
1218 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1219 {
1220 struct drm_device *dev = crtc->dev;
1221 struct drm_i915_private *dev_priv = dev->dev_private;
1222 struct drm_framebuffer *fb = crtc->fb;
1223 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1224 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1225 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1226 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1227 unsigned long stall_watermark = 200;
1228 u32 dpfc_ctl;
1229
1230 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1231 if (dpfc_ctl & DPFC_CTL_EN) {
1232 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1233 dev_priv->cfb_fence == obj_priv->fence_reg &&
1234 dev_priv->cfb_plane == intel_crtc->plane &&
1235 dev_priv->cfb_offset == obj_priv->gtt_offset &&
1236 dev_priv->cfb_y == crtc->y)
1237 return;
1238
1239 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1240 POSTING_READ(ILK_DPFC_CONTROL);
1241 intel_wait_for_vblank(dev, intel_crtc->pipe);
1242 }
1243
1244 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1245 dev_priv->cfb_fence = obj_priv->fence_reg;
1246 dev_priv->cfb_plane = intel_crtc->plane;
1247 dev_priv->cfb_offset = obj_priv->gtt_offset;
1248 dev_priv->cfb_y = crtc->y;
1249
1250 dpfc_ctl &= DPFC_RESERVED;
1251 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1252 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1253 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1254 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1255 } else {
1256 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1257 }
1258
1259 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1260 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1261 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1262 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1263 I915_WRITE(ILK_FBC_RT_BASE, obj_priv->gtt_offset | ILK_FBC_RT_VALID);
1264 /* enable it... */
1265 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1266
1267 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1268 }
1269
1270 void ironlake_disable_fbc(struct drm_device *dev)
1271 {
1272 struct drm_i915_private *dev_priv = dev->dev_private;
1273 u32 dpfc_ctl;
1274
1275 /* Disable compression */
1276 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1277 if (dpfc_ctl & DPFC_CTL_EN) {
1278 dpfc_ctl &= ~DPFC_CTL_EN;
1279 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1280
1281 DRM_DEBUG_KMS("disabled FBC\n");
1282 }
1283 }
1284
1285 static bool ironlake_fbc_enabled(struct drm_device *dev)
1286 {
1287 struct drm_i915_private *dev_priv = dev->dev_private;
1288
1289 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1290 }
1291
1292 bool intel_fbc_enabled(struct drm_device *dev)
1293 {
1294 struct drm_i915_private *dev_priv = dev->dev_private;
1295
1296 if (!dev_priv->display.fbc_enabled)
1297 return false;
1298
1299 return dev_priv->display.fbc_enabled(dev);
1300 }
1301
1302 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1303 {
1304 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1305
1306 if (!dev_priv->display.enable_fbc)
1307 return;
1308
1309 dev_priv->display.enable_fbc(crtc, interval);
1310 }
1311
1312 void intel_disable_fbc(struct drm_device *dev)
1313 {
1314 struct drm_i915_private *dev_priv = dev->dev_private;
1315
1316 if (!dev_priv->display.disable_fbc)
1317 return;
1318
1319 dev_priv->display.disable_fbc(dev);
1320 }
1321
1322 /**
1323 * intel_update_fbc - enable/disable FBC as needed
1324 * @dev: the drm_device
1325 *
1326 * Set up the framebuffer compression hardware at mode set time. We
1327 * enable it if possible:
1328 * - plane A only (on pre-965)
1329 * - no pixel mulitply/line duplication
1330 * - no alpha buffer discard
1331 * - no dual wide
1332 * - framebuffer <= 2048 in width, 1536 in height
1333 *
1334 * We can't assume that any compression will take place (worst case),
1335 * so the compressed buffer has to be the same size as the uncompressed
1336 * one. It also must reside (along with the line length buffer) in
1337 * stolen memory.
1338 *
1339 * We need to enable/disable FBC on a global basis.
1340 */
1341 static void intel_update_fbc(struct drm_device *dev)
1342 {
1343 struct drm_i915_private *dev_priv = dev->dev_private;
1344 struct drm_crtc *crtc = NULL, *tmp_crtc;
1345 struct intel_crtc *intel_crtc;
1346 struct drm_framebuffer *fb;
1347 struct intel_framebuffer *intel_fb;
1348 struct drm_i915_gem_object *obj_priv;
1349
1350 DRM_DEBUG_KMS("\n");
1351
1352 if (!i915_powersave)
1353 return;
1354
1355 if (!I915_HAS_FBC(dev))
1356 return;
1357
1358 /*
1359 * If FBC is already on, we just have to verify that we can
1360 * keep it that way...
1361 * Need to disable if:
1362 * - more than one pipe is active
1363 * - changing FBC params (stride, fence, mode)
1364 * - new fb is too large to fit in compressed buffer
1365 * - going to an unsupported config (interlace, pixel multiply, etc.)
1366 */
1367 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1368 if (tmp_crtc->enabled) {
1369 if (crtc) {
1370 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1371 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1372 goto out_disable;
1373 }
1374 crtc = tmp_crtc;
1375 }
1376 }
1377
1378 if (!crtc || crtc->fb == NULL) {
1379 DRM_DEBUG_KMS("no output, disabling\n");
1380 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1381 goto out_disable;
1382 }
1383
1384 intel_crtc = to_intel_crtc(crtc);
1385 fb = crtc->fb;
1386 intel_fb = to_intel_framebuffer(fb);
1387 obj_priv = to_intel_bo(intel_fb->obj);
1388
1389 if (intel_fb->obj->size > dev_priv->cfb_size) {
1390 DRM_DEBUG_KMS("framebuffer too large, disabling "
1391 "compression\n");
1392 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1393 goto out_disable;
1394 }
1395 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1396 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1397 DRM_DEBUG_KMS("mode incompatible with compression, "
1398 "disabling\n");
1399 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1400 goto out_disable;
1401 }
1402 if ((crtc->mode.hdisplay > 2048) ||
1403 (crtc->mode.vdisplay > 1536)) {
1404 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1405 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1406 goto out_disable;
1407 }
1408 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1409 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1410 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1411 goto out_disable;
1412 }
1413 if (obj_priv->tiling_mode != I915_TILING_X) {
1414 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1415 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1416 goto out_disable;
1417 }
1418
1419 /* If the kernel debugger is active, always disable compression */
1420 if (in_dbg_master())
1421 goto out_disable;
1422
1423 intel_enable_fbc(crtc, 500);
1424 return;
1425
1426 out_disable:
1427 /* Multiple disables should be harmless */
1428 if (intel_fbc_enabled(dev)) {
1429 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1430 intel_disable_fbc(dev);
1431 }
1432 }
1433
1434 int
1435 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1436 struct drm_gem_object *obj,
1437 bool pipelined)
1438 {
1439 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1440 u32 alignment;
1441 int ret;
1442
1443 switch (obj_priv->tiling_mode) {
1444 case I915_TILING_NONE:
1445 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1446 alignment = 128 * 1024;
1447 else if (INTEL_INFO(dev)->gen >= 4)
1448 alignment = 4 * 1024;
1449 else
1450 alignment = 64 * 1024;
1451 break;
1452 case I915_TILING_X:
1453 /* pin() will align the object as required by fence */
1454 alignment = 0;
1455 break;
1456 case I915_TILING_Y:
1457 /* FIXME: Is this true? */
1458 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1459 return -EINVAL;
1460 default:
1461 BUG();
1462 }
1463
1464 ret = i915_gem_object_pin(obj, alignment);
1465 if (ret)
1466 return ret;
1467
1468 ret = i915_gem_object_set_to_display_plane(obj, pipelined);
1469 if (ret)
1470 goto err_unpin;
1471
1472 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1473 * fence, whereas 965+ only requires a fence if using
1474 * framebuffer compression. For simplicity, we always install
1475 * a fence as the cost is not that onerous.
1476 */
1477 if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1478 obj_priv->tiling_mode != I915_TILING_NONE) {
1479 ret = i915_gem_object_get_fence_reg(obj, false);
1480 if (ret)
1481 goto err_unpin;
1482 }
1483
1484 return 0;
1485
1486 err_unpin:
1487 i915_gem_object_unpin(obj);
1488 return ret;
1489 }
1490
1491 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1492 static int
1493 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1494 int x, int y, enum mode_set_atomic state)
1495 {
1496 struct drm_device *dev = crtc->dev;
1497 struct drm_i915_private *dev_priv = dev->dev_private;
1498 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1499 struct intel_framebuffer *intel_fb;
1500 struct drm_i915_gem_object *obj_priv;
1501 struct drm_gem_object *obj;
1502 int plane = intel_crtc->plane;
1503 unsigned long Start, Offset;
1504 u32 dspcntr;
1505 u32 reg;
1506
1507 switch (plane) {
1508 case 0:
1509 case 1:
1510 break;
1511 default:
1512 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1513 return -EINVAL;
1514 }
1515
1516 intel_fb = to_intel_framebuffer(fb);
1517 obj = intel_fb->obj;
1518 obj_priv = to_intel_bo(obj);
1519
1520 reg = DSPCNTR(plane);
1521 dspcntr = I915_READ(reg);
1522 /* Mask out pixel format bits in case we change it */
1523 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1524 switch (fb->bits_per_pixel) {
1525 case 8:
1526 dspcntr |= DISPPLANE_8BPP;
1527 break;
1528 case 16:
1529 if (fb->depth == 15)
1530 dspcntr |= DISPPLANE_15_16BPP;
1531 else
1532 dspcntr |= DISPPLANE_16BPP;
1533 break;
1534 case 24:
1535 case 32:
1536 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1537 break;
1538 default:
1539 DRM_ERROR("Unknown color depth\n");
1540 return -EINVAL;
1541 }
1542 if (INTEL_INFO(dev)->gen >= 4) {
1543 if (obj_priv->tiling_mode != I915_TILING_NONE)
1544 dspcntr |= DISPPLANE_TILED;
1545 else
1546 dspcntr &= ~DISPPLANE_TILED;
1547 }
1548
1549 if (HAS_PCH_SPLIT(dev))
1550 /* must disable */
1551 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1552
1553 I915_WRITE(reg, dspcntr);
1554
1555 Start = obj_priv->gtt_offset;
1556 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1557
1558 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1559 Start, Offset, x, y, fb->pitch);
1560 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
1561 if (INTEL_INFO(dev)->gen >= 4) {
1562 I915_WRITE(DSPSURF(plane), Start);
1563 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1564 I915_WRITE(DSPADDR(plane), Offset);
1565 } else
1566 I915_WRITE(DSPADDR(plane), Start + Offset);
1567 POSTING_READ(reg);
1568
1569 intel_update_fbc(dev);
1570 intel_increase_pllclock(crtc);
1571
1572 return 0;
1573 }
1574
1575 static int
1576 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1577 struct drm_framebuffer *old_fb)
1578 {
1579 struct drm_device *dev = crtc->dev;
1580 struct drm_i915_master_private *master_priv;
1581 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1582 int ret;
1583
1584 /* no fb bound */
1585 if (!crtc->fb) {
1586 DRM_DEBUG_KMS("No FB bound\n");
1587 return 0;
1588 }
1589
1590 switch (intel_crtc->plane) {
1591 case 0:
1592 case 1:
1593 break;
1594 default:
1595 return -EINVAL;
1596 }
1597
1598 mutex_lock(&dev->struct_mutex);
1599 ret = intel_pin_and_fence_fb_obj(dev,
1600 to_intel_framebuffer(crtc->fb)->obj,
1601 false);
1602 if (ret != 0) {
1603 mutex_unlock(&dev->struct_mutex);
1604 return ret;
1605 }
1606
1607 if (old_fb) {
1608 struct drm_i915_private *dev_priv = dev->dev_private;
1609 struct drm_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
1610 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1611
1612 wait_event(dev_priv->pending_flip_queue,
1613 atomic_read(&obj_priv->pending_flip) == 0);
1614
1615 /* Big Hammer, we also need to ensure that any pending
1616 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1617 * current scanout is retired before unpinning the old
1618 * framebuffer.
1619 */
1620 ret = i915_gem_object_flush_gpu(obj_priv, false);
1621 if (ret) {
1622 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
1623 mutex_unlock(&dev->struct_mutex);
1624 return ret;
1625 }
1626 }
1627
1628 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
1629 LEAVE_ATOMIC_MODE_SET);
1630 if (ret) {
1631 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
1632 mutex_unlock(&dev->struct_mutex);
1633 return ret;
1634 }
1635
1636 if (old_fb)
1637 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
1638
1639 mutex_unlock(&dev->struct_mutex);
1640
1641 if (!dev->primary->master)
1642 return 0;
1643
1644 master_priv = dev->primary->master->driver_priv;
1645 if (!master_priv->sarea_priv)
1646 return 0;
1647
1648 if (intel_crtc->pipe) {
1649 master_priv->sarea_priv->pipeB_x = x;
1650 master_priv->sarea_priv->pipeB_y = y;
1651 } else {
1652 master_priv->sarea_priv->pipeA_x = x;
1653 master_priv->sarea_priv->pipeA_y = y;
1654 }
1655
1656 return 0;
1657 }
1658
1659 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
1660 {
1661 struct drm_device *dev = crtc->dev;
1662 struct drm_i915_private *dev_priv = dev->dev_private;
1663 u32 dpa_ctl;
1664
1665 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1666 dpa_ctl = I915_READ(DP_A);
1667 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1668
1669 if (clock < 200000) {
1670 u32 temp;
1671 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1672 /* workaround for 160Mhz:
1673 1) program 0x4600c bits 15:0 = 0x8124
1674 2) program 0x46010 bit 0 = 1
1675 3) program 0x46034 bit 24 = 1
1676 4) program 0x64000 bit 14 = 1
1677 */
1678 temp = I915_READ(0x4600c);
1679 temp &= 0xffff0000;
1680 I915_WRITE(0x4600c, temp | 0x8124);
1681
1682 temp = I915_READ(0x46010);
1683 I915_WRITE(0x46010, temp | 1);
1684
1685 temp = I915_READ(0x46034);
1686 I915_WRITE(0x46034, temp | (1 << 24));
1687 } else {
1688 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1689 }
1690 I915_WRITE(DP_A, dpa_ctl);
1691
1692 POSTING_READ(DP_A);
1693 udelay(500);
1694 }
1695
1696 static void intel_fdi_normal_train(struct drm_crtc *crtc)
1697 {
1698 struct drm_device *dev = crtc->dev;
1699 struct drm_i915_private *dev_priv = dev->dev_private;
1700 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1701 int pipe = intel_crtc->pipe;
1702 u32 reg, temp;
1703
1704 /* enable normal train */
1705 reg = FDI_TX_CTL(pipe);
1706 temp = I915_READ(reg);
1707 temp &= ~FDI_LINK_TRAIN_NONE;
1708 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
1709 I915_WRITE(reg, temp);
1710
1711 reg = FDI_RX_CTL(pipe);
1712 temp = I915_READ(reg);
1713 if (HAS_PCH_CPT(dev)) {
1714 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1715 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
1716 } else {
1717 temp &= ~FDI_LINK_TRAIN_NONE;
1718 temp |= FDI_LINK_TRAIN_NONE;
1719 }
1720 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
1721
1722 /* wait one idle pattern time */
1723 POSTING_READ(reg);
1724 udelay(1000);
1725 }
1726
1727 /* The FDI link training functions for ILK/Ibexpeak. */
1728 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1729 {
1730 struct drm_device *dev = crtc->dev;
1731 struct drm_i915_private *dev_priv = dev->dev_private;
1732 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1733 int pipe = intel_crtc->pipe;
1734 u32 reg, temp, tries;
1735
1736 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1737 for train result */
1738 reg = FDI_RX_IMR(pipe);
1739 temp = I915_READ(reg);
1740 temp &= ~FDI_RX_SYMBOL_LOCK;
1741 temp &= ~FDI_RX_BIT_LOCK;
1742 I915_WRITE(reg, temp);
1743 I915_READ(reg);
1744 udelay(150);
1745
1746 /* enable CPU FDI TX and PCH FDI RX */
1747 reg = FDI_TX_CTL(pipe);
1748 temp = I915_READ(reg);
1749 temp &= ~(7 << 19);
1750 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1751 temp &= ~FDI_LINK_TRAIN_NONE;
1752 temp |= FDI_LINK_TRAIN_PATTERN_1;
1753 I915_WRITE(reg, temp | FDI_TX_ENABLE);
1754
1755 reg = FDI_RX_CTL(pipe);
1756 temp = I915_READ(reg);
1757 temp &= ~FDI_LINK_TRAIN_NONE;
1758 temp |= FDI_LINK_TRAIN_PATTERN_1;
1759 I915_WRITE(reg, temp | FDI_RX_ENABLE);
1760
1761 POSTING_READ(reg);
1762 udelay(150);
1763
1764 /* Ironlake workaround, enable clock pointer after FDI enable*/
1765 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_ENABLE);
1766
1767 reg = FDI_RX_IIR(pipe);
1768 for (tries = 0; tries < 5; tries++) {
1769 temp = I915_READ(reg);
1770 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1771
1772 if ((temp & FDI_RX_BIT_LOCK)) {
1773 DRM_DEBUG_KMS("FDI train 1 done.\n");
1774 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
1775 break;
1776 }
1777 }
1778 if (tries == 5)
1779 DRM_ERROR("FDI train 1 fail!\n");
1780
1781 /* Train 2 */
1782 reg = FDI_TX_CTL(pipe);
1783 temp = I915_READ(reg);
1784 temp &= ~FDI_LINK_TRAIN_NONE;
1785 temp |= FDI_LINK_TRAIN_PATTERN_2;
1786 I915_WRITE(reg, temp);
1787
1788 reg = FDI_RX_CTL(pipe);
1789 temp = I915_READ(reg);
1790 temp &= ~FDI_LINK_TRAIN_NONE;
1791 temp |= FDI_LINK_TRAIN_PATTERN_2;
1792 I915_WRITE(reg, temp);
1793
1794 POSTING_READ(reg);
1795 udelay(150);
1796
1797 reg = FDI_RX_IIR(pipe);
1798 for (tries = 0; tries < 5; tries++) {
1799 temp = I915_READ(reg);
1800 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1801
1802 if (temp & FDI_RX_SYMBOL_LOCK) {
1803 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
1804 DRM_DEBUG_KMS("FDI train 2 done.\n");
1805 break;
1806 }
1807 }
1808 if (tries == 5)
1809 DRM_ERROR("FDI train 2 fail!\n");
1810
1811 DRM_DEBUG_KMS("FDI train done\n");
1812
1813 }
1814
1815 static const int const snb_b_fdi_train_param [] = {
1816 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1817 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1818 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1819 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1820 };
1821
1822 /* The FDI link training functions for SNB/Cougarpoint. */
1823 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1824 {
1825 struct drm_device *dev = crtc->dev;
1826 struct drm_i915_private *dev_priv = dev->dev_private;
1827 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1828 int pipe = intel_crtc->pipe;
1829 u32 reg, temp, i;
1830
1831 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1832 for train result */
1833 reg = FDI_RX_IMR(pipe);
1834 temp = I915_READ(reg);
1835 temp &= ~FDI_RX_SYMBOL_LOCK;
1836 temp &= ~FDI_RX_BIT_LOCK;
1837 I915_WRITE(reg, temp);
1838
1839 POSTING_READ(reg);
1840 udelay(150);
1841
1842 /* enable CPU FDI TX and PCH FDI RX */
1843 reg = FDI_TX_CTL(pipe);
1844 temp = I915_READ(reg);
1845 temp &= ~(7 << 19);
1846 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1847 temp &= ~FDI_LINK_TRAIN_NONE;
1848 temp |= FDI_LINK_TRAIN_PATTERN_1;
1849 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1850 /* SNB-B */
1851 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1852 I915_WRITE(reg, temp | FDI_TX_ENABLE);
1853
1854 reg = FDI_RX_CTL(pipe);
1855 temp = I915_READ(reg);
1856 if (HAS_PCH_CPT(dev)) {
1857 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1858 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1859 } else {
1860 temp &= ~FDI_LINK_TRAIN_NONE;
1861 temp |= FDI_LINK_TRAIN_PATTERN_1;
1862 }
1863 I915_WRITE(reg, temp | FDI_RX_ENABLE);
1864
1865 POSTING_READ(reg);
1866 udelay(150);
1867
1868 for (i = 0; i < 4; i++ ) {
1869 reg = FDI_TX_CTL(pipe);
1870 temp = I915_READ(reg);
1871 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1872 temp |= snb_b_fdi_train_param[i];
1873 I915_WRITE(reg, temp);
1874
1875 POSTING_READ(reg);
1876 udelay(500);
1877
1878 reg = FDI_RX_IIR(pipe);
1879 temp = I915_READ(reg);
1880 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1881
1882 if (temp & FDI_RX_BIT_LOCK) {
1883 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
1884 DRM_DEBUG_KMS("FDI train 1 done.\n");
1885 break;
1886 }
1887 }
1888 if (i == 4)
1889 DRM_ERROR("FDI train 1 fail!\n");
1890
1891 /* Train 2 */
1892 reg = FDI_TX_CTL(pipe);
1893 temp = I915_READ(reg);
1894 temp &= ~FDI_LINK_TRAIN_NONE;
1895 temp |= FDI_LINK_TRAIN_PATTERN_2;
1896 if (IS_GEN6(dev)) {
1897 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1898 /* SNB-B */
1899 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1900 }
1901 I915_WRITE(reg, temp);
1902
1903 reg = FDI_RX_CTL(pipe);
1904 temp = I915_READ(reg);
1905 if (HAS_PCH_CPT(dev)) {
1906 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1907 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1908 } else {
1909 temp &= ~FDI_LINK_TRAIN_NONE;
1910 temp |= FDI_LINK_TRAIN_PATTERN_2;
1911 }
1912 I915_WRITE(reg, temp);
1913
1914 POSTING_READ(reg);
1915 udelay(150);
1916
1917 for (i = 0; i < 4; i++ ) {
1918 reg = FDI_TX_CTL(pipe);
1919 temp = I915_READ(reg);
1920 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1921 temp |= snb_b_fdi_train_param[i];
1922 I915_WRITE(reg, temp);
1923
1924 POSTING_READ(reg);
1925 udelay(500);
1926
1927 reg = FDI_RX_IIR(pipe);
1928 temp = I915_READ(reg);
1929 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1930
1931 if (temp & FDI_RX_SYMBOL_LOCK) {
1932 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
1933 DRM_DEBUG_KMS("FDI train 2 done.\n");
1934 break;
1935 }
1936 }
1937 if (i == 4)
1938 DRM_ERROR("FDI train 2 fail!\n");
1939
1940 DRM_DEBUG_KMS("FDI train done.\n");
1941 }
1942
1943 static void ironlake_fdi_enable(struct drm_crtc *crtc)
1944 {
1945 struct drm_device *dev = crtc->dev;
1946 struct drm_i915_private *dev_priv = dev->dev_private;
1947 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1948 int pipe = intel_crtc->pipe;
1949 u32 reg, temp;
1950
1951 /* Write the TU size bits so error detection works */
1952 I915_WRITE(FDI_RX_TUSIZE1(pipe),
1953 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
1954
1955 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1956 reg = FDI_RX_CTL(pipe);
1957 temp = I915_READ(reg);
1958 temp &= ~((0x7 << 19) | (0x7 << 16));
1959 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1960 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
1961 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
1962
1963 POSTING_READ(reg);
1964 udelay(200);
1965
1966 /* Switch from Rawclk to PCDclk */
1967 temp = I915_READ(reg);
1968 I915_WRITE(reg, temp | FDI_PCDCLK);
1969
1970 POSTING_READ(reg);
1971 udelay(200);
1972
1973 /* Enable CPU FDI TX PLL, always on for Ironlake */
1974 reg = FDI_TX_CTL(pipe);
1975 temp = I915_READ(reg);
1976 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1977 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
1978
1979 POSTING_READ(reg);
1980 udelay(100);
1981 }
1982 }
1983
1984 static void intel_flush_display_plane(struct drm_device *dev,
1985 int plane)
1986 {
1987 struct drm_i915_private *dev_priv = dev->dev_private;
1988 u32 reg = DSPADDR(plane);
1989 I915_WRITE(reg, I915_READ(reg));
1990 }
1991
1992 /*
1993 * When we disable a pipe, we need to clear any pending scanline wait events
1994 * to avoid hanging the ring, which we assume we are waiting on.
1995 */
1996 static void intel_clear_scanline_wait(struct drm_device *dev)
1997 {
1998 struct drm_i915_private *dev_priv = dev->dev_private;
1999 u32 tmp;
2000
2001 if (IS_GEN2(dev))
2002 /* Can't break the hang on i8xx */
2003 return;
2004
2005 tmp = I915_READ(PRB0_CTL);
2006 if (tmp & RING_WAIT) {
2007 I915_WRITE(PRB0_CTL, tmp);
2008 POSTING_READ(PRB0_CTL);
2009 }
2010 }
2011
2012 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2013 {
2014 struct drm_i915_gem_object *obj_priv;
2015 struct drm_i915_private *dev_priv;
2016
2017 if (crtc->fb == NULL)
2018 return;
2019
2020 obj_priv = to_intel_bo(to_intel_framebuffer(crtc->fb)->obj);
2021 dev_priv = crtc->dev->dev_private;
2022 wait_event(dev_priv->pending_flip_queue,
2023 atomic_read(&obj_priv->pending_flip) == 0);
2024 }
2025
2026 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2027 {
2028 struct drm_device *dev = crtc->dev;
2029 struct drm_i915_private *dev_priv = dev->dev_private;
2030 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2031 int pipe = intel_crtc->pipe;
2032 int plane = intel_crtc->plane;
2033 u32 reg, temp;
2034
2035 if (intel_crtc->active)
2036 return;
2037
2038 intel_crtc->active = true;
2039 intel_update_watermarks(dev);
2040
2041 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2042 temp = I915_READ(PCH_LVDS);
2043 if ((temp & LVDS_PORT_EN) == 0)
2044 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2045 }
2046
2047 ironlake_fdi_enable(crtc);
2048
2049 /* Enable panel fitting for LVDS */
2050 if (dev_priv->pch_pf_size &&
2051 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2052 /* Force use of hard-coded filter coefficients
2053 * as some pre-programmed values are broken,
2054 * e.g. x201.
2055 */
2056 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1,
2057 PF_ENABLE | PF_FILTER_MED_3x3);
2058 I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS,
2059 dev_priv->pch_pf_pos);
2060 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ,
2061 dev_priv->pch_pf_size);
2062 }
2063
2064 /* Enable CPU pipe */
2065 reg = PIPECONF(pipe);
2066 temp = I915_READ(reg);
2067 if ((temp & PIPECONF_ENABLE) == 0) {
2068 I915_WRITE(reg, temp | PIPECONF_ENABLE);
2069 POSTING_READ(reg);
2070 intel_wait_for_vblank(dev, intel_crtc->pipe);
2071 }
2072
2073 /* configure and enable CPU plane */
2074 reg = DSPCNTR(plane);
2075 temp = I915_READ(reg);
2076 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2077 I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
2078 intel_flush_display_plane(dev, plane);
2079 }
2080
2081 /* For PCH output, training FDI link */
2082 if (IS_GEN6(dev))
2083 gen6_fdi_link_train(crtc);
2084 else
2085 ironlake_fdi_link_train(crtc);
2086
2087 /* enable PCH DPLL */
2088 reg = PCH_DPLL(pipe);
2089 temp = I915_READ(reg);
2090 if ((temp & DPLL_VCO_ENABLE) == 0) {
2091 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2092 POSTING_READ(reg);
2093 udelay(200);
2094 }
2095
2096 if (HAS_PCH_CPT(dev)) {
2097 /* Be sure PCH DPLL SEL is set */
2098 temp = I915_READ(PCH_DPLL_SEL);
2099 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
2100 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2101 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
2102 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2103 I915_WRITE(PCH_DPLL_SEL, temp);
2104 }
2105
2106 /* set transcoder timing */
2107 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2108 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2109 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
2110
2111 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2112 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2113 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
2114
2115 intel_fdi_normal_train(crtc);
2116
2117 /* For PCH DP, enable TRANS_DP_CTL */
2118 if (HAS_PCH_CPT(dev) &&
2119 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2120 reg = TRANS_DP_CTL(pipe);
2121 temp = I915_READ(reg);
2122 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2123 TRANS_DP_SYNC_MASK |
2124 TRANS_DP_BPC_MASK);
2125 temp |= (TRANS_DP_OUTPUT_ENABLE |
2126 TRANS_DP_ENH_FRAMING);
2127 temp |= TRANS_DP_8BPC;
2128
2129 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2130 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2131 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2132 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2133
2134 switch (intel_trans_dp_port_sel(crtc)) {
2135 case PCH_DP_B:
2136 temp |= TRANS_DP_PORT_SEL_B;
2137 break;
2138 case PCH_DP_C:
2139 temp |= TRANS_DP_PORT_SEL_C;
2140 break;
2141 case PCH_DP_D:
2142 temp |= TRANS_DP_PORT_SEL_D;
2143 break;
2144 default:
2145 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2146 temp |= TRANS_DP_PORT_SEL_B;
2147 break;
2148 }
2149
2150 I915_WRITE(reg, temp);
2151 }
2152
2153 /* enable PCH transcoder */
2154 reg = TRANSCONF(pipe);
2155 temp = I915_READ(reg);
2156 /*
2157 * make the BPC in transcoder be consistent with
2158 * that in pipeconf reg.
2159 */
2160 temp &= ~PIPE_BPC_MASK;
2161 temp |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
2162 I915_WRITE(reg, temp | TRANS_ENABLE);
2163 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2164 DRM_ERROR("failed to enable transcoder %d\n", pipe);
2165
2166 intel_crtc_load_lut(crtc);
2167 intel_update_fbc(dev);
2168 intel_crtc_update_cursor(crtc, true);
2169 }
2170
2171 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2172 {
2173 struct drm_device *dev = crtc->dev;
2174 struct drm_i915_private *dev_priv = dev->dev_private;
2175 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2176 int pipe = intel_crtc->pipe;
2177 int plane = intel_crtc->plane;
2178 u32 reg, temp;
2179
2180 if (!intel_crtc->active)
2181 return;
2182
2183 intel_crtc_wait_for_pending_flips(crtc);
2184 drm_vblank_off(dev, pipe);
2185 intel_crtc_update_cursor(crtc, false);
2186
2187 /* Disable display plane */
2188 reg = DSPCNTR(plane);
2189 temp = I915_READ(reg);
2190 if (temp & DISPLAY_PLANE_ENABLE) {
2191 I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
2192 intel_flush_display_plane(dev, plane);
2193 }
2194
2195 if (dev_priv->cfb_plane == plane &&
2196 dev_priv->display.disable_fbc)
2197 dev_priv->display.disable_fbc(dev);
2198
2199 /* disable cpu pipe, disable after all planes disabled */
2200 reg = PIPECONF(pipe);
2201 temp = I915_READ(reg);
2202 if (temp & PIPECONF_ENABLE) {
2203 I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
2204 POSTING_READ(reg);
2205 /* wait for cpu pipe off, pipe state */
2206 intel_wait_for_pipe_off(dev, intel_crtc->pipe);
2207 }
2208
2209 /* Disable PF */
2210 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0);
2211 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0);
2212
2213 /* disable CPU FDI tx and PCH FDI rx */
2214 reg = FDI_TX_CTL(pipe);
2215 temp = I915_READ(reg);
2216 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2217 POSTING_READ(reg);
2218
2219 reg = FDI_RX_CTL(pipe);
2220 temp = I915_READ(reg);
2221 temp &= ~(0x7 << 16);
2222 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2223 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2224
2225 POSTING_READ(reg);
2226 udelay(100);
2227
2228 /* Ironlake workaround, disable clock pointer after downing FDI */
2229 if (HAS_PCH_IBX(dev))
2230 I915_WRITE(FDI_RX_CHICKEN(pipe),
2231 I915_READ(FDI_RX_CHICKEN(pipe) &
2232 ~FDI_RX_PHASE_SYNC_POINTER_ENABLE));
2233
2234 /* still set train pattern 1 */
2235 reg = FDI_TX_CTL(pipe);
2236 temp = I915_READ(reg);
2237 temp &= ~FDI_LINK_TRAIN_NONE;
2238 temp |= FDI_LINK_TRAIN_PATTERN_1;
2239 I915_WRITE(reg, temp);
2240
2241 reg = FDI_RX_CTL(pipe);
2242 temp = I915_READ(reg);
2243 if (HAS_PCH_CPT(dev)) {
2244 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2245 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2246 } else {
2247 temp &= ~FDI_LINK_TRAIN_NONE;
2248 temp |= FDI_LINK_TRAIN_PATTERN_1;
2249 }
2250 /* BPC in FDI rx is consistent with that in PIPECONF */
2251 temp &= ~(0x07 << 16);
2252 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2253 I915_WRITE(reg, temp);
2254
2255 POSTING_READ(reg);
2256 udelay(100);
2257
2258 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2259 temp = I915_READ(PCH_LVDS);
2260 if (temp & LVDS_PORT_EN) {
2261 I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2262 POSTING_READ(PCH_LVDS);
2263 udelay(100);
2264 }
2265 }
2266
2267 /* disable PCH transcoder */
2268 reg = TRANSCONF(plane);
2269 temp = I915_READ(reg);
2270 if (temp & TRANS_ENABLE) {
2271 I915_WRITE(reg, temp & ~TRANS_ENABLE);
2272 /* wait for PCH transcoder off, transcoder state */
2273 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2274 DRM_ERROR("failed to disable transcoder\n");
2275 }
2276
2277 if (HAS_PCH_CPT(dev)) {
2278 /* disable TRANS_DP_CTL */
2279 reg = TRANS_DP_CTL(pipe);
2280 temp = I915_READ(reg);
2281 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2282 I915_WRITE(reg, temp);
2283
2284 /* disable DPLL_SEL */
2285 temp = I915_READ(PCH_DPLL_SEL);
2286 if (pipe == 0)
2287 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2288 else
2289 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2290 I915_WRITE(PCH_DPLL_SEL, temp);
2291 }
2292
2293 /* disable PCH DPLL */
2294 reg = PCH_DPLL(pipe);
2295 temp = I915_READ(reg);
2296 I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);
2297
2298 /* Switch from PCDclk to Rawclk */
2299 reg = FDI_RX_CTL(pipe);
2300 temp = I915_READ(reg);
2301 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2302
2303 /* Disable CPU FDI TX PLL */
2304 reg = FDI_TX_CTL(pipe);
2305 temp = I915_READ(reg);
2306 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2307
2308 POSTING_READ(reg);
2309 udelay(100);
2310
2311 reg = FDI_RX_CTL(pipe);
2312 temp = I915_READ(reg);
2313 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2314
2315 /* Wait for the clocks to turn off. */
2316 POSTING_READ(reg);
2317 udelay(100);
2318
2319 intel_crtc->active = false;
2320 intel_update_watermarks(dev);
2321 intel_update_fbc(dev);
2322 intel_clear_scanline_wait(dev);
2323 }
2324
2325 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2326 {
2327 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2328 int pipe = intel_crtc->pipe;
2329 int plane = intel_crtc->plane;
2330
2331 /* XXX: When our outputs are all unaware of DPMS modes other than off
2332 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2333 */
2334 switch (mode) {
2335 case DRM_MODE_DPMS_ON:
2336 case DRM_MODE_DPMS_STANDBY:
2337 case DRM_MODE_DPMS_SUSPEND:
2338 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2339 ironlake_crtc_enable(crtc);
2340 break;
2341
2342 case DRM_MODE_DPMS_OFF:
2343 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2344 ironlake_crtc_disable(crtc);
2345 break;
2346 }
2347 }
2348
2349 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2350 {
2351 if (!enable && intel_crtc->overlay) {
2352 struct drm_device *dev = intel_crtc->base.dev;
2353
2354 mutex_lock(&dev->struct_mutex);
2355 (void) intel_overlay_switch_off(intel_crtc->overlay, false);
2356 mutex_unlock(&dev->struct_mutex);
2357 }
2358
2359 /* Let userspace switch the overlay on again. In most cases userspace
2360 * has to recompute where to put it anyway.
2361 */
2362 }
2363
2364 static void i9xx_crtc_enable(struct drm_crtc *crtc)
2365 {
2366 struct drm_device *dev = crtc->dev;
2367 struct drm_i915_private *dev_priv = dev->dev_private;
2368 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2369 int pipe = intel_crtc->pipe;
2370 int plane = intel_crtc->plane;
2371 u32 reg, temp;
2372
2373 if (intel_crtc->active)
2374 return;
2375
2376 intel_crtc->active = true;
2377 intel_update_watermarks(dev);
2378
2379 /* Enable the DPLL */
2380 reg = DPLL(pipe);
2381 temp = I915_READ(reg);
2382 if ((temp & DPLL_VCO_ENABLE) == 0) {
2383 I915_WRITE(reg, temp);
2384
2385 /* Wait for the clocks to stabilize. */
2386 POSTING_READ(reg);
2387 udelay(150);
2388
2389 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2390
2391 /* Wait for the clocks to stabilize. */
2392 POSTING_READ(reg);
2393 udelay(150);
2394
2395 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2396
2397 /* Wait for the clocks to stabilize. */
2398 POSTING_READ(reg);
2399 udelay(150);
2400 }
2401
2402 /* Enable the pipe */
2403 reg = PIPECONF(pipe);
2404 temp = I915_READ(reg);
2405 if ((temp & PIPECONF_ENABLE) == 0)
2406 I915_WRITE(reg, temp | PIPECONF_ENABLE);
2407
2408 /* Enable the plane */
2409 reg = DSPCNTR(plane);
2410 temp = I915_READ(reg);
2411 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2412 I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
2413 intel_flush_display_plane(dev, plane);
2414 }
2415
2416 intel_crtc_load_lut(crtc);
2417 intel_update_fbc(dev);
2418
2419 /* Give the overlay scaler a chance to enable if it's on this pipe */
2420 intel_crtc_dpms_overlay(intel_crtc, true);
2421 intel_crtc_update_cursor(crtc, true);
2422 }
2423
2424 static void i9xx_crtc_disable(struct drm_crtc *crtc)
2425 {
2426 struct drm_device *dev = crtc->dev;
2427 struct drm_i915_private *dev_priv = dev->dev_private;
2428 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2429 int pipe = intel_crtc->pipe;
2430 int plane = intel_crtc->plane;
2431 u32 reg, temp;
2432
2433 if (!intel_crtc->active)
2434 return;
2435
2436 /* Give the overlay scaler a chance to disable if it's on this pipe */
2437 intel_crtc_wait_for_pending_flips(crtc);
2438 drm_vblank_off(dev, pipe);
2439 intel_crtc_dpms_overlay(intel_crtc, false);
2440 intel_crtc_update_cursor(crtc, false);
2441
2442 if (dev_priv->cfb_plane == plane &&
2443 dev_priv->display.disable_fbc)
2444 dev_priv->display.disable_fbc(dev);
2445
2446 /* Disable display plane */
2447 reg = DSPCNTR(plane);
2448 temp = I915_READ(reg);
2449 if (temp & DISPLAY_PLANE_ENABLE) {
2450 I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
2451 /* Flush the plane changes */
2452 intel_flush_display_plane(dev, plane);
2453
2454 /* Wait for vblank for the disable to take effect */
2455 if (IS_GEN2(dev))
2456 intel_wait_for_vblank(dev, pipe);
2457 }
2458
2459 /* Don't disable pipe A or pipe A PLLs if needed */
2460 if (pipe == 0 && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2461 goto done;
2462
2463 /* Next, disable display pipes */
2464 reg = PIPECONF(pipe);
2465 temp = I915_READ(reg);
2466 if (temp & PIPECONF_ENABLE) {
2467 I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
2468
2469 /* Wait for the pipe to turn off */
2470 POSTING_READ(reg);
2471 intel_wait_for_pipe_off(dev, pipe);
2472 }
2473
2474 reg = DPLL(pipe);
2475 temp = I915_READ(reg);
2476 if (temp & DPLL_VCO_ENABLE) {
2477 I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);
2478
2479 /* Wait for the clocks to turn off. */
2480 POSTING_READ(reg);
2481 udelay(150);
2482 }
2483
2484 done:
2485 intel_crtc->active = false;
2486 intel_update_fbc(dev);
2487 intel_update_watermarks(dev);
2488 intel_clear_scanline_wait(dev);
2489 }
2490
2491 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2492 {
2493 /* XXX: When our outputs are all unaware of DPMS modes other than off
2494 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2495 */
2496 switch (mode) {
2497 case DRM_MODE_DPMS_ON:
2498 case DRM_MODE_DPMS_STANDBY:
2499 case DRM_MODE_DPMS_SUSPEND:
2500 i9xx_crtc_enable(crtc);
2501 break;
2502 case DRM_MODE_DPMS_OFF:
2503 i9xx_crtc_disable(crtc);
2504 break;
2505 }
2506 }
2507
2508 /**
2509 * Sets the power management mode of the pipe and plane.
2510 */
2511 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2512 {
2513 struct drm_device *dev = crtc->dev;
2514 struct drm_i915_private *dev_priv = dev->dev_private;
2515 struct drm_i915_master_private *master_priv;
2516 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2517 int pipe = intel_crtc->pipe;
2518 bool enabled;
2519
2520 if (intel_crtc->dpms_mode == mode)
2521 return;
2522
2523 intel_crtc->dpms_mode = mode;
2524
2525 dev_priv->display.dpms(crtc, mode);
2526
2527 if (!dev->primary->master)
2528 return;
2529
2530 master_priv = dev->primary->master->driver_priv;
2531 if (!master_priv->sarea_priv)
2532 return;
2533
2534 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2535
2536 switch (pipe) {
2537 case 0:
2538 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2539 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2540 break;
2541 case 1:
2542 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2543 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2544 break;
2545 default:
2546 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2547 break;
2548 }
2549 }
2550
2551 static void intel_crtc_disable(struct drm_crtc *crtc)
2552 {
2553 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2554 struct drm_device *dev = crtc->dev;
2555
2556 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2557
2558 if (crtc->fb) {
2559 mutex_lock(&dev->struct_mutex);
2560 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2561 mutex_unlock(&dev->struct_mutex);
2562 }
2563 }
2564
2565 /* Prepare for a mode set.
2566 *
2567 * Note we could be a lot smarter here. We need to figure out which outputs
2568 * will be enabled, which disabled (in short, how the config will changes)
2569 * and perform the minimum necessary steps to accomplish that, e.g. updating
2570 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
2571 * panel fitting is in the proper state, etc.
2572 */
2573 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
2574 {
2575 i9xx_crtc_disable(crtc);
2576 }
2577
2578 static void i9xx_crtc_commit(struct drm_crtc *crtc)
2579 {
2580 i9xx_crtc_enable(crtc);
2581 }
2582
2583 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
2584 {
2585 ironlake_crtc_disable(crtc);
2586 }
2587
2588 static void ironlake_crtc_commit(struct drm_crtc *crtc)
2589 {
2590 ironlake_crtc_enable(crtc);
2591 }
2592
2593 void intel_encoder_prepare (struct drm_encoder *encoder)
2594 {
2595 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2596 /* lvds has its own version of prepare see intel_lvds_prepare */
2597 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2598 }
2599
2600 void intel_encoder_commit (struct drm_encoder *encoder)
2601 {
2602 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2603 /* lvds has its own version of commit see intel_lvds_commit */
2604 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2605 }
2606
2607 void intel_encoder_destroy(struct drm_encoder *encoder)
2608 {
2609 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2610
2611 drm_encoder_cleanup(encoder);
2612 kfree(intel_encoder);
2613 }
2614
2615 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2616 struct drm_display_mode *mode,
2617 struct drm_display_mode *adjusted_mode)
2618 {
2619 struct drm_device *dev = crtc->dev;
2620
2621 if (HAS_PCH_SPLIT(dev)) {
2622 /* FDI link clock is fixed at 2.7G */
2623 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
2624 return false;
2625 }
2626
2627 /* XXX some encoders set the crtcinfo, others don't.
2628 * Obviously we need some form of conflict resolution here...
2629 */
2630 if (adjusted_mode->crtc_htotal == 0)
2631 drm_mode_set_crtcinfo(adjusted_mode, 0);
2632
2633 return true;
2634 }
2635
2636 static int i945_get_display_clock_speed(struct drm_device *dev)
2637 {
2638 return 400000;
2639 }
2640
2641 static int i915_get_display_clock_speed(struct drm_device *dev)
2642 {
2643 return 333000;
2644 }
2645
2646 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2647 {
2648 return 200000;
2649 }
2650
2651 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2652 {
2653 u16 gcfgc = 0;
2654
2655 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2656
2657 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2658 return 133000;
2659 else {
2660 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2661 case GC_DISPLAY_CLOCK_333_MHZ:
2662 return 333000;
2663 default:
2664 case GC_DISPLAY_CLOCK_190_200_MHZ:
2665 return 190000;
2666 }
2667 }
2668 }
2669
2670 static int i865_get_display_clock_speed(struct drm_device *dev)
2671 {
2672 return 266000;
2673 }
2674
2675 static int i855_get_display_clock_speed(struct drm_device *dev)
2676 {
2677 u16 hpllcc = 0;
2678 /* Assume that the hardware is in the high speed state. This
2679 * should be the default.
2680 */
2681 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2682 case GC_CLOCK_133_200:
2683 case GC_CLOCK_100_200:
2684 return 200000;
2685 case GC_CLOCK_166_250:
2686 return 250000;
2687 case GC_CLOCK_100_133:
2688 return 133000;
2689 }
2690
2691 /* Shouldn't happen */
2692 return 0;
2693 }
2694
2695 static int i830_get_display_clock_speed(struct drm_device *dev)
2696 {
2697 return 133000;
2698 }
2699
2700 struct fdi_m_n {
2701 u32 tu;
2702 u32 gmch_m;
2703 u32 gmch_n;
2704 u32 link_m;
2705 u32 link_n;
2706 };
2707
2708 static void
2709 fdi_reduce_ratio(u32 *num, u32 *den)
2710 {
2711 while (*num > 0xffffff || *den > 0xffffff) {
2712 *num >>= 1;
2713 *den >>= 1;
2714 }
2715 }
2716
2717 #define DATA_N 0x800000
2718 #define LINK_N 0x80000
2719
2720 static void
2721 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2722 int link_clock, struct fdi_m_n *m_n)
2723 {
2724 u64 temp;
2725
2726 m_n->tu = 64; /* default size */
2727
2728 temp = (u64) DATA_N * pixel_clock;
2729 temp = div_u64(temp, link_clock);
2730 m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2731 m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2732 m_n->gmch_n = DATA_N;
2733 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2734
2735 temp = (u64) LINK_N * pixel_clock;
2736 m_n->link_m = div_u64(temp, link_clock);
2737 m_n->link_n = LINK_N;
2738 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2739 }
2740
2741
2742 struct intel_watermark_params {
2743 unsigned long fifo_size;
2744 unsigned long max_wm;
2745 unsigned long default_wm;
2746 unsigned long guard_size;
2747 unsigned long cacheline_size;
2748 };
2749
2750 /* Pineview has different values for various configs */
2751 static struct intel_watermark_params pineview_display_wm = {
2752 PINEVIEW_DISPLAY_FIFO,
2753 PINEVIEW_MAX_WM,
2754 PINEVIEW_DFT_WM,
2755 PINEVIEW_GUARD_WM,
2756 PINEVIEW_FIFO_LINE_SIZE
2757 };
2758 static struct intel_watermark_params pineview_display_hplloff_wm = {
2759 PINEVIEW_DISPLAY_FIFO,
2760 PINEVIEW_MAX_WM,
2761 PINEVIEW_DFT_HPLLOFF_WM,
2762 PINEVIEW_GUARD_WM,
2763 PINEVIEW_FIFO_LINE_SIZE
2764 };
2765 static struct intel_watermark_params pineview_cursor_wm = {
2766 PINEVIEW_CURSOR_FIFO,
2767 PINEVIEW_CURSOR_MAX_WM,
2768 PINEVIEW_CURSOR_DFT_WM,
2769 PINEVIEW_CURSOR_GUARD_WM,
2770 PINEVIEW_FIFO_LINE_SIZE,
2771 };
2772 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2773 PINEVIEW_CURSOR_FIFO,
2774 PINEVIEW_CURSOR_MAX_WM,
2775 PINEVIEW_CURSOR_DFT_WM,
2776 PINEVIEW_CURSOR_GUARD_WM,
2777 PINEVIEW_FIFO_LINE_SIZE
2778 };
2779 static struct intel_watermark_params g4x_wm_info = {
2780 G4X_FIFO_SIZE,
2781 G4X_MAX_WM,
2782 G4X_MAX_WM,
2783 2,
2784 G4X_FIFO_LINE_SIZE,
2785 };
2786 static struct intel_watermark_params g4x_cursor_wm_info = {
2787 I965_CURSOR_FIFO,
2788 I965_CURSOR_MAX_WM,
2789 I965_CURSOR_DFT_WM,
2790 2,
2791 G4X_FIFO_LINE_SIZE,
2792 };
2793 static struct intel_watermark_params i965_cursor_wm_info = {
2794 I965_CURSOR_FIFO,
2795 I965_CURSOR_MAX_WM,
2796 I965_CURSOR_DFT_WM,
2797 2,
2798 I915_FIFO_LINE_SIZE,
2799 };
2800 static struct intel_watermark_params i945_wm_info = {
2801 I945_FIFO_SIZE,
2802 I915_MAX_WM,
2803 1,
2804 2,
2805 I915_FIFO_LINE_SIZE
2806 };
2807 static struct intel_watermark_params i915_wm_info = {
2808 I915_FIFO_SIZE,
2809 I915_MAX_WM,
2810 1,
2811 2,
2812 I915_FIFO_LINE_SIZE
2813 };
2814 static struct intel_watermark_params i855_wm_info = {
2815 I855GM_FIFO_SIZE,
2816 I915_MAX_WM,
2817 1,
2818 2,
2819 I830_FIFO_LINE_SIZE
2820 };
2821 static struct intel_watermark_params i830_wm_info = {
2822 I830_FIFO_SIZE,
2823 I915_MAX_WM,
2824 1,
2825 2,
2826 I830_FIFO_LINE_SIZE
2827 };
2828
2829 static struct intel_watermark_params ironlake_display_wm_info = {
2830 ILK_DISPLAY_FIFO,
2831 ILK_DISPLAY_MAXWM,
2832 ILK_DISPLAY_DFTWM,
2833 2,
2834 ILK_FIFO_LINE_SIZE
2835 };
2836
2837 static struct intel_watermark_params ironlake_cursor_wm_info = {
2838 ILK_CURSOR_FIFO,
2839 ILK_CURSOR_MAXWM,
2840 ILK_CURSOR_DFTWM,
2841 2,
2842 ILK_FIFO_LINE_SIZE
2843 };
2844
2845 static struct intel_watermark_params ironlake_display_srwm_info = {
2846 ILK_DISPLAY_SR_FIFO,
2847 ILK_DISPLAY_MAX_SRWM,
2848 ILK_DISPLAY_DFT_SRWM,
2849 2,
2850 ILK_FIFO_LINE_SIZE
2851 };
2852
2853 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2854 ILK_CURSOR_SR_FIFO,
2855 ILK_CURSOR_MAX_SRWM,
2856 ILK_CURSOR_DFT_SRWM,
2857 2,
2858 ILK_FIFO_LINE_SIZE
2859 };
2860
2861 /**
2862 * intel_calculate_wm - calculate watermark level
2863 * @clock_in_khz: pixel clock
2864 * @wm: chip FIFO params
2865 * @pixel_size: display pixel size
2866 * @latency_ns: memory latency for the platform
2867 *
2868 * Calculate the watermark level (the level at which the display plane will
2869 * start fetching from memory again). Each chip has a different display
2870 * FIFO size and allocation, so the caller needs to figure that out and pass
2871 * in the correct intel_watermark_params structure.
2872 *
2873 * As the pixel clock runs, the FIFO will be drained at a rate that depends
2874 * on the pixel size. When it reaches the watermark level, it'll start
2875 * fetching FIFO line sized based chunks from memory until the FIFO fills
2876 * past the watermark point. If the FIFO drains completely, a FIFO underrun
2877 * will occur, and a display engine hang could result.
2878 */
2879 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2880 struct intel_watermark_params *wm,
2881 int pixel_size,
2882 unsigned long latency_ns)
2883 {
2884 long entries_required, wm_size;
2885
2886 /*
2887 * Note: we need to make sure we don't overflow for various clock &
2888 * latency values.
2889 * clocks go from a few thousand to several hundred thousand.
2890 * latency is usually a few thousand
2891 */
2892 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2893 1000;
2894 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
2895
2896 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2897
2898 wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2899
2900 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2901
2902 /* Don't promote wm_size to unsigned... */
2903 if (wm_size > (long)wm->max_wm)
2904 wm_size = wm->max_wm;
2905 if (wm_size <= 0)
2906 wm_size = wm->default_wm;
2907 return wm_size;
2908 }
2909
2910 struct cxsr_latency {
2911 int is_desktop;
2912 int is_ddr3;
2913 unsigned long fsb_freq;
2914 unsigned long mem_freq;
2915 unsigned long display_sr;
2916 unsigned long display_hpll_disable;
2917 unsigned long cursor_sr;
2918 unsigned long cursor_hpll_disable;
2919 };
2920
2921 static const struct cxsr_latency cxsr_latency_table[] = {
2922 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
2923 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
2924 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
2925 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
2926 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
2927
2928 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
2929 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
2930 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
2931 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
2932 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
2933
2934 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
2935 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
2936 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
2937 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
2938 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
2939
2940 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
2941 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
2942 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
2943 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
2944 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
2945
2946 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
2947 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
2948 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
2949 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
2950 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
2951
2952 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
2953 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
2954 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
2955 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
2956 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
2957 };
2958
2959 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
2960 int is_ddr3,
2961 int fsb,
2962 int mem)
2963 {
2964 const struct cxsr_latency *latency;
2965 int i;
2966
2967 if (fsb == 0 || mem == 0)
2968 return NULL;
2969
2970 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2971 latency = &cxsr_latency_table[i];
2972 if (is_desktop == latency->is_desktop &&
2973 is_ddr3 == latency->is_ddr3 &&
2974 fsb == latency->fsb_freq && mem == latency->mem_freq)
2975 return latency;
2976 }
2977
2978 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2979
2980 return NULL;
2981 }
2982
2983 static void pineview_disable_cxsr(struct drm_device *dev)
2984 {
2985 struct drm_i915_private *dev_priv = dev->dev_private;
2986
2987 /* deactivate cxsr */
2988 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
2989 }
2990
2991 /*
2992 * Latency for FIFO fetches is dependent on several factors:
2993 * - memory configuration (speed, channels)
2994 * - chipset
2995 * - current MCH state
2996 * It can be fairly high in some situations, so here we assume a fairly
2997 * pessimal value. It's a tradeoff between extra memory fetches (if we
2998 * set this value too high, the FIFO will fetch frequently to stay full)
2999 * and power consumption (set it too low to save power and we might see
3000 * FIFO underruns and display "flicker").
3001 *
3002 * A value of 5us seems to be a good balance; safe for very low end
3003 * platforms but not overly aggressive on lower latency configs.
3004 */
3005 static const int latency_ns = 5000;
3006
3007 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3008 {
3009 struct drm_i915_private *dev_priv = dev->dev_private;
3010 uint32_t dsparb = I915_READ(DSPARB);
3011 int size;
3012
3013 size = dsparb & 0x7f;
3014 if (plane)
3015 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3016
3017 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3018 plane ? "B" : "A", size);
3019
3020 return size;
3021 }
3022
3023 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3024 {
3025 struct drm_i915_private *dev_priv = dev->dev_private;
3026 uint32_t dsparb = I915_READ(DSPARB);
3027 int size;
3028
3029 size = dsparb & 0x1ff;
3030 if (plane)
3031 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3032 size >>= 1; /* Convert to cachelines */
3033
3034 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3035 plane ? "B" : "A", size);
3036
3037 return size;
3038 }
3039
3040 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3041 {
3042 struct drm_i915_private *dev_priv = dev->dev_private;
3043 uint32_t dsparb = I915_READ(DSPARB);
3044 int size;
3045
3046 size = dsparb & 0x7f;
3047 size >>= 2; /* Convert to cachelines */
3048
3049 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3050 plane ? "B" : "A",
3051 size);
3052
3053 return size;
3054 }
3055
3056 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3057 {
3058 struct drm_i915_private *dev_priv = dev->dev_private;
3059 uint32_t dsparb = I915_READ(DSPARB);
3060 int size;
3061
3062 size = dsparb & 0x7f;
3063 size >>= 1; /* Convert to cachelines */
3064
3065 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3066 plane ? "B" : "A", size);
3067
3068 return size;
3069 }
3070
3071 static void pineview_update_wm(struct drm_device *dev, int planea_clock,
3072 int planeb_clock, int sr_hdisplay, int unused,
3073 int pixel_size)
3074 {
3075 struct drm_i915_private *dev_priv = dev->dev_private;
3076 const struct cxsr_latency *latency;
3077 u32 reg;
3078 unsigned long wm;
3079 int sr_clock;
3080
3081 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3082 dev_priv->fsb_freq, dev_priv->mem_freq);
3083 if (!latency) {
3084 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3085 pineview_disable_cxsr(dev);
3086 return;
3087 }
3088
3089 if (!planea_clock || !planeb_clock) {
3090 sr_clock = planea_clock ? planea_clock : planeb_clock;
3091
3092 /* Display SR */
3093 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
3094 pixel_size, latency->display_sr);
3095 reg = I915_READ(DSPFW1);
3096 reg &= ~DSPFW_SR_MASK;
3097 reg |= wm << DSPFW_SR_SHIFT;
3098 I915_WRITE(DSPFW1, reg);
3099 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3100
3101 /* cursor SR */
3102 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
3103 pixel_size, latency->cursor_sr);
3104 reg = I915_READ(DSPFW3);
3105 reg &= ~DSPFW_CURSOR_SR_MASK;
3106 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3107 I915_WRITE(DSPFW3, reg);
3108
3109 /* Display HPLL off SR */
3110 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
3111 pixel_size, latency->display_hpll_disable);
3112 reg = I915_READ(DSPFW3);
3113 reg &= ~DSPFW_HPLL_SR_MASK;
3114 reg |= wm & DSPFW_HPLL_SR_MASK;
3115 I915_WRITE(DSPFW3, reg);
3116
3117 /* cursor HPLL off SR */
3118 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
3119 pixel_size, latency->cursor_hpll_disable);
3120 reg = I915_READ(DSPFW3);
3121 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3122 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3123 I915_WRITE(DSPFW3, reg);
3124 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3125
3126 /* activate cxsr */
3127 I915_WRITE(DSPFW3,
3128 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3129 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3130 } else {
3131 pineview_disable_cxsr(dev);
3132 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3133 }
3134 }
3135
3136 static void g4x_update_wm(struct drm_device *dev, int planea_clock,
3137 int planeb_clock, int sr_hdisplay, int sr_htotal,
3138 int pixel_size)
3139 {
3140 struct drm_i915_private *dev_priv = dev->dev_private;
3141 int total_size, cacheline_size;
3142 int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
3143 struct intel_watermark_params planea_params, planeb_params;
3144 unsigned long line_time_us;
3145 int sr_clock, sr_entries = 0, entries_required;
3146
3147 /* Create copies of the base settings for each pipe */
3148 planea_params = planeb_params = g4x_wm_info;
3149
3150 /* Grab a couple of global values before we overwrite them */
3151 total_size = planea_params.fifo_size;
3152 cacheline_size = planea_params.cacheline_size;
3153
3154 /*
3155 * Note: we need to make sure we don't overflow for various clock &
3156 * latency values.
3157 * clocks go from a few thousand to several hundred thousand.
3158 * latency is usually a few thousand
3159 */
3160 entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
3161 1000;
3162 entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3163 planea_wm = entries_required + planea_params.guard_size;
3164
3165 entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
3166 1000;
3167 entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3168 planeb_wm = entries_required + planeb_params.guard_size;
3169
3170 cursora_wm = cursorb_wm = 16;
3171 cursor_sr = 32;
3172
3173 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3174
3175 /* Calc sr entries for one plane configs */
3176 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3177 /* self-refresh has much higher latency */
3178 static const int sr_latency_ns = 12000;
3179
3180 sr_clock = planea_clock ? planea_clock : planeb_clock;
3181 line_time_us = ((sr_htotal * 1000) / sr_clock);
3182
3183 /* Use ns/us then divide to preserve precision */
3184 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3185 pixel_size * sr_hdisplay;
3186 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3187
3188 entries_required = (((sr_latency_ns / line_time_us) +
3189 1000) / 1000) * pixel_size * 64;
3190 entries_required = DIV_ROUND_UP(entries_required,
3191 g4x_cursor_wm_info.cacheline_size);
3192 cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
3193
3194 if (cursor_sr > g4x_cursor_wm_info.max_wm)
3195 cursor_sr = g4x_cursor_wm_info.max_wm;
3196 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3197 "cursor %d\n", sr_entries, cursor_sr);
3198
3199 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3200 } else {
3201 /* Turn off self refresh if both pipes are enabled */
3202 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3203 & ~FW_BLC_SELF_EN);
3204 }
3205
3206 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3207 planea_wm, planeb_wm, sr_entries);
3208
3209 planea_wm &= 0x3f;
3210 planeb_wm &= 0x3f;
3211
3212 I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
3213 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3214 (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
3215 I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3216 (cursora_wm << DSPFW_CURSORA_SHIFT));
3217 /* HPLL off in SR has some issues on G4x... disable it */
3218 I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3219 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3220 }
3221
3222 static void i965_update_wm(struct drm_device *dev, int planea_clock,
3223 int planeb_clock, int sr_hdisplay, int sr_htotal,
3224 int pixel_size)
3225 {
3226 struct drm_i915_private *dev_priv = dev->dev_private;
3227 unsigned long line_time_us;
3228 int sr_clock, sr_entries, srwm = 1;
3229 int cursor_sr = 16;
3230
3231 /* Calc sr entries for one plane configs */
3232 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3233 /* self-refresh has much higher latency */
3234 static const int sr_latency_ns = 12000;
3235
3236 sr_clock = planea_clock ? planea_clock : planeb_clock;
3237 line_time_us = ((sr_htotal * 1000) / sr_clock);
3238
3239 /* Use ns/us then divide to preserve precision */
3240 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3241 pixel_size * sr_hdisplay;
3242 sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE);
3243 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
3244 srwm = I965_FIFO_SIZE - sr_entries;
3245 if (srwm < 0)
3246 srwm = 1;
3247 srwm &= 0x1ff;
3248
3249 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3250 pixel_size * 64;
3251 sr_entries = DIV_ROUND_UP(sr_entries,
3252 i965_cursor_wm_info.cacheline_size);
3253 cursor_sr = i965_cursor_wm_info.fifo_size -
3254 (sr_entries + i965_cursor_wm_info.guard_size);
3255
3256 if (cursor_sr > i965_cursor_wm_info.max_wm)
3257 cursor_sr = i965_cursor_wm_info.max_wm;
3258
3259 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3260 "cursor %d\n", srwm, cursor_sr);
3261
3262 if (IS_CRESTLINE(dev))
3263 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3264 } else {
3265 /* Turn off self refresh if both pipes are enabled */
3266 if (IS_CRESTLINE(dev))
3267 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3268 & ~FW_BLC_SELF_EN);
3269 }
3270
3271 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3272 srwm);
3273
3274 /* 965 has limitations... */
3275 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
3276 (8 << 0));
3277 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3278 /* update cursor SR watermark */
3279 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3280 }
3281
3282 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
3283 int planeb_clock, int sr_hdisplay, int sr_htotal,
3284 int pixel_size)
3285 {
3286 struct drm_i915_private *dev_priv = dev->dev_private;
3287 uint32_t fwater_lo;
3288 uint32_t fwater_hi;
3289 int total_size, cacheline_size, cwm, srwm = 1;
3290 int planea_wm, planeb_wm;
3291 struct intel_watermark_params planea_params, planeb_params;
3292 unsigned long line_time_us;
3293 int sr_clock, sr_entries = 0;
3294
3295 /* Create copies of the base settings for each pipe */
3296 if (IS_CRESTLINE(dev) || IS_I945GM(dev))
3297 planea_params = planeb_params = i945_wm_info;
3298 else if (!IS_GEN2(dev))
3299 planea_params = planeb_params = i915_wm_info;
3300 else
3301 planea_params = planeb_params = i855_wm_info;
3302
3303 /* Grab a couple of global values before we overwrite them */
3304 total_size = planea_params.fifo_size;
3305 cacheline_size = planea_params.cacheline_size;
3306
3307 /* Update per-plane FIFO sizes */
3308 planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3309 planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3310
3311 planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3312 pixel_size, latency_ns);
3313 planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3314 pixel_size, latency_ns);
3315 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3316
3317 /*
3318 * Overlay gets an aggressive default since video jitter is bad.
3319 */
3320 cwm = 2;
3321
3322 /* Calc sr entries for one plane configs */
3323 if (HAS_FW_BLC(dev) && sr_hdisplay &&
3324 (!planea_clock || !planeb_clock)) {
3325 /* self-refresh has much higher latency */
3326 static const int sr_latency_ns = 6000;
3327
3328 sr_clock = planea_clock ? planea_clock : planeb_clock;
3329 line_time_us = ((sr_htotal * 1000) / sr_clock);
3330
3331 /* Use ns/us then divide to preserve precision */
3332 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3333 pixel_size * sr_hdisplay;
3334 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3335 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3336 srwm = total_size - sr_entries;
3337 if (srwm < 0)
3338 srwm = 1;
3339
3340 if (IS_I945G(dev) || IS_I945GM(dev))
3341 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3342 else if (IS_I915GM(dev)) {
3343 /* 915M has a smaller SRWM field */
3344 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3345 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3346 }
3347 } else {
3348 /* Turn off self refresh if both pipes are enabled */
3349 if (IS_I945G(dev) || IS_I945GM(dev)) {
3350 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3351 & ~FW_BLC_SELF_EN);
3352 } else if (IS_I915GM(dev)) {
3353 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3354 }
3355 }
3356
3357 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3358 planea_wm, planeb_wm, cwm, srwm);
3359
3360 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3361 fwater_hi = (cwm & 0x1f);
3362
3363 /* Set request length to 8 cachelines per fetch */
3364 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3365 fwater_hi = fwater_hi | (1 << 8);
3366
3367 I915_WRITE(FW_BLC, fwater_lo);
3368 I915_WRITE(FW_BLC2, fwater_hi);
3369 }
3370
3371 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3372 int unused2, int unused3, int pixel_size)
3373 {
3374 struct drm_i915_private *dev_priv = dev->dev_private;
3375 uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3376 int planea_wm;
3377
3378 i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3379
3380 planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3381 pixel_size, latency_ns);
3382 fwater_lo |= (3<<8) | planea_wm;
3383
3384 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3385
3386 I915_WRITE(FW_BLC, fwater_lo);
3387 }
3388
3389 #define ILK_LP0_PLANE_LATENCY 700
3390 #define ILK_LP0_CURSOR_LATENCY 1300
3391
3392 static bool ironlake_compute_wm0(struct drm_device *dev,
3393 int pipe,
3394 int *plane_wm,
3395 int *cursor_wm)
3396 {
3397 struct drm_crtc *crtc;
3398 int htotal, hdisplay, clock, pixel_size = 0;
3399 int line_time_us, line_count, entries;
3400
3401 crtc = intel_get_crtc_for_pipe(dev, pipe);
3402 if (crtc->fb == NULL || !crtc->enabled)
3403 return false;
3404
3405 htotal = crtc->mode.htotal;
3406 hdisplay = crtc->mode.hdisplay;
3407 clock = crtc->mode.clock;
3408 pixel_size = crtc->fb->bits_per_pixel / 8;
3409
3410 /* Use the small buffer method to calculate plane watermark */
3411 entries = ((clock * pixel_size / 1000) * ILK_LP0_PLANE_LATENCY) / 1000;
3412 entries = DIV_ROUND_UP(entries,
3413 ironlake_display_wm_info.cacheline_size);
3414 *plane_wm = entries + ironlake_display_wm_info.guard_size;
3415 if (*plane_wm > (int)ironlake_display_wm_info.max_wm)
3416 *plane_wm = ironlake_display_wm_info.max_wm;
3417
3418 /* Use the large buffer method to calculate cursor watermark */
3419 line_time_us = ((htotal * 1000) / clock);
3420 line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3421 entries = line_count * 64 * pixel_size;
3422 entries = DIV_ROUND_UP(entries,
3423 ironlake_cursor_wm_info.cacheline_size);
3424 *cursor_wm = entries + ironlake_cursor_wm_info.guard_size;
3425 if (*cursor_wm > ironlake_cursor_wm_info.max_wm)
3426 *cursor_wm = ironlake_cursor_wm_info.max_wm;
3427
3428 return true;
3429 }
3430
3431 static void ironlake_update_wm(struct drm_device *dev,
3432 int planea_clock, int planeb_clock,
3433 int sr_hdisplay, int sr_htotal,
3434 int pixel_size)
3435 {
3436 struct drm_i915_private *dev_priv = dev->dev_private;
3437 int plane_wm, cursor_wm, enabled;
3438 int tmp;
3439
3440 enabled = 0;
3441 if (ironlake_compute_wm0(dev, 0, &plane_wm, &cursor_wm)) {
3442 I915_WRITE(WM0_PIPEA_ILK,
3443 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3444 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
3445 " plane %d, " "cursor: %d\n",
3446 plane_wm, cursor_wm);
3447 enabled++;
3448 }
3449
3450 if (ironlake_compute_wm0(dev, 1, &plane_wm, &cursor_wm)) {
3451 I915_WRITE(WM0_PIPEB_ILK,
3452 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3453 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
3454 " plane %d, cursor: %d\n",
3455 plane_wm, cursor_wm);
3456 enabled++;
3457 }
3458
3459 /*
3460 * Calculate and update the self-refresh watermark only when one
3461 * display plane is used.
3462 */
3463 tmp = 0;
3464 if (enabled == 1 && /* XXX disabled due to buggy implmentation? */ 0) {
3465 unsigned long line_time_us;
3466 int small, large, plane_fbc;
3467 int sr_clock, entries;
3468 int line_count, line_size;
3469 /* Read the self-refresh latency. The unit is 0.5us */
3470 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
3471
3472 sr_clock = planea_clock ? planea_clock : planeb_clock;
3473 line_time_us = (sr_htotal * 1000) / sr_clock;
3474
3475 /* Use ns/us then divide to preserve precision */
3476 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
3477 / 1000;
3478 line_size = sr_hdisplay * pixel_size;
3479
3480 /* Use the minimum of the small and large buffer method for primary */
3481 small = ((sr_clock * pixel_size / 1000) * (ilk_sr_latency * 500)) / 1000;
3482 large = line_count * line_size;
3483
3484 entries = DIV_ROUND_UP(min(small, large),
3485 ironlake_display_srwm_info.cacheline_size);
3486
3487 plane_fbc = entries * 64;
3488 plane_fbc = DIV_ROUND_UP(plane_fbc, line_size);
3489
3490 plane_wm = entries + ironlake_display_srwm_info.guard_size;
3491 if (plane_wm > (int)ironlake_display_srwm_info.max_wm)
3492 plane_wm = ironlake_display_srwm_info.max_wm;
3493
3494 /* calculate the self-refresh watermark for display cursor */
3495 entries = line_count * pixel_size * 64;
3496 entries = DIV_ROUND_UP(entries,
3497 ironlake_cursor_srwm_info.cacheline_size);
3498
3499 cursor_wm = entries + ironlake_cursor_srwm_info.guard_size;
3500 if (cursor_wm > (int)ironlake_cursor_srwm_info.max_wm)
3501 cursor_wm = ironlake_cursor_srwm_info.max_wm;
3502
3503 /* configure watermark and enable self-refresh */
3504 tmp = (WM1_LP_SR_EN |
3505 (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3506 (plane_fbc << WM1_LP_FBC_SHIFT) |
3507 (plane_wm << WM1_LP_SR_SHIFT) |
3508 cursor_wm);
3509 DRM_DEBUG_KMS("self-refresh watermark: display plane %d, fbc lines %d,"
3510 " cursor %d\n", plane_wm, plane_fbc, cursor_wm);
3511 }
3512 I915_WRITE(WM1_LP_ILK, tmp);
3513 /* XXX setup WM2 and WM3 */
3514 }
3515
3516 /**
3517 * intel_update_watermarks - update FIFO watermark values based on current modes
3518 *
3519 * Calculate watermark values for the various WM regs based on current mode
3520 * and plane configuration.
3521 *
3522 * There are several cases to deal with here:
3523 * - normal (i.e. non-self-refresh)
3524 * - self-refresh (SR) mode
3525 * - lines are large relative to FIFO size (buffer can hold up to 2)
3526 * - lines are small relative to FIFO size (buffer can hold more than 2
3527 * lines), so need to account for TLB latency
3528 *
3529 * The normal calculation is:
3530 * watermark = dotclock * bytes per pixel * latency
3531 * where latency is platform & configuration dependent (we assume pessimal
3532 * values here).
3533 *
3534 * The SR calculation is:
3535 * watermark = (trunc(latency/line time)+1) * surface width *
3536 * bytes per pixel
3537 * where
3538 * line time = htotal / dotclock
3539 * surface width = hdisplay for normal plane and 64 for cursor
3540 * and latency is assumed to be high, as above.
3541 *
3542 * The final value programmed to the register should always be rounded up,
3543 * and include an extra 2 entries to account for clock crossings.
3544 *
3545 * We don't use the sprite, so we can ignore that. And on Crestline we have
3546 * to set the non-SR watermarks to 8.
3547 */
3548 static void intel_update_watermarks(struct drm_device *dev)
3549 {
3550 struct drm_i915_private *dev_priv = dev->dev_private;
3551 struct drm_crtc *crtc;
3552 int sr_hdisplay = 0;
3553 unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3554 int enabled = 0, pixel_size = 0;
3555 int sr_htotal = 0;
3556
3557 if (!dev_priv->display.update_wm)
3558 return;
3559
3560 /* Get the clock config from both planes */
3561 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3562 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3563 if (intel_crtc->active) {
3564 enabled++;
3565 if (intel_crtc->plane == 0) {
3566 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3567 intel_crtc->pipe, crtc->mode.clock);
3568 planea_clock = crtc->mode.clock;
3569 } else {
3570 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3571 intel_crtc->pipe, crtc->mode.clock);
3572 planeb_clock = crtc->mode.clock;
3573 }
3574 sr_hdisplay = crtc->mode.hdisplay;
3575 sr_clock = crtc->mode.clock;
3576 sr_htotal = crtc->mode.htotal;
3577 if (crtc->fb)
3578 pixel_size = crtc->fb->bits_per_pixel / 8;
3579 else
3580 pixel_size = 4; /* by default */
3581 }
3582 }
3583
3584 if (enabled <= 0)
3585 return;
3586
3587 dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3588 sr_hdisplay, sr_htotal, pixel_size);
3589 }
3590
3591 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3592 struct drm_display_mode *mode,
3593 struct drm_display_mode *adjusted_mode,
3594 int x, int y,
3595 struct drm_framebuffer *old_fb)
3596 {
3597 struct drm_device *dev = crtc->dev;
3598 struct drm_i915_private *dev_priv = dev->dev_private;
3599 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3600 int pipe = intel_crtc->pipe;
3601 int plane = intel_crtc->plane;
3602 u32 fp_reg, dpll_reg;
3603 int refclk, num_connectors = 0;
3604 intel_clock_t clock, reduced_clock;
3605 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
3606 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3607 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3608 struct intel_encoder *has_edp_encoder = NULL;
3609 struct drm_mode_config *mode_config = &dev->mode_config;
3610 struct intel_encoder *encoder;
3611 const intel_limit_t *limit;
3612 int ret;
3613 struct fdi_m_n m_n = {0};
3614 u32 reg, temp;
3615 int target_clock;
3616
3617 drm_vblank_pre_modeset(dev, pipe);
3618
3619 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3620 if (encoder->base.crtc != crtc)
3621 continue;
3622
3623 switch (encoder->type) {
3624 case INTEL_OUTPUT_LVDS:
3625 is_lvds = true;
3626 break;
3627 case INTEL_OUTPUT_SDVO:
3628 case INTEL_OUTPUT_HDMI:
3629 is_sdvo = true;
3630 if (encoder->needs_tv_clock)
3631 is_tv = true;
3632 break;
3633 case INTEL_OUTPUT_DVO:
3634 is_dvo = true;
3635 break;
3636 case INTEL_OUTPUT_TVOUT:
3637 is_tv = true;
3638 break;
3639 case INTEL_OUTPUT_ANALOG:
3640 is_crt = true;
3641 break;
3642 case INTEL_OUTPUT_DISPLAYPORT:
3643 is_dp = true;
3644 break;
3645 case INTEL_OUTPUT_EDP:
3646 has_edp_encoder = encoder;
3647 break;
3648 }
3649
3650 num_connectors++;
3651 }
3652
3653 if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
3654 refclk = dev_priv->lvds_ssc_freq * 1000;
3655 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3656 refclk / 1000);
3657 } else if (!IS_GEN2(dev)) {
3658 refclk = 96000;
3659 if (HAS_PCH_SPLIT(dev) &&
3660 (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)))
3661 refclk = 120000; /* 120Mhz refclk */
3662 } else {
3663 refclk = 48000;
3664 }
3665
3666 /*
3667 * Returns a set of divisors for the desired target clock with the given
3668 * refclk, or FALSE. The returned values represent the clock equation:
3669 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3670 */
3671 limit = intel_limit(crtc);
3672 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3673 if (!ok) {
3674 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3675 drm_vblank_post_modeset(dev, pipe);
3676 return -EINVAL;
3677 }
3678
3679 /* Ensure that the cursor is valid for the new mode before changing... */
3680 intel_crtc_update_cursor(crtc, true);
3681
3682 if (is_lvds && dev_priv->lvds_downclock_avail) {
3683 has_reduced_clock = limit->find_pll(limit, crtc,
3684 dev_priv->lvds_downclock,
3685 refclk,
3686 &reduced_clock);
3687 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3688 /*
3689 * If the different P is found, it means that we can't
3690 * switch the display clock by using the FP0/FP1.
3691 * In such case we will disable the LVDS downclock
3692 * feature.
3693 */
3694 DRM_DEBUG_KMS("Different P is found for "
3695 "LVDS clock/downclock\n");
3696 has_reduced_clock = 0;
3697 }
3698 }
3699 /* SDVO TV has fixed PLL values depend on its clock range,
3700 this mirrors vbios setting. */
3701 if (is_sdvo && is_tv) {
3702 if (adjusted_mode->clock >= 100000
3703 && adjusted_mode->clock < 140500) {
3704 clock.p1 = 2;
3705 clock.p2 = 10;
3706 clock.n = 3;
3707 clock.m1 = 16;
3708 clock.m2 = 8;
3709 } else if (adjusted_mode->clock >= 140500
3710 && adjusted_mode->clock <= 200000) {
3711 clock.p1 = 1;
3712 clock.p2 = 10;
3713 clock.n = 6;
3714 clock.m1 = 12;
3715 clock.m2 = 8;
3716 }
3717 }
3718
3719 /* FDI link */
3720 if (HAS_PCH_SPLIT(dev)) {
3721 int lane = 0, link_bw, bpp;
3722 /* CPU eDP doesn't require FDI link, so just set DP M/N
3723 according to current link config */
3724 if (has_edp_encoder && !intel_encoder_is_pch_edp(&encoder->base)) {
3725 target_clock = mode->clock;
3726 intel_edp_link_config(has_edp_encoder,
3727 &lane, &link_bw);
3728 } else {
3729 /* [e]DP over FDI requires target mode clock
3730 instead of link clock */
3731 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
3732 target_clock = mode->clock;
3733 else
3734 target_clock = adjusted_mode->clock;
3735
3736 /* FDI is a binary signal running at ~2.7GHz, encoding
3737 * each output octet as 10 bits. The actual frequency
3738 * is stored as a divider into a 100MHz clock, and the
3739 * mode pixel clock is stored in units of 1KHz.
3740 * Hence the bw of each lane in terms of the mode signal
3741 * is:
3742 */
3743 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
3744 }
3745
3746 /* determine panel color depth */
3747 temp = I915_READ(PIPECONF(pipe));
3748 temp &= ~PIPE_BPC_MASK;
3749 if (is_lvds) {
3750 /* the BPC will be 6 if it is 18-bit LVDS panel */
3751 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3752 temp |= PIPE_8BPC;
3753 else
3754 temp |= PIPE_6BPC;
3755 } else if (has_edp_encoder) {
3756 switch (dev_priv->edp.bpp/3) {
3757 case 8:
3758 temp |= PIPE_8BPC;
3759 break;
3760 case 10:
3761 temp |= PIPE_10BPC;
3762 break;
3763 case 6:
3764 temp |= PIPE_6BPC;
3765 break;
3766 case 12:
3767 temp |= PIPE_12BPC;
3768 break;
3769 }
3770 } else
3771 temp |= PIPE_8BPC;
3772 I915_WRITE(PIPECONF(pipe), temp);
3773
3774 switch (temp & PIPE_BPC_MASK) {
3775 case PIPE_8BPC:
3776 bpp = 24;
3777 break;
3778 case PIPE_10BPC:
3779 bpp = 30;
3780 break;
3781 case PIPE_6BPC:
3782 bpp = 18;
3783 break;
3784 case PIPE_12BPC:
3785 bpp = 36;
3786 break;
3787 default:
3788 DRM_ERROR("unknown pipe bpc value\n");
3789 bpp = 24;
3790 }
3791
3792 if (!lane) {
3793 /*
3794 * Account for spread spectrum to avoid
3795 * oversubscribing the link. Max center spread
3796 * is 2.5%; use 5% for safety's sake.
3797 */
3798 u32 bps = target_clock * bpp * 21 / 20;
3799 lane = bps / (link_bw * 8) + 1;
3800 }
3801
3802 intel_crtc->fdi_lanes = lane;
3803
3804 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3805 }
3806
3807 /* Ironlake: try to setup display ref clock before DPLL
3808 * enabling. This is only under driver's control after
3809 * PCH B stepping, previous chipset stepping should be
3810 * ignoring this setting.
3811 */
3812 if (HAS_PCH_SPLIT(dev)) {
3813 temp = I915_READ(PCH_DREF_CONTROL);
3814 /* Always enable nonspread source */
3815 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3816 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3817 temp &= ~DREF_SSC_SOURCE_MASK;
3818 temp |= DREF_SSC_SOURCE_ENABLE;
3819 I915_WRITE(PCH_DREF_CONTROL, temp);
3820
3821 POSTING_READ(PCH_DREF_CONTROL);
3822 udelay(200);
3823
3824 if (has_edp_encoder) {
3825 if (dev_priv->lvds_use_ssc) {
3826 temp |= DREF_SSC1_ENABLE;
3827 I915_WRITE(PCH_DREF_CONTROL, temp);
3828
3829 POSTING_READ(PCH_DREF_CONTROL);
3830 udelay(200);
3831 }
3832 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3833
3834 /* Enable CPU source on CPU attached eDP */
3835 if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
3836 if (dev_priv->lvds_use_ssc)
3837 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3838 else
3839 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3840 } else {
3841 /* Enable SSC on PCH eDP if needed */
3842 if (dev_priv->lvds_use_ssc) {
3843 DRM_ERROR("enabling SSC on PCH\n");
3844 temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
3845 }
3846 }
3847 I915_WRITE(PCH_DREF_CONTROL, temp);
3848 POSTING_READ(PCH_DREF_CONTROL);
3849 udelay(200);
3850 }
3851 }
3852
3853 if (IS_PINEVIEW(dev)) {
3854 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3855 if (has_reduced_clock)
3856 fp2 = (1 << reduced_clock.n) << 16 |
3857 reduced_clock.m1 << 8 | reduced_clock.m2;
3858 } else {
3859 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3860 if (has_reduced_clock)
3861 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3862 reduced_clock.m2;
3863 }
3864
3865 dpll = 0;
3866 if (!HAS_PCH_SPLIT(dev))
3867 dpll = DPLL_VGA_MODE_DIS;
3868
3869 if (!IS_GEN2(dev)) {
3870 if (is_lvds)
3871 dpll |= DPLLB_MODE_LVDS;
3872 else
3873 dpll |= DPLLB_MODE_DAC_SERIAL;
3874 if (is_sdvo) {
3875 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3876 if (pixel_multiplier > 1) {
3877 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3878 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3879 else if (HAS_PCH_SPLIT(dev))
3880 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3881 }
3882 dpll |= DPLL_DVO_HIGH_SPEED;
3883 }
3884 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
3885 dpll |= DPLL_DVO_HIGH_SPEED;
3886
3887 /* compute bitmask from p1 value */
3888 if (IS_PINEVIEW(dev))
3889 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3890 else {
3891 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3892 /* also FPA1 */
3893 if (HAS_PCH_SPLIT(dev))
3894 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3895 if (IS_G4X(dev) && has_reduced_clock)
3896 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3897 }
3898 switch (clock.p2) {
3899 case 5:
3900 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3901 break;
3902 case 7:
3903 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3904 break;
3905 case 10:
3906 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3907 break;
3908 case 14:
3909 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3910 break;
3911 }
3912 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
3913 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3914 } else {
3915 if (is_lvds) {
3916 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3917 } else {
3918 if (clock.p1 == 2)
3919 dpll |= PLL_P1_DIVIDE_BY_TWO;
3920 else
3921 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3922 if (clock.p2 == 4)
3923 dpll |= PLL_P2_DIVIDE_BY_4;
3924 }
3925 }
3926
3927 if (is_sdvo && is_tv)
3928 dpll |= PLL_REF_INPUT_TVCLKINBC;
3929 else if (is_tv)
3930 /* XXX: just matching BIOS for now */
3931 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3932 dpll |= 3;
3933 else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
3934 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3935 else
3936 dpll |= PLL_REF_INPUT_DREFCLK;
3937
3938 /* setup pipeconf */
3939 pipeconf = I915_READ(PIPECONF(pipe));
3940
3941 /* Set up the display plane register */
3942 dspcntr = DISPPLANE_GAMMA_ENABLE;
3943
3944 /* Ironlake's plane is forced to pipe, bit 24 is to
3945 enable color space conversion */
3946 if (!HAS_PCH_SPLIT(dev)) {
3947 if (pipe == 0)
3948 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3949 else
3950 dspcntr |= DISPPLANE_SEL_PIPE_B;
3951 }
3952
3953 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
3954 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3955 * core speed.
3956 *
3957 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3958 * pipe == 0 check?
3959 */
3960 if (mode->clock >
3961 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3962 pipeconf |= PIPECONF_DOUBLE_WIDE;
3963 else
3964 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
3965 }
3966
3967 dspcntr |= DISPLAY_PLANE_ENABLE;
3968 pipeconf |= PIPECONF_ENABLE;
3969 dpll |= DPLL_VCO_ENABLE;
3970
3971 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3972 drm_mode_debug_printmodeline(mode);
3973
3974 /* assign to Ironlake registers */
3975 if (HAS_PCH_SPLIT(dev)) {
3976 fp_reg = PCH_FP0(pipe);
3977 dpll_reg = PCH_DPLL(pipe);
3978 } else {
3979 fp_reg = FP0(pipe);
3980 dpll_reg = DPLL(pipe);
3981 }
3982
3983 /* PCH eDP needs FDI, but CPU eDP does not */
3984 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
3985 I915_WRITE(fp_reg, fp);
3986 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3987
3988 POSTING_READ(dpll_reg);
3989 udelay(150);
3990 }
3991
3992 /* enable transcoder DPLL */
3993 if (HAS_PCH_CPT(dev)) {
3994 temp = I915_READ(PCH_DPLL_SEL);
3995 if (pipe == 0)
3996 temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
3997 else
3998 temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
3999 I915_WRITE(PCH_DPLL_SEL, temp);
4000
4001 POSTING_READ(PCH_DPLL_SEL);
4002 udelay(150);
4003 }
4004
4005 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4006 * This is an exception to the general rule that mode_set doesn't turn
4007 * things on.
4008 */
4009 if (is_lvds) {
4010 reg = LVDS;
4011 if (HAS_PCH_SPLIT(dev))
4012 reg = PCH_LVDS;
4013
4014 temp = I915_READ(reg);
4015 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4016 if (pipe == 1) {
4017 if (HAS_PCH_CPT(dev))
4018 temp |= PORT_TRANS_B_SEL_CPT;
4019 else
4020 temp |= LVDS_PIPEB_SELECT;
4021 } else {
4022 if (HAS_PCH_CPT(dev))
4023 temp &= ~PORT_TRANS_SEL_MASK;
4024 else
4025 temp &= ~LVDS_PIPEB_SELECT;
4026 }
4027 /* set the corresponsding LVDS_BORDER bit */
4028 temp |= dev_priv->lvds_border_bits;
4029 /* Set the B0-B3 data pairs corresponding to whether we're going to
4030 * set the DPLLs for dual-channel mode or not.
4031 */
4032 if (clock.p2 == 7)
4033 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4034 else
4035 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4036
4037 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4038 * appropriately here, but we need to look more thoroughly into how
4039 * panels behave in the two modes.
4040 */
4041 /* set the dithering flag on non-PCH LVDS as needed */
4042 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
4043 if (dev_priv->lvds_dither)
4044 temp |= LVDS_ENABLE_DITHER;
4045 else
4046 temp &= ~LVDS_ENABLE_DITHER;
4047 }
4048 I915_WRITE(reg, temp);
4049 }
4050
4051 /* set the dithering flag and clear for anything other than a panel. */
4052 if (HAS_PCH_SPLIT(dev)) {
4053 pipeconf &= ~PIPECONF_DITHER_EN;
4054 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
4055 if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
4056 pipeconf |= PIPECONF_DITHER_EN;
4057 pipeconf |= PIPECONF_DITHER_TYPE_ST1;
4058 }
4059 }
4060
4061 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4062 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4063 } else if (HAS_PCH_SPLIT(dev)) {
4064 /* For non-DP output, clear any trans DP clock recovery setting.*/
4065 if (pipe == 0) {
4066 I915_WRITE(TRANSA_DATA_M1, 0);
4067 I915_WRITE(TRANSA_DATA_N1, 0);
4068 I915_WRITE(TRANSA_DP_LINK_M1, 0);
4069 I915_WRITE(TRANSA_DP_LINK_N1, 0);
4070 } else {
4071 I915_WRITE(TRANSB_DATA_M1, 0);
4072 I915_WRITE(TRANSB_DATA_N1, 0);
4073 I915_WRITE(TRANSB_DP_LINK_M1, 0);
4074 I915_WRITE(TRANSB_DP_LINK_N1, 0);
4075 }
4076 }
4077
4078 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4079 I915_WRITE(fp_reg, fp);
4080 I915_WRITE(dpll_reg, dpll);
4081
4082 /* Wait for the clocks to stabilize. */
4083 POSTING_READ(dpll_reg);
4084 udelay(150);
4085
4086 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
4087 temp = 0;
4088 if (is_sdvo) {
4089 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4090 if (temp > 1)
4091 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4092 else
4093 temp = 0;
4094 }
4095 I915_WRITE(DPLL_MD(pipe), temp);
4096 } else {
4097 /* write it again -- the BIOS does, after all */
4098 I915_WRITE(dpll_reg, dpll);
4099 }
4100
4101 /* Wait for the clocks to stabilize. */
4102 POSTING_READ(dpll_reg);
4103 udelay(150);
4104 }
4105
4106 intel_crtc->lowfreq_avail = false;
4107 if (is_lvds && has_reduced_clock && i915_powersave) {
4108 I915_WRITE(fp_reg + 4, fp2);
4109 intel_crtc->lowfreq_avail = true;
4110 if (HAS_PIPE_CXSR(dev)) {
4111 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4112 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4113 }
4114 } else {
4115 I915_WRITE(fp_reg + 4, fp);
4116 if (HAS_PIPE_CXSR(dev)) {
4117 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4118 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4119 }
4120 }
4121
4122 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4123 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4124 /* the chip adds 2 halflines automatically */
4125 adjusted_mode->crtc_vdisplay -= 1;
4126 adjusted_mode->crtc_vtotal -= 1;
4127 adjusted_mode->crtc_vblank_start -= 1;
4128 adjusted_mode->crtc_vblank_end -= 1;
4129 adjusted_mode->crtc_vsync_end -= 1;
4130 adjusted_mode->crtc_vsync_start -= 1;
4131 } else
4132 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4133
4134 I915_WRITE(HTOTAL(pipe),
4135 (adjusted_mode->crtc_hdisplay - 1) |
4136 ((adjusted_mode->crtc_htotal - 1) << 16));
4137 I915_WRITE(HBLANK(pipe),
4138 (adjusted_mode->crtc_hblank_start - 1) |
4139 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4140 I915_WRITE(HSYNC(pipe),
4141 (adjusted_mode->crtc_hsync_start - 1) |
4142 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4143
4144 I915_WRITE(VTOTAL(pipe),
4145 (adjusted_mode->crtc_vdisplay - 1) |
4146 ((adjusted_mode->crtc_vtotal - 1) << 16));
4147 I915_WRITE(VBLANK(pipe),
4148 (adjusted_mode->crtc_vblank_start - 1) |
4149 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4150 I915_WRITE(VSYNC(pipe),
4151 (adjusted_mode->crtc_vsync_start - 1) |
4152 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4153
4154 /* pipesrc and dspsize control the size that is scaled from,
4155 * which should always be the user's requested size.
4156 */
4157 if (!HAS_PCH_SPLIT(dev)) {
4158 I915_WRITE(DSPSIZE(plane),
4159 ((mode->vdisplay - 1) << 16) |
4160 (mode->hdisplay - 1));
4161 I915_WRITE(DSPPOS(plane), 0);
4162 }
4163 I915_WRITE(PIPESRC(pipe),
4164 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4165
4166 if (HAS_PCH_SPLIT(dev)) {
4167 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4168 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4169 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4170 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4171
4172 if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4173 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4174 }
4175 }
4176
4177 I915_WRITE(PIPECONF(pipe), pipeconf);
4178 POSTING_READ(PIPECONF(pipe));
4179
4180 intel_wait_for_vblank(dev, pipe);
4181
4182 if (IS_GEN5(dev)) {
4183 /* enable address swizzle for tiling buffer */
4184 temp = I915_READ(DISP_ARB_CTL);
4185 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
4186 }
4187
4188 I915_WRITE(DSPCNTR(plane), dspcntr);
4189
4190 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4191
4192 intel_update_watermarks(dev);
4193
4194 drm_vblank_post_modeset(dev, pipe);
4195
4196 return ret;
4197 }
4198
4199 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4200 void intel_crtc_load_lut(struct drm_crtc *crtc)
4201 {
4202 struct drm_device *dev = crtc->dev;
4203 struct drm_i915_private *dev_priv = dev->dev_private;
4204 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4205 int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
4206 int i;
4207
4208 /* The clocks have to be on to load the palette. */
4209 if (!crtc->enabled)
4210 return;
4211
4212 /* use legacy palette for Ironlake */
4213 if (HAS_PCH_SPLIT(dev))
4214 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
4215 LGC_PALETTE_B;
4216
4217 for (i = 0; i < 256; i++) {
4218 I915_WRITE(palreg + 4 * i,
4219 (intel_crtc->lut_r[i] << 16) |
4220 (intel_crtc->lut_g[i] << 8) |
4221 intel_crtc->lut_b[i]);
4222 }
4223 }
4224
4225 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4226 {
4227 struct drm_device *dev = crtc->dev;
4228 struct drm_i915_private *dev_priv = dev->dev_private;
4229 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4230 bool visible = base != 0;
4231 u32 cntl;
4232
4233 if (intel_crtc->cursor_visible == visible)
4234 return;
4235
4236 cntl = I915_READ(CURACNTR);
4237 if (visible) {
4238 /* On these chipsets we can only modify the base whilst
4239 * the cursor is disabled.
4240 */
4241 I915_WRITE(CURABASE, base);
4242
4243 cntl &= ~(CURSOR_FORMAT_MASK);
4244 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4245 cntl |= CURSOR_ENABLE |
4246 CURSOR_GAMMA_ENABLE |
4247 CURSOR_FORMAT_ARGB;
4248 } else
4249 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4250 I915_WRITE(CURACNTR, cntl);
4251
4252 intel_crtc->cursor_visible = visible;
4253 }
4254
4255 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4256 {
4257 struct drm_device *dev = crtc->dev;
4258 struct drm_i915_private *dev_priv = dev->dev_private;
4259 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4260 int pipe = intel_crtc->pipe;
4261 bool visible = base != 0;
4262
4263 if (intel_crtc->cursor_visible != visible) {
4264 uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
4265 if (base) {
4266 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4267 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4268 cntl |= pipe << 28; /* Connect to correct pipe */
4269 } else {
4270 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4271 cntl |= CURSOR_MODE_DISABLE;
4272 }
4273 I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
4274
4275 intel_crtc->cursor_visible = visible;
4276 }
4277 /* and commit changes on next vblank */
4278 I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
4279 }
4280
4281 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4282 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
4283 bool on)
4284 {
4285 struct drm_device *dev = crtc->dev;
4286 struct drm_i915_private *dev_priv = dev->dev_private;
4287 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4288 int pipe = intel_crtc->pipe;
4289 int x = intel_crtc->cursor_x;
4290 int y = intel_crtc->cursor_y;
4291 u32 base, pos;
4292 bool visible;
4293
4294 pos = 0;
4295
4296 if (on && crtc->enabled && crtc->fb) {
4297 base = intel_crtc->cursor_addr;
4298 if (x > (int) crtc->fb->width)
4299 base = 0;
4300
4301 if (y > (int) crtc->fb->height)
4302 base = 0;
4303 } else
4304 base = 0;
4305
4306 if (x < 0) {
4307 if (x + intel_crtc->cursor_width < 0)
4308 base = 0;
4309
4310 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4311 x = -x;
4312 }
4313 pos |= x << CURSOR_X_SHIFT;
4314
4315 if (y < 0) {
4316 if (y + intel_crtc->cursor_height < 0)
4317 base = 0;
4318
4319 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4320 y = -y;
4321 }
4322 pos |= y << CURSOR_Y_SHIFT;
4323
4324 visible = base != 0;
4325 if (!visible && !intel_crtc->cursor_visible)
4326 return;
4327
4328 I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
4329 if (IS_845G(dev) || IS_I865G(dev))
4330 i845_update_cursor(crtc, base);
4331 else
4332 i9xx_update_cursor(crtc, base);
4333
4334 if (visible)
4335 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
4336 }
4337
4338 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4339 struct drm_file *file_priv,
4340 uint32_t handle,
4341 uint32_t width, uint32_t height)
4342 {
4343 struct drm_device *dev = crtc->dev;
4344 struct drm_i915_private *dev_priv = dev->dev_private;
4345 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4346 struct drm_gem_object *bo;
4347 struct drm_i915_gem_object *obj_priv;
4348 uint32_t addr;
4349 int ret;
4350
4351 DRM_DEBUG_KMS("\n");
4352
4353 /* if we want to turn off the cursor ignore width and height */
4354 if (!handle) {
4355 DRM_DEBUG_KMS("cursor off\n");
4356 addr = 0;
4357 bo = NULL;
4358 mutex_lock(&dev->struct_mutex);
4359 goto finish;
4360 }
4361
4362 /* Currently we only support 64x64 cursors */
4363 if (width != 64 || height != 64) {
4364 DRM_ERROR("we currently only support 64x64 cursors\n");
4365 return -EINVAL;
4366 }
4367
4368 bo = drm_gem_object_lookup(dev, file_priv, handle);
4369 if (!bo)
4370 return -ENOENT;
4371
4372 obj_priv = to_intel_bo(bo);
4373
4374 if (bo->size < width * height * 4) {
4375 DRM_ERROR("buffer is to small\n");
4376 ret = -ENOMEM;
4377 goto fail;
4378 }
4379
4380 /* we only need to pin inside GTT if cursor is non-phy */
4381 mutex_lock(&dev->struct_mutex);
4382 if (!dev_priv->info->cursor_needs_physical) {
4383 ret = i915_gem_object_pin(bo, PAGE_SIZE);
4384 if (ret) {
4385 DRM_ERROR("failed to pin cursor bo\n");
4386 goto fail_locked;
4387 }
4388
4389 ret = i915_gem_object_set_to_gtt_domain(bo, 0);
4390 if (ret) {
4391 DRM_ERROR("failed to move cursor bo into the GTT\n");
4392 goto fail_unpin;
4393 }
4394
4395 addr = obj_priv->gtt_offset;
4396 } else {
4397 int align = IS_I830(dev) ? 16 * 1024 : 256;
4398 ret = i915_gem_attach_phys_object(dev, bo,
4399 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4400 align);
4401 if (ret) {
4402 DRM_ERROR("failed to attach phys object\n");
4403 goto fail_locked;
4404 }
4405 addr = obj_priv->phys_obj->handle->busaddr;
4406 }
4407
4408 if (IS_GEN2(dev))
4409 I915_WRITE(CURSIZE, (height << 12) | width);
4410
4411 finish:
4412 if (intel_crtc->cursor_bo) {
4413 if (dev_priv->info->cursor_needs_physical) {
4414 if (intel_crtc->cursor_bo != bo)
4415 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4416 } else
4417 i915_gem_object_unpin(intel_crtc->cursor_bo);
4418 drm_gem_object_unreference(intel_crtc->cursor_bo);
4419 }
4420
4421 mutex_unlock(&dev->struct_mutex);
4422
4423 intel_crtc->cursor_addr = addr;
4424 intel_crtc->cursor_bo = bo;
4425 intel_crtc->cursor_width = width;
4426 intel_crtc->cursor_height = height;
4427
4428 intel_crtc_update_cursor(crtc, true);
4429
4430 return 0;
4431 fail_unpin:
4432 i915_gem_object_unpin(bo);
4433 fail_locked:
4434 mutex_unlock(&dev->struct_mutex);
4435 fail:
4436 drm_gem_object_unreference_unlocked(bo);
4437 return ret;
4438 }
4439
4440 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4441 {
4442 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4443
4444 intel_crtc->cursor_x = x;
4445 intel_crtc->cursor_y = y;
4446
4447 intel_crtc_update_cursor(crtc, true);
4448
4449 return 0;
4450 }
4451
4452 /** Sets the color ramps on behalf of RandR */
4453 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4454 u16 blue, int regno)
4455 {
4456 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4457
4458 intel_crtc->lut_r[regno] = red >> 8;
4459 intel_crtc->lut_g[regno] = green >> 8;
4460 intel_crtc->lut_b[regno] = blue >> 8;
4461 }
4462
4463 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4464 u16 *blue, int regno)
4465 {
4466 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4467
4468 *red = intel_crtc->lut_r[regno] << 8;
4469 *green = intel_crtc->lut_g[regno] << 8;
4470 *blue = intel_crtc->lut_b[regno] << 8;
4471 }
4472
4473 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4474 u16 *blue, uint32_t start, uint32_t size)
4475 {
4476 int end = (start + size > 256) ? 256 : start + size, i;
4477 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4478
4479 for (i = start; i < end; i++) {
4480 intel_crtc->lut_r[i] = red[i] >> 8;
4481 intel_crtc->lut_g[i] = green[i] >> 8;
4482 intel_crtc->lut_b[i] = blue[i] >> 8;
4483 }
4484
4485 intel_crtc_load_lut(crtc);
4486 }
4487
4488 /**
4489 * Get a pipe with a simple mode set on it for doing load-based monitor
4490 * detection.
4491 *
4492 * It will be up to the load-detect code to adjust the pipe as appropriate for
4493 * its requirements. The pipe will be connected to no other encoders.
4494 *
4495 * Currently this code will only succeed if there is a pipe with no encoders
4496 * configured for it. In the future, it could choose to temporarily disable
4497 * some outputs to free up a pipe for its use.
4498 *
4499 * \return crtc, or NULL if no pipes are available.
4500 */
4501
4502 /* VESA 640x480x72Hz mode to set on the pipe */
4503 static struct drm_display_mode load_detect_mode = {
4504 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4505 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4506 };
4507
4508 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4509 struct drm_connector *connector,
4510 struct drm_display_mode *mode,
4511 int *dpms_mode)
4512 {
4513 struct intel_crtc *intel_crtc;
4514 struct drm_crtc *possible_crtc;
4515 struct drm_crtc *supported_crtc =NULL;
4516 struct drm_encoder *encoder = &intel_encoder->base;
4517 struct drm_crtc *crtc = NULL;
4518 struct drm_device *dev = encoder->dev;
4519 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4520 struct drm_crtc_helper_funcs *crtc_funcs;
4521 int i = -1;
4522
4523 /*
4524 * Algorithm gets a little messy:
4525 * - if the connector already has an assigned crtc, use it (but make
4526 * sure it's on first)
4527 * - try to find the first unused crtc that can drive this connector,
4528 * and use that if we find one
4529 * - if there are no unused crtcs available, try to use the first
4530 * one we found that supports the connector
4531 */
4532
4533 /* See if we already have a CRTC for this connector */
4534 if (encoder->crtc) {
4535 crtc = encoder->crtc;
4536 /* Make sure the crtc and connector are running */
4537 intel_crtc = to_intel_crtc(crtc);
4538 *dpms_mode = intel_crtc->dpms_mode;
4539 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4540 crtc_funcs = crtc->helper_private;
4541 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4542 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4543 }
4544 return crtc;
4545 }
4546
4547 /* Find an unused one (if possible) */
4548 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4549 i++;
4550 if (!(encoder->possible_crtcs & (1 << i)))
4551 continue;
4552 if (!possible_crtc->enabled) {
4553 crtc = possible_crtc;
4554 break;
4555 }
4556 if (!supported_crtc)
4557 supported_crtc = possible_crtc;
4558 }
4559
4560 /*
4561 * If we didn't find an unused CRTC, don't use any.
4562 */
4563 if (!crtc) {
4564 return NULL;
4565 }
4566
4567 encoder->crtc = crtc;
4568 connector->encoder = encoder;
4569 intel_encoder->load_detect_temp = true;
4570
4571 intel_crtc = to_intel_crtc(crtc);
4572 *dpms_mode = intel_crtc->dpms_mode;
4573
4574 if (!crtc->enabled) {
4575 if (!mode)
4576 mode = &load_detect_mode;
4577 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
4578 } else {
4579 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4580 crtc_funcs = crtc->helper_private;
4581 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4582 }
4583
4584 /* Add this connector to the crtc */
4585 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4586 encoder_funcs->commit(encoder);
4587 }
4588 /* let the connector get through one full cycle before testing */
4589 intel_wait_for_vblank(dev, intel_crtc->pipe);
4590
4591 return crtc;
4592 }
4593
4594 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4595 struct drm_connector *connector, int dpms_mode)
4596 {
4597 struct drm_encoder *encoder = &intel_encoder->base;
4598 struct drm_device *dev = encoder->dev;
4599 struct drm_crtc *crtc = encoder->crtc;
4600 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4601 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4602
4603 if (intel_encoder->load_detect_temp) {
4604 encoder->crtc = NULL;
4605 connector->encoder = NULL;
4606 intel_encoder->load_detect_temp = false;
4607 crtc->enabled = drm_helper_crtc_in_use(crtc);
4608 drm_helper_disable_unused_functions(dev);
4609 }
4610
4611 /* Switch crtc and encoder back off if necessary */
4612 if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4613 if (encoder->crtc == crtc)
4614 encoder_funcs->dpms(encoder, dpms_mode);
4615 crtc_funcs->dpms(crtc, dpms_mode);
4616 }
4617 }
4618
4619 /* Returns the clock of the currently programmed mode of the given pipe. */
4620 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4621 {
4622 struct drm_i915_private *dev_priv = dev->dev_private;
4623 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4624 int pipe = intel_crtc->pipe;
4625 u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4626 u32 fp;
4627 intel_clock_t clock;
4628
4629 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4630 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4631 else
4632 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4633
4634 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4635 if (IS_PINEVIEW(dev)) {
4636 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4637 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4638 } else {
4639 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4640 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4641 }
4642
4643 if (!IS_GEN2(dev)) {
4644 if (IS_PINEVIEW(dev))
4645 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4646 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4647 else
4648 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4649 DPLL_FPA01_P1_POST_DIV_SHIFT);
4650
4651 switch (dpll & DPLL_MODE_MASK) {
4652 case DPLLB_MODE_DAC_SERIAL:
4653 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4654 5 : 10;
4655 break;
4656 case DPLLB_MODE_LVDS:
4657 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4658 7 : 14;
4659 break;
4660 default:
4661 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4662 "mode\n", (int)(dpll & DPLL_MODE_MASK));
4663 return 0;
4664 }
4665
4666 /* XXX: Handle the 100Mhz refclk */
4667 intel_clock(dev, 96000, &clock);
4668 } else {
4669 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4670
4671 if (is_lvds) {
4672 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4673 DPLL_FPA01_P1_POST_DIV_SHIFT);
4674 clock.p2 = 14;
4675
4676 if ((dpll & PLL_REF_INPUT_MASK) ==
4677 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4678 /* XXX: might not be 66MHz */
4679 intel_clock(dev, 66000, &clock);
4680 } else
4681 intel_clock(dev, 48000, &clock);
4682 } else {
4683 if (dpll & PLL_P1_DIVIDE_BY_TWO)
4684 clock.p1 = 2;
4685 else {
4686 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4687 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4688 }
4689 if (dpll & PLL_P2_DIVIDE_BY_4)
4690 clock.p2 = 4;
4691 else
4692 clock.p2 = 2;
4693
4694 intel_clock(dev, 48000, &clock);
4695 }
4696 }
4697
4698 /* XXX: It would be nice to validate the clocks, but we can't reuse
4699 * i830PllIsValid() because it relies on the xf86_config connector
4700 * configuration being accurate, which it isn't necessarily.
4701 */
4702
4703 return clock.dot;
4704 }
4705
4706 /** Returns the currently programmed mode of the given pipe. */
4707 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4708 struct drm_crtc *crtc)
4709 {
4710 struct drm_i915_private *dev_priv = dev->dev_private;
4711 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4712 int pipe = intel_crtc->pipe;
4713 struct drm_display_mode *mode;
4714 int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
4715 int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
4716 int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
4717 int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
4718
4719 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4720 if (!mode)
4721 return NULL;
4722
4723 mode->clock = intel_crtc_clock_get(dev, crtc);
4724 mode->hdisplay = (htot & 0xffff) + 1;
4725 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
4726 mode->hsync_start = (hsync & 0xffff) + 1;
4727 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
4728 mode->vdisplay = (vtot & 0xffff) + 1;
4729 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
4730 mode->vsync_start = (vsync & 0xffff) + 1;
4731 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
4732
4733 drm_mode_set_name(mode);
4734 drm_mode_set_crtcinfo(mode, 0);
4735
4736 return mode;
4737 }
4738
4739 #define GPU_IDLE_TIMEOUT 500 /* ms */
4740
4741 /* When this timer fires, we've been idle for awhile */
4742 static void intel_gpu_idle_timer(unsigned long arg)
4743 {
4744 struct drm_device *dev = (struct drm_device *)arg;
4745 drm_i915_private_t *dev_priv = dev->dev_private;
4746
4747 dev_priv->busy = false;
4748
4749 queue_work(dev_priv->wq, &dev_priv->idle_work);
4750 }
4751
4752 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4753
4754 static void intel_crtc_idle_timer(unsigned long arg)
4755 {
4756 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
4757 struct drm_crtc *crtc = &intel_crtc->base;
4758 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
4759
4760 intel_crtc->busy = false;
4761
4762 queue_work(dev_priv->wq, &dev_priv->idle_work);
4763 }
4764
4765 static void intel_increase_pllclock(struct drm_crtc *crtc)
4766 {
4767 struct drm_device *dev = crtc->dev;
4768 drm_i915_private_t *dev_priv = dev->dev_private;
4769 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4770 int pipe = intel_crtc->pipe;
4771 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4772 int dpll = I915_READ(dpll_reg);
4773
4774 if (HAS_PCH_SPLIT(dev))
4775 return;
4776
4777 if (!dev_priv->lvds_downclock_avail)
4778 return;
4779
4780 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
4781 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4782
4783 /* Unlock panel regs */
4784 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4785 PANEL_UNLOCK_REGS);
4786
4787 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4788 I915_WRITE(dpll_reg, dpll);
4789 dpll = I915_READ(dpll_reg);
4790 intel_wait_for_vblank(dev, pipe);
4791 dpll = I915_READ(dpll_reg);
4792 if (dpll & DISPLAY_RATE_SELECT_FPA1)
4793 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4794
4795 /* ...and lock them again */
4796 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4797 }
4798
4799 /* Schedule downclock */
4800 mod_timer(&intel_crtc->idle_timer, jiffies +
4801 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4802 }
4803
4804 static void intel_decrease_pllclock(struct drm_crtc *crtc)
4805 {
4806 struct drm_device *dev = crtc->dev;
4807 drm_i915_private_t *dev_priv = dev->dev_private;
4808 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4809 int pipe = intel_crtc->pipe;
4810 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4811 int dpll = I915_READ(dpll_reg);
4812
4813 if (HAS_PCH_SPLIT(dev))
4814 return;
4815
4816 if (!dev_priv->lvds_downclock_avail)
4817 return;
4818
4819 /*
4820 * Since this is called by a timer, we should never get here in
4821 * the manual case.
4822 */
4823 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
4824 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4825
4826 /* Unlock panel regs */
4827 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4828 PANEL_UNLOCK_REGS);
4829
4830 dpll |= DISPLAY_RATE_SELECT_FPA1;
4831 I915_WRITE(dpll_reg, dpll);
4832 dpll = I915_READ(dpll_reg);
4833 intel_wait_for_vblank(dev, pipe);
4834 dpll = I915_READ(dpll_reg);
4835 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4836 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4837
4838 /* ...and lock them again */
4839 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4840 }
4841
4842 }
4843
4844 /**
4845 * intel_idle_update - adjust clocks for idleness
4846 * @work: work struct
4847 *
4848 * Either the GPU or display (or both) went idle. Check the busy status
4849 * here and adjust the CRTC and GPU clocks as necessary.
4850 */
4851 static void intel_idle_update(struct work_struct *work)
4852 {
4853 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4854 idle_work);
4855 struct drm_device *dev = dev_priv->dev;
4856 struct drm_crtc *crtc;
4857 struct intel_crtc *intel_crtc;
4858 int enabled = 0;
4859
4860 if (!i915_powersave)
4861 return;
4862
4863 mutex_lock(&dev->struct_mutex);
4864
4865 i915_update_gfx_val(dev_priv);
4866
4867 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4868 /* Skip inactive CRTCs */
4869 if (!crtc->fb)
4870 continue;
4871
4872 enabled++;
4873 intel_crtc = to_intel_crtc(crtc);
4874 if (!intel_crtc->busy)
4875 intel_decrease_pllclock(crtc);
4876 }
4877
4878 if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
4879 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4880 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4881 }
4882
4883 mutex_unlock(&dev->struct_mutex);
4884 }
4885
4886 /**
4887 * intel_mark_busy - mark the GPU and possibly the display busy
4888 * @dev: drm device
4889 * @obj: object we're operating on
4890 *
4891 * Callers can use this function to indicate that the GPU is busy processing
4892 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
4893 * buffer), we'll also mark the display as busy, so we know to increase its
4894 * clock frequency.
4895 */
4896 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4897 {
4898 drm_i915_private_t *dev_priv = dev->dev_private;
4899 struct drm_crtc *crtc = NULL;
4900 struct intel_framebuffer *intel_fb;
4901 struct intel_crtc *intel_crtc;
4902
4903 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4904 return;
4905
4906 if (!dev_priv->busy) {
4907 if (IS_I945G(dev) || IS_I945GM(dev)) {
4908 u32 fw_blc_self;
4909
4910 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4911 fw_blc_self = I915_READ(FW_BLC_SELF);
4912 fw_blc_self &= ~FW_BLC_SELF_EN;
4913 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4914 }
4915 dev_priv->busy = true;
4916 } else
4917 mod_timer(&dev_priv->idle_timer, jiffies +
4918 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4919
4920 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4921 if (!crtc->fb)
4922 continue;
4923
4924 intel_crtc = to_intel_crtc(crtc);
4925 intel_fb = to_intel_framebuffer(crtc->fb);
4926 if (intel_fb->obj == obj) {
4927 if (!intel_crtc->busy) {
4928 if (IS_I945G(dev) || IS_I945GM(dev)) {
4929 u32 fw_blc_self;
4930
4931 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4932 fw_blc_self = I915_READ(FW_BLC_SELF);
4933 fw_blc_self &= ~FW_BLC_SELF_EN;
4934 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4935 }
4936 /* Non-busy -> busy, upclock */
4937 intel_increase_pllclock(crtc);
4938 intel_crtc->busy = true;
4939 } else {
4940 /* Busy -> busy, put off timer */
4941 mod_timer(&intel_crtc->idle_timer, jiffies +
4942 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4943 }
4944 }
4945 }
4946 }
4947
4948 static void intel_crtc_destroy(struct drm_crtc *crtc)
4949 {
4950 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4951 struct drm_device *dev = crtc->dev;
4952 struct intel_unpin_work *work;
4953 unsigned long flags;
4954
4955 spin_lock_irqsave(&dev->event_lock, flags);
4956 work = intel_crtc->unpin_work;
4957 intel_crtc->unpin_work = NULL;
4958 spin_unlock_irqrestore(&dev->event_lock, flags);
4959
4960 if (work) {
4961 cancel_work_sync(&work->work);
4962 kfree(work);
4963 }
4964
4965 drm_crtc_cleanup(crtc);
4966
4967 kfree(intel_crtc);
4968 }
4969
4970 static void intel_unpin_work_fn(struct work_struct *__work)
4971 {
4972 struct intel_unpin_work *work =
4973 container_of(__work, struct intel_unpin_work, work);
4974
4975 mutex_lock(&work->dev->struct_mutex);
4976 i915_gem_object_unpin(work->old_fb_obj);
4977 drm_gem_object_unreference(work->pending_flip_obj);
4978 drm_gem_object_unreference(work->old_fb_obj);
4979 mutex_unlock(&work->dev->struct_mutex);
4980 kfree(work);
4981 }
4982
4983 static void do_intel_finish_page_flip(struct drm_device *dev,
4984 struct drm_crtc *crtc)
4985 {
4986 drm_i915_private_t *dev_priv = dev->dev_private;
4987 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4988 struct intel_unpin_work *work;
4989 struct drm_i915_gem_object *obj_priv;
4990 struct drm_pending_vblank_event *e;
4991 struct timeval now;
4992 unsigned long flags;
4993
4994 /* Ignore early vblank irqs */
4995 if (intel_crtc == NULL)
4996 return;
4997
4998 spin_lock_irqsave(&dev->event_lock, flags);
4999 work = intel_crtc->unpin_work;
5000 if (work == NULL || !work->pending) {
5001 spin_unlock_irqrestore(&dev->event_lock, flags);
5002 return;
5003 }
5004
5005 intel_crtc->unpin_work = NULL;
5006 drm_vblank_put(dev, intel_crtc->pipe);
5007
5008 if (work->event) {
5009 e = work->event;
5010 do_gettimeofday(&now);
5011 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
5012 e->event.tv_sec = now.tv_sec;
5013 e->event.tv_usec = now.tv_usec;
5014 list_add_tail(&e->base.link,
5015 &e->base.file_priv->event_list);
5016 wake_up_interruptible(&e->base.file_priv->event_wait);
5017 }
5018
5019 spin_unlock_irqrestore(&dev->event_lock, flags);
5020
5021 obj_priv = to_intel_bo(work->old_fb_obj);
5022 atomic_clear_mask(1 << intel_crtc->plane,
5023 &obj_priv->pending_flip.counter);
5024 if (atomic_read(&obj_priv->pending_flip) == 0)
5025 wake_up(&dev_priv->pending_flip_queue);
5026 schedule_work(&work->work);
5027
5028 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
5029 }
5030
5031 void intel_finish_page_flip(struct drm_device *dev, int pipe)
5032 {
5033 drm_i915_private_t *dev_priv = dev->dev_private;
5034 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
5035
5036 do_intel_finish_page_flip(dev, crtc);
5037 }
5038
5039 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5040 {
5041 drm_i915_private_t *dev_priv = dev->dev_private;
5042 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5043
5044 do_intel_finish_page_flip(dev, crtc);
5045 }
5046
5047 void intel_prepare_page_flip(struct drm_device *dev, int plane)
5048 {
5049 drm_i915_private_t *dev_priv = dev->dev_private;
5050 struct intel_crtc *intel_crtc =
5051 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5052 unsigned long flags;
5053
5054 spin_lock_irqsave(&dev->event_lock, flags);
5055 if (intel_crtc->unpin_work) {
5056 if ((++intel_crtc->unpin_work->pending) > 1)
5057 DRM_ERROR("Prepared flip multiple times\n");
5058 } else {
5059 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5060 }
5061 spin_unlock_irqrestore(&dev->event_lock, flags);
5062 }
5063
5064 static int intel_crtc_page_flip(struct drm_crtc *crtc,
5065 struct drm_framebuffer *fb,
5066 struct drm_pending_vblank_event *event)
5067 {
5068 struct drm_device *dev = crtc->dev;
5069 struct drm_i915_private *dev_priv = dev->dev_private;
5070 struct intel_framebuffer *intel_fb;
5071 struct drm_i915_gem_object *obj_priv;
5072 struct drm_gem_object *obj;
5073 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5074 struct intel_unpin_work *work;
5075 unsigned long flags, offset;
5076 int pipe = intel_crtc->pipe;
5077 u32 pf, pipesrc;
5078 int ret;
5079
5080 work = kzalloc(sizeof *work, GFP_KERNEL);
5081 if (work == NULL)
5082 return -ENOMEM;
5083
5084 work->event = event;
5085 work->dev = crtc->dev;
5086 intel_fb = to_intel_framebuffer(crtc->fb);
5087 work->old_fb_obj = intel_fb->obj;
5088 INIT_WORK(&work->work, intel_unpin_work_fn);
5089
5090 /* We borrow the event spin lock for protecting unpin_work */
5091 spin_lock_irqsave(&dev->event_lock, flags);
5092 if (intel_crtc->unpin_work) {
5093 spin_unlock_irqrestore(&dev->event_lock, flags);
5094 kfree(work);
5095
5096 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5097 return -EBUSY;
5098 }
5099 intel_crtc->unpin_work = work;
5100 spin_unlock_irqrestore(&dev->event_lock, flags);
5101
5102 intel_fb = to_intel_framebuffer(fb);
5103 obj = intel_fb->obj;
5104
5105 mutex_lock(&dev->struct_mutex);
5106 ret = intel_pin_and_fence_fb_obj(dev, obj, true);
5107 if (ret)
5108 goto cleanup_work;
5109
5110 /* Reference the objects for the scheduled work. */
5111 drm_gem_object_reference(work->old_fb_obj);
5112 drm_gem_object_reference(obj);
5113
5114 crtc->fb = fb;
5115
5116 ret = drm_vblank_get(dev, intel_crtc->pipe);
5117 if (ret)
5118 goto cleanup_objs;
5119
5120 /* Block clients from rendering to the new back buffer until
5121 * the flip occurs and the object is no longer visible.
5122 */
5123 atomic_add(1 << intel_crtc->plane,
5124 &to_intel_bo(work->old_fb_obj)->pending_flip);
5125
5126 work->pending_flip_obj = obj;
5127 obj_priv = to_intel_bo(obj);
5128
5129 if (IS_GEN3(dev) || IS_GEN2(dev)) {
5130 u32 flip_mask;
5131
5132 /* Can't queue multiple flips, so wait for the previous
5133 * one to finish before executing the next.
5134 */
5135 BEGIN_LP_RING(2);
5136 if (intel_crtc->plane)
5137 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5138 else
5139 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5140 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5141 OUT_RING(MI_NOOP);
5142 ADVANCE_LP_RING();
5143 }
5144
5145 work->enable_stall_check = true;
5146
5147 /* Offset into the new buffer for cases of shared fbs between CRTCs */
5148 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
5149
5150 BEGIN_LP_RING(4);
5151 switch(INTEL_INFO(dev)->gen) {
5152 case 2:
5153 OUT_RING(MI_DISPLAY_FLIP |
5154 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5155 OUT_RING(fb->pitch);
5156 OUT_RING(obj_priv->gtt_offset + offset);
5157 OUT_RING(MI_NOOP);
5158 break;
5159
5160 case 3:
5161 OUT_RING(MI_DISPLAY_FLIP_I915 |
5162 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5163 OUT_RING(fb->pitch);
5164 OUT_RING(obj_priv->gtt_offset + offset);
5165 OUT_RING(MI_NOOP);
5166 break;
5167
5168 case 4:
5169 case 5:
5170 /* i965+ uses the linear or tiled offsets from the
5171 * Display Registers (which do not change across a page-flip)
5172 * so we need only reprogram the base address.
5173 */
5174 OUT_RING(MI_DISPLAY_FLIP |
5175 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5176 OUT_RING(fb->pitch);
5177 OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
5178
5179 /* XXX Enabling the panel-fitter across page-flip is so far
5180 * untested on non-native modes, so ignore it for now.
5181 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5182 */
5183 pf = 0;
5184 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5185 OUT_RING(pf | pipesrc);
5186 break;
5187
5188 case 6:
5189 OUT_RING(MI_DISPLAY_FLIP |
5190 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5191 OUT_RING(fb->pitch | obj_priv->tiling_mode);
5192 OUT_RING(obj_priv->gtt_offset);
5193
5194 pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5195 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5196 OUT_RING(pf | pipesrc);
5197 break;
5198 }
5199 ADVANCE_LP_RING();
5200
5201 mutex_unlock(&dev->struct_mutex);
5202
5203 trace_i915_flip_request(intel_crtc->plane, obj);
5204
5205 return 0;
5206
5207 cleanup_objs:
5208 drm_gem_object_unreference(work->old_fb_obj);
5209 drm_gem_object_unreference(obj);
5210 cleanup_work:
5211 mutex_unlock(&dev->struct_mutex);
5212
5213 spin_lock_irqsave(&dev->event_lock, flags);
5214 intel_crtc->unpin_work = NULL;
5215 spin_unlock_irqrestore(&dev->event_lock, flags);
5216
5217 kfree(work);
5218
5219 return ret;
5220 }
5221
5222 static struct drm_crtc_helper_funcs intel_helper_funcs = {
5223 .dpms = intel_crtc_dpms,
5224 .mode_fixup = intel_crtc_mode_fixup,
5225 .mode_set = intel_crtc_mode_set,
5226 .mode_set_base = intel_pipe_set_base,
5227 .mode_set_base_atomic = intel_pipe_set_base_atomic,
5228 .load_lut = intel_crtc_load_lut,
5229 .disable = intel_crtc_disable,
5230 };
5231
5232 static const struct drm_crtc_funcs intel_crtc_funcs = {
5233 .cursor_set = intel_crtc_cursor_set,
5234 .cursor_move = intel_crtc_cursor_move,
5235 .gamma_set = intel_crtc_gamma_set,
5236 .set_config = drm_crtc_helper_set_config,
5237 .destroy = intel_crtc_destroy,
5238 .page_flip = intel_crtc_page_flip,
5239 };
5240
5241 static void intel_sanitize_modesetting(struct drm_device *dev,
5242 int pipe, int plane)
5243 {
5244 struct drm_i915_private *dev_priv = dev->dev_private;
5245 u32 reg, val;
5246
5247 if (HAS_PCH_SPLIT(dev))
5248 return;
5249
5250 /* Who knows what state these registers were left in by the BIOS or
5251 * grub?
5252 *
5253 * If we leave the registers in a conflicting state (e.g. with the
5254 * display plane reading from the other pipe than the one we intend
5255 * to use) then when we attempt to teardown the active mode, we will
5256 * not disable the pipes and planes in the correct order -- leaving
5257 * a plane reading from a disabled pipe and possibly leading to
5258 * undefined behaviour.
5259 */
5260
5261 reg = DSPCNTR(plane);
5262 val = I915_READ(reg);
5263
5264 if ((val & DISPLAY_PLANE_ENABLE) == 0)
5265 return;
5266 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
5267 return;
5268
5269 /* This display plane is active and attached to the other CPU pipe. */
5270 pipe = !pipe;
5271
5272 /* Disable the plane and wait for it to stop reading from the pipe. */
5273 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
5274 intel_flush_display_plane(dev, plane);
5275
5276 if (IS_GEN2(dev))
5277 intel_wait_for_vblank(dev, pipe);
5278
5279 if (pipe == 0 && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
5280 return;
5281
5282 /* Switch off the pipe. */
5283 reg = PIPECONF(pipe);
5284 val = I915_READ(reg);
5285 if (val & PIPECONF_ENABLE) {
5286 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
5287 intel_wait_for_pipe_off(dev, pipe);
5288 }
5289 }
5290
5291 static void intel_crtc_init(struct drm_device *dev, int pipe)
5292 {
5293 drm_i915_private_t *dev_priv = dev->dev_private;
5294 struct intel_crtc *intel_crtc;
5295 int i;
5296
5297 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
5298 if (intel_crtc == NULL)
5299 return;
5300
5301 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
5302
5303 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
5304 for (i = 0; i < 256; i++) {
5305 intel_crtc->lut_r[i] = i;
5306 intel_crtc->lut_g[i] = i;
5307 intel_crtc->lut_b[i] = i;
5308 }
5309
5310 /* Swap pipes & planes for FBC on pre-965 */
5311 intel_crtc->pipe = pipe;
5312 intel_crtc->plane = pipe;
5313 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
5314 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
5315 intel_crtc->plane = !pipe;
5316 }
5317
5318 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
5319 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
5320 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
5321 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
5322
5323 intel_crtc->cursor_addr = 0;
5324 intel_crtc->dpms_mode = -1;
5325 intel_crtc->active = true; /* force the pipe off on setup_init_config */
5326
5327 if (HAS_PCH_SPLIT(dev)) {
5328 intel_helper_funcs.prepare = ironlake_crtc_prepare;
5329 intel_helper_funcs.commit = ironlake_crtc_commit;
5330 } else {
5331 intel_helper_funcs.prepare = i9xx_crtc_prepare;
5332 intel_helper_funcs.commit = i9xx_crtc_commit;
5333 }
5334
5335 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5336
5337 intel_crtc->busy = false;
5338
5339 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
5340 (unsigned long)intel_crtc);
5341
5342 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
5343 }
5344
5345 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
5346 struct drm_file *file_priv)
5347 {
5348 drm_i915_private_t *dev_priv = dev->dev_private;
5349 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
5350 struct drm_mode_object *drmmode_obj;
5351 struct intel_crtc *crtc;
5352
5353 if (!dev_priv) {
5354 DRM_ERROR("called with no initialization\n");
5355 return -EINVAL;
5356 }
5357
5358 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
5359 DRM_MODE_OBJECT_CRTC);
5360
5361 if (!drmmode_obj) {
5362 DRM_ERROR("no such CRTC id\n");
5363 return -EINVAL;
5364 }
5365
5366 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
5367 pipe_from_crtc_id->pipe = crtc->pipe;
5368
5369 return 0;
5370 }
5371
5372 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
5373 {
5374 struct intel_encoder *encoder;
5375 int index_mask = 0;
5376 int entry = 0;
5377
5378 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
5379 if (type_mask & encoder->clone_mask)
5380 index_mask |= (1 << entry);
5381 entry++;
5382 }
5383
5384 return index_mask;
5385 }
5386
5387 static void intel_setup_outputs(struct drm_device *dev)
5388 {
5389 struct drm_i915_private *dev_priv = dev->dev_private;
5390 struct intel_encoder *encoder;
5391 bool dpd_is_edp = false;
5392 bool has_lvds = false;
5393
5394 if (IS_MOBILE(dev) && !IS_I830(dev))
5395 has_lvds = intel_lvds_init(dev);
5396 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
5397 /* disable the panel fitter on everything but LVDS */
5398 I915_WRITE(PFIT_CONTROL, 0);
5399 }
5400
5401 if (HAS_PCH_SPLIT(dev)) {
5402 dpd_is_edp = intel_dpd_is_edp(dev);
5403
5404 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
5405 intel_dp_init(dev, DP_A);
5406
5407 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5408 intel_dp_init(dev, PCH_DP_D);
5409 }
5410
5411 intel_crt_init(dev);
5412
5413 if (HAS_PCH_SPLIT(dev)) {
5414 int found;
5415
5416 if (I915_READ(HDMIB) & PORT_DETECTED) {
5417 /* PCH SDVOB multiplex with HDMIB */
5418 found = intel_sdvo_init(dev, PCH_SDVOB);
5419 if (!found)
5420 intel_hdmi_init(dev, HDMIB);
5421 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
5422 intel_dp_init(dev, PCH_DP_B);
5423 }
5424
5425 if (I915_READ(HDMIC) & PORT_DETECTED)
5426 intel_hdmi_init(dev, HDMIC);
5427
5428 if (I915_READ(HDMID) & PORT_DETECTED)
5429 intel_hdmi_init(dev, HDMID);
5430
5431 if (I915_READ(PCH_DP_C) & DP_DETECTED)
5432 intel_dp_init(dev, PCH_DP_C);
5433
5434 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5435 intel_dp_init(dev, PCH_DP_D);
5436
5437 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
5438 bool found = false;
5439
5440 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5441 DRM_DEBUG_KMS("probing SDVOB\n");
5442 found = intel_sdvo_init(dev, SDVOB);
5443 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
5444 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
5445 intel_hdmi_init(dev, SDVOB);
5446 }
5447
5448 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
5449 DRM_DEBUG_KMS("probing DP_B\n");
5450 intel_dp_init(dev, DP_B);
5451 }
5452 }
5453
5454 /* Before G4X SDVOC doesn't have its own detect register */
5455
5456 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5457 DRM_DEBUG_KMS("probing SDVOC\n");
5458 found = intel_sdvo_init(dev, SDVOC);
5459 }
5460
5461 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
5462
5463 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
5464 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
5465 intel_hdmi_init(dev, SDVOC);
5466 }
5467 if (SUPPORTS_INTEGRATED_DP(dev)) {
5468 DRM_DEBUG_KMS("probing DP_C\n");
5469 intel_dp_init(dev, DP_C);
5470 }
5471 }
5472
5473 if (SUPPORTS_INTEGRATED_DP(dev) &&
5474 (I915_READ(DP_D) & DP_DETECTED)) {
5475 DRM_DEBUG_KMS("probing DP_D\n");
5476 intel_dp_init(dev, DP_D);
5477 }
5478 } else if (IS_GEN2(dev))
5479 intel_dvo_init(dev);
5480
5481 if (SUPPORTS_TV(dev))
5482 intel_tv_init(dev);
5483
5484 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
5485 encoder->base.possible_crtcs = encoder->crtc_mask;
5486 encoder->base.possible_clones =
5487 intel_encoder_clones(dev, encoder->clone_mask);
5488 }
5489 }
5490
5491 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
5492 {
5493 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5494
5495 drm_framebuffer_cleanup(fb);
5496 drm_gem_object_unreference_unlocked(intel_fb->obj);
5497
5498 kfree(intel_fb);
5499 }
5500
5501 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
5502 struct drm_file *file_priv,
5503 unsigned int *handle)
5504 {
5505 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5506 struct drm_gem_object *object = intel_fb->obj;
5507
5508 return drm_gem_handle_create(file_priv, object, handle);
5509 }
5510
5511 static const struct drm_framebuffer_funcs intel_fb_funcs = {
5512 .destroy = intel_user_framebuffer_destroy,
5513 .create_handle = intel_user_framebuffer_create_handle,
5514 };
5515
5516 int intel_framebuffer_init(struct drm_device *dev,
5517 struct intel_framebuffer *intel_fb,
5518 struct drm_mode_fb_cmd *mode_cmd,
5519 struct drm_gem_object *obj)
5520 {
5521 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
5522 int ret;
5523
5524 if (obj_priv->tiling_mode == I915_TILING_Y)
5525 return -EINVAL;
5526
5527 if (mode_cmd->pitch & 63)
5528 return -EINVAL;
5529
5530 switch (mode_cmd->bpp) {
5531 case 8:
5532 case 16:
5533 case 24:
5534 case 32:
5535 break;
5536 default:
5537 return -EINVAL;
5538 }
5539
5540 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
5541 if (ret) {
5542 DRM_ERROR("framebuffer init failed %d\n", ret);
5543 return ret;
5544 }
5545
5546 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
5547 intel_fb->obj = obj;
5548 return 0;
5549 }
5550
5551 static struct drm_framebuffer *
5552 intel_user_framebuffer_create(struct drm_device *dev,
5553 struct drm_file *filp,
5554 struct drm_mode_fb_cmd *mode_cmd)
5555 {
5556 struct drm_gem_object *obj;
5557 struct intel_framebuffer *intel_fb;
5558 int ret;
5559
5560 obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
5561 if (!obj)
5562 return ERR_PTR(-ENOENT);
5563
5564 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5565 if (!intel_fb)
5566 return ERR_PTR(-ENOMEM);
5567
5568 ret = intel_framebuffer_init(dev, intel_fb,
5569 mode_cmd, obj);
5570 if (ret) {
5571 drm_gem_object_unreference_unlocked(obj);
5572 kfree(intel_fb);
5573 return ERR_PTR(ret);
5574 }
5575
5576 return &intel_fb->base;
5577 }
5578
5579 static const struct drm_mode_config_funcs intel_mode_funcs = {
5580 .fb_create = intel_user_framebuffer_create,
5581 .output_poll_changed = intel_fb_output_poll_changed,
5582 };
5583
5584 static struct drm_gem_object *
5585 intel_alloc_context_page(struct drm_device *dev)
5586 {
5587 struct drm_gem_object *ctx;
5588 int ret;
5589
5590 ctx = i915_gem_alloc_object(dev, 4096);
5591 if (!ctx) {
5592 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5593 return NULL;
5594 }
5595
5596 mutex_lock(&dev->struct_mutex);
5597 ret = i915_gem_object_pin(ctx, 4096);
5598 if (ret) {
5599 DRM_ERROR("failed to pin power context: %d\n", ret);
5600 goto err_unref;
5601 }
5602
5603 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
5604 if (ret) {
5605 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5606 goto err_unpin;
5607 }
5608 mutex_unlock(&dev->struct_mutex);
5609
5610 return ctx;
5611
5612 err_unpin:
5613 i915_gem_object_unpin(ctx);
5614 err_unref:
5615 drm_gem_object_unreference(ctx);
5616 mutex_unlock(&dev->struct_mutex);
5617 return NULL;
5618 }
5619
5620 bool ironlake_set_drps(struct drm_device *dev, u8 val)
5621 {
5622 struct drm_i915_private *dev_priv = dev->dev_private;
5623 u16 rgvswctl;
5624
5625 rgvswctl = I915_READ16(MEMSWCTL);
5626 if (rgvswctl & MEMCTL_CMD_STS) {
5627 DRM_DEBUG("gpu busy, RCS change rejected\n");
5628 return false; /* still busy with another command */
5629 }
5630
5631 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5632 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5633 I915_WRITE16(MEMSWCTL, rgvswctl);
5634 POSTING_READ16(MEMSWCTL);
5635
5636 rgvswctl |= MEMCTL_CMD_STS;
5637 I915_WRITE16(MEMSWCTL, rgvswctl);
5638
5639 return true;
5640 }
5641
5642 void ironlake_enable_drps(struct drm_device *dev)
5643 {
5644 struct drm_i915_private *dev_priv = dev->dev_private;
5645 u32 rgvmodectl = I915_READ(MEMMODECTL);
5646 u8 fmax, fmin, fstart, vstart;
5647
5648 /* Enable temp reporting */
5649 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
5650 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
5651
5652 /* 100ms RC evaluation intervals */
5653 I915_WRITE(RCUPEI, 100000);
5654 I915_WRITE(RCDNEI, 100000);
5655
5656 /* Set max/min thresholds to 90ms and 80ms respectively */
5657 I915_WRITE(RCBMAXAVG, 90000);
5658 I915_WRITE(RCBMINAVG, 80000);
5659
5660 I915_WRITE(MEMIHYST, 1);
5661
5662 /* Set up min, max, and cur for interrupt handling */
5663 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5664 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5665 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5666 MEMMODE_FSTART_SHIFT;
5667
5668 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
5669 PXVFREQ_PX_SHIFT;
5670
5671 dev_priv->fmax = fmax; /* IPS callback will increase this */
5672 dev_priv->fstart = fstart;
5673
5674 dev_priv->max_delay = fstart;
5675 dev_priv->min_delay = fmin;
5676 dev_priv->cur_delay = fstart;
5677
5678 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
5679 fmax, fmin, fstart);
5680
5681 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5682
5683 /*
5684 * Interrupts will be enabled in ironlake_irq_postinstall
5685 */
5686
5687 I915_WRITE(VIDSTART, vstart);
5688 POSTING_READ(VIDSTART);
5689
5690 rgvmodectl |= MEMMODE_SWMODE_EN;
5691 I915_WRITE(MEMMODECTL, rgvmodectl);
5692
5693 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
5694 DRM_ERROR("stuck trying to change perf mode\n");
5695 msleep(1);
5696
5697 ironlake_set_drps(dev, fstart);
5698
5699 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
5700 I915_READ(0x112e0);
5701 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
5702 dev_priv->last_count2 = I915_READ(0x112f4);
5703 getrawmonotonic(&dev_priv->last_time2);
5704 }
5705
5706 void ironlake_disable_drps(struct drm_device *dev)
5707 {
5708 struct drm_i915_private *dev_priv = dev->dev_private;
5709 u16 rgvswctl = I915_READ16(MEMSWCTL);
5710
5711 /* Ack interrupts, disable EFC interrupt */
5712 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5713 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5714 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5715 I915_WRITE(DEIIR, DE_PCU_EVENT);
5716 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5717
5718 /* Go back to the starting frequency */
5719 ironlake_set_drps(dev, dev_priv->fstart);
5720 msleep(1);
5721 rgvswctl |= MEMCTL_CMD_STS;
5722 I915_WRITE(MEMSWCTL, rgvswctl);
5723 msleep(1);
5724
5725 }
5726
5727 static unsigned long intel_pxfreq(u32 vidfreq)
5728 {
5729 unsigned long freq;
5730 int div = (vidfreq & 0x3f0000) >> 16;
5731 int post = (vidfreq & 0x3000) >> 12;
5732 int pre = (vidfreq & 0x7);
5733
5734 if (!pre)
5735 return 0;
5736
5737 freq = ((div * 133333) / ((1<<post) * pre));
5738
5739 return freq;
5740 }
5741
5742 void intel_init_emon(struct drm_device *dev)
5743 {
5744 struct drm_i915_private *dev_priv = dev->dev_private;
5745 u32 lcfuse;
5746 u8 pxw[16];
5747 int i;
5748
5749 /* Disable to program */
5750 I915_WRITE(ECR, 0);
5751 POSTING_READ(ECR);
5752
5753 /* Program energy weights for various events */
5754 I915_WRITE(SDEW, 0x15040d00);
5755 I915_WRITE(CSIEW0, 0x007f0000);
5756 I915_WRITE(CSIEW1, 0x1e220004);
5757 I915_WRITE(CSIEW2, 0x04000004);
5758
5759 for (i = 0; i < 5; i++)
5760 I915_WRITE(PEW + (i * 4), 0);
5761 for (i = 0; i < 3; i++)
5762 I915_WRITE(DEW + (i * 4), 0);
5763
5764 /* Program P-state weights to account for frequency power adjustment */
5765 for (i = 0; i < 16; i++) {
5766 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5767 unsigned long freq = intel_pxfreq(pxvidfreq);
5768 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5769 PXVFREQ_PX_SHIFT;
5770 unsigned long val;
5771
5772 val = vid * vid;
5773 val *= (freq / 1000);
5774 val *= 255;
5775 val /= (127*127*900);
5776 if (val > 0xff)
5777 DRM_ERROR("bad pxval: %ld\n", val);
5778 pxw[i] = val;
5779 }
5780 /* Render standby states get 0 weight */
5781 pxw[14] = 0;
5782 pxw[15] = 0;
5783
5784 for (i = 0; i < 4; i++) {
5785 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5786 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5787 I915_WRITE(PXW + (i * 4), val);
5788 }
5789
5790 /* Adjust magic regs to magic values (more experimental results) */
5791 I915_WRITE(OGW0, 0);
5792 I915_WRITE(OGW1, 0);
5793 I915_WRITE(EG0, 0x00007f00);
5794 I915_WRITE(EG1, 0x0000000e);
5795 I915_WRITE(EG2, 0x000e0000);
5796 I915_WRITE(EG3, 0x68000300);
5797 I915_WRITE(EG4, 0x42000000);
5798 I915_WRITE(EG5, 0x00140031);
5799 I915_WRITE(EG6, 0);
5800 I915_WRITE(EG7, 0);
5801
5802 for (i = 0; i < 8; i++)
5803 I915_WRITE(PXWL + (i * 4), 0);
5804
5805 /* Enable PMON + select events */
5806 I915_WRITE(ECR, 0x80000019);
5807
5808 lcfuse = I915_READ(LCFUSE02);
5809
5810 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
5811 }
5812
5813 void intel_init_clock_gating(struct drm_device *dev)
5814 {
5815 struct drm_i915_private *dev_priv = dev->dev_private;
5816
5817 /*
5818 * Disable clock gating reported to work incorrectly according to the
5819 * specs, but enable as much else as we can.
5820 */
5821 if (HAS_PCH_SPLIT(dev)) {
5822 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
5823
5824 if (IS_GEN5(dev)) {
5825 /* Required for FBC */
5826 dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
5827 /* Required for CxSR */
5828 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
5829
5830 I915_WRITE(PCH_3DCGDIS0,
5831 MARIUNIT_CLOCK_GATE_DISABLE |
5832 SVSMUNIT_CLOCK_GATE_DISABLE);
5833 }
5834
5835 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
5836
5837 /*
5838 * On Ibex Peak and Cougar Point, we need to disable clock
5839 * gating for the panel power sequencer or it will fail to
5840 * start up when no ports are active.
5841 */
5842 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
5843
5844 /*
5845 * According to the spec the following bits should be set in
5846 * order to enable memory self-refresh
5847 * The bit 22/21 of 0x42004
5848 * The bit 5 of 0x42020
5849 * The bit 15 of 0x45000
5850 */
5851 if (IS_GEN5(dev)) {
5852 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5853 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5854 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5855 I915_WRITE(ILK_DSPCLK_GATE,
5856 (I915_READ(ILK_DSPCLK_GATE) |
5857 ILK_DPARB_CLK_GATE));
5858 I915_WRITE(DISP_ARB_CTL,
5859 (I915_READ(DISP_ARB_CTL) |
5860 DISP_FBC_WM_DIS));
5861 I915_WRITE(WM3_LP_ILK, 0);
5862 I915_WRITE(WM2_LP_ILK, 0);
5863 I915_WRITE(WM1_LP_ILK, 0);
5864 }
5865 /*
5866 * Based on the document from hardware guys the following bits
5867 * should be set unconditionally in order to enable FBC.
5868 * The bit 22 of 0x42000
5869 * The bit 22 of 0x42004
5870 * The bit 7,8,9 of 0x42020.
5871 */
5872 if (IS_IRONLAKE_M(dev)) {
5873 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5874 I915_READ(ILK_DISPLAY_CHICKEN1) |
5875 ILK_FBCQ_DIS);
5876 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5877 I915_READ(ILK_DISPLAY_CHICKEN2) |
5878 ILK_DPARB_GATE);
5879 I915_WRITE(ILK_DSPCLK_GATE,
5880 I915_READ(ILK_DSPCLK_GATE) |
5881 ILK_DPFC_DIS1 |
5882 ILK_DPFC_DIS2 |
5883 ILK_CLK_FBC);
5884 }
5885 return;
5886 } else if (IS_G4X(dev)) {
5887 uint32_t dspclk_gate;
5888 I915_WRITE(RENCLK_GATE_D1, 0);
5889 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5890 GS_UNIT_CLOCK_GATE_DISABLE |
5891 CL_UNIT_CLOCK_GATE_DISABLE);
5892 I915_WRITE(RAMCLK_GATE_D, 0);
5893 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5894 OVRUNIT_CLOCK_GATE_DISABLE |
5895 OVCUNIT_CLOCK_GATE_DISABLE;
5896 if (IS_GM45(dev))
5897 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5898 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5899 } else if (IS_CRESTLINE(dev)) {
5900 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5901 I915_WRITE(RENCLK_GATE_D2, 0);
5902 I915_WRITE(DSPCLK_GATE_D, 0);
5903 I915_WRITE(RAMCLK_GATE_D, 0);
5904 I915_WRITE16(DEUC, 0);
5905 } else if (IS_BROADWATER(dev)) {
5906 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5907 I965_RCC_CLOCK_GATE_DISABLE |
5908 I965_RCPB_CLOCK_GATE_DISABLE |
5909 I965_ISC_CLOCK_GATE_DISABLE |
5910 I965_FBC_CLOCK_GATE_DISABLE);
5911 I915_WRITE(RENCLK_GATE_D2, 0);
5912 } else if (IS_GEN3(dev)) {
5913 u32 dstate = I915_READ(D_STATE);
5914
5915 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5916 DSTATE_DOT_CLOCK_GATING;
5917 I915_WRITE(D_STATE, dstate);
5918 } else if (IS_I85X(dev) || IS_I865G(dev)) {
5919 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5920 } else if (IS_I830(dev)) {
5921 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5922 }
5923
5924 /*
5925 * GPU can automatically power down the render unit if given a page
5926 * to save state.
5927 */
5928 if (IS_IRONLAKE_M(dev)) {
5929 if (dev_priv->renderctx == NULL)
5930 dev_priv->renderctx = intel_alloc_context_page(dev);
5931 if (dev_priv->renderctx) {
5932 struct drm_i915_gem_object *obj_priv;
5933 obj_priv = to_intel_bo(dev_priv->renderctx);
5934 if (obj_priv) {
5935 BEGIN_LP_RING(4);
5936 OUT_RING(MI_SET_CONTEXT);
5937 OUT_RING(obj_priv->gtt_offset |
5938 MI_MM_SPACE_GTT |
5939 MI_SAVE_EXT_STATE_EN |
5940 MI_RESTORE_EXT_STATE_EN |
5941 MI_RESTORE_INHIBIT);
5942 OUT_RING(MI_NOOP);
5943 OUT_RING(MI_FLUSH);
5944 ADVANCE_LP_RING();
5945 }
5946 } else
5947 DRM_DEBUG_KMS("Failed to allocate render context."
5948 "Disable RC6\n");
5949 }
5950
5951 if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
5952 struct drm_i915_gem_object *obj_priv = NULL;
5953
5954 if (dev_priv->pwrctx) {
5955 obj_priv = to_intel_bo(dev_priv->pwrctx);
5956 } else {
5957 struct drm_gem_object *pwrctx;
5958
5959 pwrctx = intel_alloc_context_page(dev);
5960 if (pwrctx) {
5961 dev_priv->pwrctx = pwrctx;
5962 obj_priv = to_intel_bo(pwrctx);
5963 }
5964 }
5965
5966 if (obj_priv) {
5967 I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
5968 I915_WRITE(MCHBAR_RENDER_STANDBY,
5969 I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
5970 }
5971 }
5972 }
5973
5974 /* Set up chip specific display functions */
5975 static void intel_init_display(struct drm_device *dev)
5976 {
5977 struct drm_i915_private *dev_priv = dev->dev_private;
5978
5979 /* We always want a DPMS function */
5980 if (HAS_PCH_SPLIT(dev))
5981 dev_priv->display.dpms = ironlake_crtc_dpms;
5982 else
5983 dev_priv->display.dpms = i9xx_crtc_dpms;
5984
5985 if (I915_HAS_FBC(dev)) {
5986 if (IS_IRONLAKE_M(dev)) {
5987 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5988 dev_priv->display.enable_fbc = ironlake_enable_fbc;
5989 dev_priv->display.disable_fbc = ironlake_disable_fbc;
5990 } else if (IS_GM45(dev)) {
5991 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5992 dev_priv->display.enable_fbc = g4x_enable_fbc;
5993 dev_priv->display.disable_fbc = g4x_disable_fbc;
5994 } else if (IS_CRESTLINE(dev)) {
5995 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5996 dev_priv->display.enable_fbc = i8xx_enable_fbc;
5997 dev_priv->display.disable_fbc = i8xx_disable_fbc;
5998 }
5999 /* 855GM needs testing */
6000 }
6001
6002 /* Returns the core display clock speed */
6003 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
6004 dev_priv->display.get_display_clock_speed =
6005 i945_get_display_clock_speed;
6006 else if (IS_I915G(dev))
6007 dev_priv->display.get_display_clock_speed =
6008 i915_get_display_clock_speed;
6009 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
6010 dev_priv->display.get_display_clock_speed =
6011 i9xx_misc_get_display_clock_speed;
6012 else if (IS_I915GM(dev))
6013 dev_priv->display.get_display_clock_speed =
6014 i915gm_get_display_clock_speed;
6015 else if (IS_I865G(dev))
6016 dev_priv->display.get_display_clock_speed =
6017 i865_get_display_clock_speed;
6018 else if (IS_I85X(dev))
6019 dev_priv->display.get_display_clock_speed =
6020 i855_get_display_clock_speed;
6021 else /* 852, 830 */
6022 dev_priv->display.get_display_clock_speed =
6023 i830_get_display_clock_speed;
6024
6025 /* For FIFO watermark updates */
6026 if (HAS_PCH_SPLIT(dev)) {
6027 if (IS_GEN5(dev)) {
6028 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
6029 dev_priv->display.update_wm = ironlake_update_wm;
6030 else {
6031 DRM_DEBUG_KMS("Failed to get proper latency. "
6032 "Disable CxSR\n");
6033 dev_priv->display.update_wm = NULL;
6034 }
6035 } else
6036 dev_priv->display.update_wm = NULL;
6037 } else if (IS_PINEVIEW(dev)) {
6038 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6039 dev_priv->is_ddr3,
6040 dev_priv->fsb_freq,
6041 dev_priv->mem_freq)) {
6042 DRM_INFO("failed to find known CxSR latency "
6043 "(found ddr%s fsb freq %d, mem freq %d), "
6044 "disabling CxSR\n",
6045 (dev_priv->is_ddr3 == 1) ? "3": "2",
6046 dev_priv->fsb_freq, dev_priv->mem_freq);
6047 /* Disable CxSR and never update its watermark again */
6048 pineview_disable_cxsr(dev);
6049 dev_priv->display.update_wm = NULL;
6050 } else
6051 dev_priv->display.update_wm = pineview_update_wm;
6052 } else if (IS_G4X(dev))
6053 dev_priv->display.update_wm = g4x_update_wm;
6054 else if (IS_GEN4(dev))
6055 dev_priv->display.update_wm = i965_update_wm;
6056 else if (IS_GEN3(dev)) {
6057 dev_priv->display.update_wm = i9xx_update_wm;
6058 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6059 } else if (IS_I85X(dev)) {
6060 dev_priv->display.update_wm = i9xx_update_wm;
6061 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
6062 } else {
6063 dev_priv->display.update_wm = i830_update_wm;
6064 if (IS_845G(dev))
6065 dev_priv->display.get_fifo_size = i845_get_fifo_size;
6066 else
6067 dev_priv->display.get_fifo_size = i830_get_fifo_size;
6068 }
6069 }
6070
6071 /*
6072 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
6073 * resume, or other times. This quirk makes sure that's the case for
6074 * affected systems.
6075 */
6076 static void quirk_pipea_force (struct drm_device *dev)
6077 {
6078 struct drm_i915_private *dev_priv = dev->dev_private;
6079
6080 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
6081 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
6082 }
6083
6084 struct intel_quirk {
6085 int device;
6086 int subsystem_vendor;
6087 int subsystem_device;
6088 void (*hook)(struct drm_device *dev);
6089 };
6090
6091 struct intel_quirk intel_quirks[] = {
6092 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
6093 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
6094 /* HP Mini needs pipe A force quirk (LP: #322104) */
6095 { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
6096
6097 /* Thinkpad R31 needs pipe A force quirk */
6098 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
6099 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
6100 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
6101
6102 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
6103 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
6104 /* ThinkPad X40 needs pipe A force quirk */
6105
6106 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
6107 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
6108
6109 /* 855 & before need to leave pipe A & dpll A up */
6110 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6111 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6112 };
6113
6114 static void intel_init_quirks(struct drm_device *dev)
6115 {
6116 struct pci_dev *d = dev->pdev;
6117 int i;
6118
6119 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
6120 struct intel_quirk *q = &intel_quirks[i];
6121
6122 if (d->device == q->device &&
6123 (d->subsystem_vendor == q->subsystem_vendor ||
6124 q->subsystem_vendor == PCI_ANY_ID) &&
6125 (d->subsystem_device == q->subsystem_device ||
6126 q->subsystem_device == PCI_ANY_ID))
6127 q->hook(dev);
6128 }
6129 }
6130
6131 /* Disable the VGA plane that we never use */
6132 static void i915_disable_vga(struct drm_device *dev)
6133 {
6134 struct drm_i915_private *dev_priv = dev->dev_private;
6135 u8 sr1;
6136 u32 vga_reg;
6137
6138 if (HAS_PCH_SPLIT(dev))
6139 vga_reg = CPU_VGACNTRL;
6140 else
6141 vga_reg = VGACNTRL;
6142
6143 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6144 outb(1, VGA_SR_INDEX);
6145 sr1 = inb(VGA_SR_DATA);
6146 outb(sr1 | 1<<5, VGA_SR_DATA);
6147 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6148 udelay(300);
6149
6150 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
6151 POSTING_READ(vga_reg);
6152 }
6153
6154 void intel_modeset_init(struct drm_device *dev)
6155 {
6156 struct drm_i915_private *dev_priv = dev->dev_private;
6157 int i;
6158
6159 drm_mode_config_init(dev);
6160
6161 dev->mode_config.min_width = 0;
6162 dev->mode_config.min_height = 0;
6163
6164 dev->mode_config.funcs = (void *)&intel_mode_funcs;
6165
6166 intel_init_quirks(dev);
6167
6168 intel_init_display(dev);
6169
6170 if (IS_GEN2(dev)) {
6171 dev->mode_config.max_width = 2048;
6172 dev->mode_config.max_height = 2048;
6173 } else if (IS_GEN3(dev)) {
6174 dev->mode_config.max_width = 4096;
6175 dev->mode_config.max_height = 4096;
6176 } else {
6177 dev->mode_config.max_width = 8192;
6178 dev->mode_config.max_height = 8192;
6179 }
6180
6181 /* set memory base */
6182 if (IS_GEN2(dev))
6183 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
6184 else
6185 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
6186
6187 if (IS_MOBILE(dev) || !IS_GEN2(dev))
6188 dev_priv->num_pipe = 2;
6189 else
6190 dev_priv->num_pipe = 1;
6191 DRM_DEBUG_KMS("%d display pipe%s available.\n",
6192 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6193
6194 for (i = 0; i < dev_priv->num_pipe; i++) {
6195 intel_crtc_init(dev, i);
6196 }
6197
6198 intel_setup_outputs(dev);
6199
6200 intel_init_clock_gating(dev);
6201
6202 /* Just disable it once at startup */
6203 i915_disable_vga(dev);
6204
6205 if (IS_IRONLAKE_M(dev)) {
6206 ironlake_enable_drps(dev);
6207 intel_init_emon(dev);
6208 }
6209
6210 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6211 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6212 (unsigned long)dev);
6213
6214 intel_setup_overlay(dev);
6215 }
6216
6217 void intel_modeset_cleanup(struct drm_device *dev)
6218 {
6219 struct drm_i915_private *dev_priv = dev->dev_private;
6220 struct drm_crtc *crtc;
6221 struct intel_crtc *intel_crtc;
6222
6223 drm_kms_helper_poll_fini(dev);
6224 mutex_lock(&dev->struct_mutex);
6225
6226 intel_unregister_dsm_handler();
6227
6228
6229 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6230 /* Skip inactive CRTCs */
6231 if (!crtc->fb)
6232 continue;
6233
6234 intel_crtc = to_intel_crtc(crtc);
6235 intel_increase_pllclock(crtc);
6236 }
6237
6238 if (dev_priv->display.disable_fbc)
6239 dev_priv->display.disable_fbc(dev);
6240
6241 if (dev_priv->renderctx) {
6242 struct drm_i915_gem_object *obj_priv;
6243
6244 obj_priv = to_intel_bo(dev_priv->renderctx);
6245 I915_WRITE(CCID, obj_priv->gtt_offset &~ CCID_EN);
6246 I915_READ(CCID);
6247 i915_gem_object_unpin(dev_priv->renderctx);
6248 drm_gem_object_unreference(dev_priv->renderctx);
6249 }
6250
6251 if (dev_priv->pwrctx) {
6252 struct drm_i915_gem_object *obj_priv;
6253
6254 obj_priv = to_intel_bo(dev_priv->pwrctx);
6255 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
6256 I915_READ(PWRCTXA);
6257 i915_gem_object_unpin(dev_priv->pwrctx);
6258 drm_gem_object_unreference(dev_priv->pwrctx);
6259 }
6260
6261 if (IS_IRONLAKE_M(dev))
6262 ironlake_disable_drps(dev);
6263
6264 mutex_unlock(&dev->struct_mutex);
6265
6266 /* Disable the irq before mode object teardown, for the irq might
6267 * enqueue unpin/hotplug work. */
6268 drm_irq_uninstall(dev);
6269 cancel_work_sync(&dev_priv->hotplug_work);
6270
6271 /* Shut off idle work before the crtcs get freed. */
6272 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6273 intel_crtc = to_intel_crtc(crtc);
6274 del_timer_sync(&intel_crtc->idle_timer);
6275 }
6276 del_timer_sync(&dev_priv->idle_timer);
6277 cancel_work_sync(&dev_priv->idle_work);
6278
6279 drm_mode_config_cleanup(dev);
6280 }
6281
6282 /*
6283 * Return which encoder is currently attached for connector.
6284 */
6285 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
6286 {
6287 return &intel_attached_encoder(connector)->base;
6288 }
6289
6290 void intel_connector_attach_encoder(struct intel_connector *connector,
6291 struct intel_encoder *encoder)
6292 {
6293 connector->encoder = encoder;
6294 drm_mode_connector_attach_encoder(&connector->base,
6295 &encoder->base);
6296 }
6297
6298 /*
6299 * set vga decode state - true == enable VGA decode
6300 */
6301 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6302 {
6303 struct drm_i915_private *dev_priv = dev->dev_private;
6304 u16 gmch_ctrl;
6305
6306 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6307 if (state)
6308 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6309 else
6310 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6311 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
6312 return 0;
6313 }
Linux kernel - Deliverables
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