2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_rect.h>
44 #include <linux/dma_remapping.h>
46 /* Primary plane formats supported by all gen */
47 #define COMMON_PRIMARY_FORMATS \
50 DRM_FORMAT_XRGB8888, \
53 /* Primary plane formats for gen <= 3 */
54 static const uint32_t intel_primary_formats_gen2
[] = {
55 COMMON_PRIMARY_FORMATS
,
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t intel_primary_formats_gen4
[] = {
62 COMMON_PRIMARY_FORMATS
, \
65 DRM_FORMAT_XRGB2101010
,
66 DRM_FORMAT_ARGB2101010
,
67 DRM_FORMAT_XBGR2101010
,
68 DRM_FORMAT_ABGR2101010
,
72 static const uint32_t intel_cursor_formats
[] = {
76 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
78 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
79 struct intel_crtc_state
*pipe_config
);
80 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
81 struct intel_crtc_state
*pipe_config
);
83 static int intel_set_mode(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
,
84 int x
, int y
, struct drm_framebuffer
*old_fb
);
85 static int intel_framebuffer_init(struct drm_device
*dev
,
86 struct intel_framebuffer
*ifb
,
87 struct drm_mode_fb_cmd2
*mode_cmd
,
88 struct drm_i915_gem_object
*obj
);
89 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
);
90 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
);
91 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
92 struct intel_link_m_n
*m_n
,
93 struct intel_link_m_n
*m2_n2
);
94 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
);
95 static void haswell_set_pipeconf(struct drm_crtc
*crtc
);
96 static void intel_set_pipe_csc(struct drm_crtc
*crtc
);
97 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
98 const struct intel_crtc_state
*pipe_config
);
99 static void chv_prepare_pll(struct intel_crtc
*crtc
,
100 const struct intel_crtc_state
*pipe_config
);
101 static void intel_begin_crtc_commit(struct drm_crtc
*crtc
);
102 static void intel_finish_crtc_commit(struct drm_crtc
*crtc
);
104 static struct intel_encoder
*intel_find_encoder(struct intel_connector
*connector
, int pipe
)
106 if (!connector
->mst_port
)
107 return connector
->encoder
;
109 return &connector
->mst_port
->mst_encoders
[pipe
]->base
;
118 int p2_slow
, p2_fast
;
121 typedef struct intel_limit intel_limit_t
;
123 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
128 intel_pch_rawclk(struct drm_device
*dev
)
130 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
132 WARN_ON(!HAS_PCH_SPLIT(dev
));
134 return I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
;
137 static inline u32
/* units of 100MHz */
138 intel_fdi_link_freq(struct drm_device
*dev
)
141 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
142 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
147 static const intel_limit_t intel_limits_i8xx_dac
= {
148 .dot
= { .min
= 25000, .max
= 350000 },
149 .vco
= { .min
= 908000, .max
= 1512000 },
150 .n
= { .min
= 2, .max
= 16 },
151 .m
= { .min
= 96, .max
= 140 },
152 .m1
= { .min
= 18, .max
= 26 },
153 .m2
= { .min
= 6, .max
= 16 },
154 .p
= { .min
= 4, .max
= 128 },
155 .p1
= { .min
= 2, .max
= 33 },
156 .p2
= { .dot_limit
= 165000,
157 .p2_slow
= 4, .p2_fast
= 2 },
160 static const intel_limit_t intel_limits_i8xx_dvo
= {
161 .dot
= { .min
= 25000, .max
= 350000 },
162 .vco
= { .min
= 908000, .max
= 1512000 },
163 .n
= { .min
= 2, .max
= 16 },
164 .m
= { .min
= 96, .max
= 140 },
165 .m1
= { .min
= 18, .max
= 26 },
166 .m2
= { .min
= 6, .max
= 16 },
167 .p
= { .min
= 4, .max
= 128 },
168 .p1
= { .min
= 2, .max
= 33 },
169 .p2
= { .dot_limit
= 165000,
170 .p2_slow
= 4, .p2_fast
= 4 },
173 static const intel_limit_t intel_limits_i8xx_lvds
= {
174 .dot
= { .min
= 25000, .max
= 350000 },
175 .vco
= { .min
= 908000, .max
= 1512000 },
176 .n
= { .min
= 2, .max
= 16 },
177 .m
= { .min
= 96, .max
= 140 },
178 .m1
= { .min
= 18, .max
= 26 },
179 .m2
= { .min
= 6, .max
= 16 },
180 .p
= { .min
= 4, .max
= 128 },
181 .p1
= { .min
= 1, .max
= 6 },
182 .p2
= { .dot_limit
= 165000,
183 .p2_slow
= 14, .p2_fast
= 7 },
186 static const intel_limit_t intel_limits_i9xx_sdvo
= {
187 .dot
= { .min
= 20000, .max
= 400000 },
188 .vco
= { .min
= 1400000, .max
= 2800000 },
189 .n
= { .min
= 1, .max
= 6 },
190 .m
= { .min
= 70, .max
= 120 },
191 .m1
= { .min
= 8, .max
= 18 },
192 .m2
= { .min
= 3, .max
= 7 },
193 .p
= { .min
= 5, .max
= 80 },
194 .p1
= { .min
= 1, .max
= 8 },
195 .p2
= { .dot_limit
= 200000,
196 .p2_slow
= 10, .p2_fast
= 5 },
199 static const intel_limit_t intel_limits_i9xx_lvds
= {
200 .dot
= { .min
= 20000, .max
= 400000 },
201 .vco
= { .min
= 1400000, .max
= 2800000 },
202 .n
= { .min
= 1, .max
= 6 },
203 .m
= { .min
= 70, .max
= 120 },
204 .m1
= { .min
= 8, .max
= 18 },
205 .m2
= { .min
= 3, .max
= 7 },
206 .p
= { .min
= 7, .max
= 98 },
207 .p1
= { .min
= 1, .max
= 8 },
208 .p2
= { .dot_limit
= 112000,
209 .p2_slow
= 14, .p2_fast
= 7 },
213 static const intel_limit_t intel_limits_g4x_sdvo
= {
214 .dot
= { .min
= 25000, .max
= 270000 },
215 .vco
= { .min
= 1750000, .max
= 3500000},
216 .n
= { .min
= 1, .max
= 4 },
217 .m
= { .min
= 104, .max
= 138 },
218 .m1
= { .min
= 17, .max
= 23 },
219 .m2
= { .min
= 5, .max
= 11 },
220 .p
= { .min
= 10, .max
= 30 },
221 .p1
= { .min
= 1, .max
= 3},
222 .p2
= { .dot_limit
= 270000,
228 static const intel_limit_t intel_limits_g4x_hdmi
= {
229 .dot
= { .min
= 22000, .max
= 400000 },
230 .vco
= { .min
= 1750000, .max
= 3500000},
231 .n
= { .min
= 1, .max
= 4 },
232 .m
= { .min
= 104, .max
= 138 },
233 .m1
= { .min
= 16, .max
= 23 },
234 .m2
= { .min
= 5, .max
= 11 },
235 .p
= { .min
= 5, .max
= 80 },
236 .p1
= { .min
= 1, .max
= 8},
237 .p2
= { .dot_limit
= 165000,
238 .p2_slow
= 10, .p2_fast
= 5 },
241 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
242 .dot
= { .min
= 20000, .max
= 115000 },
243 .vco
= { .min
= 1750000, .max
= 3500000 },
244 .n
= { .min
= 1, .max
= 3 },
245 .m
= { .min
= 104, .max
= 138 },
246 .m1
= { .min
= 17, .max
= 23 },
247 .m2
= { .min
= 5, .max
= 11 },
248 .p
= { .min
= 28, .max
= 112 },
249 .p1
= { .min
= 2, .max
= 8 },
250 .p2
= { .dot_limit
= 0,
251 .p2_slow
= 14, .p2_fast
= 14
255 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
256 .dot
= { .min
= 80000, .max
= 224000 },
257 .vco
= { .min
= 1750000, .max
= 3500000 },
258 .n
= { .min
= 1, .max
= 3 },
259 .m
= { .min
= 104, .max
= 138 },
260 .m1
= { .min
= 17, .max
= 23 },
261 .m2
= { .min
= 5, .max
= 11 },
262 .p
= { .min
= 14, .max
= 42 },
263 .p1
= { .min
= 2, .max
= 6 },
264 .p2
= { .dot_limit
= 0,
265 .p2_slow
= 7, .p2_fast
= 7
269 static const intel_limit_t intel_limits_pineview_sdvo
= {
270 .dot
= { .min
= 20000, .max
= 400000},
271 .vco
= { .min
= 1700000, .max
= 3500000 },
272 /* Pineview's Ncounter is a ring counter */
273 .n
= { .min
= 3, .max
= 6 },
274 .m
= { .min
= 2, .max
= 256 },
275 /* Pineview only has one combined m divider, which we treat as m2. */
276 .m1
= { .min
= 0, .max
= 0 },
277 .m2
= { .min
= 0, .max
= 254 },
278 .p
= { .min
= 5, .max
= 80 },
279 .p1
= { .min
= 1, .max
= 8 },
280 .p2
= { .dot_limit
= 200000,
281 .p2_slow
= 10, .p2_fast
= 5 },
284 static const intel_limit_t intel_limits_pineview_lvds
= {
285 .dot
= { .min
= 20000, .max
= 400000 },
286 .vco
= { .min
= 1700000, .max
= 3500000 },
287 .n
= { .min
= 3, .max
= 6 },
288 .m
= { .min
= 2, .max
= 256 },
289 .m1
= { .min
= 0, .max
= 0 },
290 .m2
= { .min
= 0, .max
= 254 },
291 .p
= { .min
= 7, .max
= 112 },
292 .p1
= { .min
= 1, .max
= 8 },
293 .p2
= { .dot_limit
= 112000,
294 .p2_slow
= 14, .p2_fast
= 14 },
297 /* Ironlake / Sandybridge
299 * We calculate clock using (register_value + 2) for N/M1/M2, so here
300 * the range value for them is (actual_value - 2).
302 static const intel_limit_t intel_limits_ironlake_dac
= {
303 .dot
= { .min
= 25000, .max
= 350000 },
304 .vco
= { .min
= 1760000, .max
= 3510000 },
305 .n
= { .min
= 1, .max
= 5 },
306 .m
= { .min
= 79, .max
= 127 },
307 .m1
= { .min
= 12, .max
= 22 },
308 .m2
= { .min
= 5, .max
= 9 },
309 .p
= { .min
= 5, .max
= 80 },
310 .p1
= { .min
= 1, .max
= 8 },
311 .p2
= { .dot_limit
= 225000,
312 .p2_slow
= 10, .p2_fast
= 5 },
315 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
316 .dot
= { .min
= 25000, .max
= 350000 },
317 .vco
= { .min
= 1760000, .max
= 3510000 },
318 .n
= { .min
= 1, .max
= 3 },
319 .m
= { .min
= 79, .max
= 118 },
320 .m1
= { .min
= 12, .max
= 22 },
321 .m2
= { .min
= 5, .max
= 9 },
322 .p
= { .min
= 28, .max
= 112 },
323 .p1
= { .min
= 2, .max
= 8 },
324 .p2
= { .dot_limit
= 225000,
325 .p2_slow
= 14, .p2_fast
= 14 },
328 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
329 .dot
= { .min
= 25000, .max
= 350000 },
330 .vco
= { .min
= 1760000, .max
= 3510000 },
331 .n
= { .min
= 1, .max
= 3 },
332 .m
= { .min
= 79, .max
= 127 },
333 .m1
= { .min
= 12, .max
= 22 },
334 .m2
= { .min
= 5, .max
= 9 },
335 .p
= { .min
= 14, .max
= 56 },
336 .p1
= { .min
= 2, .max
= 8 },
337 .p2
= { .dot_limit
= 225000,
338 .p2_slow
= 7, .p2_fast
= 7 },
341 /* LVDS 100mhz refclk limits. */
342 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
343 .dot
= { .min
= 25000, .max
= 350000 },
344 .vco
= { .min
= 1760000, .max
= 3510000 },
345 .n
= { .min
= 1, .max
= 2 },
346 .m
= { .min
= 79, .max
= 126 },
347 .m1
= { .min
= 12, .max
= 22 },
348 .m2
= { .min
= 5, .max
= 9 },
349 .p
= { .min
= 28, .max
= 112 },
350 .p1
= { .min
= 2, .max
= 8 },
351 .p2
= { .dot_limit
= 225000,
352 .p2_slow
= 14, .p2_fast
= 14 },
355 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
356 .dot
= { .min
= 25000, .max
= 350000 },
357 .vco
= { .min
= 1760000, .max
= 3510000 },
358 .n
= { .min
= 1, .max
= 3 },
359 .m
= { .min
= 79, .max
= 126 },
360 .m1
= { .min
= 12, .max
= 22 },
361 .m2
= { .min
= 5, .max
= 9 },
362 .p
= { .min
= 14, .max
= 42 },
363 .p1
= { .min
= 2, .max
= 6 },
364 .p2
= { .dot_limit
= 225000,
365 .p2_slow
= 7, .p2_fast
= 7 },
368 static const intel_limit_t intel_limits_vlv
= {
370 * These are the data rate limits (measured in fast clocks)
371 * since those are the strictest limits we have. The fast
372 * clock and actual rate limits are more relaxed, so checking
373 * them would make no difference.
375 .dot
= { .min
= 25000 * 5, .max
= 270000 * 5 },
376 .vco
= { .min
= 4000000, .max
= 6000000 },
377 .n
= { .min
= 1, .max
= 7 },
378 .m1
= { .min
= 2, .max
= 3 },
379 .m2
= { .min
= 11, .max
= 156 },
380 .p1
= { .min
= 2, .max
= 3 },
381 .p2
= { .p2_slow
= 2, .p2_fast
= 20 }, /* slow=min, fast=max */
384 static const intel_limit_t intel_limits_chv
= {
386 * These are the data rate limits (measured in fast clocks)
387 * since those are the strictest limits we have. The fast
388 * clock and actual rate limits are more relaxed, so checking
389 * them would make no difference.
391 .dot
= { .min
= 25000 * 5, .max
= 540000 * 5},
392 .vco
= { .min
= 4860000, .max
= 6700000 },
393 .n
= { .min
= 1, .max
= 1 },
394 .m1
= { .min
= 2, .max
= 2 },
395 .m2
= { .min
= 24 << 22, .max
= 175 << 22 },
396 .p1
= { .min
= 2, .max
= 4 },
397 .p2
= { .p2_slow
= 1, .p2_fast
= 14 },
400 static void vlv_clock(int refclk
, intel_clock_t
*clock
)
402 clock
->m
= clock
->m1
* clock
->m2
;
403 clock
->p
= clock
->p1
* clock
->p2
;
404 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
406 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
407 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
411 * Returns whether any output on the specified pipe is of the specified type
413 bool intel_pipe_has_type(struct intel_crtc
*crtc
, enum intel_output_type type
)
415 struct drm_device
*dev
= crtc
->base
.dev
;
416 struct intel_encoder
*encoder
;
418 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
)
419 if (encoder
->type
== type
)
426 * Returns whether any output on the specified pipe will have the specified
427 * type after a staged modeset is complete, i.e., the same as
428 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
431 static bool intel_pipe_will_have_type(struct intel_crtc
*crtc
, int type
)
433 struct drm_device
*dev
= crtc
->base
.dev
;
434 struct intel_encoder
*encoder
;
436 for_each_intel_encoder(dev
, encoder
)
437 if (encoder
->new_crtc
== crtc
&& encoder
->type
== type
)
443 static const intel_limit_t
*intel_ironlake_limit(struct intel_crtc
*crtc
,
446 struct drm_device
*dev
= crtc
->base
.dev
;
447 const intel_limit_t
*limit
;
449 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
)) {
450 if (intel_is_dual_link_lvds(dev
)) {
451 if (refclk
== 100000)
452 limit
= &intel_limits_ironlake_dual_lvds_100m
;
454 limit
= &intel_limits_ironlake_dual_lvds
;
456 if (refclk
== 100000)
457 limit
= &intel_limits_ironlake_single_lvds_100m
;
459 limit
= &intel_limits_ironlake_single_lvds
;
462 limit
= &intel_limits_ironlake_dac
;
467 static const intel_limit_t
*intel_g4x_limit(struct intel_crtc
*crtc
)
469 struct drm_device
*dev
= crtc
->base
.dev
;
470 const intel_limit_t
*limit
;
472 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
)) {
473 if (intel_is_dual_link_lvds(dev
))
474 limit
= &intel_limits_g4x_dual_channel_lvds
;
476 limit
= &intel_limits_g4x_single_channel_lvds
;
477 } else if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_HDMI
) ||
478 intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
479 limit
= &intel_limits_g4x_hdmi
;
480 } else if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_SDVO
)) {
481 limit
= &intel_limits_g4x_sdvo
;
482 } else /* The option is for other outputs */
483 limit
= &intel_limits_i9xx_sdvo
;
488 static const intel_limit_t
*intel_limit(struct intel_crtc
*crtc
, int refclk
)
490 struct drm_device
*dev
= crtc
->base
.dev
;
491 const intel_limit_t
*limit
;
493 if (HAS_PCH_SPLIT(dev
))
494 limit
= intel_ironlake_limit(crtc
, refclk
);
495 else if (IS_G4X(dev
)) {
496 limit
= intel_g4x_limit(crtc
);
497 } else if (IS_PINEVIEW(dev
)) {
498 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
))
499 limit
= &intel_limits_pineview_lvds
;
501 limit
= &intel_limits_pineview_sdvo
;
502 } else if (IS_CHERRYVIEW(dev
)) {
503 limit
= &intel_limits_chv
;
504 } else if (IS_VALLEYVIEW(dev
)) {
505 limit
= &intel_limits_vlv
;
506 } else if (!IS_GEN2(dev
)) {
507 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
))
508 limit
= &intel_limits_i9xx_lvds
;
510 limit
= &intel_limits_i9xx_sdvo
;
512 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
))
513 limit
= &intel_limits_i8xx_lvds
;
514 else if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_DVO
))
515 limit
= &intel_limits_i8xx_dvo
;
517 limit
= &intel_limits_i8xx_dac
;
522 /* m1 is reserved as 0 in Pineview, n is a ring counter */
523 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
525 clock
->m
= clock
->m2
+ 2;
526 clock
->p
= clock
->p1
* clock
->p2
;
527 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
529 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
530 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
533 static uint32_t i9xx_dpll_compute_m(struct dpll
*dpll
)
535 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
538 static void i9xx_clock(int refclk
, intel_clock_t
*clock
)
540 clock
->m
= i9xx_dpll_compute_m(clock
);
541 clock
->p
= clock
->p1
* clock
->p2
;
542 if (WARN_ON(clock
->n
+ 2 == 0 || clock
->p
== 0))
544 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
+ 2);
545 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
548 static void chv_clock(int refclk
, intel_clock_t
*clock
)
550 clock
->m
= clock
->m1
* clock
->m2
;
551 clock
->p
= clock
->p1
* clock
->p2
;
552 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
554 clock
->vco
= DIV_ROUND_CLOSEST_ULL((uint64_t)refclk
* clock
->m
,
556 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
559 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
561 * Returns whether the given set of divisors are valid for a given refclk with
562 * the given connectors.
565 static bool intel_PLL_is_valid(struct drm_device
*dev
,
566 const intel_limit_t
*limit
,
567 const intel_clock_t
*clock
)
569 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
570 INTELPllInvalid("n out of range\n");
571 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
572 INTELPllInvalid("p1 out of range\n");
573 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
574 INTELPllInvalid("m2 out of range\n");
575 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
576 INTELPllInvalid("m1 out of range\n");
578 if (!IS_PINEVIEW(dev
) && !IS_VALLEYVIEW(dev
))
579 if (clock
->m1
<= clock
->m2
)
580 INTELPllInvalid("m1 <= m2\n");
582 if (!IS_VALLEYVIEW(dev
)) {
583 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
584 INTELPllInvalid("p out of range\n");
585 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
586 INTELPllInvalid("m out of range\n");
589 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
590 INTELPllInvalid("vco out of range\n");
591 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
592 * connector, etc., rather than just a single range.
594 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
595 INTELPllInvalid("dot out of range\n");
601 i9xx_find_best_dpll(const intel_limit_t
*limit
, struct intel_crtc
*crtc
,
602 int target
, int refclk
, intel_clock_t
*match_clock
,
603 intel_clock_t
*best_clock
)
605 struct drm_device
*dev
= crtc
->base
.dev
;
609 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
)) {
611 * For LVDS just rely on its current settings for dual-channel.
612 * We haven't figured out how to reliably set up different
613 * single/dual channel state, if we even can.
615 if (intel_is_dual_link_lvds(dev
))
616 clock
.p2
= limit
->p2
.p2_fast
;
618 clock
.p2
= limit
->p2
.p2_slow
;
620 if (target
< limit
->p2
.dot_limit
)
621 clock
.p2
= limit
->p2
.p2_slow
;
623 clock
.p2
= limit
->p2
.p2_fast
;
626 memset(best_clock
, 0, sizeof(*best_clock
));
628 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
630 for (clock
.m2
= limit
->m2
.min
;
631 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
632 if (clock
.m2
>= clock
.m1
)
634 for (clock
.n
= limit
->n
.min
;
635 clock
.n
<= limit
->n
.max
; clock
.n
++) {
636 for (clock
.p1
= limit
->p1
.min
;
637 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
640 i9xx_clock(refclk
, &clock
);
641 if (!intel_PLL_is_valid(dev
, limit
,
645 clock
.p
!= match_clock
->p
)
648 this_err
= abs(clock
.dot
- target
);
649 if (this_err
< err
) {
658 return (err
!= target
);
662 pnv_find_best_dpll(const intel_limit_t
*limit
, struct intel_crtc
*crtc
,
663 int target
, int refclk
, intel_clock_t
*match_clock
,
664 intel_clock_t
*best_clock
)
666 struct drm_device
*dev
= crtc
->base
.dev
;
670 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
)) {
672 * For LVDS just rely on its current settings for dual-channel.
673 * We haven't figured out how to reliably set up different
674 * single/dual channel state, if we even can.
676 if (intel_is_dual_link_lvds(dev
))
677 clock
.p2
= limit
->p2
.p2_fast
;
679 clock
.p2
= limit
->p2
.p2_slow
;
681 if (target
< limit
->p2
.dot_limit
)
682 clock
.p2
= limit
->p2
.p2_slow
;
684 clock
.p2
= limit
->p2
.p2_fast
;
687 memset(best_clock
, 0, sizeof(*best_clock
));
689 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
691 for (clock
.m2
= limit
->m2
.min
;
692 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
693 for (clock
.n
= limit
->n
.min
;
694 clock
.n
<= limit
->n
.max
; clock
.n
++) {
695 for (clock
.p1
= limit
->p1
.min
;
696 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
699 pineview_clock(refclk
, &clock
);
700 if (!intel_PLL_is_valid(dev
, limit
,
704 clock
.p
!= match_clock
->p
)
707 this_err
= abs(clock
.dot
- target
);
708 if (this_err
< err
) {
717 return (err
!= target
);
721 g4x_find_best_dpll(const intel_limit_t
*limit
, struct intel_crtc
*crtc
,
722 int target
, int refclk
, intel_clock_t
*match_clock
,
723 intel_clock_t
*best_clock
)
725 struct drm_device
*dev
= crtc
->base
.dev
;
729 /* approximately equals target * 0.00585 */
730 int err_most
= (target
>> 8) + (target
>> 9);
733 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
)) {
734 if (intel_is_dual_link_lvds(dev
))
735 clock
.p2
= limit
->p2
.p2_fast
;
737 clock
.p2
= limit
->p2
.p2_slow
;
739 if (target
< limit
->p2
.dot_limit
)
740 clock
.p2
= limit
->p2
.p2_slow
;
742 clock
.p2
= limit
->p2
.p2_fast
;
745 memset(best_clock
, 0, sizeof(*best_clock
));
746 max_n
= limit
->n
.max
;
747 /* based on hardware requirement, prefer smaller n to precision */
748 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
749 /* based on hardware requirement, prefere larger m1,m2 */
750 for (clock
.m1
= limit
->m1
.max
;
751 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
752 for (clock
.m2
= limit
->m2
.max
;
753 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
754 for (clock
.p1
= limit
->p1
.max
;
755 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
758 i9xx_clock(refclk
, &clock
);
759 if (!intel_PLL_is_valid(dev
, limit
,
763 this_err
= abs(clock
.dot
- target
);
764 if (this_err
< err_most
) {
778 vlv_find_best_dpll(const intel_limit_t
*limit
, struct intel_crtc
*crtc
,
779 int target
, int refclk
, intel_clock_t
*match_clock
,
780 intel_clock_t
*best_clock
)
782 struct drm_device
*dev
= crtc
->base
.dev
;
784 unsigned int bestppm
= 1000000;
785 /* min update 19.2 MHz */
786 int max_n
= min(limit
->n
.max
, refclk
/ 19200);
789 target
*= 5; /* fast clock */
791 memset(best_clock
, 0, sizeof(*best_clock
));
793 /* based on hardware requirement, prefer smaller n to precision */
794 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
795 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
796 for (clock
.p2
= limit
->p2
.p2_fast
; clock
.p2
>= limit
->p2
.p2_slow
;
797 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
798 clock
.p
= clock
.p1
* clock
.p2
;
799 /* based on hardware requirement, prefer bigger m1,m2 values */
800 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
; clock
.m1
++) {
801 unsigned int ppm
, diff
;
803 clock
.m2
= DIV_ROUND_CLOSEST(target
* clock
.p
* clock
.n
,
806 vlv_clock(refclk
, &clock
);
808 if (!intel_PLL_is_valid(dev
, limit
,
812 diff
= abs(clock
.dot
- target
);
813 ppm
= div_u64(1000000ULL * diff
, target
);
815 if (ppm
< 100 && clock
.p
> best_clock
->p
) {
821 if (bestppm
>= 10 && ppm
< bestppm
- 10) {
835 chv_find_best_dpll(const intel_limit_t
*limit
, struct intel_crtc
*crtc
,
836 int target
, int refclk
, intel_clock_t
*match_clock
,
837 intel_clock_t
*best_clock
)
839 struct drm_device
*dev
= crtc
->base
.dev
;
844 memset(best_clock
, 0, sizeof(*best_clock
));
847 * Based on hardware doc, the n always set to 1, and m1 always
848 * set to 2. If requires to support 200Mhz refclk, we need to
849 * revisit this because n may not 1 anymore.
851 clock
.n
= 1, clock
.m1
= 2;
852 target
*= 5; /* fast clock */
854 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
855 for (clock
.p2
= limit
->p2
.p2_fast
;
856 clock
.p2
>= limit
->p2
.p2_slow
;
857 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
859 clock
.p
= clock
.p1
* clock
.p2
;
861 m2
= DIV_ROUND_CLOSEST_ULL(((uint64_t)target
* clock
.p
*
862 clock
.n
) << 22, refclk
* clock
.m1
);
864 if (m2
> INT_MAX
/clock
.m1
)
869 chv_clock(refclk
, &clock
);
871 if (!intel_PLL_is_valid(dev
, limit
, &clock
))
874 /* based on hardware requirement, prefer bigger p
876 if (clock
.p
> best_clock
->p
) {
886 bool intel_crtc_active(struct drm_crtc
*crtc
)
888 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
890 /* Be paranoid as we can arrive here with only partial
891 * state retrieved from the hardware during setup.
893 * We can ditch the adjusted_mode.crtc_clock check as soon
894 * as Haswell has gained clock readout/fastboot support.
896 * We can ditch the crtc->primary->fb check as soon as we can
897 * properly reconstruct framebuffers.
899 return intel_crtc
->active
&& crtc
->primary
->fb
&&
900 intel_crtc
->config
->base
.adjusted_mode
.crtc_clock
;
903 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
906 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
907 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
909 return intel_crtc
->config
->cpu_transcoder
;
912 static bool pipe_dsl_stopped(struct drm_device
*dev
, enum pipe pipe
)
914 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
915 u32 reg
= PIPEDSL(pipe
);
920 line_mask
= DSL_LINEMASK_GEN2
;
922 line_mask
= DSL_LINEMASK_GEN3
;
924 line1
= I915_READ(reg
) & line_mask
;
926 line2
= I915_READ(reg
) & line_mask
;
928 return line1
== line2
;
932 * intel_wait_for_pipe_off - wait for pipe to turn off
933 * @crtc: crtc whose pipe to wait for
935 * After disabling a pipe, we can't wait for vblank in the usual way,
936 * spinning on the vblank interrupt status bit, since we won't actually
937 * see an interrupt when the pipe is disabled.
940 * wait for the pipe register state bit to turn off
943 * wait for the display line value to settle (it usually
944 * ends up stopping at the start of the next frame).
947 static void intel_wait_for_pipe_off(struct intel_crtc
*crtc
)
949 struct drm_device
*dev
= crtc
->base
.dev
;
950 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
951 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
952 enum pipe pipe
= crtc
->pipe
;
954 if (INTEL_INFO(dev
)->gen
>= 4) {
955 int reg
= PIPECONF(cpu_transcoder
);
957 /* Wait for the Pipe State to go off */
958 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
960 WARN(1, "pipe_off wait timed out\n");
962 /* Wait for the display line to settle */
963 if (wait_for(pipe_dsl_stopped(dev
, pipe
), 100))
964 WARN(1, "pipe_off wait timed out\n");
969 * ibx_digital_port_connected - is the specified port connected?
970 * @dev_priv: i915 private structure
971 * @port: the port to test
973 * Returns true if @port is connected, false otherwise.
975 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
976 struct intel_digital_port
*port
)
980 if (HAS_PCH_IBX(dev_priv
->dev
)) {
981 switch (port
->port
) {
983 bit
= SDE_PORTB_HOTPLUG
;
986 bit
= SDE_PORTC_HOTPLUG
;
989 bit
= SDE_PORTD_HOTPLUG
;
995 switch (port
->port
) {
997 bit
= SDE_PORTB_HOTPLUG_CPT
;
1000 bit
= SDE_PORTC_HOTPLUG_CPT
;
1003 bit
= SDE_PORTD_HOTPLUG_CPT
;
1010 return I915_READ(SDEISR
) & bit
;
1013 static const char *state_string(bool enabled
)
1015 return enabled
? "on" : "off";
1018 /* Only for pre-ILK configs */
1019 void assert_pll(struct drm_i915_private
*dev_priv
,
1020 enum pipe pipe
, bool state
)
1027 val
= I915_READ(reg
);
1028 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1029 I915_STATE_WARN(cur_state
!= state
,
1030 "PLL state assertion failure (expected %s, current %s)\n",
1031 state_string(state
), state_string(cur_state
));
1034 /* XXX: the dsi pll is shared between MIPI DSI ports */
1035 static void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
)
1040 mutex_lock(&dev_priv
->dpio_lock
);
1041 val
= vlv_cck_read(dev_priv
, CCK_REG_DSI_PLL_CONTROL
);
1042 mutex_unlock(&dev_priv
->dpio_lock
);
1044 cur_state
= val
& DSI_PLL_VCO_EN
;
1045 I915_STATE_WARN(cur_state
!= state
,
1046 "DSI PLL state assertion failure (expected %s, current %s)\n",
1047 state_string(state
), state_string(cur_state
));
1049 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1050 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1052 struct intel_shared_dpll
*
1053 intel_crtc_to_shared_dpll(struct intel_crtc
*crtc
)
1055 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1057 if (crtc
->config
->shared_dpll
< 0)
1060 return &dev_priv
->shared_dplls
[crtc
->config
->shared_dpll
];
1064 void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
1065 struct intel_shared_dpll
*pll
,
1069 struct intel_dpll_hw_state hw_state
;
1072 "asserting DPLL %s with no DPLL\n", state_string(state
)))
1075 cur_state
= pll
->get_hw_state(dev_priv
, pll
, &hw_state
);
1076 I915_STATE_WARN(cur_state
!= state
,
1077 "%s assertion failure (expected %s, current %s)\n",
1078 pll
->name
, state_string(state
), state_string(cur_state
));
1081 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1082 enum pipe pipe
, bool state
)
1087 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1090 if (HAS_DDI(dev_priv
->dev
)) {
1091 /* DDI does not have a specific FDI_TX register */
1092 reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1093 val
= I915_READ(reg
);
1094 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
1096 reg
= FDI_TX_CTL(pipe
);
1097 val
= I915_READ(reg
);
1098 cur_state
= !!(val
& FDI_TX_ENABLE
);
1100 I915_STATE_WARN(cur_state
!= state
,
1101 "FDI TX state assertion failure (expected %s, current %s)\n",
1102 state_string(state
), state_string(cur_state
));
1104 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1105 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1107 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1108 enum pipe pipe
, bool state
)
1114 reg
= FDI_RX_CTL(pipe
);
1115 val
= I915_READ(reg
);
1116 cur_state
= !!(val
& FDI_RX_ENABLE
);
1117 I915_STATE_WARN(cur_state
!= state
,
1118 "FDI RX state assertion failure (expected %s, current %s)\n",
1119 state_string(state
), state_string(cur_state
));
1121 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1122 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1124 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1130 /* ILK FDI PLL is always enabled */
1131 if (INTEL_INFO(dev_priv
->dev
)->gen
== 5)
1134 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1135 if (HAS_DDI(dev_priv
->dev
))
1138 reg
= FDI_TX_CTL(pipe
);
1139 val
= I915_READ(reg
);
1140 I915_STATE_WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1143 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1144 enum pipe pipe
, bool state
)
1150 reg
= FDI_RX_CTL(pipe
);
1151 val
= I915_READ(reg
);
1152 cur_state
= !!(val
& FDI_RX_PLL_ENABLE
);
1153 I915_STATE_WARN(cur_state
!= state
,
1154 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1155 state_string(state
), state_string(cur_state
));
1158 void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1161 struct drm_device
*dev
= dev_priv
->dev
;
1164 enum pipe panel_pipe
= PIPE_A
;
1167 if (WARN_ON(HAS_DDI(dev
)))
1170 if (HAS_PCH_SPLIT(dev
)) {
1173 pp_reg
= PCH_PP_CONTROL
;
1174 port_sel
= I915_READ(PCH_PP_ON_DELAYS
) & PANEL_PORT_SELECT_MASK
;
1176 if (port_sel
== PANEL_PORT_SELECT_LVDS
&&
1177 I915_READ(PCH_LVDS
) & LVDS_PIPEB_SELECT
)
1178 panel_pipe
= PIPE_B
;
1179 /* XXX: else fix for eDP */
1180 } else if (IS_VALLEYVIEW(dev
)) {
1181 /* presumably write lock depends on pipe, not port select */
1182 pp_reg
= VLV_PIPE_PP_CONTROL(pipe
);
1185 pp_reg
= PP_CONTROL
;
1186 if (I915_READ(LVDS
) & LVDS_PIPEB_SELECT
)
1187 panel_pipe
= PIPE_B
;
1190 val
= I915_READ(pp_reg
);
1191 if (!(val
& PANEL_POWER_ON
) ||
1192 ((val
& PANEL_UNLOCK_MASK
) == PANEL_UNLOCK_REGS
))
1195 I915_STATE_WARN(panel_pipe
== pipe
&& locked
,
1196 "panel assertion failure, pipe %c regs locked\n",
1200 static void assert_cursor(struct drm_i915_private
*dev_priv
,
1201 enum pipe pipe
, bool state
)
1203 struct drm_device
*dev
= dev_priv
->dev
;
1206 if (IS_845G(dev
) || IS_I865G(dev
))
1207 cur_state
= I915_READ(_CURACNTR
) & CURSOR_ENABLE
;
1209 cur_state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
1211 I915_STATE_WARN(cur_state
!= state
,
1212 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1213 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1215 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1216 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1218 void assert_pipe(struct drm_i915_private
*dev_priv
,
1219 enum pipe pipe
, bool state
)
1224 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1227 /* if we need the pipe quirk it must be always on */
1228 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1229 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1232 if (!intel_display_power_is_enabled(dev_priv
,
1233 POWER_DOMAIN_TRANSCODER(cpu_transcoder
))) {
1236 reg
= PIPECONF(cpu_transcoder
);
1237 val
= I915_READ(reg
);
1238 cur_state
= !!(val
& PIPECONF_ENABLE
);
1241 I915_STATE_WARN(cur_state
!= state
,
1242 "pipe %c assertion failure (expected %s, current %s)\n",
1243 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1246 static void assert_plane(struct drm_i915_private
*dev_priv
,
1247 enum plane plane
, bool state
)
1253 reg
= DSPCNTR(plane
);
1254 val
= I915_READ(reg
);
1255 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1256 I915_STATE_WARN(cur_state
!= state
,
1257 "plane %c assertion failure (expected %s, current %s)\n",
1258 plane_name(plane
), state_string(state
), state_string(cur_state
));
1261 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1262 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1264 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1267 struct drm_device
*dev
= dev_priv
->dev
;
1272 /* Primary planes are fixed to pipes on gen4+ */
1273 if (INTEL_INFO(dev
)->gen
>= 4) {
1274 reg
= DSPCNTR(pipe
);
1275 val
= I915_READ(reg
);
1276 I915_STATE_WARN(val
& DISPLAY_PLANE_ENABLE
,
1277 "plane %c assertion failure, should be disabled but not\n",
1282 /* Need to check both planes against the pipe */
1283 for_each_pipe(dev_priv
, i
) {
1285 val
= I915_READ(reg
);
1286 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1287 DISPPLANE_SEL_PIPE_SHIFT
;
1288 I915_STATE_WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1289 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1290 plane_name(i
), pipe_name(pipe
));
1294 static void assert_sprites_disabled(struct drm_i915_private
*dev_priv
,
1297 struct drm_device
*dev
= dev_priv
->dev
;
1301 if (INTEL_INFO(dev
)->gen
>= 9) {
1302 for_each_sprite(pipe
, sprite
) {
1303 val
= I915_READ(PLANE_CTL(pipe
, sprite
));
1304 I915_STATE_WARN(val
& PLANE_CTL_ENABLE
,
1305 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1306 sprite
, pipe_name(pipe
));
1308 } else if (IS_VALLEYVIEW(dev
)) {
1309 for_each_sprite(pipe
, sprite
) {
1310 reg
= SPCNTR(pipe
, sprite
);
1311 val
= I915_READ(reg
);
1312 I915_STATE_WARN(val
& SP_ENABLE
,
1313 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1314 sprite_name(pipe
, sprite
), pipe_name(pipe
));
1316 } else if (INTEL_INFO(dev
)->gen
>= 7) {
1318 val
= I915_READ(reg
);
1319 I915_STATE_WARN(val
& SPRITE_ENABLE
,
1320 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1321 plane_name(pipe
), pipe_name(pipe
));
1322 } else if (INTEL_INFO(dev
)->gen
>= 5) {
1323 reg
= DVSCNTR(pipe
);
1324 val
= I915_READ(reg
);
1325 I915_STATE_WARN(val
& DVS_ENABLE
,
1326 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1327 plane_name(pipe
), pipe_name(pipe
));
1331 static void assert_vblank_disabled(struct drm_crtc
*crtc
)
1333 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc
) == 0))
1334 drm_crtc_vblank_put(crtc
);
1337 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1342 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv
->dev
) || HAS_PCH_CPT(dev_priv
->dev
)));
1344 val
= I915_READ(PCH_DREF_CONTROL
);
1345 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1346 DREF_SUPERSPREAD_SOURCE_MASK
));
1347 I915_STATE_WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1350 static void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1357 reg
= PCH_TRANSCONF(pipe
);
1358 val
= I915_READ(reg
);
1359 enabled
= !!(val
& TRANS_ENABLE
);
1360 I915_STATE_WARN(enabled
,
1361 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1365 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1366 enum pipe pipe
, u32 port_sel
, u32 val
)
1368 if ((val
& DP_PORT_EN
) == 0)
1371 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1372 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1373 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1374 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1376 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1377 if ((val
& DP_PIPE_MASK_CHV
) != DP_PIPE_SELECT_CHV(pipe
))
1380 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1386 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1387 enum pipe pipe
, u32 val
)
1389 if ((val
& SDVO_ENABLE
) == 0)
1392 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1393 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1395 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1396 if ((val
& SDVO_PIPE_SEL_MASK_CHV
) != SDVO_PIPE_SEL_CHV(pipe
))
1399 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1405 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1406 enum pipe pipe
, u32 val
)
1408 if ((val
& LVDS_PORT_EN
) == 0)
1411 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1412 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1415 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1421 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1422 enum pipe pipe
, u32 val
)
1424 if ((val
& ADPA_DAC_ENABLE
) == 0)
1426 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1427 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1430 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1436 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1437 enum pipe pipe
, int reg
, u32 port_sel
)
1439 u32 val
= I915_READ(reg
);
1440 I915_STATE_WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1441 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1442 reg
, pipe_name(pipe
));
1444 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& DP_PORT_EN
) == 0
1445 && (val
& DP_PIPEB_SELECT
),
1446 "IBX PCH dp port still using transcoder B\n");
1449 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1450 enum pipe pipe
, int reg
)
1452 u32 val
= I915_READ(reg
);
1453 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1454 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1455 reg
, pipe_name(pipe
));
1457 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& SDVO_ENABLE
) == 0
1458 && (val
& SDVO_PIPE_B_SELECT
),
1459 "IBX PCH hdmi port still using transcoder B\n");
1462 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1468 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1469 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1470 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1473 val
= I915_READ(reg
);
1474 I915_STATE_WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1475 "PCH VGA enabled on transcoder %c, should be disabled\n",
1479 val
= I915_READ(reg
);
1480 I915_STATE_WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1481 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1484 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1485 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1486 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1489 static void intel_init_dpio(struct drm_device
*dev
)
1491 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1493 if (!IS_VALLEYVIEW(dev
))
1497 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1498 * CHV x1 PHY (DP/HDMI D)
1499 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1501 if (IS_CHERRYVIEW(dev
)) {
1502 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO_2
;
1503 DPIO_PHY_IOSF_PORT(DPIO_PHY1
) = IOSF_PORT_DPIO
;
1505 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO
;
1509 static void vlv_enable_pll(struct intel_crtc
*crtc
,
1510 const struct intel_crtc_state
*pipe_config
)
1512 struct drm_device
*dev
= crtc
->base
.dev
;
1513 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1514 int reg
= DPLL(crtc
->pipe
);
1515 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
1517 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1519 /* No really, not for ILK+ */
1520 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
));
1522 /* PLL is protected by panel, make sure we can write it */
1523 if (IS_MOBILE(dev_priv
->dev
))
1524 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1526 I915_WRITE(reg
, dpll
);
1530 if (wait_for(((I915_READ(reg
) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1531 DRM_ERROR("DPLL %d failed to lock\n", crtc
->pipe
);
1533 I915_WRITE(DPLL_MD(crtc
->pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1534 POSTING_READ(DPLL_MD(crtc
->pipe
));
1536 /* We do this three times for luck */
1537 I915_WRITE(reg
, dpll
);
1539 udelay(150); /* wait for warmup */
1540 I915_WRITE(reg
, dpll
);
1542 udelay(150); /* wait for warmup */
1543 I915_WRITE(reg
, dpll
);
1545 udelay(150); /* wait for warmup */
1548 static void chv_enable_pll(struct intel_crtc
*crtc
,
1549 const struct intel_crtc_state
*pipe_config
)
1551 struct drm_device
*dev
= crtc
->base
.dev
;
1552 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1553 int pipe
= crtc
->pipe
;
1554 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1557 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1559 BUG_ON(!IS_CHERRYVIEW(dev_priv
->dev
));
1561 mutex_lock(&dev_priv
->dpio_lock
);
1563 /* Enable back the 10bit clock to display controller */
1564 tmp
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1565 tmp
|= DPIO_DCLKP_EN
;
1566 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), tmp
);
1569 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1574 I915_WRITE(DPLL(pipe
), pipe_config
->dpll_hw_state
.dpll
);
1576 /* Check PLL is locked */
1577 if (wait_for(((I915_READ(DPLL(pipe
)) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1578 DRM_ERROR("PLL %d failed to lock\n", pipe
);
1580 /* not sure when this should be written */
1581 I915_WRITE(DPLL_MD(pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1582 POSTING_READ(DPLL_MD(pipe
));
1584 mutex_unlock(&dev_priv
->dpio_lock
);
1587 static int intel_num_dvo_pipes(struct drm_device
*dev
)
1589 struct intel_crtc
*crtc
;
1592 for_each_intel_crtc(dev
, crtc
)
1593 count
+= crtc
->active
&&
1594 intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
);
1599 static void i9xx_enable_pll(struct intel_crtc
*crtc
)
1601 struct drm_device
*dev
= crtc
->base
.dev
;
1602 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1603 int reg
= DPLL(crtc
->pipe
);
1604 u32 dpll
= crtc
->config
->dpll_hw_state
.dpll
;
1606 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1608 /* No really, not for ILK+ */
1609 BUG_ON(INTEL_INFO(dev
)->gen
>= 5);
1611 /* PLL is protected by panel, make sure we can write it */
1612 if (IS_MOBILE(dev
) && !IS_I830(dev
))
1613 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1615 /* Enable DVO 2x clock on both PLLs if necessary */
1616 if (IS_I830(dev
) && intel_num_dvo_pipes(dev
) > 0) {
1618 * It appears to be important that we don't enable this
1619 * for the current pipe before otherwise configuring the
1620 * PLL. No idea how this should be handled if multiple
1621 * DVO outputs are enabled simultaneosly.
1623 dpll
|= DPLL_DVO_2X_MODE
;
1624 I915_WRITE(DPLL(!crtc
->pipe
),
1625 I915_READ(DPLL(!crtc
->pipe
)) | DPLL_DVO_2X_MODE
);
1628 /* Wait for the clocks to stabilize. */
1632 if (INTEL_INFO(dev
)->gen
>= 4) {
1633 I915_WRITE(DPLL_MD(crtc
->pipe
),
1634 crtc
->config
->dpll_hw_state
.dpll_md
);
1636 /* The pixel multiplier can only be updated once the
1637 * DPLL is enabled and the clocks are stable.
1639 * So write it again.
1641 I915_WRITE(reg
, dpll
);
1644 /* We do this three times for luck */
1645 I915_WRITE(reg
, dpll
);
1647 udelay(150); /* wait for warmup */
1648 I915_WRITE(reg
, dpll
);
1650 udelay(150); /* wait for warmup */
1651 I915_WRITE(reg
, dpll
);
1653 udelay(150); /* wait for warmup */
1657 * i9xx_disable_pll - disable a PLL
1658 * @dev_priv: i915 private structure
1659 * @pipe: pipe PLL to disable
1661 * Disable the PLL for @pipe, making sure the pipe is off first.
1663 * Note! This is for pre-ILK only.
1665 static void i9xx_disable_pll(struct intel_crtc
*crtc
)
1667 struct drm_device
*dev
= crtc
->base
.dev
;
1668 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1669 enum pipe pipe
= crtc
->pipe
;
1671 /* Disable DVO 2x clock on both PLLs if necessary */
1673 intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
) &&
1674 intel_num_dvo_pipes(dev
) == 1) {
1675 I915_WRITE(DPLL(PIPE_B
),
1676 I915_READ(DPLL(PIPE_B
)) & ~DPLL_DVO_2X_MODE
);
1677 I915_WRITE(DPLL(PIPE_A
),
1678 I915_READ(DPLL(PIPE_A
)) & ~DPLL_DVO_2X_MODE
);
1681 /* Don't disable pipe or pipe PLLs if needed */
1682 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1683 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1686 /* Make sure the pipe isn't still relying on us */
1687 assert_pipe_disabled(dev_priv
, pipe
);
1689 I915_WRITE(DPLL(pipe
), 0);
1690 POSTING_READ(DPLL(pipe
));
1693 static void vlv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1697 /* Make sure the pipe isn't still relying on us */
1698 assert_pipe_disabled(dev_priv
, pipe
);
1701 * Leave integrated clock source and reference clock enabled for pipe B.
1702 * The latter is needed for VGA hotplug / manual detection.
1705 val
= DPLL_INTEGRATED_CRI_CLK_VLV
| DPLL_REFA_CLK_ENABLE_VLV
;
1706 I915_WRITE(DPLL(pipe
), val
);
1707 POSTING_READ(DPLL(pipe
));
1711 static void chv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1713 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1716 /* Make sure the pipe isn't still relying on us */
1717 assert_pipe_disabled(dev_priv
, pipe
);
1719 /* Set PLL en = 0 */
1720 val
= DPLL_SSC_REF_CLOCK_CHV
| DPLL_REFA_CLK_ENABLE_VLV
;
1722 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
1723 I915_WRITE(DPLL(pipe
), val
);
1724 POSTING_READ(DPLL(pipe
));
1726 mutex_lock(&dev_priv
->dpio_lock
);
1728 /* Disable 10bit clock to display controller */
1729 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1730 val
&= ~DPIO_DCLKP_EN
;
1731 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), val
);
1733 /* disable left/right clock distribution */
1734 if (pipe
!= PIPE_B
) {
1735 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
);
1736 val
&= ~(CHV_BUFLEFTENA1_MASK
| CHV_BUFRIGHTENA1_MASK
);
1737 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
, val
);
1739 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
);
1740 val
&= ~(CHV_BUFLEFTENA2_MASK
| CHV_BUFRIGHTENA2_MASK
);
1741 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
, val
);
1744 mutex_unlock(&dev_priv
->dpio_lock
);
1747 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1748 struct intel_digital_port
*dport
)
1753 switch (dport
->port
) {
1755 port_mask
= DPLL_PORTB_READY_MASK
;
1759 port_mask
= DPLL_PORTC_READY_MASK
;
1763 port_mask
= DPLL_PORTD_READY_MASK
;
1764 dpll_reg
= DPIO_PHY_STATUS
;
1770 if (wait_for((I915_READ(dpll_reg
) & port_mask
) == 0, 1000))
1771 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1772 port_name(dport
->port
), I915_READ(dpll_reg
));
1775 static void intel_prepare_shared_dpll(struct intel_crtc
*crtc
)
1777 struct drm_device
*dev
= crtc
->base
.dev
;
1778 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1779 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1781 if (WARN_ON(pll
== NULL
))
1784 WARN_ON(!pll
->config
.crtc_mask
);
1785 if (pll
->active
== 0) {
1786 DRM_DEBUG_DRIVER("setting up %s\n", pll
->name
);
1788 assert_shared_dpll_disabled(dev_priv
, pll
);
1790 pll
->mode_set(dev_priv
, pll
);
1795 * intel_enable_shared_dpll - enable PCH PLL
1796 * @dev_priv: i915 private structure
1797 * @pipe: pipe PLL to enable
1799 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1800 * drives the transcoder clock.
1802 static void intel_enable_shared_dpll(struct intel_crtc
*crtc
)
1804 struct drm_device
*dev
= crtc
->base
.dev
;
1805 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1806 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1808 if (WARN_ON(pll
== NULL
))
1811 if (WARN_ON(pll
->config
.crtc_mask
== 0))
1814 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1815 pll
->name
, pll
->active
, pll
->on
,
1816 crtc
->base
.base
.id
);
1818 if (pll
->active
++) {
1820 assert_shared_dpll_enabled(dev_priv
, pll
);
1825 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
1827 DRM_DEBUG_KMS("enabling %s\n", pll
->name
);
1828 pll
->enable(dev_priv
, pll
);
1832 static void intel_disable_shared_dpll(struct intel_crtc
*crtc
)
1834 struct drm_device
*dev
= crtc
->base
.dev
;
1835 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1836 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1838 /* PCH only available on ILK+ */
1839 BUG_ON(INTEL_INFO(dev
)->gen
< 5);
1840 if (WARN_ON(pll
== NULL
))
1843 if (WARN_ON(pll
->config
.crtc_mask
== 0))
1846 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1847 pll
->name
, pll
->active
, pll
->on
,
1848 crtc
->base
.base
.id
);
1850 if (WARN_ON(pll
->active
== 0)) {
1851 assert_shared_dpll_disabled(dev_priv
, pll
);
1855 assert_shared_dpll_enabled(dev_priv
, pll
);
1860 DRM_DEBUG_KMS("disabling %s\n", pll
->name
);
1861 pll
->disable(dev_priv
, pll
);
1864 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
1867 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1870 struct drm_device
*dev
= dev_priv
->dev
;
1871 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1872 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1873 uint32_t reg
, val
, pipeconf_val
;
1875 /* PCH only available on ILK+ */
1876 BUG_ON(!HAS_PCH_SPLIT(dev
));
1878 /* Make sure PCH DPLL is enabled */
1879 assert_shared_dpll_enabled(dev_priv
,
1880 intel_crtc_to_shared_dpll(intel_crtc
));
1882 /* FDI must be feeding us bits for PCH ports */
1883 assert_fdi_tx_enabled(dev_priv
, pipe
);
1884 assert_fdi_rx_enabled(dev_priv
, pipe
);
1886 if (HAS_PCH_CPT(dev
)) {
1887 /* Workaround: Set the timing override bit before enabling the
1888 * pch transcoder. */
1889 reg
= TRANS_CHICKEN2(pipe
);
1890 val
= I915_READ(reg
);
1891 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1892 I915_WRITE(reg
, val
);
1895 reg
= PCH_TRANSCONF(pipe
);
1896 val
= I915_READ(reg
);
1897 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1899 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1901 * make the BPC in transcoder be consistent with
1902 * that in pipeconf reg.
1904 val
&= ~PIPECONF_BPC_MASK
;
1905 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
1908 val
&= ~TRANS_INTERLACE_MASK
;
1909 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1910 if (HAS_PCH_IBX(dev_priv
->dev
) &&
1911 intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
1912 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1914 val
|= TRANS_INTERLACED
;
1916 val
|= TRANS_PROGRESSIVE
;
1918 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1919 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1920 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
1923 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1924 enum transcoder cpu_transcoder
)
1926 u32 val
, pipeconf_val
;
1928 /* PCH only available on ILK+ */
1929 BUG_ON(!HAS_PCH_SPLIT(dev_priv
->dev
));
1931 /* FDI must be feeding us bits for PCH ports */
1932 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
1933 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
1935 /* Workaround: set timing override bit. */
1936 val
= I915_READ(_TRANSA_CHICKEN2
);
1937 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1938 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1941 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
1943 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
1944 PIPECONF_INTERLACED_ILK
)
1945 val
|= TRANS_INTERLACED
;
1947 val
|= TRANS_PROGRESSIVE
;
1949 I915_WRITE(LPT_TRANSCONF
, val
);
1950 if (wait_for(I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
, 100))
1951 DRM_ERROR("Failed to enable PCH transcoder\n");
1954 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1957 struct drm_device
*dev
= dev_priv
->dev
;
1960 /* FDI relies on the transcoder */
1961 assert_fdi_tx_disabled(dev_priv
, pipe
);
1962 assert_fdi_rx_disabled(dev_priv
, pipe
);
1964 /* Ports must be off as well */
1965 assert_pch_ports_disabled(dev_priv
, pipe
);
1967 reg
= PCH_TRANSCONF(pipe
);
1968 val
= I915_READ(reg
);
1969 val
&= ~TRANS_ENABLE
;
1970 I915_WRITE(reg
, val
);
1971 /* wait for PCH transcoder off, transcoder state */
1972 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
1973 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
1975 if (!HAS_PCH_IBX(dev
)) {
1976 /* Workaround: Clear the timing override chicken bit again. */
1977 reg
= TRANS_CHICKEN2(pipe
);
1978 val
= I915_READ(reg
);
1979 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1980 I915_WRITE(reg
, val
);
1984 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
1988 val
= I915_READ(LPT_TRANSCONF
);
1989 val
&= ~TRANS_ENABLE
;
1990 I915_WRITE(LPT_TRANSCONF
, val
);
1991 /* wait for PCH transcoder off, transcoder state */
1992 if (wait_for((I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
) == 0, 50))
1993 DRM_ERROR("Failed to disable PCH transcoder\n");
1995 /* Workaround: clear timing override bit. */
1996 val
= I915_READ(_TRANSA_CHICKEN2
);
1997 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1998 I915_WRITE(_TRANSA_CHICKEN2
, val
);
2002 * intel_enable_pipe - enable a pipe, asserting requirements
2003 * @crtc: crtc responsible for the pipe
2005 * Enable @crtc's pipe, making sure that various hardware specific requirements
2006 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2008 static void intel_enable_pipe(struct intel_crtc
*crtc
)
2010 struct drm_device
*dev
= crtc
->base
.dev
;
2011 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2012 enum pipe pipe
= crtc
->pipe
;
2013 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
2015 enum pipe pch_transcoder
;
2019 assert_planes_disabled(dev_priv
, pipe
);
2020 assert_cursor_disabled(dev_priv
, pipe
);
2021 assert_sprites_disabled(dev_priv
, pipe
);
2023 if (HAS_PCH_LPT(dev_priv
->dev
))
2024 pch_transcoder
= TRANSCODER_A
;
2026 pch_transcoder
= pipe
;
2029 * A pipe without a PLL won't actually be able to drive bits from
2030 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2033 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
2034 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
))
2035 assert_dsi_pll_enabled(dev_priv
);
2037 assert_pll_enabled(dev_priv
, pipe
);
2039 if (crtc
->config
->has_pch_encoder
) {
2040 /* if driving the PCH, we need FDI enabled */
2041 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
2042 assert_fdi_tx_pll_enabled(dev_priv
,
2043 (enum pipe
) cpu_transcoder
);
2045 /* FIXME: assert CPU port conditions for SNB+ */
2048 reg
= PIPECONF(cpu_transcoder
);
2049 val
= I915_READ(reg
);
2050 if (val
& PIPECONF_ENABLE
) {
2051 WARN_ON(!((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
2052 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
)));
2056 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
2061 * intel_disable_pipe - disable a pipe, asserting requirements
2062 * @crtc: crtc whose pipes is to be disabled
2064 * Disable the pipe of @crtc, making sure that various hardware
2065 * specific requirements are met, if applicable, e.g. plane
2066 * disabled, panel fitter off, etc.
2068 * Will wait until the pipe has shut down before returning.
2070 static void intel_disable_pipe(struct intel_crtc
*crtc
)
2072 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
2073 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
2074 enum pipe pipe
= crtc
->pipe
;
2079 * Make sure planes won't keep trying to pump pixels to us,
2080 * or we might hang the display.
2082 assert_planes_disabled(dev_priv
, pipe
);
2083 assert_cursor_disabled(dev_priv
, pipe
);
2084 assert_sprites_disabled(dev_priv
, pipe
);
2086 reg
= PIPECONF(cpu_transcoder
);
2087 val
= I915_READ(reg
);
2088 if ((val
& PIPECONF_ENABLE
) == 0)
2092 * Double wide has implications for planes
2093 * so best keep it disabled when not needed.
2095 if (crtc
->config
->double_wide
)
2096 val
&= ~PIPECONF_DOUBLE_WIDE
;
2098 /* Don't disable pipe or pipe PLLs if needed */
2099 if (!(pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) &&
2100 !(pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
2101 val
&= ~PIPECONF_ENABLE
;
2103 I915_WRITE(reg
, val
);
2104 if ((val
& PIPECONF_ENABLE
) == 0)
2105 intel_wait_for_pipe_off(crtc
);
2109 * Plane regs are double buffered, going from enabled->disabled needs a
2110 * trigger in order to latch. The display address reg provides this.
2112 void intel_flush_primary_plane(struct drm_i915_private
*dev_priv
,
2115 struct drm_device
*dev
= dev_priv
->dev
;
2116 u32 reg
= INTEL_INFO(dev
)->gen
>= 4 ? DSPSURF(plane
) : DSPADDR(plane
);
2118 I915_WRITE(reg
, I915_READ(reg
));
2123 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2124 * @plane: plane to be enabled
2125 * @crtc: crtc for the plane
2127 * Enable @plane on @crtc, making sure that the pipe is running first.
2129 static void intel_enable_primary_hw_plane(struct drm_plane
*plane
,
2130 struct drm_crtc
*crtc
)
2132 struct drm_device
*dev
= plane
->dev
;
2133 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2134 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2136 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2137 assert_pipe_enabled(dev_priv
, intel_crtc
->pipe
);
2139 if (intel_crtc
->primary_enabled
)
2142 intel_crtc
->primary_enabled
= true;
2144 dev_priv
->display
.update_primary_plane(crtc
, plane
->fb
,
2148 * BDW signals flip done immediately if the plane
2149 * is disabled, even if the plane enable is already
2150 * armed to occur at the next vblank :(
2152 if (IS_BROADWELL(dev
))
2153 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2157 * intel_disable_primary_hw_plane - disable the primary hardware plane
2158 * @plane: plane to be disabled
2159 * @crtc: crtc for the plane
2161 * Disable @plane on @crtc, making sure that the pipe is running first.
2163 static void intel_disable_primary_hw_plane(struct drm_plane
*plane
,
2164 struct drm_crtc
*crtc
)
2166 struct drm_device
*dev
= plane
->dev
;
2167 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2168 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2170 if (WARN_ON(!intel_crtc
->active
))
2173 if (!intel_crtc
->primary_enabled
)
2176 intel_crtc
->primary_enabled
= false;
2178 dev_priv
->display
.update_primary_plane(crtc
, plane
->fb
,
2182 static bool need_vtd_wa(struct drm_device
*dev
)
2184 #ifdef CONFIG_INTEL_IOMMU
2185 if (INTEL_INFO(dev
)->gen
>= 6 && intel_iommu_gfx_mapped
)
2191 static int intel_align_height(struct drm_device
*dev
, int height
, bool tiled
)
2195 tile_height
= tiled
? (IS_GEN2(dev
) ? 16 : 8) : 1;
2196 return ALIGN(height
, tile_height
);
2200 intel_pin_and_fence_fb_obj(struct drm_plane
*plane
,
2201 struct drm_framebuffer
*fb
,
2202 struct intel_engine_cs
*pipelined
)
2204 struct drm_device
*dev
= fb
->dev
;
2205 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2206 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2210 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
2212 switch (obj
->tiling_mode
) {
2213 case I915_TILING_NONE
:
2214 if (INTEL_INFO(dev
)->gen
>= 9)
2215 alignment
= 256 * 1024;
2216 else if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
2217 alignment
= 128 * 1024;
2218 else if (INTEL_INFO(dev
)->gen
>= 4)
2219 alignment
= 4 * 1024;
2221 alignment
= 64 * 1024;
2224 if (INTEL_INFO(dev
)->gen
>= 9)
2225 alignment
= 256 * 1024;
2227 /* pin() will align the object as required by fence */
2232 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2238 /* Note that the w/a also requires 64 PTE of padding following the
2239 * bo. We currently fill all unused PTE with the shadow page and so
2240 * we should always have valid PTE following the scanout preventing
2243 if (need_vtd_wa(dev
) && alignment
< 256 * 1024)
2244 alignment
= 256 * 1024;
2247 * Global gtt pte registers are special registers which actually forward
2248 * writes to a chunk of system memory. Which means that there is no risk
2249 * that the register values disappear as soon as we call
2250 * intel_runtime_pm_put(), so it is correct to wrap only the
2251 * pin/unpin/fence and not more.
2253 intel_runtime_pm_get(dev_priv
);
2255 dev_priv
->mm
.interruptible
= false;
2256 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
);
2258 goto err_interruptible
;
2260 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2261 * fence, whereas 965+ only requires a fence if using
2262 * framebuffer compression. For simplicity, we always install
2263 * a fence as the cost is not that onerous.
2265 ret
= i915_gem_object_get_fence(obj
);
2269 i915_gem_object_pin_fence(obj
);
2271 dev_priv
->mm
.interruptible
= true;
2272 intel_runtime_pm_put(dev_priv
);
2276 i915_gem_object_unpin_from_display_plane(obj
);
2278 dev_priv
->mm
.interruptible
= true;
2279 intel_runtime_pm_put(dev_priv
);
2283 void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
)
2285 WARN_ON(!mutex_is_locked(&obj
->base
.dev
->struct_mutex
));
2287 i915_gem_object_unpin_fence(obj
);
2288 i915_gem_object_unpin_from_display_plane(obj
);
2291 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2292 * is assumed to be a power-of-two. */
2293 unsigned long intel_gen4_compute_page_offset(int *x
, int *y
,
2294 unsigned int tiling_mode
,
2298 if (tiling_mode
!= I915_TILING_NONE
) {
2299 unsigned int tile_rows
, tiles
;
2304 tiles
= *x
/ (512/cpp
);
2307 return tile_rows
* pitch
* 8 + tiles
* 4096;
2309 unsigned int offset
;
2311 offset
= *y
* pitch
+ *x
* cpp
;
2313 *x
= (offset
& 4095) / cpp
;
2314 return offset
& -4096;
2318 int intel_format_to_fourcc(int format
)
2321 case DISPPLANE_8BPP
:
2322 return DRM_FORMAT_C8
;
2323 case DISPPLANE_BGRX555
:
2324 return DRM_FORMAT_XRGB1555
;
2325 case DISPPLANE_BGRX565
:
2326 return DRM_FORMAT_RGB565
;
2328 case DISPPLANE_BGRX888
:
2329 return DRM_FORMAT_XRGB8888
;
2330 case DISPPLANE_RGBX888
:
2331 return DRM_FORMAT_XBGR8888
;
2332 case DISPPLANE_BGRX101010
:
2333 return DRM_FORMAT_XRGB2101010
;
2334 case DISPPLANE_RGBX101010
:
2335 return DRM_FORMAT_XBGR2101010
;
2339 static bool intel_alloc_plane_obj(struct intel_crtc
*crtc
,
2340 struct intel_plane_config
*plane_config
)
2342 struct drm_device
*dev
= crtc
->base
.dev
;
2343 struct drm_i915_gem_object
*obj
= NULL
;
2344 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
2345 u32 base
= plane_config
->base
;
2347 if (plane_config
->size
== 0)
2350 obj
= i915_gem_object_create_stolen_for_preallocated(dev
, base
, base
,
2351 plane_config
->size
);
2355 obj
->tiling_mode
= plane_config
->tiling
;
2356 if (obj
->tiling_mode
== I915_TILING_X
)
2357 obj
->stride
= crtc
->base
.primary
->fb
->pitches
[0];
2359 mode_cmd
.pixel_format
= crtc
->base
.primary
->fb
->pixel_format
;
2360 mode_cmd
.width
= crtc
->base
.primary
->fb
->width
;
2361 mode_cmd
.height
= crtc
->base
.primary
->fb
->height
;
2362 mode_cmd
.pitches
[0] = crtc
->base
.primary
->fb
->pitches
[0];
2364 mutex_lock(&dev
->struct_mutex
);
2366 if (intel_framebuffer_init(dev
, to_intel_framebuffer(crtc
->base
.primary
->fb
),
2368 DRM_DEBUG_KMS("intel fb init failed\n");
2372 obj
->frontbuffer_bits
= INTEL_FRONTBUFFER_PRIMARY(crtc
->pipe
);
2373 mutex_unlock(&dev
->struct_mutex
);
2375 DRM_DEBUG_KMS("plane fb obj %p\n", obj
);
2379 drm_gem_object_unreference(&obj
->base
);
2380 mutex_unlock(&dev
->struct_mutex
);
2384 static void intel_find_plane_obj(struct intel_crtc
*intel_crtc
,
2385 struct intel_plane_config
*plane_config
)
2387 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2388 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2390 struct intel_crtc
*i
;
2391 struct drm_i915_gem_object
*obj
;
2393 if (!intel_crtc
->base
.primary
->fb
)
2396 if (intel_alloc_plane_obj(intel_crtc
, plane_config
))
2399 kfree(intel_crtc
->base
.primary
->fb
);
2400 intel_crtc
->base
.primary
->fb
= NULL
;
2403 * Failed to alloc the obj, check to see if we should share
2404 * an fb with another CRTC instead
2406 for_each_crtc(dev
, c
) {
2407 i
= to_intel_crtc(c
);
2409 if (c
== &intel_crtc
->base
)
2415 obj
= intel_fb_obj(c
->primary
->fb
);
2419 if (i915_gem_obj_ggtt_offset(obj
) == plane_config
->base
) {
2420 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2421 dev_priv
->preserve_bios_swizzle
= true;
2423 drm_framebuffer_reference(c
->primary
->fb
);
2424 intel_crtc
->base
.primary
->fb
= c
->primary
->fb
;
2425 obj
->frontbuffer_bits
|= INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
);
2431 static void i9xx_update_primary_plane(struct drm_crtc
*crtc
,
2432 struct drm_framebuffer
*fb
,
2435 struct drm_device
*dev
= crtc
->dev
;
2436 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2437 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2438 struct drm_i915_gem_object
*obj
;
2439 int plane
= intel_crtc
->plane
;
2440 unsigned long linear_offset
;
2442 u32 reg
= DSPCNTR(plane
);
2445 if (!intel_crtc
->primary_enabled
) {
2447 if (INTEL_INFO(dev
)->gen
>= 4)
2448 I915_WRITE(DSPSURF(plane
), 0);
2450 I915_WRITE(DSPADDR(plane
), 0);
2455 obj
= intel_fb_obj(fb
);
2456 if (WARN_ON(obj
== NULL
))
2459 pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2461 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2463 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2465 if (INTEL_INFO(dev
)->gen
< 4) {
2466 if (intel_crtc
->pipe
== PIPE_B
)
2467 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
2469 /* pipesrc and dspsize control the size that is scaled from,
2470 * which should always be the user's requested size.
2472 I915_WRITE(DSPSIZE(plane
),
2473 ((intel_crtc
->config
->pipe_src_h
- 1) << 16) |
2474 (intel_crtc
->config
->pipe_src_w
- 1));
2475 I915_WRITE(DSPPOS(plane
), 0);
2476 } else if (IS_CHERRYVIEW(dev
) && plane
== PLANE_B
) {
2477 I915_WRITE(PRIMSIZE(plane
),
2478 ((intel_crtc
->config
->pipe_src_h
- 1) << 16) |
2479 (intel_crtc
->config
->pipe_src_w
- 1));
2480 I915_WRITE(PRIMPOS(plane
), 0);
2481 I915_WRITE(PRIMCNSTALPHA(plane
), 0);
2484 switch (fb
->pixel_format
) {
2486 dspcntr
|= DISPPLANE_8BPP
;
2488 case DRM_FORMAT_XRGB1555
:
2489 case DRM_FORMAT_ARGB1555
:
2490 dspcntr
|= DISPPLANE_BGRX555
;
2492 case DRM_FORMAT_RGB565
:
2493 dspcntr
|= DISPPLANE_BGRX565
;
2495 case DRM_FORMAT_XRGB8888
:
2496 case DRM_FORMAT_ARGB8888
:
2497 dspcntr
|= DISPPLANE_BGRX888
;
2499 case DRM_FORMAT_XBGR8888
:
2500 case DRM_FORMAT_ABGR8888
:
2501 dspcntr
|= DISPPLANE_RGBX888
;
2503 case DRM_FORMAT_XRGB2101010
:
2504 case DRM_FORMAT_ARGB2101010
:
2505 dspcntr
|= DISPPLANE_BGRX101010
;
2507 case DRM_FORMAT_XBGR2101010
:
2508 case DRM_FORMAT_ABGR2101010
:
2509 dspcntr
|= DISPPLANE_RGBX101010
;
2515 if (INTEL_INFO(dev
)->gen
>= 4 &&
2516 obj
->tiling_mode
!= I915_TILING_NONE
)
2517 dspcntr
|= DISPPLANE_TILED
;
2520 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2522 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
2524 if (INTEL_INFO(dev
)->gen
>= 4) {
2525 intel_crtc
->dspaddr_offset
=
2526 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2529 linear_offset
-= intel_crtc
->dspaddr_offset
;
2531 intel_crtc
->dspaddr_offset
= linear_offset
;
2534 if (to_intel_plane(crtc
->primary
)->rotation
== BIT(DRM_ROTATE_180
)) {
2535 dspcntr
|= DISPPLANE_ROTATE_180
;
2537 x
+= (intel_crtc
->config
->pipe_src_w
- 1);
2538 y
+= (intel_crtc
->config
->pipe_src_h
- 1);
2540 /* Finding the last pixel of the last line of the display
2541 data and adding to linear_offset*/
2543 (intel_crtc
->config
->pipe_src_h
- 1) * fb
->pitches
[0] +
2544 (intel_crtc
->config
->pipe_src_w
- 1) * pixel_size
;
2547 I915_WRITE(reg
, dspcntr
);
2549 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2550 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2552 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2553 if (INTEL_INFO(dev
)->gen
>= 4) {
2554 I915_WRITE(DSPSURF(plane
),
2555 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2556 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2557 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2559 I915_WRITE(DSPADDR(plane
), i915_gem_obj_ggtt_offset(obj
) + linear_offset
);
2563 static void ironlake_update_primary_plane(struct drm_crtc
*crtc
,
2564 struct drm_framebuffer
*fb
,
2567 struct drm_device
*dev
= crtc
->dev
;
2568 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2569 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2570 struct drm_i915_gem_object
*obj
;
2571 int plane
= intel_crtc
->plane
;
2572 unsigned long linear_offset
;
2574 u32 reg
= DSPCNTR(plane
);
2577 if (!intel_crtc
->primary_enabled
) {
2579 I915_WRITE(DSPSURF(plane
), 0);
2584 obj
= intel_fb_obj(fb
);
2585 if (WARN_ON(obj
== NULL
))
2588 pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2590 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2592 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2594 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2595 dspcntr
|= DISPPLANE_PIPE_CSC_ENABLE
;
2597 switch (fb
->pixel_format
) {
2599 dspcntr
|= DISPPLANE_8BPP
;
2601 case DRM_FORMAT_RGB565
:
2602 dspcntr
|= DISPPLANE_BGRX565
;
2604 case DRM_FORMAT_XRGB8888
:
2605 case DRM_FORMAT_ARGB8888
:
2606 dspcntr
|= DISPPLANE_BGRX888
;
2608 case DRM_FORMAT_XBGR8888
:
2609 case DRM_FORMAT_ABGR8888
:
2610 dspcntr
|= DISPPLANE_RGBX888
;
2612 case DRM_FORMAT_XRGB2101010
:
2613 case DRM_FORMAT_ARGB2101010
:
2614 dspcntr
|= DISPPLANE_BGRX101010
;
2616 case DRM_FORMAT_XBGR2101010
:
2617 case DRM_FORMAT_ABGR2101010
:
2618 dspcntr
|= DISPPLANE_RGBX101010
;
2624 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2625 dspcntr
|= DISPPLANE_TILED
;
2627 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
))
2628 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2630 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
2631 intel_crtc
->dspaddr_offset
=
2632 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2635 linear_offset
-= intel_crtc
->dspaddr_offset
;
2636 if (to_intel_plane(crtc
->primary
)->rotation
== BIT(DRM_ROTATE_180
)) {
2637 dspcntr
|= DISPPLANE_ROTATE_180
;
2639 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
)) {
2640 x
+= (intel_crtc
->config
->pipe_src_w
- 1);
2641 y
+= (intel_crtc
->config
->pipe_src_h
- 1);
2643 /* Finding the last pixel of the last line of the display
2644 data and adding to linear_offset*/
2646 (intel_crtc
->config
->pipe_src_h
- 1) * fb
->pitches
[0] +
2647 (intel_crtc
->config
->pipe_src_w
- 1) * pixel_size
;
2651 I915_WRITE(reg
, dspcntr
);
2653 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2654 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2656 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2657 I915_WRITE(DSPSURF(plane
),
2658 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2659 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2660 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2662 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2663 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2668 static void skylake_update_primary_plane(struct drm_crtc
*crtc
,
2669 struct drm_framebuffer
*fb
,
2672 struct drm_device
*dev
= crtc
->dev
;
2673 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2674 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2675 struct intel_framebuffer
*intel_fb
;
2676 struct drm_i915_gem_object
*obj
;
2677 int pipe
= intel_crtc
->pipe
;
2678 u32 plane_ctl
, stride
;
2680 if (!intel_crtc
->primary_enabled
) {
2681 I915_WRITE(PLANE_CTL(pipe
, 0), 0);
2682 I915_WRITE(PLANE_SURF(pipe
, 0), 0);
2683 POSTING_READ(PLANE_CTL(pipe
, 0));
2687 plane_ctl
= PLANE_CTL_ENABLE
|
2688 PLANE_CTL_PIPE_GAMMA_ENABLE
|
2689 PLANE_CTL_PIPE_CSC_ENABLE
;
2691 switch (fb
->pixel_format
) {
2692 case DRM_FORMAT_RGB565
:
2693 plane_ctl
|= PLANE_CTL_FORMAT_RGB_565
;
2695 case DRM_FORMAT_XRGB8888
:
2696 plane_ctl
|= PLANE_CTL_FORMAT_XRGB_8888
;
2698 case DRM_FORMAT_XBGR8888
:
2699 plane_ctl
|= PLANE_CTL_ORDER_RGBX
;
2700 plane_ctl
|= PLANE_CTL_FORMAT_XRGB_8888
;
2702 case DRM_FORMAT_XRGB2101010
:
2703 plane_ctl
|= PLANE_CTL_FORMAT_XRGB_2101010
;
2705 case DRM_FORMAT_XBGR2101010
:
2706 plane_ctl
|= PLANE_CTL_ORDER_RGBX
;
2707 plane_ctl
|= PLANE_CTL_FORMAT_XRGB_2101010
;
2713 intel_fb
= to_intel_framebuffer(fb
);
2714 obj
= intel_fb
->obj
;
2717 * The stride is either expressed as a multiple of 64 bytes chunks for
2718 * linear buffers or in number of tiles for tiled buffers.
2720 switch (obj
->tiling_mode
) {
2721 case I915_TILING_NONE
:
2722 stride
= fb
->pitches
[0] >> 6;
2725 plane_ctl
|= PLANE_CTL_TILED_X
;
2726 stride
= fb
->pitches
[0] >> 9;
2732 plane_ctl
|= PLANE_CTL_PLANE_GAMMA_DISABLE
;
2733 if (to_intel_plane(crtc
->primary
)->rotation
== BIT(DRM_ROTATE_180
))
2734 plane_ctl
|= PLANE_CTL_ROTATE_180
;
2736 I915_WRITE(PLANE_CTL(pipe
, 0), plane_ctl
);
2738 DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2739 i915_gem_obj_ggtt_offset(obj
),
2740 x
, y
, fb
->width
, fb
->height
,
2743 I915_WRITE(PLANE_POS(pipe
, 0), 0);
2744 I915_WRITE(PLANE_OFFSET(pipe
, 0), (y
<< 16) | x
);
2745 I915_WRITE(PLANE_SIZE(pipe
, 0),
2746 (intel_crtc
->config
->pipe_src_h
- 1) << 16 |
2747 (intel_crtc
->config
->pipe_src_w
- 1));
2748 I915_WRITE(PLANE_STRIDE(pipe
, 0), stride
);
2749 I915_WRITE(PLANE_SURF(pipe
, 0), i915_gem_obj_ggtt_offset(obj
));
2751 POSTING_READ(PLANE_SURF(pipe
, 0));
2754 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2756 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2757 int x
, int y
, enum mode_set_atomic state
)
2759 struct drm_device
*dev
= crtc
->dev
;
2760 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2762 if (dev_priv
->display
.disable_fbc
)
2763 dev_priv
->display
.disable_fbc(dev
);
2765 dev_priv
->display
.update_primary_plane(crtc
, fb
, x
, y
);
2770 static void intel_complete_page_flips(struct drm_device
*dev
)
2772 struct drm_crtc
*crtc
;
2774 for_each_crtc(dev
, crtc
) {
2775 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2776 enum plane plane
= intel_crtc
->plane
;
2778 intel_prepare_page_flip(dev
, plane
);
2779 intel_finish_page_flip_plane(dev
, plane
);
2783 static void intel_update_primary_planes(struct drm_device
*dev
)
2785 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2786 struct drm_crtc
*crtc
;
2788 for_each_crtc(dev
, crtc
) {
2789 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2791 drm_modeset_lock(&crtc
->mutex
, NULL
);
2793 * FIXME: Once we have proper support for primary planes (and
2794 * disabling them without disabling the entire crtc) allow again
2795 * a NULL crtc->primary->fb.
2797 if (intel_crtc
->active
&& crtc
->primary
->fb
)
2798 dev_priv
->display
.update_primary_plane(crtc
,
2802 drm_modeset_unlock(&crtc
->mutex
);
2806 void intel_prepare_reset(struct drm_device
*dev
)
2808 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2809 struct intel_crtc
*crtc
;
2811 /* no reset support for gen2 */
2815 /* reset doesn't touch the display */
2816 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
2819 drm_modeset_lock_all(dev
);
2822 * Disabling the crtcs gracefully seems nicer. Also the
2823 * g33 docs say we should at least disable all the planes.
2825 for_each_intel_crtc(dev
, crtc
) {
2827 dev_priv
->display
.crtc_disable(&crtc
->base
);
2831 void intel_finish_reset(struct drm_device
*dev
)
2833 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2836 * Flips in the rings will be nuked by the reset,
2837 * so complete all pending flips so that user space
2838 * will get its events and not get stuck.
2840 intel_complete_page_flips(dev
);
2842 /* no reset support for gen2 */
2846 /* reset doesn't touch the display */
2847 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
)) {
2849 * Flips in the rings have been nuked by the reset,
2850 * so update the base address of all primary
2851 * planes to the the last fb to make sure we're
2852 * showing the correct fb after a reset.
2854 intel_update_primary_planes(dev
);
2859 * The display has been reset as well,
2860 * so need a full re-initialization.
2862 intel_runtime_pm_disable_interrupts(dev_priv
);
2863 intel_runtime_pm_enable_interrupts(dev_priv
);
2865 intel_modeset_init_hw(dev
);
2867 spin_lock_irq(&dev_priv
->irq_lock
);
2868 if (dev_priv
->display
.hpd_irq_setup
)
2869 dev_priv
->display
.hpd_irq_setup(dev
);
2870 spin_unlock_irq(&dev_priv
->irq_lock
);
2872 intel_modeset_setup_hw_state(dev
, true);
2874 intel_hpd_init(dev_priv
);
2876 drm_modeset_unlock_all(dev
);
2880 intel_finish_fb(struct drm_framebuffer
*old_fb
)
2882 struct drm_i915_gem_object
*obj
= intel_fb_obj(old_fb
);
2883 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2884 bool was_interruptible
= dev_priv
->mm
.interruptible
;
2887 /* Big Hammer, we also need to ensure that any pending
2888 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2889 * current scanout is retired before unpinning the old
2892 * This should only fail upon a hung GPU, in which case we
2893 * can safely continue.
2895 dev_priv
->mm
.interruptible
= false;
2896 ret
= i915_gem_object_finish_gpu(obj
);
2897 dev_priv
->mm
.interruptible
= was_interruptible
;
2902 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
2904 struct drm_device
*dev
= crtc
->dev
;
2905 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2906 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2909 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
2910 intel_crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
2913 spin_lock_irq(&dev
->event_lock
);
2914 pending
= to_intel_crtc(crtc
)->unpin_work
!= NULL
;
2915 spin_unlock_irq(&dev
->event_lock
);
2920 static void intel_update_pipe_size(struct intel_crtc
*crtc
)
2922 struct drm_device
*dev
= crtc
->base
.dev
;
2923 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2924 const struct drm_display_mode
*adjusted_mode
;
2930 * Update pipe size and adjust fitter if needed: the reason for this is
2931 * that in compute_mode_changes we check the native mode (not the pfit
2932 * mode) to see if we can flip rather than do a full mode set. In the
2933 * fastboot case, we'll flip, but if we don't update the pipesrc and
2934 * pfit state, we'll end up with a big fb scanned out into the wrong
2937 * To fix this properly, we need to hoist the checks up into
2938 * compute_mode_changes (or above), check the actual pfit state and
2939 * whether the platform allows pfit disable with pipe active, and only
2940 * then update the pipesrc and pfit state, even on the flip path.
2943 adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
2945 I915_WRITE(PIPESRC(crtc
->pipe
),
2946 ((adjusted_mode
->crtc_hdisplay
- 1) << 16) |
2947 (adjusted_mode
->crtc_vdisplay
- 1));
2948 if (!crtc
->config
->pch_pfit
.enabled
&&
2949 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) ||
2950 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
2951 I915_WRITE(PF_CTL(crtc
->pipe
), 0);
2952 I915_WRITE(PF_WIN_POS(crtc
->pipe
), 0);
2953 I915_WRITE(PF_WIN_SZ(crtc
->pipe
), 0);
2955 crtc
->config
->pipe_src_w
= adjusted_mode
->crtc_hdisplay
;
2956 crtc
->config
->pipe_src_h
= adjusted_mode
->crtc_vdisplay
;
2959 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
2961 struct drm_device
*dev
= crtc
->dev
;
2962 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2963 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2964 int pipe
= intel_crtc
->pipe
;
2967 /* enable normal train */
2968 reg
= FDI_TX_CTL(pipe
);
2969 temp
= I915_READ(reg
);
2970 if (IS_IVYBRIDGE(dev
)) {
2971 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2972 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2974 temp
&= ~FDI_LINK_TRAIN_NONE
;
2975 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2977 I915_WRITE(reg
, temp
);
2979 reg
= FDI_RX_CTL(pipe
);
2980 temp
= I915_READ(reg
);
2981 if (HAS_PCH_CPT(dev
)) {
2982 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2983 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
2985 temp
&= ~FDI_LINK_TRAIN_NONE
;
2986 temp
|= FDI_LINK_TRAIN_NONE
;
2988 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
2990 /* wait one idle pattern time */
2994 /* IVB wants error correction enabled */
2995 if (IS_IVYBRIDGE(dev
))
2996 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
2997 FDI_FE_ERRC_ENABLE
);
3000 static bool pipe_has_enabled_pch(struct intel_crtc
*crtc
)
3002 return crtc
->base
.enabled
&& crtc
->active
&&
3003 crtc
->config
->has_pch_encoder
;
3006 static void ivb_modeset_global_resources(struct drm_device
*dev
)
3008 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3009 struct intel_crtc
*pipe_B_crtc
=
3010 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
3011 struct intel_crtc
*pipe_C_crtc
=
3012 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]);
3016 * When everything is off disable fdi C so that we could enable fdi B
3017 * with all lanes. Note that we don't care about enabled pipes without
3018 * an enabled pch encoder.
3020 if (!pipe_has_enabled_pch(pipe_B_crtc
) &&
3021 !pipe_has_enabled_pch(pipe_C_crtc
)) {
3022 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
3023 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
3025 temp
= I915_READ(SOUTH_CHICKEN1
);
3026 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
3027 DRM_DEBUG_KMS("disabling fdi C rx\n");
3028 I915_WRITE(SOUTH_CHICKEN1
, temp
);
3032 /* The FDI link training functions for ILK/Ibexpeak. */
3033 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
3035 struct drm_device
*dev
= crtc
->dev
;
3036 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3037 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3038 int pipe
= intel_crtc
->pipe
;
3039 u32 reg
, temp
, tries
;
3041 /* FDI needs bits from pipe first */
3042 assert_pipe_enabled(dev_priv
, pipe
);
3044 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3046 reg
= FDI_RX_IMR(pipe
);
3047 temp
= I915_READ(reg
);
3048 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3049 temp
&= ~FDI_RX_BIT_LOCK
;
3050 I915_WRITE(reg
, temp
);
3054 /* enable CPU FDI TX and PCH FDI RX */
3055 reg
= FDI_TX_CTL(pipe
);
3056 temp
= I915_READ(reg
);
3057 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3058 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3059 temp
&= ~FDI_LINK_TRAIN_NONE
;
3060 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3061 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3063 reg
= FDI_RX_CTL(pipe
);
3064 temp
= I915_READ(reg
);
3065 temp
&= ~FDI_LINK_TRAIN_NONE
;
3066 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3067 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3072 /* Ironlake workaround, enable clock pointer after FDI enable*/
3073 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3074 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
3075 FDI_RX_PHASE_SYNC_POINTER_EN
);
3077 reg
= FDI_RX_IIR(pipe
);
3078 for (tries
= 0; tries
< 5; tries
++) {
3079 temp
= I915_READ(reg
);
3080 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3082 if ((temp
& FDI_RX_BIT_LOCK
)) {
3083 DRM_DEBUG_KMS("FDI train 1 done.\n");
3084 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3089 DRM_ERROR("FDI train 1 fail!\n");
3092 reg
= FDI_TX_CTL(pipe
);
3093 temp
= I915_READ(reg
);
3094 temp
&= ~FDI_LINK_TRAIN_NONE
;
3095 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3096 I915_WRITE(reg
, temp
);
3098 reg
= FDI_RX_CTL(pipe
);
3099 temp
= I915_READ(reg
);
3100 temp
&= ~FDI_LINK_TRAIN_NONE
;
3101 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3102 I915_WRITE(reg
, temp
);
3107 reg
= FDI_RX_IIR(pipe
);
3108 for (tries
= 0; tries
< 5; tries
++) {
3109 temp
= I915_READ(reg
);
3110 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3112 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3113 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3114 DRM_DEBUG_KMS("FDI train 2 done.\n");
3119 DRM_ERROR("FDI train 2 fail!\n");
3121 DRM_DEBUG_KMS("FDI train done\n");
3125 static const int snb_b_fdi_train_param
[] = {
3126 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
3127 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
3128 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
3129 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
3132 /* The FDI link training functions for SNB/Cougarpoint. */
3133 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
3135 struct drm_device
*dev
= crtc
->dev
;
3136 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3137 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3138 int pipe
= intel_crtc
->pipe
;
3139 u32 reg
, temp
, i
, retry
;
3141 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3143 reg
= FDI_RX_IMR(pipe
);
3144 temp
= I915_READ(reg
);
3145 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3146 temp
&= ~FDI_RX_BIT_LOCK
;
3147 I915_WRITE(reg
, temp
);
3152 /* enable CPU FDI TX and PCH FDI RX */
3153 reg
= FDI_TX_CTL(pipe
);
3154 temp
= I915_READ(reg
);
3155 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3156 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3157 temp
&= ~FDI_LINK_TRAIN_NONE
;
3158 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3159 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3161 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3162 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3164 I915_WRITE(FDI_RX_MISC(pipe
),
3165 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3167 reg
= FDI_RX_CTL(pipe
);
3168 temp
= I915_READ(reg
);
3169 if (HAS_PCH_CPT(dev
)) {
3170 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3171 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3173 temp
&= ~FDI_LINK_TRAIN_NONE
;
3174 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3176 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3181 for (i
= 0; i
< 4; i
++) {
3182 reg
= FDI_TX_CTL(pipe
);
3183 temp
= I915_READ(reg
);
3184 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3185 temp
|= snb_b_fdi_train_param
[i
];
3186 I915_WRITE(reg
, temp
);
3191 for (retry
= 0; retry
< 5; retry
++) {
3192 reg
= FDI_RX_IIR(pipe
);
3193 temp
= I915_READ(reg
);
3194 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3195 if (temp
& FDI_RX_BIT_LOCK
) {
3196 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3197 DRM_DEBUG_KMS("FDI train 1 done.\n");
3206 DRM_ERROR("FDI train 1 fail!\n");
3209 reg
= FDI_TX_CTL(pipe
);
3210 temp
= I915_READ(reg
);
3211 temp
&= ~FDI_LINK_TRAIN_NONE
;
3212 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3214 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3216 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3218 I915_WRITE(reg
, temp
);
3220 reg
= FDI_RX_CTL(pipe
);
3221 temp
= I915_READ(reg
);
3222 if (HAS_PCH_CPT(dev
)) {
3223 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3224 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3226 temp
&= ~FDI_LINK_TRAIN_NONE
;
3227 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3229 I915_WRITE(reg
, temp
);
3234 for (i
= 0; i
< 4; i
++) {
3235 reg
= FDI_TX_CTL(pipe
);
3236 temp
= I915_READ(reg
);
3237 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3238 temp
|= snb_b_fdi_train_param
[i
];
3239 I915_WRITE(reg
, temp
);
3244 for (retry
= 0; retry
< 5; retry
++) {
3245 reg
= FDI_RX_IIR(pipe
);
3246 temp
= I915_READ(reg
);
3247 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3248 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3249 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3250 DRM_DEBUG_KMS("FDI train 2 done.\n");
3259 DRM_ERROR("FDI train 2 fail!\n");
3261 DRM_DEBUG_KMS("FDI train done.\n");
3264 /* Manual link training for Ivy Bridge A0 parts */
3265 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
3267 struct drm_device
*dev
= crtc
->dev
;
3268 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3269 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3270 int pipe
= intel_crtc
->pipe
;
3271 u32 reg
, temp
, i
, j
;
3273 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3275 reg
= FDI_RX_IMR(pipe
);
3276 temp
= I915_READ(reg
);
3277 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3278 temp
&= ~FDI_RX_BIT_LOCK
;
3279 I915_WRITE(reg
, temp
);
3284 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3285 I915_READ(FDI_RX_IIR(pipe
)));
3287 /* Try each vswing and preemphasis setting twice before moving on */
3288 for (j
= 0; j
< ARRAY_SIZE(snb_b_fdi_train_param
) * 2; j
++) {
3289 /* disable first in case we need to retry */
3290 reg
= FDI_TX_CTL(pipe
);
3291 temp
= I915_READ(reg
);
3292 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
3293 temp
&= ~FDI_TX_ENABLE
;
3294 I915_WRITE(reg
, temp
);
3296 reg
= FDI_RX_CTL(pipe
);
3297 temp
= I915_READ(reg
);
3298 temp
&= ~FDI_LINK_TRAIN_AUTO
;
3299 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3300 temp
&= ~FDI_RX_ENABLE
;
3301 I915_WRITE(reg
, temp
);
3303 /* enable CPU FDI TX and PCH FDI RX */
3304 reg
= FDI_TX_CTL(pipe
);
3305 temp
= I915_READ(reg
);
3306 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3307 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3308 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
3309 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3310 temp
|= snb_b_fdi_train_param
[j
/2];
3311 temp
|= FDI_COMPOSITE_SYNC
;
3312 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3314 I915_WRITE(FDI_RX_MISC(pipe
),
3315 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3317 reg
= FDI_RX_CTL(pipe
);
3318 temp
= I915_READ(reg
);
3319 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3320 temp
|= FDI_COMPOSITE_SYNC
;
3321 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3324 udelay(1); /* should be 0.5us */
3326 for (i
= 0; i
< 4; i
++) {
3327 reg
= FDI_RX_IIR(pipe
);
3328 temp
= I915_READ(reg
);
3329 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3331 if (temp
& FDI_RX_BIT_LOCK
||
3332 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
3333 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3334 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3338 udelay(1); /* should be 0.5us */
3341 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j
/ 2);
3346 reg
= FDI_TX_CTL(pipe
);
3347 temp
= I915_READ(reg
);
3348 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3349 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
3350 I915_WRITE(reg
, temp
);
3352 reg
= FDI_RX_CTL(pipe
);
3353 temp
= I915_READ(reg
);
3354 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3355 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3356 I915_WRITE(reg
, temp
);
3359 udelay(2); /* should be 1.5us */
3361 for (i
= 0; i
< 4; i
++) {
3362 reg
= FDI_RX_IIR(pipe
);
3363 temp
= I915_READ(reg
);
3364 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3366 if (temp
& FDI_RX_SYMBOL_LOCK
||
3367 (I915_READ(reg
) & FDI_RX_SYMBOL_LOCK
)) {
3368 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3369 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3373 udelay(2); /* should be 1.5us */
3376 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j
/ 2);
3380 DRM_DEBUG_KMS("FDI train done.\n");
3383 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
3385 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3386 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3387 int pipe
= intel_crtc
->pipe
;
3391 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3392 reg
= FDI_RX_CTL(pipe
);
3393 temp
= I915_READ(reg
);
3394 temp
&= ~(FDI_DP_PORT_WIDTH_MASK
| (0x7 << 16));
3395 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3396 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3397 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
3402 /* Switch from Rawclk to PCDclk */
3403 temp
= I915_READ(reg
);
3404 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
3409 /* Enable CPU FDI TX PLL, always on for Ironlake */
3410 reg
= FDI_TX_CTL(pipe
);
3411 temp
= I915_READ(reg
);
3412 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
3413 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
3420 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
3422 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3423 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3424 int pipe
= intel_crtc
->pipe
;
3427 /* Switch from PCDclk to Rawclk */
3428 reg
= FDI_RX_CTL(pipe
);
3429 temp
= I915_READ(reg
);
3430 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
3432 /* Disable CPU FDI TX PLL */
3433 reg
= FDI_TX_CTL(pipe
);
3434 temp
= I915_READ(reg
);
3435 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
3440 reg
= FDI_RX_CTL(pipe
);
3441 temp
= I915_READ(reg
);
3442 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
3444 /* Wait for the clocks to turn off. */
3449 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
3451 struct drm_device
*dev
= crtc
->dev
;
3452 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3453 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3454 int pipe
= intel_crtc
->pipe
;
3457 /* disable CPU FDI tx and PCH FDI rx */
3458 reg
= FDI_TX_CTL(pipe
);
3459 temp
= I915_READ(reg
);
3460 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
3463 reg
= FDI_RX_CTL(pipe
);
3464 temp
= I915_READ(reg
);
3465 temp
&= ~(0x7 << 16);
3466 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3467 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
3472 /* Ironlake workaround, disable clock pointer after downing FDI */
3473 if (HAS_PCH_IBX(dev
))
3474 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3476 /* still set train pattern 1 */
3477 reg
= FDI_TX_CTL(pipe
);
3478 temp
= I915_READ(reg
);
3479 temp
&= ~FDI_LINK_TRAIN_NONE
;
3480 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3481 I915_WRITE(reg
, temp
);
3483 reg
= FDI_RX_CTL(pipe
);
3484 temp
= I915_READ(reg
);
3485 if (HAS_PCH_CPT(dev
)) {
3486 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3487 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3489 temp
&= ~FDI_LINK_TRAIN_NONE
;
3490 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3492 /* BPC in FDI rx is consistent with that in PIPECONF */
3493 temp
&= ~(0x07 << 16);
3494 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3495 I915_WRITE(reg
, temp
);
3501 bool intel_has_pending_fb_unpin(struct drm_device
*dev
)
3503 struct intel_crtc
*crtc
;
3505 /* Note that we don't need to be called with mode_config.lock here
3506 * as our list of CRTC objects is static for the lifetime of the
3507 * device and so cannot disappear as we iterate. Similarly, we can
3508 * happily treat the predicates as racy, atomic checks as userspace
3509 * cannot claim and pin a new fb without at least acquring the
3510 * struct_mutex and so serialising with us.
3512 for_each_intel_crtc(dev
, crtc
) {
3513 if (atomic_read(&crtc
->unpin_work_count
) == 0)
3516 if (crtc
->unpin_work
)
3517 intel_wait_for_vblank(dev
, crtc
->pipe
);
3525 static void page_flip_completed(struct intel_crtc
*intel_crtc
)
3527 struct drm_i915_private
*dev_priv
= to_i915(intel_crtc
->base
.dev
);
3528 struct intel_unpin_work
*work
= intel_crtc
->unpin_work
;
3530 /* ensure that the unpin work is consistent wrt ->pending. */
3532 intel_crtc
->unpin_work
= NULL
;
3535 drm_send_vblank_event(intel_crtc
->base
.dev
,
3539 drm_crtc_vblank_put(&intel_crtc
->base
);
3541 wake_up_all(&dev_priv
->pending_flip_queue
);
3542 queue_work(dev_priv
->wq
, &work
->work
);
3544 trace_i915_flip_complete(intel_crtc
->plane
,
3545 work
->pending_flip_obj
);
3548 void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
3550 struct drm_device
*dev
= crtc
->dev
;
3551 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3553 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
3554 if (WARN_ON(wait_event_timeout(dev_priv
->pending_flip_queue
,
3555 !intel_crtc_has_pending_flip(crtc
),
3557 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3559 spin_lock_irq(&dev
->event_lock
);
3560 if (intel_crtc
->unpin_work
) {
3561 WARN_ONCE(1, "Removing stuck page flip\n");
3562 page_flip_completed(intel_crtc
);
3564 spin_unlock_irq(&dev
->event_lock
);
3567 if (crtc
->primary
->fb
) {
3568 mutex_lock(&dev
->struct_mutex
);
3569 intel_finish_fb(crtc
->primary
->fb
);
3570 mutex_unlock(&dev
->struct_mutex
);
3574 /* Program iCLKIP clock to the desired frequency */
3575 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
3577 struct drm_device
*dev
= crtc
->dev
;
3578 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3579 int clock
= to_intel_crtc(crtc
)->config
->base
.adjusted_mode
.crtc_clock
;
3580 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
3583 mutex_lock(&dev_priv
->dpio_lock
);
3585 /* It is necessary to ungate the pixclk gate prior to programming
3586 * the divisors, and gate it back when it is done.
3588 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
3590 /* Disable SSCCTL */
3591 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
3592 intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
) |
3596 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3597 if (clock
== 20000) {
3602 /* The iCLK virtual clock root frequency is in MHz,
3603 * but the adjusted_mode->crtc_clock in in KHz. To get the
3604 * divisors, it is necessary to divide one by another, so we
3605 * convert the virtual clock precision to KHz here for higher
3608 u32 iclk_virtual_root_freq
= 172800 * 1000;
3609 u32 iclk_pi_range
= 64;
3610 u32 desired_divisor
, msb_divisor_value
, pi_value
;
3612 desired_divisor
= (iclk_virtual_root_freq
/ clock
);
3613 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
3614 pi_value
= desired_divisor
% iclk_pi_range
;
3617 divsel
= msb_divisor_value
- 2;
3618 phaseinc
= pi_value
;
3621 /* This should not happen with any sane values */
3622 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
3623 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
3624 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
3625 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
3627 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3634 /* Program SSCDIVINTPHASE6 */
3635 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
3636 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
3637 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
3638 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
3639 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
3640 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
3641 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
3642 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
3644 /* Program SSCAUXDIV */
3645 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
3646 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3647 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
3648 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
3650 /* Enable modulator and associated divider */
3651 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
3652 temp
&= ~SBI_SSCCTL_DISABLE
;
3653 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
3655 /* Wait for initialization time */
3658 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
3660 mutex_unlock(&dev_priv
->dpio_lock
);
3663 static void ironlake_pch_transcoder_set_timings(struct intel_crtc
*crtc
,
3664 enum pipe pch_transcoder
)
3666 struct drm_device
*dev
= crtc
->base
.dev
;
3667 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3668 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
3670 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder
),
3671 I915_READ(HTOTAL(cpu_transcoder
)));
3672 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder
),
3673 I915_READ(HBLANK(cpu_transcoder
)));
3674 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder
),
3675 I915_READ(HSYNC(cpu_transcoder
)));
3677 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder
),
3678 I915_READ(VTOTAL(cpu_transcoder
)));
3679 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder
),
3680 I915_READ(VBLANK(cpu_transcoder
)));
3681 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder
),
3682 I915_READ(VSYNC(cpu_transcoder
)));
3683 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder
),
3684 I915_READ(VSYNCSHIFT(cpu_transcoder
)));
3687 static void cpt_enable_fdi_bc_bifurcation(struct drm_device
*dev
)
3689 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3692 temp
= I915_READ(SOUTH_CHICKEN1
);
3693 if (temp
& FDI_BC_BIFURCATION_SELECT
)
3696 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
3697 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
3699 temp
|= FDI_BC_BIFURCATION_SELECT
;
3700 DRM_DEBUG_KMS("enabling fdi C rx\n");
3701 I915_WRITE(SOUTH_CHICKEN1
, temp
);
3702 POSTING_READ(SOUTH_CHICKEN1
);
3705 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc
*intel_crtc
)
3707 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3708 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3710 switch (intel_crtc
->pipe
) {
3714 if (intel_crtc
->config
->fdi_lanes
> 2)
3715 WARN_ON(I915_READ(SOUTH_CHICKEN1
) & FDI_BC_BIFURCATION_SELECT
);
3717 cpt_enable_fdi_bc_bifurcation(dev
);
3721 cpt_enable_fdi_bc_bifurcation(dev
);
3730 * Enable PCH resources required for PCH ports:
3732 * - FDI training & RX/TX
3733 * - update transcoder timings
3734 * - DP transcoding bits
3737 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
3739 struct drm_device
*dev
= crtc
->dev
;
3740 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3741 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3742 int pipe
= intel_crtc
->pipe
;
3745 assert_pch_transcoder_disabled(dev_priv
, pipe
);
3747 if (IS_IVYBRIDGE(dev
))
3748 ivybridge_update_fdi_bc_bifurcation(intel_crtc
);
3750 /* Write the TU size bits before fdi link training, so that error
3751 * detection works. */
3752 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
3753 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
3755 /* For PCH output, training FDI link */
3756 dev_priv
->display
.fdi_link_train(crtc
);
3758 /* We need to program the right clock selection before writing the pixel
3759 * mutliplier into the DPLL. */
3760 if (HAS_PCH_CPT(dev
)) {
3763 temp
= I915_READ(PCH_DPLL_SEL
);
3764 temp
|= TRANS_DPLL_ENABLE(pipe
);
3765 sel
= TRANS_DPLLB_SEL(pipe
);
3766 if (intel_crtc
->config
->shared_dpll
== DPLL_ID_PCH_PLL_B
)
3770 I915_WRITE(PCH_DPLL_SEL
, temp
);
3773 /* XXX: pch pll's can be enabled any time before we enable the PCH
3774 * transcoder, and we actually should do this to not upset any PCH
3775 * transcoder that already use the clock when we share it.
3777 * Note that enable_shared_dpll tries to do the right thing, but
3778 * get_shared_dpll unconditionally resets the pll - we need that to have
3779 * the right LVDS enable sequence. */
3780 intel_enable_shared_dpll(intel_crtc
);
3782 /* set transcoder timing, panel must allow it */
3783 assert_panel_unlocked(dev_priv
, pipe
);
3784 ironlake_pch_transcoder_set_timings(intel_crtc
, pipe
);
3786 intel_fdi_normal_train(crtc
);
3788 /* For PCH DP, enable TRANS_DP_CTL */
3789 if (HAS_PCH_CPT(dev
) && intel_crtc
->config
->has_dp_encoder
) {
3790 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
3791 reg
= TRANS_DP_CTL(pipe
);
3792 temp
= I915_READ(reg
);
3793 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
3794 TRANS_DP_SYNC_MASK
|
3796 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
3797 TRANS_DP_ENH_FRAMING
);
3798 temp
|= bpc
<< 9; /* same format but at 11:9 */
3800 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
3801 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
3802 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
3803 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
3805 switch (intel_trans_dp_port_sel(crtc
)) {
3807 temp
|= TRANS_DP_PORT_SEL_B
;
3810 temp
|= TRANS_DP_PORT_SEL_C
;
3813 temp
|= TRANS_DP_PORT_SEL_D
;
3819 I915_WRITE(reg
, temp
);
3822 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
3825 static void lpt_pch_enable(struct drm_crtc
*crtc
)
3827 struct drm_device
*dev
= crtc
->dev
;
3828 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3829 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3830 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
3832 assert_pch_transcoder_disabled(dev_priv
, TRANSCODER_A
);
3834 lpt_program_iclkip(crtc
);
3836 /* Set transcoder timing. */
3837 ironlake_pch_transcoder_set_timings(intel_crtc
, PIPE_A
);
3839 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
3842 void intel_put_shared_dpll(struct intel_crtc
*crtc
)
3844 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
3849 if (!(pll
->config
.crtc_mask
& (1 << crtc
->pipe
))) {
3850 WARN(1, "bad %s crtc mask\n", pll
->name
);
3854 pll
->config
.crtc_mask
&= ~(1 << crtc
->pipe
);
3855 if (pll
->config
.crtc_mask
== 0) {
3857 WARN_ON(pll
->active
);
3860 crtc
->config
->shared_dpll
= DPLL_ID_PRIVATE
;
3863 struct intel_shared_dpll
*intel_get_shared_dpll(struct intel_crtc
*crtc
,
3864 struct intel_crtc_state
*crtc_state
)
3866 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
3867 struct intel_shared_dpll
*pll
;
3868 enum intel_dpll_id i
;
3870 if (HAS_PCH_IBX(dev_priv
->dev
)) {
3871 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3872 i
= (enum intel_dpll_id
) crtc
->pipe
;
3873 pll
= &dev_priv
->shared_dplls
[i
];
3875 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3876 crtc
->base
.base
.id
, pll
->name
);
3878 WARN_ON(pll
->new_config
->crtc_mask
);
3883 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3884 pll
= &dev_priv
->shared_dplls
[i
];
3886 /* Only want to check enabled timings first */
3887 if (pll
->new_config
->crtc_mask
== 0)
3890 if (memcmp(&crtc_state
->dpll_hw_state
,
3891 &pll
->new_config
->hw_state
,
3892 sizeof(pll
->new_config
->hw_state
)) == 0) {
3893 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
3894 crtc
->base
.base
.id
, pll
->name
,
3895 pll
->new_config
->crtc_mask
,
3901 /* Ok no matching timings, maybe there's a free one? */
3902 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3903 pll
= &dev_priv
->shared_dplls
[i
];
3904 if (pll
->new_config
->crtc_mask
== 0) {
3905 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3906 crtc
->base
.base
.id
, pll
->name
);
3914 if (pll
->new_config
->crtc_mask
== 0)
3915 pll
->new_config
->hw_state
= crtc_state
->dpll_hw_state
;
3917 crtc_state
->shared_dpll
= i
;
3918 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll
->name
,
3919 pipe_name(crtc
->pipe
));
3921 pll
->new_config
->crtc_mask
|= 1 << crtc
->pipe
;
3927 * intel_shared_dpll_start_config - start a new PLL staged config
3928 * @dev_priv: DRM device
3929 * @clear_pipes: mask of pipes that will have their PLLs freed
3931 * Starts a new PLL staged config, copying the current config but
3932 * releasing the references of pipes specified in clear_pipes.
3934 static int intel_shared_dpll_start_config(struct drm_i915_private
*dev_priv
,
3935 unsigned clear_pipes
)
3937 struct intel_shared_dpll
*pll
;
3938 enum intel_dpll_id i
;
3940 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3941 pll
= &dev_priv
->shared_dplls
[i
];
3943 pll
->new_config
= kmemdup(&pll
->config
, sizeof pll
->config
,
3945 if (!pll
->new_config
)
3948 pll
->new_config
->crtc_mask
&= ~clear_pipes
;
3955 pll
= &dev_priv
->shared_dplls
[i
];
3956 kfree(pll
->new_config
);
3957 pll
->new_config
= NULL
;
3963 static void intel_shared_dpll_commit(struct drm_i915_private
*dev_priv
)
3965 struct intel_shared_dpll
*pll
;
3966 enum intel_dpll_id i
;
3968 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3969 pll
= &dev_priv
->shared_dplls
[i
];
3971 WARN_ON(pll
->new_config
== &pll
->config
);
3973 pll
->config
= *pll
->new_config
;
3974 kfree(pll
->new_config
);
3975 pll
->new_config
= NULL
;
3979 static void intel_shared_dpll_abort_config(struct drm_i915_private
*dev_priv
)
3981 struct intel_shared_dpll
*pll
;
3982 enum intel_dpll_id i
;
3984 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3985 pll
= &dev_priv
->shared_dplls
[i
];
3987 WARN_ON(pll
->new_config
== &pll
->config
);
3989 kfree(pll
->new_config
);
3990 pll
->new_config
= NULL
;
3994 static void cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
3996 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3997 int dslreg
= PIPEDSL(pipe
);
4000 temp
= I915_READ(dslreg
);
4002 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
4003 if (wait_for(I915_READ(dslreg
) != temp
, 5))
4004 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
4008 static void skylake_pfit_enable(struct intel_crtc
*crtc
)
4010 struct drm_device
*dev
= crtc
->base
.dev
;
4011 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4012 int pipe
= crtc
->pipe
;
4014 if (crtc
->config
->pch_pfit
.enabled
) {
4015 I915_WRITE(PS_CTL(pipe
), PS_ENABLE
);
4016 I915_WRITE(PS_WIN_POS(pipe
), crtc
->config
->pch_pfit
.pos
);
4017 I915_WRITE(PS_WIN_SZ(pipe
), crtc
->config
->pch_pfit
.size
);
4021 static void ironlake_pfit_enable(struct intel_crtc
*crtc
)
4023 struct drm_device
*dev
= crtc
->base
.dev
;
4024 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4025 int pipe
= crtc
->pipe
;
4027 if (crtc
->config
->pch_pfit
.enabled
) {
4028 /* Force use of hard-coded filter coefficients
4029 * as some pre-programmed values are broken,
4032 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
4033 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
4034 PF_PIPE_SEL_IVB(pipe
));
4036 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
4037 I915_WRITE(PF_WIN_POS(pipe
), crtc
->config
->pch_pfit
.pos
);
4038 I915_WRITE(PF_WIN_SZ(pipe
), crtc
->config
->pch_pfit
.size
);
4042 static void intel_enable_sprite_planes(struct drm_crtc
*crtc
)
4044 struct drm_device
*dev
= crtc
->dev
;
4045 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
4046 struct drm_plane
*plane
;
4047 struct intel_plane
*intel_plane
;
4049 drm_for_each_legacy_plane(plane
, &dev
->mode_config
.plane_list
) {
4050 intel_plane
= to_intel_plane(plane
);
4051 if (intel_plane
->pipe
== pipe
)
4052 intel_plane_restore(&intel_plane
->base
);
4056 static void intel_disable_sprite_planes(struct drm_crtc
*crtc
)
4058 struct drm_device
*dev
= crtc
->dev
;
4059 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
4060 struct drm_plane
*plane
;
4061 struct intel_plane
*intel_plane
;
4063 drm_for_each_legacy_plane(plane
, &dev
->mode_config
.plane_list
) {
4064 intel_plane
= to_intel_plane(plane
);
4065 if (intel_plane
->pipe
== pipe
)
4066 plane
->funcs
->disable_plane(plane
);
4070 void hsw_enable_ips(struct intel_crtc
*crtc
)
4072 struct drm_device
*dev
= crtc
->base
.dev
;
4073 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4075 if (!crtc
->config
->ips_enabled
)
4078 /* We can only enable IPS after we enable a plane and wait for a vblank */
4079 intel_wait_for_vblank(dev
, crtc
->pipe
);
4081 assert_plane_enabled(dev_priv
, crtc
->plane
);
4082 if (IS_BROADWELL(dev
)) {
4083 mutex_lock(&dev_priv
->rps
.hw_lock
);
4084 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0xc0000000));
4085 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4086 /* Quoting Art Runyan: "its not safe to expect any particular
4087 * value in IPS_CTL bit 31 after enabling IPS through the
4088 * mailbox." Moreover, the mailbox may return a bogus state,
4089 * so we need to just enable it and continue on.
4092 I915_WRITE(IPS_CTL
, IPS_ENABLE
);
4093 /* The bit only becomes 1 in the next vblank, so this wait here
4094 * is essentially intel_wait_for_vblank. If we don't have this
4095 * and don't wait for vblanks until the end of crtc_enable, then
4096 * the HW state readout code will complain that the expected
4097 * IPS_CTL value is not the one we read. */
4098 if (wait_for(I915_READ_NOTRACE(IPS_CTL
) & IPS_ENABLE
, 50))
4099 DRM_ERROR("Timed out waiting for IPS enable\n");
4103 void hsw_disable_ips(struct intel_crtc
*crtc
)
4105 struct drm_device
*dev
= crtc
->base
.dev
;
4106 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4108 if (!crtc
->config
->ips_enabled
)
4111 assert_plane_enabled(dev_priv
, crtc
->plane
);
4112 if (IS_BROADWELL(dev
)) {
4113 mutex_lock(&dev_priv
->rps
.hw_lock
);
4114 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0));
4115 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4116 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4117 if (wait_for((I915_READ(IPS_CTL
) & IPS_ENABLE
) == 0, 42))
4118 DRM_ERROR("Timed out waiting for IPS disable\n");
4120 I915_WRITE(IPS_CTL
, 0);
4121 POSTING_READ(IPS_CTL
);
4124 /* We need to wait for a vblank before we can disable the plane. */
4125 intel_wait_for_vblank(dev
, crtc
->pipe
);
4128 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4129 static void intel_crtc_load_lut(struct drm_crtc
*crtc
)
4131 struct drm_device
*dev
= crtc
->dev
;
4132 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4133 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4134 enum pipe pipe
= intel_crtc
->pipe
;
4135 int palreg
= PALETTE(pipe
);
4137 bool reenable_ips
= false;
4139 /* The clocks have to be on to load the palette. */
4140 if (!crtc
->enabled
|| !intel_crtc
->active
)
4143 if (!HAS_PCH_SPLIT(dev_priv
->dev
)) {
4144 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
))
4145 assert_dsi_pll_enabled(dev_priv
);
4147 assert_pll_enabled(dev_priv
, pipe
);
4150 /* use legacy palette for Ironlake */
4151 if (!HAS_GMCH_DISPLAY(dev
))
4152 palreg
= LGC_PALETTE(pipe
);
4154 /* Workaround : Do not read or write the pipe palette/gamma data while
4155 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4157 if (IS_HASWELL(dev
) && intel_crtc
->config
->ips_enabled
&&
4158 ((I915_READ(GAMMA_MODE(pipe
)) & GAMMA_MODE_MODE_MASK
) ==
4159 GAMMA_MODE_MODE_SPLIT
)) {
4160 hsw_disable_ips(intel_crtc
);
4161 reenable_ips
= true;
4164 for (i
= 0; i
< 256; i
++) {
4165 I915_WRITE(palreg
+ 4 * i
,
4166 (intel_crtc
->lut_r
[i
] << 16) |
4167 (intel_crtc
->lut_g
[i
] << 8) |
4168 intel_crtc
->lut_b
[i
]);
4172 hsw_enable_ips(intel_crtc
);
4175 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
4177 if (!enable
&& intel_crtc
->overlay
) {
4178 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4179 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4181 mutex_lock(&dev
->struct_mutex
);
4182 dev_priv
->mm
.interruptible
= false;
4183 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
4184 dev_priv
->mm
.interruptible
= true;
4185 mutex_unlock(&dev
->struct_mutex
);
4188 /* Let userspace switch the overlay on again. In most cases userspace
4189 * has to recompute where to put it anyway.
4193 static void intel_crtc_enable_planes(struct drm_crtc
*crtc
)
4195 struct drm_device
*dev
= crtc
->dev
;
4196 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4197 int pipe
= intel_crtc
->pipe
;
4199 intel_enable_primary_hw_plane(crtc
->primary
, crtc
);
4200 intel_enable_sprite_planes(crtc
);
4201 intel_crtc_update_cursor(crtc
, true);
4202 intel_crtc_dpms_overlay(intel_crtc
, true);
4204 hsw_enable_ips(intel_crtc
);
4206 mutex_lock(&dev
->struct_mutex
);
4207 intel_fbc_update(dev
);
4208 mutex_unlock(&dev
->struct_mutex
);
4211 * FIXME: Once we grow proper nuclear flip support out of this we need
4212 * to compute the mask of flip planes precisely. For the time being
4213 * consider this a flip from a NULL plane.
4215 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_ALL_MASK(pipe
));
4218 static void intel_crtc_disable_planes(struct drm_crtc
*crtc
)
4220 struct drm_device
*dev
= crtc
->dev
;
4221 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4222 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4223 int pipe
= intel_crtc
->pipe
;
4224 int plane
= intel_crtc
->plane
;
4226 intel_crtc_wait_for_pending_flips(crtc
);
4228 if (dev_priv
->fbc
.plane
== plane
)
4229 intel_fbc_disable(dev
);
4231 hsw_disable_ips(intel_crtc
);
4233 intel_crtc_dpms_overlay(intel_crtc
, false);
4234 intel_crtc_update_cursor(crtc
, false);
4235 intel_disable_sprite_planes(crtc
);
4236 intel_disable_primary_hw_plane(crtc
->primary
, crtc
);
4239 * FIXME: Once we grow proper nuclear flip support out of this we need
4240 * to compute the mask of flip planes precisely. For the time being
4241 * consider this a flip to a NULL plane.
4243 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_ALL_MASK(pipe
));
4246 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
4248 struct drm_device
*dev
= crtc
->dev
;
4249 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4250 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4251 struct intel_encoder
*encoder
;
4252 int pipe
= intel_crtc
->pipe
;
4254 WARN_ON(!crtc
->enabled
);
4256 if (intel_crtc
->active
)
4259 if (intel_crtc
->config
->has_pch_encoder
)
4260 intel_prepare_shared_dpll(intel_crtc
);
4262 if (intel_crtc
->config
->has_dp_encoder
)
4263 intel_dp_set_m_n(intel_crtc
);
4265 intel_set_pipe_timings(intel_crtc
);
4267 if (intel_crtc
->config
->has_pch_encoder
) {
4268 intel_cpu_transcoder_set_m_n(intel_crtc
,
4269 &intel_crtc
->config
->fdi_m_n
, NULL
);
4272 ironlake_set_pipeconf(crtc
);
4274 intel_crtc
->active
= true;
4276 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4277 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, true);
4279 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4280 if (encoder
->pre_enable
)
4281 encoder
->pre_enable(encoder
);
4283 if (intel_crtc
->config
->has_pch_encoder
) {
4284 /* Note: FDI PLL enabling _must_ be done before we enable the
4285 * cpu pipes, hence this is separate from all the other fdi/pch
4287 ironlake_fdi_pll_enable(intel_crtc
);
4289 assert_fdi_tx_disabled(dev_priv
, pipe
);
4290 assert_fdi_rx_disabled(dev_priv
, pipe
);
4293 ironlake_pfit_enable(intel_crtc
);
4296 * On ILK+ LUT must be loaded before the pipe is running but with
4299 intel_crtc_load_lut(crtc
);
4301 intel_update_watermarks(crtc
);
4302 intel_enable_pipe(intel_crtc
);
4304 if (intel_crtc
->config
->has_pch_encoder
)
4305 ironlake_pch_enable(crtc
);
4307 assert_vblank_disabled(crtc
);
4308 drm_crtc_vblank_on(crtc
);
4310 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4311 encoder
->enable(encoder
);
4313 if (HAS_PCH_CPT(dev
))
4314 cpt_verify_modeset(dev
, intel_crtc
->pipe
);
4316 intel_crtc_enable_planes(crtc
);
4319 /* IPS only exists on ULT machines and is tied to pipe A. */
4320 static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc
)
4322 return HAS_IPS(crtc
->base
.dev
) && crtc
->pipe
== PIPE_A
;
4326 * This implements the workaround described in the "notes" section of the mode
4327 * set sequence documentation. When going from no pipes or single pipe to
4328 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4329 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4331 static void haswell_mode_set_planes_workaround(struct intel_crtc
*crtc
)
4333 struct drm_device
*dev
= crtc
->base
.dev
;
4334 struct intel_crtc
*crtc_it
, *other_active_crtc
= NULL
;
4336 /* We want to get the other_active_crtc only if there's only 1 other
4338 for_each_intel_crtc(dev
, crtc_it
) {
4339 if (!crtc_it
->active
|| crtc_it
== crtc
)
4342 if (other_active_crtc
)
4345 other_active_crtc
= crtc_it
;
4347 if (!other_active_crtc
)
4350 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
4351 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
4354 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
4356 struct drm_device
*dev
= crtc
->dev
;
4357 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4358 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4359 struct intel_encoder
*encoder
;
4360 int pipe
= intel_crtc
->pipe
;
4362 WARN_ON(!crtc
->enabled
);
4364 if (intel_crtc
->active
)
4367 if (intel_crtc_to_shared_dpll(intel_crtc
))
4368 intel_enable_shared_dpll(intel_crtc
);
4370 if (intel_crtc
->config
->has_dp_encoder
)
4371 intel_dp_set_m_n(intel_crtc
);
4373 intel_set_pipe_timings(intel_crtc
);
4375 if (intel_crtc
->config
->cpu_transcoder
!= TRANSCODER_EDP
) {
4376 I915_WRITE(PIPE_MULT(intel_crtc
->config
->cpu_transcoder
),
4377 intel_crtc
->config
->pixel_multiplier
- 1);
4380 if (intel_crtc
->config
->has_pch_encoder
) {
4381 intel_cpu_transcoder_set_m_n(intel_crtc
,
4382 &intel_crtc
->config
->fdi_m_n
, NULL
);
4385 haswell_set_pipeconf(crtc
);
4387 intel_set_pipe_csc(crtc
);
4389 intel_crtc
->active
= true;
4391 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4392 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4393 if (encoder
->pre_enable
)
4394 encoder
->pre_enable(encoder
);
4396 if (intel_crtc
->config
->has_pch_encoder
) {
4397 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
4399 dev_priv
->display
.fdi_link_train(crtc
);
4402 intel_ddi_enable_pipe_clock(intel_crtc
);
4404 if (IS_SKYLAKE(dev
))
4405 skylake_pfit_enable(intel_crtc
);
4407 ironlake_pfit_enable(intel_crtc
);
4410 * On ILK+ LUT must be loaded before the pipe is running but with
4413 intel_crtc_load_lut(crtc
);
4415 intel_ddi_set_pipe_settings(crtc
);
4416 intel_ddi_enable_transcoder_func(crtc
);
4418 intel_update_watermarks(crtc
);
4419 intel_enable_pipe(intel_crtc
);
4421 if (intel_crtc
->config
->has_pch_encoder
)
4422 lpt_pch_enable(crtc
);
4424 if (intel_crtc
->config
->dp_encoder_is_mst
)
4425 intel_ddi_set_vc_payload_alloc(crtc
, true);
4427 assert_vblank_disabled(crtc
);
4428 drm_crtc_vblank_on(crtc
);
4430 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4431 encoder
->enable(encoder
);
4432 intel_opregion_notify_encoder(encoder
, true);
4435 /* If we change the relative order between pipe/planes enabling, we need
4436 * to change the workaround. */
4437 haswell_mode_set_planes_workaround(intel_crtc
);
4438 intel_crtc_enable_planes(crtc
);
4441 static void skylake_pfit_disable(struct intel_crtc
*crtc
)
4443 struct drm_device
*dev
= crtc
->base
.dev
;
4444 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4445 int pipe
= crtc
->pipe
;
4447 /* To avoid upsetting the power well on haswell only disable the pfit if
4448 * it's in use. The hw state code will make sure we get this right. */
4449 if (crtc
->config
->pch_pfit
.enabled
) {
4450 I915_WRITE(PS_CTL(pipe
), 0);
4451 I915_WRITE(PS_WIN_POS(pipe
), 0);
4452 I915_WRITE(PS_WIN_SZ(pipe
), 0);
4456 static void ironlake_pfit_disable(struct intel_crtc
*crtc
)
4458 struct drm_device
*dev
= crtc
->base
.dev
;
4459 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4460 int pipe
= crtc
->pipe
;
4462 /* To avoid upsetting the power well on haswell only disable the pfit if
4463 * it's in use. The hw state code will make sure we get this right. */
4464 if (crtc
->config
->pch_pfit
.enabled
) {
4465 I915_WRITE(PF_CTL(pipe
), 0);
4466 I915_WRITE(PF_WIN_POS(pipe
), 0);
4467 I915_WRITE(PF_WIN_SZ(pipe
), 0);
4471 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
4473 struct drm_device
*dev
= crtc
->dev
;
4474 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4475 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4476 struct intel_encoder
*encoder
;
4477 int pipe
= intel_crtc
->pipe
;
4480 if (!intel_crtc
->active
)
4483 intel_crtc_disable_planes(crtc
);
4485 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4486 encoder
->disable(encoder
);
4488 drm_crtc_vblank_off(crtc
);
4489 assert_vblank_disabled(crtc
);
4491 if (intel_crtc
->config
->has_pch_encoder
)
4492 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, false);
4494 intel_disable_pipe(intel_crtc
);
4496 ironlake_pfit_disable(intel_crtc
);
4498 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4499 if (encoder
->post_disable
)
4500 encoder
->post_disable(encoder
);
4502 if (intel_crtc
->config
->has_pch_encoder
) {
4503 ironlake_fdi_disable(crtc
);
4505 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
4507 if (HAS_PCH_CPT(dev
)) {
4508 /* disable TRANS_DP_CTL */
4509 reg
= TRANS_DP_CTL(pipe
);
4510 temp
= I915_READ(reg
);
4511 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
|
4512 TRANS_DP_PORT_SEL_MASK
);
4513 temp
|= TRANS_DP_PORT_SEL_NONE
;
4514 I915_WRITE(reg
, temp
);
4516 /* disable DPLL_SEL */
4517 temp
= I915_READ(PCH_DPLL_SEL
);
4518 temp
&= ~(TRANS_DPLL_ENABLE(pipe
) | TRANS_DPLLB_SEL(pipe
));
4519 I915_WRITE(PCH_DPLL_SEL
, temp
);
4522 /* disable PCH DPLL */
4523 intel_disable_shared_dpll(intel_crtc
);
4525 ironlake_fdi_pll_disable(intel_crtc
);
4528 intel_crtc
->active
= false;
4529 intel_update_watermarks(crtc
);
4531 mutex_lock(&dev
->struct_mutex
);
4532 intel_fbc_update(dev
);
4533 mutex_unlock(&dev
->struct_mutex
);
4536 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
4538 struct drm_device
*dev
= crtc
->dev
;
4539 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4540 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4541 struct intel_encoder
*encoder
;
4542 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
4544 if (!intel_crtc
->active
)
4547 intel_crtc_disable_planes(crtc
);
4549 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4550 intel_opregion_notify_encoder(encoder
, false);
4551 encoder
->disable(encoder
);
4554 drm_crtc_vblank_off(crtc
);
4555 assert_vblank_disabled(crtc
);
4557 if (intel_crtc
->config
->has_pch_encoder
)
4558 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
4560 intel_disable_pipe(intel_crtc
);
4562 if (intel_crtc
->config
->dp_encoder_is_mst
)
4563 intel_ddi_set_vc_payload_alloc(crtc
, false);
4565 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
4567 if (IS_SKYLAKE(dev
))
4568 skylake_pfit_disable(intel_crtc
);
4570 ironlake_pfit_disable(intel_crtc
);
4572 intel_ddi_disable_pipe_clock(intel_crtc
);
4574 if (intel_crtc
->config
->has_pch_encoder
) {
4575 lpt_disable_pch_transcoder(dev_priv
);
4576 intel_ddi_fdi_disable(crtc
);
4579 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4580 if (encoder
->post_disable
)
4581 encoder
->post_disable(encoder
);
4583 intel_crtc
->active
= false;
4584 intel_update_watermarks(crtc
);
4586 mutex_lock(&dev
->struct_mutex
);
4587 intel_fbc_update(dev
);
4588 mutex_unlock(&dev
->struct_mutex
);
4590 if (intel_crtc_to_shared_dpll(intel_crtc
))
4591 intel_disable_shared_dpll(intel_crtc
);
4594 static void ironlake_crtc_off(struct drm_crtc
*crtc
)
4596 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4597 intel_put_shared_dpll(intel_crtc
);
4601 static void i9xx_pfit_enable(struct intel_crtc
*crtc
)
4603 struct drm_device
*dev
= crtc
->base
.dev
;
4604 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4605 struct intel_crtc_state
*pipe_config
= crtc
->config
;
4607 if (!pipe_config
->gmch_pfit
.control
)
4611 * The panel fitter should only be adjusted whilst the pipe is disabled,
4612 * according to register description and PRM.
4614 WARN_ON(I915_READ(PFIT_CONTROL
) & PFIT_ENABLE
);
4615 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
4617 I915_WRITE(PFIT_PGM_RATIOS
, pipe_config
->gmch_pfit
.pgm_ratios
);
4618 I915_WRITE(PFIT_CONTROL
, pipe_config
->gmch_pfit
.control
);
4620 /* Border color in case we don't scale up to the full screen. Black by
4621 * default, change to something else for debugging. */
4622 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
4625 static enum intel_display_power_domain
port_to_power_domain(enum port port
)
4629 return POWER_DOMAIN_PORT_DDI_A_4_LANES
;
4631 return POWER_DOMAIN_PORT_DDI_B_4_LANES
;
4633 return POWER_DOMAIN_PORT_DDI_C_4_LANES
;
4635 return POWER_DOMAIN_PORT_DDI_D_4_LANES
;
4638 return POWER_DOMAIN_PORT_OTHER
;
4642 #define for_each_power_domain(domain, mask) \
4643 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4644 if ((1 << (domain)) & (mask))
4646 enum intel_display_power_domain
4647 intel_display_port_power_domain(struct intel_encoder
*intel_encoder
)
4649 struct drm_device
*dev
= intel_encoder
->base
.dev
;
4650 struct intel_digital_port
*intel_dig_port
;
4652 switch (intel_encoder
->type
) {
4653 case INTEL_OUTPUT_UNKNOWN
:
4654 /* Only DDI platforms should ever use this output type */
4655 WARN_ON_ONCE(!HAS_DDI(dev
));
4656 case INTEL_OUTPUT_DISPLAYPORT
:
4657 case INTEL_OUTPUT_HDMI
:
4658 case INTEL_OUTPUT_EDP
:
4659 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
4660 return port_to_power_domain(intel_dig_port
->port
);
4661 case INTEL_OUTPUT_DP_MST
:
4662 intel_dig_port
= enc_to_mst(&intel_encoder
->base
)->primary
;
4663 return port_to_power_domain(intel_dig_port
->port
);
4664 case INTEL_OUTPUT_ANALOG
:
4665 return POWER_DOMAIN_PORT_CRT
;
4666 case INTEL_OUTPUT_DSI
:
4667 return POWER_DOMAIN_PORT_DSI
;
4669 return POWER_DOMAIN_PORT_OTHER
;
4673 static unsigned long get_crtc_power_domains(struct drm_crtc
*crtc
)
4675 struct drm_device
*dev
= crtc
->dev
;
4676 struct intel_encoder
*intel_encoder
;
4677 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4678 enum pipe pipe
= intel_crtc
->pipe
;
4680 enum transcoder transcoder
;
4682 transcoder
= intel_pipe_to_cpu_transcoder(dev
->dev_private
, pipe
);
4684 mask
= BIT(POWER_DOMAIN_PIPE(pipe
));
4685 mask
|= BIT(POWER_DOMAIN_TRANSCODER(transcoder
));
4686 if (intel_crtc
->config
->pch_pfit
.enabled
||
4687 intel_crtc
->config
->pch_pfit
.force_thru
)
4688 mask
|= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe
));
4690 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
4691 mask
|= BIT(intel_display_port_power_domain(intel_encoder
));
4696 static void modeset_update_crtc_power_domains(struct drm_device
*dev
)
4698 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4699 unsigned long pipe_domains
[I915_MAX_PIPES
] = { 0, };
4700 struct intel_crtc
*crtc
;
4703 * First get all needed power domains, then put all unneeded, to avoid
4704 * any unnecessary toggling of the power wells.
4706 for_each_intel_crtc(dev
, crtc
) {
4707 enum intel_display_power_domain domain
;
4709 if (!crtc
->base
.enabled
)
4712 pipe_domains
[crtc
->pipe
] = get_crtc_power_domains(&crtc
->base
);
4714 for_each_power_domain(domain
, pipe_domains
[crtc
->pipe
])
4715 intel_display_power_get(dev_priv
, domain
);
4718 if (dev_priv
->display
.modeset_global_resources
)
4719 dev_priv
->display
.modeset_global_resources(dev
);
4721 for_each_intel_crtc(dev
, crtc
) {
4722 enum intel_display_power_domain domain
;
4724 for_each_power_domain(domain
, crtc
->enabled_power_domains
)
4725 intel_display_power_put(dev_priv
, domain
);
4727 crtc
->enabled_power_domains
= pipe_domains
[crtc
->pipe
];
4730 intel_display_set_init_power(dev_priv
, false);
4733 /* returns HPLL frequency in kHz */
4734 static int valleyview_get_vco(struct drm_i915_private
*dev_priv
)
4736 int hpll_freq
, vco_freq
[] = { 800, 1600, 2000, 2400 };
4738 /* Obtain SKU information */
4739 mutex_lock(&dev_priv
->dpio_lock
);
4740 hpll_freq
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
) &
4741 CCK_FUSE_HPLL_FREQ_MASK
;
4742 mutex_unlock(&dev_priv
->dpio_lock
);
4744 return vco_freq
[hpll_freq
] * 1000;
4747 static void vlv_update_cdclk(struct drm_device
*dev
)
4749 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4751 dev_priv
->vlv_cdclk_freq
= dev_priv
->display
.get_display_clock_speed(dev
);
4752 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4753 dev_priv
->vlv_cdclk_freq
);
4756 * Program the gmbus_freq based on the cdclk frequency.
4757 * BSpec erroneously claims we should aim for 4MHz, but
4758 * in fact 1MHz is the correct frequency.
4760 I915_WRITE(GMBUSFREQ_VLV
, DIV_ROUND_UP(dev_priv
->vlv_cdclk_freq
, 1000));
4763 /* Adjust CDclk dividers to allow high res or save power if possible */
4764 static void valleyview_set_cdclk(struct drm_device
*dev
, int cdclk
)
4766 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4769 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
) != dev_priv
->vlv_cdclk_freq
);
4771 if (cdclk
>= 320000) /* jump to highest voltage for 400MHz too */
4773 else if (cdclk
== 266667)
4778 mutex_lock(&dev_priv
->rps
.hw_lock
);
4779 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
4780 val
&= ~DSPFREQGUAR_MASK
;
4781 val
|= (cmd
<< DSPFREQGUAR_SHIFT
);
4782 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
4783 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
4784 DSPFREQSTAT_MASK
) == (cmd
<< DSPFREQSTAT_SHIFT
),
4786 DRM_ERROR("timed out waiting for CDclk change\n");
4788 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4790 if (cdclk
== 400000) {
4793 divider
= DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, cdclk
) - 1;
4795 mutex_lock(&dev_priv
->dpio_lock
);
4796 /* adjust cdclk divider */
4797 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
4798 val
&= ~DISPLAY_FREQUENCY_VALUES
;
4800 vlv_cck_write(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
, val
);
4802 if (wait_for((vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
) &
4803 DISPLAY_FREQUENCY_STATUS
) == (divider
<< DISPLAY_FREQUENCY_STATUS_SHIFT
),
4805 DRM_ERROR("timed out waiting for CDclk change\n");
4806 mutex_unlock(&dev_priv
->dpio_lock
);
4809 mutex_lock(&dev_priv
->dpio_lock
);
4810 /* adjust self-refresh exit latency value */
4811 val
= vlv_bunit_read(dev_priv
, BUNIT_REG_BISOC
);
4815 * For high bandwidth configs, we set a higher latency in the bunit
4816 * so that the core display fetch happens in time to avoid underruns.
4818 if (cdclk
== 400000)
4819 val
|= 4500 / 250; /* 4.5 usec */
4821 val
|= 3000 / 250; /* 3.0 usec */
4822 vlv_bunit_write(dev_priv
, BUNIT_REG_BISOC
, val
);
4823 mutex_unlock(&dev_priv
->dpio_lock
);
4825 vlv_update_cdclk(dev
);
4828 static void cherryview_set_cdclk(struct drm_device
*dev
, int cdclk
)
4830 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4833 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
) != dev_priv
->vlv_cdclk_freq
);
4850 MISSING_CASE(cdclk
);
4854 mutex_lock(&dev_priv
->rps
.hw_lock
);
4855 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
4856 val
&= ~DSPFREQGUAR_MASK_CHV
;
4857 val
|= (cmd
<< DSPFREQGUAR_SHIFT_CHV
);
4858 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
4859 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
4860 DSPFREQSTAT_MASK_CHV
) == (cmd
<< DSPFREQSTAT_SHIFT_CHV
),
4862 DRM_ERROR("timed out waiting for CDclk change\n");
4864 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4866 vlv_update_cdclk(dev
);
4869 static int valleyview_calc_cdclk(struct drm_i915_private
*dev_priv
,
4872 int freq_320
= (dev_priv
->hpll_freq
<< 1) % 320000 != 0 ? 333333 : 320000;
4874 /* FIXME: Punit isn't quite ready yet */
4875 if (IS_CHERRYVIEW(dev_priv
->dev
))
4879 * Really only a few cases to deal with, as only 4 CDclks are supported:
4882 * 320/333MHz (depends on HPLL freq)
4884 * So we check to see whether we're above 90% of the lower bin and
4887 * We seem to get an unstable or solid color picture at 200MHz.
4888 * Not sure what's wrong. For now use 200MHz only when all pipes
4891 if (max_pixclk
> freq_320
*9/10)
4893 else if (max_pixclk
> 266667*9/10)
4895 else if (max_pixclk
> 0)
4901 /* compute the max pixel clock for new configuration */
4902 static int intel_mode_max_pixclk(struct drm_i915_private
*dev_priv
)
4904 struct drm_device
*dev
= dev_priv
->dev
;
4905 struct intel_crtc
*intel_crtc
;
4908 for_each_intel_crtc(dev
, intel_crtc
) {
4909 if (intel_crtc
->new_enabled
)
4910 max_pixclk
= max(max_pixclk
,
4911 intel_crtc
->new_config
->base
.adjusted_mode
.crtc_clock
);
4917 static void valleyview_modeset_global_pipes(struct drm_device
*dev
,
4918 unsigned *prepare_pipes
)
4920 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4921 struct intel_crtc
*intel_crtc
;
4922 int max_pixclk
= intel_mode_max_pixclk(dev_priv
);
4924 if (valleyview_calc_cdclk(dev_priv
, max_pixclk
) ==
4925 dev_priv
->vlv_cdclk_freq
)
4928 /* disable/enable all currently active pipes while we change cdclk */
4929 for_each_intel_crtc(dev
, intel_crtc
)
4930 if (intel_crtc
->base
.enabled
)
4931 *prepare_pipes
|= (1 << intel_crtc
->pipe
);
4934 static void valleyview_modeset_global_resources(struct drm_device
*dev
)
4936 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4937 int max_pixclk
= intel_mode_max_pixclk(dev_priv
);
4938 int req_cdclk
= valleyview_calc_cdclk(dev_priv
, max_pixclk
);
4940 if (req_cdclk
!= dev_priv
->vlv_cdclk_freq
) {
4942 * FIXME: We can end up here with all power domains off, yet
4943 * with a CDCLK frequency other than the minimum. To account
4944 * for this take the PIPE-A power domain, which covers the HW
4945 * blocks needed for the following programming. This can be
4946 * removed once it's guaranteed that we get here either with
4947 * the minimum CDCLK set, or the required power domains
4950 intel_display_power_get(dev_priv
, POWER_DOMAIN_PIPE_A
);
4952 if (IS_CHERRYVIEW(dev
))
4953 cherryview_set_cdclk(dev
, req_cdclk
);
4955 valleyview_set_cdclk(dev
, req_cdclk
);
4957 intel_display_power_put(dev_priv
, POWER_DOMAIN_PIPE_A
);
4961 static void valleyview_crtc_enable(struct drm_crtc
*crtc
)
4963 struct drm_device
*dev
= crtc
->dev
;
4964 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4965 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4966 struct intel_encoder
*encoder
;
4967 int pipe
= intel_crtc
->pipe
;
4970 WARN_ON(!crtc
->enabled
);
4972 if (intel_crtc
->active
)
4975 is_dsi
= intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
);
4978 if (IS_CHERRYVIEW(dev
))
4979 chv_prepare_pll(intel_crtc
, intel_crtc
->config
);
4981 vlv_prepare_pll(intel_crtc
, intel_crtc
->config
);
4984 if (intel_crtc
->config
->has_dp_encoder
)
4985 intel_dp_set_m_n(intel_crtc
);
4987 intel_set_pipe_timings(intel_crtc
);
4989 if (IS_CHERRYVIEW(dev
) && pipe
== PIPE_B
) {
4990 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4992 I915_WRITE(CHV_BLEND(pipe
), CHV_BLEND_LEGACY
);
4993 I915_WRITE(CHV_CANVAS(pipe
), 0);
4996 i9xx_set_pipeconf(intel_crtc
);
4998 intel_crtc
->active
= true;
5000 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5002 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5003 if (encoder
->pre_pll_enable
)
5004 encoder
->pre_pll_enable(encoder
);
5007 if (IS_CHERRYVIEW(dev
))
5008 chv_enable_pll(intel_crtc
, intel_crtc
->config
);
5010 vlv_enable_pll(intel_crtc
, intel_crtc
->config
);
5013 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5014 if (encoder
->pre_enable
)
5015 encoder
->pre_enable(encoder
);
5017 i9xx_pfit_enable(intel_crtc
);
5019 intel_crtc_load_lut(crtc
);
5021 intel_update_watermarks(crtc
);
5022 intel_enable_pipe(intel_crtc
);
5024 assert_vblank_disabled(crtc
);
5025 drm_crtc_vblank_on(crtc
);
5027 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5028 encoder
->enable(encoder
);
5030 intel_crtc_enable_planes(crtc
);
5032 /* Underruns don't raise interrupts, so check manually. */
5033 i9xx_check_fifo_underruns(dev_priv
);
5036 static void i9xx_set_pll_dividers(struct intel_crtc
*crtc
)
5038 struct drm_device
*dev
= crtc
->base
.dev
;
5039 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5041 I915_WRITE(FP0(crtc
->pipe
), crtc
->config
->dpll_hw_state
.fp0
);
5042 I915_WRITE(FP1(crtc
->pipe
), crtc
->config
->dpll_hw_state
.fp1
);
5045 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
5047 struct drm_device
*dev
= crtc
->dev
;
5048 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5049 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5050 struct intel_encoder
*encoder
;
5051 int pipe
= intel_crtc
->pipe
;
5053 WARN_ON(!crtc
->enabled
);
5055 if (intel_crtc
->active
)
5058 i9xx_set_pll_dividers(intel_crtc
);
5060 if (intel_crtc
->config
->has_dp_encoder
)
5061 intel_dp_set_m_n(intel_crtc
);
5063 intel_set_pipe_timings(intel_crtc
);
5065 i9xx_set_pipeconf(intel_crtc
);
5067 intel_crtc
->active
= true;
5070 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5072 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5073 if (encoder
->pre_enable
)
5074 encoder
->pre_enable(encoder
);
5076 i9xx_enable_pll(intel_crtc
);
5078 i9xx_pfit_enable(intel_crtc
);
5080 intel_crtc_load_lut(crtc
);
5082 intel_update_watermarks(crtc
);
5083 intel_enable_pipe(intel_crtc
);
5085 assert_vblank_disabled(crtc
);
5086 drm_crtc_vblank_on(crtc
);
5088 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5089 encoder
->enable(encoder
);
5091 intel_crtc_enable_planes(crtc
);
5094 * Gen2 reports pipe underruns whenever all planes are disabled.
5095 * So don't enable underrun reporting before at least some planes
5097 * FIXME: Need to fix the logic to work when we turn off all planes
5098 * but leave the pipe running.
5101 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5103 /* Underruns don't raise interrupts, so check manually. */
5104 i9xx_check_fifo_underruns(dev_priv
);
5107 static void i9xx_pfit_disable(struct intel_crtc
*crtc
)
5109 struct drm_device
*dev
= crtc
->base
.dev
;
5110 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5112 if (!crtc
->config
->gmch_pfit
.control
)
5115 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
5117 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5118 I915_READ(PFIT_CONTROL
));
5119 I915_WRITE(PFIT_CONTROL
, 0);
5122 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
5124 struct drm_device
*dev
= crtc
->dev
;
5125 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5126 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5127 struct intel_encoder
*encoder
;
5128 int pipe
= intel_crtc
->pipe
;
5130 if (!intel_crtc
->active
)
5134 * Gen2 reports pipe underruns whenever all planes are disabled.
5135 * So diasble underrun reporting before all the planes get disabled.
5136 * FIXME: Need to fix the logic to work when we turn off all planes
5137 * but leave the pipe running.
5140 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
5143 * Vblank time updates from the shadow to live plane control register
5144 * are blocked if the memory self-refresh mode is active at that
5145 * moment. So to make sure the plane gets truly disabled, disable
5146 * first the self-refresh mode. The self-refresh enable bit in turn
5147 * will be checked/applied by the HW only at the next frame start
5148 * event which is after the vblank start event, so we need to have a
5149 * wait-for-vblank between disabling the plane and the pipe.
5151 intel_set_memory_cxsr(dev_priv
, false);
5152 intel_crtc_disable_planes(crtc
);
5155 * On gen2 planes are double buffered but the pipe isn't, so we must
5156 * wait for planes to fully turn off before disabling the pipe.
5157 * We also need to wait on all gmch platforms because of the
5158 * self-refresh mode constraint explained above.
5160 intel_wait_for_vblank(dev
, pipe
);
5162 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5163 encoder
->disable(encoder
);
5165 drm_crtc_vblank_off(crtc
);
5166 assert_vblank_disabled(crtc
);
5168 intel_disable_pipe(intel_crtc
);
5170 i9xx_pfit_disable(intel_crtc
);
5172 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5173 if (encoder
->post_disable
)
5174 encoder
->post_disable(encoder
);
5176 if (!intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
)) {
5177 if (IS_CHERRYVIEW(dev
))
5178 chv_disable_pll(dev_priv
, pipe
);
5179 else if (IS_VALLEYVIEW(dev
))
5180 vlv_disable_pll(dev_priv
, pipe
);
5182 i9xx_disable_pll(intel_crtc
);
5186 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
5188 intel_crtc
->active
= false;
5189 intel_update_watermarks(crtc
);
5191 mutex_lock(&dev
->struct_mutex
);
5192 intel_fbc_update(dev
);
5193 mutex_unlock(&dev
->struct_mutex
);
5196 static void i9xx_crtc_off(struct drm_crtc
*crtc
)
5200 /* Master function to enable/disable CRTC and corresponding power wells */
5201 void intel_crtc_control(struct drm_crtc
*crtc
, bool enable
)
5203 struct drm_device
*dev
= crtc
->dev
;
5204 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5205 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5206 enum intel_display_power_domain domain
;
5207 unsigned long domains
;
5210 if (!intel_crtc
->active
) {
5211 domains
= get_crtc_power_domains(crtc
);
5212 for_each_power_domain(domain
, domains
)
5213 intel_display_power_get(dev_priv
, domain
);
5214 intel_crtc
->enabled_power_domains
= domains
;
5216 dev_priv
->display
.crtc_enable(crtc
);
5219 if (intel_crtc
->active
) {
5220 dev_priv
->display
.crtc_disable(crtc
);
5222 domains
= intel_crtc
->enabled_power_domains
;
5223 for_each_power_domain(domain
, domains
)
5224 intel_display_power_put(dev_priv
, domain
);
5225 intel_crtc
->enabled_power_domains
= 0;
5231 * Sets the power management mode of the pipe and plane.
5233 void intel_crtc_update_dpms(struct drm_crtc
*crtc
)
5235 struct drm_device
*dev
= crtc
->dev
;
5236 struct intel_encoder
*intel_encoder
;
5237 bool enable
= false;
5239 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
5240 enable
|= intel_encoder
->connectors_active
;
5242 intel_crtc_control(crtc
, enable
);
5245 static void intel_crtc_disable(struct drm_crtc
*crtc
)
5247 struct drm_device
*dev
= crtc
->dev
;
5248 struct drm_connector
*connector
;
5249 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5251 /* crtc should still be enabled when we disable it. */
5252 WARN_ON(!crtc
->enabled
);
5254 dev_priv
->display
.crtc_disable(crtc
);
5255 dev_priv
->display
.off(crtc
);
5257 crtc
->primary
->funcs
->disable_plane(crtc
->primary
);
5259 /* Update computed state. */
5260 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
5261 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
5264 if (connector
->encoder
->crtc
!= crtc
)
5267 connector
->dpms
= DRM_MODE_DPMS_OFF
;
5268 to_intel_encoder(connector
->encoder
)->connectors_active
= false;
5272 void intel_encoder_destroy(struct drm_encoder
*encoder
)
5274 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
5276 drm_encoder_cleanup(encoder
);
5277 kfree(intel_encoder
);
5280 /* Simple dpms helper for encoders with just one connector, no cloning and only
5281 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5282 * state of the entire output pipe. */
5283 static void intel_encoder_dpms(struct intel_encoder
*encoder
, int mode
)
5285 if (mode
== DRM_MODE_DPMS_ON
) {
5286 encoder
->connectors_active
= true;
5288 intel_crtc_update_dpms(encoder
->base
.crtc
);
5290 encoder
->connectors_active
= false;
5292 intel_crtc_update_dpms(encoder
->base
.crtc
);
5296 /* Cross check the actual hw state with our own modeset state tracking (and it's
5297 * internal consistency). */
5298 static void intel_connector_check_state(struct intel_connector
*connector
)
5300 if (connector
->get_hw_state(connector
)) {
5301 struct intel_encoder
*encoder
= connector
->encoder
;
5302 struct drm_crtc
*crtc
;
5303 bool encoder_enabled
;
5306 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5307 connector
->base
.base
.id
,
5308 connector
->base
.name
);
5310 /* there is no real hw state for MST connectors */
5311 if (connector
->mst_port
)
5314 I915_STATE_WARN(connector
->base
.dpms
== DRM_MODE_DPMS_OFF
,
5315 "wrong connector dpms state\n");
5316 I915_STATE_WARN(connector
->base
.encoder
!= &encoder
->base
,
5317 "active connector not linked to encoder\n");
5320 I915_STATE_WARN(!encoder
->connectors_active
,
5321 "encoder->connectors_active not set\n");
5323 encoder_enabled
= encoder
->get_hw_state(encoder
, &pipe
);
5324 I915_STATE_WARN(!encoder_enabled
, "encoder not enabled\n");
5325 if (I915_STATE_WARN_ON(!encoder
->base
.crtc
))
5328 crtc
= encoder
->base
.crtc
;
5330 I915_STATE_WARN(!crtc
->enabled
, "crtc not enabled\n");
5331 I915_STATE_WARN(!to_intel_crtc(crtc
)->active
, "crtc not active\n");
5332 I915_STATE_WARN(pipe
!= to_intel_crtc(crtc
)->pipe
,
5333 "encoder active on the wrong pipe\n");
5338 /* Even simpler default implementation, if there's really no special case to
5340 void intel_connector_dpms(struct drm_connector
*connector
, int mode
)
5342 /* All the simple cases only support two dpms states. */
5343 if (mode
!= DRM_MODE_DPMS_ON
)
5344 mode
= DRM_MODE_DPMS_OFF
;
5346 if (mode
== connector
->dpms
)
5349 connector
->dpms
= mode
;
5351 /* Only need to change hw state when actually enabled */
5352 if (connector
->encoder
)
5353 intel_encoder_dpms(to_intel_encoder(connector
->encoder
), mode
);
5355 intel_modeset_check_state(connector
->dev
);
5358 /* Simple connector->get_hw_state implementation for encoders that support only
5359 * one connector and no cloning and hence the encoder state determines the state
5360 * of the connector. */
5361 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
5364 struct intel_encoder
*encoder
= connector
->encoder
;
5366 return encoder
->get_hw_state(encoder
, &pipe
);
5369 static bool ironlake_check_fdi_lanes(struct drm_device
*dev
, enum pipe pipe
,
5370 struct intel_crtc_state
*pipe_config
)
5372 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5373 struct intel_crtc
*pipe_B_crtc
=
5374 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
5376 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5377 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5378 if (pipe_config
->fdi_lanes
> 4) {
5379 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5380 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5384 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
5385 if (pipe_config
->fdi_lanes
> 2) {
5386 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5387 pipe_config
->fdi_lanes
);
5394 if (INTEL_INFO(dev
)->num_pipes
== 2)
5397 /* Ivybridge 3 pipe is really complicated */
5402 if (dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]->enabled
&&
5403 pipe_config
->fdi_lanes
> 2) {
5404 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5405 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5410 if (!pipe_has_enabled_pch(pipe_B_crtc
) ||
5411 pipe_B_crtc
->config
->fdi_lanes
<= 2) {
5412 if (pipe_config
->fdi_lanes
> 2) {
5413 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5414 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5418 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5428 static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc
,
5429 struct intel_crtc_state
*pipe_config
)
5431 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5432 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
5433 int lane
, link_bw
, fdi_dotclock
;
5434 bool setup_ok
, needs_recompute
= false;
5437 /* FDI is a binary signal running at ~2.7GHz, encoding
5438 * each output octet as 10 bits. The actual frequency
5439 * is stored as a divider into a 100MHz clock, and the
5440 * mode pixel clock is stored in units of 1KHz.
5441 * Hence the bw of each lane in terms of the mode signal
5444 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
5446 fdi_dotclock
= adjusted_mode
->crtc_clock
;
5448 lane
= ironlake_get_lanes_required(fdi_dotclock
, link_bw
,
5449 pipe_config
->pipe_bpp
);
5451 pipe_config
->fdi_lanes
= lane
;
5453 intel_link_compute_m_n(pipe_config
->pipe_bpp
, lane
, fdi_dotclock
,
5454 link_bw
, &pipe_config
->fdi_m_n
);
5456 setup_ok
= ironlake_check_fdi_lanes(intel_crtc
->base
.dev
,
5457 intel_crtc
->pipe
, pipe_config
);
5458 if (!setup_ok
&& pipe_config
->pipe_bpp
> 6*3) {
5459 pipe_config
->pipe_bpp
-= 2*3;
5460 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5461 pipe_config
->pipe_bpp
);
5462 needs_recompute
= true;
5463 pipe_config
->bw_constrained
= true;
5468 if (needs_recompute
)
5471 return setup_ok
? 0 : -EINVAL
;
5474 static void hsw_compute_ips_config(struct intel_crtc
*crtc
,
5475 struct intel_crtc_state
*pipe_config
)
5477 pipe_config
->ips_enabled
= i915
.enable_ips
&&
5478 hsw_crtc_supports_ips(crtc
) &&
5479 pipe_config
->pipe_bpp
<= 24;
5482 static int intel_crtc_compute_config(struct intel_crtc
*crtc
,
5483 struct intel_crtc_state
*pipe_config
)
5485 struct drm_device
*dev
= crtc
->base
.dev
;
5486 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5487 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
5489 /* FIXME should check pixel clock limits on all platforms */
5490 if (INTEL_INFO(dev
)->gen
< 4) {
5492 dev_priv
->display
.get_display_clock_speed(dev
);
5495 * Enable pixel doubling when the dot clock
5496 * is > 90% of the (display) core speed.
5498 * GDG double wide on either pipe,
5499 * otherwise pipe A only.
5501 if ((crtc
->pipe
== PIPE_A
|| IS_I915G(dev
)) &&
5502 adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10) {
5504 pipe_config
->double_wide
= true;
5507 if (adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10)
5512 * Pipe horizontal size must be even in:
5514 * - LVDS dual channel mode
5515 * - Double wide pipe
5517 if ((intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
5518 intel_is_dual_link_lvds(dev
)) || pipe_config
->double_wide
)
5519 pipe_config
->pipe_src_w
&= ~1;
5521 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5522 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5524 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
5525 adjusted_mode
->hsync_start
== adjusted_mode
->hdisplay
)
5528 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) && pipe_config
->pipe_bpp
> 10*3) {
5529 pipe_config
->pipe_bpp
= 10*3; /* 12bpc is gen5+ */
5530 } else if (INTEL_INFO(dev
)->gen
<= 4 && pipe_config
->pipe_bpp
> 8*3) {
5531 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5533 pipe_config
->pipe_bpp
= 8*3;
5537 hsw_compute_ips_config(crtc
, pipe_config
);
5539 if (pipe_config
->has_pch_encoder
)
5540 return ironlake_fdi_compute_config(crtc
, pipe_config
);
5545 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
5547 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5551 /* FIXME: Punit isn't quite ready yet */
5552 if (IS_CHERRYVIEW(dev
))
5555 if (dev_priv
->hpll_freq
== 0)
5556 dev_priv
->hpll_freq
= valleyview_get_vco(dev_priv
);
5558 mutex_lock(&dev_priv
->dpio_lock
);
5559 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
5560 mutex_unlock(&dev_priv
->dpio_lock
);
5562 divider
= val
& DISPLAY_FREQUENCY_VALUES
;
5564 WARN((val
& DISPLAY_FREQUENCY_STATUS
) !=
5565 (divider
<< DISPLAY_FREQUENCY_STATUS_SHIFT
),
5566 "cdclk change in progress\n");
5568 return DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, divider
+ 1);
5571 static int i945_get_display_clock_speed(struct drm_device
*dev
)
5576 static int i915_get_display_clock_speed(struct drm_device
*dev
)
5581 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
5586 static int pnv_get_display_clock_speed(struct drm_device
*dev
)
5590 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
5592 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
5593 case GC_DISPLAY_CLOCK_267_MHZ_PNV
:
5595 case GC_DISPLAY_CLOCK_333_MHZ_PNV
:
5597 case GC_DISPLAY_CLOCK_444_MHZ_PNV
:
5599 case GC_DISPLAY_CLOCK_200_MHZ_PNV
:
5602 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc
);
5603 case GC_DISPLAY_CLOCK_133_MHZ_PNV
:
5605 case GC_DISPLAY_CLOCK_167_MHZ_PNV
:
5610 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
5614 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
5616 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
5619 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
5620 case GC_DISPLAY_CLOCK_333_MHZ
:
5623 case GC_DISPLAY_CLOCK_190_200_MHZ
:
5629 static int i865_get_display_clock_speed(struct drm_device
*dev
)
5634 static int i855_get_display_clock_speed(struct drm_device
*dev
)
5637 /* Assume that the hardware is in the high speed state. This
5638 * should be the default.
5640 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
5641 case GC_CLOCK_133_200
:
5642 case GC_CLOCK_100_200
:
5644 case GC_CLOCK_166_250
:
5646 case GC_CLOCK_100_133
:
5650 /* Shouldn't happen */
5654 static int i830_get_display_clock_speed(struct drm_device
*dev
)
5660 intel_reduce_m_n_ratio(uint32_t *num
, uint32_t *den
)
5662 while (*num
> DATA_LINK_M_N_MASK
||
5663 *den
> DATA_LINK_M_N_MASK
) {
5669 static void compute_m_n(unsigned int m
, unsigned int n
,
5670 uint32_t *ret_m
, uint32_t *ret_n
)
5672 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
5673 *ret_m
= div_u64((uint64_t) m
* *ret_n
, n
);
5674 intel_reduce_m_n_ratio(ret_m
, ret_n
);
5678 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
5679 int pixel_clock
, int link_clock
,
5680 struct intel_link_m_n
*m_n
)
5684 compute_m_n(bits_per_pixel
* pixel_clock
,
5685 link_clock
* nlanes
* 8,
5686 &m_n
->gmch_m
, &m_n
->gmch_n
);
5688 compute_m_n(pixel_clock
, link_clock
,
5689 &m_n
->link_m
, &m_n
->link_n
);
5692 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
5694 if (i915
.panel_use_ssc
>= 0)
5695 return i915
.panel_use_ssc
!= 0;
5696 return dev_priv
->vbt
.lvds_use_ssc
5697 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
5700 static int i9xx_get_refclk(struct intel_crtc
*crtc
, int num_connectors
)
5702 struct drm_device
*dev
= crtc
->base
.dev
;
5703 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5706 if (IS_VALLEYVIEW(dev
)) {
5708 } else if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
) &&
5709 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
5710 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
5711 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
5712 } else if (!IS_GEN2(dev
)) {
5721 static uint32_t pnv_dpll_compute_fp(struct dpll
*dpll
)
5723 return (1 << dpll
->n
) << 16 | dpll
->m2
;
5726 static uint32_t i9xx_dpll_compute_fp(struct dpll
*dpll
)
5728 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
5731 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
5732 struct intel_crtc_state
*crtc_state
,
5733 intel_clock_t
*reduced_clock
)
5735 struct drm_device
*dev
= crtc
->base
.dev
;
5738 if (IS_PINEVIEW(dev
)) {
5739 fp
= pnv_dpll_compute_fp(&crtc_state
->dpll
);
5741 fp2
= pnv_dpll_compute_fp(reduced_clock
);
5743 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
5745 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
5748 crtc_state
->dpll_hw_state
.fp0
= fp
;
5750 crtc
->lowfreq_avail
= false;
5751 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
) &&
5752 reduced_clock
&& i915
.powersave
) {
5753 crtc_state
->dpll_hw_state
.fp1
= fp2
;
5754 crtc
->lowfreq_avail
= true;
5756 crtc_state
->dpll_hw_state
.fp1
= fp
;
5760 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
, enum pipe
5766 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5767 * and set it to a reasonable value instead.
5769 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
5770 reg_val
&= 0xffffff00;
5771 reg_val
|= 0x00000030;
5772 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
5774 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
5775 reg_val
&= 0x8cffffff;
5776 reg_val
= 0x8c000000;
5777 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
5779 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
5780 reg_val
&= 0xffffff00;
5781 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
5783 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
5784 reg_val
&= 0x00ffffff;
5785 reg_val
|= 0xb0000000;
5786 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
5789 static void intel_pch_transcoder_set_m_n(struct intel_crtc
*crtc
,
5790 struct intel_link_m_n
*m_n
)
5792 struct drm_device
*dev
= crtc
->base
.dev
;
5793 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5794 int pipe
= crtc
->pipe
;
5796 I915_WRITE(PCH_TRANS_DATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5797 I915_WRITE(PCH_TRANS_DATA_N1(pipe
), m_n
->gmch_n
);
5798 I915_WRITE(PCH_TRANS_LINK_M1(pipe
), m_n
->link_m
);
5799 I915_WRITE(PCH_TRANS_LINK_N1(pipe
), m_n
->link_n
);
5802 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
5803 struct intel_link_m_n
*m_n
,
5804 struct intel_link_m_n
*m2_n2
)
5806 struct drm_device
*dev
= crtc
->base
.dev
;
5807 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5808 int pipe
= crtc
->pipe
;
5809 enum transcoder transcoder
= crtc
->config
->cpu_transcoder
;
5811 if (INTEL_INFO(dev
)->gen
>= 5) {
5812 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5813 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
5814 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
5815 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
5816 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5817 * for gen < 8) and if DRRS is supported (to make sure the
5818 * registers are not unnecessarily accessed).
5820 if (m2_n2
&& INTEL_INFO(dev
)->gen
< 8 &&
5821 crtc
->config
->has_drrs
) {
5822 I915_WRITE(PIPE_DATA_M2(transcoder
),
5823 TU_SIZE(m2_n2
->tu
) | m2_n2
->gmch_m
);
5824 I915_WRITE(PIPE_DATA_N2(transcoder
), m2_n2
->gmch_n
);
5825 I915_WRITE(PIPE_LINK_M2(transcoder
), m2_n2
->link_m
);
5826 I915_WRITE(PIPE_LINK_N2(transcoder
), m2_n2
->link_n
);
5829 I915_WRITE(PIPE_DATA_M_G4X(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5830 I915_WRITE(PIPE_DATA_N_G4X(pipe
), m_n
->gmch_n
);
5831 I915_WRITE(PIPE_LINK_M_G4X(pipe
), m_n
->link_m
);
5832 I915_WRITE(PIPE_LINK_N_G4X(pipe
), m_n
->link_n
);
5836 void intel_dp_set_m_n(struct intel_crtc
*crtc
)
5838 if (crtc
->config
->has_pch_encoder
)
5839 intel_pch_transcoder_set_m_n(crtc
, &crtc
->config
->dp_m_n
);
5841 intel_cpu_transcoder_set_m_n(crtc
, &crtc
->config
->dp_m_n
,
5842 &crtc
->config
->dp_m2_n2
);
5845 static void vlv_update_pll(struct intel_crtc
*crtc
,
5846 struct intel_crtc_state
*pipe_config
)
5851 * Enable DPIO clock input. We should never disable the reference
5852 * clock for pipe B, since VGA hotplug / manual detection depends
5855 dpll
= DPLL_EXT_BUFFER_ENABLE_VLV
| DPLL_REFA_CLK_ENABLE_VLV
|
5856 DPLL_VGA_MODE_DIS
| DPLL_INTEGRATED_CLOCK_VLV
;
5857 /* We should never disable this, set it here for state tracking */
5858 if (crtc
->pipe
== PIPE_B
)
5859 dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
5860 dpll
|= DPLL_VCO_ENABLE
;
5861 pipe_config
->dpll_hw_state
.dpll
= dpll
;
5863 dpll_md
= (pipe_config
->pixel_multiplier
- 1)
5864 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
5865 pipe_config
->dpll_hw_state
.dpll_md
= dpll_md
;
5868 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
5869 const struct intel_crtc_state
*pipe_config
)
5871 struct drm_device
*dev
= crtc
->base
.dev
;
5872 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5873 int pipe
= crtc
->pipe
;
5875 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
5876 u32 coreclk
, reg_val
;
5878 mutex_lock(&dev_priv
->dpio_lock
);
5880 bestn
= pipe_config
->dpll
.n
;
5881 bestm1
= pipe_config
->dpll
.m1
;
5882 bestm2
= pipe_config
->dpll
.m2
;
5883 bestp1
= pipe_config
->dpll
.p1
;
5884 bestp2
= pipe_config
->dpll
.p2
;
5886 /* See eDP HDMI DPIO driver vbios notes doc */
5888 /* PLL B needs special handling */
5890 vlv_pllb_recal_opamp(dev_priv
, pipe
);
5892 /* Set up Tx target for periodic Rcomp update */
5893 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9_BCAST
, 0x0100000f);
5895 /* Disable target IRef on PLL */
5896 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW8(pipe
));
5897 reg_val
&= 0x00ffffff;
5898 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW8(pipe
), reg_val
);
5900 /* Disable fast lock */
5901 vlv_dpio_write(dev_priv
, pipe
, VLV_CMN_DW0
, 0x610);
5903 /* Set idtafcrecal before PLL is enabled */
5904 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
5905 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
5906 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
5907 mdiv
|= (1 << DPIO_K_SHIFT
);
5910 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5911 * but we don't support that).
5912 * Note: don't use the DAC post divider as it seems unstable.
5914 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
5915 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
5917 mdiv
|= DPIO_ENABLE_CALIBRATION
;
5918 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
5920 /* Set HBR and RBR LPF coefficients */
5921 if (pipe_config
->port_clock
== 162000 ||
5922 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
) ||
5923 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
))
5924 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
5927 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
5930 if (pipe_config
->has_dp_encoder
) {
5931 /* Use SSC source */
5933 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5936 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5938 } else { /* HDMI or VGA */
5939 /* Use bend source */
5941 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5944 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5948 coreclk
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW7(pipe
));
5949 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
5950 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
5951 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))
5952 coreclk
|= 0x01000000;
5953 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW7(pipe
), coreclk
);
5955 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW11(pipe
), 0x87871000);
5956 mutex_unlock(&dev_priv
->dpio_lock
);
5959 static void chv_update_pll(struct intel_crtc
*crtc
,
5960 struct intel_crtc_state
*pipe_config
)
5962 pipe_config
->dpll_hw_state
.dpll
= DPLL_SSC_REF_CLOCK_CHV
|
5963 DPLL_REFA_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
|
5965 if (crtc
->pipe
!= PIPE_A
)
5966 pipe_config
->dpll_hw_state
.dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
5968 pipe_config
->dpll_hw_state
.dpll_md
=
5969 (pipe_config
->pixel_multiplier
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
5972 static void chv_prepare_pll(struct intel_crtc
*crtc
,
5973 const struct intel_crtc_state
*pipe_config
)
5975 struct drm_device
*dev
= crtc
->base
.dev
;
5976 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5977 int pipe
= crtc
->pipe
;
5978 int dpll_reg
= DPLL(crtc
->pipe
);
5979 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
5980 u32 loopfilter
, intcoeff
;
5981 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
, bestm2_frac
;
5984 bestn
= pipe_config
->dpll
.n
;
5985 bestm2_frac
= pipe_config
->dpll
.m2
& 0x3fffff;
5986 bestm1
= pipe_config
->dpll
.m1
;
5987 bestm2
= pipe_config
->dpll
.m2
>> 22;
5988 bestp1
= pipe_config
->dpll
.p1
;
5989 bestp2
= pipe_config
->dpll
.p2
;
5992 * Enable Refclk and SSC
5994 I915_WRITE(dpll_reg
,
5995 pipe_config
->dpll_hw_state
.dpll
& ~DPLL_VCO_ENABLE
);
5997 mutex_lock(&dev_priv
->dpio_lock
);
5999 /* p1 and p2 divider */
6000 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW13(port
),
6001 5 << DPIO_CHV_S1_DIV_SHIFT
|
6002 bestp1
<< DPIO_CHV_P1_DIV_SHIFT
|
6003 bestp2
<< DPIO_CHV_P2_DIV_SHIFT
|
6004 1 << DPIO_CHV_K_DIV_SHIFT
);
6006 /* Feedback post-divider - m2 */
6007 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW0(port
), bestm2
);
6009 /* Feedback refclk divider - n and m1 */
6010 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW1(port
),
6011 DPIO_CHV_M1_DIV_BY_2
|
6012 1 << DPIO_CHV_N_DIV_SHIFT
);
6014 /* M2 fraction division */
6015 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW2(port
), bestm2_frac
);
6017 /* M2 fraction division enable */
6018 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW3(port
),
6019 DPIO_CHV_FRAC_DIV_EN
|
6020 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT
));
6023 refclk
= i9xx_get_refclk(crtc
, 0);
6024 loopfilter
= 5 << DPIO_CHV_PROP_COEFF_SHIFT
|
6025 2 << DPIO_CHV_GAIN_CTRL_SHIFT
;
6026 if (refclk
== 100000)
6028 else if (refclk
== 38400)
6032 loopfilter
|= intcoeff
<< DPIO_CHV_INT_COEFF_SHIFT
;
6033 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW6(port
), loopfilter
);
6036 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
),
6037 vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
)) |
6040 mutex_unlock(&dev_priv
->dpio_lock
);
6044 * vlv_force_pll_on - forcibly enable just the PLL
6045 * @dev_priv: i915 private structure
6046 * @pipe: pipe PLL to enable
6047 * @dpll: PLL configuration
6049 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6050 * in cases where we need the PLL enabled even when @pipe is not going to
6053 void vlv_force_pll_on(struct drm_device
*dev
, enum pipe pipe
,
6054 const struct dpll
*dpll
)
6056 struct intel_crtc
*crtc
=
6057 to_intel_crtc(intel_get_crtc_for_pipe(dev
, pipe
));
6058 struct intel_crtc_state pipe_config
= {
6059 .pixel_multiplier
= 1,
6063 if (IS_CHERRYVIEW(dev
)) {
6064 chv_update_pll(crtc
, &pipe_config
);
6065 chv_prepare_pll(crtc
, &pipe_config
);
6066 chv_enable_pll(crtc
, &pipe_config
);
6068 vlv_update_pll(crtc
, &pipe_config
);
6069 vlv_prepare_pll(crtc
, &pipe_config
);
6070 vlv_enable_pll(crtc
, &pipe_config
);
6075 * vlv_force_pll_off - forcibly disable just the PLL
6076 * @dev_priv: i915 private structure
6077 * @pipe: pipe PLL to disable
6079 * Disable the PLL for @pipe. To be used in cases where we need
6080 * the PLL enabled even when @pipe is not going to be enabled.
6082 void vlv_force_pll_off(struct drm_device
*dev
, enum pipe pipe
)
6084 if (IS_CHERRYVIEW(dev
))
6085 chv_disable_pll(to_i915(dev
), pipe
);
6087 vlv_disable_pll(to_i915(dev
), pipe
);
6090 static void i9xx_update_pll(struct intel_crtc
*crtc
,
6091 struct intel_crtc_state
*crtc_state
,
6092 intel_clock_t
*reduced_clock
,
6095 struct drm_device
*dev
= crtc
->base
.dev
;
6096 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6099 struct dpll
*clock
= &crtc_state
->dpll
;
6101 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
6103 is_sdvo
= intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_SDVO
) ||
6104 intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_HDMI
);
6106 dpll
= DPLL_VGA_MODE_DIS
;
6108 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
))
6109 dpll
|= DPLLB_MODE_LVDS
;
6111 dpll
|= DPLLB_MODE_DAC_SERIAL
;
6113 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
6114 dpll
|= (crtc_state
->pixel_multiplier
- 1)
6115 << SDVO_MULTIPLIER_SHIFT_HIRES
;
6119 dpll
|= DPLL_SDVO_HIGH_SPEED
;
6121 if (crtc_state
->has_dp_encoder
)
6122 dpll
|= DPLL_SDVO_HIGH_SPEED
;
6124 /* compute bitmask from p1 value */
6125 if (IS_PINEVIEW(dev
))
6126 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
6128 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
6129 if (IS_G4X(dev
) && reduced_clock
)
6130 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
6132 switch (clock
->p2
) {
6134 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
6137 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
6140 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
6143 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
6146 if (INTEL_INFO(dev
)->gen
>= 4)
6147 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
6149 if (crtc_state
->sdvo_tv_clock
)
6150 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
6151 else if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
) &&
6152 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
6153 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
6155 dpll
|= PLL_REF_INPUT_DREFCLK
;
6157 dpll
|= DPLL_VCO_ENABLE
;
6158 crtc_state
->dpll_hw_state
.dpll
= dpll
;
6160 if (INTEL_INFO(dev
)->gen
>= 4) {
6161 u32 dpll_md
= (crtc_state
->pixel_multiplier
- 1)
6162 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
6163 crtc_state
->dpll_hw_state
.dpll_md
= dpll_md
;
6167 static void i8xx_update_pll(struct intel_crtc
*crtc
,
6168 struct intel_crtc_state
*crtc_state
,
6169 intel_clock_t
*reduced_clock
,
6172 struct drm_device
*dev
= crtc
->base
.dev
;
6173 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6175 struct dpll
*clock
= &crtc_state
->dpll
;
6177 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
6179 dpll
= DPLL_VGA_MODE_DIS
;
6181 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
)) {
6182 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
6185 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
6187 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
6189 dpll
|= PLL_P2_DIVIDE_BY_4
;
6192 if (!IS_I830(dev
) && intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_DVO
))
6193 dpll
|= DPLL_DVO_2X_MODE
;
6195 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
) &&
6196 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
6197 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
6199 dpll
|= PLL_REF_INPUT_DREFCLK
;
6201 dpll
|= DPLL_VCO_ENABLE
;
6202 crtc_state
->dpll_hw_state
.dpll
= dpll
;
6205 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
)
6207 struct drm_device
*dev
= intel_crtc
->base
.dev
;
6208 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6209 enum pipe pipe
= intel_crtc
->pipe
;
6210 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
6211 struct drm_display_mode
*adjusted_mode
=
6212 &intel_crtc
->config
->base
.adjusted_mode
;
6213 uint32_t crtc_vtotal
, crtc_vblank_end
;
6216 /* We need to be careful not to changed the adjusted mode, for otherwise
6217 * the hw state checker will get angry at the mismatch. */
6218 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
6219 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
6221 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
6222 /* the chip adds 2 halflines automatically */
6224 crtc_vblank_end
-= 1;
6226 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
6227 vsyncshift
= (adjusted_mode
->crtc_htotal
- 1) / 2;
6229 vsyncshift
= adjusted_mode
->crtc_hsync_start
-
6230 adjusted_mode
->crtc_htotal
/ 2;
6232 vsyncshift
+= adjusted_mode
->crtc_htotal
;
6235 if (INTEL_INFO(dev
)->gen
> 3)
6236 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
6238 I915_WRITE(HTOTAL(cpu_transcoder
),
6239 (adjusted_mode
->crtc_hdisplay
- 1) |
6240 ((adjusted_mode
->crtc_htotal
- 1) << 16));
6241 I915_WRITE(HBLANK(cpu_transcoder
),
6242 (adjusted_mode
->crtc_hblank_start
- 1) |
6243 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
6244 I915_WRITE(HSYNC(cpu_transcoder
),
6245 (adjusted_mode
->crtc_hsync_start
- 1) |
6246 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
6248 I915_WRITE(VTOTAL(cpu_transcoder
),
6249 (adjusted_mode
->crtc_vdisplay
- 1) |
6250 ((crtc_vtotal
- 1) << 16));
6251 I915_WRITE(VBLANK(cpu_transcoder
),
6252 (adjusted_mode
->crtc_vblank_start
- 1) |
6253 ((crtc_vblank_end
- 1) << 16));
6254 I915_WRITE(VSYNC(cpu_transcoder
),
6255 (adjusted_mode
->crtc_vsync_start
- 1) |
6256 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
6258 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6259 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6260 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6262 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
6263 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
6264 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
6266 /* pipesrc controls the size that is scaled from, which should
6267 * always be the user's requested size.
6269 I915_WRITE(PIPESRC(pipe
),
6270 ((intel_crtc
->config
->pipe_src_w
- 1) << 16) |
6271 (intel_crtc
->config
->pipe_src_h
- 1));
6274 static void intel_get_pipe_timings(struct intel_crtc
*crtc
,
6275 struct intel_crtc_state
*pipe_config
)
6277 struct drm_device
*dev
= crtc
->base
.dev
;
6278 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6279 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
6282 tmp
= I915_READ(HTOTAL(cpu_transcoder
));
6283 pipe_config
->base
.adjusted_mode
.crtc_hdisplay
= (tmp
& 0xffff) + 1;
6284 pipe_config
->base
.adjusted_mode
.crtc_htotal
= ((tmp
>> 16) & 0xffff) + 1;
6285 tmp
= I915_READ(HBLANK(cpu_transcoder
));
6286 pipe_config
->base
.adjusted_mode
.crtc_hblank_start
= (tmp
& 0xffff) + 1;
6287 pipe_config
->base
.adjusted_mode
.crtc_hblank_end
= ((tmp
>> 16) & 0xffff) + 1;
6288 tmp
= I915_READ(HSYNC(cpu_transcoder
));
6289 pipe_config
->base
.adjusted_mode
.crtc_hsync_start
= (tmp
& 0xffff) + 1;
6290 pipe_config
->base
.adjusted_mode
.crtc_hsync_end
= ((tmp
>> 16) & 0xffff) + 1;
6292 tmp
= I915_READ(VTOTAL(cpu_transcoder
));
6293 pipe_config
->base
.adjusted_mode
.crtc_vdisplay
= (tmp
& 0xffff) + 1;
6294 pipe_config
->base
.adjusted_mode
.crtc_vtotal
= ((tmp
>> 16) & 0xffff) + 1;
6295 tmp
= I915_READ(VBLANK(cpu_transcoder
));
6296 pipe_config
->base
.adjusted_mode
.crtc_vblank_start
= (tmp
& 0xffff) + 1;
6297 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
= ((tmp
>> 16) & 0xffff) + 1;
6298 tmp
= I915_READ(VSYNC(cpu_transcoder
));
6299 pipe_config
->base
.adjusted_mode
.crtc_vsync_start
= (tmp
& 0xffff) + 1;
6300 pipe_config
->base
.adjusted_mode
.crtc_vsync_end
= ((tmp
>> 16) & 0xffff) + 1;
6302 if (I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_INTERLACE_MASK
) {
6303 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
6304 pipe_config
->base
.adjusted_mode
.crtc_vtotal
+= 1;
6305 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
+= 1;
6308 tmp
= I915_READ(PIPESRC(crtc
->pipe
));
6309 pipe_config
->pipe_src_h
= (tmp
& 0xffff) + 1;
6310 pipe_config
->pipe_src_w
= ((tmp
>> 16) & 0xffff) + 1;
6312 pipe_config
->base
.mode
.vdisplay
= pipe_config
->pipe_src_h
;
6313 pipe_config
->base
.mode
.hdisplay
= pipe_config
->pipe_src_w
;
6316 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
6317 struct intel_crtc_state
*pipe_config
)
6319 mode
->hdisplay
= pipe_config
->base
.adjusted_mode
.crtc_hdisplay
;
6320 mode
->htotal
= pipe_config
->base
.adjusted_mode
.crtc_htotal
;
6321 mode
->hsync_start
= pipe_config
->base
.adjusted_mode
.crtc_hsync_start
;
6322 mode
->hsync_end
= pipe_config
->base
.adjusted_mode
.crtc_hsync_end
;
6324 mode
->vdisplay
= pipe_config
->base
.adjusted_mode
.crtc_vdisplay
;
6325 mode
->vtotal
= pipe_config
->base
.adjusted_mode
.crtc_vtotal
;
6326 mode
->vsync_start
= pipe_config
->base
.adjusted_mode
.crtc_vsync_start
;
6327 mode
->vsync_end
= pipe_config
->base
.adjusted_mode
.crtc_vsync_end
;
6329 mode
->flags
= pipe_config
->base
.adjusted_mode
.flags
;
6331 mode
->clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
6332 mode
->flags
|= pipe_config
->base
.adjusted_mode
.flags
;
6335 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
)
6337 struct drm_device
*dev
= intel_crtc
->base
.dev
;
6338 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6343 if ((intel_crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
6344 (intel_crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
6345 pipeconf
|= I915_READ(PIPECONF(intel_crtc
->pipe
)) & PIPECONF_ENABLE
;
6347 if (intel_crtc
->config
->double_wide
)
6348 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
6350 /* only g4x and later have fancy bpc/dither controls */
6351 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
6352 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6353 if (intel_crtc
->config
->dither
&& intel_crtc
->config
->pipe_bpp
!= 30)
6354 pipeconf
|= PIPECONF_DITHER_EN
|
6355 PIPECONF_DITHER_TYPE_SP
;
6357 switch (intel_crtc
->config
->pipe_bpp
) {
6359 pipeconf
|= PIPECONF_6BPC
;
6362 pipeconf
|= PIPECONF_8BPC
;
6365 pipeconf
|= PIPECONF_10BPC
;
6368 /* Case prevented by intel_choose_pipe_bpp_dither. */
6373 if (HAS_PIPE_CXSR(dev
)) {
6374 if (intel_crtc
->lowfreq_avail
) {
6375 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6376 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
6378 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6382 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
6383 if (INTEL_INFO(dev
)->gen
< 4 ||
6384 intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
6385 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
6387 pipeconf
|= PIPECONF_INTERLACE_W_SYNC_SHIFT
;
6389 pipeconf
|= PIPECONF_PROGRESSIVE
;
6391 if (IS_VALLEYVIEW(dev
) && intel_crtc
->config
->limited_color_range
)
6392 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
6394 I915_WRITE(PIPECONF(intel_crtc
->pipe
), pipeconf
);
6395 POSTING_READ(PIPECONF(intel_crtc
->pipe
));
6398 static int i9xx_crtc_compute_clock(struct intel_crtc
*crtc
,
6399 struct intel_crtc_state
*crtc_state
)
6401 struct drm_device
*dev
= crtc
->base
.dev
;
6402 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6403 int refclk
, num_connectors
= 0;
6404 intel_clock_t clock
, reduced_clock
;
6405 bool ok
, has_reduced_clock
= false;
6406 bool is_lvds
= false, is_dsi
= false;
6407 struct intel_encoder
*encoder
;
6408 const intel_limit_t
*limit
;
6410 for_each_intel_encoder(dev
, encoder
) {
6411 if (encoder
->new_crtc
!= crtc
)
6414 switch (encoder
->type
) {
6415 case INTEL_OUTPUT_LVDS
:
6418 case INTEL_OUTPUT_DSI
:
6431 if (!crtc_state
->clock_set
) {
6432 refclk
= i9xx_get_refclk(crtc
, num_connectors
);
6435 * Returns a set of divisors for the desired target clock with
6436 * the given refclk, or FALSE. The returned values represent
6437 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6440 limit
= intel_limit(crtc
, refclk
);
6441 ok
= dev_priv
->display
.find_dpll(limit
, crtc
,
6442 crtc_state
->port_clock
,
6443 refclk
, NULL
, &clock
);
6445 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6449 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
6451 * Ensure we match the reduced clock's P to the target
6452 * clock. If the clocks don't match, we can't switch
6453 * the display clock by using the FP0/FP1. In such case
6454 * we will disable the LVDS downclock feature.
6457 dev_priv
->display
.find_dpll(limit
, crtc
,
6458 dev_priv
->lvds_downclock
,
6462 /* Compat-code for transition, will disappear. */
6463 crtc_state
->dpll
.n
= clock
.n
;
6464 crtc_state
->dpll
.m1
= clock
.m1
;
6465 crtc_state
->dpll
.m2
= clock
.m2
;
6466 crtc_state
->dpll
.p1
= clock
.p1
;
6467 crtc_state
->dpll
.p2
= clock
.p2
;
6471 i8xx_update_pll(crtc
, crtc_state
,
6472 has_reduced_clock
? &reduced_clock
: NULL
,
6474 } else if (IS_CHERRYVIEW(dev
)) {
6475 chv_update_pll(crtc
, crtc_state
);
6476 } else if (IS_VALLEYVIEW(dev
)) {
6477 vlv_update_pll(crtc
, crtc_state
);
6479 i9xx_update_pll(crtc
, crtc_state
,
6480 has_reduced_clock
? &reduced_clock
: NULL
,
6487 static void i9xx_get_pfit_config(struct intel_crtc
*crtc
,
6488 struct intel_crtc_state
*pipe_config
)
6490 struct drm_device
*dev
= crtc
->base
.dev
;
6491 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6494 if (INTEL_INFO(dev
)->gen
<= 3 && (IS_I830(dev
) || !IS_MOBILE(dev
)))
6497 tmp
= I915_READ(PFIT_CONTROL
);
6498 if (!(tmp
& PFIT_ENABLE
))
6501 /* Check whether the pfit is attached to our pipe. */
6502 if (INTEL_INFO(dev
)->gen
< 4) {
6503 if (crtc
->pipe
!= PIPE_B
)
6506 if ((tmp
& PFIT_PIPE_MASK
) != (crtc
->pipe
<< PFIT_PIPE_SHIFT
))
6510 pipe_config
->gmch_pfit
.control
= tmp
;
6511 pipe_config
->gmch_pfit
.pgm_ratios
= I915_READ(PFIT_PGM_RATIOS
);
6512 if (INTEL_INFO(dev
)->gen
< 5)
6513 pipe_config
->gmch_pfit
.lvds_border_bits
=
6514 I915_READ(LVDS
) & LVDS_BORDER_ENABLE
;
6517 static void vlv_crtc_clock_get(struct intel_crtc
*crtc
,
6518 struct intel_crtc_state
*pipe_config
)
6520 struct drm_device
*dev
= crtc
->base
.dev
;
6521 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6522 int pipe
= pipe_config
->cpu_transcoder
;
6523 intel_clock_t clock
;
6525 int refclk
= 100000;
6527 /* In case of MIPI DPLL will not even be used */
6528 if (!(pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
))
6531 mutex_lock(&dev_priv
->dpio_lock
);
6532 mdiv
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW3(pipe
));
6533 mutex_unlock(&dev_priv
->dpio_lock
);
6535 clock
.m1
= (mdiv
>> DPIO_M1DIV_SHIFT
) & 7;
6536 clock
.m2
= mdiv
& DPIO_M2DIV_MASK
;
6537 clock
.n
= (mdiv
>> DPIO_N_SHIFT
) & 0xf;
6538 clock
.p1
= (mdiv
>> DPIO_P1_SHIFT
) & 7;
6539 clock
.p2
= (mdiv
>> DPIO_P2_SHIFT
) & 0x1f;
6541 vlv_clock(refclk
, &clock
);
6543 /* clock.dot is the fast clock */
6544 pipe_config
->port_clock
= clock
.dot
/ 5;
6547 static void i9xx_get_plane_config(struct intel_crtc
*crtc
,
6548 struct intel_plane_config
*plane_config
)
6550 struct drm_device
*dev
= crtc
->base
.dev
;
6551 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6552 u32 val
, base
, offset
;
6553 int pipe
= crtc
->pipe
, plane
= crtc
->plane
;
6554 int fourcc
, pixel_format
;
6557 crtc
->base
.primary
->fb
= kzalloc(sizeof(struct intel_framebuffer
), GFP_KERNEL
);
6558 if (!crtc
->base
.primary
->fb
) {
6559 DRM_DEBUG_KMS("failed to alloc fb\n");
6563 val
= I915_READ(DSPCNTR(plane
));
6565 if (INTEL_INFO(dev
)->gen
>= 4)
6566 if (val
& DISPPLANE_TILED
)
6567 plane_config
->tiling
= I915_TILING_X
;
6569 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
6570 fourcc
= intel_format_to_fourcc(pixel_format
);
6571 crtc
->base
.primary
->fb
->pixel_format
= fourcc
;
6572 crtc
->base
.primary
->fb
->bits_per_pixel
=
6573 drm_format_plane_cpp(fourcc
, 0) * 8;
6575 if (INTEL_INFO(dev
)->gen
>= 4) {
6576 if (plane_config
->tiling
)
6577 offset
= I915_READ(DSPTILEOFF(plane
));
6579 offset
= I915_READ(DSPLINOFF(plane
));
6580 base
= I915_READ(DSPSURF(plane
)) & 0xfffff000;
6582 base
= I915_READ(DSPADDR(plane
));
6584 plane_config
->base
= base
;
6586 val
= I915_READ(PIPESRC(pipe
));
6587 crtc
->base
.primary
->fb
->width
= ((val
>> 16) & 0xfff) + 1;
6588 crtc
->base
.primary
->fb
->height
= ((val
>> 0) & 0xfff) + 1;
6590 val
= I915_READ(DSPSTRIDE(pipe
));
6591 crtc
->base
.primary
->fb
->pitches
[0] = val
& 0xffffffc0;
6593 aligned_height
= intel_align_height(dev
, crtc
->base
.primary
->fb
->height
,
6594 plane_config
->tiling
);
6596 plane_config
->size
= PAGE_ALIGN(crtc
->base
.primary
->fb
->pitches
[0] *
6599 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6600 pipe
, plane
, crtc
->base
.primary
->fb
->width
,
6601 crtc
->base
.primary
->fb
->height
,
6602 crtc
->base
.primary
->fb
->bits_per_pixel
, base
,
6603 crtc
->base
.primary
->fb
->pitches
[0],
6604 plane_config
->size
);
6608 static void chv_crtc_clock_get(struct intel_crtc
*crtc
,
6609 struct intel_crtc_state
*pipe_config
)
6611 struct drm_device
*dev
= crtc
->base
.dev
;
6612 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6613 int pipe
= pipe_config
->cpu_transcoder
;
6614 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
6615 intel_clock_t clock
;
6616 u32 cmn_dw13
, pll_dw0
, pll_dw1
, pll_dw2
;
6617 int refclk
= 100000;
6619 mutex_lock(&dev_priv
->dpio_lock
);
6620 cmn_dw13
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW13(port
));
6621 pll_dw0
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW0(port
));
6622 pll_dw1
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW1(port
));
6623 pll_dw2
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW2(port
));
6624 mutex_unlock(&dev_priv
->dpio_lock
);
6626 clock
.m1
= (pll_dw1
& 0x7) == DPIO_CHV_M1_DIV_BY_2
? 2 : 0;
6627 clock
.m2
= ((pll_dw0
& 0xff) << 22) | (pll_dw2
& 0x3fffff);
6628 clock
.n
= (pll_dw1
>> DPIO_CHV_N_DIV_SHIFT
) & 0xf;
6629 clock
.p1
= (cmn_dw13
>> DPIO_CHV_P1_DIV_SHIFT
) & 0x7;
6630 clock
.p2
= (cmn_dw13
>> DPIO_CHV_P2_DIV_SHIFT
) & 0x1f;
6632 chv_clock(refclk
, &clock
);
6634 /* clock.dot is the fast clock */
6635 pipe_config
->port_clock
= clock
.dot
/ 5;
6638 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
6639 struct intel_crtc_state
*pipe_config
)
6641 struct drm_device
*dev
= crtc
->base
.dev
;
6642 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6645 if (!intel_display_power_is_enabled(dev_priv
,
6646 POWER_DOMAIN_PIPE(crtc
->pipe
)))
6649 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
6650 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
6652 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
6653 if (!(tmp
& PIPECONF_ENABLE
))
6656 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
6657 switch (tmp
& PIPECONF_BPC_MASK
) {
6659 pipe_config
->pipe_bpp
= 18;
6662 pipe_config
->pipe_bpp
= 24;
6664 case PIPECONF_10BPC
:
6665 pipe_config
->pipe_bpp
= 30;
6672 if (IS_VALLEYVIEW(dev
) && (tmp
& PIPECONF_COLOR_RANGE_SELECT
))
6673 pipe_config
->limited_color_range
= true;
6675 if (INTEL_INFO(dev
)->gen
< 4)
6676 pipe_config
->double_wide
= tmp
& PIPECONF_DOUBLE_WIDE
;
6678 intel_get_pipe_timings(crtc
, pipe_config
);
6680 i9xx_get_pfit_config(crtc
, pipe_config
);
6682 if (INTEL_INFO(dev
)->gen
>= 4) {
6683 tmp
= I915_READ(DPLL_MD(crtc
->pipe
));
6684 pipe_config
->pixel_multiplier
=
6685 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
6686 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
6687 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
6688 } else if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
6689 tmp
= I915_READ(DPLL(crtc
->pipe
));
6690 pipe_config
->pixel_multiplier
=
6691 ((tmp
& SDVO_MULTIPLIER_MASK
)
6692 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
6694 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6695 * port and will be fixed up in the encoder->get_config
6697 pipe_config
->pixel_multiplier
= 1;
6699 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(crtc
->pipe
));
6700 if (!IS_VALLEYVIEW(dev
)) {
6702 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6703 * on 830. Filter it out here so that we don't
6704 * report errors due to that.
6707 pipe_config
->dpll_hw_state
.dpll
&= ~DPLL_DVO_2X_MODE
;
6709 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(crtc
->pipe
));
6710 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(crtc
->pipe
));
6712 /* Mask out read-only status bits. */
6713 pipe_config
->dpll_hw_state
.dpll
&= ~(DPLL_LOCK_VLV
|
6714 DPLL_PORTC_READY_MASK
|
6715 DPLL_PORTB_READY_MASK
);
6718 if (IS_CHERRYVIEW(dev
))
6719 chv_crtc_clock_get(crtc
, pipe_config
);
6720 else if (IS_VALLEYVIEW(dev
))
6721 vlv_crtc_clock_get(crtc
, pipe_config
);
6723 i9xx_crtc_clock_get(crtc
, pipe_config
);
6728 static void ironlake_init_pch_refclk(struct drm_device
*dev
)
6730 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6731 struct intel_encoder
*encoder
;
6733 bool has_lvds
= false;
6734 bool has_cpu_edp
= false;
6735 bool has_panel
= false;
6736 bool has_ck505
= false;
6737 bool can_ssc
= false;
6739 /* We need to take the global config into account */
6740 for_each_intel_encoder(dev
, encoder
) {
6741 switch (encoder
->type
) {
6742 case INTEL_OUTPUT_LVDS
:
6746 case INTEL_OUTPUT_EDP
:
6748 if (enc_to_dig_port(&encoder
->base
)->port
== PORT_A
)
6756 if (HAS_PCH_IBX(dev
)) {
6757 has_ck505
= dev_priv
->vbt
.display_clock_mode
;
6758 can_ssc
= has_ck505
;
6764 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6765 has_panel
, has_lvds
, has_ck505
);
6767 /* Ironlake: try to setup display ref clock before DPLL
6768 * enabling. This is only under driver's control after
6769 * PCH B stepping, previous chipset stepping should be
6770 * ignoring this setting.
6772 val
= I915_READ(PCH_DREF_CONTROL
);
6774 /* As we must carefully and slowly disable/enable each source in turn,
6775 * compute the final state we want first and check if we need to
6776 * make any changes at all.
6779 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
6781 final
|= DREF_NONSPREAD_CK505_ENABLE
;
6783 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
6785 final
&= ~DREF_SSC_SOURCE_MASK
;
6786 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
6787 final
&= ~DREF_SSC1_ENABLE
;
6790 final
|= DREF_SSC_SOURCE_ENABLE
;
6792 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
6793 final
|= DREF_SSC1_ENABLE
;
6796 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
6797 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
6799 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
6801 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6803 final
|= DREF_SSC_SOURCE_DISABLE
;
6804 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6810 /* Always enable nonspread source */
6811 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
6814 val
|= DREF_NONSPREAD_CK505_ENABLE
;
6816 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
6819 val
&= ~DREF_SSC_SOURCE_MASK
;
6820 val
|= DREF_SSC_SOURCE_ENABLE
;
6822 /* SSC must be turned on before enabling the CPU output */
6823 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
6824 DRM_DEBUG_KMS("Using SSC on panel\n");
6825 val
|= DREF_SSC1_ENABLE
;
6827 val
&= ~DREF_SSC1_ENABLE
;
6829 /* Get SSC going before enabling the outputs */
6830 I915_WRITE(PCH_DREF_CONTROL
, val
);
6831 POSTING_READ(PCH_DREF_CONTROL
);
6834 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
6836 /* Enable CPU source on CPU attached eDP */
6838 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
6839 DRM_DEBUG_KMS("Using SSC on eDP\n");
6840 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
6842 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
6844 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6846 I915_WRITE(PCH_DREF_CONTROL
, val
);
6847 POSTING_READ(PCH_DREF_CONTROL
);
6850 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6852 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
6854 /* Turn off CPU output */
6855 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6857 I915_WRITE(PCH_DREF_CONTROL
, val
);
6858 POSTING_READ(PCH_DREF_CONTROL
);
6861 /* Turn off the SSC source */
6862 val
&= ~DREF_SSC_SOURCE_MASK
;
6863 val
|= DREF_SSC_SOURCE_DISABLE
;
6866 val
&= ~DREF_SSC1_ENABLE
;
6868 I915_WRITE(PCH_DREF_CONTROL
, val
);
6869 POSTING_READ(PCH_DREF_CONTROL
);
6873 BUG_ON(val
!= final
);
6876 static void lpt_reset_fdi_mphy(struct drm_i915_private
*dev_priv
)
6880 tmp
= I915_READ(SOUTH_CHICKEN2
);
6881 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
6882 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
6884 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2
) &
6885 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
6886 DRM_ERROR("FDI mPHY reset assert timeout\n");
6888 tmp
= I915_READ(SOUTH_CHICKEN2
);
6889 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
6890 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
6892 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2
) &
6893 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0, 100))
6894 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6897 /* WaMPhyProgramming:hsw */
6898 static void lpt_program_fdi_mphy(struct drm_i915_private
*dev_priv
)
6902 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
6903 tmp
&= ~(0xFF << 24);
6904 tmp
|= (0x12 << 24);
6905 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
6907 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
6909 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
6911 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
6913 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
6915 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
6916 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
6917 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
6919 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
6920 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
6921 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
6923 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
6926 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
6928 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
6931 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
6933 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
6936 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
6938 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
6941 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
6943 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
6944 tmp
&= ~(0xFF << 16);
6945 tmp
|= (0x1C << 16);
6946 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
6948 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
6949 tmp
&= ~(0xFF << 16);
6950 tmp
|= (0x1C << 16);
6951 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
6953 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
6955 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
6957 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
6959 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
6961 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
6962 tmp
&= ~(0xF << 28);
6964 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
6966 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
6967 tmp
&= ~(0xF << 28);
6969 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
6972 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6973 * Programming" based on the parameters passed:
6974 * - Sequence to enable CLKOUT_DP
6975 * - Sequence to enable CLKOUT_DP without spread
6976 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6978 static void lpt_enable_clkout_dp(struct drm_device
*dev
, bool with_spread
,
6981 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6984 if (WARN(with_fdi
&& !with_spread
, "FDI requires downspread\n"))
6986 if (WARN(dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
&&
6987 with_fdi
, "LP PCH doesn't have FDI\n"))
6990 mutex_lock(&dev_priv
->dpio_lock
);
6992 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
6993 tmp
&= ~SBI_SSCCTL_DISABLE
;
6994 tmp
|= SBI_SSCCTL_PATHALT
;
6995 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
7000 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
7001 tmp
&= ~SBI_SSCCTL_PATHALT
;
7002 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
7005 lpt_reset_fdi_mphy(dev_priv
);
7006 lpt_program_fdi_mphy(dev_priv
);
7010 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
7011 SBI_GEN0
: SBI_DBUFF0
;
7012 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
7013 tmp
|= SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
7014 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
7016 mutex_unlock(&dev_priv
->dpio_lock
);
7019 /* Sequence to disable CLKOUT_DP */
7020 static void lpt_disable_clkout_dp(struct drm_device
*dev
)
7022 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7025 mutex_lock(&dev_priv
->dpio_lock
);
7027 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
7028 SBI_GEN0
: SBI_DBUFF0
;
7029 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
7030 tmp
&= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
7031 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
7033 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
7034 if (!(tmp
& SBI_SSCCTL_DISABLE
)) {
7035 if (!(tmp
& SBI_SSCCTL_PATHALT
)) {
7036 tmp
|= SBI_SSCCTL_PATHALT
;
7037 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
7040 tmp
|= SBI_SSCCTL_DISABLE
;
7041 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
7044 mutex_unlock(&dev_priv
->dpio_lock
);
7047 static void lpt_init_pch_refclk(struct drm_device
*dev
)
7049 struct intel_encoder
*encoder
;
7050 bool has_vga
= false;
7052 for_each_intel_encoder(dev
, encoder
) {
7053 switch (encoder
->type
) {
7054 case INTEL_OUTPUT_ANALOG
:
7063 lpt_enable_clkout_dp(dev
, true, true);
7065 lpt_disable_clkout_dp(dev
);
7069 * Initialize reference clocks when the driver loads
7071 void intel_init_pch_refclk(struct drm_device
*dev
)
7073 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
7074 ironlake_init_pch_refclk(dev
);
7075 else if (HAS_PCH_LPT(dev
))
7076 lpt_init_pch_refclk(dev
);
7079 static int ironlake_get_refclk(struct drm_crtc
*crtc
)
7081 struct drm_device
*dev
= crtc
->dev
;
7082 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7083 struct intel_encoder
*encoder
;
7084 int num_connectors
= 0;
7085 bool is_lvds
= false;
7087 for_each_intel_encoder(dev
, encoder
) {
7088 if (encoder
->new_crtc
!= to_intel_crtc(crtc
))
7091 switch (encoder
->type
) {
7092 case INTEL_OUTPUT_LVDS
:
7101 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
7102 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7103 dev_priv
->vbt
.lvds_ssc_freq
);
7104 return dev_priv
->vbt
.lvds_ssc_freq
;
7110 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
)
7112 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
7113 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7114 int pipe
= intel_crtc
->pipe
;
7119 switch (intel_crtc
->config
->pipe_bpp
) {
7121 val
|= PIPECONF_6BPC
;
7124 val
|= PIPECONF_8BPC
;
7127 val
|= PIPECONF_10BPC
;
7130 val
|= PIPECONF_12BPC
;
7133 /* Case prevented by intel_choose_pipe_bpp_dither. */
7137 if (intel_crtc
->config
->dither
)
7138 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
7140 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
7141 val
|= PIPECONF_INTERLACED_ILK
;
7143 val
|= PIPECONF_PROGRESSIVE
;
7145 if (intel_crtc
->config
->limited_color_range
)
7146 val
|= PIPECONF_COLOR_RANGE_SELECT
;
7148 I915_WRITE(PIPECONF(pipe
), val
);
7149 POSTING_READ(PIPECONF(pipe
));
7153 * Set up the pipe CSC unit.
7155 * Currently only full range RGB to limited range RGB conversion
7156 * is supported, but eventually this should handle various
7157 * RGB<->YCbCr scenarios as well.
7159 static void intel_set_pipe_csc(struct drm_crtc
*crtc
)
7161 struct drm_device
*dev
= crtc
->dev
;
7162 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7163 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7164 int pipe
= intel_crtc
->pipe
;
7165 uint16_t coeff
= 0x7800; /* 1.0 */
7168 * TODO: Check what kind of values actually come out of the pipe
7169 * with these coeff/postoff values and adjust to get the best
7170 * accuracy. Perhaps we even need to take the bpc value into
7174 if (intel_crtc
->config
->limited_color_range
)
7175 coeff
= ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7178 * GY/GU and RY/RU should be the other way around according
7179 * to BSpec, but reality doesn't agree. Just set them up in
7180 * a way that results in the correct picture.
7182 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe
), coeff
<< 16);
7183 I915_WRITE(PIPE_CSC_COEFF_BY(pipe
), 0);
7185 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe
), coeff
);
7186 I915_WRITE(PIPE_CSC_COEFF_BU(pipe
), 0);
7188 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe
), 0);
7189 I915_WRITE(PIPE_CSC_COEFF_BV(pipe
), coeff
<< 16);
7191 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe
), 0);
7192 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe
), 0);
7193 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe
), 0);
7195 if (INTEL_INFO(dev
)->gen
> 6) {
7196 uint16_t postoff
= 0;
7198 if (intel_crtc
->config
->limited_color_range
)
7199 postoff
= (16 * (1 << 12) / 255) & 0x1fff;
7201 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe
), postoff
);
7202 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe
), postoff
);
7203 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe
), postoff
);
7205 I915_WRITE(PIPE_CSC_MODE(pipe
), 0);
7207 uint32_t mode
= CSC_MODE_YUV_TO_RGB
;
7209 if (intel_crtc
->config
->limited_color_range
)
7210 mode
|= CSC_BLACK_SCREEN_OFFSET
;
7212 I915_WRITE(PIPE_CSC_MODE(pipe
), mode
);
7216 static void haswell_set_pipeconf(struct drm_crtc
*crtc
)
7218 struct drm_device
*dev
= crtc
->dev
;
7219 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7220 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7221 enum pipe pipe
= intel_crtc
->pipe
;
7222 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
7227 if (IS_HASWELL(dev
) && intel_crtc
->config
->dither
)
7228 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
7230 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
7231 val
|= PIPECONF_INTERLACED_ILK
;
7233 val
|= PIPECONF_PROGRESSIVE
;
7235 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
7236 POSTING_READ(PIPECONF(cpu_transcoder
));
7238 I915_WRITE(GAMMA_MODE(intel_crtc
->pipe
), GAMMA_MODE_MODE_8BIT
);
7239 POSTING_READ(GAMMA_MODE(intel_crtc
->pipe
));
7241 if (IS_BROADWELL(dev
) || INTEL_INFO(dev
)->gen
>= 9) {
7244 switch (intel_crtc
->config
->pipe_bpp
) {
7246 val
|= PIPEMISC_DITHER_6_BPC
;
7249 val
|= PIPEMISC_DITHER_8_BPC
;
7252 val
|= PIPEMISC_DITHER_10_BPC
;
7255 val
|= PIPEMISC_DITHER_12_BPC
;
7258 /* Case prevented by pipe_config_set_bpp. */
7262 if (intel_crtc
->config
->dither
)
7263 val
|= PIPEMISC_DITHER_ENABLE
| PIPEMISC_DITHER_TYPE_SP
;
7265 I915_WRITE(PIPEMISC(pipe
), val
);
7269 static bool ironlake_compute_clocks(struct drm_crtc
*crtc
,
7270 struct intel_crtc_state
*crtc_state
,
7271 intel_clock_t
*clock
,
7272 bool *has_reduced_clock
,
7273 intel_clock_t
*reduced_clock
)
7275 struct drm_device
*dev
= crtc
->dev
;
7276 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7277 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7279 const intel_limit_t
*limit
;
7280 bool ret
, is_lvds
= false;
7282 is_lvds
= intel_pipe_will_have_type(intel_crtc
, INTEL_OUTPUT_LVDS
);
7284 refclk
= ironlake_get_refclk(crtc
);
7287 * Returns a set of divisors for the desired target clock with the given
7288 * refclk, or FALSE. The returned values represent the clock equation:
7289 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7291 limit
= intel_limit(intel_crtc
, refclk
);
7292 ret
= dev_priv
->display
.find_dpll(limit
, intel_crtc
,
7293 crtc_state
->port_clock
,
7294 refclk
, NULL
, clock
);
7298 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
7300 * Ensure we match the reduced clock's P to the target clock.
7301 * If the clocks don't match, we can't switch the display clock
7302 * by using the FP0/FP1. In such case we will disable the LVDS
7303 * downclock feature.
7305 *has_reduced_clock
=
7306 dev_priv
->display
.find_dpll(limit
, intel_crtc
,
7307 dev_priv
->lvds_downclock
,
7315 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
7318 * Account for spread spectrum to avoid
7319 * oversubscribing the link. Max center spread
7320 * is 2.5%; use 5% for safety's sake.
7322 u32 bps
= target_clock
* bpp
* 21 / 20;
7323 return DIV_ROUND_UP(bps
, link_bw
* 8);
7326 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
7328 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
7331 static uint32_t ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
7332 struct intel_crtc_state
*crtc_state
,
7334 intel_clock_t
*reduced_clock
, u32
*fp2
)
7336 struct drm_crtc
*crtc
= &intel_crtc
->base
;
7337 struct drm_device
*dev
= crtc
->dev
;
7338 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7339 struct intel_encoder
*intel_encoder
;
7341 int factor
, num_connectors
= 0;
7342 bool is_lvds
= false, is_sdvo
= false;
7344 for_each_intel_encoder(dev
, intel_encoder
) {
7345 if (intel_encoder
->new_crtc
!= to_intel_crtc(crtc
))
7348 switch (intel_encoder
->type
) {
7349 case INTEL_OUTPUT_LVDS
:
7352 case INTEL_OUTPUT_SDVO
:
7353 case INTEL_OUTPUT_HDMI
:
7363 /* Enable autotuning of the PLL clock (if permissible) */
7366 if ((intel_panel_use_ssc(dev_priv
) &&
7367 dev_priv
->vbt
.lvds_ssc_freq
== 100000) ||
7368 (HAS_PCH_IBX(dev
) && intel_is_dual_link_lvds(dev
)))
7370 } else if (crtc_state
->sdvo_tv_clock
)
7373 if (ironlake_needs_fb_cb_tune(&crtc_state
->dpll
, factor
))
7376 if (fp2
&& (reduced_clock
->m
< factor
* reduced_clock
->n
))
7382 dpll
|= DPLLB_MODE_LVDS
;
7384 dpll
|= DPLLB_MODE_DAC_SERIAL
;
7386 dpll
|= (crtc_state
->pixel_multiplier
- 1)
7387 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
7390 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7391 if (crtc_state
->has_dp_encoder
)
7392 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7394 /* compute bitmask from p1 value */
7395 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7397 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
7399 switch (crtc_state
->dpll
.p2
) {
7401 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
7404 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
7407 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
7410 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
7414 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
7415 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
7417 dpll
|= PLL_REF_INPUT_DREFCLK
;
7419 return dpll
| DPLL_VCO_ENABLE
;
7422 static int ironlake_crtc_compute_clock(struct intel_crtc
*crtc
,
7423 struct intel_crtc_state
*crtc_state
)
7425 struct drm_device
*dev
= crtc
->base
.dev
;
7426 intel_clock_t clock
, reduced_clock
;
7427 u32 dpll
= 0, fp
= 0, fp2
= 0;
7428 bool ok
, has_reduced_clock
= false;
7429 bool is_lvds
= false;
7430 struct intel_shared_dpll
*pll
;
7432 is_lvds
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
);
7434 WARN(!(HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)),
7435 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev
));
7437 ok
= ironlake_compute_clocks(&crtc
->base
, crtc_state
, &clock
,
7438 &has_reduced_clock
, &reduced_clock
);
7439 if (!ok
&& !crtc_state
->clock_set
) {
7440 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7443 /* Compat-code for transition, will disappear. */
7444 if (!crtc_state
->clock_set
) {
7445 crtc_state
->dpll
.n
= clock
.n
;
7446 crtc_state
->dpll
.m1
= clock
.m1
;
7447 crtc_state
->dpll
.m2
= clock
.m2
;
7448 crtc_state
->dpll
.p1
= clock
.p1
;
7449 crtc_state
->dpll
.p2
= clock
.p2
;
7452 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7453 if (crtc_state
->has_pch_encoder
) {
7454 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
7455 if (has_reduced_clock
)
7456 fp2
= i9xx_dpll_compute_fp(&reduced_clock
);
7458 dpll
= ironlake_compute_dpll(crtc
, crtc_state
,
7459 &fp
, &reduced_clock
,
7460 has_reduced_clock
? &fp2
: NULL
);
7462 crtc_state
->dpll_hw_state
.dpll
= dpll
;
7463 crtc_state
->dpll_hw_state
.fp0
= fp
;
7464 if (has_reduced_clock
)
7465 crtc_state
->dpll_hw_state
.fp1
= fp2
;
7467 crtc_state
->dpll_hw_state
.fp1
= fp
;
7469 pll
= intel_get_shared_dpll(crtc
, crtc_state
);
7471 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7472 pipe_name(crtc
->pipe
));
7477 if (is_lvds
&& has_reduced_clock
&& i915
.powersave
)
7478 crtc
->lowfreq_avail
= true;
7480 crtc
->lowfreq_avail
= false;
7485 static void intel_pch_transcoder_get_m_n(struct intel_crtc
*crtc
,
7486 struct intel_link_m_n
*m_n
)
7488 struct drm_device
*dev
= crtc
->base
.dev
;
7489 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7490 enum pipe pipe
= crtc
->pipe
;
7492 m_n
->link_m
= I915_READ(PCH_TRANS_LINK_M1(pipe
));
7493 m_n
->link_n
= I915_READ(PCH_TRANS_LINK_N1(pipe
));
7494 m_n
->gmch_m
= I915_READ(PCH_TRANS_DATA_M1(pipe
))
7496 m_n
->gmch_n
= I915_READ(PCH_TRANS_DATA_N1(pipe
));
7497 m_n
->tu
= ((I915_READ(PCH_TRANS_DATA_M1(pipe
))
7498 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7501 static void intel_cpu_transcoder_get_m_n(struct intel_crtc
*crtc
,
7502 enum transcoder transcoder
,
7503 struct intel_link_m_n
*m_n
,
7504 struct intel_link_m_n
*m2_n2
)
7506 struct drm_device
*dev
= crtc
->base
.dev
;
7507 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7508 enum pipe pipe
= crtc
->pipe
;
7510 if (INTEL_INFO(dev
)->gen
>= 5) {
7511 m_n
->link_m
= I915_READ(PIPE_LINK_M1(transcoder
));
7512 m_n
->link_n
= I915_READ(PIPE_LINK_N1(transcoder
));
7513 m_n
->gmch_m
= I915_READ(PIPE_DATA_M1(transcoder
))
7515 m_n
->gmch_n
= I915_READ(PIPE_DATA_N1(transcoder
));
7516 m_n
->tu
= ((I915_READ(PIPE_DATA_M1(transcoder
))
7517 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7518 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7519 * gen < 8) and if DRRS is supported (to make sure the
7520 * registers are not unnecessarily read).
7522 if (m2_n2
&& INTEL_INFO(dev
)->gen
< 8 &&
7523 crtc
->config
->has_drrs
) {
7524 m2_n2
->link_m
= I915_READ(PIPE_LINK_M2(transcoder
));
7525 m2_n2
->link_n
= I915_READ(PIPE_LINK_N2(transcoder
));
7526 m2_n2
->gmch_m
= I915_READ(PIPE_DATA_M2(transcoder
))
7528 m2_n2
->gmch_n
= I915_READ(PIPE_DATA_N2(transcoder
));
7529 m2_n2
->tu
= ((I915_READ(PIPE_DATA_M2(transcoder
))
7530 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7533 m_n
->link_m
= I915_READ(PIPE_LINK_M_G4X(pipe
));
7534 m_n
->link_n
= I915_READ(PIPE_LINK_N_G4X(pipe
));
7535 m_n
->gmch_m
= I915_READ(PIPE_DATA_M_G4X(pipe
))
7537 m_n
->gmch_n
= I915_READ(PIPE_DATA_N_G4X(pipe
));
7538 m_n
->tu
= ((I915_READ(PIPE_DATA_M_G4X(pipe
))
7539 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7543 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
7544 struct intel_crtc_state
*pipe_config
)
7546 if (pipe_config
->has_pch_encoder
)
7547 intel_pch_transcoder_get_m_n(crtc
, &pipe_config
->dp_m_n
);
7549 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
7550 &pipe_config
->dp_m_n
,
7551 &pipe_config
->dp_m2_n2
);
7554 static void ironlake_get_fdi_m_n_config(struct intel_crtc
*crtc
,
7555 struct intel_crtc_state
*pipe_config
)
7557 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
7558 &pipe_config
->fdi_m_n
, NULL
);
7561 static void skylake_get_pfit_config(struct intel_crtc
*crtc
,
7562 struct intel_crtc_state
*pipe_config
)
7564 struct drm_device
*dev
= crtc
->base
.dev
;
7565 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7568 tmp
= I915_READ(PS_CTL(crtc
->pipe
));
7570 if (tmp
& PS_ENABLE
) {
7571 pipe_config
->pch_pfit
.enabled
= true;
7572 pipe_config
->pch_pfit
.pos
= I915_READ(PS_WIN_POS(crtc
->pipe
));
7573 pipe_config
->pch_pfit
.size
= I915_READ(PS_WIN_SZ(crtc
->pipe
));
7577 static void ironlake_get_pfit_config(struct intel_crtc
*crtc
,
7578 struct intel_crtc_state
*pipe_config
)
7580 struct drm_device
*dev
= crtc
->base
.dev
;
7581 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7584 tmp
= I915_READ(PF_CTL(crtc
->pipe
));
7586 if (tmp
& PF_ENABLE
) {
7587 pipe_config
->pch_pfit
.enabled
= true;
7588 pipe_config
->pch_pfit
.pos
= I915_READ(PF_WIN_POS(crtc
->pipe
));
7589 pipe_config
->pch_pfit
.size
= I915_READ(PF_WIN_SZ(crtc
->pipe
));
7591 /* We currently do not free assignements of panel fitters on
7592 * ivb/hsw (since we don't use the higher upscaling modes which
7593 * differentiates them) so just WARN about this case for now. */
7595 WARN_ON((tmp
& PF_PIPE_SEL_MASK_IVB
) !=
7596 PF_PIPE_SEL_IVB(crtc
->pipe
));
7601 static void ironlake_get_plane_config(struct intel_crtc
*crtc
,
7602 struct intel_plane_config
*plane_config
)
7604 struct drm_device
*dev
= crtc
->base
.dev
;
7605 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7606 u32 val
, base
, offset
;
7607 int pipe
= crtc
->pipe
, plane
= crtc
->plane
;
7608 int fourcc
, pixel_format
;
7611 crtc
->base
.primary
->fb
= kzalloc(sizeof(struct intel_framebuffer
), GFP_KERNEL
);
7612 if (!crtc
->base
.primary
->fb
) {
7613 DRM_DEBUG_KMS("failed to alloc fb\n");
7617 val
= I915_READ(DSPCNTR(plane
));
7619 if (INTEL_INFO(dev
)->gen
>= 4)
7620 if (val
& DISPPLANE_TILED
)
7621 plane_config
->tiling
= I915_TILING_X
;
7623 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
7624 fourcc
= intel_format_to_fourcc(pixel_format
);
7625 crtc
->base
.primary
->fb
->pixel_format
= fourcc
;
7626 crtc
->base
.primary
->fb
->bits_per_pixel
=
7627 drm_format_plane_cpp(fourcc
, 0) * 8;
7629 base
= I915_READ(DSPSURF(plane
)) & 0xfffff000;
7630 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
7631 offset
= I915_READ(DSPOFFSET(plane
));
7633 if (plane_config
->tiling
)
7634 offset
= I915_READ(DSPTILEOFF(plane
));
7636 offset
= I915_READ(DSPLINOFF(plane
));
7638 plane_config
->base
= base
;
7640 val
= I915_READ(PIPESRC(pipe
));
7641 crtc
->base
.primary
->fb
->width
= ((val
>> 16) & 0xfff) + 1;
7642 crtc
->base
.primary
->fb
->height
= ((val
>> 0) & 0xfff) + 1;
7644 val
= I915_READ(DSPSTRIDE(pipe
));
7645 crtc
->base
.primary
->fb
->pitches
[0] = val
& 0xffffffc0;
7647 aligned_height
= intel_align_height(dev
, crtc
->base
.primary
->fb
->height
,
7648 plane_config
->tiling
);
7650 plane_config
->size
= PAGE_ALIGN(crtc
->base
.primary
->fb
->pitches
[0] *
7653 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7654 pipe
, plane
, crtc
->base
.primary
->fb
->width
,
7655 crtc
->base
.primary
->fb
->height
,
7656 crtc
->base
.primary
->fb
->bits_per_pixel
, base
,
7657 crtc
->base
.primary
->fb
->pitches
[0],
7658 plane_config
->size
);
7661 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
7662 struct intel_crtc_state
*pipe_config
)
7664 struct drm_device
*dev
= crtc
->base
.dev
;
7665 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7668 if (!intel_display_power_is_enabled(dev_priv
,
7669 POWER_DOMAIN_PIPE(crtc
->pipe
)))
7672 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
7673 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
7675 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
7676 if (!(tmp
& PIPECONF_ENABLE
))
7679 switch (tmp
& PIPECONF_BPC_MASK
) {
7681 pipe_config
->pipe_bpp
= 18;
7684 pipe_config
->pipe_bpp
= 24;
7686 case PIPECONF_10BPC
:
7687 pipe_config
->pipe_bpp
= 30;
7689 case PIPECONF_12BPC
:
7690 pipe_config
->pipe_bpp
= 36;
7696 if (tmp
& PIPECONF_COLOR_RANGE_SELECT
)
7697 pipe_config
->limited_color_range
= true;
7699 if (I915_READ(PCH_TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
) {
7700 struct intel_shared_dpll
*pll
;
7702 pipe_config
->has_pch_encoder
= true;
7704 tmp
= I915_READ(FDI_RX_CTL(crtc
->pipe
));
7705 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
7706 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
7708 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
7710 if (HAS_PCH_IBX(dev_priv
->dev
)) {
7711 pipe_config
->shared_dpll
=
7712 (enum intel_dpll_id
) crtc
->pipe
;
7714 tmp
= I915_READ(PCH_DPLL_SEL
);
7715 if (tmp
& TRANS_DPLLB_SEL(crtc
->pipe
))
7716 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_B
;
7718 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_A
;
7721 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
7723 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
7724 &pipe_config
->dpll_hw_state
));
7726 tmp
= pipe_config
->dpll_hw_state
.dpll
;
7727 pipe_config
->pixel_multiplier
=
7728 ((tmp
& PLL_REF_SDVO_HDMI_MULTIPLIER_MASK
)
7729 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
) + 1;
7731 ironlake_pch_clock_get(crtc
, pipe_config
);
7733 pipe_config
->pixel_multiplier
= 1;
7736 intel_get_pipe_timings(crtc
, pipe_config
);
7738 ironlake_get_pfit_config(crtc
, pipe_config
);
7743 static void assert_can_disable_lcpll(struct drm_i915_private
*dev_priv
)
7745 struct drm_device
*dev
= dev_priv
->dev
;
7746 struct intel_crtc
*crtc
;
7748 for_each_intel_crtc(dev
, crtc
)
7749 I915_STATE_WARN(crtc
->active
, "CRTC for pipe %c enabled\n",
7750 pipe_name(crtc
->pipe
));
7752 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER
), "Power well on\n");
7753 I915_STATE_WARN(I915_READ(SPLL_CTL
) & SPLL_PLL_ENABLE
, "SPLL enabled\n");
7754 I915_STATE_WARN(I915_READ(WRPLL_CTL1
) & WRPLL_PLL_ENABLE
, "WRPLL1 enabled\n");
7755 I915_STATE_WARN(I915_READ(WRPLL_CTL2
) & WRPLL_PLL_ENABLE
, "WRPLL2 enabled\n");
7756 I915_STATE_WARN(I915_READ(PCH_PP_STATUS
) & PP_ON
, "Panel power on\n");
7757 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2
) & BLM_PWM_ENABLE
,
7758 "CPU PWM1 enabled\n");
7759 if (IS_HASWELL(dev
))
7760 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL
) & BLM_PWM_ENABLE
,
7761 "CPU PWM2 enabled\n");
7762 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1
) & BLM_PCH_PWM_ENABLE
,
7763 "PCH PWM1 enabled\n");
7764 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL
) & UTIL_PIN_ENABLE
,
7765 "Utility pin enabled\n");
7766 I915_STATE_WARN(I915_READ(PCH_GTC_CTL
) & PCH_GTC_ENABLE
, "PCH GTC enabled\n");
7769 * In theory we can still leave IRQs enabled, as long as only the HPD
7770 * interrupts remain enabled. We used to check for that, but since it's
7771 * gen-specific and since we only disable LCPLL after we fully disable
7772 * the interrupts, the check below should be enough.
7774 I915_STATE_WARN(intel_irqs_enabled(dev_priv
), "IRQs enabled\n");
7777 static uint32_t hsw_read_dcomp(struct drm_i915_private
*dev_priv
)
7779 struct drm_device
*dev
= dev_priv
->dev
;
7781 if (IS_HASWELL(dev
))
7782 return I915_READ(D_COMP_HSW
);
7784 return I915_READ(D_COMP_BDW
);
7787 static void hsw_write_dcomp(struct drm_i915_private
*dev_priv
, uint32_t val
)
7789 struct drm_device
*dev
= dev_priv
->dev
;
7791 if (IS_HASWELL(dev
)) {
7792 mutex_lock(&dev_priv
->rps
.hw_lock
);
7793 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
,
7795 DRM_ERROR("Failed to write to D_COMP\n");
7796 mutex_unlock(&dev_priv
->rps
.hw_lock
);
7798 I915_WRITE(D_COMP_BDW
, val
);
7799 POSTING_READ(D_COMP_BDW
);
7804 * This function implements pieces of two sequences from BSpec:
7805 * - Sequence for display software to disable LCPLL
7806 * - Sequence for display software to allow package C8+
7807 * The steps implemented here are just the steps that actually touch the LCPLL
7808 * register. Callers should take care of disabling all the display engine
7809 * functions, doing the mode unset, fixing interrupts, etc.
7811 static void hsw_disable_lcpll(struct drm_i915_private
*dev_priv
,
7812 bool switch_to_fclk
, bool allow_power_down
)
7816 assert_can_disable_lcpll(dev_priv
);
7818 val
= I915_READ(LCPLL_CTL
);
7820 if (switch_to_fclk
) {
7821 val
|= LCPLL_CD_SOURCE_FCLK
;
7822 I915_WRITE(LCPLL_CTL
, val
);
7824 if (wait_for_atomic_us(I915_READ(LCPLL_CTL
) &
7825 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
7826 DRM_ERROR("Switching to FCLK failed\n");
7828 val
= I915_READ(LCPLL_CTL
);
7831 val
|= LCPLL_PLL_DISABLE
;
7832 I915_WRITE(LCPLL_CTL
, val
);
7833 POSTING_READ(LCPLL_CTL
);
7835 if (wait_for((I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
) == 0, 1))
7836 DRM_ERROR("LCPLL still locked\n");
7838 val
= hsw_read_dcomp(dev_priv
);
7839 val
|= D_COMP_COMP_DISABLE
;
7840 hsw_write_dcomp(dev_priv
, val
);
7843 if (wait_for((hsw_read_dcomp(dev_priv
) & D_COMP_RCOMP_IN_PROGRESS
) == 0,
7845 DRM_ERROR("D_COMP RCOMP still in progress\n");
7847 if (allow_power_down
) {
7848 val
= I915_READ(LCPLL_CTL
);
7849 val
|= LCPLL_POWER_DOWN_ALLOW
;
7850 I915_WRITE(LCPLL_CTL
, val
);
7851 POSTING_READ(LCPLL_CTL
);
7856 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7859 static void hsw_restore_lcpll(struct drm_i915_private
*dev_priv
)
7863 val
= I915_READ(LCPLL_CTL
);
7865 if ((val
& (LCPLL_PLL_LOCK
| LCPLL_PLL_DISABLE
| LCPLL_CD_SOURCE_FCLK
|
7866 LCPLL_POWER_DOWN_ALLOW
)) == LCPLL_PLL_LOCK
)
7870 * Make sure we're not on PC8 state before disabling PC8, otherwise
7871 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7873 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
7875 if (val
& LCPLL_POWER_DOWN_ALLOW
) {
7876 val
&= ~LCPLL_POWER_DOWN_ALLOW
;
7877 I915_WRITE(LCPLL_CTL
, val
);
7878 POSTING_READ(LCPLL_CTL
);
7881 val
= hsw_read_dcomp(dev_priv
);
7882 val
|= D_COMP_COMP_FORCE
;
7883 val
&= ~D_COMP_COMP_DISABLE
;
7884 hsw_write_dcomp(dev_priv
, val
);
7886 val
= I915_READ(LCPLL_CTL
);
7887 val
&= ~LCPLL_PLL_DISABLE
;
7888 I915_WRITE(LCPLL_CTL
, val
);
7890 if (wait_for(I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
, 5))
7891 DRM_ERROR("LCPLL not locked yet\n");
7893 if (val
& LCPLL_CD_SOURCE_FCLK
) {
7894 val
= I915_READ(LCPLL_CTL
);
7895 val
&= ~LCPLL_CD_SOURCE_FCLK
;
7896 I915_WRITE(LCPLL_CTL
, val
);
7898 if (wait_for_atomic_us((I915_READ(LCPLL_CTL
) &
7899 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
7900 DRM_ERROR("Switching back to LCPLL failed\n");
7903 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
7907 * Package states C8 and deeper are really deep PC states that can only be
7908 * reached when all the devices on the system allow it, so even if the graphics
7909 * device allows PC8+, it doesn't mean the system will actually get to these
7910 * states. Our driver only allows PC8+ when going into runtime PM.
7912 * The requirements for PC8+ are that all the outputs are disabled, the power
7913 * well is disabled and most interrupts are disabled, and these are also
7914 * requirements for runtime PM. When these conditions are met, we manually do
7915 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7916 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7919 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7920 * the state of some registers, so when we come back from PC8+ we need to
7921 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7922 * need to take care of the registers kept by RC6. Notice that this happens even
7923 * if we don't put the device in PCI D3 state (which is what currently happens
7924 * because of the runtime PM support).
7926 * For more, read "Display Sequences for Package C8" on the hardware
7929 void hsw_enable_pc8(struct drm_i915_private
*dev_priv
)
7931 struct drm_device
*dev
= dev_priv
->dev
;
7934 DRM_DEBUG_KMS("Enabling package C8+\n");
7936 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
7937 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
7938 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
7939 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
7942 lpt_disable_clkout_dp(dev
);
7943 hsw_disable_lcpll(dev_priv
, true, true);
7946 void hsw_disable_pc8(struct drm_i915_private
*dev_priv
)
7948 struct drm_device
*dev
= dev_priv
->dev
;
7951 DRM_DEBUG_KMS("Disabling package C8+\n");
7953 hsw_restore_lcpll(dev_priv
);
7954 lpt_init_pch_refclk(dev
);
7956 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
7957 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
7958 val
|= PCH_LP_PARTITION_LEVEL_DISABLE
;
7959 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
7962 intel_prepare_ddi(dev
);
7965 static int haswell_crtc_compute_clock(struct intel_crtc
*crtc
,
7966 struct intel_crtc_state
*crtc_state
)
7968 if (!intel_ddi_pll_select(crtc
, crtc_state
))
7971 crtc
->lowfreq_avail
= false;
7976 static void skylake_get_ddi_pll(struct drm_i915_private
*dev_priv
,
7978 struct intel_crtc_state
*pipe_config
)
7980 u32 temp
, dpll_ctl1
;
7982 temp
= I915_READ(DPLL_CTRL2
) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port
);
7983 pipe_config
->ddi_pll_sel
= temp
>> (port
* 3 + 1);
7985 switch (pipe_config
->ddi_pll_sel
) {
7988 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
7989 * of the shared DPLL framework and thus needs to be read out
7992 dpll_ctl1
= I915_READ(DPLL_CTRL1
);
7993 pipe_config
->dpll_hw_state
.ctrl1
= dpll_ctl1
& 0x3f;
7996 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL1
;
7999 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL2
;
8002 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL3
;
8007 static void haswell_get_ddi_pll(struct drm_i915_private
*dev_priv
,
8009 struct intel_crtc_state
*pipe_config
)
8011 pipe_config
->ddi_pll_sel
= I915_READ(PORT_CLK_SEL(port
));
8013 switch (pipe_config
->ddi_pll_sel
) {
8014 case PORT_CLK_SEL_WRPLL1
:
8015 pipe_config
->shared_dpll
= DPLL_ID_WRPLL1
;
8017 case PORT_CLK_SEL_WRPLL2
:
8018 pipe_config
->shared_dpll
= DPLL_ID_WRPLL2
;
8023 static void haswell_get_ddi_port_state(struct intel_crtc
*crtc
,
8024 struct intel_crtc_state
*pipe_config
)
8026 struct drm_device
*dev
= crtc
->base
.dev
;
8027 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8028 struct intel_shared_dpll
*pll
;
8032 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
8034 port
= (tmp
& TRANS_DDI_PORT_MASK
) >> TRANS_DDI_PORT_SHIFT
;
8036 if (IS_SKYLAKE(dev
))
8037 skylake_get_ddi_pll(dev_priv
, port
, pipe_config
);
8039 haswell_get_ddi_pll(dev_priv
, port
, pipe_config
);
8041 if (pipe_config
->shared_dpll
>= 0) {
8042 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
8044 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
8045 &pipe_config
->dpll_hw_state
));
8049 * Haswell has only FDI/PCH transcoder A. It is which is connected to
8050 * DDI E. So just check whether this pipe is wired to DDI E and whether
8051 * the PCH transcoder is on.
8053 if (INTEL_INFO(dev
)->gen
< 9 &&
8054 (port
== PORT_E
) && I915_READ(LPT_TRANSCONF
) & TRANS_ENABLE
) {
8055 pipe_config
->has_pch_encoder
= true;
8057 tmp
= I915_READ(FDI_RX_CTL(PIPE_A
));
8058 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
8059 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
8061 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
8065 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
8066 struct intel_crtc_state
*pipe_config
)
8068 struct drm_device
*dev
= crtc
->base
.dev
;
8069 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8070 enum intel_display_power_domain pfit_domain
;
8073 if (!intel_display_power_is_enabled(dev_priv
,
8074 POWER_DOMAIN_PIPE(crtc
->pipe
)))
8077 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
8078 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
8080 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
8081 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
8082 enum pipe trans_edp_pipe
;
8083 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
8085 WARN(1, "unknown pipe linked to edp transcoder\n");
8086 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
8087 case TRANS_DDI_EDP_INPUT_A_ON
:
8088 trans_edp_pipe
= PIPE_A
;
8090 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
8091 trans_edp_pipe
= PIPE_B
;
8093 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
8094 trans_edp_pipe
= PIPE_C
;
8098 if (trans_edp_pipe
== crtc
->pipe
)
8099 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
8102 if (!intel_display_power_is_enabled(dev_priv
,
8103 POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
)))
8106 tmp
= I915_READ(PIPECONF(pipe_config
->cpu_transcoder
));
8107 if (!(tmp
& PIPECONF_ENABLE
))
8110 haswell_get_ddi_port_state(crtc
, pipe_config
);
8112 intel_get_pipe_timings(crtc
, pipe_config
);
8114 pfit_domain
= POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
);
8115 if (intel_display_power_is_enabled(dev_priv
, pfit_domain
)) {
8116 if (IS_SKYLAKE(dev
))
8117 skylake_get_pfit_config(crtc
, pipe_config
);
8119 ironlake_get_pfit_config(crtc
, pipe_config
);
8122 if (IS_HASWELL(dev
))
8123 pipe_config
->ips_enabled
= hsw_crtc_supports_ips(crtc
) &&
8124 (I915_READ(IPS_CTL
) & IPS_ENABLE
);
8126 if (pipe_config
->cpu_transcoder
!= TRANSCODER_EDP
) {
8127 pipe_config
->pixel_multiplier
=
8128 I915_READ(PIPE_MULT(pipe_config
->cpu_transcoder
)) + 1;
8130 pipe_config
->pixel_multiplier
= 1;
8136 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
8138 struct drm_device
*dev
= crtc
->dev
;
8139 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8140 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8141 uint32_t cntl
= 0, size
= 0;
8144 unsigned int width
= intel_crtc
->cursor_width
;
8145 unsigned int height
= intel_crtc
->cursor_height
;
8146 unsigned int stride
= roundup_pow_of_two(width
) * 4;
8150 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8161 cntl
|= CURSOR_ENABLE
|
8162 CURSOR_GAMMA_ENABLE
|
8163 CURSOR_FORMAT_ARGB
|
8164 CURSOR_STRIDE(stride
);
8166 size
= (height
<< 12) | width
;
8169 if (intel_crtc
->cursor_cntl
!= 0 &&
8170 (intel_crtc
->cursor_base
!= base
||
8171 intel_crtc
->cursor_size
!= size
||
8172 intel_crtc
->cursor_cntl
!= cntl
)) {
8173 /* On these chipsets we can only modify the base/size/stride
8174 * whilst the cursor is disabled.
8176 I915_WRITE(_CURACNTR
, 0);
8177 POSTING_READ(_CURACNTR
);
8178 intel_crtc
->cursor_cntl
= 0;
8181 if (intel_crtc
->cursor_base
!= base
) {
8182 I915_WRITE(_CURABASE
, base
);
8183 intel_crtc
->cursor_base
= base
;
8186 if (intel_crtc
->cursor_size
!= size
) {
8187 I915_WRITE(CURSIZE
, size
);
8188 intel_crtc
->cursor_size
= size
;
8191 if (intel_crtc
->cursor_cntl
!= cntl
) {
8192 I915_WRITE(_CURACNTR
, cntl
);
8193 POSTING_READ(_CURACNTR
);
8194 intel_crtc
->cursor_cntl
= cntl
;
8198 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
8200 struct drm_device
*dev
= crtc
->dev
;
8201 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8202 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8203 int pipe
= intel_crtc
->pipe
;
8208 cntl
= MCURSOR_GAMMA_ENABLE
;
8209 switch (intel_crtc
->cursor_width
) {
8211 cntl
|= CURSOR_MODE_64_ARGB_AX
;
8214 cntl
|= CURSOR_MODE_128_ARGB_AX
;
8217 cntl
|= CURSOR_MODE_256_ARGB_AX
;
8220 MISSING_CASE(intel_crtc
->cursor_width
);
8223 cntl
|= pipe
<< 28; /* Connect to correct pipe */
8225 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
8226 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
8229 if (to_intel_plane(crtc
->cursor
)->rotation
== BIT(DRM_ROTATE_180
))
8230 cntl
|= CURSOR_ROTATE_180
;
8232 if (intel_crtc
->cursor_cntl
!= cntl
) {
8233 I915_WRITE(CURCNTR(pipe
), cntl
);
8234 POSTING_READ(CURCNTR(pipe
));
8235 intel_crtc
->cursor_cntl
= cntl
;
8238 /* and commit changes on next vblank */
8239 I915_WRITE(CURBASE(pipe
), base
);
8240 POSTING_READ(CURBASE(pipe
));
8242 intel_crtc
->cursor_base
= base
;
8245 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8246 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
8249 struct drm_device
*dev
= crtc
->dev
;
8250 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8251 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8252 int pipe
= intel_crtc
->pipe
;
8253 int x
= crtc
->cursor_x
;
8254 int y
= crtc
->cursor_y
;
8255 u32 base
= 0, pos
= 0;
8258 base
= intel_crtc
->cursor_addr
;
8260 if (x
>= intel_crtc
->config
->pipe_src_w
)
8263 if (y
>= intel_crtc
->config
->pipe_src_h
)
8267 if (x
+ intel_crtc
->cursor_width
<= 0)
8270 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
8273 pos
|= x
<< CURSOR_X_SHIFT
;
8276 if (y
+ intel_crtc
->cursor_height
<= 0)
8279 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
8282 pos
|= y
<< CURSOR_Y_SHIFT
;
8284 if (base
== 0 && intel_crtc
->cursor_base
== 0)
8287 I915_WRITE(CURPOS(pipe
), pos
);
8289 /* ILK+ do this automagically */
8290 if (HAS_GMCH_DISPLAY(dev
) &&
8291 to_intel_plane(crtc
->cursor
)->rotation
== BIT(DRM_ROTATE_180
)) {
8292 base
+= (intel_crtc
->cursor_height
*
8293 intel_crtc
->cursor_width
- 1) * 4;
8296 if (IS_845G(dev
) || IS_I865G(dev
))
8297 i845_update_cursor(crtc
, base
);
8299 i9xx_update_cursor(crtc
, base
);
8302 static bool cursor_size_ok(struct drm_device
*dev
,
8303 uint32_t width
, uint32_t height
)
8305 if (width
== 0 || height
== 0)
8309 * 845g/865g are special in that they are only limited by
8310 * the width of their cursors, the height is arbitrary up to
8311 * the precision of the register. Everything else requires
8312 * square cursors, limited to a few power-of-two sizes.
8314 if (IS_845G(dev
) || IS_I865G(dev
)) {
8315 if ((width
& 63) != 0)
8318 if (width
> (IS_845G(dev
) ? 64 : 512))
8324 switch (width
| height
) {
8339 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
8340 u16
*blue
, uint32_t start
, uint32_t size
)
8342 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
8343 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8345 for (i
= start
; i
< end
; i
++) {
8346 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
8347 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
8348 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
8351 intel_crtc_load_lut(crtc
);
8354 /* VESA 640x480x72Hz mode to set on the pipe */
8355 static struct drm_display_mode load_detect_mode
= {
8356 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
8357 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
8360 struct drm_framebuffer
*
8361 __intel_framebuffer_create(struct drm_device
*dev
,
8362 struct drm_mode_fb_cmd2
*mode_cmd
,
8363 struct drm_i915_gem_object
*obj
)
8365 struct intel_framebuffer
*intel_fb
;
8368 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
8370 drm_gem_object_unreference(&obj
->base
);
8371 return ERR_PTR(-ENOMEM
);
8374 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
8378 return &intel_fb
->base
;
8380 drm_gem_object_unreference(&obj
->base
);
8383 return ERR_PTR(ret
);
8386 static struct drm_framebuffer
*
8387 intel_framebuffer_create(struct drm_device
*dev
,
8388 struct drm_mode_fb_cmd2
*mode_cmd
,
8389 struct drm_i915_gem_object
*obj
)
8391 struct drm_framebuffer
*fb
;
8394 ret
= i915_mutex_lock_interruptible(dev
);
8396 return ERR_PTR(ret
);
8397 fb
= __intel_framebuffer_create(dev
, mode_cmd
, obj
);
8398 mutex_unlock(&dev
->struct_mutex
);
8404 intel_framebuffer_pitch_for_width(int width
, int bpp
)
8406 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
8407 return ALIGN(pitch
, 64);
8411 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
8413 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
8414 return PAGE_ALIGN(pitch
* mode
->vdisplay
);
8417 static struct drm_framebuffer
*
8418 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
8419 struct drm_display_mode
*mode
,
8422 struct drm_i915_gem_object
*obj
;
8423 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
8425 obj
= i915_gem_alloc_object(dev
,
8426 intel_framebuffer_size_for_mode(mode
, bpp
));
8428 return ERR_PTR(-ENOMEM
);
8430 mode_cmd
.width
= mode
->hdisplay
;
8431 mode_cmd
.height
= mode
->vdisplay
;
8432 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
8434 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
8436 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
8439 static struct drm_framebuffer
*
8440 mode_fits_in_fbdev(struct drm_device
*dev
,
8441 struct drm_display_mode
*mode
)
8443 #ifdef CONFIG_DRM_I915_FBDEV
8444 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8445 struct drm_i915_gem_object
*obj
;
8446 struct drm_framebuffer
*fb
;
8448 if (!dev_priv
->fbdev
)
8451 if (!dev_priv
->fbdev
->fb
)
8454 obj
= dev_priv
->fbdev
->fb
->obj
;
8457 fb
= &dev_priv
->fbdev
->fb
->base
;
8458 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
8459 fb
->bits_per_pixel
))
8462 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
8471 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
8472 struct drm_display_mode
*mode
,
8473 struct intel_load_detect_pipe
*old
,
8474 struct drm_modeset_acquire_ctx
*ctx
)
8476 struct intel_crtc
*intel_crtc
;
8477 struct intel_encoder
*intel_encoder
=
8478 intel_attached_encoder(connector
);
8479 struct drm_crtc
*possible_crtc
;
8480 struct drm_encoder
*encoder
= &intel_encoder
->base
;
8481 struct drm_crtc
*crtc
= NULL
;
8482 struct drm_device
*dev
= encoder
->dev
;
8483 struct drm_framebuffer
*fb
;
8484 struct drm_mode_config
*config
= &dev
->mode_config
;
8487 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8488 connector
->base
.id
, connector
->name
,
8489 encoder
->base
.id
, encoder
->name
);
8492 ret
= drm_modeset_lock(&config
->connection_mutex
, ctx
);
8497 * Algorithm gets a little messy:
8499 * - if the connector already has an assigned crtc, use it (but make
8500 * sure it's on first)
8502 * - try to find the first unused crtc that can drive this connector,
8503 * and use that if we find one
8506 /* See if we already have a CRTC for this connector */
8507 if (encoder
->crtc
) {
8508 crtc
= encoder
->crtc
;
8510 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
8513 ret
= drm_modeset_lock(&crtc
->primary
->mutex
, ctx
);
8517 old
->dpms_mode
= connector
->dpms
;
8518 old
->load_detect_temp
= false;
8520 /* Make sure the crtc and connector are running */
8521 if (connector
->dpms
!= DRM_MODE_DPMS_ON
)
8522 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
8527 /* Find an unused one (if possible) */
8528 for_each_crtc(dev
, possible_crtc
) {
8530 if (!(encoder
->possible_crtcs
& (1 << i
)))
8532 if (possible_crtc
->enabled
)
8534 /* This can occur when applying the pipe A quirk on resume. */
8535 if (to_intel_crtc(possible_crtc
)->new_enabled
)
8538 crtc
= possible_crtc
;
8543 * If we didn't find an unused CRTC, don't use any.
8546 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8550 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
8553 ret
= drm_modeset_lock(&crtc
->primary
->mutex
, ctx
);
8556 intel_encoder
->new_crtc
= to_intel_crtc(crtc
);
8557 to_intel_connector(connector
)->new_encoder
= intel_encoder
;
8559 intel_crtc
= to_intel_crtc(crtc
);
8560 intel_crtc
->new_enabled
= true;
8561 intel_crtc
->new_config
= intel_crtc
->config
;
8562 old
->dpms_mode
= connector
->dpms
;
8563 old
->load_detect_temp
= true;
8564 old
->release_fb
= NULL
;
8567 mode
= &load_detect_mode
;
8569 /* We need a framebuffer large enough to accommodate all accesses
8570 * that the plane may generate whilst we perform load detection.
8571 * We can not rely on the fbcon either being present (we get called
8572 * during its initialisation to detect all boot displays, or it may
8573 * not even exist) or that it is large enough to satisfy the
8576 fb
= mode_fits_in_fbdev(dev
, mode
);
8578 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8579 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
8580 old
->release_fb
= fb
;
8582 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8584 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8588 if (intel_set_mode(crtc
, mode
, 0, 0, fb
)) {
8589 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8590 if (old
->release_fb
)
8591 old
->release_fb
->funcs
->destroy(old
->release_fb
);
8595 /* let the connector get through one full cycle before testing */
8596 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
8600 intel_crtc
->new_enabled
= crtc
->enabled
;
8601 if (intel_crtc
->new_enabled
)
8602 intel_crtc
->new_config
= intel_crtc
->config
;
8604 intel_crtc
->new_config
= NULL
;
8606 if (ret
== -EDEADLK
) {
8607 drm_modeset_backoff(ctx
);
8614 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
8615 struct intel_load_detect_pipe
*old
)
8617 struct intel_encoder
*intel_encoder
=
8618 intel_attached_encoder(connector
);
8619 struct drm_encoder
*encoder
= &intel_encoder
->base
;
8620 struct drm_crtc
*crtc
= encoder
->crtc
;
8621 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8623 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8624 connector
->base
.id
, connector
->name
,
8625 encoder
->base
.id
, encoder
->name
);
8627 if (old
->load_detect_temp
) {
8628 to_intel_connector(connector
)->new_encoder
= NULL
;
8629 intel_encoder
->new_crtc
= NULL
;
8630 intel_crtc
->new_enabled
= false;
8631 intel_crtc
->new_config
= NULL
;
8632 intel_set_mode(crtc
, NULL
, 0, 0, NULL
);
8634 if (old
->release_fb
) {
8635 drm_framebuffer_unregister_private(old
->release_fb
);
8636 drm_framebuffer_unreference(old
->release_fb
);
8642 /* Switch crtc and encoder back off if necessary */
8643 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
)
8644 connector
->funcs
->dpms(connector
, old
->dpms_mode
);
8647 static int i9xx_pll_refclk(struct drm_device
*dev
,
8648 const struct intel_crtc_state
*pipe_config
)
8650 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8651 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
8653 if ((dpll
& PLL_REF_INPUT_MASK
) == PLLB_REF_INPUT_SPREADSPECTRUMIN
)
8654 return dev_priv
->vbt
.lvds_ssc_freq
;
8655 else if (HAS_PCH_SPLIT(dev
))
8657 else if (!IS_GEN2(dev
))
8663 /* Returns the clock of the currently programmed mode of the given pipe. */
8664 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
8665 struct intel_crtc_state
*pipe_config
)
8667 struct drm_device
*dev
= crtc
->base
.dev
;
8668 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8669 int pipe
= pipe_config
->cpu_transcoder
;
8670 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
8672 intel_clock_t clock
;
8673 int refclk
= i9xx_pll_refclk(dev
, pipe_config
);
8675 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
8676 fp
= pipe_config
->dpll_hw_state
.fp0
;
8678 fp
= pipe_config
->dpll_hw_state
.fp1
;
8680 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
8681 if (IS_PINEVIEW(dev
)) {
8682 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
8683 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
8685 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
8686 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
8689 if (!IS_GEN2(dev
)) {
8690 if (IS_PINEVIEW(dev
))
8691 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
8692 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
8694 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
8695 DPLL_FPA01_P1_POST_DIV_SHIFT
);
8697 switch (dpll
& DPLL_MODE_MASK
) {
8698 case DPLLB_MODE_DAC_SERIAL
:
8699 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
8702 case DPLLB_MODE_LVDS
:
8703 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
8707 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8708 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
8712 if (IS_PINEVIEW(dev
))
8713 pineview_clock(refclk
, &clock
);
8715 i9xx_clock(refclk
, &clock
);
8717 u32 lvds
= IS_I830(dev
) ? 0 : I915_READ(LVDS
);
8718 bool is_lvds
= (pipe
== 1) && (lvds
& LVDS_PORT_EN
);
8721 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
8722 DPLL_FPA01_P1_POST_DIV_SHIFT
);
8724 if (lvds
& LVDS_CLKB_POWER_UP
)
8729 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
8732 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
8733 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
8735 if (dpll
& PLL_P2_DIVIDE_BY_4
)
8741 i9xx_clock(refclk
, &clock
);
8745 * This value includes pixel_multiplier. We will use
8746 * port_clock to compute adjusted_mode.crtc_clock in the
8747 * encoder's get_config() function.
8749 pipe_config
->port_clock
= clock
.dot
;
8752 int intel_dotclock_calculate(int link_freq
,
8753 const struct intel_link_m_n
*m_n
)
8756 * The calculation for the data clock is:
8757 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8758 * But we want to avoid losing precison if possible, so:
8759 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8761 * and the link clock is simpler:
8762 * link_clock = (m * link_clock) / n
8768 return div_u64((u64
)m_n
->link_m
* link_freq
, m_n
->link_n
);
8771 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
8772 struct intel_crtc_state
*pipe_config
)
8774 struct drm_device
*dev
= crtc
->base
.dev
;
8776 /* read out port_clock from the DPLL */
8777 i9xx_crtc_clock_get(crtc
, pipe_config
);
8780 * This value does not include pixel_multiplier.
8781 * We will check that port_clock and adjusted_mode.crtc_clock
8782 * agree once we know their relationship in the encoder's
8783 * get_config() function.
8785 pipe_config
->base
.adjusted_mode
.crtc_clock
=
8786 intel_dotclock_calculate(intel_fdi_link_freq(dev
) * 10000,
8787 &pipe_config
->fdi_m_n
);
8790 /** Returns the currently programmed mode of the given pipe. */
8791 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
8792 struct drm_crtc
*crtc
)
8794 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8795 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8796 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
8797 struct drm_display_mode
*mode
;
8798 struct intel_crtc_state pipe_config
;
8799 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
8800 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
8801 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
8802 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
8803 enum pipe pipe
= intel_crtc
->pipe
;
8805 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
8810 * Construct a pipe_config sufficient for getting the clock info
8811 * back out of crtc_clock_get.
8813 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8814 * to use a real value here instead.
8816 pipe_config
.cpu_transcoder
= (enum transcoder
) pipe
;
8817 pipe_config
.pixel_multiplier
= 1;
8818 pipe_config
.dpll_hw_state
.dpll
= I915_READ(DPLL(pipe
));
8819 pipe_config
.dpll_hw_state
.fp0
= I915_READ(FP0(pipe
));
8820 pipe_config
.dpll_hw_state
.fp1
= I915_READ(FP1(pipe
));
8821 i9xx_crtc_clock_get(intel_crtc
, &pipe_config
);
8823 mode
->clock
= pipe_config
.port_clock
/ pipe_config
.pixel_multiplier
;
8824 mode
->hdisplay
= (htot
& 0xffff) + 1;
8825 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
8826 mode
->hsync_start
= (hsync
& 0xffff) + 1;
8827 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
8828 mode
->vdisplay
= (vtot
& 0xffff) + 1;
8829 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
8830 mode
->vsync_start
= (vsync
& 0xffff) + 1;
8831 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
8833 drm_mode_set_name(mode
);
8838 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
8840 struct drm_device
*dev
= crtc
->dev
;
8841 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8842 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8844 if (!HAS_GMCH_DISPLAY(dev
))
8847 if (!dev_priv
->lvds_downclock_avail
)
8851 * Since this is called by a timer, we should never get here in
8854 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
8855 int pipe
= intel_crtc
->pipe
;
8856 int dpll_reg
= DPLL(pipe
);
8859 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8861 assert_panel_unlocked(dev_priv
, pipe
);
8863 dpll
= I915_READ(dpll_reg
);
8864 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
8865 I915_WRITE(dpll_reg
, dpll
);
8866 intel_wait_for_vblank(dev
, pipe
);
8867 dpll
= I915_READ(dpll_reg
);
8868 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
8869 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8874 void intel_mark_busy(struct drm_device
*dev
)
8876 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8878 if (dev_priv
->mm
.busy
)
8881 intel_runtime_pm_get(dev_priv
);
8882 i915_update_gfx_val(dev_priv
);
8883 dev_priv
->mm
.busy
= true;
8886 void intel_mark_idle(struct drm_device
*dev
)
8888 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8889 struct drm_crtc
*crtc
;
8891 if (!dev_priv
->mm
.busy
)
8894 dev_priv
->mm
.busy
= false;
8896 if (!i915
.powersave
)
8899 for_each_crtc(dev
, crtc
) {
8900 if (!crtc
->primary
->fb
)
8903 intel_decrease_pllclock(crtc
);
8906 if (INTEL_INFO(dev
)->gen
>= 6)
8907 gen6_rps_idle(dev
->dev_private
);
8910 intel_runtime_pm_put(dev_priv
);
8913 static void intel_crtc_set_state(struct intel_crtc
*crtc
,
8914 struct intel_crtc_state
*crtc_state
)
8916 kfree(crtc
->config
);
8917 crtc
->config
= crtc_state
;
8918 crtc
->base
.state
= &crtc_state
->base
;
8921 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
8923 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8924 struct drm_device
*dev
= crtc
->dev
;
8925 struct intel_unpin_work
*work
;
8927 spin_lock_irq(&dev
->event_lock
);
8928 work
= intel_crtc
->unpin_work
;
8929 intel_crtc
->unpin_work
= NULL
;
8930 spin_unlock_irq(&dev
->event_lock
);
8933 cancel_work_sync(&work
->work
);
8937 intel_crtc_set_state(intel_crtc
, NULL
);
8938 drm_crtc_cleanup(crtc
);
8943 static void intel_unpin_work_fn(struct work_struct
*__work
)
8945 struct intel_unpin_work
*work
=
8946 container_of(__work
, struct intel_unpin_work
, work
);
8947 struct drm_device
*dev
= work
->crtc
->dev
;
8948 enum pipe pipe
= to_intel_crtc(work
->crtc
)->pipe
;
8950 mutex_lock(&dev
->struct_mutex
);
8951 intel_unpin_fb_obj(work
->old_fb_obj
);
8952 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
8953 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
8955 intel_fbc_update(dev
);
8957 if (work
->flip_queued_req
)
8958 i915_gem_request_assign(&work
->flip_queued_req
, NULL
);
8959 mutex_unlock(&dev
->struct_mutex
);
8961 intel_frontbuffer_flip_complete(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
8963 BUG_ON(atomic_read(&to_intel_crtc(work
->crtc
)->unpin_work_count
) == 0);
8964 atomic_dec(&to_intel_crtc(work
->crtc
)->unpin_work_count
);
8969 static void do_intel_finish_page_flip(struct drm_device
*dev
,
8970 struct drm_crtc
*crtc
)
8972 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8973 struct intel_unpin_work
*work
;
8974 unsigned long flags
;
8976 /* Ignore early vblank irqs */
8977 if (intel_crtc
== NULL
)
8981 * This is called both by irq handlers and the reset code (to complete
8982 * lost pageflips) so needs the full irqsave spinlocks.
8984 spin_lock_irqsave(&dev
->event_lock
, flags
);
8985 work
= intel_crtc
->unpin_work
;
8987 /* Ensure we don't miss a work->pending update ... */
8990 if (work
== NULL
|| atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
8991 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
8995 page_flip_completed(intel_crtc
);
8997 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9000 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
9002 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9003 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
9005 do_intel_finish_page_flip(dev
, crtc
);
9008 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
9010 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9011 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
9013 do_intel_finish_page_flip(dev
, crtc
);
9016 /* Is 'a' after or equal to 'b'? */
9017 static bool g4x_flip_count_after_eq(u32 a
, u32 b
)
9019 return !((a
- b
) & 0x80000000);
9022 static bool page_flip_finished(struct intel_crtc
*crtc
)
9024 struct drm_device
*dev
= crtc
->base
.dev
;
9025 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9027 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
9028 crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
9032 * The relevant registers doen't exist on pre-ctg.
9033 * As the flip done interrupt doesn't trigger for mmio
9034 * flips on gmch platforms, a flip count check isn't
9035 * really needed there. But since ctg has the registers,
9036 * include it in the check anyway.
9038 if (INTEL_INFO(dev
)->gen
< 5 && !IS_G4X(dev
))
9042 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9043 * used the same base address. In that case the mmio flip might
9044 * have completed, but the CS hasn't even executed the flip yet.
9046 * A flip count check isn't enough as the CS might have updated
9047 * the base address just after start of vblank, but before we
9048 * managed to process the interrupt. This means we'd complete the
9051 * Combining both checks should get us a good enough result. It may
9052 * still happen that the CS flip has been executed, but has not
9053 * yet actually completed. But in case the base address is the same
9054 * anyway, we don't really care.
9056 return (I915_READ(DSPSURFLIVE(crtc
->plane
)) & ~0xfff) ==
9057 crtc
->unpin_work
->gtt_offset
&&
9058 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc
->pipe
)),
9059 crtc
->unpin_work
->flip_count
);
9062 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
9064 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9065 struct intel_crtc
*intel_crtc
=
9066 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
9067 unsigned long flags
;
9071 * This is called both by irq handlers and the reset code (to complete
9072 * lost pageflips) so needs the full irqsave spinlocks.
9074 * NB: An MMIO update of the plane base pointer will also
9075 * generate a page-flip completion irq, i.e. every modeset
9076 * is also accompanied by a spurious intel_prepare_page_flip().
9078 spin_lock_irqsave(&dev
->event_lock
, flags
);
9079 if (intel_crtc
->unpin_work
&& page_flip_finished(intel_crtc
))
9080 atomic_inc_not_zero(&intel_crtc
->unpin_work
->pending
);
9081 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9084 static inline void intel_mark_page_flip_active(struct intel_crtc
*intel_crtc
)
9086 /* Ensure that the work item is consistent when activating it ... */
9088 atomic_set(&intel_crtc
->unpin_work
->pending
, INTEL_FLIP_PENDING
);
9089 /* and that it is marked active as soon as the irq could fire. */
9093 static int intel_gen2_queue_flip(struct drm_device
*dev
,
9094 struct drm_crtc
*crtc
,
9095 struct drm_framebuffer
*fb
,
9096 struct drm_i915_gem_object
*obj
,
9097 struct intel_engine_cs
*ring
,
9100 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9104 ret
= intel_ring_begin(ring
, 6);
9108 /* Can't queue multiple flips, so wait for the previous
9109 * one to finish before executing the next.
9111 if (intel_crtc
->plane
)
9112 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
9114 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
9115 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
9116 intel_ring_emit(ring
, MI_NOOP
);
9117 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
9118 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9119 intel_ring_emit(ring
, fb
->pitches
[0]);
9120 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9121 intel_ring_emit(ring
, 0); /* aux display base address, unused */
9123 intel_mark_page_flip_active(intel_crtc
);
9124 __intel_ring_advance(ring
);
9128 static int intel_gen3_queue_flip(struct drm_device
*dev
,
9129 struct drm_crtc
*crtc
,
9130 struct drm_framebuffer
*fb
,
9131 struct drm_i915_gem_object
*obj
,
9132 struct intel_engine_cs
*ring
,
9135 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9139 ret
= intel_ring_begin(ring
, 6);
9143 if (intel_crtc
->plane
)
9144 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
9146 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
9147 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
9148 intel_ring_emit(ring
, MI_NOOP
);
9149 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
9150 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9151 intel_ring_emit(ring
, fb
->pitches
[0]);
9152 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9153 intel_ring_emit(ring
, MI_NOOP
);
9155 intel_mark_page_flip_active(intel_crtc
);
9156 __intel_ring_advance(ring
);
9160 static int intel_gen4_queue_flip(struct drm_device
*dev
,
9161 struct drm_crtc
*crtc
,
9162 struct drm_framebuffer
*fb
,
9163 struct drm_i915_gem_object
*obj
,
9164 struct intel_engine_cs
*ring
,
9167 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9168 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9169 uint32_t pf
, pipesrc
;
9172 ret
= intel_ring_begin(ring
, 4);
9176 /* i965+ uses the linear or tiled offsets from the
9177 * Display Registers (which do not change across a page-flip)
9178 * so we need only reprogram the base address.
9180 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
9181 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9182 intel_ring_emit(ring
, fb
->pitches
[0]);
9183 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
|
9186 /* XXX Enabling the panel-fitter across page-flip is so far
9187 * untested on non-native modes, so ignore it for now.
9188 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9191 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
9192 intel_ring_emit(ring
, pf
| pipesrc
);
9194 intel_mark_page_flip_active(intel_crtc
);
9195 __intel_ring_advance(ring
);
9199 static int intel_gen6_queue_flip(struct drm_device
*dev
,
9200 struct drm_crtc
*crtc
,
9201 struct drm_framebuffer
*fb
,
9202 struct drm_i915_gem_object
*obj
,
9203 struct intel_engine_cs
*ring
,
9206 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9207 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9208 uint32_t pf
, pipesrc
;
9211 ret
= intel_ring_begin(ring
, 4);
9215 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
9216 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9217 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
9218 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9220 /* Contrary to the suggestions in the documentation,
9221 * "Enable Panel Fitter" does not seem to be required when page
9222 * flipping with a non-native mode, and worse causes a normal
9224 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9227 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
9228 intel_ring_emit(ring
, pf
| pipesrc
);
9230 intel_mark_page_flip_active(intel_crtc
);
9231 __intel_ring_advance(ring
);
9235 static int intel_gen7_queue_flip(struct drm_device
*dev
,
9236 struct drm_crtc
*crtc
,
9237 struct drm_framebuffer
*fb
,
9238 struct drm_i915_gem_object
*obj
,
9239 struct intel_engine_cs
*ring
,
9242 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9243 uint32_t plane_bit
= 0;
9246 switch (intel_crtc
->plane
) {
9248 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
9251 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
9254 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
9257 WARN_ONCE(1, "unknown plane in flip command\n");
9262 if (ring
->id
== RCS
) {
9265 * On Gen 8, SRM is now taking an extra dword to accommodate
9266 * 48bits addresses, and we need a NOOP for the batch size to
9274 * BSpec MI_DISPLAY_FLIP for IVB:
9275 * "The full packet must be contained within the same cache line."
9277 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9278 * cacheline, if we ever start emitting more commands before
9279 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9280 * then do the cacheline alignment, and finally emit the
9283 ret
= intel_ring_cacheline_align(ring
);
9287 ret
= intel_ring_begin(ring
, len
);
9291 /* Unmask the flip-done completion message. Note that the bspec says that
9292 * we should do this for both the BCS and RCS, and that we must not unmask
9293 * more than one flip event at any time (or ensure that one flip message
9294 * can be sent by waiting for flip-done prior to queueing new flips).
9295 * Experimentation says that BCS works despite DERRMR masking all
9296 * flip-done completion events and that unmasking all planes at once
9297 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9298 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9300 if (ring
->id
== RCS
) {
9301 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
9302 intel_ring_emit(ring
, DERRMR
);
9303 intel_ring_emit(ring
, ~(DERRMR_PIPEA_PRI_FLIP_DONE
|
9304 DERRMR_PIPEB_PRI_FLIP_DONE
|
9305 DERRMR_PIPEC_PRI_FLIP_DONE
));
9307 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM_GEN8(1) |
9308 MI_SRM_LRM_GLOBAL_GTT
);
9310 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM(1) |
9311 MI_SRM_LRM_GLOBAL_GTT
);
9312 intel_ring_emit(ring
, DERRMR
);
9313 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
+ 256);
9315 intel_ring_emit(ring
, 0);
9316 intel_ring_emit(ring
, MI_NOOP
);
9320 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
9321 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
9322 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9323 intel_ring_emit(ring
, (MI_NOOP
));
9325 intel_mark_page_flip_active(intel_crtc
);
9326 __intel_ring_advance(ring
);
9330 static bool use_mmio_flip(struct intel_engine_cs
*ring
,
9331 struct drm_i915_gem_object
*obj
)
9334 * This is not being used for older platforms, because
9335 * non-availability of flip done interrupt forces us to use
9336 * CS flips. Older platforms derive flip done using some clever
9337 * tricks involving the flip_pending status bits and vblank irqs.
9338 * So using MMIO flips there would disrupt this mechanism.
9344 if (INTEL_INFO(ring
->dev
)->gen
< 5)
9347 if (i915
.use_mmio_flip
< 0)
9349 else if (i915
.use_mmio_flip
> 0)
9351 else if (i915
.enable_execlists
)
9354 return ring
!= i915_gem_request_get_ring(obj
->last_read_req
);
9357 static void skl_do_mmio_flip(struct intel_crtc
*intel_crtc
)
9359 struct drm_device
*dev
= intel_crtc
->base
.dev
;
9360 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9361 struct drm_framebuffer
*fb
= intel_crtc
->base
.primary
->fb
;
9362 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
9363 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
9364 const enum pipe pipe
= intel_crtc
->pipe
;
9367 ctl
= I915_READ(PLANE_CTL(pipe
, 0));
9368 ctl
&= ~PLANE_CTL_TILED_MASK
;
9369 if (obj
->tiling_mode
== I915_TILING_X
)
9370 ctl
|= PLANE_CTL_TILED_X
;
9373 * The stride is either expressed as a multiple of 64 bytes chunks for
9374 * linear buffers or in number of tiles for tiled buffers.
9376 stride
= fb
->pitches
[0] >> 6;
9377 if (obj
->tiling_mode
== I915_TILING_X
)
9378 stride
= fb
->pitches
[0] >> 9; /* X tiles are 512 bytes wide */
9381 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
9382 * PLANE_SURF updates, the update is then guaranteed to be atomic.
9384 I915_WRITE(PLANE_CTL(pipe
, 0), ctl
);
9385 I915_WRITE(PLANE_STRIDE(pipe
, 0), stride
);
9387 I915_WRITE(PLANE_SURF(pipe
, 0), intel_crtc
->unpin_work
->gtt_offset
);
9388 POSTING_READ(PLANE_SURF(pipe
, 0));
9391 static void ilk_do_mmio_flip(struct intel_crtc
*intel_crtc
)
9393 struct drm_device
*dev
= intel_crtc
->base
.dev
;
9394 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9395 struct intel_framebuffer
*intel_fb
=
9396 to_intel_framebuffer(intel_crtc
->base
.primary
->fb
);
9397 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
9401 reg
= DSPCNTR(intel_crtc
->plane
);
9402 dspcntr
= I915_READ(reg
);
9404 if (obj
->tiling_mode
!= I915_TILING_NONE
)
9405 dspcntr
|= DISPPLANE_TILED
;
9407 dspcntr
&= ~DISPPLANE_TILED
;
9409 I915_WRITE(reg
, dspcntr
);
9411 I915_WRITE(DSPSURF(intel_crtc
->plane
),
9412 intel_crtc
->unpin_work
->gtt_offset
);
9413 POSTING_READ(DSPSURF(intel_crtc
->plane
));
9418 * XXX: This is the temporary way to update the plane registers until we get
9419 * around to using the usual plane update functions for MMIO flips
9421 static void intel_do_mmio_flip(struct intel_crtc
*intel_crtc
)
9423 struct drm_device
*dev
= intel_crtc
->base
.dev
;
9425 u32 start_vbl_count
;
9427 intel_mark_page_flip_active(intel_crtc
);
9429 atomic_update
= intel_pipe_update_start(intel_crtc
, &start_vbl_count
);
9431 if (INTEL_INFO(dev
)->gen
>= 9)
9432 skl_do_mmio_flip(intel_crtc
);
9434 /* use_mmio_flip() retricts MMIO flips to ilk+ */
9435 ilk_do_mmio_flip(intel_crtc
);
9438 intel_pipe_update_end(intel_crtc
, start_vbl_count
);
9441 static void intel_mmio_flip_work_func(struct work_struct
*work
)
9443 struct intel_crtc
*crtc
=
9444 container_of(work
, struct intel_crtc
, mmio_flip
.work
);
9445 struct intel_mmio_flip
*mmio_flip
;
9447 mmio_flip
= &crtc
->mmio_flip
;
9449 WARN_ON(__i915_wait_request(mmio_flip
->req
,
9450 crtc
->reset_counter
,
9451 false, NULL
, NULL
) != 0);
9453 intel_do_mmio_flip(crtc
);
9454 if (mmio_flip
->req
) {
9455 mutex_lock(&crtc
->base
.dev
->struct_mutex
);
9456 i915_gem_request_assign(&mmio_flip
->req
, NULL
);
9457 mutex_unlock(&crtc
->base
.dev
->struct_mutex
);
9461 static int intel_queue_mmio_flip(struct drm_device
*dev
,
9462 struct drm_crtc
*crtc
,
9463 struct drm_framebuffer
*fb
,
9464 struct drm_i915_gem_object
*obj
,
9465 struct intel_engine_cs
*ring
,
9468 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9470 i915_gem_request_assign(&intel_crtc
->mmio_flip
.req
,
9471 obj
->last_write_req
);
9473 schedule_work(&intel_crtc
->mmio_flip
.work
);
9478 static int intel_gen9_queue_flip(struct drm_device
*dev
,
9479 struct drm_crtc
*crtc
,
9480 struct drm_framebuffer
*fb
,
9481 struct drm_i915_gem_object
*obj
,
9482 struct intel_engine_cs
*ring
,
9485 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9486 uint32_t plane
= 0, stride
;
9489 switch(intel_crtc
->pipe
) {
9491 plane
= MI_DISPLAY_FLIP_SKL_PLANE_1_A
;
9494 plane
= MI_DISPLAY_FLIP_SKL_PLANE_1_B
;
9497 plane
= MI_DISPLAY_FLIP_SKL_PLANE_1_C
;
9500 WARN_ONCE(1, "unknown plane in flip command\n");
9504 switch (obj
->tiling_mode
) {
9505 case I915_TILING_NONE
:
9506 stride
= fb
->pitches
[0] >> 6;
9509 stride
= fb
->pitches
[0] >> 9;
9512 WARN_ONCE(1, "unknown tiling in flip command\n");
9516 ret
= intel_ring_begin(ring
, 10);
9520 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
9521 intel_ring_emit(ring
, DERRMR
);
9522 intel_ring_emit(ring
, ~(DERRMR_PIPEA_PRI_FLIP_DONE
|
9523 DERRMR_PIPEB_PRI_FLIP_DONE
|
9524 DERRMR_PIPEC_PRI_FLIP_DONE
));
9525 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM_GEN8(1) |
9526 MI_SRM_LRM_GLOBAL_GTT
);
9527 intel_ring_emit(ring
, DERRMR
);
9528 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
+ 256);
9529 intel_ring_emit(ring
, 0);
9531 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane
);
9532 intel_ring_emit(ring
, stride
<< 6 | obj
->tiling_mode
);
9533 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9535 intel_mark_page_flip_active(intel_crtc
);
9536 __intel_ring_advance(ring
);
9541 static int intel_default_queue_flip(struct drm_device
*dev
,
9542 struct drm_crtc
*crtc
,
9543 struct drm_framebuffer
*fb
,
9544 struct drm_i915_gem_object
*obj
,
9545 struct intel_engine_cs
*ring
,
9551 static bool __intel_pageflip_stall_check(struct drm_device
*dev
,
9552 struct drm_crtc
*crtc
)
9554 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9555 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9556 struct intel_unpin_work
*work
= intel_crtc
->unpin_work
;
9559 if (atomic_read(&work
->pending
) >= INTEL_FLIP_COMPLETE
)
9562 if (!work
->enable_stall_check
)
9565 if (work
->flip_ready_vblank
== 0) {
9566 if (work
->flip_queued_req
&&
9567 !i915_gem_request_completed(work
->flip_queued_req
, true))
9570 work
->flip_ready_vblank
= drm_vblank_count(dev
, intel_crtc
->pipe
);
9573 if (drm_vblank_count(dev
, intel_crtc
->pipe
) - work
->flip_ready_vblank
< 3)
9576 /* Potential stall - if we see that the flip has happened,
9577 * assume a missed interrupt. */
9578 if (INTEL_INFO(dev
)->gen
>= 4)
9579 addr
= I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc
->plane
)));
9581 addr
= I915_READ(DSPADDR(intel_crtc
->plane
));
9583 /* There is a potential issue here with a false positive after a flip
9584 * to the same address. We could address this by checking for a
9585 * non-incrementing frame counter.
9587 return addr
== work
->gtt_offset
;
9590 void intel_check_page_flip(struct drm_device
*dev
, int pipe
)
9592 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9593 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
9594 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9601 spin_lock(&dev
->event_lock
);
9602 if (intel_crtc
->unpin_work
&& __intel_pageflip_stall_check(dev
, crtc
)) {
9603 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9604 intel_crtc
->unpin_work
->flip_queued_vblank
, drm_vblank_count(dev
, pipe
));
9605 page_flip_completed(intel_crtc
);
9607 spin_unlock(&dev
->event_lock
);
9610 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
9611 struct drm_framebuffer
*fb
,
9612 struct drm_pending_vblank_event
*event
,
9613 uint32_t page_flip_flags
)
9615 struct drm_device
*dev
= crtc
->dev
;
9616 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9617 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
9618 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
9619 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9620 struct drm_plane
*primary
= crtc
->primary
;
9621 enum pipe pipe
= intel_crtc
->pipe
;
9622 struct intel_unpin_work
*work
;
9623 struct intel_engine_cs
*ring
;
9627 * drm_mode_page_flip_ioctl() should already catch this, but double
9628 * check to be safe. In the future we may enable pageflipping from
9629 * a disabled primary plane.
9631 if (WARN_ON(intel_fb_obj(old_fb
) == NULL
))
9634 /* Can't change pixel format via MI display flips. */
9635 if (fb
->pixel_format
!= crtc
->primary
->fb
->pixel_format
)
9639 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9640 * Note that pitch changes could also affect these register.
9642 if (INTEL_INFO(dev
)->gen
> 3 &&
9643 (fb
->offsets
[0] != crtc
->primary
->fb
->offsets
[0] ||
9644 fb
->pitches
[0] != crtc
->primary
->fb
->pitches
[0]))
9647 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
9650 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
9654 work
->event
= event
;
9656 work
->old_fb_obj
= intel_fb_obj(old_fb
);
9657 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
9659 ret
= drm_crtc_vblank_get(crtc
);
9663 /* We borrow the event spin lock for protecting unpin_work */
9664 spin_lock_irq(&dev
->event_lock
);
9665 if (intel_crtc
->unpin_work
) {
9666 /* Before declaring the flip queue wedged, check if
9667 * the hardware completed the operation behind our backs.
9669 if (__intel_pageflip_stall_check(dev
, crtc
)) {
9670 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9671 page_flip_completed(intel_crtc
);
9673 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9674 spin_unlock_irq(&dev
->event_lock
);
9676 drm_crtc_vblank_put(crtc
);
9681 intel_crtc
->unpin_work
= work
;
9682 spin_unlock_irq(&dev
->event_lock
);
9684 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
9685 flush_workqueue(dev_priv
->wq
);
9687 ret
= i915_mutex_lock_interruptible(dev
);
9691 /* Reference the objects for the scheduled work. */
9692 drm_gem_object_reference(&work
->old_fb_obj
->base
);
9693 drm_gem_object_reference(&obj
->base
);
9695 crtc
->primary
->fb
= fb
;
9697 work
->pending_flip_obj
= obj
;
9699 atomic_inc(&intel_crtc
->unpin_work_count
);
9700 intel_crtc
->reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
9702 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
9703 work
->flip_count
= I915_READ(PIPE_FLIPCOUNT_GM45(pipe
)) + 1;
9705 if (IS_VALLEYVIEW(dev
)) {
9706 ring
= &dev_priv
->ring
[BCS
];
9707 if (obj
->tiling_mode
!= work
->old_fb_obj
->tiling_mode
)
9708 /* vlv: DISPLAY_FLIP fails to change tiling */
9710 } else if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
9711 ring
= &dev_priv
->ring
[BCS
];
9712 } else if (INTEL_INFO(dev
)->gen
>= 7) {
9713 ring
= i915_gem_request_get_ring(obj
->last_read_req
);
9714 if (ring
== NULL
|| ring
->id
!= RCS
)
9715 ring
= &dev_priv
->ring
[BCS
];
9717 ring
= &dev_priv
->ring
[RCS
];
9720 ret
= intel_pin_and_fence_fb_obj(crtc
->primary
, fb
, ring
);
9722 goto cleanup_pending
;
9725 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
;
9727 if (use_mmio_flip(ring
, obj
)) {
9728 ret
= intel_queue_mmio_flip(dev
, crtc
, fb
, obj
, ring
,
9733 i915_gem_request_assign(&work
->flip_queued_req
,
9734 obj
->last_write_req
);
9736 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
, ring
,
9741 i915_gem_request_assign(&work
->flip_queued_req
,
9742 intel_ring_get_request(ring
));
9745 work
->flip_queued_vblank
= drm_vblank_count(dev
, intel_crtc
->pipe
);
9746 work
->enable_stall_check
= true;
9748 i915_gem_track_fb(work
->old_fb_obj
, obj
,
9749 INTEL_FRONTBUFFER_PRIMARY(pipe
));
9751 intel_fbc_disable(dev
);
9752 intel_frontbuffer_flip_prepare(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
9753 mutex_unlock(&dev
->struct_mutex
);
9755 trace_i915_flip_request(intel_crtc
->plane
, obj
);
9760 intel_unpin_fb_obj(obj
);
9762 atomic_dec(&intel_crtc
->unpin_work_count
);
9763 crtc
->primary
->fb
= old_fb
;
9764 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
9765 drm_gem_object_unreference(&obj
->base
);
9766 mutex_unlock(&dev
->struct_mutex
);
9769 spin_lock_irq(&dev
->event_lock
);
9770 intel_crtc
->unpin_work
= NULL
;
9771 spin_unlock_irq(&dev
->event_lock
);
9773 drm_crtc_vblank_put(crtc
);
9779 ret
= intel_plane_restore(primary
);
9780 if (ret
== 0 && event
) {
9781 spin_lock_irq(&dev
->event_lock
);
9782 drm_send_vblank_event(dev
, pipe
, event
);
9783 spin_unlock_irq(&dev
->event_lock
);
9789 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
9790 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
9791 .load_lut
= intel_crtc_load_lut
,
9792 .atomic_begin
= intel_begin_crtc_commit
,
9793 .atomic_flush
= intel_finish_crtc_commit
,
9797 * intel_modeset_update_staged_output_state
9799 * Updates the staged output configuration state, e.g. after we've read out the
9802 static void intel_modeset_update_staged_output_state(struct drm_device
*dev
)
9804 struct intel_crtc
*crtc
;
9805 struct intel_encoder
*encoder
;
9806 struct intel_connector
*connector
;
9808 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9810 connector
->new_encoder
=
9811 to_intel_encoder(connector
->base
.encoder
);
9814 for_each_intel_encoder(dev
, encoder
) {
9816 to_intel_crtc(encoder
->base
.crtc
);
9819 for_each_intel_crtc(dev
, crtc
) {
9820 crtc
->new_enabled
= crtc
->base
.enabled
;
9822 if (crtc
->new_enabled
)
9823 crtc
->new_config
= crtc
->config
;
9825 crtc
->new_config
= NULL
;
9830 * intel_modeset_commit_output_state
9832 * This function copies the stage display pipe configuration to the real one.
9834 static void intel_modeset_commit_output_state(struct drm_device
*dev
)
9836 struct intel_crtc
*crtc
;
9837 struct intel_encoder
*encoder
;
9838 struct intel_connector
*connector
;
9840 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9842 connector
->base
.encoder
= &connector
->new_encoder
->base
;
9845 for_each_intel_encoder(dev
, encoder
) {
9846 encoder
->base
.crtc
= &encoder
->new_crtc
->base
;
9849 for_each_intel_crtc(dev
, crtc
) {
9850 crtc
->base
.enabled
= crtc
->new_enabled
;
9855 connected_sink_compute_bpp(struct intel_connector
*connector
,
9856 struct intel_crtc_state
*pipe_config
)
9858 int bpp
= pipe_config
->pipe_bpp
;
9860 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9861 connector
->base
.base
.id
,
9862 connector
->base
.name
);
9864 /* Don't use an invalid EDID bpc value */
9865 if (connector
->base
.display_info
.bpc
&&
9866 connector
->base
.display_info
.bpc
* 3 < bpp
) {
9867 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9868 bpp
, connector
->base
.display_info
.bpc
*3);
9869 pipe_config
->pipe_bpp
= connector
->base
.display_info
.bpc
*3;
9872 /* Clamp bpp to 8 on screens without EDID 1.4 */
9873 if (connector
->base
.display_info
.bpc
== 0 && bpp
> 24) {
9874 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9876 pipe_config
->pipe_bpp
= 24;
9881 compute_baseline_pipe_bpp(struct intel_crtc
*crtc
,
9882 struct drm_framebuffer
*fb
,
9883 struct intel_crtc_state
*pipe_config
)
9885 struct drm_device
*dev
= crtc
->base
.dev
;
9886 struct intel_connector
*connector
;
9889 switch (fb
->pixel_format
) {
9891 bpp
= 8*3; /* since we go through a colormap */
9893 case DRM_FORMAT_XRGB1555
:
9894 case DRM_FORMAT_ARGB1555
:
9895 /* checked in intel_framebuffer_init already */
9896 if (WARN_ON(INTEL_INFO(dev
)->gen
> 3))
9898 case DRM_FORMAT_RGB565
:
9899 bpp
= 6*3; /* min is 18bpp */
9901 case DRM_FORMAT_XBGR8888
:
9902 case DRM_FORMAT_ABGR8888
:
9903 /* checked in intel_framebuffer_init already */
9904 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
9906 case DRM_FORMAT_XRGB8888
:
9907 case DRM_FORMAT_ARGB8888
:
9910 case DRM_FORMAT_XRGB2101010
:
9911 case DRM_FORMAT_ARGB2101010
:
9912 case DRM_FORMAT_XBGR2101010
:
9913 case DRM_FORMAT_ABGR2101010
:
9914 /* checked in intel_framebuffer_init already */
9915 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
9919 /* TODO: gen4+ supports 16 bpc floating point, too. */
9921 DRM_DEBUG_KMS("unsupported depth\n");
9925 pipe_config
->pipe_bpp
= bpp
;
9927 /* Clamp display bpp to EDID value */
9928 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9930 if (!connector
->new_encoder
||
9931 connector
->new_encoder
->new_crtc
!= crtc
)
9934 connected_sink_compute_bpp(connector
, pipe_config
);
9940 static void intel_dump_crtc_timings(const struct drm_display_mode
*mode
)
9942 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9943 "type: 0x%x flags: 0x%x\n",
9945 mode
->crtc_hdisplay
, mode
->crtc_hsync_start
,
9946 mode
->crtc_hsync_end
, mode
->crtc_htotal
,
9947 mode
->crtc_vdisplay
, mode
->crtc_vsync_start
,
9948 mode
->crtc_vsync_end
, mode
->crtc_vtotal
, mode
->type
, mode
->flags
);
9951 static void intel_dump_pipe_config(struct intel_crtc
*crtc
,
9952 struct intel_crtc_state
*pipe_config
,
9953 const char *context
)
9955 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc
->base
.base
.id
,
9956 context
, pipe_name(crtc
->pipe
));
9958 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config
->cpu_transcoder
));
9959 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9960 pipe_config
->pipe_bpp
, pipe_config
->dither
);
9961 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9962 pipe_config
->has_pch_encoder
,
9963 pipe_config
->fdi_lanes
,
9964 pipe_config
->fdi_m_n
.gmch_m
, pipe_config
->fdi_m_n
.gmch_n
,
9965 pipe_config
->fdi_m_n
.link_m
, pipe_config
->fdi_m_n
.link_n
,
9966 pipe_config
->fdi_m_n
.tu
);
9967 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9968 pipe_config
->has_dp_encoder
,
9969 pipe_config
->dp_m_n
.gmch_m
, pipe_config
->dp_m_n
.gmch_n
,
9970 pipe_config
->dp_m_n
.link_m
, pipe_config
->dp_m_n
.link_n
,
9971 pipe_config
->dp_m_n
.tu
);
9973 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
9974 pipe_config
->has_dp_encoder
,
9975 pipe_config
->dp_m2_n2
.gmch_m
,
9976 pipe_config
->dp_m2_n2
.gmch_n
,
9977 pipe_config
->dp_m2_n2
.link_m
,
9978 pipe_config
->dp_m2_n2
.link_n
,
9979 pipe_config
->dp_m2_n2
.tu
);
9981 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
9982 pipe_config
->has_audio
,
9983 pipe_config
->has_infoframe
);
9985 DRM_DEBUG_KMS("requested mode:\n");
9986 drm_mode_debug_printmodeline(&pipe_config
->base
.mode
);
9987 DRM_DEBUG_KMS("adjusted mode:\n");
9988 drm_mode_debug_printmodeline(&pipe_config
->base
.adjusted_mode
);
9989 intel_dump_crtc_timings(&pipe_config
->base
.adjusted_mode
);
9990 DRM_DEBUG_KMS("port clock: %d\n", pipe_config
->port_clock
);
9991 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9992 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
);
9993 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9994 pipe_config
->gmch_pfit
.control
,
9995 pipe_config
->gmch_pfit
.pgm_ratios
,
9996 pipe_config
->gmch_pfit
.lvds_border_bits
);
9997 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9998 pipe_config
->pch_pfit
.pos
,
9999 pipe_config
->pch_pfit
.size
,
10000 pipe_config
->pch_pfit
.enabled
? "enabled" : "disabled");
10001 DRM_DEBUG_KMS("ips: %i\n", pipe_config
->ips_enabled
);
10002 DRM_DEBUG_KMS("double wide: %i\n", pipe_config
->double_wide
);
10005 static bool encoders_cloneable(const struct intel_encoder
*a
,
10006 const struct intel_encoder
*b
)
10008 /* masks could be asymmetric, so check both ways */
10009 return a
== b
|| (a
->cloneable
& (1 << b
->type
) &&
10010 b
->cloneable
& (1 << a
->type
));
10013 static bool check_single_encoder_cloning(struct intel_crtc
*crtc
,
10014 struct intel_encoder
*encoder
)
10016 struct drm_device
*dev
= crtc
->base
.dev
;
10017 struct intel_encoder
*source_encoder
;
10019 for_each_intel_encoder(dev
, source_encoder
) {
10020 if (source_encoder
->new_crtc
!= crtc
)
10023 if (!encoders_cloneable(encoder
, source_encoder
))
10030 static bool check_encoder_cloning(struct intel_crtc
*crtc
)
10032 struct drm_device
*dev
= crtc
->base
.dev
;
10033 struct intel_encoder
*encoder
;
10035 for_each_intel_encoder(dev
, encoder
) {
10036 if (encoder
->new_crtc
!= crtc
)
10039 if (!check_single_encoder_cloning(crtc
, encoder
))
10046 static bool check_digital_port_conflicts(struct drm_device
*dev
)
10048 struct intel_connector
*connector
;
10049 unsigned int used_ports
= 0;
10052 * Walk the connector list instead of the encoder
10053 * list to detect the problem on ddi platforms
10054 * where there's just one encoder per digital port.
10056 list_for_each_entry(connector
,
10057 &dev
->mode_config
.connector_list
, base
.head
) {
10058 struct intel_encoder
*encoder
= connector
->new_encoder
;
10063 WARN_ON(!encoder
->new_crtc
);
10065 switch (encoder
->type
) {
10066 unsigned int port_mask
;
10067 case INTEL_OUTPUT_UNKNOWN
:
10068 if (WARN_ON(!HAS_DDI(dev
)))
10070 case INTEL_OUTPUT_DISPLAYPORT
:
10071 case INTEL_OUTPUT_HDMI
:
10072 case INTEL_OUTPUT_EDP
:
10073 port_mask
= 1 << enc_to_dig_port(&encoder
->base
)->port
;
10075 /* the same port mustn't appear more than once */
10076 if (used_ports
& port_mask
)
10079 used_ports
|= port_mask
;
10088 static struct intel_crtc_state
*
10089 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
10090 struct drm_framebuffer
*fb
,
10091 struct drm_display_mode
*mode
)
10093 struct drm_device
*dev
= crtc
->dev
;
10094 struct intel_encoder
*encoder
;
10095 struct intel_crtc_state
*pipe_config
;
10096 int plane_bpp
, ret
= -EINVAL
;
10099 if (!check_encoder_cloning(to_intel_crtc(crtc
))) {
10100 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10101 return ERR_PTR(-EINVAL
);
10104 if (!check_digital_port_conflicts(dev
)) {
10105 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
10106 return ERR_PTR(-EINVAL
);
10109 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
10111 return ERR_PTR(-ENOMEM
);
10113 drm_mode_copy(&pipe_config
->base
.adjusted_mode
, mode
);
10114 drm_mode_copy(&pipe_config
->base
.mode
, mode
);
10116 pipe_config
->cpu_transcoder
=
10117 (enum transcoder
) to_intel_crtc(crtc
)->pipe
;
10118 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
10121 * Sanitize sync polarity flags based on requested ones. If neither
10122 * positive or negative polarity is requested, treat this as meaning
10123 * negative polarity.
10125 if (!(pipe_config
->base
.adjusted_mode
.flags
&
10126 (DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NHSYNC
)))
10127 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
10129 if (!(pipe_config
->base
.adjusted_mode
.flags
&
10130 (DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_NVSYNC
)))
10131 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
10133 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10134 * plane pixel format and any sink constraints into account. Returns the
10135 * source plane bpp so that dithering can be selected on mismatches
10136 * after encoders and crtc also have had their say. */
10137 plane_bpp
= compute_baseline_pipe_bpp(to_intel_crtc(crtc
),
10143 * Determine the real pipe dimensions. Note that stereo modes can
10144 * increase the actual pipe size due to the frame doubling and
10145 * insertion of additional space for blanks between the frame. This
10146 * is stored in the crtc timings. We use the requested mode to do this
10147 * computation to clearly distinguish it from the adjusted mode, which
10148 * can be changed by the connectors in the below retry loop.
10150 drm_crtc_get_hv_timing(&pipe_config
->base
.mode
,
10151 &pipe_config
->pipe_src_w
,
10152 &pipe_config
->pipe_src_h
);
10155 /* Ensure the port clock defaults are reset when retrying. */
10156 pipe_config
->port_clock
= 0;
10157 pipe_config
->pixel_multiplier
= 1;
10159 /* Fill in default crtc timings, allow encoders to overwrite them. */
10160 drm_mode_set_crtcinfo(&pipe_config
->base
.adjusted_mode
,
10161 CRTC_STEREO_DOUBLE
);
10163 /* Pass our mode to the connectors and the CRTC to give them a chance to
10164 * adjust it according to limitations or connector properties, and also
10165 * a chance to reject the mode entirely.
10167 for_each_intel_encoder(dev
, encoder
) {
10169 if (&encoder
->new_crtc
->base
!= crtc
)
10172 if (!(encoder
->compute_config(encoder
, pipe_config
))) {
10173 DRM_DEBUG_KMS("Encoder config failure\n");
10178 /* Set default port clock if not overwritten by the encoder. Needs to be
10179 * done afterwards in case the encoder adjusts the mode. */
10180 if (!pipe_config
->port_clock
)
10181 pipe_config
->port_clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
10182 * pipe_config
->pixel_multiplier
;
10184 ret
= intel_crtc_compute_config(to_intel_crtc(crtc
), pipe_config
);
10186 DRM_DEBUG_KMS("CRTC fixup failed\n");
10190 if (ret
== RETRY
) {
10191 if (WARN(!retry
, "loop in pipe configuration computation\n")) {
10196 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10198 goto encoder_retry
;
10201 pipe_config
->dither
= pipe_config
->pipe_bpp
!= plane_bpp
;
10202 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10203 plane_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
10205 return pipe_config
;
10207 kfree(pipe_config
);
10208 return ERR_PTR(ret
);
10211 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10212 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10214 intel_modeset_affected_pipes(struct drm_crtc
*crtc
, unsigned *modeset_pipes
,
10215 unsigned *prepare_pipes
, unsigned *disable_pipes
)
10217 struct intel_crtc
*intel_crtc
;
10218 struct drm_device
*dev
= crtc
->dev
;
10219 struct intel_encoder
*encoder
;
10220 struct intel_connector
*connector
;
10221 struct drm_crtc
*tmp_crtc
;
10223 *disable_pipes
= *modeset_pipes
= *prepare_pipes
= 0;
10225 /* Check which crtcs have changed outputs connected to them, these need
10226 * to be part of the prepare_pipes mask. We don't (yet) support global
10227 * modeset across multiple crtcs, so modeset_pipes will only have one
10228 * bit set at most. */
10229 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10231 if (connector
->base
.encoder
== &connector
->new_encoder
->base
)
10234 if (connector
->base
.encoder
) {
10235 tmp_crtc
= connector
->base
.encoder
->crtc
;
10237 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
10240 if (connector
->new_encoder
)
10242 1 << connector
->new_encoder
->new_crtc
->pipe
;
10245 for_each_intel_encoder(dev
, encoder
) {
10246 if (encoder
->base
.crtc
== &encoder
->new_crtc
->base
)
10249 if (encoder
->base
.crtc
) {
10250 tmp_crtc
= encoder
->base
.crtc
;
10252 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
10255 if (encoder
->new_crtc
)
10256 *prepare_pipes
|= 1 << encoder
->new_crtc
->pipe
;
10259 /* Check for pipes that will be enabled/disabled ... */
10260 for_each_intel_crtc(dev
, intel_crtc
) {
10261 if (intel_crtc
->base
.enabled
== intel_crtc
->new_enabled
)
10264 if (!intel_crtc
->new_enabled
)
10265 *disable_pipes
|= 1 << intel_crtc
->pipe
;
10267 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
10271 /* set_mode is also used to update properties on life display pipes. */
10272 intel_crtc
= to_intel_crtc(crtc
);
10273 if (intel_crtc
->new_enabled
)
10274 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
10277 * For simplicity do a full modeset on any pipe where the output routing
10278 * changed. We could be more clever, but that would require us to be
10279 * more careful with calling the relevant encoder->mode_set functions.
10281 if (*prepare_pipes
)
10282 *modeset_pipes
= *prepare_pipes
;
10284 /* ... and mask these out. */
10285 *modeset_pipes
&= ~(*disable_pipes
);
10286 *prepare_pipes
&= ~(*disable_pipes
);
10289 * HACK: We don't (yet) fully support global modesets. intel_set_config
10290 * obies this rule, but the modeset restore mode of
10291 * intel_modeset_setup_hw_state does not.
10293 *modeset_pipes
&= 1 << intel_crtc
->pipe
;
10294 *prepare_pipes
&= 1 << intel_crtc
->pipe
;
10296 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10297 *modeset_pipes
, *prepare_pipes
, *disable_pipes
);
10300 static bool intel_crtc_in_use(struct drm_crtc
*crtc
)
10302 struct drm_encoder
*encoder
;
10303 struct drm_device
*dev
= crtc
->dev
;
10305 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
)
10306 if (encoder
->crtc
== crtc
)
10313 intel_modeset_update_state(struct drm_device
*dev
, unsigned prepare_pipes
)
10315 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10316 struct intel_encoder
*intel_encoder
;
10317 struct intel_crtc
*intel_crtc
;
10318 struct drm_connector
*connector
;
10320 intel_shared_dpll_commit(dev_priv
);
10322 for_each_intel_encoder(dev
, intel_encoder
) {
10323 if (!intel_encoder
->base
.crtc
)
10326 intel_crtc
= to_intel_crtc(intel_encoder
->base
.crtc
);
10328 if (prepare_pipes
& (1 << intel_crtc
->pipe
))
10329 intel_encoder
->connectors_active
= false;
10332 intel_modeset_commit_output_state(dev
);
10334 /* Double check state. */
10335 for_each_intel_crtc(dev
, intel_crtc
) {
10336 WARN_ON(intel_crtc
->base
.enabled
!= intel_crtc_in_use(&intel_crtc
->base
));
10337 WARN_ON(intel_crtc
->new_config
&&
10338 intel_crtc
->new_config
!= intel_crtc
->config
);
10339 WARN_ON(intel_crtc
->base
.enabled
!= !!intel_crtc
->new_config
);
10342 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
10343 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
10346 intel_crtc
= to_intel_crtc(connector
->encoder
->crtc
);
10348 if (prepare_pipes
& (1 << intel_crtc
->pipe
)) {
10349 struct drm_property
*dpms_property
=
10350 dev
->mode_config
.dpms_property
;
10352 connector
->dpms
= DRM_MODE_DPMS_ON
;
10353 drm_object_property_set_value(&connector
->base
,
10357 intel_encoder
= to_intel_encoder(connector
->encoder
);
10358 intel_encoder
->connectors_active
= true;
10364 static bool intel_fuzzy_clock_check(int clock1
, int clock2
)
10368 if (clock1
== clock2
)
10371 if (!clock1
|| !clock2
)
10374 diff
= abs(clock1
- clock2
);
10376 if (((((diff
+ clock1
+ clock2
) * 100)) / (clock1
+ clock2
)) < 105)
10382 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10383 list_for_each_entry((intel_crtc), \
10384 &(dev)->mode_config.crtc_list, \
10386 if (mask & (1 <<(intel_crtc)->pipe))
10389 intel_pipe_config_compare(struct drm_device
*dev
,
10390 struct intel_crtc_state
*current_config
,
10391 struct intel_crtc_state
*pipe_config
)
10393 #define PIPE_CONF_CHECK_X(name) \
10394 if (current_config->name != pipe_config->name) { \
10395 DRM_ERROR("mismatch in " #name " " \
10396 "(expected 0x%08x, found 0x%08x)\n", \
10397 current_config->name, \
10398 pipe_config->name); \
10402 #define PIPE_CONF_CHECK_I(name) \
10403 if (current_config->name != pipe_config->name) { \
10404 DRM_ERROR("mismatch in " #name " " \
10405 "(expected %i, found %i)\n", \
10406 current_config->name, \
10407 pipe_config->name); \
10411 /* This is required for BDW+ where there is only one set of registers for
10412 * switching between high and low RR.
10413 * This macro can be used whenever a comparison has to be made between one
10414 * hw state and multiple sw state variables.
10416 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10417 if ((current_config->name != pipe_config->name) && \
10418 (current_config->alt_name != pipe_config->name)) { \
10419 DRM_ERROR("mismatch in " #name " " \
10420 "(expected %i or %i, found %i)\n", \
10421 current_config->name, \
10422 current_config->alt_name, \
10423 pipe_config->name); \
10427 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10428 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10429 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10430 "(expected %i, found %i)\n", \
10431 current_config->name & (mask), \
10432 pipe_config->name & (mask)); \
10436 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10437 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10438 DRM_ERROR("mismatch in " #name " " \
10439 "(expected %i, found %i)\n", \
10440 current_config->name, \
10441 pipe_config->name); \
10445 #define PIPE_CONF_QUIRK(quirk) \
10446 ((current_config->quirks | pipe_config->quirks) & (quirk))
10448 PIPE_CONF_CHECK_I(cpu_transcoder
);
10450 PIPE_CONF_CHECK_I(has_pch_encoder
);
10451 PIPE_CONF_CHECK_I(fdi_lanes
);
10452 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_m
);
10453 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_n
);
10454 PIPE_CONF_CHECK_I(fdi_m_n
.link_m
);
10455 PIPE_CONF_CHECK_I(fdi_m_n
.link_n
);
10456 PIPE_CONF_CHECK_I(fdi_m_n
.tu
);
10458 PIPE_CONF_CHECK_I(has_dp_encoder
);
10460 if (INTEL_INFO(dev
)->gen
< 8) {
10461 PIPE_CONF_CHECK_I(dp_m_n
.gmch_m
);
10462 PIPE_CONF_CHECK_I(dp_m_n
.gmch_n
);
10463 PIPE_CONF_CHECK_I(dp_m_n
.link_m
);
10464 PIPE_CONF_CHECK_I(dp_m_n
.link_n
);
10465 PIPE_CONF_CHECK_I(dp_m_n
.tu
);
10467 if (current_config
->has_drrs
) {
10468 PIPE_CONF_CHECK_I(dp_m2_n2
.gmch_m
);
10469 PIPE_CONF_CHECK_I(dp_m2_n2
.gmch_n
);
10470 PIPE_CONF_CHECK_I(dp_m2_n2
.link_m
);
10471 PIPE_CONF_CHECK_I(dp_m2_n2
.link_n
);
10472 PIPE_CONF_CHECK_I(dp_m2_n2
.tu
);
10475 PIPE_CONF_CHECK_I_ALT(dp_m_n
.gmch_m
, dp_m2_n2
.gmch_m
);
10476 PIPE_CONF_CHECK_I_ALT(dp_m_n
.gmch_n
, dp_m2_n2
.gmch_n
);
10477 PIPE_CONF_CHECK_I_ALT(dp_m_n
.link_m
, dp_m2_n2
.link_m
);
10478 PIPE_CONF_CHECK_I_ALT(dp_m_n
.link_n
, dp_m2_n2
.link_n
);
10479 PIPE_CONF_CHECK_I_ALT(dp_m_n
.tu
, dp_m2_n2
.tu
);
10482 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hdisplay
);
10483 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_htotal
);
10484 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_start
);
10485 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_end
);
10486 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_start
);
10487 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_end
);
10489 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vdisplay
);
10490 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vtotal
);
10491 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_start
);
10492 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_end
);
10493 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_start
);
10494 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_end
);
10496 PIPE_CONF_CHECK_I(pixel_multiplier
);
10497 PIPE_CONF_CHECK_I(has_hdmi_sink
);
10498 if ((INTEL_INFO(dev
)->gen
< 8 && !IS_HASWELL(dev
)) ||
10499 IS_VALLEYVIEW(dev
))
10500 PIPE_CONF_CHECK_I(limited_color_range
);
10501 PIPE_CONF_CHECK_I(has_infoframe
);
10503 PIPE_CONF_CHECK_I(has_audio
);
10505 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
10506 DRM_MODE_FLAG_INTERLACE
);
10508 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
10509 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
10510 DRM_MODE_FLAG_PHSYNC
);
10511 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
10512 DRM_MODE_FLAG_NHSYNC
);
10513 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
10514 DRM_MODE_FLAG_PVSYNC
);
10515 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
10516 DRM_MODE_FLAG_NVSYNC
);
10519 PIPE_CONF_CHECK_I(pipe_src_w
);
10520 PIPE_CONF_CHECK_I(pipe_src_h
);
10523 * FIXME: BIOS likes to set up a cloned config with lvds+external
10524 * screen. Since we don't yet re-compute the pipe config when moving
10525 * just the lvds port away to another pipe the sw tracking won't match.
10527 * Proper atomic modesets with recomputed global state will fix this.
10528 * Until then just don't check gmch state for inherited modes.
10530 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE
)) {
10531 PIPE_CONF_CHECK_I(gmch_pfit
.control
);
10532 /* pfit ratios are autocomputed by the hw on gen4+ */
10533 if (INTEL_INFO(dev
)->gen
< 4)
10534 PIPE_CONF_CHECK_I(gmch_pfit
.pgm_ratios
);
10535 PIPE_CONF_CHECK_I(gmch_pfit
.lvds_border_bits
);
10538 PIPE_CONF_CHECK_I(pch_pfit
.enabled
);
10539 if (current_config
->pch_pfit
.enabled
) {
10540 PIPE_CONF_CHECK_I(pch_pfit
.pos
);
10541 PIPE_CONF_CHECK_I(pch_pfit
.size
);
10544 /* BDW+ don't expose a synchronous way to read the state */
10545 if (IS_HASWELL(dev
))
10546 PIPE_CONF_CHECK_I(ips_enabled
);
10548 PIPE_CONF_CHECK_I(double_wide
);
10550 PIPE_CONF_CHECK_X(ddi_pll_sel
);
10552 PIPE_CONF_CHECK_I(shared_dpll
);
10553 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll
);
10554 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll_md
);
10555 PIPE_CONF_CHECK_X(dpll_hw_state
.fp0
);
10556 PIPE_CONF_CHECK_X(dpll_hw_state
.fp1
);
10557 PIPE_CONF_CHECK_X(dpll_hw_state
.wrpll
);
10558 PIPE_CONF_CHECK_X(dpll_hw_state
.ctrl1
);
10559 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr1
);
10560 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr2
);
10562 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5)
10563 PIPE_CONF_CHECK_I(pipe_bpp
);
10565 PIPE_CONF_CHECK_CLOCK_FUZZY(base
.adjusted_mode
.crtc_clock
);
10566 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock
);
10568 #undef PIPE_CONF_CHECK_X
10569 #undef PIPE_CONF_CHECK_I
10570 #undef PIPE_CONF_CHECK_I_ALT
10571 #undef PIPE_CONF_CHECK_FLAGS
10572 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10573 #undef PIPE_CONF_QUIRK
10578 static void check_wm_state(struct drm_device
*dev
)
10580 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10581 struct skl_ddb_allocation hw_ddb
, *sw_ddb
;
10582 struct intel_crtc
*intel_crtc
;
10585 if (INTEL_INFO(dev
)->gen
< 9)
10588 skl_ddb_get_hw_state(dev_priv
, &hw_ddb
);
10589 sw_ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
10591 for_each_intel_crtc(dev
, intel_crtc
) {
10592 struct skl_ddb_entry
*hw_entry
, *sw_entry
;
10593 const enum pipe pipe
= intel_crtc
->pipe
;
10595 if (!intel_crtc
->active
)
10599 for_each_plane(pipe
, plane
) {
10600 hw_entry
= &hw_ddb
.plane
[pipe
][plane
];
10601 sw_entry
= &sw_ddb
->plane
[pipe
][plane
];
10603 if (skl_ddb_entry_equal(hw_entry
, sw_entry
))
10606 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
10607 "(expected (%u,%u), found (%u,%u))\n",
10608 pipe_name(pipe
), plane
+ 1,
10609 sw_entry
->start
, sw_entry
->end
,
10610 hw_entry
->start
, hw_entry
->end
);
10614 hw_entry
= &hw_ddb
.cursor
[pipe
];
10615 sw_entry
= &sw_ddb
->cursor
[pipe
];
10617 if (skl_ddb_entry_equal(hw_entry
, sw_entry
))
10620 DRM_ERROR("mismatch in DDB state pipe %c cursor "
10621 "(expected (%u,%u), found (%u,%u))\n",
10623 sw_entry
->start
, sw_entry
->end
,
10624 hw_entry
->start
, hw_entry
->end
);
10629 check_connector_state(struct drm_device
*dev
)
10631 struct intel_connector
*connector
;
10633 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10635 /* This also checks the encoder/connector hw state with the
10636 * ->get_hw_state callbacks. */
10637 intel_connector_check_state(connector
);
10639 I915_STATE_WARN(&connector
->new_encoder
->base
!= connector
->base
.encoder
,
10640 "connector's staged encoder doesn't match current encoder\n");
10645 check_encoder_state(struct drm_device
*dev
)
10647 struct intel_encoder
*encoder
;
10648 struct intel_connector
*connector
;
10650 for_each_intel_encoder(dev
, encoder
) {
10651 bool enabled
= false;
10652 bool active
= false;
10653 enum pipe pipe
, tracked_pipe
;
10655 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10656 encoder
->base
.base
.id
,
10657 encoder
->base
.name
);
10659 I915_STATE_WARN(&encoder
->new_crtc
->base
!= encoder
->base
.crtc
,
10660 "encoder's stage crtc doesn't match current crtc\n");
10661 I915_STATE_WARN(encoder
->connectors_active
&& !encoder
->base
.crtc
,
10662 "encoder's active_connectors set, but no crtc\n");
10664 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10666 if (connector
->base
.encoder
!= &encoder
->base
)
10669 if (connector
->base
.dpms
!= DRM_MODE_DPMS_OFF
)
10673 * for MST connectors if we unplug the connector is gone
10674 * away but the encoder is still connected to a crtc
10675 * until a modeset happens in response to the hotplug.
10677 if (!enabled
&& encoder
->base
.encoder_type
== DRM_MODE_ENCODER_DPMST
)
10680 I915_STATE_WARN(!!encoder
->base
.crtc
!= enabled
,
10681 "encoder's enabled state mismatch "
10682 "(expected %i, found %i)\n",
10683 !!encoder
->base
.crtc
, enabled
);
10684 I915_STATE_WARN(active
&& !encoder
->base
.crtc
,
10685 "active encoder with no crtc\n");
10687 I915_STATE_WARN(encoder
->connectors_active
!= active
,
10688 "encoder's computed active state doesn't match tracked active state "
10689 "(expected %i, found %i)\n", active
, encoder
->connectors_active
);
10691 active
= encoder
->get_hw_state(encoder
, &pipe
);
10692 I915_STATE_WARN(active
!= encoder
->connectors_active
,
10693 "encoder's hw state doesn't match sw tracking "
10694 "(expected %i, found %i)\n",
10695 encoder
->connectors_active
, active
);
10697 if (!encoder
->base
.crtc
)
10700 tracked_pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
10701 I915_STATE_WARN(active
&& pipe
!= tracked_pipe
,
10702 "active encoder's pipe doesn't match"
10703 "(expected %i, found %i)\n",
10704 tracked_pipe
, pipe
);
10710 check_crtc_state(struct drm_device
*dev
)
10712 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10713 struct intel_crtc
*crtc
;
10714 struct intel_encoder
*encoder
;
10715 struct intel_crtc_state pipe_config
;
10717 for_each_intel_crtc(dev
, crtc
) {
10718 bool enabled
= false;
10719 bool active
= false;
10721 memset(&pipe_config
, 0, sizeof(pipe_config
));
10723 DRM_DEBUG_KMS("[CRTC:%d]\n",
10724 crtc
->base
.base
.id
);
10726 I915_STATE_WARN(crtc
->active
&& !crtc
->base
.enabled
,
10727 "active crtc, but not enabled in sw tracking\n");
10729 for_each_intel_encoder(dev
, encoder
) {
10730 if (encoder
->base
.crtc
!= &crtc
->base
)
10733 if (encoder
->connectors_active
)
10737 I915_STATE_WARN(active
!= crtc
->active
,
10738 "crtc's computed active state doesn't match tracked active state "
10739 "(expected %i, found %i)\n", active
, crtc
->active
);
10740 I915_STATE_WARN(enabled
!= crtc
->base
.enabled
,
10741 "crtc's computed enabled state doesn't match tracked enabled state "
10742 "(expected %i, found %i)\n", enabled
, crtc
->base
.enabled
);
10744 active
= dev_priv
->display
.get_pipe_config(crtc
,
10747 /* hw state is inconsistent with the pipe quirk */
10748 if ((crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
10749 (crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
10750 active
= crtc
->active
;
10752 for_each_intel_encoder(dev
, encoder
) {
10754 if (encoder
->base
.crtc
!= &crtc
->base
)
10756 if (encoder
->get_hw_state(encoder
, &pipe
))
10757 encoder
->get_config(encoder
, &pipe_config
);
10760 I915_STATE_WARN(crtc
->active
!= active
,
10761 "crtc active state doesn't match with hw state "
10762 "(expected %i, found %i)\n", crtc
->active
, active
);
10765 !intel_pipe_config_compare(dev
, crtc
->config
, &pipe_config
)) {
10766 I915_STATE_WARN(1, "pipe state doesn't match!\n");
10767 intel_dump_pipe_config(crtc
, &pipe_config
,
10769 intel_dump_pipe_config(crtc
, crtc
->config
,
10776 check_shared_dpll_state(struct drm_device
*dev
)
10778 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10779 struct intel_crtc
*crtc
;
10780 struct intel_dpll_hw_state dpll_hw_state
;
10783 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
10784 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
10785 int enabled_crtcs
= 0, active_crtcs
= 0;
10788 memset(&dpll_hw_state
, 0, sizeof(dpll_hw_state
));
10790 DRM_DEBUG_KMS("%s\n", pll
->name
);
10792 active
= pll
->get_hw_state(dev_priv
, pll
, &dpll_hw_state
);
10794 I915_STATE_WARN(pll
->active
> hweight32(pll
->config
.crtc_mask
),
10795 "more active pll users than references: %i vs %i\n",
10796 pll
->active
, hweight32(pll
->config
.crtc_mask
));
10797 I915_STATE_WARN(pll
->active
&& !pll
->on
,
10798 "pll in active use but not on in sw tracking\n");
10799 I915_STATE_WARN(pll
->on
&& !pll
->active
,
10800 "pll in on but not on in use in sw tracking\n");
10801 I915_STATE_WARN(pll
->on
!= active
,
10802 "pll on state mismatch (expected %i, found %i)\n",
10805 for_each_intel_crtc(dev
, crtc
) {
10806 if (crtc
->base
.enabled
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
10808 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
10811 I915_STATE_WARN(pll
->active
!= active_crtcs
,
10812 "pll active crtcs mismatch (expected %i, found %i)\n",
10813 pll
->active
, active_crtcs
);
10814 I915_STATE_WARN(hweight32(pll
->config
.crtc_mask
) != enabled_crtcs
,
10815 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10816 hweight32(pll
->config
.crtc_mask
), enabled_crtcs
);
10818 I915_STATE_WARN(pll
->on
&& memcmp(&pll
->config
.hw_state
, &dpll_hw_state
,
10819 sizeof(dpll_hw_state
)),
10820 "pll hw state mismatch\n");
10825 intel_modeset_check_state(struct drm_device
*dev
)
10827 check_wm_state(dev
);
10828 check_connector_state(dev
);
10829 check_encoder_state(dev
);
10830 check_crtc_state(dev
);
10831 check_shared_dpll_state(dev
);
10834 void ironlake_check_encoder_dotclock(const struct intel_crtc_state
*pipe_config
,
10838 * FDI already provided one idea for the dotclock.
10839 * Yell if the encoder disagrees.
10841 WARN(!intel_fuzzy_clock_check(pipe_config
->base
.adjusted_mode
.crtc_clock
, dotclock
),
10842 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10843 pipe_config
->base
.adjusted_mode
.crtc_clock
, dotclock
);
10846 static void update_scanline_offset(struct intel_crtc
*crtc
)
10848 struct drm_device
*dev
= crtc
->base
.dev
;
10851 * The scanline counter increments at the leading edge of hsync.
10853 * On most platforms it starts counting from vtotal-1 on the
10854 * first active line. That means the scanline counter value is
10855 * always one less than what we would expect. Ie. just after
10856 * start of vblank, which also occurs at start of hsync (on the
10857 * last active line), the scanline counter will read vblank_start-1.
10859 * On gen2 the scanline counter starts counting from 1 instead
10860 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10861 * to keep the value positive), instead of adding one.
10863 * On HSW+ the behaviour of the scanline counter depends on the output
10864 * type. For DP ports it behaves like most other platforms, but on HDMI
10865 * there's an extra 1 line difference. So we need to add two instead of
10866 * one to the value.
10868 if (IS_GEN2(dev
)) {
10869 const struct drm_display_mode
*mode
= &crtc
->config
->base
.adjusted_mode
;
10872 vtotal
= mode
->crtc_vtotal
;
10873 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
10876 crtc
->scanline_offset
= vtotal
- 1;
10877 } else if (HAS_DDI(dev
) &&
10878 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
)) {
10879 crtc
->scanline_offset
= 2;
10881 crtc
->scanline_offset
= 1;
10884 static struct intel_crtc_state
*
10885 intel_modeset_compute_config(struct drm_crtc
*crtc
,
10886 struct drm_display_mode
*mode
,
10887 struct drm_framebuffer
*fb
,
10888 unsigned *modeset_pipes
,
10889 unsigned *prepare_pipes
,
10890 unsigned *disable_pipes
)
10892 struct intel_crtc_state
*pipe_config
= NULL
;
10894 intel_modeset_affected_pipes(crtc
, modeset_pipes
,
10895 prepare_pipes
, disable_pipes
);
10897 if ((*modeset_pipes
) == 0)
10901 * Note this needs changes when we start tracking multiple modes
10902 * and crtcs. At that point we'll need to compute the whole config
10903 * (i.e. one pipe_config for each crtc) rather than just the one
10906 pipe_config
= intel_modeset_pipe_config(crtc
, fb
, mode
);
10907 if (IS_ERR(pipe_config
)) {
10910 intel_dump_pipe_config(to_intel_crtc(crtc
), pipe_config
,
10914 return pipe_config
;
10917 static int __intel_set_mode(struct drm_crtc
*crtc
,
10918 struct drm_display_mode
*mode
,
10919 int x
, int y
, struct drm_framebuffer
*fb
,
10920 struct intel_crtc_state
*pipe_config
,
10921 unsigned modeset_pipes
,
10922 unsigned prepare_pipes
,
10923 unsigned disable_pipes
)
10925 struct drm_device
*dev
= crtc
->dev
;
10926 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10927 struct drm_display_mode
*saved_mode
;
10928 struct intel_crtc
*intel_crtc
;
10931 saved_mode
= kmalloc(sizeof(*saved_mode
), GFP_KERNEL
);
10935 *saved_mode
= crtc
->mode
;
10938 to_intel_crtc(crtc
)->new_config
= pipe_config
;
10941 * See if the config requires any additional preparation, e.g.
10942 * to adjust global state with pipes off. We need to do this
10943 * here so we can get the modeset_pipe updated config for the new
10944 * mode set on this crtc. For other crtcs we need to use the
10945 * adjusted_mode bits in the crtc directly.
10947 if (IS_VALLEYVIEW(dev
)) {
10948 valleyview_modeset_global_pipes(dev
, &prepare_pipes
);
10950 /* may have added more to prepare_pipes than we should */
10951 prepare_pipes
&= ~disable_pipes
;
10954 if (dev_priv
->display
.crtc_compute_clock
) {
10955 unsigned clear_pipes
= modeset_pipes
| disable_pipes
;
10957 ret
= intel_shared_dpll_start_config(dev_priv
, clear_pipes
);
10961 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
10962 struct intel_crtc_state
*state
= intel_crtc
->new_config
;
10963 ret
= dev_priv
->display
.crtc_compute_clock(intel_crtc
,
10966 intel_shared_dpll_abort_config(dev_priv
);
10972 for_each_intel_crtc_masked(dev
, disable_pipes
, intel_crtc
)
10973 intel_crtc_disable(&intel_crtc
->base
);
10975 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
10976 if (intel_crtc
->base
.enabled
)
10977 dev_priv
->display
.crtc_disable(&intel_crtc
->base
);
10980 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10981 * to set it here already despite that we pass it down the callchain.
10983 * Note we'll need to fix this up when we start tracking multiple
10984 * pipes; here we assume a single modeset_pipe and only track the
10985 * single crtc and mode.
10987 if (modeset_pipes
) {
10988 crtc
->mode
= *mode
;
10989 /* mode_set/enable/disable functions rely on a correct pipe
10991 intel_crtc_set_state(to_intel_crtc(crtc
), pipe_config
);
10994 * Calculate and store various constants which
10995 * are later needed by vblank and swap-completion
10996 * timestamping. They are derived from true hwmode.
10998 drm_calc_timestamping_constants(crtc
,
10999 &pipe_config
->base
.adjusted_mode
);
11002 /* Only after disabling all output pipelines that will be changed can we
11003 * update the the output configuration. */
11004 intel_modeset_update_state(dev
, prepare_pipes
);
11006 modeset_update_crtc_power_domains(dev
);
11008 /* Set up the DPLL and any encoders state that needs to adjust or depend
11011 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
11012 struct drm_plane
*primary
= intel_crtc
->base
.primary
;
11013 int vdisplay
, hdisplay
;
11015 drm_crtc_get_hv_timing(mode
, &hdisplay
, &vdisplay
);
11016 ret
= primary
->funcs
->update_plane(primary
, &intel_crtc
->base
,
11018 hdisplay
, vdisplay
,
11020 hdisplay
<< 16, vdisplay
<< 16);
11023 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11024 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
11025 update_scanline_offset(intel_crtc
);
11027 dev_priv
->display
.crtc_enable(&intel_crtc
->base
);
11030 /* FIXME: add subpixel order */
11032 if (ret
&& crtc
->enabled
)
11033 crtc
->mode
= *saved_mode
;
11039 static int intel_set_mode_pipes(struct drm_crtc
*crtc
,
11040 struct drm_display_mode
*mode
,
11041 int x
, int y
, struct drm_framebuffer
*fb
,
11042 struct intel_crtc_state
*pipe_config
,
11043 unsigned modeset_pipes
,
11044 unsigned prepare_pipes
,
11045 unsigned disable_pipes
)
11049 ret
= __intel_set_mode(crtc
, mode
, x
, y
, fb
, pipe_config
, modeset_pipes
,
11050 prepare_pipes
, disable_pipes
);
11053 intel_modeset_check_state(crtc
->dev
);
11058 static int intel_set_mode(struct drm_crtc
*crtc
,
11059 struct drm_display_mode
*mode
,
11060 int x
, int y
, struct drm_framebuffer
*fb
)
11062 struct intel_crtc_state
*pipe_config
;
11063 unsigned modeset_pipes
, prepare_pipes
, disable_pipes
;
11065 pipe_config
= intel_modeset_compute_config(crtc
, mode
, fb
,
11070 if (IS_ERR(pipe_config
))
11071 return PTR_ERR(pipe_config
);
11073 return intel_set_mode_pipes(crtc
, mode
, x
, y
, fb
, pipe_config
,
11074 modeset_pipes
, prepare_pipes
,
11078 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
11080 intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
, crtc
->primary
->fb
);
11083 #undef for_each_intel_crtc_masked
11085 static void intel_set_config_free(struct intel_set_config
*config
)
11090 kfree(config
->save_connector_encoders
);
11091 kfree(config
->save_encoder_crtcs
);
11092 kfree(config
->save_crtc_enabled
);
11096 static int intel_set_config_save_state(struct drm_device
*dev
,
11097 struct intel_set_config
*config
)
11099 struct drm_crtc
*crtc
;
11100 struct drm_encoder
*encoder
;
11101 struct drm_connector
*connector
;
11104 config
->save_crtc_enabled
=
11105 kcalloc(dev
->mode_config
.num_crtc
,
11106 sizeof(bool), GFP_KERNEL
);
11107 if (!config
->save_crtc_enabled
)
11110 config
->save_encoder_crtcs
=
11111 kcalloc(dev
->mode_config
.num_encoder
,
11112 sizeof(struct drm_crtc
*), GFP_KERNEL
);
11113 if (!config
->save_encoder_crtcs
)
11116 config
->save_connector_encoders
=
11117 kcalloc(dev
->mode_config
.num_connector
,
11118 sizeof(struct drm_encoder
*), GFP_KERNEL
);
11119 if (!config
->save_connector_encoders
)
11122 /* Copy data. Note that driver private data is not affected.
11123 * Should anything bad happen only the expected state is
11124 * restored, not the drivers personal bookkeeping.
11127 for_each_crtc(dev
, crtc
) {
11128 config
->save_crtc_enabled
[count
++] = crtc
->enabled
;
11132 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
11133 config
->save_encoder_crtcs
[count
++] = encoder
->crtc
;
11137 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
11138 config
->save_connector_encoders
[count
++] = connector
->encoder
;
11144 static void intel_set_config_restore_state(struct drm_device
*dev
,
11145 struct intel_set_config
*config
)
11147 struct intel_crtc
*crtc
;
11148 struct intel_encoder
*encoder
;
11149 struct intel_connector
*connector
;
11153 for_each_intel_crtc(dev
, crtc
) {
11154 crtc
->new_enabled
= config
->save_crtc_enabled
[count
++];
11156 if (crtc
->new_enabled
)
11157 crtc
->new_config
= crtc
->config
;
11159 crtc
->new_config
= NULL
;
11163 for_each_intel_encoder(dev
, encoder
) {
11164 encoder
->new_crtc
=
11165 to_intel_crtc(config
->save_encoder_crtcs
[count
++]);
11169 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
11170 connector
->new_encoder
=
11171 to_intel_encoder(config
->save_connector_encoders
[count
++]);
11176 is_crtc_connector_off(struct drm_mode_set
*set
)
11180 if (set
->num_connectors
== 0)
11183 if (WARN_ON(set
->connectors
== NULL
))
11186 for (i
= 0; i
< set
->num_connectors
; i
++)
11187 if (set
->connectors
[i
]->encoder
&&
11188 set
->connectors
[i
]->encoder
->crtc
== set
->crtc
&&
11189 set
->connectors
[i
]->dpms
!= DRM_MODE_DPMS_ON
)
11196 intel_set_config_compute_mode_changes(struct drm_mode_set
*set
,
11197 struct intel_set_config
*config
)
11200 /* We should be able to check here if the fb has the same properties
11201 * and then just flip_or_move it */
11202 if (is_crtc_connector_off(set
)) {
11203 config
->mode_changed
= true;
11204 } else if (set
->crtc
->primary
->fb
!= set
->fb
) {
11206 * If we have no fb, we can only flip as long as the crtc is
11207 * active, otherwise we need a full mode set. The crtc may
11208 * be active if we've only disabled the primary plane, or
11209 * in fastboot situations.
11211 if (set
->crtc
->primary
->fb
== NULL
) {
11212 struct intel_crtc
*intel_crtc
=
11213 to_intel_crtc(set
->crtc
);
11215 if (intel_crtc
->active
) {
11216 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11217 config
->fb_changed
= true;
11219 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11220 config
->mode_changed
= true;
11222 } else if (set
->fb
== NULL
) {
11223 config
->mode_changed
= true;
11224 } else if (set
->fb
->pixel_format
!=
11225 set
->crtc
->primary
->fb
->pixel_format
) {
11226 config
->mode_changed
= true;
11228 config
->fb_changed
= true;
11232 if (set
->fb
&& (set
->x
!= set
->crtc
->x
|| set
->y
!= set
->crtc
->y
))
11233 config
->fb_changed
= true;
11235 if (set
->mode
&& !drm_mode_equal(set
->mode
, &set
->crtc
->mode
)) {
11236 DRM_DEBUG_KMS("modes are different, full mode set\n");
11237 drm_mode_debug_printmodeline(&set
->crtc
->mode
);
11238 drm_mode_debug_printmodeline(set
->mode
);
11239 config
->mode_changed
= true;
11242 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11243 set
->crtc
->base
.id
, config
->mode_changed
, config
->fb_changed
);
11247 intel_modeset_stage_output_state(struct drm_device
*dev
,
11248 struct drm_mode_set
*set
,
11249 struct intel_set_config
*config
)
11251 struct intel_connector
*connector
;
11252 struct intel_encoder
*encoder
;
11253 struct intel_crtc
*crtc
;
11256 /* The upper layers ensure that we either disable a crtc or have a list
11257 * of connectors. For paranoia, double-check this. */
11258 WARN_ON(!set
->fb
&& (set
->num_connectors
!= 0));
11259 WARN_ON(set
->fb
&& (set
->num_connectors
== 0));
11261 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
11263 /* Otherwise traverse passed in connector list and get encoders
11265 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
11266 if (set
->connectors
[ro
] == &connector
->base
) {
11267 connector
->new_encoder
= intel_find_encoder(connector
, to_intel_crtc(set
->crtc
)->pipe
);
11272 /* If we disable the crtc, disable all its connectors. Also, if
11273 * the connector is on the changing crtc but not on the new
11274 * connector list, disable it. */
11275 if ((!set
->fb
|| ro
== set
->num_connectors
) &&
11276 connector
->base
.encoder
&&
11277 connector
->base
.encoder
->crtc
== set
->crtc
) {
11278 connector
->new_encoder
= NULL
;
11280 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11281 connector
->base
.base
.id
,
11282 connector
->base
.name
);
11286 if (&connector
->new_encoder
->base
!= connector
->base
.encoder
) {
11287 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11288 config
->mode_changed
= true;
11291 /* connector->new_encoder is now updated for all connectors. */
11293 /* Update crtc of enabled connectors. */
11294 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
11296 struct drm_crtc
*new_crtc
;
11298 if (!connector
->new_encoder
)
11301 new_crtc
= connector
->new_encoder
->base
.crtc
;
11303 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
11304 if (set
->connectors
[ro
] == &connector
->base
)
11305 new_crtc
= set
->crtc
;
11308 /* Make sure the new CRTC will work with the encoder */
11309 if (!drm_encoder_crtc_ok(&connector
->new_encoder
->base
,
11313 connector
->new_encoder
->new_crtc
= to_intel_crtc(new_crtc
);
11315 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11316 connector
->base
.base
.id
,
11317 connector
->base
.name
,
11318 new_crtc
->base
.id
);
11321 /* Check for any encoders that needs to be disabled. */
11322 for_each_intel_encoder(dev
, encoder
) {
11323 int num_connectors
= 0;
11324 list_for_each_entry(connector
,
11325 &dev
->mode_config
.connector_list
,
11327 if (connector
->new_encoder
== encoder
) {
11328 WARN_ON(!connector
->new_encoder
->new_crtc
);
11333 if (num_connectors
== 0)
11334 encoder
->new_crtc
= NULL
;
11335 else if (num_connectors
> 1)
11338 /* Only now check for crtc changes so we don't miss encoders
11339 * that will be disabled. */
11340 if (&encoder
->new_crtc
->base
!= encoder
->base
.crtc
) {
11341 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11342 config
->mode_changed
= true;
11345 /* Now we've also updated encoder->new_crtc for all encoders. */
11346 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
11348 if (connector
->new_encoder
)
11349 if (connector
->new_encoder
!= connector
->encoder
)
11350 connector
->encoder
= connector
->new_encoder
;
11352 for_each_intel_crtc(dev
, crtc
) {
11353 crtc
->new_enabled
= false;
11355 for_each_intel_encoder(dev
, encoder
) {
11356 if (encoder
->new_crtc
== crtc
) {
11357 crtc
->new_enabled
= true;
11362 if (crtc
->new_enabled
!= crtc
->base
.enabled
) {
11363 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11364 crtc
->new_enabled
? "en" : "dis");
11365 config
->mode_changed
= true;
11368 if (crtc
->new_enabled
)
11369 crtc
->new_config
= crtc
->config
;
11371 crtc
->new_config
= NULL
;
11377 static void disable_crtc_nofb(struct intel_crtc
*crtc
)
11379 struct drm_device
*dev
= crtc
->base
.dev
;
11380 struct intel_encoder
*encoder
;
11381 struct intel_connector
*connector
;
11383 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11384 pipe_name(crtc
->pipe
));
11386 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
11387 if (connector
->new_encoder
&&
11388 connector
->new_encoder
->new_crtc
== crtc
)
11389 connector
->new_encoder
= NULL
;
11392 for_each_intel_encoder(dev
, encoder
) {
11393 if (encoder
->new_crtc
== crtc
)
11394 encoder
->new_crtc
= NULL
;
11397 crtc
->new_enabled
= false;
11398 crtc
->new_config
= NULL
;
11401 static int intel_crtc_set_config(struct drm_mode_set
*set
)
11403 struct drm_device
*dev
;
11404 struct drm_mode_set save_set
;
11405 struct intel_set_config
*config
;
11406 struct intel_crtc_state
*pipe_config
;
11407 unsigned modeset_pipes
, prepare_pipes
, disable_pipes
;
11411 BUG_ON(!set
->crtc
);
11412 BUG_ON(!set
->crtc
->helper_private
);
11414 /* Enforce sane interface api - has been abused by the fb helper. */
11415 BUG_ON(!set
->mode
&& set
->fb
);
11416 BUG_ON(set
->fb
&& set
->num_connectors
== 0);
11419 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11420 set
->crtc
->base
.id
, set
->fb
->base
.id
,
11421 (int)set
->num_connectors
, set
->x
, set
->y
);
11423 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set
->crtc
->base
.id
);
11426 dev
= set
->crtc
->dev
;
11429 config
= kzalloc(sizeof(*config
), GFP_KERNEL
);
11433 ret
= intel_set_config_save_state(dev
, config
);
11437 save_set
.crtc
= set
->crtc
;
11438 save_set
.mode
= &set
->crtc
->mode
;
11439 save_set
.x
= set
->crtc
->x
;
11440 save_set
.y
= set
->crtc
->y
;
11441 save_set
.fb
= set
->crtc
->primary
->fb
;
11443 /* Compute whether we need a full modeset, only an fb base update or no
11444 * change at all. In the future we might also check whether only the
11445 * mode changed, e.g. for LVDS where we only change the panel fitter in
11447 intel_set_config_compute_mode_changes(set
, config
);
11449 ret
= intel_modeset_stage_output_state(dev
, set
, config
);
11453 pipe_config
= intel_modeset_compute_config(set
->crtc
, set
->mode
,
11458 if (IS_ERR(pipe_config
)) {
11459 ret
= PTR_ERR(pipe_config
);
11461 } else if (pipe_config
) {
11462 if (pipe_config
->has_audio
!=
11463 to_intel_crtc(set
->crtc
)->config
->has_audio
)
11464 config
->mode_changed
= true;
11467 * Note we have an issue here with infoframes: current code
11468 * only updates them on the full mode set path per hw
11469 * requirements. So here we should be checking for any
11470 * required changes and forcing a mode set.
11474 /* set_mode will free it in the mode_changed case */
11475 if (!config
->mode_changed
)
11476 kfree(pipe_config
);
11478 intel_update_pipe_size(to_intel_crtc(set
->crtc
));
11480 if (config
->mode_changed
) {
11481 ret
= intel_set_mode_pipes(set
->crtc
, set
->mode
,
11482 set
->x
, set
->y
, set
->fb
, pipe_config
,
11483 modeset_pipes
, prepare_pipes
,
11485 } else if (config
->fb_changed
) {
11486 struct intel_crtc
*intel_crtc
= to_intel_crtc(set
->crtc
);
11487 struct drm_plane
*primary
= set
->crtc
->primary
;
11488 int vdisplay
, hdisplay
;
11490 drm_crtc_get_hv_timing(set
->mode
, &hdisplay
, &vdisplay
);
11491 ret
= primary
->funcs
->update_plane(primary
, set
->crtc
, set
->fb
,
11492 0, 0, hdisplay
, vdisplay
,
11493 set
->x
<< 16, set
->y
<< 16,
11494 hdisplay
<< 16, vdisplay
<< 16);
11497 * We need to make sure the primary plane is re-enabled if it
11498 * has previously been turned off.
11500 if (!intel_crtc
->primary_enabled
&& ret
== 0) {
11501 WARN_ON(!intel_crtc
->active
);
11502 intel_enable_primary_hw_plane(set
->crtc
->primary
, set
->crtc
);
11506 * In the fastboot case this may be our only check of the
11507 * state after boot. It would be better to only do it on
11508 * the first update, but we don't have a nice way of doing that
11509 * (and really, set_config isn't used much for high freq page
11510 * flipping, so increasing its cost here shouldn't be a big
11513 if (i915
.fastboot
&& ret
== 0)
11514 intel_modeset_check_state(set
->crtc
->dev
);
11518 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11519 set
->crtc
->base
.id
, ret
);
11521 intel_set_config_restore_state(dev
, config
);
11524 * HACK: if the pipe was on, but we didn't have a framebuffer,
11525 * force the pipe off to avoid oopsing in the modeset code
11526 * due to fb==NULL. This should only happen during boot since
11527 * we don't yet reconstruct the FB from the hardware state.
11529 if (to_intel_crtc(save_set
.crtc
)->new_enabled
&& !save_set
.fb
)
11530 disable_crtc_nofb(to_intel_crtc(save_set
.crtc
));
11532 /* Try to restore the config */
11533 if (config
->mode_changed
&&
11534 intel_set_mode(save_set
.crtc
, save_set
.mode
,
11535 save_set
.x
, save_set
.y
, save_set
.fb
))
11536 DRM_ERROR("failed to restore config after modeset failure\n");
11540 intel_set_config_free(config
);
11544 static const struct drm_crtc_funcs intel_crtc_funcs
= {
11545 .gamma_set
= intel_crtc_gamma_set
,
11546 .set_config
= intel_crtc_set_config
,
11547 .destroy
= intel_crtc_destroy
,
11548 .page_flip
= intel_crtc_page_flip
,
11551 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private
*dev_priv
,
11552 struct intel_shared_dpll
*pll
,
11553 struct intel_dpll_hw_state
*hw_state
)
11557 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
11560 val
= I915_READ(PCH_DPLL(pll
->id
));
11561 hw_state
->dpll
= val
;
11562 hw_state
->fp0
= I915_READ(PCH_FP0(pll
->id
));
11563 hw_state
->fp1
= I915_READ(PCH_FP1(pll
->id
));
11565 return val
& DPLL_VCO_ENABLE
;
11568 static void ibx_pch_dpll_mode_set(struct drm_i915_private
*dev_priv
,
11569 struct intel_shared_dpll
*pll
)
11571 I915_WRITE(PCH_FP0(pll
->id
), pll
->config
.hw_state
.fp0
);
11572 I915_WRITE(PCH_FP1(pll
->id
), pll
->config
.hw_state
.fp1
);
11575 static void ibx_pch_dpll_enable(struct drm_i915_private
*dev_priv
,
11576 struct intel_shared_dpll
*pll
)
11578 /* PCH refclock must be enabled first */
11579 ibx_assert_pch_refclk_enabled(dev_priv
);
11581 I915_WRITE(PCH_DPLL(pll
->id
), pll
->config
.hw_state
.dpll
);
11583 /* Wait for the clocks to stabilize. */
11584 POSTING_READ(PCH_DPLL(pll
->id
));
11587 /* The pixel multiplier can only be updated once the
11588 * DPLL is enabled and the clocks are stable.
11590 * So write it again.
11592 I915_WRITE(PCH_DPLL(pll
->id
), pll
->config
.hw_state
.dpll
);
11593 POSTING_READ(PCH_DPLL(pll
->id
));
11597 static void ibx_pch_dpll_disable(struct drm_i915_private
*dev_priv
,
11598 struct intel_shared_dpll
*pll
)
11600 struct drm_device
*dev
= dev_priv
->dev
;
11601 struct intel_crtc
*crtc
;
11603 /* Make sure no transcoder isn't still depending on us. */
11604 for_each_intel_crtc(dev
, crtc
) {
11605 if (intel_crtc_to_shared_dpll(crtc
) == pll
)
11606 assert_pch_transcoder_disabled(dev_priv
, crtc
->pipe
);
11609 I915_WRITE(PCH_DPLL(pll
->id
), 0);
11610 POSTING_READ(PCH_DPLL(pll
->id
));
11614 static char *ibx_pch_dpll_names
[] = {
11619 static void ibx_pch_dpll_init(struct drm_device
*dev
)
11621 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11624 dev_priv
->num_shared_dpll
= 2;
11626 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
11627 dev_priv
->shared_dplls
[i
].id
= i
;
11628 dev_priv
->shared_dplls
[i
].name
= ibx_pch_dpll_names
[i
];
11629 dev_priv
->shared_dplls
[i
].mode_set
= ibx_pch_dpll_mode_set
;
11630 dev_priv
->shared_dplls
[i
].enable
= ibx_pch_dpll_enable
;
11631 dev_priv
->shared_dplls
[i
].disable
= ibx_pch_dpll_disable
;
11632 dev_priv
->shared_dplls
[i
].get_hw_state
=
11633 ibx_pch_dpll_get_hw_state
;
11637 static void intel_shared_dpll_init(struct drm_device
*dev
)
11639 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11642 intel_ddi_pll_init(dev
);
11643 else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
11644 ibx_pch_dpll_init(dev
);
11646 dev_priv
->num_shared_dpll
= 0;
11648 BUG_ON(dev_priv
->num_shared_dpll
> I915_NUM_PLLS
);
11652 * intel_prepare_plane_fb - Prepare fb for usage on plane
11653 * @plane: drm plane to prepare for
11654 * @fb: framebuffer to prepare for presentation
11656 * Prepares a framebuffer for usage on a display plane. Generally this
11657 * involves pinning the underlying object and updating the frontbuffer tracking
11658 * bits. Some older platforms need special physical address handling for
11661 * Returns 0 on success, negative error code on failure.
11664 intel_prepare_plane_fb(struct drm_plane
*plane
,
11665 struct drm_framebuffer
*fb
)
11667 struct drm_device
*dev
= plane
->dev
;
11668 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
11669 enum pipe pipe
= intel_plane
->pipe
;
11670 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
11671 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(plane
->fb
);
11672 unsigned frontbuffer_bits
= 0;
11678 switch (plane
->type
) {
11679 case DRM_PLANE_TYPE_PRIMARY
:
11680 frontbuffer_bits
= INTEL_FRONTBUFFER_PRIMARY(pipe
);
11682 case DRM_PLANE_TYPE_CURSOR
:
11683 frontbuffer_bits
= INTEL_FRONTBUFFER_CURSOR(pipe
);
11685 case DRM_PLANE_TYPE_OVERLAY
:
11686 frontbuffer_bits
= INTEL_FRONTBUFFER_SPRITE(pipe
);
11690 mutex_lock(&dev
->struct_mutex
);
11692 if (plane
->type
== DRM_PLANE_TYPE_CURSOR
&&
11693 INTEL_INFO(dev
)->cursor_needs_physical
) {
11694 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
11695 ret
= i915_gem_object_attach_phys(obj
, align
);
11697 DRM_DEBUG_KMS("failed to attach phys object\n");
11699 ret
= intel_pin_and_fence_fb_obj(plane
, fb
, NULL
);
11703 i915_gem_track_fb(old_obj
, obj
, frontbuffer_bits
);
11705 mutex_unlock(&dev
->struct_mutex
);
11711 * intel_cleanup_plane_fb - Cleans up an fb after plane use
11712 * @plane: drm plane to clean up for
11713 * @fb: old framebuffer that was on plane
11715 * Cleans up a framebuffer that has just been removed from a plane.
11718 intel_cleanup_plane_fb(struct drm_plane
*plane
,
11719 struct drm_framebuffer
*fb
)
11721 struct drm_device
*dev
= plane
->dev
;
11722 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
11727 if (plane
->type
!= DRM_PLANE_TYPE_CURSOR
||
11728 !INTEL_INFO(dev
)->cursor_needs_physical
) {
11729 mutex_lock(&dev
->struct_mutex
);
11730 intel_unpin_fb_obj(obj
);
11731 mutex_unlock(&dev
->struct_mutex
);
11736 intel_check_primary_plane(struct drm_plane
*plane
,
11737 struct intel_plane_state
*state
)
11739 struct drm_device
*dev
= plane
->dev
;
11740 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11741 struct drm_crtc
*crtc
= state
->base
.crtc
;
11742 struct intel_crtc
*intel_crtc
;
11743 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
11744 struct drm_framebuffer
*fb
= state
->base
.fb
;
11745 struct drm_rect
*dest
= &state
->dst
;
11746 struct drm_rect
*src
= &state
->src
;
11747 const struct drm_rect
*clip
= &state
->clip
;
11750 crtc
= crtc
? crtc
: plane
->crtc
;
11751 intel_crtc
= to_intel_crtc(crtc
);
11753 ret
= drm_plane_helper_check_update(plane
, crtc
, fb
,
11755 DRM_PLANE_HELPER_NO_SCALING
,
11756 DRM_PLANE_HELPER_NO_SCALING
,
11757 false, true, &state
->visible
);
11761 if (intel_crtc
->active
) {
11762 intel_crtc
->atomic
.wait_for_flips
= true;
11765 * FBC does not work on some platforms for rotated
11766 * planes, so disable it when rotation is not 0 and
11767 * update it when rotation is set back to 0.
11769 * FIXME: This is redundant with the fbc update done in
11770 * the primary plane enable function except that that
11771 * one is done too late. We eventually need to unify
11774 if (intel_crtc
->primary_enabled
&&
11775 INTEL_INFO(dev
)->gen
<= 4 && !IS_G4X(dev
) &&
11776 dev_priv
->fbc
.plane
== intel_crtc
->plane
&&
11777 intel_plane
->rotation
!= BIT(DRM_ROTATE_0
)) {
11778 intel_crtc
->atomic
.disable_fbc
= true;
11781 if (state
->visible
) {
11783 * BDW signals flip done immediately if the plane
11784 * is disabled, even if the plane enable is already
11785 * armed to occur at the next vblank :(
11787 if (IS_BROADWELL(dev
) && !intel_crtc
->primary_enabled
)
11788 intel_crtc
->atomic
.wait_vblank
= true;
11791 intel_crtc
->atomic
.fb_bits
|=
11792 INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
);
11794 intel_crtc
->atomic
.update_fbc
= true;
11801 intel_commit_primary_plane(struct drm_plane
*plane
,
11802 struct intel_plane_state
*state
)
11804 struct drm_crtc
*crtc
= state
->base
.crtc
;
11805 struct drm_framebuffer
*fb
= state
->base
.fb
;
11806 struct drm_device
*dev
= plane
->dev
;
11807 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11808 struct intel_crtc
*intel_crtc
;
11809 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
11810 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
11811 struct drm_rect
*src
= &state
->src
;
11813 crtc
= crtc
? crtc
: plane
->crtc
;
11814 intel_crtc
= to_intel_crtc(crtc
);
11817 crtc
->x
= src
->x1
>> 16;
11818 crtc
->y
= src
->y1
>> 16;
11820 intel_plane
->obj
= obj
;
11822 if (intel_crtc
->active
) {
11823 if (state
->visible
) {
11824 /* FIXME: kill this fastboot hack */
11825 intel_update_pipe_size(intel_crtc
);
11827 intel_crtc
->primary_enabled
= true;
11829 dev_priv
->display
.update_primary_plane(crtc
, plane
->fb
,
11833 * If clipping results in a non-visible primary plane,
11834 * we'll disable the primary plane. Note that this is
11835 * a bit different than what happens if userspace
11836 * explicitly disables the plane by passing fb=0
11837 * because plane->fb still gets set and pinned.
11839 intel_disable_primary_hw_plane(plane
, crtc
);
11844 static void intel_begin_crtc_commit(struct drm_crtc
*crtc
)
11846 struct drm_device
*dev
= crtc
->dev
;
11847 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11848 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11849 struct intel_plane
*intel_plane
;
11850 struct drm_plane
*p
;
11851 unsigned fb_bits
= 0;
11853 /* Track fb's for any planes being disabled */
11854 list_for_each_entry(p
, &dev
->mode_config
.plane_list
, head
) {
11855 intel_plane
= to_intel_plane(p
);
11857 if (intel_crtc
->atomic
.disabled_planes
&
11858 (1 << drm_plane_index(p
))) {
11860 case DRM_PLANE_TYPE_PRIMARY
:
11861 fb_bits
= INTEL_FRONTBUFFER_PRIMARY(intel_plane
->pipe
);
11863 case DRM_PLANE_TYPE_CURSOR
:
11864 fb_bits
= INTEL_FRONTBUFFER_CURSOR(intel_plane
->pipe
);
11866 case DRM_PLANE_TYPE_OVERLAY
:
11867 fb_bits
= INTEL_FRONTBUFFER_SPRITE(intel_plane
->pipe
);
11871 mutex_lock(&dev
->struct_mutex
);
11872 i915_gem_track_fb(intel_fb_obj(p
->fb
), NULL
, fb_bits
);
11873 mutex_unlock(&dev
->struct_mutex
);
11877 if (intel_crtc
->atomic
.wait_for_flips
)
11878 intel_crtc_wait_for_pending_flips(crtc
);
11880 if (intel_crtc
->atomic
.disable_fbc
)
11881 intel_fbc_disable(dev
);
11883 if (intel_crtc
->atomic
.pre_disable_primary
)
11884 intel_pre_disable_primary(crtc
);
11886 if (intel_crtc
->atomic
.update_wm
)
11887 intel_update_watermarks(crtc
);
11889 intel_runtime_pm_get(dev_priv
);
11891 /* Perform vblank evasion around commit operation */
11892 if (intel_crtc
->active
)
11893 intel_crtc
->atomic
.evade
=
11894 intel_pipe_update_start(intel_crtc
,
11895 &intel_crtc
->atomic
.start_vbl_count
);
11898 static void intel_finish_crtc_commit(struct drm_crtc
*crtc
)
11900 struct drm_device
*dev
= crtc
->dev
;
11901 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11902 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11903 struct drm_plane
*p
;
11905 if (intel_crtc
->atomic
.evade
)
11906 intel_pipe_update_end(intel_crtc
,
11907 intel_crtc
->atomic
.start_vbl_count
);
11909 intel_runtime_pm_put(dev_priv
);
11911 if (intel_crtc
->atomic
.wait_vblank
)
11912 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
11914 intel_frontbuffer_flip(dev
, intel_crtc
->atomic
.fb_bits
);
11916 if (intel_crtc
->atomic
.update_fbc
) {
11917 mutex_lock(&dev
->struct_mutex
);
11918 intel_fbc_update(dev
);
11919 mutex_unlock(&dev
->struct_mutex
);
11922 if (intel_crtc
->atomic
.post_enable_primary
)
11923 intel_post_enable_primary(crtc
);
11925 drm_for_each_legacy_plane(p
, &dev
->mode_config
.plane_list
)
11926 if (intel_crtc
->atomic
.update_sprite_watermarks
& drm_plane_index(p
))
11927 intel_update_sprite_watermarks(p
, crtc
, 0, 0, 0,
11930 memset(&intel_crtc
->atomic
, 0, sizeof(intel_crtc
->atomic
));
11934 * intel_plane_destroy - destroy a plane
11935 * @plane: plane to destroy
11937 * Common destruction function for all types of planes (primary, cursor,
11940 void intel_plane_destroy(struct drm_plane
*plane
)
11942 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
11943 drm_plane_cleanup(plane
);
11944 kfree(intel_plane
);
11947 static const struct drm_plane_funcs intel_primary_plane_funcs
= {
11948 .update_plane
= drm_plane_helper_update
,
11949 .disable_plane
= drm_plane_helper_disable
,
11950 .destroy
= intel_plane_destroy
,
11951 .set_property
= intel_plane_set_property
,
11952 .atomic_duplicate_state
= intel_plane_duplicate_state
,
11953 .atomic_destroy_state
= intel_plane_destroy_state
,
11957 static struct drm_plane
*intel_primary_plane_create(struct drm_device
*dev
,
11960 struct intel_plane
*primary
;
11961 const uint32_t *intel_primary_formats
;
11964 primary
= kzalloc(sizeof(*primary
), GFP_KERNEL
);
11965 if (primary
== NULL
)
11968 primary
->base
.state
= intel_plane_duplicate_state(&primary
->base
);
11969 if (primary
->base
.state
== NULL
) {
11974 primary
->can_scale
= false;
11975 primary
->max_downscale
= 1;
11976 primary
->pipe
= pipe
;
11977 primary
->plane
= pipe
;
11978 primary
->rotation
= BIT(DRM_ROTATE_0
);
11979 primary
->check_plane
= intel_check_primary_plane
;
11980 primary
->commit_plane
= intel_commit_primary_plane
;
11981 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4)
11982 primary
->plane
= !pipe
;
11984 if (INTEL_INFO(dev
)->gen
<= 3) {
11985 intel_primary_formats
= intel_primary_formats_gen2
;
11986 num_formats
= ARRAY_SIZE(intel_primary_formats_gen2
);
11988 intel_primary_formats
= intel_primary_formats_gen4
;
11989 num_formats
= ARRAY_SIZE(intel_primary_formats_gen4
);
11992 drm_universal_plane_init(dev
, &primary
->base
, 0,
11993 &intel_primary_plane_funcs
,
11994 intel_primary_formats
, num_formats
,
11995 DRM_PLANE_TYPE_PRIMARY
);
11997 if (INTEL_INFO(dev
)->gen
>= 4) {
11998 if (!dev
->mode_config
.rotation_property
)
11999 dev
->mode_config
.rotation_property
=
12000 drm_mode_create_rotation_property(dev
,
12001 BIT(DRM_ROTATE_0
) |
12002 BIT(DRM_ROTATE_180
));
12003 if (dev
->mode_config
.rotation_property
)
12004 drm_object_attach_property(&primary
->base
.base
,
12005 dev
->mode_config
.rotation_property
,
12006 primary
->rotation
);
12009 drm_plane_helper_add(&primary
->base
, &intel_plane_helper_funcs
);
12011 return &primary
->base
;
12015 intel_check_cursor_plane(struct drm_plane
*plane
,
12016 struct intel_plane_state
*state
)
12018 struct drm_crtc
*crtc
= state
->base
.crtc
;
12019 struct drm_device
*dev
= plane
->dev
;
12020 struct drm_framebuffer
*fb
= state
->base
.fb
;
12021 struct drm_rect
*dest
= &state
->dst
;
12022 struct drm_rect
*src
= &state
->src
;
12023 const struct drm_rect
*clip
= &state
->clip
;
12024 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
12025 struct intel_crtc
*intel_crtc
;
12029 crtc
= crtc
? crtc
: plane
->crtc
;
12030 intel_crtc
= to_intel_crtc(crtc
);
12032 ret
= drm_plane_helper_check_update(plane
, crtc
, fb
,
12034 DRM_PLANE_HELPER_NO_SCALING
,
12035 DRM_PLANE_HELPER_NO_SCALING
,
12036 true, true, &state
->visible
);
12041 /* if we want to turn off the cursor ignore width and height */
12045 /* Check for which cursor types we support */
12046 if (!cursor_size_ok(dev
, state
->base
.crtc_w
, state
->base
.crtc_h
)) {
12047 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
12048 state
->base
.crtc_w
, state
->base
.crtc_h
);
12052 stride
= roundup_pow_of_two(state
->base
.crtc_w
) * 4;
12053 if (obj
->base
.size
< stride
* state
->base
.crtc_h
) {
12054 DRM_DEBUG_KMS("buffer is too small\n");
12058 if (fb
== crtc
->cursor
->fb
)
12061 /* we only need to pin inside GTT if cursor is non-phy */
12062 mutex_lock(&dev
->struct_mutex
);
12063 if (!INTEL_INFO(dev
)->cursor_needs_physical
&& obj
->tiling_mode
) {
12064 DRM_DEBUG_KMS("cursor cannot be tiled\n");
12067 mutex_unlock(&dev
->struct_mutex
);
12070 if (intel_crtc
->active
) {
12071 if (intel_crtc
->cursor_width
!= state
->base
.crtc_w
)
12072 intel_crtc
->atomic
.update_wm
= true;
12074 intel_crtc
->atomic
.fb_bits
|=
12075 INTEL_FRONTBUFFER_CURSOR(intel_crtc
->pipe
);
12082 intel_commit_cursor_plane(struct drm_plane
*plane
,
12083 struct intel_plane_state
*state
)
12085 struct drm_crtc
*crtc
= state
->base
.crtc
;
12086 struct drm_device
*dev
= plane
->dev
;
12087 struct intel_crtc
*intel_crtc
;
12088 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
12089 struct drm_i915_gem_object
*obj
= intel_fb_obj(state
->base
.fb
);
12092 crtc
= crtc
? crtc
: plane
->crtc
;
12093 intel_crtc
= to_intel_crtc(crtc
);
12095 plane
->fb
= state
->base
.fb
;
12096 crtc
->cursor_x
= state
->base
.crtc_x
;
12097 crtc
->cursor_y
= state
->base
.crtc_y
;
12099 intel_plane
->obj
= obj
;
12101 if (intel_crtc
->cursor_bo
== obj
)
12106 else if (!INTEL_INFO(dev
)->cursor_needs_physical
)
12107 addr
= i915_gem_obj_ggtt_offset(obj
);
12109 addr
= obj
->phys_handle
->busaddr
;
12111 intel_crtc
->cursor_addr
= addr
;
12112 intel_crtc
->cursor_bo
= obj
;
12114 intel_crtc
->cursor_width
= state
->base
.crtc_w
;
12115 intel_crtc
->cursor_height
= state
->base
.crtc_h
;
12117 if (intel_crtc
->active
)
12118 intel_crtc_update_cursor(crtc
, state
->visible
);
12121 static const struct drm_plane_funcs intel_cursor_plane_funcs
= {
12122 .update_plane
= drm_plane_helper_update
,
12123 .disable_plane
= drm_plane_helper_disable
,
12124 .destroy
= intel_plane_destroy
,
12125 .set_property
= intel_plane_set_property
,
12126 .atomic_duplicate_state
= intel_plane_duplicate_state
,
12127 .atomic_destroy_state
= intel_plane_destroy_state
,
12130 static struct drm_plane
*intel_cursor_plane_create(struct drm_device
*dev
,
12133 struct intel_plane
*cursor
;
12135 cursor
= kzalloc(sizeof(*cursor
), GFP_KERNEL
);
12136 if (cursor
== NULL
)
12139 cursor
->base
.state
= intel_plane_duplicate_state(&cursor
->base
);
12140 if (cursor
->base
.state
== NULL
) {
12145 cursor
->can_scale
= false;
12146 cursor
->max_downscale
= 1;
12147 cursor
->pipe
= pipe
;
12148 cursor
->plane
= pipe
;
12149 cursor
->rotation
= BIT(DRM_ROTATE_0
);
12150 cursor
->check_plane
= intel_check_cursor_plane
;
12151 cursor
->commit_plane
= intel_commit_cursor_plane
;
12153 drm_universal_plane_init(dev
, &cursor
->base
, 0,
12154 &intel_cursor_plane_funcs
,
12155 intel_cursor_formats
,
12156 ARRAY_SIZE(intel_cursor_formats
),
12157 DRM_PLANE_TYPE_CURSOR
);
12159 if (INTEL_INFO(dev
)->gen
>= 4) {
12160 if (!dev
->mode_config
.rotation_property
)
12161 dev
->mode_config
.rotation_property
=
12162 drm_mode_create_rotation_property(dev
,
12163 BIT(DRM_ROTATE_0
) |
12164 BIT(DRM_ROTATE_180
));
12165 if (dev
->mode_config
.rotation_property
)
12166 drm_object_attach_property(&cursor
->base
.base
,
12167 dev
->mode_config
.rotation_property
,
12171 drm_plane_helper_add(&cursor
->base
, &intel_plane_helper_funcs
);
12173 return &cursor
->base
;
12176 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
12178 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12179 struct intel_crtc
*intel_crtc
;
12180 struct intel_crtc_state
*crtc_state
= NULL
;
12181 struct drm_plane
*primary
= NULL
;
12182 struct drm_plane
*cursor
= NULL
;
12185 intel_crtc
= kzalloc(sizeof(*intel_crtc
), GFP_KERNEL
);
12186 if (intel_crtc
== NULL
)
12189 crtc_state
= kzalloc(sizeof(*crtc_state
), GFP_KERNEL
);
12192 intel_crtc_set_state(intel_crtc
, crtc_state
);
12194 primary
= intel_primary_plane_create(dev
, pipe
);
12198 cursor
= intel_cursor_plane_create(dev
, pipe
);
12202 ret
= drm_crtc_init_with_planes(dev
, &intel_crtc
->base
, primary
,
12203 cursor
, &intel_crtc_funcs
);
12207 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
12208 for (i
= 0; i
< 256; i
++) {
12209 intel_crtc
->lut_r
[i
] = i
;
12210 intel_crtc
->lut_g
[i
] = i
;
12211 intel_crtc
->lut_b
[i
] = i
;
12215 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12216 * is hooked to pipe B. Hence we want plane A feeding pipe B.
12218 intel_crtc
->pipe
= pipe
;
12219 intel_crtc
->plane
= pipe
;
12220 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4) {
12221 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12222 intel_crtc
->plane
= !pipe
;
12225 intel_crtc
->cursor_base
= ~0;
12226 intel_crtc
->cursor_cntl
= ~0;
12227 intel_crtc
->cursor_size
= ~0;
12229 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
12230 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
12231 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
12232 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
12234 INIT_WORK(&intel_crtc
->mmio_flip
.work
, intel_mmio_flip_work_func
);
12236 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
12238 WARN_ON(drm_crtc_index(&intel_crtc
->base
) != intel_crtc
->pipe
);
12243 drm_plane_cleanup(primary
);
12245 drm_plane_cleanup(cursor
);
12250 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
)
12252 struct drm_encoder
*encoder
= connector
->base
.encoder
;
12253 struct drm_device
*dev
= connector
->base
.dev
;
12255 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
12257 if (!encoder
|| WARN_ON(!encoder
->crtc
))
12258 return INVALID_PIPE
;
12260 return to_intel_crtc(encoder
->crtc
)->pipe
;
12263 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
12264 struct drm_file
*file
)
12266 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
12267 struct drm_crtc
*drmmode_crtc
;
12268 struct intel_crtc
*crtc
;
12270 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
12273 drmmode_crtc
= drm_crtc_find(dev
, pipe_from_crtc_id
->crtc_id
);
12275 if (!drmmode_crtc
) {
12276 DRM_ERROR("no such CRTC id\n");
12280 crtc
= to_intel_crtc(drmmode_crtc
);
12281 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
12286 static int intel_encoder_clones(struct intel_encoder
*encoder
)
12288 struct drm_device
*dev
= encoder
->base
.dev
;
12289 struct intel_encoder
*source_encoder
;
12290 int index_mask
= 0;
12293 for_each_intel_encoder(dev
, source_encoder
) {
12294 if (encoders_cloneable(encoder
, source_encoder
))
12295 index_mask
|= (1 << entry
);
12303 static bool has_edp_a(struct drm_device
*dev
)
12305 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12307 if (!IS_MOBILE(dev
))
12310 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
12313 if (IS_GEN5(dev
) && (I915_READ(FUSE_STRAP
) & ILK_eDP_A_DISABLE
))
12319 static bool intel_crt_present(struct drm_device
*dev
)
12321 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12323 if (INTEL_INFO(dev
)->gen
>= 9)
12326 if (IS_HSW_ULT(dev
) || IS_BDW_ULT(dev
))
12329 if (IS_CHERRYVIEW(dev
))
12332 if (IS_VALLEYVIEW(dev
) && !dev_priv
->vbt
.int_crt_support
)
12338 static void intel_setup_outputs(struct drm_device
*dev
)
12340 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12341 struct intel_encoder
*encoder
;
12342 bool dpd_is_edp
= false;
12344 intel_lvds_init(dev
);
12346 if (intel_crt_present(dev
))
12347 intel_crt_init(dev
);
12349 if (HAS_DDI(dev
)) {
12352 /* Haswell uses DDI functions to detect digital outputs */
12353 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
12354 /* DDI A only supports eDP */
12356 intel_ddi_init(dev
, PORT_A
);
12358 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12360 found
= I915_READ(SFUSE_STRAP
);
12362 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
12363 intel_ddi_init(dev
, PORT_B
);
12364 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
12365 intel_ddi_init(dev
, PORT_C
);
12366 if (found
& SFUSE_STRAP_DDID_DETECTED
)
12367 intel_ddi_init(dev
, PORT_D
);
12368 } else if (HAS_PCH_SPLIT(dev
)) {
12370 dpd_is_edp
= intel_dp_is_edp(dev
, PORT_D
);
12372 if (has_edp_a(dev
))
12373 intel_dp_init(dev
, DP_A
, PORT_A
);
12375 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
12376 /* PCH SDVOB multiplex with HDMIB */
12377 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
12379 intel_hdmi_init(dev
, PCH_HDMIB
, PORT_B
);
12380 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
12381 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
12384 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
12385 intel_hdmi_init(dev
, PCH_HDMIC
, PORT_C
);
12387 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
12388 intel_hdmi_init(dev
, PCH_HDMID
, PORT_D
);
12390 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
12391 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
12393 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
12394 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
12395 } else if (IS_VALLEYVIEW(dev
)) {
12397 * The DP_DETECTED bit is the latched state of the DDC
12398 * SDA pin at boot. However since eDP doesn't require DDC
12399 * (no way to plug in a DP->HDMI dongle) the DDC pins for
12400 * eDP ports may have been muxed to an alternate function.
12401 * Thus we can't rely on the DP_DETECTED bit alone to detect
12402 * eDP ports. Consult the VBT as well as DP_DETECTED to
12403 * detect eDP ports.
12405 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIB
) & SDVO_DETECTED
&&
12406 !intel_dp_is_edp(dev
, PORT_B
))
12407 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIB
,
12409 if (I915_READ(VLV_DISPLAY_BASE
+ DP_B
) & DP_DETECTED
||
12410 intel_dp_is_edp(dev
, PORT_B
))
12411 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_B
, PORT_B
);
12413 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIC
) & SDVO_DETECTED
&&
12414 !intel_dp_is_edp(dev
, PORT_C
))
12415 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIC
,
12417 if (I915_READ(VLV_DISPLAY_BASE
+ DP_C
) & DP_DETECTED
||
12418 intel_dp_is_edp(dev
, PORT_C
))
12419 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_C
, PORT_C
);
12421 if (IS_CHERRYVIEW(dev
)) {
12422 if (I915_READ(VLV_DISPLAY_BASE
+ CHV_HDMID
) & SDVO_DETECTED
)
12423 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ CHV_HDMID
,
12425 /* eDP not supported on port D, so don't check VBT */
12426 if (I915_READ(VLV_DISPLAY_BASE
+ DP_D
) & DP_DETECTED
)
12427 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_D
, PORT_D
);
12430 intel_dsi_init(dev
);
12431 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
12432 bool found
= false;
12434 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
12435 DRM_DEBUG_KMS("probing SDVOB\n");
12436 found
= intel_sdvo_init(dev
, GEN3_SDVOB
, true);
12437 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
12438 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12439 intel_hdmi_init(dev
, GEN4_HDMIB
, PORT_B
);
12442 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
))
12443 intel_dp_init(dev
, DP_B
, PORT_B
);
12446 /* Before G4X SDVOC doesn't have its own detect register */
12448 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
12449 DRM_DEBUG_KMS("probing SDVOC\n");
12450 found
= intel_sdvo_init(dev
, GEN3_SDVOC
, false);
12453 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
12455 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
12456 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12457 intel_hdmi_init(dev
, GEN4_HDMIC
, PORT_C
);
12459 if (SUPPORTS_INTEGRATED_DP(dev
))
12460 intel_dp_init(dev
, DP_C
, PORT_C
);
12463 if (SUPPORTS_INTEGRATED_DP(dev
) &&
12464 (I915_READ(DP_D
) & DP_DETECTED
))
12465 intel_dp_init(dev
, DP_D
, PORT_D
);
12466 } else if (IS_GEN2(dev
))
12467 intel_dvo_init(dev
);
12469 if (SUPPORTS_TV(dev
))
12470 intel_tv_init(dev
);
12472 intel_psr_init(dev
);
12474 for_each_intel_encoder(dev
, encoder
) {
12475 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
12476 encoder
->base
.possible_clones
=
12477 intel_encoder_clones(encoder
);
12480 intel_init_pch_refclk(dev
);
12482 drm_helper_move_panel_connectors_to_head(dev
);
12485 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
12487 struct drm_device
*dev
= fb
->dev
;
12488 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
12490 drm_framebuffer_cleanup(fb
);
12491 mutex_lock(&dev
->struct_mutex
);
12492 WARN_ON(!intel_fb
->obj
->framebuffer_references
--);
12493 drm_gem_object_unreference(&intel_fb
->obj
->base
);
12494 mutex_unlock(&dev
->struct_mutex
);
12498 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
12499 struct drm_file
*file
,
12500 unsigned int *handle
)
12502 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
12503 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
12505 return drm_gem_handle_create(file
, &obj
->base
, handle
);
12508 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
12509 .destroy
= intel_user_framebuffer_destroy
,
12510 .create_handle
= intel_user_framebuffer_create_handle
,
12513 static int intel_framebuffer_init(struct drm_device
*dev
,
12514 struct intel_framebuffer
*intel_fb
,
12515 struct drm_mode_fb_cmd2
*mode_cmd
,
12516 struct drm_i915_gem_object
*obj
)
12518 int aligned_height
;
12522 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
12524 if (obj
->tiling_mode
== I915_TILING_Y
) {
12525 DRM_DEBUG("hardware does not support tiling Y\n");
12529 if (mode_cmd
->pitches
[0] & 63) {
12530 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12531 mode_cmd
->pitches
[0]);
12535 if (INTEL_INFO(dev
)->gen
>= 5 && !IS_VALLEYVIEW(dev
)) {
12536 pitch_limit
= 32*1024;
12537 } else if (INTEL_INFO(dev
)->gen
>= 4) {
12538 if (obj
->tiling_mode
)
12539 pitch_limit
= 16*1024;
12541 pitch_limit
= 32*1024;
12542 } else if (INTEL_INFO(dev
)->gen
>= 3) {
12543 if (obj
->tiling_mode
)
12544 pitch_limit
= 8*1024;
12546 pitch_limit
= 16*1024;
12548 /* XXX DSPC is limited to 4k tiled */
12549 pitch_limit
= 8*1024;
12551 if (mode_cmd
->pitches
[0] > pitch_limit
) {
12552 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12553 obj
->tiling_mode
? "tiled" : "linear",
12554 mode_cmd
->pitches
[0], pitch_limit
);
12558 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
12559 mode_cmd
->pitches
[0] != obj
->stride
) {
12560 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12561 mode_cmd
->pitches
[0], obj
->stride
);
12565 /* Reject formats not supported by any plane early. */
12566 switch (mode_cmd
->pixel_format
) {
12567 case DRM_FORMAT_C8
:
12568 case DRM_FORMAT_RGB565
:
12569 case DRM_FORMAT_XRGB8888
:
12570 case DRM_FORMAT_ARGB8888
:
12572 case DRM_FORMAT_XRGB1555
:
12573 case DRM_FORMAT_ARGB1555
:
12574 if (INTEL_INFO(dev
)->gen
> 3) {
12575 DRM_DEBUG("unsupported pixel format: %s\n",
12576 drm_get_format_name(mode_cmd
->pixel_format
));
12580 case DRM_FORMAT_XBGR8888
:
12581 case DRM_FORMAT_ABGR8888
:
12582 case DRM_FORMAT_XRGB2101010
:
12583 case DRM_FORMAT_ARGB2101010
:
12584 case DRM_FORMAT_XBGR2101010
:
12585 case DRM_FORMAT_ABGR2101010
:
12586 if (INTEL_INFO(dev
)->gen
< 4) {
12587 DRM_DEBUG("unsupported pixel format: %s\n",
12588 drm_get_format_name(mode_cmd
->pixel_format
));
12592 case DRM_FORMAT_YUYV
:
12593 case DRM_FORMAT_UYVY
:
12594 case DRM_FORMAT_YVYU
:
12595 case DRM_FORMAT_VYUY
:
12596 if (INTEL_INFO(dev
)->gen
< 5) {
12597 DRM_DEBUG("unsupported pixel format: %s\n",
12598 drm_get_format_name(mode_cmd
->pixel_format
));
12603 DRM_DEBUG("unsupported pixel format: %s\n",
12604 drm_get_format_name(mode_cmd
->pixel_format
));
12608 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12609 if (mode_cmd
->offsets
[0] != 0)
12612 aligned_height
= intel_align_height(dev
, mode_cmd
->height
,
12614 /* FIXME drm helper for size checks (especially planar formats)? */
12615 if (obj
->base
.size
< aligned_height
* mode_cmd
->pitches
[0])
12618 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
12619 intel_fb
->obj
= obj
;
12620 intel_fb
->obj
->framebuffer_references
++;
12622 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
12624 DRM_ERROR("framebuffer init failed %d\n", ret
);
12631 static struct drm_framebuffer
*
12632 intel_user_framebuffer_create(struct drm_device
*dev
,
12633 struct drm_file
*filp
,
12634 struct drm_mode_fb_cmd2
*mode_cmd
)
12636 struct drm_i915_gem_object
*obj
;
12638 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
12639 mode_cmd
->handles
[0]));
12640 if (&obj
->base
== NULL
)
12641 return ERR_PTR(-ENOENT
);
12643 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
12646 #ifndef CONFIG_DRM_I915_FBDEV
12647 static inline void intel_fbdev_output_poll_changed(struct drm_device
*dev
)
12652 static const struct drm_mode_config_funcs intel_mode_funcs
= {
12653 .fb_create
= intel_user_framebuffer_create
,
12654 .output_poll_changed
= intel_fbdev_output_poll_changed
,
12657 /* Set up chip specific display functions */
12658 static void intel_init_display(struct drm_device
*dev
)
12660 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12662 if (HAS_PCH_SPLIT(dev
) || IS_G4X(dev
))
12663 dev_priv
->display
.find_dpll
= g4x_find_best_dpll
;
12664 else if (IS_CHERRYVIEW(dev
))
12665 dev_priv
->display
.find_dpll
= chv_find_best_dpll
;
12666 else if (IS_VALLEYVIEW(dev
))
12667 dev_priv
->display
.find_dpll
= vlv_find_best_dpll
;
12668 else if (IS_PINEVIEW(dev
))
12669 dev_priv
->display
.find_dpll
= pnv_find_best_dpll
;
12671 dev_priv
->display
.find_dpll
= i9xx_find_best_dpll
;
12673 if (HAS_DDI(dev
)) {
12674 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
12675 dev_priv
->display
.get_plane_config
= ironlake_get_plane_config
;
12676 dev_priv
->display
.crtc_compute_clock
=
12677 haswell_crtc_compute_clock
;
12678 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
12679 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
12680 dev_priv
->display
.off
= ironlake_crtc_off
;
12681 if (INTEL_INFO(dev
)->gen
>= 9)
12682 dev_priv
->display
.update_primary_plane
=
12683 skylake_update_primary_plane
;
12685 dev_priv
->display
.update_primary_plane
=
12686 ironlake_update_primary_plane
;
12687 } else if (HAS_PCH_SPLIT(dev
)) {
12688 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
12689 dev_priv
->display
.get_plane_config
= ironlake_get_plane_config
;
12690 dev_priv
->display
.crtc_compute_clock
=
12691 ironlake_crtc_compute_clock
;
12692 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
12693 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
12694 dev_priv
->display
.off
= ironlake_crtc_off
;
12695 dev_priv
->display
.update_primary_plane
=
12696 ironlake_update_primary_plane
;
12697 } else if (IS_VALLEYVIEW(dev
)) {
12698 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
12699 dev_priv
->display
.get_plane_config
= i9xx_get_plane_config
;
12700 dev_priv
->display
.crtc_compute_clock
= i9xx_crtc_compute_clock
;
12701 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
12702 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
12703 dev_priv
->display
.off
= i9xx_crtc_off
;
12704 dev_priv
->display
.update_primary_plane
=
12705 i9xx_update_primary_plane
;
12707 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
12708 dev_priv
->display
.get_plane_config
= i9xx_get_plane_config
;
12709 dev_priv
->display
.crtc_compute_clock
= i9xx_crtc_compute_clock
;
12710 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
12711 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
12712 dev_priv
->display
.off
= i9xx_crtc_off
;
12713 dev_priv
->display
.update_primary_plane
=
12714 i9xx_update_primary_plane
;
12717 /* Returns the core display clock speed */
12718 if (IS_VALLEYVIEW(dev
))
12719 dev_priv
->display
.get_display_clock_speed
=
12720 valleyview_get_display_clock_speed
;
12721 else if (IS_I945G(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
12722 dev_priv
->display
.get_display_clock_speed
=
12723 i945_get_display_clock_speed
;
12724 else if (IS_I915G(dev
))
12725 dev_priv
->display
.get_display_clock_speed
=
12726 i915_get_display_clock_speed
;
12727 else if (IS_I945GM(dev
) || IS_845G(dev
))
12728 dev_priv
->display
.get_display_clock_speed
=
12729 i9xx_misc_get_display_clock_speed
;
12730 else if (IS_PINEVIEW(dev
))
12731 dev_priv
->display
.get_display_clock_speed
=
12732 pnv_get_display_clock_speed
;
12733 else if (IS_I915GM(dev
))
12734 dev_priv
->display
.get_display_clock_speed
=
12735 i915gm_get_display_clock_speed
;
12736 else if (IS_I865G(dev
))
12737 dev_priv
->display
.get_display_clock_speed
=
12738 i865_get_display_clock_speed
;
12739 else if (IS_I85X(dev
))
12740 dev_priv
->display
.get_display_clock_speed
=
12741 i855_get_display_clock_speed
;
12742 else /* 852, 830 */
12743 dev_priv
->display
.get_display_clock_speed
=
12744 i830_get_display_clock_speed
;
12746 if (IS_GEN5(dev
)) {
12747 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
12748 } else if (IS_GEN6(dev
)) {
12749 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
12750 } else if (IS_IVYBRIDGE(dev
)) {
12751 /* FIXME: detect B0+ stepping and use auto training */
12752 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
12753 dev_priv
->display
.modeset_global_resources
=
12754 ivb_modeset_global_resources
;
12755 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
12756 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
12757 } else if (IS_VALLEYVIEW(dev
)) {
12758 dev_priv
->display
.modeset_global_resources
=
12759 valleyview_modeset_global_resources
;
12762 /* Default just returns -ENODEV to indicate unsupported */
12763 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
12765 switch (INTEL_INFO(dev
)->gen
) {
12767 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
12771 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
12776 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
12780 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
12783 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12784 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
12787 dev_priv
->display
.queue_flip
= intel_gen9_queue_flip
;
12791 intel_panel_init_backlight_funcs(dev
);
12793 mutex_init(&dev_priv
->pps_mutex
);
12797 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12798 * resume, or other times. This quirk makes sure that's the case for
12799 * affected systems.
12801 static void quirk_pipea_force(struct drm_device
*dev
)
12803 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12805 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
12806 DRM_INFO("applying pipe a force quirk\n");
12809 static void quirk_pipeb_force(struct drm_device
*dev
)
12811 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12813 dev_priv
->quirks
|= QUIRK_PIPEB_FORCE
;
12814 DRM_INFO("applying pipe b force quirk\n");
12818 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12820 static void quirk_ssc_force_disable(struct drm_device
*dev
)
12822 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12823 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
12824 DRM_INFO("applying lvds SSC disable quirk\n");
12828 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12831 static void quirk_invert_brightness(struct drm_device
*dev
)
12833 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12834 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
12835 DRM_INFO("applying inverted panel brightness quirk\n");
12838 /* Some VBT's incorrectly indicate no backlight is present */
12839 static void quirk_backlight_present(struct drm_device
*dev
)
12841 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12842 dev_priv
->quirks
|= QUIRK_BACKLIGHT_PRESENT
;
12843 DRM_INFO("applying backlight present quirk\n");
12846 struct intel_quirk
{
12848 int subsystem_vendor
;
12849 int subsystem_device
;
12850 void (*hook
)(struct drm_device
*dev
);
12853 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12854 struct intel_dmi_quirk
{
12855 void (*hook
)(struct drm_device
*dev
);
12856 const struct dmi_system_id (*dmi_id_list
)[];
12859 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
12861 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
12865 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
12867 .dmi_id_list
= &(const struct dmi_system_id
[]) {
12869 .callback
= intel_dmi_reverse_brightness
,
12870 .ident
= "NCR Corporation",
12871 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
12872 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
12875 { } /* terminating entry */
12877 .hook
= quirk_invert_brightness
,
12881 static struct intel_quirk intel_quirks
[] = {
12882 /* HP Mini needs pipe A force quirk (LP: #322104) */
12883 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force
},
12885 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12886 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
12888 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12889 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
12891 /* 830 needs to leave pipe A & dpll A up */
12892 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
12894 /* 830 needs to leave pipe B & dpll B up */
12895 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipeb_force
},
12897 /* Lenovo U160 cannot use SSC on LVDS */
12898 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
12900 /* Sony Vaio Y cannot use SSC on LVDS */
12901 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
12903 /* Acer Aspire 5734Z must invert backlight brightness */
12904 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
12906 /* Acer/eMachines G725 */
12907 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness
},
12909 /* Acer/eMachines e725 */
12910 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness
},
12912 /* Acer/Packard Bell NCL20 */
12913 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness
},
12915 /* Acer Aspire 4736Z */
12916 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness
},
12918 /* Acer Aspire 5336 */
12919 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness
},
12921 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12922 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present
},
12924 /* Acer C720 Chromebook (Core i3 4005U) */
12925 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present
},
12927 /* Apple Macbook 2,1 (Core 2 T7400) */
12928 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present
},
12930 /* Toshiba CB35 Chromebook (Celeron 2955U) */
12931 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present
},
12933 /* HP Chromebook 14 (Celeron 2955U) */
12934 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present
},
12937 static void intel_init_quirks(struct drm_device
*dev
)
12939 struct pci_dev
*d
= dev
->pdev
;
12942 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
12943 struct intel_quirk
*q
= &intel_quirks
[i
];
12945 if (d
->device
== q
->device
&&
12946 (d
->subsystem_vendor
== q
->subsystem_vendor
||
12947 q
->subsystem_vendor
== PCI_ANY_ID
) &&
12948 (d
->subsystem_device
== q
->subsystem_device
||
12949 q
->subsystem_device
== PCI_ANY_ID
))
12952 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
12953 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
12954 intel_dmi_quirks
[i
].hook(dev
);
12958 /* Disable the VGA plane that we never use */
12959 static void i915_disable_vga(struct drm_device
*dev
)
12961 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12963 u32 vga_reg
= i915_vgacntrl_reg(dev
);
12965 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12966 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
12967 outb(SR01
, VGA_SR_INDEX
);
12968 sr1
= inb(VGA_SR_DATA
);
12969 outb(sr1
| 1<<5, VGA_SR_DATA
);
12970 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
12973 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
12974 POSTING_READ(vga_reg
);
12977 void intel_modeset_init_hw(struct drm_device
*dev
)
12979 intel_prepare_ddi(dev
);
12981 if (IS_VALLEYVIEW(dev
))
12982 vlv_update_cdclk(dev
);
12984 intel_init_clock_gating(dev
);
12986 intel_enable_gt_powersave(dev
);
12989 void intel_modeset_init(struct drm_device
*dev
)
12991 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12994 struct intel_crtc
*crtc
;
12996 drm_mode_config_init(dev
);
12998 dev
->mode_config
.min_width
= 0;
12999 dev
->mode_config
.min_height
= 0;
13001 dev
->mode_config
.preferred_depth
= 24;
13002 dev
->mode_config
.prefer_shadow
= 1;
13004 dev
->mode_config
.funcs
= &intel_mode_funcs
;
13006 intel_init_quirks(dev
);
13008 intel_init_pm(dev
);
13010 if (INTEL_INFO(dev
)->num_pipes
== 0)
13013 intel_init_display(dev
);
13014 intel_init_audio(dev
);
13016 if (IS_GEN2(dev
)) {
13017 dev
->mode_config
.max_width
= 2048;
13018 dev
->mode_config
.max_height
= 2048;
13019 } else if (IS_GEN3(dev
)) {
13020 dev
->mode_config
.max_width
= 4096;
13021 dev
->mode_config
.max_height
= 4096;
13023 dev
->mode_config
.max_width
= 8192;
13024 dev
->mode_config
.max_height
= 8192;
13027 if (IS_845G(dev
) || IS_I865G(dev
)) {
13028 dev
->mode_config
.cursor_width
= IS_845G(dev
) ? 64 : 512;
13029 dev
->mode_config
.cursor_height
= 1023;
13030 } else if (IS_GEN2(dev
)) {
13031 dev
->mode_config
.cursor_width
= GEN2_CURSOR_WIDTH
;
13032 dev
->mode_config
.cursor_height
= GEN2_CURSOR_HEIGHT
;
13034 dev
->mode_config
.cursor_width
= MAX_CURSOR_WIDTH
;
13035 dev
->mode_config
.cursor_height
= MAX_CURSOR_HEIGHT
;
13038 dev
->mode_config
.fb_base
= dev_priv
->gtt
.mappable_base
;
13040 DRM_DEBUG_KMS("%d display pipe%s available.\n",
13041 INTEL_INFO(dev
)->num_pipes
,
13042 INTEL_INFO(dev
)->num_pipes
> 1 ? "s" : "");
13044 for_each_pipe(dev_priv
, pipe
) {
13045 intel_crtc_init(dev
, pipe
);
13046 for_each_sprite(pipe
, sprite
) {
13047 ret
= intel_plane_init(dev
, pipe
, sprite
);
13049 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
13050 pipe_name(pipe
), sprite_name(pipe
, sprite
), ret
);
13054 intel_init_dpio(dev
);
13056 intel_shared_dpll_init(dev
);
13058 /* Just disable it once at startup */
13059 i915_disable_vga(dev
);
13060 intel_setup_outputs(dev
);
13062 /* Just in case the BIOS is doing something questionable. */
13063 intel_fbc_disable(dev
);
13065 drm_modeset_lock_all(dev
);
13066 intel_modeset_setup_hw_state(dev
, false);
13067 drm_modeset_unlock_all(dev
);
13069 for_each_intel_crtc(dev
, crtc
) {
13074 * Note that reserving the BIOS fb up front prevents us
13075 * from stuffing other stolen allocations like the ring
13076 * on top. This prevents some ugliness at boot time, and
13077 * can even allow for smooth boot transitions if the BIOS
13078 * fb is large enough for the active pipe configuration.
13080 if (dev_priv
->display
.get_plane_config
) {
13081 dev_priv
->display
.get_plane_config(crtc
,
13082 &crtc
->plane_config
);
13084 * If the fb is shared between multiple heads, we'll
13085 * just get the first one.
13087 intel_find_plane_obj(crtc
, &crtc
->plane_config
);
13092 static void intel_enable_pipe_a(struct drm_device
*dev
)
13094 struct intel_connector
*connector
;
13095 struct drm_connector
*crt
= NULL
;
13096 struct intel_load_detect_pipe load_detect_temp
;
13097 struct drm_modeset_acquire_ctx
*ctx
= dev
->mode_config
.acquire_ctx
;
13099 /* We can't just switch on the pipe A, we need to set things up with a
13100 * proper mode and output configuration. As a gross hack, enable pipe A
13101 * by enabling the load detect pipe once. */
13102 list_for_each_entry(connector
,
13103 &dev
->mode_config
.connector_list
,
13105 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
13106 crt
= &connector
->base
;
13114 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
, ctx
))
13115 intel_release_load_detect_pipe(crt
, &load_detect_temp
);
13119 intel_check_plane_mapping(struct intel_crtc
*crtc
)
13121 struct drm_device
*dev
= crtc
->base
.dev
;
13122 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13125 if (INTEL_INFO(dev
)->num_pipes
== 1)
13128 reg
= DSPCNTR(!crtc
->plane
);
13129 val
= I915_READ(reg
);
13131 if ((val
& DISPLAY_PLANE_ENABLE
) &&
13132 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
13138 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
13140 struct drm_device
*dev
= crtc
->base
.dev
;
13141 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13144 /* Clear any frame start delays used for debugging left by the BIOS */
13145 reg
= PIPECONF(crtc
->config
->cpu_transcoder
);
13146 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
13148 /* restore vblank interrupts to correct state */
13149 if (crtc
->active
) {
13150 update_scanline_offset(crtc
);
13151 drm_vblank_on(dev
, crtc
->pipe
);
13153 drm_vblank_off(dev
, crtc
->pipe
);
13155 /* We need to sanitize the plane -> pipe mapping first because this will
13156 * disable the crtc (and hence change the state) if it is wrong. Note
13157 * that gen4+ has a fixed plane -> pipe mapping. */
13158 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
13159 struct intel_connector
*connector
;
13162 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13163 crtc
->base
.base
.id
);
13165 /* Pipe has the wrong plane attached and the plane is active.
13166 * Temporarily change the plane mapping and disable everything
13168 plane
= crtc
->plane
;
13169 crtc
->plane
= !plane
;
13170 crtc
->primary_enabled
= true;
13171 dev_priv
->display
.crtc_disable(&crtc
->base
);
13172 crtc
->plane
= plane
;
13174 /* ... and break all links. */
13175 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
13177 if (connector
->encoder
->base
.crtc
!= &crtc
->base
)
13180 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
13181 connector
->base
.encoder
= NULL
;
13183 /* multiple connectors may have the same encoder:
13184 * handle them and break crtc link separately */
13185 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
13187 if (connector
->encoder
->base
.crtc
== &crtc
->base
) {
13188 connector
->encoder
->base
.crtc
= NULL
;
13189 connector
->encoder
->connectors_active
= false;
13192 WARN_ON(crtc
->active
);
13193 crtc
->base
.enabled
= false;
13196 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
13197 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
13198 /* BIOS forgot to enable pipe A, this mostly happens after
13199 * resume. Force-enable the pipe to fix this, the update_dpms
13200 * call below we restore the pipe to the right state, but leave
13201 * the required bits on. */
13202 intel_enable_pipe_a(dev
);
13205 /* Adjust the state of the output pipe according to whether we
13206 * have active connectors/encoders. */
13207 intel_crtc_update_dpms(&crtc
->base
);
13209 if (crtc
->active
!= crtc
->base
.enabled
) {
13210 struct intel_encoder
*encoder
;
13212 /* This can happen either due to bugs in the get_hw_state
13213 * functions or because the pipe is force-enabled due to the
13215 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13216 crtc
->base
.base
.id
,
13217 crtc
->base
.enabled
? "enabled" : "disabled",
13218 crtc
->active
? "enabled" : "disabled");
13220 crtc
->base
.enabled
= crtc
->active
;
13222 /* Because we only establish the connector -> encoder ->
13223 * crtc links if something is active, this means the
13224 * crtc is now deactivated. Break the links. connector
13225 * -> encoder links are only establish when things are
13226 * actually up, hence no need to break them. */
13227 WARN_ON(crtc
->active
);
13229 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
13230 WARN_ON(encoder
->connectors_active
);
13231 encoder
->base
.crtc
= NULL
;
13235 if (crtc
->active
|| HAS_GMCH_DISPLAY(dev
)) {
13237 * We start out with underrun reporting disabled to avoid races.
13238 * For correct bookkeeping mark this on active crtcs.
13240 * Also on gmch platforms we dont have any hardware bits to
13241 * disable the underrun reporting. Which means we need to start
13242 * out with underrun reporting disabled also on inactive pipes,
13243 * since otherwise we'll complain about the garbage we read when
13244 * e.g. coming up after runtime pm.
13246 * No protection against concurrent access is required - at
13247 * worst a fifo underrun happens which also sets this to false.
13249 crtc
->cpu_fifo_underrun_disabled
= true;
13250 crtc
->pch_fifo_underrun_disabled
= true;
13254 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
13256 struct intel_connector
*connector
;
13257 struct drm_device
*dev
= encoder
->base
.dev
;
13259 /* We need to check both for a crtc link (meaning that the
13260 * encoder is active and trying to read from a pipe) and the
13261 * pipe itself being active. */
13262 bool has_active_crtc
= encoder
->base
.crtc
&&
13263 to_intel_crtc(encoder
->base
.crtc
)->active
;
13265 if (encoder
->connectors_active
&& !has_active_crtc
) {
13266 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13267 encoder
->base
.base
.id
,
13268 encoder
->base
.name
);
13270 /* Connector is active, but has no active pipe. This is
13271 * fallout from our resume register restoring. Disable
13272 * the encoder manually again. */
13273 if (encoder
->base
.crtc
) {
13274 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13275 encoder
->base
.base
.id
,
13276 encoder
->base
.name
);
13277 encoder
->disable(encoder
);
13278 if (encoder
->post_disable
)
13279 encoder
->post_disable(encoder
);
13281 encoder
->base
.crtc
= NULL
;
13282 encoder
->connectors_active
= false;
13284 /* Inconsistent output/port/pipe state happens presumably due to
13285 * a bug in one of the get_hw_state functions. Or someplace else
13286 * in our code, like the register restore mess on resume. Clamp
13287 * things to off as a safer default. */
13288 list_for_each_entry(connector
,
13289 &dev
->mode_config
.connector_list
,
13291 if (connector
->encoder
!= encoder
)
13293 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
13294 connector
->base
.encoder
= NULL
;
13297 /* Enabled encoders without active connectors will be fixed in
13298 * the crtc fixup. */
13301 void i915_redisable_vga_power_on(struct drm_device
*dev
)
13303 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13304 u32 vga_reg
= i915_vgacntrl_reg(dev
);
13306 if (!(I915_READ(vga_reg
) & VGA_DISP_DISABLE
)) {
13307 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13308 i915_disable_vga(dev
);
13312 void i915_redisable_vga(struct drm_device
*dev
)
13314 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13316 /* This function can be called both from intel_modeset_setup_hw_state or
13317 * at a very early point in our resume sequence, where the power well
13318 * structures are not yet restored. Since this function is at a very
13319 * paranoid "someone might have enabled VGA while we were not looking"
13320 * level, just check if the power well is enabled instead of trying to
13321 * follow the "don't touch the power well if we don't need it" policy
13322 * the rest of the driver uses. */
13323 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_VGA
))
13326 i915_redisable_vga_power_on(dev
);
13329 static bool primary_get_hw_state(struct intel_crtc
*crtc
)
13331 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
13336 return I915_READ(DSPCNTR(crtc
->plane
)) & DISPLAY_PLANE_ENABLE
;
13339 static void intel_modeset_readout_hw_state(struct drm_device
*dev
)
13341 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13343 struct intel_crtc
*crtc
;
13344 struct intel_encoder
*encoder
;
13345 struct intel_connector
*connector
;
13348 for_each_intel_crtc(dev
, crtc
) {
13349 memset(crtc
->config
, 0, sizeof(*crtc
->config
));
13351 crtc
->config
->quirks
|= PIPE_CONFIG_QUIRK_INHERITED_MODE
;
13353 crtc
->active
= dev_priv
->display
.get_pipe_config(crtc
,
13356 crtc
->base
.enabled
= crtc
->active
;
13357 crtc
->primary_enabled
= primary_get_hw_state(crtc
);
13359 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13360 crtc
->base
.base
.id
,
13361 crtc
->active
? "enabled" : "disabled");
13364 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
13365 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
13367 pll
->on
= pll
->get_hw_state(dev_priv
, pll
,
13368 &pll
->config
.hw_state
);
13370 pll
->config
.crtc_mask
= 0;
13371 for_each_intel_crtc(dev
, crtc
) {
13372 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
) {
13374 pll
->config
.crtc_mask
|= 1 << crtc
->pipe
;
13378 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
13379 pll
->name
, pll
->config
.crtc_mask
, pll
->on
);
13381 if (pll
->config
.crtc_mask
)
13382 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
13385 for_each_intel_encoder(dev
, encoder
) {
13388 if (encoder
->get_hw_state(encoder
, &pipe
)) {
13389 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
13390 encoder
->base
.crtc
= &crtc
->base
;
13391 encoder
->get_config(encoder
, crtc
->config
);
13393 encoder
->base
.crtc
= NULL
;
13396 encoder
->connectors_active
= false;
13397 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13398 encoder
->base
.base
.id
,
13399 encoder
->base
.name
,
13400 encoder
->base
.crtc
? "enabled" : "disabled",
13404 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
13406 if (connector
->get_hw_state(connector
)) {
13407 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
13408 connector
->encoder
->connectors_active
= true;
13409 connector
->base
.encoder
= &connector
->encoder
->base
;
13411 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
13412 connector
->base
.encoder
= NULL
;
13414 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13415 connector
->base
.base
.id
,
13416 connector
->base
.name
,
13417 connector
->base
.encoder
? "enabled" : "disabled");
13421 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13422 * and i915 state tracking structures. */
13423 void intel_modeset_setup_hw_state(struct drm_device
*dev
,
13424 bool force_restore
)
13426 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13428 struct intel_crtc
*crtc
;
13429 struct intel_encoder
*encoder
;
13432 intel_modeset_readout_hw_state(dev
);
13435 * Now that we have the config, copy it to each CRTC struct
13436 * Note that this could go away if we move to using crtc_config
13437 * checking everywhere.
13439 for_each_intel_crtc(dev
, crtc
) {
13440 if (crtc
->active
&& i915
.fastboot
) {
13441 intel_mode_from_pipe_config(&crtc
->base
.mode
,
13443 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13444 crtc
->base
.base
.id
);
13445 drm_mode_debug_printmodeline(&crtc
->base
.mode
);
13449 /* HW state is read out, now we need to sanitize this mess. */
13450 for_each_intel_encoder(dev
, encoder
) {
13451 intel_sanitize_encoder(encoder
);
13454 for_each_pipe(dev_priv
, pipe
) {
13455 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
13456 intel_sanitize_crtc(crtc
);
13457 intel_dump_pipe_config(crtc
, crtc
->config
,
13458 "[setup_hw_state]");
13461 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
13462 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
13464 if (!pll
->on
|| pll
->active
)
13467 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll
->name
);
13469 pll
->disable(dev_priv
, pll
);
13474 skl_wm_get_hw_state(dev
);
13475 else if (HAS_PCH_SPLIT(dev
))
13476 ilk_wm_get_hw_state(dev
);
13478 if (force_restore
) {
13479 i915_redisable_vga(dev
);
13482 * We need to use raw interfaces for restoring state to avoid
13483 * checking (bogus) intermediate states.
13485 for_each_pipe(dev_priv
, pipe
) {
13486 struct drm_crtc
*crtc
=
13487 dev_priv
->pipe_to_crtc_mapping
[pipe
];
13489 intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
,
13490 crtc
->primary
->fb
);
13493 intel_modeset_update_staged_output_state(dev
);
13496 intel_modeset_check_state(dev
);
13499 void intel_modeset_gem_init(struct drm_device
*dev
)
13501 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13502 struct drm_crtc
*c
;
13503 struct drm_i915_gem_object
*obj
;
13505 mutex_lock(&dev
->struct_mutex
);
13506 intel_init_gt_powersave(dev
);
13507 mutex_unlock(&dev
->struct_mutex
);
13510 * There may be no VBT; and if the BIOS enabled SSC we can
13511 * just keep using it to avoid unnecessary flicker. Whereas if the
13512 * BIOS isn't using it, don't assume it will work even if the VBT
13513 * indicates as much.
13515 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
13516 dev_priv
->vbt
.lvds_use_ssc
= !!(I915_READ(PCH_DREF_CONTROL
) &
13519 intel_modeset_init_hw(dev
);
13521 intel_setup_overlay(dev
);
13524 * Make sure any fbs we allocated at startup are properly
13525 * pinned & fenced. When we do the allocation it's too early
13528 mutex_lock(&dev
->struct_mutex
);
13529 for_each_crtc(dev
, c
) {
13530 obj
= intel_fb_obj(c
->primary
->fb
);
13534 if (intel_pin_and_fence_fb_obj(c
->primary
,
13537 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13538 to_intel_crtc(c
)->pipe
);
13539 drm_framebuffer_unreference(c
->primary
->fb
);
13540 c
->primary
->fb
= NULL
;
13543 mutex_unlock(&dev
->struct_mutex
);
13545 intel_backlight_register(dev
);
13548 void intel_connector_unregister(struct intel_connector
*intel_connector
)
13550 struct drm_connector
*connector
= &intel_connector
->base
;
13552 intel_panel_destroy_backlight(connector
);
13553 drm_connector_unregister(connector
);
13556 void intel_modeset_cleanup(struct drm_device
*dev
)
13558 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13559 struct drm_connector
*connector
;
13561 intel_disable_gt_powersave(dev
);
13563 intel_backlight_unregister(dev
);
13566 * Interrupts and polling as the first thing to avoid creating havoc.
13567 * Too much stuff here (turning of connectors, ...) would
13568 * experience fancy races otherwise.
13570 intel_irq_uninstall(dev_priv
);
13573 * Due to the hpd irq storm handling the hotplug work can re-arm the
13574 * poll handlers. Hence disable polling after hpd handling is shut down.
13576 drm_kms_helper_poll_fini(dev
);
13578 mutex_lock(&dev
->struct_mutex
);
13580 intel_unregister_dsm_handler();
13582 intel_fbc_disable(dev
);
13584 ironlake_teardown_rc6(dev
);
13586 mutex_unlock(&dev
->struct_mutex
);
13588 /* flush any delayed tasks or pending work */
13589 flush_scheduled_work();
13591 /* destroy the backlight and sysfs files before encoders/connectors */
13592 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
13593 struct intel_connector
*intel_connector
;
13595 intel_connector
= to_intel_connector(connector
);
13596 intel_connector
->unregister(intel_connector
);
13599 drm_mode_config_cleanup(dev
);
13601 intel_cleanup_overlay(dev
);
13603 mutex_lock(&dev
->struct_mutex
);
13604 intel_cleanup_gt_powersave(dev
);
13605 mutex_unlock(&dev
->struct_mutex
);
13609 * Return which encoder is currently attached for connector.
13611 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
13613 return &intel_attached_encoder(connector
)->base
;
13616 void intel_connector_attach_encoder(struct intel_connector
*connector
,
13617 struct intel_encoder
*encoder
)
13619 connector
->encoder
= encoder
;
13620 drm_mode_connector_attach_encoder(&connector
->base
,
13625 * set vga decode state - true == enable VGA decode
13627 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
13629 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13630 unsigned reg
= INTEL_INFO(dev
)->gen
>= 6 ? SNB_GMCH_CTRL
: INTEL_GMCH_CTRL
;
13633 if (pci_read_config_word(dev_priv
->bridge_dev
, reg
, &gmch_ctrl
)) {
13634 DRM_ERROR("failed to read control word\n");
13638 if (!!(gmch_ctrl
& INTEL_GMCH_VGA_DISABLE
) == !state
)
13642 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
13644 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
13646 if (pci_write_config_word(dev_priv
->bridge_dev
, reg
, gmch_ctrl
)) {
13647 DRM_ERROR("failed to write control word\n");
13654 struct intel_display_error_state
{
13656 u32 power_well_driver
;
13658 int num_transcoders
;
13660 struct intel_cursor_error_state
{
13665 } cursor
[I915_MAX_PIPES
];
13667 struct intel_pipe_error_state
{
13668 bool power_domain_on
;
13671 } pipe
[I915_MAX_PIPES
];
13673 struct intel_plane_error_state
{
13681 } plane
[I915_MAX_PIPES
];
13683 struct intel_transcoder_error_state
{
13684 bool power_domain_on
;
13685 enum transcoder cpu_transcoder
;
13698 struct intel_display_error_state
*
13699 intel_display_capture_error_state(struct drm_device
*dev
)
13701 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13702 struct intel_display_error_state
*error
;
13703 int transcoders
[] = {
13711 if (INTEL_INFO(dev
)->num_pipes
== 0)
13714 error
= kzalloc(sizeof(*error
), GFP_ATOMIC
);
13718 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
13719 error
->power_well_driver
= I915_READ(HSW_PWR_WELL_DRIVER
);
13721 for_each_pipe(dev_priv
, i
) {
13722 error
->pipe
[i
].power_domain_on
=
13723 __intel_display_power_is_enabled(dev_priv
,
13724 POWER_DOMAIN_PIPE(i
));
13725 if (!error
->pipe
[i
].power_domain_on
)
13728 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
13729 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
13730 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
13732 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
13733 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
13734 if (INTEL_INFO(dev
)->gen
<= 3) {
13735 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
13736 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
13738 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
13739 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
13740 if (INTEL_INFO(dev
)->gen
>= 4) {
13741 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
13742 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
13745 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
13747 if (HAS_GMCH_DISPLAY(dev
))
13748 error
->pipe
[i
].stat
= I915_READ(PIPESTAT(i
));
13751 error
->num_transcoders
= INTEL_INFO(dev
)->num_pipes
;
13752 if (HAS_DDI(dev_priv
->dev
))
13753 error
->num_transcoders
++; /* Account for eDP. */
13755 for (i
= 0; i
< error
->num_transcoders
; i
++) {
13756 enum transcoder cpu_transcoder
= transcoders
[i
];
13758 error
->transcoder
[i
].power_domain_on
=
13759 __intel_display_power_is_enabled(dev_priv
,
13760 POWER_DOMAIN_TRANSCODER(cpu_transcoder
));
13761 if (!error
->transcoder
[i
].power_domain_on
)
13764 error
->transcoder
[i
].cpu_transcoder
= cpu_transcoder
;
13766 error
->transcoder
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
13767 error
->transcoder
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
13768 error
->transcoder
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
13769 error
->transcoder
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
13770 error
->transcoder
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
13771 error
->transcoder
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
13772 error
->transcoder
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
13778 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13781 intel_display_print_error_state(struct drm_i915_error_state_buf
*m
,
13782 struct drm_device
*dev
,
13783 struct intel_display_error_state
*error
)
13785 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13791 err_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev
)->num_pipes
);
13792 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
13793 err_printf(m
, "PWR_WELL_CTL2: %08x\n",
13794 error
->power_well_driver
);
13795 for_each_pipe(dev_priv
, i
) {
13796 err_printf(m
, "Pipe [%d]:\n", i
);
13797 err_printf(m
, " Power: %s\n",
13798 error
->pipe
[i
].power_domain_on
? "on" : "off");
13799 err_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
13800 err_printf(m
, " STAT: %08x\n", error
->pipe
[i
].stat
);
13802 err_printf(m
, "Plane [%d]:\n", i
);
13803 err_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
13804 err_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
13805 if (INTEL_INFO(dev
)->gen
<= 3) {
13806 err_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
13807 err_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
13809 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
13810 err_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
13811 if (INTEL_INFO(dev
)->gen
>= 4) {
13812 err_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
13813 err_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
13816 err_printf(m
, "Cursor [%d]:\n", i
);
13817 err_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
13818 err_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
13819 err_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);
13822 for (i
= 0; i
< error
->num_transcoders
; i
++) {
13823 err_printf(m
, "CPU transcoder: %c\n",
13824 transcoder_name(error
->transcoder
[i
].cpu_transcoder
));
13825 err_printf(m
, " Power: %s\n",
13826 error
->transcoder
[i
].power_domain_on
? "on" : "off");
13827 err_printf(m
, " CONF: %08x\n", error
->transcoder
[i
].conf
);
13828 err_printf(m
, " HTOTAL: %08x\n", error
->transcoder
[i
].htotal
);
13829 err_printf(m
, " HBLANK: %08x\n", error
->transcoder
[i
].hblank
);
13830 err_printf(m
, " HSYNC: %08x\n", error
->transcoder
[i
].hsync
);
13831 err_printf(m
, " VTOTAL: %08x\n", error
->transcoder
[i
].vtotal
);
13832 err_printf(m
, " VBLANK: %08x\n", error
->transcoder
[i
].vblank
);
13833 err_printf(m
, " VSYNC: %08x\n", error
->transcoder
[i
].vsync
);
13837 void intel_modeset_preclose(struct drm_device
*dev
, struct drm_file
*file
)
13839 struct intel_crtc
*crtc
;
13841 for_each_intel_crtc(dev
, crtc
) {
13842 struct intel_unpin_work
*work
;
13844 spin_lock_irq(&dev
->event_lock
);
13846 work
= crtc
->unpin_work
;
13848 if (work
&& work
->event
&&
13849 work
->event
->base
.file_priv
== file
) {
13850 kfree(work
->event
);
13851 work
->event
= NULL
;
13854 spin_unlock_irq(&dev
->event_lock
);