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drm/i915: Move vblank enable earlier and disable later
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_rect.h>
44 #include <linux/dma_remapping.h>
45
46 /* Primary plane formats supported by all gen */
47 #define COMMON_PRIMARY_FORMATS \
48 DRM_FORMAT_C8, \
49 DRM_FORMAT_RGB565, \
50 DRM_FORMAT_XRGB8888, \
51 DRM_FORMAT_ARGB8888
52
53 /* Primary plane formats for gen <= 3 */
54 static const uint32_t intel_primary_formats_gen2[] = {
55 COMMON_PRIMARY_FORMATS,
56 DRM_FORMAT_XRGB1555,
57 DRM_FORMAT_ARGB1555,
58 };
59
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t intel_primary_formats_gen4[] = {
62 COMMON_PRIMARY_FORMATS, \
63 DRM_FORMAT_XBGR8888,
64 DRM_FORMAT_ABGR8888,
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_ARGB2101010,
67 DRM_FORMAT_XBGR2101010,
68 DRM_FORMAT_ABGR2101010,
69 };
70
71 /* Cursor formats */
72 static const uint32_t intel_cursor_formats[] = {
73 DRM_FORMAT_ARGB8888,
74 };
75
76 #define DIV_ROUND_CLOSEST_ULL(ll, d) \
77 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
78
79 static void intel_increase_pllclock(struct drm_device *dev,
80 enum pipe pipe);
81 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
82
83 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
84 struct intel_crtc_config *pipe_config);
85 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
86 struct intel_crtc_config *pipe_config);
87
88 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
89 int x, int y, struct drm_framebuffer *old_fb);
90 static int intel_framebuffer_init(struct drm_device *dev,
91 struct intel_framebuffer *ifb,
92 struct drm_mode_fb_cmd2 *mode_cmd,
93 struct drm_i915_gem_object *obj);
94 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
95 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
96 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
97 struct intel_link_m_n *m_n,
98 struct intel_link_m_n *m2_n2);
99 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
100 static void haswell_set_pipeconf(struct drm_crtc *crtc);
101 static void intel_set_pipe_csc(struct drm_crtc *crtc);
102 static void vlv_prepare_pll(struct intel_crtc *crtc);
103 static void chv_prepare_pll(struct intel_crtc *crtc);
104
105 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
106 {
107 if (!connector->mst_port)
108 return connector->encoder;
109 else
110 return &connector->mst_port->mst_encoders[pipe]->base;
111 }
112
113 typedef struct {
114 int min, max;
115 } intel_range_t;
116
117 typedef struct {
118 int dot_limit;
119 int p2_slow, p2_fast;
120 } intel_p2_t;
121
122 typedef struct intel_limit intel_limit_t;
123 struct intel_limit {
124 intel_range_t dot, vco, n, m, m1, m2, p, p1;
125 intel_p2_t p2;
126 };
127
128 int
129 intel_pch_rawclk(struct drm_device *dev)
130 {
131 struct drm_i915_private *dev_priv = dev->dev_private;
132
133 WARN_ON(!HAS_PCH_SPLIT(dev));
134
135 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
136 }
137
138 static inline u32 /* units of 100MHz */
139 intel_fdi_link_freq(struct drm_device *dev)
140 {
141 if (IS_GEN5(dev)) {
142 struct drm_i915_private *dev_priv = dev->dev_private;
143 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
144 } else
145 return 27;
146 }
147
148 static const intel_limit_t intel_limits_i8xx_dac = {
149 .dot = { .min = 25000, .max = 350000 },
150 .vco = { .min = 908000, .max = 1512000 },
151 .n = { .min = 2, .max = 16 },
152 .m = { .min = 96, .max = 140 },
153 .m1 = { .min = 18, .max = 26 },
154 .m2 = { .min = 6, .max = 16 },
155 .p = { .min = 4, .max = 128 },
156 .p1 = { .min = 2, .max = 33 },
157 .p2 = { .dot_limit = 165000,
158 .p2_slow = 4, .p2_fast = 2 },
159 };
160
161 static const intel_limit_t intel_limits_i8xx_dvo = {
162 .dot = { .min = 25000, .max = 350000 },
163 .vco = { .min = 908000, .max = 1512000 },
164 .n = { .min = 2, .max = 16 },
165 .m = { .min = 96, .max = 140 },
166 .m1 = { .min = 18, .max = 26 },
167 .m2 = { .min = 6, .max = 16 },
168 .p = { .min = 4, .max = 128 },
169 .p1 = { .min = 2, .max = 33 },
170 .p2 = { .dot_limit = 165000,
171 .p2_slow = 4, .p2_fast = 4 },
172 };
173
174 static const intel_limit_t intel_limits_i8xx_lvds = {
175 .dot = { .min = 25000, .max = 350000 },
176 .vco = { .min = 908000, .max = 1512000 },
177 .n = { .min = 2, .max = 16 },
178 .m = { .min = 96, .max = 140 },
179 .m1 = { .min = 18, .max = 26 },
180 .m2 = { .min = 6, .max = 16 },
181 .p = { .min = 4, .max = 128 },
182 .p1 = { .min = 1, .max = 6 },
183 .p2 = { .dot_limit = 165000,
184 .p2_slow = 14, .p2_fast = 7 },
185 };
186
187 static const intel_limit_t intel_limits_i9xx_sdvo = {
188 .dot = { .min = 20000, .max = 400000 },
189 .vco = { .min = 1400000, .max = 2800000 },
190 .n = { .min = 1, .max = 6 },
191 .m = { .min = 70, .max = 120 },
192 .m1 = { .min = 8, .max = 18 },
193 .m2 = { .min = 3, .max = 7 },
194 .p = { .min = 5, .max = 80 },
195 .p1 = { .min = 1, .max = 8 },
196 .p2 = { .dot_limit = 200000,
197 .p2_slow = 10, .p2_fast = 5 },
198 };
199
200 static const intel_limit_t intel_limits_i9xx_lvds = {
201 .dot = { .min = 20000, .max = 400000 },
202 .vco = { .min = 1400000, .max = 2800000 },
203 .n = { .min = 1, .max = 6 },
204 .m = { .min = 70, .max = 120 },
205 .m1 = { .min = 8, .max = 18 },
206 .m2 = { .min = 3, .max = 7 },
207 .p = { .min = 7, .max = 98 },
208 .p1 = { .min = 1, .max = 8 },
209 .p2 = { .dot_limit = 112000,
210 .p2_slow = 14, .p2_fast = 7 },
211 };
212
213
214 static const intel_limit_t intel_limits_g4x_sdvo = {
215 .dot = { .min = 25000, .max = 270000 },
216 .vco = { .min = 1750000, .max = 3500000},
217 .n = { .min = 1, .max = 4 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 10, .max = 30 },
222 .p1 = { .min = 1, .max = 3},
223 .p2 = { .dot_limit = 270000,
224 .p2_slow = 10,
225 .p2_fast = 10
226 },
227 };
228
229 static const intel_limit_t intel_limits_g4x_hdmi = {
230 .dot = { .min = 22000, .max = 400000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 4 },
233 .m = { .min = 104, .max = 138 },
234 .m1 = { .min = 16, .max = 23 },
235 .m2 = { .min = 5, .max = 11 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8},
238 .p2 = { .dot_limit = 165000,
239 .p2_slow = 10, .p2_fast = 5 },
240 };
241
242 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
243 .dot = { .min = 20000, .max = 115000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 14, .p2_fast = 14
253 },
254 };
255
256 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
257 .dot = { .min = 80000, .max = 224000 },
258 .vco = { .min = 1750000, .max = 3500000 },
259 .n = { .min = 1, .max = 3 },
260 .m = { .min = 104, .max = 138 },
261 .m1 = { .min = 17, .max = 23 },
262 .m2 = { .min = 5, .max = 11 },
263 .p = { .min = 14, .max = 42 },
264 .p1 = { .min = 2, .max = 6 },
265 .p2 = { .dot_limit = 0,
266 .p2_slow = 7, .p2_fast = 7
267 },
268 };
269
270 static const intel_limit_t intel_limits_pineview_sdvo = {
271 .dot = { .min = 20000, .max = 400000},
272 .vco = { .min = 1700000, .max = 3500000 },
273 /* Pineview's Ncounter is a ring counter */
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 /* Pineview only has one combined m divider, which we treat as m2. */
277 .m1 = { .min = 0, .max = 0 },
278 .m2 = { .min = 0, .max = 254 },
279 .p = { .min = 5, .max = 80 },
280 .p1 = { .min = 1, .max = 8 },
281 .p2 = { .dot_limit = 200000,
282 .p2_slow = 10, .p2_fast = 5 },
283 };
284
285 static const intel_limit_t intel_limits_pineview_lvds = {
286 .dot = { .min = 20000, .max = 400000 },
287 .vco = { .min = 1700000, .max = 3500000 },
288 .n = { .min = 3, .max = 6 },
289 .m = { .min = 2, .max = 256 },
290 .m1 = { .min = 0, .max = 0 },
291 .m2 = { .min = 0, .max = 254 },
292 .p = { .min = 7, .max = 112 },
293 .p1 = { .min = 1, .max = 8 },
294 .p2 = { .dot_limit = 112000,
295 .p2_slow = 14, .p2_fast = 14 },
296 };
297
298 /* Ironlake / Sandybridge
299 *
300 * We calculate clock using (register_value + 2) for N/M1/M2, so here
301 * the range value for them is (actual_value - 2).
302 */
303 static const intel_limit_t intel_limits_ironlake_dac = {
304 .dot = { .min = 25000, .max = 350000 },
305 .vco = { .min = 1760000, .max = 3510000 },
306 .n = { .min = 1, .max = 5 },
307 .m = { .min = 79, .max = 127 },
308 .m1 = { .min = 12, .max = 22 },
309 .m2 = { .min = 5, .max = 9 },
310 .p = { .min = 5, .max = 80 },
311 .p1 = { .min = 1, .max = 8 },
312 .p2 = { .dot_limit = 225000,
313 .p2_slow = 10, .p2_fast = 5 },
314 };
315
316 static const intel_limit_t intel_limits_ironlake_single_lvds = {
317 .dot = { .min = 25000, .max = 350000 },
318 .vco = { .min = 1760000, .max = 3510000 },
319 .n = { .min = 1, .max = 3 },
320 .m = { .min = 79, .max = 118 },
321 .m1 = { .min = 12, .max = 22 },
322 .m2 = { .min = 5, .max = 9 },
323 .p = { .min = 28, .max = 112 },
324 .p1 = { .min = 2, .max = 8 },
325 .p2 = { .dot_limit = 225000,
326 .p2_slow = 14, .p2_fast = 14 },
327 };
328
329 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
330 .dot = { .min = 25000, .max = 350000 },
331 .vco = { .min = 1760000, .max = 3510000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 79, .max = 127 },
334 .m1 = { .min = 12, .max = 22 },
335 .m2 = { .min = 5, .max = 9 },
336 .p = { .min = 14, .max = 56 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 225000,
339 .p2_slow = 7, .p2_fast = 7 },
340 };
341
342 /* LVDS 100mhz refclk limits. */
343 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
344 .dot = { .min = 25000, .max = 350000 },
345 .vco = { .min = 1760000, .max = 3510000 },
346 .n = { .min = 1, .max = 2 },
347 .m = { .min = 79, .max = 126 },
348 .m1 = { .min = 12, .max = 22 },
349 .m2 = { .min = 5, .max = 9 },
350 .p = { .min = 28, .max = 112 },
351 .p1 = { .min = 2, .max = 8 },
352 .p2 = { .dot_limit = 225000,
353 .p2_slow = 14, .p2_fast = 14 },
354 };
355
356 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
357 .dot = { .min = 25000, .max = 350000 },
358 .vco = { .min = 1760000, .max = 3510000 },
359 .n = { .min = 1, .max = 3 },
360 .m = { .min = 79, .max = 126 },
361 .m1 = { .min = 12, .max = 22 },
362 .m2 = { .min = 5, .max = 9 },
363 .p = { .min = 14, .max = 42 },
364 .p1 = { .min = 2, .max = 6 },
365 .p2 = { .dot_limit = 225000,
366 .p2_slow = 7, .p2_fast = 7 },
367 };
368
369 static const intel_limit_t intel_limits_vlv = {
370 /*
371 * These are the data rate limits (measured in fast clocks)
372 * since those are the strictest limits we have. The fast
373 * clock and actual rate limits are more relaxed, so checking
374 * them would make no difference.
375 */
376 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m1 = { .min = 2, .max = 3 },
380 .m2 = { .min = 11, .max = 156 },
381 .p1 = { .min = 2, .max = 3 },
382 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
383 };
384
385 static const intel_limit_t intel_limits_chv = {
386 /*
387 * These are the data rate limits (measured in fast clocks)
388 * since those are the strictest limits we have. The fast
389 * clock and actual rate limits are more relaxed, so checking
390 * them would make no difference.
391 */
392 .dot = { .min = 25000 * 5, .max = 540000 * 5},
393 .vco = { .min = 4860000, .max = 6700000 },
394 .n = { .min = 1, .max = 1 },
395 .m1 = { .min = 2, .max = 2 },
396 .m2 = { .min = 24 << 22, .max = 175 << 22 },
397 .p1 = { .min = 2, .max = 4 },
398 .p2 = { .p2_slow = 1, .p2_fast = 14 },
399 };
400
401 static void vlv_clock(int refclk, intel_clock_t *clock)
402 {
403 clock->m = clock->m1 * clock->m2;
404 clock->p = clock->p1 * clock->p2;
405 if (WARN_ON(clock->n == 0 || clock->p == 0))
406 return;
407 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
408 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
409 }
410
411 /**
412 * Returns whether any output on the specified pipe is of the specified type
413 */
414 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
415 {
416 struct drm_device *dev = crtc->dev;
417 struct intel_encoder *encoder;
418
419 for_each_encoder_on_crtc(dev, crtc, encoder)
420 if (encoder->type == type)
421 return true;
422
423 return false;
424 }
425
426 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
427 int refclk)
428 {
429 struct drm_device *dev = crtc->dev;
430 const intel_limit_t *limit;
431
432 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
433 if (intel_is_dual_link_lvds(dev)) {
434 if (refclk == 100000)
435 limit = &intel_limits_ironlake_dual_lvds_100m;
436 else
437 limit = &intel_limits_ironlake_dual_lvds;
438 } else {
439 if (refclk == 100000)
440 limit = &intel_limits_ironlake_single_lvds_100m;
441 else
442 limit = &intel_limits_ironlake_single_lvds;
443 }
444 } else
445 limit = &intel_limits_ironlake_dac;
446
447 return limit;
448 }
449
450 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
451 {
452 struct drm_device *dev = crtc->dev;
453 const intel_limit_t *limit;
454
455 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
456 if (intel_is_dual_link_lvds(dev))
457 limit = &intel_limits_g4x_dual_channel_lvds;
458 else
459 limit = &intel_limits_g4x_single_channel_lvds;
460 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
461 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
462 limit = &intel_limits_g4x_hdmi;
463 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
464 limit = &intel_limits_g4x_sdvo;
465 } else /* The option is for other outputs */
466 limit = &intel_limits_i9xx_sdvo;
467
468 return limit;
469 }
470
471 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
472 {
473 struct drm_device *dev = crtc->dev;
474 const intel_limit_t *limit;
475
476 if (HAS_PCH_SPLIT(dev))
477 limit = intel_ironlake_limit(crtc, refclk);
478 else if (IS_G4X(dev)) {
479 limit = intel_g4x_limit(crtc);
480 } else if (IS_PINEVIEW(dev)) {
481 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
482 limit = &intel_limits_pineview_lvds;
483 else
484 limit = &intel_limits_pineview_sdvo;
485 } else if (IS_CHERRYVIEW(dev)) {
486 limit = &intel_limits_chv;
487 } else if (IS_VALLEYVIEW(dev)) {
488 limit = &intel_limits_vlv;
489 } else if (!IS_GEN2(dev)) {
490 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
491 limit = &intel_limits_i9xx_lvds;
492 else
493 limit = &intel_limits_i9xx_sdvo;
494 } else {
495 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
496 limit = &intel_limits_i8xx_lvds;
497 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
498 limit = &intel_limits_i8xx_dvo;
499 else
500 limit = &intel_limits_i8xx_dac;
501 }
502 return limit;
503 }
504
505 /* m1 is reserved as 0 in Pineview, n is a ring counter */
506 static void pineview_clock(int refclk, intel_clock_t *clock)
507 {
508 clock->m = clock->m2 + 2;
509 clock->p = clock->p1 * clock->p2;
510 if (WARN_ON(clock->n == 0 || clock->p == 0))
511 return;
512 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
513 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
514 }
515
516 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
517 {
518 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
519 }
520
521 static void i9xx_clock(int refclk, intel_clock_t *clock)
522 {
523 clock->m = i9xx_dpll_compute_m(clock);
524 clock->p = clock->p1 * clock->p2;
525 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
526 return;
527 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
528 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
529 }
530
531 static void chv_clock(int refclk, intel_clock_t *clock)
532 {
533 clock->m = clock->m1 * clock->m2;
534 clock->p = clock->p1 * clock->p2;
535 if (WARN_ON(clock->n == 0 || clock->p == 0))
536 return;
537 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
538 clock->n << 22);
539 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
540 }
541
542 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
543 /**
544 * Returns whether the given set of divisors are valid for a given refclk with
545 * the given connectors.
546 */
547
548 static bool intel_PLL_is_valid(struct drm_device *dev,
549 const intel_limit_t *limit,
550 const intel_clock_t *clock)
551 {
552 if (clock->n < limit->n.min || limit->n.max < clock->n)
553 INTELPllInvalid("n out of range\n");
554 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
555 INTELPllInvalid("p1 out of range\n");
556 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
557 INTELPllInvalid("m2 out of range\n");
558 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
559 INTELPllInvalid("m1 out of range\n");
560
561 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
562 if (clock->m1 <= clock->m2)
563 INTELPllInvalid("m1 <= m2\n");
564
565 if (!IS_VALLEYVIEW(dev)) {
566 if (clock->p < limit->p.min || limit->p.max < clock->p)
567 INTELPllInvalid("p out of range\n");
568 if (clock->m < limit->m.min || limit->m.max < clock->m)
569 INTELPllInvalid("m out of range\n");
570 }
571
572 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
573 INTELPllInvalid("vco out of range\n");
574 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
575 * connector, etc., rather than just a single range.
576 */
577 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
578 INTELPllInvalid("dot out of range\n");
579
580 return true;
581 }
582
583 static bool
584 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
585 int target, int refclk, intel_clock_t *match_clock,
586 intel_clock_t *best_clock)
587 {
588 struct drm_device *dev = crtc->dev;
589 intel_clock_t clock;
590 int err = target;
591
592 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
593 /*
594 * For LVDS just rely on its current settings for dual-channel.
595 * We haven't figured out how to reliably set up different
596 * single/dual channel state, if we even can.
597 */
598 if (intel_is_dual_link_lvds(dev))
599 clock.p2 = limit->p2.p2_fast;
600 else
601 clock.p2 = limit->p2.p2_slow;
602 } else {
603 if (target < limit->p2.dot_limit)
604 clock.p2 = limit->p2.p2_slow;
605 else
606 clock.p2 = limit->p2.p2_fast;
607 }
608
609 memset(best_clock, 0, sizeof(*best_clock));
610
611 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
612 clock.m1++) {
613 for (clock.m2 = limit->m2.min;
614 clock.m2 <= limit->m2.max; clock.m2++) {
615 if (clock.m2 >= clock.m1)
616 break;
617 for (clock.n = limit->n.min;
618 clock.n <= limit->n.max; clock.n++) {
619 for (clock.p1 = limit->p1.min;
620 clock.p1 <= limit->p1.max; clock.p1++) {
621 int this_err;
622
623 i9xx_clock(refclk, &clock);
624 if (!intel_PLL_is_valid(dev, limit,
625 &clock))
626 continue;
627 if (match_clock &&
628 clock.p != match_clock->p)
629 continue;
630
631 this_err = abs(clock.dot - target);
632 if (this_err < err) {
633 *best_clock = clock;
634 err = this_err;
635 }
636 }
637 }
638 }
639 }
640
641 return (err != target);
642 }
643
644 static bool
645 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
646 int target, int refclk, intel_clock_t *match_clock,
647 intel_clock_t *best_clock)
648 {
649 struct drm_device *dev = crtc->dev;
650 intel_clock_t clock;
651 int err = target;
652
653 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
654 /*
655 * For LVDS just rely on its current settings for dual-channel.
656 * We haven't figured out how to reliably set up different
657 * single/dual channel state, if we even can.
658 */
659 if (intel_is_dual_link_lvds(dev))
660 clock.p2 = limit->p2.p2_fast;
661 else
662 clock.p2 = limit->p2.p2_slow;
663 } else {
664 if (target < limit->p2.dot_limit)
665 clock.p2 = limit->p2.p2_slow;
666 else
667 clock.p2 = limit->p2.p2_fast;
668 }
669
670 memset(best_clock, 0, sizeof(*best_clock));
671
672 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
673 clock.m1++) {
674 for (clock.m2 = limit->m2.min;
675 clock.m2 <= limit->m2.max; clock.m2++) {
676 for (clock.n = limit->n.min;
677 clock.n <= limit->n.max; clock.n++) {
678 for (clock.p1 = limit->p1.min;
679 clock.p1 <= limit->p1.max; clock.p1++) {
680 int this_err;
681
682 pineview_clock(refclk, &clock);
683 if (!intel_PLL_is_valid(dev, limit,
684 &clock))
685 continue;
686 if (match_clock &&
687 clock.p != match_clock->p)
688 continue;
689
690 this_err = abs(clock.dot - target);
691 if (this_err < err) {
692 *best_clock = clock;
693 err = this_err;
694 }
695 }
696 }
697 }
698 }
699
700 return (err != target);
701 }
702
703 static bool
704 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
705 int target, int refclk, intel_clock_t *match_clock,
706 intel_clock_t *best_clock)
707 {
708 struct drm_device *dev = crtc->dev;
709 intel_clock_t clock;
710 int max_n;
711 bool found;
712 /* approximately equals target * 0.00585 */
713 int err_most = (target >> 8) + (target >> 9);
714 found = false;
715
716 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
717 if (intel_is_dual_link_lvds(dev))
718 clock.p2 = limit->p2.p2_fast;
719 else
720 clock.p2 = limit->p2.p2_slow;
721 } else {
722 if (target < limit->p2.dot_limit)
723 clock.p2 = limit->p2.p2_slow;
724 else
725 clock.p2 = limit->p2.p2_fast;
726 }
727
728 memset(best_clock, 0, sizeof(*best_clock));
729 max_n = limit->n.max;
730 /* based on hardware requirement, prefer smaller n to precision */
731 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
732 /* based on hardware requirement, prefere larger m1,m2 */
733 for (clock.m1 = limit->m1.max;
734 clock.m1 >= limit->m1.min; clock.m1--) {
735 for (clock.m2 = limit->m2.max;
736 clock.m2 >= limit->m2.min; clock.m2--) {
737 for (clock.p1 = limit->p1.max;
738 clock.p1 >= limit->p1.min; clock.p1--) {
739 int this_err;
740
741 i9xx_clock(refclk, &clock);
742 if (!intel_PLL_is_valid(dev, limit,
743 &clock))
744 continue;
745
746 this_err = abs(clock.dot - target);
747 if (this_err < err_most) {
748 *best_clock = clock;
749 err_most = this_err;
750 max_n = clock.n;
751 found = true;
752 }
753 }
754 }
755 }
756 }
757 return found;
758 }
759
760 static bool
761 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
762 int target, int refclk, intel_clock_t *match_clock,
763 intel_clock_t *best_clock)
764 {
765 struct drm_device *dev = crtc->dev;
766 intel_clock_t clock;
767 unsigned int bestppm = 1000000;
768 /* min update 19.2 MHz */
769 int max_n = min(limit->n.max, refclk / 19200);
770 bool found = false;
771
772 target *= 5; /* fast clock */
773
774 memset(best_clock, 0, sizeof(*best_clock));
775
776 /* based on hardware requirement, prefer smaller n to precision */
777 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
778 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
779 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
780 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
781 clock.p = clock.p1 * clock.p2;
782 /* based on hardware requirement, prefer bigger m1,m2 values */
783 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
784 unsigned int ppm, diff;
785
786 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
787 refclk * clock.m1);
788
789 vlv_clock(refclk, &clock);
790
791 if (!intel_PLL_is_valid(dev, limit,
792 &clock))
793 continue;
794
795 diff = abs(clock.dot - target);
796 ppm = div_u64(1000000ULL * diff, target);
797
798 if (ppm < 100 && clock.p > best_clock->p) {
799 bestppm = 0;
800 *best_clock = clock;
801 found = true;
802 }
803
804 if (bestppm >= 10 && ppm < bestppm - 10) {
805 bestppm = ppm;
806 *best_clock = clock;
807 found = true;
808 }
809 }
810 }
811 }
812 }
813
814 return found;
815 }
816
817 static bool
818 chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
819 int target, int refclk, intel_clock_t *match_clock,
820 intel_clock_t *best_clock)
821 {
822 struct drm_device *dev = crtc->dev;
823 intel_clock_t clock;
824 uint64_t m2;
825 int found = false;
826
827 memset(best_clock, 0, sizeof(*best_clock));
828
829 /*
830 * Based on hardware doc, the n always set to 1, and m1 always
831 * set to 2. If requires to support 200Mhz refclk, we need to
832 * revisit this because n may not 1 anymore.
833 */
834 clock.n = 1, clock.m1 = 2;
835 target *= 5; /* fast clock */
836
837 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
838 for (clock.p2 = limit->p2.p2_fast;
839 clock.p2 >= limit->p2.p2_slow;
840 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
841
842 clock.p = clock.p1 * clock.p2;
843
844 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
845 clock.n) << 22, refclk * clock.m1);
846
847 if (m2 > INT_MAX/clock.m1)
848 continue;
849
850 clock.m2 = m2;
851
852 chv_clock(refclk, &clock);
853
854 if (!intel_PLL_is_valid(dev, limit, &clock))
855 continue;
856
857 /* based on hardware requirement, prefer bigger p
858 */
859 if (clock.p > best_clock->p) {
860 *best_clock = clock;
861 found = true;
862 }
863 }
864 }
865
866 return found;
867 }
868
869 bool intel_crtc_active(struct drm_crtc *crtc)
870 {
871 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
872
873 /* Be paranoid as we can arrive here with only partial
874 * state retrieved from the hardware during setup.
875 *
876 * We can ditch the adjusted_mode.crtc_clock check as soon
877 * as Haswell has gained clock readout/fastboot support.
878 *
879 * We can ditch the crtc->primary->fb check as soon as we can
880 * properly reconstruct framebuffers.
881 */
882 return intel_crtc->active && crtc->primary->fb &&
883 intel_crtc->config.adjusted_mode.crtc_clock;
884 }
885
886 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
887 enum pipe pipe)
888 {
889 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
890 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
891
892 return intel_crtc->config.cpu_transcoder;
893 }
894
895 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
896 {
897 struct drm_i915_private *dev_priv = dev->dev_private;
898 u32 reg = PIPEDSL(pipe);
899 u32 line1, line2;
900 u32 line_mask;
901
902 if (IS_GEN2(dev))
903 line_mask = DSL_LINEMASK_GEN2;
904 else
905 line_mask = DSL_LINEMASK_GEN3;
906
907 line1 = I915_READ(reg) & line_mask;
908 mdelay(5);
909 line2 = I915_READ(reg) & line_mask;
910
911 return line1 == line2;
912 }
913
914 /*
915 * intel_wait_for_pipe_off - wait for pipe to turn off
916 * @crtc: crtc whose pipe to wait for
917 *
918 * After disabling a pipe, we can't wait for vblank in the usual way,
919 * spinning on the vblank interrupt status bit, since we won't actually
920 * see an interrupt when the pipe is disabled.
921 *
922 * On Gen4 and above:
923 * wait for the pipe register state bit to turn off
924 *
925 * Otherwise:
926 * wait for the display line value to settle (it usually
927 * ends up stopping at the start of the next frame).
928 *
929 */
930 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
931 {
932 struct drm_device *dev = crtc->base.dev;
933 struct drm_i915_private *dev_priv = dev->dev_private;
934 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
935 enum pipe pipe = crtc->pipe;
936
937 if (INTEL_INFO(dev)->gen >= 4) {
938 int reg = PIPECONF(cpu_transcoder);
939
940 /* Wait for the Pipe State to go off */
941 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
942 100))
943 WARN(1, "pipe_off wait timed out\n");
944 } else {
945 /* Wait for the display line to settle */
946 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
947 WARN(1, "pipe_off wait timed out\n");
948 }
949 }
950
951 /*
952 * ibx_digital_port_connected - is the specified port connected?
953 * @dev_priv: i915 private structure
954 * @port: the port to test
955 *
956 * Returns true if @port is connected, false otherwise.
957 */
958 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
959 struct intel_digital_port *port)
960 {
961 u32 bit;
962
963 if (HAS_PCH_IBX(dev_priv->dev)) {
964 switch (port->port) {
965 case PORT_B:
966 bit = SDE_PORTB_HOTPLUG;
967 break;
968 case PORT_C:
969 bit = SDE_PORTC_HOTPLUG;
970 break;
971 case PORT_D:
972 bit = SDE_PORTD_HOTPLUG;
973 break;
974 default:
975 return true;
976 }
977 } else {
978 switch (port->port) {
979 case PORT_B:
980 bit = SDE_PORTB_HOTPLUG_CPT;
981 break;
982 case PORT_C:
983 bit = SDE_PORTC_HOTPLUG_CPT;
984 break;
985 case PORT_D:
986 bit = SDE_PORTD_HOTPLUG_CPT;
987 break;
988 default:
989 return true;
990 }
991 }
992
993 return I915_READ(SDEISR) & bit;
994 }
995
996 static const char *state_string(bool enabled)
997 {
998 return enabled ? "on" : "off";
999 }
1000
1001 /* Only for pre-ILK configs */
1002 void assert_pll(struct drm_i915_private *dev_priv,
1003 enum pipe pipe, bool state)
1004 {
1005 int reg;
1006 u32 val;
1007 bool cur_state;
1008
1009 reg = DPLL(pipe);
1010 val = I915_READ(reg);
1011 cur_state = !!(val & DPLL_VCO_ENABLE);
1012 WARN(cur_state != state,
1013 "PLL state assertion failure (expected %s, current %s)\n",
1014 state_string(state), state_string(cur_state));
1015 }
1016
1017 /* XXX: the dsi pll is shared between MIPI DSI ports */
1018 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1019 {
1020 u32 val;
1021 bool cur_state;
1022
1023 mutex_lock(&dev_priv->dpio_lock);
1024 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1025 mutex_unlock(&dev_priv->dpio_lock);
1026
1027 cur_state = val & DSI_PLL_VCO_EN;
1028 WARN(cur_state != state,
1029 "DSI PLL state assertion failure (expected %s, current %s)\n",
1030 state_string(state), state_string(cur_state));
1031 }
1032 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1033 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1034
1035 struct intel_shared_dpll *
1036 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1037 {
1038 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1039
1040 if (crtc->config.shared_dpll < 0)
1041 return NULL;
1042
1043 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1044 }
1045
1046 /* For ILK+ */
1047 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1048 struct intel_shared_dpll *pll,
1049 bool state)
1050 {
1051 bool cur_state;
1052 struct intel_dpll_hw_state hw_state;
1053
1054 if (WARN (!pll,
1055 "asserting DPLL %s with no DPLL\n", state_string(state)))
1056 return;
1057
1058 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1059 WARN(cur_state != state,
1060 "%s assertion failure (expected %s, current %s)\n",
1061 pll->name, state_string(state), state_string(cur_state));
1062 }
1063
1064 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1065 enum pipe pipe, bool state)
1066 {
1067 int reg;
1068 u32 val;
1069 bool cur_state;
1070 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1071 pipe);
1072
1073 if (HAS_DDI(dev_priv->dev)) {
1074 /* DDI does not have a specific FDI_TX register */
1075 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1076 val = I915_READ(reg);
1077 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1078 } else {
1079 reg = FDI_TX_CTL(pipe);
1080 val = I915_READ(reg);
1081 cur_state = !!(val & FDI_TX_ENABLE);
1082 }
1083 WARN(cur_state != state,
1084 "FDI TX state assertion failure (expected %s, current %s)\n",
1085 state_string(state), state_string(cur_state));
1086 }
1087 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1088 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1089
1090 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1091 enum pipe pipe, bool state)
1092 {
1093 int reg;
1094 u32 val;
1095 bool cur_state;
1096
1097 reg = FDI_RX_CTL(pipe);
1098 val = I915_READ(reg);
1099 cur_state = !!(val & FDI_RX_ENABLE);
1100 WARN(cur_state != state,
1101 "FDI RX state assertion failure (expected %s, current %s)\n",
1102 state_string(state), state_string(cur_state));
1103 }
1104 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1105 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1106
1107 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1108 enum pipe pipe)
1109 {
1110 int reg;
1111 u32 val;
1112
1113 /* ILK FDI PLL is always enabled */
1114 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1115 return;
1116
1117 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1118 if (HAS_DDI(dev_priv->dev))
1119 return;
1120
1121 reg = FDI_TX_CTL(pipe);
1122 val = I915_READ(reg);
1123 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1124 }
1125
1126 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1127 enum pipe pipe, bool state)
1128 {
1129 int reg;
1130 u32 val;
1131 bool cur_state;
1132
1133 reg = FDI_RX_CTL(pipe);
1134 val = I915_READ(reg);
1135 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1136 WARN(cur_state != state,
1137 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1138 state_string(state), state_string(cur_state));
1139 }
1140
1141 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1142 enum pipe pipe)
1143 {
1144 struct drm_device *dev = dev_priv->dev;
1145 int pp_reg;
1146 u32 val;
1147 enum pipe panel_pipe = PIPE_A;
1148 bool locked = true;
1149
1150 if (WARN_ON(HAS_DDI(dev)))
1151 return;
1152
1153 if (HAS_PCH_SPLIT(dev)) {
1154 u32 port_sel;
1155
1156 pp_reg = PCH_PP_CONTROL;
1157 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1158
1159 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1160 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1161 panel_pipe = PIPE_B;
1162 /* XXX: else fix for eDP */
1163 } else if (IS_VALLEYVIEW(dev)) {
1164 /* presumably write lock depends on pipe, not port select */
1165 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1166 panel_pipe = pipe;
1167 } else {
1168 pp_reg = PP_CONTROL;
1169 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1170 panel_pipe = PIPE_B;
1171 }
1172
1173 val = I915_READ(pp_reg);
1174 if (!(val & PANEL_POWER_ON) ||
1175 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1176 locked = false;
1177
1178 WARN(panel_pipe == pipe && locked,
1179 "panel assertion failure, pipe %c regs locked\n",
1180 pipe_name(pipe));
1181 }
1182
1183 static void assert_cursor(struct drm_i915_private *dev_priv,
1184 enum pipe pipe, bool state)
1185 {
1186 struct drm_device *dev = dev_priv->dev;
1187 bool cur_state;
1188
1189 if (IS_845G(dev) || IS_I865G(dev))
1190 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1191 else
1192 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1193
1194 WARN(cur_state != state,
1195 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1196 pipe_name(pipe), state_string(state), state_string(cur_state));
1197 }
1198 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1199 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1200
1201 void assert_pipe(struct drm_i915_private *dev_priv,
1202 enum pipe pipe, bool state)
1203 {
1204 int reg;
1205 u32 val;
1206 bool cur_state;
1207 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1208 pipe);
1209
1210 /* if we need the pipe quirk it must be always on */
1211 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1212 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1213 state = true;
1214
1215 if (!intel_display_power_enabled(dev_priv,
1216 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1217 cur_state = false;
1218 } else {
1219 reg = PIPECONF(cpu_transcoder);
1220 val = I915_READ(reg);
1221 cur_state = !!(val & PIPECONF_ENABLE);
1222 }
1223
1224 WARN(cur_state != state,
1225 "pipe %c assertion failure (expected %s, current %s)\n",
1226 pipe_name(pipe), state_string(state), state_string(cur_state));
1227 }
1228
1229 static void assert_plane(struct drm_i915_private *dev_priv,
1230 enum plane plane, bool state)
1231 {
1232 int reg;
1233 u32 val;
1234 bool cur_state;
1235
1236 reg = DSPCNTR(plane);
1237 val = I915_READ(reg);
1238 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1239 WARN(cur_state != state,
1240 "plane %c assertion failure (expected %s, current %s)\n",
1241 plane_name(plane), state_string(state), state_string(cur_state));
1242 }
1243
1244 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1245 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1246
1247 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1248 enum pipe pipe)
1249 {
1250 struct drm_device *dev = dev_priv->dev;
1251 int reg, i;
1252 u32 val;
1253 int cur_pipe;
1254
1255 /* Primary planes are fixed to pipes on gen4+ */
1256 if (INTEL_INFO(dev)->gen >= 4) {
1257 reg = DSPCNTR(pipe);
1258 val = I915_READ(reg);
1259 WARN(val & DISPLAY_PLANE_ENABLE,
1260 "plane %c assertion failure, should be disabled but not\n",
1261 plane_name(pipe));
1262 return;
1263 }
1264
1265 /* Need to check both planes against the pipe */
1266 for_each_pipe(dev_priv, i) {
1267 reg = DSPCNTR(i);
1268 val = I915_READ(reg);
1269 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1270 DISPPLANE_SEL_PIPE_SHIFT;
1271 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1272 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1273 plane_name(i), pipe_name(pipe));
1274 }
1275 }
1276
1277 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1278 enum pipe pipe)
1279 {
1280 struct drm_device *dev = dev_priv->dev;
1281 int reg, sprite;
1282 u32 val;
1283
1284 if (IS_VALLEYVIEW(dev)) {
1285 for_each_sprite(pipe, sprite) {
1286 reg = SPCNTR(pipe, sprite);
1287 val = I915_READ(reg);
1288 WARN(val & SP_ENABLE,
1289 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1290 sprite_name(pipe, sprite), pipe_name(pipe));
1291 }
1292 } else if (INTEL_INFO(dev)->gen >= 7) {
1293 reg = SPRCTL(pipe);
1294 val = I915_READ(reg);
1295 WARN(val & SPRITE_ENABLE,
1296 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1297 plane_name(pipe), pipe_name(pipe));
1298 } else if (INTEL_INFO(dev)->gen >= 5) {
1299 reg = DVSCNTR(pipe);
1300 val = I915_READ(reg);
1301 WARN(val & DVS_ENABLE,
1302 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1303 plane_name(pipe), pipe_name(pipe));
1304 }
1305 }
1306
1307 static void assert_vblank_disabled(struct drm_crtc *crtc)
1308 {
1309 if (WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1310 drm_crtc_vblank_put(crtc);
1311 }
1312
1313 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1314 {
1315 u32 val;
1316 bool enabled;
1317
1318 WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1319
1320 val = I915_READ(PCH_DREF_CONTROL);
1321 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1322 DREF_SUPERSPREAD_SOURCE_MASK));
1323 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1324 }
1325
1326 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1327 enum pipe pipe)
1328 {
1329 int reg;
1330 u32 val;
1331 bool enabled;
1332
1333 reg = PCH_TRANSCONF(pipe);
1334 val = I915_READ(reg);
1335 enabled = !!(val & TRANS_ENABLE);
1336 WARN(enabled,
1337 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1338 pipe_name(pipe));
1339 }
1340
1341 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1342 enum pipe pipe, u32 port_sel, u32 val)
1343 {
1344 if ((val & DP_PORT_EN) == 0)
1345 return false;
1346
1347 if (HAS_PCH_CPT(dev_priv->dev)) {
1348 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1349 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1350 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1351 return false;
1352 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1353 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1354 return false;
1355 } else {
1356 if ((val & DP_PIPE_MASK) != (pipe << 30))
1357 return false;
1358 }
1359 return true;
1360 }
1361
1362 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1363 enum pipe pipe, u32 val)
1364 {
1365 if ((val & SDVO_ENABLE) == 0)
1366 return false;
1367
1368 if (HAS_PCH_CPT(dev_priv->dev)) {
1369 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1370 return false;
1371 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1372 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1373 return false;
1374 } else {
1375 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1376 return false;
1377 }
1378 return true;
1379 }
1380
1381 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1382 enum pipe pipe, u32 val)
1383 {
1384 if ((val & LVDS_PORT_EN) == 0)
1385 return false;
1386
1387 if (HAS_PCH_CPT(dev_priv->dev)) {
1388 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1389 return false;
1390 } else {
1391 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1392 return false;
1393 }
1394 return true;
1395 }
1396
1397 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1398 enum pipe pipe, u32 val)
1399 {
1400 if ((val & ADPA_DAC_ENABLE) == 0)
1401 return false;
1402 if (HAS_PCH_CPT(dev_priv->dev)) {
1403 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1404 return false;
1405 } else {
1406 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1407 return false;
1408 }
1409 return true;
1410 }
1411
1412 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1413 enum pipe pipe, int reg, u32 port_sel)
1414 {
1415 u32 val = I915_READ(reg);
1416 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1417 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1418 reg, pipe_name(pipe));
1419
1420 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1421 && (val & DP_PIPEB_SELECT),
1422 "IBX PCH dp port still using transcoder B\n");
1423 }
1424
1425 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1426 enum pipe pipe, int reg)
1427 {
1428 u32 val = I915_READ(reg);
1429 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1430 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1431 reg, pipe_name(pipe));
1432
1433 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1434 && (val & SDVO_PIPE_B_SELECT),
1435 "IBX PCH hdmi port still using transcoder B\n");
1436 }
1437
1438 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1439 enum pipe pipe)
1440 {
1441 int reg;
1442 u32 val;
1443
1444 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1445 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1446 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1447
1448 reg = PCH_ADPA;
1449 val = I915_READ(reg);
1450 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1451 "PCH VGA enabled on transcoder %c, should be disabled\n",
1452 pipe_name(pipe));
1453
1454 reg = PCH_LVDS;
1455 val = I915_READ(reg);
1456 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1457 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1458 pipe_name(pipe));
1459
1460 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1461 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1462 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1463 }
1464
1465 static void intel_init_dpio(struct drm_device *dev)
1466 {
1467 struct drm_i915_private *dev_priv = dev->dev_private;
1468
1469 if (!IS_VALLEYVIEW(dev))
1470 return;
1471
1472 /*
1473 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1474 * CHV x1 PHY (DP/HDMI D)
1475 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1476 */
1477 if (IS_CHERRYVIEW(dev)) {
1478 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1479 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1480 } else {
1481 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1482 }
1483 }
1484
1485 static void vlv_enable_pll(struct intel_crtc *crtc)
1486 {
1487 struct drm_device *dev = crtc->base.dev;
1488 struct drm_i915_private *dev_priv = dev->dev_private;
1489 int reg = DPLL(crtc->pipe);
1490 u32 dpll = crtc->config.dpll_hw_state.dpll;
1491
1492 assert_pipe_disabled(dev_priv, crtc->pipe);
1493
1494 /* No really, not for ILK+ */
1495 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1496
1497 /* PLL is protected by panel, make sure we can write it */
1498 if (IS_MOBILE(dev_priv->dev))
1499 assert_panel_unlocked(dev_priv, crtc->pipe);
1500
1501 I915_WRITE(reg, dpll);
1502 POSTING_READ(reg);
1503 udelay(150);
1504
1505 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1506 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1507
1508 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1509 POSTING_READ(DPLL_MD(crtc->pipe));
1510
1511 /* We do this three times for luck */
1512 I915_WRITE(reg, dpll);
1513 POSTING_READ(reg);
1514 udelay(150); /* wait for warmup */
1515 I915_WRITE(reg, dpll);
1516 POSTING_READ(reg);
1517 udelay(150); /* wait for warmup */
1518 I915_WRITE(reg, dpll);
1519 POSTING_READ(reg);
1520 udelay(150); /* wait for warmup */
1521 }
1522
1523 static void chv_enable_pll(struct intel_crtc *crtc)
1524 {
1525 struct drm_device *dev = crtc->base.dev;
1526 struct drm_i915_private *dev_priv = dev->dev_private;
1527 int pipe = crtc->pipe;
1528 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1529 u32 tmp;
1530
1531 assert_pipe_disabled(dev_priv, crtc->pipe);
1532
1533 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1534
1535 mutex_lock(&dev_priv->dpio_lock);
1536
1537 /* Enable back the 10bit clock to display controller */
1538 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1539 tmp |= DPIO_DCLKP_EN;
1540 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1541
1542 /*
1543 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1544 */
1545 udelay(1);
1546
1547 /* Enable PLL */
1548 I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll);
1549
1550 /* Check PLL is locked */
1551 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1552 DRM_ERROR("PLL %d failed to lock\n", pipe);
1553
1554 /* not sure when this should be written */
1555 I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
1556 POSTING_READ(DPLL_MD(pipe));
1557
1558 mutex_unlock(&dev_priv->dpio_lock);
1559 }
1560
1561 static int intel_num_dvo_pipes(struct drm_device *dev)
1562 {
1563 struct intel_crtc *crtc;
1564 int count = 0;
1565
1566 for_each_intel_crtc(dev, crtc)
1567 count += crtc->active &&
1568 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO);
1569
1570 return count;
1571 }
1572
1573 static void i9xx_enable_pll(struct intel_crtc *crtc)
1574 {
1575 struct drm_device *dev = crtc->base.dev;
1576 struct drm_i915_private *dev_priv = dev->dev_private;
1577 int reg = DPLL(crtc->pipe);
1578 u32 dpll = crtc->config.dpll_hw_state.dpll;
1579
1580 assert_pipe_disabled(dev_priv, crtc->pipe);
1581
1582 /* No really, not for ILK+ */
1583 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1584
1585 /* PLL is protected by panel, make sure we can write it */
1586 if (IS_MOBILE(dev) && !IS_I830(dev))
1587 assert_panel_unlocked(dev_priv, crtc->pipe);
1588
1589 /* Enable DVO 2x clock on both PLLs if necessary */
1590 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1591 /*
1592 * It appears to be important that we don't enable this
1593 * for the current pipe before otherwise configuring the
1594 * PLL. No idea how this should be handled if multiple
1595 * DVO outputs are enabled simultaneosly.
1596 */
1597 dpll |= DPLL_DVO_2X_MODE;
1598 I915_WRITE(DPLL(!crtc->pipe),
1599 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1600 }
1601
1602 /* Wait for the clocks to stabilize. */
1603 POSTING_READ(reg);
1604 udelay(150);
1605
1606 if (INTEL_INFO(dev)->gen >= 4) {
1607 I915_WRITE(DPLL_MD(crtc->pipe),
1608 crtc->config.dpll_hw_state.dpll_md);
1609 } else {
1610 /* The pixel multiplier can only be updated once the
1611 * DPLL is enabled and the clocks are stable.
1612 *
1613 * So write it again.
1614 */
1615 I915_WRITE(reg, dpll);
1616 }
1617
1618 /* We do this three times for luck */
1619 I915_WRITE(reg, dpll);
1620 POSTING_READ(reg);
1621 udelay(150); /* wait for warmup */
1622 I915_WRITE(reg, dpll);
1623 POSTING_READ(reg);
1624 udelay(150); /* wait for warmup */
1625 I915_WRITE(reg, dpll);
1626 POSTING_READ(reg);
1627 udelay(150); /* wait for warmup */
1628 }
1629
1630 /**
1631 * i9xx_disable_pll - disable a PLL
1632 * @dev_priv: i915 private structure
1633 * @pipe: pipe PLL to disable
1634 *
1635 * Disable the PLL for @pipe, making sure the pipe is off first.
1636 *
1637 * Note! This is for pre-ILK only.
1638 */
1639 static void i9xx_disable_pll(struct intel_crtc *crtc)
1640 {
1641 struct drm_device *dev = crtc->base.dev;
1642 struct drm_i915_private *dev_priv = dev->dev_private;
1643 enum pipe pipe = crtc->pipe;
1644
1645 /* Disable DVO 2x clock on both PLLs if necessary */
1646 if (IS_I830(dev) &&
1647 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO) &&
1648 intel_num_dvo_pipes(dev) == 1) {
1649 I915_WRITE(DPLL(PIPE_B),
1650 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1651 I915_WRITE(DPLL(PIPE_A),
1652 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1653 }
1654
1655 /* Don't disable pipe or pipe PLLs if needed */
1656 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1657 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1658 return;
1659
1660 /* Make sure the pipe isn't still relying on us */
1661 assert_pipe_disabled(dev_priv, pipe);
1662
1663 I915_WRITE(DPLL(pipe), 0);
1664 POSTING_READ(DPLL(pipe));
1665 }
1666
1667 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1668 {
1669 u32 val = 0;
1670
1671 /* Make sure the pipe isn't still relying on us */
1672 assert_pipe_disabled(dev_priv, pipe);
1673
1674 /*
1675 * Leave integrated clock source and reference clock enabled for pipe B.
1676 * The latter is needed for VGA hotplug / manual detection.
1677 */
1678 if (pipe == PIPE_B)
1679 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1680 I915_WRITE(DPLL(pipe), val);
1681 POSTING_READ(DPLL(pipe));
1682
1683 }
1684
1685 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1686 {
1687 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1688 u32 val;
1689
1690 /* Make sure the pipe isn't still relying on us */
1691 assert_pipe_disabled(dev_priv, pipe);
1692
1693 /* Set PLL en = 0 */
1694 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1695 if (pipe != PIPE_A)
1696 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1697 I915_WRITE(DPLL(pipe), val);
1698 POSTING_READ(DPLL(pipe));
1699
1700 mutex_lock(&dev_priv->dpio_lock);
1701
1702 /* Disable 10bit clock to display controller */
1703 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1704 val &= ~DPIO_DCLKP_EN;
1705 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1706
1707 /* disable left/right clock distribution */
1708 if (pipe != PIPE_B) {
1709 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1710 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1711 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1712 } else {
1713 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1714 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1715 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1716 }
1717
1718 mutex_unlock(&dev_priv->dpio_lock);
1719 }
1720
1721 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1722 struct intel_digital_port *dport)
1723 {
1724 u32 port_mask;
1725 int dpll_reg;
1726
1727 switch (dport->port) {
1728 case PORT_B:
1729 port_mask = DPLL_PORTB_READY_MASK;
1730 dpll_reg = DPLL(0);
1731 break;
1732 case PORT_C:
1733 port_mask = DPLL_PORTC_READY_MASK;
1734 dpll_reg = DPLL(0);
1735 break;
1736 case PORT_D:
1737 port_mask = DPLL_PORTD_READY_MASK;
1738 dpll_reg = DPIO_PHY_STATUS;
1739 break;
1740 default:
1741 BUG();
1742 }
1743
1744 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1745 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1746 port_name(dport->port), I915_READ(dpll_reg));
1747 }
1748
1749 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1750 {
1751 struct drm_device *dev = crtc->base.dev;
1752 struct drm_i915_private *dev_priv = dev->dev_private;
1753 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1754
1755 if (WARN_ON(pll == NULL))
1756 return;
1757
1758 WARN_ON(!pll->refcount);
1759 if (pll->active == 0) {
1760 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1761 WARN_ON(pll->on);
1762 assert_shared_dpll_disabled(dev_priv, pll);
1763
1764 pll->mode_set(dev_priv, pll);
1765 }
1766 }
1767
1768 /**
1769 * intel_enable_shared_dpll - enable PCH PLL
1770 * @dev_priv: i915 private structure
1771 * @pipe: pipe PLL to enable
1772 *
1773 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1774 * drives the transcoder clock.
1775 */
1776 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1777 {
1778 struct drm_device *dev = crtc->base.dev;
1779 struct drm_i915_private *dev_priv = dev->dev_private;
1780 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1781
1782 if (WARN_ON(pll == NULL))
1783 return;
1784
1785 if (WARN_ON(pll->refcount == 0))
1786 return;
1787
1788 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1789 pll->name, pll->active, pll->on,
1790 crtc->base.base.id);
1791
1792 if (pll->active++) {
1793 WARN_ON(!pll->on);
1794 assert_shared_dpll_enabled(dev_priv, pll);
1795 return;
1796 }
1797 WARN_ON(pll->on);
1798
1799 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1800
1801 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1802 pll->enable(dev_priv, pll);
1803 pll->on = true;
1804 }
1805
1806 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1807 {
1808 struct drm_device *dev = crtc->base.dev;
1809 struct drm_i915_private *dev_priv = dev->dev_private;
1810 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1811
1812 /* PCH only available on ILK+ */
1813 BUG_ON(INTEL_INFO(dev)->gen < 5);
1814 if (WARN_ON(pll == NULL))
1815 return;
1816
1817 if (WARN_ON(pll->refcount == 0))
1818 return;
1819
1820 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1821 pll->name, pll->active, pll->on,
1822 crtc->base.base.id);
1823
1824 if (WARN_ON(pll->active == 0)) {
1825 assert_shared_dpll_disabled(dev_priv, pll);
1826 return;
1827 }
1828
1829 assert_shared_dpll_enabled(dev_priv, pll);
1830 WARN_ON(!pll->on);
1831 if (--pll->active)
1832 return;
1833
1834 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1835 pll->disable(dev_priv, pll);
1836 pll->on = false;
1837
1838 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1839 }
1840
1841 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1842 enum pipe pipe)
1843 {
1844 struct drm_device *dev = dev_priv->dev;
1845 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1846 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1847 uint32_t reg, val, pipeconf_val;
1848
1849 /* PCH only available on ILK+ */
1850 BUG_ON(!HAS_PCH_SPLIT(dev));
1851
1852 /* Make sure PCH DPLL is enabled */
1853 assert_shared_dpll_enabled(dev_priv,
1854 intel_crtc_to_shared_dpll(intel_crtc));
1855
1856 /* FDI must be feeding us bits for PCH ports */
1857 assert_fdi_tx_enabled(dev_priv, pipe);
1858 assert_fdi_rx_enabled(dev_priv, pipe);
1859
1860 if (HAS_PCH_CPT(dev)) {
1861 /* Workaround: Set the timing override bit before enabling the
1862 * pch transcoder. */
1863 reg = TRANS_CHICKEN2(pipe);
1864 val = I915_READ(reg);
1865 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1866 I915_WRITE(reg, val);
1867 }
1868
1869 reg = PCH_TRANSCONF(pipe);
1870 val = I915_READ(reg);
1871 pipeconf_val = I915_READ(PIPECONF(pipe));
1872
1873 if (HAS_PCH_IBX(dev_priv->dev)) {
1874 /*
1875 * make the BPC in transcoder be consistent with
1876 * that in pipeconf reg.
1877 */
1878 val &= ~PIPECONF_BPC_MASK;
1879 val |= pipeconf_val & PIPECONF_BPC_MASK;
1880 }
1881
1882 val &= ~TRANS_INTERLACE_MASK;
1883 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1884 if (HAS_PCH_IBX(dev_priv->dev) &&
1885 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1886 val |= TRANS_LEGACY_INTERLACED_ILK;
1887 else
1888 val |= TRANS_INTERLACED;
1889 else
1890 val |= TRANS_PROGRESSIVE;
1891
1892 I915_WRITE(reg, val | TRANS_ENABLE);
1893 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1894 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1895 }
1896
1897 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1898 enum transcoder cpu_transcoder)
1899 {
1900 u32 val, pipeconf_val;
1901
1902 /* PCH only available on ILK+ */
1903 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1904
1905 /* FDI must be feeding us bits for PCH ports */
1906 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1907 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1908
1909 /* Workaround: set timing override bit. */
1910 val = I915_READ(_TRANSA_CHICKEN2);
1911 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1912 I915_WRITE(_TRANSA_CHICKEN2, val);
1913
1914 val = TRANS_ENABLE;
1915 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1916
1917 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1918 PIPECONF_INTERLACED_ILK)
1919 val |= TRANS_INTERLACED;
1920 else
1921 val |= TRANS_PROGRESSIVE;
1922
1923 I915_WRITE(LPT_TRANSCONF, val);
1924 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1925 DRM_ERROR("Failed to enable PCH transcoder\n");
1926 }
1927
1928 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1929 enum pipe pipe)
1930 {
1931 struct drm_device *dev = dev_priv->dev;
1932 uint32_t reg, val;
1933
1934 /* FDI relies on the transcoder */
1935 assert_fdi_tx_disabled(dev_priv, pipe);
1936 assert_fdi_rx_disabled(dev_priv, pipe);
1937
1938 /* Ports must be off as well */
1939 assert_pch_ports_disabled(dev_priv, pipe);
1940
1941 reg = PCH_TRANSCONF(pipe);
1942 val = I915_READ(reg);
1943 val &= ~TRANS_ENABLE;
1944 I915_WRITE(reg, val);
1945 /* wait for PCH transcoder off, transcoder state */
1946 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1947 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1948
1949 if (!HAS_PCH_IBX(dev)) {
1950 /* Workaround: Clear the timing override chicken bit again. */
1951 reg = TRANS_CHICKEN2(pipe);
1952 val = I915_READ(reg);
1953 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1954 I915_WRITE(reg, val);
1955 }
1956 }
1957
1958 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1959 {
1960 u32 val;
1961
1962 val = I915_READ(LPT_TRANSCONF);
1963 val &= ~TRANS_ENABLE;
1964 I915_WRITE(LPT_TRANSCONF, val);
1965 /* wait for PCH transcoder off, transcoder state */
1966 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1967 DRM_ERROR("Failed to disable PCH transcoder\n");
1968
1969 /* Workaround: clear timing override bit. */
1970 val = I915_READ(_TRANSA_CHICKEN2);
1971 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1972 I915_WRITE(_TRANSA_CHICKEN2, val);
1973 }
1974
1975 /**
1976 * intel_enable_pipe - enable a pipe, asserting requirements
1977 * @crtc: crtc responsible for the pipe
1978 *
1979 * Enable @crtc's pipe, making sure that various hardware specific requirements
1980 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1981 */
1982 static void intel_enable_pipe(struct intel_crtc *crtc)
1983 {
1984 struct drm_device *dev = crtc->base.dev;
1985 struct drm_i915_private *dev_priv = dev->dev_private;
1986 enum pipe pipe = crtc->pipe;
1987 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1988 pipe);
1989 enum pipe pch_transcoder;
1990 int reg;
1991 u32 val;
1992
1993 assert_planes_disabled(dev_priv, pipe);
1994 assert_cursor_disabled(dev_priv, pipe);
1995 assert_sprites_disabled(dev_priv, pipe);
1996
1997 if (HAS_PCH_LPT(dev_priv->dev))
1998 pch_transcoder = TRANSCODER_A;
1999 else
2000 pch_transcoder = pipe;
2001
2002 /*
2003 * A pipe without a PLL won't actually be able to drive bits from
2004 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2005 * need the check.
2006 */
2007 if (!HAS_PCH_SPLIT(dev_priv->dev))
2008 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
2009 assert_dsi_pll_enabled(dev_priv);
2010 else
2011 assert_pll_enabled(dev_priv, pipe);
2012 else {
2013 if (crtc->config.has_pch_encoder) {
2014 /* if driving the PCH, we need FDI enabled */
2015 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2016 assert_fdi_tx_pll_enabled(dev_priv,
2017 (enum pipe) cpu_transcoder);
2018 }
2019 /* FIXME: assert CPU port conditions for SNB+ */
2020 }
2021
2022 reg = PIPECONF(cpu_transcoder);
2023 val = I915_READ(reg);
2024 if (val & PIPECONF_ENABLE) {
2025 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2026 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2027 return;
2028 }
2029
2030 I915_WRITE(reg, val | PIPECONF_ENABLE);
2031 POSTING_READ(reg);
2032 }
2033
2034 /**
2035 * intel_disable_pipe - disable a pipe, asserting requirements
2036 * @crtc: crtc whose pipes is to be disabled
2037 *
2038 * Disable the pipe of @crtc, making sure that various hardware
2039 * specific requirements are met, if applicable, e.g. plane
2040 * disabled, panel fitter off, etc.
2041 *
2042 * Will wait until the pipe has shut down before returning.
2043 */
2044 static void intel_disable_pipe(struct intel_crtc *crtc)
2045 {
2046 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2047 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2048 enum pipe pipe = crtc->pipe;
2049 int reg;
2050 u32 val;
2051
2052 /*
2053 * Make sure planes won't keep trying to pump pixels to us,
2054 * or we might hang the display.
2055 */
2056 assert_planes_disabled(dev_priv, pipe);
2057 assert_cursor_disabled(dev_priv, pipe);
2058 assert_sprites_disabled(dev_priv, pipe);
2059
2060 reg = PIPECONF(cpu_transcoder);
2061 val = I915_READ(reg);
2062 if ((val & PIPECONF_ENABLE) == 0)
2063 return;
2064
2065 /*
2066 * Double wide has implications for planes
2067 * so best keep it disabled when not needed.
2068 */
2069 if (crtc->config.double_wide)
2070 val &= ~PIPECONF_DOUBLE_WIDE;
2071
2072 /* Don't disable pipe or pipe PLLs if needed */
2073 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2074 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2075 val &= ~PIPECONF_ENABLE;
2076
2077 I915_WRITE(reg, val);
2078 if ((val & PIPECONF_ENABLE) == 0)
2079 intel_wait_for_pipe_off(crtc);
2080 }
2081
2082 /*
2083 * Plane regs are double buffered, going from enabled->disabled needs a
2084 * trigger in order to latch. The display address reg provides this.
2085 */
2086 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2087 enum plane plane)
2088 {
2089 struct drm_device *dev = dev_priv->dev;
2090 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2091
2092 I915_WRITE(reg, I915_READ(reg));
2093 POSTING_READ(reg);
2094 }
2095
2096 /**
2097 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2098 * @plane: plane to be enabled
2099 * @crtc: crtc for the plane
2100 *
2101 * Enable @plane on @crtc, making sure that the pipe is running first.
2102 */
2103 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2104 struct drm_crtc *crtc)
2105 {
2106 struct drm_device *dev = plane->dev;
2107 struct drm_i915_private *dev_priv = dev->dev_private;
2108 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2109
2110 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2111 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2112
2113 if (intel_crtc->primary_enabled)
2114 return;
2115
2116 intel_crtc->primary_enabled = true;
2117
2118 dev_priv->display.update_primary_plane(crtc, plane->fb,
2119 crtc->x, crtc->y);
2120
2121 /*
2122 * BDW signals flip done immediately if the plane
2123 * is disabled, even if the plane enable is already
2124 * armed to occur at the next vblank :(
2125 */
2126 if (IS_BROADWELL(dev))
2127 intel_wait_for_vblank(dev, intel_crtc->pipe);
2128 }
2129
2130 /**
2131 * intel_disable_primary_hw_plane - disable the primary hardware plane
2132 * @plane: plane to be disabled
2133 * @crtc: crtc for the plane
2134 *
2135 * Disable @plane on @crtc, making sure that the pipe is running first.
2136 */
2137 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2138 struct drm_crtc *crtc)
2139 {
2140 struct drm_device *dev = plane->dev;
2141 struct drm_i915_private *dev_priv = dev->dev_private;
2142 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2143
2144 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2145
2146 if (!intel_crtc->primary_enabled)
2147 return;
2148
2149 intel_crtc->primary_enabled = false;
2150
2151 dev_priv->display.update_primary_plane(crtc, plane->fb,
2152 crtc->x, crtc->y);
2153 }
2154
2155 static bool need_vtd_wa(struct drm_device *dev)
2156 {
2157 #ifdef CONFIG_INTEL_IOMMU
2158 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2159 return true;
2160 #endif
2161 return false;
2162 }
2163
2164 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2165 {
2166 int tile_height;
2167
2168 tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2169 return ALIGN(height, tile_height);
2170 }
2171
2172 int
2173 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2174 struct drm_i915_gem_object *obj,
2175 struct intel_engine_cs *pipelined)
2176 {
2177 struct drm_i915_private *dev_priv = dev->dev_private;
2178 u32 alignment;
2179 int ret;
2180
2181 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2182
2183 switch (obj->tiling_mode) {
2184 case I915_TILING_NONE:
2185 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2186 alignment = 128 * 1024;
2187 else if (INTEL_INFO(dev)->gen >= 4)
2188 alignment = 4 * 1024;
2189 else
2190 alignment = 64 * 1024;
2191 break;
2192 case I915_TILING_X:
2193 /* pin() will align the object as required by fence */
2194 alignment = 0;
2195 break;
2196 case I915_TILING_Y:
2197 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2198 return -EINVAL;
2199 default:
2200 BUG();
2201 }
2202
2203 /* Note that the w/a also requires 64 PTE of padding following the
2204 * bo. We currently fill all unused PTE with the shadow page and so
2205 * we should always have valid PTE following the scanout preventing
2206 * the VT-d warning.
2207 */
2208 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2209 alignment = 256 * 1024;
2210
2211 /*
2212 * Global gtt pte registers are special registers which actually forward
2213 * writes to a chunk of system memory. Which means that there is no risk
2214 * that the register values disappear as soon as we call
2215 * intel_runtime_pm_put(), so it is correct to wrap only the
2216 * pin/unpin/fence and not more.
2217 */
2218 intel_runtime_pm_get(dev_priv);
2219
2220 dev_priv->mm.interruptible = false;
2221 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2222 if (ret)
2223 goto err_interruptible;
2224
2225 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2226 * fence, whereas 965+ only requires a fence if using
2227 * framebuffer compression. For simplicity, we always install
2228 * a fence as the cost is not that onerous.
2229 */
2230 ret = i915_gem_object_get_fence(obj);
2231 if (ret)
2232 goto err_unpin;
2233
2234 i915_gem_object_pin_fence(obj);
2235
2236 dev_priv->mm.interruptible = true;
2237 intel_runtime_pm_put(dev_priv);
2238 return 0;
2239
2240 err_unpin:
2241 i915_gem_object_unpin_from_display_plane(obj);
2242 err_interruptible:
2243 dev_priv->mm.interruptible = true;
2244 intel_runtime_pm_put(dev_priv);
2245 return ret;
2246 }
2247
2248 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2249 {
2250 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2251
2252 i915_gem_object_unpin_fence(obj);
2253 i915_gem_object_unpin_from_display_plane(obj);
2254 }
2255
2256 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2257 * is assumed to be a power-of-two. */
2258 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2259 unsigned int tiling_mode,
2260 unsigned int cpp,
2261 unsigned int pitch)
2262 {
2263 if (tiling_mode != I915_TILING_NONE) {
2264 unsigned int tile_rows, tiles;
2265
2266 tile_rows = *y / 8;
2267 *y %= 8;
2268
2269 tiles = *x / (512/cpp);
2270 *x %= 512/cpp;
2271
2272 return tile_rows * pitch * 8 + tiles * 4096;
2273 } else {
2274 unsigned int offset;
2275
2276 offset = *y * pitch + *x * cpp;
2277 *y = 0;
2278 *x = (offset & 4095) / cpp;
2279 return offset & -4096;
2280 }
2281 }
2282
2283 int intel_format_to_fourcc(int format)
2284 {
2285 switch (format) {
2286 case DISPPLANE_8BPP:
2287 return DRM_FORMAT_C8;
2288 case DISPPLANE_BGRX555:
2289 return DRM_FORMAT_XRGB1555;
2290 case DISPPLANE_BGRX565:
2291 return DRM_FORMAT_RGB565;
2292 default:
2293 case DISPPLANE_BGRX888:
2294 return DRM_FORMAT_XRGB8888;
2295 case DISPPLANE_RGBX888:
2296 return DRM_FORMAT_XBGR8888;
2297 case DISPPLANE_BGRX101010:
2298 return DRM_FORMAT_XRGB2101010;
2299 case DISPPLANE_RGBX101010:
2300 return DRM_FORMAT_XBGR2101010;
2301 }
2302 }
2303
2304 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2305 struct intel_plane_config *plane_config)
2306 {
2307 struct drm_device *dev = crtc->base.dev;
2308 struct drm_i915_gem_object *obj = NULL;
2309 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2310 u32 base = plane_config->base;
2311
2312 if (plane_config->size == 0)
2313 return false;
2314
2315 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2316 plane_config->size);
2317 if (!obj)
2318 return false;
2319
2320 if (plane_config->tiled) {
2321 obj->tiling_mode = I915_TILING_X;
2322 obj->stride = crtc->base.primary->fb->pitches[0];
2323 }
2324
2325 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2326 mode_cmd.width = crtc->base.primary->fb->width;
2327 mode_cmd.height = crtc->base.primary->fb->height;
2328 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2329
2330 mutex_lock(&dev->struct_mutex);
2331
2332 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2333 &mode_cmd, obj)) {
2334 DRM_DEBUG_KMS("intel fb init failed\n");
2335 goto out_unref_obj;
2336 }
2337
2338 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2339 mutex_unlock(&dev->struct_mutex);
2340
2341 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2342 return true;
2343
2344 out_unref_obj:
2345 drm_gem_object_unreference(&obj->base);
2346 mutex_unlock(&dev->struct_mutex);
2347 return false;
2348 }
2349
2350 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2351 struct intel_plane_config *plane_config)
2352 {
2353 struct drm_device *dev = intel_crtc->base.dev;
2354 struct drm_crtc *c;
2355 struct intel_crtc *i;
2356 struct drm_i915_gem_object *obj;
2357
2358 if (!intel_crtc->base.primary->fb)
2359 return;
2360
2361 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2362 return;
2363
2364 kfree(intel_crtc->base.primary->fb);
2365 intel_crtc->base.primary->fb = NULL;
2366
2367 /*
2368 * Failed to alloc the obj, check to see if we should share
2369 * an fb with another CRTC instead
2370 */
2371 for_each_crtc(dev, c) {
2372 i = to_intel_crtc(c);
2373
2374 if (c == &intel_crtc->base)
2375 continue;
2376
2377 if (!i->active)
2378 continue;
2379
2380 obj = intel_fb_obj(c->primary->fb);
2381 if (obj == NULL)
2382 continue;
2383
2384 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2385 drm_framebuffer_reference(c->primary->fb);
2386 intel_crtc->base.primary->fb = c->primary->fb;
2387 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2388 break;
2389 }
2390 }
2391 }
2392
2393 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2394 struct drm_framebuffer *fb,
2395 int x, int y)
2396 {
2397 struct drm_device *dev = crtc->dev;
2398 struct drm_i915_private *dev_priv = dev->dev_private;
2399 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2400 struct drm_i915_gem_object *obj;
2401 int plane = intel_crtc->plane;
2402 unsigned long linear_offset;
2403 u32 dspcntr;
2404 u32 reg = DSPCNTR(plane);
2405 int pixel_size;
2406
2407 if (!intel_crtc->primary_enabled) {
2408 I915_WRITE(reg, 0);
2409 if (INTEL_INFO(dev)->gen >= 4)
2410 I915_WRITE(DSPSURF(plane), 0);
2411 else
2412 I915_WRITE(DSPADDR(plane), 0);
2413 POSTING_READ(reg);
2414 return;
2415 }
2416
2417 obj = intel_fb_obj(fb);
2418 if (WARN_ON(obj == NULL))
2419 return;
2420
2421 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2422
2423 dspcntr = DISPPLANE_GAMMA_ENABLE;
2424
2425 dspcntr |= DISPLAY_PLANE_ENABLE;
2426
2427 if (INTEL_INFO(dev)->gen < 4) {
2428 if (intel_crtc->pipe == PIPE_B)
2429 dspcntr |= DISPPLANE_SEL_PIPE_B;
2430
2431 /* pipesrc and dspsize control the size that is scaled from,
2432 * which should always be the user's requested size.
2433 */
2434 I915_WRITE(DSPSIZE(plane),
2435 ((intel_crtc->config.pipe_src_h - 1) << 16) |
2436 (intel_crtc->config.pipe_src_w - 1));
2437 I915_WRITE(DSPPOS(plane), 0);
2438 }
2439
2440 switch (fb->pixel_format) {
2441 case DRM_FORMAT_C8:
2442 dspcntr |= DISPPLANE_8BPP;
2443 break;
2444 case DRM_FORMAT_XRGB1555:
2445 case DRM_FORMAT_ARGB1555:
2446 dspcntr |= DISPPLANE_BGRX555;
2447 break;
2448 case DRM_FORMAT_RGB565:
2449 dspcntr |= DISPPLANE_BGRX565;
2450 break;
2451 case DRM_FORMAT_XRGB8888:
2452 case DRM_FORMAT_ARGB8888:
2453 dspcntr |= DISPPLANE_BGRX888;
2454 break;
2455 case DRM_FORMAT_XBGR8888:
2456 case DRM_FORMAT_ABGR8888:
2457 dspcntr |= DISPPLANE_RGBX888;
2458 break;
2459 case DRM_FORMAT_XRGB2101010:
2460 case DRM_FORMAT_ARGB2101010:
2461 dspcntr |= DISPPLANE_BGRX101010;
2462 break;
2463 case DRM_FORMAT_XBGR2101010:
2464 case DRM_FORMAT_ABGR2101010:
2465 dspcntr |= DISPPLANE_RGBX101010;
2466 break;
2467 default:
2468 BUG();
2469 }
2470
2471 if (INTEL_INFO(dev)->gen >= 4 &&
2472 obj->tiling_mode != I915_TILING_NONE)
2473 dspcntr |= DISPPLANE_TILED;
2474
2475 if (IS_G4X(dev))
2476 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2477
2478 linear_offset = y * fb->pitches[0] + x * pixel_size;
2479
2480 if (INTEL_INFO(dev)->gen >= 4) {
2481 intel_crtc->dspaddr_offset =
2482 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2483 pixel_size,
2484 fb->pitches[0]);
2485 linear_offset -= intel_crtc->dspaddr_offset;
2486 } else {
2487 intel_crtc->dspaddr_offset = linear_offset;
2488 }
2489
2490 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2491 dspcntr |= DISPPLANE_ROTATE_180;
2492
2493 x += (intel_crtc->config.pipe_src_w - 1);
2494 y += (intel_crtc->config.pipe_src_h - 1);
2495
2496 /* Finding the last pixel of the last line of the display
2497 data and adding to linear_offset*/
2498 linear_offset +=
2499 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2500 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2501 }
2502
2503 I915_WRITE(reg, dspcntr);
2504
2505 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2506 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2507 fb->pitches[0]);
2508 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2509 if (INTEL_INFO(dev)->gen >= 4) {
2510 I915_WRITE(DSPSURF(plane),
2511 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2512 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2513 I915_WRITE(DSPLINOFF(plane), linear_offset);
2514 } else
2515 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2516 POSTING_READ(reg);
2517 }
2518
2519 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2520 struct drm_framebuffer *fb,
2521 int x, int y)
2522 {
2523 struct drm_device *dev = crtc->dev;
2524 struct drm_i915_private *dev_priv = dev->dev_private;
2525 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2526 struct drm_i915_gem_object *obj;
2527 int plane = intel_crtc->plane;
2528 unsigned long linear_offset;
2529 u32 dspcntr;
2530 u32 reg = DSPCNTR(plane);
2531 int pixel_size;
2532
2533 if (!intel_crtc->primary_enabled) {
2534 I915_WRITE(reg, 0);
2535 I915_WRITE(DSPSURF(plane), 0);
2536 POSTING_READ(reg);
2537 return;
2538 }
2539
2540 obj = intel_fb_obj(fb);
2541 if (WARN_ON(obj == NULL))
2542 return;
2543
2544 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2545
2546 dspcntr = DISPPLANE_GAMMA_ENABLE;
2547
2548 dspcntr |= DISPLAY_PLANE_ENABLE;
2549
2550 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2551 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2552
2553 switch (fb->pixel_format) {
2554 case DRM_FORMAT_C8:
2555 dspcntr |= DISPPLANE_8BPP;
2556 break;
2557 case DRM_FORMAT_RGB565:
2558 dspcntr |= DISPPLANE_BGRX565;
2559 break;
2560 case DRM_FORMAT_XRGB8888:
2561 case DRM_FORMAT_ARGB8888:
2562 dspcntr |= DISPPLANE_BGRX888;
2563 break;
2564 case DRM_FORMAT_XBGR8888:
2565 case DRM_FORMAT_ABGR8888:
2566 dspcntr |= DISPPLANE_RGBX888;
2567 break;
2568 case DRM_FORMAT_XRGB2101010:
2569 case DRM_FORMAT_ARGB2101010:
2570 dspcntr |= DISPPLANE_BGRX101010;
2571 break;
2572 case DRM_FORMAT_XBGR2101010:
2573 case DRM_FORMAT_ABGR2101010:
2574 dspcntr |= DISPPLANE_RGBX101010;
2575 break;
2576 default:
2577 BUG();
2578 }
2579
2580 if (obj->tiling_mode != I915_TILING_NONE)
2581 dspcntr |= DISPPLANE_TILED;
2582
2583 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2584 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2585
2586 linear_offset = y * fb->pitches[0] + x * pixel_size;
2587 intel_crtc->dspaddr_offset =
2588 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2589 pixel_size,
2590 fb->pitches[0]);
2591 linear_offset -= intel_crtc->dspaddr_offset;
2592 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2593 dspcntr |= DISPPLANE_ROTATE_180;
2594
2595 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2596 x += (intel_crtc->config.pipe_src_w - 1);
2597 y += (intel_crtc->config.pipe_src_h - 1);
2598
2599 /* Finding the last pixel of the last line of the display
2600 data and adding to linear_offset*/
2601 linear_offset +=
2602 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2603 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2604 }
2605 }
2606
2607 I915_WRITE(reg, dspcntr);
2608
2609 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2610 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2611 fb->pitches[0]);
2612 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2613 I915_WRITE(DSPSURF(plane),
2614 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2615 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2616 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2617 } else {
2618 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2619 I915_WRITE(DSPLINOFF(plane), linear_offset);
2620 }
2621 POSTING_READ(reg);
2622 }
2623
2624 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2625 static int
2626 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2627 int x, int y, enum mode_set_atomic state)
2628 {
2629 struct drm_device *dev = crtc->dev;
2630 struct drm_i915_private *dev_priv = dev->dev_private;
2631
2632 if (dev_priv->display.disable_fbc)
2633 dev_priv->display.disable_fbc(dev);
2634 intel_increase_pllclock(dev, to_intel_crtc(crtc)->pipe);
2635
2636 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2637
2638 return 0;
2639 }
2640
2641 void intel_display_handle_reset(struct drm_device *dev)
2642 {
2643 struct drm_i915_private *dev_priv = dev->dev_private;
2644 struct drm_crtc *crtc;
2645
2646 /*
2647 * Flips in the rings have been nuked by the reset,
2648 * so complete all pending flips so that user space
2649 * will get its events and not get stuck.
2650 *
2651 * Also update the base address of all primary
2652 * planes to the the last fb to make sure we're
2653 * showing the correct fb after a reset.
2654 *
2655 * Need to make two loops over the crtcs so that we
2656 * don't try to grab a crtc mutex before the
2657 * pending_flip_queue really got woken up.
2658 */
2659
2660 for_each_crtc(dev, crtc) {
2661 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2662 enum plane plane = intel_crtc->plane;
2663
2664 intel_prepare_page_flip(dev, plane);
2665 intel_finish_page_flip_plane(dev, plane);
2666 }
2667
2668 for_each_crtc(dev, crtc) {
2669 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2670
2671 drm_modeset_lock(&crtc->mutex, NULL);
2672 /*
2673 * FIXME: Once we have proper support for primary planes (and
2674 * disabling them without disabling the entire crtc) allow again
2675 * a NULL crtc->primary->fb.
2676 */
2677 if (intel_crtc->active && crtc->primary->fb)
2678 dev_priv->display.update_primary_plane(crtc,
2679 crtc->primary->fb,
2680 crtc->x,
2681 crtc->y);
2682 drm_modeset_unlock(&crtc->mutex);
2683 }
2684 }
2685
2686 static int
2687 intel_finish_fb(struct drm_framebuffer *old_fb)
2688 {
2689 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2690 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2691 bool was_interruptible = dev_priv->mm.interruptible;
2692 int ret;
2693
2694 /* Big Hammer, we also need to ensure that any pending
2695 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2696 * current scanout is retired before unpinning the old
2697 * framebuffer.
2698 *
2699 * This should only fail upon a hung GPU, in which case we
2700 * can safely continue.
2701 */
2702 dev_priv->mm.interruptible = false;
2703 ret = i915_gem_object_finish_gpu(obj);
2704 dev_priv->mm.interruptible = was_interruptible;
2705
2706 return ret;
2707 }
2708
2709 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2710 {
2711 struct drm_device *dev = crtc->dev;
2712 struct drm_i915_private *dev_priv = dev->dev_private;
2713 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2714 unsigned long flags;
2715 bool pending;
2716
2717 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2718 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2719 return false;
2720
2721 spin_lock_irqsave(&dev->event_lock, flags);
2722 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2723 spin_unlock_irqrestore(&dev->event_lock, flags);
2724
2725 return pending;
2726 }
2727
2728 static void intel_update_pipe_size(struct intel_crtc *crtc)
2729 {
2730 struct drm_device *dev = crtc->base.dev;
2731 struct drm_i915_private *dev_priv = dev->dev_private;
2732 const struct drm_display_mode *adjusted_mode;
2733
2734 if (!i915.fastboot)
2735 return;
2736
2737 /*
2738 * Update pipe size and adjust fitter if needed: the reason for this is
2739 * that in compute_mode_changes we check the native mode (not the pfit
2740 * mode) to see if we can flip rather than do a full mode set. In the
2741 * fastboot case, we'll flip, but if we don't update the pipesrc and
2742 * pfit state, we'll end up with a big fb scanned out into the wrong
2743 * sized surface.
2744 *
2745 * To fix this properly, we need to hoist the checks up into
2746 * compute_mode_changes (or above), check the actual pfit state and
2747 * whether the platform allows pfit disable with pipe active, and only
2748 * then update the pipesrc and pfit state, even on the flip path.
2749 */
2750
2751 adjusted_mode = &crtc->config.adjusted_mode;
2752
2753 I915_WRITE(PIPESRC(crtc->pipe),
2754 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2755 (adjusted_mode->crtc_vdisplay - 1));
2756 if (!crtc->config.pch_pfit.enabled &&
2757 (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) ||
2758 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))) {
2759 I915_WRITE(PF_CTL(crtc->pipe), 0);
2760 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
2761 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
2762 }
2763 crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2764 crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2765 }
2766
2767 static int
2768 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2769 struct drm_framebuffer *fb)
2770 {
2771 struct drm_device *dev = crtc->dev;
2772 struct drm_i915_private *dev_priv = dev->dev_private;
2773 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2774 enum pipe pipe = intel_crtc->pipe;
2775 struct drm_framebuffer *old_fb = crtc->primary->fb;
2776 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2777 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
2778 int ret;
2779
2780 if (intel_crtc_has_pending_flip(crtc)) {
2781 DRM_ERROR("pipe is still busy with an old pageflip\n");
2782 return -EBUSY;
2783 }
2784
2785 /* no fb bound */
2786 if (!fb) {
2787 DRM_ERROR("No FB bound\n");
2788 return 0;
2789 }
2790
2791 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2792 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2793 plane_name(intel_crtc->plane),
2794 INTEL_INFO(dev)->num_pipes);
2795 return -EINVAL;
2796 }
2797
2798 mutex_lock(&dev->struct_mutex);
2799 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
2800 if (ret == 0)
2801 i915_gem_track_fb(old_obj, obj,
2802 INTEL_FRONTBUFFER_PRIMARY(pipe));
2803 mutex_unlock(&dev->struct_mutex);
2804 if (ret != 0) {
2805 DRM_ERROR("pin & fence failed\n");
2806 return ret;
2807 }
2808
2809 intel_update_pipe_size(intel_crtc);
2810
2811 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2812
2813 if (intel_crtc->active)
2814 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
2815
2816 crtc->primary->fb = fb;
2817 crtc->x = x;
2818 crtc->y = y;
2819
2820 if (old_fb) {
2821 if (intel_crtc->active && old_fb != fb)
2822 intel_wait_for_vblank(dev, intel_crtc->pipe);
2823 mutex_lock(&dev->struct_mutex);
2824 intel_unpin_fb_obj(old_obj);
2825 mutex_unlock(&dev->struct_mutex);
2826 }
2827
2828 mutex_lock(&dev->struct_mutex);
2829 intel_update_fbc(dev);
2830 mutex_unlock(&dev->struct_mutex);
2831
2832 return 0;
2833 }
2834
2835 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2836 {
2837 struct drm_device *dev = crtc->dev;
2838 struct drm_i915_private *dev_priv = dev->dev_private;
2839 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2840 int pipe = intel_crtc->pipe;
2841 u32 reg, temp;
2842
2843 /* enable normal train */
2844 reg = FDI_TX_CTL(pipe);
2845 temp = I915_READ(reg);
2846 if (IS_IVYBRIDGE(dev)) {
2847 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2848 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2849 } else {
2850 temp &= ~FDI_LINK_TRAIN_NONE;
2851 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2852 }
2853 I915_WRITE(reg, temp);
2854
2855 reg = FDI_RX_CTL(pipe);
2856 temp = I915_READ(reg);
2857 if (HAS_PCH_CPT(dev)) {
2858 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2859 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2860 } else {
2861 temp &= ~FDI_LINK_TRAIN_NONE;
2862 temp |= FDI_LINK_TRAIN_NONE;
2863 }
2864 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2865
2866 /* wait one idle pattern time */
2867 POSTING_READ(reg);
2868 udelay(1000);
2869
2870 /* IVB wants error correction enabled */
2871 if (IS_IVYBRIDGE(dev))
2872 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2873 FDI_FE_ERRC_ENABLE);
2874 }
2875
2876 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2877 {
2878 return crtc->base.enabled && crtc->active &&
2879 crtc->config.has_pch_encoder;
2880 }
2881
2882 static void ivb_modeset_global_resources(struct drm_device *dev)
2883 {
2884 struct drm_i915_private *dev_priv = dev->dev_private;
2885 struct intel_crtc *pipe_B_crtc =
2886 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2887 struct intel_crtc *pipe_C_crtc =
2888 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2889 uint32_t temp;
2890
2891 /*
2892 * When everything is off disable fdi C so that we could enable fdi B
2893 * with all lanes. Note that we don't care about enabled pipes without
2894 * an enabled pch encoder.
2895 */
2896 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2897 !pipe_has_enabled_pch(pipe_C_crtc)) {
2898 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2899 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2900
2901 temp = I915_READ(SOUTH_CHICKEN1);
2902 temp &= ~FDI_BC_BIFURCATION_SELECT;
2903 DRM_DEBUG_KMS("disabling fdi C rx\n");
2904 I915_WRITE(SOUTH_CHICKEN1, temp);
2905 }
2906 }
2907
2908 /* The FDI link training functions for ILK/Ibexpeak. */
2909 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2910 {
2911 struct drm_device *dev = crtc->dev;
2912 struct drm_i915_private *dev_priv = dev->dev_private;
2913 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2914 int pipe = intel_crtc->pipe;
2915 u32 reg, temp, tries;
2916
2917 /* FDI needs bits from pipe first */
2918 assert_pipe_enabled(dev_priv, pipe);
2919
2920 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2921 for train result */
2922 reg = FDI_RX_IMR(pipe);
2923 temp = I915_READ(reg);
2924 temp &= ~FDI_RX_SYMBOL_LOCK;
2925 temp &= ~FDI_RX_BIT_LOCK;
2926 I915_WRITE(reg, temp);
2927 I915_READ(reg);
2928 udelay(150);
2929
2930 /* enable CPU FDI TX and PCH FDI RX */
2931 reg = FDI_TX_CTL(pipe);
2932 temp = I915_READ(reg);
2933 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2934 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2935 temp &= ~FDI_LINK_TRAIN_NONE;
2936 temp |= FDI_LINK_TRAIN_PATTERN_1;
2937 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2938
2939 reg = FDI_RX_CTL(pipe);
2940 temp = I915_READ(reg);
2941 temp &= ~FDI_LINK_TRAIN_NONE;
2942 temp |= FDI_LINK_TRAIN_PATTERN_1;
2943 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2944
2945 POSTING_READ(reg);
2946 udelay(150);
2947
2948 /* Ironlake workaround, enable clock pointer after FDI enable*/
2949 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2950 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2951 FDI_RX_PHASE_SYNC_POINTER_EN);
2952
2953 reg = FDI_RX_IIR(pipe);
2954 for (tries = 0; tries < 5; tries++) {
2955 temp = I915_READ(reg);
2956 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2957
2958 if ((temp & FDI_RX_BIT_LOCK)) {
2959 DRM_DEBUG_KMS("FDI train 1 done.\n");
2960 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2961 break;
2962 }
2963 }
2964 if (tries == 5)
2965 DRM_ERROR("FDI train 1 fail!\n");
2966
2967 /* Train 2 */
2968 reg = FDI_TX_CTL(pipe);
2969 temp = I915_READ(reg);
2970 temp &= ~FDI_LINK_TRAIN_NONE;
2971 temp |= FDI_LINK_TRAIN_PATTERN_2;
2972 I915_WRITE(reg, temp);
2973
2974 reg = FDI_RX_CTL(pipe);
2975 temp = I915_READ(reg);
2976 temp &= ~FDI_LINK_TRAIN_NONE;
2977 temp |= FDI_LINK_TRAIN_PATTERN_2;
2978 I915_WRITE(reg, temp);
2979
2980 POSTING_READ(reg);
2981 udelay(150);
2982
2983 reg = FDI_RX_IIR(pipe);
2984 for (tries = 0; tries < 5; tries++) {
2985 temp = I915_READ(reg);
2986 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2987
2988 if (temp & FDI_RX_SYMBOL_LOCK) {
2989 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2990 DRM_DEBUG_KMS("FDI train 2 done.\n");
2991 break;
2992 }
2993 }
2994 if (tries == 5)
2995 DRM_ERROR("FDI train 2 fail!\n");
2996
2997 DRM_DEBUG_KMS("FDI train done\n");
2998
2999 }
3000
3001 static const int snb_b_fdi_train_param[] = {
3002 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3003 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3004 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3005 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3006 };
3007
3008 /* The FDI link training functions for SNB/Cougarpoint. */
3009 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3010 {
3011 struct drm_device *dev = crtc->dev;
3012 struct drm_i915_private *dev_priv = dev->dev_private;
3013 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3014 int pipe = intel_crtc->pipe;
3015 u32 reg, temp, i, retry;
3016
3017 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3018 for train result */
3019 reg = FDI_RX_IMR(pipe);
3020 temp = I915_READ(reg);
3021 temp &= ~FDI_RX_SYMBOL_LOCK;
3022 temp &= ~FDI_RX_BIT_LOCK;
3023 I915_WRITE(reg, temp);
3024
3025 POSTING_READ(reg);
3026 udelay(150);
3027
3028 /* enable CPU FDI TX and PCH FDI RX */
3029 reg = FDI_TX_CTL(pipe);
3030 temp = I915_READ(reg);
3031 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3032 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3033 temp &= ~FDI_LINK_TRAIN_NONE;
3034 temp |= FDI_LINK_TRAIN_PATTERN_1;
3035 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3036 /* SNB-B */
3037 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3038 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3039
3040 I915_WRITE(FDI_RX_MISC(pipe),
3041 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3042
3043 reg = FDI_RX_CTL(pipe);
3044 temp = I915_READ(reg);
3045 if (HAS_PCH_CPT(dev)) {
3046 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3047 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3048 } else {
3049 temp &= ~FDI_LINK_TRAIN_NONE;
3050 temp |= FDI_LINK_TRAIN_PATTERN_1;
3051 }
3052 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3053
3054 POSTING_READ(reg);
3055 udelay(150);
3056
3057 for (i = 0; i < 4; i++) {
3058 reg = FDI_TX_CTL(pipe);
3059 temp = I915_READ(reg);
3060 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3061 temp |= snb_b_fdi_train_param[i];
3062 I915_WRITE(reg, temp);
3063
3064 POSTING_READ(reg);
3065 udelay(500);
3066
3067 for (retry = 0; retry < 5; retry++) {
3068 reg = FDI_RX_IIR(pipe);
3069 temp = I915_READ(reg);
3070 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3071 if (temp & FDI_RX_BIT_LOCK) {
3072 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3073 DRM_DEBUG_KMS("FDI train 1 done.\n");
3074 break;
3075 }
3076 udelay(50);
3077 }
3078 if (retry < 5)
3079 break;
3080 }
3081 if (i == 4)
3082 DRM_ERROR("FDI train 1 fail!\n");
3083
3084 /* Train 2 */
3085 reg = FDI_TX_CTL(pipe);
3086 temp = I915_READ(reg);
3087 temp &= ~FDI_LINK_TRAIN_NONE;
3088 temp |= FDI_LINK_TRAIN_PATTERN_2;
3089 if (IS_GEN6(dev)) {
3090 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3091 /* SNB-B */
3092 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3093 }
3094 I915_WRITE(reg, temp);
3095
3096 reg = FDI_RX_CTL(pipe);
3097 temp = I915_READ(reg);
3098 if (HAS_PCH_CPT(dev)) {
3099 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3100 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3101 } else {
3102 temp &= ~FDI_LINK_TRAIN_NONE;
3103 temp |= FDI_LINK_TRAIN_PATTERN_2;
3104 }
3105 I915_WRITE(reg, temp);
3106
3107 POSTING_READ(reg);
3108 udelay(150);
3109
3110 for (i = 0; i < 4; i++) {
3111 reg = FDI_TX_CTL(pipe);
3112 temp = I915_READ(reg);
3113 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3114 temp |= snb_b_fdi_train_param[i];
3115 I915_WRITE(reg, temp);
3116
3117 POSTING_READ(reg);
3118 udelay(500);
3119
3120 for (retry = 0; retry < 5; retry++) {
3121 reg = FDI_RX_IIR(pipe);
3122 temp = I915_READ(reg);
3123 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3124 if (temp & FDI_RX_SYMBOL_LOCK) {
3125 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3126 DRM_DEBUG_KMS("FDI train 2 done.\n");
3127 break;
3128 }
3129 udelay(50);
3130 }
3131 if (retry < 5)
3132 break;
3133 }
3134 if (i == 4)
3135 DRM_ERROR("FDI train 2 fail!\n");
3136
3137 DRM_DEBUG_KMS("FDI train done.\n");
3138 }
3139
3140 /* Manual link training for Ivy Bridge A0 parts */
3141 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3142 {
3143 struct drm_device *dev = crtc->dev;
3144 struct drm_i915_private *dev_priv = dev->dev_private;
3145 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3146 int pipe = intel_crtc->pipe;
3147 u32 reg, temp, i, j;
3148
3149 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3150 for train result */
3151 reg = FDI_RX_IMR(pipe);
3152 temp = I915_READ(reg);
3153 temp &= ~FDI_RX_SYMBOL_LOCK;
3154 temp &= ~FDI_RX_BIT_LOCK;
3155 I915_WRITE(reg, temp);
3156
3157 POSTING_READ(reg);
3158 udelay(150);
3159
3160 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3161 I915_READ(FDI_RX_IIR(pipe)));
3162
3163 /* Try each vswing and preemphasis setting twice before moving on */
3164 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3165 /* disable first in case we need to retry */
3166 reg = FDI_TX_CTL(pipe);
3167 temp = I915_READ(reg);
3168 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3169 temp &= ~FDI_TX_ENABLE;
3170 I915_WRITE(reg, temp);
3171
3172 reg = FDI_RX_CTL(pipe);
3173 temp = I915_READ(reg);
3174 temp &= ~FDI_LINK_TRAIN_AUTO;
3175 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3176 temp &= ~FDI_RX_ENABLE;
3177 I915_WRITE(reg, temp);
3178
3179 /* enable CPU FDI TX and PCH FDI RX */
3180 reg = FDI_TX_CTL(pipe);
3181 temp = I915_READ(reg);
3182 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3183 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3184 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3185 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3186 temp |= snb_b_fdi_train_param[j/2];
3187 temp |= FDI_COMPOSITE_SYNC;
3188 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3189
3190 I915_WRITE(FDI_RX_MISC(pipe),
3191 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3192
3193 reg = FDI_RX_CTL(pipe);
3194 temp = I915_READ(reg);
3195 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3196 temp |= FDI_COMPOSITE_SYNC;
3197 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3198
3199 POSTING_READ(reg);
3200 udelay(1); /* should be 0.5us */
3201
3202 for (i = 0; i < 4; i++) {
3203 reg = FDI_RX_IIR(pipe);
3204 temp = I915_READ(reg);
3205 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3206
3207 if (temp & FDI_RX_BIT_LOCK ||
3208 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3209 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3210 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3211 i);
3212 break;
3213 }
3214 udelay(1); /* should be 0.5us */
3215 }
3216 if (i == 4) {
3217 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3218 continue;
3219 }
3220
3221 /* Train 2 */
3222 reg = FDI_TX_CTL(pipe);
3223 temp = I915_READ(reg);
3224 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3225 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3226 I915_WRITE(reg, temp);
3227
3228 reg = FDI_RX_CTL(pipe);
3229 temp = I915_READ(reg);
3230 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3231 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3232 I915_WRITE(reg, temp);
3233
3234 POSTING_READ(reg);
3235 udelay(2); /* should be 1.5us */
3236
3237 for (i = 0; i < 4; i++) {
3238 reg = FDI_RX_IIR(pipe);
3239 temp = I915_READ(reg);
3240 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3241
3242 if (temp & FDI_RX_SYMBOL_LOCK ||
3243 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3244 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3245 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3246 i);
3247 goto train_done;
3248 }
3249 udelay(2); /* should be 1.5us */
3250 }
3251 if (i == 4)
3252 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3253 }
3254
3255 train_done:
3256 DRM_DEBUG_KMS("FDI train done.\n");
3257 }
3258
3259 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3260 {
3261 struct drm_device *dev = intel_crtc->base.dev;
3262 struct drm_i915_private *dev_priv = dev->dev_private;
3263 int pipe = intel_crtc->pipe;
3264 u32 reg, temp;
3265
3266
3267 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3268 reg = FDI_RX_CTL(pipe);
3269 temp = I915_READ(reg);
3270 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3271 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3272 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3273 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3274
3275 POSTING_READ(reg);
3276 udelay(200);
3277
3278 /* Switch from Rawclk to PCDclk */
3279 temp = I915_READ(reg);
3280 I915_WRITE(reg, temp | FDI_PCDCLK);
3281
3282 POSTING_READ(reg);
3283 udelay(200);
3284
3285 /* Enable CPU FDI TX PLL, always on for Ironlake */
3286 reg = FDI_TX_CTL(pipe);
3287 temp = I915_READ(reg);
3288 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3289 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3290
3291 POSTING_READ(reg);
3292 udelay(100);
3293 }
3294 }
3295
3296 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3297 {
3298 struct drm_device *dev = intel_crtc->base.dev;
3299 struct drm_i915_private *dev_priv = dev->dev_private;
3300 int pipe = intel_crtc->pipe;
3301 u32 reg, temp;
3302
3303 /* Switch from PCDclk to Rawclk */
3304 reg = FDI_RX_CTL(pipe);
3305 temp = I915_READ(reg);
3306 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3307
3308 /* Disable CPU FDI TX PLL */
3309 reg = FDI_TX_CTL(pipe);
3310 temp = I915_READ(reg);
3311 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3312
3313 POSTING_READ(reg);
3314 udelay(100);
3315
3316 reg = FDI_RX_CTL(pipe);
3317 temp = I915_READ(reg);
3318 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3319
3320 /* Wait for the clocks to turn off. */
3321 POSTING_READ(reg);
3322 udelay(100);
3323 }
3324
3325 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3326 {
3327 struct drm_device *dev = crtc->dev;
3328 struct drm_i915_private *dev_priv = dev->dev_private;
3329 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3330 int pipe = intel_crtc->pipe;
3331 u32 reg, temp;
3332
3333 /* disable CPU FDI tx and PCH FDI rx */
3334 reg = FDI_TX_CTL(pipe);
3335 temp = I915_READ(reg);
3336 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3337 POSTING_READ(reg);
3338
3339 reg = FDI_RX_CTL(pipe);
3340 temp = I915_READ(reg);
3341 temp &= ~(0x7 << 16);
3342 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3343 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3344
3345 POSTING_READ(reg);
3346 udelay(100);
3347
3348 /* Ironlake workaround, disable clock pointer after downing FDI */
3349 if (HAS_PCH_IBX(dev))
3350 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3351
3352 /* still set train pattern 1 */
3353 reg = FDI_TX_CTL(pipe);
3354 temp = I915_READ(reg);
3355 temp &= ~FDI_LINK_TRAIN_NONE;
3356 temp |= FDI_LINK_TRAIN_PATTERN_1;
3357 I915_WRITE(reg, temp);
3358
3359 reg = FDI_RX_CTL(pipe);
3360 temp = I915_READ(reg);
3361 if (HAS_PCH_CPT(dev)) {
3362 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3363 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3364 } else {
3365 temp &= ~FDI_LINK_TRAIN_NONE;
3366 temp |= FDI_LINK_TRAIN_PATTERN_1;
3367 }
3368 /* BPC in FDI rx is consistent with that in PIPECONF */
3369 temp &= ~(0x07 << 16);
3370 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3371 I915_WRITE(reg, temp);
3372
3373 POSTING_READ(reg);
3374 udelay(100);
3375 }
3376
3377 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3378 {
3379 struct intel_crtc *crtc;
3380
3381 /* Note that we don't need to be called with mode_config.lock here
3382 * as our list of CRTC objects is static for the lifetime of the
3383 * device and so cannot disappear as we iterate. Similarly, we can
3384 * happily treat the predicates as racy, atomic checks as userspace
3385 * cannot claim and pin a new fb without at least acquring the
3386 * struct_mutex and so serialising with us.
3387 */
3388 for_each_intel_crtc(dev, crtc) {
3389 if (atomic_read(&crtc->unpin_work_count) == 0)
3390 continue;
3391
3392 if (crtc->unpin_work)
3393 intel_wait_for_vblank(dev, crtc->pipe);
3394
3395 return true;
3396 }
3397
3398 return false;
3399 }
3400
3401 static void page_flip_completed(struct intel_crtc *intel_crtc)
3402 {
3403 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3404 struct intel_unpin_work *work = intel_crtc->unpin_work;
3405
3406 /* ensure that the unpin work is consistent wrt ->pending. */
3407 smp_rmb();
3408 intel_crtc->unpin_work = NULL;
3409
3410 if (work->event)
3411 drm_send_vblank_event(intel_crtc->base.dev,
3412 intel_crtc->pipe,
3413 work->event);
3414
3415 drm_crtc_vblank_put(&intel_crtc->base);
3416
3417 wake_up_all(&dev_priv->pending_flip_queue);
3418 queue_work(dev_priv->wq, &work->work);
3419
3420 trace_i915_flip_complete(intel_crtc->plane,
3421 work->pending_flip_obj);
3422 }
3423
3424 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3425 {
3426 struct drm_device *dev = crtc->dev;
3427 struct drm_i915_private *dev_priv = dev->dev_private;
3428
3429 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3430 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3431 !intel_crtc_has_pending_flip(crtc),
3432 60*HZ) == 0)) {
3433 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3434 unsigned long flags;
3435
3436 spin_lock_irqsave(&dev->event_lock, flags);
3437 if (intel_crtc->unpin_work) {
3438 WARN_ONCE(1, "Removing stuck page flip\n");
3439 page_flip_completed(intel_crtc);
3440 }
3441 spin_unlock_irqrestore(&dev->event_lock, flags);
3442 }
3443
3444 if (crtc->primary->fb) {
3445 mutex_lock(&dev->struct_mutex);
3446 intel_finish_fb(crtc->primary->fb);
3447 mutex_unlock(&dev->struct_mutex);
3448 }
3449 }
3450
3451 /* Program iCLKIP clock to the desired frequency */
3452 static void lpt_program_iclkip(struct drm_crtc *crtc)
3453 {
3454 struct drm_device *dev = crtc->dev;
3455 struct drm_i915_private *dev_priv = dev->dev_private;
3456 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3457 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3458 u32 temp;
3459
3460 mutex_lock(&dev_priv->dpio_lock);
3461
3462 /* It is necessary to ungate the pixclk gate prior to programming
3463 * the divisors, and gate it back when it is done.
3464 */
3465 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3466
3467 /* Disable SSCCTL */
3468 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3469 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3470 SBI_SSCCTL_DISABLE,
3471 SBI_ICLK);
3472
3473 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3474 if (clock == 20000) {
3475 auxdiv = 1;
3476 divsel = 0x41;
3477 phaseinc = 0x20;
3478 } else {
3479 /* The iCLK virtual clock root frequency is in MHz,
3480 * but the adjusted_mode->crtc_clock in in KHz. To get the
3481 * divisors, it is necessary to divide one by another, so we
3482 * convert the virtual clock precision to KHz here for higher
3483 * precision.
3484 */
3485 u32 iclk_virtual_root_freq = 172800 * 1000;
3486 u32 iclk_pi_range = 64;
3487 u32 desired_divisor, msb_divisor_value, pi_value;
3488
3489 desired_divisor = (iclk_virtual_root_freq / clock);
3490 msb_divisor_value = desired_divisor / iclk_pi_range;
3491 pi_value = desired_divisor % iclk_pi_range;
3492
3493 auxdiv = 0;
3494 divsel = msb_divisor_value - 2;
3495 phaseinc = pi_value;
3496 }
3497
3498 /* This should not happen with any sane values */
3499 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3500 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3501 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3502 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3503
3504 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3505 clock,
3506 auxdiv,
3507 divsel,
3508 phasedir,
3509 phaseinc);
3510
3511 /* Program SSCDIVINTPHASE6 */
3512 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3513 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3514 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3515 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3516 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3517 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3518 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3519 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3520
3521 /* Program SSCAUXDIV */
3522 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3523 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3524 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3525 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3526
3527 /* Enable modulator and associated divider */
3528 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3529 temp &= ~SBI_SSCCTL_DISABLE;
3530 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3531
3532 /* Wait for initialization time */
3533 udelay(24);
3534
3535 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3536
3537 mutex_unlock(&dev_priv->dpio_lock);
3538 }
3539
3540 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3541 enum pipe pch_transcoder)
3542 {
3543 struct drm_device *dev = crtc->base.dev;
3544 struct drm_i915_private *dev_priv = dev->dev_private;
3545 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3546
3547 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3548 I915_READ(HTOTAL(cpu_transcoder)));
3549 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3550 I915_READ(HBLANK(cpu_transcoder)));
3551 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3552 I915_READ(HSYNC(cpu_transcoder)));
3553
3554 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3555 I915_READ(VTOTAL(cpu_transcoder)));
3556 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3557 I915_READ(VBLANK(cpu_transcoder)));
3558 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3559 I915_READ(VSYNC(cpu_transcoder)));
3560 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3561 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3562 }
3563
3564 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3565 {
3566 struct drm_i915_private *dev_priv = dev->dev_private;
3567 uint32_t temp;
3568
3569 temp = I915_READ(SOUTH_CHICKEN1);
3570 if (temp & FDI_BC_BIFURCATION_SELECT)
3571 return;
3572
3573 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3574 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3575
3576 temp |= FDI_BC_BIFURCATION_SELECT;
3577 DRM_DEBUG_KMS("enabling fdi C rx\n");
3578 I915_WRITE(SOUTH_CHICKEN1, temp);
3579 POSTING_READ(SOUTH_CHICKEN1);
3580 }
3581
3582 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3583 {
3584 struct drm_device *dev = intel_crtc->base.dev;
3585 struct drm_i915_private *dev_priv = dev->dev_private;
3586
3587 switch (intel_crtc->pipe) {
3588 case PIPE_A:
3589 break;
3590 case PIPE_B:
3591 if (intel_crtc->config.fdi_lanes > 2)
3592 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3593 else
3594 cpt_enable_fdi_bc_bifurcation(dev);
3595
3596 break;
3597 case PIPE_C:
3598 cpt_enable_fdi_bc_bifurcation(dev);
3599
3600 break;
3601 default:
3602 BUG();
3603 }
3604 }
3605
3606 /*
3607 * Enable PCH resources required for PCH ports:
3608 * - PCH PLLs
3609 * - FDI training & RX/TX
3610 * - update transcoder timings
3611 * - DP transcoding bits
3612 * - transcoder
3613 */
3614 static void ironlake_pch_enable(struct drm_crtc *crtc)
3615 {
3616 struct drm_device *dev = crtc->dev;
3617 struct drm_i915_private *dev_priv = dev->dev_private;
3618 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3619 int pipe = intel_crtc->pipe;
3620 u32 reg, temp;
3621
3622 assert_pch_transcoder_disabled(dev_priv, pipe);
3623
3624 if (IS_IVYBRIDGE(dev))
3625 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3626
3627 /* Write the TU size bits before fdi link training, so that error
3628 * detection works. */
3629 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3630 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3631
3632 /* For PCH output, training FDI link */
3633 dev_priv->display.fdi_link_train(crtc);
3634
3635 /* We need to program the right clock selection before writing the pixel
3636 * mutliplier into the DPLL. */
3637 if (HAS_PCH_CPT(dev)) {
3638 u32 sel;
3639
3640 temp = I915_READ(PCH_DPLL_SEL);
3641 temp |= TRANS_DPLL_ENABLE(pipe);
3642 sel = TRANS_DPLLB_SEL(pipe);
3643 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3644 temp |= sel;
3645 else
3646 temp &= ~sel;
3647 I915_WRITE(PCH_DPLL_SEL, temp);
3648 }
3649
3650 /* XXX: pch pll's can be enabled any time before we enable the PCH
3651 * transcoder, and we actually should do this to not upset any PCH
3652 * transcoder that already use the clock when we share it.
3653 *
3654 * Note that enable_shared_dpll tries to do the right thing, but
3655 * get_shared_dpll unconditionally resets the pll - we need that to have
3656 * the right LVDS enable sequence. */
3657 intel_enable_shared_dpll(intel_crtc);
3658
3659 /* set transcoder timing, panel must allow it */
3660 assert_panel_unlocked(dev_priv, pipe);
3661 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3662
3663 intel_fdi_normal_train(crtc);
3664
3665 /* For PCH DP, enable TRANS_DP_CTL */
3666 if (HAS_PCH_CPT(dev) &&
3667 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3668 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3669 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3670 reg = TRANS_DP_CTL(pipe);
3671 temp = I915_READ(reg);
3672 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3673 TRANS_DP_SYNC_MASK |
3674 TRANS_DP_BPC_MASK);
3675 temp |= (TRANS_DP_OUTPUT_ENABLE |
3676 TRANS_DP_ENH_FRAMING);
3677 temp |= bpc << 9; /* same format but at 11:9 */
3678
3679 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3680 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3681 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3682 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3683
3684 switch (intel_trans_dp_port_sel(crtc)) {
3685 case PCH_DP_B:
3686 temp |= TRANS_DP_PORT_SEL_B;
3687 break;
3688 case PCH_DP_C:
3689 temp |= TRANS_DP_PORT_SEL_C;
3690 break;
3691 case PCH_DP_D:
3692 temp |= TRANS_DP_PORT_SEL_D;
3693 break;
3694 default:
3695 BUG();
3696 }
3697
3698 I915_WRITE(reg, temp);
3699 }
3700
3701 ironlake_enable_pch_transcoder(dev_priv, pipe);
3702 }
3703
3704 static void lpt_pch_enable(struct drm_crtc *crtc)
3705 {
3706 struct drm_device *dev = crtc->dev;
3707 struct drm_i915_private *dev_priv = dev->dev_private;
3708 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3709 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3710
3711 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3712
3713 lpt_program_iclkip(crtc);
3714
3715 /* Set transcoder timing. */
3716 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3717
3718 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3719 }
3720
3721 void intel_put_shared_dpll(struct intel_crtc *crtc)
3722 {
3723 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3724
3725 if (pll == NULL)
3726 return;
3727
3728 if (pll->refcount == 0) {
3729 WARN(1, "bad %s refcount\n", pll->name);
3730 return;
3731 }
3732
3733 if (--pll->refcount == 0) {
3734 WARN_ON(pll->on);
3735 WARN_ON(pll->active);
3736 }
3737
3738 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3739 }
3740
3741 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3742 {
3743 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3744 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3745 enum intel_dpll_id i;
3746
3747 if (pll) {
3748 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3749 crtc->base.base.id, pll->name);
3750 intel_put_shared_dpll(crtc);
3751 }
3752
3753 if (HAS_PCH_IBX(dev_priv->dev)) {
3754 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3755 i = (enum intel_dpll_id) crtc->pipe;
3756 pll = &dev_priv->shared_dplls[i];
3757
3758 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3759 crtc->base.base.id, pll->name);
3760
3761 WARN_ON(pll->refcount);
3762
3763 goto found;
3764 }
3765
3766 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3767 pll = &dev_priv->shared_dplls[i];
3768
3769 /* Only want to check enabled timings first */
3770 if (pll->refcount == 0)
3771 continue;
3772
3773 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3774 sizeof(pll->hw_state)) == 0) {
3775 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3776 crtc->base.base.id,
3777 pll->name, pll->refcount, pll->active);
3778
3779 goto found;
3780 }
3781 }
3782
3783 /* Ok no matching timings, maybe there's a free one? */
3784 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3785 pll = &dev_priv->shared_dplls[i];
3786 if (pll->refcount == 0) {
3787 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3788 crtc->base.base.id, pll->name);
3789 goto found;
3790 }
3791 }
3792
3793 return NULL;
3794
3795 found:
3796 if (pll->refcount == 0)
3797 pll->hw_state = crtc->config.dpll_hw_state;
3798
3799 crtc->config.shared_dpll = i;
3800 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3801 pipe_name(crtc->pipe));
3802
3803 pll->refcount++;
3804
3805 return pll;
3806 }
3807
3808 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3809 {
3810 struct drm_i915_private *dev_priv = dev->dev_private;
3811 int dslreg = PIPEDSL(pipe);
3812 u32 temp;
3813
3814 temp = I915_READ(dslreg);
3815 udelay(500);
3816 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3817 if (wait_for(I915_READ(dslreg) != temp, 5))
3818 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3819 }
3820 }
3821
3822 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3823 {
3824 struct drm_device *dev = crtc->base.dev;
3825 struct drm_i915_private *dev_priv = dev->dev_private;
3826 int pipe = crtc->pipe;
3827
3828 if (crtc->config.pch_pfit.enabled) {
3829 /* Force use of hard-coded filter coefficients
3830 * as some pre-programmed values are broken,
3831 * e.g. x201.
3832 */
3833 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3834 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3835 PF_PIPE_SEL_IVB(pipe));
3836 else
3837 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3838 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3839 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3840 }
3841 }
3842
3843 static void intel_enable_planes(struct drm_crtc *crtc)
3844 {
3845 struct drm_device *dev = crtc->dev;
3846 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3847 struct drm_plane *plane;
3848 struct intel_plane *intel_plane;
3849
3850 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3851 intel_plane = to_intel_plane(plane);
3852 if (intel_plane->pipe == pipe)
3853 intel_plane_restore(&intel_plane->base);
3854 }
3855 }
3856
3857 static void intel_disable_planes(struct drm_crtc *crtc)
3858 {
3859 struct drm_device *dev = crtc->dev;
3860 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3861 struct drm_plane *plane;
3862 struct intel_plane *intel_plane;
3863
3864 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3865 intel_plane = to_intel_plane(plane);
3866 if (intel_plane->pipe == pipe)
3867 intel_plane_disable(&intel_plane->base);
3868 }
3869 }
3870
3871 void hsw_enable_ips(struct intel_crtc *crtc)
3872 {
3873 struct drm_device *dev = crtc->base.dev;
3874 struct drm_i915_private *dev_priv = dev->dev_private;
3875
3876 if (!crtc->config.ips_enabled)
3877 return;
3878
3879 /* We can only enable IPS after we enable a plane and wait for a vblank */
3880 intel_wait_for_vblank(dev, crtc->pipe);
3881
3882 assert_plane_enabled(dev_priv, crtc->plane);
3883 if (IS_BROADWELL(dev)) {
3884 mutex_lock(&dev_priv->rps.hw_lock);
3885 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3886 mutex_unlock(&dev_priv->rps.hw_lock);
3887 /* Quoting Art Runyan: "its not safe to expect any particular
3888 * value in IPS_CTL bit 31 after enabling IPS through the
3889 * mailbox." Moreover, the mailbox may return a bogus state,
3890 * so we need to just enable it and continue on.
3891 */
3892 } else {
3893 I915_WRITE(IPS_CTL, IPS_ENABLE);
3894 /* The bit only becomes 1 in the next vblank, so this wait here
3895 * is essentially intel_wait_for_vblank. If we don't have this
3896 * and don't wait for vblanks until the end of crtc_enable, then
3897 * the HW state readout code will complain that the expected
3898 * IPS_CTL value is not the one we read. */
3899 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3900 DRM_ERROR("Timed out waiting for IPS enable\n");
3901 }
3902 }
3903
3904 void hsw_disable_ips(struct intel_crtc *crtc)
3905 {
3906 struct drm_device *dev = crtc->base.dev;
3907 struct drm_i915_private *dev_priv = dev->dev_private;
3908
3909 if (!crtc->config.ips_enabled)
3910 return;
3911
3912 assert_plane_enabled(dev_priv, crtc->plane);
3913 if (IS_BROADWELL(dev)) {
3914 mutex_lock(&dev_priv->rps.hw_lock);
3915 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3916 mutex_unlock(&dev_priv->rps.hw_lock);
3917 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3918 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3919 DRM_ERROR("Timed out waiting for IPS disable\n");
3920 } else {
3921 I915_WRITE(IPS_CTL, 0);
3922 POSTING_READ(IPS_CTL);
3923 }
3924
3925 /* We need to wait for a vblank before we can disable the plane. */
3926 intel_wait_for_vblank(dev, crtc->pipe);
3927 }
3928
3929 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3930 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3931 {
3932 struct drm_device *dev = crtc->dev;
3933 struct drm_i915_private *dev_priv = dev->dev_private;
3934 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3935 enum pipe pipe = intel_crtc->pipe;
3936 int palreg = PALETTE(pipe);
3937 int i;
3938 bool reenable_ips = false;
3939
3940 /* The clocks have to be on to load the palette. */
3941 if (!crtc->enabled || !intel_crtc->active)
3942 return;
3943
3944 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3945 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3946 assert_dsi_pll_enabled(dev_priv);
3947 else
3948 assert_pll_enabled(dev_priv, pipe);
3949 }
3950
3951 /* use legacy palette for Ironlake */
3952 if (!HAS_GMCH_DISPLAY(dev))
3953 palreg = LGC_PALETTE(pipe);
3954
3955 /* Workaround : Do not read or write the pipe palette/gamma data while
3956 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3957 */
3958 if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3959 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3960 GAMMA_MODE_MODE_SPLIT)) {
3961 hsw_disable_ips(intel_crtc);
3962 reenable_ips = true;
3963 }
3964
3965 for (i = 0; i < 256; i++) {
3966 I915_WRITE(palreg + 4 * i,
3967 (intel_crtc->lut_r[i] << 16) |
3968 (intel_crtc->lut_g[i] << 8) |
3969 intel_crtc->lut_b[i]);
3970 }
3971
3972 if (reenable_ips)
3973 hsw_enable_ips(intel_crtc);
3974 }
3975
3976 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3977 {
3978 if (!enable && intel_crtc->overlay) {
3979 struct drm_device *dev = intel_crtc->base.dev;
3980 struct drm_i915_private *dev_priv = dev->dev_private;
3981
3982 mutex_lock(&dev->struct_mutex);
3983 dev_priv->mm.interruptible = false;
3984 (void) intel_overlay_switch_off(intel_crtc->overlay);
3985 dev_priv->mm.interruptible = true;
3986 mutex_unlock(&dev->struct_mutex);
3987 }
3988
3989 /* Let userspace switch the overlay on again. In most cases userspace
3990 * has to recompute where to put it anyway.
3991 */
3992 }
3993
3994 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
3995 {
3996 struct drm_device *dev = crtc->dev;
3997 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3998 int pipe = intel_crtc->pipe;
3999
4000 intel_enable_primary_hw_plane(crtc->primary, crtc);
4001 intel_enable_planes(crtc);
4002 intel_crtc_update_cursor(crtc, true);
4003 intel_crtc_dpms_overlay(intel_crtc, true);
4004
4005 hsw_enable_ips(intel_crtc);
4006
4007 mutex_lock(&dev->struct_mutex);
4008 intel_update_fbc(dev);
4009 mutex_unlock(&dev->struct_mutex);
4010
4011 /*
4012 * FIXME: Once we grow proper nuclear flip support out of this we need
4013 * to compute the mask of flip planes precisely. For the time being
4014 * consider this a flip from a NULL plane.
4015 */
4016 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4017 }
4018
4019 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4020 {
4021 struct drm_device *dev = crtc->dev;
4022 struct drm_i915_private *dev_priv = dev->dev_private;
4023 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4024 int pipe = intel_crtc->pipe;
4025 int plane = intel_crtc->plane;
4026
4027 intel_crtc_wait_for_pending_flips(crtc);
4028
4029 if (dev_priv->fbc.plane == plane)
4030 intel_disable_fbc(dev);
4031
4032 hsw_disable_ips(intel_crtc);
4033
4034 intel_crtc_dpms_overlay(intel_crtc, false);
4035 intel_crtc_update_cursor(crtc, false);
4036 intel_disable_planes(crtc);
4037 intel_disable_primary_hw_plane(crtc->primary, crtc);
4038
4039 /*
4040 * FIXME: Once we grow proper nuclear flip support out of this we need
4041 * to compute the mask of flip planes precisely. For the time being
4042 * consider this a flip to a NULL plane.
4043 */
4044 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4045 }
4046
4047 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4048 {
4049 struct drm_device *dev = crtc->dev;
4050 struct drm_i915_private *dev_priv = dev->dev_private;
4051 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4052 struct intel_encoder *encoder;
4053 int pipe = intel_crtc->pipe;
4054
4055 WARN_ON(!crtc->enabled);
4056
4057 if (intel_crtc->active)
4058 return;
4059
4060 if (intel_crtc->config.has_pch_encoder)
4061 intel_prepare_shared_dpll(intel_crtc);
4062
4063 if (intel_crtc->config.has_dp_encoder)
4064 intel_dp_set_m_n(intel_crtc);
4065
4066 intel_set_pipe_timings(intel_crtc);
4067
4068 if (intel_crtc->config.has_pch_encoder) {
4069 intel_cpu_transcoder_set_m_n(intel_crtc,
4070 &intel_crtc->config.fdi_m_n, NULL);
4071 }
4072
4073 ironlake_set_pipeconf(crtc);
4074
4075 intel_crtc->active = true;
4076
4077 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4078 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4079
4080 for_each_encoder_on_crtc(dev, crtc, encoder)
4081 if (encoder->pre_enable)
4082 encoder->pre_enable(encoder);
4083
4084 if (intel_crtc->config.has_pch_encoder) {
4085 /* Note: FDI PLL enabling _must_ be done before we enable the
4086 * cpu pipes, hence this is separate from all the other fdi/pch
4087 * enabling. */
4088 ironlake_fdi_pll_enable(intel_crtc);
4089 } else {
4090 assert_fdi_tx_disabled(dev_priv, pipe);
4091 assert_fdi_rx_disabled(dev_priv, pipe);
4092 }
4093
4094 ironlake_pfit_enable(intel_crtc);
4095
4096 /*
4097 * On ILK+ LUT must be loaded before the pipe is running but with
4098 * clocks enabled
4099 */
4100 intel_crtc_load_lut(crtc);
4101
4102 intel_update_watermarks(crtc);
4103 intel_enable_pipe(intel_crtc);
4104
4105 if (intel_crtc->config.has_pch_encoder)
4106 ironlake_pch_enable(crtc);
4107
4108 for_each_encoder_on_crtc(dev, crtc, encoder)
4109 encoder->enable(encoder);
4110
4111 if (HAS_PCH_CPT(dev))
4112 cpt_verify_modeset(dev, intel_crtc->pipe);
4113
4114 assert_vblank_disabled(crtc);
4115 drm_crtc_vblank_on(crtc);
4116
4117 intel_crtc_enable_planes(crtc);
4118 }
4119
4120 /* IPS only exists on ULT machines and is tied to pipe A. */
4121 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4122 {
4123 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4124 }
4125
4126 /*
4127 * This implements the workaround described in the "notes" section of the mode
4128 * set sequence documentation. When going from no pipes or single pipe to
4129 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4130 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4131 */
4132 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4133 {
4134 struct drm_device *dev = crtc->base.dev;
4135 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4136
4137 /* We want to get the other_active_crtc only if there's only 1 other
4138 * active crtc. */
4139 for_each_intel_crtc(dev, crtc_it) {
4140 if (!crtc_it->active || crtc_it == crtc)
4141 continue;
4142
4143 if (other_active_crtc)
4144 return;
4145
4146 other_active_crtc = crtc_it;
4147 }
4148 if (!other_active_crtc)
4149 return;
4150
4151 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4152 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4153 }
4154
4155 static void haswell_crtc_enable(struct drm_crtc *crtc)
4156 {
4157 struct drm_device *dev = crtc->dev;
4158 struct drm_i915_private *dev_priv = dev->dev_private;
4159 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4160 struct intel_encoder *encoder;
4161 int pipe = intel_crtc->pipe;
4162
4163 WARN_ON(!crtc->enabled);
4164
4165 if (intel_crtc->active)
4166 return;
4167
4168 if (intel_crtc_to_shared_dpll(intel_crtc))
4169 intel_enable_shared_dpll(intel_crtc);
4170
4171 if (intel_crtc->config.has_dp_encoder)
4172 intel_dp_set_m_n(intel_crtc);
4173
4174 intel_set_pipe_timings(intel_crtc);
4175
4176 if (intel_crtc->config.has_pch_encoder) {
4177 intel_cpu_transcoder_set_m_n(intel_crtc,
4178 &intel_crtc->config.fdi_m_n, NULL);
4179 }
4180
4181 haswell_set_pipeconf(crtc);
4182
4183 intel_set_pipe_csc(crtc);
4184
4185 intel_crtc->active = true;
4186
4187 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4188 for_each_encoder_on_crtc(dev, crtc, encoder)
4189 if (encoder->pre_enable)
4190 encoder->pre_enable(encoder);
4191
4192 if (intel_crtc->config.has_pch_encoder) {
4193 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4194 dev_priv->display.fdi_link_train(crtc);
4195 }
4196
4197 intel_ddi_enable_pipe_clock(intel_crtc);
4198
4199 ironlake_pfit_enable(intel_crtc);
4200
4201 /*
4202 * On ILK+ LUT must be loaded before the pipe is running but with
4203 * clocks enabled
4204 */
4205 intel_crtc_load_lut(crtc);
4206
4207 intel_ddi_set_pipe_settings(crtc);
4208 intel_ddi_enable_transcoder_func(crtc);
4209
4210 intel_update_watermarks(crtc);
4211 intel_enable_pipe(intel_crtc);
4212
4213 if (intel_crtc->config.has_pch_encoder)
4214 lpt_pch_enable(crtc);
4215
4216 if (intel_crtc->config.dp_encoder_is_mst)
4217 intel_ddi_set_vc_payload_alloc(crtc, true);
4218
4219 for_each_encoder_on_crtc(dev, crtc, encoder) {
4220 encoder->enable(encoder);
4221 intel_opregion_notify_encoder(encoder, true);
4222 }
4223
4224 assert_vblank_disabled(crtc);
4225 drm_crtc_vblank_on(crtc);
4226
4227 /* If we change the relative order between pipe/planes enabling, we need
4228 * to change the workaround. */
4229 haswell_mode_set_planes_workaround(intel_crtc);
4230 intel_crtc_enable_planes(crtc);
4231 }
4232
4233 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4234 {
4235 struct drm_device *dev = crtc->base.dev;
4236 struct drm_i915_private *dev_priv = dev->dev_private;
4237 int pipe = crtc->pipe;
4238
4239 /* To avoid upsetting the power well on haswell only disable the pfit if
4240 * it's in use. The hw state code will make sure we get this right. */
4241 if (crtc->config.pch_pfit.enabled) {
4242 I915_WRITE(PF_CTL(pipe), 0);
4243 I915_WRITE(PF_WIN_POS(pipe), 0);
4244 I915_WRITE(PF_WIN_SZ(pipe), 0);
4245 }
4246 }
4247
4248 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4249 {
4250 struct drm_device *dev = crtc->dev;
4251 struct drm_i915_private *dev_priv = dev->dev_private;
4252 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4253 struct intel_encoder *encoder;
4254 int pipe = intel_crtc->pipe;
4255 u32 reg, temp;
4256
4257 if (!intel_crtc->active)
4258 return;
4259
4260 intel_crtc_disable_planes(crtc);
4261
4262 drm_crtc_vblank_off(crtc);
4263 assert_vblank_disabled(crtc);
4264
4265 for_each_encoder_on_crtc(dev, crtc, encoder)
4266 encoder->disable(encoder);
4267
4268 if (intel_crtc->config.has_pch_encoder)
4269 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
4270
4271 intel_disable_pipe(intel_crtc);
4272
4273 ironlake_pfit_disable(intel_crtc);
4274
4275 for_each_encoder_on_crtc(dev, crtc, encoder)
4276 if (encoder->post_disable)
4277 encoder->post_disable(encoder);
4278
4279 if (intel_crtc->config.has_pch_encoder) {
4280 ironlake_fdi_disable(crtc);
4281
4282 ironlake_disable_pch_transcoder(dev_priv, pipe);
4283 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4284
4285 if (HAS_PCH_CPT(dev)) {
4286 /* disable TRANS_DP_CTL */
4287 reg = TRANS_DP_CTL(pipe);
4288 temp = I915_READ(reg);
4289 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4290 TRANS_DP_PORT_SEL_MASK);
4291 temp |= TRANS_DP_PORT_SEL_NONE;
4292 I915_WRITE(reg, temp);
4293
4294 /* disable DPLL_SEL */
4295 temp = I915_READ(PCH_DPLL_SEL);
4296 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4297 I915_WRITE(PCH_DPLL_SEL, temp);
4298 }
4299
4300 /* disable PCH DPLL */
4301 intel_disable_shared_dpll(intel_crtc);
4302
4303 ironlake_fdi_pll_disable(intel_crtc);
4304 }
4305
4306 intel_crtc->active = false;
4307 intel_update_watermarks(crtc);
4308
4309 mutex_lock(&dev->struct_mutex);
4310 intel_update_fbc(dev);
4311 mutex_unlock(&dev->struct_mutex);
4312 }
4313
4314 static void haswell_crtc_disable(struct drm_crtc *crtc)
4315 {
4316 struct drm_device *dev = crtc->dev;
4317 struct drm_i915_private *dev_priv = dev->dev_private;
4318 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4319 struct intel_encoder *encoder;
4320 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4321
4322 if (!intel_crtc->active)
4323 return;
4324
4325 intel_crtc_disable_planes(crtc);
4326
4327 drm_crtc_vblank_off(crtc);
4328 assert_vblank_disabled(crtc);
4329
4330 for_each_encoder_on_crtc(dev, crtc, encoder) {
4331 intel_opregion_notify_encoder(encoder, false);
4332 encoder->disable(encoder);
4333 }
4334
4335 if (intel_crtc->config.has_pch_encoder)
4336 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4337 intel_disable_pipe(intel_crtc);
4338
4339 if (intel_crtc->config.dp_encoder_is_mst)
4340 intel_ddi_set_vc_payload_alloc(crtc, false);
4341
4342 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4343
4344 ironlake_pfit_disable(intel_crtc);
4345
4346 intel_ddi_disable_pipe_clock(intel_crtc);
4347
4348 if (intel_crtc->config.has_pch_encoder) {
4349 lpt_disable_pch_transcoder(dev_priv);
4350 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4351 intel_ddi_fdi_disable(crtc);
4352 }
4353
4354 for_each_encoder_on_crtc(dev, crtc, encoder)
4355 if (encoder->post_disable)
4356 encoder->post_disable(encoder);
4357
4358 intel_crtc->active = false;
4359 intel_update_watermarks(crtc);
4360
4361 mutex_lock(&dev->struct_mutex);
4362 intel_update_fbc(dev);
4363 mutex_unlock(&dev->struct_mutex);
4364
4365 if (intel_crtc_to_shared_dpll(intel_crtc))
4366 intel_disable_shared_dpll(intel_crtc);
4367 }
4368
4369 static void ironlake_crtc_off(struct drm_crtc *crtc)
4370 {
4371 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4372 intel_put_shared_dpll(intel_crtc);
4373 }
4374
4375
4376 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4377 {
4378 struct drm_device *dev = crtc->base.dev;
4379 struct drm_i915_private *dev_priv = dev->dev_private;
4380 struct intel_crtc_config *pipe_config = &crtc->config;
4381
4382 if (!crtc->config.gmch_pfit.control)
4383 return;
4384
4385 /*
4386 * The panel fitter should only be adjusted whilst the pipe is disabled,
4387 * according to register description and PRM.
4388 */
4389 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4390 assert_pipe_disabled(dev_priv, crtc->pipe);
4391
4392 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4393 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4394
4395 /* Border color in case we don't scale up to the full screen. Black by
4396 * default, change to something else for debugging. */
4397 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4398 }
4399
4400 static enum intel_display_power_domain port_to_power_domain(enum port port)
4401 {
4402 switch (port) {
4403 case PORT_A:
4404 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4405 case PORT_B:
4406 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4407 case PORT_C:
4408 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4409 case PORT_D:
4410 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4411 default:
4412 WARN_ON_ONCE(1);
4413 return POWER_DOMAIN_PORT_OTHER;
4414 }
4415 }
4416
4417 #define for_each_power_domain(domain, mask) \
4418 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4419 if ((1 << (domain)) & (mask))
4420
4421 enum intel_display_power_domain
4422 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4423 {
4424 struct drm_device *dev = intel_encoder->base.dev;
4425 struct intel_digital_port *intel_dig_port;
4426
4427 switch (intel_encoder->type) {
4428 case INTEL_OUTPUT_UNKNOWN:
4429 /* Only DDI platforms should ever use this output type */
4430 WARN_ON_ONCE(!HAS_DDI(dev));
4431 case INTEL_OUTPUT_DISPLAYPORT:
4432 case INTEL_OUTPUT_HDMI:
4433 case INTEL_OUTPUT_EDP:
4434 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4435 return port_to_power_domain(intel_dig_port->port);
4436 case INTEL_OUTPUT_DP_MST:
4437 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4438 return port_to_power_domain(intel_dig_port->port);
4439 case INTEL_OUTPUT_ANALOG:
4440 return POWER_DOMAIN_PORT_CRT;
4441 case INTEL_OUTPUT_DSI:
4442 return POWER_DOMAIN_PORT_DSI;
4443 default:
4444 return POWER_DOMAIN_PORT_OTHER;
4445 }
4446 }
4447
4448 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4449 {
4450 struct drm_device *dev = crtc->dev;
4451 struct intel_encoder *intel_encoder;
4452 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4453 enum pipe pipe = intel_crtc->pipe;
4454 unsigned long mask;
4455 enum transcoder transcoder;
4456
4457 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4458
4459 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4460 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4461 if (intel_crtc->config.pch_pfit.enabled ||
4462 intel_crtc->config.pch_pfit.force_thru)
4463 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4464
4465 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4466 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4467
4468 return mask;
4469 }
4470
4471 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4472 bool enable)
4473 {
4474 if (dev_priv->power_domains.init_power_on == enable)
4475 return;
4476
4477 if (enable)
4478 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4479 else
4480 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4481
4482 dev_priv->power_domains.init_power_on = enable;
4483 }
4484
4485 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4486 {
4487 struct drm_i915_private *dev_priv = dev->dev_private;
4488 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4489 struct intel_crtc *crtc;
4490
4491 /*
4492 * First get all needed power domains, then put all unneeded, to avoid
4493 * any unnecessary toggling of the power wells.
4494 */
4495 for_each_intel_crtc(dev, crtc) {
4496 enum intel_display_power_domain domain;
4497
4498 if (!crtc->base.enabled)
4499 continue;
4500
4501 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4502
4503 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4504 intel_display_power_get(dev_priv, domain);
4505 }
4506
4507 for_each_intel_crtc(dev, crtc) {
4508 enum intel_display_power_domain domain;
4509
4510 for_each_power_domain(domain, crtc->enabled_power_domains)
4511 intel_display_power_put(dev_priv, domain);
4512
4513 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4514 }
4515
4516 intel_display_set_init_power(dev_priv, false);
4517 }
4518
4519 /* returns HPLL frequency in kHz */
4520 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4521 {
4522 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4523
4524 /* Obtain SKU information */
4525 mutex_lock(&dev_priv->dpio_lock);
4526 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4527 CCK_FUSE_HPLL_FREQ_MASK;
4528 mutex_unlock(&dev_priv->dpio_lock);
4529
4530 return vco_freq[hpll_freq] * 1000;
4531 }
4532
4533 static void vlv_update_cdclk(struct drm_device *dev)
4534 {
4535 struct drm_i915_private *dev_priv = dev->dev_private;
4536
4537 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4538 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz",
4539 dev_priv->vlv_cdclk_freq);
4540
4541 /*
4542 * Program the gmbus_freq based on the cdclk frequency.
4543 * BSpec erroneously claims we should aim for 4MHz, but
4544 * in fact 1MHz is the correct frequency.
4545 */
4546 I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq);
4547 }
4548
4549 /* Adjust CDclk dividers to allow high res or save power if possible */
4550 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4551 {
4552 struct drm_i915_private *dev_priv = dev->dev_private;
4553 u32 val, cmd;
4554
4555 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4556
4557 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4558 cmd = 2;
4559 else if (cdclk == 266667)
4560 cmd = 1;
4561 else
4562 cmd = 0;
4563
4564 mutex_lock(&dev_priv->rps.hw_lock);
4565 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4566 val &= ~DSPFREQGUAR_MASK;
4567 val |= (cmd << DSPFREQGUAR_SHIFT);
4568 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4569 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4570 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4571 50)) {
4572 DRM_ERROR("timed out waiting for CDclk change\n");
4573 }
4574 mutex_unlock(&dev_priv->rps.hw_lock);
4575
4576 if (cdclk == 400000) {
4577 u32 divider, vco;
4578
4579 vco = valleyview_get_vco(dev_priv);
4580 divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1;
4581
4582 mutex_lock(&dev_priv->dpio_lock);
4583 /* adjust cdclk divider */
4584 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4585 val &= ~DISPLAY_FREQUENCY_VALUES;
4586 val |= divider;
4587 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4588
4589 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4590 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4591 50))
4592 DRM_ERROR("timed out waiting for CDclk change\n");
4593 mutex_unlock(&dev_priv->dpio_lock);
4594 }
4595
4596 mutex_lock(&dev_priv->dpio_lock);
4597 /* adjust self-refresh exit latency value */
4598 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4599 val &= ~0x7f;
4600
4601 /*
4602 * For high bandwidth configs, we set a higher latency in the bunit
4603 * so that the core display fetch happens in time to avoid underruns.
4604 */
4605 if (cdclk == 400000)
4606 val |= 4500 / 250; /* 4.5 usec */
4607 else
4608 val |= 3000 / 250; /* 3.0 usec */
4609 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4610 mutex_unlock(&dev_priv->dpio_lock);
4611
4612 vlv_update_cdclk(dev);
4613 }
4614
4615 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4616 {
4617 struct drm_i915_private *dev_priv = dev->dev_private;
4618 u32 val, cmd;
4619
4620 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4621
4622 switch (cdclk) {
4623 case 400000:
4624 cmd = 3;
4625 break;
4626 case 333333:
4627 case 320000:
4628 cmd = 2;
4629 break;
4630 case 266667:
4631 cmd = 1;
4632 break;
4633 case 200000:
4634 cmd = 0;
4635 break;
4636 default:
4637 WARN_ON(1);
4638 return;
4639 }
4640
4641 mutex_lock(&dev_priv->rps.hw_lock);
4642 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4643 val &= ~DSPFREQGUAR_MASK_CHV;
4644 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4645 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4646 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4647 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4648 50)) {
4649 DRM_ERROR("timed out waiting for CDclk change\n");
4650 }
4651 mutex_unlock(&dev_priv->rps.hw_lock);
4652
4653 vlv_update_cdclk(dev);
4654 }
4655
4656 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4657 int max_pixclk)
4658 {
4659 int vco = valleyview_get_vco(dev_priv);
4660 int freq_320 = (vco << 1) % 320000 != 0 ? 333333 : 320000;
4661
4662 /* FIXME: Punit isn't quite ready yet */
4663 if (IS_CHERRYVIEW(dev_priv->dev))
4664 return 400000;
4665
4666 /*
4667 * Really only a few cases to deal with, as only 4 CDclks are supported:
4668 * 200MHz
4669 * 267MHz
4670 * 320/333MHz (depends on HPLL freq)
4671 * 400MHz
4672 * So we check to see whether we're above 90% of the lower bin and
4673 * adjust if needed.
4674 *
4675 * We seem to get an unstable or solid color picture at 200MHz.
4676 * Not sure what's wrong. For now use 200MHz only when all pipes
4677 * are off.
4678 */
4679 if (max_pixclk > freq_320*9/10)
4680 return 400000;
4681 else if (max_pixclk > 266667*9/10)
4682 return freq_320;
4683 else if (max_pixclk > 0)
4684 return 266667;
4685 else
4686 return 200000;
4687 }
4688
4689 /* compute the max pixel clock for new configuration */
4690 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4691 {
4692 struct drm_device *dev = dev_priv->dev;
4693 struct intel_crtc *intel_crtc;
4694 int max_pixclk = 0;
4695
4696 for_each_intel_crtc(dev, intel_crtc) {
4697 if (intel_crtc->new_enabled)
4698 max_pixclk = max(max_pixclk,
4699 intel_crtc->new_config->adjusted_mode.crtc_clock);
4700 }
4701
4702 return max_pixclk;
4703 }
4704
4705 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4706 unsigned *prepare_pipes)
4707 {
4708 struct drm_i915_private *dev_priv = dev->dev_private;
4709 struct intel_crtc *intel_crtc;
4710 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4711
4712 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4713 dev_priv->vlv_cdclk_freq)
4714 return;
4715
4716 /* disable/enable all currently active pipes while we change cdclk */
4717 for_each_intel_crtc(dev, intel_crtc)
4718 if (intel_crtc->base.enabled)
4719 *prepare_pipes |= (1 << intel_crtc->pipe);
4720 }
4721
4722 static void valleyview_modeset_global_resources(struct drm_device *dev)
4723 {
4724 struct drm_i915_private *dev_priv = dev->dev_private;
4725 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4726 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4727
4728 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
4729 if (IS_CHERRYVIEW(dev))
4730 cherryview_set_cdclk(dev, req_cdclk);
4731 else
4732 valleyview_set_cdclk(dev, req_cdclk);
4733 }
4734
4735 modeset_update_crtc_power_domains(dev);
4736 }
4737
4738 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4739 {
4740 struct drm_device *dev = crtc->dev;
4741 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4742 struct intel_encoder *encoder;
4743 int pipe = intel_crtc->pipe;
4744 bool is_dsi;
4745
4746 WARN_ON(!crtc->enabled);
4747
4748 if (intel_crtc->active)
4749 return;
4750
4751 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4752
4753 if (!is_dsi) {
4754 if (IS_CHERRYVIEW(dev))
4755 chv_prepare_pll(intel_crtc);
4756 else
4757 vlv_prepare_pll(intel_crtc);
4758 }
4759
4760 if (intel_crtc->config.has_dp_encoder)
4761 intel_dp_set_m_n(intel_crtc);
4762
4763 intel_set_pipe_timings(intel_crtc);
4764
4765 i9xx_set_pipeconf(intel_crtc);
4766
4767 intel_crtc->active = true;
4768
4769 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4770
4771 for_each_encoder_on_crtc(dev, crtc, encoder)
4772 if (encoder->pre_pll_enable)
4773 encoder->pre_pll_enable(encoder);
4774
4775 if (!is_dsi) {
4776 if (IS_CHERRYVIEW(dev))
4777 chv_enable_pll(intel_crtc);
4778 else
4779 vlv_enable_pll(intel_crtc);
4780 }
4781
4782 for_each_encoder_on_crtc(dev, crtc, encoder)
4783 if (encoder->pre_enable)
4784 encoder->pre_enable(encoder);
4785
4786 i9xx_pfit_enable(intel_crtc);
4787
4788 intel_crtc_load_lut(crtc);
4789
4790 intel_update_watermarks(crtc);
4791 intel_enable_pipe(intel_crtc);
4792
4793 for_each_encoder_on_crtc(dev, crtc, encoder)
4794 encoder->enable(encoder);
4795
4796 assert_vblank_disabled(crtc);
4797 drm_crtc_vblank_on(crtc);
4798
4799 intel_crtc_enable_planes(crtc);
4800
4801 /* Underruns don't raise interrupts, so check manually. */
4802 i9xx_check_fifo_underruns(dev);
4803 }
4804
4805 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4806 {
4807 struct drm_device *dev = crtc->base.dev;
4808 struct drm_i915_private *dev_priv = dev->dev_private;
4809
4810 I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4811 I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4812 }
4813
4814 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4815 {
4816 struct drm_device *dev = crtc->dev;
4817 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4818 struct intel_encoder *encoder;
4819 int pipe = intel_crtc->pipe;
4820
4821 WARN_ON(!crtc->enabled);
4822
4823 if (intel_crtc->active)
4824 return;
4825
4826 i9xx_set_pll_dividers(intel_crtc);
4827
4828 if (intel_crtc->config.has_dp_encoder)
4829 intel_dp_set_m_n(intel_crtc);
4830
4831 intel_set_pipe_timings(intel_crtc);
4832
4833 i9xx_set_pipeconf(intel_crtc);
4834
4835 intel_crtc->active = true;
4836
4837 if (!IS_GEN2(dev))
4838 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4839
4840 for_each_encoder_on_crtc(dev, crtc, encoder)
4841 if (encoder->pre_enable)
4842 encoder->pre_enable(encoder);
4843
4844 i9xx_enable_pll(intel_crtc);
4845
4846 i9xx_pfit_enable(intel_crtc);
4847
4848 intel_crtc_load_lut(crtc);
4849
4850 intel_update_watermarks(crtc);
4851 intel_enable_pipe(intel_crtc);
4852
4853 for_each_encoder_on_crtc(dev, crtc, encoder)
4854 encoder->enable(encoder);
4855
4856 assert_vblank_disabled(crtc);
4857 drm_crtc_vblank_on(crtc);
4858
4859 intel_crtc_enable_planes(crtc);
4860
4861 /*
4862 * Gen2 reports pipe underruns whenever all planes are disabled.
4863 * So don't enable underrun reporting before at least some planes
4864 * are enabled.
4865 * FIXME: Need to fix the logic to work when we turn off all planes
4866 * but leave the pipe running.
4867 */
4868 if (IS_GEN2(dev))
4869 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4870
4871 /* Underruns don't raise interrupts, so check manually. */
4872 i9xx_check_fifo_underruns(dev);
4873 }
4874
4875 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4876 {
4877 struct drm_device *dev = crtc->base.dev;
4878 struct drm_i915_private *dev_priv = dev->dev_private;
4879
4880 if (!crtc->config.gmch_pfit.control)
4881 return;
4882
4883 assert_pipe_disabled(dev_priv, crtc->pipe);
4884
4885 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4886 I915_READ(PFIT_CONTROL));
4887 I915_WRITE(PFIT_CONTROL, 0);
4888 }
4889
4890 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4891 {
4892 struct drm_device *dev = crtc->dev;
4893 struct drm_i915_private *dev_priv = dev->dev_private;
4894 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4895 struct intel_encoder *encoder;
4896 int pipe = intel_crtc->pipe;
4897
4898 if (!intel_crtc->active)
4899 return;
4900
4901 /*
4902 * Gen2 reports pipe underruns whenever all planes are disabled.
4903 * So diasble underrun reporting before all the planes get disabled.
4904 * FIXME: Need to fix the logic to work when we turn off all planes
4905 * but leave the pipe running.
4906 */
4907 if (IS_GEN2(dev))
4908 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4909
4910 /*
4911 * Vblank time updates from the shadow to live plane control register
4912 * are blocked if the memory self-refresh mode is active at that
4913 * moment. So to make sure the plane gets truly disabled, disable
4914 * first the self-refresh mode. The self-refresh enable bit in turn
4915 * will be checked/applied by the HW only at the next frame start
4916 * event which is after the vblank start event, so we need to have a
4917 * wait-for-vblank between disabling the plane and the pipe.
4918 */
4919 intel_set_memory_cxsr(dev_priv, false);
4920 intel_crtc_disable_planes(crtc);
4921
4922 /*
4923 * On gen2 planes are double buffered but the pipe isn't, so we must
4924 * wait for planes to fully turn off before disabling the pipe.
4925 * We also need to wait on all gmch platforms because of the
4926 * self-refresh mode constraint explained above.
4927 */
4928 intel_wait_for_vblank(dev, pipe);
4929
4930 drm_crtc_vblank_off(crtc);
4931 assert_vblank_disabled(crtc);
4932
4933 for_each_encoder_on_crtc(dev, crtc, encoder)
4934 encoder->disable(encoder);
4935
4936 intel_disable_pipe(intel_crtc);
4937
4938 i9xx_pfit_disable(intel_crtc);
4939
4940 for_each_encoder_on_crtc(dev, crtc, encoder)
4941 if (encoder->post_disable)
4942 encoder->post_disable(encoder);
4943
4944 if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
4945 if (IS_CHERRYVIEW(dev))
4946 chv_disable_pll(dev_priv, pipe);
4947 else if (IS_VALLEYVIEW(dev))
4948 vlv_disable_pll(dev_priv, pipe);
4949 else
4950 i9xx_disable_pll(intel_crtc);
4951 }
4952
4953 if (!IS_GEN2(dev))
4954 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4955
4956 intel_crtc->active = false;
4957 intel_update_watermarks(crtc);
4958
4959 mutex_lock(&dev->struct_mutex);
4960 intel_update_fbc(dev);
4961 mutex_unlock(&dev->struct_mutex);
4962 }
4963
4964 static void i9xx_crtc_off(struct drm_crtc *crtc)
4965 {
4966 }
4967
4968 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4969 bool enabled)
4970 {
4971 struct drm_device *dev = crtc->dev;
4972 struct drm_i915_master_private *master_priv;
4973 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4974 int pipe = intel_crtc->pipe;
4975
4976 if (!dev->primary->master)
4977 return;
4978
4979 master_priv = dev->primary->master->driver_priv;
4980 if (!master_priv->sarea_priv)
4981 return;
4982
4983 switch (pipe) {
4984 case 0:
4985 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4986 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4987 break;
4988 case 1:
4989 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4990 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4991 break;
4992 default:
4993 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4994 break;
4995 }
4996 }
4997
4998 /* Master function to enable/disable CRTC and corresponding power wells */
4999 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5000 {
5001 struct drm_device *dev = crtc->dev;
5002 struct drm_i915_private *dev_priv = dev->dev_private;
5003 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5004 enum intel_display_power_domain domain;
5005 unsigned long domains;
5006
5007 if (enable) {
5008 if (!intel_crtc->active) {
5009 domains = get_crtc_power_domains(crtc);
5010 for_each_power_domain(domain, domains)
5011 intel_display_power_get(dev_priv, domain);
5012 intel_crtc->enabled_power_domains = domains;
5013
5014 dev_priv->display.crtc_enable(crtc);
5015 }
5016 } else {
5017 if (intel_crtc->active) {
5018 dev_priv->display.crtc_disable(crtc);
5019
5020 domains = intel_crtc->enabled_power_domains;
5021 for_each_power_domain(domain, domains)
5022 intel_display_power_put(dev_priv, domain);
5023 intel_crtc->enabled_power_domains = 0;
5024 }
5025 }
5026 }
5027
5028 /**
5029 * Sets the power management mode of the pipe and plane.
5030 */
5031 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5032 {
5033 struct drm_device *dev = crtc->dev;
5034 struct intel_encoder *intel_encoder;
5035 bool enable = false;
5036
5037 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5038 enable |= intel_encoder->connectors_active;
5039
5040 intel_crtc_control(crtc, enable);
5041
5042 intel_crtc_update_sarea(crtc, enable);
5043 }
5044
5045 static void intel_crtc_disable(struct drm_crtc *crtc)
5046 {
5047 struct drm_device *dev = crtc->dev;
5048 struct drm_connector *connector;
5049 struct drm_i915_private *dev_priv = dev->dev_private;
5050 struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
5051 enum pipe pipe = to_intel_crtc(crtc)->pipe;
5052
5053 /* crtc should still be enabled when we disable it. */
5054 WARN_ON(!crtc->enabled);
5055
5056 dev_priv->display.crtc_disable(crtc);
5057 intel_crtc_update_sarea(crtc, false);
5058 dev_priv->display.off(crtc);
5059
5060 if (crtc->primary->fb) {
5061 mutex_lock(&dev->struct_mutex);
5062 intel_unpin_fb_obj(old_obj);
5063 i915_gem_track_fb(old_obj, NULL,
5064 INTEL_FRONTBUFFER_PRIMARY(pipe));
5065 mutex_unlock(&dev->struct_mutex);
5066 crtc->primary->fb = NULL;
5067 }
5068
5069 /* Update computed state. */
5070 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5071 if (!connector->encoder || !connector->encoder->crtc)
5072 continue;
5073
5074 if (connector->encoder->crtc != crtc)
5075 continue;
5076
5077 connector->dpms = DRM_MODE_DPMS_OFF;
5078 to_intel_encoder(connector->encoder)->connectors_active = false;
5079 }
5080 }
5081
5082 void intel_encoder_destroy(struct drm_encoder *encoder)
5083 {
5084 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5085
5086 drm_encoder_cleanup(encoder);
5087 kfree(intel_encoder);
5088 }
5089
5090 /* Simple dpms helper for encoders with just one connector, no cloning and only
5091 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5092 * state of the entire output pipe. */
5093 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5094 {
5095 if (mode == DRM_MODE_DPMS_ON) {
5096 encoder->connectors_active = true;
5097
5098 intel_crtc_update_dpms(encoder->base.crtc);
5099 } else {
5100 encoder->connectors_active = false;
5101
5102 intel_crtc_update_dpms(encoder->base.crtc);
5103 }
5104 }
5105
5106 /* Cross check the actual hw state with our own modeset state tracking (and it's
5107 * internal consistency). */
5108 static void intel_connector_check_state(struct intel_connector *connector)
5109 {
5110 if (connector->get_hw_state(connector)) {
5111 struct intel_encoder *encoder = connector->encoder;
5112 struct drm_crtc *crtc;
5113 bool encoder_enabled;
5114 enum pipe pipe;
5115
5116 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5117 connector->base.base.id,
5118 connector->base.name);
5119
5120 /* there is no real hw state for MST connectors */
5121 if (connector->mst_port)
5122 return;
5123
5124 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5125 "wrong connector dpms state\n");
5126 WARN(connector->base.encoder != &encoder->base,
5127 "active connector not linked to encoder\n");
5128
5129 if (encoder) {
5130 WARN(!encoder->connectors_active,
5131 "encoder->connectors_active not set\n");
5132
5133 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5134 WARN(!encoder_enabled, "encoder not enabled\n");
5135 if (WARN_ON(!encoder->base.crtc))
5136 return;
5137
5138 crtc = encoder->base.crtc;
5139
5140 WARN(!crtc->enabled, "crtc not enabled\n");
5141 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5142 WARN(pipe != to_intel_crtc(crtc)->pipe,
5143 "encoder active on the wrong pipe\n");
5144 }
5145 }
5146 }
5147
5148 /* Even simpler default implementation, if there's really no special case to
5149 * consider. */
5150 void intel_connector_dpms(struct drm_connector *connector, int mode)
5151 {
5152 /* All the simple cases only support two dpms states. */
5153 if (mode != DRM_MODE_DPMS_ON)
5154 mode = DRM_MODE_DPMS_OFF;
5155
5156 if (mode == connector->dpms)
5157 return;
5158
5159 connector->dpms = mode;
5160
5161 /* Only need to change hw state when actually enabled */
5162 if (connector->encoder)
5163 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5164
5165 intel_modeset_check_state(connector->dev);
5166 }
5167
5168 /* Simple connector->get_hw_state implementation for encoders that support only
5169 * one connector and no cloning and hence the encoder state determines the state
5170 * of the connector. */
5171 bool intel_connector_get_hw_state(struct intel_connector *connector)
5172 {
5173 enum pipe pipe = 0;
5174 struct intel_encoder *encoder = connector->encoder;
5175
5176 return encoder->get_hw_state(encoder, &pipe);
5177 }
5178
5179 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5180 struct intel_crtc_config *pipe_config)
5181 {
5182 struct drm_i915_private *dev_priv = dev->dev_private;
5183 struct intel_crtc *pipe_B_crtc =
5184 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5185
5186 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5187 pipe_name(pipe), pipe_config->fdi_lanes);
5188 if (pipe_config->fdi_lanes > 4) {
5189 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5190 pipe_name(pipe), pipe_config->fdi_lanes);
5191 return false;
5192 }
5193
5194 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5195 if (pipe_config->fdi_lanes > 2) {
5196 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5197 pipe_config->fdi_lanes);
5198 return false;
5199 } else {
5200 return true;
5201 }
5202 }
5203
5204 if (INTEL_INFO(dev)->num_pipes == 2)
5205 return true;
5206
5207 /* Ivybridge 3 pipe is really complicated */
5208 switch (pipe) {
5209 case PIPE_A:
5210 return true;
5211 case PIPE_B:
5212 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5213 pipe_config->fdi_lanes > 2) {
5214 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5215 pipe_name(pipe), pipe_config->fdi_lanes);
5216 return false;
5217 }
5218 return true;
5219 case PIPE_C:
5220 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5221 pipe_B_crtc->config.fdi_lanes <= 2) {
5222 if (pipe_config->fdi_lanes > 2) {
5223 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5224 pipe_name(pipe), pipe_config->fdi_lanes);
5225 return false;
5226 }
5227 } else {
5228 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5229 return false;
5230 }
5231 return true;
5232 default:
5233 BUG();
5234 }
5235 }
5236
5237 #define RETRY 1
5238 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5239 struct intel_crtc_config *pipe_config)
5240 {
5241 struct drm_device *dev = intel_crtc->base.dev;
5242 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5243 int lane, link_bw, fdi_dotclock;
5244 bool setup_ok, needs_recompute = false;
5245
5246 retry:
5247 /* FDI is a binary signal running at ~2.7GHz, encoding
5248 * each output octet as 10 bits. The actual frequency
5249 * is stored as a divider into a 100MHz clock, and the
5250 * mode pixel clock is stored in units of 1KHz.
5251 * Hence the bw of each lane in terms of the mode signal
5252 * is:
5253 */
5254 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5255
5256 fdi_dotclock = adjusted_mode->crtc_clock;
5257
5258 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5259 pipe_config->pipe_bpp);
5260
5261 pipe_config->fdi_lanes = lane;
5262
5263 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5264 link_bw, &pipe_config->fdi_m_n);
5265
5266 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5267 intel_crtc->pipe, pipe_config);
5268 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5269 pipe_config->pipe_bpp -= 2*3;
5270 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5271 pipe_config->pipe_bpp);
5272 needs_recompute = true;
5273 pipe_config->bw_constrained = true;
5274
5275 goto retry;
5276 }
5277
5278 if (needs_recompute)
5279 return RETRY;
5280
5281 return setup_ok ? 0 : -EINVAL;
5282 }
5283
5284 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5285 struct intel_crtc_config *pipe_config)
5286 {
5287 pipe_config->ips_enabled = i915.enable_ips &&
5288 hsw_crtc_supports_ips(crtc) &&
5289 pipe_config->pipe_bpp <= 24;
5290 }
5291
5292 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5293 struct intel_crtc_config *pipe_config)
5294 {
5295 struct drm_device *dev = crtc->base.dev;
5296 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5297
5298 /* FIXME should check pixel clock limits on all platforms */
5299 if (INTEL_INFO(dev)->gen < 4) {
5300 struct drm_i915_private *dev_priv = dev->dev_private;
5301 int clock_limit =
5302 dev_priv->display.get_display_clock_speed(dev);
5303
5304 /*
5305 * Enable pixel doubling when the dot clock
5306 * is > 90% of the (display) core speed.
5307 *
5308 * GDG double wide on either pipe,
5309 * otherwise pipe A only.
5310 */
5311 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5312 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5313 clock_limit *= 2;
5314 pipe_config->double_wide = true;
5315 }
5316
5317 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5318 return -EINVAL;
5319 }
5320
5321 /*
5322 * Pipe horizontal size must be even in:
5323 * - DVO ganged mode
5324 * - LVDS dual channel mode
5325 * - Double wide pipe
5326 */
5327 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5328 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5329 pipe_config->pipe_src_w &= ~1;
5330
5331 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5332 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5333 */
5334 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5335 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5336 return -EINVAL;
5337
5338 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5339 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5340 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5341 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5342 * for lvds. */
5343 pipe_config->pipe_bpp = 8*3;
5344 }
5345
5346 if (HAS_IPS(dev))
5347 hsw_compute_ips_config(crtc, pipe_config);
5348
5349 /*
5350 * XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the
5351 * old clock survives for now.
5352 */
5353 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev) || HAS_DDI(dev))
5354 pipe_config->shared_dpll = crtc->config.shared_dpll;
5355
5356 if (pipe_config->has_pch_encoder)
5357 return ironlake_fdi_compute_config(crtc, pipe_config);
5358
5359 return 0;
5360 }
5361
5362 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5363 {
5364 struct drm_i915_private *dev_priv = dev->dev_private;
5365 int vco = valleyview_get_vco(dev_priv);
5366 u32 val;
5367 int divider;
5368
5369 /* FIXME: Punit isn't quite ready yet */
5370 if (IS_CHERRYVIEW(dev))
5371 return 400000;
5372
5373 mutex_lock(&dev_priv->dpio_lock);
5374 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5375 mutex_unlock(&dev_priv->dpio_lock);
5376
5377 divider = val & DISPLAY_FREQUENCY_VALUES;
5378
5379 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5380 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5381 "cdclk change in progress\n");
5382
5383 return DIV_ROUND_CLOSEST(vco << 1, divider + 1);
5384 }
5385
5386 static int i945_get_display_clock_speed(struct drm_device *dev)
5387 {
5388 return 400000;
5389 }
5390
5391 static int i915_get_display_clock_speed(struct drm_device *dev)
5392 {
5393 return 333000;
5394 }
5395
5396 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5397 {
5398 return 200000;
5399 }
5400
5401 static int pnv_get_display_clock_speed(struct drm_device *dev)
5402 {
5403 u16 gcfgc = 0;
5404
5405 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5406
5407 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5408 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5409 return 267000;
5410 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5411 return 333000;
5412 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5413 return 444000;
5414 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5415 return 200000;
5416 default:
5417 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5418 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5419 return 133000;
5420 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5421 return 167000;
5422 }
5423 }
5424
5425 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5426 {
5427 u16 gcfgc = 0;
5428
5429 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5430
5431 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5432 return 133000;
5433 else {
5434 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5435 case GC_DISPLAY_CLOCK_333_MHZ:
5436 return 333000;
5437 default:
5438 case GC_DISPLAY_CLOCK_190_200_MHZ:
5439 return 190000;
5440 }
5441 }
5442 }
5443
5444 static int i865_get_display_clock_speed(struct drm_device *dev)
5445 {
5446 return 266000;
5447 }
5448
5449 static int i855_get_display_clock_speed(struct drm_device *dev)
5450 {
5451 u16 hpllcc = 0;
5452 /* Assume that the hardware is in the high speed state. This
5453 * should be the default.
5454 */
5455 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5456 case GC_CLOCK_133_200:
5457 case GC_CLOCK_100_200:
5458 return 200000;
5459 case GC_CLOCK_166_250:
5460 return 250000;
5461 case GC_CLOCK_100_133:
5462 return 133000;
5463 }
5464
5465 /* Shouldn't happen */
5466 return 0;
5467 }
5468
5469 static int i830_get_display_clock_speed(struct drm_device *dev)
5470 {
5471 return 133000;
5472 }
5473
5474 static void
5475 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5476 {
5477 while (*num > DATA_LINK_M_N_MASK ||
5478 *den > DATA_LINK_M_N_MASK) {
5479 *num >>= 1;
5480 *den >>= 1;
5481 }
5482 }
5483
5484 static void compute_m_n(unsigned int m, unsigned int n,
5485 uint32_t *ret_m, uint32_t *ret_n)
5486 {
5487 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5488 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5489 intel_reduce_m_n_ratio(ret_m, ret_n);
5490 }
5491
5492 void
5493 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5494 int pixel_clock, int link_clock,
5495 struct intel_link_m_n *m_n)
5496 {
5497 m_n->tu = 64;
5498
5499 compute_m_n(bits_per_pixel * pixel_clock,
5500 link_clock * nlanes * 8,
5501 &m_n->gmch_m, &m_n->gmch_n);
5502
5503 compute_m_n(pixel_clock, link_clock,
5504 &m_n->link_m, &m_n->link_n);
5505 }
5506
5507 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5508 {
5509 if (i915.panel_use_ssc >= 0)
5510 return i915.panel_use_ssc != 0;
5511 return dev_priv->vbt.lvds_use_ssc
5512 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5513 }
5514
5515 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5516 {
5517 struct drm_device *dev = crtc->dev;
5518 struct drm_i915_private *dev_priv = dev->dev_private;
5519 int refclk;
5520
5521 if (IS_VALLEYVIEW(dev)) {
5522 refclk = 100000;
5523 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5524 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5525 refclk = dev_priv->vbt.lvds_ssc_freq;
5526 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5527 } else if (!IS_GEN2(dev)) {
5528 refclk = 96000;
5529 } else {
5530 refclk = 48000;
5531 }
5532
5533 return refclk;
5534 }
5535
5536 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5537 {
5538 return (1 << dpll->n) << 16 | dpll->m2;
5539 }
5540
5541 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5542 {
5543 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5544 }
5545
5546 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5547 intel_clock_t *reduced_clock)
5548 {
5549 struct drm_device *dev = crtc->base.dev;
5550 u32 fp, fp2 = 0;
5551
5552 if (IS_PINEVIEW(dev)) {
5553 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5554 if (reduced_clock)
5555 fp2 = pnv_dpll_compute_fp(reduced_clock);
5556 } else {
5557 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5558 if (reduced_clock)
5559 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5560 }
5561
5562 crtc->config.dpll_hw_state.fp0 = fp;
5563
5564 crtc->lowfreq_avail = false;
5565 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5566 reduced_clock && i915.powersave) {
5567 crtc->config.dpll_hw_state.fp1 = fp2;
5568 crtc->lowfreq_avail = true;
5569 } else {
5570 crtc->config.dpll_hw_state.fp1 = fp;
5571 }
5572 }
5573
5574 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5575 pipe)
5576 {
5577 u32 reg_val;
5578
5579 /*
5580 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5581 * and set it to a reasonable value instead.
5582 */
5583 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5584 reg_val &= 0xffffff00;
5585 reg_val |= 0x00000030;
5586 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5587
5588 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5589 reg_val &= 0x8cffffff;
5590 reg_val = 0x8c000000;
5591 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5592
5593 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5594 reg_val &= 0xffffff00;
5595 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5596
5597 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5598 reg_val &= 0x00ffffff;
5599 reg_val |= 0xb0000000;
5600 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5601 }
5602
5603 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5604 struct intel_link_m_n *m_n)
5605 {
5606 struct drm_device *dev = crtc->base.dev;
5607 struct drm_i915_private *dev_priv = dev->dev_private;
5608 int pipe = crtc->pipe;
5609
5610 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5611 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5612 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5613 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5614 }
5615
5616 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5617 struct intel_link_m_n *m_n,
5618 struct intel_link_m_n *m2_n2)
5619 {
5620 struct drm_device *dev = crtc->base.dev;
5621 struct drm_i915_private *dev_priv = dev->dev_private;
5622 int pipe = crtc->pipe;
5623 enum transcoder transcoder = crtc->config.cpu_transcoder;
5624
5625 if (INTEL_INFO(dev)->gen >= 5) {
5626 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5627 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5628 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5629 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5630 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5631 * for gen < 8) and if DRRS is supported (to make sure the
5632 * registers are not unnecessarily accessed).
5633 */
5634 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5635 crtc->config.has_drrs) {
5636 I915_WRITE(PIPE_DATA_M2(transcoder),
5637 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5638 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5639 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5640 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5641 }
5642 } else {
5643 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5644 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5645 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5646 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5647 }
5648 }
5649
5650 void intel_dp_set_m_n(struct intel_crtc *crtc)
5651 {
5652 if (crtc->config.has_pch_encoder)
5653 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5654 else
5655 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n,
5656 &crtc->config.dp_m2_n2);
5657 }
5658
5659 static void vlv_update_pll(struct intel_crtc *crtc)
5660 {
5661 u32 dpll, dpll_md;
5662
5663 /*
5664 * Enable DPIO clock input. We should never disable the reference
5665 * clock for pipe B, since VGA hotplug / manual detection depends
5666 * on it.
5667 */
5668 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5669 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5670 /* We should never disable this, set it here for state tracking */
5671 if (crtc->pipe == PIPE_B)
5672 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5673 dpll |= DPLL_VCO_ENABLE;
5674 crtc->config.dpll_hw_state.dpll = dpll;
5675
5676 dpll_md = (crtc->config.pixel_multiplier - 1)
5677 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5678 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5679 }
5680
5681 static void vlv_prepare_pll(struct intel_crtc *crtc)
5682 {
5683 struct drm_device *dev = crtc->base.dev;
5684 struct drm_i915_private *dev_priv = dev->dev_private;
5685 int pipe = crtc->pipe;
5686 u32 mdiv;
5687 u32 bestn, bestm1, bestm2, bestp1, bestp2;
5688 u32 coreclk, reg_val;
5689
5690 mutex_lock(&dev_priv->dpio_lock);
5691
5692 bestn = crtc->config.dpll.n;
5693 bestm1 = crtc->config.dpll.m1;
5694 bestm2 = crtc->config.dpll.m2;
5695 bestp1 = crtc->config.dpll.p1;
5696 bestp2 = crtc->config.dpll.p2;
5697
5698 /* See eDP HDMI DPIO driver vbios notes doc */
5699
5700 /* PLL B needs special handling */
5701 if (pipe == PIPE_B)
5702 vlv_pllb_recal_opamp(dev_priv, pipe);
5703
5704 /* Set up Tx target for periodic Rcomp update */
5705 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5706
5707 /* Disable target IRef on PLL */
5708 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5709 reg_val &= 0x00ffffff;
5710 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5711
5712 /* Disable fast lock */
5713 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5714
5715 /* Set idtafcrecal before PLL is enabled */
5716 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5717 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5718 mdiv |= ((bestn << DPIO_N_SHIFT));
5719 mdiv |= (1 << DPIO_K_SHIFT);
5720
5721 /*
5722 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5723 * but we don't support that).
5724 * Note: don't use the DAC post divider as it seems unstable.
5725 */
5726 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5727 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5728
5729 mdiv |= DPIO_ENABLE_CALIBRATION;
5730 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5731
5732 /* Set HBR and RBR LPF coefficients */
5733 if (crtc->config.port_clock == 162000 ||
5734 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5735 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5736 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5737 0x009f0003);
5738 else
5739 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5740 0x00d0000f);
5741
5742 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5743 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5744 /* Use SSC source */
5745 if (pipe == PIPE_A)
5746 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5747 0x0df40000);
5748 else
5749 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5750 0x0df70000);
5751 } else { /* HDMI or VGA */
5752 /* Use bend source */
5753 if (pipe == PIPE_A)
5754 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5755 0x0df70000);
5756 else
5757 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5758 0x0df40000);
5759 }
5760
5761 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5762 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5763 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5764 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5765 coreclk |= 0x01000000;
5766 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5767
5768 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5769 mutex_unlock(&dev_priv->dpio_lock);
5770 }
5771
5772 static void chv_update_pll(struct intel_crtc *crtc)
5773 {
5774 crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5775 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5776 DPLL_VCO_ENABLE;
5777 if (crtc->pipe != PIPE_A)
5778 crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5779
5780 crtc->config.dpll_hw_state.dpll_md =
5781 (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5782 }
5783
5784 static void chv_prepare_pll(struct intel_crtc *crtc)
5785 {
5786 struct drm_device *dev = crtc->base.dev;
5787 struct drm_i915_private *dev_priv = dev->dev_private;
5788 int pipe = crtc->pipe;
5789 int dpll_reg = DPLL(crtc->pipe);
5790 enum dpio_channel port = vlv_pipe_to_channel(pipe);
5791 u32 loopfilter, intcoeff;
5792 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5793 int refclk;
5794
5795 bestn = crtc->config.dpll.n;
5796 bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5797 bestm1 = crtc->config.dpll.m1;
5798 bestm2 = crtc->config.dpll.m2 >> 22;
5799 bestp1 = crtc->config.dpll.p1;
5800 bestp2 = crtc->config.dpll.p2;
5801
5802 /*
5803 * Enable Refclk and SSC
5804 */
5805 I915_WRITE(dpll_reg,
5806 crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5807
5808 mutex_lock(&dev_priv->dpio_lock);
5809
5810 /* p1 and p2 divider */
5811 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5812 5 << DPIO_CHV_S1_DIV_SHIFT |
5813 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5814 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5815 1 << DPIO_CHV_K_DIV_SHIFT);
5816
5817 /* Feedback post-divider - m2 */
5818 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5819
5820 /* Feedback refclk divider - n and m1 */
5821 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5822 DPIO_CHV_M1_DIV_BY_2 |
5823 1 << DPIO_CHV_N_DIV_SHIFT);
5824
5825 /* M2 fraction division */
5826 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5827
5828 /* M2 fraction division enable */
5829 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5830 DPIO_CHV_FRAC_DIV_EN |
5831 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5832
5833 /* Loop filter */
5834 refclk = i9xx_get_refclk(&crtc->base, 0);
5835 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5836 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5837 if (refclk == 100000)
5838 intcoeff = 11;
5839 else if (refclk == 38400)
5840 intcoeff = 10;
5841 else
5842 intcoeff = 9;
5843 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5844 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5845
5846 /* AFC Recal */
5847 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5848 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5849 DPIO_AFC_RECAL);
5850
5851 mutex_unlock(&dev_priv->dpio_lock);
5852 }
5853
5854 static void i9xx_update_pll(struct intel_crtc *crtc,
5855 intel_clock_t *reduced_clock,
5856 int num_connectors)
5857 {
5858 struct drm_device *dev = crtc->base.dev;
5859 struct drm_i915_private *dev_priv = dev->dev_private;
5860 u32 dpll;
5861 bool is_sdvo;
5862 struct dpll *clock = &crtc->config.dpll;
5863
5864 i9xx_update_pll_dividers(crtc, reduced_clock);
5865
5866 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5867 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5868
5869 dpll = DPLL_VGA_MODE_DIS;
5870
5871 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5872 dpll |= DPLLB_MODE_LVDS;
5873 else
5874 dpll |= DPLLB_MODE_DAC_SERIAL;
5875
5876 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5877 dpll |= (crtc->config.pixel_multiplier - 1)
5878 << SDVO_MULTIPLIER_SHIFT_HIRES;
5879 }
5880
5881 if (is_sdvo)
5882 dpll |= DPLL_SDVO_HIGH_SPEED;
5883
5884 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5885 dpll |= DPLL_SDVO_HIGH_SPEED;
5886
5887 /* compute bitmask from p1 value */
5888 if (IS_PINEVIEW(dev))
5889 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5890 else {
5891 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5892 if (IS_G4X(dev) && reduced_clock)
5893 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5894 }
5895 switch (clock->p2) {
5896 case 5:
5897 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5898 break;
5899 case 7:
5900 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5901 break;
5902 case 10:
5903 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5904 break;
5905 case 14:
5906 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5907 break;
5908 }
5909 if (INTEL_INFO(dev)->gen >= 4)
5910 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5911
5912 if (crtc->config.sdvo_tv_clock)
5913 dpll |= PLL_REF_INPUT_TVCLKINBC;
5914 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5915 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5916 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5917 else
5918 dpll |= PLL_REF_INPUT_DREFCLK;
5919
5920 dpll |= DPLL_VCO_ENABLE;
5921 crtc->config.dpll_hw_state.dpll = dpll;
5922
5923 if (INTEL_INFO(dev)->gen >= 4) {
5924 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5925 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5926 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5927 }
5928 }
5929
5930 static void i8xx_update_pll(struct intel_crtc *crtc,
5931 intel_clock_t *reduced_clock,
5932 int num_connectors)
5933 {
5934 struct drm_device *dev = crtc->base.dev;
5935 struct drm_i915_private *dev_priv = dev->dev_private;
5936 u32 dpll;
5937 struct dpll *clock = &crtc->config.dpll;
5938
5939 i9xx_update_pll_dividers(crtc, reduced_clock);
5940
5941 dpll = DPLL_VGA_MODE_DIS;
5942
5943 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5944 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5945 } else {
5946 if (clock->p1 == 2)
5947 dpll |= PLL_P1_DIVIDE_BY_TWO;
5948 else
5949 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5950 if (clock->p2 == 4)
5951 dpll |= PLL_P2_DIVIDE_BY_4;
5952 }
5953
5954 if (!IS_I830(dev) && intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5955 dpll |= DPLL_DVO_2X_MODE;
5956
5957 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5958 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5959 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5960 else
5961 dpll |= PLL_REF_INPUT_DREFCLK;
5962
5963 dpll |= DPLL_VCO_ENABLE;
5964 crtc->config.dpll_hw_state.dpll = dpll;
5965 }
5966
5967 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5968 {
5969 struct drm_device *dev = intel_crtc->base.dev;
5970 struct drm_i915_private *dev_priv = dev->dev_private;
5971 enum pipe pipe = intel_crtc->pipe;
5972 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5973 struct drm_display_mode *adjusted_mode =
5974 &intel_crtc->config.adjusted_mode;
5975 uint32_t crtc_vtotal, crtc_vblank_end;
5976 int vsyncshift = 0;
5977
5978 /* We need to be careful not to changed the adjusted mode, for otherwise
5979 * the hw state checker will get angry at the mismatch. */
5980 crtc_vtotal = adjusted_mode->crtc_vtotal;
5981 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5982
5983 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5984 /* the chip adds 2 halflines automatically */
5985 crtc_vtotal -= 1;
5986 crtc_vblank_end -= 1;
5987
5988 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5989 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5990 else
5991 vsyncshift = adjusted_mode->crtc_hsync_start -
5992 adjusted_mode->crtc_htotal / 2;
5993 if (vsyncshift < 0)
5994 vsyncshift += adjusted_mode->crtc_htotal;
5995 }
5996
5997 if (INTEL_INFO(dev)->gen > 3)
5998 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5999
6000 I915_WRITE(HTOTAL(cpu_transcoder),
6001 (adjusted_mode->crtc_hdisplay - 1) |
6002 ((adjusted_mode->crtc_htotal - 1) << 16));
6003 I915_WRITE(HBLANK(cpu_transcoder),
6004 (adjusted_mode->crtc_hblank_start - 1) |
6005 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6006 I915_WRITE(HSYNC(cpu_transcoder),
6007 (adjusted_mode->crtc_hsync_start - 1) |
6008 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6009
6010 I915_WRITE(VTOTAL(cpu_transcoder),
6011 (adjusted_mode->crtc_vdisplay - 1) |
6012 ((crtc_vtotal - 1) << 16));
6013 I915_WRITE(VBLANK(cpu_transcoder),
6014 (adjusted_mode->crtc_vblank_start - 1) |
6015 ((crtc_vblank_end - 1) << 16));
6016 I915_WRITE(VSYNC(cpu_transcoder),
6017 (adjusted_mode->crtc_vsync_start - 1) |
6018 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6019
6020 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6021 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6022 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6023 * bits. */
6024 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6025 (pipe == PIPE_B || pipe == PIPE_C))
6026 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6027
6028 /* pipesrc controls the size that is scaled from, which should
6029 * always be the user's requested size.
6030 */
6031 I915_WRITE(PIPESRC(pipe),
6032 ((intel_crtc->config.pipe_src_w - 1) << 16) |
6033 (intel_crtc->config.pipe_src_h - 1));
6034 }
6035
6036 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6037 struct intel_crtc_config *pipe_config)
6038 {
6039 struct drm_device *dev = crtc->base.dev;
6040 struct drm_i915_private *dev_priv = dev->dev_private;
6041 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6042 uint32_t tmp;
6043
6044 tmp = I915_READ(HTOTAL(cpu_transcoder));
6045 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6046 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6047 tmp = I915_READ(HBLANK(cpu_transcoder));
6048 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6049 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6050 tmp = I915_READ(HSYNC(cpu_transcoder));
6051 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6052 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6053
6054 tmp = I915_READ(VTOTAL(cpu_transcoder));
6055 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6056 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6057 tmp = I915_READ(VBLANK(cpu_transcoder));
6058 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6059 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6060 tmp = I915_READ(VSYNC(cpu_transcoder));
6061 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6062 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6063
6064 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6065 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6066 pipe_config->adjusted_mode.crtc_vtotal += 1;
6067 pipe_config->adjusted_mode.crtc_vblank_end += 1;
6068 }
6069
6070 tmp = I915_READ(PIPESRC(crtc->pipe));
6071 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6072 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6073
6074 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
6075 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
6076 }
6077
6078 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6079 struct intel_crtc_config *pipe_config)
6080 {
6081 mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
6082 mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
6083 mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
6084 mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
6085
6086 mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
6087 mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
6088 mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
6089 mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
6090
6091 mode->flags = pipe_config->adjusted_mode.flags;
6092
6093 mode->clock = pipe_config->adjusted_mode.crtc_clock;
6094 mode->flags |= pipe_config->adjusted_mode.flags;
6095 }
6096
6097 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6098 {
6099 struct drm_device *dev = intel_crtc->base.dev;
6100 struct drm_i915_private *dev_priv = dev->dev_private;
6101 uint32_t pipeconf;
6102
6103 pipeconf = 0;
6104
6105 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6106 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6107 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6108
6109 if (intel_crtc->config.double_wide)
6110 pipeconf |= PIPECONF_DOUBLE_WIDE;
6111
6112 /* only g4x and later have fancy bpc/dither controls */
6113 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6114 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6115 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
6116 pipeconf |= PIPECONF_DITHER_EN |
6117 PIPECONF_DITHER_TYPE_SP;
6118
6119 switch (intel_crtc->config.pipe_bpp) {
6120 case 18:
6121 pipeconf |= PIPECONF_6BPC;
6122 break;
6123 case 24:
6124 pipeconf |= PIPECONF_8BPC;
6125 break;
6126 case 30:
6127 pipeconf |= PIPECONF_10BPC;
6128 break;
6129 default:
6130 /* Case prevented by intel_choose_pipe_bpp_dither. */
6131 BUG();
6132 }
6133 }
6134
6135 if (HAS_PIPE_CXSR(dev)) {
6136 if (intel_crtc->lowfreq_avail) {
6137 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6138 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6139 } else {
6140 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6141 }
6142 }
6143
6144 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6145 if (INTEL_INFO(dev)->gen < 4 ||
6146 intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
6147 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6148 else
6149 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6150 } else
6151 pipeconf |= PIPECONF_PROGRESSIVE;
6152
6153 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6154 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6155
6156 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6157 POSTING_READ(PIPECONF(intel_crtc->pipe));
6158 }
6159
6160 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
6161 int x, int y,
6162 struct drm_framebuffer *fb)
6163 {
6164 struct drm_device *dev = crtc->dev;
6165 struct drm_i915_private *dev_priv = dev->dev_private;
6166 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6167 int refclk, num_connectors = 0;
6168 intel_clock_t clock, reduced_clock;
6169 bool ok, has_reduced_clock = false;
6170 bool is_lvds = false, is_dsi = false;
6171 struct intel_encoder *encoder;
6172 const intel_limit_t *limit;
6173
6174 for_each_encoder_on_crtc(dev, crtc, encoder) {
6175 switch (encoder->type) {
6176 case INTEL_OUTPUT_LVDS:
6177 is_lvds = true;
6178 break;
6179 case INTEL_OUTPUT_DSI:
6180 is_dsi = true;
6181 break;
6182 }
6183
6184 num_connectors++;
6185 }
6186
6187 if (is_dsi)
6188 return 0;
6189
6190 if (!intel_crtc->config.clock_set) {
6191 refclk = i9xx_get_refclk(crtc, num_connectors);
6192
6193 /*
6194 * Returns a set of divisors for the desired target clock with
6195 * the given refclk, or FALSE. The returned values represent
6196 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6197 * 2) / p1 / p2.
6198 */
6199 limit = intel_limit(crtc, refclk);
6200 ok = dev_priv->display.find_dpll(limit, crtc,
6201 intel_crtc->config.port_clock,
6202 refclk, NULL, &clock);
6203 if (!ok) {
6204 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6205 return -EINVAL;
6206 }
6207
6208 if (is_lvds && dev_priv->lvds_downclock_avail) {
6209 /*
6210 * Ensure we match the reduced clock's P to the target
6211 * clock. If the clocks don't match, we can't switch
6212 * the display clock by using the FP0/FP1. In such case
6213 * we will disable the LVDS downclock feature.
6214 */
6215 has_reduced_clock =
6216 dev_priv->display.find_dpll(limit, crtc,
6217 dev_priv->lvds_downclock,
6218 refclk, &clock,
6219 &reduced_clock);
6220 }
6221 /* Compat-code for transition, will disappear. */
6222 intel_crtc->config.dpll.n = clock.n;
6223 intel_crtc->config.dpll.m1 = clock.m1;
6224 intel_crtc->config.dpll.m2 = clock.m2;
6225 intel_crtc->config.dpll.p1 = clock.p1;
6226 intel_crtc->config.dpll.p2 = clock.p2;
6227 }
6228
6229 if (IS_GEN2(dev)) {
6230 i8xx_update_pll(intel_crtc,
6231 has_reduced_clock ? &reduced_clock : NULL,
6232 num_connectors);
6233 } else if (IS_CHERRYVIEW(dev)) {
6234 chv_update_pll(intel_crtc);
6235 } else if (IS_VALLEYVIEW(dev)) {
6236 vlv_update_pll(intel_crtc);
6237 } else {
6238 i9xx_update_pll(intel_crtc,
6239 has_reduced_clock ? &reduced_clock : NULL,
6240 num_connectors);
6241 }
6242
6243 return 0;
6244 }
6245
6246 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6247 struct intel_crtc_config *pipe_config)
6248 {
6249 struct drm_device *dev = crtc->base.dev;
6250 struct drm_i915_private *dev_priv = dev->dev_private;
6251 uint32_t tmp;
6252
6253 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6254 return;
6255
6256 tmp = I915_READ(PFIT_CONTROL);
6257 if (!(tmp & PFIT_ENABLE))
6258 return;
6259
6260 /* Check whether the pfit is attached to our pipe. */
6261 if (INTEL_INFO(dev)->gen < 4) {
6262 if (crtc->pipe != PIPE_B)
6263 return;
6264 } else {
6265 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6266 return;
6267 }
6268
6269 pipe_config->gmch_pfit.control = tmp;
6270 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6271 if (INTEL_INFO(dev)->gen < 5)
6272 pipe_config->gmch_pfit.lvds_border_bits =
6273 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6274 }
6275
6276 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6277 struct intel_crtc_config *pipe_config)
6278 {
6279 struct drm_device *dev = crtc->base.dev;
6280 struct drm_i915_private *dev_priv = dev->dev_private;
6281 int pipe = pipe_config->cpu_transcoder;
6282 intel_clock_t clock;
6283 u32 mdiv;
6284 int refclk = 100000;
6285
6286 /* In case of MIPI DPLL will not even be used */
6287 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6288 return;
6289
6290 mutex_lock(&dev_priv->dpio_lock);
6291 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6292 mutex_unlock(&dev_priv->dpio_lock);
6293
6294 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6295 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6296 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6297 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6298 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6299
6300 vlv_clock(refclk, &clock);
6301
6302 /* clock.dot is the fast clock */
6303 pipe_config->port_clock = clock.dot / 5;
6304 }
6305
6306 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6307 struct intel_plane_config *plane_config)
6308 {
6309 struct drm_device *dev = crtc->base.dev;
6310 struct drm_i915_private *dev_priv = dev->dev_private;
6311 u32 val, base, offset;
6312 int pipe = crtc->pipe, plane = crtc->plane;
6313 int fourcc, pixel_format;
6314 int aligned_height;
6315
6316 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6317 if (!crtc->base.primary->fb) {
6318 DRM_DEBUG_KMS("failed to alloc fb\n");
6319 return;
6320 }
6321
6322 val = I915_READ(DSPCNTR(plane));
6323
6324 if (INTEL_INFO(dev)->gen >= 4)
6325 if (val & DISPPLANE_TILED)
6326 plane_config->tiled = true;
6327
6328 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6329 fourcc = intel_format_to_fourcc(pixel_format);
6330 crtc->base.primary->fb->pixel_format = fourcc;
6331 crtc->base.primary->fb->bits_per_pixel =
6332 drm_format_plane_cpp(fourcc, 0) * 8;
6333
6334 if (INTEL_INFO(dev)->gen >= 4) {
6335 if (plane_config->tiled)
6336 offset = I915_READ(DSPTILEOFF(plane));
6337 else
6338 offset = I915_READ(DSPLINOFF(plane));
6339 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6340 } else {
6341 base = I915_READ(DSPADDR(plane));
6342 }
6343 plane_config->base = base;
6344
6345 val = I915_READ(PIPESRC(pipe));
6346 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6347 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6348
6349 val = I915_READ(DSPSTRIDE(pipe));
6350 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
6351
6352 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6353 plane_config->tiled);
6354
6355 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6356 aligned_height);
6357
6358 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6359 pipe, plane, crtc->base.primary->fb->width,
6360 crtc->base.primary->fb->height,
6361 crtc->base.primary->fb->bits_per_pixel, base,
6362 crtc->base.primary->fb->pitches[0],
6363 plane_config->size);
6364
6365 }
6366
6367 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6368 struct intel_crtc_config *pipe_config)
6369 {
6370 struct drm_device *dev = crtc->base.dev;
6371 struct drm_i915_private *dev_priv = dev->dev_private;
6372 int pipe = pipe_config->cpu_transcoder;
6373 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6374 intel_clock_t clock;
6375 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6376 int refclk = 100000;
6377
6378 mutex_lock(&dev_priv->dpio_lock);
6379 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6380 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6381 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6382 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6383 mutex_unlock(&dev_priv->dpio_lock);
6384
6385 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6386 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6387 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6388 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6389 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6390
6391 chv_clock(refclk, &clock);
6392
6393 /* clock.dot is the fast clock */
6394 pipe_config->port_clock = clock.dot / 5;
6395 }
6396
6397 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6398 struct intel_crtc_config *pipe_config)
6399 {
6400 struct drm_device *dev = crtc->base.dev;
6401 struct drm_i915_private *dev_priv = dev->dev_private;
6402 uint32_t tmp;
6403
6404 if (!intel_display_power_enabled(dev_priv,
6405 POWER_DOMAIN_PIPE(crtc->pipe)))
6406 return false;
6407
6408 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6409 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6410
6411 tmp = I915_READ(PIPECONF(crtc->pipe));
6412 if (!(tmp & PIPECONF_ENABLE))
6413 return false;
6414
6415 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6416 switch (tmp & PIPECONF_BPC_MASK) {
6417 case PIPECONF_6BPC:
6418 pipe_config->pipe_bpp = 18;
6419 break;
6420 case PIPECONF_8BPC:
6421 pipe_config->pipe_bpp = 24;
6422 break;
6423 case PIPECONF_10BPC:
6424 pipe_config->pipe_bpp = 30;
6425 break;
6426 default:
6427 break;
6428 }
6429 }
6430
6431 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6432 pipe_config->limited_color_range = true;
6433
6434 if (INTEL_INFO(dev)->gen < 4)
6435 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6436
6437 intel_get_pipe_timings(crtc, pipe_config);
6438
6439 i9xx_get_pfit_config(crtc, pipe_config);
6440
6441 if (INTEL_INFO(dev)->gen >= 4) {
6442 tmp = I915_READ(DPLL_MD(crtc->pipe));
6443 pipe_config->pixel_multiplier =
6444 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6445 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6446 pipe_config->dpll_hw_state.dpll_md = tmp;
6447 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6448 tmp = I915_READ(DPLL(crtc->pipe));
6449 pipe_config->pixel_multiplier =
6450 ((tmp & SDVO_MULTIPLIER_MASK)
6451 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6452 } else {
6453 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6454 * port and will be fixed up in the encoder->get_config
6455 * function. */
6456 pipe_config->pixel_multiplier = 1;
6457 }
6458 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6459 if (!IS_VALLEYVIEW(dev)) {
6460 /*
6461 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6462 * on 830. Filter it out here so that we don't
6463 * report errors due to that.
6464 */
6465 if (IS_I830(dev))
6466 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6467
6468 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6469 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6470 } else {
6471 /* Mask out read-only status bits. */
6472 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6473 DPLL_PORTC_READY_MASK |
6474 DPLL_PORTB_READY_MASK);
6475 }
6476
6477 if (IS_CHERRYVIEW(dev))
6478 chv_crtc_clock_get(crtc, pipe_config);
6479 else if (IS_VALLEYVIEW(dev))
6480 vlv_crtc_clock_get(crtc, pipe_config);
6481 else
6482 i9xx_crtc_clock_get(crtc, pipe_config);
6483
6484 return true;
6485 }
6486
6487 static void ironlake_init_pch_refclk(struct drm_device *dev)
6488 {
6489 struct drm_i915_private *dev_priv = dev->dev_private;
6490 struct intel_encoder *encoder;
6491 u32 val, final;
6492 bool has_lvds = false;
6493 bool has_cpu_edp = false;
6494 bool has_panel = false;
6495 bool has_ck505 = false;
6496 bool can_ssc = false;
6497
6498 /* We need to take the global config into account */
6499 for_each_intel_encoder(dev, encoder) {
6500 switch (encoder->type) {
6501 case INTEL_OUTPUT_LVDS:
6502 has_panel = true;
6503 has_lvds = true;
6504 break;
6505 case INTEL_OUTPUT_EDP:
6506 has_panel = true;
6507 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6508 has_cpu_edp = true;
6509 break;
6510 }
6511 }
6512
6513 if (HAS_PCH_IBX(dev)) {
6514 has_ck505 = dev_priv->vbt.display_clock_mode;
6515 can_ssc = has_ck505;
6516 } else {
6517 has_ck505 = false;
6518 can_ssc = true;
6519 }
6520
6521 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6522 has_panel, has_lvds, has_ck505);
6523
6524 /* Ironlake: try to setup display ref clock before DPLL
6525 * enabling. This is only under driver's control after
6526 * PCH B stepping, previous chipset stepping should be
6527 * ignoring this setting.
6528 */
6529 val = I915_READ(PCH_DREF_CONTROL);
6530
6531 /* As we must carefully and slowly disable/enable each source in turn,
6532 * compute the final state we want first and check if we need to
6533 * make any changes at all.
6534 */
6535 final = val;
6536 final &= ~DREF_NONSPREAD_SOURCE_MASK;
6537 if (has_ck505)
6538 final |= DREF_NONSPREAD_CK505_ENABLE;
6539 else
6540 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6541
6542 final &= ~DREF_SSC_SOURCE_MASK;
6543 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6544 final &= ~DREF_SSC1_ENABLE;
6545
6546 if (has_panel) {
6547 final |= DREF_SSC_SOURCE_ENABLE;
6548
6549 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6550 final |= DREF_SSC1_ENABLE;
6551
6552 if (has_cpu_edp) {
6553 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6554 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6555 else
6556 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6557 } else
6558 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6559 } else {
6560 final |= DREF_SSC_SOURCE_DISABLE;
6561 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6562 }
6563
6564 if (final == val)
6565 return;
6566
6567 /* Always enable nonspread source */
6568 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6569
6570 if (has_ck505)
6571 val |= DREF_NONSPREAD_CK505_ENABLE;
6572 else
6573 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6574
6575 if (has_panel) {
6576 val &= ~DREF_SSC_SOURCE_MASK;
6577 val |= DREF_SSC_SOURCE_ENABLE;
6578
6579 /* SSC must be turned on before enabling the CPU output */
6580 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6581 DRM_DEBUG_KMS("Using SSC on panel\n");
6582 val |= DREF_SSC1_ENABLE;
6583 } else
6584 val &= ~DREF_SSC1_ENABLE;
6585
6586 /* Get SSC going before enabling the outputs */
6587 I915_WRITE(PCH_DREF_CONTROL, val);
6588 POSTING_READ(PCH_DREF_CONTROL);
6589 udelay(200);
6590
6591 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6592
6593 /* Enable CPU source on CPU attached eDP */
6594 if (has_cpu_edp) {
6595 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6596 DRM_DEBUG_KMS("Using SSC on eDP\n");
6597 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6598 } else
6599 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6600 } else
6601 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6602
6603 I915_WRITE(PCH_DREF_CONTROL, val);
6604 POSTING_READ(PCH_DREF_CONTROL);
6605 udelay(200);
6606 } else {
6607 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6608
6609 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6610
6611 /* Turn off CPU output */
6612 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6613
6614 I915_WRITE(PCH_DREF_CONTROL, val);
6615 POSTING_READ(PCH_DREF_CONTROL);
6616 udelay(200);
6617
6618 /* Turn off the SSC source */
6619 val &= ~DREF_SSC_SOURCE_MASK;
6620 val |= DREF_SSC_SOURCE_DISABLE;
6621
6622 /* Turn off SSC1 */
6623 val &= ~DREF_SSC1_ENABLE;
6624
6625 I915_WRITE(PCH_DREF_CONTROL, val);
6626 POSTING_READ(PCH_DREF_CONTROL);
6627 udelay(200);
6628 }
6629
6630 BUG_ON(val != final);
6631 }
6632
6633 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6634 {
6635 uint32_t tmp;
6636
6637 tmp = I915_READ(SOUTH_CHICKEN2);
6638 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6639 I915_WRITE(SOUTH_CHICKEN2, tmp);
6640
6641 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6642 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6643 DRM_ERROR("FDI mPHY reset assert timeout\n");
6644
6645 tmp = I915_READ(SOUTH_CHICKEN2);
6646 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6647 I915_WRITE(SOUTH_CHICKEN2, tmp);
6648
6649 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6650 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6651 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6652 }
6653
6654 /* WaMPhyProgramming:hsw */
6655 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6656 {
6657 uint32_t tmp;
6658
6659 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6660 tmp &= ~(0xFF << 24);
6661 tmp |= (0x12 << 24);
6662 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6663
6664 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6665 tmp |= (1 << 11);
6666 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6667
6668 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6669 tmp |= (1 << 11);
6670 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6671
6672 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6673 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6674 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6675
6676 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6677 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6678 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6679
6680 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6681 tmp &= ~(7 << 13);
6682 tmp |= (5 << 13);
6683 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6684
6685 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6686 tmp &= ~(7 << 13);
6687 tmp |= (5 << 13);
6688 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6689
6690 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6691 tmp &= ~0xFF;
6692 tmp |= 0x1C;
6693 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6694
6695 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6696 tmp &= ~0xFF;
6697 tmp |= 0x1C;
6698 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6699
6700 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6701 tmp &= ~(0xFF << 16);
6702 tmp |= (0x1C << 16);
6703 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6704
6705 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6706 tmp &= ~(0xFF << 16);
6707 tmp |= (0x1C << 16);
6708 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6709
6710 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6711 tmp |= (1 << 27);
6712 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6713
6714 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6715 tmp |= (1 << 27);
6716 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6717
6718 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6719 tmp &= ~(0xF << 28);
6720 tmp |= (4 << 28);
6721 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6722
6723 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6724 tmp &= ~(0xF << 28);
6725 tmp |= (4 << 28);
6726 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6727 }
6728
6729 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6730 * Programming" based on the parameters passed:
6731 * - Sequence to enable CLKOUT_DP
6732 * - Sequence to enable CLKOUT_DP without spread
6733 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6734 */
6735 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6736 bool with_fdi)
6737 {
6738 struct drm_i915_private *dev_priv = dev->dev_private;
6739 uint32_t reg, tmp;
6740
6741 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6742 with_spread = true;
6743 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6744 with_fdi, "LP PCH doesn't have FDI\n"))
6745 with_fdi = false;
6746
6747 mutex_lock(&dev_priv->dpio_lock);
6748
6749 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6750 tmp &= ~SBI_SSCCTL_DISABLE;
6751 tmp |= SBI_SSCCTL_PATHALT;
6752 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6753
6754 udelay(24);
6755
6756 if (with_spread) {
6757 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6758 tmp &= ~SBI_SSCCTL_PATHALT;
6759 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6760
6761 if (with_fdi) {
6762 lpt_reset_fdi_mphy(dev_priv);
6763 lpt_program_fdi_mphy(dev_priv);
6764 }
6765 }
6766
6767 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6768 SBI_GEN0 : SBI_DBUFF0;
6769 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6770 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6771 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6772
6773 mutex_unlock(&dev_priv->dpio_lock);
6774 }
6775
6776 /* Sequence to disable CLKOUT_DP */
6777 static void lpt_disable_clkout_dp(struct drm_device *dev)
6778 {
6779 struct drm_i915_private *dev_priv = dev->dev_private;
6780 uint32_t reg, tmp;
6781
6782 mutex_lock(&dev_priv->dpio_lock);
6783
6784 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6785 SBI_GEN0 : SBI_DBUFF0;
6786 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6787 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6788 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6789
6790 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6791 if (!(tmp & SBI_SSCCTL_DISABLE)) {
6792 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6793 tmp |= SBI_SSCCTL_PATHALT;
6794 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6795 udelay(32);
6796 }
6797 tmp |= SBI_SSCCTL_DISABLE;
6798 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6799 }
6800
6801 mutex_unlock(&dev_priv->dpio_lock);
6802 }
6803
6804 static void lpt_init_pch_refclk(struct drm_device *dev)
6805 {
6806 struct intel_encoder *encoder;
6807 bool has_vga = false;
6808
6809 for_each_intel_encoder(dev, encoder) {
6810 switch (encoder->type) {
6811 case INTEL_OUTPUT_ANALOG:
6812 has_vga = true;
6813 break;
6814 }
6815 }
6816
6817 if (has_vga)
6818 lpt_enable_clkout_dp(dev, true, true);
6819 else
6820 lpt_disable_clkout_dp(dev);
6821 }
6822
6823 /*
6824 * Initialize reference clocks when the driver loads
6825 */
6826 void intel_init_pch_refclk(struct drm_device *dev)
6827 {
6828 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6829 ironlake_init_pch_refclk(dev);
6830 else if (HAS_PCH_LPT(dev))
6831 lpt_init_pch_refclk(dev);
6832 }
6833
6834 static int ironlake_get_refclk(struct drm_crtc *crtc)
6835 {
6836 struct drm_device *dev = crtc->dev;
6837 struct drm_i915_private *dev_priv = dev->dev_private;
6838 struct intel_encoder *encoder;
6839 int num_connectors = 0;
6840 bool is_lvds = false;
6841
6842 for_each_encoder_on_crtc(dev, crtc, encoder) {
6843 switch (encoder->type) {
6844 case INTEL_OUTPUT_LVDS:
6845 is_lvds = true;
6846 break;
6847 }
6848 num_connectors++;
6849 }
6850
6851 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6852 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6853 dev_priv->vbt.lvds_ssc_freq);
6854 return dev_priv->vbt.lvds_ssc_freq;
6855 }
6856
6857 return 120000;
6858 }
6859
6860 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6861 {
6862 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6863 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6864 int pipe = intel_crtc->pipe;
6865 uint32_t val;
6866
6867 val = 0;
6868
6869 switch (intel_crtc->config.pipe_bpp) {
6870 case 18:
6871 val |= PIPECONF_6BPC;
6872 break;
6873 case 24:
6874 val |= PIPECONF_8BPC;
6875 break;
6876 case 30:
6877 val |= PIPECONF_10BPC;
6878 break;
6879 case 36:
6880 val |= PIPECONF_12BPC;
6881 break;
6882 default:
6883 /* Case prevented by intel_choose_pipe_bpp_dither. */
6884 BUG();
6885 }
6886
6887 if (intel_crtc->config.dither)
6888 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6889
6890 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6891 val |= PIPECONF_INTERLACED_ILK;
6892 else
6893 val |= PIPECONF_PROGRESSIVE;
6894
6895 if (intel_crtc->config.limited_color_range)
6896 val |= PIPECONF_COLOR_RANGE_SELECT;
6897
6898 I915_WRITE(PIPECONF(pipe), val);
6899 POSTING_READ(PIPECONF(pipe));
6900 }
6901
6902 /*
6903 * Set up the pipe CSC unit.
6904 *
6905 * Currently only full range RGB to limited range RGB conversion
6906 * is supported, but eventually this should handle various
6907 * RGB<->YCbCr scenarios as well.
6908 */
6909 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6910 {
6911 struct drm_device *dev = crtc->dev;
6912 struct drm_i915_private *dev_priv = dev->dev_private;
6913 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6914 int pipe = intel_crtc->pipe;
6915 uint16_t coeff = 0x7800; /* 1.0 */
6916
6917 /*
6918 * TODO: Check what kind of values actually come out of the pipe
6919 * with these coeff/postoff values and adjust to get the best
6920 * accuracy. Perhaps we even need to take the bpc value into
6921 * consideration.
6922 */
6923
6924 if (intel_crtc->config.limited_color_range)
6925 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6926
6927 /*
6928 * GY/GU and RY/RU should be the other way around according
6929 * to BSpec, but reality doesn't agree. Just set them up in
6930 * a way that results in the correct picture.
6931 */
6932 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6933 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6934
6935 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6936 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6937
6938 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6939 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6940
6941 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6942 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6943 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6944
6945 if (INTEL_INFO(dev)->gen > 6) {
6946 uint16_t postoff = 0;
6947
6948 if (intel_crtc->config.limited_color_range)
6949 postoff = (16 * (1 << 12) / 255) & 0x1fff;
6950
6951 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6952 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6953 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6954
6955 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6956 } else {
6957 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6958
6959 if (intel_crtc->config.limited_color_range)
6960 mode |= CSC_BLACK_SCREEN_OFFSET;
6961
6962 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6963 }
6964 }
6965
6966 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6967 {
6968 struct drm_device *dev = crtc->dev;
6969 struct drm_i915_private *dev_priv = dev->dev_private;
6970 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6971 enum pipe pipe = intel_crtc->pipe;
6972 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6973 uint32_t val;
6974
6975 val = 0;
6976
6977 if (IS_HASWELL(dev) && intel_crtc->config.dither)
6978 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6979
6980 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6981 val |= PIPECONF_INTERLACED_ILK;
6982 else
6983 val |= PIPECONF_PROGRESSIVE;
6984
6985 I915_WRITE(PIPECONF(cpu_transcoder), val);
6986 POSTING_READ(PIPECONF(cpu_transcoder));
6987
6988 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6989 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6990
6991 if (IS_BROADWELL(dev)) {
6992 val = 0;
6993
6994 switch (intel_crtc->config.pipe_bpp) {
6995 case 18:
6996 val |= PIPEMISC_DITHER_6_BPC;
6997 break;
6998 case 24:
6999 val |= PIPEMISC_DITHER_8_BPC;
7000 break;
7001 case 30:
7002 val |= PIPEMISC_DITHER_10_BPC;
7003 break;
7004 case 36:
7005 val |= PIPEMISC_DITHER_12_BPC;
7006 break;
7007 default:
7008 /* Case prevented by pipe_config_set_bpp. */
7009 BUG();
7010 }
7011
7012 if (intel_crtc->config.dither)
7013 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7014
7015 I915_WRITE(PIPEMISC(pipe), val);
7016 }
7017 }
7018
7019 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7020 intel_clock_t *clock,
7021 bool *has_reduced_clock,
7022 intel_clock_t *reduced_clock)
7023 {
7024 struct drm_device *dev = crtc->dev;
7025 struct drm_i915_private *dev_priv = dev->dev_private;
7026 struct intel_encoder *intel_encoder;
7027 int refclk;
7028 const intel_limit_t *limit;
7029 bool ret, is_lvds = false;
7030
7031 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
7032 switch (intel_encoder->type) {
7033 case INTEL_OUTPUT_LVDS:
7034 is_lvds = true;
7035 break;
7036 }
7037 }
7038
7039 refclk = ironlake_get_refclk(crtc);
7040
7041 /*
7042 * Returns a set of divisors for the desired target clock with the given
7043 * refclk, or FALSE. The returned values represent the clock equation:
7044 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7045 */
7046 limit = intel_limit(crtc, refclk);
7047 ret = dev_priv->display.find_dpll(limit, crtc,
7048 to_intel_crtc(crtc)->config.port_clock,
7049 refclk, NULL, clock);
7050 if (!ret)
7051 return false;
7052
7053 if (is_lvds && dev_priv->lvds_downclock_avail) {
7054 /*
7055 * Ensure we match the reduced clock's P to the target clock.
7056 * If the clocks don't match, we can't switch the display clock
7057 * by using the FP0/FP1. In such case we will disable the LVDS
7058 * downclock feature.
7059 */
7060 *has_reduced_clock =
7061 dev_priv->display.find_dpll(limit, crtc,
7062 dev_priv->lvds_downclock,
7063 refclk, clock,
7064 reduced_clock);
7065 }
7066
7067 return true;
7068 }
7069
7070 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7071 {
7072 /*
7073 * Account for spread spectrum to avoid
7074 * oversubscribing the link. Max center spread
7075 * is 2.5%; use 5% for safety's sake.
7076 */
7077 u32 bps = target_clock * bpp * 21 / 20;
7078 return DIV_ROUND_UP(bps, link_bw * 8);
7079 }
7080
7081 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7082 {
7083 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7084 }
7085
7086 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7087 u32 *fp,
7088 intel_clock_t *reduced_clock, u32 *fp2)
7089 {
7090 struct drm_crtc *crtc = &intel_crtc->base;
7091 struct drm_device *dev = crtc->dev;
7092 struct drm_i915_private *dev_priv = dev->dev_private;
7093 struct intel_encoder *intel_encoder;
7094 uint32_t dpll;
7095 int factor, num_connectors = 0;
7096 bool is_lvds = false, is_sdvo = false;
7097
7098 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
7099 switch (intel_encoder->type) {
7100 case INTEL_OUTPUT_LVDS:
7101 is_lvds = true;
7102 break;
7103 case INTEL_OUTPUT_SDVO:
7104 case INTEL_OUTPUT_HDMI:
7105 is_sdvo = true;
7106 break;
7107 }
7108
7109 num_connectors++;
7110 }
7111
7112 /* Enable autotuning of the PLL clock (if permissible) */
7113 factor = 21;
7114 if (is_lvds) {
7115 if ((intel_panel_use_ssc(dev_priv) &&
7116 dev_priv->vbt.lvds_ssc_freq == 100000) ||
7117 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7118 factor = 25;
7119 } else if (intel_crtc->config.sdvo_tv_clock)
7120 factor = 20;
7121
7122 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7123 *fp |= FP_CB_TUNE;
7124
7125 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7126 *fp2 |= FP_CB_TUNE;
7127
7128 dpll = 0;
7129
7130 if (is_lvds)
7131 dpll |= DPLLB_MODE_LVDS;
7132 else
7133 dpll |= DPLLB_MODE_DAC_SERIAL;
7134
7135 dpll |= (intel_crtc->config.pixel_multiplier - 1)
7136 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7137
7138 if (is_sdvo)
7139 dpll |= DPLL_SDVO_HIGH_SPEED;
7140 if (intel_crtc->config.has_dp_encoder)
7141 dpll |= DPLL_SDVO_HIGH_SPEED;
7142
7143 /* compute bitmask from p1 value */
7144 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7145 /* also FPA1 */
7146 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7147
7148 switch (intel_crtc->config.dpll.p2) {
7149 case 5:
7150 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7151 break;
7152 case 7:
7153 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7154 break;
7155 case 10:
7156 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7157 break;
7158 case 14:
7159 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7160 break;
7161 }
7162
7163 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7164 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7165 else
7166 dpll |= PLL_REF_INPUT_DREFCLK;
7167
7168 return dpll | DPLL_VCO_ENABLE;
7169 }
7170
7171 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
7172 int x, int y,
7173 struct drm_framebuffer *fb)
7174 {
7175 struct drm_device *dev = crtc->dev;
7176 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7177 int num_connectors = 0;
7178 intel_clock_t clock, reduced_clock;
7179 u32 dpll = 0, fp = 0, fp2 = 0;
7180 bool ok, has_reduced_clock = false;
7181 bool is_lvds = false;
7182 struct intel_encoder *encoder;
7183 struct intel_shared_dpll *pll;
7184
7185 for_each_encoder_on_crtc(dev, crtc, encoder) {
7186 switch (encoder->type) {
7187 case INTEL_OUTPUT_LVDS:
7188 is_lvds = true;
7189 break;
7190 }
7191
7192 num_connectors++;
7193 }
7194
7195 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7196 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7197
7198 ok = ironlake_compute_clocks(crtc, &clock,
7199 &has_reduced_clock, &reduced_clock);
7200 if (!ok && !intel_crtc->config.clock_set) {
7201 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7202 return -EINVAL;
7203 }
7204 /* Compat-code for transition, will disappear. */
7205 if (!intel_crtc->config.clock_set) {
7206 intel_crtc->config.dpll.n = clock.n;
7207 intel_crtc->config.dpll.m1 = clock.m1;
7208 intel_crtc->config.dpll.m2 = clock.m2;
7209 intel_crtc->config.dpll.p1 = clock.p1;
7210 intel_crtc->config.dpll.p2 = clock.p2;
7211 }
7212
7213 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7214 if (intel_crtc->config.has_pch_encoder) {
7215 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
7216 if (has_reduced_clock)
7217 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7218
7219 dpll = ironlake_compute_dpll(intel_crtc,
7220 &fp, &reduced_clock,
7221 has_reduced_clock ? &fp2 : NULL);
7222
7223 intel_crtc->config.dpll_hw_state.dpll = dpll;
7224 intel_crtc->config.dpll_hw_state.fp0 = fp;
7225 if (has_reduced_clock)
7226 intel_crtc->config.dpll_hw_state.fp1 = fp2;
7227 else
7228 intel_crtc->config.dpll_hw_state.fp1 = fp;
7229
7230 pll = intel_get_shared_dpll(intel_crtc);
7231 if (pll == NULL) {
7232 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7233 pipe_name(intel_crtc->pipe));
7234 return -EINVAL;
7235 }
7236 } else
7237 intel_put_shared_dpll(intel_crtc);
7238
7239 if (is_lvds && has_reduced_clock && i915.powersave)
7240 intel_crtc->lowfreq_avail = true;
7241 else
7242 intel_crtc->lowfreq_avail = false;
7243
7244 return 0;
7245 }
7246
7247 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7248 struct intel_link_m_n *m_n)
7249 {
7250 struct drm_device *dev = crtc->base.dev;
7251 struct drm_i915_private *dev_priv = dev->dev_private;
7252 enum pipe pipe = crtc->pipe;
7253
7254 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7255 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7256 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7257 & ~TU_SIZE_MASK;
7258 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7259 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7260 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7261 }
7262
7263 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7264 enum transcoder transcoder,
7265 struct intel_link_m_n *m_n,
7266 struct intel_link_m_n *m2_n2)
7267 {
7268 struct drm_device *dev = crtc->base.dev;
7269 struct drm_i915_private *dev_priv = dev->dev_private;
7270 enum pipe pipe = crtc->pipe;
7271
7272 if (INTEL_INFO(dev)->gen >= 5) {
7273 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7274 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7275 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7276 & ~TU_SIZE_MASK;
7277 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7278 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7279 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7280 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7281 * gen < 8) and if DRRS is supported (to make sure the
7282 * registers are not unnecessarily read).
7283 */
7284 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7285 crtc->config.has_drrs) {
7286 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7287 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7288 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7289 & ~TU_SIZE_MASK;
7290 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7291 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7292 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7293 }
7294 } else {
7295 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7296 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7297 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7298 & ~TU_SIZE_MASK;
7299 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7300 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7301 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7302 }
7303 }
7304
7305 void intel_dp_get_m_n(struct intel_crtc *crtc,
7306 struct intel_crtc_config *pipe_config)
7307 {
7308 if (crtc->config.has_pch_encoder)
7309 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7310 else
7311 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7312 &pipe_config->dp_m_n,
7313 &pipe_config->dp_m2_n2);
7314 }
7315
7316 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7317 struct intel_crtc_config *pipe_config)
7318 {
7319 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7320 &pipe_config->fdi_m_n, NULL);
7321 }
7322
7323 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7324 struct intel_crtc_config *pipe_config)
7325 {
7326 struct drm_device *dev = crtc->base.dev;
7327 struct drm_i915_private *dev_priv = dev->dev_private;
7328 uint32_t tmp;
7329
7330 tmp = I915_READ(PF_CTL(crtc->pipe));
7331
7332 if (tmp & PF_ENABLE) {
7333 pipe_config->pch_pfit.enabled = true;
7334 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7335 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7336
7337 /* We currently do not free assignements of panel fitters on
7338 * ivb/hsw (since we don't use the higher upscaling modes which
7339 * differentiates them) so just WARN about this case for now. */
7340 if (IS_GEN7(dev)) {
7341 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7342 PF_PIPE_SEL_IVB(crtc->pipe));
7343 }
7344 }
7345 }
7346
7347 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7348 struct intel_plane_config *plane_config)
7349 {
7350 struct drm_device *dev = crtc->base.dev;
7351 struct drm_i915_private *dev_priv = dev->dev_private;
7352 u32 val, base, offset;
7353 int pipe = crtc->pipe, plane = crtc->plane;
7354 int fourcc, pixel_format;
7355 int aligned_height;
7356
7357 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7358 if (!crtc->base.primary->fb) {
7359 DRM_DEBUG_KMS("failed to alloc fb\n");
7360 return;
7361 }
7362
7363 val = I915_READ(DSPCNTR(plane));
7364
7365 if (INTEL_INFO(dev)->gen >= 4)
7366 if (val & DISPPLANE_TILED)
7367 plane_config->tiled = true;
7368
7369 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7370 fourcc = intel_format_to_fourcc(pixel_format);
7371 crtc->base.primary->fb->pixel_format = fourcc;
7372 crtc->base.primary->fb->bits_per_pixel =
7373 drm_format_plane_cpp(fourcc, 0) * 8;
7374
7375 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7376 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7377 offset = I915_READ(DSPOFFSET(plane));
7378 } else {
7379 if (plane_config->tiled)
7380 offset = I915_READ(DSPTILEOFF(plane));
7381 else
7382 offset = I915_READ(DSPLINOFF(plane));
7383 }
7384 plane_config->base = base;
7385
7386 val = I915_READ(PIPESRC(pipe));
7387 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7388 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7389
7390 val = I915_READ(DSPSTRIDE(pipe));
7391 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
7392
7393 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7394 plane_config->tiled);
7395
7396 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7397 aligned_height);
7398
7399 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7400 pipe, plane, crtc->base.primary->fb->width,
7401 crtc->base.primary->fb->height,
7402 crtc->base.primary->fb->bits_per_pixel, base,
7403 crtc->base.primary->fb->pitches[0],
7404 plane_config->size);
7405 }
7406
7407 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7408 struct intel_crtc_config *pipe_config)
7409 {
7410 struct drm_device *dev = crtc->base.dev;
7411 struct drm_i915_private *dev_priv = dev->dev_private;
7412 uint32_t tmp;
7413
7414 if (!intel_display_power_enabled(dev_priv,
7415 POWER_DOMAIN_PIPE(crtc->pipe)))
7416 return false;
7417
7418 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7419 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7420
7421 tmp = I915_READ(PIPECONF(crtc->pipe));
7422 if (!(tmp & PIPECONF_ENABLE))
7423 return false;
7424
7425 switch (tmp & PIPECONF_BPC_MASK) {
7426 case PIPECONF_6BPC:
7427 pipe_config->pipe_bpp = 18;
7428 break;
7429 case PIPECONF_8BPC:
7430 pipe_config->pipe_bpp = 24;
7431 break;
7432 case PIPECONF_10BPC:
7433 pipe_config->pipe_bpp = 30;
7434 break;
7435 case PIPECONF_12BPC:
7436 pipe_config->pipe_bpp = 36;
7437 break;
7438 default:
7439 break;
7440 }
7441
7442 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7443 pipe_config->limited_color_range = true;
7444
7445 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7446 struct intel_shared_dpll *pll;
7447
7448 pipe_config->has_pch_encoder = true;
7449
7450 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7451 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7452 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7453
7454 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7455
7456 if (HAS_PCH_IBX(dev_priv->dev)) {
7457 pipe_config->shared_dpll =
7458 (enum intel_dpll_id) crtc->pipe;
7459 } else {
7460 tmp = I915_READ(PCH_DPLL_SEL);
7461 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7462 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7463 else
7464 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7465 }
7466
7467 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7468
7469 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7470 &pipe_config->dpll_hw_state));
7471
7472 tmp = pipe_config->dpll_hw_state.dpll;
7473 pipe_config->pixel_multiplier =
7474 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7475 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7476
7477 ironlake_pch_clock_get(crtc, pipe_config);
7478 } else {
7479 pipe_config->pixel_multiplier = 1;
7480 }
7481
7482 intel_get_pipe_timings(crtc, pipe_config);
7483
7484 ironlake_get_pfit_config(crtc, pipe_config);
7485
7486 return true;
7487 }
7488
7489 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7490 {
7491 struct drm_device *dev = dev_priv->dev;
7492 struct intel_crtc *crtc;
7493
7494 for_each_intel_crtc(dev, crtc)
7495 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7496 pipe_name(crtc->pipe));
7497
7498 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7499 WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7500 WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7501 WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7502 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7503 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7504 "CPU PWM1 enabled\n");
7505 if (IS_HASWELL(dev))
7506 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7507 "CPU PWM2 enabled\n");
7508 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7509 "PCH PWM1 enabled\n");
7510 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7511 "Utility pin enabled\n");
7512 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7513
7514 /*
7515 * In theory we can still leave IRQs enabled, as long as only the HPD
7516 * interrupts remain enabled. We used to check for that, but since it's
7517 * gen-specific and since we only disable LCPLL after we fully disable
7518 * the interrupts, the check below should be enough.
7519 */
7520 WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7521 }
7522
7523 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7524 {
7525 struct drm_device *dev = dev_priv->dev;
7526
7527 if (IS_HASWELL(dev))
7528 return I915_READ(D_COMP_HSW);
7529 else
7530 return I915_READ(D_COMP_BDW);
7531 }
7532
7533 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7534 {
7535 struct drm_device *dev = dev_priv->dev;
7536
7537 if (IS_HASWELL(dev)) {
7538 mutex_lock(&dev_priv->rps.hw_lock);
7539 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7540 val))
7541 DRM_ERROR("Failed to write to D_COMP\n");
7542 mutex_unlock(&dev_priv->rps.hw_lock);
7543 } else {
7544 I915_WRITE(D_COMP_BDW, val);
7545 POSTING_READ(D_COMP_BDW);
7546 }
7547 }
7548
7549 /*
7550 * This function implements pieces of two sequences from BSpec:
7551 * - Sequence for display software to disable LCPLL
7552 * - Sequence for display software to allow package C8+
7553 * The steps implemented here are just the steps that actually touch the LCPLL
7554 * register. Callers should take care of disabling all the display engine
7555 * functions, doing the mode unset, fixing interrupts, etc.
7556 */
7557 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7558 bool switch_to_fclk, bool allow_power_down)
7559 {
7560 uint32_t val;
7561
7562 assert_can_disable_lcpll(dev_priv);
7563
7564 val = I915_READ(LCPLL_CTL);
7565
7566 if (switch_to_fclk) {
7567 val |= LCPLL_CD_SOURCE_FCLK;
7568 I915_WRITE(LCPLL_CTL, val);
7569
7570 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7571 LCPLL_CD_SOURCE_FCLK_DONE, 1))
7572 DRM_ERROR("Switching to FCLK failed\n");
7573
7574 val = I915_READ(LCPLL_CTL);
7575 }
7576
7577 val |= LCPLL_PLL_DISABLE;
7578 I915_WRITE(LCPLL_CTL, val);
7579 POSTING_READ(LCPLL_CTL);
7580
7581 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7582 DRM_ERROR("LCPLL still locked\n");
7583
7584 val = hsw_read_dcomp(dev_priv);
7585 val |= D_COMP_COMP_DISABLE;
7586 hsw_write_dcomp(dev_priv, val);
7587 ndelay(100);
7588
7589 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7590 1))
7591 DRM_ERROR("D_COMP RCOMP still in progress\n");
7592
7593 if (allow_power_down) {
7594 val = I915_READ(LCPLL_CTL);
7595 val |= LCPLL_POWER_DOWN_ALLOW;
7596 I915_WRITE(LCPLL_CTL, val);
7597 POSTING_READ(LCPLL_CTL);
7598 }
7599 }
7600
7601 /*
7602 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7603 * source.
7604 */
7605 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7606 {
7607 uint32_t val;
7608 unsigned long irqflags;
7609
7610 val = I915_READ(LCPLL_CTL);
7611
7612 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7613 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7614 return;
7615
7616 /*
7617 * Make sure we're not on PC8 state before disabling PC8, otherwise
7618 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7619 *
7620 * The other problem is that hsw_restore_lcpll() is called as part of
7621 * the runtime PM resume sequence, so we can't just call
7622 * gen6_gt_force_wake_get() because that function calls
7623 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7624 * while we are on the resume sequence. So to solve this problem we have
7625 * to call special forcewake code that doesn't touch runtime PM and
7626 * doesn't enable the forcewake delayed work.
7627 */
7628 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7629 if (dev_priv->uncore.forcewake_count++ == 0)
7630 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7631 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7632
7633 if (val & LCPLL_POWER_DOWN_ALLOW) {
7634 val &= ~LCPLL_POWER_DOWN_ALLOW;
7635 I915_WRITE(LCPLL_CTL, val);
7636 POSTING_READ(LCPLL_CTL);
7637 }
7638
7639 val = hsw_read_dcomp(dev_priv);
7640 val |= D_COMP_COMP_FORCE;
7641 val &= ~D_COMP_COMP_DISABLE;
7642 hsw_write_dcomp(dev_priv, val);
7643
7644 val = I915_READ(LCPLL_CTL);
7645 val &= ~LCPLL_PLL_DISABLE;
7646 I915_WRITE(LCPLL_CTL, val);
7647
7648 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7649 DRM_ERROR("LCPLL not locked yet\n");
7650
7651 if (val & LCPLL_CD_SOURCE_FCLK) {
7652 val = I915_READ(LCPLL_CTL);
7653 val &= ~LCPLL_CD_SOURCE_FCLK;
7654 I915_WRITE(LCPLL_CTL, val);
7655
7656 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7657 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7658 DRM_ERROR("Switching back to LCPLL failed\n");
7659 }
7660
7661 /* See the big comment above. */
7662 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7663 if (--dev_priv->uncore.forcewake_count == 0)
7664 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7665 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7666 }
7667
7668 /*
7669 * Package states C8 and deeper are really deep PC states that can only be
7670 * reached when all the devices on the system allow it, so even if the graphics
7671 * device allows PC8+, it doesn't mean the system will actually get to these
7672 * states. Our driver only allows PC8+ when going into runtime PM.
7673 *
7674 * The requirements for PC8+ are that all the outputs are disabled, the power
7675 * well is disabled and most interrupts are disabled, and these are also
7676 * requirements for runtime PM. When these conditions are met, we manually do
7677 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7678 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7679 * hang the machine.
7680 *
7681 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7682 * the state of some registers, so when we come back from PC8+ we need to
7683 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7684 * need to take care of the registers kept by RC6. Notice that this happens even
7685 * if we don't put the device in PCI D3 state (which is what currently happens
7686 * because of the runtime PM support).
7687 *
7688 * For more, read "Display Sequences for Package C8" on the hardware
7689 * documentation.
7690 */
7691 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7692 {
7693 struct drm_device *dev = dev_priv->dev;
7694 uint32_t val;
7695
7696 DRM_DEBUG_KMS("Enabling package C8+\n");
7697
7698 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7699 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7700 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7701 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7702 }
7703
7704 lpt_disable_clkout_dp(dev);
7705 hsw_disable_lcpll(dev_priv, true, true);
7706 }
7707
7708 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7709 {
7710 struct drm_device *dev = dev_priv->dev;
7711 uint32_t val;
7712
7713 DRM_DEBUG_KMS("Disabling package C8+\n");
7714
7715 hsw_restore_lcpll(dev_priv);
7716 lpt_init_pch_refclk(dev);
7717
7718 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7719 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7720 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7721 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7722 }
7723
7724 intel_prepare_ddi(dev);
7725 }
7726
7727 static void snb_modeset_global_resources(struct drm_device *dev)
7728 {
7729 modeset_update_crtc_power_domains(dev);
7730 }
7731
7732 static void haswell_modeset_global_resources(struct drm_device *dev)
7733 {
7734 modeset_update_crtc_power_domains(dev);
7735 }
7736
7737 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7738 int x, int y,
7739 struct drm_framebuffer *fb)
7740 {
7741 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7742
7743 if (!intel_ddi_pll_select(intel_crtc))
7744 return -EINVAL;
7745
7746 intel_crtc->lowfreq_avail = false;
7747
7748 return 0;
7749 }
7750
7751 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
7752 enum port port,
7753 struct intel_crtc_config *pipe_config)
7754 {
7755 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
7756
7757 switch (pipe_config->ddi_pll_sel) {
7758 case PORT_CLK_SEL_WRPLL1:
7759 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
7760 break;
7761 case PORT_CLK_SEL_WRPLL2:
7762 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
7763 break;
7764 }
7765 }
7766
7767 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
7768 struct intel_crtc_config *pipe_config)
7769 {
7770 struct drm_device *dev = crtc->base.dev;
7771 struct drm_i915_private *dev_priv = dev->dev_private;
7772 struct intel_shared_dpll *pll;
7773 enum port port;
7774 uint32_t tmp;
7775
7776 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7777
7778 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
7779
7780 haswell_get_ddi_pll(dev_priv, port, pipe_config);
7781
7782 if (pipe_config->shared_dpll >= 0) {
7783 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7784
7785 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7786 &pipe_config->dpll_hw_state));
7787 }
7788
7789 /*
7790 * Haswell has only FDI/PCH transcoder A. It is which is connected to
7791 * DDI E. So just check whether this pipe is wired to DDI E and whether
7792 * the PCH transcoder is on.
7793 */
7794 if ((port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7795 pipe_config->has_pch_encoder = true;
7796
7797 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7798 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7799 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7800
7801 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7802 }
7803 }
7804
7805 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7806 struct intel_crtc_config *pipe_config)
7807 {
7808 struct drm_device *dev = crtc->base.dev;
7809 struct drm_i915_private *dev_priv = dev->dev_private;
7810 enum intel_display_power_domain pfit_domain;
7811 uint32_t tmp;
7812
7813 if (!intel_display_power_enabled(dev_priv,
7814 POWER_DOMAIN_PIPE(crtc->pipe)))
7815 return false;
7816
7817 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7818 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7819
7820 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7821 if (tmp & TRANS_DDI_FUNC_ENABLE) {
7822 enum pipe trans_edp_pipe;
7823 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7824 default:
7825 WARN(1, "unknown pipe linked to edp transcoder\n");
7826 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7827 case TRANS_DDI_EDP_INPUT_A_ON:
7828 trans_edp_pipe = PIPE_A;
7829 break;
7830 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7831 trans_edp_pipe = PIPE_B;
7832 break;
7833 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7834 trans_edp_pipe = PIPE_C;
7835 break;
7836 }
7837
7838 if (trans_edp_pipe == crtc->pipe)
7839 pipe_config->cpu_transcoder = TRANSCODER_EDP;
7840 }
7841
7842 if (!intel_display_power_enabled(dev_priv,
7843 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7844 return false;
7845
7846 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7847 if (!(tmp & PIPECONF_ENABLE))
7848 return false;
7849
7850 haswell_get_ddi_port_state(crtc, pipe_config);
7851
7852 intel_get_pipe_timings(crtc, pipe_config);
7853
7854 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7855 if (intel_display_power_enabled(dev_priv, pfit_domain))
7856 ironlake_get_pfit_config(crtc, pipe_config);
7857
7858 if (IS_HASWELL(dev))
7859 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7860 (I915_READ(IPS_CTL) & IPS_ENABLE);
7861
7862 pipe_config->pixel_multiplier = 1;
7863
7864 return true;
7865 }
7866
7867 static struct {
7868 int clock;
7869 u32 config;
7870 } hdmi_audio_clock[] = {
7871 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7872 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7873 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7874 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7875 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7876 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7877 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7878 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7879 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7880 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7881 };
7882
7883 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7884 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7885 {
7886 int i;
7887
7888 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7889 if (mode->clock == hdmi_audio_clock[i].clock)
7890 break;
7891 }
7892
7893 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7894 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7895 i = 1;
7896 }
7897
7898 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7899 hdmi_audio_clock[i].clock,
7900 hdmi_audio_clock[i].config);
7901
7902 return hdmi_audio_clock[i].config;
7903 }
7904
7905 static bool intel_eld_uptodate(struct drm_connector *connector,
7906 int reg_eldv, uint32_t bits_eldv,
7907 int reg_elda, uint32_t bits_elda,
7908 int reg_edid)
7909 {
7910 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7911 uint8_t *eld = connector->eld;
7912 uint32_t i;
7913
7914 i = I915_READ(reg_eldv);
7915 i &= bits_eldv;
7916
7917 if (!eld[0])
7918 return !i;
7919
7920 if (!i)
7921 return false;
7922
7923 i = I915_READ(reg_elda);
7924 i &= ~bits_elda;
7925 I915_WRITE(reg_elda, i);
7926
7927 for (i = 0; i < eld[2]; i++)
7928 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7929 return false;
7930
7931 return true;
7932 }
7933
7934 static void g4x_write_eld(struct drm_connector *connector,
7935 struct drm_crtc *crtc,
7936 struct drm_display_mode *mode)
7937 {
7938 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7939 uint8_t *eld = connector->eld;
7940 uint32_t eldv;
7941 uint32_t len;
7942 uint32_t i;
7943
7944 i = I915_READ(G4X_AUD_VID_DID);
7945
7946 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7947 eldv = G4X_ELDV_DEVCL_DEVBLC;
7948 else
7949 eldv = G4X_ELDV_DEVCTG;
7950
7951 if (intel_eld_uptodate(connector,
7952 G4X_AUD_CNTL_ST, eldv,
7953 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7954 G4X_HDMIW_HDMIEDID))
7955 return;
7956
7957 i = I915_READ(G4X_AUD_CNTL_ST);
7958 i &= ~(eldv | G4X_ELD_ADDR);
7959 len = (i >> 9) & 0x1f; /* ELD buffer size */
7960 I915_WRITE(G4X_AUD_CNTL_ST, i);
7961
7962 if (!eld[0])
7963 return;
7964
7965 len = min_t(uint8_t, eld[2], len);
7966 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7967 for (i = 0; i < len; i++)
7968 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7969
7970 i = I915_READ(G4X_AUD_CNTL_ST);
7971 i |= eldv;
7972 I915_WRITE(G4X_AUD_CNTL_ST, i);
7973 }
7974
7975 static void haswell_write_eld(struct drm_connector *connector,
7976 struct drm_crtc *crtc,
7977 struct drm_display_mode *mode)
7978 {
7979 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7980 uint8_t *eld = connector->eld;
7981 uint32_t eldv;
7982 uint32_t i;
7983 int len;
7984 int pipe = to_intel_crtc(crtc)->pipe;
7985 int tmp;
7986
7987 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7988 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7989 int aud_config = HSW_AUD_CFG(pipe);
7990 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7991
7992 /* Audio output enable */
7993 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7994 tmp = I915_READ(aud_cntrl_st2);
7995 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7996 I915_WRITE(aud_cntrl_st2, tmp);
7997 POSTING_READ(aud_cntrl_st2);
7998
7999 assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
8000
8001 /* Set ELD valid state */
8002 tmp = I915_READ(aud_cntrl_st2);
8003 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
8004 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
8005 I915_WRITE(aud_cntrl_st2, tmp);
8006 tmp = I915_READ(aud_cntrl_st2);
8007 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
8008
8009 /* Enable HDMI mode */
8010 tmp = I915_READ(aud_config);
8011 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
8012 /* clear N_programing_enable and N_value_index */
8013 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
8014 I915_WRITE(aud_config, tmp);
8015
8016 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
8017
8018 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
8019
8020 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
8021 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
8022 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
8023 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
8024 } else {
8025 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
8026 }
8027
8028 if (intel_eld_uptodate(connector,
8029 aud_cntrl_st2, eldv,
8030 aud_cntl_st, IBX_ELD_ADDRESS,
8031 hdmiw_hdmiedid))
8032 return;
8033
8034 i = I915_READ(aud_cntrl_st2);
8035 i &= ~eldv;
8036 I915_WRITE(aud_cntrl_st2, i);
8037
8038 if (!eld[0])
8039 return;
8040
8041 i = I915_READ(aud_cntl_st);
8042 i &= ~IBX_ELD_ADDRESS;
8043 I915_WRITE(aud_cntl_st, i);
8044 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
8045 DRM_DEBUG_DRIVER("port num:%d\n", i);
8046
8047 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
8048 DRM_DEBUG_DRIVER("ELD size %d\n", len);
8049 for (i = 0; i < len; i++)
8050 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
8051
8052 i = I915_READ(aud_cntrl_st2);
8053 i |= eldv;
8054 I915_WRITE(aud_cntrl_st2, i);
8055
8056 }
8057
8058 static void ironlake_write_eld(struct drm_connector *connector,
8059 struct drm_crtc *crtc,
8060 struct drm_display_mode *mode)
8061 {
8062 struct drm_i915_private *dev_priv = connector->dev->dev_private;
8063 uint8_t *eld = connector->eld;
8064 uint32_t eldv;
8065 uint32_t i;
8066 int len;
8067 int hdmiw_hdmiedid;
8068 int aud_config;
8069 int aud_cntl_st;
8070 int aud_cntrl_st2;
8071 int pipe = to_intel_crtc(crtc)->pipe;
8072
8073 if (HAS_PCH_IBX(connector->dev)) {
8074 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
8075 aud_config = IBX_AUD_CFG(pipe);
8076 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
8077 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
8078 } else if (IS_VALLEYVIEW(connector->dev)) {
8079 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
8080 aud_config = VLV_AUD_CFG(pipe);
8081 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
8082 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
8083 } else {
8084 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
8085 aud_config = CPT_AUD_CFG(pipe);
8086 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
8087 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
8088 }
8089
8090 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
8091
8092 if (IS_VALLEYVIEW(connector->dev)) {
8093 struct intel_encoder *intel_encoder;
8094 struct intel_digital_port *intel_dig_port;
8095
8096 intel_encoder = intel_attached_encoder(connector);
8097 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
8098 i = intel_dig_port->port;
8099 } else {
8100 i = I915_READ(aud_cntl_st);
8101 i = (i >> 29) & DIP_PORT_SEL_MASK;
8102 /* DIP_Port_Select, 0x1 = PortB */
8103 }
8104
8105 if (!i) {
8106 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
8107 /* operate blindly on all ports */
8108 eldv = IBX_ELD_VALIDB;
8109 eldv |= IBX_ELD_VALIDB << 4;
8110 eldv |= IBX_ELD_VALIDB << 8;
8111 } else {
8112 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
8113 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
8114 }
8115
8116 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
8117 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
8118 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
8119 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
8120 } else {
8121 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
8122 }
8123
8124 if (intel_eld_uptodate(connector,
8125 aud_cntrl_st2, eldv,
8126 aud_cntl_st, IBX_ELD_ADDRESS,
8127 hdmiw_hdmiedid))
8128 return;
8129
8130 i = I915_READ(aud_cntrl_st2);
8131 i &= ~eldv;
8132 I915_WRITE(aud_cntrl_st2, i);
8133
8134 if (!eld[0])
8135 return;
8136
8137 i = I915_READ(aud_cntl_st);
8138 i &= ~IBX_ELD_ADDRESS;
8139 I915_WRITE(aud_cntl_st, i);
8140
8141 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
8142 DRM_DEBUG_DRIVER("ELD size %d\n", len);
8143 for (i = 0; i < len; i++)
8144 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
8145
8146 i = I915_READ(aud_cntrl_st2);
8147 i |= eldv;
8148 I915_WRITE(aud_cntrl_st2, i);
8149 }
8150
8151 void intel_write_eld(struct drm_encoder *encoder,
8152 struct drm_display_mode *mode)
8153 {
8154 struct drm_crtc *crtc = encoder->crtc;
8155 struct drm_connector *connector;
8156 struct drm_device *dev = encoder->dev;
8157 struct drm_i915_private *dev_priv = dev->dev_private;
8158
8159 connector = drm_select_eld(encoder, mode);
8160 if (!connector)
8161 return;
8162
8163 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8164 connector->base.id,
8165 connector->name,
8166 connector->encoder->base.id,
8167 connector->encoder->name);
8168
8169 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
8170
8171 if (dev_priv->display.write_eld)
8172 dev_priv->display.write_eld(connector, crtc, mode);
8173 }
8174
8175 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8176 {
8177 struct drm_device *dev = crtc->dev;
8178 struct drm_i915_private *dev_priv = dev->dev_private;
8179 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8180 uint32_t cntl = 0, size = 0;
8181
8182 if (base) {
8183 unsigned int width = intel_crtc->cursor_width;
8184 unsigned int height = intel_crtc->cursor_height;
8185 unsigned int stride = roundup_pow_of_two(width) * 4;
8186
8187 switch (stride) {
8188 default:
8189 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8190 width, stride);
8191 stride = 256;
8192 /* fallthrough */
8193 case 256:
8194 case 512:
8195 case 1024:
8196 case 2048:
8197 break;
8198 }
8199
8200 cntl |= CURSOR_ENABLE |
8201 CURSOR_GAMMA_ENABLE |
8202 CURSOR_FORMAT_ARGB |
8203 CURSOR_STRIDE(stride);
8204
8205 size = (height << 12) | width;
8206 }
8207
8208 if (intel_crtc->cursor_cntl != 0 &&
8209 (intel_crtc->cursor_base != base ||
8210 intel_crtc->cursor_size != size ||
8211 intel_crtc->cursor_cntl != cntl)) {
8212 /* On these chipsets we can only modify the base/size/stride
8213 * whilst the cursor is disabled.
8214 */
8215 I915_WRITE(_CURACNTR, 0);
8216 POSTING_READ(_CURACNTR);
8217 intel_crtc->cursor_cntl = 0;
8218 }
8219
8220 if (intel_crtc->cursor_base != base) {
8221 I915_WRITE(_CURABASE, base);
8222 intel_crtc->cursor_base = base;
8223 }
8224
8225 if (intel_crtc->cursor_size != size) {
8226 I915_WRITE(CURSIZE, size);
8227 intel_crtc->cursor_size = size;
8228 }
8229
8230 if (intel_crtc->cursor_cntl != cntl) {
8231 I915_WRITE(_CURACNTR, cntl);
8232 POSTING_READ(_CURACNTR);
8233 intel_crtc->cursor_cntl = cntl;
8234 }
8235 }
8236
8237 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8238 {
8239 struct drm_device *dev = crtc->dev;
8240 struct drm_i915_private *dev_priv = dev->dev_private;
8241 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8242 int pipe = intel_crtc->pipe;
8243 uint32_t cntl;
8244
8245 cntl = 0;
8246 if (base) {
8247 cntl = MCURSOR_GAMMA_ENABLE;
8248 switch (intel_crtc->cursor_width) {
8249 case 64:
8250 cntl |= CURSOR_MODE_64_ARGB_AX;
8251 break;
8252 case 128:
8253 cntl |= CURSOR_MODE_128_ARGB_AX;
8254 break;
8255 case 256:
8256 cntl |= CURSOR_MODE_256_ARGB_AX;
8257 break;
8258 default:
8259 WARN_ON(1);
8260 return;
8261 }
8262 cntl |= pipe << 28; /* Connect to correct pipe */
8263
8264 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8265 cntl |= CURSOR_PIPE_CSC_ENABLE;
8266 }
8267
8268 if (intel_crtc->cursor_cntl != cntl) {
8269 I915_WRITE(CURCNTR(pipe), cntl);
8270 POSTING_READ(CURCNTR(pipe));
8271 intel_crtc->cursor_cntl = cntl;
8272 }
8273
8274 /* and commit changes on next vblank */
8275 I915_WRITE(CURBASE(pipe), base);
8276 POSTING_READ(CURBASE(pipe));
8277
8278 intel_crtc->cursor_base = base;
8279 }
8280
8281 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8282 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8283 bool on)
8284 {
8285 struct drm_device *dev = crtc->dev;
8286 struct drm_i915_private *dev_priv = dev->dev_private;
8287 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8288 int pipe = intel_crtc->pipe;
8289 int x = crtc->cursor_x;
8290 int y = crtc->cursor_y;
8291 u32 base = 0, pos = 0;
8292
8293 if (on)
8294 base = intel_crtc->cursor_addr;
8295
8296 if (x >= intel_crtc->config.pipe_src_w)
8297 base = 0;
8298
8299 if (y >= intel_crtc->config.pipe_src_h)
8300 base = 0;
8301
8302 if (x < 0) {
8303 if (x + intel_crtc->cursor_width <= 0)
8304 base = 0;
8305
8306 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8307 x = -x;
8308 }
8309 pos |= x << CURSOR_X_SHIFT;
8310
8311 if (y < 0) {
8312 if (y + intel_crtc->cursor_height <= 0)
8313 base = 0;
8314
8315 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8316 y = -y;
8317 }
8318 pos |= y << CURSOR_Y_SHIFT;
8319
8320 if (base == 0 && intel_crtc->cursor_base == 0)
8321 return;
8322
8323 I915_WRITE(CURPOS(pipe), pos);
8324
8325 if (IS_845G(dev) || IS_I865G(dev))
8326 i845_update_cursor(crtc, base);
8327 else
8328 i9xx_update_cursor(crtc, base);
8329 }
8330
8331 static bool cursor_size_ok(struct drm_device *dev,
8332 uint32_t width, uint32_t height)
8333 {
8334 if (width == 0 || height == 0)
8335 return false;
8336
8337 /*
8338 * 845g/865g are special in that they are only limited by
8339 * the width of their cursors, the height is arbitrary up to
8340 * the precision of the register. Everything else requires
8341 * square cursors, limited to a few power-of-two sizes.
8342 */
8343 if (IS_845G(dev) || IS_I865G(dev)) {
8344 if ((width & 63) != 0)
8345 return false;
8346
8347 if (width > (IS_845G(dev) ? 64 : 512))
8348 return false;
8349
8350 if (height > 1023)
8351 return false;
8352 } else {
8353 switch (width | height) {
8354 case 256:
8355 case 128:
8356 if (IS_GEN2(dev))
8357 return false;
8358 case 64:
8359 break;
8360 default:
8361 return false;
8362 }
8363 }
8364
8365 return true;
8366 }
8367
8368 /*
8369 * intel_crtc_cursor_set_obj - Set cursor to specified GEM object
8370 *
8371 * Note that the object's reference will be consumed if the update fails. If
8372 * the update succeeds, the reference of the old object (if any) will be
8373 * consumed.
8374 */
8375 static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8376 struct drm_i915_gem_object *obj,
8377 uint32_t width, uint32_t height)
8378 {
8379 struct drm_device *dev = crtc->dev;
8380 struct drm_i915_private *dev_priv = dev->dev_private;
8381 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8382 enum pipe pipe = intel_crtc->pipe;
8383 unsigned old_width, stride;
8384 uint32_t addr;
8385 int ret;
8386
8387 /* if we want to turn off the cursor ignore width and height */
8388 if (!obj) {
8389 DRM_DEBUG_KMS("cursor off\n");
8390 addr = 0;
8391 mutex_lock(&dev->struct_mutex);
8392 goto finish;
8393 }
8394
8395 /* Check for which cursor types we support */
8396 if (!cursor_size_ok(dev, width, height)) {
8397 DRM_DEBUG("Cursor dimension not supported\n");
8398 return -EINVAL;
8399 }
8400
8401 stride = roundup_pow_of_two(width) * 4;
8402 if (obj->base.size < stride * height) {
8403 DRM_DEBUG_KMS("buffer is too small\n");
8404 ret = -ENOMEM;
8405 goto fail;
8406 }
8407
8408 /* we only need to pin inside GTT if cursor is non-phy */
8409 mutex_lock(&dev->struct_mutex);
8410 if (!INTEL_INFO(dev)->cursor_needs_physical) {
8411 unsigned alignment;
8412
8413 if (obj->tiling_mode) {
8414 DRM_DEBUG_KMS("cursor cannot be tiled\n");
8415 ret = -EINVAL;
8416 goto fail_locked;
8417 }
8418
8419 /*
8420 * Global gtt pte registers are special registers which actually
8421 * forward writes to a chunk of system memory. Which means that
8422 * there is no risk that the register values disappear as soon
8423 * as we call intel_runtime_pm_put(), so it is correct to wrap
8424 * only the pin/unpin/fence and not more.
8425 */
8426 intel_runtime_pm_get(dev_priv);
8427
8428 /* Note that the w/a also requires 2 PTE of padding following
8429 * the bo. We currently fill all unused PTE with the shadow
8430 * page and so we should always have valid PTE following the
8431 * cursor preventing the VT-d warning.
8432 */
8433 alignment = 0;
8434 if (need_vtd_wa(dev))
8435 alignment = 64*1024;
8436
8437 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8438 if (ret) {
8439 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8440 intel_runtime_pm_put(dev_priv);
8441 goto fail_locked;
8442 }
8443
8444 ret = i915_gem_object_put_fence(obj);
8445 if (ret) {
8446 DRM_DEBUG_KMS("failed to release fence for cursor");
8447 intel_runtime_pm_put(dev_priv);
8448 goto fail_unpin;
8449 }
8450
8451 addr = i915_gem_obj_ggtt_offset(obj);
8452
8453 intel_runtime_pm_put(dev_priv);
8454 } else {
8455 int align = IS_I830(dev) ? 16 * 1024 : 256;
8456 ret = i915_gem_object_attach_phys(obj, align);
8457 if (ret) {
8458 DRM_DEBUG_KMS("failed to attach phys object\n");
8459 goto fail_locked;
8460 }
8461 addr = obj->phys_handle->busaddr;
8462 }
8463
8464 finish:
8465 if (intel_crtc->cursor_bo) {
8466 if (!INTEL_INFO(dev)->cursor_needs_physical)
8467 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8468 }
8469
8470 i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8471 INTEL_FRONTBUFFER_CURSOR(pipe));
8472 mutex_unlock(&dev->struct_mutex);
8473
8474 old_width = intel_crtc->cursor_width;
8475
8476 intel_crtc->cursor_addr = addr;
8477 intel_crtc->cursor_bo = obj;
8478 intel_crtc->cursor_width = width;
8479 intel_crtc->cursor_height = height;
8480
8481 if (intel_crtc->active) {
8482 if (old_width != width)
8483 intel_update_watermarks(crtc);
8484 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8485 }
8486
8487 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
8488
8489 return 0;
8490 fail_unpin:
8491 i915_gem_object_unpin_from_display_plane(obj);
8492 fail_locked:
8493 mutex_unlock(&dev->struct_mutex);
8494 fail:
8495 drm_gem_object_unreference_unlocked(&obj->base);
8496 return ret;
8497 }
8498
8499 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8500 u16 *blue, uint32_t start, uint32_t size)
8501 {
8502 int end = (start + size > 256) ? 256 : start + size, i;
8503 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8504
8505 for (i = start; i < end; i++) {
8506 intel_crtc->lut_r[i] = red[i] >> 8;
8507 intel_crtc->lut_g[i] = green[i] >> 8;
8508 intel_crtc->lut_b[i] = blue[i] >> 8;
8509 }
8510
8511 intel_crtc_load_lut(crtc);
8512 }
8513
8514 /* VESA 640x480x72Hz mode to set on the pipe */
8515 static struct drm_display_mode load_detect_mode = {
8516 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8517 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8518 };
8519
8520 struct drm_framebuffer *
8521 __intel_framebuffer_create(struct drm_device *dev,
8522 struct drm_mode_fb_cmd2 *mode_cmd,
8523 struct drm_i915_gem_object *obj)
8524 {
8525 struct intel_framebuffer *intel_fb;
8526 int ret;
8527
8528 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8529 if (!intel_fb) {
8530 drm_gem_object_unreference_unlocked(&obj->base);
8531 return ERR_PTR(-ENOMEM);
8532 }
8533
8534 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8535 if (ret)
8536 goto err;
8537
8538 return &intel_fb->base;
8539 err:
8540 drm_gem_object_unreference_unlocked(&obj->base);
8541 kfree(intel_fb);
8542
8543 return ERR_PTR(ret);
8544 }
8545
8546 static struct drm_framebuffer *
8547 intel_framebuffer_create(struct drm_device *dev,
8548 struct drm_mode_fb_cmd2 *mode_cmd,
8549 struct drm_i915_gem_object *obj)
8550 {
8551 struct drm_framebuffer *fb;
8552 int ret;
8553
8554 ret = i915_mutex_lock_interruptible(dev);
8555 if (ret)
8556 return ERR_PTR(ret);
8557 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8558 mutex_unlock(&dev->struct_mutex);
8559
8560 return fb;
8561 }
8562
8563 static u32
8564 intel_framebuffer_pitch_for_width(int width, int bpp)
8565 {
8566 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8567 return ALIGN(pitch, 64);
8568 }
8569
8570 static u32
8571 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8572 {
8573 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8574 return PAGE_ALIGN(pitch * mode->vdisplay);
8575 }
8576
8577 static struct drm_framebuffer *
8578 intel_framebuffer_create_for_mode(struct drm_device *dev,
8579 struct drm_display_mode *mode,
8580 int depth, int bpp)
8581 {
8582 struct drm_i915_gem_object *obj;
8583 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8584
8585 obj = i915_gem_alloc_object(dev,
8586 intel_framebuffer_size_for_mode(mode, bpp));
8587 if (obj == NULL)
8588 return ERR_PTR(-ENOMEM);
8589
8590 mode_cmd.width = mode->hdisplay;
8591 mode_cmd.height = mode->vdisplay;
8592 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8593 bpp);
8594 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8595
8596 return intel_framebuffer_create(dev, &mode_cmd, obj);
8597 }
8598
8599 static struct drm_framebuffer *
8600 mode_fits_in_fbdev(struct drm_device *dev,
8601 struct drm_display_mode *mode)
8602 {
8603 #ifdef CONFIG_DRM_I915_FBDEV
8604 struct drm_i915_private *dev_priv = dev->dev_private;
8605 struct drm_i915_gem_object *obj;
8606 struct drm_framebuffer *fb;
8607
8608 if (!dev_priv->fbdev)
8609 return NULL;
8610
8611 if (!dev_priv->fbdev->fb)
8612 return NULL;
8613
8614 obj = dev_priv->fbdev->fb->obj;
8615 BUG_ON(!obj);
8616
8617 fb = &dev_priv->fbdev->fb->base;
8618 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8619 fb->bits_per_pixel))
8620 return NULL;
8621
8622 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8623 return NULL;
8624
8625 return fb;
8626 #else
8627 return NULL;
8628 #endif
8629 }
8630
8631 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8632 struct drm_display_mode *mode,
8633 struct intel_load_detect_pipe *old,
8634 struct drm_modeset_acquire_ctx *ctx)
8635 {
8636 struct intel_crtc *intel_crtc;
8637 struct intel_encoder *intel_encoder =
8638 intel_attached_encoder(connector);
8639 struct drm_crtc *possible_crtc;
8640 struct drm_encoder *encoder = &intel_encoder->base;
8641 struct drm_crtc *crtc = NULL;
8642 struct drm_device *dev = encoder->dev;
8643 struct drm_framebuffer *fb;
8644 struct drm_mode_config *config = &dev->mode_config;
8645 int ret, i = -1;
8646
8647 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8648 connector->base.id, connector->name,
8649 encoder->base.id, encoder->name);
8650
8651 retry:
8652 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8653 if (ret)
8654 goto fail_unlock;
8655
8656 /*
8657 * Algorithm gets a little messy:
8658 *
8659 * - if the connector already has an assigned crtc, use it (but make
8660 * sure it's on first)
8661 *
8662 * - try to find the first unused crtc that can drive this connector,
8663 * and use that if we find one
8664 */
8665
8666 /* See if we already have a CRTC for this connector */
8667 if (encoder->crtc) {
8668 crtc = encoder->crtc;
8669
8670 ret = drm_modeset_lock(&crtc->mutex, ctx);
8671 if (ret)
8672 goto fail_unlock;
8673
8674 old->dpms_mode = connector->dpms;
8675 old->load_detect_temp = false;
8676
8677 /* Make sure the crtc and connector are running */
8678 if (connector->dpms != DRM_MODE_DPMS_ON)
8679 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8680
8681 return true;
8682 }
8683
8684 /* Find an unused one (if possible) */
8685 for_each_crtc(dev, possible_crtc) {
8686 i++;
8687 if (!(encoder->possible_crtcs & (1 << i)))
8688 continue;
8689 if (possible_crtc->enabled)
8690 continue;
8691 /* This can occur when applying the pipe A quirk on resume. */
8692 if (to_intel_crtc(possible_crtc)->new_enabled)
8693 continue;
8694
8695 crtc = possible_crtc;
8696 break;
8697 }
8698
8699 /*
8700 * If we didn't find an unused CRTC, don't use any.
8701 */
8702 if (!crtc) {
8703 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8704 goto fail_unlock;
8705 }
8706
8707 ret = drm_modeset_lock(&crtc->mutex, ctx);
8708 if (ret)
8709 goto fail_unlock;
8710 intel_encoder->new_crtc = to_intel_crtc(crtc);
8711 to_intel_connector(connector)->new_encoder = intel_encoder;
8712
8713 intel_crtc = to_intel_crtc(crtc);
8714 intel_crtc->new_enabled = true;
8715 intel_crtc->new_config = &intel_crtc->config;
8716 old->dpms_mode = connector->dpms;
8717 old->load_detect_temp = true;
8718 old->release_fb = NULL;
8719
8720 if (!mode)
8721 mode = &load_detect_mode;
8722
8723 /* We need a framebuffer large enough to accommodate all accesses
8724 * that the plane may generate whilst we perform load detection.
8725 * We can not rely on the fbcon either being present (we get called
8726 * during its initialisation to detect all boot displays, or it may
8727 * not even exist) or that it is large enough to satisfy the
8728 * requested mode.
8729 */
8730 fb = mode_fits_in_fbdev(dev, mode);
8731 if (fb == NULL) {
8732 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8733 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8734 old->release_fb = fb;
8735 } else
8736 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8737 if (IS_ERR(fb)) {
8738 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8739 goto fail;
8740 }
8741
8742 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8743 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8744 if (old->release_fb)
8745 old->release_fb->funcs->destroy(old->release_fb);
8746 goto fail;
8747 }
8748
8749 /* let the connector get through one full cycle before testing */
8750 intel_wait_for_vblank(dev, intel_crtc->pipe);
8751 return true;
8752
8753 fail:
8754 intel_crtc->new_enabled = crtc->enabled;
8755 if (intel_crtc->new_enabled)
8756 intel_crtc->new_config = &intel_crtc->config;
8757 else
8758 intel_crtc->new_config = NULL;
8759 fail_unlock:
8760 if (ret == -EDEADLK) {
8761 drm_modeset_backoff(ctx);
8762 goto retry;
8763 }
8764
8765 return false;
8766 }
8767
8768 void intel_release_load_detect_pipe(struct drm_connector *connector,
8769 struct intel_load_detect_pipe *old)
8770 {
8771 struct intel_encoder *intel_encoder =
8772 intel_attached_encoder(connector);
8773 struct drm_encoder *encoder = &intel_encoder->base;
8774 struct drm_crtc *crtc = encoder->crtc;
8775 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8776
8777 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8778 connector->base.id, connector->name,
8779 encoder->base.id, encoder->name);
8780
8781 if (old->load_detect_temp) {
8782 to_intel_connector(connector)->new_encoder = NULL;
8783 intel_encoder->new_crtc = NULL;
8784 intel_crtc->new_enabled = false;
8785 intel_crtc->new_config = NULL;
8786 intel_set_mode(crtc, NULL, 0, 0, NULL);
8787
8788 if (old->release_fb) {
8789 drm_framebuffer_unregister_private(old->release_fb);
8790 drm_framebuffer_unreference(old->release_fb);
8791 }
8792
8793 return;
8794 }
8795
8796 /* Switch crtc and encoder back off if necessary */
8797 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8798 connector->funcs->dpms(connector, old->dpms_mode);
8799 }
8800
8801 static int i9xx_pll_refclk(struct drm_device *dev,
8802 const struct intel_crtc_config *pipe_config)
8803 {
8804 struct drm_i915_private *dev_priv = dev->dev_private;
8805 u32 dpll = pipe_config->dpll_hw_state.dpll;
8806
8807 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8808 return dev_priv->vbt.lvds_ssc_freq;
8809 else if (HAS_PCH_SPLIT(dev))
8810 return 120000;
8811 else if (!IS_GEN2(dev))
8812 return 96000;
8813 else
8814 return 48000;
8815 }
8816
8817 /* Returns the clock of the currently programmed mode of the given pipe. */
8818 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8819 struct intel_crtc_config *pipe_config)
8820 {
8821 struct drm_device *dev = crtc->base.dev;
8822 struct drm_i915_private *dev_priv = dev->dev_private;
8823 int pipe = pipe_config->cpu_transcoder;
8824 u32 dpll = pipe_config->dpll_hw_state.dpll;
8825 u32 fp;
8826 intel_clock_t clock;
8827 int refclk = i9xx_pll_refclk(dev, pipe_config);
8828
8829 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8830 fp = pipe_config->dpll_hw_state.fp0;
8831 else
8832 fp = pipe_config->dpll_hw_state.fp1;
8833
8834 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8835 if (IS_PINEVIEW(dev)) {
8836 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8837 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8838 } else {
8839 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8840 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8841 }
8842
8843 if (!IS_GEN2(dev)) {
8844 if (IS_PINEVIEW(dev))
8845 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8846 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8847 else
8848 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8849 DPLL_FPA01_P1_POST_DIV_SHIFT);
8850
8851 switch (dpll & DPLL_MODE_MASK) {
8852 case DPLLB_MODE_DAC_SERIAL:
8853 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8854 5 : 10;
8855 break;
8856 case DPLLB_MODE_LVDS:
8857 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8858 7 : 14;
8859 break;
8860 default:
8861 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8862 "mode\n", (int)(dpll & DPLL_MODE_MASK));
8863 return;
8864 }
8865
8866 if (IS_PINEVIEW(dev))
8867 pineview_clock(refclk, &clock);
8868 else
8869 i9xx_clock(refclk, &clock);
8870 } else {
8871 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8872 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8873
8874 if (is_lvds) {
8875 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8876 DPLL_FPA01_P1_POST_DIV_SHIFT);
8877
8878 if (lvds & LVDS_CLKB_POWER_UP)
8879 clock.p2 = 7;
8880 else
8881 clock.p2 = 14;
8882 } else {
8883 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8884 clock.p1 = 2;
8885 else {
8886 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8887 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8888 }
8889 if (dpll & PLL_P2_DIVIDE_BY_4)
8890 clock.p2 = 4;
8891 else
8892 clock.p2 = 2;
8893 }
8894
8895 i9xx_clock(refclk, &clock);
8896 }
8897
8898 /*
8899 * This value includes pixel_multiplier. We will use
8900 * port_clock to compute adjusted_mode.crtc_clock in the
8901 * encoder's get_config() function.
8902 */
8903 pipe_config->port_clock = clock.dot;
8904 }
8905
8906 int intel_dotclock_calculate(int link_freq,
8907 const struct intel_link_m_n *m_n)
8908 {
8909 /*
8910 * The calculation for the data clock is:
8911 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8912 * But we want to avoid losing precison if possible, so:
8913 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8914 *
8915 * and the link clock is simpler:
8916 * link_clock = (m * link_clock) / n
8917 */
8918
8919 if (!m_n->link_n)
8920 return 0;
8921
8922 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8923 }
8924
8925 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8926 struct intel_crtc_config *pipe_config)
8927 {
8928 struct drm_device *dev = crtc->base.dev;
8929
8930 /* read out port_clock from the DPLL */
8931 i9xx_crtc_clock_get(crtc, pipe_config);
8932
8933 /*
8934 * This value does not include pixel_multiplier.
8935 * We will check that port_clock and adjusted_mode.crtc_clock
8936 * agree once we know their relationship in the encoder's
8937 * get_config() function.
8938 */
8939 pipe_config->adjusted_mode.crtc_clock =
8940 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8941 &pipe_config->fdi_m_n);
8942 }
8943
8944 /** Returns the currently programmed mode of the given pipe. */
8945 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8946 struct drm_crtc *crtc)
8947 {
8948 struct drm_i915_private *dev_priv = dev->dev_private;
8949 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8950 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8951 struct drm_display_mode *mode;
8952 struct intel_crtc_config pipe_config;
8953 int htot = I915_READ(HTOTAL(cpu_transcoder));
8954 int hsync = I915_READ(HSYNC(cpu_transcoder));
8955 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8956 int vsync = I915_READ(VSYNC(cpu_transcoder));
8957 enum pipe pipe = intel_crtc->pipe;
8958
8959 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8960 if (!mode)
8961 return NULL;
8962
8963 /*
8964 * Construct a pipe_config sufficient for getting the clock info
8965 * back out of crtc_clock_get.
8966 *
8967 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8968 * to use a real value here instead.
8969 */
8970 pipe_config.cpu_transcoder = (enum transcoder) pipe;
8971 pipe_config.pixel_multiplier = 1;
8972 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8973 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8974 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8975 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8976
8977 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8978 mode->hdisplay = (htot & 0xffff) + 1;
8979 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8980 mode->hsync_start = (hsync & 0xffff) + 1;
8981 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8982 mode->vdisplay = (vtot & 0xffff) + 1;
8983 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8984 mode->vsync_start = (vsync & 0xffff) + 1;
8985 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8986
8987 drm_mode_set_name(mode);
8988
8989 return mode;
8990 }
8991
8992 static void intel_increase_pllclock(struct drm_device *dev,
8993 enum pipe pipe)
8994 {
8995 struct drm_i915_private *dev_priv = dev->dev_private;
8996 int dpll_reg = DPLL(pipe);
8997 int dpll;
8998
8999 if (!HAS_GMCH_DISPLAY(dev))
9000 return;
9001
9002 if (!dev_priv->lvds_downclock_avail)
9003 return;
9004
9005 dpll = I915_READ(dpll_reg);
9006 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
9007 DRM_DEBUG_DRIVER("upclocking LVDS\n");
9008
9009 assert_panel_unlocked(dev_priv, pipe);
9010
9011 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
9012 I915_WRITE(dpll_reg, dpll);
9013 intel_wait_for_vblank(dev, pipe);
9014
9015 dpll = I915_READ(dpll_reg);
9016 if (dpll & DISPLAY_RATE_SELECT_FPA1)
9017 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
9018 }
9019 }
9020
9021 static void intel_decrease_pllclock(struct drm_crtc *crtc)
9022 {
9023 struct drm_device *dev = crtc->dev;
9024 struct drm_i915_private *dev_priv = dev->dev_private;
9025 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9026
9027 if (!HAS_GMCH_DISPLAY(dev))
9028 return;
9029
9030 if (!dev_priv->lvds_downclock_avail)
9031 return;
9032
9033 /*
9034 * Since this is called by a timer, we should never get here in
9035 * the manual case.
9036 */
9037 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
9038 int pipe = intel_crtc->pipe;
9039 int dpll_reg = DPLL(pipe);
9040 int dpll;
9041
9042 DRM_DEBUG_DRIVER("downclocking LVDS\n");
9043
9044 assert_panel_unlocked(dev_priv, pipe);
9045
9046 dpll = I915_READ(dpll_reg);
9047 dpll |= DISPLAY_RATE_SELECT_FPA1;
9048 I915_WRITE(dpll_reg, dpll);
9049 intel_wait_for_vblank(dev, pipe);
9050 dpll = I915_READ(dpll_reg);
9051 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
9052 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
9053 }
9054
9055 }
9056
9057 void intel_mark_busy(struct drm_device *dev)
9058 {
9059 struct drm_i915_private *dev_priv = dev->dev_private;
9060
9061 if (dev_priv->mm.busy)
9062 return;
9063
9064 intel_runtime_pm_get(dev_priv);
9065 i915_update_gfx_val(dev_priv);
9066 dev_priv->mm.busy = true;
9067 }
9068
9069 void intel_mark_idle(struct drm_device *dev)
9070 {
9071 struct drm_i915_private *dev_priv = dev->dev_private;
9072 struct drm_crtc *crtc;
9073
9074 if (!dev_priv->mm.busy)
9075 return;
9076
9077 dev_priv->mm.busy = false;
9078
9079 if (!i915.powersave)
9080 goto out;
9081
9082 for_each_crtc(dev, crtc) {
9083 if (!crtc->primary->fb)
9084 continue;
9085
9086 intel_decrease_pllclock(crtc);
9087 }
9088
9089 if (INTEL_INFO(dev)->gen >= 6)
9090 gen6_rps_idle(dev->dev_private);
9091
9092 out:
9093 intel_runtime_pm_put(dev_priv);
9094 }
9095
9096
9097 /**
9098 * intel_mark_fb_busy - mark given planes as busy
9099 * @dev: DRM device
9100 * @frontbuffer_bits: bits for the affected planes
9101 * @ring: optional ring for asynchronous commands
9102 *
9103 * This function gets called every time the screen contents change. It can be
9104 * used to keep e.g. the update rate at the nominal refresh rate with DRRS.
9105 */
9106 static void intel_mark_fb_busy(struct drm_device *dev,
9107 unsigned frontbuffer_bits,
9108 struct intel_engine_cs *ring)
9109 {
9110 struct drm_i915_private *dev_priv = dev->dev_private;
9111 enum pipe pipe;
9112
9113 if (!i915.powersave)
9114 return;
9115
9116 for_each_pipe(dev_priv, pipe) {
9117 if (!(frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe)))
9118 continue;
9119
9120 intel_increase_pllclock(dev, pipe);
9121 if (ring && intel_fbc_enabled(dev))
9122 ring->fbc_dirty = true;
9123 }
9124 }
9125
9126 /**
9127 * intel_fb_obj_invalidate - invalidate frontbuffer object
9128 * @obj: GEM object to invalidate
9129 * @ring: set for asynchronous rendering
9130 *
9131 * This function gets called every time rendering on the given object starts and
9132 * frontbuffer caching (fbc, low refresh rate for DRRS, panel self refresh) must
9133 * be invalidated. If @ring is non-NULL any subsequent invalidation will be delayed
9134 * until the rendering completes or a flip on this frontbuffer plane is
9135 * scheduled.
9136 */
9137 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
9138 struct intel_engine_cs *ring)
9139 {
9140 struct drm_device *dev = obj->base.dev;
9141 struct drm_i915_private *dev_priv = dev->dev_private;
9142
9143 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
9144
9145 if (!obj->frontbuffer_bits)
9146 return;
9147
9148 if (ring) {
9149 mutex_lock(&dev_priv->fb_tracking.lock);
9150 dev_priv->fb_tracking.busy_bits
9151 |= obj->frontbuffer_bits;
9152 dev_priv->fb_tracking.flip_bits
9153 &= ~obj->frontbuffer_bits;
9154 mutex_unlock(&dev_priv->fb_tracking.lock);
9155 }
9156
9157 intel_mark_fb_busy(dev, obj->frontbuffer_bits, ring);
9158
9159 intel_edp_psr_invalidate(dev, obj->frontbuffer_bits);
9160 }
9161
9162 /**
9163 * intel_frontbuffer_flush - flush frontbuffer
9164 * @dev: DRM device
9165 * @frontbuffer_bits: frontbuffer plane tracking bits
9166 *
9167 * This function gets called every time rendering on the given planes has
9168 * completed and frontbuffer caching can be started again. Flushes will get
9169 * delayed if they're blocked by some oustanding asynchronous rendering.
9170 *
9171 * Can be called without any locks held.
9172 */
9173 void intel_frontbuffer_flush(struct drm_device *dev,
9174 unsigned frontbuffer_bits)
9175 {
9176 struct drm_i915_private *dev_priv = dev->dev_private;
9177
9178 /* Delay flushing when rings are still busy.*/
9179 mutex_lock(&dev_priv->fb_tracking.lock);
9180 frontbuffer_bits &= ~dev_priv->fb_tracking.busy_bits;
9181 mutex_unlock(&dev_priv->fb_tracking.lock);
9182
9183 intel_mark_fb_busy(dev, frontbuffer_bits, NULL);
9184
9185 intel_edp_psr_flush(dev, frontbuffer_bits);
9186
9187 /*
9188 * FIXME: Unconditional fbc flushing here is a rather gross hack and
9189 * needs to be reworked into a proper frontbuffer tracking scheme like
9190 * psr employs.
9191 */
9192 if (IS_BROADWELL(dev))
9193 gen8_fbc_sw_flush(dev, FBC_REND_CACHE_CLEAN);
9194 }
9195
9196 /**
9197 * intel_fb_obj_flush - flush frontbuffer object
9198 * @obj: GEM object to flush
9199 * @retire: set when retiring asynchronous rendering
9200 *
9201 * This function gets called every time rendering on the given object has
9202 * completed and frontbuffer caching can be started again. If @retire is true
9203 * then any delayed flushes will be unblocked.
9204 */
9205 void intel_fb_obj_flush(struct drm_i915_gem_object *obj,
9206 bool retire)
9207 {
9208 struct drm_device *dev = obj->base.dev;
9209 struct drm_i915_private *dev_priv = dev->dev_private;
9210 unsigned frontbuffer_bits;
9211
9212 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
9213
9214 if (!obj->frontbuffer_bits)
9215 return;
9216
9217 frontbuffer_bits = obj->frontbuffer_bits;
9218
9219 if (retire) {
9220 mutex_lock(&dev_priv->fb_tracking.lock);
9221 /* Filter out new bits since rendering started. */
9222 frontbuffer_bits &= dev_priv->fb_tracking.busy_bits;
9223
9224 dev_priv->fb_tracking.busy_bits &= ~frontbuffer_bits;
9225 mutex_unlock(&dev_priv->fb_tracking.lock);
9226 }
9227
9228 intel_frontbuffer_flush(dev, frontbuffer_bits);
9229 }
9230
9231 /**
9232 * intel_frontbuffer_flip_prepare - prepare asnychronous frontbuffer flip
9233 * @dev: DRM device
9234 * @frontbuffer_bits: frontbuffer plane tracking bits
9235 *
9236 * This function gets called after scheduling a flip on @obj. The actual
9237 * frontbuffer flushing will be delayed until completion is signalled with
9238 * intel_frontbuffer_flip_complete. If an invalidate happens in between this
9239 * flush will be cancelled.
9240 *
9241 * Can be called without any locks held.
9242 */
9243 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
9244 unsigned frontbuffer_bits)
9245 {
9246 struct drm_i915_private *dev_priv = dev->dev_private;
9247
9248 mutex_lock(&dev_priv->fb_tracking.lock);
9249 dev_priv->fb_tracking.flip_bits
9250 |= frontbuffer_bits;
9251 mutex_unlock(&dev_priv->fb_tracking.lock);
9252 }
9253
9254 /**
9255 * intel_frontbuffer_flip_complete - complete asynchronous frontbuffer flush
9256 * @dev: DRM device
9257 * @frontbuffer_bits: frontbuffer plane tracking bits
9258 *
9259 * This function gets called after the flip has been latched and will complete
9260 * on the next vblank. It will execute the fush if it hasn't been cancalled yet.
9261 *
9262 * Can be called without any locks held.
9263 */
9264 void intel_frontbuffer_flip_complete(struct drm_device *dev,
9265 unsigned frontbuffer_bits)
9266 {
9267 struct drm_i915_private *dev_priv = dev->dev_private;
9268
9269 mutex_lock(&dev_priv->fb_tracking.lock);
9270 /* Mask any cancelled flips. */
9271 frontbuffer_bits &= dev_priv->fb_tracking.flip_bits;
9272 dev_priv->fb_tracking.flip_bits &= ~frontbuffer_bits;
9273 mutex_unlock(&dev_priv->fb_tracking.lock);
9274
9275 intel_frontbuffer_flush(dev, frontbuffer_bits);
9276 }
9277
9278 static void intel_crtc_destroy(struct drm_crtc *crtc)
9279 {
9280 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9281 struct drm_device *dev = crtc->dev;
9282 struct intel_unpin_work *work;
9283 unsigned long flags;
9284
9285 spin_lock_irqsave(&dev->event_lock, flags);
9286 work = intel_crtc->unpin_work;
9287 intel_crtc->unpin_work = NULL;
9288 spin_unlock_irqrestore(&dev->event_lock, flags);
9289
9290 if (work) {
9291 cancel_work_sync(&work->work);
9292 kfree(work);
9293 }
9294
9295 drm_crtc_cleanup(crtc);
9296
9297 kfree(intel_crtc);
9298 }
9299
9300 static void intel_unpin_work_fn(struct work_struct *__work)
9301 {
9302 struct intel_unpin_work *work =
9303 container_of(__work, struct intel_unpin_work, work);
9304 struct drm_device *dev = work->crtc->dev;
9305 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9306
9307 mutex_lock(&dev->struct_mutex);
9308 intel_unpin_fb_obj(work->old_fb_obj);
9309 drm_gem_object_unreference(&work->pending_flip_obj->base);
9310 drm_gem_object_unreference(&work->old_fb_obj->base);
9311
9312 intel_update_fbc(dev);
9313 mutex_unlock(&dev->struct_mutex);
9314
9315 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9316
9317 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9318 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9319
9320 kfree(work);
9321 }
9322
9323 static void do_intel_finish_page_flip(struct drm_device *dev,
9324 struct drm_crtc *crtc)
9325 {
9326 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9327 struct intel_unpin_work *work;
9328 unsigned long flags;
9329
9330 /* Ignore early vblank irqs */
9331 if (intel_crtc == NULL)
9332 return;
9333
9334 spin_lock_irqsave(&dev->event_lock, flags);
9335 work = intel_crtc->unpin_work;
9336
9337 /* Ensure we don't miss a work->pending update ... */
9338 smp_rmb();
9339
9340 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9341 spin_unlock_irqrestore(&dev->event_lock, flags);
9342 return;
9343 }
9344
9345 page_flip_completed(intel_crtc);
9346
9347 spin_unlock_irqrestore(&dev->event_lock, flags);
9348 }
9349
9350 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9351 {
9352 struct drm_i915_private *dev_priv = dev->dev_private;
9353 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9354
9355 do_intel_finish_page_flip(dev, crtc);
9356 }
9357
9358 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9359 {
9360 struct drm_i915_private *dev_priv = dev->dev_private;
9361 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9362
9363 do_intel_finish_page_flip(dev, crtc);
9364 }
9365
9366 /* Is 'a' after or equal to 'b'? */
9367 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9368 {
9369 return !((a - b) & 0x80000000);
9370 }
9371
9372 static bool page_flip_finished(struct intel_crtc *crtc)
9373 {
9374 struct drm_device *dev = crtc->base.dev;
9375 struct drm_i915_private *dev_priv = dev->dev_private;
9376
9377 /*
9378 * The relevant registers doen't exist on pre-ctg.
9379 * As the flip done interrupt doesn't trigger for mmio
9380 * flips on gmch platforms, a flip count check isn't
9381 * really needed there. But since ctg has the registers,
9382 * include it in the check anyway.
9383 */
9384 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9385 return true;
9386
9387 /*
9388 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9389 * used the same base address. In that case the mmio flip might
9390 * have completed, but the CS hasn't even executed the flip yet.
9391 *
9392 * A flip count check isn't enough as the CS might have updated
9393 * the base address just after start of vblank, but before we
9394 * managed to process the interrupt. This means we'd complete the
9395 * CS flip too soon.
9396 *
9397 * Combining both checks should get us a good enough result. It may
9398 * still happen that the CS flip has been executed, but has not
9399 * yet actually completed. But in case the base address is the same
9400 * anyway, we don't really care.
9401 */
9402 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9403 crtc->unpin_work->gtt_offset &&
9404 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9405 crtc->unpin_work->flip_count);
9406 }
9407
9408 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9409 {
9410 struct drm_i915_private *dev_priv = dev->dev_private;
9411 struct intel_crtc *intel_crtc =
9412 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9413 unsigned long flags;
9414
9415 /* NB: An MMIO update of the plane base pointer will also
9416 * generate a page-flip completion irq, i.e. every modeset
9417 * is also accompanied by a spurious intel_prepare_page_flip().
9418 */
9419 spin_lock_irqsave(&dev->event_lock, flags);
9420 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9421 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9422 spin_unlock_irqrestore(&dev->event_lock, flags);
9423 }
9424
9425 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9426 {
9427 /* Ensure that the work item is consistent when activating it ... */
9428 smp_wmb();
9429 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9430 /* and that it is marked active as soon as the irq could fire. */
9431 smp_wmb();
9432 }
9433
9434 static int intel_gen2_queue_flip(struct drm_device *dev,
9435 struct drm_crtc *crtc,
9436 struct drm_framebuffer *fb,
9437 struct drm_i915_gem_object *obj,
9438 struct intel_engine_cs *ring,
9439 uint32_t flags)
9440 {
9441 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9442 u32 flip_mask;
9443 int ret;
9444
9445 ret = intel_ring_begin(ring, 6);
9446 if (ret)
9447 return ret;
9448
9449 /* Can't queue multiple flips, so wait for the previous
9450 * one to finish before executing the next.
9451 */
9452 if (intel_crtc->plane)
9453 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9454 else
9455 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9456 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9457 intel_ring_emit(ring, MI_NOOP);
9458 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9459 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9460 intel_ring_emit(ring, fb->pitches[0]);
9461 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9462 intel_ring_emit(ring, 0); /* aux display base address, unused */
9463
9464 intel_mark_page_flip_active(intel_crtc);
9465 __intel_ring_advance(ring);
9466 return 0;
9467 }
9468
9469 static int intel_gen3_queue_flip(struct drm_device *dev,
9470 struct drm_crtc *crtc,
9471 struct drm_framebuffer *fb,
9472 struct drm_i915_gem_object *obj,
9473 struct intel_engine_cs *ring,
9474 uint32_t flags)
9475 {
9476 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9477 u32 flip_mask;
9478 int ret;
9479
9480 ret = intel_ring_begin(ring, 6);
9481 if (ret)
9482 return ret;
9483
9484 if (intel_crtc->plane)
9485 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9486 else
9487 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9488 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9489 intel_ring_emit(ring, MI_NOOP);
9490 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9491 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9492 intel_ring_emit(ring, fb->pitches[0]);
9493 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9494 intel_ring_emit(ring, MI_NOOP);
9495
9496 intel_mark_page_flip_active(intel_crtc);
9497 __intel_ring_advance(ring);
9498 return 0;
9499 }
9500
9501 static int intel_gen4_queue_flip(struct drm_device *dev,
9502 struct drm_crtc *crtc,
9503 struct drm_framebuffer *fb,
9504 struct drm_i915_gem_object *obj,
9505 struct intel_engine_cs *ring,
9506 uint32_t flags)
9507 {
9508 struct drm_i915_private *dev_priv = dev->dev_private;
9509 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9510 uint32_t pf, pipesrc;
9511 int ret;
9512
9513 ret = intel_ring_begin(ring, 4);
9514 if (ret)
9515 return ret;
9516
9517 /* i965+ uses the linear or tiled offsets from the
9518 * Display Registers (which do not change across a page-flip)
9519 * so we need only reprogram the base address.
9520 */
9521 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9522 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9523 intel_ring_emit(ring, fb->pitches[0]);
9524 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9525 obj->tiling_mode);
9526
9527 /* XXX Enabling the panel-fitter across page-flip is so far
9528 * untested on non-native modes, so ignore it for now.
9529 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9530 */
9531 pf = 0;
9532 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9533 intel_ring_emit(ring, pf | pipesrc);
9534
9535 intel_mark_page_flip_active(intel_crtc);
9536 __intel_ring_advance(ring);
9537 return 0;
9538 }
9539
9540 static int intel_gen6_queue_flip(struct drm_device *dev,
9541 struct drm_crtc *crtc,
9542 struct drm_framebuffer *fb,
9543 struct drm_i915_gem_object *obj,
9544 struct intel_engine_cs *ring,
9545 uint32_t flags)
9546 {
9547 struct drm_i915_private *dev_priv = dev->dev_private;
9548 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9549 uint32_t pf, pipesrc;
9550 int ret;
9551
9552 ret = intel_ring_begin(ring, 4);
9553 if (ret)
9554 return ret;
9555
9556 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9557 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9558 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9559 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9560
9561 /* Contrary to the suggestions in the documentation,
9562 * "Enable Panel Fitter" does not seem to be required when page
9563 * flipping with a non-native mode, and worse causes a normal
9564 * modeset to fail.
9565 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9566 */
9567 pf = 0;
9568 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9569 intel_ring_emit(ring, pf | pipesrc);
9570
9571 intel_mark_page_flip_active(intel_crtc);
9572 __intel_ring_advance(ring);
9573 return 0;
9574 }
9575
9576 static int intel_gen7_queue_flip(struct drm_device *dev,
9577 struct drm_crtc *crtc,
9578 struct drm_framebuffer *fb,
9579 struct drm_i915_gem_object *obj,
9580 struct intel_engine_cs *ring,
9581 uint32_t flags)
9582 {
9583 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9584 uint32_t plane_bit = 0;
9585 int len, ret;
9586
9587 switch (intel_crtc->plane) {
9588 case PLANE_A:
9589 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9590 break;
9591 case PLANE_B:
9592 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9593 break;
9594 case PLANE_C:
9595 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9596 break;
9597 default:
9598 WARN_ONCE(1, "unknown plane in flip command\n");
9599 return -ENODEV;
9600 }
9601
9602 len = 4;
9603 if (ring->id == RCS) {
9604 len += 6;
9605 /*
9606 * On Gen 8, SRM is now taking an extra dword to accommodate
9607 * 48bits addresses, and we need a NOOP for the batch size to
9608 * stay even.
9609 */
9610 if (IS_GEN8(dev))
9611 len += 2;
9612 }
9613
9614 /*
9615 * BSpec MI_DISPLAY_FLIP for IVB:
9616 * "The full packet must be contained within the same cache line."
9617 *
9618 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9619 * cacheline, if we ever start emitting more commands before
9620 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9621 * then do the cacheline alignment, and finally emit the
9622 * MI_DISPLAY_FLIP.
9623 */
9624 ret = intel_ring_cacheline_align(ring);
9625 if (ret)
9626 return ret;
9627
9628 ret = intel_ring_begin(ring, len);
9629 if (ret)
9630 return ret;
9631
9632 /* Unmask the flip-done completion message. Note that the bspec says that
9633 * we should do this for both the BCS and RCS, and that we must not unmask
9634 * more than one flip event at any time (or ensure that one flip message
9635 * can be sent by waiting for flip-done prior to queueing new flips).
9636 * Experimentation says that BCS works despite DERRMR masking all
9637 * flip-done completion events and that unmasking all planes at once
9638 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9639 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9640 */
9641 if (ring->id == RCS) {
9642 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9643 intel_ring_emit(ring, DERRMR);
9644 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9645 DERRMR_PIPEB_PRI_FLIP_DONE |
9646 DERRMR_PIPEC_PRI_FLIP_DONE));
9647 if (IS_GEN8(dev))
9648 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9649 MI_SRM_LRM_GLOBAL_GTT);
9650 else
9651 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9652 MI_SRM_LRM_GLOBAL_GTT);
9653 intel_ring_emit(ring, DERRMR);
9654 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9655 if (IS_GEN8(dev)) {
9656 intel_ring_emit(ring, 0);
9657 intel_ring_emit(ring, MI_NOOP);
9658 }
9659 }
9660
9661 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9662 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9663 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9664 intel_ring_emit(ring, (MI_NOOP));
9665
9666 intel_mark_page_flip_active(intel_crtc);
9667 __intel_ring_advance(ring);
9668 return 0;
9669 }
9670
9671 static bool use_mmio_flip(struct intel_engine_cs *ring,
9672 struct drm_i915_gem_object *obj)
9673 {
9674 /*
9675 * This is not being used for older platforms, because
9676 * non-availability of flip done interrupt forces us to use
9677 * CS flips. Older platforms derive flip done using some clever
9678 * tricks involving the flip_pending status bits and vblank irqs.
9679 * So using MMIO flips there would disrupt this mechanism.
9680 */
9681
9682 if (ring == NULL)
9683 return true;
9684
9685 if (INTEL_INFO(ring->dev)->gen < 5)
9686 return false;
9687
9688 if (i915.use_mmio_flip < 0)
9689 return false;
9690 else if (i915.use_mmio_flip > 0)
9691 return true;
9692 else if (i915.enable_execlists)
9693 return true;
9694 else
9695 return ring != obj->ring;
9696 }
9697
9698 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9699 {
9700 struct drm_device *dev = intel_crtc->base.dev;
9701 struct drm_i915_private *dev_priv = dev->dev_private;
9702 struct intel_framebuffer *intel_fb =
9703 to_intel_framebuffer(intel_crtc->base.primary->fb);
9704 struct drm_i915_gem_object *obj = intel_fb->obj;
9705 u32 dspcntr;
9706 u32 reg;
9707
9708 intel_mark_page_flip_active(intel_crtc);
9709
9710 reg = DSPCNTR(intel_crtc->plane);
9711 dspcntr = I915_READ(reg);
9712
9713 if (INTEL_INFO(dev)->gen >= 4) {
9714 if (obj->tiling_mode != I915_TILING_NONE)
9715 dspcntr |= DISPPLANE_TILED;
9716 else
9717 dspcntr &= ~DISPPLANE_TILED;
9718 }
9719 I915_WRITE(reg, dspcntr);
9720
9721 I915_WRITE(DSPSURF(intel_crtc->plane),
9722 intel_crtc->unpin_work->gtt_offset);
9723 POSTING_READ(DSPSURF(intel_crtc->plane));
9724 }
9725
9726 static int intel_postpone_flip(struct drm_i915_gem_object *obj)
9727 {
9728 struct intel_engine_cs *ring;
9729 int ret;
9730
9731 lockdep_assert_held(&obj->base.dev->struct_mutex);
9732
9733 if (!obj->last_write_seqno)
9734 return 0;
9735
9736 ring = obj->ring;
9737
9738 if (i915_seqno_passed(ring->get_seqno(ring, true),
9739 obj->last_write_seqno))
9740 return 0;
9741
9742 ret = i915_gem_check_olr(ring, obj->last_write_seqno);
9743 if (ret)
9744 return ret;
9745
9746 if (WARN_ON(!ring->irq_get(ring)))
9747 return 0;
9748
9749 return 1;
9750 }
9751
9752 void intel_notify_mmio_flip(struct intel_engine_cs *ring)
9753 {
9754 struct drm_i915_private *dev_priv = to_i915(ring->dev);
9755 struct intel_crtc *intel_crtc;
9756 unsigned long irq_flags;
9757 u32 seqno;
9758
9759 seqno = ring->get_seqno(ring, false);
9760
9761 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9762 for_each_intel_crtc(ring->dev, intel_crtc) {
9763 struct intel_mmio_flip *mmio_flip;
9764
9765 mmio_flip = &intel_crtc->mmio_flip;
9766 if (mmio_flip->seqno == 0)
9767 continue;
9768
9769 if (ring->id != mmio_flip->ring_id)
9770 continue;
9771
9772 if (i915_seqno_passed(seqno, mmio_flip->seqno)) {
9773 intel_do_mmio_flip(intel_crtc);
9774 mmio_flip->seqno = 0;
9775 ring->irq_put(ring);
9776 }
9777 }
9778 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9779 }
9780
9781 static int intel_queue_mmio_flip(struct drm_device *dev,
9782 struct drm_crtc *crtc,
9783 struct drm_framebuffer *fb,
9784 struct drm_i915_gem_object *obj,
9785 struct intel_engine_cs *ring,
9786 uint32_t flags)
9787 {
9788 struct drm_i915_private *dev_priv = dev->dev_private;
9789 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9790 unsigned long irq_flags;
9791 int ret;
9792
9793 if (WARN_ON(intel_crtc->mmio_flip.seqno))
9794 return -EBUSY;
9795
9796 ret = intel_postpone_flip(obj);
9797 if (ret < 0)
9798 return ret;
9799 if (ret == 0) {
9800 intel_do_mmio_flip(intel_crtc);
9801 return 0;
9802 }
9803
9804 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9805 intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
9806 intel_crtc->mmio_flip.ring_id = obj->ring->id;
9807 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9808
9809 /*
9810 * Double check to catch cases where irq fired before
9811 * mmio flip data was ready
9812 */
9813 intel_notify_mmio_flip(obj->ring);
9814 return 0;
9815 }
9816
9817 static int intel_default_queue_flip(struct drm_device *dev,
9818 struct drm_crtc *crtc,
9819 struct drm_framebuffer *fb,
9820 struct drm_i915_gem_object *obj,
9821 struct intel_engine_cs *ring,
9822 uint32_t flags)
9823 {
9824 return -ENODEV;
9825 }
9826
9827 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9828 struct drm_crtc *crtc)
9829 {
9830 struct drm_i915_private *dev_priv = dev->dev_private;
9831 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9832 struct intel_unpin_work *work = intel_crtc->unpin_work;
9833 u32 addr;
9834
9835 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9836 return true;
9837
9838 if (!work->enable_stall_check)
9839 return false;
9840
9841 if (work->flip_ready_vblank == 0) {
9842 if (work->flip_queued_ring &&
9843 !i915_seqno_passed(work->flip_queued_ring->get_seqno(work->flip_queued_ring, true),
9844 work->flip_queued_seqno))
9845 return false;
9846
9847 work->flip_ready_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9848 }
9849
9850 if (drm_vblank_count(dev, intel_crtc->pipe) - work->flip_ready_vblank < 3)
9851 return false;
9852
9853 /* Potential stall - if we see that the flip has happened,
9854 * assume a missed interrupt. */
9855 if (INTEL_INFO(dev)->gen >= 4)
9856 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9857 else
9858 addr = I915_READ(DSPADDR(intel_crtc->plane));
9859
9860 /* There is a potential issue here with a false positive after a flip
9861 * to the same address. We could address this by checking for a
9862 * non-incrementing frame counter.
9863 */
9864 return addr == work->gtt_offset;
9865 }
9866
9867 void intel_check_page_flip(struct drm_device *dev, int pipe)
9868 {
9869 struct drm_i915_private *dev_priv = dev->dev_private;
9870 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9871 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9872 unsigned long flags;
9873
9874 if (crtc == NULL)
9875 return;
9876
9877 spin_lock_irqsave(&dev->event_lock, flags);
9878 if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9879 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9880 intel_crtc->unpin_work->flip_queued_vblank, drm_vblank_count(dev, pipe));
9881 page_flip_completed(intel_crtc);
9882 }
9883 spin_unlock_irqrestore(&dev->event_lock, flags);
9884 }
9885
9886 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9887 struct drm_framebuffer *fb,
9888 struct drm_pending_vblank_event *event,
9889 uint32_t page_flip_flags)
9890 {
9891 struct drm_device *dev = crtc->dev;
9892 struct drm_i915_private *dev_priv = dev->dev_private;
9893 struct drm_framebuffer *old_fb = crtc->primary->fb;
9894 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9895 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9896 enum pipe pipe = intel_crtc->pipe;
9897 struct intel_unpin_work *work;
9898 struct intel_engine_cs *ring;
9899 unsigned long flags;
9900 int ret;
9901
9902 //trigger software GT busyness calculation
9903 gen8_flip_interrupt(dev);
9904
9905 /*
9906 * drm_mode_page_flip_ioctl() should already catch this, but double
9907 * check to be safe. In the future we may enable pageflipping from
9908 * a disabled primary plane.
9909 */
9910 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9911 return -EBUSY;
9912
9913 /* Can't change pixel format via MI display flips. */
9914 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9915 return -EINVAL;
9916
9917 /*
9918 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9919 * Note that pitch changes could also affect these register.
9920 */
9921 if (INTEL_INFO(dev)->gen > 3 &&
9922 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9923 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9924 return -EINVAL;
9925
9926 if (i915_terminally_wedged(&dev_priv->gpu_error))
9927 goto out_hang;
9928
9929 work = kzalloc(sizeof(*work), GFP_KERNEL);
9930 if (work == NULL)
9931 return -ENOMEM;
9932
9933 work->event = event;
9934 work->crtc = crtc;
9935 work->old_fb_obj = intel_fb_obj(old_fb);
9936 INIT_WORK(&work->work, intel_unpin_work_fn);
9937
9938 ret = drm_crtc_vblank_get(crtc);
9939 if (ret)
9940 goto free_work;
9941
9942 /* We borrow the event spin lock for protecting unpin_work */
9943 spin_lock_irqsave(&dev->event_lock, flags);
9944 if (intel_crtc->unpin_work) {
9945 /* Before declaring the flip queue wedged, check if
9946 * the hardware completed the operation behind our backs.
9947 */
9948 if (__intel_pageflip_stall_check(dev, crtc)) {
9949 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9950 page_flip_completed(intel_crtc);
9951 } else {
9952 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9953 spin_unlock_irqrestore(&dev->event_lock, flags);
9954
9955 drm_crtc_vblank_put(crtc);
9956 kfree(work);
9957 return -EBUSY;
9958 }
9959 }
9960 intel_crtc->unpin_work = work;
9961 spin_unlock_irqrestore(&dev->event_lock, flags);
9962
9963 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9964 flush_workqueue(dev_priv->wq);
9965
9966 ret = i915_mutex_lock_interruptible(dev);
9967 if (ret)
9968 goto cleanup;
9969
9970 /* Reference the objects for the scheduled work. */
9971 drm_gem_object_reference(&work->old_fb_obj->base);
9972 drm_gem_object_reference(&obj->base);
9973
9974 crtc->primary->fb = fb;
9975
9976 work->pending_flip_obj = obj;
9977
9978 atomic_inc(&intel_crtc->unpin_work_count);
9979 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9980
9981 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9982 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9983
9984 if (IS_VALLEYVIEW(dev)) {
9985 ring = &dev_priv->ring[BCS];
9986 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9987 /* vlv: DISPLAY_FLIP fails to change tiling */
9988 ring = NULL;
9989 } else if (IS_IVYBRIDGE(dev)) {
9990 ring = &dev_priv->ring[BCS];
9991 } else if (INTEL_INFO(dev)->gen >= 7) {
9992 ring = obj->ring;
9993 if (ring == NULL || ring->id != RCS)
9994 ring = &dev_priv->ring[BCS];
9995 } else {
9996 ring = &dev_priv->ring[RCS];
9997 }
9998
9999 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
10000 if (ret)
10001 goto cleanup_pending;
10002
10003 work->gtt_offset =
10004 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
10005
10006 if (use_mmio_flip(ring, obj)) {
10007 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
10008 page_flip_flags);
10009 if (ret)
10010 goto cleanup_unpin;
10011
10012 work->flip_queued_seqno = obj->last_write_seqno;
10013 work->flip_queued_ring = obj->ring;
10014 } else {
10015 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
10016 page_flip_flags);
10017 if (ret)
10018 goto cleanup_unpin;
10019
10020 work->flip_queued_seqno = intel_ring_get_seqno(ring);
10021 work->flip_queued_ring = ring;
10022 }
10023
10024 work->flip_queued_vblank = drm_vblank_count(dev, intel_crtc->pipe);
10025 work->enable_stall_check = true;
10026
10027 i915_gem_track_fb(work->old_fb_obj, obj,
10028 INTEL_FRONTBUFFER_PRIMARY(pipe));
10029
10030 intel_disable_fbc(dev);
10031 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
10032 mutex_unlock(&dev->struct_mutex);
10033
10034 trace_i915_flip_request(intel_crtc->plane, obj);
10035
10036 return 0;
10037
10038 cleanup_unpin:
10039 intel_unpin_fb_obj(obj);
10040 cleanup_pending:
10041 atomic_dec(&intel_crtc->unpin_work_count);
10042 crtc->primary->fb = old_fb;
10043 drm_gem_object_unreference(&work->old_fb_obj->base);
10044 drm_gem_object_unreference(&obj->base);
10045 mutex_unlock(&dev->struct_mutex);
10046
10047 cleanup:
10048 spin_lock_irqsave(&dev->event_lock, flags);
10049 intel_crtc->unpin_work = NULL;
10050 spin_unlock_irqrestore(&dev->event_lock, flags);
10051
10052 drm_crtc_vblank_put(crtc);
10053 free_work:
10054 kfree(work);
10055
10056 if (ret == -EIO) {
10057 out_hang:
10058 intel_crtc_wait_for_pending_flips(crtc);
10059 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
10060 if (ret == 0 && event) {
10061 spin_lock_irqsave(&dev->event_lock, flags);
10062 drm_send_vblank_event(dev, pipe, event);
10063 spin_unlock_irqrestore(&dev->event_lock, flags);
10064 }
10065 }
10066 return ret;
10067 }
10068
10069 static struct drm_crtc_helper_funcs intel_helper_funcs = {
10070 .mode_set_base_atomic = intel_pipe_set_base_atomic,
10071 .load_lut = intel_crtc_load_lut,
10072 };
10073
10074 /**
10075 * intel_modeset_update_staged_output_state
10076 *
10077 * Updates the staged output configuration state, e.g. after we've read out the
10078 * current hw state.
10079 */
10080 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
10081 {
10082 struct intel_crtc *crtc;
10083 struct intel_encoder *encoder;
10084 struct intel_connector *connector;
10085
10086 list_for_each_entry(connector, &dev->mode_config.connector_list,
10087 base.head) {
10088 connector->new_encoder =
10089 to_intel_encoder(connector->base.encoder);
10090 }
10091
10092 for_each_intel_encoder(dev, encoder) {
10093 encoder->new_crtc =
10094 to_intel_crtc(encoder->base.crtc);
10095 }
10096
10097 for_each_intel_crtc(dev, crtc) {
10098 crtc->new_enabled = crtc->base.enabled;
10099
10100 if (crtc->new_enabled)
10101 crtc->new_config = &crtc->config;
10102 else
10103 crtc->new_config = NULL;
10104 }
10105 }
10106
10107 /**
10108 * intel_modeset_commit_output_state
10109 *
10110 * This function copies the stage display pipe configuration to the real one.
10111 */
10112 static void intel_modeset_commit_output_state(struct drm_device *dev)
10113 {
10114 struct intel_crtc *crtc;
10115 struct intel_encoder *encoder;
10116 struct intel_connector *connector;
10117
10118 list_for_each_entry(connector, &dev->mode_config.connector_list,
10119 base.head) {
10120 connector->base.encoder = &connector->new_encoder->base;
10121 }
10122
10123 for_each_intel_encoder(dev, encoder) {
10124 encoder->base.crtc = &encoder->new_crtc->base;
10125 }
10126
10127 for_each_intel_crtc(dev, crtc) {
10128 crtc->base.enabled = crtc->new_enabled;
10129 }
10130 }
10131
10132 static void
10133 connected_sink_compute_bpp(struct intel_connector *connector,
10134 struct intel_crtc_config *pipe_config)
10135 {
10136 int bpp = pipe_config->pipe_bpp;
10137
10138 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10139 connector->base.base.id,
10140 connector->base.name);
10141
10142 /* Don't use an invalid EDID bpc value */
10143 if (connector->base.display_info.bpc &&
10144 connector->base.display_info.bpc * 3 < bpp) {
10145 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10146 bpp, connector->base.display_info.bpc*3);
10147 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
10148 }
10149
10150 /* Clamp bpp to 8 on screens without EDID 1.4 */
10151 if (connector->base.display_info.bpc == 0 && bpp > 24) {
10152 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10153 bpp);
10154 pipe_config->pipe_bpp = 24;
10155 }
10156 }
10157
10158 static int
10159 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10160 struct drm_framebuffer *fb,
10161 struct intel_crtc_config *pipe_config)
10162 {
10163 struct drm_device *dev = crtc->base.dev;
10164 struct intel_connector *connector;
10165 int bpp;
10166
10167 switch (fb->pixel_format) {
10168 case DRM_FORMAT_C8:
10169 bpp = 8*3; /* since we go through a colormap */
10170 break;
10171 case DRM_FORMAT_XRGB1555:
10172 case DRM_FORMAT_ARGB1555:
10173 /* checked in intel_framebuffer_init already */
10174 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10175 return -EINVAL;
10176 case DRM_FORMAT_RGB565:
10177 bpp = 6*3; /* min is 18bpp */
10178 break;
10179 case DRM_FORMAT_XBGR8888:
10180 case DRM_FORMAT_ABGR8888:
10181 /* checked in intel_framebuffer_init already */
10182 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10183 return -EINVAL;
10184 case DRM_FORMAT_XRGB8888:
10185 case DRM_FORMAT_ARGB8888:
10186 bpp = 8*3;
10187 break;
10188 case DRM_FORMAT_XRGB2101010:
10189 case DRM_FORMAT_ARGB2101010:
10190 case DRM_FORMAT_XBGR2101010:
10191 case DRM_FORMAT_ABGR2101010:
10192 /* checked in intel_framebuffer_init already */
10193 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10194 return -EINVAL;
10195 bpp = 10*3;
10196 break;
10197 /* TODO: gen4+ supports 16 bpc floating point, too. */
10198 default:
10199 DRM_DEBUG_KMS("unsupported depth\n");
10200 return -EINVAL;
10201 }
10202
10203 pipe_config->pipe_bpp = bpp;
10204
10205 /* Clamp display bpp to EDID value */
10206 list_for_each_entry(connector, &dev->mode_config.connector_list,
10207 base.head) {
10208 if (!connector->new_encoder ||
10209 connector->new_encoder->new_crtc != crtc)
10210 continue;
10211
10212 connected_sink_compute_bpp(connector, pipe_config);
10213 }
10214
10215 return bpp;
10216 }
10217
10218 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10219 {
10220 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10221 "type: 0x%x flags: 0x%x\n",
10222 mode->crtc_clock,
10223 mode->crtc_hdisplay, mode->crtc_hsync_start,
10224 mode->crtc_hsync_end, mode->crtc_htotal,
10225 mode->crtc_vdisplay, mode->crtc_vsync_start,
10226 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10227 }
10228
10229 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10230 struct intel_crtc_config *pipe_config,
10231 const char *context)
10232 {
10233 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10234 context, pipe_name(crtc->pipe));
10235
10236 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10237 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10238 pipe_config->pipe_bpp, pipe_config->dither);
10239 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10240 pipe_config->has_pch_encoder,
10241 pipe_config->fdi_lanes,
10242 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10243 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10244 pipe_config->fdi_m_n.tu);
10245 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10246 pipe_config->has_dp_encoder,
10247 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10248 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10249 pipe_config->dp_m_n.tu);
10250
10251 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10252 pipe_config->has_dp_encoder,
10253 pipe_config->dp_m2_n2.gmch_m,
10254 pipe_config->dp_m2_n2.gmch_n,
10255 pipe_config->dp_m2_n2.link_m,
10256 pipe_config->dp_m2_n2.link_n,
10257 pipe_config->dp_m2_n2.tu);
10258
10259 DRM_DEBUG_KMS("requested mode:\n");
10260 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
10261 DRM_DEBUG_KMS("adjusted mode:\n");
10262 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
10263 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
10264 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10265 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10266 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10267 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10268 pipe_config->gmch_pfit.control,
10269 pipe_config->gmch_pfit.pgm_ratios,
10270 pipe_config->gmch_pfit.lvds_border_bits);
10271 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10272 pipe_config->pch_pfit.pos,
10273 pipe_config->pch_pfit.size,
10274 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10275 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10276 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10277 }
10278
10279 static bool encoders_cloneable(const struct intel_encoder *a,
10280 const struct intel_encoder *b)
10281 {
10282 /* masks could be asymmetric, so check both ways */
10283 return a == b || (a->cloneable & (1 << b->type) &&
10284 b->cloneable & (1 << a->type));
10285 }
10286
10287 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10288 struct intel_encoder *encoder)
10289 {
10290 struct drm_device *dev = crtc->base.dev;
10291 struct intel_encoder *source_encoder;
10292
10293 for_each_intel_encoder(dev, source_encoder) {
10294 if (source_encoder->new_crtc != crtc)
10295 continue;
10296
10297 if (!encoders_cloneable(encoder, source_encoder))
10298 return false;
10299 }
10300
10301 return true;
10302 }
10303
10304 static bool check_encoder_cloning(struct intel_crtc *crtc)
10305 {
10306 struct drm_device *dev = crtc->base.dev;
10307 struct intel_encoder *encoder;
10308
10309 for_each_intel_encoder(dev, encoder) {
10310 if (encoder->new_crtc != crtc)
10311 continue;
10312
10313 if (!check_single_encoder_cloning(crtc, encoder))
10314 return false;
10315 }
10316
10317 return true;
10318 }
10319
10320 static struct intel_crtc_config *
10321 intel_modeset_pipe_config(struct drm_crtc *crtc,
10322 struct drm_framebuffer *fb,
10323 struct drm_display_mode *mode)
10324 {
10325 struct drm_device *dev = crtc->dev;
10326 struct intel_encoder *encoder;
10327 struct intel_crtc_config *pipe_config;
10328 int plane_bpp, ret = -EINVAL;
10329 bool retry = true;
10330
10331 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10332 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10333 return ERR_PTR(-EINVAL);
10334 }
10335
10336 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10337 if (!pipe_config)
10338 return ERR_PTR(-ENOMEM);
10339
10340 drm_mode_copy(&pipe_config->adjusted_mode, mode);
10341 drm_mode_copy(&pipe_config->requested_mode, mode);
10342
10343 pipe_config->cpu_transcoder =
10344 (enum transcoder) to_intel_crtc(crtc)->pipe;
10345 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10346
10347 /*
10348 * Sanitize sync polarity flags based on requested ones. If neither
10349 * positive or negative polarity is requested, treat this as meaning
10350 * negative polarity.
10351 */
10352 if (!(pipe_config->adjusted_mode.flags &
10353 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10354 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10355
10356 if (!(pipe_config->adjusted_mode.flags &
10357 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10358 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10359
10360 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10361 * plane pixel format and any sink constraints into account. Returns the
10362 * source plane bpp so that dithering can be selected on mismatches
10363 * after encoders and crtc also have had their say. */
10364 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10365 fb, pipe_config);
10366 if (plane_bpp < 0)
10367 goto fail;
10368
10369 /*
10370 * Determine the real pipe dimensions. Note that stereo modes can
10371 * increase the actual pipe size due to the frame doubling and
10372 * insertion of additional space for blanks between the frame. This
10373 * is stored in the crtc timings. We use the requested mode to do this
10374 * computation to clearly distinguish it from the adjusted mode, which
10375 * can be changed by the connectors in the below retry loop.
10376 */
10377 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
10378 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
10379 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
10380
10381 encoder_retry:
10382 /* Ensure the port clock defaults are reset when retrying. */
10383 pipe_config->port_clock = 0;
10384 pipe_config->pixel_multiplier = 1;
10385
10386 /* Fill in default crtc timings, allow encoders to overwrite them. */
10387 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
10388
10389 /* Pass our mode to the connectors and the CRTC to give them a chance to
10390 * adjust it according to limitations or connector properties, and also
10391 * a chance to reject the mode entirely.
10392 */
10393 for_each_intel_encoder(dev, encoder) {
10394
10395 if (&encoder->new_crtc->base != crtc)
10396 continue;
10397
10398 if (!(encoder->compute_config(encoder, pipe_config))) {
10399 DRM_DEBUG_KMS("Encoder config failure\n");
10400 goto fail;
10401 }
10402 }
10403
10404 /* Set default port clock if not overwritten by the encoder. Needs to be
10405 * done afterwards in case the encoder adjusts the mode. */
10406 if (!pipe_config->port_clock)
10407 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10408 * pipe_config->pixel_multiplier;
10409
10410 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10411 if (ret < 0) {
10412 DRM_DEBUG_KMS("CRTC fixup failed\n");
10413 goto fail;
10414 }
10415
10416 if (ret == RETRY) {
10417 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10418 ret = -EINVAL;
10419 goto fail;
10420 }
10421
10422 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10423 retry = false;
10424 goto encoder_retry;
10425 }
10426
10427 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10428 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10429 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10430
10431 return pipe_config;
10432 fail:
10433 kfree(pipe_config);
10434 return ERR_PTR(ret);
10435 }
10436
10437 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10438 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10439 static void
10440 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10441 unsigned *prepare_pipes, unsigned *disable_pipes)
10442 {
10443 struct intel_crtc *intel_crtc;
10444 struct drm_device *dev = crtc->dev;
10445 struct intel_encoder *encoder;
10446 struct intel_connector *connector;
10447 struct drm_crtc *tmp_crtc;
10448
10449 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10450
10451 /* Check which crtcs have changed outputs connected to them, these need
10452 * to be part of the prepare_pipes mask. We don't (yet) support global
10453 * modeset across multiple crtcs, so modeset_pipes will only have one
10454 * bit set at most. */
10455 list_for_each_entry(connector, &dev->mode_config.connector_list,
10456 base.head) {
10457 if (connector->base.encoder == &connector->new_encoder->base)
10458 continue;
10459
10460 if (connector->base.encoder) {
10461 tmp_crtc = connector->base.encoder->crtc;
10462
10463 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10464 }
10465
10466 if (connector->new_encoder)
10467 *prepare_pipes |=
10468 1 << connector->new_encoder->new_crtc->pipe;
10469 }
10470
10471 for_each_intel_encoder(dev, encoder) {
10472 if (encoder->base.crtc == &encoder->new_crtc->base)
10473 continue;
10474
10475 if (encoder->base.crtc) {
10476 tmp_crtc = encoder->base.crtc;
10477
10478 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10479 }
10480
10481 if (encoder->new_crtc)
10482 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10483 }
10484
10485 /* Check for pipes that will be enabled/disabled ... */
10486 for_each_intel_crtc(dev, intel_crtc) {
10487 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10488 continue;
10489
10490 if (!intel_crtc->new_enabled)
10491 *disable_pipes |= 1 << intel_crtc->pipe;
10492 else
10493 *prepare_pipes |= 1 << intel_crtc->pipe;
10494 }
10495
10496
10497 /* set_mode is also used to update properties on life display pipes. */
10498 intel_crtc = to_intel_crtc(crtc);
10499 if (intel_crtc->new_enabled)
10500 *prepare_pipes |= 1 << intel_crtc->pipe;
10501
10502 /*
10503 * For simplicity do a full modeset on any pipe where the output routing
10504 * changed. We could be more clever, but that would require us to be
10505 * more careful with calling the relevant encoder->mode_set functions.
10506 */
10507 if (*prepare_pipes)
10508 *modeset_pipes = *prepare_pipes;
10509
10510 /* ... and mask these out. */
10511 *modeset_pipes &= ~(*disable_pipes);
10512 *prepare_pipes &= ~(*disable_pipes);
10513
10514 /*
10515 * HACK: We don't (yet) fully support global modesets. intel_set_config
10516 * obies this rule, but the modeset restore mode of
10517 * intel_modeset_setup_hw_state does not.
10518 */
10519 *modeset_pipes &= 1 << intel_crtc->pipe;
10520 *prepare_pipes &= 1 << intel_crtc->pipe;
10521
10522 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10523 *modeset_pipes, *prepare_pipes, *disable_pipes);
10524 }
10525
10526 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10527 {
10528 struct drm_encoder *encoder;
10529 struct drm_device *dev = crtc->dev;
10530
10531 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10532 if (encoder->crtc == crtc)
10533 return true;
10534
10535 return false;
10536 }
10537
10538 static void
10539 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10540 {
10541 struct intel_encoder *intel_encoder;
10542 struct intel_crtc *intel_crtc;
10543 struct drm_connector *connector;
10544
10545 for_each_intel_encoder(dev, intel_encoder) {
10546 if (!intel_encoder->base.crtc)
10547 continue;
10548
10549 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10550
10551 if (prepare_pipes & (1 << intel_crtc->pipe))
10552 intel_encoder->connectors_active = false;
10553 }
10554
10555 intel_modeset_commit_output_state(dev);
10556
10557 /* Double check state. */
10558 for_each_intel_crtc(dev, intel_crtc) {
10559 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10560 WARN_ON(intel_crtc->new_config &&
10561 intel_crtc->new_config != &intel_crtc->config);
10562 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10563 }
10564
10565 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10566 if (!connector->encoder || !connector->encoder->crtc)
10567 continue;
10568
10569 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10570
10571 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10572 struct drm_property *dpms_property =
10573 dev->mode_config.dpms_property;
10574
10575 connector->dpms = DRM_MODE_DPMS_ON;
10576 drm_object_property_set_value(&connector->base,
10577 dpms_property,
10578 DRM_MODE_DPMS_ON);
10579
10580 intel_encoder = to_intel_encoder(connector->encoder);
10581 intel_encoder->connectors_active = true;
10582 }
10583 }
10584
10585 }
10586
10587 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10588 {
10589 int diff;
10590
10591 if (clock1 == clock2)
10592 return true;
10593
10594 if (!clock1 || !clock2)
10595 return false;
10596
10597 diff = abs(clock1 - clock2);
10598
10599 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10600 return true;
10601
10602 return false;
10603 }
10604
10605 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10606 list_for_each_entry((intel_crtc), \
10607 &(dev)->mode_config.crtc_list, \
10608 base.head) \
10609 if (mask & (1 <<(intel_crtc)->pipe))
10610
10611 static bool
10612 intel_pipe_config_compare(struct drm_device *dev,
10613 struct intel_crtc_config *current_config,
10614 struct intel_crtc_config *pipe_config)
10615 {
10616 #define PIPE_CONF_CHECK_X(name) \
10617 if (current_config->name != pipe_config->name) { \
10618 DRM_ERROR("mismatch in " #name " " \
10619 "(expected 0x%08x, found 0x%08x)\n", \
10620 current_config->name, \
10621 pipe_config->name); \
10622 return false; \
10623 }
10624
10625 #define PIPE_CONF_CHECK_I(name) \
10626 if (current_config->name != pipe_config->name) { \
10627 DRM_ERROR("mismatch in " #name " " \
10628 "(expected %i, found %i)\n", \
10629 current_config->name, \
10630 pipe_config->name); \
10631 return false; \
10632 }
10633
10634 /* This is required for BDW+ where there is only one set of registers for
10635 * switching between high and low RR.
10636 * This macro can be used whenever a comparison has to be made between one
10637 * hw state and multiple sw state variables.
10638 */
10639 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10640 if ((current_config->name != pipe_config->name) && \
10641 (current_config->alt_name != pipe_config->name)) { \
10642 DRM_ERROR("mismatch in " #name " " \
10643 "(expected %i or %i, found %i)\n", \
10644 current_config->name, \
10645 current_config->alt_name, \
10646 pipe_config->name); \
10647 return false; \
10648 }
10649
10650 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10651 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10652 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10653 "(expected %i, found %i)\n", \
10654 current_config->name & (mask), \
10655 pipe_config->name & (mask)); \
10656 return false; \
10657 }
10658
10659 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10660 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10661 DRM_ERROR("mismatch in " #name " " \
10662 "(expected %i, found %i)\n", \
10663 current_config->name, \
10664 pipe_config->name); \
10665 return false; \
10666 }
10667
10668 #define PIPE_CONF_QUIRK(quirk) \
10669 ((current_config->quirks | pipe_config->quirks) & (quirk))
10670
10671 PIPE_CONF_CHECK_I(cpu_transcoder);
10672
10673 PIPE_CONF_CHECK_I(has_pch_encoder);
10674 PIPE_CONF_CHECK_I(fdi_lanes);
10675 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10676 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10677 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10678 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10679 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10680
10681 PIPE_CONF_CHECK_I(has_dp_encoder);
10682
10683 if (INTEL_INFO(dev)->gen < 8) {
10684 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10685 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10686 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10687 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10688 PIPE_CONF_CHECK_I(dp_m_n.tu);
10689
10690 if (current_config->has_drrs) {
10691 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10692 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10693 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10694 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10695 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10696 }
10697 } else {
10698 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10699 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10700 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10701 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10702 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10703 }
10704
10705 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10706 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10707 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10708 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10709 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10710 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10711
10712 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10713 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10714 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10715 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10716 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10717 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10718
10719 PIPE_CONF_CHECK_I(pixel_multiplier);
10720 PIPE_CONF_CHECK_I(has_hdmi_sink);
10721 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10722 IS_VALLEYVIEW(dev))
10723 PIPE_CONF_CHECK_I(limited_color_range);
10724
10725 PIPE_CONF_CHECK_I(has_audio);
10726
10727 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10728 DRM_MODE_FLAG_INTERLACE);
10729
10730 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10731 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10732 DRM_MODE_FLAG_PHSYNC);
10733 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10734 DRM_MODE_FLAG_NHSYNC);
10735 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10736 DRM_MODE_FLAG_PVSYNC);
10737 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10738 DRM_MODE_FLAG_NVSYNC);
10739 }
10740
10741 PIPE_CONF_CHECK_I(pipe_src_w);
10742 PIPE_CONF_CHECK_I(pipe_src_h);
10743
10744 /*
10745 * FIXME: BIOS likes to set up a cloned config with lvds+external
10746 * screen. Since we don't yet re-compute the pipe config when moving
10747 * just the lvds port away to another pipe the sw tracking won't match.
10748 *
10749 * Proper atomic modesets with recomputed global state will fix this.
10750 * Until then just don't check gmch state for inherited modes.
10751 */
10752 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10753 PIPE_CONF_CHECK_I(gmch_pfit.control);
10754 /* pfit ratios are autocomputed by the hw on gen4+ */
10755 if (INTEL_INFO(dev)->gen < 4)
10756 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10757 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10758 }
10759
10760 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10761 if (current_config->pch_pfit.enabled) {
10762 PIPE_CONF_CHECK_I(pch_pfit.pos);
10763 PIPE_CONF_CHECK_I(pch_pfit.size);
10764 }
10765
10766 /* BDW+ don't expose a synchronous way to read the state */
10767 if (IS_HASWELL(dev))
10768 PIPE_CONF_CHECK_I(ips_enabled);
10769
10770 PIPE_CONF_CHECK_I(double_wide);
10771
10772 PIPE_CONF_CHECK_X(ddi_pll_sel);
10773
10774 PIPE_CONF_CHECK_I(shared_dpll);
10775 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10776 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10777 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10778 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10779 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10780
10781 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10782 PIPE_CONF_CHECK_I(pipe_bpp);
10783
10784 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10785 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10786
10787 #undef PIPE_CONF_CHECK_X
10788 #undef PIPE_CONF_CHECK_I
10789 #undef PIPE_CONF_CHECK_I_ALT
10790 #undef PIPE_CONF_CHECK_FLAGS
10791 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10792 #undef PIPE_CONF_QUIRK
10793
10794 return true;
10795 }
10796
10797 static void
10798 check_connector_state(struct drm_device *dev)
10799 {
10800 struct intel_connector *connector;
10801
10802 list_for_each_entry(connector, &dev->mode_config.connector_list,
10803 base.head) {
10804 /* This also checks the encoder/connector hw state with the
10805 * ->get_hw_state callbacks. */
10806 intel_connector_check_state(connector);
10807
10808 WARN(&connector->new_encoder->base != connector->base.encoder,
10809 "connector's staged encoder doesn't match current encoder\n");
10810 }
10811 }
10812
10813 static void
10814 check_encoder_state(struct drm_device *dev)
10815 {
10816 struct intel_encoder *encoder;
10817 struct intel_connector *connector;
10818
10819 for_each_intel_encoder(dev, encoder) {
10820 bool enabled = false;
10821 bool active = false;
10822 enum pipe pipe, tracked_pipe;
10823
10824 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10825 encoder->base.base.id,
10826 encoder->base.name);
10827
10828 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10829 "encoder's stage crtc doesn't match current crtc\n");
10830 WARN(encoder->connectors_active && !encoder->base.crtc,
10831 "encoder's active_connectors set, but no crtc\n");
10832
10833 list_for_each_entry(connector, &dev->mode_config.connector_list,
10834 base.head) {
10835 if (connector->base.encoder != &encoder->base)
10836 continue;
10837 enabled = true;
10838 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10839 active = true;
10840 }
10841 /*
10842 * for MST connectors if we unplug the connector is gone
10843 * away but the encoder is still connected to a crtc
10844 * until a modeset happens in response to the hotplug.
10845 */
10846 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10847 continue;
10848
10849 WARN(!!encoder->base.crtc != enabled,
10850 "encoder's enabled state mismatch "
10851 "(expected %i, found %i)\n",
10852 !!encoder->base.crtc, enabled);
10853 WARN(active && !encoder->base.crtc,
10854 "active encoder with no crtc\n");
10855
10856 WARN(encoder->connectors_active != active,
10857 "encoder's computed active state doesn't match tracked active state "
10858 "(expected %i, found %i)\n", active, encoder->connectors_active);
10859
10860 active = encoder->get_hw_state(encoder, &pipe);
10861 WARN(active != encoder->connectors_active,
10862 "encoder's hw state doesn't match sw tracking "
10863 "(expected %i, found %i)\n",
10864 encoder->connectors_active, active);
10865
10866 if (!encoder->base.crtc)
10867 continue;
10868
10869 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10870 WARN(active && pipe != tracked_pipe,
10871 "active encoder's pipe doesn't match"
10872 "(expected %i, found %i)\n",
10873 tracked_pipe, pipe);
10874
10875 }
10876 }
10877
10878 static void
10879 check_crtc_state(struct drm_device *dev)
10880 {
10881 struct drm_i915_private *dev_priv = dev->dev_private;
10882 struct intel_crtc *crtc;
10883 struct intel_encoder *encoder;
10884 struct intel_crtc_config pipe_config;
10885
10886 for_each_intel_crtc(dev, crtc) {
10887 bool enabled = false;
10888 bool active = false;
10889
10890 memset(&pipe_config, 0, sizeof(pipe_config));
10891
10892 DRM_DEBUG_KMS("[CRTC:%d]\n",
10893 crtc->base.base.id);
10894
10895 WARN(crtc->active && !crtc->base.enabled,
10896 "active crtc, but not enabled in sw tracking\n");
10897
10898 for_each_intel_encoder(dev, encoder) {
10899 if (encoder->base.crtc != &crtc->base)
10900 continue;
10901 enabled = true;
10902 if (encoder->connectors_active)
10903 active = true;
10904 }
10905
10906 WARN(active != crtc->active,
10907 "crtc's computed active state doesn't match tracked active state "
10908 "(expected %i, found %i)\n", active, crtc->active);
10909 WARN(enabled != crtc->base.enabled,
10910 "crtc's computed enabled state doesn't match tracked enabled state "
10911 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10912
10913 active = dev_priv->display.get_pipe_config(crtc,
10914 &pipe_config);
10915
10916 /* hw state is inconsistent with the pipe quirk */
10917 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10918 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
10919 active = crtc->active;
10920
10921 for_each_intel_encoder(dev, encoder) {
10922 enum pipe pipe;
10923 if (encoder->base.crtc != &crtc->base)
10924 continue;
10925 if (encoder->get_hw_state(encoder, &pipe))
10926 encoder->get_config(encoder, &pipe_config);
10927 }
10928
10929 WARN(crtc->active != active,
10930 "crtc active state doesn't match with hw state "
10931 "(expected %i, found %i)\n", crtc->active, active);
10932
10933 if (active &&
10934 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10935 WARN(1, "pipe state doesn't match!\n");
10936 intel_dump_pipe_config(crtc, &pipe_config,
10937 "[hw state]");
10938 intel_dump_pipe_config(crtc, &crtc->config,
10939 "[sw state]");
10940 }
10941 }
10942 }
10943
10944 static void
10945 check_shared_dpll_state(struct drm_device *dev)
10946 {
10947 struct drm_i915_private *dev_priv = dev->dev_private;
10948 struct intel_crtc *crtc;
10949 struct intel_dpll_hw_state dpll_hw_state;
10950 int i;
10951
10952 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10953 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10954 int enabled_crtcs = 0, active_crtcs = 0;
10955 bool active;
10956
10957 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10958
10959 DRM_DEBUG_KMS("%s\n", pll->name);
10960
10961 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10962
10963 WARN(pll->active > pll->refcount,
10964 "more active pll users than references: %i vs %i\n",
10965 pll->active, pll->refcount);
10966 WARN(pll->active && !pll->on,
10967 "pll in active use but not on in sw tracking\n");
10968 WARN(pll->on && !pll->active,
10969 "pll in on but not on in use in sw tracking\n");
10970 WARN(pll->on != active,
10971 "pll on state mismatch (expected %i, found %i)\n",
10972 pll->on, active);
10973
10974 for_each_intel_crtc(dev, crtc) {
10975 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10976 enabled_crtcs++;
10977 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10978 active_crtcs++;
10979 }
10980 WARN(pll->active != active_crtcs,
10981 "pll active crtcs mismatch (expected %i, found %i)\n",
10982 pll->active, active_crtcs);
10983 WARN(pll->refcount != enabled_crtcs,
10984 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10985 pll->refcount, enabled_crtcs);
10986
10987 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
10988 sizeof(dpll_hw_state)),
10989 "pll hw state mismatch\n");
10990 }
10991 }
10992
10993 void
10994 intel_modeset_check_state(struct drm_device *dev)
10995 {
10996 check_connector_state(dev);
10997 check_encoder_state(dev);
10998 check_crtc_state(dev);
10999 check_shared_dpll_state(dev);
11000 }
11001
11002 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
11003 int dotclock)
11004 {
11005 /*
11006 * FDI already provided one idea for the dotclock.
11007 * Yell if the encoder disagrees.
11008 */
11009 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
11010 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11011 pipe_config->adjusted_mode.crtc_clock, dotclock);
11012 }
11013
11014 static void update_scanline_offset(struct intel_crtc *crtc)
11015 {
11016 struct drm_device *dev = crtc->base.dev;
11017
11018 /*
11019 * The scanline counter increments at the leading edge of hsync.
11020 *
11021 * On most platforms it starts counting from vtotal-1 on the
11022 * first active line. That means the scanline counter value is
11023 * always one less than what we would expect. Ie. just after
11024 * start of vblank, which also occurs at start of hsync (on the
11025 * last active line), the scanline counter will read vblank_start-1.
11026 *
11027 * On gen2 the scanline counter starts counting from 1 instead
11028 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11029 * to keep the value positive), instead of adding one.
11030 *
11031 * On HSW+ the behaviour of the scanline counter depends on the output
11032 * type. For DP ports it behaves like most other platforms, but on HDMI
11033 * there's an extra 1 line difference. So we need to add two instead of
11034 * one to the value.
11035 */
11036 if (IS_GEN2(dev)) {
11037 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
11038 int vtotal;
11039
11040 vtotal = mode->crtc_vtotal;
11041 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
11042 vtotal /= 2;
11043
11044 crtc->scanline_offset = vtotal - 1;
11045 } else if (HAS_DDI(dev) &&
11046 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {
11047 crtc->scanline_offset = 2;
11048 } else
11049 crtc->scanline_offset = 1;
11050 }
11051
11052 static int __intel_set_mode(struct drm_crtc *crtc,
11053 struct drm_display_mode *mode,
11054 int x, int y, struct drm_framebuffer *fb)
11055 {
11056 struct drm_device *dev = crtc->dev;
11057 struct drm_i915_private *dev_priv = dev->dev_private;
11058 struct drm_display_mode *saved_mode;
11059 struct intel_crtc_config *pipe_config = NULL;
11060 struct intel_crtc *intel_crtc;
11061 unsigned disable_pipes, prepare_pipes, modeset_pipes;
11062 int ret = 0;
11063
11064 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
11065 if (!saved_mode)
11066 return -ENOMEM;
11067
11068 intel_modeset_affected_pipes(crtc, &modeset_pipes,
11069 &prepare_pipes, &disable_pipes);
11070
11071 *saved_mode = crtc->mode;
11072
11073 /* Hack: Because we don't (yet) support global modeset on multiple
11074 * crtcs, we don't keep track of the new mode for more than one crtc.
11075 * Hence simply check whether any bit is set in modeset_pipes in all the
11076 * pieces of code that are not yet converted to deal with mutliple crtcs
11077 * changing their mode at the same time. */
11078 if (modeset_pipes) {
11079 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
11080 if (IS_ERR(pipe_config)) {
11081 ret = PTR_ERR(pipe_config);
11082 pipe_config = NULL;
11083
11084 goto out;
11085 }
11086 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11087 "[modeset]");
11088 to_intel_crtc(crtc)->new_config = pipe_config;
11089 }
11090
11091 /*
11092 * See if the config requires any additional preparation, e.g.
11093 * to adjust global state with pipes off. We need to do this
11094 * here so we can get the modeset_pipe updated config for the new
11095 * mode set on this crtc. For other crtcs we need to use the
11096 * adjusted_mode bits in the crtc directly.
11097 */
11098 if (IS_VALLEYVIEW(dev)) {
11099 valleyview_modeset_global_pipes(dev, &prepare_pipes);
11100
11101 /* may have added more to prepare_pipes than we should */
11102 prepare_pipes &= ~disable_pipes;
11103 }
11104
11105 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
11106 intel_crtc_disable(&intel_crtc->base);
11107
11108 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11109 if (intel_crtc->base.enabled)
11110 dev_priv->display.crtc_disable(&intel_crtc->base);
11111 }
11112
11113 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11114 * to set it here already despite that we pass it down the callchain.
11115 */
11116 if (modeset_pipes) {
11117 crtc->mode = *mode;
11118 /* mode_set/enable/disable functions rely on a correct pipe
11119 * config. */
11120 to_intel_crtc(crtc)->config = *pipe_config;
11121 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
11122
11123 /*
11124 * Calculate and store various constants which
11125 * are later needed by vblank and swap-completion
11126 * timestamping. They are derived from true hwmode.
11127 */
11128 drm_calc_timestamping_constants(crtc,
11129 &pipe_config->adjusted_mode);
11130 }
11131
11132 /* Only after disabling all output pipelines that will be changed can we
11133 * update the the output configuration. */
11134 intel_modeset_update_state(dev, prepare_pipes);
11135
11136 if (dev_priv->display.modeset_global_resources)
11137 dev_priv->display.modeset_global_resources(dev);
11138
11139 /* Set up the DPLL and any encoders state that needs to adjust or depend
11140 * on the DPLL.
11141 */
11142 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11143 struct drm_framebuffer *old_fb = crtc->primary->fb;
11144 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
11145 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11146
11147 mutex_lock(&dev->struct_mutex);
11148 ret = intel_pin_and_fence_fb_obj(dev,
11149 obj,
11150 NULL);
11151 if (ret != 0) {
11152 DRM_ERROR("pin & fence failed\n");
11153 mutex_unlock(&dev->struct_mutex);
11154 goto done;
11155 }
11156 if (old_fb)
11157 intel_unpin_fb_obj(old_obj);
11158 i915_gem_track_fb(old_obj, obj,
11159 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11160 mutex_unlock(&dev->struct_mutex);
11161
11162 crtc->primary->fb = fb;
11163 crtc->x = x;
11164 crtc->y = y;
11165
11166 ret = dev_priv->display.crtc_mode_set(&intel_crtc->base,
11167 x, y, fb);
11168 if (ret)
11169 goto done;
11170 }
11171
11172 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11173 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11174 update_scanline_offset(intel_crtc);
11175
11176 dev_priv->display.crtc_enable(&intel_crtc->base);
11177 }
11178
11179 /* FIXME: add subpixel order */
11180 done:
11181 if (ret && crtc->enabled)
11182 crtc->mode = *saved_mode;
11183
11184 out:
11185 kfree(pipe_config);
11186 kfree(saved_mode);
11187 return ret;
11188 }
11189
11190 static int intel_set_mode(struct drm_crtc *crtc,
11191 struct drm_display_mode *mode,
11192 int x, int y, struct drm_framebuffer *fb)
11193 {
11194 int ret;
11195
11196 ret = __intel_set_mode(crtc, mode, x, y, fb);
11197
11198 if (ret == 0)
11199 intel_modeset_check_state(crtc->dev);
11200
11201 return ret;
11202 }
11203
11204 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11205 {
11206 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
11207 }
11208
11209 #undef for_each_intel_crtc_masked
11210
11211 static void intel_set_config_free(struct intel_set_config *config)
11212 {
11213 if (!config)
11214 return;
11215
11216 kfree(config->save_connector_encoders);
11217 kfree(config->save_encoder_crtcs);
11218 kfree(config->save_crtc_enabled);
11219 kfree(config);
11220 }
11221
11222 static int intel_set_config_save_state(struct drm_device *dev,
11223 struct intel_set_config *config)
11224 {
11225 struct drm_crtc *crtc;
11226 struct drm_encoder *encoder;
11227 struct drm_connector *connector;
11228 int count;
11229
11230 config->save_crtc_enabled =
11231 kcalloc(dev->mode_config.num_crtc,
11232 sizeof(bool), GFP_KERNEL);
11233 if (!config->save_crtc_enabled)
11234 return -ENOMEM;
11235
11236 config->save_encoder_crtcs =
11237 kcalloc(dev->mode_config.num_encoder,
11238 sizeof(struct drm_crtc *), GFP_KERNEL);
11239 if (!config->save_encoder_crtcs)
11240 return -ENOMEM;
11241
11242 config->save_connector_encoders =
11243 kcalloc(dev->mode_config.num_connector,
11244 sizeof(struct drm_encoder *), GFP_KERNEL);
11245 if (!config->save_connector_encoders)
11246 return -ENOMEM;
11247
11248 /* Copy data. Note that driver private data is not affected.
11249 * Should anything bad happen only the expected state is
11250 * restored, not the drivers personal bookkeeping.
11251 */
11252 count = 0;
11253 for_each_crtc(dev, crtc) {
11254 config->save_crtc_enabled[count++] = crtc->enabled;
11255 }
11256
11257 count = 0;
11258 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11259 config->save_encoder_crtcs[count++] = encoder->crtc;
11260 }
11261
11262 count = 0;
11263 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11264 config->save_connector_encoders[count++] = connector->encoder;
11265 }
11266
11267 return 0;
11268 }
11269
11270 static void intel_set_config_restore_state(struct drm_device *dev,
11271 struct intel_set_config *config)
11272 {
11273 struct intel_crtc *crtc;
11274 struct intel_encoder *encoder;
11275 struct intel_connector *connector;
11276 int count;
11277
11278 count = 0;
11279 for_each_intel_crtc(dev, crtc) {
11280 crtc->new_enabled = config->save_crtc_enabled[count++];
11281
11282 if (crtc->new_enabled)
11283 crtc->new_config = &crtc->config;
11284 else
11285 crtc->new_config = NULL;
11286 }
11287
11288 count = 0;
11289 for_each_intel_encoder(dev, encoder) {
11290 encoder->new_crtc =
11291 to_intel_crtc(config->save_encoder_crtcs[count++]);
11292 }
11293
11294 count = 0;
11295 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11296 connector->new_encoder =
11297 to_intel_encoder(config->save_connector_encoders[count++]);
11298 }
11299 }
11300
11301 static bool
11302 is_crtc_connector_off(struct drm_mode_set *set)
11303 {
11304 int i;
11305
11306 if (set->num_connectors == 0)
11307 return false;
11308
11309 if (WARN_ON(set->connectors == NULL))
11310 return false;
11311
11312 for (i = 0; i < set->num_connectors; i++)
11313 if (set->connectors[i]->encoder &&
11314 set->connectors[i]->encoder->crtc == set->crtc &&
11315 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11316 return true;
11317
11318 return false;
11319 }
11320
11321 static void
11322 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11323 struct intel_set_config *config)
11324 {
11325
11326 /* We should be able to check here if the fb has the same properties
11327 * and then just flip_or_move it */
11328 if (is_crtc_connector_off(set)) {
11329 config->mode_changed = true;
11330 } else if (set->crtc->primary->fb != set->fb) {
11331 /*
11332 * If we have no fb, we can only flip as long as the crtc is
11333 * active, otherwise we need a full mode set. The crtc may
11334 * be active if we've only disabled the primary plane, or
11335 * in fastboot situations.
11336 */
11337 if (set->crtc->primary->fb == NULL) {
11338 struct intel_crtc *intel_crtc =
11339 to_intel_crtc(set->crtc);
11340
11341 if (intel_crtc->active) {
11342 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11343 config->fb_changed = true;
11344 } else {
11345 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11346 config->mode_changed = true;
11347 }
11348 } else if (set->fb == NULL) {
11349 config->mode_changed = true;
11350 } else if (set->fb->pixel_format !=
11351 set->crtc->primary->fb->pixel_format) {
11352 config->mode_changed = true;
11353 } else {
11354 config->fb_changed = true;
11355 }
11356 }
11357
11358 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11359 config->fb_changed = true;
11360
11361 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11362 DRM_DEBUG_KMS("modes are different, full mode set\n");
11363 drm_mode_debug_printmodeline(&set->crtc->mode);
11364 drm_mode_debug_printmodeline(set->mode);
11365 config->mode_changed = true;
11366 }
11367
11368 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11369 set->crtc->base.id, config->mode_changed, config->fb_changed);
11370 }
11371
11372 static int
11373 intel_modeset_stage_output_state(struct drm_device *dev,
11374 struct drm_mode_set *set,
11375 struct intel_set_config *config)
11376 {
11377 struct intel_connector *connector;
11378 struct intel_encoder *encoder;
11379 struct intel_crtc *crtc;
11380 int ro;
11381
11382 /* The upper layers ensure that we either disable a crtc or have a list
11383 * of connectors. For paranoia, double-check this. */
11384 WARN_ON(!set->fb && (set->num_connectors != 0));
11385 WARN_ON(set->fb && (set->num_connectors == 0));
11386
11387 list_for_each_entry(connector, &dev->mode_config.connector_list,
11388 base.head) {
11389 /* Otherwise traverse passed in connector list and get encoders
11390 * for them. */
11391 for (ro = 0; ro < set->num_connectors; ro++) {
11392 if (set->connectors[ro] == &connector->base) {
11393 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11394 break;
11395 }
11396 }
11397
11398 /* If we disable the crtc, disable all its connectors. Also, if
11399 * the connector is on the changing crtc but not on the new
11400 * connector list, disable it. */
11401 if ((!set->fb || ro == set->num_connectors) &&
11402 connector->base.encoder &&
11403 connector->base.encoder->crtc == set->crtc) {
11404 connector->new_encoder = NULL;
11405
11406 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11407 connector->base.base.id,
11408 connector->base.name);
11409 }
11410
11411
11412 if (&connector->new_encoder->base != connector->base.encoder) {
11413 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11414 config->mode_changed = true;
11415 }
11416 }
11417 /* connector->new_encoder is now updated for all connectors. */
11418
11419 /* Update crtc of enabled connectors. */
11420 list_for_each_entry(connector, &dev->mode_config.connector_list,
11421 base.head) {
11422 struct drm_crtc *new_crtc;
11423
11424 if (!connector->new_encoder)
11425 continue;
11426
11427 new_crtc = connector->new_encoder->base.crtc;
11428
11429 for (ro = 0; ro < set->num_connectors; ro++) {
11430 if (set->connectors[ro] == &connector->base)
11431 new_crtc = set->crtc;
11432 }
11433
11434 /* Make sure the new CRTC will work with the encoder */
11435 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11436 new_crtc)) {
11437 return -EINVAL;
11438 }
11439 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11440
11441 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11442 connector->base.base.id,
11443 connector->base.name,
11444 new_crtc->base.id);
11445 }
11446
11447 /* Check for any encoders that needs to be disabled. */
11448 for_each_intel_encoder(dev, encoder) {
11449 int num_connectors = 0;
11450 list_for_each_entry(connector,
11451 &dev->mode_config.connector_list,
11452 base.head) {
11453 if (connector->new_encoder == encoder) {
11454 WARN_ON(!connector->new_encoder->new_crtc);
11455 num_connectors++;
11456 }
11457 }
11458
11459 if (num_connectors == 0)
11460 encoder->new_crtc = NULL;
11461 else if (num_connectors > 1)
11462 return -EINVAL;
11463
11464 /* Only now check for crtc changes so we don't miss encoders
11465 * that will be disabled. */
11466 if (&encoder->new_crtc->base != encoder->base.crtc) {
11467 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11468 config->mode_changed = true;
11469 }
11470 }
11471 /* Now we've also updated encoder->new_crtc for all encoders. */
11472 list_for_each_entry(connector, &dev->mode_config.connector_list,
11473 base.head) {
11474 if (connector->new_encoder)
11475 if (connector->new_encoder != connector->encoder)
11476 connector->encoder = connector->new_encoder;
11477 }
11478 for_each_intel_crtc(dev, crtc) {
11479 crtc->new_enabled = false;
11480
11481 for_each_intel_encoder(dev, encoder) {
11482 if (encoder->new_crtc == crtc) {
11483 crtc->new_enabled = true;
11484 break;
11485 }
11486 }
11487
11488 if (crtc->new_enabled != crtc->base.enabled) {
11489 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11490 crtc->new_enabled ? "en" : "dis");
11491 config->mode_changed = true;
11492 }
11493
11494 if (crtc->new_enabled)
11495 crtc->new_config = &crtc->config;
11496 else
11497 crtc->new_config = NULL;
11498 }
11499
11500 return 0;
11501 }
11502
11503 static void disable_crtc_nofb(struct intel_crtc *crtc)
11504 {
11505 struct drm_device *dev = crtc->base.dev;
11506 struct intel_encoder *encoder;
11507 struct intel_connector *connector;
11508
11509 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11510 pipe_name(crtc->pipe));
11511
11512 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11513 if (connector->new_encoder &&
11514 connector->new_encoder->new_crtc == crtc)
11515 connector->new_encoder = NULL;
11516 }
11517
11518 for_each_intel_encoder(dev, encoder) {
11519 if (encoder->new_crtc == crtc)
11520 encoder->new_crtc = NULL;
11521 }
11522
11523 crtc->new_enabled = false;
11524 crtc->new_config = NULL;
11525 }
11526
11527 static int intel_crtc_set_config(struct drm_mode_set *set)
11528 {
11529 struct drm_device *dev;
11530 struct drm_mode_set save_set;
11531 struct intel_set_config *config;
11532 int ret;
11533
11534 BUG_ON(!set);
11535 BUG_ON(!set->crtc);
11536 BUG_ON(!set->crtc->helper_private);
11537
11538 /* Enforce sane interface api - has been abused by the fb helper. */
11539 BUG_ON(!set->mode && set->fb);
11540 BUG_ON(set->fb && set->num_connectors == 0);
11541
11542 if (set->fb) {
11543 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11544 set->crtc->base.id, set->fb->base.id,
11545 (int)set->num_connectors, set->x, set->y);
11546 } else {
11547 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11548 }
11549
11550 dev = set->crtc->dev;
11551
11552 ret = -ENOMEM;
11553 config = kzalloc(sizeof(*config), GFP_KERNEL);
11554 if (!config)
11555 goto out_config;
11556
11557 ret = intel_set_config_save_state(dev, config);
11558 if (ret)
11559 goto out_config;
11560
11561 save_set.crtc = set->crtc;
11562 save_set.mode = &set->crtc->mode;
11563 save_set.x = set->crtc->x;
11564 save_set.y = set->crtc->y;
11565 save_set.fb = set->crtc->primary->fb;
11566
11567 /* Compute whether we need a full modeset, only an fb base update or no
11568 * change at all. In the future we might also check whether only the
11569 * mode changed, e.g. for LVDS where we only change the panel fitter in
11570 * such cases. */
11571 intel_set_config_compute_mode_changes(set, config);
11572
11573 ret = intel_modeset_stage_output_state(dev, set, config);
11574 if (ret)
11575 goto fail;
11576
11577 if (config->mode_changed) {
11578 ret = intel_set_mode(set->crtc, set->mode,
11579 set->x, set->y, set->fb);
11580 } else if (config->fb_changed) {
11581 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11582
11583 intel_crtc_wait_for_pending_flips(set->crtc);
11584
11585 ret = intel_pipe_set_base(set->crtc,
11586 set->x, set->y, set->fb);
11587
11588 /*
11589 * We need to make sure the primary plane is re-enabled if it
11590 * has previously been turned off.
11591 */
11592 if (!intel_crtc->primary_enabled && ret == 0) {
11593 WARN_ON(!intel_crtc->active);
11594 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11595 }
11596
11597 /*
11598 * In the fastboot case this may be our only check of the
11599 * state after boot. It would be better to only do it on
11600 * the first update, but we don't have a nice way of doing that
11601 * (and really, set_config isn't used much for high freq page
11602 * flipping, so increasing its cost here shouldn't be a big
11603 * deal).
11604 */
11605 if (i915.fastboot && ret == 0)
11606 intel_modeset_check_state(set->crtc->dev);
11607 }
11608
11609 if (ret) {
11610 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11611 set->crtc->base.id, ret);
11612 fail:
11613 intel_set_config_restore_state(dev, config);
11614
11615 /*
11616 * HACK: if the pipe was on, but we didn't have a framebuffer,
11617 * force the pipe off to avoid oopsing in the modeset code
11618 * due to fb==NULL. This should only happen during boot since
11619 * we don't yet reconstruct the FB from the hardware state.
11620 */
11621 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11622 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11623
11624 /* Try to restore the config */
11625 if (config->mode_changed &&
11626 intel_set_mode(save_set.crtc, save_set.mode,
11627 save_set.x, save_set.y, save_set.fb))
11628 DRM_ERROR("failed to restore config after modeset failure\n");
11629 }
11630
11631 out_config:
11632 intel_set_config_free(config);
11633 return ret;
11634 }
11635
11636 static const struct drm_crtc_funcs intel_crtc_funcs = {
11637 .gamma_set = intel_crtc_gamma_set,
11638 .set_config = intel_crtc_set_config,
11639 .destroy = intel_crtc_destroy,
11640 .page_flip = intel_crtc_page_flip,
11641 };
11642
11643 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11644 struct intel_shared_dpll *pll,
11645 struct intel_dpll_hw_state *hw_state)
11646 {
11647 uint32_t val;
11648
11649 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_PLLS))
11650 return false;
11651
11652 val = I915_READ(PCH_DPLL(pll->id));
11653 hw_state->dpll = val;
11654 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11655 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11656
11657 return val & DPLL_VCO_ENABLE;
11658 }
11659
11660 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11661 struct intel_shared_dpll *pll)
11662 {
11663 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
11664 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
11665 }
11666
11667 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11668 struct intel_shared_dpll *pll)
11669 {
11670 /* PCH refclock must be enabled first */
11671 ibx_assert_pch_refclk_enabled(dev_priv);
11672
11673 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11674
11675 /* Wait for the clocks to stabilize. */
11676 POSTING_READ(PCH_DPLL(pll->id));
11677 udelay(150);
11678
11679 /* The pixel multiplier can only be updated once the
11680 * DPLL is enabled and the clocks are stable.
11681 *
11682 * So write it again.
11683 */
11684 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11685 POSTING_READ(PCH_DPLL(pll->id));
11686 udelay(200);
11687 }
11688
11689 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11690 struct intel_shared_dpll *pll)
11691 {
11692 struct drm_device *dev = dev_priv->dev;
11693 struct intel_crtc *crtc;
11694
11695 /* Make sure no transcoder isn't still depending on us. */
11696 for_each_intel_crtc(dev, crtc) {
11697 if (intel_crtc_to_shared_dpll(crtc) == pll)
11698 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11699 }
11700
11701 I915_WRITE(PCH_DPLL(pll->id), 0);
11702 POSTING_READ(PCH_DPLL(pll->id));
11703 udelay(200);
11704 }
11705
11706 static char *ibx_pch_dpll_names[] = {
11707 "PCH DPLL A",
11708 "PCH DPLL B",
11709 };
11710
11711 static void ibx_pch_dpll_init(struct drm_device *dev)
11712 {
11713 struct drm_i915_private *dev_priv = dev->dev_private;
11714 int i;
11715
11716 dev_priv->num_shared_dpll = 2;
11717
11718 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11719 dev_priv->shared_dplls[i].id = i;
11720 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11721 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11722 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11723 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11724 dev_priv->shared_dplls[i].get_hw_state =
11725 ibx_pch_dpll_get_hw_state;
11726 }
11727 }
11728
11729 static void intel_shared_dpll_init(struct drm_device *dev)
11730 {
11731 struct drm_i915_private *dev_priv = dev->dev_private;
11732
11733 if (HAS_DDI(dev))
11734 intel_ddi_pll_init(dev);
11735 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11736 ibx_pch_dpll_init(dev);
11737 else
11738 dev_priv->num_shared_dpll = 0;
11739
11740 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11741 }
11742
11743 static int
11744 intel_primary_plane_disable(struct drm_plane *plane)
11745 {
11746 struct drm_device *dev = plane->dev;
11747 struct intel_crtc *intel_crtc;
11748
11749 if (!plane->fb)
11750 return 0;
11751
11752 BUG_ON(!plane->crtc);
11753
11754 intel_crtc = to_intel_crtc(plane->crtc);
11755
11756 /*
11757 * Even though we checked plane->fb above, it's still possible that
11758 * the primary plane has been implicitly disabled because the crtc
11759 * coordinates given weren't visible, or because we detected
11760 * that it was 100% covered by a sprite plane. Or, the CRTC may be
11761 * off and we've set a fb, but haven't actually turned on the CRTC yet.
11762 * In either case, we need to unpin the FB and let the fb pointer get
11763 * updated, but otherwise we don't need to touch the hardware.
11764 */
11765 if (!intel_crtc->primary_enabled)
11766 goto disable_unpin;
11767
11768 intel_crtc_wait_for_pending_flips(plane->crtc);
11769 intel_disable_primary_hw_plane(plane, plane->crtc);
11770
11771 disable_unpin:
11772 mutex_lock(&dev->struct_mutex);
11773 i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
11774 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11775 intel_unpin_fb_obj(intel_fb_obj(plane->fb));
11776 mutex_unlock(&dev->struct_mutex);
11777 plane->fb = NULL;
11778
11779 return 0;
11780 }
11781
11782 static int
11783 intel_check_primary_plane(struct drm_plane *plane,
11784 struct intel_plane_state *state)
11785 {
11786 struct drm_crtc *crtc = state->crtc;
11787 struct drm_framebuffer *fb = state->fb;
11788 struct drm_rect *dest = &state->dst;
11789 struct drm_rect *src = &state->src;
11790 const struct drm_rect *clip = &state->clip;
11791
11792 return drm_plane_helper_check_update(plane, crtc, fb,
11793 src, dest, clip,
11794 DRM_PLANE_HELPER_NO_SCALING,
11795 DRM_PLANE_HELPER_NO_SCALING,
11796 false, true, &state->visible);
11797 }
11798
11799 static int
11800 intel_commit_primary_plane(struct drm_plane *plane,
11801 struct intel_plane_state *state)
11802 {
11803 struct drm_crtc *crtc = state->crtc;
11804 struct drm_framebuffer *fb = state->fb;
11805 struct drm_device *dev = crtc->dev;
11806 struct drm_i915_private *dev_priv = dev->dev_private;
11807 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11808 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11809 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11810 struct intel_plane *intel_plane = to_intel_plane(plane);
11811 struct drm_rect *src = &state->src;
11812 int ret;
11813
11814 intel_crtc_wait_for_pending_flips(crtc);
11815
11816 /*
11817 * If clipping results in a non-visible primary plane, we'll disable
11818 * the primary plane. Note that this is a bit different than what
11819 * happens if userspace explicitly disables the plane by passing fb=0
11820 * because plane->fb still gets set and pinned.
11821 */
11822 if (!state->visible) {
11823 mutex_lock(&dev->struct_mutex);
11824
11825 /*
11826 * Try to pin the new fb first so that we can bail out if we
11827 * fail.
11828 */
11829 if (plane->fb != fb) {
11830 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11831 if (ret) {
11832 mutex_unlock(&dev->struct_mutex);
11833 return ret;
11834 }
11835 }
11836
11837 i915_gem_track_fb(old_obj, obj,
11838 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11839
11840 if (intel_crtc->primary_enabled)
11841 intel_disable_primary_hw_plane(plane, crtc);
11842
11843
11844 if (plane->fb != fb)
11845 if (plane->fb)
11846 intel_unpin_fb_obj(old_obj);
11847
11848 mutex_unlock(&dev->struct_mutex);
11849
11850 } else {
11851 if (intel_crtc && intel_crtc->active &&
11852 intel_crtc->primary_enabled) {
11853 /*
11854 * FBC does not work on some platforms for rotated
11855 * planes, so disable it when rotation is not 0 and
11856 * update it when rotation is set back to 0.
11857 *
11858 * FIXME: This is redundant with the fbc update done in
11859 * the primary plane enable function except that that
11860 * one is done too late. We eventually need to unify
11861 * this.
11862 */
11863 if (INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11864 dev_priv->fbc.plane == intel_crtc->plane &&
11865 intel_plane->rotation != BIT(DRM_ROTATE_0)) {
11866 intel_disable_fbc(dev);
11867 }
11868 }
11869 ret = intel_pipe_set_base(crtc, src->x1, src->y1, fb);
11870 if (ret)
11871 return ret;
11872
11873 if (!intel_crtc->primary_enabled)
11874 intel_enable_primary_hw_plane(plane, crtc);
11875 }
11876
11877 intel_plane->crtc_x = state->orig_dst.x1;
11878 intel_plane->crtc_y = state->orig_dst.y1;
11879 intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
11880 intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
11881 intel_plane->src_x = state->orig_src.x1;
11882 intel_plane->src_y = state->orig_src.y1;
11883 intel_plane->src_w = drm_rect_width(&state->orig_src);
11884 intel_plane->src_h = drm_rect_height(&state->orig_src);
11885 intel_plane->obj = obj;
11886
11887 return 0;
11888 }
11889
11890 static int
11891 intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11892 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11893 unsigned int crtc_w, unsigned int crtc_h,
11894 uint32_t src_x, uint32_t src_y,
11895 uint32_t src_w, uint32_t src_h)
11896 {
11897 struct intel_plane_state state;
11898 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11899 int ret;
11900
11901 state.crtc = crtc;
11902 state.fb = fb;
11903
11904 /* sample coordinates in 16.16 fixed point */
11905 state.src.x1 = src_x;
11906 state.src.x2 = src_x + src_w;
11907 state.src.y1 = src_y;
11908 state.src.y2 = src_y + src_h;
11909
11910 /* integer pixels */
11911 state.dst.x1 = crtc_x;
11912 state.dst.x2 = crtc_x + crtc_w;
11913 state.dst.y1 = crtc_y;
11914 state.dst.y2 = crtc_y + crtc_h;
11915
11916 state.clip.x1 = 0;
11917 state.clip.y1 = 0;
11918 state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
11919 state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
11920
11921 state.orig_src = state.src;
11922 state.orig_dst = state.dst;
11923
11924 ret = intel_check_primary_plane(plane, &state);
11925 if (ret)
11926 return ret;
11927
11928 intel_commit_primary_plane(plane, &state);
11929
11930 return 0;
11931 }
11932
11933 /* Common destruction function for both primary and cursor planes */
11934 static void intel_plane_destroy(struct drm_plane *plane)
11935 {
11936 struct intel_plane *intel_plane = to_intel_plane(plane);
11937 drm_plane_cleanup(plane);
11938 kfree(intel_plane);
11939 }
11940
11941 static const struct drm_plane_funcs intel_primary_plane_funcs = {
11942 .update_plane = intel_primary_plane_setplane,
11943 .disable_plane = intel_primary_plane_disable,
11944 .destroy = intel_plane_destroy,
11945 .set_property = intel_plane_set_property
11946 };
11947
11948 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11949 int pipe)
11950 {
11951 struct intel_plane *primary;
11952 const uint32_t *intel_primary_formats;
11953 int num_formats;
11954
11955 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11956 if (primary == NULL)
11957 return NULL;
11958
11959 primary->can_scale = false;
11960 primary->max_downscale = 1;
11961 primary->pipe = pipe;
11962 primary->plane = pipe;
11963 primary->rotation = BIT(DRM_ROTATE_0);
11964 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11965 primary->plane = !pipe;
11966
11967 if (INTEL_INFO(dev)->gen <= 3) {
11968 intel_primary_formats = intel_primary_formats_gen2;
11969 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
11970 } else {
11971 intel_primary_formats = intel_primary_formats_gen4;
11972 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
11973 }
11974
11975 drm_universal_plane_init(dev, &primary->base, 0,
11976 &intel_primary_plane_funcs,
11977 intel_primary_formats, num_formats,
11978 DRM_PLANE_TYPE_PRIMARY);
11979
11980 if (INTEL_INFO(dev)->gen >= 4) {
11981 if (!dev->mode_config.rotation_property)
11982 dev->mode_config.rotation_property =
11983 drm_mode_create_rotation_property(dev,
11984 BIT(DRM_ROTATE_0) |
11985 BIT(DRM_ROTATE_180));
11986 if (dev->mode_config.rotation_property)
11987 drm_object_attach_property(&primary->base.base,
11988 dev->mode_config.rotation_property,
11989 primary->rotation);
11990 }
11991
11992 return &primary->base;
11993 }
11994
11995 static int
11996 intel_cursor_plane_disable(struct drm_plane *plane)
11997 {
11998 if (!plane->fb)
11999 return 0;
12000
12001 BUG_ON(!plane->crtc);
12002
12003 return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
12004 }
12005
12006 static int
12007 intel_check_cursor_plane(struct drm_plane *plane,
12008 struct intel_plane_state *state)
12009 {
12010 struct drm_crtc *crtc = state->crtc;
12011 struct drm_framebuffer *fb = state->fb;
12012 struct drm_rect *dest = &state->dst;
12013 struct drm_rect *src = &state->src;
12014 const struct drm_rect *clip = &state->clip;
12015
12016 return drm_plane_helper_check_update(plane, crtc, fb,
12017 src, dest, clip,
12018 DRM_PLANE_HELPER_NO_SCALING,
12019 DRM_PLANE_HELPER_NO_SCALING,
12020 true, true, &state->visible);
12021 }
12022
12023 static int
12024 intel_commit_cursor_plane(struct drm_plane *plane,
12025 struct intel_plane_state *state)
12026 {
12027 struct drm_crtc *crtc = state->crtc;
12028 struct drm_framebuffer *fb = state->fb;
12029 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12030 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12031 struct drm_i915_gem_object *obj = intel_fb->obj;
12032 int crtc_w, crtc_h;
12033
12034 crtc->cursor_x = state->orig_dst.x1;
12035 crtc->cursor_y = state->orig_dst.y1;
12036 if (fb != crtc->cursor->fb) {
12037 crtc_w = drm_rect_width(&state->orig_dst);
12038 crtc_h = drm_rect_height(&state->orig_dst);
12039 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
12040 } else {
12041 intel_crtc_update_cursor(crtc, state->visible);
12042
12043 intel_frontbuffer_flip(crtc->dev,
12044 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe));
12045
12046 return 0;
12047 }
12048 }
12049
12050 static int
12051 intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
12052 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
12053 unsigned int crtc_w, unsigned int crtc_h,
12054 uint32_t src_x, uint32_t src_y,
12055 uint32_t src_w, uint32_t src_h)
12056 {
12057 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12058 struct intel_plane_state state;
12059 int ret;
12060
12061 state.crtc = crtc;
12062 state.fb = fb;
12063
12064 /* sample coordinates in 16.16 fixed point */
12065 state.src.x1 = src_x;
12066 state.src.x2 = src_x + src_w;
12067 state.src.y1 = src_y;
12068 state.src.y2 = src_y + src_h;
12069
12070 /* integer pixels */
12071 state.dst.x1 = crtc_x;
12072 state.dst.x2 = crtc_x + crtc_w;
12073 state.dst.y1 = crtc_y;
12074 state.dst.y2 = crtc_y + crtc_h;
12075
12076 state.clip.x1 = 0;
12077 state.clip.y1 = 0;
12078 state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
12079 state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
12080
12081 state.orig_src = state.src;
12082 state.orig_dst = state.dst;
12083
12084 ret = intel_check_cursor_plane(plane, &state);
12085 if (ret)
12086 return ret;
12087
12088 return intel_commit_cursor_plane(plane, &state);
12089 }
12090
12091 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
12092 .update_plane = intel_cursor_plane_update,
12093 .disable_plane = intel_cursor_plane_disable,
12094 .destroy = intel_plane_destroy,
12095 };
12096
12097 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12098 int pipe)
12099 {
12100 struct intel_plane *cursor;
12101
12102 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12103 if (cursor == NULL)
12104 return NULL;
12105
12106 cursor->can_scale = false;
12107 cursor->max_downscale = 1;
12108 cursor->pipe = pipe;
12109 cursor->plane = pipe;
12110
12111 drm_universal_plane_init(dev, &cursor->base, 0,
12112 &intel_cursor_plane_funcs,
12113 intel_cursor_formats,
12114 ARRAY_SIZE(intel_cursor_formats),
12115 DRM_PLANE_TYPE_CURSOR);
12116 return &cursor->base;
12117 }
12118
12119 static void intel_crtc_init(struct drm_device *dev, int pipe)
12120 {
12121 struct drm_i915_private *dev_priv = dev->dev_private;
12122 struct intel_crtc *intel_crtc;
12123 struct drm_plane *primary = NULL;
12124 struct drm_plane *cursor = NULL;
12125 int i, ret;
12126
12127 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12128 if (intel_crtc == NULL)
12129 return;
12130
12131 primary = intel_primary_plane_create(dev, pipe);
12132 if (!primary)
12133 goto fail;
12134
12135 cursor = intel_cursor_plane_create(dev, pipe);
12136 if (!cursor)
12137 goto fail;
12138
12139 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12140 cursor, &intel_crtc_funcs);
12141 if (ret)
12142 goto fail;
12143
12144 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12145 for (i = 0; i < 256; i++) {
12146 intel_crtc->lut_r[i] = i;
12147 intel_crtc->lut_g[i] = i;
12148 intel_crtc->lut_b[i] = i;
12149 }
12150
12151 /*
12152 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12153 * is hooked to pipe B. Hence we want plane A feeding pipe B.
12154 */
12155 intel_crtc->pipe = pipe;
12156 intel_crtc->plane = pipe;
12157 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12158 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12159 intel_crtc->plane = !pipe;
12160 }
12161
12162 intel_crtc->cursor_base = ~0;
12163 intel_crtc->cursor_cntl = ~0;
12164 intel_crtc->cursor_size = ~0;
12165
12166 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12167 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12168 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12169 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12170
12171 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12172
12173 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12174 return;
12175
12176 fail:
12177 if (primary)
12178 drm_plane_cleanup(primary);
12179 if (cursor)
12180 drm_plane_cleanup(cursor);
12181 kfree(intel_crtc);
12182 }
12183
12184 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12185 {
12186 struct drm_encoder *encoder = connector->base.encoder;
12187 struct drm_device *dev = connector->base.dev;
12188
12189 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12190
12191 if (!encoder)
12192 return INVALID_PIPE;
12193
12194 return to_intel_crtc(encoder->crtc)->pipe;
12195 }
12196
12197 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12198 struct drm_file *file)
12199 {
12200 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12201 struct drm_crtc *drmmode_crtc;
12202 struct intel_crtc *crtc;
12203
12204 if (!drm_core_check_feature(dev, DRIVER_MODESET))
12205 return -ENODEV;
12206
12207 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12208
12209 if (!drmmode_crtc) {
12210 DRM_ERROR("no such CRTC id\n");
12211 return -ENOENT;
12212 }
12213
12214 crtc = to_intel_crtc(drmmode_crtc);
12215 pipe_from_crtc_id->pipe = crtc->pipe;
12216
12217 return 0;
12218 }
12219
12220 static int intel_encoder_clones(struct intel_encoder *encoder)
12221 {
12222 struct drm_device *dev = encoder->base.dev;
12223 struct intel_encoder *source_encoder;
12224 int index_mask = 0;
12225 int entry = 0;
12226
12227 for_each_intel_encoder(dev, source_encoder) {
12228 if (encoders_cloneable(encoder, source_encoder))
12229 index_mask |= (1 << entry);
12230
12231 entry++;
12232 }
12233
12234 return index_mask;
12235 }
12236
12237 static bool has_edp_a(struct drm_device *dev)
12238 {
12239 struct drm_i915_private *dev_priv = dev->dev_private;
12240
12241 if (!IS_MOBILE(dev))
12242 return false;
12243
12244 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12245 return false;
12246
12247 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12248 return false;
12249
12250 return true;
12251 }
12252
12253 const char *intel_output_name(int output)
12254 {
12255 static const char *names[] = {
12256 [INTEL_OUTPUT_UNUSED] = "Unused",
12257 [INTEL_OUTPUT_ANALOG] = "Analog",
12258 [INTEL_OUTPUT_DVO] = "DVO",
12259 [INTEL_OUTPUT_SDVO] = "SDVO",
12260 [INTEL_OUTPUT_LVDS] = "LVDS",
12261 [INTEL_OUTPUT_TVOUT] = "TV",
12262 [INTEL_OUTPUT_HDMI] = "HDMI",
12263 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
12264 [INTEL_OUTPUT_EDP] = "eDP",
12265 [INTEL_OUTPUT_DSI] = "DSI",
12266 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
12267 };
12268
12269 if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
12270 return "Invalid";
12271
12272 return names[output];
12273 }
12274
12275 static bool intel_crt_present(struct drm_device *dev)
12276 {
12277 struct drm_i915_private *dev_priv = dev->dev_private;
12278
12279 if (IS_ULT(dev))
12280 return false;
12281
12282 if (IS_CHERRYVIEW(dev))
12283 return false;
12284
12285 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12286 return false;
12287
12288 return true;
12289 }
12290
12291 static void intel_setup_outputs(struct drm_device *dev)
12292 {
12293 struct drm_i915_private *dev_priv = dev->dev_private;
12294 struct intel_encoder *encoder;
12295 bool dpd_is_edp = false;
12296
12297 intel_lvds_init(dev);
12298
12299 if (intel_crt_present(dev))
12300 intel_crt_init(dev);
12301
12302 if (HAS_DDI(dev)) {
12303 int found;
12304
12305 /* Haswell uses DDI functions to detect digital outputs */
12306 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12307 /* DDI A only supports eDP */
12308 if (found)
12309 intel_ddi_init(dev, PORT_A);
12310
12311 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12312 * register */
12313 found = I915_READ(SFUSE_STRAP);
12314
12315 if (found & SFUSE_STRAP_DDIB_DETECTED)
12316 intel_ddi_init(dev, PORT_B);
12317 if (found & SFUSE_STRAP_DDIC_DETECTED)
12318 intel_ddi_init(dev, PORT_C);
12319 if (found & SFUSE_STRAP_DDID_DETECTED)
12320 intel_ddi_init(dev, PORT_D);
12321 } else if (HAS_PCH_SPLIT(dev)) {
12322 int found;
12323 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12324
12325 if (has_edp_a(dev))
12326 intel_dp_init(dev, DP_A, PORT_A);
12327
12328 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12329 /* PCH SDVOB multiplex with HDMIB */
12330 found = intel_sdvo_init(dev, PCH_SDVOB, true);
12331 if (!found)
12332 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12333 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12334 intel_dp_init(dev, PCH_DP_B, PORT_B);
12335 }
12336
12337 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12338 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12339
12340 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12341 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12342
12343 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12344 intel_dp_init(dev, PCH_DP_C, PORT_C);
12345
12346 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12347 intel_dp_init(dev, PCH_DP_D, PORT_D);
12348 } else if (IS_VALLEYVIEW(dev)) {
12349 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
12350 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12351 PORT_B);
12352 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
12353 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12354 }
12355
12356 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
12357 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12358 PORT_C);
12359 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
12360 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12361 }
12362
12363 if (IS_CHERRYVIEW(dev)) {
12364 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) {
12365 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12366 PORT_D);
12367 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12368 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12369 }
12370 }
12371
12372 intel_dsi_init(dev);
12373 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12374 bool found = false;
12375
12376 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12377 DRM_DEBUG_KMS("probing SDVOB\n");
12378 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12379 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12380 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12381 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12382 }
12383
12384 if (!found && SUPPORTS_INTEGRATED_DP(dev))
12385 intel_dp_init(dev, DP_B, PORT_B);
12386 }
12387
12388 /* Before G4X SDVOC doesn't have its own detect register */
12389
12390 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12391 DRM_DEBUG_KMS("probing SDVOC\n");
12392 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12393 }
12394
12395 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12396
12397 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12398 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12399 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12400 }
12401 if (SUPPORTS_INTEGRATED_DP(dev))
12402 intel_dp_init(dev, DP_C, PORT_C);
12403 }
12404
12405 if (SUPPORTS_INTEGRATED_DP(dev) &&
12406 (I915_READ(DP_D) & DP_DETECTED))
12407 intel_dp_init(dev, DP_D, PORT_D);
12408 } else if (IS_GEN2(dev))
12409 intel_dvo_init(dev);
12410
12411 if (SUPPORTS_TV(dev))
12412 intel_tv_init(dev);
12413
12414 intel_edp_psr_init(dev);
12415
12416 for_each_intel_encoder(dev, encoder) {
12417 encoder->base.possible_crtcs = encoder->crtc_mask;
12418 encoder->base.possible_clones =
12419 intel_encoder_clones(encoder);
12420 }
12421
12422 intel_init_pch_refclk(dev);
12423
12424 drm_helper_move_panel_connectors_to_head(dev);
12425 }
12426
12427 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12428 {
12429 struct drm_device *dev = fb->dev;
12430 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12431
12432 drm_framebuffer_cleanup(fb);
12433 mutex_lock(&dev->struct_mutex);
12434 WARN_ON(!intel_fb->obj->framebuffer_references--);
12435 drm_gem_object_unreference(&intel_fb->obj->base);
12436 mutex_unlock(&dev->struct_mutex);
12437 kfree(intel_fb);
12438 }
12439
12440 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12441 struct drm_file *file,
12442 unsigned int *handle)
12443 {
12444 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12445 struct drm_i915_gem_object *obj = intel_fb->obj;
12446
12447 return drm_gem_handle_create(file, &obj->base, handle);
12448 }
12449
12450 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12451 .destroy = intel_user_framebuffer_destroy,
12452 .create_handle = intel_user_framebuffer_create_handle,
12453 };
12454
12455 static int intel_framebuffer_init(struct drm_device *dev,
12456 struct intel_framebuffer *intel_fb,
12457 struct drm_mode_fb_cmd2 *mode_cmd,
12458 struct drm_i915_gem_object *obj)
12459 {
12460 int aligned_height;
12461 int pitch_limit;
12462 int ret;
12463
12464 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12465
12466 if (obj->tiling_mode == I915_TILING_Y) {
12467 DRM_DEBUG("hardware does not support tiling Y\n");
12468 return -EINVAL;
12469 }
12470
12471 if (mode_cmd->pitches[0] & 63) {
12472 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12473 mode_cmd->pitches[0]);
12474 return -EINVAL;
12475 }
12476
12477 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12478 pitch_limit = 32*1024;
12479 } else if (INTEL_INFO(dev)->gen >= 4) {
12480 if (obj->tiling_mode)
12481 pitch_limit = 16*1024;
12482 else
12483 pitch_limit = 32*1024;
12484 } else if (INTEL_INFO(dev)->gen >= 3) {
12485 if (obj->tiling_mode)
12486 pitch_limit = 8*1024;
12487 else
12488 pitch_limit = 16*1024;
12489 } else
12490 /* XXX DSPC is limited to 4k tiled */
12491 pitch_limit = 8*1024;
12492
12493 if (mode_cmd->pitches[0] > pitch_limit) {
12494 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12495 obj->tiling_mode ? "tiled" : "linear",
12496 mode_cmd->pitches[0], pitch_limit);
12497 return -EINVAL;
12498 }
12499
12500 if (obj->tiling_mode != I915_TILING_NONE &&
12501 mode_cmd->pitches[0] != obj->stride) {
12502 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12503 mode_cmd->pitches[0], obj->stride);
12504 return -EINVAL;
12505 }
12506
12507 /* Reject formats not supported by any plane early. */
12508 switch (mode_cmd->pixel_format) {
12509 case DRM_FORMAT_C8:
12510 case DRM_FORMAT_RGB565:
12511 case DRM_FORMAT_XRGB8888:
12512 case DRM_FORMAT_ARGB8888:
12513 break;
12514 case DRM_FORMAT_XRGB1555:
12515 case DRM_FORMAT_ARGB1555:
12516 if (INTEL_INFO(dev)->gen > 3) {
12517 DRM_DEBUG("unsupported pixel format: %s\n",
12518 drm_get_format_name(mode_cmd->pixel_format));
12519 return -EINVAL;
12520 }
12521 break;
12522 case DRM_FORMAT_XBGR8888:
12523 case DRM_FORMAT_ABGR8888:
12524 case DRM_FORMAT_XRGB2101010:
12525 case DRM_FORMAT_ARGB2101010:
12526 case DRM_FORMAT_XBGR2101010:
12527 case DRM_FORMAT_ABGR2101010:
12528 if (INTEL_INFO(dev)->gen < 4) {
12529 DRM_DEBUG("unsupported pixel format: %s\n",
12530 drm_get_format_name(mode_cmd->pixel_format));
12531 return -EINVAL;
12532 }
12533 break;
12534 case DRM_FORMAT_YUYV:
12535 case DRM_FORMAT_UYVY:
12536 case DRM_FORMAT_YVYU:
12537 case DRM_FORMAT_VYUY:
12538 if (INTEL_INFO(dev)->gen < 5) {
12539 DRM_DEBUG("unsupported pixel format: %s\n",
12540 drm_get_format_name(mode_cmd->pixel_format));
12541 return -EINVAL;
12542 }
12543 break;
12544 default:
12545 DRM_DEBUG("unsupported pixel format: %s\n",
12546 drm_get_format_name(mode_cmd->pixel_format));
12547 return -EINVAL;
12548 }
12549
12550 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12551 if (mode_cmd->offsets[0] != 0)
12552 return -EINVAL;
12553
12554 aligned_height = intel_align_height(dev, mode_cmd->height,
12555 obj->tiling_mode);
12556 /* FIXME drm helper for size checks (especially planar formats)? */
12557 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12558 return -EINVAL;
12559
12560 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12561 intel_fb->obj = obj;
12562 intel_fb->obj->framebuffer_references++;
12563
12564 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12565 if (ret) {
12566 DRM_ERROR("framebuffer init failed %d\n", ret);
12567 return ret;
12568 }
12569
12570 return 0;
12571 }
12572
12573 static struct drm_framebuffer *
12574 intel_user_framebuffer_create(struct drm_device *dev,
12575 struct drm_file *filp,
12576 struct drm_mode_fb_cmd2 *mode_cmd)
12577 {
12578 struct drm_i915_gem_object *obj;
12579
12580 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12581 mode_cmd->handles[0]));
12582 if (&obj->base == NULL)
12583 return ERR_PTR(-ENOENT);
12584
12585 return intel_framebuffer_create(dev, mode_cmd, obj);
12586 }
12587
12588 #ifndef CONFIG_DRM_I915_FBDEV
12589 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12590 {
12591 }
12592 #endif
12593
12594 static const struct drm_mode_config_funcs intel_mode_funcs = {
12595 .fb_create = intel_user_framebuffer_create,
12596 .output_poll_changed = intel_fbdev_output_poll_changed,
12597 };
12598
12599 /* Set up chip specific display functions */
12600 static void intel_init_display(struct drm_device *dev)
12601 {
12602 struct drm_i915_private *dev_priv = dev->dev_private;
12603
12604 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12605 dev_priv->display.find_dpll = g4x_find_best_dpll;
12606 else if (IS_CHERRYVIEW(dev))
12607 dev_priv->display.find_dpll = chv_find_best_dpll;
12608 else if (IS_VALLEYVIEW(dev))
12609 dev_priv->display.find_dpll = vlv_find_best_dpll;
12610 else if (IS_PINEVIEW(dev))
12611 dev_priv->display.find_dpll = pnv_find_best_dpll;
12612 else
12613 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12614
12615 if (HAS_DDI(dev)) {
12616 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12617 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12618 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
12619 dev_priv->display.crtc_enable = haswell_crtc_enable;
12620 dev_priv->display.crtc_disable = haswell_crtc_disable;
12621 dev_priv->display.off = ironlake_crtc_off;
12622 dev_priv->display.update_primary_plane =
12623 ironlake_update_primary_plane;
12624 } else if (HAS_PCH_SPLIT(dev)) {
12625 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12626 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12627 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
12628 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12629 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12630 dev_priv->display.off = ironlake_crtc_off;
12631 dev_priv->display.update_primary_plane =
12632 ironlake_update_primary_plane;
12633 } else if (IS_VALLEYVIEW(dev)) {
12634 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12635 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12636 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12637 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12638 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12639 dev_priv->display.off = i9xx_crtc_off;
12640 dev_priv->display.update_primary_plane =
12641 i9xx_update_primary_plane;
12642 } else {
12643 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12644 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12645 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12646 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12647 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12648 dev_priv->display.off = i9xx_crtc_off;
12649 dev_priv->display.update_primary_plane =
12650 i9xx_update_primary_plane;
12651 }
12652
12653 /* Returns the core display clock speed */
12654 if (IS_VALLEYVIEW(dev))
12655 dev_priv->display.get_display_clock_speed =
12656 valleyview_get_display_clock_speed;
12657 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12658 dev_priv->display.get_display_clock_speed =
12659 i945_get_display_clock_speed;
12660 else if (IS_I915G(dev))
12661 dev_priv->display.get_display_clock_speed =
12662 i915_get_display_clock_speed;
12663 else if (IS_I945GM(dev) || IS_845G(dev))
12664 dev_priv->display.get_display_clock_speed =
12665 i9xx_misc_get_display_clock_speed;
12666 else if (IS_PINEVIEW(dev))
12667 dev_priv->display.get_display_clock_speed =
12668 pnv_get_display_clock_speed;
12669 else if (IS_I915GM(dev))
12670 dev_priv->display.get_display_clock_speed =
12671 i915gm_get_display_clock_speed;
12672 else if (IS_I865G(dev))
12673 dev_priv->display.get_display_clock_speed =
12674 i865_get_display_clock_speed;
12675 else if (IS_I85X(dev))
12676 dev_priv->display.get_display_clock_speed =
12677 i855_get_display_clock_speed;
12678 else /* 852, 830 */
12679 dev_priv->display.get_display_clock_speed =
12680 i830_get_display_clock_speed;
12681
12682 if (IS_G4X(dev)) {
12683 dev_priv->display.write_eld = g4x_write_eld;
12684 } else if (IS_GEN5(dev)) {
12685 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12686 dev_priv->display.write_eld = ironlake_write_eld;
12687 } else if (IS_GEN6(dev)) {
12688 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12689 dev_priv->display.write_eld = ironlake_write_eld;
12690 dev_priv->display.modeset_global_resources =
12691 snb_modeset_global_resources;
12692 } else if (IS_IVYBRIDGE(dev)) {
12693 /* FIXME: detect B0+ stepping and use auto training */
12694 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12695 dev_priv->display.write_eld = ironlake_write_eld;
12696 dev_priv->display.modeset_global_resources =
12697 ivb_modeset_global_resources;
12698 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12699 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12700 dev_priv->display.write_eld = haswell_write_eld;
12701 dev_priv->display.modeset_global_resources =
12702 haswell_modeset_global_resources;
12703 } else if (IS_VALLEYVIEW(dev)) {
12704 dev_priv->display.modeset_global_resources =
12705 valleyview_modeset_global_resources;
12706 dev_priv->display.write_eld = ironlake_write_eld;
12707 }
12708
12709 /* Default just returns -ENODEV to indicate unsupported */
12710 dev_priv->display.queue_flip = intel_default_queue_flip;
12711
12712 switch (INTEL_INFO(dev)->gen) {
12713 case 2:
12714 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12715 break;
12716
12717 case 3:
12718 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12719 break;
12720
12721 case 4:
12722 case 5:
12723 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12724 break;
12725
12726 case 6:
12727 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12728 break;
12729 case 7:
12730 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12731 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12732 break;
12733 }
12734
12735 intel_panel_init_backlight_funcs(dev);
12736
12737 mutex_init(&dev_priv->pps_mutex);
12738 }
12739
12740 /*
12741 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12742 * resume, or other times. This quirk makes sure that's the case for
12743 * affected systems.
12744 */
12745 static void quirk_pipea_force(struct drm_device *dev)
12746 {
12747 struct drm_i915_private *dev_priv = dev->dev_private;
12748
12749 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12750 DRM_INFO("applying pipe a force quirk\n");
12751 }
12752
12753 static void quirk_pipeb_force(struct drm_device *dev)
12754 {
12755 struct drm_i915_private *dev_priv = dev->dev_private;
12756
12757 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
12758 DRM_INFO("applying pipe b force quirk\n");
12759 }
12760
12761 /*
12762 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12763 */
12764 static void quirk_ssc_force_disable(struct drm_device *dev)
12765 {
12766 struct drm_i915_private *dev_priv = dev->dev_private;
12767 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12768 DRM_INFO("applying lvds SSC disable quirk\n");
12769 }
12770
12771 /*
12772 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12773 * brightness value
12774 */
12775 static void quirk_invert_brightness(struct drm_device *dev)
12776 {
12777 struct drm_i915_private *dev_priv = dev->dev_private;
12778 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
12779 DRM_INFO("applying inverted panel brightness quirk\n");
12780 }
12781
12782 /* Some VBT's incorrectly indicate no backlight is present */
12783 static void quirk_backlight_present(struct drm_device *dev)
12784 {
12785 struct drm_i915_private *dev_priv = dev->dev_private;
12786 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
12787 DRM_INFO("applying backlight present quirk\n");
12788 }
12789
12790 struct intel_quirk {
12791 int device;
12792 int subsystem_vendor;
12793 int subsystem_device;
12794 void (*hook)(struct drm_device *dev);
12795 };
12796
12797 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12798 struct intel_dmi_quirk {
12799 void (*hook)(struct drm_device *dev);
12800 const struct dmi_system_id (*dmi_id_list)[];
12801 };
12802
12803 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12804 {
12805 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12806 return 1;
12807 }
12808
12809 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12810 {
12811 .dmi_id_list = &(const struct dmi_system_id[]) {
12812 {
12813 .callback = intel_dmi_reverse_brightness,
12814 .ident = "NCR Corporation",
12815 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12816 DMI_MATCH(DMI_PRODUCT_NAME, ""),
12817 },
12818 },
12819 { } /* terminating entry */
12820 },
12821 .hook = quirk_invert_brightness,
12822 },
12823 };
12824
12825 static struct intel_quirk intel_quirks[] = {
12826 /* HP Mini needs pipe A force quirk (LP: #322104) */
12827 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
12828
12829 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12830 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12831
12832 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12833 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12834
12835 /* 830 needs to leave pipe A & dpll A up */
12836 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
12837
12838 /* 830 needs to leave pipe B & dpll B up */
12839 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
12840
12841 /* Lenovo U160 cannot use SSC on LVDS */
12842 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
12843
12844 /* Sony Vaio Y cannot use SSC on LVDS */
12845 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
12846
12847 /* Acer Aspire 5734Z must invert backlight brightness */
12848 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12849
12850 /* Acer/eMachines G725 */
12851 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12852
12853 /* Acer/eMachines e725 */
12854 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12855
12856 /* Acer/Packard Bell NCL20 */
12857 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12858
12859 /* Acer Aspire 4736Z */
12860 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
12861
12862 /* Acer Aspire 5336 */
12863 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
12864
12865 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12866 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
12867
12868 /* Acer C720 Chromebook (Core i3 4005U) */
12869 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
12870
12871 /* Toshiba CB35 Chromebook (Celeron 2955U) */
12872 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
12873
12874 /* HP Chromebook 14 (Celeron 2955U) */
12875 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
12876 };
12877
12878 static void intel_init_quirks(struct drm_device *dev)
12879 {
12880 struct pci_dev *d = dev->pdev;
12881 int i;
12882
12883 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12884 struct intel_quirk *q = &intel_quirks[i];
12885
12886 if (d->device == q->device &&
12887 (d->subsystem_vendor == q->subsystem_vendor ||
12888 q->subsystem_vendor == PCI_ANY_ID) &&
12889 (d->subsystem_device == q->subsystem_device ||
12890 q->subsystem_device == PCI_ANY_ID))
12891 q->hook(dev);
12892 }
12893 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12894 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12895 intel_dmi_quirks[i].hook(dev);
12896 }
12897 }
12898
12899 /* Disable the VGA plane that we never use */
12900 static void i915_disable_vga(struct drm_device *dev)
12901 {
12902 struct drm_i915_private *dev_priv = dev->dev_private;
12903 u8 sr1;
12904 u32 vga_reg = i915_vgacntrl_reg(dev);
12905
12906 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12907 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
12908 outb(SR01, VGA_SR_INDEX);
12909 sr1 = inb(VGA_SR_DATA);
12910 outb(sr1 | 1<<5, VGA_SR_DATA);
12911 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12912 udelay(300);
12913
12914 /*
12915 * Fujitsu-Siemens Lifebook S6010 (830) has problems resuming
12916 * from S3 without preserving (some of?) the other bits.
12917 */
12918 I915_WRITE(vga_reg, dev_priv->bios_vgacntr | VGA_DISP_DISABLE);
12919 POSTING_READ(vga_reg);
12920 }
12921
12922 void intel_modeset_init_hw(struct drm_device *dev)
12923 {
12924 intel_prepare_ddi(dev);
12925
12926 if (IS_VALLEYVIEW(dev))
12927 vlv_update_cdclk(dev);
12928
12929 intel_init_clock_gating(dev);
12930
12931 intel_enable_gt_powersave(dev);
12932 }
12933
12934 void intel_modeset_suspend_hw(struct drm_device *dev)
12935 {
12936 intel_suspend_hw(dev);
12937 }
12938
12939 void intel_modeset_init(struct drm_device *dev)
12940 {
12941 struct drm_i915_private *dev_priv = dev->dev_private;
12942 int sprite, ret;
12943 enum pipe pipe;
12944 struct intel_crtc *crtc;
12945
12946 drm_mode_config_init(dev);
12947
12948 dev->mode_config.min_width = 0;
12949 dev->mode_config.min_height = 0;
12950
12951 dev->mode_config.preferred_depth = 24;
12952 dev->mode_config.prefer_shadow = 1;
12953
12954 dev->mode_config.funcs = &intel_mode_funcs;
12955
12956 intel_init_quirks(dev);
12957
12958 intel_init_pm(dev);
12959
12960 if (INTEL_INFO(dev)->num_pipes == 0)
12961 return;
12962
12963 intel_init_display(dev);
12964
12965 if (IS_GEN2(dev)) {
12966 dev->mode_config.max_width = 2048;
12967 dev->mode_config.max_height = 2048;
12968 } else if (IS_GEN3(dev)) {
12969 dev->mode_config.max_width = 4096;
12970 dev->mode_config.max_height = 4096;
12971 } else {
12972 dev->mode_config.max_width = 8192;
12973 dev->mode_config.max_height = 8192;
12974 }
12975
12976 if (IS_845G(dev) || IS_I865G(dev)) {
12977 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
12978 dev->mode_config.cursor_height = 1023;
12979 } else if (IS_GEN2(dev)) {
12980 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
12981 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
12982 } else {
12983 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
12984 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
12985 }
12986
12987 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
12988
12989 DRM_DEBUG_KMS("%d display pipe%s available.\n",
12990 INTEL_INFO(dev)->num_pipes,
12991 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
12992
12993 for_each_pipe(dev_priv, pipe) {
12994 intel_crtc_init(dev, pipe);
12995 for_each_sprite(pipe, sprite) {
12996 ret = intel_plane_init(dev, pipe, sprite);
12997 if (ret)
12998 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
12999 pipe_name(pipe), sprite_name(pipe, sprite), ret);
13000 }
13001 }
13002
13003 intel_init_dpio(dev);
13004
13005 intel_shared_dpll_init(dev);
13006
13007 /* save the BIOS value before clobbering it */
13008 dev_priv->bios_vgacntr = I915_READ(i915_vgacntrl_reg(dev));
13009 /* Just disable it once at startup */
13010 i915_disable_vga(dev);
13011 intel_setup_outputs(dev);
13012
13013 /* Just in case the BIOS is doing something questionable. */
13014 intel_disable_fbc(dev);
13015
13016 drm_modeset_lock_all(dev);
13017 intel_modeset_setup_hw_state(dev, false);
13018 drm_modeset_unlock_all(dev);
13019
13020 for_each_intel_crtc(dev, crtc) {
13021 if (!crtc->active)
13022 continue;
13023
13024 /*
13025 * Note that reserving the BIOS fb up front prevents us
13026 * from stuffing other stolen allocations like the ring
13027 * on top. This prevents some ugliness at boot time, and
13028 * can even allow for smooth boot transitions if the BIOS
13029 * fb is large enough for the active pipe configuration.
13030 */
13031 if (dev_priv->display.get_plane_config) {
13032 dev_priv->display.get_plane_config(crtc,
13033 &crtc->plane_config);
13034 /*
13035 * If the fb is shared between multiple heads, we'll
13036 * just get the first one.
13037 */
13038 intel_find_plane_obj(crtc, &crtc->plane_config);
13039 }
13040 }
13041 }
13042
13043 static void intel_enable_pipe_a(struct drm_device *dev)
13044 {
13045 struct intel_connector *connector;
13046 struct drm_connector *crt = NULL;
13047 struct intel_load_detect_pipe load_detect_temp;
13048 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
13049
13050 /* We can't just switch on the pipe A, we need to set things up with a
13051 * proper mode and output configuration. As a gross hack, enable pipe A
13052 * by enabling the load detect pipe once. */
13053 list_for_each_entry(connector,
13054 &dev->mode_config.connector_list,
13055 base.head) {
13056 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13057 crt = &connector->base;
13058 break;
13059 }
13060 }
13061
13062 if (!crt)
13063 return;
13064
13065 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13066 intel_release_load_detect_pipe(crt, &load_detect_temp);
13067 }
13068
13069 static bool
13070 intel_check_plane_mapping(struct intel_crtc *crtc)
13071 {
13072 struct drm_device *dev = crtc->base.dev;
13073 struct drm_i915_private *dev_priv = dev->dev_private;
13074 u32 reg, val;
13075
13076 if (INTEL_INFO(dev)->num_pipes == 1)
13077 return true;
13078
13079 reg = DSPCNTR(!crtc->plane);
13080 val = I915_READ(reg);
13081
13082 if ((val & DISPLAY_PLANE_ENABLE) &&
13083 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13084 return false;
13085
13086 return true;
13087 }
13088
13089 static void intel_sanitize_crtc(struct intel_crtc *crtc)
13090 {
13091 struct drm_device *dev = crtc->base.dev;
13092 struct drm_i915_private *dev_priv = dev->dev_private;
13093 u32 reg;
13094
13095 /* Clear any frame start delays used for debugging left by the BIOS */
13096 reg = PIPECONF(crtc->config.cpu_transcoder);
13097 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13098
13099 /* restore vblank interrupts to correct state */
13100 if (crtc->active) {
13101 update_scanline_offset(crtc);
13102 drm_vblank_on(dev, crtc->pipe);
13103 } else
13104 drm_vblank_off(dev, crtc->pipe);
13105
13106 /* We need to sanitize the plane -> pipe mapping first because this will
13107 * disable the crtc (and hence change the state) if it is wrong. Note
13108 * that gen4+ has a fixed plane -> pipe mapping. */
13109 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13110 struct intel_connector *connector;
13111 bool plane;
13112
13113 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13114 crtc->base.base.id);
13115
13116 /* Pipe has the wrong plane attached and the plane is active.
13117 * Temporarily change the plane mapping and disable everything
13118 * ... */
13119 plane = crtc->plane;
13120 crtc->plane = !plane;
13121 crtc->primary_enabled = true;
13122 dev_priv->display.crtc_disable(&crtc->base);
13123 crtc->plane = plane;
13124
13125 /* ... and break all links. */
13126 list_for_each_entry(connector, &dev->mode_config.connector_list,
13127 base.head) {
13128 if (connector->encoder->base.crtc != &crtc->base)
13129 continue;
13130
13131 connector->base.dpms = DRM_MODE_DPMS_OFF;
13132 connector->base.encoder = NULL;
13133 }
13134 /* multiple connectors may have the same encoder:
13135 * handle them and break crtc link separately */
13136 list_for_each_entry(connector, &dev->mode_config.connector_list,
13137 base.head)
13138 if (connector->encoder->base.crtc == &crtc->base) {
13139 connector->encoder->base.crtc = NULL;
13140 connector->encoder->connectors_active = false;
13141 }
13142
13143 WARN_ON(crtc->active);
13144 crtc->base.enabled = false;
13145 }
13146
13147 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13148 crtc->pipe == PIPE_A && !crtc->active) {
13149 /* BIOS forgot to enable pipe A, this mostly happens after
13150 * resume. Force-enable the pipe to fix this, the update_dpms
13151 * call below we restore the pipe to the right state, but leave
13152 * the required bits on. */
13153 intel_enable_pipe_a(dev);
13154 }
13155
13156 /* Adjust the state of the output pipe according to whether we
13157 * have active connectors/encoders. */
13158 intel_crtc_update_dpms(&crtc->base);
13159
13160 if (crtc->active != crtc->base.enabled) {
13161 struct intel_encoder *encoder;
13162
13163 /* This can happen either due to bugs in the get_hw_state
13164 * functions or because the pipe is force-enabled due to the
13165 * pipe A quirk. */
13166 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13167 crtc->base.base.id,
13168 crtc->base.enabled ? "enabled" : "disabled",
13169 crtc->active ? "enabled" : "disabled");
13170
13171 crtc->base.enabled = crtc->active;
13172
13173 /* Because we only establish the connector -> encoder ->
13174 * crtc links if something is active, this means the
13175 * crtc is now deactivated. Break the links. connector
13176 * -> encoder links are only establish when things are
13177 * actually up, hence no need to break them. */
13178 WARN_ON(crtc->active);
13179
13180 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13181 WARN_ON(encoder->connectors_active);
13182 encoder->base.crtc = NULL;
13183 }
13184 }
13185
13186 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13187 /*
13188 * We start out with underrun reporting disabled to avoid races.
13189 * For correct bookkeeping mark this on active crtcs.
13190 *
13191 * Also on gmch platforms we dont have any hardware bits to
13192 * disable the underrun reporting. Which means we need to start
13193 * out with underrun reporting disabled also on inactive pipes,
13194 * since otherwise we'll complain about the garbage we read when
13195 * e.g. coming up after runtime pm.
13196 *
13197 * No protection against concurrent access is required - at
13198 * worst a fifo underrun happens which also sets this to false.
13199 */
13200 crtc->cpu_fifo_underrun_disabled = true;
13201 crtc->pch_fifo_underrun_disabled = true;
13202 }
13203 }
13204
13205 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13206 {
13207 struct intel_connector *connector;
13208 struct drm_device *dev = encoder->base.dev;
13209
13210 /* We need to check both for a crtc link (meaning that the
13211 * encoder is active and trying to read from a pipe) and the
13212 * pipe itself being active. */
13213 bool has_active_crtc = encoder->base.crtc &&
13214 to_intel_crtc(encoder->base.crtc)->active;
13215
13216 if (encoder->connectors_active && !has_active_crtc) {
13217 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13218 encoder->base.base.id,
13219 encoder->base.name);
13220
13221 /* Connector is active, but has no active pipe. This is
13222 * fallout from our resume register restoring. Disable
13223 * the encoder manually again. */
13224 if (encoder->base.crtc) {
13225 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13226 encoder->base.base.id,
13227 encoder->base.name);
13228 encoder->disable(encoder);
13229 if (encoder->post_disable)
13230 encoder->post_disable(encoder);
13231 }
13232 encoder->base.crtc = NULL;
13233 encoder->connectors_active = false;
13234
13235 /* Inconsistent output/port/pipe state happens presumably due to
13236 * a bug in one of the get_hw_state functions. Or someplace else
13237 * in our code, like the register restore mess on resume. Clamp
13238 * things to off as a safer default. */
13239 list_for_each_entry(connector,
13240 &dev->mode_config.connector_list,
13241 base.head) {
13242 if (connector->encoder != encoder)
13243 continue;
13244 connector->base.dpms = DRM_MODE_DPMS_OFF;
13245 connector->base.encoder = NULL;
13246 }
13247 }
13248 /* Enabled encoders without active connectors will be fixed in
13249 * the crtc fixup. */
13250 }
13251
13252 void i915_redisable_vga_power_on(struct drm_device *dev)
13253 {
13254 struct drm_i915_private *dev_priv = dev->dev_private;
13255 u32 vga_reg = i915_vgacntrl_reg(dev);
13256
13257 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13258 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13259 i915_disable_vga(dev);
13260 }
13261 }
13262
13263 void i915_redisable_vga(struct drm_device *dev)
13264 {
13265 struct drm_i915_private *dev_priv = dev->dev_private;
13266
13267 /* This function can be called both from intel_modeset_setup_hw_state or
13268 * at a very early point in our resume sequence, where the power well
13269 * structures are not yet restored. Since this function is at a very
13270 * paranoid "someone might have enabled VGA while we were not looking"
13271 * level, just check if the power well is enabled instead of trying to
13272 * follow the "don't touch the power well if we don't need it" policy
13273 * the rest of the driver uses. */
13274 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
13275 return;
13276
13277 i915_redisable_vga_power_on(dev);
13278 }
13279
13280 static bool primary_get_hw_state(struct intel_crtc *crtc)
13281 {
13282 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13283
13284 if (!crtc->active)
13285 return false;
13286
13287 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13288 }
13289
13290 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13291 {
13292 struct drm_i915_private *dev_priv = dev->dev_private;
13293 enum pipe pipe;
13294 struct intel_crtc *crtc;
13295 struct intel_encoder *encoder;
13296 struct intel_connector *connector;
13297 int i;
13298
13299 for_each_intel_crtc(dev, crtc) {
13300 memset(&crtc->config, 0, sizeof(crtc->config));
13301
13302 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13303
13304 crtc->active = dev_priv->display.get_pipe_config(crtc,
13305 &crtc->config);
13306
13307 crtc->base.enabled = crtc->active;
13308 crtc->primary_enabled = primary_get_hw_state(crtc);
13309
13310 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13311 crtc->base.base.id,
13312 crtc->active ? "enabled" : "disabled");
13313 }
13314
13315 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13316 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13317
13318 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
13319 pll->active = 0;
13320 for_each_intel_crtc(dev, crtc) {
13321 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
13322 pll->active++;
13323 }
13324 pll->refcount = pll->active;
13325
13326 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
13327 pll->name, pll->refcount, pll->on);
13328
13329 if (pll->refcount)
13330 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13331 }
13332
13333 for_each_intel_encoder(dev, encoder) {
13334 pipe = 0;
13335
13336 if (encoder->get_hw_state(encoder, &pipe)) {
13337 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13338 encoder->base.crtc = &crtc->base;
13339 encoder->get_config(encoder, &crtc->config);
13340 } else {
13341 encoder->base.crtc = NULL;
13342 }
13343
13344 encoder->connectors_active = false;
13345 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13346 encoder->base.base.id,
13347 encoder->base.name,
13348 encoder->base.crtc ? "enabled" : "disabled",
13349 pipe_name(pipe));
13350 }
13351
13352 list_for_each_entry(connector, &dev->mode_config.connector_list,
13353 base.head) {
13354 if (connector->get_hw_state(connector)) {
13355 connector->base.dpms = DRM_MODE_DPMS_ON;
13356 connector->encoder->connectors_active = true;
13357 connector->base.encoder = &connector->encoder->base;
13358 } else {
13359 connector->base.dpms = DRM_MODE_DPMS_OFF;
13360 connector->base.encoder = NULL;
13361 }
13362 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13363 connector->base.base.id,
13364 connector->base.name,
13365 connector->base.encoder ? "enabled" : "disabled");
13366 }
13367 }
13368
13369 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13370 * and i915 state tracking structures. */
13371 void intel_modeset_setup_hw_state(struct drm_device *dev,
13372 bool force_restore)
13373 {
13374 struct drm_i915_private *dev_priv = dev->dev_private;
13375 enum pipe pipe;
13376 struct intel_crtc *crtc;
13377 struct intel_encoder *encoder;
13378 int i;
13379
13380 intel_modeset_readout_hw_state(dev);
13381
13382 /*
13383 * Now that we have the config, copy it to each CRTC struct
13384 * Note that this could go away if we move to using crtc_config
13385 * checking everywhere.
13386 */
13387 for_each_intel_crtc(dev, crtc) {
13388 if (crtc->active && i915.fastboot) {
13389 intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
13390 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13391 crtc->base.base.id);
13392 drm_mode_debug_printmodeline(&crtc->base.mode);
13393 }
13394 }
13395
13396 /* HW state is read out, now we need to sanitize this mess. */
13397 for_each_intel_encoder(dev, encoder) {
13398 intel_sanitize_encoder(encoder);
13399 }
13400
13401 for_each_pipe(dev_priv, pipe) {
13402 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13403 intel_sanitize_crtc(crtc);
13404 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
13405 }
13406
13407 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13408 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13409
13410 if (!pll->on || pll->active)
13411 continue;
13412
13413 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13414
13415 pll->disable(dev_priv, pll);
13416 pll->on = false;
13417 }
13418
13419 if (HAS_PCH_SPLIT(dev))
13420 ilk_wm_get_hw_state(dev);
13421
13422 if (force_restore) {
13423 i915_redisable_vga(dev);
13424
13425 /*
13426 * We need to use raw interfaces for restoring state to avoid
13427 * checking (bogus) intermediate states.
13428 */
13429 for_each_pipe(dev_priv, pipe) {
13430 struct drm_crtc *crtc =
13431 dev_priv->pipe_to_crtc_mapping[pipe];
13432
13433 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13434 crtc->primary->fb);
13435 }
13436 } else {
13437 intel_modeset_update_staged_output_state(dev);
13438 }
13439
13440 intel_modeset_check_state(dev);
13441 }
13442
13443 void intel_modeset_gem_init(struct drm_device *dev)
13444 {
13445 struct drm_crtc *c;
13446 struct drm_i915_gem_object *obj;
13447
13448 mutex_lock(&dev->struct_mutex);
13449 intel_init_gt_powersave(dev);
13450 mutex_unlock(&dev->struct_mutex);
13451
13452 intel_modeset_init_hw(dev);
13453
13454 intel_setup_overlay(dev);
13455
13456 /*
13457 * Make sure any fbs we allocated at startup are properly
13458 * pinned & fenced. When we do the allocation it's too early
13459 * for this.
13460 */
13461 mutex_lock(&dev->struct_mutex);
13462 for_each_crtc(dev, c) {
13463 obj = intel_fb_obj(c->primary->fb);
13464 if (obj == NULL)
13465 continue;
13466
13467 if (intel_pin_and_fence_fb_obj(dev, obj, NULL)) {
13468 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13469 to_intel_crtc(c)->pipe);
13470 drm_framebuffer_unreference(c->primary->fb);
13471 c->primary->fb = NULL;
13472 }
13473 }
13474 mutex_unlock(&dev->struct_mutex);
13475 }
13476
13477 void intel_connector_unregister(struct intel_connector *intel_connector)
13478 {
13479 struct drm_connector *connector = &intel_connector->base;
13480
13481 intel_panel_destroy_backlight(connector);
13482 drm_connector_unregister(connector);
13483 }
13484
13485 void intel_modeset_cleanup(struct drm_device *dev)
13486 {
13487 struct drm_i915_private *dev_priv = dev->dev_private;
13488 struct drm_connector *connector;
13489
13490 /*
13491 * Interrupts and polling as the first thing to avoid creating havoc.
13492 * Too much stuff here (turning of rps, connectors, ...) would
13493 * experience fancy races otherwise.
13494 */
13495 drm_irq_uninstall(dev);
13496 intel_hpd_cancel_work(dev_priv);
13497 dev_priv->pm._irqs_disabled = true;
13498
13499 /*
13500 * Due to the hpd irq storm handling the hotplug work can re-arm the
13501 * poll handlers. Hence disable polling after hpd handling is shut down.
13502 */
13503 drm_kms_helper_poll_fini(dev);
13504
13505 mutex_lock(&dev->struct_mutex);
13506
13507 intel_unregister_dsm_handler();
13508
13509 intel_disable_fbc(dev);
13510
13511 intel_disable_gt_powersave(dev);
13512
13513 ironlake_teardown_rc6(dev);
13514
13515 mutex_unlock(&dev->struct_mutex);
13516
13517 /* flush any delayed tasks or pending work */
13518 flush_scheduled_work();
13519
13520 /* destroy the backlight and sysfs files before encoders/connectors */
13521 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13522 struct intel_connector *intel_connector;
13523
13524 intel_connector = to_intel_connector(connector);
13525 intel_connector->unregister(intel_connector);
13526 }
13527
13528 drm_mode_config_cleanup(dev);
13529
13530 intel_cleanup_overlay(dev);
13531
13532 mutex_lock(&dev->struct_mutex);
13533 intel_cleanup_gt_powersave(dev);
13534 mutex_unlock(&dev->struct_mutex);
13535 }
13536
13537 /*
13538 * Return which encoder is currently attached for connector.
13539 */
13540 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13541 {
13542 return &intel_attached_encoder(connector)->base;
13543 }
13544
13545 void intel_connector_attach_encoder(struct intel_connector *connector,
13546 struct intel_encoder *encoder)
13547 {
13548 connector->encoder = encoder;
13549 drm_mode_connector_attach_encoder(&connector->base,
13550 &encoder->base);
13551 }
13552
13553 /*
13554 * set vga decode state - true == enable VGA decode
13555 */
13556 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13557 {
13558 struct drm_i915_private *dev_priv = dev->dev_private;
13559 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13560 u16 gmch_ctrl;
13561
13562 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13563 DRM_ERROR("failed to read control word\n");
13564 return -EIO;
13565 }
13566
13567 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13568 return 0;
13569
13570 if (state)
13571 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13572 else
13573 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13574
13575 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13576 DRM_ERROR("failed to write control word\n");
13577 return -EIO;
13578 }
13579
13580 return 0;
13581 }
13582
13583 struct intel_display_error_state {
13584
13585 u32 power_well_driver;
13586
13587 int num_transcoders;
13588
13589 struct intel_cursor_error_state {
13590 u32 control;
13591 u32 position;
13592 u32 base;
13593 u32 size;
13594 } cursor[I915_MAX_PIPES];
13595
13596 struct intel_pipe_error_state {
13597 bool power_domain_on;
13598 u32 source;
13599 u32 stat;
13600 } pipe[I915_MAX_PIPES];
13601
13602 struct intel_plane_error_state {
13603 u32 control;
13604 u32 stride;
13605 u32 size;
13606 u32 pos;
13607 u32 addr;
13608 u32 surface;
13609 u32 tile_offset;
13610 } plane[I915_MAX_PIPES];
13611
13612 struct intel_transcoder_error_state {
13613 bool power_domain_on;
13614 enum transcoder cpu_transcoder;
13615
13616 u32 conf;
13617
13618 u32 htotal;
13619 u32 hblank;
13620 u32 hsync;
13621 u32 vtotal;
13622 u32 vblank;
13623 u32 vsync;
13624 } transcoder[4];
13625 };
13626
13627 struct intel_display_error_state *
13628 intel_display_capture_error_state(struct drm_device *dev)
13629 {
13630 struct drm_i915_private *dev_priv = dev->dev_private;
13631 struct intel_display_error_state *error;
13632 int transcoders[] = {
13633 TRANSCODER_A,
13634 TRANSCODER_B,
13635 TRANSCODER_C,
13636 TRANSCODER_EDP,
13637 };
13638 int i;
13639
13640 if (INTEL_INFO(dev)->num_pipes == 0)
13641 return NULL;
13642
13643 error = kzalloc(sizeof(*error), GFP_ATOMIC);
13644 if (error == NULL)
13645 return NULL;
13646
13647 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13648 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13649
13650 for_each_pipe(dev_priv, i) {
13651 error->pipe[i].power_domain_on =
13652 intel_display_power_enabled_unlocked(dev_priv,
13653 POWER_DOMAIN_PIPE(i));
13654 if (!error->pipe[i].power_domain_on)
13655 continue;
13656
13657 error->cursor[i].control = I915_READ(CURCNTR(i));
13658 error->cursor[i].position = I915_READ(CURPOS(i));
13659 error->cursor[i].base = I915_READ(CURBASE(i));
13660
13661 error->plane[i].control = I915_READ(DSPCNTR(i));
13662 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13663 if (INTEL_INFO(dev)->gen <= 3) {
13664 error->plane[i].size = I915_READ(DSPSIZE(i));
13665 error->plane[i].pos = I915_READ(DSPPOS(i));
13666 }
13667 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13668 error->plane[i].addr = I915_READ(DSPADDR(i));
13669 if (INTEL_INFO(dev)->gen >= 4) {
13670 error->plane[i].surface = I915_READ(DSPSURF(i));
13671 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13672 }
13673
13674 error->pipe[i].source = I915_READ(PIPESRC(i));
13675
13676 if (HAS_GMCH_DISPLAY(dev))
13677 error->pipe[i].stat = I915_READ(PIPESTAT(i));
13678 }
13679
13680 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13681 if (HAS_DDI(dev_priv->dev))
13682 error->num_transcoders++; /* Account for eDP. */
13683
13684 for (i = 0; i < error->num_transcoders; i++) {
13685 enum transcoder cpu_transcoder = transcoders[i];
13686
13687 error->transcoder[i].power_domain_on =
13688 intel_display_power_enabled_unlocked(dev_priv,
13689 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13690 if (!error->transcoder[i].power_domain_on)
13691 continue;
13692
13693 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13694
13695 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13696 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13697 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13698 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13699 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13700 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13701 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13702 }
13703
13704 return error;
13705 }
13706
13707 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13708
13709 void
13710 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13711 struct drm_device *dev,
13712 struct intel_display_error_state *error)
13713 {
13714 struct drm_i915_private *dev_priv = dev->dev_private;
13715 int i;
13716
13717 if (!error)
13718 return;
13719
13720 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13721 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13722 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13723 error->power_well_driver);
13724 for_each_pipe(dev_priv, i) {
13725 err_printf(m, "Pipe [%d]:\n", i);
13726 err_printf(m, " Power: %s\n",
13727 error->pipe[i].power_domain_on ? "on" : "off");
13728 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
13729 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
13730
13731 err_printf(m, "Plane [%d]:\n", i);
13732 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
13733 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
13734 if (INTEL_INFO(dev)->gen <= 3) {
13735 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
13736 err_printf(m, " POS: %08x\n", error->plane[i].pos);
13737 }
13738 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13739 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
13740 if (INTEL_INFO(dev)->gen >= 4) {
13741 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
13742 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
13743 }
13744
13745 err_printf(m, "Cursor [%d]:\n", i);
13746 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
13747 err_printf(m, " POS: %08x\n", error->cursor[i].position);
13748 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
13749 }
13750
13751 for (i = 0; i < error->num_transcoders; i++) {
13752 err_printf(m, "CPU transcoder: %c\n",
13753 transcoder_name(error->transcoder[i].cpu_transcoder));
13754 err_printf(m, " Power: %s\n",
13755 error->transcoder[i].power_domain_on ? "on" : "off");
13756 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
13757 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
13758 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
13759 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
13760 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
13761 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
13762 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
13763 }
13764 }
13765
13766 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
13767 {
13768 struct intel_crtc *crtc;
13769
13770 for_each_intel_crtc(dev, crtc) {
13771 struct intel_unpin_work *work;
13772 unsigned long irqflags;
13773
13774 spin_lock_irqsave(&dev->event_lock, irqflags);
13775
13776 work = crtc->unpin_work;
13777
13778 if (work && work->event &&
13779 work->event->base.file_priv == file) {
13780 kfree(work->event);
13781 work->event = NULL;
13782 }
13783
13784 spin_unlock_irqrestore(&dev->event_lock, irqflags);
13785 }
13786 }
Linux kernel - Deliverables
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