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drm/i915: vlv: get power domain for eDP vdd
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
43
44 static void intel_increase_pllclock(struct drm_crtc *crtc);
45 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
46
47 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
48 struct intel_crtc_config *pipe_config);
49 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
50 struct intel_crtc_config *pipe_config);
51
52 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
53 int x, int y, struct drm_framebuffer *old_fb);
54 static int intel_framebuffer_init(struct drm_device *dev,
55 struct intel_framebuffer *ifb,
56 struct drm_mode_fb_cmd2 *mode_cmd,
57 struct drm_i915_gem_object *obj);
58
59 typedef struct {
60 int min, max;
61 } intel_range_t;
62
63 typedef struct {
64 int dot_limit;
65 int p2_slow, p2_fast;
66 } intel_p2_t;
67
68 typedef struct intel_limit intel_limit_t;
69 struct intel_limit {
70 intel_range_t dot, vco, n, m, m1, m2, p, p1;
71 intel_p2_t p2;
72 };
73
74 int
75 intel_pch_rawclk(struct drm_device *dev)
76 {
77 struct drm_i915_private *dev_priv = dev->dev_private;
78
79 WARN_ON(!HAS_PCH_SPLIT(dev));
80
81 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
82 }
83
84 static inline u32 /* units of 100MHz */
85 intel_fdi_link_freq(struct drm_device *dev)
86 {
87 if (IS_GEN5(dev)) {
88 struct drm_i915_private *dev_priv = dev->dev_private;
89 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
90 } else
91 return 27;
92 }
93
94 static const intel_limit_t intel_limits_i8xx_dac = {
95 .dot = { .min = 25000, .max = 350000 },
96 .vco = { .min = 908000, .max = 1512000 },
97 .n = { .min = 2, .max = 16 },
98 .m = { .min = 96, .max = 140 },
99 .m1 = { .min = 18, .max = 26 },
100 .m2 = { .min = 6, .max = 16 },
101 .p = { .min = 4, .max = 128 },
102 .p1 = { .min = 2, .max = 33 },
103 .p2 = { .dot_limit = 165000,
104 .p2_slow = 4, .p2_fast = 2 },
105 };
106
107 static const intel_limit_t intel_limits_i8xx_dvo = {
108 .dot = { .min = 25000, .max = 350000 },
109 .vco = { .min = 908000, .max = 1512000 },
110 .n = { .min = 2, .max = 16 },
111 .m = { .min = 96, .max = 140 },
112 .m1 = { .min = 18, .max = 26 },
113 .m2 = { .min = 6, .max = 16 },
114 .p = { .min = 4, .max = 128 },
115 .p1 = { .min = 2, .max = 33 },
116 .p2 = { .dot_limit = 165000,
117 .p2_slow = 4, .p2_fast = 4 },
118 };
119
120 static const intel_limit_t intel_limits_i8xx_lvds = {
121 .dot = { .min = 25000, .max = 350000 },
122 .vco = { .min = 908000, .max = 1512000 },
123 .n = { .min = 2, .max = 16 },
124 .m = { .min = 96, .max = 140 },
125 .m1 = { .min = 18, .max = 26 },
126 .m2 = { .min = 6, .max = 16 },
127 .p = { .min = 4, .max = 128 },
128 .p1 = { .min = 1, .max = 6 },
129 .p2 = { .dot_limit = 165000,
130 .p2_slow = 14, .p2_fast = 7 },
131 };
132
133 static const intel_limit_t intel_limits_i9xx_sdvo = {
134 .dot = { .min = 20000, .max = 400000 },
135 .vco = { .min = 1400000, .max = 2800000 },
136 .n = { .min = 1, .max = 6 },
137 .m = { .min = 70, .max = 120 },
138 .m1 = { .min = 8, .max = 18 },
139 .m2 = { .min = 3, .max = 7 },
140 .p = { .min = 5, .max = 80 },
141 .p1 = { .min = 1, .max = 8 },
142 .p2 = { .dot_limit = 200000,
143 .p2_slow = 10, .p2_fast = 5 },
144 };
145
146 static const intel_limit_t intel_limits_i9xx_lvds = {
147 .dot = { .min = 20000, .max = 400000 },
148 .vco = { .min = 1400000, .max = 2800000 },
149 .n = { .min = 1, .max = 6 },
150 .m = { .min = 70, .max = 120 },
151 .m1 = { .min = 8, .max = 18 },
152 .m2 = { .min = 3, .max = 7 },
153 .p = { .min = 7, .max = 98 },
154 .p1 = { .min = 1, .max = 8 },
155 .p2 = { .dot_limit = 112000,
156 .p2_slow = 14, .p2_fast = 7 },
157 };
158
159
160 static const intel_limit_t intel_limits_g4x_sdvo = {
161 .dot = { .min = 25000, .max = 270000 },
162 .vco = { .min = 1750000, .max = 3500000},
163 .n = { .min = 1, .max = 4 },
164 .m = { .min = 104, .max = 138 },
165 .m1 = { .min = 17, .max = 23 },
166 .m2 = { .min = 5, .max = 11 },
167 .p = { .min = 10, .max = 30 },
168 .p1 = { .min = 1, .max = 3},
169 .p2 = { .dot_limit = 270000,
170 .p2_slow = 10,
171 .p2_fast = 10
172 },
173 };
174
175 static const intel_limit_t intel_limits_g4x_hdmi = {
176 .dot = { .min = 22000, .max = 400000 },
177 .vco = { .min = 1750000, .max = 3500000},
178 .n = { .min = 1, .max = 4 },
179 .m = { .min = 104, .max = 138 },
180 .m1 = { .min = 16, .max = 23 },
181 .m2 = { .min = 5, .max = 11 },
182 .p = { .min = 5, .max = 80 },
183 .p1 = { .min = 1, .max = 8},
184 .p2 = { .dot_limit = 165000,
185 .p2_slow = 10, .p2_fast = 5 },
186 };
187
188 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
189 .dot = { .min = 20000, .max = 115000 },
190 .vco = { .min = 1750000, .max = 3500000 },
191 .n = { .min = 1, .max = 3 },
192 .m = { .min = 104, .max = 138 },
193 .m1 = { .min = 17, .max = 23 },
194 .m2 = { .min = 5, .max = 11 },
195 .p = { .min = 28, .max = 112 },
196 .p1 = { .min = 2, .max = 8 },
197 .p2 = { .dot_limit = 0,
198 .p2_slow = 14, .p2_fast = 14
199 },
200 };
201
202 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
203 .dot = { .min = 80000, .max = 224000 },
204 .vco = { .min = 1750000, .max = 3500000 },
205 .n = { .min = 1, .max = 3 },
206 .m = { .min = 104, .max = 138 },
207 .m1 = { .min = 17, .max = 23 },
208 .m2 = { .min = 5, .max = 11 },
209 .p = { .min = 14, .max = 42 },
210 .p1 = { .min = 2, .max = 6 },
211 .p2 = { .dot_limit = 0,
212 .p2_slow = 7, .p2_fast = 7
213 },
214 };
215
216 static const intel_limit_t intel_limits_pineview_sdvo = {
217 .dot = { .min = 20000, .max = 400000},
218 .vco = { .min = 1700000, .max = 3500000 },
219 /* Pineview's Ncounter is a ring counter */
220 .n = { .min = 3, .max = 6 },
221 .m = { .min = 2, .max = 256 },
222 /* Pineview only has one combined m divider, which we treat as m2. */
223 .m1 = { .min = 0, .max = 0 },
224 .m2 = { .min = 0, .max = 254 },
225 .p = { .min = 5, .max = 80 },
226 .p1 = { .min = 1, .max = 8 },
227 .p2 = { .dot_limit = 200000,
228 .p2_slow = 10, .p2_fast = 5 },
229 };
230
231 static const intel_limit_t intel_limits_pineview_lvds = {
232 .dot = { .min = 20000, .max = 400000 },
233 .vco = { .min = 1700000, .max = 3500000 },
234 .n = { .min = 3, .max = 6 },
235 .m = { .min = 2, .max = 256 },
236 .m1 = { .min = 0, .max = 0 },
237 .m2 = { .min = 0, .max = 254 },
238 .p = { .min = 7, .max = 112 },
239 .p1 = { .min = 1, .max = 8 },
240 .p2 = { .dot_limit = 112000,
241 .p2_slow = 14, .p2_fast = 14 },
242 };
243
244 /* Ironlake / Sandybridge
245 *
246 * We calculate clock using (register_value + 2) for N/M1/M2, so here
247 * the range value for them is (actual_value - 2).
248 */
249 static const intel_limit_t intel_limits_ironlake_dac = {
250 .dot = { .min = 25000, .max = 350000 },
251 .vco = { .min = 1760000, .max = 3510000 },
252 .n = { .min = 1, .max = 5 },
253 .m = { .min = 79, .max = 127 },
254 .m1 = { .min = 12, .max = 22 },
255 .m2 = { .min = 5, .max = 9 },
256 .p = { .min = 5, .max = 80 },
257 .p1 = { .min = 1, .max = 8 },
258 .p2 = { .dot_limit = 225000,
259 .p2_slow = 10, .p2_fast = 5 },
260 };
261
262 static const intel_limit_t intel_limits_ironlake_single_lvds = {
263 .dot = { .min = 25000, .max = 350000 },
264 .vco = { .min = 1760000, .max = 3510000 },
265 .n = { .min = 1, .max = 3 },
266 .m = { .min = 79, .max = 118 },
267 .m1 = { .min = 12, .max = 22 },
268 .m2 = { .min = 5, .max = 9 },
269 .p = { .min = 28, .max = 112 },
270 .p1 = { .min = 2, .max = 8 },
271 .p2 = { .dot_limit = 225000,
272 .p2_slow = 14, .p2_fast = 14 },
273 };
274
275 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
276 .dot = { .min = 25000, .max = 350000 },
277 .vco = { .min = 1760000, .max = 3510000 },
278 .n = { .min = 1, .max = 3 },
279 .m = { .min = 79, .max = 127 },
280 .m1 = { .min = 12, .max = 22 },
281 .m2 = { .min = 5, .max = 9 },
282 .p = { .min = 14, .max = 56 },
283 .p1 = { .min = 2, .max = 8 },
284 .p2 = { .dot_limit = 225000,
285 .p2_slow = 7, .p2_fast = 7 },
286 };
287
288 /* LVDS 100mhz refclk limits. */
289 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
290 .dot = { .min = 25000, .max = 350000 },
291 .vco = { .min = 1760000, .max = 3510000 },
292 .n = { .min = 1, .max = 2 },
293 .m = { .min = 79, .max = 126 },
294 .m1 = { .min = 12, .max = 22 },
295 .m2 = { .min = 5, .max = 9 },
296 .p = { .min = 28, .max = 112 },
297 .p1 = { .min = 2, .max = 8 },
298 .p2 = { .dot_limit = 225000,
299 .p2_slow = 14, .p2_fast = 14 },
300 };
301
302 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
303 .dot = { .min = 25000, .max = 350000 },
304 .vco = { .min = 1760000, .max = 3510000 },
305 .n = { .min = 1, .max = 3 },
306 .m = { .min = 79, .max = 126 },
307 .m1 = { .min = 12, .max = 22 },
308 .m2 = { .min = 5, .max = 9 },
309 .p = { .min = 14, .max = 42 },
310 .p1 = { .min = 2, .max = 6 },
311 .p2 = { .dot_limit = 225000,
312 .p2_slow = 7, .p2_fast = 7 },
313 };
314
315 static const intel_limit_t intel_limits_vlv = {
316 /*
317 * These are the data rate limits (measured in fast clocks)
318 * since those are the strictest limits we have. The fast
319 * clock and actual rate limits are more relaxed, so checking
320 * them would make no difference.
321 */
322 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
323 .vco = { .min = 4000000, .max = 6000000 },
324 .n = { .min = 1, .max = 7 },
325 .m1 = { .min = 2, .max = 3 },
326 .m2 = { .min = 11, .max = 156 },
327 .p1 = { .min = 2, .max = 3 },
328 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
329 };
330
331 static void vlv_clock(int refclk, intel_clock_t *clock)
332 {
333 clock->m = clock->m1 * clock->m2;
334 clock->p = clock->p1 * clock->p2;
335 if (WARN_ON(clock->n == 0 || clock->p == 0))
336 return;
337 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
338 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
339 }
340
341 /**
342 * Returns whether any output on the specified pipe is of the specified type
343 */
344 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
345 {
346 struct drm_device *dev = crtc->dev;
347 struct intel_encoder *encoder;
348
349 for_each_encoder_on_crtc(dev, crtc, encoder)
350 if (encoder->type == type)
351 return true;
352
353 return false;
354 }
355
356 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
357 int refclk)
358 {
359 struct drm_device *dev = crtc->dev;
360 const intel_limit_t *limit;
361
362 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
363 if (intel_is_dual_link_lvds(dev)) {
364 if (refclk == 100000)
365 limit = &intel_limits_ironlake_dual_lvds_100m;
366 else
367 limit = &intel_limits_ironlake_dual_lvds;
368 } else {
369 if (refclk == 100000)
370 limit = &intel_limits_ironlake_single_lvds_100m;
371 else
372 limit = &intel_limits_ironlake_single_lvds;
373 }
374 } else
375 limit = &intel_limits_ironlake_dac;
376
377 return limit;
378 }
379
380 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
381 {
382 struct drm_device *dev = crtc->dev;
383 const intel_limit_t *limit;
384
385 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
386 if (intel_is_dual_link_lvds(dev))
387 limit = &intel_limits_g4x_dual_channel_lvds;
388 else
389 limit = &intel_limits_g4x_single_channel_lvds;
390 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
391 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
392 limit = &intel_limits_g4x_hdmi;
393 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
394 limit = &intel_limits_g4x_sdvo;
395 } else /* The option is for other outputs */
396 limit = &intel_limits_i9xx_sdvo;
397
398 return limit;
399 }
400
401 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
402 {
403 struct drm_device *dev = crtc->dev;
404 const intel_limit_t *limit;
405
406 if (HAS_PCH_SPLIT(dev))
407 limit = intel_ironlake_limit(crtc, refclk);
408 else if (IS_G4X(dev)) {
409 limit = intel_g4x_limit(crtc);
410 } else if (IS_PINEVIEW(dev)) {
411 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
412 limit = &intel_limits_pineview_lvds;
413 else
414 limit = &intel_limits_pineview_sdvo;
415 } else if (IS_VALLEYVIEW(dev)) {
416 limit = &intel_limits_vlv;
417 } else if (!IS_GEN2(dev)) {
418 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
419 limit = &intel_limits_i9xx_lvds;
420 else
421 limit = &intel_limits_i9xx_sdvo;
422 } else {
423 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
424 limit = &intel_limits_i8xx_lvds;
425 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
426 limit = &intel_limits_i8xx_dvo;
427 else
428 limit = &intel_limits_i8xx_dac;
429 }
430 return limit;
431 }
432
433 /* m1 is reserved as 0 in Pineview, n is a ring counter */
434 static void pineview_clock(int refclk, intel_clock_t *clock)
435 {
436 clock->m = clock->m2 + 2;
437 clock->p = clock->p1 * clock->p2;
438 if (WARN_ON(clock->n == 0 || clock->p == 0))
439 return;
440 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
441 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
442 }
443
444 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
445 {
446 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
447 }
448
449 static void i9xx_clock(int refclk, intel_clock_t *clock)
450 {
451 clock->m = i9xx_dpll_compute_m(clock);
452 clock->p = clock->p1 * clock->p2;
453 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
454 return;
455 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
456 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
457 }
458
459 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
460 /**
461 * Returns whether the given set of divisors are valid for a given refclk with
462 * the given connectors.
463 */
464
465 static bool intel_PLL_is_valid(struct drm_device *dev,
466 const intel_limit_t *limit,
467 const intel_clock_t *clock)
468 {
469 if (clock->n < limit->n.min || limit->n.max < clock->n)
470 INTELPllInvalid("n out of range\n");
471 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
472 INTELPllInvalid("p1 out of range\n");
473 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
474 INTELPllInvalid("m2 out of range\n");
475 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
476 INTELPllInvalid("m1 out of range\n");
477
478 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
479 if (clock->m1 <= clock->m2)
480 INTELPllInvalid("m1 <= m2\n");
481
482 if (!IS_VALLEYVIEW(dev)) {
483 if (clock->p < limit->p.min || limit->p.max < clock->p)
484 INTELPllInvalid("p out of range\n");
485 if (clock->m < limit->m.min || limit->m.max < clock->m)
486 INTELPllInvalid("m out of range\n");
487 }
488
489 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
490 INTELPllInvalid("vco out of range\n");
491 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
492 * connector, etc., rather than just a single range.
493 */
494 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
495 INTELPllInvalid("dot out of range\n");
496
497 return true;
498 }
499
500 static bool
501 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
502 int target, int refclk, intel_clock_t *match_clock,
503 intel_clock_t *best_clock)
504 {
505 struct drm_device *dev = crtc->dev;
506 intel_clock_t clock;
507 int err = target;
508
509 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
510 /*
511 * For LVDS just rely on its current settings for dual-channel.
512 * We haven't figured out how to reliably set up different
513 * single/dual channel state, if we even can.
514 */
515 if (intel_is_dual_link_lvds(dev))
516 clock.p2 = limit->p2.p2_fast;
517 else
518 clock.p2 = limit->p2.p2_slow;
519 } else {
520 if (target < limit->p2.dot_limit)
521 clock.p2 = limit->p2.p2_slow;
522 else
523 clock.p2 = limit->p2.p2_fast;
524 }
525
526 memset(best_clock, 0, sizeof(*best_clock));
527
528 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
529 clock.m1++) {
530 for (clock.m2 = limit->m2.min;
531 clock.m2 <= limit->m2.max; clock.m2++) {
532 if (clock.m2 >= clock.m1)
533 break;
534 for (clock.n = limit->n.min;
535 clock.n <= limit->n.max; clock.n++) {
536 for (clock.p1 = limit->p1.min;
537 clock.p1 <= limit->p1.max; clock.p1++) {
538 int this_err;
539
540 i9xx_clock(refclk, &clock);
541 if (!intel_PLL_is_valid(dev, limit,
542 &clock))
543 continue;
544 if (match_clock &&
545 clock.p != match_clock->p)
546 continue;
547
548 this_err = abs(clock.dot - target);
549 if (this_err < err) {
550 *best_clock = clock;
551 err = this_err;
552 }
553 }
554 }
555 }
556 }
557
558 return (err != target);
559 }
560
561 static bool
562 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
563 int target, int refclk, intel_clock_t *match_clock,
564 intel_clock_t *best_clock)
565 {
566 struct drm_device *dev = crtc->dev;
567 intel_clock_t clock;
568 int err = target;
569
570 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
571 /*
572 * For LVDS just rely on its current settings for dual-channel.
573 * We haven't figured out how to reliably set up different
574 * single/dual channel state, if we even can.
575 */
576 if (intel_is_dual_link_lvds(dev))
577 clock.p2 = limit->p2.p2_fast;
578 else
579 clock.p2 = limit->p2.p2_slow;
580 } else {
581 if (target < limit->p2.dot_limit)
582 clock.p2 = limit->p2.p2_slow;
583 else
584 clock.p2 = limit->p2.p2_fast;
585 }
586
587 memset(best_clock, 0, sizeof(*best_clock));
588
589 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
590 clock.m1++) {
591 for (clock.m2 = limit->m2.min;
592 clock.m2 <= limit->m2.max; clock.m2++) {
593 for (clock.n = limit->n.min;
594 clock.n <= limit->n.max; clock.n++) {
595 for (clock.p1 = limit->p1.min;
596 clock.p1 <= limit->p1.max; clock.p1++) {
597 int this_err;
598
599 pineview_clock(refclk, &clock);
600 if (!intel_PLL_is_valid(dev, limit,
601 &clock))
602 continue;
603 if (match_clock &&
604 clock.p != match_clock->p)
605 continue;
606
607 this_err = abs(clock.dot - target);
608 if (this_err < err) {
609 *best_clock = clock;
610 err = this_err;
611 }
612 }
613 }
614 }
615 }
616
617 return (err != target);
618 }
619
620 static bool
621 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
622 int target, int refclk, intel_clock_t *match_clock,
623 intel_clock_t *best_clock)
624 {
625 struct drm_device *dev = crtc->dev;
626 intel_clock_t clock;
627 int max_n;
628 bool found;
629 /* approximately equals target * 0.00585 */
630 int err_most = (target >> 8) + (target >> 9);
631 found = false;
632
633 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
634 if (intel_is_dual_link_lvds(dev))
635 clock.p2 = limit->p2.p2_fast;
636 else
637 clock.p2 = limit->p2.p2_slow;
638 } else {
639 if (target < limit->p2.dot_limit)
640 clock.p2 = limit->p2.p2_slow;
641 else
642 clock.p2 = limit->p2.p2_fast;
643 }
644
645 memset(best_clock, 0, sizeof(*best_clock));
646 max_n = limit->n.max;
647 /* based on hardware requirement, prefer smaller n to precision */
648 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
649 /* based on hardware requirement, prefere larger m1,m2 */
650 for (clock.m1 = limit->m1.max;
651 clock.m1 >= limit->m1.min; clock.m1--) {
652 for (clock.m2 = limit->m2.max;
653 clock.m2 >= limit->m2.min; clock.m2--) {
654 for (clock.p1 = limit->p1.max;
655 clock.p1 >= limit->p1.min; clock.p1--) {
656 int this_err;
657
658 i9xx_clock(refclk, &clock);
659 if (!intel_PLL_is_valid(dev, limit,
660 &clock))
661 continue;
662
663 this_err = abs(clock.dot - target);
664 if (this_err < err_most) {
665 *best_clock = clock;
666 err_most = this_err;
667 max_n = clock.n;
668 found = true;
669 }
670 }
671 }
672 }
673 }
674 return found;
675 }
676
677 static bool
678 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
679 int target, int refclk, intel_clock_t *match_clock,
680 intel_clock_t *best_clock)
681 {
682 struct drm_device *dev = crtc->dev;
683 intel_clock_t clock;
684 unsigned int bestppm = 1000000;
685 /* min update 19.2 MHz */
686 int max_n = min(limit->n.max, refclk / 19200);
687 bool found = false;
688
689 target *= 5; /* fast clock */
690
691 memset(best_clock, 0, sizeof(*best_clock));
692
693 /* based on hardware requirement, prefer smaller n to precision */
694 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
695 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
696 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
697 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
698 clock.p = clock.p1 * clock.p2;
699 /* based on hardware requirement, prefer bigger m1,m2 values */
700 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
701 unsigned int ppm, diff;
702
703 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
704 refclk * clock.m1);
705
706 vlv_clock(refclk, &clock);
707
708 if (!intel_PLL_is_valid(dev, limit,
709 &clock))
710 continue;
711
712 diff = abs(clock.dot - target);
713 ppm = div_u64(1000000ULL * diff, target);
714
715 if (ppm < 100 && clock.p > best_clock->p) {
716 bestppm = 0;
717 *best_clock = clock;
718 found = true;
719 }
720
721 if (bestppm >= 10 && ppm < bestppm - 10) {
722 bestppm = ppm;
723 *best_clock = clock;
724 found = true;
725 }
726 }
727 }
728 }
729 }
730
731 return found;
732 }
733
734 bool intel_crtc_active(struct drm_crtc *crtc)
735 {
736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
737
738 /* Be paranoid as we can arrive here with only partial
739 * state retrieved from the hardware during setup.
740 *
741 * We can ditch the adjusted_mode.crtc_clock check as soon
742 * as Haswell has gained clock readout/fastboot support.
743 *
744 * We can ditch the crtc->fb check as soon as we can
745 * properly reconstruct framebuffers.
746 */
747 return intel_crtc->active && crtc->fb &&
748 intel_crtc->config.adjusted_mode.crtc_clock;
749 }
750
751 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
752 enum pipe pipe)
753 {
754 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
755 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756
757 return intel_crtc->config.cpu_transcoder;
758 }
759
760 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
761 {
762 struct drm_i915_private *dev_priv = dev->dev_private;
763 u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
764
765 frame = I915_READ(frame_reg);
766
767 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
768 DRM_DEBUG_KMS("vblank wait timed out\n");
769 }
770
771 /**
772 * intel_wait_for_vblank - wait for vblank on a given pipe
773 * @dev: drm device
774 * @pipe: pipe to wait for
775 *
776 * Wait for vblank to occur on a given pipe. Needed for various bits of
777 * mode setting code.
778 */
779 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
780 {
781 struct drm_i915_private *dev_priv = dev->dev_private;
782 int pipestat_reg = PIPESTAT(pipe);
783
784 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
785 g4x_wait_for_vblank(dev, pipe);
786 return;
787 }
788
789 /* Clear existing vblank status. Note this will clear any other
790 * sticky status fields as well.
791 *
792 * This races with i915_driver_irq_handler() with the result
793 * that either function could miss a vblank event. Here it is not
794 * fatal, as we will either wait upon the next vblank interrupt or
795 * timeout. Generally speaking intel_wait_for_vblank() is only
796 * called during modeset at which time the GPU should be idle and
797 * should *not* be performing page flips and thus not waiting on
798 * vblanks...
799 * Currently, the result of us stealing a vblank from the irq
800 * handler is that a single frame will be skipped during swapbuffers.
801 */
802 I915_WRITE(pipestat_reg,
803 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
804
805 /* Wait for vblank interrupt bit to set */
806 if (wait_for(I915_READ(pipestat_reg) &
807 PIPE_VBLANK_INTERRUPT_STATUS,
808 50))
809 DRM_DEBUG_KMS("vblank wait timed out\n");
810 }
811
812 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
813 {
814 struct drm_i915_private *dev_priv = dev->dev_private;
815 u32 reg = PIPEDSL(pipe);
816 u32 line1, line2;
817 u32 line_mask;
818
819 if (IS_GEN2(dev))
820 line_mask = DSL_LINEMASK_GEN2;
821 else
822 line_mask = DSL_LINEMASK_GEN3;
823
824 line1 = I915_READ(reg) & line_mask;
825 mdelay(5);
826 line2 = I915_READ(reg) & line_mask;
827
828 return line1 == line2;
829 }
830
831 /*
832 * intel_wait_for_pipe_off - wait for pipe to turn off
833 * @dev: drm device
834 * @pipe: pipe to wait for
835 *
836 * After disabling a pipe, we can't wait for vblank in the usual way,
837 * spinning on the vblank interrupt status bit, since we won't actually
838 * see an interrupt when the pipe is disabled.
839 *
840 * On Gen4 and above:
841 * wait for the pipe register state bit to turn off
842 *
843 * Otherwise:
844 * wait for the display line value to settle (it usually
845 * ends up stopping at the start of the next frame).
846 *
847 */
848 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
849 {
850 struct drm_i915_private *dev_priv = dev->dev_private;
851 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
852 pipe);
853
854 if (INTEL_INFO(dev)->gen >= 4) {
855 int reg = PIPECONF(cpu_transcoder);
856
857 /* Wait for the Pipe State to go off */
858 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
859 100))
860 WARN(1, "pipe_off wait timed out\n");
861 } else {
862 /* Wait for the display line to settle */
863 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
864 WARN(1, "pipe_off wait timed out\n");
865 }
866 }
867
868 /*
869 * ibx_digital_port_connected - is the specified port connected?
870 * @dev_priv: i915 private structure
871 * @port: the port to test
872 *
873 * Returns true if @port is connected, false otherwise.
874 */
875 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
876 struct intel_digital_port *port)
877 {
878 u32 bit;
879
880 if (HAS_PCH_IBX(dev_priv->dev)) {
881 switch(port->port) {
882 case PORT_B:
883 bit = SDE_PORTB_HOTPLUG;
884 break;
885 case PORT_C:
886 bit = SDE_PORTC_HOTPLUG;
887 break;
888 case PORT_D:
889 bit = SDE_PORTD_HOTPLUG;
890 break;
891 default:
892 return true;
893 }
894 } else {
895 switch(port->port) {
896 case PORT_B:
897 bit = SDE_PORTB_HOTPLUG_CPT;
898 break;
899 case PORT_C:
900 bit = SDE_PORTC_HOTPLUG_CPT;
901 break;
902 case PORT_D:
903 bit = SDE_PORTD_HOTPLUG_CPT;
904 break;
905 default:
906 return true;
907 }
908 }
909
910 return I915_READ(SDEISR) & bit;
911 }
912
913 static const char *state_string(bool enabled)
914 {
915 return enabled ? "on" : "off";
916 }
917
918 /* Only for pre-ILK configs */
919 void assert_pll(struct drm_i915_private *dev_priv,
920 enum pipe pipe, bool state)
921 {
922 int reg;
923 u32 val;
924 bool cur_state;
925
926 reg = DPLL(pipe);
927 val = I915_READ(reg);
928 cur_state = !!(val & DPLL_VCO_ENABLE);
929 WARN(cur_state != state,
930 "PLL state assertion failure (expected %s, current %s)\n",
931 state_string(state), state_string(cur_state));
932 }
933
934 /* XXX: the dsi pll is shared between MIPI DSI ports */
935 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
936 {
937 u32 val;
938 bool cur_state;
939
940 mutex_lock(&dev_priv->dpio_lock);
941 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
942 mutex_unlock(&dev_priv->dpio_lock);
943
944 cur_state = val & DSI_PLL_VCO_EN;
945 WARN(cur_state != state,
946 "DSI PLL state assertion failure (expected %s, current %s)\n",
947 state_string(state), state_string(cur_state));
948 }
949 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
950 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
951
952 struct intel_shared_dpll *
953 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
954 {
955 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
956
957 if (crtc->config.shared_dpll < 0)
958 return NULL;
959
960 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
961 }
962
963 /* For ILK+ */
964 void assert_shared_dpll(struct drm_i915_private *dev_priv,
965 struct intel_shared_dpll *pll,
966 bool state)
967 {
968 bool cur_state;
969 struct intel_dpll_hw_state hw_state;
970
971 if (HAS_PCH_LPT(dev_priv->dev)) {
972 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
973 return;
974 }
975
976 if (WARN (!pll,
977 "asserting DPLL %s with no DPLL\n", state_string(state)))
978 return;
979
980 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
981 WARN(cur_state != state,
982 "%s assertion failure (expected %s, current %s)\n",
983 pll->name, state_string(state), state_string(cur_state));
984 }
985
986 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
987 enum pipe pipe, bool state)
988 {
989 int reg;
990 u32 val;
991 bool cur_state;
992 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
993 pipe);
994
995 if (HAS_DDI(dev_priv->dev)) {
996 /* DDI does not have a specific FDI_TX register */
997 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
998 val = I915_READ(reg);
999 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1000 } else {
1001 reg = FDI_TX_CTL(pipe);
1002 val = I915_READ(reg);
1003 cur_state = !!(val & FDI_TX_ENABLE);
1004 }
1005 WARN(cur_state != state,
1006 "FDI TX state assertion failure (expected %s, current %s)\n",
1007 state_string(state), state_string(cur_state));
1008 }
1009 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1010 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1011
1012 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1013 enum pipe pipe, bool state)
1014 {
1015 int reg;
1016 u32 val;
1017 bool cur_state;
1018
1019 reg = FDI_RX_CTL(pipe);
1020 val = I915_READ(reg);
1021 cur_state = !!(val & FDI_RX_ENABLE);
1022 WARN(cur_state != state,
1023 "FDI RX state assertion failure (expected %s, current %s)\n",
1024 state_string(state), state_string(cur_state));
1025 }
1026 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1027 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1028
1029 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1030 enum pipe pipe)
1031 {
1032 int reg;
1033 u32 val;
1034
1035 /* ILK FDI PLL is always enabled */
1036 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1037 return;
1038
1039 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1040 if (HAS_DDI(dev_priv->dev))
1041 return;
1042
1043 reg = FDI_TX_CTL(pipe);
1044 val = I915_READ(reg);
1045 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1046 }
1047
1048 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1049 enum pipe pipe, bool state)
1050 {
1051 int reg;
1052 u32 val;
1053 bool cur_state;
1054
1055 reg = FDI_RX_CTL(pipe);
1056 val = I915_READ(reg);
1057 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1058 WARN(cur_state != state,
1059 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1060 state_string(state), state_string(cur_state));
1061 }
1062
1063 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1064 enum pipe pipe)
1065 {
1066 int pp_reg, lvds_reg;
1067 u32 val;
1068 enum pipe panel_pipe = PIPE_A;
1069 bool locked = true;
1070
1071 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1072 pp_reg = PCH_PP_CONTROL;
1073 lvds_reg = PCH_LVDS;
1074 } else {
1075 pp_reg = PP_CONTROL;
1076 lvds_reg = LVDS;
1077 }
1078
1079 val = I915_READ(pp_reg);
1080 if (!(val & PANEL_POWER_ON) ||
1081 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1082 locked = false;
1083
1084 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1085 panel_pipe = PIPE_B;
1086
1087 WARN(panel_pipe == pipe && locked,
1088 "panel assertion failure, pipe %c regs locked\n",
1089 pipe_name(pipe));
1090 }
1091
1092 static void assert_cursor(struct drm_i915_private *dev_priv,
1093 enum pipe pipe, bool state)
1094 {
1095 struct drm_device *dev = dev_priv->dev;
1096 bool cur_state;
1097
1098 if (IS_845G(dev) || IS_I865G(dev))
1099 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1100 else if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev))
1101 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1102 else
1103 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1104
1105 WARN(cur_state != state,
1106 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1107 pipe_name(pipe), state_string(state), state_string(cur_state));
1108 }
1109 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1110 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1111
1112 void assert_pipe(struct drm_i915_private *dev_priv,
1113 enum pipe pipe, bool state)
1114 {
1115 int reg;
1116 u32 val;
1117 bool cur_state;
1118 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1119 pipe);
1120
1121 /* if we need the pipe A quirk it must be always on */
1122 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1123 state = true;
1124
1125 if (!intel_display_power_enabled(dev_priv,
1126 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1127 cur_state = false;
1128 } else {
1129 reg = PIPECONF(cpu_transcoder);
1130 val = I915_READ(reg);
1131 cur_state = !!(val & PIPECONF_ENABLE);
1132 }
1133
1134 WARN(cur_state != state,
1135 "pipe %c assertion failure (expected %s, current %s)\n",
1136 pipe_name(pipe), state_string(state), state_string(cur_state));
1137 }
1138
1139 static void assert_plane(struct drm_i915_private *dev_priv,
1140 enum plane plane, bool state)
1141 {
1142 int reg;
1143 u32 val;
1144 bool cur_state;
1145
1146 reg = DSPCNTR(plane);
1147 val = I915_READ(reg);
1148 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1149 WARN(cur_state != state,
1150 "plane %c assertion failure (expected %s, current %s)\n",
1151 plane_name(plane), state_string(state), state_string(cur_state));
1152 }
1153
1154 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1155 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1156
1157 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1158 enum pipe pipe)
1159 {
1160 struct drm_device *dev = dev_priv->dev;
1161 int reg, i;
1162 u32 val;
1163 int cur_pipe;
1164
1165 /* Primary planes are fixed to pipes on gen4+ */
1166 if (INTEL_INFO(dev)->gen >= 4) {
1167 reg = DSPCNTR(pipe);
1168 val = I915_READ(reg);
1169 WARN(val & DISPLAY_PLANE_ENABLE,
1170 "plane %c assertion failure, should be disabled but not\n",
1171 plane_name(pipe));
1172 return;
1173 }
1174
1175 /* Need to check both planes against the pipe */
1176 for_each_pipe(i) {
1177 reg = DSPCNTR(i);
1178 val = I915_READ(reg);
1179 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1180 DISPPLANE_SEL_PIPE_SHIFT;
1181 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1182 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1183 plane_name(i), pipe_name(pipe));
1184 }
1185 }
1186
1187 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1188 enum pipe pipe)
1189 {
1190 struct drm_device *dev = dev_priv->dev;
1191 int reg, sprite;
1192 u32 val;
1193
1194 if (IS_VALLEYVIEW(dev)) {
1195 for_each_sprite(pipe, sprite) {
1196 reg = SPCNTR(pipe, sprite);
1197 val = I915_READ(reg);
1198 WARN(val & SP_ENABLE,
1199 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1200 sprite_name(pipe, sprite), pipe_name(pipe));
1201 }
1202 } else if (INTEL_INFO(dev)->gen >= 7) {
1203 reg = SPRCTL(pipe);
1204 val = I915_READ(reg);
1205 WARN(val & SPRITE_ENABLE,
1206 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1207 plane_name(pipe), pipe_name(pipe));
1208 } else if (INTEL_INFO(dev)->gen >= 5) {
1209 reg = DVSCNTR(pipe);
1210 val = I915_READ(reg);
1211 WARN(val & DVS_ENABLE,
1212 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1213 plane_name(pipe), pipe_name(pipe));
1214 }
1215 }
1216
1217 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1218 {
1219 u32 val;
1220 bool enabled;
1221
1222 WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1223
1224 val = I915_READ(PCH_DREF_CONTROL);
1225 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1226 DREF_SUPERSPREAD_SOURCE_MASK));
1227 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1228 }
1229
1230 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1231 enum pipe pipe)
1232 {
1233 int reg;
1234 u32 val;
1235 bool enabled;
1236
1237 reg = PCH_TRANSCONF(pipe);
1238 val = I915_READ(reg);
1239 enabled = !!(val & TRANS_ENABLE);
1240 WARN(enabled,
1241 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1242 pipe_name(pipe));
1243 }
1244
1245 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1246 enum pipe pipe, u32 port_sel, u32 val)
1247 {
1248 if ((val & DP_PORT_EN) == 0)
1249 return false;
1250
1251 if (HAS_PCH_CPT(dev_priv->dev)) {
1252 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1253 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1254 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1255 return false;
1256 } else {
1257 if ((val & DP_PIPE_MASK) != (pipe << 30))
1258 return false;
1259 }
1260 return true;
1261 }
1262
1263 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1264 enum pipe pipe, u32 val)
1265 {
1266 if ((val & SDVO_ENABLE) == 0)
1267 return false;
1268
1269 if (HAS_PCH_CPT(dev_priv->dev)) {
1270 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1271 return false;
1272 } else {
1273 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1274 return false;
1275 }
1276 return true;
1277 }
1278
1279 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1280 enum pipe pipe, u32 val)
1281 {
1282 if ((val & LVDS_PORT_EN) == 0)
1283 return false;
1284
1285 if (HAS_PCH_CPT(dev_priv->dev)) {
1286 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1287 return false;
1288 } else {
1289 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1290 return false;
1291 }
1292 return true;
1293 }
1294
1295 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1296 enum pipe pipe, u32 val)
1297 {
1298 if ((val & ADPA_DAC_ENABLE) == 0)
1299 return false;
1300 if (HAS_PCH_CPT(dev_priv->dev)) {
1301 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1302 return false;
1303 } else {
1304 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1305 return false;
1306 }
1307 return true;
1308 }
1309
1310 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1311 enum pipe pipe, int reg, u32 port_sel)
1312 {
1313 u32 val = I915_READ(reg);
1314 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1315 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1316 reg, pipe_name(pipe));
1317
1318 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1319 && (val & DP_PIPEB_SELECT),
1320 "IBX PCH dp port still using transcoder B\n");
1321 }
1322
1323 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1324 enum pipe pipe, int reg)
1325 {
1326 u32 val = I915_READ(reg);
1327 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1328 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1329 reg, pipe_name(pipe));
1330
1331 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1332 && (val & SDVO_PIPE_B_SELECT),
1333 "IBX PCH hdmi port still using transcoder B\n");
1334 }
1335
1336 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1337 enum pipe pipe)
1338 {
1339 int reg;
1340 u32 val;
1341
1342 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1343 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1344 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1345
1346 reg = PCH_ADPA;
1347 val = I915_READ(reg);
1348 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1349 "PCH VGA enabled on transcoder %c, should be disabled\n",
1350 pipe_name(pipe));
1351
1352 reg = PCH_LVDS;
1353 val = I915_READ(reg);
1354 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1355 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1356 pipe_name(pipe));
1357
1358 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1359 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1360 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1361 }
1362
1363 static void intel_init_dpio(struct drm_device *dev)
1364 {
1365 struct drm_i915_private *dev_priv = dev->dev_private;
1366
1367 if (!IS_VALLEYVIEW(dev))
1368 return;
1369
1370 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1371 }
1372
1373 static void intel_reset_dpio(struct drm_device *dev)
1374 {
1375 struct drm_i915_private *dev_priv = dev->dev_private;
1376
1377 if (!IS_VALLEYVIEW(dev))
1378 return;
1379
1380 /*
1381 * Enable the CRI clock source so we can get at the display and the
1382 * reference clock for VGA hotplug / manual detection.
1383 */
1384 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
1385 DPLL_REFA_CLK_ENABLE_VLV |
1386 DPLL_INTEGRATED_CRI_CLK_VLV);
1387
1388 /*
1389 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1390 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
1391 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
1392 * b. The other bits such as sfr settings / modesel may all be set
1393 * to 0.
1394 *
1395 * This should only be done on init and resume from S3 with both
1396 * PLLs disabled, or we risk losing DPIO and PLL synchronization.
1397 */
1398 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1399 }
1400
1401 static void vlv_enable_pll(struct intel_crtc *crtc)
1402 {
1403 struct drm_device *dev = crtc->base.dev;
1404 struct drm_i915_private *dev_priv = dev->dev_private;
1405 int reg = DPLL(crtc->pipe);
1406 u32 dpll = crtc->config.dpll_hw_state.dpll;
1407
1408 assert_pipe_disabled(dev_priv, crtc->pipe);
1409
1410 /* No really, not for ILK+ */
1411 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1412
1413 /* PLL is protected by panel, make sure we can write it */
1414 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1415 assert_panel_unlocked(dev_priv, crtc->pipe);
1416
1417 I915_WRITE(reg, dpll);
1418 POSTING_READ(reg);
1419 udelay(150);
1420
1421 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1422 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1423
1424 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1425 POSTING_READ(DPLL_MD(crtc->pipe));
1426
1427 /* We do this three times for luck */
1428 I915_WRITE(reg, dpll);
1429 POSTING_READ(reg);
1430 udelay(150); /* wait for warmup */
1431 I915_WRITE(reg, dpll);
1432 POSTING_READ(reg);
1433 udelay(150); /* wait for warmup */
1434 I915_WRITE(reg, dpll);
1435 POSTING_READ(reg);
1436 udelay(150); /* wait for warmup */
1437 }
1438
1439 static void i9xx_enable_pll(struct intel_crtc *crtc)
1440 {
1441 struct drm_device *dev = crtc->base.dev;
1442 struct drm_i915_private *dev_priv = dev->dev_private;
1443 int reg = DPLL(crtc->pipe);
1444 u32 dpll = crtc->config.dpll_hw_state.dpll;
1445
1446 assert_pipe_disabled(dev_priv, crtc->pipe);
1447
1448 /* No really, not for ILK+ */
1449 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1450
1451 /* PLL is protected by panel, make sure we can write it */
1452 if (IS_MOBILE(dev) && !IS_I830(dev))
1453 assert_panel_unlocked(dev_priv, crtc->pipe);
1454
1455 I915_WRITE(reg, dpll);
1456
1457 /* Wait for the clocks to stabilize. */
1458 POSTING_READ(reg);
1459 udelay(150);
1460
1461 if (INTEL_INFO(dev)->gen >= 4) {
1462 I915_WRITE(DPLL_MD(crtc->pipe),
1463 crtc->config.dpll_hw_state.dpll_md);
1464 } else {
1465 /* The pixel multiplier can only be updated once the
1466 * DPLL is enabled and the clocks are stable.
1467 *
1468 * So write it again.
1469 */
1470 I915_WRITE(reg, dpll);
1471 }
1472
1473 /* We do this three times for luck */
1474 I915_WRITE(reg, dpll);
1475 POSTING_READ(reg);
1476 udelay(150); /* wait for warmup */
1477 I915_WRITE(reg, dpll);
1478 POSTING_READ(reg);
1479 udelay(150); /* wait for warmup */
1480 I915_WRITE(reg, dpll);
1481 POSTING_READ(reg);
1482 udelay(150); /* wait for warmup */
1483 }
1484
1485 /**
1486 * i9xx_disable_pll - disable a PLL
1487 * @dev_priv: i915 private structure
1488 * @pipe: pipe PLL to disable
1489 *
1490 * Disable the PLL for @pipe, making sure the pipe is off first.
1491 *
1492 * Note! This is for pre-ILK only.
1493 */
1494 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1495 {
1496 /* Don't disable pipe A or pipe A PLLs if needed */
1497 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1498 return;
1499
1500 /* Make sure the pipe isn't still relying on us */
1501 assert_pipe_disabled(dev_priv, pipe);
1502
1503 I915_WRITE(DPLL(pipe), 0);
1504 POSTING_READ(DPLL(pipe));
1505 }
1506
1507 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1508 {
1509 u32 val = 0;
1510
1511 /* Make sure the pipe isn't still relying on us */
1512 assert_pipe_disabled(dev_priv, pipe);
1513
1514 /*
1515 * Leave integrated clock source and reference clock enabled for pipe B.
1516 * The latter is needed for VGA hotplug / manual detection.
1517 */
1518 if (pipe == PIPE_B)
1519 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1520 I915_WRITE(DPLL(pipe), val);
1521 POSTING_READ(DPLL(pipe));
1522 }
1523
1524 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1525 struct intel_digital_port *dport)
1526 {
1527 u32 port_mask;
1528
1529 switch (dport->port) {
1530 case PORT_B:
1531 port_mask = DPLL_PORTB_READY_MASK;
1532 break;
1533 case PORT_C:
1534 port_mask = DPLL_PORTC_READY_MASK;
1535 break;
1536 default:
1537 BUG();
1538 }
1539
1540 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1541 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1542 port_name(dport->port), I915_READ(DPLL(0)));
1543 }
1544
1545 /**
1546 * ironlake_enable_shared_dpll - enable PCH PLL
1547 * @dev_priv: i915 private structure
1548 * @pipe: pipe PLL to enable
1549 *
1550 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1551 * drives the transcoder clock.
1552 */
1553 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1554 {
1555 struct drm_device *dev = crtc->base.dev;
1556 struct drm_i915_private *dev_priv = dev->dev_private;
1557 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1558
1559 /* PCH PLLs only available on ILK, SNB and IVB */
1560 BUG_ON(INTEL_INFO(dev)->gen < 5);
1561 if (WARN_ON(pll == NULL))
1562 return;
1563
1564 if (WARN_ON(pll->refcount == 0))
1565 return;
1566
1567 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1568 pll->name, pll->active, pll->on,
1569 crtc->base.base.id);
1570
1571 if (pll->active++) {
1572 WARN_ON(!pll->on);
1573 assert_shared_dpll_enabled(dev_priv, pll);
1574 return;
1575 }
1576 WARN_ON(pll->on);
1577
1578 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1579 pll->enable(dev_priv, pll);
1580 pll->on = true;
1581 }
1582
1583 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1584 {
1585 struct drm_device *dev = crtc->base.dev;
1586 struct drm_i915_private *dev_priv = dev->dev_private;
1587 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1588
1589 /* PCH only available on ILK+ */
1590 BUG_ON(INTEL_INFO(dev)->gen < 5);
1591 if (WARN_ON(pll == NULL))
1592 return;
1593
1594 if (WARN_ON(pll->refcount == 0))
1595 return;
1596
1597 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1598 pll->name, pll->active, pll->on,
1599 crtc->base.base.id);
1600
1601 if (WARN_ON(pll->active == 0)) {
1602 assert_shared_dpll_disabled(dev_priv, pll);
1603 return;
1604 }
1605
1606 assert_shared_dpll_enabled(dev_priv, pll);
1607 WARN_ON(!pll->on);
1608 if (--pll->active)
1609 return;
1610
1611 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1612 pll->disable(dev_priv, pll);
1613 pll->on = false;
1614 }
1615
1616 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1617 enum pipe pipe)
1618 {
1619 struct drm_device *dev = dev_priv->dev;
1620 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1621 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1622 uint32_t reg, val, pipeconf_val;
1623
1624 /* PCH only available on ILK+ */
1625 BUG_ON(INTEL_INFO(dev)->gen < 5);
1626
1627 /* Make sure PCH DPLL is enabled */
1628 assert_shared_dpll_enabled(dev_priv,
1629 intel_crtc_to_shared_dpll(intel_crtc));
1630
1631 /* FDI must be feeding us bits for PCH ports */
1632 assert_fdi_tx_enabled(dev_priv, pipe);
1633 assert_fdi_rx_enabled(dev_priv, pipe);
1634
1635 if (HAS_PCH_CPT(dev)) {
1636 /* Workaround: Set the timing override bit before enabling the
1637 * pch transcoder. */
1638 reg = TRANS_CHICKEN2(pipe);
1639 val = I915_READ(reg);
1640 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1641 I915_WRITE(reg, val);
1642 }
1643
1644 reg = PCH_TRANSCONF(pipe);
1645 val = I915_READ(reg);
1646 pipeconf_val = I915_READ(PIPECONF(pipe));
1647
1648 if (HAS_PCH_IBX(dev_priv->dev)) {
1649 /*
1650 * make the BPC in transcoder be consistent with
1651 * that in pipeconf reg.
1652 */
1653 val &= ~PIPECONF_BPC_MASK;
1654 val |= pipeconf_val & PIPECONF_BPC_MASK;
1655 }
1656
1657 val &= ~TRANS_INTERLACE_MASK;
1658 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1659 if (HAS_PCH_IBX(dev_priv->dev) &&
1660 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1661 val |= TRANS_LEGACY_INTERLACED_ILK;
1662 else
1663 val |= TRANS_INTERLACED;
1664 else
1665 val |= TRANS_PROGRESSIVE;
1666
1667 I915_WRITE(reg, val | TRANS_ENABLE);
1668 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1669 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1670 }
1671
1672 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1673 enum transcoder cpu_transcoder)
1674 {
1675 u32 val, pipeconf_val;
1676
1677 /* PCH only available on ILK+ */
1678 BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
1679
1680 /* FDI must be feeding us bits for PCH ports */
1681 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1682 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1683
1684 /* Workaround: set timing override bit. */
1685 val = I915_READ(_TRANSA_CHICKEN2);
1686 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1687 I915_WRITE(_TRANSA_CHICKEN2, val);
1688
1689 val = TRANS_ENABLE;
1690 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1691
1692 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1693 PIPECONF_INTERLACED_ILK)
1694 val |= TRANS_INTERLACED;
1695 else
1696 val |= TRANS_PROGRESSIVE;
1697
1698 I915_WRITE(LPT_TRANSCONF, val);
1699 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1700 DRM_ERROR("Failed to enable PCH transcoder\n");
1701 }
1702
1703 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1704 enum pipe pipe)
1705 {
1706 struct drm_device *dev = dev_priv->dev;
1707 uint32_t reg, val;
1708
1709 /* FDI relies on the transcoder */
1710 assert_fdi_tx_disabled(dev_priv, pipe);
1711 assert_fdi_rx_disabled(dev_priv, pipe);
1712
1713 /* Ports must be off as well */
1714 assert_pch_ports_disabled(dev_priv, pipe);
1715
1716 reg = PCH_TRANSCONF(pipe);
1717 val = I915_READ(reg);
1718 val &= ~TRANS_ENABLE;
1719 I915_WRITE(reg, val);
1720 /* wait for PCH transcoder off, transcoder state */
1721 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1722 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1723
1724 if (!HAS_PCH_IBX(dev)) {
1725 /* Workaround: Clear the timing override chicken bit again. */
1726 reg = TRANS_CHICKEN2(pipe);
1727 val = I915_READ(reg);
1728 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1729 I915_WRITE(reg, val);
1730 }
1731 }
1732
1733 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1734 {
1735 u32 val;
1736
1737 val = I915_READ(LPT_TRANSCONF);
1738 val &= ~TRANS_ENABLE;
1739 I915_WRITE(LPT_TRANSCONF, val);
1740 /* wait for PCH transcoder off, transcoder state */
1741 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1742 DRM_ERROR("Failed to disable PCH transcoder\n");
1743
1744 /* Workaround: clear timing override bit. */
1745 val = I915_READ(_TRANSA_CHICKEN2);
1746 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1747 I915_WRITE(_TRANSA_CHICKEN2, val);
1748 }
1749
1750 /**
1751 * intel_enable_pipe - enable a pipe, asserting requirements
1752 * @crtc: crtc responsible for the pipe
1753 *
1754 * Enable @crtc's pipe, making sure that various hardware specific requirements
1755 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1756 */
1757 static void intel_enable_pipe(struct intel_crtc *crtc)
1758 {
1759 struct drm_device *dev = crtc->base.dev;
1760 struct drm_i915_private *dev_priv = dev->dev_private;
1761 enum pipe pipe = crtc->pipe;
1762 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1763 pipe);
1764 enum pipe pch_transcoder;
1765 int reg;
1766 u32 val;
1767
1768 assert_planes_disabled(dev_priv, pipe);
1769 assert_cursor_disabled(dev_priv, pipe);
1770 assert_sprites_disabled(dev_priv, pipe);
1771
1772 if (HAS_PCH_LPT(dev_priv->dev))
1773 pch_transcoder = TRANSCODER_A;
1774 else
1775 pch_transcoder = pipe;
1776
1777 /*
1778 * A pipe without a PLL won't actually be able to drive bits from
1779 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1780 * need the check.
1781 */
1782 if (!HAS_PCH_SPLIT(dev_priv->dev))
1783 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
1784 assert_dsi_pll_enabled(dev_priv);
1785 else
1786 assert_pll_enabled(dev_priv, pipe);
1787 else {
1788 if (crtc->config.has_pch_encoder) {
1789 /* if driving the PCH, we need FDI enabled */
1790 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1791 assert_fdi_tx_pll_enabled(dev_priv,
1792 (enum pipe) cpu_transcoder);
1793 }
1794 /* FIXME: assert CPU port conditions for SNB+ */
1795 }
1796
1797 reg = PIPECONF(cpu_transcoder);
1798 val = I915_READ(reg);
1799 if (val & PIPECONF_ENABLE) {
1800 WARN_ON(!(pipe == PIPE_A &&
1801 dev_priv->quirks & QUIRK_PIPEA_FORCE));
1802 return;
1803 }
1804
1805 I915_WRITE(reg, val | PIPECONF_ENABLE);
1806 POSTING_READ(reg);
1807
1808 /*
1809 * There's no guarantee the pipe will really start running now. It
1810 * depends on the Gen, the output type and the relative order between
1811 * pipe and plane enabling. Avoid waiting on HSW+ since it's not
1812 * necessary.
1813 * TODO: audit the previous gens.
1814 */
1815 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
1816 intel_wait_for_vblank(dev_priv->dev, pipe);
1817 }
1818
1819 /**
1820 * intel_disable_pipe - disable a pipe, asserting requirements
1821 * @dev_priv: i915 private structure
1822 * @pipe: pipe to disable
1823 *
1824 * Disable @pipe, making sure that various hardware specific requirements
1825 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1826 *
1827 * @pipe should be %PIPE_A or %PIPE_B.
1828 *
1829 * Will wait until the pipe has shut down before returning.
1830 */
1831 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1832 enum pipe pipe)
1833 {
1834 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1835 pipe);
1836 int reg;
1837 u32 val;
1838
1839 /*
1840 * Make sure planes won't keep trying to pump pixels to us,
1841 * or we might hang the display.
1842 */
1843 assert_planes_disabled(dev_priv, pipe);
1844 assert_cursor_disabled(dev_priv, pipe);
1845 assert_sprites_disabled(dev_priv, pipe);
1846
1847 /* Don't disable pipe A or pipe A PLLs if needed */
1848 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1849 return;
1850
1851 reg = PIPECONF(cpu_transcoder);
1852 val = I915_READ(reg);
1853 if ((val & PIPECONF_ENABLE) == 0)
1854 return;
1855
1856 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1857 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1858 }
1859
1860 /*
1861 * Plane regs are double buffered, going from enabled->disabled needs a
1862 * trigger in order to latch. The display address reg provides this.
1863 */
1864 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1865 enum plane plane)
1866 {
1867 struct drm_device *dev = dev_priv->dev;
1868 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1869
1870 I915_WRITE(reg, I915_READ(reg));
1871 POSTING_READ(reg);
1872 }
1873
1874 /**
1875 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
1876 * @dev_priv: i915 private structure
1877 * @plane: plane to enable
1878 * @pipe: pipe being fed
1879 *
1880 * Enable @plane on @pipe, making sure that @pipe is running first.
1881 */
1882 static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
1883 enum plane plane, enum pipe pipe)
1884 {
1885 struct intel_crtc *intel_crtc =
1886 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1887 int reg;
1888 u32 val;
1889
1890 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1891 assert_pipe_enabled(dev_priv, pipe);
1892
1893 WARN(intel_crtc->primary_enabled, "Primary plane already enabled\n");
1894
1895 intel_crtc->primary_enabled = true;
1896
1897 reg = DSPCNTR(plane);
1898 val = I915_READ(reg);
1899 if (val & DISPLAY_PLANE_ENABLE)
1900 return;
1901
1902 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1903 intel_flush_primary_plane(dev_priv, plane);
1904 intel_wait_for_vblank(dev_priv->dev, pipe);
1905 }
1906
1907 /**
1908 * intel_disable_primary_hw_plane - disable the primary hardware plane
1909 * @dev_priv: i915 private structure
1910 * @plane: plane to disable
1911 * @pipe: pipe consuming the data
1912 *
1913 * Disable @plane; should be an independent operation.
1914 */
1915 static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv,
1916 enum plane plane, enum pipe pipe)
1917 {
1918 struct intel_crtc *intel_crtc =
1919 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1920 int reg;
1921 u32 val;
1922
1923 WARN(!intel_crtc->primary_enabled, "Primary plane already disabled\n");
1924
1925 intel_crtc->primary_enabled = false;
1926
1927 reg = DSPCNTR(plane);
1928 val = I915_READ(reg);
1929 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1930 return;
1931
1932 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1933 intel_flush_primary_plane(dev_priv, plane);
1934 intel_wait_for_vblank(dev_priv->dev, pipe);
1935 }
1936
1937 static bool need_vtd_wa(struct drm_device *dev)
1938 {
1939 #ifdef CONFIG_INTEL_IOMMU
1940 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1941 return true;
1942 #endif
1943 return false;
1944 }
1945
1946 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
1947 {
1948 int tile_height;
1949
1950 tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
1951 return ALIGN(height, tile_height);
1952 }
1953
1954 int
1955 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1956 struct drm_i915_gem_object *obj,
1957 struct intel_ring_buffer *pipelined)
1958 {
1959 struct drm_i915_private *dev_priv = dev->dev_private;
1960 u32 alignment;
1961 int ret;
1962
1963 switch (obj->tiling_mode) {
1964 case I915_TILING_NONE:
1965 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1966 alignment = 128 * 1024;
1967 else if (INTEL_INFO(dev)->gen >= 4)
1968 alignment = 4 * 1024;
1969 else
1970 alignment = 64 * 1024;
1971 break;
1972 case I915_TILING_X:
1973 /* pin() will align the object as required by fence */
1974 alignment = 0;
1975 break;
1976 case I915_TILING_Y:
1977 WARN(1, "Y tiled bo slipped through, driver bug!\n");
1978 return -EINVAL;
1979 default:
1980 BUG();
1981 }
1982
1983 /* Note that the w/a also requires 64 PTE of padding following the
1984 * bo. We currently fill all unused PTE with the shadow page and so
1985 * we should always have valid PTE following the scanout preventing
1986 * the VT-d warning.
1987 */
1988 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1989 alignment = 256 * 1024;
1990
1991 dev_priv->mm.interruptible = false;
1992 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1993 if (ret)
1994 goto err_interruptible;
1995
1996 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1997 * fence, whereas 965+ only requires a fence if using
1998 * framebuffer compression. For simplicity, we always install
1999 * a fence as the cost is not that onerous.
2000 */
2001 ret = i915_gem_object_get_fence(obj);
2002 if (ret)
2003 goto err_unpin;
2004
2005 i915_gem_object_pin_fence(obj);
2006
2007 dev_priv->mm.interruptible = true;
2008 return 0;
2009
2010 err_unpin:
2011 i915_gem_object_unpin_from_display_plane(obj);
2012 err_interruptible:
2013 dev_priv->mm.interruptible = true;
2014 return ret;
2015 }
2016
2017 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2018 {
2019 i915_gem_object_unpin_fence(obj);
2020 i915_gem_object_unpin_from_display_plane(obj);
2021 }
2022
2023 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2024 * is assumed to be a power-of-two. */
2025 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2026 unsigned int tiling_mode,
2027 unsigned int cpp,
2028 unsigned int pitch)
2029 {
2030 if (tiling_mode != I915_TILING_NONE) {
2031 unsigned int tile_rows, tiles;
2032
2033 tile_rows = *y / 8;
2034 *y %= 8;
2035
2036 tiles = *x / (512/cpp);
2037 *x %= 512/cpp;
2038
2039 return tile_rows * pitch * 8 + tiles * 4096;
2040 } else {
2041 unsigned int offset;
2042
2043 offset = *y * pitch + *x * cpp;
2044 *y = 0;
2045 *x = (offset & 4095) / cpp;
2046 return offset & -4096;
2047 }
2048 }
2049
2050 int intel_format_to_fourcc(int format)
2051 {
2052 switch (format) {
2053 case DISPPLANE_8BPP:
2054 return DRM_FORMAT_C8;
2055 case DISPPLANE_BGRX555:
2056 return DRM_FORMAT_XRGB1555;
2057 case DISPPLANE_BGRX565:
2058 return DRM_FORMAT_RGB565;
2059 default:
2060 case DISPPLANE_BGRX888:
2061 return DRM_FORMAT_XRGB8888;
2062 case DISPPLANE_RGBX888:
2063 return DRM_FORMAT_XBGR8888;
2064 case DISPPLANE_BGRX101010:
2065 return DRM_FORMAT_XRGB2101010;
2066 case DISPPLANE_RGBX101010:
2067 return DRM_FORMAT_XBGR2101010;
2068 }
2069 }
2070
2071 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2072 struct intel_plane_config *plane_config)
2073 {
2074 struct drm_device *dev = crtc->base.dev;
2075 struct drm_i915_gem_object *obj = NULL;
2076 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2077 u32 base = plane_config->base;
2078
2079 if (plane_config->size == 0)
2080 return false;
2081
2082 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2083 plane_config->size);
2084 if (!obj)
2085 return false;
2086
2087 if (plane_config->tiled) {
2088 obj->tiling_mode = I915_TILING_X;
2089 obj->stride = crtc->base.fb->pitches[0];
2090 }
2091
2092 mode_cmd.pixel_format = crtc->base.fb->pixel_format;
2093 mode_cmd.width = crtc->base.fb->width;
2094 mode_cmd.height = crtc->base.fb->height;
2095 mode_cmd.pitches[0] = crtc->base.fb->pitches[0];
2096
2097 mutex_lock(&dev->struct_mutex);
2098
2099 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.fb),
2100 &mode_cmd, obj)) {
2101 DRM_DEBUG_KMS("intel fb init failed\n");
2102 goto out_unref_obj;
2103 }
2104
2105 mutex_unlock(&dev->struct_mutex);
2106
2107 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2108 return true;
2109
2110 out_unref_obj:
2111 drm_gem_object_unreference(&obj->base);
2112 mutex_unlock(&dev->struct_mutex);
2113 return false;
2114 }
2115
2116 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2117 struct intel_plane_config *plane_config)
2118 {
2119 struct drm_device *dev = intel_crtc->base.dev;
2120 struct drm_crtc *c;
2121 struct intel_crtc *i;
2122 struct intel_framebuffer *fb;
2123
2124 if (!intel_crtc->base.fb)
2125 return;
2126
2127 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2128 return;
2129
2130 kfree(intel_crtc->base.fb);
2131 intel_crtc->base.fb = NULL;
2132
2133 /*
2134 * Failed to alloc the obj, check to see if we should share
2135 * an fb with another CRTC instead
2136 */
2137 list_for_each_entry(c, &dev->mode_config.crtc_list, head) {
2138 i = to_intel_crtc(c);
2139
2140 if (c == &intel_crtc->base)
2141 continue;
2142
2143 if (!i->active || !c->fb)
2144 continue;
2145
2146 fb = to_intel_framebuffer(c->fb);
2147 if (i915_gem_obj_ggtt_offset(fb->obj) == plane_config->base) {
2148 drm_framebuffer_reference(c->fb);
2149 intel_crtc->base.fb = c->fb;
2150 break;
2151 }
2152 }
2153 }
2154
2155 static int i9xx_update_primary_plane(struct drm_crtc *crtc,
2156 struct drm_framebuffer *fb,
2157 int x, int y)
2158 {
2159 struct drm_device *dev = crtc->dev;
2160 struct drm_i915_private *dev_priv = dev->dev_private;
2161 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2162 struct intel_framebuffer *intel_fb;
2163 struct drm_i915_gem_object *obj;
2164 int plane = intel_crtc->plane;
2165 unsigned long linear_offset;
2166 u32 dspcntr;
2167 u32 reg;
2168
2169 switch (plane) {
2170 case 0:
2171 case 1:
2172 break;
2173 default:
2174 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2175 return -EINVAL;
2176 }
2177
2178 intel_fb = to_intel_framebuffer(fb);
2179 obj = intel_fb->obj;
2180
2181 reg = DSPCNTR(plane);
2182 dspcntr = I915_READ(reg);
2183 /* Mask out pixel format bits in case we change it */
2184 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2185 switch (fb->pixel_format) {
2186 case DRM_FORMAT_C8:
2187 dspcntr |= DISPPLANE_8BPP;
2188 break;
2189 case DRM_FORMAT_XRGB1555:
2190 case DRM_FORMAT_ARGB1555:
2191 dspcntr |= DISPPLANE_BGRX555;
2192 break;
2193 case DRM_FORMAT_RGB565:
2194 dspcntr |= DISPPLANE_BGRX565;
2195 break;
2196 case DRM_FORMAT_XRGB8888:
2197 case DRM_FORMAT_ARGB8888:
2198 dspcntr |= DISPPLANE_BGRX888;
2199 break;
2200 case DRM_FORMAT_XBGR8888:
2201 case DRM_FORMAT_ABGR8888:
2202 dspcntr |= DISPPLANE_RGBX888;
2203 break;
2204 case DRM_FORMAT_XRGB2101010:
2205 case DRM_FORMAT_ARGB2101010:
2206 dspcntr |= DISPPLANE_BGRX101010;
2207 break;
2208 case DRM_FORMAT_XBGR2101010:
2209 case DRM_FORMAT_ABGR2101010:
2210 dspcntr |= DISPPLANE_RGBX101010;
2211 break;
2212 default:
2213 BUG();
2214 }
2215
2216 if (INTEL_INFO(dev)->gen >= 4) {
2217 if (obj->tiling_mode != I915_TILING_NONE)
2218 dspcntr |= DISPPLANE_TILED;
2219 else
2220 dspcntr &= ~DISPPLANE_TILED;
2221 }
2222
2223 if (IS_G4X(dev))
2224 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2225
2226 I915_WRITE(reg, dspcntr);
2227
2228 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2229
2230 if (INTEL_INFO(dev)->gen >= 4) {
2231 intel_crtc->dspaddr_offset =
2232 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2233 fb->bits_per_pixel / 8,
2234 fb->pitches[0]);
2235 linear_offset -= intel_crtc->dspaddr_offset;
2236 } else {
2237 intel_crtc->dspaddr_offset = linear_offset;
2238 }
2239
2240 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2241 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2242 fb->pitches[0]);
2243 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2244 if (INTEL_INFO(dev)->gen >= 4) {
2245 I915_WRITE(DSPSURF(plane),
2246 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2247 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2248 I915_WRITE(DSPLINOFF(plane), linear_offset);
2249 } else
2250 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2251 POSTING_READ(reg);
2252
2253 return 0;
2254 }
2255
2256 static int ironlake_update_primary_plane(struct drm_crtc *crtc,
2257 struct drm_framebuffer *fb,
2258 int x, int y)
2259 {
2260 struct drm_device *dev = crtc->dev;
2261 struct drm_i915_private *dev_priv = dev->dev_private;
2262 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2263 struct intel_framebuffer *intel_fb;
2264 struct drm_i915_gem_object *obj;
2265 int plane = intel_crtc->plane;
2266 unsigned long linear_offset;
2267 u32 dspcntr;
2268 u32 reg;
2269
2270 switch (plane) {
2271 case 0:
2272 case 1:
2273 case 2:
2274 break;
2275 default:
2276 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2277 return -EINVAL;
2278 }
2279
2280 intel_fb = to_intel_framebuffer(fb);
2281 obj = intel_fb->obj;
2282
2283 reg = DSPCNTR(plane);
2284 dspcntr = I915_READ(reg);
2285 /* Mask out pixel format bits in case we change it */
2286 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2287 switch (fb->pixel_format) {
2288 case DRM_FORMAT_C8:
2289 dspcntr |= DISPPLANE_8BPP;
2290 break;
2291 case DRM_FORMAT_RGB565:
2292 dspcntr |= DISPPLANE_BGRX565;
2293 break;
2294 case DRM_FORMAT_XRGB8888:
2295 case DRM_FORMAT_ARGB8888:
2296 dspcntr |= DISPPLANE_BGRX888;
2297 break;
2298 case DRM_FORMAT_XBGR8888:
2299 case DRM_FORMAT_ABGR8888:
2300 dspcntr |= DISPPLANE_RGBX888;
2301 break;
2302 case DRM_FORMAT_XRGB2101010:
2303 case DRM_FORMAT_ARGB2101010:
2304 dspcntr |= DISPPLANE_BGRX101010;
2305 break;
2306 case DRM_FORMAT_XBGR2101010:
2307 case DRM_FORMAT_ABGR2101010:
2308 dspcntr |= DISPPLANE_RGBX101010;
2309 break;
2310 default:
2311 BUG();
2312 }
2313
2314 if (obj->tiling_mode != I915_TILING_NONE)
2315 dspcntr |= DISPPLANE_TILED;
2316 else
2317 dspcntr &= ~DISPPLANE_TILED;
2318
2319 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2320 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2321 else
2322 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2323
2324 I915_WRITE(reg, dspcntr);
2325
2326 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2327 intel_crtc->dspaddr_offset =
2328 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2329 fb->bits_per_pixel / 8,
2330 fb->pitches[0]);
2331 linear_offset -= intel_crtc->dspaddr_offset;
2332
2333 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2334 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2335 fb->pitches[0]);
2336 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2337 I915_WRITE(DSPSURF(plane),
2338 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2339 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2340 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2341 } else {
2342 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2343 I915_WRITE(DSPLINOFF(plane), linear_offset);
2344 }
2345 POSTING_READ(reg);
2346
2347 return 0;
2348 }
2349
2350 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2351 static int
2352 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2353 int x, int y, enum mode_set_atomic state)
2354 {
2355 struct drm_device *dev = crtc->dev;
2356 struct drm_i915_private *dev_priv = dev->dev_private;
2357
2358 if (dev_priv->display.disable_fbc)
2359 dev_priv->display.disable_fbc(dev);
2360 intel_increase_pllclock(crtc);
2361
2362 return dev_priv->display.update_primary_plane(crtc, fb, x, y);
2363 }
2364
2365 void intel_display_handle_reset(struct drm_device *dev)
2366 {
2367 struct drm_i915_private *dev_priv = dev->dev_private;
2368 struct drm_crtc *crtc;
2369
2370 /*
2371 * Flips in the rings have been nuked by the reset,
2372 * so complete all pending flips so that user space
2373 * will get its events and not get stuck.
2374 *
2375 * Also update the base address of all primary
2376 * planes to the the last fb to make sure we're
2377 * showing the correct fb after a reset.
2378 *
2379 * Need to make two loops over the crtcs so that we
2380 * don't try to grab a crtc mutex before the
2381 * pending_flip_queue really got woken up.
2382 */
2383
2384 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2385 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2386 enum plane plane = intel_crtc->plane;
2387
2388 intel_prepare_page_flip(dev, plane);
2389 intel_finish_page_flip_plane(dev, plane);
2390 }
2391
2392 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2393 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2394
2395 mutex_lock(&crtc->mutex);
2396 /*
2397 * FIXME: Once we have proper support for primary planes (and
2398 * disabling them without disabling the entire crtc) allow again
2399 * a NULL crtc->fb.
2400 */
2401 if (intel_crtc->active && crtc->fb)
2402 dev_priv->display.update_primary_plane(crtc,
2403 crtc->fb,
2404 crtc->x,
2405 crtc->y);
2406 mutex_unlock(&crtc->mutex);
2407 }
2408 }
2409
2410 static int
2411 intel_finish_fb(struct drm_framebuffer *old_fb)
2412 {
2413 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2414 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2415 bool was_interruptible = dev_priv->mm.interruptible;
2416 int ret;
2417
2418 /* Big Hammer, we also need to ensure that any pending
2419 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2420 * current scanout is retired before unpinning the old
2421 * framebuffer.
2422 *
2423 * This should only fail upon a hung GPU, in which case we
2424 * can safely continue.
2425 */
2426 dev_priv->mm.interruptible = false;
2427 ret = i915_gem_object_finish_gpu(obj);
2428 dev_priv->mm.interruptible = was_interruptible;
2429
2430 return ret;
2431 }
2432
2433 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2434 {
2435 struct drm_device *dev = crtc->dev;
2436 struct drm_i915_private *dev_priv = dev->dev_private;
2437 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2438 unsigned long flags;
2439 bool pending;
2440
2441 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2442 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2443 return false;
2444
2445 spin_lock_irqsave(&dev->event_lock, flags);
2446 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2447 spin_unlock_irqrestore(&dev->event_lock, flags);
2448
2449 return pending;
2450 }
2451
2452 static int
2453 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2454 struct drm_framebuffer *fb)
2455 {
2456 struct drm_device *dev = crtc->dev;
2457 struct drm_i915_private *dev_priv = dev->dev_private;
2458 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2459 struct drm_framebuffer *old_fb;
2460 int ret;
2461
2462 if (intel_crtc_has_pending_flip(crtc)) {
2463 DRM_ERROR("pipe is still busy with an old pageflip\n");
2464 return -EBUSY;
2465 }
2466
2467 /* no fb bound */
2468 if (!fb) {
2469 DRM_ERROR("No FB bound\n");
2470 return 0;
2471 }
2472
2473 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2474 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2475 plane_name(intel_crtc->plane),
2476 INTEL_INFO(dev)->num_pipes);
2477 return -EINVAL;
2478 }
2479
2480 mutex_lock(&dev->struct_mutex);
2481 ret = intel_pin_and_fence_fb_obj(dev,
2482 to_intel_framebuffer(fb)->obj,
2483 NULL);
2484 mutex_unlock(&dev->struct_mutex);
2485 if (ret != 0) {
2486 DRM_ERROR("pin & fence failed\n");
2487 return ret;
2488 }
2489
2490 /*
2491 * Update pipe size and adjust fitter if needed: the reason for this is
2492 * that in compute_mode_changes we check the native mode (not the pfit
2493 * mode) to see if we can flip rather than do a full mode set. In the
2494 * fastboot case, we'll flip, but if we don't update the pipesrc and
2495 * pfit state, we'll end up with a big fb scanned out into the wrong
2496 * sized surface.
2497 *
2498 * To fix this properly, we need to hoist the checks up into
2499 * compute_mode_changes (or above), check the actual pfit state and
2500 * whether the platform allows pfit disable with pipe active, and only
2501 * then update the pipesrc and pfit state, even on the flip path.
2502 */
2503 if (i915.fastboot) {
2504 const struct drm_display_mode *adjusted_mode =
2505 &intel_crtc->config.adjusted_mode;
2506
2507 I915_WRITE(PIPESRC(intel_crtc->pipe),
2508 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2509 (adjusted_mode->crtc_vdisplay - 1));
2510 if (!intel_crtc->config.pch_pfit.enabled &&
2511 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2512 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2513 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2514 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2515 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2516 }
2517 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2518 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2519 }
2520
2521 ret = dev_priv->display.update_primary_plane(crtc, fb, x, y);
2522 if (ret) {
2523 mutex_lock(&dev->struct_mutex);
2524 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2525 mutex_unlock(&dev->struct_mutex);
2526 DRM_ERROR("failed to update base address\n");
2527 return ret;
2528 }
2529
2530 old_fb = crtc->fb;
2531 crtc->fb = fb;
2532 crtc->x = x;
2533 crtc->y = y;
2534
2535 if (old_fb) {
2536 if (intel_crtc->active && old_fb != fb)
2537 intel_wait_for_vblank(dev, intel_crtc->pipe);
2538 mutex_lock(&dev->struct_mutex);
2539 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2540 mutex_unlock(&dev->struct_mutex);
2541 }
2542
2543 mutex_lock(&dev->struct_mutex);
2544 intel_update_fbc(dev);
2545 intel_edp_psr_update(dev);
2546 mutex_unlock(&dev->struct_mutex);
2547
2548 return 0;
2549 }
2550
2551 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2552 {
2553 struct drm_device *dev = crtc->dev;
2554 struct drm_i915_private *dev_priv = dev->dev_private;
2555 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2556 int pipe = intel_crtc->pipe;
2557 u32 reg, temp;
2558
2559 /* enable normal train */
2560 reg = FDI_TX_CTL(pipe);
2561 temp = I915_READ(reg);
2562 if (IS_IVYBRIDGE(dev)) {
2563 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2564 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2565 } else {
2566 temp &= ~FDI_LINK_TRAIN_NONE;
2567 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2568 }
2569 I915_WRITE(reg, temp);
2570
2571 reg = FDI_RX_CTL(pipe);
2572 temp = I915_READ(reg);
2573 if (HAS_PCH_CPT(dev)) {
2574 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2575 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2576 } else {
2577 temp &= ~FDI_LINK_TRAIN_NONE;
2578 temp |= FDI_LINK_TRAIN_NONE;
2579 }
2580 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2581
2582 /* wait one idle pattern time */
2583 POSTING_READ(reg);
2584 udelay(1000);
2585
2586 /* IVB wants error correction enabled */
2587 if (IS_IVYBRIDGE(dev))
2588 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2589 FDI_FE_ERRC_ENABLE);
2590 }
2591
2592 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2593 {
2594 return crtc->base.enabled && crtc->active &&
2595 crtc->config.has_pch_encoder;
2596 }
2597
2598 static void ivb_modeset_global_resources(struct drm_device *dev)
2599 {
2600 struct drm_i915_private *dev_priv = dev->dev_private;
2601 struct intel_crtc *pipe_B_crtc =
2602 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2603 struct intel_crtc *pipe_C_crtc =
2604 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2605 uint32_t temp;
2606
2607 /*
2608 * When everything is off disable fdi C so that we could enable fdi B
2609 * with all lanes. Note that we don't care about enabled pipes without
2610 * an enabled pch encoder.
2611 */
2612 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2613 !pipe_has_enabled_pch(pipe_C_crtc)) {
2614 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2615 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2616
2617 temp = I915_READ(SOUTH_CHICKEN1);
2618 temp &= ~FDI_BC_BIFURCATION_SELECT;
2619 DRM_DEBUG_KMS("disabling fdi C rx\n");
2620 I915_WRITE(SOUTH_CHICKEN1, temp);
2621 }
2622 }
2623
2624 /* The FDI link training functions for ILK/Ibexpeak. */
2625 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2626 {
2627 struct drm_device *dev = crtc->dev;
2628 struct drm_i915_private *dev_priv = dev->dev_private;
2629 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2630 int pipe = intel_crtc->pipe;
2631 int plane = intel_crtc->plane;
2632 u32 reg, temp, tries;
2633
2634 /* FDI needs bits from pipe & plane first */
2635 assert_pipe_enabled(dev_priv, pipe);
2636 assert_plane_enabled(dev_priv, plane);
2637
2638 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2639 for train result */
2640 reg = FDI_RX_IMR(pipe);
2641 temp = I915_READ(reg);
2642 temp &= ~FDI_RX_SYMBOL_LOCK;
2643 temp &= ~FDI_RX_BIT_LOCK;
2644 I915_WRITE(reg, temp);
2645 I915_READ(reg);
2646 udelay(150);
2647
2648 /* enable CPU FDI TX and PCH FDI RX */
2649 reg = FDI_TX_CTL(pipe);
2650 temp = I915_READ(reg);
2651 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2652 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2653 temp &= ~FDI_LINK_TRAIN_NONE;
2654 temp |= FDI_LINK_TRAIN_PATTERN_1;
2655 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2656
2657 reg = FDI_RX_CTL(pipe);
2658 temp = I915_READ(reg);
2659 temp &= ~FDI_LINK_TRAIN_NONE;
2660 temp |= FDI_LINK_TRAIN_PATTERN_1;
2661 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2662
2663 POSTING_READ(reg);
2664 udelay(150);
2665
2666 /* Ironlake workaround, enable clock pointer after FDI enable*/
2667 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2668 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2669 FDI_RX_PHASE_SYNC_POINTER_EN);
2670
2671 reg = FDI_RX_IIR(pipe);
2672 for (tries = 0; tries < 5; tries++) {
2673 temp = I915_READ(reg);
2674 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2675
2676 if ((temp & FDI_RX_BIT_LOCK)) {
2677 DRM_DEBUG_KMS("FDI train 1 done.\n");
2678 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2679 break;
2680 }
2681 }
2682 if (tries == 5)
2683 DRM_ERROR("FDI train 1 fail!\n");
2684
2685 /* Train 2 */
2686 reg = FDI_TX_CTL(pipe);
2687 temp = I915_READ(reg);
2688 temp &= ~FDI_LINK_TRAIN_NONE;
2689 temp |= FDI_LINK_TRAIN_PATTERN_2;
2690 I915_WRITE(reg, temp);
2691
2692 reg = FDI_RX_CTL(pipe);
2693 temp = I915_READ(reg);
2694 temp &= ~FDI_LINK_TRAIN_NONE;
2695 temp |= FDI_LINK_TRAIN_PATTERN_2;
2696 I915_WRITE(reg, temp);
2697
2698 POSTING_READ(reg);
2699 udelay(150);
2700
2701 reg = FDI_RX_IIR(pipe);
2702 for (tries = 0; tries < 5; tries++) {
2703 temp = I915_READ(reg);
2704 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2705
2706 if (temp & FDI_RX_SYMBOL_LOCK) {
2707 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2708 DRM_DEBUG_KMS("FDI train 2 done.\n");
2709 break;
2710 }
2711 }
2712 if (tries == 5)
2713 DRM_ERROR("FDI train 2 fail!\n");
2714
2715 DRM_DEBUG_KMS("FDI train done\n");
2716
2717 }
2718
2719 static const int snb_b_fdi_train_param[] = {
2720 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2721 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2722 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2723 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2724 };
2725
2726 /* The FDI link training functions for SNB/Cougarpoint. */
2727 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2728 {
2729 struct drm_device *dev = crtc->dev;
2730 struct drm_i915_private *dev_priv = dev->dev_private;
2731 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2732 int pipe = intel_crtc->pipe;
2733 u32 reg, temp, i, retry;
2734
2735 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2736 for train result */
2737 reg = FDI_RX_IMR(pipe);
2738 temp = I915_READ(reg);
2739 temp &= ~FDI_RX_SYMBOL_LOCK;
2740 temp &= ~FDI_RX_BIT_LOCK;
2741 I915_WRITE(reg, temp);
2742
2743 POSTING_READ(reg);
2744 udelay(150);
2745
2746 /* enable CPU FDI TX and PCH FDI RX */
2747 reg = FDI_TX_CTL(pipe);
2748 temp = I915_READ(reg);
2749 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2750 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2751 temp &= ~FDI_LINK_TRAIN_NONE;
2752 temp |= FDI_LINK_TRAIN_PATTERN_1;
2753 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2754 /* SNB-B */
2755 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2756 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2757
2758 I915_WRITE(FDI_RX_MISC(pipe),
2759 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2760
2761 reg = FDI_RX_CTL(pipe);
2762 temp = I915_READ(reg);
2763 if (HAS_PCH_CPT(dev)) {
2764 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2765 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2766 } else {
2767 temp &= ~FDI_LINK_TRAIN_NONE;
2768 temp |= FDI_LINK_TRAIN_PATTERN_1;
2769 }
2770 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2771
2772 POSTING_READ(reg);
2773 udelay(150);
2774
2775 for (i = 0; i < 4; i++) {
2776 reg = FDI_TX_CTL(pipe);
2777 temp = I915_READ(reg);
2778 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2779 temp |= snb_b_fdi_train_param[i];
2780 I915_WRITE(reg, temp);
2781
2782 POSTING_READ(reg);
2783 udelay(500);
2784
2785 for (retry = 0; retry < 5; retry++) {
2786 reg = FDI_RX_IIR(pipe);
2787 temp = I915_READ(reg);
2788 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2789 if (temp & FDI_RX_BIT_LOCK) {
2790 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2791 DRM_DEBUG_KMS("FDI train 1 done.\n");
2792 break;
2793 }
2794 udelay(50);
2795 }
2796 if (retry < 5)
2797 break;
2798 }
2799 if (i == 4)
2800 DRM_ERROR("FDI train 1 fail!\n");
2801
2802 /* Train 2 */
2803 reg = FDI_TX_CTL(pipe);
2804 temp = I915_READ(reg);
2805 temp &= ~FDI_LINK_TRAIN_NONE;
2806 temp |= FDI_LINK_TRAIN_PATTERN_2;
2807 if (IS_GEN6(dev)) {
2808 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2809 /* SNB-B */
2810 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2811 }
2812 I915_WRITE(reg, temp);
2813
2814 reg = FDI_RX_CTL(pipe);
2815 temp = I915_READ(reg);
2816 if (HAS_PCH_CPT(dev)) {
2817 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2818 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2819 } else {
2820 temp &= ~FDI_LINK_TRAIN_NONE;
2821 temp |= FDI_LINK_TRAIN_PATTERN_2;
2822 }
2823 I915_WRITE(reg, temp);
2824
2825 POSTING_READ(reg);
2826 udelay(150);
2827
2828 for (i = 0; i < 4; i++) {
2829 reg = FDI_TX_CTL(pipe);
2830 temp = I915_READ(reg);
2831 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2832 temp |= snb_b_fdi_train_param[i];
2833 I915_WRITE(reg, temp);
2834
2835 POSTING_READ(reg);
2836 udelay(500);
2837
2838 for (retry = 0; retry < 5; retry++) {
2839 reg = FDI_RX_IIR(pipe);
2840 temp = I915_READ(reg);
2841 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2842 if (temp & FDI_RX_SYMBOL_LOCK) {
2843 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2844 DRM_DEBUG_KMS("FDI train 2 done.\n");
2845 break;
2846 }
2847 udelay(50);
2848 }
2849 if (retry < 5)
2850 break;
2851 }
2852 if (i == 4)
2853 DRM_ERROR("FDI train 2 fail!\n");
2854
2855 DRM_DEBUG_KMS("FDI train done.\n");
2856 }
2857
2858 /* Manual link training for Ivy Bridge A0 parts */
2859 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2860 {
2861 struct drm_device *dev = crtc->dev;
2862 struct drm_i915_private *dev_priv = dev->dev_private;
2863 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2864 int pipe = intel_crtc->pipe;
2865 u32 reg, temp, i, j;
2866
2867 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2868 for train result */
2869 reg = FDI_RX_IMR(pipe);
2870 temp = I915_READ(reg);
2871 temp &= ~FDI_RX_SYMBOL_LOCK;
2872 temp &= ~FDI_RX_BIT_LOCK;
2873 I915_WRITE(reg, temp);
2874
2875 POSTING_READ(reg);
2876 udelay(150);
2877
2878 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2879 I915_READ(FDI_RX_IIR(pipe)));
2880
2881 /* Try each vswing and preemphasis setting twice before moving on */
2882 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2883 /* disable first in case we need to retry */
2884 reg = FDI_TX_CTL(pipe);
2885 temp = I915_READ(reg);
2886 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2887 temp &= ~FDI_TX_ENABLE;
2888 I915_WRITE(reg, temp);
2889
2890 reg = FDI_RX_CTL(pipe);
2891 temp = I915_READ(reg);
2892 temp &= ~FDI_LINK_TRAIN_AUTO;
2893 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2894 temp &= ~FDI_RX_ENABLE;
2895 I915_WRITE(reg, temp);
2896
2897 /* enable CPU FDI TX and PCH FDI RX */
2898 reg = FDI_TX_CTL(pipe);
2899 temp = I915_READ(reg);
2900 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2901 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2902 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2903 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2904 temp |= snb_b_fdi_train_param[j/2];
2905 temp |= FDI_COMPOSITE_SYNC;
2906 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2907
2908 I915_WRITE(FDI_RX_MISC(pipe),
2909 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2910
2911 reg = FDI_RX_CTL(pipe);
2912 temp = I915_READ(reg);
2913 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2914 temp |= FDI_COMPOSITE_SYNC;
2915 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2916
2917 POSTING_READ(reg);
2918 udelay(1); /* should be 0.5us */
2919
2920 for (i = 0; i < 4; i++) {
2921 reg = FDI_RX_IIR(pipe);
2922 temp = I915_READ(reg);
2923 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2924
2925 if (temp & FDI_RX_BIT_LOCK ||
2926 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2927 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2928 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2929 i);
2930 break;
2931 }
2932 udelay(1); /* should be 0.5us */
2933 }
2934 if (i == 4) {
2935 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2936 continue;
2937 }
2938
2939 /* Train 2 */
2940 reg = FDI_TX_CTL(pipe);
2941 temp = I915_READ(reg);
2942 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2943 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2944 I915_WRITE(reg, temp);
2945
2946 reg = FDI_RX_CTL(pipe);
2947 temp = I915_READ(reg);
2948 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2949 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2950 I915_WRITE(reg, temp);
2951
2952 POSTING_READ(reg);
2953 udelay(2); /* should be 1.5us */
2954
2955 for (i = 0; i < 4; i++) {
2956 reg = FDI_RX_IIR(pipe);
2957 temp = I915_READ(reg);
2958 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2959
2960 if (temp & FDI_RX_SYMBOL_LOCK ||
2961 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2962 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2963 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2964 i);
2965 goto train_done;
2966 }
2967 udelay(2); /* should be 1.5us */
2968 }
2969 if (i == 4)
2970 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
2971 }
2972
2973 train_done:
2974 DRM_DEBUG_KMS("FDI train done.\n");
2975 }
2976
2977 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2978 {
2979 struct drm_device *dev = intel_crtc->base.dev;
2980 struct drm_i915_private *dev_priv = dev->dev_private;
2981 int pipe = intel_crtc->pipe;
2982 u32 reg, temp;
2983
2984
2985 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2986 reg = FDI_RX_CTL(pipe);
2987 temp = I915_READ(reg);
2988 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2989 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2990 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2991 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2992
2993 POSTING_READ(reg);
2994 udelay(200);
2995
2996 /* Switch from Rawclk to PCDclk */
2997 temp = I915_READ(reg);
2998 I915_WRITE(reg, temp | FDI_PCDCLK);
2999
3000 POSTING_READ(reg);
3001 udelay(200);
3002
3003 /* Enable CPU FDI TX PLL, always on for Ironlake */
3004 reg = FDI_TX_CTL(pipe);
3005 temp = I915_READ(reg);
3006 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3007 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3008
3009 POSTING_READ(reg);
3010 udelay(100);
3011 }
3012 }
3013
3014 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3015 {
3016 struct drm_device *dev = intel_crtc->base.dev;
3017 struct drm_i915_private *dev_priv = dev->dev_private;
3018 int pipe = intel_crtc->pipe;
3019 u32 reg, temp;
3020
3021 /* Switch from PCDclk to Rawclk */
3022 reg = FDI_RX_CTL(pipe);
3023 temp = I915_READ(reg);
3024 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3025
3026 /* Disable CPU FDI TX PLL */
3027 reg = FDI_TX_CTL(pipe);
3028 temp = I915_READ(reg);
3029 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3030
3031 POSTING_READ(reg);
3032 udelay(100);
3033
3034 reg = FDI_RX_CTL(pipe);
3035 temp = I915_READ(reg);
3036 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3037
3038 /* Wait for the clocks to turn off. */
3039 POSTING_READ(reg);
3040 udelay(100);
3041 }
3042
3043 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3044 {
3045 struct drm_device *dev = crtc->dev;
3046 struct drm_i915_private *dev_priv = dev->dev_private;
3047 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3048 int pipe = intel_crtc->pipe;
3049 u32 reg, temp;
3050
3051 /* disable CPU FDI tx and PCH FDI rx */
3052 reg = FDI_TX_CTL(pipe);
3053 temp = I915_READ(reg);
3054 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3055 POSTING_READ(reg);
3056
3057 reg = FDI_RX_CTL(pipe);
3058 temp = I915_READ(reg);
3059 temp &= ~(0x7 << 16);
3060 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3061 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3062
3063 POSTING_READ(reg);
3064 udelay(100);
3065
3066 /* Ironlake workaround, disable clock pointer after downing FDI */
3067 if (HAS_PCH_IBX(dev)) {
3068 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3069 }
3070
3071 /* still set train pattern 1 */
3072 reg = FDI_TX_CTL(pipe);
3073 temp = I915_READ(reg);
3074 temp &= ~FDI_LINK_TRAIN_NONE;
3075 temp |= FDI_LINK_TRAIN_PATTERN_1;
3076 I915_WRITE(reg, temp);
3077
3078 reg = FDI_RX_CTL(pipe);
3079 temp = I915_READ(reg);
3080 if (HAS_PCH_CPT(dev)) {
3081 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3082 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3083 } else {
3084 temp &= ~FDI_LINK_TRAIN_NONE;
3085 temp |= FDI_LINK_TRAIN_PATTERN_1;
3086 }
3087 /* BPC in FDI rx is consistent with that in PIPECONF */
3088 temp &= ~(0x07 << 16);
3089 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3090 I915_WRITE(reg, temp);
3091
3092 POSTING_READ(reg);
3093 udelay(100);
3094 }
3095
3096 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3097 {
3098 struct intel_crtc *crtc;
3099
3100 /* Note that we don't need to be called with mode_config.lock here
3101 * as our list of CRTC objects is static for the lifetime of the
3102 * device and so cannot disappear as we iterate. Similarly, we can
3103 * happily treat the predicates as racy, atomic checks as userspace
3104 * cannot claim and pin a new fb without at least acquring the
3105 * struct_mutex and so serialising with us.
3106 */
3107 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3108 if (atomic_read(&crtc->unpin_work_count) == 0)
3109 continue;
3110
3111 if (crtc->unpin_work)
3112 intel_wait_for_vblank(dev, crtc->pipe);
3113
3114 return true;
3115 }
3116
3117 return false;
3118 }
3119
3120 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3121 {
3122 struct drm_device *dev = crtc->dev;
3123 struct drm_i915_private *dev_priv = dev->dev_private;
3124
3125 if (crtc->fb == NULL)
3126 return;
3127
3128 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3129
3130 wait_event(dev_priv->pending_flip_queue,
3131 !intel_crtc_has_pending_flip(crtc));
3132
3133 mutex_lock(&dev->struct_mutex);
3134 intel_finish_fb(crtc->fb);
3135 mutex_unlock(&dev->struct_mutex);
3136 }
3137
3138 /* Program iCLKIP clock to the desired frequency */
3139 static void lpt_program_iclkip(struct drm_crtc *crtc)
3140 {
3141 struct drm_device *dev = crtc->dev;
3142 struct drm_i915_private *dev_priv = dev->dev_private;
3143 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3144 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3145 u32 temp;
3146
3147 mutex_lock(&dev_priv->dpio_lock);
3148
3149 /* It is necessary to ungate the pixclk gate prior to programming
3150 * the divisors, and gate it back when it is done.
3151 */
3152 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3153
3154 /* Disable SSCCTL */
3155 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3156 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3157 SBI_SSCCTL_DISABLE,
3158 SBI_ICLK);
3159
3160 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3161 if (clock == 20000) {
3162 auxdiv = 1;
3163 divsel = 0x41;
3164 phaseinc = 0x20;
3165 } else {
3166 /* The iCLK virtual clock root frequency is in MHz,
3167 * but the adjusted_mode->crtc_clock in in KHz. To get the
3168 * divisors, it is necessary to divide one by another, so we
3169 * convert the virtual clock precision to KHz here for higher
3170 * precision.
3171 */
3172 u32 iclk_virtual_root_freq = 172800 * 1000;
3173 u32 iclk_pi_range = 64;
3174 u32 desired_divisor, msb_divisor_value, pi_value;
3175
3176 desired_divisor = (iclk_virtual_root_freq / clock);
3177 msb_divisor_value = desired_divisor / iclk_pi_range;
3178 pi_value = desired_divisor % iclk_pi_range;
3179
3180 auxdiv = 0;
3181 divsel = msb_divisor_value - 2;
3182 phaseinc = pi_value;
3183 }
3184
3185 /* This should not happen with any sane values */
3186 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3187 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3188 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3189 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3190
3191 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3192 clock,
3193 auxdiv,
3194 divsel,
3195 phasedir,
3196 phaseinc);
3197
3198 /* Program SSCDIVINTPHASE6 */
3199 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3200 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3201 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3202 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3203 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3204 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3205 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3206 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3207
3208 /* Program SSCAUXDIV */
3209 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3210 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3211 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3212 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3213
3214 /* Enable modulator and associated divider */
3215 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3216 temp &= ~SBI_SSCCTL_DISABLE;
3217 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3218
3219 /* Wait for initialization time */
3220 udelay(24);
3221
3222 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3223
3224 mutex_unlock(&dev_priv->dpio_lock);
3225 }
3226
3227 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3228 enum pipe pch_transcoder)
3229 {
3230 struct drm_device *dev = crtc->base.dev;
3231 struct drm_i915_private *dev_priv = dev->dev_private;
3232 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3233
3234 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3235 I915_READ(HTOTAL(cpu_transcoder)));
3236 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3237 I915_READ(HBLANK(cpu_transcoder)));
3238 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3239 I915_READ(HSYNC(cpu_transcoder)));
3240
3241 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3242 I915_READ(VTOTAL(cpu_transcoder)));
3243 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3244 I915_READ(VBLANK(cpu_transcoder)));
3245 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3246 I915_READ(VSYNC(cpu_transcoder)));
3247 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3248 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3249 }
3250
3251 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3252 {
3253 struct drm_i915_private *dev_priv = dev->dev_private;
3254 uint32_t temp;
3255
3256 temp = I915_READ(SOUTH_CHICKEN1);
3257 if (temp & FDI_BC_BIFURCATION_SELECT)
3258 return;
3259
3260 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3261 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3262
3263 temp |= FDI_BC_BIFURCATION_SELECT;
3264 DRM_DEBUG_KMS("enabling fdi C rx\n");
3265 I915_WRITE(SOUTH_CHICKEN1, temp);
3266 POSTING_READ(SOUTH_CHICKEN1);
3267 }
3268
3269 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3270 {
3271 struct drm_device *dev = intel_crtc->base.dev;
3272 struct drm_i915_private *dev_priv = dev->dev_private;
3273
3274 switch (intel_crtc->pipe) {
3275 case PIPE_A:
3276 break;
3277 case PIPE_B:
3278 if (intel_crtc->config.fdi_lanes > 2)
3279 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3280 else
3281 cpt_enable_fdi_bc_bifurcation(dev);
3282
3283 break;
3284 case PIPE_C:
3285 cpt_enable_fdi_bc_bifurcation(dev);
3286
3287 break;
3288 default:
3289 BUG();
3290 }
3291 }
3292
3293 /*
3294 * Enable PCH resources required for PCH ports:
3295 * - PCH PLLs
3296 * - FDI training & RX/TX
3297 * - update transcoder timings
3298 * - DP transcoding bits
3299 * - transcoder
3300 */
3301 static void ironlake_pch_enable(struct drm_crtc *crtc)
3302 {
3303 struct drm_device *dev = crtc->dev;
3304 struct drm_i915_private *dev_priv = dev->dev_private;
3305 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3306 int pipe = intel_crtc->pipe;
3307 u32 reg, temp;
3308
3309 assert_pch_transcoder_disabled(dev_priv, pipe);
3310
3311 if (IS_IVYBRIDGE(dev))
3312 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3313
3314 /* Write the TU size bits before fdi link training, so that error
3315 * detection works. */
3316 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3317 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3318
3319 /* For PCH output, training FDI link */
3320 dev_priv->display.fdi_link_train(crtc);
3321
3322 /* We need to program the right clock selection before writing the pixel
3323 * mutliplier into the DPLL. */
3324 if (HAS_PCH_CPT(dev)) {
3325 u32 sel;
3326
3327 temp = I915_READ(PCH_DPLL_SEL);
3328 temp |= TRANS_DPLL_ENABLE(pipe);
3329 sel = TRANS_DPLLB_SEL(pipe);
3330 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3331 temp |= sel;
3332 else
3333 temp &= ~sel;
3334 I915_WRITE(PCH_DPLL_SEL, temp);
3335 }
3336
3337 /* XXX: pch pll's can be enabled any time before we enable the PCH
3338 * transcoder, and we actually should do this to not upset any PCH
3339 * transcoder that already use the clock when we share it.
3340 *
3341 * Note that enable_shared_dpll tries to do the right thing, but
3342 * get_shared_dpll unconditionally resets the pll - we need that to have
3343 * the right LVDS enable sequence. */
3344 ironlake_enable_shared_dpll(intel_crtc);
3345
3346 /* set transcoder timing, panel must allow it */
3347 assert_panel_unlocked(dev_priv, pipe);
3348 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3349
3350 intel_fdi_normal_train(crtc);
3351
3352 /* For PCH DP, enable TRANS_DP_CTL */
3353 if (HAS_PCH_CPT(dev) &&
3354 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3355 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3356 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3357 reg = TRANS_DP_CTL(pipe);
3358 temp = I915_READ(reg);
3359 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3360 TRANS_DP_SYNC_MASK |
3361 TRANS_DP_BPC_MASK);
3362 temp |= (TRANS_DP_OUTPUT_ENABLE |
3363 TRANS_DP_ENH_FRAMING);
3364 temp |= bpc << 9; /* same format but at 11:9 */
3365
3366 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3367 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3368 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3369 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3370
3371 switch (intel_trans_dp_port_sel(crtc)) {
3372 case PCH_DP_B:
3373 temp |= TRANS_DP_PORT_SEL_B;
3374 break;
3375 case PCH_DP_C:
3376 temp |= TRANS_DP_PORT_SEL_C;
3377 break;
3378 case PCH_DP_D:
3379 temp |= TRANS_DP_PORT_SEL_D;
3380 break;
3381 default:
3382 BUG();
3383 }
3384
3385 I915_WRITE(reg, temp);
3386 }
3387
3388 ironlake_enable_pch_transcoder(dev_priv, pipe);
3389 }
3390
3391 static void lpt_pch_enable(struct drm_crtc *crtc)
3392 {
3393 struct drm_device *dev = crtc->dev;
3394 struct drm_i915_private *dev_priv = dev->dev_private;
3395 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3396 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3397
3398 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3399
3400 lpt_program_iclkip(crtc);
3401
3402 /* Set transcoder timing. */
3403 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3404
3405 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3406 }
3407
3408 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3409 {
3410 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3411
3412 if (pll == NULL)
3413 return;
3414
3415 if (pll->refcount == 0) {
3416 WARN(1, "bad %s refcount\n", pll->name);
3417 return;
3418 }
3419
3420 if (--pll->refcount == 0) {
3421 WARN_ON(pll->on);
3422 WARN_ON(pll->active);
3423 }
3424
3425 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3426 }
3427
3428 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3429 {
3430 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3431 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3432 enum intel_dpll_id i;
3433
3434 if (pll) {
3435 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3436 crtc->base.base.id, pll->name);
3437 intel_put_shared_dpll(crtc);
3438 }
3439
3440 if (HAS_PCH_IBX(dev_priv->dev)) {
3441 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3442 i = (enum intel_dpll_id) crtc->pipe;
3443 pll = &dev_priv->shared_dplls[i];
3444
3445 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3446 crtc->base.base.id, pll->name);
3447
3448 goto found;
3449 }
3450
3451 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3452 pll = &dev_priv->shared_dplls[i];
3453
3454 /* Only want to check enabled timings first */
3455 if (pll->refcount == 0)
3456 continue;
3457
3458 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3459 sizeof(pll->hw_state)) == 0) {
3460 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3461 crtc->base.base.id,
3462 pll->name, pll->refcount, pll->active);
3463
3464 goto found;
3465 }
3466 }
3467
3468 /* Ok no matching timings, maybe there's a free one? */
3469 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3470 pll = &dev_priv->shared_dplls[i];
3471 if (pll->refcount == 0) {
3472 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3473 crtc->base.base.id, pll->name);
3474 goto found;
3475 }
3476 }
3477
3478 return NULL;
3479
3480 found:
3481 crtc->config.shared_dpll = i;
3482 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3483 pipe_name(crtc->pipe));
3484
3485 if (pll->active == 0) {
3486 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3487 sizeof(pll->hw_state));
3488
3489 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3490 WARN_ON(pll->on);
3491 assert_shared_dpll_disabled(dev_priv, pll);
3492
3493 pll->mode_set(dev_priv, pll);
3494 }
3495 pll->refcount++;
3496
3497 return pll;
3498 }
3499
3500 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3501 {
3502 struct drm_i915_private *dev_priv = dev->dev_private;
3503 int dslreg = PIPEDSL(pipe);
3504 u32 temp;
3505
3506 temp = I915_READ(dslreg);
3507 udelay(500);
3508 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3509 if (wait_for(I915_READ(dslreg) != temp, 5))
3510 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3511 }
3512 }
3513
3514 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3515 {
3516 struct drm_device *dev = crtc->base.dev;
3517 struct drm_i915_private *dev_priv = dev->dev_private;
3518 int pipe = crtc->pipe;
3519
3520 if (crtc->config.pch_pfit.enabled) {
3521 /* Force use of hard-coded filter coefficients
3522 * as some pre-programmed values are broken,
3523 * e.g. x201.
3524 */
3525 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3526 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3527 PF_PIPE_SEL_IVB(pipe));
3528 else
3529 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3530 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3531 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3532 }
3533 }
3534
3535 static void intel_enable_planes(struct drm_crtc *crtc)
3536 {
3537 struct drm_device *dev = crtc->dev;
3538 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3539 struct intel_plane *intel_plane;
3540
3541 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3542 if (intel_plane->pipe == pipe)
3543 intel_plane_restore(&intel_plane->base);
3544 }
3545
3546 static void intel_disable_planes(struct drm_crtc *crtc)
3547 {
3548 struct drm_device *dev = crtc->dev;
3549 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3550 struct intel_plane *intel_plane;
3551
3552 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3553 if (intel_plane->pipe == pipe)
3554 intel_plane_disable(&intel_plane->base);
3555 }
3556
3557 void hsw_enable_ips(struct intel_crtc *crtc)
3558 {
3559 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3560
3561 if (!crtc->config.ips_enabled)
3562 return;
3563
3564 /* We can only enable IPS after we enable a plane and wait for a vblank.
3565 * We guarantee that the plane is enabled by calling intel_enable_ips
3566 * only after intel_enable_plane. And intel_enable_plane already waits
3567 * for a vblank, so all we need to do here is to enable the IPS bit. */
3568 assert_plane_enabled(dev_priv, crtc->plane);
3569 if (IS_BROADWELL(crtc->base.dev)) {
3570 mutex_lock(&dev_priv->rps.hw_lock);
3571 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3572 mutex_unlock(&dev_priv->rps.hw_lock);
3573 /* Quoting Art Runyan: "its not safe to expect any particular
3574 * value in IPS_CTL bit 31 after enabling IPS through the
3575 * mailbox." Moreover, the mailbox may return a bogus state,
3576 * so we need to just enable it and continue on.
3577 */
3578 } else {
3579 I915_WRITE(IPS_CTL, IPS_ENABLE);
3580 /* The bit only becomes 1 in the next vblank, so this wait here
3581 * is essentially intel_wait_for_vblank. If we don't have this
3582 * and don't wait for vblanks until the end of crtc_enable, then
3583 * the HW state readout code will complain that the expected
3584 * IPS_CTL value is not the one we read. */
3585 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3586 DRM_ERROR("Timed out waiting for IPS enable\n");
3587 }
3588 }
3589
3590 void hsw_disable_ips(struct intel_crtc *crtc)
3591 {
3592 struct drm_device *dev = crtc->base.dev;
3593 struct drm_i915_private *dev_priv = dev->dev_private;
3594
3595 if (!crtc->config.ips_enabled)
3596 return;
3597
3598 assert_plane_enabled(dev_priv, crtc->plane);
3599 if (IS_BROADWELL(crtc->base.dev)) {
3600 mutex_lock(&dev_priv->rps.hw_lock);
3601 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3602 mutex_unlock(&dev_priv->rps.hw_lock);
3603 } else {
3604 I915_WRITE(IPS_CTL, 0);
3605 POSTING_READ(IPS_CTL);
3606 }
3607
3608 /* We need to wait for a vblank before we can disable the plane. */
3609 intel_wait_for_vblank(dev, crtc->pipe);
3610 }
3611
3612 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3613 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3614 {
3615 struct drm_device *dev = crtc->dev;
3616 struct drm_i915_private *dev_priv = dev->dev_private;
3617 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3618 enum pipe pipe = intel_crtc->pipe;
3619 int palreg = PALETTE(pipe);
3620 int i;
3621 bool reenable_ips = false;
3622
3623 /* The clocks have to be on to load the palette. */
3624 if (!crtc->enabled || !intel_crtc->active)
3625 return;
3626
3627 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3628 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3629 assert_dsi_pll_enabled(dev_priv);
3630 else
3631 assert_pll_enabled(dev_priv, pipe);
3632 }
3633
3634 /* use legacy palette for Ironlake */
3635 if (HAS_PCH_SPLIT(dev))
3636 palreg = LGC_PALETTE(pipe);
3637
3638 /* Workaround : Do not read or write the pipe palette/gamma data while
3639 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3640 */
3641 if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3642 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3643 GAMMA_MODE_MODE_SPLIT)) {
3644 hsw_disable_ips(intel_crtc);
3645 reenable_ips = true;
3646 }
3647
3648 for (i = 0; i < 256; i++) {
3649 I915_WRITE(palreg + 4 * i,
3650 (intel_crtc->lut_r[i] << 16) |
3651 (intel_crtc->lut_g[i] << 8) |
3652 intel_crtc->lut_b[i]);
3653 }
3654
3655 if (reenable_ips)
3656 hsw_enable_ips(intel_crtc);
3657 }
3658
3659 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3660 {
3661 struct drm_device *dev = crtc->dev;
3662 struct drm_i915_private *dev_priv = dev->dev_private;
3663 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3664 struct intel_encoder *encoder;
3665 int pipe = intel_crtc->pipe;
3666 int plane = intel_crtc->plane;
3667
3668 WARN_ON(!crtc->enabled);
3669
3670 if (intel_crtc->active)
3671 return;
3672
3673 intel_crtc->active = true;
3674
3675 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3676 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3677
3678 for_each_encoder_on_crtc(dev, crtc, encoder)
3679 if (encoder->pre_enable)
3680 encoder->pre_enable(encoder);
3681
3682 if (intel_crtc->config.has_pch_encoder) {
3683 /* Note: FDI PLL enabling _must_ be done before we enable the
3684 * cpu pipes, hence this is separate from all the other fdi/pch
3685 * enabling. */
3686 ironlake_fdi_pll_enable(intel_crtc);
3687 } else {
3688 assert_fdi_tx_disabled(dev_priv, pipe);
3689 assert_fdi_rx_disabled(dev_priv, pipe);
3690 }
3691
3692 ironlake_pfit_enable(intel_crtc);
3693
3694 /*
3695 * On ILK+ LUT must be loaded before the pipe is running but with
3696 * clocks enabled
3697 */
3698 intel_crtc_load_lut(crtc);
3699
3700 intel_update_watermarks(crtc);
3701 intel_enable_pipe(intel_crtc);
3702 intel_enable_primary_hw_plane(dev_priv, plane, pipe);
3703 intel_enable_planes(crtc);
3704 intel_crtc_update_cursor(crtc, true);
3705
3706 if (intel_crtc->config.has_pch_encoder)
3707 ironlake_pch_enable(crtc);
3708
3709 mutex_lock(&dev->struct_mutex);
3710 intel_update_fbc(dev);
3711 mutex_unlock(&dev->struct_mutex);
3712
3713 for_each_encoder_on_crtc(dev, crtc, encoder)
3714 encoder->enable(encoder);
3715
3716 if (HAS_PCH_CPT(dev))
3717 cpt_verify_modeset(dev, intel_crtc->pipe);
3718
3719 /*
3720 * There seems to be a race in PCH platform hw (at least on some
3721 * outputs) where an enabled pipe still completes any pageflip right
3722 * away (as if the pipe is off) instead of waiting for vblank. As soon
3723 * as the first vblank happend, everything works as expected. Hence just
3724 * wait for one vblank before returning to avoid strange things
3725 * happening.
3726 */
3727 intel_wait_for_vblank(dev, intel_crtc->pipe);
3728 }
3729
3730 /* IPS only exists on ULT machines and is tied to pipe A. */
3731 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3732 {
3733 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3734 }
3735
3736 static void haswell_crtc_enable_planes(struct drm_crtc *crtc)
3737 {
3738 struct drm_device *dev = crtc->dev;
3739 struct drm_i915_private *dev_priv = dev->dev_private;
3740 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3741 int pipe = intel_crtc->pipe;
3742 int plane = intel_crtc->plane;
3743
3744 intel_enable_primary_hw_plane(dev_priv, plane, pipe);
3745 intel_enable_planes(crtc);
3746 intel_crtc_update_cursor(crtc, true);
3747
3748 hsw_enable_ips(intel_crtc);
3749
3750 mutex_lock(&dev->struct_mutex);
3751 intel_update_fbc(dev);
3752 mutex_unlock(&dev->struct_mutex);
3753 }
3754
3755 static void haswell_crtc_disable_planes(struct drm_crtc *crtc)
3756 {
3757 struct drm_device *dev = crtc->dev;
3758 struct drm_i915_private *dev_priv = dev->dev_private;
3759 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3760 int pipe = intel_crtc->pipe;
3761 int plane = intel_crtc->plane;
3762
3763 intel_crtc_wait_for_pending_flips(crtc);
3764 drm_vblank_off(dev, pipe);
3765
3766 /* FBC must be disabled before disabling the plane on HSW. */
3767 if (dev_priv->fbc.plane == plane)
3768 intel_disable_fbc(dev);
3769
3770 hsw_disable_ips(intel_crtc);
3771
3772 intel_crtc_update_cursor(crtc, false);
3773 intel_disable_planes(crtc);
3774 intel_disable_primary_hw_plane(dev_priv, plane, pipe);
3775 }
3776
3777 /*
3778 * This implements the workaround described in the "notes" section of the mode
3779 * set sequence documentation. When going from no pipes or single pipe to
3780 * multiple pipes, and planes are enabled after the pipe, we need to wait at
3781 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3782 */
3783 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3784 {
3785 struct drm_device *dev = crtc->base.dev;
3786 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3787
3788 /* We want to get the other_active_crtc only if there's only 1 other
3789 * active crtc. */
3790 list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
3791 if (!crtc_it->active || crtc_it == crtc)
3792 continue;
3793
3794 if (other_active_crtc)
3795 return;
3796
3797 other_active_crtc = crtc_it;
3798 }
3799 if (!other_active_crtc)
3800 return;
3801
3802 intel_wait_for_vblank(dev, other_active_crtc->pipe);
3803 intel_wait_for_vblank(dev, other_active_crtc->pipe);
3804 }
3805
3806 static void haswell_crtc_enable(struct drm_crtc *crtc)
3807 {
3808 struct drm_device *dev = crtc->dev;
3809 struct drm_i915_private *dev_priv = dev->dev_private;
3810 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3811 struct intel_encoder *encoder;
3812 int pipe = intel_crtc->pipe;
3813
3814 WARN_ON(!crtc->enabled);
3815
3816 if (intel_crtc->active)
3817 return;
3818
3819 intel_crtc->active = true;
3820
3821 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3822 if (intel_crtc->config.has_pch_encoder)
3823 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3824
3825 if (intel_crtc->config.has_pch_encoder)
3826 dev_priv->display.fdi_link_train(crtc);
3827
3828 for_each_encoder_on_crtc(dev, crtc, encoder)
3829 if (encoder->pre_enable)
3830 encoder->pre_enable(encoder);
3831
3832 intel_ddi_enable_pipe_clock(intel_crtc);
3833
3834 ironlake_pfit_enable(intel_crtc);
3835
3836 /*
3837 * On ILK+ LUT must be loaded before the pipe is running but with
3838 * clocks enabled
3839 */
3840 intel_crtc_load_lut(crtc);
3841
3842 intel_ddi_set_pipe_settings(crtc);
3843 intel_ddi_enable_transcoder_func(crtc);
3844
3845 intel_update_watermarks(crtc);
3846 intel_enable_pipe(intel_crtc);
3847
3848 if (intel_crtc->config.has_pch_encoder)
3849 lpt_pch_enable(crtc);
3850
3851 for_each_encoder_on_crtc(dev, crtc, encoder) {
3852 encoder->enable(encoder);
3853 intel_opregion_notify_encoder(encoder, true);
3854 }
3855
3856 /* If we change the relative order between pipe/planes enabling, we need
3857 * to change the workaround. */
3858 haswell_mode_set_planes_workaround(intel_crtc);
3859 haswell_crtc_enable_planes(crtc);
3860 }
3861
3862 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3863 {
3864 struct drm_device *dev = crtc->base.dev;
3865 struct drm_i915_private *dev_priv = dev->dev_private;
3866 int pipe = crtc->pipe;
3867
3868 /* To avoid upsetting the power well on haswell only disable the pfit if
3869 * it's in use. The hw state code will make sure we get this right. */
3870 if (crtc->config.pch_pfit.enabled) {
3871 I915_WRITE(PF_CTL(pipe), 0);
3872 I915_WRITE(PF_WIN_POS(pipe), 0);
3873 I915_WRITE(PF_WIN_SZ(pipe), 0);
3874 }
3875 }
3876
3877 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3878 {
3879 struct drm_device *dev = crtc->dev;
3880 struct drm_i915_private *dev_priv = dev->dev_private;
3881 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3882 struct intel_encoder *encoder;
3883 int pipe = intel_crtc->pipe;
3884 int plane = intel_crtc->plane;
3885 u32 reg, temp;
3886
3887
3888 if (!intel_crtc->active)
3889 return;
3890
3891 for_each_encoder_on_crtc(dev, crtc, encoder)
3892 encoder->disable(encoder);
3893
3894 intel_crtc_wait_for_pending_flips(crtc);
3895 drm_vblank_off(dev, pipe);
3896
3897 if (dev_priv->fbc.plane == plane)
3898 intel_disable_fbc(dev);
3899
3900 intel_crtc_update_cursor(crtc, false);
3901 intel_disable_planes(crtc);
3902 intel_disable_primary_hw_plane(dev_priv, plane, pipe);
3903
3904 if (intel_crtc->config.has_pch_encoder)
3905 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3906
3907 intel_disable_pipe(dev_priv, pipe);
3908
3909 ironlake_pfit_disable(intel_crtc);
3910
3911 for_each_encoder_on_crtc(dev, crtc, encoder)
3912 if (encoder->post_disable)
3913 encoder->post_disable(encoder);
3914
3915 if (intel_crtc->config.has_pch_encoder) {
3916 ironlake_fdi_disable(crtc);
3917
3918 ironlake_disable_pch_transcoder(dev_priv, pipe);
3919 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3920
3921 if (HAS_PCH_CPT(dev)) {
3922 /* disable TRANS_DP_CTL */
3923 reg = TRANS_DP_CTL(pipe);
3924 temp = I915_READ(reg);
3925 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3926 TRANS_DP_PORT_SEL_MASK);
3927 temp |= TRANS_DP_PORT_SEL_NONE;
3928 I915_WRITE(reg, temp);
3929
3930 /* disable DPLL_SEL */
3931 temp = I915_READ(PCH_DPLL_SEL);
3932 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3933 I915_WRITE(PCH_DPLL_SEL, temp);
3934 }
3935
3936 /* disable PCH DPLL */
3937 intel_disable_shared_dpll(intel_crtc);
3938
3939 ironlake_fdi_pll_disable(intel_crtc);
3940 }
3941
3942 intel_crtc->active = false;
3943 intel_update_watermarks(crtc);
3944
3945 mutex_lock(&dev->struct_mutex);
3946 intel_update_fbc(dev);
3947 mutex_unlock(&dev->struct_mutex);
3948 }
3949
3950 static void haswell_crtc_disable(struct drm_crtc *crtc)
3951 {
3952 struct drm_device *dev = crtc->dev;
3953 struct drm_i915_private *dev_priv = dev->dev_private;
3954 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3955 struct intel_encoder *encoder;
3956 int pipe = intel_crtc->pipe;
3957 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3958
3959 if (!intel_crtc->active)
3960 return;
3961
3962 haswell_crtc_disable_planes(crtc);
3963
3964 for_each_encoder_on_crtc(dev, crtc, encoder) {
3965 intel_opregion_notify_encoder(encoder, false);
3966 encoder->disable(encoder);
3967 }
3968
3969 if (intel_crtc->config.has_pch_encoder)
3970 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3971 intel_disable_pipe(dev_priv, pipe);
3972
3973 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3974
3975 ironlake_pfit_disable(intel_crtc);
3976
3977 intel_ddi_disable_pipe_clock(intel_crtc);
3978
3979 for_each_encoder_on_crtc(dev, crtc, encoder)
3980 if (encoder->post_disable)
3981 encoder->post_disable(encoder);
3982
3983 if (intel_crtc->config.has_pch_encoder) {
3984 lpt_disable_pch_transcoder(dev_priv);
3985 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3986 intel_ddi_fdi_disable(crtc);
3987 }
3988
3989 intel_crtc->active = false;
3990 intel_update_watermarks(crtc);
3991
3992 mutex_lock(&dev->struct_mutex);
3993 intel_update_fbc(dev);
3994 mutex_unlock(&dev->struct_mutex);
3995 }
3996
3997 static void ironlake_crtc_off(struct drm_crtc *crtc)
3998 {
3999 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4000 intel_put_shared_dpll(intel_crtc);
4001 }
4002
4003 static void haswell_crtc_off(struct drm_crtc *crtc)
4004 {
4005 intel_ddi_put_crtc_pll(crtc);
4006 }
4007
4008 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4009 {
4010 if (!enable && intel_crtc->overlay) {
4011 struct drm_device *dev = intel_crtc->base.dev;
4012 struct drm_i915_private *dev_priv = dev->dev_private;
4013
4014 mutex_lock(&dev->struct_mutex);
4015 dev_priv->mm.interruptible = false;
4016 (void) intel_overlay_switch_off(intel_crtc->overlay);
4017 dev_priv->mm.interruptible = true;
4018 mutex_unlock(&dev->struct_mutex);
4019 }
4020
4021 /* Let userspace switch the overlay on again. In most cases userspace
4022 * has to recompute where to put it anyway.
4023 */
4024 }
4025
4026 /**
4027 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
4028 * cursor plane briefly if not already running after enabling the display
4029 * plane.
4030 * This workaround avoids occasional blank screens when self refresh is
4031 * enabled.
4032 */
4033 static void
4034 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
4035 {
4036 u32 cntl = I915_READ(CURCNTR(pipe));
4037
4038 if ((cntl & CURSOR_MODE) == 0) {
4039 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
4040
4041 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
4042 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
4043 intel_wait_for_vblank(dev_priv->dev, pipe);
4044 I915_WRITE(CURCNTR(pipe), cntl);
4045 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
4046 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
4047 }
4048 }
4049
4050 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4051 {
4052 struct drm_device *dev = crtc->base.dev;
4053 struct drm_i915_private *dev_priv = dev->dev_private;
4054 struct intel_crtc_config *pipe_config = &crtc->config;
4055
4056 if (!crtc->config.gmch_pfit.control)
4057 return;
4058
4059 /*
4060 * The panel fitter should only be adjusted whilst the pipe is disabled,
4061 * according to register description and PRM.
4062 */
4063 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4064 assert_pipe_disabled(dev_priv, crtc->pipe);
4065
4066 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4067 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4068
4069 /* Border color in case we don't scale up to the full screen. Black by
4070 * default, change to something else for debugging. */
4071 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4072 }
4073
4074 #define for_each_power_domain(domain, mask) \
4075 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4076 if ((1 << (domain)) & (mask))
4077
4078 enum intel_display_power_domain
4079 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4080 {
4081 struct drm_device *dev = intel_encoder->base.dev;
4082 struct intel_digital_port *intel_dig_port;
4083
4084 switch (intel_encoder->type) {
4085 case INTEL_OUTPUT_UNKNOWN:
4086 /* Only DDI platforms should ever use this output type */
4087 WARN_ON_ONCE(!HAS_DDI(dev));
4088 case INTEL_OUTPUT_DISPLAYPORT:
4089 case INTEL_OUTPUT_HDMI:
4090 case INTEL_OUTPUT_EDP:
4091 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4092 switch (intel_dig_port->port) {
4093 case PORT_A:
4094 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4095 case PORT_B:
4096 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4097 case PORT_C:
4098 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4099 case PORT_D:
4100 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4101 default:
4102 WARN_ON_ONCE(1);
4103 return POWER_DOMAIN_PORT_OTHER;
4104 }
4105 case INTEL_OUTPUT_ANALOG:
4106 return POWER_DOMAIN_PORT_CRT;
4107 case INTEL_OUTPUT_DSI:
4108 return POWER_DOMAIN_PORT_DSI;
4109 default:
4110 return POWER_DOMAIN_PORT_OTHER;
4111 }
4112 }
4113
4114 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4115 {
4116 struct drm_device *dev = crtc->dev;
4117 struct intel_encoder *intel_encoder;
4118 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4119 enum pipe pipe = intel_crtc->pipe;
4120 bool pfit_enabled = intel_crtc->config.pch_pfit.enabled;
4121 unsigned long mask;
4122 enum transcoder transcoder;
4123
4124 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4125
4126 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4127 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4128 if (pfit_enabled)
4129 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4130
4131 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4132 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4133
4134 return mask;
4135 }
4136
4137 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4138 bool enable)
4139 {
4140 if (dev_priv->power_domains.init_power_on == enable)
4141 return;
4142
4143 if (enable)
4144 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4145 else
4146 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4147
4148 dev_priv->power_domains.init_power_on = enable;
4149 }
4150
4151 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4152 {
4153 struct drm_i915_private *dev_priv = dev->dev_private;
4154 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4155 struct intel_crtc *crtc;
4156
4157 /*
4158 * First get all needed power domains, then put all unneeded, to avoid
4159 * any unnecessary toggling of the power wells.
4160 */
4161 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
4162 enum intel_display_power_domain domain;
4163
4164 if (!crtc->base.enabled)
4165 continue;
4166
4167 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4168
4169 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4170 intel_display_power_get(dev_priv, domain);
4171 }
4172
4173 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
4174 enum intel_display_power_domain domain;
4175
4176 for_each_power_domain(domain, crtc->enabled_power_domains)
4177 intel_display_power_put(dev_priv, domain);
4178
4179 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4180 }
4181
4182 intel_display_set_init_power(dev_priv, false);
4183 }
4184
4185 int valleyview_get_vco(struct drm_i915_private *dev_priv)
4186 {
4187 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4188
4189 /* Obtain SKU information */
4190 mutex_lock(&dev_priv->dpio_lock);
4191 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4192 CCK_FUSE_HPLL_FREQ_MASK;
4193 mutex_unlock(&dev_priv->dpio_lock);
4194
4195 return vco_freq[hpll_freq];
4196 }
4197
4198 /* Adjust CDclk dividers to allow high res or save power if possible */
4199 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4200 {
4201 struct drm_i915_private *dev_priv = dev->dev_private;
4202 u32 val, cmd;
4203
4204 WARN_ON(valleyview_cur_cdclk(dev_priv) != dev_priv->vlv_cdclk_freq);
4205 dev_priv->vlv_cdclk_freq = cdclk;
4206
4207 if (cdclk >= 320) /* jump to highest voltage for 400MHz too */
4208 cmd = 2;
4209 else if (cdclk == 266)
4210 cmd = 1;
4211 else
4212 cmd = 0;
4213
4214 mutex_lock(&dev_priv->rps.hw_lock);
4215 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4216 val &= ~DSPFREQGUAR_MASK;
4217 val |= (cmd << DSPFREQGUAR_SHIFT);
4218 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4219 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4220 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4221 50)) {
4222 DRM_ERROR("timed out waiting for CDclk change\n");
4223 }
4224 mutex_unlock(&dev_priv->rps.hw_lock);
4225
4226 if (cdclk == 400) {
4227 u32 divider, vco;
4228
4229 vco = valleyview_get_vco(dev_priv);
4230 divider = ((vco << 1) / cdclk) - 1;
4231
4232 mutex_lock(&dev_priv->dpio_lock);
4233 /* adjust cdclk divider */
4234 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4235 val &= ~0xf;
4236 val |= divider;
4237 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4238 mutex_unlock(&dev_priv->dpio_lock);
4239 }
4240
4241 mutex_lock(&dev_priv->dpio_lock);
4242 /* adjust self-refresh exit latency value */
4243 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4244 val &= ~0x7f;
4245
4246 /*
4247 * For high bandwidth configs, we set a higher latency in the bunit
4248 * so that the core display fetch happens in time to avoid underruns.
4249 */
4250 if (cdclk == 400)
4251 val |= 4500 / 250; /* 4.5 usec */
4252 else
4253 val |= 3000 / 250; /* 3.0 usec */
4254 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4255 mutex_unlock(&dev_priv->dpio_lock);
4256
4257 /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
4258 intel_i2c_reset(dev);
4259 }
4260
4261 int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
4262 {
4263 int cur_cdclk, vco;
4264 int divider;
4265
4266 vco = valleyview_get_vco(dev_priv);
4267
4268 mutex_lock(&dev_priv->dpio_lock);
4269 divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4270 mutex_unlock(&dev_priv->dpio_lock);
4271
4272 divider &= 0xf;
4273
4274 cur_cdclk = (vco << 1) / (divider + 1);
4275
4276 return cur_cdclk;
4277 }
4278
4279 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4280 int max_pixclk)
4281 {
4282 /*
4283 * Really only a few cases to deal with, as only 4 CDclks are supported:
4284 * 200MHz
4285 * 267MHz
4286 * 320MHz
4287 * 400MHz
4288 * So we check to see whether we're above 90% of the lower bin and
4289 * adjust if needed.
4290 */
4291 if (max_pixclk > 288000) {
4292 return 400;
4293 } else if (max_pixclk > 240000) {
4294 return 320;
4295 } else
4296 return 266;
4297 /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4298 }
4299
4300 /* compute the max pixel clock for new configuration */
4301 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4302 {
4303 struct drm_device *dev = dev_priv->dev;
4304 struct intel_crtc *intel_crtc;
4305 int max_pixclk = 0;
4306
4307 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4308 base.head) {
4309 if (intel_crtc->new_enabled)
4310 max_pixclk = max(max_pixclk,
4311 intel_crtc->new_config->adjusted_mode.crtc_clock);
4312 }
4313
4314 return max_pixclk;
4315 }
4316
4317 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4318 unsigned *prepare_pipes)
4319 {
4320 struct drm_i915_private *dev_priv = dev->dev_private;
4321 struct intel_crtc *intel_crtc;
4322 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4323
4324 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4325 dev_priv->vlv_cdclk_freq)
4326 return;
4327
4328 /* disable/enable all currently active pipes while we change cdclk */
4329 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4330 base.head)
4331 if (intel_crtc->base.enabled)
4332 *prepare_pipes |= (1 << intel_crtc->pipe);
4333 }
4334
4335 static void valleyview_modeset_global_resources(struct drm_device *dev)
4336 {
4337 struct drm_i915_private *dev_priv = dev->dev_private;
4338 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4339 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4340
4341 if (req_cdclk != dev_priv->vlv_cdclk_freq)
4342 valleyview_set_cdclk(dev, req_cdclk);
4343 modeset_update_crtc_power_domains(dev);
4344 }
4345
4346 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4347 {
4348 struct drm_device *dev = crtc->dev;
4349 struct drm_i915_private *dev_priv = dev->dev_private;
4350 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4351 struct intel_encoder *encoder;
4352 int pipe = intel_crtc->pipe;
4353 int plane = intel_crtc->plane;
4354 bool is_dsi;
4355
4356 WARN_ON(!crtc->enabled);
4357
4358 if (intel_crtc->active)
4359 return;
4360
4361 intel_crtc->active = true;
4362
4363 for_each_encoder_on_crtc(dev, crtc, encoder)
4364 if (encoder->pre_pll_enable)
4365 encoder->pre_pll_enable(encoder);
4366
4367 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4368
4369 if (!is_dsi)
4370 vlv_enable_pll(intel_crtc);
4371
4372 for_each_encoder_on_crtc(dev, crtc, encoder)
4373 if (encoder->pre_enable)
4374 encoder->pre_enable(encoder);
4375
4376 i9xx_pfit_enable(intel_crtc);
4377
4378 intel_crtc_load_lut(crtc);
4379
4380 intel_update_watermarks(crtc);
4381 intel_enable_pipe(intel_crtc);
4382 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4383 intel_enable_primary_hw_plane(dev_priv, plane, pipe);
4384 intel_enable_planes(crtc);
4385 intel_crtc_update_cursor(crtc, true);
4386
4387 intel_update_fbc(dev);
4388
4389 for_each_encoder_on_crtc(dev, crtc, encoder)
4390 encoder->enable(encoder);
4391 }
4392
4393 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4394 {
4395 struct drm_device *dev = crtc->dev;
4396 struct drm_i915_private *dev_priv = dev->dev_private;
4397 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4398 struct intel_encoder *encoder;
4399 int pipe = intel_crtc->pipe;
4400 int plane = intel_crtc->plane;
4401
4402 WARN_ON(!crtc->enabled);
4403
4404 if (intel_crtc->active)
4405 return;
4406
4407 intel_crtc->active = true;
4408
4409 for_each_encoder_on_crtc(dev, crtc, encoder)
4410 if (encoder->pre_enable)
4411 encoder->pre_enable(encoder);
4412
4413 i9xx_enable_pll(intel_crtc);
4414
4415 i9xx_pfit_enable(intel_crtc);
4416
4417 intel_crtc_load_lut(crtc);
4418
4419 intel_update_watermarks(crtc);
4420 intel_enable_pipe(intel_crtc);
4421 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4422 intel_enable_primary_hw_plane(dev_priv, plane, pipe);
4423 intel_enable_planes(crtc);
4424 /* The fixup needs to happen before cursor is enabled */
4425 if (IS_G4X(dev))
4426 g4x_fixup_plane(dev_priv, pipe);
4427 intel_crtc_update_cursor(crtc, true);
4428
4429 /* Give the overlay scaler a chance to enable if it's on this pipe */
4430 intel_crtc_dpms_overlay(intel_crtc, true);
4431
4432 intel_update_fbc(dev);
4433
4434 for_each_encoder_on_crtc(dev, crtc, encoder)
4435 encoder->enable(encoder);
4436 }
4437
4438 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4439 {
4440 struct drm_device *dev = crtc->base.dev;
4441 struct drm_i915_private *dev_priv = dev->dev_private;
4442
4443 if (!crtc->config.gmch_pfit.control)
4444 return;
4445
4446 assert_pipe_disabled(dev_priv, crtc->pipe);
4447
4448 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4449 I915_READ(PFIT_CONTROL));
4450 I915_WRITE(PFIT_CONTROL, 0);
4451 }
4452
4453 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4454 {
4455 struct drm_device *dev = crtc->dev;
4456 struct drm_i915_private *dev_priv = dev->dev_private;
4457 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4458 struct intel_encoder *encoder;
4459 int pipe = intel_crtc->pipe;
4460 int plane = intel_crtc->plane;
4461
4462 if (!intel_crtc->active)
4463 return;
4464
4465 for_each_encoder_on_crtc(dev, crtc, encoder)
4466 encoder->disable(encoder);
4467
4468 /* Give the overlay scaler a chance to disable if it's on this pipe */
4469 intel_crtc_wait_for_pending_flips(crtc);
4470 drm_vblank_off(dev, pipe);
4471
4472 if (dev_priv->fbc.plane == plane)
4473 intel_disable_fbc(dev);
4474
4475 intel_crtc_dpms_overlay(intel_crtc, false);
4476 intel_crtc_update_cursor(crtc, false);
4477 intel_disable_planes(crtc);
4478 intel_disable_primary_hw_plane(dev_priv, plane, pipe);
4479
4480 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4481 intel_disable_pipe(dev_priv, pipe);
4482
4483 i9xx_pfit_disable(intel_crtc);
4484
4485 for_each_encoder_on_crtc(dev, crtc, encoder)
4486 if (encoder->post_disable)
4487 encoder->post_disable(encoder);
4488
4489 if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
4490 vlv_disable_pll(dev_priv, pipe);
4491 else if (!IS_VALLEYVIEW(dev))
4492 i9xx_disable_pll(dev_priv, pipe);
4493
4494 intel_crtc->active = false;
4495 intel_update_watermarks(crtc);
4496
4497 intel_update_fbc(dev);
4498 }
4499
4500 static void i9xx_crtc_off(struct drm_crtc *crtc)
4501 {
4502 }
4503
4504 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4505 bool enabled)
4506 {
4507 struct drm_device *dev = crtc->dev;
4508 struct drm_i915_master_private *master_priv;
4509 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4510 int pipe = intel_crtc->pipe;
4511
4512 if (!dev->primary->master)
4513 return;
4514
4515 master_priv = dev->primary->master->driver_priv;
4516 if (!master_priv->sarea_priv)
4517 return;
4518
4519 switch (pipe) {
4520 case 0:
4521 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4522 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4523 break;
4524 case 1:
4525 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4526 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4527 break;
4528 default:
4529 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4530 break;
4531 }
4532 }
4533
4534 /**
4535 * Sets the power management mode of the pipe and plane.
4536 */
4537 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4538 {
4539 struct drm_device *dev = crtc->dev;
4540 struct drm_i915_private *dev_priv = dev->dev_private;
4541 struct intel_encoder *intel_encoder;
4542 bool enable = false;
4543
4544 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4545 enable |= intel_encoder->connectors_active;
4546
4547 if (enable)
4548 dev_priv->display.crtc_enable(crtc);
4549 else
4550 dev_priv->display.crtc_disable(crtc);
4551
4552 intel_crtc_update_sarea(crtc, enable);
4553 }
4554
4555 static void intel_crtc_disable(struct drm_crtc *crtc)
4556 {
4557 struct drm_device *dev = crtc->dev;
4558 struct drm_connector *connector;
4559 struct drm_i915_private *dev_priv = dev->dev_private;
4560 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4561
4562 /* crtc should still be enabled when we disable it. */
4563 WARN_ON(!crtc->enabled);
4564
4565 dev_priv->display.crtc_disable(crtc);
4566 intel_crtc->eld_vld = false;
4567 intel_crtc_update_sarea(crtc, false);
4568 dev_priv->display.off(crtc);
4569
4570 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4571 assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4572 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4573
4574 if (crtc->fb) {
4575 mutex_lock(&dev->struct_mutex);
4576 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
4577 mutex_unlock(&dev->struct_mutex);
4578 crtc->fb = NULL;
4579 }
4580
4581 /* Update computed state. */
4582 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4583 if (!connector->encoder || !connector->encoder->crtc)
4584 continue;
4585
4586 if (connector->encoder->crtc != crtc)
4587 continue;
4588
4589 connector->dpms = DRM_MODE_DPMS_OFF;
4590 to_intel_encoder(connector->encoder)->connectors_active = false;
4591 }
4592 }
4593
4594 void intel_encoder_destroy(struct drm_encoder *encoder)
4595 {
4596 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4597
4598 drm_encoder_cleanup(encoder);
4599 kfree(intel_encoder);
4600 }
4601
4602 /* Simple dpms helper for encoders with just one connector, no cloning and only
4603 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4604 * state of the entire output pipe. */
4605 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4606 {
4607 if (mode == DRM_MODE_DPMS_ON) {
4608 encoder->connectors_active = true;
4609
4610 intel_crtc_update_dpms(encoder->base.crtc);
4611 } else {
4612 encoder->connectors_active = false;
4613
4614 intel_crtc_update_dpms(encoder->base.crtc);
4615 }
4616 }
4617
4618 /* Cross check the actual hw state with our own modeset state tracking (and it's
4619 * internal consistency). */
4620 static void intel_connector_check_state(struct intel_connector *connector)
4621 {
4622 if (connector->get_hw_state(connector)) {
4623 struct intel_encoder *encoder = connector->encoder;
4624 struct drm_crtc *crtc;
4625 bool encoder_enabled;
4626 enum pipe pipe;
4627
4628 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4629 connector->base.base.id,
4630 drm_get_connector_name(&connector->base));
4631
4632 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4633 "wrong connector dpms state\n");
4634 WARN(connector->base.encoder != &encoder->base,
4635 "active connector not linked to encoder\n");
4636 WARN(!encoder->connectors_active,
4637 "encoder->connectors_active not set\n");
4638
4639 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4640 WARN(!encoder_enabled, "encoder not enabled\n");
4641 if (WARN_ON(!encoder->base.crtc))
4642 return;
4643
4644 crtc = encoder->base.crtc;
4645
4646 WARN(!crtc->enabled, "crtc not enabled\n");
4647 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4648 WARN(pipe != to_intel_crtc(crtc)->pipe,
4649 "encoder active on the wrong pipe\n");
4650 }
4651 }
4652
4653 /* Even simpler default implementation, if there's really no special case to
4654 * consider. */
4655 void intel_connector_dpms(struct drm_connector *connector, int mode)
4656 {
4657 /* All the simple cases only support two dpms states. */
4658 if (mode != DRM_MODE_DPMS_ON)
4659 mode = DRM_MODE_DPMS_OFF;
4660
4661 if (mode == connector->dpms)
4662 return;
4663
4664 connector->dpms = mode;
4665
4666 /* Only need to change hw state when actually enabled */
4667 if (connector->encoder)
4668 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
4669
4670 intel_modeset_check_state(connector->dev);
4671 }
4672
4673 /* Simple connector->get_hw_state implementation for encoders that support only
4674 * one connector and no cloning and hence the encoder state determines the state
4675 * of the connector. */
4676 bool intel_connector_get_hw_state(struct intel_connector *connector)
4677 {
4678 enum pipe pipe = 0;
4679 struct intel_encoder *encoder = connector->encoder;
4680
4681 return encoder->get_hw_state(encoder, &pipe);
4682 }
4683
4684 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4685 struct intel_crtc_config *pipe_config)
4686 {
4687 struct drm_i915_private *dev_priv = dev->dev_private;
4688 struct intel_crtc *pipe_B_crtc =
4689 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4690
4691 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4692 pipe_name(pipe), pipe_config->fdi_lanes);
4693 if (pipe_config->fdi_lanes > 4) {
4694 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4695 pipe_name(pipe), pipe_config->fdi_lanes);
4696 return false;
4697 }
4698
4699 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4700 if (pipe_config->fdi_lanes > 2) {
4701 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4702 pipe_config->fdi_lanes);
4703 return false;
4704 } else {
4705 return true;
4706 }
4707 }
4708
4709 if (INTEL_INFO(dev)->num_pipes == 2)
4710 return true;
4711
4712 /* Ivybridge 3 pipe is really complicated */
4713 switch (pipe) {
4714 case PIPE_A:
4715 return true;
4716 case PIPE_B:
4717 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4718 pipe_config->fdi_lanes > 2) {
4719 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4720 pipe_name(pipe), pipe_config->fdi_lanes);
4721 return false;
4722 }
4723 return true;
4724 case PIPE_C:
4725 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4726 pipe_B_crtc->config.fdi_lanes <= 2) {
4727 if (pipe_config->fdi_lanes > 2) {
4728 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4729 pipe_name(pipe), pipe_config->fdi_lanes);
4730 return false;
4731 }
4732 } else {
4733 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4734 return false;
4735 }
4736 return true;
4737 default:
4738 BUG();
4739 }
4740 }
4741
4742 #define RETRY 1
4743 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4744 struct intel_crtc_config *pipe_config)
4745 {
4746 struct drm_device *dev = intel_crtc->base.dev;
4747 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4748 int lane, link_bw, fdi_dotclock;
4749 bool setup_ok, needs_recompute = false;
4750
4751 retry:
4752 /* FDI is a binary signal running at ~2.7GHz, encoding
4753 * each output octet as 10 bits. The actual frequency
4754 * is stored as a divider into a 100MHz clock, and the
4755 * mode pixel clock is stored in units of 1KHz.
4756 * Hence the bw of each lane in terms of the mode signal
4757 * is:
4758 */
4759 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4760
4761 fdi_dotclock = adjusted_mode->crtc_clock;
4762
4763 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4764 pipe_config->pipe_bpp);
4765
4766 pipe_config->fdi_lanes = lane;
4767
4768 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4769 link_bw, &pipe_config->fdi_m_n);
4770
4771 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4772 intel_crtc->pipe, pipe_config);
4773 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4774 pipe_config->pipe_bpp -= 2*3;
4775 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4776 pipe_config->pipe_bpp);
4777 needs_recompute = true;
4778 pipe_config->bw_constrained = true;
4779
4780 goto retry;
4781 }
4782
4783 if (needs_recompute)
4784 return RETRY;
4785
4786 return setup_ok ? 0 : -EINVAL;
4787 }
4788
4789 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4790 struct intel_crtc_config *pipe_config)
4791 {
4792 pipe_config->ips_enabled = i915.enable_ips &&
4793 hsw_crtc_supports_ips(crtc) &&
4794 pipe_config->pipe_bpp <= 24;
4795 }
4796
4797 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4798 struct intel_crtc_config *pipe_config)
4799 {
4800 struct drm_device *dev = crtc->base.dev;
4801 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4802
4803 /* FIXME should check pixel clock limits on all platforms */
4804 if (INTEL_INFO(dev)->gen < 4) {
4805 struct drm_i915_private *dev_priv = dev->dev_private;
4806 int clock_limit =
4807 dev_priv->display.get_display_clock_speed(dev);
4808
4809 /*
4810 * Enable pixel doubling when the dot clock
4811 * is > 90% of the (display) core speed.
4812 *
4813 * GDG double wide on either pipe,
4814 * otherwise pipe A only.
4815 */
4816 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
4817 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
4818 clock_limit *= 2;
4819 pipe_config->double_wide = true;
4820 }
4821
4822 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
4823 return -EINVAL;
4824 }
4825
4826 /*
4827 * Pipe horizontal size must be even in:
4828 * - DVO ganged mode
4829 * - LVDS dual channel mode
4830 * - Double wide pipe
4831 */
4832 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4833 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4834 pipe_config->pipe_src_w &= ~1;
4835
4836 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4837 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4838 */
4839 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4840 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4841 return -EINVAL;
4842
4843 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4844 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4845 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4846 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4847 * for lvds. */
4848 pipe_config->pipe_bpp = 8*3;
4849 }
4850
4851 if (HAS_IPS(dev))
4852 hsw_compute_ips_config(crtc, pipe_config);
4853
4854 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4855 * clock survives for now. */
4856 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4857 pipe_config->shared_dpll = crtc->config.shared_dpll;
4858
4859 if (pipe_config->has_pch_encoder)
4860 return ironlake_fdi_compute_config(crtc, pipe_config);
4861
4862 return 0;
4863 }
4864
4865 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4866 {
4867 return 400000; /* FIXME */
4868 }
4869
4870 static int i945_get_display_clock_speed(struct drm_device *dev)
4871 {
4872 return 400000;
4873 }
4874
4875 static int i915_get_display_clock_speed(struct drm_device *dev)
4876 {
4877 return 333000;
4878 }
4879
4880 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4881 {
4882 return 200000;
4883 }
4884
4885 static int pnv_get_display_clock_speed(struct drm_device *dev)
4886 {
4887 u16 gcfgc = 0;
4888
4889 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4890
4891 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4892 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4893 return 267000;
4894 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4895 return 333000;
4896 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4897 return 444000;
4898 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4899 return 200000;
4900 default:
4901 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4902 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4903 return 133000;
4904 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4905 return 167000;
4906 }
4907 }
4908
4909 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4910 {
4911 u16 gcfgc = 0;
4912
4913 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4914
4915 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4916 return 133000;
4917 else {
4918 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4919 case GC_DISPLAY_CLOCK_333_MHZ:
4920 return 333000;
4921 default:
4922 case GC_DISPLAY_CLOCK_190_200_MHZ:
4923 return 190000;
4924 }
4925 }
4926 }
4927
4928 static int i865_get_display_clock_speed(struct drm_device *dev)
4929 {
4930 return 266000;
4931 }
4932
4933 static int i855_get_display_clock_speed(struct drm_device *dev)
4934 {
4935 u16 hpllcc = 0;
4936 /* Assume that the hardware is in the high speed state. This
4937 * should be the default.
4938 */
4939 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4940 case GC_CLOCK_133_200:
4941 case GC_CLOCK_100_200:
4942 return 200000;
4943 case GC_CLOCK_166_250:
4944 return 250000;
4945 case GC_CLOCK_100_133:
4946 return 133000;
4947 }
4948
4949 /* Shouldn't happen */
4950 return 0;
4951 }
4952
4953 static int i830_get_display_clock_speed(struct drm_device *dev)
4954 {
4955 return 133000;
4956 }
4957
4958 static void
4959 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4960 {
4961 while (*num > DATA_LINK_M_N_MASK ||
4962 *den > DATA_LINK_M_N_MASK) {
4963 *num >>= 1;
4964 *den >>= 1;
4965 }
4966 }
4967
4968 static void compute_m_n(unsigned int m, unsigned int n,
4969 uint32_t *ret_m, uint32_t *ret_n)
4970 {
4971 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4972 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4973 intel_reduce_m_n_ratio(ret_m, ret_n);
4974 }
4975
4976 void
4977 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4978 int pixel_clock, int link_clock,
4979 struct intel_link_m_n *m_n)
4980 {
4981 m_n->tu = 64;
4982
4983 compute_m_n(bits_per_pixel * pixel_clock,
4984 link_clock * nlanes * 8,
4985 &m_n->gmch_m, &m_n->gmch_n);
4986
4987 compute_m_n(pixel_clock, link_clock,
4988 &m_n->link_m, &m_n->link_n);
4989 }
4990
4991 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4992 {
4993 if (i915.panel_use_ssc >= 0)
4994 return i915.panel_use_ssc != 0;
4995 return dev_priv->vbt.lvds_use_ssc
4996 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4997 }
4998
4999 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5000 {
5001 struct drm_device *dev = crtc->dev;
5002 struct drm_i915_private *dev_priv = dev->dev_private;
5003 int refclk;
5004
5005 if (IS_VALLEYVIEW(dev)) {
5006 refclk = 100000;
5007 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5008 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5009 refclk = dev_priv->vbt.lvds_ssc_freq;
5010 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5011 } else if (!IS_GEN2(dev)) {
5012 refclk = 96000;
5013 } else {
5014 refclk = 48000;
5015 }
5016
5017 return refclk;
5018 }
5019
5020 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5021 {
5022 return (1 << dpll->n) << 16 | dpll->m2;
5023 }
5024
5025 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5026 {
5027 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5028 }
5029
5030 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5031 intel_clock_t *reduced_clock)
5032 {
5033 struct drm_device *dev = crtc->base.dev;
5034 struct drm_i915_private *dev_priv = dev->dev_private;
5035 int pipe = crtc->pipe;
5036 u32 fp, fp2 = 0;
5037
5038 if (IS_PINEVIEW(dev)) {
5039 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5040 if (reduced_clock)
5041 fp2 = pnv_dpll_compute_fp(reduced_clock);
5042 } else {
5043 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5044 if (reduced_clock)
5045 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5046 }
5047
5048 I915_WRITE(FP0(pipe), fp);
5049 crtc->config.dpll_hw_state.fp0 = fp;
5050
5051 crtc->lowfreq_avail = false;
5052 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5053 reduced_clock && i915.powersave) {
5054 I915_WRITE(FP1(pipe), fp2);
5055 crtc->config.dpll_hw_state.fp1 = fp2;
5056 crtc->lowfreq_avail = true;
5057 } else {
5058 I915_WRITE(FP1(pipe), fp);
5059 crtc->config.dpll_hw_state.fp1 = fp;
5060 }
5061 }
5062
5063 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5064 pipe)
5065 {
5066 u32 reg_val;
5067
5068 /*
5069 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5070 * and set it to a reasonable value instead.
5071 */
5072 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5073 reg_val &= 0xffffff00;
5074 reg_val |= 0x00000030;
5075 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5076
5077 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5078 reg_val &= 0x8cffffff;
5079 reg_val = 0x8c000000;
5080 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5081
5082 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5083 reg_val &= 0xffffff00;
5084 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5085
5086 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5087 reg_val &= 0x00ffffff;
5088 reg_val |= 0xb0000000;
5089 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5090 }
5091
5092 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5093 struct intel_link_m_n *m_n)
5094 {
5095 struct drm_device *dev = crtc->base.dev;
5096 struct drm_i915_private *dev_priv = dev->dev_private;
5097 int pipe = crtc->pipe;
5098
5099 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5100 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5101 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5102 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5103 }
5104
5105 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5106 struct intel_link_m_n *m_n)
5107 {
5108 struct drm_device *dev = crtc->base.dev;
5109 struct drm_i915_private *dev_priv = dev->dev_private;
5110 int pipe = crtc->pipe;
5111 enum transcoder transcoder = crtc->config.cpu_transcoder;
5112
5113 if (INTEL_INFO(dev)->gen >= 5) {
5114 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5115 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5116 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5117 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5118 } else {
5119 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5120 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5121 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5122 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5123 }
5124 }
5125
5126 static void intel_dp_set_m_n(struct intel_crtc *crtc)
5127 {
5128 if (crtc->config.has_pch_encoder)
5129 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5130 else
5131 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5132 }
5133
5134 static void vlv_update_pll(struct intel_crtc *crtc)
5135 {
5136 struct drm_device *dev = crtc->base.dev;
5137 struct drm_i915_private *dev_priv = dev->dev_private;
5138 int pipe = crtc->pipe;
5139 u32 dpll, mdiv;
5140 u32 bestn, bestm1, bestm2, bestp1, bestp2;
5141 u32 coreclk, reg_val, dpll_md;
5142
5143 mutex_lock(&dev_priv->dpio_lock);
5144
5145 bestn = crtc->config.dpll.n;
5146 bestm1 = crtc->config.dpll.m1;
5147 bestm2 = crtc->config.dpll.m2;
5148 bestp1 = crtc->config.dpll.p1;
5149 bestp2 = crtc->config.dpll.p2;
5150
5151 /* See eDP HDMI DPIO driver vbios notes doc */
5152
5153 /* PLL B needs special handling */
5154 if (pipe)
5155 vlv_pllb_recal_opamp(dev_priv, pipe);
5156
5157 /* Set up Tx target for periodic Rcomp update */
5158 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5159
5160 /* Disable target IRef on PLL */
5161 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5162 reg_val &= 0x00ffffff;
5163 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5164
5165 /* Disable fast lock */
5166 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5167
5168 /* Set idtafcrecal before PLL is enabled */
5169 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5170 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5171 mdiv |= ((bestn << DPIO_N_SHIFT));
5172 mdiv |= (1 << DPIO_K_SHIFT);
5173
5174 /*
5175 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5176 * but we don't support that).
5177 * Note: don't use the DAC post divider as it seems unstable.
5178 */
5179 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5180 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5181
5182 mdiv |= DPIO_ENABLE_CALIBRATION;
5183 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5184
5185 /* Set HBR and RBR LPF coefficients */
5186 if (crtc->config.port_clock == 162000 ||
5187 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5188 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5189 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5190 0x009f0003);
5191 else
5192 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5193 0x00d0000f);
5194
5195 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5196 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5197 /* Use SSC source */
5198 if (!pipe)
5199 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5200 0x0df40000);
5201 else
5202 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5203 0x0df70000);
5204 } else { /* HDMI or VGA */
5205 /* Use bend source */
5206 if (!pipe)
5207 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5208 0x0df70000);
5209 else
5210 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5211 0x0df40000);
5212 }
5213
5214 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5215 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5216 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5217 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5218 coreclk |= 0x01000000;
5219 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5220
5221 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5222
5223 /*
5224 * Enable DPIO clock input. We should never disable the reference
5225 * clock for pipe B, since VGA hotplug / manual detection depends
5226 * on it.
5227 */
5228 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5229 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5230 /* We should never disable this, set it here for state tracking */
5231 if (pipe == PIPE_B)
5232 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5233 dpll |= DPLL_VCO_ENABLE;
5234 crtc->config.dpll_hw_state.dpll = dpll;
5235
5236 dpll_md = (crtc->config.pixel_multiplier - 1)
5237 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5238 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5239
5240 if (crtc->config.has_dp_encoder)
5241 intel_dp_set_m_n(crtc);
5242
5243 mutex_unlock(&dev_priv->dpio_lock);
5244 }
5245
5246 static void i9xx_update_pll(struct intel_crtc *crtc,
5247 intel_clock_t *reduced_clock,
5248 int num_connectors)
5249 {
5250 struct drm_device *dev = crtc->base.dev;
5251 struct drm_i915_private *dev_priv = dev->dev_private;
5252 u32 dpll;
5253 bool is_sdvo;
5254 struct dpll *clock = &crtc->config.dpll;
5255
5256 i9xx_update_pll_dividers(crtc, reduced_clock);
5257
5258 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5259 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5260
5261 dpll = DPLL_VGA_MODE_DIS;
5262
5263 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5264 dpll |= DPLLB_MODE_LVDS;
5265 else
5266 dpll |= DPLLB_MODE_DAC_SERIAL;
5267
5268 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5269 dpll |= (crtc->config.pixel_multiplier - 1)
5270 << SDVO_MULTIPLIER_SHIFT_HIRES;
5271 }
5272
5273 if (is_sdvo)
5274 dpll |= DPLL_SDVO_HIGH_SPEED;
5275
5276 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5277 dpll |= DPLL_SDVO_HIGH_SPEED;
5278
5279 /* compute bitmask from p1 value */
5280 if (IS_PINEVIEW(dev))
5281 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5282 else {
5283 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5284 if (IS_G4X(dev) && reduced_clock)
5285 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5286 }
5287 switch (clock->p2) {
5288 case 5:
5289 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5290 break;
5291 case 7:
5292 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5293 break;
5294 case 10:
5295 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5296 break;
5297 case 14:
5298 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5299 break;
5300 }
5301 if (INTEL_INFO(dev)->gen >= 4)
5302 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5303
5304 if (crtc->config.sdvo_tv_clock)
5305 dpll |= PLL_REF_INPUT_TVCLKINBC;
5306 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5307 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5308 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5309 else
5310 dpll |= PLL_REF_INPUT_DREFCLK;
5311
5312 dpll |= DPLL_VCO_ENABLE;
5313 crtc->config.dpll_hw_state.dpll = dpll;
5314
5315 if (INTEL_INFO(dev)->gen >= 4) {
5316 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5317 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5318 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5319 }
5320
5321 if (crtc->config.has_dp_encoder)
5322 intel_dp_set_m_n(crtc);
5323 }
5324
5325 static void i8xx_update_pll(struct intel_crtc *crtc,
5326 intel_clock_t *reduced_clock,
5327 int num_connectors)
5328 {
5329 struct drm_device *dev = crtc->base.dev;
5330 struct drm_i915_private *dev_priv = dev->dev_private;
5331 u32 dpll;
5332 struct dpll *clock = &crtc->config.dpll;
5333
5334 i9xx_update_pll_dividers(crtc, reduced_clock);
5335
5336 dpll = DPLL_VGA_MODE_DIS;
5337
5338 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5339 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5340 } else {
5341 if (clock->p1 == 2)
5342 dpll |= PLL_P1_DIVIDE_BY_TWO;
5343 else
5344 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5345 if (clock->p2 == 4)
5346 dpll |= PLL_P2_DIVIDE_BY_4;
5347 }
5348
5349 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5350 dpll |= DPLL_DVO_2X_MODE;
5351
5352 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5353 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5354 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5355 else
5356 dpll |= PLL_REF_INPUT_DREFCLK;
5357
5358 dpll |= DPLL_VCO_ENABLE;
5359 crtc->config.dpll_hw_state.dpll = dpll;
5360 }
5361
5362 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5363 {
5364 struct drm_device *dev = intel_crtc->base.dev;
5365 struct drm_i915_private *dev_priv = dev->dev_private;
5366 enum pipe pipe = intel_crtc->pipe;
5367 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5368 struct drm_display_mode *adjusted_mode =
5369 &intel_crtc->config.adjusted_mode;
5370 uint32_t crtc_vtotal, crtc_vblank_end;
5371 int vsyncshift = 0;
5372
5373 /* We need to be careful not to changed the adjusted mode, for otherwise
5374 * the hw state checker will get angry at the mismatch. */
5375 crtc_vtotal = adjusted_mode->crtc_vtotal;
5376 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5377
5378 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5379 /* the chip adds 2 halflines automatically */
5380 crtc_vtotal -= 1;
5381 crtc_vblank_end -= 1;
5382
5383 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5384 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5385 else
5386 vsyncshift = adjusted_mode->crtc_hsync_start -
5387 adjusted_mode->crtc_htotal / 2;
5388 if (vsyncshift < 0)
5389 vsyncshift += adjusted_mode->crtc_htotal;
5390 }
5391
5392 if (INTEL_INFO(dev)->gen > 3)
5393 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5394
5395 I915_WRITE(HTOTAL(cpu_transcoder),
5396 (adjusted_mode->crtc_hdisplay - 1) |
5397 ((adjusted_mode->crtc_htotal - 1) << 16));
5398 I915_WRITE(HBLANK(cpu_transcoder),
5399 (adjusted_mode->crtc_hblank_start - 1) |
5400 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5401 I915_WRITE(HSYNC(cpu_transcoder),
5402 (adjusted_mode->crtc_hsync_start - 1) |
5403 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5404
5405 I915_WRITE(VTOTAL(cpu_transcoder),
5406 (adjusted_mode->crtc_vdisplay - 1) |
5407 ((crtc_vtotal - 1) << 16));
5408 I915_WRITE(VBLANK(cpu_transcoder),
5409 (adjusted_mode->crtc_vblank_start - 1) |
5410 ((crtc_vblank_end - 1) << 16));
5411 I915_WRITE(VSYNC(cpu_transcoder),
5412 (adjusted_mode->crtc_vsync_start - 1) |
5413 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5414
5415 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5416 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5417 * documented on the DDI_FUNC_CTL register description, EDP Input Select
5418 * bits. */
5419 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5420 (pipe == PIPE_B || pipe == PIPE_C))
5421 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5422
5423 /* pipesrc controls the size that is scaled from, which should
5424 * always be the user's requested size.
5425 */
5426 I915_WRITE(PIPESRC(pipe),
5427 ((intel_crtc->config.pipe_src_w - 1) << 16) |
5428 (intel_crtc->config.pipe_src_h - 1));
5429 }
5430
5431 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5432 struct intel_crtc_config *pipe_config)
5433 {
5434 struct drm_device *dev = crtc->base.dev;
5435 struct drm_i915_private *dev_priv = dev->dev_private;
5436 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5437 uint32_t tmp;
5438
5439 tmp = I915_READ(HTOTAL(cpu_transcoder));
5440 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5441 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5442 tmp = I915_READ(HBLANK(cpu_transcoder));
5443 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5444 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5445 tmp = I915_READ(HSYNC(cpu_transcoder));
5446 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5447 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5448
5449 tmp = I915_READ(VTOTAL(cpu_transcoder));
5450 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5451 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5452 tmp = I915_READ(VBLANK(cpu_transcoder));
5453 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5454 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5455 tmp = I915_READ(VSYNC(cpu_transcoder));
5456 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5457 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5458
5459 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5460 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5461 pipe_config->adjusted_mode.crtc_vtotal += 1;
5462 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5463 }
5464
5465 tmp = I915_READ(PIPESRC(crtc->pipe));
5466 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5467 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5468
5469 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5470 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5471 }
5472
5473 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5474 struct intel_crtc_config *pipe_config)
5475 {
5476 mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5477 mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
5478 mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5479 mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5480
5481 mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5482 mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5483 mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5484 mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5485
5486 mode->flags = pipe_config->adjusted_mode.flags;
5487
5488 mode->clock = pipe_config->adjusted_mode.crtc_clock;
5489 mode->flags |= pipe_config->adjusted_mode.flags;
5490 }
5491
5492 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5493 {
5494 struct drm_device *dev = intel_crtc->base.dev;
5495 struct drm_i915_private *dev_priv = dev->dev_private;
5496 uint32_t pipeconf;
5497
5498 pipeconf = 0;
5499
5500 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5501 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5502 pipeconf |= PIPECONF_ENABLE;
5503
5504 if (intel_crtc->config.double_wide)
5505 pipeconf |= PIPECONF_DOUBLE_WIDE;
5506
5507 /* only g4x and later have fancy bpc/dither controls */
5508 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5509 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5510 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5511 pipeconf |= PIPECONF_DITHER_EN |
5512 PIPECONF_DITHER_TYPE_SP;
5513
5514 switch (intel_crtc->config.pipe_bpp) {
5515 case 18:
5516 pipeconf |= PIPECONF_6BPC;
5517 break;
5518 case 24:
5519 pipeconf |= PIPECONF_8BPC;
5520 break;
5521 case 30:
5522 pipeconf |= PIPECONF_10BPC;
5523 break;
5524 default:
5525 /* Case prevented by intel_choose_pipe_bpp_dither. */
5526 BUG();
5527 }
5528 }
5529
5530 if (HAS_PIPE_CXSR(dev)) {
5531 if (intel_crtc->lowfreq_avail) {
5532 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5533 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5534 } else {
5535 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5536 }
5537 }
5538
5539 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
5540 if (INTEL_INFO(dev)->gen < 4 ||
5541 intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5542 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5543 else
5544 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
5545 } else
5546 pipeconf |= PIPECONF_PROGRESSIVE;
5547
5548 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5549 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5550
5551 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5552 POSTING_READ(PIPECONF(intel_crtc->pipe));
5553 }
5554
5555 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5556 int x, int y,
5557 struct drm_framebuffer *fb)
5558 {
5559 struct drm_device *dev = crtc->dev;
5560 struct drm_i915_private *dev_priv = dev->dev_private;
5561 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5562 int pipe = intel_crtc->pipe;
5563 int plane = intel_crtc->plane;
5564 int refclk, num_connectors = 0;
5565 intel_clock_t clock, reduced_clock;
5566 u32 dspcntr;
5567 bool ok, has_reduced_clock = false;
5568 bool is_lvds = false, is_dsi = false;
5569 struct intel_encoder *encoder;
5570 const intel_limit_t *limit;
5571 int ret;
5572
5573 for_each_encoder_on_crtc(dev, crtc, encoder) {
5574 switch (encoder->type) {
5575 case INTEL_OUTPUT_LVDS:
5576 is_lvds = true;
5577 break;
5578 case INTEL_OUTPUT_DSI:
5579 is_dsi = true;
5580 break;
5581 }
5582
5583 num_connectors++;
5584 }
5585
5586 if (is_dsi)
5587 goto skip_dpll;
5588
5589 if (!intel_crtc->config.clock_set) {
5590 refclk = i9xx_get_refclk(crtc, num_connectors);
5591
5592 /*
5593 * Returns a set of divisors for the desired target clock with
5594 * the given refclk, or FALSE. The returned values represent
5595 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5596 * 2) / p1 / p2.
5597 */
5598 limit = intel_limit(crtc, refclk);
5599 ok = dev_priv->display.find_dpll(limit, crtc,
5600 intel_crtc->config.port_clock,
5601 refclk, NULL, &clock);
5602 if (!ok) {
5603 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5604 return -EINVAL;
5605 }
5606
5607 if (is_lvds && dev_priv->lvds_downclock_avail) {
5608 /*
5609 * Ensure we match the reduced clock's P to the target
5610 * clock. If the clocks don't match, we can't switch
5611 * the display clock by using the FP0/FP1. In such case
5612 * we will disable the LVDS downclock feature.
5613 */
5614 has_reduced_clock =
5615 dev_priv->display.find_dpll(limit, crtc,
5616 dev_priv->lvds_downclock,
5617 refclk, &clock,
5618 &reduced_clock);
5619 }
5620 /* Compat-code for transition, will disappear. */
5621 intel_crtc->config.dpll.n = clock.n;
5622 intel_crtc->config.dpll.m1 = clock.m1;
5623 intel_crtc->config.dpll.m2 = clock.m2;
5624 intel_crtc->config.dpll.p1 = clock.p1;
5625 intel_crtc->config.dpll.p2 = clock.p2;
5626 }
5627
5628 if (IS_GEN2(dev)) {
5629 i8xx_update_pll(intel_crtc,
5630 has_reduced_clock ? &reduced_clock : NULL,
5631 num_connectors);
5632 } else if (IS_VALLEYVIEW(dev)) {
5633 vlv_update_pll(intel_crtc);
5634 } else {
5635 i9xx_update_pll(intel_crtc,
5636 has_reduced_clock ? &reduced_clock : NULL,
5637 num_connectors);
5638 }
5639
5640 skip_dpll:
5641 /* Set up the display plane register */
5642 dspcntr = DISPPLANE_GAMMA_ENABLE;
5643
5644 if (!IS_VALLEYVIEW(dev)) {
5645 if (pipe == 0)
5646 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5647 else
5648 dspcntr |= DISPPLANE_SEL_PIPE_B;
5649 }
5650
5651 intel_set_pipe_timings(intel_crtc);
5652
5653 /* pipesrc and dspsize control the size that is scaled from,
5654 * which should always be the user's requested size.
5655 */
5656 I915_WRITE(DSPSIZE(plane),
5657 ((intel_crtc->config.pipe_src_h - 1) << 16) |
5658 (intel_crtc->config.pipe_src_w - 1));
5659 I915_WRITE(DSPPOS(plane), 0);
5660
5661 i9xx_set_pipeconf(intel_crtc);
5662
5663 I915_WRITE(DSPCNTR(plane), dspcntr);
5664 POSTING_READ(DSPCNTR(plane));
5665
5666 ret = intel_pipe_set_base(crtc, x, y, fb);
5667
5668 return ret;
5669 }
5670
5671 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5672 struct intel_crtc_config *pipe_config)
5673 {
5674 struct drm_device *dev = crtc->base.dev;
5675 struct drm_i915_private *dev_priv = dev->dev_private;
5676 uint32_t tmp;
5677
5678 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
5679 return;
5680
5681 tmp = I915_READ(PFIT_CONTROL);
5682 if (!(tmp & PFIT_ENABLE))
5683 return;
5684
5685 /* Check whether the pfit is attached to our pipe. */
5686 if (INTEL_INFO(dev)->gen < 4) {
5687 if (crtc->pipe != PIPE_B)
5688 return;
5689 } else {
5690 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5691 return;
5692 }
5693
5694 pipe_config->gmch_pfit.control = tmp;
5695 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5696 if (INTEL_INFO(dev)->gen < 5)
5697 pipe_config->gmch_pfit.lvds_border_bits =
5698 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5699 }
5700
5701 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5702 struct intel_crtc_config *pipe_config)
5703 {
5704 struct drm_device *dev = crtc->base.dev;
5705 struct drm_i915_private *dev_priv = dev->dev_private;
5706 int pipe = pipe_config->cpu_transcoder;
5707 intel_clock_t clock;
5708 u32 mdiv;
5709 int refclk = 100000;
5710
5711 mutex_lock(&dev_priv->dpio_lock);
5712 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
5713 mutex_unlock(&dev_priv->dpio_lock);
5714
5715 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5716 clock.m2 = mdiv & DPIO_M2DIV_MASK;
5717 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5718 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5719 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5720
5721 vlv_clock(refclk, &clock);
5722
5723 /* clock.dot is the fast clock */
5724 pipe_config->port_clock = clock.dot / 5;
5725 }
5726
5727 static void i9xx_get_plane_config(struct intel_crtc *crtc,
5728 struct intel_plane_config *plane_config)
5729 {
5730 struct drm_device *dev = crtc->base.dev;
5731 struct drm_i915_private *dev_priv = dev->dev_private;
5732 u32 val, base, offset;
5733 int pipe = crtc->pipe, plane = crtc->plane;
5734 int fourcc, pixel_format;
5735 int aligned_height;
5736
5737 crtc->base.fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
5738 if (!crtc->base.fb) {
5739 DRM_DEBUG_KMS("failed to alloc fb\n");
5740 return;
5741 }
5742
5743 val = I915_READ(DSPCNTR(plane));
5744
5745 if (INTEL_INFO(dev)->gen >= 4)
5746 if (val & DISPPLANE_TILED)
5747 plane_config->tiled = true;
5748
5749 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
5750 fourcc = intel_format_to_fourcc(pixel_format);
5751 crtc->base.fb->pixel_format = fourcc;
5752 crtc->base.fb->bits_per_pixel =
5753 drm_format_plane_cpp(fourcc, 0) * 8;
5754
5755 if (INTEL_INFO(dev)->gen >= 4) {
5756 if (plane_config->tiled)
5757 offset = I915_READ(DSPTILEOFF(plane));
5758 else
5759 offset = I915_READ(DSPLINOFF(plane));
5760 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
5761 } else {
5762 base = I915_READ(DSPADDR(plane));
5763 }
5764 plane_config->base = base;
5765
5766 val = I915_READ(PIPESRC(pipe));
5767 crtc->base.fb->width = ((val >> 16) & 0xfff) + 1;
5768 crtc->base.fb->height = ((val >> 0) & 0xfff) + 1;
5769
5770 val = I915_READ(DSPSTRIDE(pipe));
5771 crtc->base.fb->pitches[0] = val & 0xffffff80;
5772
5773 aligned_height = intel_align_height(dev, crtc->base.fb->height,
5774 plane_config->tiled);
5775
5776 plane_config->size = ALIGN(crtc->base.fb->pitches[0] *
5777 aligned_height, PAGE_SIZE);
5778
5779 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
5780 pipe, plane, crtc->base.fb->width,
5781 crtc->base.fb->height,
5782 crtc->base.fb->bits_per_pixel, base,
5783 crtc->base.fb->pitches[0],
5784 plane_config->size);
5785
5786 }
5787
5788 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5789 struct intel_crtc_config *pipe_config)
5790 {
5791 struct drm_device *dev = crtc->base.dev;
5792 struct drm_i915_private *dev_priv = dev->dev_private;
5793 uint32_t tmp;
5794
5795 if (!intel_display_power_enabled(dev_priv,
5796 POWER_DOMAIN_PIPE(crtc->pipe)))
5797 return false;
5798
5799 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5800 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5801
5802 tmp = I915_READ(PIPECONF(crtc->pipe));
5803 if (!(tmp & PIPECONF_ENABLE))
5804 return false;
5805
5806 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5807 switch (tmp & PIPECONF_BPC_MASK) {
5808 case PIPECONF_6BPC:
5809 pipe_config->pipe_bpp = 18;
5810 break;
5811 case PIPECONF_8BPC:
5812 pipe_config->pipe_bpp = 24;
5813 break;
5814 case PIPECONF_10BPC:
5815 pipe_config->pipe_bpp = 30;
5816 break;
5817 default:
5818 break;
5819 }
5820 }
5821
5822 if (INTEL_INFO(dev)->gen < 4)
5823 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5824
5825 intel_get_pipe_timings(crtc, pipe_config);
5826
5827 i9xx_get_pfit_config(crtc, pipe_config);
5828
5829 if (INTEL_INFO(dev)->gen >= 4) {
5830 tmp = I915_READ(DPLL_MD(crtc->pipe));
5831 pipe_config->pixel_multiplier =
5832 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5833 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5834 pipe_config->dpll_hw_state.dpll_md = tmp;
5835 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5836 tmp = I915_READ(DPLL(crtc->pipe));
5837 pipe_config->pixel_multiplier =
5838 ((tmp & SDVO_MULTIPLIER_MASK)
5839 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5840 } else {
5841 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5842 * port and will be fixed up in the encoder->get_config
5843 * function. */
5844 pipe_config->pixel_multiplier = 1;
5845 }
5846 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5847 if (!IS_VALLEYVIEW(dev)) {
5848 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5849 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5850 } else {
5851 /* Mask out read-only status bits. */
5852 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5853 DPLL_PORTC_READY_MASK |
5854 DPLL_PORTB_READY_MASK);
5855 }
5856
5857 if (IS_VALLEYVIEW(dev))
5858 vlv_crtc_clock_get(crtc, pipe_config);
5859 else
5860 i9xx_crtc_clock_get(crtc, pipe_config);
5861
5862 return true;
5863 }
5864
5865 static void ironlake_init_pch_refclk(struct drm_device *dev)
5866 {
5867 struct drm_i915_private *dev_priv = dev->dev_private;
5868 struct drm_mode_config *mode_config = &dev->mode_config;
5869 struct intel_encoder *encoder;
5870 u32 val, final;
5871 bool has_lvds = false;
5872 bool has_cpu_edp = false;
5873 bool has_panel = false;
5874 bool has_ck505 = false;
5875 bool can_ssc = false;
5876
5877 /* We need to take the global config into account */
5878 list_for_each_entry(encoder, &mode_config->encoder_list,
5879 base.head) {
5880 switch (encoder->type) {
5881 case INTEL_OUTPUT_LVDS:
5882 has_panel = true;
5883 has_lvds = true;
5884 break;
5885 case INTEL_OUTPUT_EDP:
5886 has_panel = true;
5887 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5888 has_cpu_edp = true;
5889 break;
5890 }
5891 }
5892
5893 if (HAS_PCH_IBX(dev)) {
5894 has_ck505 = dev_priv->vbt.display_clock_mode;
5895 can_ssc = has_ck505;
5896 } else {
5897 has_ck505 = false;
5898 can_ssc = true;
5899 }
5900
5901 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5902 has_panel, has_lvds, has_ck505);
5903
5904 /* Ironlake: try to setup display ref clock before DPLL
5905 * enabling. This is only under driver's control after
5906 * PCH B stepping, previous chipset stepping should be
5907 * ignoring this setting.
5908 */
5909 val = I915_READ(PCH_DREF_CONTROL);
5910
5911 /* As we must carefully and slowly disable/enable each source in turn,
5912 * compute the final state we want first and check if we need to
5913 * make any changes at all.
5914 */
5915 final = val;
5916 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5917 if (has_ck505)
5918 final |= DREF_NONSPREAD_CK505_ENABLE;
5919 else
5920 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5921
5922 final &= ~DREF_SSC_SOURCE_MASK;
5923 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5924 final &= ~DREF_SSC1_ENABLE;
5925
5926 if (has_panel) {
5927 final |= DREF_SSC_SOURCE_ENABLE;
5928
5929 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5930 final |= DREF_SSC1_ENABLE;
5931
5932 if (has_cpu_edp) {
5933 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5934 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5935 else
5936 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5937 } else
5938 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5939 } else {
5940 final |= DREF_SSC_SOURCE_DISABLE;
5941 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5942 }
5943
5944 if (final == val)
5945 return;
5946
5947 /* Always enable nonspread source */
5948 val &= ~DREF_NONSPREAD_SOURCE_MASK;
5949
5950 if (has_ck505)
5951 val |= DREF_NONSPREAD_CK505_ENABLE;
5952 else
5953 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5954
5955 if (has_panel) {
5956 val &= ~DREF_SSC_SOURCE_MASK;
5957 val |= DREF_SSC_SOURCE_ENABLE;
5958
5959 /* SSC must be turned on before enabling the CPU output */
5960 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5961 DRM_DEBUG_KMS("Using SSC on panel\n");
5962 val |= DREF_SSC1_ENABLE;
5963 } else
5964 val &= ~DREF_SSC1_ENABLE;
5965
5966 /* Get SSC going before enabling the outputs */
5967 I915_WRITE(PCH_DREF_CONTROL, val);
5968 POSTING_READ(PCH_DREF_CONTROL);
5969 udelay(200);
5970
5971 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5972
5973 /* Enable CPU source on CPU attached eDP */
5974 if (has_cpu_edp) {
5975 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5976 DRM_DEBUG_KMS("Using SSC on eDP\n");
5977 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5978 }
5979 else
5980 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5981 } else
5982 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5983
5984 I915_WRITE(PCH_DREF_CONTROL, val);
5985 POSTING_READ(PCH_DREF_CONTROL);
5986 udelay(200);
5987 } else {
5988 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5989
5990 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5991
5992 /* Turn off CPU output */
5993 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5994
5995 I915_WRITE(PCH_DREF_CONTROL, val);
5996 POSTING_READ(PCH_DREF_CONTROL);
5997 udelay(200);
5998
5999 /* Turn off the SSC source */
6000 val &= ~DREF_SSC_SOURCE_MASK;
6001 val |= DREF_SSC_SOURCE_DISABLE;
6002
6003 /* Turn off SSC1 */
6004 val &= ~DREF_SSC1_ENABLE;
6005
6006 I915_WRITE(PCH_DREF_CONTROL, val);
6007 POSTING_READ(PCH_DREF_CONTROL);
6008 udelay(200);
6009 }
6010
6011 BUG_ON(val != final);
6012 }
6013
6014 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6015 {
6016 uint32_t tmp;
6017
6018 tmp = I915_READ(SOUTH_CHICKEN2);
6019 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6020 I915_WRITE(SOUTH_CHICKEN2, tmp);
6021
6022 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6023 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6024 DRM_ERROR("FDI mPHY reset assert timeout\n");
6025
6026 tmp = I915_READ(SOUTH_CHICKEN2);
6027 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6028 I915_WRITE(SOUTH_CHICKEN2, tmp);
6029
6030 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6031 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6032 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6033 }
6034
6035 /* WaMPhyProgramming:hsw */
6036 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6037 {
6038 uint32_t tmp;
6039
6040 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6041 tmp &= ~(0xFF << 24);
6042 tmp |= (0x12 << 24);
6043 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6044
6045 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6046 tmp |= (1 << 11);
6047 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6048
6049 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6050 tmp |= (1 << 11);
6051 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6052
6053 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6054 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6055 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6056
6057 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6058 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6059 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6060
6061 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6062 tmp &= ~(7 << 13);
6063 tmp |= (5 << 13);
6064 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6065
6066 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6067 tmp &= ~(7 << 13);
6068 tmp |= (5 << 13);
6069 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6070
6071 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6072 tmp &= ~0xFF;
6073 tmp |= 0x1C;
6074 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6075
6076 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6077 tmp &= ~0xFF;
6078 tmp |= 0x1C;
6079 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6080
6081 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6082 tmp &= ~(0xFF << 16);
6083 tmp |= (0x1C << 16);
6084 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6085
6086 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6087 tmp &= ~(0xFF << 16);
6088 tmp |= (0x1C << 16);
6089 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6090
6091 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6092 tmp |= (1 << 27);
6093 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6094
6095 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6096 tmp |= (1 << 27);
6097 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6098
6099 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6100 tmp &= ~(0xF << 28);
6101 tmp |= (4 << 28);
6102 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6103
6104 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6105 tmp &= ~(0xF << 28);
6106 tmp |= (4 << 28);
6107 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6108 }
6109
6110 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6111 * Programming" based on the parameters passed:
6112 * - Sequence to enable CLKOUT_DP
6113 * - Sequence to enable CLKOUT_DP without spread
6114 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6115 */
6116 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6117 bool with_fdi)
6118 {
6119 struct drm_i915_private *dev_priv = dev->dev_private;
6120 uint32_t reg, tmp;
6121
6122 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6123 with_spread = true;
6124 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6125 with_fdi, "LP PCH doesn't have FDI\n"))
6126 with_fdi = false;
6127
6128 mutex_lock(&dev_priv->dpio_lock);
6129
6130 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6131 tmp &= ~SBI_SSCCTL_DISABLE;
6132 tmp |= SBI_SSCCTL_PATHALT;
6133 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6134
6135 udelay(24);
6136
6137 if (with_spread) {
6138 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6139 tmp &= ~SBI_SSCCTL_PATHALT;
6140 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6141
6142 if (with_fdi) {
6143 lpt_reset_fdi_mphy(dev_priv);
6144 lpt_program_fdi_mphy(dev_priv);
6145 }
6146 }
6147
6148 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6149 SBI_GEN0 : SBI_DBUFF0;
6150 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6151 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6152 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6153
6154 mutex_unlock(&dev_priv->dpio_lock);
6155 }
6156
6157 /* Sequence to disable CLKOUT_DP */
6158 static void lpt_disable_clkout_dp(struct drm_device *dev)
6159 {
6160 struct drm_i915_private *dev_priv = dev->dev_private;
6161 uint32_t reg, tmp;
6162
6163 mutex_lock(&dev_priv->dpio_lock);
6164
6165 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6166 SBI_GEN0 : SBI_DBUFF0;
6167 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6168 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6169 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6170
6171 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6172 if (!(tmp & SBI_SSCCTL_DISABLE)) {
6173 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6174 tmp |= SBI_SSCCTL_PATHALT;
6175 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6176 udelay(32);
6177 }
6178 tmp |= SBI_SSCCTL_DISABLE;
6179 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6180 }
6181
6182 mutex_unlock(&dev_priv->dpio_lock);
6183 }
6184
6185 static void lpt_init_pch_refclk(struct drm_device *dev)
6186 {
6187 struct drm_mode_config *mode_config = &dev->mode_config;
6188 struct intel_encoder *encoder;
6189 bool has_vga = false;
6190
6191 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
6192 switch (encoder->type) {
6193 case INTEL_OUTPUT_ANALOG:
6194 has_vga = true;
6195 break;
6196 }
6197 }
6198
6199 if (has_vga)
6200 lpt_enable_clkout_dp(dev, true, true);
6201 else
6202 lpt_disable_clkout_dp(dev);
6203 }
6204
6205 /*
6206 * Initialize reference clocks when the driver loads
6207 */
6208 void intel_init_pch_refclk(struct drm_device *dev)
6209 {
6210 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6211 ironlake_init_pch_refclk(dev);
6212 else if (HAS_PCH_LPT(dev))
6213 lpt_init_pch_refclk(dev);
6214 }
6215
6216 static int ironlake_get_refclk(struct drm_crtc *crtc)
6217 {
6218 struct drm_device *dev = crtc->dev;
6219 struct drm_i915_private *dev_priv = dev->dev_private;
6220 struct intel_encoder *encoder;
6221 int num_connectors = 0;
6222 bool is_lvds = false;
6223
6224 for_each_encoder_on_crtc(dev, crtc, encoder) {
6225 switch (encoder->type) {
6226 case INTEL_OUTPUT_LVDS:
6227 is_lvds = true;
6228 break;
6229 }
6230 num_connectors++;
6231 }
6232
6233 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6234 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6235 dev_priv->vbt.lvds_ssc_freq);
6236 return dev_priv->vbt.lvds_ssc_freq;
6237 }
6238
6239 return 120000;
6240 }
6241
6242 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6243 {
6244 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6245 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6246 int pipe = intel_crtc->pipe;
6247 uint32_t val;
6248
6249 val = 0;
6250
6251 switch (intel_crtc->config.pipe_bpp) {
6252 case 18:
6253 val |= PIPECONF_6BPC;
6254 break;
6255 case 24:
6256 val |= PIPECONF_8BPC;
6257 break;
6258 case 30:
6259 val |= PIPECONF_10BPC;
6260 break;
6261 case 36:
6262 val |= PIPECONF_12BPC;
6263 break;
6264 default:
6265 /* Case prevented by intel_choose_pipe_bpp_dither. */
6266 BUG();
6267 }
6268
6269 if (intel_crtc->config.dither)
6270 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6271
6272 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6273 val |= PIPECONF_INTERLACED_ILK;
6274 else
6275 val |= PIPECONF_PROGRESSIVE;
6276
6277 if (intel_crtc->config.limited_color_range)
6278 val |= PIPECONF_COLOR_RANGE_SELECT;
6279
6280 I915_WRITE(PIPECONF(pipe), val);
6281 POSTING_READ(PIPECONF(pipe));
6282 }
6283
6284 /*
6285 * Set up the pipe CSC unit.
6286 *
6287 * Currently only full range RGB to limited range RGB conversion
6288 * is supported, but eventually this should handle various
6289 * RGB<->YCbCr scenarios as well.
6290 */
6291 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6292 {
6293 struct drm_device *dev = crtc->dev;
6294 struct drm_i915_private *dev_priv = dev->dev_private;
6295 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6296 int pipe = intel_crtc->pipe;
6297 uint16_t coeff = 0x7800; /* 1.0 */
6298
6299 /*
6300 * TODO: Check what kind of values actually come out of the pipe
6301 * with these coeff/postoff values and adjust to get the best
6302 * accuracy. Perhaps we even need to take the bpc value into
6303 * consideration.
6304 */
6305
6306 if (intel_crtc->config.limited_color_range)
6307 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6308
6309 /*
6310 * GY/GU and RY/RU should be the other way around according
6311 * to BSpec, but reality doesn't agree. Just set them up in
6312 * a way that results in the correct picture.
6313 */
6314 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6315 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6316
6317 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6318 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6319
6320 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6321 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6322
6323 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6324 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6325 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6326
6327 if (INTEL_INFO(dev)->gen > 6) {
6328 uint16_t postoff = 0;
6329
6330 if (intel_crtc->config.limited_color_range)
6331 postoff = (16 * (1 << 12) / 255) & 0x1fff;
6332
6333 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6334 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6335 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6336
6337 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6338 } else {
6339 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6340
6341 if (intel_crtc->config.limited_color_range)
6342 mode |= CSC_BLACK_SCREEN_OFFSET;
6343
6344 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6345 }
6346 }
6347
6348 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6349 {
6350 struct drm_device *dev = crtc->dev;
6351 struct drm_i915_private *dev_priv = dev->dev_private;
6352 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6353 enum pipe pipe = intel_crtc->pipe;
6354 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6355 uint32_t val;
6356
6357 val = 0;
6358
6359 if (IS_HASWELL(dev) && intel_crtc->config.dither)
6360 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6361
6362 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6363 val |= PIPECONF_INTERLACED_ILK;
6364 else
6365 val |= PIPECONF_PROGRESSIVE;
6366
6367 I915_WRITE(PIPECONF(cpu_transcoder), val);
6368 POSTING_READ(PIPECONF(cpu_transcoder));
6369
6370 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6371 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6372
6373 if (IS_BROADWELL(dev)) {
6374 val = 0;
6375
6376 switch (intel_crtc->config.pipe_bpp) {
6377 case 18:
6378 val |= PIPEMISC_DITHER_6_BPC;
6379 break;
6380 case 24:
6381 val |= PIPEMISC_DITHER_8_BPC;
6382 break;
6383 case 30:
6384 val |= PIPEMISC_DITHER_10_BPC;
6385 break;
6386 case 36:
6387 val |= PIPEMISC_DITHER_12_BPC;
6388 break;
6389 default:
6390 /* Case prevented by pipe_config_set_bpp. */
6391 BUG();
6392 }
6393
6394 if (intel_crtc->config.dither)
6395 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6396
6397 I915_WRITE(PIPEMISC(pipe), val);
6398 }
6399 }
6400
6401 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6402 intel_clock_t *clock,
6403 bool *has_reduced_clock,
6404 intel_clock_t *reduced_clock)
6405 {
6406 struct drm_device *dev = crtc->dev;
6407 struct drm_i915_private *dev_priv = dev->dev_private;
6408 struct intel_encoder *intel_encoder;
6409 int refclk;
6410 const intel_limit_t *limit;
6411 bool ret, is_lvds = false;
6412
6413 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6414 switch (intel_encoder->type) {
6415 case INTEL_OUTPUT_LVDS:
6416 is_lvds = true;
6417 break;
6418 }
6419 }
6420
6421 refclk = ironlake_get_refclk(crtc);
6422
6423 /*
6424 * Returns a set of divisors for the desired target clock with the given
6425 * refclk, or FALSE. The returned values represent the clock equation:
6426 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6427 */
6428 limit = intel_limit(crtc, refclk);
6429 ret = dev_priv->display.find_dpll(limit, crtc,
6430 to_intel_crtc(crtc)->config.port_clock,
6431 refclk, NULL, clock);
6432 if (!ret)
6433 return false;
6434
6435 if (is_lvds && dev_priv->lvds_downclock_avail) {
6436 /*
6437 * Ensure we match the reduced clock's P to the target clock.
6438 * If the clocks don't match, we can't switch the display clock
6439 * by using the FP0/FP1. In such case we will disable the LVDS
6440 * downclock feature.
6441 */
6442 *has_reduced_clock =
6443 dev_priv->display.find_dpll(limit, crtc,
6444 dev_priv->lvds_downclock,
6445 refclk, clock,
6446 reduced_clock);
6447 }
6448
6449 return true;
6450 }
6451
6452 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6453 {
6454 /*
6455 * Account for spread spectrum to avoid
6456 * oversubscribing the link. Max center spread
6457 * is 2.5%; use 5% for safety's sake.
6458 */
6459 u32 bps = target_clock * bpp * 21 / 20;
6460 return DIV_ROUND_UP(bps, link_bw * 8);
6461 }
6462
6463 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6464 {
6465 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6466 }
6467
6468 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6469 u32 *fp,
6470 intel_clock_t *reduced_clock, u32 *fp2)
6471 {
6472 struct drm_crtc *crtc = &intel_crtc->base;
6473 struct drm_device *dev = crtc->dev;
6474 struct drm_i915_private *dev_priv = dev->dev_private;
6475 struct intel_encoder *intel_encoder;
6476 uint32_t dpll;
6477 int factor, num_connectors = 0;
6478 bool is_lvds = false, is_sdvo = false;
6479
6480 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6481 switch (intel_encoder->type) {
6482 case INTEL_OUTPUT_LVDS:
6483 is_lvds = true;
6484 break;
6485 case INTEL_OUTPUT_SDVO:
6486 case INTEL_OUTPUT_HDMI:
6487 is_sdvo = true;
6488 break;
6489 }
6490
6491 num_connectors++;
6492 }
6493
6494 /* Enable autotuning of the PLL clock (if permissible) */
6495 factor = 21;
6496 if (is_lvds) {
6497 if ((intel_panel_use_ssc(dev_priv) &&
6498 dev_priv->vbt.lvds_ssc_freq == 100000) ||
6499 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6500 factor = 25;
6501 } else if (intel_crtc->config.sdvo_tv_clock)
6502 factor = 20;
6503
6504 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
6505 *fp |= FP_CB_TUNE;
6506
6507 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6508 *fp2 |= FP_CB_TUNE;
6509
6510 dpll = 0;
6511
6512 if (is_lvds)
6513 dpll |= DPLLB_MODE_LVDS;
6514 else
6515 dpll |= DPLLB_MODE_DAC_SERIAL;
6516
6517 dpll |= (intel_crtc->config.pixel_multiplier - 1)
6518 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6519
6520 if (is_sdvo)
6521 dpll |= DPLL_SDVO_HIGH_SPEED;
6522 if (intel_crtc->config.has_dp_encoder)
6523 dpll |= DPLL_SDVO_HIGH_SPEED;
6524
6525 /* compute bitmask from p1 value */
6526 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6527 /* also FPA1 */
6528 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6529
6530 switch (intel_crtc->config.dpll.p2) {
6531 case 5:
6532 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6533 break;
6534 case 7:
6535 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6536 break;
6537 case 10:
6538 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6539 break;
6540 case 14:
6541 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6542 break;
6543 }
6544
6545 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6546 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6547 else
6548 dpll |= PLL_REF_INPUT_DREFCLK;
6549
6550 return dpll | DPLL_VCO_ENABLE;
6551 }
6552
6553 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
6554 int x, int y,
6555 struct drm_framebuffer *fb)
6556 {
6557 struct drm_device *dev = crtc->dev;
6558 struct drm_i915_private *dev_priv = dev->dev_private;
6559 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6560 int pipe = intel_crtc->pipe;
6561 int plane = intel_crtc->plane;
6562 int num_connectors = 0;
6563 intel_clock_t clock, reduced_clock;
6564 u32 dpll = 0, fp = 0, fp2 = 0;
6565 bool ok, has_reduced_clock = false;
6566 bool is_lvds = false;
6567 struct intel_encoder *encoder;
6568 struct intel_shared_dpll *pll;
6569 int ret;
6570
6571 for_each_encoder_on_crtc(dev, crtc, encoder) {
6572 switch (encoder->type) {
6573 case INTEL_OUTPUT_LVDS:
6574 is_lvds = true;
6575 break;
6576 }
6577
6578 num_connectors++;
6579 }
6580
6581 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6582 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6583
6584 ok = ironlake_compute_clocks(crtc, &clock,
6585 &has_reduced_clock, &reduced_clock);
6586 if (!ok && !intel_crtc->config.clock_set) {
6587 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6588 return -EINVAL;
6589 }
6590 /* Compat-code for transition, will disappear. */
6591 if (!intel_crtc->config.clock_set) {
6592 intel_crtc->config.dpll.n = clock.n;
6593 intel_crtc->config.dpll.m1 = clock.m1;
6594 intel_crtc->config.dpll.m2 = clock.m2;
6595 intel_crtc->config.dpll.p1 = clock.p1;
6596 intel_crtc->config.dpll.p2 = clock.p2;
6597 }
6598
6599 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6600 if (intel_crtc->config.has_pch_encoder) {
6601 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
6602 if (has_reduced_clock)
6603 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
6604
6605 dpll = ironlake_compute_dpll(intel_crtc,
6606 &fp, &reduced_clock,
6607 has_reduced_clock ? &fp2 : NULL);
6608
6609 intel_crtc->config.dpll_hw_state.dpll = dpll;
6610 intel_crtc->config.dpll_hw_state.fp0 = fp;
6611 if (has_reduced_clock)
6612 intel_crtc->config.dpll_hw_state.fp1 = fp2;
6613 else
6614 intel_crtc->config.dpll_hw_state.fp1 = fp;
6615
6616 pll = intel_get_shared_dpll(intel_crtc);
6617 if (pll == NULL) {
6618 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6619 pipe_name(pipe));
6620 return -EINVAL;
6621 }
6622 } else
6623 intel_put_shared_dpll(intel_crtc);
6624
6625 if (intel_crtc->config.has_dp_encoder)
6626 intel_dp_set_m_n(intel_crtc);
6627
6628 if (is_lvds && has_reduced_clock && i915.powersave)
6629 intel_crtc->lowfreq_avail = true;
6630 else
6631 intel_crtc->lowfreq_avail = false;
6632
6633 intel_set_pipe_timings(intel_crtc);
6634
6635 if (intel_crtc->config.has_pch_encoder) {
6636 intel_cpu_transcoder_set_m_n(intel_crtc,
6637 &intel_crtc->config.fdi_m_n);
6638 }
6639
6640 ironlake_set_pipeconf(crtc);
6641
6642 /* Set up the display plane register */
6643 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
6644 POSTING_READ(DSPCNTR(plane));
6645
6646 ret = intel_pipe_set_base(crtc, x, y, fb);
6647
6648 return ret;
6649 }
6650
6651 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6652 struct intel_link_m_n *m_n)
6653 {
6654 struct drm_device *dev = crtc->base.dev;
6655 struct drm_i915_private *dev_priv = dev->dev_private;
6656 enum pipe pipe = crtc->pipe;
6657
6658 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6659 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6660 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6661 & ~TU_SIZE_MASK;
6662 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6663 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6664 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6665 }
6666
6667 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6668 enum transcoder transcoder,
6669 struct intel_link_m_n *m_n)
6670 {
6671 struct drm_device *dev = crtc->base.dev;
6672 struct drm_i915_private *dev_priv = dev->dev_private;
6673 enum pipe pipe = crtc->pipe;
6674
6675 if (INTEL_INFO(dev)->gen >= 5) {
6676 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6677 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6678 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6679 & ~TU_SIZE_MASK;
6680 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6681 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6682 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6683 } else {
6684 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6685 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6686 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6687 & ~TU_SIZE_MASK;
6688 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6689 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6690 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6691 }
6692 }
6693
6694 void intel_dp_get_m_n(struct intel_crtc *crtc,
6695 struct intel_crtc_config *pipe_config)
6696 {
6697 if (crtc->config.has_pch_encoder)
6698 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6699 else
6700 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6701 &pipe_config->dp_m_n);
6702 }
6703
6704 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6705 struct intel_crtc_config *pipe_config)
6706 {
6707 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6708 &pipe_config->fdi_m_n);
6709 }
6710
6711 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6712 struct intel_crtc_config *pipe_config)
6713 {
6714 struct drm_device *dev = crtc->base.dev;
6715 struct drm_i915_private *dev_priv = dev->dev_private;
6716 uint32_t tmp;
6717
6718 tmp = I915_READ(PF_CTL(crtc->pipe));
6719
6720 if (tmp & PF_ENABLE) {
6721 pipe_config->pch_pfit.enabled = true;
6722 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6723 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
6724
6725 /* We currently do not free assignements of panel fitters on
6726 * ivb/hsw (since we don't use the higher upscaling modes which
6727 * differentiates them) so just WARN about this case for now. */
6728 if (IS_GEN7(dev)) {
6729 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6730 PF_PIPE_SEL_IVB(crtc->pipe));
6731 }
6732 }
6733 }
6734
6735 static void ironlake_get_plane_config(struct intel_crtc *crtc,
6736 struct intel_plane_config *plane_config)
6737 {
6738 struct drm_device *dev = crtc->base.dev;
6739 struct drm_i915_private *dev_priv = dev->dev_private;
6740 u32 val, base, offset;
6741 int pipe = crtc->pipe, plane = crtc->plane;
6742 int fourcc, pixel_format;
6743 int aligned_height;
6744
6745 crtc->base.fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6746 if (!crtc->base.fb) {
6747 DRM_DEBUG_KMS("failed to alloc fb\n");
6748 return;
6749 }
6750
6751 val = I915_READ(DSPCNTR(plane));
6752
6753 if (INTEL_INFO(dev)->gen >= 4)
6754 if (val & DISPPLANE_TILED)
6755 plane_config->tiled = true;
6756
6757 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6758 fourcc = intel_format_to_fourcc(pixel_format);
6759 crtc->base.fb->pixel_format = fourcc;
6760 crtc->base.fb->bits_per_pixel =
6761 drm_format_plane_cpp(fourcc, 0) * 8;
6762
6763 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6764 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6765 offset = I915_READ(DSPOFFSET(plane));
6766 } else {
6767 if (plane_config->tiled)
6768 offset = I915_READ(DSPTILEOFF(plane));
6769 else
6770 offset = I915_READ(DSPLINOFF(plane));
6771 }
6772 plane_config->base = base;
6773
6774 val = I915_READ(PIPESRC(pipe));
6775 crtc->base.fb->width = ((val >> 16) & 0xfff) + 1;
6776 crtc->base.fb->height = ((val >> 0) & 0xfff) + 1;
6777
6778 val = I915_READ(DSPSTRIDE(pipe));
6779 crtc->base.fb->pitches[0] = val & 0xffffff80;
6780
6781 aligned_height = intel_align_height(dev, crtc->base.fb->height,
6782 plane_config->tiled);
6783
6784 plane_config->size = ALIGN(crtc->base.fb->pitches[0] *
6785 aligned_height, PAGE_SIZE);
6786
6787 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6788 pipe, plane, crtc->base.fb->width,
6789 crtc->base.fb->height,
6790 crtc->base.fb->bits_per_pixel, base,
6791 crtc->base.fb->pitches[0],
6792 plane_config->size);
6793 }
6794
6795 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6796 struct intel_crtc_config *pipe_config)
6797 {
6798 struct drm_device *dev = crtc->base.dev;
6799 struct drm_i915_private *dev_priv = dev->dev_private;
6800 uint32_t tmp;
6801
6802 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6803 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6804
6805 tmp = I915_READ(PIPECONF(crtc->pipe));
6806 if (!(tmp & PIPECONF_ENABLE))
6807 return false;
6808
6809 switch (tmp & PIPECONF_BPC_MASK) {
6810 case PIPECONF_6BPC:
6811 pipe_config->pipe_bpp = 18;
6812 break;
6813 case PIPECONF_8BPC:
6814 pipe_config->pipe_bpp = 24;
6815 break;
6816 case PIPECONF_10BPC:
6817 pipe_config->pipe_bpp = 30;
6818 break;
6819 case PIPECONF_12BPC:
6820 pipe_config->pipe_bpp = 36;
6821 break;
6822 default:
6823 break;
6824 }
6825
6826 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
6827 struct intel_shared_dpll *pll;
6828
6829 pipe_config->has_pch_encoder = true;
6830
6831 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6832 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6833 FDI_DP_PORT_WIDTH_SHIFT) + 1;
6834
6835 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6836
6837 if (HAS_PCH_IBX(dev_priv->dev)) {
6838 pipe_config->shared_dpll =
6839 (enum intel_dpll_id) crtc->pipe;
6840 } else {
6841 tmp = I915_READ(PCH_DPLL_SEL);
6842 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6843 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6844 else
6845 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6846 }
6847
6848 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6849
6850 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6851 &pipe_config->dpll_hw_state));
6852
6853 tmp = pipe_config->dpll_hw_state.dpll;
6854 pipe_config->pixel_multiplier =
6855 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6856 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6857
6858 ironlake_pch_clock_get(crtc, pipe_config);
6859 } else {
6860 pipe_config->pixel_multiplier = 1;
6861 }
6862
6863 intel_get_pipe_timings(crtc, pipe_config);
6864
6865 ironlake_get_pfit_config(crtc, pipe_config);
6866
6867 return true;
6868 }
6869
6870 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6871 {
6872 struct drm_device *dev = dev_priv->dev;
6873 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6874 struct intel_crtc *crtc;
6875 unsigned long irqflags;
6876 uint32_t val;
6877
6878 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6879 WARN(crtc->active, "CRTC for pipe %c enabled\n",
6880 pipe_name(crtc->pipe));
6881
6882 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6883 WARN(plls->spll_refcount, "SPLL enabled\n");
6884 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6885 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6886 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6887 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6888 "CPU PWM1 enabled\n");
6889 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6890 "CPU PWM2 enabled\n");
6891 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6892 "PCH PWM1 enabled\n");
6893 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6894 "Utility pin enabled\n");
6895 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6896
6897 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6898 val = I915_READ(DEIMR);
6899 WARN((val | DE_PCH_EVENT_IVB) != 0xffffffff,
6900 "Unexpected DEIMR bits enabled: 0x%x\n", val);
6901 val = I915_READ(SDEIMR);
6902 WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
6903 "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6904 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6905 }
6906
6907 /*
6908 * This function implements pieces of two sequences from BSpec:
6909 * - Sequence for display software to disable LCPLL
6910 * - Sequence for display software to allow package C8+
6911 * The steps implemented here are just the steps that actually touch the LCPLL
6912 * register. Callers should take care of disabling all the display engine
6913 * functions, doing the mode unset, fixing interrupts, etc.
6914 */
6915 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6916 bool switch_to_fclk, bool allow_power_down)
6917 {
6918 uint32_t val;
6919
6920 assert_can_disable_lcpll(dev_priv);
6921
6922 val = I915_READ(LCPLL_CTL);
6923
6924 if (switch_to_fclk) {
6925 val |= LCPLL_CD_SOURCE_FCLK;
6926 I915_WRITE(LCPLL_CTL, val);
6927
6928 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6929 LCPLL_CD_SOURCE_FCLK_DONE, 1))
6930 DRM_ERROR("Switching to FCLK failed\n");
6931
6932 val = I915_READ(LCPLL_CTL);
6933 }
6934
6935 val |= LCPLL_PLL_DISABLE;
6936 I915_WRITE(LCPLL_CTL, val);
6937 POSTING_READ(LCPLL_CTL);
6938
6939 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6940 DRM_ERROR("LCPLL still locked\n");
6941
6942 val = I915_READ(D_COMP);
6943 val |= D_COMP_COMP_DISABLE;
6944 mutex_lock(&dev_priv->rps.hw_lock);
6945 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6946 DRM_ERROR("Failed to disable D_COMP\n");
6947 mutex_unlock(&dev_priv->rps.hw_lock);
6948 POSTING_READ(D_COMP);
6949 ndelay(100);
6950
6951 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6952 DRM_ERROR("D_COMP RCOMP still in progress\n");
6953
6954 if (allow_power_down) {
6955 val = I915_READ(LCPLL_CTL);
6956 val |= LCPLL_POWER_DOWN_ALLOW;
6957 I915_WRITE(LCPLL_CTL, val);
6958 POSTING_READ(LCPLL_CTL);
6959 }
6960 }
6961
6962 /*
6963 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6964 * source.
6965 */
6966 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6967 {
6968 uint32_t val;
6969 unsigned long irqflags;
6970
6971 val = I915_READ(LCPLL_CTL);
6972
6973 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6974 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6975 return;
6976
6977 /*
6978 * Make sure we're not on PC8 state before disabling PC8, otherwise
6979 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
6980 *
6981 * The other problem is that hsw_restore_lcpll() is called as part of
6982 * the runtime PM resume sequence, so we can't just call
6983 * gen6_gt_force_wake_get() because that function calls
6984 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
6985 * while we are on the resume sequence. So to solve this problem we have
6986 * to call special forcewake code that doesn't touch runtime PM and
6987 * doesn't enable the forcewake delayed work.
6988 */
6989 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
6990 if (dev_priv->uncore.forcewake_count++ == 0)
6991 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
6992 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
6993
6994 if (val & LCPLL_POWER_DOWN_ALLOW) {
6995 val &= ~LCPLL_POWER_DOWN_ALLOW;
6996 I915_WRITE(LCPLL_CTL, val);
6997 POSTING_READ(LCPLL_CTL);
6998 }
6999
7000 val = I915_READ(D_COMP);
7001 val |= D_COMP_COMP_FORCE;
7002 val &= ~D_COMP_COMP_DISABLE;
7003 mutex_lock(&dev_priv->rps.hw_lock);
7004 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
7005 DRM_ERROR("Failed to enable D_COMP\n");
7006 mutex_unlock(&dev_priv->rps.hw_lock);
7007 POSTING_READ(D_COMP);
7008
7009 val = I915_READ(LCPLL_CTL);
7010 val &= ~LCPLL_PLL_DISABLE;
7011 I915_WRITE(LCPLL_CTL, val);
7012
7013 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7014 DRM_ERROR("LCPLL not locked yet\n");
7015
7016 if (val & LCPLL_CD_SOURCE_FCLK) {
7017 val = I915_READ(LCPLL_CTL);
7018 val &= ~LCPLL_CD_SOURCE_FCLK;
7019 I915_WRITE(LCPLL_CTL, val);
7020
7021 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7022 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7023 DRM_ERROR("Switching back to LCPLL failed\n");
7024 }
7025
7026 /* See the big comment above. */
7027 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7028 if (--dev_priv->uncore.forcewake_count == 0)
7029 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7030 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7031 }
7032
7033 /*
7034 * Package states C8 and deeper are really deep PC states that can only be
7035 * reached when all the devices on the system allow it, so even if the graphics
7036 * device allows PC8+, it doesn't mean the system will actually get to these
7037 * states. Our driver only allows PC8+ when going into runtime PM.
7038 *
7039 * The requirements for PC8+ are that all the outputs are disabled, the power
7040 * well is disabled and most interrupts are disabled, and these are also
7041 * requirements for runtime PM. When these conditions are met, we manually do
7042 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7043 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7044 * hang the machine.
7045 *
7046 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7047 * the state of some registers, so when we come back from PC8+ we need to
7048 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7049 * need to take care of the registers kept by RC6. Notice that this happens even
7050 * if we don't put the device in PCI D3 state (which is what currently happens
7051 * because of the runtime PM support).
7052 *
7053 * For more, read "Display Sequences for Package C8" on the hardware
7054 * documentation.
7055 */
7056 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7057 {
7058 struct drm_device *dev = dev_priv->dev;
7059 uint32_t val;
7060
7061 WARN_ON(!HAS_PC8(dev));
7062
7063 DRM_DEBUG_KMS("Enabling package C8+\n");
7064
7065 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7066 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7067 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7068 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7069 }
7070
7071 lpt_disable_clkout_dp(dev);
7072 hsw_runtime_pm_disable_interrupts(dev);
7073 hsw_disable_lcpll(dev_priv, true, true);
7074 }
7075
7076 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7077 {
7078 struct drm_device *dev = dev_priv->dev;
7079 uint32_t val;
7080
7081 WARN_ON(!HAS_PC8(dev));
7082
7083 DRM_DEBUG_KMS("Disabling package C8+\n");
7084
7085 hsw_restore_lcpll(dev_priv);
7086 hsw_runtime_pm_restore_interrupts(dev);
7087 lpt_init_pch_refclk(dev);
7088
7089 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7090 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7091 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7092 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7093 }
7094
7095 intel_prepare_ddi(dev);
7096 i915_gem_init_swizzling(dev);
7097 mutex_lock(&dev_priv->rps.hw_lock);
7098 gen6_update_ring_freq(dev);
7099 mutex_unlock(&dev_priv->rps.hw_lock);
7100 }
7101
7102 static void haswell_modeset_global_resources(struct drm_device *dev)
7103 {
7104 modeset_update_crtc_power_domains(dev);
7105 }
7106
7107 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7108 int x, int y,
7109 struct drm_framebuffer *fb)
7110 {
7111 struct drm_device *dev = crtc->dev;
7112 struct drm_i915_private *dev_priv = dev->dev_private;
7113 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7114 int plane = intel_crtc->plane;
7115 int ret;
7116
7117 if (!intel_ddi_pll_select(intel_crtc))
7118 return -EINVAL;
7119 intel_ddi_pll_enable(intel_crtc);
7120
7121 if (intel_crtc->config.has_dp_encoder)
7122 intel_dp_set_m_n(intel_crtc);
7123
7124 intel_crtc->lowfreq_avail = false;
7125
7126 intel_set_pipe_timings(intel_crtc);
7127
7128 if (intel_crtc->config.has_pch_encoder) {
7129 intel_cpu_transcoder_set_m_n(intel_crtc,
7130 &intel_crtc->config.fdi_m_n);
7131 }
7132
7133 haswell_set_pipeconf(crtc);
7134
7135 intel_set_pipe_csc(crtc);
7136
7137 /* Set up the display plane register */
7138 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
7139 POSTING_READ(DSPCNTR(plane));
7140
7141 ret = intel_pipe_set_base(crtc, x, y, fb);
7142
7143 return ret;
7144 }
7145
7146 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7147 struct intel_crtc_config *pipe_config)
7148 {
7149 struct drm_device *dev = crtc->base.dev;
7150 struct drm_i915_private *dev_priv = dev->dev_private;
7151 enum intel_display_power_domain pfit_domain;
7152 uint32_t tmp;
7153
7154 if (!intel_display_power_enabled(dev_priv,
7155 POWER_DOMAIN_PIPE(crtc->pipe)))
7156 return false;
7157
7158 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7159 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7160
7161 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7162 if (tmp & TRANS_DDI_FUNC_ENABLE) {
7163 enum pipe trans_edp_pipe;
7164 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7165 default:
7166 WARN(1, "unknown pipe linked to edp transcoder\n");
7167 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7168 case TRANS_DDI_EDP_INPUT_A_ON:
7169 trans_edp_pipe = PIPE_A;
7170 break;
7171 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7172 trans_edp_pipe = PIPE_B;
7173 break;
7174 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7175 trans_edp_pipe = PIPE_C;
7176 break;
7177 }
7178
7179 if (trans_edp_pipe == crtc->pipe)
7180 pipe_config->cpu_transcoder = TRANSCODER_EDP;
7181 }
7182
7183 if (!intel_display_power_enabled(dev_priv,
7184 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7185 return false;
7186
7187 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7188 if (!(tmp & PIPECONF_ENABLE))
7189 return false;
7190
7191 /*
7192 * Haswell has only FDI/PCH transcoder A. It is which is connected to
7193 * DDI E. So just check whether this pipe is wired to DDI E and whether
7194 * the PCH transcoder is on.
7195 */
7196 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7197 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
7198 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7199 pipe_config->has_pch_encoder = true;
7200
7201 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7202 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7203 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7204
7205 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7206 }
7207
7208 intel_get_pipe_timings(crtc, pipe_config);
7209
7210 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7211 if (intel_display_power_enabled(dev_priv, pfit_domain))
7212 ironlake_get_pfit_config(crtc, pipe_config);
7213
7214 if (IS_HASWELL(dev))
7215 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7216 (I915_READ(IPS_CTL) & IPS_ENABLE);
7217
7218 pipe_config->pixel_multiplier = 1;
7219
7220 return true;
7221 }
7222
7223 static int intel_crtc_mode_set(struct drm_crtc *crtc,
7224 int x, int y,
7225 struct drm_framebuffer *fb)
7226 {
7227 struct drm_device *dev = crtc->dev;
7228 struct drm_i915_private *dev_priv = dev->dev_private;
7229 struct intel_encoder *encoder;
7230 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7231 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
7232 int pipe = intel_crtc->pipe;
7233 int ret;
7234
7235 drm_vblank_pre_modeset(dev, pipe);
7236
7237 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
7238
7239 drm_vblank_post_modeset(dev, pipe);
7240
7241 if (ret != 0)
7242 return ret;
7243
7244 for_each_encoder_on_crtc(dev, crtc, encoder) {
7245 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7246 encoder->base.base.id,
7247 drm_get_encoder_name(&encoder->base),
7248 mode->base.id, mode->name);
7249 encoder->mode_set(encoder);
7250 }
7251
7252 return 0;
7253 }
7254
7255 static struct {
7256 int clock;
7257 u32 config;
7258 } hdmi_audio_clock[] = {
7259 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7260 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7261 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7262 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7263 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7264 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7265 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7266 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7267 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7268 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7269 };
7270
7271 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7272 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7273 {
7274 int i;
7275
7276 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7277 if (mode->clock == hdmi_audio_clock[i].clock)
7278 break;
7279 }
7280
7281 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7282 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7283 i = 1;
7284 }
7285
7286 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7287 hdmi_audio_clock[i].clock,
7288 hdmi_audio_clock[i].config);
7289
7290 return hdmi_audio_clock[i].config;
7291 }
7292
7293 static bool intel_eld_uptodate(struct drm_connector *connector,
7294 int reg_eldv, uint32_t bits_eldv,
7295 int reg_elda, uint32_t bits_elda,
7296 int reg_edid)
7297 {
7298 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7299 uint8_t *eld = connector->eld;
7300 uint32_t i;
7301
7302 i = I915_READ(reg_eldv);
7303 i &= bits_eldv;
7304
7305 if (!eld[0])
7306 return !i;
7307
7308 if (!i)
7309 return false;
7310
7311 i = I915_READ(reg_elda);
7312 i &= ~bits_elda;
7313 I915_WRITE(reg_elda, i);
7314
7315 for (i = 0; i < eld[2]; i++)
7316 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7317 return false;
7318
7319 return true;
7320 }
7321
7322 static void g4x_write_eld(struct drm_connector *connector,
7323 struct drm_crtc *crtc,
7324 struct drm_display_mode *mode)
7325 {
7326 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7327 uint8_t *eld = connector->eld;
7328 uint32_t eldv;
7329 uint32_t len;
7330 uint32_t i;
7331
7332 i = I915_READ(G4X_AUD_VID_DID);
7333
7334 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7335 eldv = G4X_ELDV_DEVCL_DEVBLC;
7336 else
7337 eldv = G4X_ELDV_DEVCTG;
7338
7339 if (intel_eld_uptodate(connector,
7340 G4X_AUD_CNTL_ST, eldv,
7341 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7342 G4X_HDMIW_HDMIEDID))
7343 return;
7344
7345 i = I915_READ(G4X_AUD_CNTL_ST);
7346 i &= ~(eldv | G4X_ELD_ADDR);
7347 len = (i >> 9) & 0x1f; /* ELD buffer size */
7348 I915_WRITE(G4X_AUD_CNTL_ST, i);
7349
7350 if (!eld[0])
7351 return;
7352
7353 len = min_t(uint8_t, eld[2], len);
7354 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7355 for (i = 0; i < len; i++)
7356 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7357
7358 i = I915_READ(G4X_AUD_CNTL_ST);
7359 i |= eldv;
7360 I915_WRITE(G4X_AUD_CNTL_ST, i);
7361 }
7362
7363 static void haswell_write_eld(struct drm_connector *connector,
7364 struct drm_crtc *crtc,
7365 struct drm_display_mode *mode)
7366 {
7367 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7368 uint8_t *eld = connector->eld;
7369 struct drm_device *dev = crtc->dev;
7370 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7371 uint32_t eldv;
7372 uint32_t i;
7373 int len;
7374 int pipe = to_intel_crtc(crtc)->pipe;
7375 int tmp;
7376
7377 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7378 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7379 int aud_config = HSW_AUD_CFG(pipe);
7380 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7381
7382
7383 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
7384
7385 /* Audio output enable */
7386 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7387 tmp = I915_READ(aud_cntrl_st2);
7388 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7389 I915_WRITE(aud_cntrl_st2, tmp);
7390
7391 /* Wait for 1 vertical blank */
7392 intel_wait_for_vblank(dev, pipe);
7393
7394 /* Set ELD valid state */
7395 tmp = I915_READ(aud_cntrl_st2);
7396 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7397 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7398 I915_WRITE(aud_cntrl_st2, tmp);
7399 tmp = I915_READ(aud_cntrl_st2);
7400 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7401
7402 /* Enable HDMI mode */
7403 tmp = I915_READ(aud_config);
7404 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7405 /* clear N_programing_enable and N_value_index */
7406 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7407 I915_WRITE(aud_config, tmp);
7408
7409 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7410
7411 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7412 intel_crtc->eld_vld = true;
7413
7414 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7415 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7416 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7417 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7418 } else {
7419 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7420 }
7421
7422 if (intel_eld_uptodate(connector,
7423 aud_cntrl_st2, eldv,
7424 aud_cntl_st, IBX_ELD_ADDRESS,
7425 hdmiw_hdmiedid))
7426 return;
7427
7428 i = I915_READ(aud_cntrl_st2);
7429 i &= ~eldv;
7430 I915_WRITE(aud_cntrl_st2, i);
7431
7432 if (!eld[0])
7433 return;
7434
7435 i = I915_READ(aud_cntl_st);
7436 i &= ~IBX_ELD_ADDRESS;
7437 I915_WRITE(aud_cntl_st, i);
7438 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
7439 DRM_DEBUG_DRIVER("port num:%d\n", i);
7440
7441 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7442 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7443 for (i = 0; i < len; i++)
7444 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7445
7446 i = I915_READ(aud_cntrl_st2);
7447 i |= eldv;
7448 I915_WRITE(aud_cntrl_st2, i);
7449
7450 }
7451
7452 static void ironlake_write_eld(struct drm_connector *connector,
7453 struct drm_crtc *crtc,
7454 struct drm_display_mode *mode)
7455 {
7456 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7457 uint8_t *eld = connector->eld;
7458 uint32_t eldv;
7459 uint32_t i;
7460 int len;
7461 int hdmiw_hdmiedid;
7462 int aud_config;
7463 int aud_cntl_st;
7464 int aud_cntrl_st2;
7465 int pipe = to_intel_crtc(crtc)->pipe;
7466
7467 if (HAS_PCH_IBX(connector->dev)) {
7468 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7469 aud_config = IBX_AUD_CFG(pipe);
7470 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7471 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7472 } else if (IS_VALLEYVIEW(connector->dev)) {
7473 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7474 aud_config = VLV_AUD_CFG(pipe);
7475 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7476 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7477 } else {
7478 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7479 aud_config = CPT_AUD_CFG(pipe);
7480 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7481 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7482 }
7483
7484 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7485
7486 if (IS_VALLEYVIEW(connector->dev)) {
7487 struct intel_encoder *intel_encoder;
7488 struct intel_digital_port *intel_dig_port;
7489
7490 intel_encoder = intel_attached_encoder(connector);
7491 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7492 i = intel_dig_port->port;
7493 } else {
7494 i = I915_READ(aud_cntl_st);
7495 i = (i >> 29) & DIP_PORT_SEL_MASK;
7496 /* DIP_Port_Select, 0x1 = PortB */
7497 }
7498
7499 if (!i) {
7500 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7501 /* operate blindly on all ports */
7502 eldv = IBX_ELD_VALIDB;
7503 eldv |= IBX_ELD_VALIDB << 4;
7504 eldv |= IBX_ELD_VALIDB << 8;
7505 } else {
7506 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7507 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7508 }
7509
7510 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7511 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7512 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7513 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7514 } else {
7515 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7516 }
7517
7518 if (intel_eld_uptodate(connector,
7519 aud_cntrl_st2, eldv,
7520 aud_cntl_st, IBX_ELD_ADDRESS,
7521 hdmiw_hdmiedid))
7522 return;
7523
7524 i = I915_READ(aud_cntrl_st2);
7525 i &= ~eldv;
7526 I915_WRITE(aud_cntrl_st2, i);
7527
7528 if (!eld[0])
7529 return;
7530
7531 i = I915_READ(aud_cntl_st);
7532 i &= ~IBX_ELD_ADDRESS;
7533 I915_WRITE(aud_cntl_st, i);
7534
7535 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7536 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7537 for (i = 0; i < len; i++)
7538 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7539
7540 i = I915_READ(aud_cntrl_st2);
7541 i |= eldv;
7542 I915_WRITE(aud_cntrl_st2, i);
7543 }
7544
7545 void intel_write_eld(struct drm_encoder *encoder,
7546 struct drm_display_mode *mode)
7547 {
7548 struct drm_crtc *crtc = encoder->crtc;
7549 struct drm_connector *connector;
7550 struct drm_device *dev = encoder->dev;
7551 struct drm_i915_private *dev_priv = dev->dev_private;
7552
7553 connector = drm_select_eld(encoder, mode);
7554 if (!connector)
7555 return;
7556
7557 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7558 connector->base.id,
7559 drm_get_connector_name(connector),
7560 connector->encoder->base.id,
7561 drm_get_encoder_name(connector->encoder));
7562
7563 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7564
7565 if (dev_priv->display.write_eld)
7566 dev_priv->display.write_eld(connector, crtc, mode);
7567 }
7568
7569 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7570 {
7571 struct drm_device *dev = crtc->dev;
7572 struct drm_i915_private *dev_priv = dev->dev_private;
7573 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7574 bool visible = base != 0;
7575 u32 cntl;
7576
7577 if (intel_crtc->cursor_visible == visible)
7578 return;
7579
7580 cntl = I915_READ(_CURACNTR);
7581 if (visible) {
7582 /* On these chipsets we can only modify the base whilst
7583 * the cursor is disabled.
7584 */
7585 I915_WRITE(_CURABASE, base);
7586
7587 cntl &= ~(CURSOR_FORMAT_MASK);
7588 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7589 cntl |= CURSOR_ENABLE |
7590 CURSOR_GAMMA_ENABLE |
7591 CURSOR_FORMAT_ARGB;
7592 } else
7593 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
7594 I915_WRITE(_CURACNTR, cntl);
7595
7596 intel_crtc->cursor_visible = visible;
7597 }
7598
7599 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7600 {
7601 struct drm_device *dev = crtc->dev;
7602 struct drm_i915_private *dev_priv = dev->dev_private;
7603 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7604 int pipe = intel_crtc->pipe;
7605 bool visible = base != 0;
7606
7607 if (intel_crtc->cursor_visible != visible) {
7608 int16_t width = intel_crtc->cursor_width;
7609 uint32_t cntl = I915_READ(CURCNTR(pipe));
7610 if (base) {
7611 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7612 cntl |= MCURSOR_GAMMA_ENABLE;
7613
7614 switch (width) {
7615 case 64:
7616 cntl |= CURSOR_MODE_64_ARGB_AX;
7617 break;
7618 case 128:
7619 cntl |= CURSOR_MODE_128_ARGB_AX;
7620 break;
7621 case 256:
7622 cntl |= CURSOR_MODE_256_ARGB_AX;
7623 break;
7624 default:
7625 WARN_ON(1);
7626 return;
7627 }
7628 cntl |= pipe << 28; /* Connect to correct pipe */
7629 } else {
7630 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7631 cntl |= CURSOR_MODE_DISABLE;
7632 }
7633 I915_WRITE(CURCNTR(pipe), cntl);
7634
7635 intel_crtc->cursor_visible = visible;
7636 }
7637 /* and commit changes on next vblank */
7638 POSTING_READ(CURCNTR(pipe));
7639 I915_WRITE(CURBASE(pipe), base);
7640 POSTING_READ(CURBASE(pipe));
7641 }
7642
7643 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7644 {
7645 struct drm_device *dev = crtc->dev;
7646 struct drm_i915_private *dev_priv = dev->dev_private;
7647 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7648 int pipe = intel_crtc->pipe;
7649 bool visible = base != 0;
7650
7651 if (intel_crtc->cursor_visible != visible) {
7652 int16_t width = intel_crtc->cursor_width;
7653 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7654 if (base) {
7655 cntl &= ~CURSOR_MODE;
7656 cntl |= MCURSOR_GAMMA_ENABLE;
7657 switch (width) {
7658 case 64:
7659 cntl |= CURSOR_MODE_64_ARGB_AX;
7660 break;
7661 case 128:
7662 cntl |= CURSOR_MODE_128_ARGB_AX;
7663 break;
7664 case 256:
7665 cntl |= CURSOR_MODE_256_ARGB_AX;
7666 break;
7667 default:
7668 WARN_ON(1);
7669 return;
7670 }
7671 } else {
7672 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7673 cntl |= CURSOR_MODE_DISABLE;
7674 }
7675 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7676 cntl |= CURSOR_PIPE_CSC_ENABLE;
7677 cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7678 }
7679 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7680
7681 intel_crtc->cursor_visible = visible;
7682 }
7683 /* and commit changes on next vblank */
7684 POSTING_READ(CURCNTR_IVB(pipe));
7685 I915_WRITE(CURBASE_IVB(pipe), base);
7686 POSTING_READ(CURBASE_IVB(pipe));
7687 }
7688
7689 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7690 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7691 bool on)
7692 {
7693 struct drm_device *dev = crtc->dev;
7694 struct drm_i915_private *dev_priv = dev->dev_private;
7695 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7696 int pipe = intel_crtc->pipe;
7697 int x = intel_crtc->cursor_x;
7698 int y = intel_crtc->cursor_y;
7699 u32 base = 0, pos = 0;
7700 bool visible;
7701
7702 if (on)
7703 base = intel_crtc->cursor_addr;
7704
7705 if (x >= intel_crtc->config.pipe_src_w)
7706 base = 0;
7707
7708 if (y >= intel_crtc->config.pipe_src_h)
7709 base = 0;
7710
7711 if (x < 0) {
7712 if (x + intel_crtc->cursor_width <= 0)
7713 base = 0;
7714
7715 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7716 x = -x;
7717 }
7718 pos |= x << CURSOR_X_SHIFT;
7719
7720 if (y < 0) {
7721 if (y + intel_crtc->cursor_height <= 0)
7722 base = 0;
7723
7724 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7725 y = -y;
7726 }
7727 pos |= y << CURSOR_Y_SHIFT;
7728
7729 visible = base != 0;
7730 if (!visible && !intel_crtc->cursor_visible)
7731 return;
7732
7733 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7734 I915_WRITE(CURPOS_IVB(pipe), pos);
7735 ivb_update_cursor(crtc, base);
7736 } else {
7737 I915_WRITE(CURPOS(pipe), pos);
7738 if (IS_845G(dev) || IS_I865G(dev))
7739 i845_update_cursor(crtc, base);
7740 else
7741 i9xx_update_cursor(crtc, base);
7742 }
7743 }
7744
7745 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
7746 struct drm_file *file,
7747 uint32_t handle,
7748 uint32_t width, uint32_t height)
7749 {
7750 struct drm_device *dev = crtc->dev;
7751 struct drm_i915_private *dev_priv = dev->dev_private;
7752 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7753 struct drm_i915_gem_object *obj;
7754 unsigned old_width;
7755 uint32_t addr;
7756 int ret;
7757
7758 /* if we want to turn off the cursor ignore width and height */
7759 if (!handle) {
7760 DRM_DEBUG_KMS("cursor off\n");
7761 addr = 0;
7762 obj = NULL;
7763 mutex_lock(&dev->struct_mutex);
7764 goto finish;
7765 }
7766
7767 /* Check for which cursor types we support */
7768 if (!((width == 64 && height == 64) ||
7769 (width == 128 && height == 128 && !IS_GEN2(dev)) ||
7770 (width == 256 && height == 256 && !IS_GEN2(dev)))) {
7771 DRM_DEBUG("Cursor dimension not supported\n");
7772 return -EINVAL;
7773 }
7774
7775 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
7776 if (&obj->base == NULL)
7777 return -ENOENT;
7778
7779 if (obj->base.size < width * height * 4) {
7780 DRM_DEBUG_KMS("buffer is to small\n");
7781 ret = -ENOMEM;
7782 goto fail;
7783 }
7784
7785 /* we only need to pin inside GTT if cursor is non-phy */
7786 mutex_lock(&dev->struct_mutex);
7787 if (!INTEL_INFO(dev)->cursor_needs_physical) {
7788 unsigned alignment;
7789
7790 if (obj->tiling_mode) {
7791 DRM_DEBUG_KMS("cursor cannot be tiled\n");
7792 ret = -EINVAL;
7793 goto fail_locked;
7794 }
7795
7796 /* Note that the w/a also requires 2 PTE of padding following
7797 * the bo. We currently fill all unused PTE with the shadow
7798 * page and so we should always have valid PTE following the
7799 * cursor preventing the VT-d warning.
7800 */
7801 alignment = 0;
7802 if (need_vtd_wa(dev))
7803 alignment = 64*1024;
7804
7805 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
7806 if (ret) {
7807 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
7808 goto fail_locked;
7809 }
7810
7811 ret = i915_gem_object_put_fence(obj);
7812 if (ret) {
7813 DRM_DEBUG_KMS("failed to release fence for cursor");
7814 goto fail_unpin;
7815 }
7816
7817 addr = i915_gem_obj_ggtt_offset(obj);
7818 } else {
7819 int align = IS_I830(dev) ? 16 * 1024 : 256;
7820 ret = i915_gem_attach_phys_object(dev, obj,
7821 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7822 align);
7823 if (ret) {
7824 DRM_DEBUG_KMS("failed to attach phys object\n");
7825 goto fail_locked;
7826 }
7827 addr = obj->phys_obj->handle->busaddr;
7828 }
7829
7830 if (IS_GEN2(dev))
7831 I915_WRITE(CURSIZE, (height << 12) | width);
7832
7833 finish:
7834 if (intel_crtc->cursor_bo) {
7835 if (INTEL_INFO(dev)->cursor_needs_physical) {
7836 if (intel_crtc->cursor_bo != obj)
7837 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7838 } else
7839 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
7840 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
7841 }
7842
7843 mutex_unlock(&dev->struct_mutex);
7844
7845 old_width = intel_crtc->cursor_width;
7846
7847 intel_crtc->cursor_addr = addr;
7848 intel_crtc->cursor_bo = obj;
7849 intel_crtc->cursor_width = width;
7850 intel_crtc->cursor_height = height;
7851
7852 if (intel_crtc->active) {
7853 if (old_width != width)
7854 intel_update_watermarks(crtc);
7855 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7856 }
7857
7858 return 0;
7859 fail_unpin:
7860 i915_gem_object_unpin_from_display_plane(obj);
7861 fail_locked:
7862 mutex_unlock(&dev->struct_mutex);
7863 fail:
7864 drm_gem_object_unreference_unlocked(&obj->base);
7865 return ret;
7866 }
7867
7868 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7869 {
7870 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7871
7872 intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX);
7873 intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX);
7874
7875 if (intel_crtc->active)
7876 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7877
7878 return 0;
7879 }
7880
7881 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7882 u16 *blue, uint32_t start, uint32_t size)
7883 {
7884 int end = (start + size > 256) ? 256 : start + size, i;
7885 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7886
7887 for (i = start; i < end; i++) {
7888 intel_crtc->lut_r[i] = red[i] >> 8;
7889 intel_crtc->lut_g[i] = green[i] >> 8;
7890 intel_crtc->lut_b[i] = blue[i] >> 8;
7891 }
7892
7893 intel_crtc_load_lut(crtc);
7894 }
7895
7896 /* VESA 640x480x72Hz mode to set on the pipe */
7897 static struct drm_display_mode load_detect_mode = {
7898 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7899 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7900 };
7901
7902 struct drm_framebuffer *
7903 __intel_framebuffer_create(struct drm_device *dev,
7904 struct drm_mode_fb_cmd2 *mode_cmd,
7905 struct drm_i915_gem_object *obj)
7906 {
7907 struct intel_framebuffer *intel_fb;
7908 int ret;
7909
7910 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7911 if (!intel_fb) {
7912 drm_gem_object_unreference_unlocked(&obj->base);
7913 return ERR_PTR(-ENOMEM);
7914 }
7915
7916 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7917 if (ret)
7918 goto err;
7919
7920 return &intel_fb->base;
7921 err:
7922 drm_gem_object_unreference_unlocked(&obj->base);
7923 kfree(intel_fb);
7924
7925 return ERR_PTR(ret);
7926 }
7927
7928 static struct drm_framebuffer *
7929 intel_framebuffer_create(struct drm_device *dev,
7930 struct drm_mode_fb_cmd2 *mode_cmd,
7931 struct drm_i915_gem_object *obj)
7932 {
7933 struct drm_framebuffer *fb;
7934 int ret;
7935
7936 ret = i915_mutex_lock_interruptible(dev);
7937 if (ret)
7938 return ERR_PTR(ret);
7939 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
7940 mutex_unlock(&dev->struct_mutex);
7941
7942 return fb;
7943 }
7944
7945 static u32
7946 intel_framebuffer_pitch_for_width(int width, int bpp)
7947 {
7948 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7949 return ALIGN(pitch, 64);
7950 }
7951
7952 static u32
7953 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7954 {
7955 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7956 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7957 }
7958
7959 static struct drm_framebuffer *
7960 intel_framebuffer_create_for_mode(struct drm_device *dev,
7961 struct drm_display_mode *mode,
7962 int depth, int bpp)
7963 {
7964 struct drm_i915_gem_object *obj;
7965 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
7966
7967 obj = i915_gem_alloc_object(dev,
7968 intel_framebuffer_size_for_mode(mode, bpp));
7969 if (obj == NULL)
7970 return ERR_PTR(-ENOMEM);
7971
7972 mode_cmd.width = mode->hdisplay;
7973 mode_cmd.height = mode->vdisplay;
7974 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7975 bpp);
7976 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
7977
7978 return intel_framebuffer_create(dev, &mode_cmd, obj);
7979 }
7980
7981 static struct drm_framebuffer *
7982 mode_fits_in_fbdev(struct drm_device *dev,
7983 struct drm_display_mode *mode)
7984 {
7985 #ifdef CONFIG_DRM_I915_FBDEV
7986 struct drm_i915_private *dev_priv = dev->dev_private;
7987 struct drm_i915_gem_object *obj;
7988 struct drm_framebuffer *fb;
7989
7990 if (!dev_priv->fbdev)
7991 return NULL;
7992
7993 if (!dev_priv->fbdev->fb)
7994 return NULL;
7995
7996 obj = dev_priv->fbdev->fb->obj;
7997 BUG_ON(!obj);
7998
7999 fb = &dev_priv->fbdev->fb->base;
8000 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8001 fb->bits_per_pixel))
8002 return NULL;
8003
8004 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8005 return NULL;
8006
8007 return fb;
8008 #else
8009 return NULL;
8010 #endif
8011 }
8012
8013 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8014 struct drm_display_mode *mode,
8015 struct intel_load_detect_pipe *old)
8016 {
8017 struct intel_crtc *intel_crtc;
8018 struct intel_encoder *intel_encoder =
8019 intel_attached_encoder(connector);
8020 struct drm_crtc *possible_crtc;
8021 struct drm_encoder *encoder = &intel_encoder->base;
8022 struct drm_crtc *crtc = NULL;
8023 struct drm_device *dev = encoder->dev;
8024 struct drm_framebuffer *fb;
8025 int i = -1;
8026
8027 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8028 connector->base.id, drm_get_connector_name(connector),
8029 encoder->base.id, drm_get_encoder_name(encoder));
8030
8031 /*
8032 * Algorithm gets a little messy:
8033 *
8034 * - if the connector already has an assigned crtc, use it (but make
8035 * sure it's on first)
8036 *
8037 * - try to find the first unused crtc that can drive this connector,
8038 * and use that if we find one
8039 */
8040
8041 /* See if we already have a CRTC for this connector */
8042 if (encoder->crtc) {
8043 crtc = encoder->crtc;
8044
8045 mutex_lock(&crtc->mutex);
8046
8047 old->dpms_mode = connector->dpms;
8048 old->load_detect_temp = false;
8049
8050 /* Make sure the crtc and connector are running */
8051 if (connector->dpms != DRM_MODE_DPMS_ON)
8052 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8053
8054 return true;
8055 }
8056
8057 /* Find an unused one (if possible) */
8058 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
8059 i++;
8060 if (!(encoder->possible_crtcs & (1 << i)))
8061 continue;
8062 if (!possible_crtc->enabled) {
8063 crtc = possible_crtc;
8064 break;
8065 }
8066 }
8067
8068 /*
8069 * If we didn't find an unused CRTC, don't use any.
8070 */
8071 if (!crtc) {
8072 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8073 return false;
8074 }
8075
8076 mutex_lock(&crtc->mutex);
8077 intel_encoder->new_crtc = to_intel_crtc(crtc);
8078 to_intel_connector(connector)->new_encoder = intel_encoder;
8079
8080 intel_crtc = to_intel_crtc(crtc);
8081 intel_crtc->new_enabled = true;
8082 intel_crtc->new_config = &intel_crtc->config;
8083 old->dpms_mode = connector->dpms;
8084 old->load_detect_temp = true;
8085 old->release_fb = NULL;
8086
8087 if (!mode)
8088 mode = &load_detect_mode;
8089
8090 /* We need a framebuffer large enough to accommodate all accesses
8091 * that the plane may generate whilst we perform load detection.
8092 * We can not rely on the fbcon either being present (we get called
8093 * during its initialisation to detect all boot displays, or it may
8094 * not even exist) or that it is large enough to satisfy the
8095 * requested mode.
8096 */
8097 fb = mode_fits_in_fbdev(dev, mode);
8098 if (fb == NULL) {
8099 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8100 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8101 old->release_fb = fb;
8102 } else
8103 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8104 if (IS_ERR(fb)) {
8105 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8106 goto fail;
8107 }
8108
8109 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8110 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8111 if (old->release_fb)
8112 old->release_fb->funcs->destroy(old->release_fb);
8113 goto fail;
8114 }
8115
8116 /* let the connector get through one full cycle before testing */
8117 intel_wait_for_vblank(dev, intel_crtc->pipe);
8118 return true;
8119
8120 fail:
8121 intel_crtc->new_enabled = crtc->enabled;
8122 if (intel_crtc->new_enabled)
8123 intel_crtc->new_config = &intel_crtc->config;
8124 else
8125 intel_crtc->new_config = NULL;
8126 mutex_unlock(&crtc->mutex);
8127 return false;
8128 }
8129
8130 void intel_release_load_detect_pipe(struct drm_connector *connector,
8131 struct intel_load_detect_pipe *old)
8132 {
8133 struct intel_encoder *intel_encoder =
8134 intel_attached_encoder(connector);
8135 struct drm_encoder *encoder = &intel_encoder->base;
8136 struct drm_crtc *crtc = encoder->crtc;
8137 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8138
8139 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8140 connector->base.id, drm_get_connector_name(connector),
8141 encoder->base.id, drm_get_encoder_name(encoder));
8142
8143 if (old->load_detect_temp) {
8144 to_intel_connector(connector)->new_encoder = NULL;
8145 intel_encoder->new_crtc = NULL;
8146 intel_crtc->new_enabled = false;
8147 intel_crtc->new_config = NULL;
8148 intel_set_mode(crtc, NULL, 0, 0, NULL);
8149
8150 if (old->release_fb) {
8151 drm_framebuffer_unregister_private(old->release_fb);
8152 drm_framebuffer_unreference(old->release_fb);
8153 }
8154
8155 mutex_unlock(&crtc->mutex);
8156 return;
8157 }
8158
8159 /* Switch crtc and encoder back off if necessary */
8160 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8161 connector->funcs->dpms(connector, old->dpms_mode);
8162
8163 mutex_unlock(&crtc->mutex);
8164 }
8165
8166 static int i9xx_pll_refclk(struct drm_device *dev,
8167 const struct intel_crtc_config *pipe_config)
8168 {
8169 struct drm_i915_private *dev_priv = dev->dev_private;
8170 u32 dpll = pipe_config->dpll_hw_state.dpll;
8171
8172 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8173 return dev_priv->vbt.lvds_ssc_freq;
8174 else if (HAS_PCH_SPLIT(dev))
8175 return 120000;
8176 else if (!IS_GEN2(dev))
8177 return 96000;
8178 else
8179 return 48000;
8180 }
8181
8182 /* Returns the clock of the currently programmed mode of the given pipe. */
8183 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8184 struct intel_crtc_config *pipe_config)
8185 {
8186 struct drm_device *dev = crtc->base.dev;
8187 struct drm_i915_private *dev_priv = dev->dev_private;
8188 int pipe = pipe_config->cpu_transcoder;
8189 u32 dpll = pipe_config->dpll_hw_state.dpll;
8190 u32 fp;
8191 intel_clock_t clock;
8192 int refclk = i9xx_pll_refclk(dev, pipe_config);
8193
8194 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8195 fp = pipe_config->dpll_hw_state.fp0;
8196 else
8197 fp = pipe_config->dpll_hw_state.fp1;
8198
8199 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8200 if (IS_PINEVIEW(dev)) {
8201 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8202 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8203 } else {
8204 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8205 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8206 }
8207
8208 if (!IS_GEN2(dev)) {
8209 if (IS_PINEVIEW(dev))
8210 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8211 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8212 else
8213 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8214 DPLL_FPA01_P1_POST_DIV_SHIFT);
8215
8216 switch (dpll & DPLL_MODE_MASK) {
8217 case DPLLB_MODE_DAC_SERIAL:
8218 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8219 5 : 10;
8220 break;
8221 case DPLLB_MODE_LVDS:
8222 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8223 7 : 14;
8224 break;
8225 default:
8226 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8227 "mode\n", (int)(dpll & DPLL_MODE_MASK));
8228 return;
8229 }
8230
8231 if (IS_PINEVIEW(dev))
8232 pineview_clock(refclk, &clock);
8233 else
8234 i9xx_clock(refclk, &clock);
8235 } else {
8236 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8237 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8238
8239 if (is_lvds) {
8240 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8241 DPLL_FPA01_P1_POST_DIV_SHIFT);
8242
8243 if (lvds & LVDS_CLKB_POWER_UP)
8244 clock.p2 = 7;
8245 else
8246 clock.p2 = 14;
8247 } else {
8248 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8249 clock.p1 = 2;
8250 else {
8251 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8252 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8253 }
8254 if (dpll & PLL_P2_DIVIDE_BY_4)
8255 clock.p2 = 4;
8256 else
8257 clock.p2 = 2;
8258 }
8259
8260 i9xx_clock(refclk, &clock);
8261 }
8262
8263 /*
8264 * This value includes pixel_multiplier. We will use
8265 * port_clock to compute adjusted_mode.crtc_clock in the
8266 * encoder's get_config() function.
8267 */
8268 pipe_config->port_clock = clock.dot;
8269 }
8270
8271 int intel_dotclock_calculate(int link_freq,
8272 const struct intel_link_m_n *m_n)
8273 {
8274 /*
8275 * The calculation for the data clock is:
8276 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8277 * But we want to avoid losing precison if possible, so:
8278 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8279 *
8280 * and the link clock is simpler:
8281 * link_clock = (m * link_clock) / n
8282 */
8283
8284 if (!m_n->link_n)
8285 return 0;
8286
8287 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8288 }
8289
8290 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8291 struct intel_crtc_config *pipe_config)
8292 {
8293 struct drm_device *dev = crtc->base.dev;
8294
8295 /* read out port_clock from the DPLL */
8296 i9xx_crtc_clock_get(crtc, pipe_config);
8297
8298 /*
8299 * This value does not include pixel_multiplier.
8300 * We will check that port_clock and adjusted_mode.crtc_clock
8301 * agree once we know their relationship in the encoder's
8302 * get_config() function.
8303 */
8304 pipe_config->adjusted_mode.crtc_clock =
8305 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8306 &pipe_config->fdi_m_n);
8307 }
8308
8309 /** Returns the currently programmed mode of the given pipe. */
8310 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8311 struct drm_crtc *crtc)
8312 {
8313 struct drm_i915_private *dev_priv = dev->dev_private;
8314 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8315 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8316 struct drm_display_mode *mode;
8317 struct intel_crtc_config pipe_config;
8318 int htot = I915_READ(HTOTAL(cpu_transcoder));
8319 int hsync = I915_READ(HSYNC(cpu_transcoder));
8320 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8321 int vsync = I915_READ(VSYNC(cpu_transcoder));
8322 enum pipe pipe = intel_crtc->pipe;
8323
8324 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8325 if (!mode)
8326 return NULL;
8327
8328 /*
8329 * Construct a pipe_config sufficient for getting the clock info
8330 * back out of crtc_clock_get.
8331 *
8332 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8333 * to use a real value here instead.
8334 */
8335 pipe_config.cpu_transcoder = (enum transcoder) pipe;
8336 pipe_config.pixel_multiplier = 1;
8337 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8338 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8339 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8340 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8341
8342 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8343 mode->hdisplay = (htot & 0xffff) + 1;
8344 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8345 mode->hsync_start = (hsync & 0xffff) + 1;
8346 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8347 mode->vdisplay = (vtot & 0xffff) + 1;
8348 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8349 mode->vsync_start = (vsync & 0xffff) + 1;
8350 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8351
8352 drm_mode_set_name(mode);
8353
8354 return mode;
8355 }
8356
8357 static void intel_increase_pllclock(struct drm_crtc *crtc)
8358 {
8359 struct drm_device *dev = crtc->dev;
8360 struct drm_i915_private *dev_priv = dev->dev_private;
8361 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8362 int pipe = intel_crtc->pipe;
8363 int dpll_reg = DPLL(pipe);
8364 int dpll;
8365
8366 if (HAS_PCH_SPLIT(dev))
8367 return;
8368
8369 if (!dev_priv->lvds_downclock_avail)
8370 return;
8371
8372 dpll = I915_READ(dpll_reg);
8373 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8374 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8375
8376 assert_panel_unlocked(dev_priv, pipe);
8377
8378 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8379 I915_WRITE(dpll_reg, dpll);
8380 intel_wait_for_vblank(dev, pipe);
8381
8382 dpll = I915_READ(dpll_reg);
8383 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8384 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8385 }
8386 }
8387
8388 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8389 {
8390 struct drm_device *dev = crtc->dev;
8391 struct drm_i915_private *dev_priv = dev->dev_private;
8392 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8393
8394 if (HAS_PCH_SPLIT(dev))
8395 return;
8396
8397 if (!dev_priv->lvds_downclock_avail)
8398 return;
8399
8400 /*
8401 * Since this is called by a timer, we should never get here in
8402 * the manual case.
8403 */
8404 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8405 int pipe = intel_crtc->pipe;
8406 int dpll_reg = DPLL(pipe);
8407 int dpll;
8408
8409 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8410
8411 assert_panel_unlocked(dev_priv, pipe);
8412
8413 dpll = I915_READ(dpll_reg);
8414 dpll |= DISPLAY_RATE_SELECT_FPA1;
8415 I915_WRITE(dpll_reg, dpll);
8416 intel_wait_for_vblank(dev, pipe);
8417 dpll = I915_READ(dpll_reg);
8418 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8419 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8420 }
8421
8422 }
8423
8424 void intel_mark_busy(struct drm_device *dev)
8425 {
8426 struct drm_i915_private *dev_priv = dev->dev_private;
8427
8428 if (dev_priv->mm.busy)
8429 return;
8430
8431 intel_runtime_pm_get(dev_priv);
8432 i915_update_gfx_val(dev_priv);
8433 dev_priv->mm.busy = true;
8434 }
8435
8436 void intel_mark_idle(struct drm_device *dev)
8437 {
8438 struct drm_i915_private *dev_priv = dev->dev_private;
8439 struct drm_crtc *crtc;
8440
8441 if (!dev_priv->mm.busy)
8442 return;
8443
8444 dev_priv->mm.busy = false;
8445
8446 if (!i915.powersave)
8447 goto out;
8448
8449 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8450 if (!crtc->fb)
8451 continue;
8452
8453 intel_decrease_pllclock(crtc);
8454 }
8455
8456 if (INTEL_INFO(dev)->gen >= 6)
8457 gen6_rps_idle(dev->dev_private);
8458
8459 out:
8460 intel_runtime_pm_put(dev_priv);
8461 }
8462
8463 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
8464 struct intel_ring_buffer *ring)
8465 {
8466 struct drm_device *dev = obj->base.dev;
8467 struct drm_crtc *crtc;
8468
8469 if (!i915.powersave)
8470 return;
8471
8472 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8473 if (!crtc->fb)
8474 continue;
8475
8476 if (to_intel_framebuffer(crtc->fb)->obj != obj)
8477 continue;
8478
8479 intel_increase_pllclock(crtc);
8480 if (ring && intel_fbc_enabled(dev))
8481 ring->fbc_dirty = true;
8482 }
8483 }
8484
8485 static void intel_crtc_destroy(struct drm_crtc *crtc)
8486 {
8487 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8488 struct drm_device *dev = crtc->dev;
8489 struct intel_unpin_work *work;
8490 unsigned long flags;
8491
8492 spin_lock_irqsave(&dev->event_lock, flags);
8493 work = intel_crtc->unpin_work;
8494 intel_crtc->unpin_work = NULL;
8495 spin_unlock_irqrestore(&dev->event_lock, flags);
8496
8497 if (work) {
8498 cancel_work_sync(&work->work);
8499 kfree(work);
8500 }
8501
8502 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
8503
8504 drm_crtc_cleanup(crtc);
8505
8506 kfree(intel_crtc);
8507 }
8508
8509 static void intel_unpin_work_fn(struct work_struct *__work)
8510 {
8511 struct intel_unpin_work *work =
8512 container_of(__work, struct intel_unpin_work, work);
8513 struct drm_device *dev = work->crtc->dev;
8514
8515 mutex_lock(&dev->struct_mutex);
8516 intel_unpin_fb_obj(work->old_fb_obj);
8517 drm_gem_object_unreference(&work->pending_flip_obj->base);
8518 drm_gem_object_unreference(&work->old_fb_obj->base);
8519
8520 intel_update_fbc(dev);
8521 mutex_unlock(&dev->struct_mutex);
8522
8523 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8524 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8525
8526 kfree(work);
8527 }
8528
8529 static void do_intel_finish_page_flip(struct drm_device *dev,
8530 struct drm_crtc *crtc)
8531 {
8532 struct drm_i915_private *dev_priv = dev->dev_private;
8533 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8534 struct intel_unpin_work *work;
8535 unsigned long flags;
8536
8537 /* Ignore early vblank irqs */
8538 if (intel_crtc == NULL)
8539 return;
8540
8541 spin_lock_irqsave(&dev->event_lock, flags);
8542 work = intel_crtc->unpin_work;
8543
8544 /* Ensure we don't miss a work->pending update ... */
8545 smp_rmb();
8546
8547 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
8548 spin_unlock_irqrestore(&dev->event_lock, flags);
8549 return;
8550 }
8551
8552 /* and that the unpin work is consistent wrt ->pending. */
8553 smp_rmb();
8554
8555 intel_crtc->unpin_work = NULL;
8556
8557 if (work->event)
8558 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
8559
8560 drm_vblank_put(dev, intel_crtc->pipe);
8561
8562 spin_unlock_irqrestore(&dev->event_lock, flags);
8563
8564 wake_up_all(&dev_priv->pending_flip_queue);
8565
8566 queue_work(dev_priv->wq, &work->work);
8567
8568 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
8569 }
8570
8571 void intel_finish_page_flip(struct drm_device *dev, int pipe)
8572 {
8573 struct drm_i915_private *dev_priv = dev->dev_private;
8574 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8575
8576 do_intel_finish_page_flip(dev, crtc);
8577 }
8578
8579 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8580 {
8581 struct drm_i915_private *dev_priv = dev->dev_private;
8582 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8583
8584 do_intel_finish_page_flip(dev, crtc);
8585 }
8586
8587 void intel_prepare_page_flip(struct drm_device *dev, int plane)
8588 {
8589 struct drm_i915_private *dev_priv = dev->dev_private;
8590 struct intel_crtc *intel_crtc =
8591 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8592 unsigned long flags;
8593
8594 /* NB: An MMIO update of the plane base pointer will also
8595 * generate a page-flip completion irq, i.e. every modeset
8596 * is also accompanied by a spurious intel_prepare_page_flip().
8597 */
8598 spin_lock_irqsave(&dev->event_lock, flags);
8599 if (intel_crtc->unpin_work)
8600 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
8601 spin_unlock_irqrestore(&dev->event_lock, flags);
8602 }
8603
8604 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
8605 {
8606 /* Ensure that the work item is consistent when activating it ... */
8607 smp_wmb();
8608 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
8609 /* and that it is marked active as soon as the irq could fire. */
8610 smp_wmb();
8611 }
8612
8613 static int intel_gen2_queue_flip(struct drm_device *dev,
8614 struct drm_crtc *crtc,
8615 struct drm_framebuffer *fb,
8616 struct drm_i915_gem_object *obj,
8617 uint32_t flags)
8618 {
8619 struct drm_i915_private *dev_priv = dev->dev_private;
8620 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8621 u32 flip_mask;
8622 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8623 int ret;
8624
8625 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8626 if (ret)
8627 goto err;
8628
8629 ret = intel_ring_begin(ring, 6);
8630 if (ret)
8631 goto err_unpin;
8632
8633 /* Can't queue multiple flips, so wait for the previous
8634 * one to finish before executing the next.
8635 */
8636 if (intel_crtc->plane)
8637 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8638 else
8639 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8640 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8641 intel_ring_emit(ring, MI_NOOP);
8642 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8643 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8644 intel_ring_emit(ring, fb->pitches[0]);
8645 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8646 intel_ring_emit(ring, 0); /* aux display base address, unused */
8647
8648 intel_mark_page_flip_active(intel_crtc);
8649 __intel_ring_advance(ring);
8650 return 0;
8651
8652 err_unpin:
8653 intel_unpin_fb_obj(obj);
8654 err:
8655 return ret;
8656 }
8657
8658 static int intel_gen3_queue_flip(struct drm_device *dev,
8659 struct drm_crtc *crtc,
8660 struct drm_framebuffer *fb,
8661 struct drm_i915_gem_object *obj,
8662 uint32_t flags)
8663 {
8664 struct drm_i915_private *dev_priv = dev->dev_private;
8665 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8666 u32 flip_mask;
8667 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8668 int ret;
8669
8670 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8671 if (ret)
8672 goto err;
8673
8674 ret = intel_ring_begin(ring, 6);
8675 if (ret)
8676 goto err_unpin;
8677
8678 if (intel_crtc->plane)
8679 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8680 else
8681 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8682 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8683 intel_ring_emit(ring, MI_NOOP);
8684 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
8685 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8686 intel_ring_emit(ring, fb->pitches[0]);
8687 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8688 intel_ring_emit(ring, MI_NOOP);
8689
8690 intel_mark_page_flip_active(intel_crtc);
8691 __intel_ring_advance(ring);
8692 return 0;
8693
8694 err_unpin:
8695 intel_unpin_fb_obj(obj);
8696 err:
8697 return ret;
8698 }
8699
8700 static int intel_gen4_queue_flip(struct drm_device *dev,
8701 struct drm_crtc *crtc,
8702 struct drm_framebuffer *fb,
8703 struct drm_i915_gem_object *obj,
8704 uint32_t flags)
8705 {
8706 struct drm_i915_private *dev_priv = dev->dev_private;
8707 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8708 uint32_t pf, pipesrc;
8709 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8710 int ret;
8711
8712 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8713 if (ret)
8714 goto err;
8715
8716 ret = intel_ring_begin(ring, 4);
8717 if (ret)
8718 goto err_unpin;
8719
8720 /* i965+ uses the linear or tiled offsets from the
8721 * Display Registers (which do not change across a page-flip)
8722 * so we need only reprogram the base address.
8723 */
8724 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8725 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8726 intel_ring_emit(ring, fb->pitches[0]);
8727 intel_ring_emit(ring,
8728 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
8729 obj->tiling_mode);
8730
8731 /* XXX Enabling the panel-fitter across page-flip is so far
8732 * untested on non-native modes, so ignore it for now.
8733 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8734 */
8735 pf = 0;
8736 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8737 intel_ring_emit(ring, pf | pipesrc);
8738
8739 intel_mark_page_flip_active(intel_crtc);
8740 __intel_ring_advance(ring);
8741 return 0;
8742
8743 err_unpin:
8744 intel_unpin_fb_obj(obj);
8745 err:
8746 return ret;
8747 }
8748
8749 static int intel_gen6_queue_flip(struct drm_device *dev,
8750 struct drm_crtc *crtc,
8751 struct drm_framebuffer *fb,
8752 struct drm_i915_gem_object *obj,
8753 uint32_t flags)
8754 {
8755 struct drm_i915_private *dev_priv = dev->dev_private;
8756 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8757 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8758 uint32_t pf, pipesrc;
8759 int ret;
8760
8761 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8762 if (ret)
8763 goto err;
8764
8765 ret = intel_ring_begin(ring, 4);
8766 if (ret)
8767 goto err_unpin;
8768
8769 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8770 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8771 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
8772 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8773
8774 /* Contrary to the suggestions in the documentation,
8775 * "Enable Panel Fitter" does not seem to be required when page
8776 * flipping with a non-native mode, and worse causes a normal
8777 * modeset to fail.
8778 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8779 */
8780 pf = 0;
8781 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8782 intel_ring_emit(ring, pf | pipesrc);
8783
8784 intel_mark_page_flip_active(intel_crtc);
8785 __intel_ring_advance(ring);
8786 return 0;
8787
8788 err_unpin:
8789 intel_unpin_fb_obj(obj);
8790 err:
8791 return ret;
8792 }
8793
8794 static int intel_gen7_queue_flip(struct drm_device *dev,
8795 struct drm_crtc *crtc,
8796 struct drm_framebuffer *fb,
8797 struct drm_i915_gem_object *obj,
8798 uint32_t flags)
8799 {
8800 struct drm_i915_private *dev_priv = dev->dev_private;
8801 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8802 struct intel_ring_buffer *ring;
8803 uint32_t plane_bit = 0;
8804 int len, ret;
8805
8806 ring = obj->ring;
8807 if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
8808 ring = &dev_priv->ring[BCS];
8809
8810 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8811 if (ret)
8812 goto err;
8813
8814 switch(intel_crtc->plane) {
8815 case PLANE_A:
8816 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8817 break;
8818 case PLANE_B:
8819 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8820 break;
8821 case PLANE_C:
8822 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8823 break;
8824 default:
8825 WARN_ONCE(1, "unknown plane in flip command\n");
8826 ret = -ENODEV;
8827 goto err_unpin;
8828 }
8829
8830 len = 4;
8831 if (ring->id == RCS)
8832 len += 6;
8833
8834 /*
8835 * BSpec MI_DISPLAY_FLIP for IVB:
8836 * "The full packet must be contained within the same cache line."
8837 *
8838 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
8839 * cacheline, if we ever start emitting more commands before
8840 * the MI_DISPLAY_FLIP we may need to first emit everything else,
8841 * then do the cacheline alignment, and finally emit the
8842 * MI_DISPLAY_FLIP.
8843 */
8844 ret = intel_ring_cacheline_align(ring);
8845 if (ret)
8846 goto err_unpin;
8847
8848 ret = intel_ring_begin(ring, len);
8849 if (ret)
8850 goto err_unpin;
8851
8852 /* Unmask the flip-done completion message. Note that the bspec says that
8853 * we should do this for both the BCS and RCS, and that we must not unmask
8854 * more than one flip event at any time (or ensure that one flip message
8855 * can be sent by waiting for flip-done prior to queueing new flips).
8856 * Experimentation says that BCS works despite DERRMR masking all
8857 * flip-done completion events and that unmasking all planes at once
8858 * for the RCS also doesn't appear to drop events. Setting the DERRMR
8859 * to zero does lead to lockups within MI_DISPLAY_FLIP.
8860 */
8861 if (ring->id == RCS) {
8862 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8863 intel_ring_emit(ring, DERRMR);
8864 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8865 DERRMR_PIPEB_PRI_FLIP_DONE |
8866 DERRMR_PIPEC_PRI_FLIP_DONE));
8867 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
8868 MI_SRM_LRM_GLOBAL_GTT);
8869 intel_ring_emit(ring, DERRMR);
8870 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8871 }
8872
8873 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
8874 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
8875 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8876 intel_ring_emit(ring, (MI_NOOP));
8877
8878 intel_mark_page_flip_active(intel_crtc);
8879 __intel_ring_advance(ring);
8880 return 0;
8881
8882 err_unpin:
8883 intel_unpin_fb_obj(obj);
8884 err:
8885 return ret;
8886 }
8887
8888 static int intel_default_queue_flip(struct drm_device *dev,
8889 struct drm_crtc *crtc,
8890 struct drm_framebuffer *fb,
8891 struct drm_i915_gem_object *obj,
8892 uint32_t flags)
8893 {
8894 return -ENODEV;
8895 }
8896
8897 static int intel_crtc_page_flip(struct drm_crtc *crtc,
8898 struct drm_framebuffer *fb,
8899 struct drm_pending_vblank_event *event,
8900 uint32_t page_flip_flags)
8901 {
8902 struct drm_device *dev = crtc->dev;
8903 struct drm_i915_private *dev_priv = dev->dev_private;
8904 struct drm_framebuffer *old_fb = crtc->fb;
8905 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
8906 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8907 struct intel_unpin_work *work;
8908 unsigned long flags;
8909 int ret;
8910
8911 /* Can't change pixel format via MI display flips. */
8912 if (fb->pixel_format != crtc->fb->pixel_format)
8913 return -EINVAL;
8914
8915 /*
8916 * TILEOFF/LINOFF registers can't be changed via MI display flips.
8917 * Note that pitch changes could also affect these register.
8918 */
8919 if (INTEL_INFO(dev)->gen > 3 &&
8920 (fb->offsets[0] != crtc->fb->offsets[0] ||
8921 fb->pitches[0] != crtc->fb->pitches[0]))
8922 return -EINVAL;
8923
8924 if (i915_terminally_wedged(&dev_priv->gpu_error))
8925 goto out_hang;
8926
8927 work = kzalloc(sizeof(*work), GFP_KERNEL);
8928 if (work == NULL)
8929 return -ENOMEM;
8930
8931 work->event = event;
8932 work->crtc = crtc;
8933 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
8934 INIT_WORK(&work->work, intel_unpin_work_fn);
8935
8936 ret = drm_vblank_get(dev, intel_crtc->pipe);
8937 if (ret)
8938 goto free_work;
8939
8940 /* We borrow the event spin lock for protecting unpin_work */
8941 spin_lock_irqsave(&dev->event_lock, flags);
8942 if (intel_crtc->unpin_work) {
8943 spin_unlock_irqrestore(&dev->event_lock, flags);
8944 kfree(work);
8945 drm_vblank_put(dev, intel_crtc->pipe);
8946
8947 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
8948 return -EBUSY;
8949 }
8950 intel_crtc->unpin_work = work;
8951 spin_unlock_irqrestore(&dev->event_lock, flags);
8952
8953 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8954 flush_workqueue(dev_priv->wq);
8955
8956 ret = i915_mutex_lock_interruptible(dev);
8957 if (ret)
8958 goto cleanup;
8959
8960 /* Reference the objects for the scheduled work. */
8961 drm_gem_object_reference(&work->old_fb_obj->base);
8962 drm_gem_object_reference(&obj->base);
8963
8964 crtc->fb = fb;
8965
8966 work->pending_flip_obj = obj;
8967
8968 work->enable_stall_check = true;
8969
8970 atomic_inc(&intel_crtc->unpin_work_count);
8971 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
8972
8973 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8974 if (ret)
8975 goto cleanup_pending;
8976
8977 intel_disable_fbc(dev);
8978 intel_mark_fb_busy(obj, NULL);
8979 mutex_unlock(&dev->struct_mutex);
8980
8981 trace_i915_flip_request(intel_crtc->plane, obj);
8982
8983 return 0;
8984
8985 cleanup_pending:
8986 atomic_dec(&intel_crtc->unpin_work_count);
8987 crtc->fb = old_fb;
8988 drm_gem_object_unreference(&work->old_fb_obj->base);
8989 drm_gem_object_unreference(&obj->base);
8990 mutex_unlock(&dev->struct_mutex);
8991
8992 cleanup:
8993 spin_lock_irqsave(&dev->event_lock, flags);
8994 intel_crtc->unpin_work = NULL;
8995 spin_unlock_irqrestore(&dev->event_lock, flags);
8996
8997 drm_vblank_put(dev, intel_crtc->pipe);
8998 free_work:
8999 kfree(work);
9000
9001 if (ret == -EIO) {
9002 out_hang:
9003 intel_crtc_wait_for_pending_flips(crtc);
9004 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9005 if (ret == 0 && event)
9006 drm_send_vblank_event(dev, intel_crtc->pipe, event);
9007 }
9008 return ret;
9009 }
9010
9011 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9012 .mode_set_base_atomic = intel_pipe_set_base_atomic,
9013 .load_lut = intel_crtc_load_lut,
9014 };
9015
9016 /**
9017 * intel_modeset_update_staged_output_state
9018 *
9019 * Updates the staged output configuration state, e.g. after we've read out the
9020 * current hw state.
9021 */
9022 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9023 {
9024 struct intel_crtc *crtc;
9025 struct intel_encoder *encoder;
9026 struct intel_connector *connector;
9027
9028 list_for_each_entry(connector, &dev->mode_config.connector_list,
9029 base.head) {
9030 connector->new_encoder =
9031 to_intel_encoder(connector->base.encoder);
9032 }
9033
9034 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9035 base.head) {
9036 encoder->new_crtc =
9037 to_intel_crtc(encoder->base.crtc);
9038 }
9039
9040 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9041 base.head) {
9042 crtc->new_enabled = crtc->base.enabled;
9043
9044 if (crtc->new_enabled)
9045 crtc->new_config = &crtc->config;
9046 else
9047 crtc->new_config = NULL;
9048 }
9049 }
9050
9051 /**
9052 * intel_modeset_commit_output_state
9053 *
9054 * This function copies the stage display pipe configuration to the real one.
9055 */
9056 static void intel_modeset_commit_output_state(struct drm_device *dev)
9057 {
9058 struct intel_crtc *crtc;
9059 struct intel_encoder *encoder;
9060 struct intel_connector *connector;
9061
9062 list_for_each_entry(connector, &dev->mode_config.connector_list,
9063 base.head) {
9064 connector->base.encoder = &connector->new_encoder->base;
9065 }
9066
9067 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9068 base.head) {
9069 encoder->base.crtc = &encoder->new_crtc->base;
9070 }
9071
9072 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9073 base.head) {
9074 crtc->base.enabled = crtc->new_enabled;
9075 }
9076 }
9077
9078 static void
9079 connected_sink_compute_bpp(struct intel_connector * connector,
9080 struct intel_crtc_config *pipe_config)
9081 {
9082 int bpp = pipe_config->pipe_bpp;
9083
9084 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9085 connector->base.base.id,
9086 drm_get_connector_name(&connector->base));
9087
9088 /* Don't use an invalid EDID bpc value */
9089 if (connector->base.display_info.bpc &&
9090 connector->base.display_info.bpc * 3 < bpp) {
9091 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9092 bpp, connector->base.display_info.bpc*3);
9093 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9094 }
9095
9096 /* Clamp bpp to 8 on screens without EDID 1.4 */
9097 if (connector->base.display_info.bpc == 0 && bpp > 24) {
9098 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9099 bpp);
9100 pipe_config->pipe_bpp = 24;
9101 }
9102 }
9103
9104 static int
9105 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9106 struct drm_framebuffer *fb,
9107 struct intel_crtc_config *pipe_config)
9108 {
9109 struct drm_device *dev = crtc->base.dev;
9110 struct intel_connector *connector;
9111 int bpp;
9112
9113 switch (fb->pixel_format) {
9114 case DRM_FORMAT_C8:
9115 bpp = 8*3; /* since we go through a colormap */
9116 break;
9117 case DRM_FORMAT_XRGB1555:
9118 case DRM_FORMAT_ARGB1555:
9119 /* checked in intel_framebuffer_init already */
9120 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9121 return -EINVAL;
9122 case DRM_FORMAT_RGB565:
9123 bpp = 6*3; /* min is 18bpp */
9124 break;
9125 case DRM_FORMAT_XBGR8888:
9126 case DRM_FORMAT_ABGR8888:
9127 /* checked in intel_framebuffer_init already */
9128 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9129 return -EINVAL;
9130 case DRM_FORMAT_XRGB8888:
9131 case DRM_FORMAT_ARGB8888:
9132 bpp = 8*3;
9133 break;
9134 case DRM_FORMAT_XRGB2101010:
9135 case DRM_FORMAT_ARGB2101010:
9136 case DRM_FORMAT_XBGR2101010:
9137 case DRM_FORMAT_ABGR2101010:
9138 /* checked in intel_framebuffer_init already */
9139 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9140 return -EINVAL;
9141 bpp = 10*3;
9142 break;
9143 /* TODO: gen4+ supports 16 bpc floating point, too. */
9144 default:
9145 DRM_DEBUG_KMS("unsupported depth\n");
9146 return -EINVAL;
9147 }
9148
9149 pipe_config->pipe_bpp = bpp;
9150
9151 /* Clamp display bpp to EDID value */
9152 list_for_each_entry(connector, &dev->mode_config.connector_list,
9153 base.head) {
9154 if (!connector->new_encoder ||
9155 connector->new_encoder->new_crtc != crtc)
9156 continue;
9157
9158 connected_sink_compute_bpp(connector, pipe_config);
9159 }
9160
9161 return bpp;
9162 }
9163
9164 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9165 {
9166 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9167 "type: 0x%x flags: 0x%x\n",
9168 mode->crtc_clock,
9169 mode->crtc_hdisplay, mode->crtc_hsync_start,
9170 mode->crtc_hsync_end, mode->crtc_htotal,
9171 mode->crtc_vdisplay, mode->crtc_vsync_start,
9172 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9173 }
9174
9175 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9176 struct intel_crtc_config *pipe_config,
9177 const char *context)
9178 {
9179 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9180 context, pipe_name(crtc->pipe));
9181
9182 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9183 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9184 pipe_config->pipe_bpp, pipe_config->dither);
9185 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9186 pipe_config->has_pch_encoder,
9187 pipe_config->fdi_lanes,
9188 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9189 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9190 pipe_config->fdi_m_n.tu);
9191 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9192 pipe_config->has_dp_encoder,
9193 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9194 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9195 pipe_config->dp_m_n.tu);
9196 DRM_DEBUG_KMS("requested mode:\n");
9197 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9198 DRM_DEBUG_KMS("adjusted mode:\n");
9199 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
9200 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
9201 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9202 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9203 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
9204 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9205 pipe_config->gmch_pfit.control,
9206 pipe_config->gmch_pfit.pgm_ratios,
9207 pipe_config->gmch_pfit.lvds_border_bits);
9208 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9209 pipe_config->pch_pfit.pos,
9210 pipe_config->pch_pfit.size,
9211 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
9212 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
9213 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
9214 }
9215
9216 static bool encoders_cloneable(const struct intel_encoder *a,
9217 const struct intel_encoder *b)
9218 {
9219 /* masks could be asymmetric, so check both ways */
9220 return a == b || (a->cloneable & (1 << b->type) &&
9221 b->cloneable & (1 << a->type));
9222 }
9223
9224 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
9225 struct intel_encoder *encoder)
9226 {
9227 struct drm_device *dev = crtc->base.dev;
9228 struct intel_encoder *source_encoder;
9229
9230 list_for_each_entry(source_encoder,
9231 &dev->mode_config.encoder_list, base.head) {
9232 if (source_encoder->new_crtc != crtc)
9233 continue;
9234
9235 if (!encoders_cloneable(encoder, source_encoder))
9236 return false;
9237 }
9238
9239 return true;
9240 }
9241
9242 static bool check_encoder_cloning(struct intel_crtc *crtc)
9243 {
9244 struct drm_device *dev = crtc->base.dev;
9245 struct intel_encoder *encoder;
9246
9247 list_for_each_entry(encoder,
9248 &dev->mode_config.encoder_list, base.head) {
9249 if (encoder->new_crtc != crtc)
9250 continue;
9251
9252 if (!check_single_encoder_cloning(crtc, encoder))
9253 return false;
9254 }
9255
9256 return true;
9257 }
9258
9259 static struct intel_crtc_config *
9260 intel_modeset_pipe_config(struct drm_crtc *crtc,
9261 struct drm_framebuffer *fb,
9262 struct drm_display_mode *mode)
9263 {
9264 struct drm_device *dev = crtc->dev;
9265 struct intel_encoder *encoder;
9266 struct intel_crtc_config *pipe_config;
9267 int plane_bpp, ret = -EINVAL;
9268 bool retry = true;
9269
9270 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
9271 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
9272 return ERR_PTR(-EINVAL);
9273 }
9274
9275 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9276 if (!pipe_config)
9277 return ERR_PTR(-ENOMEM);
9278
9279 drm_mode_copy(&pipe_config->adjusted_mode, mode);
9280 drm_mode_copy(&pipe_config->requested_mode, mode);
9281
9282 pipe_config->cpu_transcoder =
9283 (enum transcoder) to_intel_crtc(crtc)->pipe;
9284 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9285
9286 /*
9287 * Sanitize sync polarity flags based on requested ones. If neither
9288 * positive or negative polarity is requested, treat this as meaning
9289 * negative polarity.
9290 */
9291 if (!(pipe_config->adjusted_mode.flags &
9292 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
9293 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
9294
9295 if (!(pipe_config->adjusted_mode.flags &
9296 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
9297 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
9298
9299 /* Compute a starting value for pipe_config->pipe_bpp taking the source
9300 * plane pixel format and any sink constraints into account. Returns the
9301 * source plane bpp so that dithering can be selected on mismatches
9302 * after encoders and crtc also have had their say. */
9303 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
9304 fb, pipe_config);
9305 if (plane_bpp < 0)
9306 goto fail;
9307
9308 /*
9309 * Determine the real pipe dimensions. Note that stereo modes can
9310 * increase the actual pipe size due to the frame doubling and
9311 * insertion of additional space for blanks between the frame. This
9312 * is stored in the crtc timings. We use the requested mode to do this
9313 * computation to clearly distinguish it from the adjusted mode, which
9314 * can be changed by the connectors in the below retry loop.
9315 */
9316 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
9317 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
9318 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
9319
9320 encoder_retry:
9321 /* Ensure the port clock defaults are reset when retrying. */
9322 pipe_config->port_clock = 0;
9323 pipe_config->pixel_multiplier = 1;
9324
9325 /* Fill in default crtc timings, allow encoders to overwrite them. */
9326 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
9327
9328 /* Pass our mode to the connectors and the CRTC to give them a chance to
9329 * adjust it according to limitations or connector properties, and also
9330 * a chance to reject the mode entirely.
9331 */
9332 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9333 base.head) {
9334
9335 if (&encoder->new_crtc->base != crtc)
9336 continue;
9337
9338 if (!(encoder->compute_config(encoder, pipe_config))) {
9339 DRM_DEBUG_KMS("Encoder config failure\n");
9340 goto fail;
9341 }
9342 }
9343
9344 /* Set default port clock if not overwritten by the encoder. Needs to be
9345 * done afterwards in case the encoder adjusts the mode. */
9346 if (!pipe_config->port_clock)
9347 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
9348 * pipe_config->pixel_multiplier;
9349
9350 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
9351 if (ret < 0) {
9352 DRM_DEBUG_KMS("CRTC fixup failed\n");
9353 goto fail;
9354 }
9355
9356 if (ret == RETRY) {
9357 if (WARN(!retry, "loop in pipe configuration computation\n")) {
9358 ret = -EINVAL;
9359 goto fail;
9360 }
9361
9362 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
9363 retry = false;
9364 goto encoder_retry;
9365 }
9366
9367 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
9368 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
9369 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
9370
9371 return pipe_config;
9372 fail:
9373 kfree(pipe_config);
9374 return ERR_PTR(ret);
9375 }
9376
9377 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
9378 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
9379 static void
9380 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
9381 unsigned *prepare_pipes, unsigned *disable_pipes)
9382 {
9383 struct intel_crtc *intel_crtc;
9384 struct drm_device *dev = crtc->dev;
9385 struct intel_encoder *encoder;
9386 struct intel_connector *connector;
9387 struct drm_crtc *tmp_crtc;
9388
9389 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
9390
9391 /* Check which crtcs have changed outputs connected to them, these need
9392 * to be part of the prepare_pipes mask. We don't (yet) support global
9393 * modeset across multiple crtcs, so modeset_pipes will only have one
9394 * bit set at most. */
9395 list_for_each_entry(connector, &dev->mode_config.connector_list,
9396 base.head) {
9397 if (connector->base.encoder == &connector->new_encoder->base)
9398 continue;
9399
9400 if (connector->base.encoder) {
9401 tmp_crtc = connector->base.encoder->crtc;
9402
9403 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9404 }
9405
9406 if (connector->new_encoder)
9407 *prepare_pipes |=
9408 1 << connector->new_encoder->new_crtc->pipe;
9409 }
9410
9411 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9412 base.head) {
9413 if (encoder->base.crtc == &encoder->new_crtc->base)
9414 continue;
9415
9416 if (encoder->base.crtc) {
9417 tmp_crtc = encoder->base.crtc;
9418
9419 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9420 }
9421
9422 if (encoder->new_crtc)
9423 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
9424 }
9425
9426 /* Check for pipes that will be enabled/disabled ... */
9427 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9428 base.head) {
9429 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
9430 continue;
9431
9432 if (!intel_crtc->new_enabled)
9433 *disable_pipes |= 1 << intel_crtc->pipe;
9434 else
9435 *prepare_pipes |= 1 << intel_crtc->pipe;
9436 }
9437
9438
9439 /* set_mode is also used to update properties on life display pipes. */
9440 intel_crtc = to_intel_crtc(crtc);
9441 if (intel_crtc->new_enabled)
9442 *prepare_pipes |= 1 << intel_crtc->pipe;
9443
9444 /*
9445 * For simplicity do a full modeset on any pipe where the output routing
9446 * changed. We could be more clever, but that would require us to be
9447 * more careful with calling the relevant encoder->mode_set functions.
9448 */
9449 if (*prepare_pipes)
9450 *modeset_pipes = *prepare_pipes;
9451
9452 /* ... and mask these out. */
9453 *modeset_pipes &= ~(*disable_pipes);
9454 *prepare_pipes &= ~(*disable_pipes);
9455
9456 /*
9457 * HACK: We don't (yet) fully support global modesets. intel_set_config
9458 * obies this rule, but the modeset restore mode of
9459 * intel_modeset_setup_hw_state does not.
9460 */
9461 *modeset_pipes &= 1 << intel_crtc->pipe;
9462 *prepare_pipes &= 1 << intel_crtc->pipe;
9463
9464 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
9465 *modeset_pipes, *prepare_pipes, *disable_pipes);
9466 }
9467
9468 static bool intel_crtc_in_use(struct drm_crtc *crtc)
9469 {
9470 struct drm_encoder *encoder;
9471 struct drm_device *dev = crtc->dev;
9472
9473 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
9474 if (encoder->crtc == crtc)
9475 return true;
9476
9477 return false;
9478 }
9479
9480 static void
9481 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
9482 {
9483 struct intel_encoder *intel_encoder;
9484 struct intel_crtc *intel_crtc;
9485 struct drm_connector *connector;
9486
9487 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
9488 base.head) {
9489 if (!intel_encoder->base.crtc)
9490 continue;
9491
9492 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
9493
9494 if (prepare_pipes & (1 << intel_crtc->pipe))
9495 intel_encoder->connectors_active = false;
9496 }
9497
9498 intel_modeset_commit_output_state(dev);
9499
9500 /* Double check state. */
9501 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9502 base.head) {
9503 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
9504 WARN_ON(intel_crtc->new_config &&
9505 intel_crtc->new_config != &intel_crtc->config);
9506 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
9507 }
9508
9509 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9510 if (!connector->encoder || !connector->encoder->crtc)
9511 continue;
9512
9513 intel_crtc = to_intel_crtc(connector->encoder->crtc);
9514
9515 if (prepare_pipes & (1 << intel_crtc->pipe)) {
9516 struct drm_property *dpms_property =
9517 dev->mode_config.dpms_property;
9518
9519 connector->dpms = DRM_MODE_DPMS_ON;
9520 drm_object_property_set_value(&connector->base,
9521 dpms_property,
9522 DRM_MODE_DPMS_ON);
9523
9524 intel_encoder = to_intel_encoder(connector->encoder);
9525 intel_encoder->connectors_active = true;
9526 }
9527 }
9528
9529 }
9530
9531 static bool intel_fuzzy_clock_check(int clock1, int clock2)
9532 {
9533 int diff;
9534
9535 if (clock1 == clock2)
9536 return true;
9537
9538 if (!clock1 || !clock2)
9539 return false;
9540
9541 diff = abs(clock1 - clock2);
9542
9543 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
9544 return true;
9545
9546 return false;
9547 }
9548
9549 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
9550 list_for_each_entry((intel_crtc), \
9551 &(dev)->mode_config.crtc_list, \
9552 base.head) \
9553 if (mask & (1 <<(intel_crtc)->pipe))
9554
9555 static bool
9556 intel_pipe_config_compare(struct drm_device *dev,
9557 struct intel_crtc_config *current_config,
9558 struct intel_crtc_config *pipe_config)
9559 {
9560 #define PIPE_CONF_CHECK_X(name) \
9561 if (current_config->name != pipe_config->name) { \
9562 DRM_ERROR("mismatch in " #name " " \
9563 "(expected 0x%08x, found 0x%08x)\n", \
9564 current_config->name, \
9565 pipe_config->name); \
9566 return false; \
9567 }
9568
9569 #define PIPE_CONF_CHECK_I(name) \
9570 if (current_config->name != pipe_config->name) { \
9571 DRM_ERROR("mismatch in " #name " " \
9572 "(expected %i, found %i)\n", \
9573 current_config->name, \
9574 pipe_config->name); \
9575 return false; \
9576 }
9577
9578 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
9579 if ((current_config->name ^ pipe_config->name) & (mask)) { \
9580 DRM_ERROR("mismatch in " #name "(" #mask ") " \
9581 "(expected %i, found %i)\n", \
9582 current_config->name & (mask), \
9583 pipe_config->name & (mask)); \
9584 return false; \
9585 }
9586
9587 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
9588 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
9589 DRM_ERROR("mismatch in " #name " " \
9590 "(expected %i, found %i)\n", \
9591 current_config->name, \
9592 pipe_config->name); \
9593 return false; \
9594 }
9595
9596 #define PIPE_CONF_QUIRK(quirk) \
9597 ((current_config->quirks | pipe_config->quirks) & (quirk))
9598
9599 PIPE_CONF_CHECK_I(cpu_transcoder);
9600
9601 PIPE_CONF_CHECK_I(has_pch_encoder);
9602 PIPE_CONF_CHECK_I(fdi_lanes);
9603 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
9604 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
9605 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
9606 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
9607 PIPE_CONF_CHECK_I(fdi_m_n.tu);
9608
9609 PIPE_CONF_CHECK_I(has_dp_encoder);
9610 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
9611 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
9612 PIPE_CONF_CHECK_I(dp_m_n.link_m);
9613 PIPE_CONF_CHECK_I(dp_m_n.link_n);
9614 PIPE_CONF_CHECK_I(dp_m_n.tu);
9615
9616 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
9617 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
9618 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
9619 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
9620 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
9621 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
9622
9623 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
9624 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
9625 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
9626 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
9627 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
9628 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
9629
9630 PIPE_CONF_CHECK_I(pixel_multiplier);
9631
9632 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9633 DRM_MODE_FLAG_INTERLACE);
9634
9635 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
9636 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9637 DRM_MODE_FLAG_PHSYNC);
9638 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9639 DRM_MODE_FLAG_NHSYNC);
9640 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9641 DRM_MODE_FLAG_PVSYNC);
9642 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9643 DRM_MODE_FLAG_NVSYNC);
9644 }
9645
9646 PIPE_CONF_CHECK_I(pipe_src_w);
9647 PIPE_CONF_CHECK_I(pipe_src_h);
9648
9649 PIPE_CONF_CHECK_I(gmch_pfit.control);
9650 /* pfit ratios are autocomputed by the hw on gen4+ */
9651 if (INTEL_INFO(dev)->gen < 4)
9652 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
9653 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
9654 PIPE_CONF_CHECK_I(pch_pfit.enabled);
9655 if (current_config->pch_pfit.enabled) {
9656 PIPE_CONF_CHECK_I(pch_pfit.pos);
9657 PIPE_CONF_CHECK_I(pch_pfit.size);
9658 }
9659
9660 /* BDW+ don't expose a synchronous way to read the state */
9661 if (IS_HASWELL(dev))
9662 PIPE_CONF_CHECK_I(ips_enabled);
9663
9664 PIPE_CONF_CHECK_I(double_wide);
9665
9666 PIPE_CONF_CHECK_I(shared_dpll);
9667 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
9668 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
9669 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
9670 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
9671
9672 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
9673 PIPE_CONF_CHECK_I(pipe_bpp);
9674
9675 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
9676 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
9677
9678 #undef PIPE_CONF_CHECK_X
9679 #undef PIPE_CONF_CHECK_I
9680 #undef PIPE_CONF_CHECK_FLAGS
9681 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
9682 #undef PIPE_CONF_QUIRK
9683
9684 return true;
9685 }
9686
9687 static void
9688 check_connector_state(struct drm_device *dev)
9689 {
9690 struct intel_connector *connector;
9691
9692 list_for_each_entry(connector, &dev->mode_config.connector_list,
9693 base.head) {
9694 /* This also checks the encoder/connector hw state with the
9695 * ->get_hw_state callbacks. */
9696 intel_connector_check_state(connector);
9697
9698 WARN(&connector->new_encoder->base != connector->base.encoder,
9699 "connector's staged encoder doesn't match current encoder\n");
9700 }
9701 }
9702
9703 static void
9704 check_encoder_state(struct drm_device *dev)
9705 {
9706 struct intel_encoder *encoder;
9707 struct intel_connector *connector;
9708
9709 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9710 base.head) {
9711 bool enabled = false;
9712 bool active = false;
9713 enum pipe pipe, tracked_pipe;
9714
9715 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
9716 encoder->base.base.id,
9717 drm_get_encoder_name(&encoder->base));
9718
9719 WARN(&encoder->new_crtc->base != encoder->base.crtc,
9720 "encoder's stage crtc doesn't match current crtc\n");
9721 WARN(encoder->connectors_active && !encoder->base.crtc,
9722 "encoder's active_connectors set, but no crtc\n");
9723
9724 list_for_each_entry(connector, &dev->mode_config.connector_list,
9725 base.head) {
9726 if (connector->base.encoder != &encoder->base)
9727 continue;
9728 enabled = true;
9729 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
9730 active = true;
9731 }
9732 WARN(!!encoder->base.crtc != enabled,
9733 "encoder's enabled state mismatch "
9734 "(expected %i, found %i)\n",
9735 !!encoder->base.crtc, enabled);
9736 WARN(active && !encoder->base.crtc,
9737 "active encoder with no crtc\n");
9738
9739 WARN(encoder->connectors_active != active,
9740 "encoder's computed active state doesn't match tracked active state "
9741 "(expected %i, found %i)\n", active, encoder->connectors_active);
9742
9743 active = encoder->get_hw_state(encoder, &pipe);
9744 WARN(active != encoder->connectors_active,
9745 "encoder's hw state doesn't match sw tracking "
9746 "(expected %i, found %i)\n",
9747 encoder->connectors_active, active);
9748
9749 if (!encoder->base.crtc)
9750 continue;
9751
9752 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
9753 WARN(active && pipe != tracked_pipe,
9754 "active encoder's pipe doesn't match"
9755 "(expected %i, found %i)\n",
9756 tracked_pipe, pipe);
9757
9758 }
9759 }
9760
9761 static void
9762 check_crtc_state(struct drm_device *dev)
9763 {
9764 struct drm_i915_private *dev_priv = dev->dev_private;
9765 struct intel_crtc *crtc;
9766 struct intel_encoder *encoder;
9767 struct intel_crtc_config pipe_config;
9768
9769 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9770 base.head) {
9771 bool enabled = false;
9772 bool active = false;
9773
9774 memset(&pipe_config, 0, sizeof(pipe_config));
9775
9776 DRM_DEBUG_KMS("[CRTC:%d]\n",
9777 crtc->base.base.id);
9778
9779 WARN(crtc->active && !crtc->base.enabled,
9780 "active crtc, but not enabled in sw tracking\n");
9781
9782 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9783 base.head) {
9784 if (encoder->base.crtc != &crtc->base)
9785 continue;
9786 enabled = true;
9787 if (encoder->connectors_active)
9788 active = true;
9789 }
9790
9791 WARN(active != crtc->active,
9792 "crtc's computed active state doesn't match tracked active state "
9793 "(expected %i, found %i)\n", active, crtc->active);
9794 WARN(enabled != crtc->base.enabled,
9795 "crtc's computed enabled state doesn't match tracked enabled state "
9796 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
9797
9798 active = dev_priv->display.get_pipe_config(crtc,
9799 &pipe_config);
9800
9801 /* hw state is inconsistent with the pipe A quirk */
9802 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
9803 active = crtc->active;
9804
9805 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9806 base.head) {
9807 enum pipe pipe;
9808 if (encoder->base.crtc != &crtc->base)
9809 continue;
9810 if (encoder->get_hw_state(encoder, &pipe))
9811 encoder->get_config(encoder, &pipe_config);
9812 }
9813
9814 WARN(crtc->active != active,
9815 "crtc active state doesn't match with hw state "
9816 "(expected %i, found %i)\n", crtc->active, active);
9817
9818 if (active &&
9819 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
9820 WARN(1, "pipe state doesn't match!\n");
9821 intel_dump_pipe_config(crtc, &pipe_config,
9822 "[hw state]");
9823 intel_dump_pipe_config(crtc, &crtc->config,
9824 "[sw state]");
9825 }
9826 }
9827 }
9828
9829 static void
9830 check_shared_dpll_state(struct drm_device *dev)
9831 {
9832 struct drm_i915_private *dev_priv = dev->dev_private;
9833 struct intel_crtc *crtc;
9834 struct intel_dpll_hw_state dpll_hw_state;
9835 int i;
9836
9837 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9838 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9839 int enabled_crtcs = 0, active_crtcs = 0;
9840 bool active;
9841
9842 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9843
9844 DRM_DEBUG_KMS("%s\n", pll->name);
9845
9846 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
9847
9848 WARN(pll->active > pll->refcount,
9849 "more active pll users than references: %i vs %i\n",
9850 pll->active, pll->refcount);
9851 WARN(pll->active && !pll->on,
9852 "pll in active use but not on in sw tracking\n");
9853 WARN(pll->on && !pll->active,
9854 "pll in on but not on in use in sw tracking\n");
9855 WARN(pll->on != active,
9856 "pll on state mismatch (expected %i, found %i)\n",
9857 pll->on, active);
9858
9859 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9860 base.head) {
9861 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9862 enabled_crtcs++;
9863 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9864 active_crtcs++;
9865 }
9866 WARN(pll->active != active_crtcs,
9867 "pll active crtcs mismatch (expected %i, found %i)\n",
9868 pll->active, active_crtcs);
9869 WARN(pll->refcount != enabled_crtcs,
9870 "pll enabled crtcs mismatch (expected %i, found %i)\n",
9871 pll->refcount, enabled_crtcs);
9872
9873 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9874 sizeof(dpll_hw_state)),
9875 "pll hw state mismatch\n");
9876 }
9877 }
9878
9879 void
9880 intel_modeset_check_state(struct drm_device *dev)
9881 {
9882 check_connector_state(dev);
9883 check_encoder_state(dev);
9884 check_crtc_state(dev);
9885 check_shared_dpll_state(dev);
9886 }
9887
9888 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9889 int dotclock)
9890 {
9891 /*
9892 * FDI already provided one idea for the dotclock.
9893 * Yell if the encoder disagrees.
9894 */
9895 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
9896 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
9897 pipe_config->adjusted_mode.crtc_clock, dotclock);
9898 }
9899
9900 static int __intel_set_mode(struct drm_crtc *crtc,
9901 struct drm_display_mode *mode,
9902 int x, int y, struct drm_framebuffer *fb)
9903 {
9904 struct drm_device *dev = crtc->dev;
9905 struct drm_i915_private *dev_priv = dev->dev_private;
9906 struct drm_display_mode *saved_mode;
9907 struct intel_crtc_config *pipe_config = NULL;
9908 struct intel_crtc *intel_crtc;
9909 unsigned disable_pipes, prepare_pipes, modeset_pipes;
9910 int ret = 0;
9911
9912 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
9913 if (!saved_mode)
9914 return -ENOMEM;
9915
9916 intel_modeset_affected_pipes(crtc, &modeset_pipes,
9917 &prepare_pipes, &disable_pipes);
9918
9919 *saved_mode = crtc->mode;
9920
9921 /* Hack: Because we don't (yet) support global modeset on multiple
9922 * crtcs, we don't keep track of the new mode for more than one crtc.
9923 * Hence simply check whether any bit is set in modeset_pipes in all the
9924 * pieces of code that are not yet converted to deal with mutliple crtcs
9925 * changing their mode at the same time. */
9926 if (modeset_pipes) {
9927 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
9928 if (IS_ERR(pipe_config)) {
9929 ret = PTR_ERR(pipe_config);
9930 pipe_config = NULL;
9931
9932 goto out;
9933 }
9934 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9935 "[modeset]");
9936 to_intel_crtc(crtc)->new_config = pipe_config;
9937 }
9938
9939 /*
9940 * See if the config requires any additional preparation, e.g.
9941 * to adjust global state with pipes off. We need to do this
9942 * here so we can get the modeset_pipe updated config for the new
9943 * mode set on this crtc. For other crtcs we need to use the
9944 * adjusted_mode bits in the crtc directly.
9945 */
9946 if (IS_VALLEYVIEW(dev)) {
9947 valleyview_modeset_global_pipes(dev, &prepare_pipes);
9948
9949 /* may have added more to prepare_pipes than we should */
9950 prepare_pipes &= ~disable_pipes;
9951 }
9952
9953 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9954 intel_crtc_disable(&intel_crtc->base);
9955
9956 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9957 if (intel_crtc->base.enabled)
9958 dev_priv->display.crtc_disable(&intel_crtc->base);
9959 }
9960
9961 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9962 * to set it here already despite that we pass it down the callchain.
9963 */
9964 if (modeset_pipes) {
9965 crtc->mode = *mode;
9966 /* mode_set/enable/disable functions rely on a correct pipe
9967 * config. */
9968 to_intel_crtc(crtc)->config = *pipe_config;
9969 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
9970
9971 /*
9972 * Calculate and store various constants which
9973 * are later needed by vblank and swap-completion
9974 * timestamping. They are derived from true hwmode.
9975 */
9976 drm_calc_timestamping_constants(crtc,
9977 &pipe_config->adjusted_mode);
9978 }
9979
9980 /* Only after disabling all output pipelines that will be changed can we
9981 * update the the output configuration. */
9982 intel_modeset_update_state(dev, prepare_pipes);
9983
9984 if (dev_priv->display.modeset_global_resources)
9985 dev_priv->display.modeset_global_resources(dev);
9986
9987 /* Set up the DPLL and any encoders state that needs to adjust or depend
9988 * on the DPLL.
9989 */
9990 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
9991 ret = intel_crtc_mode_set(&intel_crtc->base,
9992 x, y, fb);
9993 if (ret)
9994 goto done;
9995 }
9996
9997 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
9998 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9999 dev_priv->display.crtc_enable(&intel_crtc->base);
10000
10001 /* FIXME: add subpixel order */
10002 done:
10003 if (ret && crtc->enabled)
10004 crtc->mode = *saved_mode;
10005
10006 out:
10007 kfree(pipe_config);
10008 kfree(saved_mode);
10009 return ret;
10010 }
10011
10012 static int intel_set_mode(struct drm_crtc *crtc,
10013 struct drm_display_mode *mode,
10014 int x, int y, struct drm_framebuffer *fb)
10015 {
10016 int ret;
10017
10018 ret = __intel_set_mode(crtc, mode, x, y, fb);
10019
10020 if (ret == 0)
10021 intel_modeset_check_state(crtc->dev);
10022
10023 return ret;
10024 }
10025
10026 void intel_crtc_restore_mode(struct drm_crtc *crtc)
10027 {
10028 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
10029 }
10030
10031 #undef for_each_intel_crtc_masked
10032
10033 static void intel_set_config_free(struct intel_set_config *config)
10034 {
10035 if (!config)
10036 return;
10037
10038 kfree(config->save_connector_encoders);
10039 kfree(config->save_encoder_crtcs);
10040 kfree(config->save_crtc_enabled);
10041 kfree(config);
10042 }
10043
10044 static int intel_set_config_save_state(struct drm_device *dev,
10045 struct intel_set_config *config)
10046 {
10047 struct drm_crtc *crtc;
10048 struct drm_encoder *encoder;
10049 struct drm_connector *connector;
10050 int count;
10051
10052 config->save_crtc_enabled =
10053 kcalloc(dev->mode_config.num_crtc,
10054 sizeof(bool), GFP_KERNEL);
10055 if (!config->save_crtc_enabled)
10056 return -ENOMEM;
10057
10058 config->save_encoder_crtcs =
10059 kcalloc(dev->mode_config.num_encoder,
10060 sizeof(struct drm_crtc *), GFP_KERNEL);
10061 if (!config->save_encoder_crtcs)
10062 return -ENOMEM;
10063
10064 config->save_connector_encoders =
10065 kcalloc(dev->mode_config.num_connector,
10066 sizeof(struct drm_encoder *), GFP_KERNEL);
10067 if (!config->save_connector_encoders)
10068 return -ENOMEM;
10069
10070 /* Copy data. Note that driver private data is not affected.
10071 * Should anything bad happen only the expected state is
10072 * restored, not the drivers personal bookkeeping.
10073 */
10074 count = 0;
10075 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10076 config->save_crtc_enabled[count++] = crtc->enabled;
10077 }
10078
10079 count = 0;
10080 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
10081 config->save_encoder_crtcs[count++] = encoder->crtc;
10082 }
10083
10084 count = 0;
10085 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10086 config->save_connector_encoders[count++] = connector->encoder;
10087 }
10088
10089 return 0;
10090 }
10091
10092 static void intel_set_config_restore_state(struct drm_device *dev,
10093 struct intel_set_config *config)
10094 {
10095 struct intel_crtc *crtc;
10096 struct intel_encoder *encoder;
10097 struct intel_connector *connector;
10098 int count;
10099
10100 count = 0;
10101 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
10102 crtc->new_enabled = config->save_crtc_enabled[count++];
10103
10104 if (crtc->new_enabled)
10105 crtc->new_config = &crtc->config;
10106 else
10107 crtc->new_config = NULL;
10108 }
10109
10110 count = 0;
10111 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10112 encoder->new_crtc =
10113 to_intel_crtc(config->save_encoder_crtcs[count++]);
10114 }
10115
10116 count = 0;
10117 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10118 connector->new_encoder =
10119 to_intel_encoder(config->save_connector_encoders[count++]);
10120 }
10121 }
10122
10123 static bool
10124 is_crtc_connector_off(struct drm_mode_set *set)
10125 {
10126 int i;
10127
10128 if (set->num_connectors == 0)
10129 return false;
10130
10131 if (WARN_ON(set->connectors == NULL))
10132 return false;
10133
10134 for (i = 0; i < set->num_connectors; i++)
10135 if (set->connectors[i]->encoder &&
10136 set->connectors[i]->encoder->crtc == set->crtc &&
10137 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
10138 return true;
10139
10140 return false;
10141 }
10142
10143 static void
10144 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
10145 struct intel_set_config *config)
10146 {
10147
10148 /* We should be able to check here if the fb has the same properties
10149 * and then just flip_or_move it */
10150 if (is_crtc_connector_off(set)) {
10151 config->mode_changed = true;
10152 } else if (set->crtc->fb != set->fb) {
10153 /* If we have no fb then treat it as a full mode set */
10154 if (set->crtc->fb == NULL) {
10155 struct intel_crtc *intel_crtc =
10156 to_intel_crtc(set->crtc);
10157
10158 if (intel_crtc->active && i915.fastboot) {
10159 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
10160 config->fb_changed = true;
10161 } else {
10162 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
10163 config->mode_changed = true;
10164 }
10165 } else if (set->fb == NULL) {
10166 config->mode_changed = true;
10167 } else if (set->fb->pixel_format !=
10168 set->crtc->fb->pixel_format) {
10169 config->mode_changed = true;
10170 } else {
10171 config->fb_changed = true;
10172 }
10173 }
10174
10175 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
10176 config->fb_changed = true;
10177
10178 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
10179 DRM_DEBUG_KMS("modes are different, full mode set\n");
10180 drm_mode_debug_printmodeline(&set->crtc->mode);
10181 drm_mode_debug_printmodeline(set->mode);
10182 config->mode_changed = true;
10183 }
10184
10185 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
10186 set->crtc->base.id, config->mode_changed, config->fb_changed);
10187 }
10188
10189 static int
10190 intel_modeset_stage_output_state(struct drm_device *dev,
10191 struct drm_mode_set *set,
10192 struct intel_set_config *config)
10193 {
10194 struct intel_connector *connector;
10195 struct intel_encoder *encoder;
10196 struct intel_crtc *crtc;
10197 int ro;
10198
10199 /* The upper layers ensure that we either disable a crtc or have a list
10200 * of connectors. For paranoia, double-check this. */
10201 WARN_ON(!set->fb && (set->num_connectors != 0));
10202 WARN_ON(set->fb && (set->num_connectors == 0));
10203
10204 list_for_each_entry(connector, &dev->mode_config.connector_list,
10205 base.head) {
10206 /* Otherwise traverse passed in connector list and get encoders
10207 * for them. */
10208 for (ro = 0; ro < set->num_connectors; ro++) {
10209 if (set->connectors[ro] == &connector->base) {
10210 connector->new_encoder = connector->encoder;
10211 break;
10212 }
10213 }
10214
10215 /* If we disable the crtc, disable all its connectors. Also, if
10216 * the connector is on the changing crtc but not on the new
10217 * connector list, disable it. */
10218 if ((!set->fb || ro == set->num_connectors) &&
10219 connector->base.encoder &&
10220 connector->base.encoder->crtc == set->crtc) {
10221 connector->new_encoder = NULL;
10222
10223 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
10224 connector->base.base.id,
10225 drm_get_connector_name(&connector->base));
10226 }
10227
10228
10229 if (&connector->new_encoder->base != connector->base.encoder) {
10230 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
10231 config->mode_changed = true;
10232 }
10233 }
10234 /* connector->new_encoder is now updated for all connectors. */
10235
10236 /* Update crtc of enabled connectors. */
10237 list_for_each_entry(connector, &dev->mode_config.connector_list,
10238 base.head) {
10239 struct drm_crtc *new_crtc;
10240
10241 if (!connector->new_encoder)
10242 continue;
10243
10244 new_crtc = connector->new_encoder->base.crtc;
10245
10246 for (ro = 0; ro < set->num_connectors; ro++) {
10247 if (set->connectors[ro] == &connector->base)
10248 new_crtc = set->crtc;
10249 }
10250
10251 /* Make sure the new CRTC will work with the encoder */
10252 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
10253 new_crtc)) {
10254 return -EINVAL;
10255 }
10256 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
10257
10258 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
10259 connector->base.base.id,
10260 drm_get_connector_name(&connector->base),
10261 new_crtc->base.id);
10262 }
10263
10264 /* Check for any encoders that needs to be disabled. */
10265 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10266 base.head) {
10267 int num_connectors = 0;
10268 list_for_each_entry(connector,
10269 &dev->mode_config.connector_list,
10270 base.head) {
10271 if (connector->new_encoder == encoder) {
10272 WARN_ON(!connector->new_encoder->new_crtc);
10273 num_connectors++;
10274 }
10275 }
10276
10277 if (num_connectors == 0)
10278 encoder->new_crtc = NULL;
10279 else if (num_connectors > 1)
10280 return -EINVAL;
10281
10282 /* Only now check for crtc changes so we don't miss encoders
10283 * that will be disabled. */
10284 if (&encoder->new_crtc->base != encoder->base.crtc) {
10285 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
10286 config->mode_changed = true;
10287 }
10288 }
10289 /* Now we've also updated encoder->new_crtc for all encoders. */
10290
10291 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10292 base.head) {
10293 crtc->new_enabled = false;
10294
10295 list_for_each_entry(encoder,
10296 &dev->mode_config.encoder_list,
10297 base.head) {
10298 if (encoder->new_crtc == crtc) {
10299 crtc->new_enabled = true;
10300 break;
10301 }
10302 }
10303
10304 if (crtc->new_enabled != crtc->base.enabled) {
10305 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
10306 crtc->new_enabled ? "en" : "dis");
10307 config->mode_changed = true;
10308 }
10309
10310 if (crtc->new_enabled)
10311 crtc->new_config = &crtc->config;
10312 else
10313 crtc->new_config = NULL;
10314 }
10315
10316 return 0;
10317 }
10318
10319 static void disable_crtc_nofb(struct intel_crtc *crtc)
10320 {
10321 struct drm_device *dev = crtc->base.dev;
10322 struct intel_encoder *encoder;
10323 struct intel_connector *connector;
10324
10325 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
10326 pipe_name(crtc->pipe));
10327
10328 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10329 if (connector->new_encoder &&
10330 connector->new_encoder->new_crtc == crtc)
10331 connector->new_encoder = NULL;
10332 }
10333
10334 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10335 if (encoder->new_crtc == crtc)
10336 encoder->new_crtc = NULL;
10337 }
10338
10339 crtc->new_enabled = false;
10340 crtc->new_config = NULL;
10341 }
10342
10343 static int intel_crtc_set_config(struct drm_mode_set *set)
10344 {
10345 struct drm_device *dev;
10346 struct drm_mode_set save_set;
10347 struct intel_set_config *config;
10348 int ret;
10349
10350 BUG_ON(!set);
10351 BUG_ON(!set->crtc);
10352 BUG_ON(!set->crtc->helper_private);
10353
10354 /* Enforce sane interface api - has been abused by the fb helper. */
10355 BUG_ON(!set->mode && set->fb);
10356 BUG_ON(set->fb && set->num_connectors == 0);
10357
10358 if (set->fb) {
10359 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
10360 set->crtc->base.id, set->fb->base.id,
10361 (int)set->num_connectors, set->x, set->y);
10362 } else {
10363 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
10364 }
10365
10366 dev = set->crtc->dev;
10367
10368 ret = -ENOMEM;
10369 config = kzalloc(sizeof(*config), GFP_KERNEL);
10370 if (!config)
10371 goto out_config;
10372
10373 ret = intel_set_config_save_state(dev, config);
10374 if (ret)
10375 goto out_config;
10376
10377 save_set.crtc = set->crtc;
10378 save_set.mode = &set->crtc->mode;
10379 save_set.x = set->crtc->x;
10380 save_set.y = set->crtc->y;
10381 save_set.fb = set->crtc->fb;
10382
10383 /* Compute whether we need a full modeset, only an fb base update or no
10384 * change at all. In the future we might also check whether only the
10385 * mode changed, e.g. for LVDS where we only change the panel fitter in
10386 * such cases. */
10387 intel_set_config_compute_mode_changes(set, config);
10388
10389 ret = intel_modeset_stage_output_state(dev, set, config);
10390 if (ret)
10391 goto fail;
10392
10393 if (config->mode_changed) {
10394 ret = intel_set_mode(set->crtc, set->mode,
10395 set->x, set->y, set->fb);
10396 } else if (config->fb_changed) {
10397 intel_crtc_wait_for_pending_flips(set->crtc);
10398
10399 ret = intel_pipe_set_base(set->crtc,
10400 set->x, set->y, set->fb);
10401 /*
10402 * In the fastboot case this may be our only check of the
10403 * state after boot. It would be better to only do it on
10404 * the first update, but we don't have a nice way of doing that
10405 * (and really, set_config isn't used much for high freq page
10406 * flipping, so increasing its cost here shouldn't be a big
10407 * deal).
10408 */
10409 if (i915.fastboot && ret == 0)
10410 intel_modeset_check_state(set->crtc->dev);
10411 }
10412
10413 if (ret) {
10414 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
10415 set->crtc->base.id, ret);
10416 fail:
10417 intel_set_config_restore_state(dev, config);
10418
10419 /*
10420 * HACK: if the pipe was on, but we didn't have a framebuffer,
10421 * force the pipe off to avoid oopsing in the modeset code
10422 * due to fb==NULL. This should only happen during boot since
10423 * we don't yet reconstruct the FB from the hardware state.
10424 */
10425 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
10426 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
10427
10428 /* Try to restore the config */
10429 if (config->mode_changed &&
10430 intel_set_mode(save_set.crtc, save_set.mode,
10431 save_set.x, save_set.y, save_set.fb))
10432 DRM_ERROR("failed to restore config after modeset failure\n");
10433 }
10434
10435 out_config:
10436 intel_set_config_free(config);
10437 return ret;
10438 }
10439
10440 static const struct drm_crtc_funcs intel_crtc_funcs = {
10441 .cursor_set = intel_crtc_cursor_set,
10442 .cursor_move = intel_crtc_cursor_move,
10443 .gamma_set = intel_crtc_gamma_set,
10444 .set_config = intel_crtc_set_config,
10445 .destroy = intel_crtc_destroy,
10446 .page_flip = intel_crtc_page_flip,
10447 };
10448
10449 static void intel_cpu_pll_init(struct drm_device *dev)
10450 {
10451 if (HAS_DDI(dev))
10452 intel_ddi_pll_init(dev);
10453 }
10454
10455 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
10456 struct intel_shared_dpll *pll,
10457 struct intel_dpll_hw_state *hw_state)
10458 {
10459 uint32_t val;
10460
10461 val = I915_READ(PCH_DPLL(pll->id));
10462 hw_state->dpll = val;
10463 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
10464 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
10465
10466 return val & DPLL_VCO_ENABLE;
10467 }
10468
10469 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
10470 struct intel_shared_dpll *pll)
10471 {
10472 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
10473 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
10474 }
10475
10476 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
10477 struct intel_shared_dpll *pll)
10478 {
10479 /* PCH refclock must be enabled first */
10480 ibx_assert_pch_refclk_enabled(dev_priv);
10481
10482 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10483
10484 /* Wait for the clocks to stabilize. */
10485 POSTING_READ(PCH_DPLL(pll->id));
10486 udelay(150);
10487
10488 /* The pixel multiplier can only be updated once the
10489 * DPLL is enabled and the clocks are stable.
10490 *
10491 * So write it again.
10492 */
10493 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10494 POSTING_READ(PCH_DPLL(pll->id));
10495 udelay(200);
10496 }
10497
10498 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
10499 struct intel_shared_dpll *pll)
10500 {
10501 struct drm_device *dev = dev_priv->dev;
10502 struct intel_crtc *crtc;
10503
10504 /* Make sure no transcoder isn't still depending on us. */
10505 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
10506 if (intel_crtc_to_shared_dpll(crtc) == pll)
10507 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
10508 }
10509
10510 I915_WRITE(PCH_DPLL(pll->id), 0);
10511 POSTING_READ(PCH_DPLL(pll->id));
10512 udelay(200);
10513 }
10514
10515 static char *ibx_pch_dpll_names[] = {
10516 "PCH DPLL A",
10517 "PCH DPLL B",
10518 };
10519
10520 static void ibx_pch_dpll_init(struct drm_device *dev)
10521 {
10522 struct drm_i915_private *dev_priv = dev->dev_private;
10523 int i;
10524
10525 dev_priv->num_shared_dpll = 2;
10526
10527 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10528 dev_priv->shared_dplls[i].id = i;
10529 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
10530 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
10531 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
10532 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
10533 dev_priv->shared_dplls[i].get_hw_state =
10534 ibx_pch_dpll_get_hw_state;
10535 }
10536 }
10537
10538 static void intel_shared_dpll_init(struct drm_device *dev)
10539 {
10540 struct drm_i915_private *dev_priv = dev->dev_private;
10541
10542 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
10543 ibx_pch_dpll_init(dev);
10544 else
10545 dev_priv->num_shared_dpll = 0;
10546
10547 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
10548 }
10549
10550 static void intel_crtc_init(struct drm_device *dev, int pipe)
10551 {
10552 struct drm_i915_private *dev_priv = dev->dev_private;
10553 struct intel_crtc *intel_crtc;
10554 int i;
10555
10556 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
10557 if (intel_crtc == NULL)
10558 return;
10559
10560 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
10561
10562 if (IS_GEN2(dev)) {
10563 intel_crtc->max_cursor_width = GEN2_CURSOR_WIDTH;
10564 intel_crtc->max_cursor_height = GEN2_CURSOR_HEIGHT;
10565 } else {
10566 intel_crtc->max_cursor_width = CURSOR_WIDTH;
10567 intel_crtc->max_cursor_height = CURSOR_HEIGHT;
10568 }
10569 dev->mode_config.cursor_width = intel_crtc->max_cursor_width;
10570 dev->mode_config.cursor_height = intel_crtc->max_cursor_height;
10571
10572 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
10573 for (i = 0; i < 256; i++) {
10574 intel_crtc->lut_r[i] = i;
10575 intel_crtc->lut_g[i] = i;
10576 intel_crtc->lut_b[i] = i;
10577 }
10578
10579 /*
10580 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
10581 * is hooked to plane B. Hence we want plane A feeding pipe B.
10582 */
10583 intel_crtc->pipe = pipe;
10584 intel_crtc->plane = pipe;
10585 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
10586 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
10587 intel_crtc->plane = !pipe;
10588 }
10589
10590 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
10591 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
10592 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
10593 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
10594
10595 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
10596 }
10597
10598 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
10599 {
10600 struct drm_encoder *encoder = connector->base.encoder;
10601
10602 WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex));
10603
10604 if (!encoder)
10605 return INVALID_PIPE;
10606
10607 return to_intel_crtc(encoder->crtc)->pipe;
10608 }
10609
10610 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
10611 struct drm_file *file)
10612 {
10613 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
10614 struct drm_mode_object *drmmode_obj;
10615 struct intel_crtc *crtc;
10616
10617 if (!drm_core_check_feature(dev, DRIVER_MODESET))
10618 return -ENODEV;
10619
10620 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
10621 DRM_MODE_OBJECT_CRTC);
10622
10623 if (!drmmode_obj) {
10624 DRM_ERROR("no such CRTC id\n");
10625 return -ENOENT;
10626 }
10627
10628 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
10629 pipe_from_crtc_id->pipe = crtc->pipe;
10630
10631 return 0;
10632 }
10633
10634 static int intel_encoder_clones(struct intel_encoder *encoder)
10635 {
10636 struct drm_device *dev = encoder->base.dev;
10637 struct intel_encoder *source_encoder;
10638 int index_mask = 0;
10639 int entry = 0;
10640
10641 list_for_each_entry(source_encoder,
10642 &dev->mode_config.encoder_list, base.head) {
10643 if (encoders_cloneable(encoder, source_encoder))
10644 index_mask |= (1 << entry);
10645
10646 entry++;
10647 }
10648
10649 return index_mask;
10650 }
10651
10652 static bool has_edp_a(struct drm_device *dev)
10653 {
10654 struct drm_i915_private *dev_priv = dev->dev_private;
10655
10656 if (!IS_MOBILE(dev))
10657 return false;
10658
10659 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
10660 return false;
10661
10662 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
10663 return false;
10664
10665 return true;
10666 }
10667
10668 const char *intel_output_name(int output)
10669 {
10670 static const char *names[] = {
10671 [INTEL_OUTPUT_UNUSED] = "Unused",
10672 [INTEL_OUTPUT_ANALOG] = "Analog",
10673 [INTEL_OUTPUT_DVO] = "DVO",
10674 [INTEL_OUTPUT_SDVO] = "SDVO",
10675 [INTEL_OUTPUT_LVDS] = "LVDS",
10676 [INTEL_OUTPUT_TVOUT] = "TV",
10677 [INTEL_OUTPUT_HDMI] = "HDMI",
10678 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
10679 [INTEL_OUTPUT_EDP] = "eDP",
10680 [INTEL_OUTPUT_DSI] = "DSI",
10681 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
10682 };
10683
10684 if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
10685 return "Invalid";
10686
10687 return names[output];
10688 }
10689
10690 static void intel_setup_outputs(struct drm_device *dev)
10691 {
10692 struct drm_i915_private *dev_priv = dev->dev_private;
10693 struct intel_encoder *encoder;
10694 bool dpd_is_edp = false;
10695
10696 intel_lvds_init(dev);
10697
10698 if (!IS_ULT(dev))
10699 intel_crt_init(dev);
10700
10701 if (HAS_DDI(dev)) {
10702 int found;
10703
10704 /* Haswell uses DDI functions to detect digital outputs */
10705 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
10706 /* DDI A only supports eDP */
10707 if (found)
10708 intel_ddi_init(dev, PORT_A);
10709
10710 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
10711 * register */
10712 found = I915_READ(SFUSE_STRAP);
10713
10714 if (found & SFUSE_STRAP_DDIB_DETECTED)
10715 intel_ddi_init(dev, PORT_B);
10716 if (found & SFUSE_STRAP_DDIC_DETECTED)
10717 intel_ddi_init(dev, PORT_C);
10718 if (found & SFUSE_STRAP_DDID_DETECTED)
10719 intel_ddi_init(dev, PORT_D);
10720 } else if (HAS_PCH_SPLIT(dev)) {
10721 int found;
10722 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
10723
10724 if (has_edp_a(dev))
10725 intel_dp_init(dev, DP_A, PORT_A);
10726
10727 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
10728 /* PCH SDVOB multiplex with HDMIB */
10729 found = intel_sdvo_init(dev, PCH_SDVOB, true);
10730 if (!found)
10731 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
10732 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
10733 intel_dp_init(dev, PCH_DP_B, PORT_B);
10734 }
10735
10736 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
10737 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
10738
10739 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
10740 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
10741
10742 if (I915_READ(PCH_DP_C) & DP_DETECTED)
10743 intel_dp_init(dev, PCH_DP_C, PORT_C);
10744
10745 if (I915_READ(PCH_DP_D) & DP_DETECTED)
10746 intel_dp_init(dev, PCH_DP_D, PORT_D);
10747 } else if (IS_VALLEYVIEW(dev)) {
10748 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
10749 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
10750 PORT_B);
10751 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
10752 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
10753 }
10754
10755 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
10756 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
10757 PORT_C);
10758 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
10759 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
10760 }
10761
10762 intel_dsi_init(dev);
10763 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
10764 bool found = false;
10765
10766 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10767 DRM_DEBUG_KMS("probing SDVOB\n");
10768 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
10769 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
10770 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
10771 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
10772 }
10773
10774 if (!found && SUPPORTS_INTEGRATED_DP(dev))
10775 intel_dp_init(dev, DP_B, PORT_B);
10776 }
10777
10778 /* Before G4X SDVOC doesn't have its own detect register */
10779
10780 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10781 DRM_DEBUG_KMS("probing SDVOC\n");
10782 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
10783 }
10784
10785 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
10786
10787 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
10788 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
10789 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
10790 }
10791 if (SUPPORTS_INTEGRATED_DP(dev))
10792 intel_dp_init(dev, DP_C, PORT_C);
10793 }
10794
10795 if (SUPPORTS_INTEGRATED_DP(dev) &&
10796 (I915_READ(DP_D) & DP_DETECTED))
10797 intel_dp_init(dev, DP_D, PORT_D);
10798 } else if (IS_GEN2(dev))
10799 intel_dvo_init(dev);
10800
10801 if (SUPPORTS_TV(dev))
10802 intel_tv_init(dev);
10803
10804 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10805 encoder->base.possible_crtcs = encoder->crtc_mask;
10806 encoder->base.possible_clones =
10807 intel_encoder_clones(encoder);
10808 }
10809
10810 intel_init_pch_refclk(dev);
10811
10812 drm_helper_move_panel_connectors_to_head(dev);
10813 }
10814
10815 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
10816 {
10817 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10818
10819 drm_framebuffer_cleanup(fb);
10820 WARN_ON(!intel_fb->obj->framebuffer_references--);
10821 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
10822 kfree(intel_fb);
10823 }
10824
10825 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
10826 struct drm_file *file,
10827 unsigned int *handle)
10828 {
10829 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10830 struct drm_i915_gem_object *obj = intel_fb->obj;
10831
10832 return drm_gem_handle_create(file, &obj->base, handle);
10833 }
10834
10835 static const struct drm_framebuffer_funcs intel_fb_funcs = {
10836 .destroy = intel_user_framebuffer_destroy,
10837 .create_handle = intel_user_framebuffer_create_handle,
10838 };
10839
10840 static int intel_framebuffer_init(struct drm_device *dev,
10841 struct intel_framebuffer *intel_fb,
10842 struct drm_mode_fb_cmd2 *mode_cmd,
10843 struct drm_i915_gem_object *obj)
10844 {
10845 int aligned_height;
10846 int pitch_limit;
10847 int ret;
10848
10849 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
10850
10851 if (obj->tiling_mode == I915_TILING_Y) {
10852 DRM_DEBUG("hardware does not support tiling Y\n");
10853 return -EINVAL;
10854 }
10855
10856 if (mode_cmd->pitches[0] & 63) {
10857 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
10858 mode_cmd->pitches[0]);
10859 return -EINVAL;
10860 }
10861
10862 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
10863 pitch_limit = 32*1024;
10864 } else if (INTEL_INFO(dev)->gen >= 4) {
10865 if (obj->tiling_mode)
10866 pitch_limit = 16*1024;
10867 else
10868 pitch_limit = 32*1024;
10869 } else if (INTEL_INFO(dev)->gen >= 3) {
10870 if (obj->tiling_mode)
10871 pitch_limit = 8*1024;
10872 else
10873 pitch_limit = 16*1024;
10874 } else
10875 /* XXX DSPC is limited to 4k tiled */
10876 pitch_limit = 8*1024;
10877
10878 if (mode_cmd->pitches[0] > pitch_limit) {
10879 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
10880 obj->tiling_mode ? "tiled" : "linear",
10881 mode_cmd->pitches[0], pitch_limit);
10882 return -EINVAL;
10883 }
10884
10885 if (obj->tiling_mode != I915_TILING_NONE &&
10886 mode_cmd->pitches[0] != obj->stride) {
10887 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
10888 mode_cmd->pitches[0], obj->stride);
10889 return -EINVAL;
10890 }
10891
10892 /* Reject formats not supported by any plane early. */
10893 switch (mode_cmd->pixel_format) {
10894 case DRM_FORMAT_C8:
10895 case DRM_FORMAT_RGB565:
10896 case DRM_FORMAT_XRGB8888:
10897 case DRM_FORMAT_ARGB8888:
10898 break;
10899 case DRM_FORMAT_XRGB1555:
10900 case DRM_FORMAT_ARGB1555:
10901 if (INTEL_INFO(dev)->gen > 3) {
10902 DRM_DEBUG("unsupported pixel format: %s\n",
10903 drm_get_format_name(mode_cmd->pixel_format));
10904 return -EINVAL;
10905 }
10906 break;
10907 case DRM_FORMAT_XBGR8888:
10908 case DRM_FORMAT_ABGR8888:
10909 case DRM_FORMAT_XRGB2101010:
10910 case DRM_FORMAT_ARGB2101010:
10911 case DRM_FORMAT_XBGR2101010:
10912 case DRM_FORMAT_ABGR2101010:
10913 if (INTEL_INFO(dev)->gen < 4) {
10914 DRM_DEBUG("unsupported pixel format: %s\n",
10915 drm_get_format_name(mode_cmd->pixel_format));
10916 return -EINVAL;
10917 }
10918 break;
10919 case DRM_FORMAT_YUYV:
10920 case DRM_FORMAT_UYVY:
10921 case DRM_FORMAT_YVYU:
10922 case DRM_FORMAT_VYUY:
10923 if (INTEL_INFO(dev)->gen < 5) {
10924 DRM_DEBUG("unsupported pixel format: %s\n",
10925 drm_get_format_name(mode_cmd->pixel_format));
10926 return -EINVAL;
10927 }
10928 break;
10929 default:
10930 DRM_DEBUG("unsupported pixel format: %s\n",
10931 drm_get_format_name(mode_cmd->pixel_format));
10932 return -EINVAL;
10933 }
10934
10935 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
10936 if (mode_cmd->offsets[0] != 0)
10937 return -EINVAL;
10938
10939 aligned_height = intel_align_height(dev, mode_cmd->height,
10940 obj->tiling_mode);
10941 /* FIXME drm helper for size checks (especially planar formats)? */
10942 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
10943 return -EINVAL;
10944
10945 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
10946 intel_fb->obj = obj;
10947 intel_fb->obj->framebuffer_references++;
10948
10949 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
10950 if (ret) {
10951 DRM_ERROR("framebuffer init failed %d\n", ret);
10952 return ret;
10953 }
10954
10955 return 0;
10956 }
10957
10958 static struct drm_framebuffer *
10959 intel_user_framebuffer_create(struct drm_device *dev,
10960 struct drm_file *filp,
10961 struct drm_mode_fb_cmd2 *mode_cmd)
10962 {
10963 struct drm_i915_gem_object *obj;
10964
10965 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
10966 mode_cmd->handles[0]));
10967 if (&obj->base == NULL)
10968 return ERR_PTR(-ENOENT);
10969
10970 return intel_framebuffer_create(dev, mode_cmd, obj);
10971 }
10972
10973 #ifndef CONFIG_DRM_I915_FBDEV
10974 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
10975 {
10976 }
10977 #endif
10978
10979 static const struct drm_mode_config_funcs intel_mode_funcs = {
10980 .fb_create = intel_user_framebuffer_create,
10981 .output_poll_changed = intel_fbdev_output_poll_changed,
10982 };
10983
10984 /* Set up chip specific display functions */
10985 static void intel_init_display(struct drm_device *dev)
10986 {
10987 struct drm_i915_private *dev_priv = dev->dev_private;
10988
10989 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
10990 dev_priv->display.find_dpll = g4x_find_best_dpll;
10991 else if (IS_VALLEYVIEW(dev))
10992 dev_priv->display.find_dpll = vlv_find_best_dpll;
10993 else if (IS_PINEVIEW(dev))
10994 dev_priv->display.find_dpll = pnv_find_best_dpll;
10995 else
10996 dev_priv->display.find_dpll = i9xx_find_best_dpll;
10997
10998 if (HAS_DDI(dev)) {
10999 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
11000 dev_priv->display.get_plane_config = ironlake_get_plane_config;
11001 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
11002 dev_priv->display.crtc_enable = haswell_crtc_enable;
11003 dev_priv->display.crtc_disable = haswell_crtc_disable;
11004 dev_priv->display.off = haswell_crtc_off;
11005 dev_priv->display.update_primary_plane =
11006 ironlake_update_primary_plane;
11007 } else if (HAS_PCH_SPLIT(dev)) {
11008 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
11009 dev_priv->display.get_plane_config = ironlake_get_plane_config;
11010 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
11011 dev_priv->display.crtc_enable = ironlake_crtc_enable;
11012 dev_priv->display.crtc_disable = ironlake_crtc_disable;
11013 dev_priv->display.off = ironlake_crtc_off;
11014 dev_priv->display.update_primary_plane =
11015 ironlake_update_primary_plane;
11016 } else if (IS_VALLEYVIEW(dev)) {
11017 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11018 dev_priv->display.get_plane_config = i9xx_get_plane_config;
11019 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
11020 dev_priv->display.crtc_enable = valleyview_crtc_enable;
11021 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11022 dev_priv->display.off = i9xx_crtc_off;
11023 dev_priv->display.update_primary_plane =
11024 i9xx_update_primary_plane;
11025 } else {
11026 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11027 dev_priv->display.get_plane_config = i9xx_get_plane_config;
11028 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
11029 dev_priv->display.crtc_enable = i9xx_crtc_enable;
11030 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11031 dev_priv->display.off = i9xx_crtc_off;
11032 dev_priv->display.update_primary_plane =
11033 i9xx_update_primary_plane;
11034 }
11035
11036 /* Returns the core display clock speed */
11037 if (IS_VALLEYVIEW(dev))
11038 dev_priv->display.get_display_clock_speed =
11039 valleyview_get_display_clock_speed;
11040 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
11041 dev_priv->display.get_display_clock_speed =
11042 i945_get_display_clock_speed;
11043 else if (IS_I915G(dev))
11044 dev_priv->display.get_display_clock_speed =
11045 i915_get_display_clock_speed;
11046 else if (IS_I945GM(dev) || IS_845G(dev))
11047 dev_priv->display.get_display_clock_speed =
11048 i9xx_misc_get_display_clock_speed;
11049 else if (IS_PINEVIEW(dev))
11050 dev_priv->display.get_display_clock_speed =
11051 pnv_get_display_clock_speed;
11052 else if (IS_I915GM(dev))
11053 dev_priv->display.get_display_clock_speed =
11054 i915gm_get_display_clock_speed;
11055 else if (IS_I865G(dev))
11056 dev_priv->display.get_display_clock_speed =
11057 i865_get_display_clock_speed;
11058 else if (IS_I85X(dev))
11059 dev_priv->display.get_display_clock_speed =
11060 i855_get_display_clock_speed;
11061 else /* 852, 830 */
11062 dev_priv->display.get_display_clock_speed =
11063 i830_get_display_clock_speed;
11064
11065 if (HAS_PCH_SPLIT(dev)) {
11066 if (IS_GEN5(dev)) {
11067 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
11068 dev_priv->display.write_eld = ironlake_write_eld;
11069 } else if (IS_GEN6(dev)) {
11070 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
11071 dev_priv->display.write_eld = ironlake_write_eld;
11072 } else if (IS_IVYBRIDGE(dev)) {
11073 /* FIXME: detect B0+ stepping and use auto training */
11074 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
11075 dev_priv->display.write_eld = ironlake_write_eld;
11076 dev_priv->display.modeset_global_resources =
11077 ivb_modeset_global_resources;
11078 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
11079 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
11080 dev_priv->display.write_eld = haswell_write_eld;
11081 dev_priv->display.modeset_global_resources =
11082 haswell_modeset_global_resources;
11083 }
11084 } else if (IS_G4X(dev)) {
11085 dev_priv->display.write_eld = g4x_write_eld;
11086 } else if (IS_VALLEYVIEW(dev)) {
11087 dev_priv->display.modeset_global_resources =
11088 valleyview_modeset_global_resources;
11089 dev_priv->display.write_eld = ironlake_write_eld;
11090 }
11091
11092 /* Default just returns -ENODEV to indicate unsupported */
11093 dev_priv->display.queue_flip = intel_default_queue_flip;
11094
11095 switch (INTEL_INFO(dev)->gen) {
11096 case 2:
11097 dev_priv->display.queue_flip = intel_gen2_queue_flip;
11098 break;
11099
11100 case 3:
11101 dev_priv->display.queue_flip = intel_gen3_queue_flip;
11102 break;
11103
11104 case 4:
11105 case 5:
11106 dev_priv->display.queue_flip = intel_gen4_queue_flip;
11107 break;
11108
11109 case 6:
11110 dev_priv->display.queue_flip = intel_gen6_queue_flip;
11111 break;
11112 case 7:
11113 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
11114 dev_priv->display.queue_flip = intel_gen7_queue_flip;
11115 break;
11116 }
11117
11118 intel_panel_init_backlight_funcs(dev);
11119 }
11120
11121 /*
11122 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
11123 * resume, or other times. This quirk makes sure that's the case for
11124 * affected systems.
11125 */
11126 static void quirk_pipea_force(struct drm_device *dev)
11127 {
11128 struct drm_i915_private *dev_priv = dev->dev_private;
11129
11130 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
11131 DRM_INFO("applying pipe a force quirk\n");
11132 }
11133
11134 /*
11135 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
11136 */
11137 static void quirk_ssc_force_disable(struct drm_device *dev)
11138 {
11139 struct drm_i915_private *dev_priv = dev->dev_private;
11140 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
11141 DRM_INFO("applying lvds SSC disable quirk\n");
11142 }
11143
11144 /*
11145 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
11146 * brightness value
11147 */
11148 static void quirk_invert_brightness(struct drm_device *dev)
11149 {
11150 struct drm_i915_private *dev_priv = dev->dev_private;
11151 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
11152 DRM_INFO("applying inverted panel brightness quirk\n");
11153 }
11154
11155 struct intel_quirk {
11156 int device;
11157 int subsystem_vendor;
11158 int subsystem_device;
11159 void (*hook)(struct drm_device *dev);
11160 };
11161
11162 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
11163 struct intel_dmi_quirk {
11164 void (*hook)(struct drm_device *dev);
11165 const struct dmi_system_id (*dmi_id_list)[];
11166 };
11167
11168 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
11169 {
11170 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
11171 return 1;
11172 }
11173
11174 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
11175 {
11176 .dmi_id_list = &(const struct dmi_system_id[]) {
11177 {
11178 .callback = intel_dmi_reverse_brightness,
11179 .ident = "NCR Corporation",
11180 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
11181 DMI_MATCH(DMI_PRODUCT_NAME, ""),
11182 },
11183 },
11184 { } /* terminating entry */
11185 },
11186 .hook = quirk_invert_brightness,
11187 },
11188 };
11189
11190 static struct intel_quirk intel_quirks[] = {
11191 /* HP Mini needs pipe A force quirk (LP: #322104) */
11192 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
11193
11194 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
11195 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
11196
11197 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
11198 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
11199
11200 /* 830 needs to leave pipe A & dpll A up */
11201 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
11202
11203 /* Lenovo U160 cannot use SSC on LVDS */
11204 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
11205
11206 /* Sony Vaio Y cannot use SSC on LVDS */
11207 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
11208
11209 /* Acer Aspire 5734Z must invert backlight brightness */
11210 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
11211
11212 /* Acer/eMachines G725 */
11213 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
11214
11215 /* Acer/eMachines e725 */
11216 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
11217
11218 /* Acer/Packard Bell NCL20 */
11219 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
11220
11221 /* Acer Aspire 4736Z */
11222 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
11223
11224 /* Acer Aspire 5336 */
11225 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
11226 };
11227
11228 static void intel_init_quirks(struct drm_device *dev)
11229 {
11230 struct pci_dev *d = dev->pdev;
11231 int i;
11232
11233 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
11234 struct intel_quirk *q = &intel_quirks[i];
11235
11236 if (d->device == q->device &&
11237 (d->subsystem_vendor == q->subsystem_vendor ||
11238 q->subsystem_vendor == PCI_ANY_ID) &&
11239 (d->subsystem_device == q->subsystem_device ||
11240 q->subsystem_device == PCI_ANY_ID))
11241 q->hook(dev);
11242 }
11243 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
11244 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
11245 intel_dmi_quirks[i].hook(dev);
11246 }
11247 }
11248
11249 /* Disable the VGA plane that we never use */
11250 static void i915_disable_vga(struct drm_device *dev)
11251 {
11252 struct drm_i915_private *dev_priv = dev->dev_private;
11253 u8 sr1;
11254 u32 vga_reg = i915_vgacntrl_reg(dev);
11255
11256 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
11257 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
11258 outb(SR01, VGA_SR_INDEX);
11259 sr1 = inb(VGA_SR_DATA);
11260 outb(sr1 | 1<<5, VGA_SR_DATA);
11261 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
11262 udelay(300);
11263
11264 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
11265 POSTING_READ(vga_reg);
11266 }
11267
11268 void intel_modeset_init_hw(struct drm_device *dev)
11269 {
11270 intel_prepare_ddi(dev);
11271
11272 intel_init_clock_gating(dev);
11273
11274 intel_reset_dpio(dev);
11275
11276 mutex_lock(&dev->struct_mutex);
11277 intel_enable_gt_powersave(dev);
11278 mutex_unlock(&dev->struct_mutex);
11279 }
11280
11281 void intel_modeset_suspend_hw(struct drm_device *dev)
11282 {
11283 intel_suspend_hw(dev);
11284 }
11285
11286 void intel_modeset_init(struct drm_device *dev)
11287 {
11288 struct drm_i915_private *dev_priv = dev->dev_private;
11289 int sprite, ret;
11290 enum pipe pipe;
11291 struct intel_crtc *crtc;
11292
11293 drm_mode_config_init(dev);
11294
11295 dev->mode_config.min_width = 0;
11296 dev->mode_config.min_height = 0;
11297
11298 dev->mode_config.preferred_depth = 24;
11299 dev->mode_config.prefer_shadow = 1;
11300
11301 dev->mode_config.funcs = &intel_mode_funcs;
11302
11303 intel_init_quirks(dev);
11304
11305 intel_init_pm(dev);
11306
11307 if (INTEL_INFO(dev)->num_pipes == 0)
11308 return;
11309
11310 intel_init_display(dev);
11311
11312 if (IS_GEN2(dev)) {
11313 dev->mode_config.max_width = 2048;
11314 dev->mode_config.max_height = 2048;
11315 } else if (IS_GEN3(dev)) {
11316 dev->mode_config.max_width = 4096;
11317 dev->mode_config.max_height = 4096;
11318 } else {
11319 dev->mode_config.max_width = 8192;
11320 dev->mode_config.max_height = 8192;
11321 }
11322 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
11323
11324 DRM_DEBUG_KMS("%d display pipe%s available.\n",
11325 INTEL_INFO(dev)->num_pipes,
11326 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
11327
11328 for_each_pipe(pipe) {
11329 intel_crtc_init(dev, pipe);
11330 for_each_sprite(pipe, sprite) {
11331 ret = intel_plane_init(dev, pipe, sprite);
11332 if (ret)
11333 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
11334 pipe_name(pipe), sprite_name(pipe, sprite), ret);
11335 }
11336 }
11337
11338 intel_init_dpio(dev);
11339 intel_reset_dpio(dev);
11340
11341 intel_cpu_pll_init(dev);
11342 intel_shared_dpll_init(dev);
11343
11344 /* Just disable it once at startup */
11345 i915_disable_vga(dev);
11346 intel_setup_outputs(dev);
11347
11348 /* Just in case the BIOS is doing something questionable. */
11349 intel_disable_fbc(dev);
11350
11351 mutex_lock(&dev->mode_config.mutex);
11352 intel_modeset_setup_hw_state(dev, false);
11353 mutex_unlock(&dev->mode_config.mutex);
11354
11355 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11356 base.head) {
11357 if (!crtc->active)
11358 continue;
11359
11360 /*
11361 * Note that reserving the BIOS fb up front prevents us
11362 * from stuffing other stolen allocations like the ring
11363 * on top. This prevents some ugliness at boot time, and
11364 * can even allow for smooth boot transitions if the BIOS
11365 * fb is large enough for the active pipe configuration.
11366 */
11367 if (dev_priv->display.get_plane_config) {
11368 dev_priv->display.get_plane_config(crtc,
11369 &crtc->plane_config);
11370 /*
11371 * If the fb is shared between multiple heads, we'll
11372 * just get the first one.
11373 */
11374 intel_find_plane_obj(crtc, &crtc->plane_config);
11375 }
11376 }
11377 }
11378
11379 static void
11380 intel_connector_break_all_links(struct intel_connector *connector)
11381 {
11382 connector->base.dpms = DRM_MODE_DPMS_OFF;
11383 connector->base.encoder = NULL;
11384 connector->encoder->connectors_active = false;
11385 connector->encoder->base.crtc = NULL;
11386 }
11387
11388 static void intel_enable_pipe_a(struct drm_device *dev)
11389 {
11390 struct intel_connector *connector;
11391 struct drm_connector *crt = NULL;
11392 struct intel_load_detect_pipe load_detect_temp;
11393
11394 /* We can't just switch on the pipe A, we need to set things up with a
11395 * proper mode and output configuration. As a gross hack, enable pipe A
11396 * by enabling the load detect pipe once. */
11397 list_for_each_entry(connector,
11398 &dev->mode_config.connector_list,
11399 base.head) {
11400 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
11401 crt = &connector->base;
11402 break;
11403 }
11404 }
11405
11406 if (!crt)
11407 return;
11408
11409 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
11410 intel_release_load_detect_pipe(crt, &load_detect_temp);
11411
11412
11413 }
11414
11415 static bool
11416 intel_check_plane_mapping(struct intel_crtc *crtc)
11417 {
11418 struct drm_device *dev = crtc->base.dev;
11419 struct drm_i915_private *dev_priv = dev->dev_private;
11420 u32 reg, val;
11421
11422 if (INTEL_INFO(dev)->num_pipes == 1)
11423 return true;
11424
11425 reg = DSPCNTR(!crtc->plane);
11426 val = I915_READ(reg);
11427
11428 if ((val & DISPLAY_PLANE_ENABLE) &&
11429 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
11430 return false;
11431
11432 return true;
11433 }
11434
11435 static void intel_sanitize_crtc(struct intel_crtc *crtc)
11436 {
11437 struct drm_device *dev = crtc->base.dev;
11438 struct drm_i915_private *dev_priv = dev->dev_private;
11439 u32 reg;
11440
11441 /* Clear any frame start delays used for debugging left by the BIOS */
11442 reg = PIPECONF(crtc->config.cpu_transcoder);
11443 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
11444
11445 /* We need to sanitize the plane -> pipe mapping first because this will
11446 * disable the crtc (and hence change the state) if it is wrong. Note
11447 * that gen4+ has a fixed plane -> pipe mapping. */
11448 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
11449 struct intel_connector *connector;
11450 bool plane;
11451
11452 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
11453 crtc->base.base.id);
11454
11455 /* Pipe has the wrong plane attached and the plane is active.
11456 * Temporarily change the plane mapping and disable everything
11457 * ... */
11458 plane = crtc->plane;
11459 crtc->plane = !plane;
11460 dev_priv->display.crtc_disable(&crtc->base);
11461 crtc->plane = plane;
11462
11463 /* ... and break all links. */
11464 list_for_each_entry(connector, &dev->mode_config.connector_list,
11465 base.head) {
11466 if (connector->encoder->base.crtc != &crtc->base)
11467 continue;
11468
11469 intel_connector_break_all_links(connector);
11470 }
11471
11472 WARN_ON(crtc->active);
11473 crtc->base.enabled = false;
11474 }
11475
11476 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
11477 crtc->pipe == PIPE_A && !crtc->active) {
11478 /* BIOS forgot to enable pipe A, this mostly happens after
11479 * resume. Force-enable the pipe to fix this, the update_dpms
11480 * call below we restore the pipe to the right state, but leave
11481 * the required bits on. */
11482 intel_enable_pipe_a(dev);
11483 }
11484
11485 /* Adjust the state of the output pipe according to whether we
11486 * have active connectors/encoders. */
11487 intel_crtc_update_dpms(&crtc->base);
11488
11489 if (crtc->active != crtc->base.enabled) {
11490 struct intel_encoder *encoder;
11491
11492 /* This can happen either due to bugs in the get_hw_state
11493 * functions or because the pipe is force-enabled due to the
11494 * pipe A quirk. */
11495 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
11496 crtc->base.base.id,
11497 crtc->base.enabled ? "enabled" : "disabled",
11498 crtc->active ? "enabled" : "disabled");
11499
11500 crtc->base.enabled = crtc->active;
11501
11502 /* Because we only establish the connector -> encoder ->
11503 * crtc links if something is active, this means the
11504 * crtc is now deactivated. Break the links. connector
11505 * -> encoder links are only establish when things are
11506 * actually up, hence no need to break them. */
11507 WARN_ON(crtc->active);
11508
11509 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
11510 WARN_ON(encoder->connectors_active);
11511 encoder->base.crtc = NULL;
11512 }
11513 }
11514 if (crtc->active) {
11515 /*
11516 * We start out with underrun reporting disabled to avoid races.
11517 * For correct bookkeeping mark this on active crtcs.
11518 *
11519 * No protection against concurrent access is required - at
11520 * worst a fifo underrun happens which also sets this to false.
11521 */
11522 crtc->cpu_fifo_underrun_disabled = true;
11523 crtc->pch_fifo_underrun_disabled = true;
11524 }
11525 }
11526
11527 static void intel_sanitize_encoder(struct intel_encoder *encoder)
11528 {
11529 struct intel_connector *connector;
11530 struct drm_device *dev = encoder->base.dev;
11531
11532 /* We need to check both for a crtc link (meaning that the
11533 * encoder is active and trying to read from a pipe) and the
11534 * pipe itself being active. */
11535 bool has_active_crtc = encoder->base.crtc &&
11536 to_intel_crtc(encoder->base.crtc)->active;
11537
11538 if (encoder->connectors_active && !has_active_crtc) {
11539 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
11540 encoder->base.base.id,
11541 drm_get_encoder_name(&encoder->base));
11542
11543 /* Connector is active, but has no active pipe. This is
11544 * fallout from our resume register restoring. Disable
11545 * the encoder manually again. */
11546 if (encoder->base.crtc) {
11547 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
11548 encoder->base.base.id,
11549 drm_get_encoder_name(&encoder->base));
11550 encoder->disable(encoder);
11551 }
11552
11553 /* Inconsistent output/port/pipe state happens presumably due to
11554 * a bug in one of the get_hw_state functions. Or someplace else
11555 * in our code, like the register restore mess on resume. Clamp
11556 * things to off as a safer default. */
11557 list_for_each_entry(connector,
11558 &dev->mode_config.connector_list,
11559 base.head) {
11560 if (connector->encoder != encoder)
11561 continue;
11562
11563 intel_connector_break_all_links(connector);
11564 }
11565 }
11566 /* Enabled encoders without active connectors will be fixed in
11567 * the crtc fixup. */
11568 }
11569
11570 void i915_redisable_vga_power_on(struct drm_device *dev)
11571 {
11572 struct drm_i915_private *dev_priv = dev->dev_private;
11573 u32 vga_reg = i915_vgacntrl_reg(dev);
11574
11575 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
11576 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
11577 i915_disable_vga(dev);
11578 }
11579 }
11580
11581 void i915_redisable_vga(struct drm_device *dev)
11582 {
11583 struct drm_i915_private *dev_priv = dev->dev_private;
11584
11585 /* This function can be called both from intel_modeset_setup_hw_state or
11586 * at a very early point in our resume sequence, where the power well
11587 * structures are not yet restored. Since this function is at a very
11588 * paranoid "someone might have enabled VGA while we were not looking"
11589 * level, just check if the power well is enabled instead of trying to
11590 * follow the "don't touch the power well if we don't need it" policy
11591 * the rest of the driver uses. */
11592 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
11593 return;
11594
11595 i915_redisable_vga_power_on(dev);
11596 }
11597
11598 static void intel_modeset_readout_hw_state(struct drm_device *dev)
11599 {
11600 struct drm_i915_private *dev_priv = dev->dev_private;
11601 enum pipe pipe;
11602 struct intel_crtc *crtc;
11603 struct intel_encoder *encoder;
11604 struct intel_connector *connector;
11605 int i;
11606
11607 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11608 base.head) {
11609 memset(&crtc->config, 0, sizeof(crtc->config));
11610
11611 crtc->active = dev_priv->display.get_pipe_config(crtc,
11612 &crtc->config);
11613
11614 crtc->base.enabled = crtc->active;
11615 crtc->primary_enabled = crtc->active;
11616
11617 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
11618 crtc->base.base.id,
11619 crtc->active ? "enabled" : "disabled");
11620 }
11621
11622 /* FIXME: Smash this into the new shared dpll infrastructure. */
11623 if (HAS_DDI(dev))
11624 intel_ddi_setup_hw_pll_state(dev);
11625
11626 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11627 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11628
11629 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
11630 pll->active = 0;
11631 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11632 base.head) {
11633 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11634 pll->active++;
11635 }
11636 pll->refcount = pll->active;
11637
11638 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
11639 pll->name, pll->refcount, pll->on);
11640 }
11641
11642 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11643 base.head) {
11644 pipe = 0;
11645
11646 if (encoder->get_hw_state(encoder, &pipe)) {
11647 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11648 encoder->base.crtc = &crtc->base;
11649 encoder->get_config(encoder, &crtc->config);
11650 } else {
11651 encoder->base.crtc = NULL;
11652 }
11653
11654 encoder->connectors_active = false;
11655 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
11656 encoder->base.base.id,
11657 drm_get_encoder_name(&encoder->base),
11658 encoder->base.crtc ? "enabled" : "disabled",
11659 pipe_name(pipe));
11660 }
11661
11662 list_for_each_entry(connector, &dev->mode_config.connector_list,
11663 base.head) {
11664 if (connector->get_hw_state(connector)) {
11665 connector->base.dpms = DRM_MODE_DPMS_ON;
11666 connector->encoder->connectors_active = true;
11667 connector->base.encoder = &connector->encoder->base;
11668 } else {
11669 connector->base.dpms = DRM_MODE_DPMS_OFF;
11670 connector->base.encoder = NULL;
11671 }
11672 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
11673 connector->base.base.id,
11674 drm_get_connector_name(&connector->base),
11675 connector->base.encoder ? "enabled" : "disabled");
11676 }
11677 }
11678
11679 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
11680 * and i915 state tracking structures. */
11681 void intel_modeset_setup_hw_state(struct drm_device *dev,
11682 bool force_restore)
11683 {
11684 struct drm_i915_private *dev_priv = dev->dev_private;
11685 enum pipe pipe;
11686 struct intel_crtc *crtc;
11687 struct intel_encoder *encoder;
11688 int i;
11689
11690 intel_modeset_readout_hw_state(dev);
11691
11692 /*
11693 * Now that we have the config, copy it to each CRTC struct
11694 * Note that this could go away if we move to using crtc_config
11695 * checking everywhere.
11696 */
11697 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11698 base.head) {
11699 if (crtc->active && i915.fastboot) {
11700 intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
11701 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
11702 crtc->base.base.id);
11703 drm_mode_debug_printmodeline(&crtc->base.mode);
11704 }
11705 }
11706
11707 /* HW state is read out, now we need to sanitize this mess. */
11708 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11709 base.head) {
11710 intel_sanitize_encoder(encoder);
11711 }
11712
11713 for_each_pipe(pipe) {
11714 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11715 intel_sanitize_crtc(crtc);
11716 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
11717 }
11718
11719 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11720 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11721
11722 if (!pll->on || pll->active)
11723 continue;
11724
11725 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
11726
11727 pll->disable(dev_priv, pll);
11728 pll->on = false;
11729 }
11730
11731 if (HAS_PCH_SPLIT(dev))
11732 ilk_wm_get_hw_state(dev);
11733
11734 if (force_restore) {
11735 i915_redisable_vga(dev);
11736
11737 /*
11738 * We need to use raw interfaces for restoring state to avoid
11739 * checking (bogus) intermediate states.
11740 */
11741 for_each_pipe(pipe) {
11742 struct drm_crtc *crtc =
11743 dev_priv->pipe_to_crtc_mapping[pipe];
11744
11745 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
11746 crtc->fb);
11747 }
11748 } else {
11749 intel_modeset_update_staged_output_state(dev);
11750 }
11751
11752 intel_modeset_check_state(dev);
11753 }
11754
11755 void intel_modeset_gem_init(struct drm_device *dev)
11756 {
11757 struct drm_crtc *c;
11758 struct intel_framebuffer *fb;
11759
11760 mutex_lock(&dev->struct_mutex);
11761 intel_init_gt_powersave(dev);
11762 mutex_unlock(&dev->struct_mutex);
11763
11764 intel_modeset_init_hw(dev);
11765
11766 intel_setup_overlay(dev);
11767
11768 /*
11769 * Make sure any fbs we allocated at startup are properly
11770 * pinned & fenced. When we do the allocation it's too early
11771 * for this.
11772 */
11773 mutex_lock(&dev->struct_mutex);
11774 list_for_each_entry(c, &dev->mode_config.crtc_list, head) {
11775 if (!c->fb)
11776 continue;
11777
11778 fb = to_intel_framebuffer(c->fb);
11779 if (intel_pin_and_fence_fb_obj(dev, fb->obj, NULL)) {
11780 DRM_ERROR("failed to pin boot fb on pipe %d\n",
11781 to_intel_crtc(c)->pipe);
11782 drm_framebuffer_unreference(c->fb);
11783 c->fb = NULL;
11784 }
11785 }
11786 mutex_unlock(&dev->struct_mutex);
11787 }
11788
11789 void intel_connector_unregister(struct intel_connector *intel_connector)
11790 {
11791 struct drm_connector *connector = &intel_connector->base;
11792
11793 intel_panel_destroy_backlight(connector);
11794 drm_sysfs_connector_remove(connector);
11795 }
11796
11797 void intel_modeset_cleanup(struct drm_device *dev)
11798 {
11799 struct drm_i915_private *dev_priv = dev->dev_private;
11800 struct drm_crtc *crtc;
11801 struct drm_connector *connector;
11802
11803 /*
11804 * Interrupts and polling as the first thing to avoid creating havoc.
11805 * Too much stuff here (turning of rps, connectors, ...) would
11806 * experience fancy races otherwise.
11807 */
11808 drm_irq_uninstall(dev);
11809 cancel_work_sync(&dev_priv->hotplug_work);
11810 /*
11811 * Due to the hpd irq storm handling the hotplug work can re-arm the
11812 * poll handlers. Hence disable polling after hpd handling is shut down.
11813 */
11814 drm_kms_helper_poll_fini(dev);
11815
11816 mutex_lock(&dev->struct_mutex);
11817
11818 intel_unregister_dsm_handler();
11819
11820 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
11821 /* Skip inactive CRTCs */
11822 if (!crtc->fb)
11823 continue;
11824
11825 intel_increase_pllclock(crtc);
11826 }
11827
11828 intel_disable_fbc(dev);
11829
11830 intel_disable_gt_powersave(dev);
11831
11832 ironlake_teardown_rc6(dev);
11833
11834 mutex_unlock(&dev->struct_mutex);
11835
11836 /* flush any delayed tasks or pending work */
11837 flush_scheduled_work();
11838
11839 /* destroy the backlight and sysfs files before encoders/connectors */
11840 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11841 struct intel_connector *intel_connector;
11842
11843 intel_connector = to_intel_connector(connector);
11844 intel_connector->unregister(intel_connector);
11845 }
11846
11847 drm_mode_config_cleanup(dev);
11848
11849 intel_cleanup_overlay(dev);
11850
11851 mutex_lock(&dev->struct_mutex);
11852 intel_cleanup_gt_powersave(dev);
11853 mutex_unlock(&dev->struct_mutex);
11854 }
11855
11856 /*
11857 * Return which encoder is currently attached for connector.
11858 */
11859 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
11860 {
11861 return &intel_attached_encoder(connector)->base;
11862 }
11863
11864 void intel_connector_attach_encoder(struct intel_connector *connector,
11865 struct intel_encoder *encoder)
11866 {
11867 connector->encoder = encoder;
11868 drm_mode_connector_attach_encoder(&connector->base,
11869 &encoder->base);
11870 }
11871
11872 /*
11873 * set vga decode state - true == enable VGA decode
11874 */
11875 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
11876 {
11877 struct drm_i915_private *dev_priv = dev->dev_private;
11878 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
11879 u16 gmch_ctrl;
11880
11881 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
11882 DRM_ERROR("failed to read control word\n");
11883 return -EIO;
11884 }
11885
11886 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
11887 return 0;
11888
11889 if (state)
11890 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
11891 else
11892 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
11893
11894 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
11895 DRM_ERROR("failed to write control word\n");
11896 return -EIO;
11897 }
11898
11899 return 0;
11900 }
11901
11902 struct intel_display_error_state {
11903
11904 u32 power_well_driver;
11905
11906 int num_transcoders;
11907
11908 struct intel_cursor_error_state {
11909 u32 control;
11910 u32 position;
11911 u32 base;
11912 u32 size;
11913 } cursor[I915_MAX_PIPES];
11914
11915 struct intel_pipe_error_state {
11916 bool power_domain_on;
11917 u32 source;
11918 } pipe[I915_MAX_PIPES];
11919
11920 struct intel_plane_error_state {
11921 u32 control;
11922 u32 stride;
11923 u32 size;
11924 u32 pos;
11925 u32 addr;
11926 u32 surface;
11927 u32 tile_offset;
11928 } plane[I915_MAX_PIPES];
11929
11930 struct intel_transcoder_error_state {
11931 bool power_domain_on;
11932 enum transcoder cpu_transcoder;
11933
11934 u32 conf;
11935
11936 u32 htotal;
11937 u32 hblank;
11938 u32 hsync;
11939 u32 vtotal;
11940 u32 vblank;
11941 u32 vsync;
11942 } transcoder[4];
11943 };
11944
11945 struct intel_display_error_state *
11946 intel_display_capture_error_state(struct drm_device *dev)
11947 {
11948 struct drm_i915_private *dev_priv = dev->dev_private;
11949 struct intel_display_error_state *error;
11950 int transcoders[] = {
11951 TRANSCODER_A,
11952 TRANSCODER_B,
11953 TRANSCODER_C,
11954 TRANSCODER_EDP,
11955 };
11956 int i;
11957
11958 if (INTEL_INFO(dev)->num_pipes == 0)
11959 return NULL;
11960
11961 error = kzalloc(sizeof(*error), GFP_ATOMIC);
11962 if (error == NULL)
11963 return NULL;
11964
11965 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
11966 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
11967
11968 for_each_pipe(i) {
11969 error->pipe[i].power_domain_on =
11970 intel_display_power_enabled_sw(dev_priv,
11971 POWER_DOMAIN_PIPE(i));
11972 if (!error->pipe[i].power_domain_on)
11973 continue;
11974
11975 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
11976 error->cursor[i].control = I915_READ(CURCNTR(i));
11977 error->cursor[i].position = I915_READ(CURPOS(i));
11978 error->cursor[i].base = I915_READ(CURBASE(i));
11979 } else {
11980 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
11981 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
11982 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
11983 }
11984
11985 error->plane[i].control = I915_READ(DSPCNTR(i));
11986 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
11987 if (INTEL_INFO(dev)->gen <= 3) {
11988 error->plane[i].size = I915_READ(DSPSIZE(i));
11989 error->plane[i].pos = I915_READ(DSPPOS(i));
11990 }
11991 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11992 error->plane[i].addr = I915_READ(DSPADDR(i));
11993 if (INTEL_INFO(dev)->gen >= 4) {
11994 error->plane[i].surface = I915_READ(DSPSURF(i));
11995 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
11996 }
11997
11998 error->pipe[i].source = I915_READ(PIPESRC(i));
11999 }
12000
12001 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
12002 if (HAS_DDI(dev_priv->dev))
12003 error->num_transcoders++; /* Account for eDP. */
12004
12005 for (i = 0; i < error->num_transcoders; i++) {
12006 enum transcoder cpu_transcoder = transcoders[i];
12007
12008 error->transcoder[i].power_domain_on =
12009 intel_display_power_enabled_sw(dev_priv,
12010 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
12011 if (!error->transcoder[i].power_domain_on)
12012 continue;
12013
12014 error->transcoder[i].cpu_transcoder = cpu_transcoder;
12015
12016 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
12017 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
12018 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
12019 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
12020 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
12021 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
12022 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
12023 }
12024
12025 return error;
12026 }
12027
12028 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
12029
12030 void
12031 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
12032 struct drm_device *dev,
12033 struct intel_display_error_state *error)
12034 {
12035 int i;
12036
12037 if (!error)
12038 return;
12039
12040 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
12041 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
12042 err_printf(m, "PWR_WELL_CTL2: %08x\n",
12043 error->power_well_driver);
12044 for_each_pipe(i) {
12045 err_printf(m, "Pipe [%d]:\n", i);
12046 err_printf(m, " Power: %s\n",
12047 error->pipe[i].power_domain_on ? "on" : "off");
12048 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
12049
12050 err_printf(m, "Plane [%d]:\n", i);
12051 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
12052 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
12053 if (INTEL_INFO(dev)->gen <= 3) {
12054 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
12055 err_printf(m, " POS: %08x\n", error->plane[i].pos);
12056 }
12057 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
12058 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
12059 if (INTEL_INFO(dev)->gen >= 4) {
12060 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
12061 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
12062 }
12063
12064 err_printf(m, "Cursor [%d]:\n", i);
12065 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
12066 err_printf(m, " POS: %08x\n", error->cursor[i].position);
12067 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
12068 }
12069
12070 for (i = 0; i < error->num_transcoders; i++) {
12071 err_printf(m, "CPU transcoder: %c\n",
12072 transcoder_name(error->transcoder[i].cpu_transcoder));
12073 err_printf(m, " Power: %s\n",
12074 error->transcoder[i].power_domain_on ? "on" : "off");
12075 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
12076 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
12077 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
12078 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
12079 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
12080 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
12081 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
12082 }
12083 }
Linux kernel - Deliverables
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