2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_rect.h>
44 #include <linux/dma_remapping.h>
46 /* Primary plane formats supported by all gen */
47 #define COMMON_PRIMARY_FORMATS \
50 DRM_FORMAT_XRGB8888, \
53 /* Primary plane formats for gen <= 3 */
54 static const uint32_t intel_primary_formats_gen2
[] = {
55 COMMON_PRIMARY_FORMATS
,
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t intel_primary_formats_gen4
[] = {
62 COMMON_PRIMARY_FORMATS
, \
65 DRM_FORMAT_XRGB2101010
,
66 DRM_FORMAT_ARGB2101010
,
67 DRM_FORMAT_XBGR2101010
,
68 DRM_FORMAT_ABGR2101010
,
72 static const uint32_t intel_cursor_formats
[] = {
76 #define DIV_ROUND_CLOSEST_ULL(ll, d) \
77 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
79 static void intel_increase_pllclock(struct drm_device
*dev
,
81 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
83 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
84 struct intel_crtc_config
*pipe_config
);
85 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
86 struct intel_crtc_config
*pipe_config
);
88 static int intel_set_mode(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
,
89 int x
, int y
, struct drm_framebuffer
*old_fb
);
90 static int intel_framebuffer_init(struct drm_device
*dev
,
91 struct intel_framebuffer
*ifb
,
92 struct drm_mode_fb_cmd2
*mode_cmd
,
93 struct drm_i915_gem_object
*obj
);
94 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
);
95 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
);
96 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
97 struct intel_link_m_n
*m_n
,
98 struct intel_link_m_n
*m2_n2
);
99 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
);
100 static void haswell_set_pipeconf(struct drm_crtc
*crtc
);
101 static void intel_set_pipe_csc(struct drm_crtc
*crtc
);
102 static void vlv_prepare_pll(struct intel_crtc
*crtc
);
103 static void chv_prepare_pll(struct intel_crtc
*crtc
);
105 static struct intel_encoder
*intel_find_encoder(struct intel_connector
*connector
, int pipe
)
107 if (!connector
->mst_port
)
108 return connector
->encoder
;
110 return &connector
->mst_port
->mst_encoders
[pipe
]->base
;
119 int p2_slow
, p2_fast
;
122 typedef struct intel_limit intel_limit_t
;
124 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
129 intel_pch_rawclk(struct drm_device
*dev
)
131 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
133 WARN_ON(!HAS_PCH_SPLIT(dev
));
135 return I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
;
138 static inline u32
/* units of 100MHz */
139 intel_fdi_link_freq(struct drm_device
*dev
)
142 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
143 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
148 static const intel_limit_t intel_limits_i8xx_dac
= {
149 .dot
= { .min
= 25000, .max
= 350000 },
150 .vco
= { .min
= 908000, .max
= 1512000 },
151 .n
= { .min
= 2, .max
= 16 },
152 .m
= { .min
= 96, .max
= 140 },
153 .m1
= { .min
= 18, .max
= 26 },
154 .m2
= { .min
= 6, .max
= 16 },
155 .p
= { .min
= 4, .max
= 128 },
156 .p1
= { .min
= 2, .max
= 33 },
157 .p2
= { .dot_limit
= 165000,
158 .p2_slow
= 4, .p2_fast
= 2 },
161 static const intel_limit_t intel_limits_i8xx_dvo
= {
162 .dot
= { .min
= 25000, .max
= 350000 },
163 .vco
= { .min
= 908000, .max
= 1512000 },
164 .n
= { .min
= 2, .max
= 16 },
165 .m
= { .min
= 96, .max
= 140 },
166 .m1
= { .min
= 18, .max
= 26 },
167 .m2
= { .min
= 6, .max
= 16 },
168 .p
= { .min
= 4, .max
= 128 },
169 .p1
= { .min
= 2, .max
= 33 },
170 .p2
= { .dot_limit
= 165000,
171 .p2_slow
= 4, .p2_fast
= 4 },
174 static const intel_limit_t intel_limits_i8xx_lvds
= {
175 .dot
= { .min
= 25000, .max
= 350000 },
176 .vco
= { .min
= 908000, .max
= 1512000 },
177 .n
= { .min
= 2, .max
= 16 },
178 .m
= { .min
= 96, .max
= 140 },
179 .m1
= { .min
= 18, .max
= 26 },
180 .m2
= { .min
= 6, .max
= 16 },
181 .p
= { .min
= 4, .max
= 128 },
182 .p1
= { .min
= 1, .max
= 6 },
183 .p2
= { .dot_limit
= 165000,
184 .p2_slow
= 14, .p2_fast
= 7 },
187 static const intel_limit_t intel_limits_i9xx_sdvo
= {
188 .dot
= { .min
= 20000, .max
= 400000 },
189 .vco
= { .min
= 1400000, .max
= 2800000 },
190 .n
= { .min
= 1, .max
= 6 },
191 .m
= { .min
= 70, .max
= 120 },
192 .m1
= { .min
= 8, .max
= 18 },
193 .m2
= { .min
= 3, .max
= 7 },
194 .p
= { .min
= 5, .max
= 80 },
195 .p1
= { .min
= 1, .max
= 8 },
196 .p2
= { .dot_limit
= 200000,
197 .p2_slow
= 10, .p2_fast
= 5 },
200 static const intel_limit_t intel_limits_i9xx_lvds
= {
201 .dot
= { .min
= 20000, .max
= 400000 },
202 .vco
= { .min
= 1400000, .max
= 2800000 },
203 .n
= { .min
= 1, .max
= 6 },
204 .m
= { .min
= 70, .max
= 120 },
205 .m1
= { .min
= 8, .max
= 18 },
206 .m2
= { .min
= 3, .max
= 7 },
207 .p
= { .min
= 7, .max
= 98 },
208 .p1
= { .min
= 1, .max
= 8 },
209 .p2
= { .dot_limit
= 112000,
210 .p2_slow
= 14, .p2_fast
= 7 },
214 static const intel_limit_t intel_limits_g4x_sdvo
= {
215 .dot
= { .min
= 25000, .max
= 270000 },
216 .vco
= { .min
= 1750000, .max
= 3500000},
217 .n
= { .min
= 1, .max
= 4 },
218 .m
= { .min
= 104, .max
= 138 },
219 .m1
= { .min
= 17, .max
= 23 },
220 .m2
= { .min
= 5, .max
= 11 },
221 .p
= { .min
= 10, .max
= 30 },
222 .p1
= { .min
= 1, .max
= 3},
223 .p2
= { .dot_limit
= 270000,
229 static const intel_limit_t intel_limits_g4x_hdmi
= {
230 .dot
= { .min
= 22000, .max
= 400000 },
231 .vco
= { .min
= 1750000, .max
= 3500000},
232 .n
= { .min
= 1, .max
= 4 },
233 .m
= { .min
= 104, .max
= 138 },
234 .m1
= { .min
= 16, .max
= 23 },
235 .m2
= { .min
= 5, .max
= 11 },
236 .p
= { .min
= 5, .max
= 80 },
237 .p1
= { .min
= 1, .max
= 8},
238 .p2
= { .dot_limit
= 165000,
239 .p2_slow
= 10, .p2_fast
= 5 },
242 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
243 .dot
= { .min
= 20000, .max
= 115000 },
244 .vco
= { .min
= 1750000, .max
= 3500000 },
245 .n
= { .min
= 1, .max
= 3 },
246 .m
= { .min
= 104, .max
= 138 },
247 .m1
= { .min
= 17, .max
= 23 },
248 .m2
= { .min
= 5, .max
= 11 },
249 .p
= { .min
= 28, .max
= 112 },
250 .p1
= { .min
= 2, .max
= 8 },
251 .p2
= { .dot_limit
= 0,
252 .p2_slow
= 14, .p2_fast
= 14
256 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
257 .dot
= { .min
= 80000, .max
= 224000 },
258 .vco
= { .min
= 1750000, .max
= 3500000 },
259 .n
= { .min
= 1, .max
= 3 },
260 .m
= { .min
= 104, .max
= 138 },
261 .m1
= { .min
= 17, .max
= 23 },
262 .m2
= { .min
= 5, .max
= 11 },
263 .p
= { .min
= 14, .max
= 42 },
264 .p1
= { .min
= 2, .max
= 6 },
265 .p2
= { .dot_limit
= 0,
266 .p2_slow
= 7, .p2_fast
= 7
270 static const intel_limit_t intel_limits_pineview_sdvo
= {
271 .dot
= { .min
= 20000, .max
= 400000},
272 .vco
= { .min
= 1700000, .max
= 3500000 },
273 /* Pineview's Ncounter is a ring counter */
274 .n
= { .min
= 3, .max
= 6 },
275 .m
= { .min
= 2, .max
= 256 },
276 /* Pineview only has one combined m divider, which we treat as m2. */
277 .m1
= { .min
= 0, .max
= 0 },
278 .m2
= { .min
= 0, .max
= 254 },
279 .p
= { .min
= 5, .max
= 80 },
280 .p1
= { .min
= 1, .max
= 8 },
281 .p2
= { .dot_limit
= 200000,
282 .p2_slow
= 10, .p2_fast
= 5 },
285 static const intel_limit_t intel_limits_pineview_lvds
= {
286 .dot
= { .min
= 20000, .max
= 400000 },
287 .vco
= { .min
= 1700000, .max
= 3500000 },
288 .n
= { .min
= 3, .max
= 6 },
289 .m
= { .min
= 2, .max
= 256 },
290 .m1
= { .min
= 0, .max
= 0 },
291 .m2
= { .min
= 0, .max
= 254 },
292 .p
= { .min
= 7, .max
= 112 },
293 .p1
= { .min
= 1, .max
= 8 },
294 .p2
= { .dot_limit
= 112000,
295 .p2_slow
= 14, .p2_fast
= 14 },
298 /* Ironlake / Sandybridge
300 * We calculate clock using (register_value + 2) for N/M1/M2, so here
301 * the range value for them is (actual_value - 2).
303 static const intel_limit_t intel_limits_ironlake_dac
= {
304 .dot
= { .min
= 25000, .max
= 350000 },
305 .vco
= { .min
= 1760000, .max
= 3510000 },
306 .n
= { .min
= 1, .max
= 5 },
307 .m
= { .min
= 79, .max
= 127 },
308 .m1
= { .min
= 12, .max
= 22 },
309 .m2
= { .min
= 5, .max
= 9 },
310 .p
= { .min
= 5, .max
= 80 },
311 .p1
= { .min
= 1, .max
= 8 },
312 .p2
= { .dot_limit
= 225000,
313 .p2_slow
= 10, .p2_fast
= 5 },
316 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
317 .dot
= { .min
= 25000, .max
= 350000 },
318 .vco
= { .min
= 1760000, .max
= 3510000 },
319 .n
= { .min
= 1, .max
= 3 },
320 .m
= { .min
= 79, .max
= 118 },
321 .m1
= { .min
= 12, .max
= 22 },
322 .m2
= { .min
= 5, .max
= 9 },
323 .p
= { .min
= 28, .max
= 112 },
324 .p1
= { .min
= 2, .max
= 8 },
325 .p2
= { .dot_limit
= 225000,
326 .p2_slow
= 14, .p2_fast
= 14 },
329 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
330 .dot
= { .min
= 25000, .max
= 350000 },
331 .vco
= { .min
= 1760000, .max
= 3510000 },
332 .n
= { .min
= 1, .max
= 3 },
333 .m
= { .min
= 79, .max
= 127 },
334 .m1
= { .min
= 12, .max
= 22 },
335 .m2
= { .min
= 5, .max
= 9 },
336 .p
= { .min
= 14, .max
= 56 },
337 .p1
= { .min
= 2, .max
= 8 },
338 .p2
= { .dot_limit
= 225000,
339 .p2_slow
= 7, .p2_fast
= 7 },
342 /* LVDS 100mhz refclk limits. */
343 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
344 .dot
= { .min
= 25000, .max
= 350000 },
345 .vco
= { .min
= 1760000, .max
= 3510000 },
346 .n
= { .min
= 1, .max
= 2 },
347 .m
= { .min
= 79, .max
= 126 },
348 .m1
= { .min
= 12, .max
= 22 },
349 .m2
= { .min
= 5, .max
= 9 },
350 .p
= { .min
= 28, .max
= 112 },
351 .p1
= { .min
= 2, .max
= 8 },
352 .p2
= { .dot_limit
= 225000,
353 .p2_slow
= 14, .p2_fast
= 14 },
356 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
357 .dot
= { .min
= 25000, .max
= 350000 },
358 .vco
= { .min
= 1760000, .max
= 3510000 },
359 .n
= { .min
= 1, .max
= 3 },
360 .m
= { .min
= 79, .max
= 126 },
361 .m1
= { .min
= 12, .max
= 22 },
362 .m2
= { .min
= 5, .max
= 9 },
363 .p
= { .min
= 14, .max
= 42 },
364 .p1
= { .min
= 2, .max
= 6 },
365 .p2
= { .dot_limit
= 225000,
366 .p2_slow
= 7, .p2_fast
= 7 },
369 static const intel_limit_t intel_limits_vlv
= {
371 * These are the data rate limits (measured in fast clocks)
372 * since those are the strictest limits we have. The fast
373 * clock and actual rate limits are more relaxed, so checking
374 * them would make no difference.
376 .dot
= { .min
= 25000 * 5, .max
= 270000 * 5 },
377 .vco
= { .min
= 4000000, .max
= 6000000 },
378 .n
= { .min
= 1, .max
= 7 },
379 .m1
= { .min
= 2, .max
= 3 },
380 .m2
= { .min
= 11, .max
= 156 },
381 .p1
= { .min
= 2, .max
= 3 },
382 .p2
= { .p2_slow
= 2, .p2_fast
= 20 }, /* slow=min, fast=max */
385 static const intel_limit_t intel_limits_chv
= {
387 * These are the data rate limits (measured in fast clocks)
388 * since those are the strictest limits we have. The fast
389 * clock and actual rate limits are more relaxed, so checking
390 * them would make no difference.
392 .dot
= { .min
= 25000 * 5, .max
= 540000 * 5},
393 .vco
= { .min
= 4860000, .max
= 6700000 },
394 .n
= { .min
= 1, .max
= 1 },
395 .m1
= { .min
= 2, .max
= 2 },
396 .m2
= { .min
= 24 << 22, .max
= 175 << 22 },
397 .p1
= { .min
= 2, .max
= 4 },
398 .p2
= { .p2_slow
= 1, .p2_fast
= 14 },
401 static void vlv_clock(int refclk
, intel_clock_t
*clock
)
403 clock
->m
= clock
->m1
* clock
->m2
;
404 clock
->p
= clock
->p1
* clock
->p2
;
405 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
407 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
408 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
412 * Returns whether any output on the specified pipe is of the specified type
414 static bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
)
416 struct drm_device
*dev
= crtc
->dev
;
417 struct intel_encoder
*encoder
;
419 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
420 if (encoder
->type
== type
)
426 static const intel_limit_t
*intel_ironlake_limit(struct drm_crtc
*crtc
,
429 struct drm_device
*dev
= crtc
->dev
;
430 const intel_limit_t
*limit
;
432 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
433 if (intel_is_dual_link_lvds(dev
)) {
434 if (refclk
== 100000)
435 limit
= &intel_limits_ironlake_dual_lvds_100m
;
437 limit
= &intel_limits_ironlake_dual_lvds
;
439 if (refclk
== 100000)
440 limit
= &intel_limits_ironlake_single_lvds_100m
;
442 limit
= &intel_limits_ironlake_single_lvds
;
445 limit
= &intel_limits_ironlake_dac
;
450 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
452 struct drm_device
*dev
= crtc
->dev
;
453 const intel_limit_t
*limit
;
455 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
456 if (intel_is_dual_link_lvds(dev
))
457 limit
= &intel_limits_g4x_dual_channel_lvds
;
459 limit
= &intel_limits_g4x_single_channel_lvds
;
460 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
461 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
462 limit
= &intel_limits_g4x_hdmi
;
463 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
464 limit
= &intel_limits_g4x_sdvo
;
465 } else /* The option is for other outputs */
466 limit
= &intel_limits_i9xx_sdvo
;
471 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
, int refclk
)
473 struct drm_device
*dev
= crtc
->dev
;
474 const intel_limit_t
*limit
;
476 if (HAS_PCH_SPLIT(dev
))
477 limit
= intel_ironlake_limit(crtc
, refclk
);
478 else if (IS_G4X(dev
)) {
479 limit
= intel_g4x_limit(crtc
);
480 } else if (IS_PINEVIEW(dev
)) {
481 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
482 limit
= &intel_limits_pineview_lvds
;
484 limit
= &intel_limits_pineview_sdvo
;
485 } else if (IS_CHERRYVIEW(dev
)) {
486 limit
= &intel_limits_chv
;
487 } else if (IS_VALLEYVIEW(dev
)) {
488 limit
= &intel_limits_vlv
;
489 } else if (!IS_GEN2(dev
)) {
490 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
491 limit
= &intel_limits_i9xx_lvds
;
493 limit
= &intel_limits_i9xx_sdvo
;
495 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
496 limit
= &intel_limits_i8xx_lvds
;
497 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
))
498 limit
= &intel_limits_i8xx_dvo
;
500 limit
= &intel_limits_i8xx_dac
;
505 /* m1 is reserved as 0 in Pineview, n is a ring counter */
506 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
508 clock
->m
= clock
->m2
+ 2;
509 clock
->p
= clock
->p1
* clock
->p2
;
510 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
512 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
513 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
516 static uint32_t i9xx_dpll_compute_m(struct dpll
*dpll
)
518 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
521 static void i9xx_clock(int refclk
, intel_clock_t
*clock
)
523 clock
->m
= i9xx_dpll_compute_m(clock
);
524 clock
->p
= clock
->p1
* clock
->p2
;
525 if (WARN_ON(clock
->n
+ 2 == 0 || clock
->p
== 0))
527 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
+ 2);
528 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
531 static void chv_clock(int refclk
, intel_clock_t
*clock
)
533 clock
->m
= clock
->m1
* clock
->m2
;
534 clock
->p
= clock
->p1
* clock
->p2
;
535 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
537 clock
->vco
= DIV_ROUND_CLOSEST_ULL((uint64_t)refclk
* clock
->m
,
539 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
542 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
544 * Returns whether the given set of divisors are valid for a given refclk with
545 * the given connectors.
548 static bool intel_PLL_is_valid(struct drm_device
*dev
,
549 const intel_limit_t
*limit
,
550 const intel_clock_t
*clock
)
552 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
553 INTELPllInvalid("n out of range\n");
554 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
555 INTELPllInvalid("p1 out of range\n");
556 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
557 INTELPllInvalid("m2 out of range\n");
558 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
559 INTELPllInvalid("m1 out of range\n");
561 if (!IS_PINEVIEW(dev
) && !IS_VALLEYVIEW(dev
))
562 if (clock
->m1
<= clock
->m2
)
563 INTELPllInvalid("m1 <= m2\n");
565 if (!IS_VALLEYVIEW(dev
)) {
566 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
567 INTELPllInvalid("p out of range\n");
568 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
569 INTELPllInvalid("m out of range\n");
572 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
573 INTELPllInvalid("vco out of range\n");
574 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
575 * connector, etc., rather than just a single range.
577 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
578 INTELPllInvalid("dot out of range\n");
584 i9xx_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
585 int target
, int refclk
, intel_clock_t
*match_clock
,
586 intel_clock_t
*best_clock
)
588 struct drm_device
*dev
= crtc
->dev
;
592 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
594 * For LVDS just rely on its current settings for dual-channel.
595 * We haven't figured out how to reliably set up different
596 * single/dual channel state, if we even can.
598 if (intel_is_dual_link_lvds(dev
))
599 clock
.p2
= limit
->p2
.p2_fast
;
601 clock
.p2
= limit
->p2
.p2_slow
;
603 if (target
< limit
->p2
.dot_limit
)
604 clock
.p2
= limit
->p2
.p2_slow
;
606 clock
.p2
= limit
->p2
.p2_fast
;
609 memset(best_clock
, 0, sizeof(*best_clock
));
611 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
613 for (clock
.m2
= limit
->m2
.min
;
614 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
615 if (clock
.m2
>= clock
.m1
)
617 for (clock
.n
= limit
->n
.min
;
618 clock
.n
<= limit
->n
.max
; clock
.n
++) {
619 for (clock
.p1
= limit
->p1
.min
;
620 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
623 i9xx_clock(refclk
, &clock
);
624 if (!intel_PLL_is_valid(dev
, limit
,
628 clock
.p
!= match_clock
->p
)
631 this_err
= abs(clock
.dot
- target
);
632 if (this_err
< err
) {
641 return (err
!= target
);
645 pnv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
646 int target
, int refclk
, intel_clock_t
*match_clock
,
647 intel_clock_t
*best_clock
)
649 struct drm_device
*dev
= crtc
->dev
;
653 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
655 * For LVDS just rely on its current settings for dual-channel.
656 * We haven't figured out how to reliably set up different
657 * single/dual channel state, if we even can.
659 if (intel_is_dual_link_lvds(dev
))
660 clock
.p2
= limit
->p2
.p2_fast
;
662 clock
.p2
= limit
->p2
.p2_slow
;
664 if (target
< limit
->p2
.dot_limit
)
665 clock
.p2
= limit
->p2
.p2_slow
;
667 clock
.p2
= limit
->p2
.p2_fast
;
670 memset(best_clock
, 0, sizeof(*best_clock
));
672 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
674 for (clock
.m2
= limit
->m2
.min
;
675 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
676 for (clock
.n
= limit
->n
.min
;
677 clock
.n
<= limit
->n
.max
; clock
.n
++) {
678 for (clock
.p1
= limit
->p1
.min
;
679 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
682 pineview_clock(refclk
, &clock
);
683 if (!intel_PLL_is_valid(dev
, limit
,
687 clock
.p
!= match_clock
->p
)
690 this_err
= abs(clock
.dot
- target
);
691 if (this_err
< err
) {
700 return (err
!= target
);
704 g4x_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
705 int target
, int refclk
, intel_clock_t
*match_clock
,
706 intel_clock_t
*best_clock
)
708 struct drm_device
*dev
= crtc
->dev
;
712 /* approximately equals target * 0.00585 */
713 int err_most
= (target
>> 8) + (target
>> 9);
716 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
717 if (intel_is_dual_link_lvds(dev
))
718 clock
.p2
= limit
->p2
.p2_fast
;
720 clock
.p2
= limit
->p2
.p2_slow
;
722 if (target
< limit
->p2
.dot_limit
)
723 clock
.p2
= limit
->p2
.p2_slow
;
725 clock
.p2
= limit
->p2
.p2_fast
;
728 memset(best_clock
, 0, sizeof(*best_clock
));
729 max_n
= limit
->n
.max
;
730 /* based on hardware requirement, prefer smaller n to precision */
731 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
732 /* based on hardware requirement, prefere larger m1,m2 */
733 for (clock
.m1
= limit
->m1
.max
;
734 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
735 for (clock
.m2
= limit
->m2
.max
;
736 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
737 for (clock
.p1
= limit
->p1
.max
;
738 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
741 i9xx_clock(refclk
, &clock
);
742 if (!intel_PLL_is_valid(dev
, limit
,
746 this_err
= abs(clock
.dot
- target
);
747 if (this_err
< err_most
) {
761 vlv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
762 int target
, int refclk
, intel_clock_t
*match_clock
,
763 intel_clock_t
*best_clock
)
765 struct drm_device
*dev
= crtc
->dev
;
767 unsigned int bestppm
= 1000000;
768 /* min update 19.2 MHz */
769 int max_n
= min(limit
->n
.max
, refclk
/ 19200);
772 target
*= 5; /* fast clock */
774 memset(best_clock
, 0, sizeof(*best_clock
));
776 /* based on hardware requirement, prefer smaller n to precision */
777 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
778 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
779 for (clock
.p2
= limit
->p2
.p2_fast
; clock
.p2
>= limit
->p2
.p2_slow
;
780 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
781 clock
.p
= clock
.p1
* clock
.p2
;
782 /* based on hardware requirement, prefer bigger m1,m2 values */
783 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
; clock
.m1
++) {
784 unsigned int ppm
, diff
;
786 clock
.m2
= DIV_ROUND_CLOSEST(target
* clock
.p
* clock
.n
,
789 vlv_clock(refclk
, &clock
);
791 if (!intel_PLL_is_valid(dev
, limit
,
795 diff
= abs(clock
.dot
- target
);
796 ppm
= div_u64(1000000ULL * diff
, target
);
798 if (ppm
< 100 && clock
.p
> best_clock
->p
) {
804 if (bestppm
>= 10 && ppm
< bestppm
- 10) {
818 chv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
819 int target
, int refclk
, intel_clock_t
*match_clock
,
820 intel_clock_t
*best_clock
)
822 struct drm_device
*dev
= crtc
->dev
;
827 memset(best_clock
, 0, sizeof(*best_clock
));
830 * Based on hardware doc, the n always set to 1, and m1 always
831 * set to 2. If requires to support 200Mhz refclk, we need to
832 * revisit this because n may not 1 anymore.
834 clock
.n
= 1, clock
.m1
= 2;
835 target
*= 5; /* fast clock */
837 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
838 for (clock
.p2
= limit
->p2
.p2_fast
;
839 clock
.p2
>= limit
->p2
.p2_slow
;
840 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
842 clock
.p
= clock
.p1
* clock
.p2
;
844 m2
= DIV_ROUND_CLOSEST_ULL(((uint64_t)target
* clock
.p
*
845 clock
.n
) << 22, refclk
* clock
.m1
);
847 if (m2
> INT_MAX
/clock
.m1
)
852 chv_clock(refclk
, &clock
);
854 if (!intel_PLL_is_valid(dev
, limit
, &clock
))
857 /* based on hardware requirement, prefer bigger p
859 if (clock
.p
> best_clock
->p
) {
869 bool intel_crtc_active(struct drm_crtc
*crtc
)
871 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
873 /* Be paranoid as we can arrive here with only partial
874 * state retrieved from the hardware during setup.
876 * We can ditch the adjusted_mode.crtc_clock check as soon
877 * as Haswell has gained clock readout/fastboot support.
879 * We can ditch the crtc->primary->fb check as soon as we can
880 * properly reconstruct framebuffers.
882 return intel_crtc
->active
&& crtc
->primary
->fb
&&
883 intel_crtc
->config
.adjusted_mode
.crtc_clock
;
886 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
889 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
890 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
892 return intel_crtc
->config
.cpu_transcoder
;
895 static bool pipe_dsl_stopped(struct drm_device
*dev
, enum pipe pipe
)
897 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
898 u32 reg
= PIPEDSL(pipe
);
903 line_mask
= DSL_LINEMASK_GEN2
;
905 line_mask
= DSL_LINEMASK_GEN3
;
907 line1
= I915_READ(reg
) & line_mask
;
909 line2
= I915_READ(reg
) & line_mask
;
911 return line1
== line2
;
915 * intel_wait_for_pipe_off - wait for pipe to turn off
916 * @crtc: crtc whose pipe to wait for
918 * After disabling a pipe, we can't wait for vblank in the usual way,
919 * spinning on the vblank interrupt status bit, since we won't actually
920 * see an interrupt when the pipe is disabled.
923 * wait for the pipe register state bit to turn off
926 * wait for the display line value to settle (it usually
927 * ends up stopping at the start of the next frame).
930 static void intel_wait_for_pipe_off(struct intel_crtc
*crtc
)
932 struct drm_device
*dev
= crtc
->base
.dev
;
933 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
934 enum transcoder cpu_transcoder
= crtc
->config
.cpu_transcoder
;
935 enum pipe pipe
= crtc
->pipe
;
937 if (INTEL_INFO(dev
)->gen
>= 4) {
938 int reg
= PIPECONF(cpu_transcoder
);
940 /* Wait for the Pipe State to go off */
941 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
943 WARN(1, "pipe_off wait timed out\n");
945 /* Wait for the display line to settle */
946 if (wait_for(pipe_dsl_stopped(dev
, pipe
), 100))
947 WARN(1, "pipe_off wait timed out\n");
952 * ibx_digital_port_connected - is the specified port connected?
953 * @dev_priv: i915 private structure
954 * @port: the port to test
956 * Returns true if @port is connected, false otherwise.
958 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
959 struct intel_digital_port
*port
)
963 if (HAS_PCH_IBX(dev_priv
->dev
)) {
964 switch (port
->port
) {
966 bit
= SDE_PORTB_HOTPLUG
;
969 bit
= SDE_PORTC_HOTPLUG
;
972 bit
= SDE_PORTD_HOTPLUG
;
978 switch (port
->port
) {
980 bit
= SDE_PORTB_HOTPLUG_CPT
;
983 bit
= SDE_PORTC_HOTPLUG_CPT
;
986 bit
= SDE_PORTD_HOTPLUG_CPT
;
993 return I915_READ(SDEISR
) & bit
;
996 static const char *state_string(bool enabled
)
998 return enabled
? "on" : "off";
1001 /* Only for pre-ILK configs */
1002 void assert_pll(struct drm_i915_private
*dev_priv
,
1003 enum pipe pipe
, bool state
)
1010 val
= I915_READ(reg
);
1011 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1012 WARN(cur_state
!= state
,
1013 "PLL state assertion failure (expected %s, current %s)\n",
1014 state_string(state
), state_string(cur_state
));
1017 /* XXX: the dsi pll is shared between MIPI DSI ports */
1018 static void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
)
1023 mutex_lock(&dev_priv
->dpio_lock
);
1024 val
= vlv_cck_read(dev_priv
, CCK_REG_DSI_PLL_CONTROL
);
1025 mutex_unlock(&dev_priv
->dpio_lock
);
1027 cur_state
= val
& DSI_PLL_VCO_EN
;
1028 WARN(cur_state
!= state
,
1029 "DSI PLL state assertion failure (expected %s, current %s)\n",
1030 state_string(state
), state_string(cur_state
));
1032 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1033 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1035 struct intel_shared_dpll
*
1036 intel_crtc_to_shared_dpll(struct intel_crtc
*crtc
)
1038 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1040 if (crtc
->config
.shared_dpll
< 0)
1043 return &dev_priv
->shared_dplls
[crtc
->config
.shared_dpll
];
1047 void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
1048 struct intel_shared_dpll
*pll
,
1052 struct intel_dpll_hw_state hw_state
;
1055 "asserting DPLL %s with no DPLL\n", state_string(state
)))
1058 cur_state
= pll
->get_hw_state(dev_priv
, pll
, &hw_state
);
1059 WARN(cur_state
!= state
,
1060 "%s assertion failure (expected %s, current %s)\n",
1061 pll
->name
, state_string(state
), state_string(cur_state
));
1064 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1065 enum pipe pipe
, bool state
)
1070 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1073 if (HAS_DDI(dev_priv
->dev
)) {
1074 /* DDI does not have a specific FDI_TX register */
1075 reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1076 val
= I915_READ(reg
);
1077 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
1079 reg
= FDI_TX_CTL(pipe
);
1080 val
= I915_READ(reg
);
1081 cur_state
= !!(val
& FDI_TX_ENABLE
);
1083 WARN(cur_state
!= state
,
1084 "FDI TX state assertion failure (expected %s, current %s)\n",
1085 state_string(state
), state_string(cur_state
));
1087 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1088 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1090 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1091 enum pipe pipe
, bool state
)
1097 reg
= FDI_RX_CTL(pipe
);
1098 val
= I915_READ(reg
);
1099 cur_state
= !!(val
& FDI_RX_ENABLE
);
1100 WARN(cur_state
!= state
,
1101 "FDI RX state assertion failure (expected %s, current %s)\n",
1102 state_string(state
), state_string(cur_state
));
1104 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1105 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1107 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1113 /* ILK FDI PLL is always enabled */
1114 if (INTEL_INFO(dev_priv
->dev
)->gen
== 5)
1117 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1118 if (HAS_DDI(dev_priv
->dev
))
1121 reg
= FDI_TX_CTL(pipe
);
1122 val
= I915_READ(reg
);
1123 WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1126 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1127 enum pipe pipe
, bool state
)
1133 reg
= FDI_RX_CTL(pipe
);
1134 val
= I915_READ(reg
);
1135 cur_state
= !!(val
& FDI_RX_PLL_ENABLE
);
1136 WARN(cur_state
!= state
,
1137 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1138 state_string(state
), state_string(cur_state
));
1141 static void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1144 struct drm_device
*dev
= dev_priv
->dev
;
1147 enum pipe panel_pipe
= PIPE_A
;
1150 if (WARN_ON(HAS_DDI(dev
)))
1153 if (HAS_PCH_SPLIT(dev
)) {
1156 pp_reg
= PCH_PP_CONTROL
;
1157 port_sel
= I915_READ(PCH_PP_ON_DELAYS
) & PANEL_PORT_SELECT_MASK
;
1159 if (port_sel
== PANEL_PORT_SELECT_LVDS
&&
1160 I915_READ(PCH_LVDS
) & LVDS_PIPEB_SELECT
)
1161 panel_pipe
= PIPE_B
;
1162 /* XXX: else fix for eDP */
1163 } else if (IS_VALLEYVIEW(dev
)) {
1164 /* presumably write lock depends on pipe, not port select */
1165 pp_reg
= VLV_PIPE_PP_CONTROL(pipe
);
1168 pp_reg
= PP_CONTROL
;
1169 if (I915_READ(LVDS
) & LVDS_PIPEB_SELECT
)
1170 panel_pipe
= PIPE_B
;
1173 val
= I915_READ(pp_reg
);
1174 if (!(val
& PANEL_POWER_ON
) ||
1175 ((val
& PANEL_UNLOCK_MASK
) == PANEL_UNLOCK_REGS
))
1178 WARN(panel_pipe
== pipe
&& locked
,
1179 "panel assertion failure, pipe %c regs locked\n",
1183 static void assert_cursor(struct drm_i915_private
*dev_priv
,
1184 enum pipe pipe
, bool state
)
1186 struct drm_device
*dev
= dev_priv
->dev
;
1189 if (IS_845G(dev
) || IS_I865G(dev
))
1190 cur_state
= I915_READ(_CURACNTR
) & CURSOR_ENABLE
;
1192 cur_state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
1194 WARN(cur_state
!= state
,
1195 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1196 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1198 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1199 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1201 void assert_pipe(struct drm_i915_private
*dev_priv
,
1202 enum pipe pipe
, bool state
)
1207 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1210 /* if we need the pipe quirk it must be always on */
1211 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1212 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1215 if (!intel_display_power_enabled(dev_priv
,
1216 POWER_DOMAIN_TRANSCODER(cpu_transcoder
))) {
1219 reg
= PIPECONF(cpu_transcoder
);
1220 val
= I915_READ(reg
);
1221 cur_state
= !!(val
& PIPECONF_ENABLE
);
1224 WARN(cur_state
!= state
,
1225 "pipe %c assertion failure (expected %s, current %s)\n",
1226 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1229 static void assert_plane(struct drm_i915_private
*dev_priv
,
1230 enum plane plane
, bool state
)
1236 reg
= DSPCNTR(plane
);
1237 val
= I915_READ(reg
);
1238 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1239 WARN(cur_state
!= state
,
1240 "plane %c assertion failure (expected %s, current %s)\n",
1241 plane_name(plane
), state_string(state
), state_string(cur_state
));
1244 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1245 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1247 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1250 struct drm_device
*dev
= dev_priv
->dev
;
1255 /* Primary planes are fixed to pipes on gen4+ */
1256 if (INTEL_INFO(dev
)->gen
>= 4) {
1257 reg
= DSPCNTR(pipe
);
1258 val
= I915_READ(reg
);
1259 WARN(val
& DISPLAY_PLANE_ENABLE
,
1260 "plane %c assertion failure, should be disabled but not\n",
1265 /* Need to check both planes against the pipe */
1266 for_each_pipe(dev_priv
, i
) {
1268 val
= I915_READ(reg
);
1269 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1270 DISPPLANE_SEL_PIPE_SHIFT
;
1271 WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1272 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1273 plane_name(i
), pipe_name(pipe
));
1277 static void assert_sprites_disabled(struct drm_i915_private
*dev_priv
,
1280 struct drm_device
*dev
= dev_priv
->dev
;
1284 if (IS_VALLEYVIEW(dev
)) {
1285 for_each_sprite(pipe
, sprite
) {
1286 reg
= SPCNTR(pipe
, sprite
);
1287 val
= I915_READ(reg
);
1288 WARN(val
& SP_ENABLE
,
1289 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1290 sprite_name(pipe
, sprite
), pipe_name(pipe
));
1292 } else if (INTEL_INFO(dev
)->gen
>= 7) {
1294 val
= I915_READ(reg
);
1295 WARN(val
& SPRITE_ENABLE
,
1296 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1297 plane_name(pipe
), pipe_name(pipe
));
1298 } else if (INTEL_INFO(dev
)->gen
>= 5) {
1299 reg
= DVSCNTR(pipe
);
1300 val
= I915_READ(reg
);
1301 WARN(val
& DVS_ENABLE
,
1302 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1303 plane_name(pipe
), pipe_name(pipe
));
1307 static void assert_vblank_disabled(struct drm_crtc
*crtc
)
1309 if (WARN_ON(drm_crtc_vblank_get(crtc
) == 0))
1310 drm_crtc_vblank_put(crtc
);
1313 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1318 WARN_ON(!(HAS_PCH_IBX(dev_priv
->dev
) || HAS_PCH_CPT(dev_priv
->dev
)));
1320 val
= I915_READ(PCH_DREF_CONTROL
);
1321 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1322 DREF_SUPERSPREAD_SOURCE_MASK
));
1323 WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1326 static void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1333 reg
= PCH_TRANSCONF(pipe
);
1334 val
= I915_READ(reg
);
1335 enabled
= !!(val
& TRANS_ENABLE
);
1337 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1341 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1342 enum pipe pipe
, u32 port_sel
, u32 val
)
1344 if ((val
& DP_PORT_EN
) == 0)
1347 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1348 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1349 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1350 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1352 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1353 if ((val
& DP_PIPE_MASK_CHV
) != DP_PIPE_SELECT_CHV(pipe
))
1356 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1362 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1363 enum pipe pipe
, u32 val
)
1365 if ((val
& SDVO_ENABLE
) == 0)
1368 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1369 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1371 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1372 if ((val
& SDVO_PIPE_SEL_MASK_CHV
) != SDVO_PIPE_SEL_CHV(pipe
))
1375 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1381 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1382 enum pipe pipe
, u32 val
)
1384 if ((val
& LVDS_PORT_EN
) == 0)
1387 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1388 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1391 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1397 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1398 enum pipe pipe
, u32 val
)
1400 if ((val
& ADPA_DAC_ENABLE
) == 0)
1402 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1403 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1406 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1412 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1413 enum pipe pipe
, int reg
, u32 port_sel
)
1415 u32 val
= I915_READ(reg
);
1416 WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1417 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1418 reg
, pipe_name(pipe
));
1420 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& DP_PORT_EN
) == 0
1421 && (val
& DP_PIPEB_SELECT
),
1422 "IBX PCH dp port still using transcoder B\n");
1425 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1426 enum pipe pipe
, int reg
)
1428 u32 val
= I915_READ(reg
);
1429 WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1430 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1431 reg
, pipe_name(pipe
));
1433 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& SDVO_ENABLE
) == 0
1434 && (val
& SDVO_PIPE_B_SELECT
),
1435 "IBX PCH hdmi port still using transcoder B\n");
1438 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1444 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1445 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1446 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1449 val
= I915_READ(reg
);
1450 WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1451 "PCH VGA enabled on transcoder %c, should be disabled\n",
1455 val
= I915_READ(reg
);
1456 WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1457 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1460 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1461 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1462 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1465 static void intel_init_dpio(struct drm_device
*dev
)
1467 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1469 if (!IS_VALLEYVIEW(dev
))
1473 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1474 * CHV x1 PHY (DP/HDMI D)
1475 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1477 if (IS_CHERRYVIEW(dev
)) {
1478 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO_2
;
1479 DPIO_PHY_IOSF_PORT(DPIO_PHY1
) = IOSF_PORT_DPIO
;
1481 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO
;
1485 static void vlv_enable_pll(struct intel_crtc
*crtc
)
1487 struct drm_device
*dev
= crtc
->base
.dev
;
1488 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1489 int reg
= DPLL(crtc
->pipe
);
1490 u32 dpll
= crtc
->config
.dpll_hw_state
.dpll
;
1492 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1494 /* No really, not for ILK+ */
1495 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
));
1497 /* PLL is protected by panel, make sure we can write it */
1498 if (IS_MOBILE(dev_priv
->dev
))
1499 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1501 I915_WRITE(reg
, dpll
);
1505 if (wait_for(((I915_READ(reg
) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1506 DRM_ERROR("DPLL %d failed to lock\n", crtc
->pipe
);
1508 I915_WRITE(DPLL_MD(crtc
->pipe
), crtc
->config
.dpll_hw_state
.dpll_md
);
1509 POSTING_READ(DPLL_MD(crtc
->pipe
));
1511 /* We do this three times for luck */
1512 I915_WRITE(reg
, dpll
);
1514 udelay(150); /* wait for warmup */
1515 I915_WRITE(reg
, dpll
);
1517 udelay(150); /* wait for warmup */
1518 I915_WRITE(reg
, dpll
);
1520 udelay(150); /* wait for warmup */
1523 static void chv_enable_pll(struct intel_crtc
*crtc
)
1525 struct drm_device
*dev
= crtc
->base
.dev
;
1526 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1527 int pipe
= crtc
->pipe
;
1528 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1531 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1533 BUG_ON(!IS_CHERRYVIEW(dev_priv
->dev
));
1535 mutex_lock(&dev_priv
->dpio_lock
);
1537 /* Enable back the 10bit clock to display controller */
1538 tmp
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1539 tmp
|= DPIO_DCLKP_EN
;
1540 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), tmp
);
1543 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1548 I915_WRITE(DPLL(pipe
), crtc
->config
.dpll_hw_state
.dpll
);
1550 /* Check PLL is locked */
1551 if (wait_for(((I915_READ(DPLL(pipe
)) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1552 DRM_ERROR("PLL %d failed to lock\n", pipe
);
1554 /* not sure when this should be written */
1555 I915_WRITE(DPLL_MD(pipe
), crtc
->config
.dpll_hw_state
.dpll_md
);
1556 POSTING_READ(DPLL_MD(pipe
));
1558 mutex_unlock(&dev_priv
->dpio_lock
);
1561 static int intel_num_dvo_pipes(struct drm_device
*dev
)
1563 struct intel_crtc
*crtc
;
1566 for_each_intel_crtc(dev
, crtc
)
1567 count
+= crtc
->active
&&
1568 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DVO
);
1573 static void i9xx_enable_pll(struct intel_crtc
*crtc
)
1575 struct drm_device
*dev
= crtc
->base
.dev
;
1576 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1577 int reg
= DPLL(crtc
->pipe
);
1578 u32 dpll
= crtc
->config
.dpll_hw_state
.dpll
;
1580 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1582 /* No really, not for ILK+ */
1583 BUG_ON(INTEL_INFO(dev
)->gen
>= 5);
1585 /* PLL is protected by panel, make sure we can write it */
1586 if (IS_MOBILE(dev
) && !IS_I830(dev
))
1587 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1589 /* Enable DVO 2x clock on both PLLs if necessary */
1590 if (IS_I830(dev
) && intel_num_dvo_pipes(dev
) > 0) {
1592 * It appears to be important that we don't enable this
1593 * for the current pipe before otherwise configuring the
1594 * PLL. No idea how this should be handled if multiple
1595 * DVO outputs are enabled simultaneosly.
1597 dpll
|= DPLL_DVO_2X_MODE
;
1598 I915_WRITE(DPLL(!crtc
->pipe
),
1599 I915_READ(DPLL(!crtc
->pipe
)) | DPLL_DVO_2X_MODE
);
1602 /* Wait for the clocks to stabilize. */
1606 if (INTEL_INFO(dev
)->gen
>= 4) {
1607 I915_WRITE(DPLL_MD(crtc
->pipe
),
1608 crtc
->config
.dpll_hw_state
.dpll_md
);
1610 /* The pixel multiplier can only be updated once the
1611 * DPLL is enabled and the clocks are stable.
1613 * So write it again.
1615 I915_WRITE(reg
, dpll
);
1618 /* We do this three times for luck */
1619 I915_WRITE(reg
, dpll
);
1621 udelay(150); /* wait for warmup */
1622 I915_WRITE(reg
, dpll
);
1624 udelay(150); /* wait for warmup */
1625 I915_WRITE(reg
, dpll
);
1627 udelay(150); /* wait for warmup */
1631 * i9xx_disable_pll - disable a PLL
1632 * @dev_priv: i915 private structure
1633 * @pipe: pipe PLL to disable
1635 * Disable the PLL for @pipe, making sure the pipe is off first.
1637 * Note! This is for pre-ILK only.
1639 static void i9xx_disable_pll(struct intel_crtc
*crtc
)
1641 struct drm_device
*dev
= crtc
->base
.dev
;
1642 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1643 enum pipe pipe
= crtc
->pipe
;
1645 /* Disable DVO 2x clock on both PLLs if necessary */
1647 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DVO
) &&
1648 intel_num_dvo_pipes(dev
) == 1) {
1649 I915_WRITE(DPLL(PIPE_B
),
1650 I915_READ(DPLL(PIPE_B
)) & ~DPLL_DVO_2X_MODE
);
1651 I915_WRITE(DPLL(PIPE_A
),
1652 I915_READ(DPLL(PIPE_A
)) & ~DPLL_DVO_2X_MODE
);
1655 /* Don't disable pipe or pipe PLLs if needed */
1656 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1657 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1660 /* Make sure the pipe isn't still relying on us */
1661 assert_pipe_disabled(dev_priv
, pipe
);
1663 I915_WRITE(DPLL(pipe
), 0);
1664 POSTING_READ(DPLL(pipe
));
1667 static void vlv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1671 /* Make sure the pipe isn't still relying on us */
1672 assert_pipe_disabled(dev_priv
, pipe
);
1675 * Leave integrated clock source and reference clock enabled for pipe B.
1676 * The latter is needed for VGA hotplug / manual detection.
1679 val
= DPLL_INTEGRATED_CRI_CLK_VLV
| DPLL_REFA_CLK_ENABLE_VLV
;
1680 I915_WRITE(DPLL(pipe
), val
);
1681 POSTING_READ(DPLL(pipe
));
1685 static void chv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1687 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1690 /* Make sure the pipe isn't still relying on us */
1691 assert_pipe_disabled(dev_priv
, pipe
);
1693 /* Set PLL en = 0 */
1694 val
= DPLL_SSC_REF_CLOCK_CHV
| DPLL_REFA_CLK_ENABLE_VLV
;
1696 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
1697 I915_WRITE(DPLL(pipe
), val
);
1698 POSTING_READ(DPLL(pipe
));
1700 mutex_lock(&dev_priv
->dpio_lock
);
1702 /* Disable 10bit clock to display controller */
1703 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1704 val
&= ~DPIO_DCLKP_EN
;
1705 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), val
);
1707 /* disable left/right clock distribution */
1708 if (pipe
!= PIPE_B
) {
1709 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
);
1710 val
&= ~(CHV_BUFLEFTENA1_MASK
| CHV_BUFRIGHTENA1_MASK
);
1711 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
, val
);
1713 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
);
1714 val
&= ~(CHV_BUFLEFTENA2_MASK
| CHV_BUFRIGHTENA2_MASK
);
1715 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
, val
);
1718 mutex_unlock(&dev_priv
->dpio_lock
);
1721 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1722 struct intel_digital_port
*dport
)
1727 switch (dport
->port
) {
1729 port_mask
= DPLL_PORTB_READY_MASK
;
1733 port_mask
= DPLL_PORTC_READY_MASK
;
1737 port_mask
= DPLL_PORTD_READY_MASK
;
1738 dpll_reg
= DPIO_PHY_STATUS
;
1744 if (wait_for((I915_READ(dpll_reg
) & port_mask
) == 0, 1000))
1745 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1746 port_name(dport
->port
), I915_READ(dpll_reg
));
1749 static void intel_prepare_shared_dpll(struct intel_crtc
*crtc
)
1751 struct drm_device
*dev
= crtc
->base
.dev
;
1752 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1753 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1755 if (WARN_ON(pll
== NULL
))
1758 WARN_ON(!pll
->refcount
);
1759 if (pll
->active
== 0) {
1760 DRM_DEBUG_DRIVER("setting up %s\n", pll
->name
);
1762 assert_shared_dpll_disabled(dev_priv
, pll
);
1764 pll
->mode_set(dev_priv
, pll
);
1769 * intel_enable_shared_dpll - enable PCH PLL
1770 * @dev_priv: i915 private structure
1771 * @pipe: pipe PLL to enable
1773 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1774 * drives the transcoder clock.
1776 static void intel_enable_shared_dpll(struct intel_crtc
*crtc
)
1778 struct drm_device
*dev
= crtc
->base
.dev
;
1779 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1780 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1782 if (WARN_ON(pll
== NULL
))
1785 if (WARN_ON(pll
->refcount
== 0))
1788 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1789 pll
->name
, pll
->active
, pll
->on
,
1790 crtc
->base
.base
.id
);
1792 if (pll
->active
++) {
1794 assert_shared_dpll_enabled(dev_priv
, pll
);
1799 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
1801 DRM_DEBUG_KMS("enabling %s\n", pll
->name
);
1802 pll
->enable(dev_priv
, pll
);
1806 static void intel_disable_shared_dpll(struct intel_crtc
*crtc
)
1808 struct drm_device
*dev
= crtc
->base
.dev
;
1809 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1810 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1812 /* PCH only available on ILK+ */
1813 BUG_ON(INTEL_INFO(dev
)->gen
< 5);
1814 if (WARN_ON(pll
== NULL
))
1817 if (WARN_ON(pll
->refcount
== 0))
1820 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1821 pll
->name
, pll
->active
, pll
->on
,
1822 crtc
->base
.base
.id
);
1824 if (WARN_ON(pll
->active
== 0)) {
1825 assert_shared_dpll_disabled(dev_priv
, pll
);
1829 assert_shared_dpll_enabled(dev_priv
, pll
);
1834 DRM_DEBUG_KMS("disabling %s\n", pll
->name
);
1835 pll
->disable(dev_priv
, pll
);
1838 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
1841 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1844 struct drm_device
*dev
= dev_priv
->dev
;
1845 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1846 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1847 uint32_t reg
, val
, pipeconf_val
;
1849 /* PCH only available on ILK+ */
1850 BUG_ON(!HAS_PCH_SPLIT(dev
));
1852 /* Make sure PCH DPLL is enabled */
1853 assert_shared_dpll_enabled(dev_priv
,
1854 intel_crtc_to_shared_dpll(intel_crtc
));
1856 /* FDI must be feeding us bits for PCH ports */
1857 assert_fdi_tx_enabled(dev_priv
, pipe
);
1858 assert_fdi_rx_enabled(dev_priv
, pipe
);
1860 if (HAS_PCH_CPT(dev
)) {
1861 /* Workaround: Set the timing override bit before enabling the
1862 * pch transcoder. */
1863 reg
= TRANS_CHICKEN2(pipe
);
1864 val
= I915_READ(reg
);
1865 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1866 I915_WRITE(reg
, val
);
1869 reg
= PCH_TRANSCONF(pipe
);
1870 val
= I915_READ(reg
);
1871 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1873 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1875 * make the BPC in transcoder be consistent with
1876 * that in pipeconf reg.
1878 val
&= ~PIPECONF_BPC_MASK
;
1879 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
1882 val
&= ~TRANS_INTERLACE_MASK
;
1883 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1884 if (HAS_PCH_IBX(dev_priv
->dev
) &&
1885 intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
))
1886 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1888 val
|= TRANS_INTERLACED
;
1890 val
|= TRANS_PROGRESSIVE
;
1892 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1893 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1894 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
1897 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1898 enum transcoder cpu_transcoder
)
1900 u32 val
, pipeconf_val
;
1902 /* PCH only available on ILK+ */
1903 BUG_ON(!HAS_PCH_SPLIT(dev_priv
->dev
));
1905 /* FDI must be feeding us bits for PCH ports */
1906 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
1907 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
1909 /* Workaround: set timing override bit. */
1910 val
= I915_READ(_TRANSA_CHICKEN2
);
1911 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1912 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1915 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
1917 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
1918 PIPECONF_INTERLACED_ILK
)
1919 val
|= TRANS_INTERLACED
;
1921 val
|= TRANS_PROGRESSIVE
;
1923 I915_WRITE(LPT_TRANSCONF
, val
);
1924 if (wait_for(I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
, 100))
1925 DRM_ERROR("Failed to enable PCH transcoder\n");
1928 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1931 struct drm_device
*dev
= dev_priv
->dev
;
1934 /* FDI relies on the transcoder */
1935 assert_fdi_tx_disabled(dev_priv
, pipe
);
1936 assert_fdi_rx_disabled(dev_priv
, pipe
);
1938 /* Ports must be off as well */
1939 assert_pch_ports_disabled(dev_priv
, pipe
);
1941 reg
= PCH_TRANSCONF(pipe
);
1942 val
= I915_READ(reg
);
1943 val
&= ~TRANS_ENABLE
;
1944 I915_WRITE(reg
, val
);
1945 /* wait for PCH transcoder off, transcoder state */
1946 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
1947 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
1949 if (!HAS_PCH_IBX(dev
)) {
1950 /* Workaround: Clear the timing override chicken bit again. */
1951 reg
= TRANS_CHICKEN2(pipe
);
1952 val
= I915_READ(reg
);
1953 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1954 I915_WRITE(reg
, val
);
1958 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
1962 val
= I915_READ(LPT_TRANSCONF
);
1963 val
&= ~TRANS_ENABLE
;
1964 I915_WRITE(LPT_TRANSCONF
, val
);
1965 /* wait for PCH transcoder off, transcoder state */
1966 if (wait_for((I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
) == 0, 50))
1967 DRM_ERROR("Failed to disable PCH transcoder\n");
1969 /* Workaround: clear timing override bit. */
1970 val
= I915_READ(_TRANSA_CHICKEN2
);
1971 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1972 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1976 * intel_enable_pipe - enable a pipe, asserting requirements
1977 * @crtc: crtc responsible for the pipe
1979 * Enable @crtc's pipe, making sure that various hardware specific requirements
1980 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1982 static void intel_enable_pipe(struct intel_crtc
*crtc
)
1984 struct drm_device
*dev
= crtc
->base
.dev
;
1985 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1986 enum pipe pipe
= crtc
->pipe
;
1987 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1989 enum pipe pch_transcoder
;
1993 assert_planes_disabled(dev_priv
, pipe
);
1994 assert_cursor_disabled(dev_priv
, pipe
);
1995 assert_sprites_disabled(dev_priv
, pipe
);
1997 if (HAS_PCH_LPT(dev_priv
->dev
))
1998 pch_transcoder
= TRANSCODER_A
;
2000 pch_transcoder
= pipe
;
2003 * A pipe without a PLL won't actually be able to drive bits from
2004 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2007 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
2008 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DSI
))
2009 assert_dsi_pll_enabled(dev_priv
);
2011 assert_pll_enabled(dev_priv
, pipe
);
2013 if (crtc
->config
.has_pch_encoder
) {
2014 /* if driving the PCH, we need FDI enabled */
2015 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
2016 assert_fdi_tx_pll_enabled(dev_priv
,
2017 (enum pipe
) cpu_transcoder
);
2019 /* FIXME: assert CPU port conditions for SNB+ */
2022 reg
= PIPECONF(cpu_transcoder
);
2023 val
= I915_READ(reg
);
2024 if (val
& PIPECONF_ENABLE
) {
2025 WARN_ON(!((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
2026 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
)));
2030 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
2035 * intel_disable_pipe - disable a pipe, asserting requirements
2036 * @crtc: crtc whose pipes is to be disabled
2038 * Disable the pipe of @crtc, making sure that various hardware
2039 * specific requirements are met, if applicable, e.g. plane
2040 * disabled, panel fitter off, etc.
2042 * Will wait until the pipe has shut down before returning.
2044 static void intel_disable_pipe(struct intel_crtc
*crtc
)
2046 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
2047 enum transcoder cpu_transcoder
= crtc
->config
.cpu_transcoder
;
2048 enum pipe pipe
= crtc
->pipe
;
2053 * Make sure planes won't keep trying to pump pixels to us,
2054 * or we might hang the display.
2056 assert_planes_disabled(dev_priv
, pipe
);
2057 assert_cursor_disabled(dev_priv
, pipe
);
2058 assert_sprites_disabled(dev_priv
, pipe
);
2060 reg
= PIPECONF(cpu_transcoder
);
2061 val
= I915_READ(reg
);
2062 if ((val
& PIPECONF_ENABLE
) == 0)
2066 * Double wide has implications for planes
2067 * so best keep it disabled when not needed.
2069 if (crtc
->config
.double_wide
)
2070 val
&= ~PIPECONF_DOUBLE_WIDE
;
2072 /* Don't disable pipe or pipe PLLs if needed */
2073 if (!(pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) &&
2074 !(pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
2075 val
&= ~PIPECONF_ENABLE
;
2077 I915_WRITE(reg
, val
);
2078 if ((val
& PIPECONF_ENABLE
) == 0)
2079 intel_wait_for_pipe_off(crtc
);
2083 * Plane regs are double buffered, going from enabled->disabled needs a
2084 * trigger in order to latch. The display address reg provides this.
2086 void intel_flush_primary_plane(struct drm_i915_private
*dev_priv
,
2089 struct drm_device
*dev
= dev_priv
->dev
;
2090 u32 reg
= INTEL_INFO(dev
)->gen
>= 4 ? DSPSURF(plane
) : DSPADDR(plane
);
2092 I915_WRITE(reg
, I915_READ(reg
));
2097 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2098 * @plane: plane to be enabled
2099 * @crtc: crtc for the plane
2101 * Enable @plane on @crtc, making sure that the pipe is running first.
2103 static void intel_enable_primary_hw_plane(struct drm_plane
*plane
,
2104 struct drm_crtc
*crtc
)
2106 struct drm_device
*dev
= plane
->dev
;
2107 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2108 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2110 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2111 assert_pipe_enabled(dev_priv
, intel_crtc
->pipe
);
2113 if (intel_crtc
->primary_enabled
)
2116 intel_crtc
->primary_enabled
= true;
2118 dev_priv
->display
.update_primary_plane(crtc
, plane
->fb
,
2122 * BDW signals flip done immediately if the plane
2123 * is disabled, even if the plane enable is already
2124 * armed to occur at the next vblank :(
2126 if (IS_BROADWELL(dev
))
2127 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2131 * intel_disable_primary_hw_plane - disable the primary hardware plane
2132 * @plane: plane to be disabled
2133 * @crtc: crtc for the plane
2135 * Disable @plane on @crtc, making sure that the pipe is running first.
2137 static void intel_disable_primary_hw_plane(struct drm_plane
*plane
,
2138 struct drm_crtc
*crtc
)
2140 struct drm_device
*dev
= plane
->dev
;
2141 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2142 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2144 assert_pipe_enabled(dev_priv
, intel_crtc
->pipe
);
2146 if (!intel_crtc
->primary_enabled
)
2149 intel_crtc
->primary_enabled
= false;
2151 dev_priv
->display
.update_primary_plane(crtc
, plane
->fb
,
2155 static bool need_vtd_wa(struct drm_device
*dev
)
2157 #ifdef CONFIG_INTEL_IOMMU
2158 if (INTEL_INFO(dev
)->gen
>= 6 && intel_iommu_gfx_mapped
)
2164 static int intel_align_height(struct drm_device
*dev
, int height
, bool tiled
)
2168 tile_height
= tiled
? (IS_GEN2(dev
) ? 16 : 8) : 1;
2169 return ALIGN(height
, tile_height
);
2173 intel_pin_and_fence_fb_obj(struct drm_device
*dev
,
2174 struct drm_i915_gem_object
*obj
,
2175 struct intel_engine_cs
*pipelined
)
2177 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2181 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
2183 switch (obj
->tiling_mode
) {
2184 case I915_TILING_NONE
:
2185 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
2186 alignment
= 128 * 1024;
2187 else if (INTEL_INFO(dev
)->gen
>= 4)
2188 alignment
= 4 * 1024;
2190 alignment
= 64 * 1024;
2193 /* pin() will align the object as required by fence */
2197 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2203 /* Note that the w/a also requires 64 PTE of padding following the
2204 * bo. We currently fill all unused PTE with the shadow page and so
2205 * we should always have valid PTE following the scanout preventing
2208 if (need_vtd_wa(dev
) && alignment
< 256 * 1024)
2209 alignment
= 256 * 1024;
2212 * Global gtt pte registers are special registers which actually forward
2213 * writes to a chunk of system memory. Which means that there is no risk
2214 * that the register values disappear as soon as we call
2215 * intel_runtime_pm_put(), so it is correct to wrap only the
2216 * pin/unpin/fence and not more.
2218 intel_runtime_pm_get(dev_priv
);
2220 dev_priv
->mm
.interruptible
= false;
2221 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
);
2223 goto err_interruptible
;
2225 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2226 * fence, whereas 965+ only requires a fence if using
2227 * framebuffer compression. For simplicity, we always install
2228 * a fence as the cost is not that onerous.
2230 ret
= i915_gem_object_get_fence(obj
);
2234 i915_gem_object_pin_fence(obj
);
2236 dev_priv
->mm
.interruptible
= true;
2237 intel_runtime_pm_put(dev_priv
);
2241 i915_gem_object_unpin_from_display_plane(obj
);
2243 dev_priv
->mm
.interruptible
= true;
2244 intel_runtime_pm_put(dev_priv
);
2248 void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
)
2250 WARN_ON(!mutex_is_locked(&obj
->base
.dev
->struct_mutex
));
2252 i915_gem_object_unpin_fence(obj
);
2253 i915_gem_object_unpin_from_display_plane(obj
);
2256 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2257 * is assumed to be a power-of-two. */
2258 unsigned long intel_gen4_compute_page_offset(int *x
, int *y
,
2259 unsigned int tiling_mode
,
2263 if (tiling_mode
!= I915_TILING_NONE
) {
2264 unsigned int tile_rows
, tiles
;
2269 tiles
= *x
/ (512/cpp
);
2272 return tile_rows
* pitch
* 8 + tiles
* 4096;
2274 unsigned int offset
;
2276 offset
= *y
* pitch
+ *x
* cpp
;
2278 *x
= (offset
& 4095) / cpp
;
2279 return offset
& -4096;
2283 int intel_format_to_fourcc(int format
)
2286 case DISPPLANE_8BPP
:
2287 return DRM_FORMAT_C8
;
2288 case DISPPLANE_BGRX555
:
2289 return DRM_FORMAT_XRGB1555
;
2290 case DISPPLANE_BGRX565
:
2291 return DRM_FORMAT_RGB565
;
2293 case DISPPLANE_BGRX888
:
2294 return DRM_FORMAT_XRGB8888
;
2295 case DISPPLANE_RGBX888
:
2296 return DRM_FORMAT_XBGR8888
;
2297 case DISPPLANE_BGRX101010
:
2298 return DRM_FORMAT_XRGB2101010
;
2299 case DISPPLANE_RGBX101010
:
2300 return DRM_FORMAT_XBGR2101010
;
2304 static bool intel_alloc_plane_obj(struct intel_crtc
*crtc
,
2305 struct intel_plane_config
*plane_config
)
2307 struct drm_device
*dev
= crtc
->base
.dev
;
2308 struct drm_i915_gem_object
*obj
= NULL
;
2309 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
2310 u32 base
= plane_config
->base
;
2312 if (plane_config
->size
== 0)
2315 obj
= i915_gem_object_create_stolen_for_preallocated(dev
, base
, base
,
2316 plane_config
->size
);
2320 if (plane_config
->tiled
) {
2321 obj
->tiling_mode
= I915_TILING_X
;
2322 obj
->stride
= crtc
->base
.primary
->fb
->pitches
[0];
2325 mode_cmd
.pixel_format
= crtc
->base
.primary
->fb
->pixel_format
;
2326 mode_cmd
.width
= crtc
->base
.primary
->fb
->width
;
2327 mode_cmd
.height
= crtc
->base
.primary
->fb
->height
;
2328 mode_cmd
.pitches
[0] = crtc
->base
.primary
->fb
->pitches
[0];
2330 mutex_lock(&dev
->struct_mutex
);
2332 if (intel_framebuffer_init(dev
, to_intel_framebuffer(crtc
->base
.primary
->fb
),
2334 DRM_DEBUG_KMS("intel fb init failed\n");
2338 obj
->frontbuffer_bits
= INTEL_FRONTBUFFER_PRIMARY(crtc
->pipe
);
2339 mutex_unlock(&dev
->struct_mutex
);
2341 DRM_DEBUG_KMS("plane fb obj %p\n", obj
);
2345 drm_gem_object_unreference(&obj
->base
);
2346 mutex_unlock(&dev
->struct_mutex
);
2350 static void intel_find_plane_obj(struct intel_crtc
*intel_crtc
,
2351 struct intel_plane_config
*plane_config
)
2353 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2355 struct intel_crtc
*i
;
2356 struct drm_i915_gem_object
*obj
;
2358 if (!intel_crtc
->base
.primary
->fb
)
2361 if (intel_alloc_plane_obj(intel_crtc
, plane_config
))
2364 kfree(intel_crtc
->base
.primary
->fb
);
2365 intel_crtc
->base
.primary
->fb
= NULL
;
2368 * Failed to alloc the obj, check to see if we should share
2369 * an fb with another CRTC instead
2371 for_each_crtc(dev
, c
) {
2372 i
= to_intel_crtc(c
);
2374 if (c
== &intel_crtc
->base
)
2380 obj
= intel_fb_obj(c
->primary
->fb
);
2384 if (i915_gem_obj_ggtt_offset(obj
) == plane_config
->base
) {
2385 drm_framebuffer_reference(c
->primary
->fb
);
2386 intel_crtc
->base
.primary
->fb
= c
->primary
->fb
;
2387 obj
->frontbuffer_bits
|= INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
);
2393 static void i9xx_update_primary_plane(struct drm_crtc
*crtc
,
2394 struct drm_framebuffer
*fb
,
2397 struct drm_device
*dev
= crtc
->dev
;
2398 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2399 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2400 struct drm_i915_gem_object
*obj
;
2401 int plane
= intel_crtc
->plane
;
2402 unsigned long linear_offset
;
2404 u32 reg
= DSPCNTR(plane
);
2407 if (!intel_crtc
->primary_enabled
) {
2409 if (INTEL_INFO(dev
)->gen
>= 4)
2410 I915_WRITE(DSPSURF(plane
), 0);
2412 I915_WRITE(DSPADDR(plane
), 0);
2417 obj
= intel_fb_obj(fb
);
2418 if (WARN_ON(obj
== NULL
))
2421 pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2423 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2425 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2427 if (INTEL_INFO(dev
)->gen
< 4) {
2428 if (intel_crtc
->pipe
== PIPE_B
)
2429 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
2431 /* pipesrc and dspsize control the size that is scaled from,
2432 * which should always be the user's requested size.
2434 I915_WRITE(DSPSIZE(plane
),
2435 ((intel_crtc
->config
.pipe_src_h
- 1) << 16) |
2436 (intel_crtc
->config
.pipe_src_w
- 1));
2437 I915_WRITE(DSPPOS(plane
), 0);
2440 switch (fb
->pixel_format
) {
2442 dspcntr
|= DISPPLANE_8BPP
;
2444 case DRM_FORMAT_XRGB1555
:
2445 case DRM_FORMAT_ARGB1555
:
2446 dspcntr
|= DISPPLANE_BGRX555
;
2448 case DRM_FORMAT_RGB565
:
2449 dspcntr
|= DISPPLANE_BGRX565
;
2451 case DRM_FORMAT_XRGB8888
:
2452 case DRM_FORMAT_ARGB8888
:
2453 dspcntr
|= DISPPLANE_BGRX888
;
2455 case DRM_FORMAT_XBGR8888
:
2456 case DRM_FORMAT_ABGR8888
:
2457 dspcntr
|= DISPPLANE_RGBX888
;
2459 case DRM_FORMAT_XRGB2101010
:
2460 case DRM_FORMAT_ARGB2101010
:
2461 dspcntr
|= DISPPLANE_BGRX101010
;
2463 case DRM_FORMAT_XBGR2101010
:
2464 case DRM_FORMAT_ABGR2101010
:
2465 dspcntr
|= DISPPLANE_RGBX101010
;
2471 if (INTEL_INFO(dev
)->gen
>= 4 &&
2472 obj
->tiling_mode
!= I915_TILING_NONE
)
2473 dspcntr
|= DISPPLANE_TILED
;
2476 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2478 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
2480 if (INTEL_INFO(dev
)->gen
>= 4) {
2481 intel_crtc
->dspaddr_offset
=
2482 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2485 linear_offset
-= intel_crtc
->dspaddr_offset
;
2487 intel_crtc
->dspaddr_offset
= linear_offset
;
2490 if (to_intel_plane(crtc
->primary
)->rotation
== BIT(DRM_ROTATE_180
)) {
2491 dspcntr
|= DISPPLANE_ROTATE_180
;
2493 x
+= (intel_crtc
->config
.pipe_src_w
- 1);
2494 y
+= (intel_crtc
->config
.pipe_src_h
- 1);
2496 /* Finding the last pixel of the last line of the display
2497 data and adding to linear_offset*/
2499 (intel_crtc
->config
.pipe_src_h
- 1) * fb
->pitches
[0] +
2500 (intel_crtc
->config
.pipe_src_w
- 1) * pixel_size
;
2503 I915_WRITE(reg
, dspcntr
);
2505 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2506 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2508 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2509 if (INTEL_INFO(dev
)->gen
>= 4) {
2510 I915_WRITE(DSPSURF(plane
),
2511 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2512 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2513 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2515 I915_WRITE(DSPADDR(plane
), i915_gem_obj_ggtt_offset(obj
) + linear_offset
);
2519 static void ironlake_update_primary_plane(struct drm_crtc
*crtc
,
2520 struct drm_framebuffer
*fb
,
2523 struct drm_device
*dev
= crtc
->dev
;
2524 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2525 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2526 struct drm_i915_gem_object
*obj
;
2527 int plane
= intel_crtc
->plane
;
2528 unsigned long linear_offset
;
2530 u32 reg
= DSPCNTR(plane
);
2533 if (!intel_crtc
->primary_enabled
) {
2535 I915_WRITE(DSPSURF(plane
), 0);
2540 obj
= intel_fb_obj(fb
);
2541 if (WARN_ON(obj
== NULL
))
2544 pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2546 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2548 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2550 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2551 dspcntr
|= DISPPLANE_PIPE_CSC_ENABLE
;
2553 switch (fb
->pixel_format
) {
2555 dspcntr
|= DISPPLANE_8BPP
;
2557 case DRM_FORMAT_RGB565
:
2558 dspcntr
|= DISPPLANE_BGRX565
;
2560 case DRM_FORMAT_XRGB8888
:
2561 case DRM_FORMAT_ARGB8888
:
2562 dspcntr
|= DISPPLANE_BGRX888
;
2564 case DRM_FORMAT_XBGR8888
:
2565 case DRM_FORMAT_ABGR8888
:
2566 dspcntr
|= DISPPLANE_RGBX888
;
2568 case DRM_FORMAT_XRGB2101010
:
2569 case DRM_FORMAT_ARGB2101010
:
2570 dspcntr
|= DISPPLANE_BGRX101010
;
2572 case DRM_FORMAT_XBGR2101010
:
2573 case DRM_FORMAT_ABGR2101010
:
2574 dspcntr
|= DISPPLANE_RGBX101010
;
2580 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2581 dspcntr
|= DISPPLANE_TILED
;
2583 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
))
2584 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2586 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
2587 intel_crtc
->dspaddr_offset
=
2588 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2591 linear_offset
-= intel_crtc
->dspaddr_offset
;
2592 if (to_intel_plane(crtc
->primary
)->rotation
== BIT(DRM_ROTATE_180
)) {
2593 dspcntr
|= DISPPLANE_ROTATE_180
;
2595 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
)) {
2596 x
+= (intel_crtc
->config
.pipe_src_w
- 1);
2597 y
+= (intel_crtc
->config
.pipe_src_h
- 1);
2599 /* Finding the last pixel of the last line of the display
2600 data and adding to linear_offset*/
2602 (intel_crtc
->config
.pipe_src_h
- 1) * fb
->pitches
[0] +
2603 (intel_crtc
->config
.pipe_src_w
- 1) * pixel_size
;
2607 I915_WRITE(reg
, dspcntr
);
2609 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2610 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2612 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2613 I915_WRITE(DSPSURF(plane
),
2614 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2615 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2616 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2618 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2619 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2624 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2626 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2627 int x
, int y
, enum mode_set_atomic state
)
2629 struct drm_device
*dev
= crtc
->dev
;
2630 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2632 if (dev_priv
->display
.disable_fbc
)
2633 dev_priv
->display
.disable_fbc(dev
);
2634 intel_increase_pllclock(dev
, to_intel_crtc(crtc
)->pipe
);
2636 dev_priv
->display
.update_primary_plane(crtc
, fb
, x
, y
);
2641 void intel_display_handle_reset(struct drm_device
*dev
)
2643 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2644 struct drm_crtc
*crtc
;
2647 * Flips in the rings have been nuked by the reset,
2648 * so complete all pending flips so that user space
2649 * will get its events and not get stuck.
2651 * Also update the base address of all primary
2652 * planes to the the last fb to make sure we're
2653 * showing the correct fb after a reset.
2655 * Need to make two loops over the crtcs so that we
2656 * don't try to grab a crtc mutex before the
2657 * pending_flip_queue really got woken up.
2660 for_each_crtc(dev
, crtc
) {
2661 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2662 enum plane plane
= intel_crtc
->plane
;
2664 intel_prepare_page_flip(dev
, plane
);
2665 intel_finish_page_flip_plane(dev
, plane
);
2668 for_each_crtc(dev
, crtc
) {
2669 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2671 drm_modeset_lock(&crtc
->mutex
, NULL
);
2673 * FIXME: Once we have proper support for primary planes (and
2674 * disabling them without disabling the entire crtc) allow again
2675 * a NULL crtc->primary->fb.
2677 if (intel_crtc
->active
&& crtc
->primary
->fb
)
2678 dev_priv
->display
.update_primary_plane(crtc
,
2682 drm_modeset_unlock(&crtc
->mutex
);
2687 intel_finish_fb(struct drm_framebuffer
*old_fb
)
2689 struct drm_i915_gem_object
*obj
= intel_fb_obj(old_fb
);
2690 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2691 bool was_interruptible
= dev_priv
->mm
.interruptible
;
2694 /* Big Hammer, we also need to ensure that any pending
2695 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2696 * current scanout is retired before unpinning the old
2699 * This should only fail upon a hung GPU, in which case we
2700 * can safely continue.
2702 dev_priv
->mm
.interruptible
= false;
2703 ret
= i915_gem_object_finish_gpu(obj
);
2704 dev_priv
->mm
.interruptible
= was_interruptible
;
2709 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
2711 struct drm_device
*dev
= crtc
->dev
;
2712 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2713 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2714 unsigned long flags
;
2717 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
2718 intel_crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
2721 spin_lock_irqsave(&dev
->event_lock
, flags
);
2722 pending
= to_intel_crtc(crtc
)->unpin_work
!= NULL
;
2723 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
2728 static void intel_update_pipe_size(struct intel_crtc
*crtc
)
2730 struct drm_device
*dev
= crtc
->base
.dev
;
2731 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2732 const struct drm_display_mode
*adjusted_mode
;
2738 * Update pipe size and adjust fitter if needed: the reason for this is
2739 * that in compute_mode_changes we check the native mode (not the pfit
2740 * mode) to see if we can flip rather than do a full mode set. In the
2741 * fastboot case, we'll flip, but if we don't update the pipesrc and
2742 * pfit state, we'll end up with a big fb scanned out into the wrong
2745 * To fix this properly, we need to hoist the checks up into
2746 * compute_mode_changes (or above), check the actual pfit state and
2747 * whether the platform allows pfit disable with pipe active, and only
2748 * then update the pipesrc and pfit state, even on the flip path.
2751 adjusted_mode
= &crtc
->config
.adjusted_mode
;
2753 I915_WRITE(PIPESRC(crtc
->pipe
),
2754 ((adjusted_mode
->crtc_hdisplay
- 1) << 16) |
2755 (adjusted_mode
->crtc_vdisplay
- 1));
2756 if (!crtc
->config
.pch_pfit
.enabled
&&
2757 (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) ||
2758 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
))) {
2759 I915_WRITE(PF_CTL(crtc
->pipe
), 0);
2760 I915_WRITE(PF_WIN_POS(crtc
->pipe
), 0);
2761 I915_WRITE(PF_WIN_SZ(crtc
->pipe
), 0);
2763 crtc
->config
.pipe_src_w
= adjusted_mode
->crtc_hdisplay
;
2764 crtc
->config
.pipe_src_h
= adjusted_mode
->crtc_vdisplay
;
2768 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2769 struct drm_framebuffer
*fb
)
2771 struct drm_device
*dev
= crtc
->dev
;
2772 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2773 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2774 enum pipe pipe
= intel_crtc
->pipe
;
2775 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
2776 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2777 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(old_fb
);
2780 if (intel_crtc_has_pending_flip(crtc
)) {
2781 DRM_ERROR("pipe is still busy with an old pageflip\n");
2787 DRM_ERROR("No FB bound\n");
2791 if (intel_crtc
->plane
> INTEL_INFO(dev
)->num_pipes
) {
2792 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2793 plane_name(intel_crtc
->plane
),
2794 INTEL_INFO(dev
)->num_pipes
);
2798 mutex_lock(&dev
->struct_mutex
);
2799 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, NULL
);
2801 i915_gem_track_fb(old_obj
, obj
,
2802 INTEL_FRONTBUFFER_PRIMARY(pipe
));
2803 mutex_unlock(&dev
->struct_mutex
);
2805 DRM_ERROR("pin & fence failed\n");
2809 intel_update_pipe_size(intel_crtc
);
2811 dev_priv
->display
.update_primary_plane(crtc
, fb
, x
, y
);
2813 if (intel_crtc
->active
)
2814 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
2816 crtc
->primary
->fb
= fb
;
2821 if (intel_crtc
->active
&& old_fb
!= fb
)
2822 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2823 mutex_lock(&dev
->struct_mutex
);
2824 intel_unpin_fb_obj(old_obj
);
2825 mutex_unlock(&dev
->struct_mutex
);
2828 mutex_lock(&dev
->struct_mutex
);
2829 intel_update_fbc(dev
);
2830 mutex_unlock(&dev
->struct_mutex
);
2835 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
2837 struct drm_device
*dev
= crtc
->dev
;
2838 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2839 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2840 int pipe
= intel_crtc
->pipe
;
2843 /* enable normal train */
2844 reg
= FDI_TX_CTL(pipe
);
2845 temp
= I915_READ(reg
);
2846 if (IS_IVYBRIDGE(dev
)) {
2847 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2848 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2850 temp
&= ~FDI_LINK_TRAIN_NONE
;
2851 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2853 I915_WRITE(reg
, temp
);
2855 reg
= FDI_RX_CTL(pipe
);
2856 temp
= I915_READ(reg
);
2857 if (HAS_PCH_CPT(dev
)) {
2858 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2859 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
2861 temp
&= ~FDI_LINK_TRAIN_NONE
;
2862 temp
|= FDI_LINK_TRAIN_NONE
;
2864 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
2866 /* wait one idle pattern time */
2870 /* IVB wants error correction enabled */
2871 if (IS_IVYBRIDGE(dev
))
2872 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
2873 FDI_FE_ERRC_ENABLE
);
2876 static bool pipe_has_enabled_pch(struct intel_crtc
*crtc
)
2878 return crtc
->base
.enabled
&& crtc
->active
&&
2879 crtc
->config
.has_pch_encoder
;
2882 static void ivb_modeset_global_resources(struct drm_device
*dev
)
2884 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2885 struct intel_crtc
*pipe_B_crtc
=
2886 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
2887 struct intel_crtc
*pipe_C_crtc
=
2888 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]);
2892 * When everything is off disable fdi C so that we could enable fdi B
2893 * with all lanes. Note that we don't care about enabled pipes without
2894 * an enabled pch encoder.
2896 if (!pipe_has_enabled_pch(pipe_B_crtc
) &&
2897 !pipe_has_enabled_pch(pipe_C_crtc
)) {
2898 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
2899 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
2901 temp
= I915_READ(SOUTH_CHICKEN1
);
2902 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
2903 DRM_DEBUG_KMS("disabling fdi C rx\n");
2904 I915_WRITE(SOUTH_CHICKEN1
, temp
);
2908 /* The FDI link training functions for ILK/Ibexpeak. */
2909 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
2911 struct drm_device
*dev
= crtc
->dev
;
2912 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2913 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2914 int pipe
= intel_crtc
->pipe
;
2915 u32 reg
, temp
, tries
;
2917 /* FDI needs bits from pipe first */
2918 assert_pipe_enabled(dev_priv
, pipe
);
2920 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2922 reg
= FDI_RX_IMR(pipe
);
2923 temp
= I915_READ(reg
);
2924 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2925 temp
&= ~FDI_RX_BIT_LOCK
;
2926 I915_WRITE(reg
, temp
);
2930 /* enable CPU FDI TX and PCH FDI RX */
2931 reg
= FDI_TX_CTL(pipe
);
2932 temp
= I915_READ(reg
);
2933 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
2934 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2935 temp
&= ~FDI_LINK_TRAIN_NONE
;
2936 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2937 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2939 reg
= FDI_RX_CTL(pipe
);
2940 temp
= I915_READ(reg
);
2941 temp
&= ~FDI_LINK_TRAIN_NONE
;
2942 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2943 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2948 /* Ironlake workaround, enable clock pointer after FDI enable*/
2949 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2950 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
2951 FDI_RX_PHASE_SYNC_POINTER_EN
);
2953 reg
= FDI_RX_IIR(pipe
);
2954 for (tries
= 0; tries
< 5; tries
++) {
2955 temp
= I915_READ(reg
);
2956 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2958 if ((temp
& FDI_RX_BIT_LOCK
)) {
2959 DRM_DEBUG_KMS("FDI train 1 done.\n");
2960 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2965 DRM_ERROR("FDI train 1 fail!\n");
2968 reg
= FDI_TX_CTL(pipe
);
2969 temp
= I915_READ(reg
);
2970 temp
&= ~FDI_LINK_TRAIN_NONE
;
2971 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2972 I915_WRITE(reg
, temp
);
2974 reg
= FDI_RX_CTL(pipe
);
2975 temp
= I915_READ(reg
);
2976 temp
&= ~FDI_LINK_TRAIN_NONE
;
2977 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2978 I915_WRITE(reg
, temp
);
2983 reg
= FDI_RX_IIR(pipe
);
2984 for (tries
= 0; tries
< 5; tries
++) {
2985 temp
= I915_READ(reg
);
2986 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2988 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2989 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2990 DRM_DEBUG_KMS("FDI train 2 done.\n");
2995 DRM_ERROR("FDI train 2 fail!\n");
2997 DRM_DEBUG_KMS("FDI train done\n");
3001 static const int snb_b_fdi_train_param
[] = {
3002 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
3003 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
3004 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
3005 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
3008 /* The FDI link training functions for SNB/Cougarpoint. */
3009 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
3011 struct drm_device
*dev
= crtc
->dev
;
3012 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3013 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3014 int pipe
= intel_crtc
->pipe
;
3015 u32 reg
, temp
, i
, retry
;
3017 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3019 reg
= FDI_RX_IMR(pipe
);
3020 temp
= I915_READ(reg
);
3021 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3022 temp
&= ~FDI_RX_BIT_LOCK
;
3023 I915_WRITE(reg
, temp
);
3028 /* enable CPU FDI TX and PCH FDI RX */
3029 reg
= FDI_TX_CTL(pipe
);
3030 temp
= I915_READ(reg
);
3031 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3032 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
3033 temp
&= ~FDI_LINK_TRAIN_NONE
;
3034 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3035 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3037 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3038 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3040 I915_WRITE(FDI_RX_MISC(pipe
),
3041 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3043 reg
= FDI_RX_CTL(pipe
);
3044 temp
= I915_READ(reg
);
3045 if (HAS_PCH_CPT(dev
)) {
3046 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3047 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3049 temp
&= ~FDI_LINK_TRAIN_NONE
;
3050 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3052 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3057 for (i
= 0; i
< 4; i
++) {
3058 reg
= FDI_TX_CTL(pipe
);
3059 temp
= I915_READ(reg
);
3060 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3061 temp
|= snb_b_fdi_train_param
[i
];
3062 I915_WRITE(reg
, temp
);
3067 for (retry
= 0; retry
< 5; retry
++) {
3068 reg
= FDI_RX_IIR(pipe
);
3069 temp
= I915_READ(reg
);
3070 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3071 if (temp
& FDI_RX_BIT_LOCK
) {
3072 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3073 DRM_DEBUG_KMS("FDI train 1 done.\n");
3082 DRM_ERROR("FDI train 1 fail!\n");
3085 reg
= FDI_TX_CTL(pipe
);
3086 temp
= I915_READ(reg
);
3087 temp
&= ~FDI_LINK_TRAIN_NONE
;
3088 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3090 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3092 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3094 I915_WRITE(reg
, temp
);
3096 reg
= FDI_RX_CTL(pipe
);
3097 temp
= I915_READ(reg
);
3098 if (HAS_PCH_CPT(dev
)) {
3099 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3100 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3102 temp
&= ~FDI_LINK_TRAIN_NONE
;
3103 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3105 I915_WRITE(reg
, temp
);
3110 for (i
= 0; i
< 4; i
++) {
3111 reg
= FDI_TX_CTL(pipe
);
3112 temp
= I915_READ(reg
);
3113 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3114 temp
|= snb_b_fdi_train_param
[i
];
3115 I915_WRITE(reg
, temp
);
3120 for (retry
= 0; retry
< 5; retry
++) {
3121 reg
= FDI_RX_IIR(pipe
);
3122 temp
= I915_READ(reg
);
3123 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3124 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3125 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3126 DRM_DEBUG_KMS("FDI train 2 done.\n");
3135 DRM_ERROR("FDI train 2 fail!\n");
3137 DRM_DEBUG_KMS("FDI train done.\n");
3140 /* Manual link training for Ivy Bridge A0 parts */
3141 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
3143 struct drm_device
*dev
= crtc
->dev
;
3144 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3145 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3146 int pipe
= intel_crtc
->pipe
;
3147 u32 reg
, temp
, i
, j
;
3149 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3151 reg
= FDI_RX_IMR(pipe
);
3152 temp
= I915_READ(reg
);
3153 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3154 temp
&= ~FDI_RX_BIT_LOCK
;
3155 I915_WRITE(reg
, temp
);
3160 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3161 I915_READ(FDI_RX_IIR(pipe
)));
3163 /* Try each vswing and preemphasis setting twice before moving on */
3164 for (j
= 0; j
< ARRAY_SIZE(snb_b_fdi_train_param
) * 2; j
++) {
3165 /* disable first in case we need to retry */
3166 reg
= FDI_TX_CTL(pipe
);
3167 temp
= I915_READ(reg
);
3168 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
3169 temp
&= ~FDI_TX_ENABLE
;
3170 I915_WRITE(reg
, temp
);
3172 reg
= FDI_RX_CTL(pipe
);
3173 temp
= I915_READ(reg
);
3174 temp
&= ~FDI_LINK_TRAIN_AUTO
;
3175 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3176 temp
&= ~FDI_RX_ENABLE
;
3177 I915_WRITE(reg
, temp
);
3179 /* enable CPU FDI TX and PCH FDI RX */
3180 reg
= FDI_TX_CTL(pipe
);
3181 temp
= I915_READ(reg
);
3182 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3183 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
3184 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
3185 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3186 temp
|= snb_b_fdi_train_param
[j
/2];
3187 temp
|= FDI_COMPOSITE_SYNC
;
3188 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3190 I915_WRITE(FDI_RX_MISC(pipe
),
3191 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3193 reg
= FDI_RX_CTL(pipe
);
3194 temp
= I915_READ(reg
);
3195 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3196 temp
|= FDI_COMPOSITE_SYNC
;
3197 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3200 udelay(1); /* should be 0.5us */
3202 for (i
= 0; i
< 4; i
++) {
3203 reg
= FDI_RX_IIR(pipe
);
3204 temp
= I915_READ(reg
);
3205 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3207 if (temp
& FDI_RX_BIT_LOCK
||
3208 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
3209 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3210 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3214 udelay(1); /* should be 0.5us */
3217 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j
/ 2);
3222 reg
= FDI_TX_CTL(pipe
);
3223 temp
= I915_READ(reg
);
3224 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3225 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
3226 I915_WRITE(reg
, temp
);
3228 reg
= FDI_RX_CTL(pipe
);
3229 temp
= I915_READ(reg
);
3230 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3231 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3232 I915_WRITE(reg
, temp
);
3235 udelay(2); /* should be 1.5us */
3237 for (i
= 0; i
< 4; i
++) {
3238 reg
= FDI_RX_IIR(pipe
);
3239 temp
= I915_READ(reg
);
3240 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3242 if (temp
& FDI_RX_SYMBOL_LOCK
||
3243 (I915_READ(reg
) & FDI_RX_SYMBOL_LOCK
)) {
3244 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3245 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3249 udelay(2); /* should be 1.5us */
3252 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j
/ 2);
3256 DRM_DEBUG_KMS("FDI train done.\n");
3259 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
3261 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3262 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3263 int pipe
= intel_crtc
->pipe
;
3267 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3268 reg
= FDI_RX_CTL(pipe
);
3269 temp
= I915_READ(reg
);
3270 temp
&= ~(FDI_DP_PORT_WIDTH_MASK
| (0x7 << 16));
3271 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
3272 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3273 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
3278 /* Switch from Rawclk to PCDclk */
3279 temp
= I915_READ(reg
);
3280 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
3285 /* Enable CPU FDI TX PLL, always on for Ironlake */
3286 reg
= FDI_TX_CTL(pipe
);
3287 temp
= I915_READ(reg
);
3288 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
3289 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
3296 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
3298 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3299 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3300 int pipe
= intel_crtc
->pipe
;
3303 /* Switch from PCDclk to Rawclk */
3304 reg
= FDI_RX_CTL(pipe
);
3305 temp
= I915_READ(reg
);
3306 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
3308 /* Disable CPU FDI TX PLL */
3309 reg
= FDI_TX_CTL(pipe
);
3310 temp
= I915_READ(reg
);
3311 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
3316 reg
= FDI_RX_CTL(pipe
);
3317 temp
= I915_READ(reg
);
3318 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
3320 /* Wait for the clocks to turn off. */
3325 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
3327 struct drm_device
*dev
= crtc
->dev
;
3328 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3329 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3330 int pipe
= intel_crtc
->pipe
;
3333 /* disable CPU FDI tx and PCH FDI rx */
3334 reg
= FDI_TX_CTL(pipe
);
3335 temp
= I915_READ(reg
);
3336 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
3339 reg
= FDI_RX_CTL(pipe
);
3340 temp
= I915_READ(reg
);
3341 temp
&= ~(0x7 << 16);
3342 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3343 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
3348 /* Ironlake workaround, disable clock pointer after downing FDI */
3349 if (HAS_PCH_IBX(dev
))
3350 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3352 /* still set train pattern 1 */
3353 reg
= FDI_TX_CTL(pipe
);
3354 temp
= I915_READ(reg
);
3355 temp
&= ~FDI_LINK_TRAIN_NONE
;
3356 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3357 I915_WRITE(reg
, temp
);
3359 reg
= FDI_RX_CTL(pipe
);
3360 temp
= I915_READ(reg
);
3361 if (HAS_PCH_CPT(dev
)) {
3362 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3363 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3365 temp
&= ~FDI_LINK_TRAIN_NONE
;
3366 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3368 /* BPC in FDI rx is consistent with that in PIPECONF */
3369 temp
&= ~(0x07 << 16);
3370 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3371 I915_WRITE(reg
, temp
);
3377 bool intel_has_pending_fb_unpin(struct drm_device
*dev
)
3379 struct intel_crtc
*crtc
;
3381 /* Note that we don't need to be called with mode_config.lock here
3382 * as our list of CRTC objects is static for the lifetime of the
3383 * device and so cannot disappear as we iterate. Similarly, we can
3384 * happily treat the predicates as racy, atomic checks as userspace
3385 * cannot claim and pin a new fb without at least acquring the
3386 * struct_mutex and so serialising with us.
3388 for_each_intel_crtc(dev
, crtc
) {
3389 if (atomic_read(&crtc
->unpin_work_count
) == 0)
3392 if (crtc
->unpin_work
)
3393 intel_wait_for_vblank(dev
, crtc
->pipe
);
3401 static void page_flip_completed(struct intel_crtc
*intel_crtc
)
3403 struct drm_i915_private
*dev_priv
= to_i915(intel_crtc
->base
.dev
);
3404 struct intel_unpin_work
*work
= intel_crtc
->unpin_work
;
3406 /* ensure that the unpin work is consistent wrt ->pending. */
3408 intel_crtc
->unpin_work
= NULL
;
3411 drm_send_vblank_event(intel_crtc
->base
.dev
,
3415 drm_crtc_vblank_put(&intel_crtc
->base
);
3417 wake_up_all(&dev_priv
->pending_flip_queue
);
3418 queue_work(dev_priv
->wq
, &work
->work
);
3420 trace_i915_flip_complete(intel_crtc
->plane
,
3421 work
->pending_flip_obj
);
3424 void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
3426 struct drm_device
*dev
= crtc
->dev
;
3427 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3429 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
3430 if (WARN_ON(wait_event_timeout(dev_priv
->pending_flip_queue
,
3431 !intel_crtc_has_pending_flip(crtc
),
3433 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3434 unsigned long flags
;
3436 spin_lock_irqsave(&dev
->event_lock
, flags
);
3437 if (intel_crtc
->unpin_work
) {
3438 WARN_ONCE(1, "Removing stuck page flip\n");
3439 page_flip_completed(intel_crtc
);
3441 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
3444 if (crtc
->primary
->fb
) {
3445 mutex_lock(&dev
->struct_mutex
);
3446 intel_finish_fb(crtc
->primary
->fb
);
3447 mutex_unlock(&dev
->struct_mutex
);
3451 /* Program iCLKIP clock to the desired frequency */
3452 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
3454 struct drm_device
*dev
= crtc
->dev
;
3455 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3456 int clock
= to_intel_crtc(crtc
)->config
.adjusted_mode
.crtc_clock
;
3457 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
3460 mutex_lock(&dev_priv
->dpio_lock
);
3462 /* It is necessary to ungate the pixclk gate prior to programming
3463 * the divisors, and gate it back when it is done.
3465 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
3467 /* Disable SSCCTL */
3468 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
3469 intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
) |
3473 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3474 if (clock
== 20000) {
3479 /* The iCLK virtual clock root frequency is in MHz,
3480 * but the adjusted_mode->crtc_clock in in KHz. To get the
3481 * divisors, it is necessary to divide one by another, so we
3482 * convert the virtual clock precision to KHz here for higher
3485 u32 iclk_virtual_root_freq
= 172800 * 1000;
3486 u32 iclk_pi_range
= 64;
3487 u32 desired_divisor
, msb_divisor_value
, pi_value
;
3489 desired_divisor
= (iclk_virtual_root_freq
/ clock
);
3490 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
3491 pi_value
= desired_divisor
% iclk_pi_range
;
3494 divsel
= msb_divisor_value
- 2;
3495 phaseinc
= pi_value
;
3498 /* This should not happen with any sane values */
3499 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
3500 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
3501 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
3502 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
3504 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3511 /* Program SSCDIVINTPHASE6 */
3512 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
3513 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
3514 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
3515 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
3516 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
3517 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
3518 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
3519 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
3521 /* Program SSCAUXDIV */
3522 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
3523 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3524 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
3525 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
3527 /* Enable modulator and associated divider */
3528 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
3529 temp
&= ~SBI_SSCCTL_DISABLE
;
3530 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
3532 /* Wait for initialization time */
3535 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
3537 mutex_unlock(&dev_priv
->dpio_lock
);
3540 static void ironlake_pch_transcoder_set_timings(struct intel_crtc
*crtc
,
3541 enum pipe pch_transcoder
)
3543 struct drm_device
*dev
= crtc
->base
.dev
;
3544 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3545 enum transcoder cpu_transcoder
= crtc
->config
.cpu_transcoder
;
3547 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder
),
3548 I915_READ(HTOTAL(cpu_transcoder
)));
3549 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder
),
3550 I915_READ(HBLANK(cpu_transcoder
)));
3551 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder
),
3552 I915_READ(HSYNC(cpu_transcoder
)));
3554 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder
),
3555 I915_READ(VTOTAL(cpu_transcoder
)));
3556 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder
),
3557 I915_READ(VBLANK(cpu_transcoder
)));
3558 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder
),
3559 I915_READ(VSYNC(cpu_transcoder
)));
3560 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder
),
3561 I915_READ(VSYNCSHIFT(cpu_transcoder
)));
3564 static void cpt_enable_fdi_bc_bifurcation(struct drm_device
*dev
)
3566 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3569 temp
= I915_READ(SOUTH_CHICKEN1
);
3570 if (temp
& FDI_BC_BIFURCATION_SELECT
)
3573 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
3574 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
3576 temp
|= FDI_BC_BIFURCATION_SELECT
;
3577 DRM_DEBUG_KMS("enabling fdi C rx\n");
3578 I915_WRITE(SOUTH_CHICKEN1
, temp
);
3579 POSTING_READ(SOUTH_CHICKEN1
);
3582 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc
*intel_crtc
)
3584 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3585 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3587 switch (intel_crtc
->pipe
) {
3591 if (intel_crtc
->config
.fdi_lanes
> 2)
3592 WARN_ON(I915_READ(SOUTH_CHICKEN1
) & FDI_BC_BIFURCATION_SELECT
);
3594 cpt_enable_fdi_bc_bifurcation(dev
);
3598 cpt_enable_fdi_bc_bifurcation(dev
);
3607 * Enable PCH resources required for PCH ports:
3609 * - FDI training & RX/TX
3610 * - update transcoder timings
3611 * - DP transcoding bits
3614 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
3616 struct drm_device
*dev
= crtc
->dev
;
3617 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3618 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3619 int pipe
= intel_crtc
->pipe
;
3622 assert_pch_transcoder_disabled(dev_priv
, pipe
);
3624 if (IS_IVYBRIDGE(dev
))
3625 ivybridge_update_fdi_bc_bifurcation(intel_crtc
);
3627 /* Write the TU size bits before fdi link training, so that error
3628 * detection works. */
3629 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
3630 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
3632 /* For PCH output, training FDI link */
3633 dev_priv
->display
.fdi_link_train(crtc
);
3635 /* We need to program the right clock selection before writing the pixel
3636 * mutliplier into the DPLL. */
3637 if (HAS_PCH_CPT(dev
)) {
3640 temp
= I915_READ(PCH_DPLL_SEL
);
3641 temp
|= TRANS_DPLL_ENABLE(pipe
);
3642 sel
= TRANS_DPLLB_SEL(pipe
);
3643 if (intel_crtc
->config
.shared_dpll
== DPLL_ID_PCH_PLL_B
)
3647 I915_WRITE(PCH_DPLL_SEL
, temp
);
3650 /* XXX: pch pll's can be enabled any time before we enable the PCH
3651 * transcoder, and we actually should do this to not upset any PCH
3652 * transcoder that already use the clock when we share it.
3654 * Note that enable_shared_dpll tries to do the right thing, but
3655 * get_shared_dpll unconditionally resets the pll - we need that to have
3656 * the right LVDS enable sequence. */
3657 intel_enable_shared_dpll(intel_crtc
);
3659 /* set transcoder timing, panel must allow it */
3660 assert_panel_unlocked(dev_priv
, pipe
);
3661 ironlake_pch_transcoder_set_timings(intel_crtc
, pipe
);
3663 intel_fdi_normal_train(crtc
);
3665 /* For PCH DP, enable TRANS_DP_CTL */
3666 if (HAS_PCH_CPT(dev
) &&
3667 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
3668 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3669 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
3670 reg
= TRANS_DP_CTL(pipe
);
3671 temp
= I915_READ(reg
);
3672 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
3673 TRANS_DP_SYNC_MASK
|
3675 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
3676 TRANS_DP_ENH_FRAMING
);
3677 temp
|= bpc
<< 9; /* same format but at 11:9 */
3679 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
3680 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
3681 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
3682 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
3684 switch (intel_trans_dp_port_sel(crtc
)) {
3686 temp
|= TRANS_DP_PORT_SEL_B
;
3689 temp
|= TRANS_DP_PORT_SEL_C
;
3692 temp
|= TRANS_DP_PORT_SEL_D
;
3698 I915_WRITE(reg
, temp
);
3701 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
3704 static void lpt_pch_enable(struct drm_crtc
*crtc
)
3706 struct drm_device
*dev
= crtc
->dev
;
3707 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3708 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3709 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
3711 assert_pch_transcoder_disabled(dev_priv
, TRANSCODER_A
);
3713 lpt_program_iclkip(crtc
);
3715 /* Set transcoder timing. */
3716 ironlake_pch_transcoder_set_timings(intel_crtc
, PIPE_A
);
3718 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
3721 void intel_put_shared_dpll(struct intel_crtc
*crtc
)
3723 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
3728 if (pll
->refcount
== 0) {
3729 WARN(1, "bad %s refcount\n", pll
->name
);
3733 if (--pll
->refcount
== 0) {
3735 WARN_ON(pll
->active
);
3738 crtc
->config
.shared_dpll
= DPLL_ID_PRIVATE
;
3741 struct intel_shared_dpll
*intel_get_shared_dpll(struct intel_crtc
*crtc
)
3743 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
3744 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
3745 enum intel_dpll_id i
;
3748 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3749 crtc
->base
.base
.id
, pll
->name
);
3750 intel_put_shared_dpll(crtc
);
3753 if (HAS_PCH_IBX(dev_priv
->dev
)) {
3754 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3755 i
= (enum intel_dpll_id
) crtc
->pipe
;
3756 pll
= &dev_priv
->shared_dplls
[i
];
3758 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3759 crtc
->base
.base
.id
, pll
->name
);
3761 WARN_ON(pll
->refcount
);
3766 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3767 pll
= &dev_priv
->shared_dplls
[i
];
3769 /* Only want to check enabled timings first */
3770 if (pll
->refcount
== 0)
3773 if (memcmp(&crtc
->config
.dpll_hw_state
, &pll
->hw_state
,
3774 sizeof(pll
->hw_state
)) == 0) {
3775 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3777 pll
->name
, pll
->refcount
, pll
->active
);
3783 /* Ok no matching timings, maybe there's a free one? */
3784 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3785 pll
= &dev_priv
->shared_dplls
[i
];
3786 if (pll
->refcount
== 0) {
3787 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3788 crtc
->base
.base
.id
, pll
->name
);
3796 if (pll
->refcount
== 0)
3797 pll
->hw_state
= crtc
->config
.dpll_hw_state
;
3799 crtc
->config
.shared_dpll
= i
;
3800 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll
->name
,
3801 pipe_name(crtc
->pipe
));
3808 static void cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
3810 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3811 int dslreg
= PIPEDSL(pipe
);
3814 temp
= I915_READ(dslreg
);
3816 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
3817 if (wait_for(I915_READ(dslreg
) != temp
, 5))
3818 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
3822 static void ironlake_pfit_enable(struct intel_crtc
*crtc
)
3824 struct drm_device
*dev
= crtc
->base
.dev
;
3825 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3826 int pipe
= crtc
->pipe
;
3828 if (crtc
->config
.pch_pfit
.enabled
) {
3829 /* Force use of hard-coded filter coefficients
3830 * as some pre-programmed values are broken,
3833 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
3834 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
3835 PF_PIPE_SEL_IVB(pipe
));
3837 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
3838 I915_WRITE(PF_WIN_POS(pipe
), crtc
->config
.pch_pfit
.pos
);
3839 I915_WRITE(PF_WIN_SZ(pipe
), crtc
->config
.pch_pfit
.size
);
3843 static void intel_enable_planes(struct drm_crtc
*crtc
)
3845 struct drm_device
*dev
= crtc
->dev
;
3846 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
3847 struct drm_plane
*plane
;
3848 struct intel_plane
*intel_plane
;
3850 drm_for_each_legacy_plane(plane
, &dev
->mode_config
.plane_list
) {
3851 intel_plane
= to_intel_plane(plane
);
3852 if (intel_plane
->pipe
== pipe
)
3853 intel_plane_restore(&intel_plane
->base
);
3857 static void intel_disable_planes(struct drm_crtc
*crtc
)
3859 struct drm_device
*dev
= crtc
->dev
;
3860 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
3861 struct drm_plane
*plane
;
3862 struct intel_plane
*intel_plane
;
3864 drm_for_each_legacy_plane(plane
, &dev
->mode_config
.plane_list
) {
3865 intel_plane
= to_intel_plane(plane
);
3866 if (intel_plane
->pipe
== pipe
)
3867 intel_plane_disable(&intel_plane
->base
);
3871 void hsw_enable_ips(struct intel_crtc
*crtc
)
3873 struct drm_device
*dev
= crtc
->base
.dev
;
3874 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3876 if (!crtc
->config
.ips_enabled
)
3879 /* We can only enable IPS after we enable a plane and wait for a vblank */
3880 intel_wait_for_vblank(dev
, crtc
->pipe
);
3882 assert_plane_enabled(dev_priv
, crtc
->plane
);
3883 if (IS_BROADWELL(dev
)) {
3884 mutex_lock(&dev_priv
->rps
.hw_lock
);
3885 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0xc0000000));
3886 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3887 /* Quoting Art Runyan: "its not safe to expect any particular
3888 * value in IPS_CTL bit 31 after enabling IPS through the
3889 * mailbox." Moreover, the mailbox may return a bogus state,
3890 * so we need to just enable it and continue on.
3893 I915_WRITE(IPS_CTL
, IPS_ENABLE
);
3894 /* The bit only becomes 1 in the next vblank, so this wait here
3895 * is essentially intel_wait_for_vblank. If we don't have this
3896 * and don't wait for vblanks until the end of crtc_enable, then
3897 * the HW state readout code will complain that the expected
3898 * IPS_CTL value is not the one we read. */
3899 if (wait_for(I915_READ_NOTRACE(IPS_CTL
) & IPS_ENABLE
, 50))
3900 DRM_ERROR("Timed out waiting for IPS enable\n");
3904 void hsw_disable_ips(struct intel_crtc
*crtc
)
3906 struct drm_device
*dev
= crtc
->base
.dev
;
3907 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3909 if (!crtc
->config
.ips_enabled
)
3912 assert_plane_enabled(dev_priv
, crtc
->plane
);
3913 if (IS_BROADWELL(dev
)) {
3914 mutex_lock(&dev_priv
->rps
.hw_lock
);
3915 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0));
3916 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3917 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3918 if (wait_for((I915_READ(IPS_CTL
) & IPS_ENABLE
) == 0, 42))
3919 DRM_ERROR("Timed out waiting for IPS disable\n");
3921 I915_WRITE(IPS_CTL
, 0);
3922 POSTING_READ(IPS_CTL
);
3925 /* We need to wait for a vblank before we can disable the plane. */
3926 intel_wait_for_vblank(dev
, crtc
->pipe
);
3929 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3930 static void intel_crtc_load_lut(struct drm_crtc
*crtc
)
3932 struct drm_device
*dev
= crtc
->dev
;
3933 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3934 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3935 enum pipe pipe
= intel_crtc
->pipe
;
3936 int palreg
= PALETTE(pipe
);
3938 bool reenable_ips
= false;
3940 /* The clocks have to be on to load the palette. */
3941 if (!crtc
->enabled
|| !intel_crtc
->active
)
3944 if (!HAS_PCH_SPLIT(dev_priv
->dev
)) {
3945 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
))
3946 assert_dsi_pll_enabled(dev_priv
);
3948 assert_pll_enabled(dev_priv
, pipe
);
3951 /* use legacy palette for Ironlake */
3952 if (!HAS_GMCH_DISPLAY(dev
))
3953 palreg
= LGC_PALETTE(pipe
);
3955 /* Workaround : Do not read or write the pipe palette/gamma data while
3956 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3958 if (IS_HASWELL(dev
) && intel_crtc
->config
.ips_enabled
&&
3959 ((I915_READ(GAMMA_MODE(pipe
)) & GAMMA_MODE_MODE_MASK
) ==
3960 GAMMA_MODE_MODE_SPLIT
)) {
3961 hsw_disable_ips(intel_crtc
);
3962 reenable_ips
= true;
3965 for (i
= 0; i
< 256; i
++) {
3966 I915_WRITE(palreg
+ 4 * i
,
3967 (intel_crtc
->lut_r
[i
] << 16) |
3968 (intel_crtc
->lut_g
[i
] << 8) |
3969 intel_crtc
->lut_b
[i
]);
3973 hsw_enable_ips(intel_crtc
);
3976 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
3978 if (!enable
&& intel_crtc
->overlay
) {
3979 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3980 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3982 mutex_lock(&dev
->struct_mutex
);
3983 dev_priv
->mm
.interruptible
= false;
3984 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
3985 dev_priv
->mm
.interruptible
= true;
3986 mutex_unlock(&dev
->struct_mutex
);
3989 /* Let userspace switch the overlay on again. In most cases userspace
3990 * has to recompute where to put it anyway.
3994 static void intel_crtc_enable_planes(struct drm_crtc
*crtc
)
3996 struct drm_device
*dev
= crtc
->dev
;
3997 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3998 int pipe
= intel_crtc
->pipe
;
4000 assert_vblank_disabled(crtc
);
4002 drm_vblank_on(dev
, pipe
);
4004 intel_enable_primary_hw_plane(crtc
->primary
, crtc
);
4005 intel_enable_planes(crtc
);
4006 intel_crtc_update_cursor(crtc
, true);
4007 intel_crtc_dpms_overlay(intel_crtc
, true);
4009 hsw_enable_ips(intel_crtc
);
4011 mutex_lock(&dev
->struct_mutex
);
4012 intel_update_fbc(dev
);
4013 mutex_unlock(&dev
->struct_mutex
);
4016 * FIXME: Once we grow proper nuclear flip support out of this we need
4017 * to compute the mask of flip planes precisely. For the time being
4018 * consider this a flip from a NULL plane.
4020 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_ALL_MASK(pipe
));
4023 static void intel_crtc_disable_planes(struct drm_crtc
*crtc
)
4025 struct drm_device
*dev
= crtc
->dev
;
4026 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4027 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4028 int pipe
= intel_crtc
->pipe
;
4029 int plane
= intel_crtc
->plane
;
4031 intel_crtc_wait_for_pending_flips(crtc
);
4033 if (dev_priv
->fbc
.plane
== plane
)
4034 intel_disable_fbc(dev
);
4036 hsw_disable_ips(intel_crtc
);
4038 intel_crtc_dpms_overlay(intel_crtc
, false);
4039 intel_crtc_update_cursor(crtc
, false);
4040 intel_disable_planes(crtc
);
4041 intel_disable_primary_hw_plane(crtc
->primary
, crtc
);
4044 * FIXME: Once we grow proper nuclear flip support out of this we need
4045 * to compute the mask of flip planes precisely. For the time being
4046 * consider this a flip to a NULL plane.
4048 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_ALL_MASK(pipe
));
4050 drm_vblank_off(dev
, pipe
);
4052 assert_vblank_disabled(crtc
);
4055 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
4057 struct drm_device
*dev
= crtc
->dev
;
4058 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4059 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4060 struct intel_encoder
*encoder
;
4061 int pipe
= intel_crtc
->pipe
;
4063 WARN_ON(!crtc
->enabled
);
4065 if (intel_crtc
->active
)
4068 if (intel_crtc
->config
.has_pch_encoder
)
4069 intel_prepare_shared_dpll(intel_crtc
);
4071 if (intel_crtc
->config
.has_dp_encoder
)
4072 intel_dp_set_m_n(intel_crtc
);
4074 intel_set_pipe_timings(intel_crtc
);
4076 if (intel_crtc
->config
.has_pch_encoder
) {
4077 intel_cpu_transcoder_set_m_n(intel_crtc
,
4078 &intel_crtc
->config
.fdi_m_n
, NULL
);
4081 ironlake_set_pipeconf(crtc
);
4083 intel_crtc
->active
= true;
4085 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
4086 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, true);
4088 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4089 if (encoder
->pre_enable
)
4090 encoder
->pre_enable(encoder
);
4092 if (intel_crtc
->config
.has_pch_encoder
) {
4093 /* Note: FDI PLL enabling _must_ be done before we enable the
4094 * cpu pipes, hence this is separate from all the other fdi/pch
4096 ironlake_fdi_pll_enable(intel_crtc
);
4098 assert_fdi_tx_disabled(dev_priv
, pipe
);
4099 assert_fdi_rx_disabled(dev_priv
, pipe
);
4102 ironlake_pfit_enable(intel_crtc
);
4105 * On ILK+ LUT must be loaded before the pipe is running but with
4108 intel_crtc_load_lut(crtc
);
4110 intel_update_watermarks(crtc
);
4111 intel_enable_pipe(intel_crtc
);
4113 if (intel_crtc
->config
.has_pch_encoder
)
4114 ironlake_pch_enable(crtc
);
4116 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4117 encoder
->enable(encoder
);
4119 if (HAS_PCH_CPT(dev
))
4120 cpt_verify_modeset(dev
, intel_crtc
->pipe
);
4122 intel_crtc_enable_planes(crtc
);
4125 /* IPS only exists on ULT machines and is tied to pipe A. */
4126 static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc
)
4128 return HAS_IPS(crtc
->base
.dev
) && crtc
->pipe
== PIPE_A
;
4132 * This implements the workaround described in the "notes" section of the mode
4133 * set sequence documentation. When going from no pipes or single pipe to
4134 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4135 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4137 static void haswell_mode_set_planes_workaround(struct intel_crtc
*crtc
)
4139 struct drm_device
*dev
= crtc
->base
.dev
;
4140 struct intel_crtc
*crtc_it
, *other_active_crtc
= NULL
;
4142 /* We want to get the other_active_crtc only if there's only 1 other
4144 for_each_intel_crtc(dev
, crtc_it
) {
4145 if (!crtc_it
->active
|| crtc_it
== crtc
)
4148 if (other_active_crtc
)
4151 other_active_crtc
= crtc_it
;
4153 if (!other_active_crtc
)
4156 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
4157 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
4160 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
4162 struct drm_device
*dev
= crtc
->dev
;
4163 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4164 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4165 struct intel_encoder
*encoder
;
4166 int pipe
= intel_crtc
->pipe
;
4168 WARN_ON(!crtc
->enabled
);
4170 if (intel_crtc
->active
)
4173 if (intel_crtc_to_shared_dpll(intel_crtc
))
4174 intel_enable_shared_dpll(intel_crtc
);
4176 if (intel_crtc
->config
.has_dp_encoder
)
4177 intel_dp_set_m_n(intel_crtc
);
4179 intel_set_pipe_timings(intel_crtc
);
4181 if (intel_crtc
->config
.has_pch_encoder
) {
4182 intel_cpu_transcoder_set_m_n(intel_crtc
,
4183 &intel_crtc
->config
.fdi_m_n
, NULL
);
4186 haswell_set_pipeconf(crtc
);
4188 intel_set_pipe_csc(crtc
);
4190 intel_crtc
->active
= true;
4192 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
4193 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4194 if (encoder
->pre_enable
)
4195 encoder
->pre_enable(encoder
);
4197 if (intel_crtc
->config
.has_pch_encoder
) {
4198 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, true);
4199 dev_priv
->display
.fdi_link_train(crtc
);
4202 intel_ddi_enable_pipe_clock(intel_crtc
);
4204 ironlake_pfit_enable(intel_crtc
);
4207 * On ILK+ LUT must be loaded before the pipe is running but with
4210 intel_crtc_load_lut(crtc
);
4212 intel_ddi_set_pipe_settings(crtc
);
4213 intel_ddi_enable_transcoder_func(crtc
);
4215 intel_update_watermarks(crtc
);
4216 intel_enable_pipe(intel_crtc
);
4218 if (intel_crtc
->config
.has_pch_encoder
)
4219 lpt_pch_enable(crtc
);
4221 if (intel_crtc
->config
.dp_encoder_is_mst
)
4222 intel_ddi_set_vc_payload_alloc(crtc
, true);
4224 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4225 encoder
->enable(encoder
);
4226 intel_opregion_notify_encoder(encoder
, true);
4229 /* If we change the relative order between pipe/planes enabling, we need
4230 * to change the workaround. */
4231 haswell_mode_set_planes_workaround(intel_crtc
);
4232 intel_crtc_enable_planes(crtc
);
4235 static void ironlake_pfit_disable(struct intel_crtc
*crtc
)
4237 struct drm_device
*dev
= crtc
->base
.dev
;
4238 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4239 int pipe
= crtc
->pipe
;
4241 /* To avoid upsetting the power well on haswell only disable the pfit if
4242 * it's in use. The hw state code will make sure we get this right. */
4243 if (crtc
->config
.pch_pfit
.enabled
) {
4244 I915_WRITE(PF_CTL(pipe
), 0);
4245 I915_WRITE(PF_WIN_POS(pipe
), 0);
4246 I915_WRITE(PF_WIN_SZ(pipe
), 0);
4250 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
4252 struct drm_device
*dev
= crtc
->dev
;
4253 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4254 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4255 struct intel_encoder
*encoder
;
4256 int pipe
= intel_crtc
->pipe
;
4259 if (!intel_crtc
->active
)
4262 intel_crtc_disable_planes(crtc
);
4264 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4265 encoder
->disable(encoder
);
4267 if (intel_crtc
->config
.has_pch_encoder
)
4268 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, false);
4270 intel_disable_pipe(intel_crtc
);
4272 ironlake_pfit_disable(intel_crtc
);
4274 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4275 if (encoder
->post_disable
)
4276 encoder
->post_disable(encoder
);
4278 if (intel_crtc
->config
.has_pch_encoder
) {
4279 ironlake_fdi_disable(crtc
);
4281 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
4282 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, true);
4284 if (HAS_PCH_CPT(dev
)) {
4285 /* disable TRANS_DP_CTL */
4286 reg
= TRANS_DP_CTL(pipe
);
4287 temp
= I915_READ(reg
);
4288 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
|
4289 TRANS_DP_PORT_SEL_MASK
);
4290 temp
|= TRANS_DP_PORT_SEL_NONE
;
4291 I915_WRITE(reg
, temp
);
4293 /* disable DPLL_SEL */
4294 temp
= I915_READ(PCH_DPLL_SEL
);
4295 temp
&= ~(TRANS_DPLL_ENABLE(pipe
) | TRANS_DPLLB_SEL(pipe
));
4296 I915_WRITE(PCH_DPLL_SEL
, temp
);
4299 /* disable PCH DPLL */
4300 intel_disable_shared_dpll(intel_crtc
);
4302 ironlake_fdi_pll_disable(intel_crtc
);
4305 intel_crtc
->active
= false;
4306 intel_update_watermarks(crtc
);
4308 mutex_lock(&dev
->struct_mutex
);
4309 intel_update_fbc(dev
);
4310 mutex_unlock(&dev
->struct_mutex
);
4313 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
4315 struct drm_device
*dev
= crtc
->dev
;
4316 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4317 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4318 struct intel_encoder
*encoder
;
4319 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
4321 if (!intel_crtc
->active
)
4324 intel_crtc_disable_planes(crtc
);
4326 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4327 intel_opregion_notify_encoder(encoder
, false);
4328 encoder
->disable(encoder
);
4331 if (intel_crtc
->config
.has_pch_encoder
)
4332 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, false);
4333 intel_disable_pipe(intel_crtc
);
4335 if (intel_crtc
->config
.dp_encoder_is_mst
)
4336 intel_ddi_set_vc_payload_alloc(crtc
, false);
4338 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
4340 ironlake_pfit_disable(intel_crtc
);
4342 intel_ddi_disable_pipe_clock(intel_crtc
);
4344 if (intel_crtc
->config
.has_pch_encoder
) {
4345 lpt_disable_pch_transcoder(dev_priv
);
4346 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, true);
4347 intel_ddi_fdi_disable(crtc
);
4350 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4351 if (encoder
->post_disable
)
4352 encoder
->post_disable(encoder
);
4354 intel_crtc
->active
= false;
4355 intel_update_watermarks(crtc
);
4357 mutex_lock(&dev
->struct_mutex
);
4358 intel_update_fbc(dev
);
4359 mutex_unlock(&dev
->struct_mutex
);
4361 if (intel_crtc_to_shared_dpll(intel_crtc
))
4362 intel_disable_shared_dpll(intel_crtc
);
4365 static void ironlake_crtc_off(struct drm_crtc
*crtc
)
4367 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4368 intel_put_shared_dpll(intel_crtc
);
4372 static void i9xx_pfit_enable(struct intel_crtc
*crtc
)
4374 struct drm_device
*dev
= crtc
->base
.dev
;
4375 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4376 struct intel_crtc_config
*pipe_config
= &crtc
->config
;
4378 if (!crtc
->config
.gmch_pfit
.control
)
4382 * The panel fitter should only be adjusted whilst the pipe is disabled,
4383 * according to register description and PRM.
4385 WARN_ON(I915_READ(PFIT_CONTROL
) & PFIT_ENABLE
);
4386 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
4388 I915_WRITE(PFIT_PGM_RATIOS
, pipe_config
->gmch_pfit
.pgm_ratios
);
4389 I915_WRITE(PFIT_CONTROL
, pipe_config
->gmch_pfit
.control
);
4391 /* Border color in case we don't scale up to the full screen. Black by
4392 * default, change to something else for debugging. */
4393 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
4396 static enum intel_display_power_domain
port_to_power_domain(enum port port
)
4400 return POWER_DOMAIN_PORT_DDI_A_4_LANES
;
4402 return POWER_DOMAIN_PORT_DDI_B_4_LANES
;
4404 return POWER_DOMAIN_PORT_DDI_C_4_LANES
;
4406 return POWER_DOMAIN_PORT_DDI_D_4_LANES
;
4409 return POWER_DOMAIN_PORT_OTHER
;
4413 #define for_each_power_domain(domain, mask) \
4414 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4415 if ((1 << (domain)) & (mask))
4417 enum intel_display_power_domain
4418 intel_display_port_power_domain(struct intel_encoder
*intel_encoder
)
4420 struct drm_device
*dev
= intel_encoder
->base
.dev
;
4421 struct intel_digital_port
*intel_dig_port
;
4423 switch (intel_encoder
->type
) {
4424 case INTEL_OUTPUT_UNKNOWN
:
4425 /* Only DDI platforms should ever use this output type */
4426 WARN_ON_ONCE(!HAS_DDI(dev
));
4427 case INTEL_OUTPUT_DISPLAYPORT
:
4428 case INTEL_OUTPUT_HDMI
:
4429 case INTEL_OUTPUT_EDP
:
4430 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
4431 return port_to_power_domain(intel_dig_port
->port
);
4432 case INTEL_OUTPUT_DP_MST
:
4433 intel_dig_port
= enc_to_mst(&intel_encoder
->base
)->primary
;
4434 return port_to_power_domain(intel_dig_port
->port
);
4435 case INTEL_OUTPUT_ANALOG
:
4436 return POWER_DOMAIN_PORT_CRT
;
4437 case INTEL_OUTPUT_DSI
:
4438 return POWER_DOMAIN_PORT_DSI
;
4440 return POWER_DOMAIN_PORT_OTHER
;
4444 static unsigned long get_crtc_power_domains(struct drm_crtc
*crtc
)
4446 struct drm_device
*dev
= crtc
->dev
;
4447 struct intel_encoder
*intel_encoder
;
4448 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4449 enum pipe pipe
= intel_crtc
->pipe
;
4451 enum transcoder transcoder
;
4453 transcoder
= intel_pipe_to_cpu_transcoder(dev
->dev_private
, pipe
);
4455 mask
= BIT(POWER_DOMAIN_PIPE(pipe
));
4456 mask
|= BIT(POWER_DOMAIN_TRANSCODER(transcoder
));
4457 if (intel_crtc
->config
.pch_pfit
.enabled
||
4458 intel_crtc
->config
.pch_pfit
.force_thru
)
4459 mask
|= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe
));
4461 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
4462 mask
|= BIT(intel_display_port_power_domain(intel_encoder
));
4467 void intel_display_set_init_power(struct drm_i915_private
*dev_priv
,
4470 if (dev_priv
->power_domains
.init_power_on
== enable
)
4474 intel_display_power_get(dev_priv
, POWER_DOMAIN_INIT
);
4476 intel_display_power_put(dev_priv
, POWER_DOMAIN_INIT
);
4478 dev_priv
->power_domains
.init_power_on
= enable
;
4481 static void modeset_update_crtc_power_domains(struct drm_device
*dev
)
4483 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4484 unsigned long pipe_domains
[I915_MAX_PIPES
] = { 0, };
4485 struct intel_crtc
*crtc
;
4488 * First get all needed power domains, then put all unneeded, to avoid
4489 * any unnecessary toggling of the power wells.
4491 for_each_intel_crtc(dev
, crtc
) {
4492 enum intel_display_power_domain domain
;
4494 if (!crtc
->base
.enabled
)
4497 pipe_domains
[crtc
->pipe
] = get_crtc_power_domains(&crtc
->base
);
4499 for_each_power_domain(domain
, pipe_domains
[crtc
->pipe
])
4500 intel_display_power_get(dev_priv
, domain
);
4503 for_each_intel_crtc(dev
, crtc
) {
4504 enum intel_display_power_domain domain
;
4506 for_each_power_domain(domain
, crtc
->enabled_power_domains
)
4507 intel_display_power_put(dev_priv
, domain
);
4509 crtc
->enabled_power_domains
= pipe_domains
[crtc
->pipe
];
4512 intel_display_set_init_power(dev_priv
, false);
4515 /* returns HPLL frequency in kHz */
4516 static int valleyview_get_vco(struct drm_i915_private
*dev_priv
)
4518 int hpll_freq
, vco_freq
[] = { 800, 1600, 2000, 2400 };
4520 /* Obtain SKU information */
4521 mutex_lock(&dev_priv
->dpio_lock
);
4522 hpll_freq
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
) &
4523 CCK_FUSE_HPLL_FREQ_MASK
;
4524 mutex_unlock(&dev_priv
->dpio_lock
);
4526 return vco_freq
[hpll_freq
] * 1000;
4529 static void vlv_update_cdclk(struct drm_device
*dev
)
4531 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4533 dev_priv
->vlv_cdclk_freq
= dev_priv
->display
.get_display_clock_speed(dev
);
4534 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz",
4535 dev_priv
->vlv_cdclk_freq
);
4538 * Program the gmbus_freq based on the cdclk frequency.
4539 * BSpec erroneously claims we should aim for 4MHz, but
4540 * in fact 1MHz is the correct frequency.
4542 I915_WRITE(GMBUSFREQ_VLV
, dev_priv
->vlv_cdclk_freq
);
4545 /* Adjust CDclk dividers to allow high res or save power if possible */
4546 static void valleyview_set_cdclk(struct drm_device
*dev
, int cdclk
)
4548 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4551 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
) != dev_priv
->vlv_cdclk_freq
);
4553 if (cdclk
>= 320000) /* jump to highest voltage for 400MHz too */
4555 else if (cdclk
== 266667)
4560 mutex_lock(&dev_priv
->rps
.hw_lock
);
4561 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
4562 val
&= ~DSPFREQGUAR_MASK
;
4563 val
|= (cmd
<< DSPFREQGUAR_SHIFT
);
4564 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
4565 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
4566 DSPFREQSTAT_MASK
) == (cmd
<< DSPFREQSTAT_SHIFT
),
4568 DRM_ERROR("timed out waiting for CDclk change\n");
4570 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4572 if (cdclk
== 400000) {
4575 vco
= valleyview_get_vco(dev_priv
);
4576 divider
= DIV_ROUND_CLOSEST(vco
<< 1, cdclk
) - 1;
4578 mutex_lock(&dev_priv
->dpio_lock
);
4579 /* adjust cdclk divider */
4580 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
4581 val
&= ~DISPLAY_FREQUENCY_VALUES
;
4583 vlv_cck_write(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
, val
);
4585 if (wait_for((vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
) &
4586 DISPLAY_FREQUENCY_STATUS
) == (divider
<< DISPLAY_FREQUENCY_STATUS_SHIFT
),
4588 DRM_ERROR("timed out waiting for CDclk change\n");
4589 mutex_unlock(&dev_priv
->dpio_lock
);
4592 mutex_lock(&dev_priv
->dpio_lock
);
4593 /* adjust self-refresh exit latency value */
4594 val
= vlv_bunit_read(dev_priv
, BUNIT_REG_BISOC
);
4598 * For high bandwidth configs, we set a higher latency in the bunit
4599 * so that the core display fetch happens in time to avoid underruns.
4601 if (cdclk
== 400000)
4602 val
|= 4500 / 250; /* 4.5 usec */
4604 val
|= 3000 / 250; /* 3.0 usec */
4605 vlv_bunit_write(dev_priv
, BUNIT_REG_BISOC
, val
);
4606 mutex_unlock(&dev_priv
->dpio_lock
);
4608 vlv_update_cdclk(dev
);
4611 static void cherryview_set_cdclk(struct drm_device
*dev
, int cdclk
)
4613 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4616 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
) != dev_priv
->vlv_cdclk_freq
);
4637 mutex_lock(&dev_priv
->rps
.hw_lock
);
4638 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
4639 val
&= ~DSPFREQGUAR_MASK_CHV
;
4640 val
|= (cmd
<< DSPFREQGUAR_SHIFT_CHV
);
4641 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
4642 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
4643 DSPFREQSTAT_MASK_CHV
) == (cmd
<< DSPFREQSTAT_SHIFT_CHV
),
4645 DRM_ERROR("timed out waiting for CDclk change\n");
4647 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4649 vlv_update_cdclk(dev
);
4652 static int valleyview_calc_cdclk(struct drm_i915_private
*dev_priv
,
4655 int vco
= valleyview_get_vco(dev_priv
);
4656 int freq_320
= (vco
<< 1) % 320000 != 0 ? 333333 : 320000;
4658 /* FIXME: Punit isn't quite ready yet */
4659 if (IS_CHERRYVIEW(dev_priv
->dev
))
4663 * Really only a few cases to deal with, as only 4 CDclks are supported:
4666 * 320/333MHz (depends on HPLL freq)
4668 * So we check to see whether we're above 90% of the lower bin and
4671 * We seem to get an unstable or solid color picture at 200MHz.
4672 * Not sure what's wrong. For now use 200MHz only when all pipes
4675 if (max_pixclk
> freq_320
*9/10)
4677 else if (max_pixclk
> 266667*9/10)
4679 else if (max_pixclk
> 0)
4685 /* compute the max pixel clock for new configuration */
4686 static int intel_mode_max_pixclk(struct drm_i915_private
*dev_priv
)
4688 struct drm_device
*dev
= dev_priv
->dev
;
4689 struct intel_crtc
*intel_crtc
;
4692 for_each_intel_crtc(dev
, intel_crtc
) {
4693 if (intel_crtc
->new_enabled
)
4694 max_pixclk
= max(max_pixclk
,
4695 intel_crtc
->new_config
->adjusted_mode
.crtc_clock
);
4701 static void valleyview_modeset_global_pipes(struct drm_device
*dev
,
4702 unsigned *prepare_pipes
)
4704 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4705 struct intel_crtc
*intel_crtc
;
4706 int max_pixclk
= intel_mode_max_pixclk(dev_priv
);
4708 if (valleyview_calc_cdclk(dev_priv
, max_pixclk
) ==
4709 dev_priv
->vlv_cdclk_freq
)
4712 /* disable/enable all currently active pipes while we change cdclk */
4713 for_each_intel_crtc(dev
, intel_crtc
)
4714 if (intel_crtc
->base
.enabled
)
4715 *prepare_pipes
|= (1 << intel_crtc
->pipe
);
4718 static void valleyview_modeset_global_resources(struct drm_device
*dev
)
4720 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4721 int max_pixclk
= intel_mode_max_pixclk(dev_priv
);
4722 int req_cdclk
= valleyview_calc_cdclk(dev_priv
, max_pixclk
);
4724 if (req_cdclk
!= dev_priv
->vlv_cdclk_freq
) {
4725 if (IS_CHERRYVIEW(dev
))
4726 cherryview_set_cdclk(dev
, req_cdclk
);
4728 valleyview_set_cdclk(dev
, req_cdclk
);
4731 modeset_update_crtc_power_domains(dev
);
4734 static void valleyview_crtc_enable(struct drm_crtc
*crtc
)
4736 struct drm_device
*dev
= crtc
->dev
;
4737 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4738 struct intel_encoder
*encoder
;
4739 int pipe
= intel_crtc
->pipe
;
4742 WARN_ON(!crtc
->enabled
);
4744 if (intel_crtc
->active
)
4747 is_dsi
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
);
4750 if (IS_CHERRYVIEW(dev
))
4751 chv_prepare_pll(intel_crtc
);
4753 vlv_prepare_pll(intel_crtc
);
4756 if (intel_crtc
->config
.has_dp_encoder
)
4757 intel_dp_set_m_n(intel_crtc
);
4759 intel_set_pipe_timings(intel_crtc
);
4761 i9xx_set_pipeconf(intel_crtc
);
4763 intel_crtc
->active
= true;
4765 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
4767 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4768 if (encoder
->pre_pll_enable
)
4769 encoder
->pre_pll_enable(encoder
);
4772 if (IS_CHERRYVIEW(dev
))
4773 chv_enable_pll(intel_crtc
);
4775 vlv_enable_pll(intel_crtc
);
4778 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4779 if (encoder
->pre_enable
)
4780 encoder
->pre_enable(encoder
);
4782 i9xx_pfit_enable(intel_crtc
);
4784 intel_crtc_load_lut(crtc
);
4786 intel_update_watermarks(crtc
);
4787 intel_enable_pipe(intel_crtc
);
4789 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4790 encoder
->enable(encoder
);
4792 intel_crtc_enable_planes(crtc
);
4794 /* Underruns don't raise interrupts, so check manually. */
4795 i9xx_check_fifo_underruns(dev
);
4798 static void i9xx_set_pll_dividers(struct intel_crtc
*crtc
)
4800 struct drm_device
*dev
= crtc
->base
.dev
;
4801 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4803 I915_WRITE(FP0(crtc
->pipe
), crtc
->config
.dpll_hw_state
.fp0
);
4804 I915_WRITE(FP1(crtc
->pipe
), crtc
->config
.dpll_hw_state
.fp1
);
4807 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
4809 struct drm_device
*dev
= crtc
->dev
;
4810 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4811 struct intel_encoder
*encoder
;
4812 int pipe
= intel_crtc
->pipe
;
4814 WARN_ON(!crtc
->enabled
);
4816 if (intel_crtc
->active
)
4819 i9xx_set_pll_dividers(intel_crtc
);
4821 if (intel_crtc
->config
.has_dp_encoder
)
4822 intel_dp_set_m_n(intel_crtc
);
4824 intel_set_pipe_timings(intel_crtc
);
4826 i9xx_set_pipeconf(intel_crtc
);
4828 intel_crtc
->active
= true;
4831 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
4833 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4834 if (encoder
->pre_enable
)
4835 encoder
->pre_enable(encoder
);
4837 i9xx_enable_pll(intel_crtc
);
4839 i9xx_pfit_enable(intel_crtc
);
4841 intel_crtc_load_lut(crtc
);
4843 intel_update_watermarks(crtc
);
4844 intel_enable_pipe(intel_crtc
);
4846 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4847 encoder
->enable(encoder
);
4849 intel_crtc_enable_planes(crtc
);
4852 * Gen2 reports pipe underruns whenever all planes are disabled.
4853 * So don't enable underrun reporting before at least some planes
4855 * FIXME: Need to fix the logic to work when we turn off all planes
4856 * but leave the pipe running.
4859 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
4861 /* Underruns don't raise interrupts, so check manually. */
4862 i9xx_check_fifo_underruns(dev
);
4865 static void i9xx_pfit_disable(struct intel_crtc
*crtc
)
4867 struct drm_device
*dev
= crtc
->base
.dev
;
4868 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4870 if (!crtc
->config
.gmch_pfit
.control
)
4873 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
4875 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4876 I915_READ(PFIT_CONTROL
));
4877 I915_WRITE(PFIT_CONTROL
, 0);
4880 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
4882 struct drm_device
*dev
= crtc
->dev
;
4883 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4884 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4885 struct intel_encoder
*encoder
;
4886 int pipe
= intel_crtc
->pipe
;
4888 if (!intel_crtc
->active
)
4892 * Gen2 reports pipe underruns whenever all planes are disabled.
4893 * So diasble underrun reporting before all the planes get disabled.
4894 * FIXME: Need to fix the logic to work when we turn off all planes
4895 * but leave the pipe running.
4898 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, false);
4901 * Vblank time updates from the shadow to live plane control register
4902 * are blocked if the memory self-refresh mode is active at that
4903 * moment. So to make sure the plane gets truly disabled, disable
4904 * first the self-refresh mode. The self-refresh enable bit in turn
4905 * will be checked/applied by the HW only at the next frame start
4906 * event which is after the vblank start event, so we need to have a
4907 * wait-for-vblank between disabling the plane and the pipe.
4909 intel_set_memory_cxsr(dev_priv
, false);
4910 intel_crtc_disable_planes(crtc
);
4912 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4913 encoder
->disable(encoder
);
4916 * On gen2 planes are double buffered but the pipe isn't, so we must
4917 * wait for planes to fully turn off before disabling the pipe.
4918 * We also need to wait on all gmch platforms because of the
4919 * self-refresh mode constraint explained above.
4921 intel_wait_for_vblank(dev
, pipe
);
4923 intel_disable_pipe(intel_crtc
);
4925 i9xx_pfit_disable(intel_crtc
);
4927 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4928 if (encoder
->post_disable
)
4929 encoder
->post_disable(encoder
);
4931 if (!intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
)) {
4932 if (IS_CHERRYVIEW(dev
))
4933 chv_disable_pll(dev_priv
, pipe
);
4934 else if (IS_VALLEYVIEW(dev
))
4935 vlv_disable_pll(dev_priv
, pipe
);
4937 i9xx_disable_pll(intel_crtc
);
4941 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, false);
4943 intel_crtc
->active
= false;
4944 intel_update_watermarks(crtc
);
4946 mutex_lock(&dev
->struct_mutex
);
4947 intel_update_fbc(dev
);
4948 mutex_unlock(&dev
->struct_mutex
);
4951 static void i9xx_crtc_off(struct drm_crtc
*crtc
)
4955 static void intel_crtc_update_sarea(struct drm_crtc
*crtc
,
4958 struct drm_device
*dev
= crtc
->dev
;
4959 struct drm_i915_master_private
*master_priv
;
4960 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4961 int pipe
= intel_crtc
->pipe
;
4963 if (!dev
->primary
->master
)
4966 master_priv
= dev
->primary
->master
->driver_priv
;
4967 if (!master_priv
->sarea_priv
)
4972 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
4973 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
4976 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
4977 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
4980 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe
));
4985 /* Master function to enable/disable CRTC and corresponding power wells */
4986 void intel_crtc_control(struct drm_crtc
*crtc
, bool enable
)
4988 struct drm_device
*dev
= crtc
->dev
;
4989 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4990 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4991 enum intel_display_power_domain domain
;
4992 unsigned long domains
;
4995 if (!intel_crtc
->active
) {
4996 domains
= get_crtc_power_domains(crtc
);
4997 for_each_power_domain(domain
, domains
)
4998 intel_display_power_get(dev_priv
, domain
);
4999 intel_crtc
->enabled_power_domains
= domains
;
5001 dev_priv
->display
.crtc_enable(crtc
);
5004 if (intel_crtc
->active
) {
5005 dev_priv
->display
.crtc_disable(crtc
);
5007 domains
= intel_crtc
->enabled_power_domains
;
5008 for_each_power_domain(domain
, domains
)
5009 intel_display_power_put(dev_priv
, domain
);
5010 intel_crtc
->enabled_power_domains
= 0;
5016 * Sets the power management mode of the pipe and plane.
5018 void intel_crtc_update_dpms(struct drm_crtc
*crtc
)
5020 struct drm_device
*dev
= crtc
->dev
;
5021 struct intel_encoder
*intel_encoder
;
5022 bool enable
= false;
5024 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
5025 enable
|= intel_encoder
->connectors_active
;
5027 intel_crtc_control(crtc
, enable
);
5029 intel_crtc_update_sarea(crtc
, enable
);
5032 static void intel_crtc_disable(struct drm_crtc
*crtc
)
5034 struct drm_device
*dev
= crtc
->dev
;
5035 struct drm_connector
*connector
;
5036 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5037 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(crtc
->primary
->fb
);
5038 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
5040 /* crtc should still be enabled when we disable it. */
5041 WARN_ON(!crtc
->enabled
);
5043 dev_priv
->display
.crtc_disable(crtc
);
5044 intel_crtc_update_sarea(crtc
, false);
5045 dev_priv
->display
.off(crtc
);
5047 if (crtc
->primary
->fb
) {
5048 mutex_lock(&dev
->struct_mutex
);
5049 intel_unpin_fb_obj(old_obj
);
5050 i915_gem_track_fb(old_obj
, NULL
,
5051 INTEL_FRONTBUFFER_PRIMARY(pipe
));
5052 mutex_unlock(&dev
->struct_mutex
);
5053 crtc
->primary
->fb
= NULL
;
5056 /* Update computed state. */
5057 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
5058 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
5061 if (connector
->encoder
->crtc
!= crtc
)
5064 connector
->dpms
= DRM_MODE_DPMS_OFF
;
5065 to_intel_encoder(connector
->encoder
)->connectors_active
= false;
5069 void intel_encoder_destroy(struct drm_encoder
*encoder
)
5071 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
5073 drm_encoder_cleanup(encoder
);
5074 kfree(intel_encoder
);
5077 /* Simple dpms helper for encoders with just one connector, no cloning and only
5078 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5079 * state of the entire output pipe. */
5080 static void intel_encoder_dpms(struct intel_encoder
*encoder
, int mode
)
5082 if (mode
== DRM_MODE_DPMS_ON
) {
5083 encoder
->connectors_active
= true;
5085 intel_crtc_update_dpms(encoder
->base
.crtc
);
5087 encoder
->connectors_active
= false;
5089 intel_crtc_update_dpms(encoder
->base
.crtc
);
5093 /* Cross check the actual hw state with our own modeset state tracking (and it's
5094 * internal consistency). */
5095 static void intel_connector_check_state(struct intel_connector
*connector
)
5097 if (connector
->get_hw_state(connector
)) {
5098 struct intel_encoder
*encoder
= connector
->encoder
;
5099 struct drm_crtc
*crtc
;
5100 bool encoder_enabled
;
5103 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5104 connector
->base
.base
.id
,
5105 connector
->base
.name
);
5107 /* there is no real hw state for MST connectors */
5108 if (connector
->mst_port
)
5111 WARN(connector
->base
.dpms
== DRM_MODE_DPMS_OFF
,
5112 "wrong connector dpms state\n");
5113 WARN(connector
->base
.encoder
!= &encoder
->base
,
5114 "active connector not linked to encoder\n");
5117 WARN(!encoder
->connectors_active
,
5118 "encoder->connectors_active not set\n");
5120 encoder_enabled
= encoder
->get_hw_state(encoder
, &pipe
);
5121 WARN(!encoder_enabled
, "encoder not enabled\n");
5122 if (WARN_ON(!encoder
->base
.crtc
))
5125 crtc
= encoder
->base
.crtc
;
5127 WARN(!crtc
->enabled
, "crtc not enabled\n");
5128 WARN(!to_intel_crtc(crtc
)->active
, "crtc not active\n");
5129 WARN(pipe
!= to_intel_crtc(crtc
)->pipe
,
5130 "encoder active on the wrong pipe\n");
5135 /* Even simpler default implementation, if there's really no special case to
5137 void intel_connector_dpms(struct drm_connector
*connector
, int mode
)
5139 /* All the simple cases only support two dpms states. */
5140 if (mode
!= DRM_MODE_DPMS_ON
)
5141 mode
= DRM_MODE_DPMS_OFF
;
5143 if (mode
== connector
->dpms
)
5146 connector
->dpms
= mode
;
5148 /* Only need to change hw state when actually enabled */
5149 if (connector
->encoder
)
5150 intel_encoder_dpms(to_intel_encoder(connector
->encoder
), mode
);
5152 intel_modeset_check_state(connector
->dev
);
5155 /* Simple connector->get_hw_state implementation for encoders that support only
5156 * one connector and no cloning and hence the encoder state determines the state
5157 * of the connector. */
5158 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
5161 struct intel_encoder
*encoder
= connector
->encoder
;
5163 return encoder
->get_hw_state(encoder
, &pipe
);
5166 static bool ironlake_check_fdi_lanes(struct drm_device
*dev
, enum pipe pipe
,
5167 struct intel_crtc_config
*pipe_config
)
5169 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5170 struct intel_crtc
*pipe_B_crtc
=
5171 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
5173 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5174 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5175 if (pipe_config
->fdi_lanes
> 4) {
5176 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5177 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5181 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
5182 if (pipe_config
->fdi_lanes
> 2) {
5183 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5184 pipe_config
->fdi_lanes
);
5191 if (INTEL_INFO(dev
)->num_pipes
== 2)
5194 /* Ivybridge 3 pipe is really complicated */
5199 if (dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]->enabled
&&
5200 pipe_config
->fdi_lanes
> 2) {
5201 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5202 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5207 if (!pipe_has_enabled_pch(pipe_B_crtc
) ||
5208 pipe_B_crtc
->config
.fdi_lanes
<= 2) {
5209 if (pipe_config
->fdi_lanes
> 2) {
5210 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5211 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5215 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5225 static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc
,
5226 struct intel_crtc_config
*pipe_config
)
5228 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5229 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
5230 int lane
, link_bw
, fdi_dotclock
;
5231 bool setup_ok
, needs_recompute
= false;
5234 /* FDI is a binary signal running at ~2.7GHz, encoding
5235 * each output octet as 10 bits. The actual frequency
5236 * is stored as a divider into a 100MHz clock, and the
5237 * mode pixel clock is stored in units of 1KHz.
5238 * Hence the bw of each lane in terms of the mode signal
5241 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
5243 fdi_dotclock
= adjusted_mode
->crtc_clock
;
5245 lane
= ironlake_get_lanes_required(fdi_dotclock
, link_bw
,
5246 pipe_config
->pipe_bpp
);
5248 pipe_config
->fdi_lanes
= lane
;
5250 intel_link_compute_m_n(pipe_config
->pipe_bpp
, lane
, fdi_dotclock
,
5251 link_bw
, &pipe_config
->fdi_m_n
);
5253 setup_ok
= ironlake_check_fdi_lanes(intel_crtc
->base
.dev
,
5254 intel_crtc
->pipe
, pipe_config
);
5255 if (!setup_ok
&& pipe_config
->pipe_bpp
> 6*3) {
5256 pipe_config
->pipe_bpp
-= 2*3;
5257 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5258 pipe_config
->pipe_bpp
);
5259 needs_recompute
= true;
5260 pipe_config
->bw_constrained
= true;
5265 if (needs_recompute
)
5268 return setup_ok
? 0 : -EINVAL
;
5271 static void hsw_compute_ips_config(struct intel_crtc
*crtc
,
5272 struct intel_crtc_config
*pipe_config
)
5274 pipe_config
->ips_enabled
= i915
.enable_ips
&&
5275 hsw_crtc_supports_ips(crtc
) &&
5276 pipe_config
->pipe_bpp
<= 24;
5279 static int intel_crtc_compute_config(struct intel_crtc
*crtc
,
5280 struct intel_crtc_config
*pipe_config
)
5282 struct drm_device
*dev
= crtc
->base
.dev
;
5283 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
5285 /* FIXME should check pixel clock limits on all platforms */
5286 if (INTEL_INFO(dev
)->gen
< 4) {
5287 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5289 dev_priv
->display
.get_display_clock_speed(dev
);
5292 * Enable pixel doubling when the dot clock
5293 * is > 90% of the (display) core speed.
5295 * GDG double wide on either pipe,
5296 * otherwise pipe A only.
5298 if ((crtc
->pipe
== PIPE_A
|| IS_I915G(dev
)) &&
5299 adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10) {
5301 pipe_config
->double_wide
= true;
5304 if (adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10)
5309 * Pipe horizontal size must be even in:
5311 * - LVDS dual channel mode
5312 * - Double wide pipe
5314 if ((intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
5315 intel_is_dual_link_lvds(dev
)) || pipe_config
->double_wide
)
5316 pipe_config
->pipe_src_w
&= ~1;
5318 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5319 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5321 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
5322 adjusted_mode
->hsync_start
== adjusted_mode
->hdisplay
)
5325 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) && pipe_config
->pipe_bpp
> 10*3) {
5326 pipe_config
->pipe_bpp
= 10*3; /* 12bpc is gen5+ */
5327 } else if (INTEL_INFO(dev
)->gen
<= 4 && pipe_config
->pipe_bpp
> 8*3) {
5328 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5330 pipe_config
->pipe_bpp
= 8*3;
5334 hsw_compute_ips_config(crtc
, pipe_config
);
5337 * XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the
5338 * old clock survives for now.
5340 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
) || HAS_DDI(dev
))
5341 pipe_config
->shared_dpll
= crtc
->config
.shared_dpll
;
5343 if (pipe_config
->has_pch_encoder
)
5344 return ironlake_fdi_compute_config(crtc
, pipe_config
);
5349 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
5351 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5352 int vco
= valleyview_get_vco(dev_priv
);
5356 /* FIXME: Punit isn't quite ready yet */
5357 if (IS_CHERRYVIEW(dev
))
5360 mutex_lock(&dev_priv
->dpio_lock
);
5361 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
5362 mutex_unlock(&dev_priv
->dpio_lock
);
5364 divider
= val
& DISPLAY_FREQUENCY_VALUES
;
5366 WARN((val
& DISPLAY_FREQUENCY_STATUS
) !=
5367 (divider
<< DISPLAY_FREQUENCY_STATUS_SHIFT
),
5368 "cdclk change in progress\n");
5370 return DIV_ROUND_CLOSEST(vco
<< 1, divider
+ 1);
5373 static int i945_get_display_clock_speed(struct drm_device
*dev
)
5378 static int i915_get_display_clock_speed(struct drm_device
*dev
)
5383 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
5388 static int pnv_get_display_clock_speed(struct drm_device
*dev
)
5392 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
5394 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
5395 case GC_DISPLAY_CLOCK_267_MHZ_PNV
:
5397 case GC_DISPLAY_CLOCK_333_MHZ_PNV
:
5399 case GC_DISPLAY_CLOCK_444_MHZ_PNV
:
5401 case GC_DISPLAY_CLOCK_200_MHZ_PNV
:
5404 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc
);
5405 case GC_DISPLAY_CLOCK_133_MHZ_PNV
:
5407 case GC_DISPLAY_CLOCK_167_MHZ_PNV
:
5412 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
5416 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
5418 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
5421 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
5422 case GC_DISPLAY_CLOCK_333_MHZ
:
5425 case GC_DISPLAY_CLOCK_190_200_MHZ
:
5431 static int i865_get_display_clock_speed(struct drm_device
*dev
)
5436 static int i855_get_display_clock_speed(struct drm_device
*dev
)
5439 /* Assume that the hardware is in the high speed state. This
5440 * should be the default.
5442 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
5443 case GC_CLOCK_133_200
:
5444 case GC_CLOCK_100_200
:
5446 case GC_CLOCK_166_250
:
5448 case GC_CLOCK_100_133
:
5452 /* Shouldn't happen */
5456 static int i830_get_display_clock_speed(struct drm_device
*dev
)
5462 intel_reduce_m_n_ratio(uint32_t *num
, uint32_t *den
)
5464 while (*num
> DATA_LINK_M_N_MASK
||
5465 *den
> DATA_LINK_M_N_MASK
) {
5471 static void compute_m_n(unsigned int m
, unsigned int n
,
5472 uint32_t *ret_m
, uint32_t *ret_n
)
5474 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
5475 *ret_m
= div_u64((uint64_t) m
* *ret_n
, n
);
5476 intel_reduce_m_n_ratio(ret_m
, ret_n
);
5480 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
5481 int pixel_clock
, int link_clock
,
5482 struct intel_link_m_n
*m_n
)
5486 compute_m_n(bits_per_pixel
* pixel_clock
,
5487 link_clock
* nlanes
* 8,
5488 &m_n
->gmch_m
, &m_n
->gmch_n
);
5490 compute_m_n(pixel_clock
, link_clock
,
5491 &m_n
->link_m
, &m_n
->link_n
);
5494 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
5496 if (i915
.panel_use_ssc
>= 0)
5497 return i915
.panel_use_ssc
!= 0;
5498 return dev_priv
->vbt
.lvds_use_ssc
5499 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
5502 static int i9xx_get_refclk(struct drm_crtc
*crtc
, int num_connectors
)
5504 struct drm_device
*dev
= crtc
->dev
;
5505 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5508 if (IS_VALLEYVIEW(dev
)) {
5510 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
5511 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
5512 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
5513 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
5514 } else if (!IS_GEN2(dev
)) {
5523 static uint32_t pnv_dpll_compute_fp(struct dpll
*dpll
)
5525 return (1 << dpll
->n
) << 16 | dpll
->m2
;
5528 static uint32_t i9xx_dpll_compute_fp(struct dpll
*dpll
)
5530 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
5533 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
5534 intel_clock_t
*reduced_clock
)
5536 struct drm_device
*dev
= crtc
->base
.dev
;
5539 if (IS_PINEVIEW(dev
)) {
5540 fp
= pnv_dpll_compute_fp(&crtc
->config
.dpll
);
5542 fp2
= pnv_dpll_compute_fp(reduced_clock
);
5544 fp
= i9xx_dpll_compute_fp(&crtc
->config
.dpll
);
5546 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
5549 crtc
->config
.dpll_hw_state
.fp0
= fp
;
5551 crtc
->lowfreq_avail
= false;
5552 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
5553 reduced_clock
&& i915
.powersave
) {
5554 crtc
->config
.dpll_hw_state
.fp1
= fp2
;
5555 crtc
->lowfreq_avail
= true;
5557 crtc
->config
.dpll_hw_state
.fp1
= fp
;
5561 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
, enum pipe
5567 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5568 * and set it to a reasonable value instead.
5570 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
5571 reg_val
&= 0xffffff00;
5572 reg_val
|= 0x00000030;
5573 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
5575 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
5576 reg_val
&= 0x8cffffff;
5577 reg_val
= 0x8c000000;
5578 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
5580 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
5581 reg_val
&= 0xffffff00;
5582 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
5584 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
5585 reg_val
&= 0x00ffffff;
5586 reg_val
|= 0xb0000000;
5587 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
5590 static void intel_pch_transcoder_set_m_n(struct intel_crtc
*crtc
,
5591 struct intel_link_m_n
*m_n
)
5593 struct drm_device
*dev
= crtc
->base
.dev
;
5594 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5595 int pipe
= crtc
->pipe
;
5597 I915_WRITE(PCH_TRANS_DATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5598 I915_WRITE(PCH_TRANS_DATA_N1(pipe
), m_n
->gmch_n
);
5599 I915_WRITE(PCH_TRANS_LINK_M1(pipe
), m_n
->link_m
);
5600 I915_WRITE(PCH_TRANS_LINK_N1(pipe
), m_n
->link_n
);
5603 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
5604 struct intel_link_m_n
*m_n
,
5605 struct intel_link_m_n
*m2_n2
)
5607 struct drm_device
*dev
= crtc
->base
.dev
;
5608 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5609 int pipe
= crtc
->pipe
;
5610 enum transcoder transcoder
= crtc
->config
.cpu_transcoder
;
5612 if (INTEL_INFO(dev
)->gen
>= 5) {
5613 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5614 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
5615 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
5616 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
5617 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5618 * for gen < 8) and if DRRS is supported (to make sure the
5619 * registers are not unnecessarily accessed).
5621 if (m2_n2
&& INTEL_INFO(dev
)->gen
< 8 &&
5622 crtc
->config
.has_drrs
) {
5623 I915_WRITE(PIPE_DATA_M2(transcoder
),
5624 TU_SIZE(m2_n2
->tu
) | m2_n2
->gmch_m
);
5625 I915_WRITE(PIPE_DATA_N2(transcoder
), m2_n2
->gmch_n
);
5626 I915_WRITE(PIPE_LINK_M2(transcoder
), m2_n2
->link_m
);
5627 I915_WRITE(PIPE_LINK_N2(transcoder
), m2_n2
->link_n
);
5630 I915_WRITE(PIPE_DATA_M_G4X(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5631 I915_WRITE(PIPE_DATA_N_G4X(pipe
), m_n
->gmch_n
);
5632 I915_WRITE(PIPE_LINK_M_G4X(pipe
), m_n
->link_m
);
5633 I915_WRITE(PIPE_LINK_N_G4X(pipe
), m_n
->link_n
);
5637 void intel_dp_set_m_n(struct intel_crtc
*crtc
)
5639 if (crtc
->config
.has_pch_encoder
)
5640 intel_pch_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
);
5642 intel_cpu_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
,
5643 &crtc
->config
.dp_m2_n2
);
5646 static void vlv_update_pll(struct intel_crtc
*crtc
)
5651 * Enable DPIO clock input. We should never disable the reference
5652 * clock for pipe B, since VGA hotplug / manual detection depends
5655 dpll
= DPLL_EXT_BUFFER_ENABLE_VLV
| DPLL_REFA_CLK_ENABLE_VLV
|
5656 DPLL_VGA_MODE_DIS
| DPLL_INTEGRATED_CLOCK_VLV
;
5657 /* We should never disable this, set it here for state tracking */
5658 if (crtc
->pipe
== PIPE_B
)
5659 dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
5660 dpll
|= DPLL_VCO_ENABLE
;
5661 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
5663 dpll_md
= (crtc
->config
.pixel_multiplier
- 1)
5664 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
5665 crtc
->config
.dpll_hw_state
.dpll_md
= dpll_md
;
5668 static void vlv_prepare_pll(struct intel_crtc
*crtc
)
5670 struct drm_device
*dev
= crtc
->base
.dev
;
5671 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5672 int pipe
= crtc
->pipe
;
5674 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
5675 u32 coreclk
, reg_val
;
5677 mutex_lock(&dev_priv
->dpio_lock
);
5679 bestn
= crtc
->config
.dpll
.n
;
5680 bestm1
= crtc
->config
.dpll
.m1
;
5681 bestm2
= crtc
->config
.dpll
.m2
;
5682 bestp1
= crtc
->config
.dpll
.p1
;
5683 bestp2
= crtc
->config
.dpll
.p2
;
5685 /* See eDP HDMI DPIO driver vbios notes doc */
5687 /* PLL B needs special handling */
5689 vlv_pllb_recal_opamp(dev_priv
, pipe
);
5691 /* Set up Tx target for periodic Rcomp update */
5692 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9_BCAST
, 0x0100000f);
5694 /* Disable target IRef on PLL */
5695 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW8(pipe
));
5696 reg_val
&= 0x00ffffff;
5697 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW8(pipe
), reg_val
);
5699 /* Disable fast lock */
5700 vlv_dpio_write(dev_priv
, pipe
, VLV_CMN_DW0
, 0x610);
5702 /* Set idtafcrecal before PLL is enabled */
5703 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
5704 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
5705 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
5706 mdiv
|= (1 << DPIO_K_SHIFT
);
5709 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5710 * but we don't support that).
5711 * Note: don't use the DAC post divider as it seems unstable.
5713 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
5714 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
5716 mdiv
|= DPIO_ENABLE_CALIBRATION
;
5717 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
5719 /* Set HBR and RBR LPF coefficients */
5720 if (crtc
->config
.port_clock
== 162000 ||
5721 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_ANALOG
) ||
5722 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
))
5723 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
5726 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
5729 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
) ||
5730 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
)) {
5731 /* Use SSC source */
5733 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5736 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5738 } else { /* HDMI or VGA */
5739 /* Use bend source */
5741 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5744 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5748 coreclk
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW7(pipe
));
5749 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
5750 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
) ||
5751 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
))
5752 coreclk
|= 0x01000000;
5753 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW7(pipe
), coreclk
);
5755 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW11(pipe
), 0x87871000);
5756 mutex_unlock(&dev_priv
->dpio_lock
);
5759 static void chv_update_pll(struct intel_crtc
*crtc
)
5761 crtc
->config
.dpll_hw_state
.dpll
= DPLL_SSC_REF_CLOCK_CHV
|
5762 DPLL_REFA_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
|
5764 if (crtc
->pipe
!= PIPE_A
)
5765 crtc
->config
.dpll_hw_state
.dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
5767 crtc
->config
.dpll_hw_state
.dpll_md
=
5768 (crtc
->config
.pixel_multiplier
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
5771 static void chv_prepare_pll(struct intel_crtc
*crtc
)
5773 struct drm_device
*dev
= crtc
->base
.dev
;
5774 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5775 int pipe
= crtc
->pipe
;
5776 int dpll_reg
= DPLL(crtc
->pipe
);
5777 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
5778 u32 loopfilter
, intcoeff
;
5779 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
, bestm2_frac
;
5782 bestn
= crtc
->config
.dpll
.n
;
5783 bestm2_frac
= crtc
->config
.dpll
.m2
& 0x3fffff;
5784 bestm1
= crtc
->config
.dpll
.m1
;
5785 bestm2
= crtc
->config
.dpll
.m2
>> 22;
5786 bestp1
= crtc
->config
.dpll
.p1
;
5787 bestp2
= crtc
->config
.dpll
.p2
;
5790 * Enable Refclk and SSC
5792 I915_WRITE(dpll_reg
,
5793 crtc
->config
.dpll_hw_state
.dpll
& ~DPLL_VCO_ENABLE
);
5795 mutex_lock(&dev_priv
->dpio_lock
);
5797 /* p1 and p2 divider */
5798 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW13(port
),
5799 5 << DPIO_CHV_S1_DIV_SHIFT
|
5800 bestp1
<< DPIO_CHV_P1_DIV_SHIFT
|
5801 bestp2
<< DPIO_CHV_P2_DIV_SHIFT
|
5802 1 << DPIO_CHV_K_DIV_SHIFT
);
5804 /* Feedback post-divider - m2 */
5805 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW0(port
), bestm2
);
5807 /* Feedback refclk divider - n and m1 */
5808 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW1(port
),
5809 DPIO_CHV_M1_DIV_BY_2
|
5810 1 << DPIO_CHV_N_DIV_SHIFT
);
5812 /* M2 fraction division */
5813 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW2(port
), bestm2_frac
);
5815 /* M2 fraction division enable */
5816 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW3(port
),
5817 DPIO_CHV_FRAC_DIV_EN
|
5818 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT
));
5821 refclk
= i9xx_get_refclk(&crtc
->base
, 0);
5822 loopfilter
= 5 << DPIO_CHV_PROP_COEFF_SHIFT
|
5823 2 << DPIO_CHV_GAIN_CTRL_SHIFT
;
5824 if (refclk
== 100000)
5826 else if (refclk
== 38400)
5830 loopfilter
|= intcoeff
<< DPIO_CHV_INT_COEFF_SHIFT
;
5831 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW6(port
), loopfilter
);
5834 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
),
5835 vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
)) |
5838 mutex_unlock(&dev_priv
->dpio_lock
);
5841 static void i9xx_update_pll(struct intel_crtc
*crtc
,
5842 intel_clock_t
*reduced_clock
,
5845 struct drm_device
*dev
= crtc
->base
.dev
;
5846 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5849 struct dpll
*clock
= &crtc
->config
.dpll
;
5851 i9xx_update_pll_dividers(crtc
, reduced_clock
);
5853 is_sdvo
= intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_SDVO
) ||
5854 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
);
5856 dpll
= DPLL_VGA_MODE_DIS
;
5858 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
))
5859 dpll
|= DPLLB_MODE_LVDS
;
5861 dpll
|= DPLLB_MODE_DAC_SERIAL
;
5863 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
5864 dpll
|= (crtc
->config
.pixel_multiplier
- 1)
5865 << SDVO_MULTIPLIER_SHIFT_HIRES
;
5869 dpll
|= DPLL_SDVO_HIGH_SPEED
;
5871 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
))
5872 dpll
|= DPLL_SDVO_HIGH_SPEED
;
5874 /* compute bitmask from p1 value */
5875 if (IS_PINEVIEW(dev
))
5876 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
5878 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5879 if (IS_G4X(dev
) && reduced_clock
)
5880 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
5882 switch (clock
->p2
) {
5884 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
5887 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
5890 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
5893 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
5896 if (INTEL_INFO(dev
)->gen
>= 4)
5897 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
5899 if (crtc
->config
.sdvo_tv_clock
)
5900 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
5901 else if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
5902 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
5903 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
5905 dpll
|= PLL_REF_INPUT_DREFCLK
;
5907 dpll
|= DPLL_VCO_ENABLE
;
5908 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
5910 if (INTEL_INFO(dev
)->gen
>= 4) {
5911 u32 dpll_md
= (crtc
->config
.pixel_multiplier
- 1)
5912 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
5913 crtc
->config
.dpll_hw_state
.dpll_md
= dpll_md
;
5917 static void i8xx_update_pll(struct intel_crtc
*crtc
,
5918 intel_clock_t
*reduced_clock
,
5921 struct drm_device
*dev
= crtc
->base
.dev
;
5922 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5924 struct dpll
*clock
= &crtc
->config
.dpll
;
5926 i9xx_update_pll_dividers(crtc
, reduced_clock
);
5928 dpll
= DPLL_VGA_MODE_DIS
;
5930 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
)) {
5931 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5934 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
5936 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5938 dpll
|= PLL_P2_DIVIDE_BY_4
;
5941 if (!IS_I830(dev
) && intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DVO
))
5942 dpll
|= DPLL_DVO_2X_MODE
;
5944 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
5945 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
5946 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
5948 dpll
|= PLL_REF_INPUT_DREFCLK
;
5950 dpll
|= DPLL_VCO_ENABLE
;
5951 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
5954 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
)
5956 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5957 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5958 enum pipe pipe
= intel_crtc
->pipe
;
5959 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
5960 struct drm_display_mode
*adjusted_mode
=
5961 &intel_crtc
->config
.adjusted_mode
;
5962 uint32_t crtc_vtotal
, crtc_vblank_end
;
5965 /* We need to be careful not to changed the adjusted mode, for otherwise
5966 * the hw state checker will get angry at the mismatch. */
5967 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
5968 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
5970 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
5971 /* the chip adds 2 halflines automatically */
5973 crtc_vblank_end
-= 1;
5975 if (intel_pipe_has_type(&intel_crtc
->base
, INTEL_OUTPUT_SDVO
))
5976 vsyncshift
= (adjusted_mode
->crtc_htotal
- 1) / 2;
5978 vsyncshift
= adjusted_mode
->crtc_hsync_start
-
5979 adjusted_mode
->crtc_htotal
/ 2;
5981 vsyncshift
+= adjusted_mode
->crtc_htotal
;
5984 if (INTEL_INFO(dev
)->gen
> 3)
5985 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
5987 I915_WRITE(HTOTAL(cpu_transcoder
),
5988 (adjusted_mode
->crtc_hdisplay
- 1) |
5989 ((adjusted_mode
->crtc_htotal
- 1) << 16));
5990 I915_WRITE(HBLANK(cpu_transcoder
),
5991 (adjusted_mode
->crtc_hblank_start
- 1) |
5992 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
5993 I915_WRITE(HSYNC(cpu_transcoder
),
5994 (adjusted_mode
->crtc_hsync_start
- 1) |
5995 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
5997 I915_WRITE(VTOTAL(cpu_transcoder
),
5998 (adjusted_mode
->crtc_vdisplay
- 1) |
5999 ((crtc_vtotal
- 1) << 16));
6000 I915_WRITE(VBLANK(cpu_transcoder
),
6001 (adjusted_mode
->crtc_vblank_start
- 1) |
6002 ((crtc_vblank_end
- 1) << 16));
6003 I915_WRITE(VSYNC(cpu_transcoder
),
6004 (adjusted_mode
->crtc_vsync_start
- 1) |
6005 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
6007 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6008 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6009 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6011 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
6012 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
6013 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
6015 /* pipesrc controls the size that is scaled from, which should
6016 * always be the user's requested size.
6018 I915_WRITE(PIPESRC(pipe
),
6019 ((intel_crtc
->config
.pipe_src_w
- 1) << 16) |
6020 (intel_crtc
->config
.pipe_src_h
- 1));
6023 static void intel_get_pipe_timings(struct intel_crtc
*crtc
,
6024 struct intel_crtc_config
*pipe_config
)
6026 struct drm_device
*dev
= crtc
->base
.dev
;
6027 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6028 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
6031 tmp
= I915_READ(HTOTAL(cpu_transcoder
));
6032 pipe_config
->adjusted_mode
.crtc_hdisplay
= (tmp
& 0xffff) + 1;
6033 pipe_config
->adjusted_mode
.crtc_htotal
= ((tmp
>> 16) & 0xffff) + 1;
6034 tmp
= I915_READ(HBLANK(cpu_transcoder
));
6035 pipe_config
->adjusted_mode
.crtc_hblank_start
= (tmp
& 0xffff) + 1;
6036 pipe_config
->adjusted_mode
.crtc_hblank_end
= ((tmp
>> 16) & 0xffff) + 1;
6037 tmp
= I915_READ(HSYNC(cpu_transcoder
));
6038 pipe_config
->adjusted_mode
.crtc_hsync_start
= (tmp
& 0xffff) + 1;
6039 pipe_config
->adjusted_mode
.crtc_hsync_end
= ((tmp
>> 16) & 0xffff) + 1;
6041 tmp
= I915_READ(VTOTAL(cpu_transcoder
));
6042 pipe_config
->adjusted_mode
.crtc_vdisplay
= (tmp
& 0xffff) + 1;
6043 pipe_config
->adjusted_mode
.crtc_vtotal
= ((tmp
>> 16) & 0xffff) + 1;
6044 tmp
= I915_READ(VBLANK(cpu_transcoder
));
6045 pipe_config
->adjusted_mode
.crtc_vblank_start
= (tmp
& 0xffff) + 1;
6046 pipe_config
->adjusted_mode
.crtc_vblank_end
= ((tmp
>> 16) & 0xffff) + 1;
6047 tmp
= I915_READ(VSYNC(cpu_transcoder
));
6048 pipe_config
->adjusted_mode
.crtc_vsync_start
= (tmp
& 0xffff) + 1;
6049 pipe_config
->adjusted_mode
.crtc_vsync_end
= ((tmp
>> 16) & 0xffff) + 1;
6051 if (I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_INTERLACE_MASK
) {
6052 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
6053 pipe_config
->adjusted_mode
.crtc_vtotal
+= 1;
6054 pipe_config
->adjusted_mode
.crtc_vblank_end
+= 1;
6057 tmp
= I915_READ(PIPESRC(crtc
->pipe
));
6058 pipe_config
->pipe_src_h
= (tmp
& 0xffff) + 1;
6059 pipe_config
->pipe_src_w
= ((tmp
>> 16) & 0xffff) + 1;
6061 pipe_config
->requested_mode
.vdisplay
= pipe_config
->pipe_src_h
;
6062 pipe_config
->requested_mode
.hdisplay
= pipe_config
->pipe_src_w
;
6065 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
6066 struct intel_crtc_config
*pipe_config
)
6068 mode
->hdisplay
= pipe_config
->adjusted_mode
.crtc_hdisplay
;
6069 mode
->htotal
= pipe_config
->adjusted_mode
.crtc_htotal
;
6070 mode
->hsync_start
= pipe_config
->adjusted_mode
.crtc_hsync_start
;
6071 mode
->hsync_end
= pipe_config
->adjusted_mode
.crtc_hsync_end
;
6073 mode
->vdisplay
= pipe_config
->adjusted_mode
.crtc_vdisplay
;
6074 mode
->vtotal
= pipe_config
->adjusted_mode
.crtc_vtotal
;
6075 mode
->vsync_start
= pipe_config
->adjusted_mode
.crtc_vsync_start
;
6076 mode
->vsync_end
= pipe_config
->adjusted_mode
.crtc_vsync_end
;
6078 mode
->flags
= pipe_config
->adjusted_mode
.flags
;
6080 mode
->clock
= pipe_config
->adjusted_mode
.crtc_clock
;
6081 mode
->flags
|= pipe_config
->adjusted_mode
.flags
;
6084 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
)
6086 struct drm_device
*dev
= intel_crtc
->base
.dev
;
6087 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6092 if ((intel_crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
6093 (intel_crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
6094 pipeconf
|= I915_READ(PIPECONF(intel_crtc
->pipe
)) & PIPECONF_ENABLE
;
6096 if (intel_crtc
->config
.double_wide
)
6097 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
6099 /* only g4x and later have fancy bpc/dither controls */
6100 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
6101 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6102 if (intel_crtc
->config
.dither
&& intel_crtc
->config
.pipe_bpp
!= 30)
6103 pipeconf
|= PIPECONF_DITHER_EN
|
6104 PIPECONF_DITHER_TYPE_SP
;
6106 switch (intel_crtc
->config
.pipe_bpp
) {
6108 pipeconf
|= PIPECONF_6BPC
;
6111 pipeconf
|= PIPECONF_8BPC
;
6114 pipeconf
|= PIPECONF_10BPC
;
6117 /* Case prevented by intel_choose_pipe_bpp_dither. */
6122 if (HAS_PIPE_CXSR(dev
)) {
6123 if (intel_crtc
->lowfreq_avail
) {
6124 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6125 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
6127 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6131 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
6132 if (INTEL_INFO(dev
)->gen
< 4 ||
6133 intel_pipe_has_type(&intel_crtc
->base
, INTEL_OUTPUT_SDVO
))
6134 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
6136 pipeconf
|= PIPECONF_INTERLACE_W_SYNC_SHIFT
;
6138 pipeconf
|= PIPECONF_PROGRESSIVE
;
6140 if (IS_VALLEYVIEW(dev
) && intel_crtc
->config
.limited_color_range
)
6141 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
6143 I915_WRITE(PIPECONF(intel_crtc
->pipe
), pipeconf
);
6144 POSTING_READ(PIPECONF(intel_crtc
->pipe
));
6147 static int i9xx_crtc_mode_set(struct drm_crtc
*crtc
,
6149 struct drm_framebuffer
*fb
)
6151 struct drm_device
*dev
= crtc
->dev
;
6152 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6153 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6154 int refclk
, num_connectors
= 0;
6155 intel_clock_t clock
, reduced_clock
;
6156 bool ok
, has_reduced_clock
= false;
6157 bool is_lvds
= false, is_dsi
= false;
6158 struct intel_encoder
*encoder
;
6159 const intel_limit_t
*limit
;
6161 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
6162 switch (encoder
->type
) {
6163 case INTEL_OUTPUT_LVDS
:
6166 case INTEL_OUTPUT_DSI
:
6177 if (!intel_crtc
->config
.clock_set
) {
6178 refclk
= i9xx_get_refclk(crtc
, num_connectors
);
6181 * Returns a set of divisors for the desired target clock with
6182 * the given refclk, or FALSE. The returned values represent
6183 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6186 limit
= intel_limit(crtc
, refclk
);
6187 ok
= dev_priv
->display
.find_dpll(limit
, crtc
,
6188 intel_crtc
->config
.port_clock
,
6189 refclk
, NULL
, &clock
);
6191 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6195 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
6197 * Ensure we match the reduced clock's P to the target
6198 * clock. If the clocks don't match, we can't switch
6199 * the display clock by using the FP0/FP1. In such case
6200 * we will disable the LVDS downclock feature.
6203 dev_priv
->display
.find_dpll(limit
, crtc
,
6204 dev_priv
->lvds_downclock
,
6208 /* Compat-code for transition, will disappear. */
6209 intel_crtc
->config
.dpll
.n
= clock
.n
;
6210 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
6211 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
6212 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
6213 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
6217 i8xx_update_pll(intel_crtc
,
6218 has_reduced_clock
? &reduced_clock
: NULL
,
6220 } else if (IS_CHERRYVIEW(dev
)) {
6221 chv_update_pll(intel_crtc
);
6222 } else if (IS_VALLEYVIEW(dev
)) {
6223 vlv_update_pll(intel_crtc
);
6225 i9xx_update_pll(intel_crtc
,
6226 has_reduced_clock
? &reduced_clock
: NULL
,
6233 static void i9xx_get_pfit_config(struct intel_crtc
*crtc
,
6234 struct intel_crtc_config
*pipe_config
)
6236 struct drm_device
*dev
= crtc
->base
.dev
;
6237 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6240 if (INTEL_INFO(dev
)->gen
<= 3 && (IS_I830(dev
) || !IS_MOBILE(dev
)))
6243 tmp
= I915_READ(PFIT_CONTROL
);
6244 if (!(tmp
& PFIT_ENABLE
))
6247 /* Check whether the pfit is attached to our pipe. */
6248 if (INTEL_INFO(dev
)->gen
< 4) {
6249 if (crtc
->pipe
!= PIPE_B
)
6252 if ((tmp
& PFIT_PIPE_MASK
) != (crtc
->pipe
<< PFIT_PIPE_SHIFT
))
6256 pipe_config
->gmch_pfit
.control
= tmp
;
6257 pipe_config
->gmch_pfit
.pgm_ratios
= I915_READ(PFIT_PGM_RATIOS
);
6258 if (INTEL_INFO(dev
)->gen
< 5)
6259 pipe_config
->gmch_pfit
.lvds_border_bits
=
6260 I915_READ(LVDS
) & LVDS_BORDER_ENABLE
;
6263 static void vlv_crtc_clock_get(struct intel_crtc
*crtc
,
6264 struct intel_crtc_config
*pipe_config
)
6266 struct drm_device
*dev
= crtc
->base
.dev
;
6267 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6268 int pipe
= pipe_config
->cpu_transcoder
;
6269 intel_clock_t clock
;
6271 int refclk
= 100000;
6273 /* In case of MIPI DPLL will not even be used */
6274 if (!(pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
))
6277 mutex_lock(&dev_priv
->dpio_lock
);
6278 mdiv
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW3(pipe
));
6279 mutex_unlock(&dev_priv
->dpio_lock
);
6281 clock
.m1
= (mdiv
>> DPIO_M1DIV_SHIFT
) & 7;
6282 clock
.m2
= mdiv
& DPIO_M2DIV_MASK
;
6283 clock
.n
= (mdiv
>> DPIO_N_SHIFT
) & 0xf;
6284 clock
.p1
= (mdiv
>> DPIO_P1_SHIFT
) & 7;
6285 clock
.p2
= (mdiv
>> DPIO_P2_SHIFT
) & 0x1f;
6287 vlv_clock(refclk
, &clock
);
6289 /* clock.dot is the fast clock */
6290 pipe_config
->port_clock
= clock
.dot
/ 5;
6293 static void i9xx_get_plane_config(struct intel_crtc
*crtc
,
6294 struct intel_plane_config
*plane_config
)
6296 struct drm_device
*dev
= crtc
->base
.dev
;
6297 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6298 u32 val
, base
, offset
;
6299 int pipe
= crtc
->pipe
, plane
= crtc
->plane
;
6300 int fourcc
, pixel_format
;
6303 crtc
->base
.primary
->fb
= kzalloc(sizeof(struct intel_framebuffer
), GFP_KERNEL
);
6304 if (!crtc
->base
.primary
->fb
) {
6305 DRM_DEBUG_KMS("failed to alloc fb\n");
6309 val
= I915_READ(DSPCNTR(plane
));
6311 if (INTEL_INFO(dev
)->gen
>= 4)
6312 if (val
& DISPPLANE_TILED
)
6313 plane_config
->tiled
= true;
6315 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
6316 fourcc
= intel_format_to_fourcc(pixel_format
);
6317 crtc
->base
.primary
->fb
->pixel_format
= fourcc
;
6318 crtc
->base
.primary
->fb
->bits_per_pixel
=
6319 drm_format_plane_cpp(fourcc
, 0) * 8;
6321 if (INTEL_INFO(dev
)->gen
>= 4) {
6322 if (plane_config
->tiled
)
6323 offset
= I915_READ(DSPTILEOFF(plane
));
6325 offset
= I915_READ(DSPLINOFF(plane
));
6326 base
= I915_READ(DSPSURF(plane
)) & 0xfffff000;
6328 base
= I915_READ(DSPADDR(plane
));
6330 plane_config
->base
= base
;
6332 val
= I915_READ(PIPESRC(pipe
));
6333 crtc
->base
.primary
->fb
->width
= ((val
>> 16) & 0xfff) + 1;
6334 crtc
->base
.primary
->fb
->height
= ((val
>> 0) & 0xfff) + 1;
6336 val
= I915_READ(DSPSTRIDE(pipe
));
6337 crtc
->base
.primary
->fb
->pitches
[0] = val
& 0xffffffc0;
6339 aligned_height
= intel_align_height(dev
, crtc
->base
.primary
->fb
->height
,
6340 plane_config
->tiled
);
6342 plane_config
->size
= PAGE_ALIGN(crtc
->base
.primary
->fb
->pitches
[0] *
6345 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6346 pipe
, plane
, crtc
->base
.primary
->fb
->width
,
6347 crtc
->base
.primary
->fb
->height
,
6348 crtc
->base
.primary
->fb
->bits_per_pixel
, base
,
6349 crtc
->base
.primary
->fb
->pitches
[0],
6350 plane_config
->size
);
6354 static void chv_crtc_clock_get(struct intel_crtc
*crtc
,
6355 struct intel_crtc_config
*pipe_config
)
6357 struct drm_device
*dev
= crtc
->base
.dev
;
6358 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6359 int pipe
= pipe_config
->cpu_transcoder
;
6360 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
6361 intel_clock_t clock
;
6362 u32 cmn_dw13
, pll_dw0
, pll_dw1
, pll_dw2
;
6363 int refclk
= 100000;
6365 mutex_lock(&dev_priv
->dpio_lock
);
6366 cmn_dw13
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW13(port
));
6367 pll_dw0
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW0(port
));
6368 pll_dw1
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW1(port
));
6369 pll_dw2
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW2(port
));
6370 mutex_unlock(&dev_priv
->dpio_lock
);
6372 clock
.m1
= (pll_dw1
& 0x7) == DPIO_CHV_M1_DIV_BY_2
? 2 : 0;
6373 clock
.m2
= ((pll_dw0
& 0xff) << 22) | (pll_dw2
& 0x3fffff);
6374 clock
.n
= (pll_dw1
>> DPIO_CHV_N_DIV_SHIFT
) & 0xf;
6375 clock
.p1
= (cmn_dw13
>> DPIO_CHV_P1_DIV_SHIFT
) & 0x7;
6376 clock
.p2
= (cmn_dw13
>> DPIO_CHV_P2_DIV_SHIFT
) & 0x1f;
6378 chv_clock(refclk
, &clock
);
6380 /* clock.dot is the fast clock */
6381 pipe_config
->port_clock
= clock
.dot
/ 5;
6384 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
6385 struct intel_crtc_config
*pipe_config
)
6387 struct drm_device
*dev
= crtc
->base
.dev
;
6388 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6391 if (!intel_display_power_enabled(dev_priv
,
6392 POWER_DOMAIN_PIPE(crtc
->pipe
)))
6395 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
6396 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
6398 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
6399 if (!(tmp
& PIPECONF_ENABLE
))
6402 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
6403 switch (tmp
& PIPECONF_BPC_MASK
) {
6405 pipe_config
->pipe_bpp
= 18;
6408 pipe_config
->pipe_bpp
= 24;
6410 case PIPECONF_10BPC
:
6411 pipe_config
->pipe_bpp
= 30;
6418 if (IS_VALLEYVIEW(dev
) && (tmp
& PIPECONF_COLOR_RANGE_SELECT
))
6419 pipe_config
->limited_color_range
= true;
6421 if (INTEL_INFO(dev
)->gen
< 4)
6422 pipe_config
->double_wide
= tmp
& PIPECONF_DOUBLE_WIDE
;
6424 intel_get_pipe_timings(crtc
, pipe_config
);
6426 i9xx_get_pfit_config(crtc
, pipe_config
);
6428 if (INTEL_INFO(dev
)->gen
>= 4) {
6429 tmp
= I915_READ(DPLL_MD(crtc
->pipe
));
6430 pipe_config
->pixel_multiplier
=
6431 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
6432 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
6433 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
6434 } else if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
6435 tmp
= I915_READ(DPLL(crtc
->pipe
));
6436 pipe_config
->pixel_multiplier
=
6437 ((tmp
& SDVO_MULTIPLIER_MASK
)
6438 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
6440 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6441 * port and will be fixed up in the encoder->get_config
6443 pipe_config
->pixel_multiplier
= 1;
6445 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(crtc
->pipe
));
6446 if (!IS_VALLEYVIEW(dev
)) {
6448 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6449 * on 830. Filter it out here so that we don't
6450 * report errors due to that.
6453 pipe_config
->dpll_hw_state
.dpll
&= ~DPLL_DVO_2X_MODE
;
6455 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(crtc
->pipe
));
6456 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(crtc
->pipe
));
6458 /* Mask out read-only status bits. */
6459 pipe_config
->dpll_hw_state
.dpll
&= ~(DPLL_LOCK_VLV
|
6460 DPLL_PORTC_READY_MASK
|
6461 DPLL_PORTB_READY_MASK
);
6464 if (IS_CHERRYVIEW(dev
))
6465 chv_crtc_clock_get(crtc
, pipe_config
);
6466 else if (IS_VALLEYVIEW(dev
))
6467 vlv_crtc_clock_get(crtc
, pipe_config
);
6469 i9xx_crtc_clock_get(crtc
, pipe_config
);
6474 static void ironlake_init_pch_refclk(struct drm_device
*dev
)
6476 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6477 struct intel_encoder
*encoder
;
6479 bool has_lvds
= false;
6480 bool has_cpu_edp
= false;
6481 bool has_panel
= false;
6482 bool has_ck505
= false;
6483 bool can_ssc
= false;
6485 /* We need to take the global config into account */
6486 for_each_intel_encoder(dev
, encoder
) {
6487 switch (encoder
->type
) {
6488 case INTEL_OUTPUT_LVDS
:
6492 case INTEL_OUTPUT_EDP
:
6494 if (enc_to_dig_port(&encoder
->base
)->port
== PORT_A
)
6500 if (HAS_PCH_IBX(dev
)) {
6501 has_ck505
= dev_priv
->vbt
.display_clock_mode
;
6502 can_ssc
= has_ck505
;
6508 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6509 has_panel
, has_lvds
, has_ck505
);
6511 /* Ironlake: try to setup display ref clock before DPLL
6512 * enabling. This is only under driver's control after
6513 * PCH B stepping, previous chipset stepping should be
6514 * ignoring this setting.
6516 val
= I915_READ(PCH_DREF_CONTROL
);
6518 /* As we must carefully and slowly disable/enable each source in turn,
6519 * compute the final state we want first and check if we need to
6520 * make any changes at all.
6523 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
6525 final
|= DREF_NONSPREAD_CK505_ENABLE
;
6527 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
6529 final
&= ~DREF_SSC_SOURCE_MASK
;
6530 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
6531 final
&= ~DREF_SSC1_ENABLE
;
6534 final
|= DREF_SSC_SOURCE_ENABLE
;
6536 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
6537 final
|= DREF_SSC1_ENABLE
;
6540 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
6541 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
6543 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
6545 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6547 final
|= DREF_SSC_SOURCE_DISABLE
;
6548 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6554 /* Always enable nonspread source */
6555 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
6558 val
|= DREF_NONSPREAD_CK505_ENABLE
;
6560 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
6563 val
&= ~DREF_SSC_SOURCE_MASK
;
6564 val
|= DREF_SSC_SOURCE_ENABLE
;
6566 /* SSC must be turned on before enabling the CPU output */
6567 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
6568 DRM_DEBUG_KMS("Using SSC on panel\n");
6569 val
|= DREF_SSC1_ENABLE
;
6571 val
&= ~DREF_SSC1_ENABLE
;
6573 /* Get SSC going before enabling the outputs */
6574 I915_WRITE(PCH_DREF_CONTROL
, val
);
6575 POSTING_READ(PCH_DREF_CONTROL
);
6578 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
6580 /* Enable CPU source on CPU attached eDP */
6582 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
6583 DRM_DEBUG_KMS("Using SSC on eDP\n");
6584 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
6586 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
6588 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6590 I915_WRITE(PCH_DREF_CONTROL
, val
);
6591 POSTING_READ(PCH_DREF_CONTROL
);
6594 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6596 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
6598 /* Turn off CPU output */
6599 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6601 I915_WRITE(PCH_DREF_CONTROL
, val
);
6602 POSTING_READ(PCH_DREF_CONTROL
);
6605 /* Turn off the SSC source */
6606 val
&= ~DREF_SSC_SOURCE_MASK
;
6607 val
|= DREF_SSC_SOURCE_DISABLE
;
6610 val
&= ~DREF_SSC1_ENABLE
;
6612 I915_WRITE(PCH_DREF_CONTROL
, val
);
6613 POSTING_READ(PCH_DREF_CONTROL
);
6617 BUG_ON(val
!= final
);
6620 static void lpt_reset_fdi_mphy(struct drm_i915_private
*dev_priv
)
6624 tmp
= I915_READ(SOUTH_CHICKEN2
);
6625 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
6626 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
6628 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2
) &
6629 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
6630 DRM_ERROR("FDI mPHY reset assert timeout\n");
6632 tmp
= I915_READ(SOUTH_CHICKEN2
);
6633 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
6634 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
6636 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2
) &
6637 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0, 100))
6638 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6641 /* WaMPhyProgramming:hsw */
6642 static void lpt_program_fdi_mphy(struct drm_i915_private
*dev_priv
)
6646 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
6647 tmp
&= ~(0xFF << 24);
6648 tmp
|= (0x12 << 24);
6649 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
6651 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
6653 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
6655 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
6657 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
6659 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
6660 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
6661 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
6663 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
6664 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
6665 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
6667 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
6670 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
6672 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
6675 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
6677 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
6680 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
6682 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
6685 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
6687 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
6688 tmp
&= ~(0xFF << 16);
6689 tmp
|= (0x1C << 16);
6690 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
6692 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
6693 tmp
&= ~(0xFF << 16);
6694 tmp
|= (0x1C << 16);
6695 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
6697 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
6699 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
6701 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
6703 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
6705 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
6706 tmp
&= ~(0xF << 28);
6708 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
6710 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
6711 tmp
&= ~(0xF << 28);
6713 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
6716 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6717 * Programming" based on the parameters passed:
6718 * - Sequence to enable CLKOUT_DP
6719 * - Sequence to enable CLKOUT_DP without spread
6720 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6722 static void lpt_enable_clkout_dp(struct drm_device
*dev
, bool with_spread
,
6725 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6728 if (WARN(with_fdi
&& !with_spread
, "FDI requires downspread\n"))
6730 if (WARN(dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
&&
6731 with_fdi
, "LP PCH doesn't have FDI\n"))
6734 mutex_lock(&dev_priv
->dpio_lock
);
6736 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
6737 tmp
&= ~SBI_SSCCTL_DISABLE
;
6738 tmp
|= SBI_SSCCTL_PATHALT
;
6739 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
6744 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
6745 tmp
&= ~SBI_SSCCTL_PATHALT
;
6746 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
6749 lpt_reset_fdi_mphy(dev_priv
);
6750 lpt_program_fdi_mphy(dev_priv
);
6754 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
6755 SBI_GEN0
: SBI_DBUFF0
;
6756 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
6757 tmp
|= SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
6758 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
6760 mutex_unlock(&dev_priv
->dpio_lock
);
6763 /* Sequence to disable CLKOUT_DP */
6764 static void lpt_disable_clkout_dp(struct drm_device
*dev
)
6766 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6769 mutex_lock(&dev_priv
->dpio_lock
);
6771 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
6772 SBI_GEN0
: SBI_DBUFF0
;
6773 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
6774 tmp
&= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
6775 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
6777 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
6778 if (!(tmp
& SBI_SSCCTL_DISABLE
)) {
6779 if (!(tmp
& SBI_SSCCTL_PATHALT
)) {
6780 tmp
|= SBI_SSCCTL_PATHALT
;
6781 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
6784 tmp
|= SBI_SSCCTL_DISABLE
;
6785 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
6788 mutex_unlock(&dev_priv
->dpio_lock
);
6791 static void lpt_init_pch_refclk(struct drm_device
*dev
)
6793 struct intel_encoder
*encoder
;
6794 bool has_vga
= false;
6796 for_each_intel_encoder(dev
, encoder
) {
6797 switch (encoder
->type
) {
6798 case INTEL_OUTPUT_ANALOG
:
6805 lpt_enable_clkout_dp(dev
, true, true);
6807 lpt_disable_clkout_dp(dev
);
6811 * Initialize reference clocks when the driver loads
6813 void intel_init_pch_refclk(struct drm_device
*dev
)
6815 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
6816 ironlake_init_pch_refclk(dev
);
6817 else if (HAS_PCH_LPT(dev
))
6818 lpt_init_pch_refclk(dev
);
6821 static int ironlake_get_refclk(struct drm_crtc
*crtc
)
6823 struct drm_device
*dev
= crtc
->dev
;
6824 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6825 struct intel_encoder
*encoder
;
6826 int num_connectors
= 0;
6827 bool is_lvds
= false;
6829 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
6830 switch (encoder
->type
) {
6831 case INTEL_OUTPUT_LVDS
:
6838 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
6839 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6840 dev_priv
->vbt
.lvds_ssc_freq
);
6841 return dev_priv
->vbt
.lvds_ssc_freq
;
6847 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
)
6849 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
6850 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6851 int pipe
= intel_crtc
->pipe
;
6856 switch (intel_crtc
->config
.pipe_bpp
) {
6858 val
|= PIPECONF_6BPC
;
6861 val
|= PIPECONF_8BPC
;
6864 val
|= PIPECONF_10BPC
;
6867 val
|= PIPECONF_12BPC
;
6870 /* Case prevented by intel_choose_pipe_bpp_dither. */
6874 if (intel_crtc
->config
.dither
)
6875 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
6877 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
6878 val
|= PIPECONF_INTERLACED_ILK
;
6880 val
|= PIPECONF_PROGRESSIVE
;
6882 if (intel_crtc
->config
.limited_color_range
)
6883 val
|= PIPECONF_COLOR_RANGE_SELECT
;
6885 I915_WRITE(PIPECONF(pipe
), val
);
6886 POSTING_READ(PIPECONF(pipe
));
6890 * Set up the pipe CSC unit.
6892 * Currently only full range RGB to limited range RGB conversion
6893 * is supported, but eventually this should handle various
6894 * RGB<->YCbCr scenarios as well.
6896 static void intel_set_pipe_csc(struct drm_crtc
*crtc
)
6898 struct drm_device
*dev
= crtc
->dev
;
6899 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6900 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6901 int pipe
= intel_crtc
->pipe
;
6902 uint16_t coeff
= 0x7800; /* 1.0 */
6905 * TODO: Check what kind of values actually come out of the pipe
6906 * with these coeff/postoff values and adjust to get the best
6907 * accuracy. Perhaps we even need to take the bpc value into
6911 if (intel_crtc
->config
.limited_color_range
)
6912 coeff
= ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6915 * GY/GU and RY/RU should be the other way around according
6916 * to BSpec, but reality doesn't agree. Just set them up in
6917 * a way that results in the correct picture.
6919 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe
), coeff
<< 16);
6920 I915_WRITE(PIPE_CSC_COEFF_BY(pipe
), 0);
6922 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe
), coeff
);
6923 I915_WRITE(PIPE_CSC_COEFF_BU(pipe
), 0);
6925 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe
), 0);
6926 I915_WRITE(PIPE_CSC_COEFF_BV(pipe
), coeff
<< 16);
6928 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe
), 0);
6929 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe
), 0);
6930 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe
), 0);
6932 if (INTEL_INFO(dev
)->gen
> 6) {
6933 uint16_t postoff
= 0;
6935 if (intel_crtc
->config
.limited_color_range
)
6936 postoff
= (16 * (1 << 12) / 255) & 0x1fff;
6938 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe
), postoff
);
6939 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe
), postoff
);
6940 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe
), postoff
);
6942 I915_WRITE(PIPE_CSC_MODE(pipe
), 0);
6944 uint32_t mode
= CSC_MODE_YUV_TO_RGB
;
6946 if (intel_crtc
->config
.limited_color_range
)
6947 mode
|= CSC_BLACK_SCREEN_OFFSET
;
6949 I915_WRITE(PIPE_CSC_MODE(pipe
), mode
);
6953 static void haswell_set_pipeconf(struct drm_crtc
*crtc
)
6955 struct drm_device
*dev
= crtc
->dev
;
6956 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6957 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6958 enum pipe pipe
= intel_crtc
->pipe
;
6959 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
6964 if (IS_HASWELL(dev
) && intel_crtc
->config
.dither
)
6965 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
6967 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
6968 val
|= PIPECONF_INTERLACED_ILK
;
6970 val
|= PIPECONF_PROGRESSIVE
;
6972 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
6973 POSTING_READ(PIPECONF(cpu_transcoder
));
6975 I915_WRITE(GAMMA_MODE(intel_crtc
->pipe
), GAMMA_MODE_MODE_8BIT
);
6976 POSTING_READ(GAMMA_MODE(intel_crtc
->pipe
));
6978 if (IS_BROADWELL(dev
)) {
6981 switch (intel_crtc
->config
.pipe_bpp
) {
6983 val
|= PIPEMISC_DITHER_6_BPC
;
6986 val
|= PIPEMISC_DITHER_8_BPC
;
6989 val
|= PIPEMISC_DITHER_10_BPC
;
6992 val
|= PIPEMISC_DITHER_12_BPC
;
6995 /* Case prevented by pipe_config_set_bpp. */
6999 if (intel_crtc
->config
.dither
)
7000 val
|= PIPEMISC_DITHER_ENABLE
| PIPEMISC_DITHER_TYPE_SP
;
7002 I915_WRITE(PIPEMISC(pipe
), val
);
7006 static bool ironlake_compute_clocks(struct drm_crtc
*crtc
,
7007 intel_clock_t
*clock
,
7008 bool *has_reduced_clock
,
7009 intel_clock_t
*reduced_clock
)
7011 struct drm_device
*dev
= crtc
->dev
;
7012 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7013 struct intel_encoder
*intel_encoder
;
7015 const intel_limit_t
*limit
;
7016 bool ret
, is_lvds
= false;
7018 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
7019 switch (intel_encoder
->type
) {
7020 case INTEL_OUTPUT_LVDS
:
7026 refclk
= ironlake_get_refclk(crtc
);
7029 * Returns a set of divisors for the desired target clock with the given
7030 * refclk, or FALSE. The returned values represent the clock equation:
7031 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7033 limit
= intel_limit(crtc
, refclk
);
7034 ret
= dev_priv
->display
.find_dpll(limit
, crtc
,
7035 to_intel_crtc(crtc
)->config
.port_clock
,
7036 refclk
, NULL
, clock
);
7040 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
7042 * Ensure we match the reduced clock's P to the target clock.
7043 * If the clocks don't match, we can't switch the display clock
7044 * by using the FP0/FP1. In such case we will disable the LVDS
7045 * downclock feature.
7047 *has_reduced_clock
=
7048 dev_priv
->display
.find_dpll(limit
, crtc
,
7049 dev_priv
->lvds_downclock
,
7057 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
7060 * Account for spread spectrum to avoid
7061 * oversubscribing the link. Max center spread
7062 * is 2.5%; use 5% for safety's sake.
7064 u32 bps
= target_clock
* bpp
* 21 / 20;
7065 return DIV_ROUND_UP(bps
, link_bw
* 8);
7068 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
7070 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
7073 static uint32_t ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
7075 intel_clock_t
*reduced_clock
, u32
*fp2
)
7077 struct drm_crtc
*crtc
= &intel_crtc
->base
;
7078 struct drm_device
*dev
= crtc
->dev
;
7079 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7080 struct intel_encoder
*intel_encoder
;
7082 int factor
, num_connectors
= 0;
7083 bool is_lvds
= false, is_sdvo
= false;
7085 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
7086 switch (intel_encoder
->type
) {
7087 case INTEL_OUTPUT_LVDS
:
7090 case INTEL_OUTPUT_SDVO
:
7091 case INTEL_OUTPUT_HDMI
:
7099 /* Enable autotuning of the PLL clock (if permissible) */
7102 if ((intel_panel_use_ssc(dev_priv
) &&
7103 dev_priv
->vbt
.lvds_ssc_freq
== 100000) ||
7104 (HAS_PCH_IBX(dev
) && intel_is_dual_link_lvds(dev
)))
7106 } else if (intel_crtc
->config
.sdvo_tv_clock
)
7109 if (ironlake_needs_fb_cb_tune(&intel_crtc
->config
.dpll
, factor
))
7112 if (fp2
&& (reduced_clock
->m
< factor
* reduced_clock
->n
))
7118 dpll
|= DPLLB_MODE_LVDS
;
7120 dpll
|= DPLLB_MODE_DAC_SERIAL
;
7122 dpll
|= (intel_crtc
->config
.pixel_multiplier
- 1)
7123 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
7126 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7127 if (intel_crtc
->config
.has_dp_encoder
)
7128 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7130 /* compute bitmask from p1 value */
7131 dpll
|= (1 << (intel_crtc
->config
.dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7133 dpll
|= (1 << (intel_crtc
->config
.dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
7135 switch (intel_crtc
->config
.dpll
.p2
) {
7137 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
7140 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
7143 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
7146 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
7150 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
7151 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
7153 dpll
|= PLL_REF_INPUT_DREFCLK
;
7155 return dpll
| DPLL_VCO_ENABLE
;
7158 static int ironlake_crtc_mode_set(struct drm_crtc
*crtc
,
7160 struct drm_framebuffer
*fb
)
7162 struct drm_device
*dev
= crtc
->dev
;
7163 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7164 int num_connectors
= 0;
7165 intel_clock_t clock
, reduced_clock
;
7166 u32 dpll
= 0, fp
= 0, fp2
= 0;
7167 bool ok
, has_reduced_clock
= false;
7168 bool is_lvds
= false;
7169 struct intel_encoder
*encoder
;
7170 struct intel_shared_dpll
*pll
;
7172 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
7173 switch (encoder
->type
) {
7174 case INTEL_OUTPUT_LVDS
:
7182 WARN(!(HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)),
7183 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev
));
7185 ok
= ironlake_compute_clocks(crtc
, &clock
,
7186 &has_reduced_clock
, &reduced_clock
);
7187 if (!ok
&& !intel_crtc
->config
.clock_set
) {
7188 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7191 /* Compat-code for transition, will disappear. */
7192 if (!intel_crtc
->config
.clock_set
) {
7193 intel_crtc
->config
.dpll
.n
= clock
.n
;
7194 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
7195 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
7196 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
7197 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
7200 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7201 if (intel_crtc
->config
.has_pch_encoder
) {
7202 fp
= i9xx_dpll_compute_fp(&intel_crtc
->config
.dpll
);
7203 if (has_reduced_clock
)
7204 fp2
= i9xx_dpll_compute_fp(&reduced_clock
);
7206 dpll
= ironlake_compute_dpll(intel_crtc
,
7207 &fp
, &reduced_clock
,
7208 has_reduced_clock
? &fp2
: NULL
);
7210 intel_crtc
->config
.dpll_hw_state
.dpll
= dpll
;
7211 intel_crtc
->config
.dpll_hw_state
.fp0
= fp
;
7212 if (has_reduced_clock
)
7213 intel_crtc
->config
.dpll_hw_state
.fp1
= fp2
;
7215 intel_crtc
->config
.dpll_hw_state
.fp1
= fp
;
7217 pll
= intel_get_shared_dpll(intel_crtc
);
7219 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7220 pipe_name(intel_crtc
->pipe
));
7224 intel_put_shared_dpll(intel_crtc
);
7226 if (is_lvds
&& has_reduced_clock
&& i915
.powersave
)
7227 intel_crtc
->lowfreq_avail
= true;
7229 intel_crtc
->lowfreq_avail
= false;
7234 static void intel_pch_transcoder_get_m_n(struct intel_crtc
*crtc
,
7235 struct intel_link_m_n
*m_n
)
7237 struct drm_device
*dev
= crtc
->base
.dev
;
7238 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7239 enum pipe pipe
= crtc
->pipe
;
7241 m_n
->link_m
= I915_READ(PCH_TRANS_LINK_M1(pipe
));
7242 m_n
->link_n
= I915_READ(PCH_TRANS_LINK_N1(pipe
));
7243 m_n
->gmch_m
= I915_READ(PCH_TRANS_DATA_M1(pipe
))
7245 m_n
->gmch_n
= I915_READ(PCH_TRANS_DATA_N1(pipe
));
7246 m_n
->tu
= ((I915_READ(PCH_TRANS_DATA_M1(pipe
))
7247 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7250 static void intel_cpu_transcoder_get_m_n(struct intel_crtc
*crtc
,
7251 enum transcoder transcoder
,
7252 struct intel_link_m_n
*m_n
,
7253 struct intel_link_m_n
*m2_n2
)
7255 struct drm_device
*dev
= crtc
->base
.dev
;
7256 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7257 enum pipe pipe
= crtc
->pipe
;
7259 if (INTEL_INFO(dev
)->gen
>= 5) {
7260 m_n
->link_m
= I915_READ(PIPE_LINK_M1(transcoder
));
7261 m_n
->link_n
= I915_READ(PIPE_LINK_N1(transcoder
));
7262 m_n
->gmch_m
= I915_READ(PIPE_DATA_M1(transcoder
))
7264 m_n
->gmch_n
= I915_READ(PIPE_DATA_N1(transcoder
));
7265 m_n
->tu
= ((I915_READ(PIPE_DATA_M1(transcoder
))
7266 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7267 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7268 * gen < 8) and if DRRS is supported (to make sure the
7269 * registers are not unnecessarily read).
7271 if (m2_n2
&& INTEL_INFO(dev
)->gen
< 8 &&
7272 crtc
->config
.has_drrs
) {
7273 m2_n2
->link_m
= I915_READ(PIPE_LINK_M2(transcoder
));
7274 m2_n2
->link_n
= I915_READ(PIPE_LINK_N2(transcoder
));
7275 m2_n2
->gmch_m
= I915_READ(PIPE_DATA_M2(transcoder
))
7277 m2_n2
->gmch_n
= I915_READ(PIPE_DATA_N2(transcoder
));
7278 m2_n2
->tu
= ((I915_READ(PIPE_DATA_M2(transcoder
))
7279 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7282 m_n
->link_m
= I915_READ(PIPE_LINK_M_G4X(pipe
));
7283 m_n
->link_n
= I915_READ(PIPE_LINK_N_G4X(pipe
));
7284 m_n
->gmch_m
= I915_READ(PIPE_DATA_M_G4X(pipe
))
7286 m_n
->gmch_n
= I915_READ(PIPE_DATA_N_G4X(pipe
));
7287 m_n
->tu
= ((I915_READ(PIPE_DATA_M_G4X(pipe
))
7288 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7292 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
7293 struct intel_crtc_config
*pipe_config
)
7295 if (crtc
->config
.has_pch_encoder
)
7296 intel_pch_transcoder_get_m_n(crtc
, &pipe_config
->dp_m_n
);
7298 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
7299 &pipe_config
->dp_m_n
,
7300 &pipe_config
->dp_m2_n2
);
7303 static void ironlake_get_fdi_m_n_config(struct intel_crtc
*crtc
,
7304 struct intel_crtc_config
*pipe_config
)
7306 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
7307 &pipe_config
->fdi_m_n
, NULL
);
7310 static void ironlake_get_pfit_config(struct intel_crtc
*crtc
,
7311 struct intel_crtc_config
*pipe_config
)
7313 struct drm_device
*dev
= crtc
->base
.dev
;
7314 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7317 tmp
= I915_READ(PF_CTL(crtc
->pipe
));
7319 if (tmp
& PF_ENABLE
) {
7320 pipe_config
->pch_pfit
.enabled
= true;
7321 pipe_config
->pch_pfit
.pos
= I915_READ(PF_WIN_POS(crtc
->pipe
));
7322 pipe_config
->pch_pfit
.size
= I915_READ(PF_WIN_SZ(crtc
->pipe
));
7324 /* We currently do not free assignements of panel fitters on
7325 * ivb/hsw (since we don't use the higher upscaling modes which
7326 * differentiates them) so just WARN about this case for now. */
7328 WARN_ON((tmp
& PF_PIPE_SEL_MASK_IVB
) !=
7329 PF_PIPE_SEL_IVB(crtc
->pipe
));
7334 static void ironlake_get_plane_config(struct intel_crtc
*crtc
,
7335 struct intel_plane_config
*plane_config
)
7337 struct drm_device
*dev
= crtc
->base
.dev
;
7338 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7339 u32 val
, base
, offset
;
7340 int pipe
= crtc
->pipe
, plane
= crtc
->plane
;
7341 int fourcc
, pixel_format
;
7344 crtc
->base
.primary
->fb
= kzalloc(sizeof(struct intel_framebuffer
), GFP_KERNEL
);
7345 if (!crtc
->base
.primary
->fb
) {
7346 DRM_DEBUG_KMS("failed to alloc fb\n");
7350 val
= I915_READ(DSPCNTR(plane
));
7352 if (INTEL_INFO(dev
)->gen
>= 4)
7353 if (val
& DISPPLANE_TILED
)
7354 plane_config
->tiled
= true;
7356 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
7357 fourcc
= intel_format_to_fourcc(pixel_format
);
7358 crtc
->base
.primary
->fb
->pixel_format
= fourcc
;
7359 crtc
->base
.primary
->fb
->bits_per_pixel
=
7360 drm_format_plane_cpp(fourcc
, 0) * 8;
7362 base
= I915_READ(DSPSURF(plane
)) & 0xfffff000;
7363 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
7364 offset
= I915_READ(DSPOFFSET(plane
));
7366 if (plane_config
->tiled
)
7367 offset
= I915_READ(DSPTILEOFF(plane
));
7369 offset
= I915_READ(DSPLINOFF(plane
));
7371 plane_config
->base
= base
;
7373 val
= I915_READ(PIPESRC(pipe
));
7374 crtc
->base
.primary
->fb
->width
= ((val
>> 16) & 0xfff) + 1;
7375 crtc
->base
.primary
->fb
->height
= ((val
>> 0) & 0xfff) + 1;
7377 val
= I915_READ(DSPSTRIDE(pipe
));
7378 crtc
->base
.primary
->fb
->pitches
[0] = val
& 0xffffffc0;
7380 aligned_height
= intel_align_height(dev
, crtc
->base
.primary
->fb
->height
,
7381 plane_config
->tiled
);
7383 plane_config
->size
= PAGE_ALIGN(crtc
->base
.primary
->fb
->pitches
[0] *
7386 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7387 pipe
, plane
, crtc
->base
.primary
->fb
->width
,
7388 crtc
->base
.primary
->fb
->height
,
7389 crtc
->base
.primary
->fb
->bits_per_pixel
, base
,
7390 crtc
->base
.primary
->fb
->pitches
[0],
7391 plane_config
->size
);
7394 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
7395 struct intel_crtc_config
*pipe_config
)
7397 struct drm_device
*dev
= crtc
->base
.dev
;
7398 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7401 if (!intel_display_power_enabled(dev_priv
,
7402 POWER_DOMAIN_PIPE(crtc
->pipe
)))
7405 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
7406 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
7408 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
7409 if (!(tmp
& PIPECONF_ENABLE
))
7412 switch (tmp
& PIPECONF_BPC_MASK
) {
7414 pipe_config
->pipe_bpp
= 18;
7417 pipe_config
->pipe_bpp
= 24;
7419 case PIPECONF_10BPC
:
7420 pipe_config
->pipe_bpp
= 30;
7422 case PIPECONF_12BPC
:
7423 pipe_config
->pipe_bpp
= 36;
7429 if (tmp
& PIPECONF_COLOR_RANGE_SELECT
)
7430 pipe_config
->limited_color_range
= true;
7432 if (I915_READ(PCH_TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
) {
7433 struct intel_shared_dpll
*pll
;
7435 pipe_config
->has_pch_encoder
= true;
7437 tmp
= I915_READ(FDI_RX_CTL(crtc
->pipe
));
7438 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
7439 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
7441 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
7443 if (HAS_PCH_IBX(dev_priv
->dev
)) {
7444 pipe_config
->shared_dpll
=
7445 (enum intel_dpll_id
) crtc
->pipe
;
7447 tmp
= I915_READ(PCH_DPLL_SEL
);
7448 if (tmp
& TRANS_DPLLB_SEL(crtc
->pipe
))
7449 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_B
;
7451 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_A
;
7454 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
7456 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
7457 &pipe_config
->dpll_hw_state
));
7459 tmp
= pipe_config
->dpll_hw_state
.dpll
;
7460 pipe_config
->pixel_multiplier
=
7461 ((tmp
& PLL_REF_SDVO_HDMI_MULTIPLIER_MASK
)
7462 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
) + 1;
7464 ironlake_pch_clock_get(crtc
, pipe_config
);
7466 pipe_config
->pixel_multiplier
= 1;
7469 intel_get_pipe_timings(crtc
, pipe_config
);
7471 ironlake_get_pfit_config(crtc
, pipe_config
);
7476 static void assert_can_disable_lcpll(struct drm_i915_private
*dev_priv
)
7478 struct drm_device
*dev
= dev_priv
->dev
;
7479 struct intel_crtc
*crtc
;
7481 for_each_intel_crtc(dev
, crtc
)
7482 WARN(crtc
->active
, "CRTC for pipe %c enabled\n",
7483 pipe_name(crtc
->pipe
));
7485 WARN(I915_READ(HSW_PWR_WELL_DRIVER
), "Power well on\n");
7486 WARN(I915_READ(SPLL_CTL
) & SPLL_PLL_ENABLE
, "SPLL enabled\n");
7487 WARN(I915_READ(WRPLL_CTL1
) & WRPLL_PLL_ENABLE
, "WRPLL1 enabled\n");
7488 WARN(I915_READ(WRPLL_CTL2
) & WRPLL_PLL_ENABLE
, "WRPLL2 enabled\n");
7489 WARN(I915_READ(PCH_PP_STATUS
) & PP_ON
, "Panel power on\n");
7490 WARN(I915_READ(BLC_PWM_CPU_CTL2
) & BLM_PWM_ENABLE
,
7491 "CPU PWM1 enabled\n");
7492 if (IS_HASWELL(dev
))
7493 WARN(I915_READ(HSW_BLC_PWM2_CTL
) & BLM_PWM_ENABLE
,
7494 "CPU PWM2 enabled\n");
7495 WARN(I915_READ(BLC_PWM_PCH_CTL1
) & BLM_PCH_PWM_ENABLE
,
7496 "PCH PWM1 enabled\n");
7497 WARN(I915_READ(UTIL_PIN_CTL
) & UTIL_PIN_ENABLE
,
7498 "Utility pin enabled\n");
7499 WARN(I915_READ(PCH_GTC_CTL
) & PCH_GTC_ENABLE
, "PCH GTC enabled\n");
7502 * In theory we can still leave IRQs enabled, as long as only the HPD
7503 * interrupts remain enabled. We used to check for that, but since it's
7504 * gen-specific and since we only disable LCPLL after we fully disable
7505 * the interrupts, the check below should be enough.
7507 WARN(intel_irqs_enabled(dev_priv
), "IRQs enabled\n");
7510 static uint32_t hsw_read_dcomp(struct drm_i915_private
*dev_priv
)
7512 struct drm_device
*dev
= dev_priv
->dev
;
7514 if (IS_HASWELL(dev
))
7515 return I915_READ(D_COMP_HSW
);
7517 return I915_READ(D_COMP_BDW
);
7520 static void hsw_write_dcomp(struct drm_i915_private
*dev_priv
, uint32_t val
)
7522 struct drm_device
*dev
= dev_priv
->dev
;
7524 if (IS_HASWELL(dev
)) {
7525 mutex_lock(&dev_priv
->rps
.hw_lock
);
7526 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
,
7528 DRM_ERROR("Failed to write to D_COMP\n");
7529 mutex_unlock(&dev_priv
->rps
.hw_lock
);
7531 I915_WRITE(D_COMP_BDW
, val
);
7532 POSTING_READ(D_COMP_BDW
);
7537 * This function implements pieces of two sequences from BSpec:
7538 * - Sequence for display software to disable LCPLL
7539 * - Sequence for display software to allow package C8+
7540 * The steps implemented here are just the steps that actually touch the LCPLL
7541 * register. Callers should take care of disabling all the display engine
7542 * functions, doing the mode unset, fixing interrupts, etc.
7544 static void hsw_disable_lcpll(struct drm_i915_private
*dev_priv
,
7545 bool switch_to_fclk
, bool allow_power_down
)
7549 assert_can_disable_lcpll(dev_priv
);
7551 val
= I915_READ(LCPLL_CTL
);
7553 if (switch_to_fclk
) {
7554 val
|= LCPLL_CD_SOURCE_FCLK
;
7555 I915_WRITE(LCPLL_CTL
, val
);
7557 if (wait_for_atomic_us(I915_READ(LCPLL_CTL
) &
7558 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
7559 DRM_ERROR("Switching to FCLK failed\n");
7561 val
= I915_READ(LCPLL_CTL
);
7564 val
|= LCPLL_PLL_DISABLE
;
7565 I915_WRITE(LCPLL_CTL
, val
);
7566 POSTING_READ(LCPLL_CTL
);
7568 if (wait_for((I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
) == 0, 1))
7569 DRM_ERROR("LCPLL still locked\n");
7571 val
= hsw_read_dcomp(dev_priv
);
7572 val
|= D_COMP_COMP_DISABLE
;
7573 hsw_write_dcomp(dev_priv
, val
);
7576 if (wait_for((hsw_read_dcomp(dev_priv
) & D_COMP_RCOMP_IN_PROGRESS
) == 0,
7578 DRM_ERROR("D_COMP RCOMP still in progress\n");
7580 if (allow_power_down
) {
7581 val
= I915_READ(LCPLL_CTL
);
7582 val
|= LCPLL_POWER_DOWN_ALLOW
;
7583 I915_WRITE(LCPLL_CTL
, val
);
7584 POSTING_READ(LCPLL_CTL
);
7589 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7592 static void hsw_restore_lcpll(struct drm_i915_private
*dev_priv
)
7595 unsigned long irqflags
;
7597 val
= I915_READ(LCPLL_CTL
);
7599 if ((val
& (LCPLL_PLL_LOCK
| LCPLL_PLL_DISABLE
| LCPLL_CD_SOURCE_FCLK
|
7600 LCPLL_POWER_DOWN_ALLOW
)) == LCPLL_PLL_LOCK
)
7604 * Make sure we're not on PC8 state before disabling PC8, otherwise
7605 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7607 * The other problem is that hsw_restore_lcpll() is called as part of
7608 * the runtime PM resume sequence, so we can't just call
7609 * gen6_gt_force_wake_get() because that function calls
7610 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7611 * while we are on the resume sequence. So to solve this problem we have
7612 * to call special forcewake code that doesn't touch runtime PM and
7613 * doesn't enable the forcewake delayed work.
7615 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
7616 if (dev_priv
->uncore
.forcewake_count
++ == 0)
7617 dev_priv
->uncore
.funcs
.force_wake_get(dev_priv
, FORCEWAKE_ALL
);
7618 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
7620 if (val
& LCPLL_POWER_DOWN_ALLOW
) {
7621 val
&= ~LCPLL_POWER_DOWN_ALLOW
;
7622 I915_WRITE(LCPLL_CTL
, val
);
7623 POSTING_READ(LCPLL_CTL
);
7626 val
= hsw_read_dcomp(dev_priv
);
7627 val
|= D_COMP_COMP_FORCE
;
7628 val
&= ~D_COMP_COMP_DISABLE
;
7629 hsw_write_dcomp(dev_priv
, val
);
7631 val
= I915_READ(LCPLL_CTL
);
7632 val
&= ~LCPLL_PLL_DISABLE
;
7633 I915_WRITE(LCPLL_CTL
, val
);
7635 if (wait_for(I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
, 5))
7636 DRM_ERROR("LCPLL not locked yet\n");
7638 if (val
& LCPLL_CD_SOURCE_FCLK
) {
7639 val
= I915_READ(LCPLL_CTL
);
7640 val
&= ~LCPLL_CD_SOURCE_FCLK
;
7641 I915_WRITE(LCPLL_CTL
, val
);
7643 if (wait_for_atomic_us((I915_READ(LCPLL_CTL
) &
7644 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
7645 DRM_ERROR("Switching back to LCPLL failed\n");
7648 /* See the big comment above. */
7649 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
7650 if (--dev_priv
->uncore
.forcewake_count
== 0)
7651 dev_priv
->uncore
.funcs
.force_wake_put(dev_priv
, FORCEWAKE_ALL
);
7652 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
7656 * Package states C8 and deeper are really deep PC states that can only be
7657 * reached when all the devices on the system allow it, so even if the graphics
7658 * device allows PC8+, it doesn't mean the system will actually get to these
7659 * states. Our driver only allows PC8+ when going into runtime PM.
7661 * The requirements for PC8+ are that all the outputs are disabled, the power
7662 * well is disabled and most interrupts are disabled, and these are also
7663 * requirements for runtime PM. When these conditions are met, we manually do
7664 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7665 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7668 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7669 * the state of some registers, so when we come back from PC8+ we need to
7670 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7671 * need to take care of the registers kept by RC6. Notice that this happens even
7672 * if we don't put the device in PCI D3 state (which is what currently happens
7673 * because of the runtime PM support).
7675 * For more, read "Display Sequences for Package C8" on the hardware
7678 void hsw_enable_pc8(struct drm_i915_private
*dev_priv
)
7680 struct drm_device
*dev
= dev_priv
->dev
;
7683 DRM_DEBUG_KMS("Enabling package C8+\n");
7685 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
7686 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
7687 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
7688 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
7691 lpt_disable_clkout_dp(dev
);
7692 hsw_disable_lcpll(dev_priv
, true, true);
7695 void hsw_disable_pc8(struct drm_i915_private
*dev_priv
)
7697 struct drm_device
*dev
= dev_priv
->dev
;
7700 DRM_DEBUG_KMS("Disabling package C8+\n");
7702 hsw_restore_lcpll(dev_priv
);
7703 lpt_init_pch_refclk(dev
);
7705 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
7706 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
7707 val
|= PCH_LP_PARTITION_LEVEL_DISABLE
;
7708 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
7711 intel_prepare_ddi(dev
);
7714 static void snb_modeset_global_resources(struct drm_device
*dev
)
7716 modeset_update_crtc_power_domains(dev
);
7719 static void haswell_modeset_global_resources(struct drm_device
*dev
)
7721 modeset_update_crtc_power_domains(dev
);
7724 static int haswell_crtc_mode_set(struct drm_crtc
*crtc
,
7726 struct drm_framebuffer
*fb
)
7728 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7730 if (!intel_ddi_pll_select(intel_crtc
))
7733 intel_crtc
->lowfreq_avail
= false;
7738 static void haswell_get_ddi_pll(struct drm_i915_private
*dev_priv
,
7740 struct intel_crtc_config
*pipe_config
)
7742 pipe_config
->ddi_pll_sel
= I915_READ(PORT_CLK_SEL(port
));
7744 switch (pipe_config
->ddi_pll_sel
) {
7745 case PORT_CLK_SEL_WRPLL1
:
7746 pipe_config
->shared_dpll
= DPLL_ID_WRPLL1
;
7748 case PORT_CLK_SEL_WRPLL2
:
7749 pipe_config
->shared_dpll
= DPLL_ID_WRPLL2
;
7754 static void haswell_get_ddi_port_state(struct intel_crtc
*crtc
,
7755 struct intel_crtc_config
*pipe_config
)
7757 struct drm_device
*dev
= crtc
->base
.dev
;
7758 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7759 struct intel_shared_dpll
*pll
;
7763 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
7765 port
= (tmp
& TRANS_DDI_PORT_MASK
) >> TRANS_DDI_PORT_SHIFT
;
7767 haswell_get_ddi_pll(dev_priv
, port
, pipe_config
);
7769 if (pipe_config
->shared_dpll
>= 0) {
7770 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
7772 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
7773 &pipe_config
->dpll_hw_state
));
7777 * Haswell has only FDI/PCH transcoder A. It is which is connected to
7778 * DDI E. So just check whether this pipe is wired to DDI E and whether
7779 * the PCH transcoder is on.
7781 if ((port
== PORT_E
) && I915_READ(LPT_TRANSCONF
) & TRANS_ENABLE
) {
7782 pipe_config
->has_pch_encoder
= true;
7784 tmp
= I915_READ(FDI_RX_CTL(PIPE_A
));
7785 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
7786 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
7788 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
7792 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
7793 struct intel_crtc_config
*pipe_config
)
7795 struct drm_device
*dev
= crtc
->base
.dev
;
7796 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7797 enum intel_display_power_domain pfit_domain
;
7800 if (!intel_display_power_enabled(dev_priv
,
7801 POWER_DOMAIN_PIPE(crtc
->pipe
)))
7804 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
7805 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
7807 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
7808 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
7809 enum pipe trans_edp_pipe
;
7810 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
7812 WARN(1, "unknown pipe linked to edp transcoder\n");
7813 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
7814 case TRANS_DDI_EDP_INPUT_A_ON
:
7815 trans_edp_pipe
= PIPE_A
;
7817 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
7818 trans_edp_pipe
= PIPE_B
;
7820 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
7821 trans_edp_pipe
= PIPE_C
;
7825 if (trans_edp_pipe
== crtc
->pipe
)
7826 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
7829 if (!intel_display_power_enabled(dev_priv
,
7830 POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
)))
7833 tmp
= I915_READ(PIPECONF(pipe_config
->cpu_transcoder
));
7834 if (!(tmp
& PIPECONF_ENABLE
))
7837 haswell_get_ddi_port_state(crtc
, pipe_config
);
7839 intel_get_pipe_timings(crtc
, pipe_config
);
7841 pfit_domain
= POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
);
7842 if (intel_display_power_enabled(dev_priv
, pfit_domain
))
7843 ironlake_get_pfit_config(crtc
, pipe_config
);
7845 if (IS_HASWELL(dev
))
7846 pipe_config
->ips_enabled
= hsw_crtc_supports_ips(crtc
) &&
7847 (I915_READ(IPS_CTL
) & IPS_ENABLE
);
7849 pipe_config
->pixel_multiplier
= 1;
7857 } hdmi_audio_clock
[] = {
7858 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175
},
7859 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200
}, /* default per bspec */
7860 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000
},
7861 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027
},
7862 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000
},
7863 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054
},
7864 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176
},
7865 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250
},
7866 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352
},
7867 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500
},
7870 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7871 static u32
audio_config_hdmi_pixel_clock(struct drm_display_mode
*mode
)
7875 for (i
= 0; i
< ARRAY_SIZE(hdmi_audio_clock
); i
++) {
7876 if (mode
->clock
== hdmi_audio_clock
[i
].clock
)
7880 if (i
== ARRAY_SIZE(hdmi_audio_clock
)) {
7881 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode
->clock
);
7885 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7886 hdmi_audio_clock
[i
].clock
,
7887 hdmi_audio_clock
[i
].config
);
7889 return hdmi_audio_clock
[i
].config
;
7892 static bool intel_eld_uptodate(struct drm_connector
*connector
,
7893 int reg_eldv
, uint32_t bits_eldv
,
7894 int reg_elda
, uint32_t bits_elda
,
7897 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
7898 uint8_t *eld
= connector
->eld
;
7901 i
= I915_READ(reg_eldv
);
7910 i
= I915_READ(reg_elda
);
7912 I915_WRITE(reg_elda
, i
);
7914 for (i
= 0; i
< eld
[2]; i
++)
7915 if (I915_READ(reg_edid
) != *((uint32_t *)eld
+ i
))
7921 static void g4x_write_eld(struct drm_connector
*connector
,
7922 struct drm_crtc
*crtc
,
7923 struct drm_display_mode
*mode
)
7925 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
7926 uint8_t *eld
= connector
->eld
;
7931 i
= I915_READ(G4X_AUD_VID_DID
);
7933 if (i
== INTEL_AUDIO_DEVBLC
|| i
== INTEL_AUDIO_DEVCL
)
7934 eldv
= G4X_ELDV_DEVCL_DEVBLC
;
7936 eldv
= G4X_ELDV_DEVCTG
;
7938 if (intel_eld_uptodate(connector
,
7939 G4X_AUD_CNTL_ST
, eldv
,
7940 G4X_AUD_CNTL_ST
, G4X_ELD_ADDR
,
7941 G4X_HDMIW_HDMIEDID
))
7944 i
= I915_READ(G4X_AUD_CNTL_ST
);
7945 i
&= ~(eldv
| G4X_ELD_ADDR
);
7946 len
= (i
>> 9) & 0x1f; /* ELD buffer size */
7947 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
7952 len
= min_t(uint8_t, eld
[2], len
);
7953 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
7954 for (i
= 0; i
< len
; i
++)
7955 I915_WRITE(G4X_HDMIW_HDMIEDID
, *((uint32_t *)eld
+ i
));
7957 i
= I915_READ(G4X_AUD_CNTL_ST
);
7959 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
7962 static void haswell_write_eld(struct drm_connector
*connector
,
7963 struct drm_crtc
*crtc
,
7964 struct drm_display_mode
*mode
)
7966 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
7967 uint8_t *eld
= connector
->eld
;
7971 int pipe
= to_intel_crtc(crtc
)->pipe
;
7974 int hdmiw_hdmiedid
= HSW_AUD_EDID_DATA(pipe
);
7975 int aud_cntl_st
= HSW_AUD_DIP_ELD_CTRL(pipe
);
7976 int aud_config
= HSW_AUD_CFG(pipe
);
7977 int aud_cntrl_st2
= HSW_AUD_PIN_ELD_CP_VLD
;
7979 /* Audio output enable */
7980 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7981 tmp
= I915_READ(aud_cntrl_st2
);
7982 tmp
|= (AUDIO_OUTPUT_ENABLE_A
<< (pipe
* 4));
7983 I915_WRITE(aud_cntrl_st2
, tmp
);
7984 POSTING_READ(aud_cntrl_st2
);
7986 assert_pipe_disabled(dev_priv
, to_intel_crtc(crtc
)->pipe
);
7988 /* Set ELD valid state */
7989 tmp
= I915_READ(aud_cntrl_st2
);
7990 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp
);
7991 tmp
|= (AUDIO_ELD_VALID_A
<< (pipe
* 4));
7992 I915_WRITE(aud_cntrl_st2
, tmp
);
7993 tmp
= I915_READ(aud_cntrl_st2
);
7994 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp
);
7996 /* Enable HDMI mode */
7997 tmp
= I915_READ(aud_config
);
7998 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp
);
7999 /* clear N_programing_enable and N_value_index */
8000 tmp
&= ~(AUD_CONFIG_N_VALUE_INDEX
| AUD_CONFIG_N_PROG_ENABLE
);
8001 I915_WRITE(aud_config
, tmp
);
8003 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
8005 eldv
= AUDIO_ELD_VALID_A
<< (pipe
* 4);
8007 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
8008 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
8009 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
8010 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
8012 I915_WRITE(aud_config
, audio_config_hdmi_pixel_clock(mode
));
8015 if (intel_eld_uptodate(connector
,
8016 aud_cntrl_st2
, eldv
,
8017 aud_cntl_st
, IBX_ELD_ADDRESS
,
8021 i
= I915_READ(aud_cntrl_st2
);
8023 I915_WRITE(aud_cntrl_st2
, i
);
8028 i
= I915_READ(aud_cntl_st
);
8029 i
&= ~IBX_ELD_ADDRESS
;
8030 I915_WRITE(aud_cntl_st
, i
);
8031 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
8032 DRM_DEBUG_DRIVER("port num:%d\n", i
);
8034 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
8035 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
8036 for (i
= 0; i
< len
; i
++)
8037 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
8039 i
= I915_READ(aud_cntrl_st2
);
8041 I915_WRITE(aud_cntrl_st2
, i
);
8045 static void ironlake_write_eld(struct drm_connector
*connector
,
8046 struct drm_crtc
*crtc
,
8047 struct drm_display_mode
*mode
)
8049 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
8050 uint8_t *eld
= connector
->eld
;
8058 int pipe
= to_intel_crtc(crtc
)->pipe
;
8060 if (HAS_PCH_IBX(connector
->dev
)) {
8061 hdmiw_hdmiedid
= IBX_HDMIW_HDMIEDID(pipe
);
8062 aud_config
= IBX_AUD_CFG(pipe
);
8063 aud_cntl_st
= IBX_AUD_CNTL_ST(pipe
);
8064 aud_cntrl_st2
= IBX_AUD_CNTL_ST2
;
8065 } else if (IS_VALLEYVIEW(connector
->dev
)) {
8066 hdmiw_hdmiedid
= VLV_HDMIW_HDMIEDID(pipe
);
8067 aud_config
= VLV_AUD_CFG(pipe
);
8068 aud_cntl_st
= VLV_AUD_CNTL_ST(pipe
);
8069 aud_cntrl_st2
= VLV_AUD_CNTL_ST2
;
8071 hdmiw_hdmiedid
= CPT_HDMIW_HDMIEDID(pipe
);
8072 aud_config
= CPT_AUD_CFG(pipe
);
8073 aud_cntl_st
= CPT_AUD_CNTL_ST(pipe
);
8074 aud_cntrl_st2
= CPT_AUD_CNTRL_ST2
;
8077 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
8079 if (IS_VALLEYVIEW(connector
->dev
)) {
8080 struct intel_encoder
*intel_encoder
;
8081 struct intel_digital_port
*intel_dig_port
;
8083 intel_encoder
= intel_attached_encoder(connector
);
8084 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
8085 i
= intel_dig_port
->port
;
8087 i
= I915_READ(aud_cntl_st
);
8088 i
= (i
>> 29) & DIP_PORT_SEL_MASK
;
8089 /* DIP_Port_Select, 0x1 = PortB */
8093 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
8094 /* operate blindly on all ports */
8095 eldv
= IBX_ELD_VALIDB
;
8096 eldv
|= IBX_ELD_VALIDB
<< 4;
8097 eldv
|= IBX_ELD_VALIDB
<< 8;
8099 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i
));
8100 eldv
= IBX_ELD_VALIDB
<< ((i
- 1) * 4);
8103 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
8104 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
8105 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
8106 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
8108 I915_WRITE(aud_config
, audio_config_hdmi_pixel_clock(mode
));
8111 if (intel_eld_uptodate(connector
,
8112 aud_cntrl_st2
, eldv
,
8113 aud_cntl_st
, IBX_ELD_ADDRESS
,
8117 i
= I915_READ(aud_cntrl_st2
);
8119 I915_WRITE(aud_cntrl_st2
, i
);
8124 i
= I915_READ(aud_cntl_st
);
8125 i
&= ~IBX_ELD_ADDRESS
;
8126 I915_WRITE(aud_cntl_st
, i
);
8128 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
8129 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
8130 for (i
= 0; i
< len
; i
++)
8131 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
8133 i
= I915_READ(aud_cntrl_st2
);
8135 I915_WRITE(aud_cntrl_st2
, i
);
8138 void intel_write_eld(struct drm_encoder
*encoder
,
8139 struct drm_display_mode
*mode
)
8141 struct drm_crtc
*crtc
= encoder
->crtc
;
8142 struct drm_connector
*connector
;
8143 struct drm_device
*dev
= encoder
->dev
;
8144 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8146 connector
= drm_select_eld(encoder
, mode
);
8150 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8153 connector
->encoder
->base
.id
,
8154 connector
->encoder
->name
);
8156 connector
->eld
[6] = drm_av_sync_delay(connector
, mode
) / 2;
8158 if (dev_priv
->display
.write_eld
)
8159 dev_priv
->display
.write_eld(connector
, crtc
, mode
);
8162 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
8164 struct drm_device
*dev
= crtc
->dev
;
8165 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8166 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8167 uint32_t cntl
= 0, size
= 0;
8170 unsigned int width
= intel_crtc
->cursor_width
;
8171 unsigned int height
= intel_crtc
->cursor_height
;
8172 unsigned int stride
= roundup_pow_of_two(width
) * 4;
8176 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8187 cntl
|= CURSOR_ENABLE
|
8188 CURSOR_GAMMA_ENABLE
|
8189 CURSOR_FORMAT_ARGB
|
8190 CURSOR_STRIDE(stride
);
8192 size
= (height
<< 12) | width
;
8195 if (intel_crtc
->cursor_cntl
!= 0 &&
8196 (intel_crtc
->cursor_base
!= base
||
8197 intel_crtc
->cursor_size
!= size
||
8198 intel_crtc
->cursor_cntl
!= cntl
)) {
8199 /* On these chipsets we can only modify the base/size/stride
8200 * whilst the cursor is disabled.
8202 I915_WRITE(_CURACNTR
, 0);
8203 POSTING_READ(_CURACNTR
);
8204 intel_crtc
->cursor_cntl
= 0;
8207 if (intel_crtc
->cursor_base
!= base
) {
8208 I915_WRITE(_CURABASE
, base
);
8209 intel_crtc
->cursor_base
= base
;
8212 if (intel_crtc
->cursor_size
!= size
) {
8213 I915_WRITE(CURSIZE
, size
);
8214 intel_crtc
->cursor_size
= size
;
8217 if (intel_crtc
->cursor_cntl
!= cntl
) {
8218 I915_WRITE(_CURACNTR
, cntl
);
8219 POSTING_READ(_CURACNTR
);
8220 intel_crtc
->cursor_cntl
= cntl
;
8224 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
8226 struct drm_device
*dev
= crtc
->dev
;
8227 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8228 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8229 int pipe
= intel_crtc
->pipe
;
8234 cntl
= MCURSOR_GAMMA_ENABLE
;
8235 switch (intel_crtc
->cursor_width
) {
8237 cntl
|= CURSOR_MODE_64_ARGB_AX
;
8240 cntl
|= CURSOR_MODE_128_ARGB_AX
;
8243 cntl
|= CURSOR_MODE_256_ARGB_AX
;
8249 cntl
|= pipe
<< 28; /* Connect to correct pipe */
8251 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
8252 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
8255 if (intel_crtc
->cursor_cntl
!= cntl
) {
8256 I915_WRITE(CURCNTR(pipe
), cntl
);
8257 POSTING_READ(CURCNTR(pipe
));
8258 intel_crtc
->cursor_cntl
= cntl
;
8261 /* and commit changes on next vblank */
8262 I915_WRITE(CURBASE(pipe
), base
);
8263 POSTING_READ(CURBASE(pipe
));
8265 intel_crtc
->cursor_base
= base
;
8268 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8269 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
8272 struct drm_device
*dev
= crtc
->dev
;
8273 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8274 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8275 int pipe
= intel_crtc
->pipe
;
8276 int x
= crtc
->cursor_x
;
8277 int y
= crtc
->cursor_y
;
8278 u32 base
= 0, pos
= 0;
8281 base
= intel_crtc
->cursor_addr
;
8283 if (x
>= intel_crtc
->config
.pipe_src_w
)
8286 if (y
>= intel_crtc
->config
.pipe_src_h
)
8290 if (x
+ intel_crtc
->cursor_width
<= 0)
8293 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
8296 pos
|= x
<< CURSOR_X_SHIFT
;
8299 if (y
+ intel_crtc
->cursor_height
<= 0)
8302 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
8305 pos
|= y
<< CURSOR_Y_SHIFT
;
8307 if (base
== 0 && intel_crtc
->cursor_base
== 0)
8310 I915_WRITE(CURPOS(pipe
), pos
);
8312 if (IS_845G(dev
) || IS_I865G(dev
))
8313 i845_update_cursor(crtc
, base
);
8315 i9xx_update_cursor(crtc
, base
);
8318 static bool cursor_size_ok(struct drm_device
*dev
,
8319 uint32_t width
, uint32_t height
)
8321 if (width
== 0 || height
== 0)
8325 * 845g/865g are special in that they are only limited by
8326 * the width of their cursors, the height is arbitrary up to
8327 * the precision of the register. Everything else requires
8328 * square cursors, limited to a few power-of-two sizes.
8330 if (IS_845G(dev
) || IS_I865G(dev
)) {
8331 if ((width
& 63) != 0)
8334 if (width
> (IS_845G(dev
) ? 64 : 512))
8340 switch (width
| height
) {
8356 * intel_crtc_cursor_set_obj - Set cursor to specified GEM object
8358 * Note that the object's reference will be consumed if the update fails. If
8359 * the update succeeds, the reference of the old object (if any) will be
8362 static int intel_crtc_cursor_set_obj(struct drm_crtc
*crtc
,
8363 struct drm_i915_gem_object
*obj
,
8364 uint32_t width
, uint32_t height
)
8366 struct drm_device
*dev
= crtc
->dev
;
8367 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8368 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8369 enum pipe pipe
= intel_crtc
->pipe
;
8370 unsigned old_width
, stride
;
8374 /* if we want to turn off the cursor ignore width and height */
8376 DRM_DEBUG_KMS("cursor off\n");
8378 mutex_lock(&dev
->struct_mutex
);
8382 /* Check for which cursor types we support */
8383 if (!cursor_size_ok(dev
, width
, height
)) {
8384 DRM_DEBUG("Cursor dimension not supported\n");
8388 stride
= roundup_pow_of_two(width
) * 4;
8389 if (obj
->base
.size
< stride
* height
) {
8390 DRM_DEBUG_KMS("buffer is too small\n");
8395 /* we only need to pin inside GTT if cursor is non-phy */
8396 mutex_lock(&dev
->struct_mutex
);
8397 if (!INTEL_INFO(dev
)->cursor_needs_physical
) {
8400 if (obj
->tiling_mode
) {
8401 DRM_DEBUG_KMS("cursor cannot be tiled\n");
8407 * Global gtt pte registers are special registers which actually
8408 * forward writes to a chunk of system memory. Which means that
8409 * there is no risk that the register values disappear as soon
8410 * as we call intel_runtime_pm_put(), so it is correct to wrap
8411 * only the pin/unpin/fence and not more.
8413 intel_runtime_pm_get(dev_priv
);
8415 /* Note that the w/a also requires 2 PTE of padding following
8416 * the bo. We currently fill all unused PTE with the shadow
8417 * page and so we should always have valid PTE following the
8418 * cursor preventing the VT-d warning.
8421 if (need_vtd_wa(dev
))
8422 alignment
= 64*1024;
8424 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, NULL
);
8426 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8427 intel_runtime_pm_put(dev_priv
);
8431 ret
= i915_gem_object_put_fence(obj
);
8433 DRM_DEBUG_KMS("failed to release fence for cursor");
8434 intel_runtime_pm_put(dev_priv
);
8438 addr
= i915_gem_obj_ggtt_offset(obj
);
8440 intel_runtime_pm_put(dev_priv
);
8442 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
8443 ret
= i915_gem_object_attach_phys(obj
, align
);
8445 DRM_DEBUG_KMS("failed to attach phys object\n");
8448 addr
= obj
->phys_handle
->busaddr
;
8452 if (intel_crtc
->cursor_bo
) {
8453 if (!INTEL_INFO(dev
)->cursor_needs_physical
)
8454 i915_gem_object_unpin_from_display_plane(intel_crtc
->cursor_bo
);
8457 i915_gem_track_fb(intel_crtc
->cursor_bo
, obj
,
8458 INTEL_FRONTBUFFER_CURSOR(pipe
));
8459 mutex_unlock(&dev
->struct_mutex
);
8461 old_width
= intel_crtc
->cursor_width
;
8463 intel_crtc
->cursor_addr
= addr
;
8464 intel_crtc
->cursor_bo
= obj
;
8465 intel_crtc
->cursor_width
= width
;
8466 intel_crtc
->cursor_height
= height
;
8468 if (intel_crtc
->active
) {
8469 if (old_width
!= width
)
8470 intel_update_watermarks(crtc
);
8471 intel_crtc_update_cursor(crtc
, intel_crtc
->cursor_bo
!= NULL
);
8474 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_CURSOR(pipe
));
8478 i915_gem_object_unpin_from_display_plane(obj
);
8480 mutex_unlock(&dev
->struct_mutex
);
8482 drm_gem_object_unreference_unlocked(&obj
->base
);
8486 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
8487 u16
*blue
, uint32_t start
, uint32_t size
)
8489 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
8490 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8492 for (i
= start
; i
< end
; i
++) {
8493 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
8494 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
8495 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
8498 intel_crtc_load_lut(crtc
);
8501 /* VESA 640x480x72Hz mode to set on the pipe */
8502 static struct drm_display_mode load_detect_mode
= {
8503 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
8504 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
8507 struct drm_framebuffer
*
8508 __intel_framebuffer_create(struct drm_device
*dev
,
8509 struct drm_mode_fb_cmd2
*mode_cmd
,
8510 struct drm_i915_gem_object
*obj
)
8512 struct intel_framebuffer
*intel_fb
;
8515 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
8517 drm_gem_object_unreference_unlocked(&obj
->base
);
8518 return ERR_PTR(-ENOMEM
);
8521 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
8525 return &intel_fb
->base
;
8527 drm_gem_object_unreference_unlocked(&obj
->base
);
8530 return ERR_PTR(ret
);
8533 static struct drm_framebuffer
*
8534 intel_framebuffer_create(struct drm_device
*dev
,
8535 struct drm_mode_fb_cmd2
*mode_cmd
,
8536 struct drm_i915_gem_object
*obj
)
8538 struct drm_framebuffer
*fb
;
8541 ret
= i915_mutex_lock_interruptible(dev
);
8543 return ERR_PTR(ret
);
8544 fb
= __intel_framebuffer_create(dev
, mode_cmd
, obj
);
8545 mutex_unlock(&dev
->struct_mutex
);
8551 intel_framebuffer_pitch_for_width(int width
, int bpp
)
8553 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
8554 return ALIGN(pitch
, 64);
8558 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
8560 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
8561 return PAGE_ALIGN(pitch
* mode
->vdisplay
);
8564 static struct drm_framebuffer
*
8565 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
8566 struct drm_display_mode
*mode
,
8569 struct drm_i915_gem_object
*obj
;
8570 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
8572 obj
= i915_gem_alloc_object(dev
,
8573 intel_framebuffer_size_for_mode(mode
, bpp
));
8575 return ERR_PTR(-ENOMEM
);
8577 mode_cmd
.width
= mode
->hdisplay
;
8578 mode_cmd
.height
= mode
->vdisplay
;
8579 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
8581 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
8583 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
8586 static struct drm_framebuffer
*
8587 mode_fits_in_fbdev(struct drm_device
*dev
,
8588 struct drm_display_mode
*mode
)
8590 #ifdef CONFIG_DRM_I915_FBDEV
8591 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8592 struct drm_i915_gem_object
*obj
;
8593 struct drm_framebuffer
*fb
;
8595 if (!dev_priv
->fbdev
)
8598 if (!dev_priv
->fbdev
->fb
)
8601 obj
= dev_priv
->fbdev
->fb
->obj
;
8604 fb
= &dev_priv
->fbdev
->fb
->base
;
8605 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
8606 fb
->bits_per_pixel
))
8609 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
8618 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
8619 struct drm_display_mode
*mode
,
8620 struct intel_load_detect_pipe
*old
,
8621 struct drm_modeset_acquire_ctx
*ctx
)
8623 struct intel_crtc
*intel_crtc
;
8624 struct intel_encoder
*intel_encoder
=
8625 intel_attached_encoder(connector
);
8626 struct drm_crtc
*possible_crtc
;
8627 struct drm_encoder
*encoder
= &intel_encoder
->base
;
8628 struct drm_crtc
*crtc
= NULL
;
8629 struct drm_device
*dev
= encoder
->dev
;
8630 struct drm_framebuffer
*fb
;
8631 struct drm_mode_config
*config
= &dev
->mode_config
;
8634 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8635 connector
->base
.id
, connector
->name
,
8636 encoder
->base
.id
, encoder
->name
);
8639 ret
= drm_modeset_lock(&config
->connection_mutex
, ctx
);
8644 * Algorithm gets a little messy:
8646 * - if the connector already has an assigned crtc, use it (but make
8647 * sure it's on first)
8649 * - try to find the first unused crtc that can drive this connector,
8650 * and use that if we find one
8653 /* See if we already have a CRTC for this connector */
8654 if (encoder
->crtc
) {
8655 crtc
= encoder
->crtc
;
8657 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
8661 old
->dpms_mode
= connector
->dpms
;
8662 old
->load_detect_temp
= false;
8664 /* Make sure the crtc and connector are running */
8665 if (connector
->dpms
!= DRM_MODE_DPMS_ON
)
8666 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
8671 /* Find an unused one (if possible) */
8672 for_each_crtc(dev
, possible_crtc
) {
8674 if (!(encoder
->possible_crtcs
& (1 << i
)))
8676 if (possible_crtc
->enabled
)
8678 /* This can occur when applying the pipe A quirk on resume. */
8679 if (to_intel_crtc(possible_crtc
)->new_enabled
)
8682 crtc
= possible_crtc
;
8687 * If we didn't find an unused CRTC, don't use any.
8690 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8694 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
8697 intel_encoder
->new_crtc
= to_intel_crtc(crtc
);
8698 to_intel_connector(connector
)->new_encoder
= intel_encoder
;
8700 intel_crtc
= to_intel_crtc(crtc
);
8701 intel_crtc
->new_enabled
= true;
8702 intel_crtc
->new_config
= &intel_crtc
->config
;
8703 old
->dpms_mode
= connector
->dpms
;
8704 old
->load_detect_temp
= true;
8705 old
->release_fb
= NULL
;
8708 mode
= &load_detect_mode
;
8710 /* We need a framebuffer large enough to accommodate all accesses
8711 * that the plane may generate whilst we perform load detection.
8712 * We can not rely on the fbcon either being present (we get called
8713 * during its initialisation to detect all boot displays, or it may
8714 * not even exist) or that it is large enough to satisfy the
8717 fb
= mode_fits_in_fbdev(dev
, mode
);
8719 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8720 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
8721 old
->release_fb
= fb
;
8723 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8725 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8729 if (intel_set_mode(crtc
, mode
, 0, 0, fb
)) {
8730 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8731 if (old
->release_fb
)
8732 old
->release_fb
->funcs
->destroy(old
->release_fb
);
8736 /* let the connector get through one full cycle before testing */
8737 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
8741 intel_crtc
->new_enabled
= crtc
->enabled
;
8742 if (intel_crtc
->new_enabled
)
8743 intel_crtc
->new_config
= &intel_crtc
->config
;
8745 intel_crtc
->new_config
= NULL
;
8747 if (ret
== -EDEADLK
) {
8748 drm_modeset_backoff(ctx
);
8755 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
8756 struct intel_load_detect_pipe
*old
)
8758 struct intel_encoder
*intel_encoder
=
8759 intel_attached_encoder(connector
);
8760 struct drm_encoder
*encoder
= &intel_encoder
->base
;
8761 struct drm_crtc
*crtc
= encoder
->crtc
;
8762 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8764 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8765 connector
->base
.id
, connector
->name
,
8766 encoder
->base
.id
, encoder
->name
);
8768 if (old
->load_detect_temp
) {
8769 to_intel_connector(connector
)->new_encoder
= NULL
;
8770 intel_encoder
->new_crtc
= NULL
;
8771 intel_crtc
->new_enabled
= false;
8772 intel_crtc
->new_config
= NULL
;
8773 intel_set_mode(crtc
, NULL
, 0, 0, NULL
);
8775 if (old
->release_fb
) {
8776 drm_framebuffer_unregister_private(old
->release_fb
);
8777 drm_framebuffer_unreference(old
->release_fb
);
8783 /* Switch crtc and encoder back off if necessary */
8784 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
)
8785 connector
->funcs
->dpms(connector
, old
->dpms_mode
);
8788 static int i9xx_pll_refclk(struct drm_device
*dev
,
8789 const struct intel_crtc_config
*pipe_config
)
8791 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8792 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
8794 if ((dpll
& PLL_REF_INPUT_MASK
) == PLLB_REF_INPUT_SPREADSPECTRUMIN
)
8795 return dev_priv
->vbt
.lvds_ssc_freq
;
8796 else if (HAS_PCH_SPLIT(dev
))
8798 else if (!IS_GEN2(dev
))
8804 /* Returns the clock of the currently programmed mode of the given pipe. */
8805 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
8806 struct intel_crtc_config
*pipe_config
)
8808 struct drm_device
*dev
= crtc
->base
.dev
;
8809 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8810 int pipe
= pipe_config
->cpu_transcoder
;
8811 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
8813 intel_clock_t clock
;
8814 int refclk
= i9xx_pll_refclk(dev
, pipe_config
);
8816 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
8817 fp
= pipe_config
->dpll_hw_state
.fp0
;
8819 fp
= pipe_config
->dpll_hw_state
.fp1
;
8821 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
8822 if (IS_PINEVIEW(dev
)) {
8823 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
8824 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
8826 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
8827 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
8830 if (!IS_GEN2(dev
)) {
8831 if (IS_PINEVIEW(dev
))
8832 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
8833 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
8835 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
8836 DPLL_FPA01_P1_POST_DIV_SHIFT
);
8838 switch (dpll
& DPLL_MODE_MASK
) {
8839 case DPLLB_MODE_DAC_SERIAL
:
8840 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
8843 case DPLLB_MODE_LVDS
:
8844 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
8848 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8849 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
8853 if (IS_PINEVIEW(dev
))
8854 pineview_clock(refclk
, &clock
);
8856 i9xx_clock(refclk
, &clock
);
8858 u32 lvds
= IS_I830(dev
) ? 0 : I915_READ(LVDS
);
8859 bool is_lvds
= (pipe
== 1) && (lvds
& LVDS_PORT_EN
);
8862 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
8863 DPLL_FPA01_P1_POST_DIV_SHIFT
);
8865 if (lvds
& LVDS_CLKB_POWER_UP
)
8870 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
8873 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
8874 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
8876 if (dpll
& PLL_P2_DIVIDE_BY_4
)
8882 i9xx_clock(refclk
, &clock
);
8886 * This value includes pixel_multiplier. We will use
8887 * port_clock to compute adjusted_mode.crtc_clock in the
8888 * encoder's get_config() function.
8890 pipe_config
->port_clock
= clock
.dot
;
8893 int intel_dotclock_calculate(int link_freq
,
8894 const struct intel_link_m_n
*m_n
)
8897 * The calculation for the data clock is:
8898 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8899 * But we want to avoid losing precison if possible, so:
8900 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8902 * and the link clock is simpler:
8903 * link_clock = (m * link_clock) / n
8909 return div_u64((u64
)m_n
->link_m
* link_freq
, m_n
->link_n
);
8912 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
8913 struct intel_crtc_config
*pipe_config
)
8915 struct drm_device
*dev
= crtc
->base
.dev
;
8917 /* read out port_clock from the DPLL */
8918 i9xx_crtc_clock_get(crtc
, pipe_config
);
8921 * This value does not include pixel_multiplier.
8922 * We will check that port_clock and adjusted_mode.crtc_clock
8923 * agree once we know their relationship in the encoder's
8924 * get_config() function.
8926 pipe_config
->adjusted_mode
.crtc_clock
=
8927 intel_dotclock_calculate(intel_fdi_link_freq(dev
) * 10000,
8928 &pipe_config
->fdi_m_n
);
8931 /** Returns the currently programmed mode of the given pipe. */
8932 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
8933 struct drm_crtc
*crtc
)
8935 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8936 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8937 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
8938 struct drm_display_mode
*mode
;
8939 struct intel_crtc_config pipe_config
;
8940 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
8941 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
8942 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
8943 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
8944 enum pipe pipe
= intel_crtc
->pipe
;
8946 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
8951 * Construct a pipe_config sufficient for getting the clock info
8952 * back out of crtc_clock_get.
8954 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8955 * to use a real value here instead.
8957 pipe_config
.cpu_transcoder
= (enum transcoder
) pipe
;
8958 pipe_config
.pixel_multiplier
= 1;
8959 pipe_config
.dpll_hw_state
.dpll
= I915_READ(DPLL(pipe
));
8960 pipe_config
.dpll_hw_state
.fp0
= I915_READ(FP0(pipe
));
8961 pipe_config
.dpll_hw_state
.fp1
= I915_READ(FP1(pipe
));
8962 i9xx_crtc_clock_get(intel_crtc
, &pipe_config
);
8964 mode
->clock
= pipe_config
.port_clock
/ pipe_config
.pixel_multiplier
;
8965 mode
->hdisplay
= (htot
& 0xffff) + 1;
8966 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
8967 mode
->hsync_start
= (hsync
& 0xffff) + 1;
8968 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
8969 mode
->vdisplay
= (vtot
& 0xffff) + 1;
8970 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
8971 mode
->vsync_start
= (vsync
& 0xffff) + 1;
8972 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
8974 drm_mode_set_name(mode
);
8979 static void intel_increase_pllclock(struct drm_device
*dev
,
8982 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8983 int dpll_reg
= DPLL(pipe
);
8986 if (!HAS_GMCH_DISPLAY(dev
))
8989 if (!dev_priv
->lvds_downclock_avail
)
8992 dpll
= I915_READ(dpll_reg
);
8993 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
8994 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8996 assert_panel_unlocked(dev_priv
, pipe
);
8998 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
8999 I915_WRITE(dpll_reg
, dpll
);
9000 intel_wait_for_vblank(dev
, pipe
);
9002 dpll
= I915_READ(dpll_reg
);
9003 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
9004 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
9008 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
9010 struct drm_device
*dev
= crtc
->dev
;
9011 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9012 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9014 if (!HAS_GMCH_DISPLAY(dev
))
9017 if (!dev_priv
->lvds_downclock_avail
)
9021 * Since this is called by a timer, we should never get here in
9024 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
9025 int pipe
= intel_crtc
->pipe
;
9026 int dpll_reg
= DPLL(pipe
);
9029 DRM_DEBUG_DRIVER("downclocking LVDS\n");
9031 assert_panel_unlocked(dev_priv
, pipe
);
9033 dpll
= I915_READ(dpll_reg
);
9034 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
9035 I915_WRITE(dpll_reg
, dpll
);
9036 intel_wait_for_vblank(dev
, pipe
);
9037 dpll
= I915_READ(dpll_reg
);
9038 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
9039 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
9044 void intel_mark_busy(struct drm_device
*dev
)
9046 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9048 if (dev_priv
->mm
.busy
)
9051 intel_runtime_pm_get(dev_priv
);
9052 i915_update_gfx_val(dev_priv
);
9053 dev_priv
->mm
.busy
= true;
9056 void intel_mark_idle(struct drm_device
*dev
)
9058 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9059 struct drm_crtc
*crtc
;
9061 if (!dev_priv
->mm
.busy
)
9064 dev_priv
->mm
.busy
= false;
9066 if (!i915
.powersave
)
9069 for_each_crtc(dev
, crtc
) {
9070 if (!crtc
->primary
->fb
)
9073 intel_decrease_pllclock(crtc
);
9076 if (INTEL_INFO(dev
)->gen
>= 6)
9077 gen6_rps_idle(dev
->dev_private
);
9080 intel_runtime_pm_put(dev_priv
);
9085 * intel_mark_fb_busy - mark given planes as busy
9087 * @frontbuffer_bits: bits for the affected planes
9088 * @ring: optional ring for asynchronous commands
9090 * This function gets called every time the screen contents change. It can be
9091 * used to keep e.g. the update rate at the nominal refresh rate with DRRS.
9093 static void intel_mark_fb_busy(struct drm_device
*dev
,
9094 unsigned frontbuffer_bits
,
9095 struct intel_engine_cs
*ring
)
9097 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9100 if (!i915
.powersave
)
9103 for_each_pipe(dev_priv
, pipe
) {
9104 if (!(frontbuffer_bits
& INTEL_FRONTBUFFER_ALL_MASK(pipe
)))
9107 intel_increase_pllclock(dev
, pipe
);
9108 if (ring
&& intel_fbc_enabled(dev
))
9109 ring
->fbc_dirty
= true;
9114 * intel_fb_obj_invalidate - invalidate frontbuffer object
9115 * @obj: GEM object to invalidate
9116 * @ring: set for asynchronous rendering
9118 * This function gets called every time rendering on the given object starts and
9119 * frontbuffer caching (fbc, low refresh rate for DRRS, panel self refresh) must
9120 * be invalidated. If @ring is non-NULL any subsequent invalidation will be delayed
9121 * until the rendering completes or a flip on this frontbuffer plane is
9124 void intel_fb_obj_invalidate(struct drm_i915_gem_object
*obj
,
9125 struct intel_engine_cs
*ring
)
9127 struct drm_device
*dev
= obj
->base
.dev
;
9128 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9130 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
9132 if (!obj
->frontbuffer_bits
)
9136 mutex_lock(&dev_priv
->fb_tracking
.lock
);
9137 dev_priv
->fb_tracking
.busy_bits
9138 |= obj
->frontbuffer_bits
;
9139 dev_priv
->fb_tracking
.flip_bits
9140 &= ~obj
->frontbuffer_bits
;
9141 mutex_unlock(&dev_priv
->fb_tracking
.lock
);
9144 intel_mark_fb_busy(dev
, obj
->frontbuffer_bits
, ring
);
9146 intel_edp_psr_invalidate(dev
, obj
->frontbuffer_bits
);
9150 * intel_frontbuffer_flush - flush frontbuffer
9152 * @frontbuffer_bits: frontbuffer plane tracking bits
9154 * This function gets called every time rendering on the given planes has
9155 * completed and frontbuffer caching can be started again. Flushes will get
9156 * delayed if they're blocked by some oustanding asynchronous rendering.
9158 * Can be called without any locks held.
9160 void intel_frontbuffer_flush(struct drm_device
*dev
,
9161 unsigned frontbuffer_bits
)
9163 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9165 /* Delay flushing when rings are still busy.*/
9166 mutex_lock(&dev_priv
->fb_tracking
.lock
);
9167 frontbuffer_bits
&= ~dev_priv
->fb_tracking
.busy_bits
;
9168 mutex_unlock(&dev_priv
->fb_tracking
.lock
);
9170 intel_mark_fb_busy(dev
, frontbuffer_bits
, NULL
);
9172 intel_edp_psr_flush(dev
, frontbuffer_bits
);
9175 * FIXME: Unconditional fbc flushing here is a rather gross hack and
9176 * needs to be reworked into a proper frontbuffer tracking scheme like
9179 if (IS_BROADWELL(dev
))
9180 gen8_fbc_sw_flush(dev
, FBC_REND_CACHE_CLEAN
);
9184 * intel_fb_obj_flush - flush frontbuffer object
9185 * @obj: GEM object to flush
9186 * @retire: set when retiring asynchronous rendering
9188 * This function gets called every time rendering on the given object has
9189 * completed and frontbuffer caching can be started again. If @retire is true
9190 * then any delayed flushes will be unblocked.
9192 void intel_fb_obj_flush(struct drm_i915_gem_object
*obj
,
9195 struct drm_device
*dev
= obj
->base
.dev
;
9196 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9197 unsigned frontbuffer_bits
;
9199 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
9201 if (!obj
->frontbuffer_bits
)
9204 frontbuffer_bits
= obj
->frontbuffer_bits
;
9207 mutex_lock(&dev_priv
->fb_tracking
.lock
);
9208 /* Filter out new bits since rendering started. */
9209 frontbuffer_bits
&= dev_priv
->fb_tracking
.busy_bits
;
9211 dev_priv
->fb_tracking
.busy_bits
&= ~frontbuffer_bits
;
9212 mutex_unlock(&dev_priv
->fb_tracking
.lock
);
9215 intel_frontbuffer_flush(dev
, frontbuffer_bits
);
9219 * intel_frontbuffer_flip_prepare - prepare asnychronous frontbuffer flip
9221 * @frontbuffer_bits: frontbuffer plane tracking bits
9223 * This function gets called after scheduling a flip on @obj. The actual
9224 * frontbuffer flushing will be delayed until completion is signalled with
9225 * intel_frontbuffer_flip_complete. If an invalidate happens in between this
9226 * flush will be cancelled.
9228 * Can be called without any locks held.
9230 void intel_frontbuffer_flip_prepare(struct drm_device
*dev
,
9231 unsigned frontbuffer_bits
)
9233 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9235 mutex_lock(&dev_priv
->fb_tracking
.lock
);
9236 dev_priv
->fb_tracking
.flip_bits
9237 |= frontbuffer_bits
;
9238 mutex_unlock(&dev_priv
->fb_tracking
.lock
);
9242 * intel_frontbuffer_flip_complete - complete asynchronous frontbuffer flush
9244 * @frontbuffer_bits: frontbuffer plane tracking bits
9246 * This function gets called after the flip has been latched and will complete
9247 * on the next vblank. It will execute the fush if it hasn't been cancalled yet.
9249 * Can be called without any locks held.
9251 void intel_frontbuffer_flip_complete(struct drm_device
*dev
,
9252 unsigned frontbuffer_bits
)
9254 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9256 mutex_lock(&dev_priv
->fb_tracking
.lock
);
9257 /* Mask any cancelled flips. */
9258 frontbuffer_bits
&= dev_priv
->fb_tracking
.flip_bits
;
9259 dev_priv
->fb_tracking
.flip_bits
&= ~frontbuffer_bits
;
9260 mutex_unlock(&dev_priv
->fb_tracking
.lock
);
9262 intel_frontbuffer_flush(dev
, frontbuffer_bits
);
9265 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
9267 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9268 struct drm_device
*dev
= crtc
->dev
;
9269 struct intel_unpin_work
*work
;
9270 unsigned long flags
;
9272 spin_lock_irqsave(&dev
->event_lock
, flags
);
9273 work
= intel_crtc
->unpin_work
;
9274 intel_crtc
->unpin_work
= NULL
;
9275 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9278 cancel_work_sync(&work
->work
);
9282 drm_crtc_cleanup(crtc
);
9287 static void intel_unpin_work_fn(struct work_struct
*__work
)
9289 struct intel_unpin_work
*work
=
9290 container_of(__work
, struct intel_unpin_work
, work
);
9291 struct drm_device
*dev
= work
->crtc
->dev
;
9292 enum pipe pipe
= to_intel_crtc(work
->crtc
)->pipe
;
9294 mutex_lock(&dev
->struct_mutex
);
9295 intel_unpin_fb_obj(work
->old_fb_obj
);
9296 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
9297 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
9299 intel_update_fbc(dev
);
9300 mutex_unlock(&dev
->struct_mutex
);
9302 intel_frontbuffer_flip_complete(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
9304 BUG_ON(atomic_read(&to_intel_crtc(work
->crtc
)->unpin_work_count
) == 0);
9305 atomic_dec(&to_intel_crtc(work
->crtc
)->unpin_work_count
);
9310 static void do_intel_finish_page_flip(struct drm_device
*dev
,
9311 struct drm_crtc
*crtc
)
9313 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9314 struct intel_unpin_work
*work
;
9315 unsigned long flags
;
9317 /* Ignore early vblank irqs */
9318 if (intel_crtc
== NULL
)
9321 spin_lock_irqsave(&dev
->event_lock
, flags
);
9322 work
= intel_crtc
->unpin_work
;
9324 /* Ensure we don't miss a work->pending update ... */
9327 if (work
== NULL
|| atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
9328 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9332 page_flip_completed(intel_crtc
);
9334 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9337 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
9339 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9340 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
9342 do_intel_finish_page_flip(dev
, crtc
);
9345 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
9347 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9348 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
9350 do_intel_finish_page_flip(dev
, crtc
);
9353 /* Is 'a' after or equal to 'b'? */
9354 static bool g4x_flip_count_after_eq(u32 a
, u32 b
)
9356 return !((a
- b
) & 0x80000000);
9359 static bool page_flip_finished(struct intel_crtc
*crtc
)
9361 struct drm_device
*dev
= crtc
->base
.dev
;
9362 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9365 * The relevant registers doen't exist on pre-ctg.
9366 * As the flip done interrupt doesn't trigger for mmio
9367 * flips on gmch platforms, a flip count check isn't
9368 * really needed there. But since ctg has the registers,
9369 * include it in the check anyway.
9371 if (INTEL_INFO(dev
)->gen
< 5 && !IS_G4X(dev
))
9375 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9376 * used the same base address. In that case the mmio flip might
9377 * have completed, but the CS hasn't even executed the flip yet.
9379 * A flip count check isn't enough as the CS might have updated
9380 * the base address just after start of vblank, but before we
9381 * managed to process the interrupt. This means we'd complete the
9384 * Combining both checks should get us a good enough result. It may
9385 * still happen that the CS flip has been executed, but has not
9386 * yet actually completed. But in case the base address is the same
9387 * anyway, we don't really care.
9389 return (I915_READ(DSPSURFLIVE(crtc
->plane
)) & ~0xfff) ==
9390 crtc
->unpin_work
->gtt_offset
&&
9391 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc
->pipe
)),
9392 crtc
->unpin_work
->flip_count
);
9395 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
9397 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9398 struct intel_crtc
*intel_crtc
=
9399 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
9400 unsigned long flags
;
9402 /* NB: An MMIO update of the plane base pointer will also
9403 * generate a page-flip completion irq, i.e. every modeset
9404 * is also accompanied by a spurious intel_prepare_page_flip().
9406 spin_lock_irqsave(&dev
->event_lock
, flags
);
9407 if (intel_crtc
->unpin_work
&& page_flip_finished(intel_crtc
))
9408 atomic_inc_not_zero(&intel_crtc
->unpin_work
->pending
);
9409 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9412 static inline void intel_mark_page_flip_active(struct intel_crtc
*intel_crtc
)
9414 /* Ensure that the work item is consistent when activating it ... */
9416 atomic_set(&intel_crtc
->unpin_work
->pending
, INTEL_FLIP_PENDING
);
9417 /* and that it is marked active as soon as the irq could fire. */
9421 static int intel_gen2_queue_flip(struct drm_device
*dev
,
9422 struct drm_crtc
*crtc
,
9423 struct drm_framebuffer
*fb
,
9424 struct drm_i915_gem_object
*obj
,
9425 struct intel_engine_cs
*ring
,
9428 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9432 ret
= intel_ring_begin(ring
, 6);
9436 /* Can't queue multiple flips, so wait for the previous
9437 * one to finish before executing the next.
9439 if (intel_crtc
->plane
)
9440 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
9442 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
9443 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
9444 intel_ring_emit(ring
, MI_NOOP
);
9445 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
9446 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9447 intel_ring_emit(ring
, fb
->pitches
[0]);
9448 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9449 intel_ring_emit(ring
, 0); /* aux display base address, unused */
9451 intel_mark_page_flip_active(intel_crtc
);
9452 __intel_ring_advance(ring
);
9456 static int intel_gen3_queue_flip(struct drm_device
*dev
,
9457 struct drm_crtc
*crtc
,
9458 struct drm_framebuffer
*fb
,
9459 struct drm_i915_gem_object
*obj
,
9460 struct intel_engine_cs
*ring
,
9463 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9467 ret
= intel_ring_begin(ring
, 6);
9471 if (intel_crtc
->plane
)
9472 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
9474 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
9475 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
9476 intel_ring_emit(ring
, MI_NOOP
);
9477 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
9478 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9479 intel_ring_emit(ring
, fb
->pitches
[0]);
9480 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9481 intel_ring_emit(ring
, MI_NOOP
);
9483 intel_mark_page_flip_active(intel_crtc
);
9484 __intel_ring_advance(ring
);
9488 static int intel_gen4_queue_flip(struct drm_device
*dev
,
9489 struct drm_crtc
*crtc
,
9490 struct drm_framebuffer
*fb
,
9491 struct drm_i915_gem_object
*obj
,
9492 struct intel_engine_cs
*ring
,
9495 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9496 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9497 uint32_t pf
, pipesrc
;
9500 ret
= intel_ring_begin(ring
, 4);
9504 /* i965+ uses the linear or tiled offsets from the
9505 * Display Registers (which do not change across a page-flip)
9506 * so we need only reprogram the base address.
9508 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
9509 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9510 intel_ring_emit(ring
, fb
->pitches
[0]);
9511 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
|
9514 /* XXX Enabling the panel-fitter across page-flip is so far
9515 * untested on non-native modes, so ignore it for now.
9516 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9519 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
9520 intel_ring_emit(ring
, pf
| pipesrc
);
9522 intel_mark_page_flip_active(intel_crtc
);
9523 __intel_ring_advance(ring
);
9527 static int intel_gen6_queue_flip(struct drm_device
*dev
,
9528 struct drm_crtc
*crtc
,
9529 struct drm_framebuffer
*fb
,
9530 struct drm_i915_gem_object
*obj
,
9531 struct intel_engine_cs
*ring
,
9534 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9535 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9536 uint32_t pf
, pipesrc
;
9539 ret
= intel_ring_begin(ring
, 4);
9543 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
9544 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9545 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
9546 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9548 /* Contrary to the suggestions in the documentation,
9549 * "Enable Panel Fitter" does not seem to be required when page
9550 * flipping with a non-native mode, and worse causes a normal
9552 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9555 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
9556 intel_ring_emit(ring
, pf
| pipesrc
);
9558 intel_mark_page_flip_active(intel_crtc
);
9559 __intel_ring_advance(ring
);
9563 static int intel_gen7_queue_flip(struct drm_device
*dev
,
9564 struct drm_crtc
*crtc
,
9565 struct drm_framebuffer
*fb
,
9566 struct drm_i915_gem_object
*obj
,
9567 struct intel_engine_cs
*ring
,
9570 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9571 uint32_t plane_bit
= 0;
9574 switch (intel_crtc
->plane
) {
9576 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
9579 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
9582 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
9585 WARN_ONCE(1, "unknown plane in flip command\n");
9590 if (ring
->id
== RCS
) {
9593 * On Gen 8, SRM is now taking an extra dword to accommodate
9594 * 48bits addresses, and we need a NOOP for the batch size to
9602 * BSpec MI_DISPLAY_FLIP for IVB:
9603 * "The full packet must be contained within the same cache line."
9605 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9606 * cacheline, if we ever start emitting more commands before
9607 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9608 * then do the cacheline alignment, and finally emit the
9611 ret
= intel_ring_cacheline_align(ring
);
9615 ret
= intel_ring_begin(ring
, len
);
9619 /* Unmask the flip-done completion message. Note that the bspec says that
9620 * we should do this for both the BCS and RCS, and that we must not unmask
9621 * more than one flip event at any time (or ensure that one flip message
9622 * can be sent by waiting for flip-done prior to queueing new flips).
9623 * Experimentation says that BCS works despite DERRMR masking all
9624 * flip-done completion events and that unmasking all planes at once
9625 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9626 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9628 if (ring
->id
== RCS
) {
9629 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
9630 intel_ring_emit(ring
, DERRMR
);
9631 intel_ring_emit(ring
, ~(DERRMR_PIPEA_PRI_FLIP_DONE
|
9632 DERRMR_PIPEB_PRI_FLIP_DONE
|
9633 DERRMR_PIPEC_PRI_FLIP_DONE
));
9635 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM_GEN8(1) |
9636 MI_SRM_LRM_GLOBAL_GTT
);
9638 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM(1) |
9639 MI_SRM_LRM_GLOBAL_GTT
);
9640 intel_ring_emit(ring
, DERRMR
);
9641 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
+ 256);
9643 intel_ring_emit(ring
, 0);
9644 intel_ring_emit(ring
, MI_NOOP
);
9648 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
9649 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
9650 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9651 intel_ring_emit(ring
, (MI_NOOP
));
9653 intel_mark_page_flip_active(intel_crtc
);
9654 __intel_ring_advance(ring
);
9658 static bool use_mmio_flip(struct intel_engine_cs
*ring
,
9659 struct drm_i915_gem_object
*obj
)
9662 * This is not being used for older platforms, because
9663 * non-availability of flip done interrupt forces us to use
9664 * CS flips. Older platforms derive flip done using some clever
9665 * tricks involving the flip_pending status bits and vblank irqs.
9666 * So using MMIO flips there would disrupt this mechanism.
9672 if (INTEL_INFO(ring
->dev
)->gen
< 5)
9675 if (i915
.use_mmio_flip
< 0)
9677 else if (i915
.use_mmio_flip
> 0)
9679 else if (i915
.enable_execlists
)
9682 return ring
!= obj
->ring
;
9685 static void intel_do_mmio_flip(struct intel_crtc
*intel_crtc
)
9687 struct drm_device
*dev
= intel_crtc
->base
.dev
;
9688 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9689 struct intel_framebuffer
*intel_fb
=
9690 to_intel_framebuffer(intel_crtc
->base
.primary
->fb
);
9691 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
9695 intel_mark_page_flip_active(intel_crtc
);
9697 reg
= DSPCNTR(intel_crtc
->plane
);
9698 dspcntr
= I915_READ(reg
);
9700 if (INTEL_INFO(dev
)->gen
>= 4) {
9701 if (obj
->tiling_mode
!= I915_TILING_NONE
)
9702 dspcntr
|= DISPPLANE_TILED
;
9704 dspcntr
&= ~DISPPLANE_TILED
;
9706 I915_WRITE(reg
, dspcntr
);
9708 I915_WRITE(DSPSURF(intel_crtc
->plane
),
9709 intel_crtc
->unpin_work
->gtt_offset
);
9710 POSTING_READ(DSPSURF(intel_crtc
->plane
));
9713 static int intel_postpone_flip(struct drm_i915_gem_object
*obj
)
9715 struct intel_engine_cs
*ring
;
9718 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
9720 if (!obj
->last_write_seqno
)
9725 if (i915_seqno_passed(ring
->get_seqno(ring
, true),
9726 obj
->last_write_seqno
))
9729 ret
= i915_gem_check_olr(ring
, obj
->last_write_seqno
);
9733 if (WARN_ON(!ring
->irq_get(ring
)))
9739 void intel_notify_mmio_flip(struct intel_engine_cs
*ring
)
9741 struct drm_i915_private
*dev_priv
= to_i915(ring
->dev
);
9742 struct intel_crtc
*intel_crtc
;
9743 unsigned long irq_flags
;
9746 seqno
= ring
->get_seqno(ring
, false);
9748 spin_lock_irqsave(&dev_priv
->mmio_flip_lock
, irq_flags
);
9749 for_each_intel_crtc(ring
->dev
, intel_crtc
) {
9750 struct intel_mmio_flip
*mmio_flip
;
9752 mmio_flip
= &intel_crtc
->mmio_flip
;
9753 if (mmio_flip
->seqno
== 0)
9756 if (ring
->id
!= mmio_flip
->ring_id
)
9759 if (i915_seqno_passed(seqno
, mmio_flip
->seqno
)) {
9760 intel_do_mmio_flip(intel_crtc
);
9761 mmio_flip
->seqno
= 0;
9762 ring
->irq_put(ring
);
9765 spin_unlock_irqrestore(&dev_priv
->mmio_flip_lock
, irq_flags
);
9768 static int intel_queue_mmio_flip(struct drm_device
*dev
,
9769 struct drm_crtc
*crtc
,
9770 struct drm_framebuffer
*fb
,
9771 struct drm_i915_gem_object
*obj
,
9772 struct intel_engine_cs
*ring
,
9775 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9776 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9777 unsigned long irq_flags
;
9780 if (WARN_ON(intel_crtc
->mmio_flip
.seqno
))
9783 ret
= intel_postpone_flip(obj
);
9787 intel_do_mmio_flip(intel_crtc
);
9791 spin_lock_irqsave(&dev_priv
->mmio_flip_lock
, irq_flags
);
9792 intel_crtc
->mmio_flip
.seqno
= obj
->last_write_seqno
;
9793 intel_crtc
->mmio_flip
.ring_id
= obj
->ring
->id
;
9794 spin_unlock_irqrestore(&dev_priv
->mmio_flip_lock
, irq_flags
);
9797 * Double check to catch cases where irq fired before
9798 * mmio flip data was ready
9800 intel_notify_mmio_flip(obj
->ring
);
9804 static int intel_default_queue_flip(struct drm_device
*dev
,
9805 struct drm_crtc
*crtc
,
9806 struct drm_framebuffer
*fb
,
9807 struct drm_i915_gem_object
*obj
,
9808 struct intel_engine_cs
*ring
,
9814 static bool __intel_pageflip_stall_check(struct drm_device
*dev
,
9815 struct drm_crtc
*crtc
)
9817 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9818 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9819 struct intel_unpin_work
*work
= intel_crtc
->unpin_work
;
9822 if (atomic_read(&work
->pending
) >= INTEL_FLIP_COMPLETE
)
9825 if (!work
->enable_stall_check
)
9828 if (work
->flip_ready_vblank
== 0) {
9829 if (work
->flip_queued_ring
&&
9830 !i915_seqno_passed(work
->flip_queued_ring
->get_seqno(work
->flip_queued_ring
, true),
9831 work
->flip_queued_seqno
))
9834 work
->flip_ready_vblank
= drm_vblank_count(dev
, intel_crtc
->pipe
);
9837 if (drm_vblank_count(dev
, intel_crtc
->pipe
) - work
->flip_ready_vblank
< 3)
9840 /* Potential stall - if we see that the flip has happened,
9841 * assume a missed interrupt. */
9842 if (INTEL_INFO(dev
)->gen
>= 4)
9843 addr
= I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc
->plane
)));
9845 addr
= I915_READ(DSPADDR(intel_crtc
->plane
));
9847 /* There is a potential issue here with a false positive after a flip
9848 * to the same address. We could address this by checking for a
9849 * non-incrementing frame counter.
9851 return addr
== work
->gtt_offset
;
9854 void intel_check_page_flip(struct drm_device
*dev
, int pipe
)
9856 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9857 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
9858 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9859 unsigned long flags
;
9864 spin_lock_irqsave(&dev
->event_lock
, flags
);
9865 if (intel_crtc
->unpin_work
&& __intel_pageflip_stall_check(dev
, crtc
)) {
9866 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9867 intel_crtc
->unpin_work
->flip_queued_vblank
, drm_vblank_count(dev
, pipe
));
9868 page_flip_completed(intel_crtc
);
9870 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9873 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
9874 struct drm_framebuffer
*fb
,
9875 struct drm_pending_vblank_event
*event
,
9876 uint32_t page_flip_flags
)
9878 struct drm_device
*dev
= crtc
->dev
;
9879 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9880 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
9881 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
9882 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9883 enum pipe pipe
= intel_crtc
->pipe
;
9884 struct intel_unpin_work
*work
;
9885 struct intel_engine_cs
*ring
;
9886 unsigned long flags
;
9889 //trigger software GT busyness calculation
9890 gen8_flip_interrupt(dev
);
9893 * drm_mode_page_flip_ioctl() should already catch this, but double
9894 * check to be safe. In the future we may enable pageflipping from
9895 * a disabled primary plane.
9897 if (WARN_ON(intel_fb_obj(old_fb
) == NULL
))
9900 /* Can't change pixel format via MI display flips. */
9901 if (fb
->pixel_format
!= crtc
->primary
->fb
->pixel_format
)
9905 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9906 * Note that pitch changes could also affect these register.
9908 if (INTEL_INFO(dev
)->gen
> 3 &&
9909 (fb
->offsets
[0] != crtc
->primary
->fb
->offsets
[0] ||
9910 fb
->pitches
[0] != crtc
->primary
->fb
->pitches
[0]))
9913 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
9916 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
9920 work
->event
= event
;
9922 work
->old_fb_obj
= intel_fb_obj(old_fb
);
9923 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
9925 ret
= drm_crtc_vblank_get(crtc
);
9929 /* We borrow the event spin lock for protecting unpin_work */
9930 spin_lock_irqsave(&dev
->event_lock
, flags
);
9931 if (intel_crtc
->unpin_work
) {
9932 /* Before declaring the flip queue wedged, check if
9933 * the hardware completed the operation behind our backs.
9935 if (__intel_pageflip_stall_check(dev
, crtc
)) {
9936 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9937 page_flip_completed(intel_crtc
);
9939 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9940 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9942 drm_crtc_vblank_put(crtc
);
9947 intel_crtc
->unpin_work
= work
;
9948 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9950 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
9951 flush_workqueue(dev_priv
->wq
);
9953 ret
= i915_mutex_lock_interruptible(dev
);
9957 /* Reference the objects for the scheduled work. */
9958 drm_gem_object_reference(&work
->old_fb_obj
->base
);
9959 drm_gem_object_reference(&obj
->base
);
9961 crtc
->primary
->fb
= fb
;
9963 work
->pending_flip_obj
= obj
;
9965 atomic_inc(&intel_crtc
->unpin_work_count
);
9966 intel_crtc
->reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
9968 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
9969 work
->flip_count
= I915_READ(PIPE_FLIPCOUNT_GM45(pipe
)) + 1;
9971 if (IS_VALLEYVIEW(dev
)) {
9972 ring
= &dev_priv
->ring
[BCS
];
9973 if (obj
->tiling_mode
!= work
->old_fb_obj
->tiling_mode
)
9974 /* vlv: DISPLAY_FLIP fails to change tiling */
9976 } else if (IS_IVYBRIDGE(dev
)) {
9977 ring
= &dev_priv
->ring
[BCS
];
9978 } else if (INTEL_INFO(dev
)->gen
>= 7) {
9980 if (ring
== NULL
|| ring
->id
!= RCS
)
9981 ring
= &dev_priv
->ring
[BCS
];
9983 ring
= &dev_priv
->ring
[RCS
];
9986 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
9988 goto cleanup_pending
;
9991 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
;
9993 if (use_mmio_flip(ring
, obj
)) {
9994 ret
= intel_queue_mmio_flip(dev
, crtc
, fb
, obj
, ring
,
9999 work
->flip_queued_seqno
= obj
->last_write_seqno
;
10000 work
->flip_queued_ring
= obj
->ring
;
10002 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
, ring
,
10005 goto cleanup_unpin
;
10007 work
->flip_queued_seqno
= intel_ring_get_seqno(ring
);
10008 work
->flip_queued_ring
= ring
;
10011 work
->flip_queued_vblank
= drm_vblank_count(dev
, intel_crtc
->pipe
);
10012 work
->enable_stall_check
= true;
10014 i915_gem_track_fb(work
->old_fb_obj
, obj
,
10015 INTEL_FRONTBUFFER_PRIMARY(pipe
));
10017 intel_disable_fbc(dev
);
10018 intel_frontbuffer_flip_prepare(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
10019 mutex_unlock(&dev
->struct_mutex
);
10021 trace_i915_flip_request(intel_crtc
->plane
, obj
);
10026 intel_unpin_fb_obj(obj
);
10028 atomic_dec(&intel_crtc
->unpin_work_count
);
10029 crtc
->primary
->fb
= old_fb
;
10030 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
10031 drm_gem_object_unreference(&obj
->base
);
10032 mutex_unlock(&dev
->struct_mutex
);
10035 spin_lock_irqsave(&dev
->event_lock
, flags
);
10036 intel_crtc
->unpin_work
= NULL
;
10037 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
10039 drm_crtc_vblank_put(crtc
);
10045 intel_crtc_wait_for_pending_flips(crtc
);
10046 ret
= intel_pipe_set_base(crtc
, crtc
->x
, crtc
->y
, fb
);
10047 if (ret
== 0 && event
) {
10048 spin_lock_irqsave(&dev
->event_lock
, flags
);
10049 drm_send_vblank_event(dev
, pipe
, event
);
10050 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
10056 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
10057 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
10058 .load_lut
= intel_crtc_load_lut
,
10062 * intel_modeset_update_staged_output_state
10064 * Updates the staged output configuration state, e.g. after we've read out the
10065 * current hw state.
10067 static void intel_modeset_update_staged_output_state(struct drm_device
*dev
)
10069 struct intel_crtc
*crtc
;
10070 struct intel_encoder
*encoder
;
10071 struct intel_connector
*connector
;
10073 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10075 connector
->new_encoder
=
10076 to_intel_encoder(connector
->base
.encoder
);
10079 for_each_intel_encoder(dev
, encoder
) {
10080 encoder
->new_crtc
=
10081 to_intel_crtc(encoder
->base
.crtc
);
10084 for_each_intel_crtc(dev
, crtc
) {
10085 crtc
->new_enabled
= crtc
->base
.enabled
;
10087 if (crtc
->new_enabled
)
10088 crtc
->new_config
= &crtc
->config
;
10090 crtc
->new_config
= NULL
;
10095 * intel_modeset_commit_output_state
10097 * This function copies the stage display pipe configuration to the real one.
10099 static void intel_modeset_commit_output_state(struct drm_device
*dev
)
10101 struct intel_crtc
*crtc
;
10102 struct intel_encoder
*encoder
;
10103 struct intel_connector
*connector
;
10105 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10107 connector
->base
.encoder
= &connector
->new_encoder
->base
;
10110 for_each_intel_encoder(dev
, encoder
) {
10111 encoder
->base
.crtc
= &encoder
->new_crtc
->base
;
10114 for_each_intel_crtc(dev
, crtc
) {
10115 crtc
->base
.enabled
= crtc
->new_enabled
;
10120 connected_sink_compute_bpp(struct intel_connector
*connector
,
10121 struct intel_crtc_config
*pipe_config
)
10123 int bpp
= pipe_config
->pipe_bpp
;
10125 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10126 connector
->base
.base
.id
,
10127 connector
->base
.name
);
10129 /* Don't use an invalid EDID bpc value */
10130 if (connector
->base
.display_info
.bpc
&&
10131 connector
->base
.display_info
.bpc
* 3 < bpp
) {
10132 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10133 bpp
, connector
->base
.display_info
.bpc
*3);
10134 pipe_config
->pipe_bpp
= connector
->base
.display_info
.bpc
*3;
10137 /* Clamp bpp to 8 on screens without EDID 1.4 */
10138 if (connector
->base
.display_info
.bpc
== 0 && bpp
> 24) {
10139 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10141 pipe_config
->pipe_bpp
= 24;
10146 compute_baseline_pipe_bpp(struct intel_crtc
*crtc
,
10147 struct drm_framebuffer
*fb
,
10148 struct intel_crtc_config
*pipe_config
)
10150 struct drm_device
*dev
= crtc
->base
.dev
;
10151 struct intel_connector
*connector
;
10154 switch (fb
->pixel_format
) {
10155 case DRM_FORMAT_C8
:
10156 bpp
= 8*3; /* since we go through a colormap */
10158 case DRM_FORMAT_XRGB1555
:
10159 case DRM_FORMAT_ARGB1555
:
10160 /* checked in intel_framebuffer_init already */
10161 if (WARN_ON(INTEL_INFO(dev
)->gen
> 3))
10163 case DRM_FORMAT_RGB565
:
10164 bpp
= 6*3; /* min is 18bpp */
10166 case DRM_FORMAT_XBGR8888
:
10167 case DRM_FORMAT_ABGR8888
:
10168 /* checked in intel_framebuffer_init already */
10169 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
10171 case DRM_FORMAT_XRGB8888
:
10172 case DRM_FORMAT_ARGB8888
:
10175 case DRM_FORMAT_XRGB2101010
:
10176 case DRM_FORMAT_ARGB2101010
:
10177 case DRM_FORMAT_XBGR2101010
:
10178 case DRM_FORMAT_ABGR2101010
:
10179 /* checked in intel_framebuffer_init already */
10180 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
10184 /* TODO: gen4+ supports 16 bpc floating point, too. */
10186 DRM_DEBUG_KMS("unsupported depth\n");
10190 pipe_config
->pipe_bpp
= bpp
;
10192 /* Clamp display bpp to EDID value */
10193 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10195 if (!connector
->new_encoder
||
10196 connector
->new_encoder
->new_crtc
!= crtc
)
10199 connected_sink_compute_bpp(connector
, pipe_config
);
10205 static void intel_dump_crtc_timings(const struct drm_display_mode
*mode
)
10207 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10208 "type: 0x%x flags: 0x%x\n",
10210 mode
->crtc_hdisplay
, mode
->crtc_hsync_start
,
10211 mode
->crtc_hsync_end
, mode
->crtc_htotal
,
10212 mode
->crtc_vdisplay
, mode
->crtc_vsync_start
,
10213 mode
->crtc_vsync_end
, mode
->crtc_vtotal
, mode
->type
, mode
->flags
);
10216 static void intel_dump_pipe_config(struct intel_crtc
*crtc
,
10217 struct intel_crtc_config
*pipe_config
,
10218 const char *context
)
10220 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc
->base
.base
.id
,
10221 context
, pipe_name(crtc
->pipe
));
10223 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config
->cpu_transcoder
));
10224 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10225 pipe_config
->pipe_bpp
, pipe_config
->dither
);
10226 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10227 pipe_config
->has_pch_encoder
,
10228 pipe_config
->fdi_lanes
,
10229 pipe_config
->fdi_m_n
.gmch_m
, pipe_config
->fdi_m_n
.gmch_n
,
10230 pipe_config
->fdi_m_n
.link_m
, pipe_config
->fdi_m_n
.link_n
,
10231 pipe_config
->fdi_m_n
.tu
);
10232 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10233 pipe_config
->has_dp_encoder
,
10234 pipe_config
->dp_m_n
.gmch_m
, pipe_config
->dp_m_n
.gmch_n
,
10235 pipe_config
->dp_m_n
.link_m
, pipe_config
->dp_m_n
.link_n
,
10236 pipe_config
->dp_m_n
.tu
);
10238 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10239 pipe_config
->has_dp_encoder
,
10240 pipe_config
->dp_m2_n2
.gmch_m
,
10241 pipe_config
->dp_m2_n2
.gmch_n
,
10242 pipe_config
->dp_m2_n2
.link_m
,
10243 pipe_config
->dp_m2_n2
.link_n
,
10244 pipe_config
->dp_m2_n2
.tu
);
10246 DRM_DEBUG_KMS("requested mode:\n");
10247 drm_mode_debug_printmodeline(&pipe_config
->requested_mode
);
10248 DRM_DEBUG_KMS("adjusted mode:\n");
10249 drm_mode_debug_printmodeline(&pipe_config
->adjusted_mode
);
10250 intel_dump_crtc_timings(&pipe_config
->adjusted_mode
);
10251 DRM_DEBUG_KMS("port clock: %d\n", pipe_config
->port_clock
);
10252 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10253 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
);
10254 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10255 pipe_config
->gmch_pfit
.control
,
10256 pipe_config
->gmch_pfit
.pgm_ratios
,
10257 pipe_config
->gmch_pfit
.lvds_border_bits
);
10258 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10259 pipe_config
->pch_pfit
.pos
,
10260 pipe_config
->pch_pfit
.size
,
10261 pipe_config
->pch_pfit
.enabled
? "enabled" : "disabled");
10262 DRM_DEBUG_KMS("ips: %i\n", pipe_config
->ips_enabled
);
10263 DRM_DEBUG_KMS("double wide: %i\n", pipe_config
->double_wide
);
10266 static bool encoders_cloneable(const struct intel_encoder
*a
,
10267 const struct intel_encoder
*b
)
10269 /* masks could be asymmetric, so check both ways */
10270 return a
== b
|| (a
->cloneable
& (1 << b
->type
) &&
10271 b
->cloneable
& (1 << a
->type
));
10274 static bool check_single_encoder_cloning(struct intel_crtc
*crtc
,
10275 struct intel_encoder
*encoder
)
10277 struct drm_device
*dev
= crtc
->base
.dev
;
10278 struct intel_encoder
*source_encoder
;
10280 for_each_intel_encoder(dev
, source_encoder
) {
10281 if (source_encoder
->new_crtc
!= crtc
)
10284 if (!encoders_cloneable(encoder
, source_encoder
))
10291 static bool check_encoder_cloning(struct intel_crtc
*crtc
)
10293 struct drm_device
*dev
= crtc
->base
.dev
;
10294 struct intel_encoder
*encoder
;
10296 for_each_intel_encoder(dev
, encoder
) {
10297 if (encoder
->new_crtc
!= crtc
)
10300 if (!check_single_encoder_cloning(crtc
, encoder
))
10307 static struct intel_crtc_config
*
10308 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
10309 struct drm_framebuffer
*fb
,
10310 struct drm_display_mode
*mode
)
10312 struct drm_device
*dev
= crtc
->dev
;
10313 struct intel_encoder
*encoder
;
10314 struct intel_crtc_config
*pipe_config
;
10315 int plane_bpp
, ret
= -EINVAL
;
10318 if (!check_encoder_cloning(to_intel_crtc(crtc
))) {
10319 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10320 return ERR_PTR(-EINVAL
);
10323 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
10325 return ERR_PTR(-ENOMEM
);
10327 drm_mode_copy(&pipe_config
->adjusted_mode
, mode
);
10328 drm_mode_copy(&pipe_config
->requested_mode
, mode
);
10330 pipe_config
->cpu_transcoder
=
10331 (enum transcoder
) to_intel_crtc(crtc
)->pipe
;
10332 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
10335 * Sanitize sync polarity flags based on requested ones. If neither
10336 * positive or negative polarity is requested, treat this as meaning
10337 * negative polarity.
10339 if (!(pipe_config
->adjusted_mode
.flags
&
10340 (DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NHSYNC
)))
10341 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
10343 if (!(pipe_config
->adjusted_mode
.flags
&
10344 (DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_NVSYNC
)))
10345 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
10347 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10348 * plane pixel format and any sink constraints into account. Returns the
10349 * source plane bpp so that dithering can be selected on mismatches
10350 * after encoders and crtc also have had their say. */
10351 plane_bpp
= compute_baseline_pipe_bpp(to_intel_crtc(crtc
),
10357 * Determine the real pipe dimensions. Note that stereo modes can
10358 * increase the actual pipe size due to the frame doubling and
10359 * insertion of additional space for blanks between the frame. This
10360 * is stored in the crtc timings. We use the requested mode to do this
10361 * computation to clearly distinguish it from the adjusted mode, which
10362 * can be changed by the connectors in the below retry loop.
10364 drm_mode_set_crtcinfo(&pipe_config
->requested_mode
, CRTC_STEREO_DOUBLE
);
10365 pipe_config
->pipe_src_w
= pipe_config
->requested_mode
.crtc_hdisplay
;
10366 pipe_config
->pipe_src_h
= pipe_config
->requested_mode
.crtc_vdisplay
;
10369 /* Ensure the port clock defaults are reset when retrying. */
10370 pipe_config
->port_clock
= 0;
10371 pipe_config
->pixel_multiplier
= 1;
10373 /* Fill in default crtc timings, allow encoders to overwrite them. */
10374 drm_mode_set_crtcinfo(&pipe_config
->adjusted_mode
, CRTC_STEREO_DOUBLE
);
10376 /* Pass our mode to the connectors and the CRTC to give them a chance to
10377 * adjust it according to limitations or connector properties, and also
10378 * a chance to reject the mode entirely.
10380 for_each_intel_encoder(dev
, encoder
) {
10382 if (&encoder
->new_crtc
->base
!= crtc
)
10385 if (!(encoder
->compute_config(encoder
, pipe_config
))) {
10386 DRM_DEBUG_KMS("Encoder config failure\n");
10391 /* Set default port clock if not overwritten by the encoder. Needs to be
10392 * done afterwards in case the encoder adjusts the mode. */
10393 if (!pipe_config
->port_clock
)
10394 pipe_config
->port_clock
= pipe_config
->adjusted_mode
.crtc_clock
10395 * pipe_config
->pixel_multiplier
;
10397 ret
= intel_crtc_compute_config(to_intel_crtc(crtc
), pipe_config
);
10399 DRM_DEBUG_KMS("CRTC fixup failed\n");
10403 if (ret
== RETRY
) {
10404 if (WARN(!retry
, "loop in pipe configuration computation\n")) {
10409 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10411 goto encoder_retry
;
10414 pipe_config
->dither
= pipe_config
->pipe_bpp
!= plane_bpp
;
10415 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10416 plane_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
10418 return pipe_config
;
10420 kfree(pipe_config
);
10421 return ERR_PTR(ret
);
10424 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10425 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10427 intel_modeset_affected_pipes(struct drm_crtc
*crtc
, unsigned *modeset_pipes
,
10428 unsigned *prepare_pipes
, unsigned *disable_pipes
)
10430 struct intel_crtc
*intel_crtc
;
10431 struct drm_device
*dev
= crtc
->dev
;
10432 struct intel_encoder
*encoder
;
10433 struct intel_connector
*connector
;
10434 struct drm_crtc
*tmp_crtc
;
10436 *disable_pipes
= *modeset_pipes
= *prepare_pipes
= 0;
10438 /* Check which crtcs have changed outputs connected to them, these need
10439 * to be part of the prepare_pipes mask. We don't (yet) support global
10440 * modeset across multiple crtcs, so modeset_pipes will only have one
10441 * bit set at most. */
10442 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10444 if (connector
->base
.encoder
== &connector
->new_encoder
->base
)
10447 if (connector
->base
.encoder
) {
10448 tmp_crtc
= connector
->base
.encoder
->crtc
;
10450 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
10453 if (connector
->new_encoder
)
10455 1 << connector
->new_encoder
->new_crtc
->pipe
;
10458 for_each_intel_encoder(dev
, encoder
) {
10459 if (encoder
->base
.crtc
== &encoder
->new_crtc
->base
)
10462 if (encoder
->base
.crtc
) {
10463 tmp_crtc
= encoder
->base
.crtc
;
10465 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
10468 if (encoder
->new_crtc
)
10469 *prepare_pipes
|= 1 << encoder
->new_crtc
->pipe
;
10472 /* Check for pipes that will be enabled/disabled ... */
10473 for_each_intel_crtc(dev
, intel_crtc
) {
10474 if (intel_crtc
->base
.enabled
== intel_crtc
->new_enabled
)
10477 if (!intel_crtc
->new_enabled
)
10478 *disable_pipes
|= 1 << intel_crtc
->pipe
;
10480 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
10484 /* set_mode is also used to update properties on life display pipes. */
10485 intel_crtc
= to_intel_crtc(crtc
);
10486 if (intel_crtc
->new_enabled
)
10487 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
10490 * For simplicity do a full modeset on any pipe where the output routing
10491 * changed. We could be more clever, but that would require us to be
10492 * more careful with calling the relevant encoder->mode_set functions.
10494 if (*prepare_pipes
)
10495 *modeset_pipes
= *prepare_pipes
;
10497 /* ... and mask these out. */
10498 *modeset_pipes
&= ~(*disable_pipes
);
10499 *prepare_pipes
&= ~(*disable_pipes
);
10502 * HACK: We don't (yet) fully support global modesets. intel_set_config
10503 * obies this rule, but the modeset restore mode of
10504 * intel_modeset_setup_hw_state does not.
10506 *modeset_pipes
&= 1 << intel_crtc
->pipe
;
10507 *prepare_pipes
&= 1 << intel_crtc
->pipe
;
10509 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10510 *modeset_pipes
, *prepare_pipes
, *disable_pipes
);
10513 static bool intel_crtc_in_use(struct drm_crtc
*crtc
)
10515 struct drm_encoder
*encoder
;
10516 struct drm_device
*dev
= crtc
->dev
;
10518 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
)
10519 if (encoder
->crtc
== crtc
)
10526 intel_modeset_update_state(struct drm_device
*dev
, unsigned prepare_pipes
)
10528 struct intel_encoder
*intel_encoder
;
10529 struct intel_crtc
*intel_crtc
;
10530 struct drm_connector
*connector
;
10532 for_each_intel_encoder(dev
, intel_encoder
) {
10533 if (!intel_encoder
->base
.crtc
)
10536 intel_crtc
= to_intel_crtc(intel_encoder
->base
.crtc
);
10538 if (prepare_pipes
& (1 << intel_crtc
->pipe
))
10539 intel_encoder
->connectors_active
= false;
10542 intel_modeset_commit_output_state(dev
);
10544 /* Double check state. */
10545 for_each_intel_crtc(dev
, intel_crtc
) {
10546 WARN_ON(intel_crtc
->base
.enabled
!= intel_crtc_in_use(&intel_crtc
->base
));
10547 WARN_ON(intel_crtc
->new_config
&&
10548 intel_crtc
->new_config
!= &intel_crtc
->config
);
10549 WARN_ON(intel_crtc
->base
.enabled
!= !!intel_crtc
->new_config
);
10552 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
10553 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
10556 intel_crtc
= to_intel_crtc(connector
->encoder
->crtc
);
10558 if (prepare_pipes
& (1 << intel_crtc
->pipe
)) {
10559 struct drm_property
*dpms_property
=
10560 dev
->mode_config
.dpms_property
;
10562 connector
->dpms
= DRM_MODE_DPMS_ON
;
10563 drm_object_property_set_value(&connector
->base
,
10567 intel_encoder
= to_intel_encoder(connector
->encoder
);
10568 intel_encoder
->connectors_active
= true;
10574 static bool intel_fuzzy_clock_check(int clock1
, int clock2
)
10578 if (clock1
== clock2
)
10581 if (!clock1
|| !clock2
)
10584 diff
= abs(clock1
- clock2
);
10586 if (((((diff
+ clock1
+ clock2
) * 100)) / (clock1
+ clock2
)) < 105)
10592 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10593 list_for_each_entry((intel_crtc), \
10594 &(dev)->mode_config.crtc_list, \
10596 if (mask & (1 <<(intel_crtc)->pipe))
10599 intel_pipe_config_compare(struct drm_device
*dev
,
10600 struct intel_crtc_config
*current_config
,
10601 struct intel_crtc_config
*pipe_config
)
10603 #define PIPE_CONF_CHECK_X(name) \
10604 if (current_config->name != pipe_config->name) { \
10605 DRM_ERROR("mismatch in " #name " " \
10606 "(expected 0x%08x, found 0x%08x)\n", \
10607 current_config->name, \
10608 pipe_config->name); \
10612 #define PIPE_CONF_CHECK_I(name) \
10613 if (current_config->name != pipe_config->name) { \
10614 DRM_ERROR("mismatch in " #name " " \
10615 "(expected %i, found %i)\n", \
10616 current_config->name, \
10617 pipe_config->name); \
10621 /* This is required for BDW+ where there is only one set of registers for
10622 * switching between high and low RR.
10623 * This macro can be used whenever a comparison has to be made between one
10624 * hw state and multiple sw state variables.
10626 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10627 if ((current_config->name != pipe_config->name) && \
10628 (current_config->alt_name != pipe_config->name)) { \
10629 DRM_ERROR("mismatch in " #name " " \
10630 "(expected %i or %i, found %i)\n", \
10631 current_config->name, \
10632 current_config->alt_name, \
10633 pipe_config->name); \
10637 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10638 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10639 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10640 "(expected %i, found %i)\n", \
10641 current_config->name & (mask), \
10642 pipe_config->name & (mask)); \
10646 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10647 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10648 DRM_ERROR("mismatch in " #name " " \
10649 "(expected %i, found %i)\n", \
10650 current_config->name, \
10651 pipe_config->name); \
10655 #define PIPE_CONF_QUIRK(quirk) \
10656 ((current_config->quirks | pipe_config->quirks) & (quirk))
10658 PIPE_CONF_CHECK_I(cpu_transcoder
);
10660 PIPE_CONF_CHECK_I(has_pch_encoder
);
10661 PIPE_CONF_CHECK_I(fdi_lanes
);
10662 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_m
);
10663 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_n
);
10664 PIPE_CONF_CHECK_I(fdi_m_n
.link_m
);
10665 PIPE_CONF_CHECK_I(fdi_m_n
.link_n
);
10666 PIPE_CONF_CHECK_I(fdi_m_n
.tu
);
10668 PIPE_CONF_CHECK_I(has_dp_encoder
);
10670 if (INTEL_INFO(dev
)->gen
< 8) {
10671 PIPE_CONF_CHECK_I(dp_m_n
.gmch_m
);
10672 PIPE_CONF_CHECK_I(dp_m_n
.gmch_n
);
10673 PIPE_CONF_CHECK_I(dp_m_n
.link_m
);
10674 PIPE_CONF_CHECK_I(dp_m_n
.link_n
);
10675 PIPE_CONF_CHECK_I(dp_m_n
.tu
);
10677 if (current_config
->has_drrs
) {
10678 PIPE_CONF_CHECK_I(dp_m2_n2
.gmch_m
);
10679 PIPE_CONF_CHECK_I(dp_m2_n2
.gmch_n
);
10680 PIPE_CONF_CHECK_I(dp_m2_n2
.link_m
);
10681 PIPE_CONF_CHECK_I(dp_m2_n2
.link_n
);
10682 PIPE_CONF_CHECK_I(dp_m2_n2
.tu
);
10685 PIPE_CONF_CHECK_I_ALT(dp_m_n
.gmch_m
, dp_m2_n2
.gmch_m
);
10686 PIPE_CONF_CHECK_I_ALT(dp_m_n
.gmch_n
, dp_m2_n2
.gmch_n
);
10687 PIPE_CONF_CHECK_I_ALT(dp_m_n
.link_m
, dp_m2_n2
.link_m
);
10688 PIPE_CONF_CHECK_I_ALT(dp_m_n
.link_n
, dp_m2_n2
.link_n
);
10689 PIPE_CONF_CHECK_I_ALT(dp_m_n
.tu
, dp_m2_n2
.tu
);
10692 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hdisplay
);
10693 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_htotal
);
10694 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hblank_start
);
10695 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hblank_end
);
10696 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hsync_start
);
10697 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hsync_end
);
10699 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vdisplay
);
10700 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vtotal
);
10701 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vblank_start
);
10702 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vblank_end
);
10703 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vsync_start
);
10704 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vsync_end
);
10706 PIPE_CONF_CHECK_I(pixel_multiplier
);
10707 PIPE_CONF_CHECK_I(has_hdmi_sink
);
10708 if ((INTEL_INFO(dev
)->gen
< 8 && !IS_HASWELL(dev
)) ||
10709 IS_VALLEYVIEW(dev
))
10710 PIPE_CONF_CHECK_I(limited_color_range
);
10712 PIPE_CONF_CHECK_I(has_audio
);
10714 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10715 DRM_MODE_FLAG_INTERLACE
);
10717 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
10718 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10719 DRM_MODE_FLAG_PHSYNC
);
10720 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10721 DRM_MODE_FLAG_NHSYNC
);
10722 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10723 DRM_MODE_FLAG_PVSYNC
);
10724 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10725 DRM_MODE_FLAG_NVSYNC
);
10728 PIPE_CONF_CHECK_I(pipe_src_w
);
10729 PIPE_CONF_CHECK_I(pipe_src_h
);
10732 * FIXME: BIOS likes to set up a cloned config with lvds+external
10733 * screen. Since we don't yet re-compute the pipe config when moving
10734 * just the lvds port away to another pipe the sw tracking won't match.
10736 * Proper atomic modesets with recomputed global state will fix this.
10737 * Until then just don't check gmch state for inherited modes.
10739 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE
)) {
10740 PIPE_CONF_CHECK_I(gmch_pfit
.control
);
10741 /* pfit ratios are autocomputed by the hw on gen4+ */
10742 if (INTEL_INFO(dev
)->gen
< 4)
10743 PIPE_CONF_CHECK_I(gmch_pfit
.pgm_ratios
);
10744 PIPE_CONF_CHECK_I(gmch_pfit
.lvds_border_bits
);
10747 PIPE_CONF_CHECK_I(pch_pfit
.enabled
);
10748 if (current_config
->pch_pfit
.enabled
) {
10749 PIPE_CONF_CHECK_I(pch_pfit
.pos
);
10750 PIPE_CONF_CHECK_I(pch_pfit
.size
);
10753 /* BDW+ don't expose a synchronous way to read the state */
10754 if (IS_HASWELL(dev
))
10755 PIPE_CONF_CHECK_I(ips_enabled
);
10757 PIPE_CONF_CHECK_I(double_wide
);
10759 PIPE_CONF_CHECK_X(ddi_pll_sel
);
10761 PIPE_CONF_CHECK_I(shared_dpll
);
10762 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll
);
10763 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll_md
);
10764 PIPE_CONF_CHECK_X(dpll_hw_state
.fp0
);
10765 PIPE_CONF_CHECK_X(dpll_hw_state
.fp1
);
10766 PIPE_CONF_CHECK_X(dpll_hw_state
.wrpll
);
10768 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5)
10769 PIPE_CONF_CHECK_I(pipe_bpp
);
10771 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode
.crtc_clock
);
10772 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock
);
10774 #undef PIPE_CONF_CHECK_X
10775 #undef PIPE_CONF_CHECK_I
10776 #undef PIPE_CONF_CHECK_I_ALT
10777 #undef PIPE_CONF_CHECK_FLAGS
10778 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10779 #undef PIPE_CONF_QUIRK
10785 check_connector_state(struct drm_device
*dev
)
10787 struct intel_connector
*connector
;
10789 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10791 /* This also checks the encoder/connector hw state with the
10792 * ->get_hw_state callbacks. */
10793 intel_connector_check_state(connector
);
10795 WARN(&connector
->new_encoder
->base
!= connector
->base
.encoder
,
10796 "connector's staged encoder doesn't match current encoder\n");
10801 check_encoder_state(struct drm_device
*dev
)
10803 struct intel_encoder
*encoder
;
10804 struct intel_connector
*connector
;
10806 for_each_intel_encoder(dev
, encoder
) {
10807 bool enabled
= false;
10808 bool active
= false;
10809 enum pipe pipe
, tracked_pipe
;
10811 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10812 encoder
->base
.base
.id
,
10813 encoder
->base
.name
);
10815 WARN(&encoder
->new_crtc
->base
!= encoder
->base
.crtc
,
10816 "encoder's stage crtc doesn't match current crtc\n");
10817 WARN(encoder
->connectors_active
&& !encoder
->base
.crtc
,
10818 "encoder's active_connectors set, but no crtc\n");
10820 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10822 if (connector
->base
.encoder
!= &encoder
->base
)
10825 if (connector
->base
.dpms
!= DRM_MODE_DPMS_OFF
)
10829 * for MST connectors if we unplug the connector is gone
10830 * away but the encoder is still connected to a crtc
10831 * until a modeset happens in response to the hotplug.
10833 if (!enabled
&& encoder
->base
.encoder_type
== DRM_MODE_ENCODER_DPMST
)
10836 WARN(!!encoder
->base
.crtc
!= enabled
,
10837 "encoder's enabled state mismatch "
10838 "(expected %i, found %i)\n",
10839 !!encoder
->base
.crtc
, enabled
);
10840 WARN(active
&& !encoder
->base
.crtc
,
10841 "active encoder with no crtc\n");
10843 WARN(encoder
->connectors_active
!= active
,
10844 "encoder's computed active state doesn't match tracked active state "
10845 "(expected %i, found %i)\n", active
, encoder
->connectors_active
);
10847 active
= encoder
->get_hw_state(encoder
, &pipe
);
10848 WARN(active
!= encoder
->connectors_active
,
10849 "encoder's hw state doesn't match sw tracking "
10850 "(expected %i, found %i)\n",
10851 encoder
->connectors_active
, active
);
10853 if (!encoder
->base
.crtc
)
10856 tracked_pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
10857 WARN(active
&& pipe
!= tracked_pipe
,
10858 "active encoder's pipe doesn't match"
10859 "(expected %i, found %i)\n",
10860 tracked_pipe
, pipe
);
10866 check_crtc_state(struct drm_device
*dev
)
10868 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10869 struct intel_crtc
*crtc
;
10870 struct intel_encoder
*encoder
;
10871 struct intel_crtc_config pipe_config
;
10873 for_each_intel_crtc(dev
, crtc
) {
10874 bool enabled
= false;
10875 bool active
= false;
10877 memset(&pipe_config
, 0, sizeof(pipe_config
));
10879 DRM_DEBUG_KMS("[CRTC:%d]\n",
10880 crtc
->base
.base
.id
);
10882 WARN(crtc
->active
&& !crtc
->base
.enabled
,
10883 "active crtc, but not enabled in sw tracking\n");
10885 for_each_intel_encoder(dev
, encoder
) {
10886 if (encoder
->base
.crtc
!= &crtc
->base
)
10889 if (encoder
->connectors_active
)
10893 WARN(active
!= crtc
->active
,
10894 "crtc's computed active state doesn't match tracked active state "
10895 "(expected %i, found %i)\n", active
, crtc
->active
);
10896 WARN(enabled
!= crtc
->base
.enabled
,
10897 "crtc's computed enabled state doesn't match tracked enabled state "
10898 "(expected %i, found %i)\n", enabled
, crtc
->base
.enabled
);
10900 active
= dev_priv
->display
.get_pipe_config(crtc
,
10903 /* hw state is inconsistent with the pipe quirk */
10904 if ((crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
10905 (crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
10906 active
= crtc
->active
;
10908 for_each_intel_encoder(dev
, encoder
) {
10910 if (encoder
->base
.crtc
!= &crtc
->base
)
10912 if (encoder
->get_hw_state(encoder
, &pipe
))
10913 encoder
->get_config(encoder
, &pipe_config
);
10916 WARN(crtc
->active
!= active
,
10917 "crtc active state doesn't match with hw state "
10918 "(expected %i, found %i)\n", crtc
->active
, active
);
10921 !intel_pipe_config_compare(dev
, &crtc
->config
, &pipe_config
)) {
10922 WARN(1, "pipe state doesn't match!\n");
10923 intel_dump_pipe_config(crtc
, &pipe_config
,
10925 intel_dump_pipe_config(crtc
, &crtc
->config
,
10932 check_shared_dpll_state(struct drm_device
*dev
)
10934 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10935 struct intel_crtc
*crtc
;
10936 struct intel_dpll_hw_state dpll_hw_state
;
10939 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
10940 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
10941 int enabled_crtcs
= 0, active_crtcs
= 0;
10944 memset(&dpll_hw_state
, 0, sizeof(dpll_hw_state
));
10946 DRM_DEBUG_KMS("%s\n", pll
->name
);
10948 active
= pll
->get_hw_state(dev_priv
, pll
, &dpll_hw_state
);
10950 WARN(pll
->active
> pll
->refcount
,
10951 "more active pll users than references: %i vs %i\n",
10952 pll
->active
, pll
->refcount
);
10953 WARN(pll
->active
&& !pll
->on
,
10954 "pll in active use but not on in sw tracking\n");
10955 WARN(pll
->on
&& !pll
->active
,
10956 "pll in on but not on in use in sw tracking\n");
10957 WARN(pll
->on
!= active
,
10958 "pll on state mismatch (expected %i, found %i)\n",
10961 for_each_intel_crtc(dev
, crtc
) {
10962 if (crtc
->base
.enabled
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
10964 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
10967 WARN(pll
->active
!= active_crtcs
,
10968 "pll active crtcs mismatch (expected %i, found %i)\n",
10969 pll
->active
, active_crtcs
);
10970 WARN(pll
->refcount
!= enabled_crtcs
,
10971 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10972 pll
->refcount
, enabled_crtcs
);
10974 WARN(pll
->on
&& memcmp(&pll
->hw_state
, &dpll_hw_state
,
10975 sizeof(dpll_hw_state
)),
10976 "pll hw state mismatch\n");
10981 intel_modeset_check_state(struct drm_device
*dev
)
10983 check_connector_state(dev
);
10984 check_encoder_state(dev
);
10985 check_crtc_state(dev
);
10986 check_shared_dpll_state(dev
);
10989 void ironlake_check_encoder_dotclock(const struct intel_crtc_config
*pipe_config
,
10993 * FDI already provided one idea for the dotclock.
10994 * Yell if the encoder disagrees.
10996 WARN(!intel_fuzzy_clock_check(pipe_config
->adjusted_mode
.crtc_clock
, dotclock
),
10997 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10998 pipe_config
->adjusted_mode
.crtc_clock
, dotclock
);
11001 static void update_scanline_offset(struct intel_crtc
*crtc
)
11003 struct drm_device
*dev
= crtc
->base
.dev
;
11006 * The scanline counter increments at the leading edge of hsync.
11008 * On most platforms it starts counting from vtotal-1 on the
11009 * first active line. That means the scanline counter value is
11010 * always one less than what we would expect. Ie. just after
11011 * start of vblank, which also occurs at start of hsync (on the
11012 * last active line), the scanline counter will read vblank_start-1.
11014 * On gen2 the scanline counter starts counting from 1 instead
11015 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11016 * to keep the value positive), instead of adding one.
11018 * On HSW+ the behaviour of the scanline counter depends on the output
11019 * type. For DP ports it behaves like most other platforms, but on HDMI
11020 * there's an extra 1 line difference. So we need to add two instead of
11021 * one to the value.
11023 if (IS_GEN2(dev
)) {
11024 const struct drm_display_mode
*mode
= &crtc
->config
.adjusted_mode
;
11027 vtotal
= mode
->crtc_vtotal
;
11028 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
11031 crtc
->scanline_offset
= vtotal
- 1;
11032 } else if (HAS_DDI(dev
) &&
11033 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
)) {
11034 crtc
->scanline_offset
= 2;
11036 crtc
->scanline_offset
= 1;
11039 static int __intel_set_mode(struct drm_crtc
*crtc
,
11040 struct drm_display_mode
*mode
,
11041 int x
, int y
, struct drm_framebuffer
*fb
)
11043 struct drm_device
*dev
= crtc
->dev
;
11044 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11045 struct drm_display_mode
*saved_mode
;
11046 struct intel_crtc_config
*pipe_config
= NULL
;
11047 struct intel_crtc
*intel_crtc
;
11048 unsigned disable_pipes
, prepare_pipes
, modeset_pipes
;
11051 saved_mode
= kmalloc(sizeof(*saved_mode
), GFP_KERNEL
);
11055 intel_modeset_affected_pipes(crtc
, &modeset_pipes
,
11056 &prepare_pipes
, &disable_pipes
);
11058 *saved_mode
= crtc
->mode
;
11060 /* Hack: Because we don't (yet) support global modeset on multiple
11061 * crtcs, we don't keep track of the new mode for more than one crtc.
11062 * Hence simply check whether any bit is set in modeset_pipes in all the
11063 * pieces of code that are not yet converted to deal with mutliple crtcs
11064 * changing their mode at the same time. */
11065 if (modeset_pipes
) {
11066 pipe_config
= intel_modeset_pipe_config(crtc
, fb
, mode
);
11067 if (IS_ERR(pipe_config
)) {
11068 ret
= PTR_ERR(pipe_config
);
11069 pipe_config
= NULL
;
11073 intel_dump_pipe_config(to_intel_crtc(crtc
), pipe_config
,
11075 to_intel_crtc(crtc
)->new_config
= pipe_config
;
11079 * See if the config requires any additional preparation, e.g.
11080 * to adjust global state with pipes off. We need to do this
11081 * here so we can get the modeset_pipe updated config for the new
11082 * mode set on this crtc. For other crtcs we need to use the
11083 * adjusted_mode bits in the crtc directly.
11085 if (IS_VALLEYVIEW(dev
)) {
11086 valleyview_modeset_global_pipes(dev
, &prepare_pipes
);
11088 /* may have added more to prepare_pipes than we should */
11089 prepare_pipes
&= ~disable_pipes
;
11092 for_each_intel_crtc_masked(dev
, disable_pipes
, intel_crtc
)
11093 intel_crtc_disable(&intel_crtc
->base
);
11095 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
11096 if (intel_crtc
->base
.enabled
)
11097 dev_priv
->display
.crtc_disable(&intel_crtc
->base
);
11100 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11101 * to set it here already despite that we pass it down the callchain.
11103 if (modeset_pipes
) {
11104 crtc
->mode
= *mode
;
11105 /* mode_set/enable/disable functions rely on a correct pipe
11107 to_intel_crtc(crtc
)->config
= *pipe_config
;
11108 to_intel_crtc(crtc
)->new_config
= &to_intel_crtc(crtc
)->config
;
11111 * Calculate and store various constants which
11112 * are later needed by vblank and swap-completion
11113 * timestamping. They are derived from true hwmode.
11115 drm_calc_timestamping_constants(crtc
,
11116 &pipe_config
->adjusted_mode
);
11119 /* Only after disabling all output pipelines that will be changed can we
11120 * update the the output configuration. */
11121 intel_modeset_update_state(dev
, prepare_pipes
);
11123 if (dev_priv
->display
.modeset_global_resources
)
11124 dev_priv
->display
.modeset_global_resources(dev
);
11126 /* Set up the DPLL and any encoders state that needs to adjust or depend
11129 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
11130 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
11131 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(old_fb
);
11132 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
11134 mutex_lock(&dev
->struct_mutex
);
11135 ret
= intel_pin_and_fence_fb_obj(dev
,
11139 DRM_ERROR("pin & fence failed\n");
11140 mutex_unlock(&dev
->struct_mutex
);
11144 intel_unpin_fb_obj(old_obj
);
11145 i915_gem_track_fb(old_obj
, obj
,
11146 INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
));
11147 mutex_unlock(&dev
->struct_mutex
);
11149 crtc
->primary
->fb
= fb
;
11153 ret
= dev_priv
->display
.crtc_mode_set(&intel_crtc
->base
,
11159 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11160 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
11161 update_scanline_offset(intel_crtc
);
11163 dev_priv
->display
.crtc_enable(&intel_crtc
->base
);
11166 /* FIXME: add subpixel order */
11168 if (ret
&& crtc
->enabled
)
11169 crtc
->mode
= *saved_mode
;
11172 kfree(pipe_config
);
11177 static int intel_set_mode(struct drm_crtc
*crtc
,
11178 struct drm_display_mode
*mode
,
11179 int x
, int y
, struct drm_framebuffer
*fb
)
11183 ret
= __intel_set_mode(crtc
, mode
, x
, y
, fb
);
11186 intel_modeset_check_state(crtc
->dev
);
11191 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
11193 intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
, crtc
->primary
->fb
);
11196 #undef for_each_intel_crtc_masked
11198 static void intel_set_config_free(struct intel_set_config
*config
)
11203 kfree(config
->save_connector_encoders
);
11204 kfree(config
->save_encoder_crtcs
);
11205 kfree(config
->save_crtc_enabled
);
11209 static int intel_set_config_save_state(struct drm_device
*dev
,
11210 struct intel_set_config
*config
)
11212 struct drm_crtc
*crtc
;
11213 struct drm_encoder
*encoder
;
11214 struct drm_connector
*connector
;
11217 config
->save_crtc_enabled
=
11218 kcalloc(dev
->mode_config
.num_crtc
,
11219 sizeof(bool), GFP_KERNEL
);
11220 if (!config
->save_crtc_enabled
)
11223 config
->save_encoder_crtcs
=
11224 kcalloc(dev
->mode_config
.num_encoder
,
11225 sizeof(struct drm_crtc
*), GFP_KERNEL
);
11226 if (!config
->save_encoder_crtcs
)
11229 config
->save_connector_encoders
=
11230 kcalloc(dev
->mode_config
.num_connector
,
11231 sizeof(struct drm_encoder
*), GFP_KERNEL
);
11232 if (!config
->save_connector_encoders
)
11235 /* Copy data. Note that driver private data is not affected.
11236 * Should anything bad happen only the expected state is
11237 * restored, not the drivers personal bookkeeping.
11240 for_each_crtc(dev
, crtc
) {
11241 config
->save_crtc_enabled
[count
++] = crtc
->enabled
;
11245 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
11246 config
->save_encoder_crtcs
[count
++] = encoder
->crtc
;
11250 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
11251 config
->save_connector_encoders
[count
++] = connector
->encoder
;
11257 static void intel_set_config_restore_state(struct drm_device
*dev
,
11258 struct intel_set_config
*config
)
11260 struct intel_crtc
*crtc
;
11261 struct intel_encoder
*encoder
;
11262 struct intel_connector
*connector
;
11266 for_each_intel_crtc(dev
, crtc
) {
11267 crtc
->new_enabled
= config
->save_crtc_enabled
[count
++];
11269 if (crtc
->new_enabled
)
11270 crtc
->new_config
= &crtc
->config
;
11272 crtc
->new_config
= NULL
;
11276 for_each_intel_encoder(dev
, encoder
) {
11277 encoder
->new_crtc
=
11278 to_intel_crtc(config
->save_encoder_crtcs
[count
++]);
11282 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
11283 connector
->new_encoder
=
11284 to_intel_encoder(config
->save_connector_encoders
[count
++]);
11289 is_crtc_connector_off(struct drm_mode_set
*set
)
11293 if (set
->num_connectors
== 0)
11296 if (WARN_ON(set
->connectors
== NULL
))
11299 for (i
= 0; i
< set
->num_connectors
; i
++)
11300 if (set
->connectors
[i
]->encoder
&&
11301 set
->connectors
[i
]->encoder
->crtc
== set
->crtc
&&
11302 set
->connectors
[i
]->dpms
!= DRM_MODE_DPMS_ON
)
11309 intel_set_config_compute_mode_changes(struct drm_mode_set
*set
,
11310 struct intel_set_config
*config
)
11313 /* We should be able to check here if the fb has the same properties
11314 * and then just flip_or_move it */
11315 if (is_crtc_connector_off(set
)) {
11316 config
->mode_changed
= true;
11317 } else if (set
->crtc
->primary
->fb
!= set
->fb
) {
11319 * If we have no fb, we can only flip as long as the crtc is
11320 * active, otherwise we need a full mode set. The crtc may
11321 * be active if we've only disabled the primary plane, or
11322 * in fastboot situations.
11324 if (set
->crtc
->primary
->fb
== NULL
) {
11325 struct intel_crtc
*intel_crtc
=
11326 to_intel_crtc(set
->crtc
);
11328 if (intel_crtc
->active
) {
11329 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11330 config
->fb_changed
= true;
11332 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11333 config
->mode_changed
= true;
11335 } else if (set
->fb
== NULL
) {
11336 config
->mode_changed
= true;
11337 } else if (set
->fb
->pixel_format
!=
11338 set
->crtc
->primary
->fb
->pixel_format
) {
11339 config
->mode_changed
= true;
11341 config
->fb_changed
= true;
11345 if (set
->fb
&& (set
->x
!= set
->crtc
->x
|| set
->y
!= set
->crtc
->y
))
11346 config
->fb_changed
= true;
11348 if (set
->mode
&& !drm_mode_equal(set
->mode
, &set
->crtc
->mode
)) {
11349 DRM_DEBUG_KMS("modes are different, full mode set\n");
11350 drm_mode_debug_printmodeline(&set
->crtc
->mode
);
11351 drm_mode_debug_printmodeline(set
->mode
);
11352 config
->mode_changed
= true;
11355 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11356 set
->crtc
->base
.id
, config
->mode_changed
, config
->fb_changed
);
11360 intel_modeset_stage_output_state(struct drm_device
*dev
,
11361 struct drm_mode_set
*set
,
11362 struct intel_set_config
*config
)
11364 struct intel_connector
*connector
;
11365 struct intel_encoder
*encoder
;
11366 struct intel_crtc
*crtc
;
11369 /* The upper layers ensure that we either disable a crtc or have a list
11370 * of connectors. For paranoia, double-check this. */
11371 WARN_ON(!set
->fb
&& (set
->num_connectors
!= 0));
11372 WARN_ON(set
->fb
&& (set
->num_connectors
== 0));
11374 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
11376 /* Otherwise traverse passed in connector list and get encoders
11378 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
11379 if (set
->connectors
[ro
] == &connector
->base
) {
11380 connector
->new_encoder
= intel_find_encoder(connector
, to_intel_crtc(set
->crtc
)->pipe
);
11385 /* If we disable the crtc, disable all its connectors. Also, if
11386 * the connector is on the changing crtc but not on the new
11387 * connector list, disable it. */
11388 if ((!set
->fb
|| ro
== set
->num_connectors
) &&
11389 connector
->base
.encoder
&&
11390 connector
->base
.encoder
->crtc
== set
->crtc
) {
11391 connector
->new_encoder
= NULL
;
11393 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11394 connector
->base
.base
.id
,
11395 connector
->base
.name
);
11399 if (&connector
->new_encoder
->base
!= connector
->base
.encoder
) {
11400 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11401 config
->mode_changed
= true;
11404 /* connector->new_encoder is now updated for all connectors. */
11406 /* Update crtc of enabled connectors. */
11407 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
11409 struct drm_crtc
*new_crtc
;
11411 if (!connector
->new_encoder
)
11414 new_crtc
= connector
->new_encoder
->base
.crtc
;
11416 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
11417 if (set
->connectors
[ro
] == &connector
->base
)
11418 new_crtc
= set
->crtc
;
11421 /* Make sure the new CRTC will work with the encoder */
11422 if (!drm_encoder_crtc_ok(&connector
->new_encoder
->base
,
11426 connector
->new_encoder
->new_crtc
= to_intel_crtc(new_crtc
);
11428 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11429 connector
->base
.base
.id
,
11430 connector
->base
.name
,
11431 new_crtc
->base
.id
);
11434 /* Check for any encoders that needs to be disabled. */
11435 for_each_intel_encoder(dev
, encoder
) {
11436 int num_connectors
= 0;
11437 list_for_each_entry(connector
,
11438 &dev
->mode_config
.connector_list
,
11440 if (connector
->new_encoder
== encoder
) {
11441 WARN_ON(!connector
->new_encoder
->new_crtc
);
11446 if (num_connectors
== 0)
11447 encoder
->new_crtc
= NULL
;
11448 else if (num_connectors
> 1)
11451 /* Only now check for crtc changes so we don't miss encoders
11452 * that will be disabled. */
11453 if (&encoder
->new_crtc
->base
!= encoder
->base
.crtc
) {
11454 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11455 config
->mode_changed
= true;
11458 /* Now we've also updated encoder->new_crtc for all encoders. */
11459 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
11461 if (connector
->new_encoder
)
11462 if (connector
->new_encoder
!= connector
->encoder
)
11463 connector
->encoder
= connector
->new_encoder
;
11465 for_each_intel_crtc(dev
, crtc
) {
11466 crtc
->new_enabled
= false;
11468 for_each_intel_encoder(dev
, encoder
) {
11469 if (encoder
->new_crtc
== crtc
) {
11470 crtc
->new_enabled
= true;
11475 if (crtc
->new_enabled
!= crtc
->base
.enabled
) {
11476 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11477 crtc
->new_enabled
? "en" : "dis");
11478 config
->mode_changed
= true;
11481 if (crtc
->new_enabled
)
11482 crtc
->new_config
= &crtc
->config
;
11484 crtc
->new_config
= NULL
;
11490 static void disable_crtc_nofb(struct intel_crtc
*crtc
)
11492 struct drm_device
*dev
= crtc
->base
.dev
;
11493 struct intel_encoder
*encoder
;
11494 struct intel_connector
*connector
;
11496 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11497 pipe_name(crtc
->pipe
));
11499 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
11500 if (connector
->new_encoder
&&
11501 connector
->new_encoder
->new_crtc
== crtc
)
11502 connector
->new_encoder
= NULL
;
11505 for_each_intel_encoder(dev
, encoder
) {
11506 if (encoder
->new_crtc
== crtc
)
11507 encoder
->new_crtc
= NULL
;
11510 crtc
->new_enabled
= false;
11511 crtc
->new_config
= NULL
;
11514 static int intel_crtc_set_config(struct drm_mode_set
*set
)
11516 struct drm_device
*dev
;
11517 struct drm_mode_set save_set
;
11518 struct intel_set_config
*config
;
11522 BUG_ON(!set
->crtc
);
11523 BUG_ON(!set
->crtc
->helper_private
);
11525 /* Enforce sane interface api - has been abused by the fb helper. */
11526 BUG_ON(!set
->mode
&& set
->fb
);
11527 BUG_ON(set
->fb
&& set
->num_connectors
== 0);
11530 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11531 set
->crtc
->base
.id
, set
->fb
->base
.id
,
11532 (int)set
->num_connectors
, set
->x
, set
->y
);
11534 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set
->crtc
->base
.id
);
11537 dev
= set
->crtc
->dev
;
11540 config
= kzalloc(sizeof(*config
), GFP_KERNEL
);
11544 ret
= intel_set_config_save_state(dev
, config
);
11548 save_set
.crtc
= set
->crtc
;
11549 save_set
.mode
= &set
->crtc
->mode
;
11550 save_set
.x
= set
->crtc
->x
;
11551 save_set
.y
= set
->crtc
->y
;
11552 save_set
.fb
= set
->crtc
->primary
->fb
;
11554 /* Compute whether we need a full modeset, only an fb base update or no
11555 * change at all. In the future we might also check whether only the
11556 * mode changed, e.g. for LVDS where we only change the panel fitter in
11558 intel_set_config_compute_mode_changes(set
, config
);
11560 ret
= intel_modeset_stage_output_state(dev
, set
, config
);
11564 if (config
->mode_changed
) {
11565 ret
= intel_set_mode(set
->crtc
, set
->mode
,
11566 set
->x
, set
->y
, set
->fb
);
11567 } else if (config
->fb_changed
) {
11568 struct intel_crtc
*intel_crtc
= to_intel_crtc(set
->crtc
);
11570 intel_crtc_wait_for_pending_flips(set
->crtc
);
11572 ret
= intel_pipe_set_base(set
->crtc
,
11573 set
->x
, set
->y
, set
->fb
);
11576 * We need to make sure the primary plane is re-enabled if it
11577 * has previously been turned off.
11579 if (!intel_crtc
->primary_enabled
&& ret
== 0) {
11580 WARN_ON(!intel_crtc
->active
);
11581 intel_enable_primary_hw_plane(set
->crtc
->primary
, set
->crtc
);
11585 * In the fastboot case this may be our only check of the
11586 * state after boot. It would be better to only do it on
11587 * the first update, but we don't have a nice way of doing that
11588 * (and really, set_config isn't used much for high freq page
11589 * flipping, so increasing its cost here shouldn't be a big
11592 if (i915
.fastboot
&& ret
== 0)
11593 intel_modeset_check_state(set
->crtc
->dev
);
11597 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11598 set
->crtc
->base
.id
, ret
);
11600 intel_set_config_restore_state(dev
, config
);
11603 * HACK: if the pipe was on, but we didn't have a framebuffer,
11604 * force the pipe off to avoid oopsing in the modeset code
11605 * due to fb==NULL. This should only happen during boot since
11606 * we don't yet reconstruct the FB from the hardware state.
11608 if (to_intel_crtc(save_set
.crtc
)->new_enabled
&& !save_set
.fb
)
11609 disable_crtc_nofb(to_intel_crtc(save_set
.crtc
));
11611 /* Try to restore the config */
11612 if (config
->mode_changed
&&
11613 intel_set_mode(save_set
.crtc
, save_set
.mode
,
11614 save_set
.x
, save_set
.y
, save_set
.fb
))
11615 DRM_ERROR("failed to restore config after modeset failure\n");
11619 intel_set_config_free(config
);
11623 static const struct drm_crtc_funcs intel_crtc_funcs
= {
11624 .gamma_set
= intel_crtc_gamma_set
,
11625 .set_config
= intel_crtc_set_config
,
11626 .destroy
= intel_crtc_destroy
,
11627 .page_flip
= intel_crtc_page_flip
,
11630 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private
*dev_priv
,
11631 struct intel_shared_dpll
*pll
,
11632 struct intel_dpll_hw_state
*hw_state
)
11636 if (!intel_display_power_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
11639 val
= I915_READ(PCH_DPLL(pll
->id
));
11640 hw_state
->dpll
= val
;
11641 hw_state
->fp0
= I915_READ(PCH_FP0(pll
->id
));
11642 hw_state
->fp1
= I915_READ(PCH_FP1(pll
->id
));
11644 return val
& DPLL_VCO_ENABLE
;
11647 static void ibx_pch_dpll_mode_set(struct drm_i915_private
*dev_priv
,
11648 struct intel_shared_dpll
*pll
)
11650 I915_WRITE(PCH_FP0(pll
->id
), pll
->hw_state
.fp0
);
11651 I915_WRITE(PCH_FP1(pll
->id
), pll
->hw_state
.fp1
);
11654 static void ibx_pch_dpll_enable(struct drm_i915_private
*dev_priv
,
11655 struct intel_shared_dpll
*pll
)
11657 /* PCH refclock must be enabled first */
11658 ibx_assert_pch_refclk_enabled(dev_priv
);
11660 I915_WRITE(PCH_DPLL(pll
->id
), pll
->hw_state
.dpll
);
11662 /* Wait for the clocks to stabilize. */
11663 POSTING_READ(PCH_DPLL(pll
->id
));
11666 /* The pixel multiplier can only be updated once the
11667 * DPLL is enabled and the clocks are stable.
11669 * So write it again.
11671 I915_WRITE(PCH_DPLL(pll
->id
), pll
->hw_state
.dpll
);
11672 POSTING_READ(PCH_DPLL(pll
->id
));
11676 static void ibx_pch_dpll_disable(struct drm_i915_private
*dev_priv
,
11677 struct intel_shared_dpll
*pll
)
11679 struct drm_device
*dev
= dev_priv
->dev
;
11680 struct intel_crtc
*crtc
;
11682 /* Make sure no transcoder isn't still depending on us. */
11683 for_each_intel_crtc(dev
, crtc
) {
11684 if (intel_crtc_to_shared_dpll(crtc
) == pll
)
11685 assert_pch_transcoder_disabled(dev_priv
, crtc
->pipe
);
11688 I915_WRITE(PCH_DPLL(pll
->id
), 0);
11689 POSTING_READ(PCH_DPLL(pll
->id
));
11693 static char *ibx_pch_dpll_names
[] = {
11698 static void ibx_pch_dpll_init(struct drm_device
*dev
)
11700 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11703 dev_priv
->num_shared_dpll
= 2;
11705 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
11706 dev_priv
->shared_dplls
[i
].id
= i
;
11707 dev_priv
->shared_dplls
[i
].name
= ibx_pch_dpll_names
[i
];
11708 dev_priv
->shared_dplls
[i
].mode_set
= ibx_pch_dpll_mode_set
;
11709 dev_priv
->shared_dplls
[i
].enable
= ibx_pch_dpll_enable
;
11710 dev_priv
->shared_dplls
[i
].disable
= ibx_pch_dpll_disable
;
11711 dev_priv
->shared_dplls
[i
].get_hw_state
=
11712 ibx_pch_dpll_get_hw_state
;
11716 static void intel_shared_dpll_init(struct drm_device
*dev
)
11718 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11721 intel_ddi_pll_init(dev
);
11722 else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
11723 ibx_pch_dpll_init(dev
);
11725 dev_priv
->num_shared_dpll
= 0;
11727 BUG_ON(dev_priv
->num_shared_dpll
> I915_NUM_PLLS
);
11731 intel_primary_plane_disable(struct drm_plane
*plane
)
11733 struct drm_device
*dev
= plane
->dev
;
11734 struct intel_crtc
*intel_crtc
;
11739 BUG_ON(!plane
->crtc
);
11741 intel_crtc
= to_intel_crtc(plane
->crtc
);
11744 * Even though we checked plane->fb above, it's still possible that
11745 * the primary plane has been implicitly disabled because the crtc
11746 * coordinates given weren't visible, or because we detected
11747 * that it was 100% covered by a sprite plane. Or, the CRTC may be
11748 * off and we've set a fb, but haven't actually turned on the CRTC yet.
11749 * In either case, we need to unpin the FB and let the fb pointer get
11750 * updated, but otherwise we don't need to touch the hardware.
11752 if (!intel_crtc
->primary_enabled
)
11753 goto disable_unpin
;
11755 intel_crtc_wait_for_pending_flips(plane
->crtc
);
11756 intel_disable_primary_hw_plane(plane
, plane
->crtc
);
11759 mutex_lock(&dev
->struct_mutex
);
11760 i915_gem_track_fb(intel_fb_obj(plane
->fb
), NULL
,
11761 INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
));
11762 intel_unpin_fb_obj(intel_fb_obj(plane
->fb
));
11763 mutex_unlock(&dev
->struct_mutex
);
11770 intel_check_primary_plane(struct drm_plane
*plane
,
11771 struct intel_plane_state
*state
)
11773 struct drm_crtc
*crtc
= state
->crtc
;
11774 struct drm_framebuffer
*fb
= state
->fb
;
11775 struct drm_rect
*dest
= &state
->dst
;
11776 struct drm_rect
*src
= &state
->src
;
11777 const struct drm_rect
*clip
= &state
->clip
;
11779 return drm_plane_helper_check_update(plane
, crtc
, fb
,
11781 DRM_PLANE_HELPER_NO_SCALING
,
11782 DRM_PLANE_HELPER_NO_SCALING
,
11783 false, true, &state
->visible
);
11787 intel_commit_primary_plane(struct drm_plane
*plane
,
11788 struct intel_plane_state
*state
)
11790 struct drm_crtc
*crtc
= state
->crtc
;
11791 struct drm_framebuffer
*fb
= state
->fb
;
11792 struct drm_device
*dev
= crtc
->dev
;
11793 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11794 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11795 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
11796 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(plane
->fb
);
11797 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
11798 struct drm_rect
*src
= &state
->src
;
11801 intel_crtc_wait_for_pending_flips(crtc
);
11804 * If clipping results in a non-visible primary plane, we'll disable
11805 * the primary plane. Note that this is a bit different than what
11806 * happens if userspace explicitly disables the plane by passing fb=0
11807 * because plane->fb still gets set and pinned.
11809 if (!state
->visible
) {
11810 mutex_lock(&dev
->struct_mutex
);
11813 * Try to pin the new fb first so that we can bail out if we
11816 if (plane
->fb
!= fb
) {
11817 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, NULL
);
11819 mutex_unlock(&dev
->struct_mutex
);
11824 i915_gem_track_fb(old_obj
, obj
,
11825 INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
));
11827 if (intel_crtc
->primary_enabled
)
11828 intel_disable_primary_hw_plane(plane
, crtc
);
11831 if (plane
->fb
!= fb
)
11833 intel_unpin_fb_obj(old_obj
);
11835 mutex_unlock(&dev
->struct_mutex
);
11838 if (intel_crtc
&& intel_crtc
->active
&&
11839 intel_crtc
->primary_enabled
) {
11841 * FBC does not work on some platforms for rotated
11842 * planes, so disable it when rotation is not 0 and
11843 * update it when rotation is set back to 0.
11845 * FIXME: This is redundant with the fbc update done in
11846 * the primary plane enable function except that that
11847 * one is done too late. We eventually need to unify
11850 if (INTEL_INFO(dev
)->gen
<= 4 && !IS_G4X(dev
) &&
11851 dev_priv
->fbc
.plane
== intel_crtc
->plane
&&
11852 intel_plane
->rotation
!= BIT(DRM_ROTATE_0
)) {
11853 intel_disable_fbc(dev
);
11856 ret
= intel_pipe_set_base(crtc
, src
->x1
, src
->y1
, fb
);
11860 if (!intel_crtc
->primary_enabled
)
11861 intel_enable_primary_hw_plane(plane
, crtc
);
11864 intel_plane
->crtc_x
= state
->orig_dst
.x1
;
11865 intel_plane
->crtc_y
= state
->orig_dst
.y1
;
11866 intel_plane
->crtc_w
= drm_rect_width(&state
->orig_dst
);
11867 intel_plane
->crtc_h
= drm_rect_height(&state
->orig_dst
);
11868 intel_plane
->src_x
= state
->orig_src
.x1
;
11869 intel_plane
->src_y
= state
->orig_src
.y1
;
11870 intel_plane
->src_w
= drm_rect_width(&state
->orig_src
);
11871 intel_plane
->src_h
= drm_rect_height(&state
->orig_src
);
11872 intel_plane
->obj
= obj
;
11878 intel_primary_plane_setplane(struct drm_plane
*plane
, struct drm_crtc
*crtc
,
11879 struct drm_framebuffer
*fb
, int crtc_x
, int crtc_y
,
11880 unsigned int crtc_w
, unsigned int crtc_h
,
11881 uint32_t src_x
, uint32_t src_y
,
11882 uint32_t src_w
, uint32_t src_h
)
11884 struct intel_plane_state state
;
11885 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11891 /* sample coordinates in 16.16 fixed point */
11892 state
.src
.x1
= src_x
;
11893 state
.src
.x2
= src_x
+ src_w
;
11894 state
.src
.y1
= src_y
;
11895 state
.src
.y2
= src_y
+ src_h
;
11897 /* integer pixels */
11898 state
.dst
.x1
= crtc_x
;
11899 state
.dst
.x2
= crtc_x
+ crtc_w
;
11900 state
.dst
.y1
= crtc_y
;
11901 state
.dst
.y2
= crtc_y
+ crtc_h
;
11905 state
.clip
.x2
= intel_crtc
->active
? intel_crtc
->config
.pipe_src_w
: 0;
11906 state
.clip
.y2
= intel_crtc
->active
? intel_crtc
->config
.pipe_src_h
: 0;
11908 state
.orig_src
= state
.src
;
11909 state
.orig_dst
= state
.dst
;
11911 ret
= intel_check_primary_plane(plane
, &state
);
11915 intel_commit_primary_plane(plane
, &state
);
11920 /* Common destruction function for both primary and cursor planes */
11921 static void intel_plane_destroy(struct drm_plane
*plane
)
11923 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
11924 drm_plane_cleanup(plane
);
11925 kfree(intel_plane
);
11928 static const struct drm_plane_funcs intel_primary_plane_funcs
= {
11929 .update_plane
= intel_primary_plane_setplane
,
11930 .disable_plane
= intel_primary_plane_disable
,
11931 .destroy
= intel_plane_destroy
,
11932 .set_property
= intel_plane_set_property
11935 static struct drm_plane
*intel_primary_plane_create(struct drm_device
*dev
,
11938 struct intel_plane
*primary
;
11939 const uint32_t *intel_primary_formats
;
11942 primary
= kzalloc(sizeof(*primary
), GFP_KERNEL
);
11943 if (primary
== NULL
)
11946 primary
->can_scale
= false;
11947 primary
->max_downscale
= 1;
11948 primary
->pipe
= pipe
;
11949 primary
->plane
= pipe
;
11950 primary
->rotation
= BIT(DRM_ROTATE_0
);
11951 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4)
11952 primary
->plane
= !pipe
;
11954 if (INTEL_INFO(dev
)->gen
<= 3) {
11955 intel_primary_formats
= intel_primary_formats_gen2
;
11956 num_formats
= ARRAY_SIZE(intel_primary_formats_gen2
);
11958 intel_primary_formats
= intel_primary_formats_gen4
;
11959 num_formats
= ARRAY_SIZE(intel_primary_formats_gen4
);
11962 drm_universal_plane_init(dev
, &primary
->base
, 0,
11963 &intel_primary_plane_funcs
,
11964 intel_primary_formats
, num_formats
,
11965 DRM_PLANE_TYPE_PRIMARY
);
11967 if (INTEL_INFO(dev
)->gen
>= 4) {
11968 if (!dev
->mode_config
.rotation_property
)
11969 dev
->mode_config
.rotation_property
=
11970 drm_mode_create_rotation_property(dev
,
11971 BIT(DRM_ROTATE_0
) |
11972 BIT(DRM_ROTATE_180
));
11973 if (dev
->mode_config
.rotation_property
)
11974 drm_object_attach_property(&primary
->base
.base
,
11975 dev
->mode_config
.rotation_property
,
11976 primary
->rotation
);
11979 return &primary
->base
;
11983 intel_cursor_plane_disable(struct drm_plane
*plane
)
11988 BUG_ON(!plane
->crtc
);
11990 return intel_crtc_cursor_set_obj(plane
->crtc
, NULL
, 0, 0);
11994 intel_check_cursor_plane(struct drm_plane
*plane
,
11995 struct intel_plane_state
*state
)
11997 struct drm_crtc
*crtc
= state
->crtc
;
11998 struct drm_framebuffer
*fb
= state
->fb
;
11999 struct drm_rect
*dest
= &state
->dst
;
12000 struct drm_rect
*src
= &state
->src
;
12001 const struct drm_rect
*clip
= &state
->clip
;
12003 return drm_plane_helper_check_update(plane
, crtc
, fb
,
12005 DRM_PLANE_HELPER_NO_SCALING
,
12006 DRM_PLANE_HELPER_NO_SCALING
,
12007 true, true, &state
->visible
);
12011 intel_commit_cursor_plane(struct drm_plane
*plane
,
12012 struct intel_plane_state
*state
)
12014 struct drm_crtc
*crtc
= state
->crtc
;
12015 struct drm_framebuffer
*fb
= state
->fb
;
12016 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
12017 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
12018 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
12019 int crtc_w
, crtc_h
;
12021 crtc
->cursor_x
= state
->orig_dst
.x1
;
12022 crtc
->cursor_y
= state
->orig_dst
.y1
;
12023 if (fb
!= crtc
->cursor
->fb
) {
12024 crtc_w
= drm_rect_width(&state
->orig_dst
);
12025 crtc_h
= drm_rect_height(&state
->orig_dst
);
12026 return intel_crtc_cursor_set_obj(crtc
, obj
, crtc_w
, crtc_h
);
12028 intel_crtc_update_cursor(crtc
, state
->visible
);
12030 intel_frontbuffer_flip(crtc
->dev
,
12031 INTEL_FRONTBUFFER_CURSOR(intel_crtc
->pipe
));
12038 intel_cursor_plane_update(struct drm_plane
*plane
, struct drm_crtc
*crtc
,
12039 struct drm_framebuffer
*fb
, int crtc_x
, int crtc_y
,
12040 unsigned int crtc_w
, unsigned int crtc_h
,
12041 uint32_t src_x
, uint32_t src_y
,
12042 uint32_t src_w
, uint32_t src_h
)
12044 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
12045 struct intel_plane_state state
;
12051 /* sample coordinates in 16.16 fixed point */
12052 state
.src
.x1
= src_x
;
12053 state
.src
.x2
= src_x
+ src_w
;
12054 state
.src
.y1
= src_y
;
12055 state
.src
.y2
= src_y
+ src_h
;
12057 /* integer pixels */
12058 state
.dst
.x1
= crtc_x
;
12059 state
.dst
.x2
= crtc_x
+ crtc_w
;
12060 state
.dst
.y1
= crtc_y
;
12061 state
.dst
.y2
= crtc_y
+ crtc_h
;
12065 state
.clip
.x2
= intel_crtc
->active
? intel_crtc
->config
.pipe_src_w
: 0;
12066 state
.clip
.y2
= intel_crtc
->active
? intel_crtc
->config
.pipe_src_h
: 0;
12068 state
.orig_src
= state
.src
;
12069 state
.orig_dst
= state
.dst
;
12071 ret
= intel_check_cursor_plane(plane
, &state
);
12075 return intel_commit_cursor_plane(plane
, &state
);
12078 static const struct drm_plane_funcs intel_cursor_plane_funcs
= {
12079 .update_plane
= intel_cursor_plane_update
,
12080 .disable_plane
= intel_cursor_plane_disable
,
12081 .destroy
= intel_plane_destroy
,
12084 static struct drm_plane
*intel_cursor_plane_create(struct drm_device
*dev
,
12087 struct intel_plane
*cursor
;
12089 cursor
= kzalloc(sizeof(*cursor
), GFP_KERNEL
);
12090 if (cursor
== NULL
)
12093 cursor
->can_scale
= false;
12094 cursor
->max_downscale
= 1;
12095 cursor
->pipe
= pipe
;
12096 cursor
->plane
= pipe
;
12098 drm_universal_plane_init(dev
, &cursor
->base
, 0,
12099 &intel_cursor_plane_funcs
,
12100 intel_cursor_formats
,
12101 ARRAY_SIZE(intel_cursor_formats
),
12102 DRM_PLANE_TYPE_CURSOR
);
12103 return &cursor
->base
;
12106 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
12108 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12109 struct intel_crtc
*intel_crtc
;
12110 struct drm_plane
*primary
= NULL
;
12111 struct drm_plane
*cursor
= NULL
;
12114 intel_crtc
= kzalloc(sizeof(*intel_crtc
), GFP_KERNEL
);
12115 if (intel_crtc
== NULL
)
12118 primary
= intel_primary_plane_create(dev
, pipe
);
12122 cursor
= intel_cursor_plane_create(dev
, pipe
);
12126 ret
= drm_crtc_init_with_planes(dev
, &intel_crtc
->base
, primary
,
12127 cursor
, &intel_crtc_funcs
);
12131 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
12132 for (i
= 0; i
< 256; i
++) {
12133 intel_crtc
->lut_r
[i
] = i
;
12134 intel_crtc
->lut_g
[i
] = i
;
12135 intel_crtc
->lut_b
[i
] = i
;
12139 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12140 * is hooked to pipe B. Hence we want plane A feeding pipe B.
12142 intel_crtc
->pipe
= pipe
;
12143 intel_crtc
->plane
= pipe
;
12144 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4) {
12145 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12146 intel_crtc
->plane
= !pipe
;
12149 intel_crtc
->cursor_base
= ~0;
12150 intel_crtc
->cursor_cntl
= ~0;
12151 intel_crtc
->cursor_size
= ~0;
12153 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
12154 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
12155 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
12156 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
12158 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
12160 WARN_ON(drm_crtc_index(&intel_crtc
->base
) != intel_crtc
->pipe
);
12165 drm_plane_cleanup(primary
);
12167 drm_plane_cleanup(cursor
);
12171 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
)
12173 struct drm_encoder
*encoder
= connector
->base
.encoder
;
12174 struct drm_device
*dev
= connector
->base
.dev
;
12176 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
12179 return INVALID_PIPE
;
12181 return to_intel_crtc(encoder
->crtc
)->pipe
;
12184 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
12185 struct drm_file
*file
)
12187 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
12188 struct drm_crtc
*drmmode_crtc
;
12189 struct intel_crtc
*crtc
;
12191 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
12194 drmmode_crtc
= drm_crtc_find(dev
, pipe_from_crtc_id
->crtc_id
);
12196 if (!drmmode_crtc
) {
12197 DRM_ERROR("no such CRTC id\n");
12201 crtc
= to_intel_crtc(drmmode_crtc
);
12202 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
12207 static int intel_encoder_clones(struct intel_encoder
*encoder
)
12209 struct drm_device
*dev
= encoder
->base
.dev
;
12210 struct intel_encoder
*source_encoder
;
12211 int index_mask
= 0;
12214 for_each_intel_encoder(dev
, source_encoder
) {
12215 if (encoders_cloneable(encoder
, source_encoder
))
12216 index_mask
|= (1 << entry
);
12224 static bool has_edp_a(struct drm_device
*dev
)
12226 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12228 if (!IS_MOBILE(dev
))
12231 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
12234 if (IS_GEN5(dev
) && (I915_READ(FUSE_STRAP
) & ILK_eDP_A_DISABLE
))
12240 const char *intel_output_name(int output
)
12242 static const char *names
[] = {
12243 [INTEL_OUTPUT_UNUSED
] = "Unused",
12244 [INTEL_OUTPUT_ANALOG
] = "Analog",
12245 [INTEL_OUTPUT_DVO
] = "DVO",
12246 [INTEL_OUTPUT_SDVO
] = "SDVO",
12247 [INTEL_OUTPUT_LVDS
] = "LVDS",
12248 [INTEL_OUTPUT_TVOUT
] = "TV",
12249 [INTEL_OUTPUT_HDMI
] = "HDMI",
12250 [INTEL_OUTPUT_DISPLAYPORT
] = "DisplayPort",
12251 [INTEL_OUTPUT_EDP
] = "eDP",
12252 [INTEL_OUTPUT_DSI
] = "DSI",
12253 [INTEL_OUTPUT_UNKNOWN
] = "Unknown",
12256 if (output
< 0 || output
>= ARRAY_SIZE(names
) || !names
[output
])
12259 return names
[output
];
12262 static bool intel_crt_present(struct drm_device
*dev
)
12264 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12269 if (IS_CHERRYVIEW(dev
))
12272 if (IS_VALLEYVIEW(dev
) && !dev_priv
->vbt
.int_crt_support
)
12278 static void intel_setup_outputs(struct drm_device
*dev
)
12280 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12281 struct intel_encoder
*encoder
;
12282 bool dpd_is_edp
= false;
12284 intel_lvds_init(dev
);
12286 if (intel_crt_present(dev
))
12287 intel_crt_init(dev
);
12289 if (HAS_DDI(dev
)) {
12292 /* Haswell uses DDI functions to detect digital outputs */
12293 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
12294 /* DDI A only supports eDP */
12296 intel_ddi_init(dev
, PORT_A
);
12298 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12300 found
= I915_READ(SFUSE_STRAP
);
12302 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
12303 intel_ddi_init(dev
, PORT_B
);
12304 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
12305 intel_ddi_init(dev
, PORT_C
);
12306 if (found
& SFUSE_STRAP_DDID_DETECTED
)
12307 intel_ddi_init(dev
, PORT_D
);
12308 } else if (HAS_PCH_SPLIT(dev
)) {
12310 dpd_is_edp
= intel_dp_is_edp(dev
, PORT_D
);
12312 if (has_edp_a(dev
))
12313 intel_dp_init(dev
, DP_A
, PORT_A
);
12315 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
12316 /* PCH SDVOB multiplex with HDMIB */
12317 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
12319 intel_hdmi_init(dev
, PCH_HDMIB
, PORT_B
);
12320 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
12321 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
12324 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
12325 intel_hdmi_init(dev
, PCH_HDMIC
, PORT_C
);
12327 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
12328 intel_hdmi_init(dev
, PCH_HDMID
, PORT_D
);
12330 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
12331 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
12333 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
12334 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
12335 } else if (IS_VALLEYVIEW(dev
)) {
12336 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIB
) & SDVO_DETECTED
) {
12337 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIB
,
12339 if (I915_READ(VLV_DISPLAY_BASE
+ DP_B
) & DP_DETECTED
)
12340 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_B
, PORT_B
);
12343 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIC
) & SDVO_DETECTED
) {
12344 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIC
,
12346 if (I915_READ(VLV_DISPLAY_BASE
+ DP_C
) & DP_DETECTED
)
12347 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_C
, PORT_C
);
12350 if (IS_CHERRYVIEW(dev
)) {
12351 if (I915_READ(VLV_DISPLAY_BASE
+ CHV_HDMID
) & SDVO_DETECTED
) {
12352 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ CHV_HDMID
,
12354 if (I915_READ(VLV_DISPLAY_BASE
+ DP_D
) & DP_DETECTED
)
12355 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_D
, PORT_D
);
12359 intel_dsi_init(dev
);
12360 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
12361 bool found
= false;
12363 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
12364 DRM_DEBUG_KMS("probing SDVOB\n");
12365 found
= intel_sdvo_init(dev
, GEN3_SDVOB
, true);
12366 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
12367 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12368 intel_hdmi_init(dev
, GEN4_HDMIB
, PORT_B
);
12371 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
))
12372 intel_dp_init(dev
, DP_B
, PORT_B
);
12375 /* Before G4X SDVOC doesn't have its own detect register */
12377 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
12378 DRM_DEBUG_KMS("probing SDVOC\n");
12379 found
= intel_sdvo_init(dev
, GEN3_SDVOC
, false);
12382 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
12384 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
12385 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12386 intel_hdmi_init(dev
, GEN4_HDMIC
, PORT_C
);
12388 if (SUPPORTS_INTEGRATED_DP(dev
))
12389 intel_dp_init(dev
, DP_C
, PORT_C
);
12392 if (SUPPORTS_INTEGRATED_DP(dev
) &&
12393 (I915_READ(DP_D
) & DP_DETECTED
))
12394 intel_dp_init(dev
, DP_D
, PORT_D
);
12395 } else if (IS_GEN2(dev
))
12396 intel_dvo_init(dev
);
12398 if (SUPPORTS_TV(dev
))
12399 intel_tv_init(dev
);
12401 intel_edp_psr_init(dev
);
12403 for_each_intel_encoder(dev
, encoder
) {
12404 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
12405 encoder
->base
.possible_clones
=
12406 intel_encoder_clones(encoder
);
12409 intel_init_pch_refclk(dev
);
12411 drm_helper_move_panel_connectors_to_head(dev
);
12414 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
12416 struct drm_device
*dev
= fb
->dev
;
12417 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
12419 drm_framebuffer_cleanup(fb
);
12420 mutex_lock(&dev
->struct_mutex
);
12421 WARN_ON(!intel_fb
->obj
->framebuffer_references
--);
12422 drm_gem_object_unreference(&intel_fb
->obj
->base
);
12423 mutex_unlock(&dev
->struct_mutex
);
12427 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
12428 struct drm_file
*file
,
12429 unsigned int *handle
)
12431 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
12432 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
12434 return drm_gem_handle_create(file
, &obj
->base
, handle
);
12437 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
12438 .destroy
= intel_user_framebuffer_destroy
,
12439 .create_handle
= intel_user_framebuffer_create_handle
,
12442 static int intel_framebuffer_init(struct drm_device
*dev
,
12443 struct intel_framebuffer
*intel_fb
,
12444 struct drm_mode_fb_cmd2
*mode_cmd
,
12445 struct drm_i915_gem_object
*obj
)
12447 int aligned_height
;
12451 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
12453 if (obj
->tiling_mode
== I915_TILING_Y
) {
12454 DRM_DEBUG("hardware does not support tiling Y\n");
12458 if (mode_cmd
->pitches
[0] & 63) {
12459 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12460 mode_cmd
->pitches
[0]);
12464 if (INTEL_INFO(dev
)->gen
>= 5 && !IS_VALLEYVIEW(dev
)) {
12465 pitch_limit
= 32*1024;
12466 } else if (INTEL_INFO(dev
)->gen
>= 4) {
12467 if (obj
->tiling_mode
)
12468 pitch_limit
= 16*1024;
12470 pitch_limit
= 32*1024;
12471 } else if (INTEL_INFO(dev
)->gen
>= 3) {
12472 if (obj
->tiling_mode
)
12473 pitch_limit
= 8*1024;
12475 pitch_limit
= 16*1024;
12477 /* XXX DSPC is limited to 4k tiled */
12478 pitch_limit
= 8*1024;
12480 if (mode_cmd
->pitches
[0] > pitch_limit
) {
12481 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12482 obj
->tiling_mode
? "tiled" : "linear",
12483 mode_cmd
->pitches
[0], pitch_limit
);
12487 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
12488 mode_cmd
->pitches
[0] != obj
->stride
) {
12489 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12490 mode_cmd
->pitches
[0], obj
->stride
);
12494 /* Reject formats not supported by any plane early. */
12495 switch (mode_cmd
->pixel_format
) {
12496 case DRM_FORMAT_C8
:
12497 case DRM_FORMAT_RGB565
:
12498 case DRM_FORMAT_XRGB8888
:
12499 case DRM_FORMAT_ARGB8888
:
12501 case DRM_FORMAT_XRGB1555
:
12502 case DRM_FORMAT_ARGB1555
:
12503 if (INTEL_INFO(dev
)->gen
> 3) {
12504 DRM_DEBUG("unsupported pixel format: %s\n",
12505 drm_get_format_name(mode_cmd
->pixel_format
));
12509 case DRM_FORMAT_XBGR8888
:
12510 case DRM_FORMAT_ABGR8888
:
12511 case DRM_FORMAT_XRGB2101010
:
12512 case DRM_FORMAT_ARGB2101010
:
12513 case DRM_FORMAT_XBGR2101010
:
12514 case DRM_FORMAT_ABGR2101010
:
12515 if (INTEL_INFO(dev
)->gen
< 4) {
12516 DRM_DEBUG("unsupported pixel format: %s\n",
12517 drm_get_format_name(mode_cmd
->pixel_format
));
12521 case DRM_FORMAT_YUYV
:
12522 case DRM_FORMAT_UYVY
:
12523 case DRM_FORMAT_YVYU
:
12524 case DRM_FORMAT_VYUY
:
12525 if (INTEL_INFO(dev
)->gen
< 5) {
12526 DRM_DEBUG("unsupported pixel format: %s\n",
12527 drm_get_format_name(mode_cmd
->pixel_format
));
12532 DRM_DEBUG("unsupported pixel format: %s\n",
12533 drm_get_format_name(mode_cmd
->pixel_format
));
12537 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12538 if (mode_cmd
->offsets
[0] != 0)
12541 aligned_height
= intel_align_height(dev
, mode_cmd
->height
,
12543 /* FIXME drm helper for size checks (especially planar formats)? */
12544 if (obj
->base
.size
< aligned_height
* mode_cmd
->pitches
[0])
12547 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
12548 intel_fb
->obj
= obj
;
12549 intel_fb
->obj
->framebuffer_references
++;
12551 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
12553 DRM_ERROR("framebuffer init failed %d\n", ret
);
12560 static struct drm_framebuffer
*
12561 intel_user_framebuffer_create(struct drm_device
*dev
,
12562 struct drm_file
*filp
,
12563 struct drm_mode_fb_cmd2
*mode_cmd
)
12565 struct drm_i915_gem_object
*obj
;
12567 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
12568 mode_cmd
->handles
[0]));
12569 if (&obj
->base
== NULL
)
12570 return ERR_PTR(-ENOENT
);
12572 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
12575 #ifndef CONFIG_DRM_I915_FBDEV
12576 static inline void intel_fbdev_output_poll_changed(struct drm_device
*dev
)
12581 static const struct drm_mode_config_funcs intel_mode_funcs
= {
12582 .fb_create
= intel_user_framebuffer_create
,
12583 .output_poll_changed
= intel_fbdev_output_poll_changed
,
12586 /* Set up chip specific display functions */
12587 static void intel_init_display(struct drm_device
*dev
)
12589 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12591 if (HAS_PCH_SPLIT(dev
) || IS_G4X(dev
))
12592 dev_priv
->display
.find_dpll
= g4x_find_best_dpll
;
12593 else if (IS_CHERRYVIEW(dev
))
12594 dev_priv
->display
.find_dpll
= chv_find_best_dpll
;
12595 else if (IS_VALLEYVIEW(dev
))
12596 dev_priv
->display
.find_dpll
= vlv_find_best_dpll
;
12597 else if (IS_PINEVIEW(dev
))
12598 dev_priv
->display
.find_dpll
= pnv_find_best_dpll
;
12600 dev_priv
->display
.find_dpll
= i9xx_find_best_dpll
;
12602 if (HAS_DDI(dev
)) {
12603 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
12604 dev_priv
->display
.get_plane_config
= ironlake_get_plane_config
;
12605 dev_priv
->display
.crtc_mode_set
= haswell_crtc_mode_set
;
12606 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
12607 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
12608 dev_priv
->display
.off
= ironlake_crtc_off
;
12609 dev_priv
->display
.update_primary_plane
=
12610 ironlake_update_primary_plane
;
12611 } else if (HAS_PCH_SPLIT(dev
)) {
12612 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
12613 dev_priv
->display
.get_plane_config
= ironlake_get_plane_config
;
12614 dev_priv
->display
.crtc_mode_set
= ironlake_crtc_mode_set
;
12615 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
12616 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
12617 dev_priv
->display
.off
= ironlake_crtc_off
;
12618 dev_priv
->display
.update_primary_plane
=
12619 ironlake_update_primary_plane
;
12620 } else if (IS_VALLEYVIEW(dev
)) {
12621 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
12622 dev_priv
->display
.get_plane_config
= i9xx_get_plane_config
;
12623 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
12624 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
12625 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
12626 dev_priv
->display
.off
= i9xx_crtc_off
;
12627 dev_priv
->display
.update_primary_plane
=
12628 i9xx_update_primary_plane
;
12630 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
12631 dev_priv
->display
.get_plane_config
= i9xx_get_plane_config
;
12632 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
12633 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
12634 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
12635 dev_priv
->display
.off
= i9xx_crtc_off
;
12636 dev_priv
->display
.update_primary_plane
=
12637 i9xx_update_primary_plane
;
12640 /* Returns the core display clock speed */
12641 if (IS_VALLEYVIEW(dev
))
12642 dev_priv
->display
.get_display_clock_speed
=
12643 valleyview_get_display_clock_speed
;
12644 else if (IS_I945G(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
12645 dev_priv
->display
.get_display_clock_speed
=
12646 i945_get_display_clock_speed
;
12647 else if (IS_I915G(dev
))
12648 dev_priv
->display
.get_display_clock_speed
=
12649 i915_get_display_clock_speed
;
12650 else if (IS_I945GM(dev
) || IS_845G(dev
))
12651 dev_priv
->display
.get_display_clock_speed
=
12652 i9xx_misc_get_display_clock_speed
;
12653 else if (IS_PINEVIEW(dev
))
12654 dev_priv
->display
.get_display_clock_speed
=
12655 pnv_get_display_clock_speed
;
12656 else if (IS_I915GM(dev
))
12657 dev_priv
->display
.get_display_clock_speed
=
12658 i915gm_get_display_clock_speed
;
12659 else if (IS_I865G(dev
))
12660 dev_priv
->display
.get_display_clock_speed
=
12661 i865_get_display_clock_speed
;
12662 else if (IS_I85X(dev
))
12663 dev_priv
->display
.get_display_clock_speed
=
12664 i855_get_display_clock_speed
;
12665 else /* 852, 830 */
12666 dev_priv
->display
.get_display_clock_speed
=
12667 i830_get_display_clock_speed
;
12670 dev_priv
->display
.write_eld
= g4x_write_eld
;
12671 } else if (IS_GEN5(dev
)) {
12672 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
12673 dev_priv
->display
.write_eld
= ironlake_write_eld
;
12674 } else if (IS_GEN6(dev
)) {
12675 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
12676 dev_priv
->display
.write_eld
= ironlake_write_eld
;
12677 dev_priv
->display
.modeset_global_resources
=
12678 snb_modeset_global_resources
;
12679 } else if (IS_IVYBRIDGE(dev
)) {
12680 /* FIXME: detect B0+ stepping and use auto training */
12681 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
12682 dev_priv
->display
.write_eld
= ironlake_write_eld
;
12683 dev_priv
->display
.modeset_global_resources
=
12684 ivb_modeset_global_resources
;
12685 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
12686 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
12687 dev_priv
->display
.write_eld
= haswell_write_eld
;
12688 dev_priv
->display
.modeset_global_resources
=
12689 haswell_modeset_global_resources
;
12690 } else if (IS_VALLEYVIEW(dev
)) {
12691 dev_priv
->display
.modeset_global_resources
=
12692 valleyview_modeset_global_resources
;
12693 dev_priv
->display
.write_eld
= ironlake_write_eld
;
12696 /* Default just returns -ENODEV to indicate unsupported */
12697 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
12699 switch (INTEL_INFO(dev
)->gen
) {
12701 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
12705 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
12710 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
12714 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
12717 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12718 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
12722 intel_panel_init_backlight_funcs(dev
);
12724 mutex_init(&dev_priv
->pps_mutex
);
12728 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12729 * resume, or other times. This quirk makes sure that's the case for
12730 * affected systems.
12732 static void quirk_pipea_force(struct drm_device
*dev
)
12734 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12736 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
12737 DRM_INFO("applying pipe a force quirk\n");
12740 static void quirk_pipeb_force(struct drm_device
*dev
)
12742 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12744 dev_priv
->quirks
|= QUIRK_PIPEB_FORCE
;
12745 DRM_INFO("applying pipe b force quirk\n");
12749 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12751 static void quirk_ssc_force_disable(struct drm_device
*dev
)
12753 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12754 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
12755 DRM_INFO("applying lvds SSC disable quirk\n");
12759 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12762 static void quirk_invert_brightness(struct drm_device
*dev
)
12764 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12765 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
12766 DRM_INFO("applying inverted panel brightness quirk\n");
12769 /* Some VBT's incorrectly indicate no backlight is present */
12770 static void quirk_backlight_present(struct drm_device
*dev
)
12772 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12773 dev_priv
->quirks
|= QUIRK_BACKLIGHT_PRESENT
;
12774 DRM_INFO("applying backlight present quirk\n");
12777 struct intel_quirk
{
12779 int subsystem_vendor
;
12780 int subsystem_device
;
12781 void (*hook
)(struct drm_device
*dev
);
12784 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12785 struct intel_dmi_quirk
{
12786 void (*hook
)(struct drm_device
*dev
);
12787 const struct dmi_system_id (*dmi_id_list
)[];
12790 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
12792 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
12796 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
12798 .dmi_id_list
= &(const struct dmi_system_id
[]) {
12800 .callback
= intel_dmi_reverse_brightness
,
12801 .ident
= "NCR Corporation",
12802 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
12803 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
12806 { } /* terminating entry */
12808 .hook
= quirk_invert_brightness
,
12812 static struct intel_quirk intel_quirks
[] = {
12813 /* HP Mini needs pipe A force quirk (LP: #322104) */
12814 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force
},
12816 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12817 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
12819 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12820 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
12822 /* 830 needs to leave pipe A & dpll A up */
12823 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
12825 /* 830 needs to leave pipe B & dpll B up */
12826 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipeb_force
},
12828 /* Lenovo U160 cannot use SSC on LVDS */
12829 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
12831 /* Sony Vaio Y cannot use SSC on LVDS */
12832 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
12834 /* Acer Aspire 5734Z must invert backlight brightness */
12835 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
12837 /* Acer/eMachines G725 */
12838 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness
},
12840 /* Acer/eMachines e725 */
12841 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness
},
12843 /* Acer/Packard Bell NCL20 */
12844 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness
},
12846 /* Acer Aspire 4736Z */
12847 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness
},
12849 /* Acer Aspire 5336 */
12850 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness
},
12852 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12853 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present
},
12855 /* Acer C720 Chromebook (Core i3 4005U) */
12856 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present
},
12858 /* Toshiba CB35 Chromebook (Celeron 2955U) */
12859 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present
},
12861 /* HP Chromebook 14 (Celeron 2955U) */
12862 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present
},
12865 static void intel_init_quirks(struct drm_device
*dev
)
12867 struct pci_dev
*d
= dev
->pdev
;
12870 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
12871 struct intel_quirk
*q
= &intel_quirks
[i
];
12873 if (d
->device
== q
->device
&&
12874 (d
->subsystem_vendor
== q
->subsystem_vendor
||
12875 q
->subsystem_vendor
== PCI_ANY_ID
) &&
12876 (d
->subsystem_device
== q
->subsystem_device
||
12877 q
->subsystem_device
== PCI_ANY_ID
))
12880 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
12881 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
12882 intel_dmi_quirks
[i
].hook(dev
);
12886 /* Disable the VGA plane that we never use */
12887 static void i915_disable_vga(struct drm_device
*dev
)
12889 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12891 u32 vga_reg
= i915_vgacntrl_reg(dev
);
12893 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12894 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
12895 outb(SR01
, VGA_SR_INDEX
);
12896 sr1
= inb(VGA_SR_DATA
);
12897 outb(sr1
| 1<<5, VGA_SR_DATA
);
12898 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
12902 * Fujitsu-Siemens Lifebook S6010 (830) has problems resuming
12903 * from S3 without preserving (some of?) the other bits.
12905 I915_WRITE(vga_reg
, dev_priv
->bios_vgacntr
| VGA_DISP_DISABLE
);
12906 POSTING_READ(vga_reg
);
12909 void intel_modeset_init_hw(struct drm_device
*dev
)
12911 intel_prepare_ddi(dev
);
12913 if (IS_VALLEYVIEW(dev
))
12914 vlv_update_cdclk(dev
);
12916 intel_init_clock_gating(dev
);
12918 intel_enable_gt_powersave(dev
);
12921 void intel_modeset_suspend_hw(struct drm_device
*dev
)
12923 intel_suspend_hw(dev
);
12926 void intel_modeset_init(struct drm_device
*dev
)
12928 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12931 struct intel_crtc
*crtc
;
12933 drm_mode_config_init(dev
);
12935 dev
->mode_config
.min_width
= 0;
12936 dev
->mode_config
.min_height
= 0;
12938 dev
->mode_config
.preferred_depth
= 24;
12939 dev
->mode_config
.prefer_shadow
= 1;
12941 dev
->mode_config
.funcs
= &intel_mode_funcs
;
12943 intel_init_quirks(dev
);
12945 intel_init_pm(dev
);
12947 if (INTEL_INFO(dev
)->num_pipes
== 0)
12950 intel_init_display(dev
);
12952 if (IS_GEN2(dev
)) {
12953 dev
->mode_config
.max_width
= 2048;
12954 dev
->mode_config
.max_height
= 2048;
12955 } else if (IS_GEN3(dev
)) {
12956 dev
->mode_config
.max_width
= 4096;
12957 dev
->mode_config
.max_height
= 4096;
12959 dev
->mode_config
.max_width
= 8192;
12960 dev
->mode_config
.max_height
= 8192;
12963 if (IS_845G(dev
) || IS_I865G(dev
)) {
12964 dev
->mode_config
.cursor_width
= IS_845G(dev
) ? 64 : 512;
12965 dev
->mode_config
.cursor_height
= 1023;
12966 } else if (IS_GEN2(dev
)) {
12967 dev
->mode_config
.cursor_width
= GEN2_CURSOR_WIDTH
;
12968 dev
->mode_config
.cursor_height
= GEN2_CURSOR_HEIGHT
;
12970 dev
->mode_config
.cursor_width
= MAX_CURSOR_WIDTH
;
12971 dev
->mode_config
.cursor_height
= MAX_CURSOR_HEIGHT
;
12974 dev
->mode_config
.fb_base
= dev_priv
->gtt
.mappable_base
;
12976 DRM_DEBUG_KMS("%d display pipe%s available.\n",
12977 INTEL_INFO(dev
)->num_pipes
,
12978 INTEL_INFO(dev
)->num_pipes
> 1 ? "s" : "");
12980 for_each_pipe(dev_priv
, pipe
) {
12981 intel_crtc_init(dev
, pipe
);
12982 for_each_sprite(pipe
, sprite
) {
12983 ret
= intel_plane_init(dev
, pipe
, sprite
);
12985 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
12986 pipe_name(pipe
), sprite_name(pipe
, sprite
), ret
);
12990 intel_init_dpio(dev
);
12992 intel_shared_dpll_init(dev
);
12994 /* save the BIOS value before clobbering it */
12995 dev_priv
->bios_vgacntr
= I915_READ(i915_vgacntrl_reg(dev
));
12996 /* Just disable it once at startup */
12997 i915_disable_vga(dev
);
12998 intel_setup_outputs(dev
);
13000 /* Just in case the BIOS is doing something questionable. */
13001 intel_disable_fbc(dev
);
13003 drm_modeset_lock_all(dev
);
13004 intel_modeset_setup_hw_state(dev
, false);
13005 drm_modeset_unlock_all(dev
);
13007 for_each_intel_crtc(dev
, crtc
) {
13012 * Note that reserving the BIOS fb up front prevents us
13013 * from stuffing other stolen allocations like the ring
13014 * on top. This prevents some ugliness at boot time, and
13015 * can even allow for smooth boot transitions if the BIOS
13016 * fb is large enough for the active pipe configuration.
13018 if (dev_priv
->display
.get_plane_config
) {
13019 dev_priv
->display
.get_plane_config(crtc
,
13020 &crtc
->plane_config
);
13022 * If the fb is shared between multiple heads, we'll
13023 * just get the first one.
13025 intel_find_plane_obj(crtc
, &crtc
->plane_config
);
13030 static void intel_enable_pipe_a(struct drm_device
*dev
)
13032 struct intel_connector
*connector
;
13033 struct drm_connector
*crt
= NULL
;
13034 struct intel_load_detect_pipe load_detect_temp
;
13035 struct drm_modeset_acquire_ctx
*ctx
= dev
->mode_config
.acquire_ctx
;
13037 /* We can't just switch on the pipe A, we need to set things up with a
13038 * proper mode and output configuration. As a gross hack, enable pipe A
13039 * by enabling the load detect pipe once. */
13040 list_for_each_entry(connector
,
13041 &dev
->mode_config
.connector_list
,
13043 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
13044 crt
= &connector
->base
;
13052 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
, ctx
))
13053 intel_release_load_detect_pipe(crt
, &load_detect_temp
);
13057 intel_check_plane_mapping(struct intel_crtc
*crtc
)
13059 struct drm_device
*dev
= crtc
->base
.dev
;
13060 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13063 if (INTEL_INFO(dev
)->num_pipes
== 1)
13066 reg
= DSPCNTR(!crtc
->plane
);
13067 val
= I915_READ(reg
);
13069 if ((val
& DISPLAY_PLANE_ENABLE
) &&
13070 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
13076 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
13078 struct drm_device
*dev
= crtc
->base
.dev
;
13079 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13082 /* Clear any frame start delays used for debugging left by the BIOS */
13083 reg
= PIPECONF(crtc
->config
.cpu_transcoder
);
13084 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
13086 /* restore vblank interrupts to correct state */
13087 if (crtc
->active
) {
13088 update_scanline_offset(crtc
);
13089 drm_vblank_on(dev
, crtc
->pipe
);
13091 drm_vblank_off(dev
, crtc
->pipe
);
13093 /* We need to sanitize the plane -> pipe mapping first because this will
13094 * disable the crtc (and hence change the state) if it is wrong. Note
13095 * that gen4+ has a fixed plane -> pipe mapping. */
13096 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
13097 struct intel_connector
*connector
;
13100 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13101 crtc
->base
.base
.id
);
13103 /* Pipe has the wrong plane attached and the plane is active.
13104 * Temporarily change the plane mapping and disable everything
13106 plane
= crtc
->plane
;
13107 crtc
->plane
= !plane
;
13108 crtc
->primary_enabled
= true;
13109 dev_priv
->display
.crtc_disable(&crtc
->base
);
13110 crtc
->plane
= plane
;
13112 /* ... and break all links. */
13113 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
13115 if (connector
->encoder
->base
.crtc
!= &crtc
->base
)
13118 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
13119 connector
->base
.encoder
= NULL
;
13121 /* multiple connectors may have the same encoder:
13122 * handle them and break crtc link separately */
13123 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
13125 if (connector
->encoder
->base
.crtc
== &crtc
->base
) {
13126 connector
->encoder
->base
.crtc
= NULL
;
13127 connector
->encoder
->connectors_active
= false;
13130 WARN_ON(crtc
->active
);
13131 crtc
->base
.enabled
= false;
13134 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
13135 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
13136 /* BIOS forgot to enable pipe A, this mostly happens after
13137 * resume. Force-enable the pipe to fix this, the update_dpms
13138 * call below we restore the pipe to the right state, but leave
13139 * the required bits on. */
13140 intel_enable_pipe_a(dev
);
13143 /* Adjust the state of the output pipe according to whether we
13144 * have active connectors/encoders. */
13145 intel_crtc_update_dpms(&crtc
->base
);
13147 if (crtc
->active
!= crtc
->base
.enabled
) {
13148 struct intel_encoder
*encoder
;
13150 /* This can happen either due to bugs in the get_hw_state
13151 * functions or because the pipe is force-enabled due to the
13153 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13154 crtc
->base
.base
.id
,
13155 crtc
->base
.enabled
? "enabled" : "disabled",
13156 crtc
->active
? "enabled" : "disabled");
13158 crtc
->base
.enabled
= crtc
->active
;
13160 /* Because we only establish the connector -> encoder ->
13161 * crtc links if something is active, this means the
13162 * crtc is now deactivated. Break the links. connector
13163 * -> encoder links are only establish when things are
13164 * actually up, hence no need to break them. */
13165 WARN_ON(crtc
->active
);
13167 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
13168 WARN_ON(encoder
->connectors_active
);
13169 encoder
->base
.crtc
= NULL
;
13173 if (crtc
->active
|| HAS_GMCH_DISPLAY(dev
)) {
13175 * We start out with underrun reporting disabled to avoid races.
13176 * For correct bookkeeping mark this on active crtcs.
13178 * Also on gmch platforms we dont have any hardware bits to
13179 * disable the underrun reporting. Which means we need to start
13180 * out with underrun reporting disabled also on inactive pipes,
13181 * since otherwise we'll complain about the garbage we read when
13182 * e.g. coming up after runtime pm.
13184 * No protection against concurrent access is required - at
13185 * worst a fifo underrun happens which also sets this to false.
13187 crtc
->cpu_fifo_underrun_disabled
= true;
13188 crtc
->pch_fifo_underrun_disabled
= true;
13192 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
13194 struct intel_connector
*connector
;
13195 struct drm_device
*dev
= encoder
->base
.dev
;
13197 /* We need to check both for a crtc link (meaning that the
13198 * encoder is active and trying to read from a pipe) and the
13199 * pipe itself being active. */
13200 bool has_active_crtc
= encoder
->base
.crtc
&&
13201 to_intel_crtc(encoder
->base
.crtc
)->active
;
13203 if (encoder
->connectors_active
&& !has_active_crtc
) {
13204 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13205 encoder
->base
.base
.id
,
13206 encoder
->base
.name
);
13208 /* Connector is active, but has no active pipe. This is
13209 * fallout from our resume register restoring. Disable
13210 * the encoder manually again. */
13211 if (encoder
->base
.crtc
) {
13212 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13213 encoder
->base
.base
.id
,
13214 encoder
->base
.name
);
13215 encoder
->disable(encoder
);
13216 if (encoder
->post_disable
)
13217 encoder
->post_disable(encoder
);
13219 encoder
->base
.crtc
= NULL
;
13220 encoder
->connectors_active
= false;
13222 /* Inconsistent output/port/pipe state happens presumably due to
13223 * a bug in one of the get_hw_state functions. Or someplace else
13224 * in our code, like the register restore mess on resume. Clamp
13225 * things to off as a safer default. */
13226 list_for_each_entry(connector
,
13227 &dev
->mode_config
.connector_list
,
13229 if (connector
->encoder
!= encoder
)
13231 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
13232 connector
->base
.encoder
= NULL
;
13235 /* Enabled encoders without active connectors will be fixed in
13236 * the crtc fixup. */
13239 void i915_redisable_vga_power_on(struct drm_device
*dev
)
13241 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13242 u32 vga_reg
= i915_vgacntrl_reg(dev
);
13244 if (!(I915_READ(vga_reg
) & VGA_DISP_DISABLE
)) {
13245 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13246 i915_disable_vga(dev
);
13250 void i915_redisable_vga(struct drm_device
*dev
)
13252 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13254 /* This function can be called both from intel_modeset_setup_hw_state or
13255 * at a very early point in our resume sequence, where the power well
13256 * structures are not yet restored. Since this function is at a very
13257 * paranoid "someone might have enabled VGA while we were not looking"
13258 * level, just check if the power well is enabled instead of trying to
13259 * follow the "don't touch the power well if we don't need it" policy
13260 * the rest of the driver uses. */
13261 if (!intel_display_power_enabled(dev_priv
, POWER_DOMAIN_VGA
))
13264 i915_redisable_vga_power_on(dev
);
13267 static bool primary_get_hw_state(struct intel_crtc
*crtc
)
13269 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
13274 return I915_READ(DSPCNTR(crtc
->plane
)) & DISPLAY_PLANE_ENABLE
;
13277 static void intel_modeset_readout_hw_state(struct drm_device
*dev
)
13279 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13281 struct intel_crtc
*crtc
;
13282 struct intel_encoder
*encoder
;
13283 struct intel_connector
*connector
;
13286 for_each_intel_crtc(dev
, crtc
) {
13287 memset(&crtc
->config
, 0, sizeof(crtc
->config
));
13289 crtc
->config
.quirks
|= PIPE_CONFIG_QUIRK_INHERITED_MODE
;
13291 crtc
->active
= dev_priv
->display
.get_pipe_config(crtc
,
13294 crtc
->base
.enabled
= crtc
->active
;
13295 crtc
->primary_enabled
= primary_get_hw_state(crtc
);
13297 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13298 crtc
->base
.base
.id
,
13299 crtc
->active
? "enabled" : "disabled");
13302 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
13303 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
13305 pll
->on
= pll
->get_hw_state(dev_priv
, pll
, &pll
->hw_state
);
13307 for_each_intel_crtc(dev
, crtc
) {
13308 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
13311 pll
->refcount
= pll
->active
;
13313 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
13314 pll
->name
, pll
->refcount
, pll
->on
);
13317 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
13320 for_each_intel_encoder(dev
, encoder
) {
13323 if (encoder
->get_hw_state(encoder
, &pipe
)) {
13324 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
13325 encoder
->base
.crtc
= &crtc
->base
;
13326 encoder
->get_config(encoder
, &crtc
->config
);
13328 encoder
->base
.crtc
= NULL
;
13331 encoder
->connectors_active
= false;
13332 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13333 encoder
->base
.base
.id
,
13334 encoder
->base
.name
,
13335 encoder
->base
.crtc
? "enabled" : "disabled",
13339 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
13341 if (connector
->get_hw_state(connector
)) {
13342 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
13343 connector
->encoder
->connectors_active
= true;
13344 connector
->base
.encoder
= &connector
->encoder
->base
;
13346 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
13347 connector
->base
.encoder
= NULL
;
13349 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13350 connector
->base
.base
.id
,
13351 connector
->base
.name
,
13352 connector
->base
.encoder
? "enabled" : "disabled");
13356 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13357 * and i915 state tracking structures. */
13358 void intel_modeset_setup_hw_state(struct drm_device
*dev
,
13359 bool force_restore
)
13361 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13363 struct intel_crtc
*crtc
;
13364 struct intel_encoder
*encoder
;
13367 intel_modeset_readout_hw_state(dev
);
13370 * Now that we have the config, copy it to each CRTC struct
13371 * Note that this could go away if we move to using crtc_config
13372 * checking everywhere.
13374 for_each_intel_crtc(dev
, crtc
) {
13375 if (crtc
->active
&& i915
.fastboot
) {
13376 intel_mode_from_pipe_config(&crtc
->base
.mode
, &crtc
->config
);
13377 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13378 crtc
->base
.base
.id
);
13379 drm_mode_debug_printmodeline(&crtc
->base
.mode
);
13383 /* HW state is read out, now we need to sanitize this mess. */
13384 for_each_intel_encoder(dev
, encoder
) {
13385 intel_sanitize_encoder(encoder
);
13388 for_each_pipe(dev_priv
, pipe
) {
13389 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
13390 intel_sanitize_crtc(crtc
);
13391 intel_dump_pipe_config(crtc
, &crtc
->config
, "[setup_hw_state]");
13394 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
13395 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
13397 if (!pll
->on
|| pll
->active
)
13400 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll
->name
);
13402 pll
->disable(dev_priv
, pll
);
13406 if (HAS_PCH_SPLIT(dev
))
13407 ilk_wm_get_hw_state(dev
);
13409 if (force_restore
) {
13410 i915_redisable_vga(dev
);
13413 * We need to use raw interfaces for restoring state to avoid
13414 * checking (bogus) intermediate states.
13416 for_each_pipe(dev_priv
, pipe
) {
13417 struct drm_crtc
*crtc
=
13418 dev_priv
->pipe_to_crtc_mapping
[pipe
];
13420 __intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
,
13421 crtc
->primary
->fb
);
13424 intel_modeset_update_staged_output_state(dev
);
13427 intel_modeset_check_state(dev
);
13430 void intel_modeset_gem_init(struct drm_device
*dev
)
13432 struct drm_crtc
*c
;
13433 struct drm_i915_gem_object
*obj
;
13435 mutex_lock(&dev
->struct_mutex
);
13436 intel_init_gt_powersave(dev
);
13437 mutex_unlock(&dev
->struct_mutex
);
13439 intel_modeset_init_hw(dev
);
13441 intel_setup_overlay(dev
);
13444 * Make sure any fbs we allocated at startup are properly
13445 * pinned & fenced. When we do the allocation it's too early
13448 mutex_lock(&dev
->struct_mutex
);
13449 for_each_crtc(dev
, c
) {
13450 obj
= intel_fb_obj(c
->primary
->fb
);
13454 if (intel_pin_and_fence_fb_obj(dev
, obj
, NULL
)) {
13455 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13456 to_intel_crtc(c
)->pipe
);
13457 drm_framebuffer_unreference(c
->primary
->fb
);
13458 c
->primary
->fb
= NULL
;
13461 mutex_unlock(&dev
->struct_mutex
);
13464 void intel_connector_unregister(struct intel_connector
*intel_connector
)
13466 struct drm_connector
*connector
= &intel_connector
->base
;
13468 intel_panel_destroy_backlight(connector
);
13469 drm_connector_unregister(connector
);
13472 void intel_modeset_cleanup(struct drm_device
*dev
)
13474 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13475 struct drm_connector
*connector
;
13478 * Interrupts and polling as the first thing to avoid creating havoc.
13479 * Too much stuff here (turning of rps, connectors, ...) would
13480 * experience fancy races otherwise.
13482 drm_irq_uninstall(dev
);
13483 intel_hpd_cancel_work(dev_priv
);
13484 dev_priv
->pm
._irqs_disabled
= true;
13487 * Due to the hpd irq storm handling the hotplug work can re-arm the
13488 * poll handlers. Hence disable polling after hpd handling is shut down.
13490 drm_kms_helper_poll_fini(dev
);
13492 mutex_lock(&dev
->struct_mutex
);
13494 intel_unregister_dsm_handler();
13496 intel_disable_fbc(dev
);
13498 intel_disable_gt_powersave(dev
);
13500 ironlake_teardown_rc6(dev
);
13502 mutex_unlock(&dev
->struct_mutex
);
13504 /* flush any delayed tasks or pending work */
13505 flush_scheduled_work();
13507 /* destroy the backlight and sysfs files before encoders/connectors */
13508 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
13509 struct intel_connector
*intel_connector
;
13511 intel_connector
= to_intel_connector(connector
);
13512 intel_connector
->unregister(intel_connector
);
13515 drm_mode_config_cleanup(dev
);
13517 intel_cleanup_overlay(dev
);
13519 mutex_lock(&dev
->struct_mutex
);
13520 intel_cleanup_gt_powersave(dev
);
13521 mutex_unlock(&dev
->struct_mutex
);
13525 * Return which encoder is currently attached for connector.
13527 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
13529 return &intel_attached_encoder(connector
)->base
;
13532 void intel_connector_attach_encoder(struct intel_connector
*connector
,
13533 struct intel_encoder
*encoder
)
13535 connector
->encoder
= encoder
;
13536 drm_mode_connector_attach_encoder(&connector
->base
,
13541 * set vga decode state - true == enable VGA decode
13543 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
13545 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13546 unsigned reg
= INTEL_INFO(dev
)->gen
>= 6 ? SNB_GMCH_CTRL
: INTEL_GMCH_CTRL
;
13549 if (pci_read_config_word(dev_priv
->bridge_dev
, reg
, &gmch_ctrl
)) {
13550 DRM_ERROR("failed to read control word\n");
13554 if (!!(gmch_ctrl
& INTEL_GMCH_VGA_DISABLE
) == !state
)
13558 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
13560 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
13562 if (pci_write_config_word(dev_priv
->bridge_dev
, reg
, gmch_ctrl
)) {
13563 DRM_ERROR("failed to write control word\n");
13570 struct intel_display_error_state
{
13572 u32 power_well_driver
;
13574 int num_transcoders
;
13576 struct intel_cursor_error_state
{
13581 } cursor
[I915_MAX_PIPES
];
13583 struct intel_pipe_error_state
{
13584 bool power_domain_on
;
13587 } pipe
[I915_MAX_PIPES
];
13589 struct intel_plane_error_state
{
13597 } plane
[I915_MAX_PIPES
];
13599 struct intel_transcoder_error_state
{
13600 bool power_domain_on
;
13601 enum transcoder cpu_transcoder
;
13614 struct intel_display_error_state
*
13615 intel_display_capture_error_state(struct drm_device
*dev
)
13617 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13618 struct intel_display_error_state
*error
;
13619 int transcoders
[] = {
13627 if (INTEL_INFO(dev
)->num_pipes
== 0)
13630 error
= kzalloc(sizeof(*error
), GFP_ATOMIC
);
13634 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
13635 error
->power_well_driver
= I915_READ(HSW_PWR_WELL_DRIVER
);
13637 for_each_pipe(dev_priv
, i
) {
13638 error
->pipe
[i
].power_domain_on
=
13639 intel_display_power_enabled_unlocked(dev_priv
,
13640 POWER_DOMAIN_PIPE(i
));
13641 if (!error
->pipe
[i
].power_domain_on
)
13644 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
13645 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
13646 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
13648 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
13649 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
13650 if (INTEL_INFO(dev
)->gen
<= 3) {
13651 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
13652 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
13654 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
13655 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
13656 if (INTEL_INFO(dev
)->gen
>= 4) {
13657 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
13658 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
13661 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
13663 if (HAS_GMCH_DISPLAY(dev
))
13664 error
->pipe
[i
].stat
= I915_READ(PIPESTAT(i
));
13667 error
->num_transcoders
= INTEL_INFO(dev
)->num_pipes
;
13668 if (HAS_DDI(dev_priv
->dev
))
13669 error
->num_transcoders
++; /* Account for eDP. */
13671 for (i
= 0; i
< error
->num_transcoders
; i
++) {
13672 enum transcoder cpu_transcoder
= transcoders
[i
];
13674 error
->transcoder
[i
].power_domain_on
=
13675 intel_display_power_enabled_unlocked(dev_priv
,
13676 POWER_DOMAIN_TRANSCODER(cpu_transcoder
));
13677 if (!error
->transcoder
[i
].power_domain_on
)
13680 error
->transcoder
[i
].cpu_transcoder
= cpu_transcoder
;
13682 error
->transcoder
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
13683 error
->transcoder
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
13684 error
->transcoder
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
13685 error
->transcoder
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
13686 error
->transcoder
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
13687 error
->transcoder
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
13688 error
->transcoder
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
13694 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13697 intel_display_print_error_state(struct drm_i915_error_state_buf
*m
,
13698 struct drm_device
*dev
,
13699 struct intel_display_error_state
*error
)
13701 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13707 err_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev
)->num_pipes
);
13708 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
13709 err_printf(m
, "PWR_WELL_CTL2: %08x\n",
13710 error
->power_well_driver
);
13711 for_each_pipe(dev_priv
, i
) {
13712 err_printf(m
, "Pipe [%d]:\n", i
);
13713 err_printf(m
, " Power: %s\n",
13714 error
->pipe
[i
].power_domain_on
? "on" : "off");
13715 err_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
13716 err_printf(m
, " STAT: %08x\n", error
->pipe
[i
].stat
);
13718 err_printf(m
, "Plane [%d]:\n", i
);
13719 err_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
13720 err_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
13721 if (INTEL_INFO(dev
)->gen
<= 3) {
13722 err_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
13723 err_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
13725 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
13726 err_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
13727 if (INTEL_INFO(dev
)->gen
>= 4) {
13728 err_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
13729 err_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
13732 err_printf(m
, "Cursor [%d]:\n", i
);
13733 err_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
13734 err_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
13735 err_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);
13738 for (i
= 0; i
< error
->num_transcoders
; i
++) {
13739 err_printf(m
, "CPU transcoder: %c\n",
13740 transcoder_name(error
->transcoder
[i
].cpu_transcoder
));
13741 err_printf(m
, " Power: %s\n",
13742 error
->transcoder
[i
].power_domain_on
? "on" : "off");
13743 err_printf(m
, " CONF: %08x\n", error
->transcoder
[i
].conf
);
13744 err_printf(m
, " HTOTAL: %08x\n", error
->transcoder
[i
].htotal
);
13745 err_printf(m
, " HBLANK: %08x\n", error
->transcoder
[i
].hblank
);
13746 err_printf(m
, " HSYNC: %08x\n", error
->transcoder
[i
].hsync
);
13747 err_printf(m
, " VTOTAL: %08x\n", error
->transcoder
[i
].vtotal
);
13748 err_printf(m
, " VBLANK: %08x\n", error
->transcoder
[i
].vblank
);
13749 err_printf(m
, " VSYNC: %08x\n", error
->transcoder
[i
].vsync
);
13753 void intel_modeset_preclose(struct drm_device
*dev
, struct drm_file
*file
)
13755 struct intel_crtc
*crtc
;
13757 for_each_intel_crtc(dev
, crtc
) {
13758 struct intel_unpin_work
*work
;
13759 unsigned long irqflags
;
13761 spin_lock_irqsave(&dev
->event_lock
, irqflags
);
13763 work
= crtc
->unpin_work
;
13765 if (work
&& work
->event
&&
13766 work
->event
->base
.file_priv
== file
) {
13767 kfree(work
->event
);
13768 work
->event
= NULL
;
13771 spin_unlock_irqrestore(&dev
->event_lock
, irqflags
);