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Merge tag 'drm-intel-fixes-2014-11-19' into drm-intel-next-queued
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_rect.h>
44 #include <linux/dma_remapping.h>
45
46 /* Primary plane formats supported by all gen */
47 #define COMMON_PRIMARY_FORMATS \
48 DRM_FORMAT_C8, \
49 DRM_FORMAT_RGB565, \
50 DRM_FORMAT_XRGB8888, \
51 DRM_FORMAT_ARGB8888
52
53 /* Primary plane formats for gen <= 3 */
54 static const uint32_t intel_primary_formats_gen2[] = {
55 COMMON_PRIMARY_FORMATS,
56 DRM_FORMAT_XRGB1555,
57 DRM_FORMAT_ARGB1555,
58 };
59
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t intel_primary_formats_gen4[] = {
62 COMMON_PRIMARY_FORMATS, \
63 DRM_FORMAT_XBGR8888,
64 DRM_FORMAT_ABGR8888,
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_ARGB2101010,
67 DRM_FORMAT_XBGR2101010,
68 DRM_FORMAT_ABGR2101010,
69 };
70
71 /* Cursor formats */
72 static const uint32_t intel_cursor_formats[] = {
73 DRM_FORMAT_ARGB8888,
74 };
75
76 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
77
78 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
79 struct intel_crtc_config *pipe_config);
80 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
81 struct intel_crtc_config *pipe_config);
82
83 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
84 int x, int y, struct drm_framebuffer *old_fb);
85 static int intel_framebuffer_init(struct drm_device *dev,
86 struct intel_framebuffer *ifb,
87 struct drm_mode_fb_cmd2 *mode_cmd,
88 struct drm_i915_gem_object *obj);
89 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
90 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
91 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
92 struct intel_link_m_n *m_n,
93 struct intel_link_m_n *m2_n2);
94 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
95 static void haswell_set_pipeconf(struct drm_crtc *crtc);
96 static void intel_set_pipe_csc(struct drm_crtc *crtc);
97 static void vlv_prepare_pll(struct intel_crtc *crtc,
98 const struct intel_crtc_config *pipe_config);
99 static void chv_prepare_pll(struct intel_crtc *crtc,
100 const struct intel_crtc_config *pipe_config);
101
102 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
103 {
104 if (!connector->mst_port)
105 return connector->encoder;
106 else
107 return &connector->mst_port->mst_encoders[pipe]->base;
108 }
109
110 typedef struct {
111 int min, max;
112 } intel_range_t;
113
114 typedef struct {
115 int dot_limit;
116 int p2_slow, p2_fast;
117 } intel_p2_t;
118
119 typedef struct intel_limit intel_limit_t;
120 struct intel_limit {
121 intel_range_t dot, vco, n, m, m1, m2, p, p1;
122 intel_p2_t p2;
123 };
124
125 int
126 intel_pch_rawclk(struct drm_device *dev)
127 {
128 struct drm_i915_private *dev_priv = dev->dev_private;
129
130 WARN_ON(!HAS_PCH_SPLIT(dev));
131
132 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
133 }
134
135 static inline u32 /* units of 100MHz */
136 intel_fdi_link_freq(struct drm_device *dev)
137 {
138 if (IS_GEN5(dev)) {
139 struct drm_i915_private *dev_priv = dev->dev_private;
140 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
141 } else
142 return 27;
143 }
144
145 static const intel_limit_t intel_limits_i8xx_dac = {
146 .dot = { .min = 25000, .max = 350000 },
147 .vco = { .min = 908000, .max = 1512000 },
148 .n = { .min = 2, .max = 16 },
149 .m = { .min = 96, .max = 140 },
150 .m1 = { .min = 18, .max = 26 },
151 .m2 = { .min = 6, .max = 16 },
152 .p = { .min = 4, .max = 128 },
153 .p1 = { .min = 2, .max = 33 },
154 .p2 = { .dot_limit = 165000,
155 .p2_slow = 4, .p2_fast = 2 },
156 };
157
158 static const intel_limit_t intel_limits_i8xx_dvo = {
159 .dot = { .min = 25000, .max = 350000 },
160 .vco = { .min = 908000, .max = 1512000 },
161 .n = { .min = 2, .max = 16 },
162 .m = { .min = 96, .max = 140 },
163 .m1 = { .min = 18, .max = 26 },
164 .m2 = { .min = 6, .max = 16 },
165 .p = { .min = 4, .max = 128 },
166 .p1 = { .min = 2, .max = 33 },
167 .p2 = { .dot_limit = 165000,
168 .p2_slow = 4, .p2_fast = 4 },
169 };
170
171 static const intel_limit_t intel_limits_i8xx_lvds = {
172 .dot = { .min = 25000, .max = 350000 },
173 .vco = { .min = 908000, .max = 1512000 },
174 .n = { .min = 2, .max = 16 },
175 .m = { .min = 96, .max = 140 },
176 .m1 = { .min = 18, .max = 26 },
177 .m2 = { .min = 6, .max = 16 },
178 .p = { .min = 4, .max = 128 },
179 .p1 = { .min = 1, .max = 6 },
180 .p2 = { .dot_limit = 165000,
181 .p2_slow = 14, .p2_fast = 7 },
182 };
183
184 static const intel_limit_t intel_limits_i9xx_sdvo = {
185 .dot = { .min = 20000, .max = 400000 },
186 .vco = { .min = 1400000, .max = 2800000 },
187 .n = { .min = 1, .max = 6 },
188 .m = { .min = 70, .max = 120 },
189 .m1 = { .min = 8, .max = 18 },
190 .m2 = { .min = 3, .max = 7 },
191 .p = { .min = 5, .max = 80 },
192 .p1 = { .min = 1, .max = 8 },
193 .p2 = { .dot_limit = 200000,
194 .p2_slow = 10, .p2_fast = 5 },
195 };
196
197 static const intel_limit_t intel_limits_i9xx_lvds = {
198 .dot = { .min = 20000, .max = 400000 },
199 .vco = { .min = 1400000, .max = 2800000 },
200 .n = { .min = 1, .max = 6 },
201 .m = { .min = 70, .max = 120 },
202 .m1 = { .min = 8, .max = 18 },
203 .m2 = { .min = 3, .max = 7 },
204 .p = { .min = 7, .max = 98 },
205 .p1 = { .min = 1, .max = 8 },
206 .p2 = { .dot_limit = 112000,
207 .p2_slow = 14, .p2_fast = 7 },
208 };
209
210
211 static const intel_limit_t intel_limits_g4x_sdvo = {
212 .dot = { .min = 25000, .max = 270000 },
213 .vco = { .min = 1750000, .max = 3500000},
214 .n = { .min = 1, .max = 4 },
215 .m = { .min = 104, .max = 138 },
216 .m1 = { .min = 17, .max = 23 },
217 .m2 = { .min = 5, .max = 11 },
218 .p = { .min = 10, .max = 30 },
219 .p1 = { .min = 1, .max = 3},
220 .p2 = { .dot_limit = 270000,
221 .p2_slow = 10,
222 .p2_fast = 10
223 },
224 };
225
226 static const intel_limit_t intel_limits_g4x_hdmi = {
227 .dot = { .min = 22000, .max = 400000 },
228 .vco = { .min = 1750000, .max = 3500000},
229 .n = { .min = 1, .max = 4 },
230 .m = { .min = 104, .max = 138 },
231 .m1 = { .min = 16, .max = 23 },
232 .m2 = { .min = 5, .max = 11 },
233 .p = { .min = 5, .max = 80 },
234 .p1 = { .min = 1, .max = 8},
235 .p2 = { .dot_limit = 165000,
236 .p2_slow = 10, .p2_fast = 5 },
237 };
238
239 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
240 .dot = { .min = 20000, .max = 115000 },
241 .vco = { .min = 1750000, .max = 3500000 },
242 .n = { .min = 1, .max = 3 },
243 .m = { .min = 104, .max = 138 },
244 .m1 = { .min = 17, .max = 23 },
245 .m2 = { .min = 5, .max = 11 },
246 .p = { .min = 28, .max = 112 },
247 .p1 = { .min = 2, .max = 8 },
248 .p2 = { .dot_limit = 0,
249 .p2_slow = 14, .p2_fast = 14
250 },
251 };
252
253 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
254 .dot = { .min = 80000, .max = 224000 },
255 .vco = { .min = 1750000, .max = 3500000 },
256 .n = { .min = 1, .max = 3 },
257 .m = { .min = 104, .max = 138 },
258 .m1 = { .min = 17, .max = 23 },
259 .m2 = { .min = 5, .max = 11 },
260 .p = { .min = 14, .max = 42 },
261 .p1 = { .min = 2, .max = 6 },
262 .p2 = { .dot_limit = 0,
263 .p2_slow = 7, .p2_fast = 7
264 },
265 };
266
267 static const intel_limit_t intel_limits_pineview_sdvo = {
268 .dot = { .min = 20000, .max = 400000},
269 .vco = { .min = 1700000, .max = 3500000 },
270 /* Pineview's Ncounter is a ring counter */
271 .n = { .min = 3, .max = 6 },
272 .m = { .min = 2, .max = 256 },
273 /* Pineview only has one combined m divider, which we treat as m2. */
274 .m1 = { .min = 0, .max = 0 },
275 .m2 = { .min = 0, .max = 254 },
276 .p = { .min = 5, .max = 80 },
277 .p1 = { .min = 1, .max = 8 },
278 .p2 = { .dot_limit = 200000,
279 .p2_slow = 10, .p2_fast = 5 },
280 };
281
282 static const intel_limit_t intel_limits_pineview_lvds = {
283 .dot = { .min = 20000, .max = 400000 },
284 .vco = { .min = 1700000, .max = 3500000 },
285 .n = { .min = 3, .max = 6 },
286 .m = { .min = 2, .max = 256 },
287 .m1 = { .min = 0, .max = 0 },
288 .m2 = { .min = 0, .max = 254 },
289 .p = { .min = 7, .max = 112 },
290 .p1 = { .min = 1, .max = 8 },
291 .p2 = { .dot_limit = 112000,
292 .p2_slow = 14, .p2_fast = 14 },
293 };
294
295 /* Ironlake / Sandybridge
296 *
297 * We calculate clock using (register_value + 2) for N/M1/M2, so here
298 * the range value for them is (actual_value - 2).
299 */
300 static const intel_limit_t intel_limits_ironlake_dac = {
301 .dot = { .min = 25000, .max = 350000 },
302 .vco = { .min = 1760000, .max = 3510000 },
303 .n = { .min = 1, .max = 5 },
304 .m = { .min = 79, .max = 127 },
305 .m1 = { .min = 12, .max = 22 },
306 .m2 = { .min = 5, .max = 9 },
307 .p = { .min = 5, .max = 80 },
308 .p1 = { .min = 1, .max = 8 },
309 .p2 = { .dot_limit = 225000,
310 .p2_slow = 10, .p2_fast = 5 },
311 };
312
313 static const intel_limit_t intel_limits_ironlake_single_lvds = {
314 .dot = { .min = 25000, .max = 350000 },
315 .vco = { .min = 1760000, .max = 3510000 },
316 .n = { .min = 1, .max = 3 },
317 .m = { .min = 79, .max = 118 },
318 .m1 = { .min = 12, .max = 22 },
319 .m2 = { .min = 5, .max = 9 },
320 .p = { .min = 28, .max = 112 },
321 .p1 = { .min = 2, .max = 8 },
322 .p2 = { .dot_limit = 225000,
323 .p2_slow = 14, .p2_fast = 14 },
324 };
325
326 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
327 .dot = { .min = 25000, .max = 350000 },
328 .vco = { .min = 1760000, .max = 3510000 },
329 .n = { .min = 1, .max = 3 },
330 .m = { .min = 79, .max = 127 },
331 .m1 = { .min = 12, .max = 22 },
332 .m2 = { .min = 5, .max = 9 },
333 .p = { .min = 14, .max = 56 },
334 .p1 = { .min = 2, .max = 8 },
335 .p2 = { .dot_limit = 225000,
336 .p2_slow = 7, .p2_fast = 7 },
337 };
338
339 /* LVDS 100mhz refclk limits. */
340 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
341 .dot = { .min = 25000, .max = 350000 },
342 .vco = { .min = 1760000, .max = 3510000 },
343 .n = { .min = 1, .max = 2 },
344 .m = { .min = 79, .max = 126 },
345 .m1 = { .min = 12, .max = 22 },
346 .m2 = { .min = 5, .max = 9 },
347 .p = { .min = 28, .max = 112 },
348 .p1 = { .min = 2, .max = 8 },
349 .p2 = { .dot_limit = 225000,
350 .p2_slow = 14, .p2_fast = 14 },
351 };
352
353 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
354 .dot = { .min = 25000, .max = 350000 },
355 .vco = { .min = 1760000, .max = 3510000 },
356 .n = { .min = 1, .max = 3 },
357 .m = { .min = 79, .max = 126 },
358 .m1 = { .min = 12, .max = 22 },
359 .m2 = { .min = 5, .max = 9 },
360 .p = { .min = 14, .max = 42 },
361 .p1 = { .min = 2, .max = 6 },
362 .p2 = { .dot_limit = 225000,
363 .p2_slow = 7, .p2_fast = 7 },
364 };
365
366 static const intel_limit_t intel_limits_vlv = {
367 /*
368 * These are the data rate limits (measured in fast clocks)
369 * since those are the strictest limits we have. The fast
370 * clock and actual rate limits are more relaxed, so checking
371 * them would make no difference.
372 */
373 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
374 .vco = { .min = 4000000, .max = 6000000 },
375 .n = { .min = 1, .max = 7 },
376 .m1 = { .min = 2, .max = 3 },
377 .m2 = { .min = 11, .max = 156 },
378 .p1 = { .min = 2, .max = 3 },
379 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
380 };
381
382 static const intel_limit_t intel_limits_chv = {
383 /*
384 * These are the data rate limits (measured in fast clocks)
385 * since those are the strictest limits we have. The fast
386 * clock and actual rate limits are more relaxed, so checking
387 * them would make no difference.
388 */
389 .dot = { .min = 25000 * 5, .max = 540000 * 5},
390 .vco = { .min = 4860000, .max = 6700000 },
391 .n = { .min = 1, .max = 1 },
392 .m1 = { .min = 2, .max = 2 },
393 .m2 = { .min = 24 << 22, .max = 175 << 22 },
394 .p1 = { .min = 2, .max = 4 },
395 .p2 = { .p2_slow = 1, .p2_fast = 14 },
396 };
397
398 static void vlv_clock(int refclk, intel_clock_t *clock)
399 {
400 clock->m = clock->m1 * clock->m2;
401 clock->p = clock->p1 * clock->p2;
402 if (WARN_ON(clock->n == 0 || clock->p == 0))
403 return;
404 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
405 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
406 }
407
408 /**
409 * Returns whether any output on the specified pipe is of the specified type
410 */
411 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
412 {
413 struct drm_device *dev = crtc->base.dev;
414 struct intel_encoder *encoder;
415
416 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
417 if (encoder->type == type)
418 return true;
419
420 return false;
421 }
422
423 /**
424 * Returns whether any output on the specified pipe will have the specified
425 * type after a staged modeset is complete, i.e., the same as
426 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
427 * encoder->crtc.
428 */
429 static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
430 {
431 struct drm_device *dev = crtc->base.dev;
432 struct intel_encoder *encoder;
433
434 for_each_intel_encoder(dev, encoder)
435 if (encoder->new_crtc == crtc && encoder->type == type)
436 return true;
437
438 return false;
439 }
440
441 static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
442 int refclk)
443 {
444 struct drm_device *dev = crtc->base.dev;
445 const intel_limit_t *limit;
446
447 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
448 if (intel_is_dual_link_lvds(dev)) {
449 if (refclk == 100000)
450 limit = &intel_limits_ironlake_dual_lvds_100m;
451 else
452 limit = &intel_limits_ironlake_dual_lvds;
453 } else {
454 if (refclk == 100000)
455 limit = &intel_limits_ironlake_single_lvds_100m;
456 else
457 limit = &intel_limits_ironlake_single_lvds;
458 }
459 } else
460 limit = &intel_limits_ironlake_dac;
461
462 return limit;
463 }
464
465 static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
466 {
467 struct drm_device *dev = crtc->base.dev;
468 const intel_limit_t *limit;
469
470 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
471 if (intel_is_dual_link_lvds(dev))
472 limit = &intel_limits_g4x_dual_channel_lvds;
473 else
474 limit = &intel_limits_g4x_single_channel_lvds;
475 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
476 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
477 limit = &intel_limits_g4x_hdmi;
478 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
479 limit = &intel_limits_g4x_sdvo;
480 } else /* The option is for other outputs */
481 limit = &intel_limits_i9xx_sdvo;
482
483 return limit;
484 }
485
486 static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
487 {
488 struct drm_device *dev = crtc->base.dev;
489 const intel_limit_t *limit;
490
491 if (HAS_PCH_SPLIT(dev))
492 limit = intel_ironlake_limit(crtc, refclk);
493 else if (IS_G4X(dev)) {
494 limit = intel_g4x_limit(crtc);
495 } else if (IS_PINEVIEW(dev)) {
496 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
497 limit = &intel_limits_pineview_lvds;
498 else
499 limit = &intel_limits_pineview_sdvo;
500 } else if (IS_CHERRYVIEW(dev)) {
501 limit = &intel_limits_chv;
502 } else if (IS_VALLEYVIEW(dev)) {
503 limit = &intel_limits_vlv;
504 } else if (!IS_GEN2(dev)) {
505 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
506 limit = &intel_limits_i9xx_lvds;
507 else
508 limit = &intel_limits_i9xx_sdvo;
509 } else {
510 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
511 limit = &intel_limits_i8xx_lvds;
512 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
513 limit = &intel_limits_i8xx_dvo;
514 else
515 limit = &intel_limits_i8xx_dac;
516 }
517 return limit;
518 }
519
520 /* m1 is reserved as 0 in Pineview, n is a ring counter */
521 static void pineview_clock(int refclk, intel_clock_t *clock)
522 {
523 clock->m = clock->m2 + 2;
524 clock->p = clock->p1 * clock->p2;
525 if (WARN_ON(clock->n == 0 || clock->p == 0))
526 return;
527 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
528 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
529 }
530
531 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
532 {
533 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
534 }
535
536 static void i9xx_clock(int refclk, intel_clock_t *clock)
537 {
538 clock->m = i9xx_dpll_compute_m(clock);
539 clock->p = clock->p1 * clock->p2;
540 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
541 return;
542 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
543 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
544 }
545
546 static void chv_clock(int refclk, intel_clock_t *clock)
547 {
548 clock->m = clock->m1 * clock->m2;
549 clock->p = clock->p1 * clock->p2;
550 if (WARN_ON(clock->n == 0 || clock->p == 0))
551 return;
552 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
553 clock->n << 22);
554 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
555 }
556
557 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
558 /**
559 * Returns whether the given set of divisors are valid for a given refclk with
560 * the given connectors.
561 */
562
563 static bool intel_PLL_is_valid(struct drm_device *dev,
564 const intel_limit_t *limit,
565 const intel_clock_t *clock)
566 {
567 if (clock->n < limit->n.min || limit->n.max < clock->n)
568 INTELPllInvalid("n out of range\n");
569 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
570 INTELPllInvalid("p1 out of range\n");
571 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
572 INTELPllInvalid("m2 out of range\n");
573 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
574 INTELPllInvalid("m1 out of range\n");
575
576 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
577 if (clock->m1 <= clock->m2)
578 INTELPllInvalid("m1 <= m2\n");
579
580 if (!IS_VALLEYVIEW(dev)) {
581 if (clock->p < limit->p.min || limit->p.max < clock->p)
582 INTELPllInvalid("p out of range\n");
583 if (clock->m < limit->m.min || limit->m.max < clock->m)
584 INTELPllInvalid("m out of range\n");
585 }
586
587 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
588 INTELPllInvalid("vco out of range\n");
589 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
590 * connector, etc., rather than just a single range.
591 */
592 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
593 INTELPllInvalid("dot out of range\n");
594
595 return true;
596 }
597
598 static bool
599 i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
600 int target, int refclk, intel_clock_t *match_clock,
601 intel_clock_t *best_clock)
602 {
603 struct drm_device *dev = crtc->base.dev;
604 intel_clock_t clock;
605 int err = target;
606
607 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
608 /*
609 * For LVDS just rely on its current settings for dual-channel.
610 * We haven't figured out how to reliably set up different
611 * single/dual channel state, if we even can.
612 */
613 if (intel_is_dual_link_lvds(dev))
614 clock.p2 = limit->p2.p2_fast;
615 else
616 clock.p2 = limit->p2.p2_slow;
617 } else {
618 if (target < limit->p2.dot_limit)
619 clock.p2 = limit->p2.p2_slow;
620 else
621 clock.p2 = limit->p2.p2_fast;
622 }
623
624 memset(best_clock, 0, sizeof(*best_clock));
625
626 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
627 clock.m1++) {
628 for (clock.m2 = limit->m2.min;
629 clock.m2 <= limit->m2.max; clock.m2++) {
630 if (clock.m2 >= clock.m1)
631 break;
632 for (clock.n = limit->n.min;
633 clock.n <= limit->n.max; clock.n++) {
634 for (clock.p1 = limit->p1.min;
635 clock.p1 <= limit->p1.max; clock.p1++) {
636 int this_err;
637
638 i9xx_clock(refclk, &clock);
639 if (!intel_PLL_is_valid(dev, limit,
640 &clock))
641 continue;
642 if (match_clock &&
643 clock.p != match_clock->p)
644 continue;
645
646 this_err = abs(clock.dot - target);
647 if (this_err < err) {
648 *best_clock = clock;
649 err = this_err;
650 }
651 }
652 }
653 }
654 }
655
656 return (err != target);
657 }
658
659 static bool
660 pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
661 int target, int refclk, intel_clock_t *match_clock,
662 intel_clock_t *best_clock)
663 {
664 struct drm_device *dev = crtc->base.dev;
665 intel_clock_t clock;
666 int err = target;
667
668 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
669 /*
670 * For LVDS just rely on its current settings for dual-channel.
671 * We haven't figured out how to reliably set up different
672 * single/dual channel state, if we even can.
673 */
674 if (intel_is_dual_link_lvds(dev))
675 clock.p2 = limit->p2.p2_fast;
676 else
677 clock.p2 = limit->p2.p2_slow;
678 } else {
679 if (target < limit->p2.dot_limit)
680 clock.p2 = limit->p2.p2_slow;
681 else
682 clock.p2 = limit->p2.p2_fast;
683 }
684
685 memset(best_clock, 0, sizeof(*best_clock));
686
687 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
688 clock.m1++) {
689 for (clock.m2 = limit->m2.min;
690 clock.m2 <= limit->m2.max; clock.m2++) {
691 for (clock.n = limit->n.min;
692 clock.n <= limit->n.max; clock.n++) {
693 for (clock.p1 = limit->p1.min;
694 clock.p1 <= limit->p1.max; clock.p1++) {
695 int this_err;
696
697 pineview_clock(refclk, &clock);
698 if (!intel_PLL_is_valid(dev, limit,
699 &clock))
700 continue;
701 if (match_clock &&
702 clock.p != match_clock->p)
703 continue;
704
705 this_err = abs(clock.dot - target);
706 if (this_err < err) {
707 *best_clock = clock;
708 err = this_err;
709 }
710 }
711 }
712 }
713 }
714
715 return (err != target);
716 }
717
718 static bool
719 g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
720 int target, int refclk, intel_clock_t *match_clock,
721 intel_clock_t *best_clock)
722 {
723 struct drm_device *dev = crtc->base.dev;
724 intel_clock_t clock;
725 int max_n;
726 bool found;
727 /* approximately equals target * 0.00585 */
728 int err_most = (target >> 8) + (target >> 9);
729 found = false;
730
731 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
732 if (intel_is_dual_link_lvds(dev))
733 clock.p2 = limit->p2.p2_fast;
734 else
735 clock.p2 = limit->p2.p2_slow;
736 } else {
737 if (target < limit->p2.dot_limit)
738 clock.p2 = limit->p2.p2_slow;
739 else
740 clock.p2 = limit->p2.p2_fast;
741 }
742
743 memset(best_clock, 0, sizeof(*best_clock));
744 max_n = limit->n.max;
745 /* based on hardware requirement, prefer smaller n to precision */
746 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
747 /* based on hardware requirement, prefere larger m1,m2 */
748 for (clock.m1 = limit->m1.max;
749 clock.m1 >= limit->m1.min; clock.m1--) {
750 for (clock.m2 = limit->m2.max;
751 clock.m2 >= limit->m2.min; clock.m2--) {
752 for (clock.p1 = limit->p1.max;
753 clock.p1 >= limit->p1.min; clock.p1--) {
754 int this_err;
755
756 i9xx_clock(refclk, &clock);
757 if (!intel_PLL_is_valid(dev, limit,
758 &clock))
759 continue;
760
761 this_err = abs(clock.dot - target);
762 if (this_err < err_most) {
763 *best_clock = clock;
764 err_most = this_err;
765 max_n = clock.n;
766 found = true;
767 }
768 }
769 }
770 }
771 }
772 return found;
773 }
774
775 static bool
776 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
777 int target, int refclk, intel_clock_t *match_clock,
778 intel_clock_t *best_clock)
779 {
780 struct drm_device *dev = crtc->base.dev;
781 intel_clock_t clock;
782 unsigned int bestppm = 1000000;
783 /* min update 19.2 MHz */
784 int max_n = min(limit->n.max, refclk / 19200);
785 bool found = false;
786
787 target *= 5; /* fast clock */
788
789 memset(best_clock, 0, sizeof(*best_clock));
790
791 /* based on hardware requirement, prefer smaller n to precision */
792 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
793 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
794 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
795 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
796 clock.p = clock.p1 * clock.p2;
797 /* based on hardware requirement, prefer bigger m1,m2 values */
798 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
799 unsigned int ppm, diff;
800
801 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
802 refclk * clock.m1);
803
804 vlv_clock(refclk, &clock);
805
806 if (!intel_PLL_is_valid(dev, limit,
807 &clock))
808 continue;
809
810 diff = abs(clock.dot - target);
811 ppm = div_u64(1000000ULL * diff, target);
812
813 if (ppm < 100 && clock.p > best_clock->p) {
814 bestppm = 0;
815 *best_clock = clock;
816 found = true;
817 }
818
819 if (bestppm >= 10 && ppm < bestppm - 10) {
820 bestppm = ppm;
821 *best_clock = clock;
822 found = true;
823 }
824 }
825 }
826 }
827 }
828
829 return found;
830 }
831
832 static bool
833 chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
834 int target, int refclk, intel_clock_t *match_clock,
835 intel_clock_t *best_clock)
836 {
837 struct drm_device *dev = crtc->base.dev;
838 intel_clock_t clock;
839 uint64_t m2;
840 int found = false;
841
842 memset(best_clock, 0, sizeof(*best_clock));
843
844 /*
845 * Based on hardware doc, the n always set to 1, and m1 always
846 * set to 2. If requires to support 200Mhz refclk, we need to
847 * revisit this because n may not 1 anymore.
848 */
849 clock.n = 1, clock.m1 = 2;
850 target *= 5; /* fast clock */
851
852 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
853 for (clock.p2 = limit->p2.p2_fast;
854 clock.p2 >= limit->p2.p2_slow;
855 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
856
857 clock.p = clock.p1 * clock.p2;
858
859 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
860 clock.n) << 22, refclk * clock.m1);
861
862 if (m2 > INT_MAX/clock.m1)
863 continue;
864
865 clock.m2 = m2;
866
867 chv_clock(refclk, &clock);
868
869 if (!intel_PLL_is_valid(dev, limit, &clock))
870 continue;
871
872 /* based on hardware requirement, prefer bigger p
873 */
874 if (clock.p > best_clock->p) {
875 *best_clock = clock;
876 found = true;
877 }
878 }
879 }
880
881 return found;
882 }
883
884 bool intel_crtc_active(struct drm_crtc *crtc)
885 {
886 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
887
888 /* Be paranoid as we can arrive here with only partial
889 * state retrieved from the hardware during setup.
890 *
891 * We can ditch the adjusted_mode.crtc_clock check as soon
892 * as Haswell has gained clock readout/fastboot support.
893 *
894 * We can ditch the crtc->primary->fb check as soon as we can
895 * properly reconstruct framebuffers.
896 */
897 return intel_crtc->active && crtc->primary->fb &&
898 intel_crtc->config.adjusted_mode.crtc_clock;
899 }
900
901 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
902 enum pipe pipe)
903 {
904 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
905 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
906
907 return intel_crtc->config.cpu_transcoder;
908 }
909
910 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
911 {
912 struct drm_i915_private *dev_priv = dev->dev_private;
913 u32 reg = PIPEDSL(pipe);
914 u32 line1, line2;
915 u32 line_mask;
916
917 if (IS_GEN2(dev))
918 line_mask = DSL_LINEMASK_GEN2;
919 else
920 line_mask = DSL_LINEMASK_GEN3;
921
922 line1 = I915_READ(reg) & line_mask;
923 mdelay(5);
924 line2 = I915_READ(reg) & line_mask;
925
926 return line1 == line2;
927 }
928
929 /*
930 * intel_wait_for_pipe_off - wait for pipe to turn off
931 * @crtc: crtc whose pipe to wait for
932 *
933 * After disabling a pipe, we can't wait for vblank in the usual way,
934 * spinning on the vblank interrupt status bit, since we won't actually
935 * see an interrupt when the pipe is disabled.
936 *
937 * On Gen4 and above:
938 * wait for the pipe register state bit to turn off
939 *
940 * Otherwise:
941 * wait for the display line value to settle (it usually
942 * ends up stopping at the start of the next frame).
943 *
944 */
945 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
946 {
947 struct drm_device *dev = crtc->base.dev;
948 struct drm_i915_private *dev_priv = dev->dev_private;
949 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
950 enum pipe pipe = crtc->pipe;
951
952 if (INTEL_INFO(dev)->gen >= 4) {
953 int reg = PIPECONF(cpu_transcoder);
954
955 /* Wait for the Pipe State to go off */
956 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
957 100))
958 WARN(1, "pipe_off wait timed out\n");
959 } else {
960 /* Wait for the display line to settle */
961 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
962 WARN(1, "pipe_off wait timed out\n");
963 }
964 }
965
966 /*
967 * ibx_digital_port_connected - is the specified port connected?
968 * @dev_priv: i915 private structure
969 * @port: the port to test
970 *
971 * Returns true if @port is connected, false otherwise.
972 */
973 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
974 struct intel_digital_port *port)
975 {
976 u32 bit;
977
978 if (HAS_PCH_IBX(dev_priv->dev)) {
979 switch (port->port) {
980 case PORT_B:
981 bit = SDE_PORTB_HOTPLUG;
982 break;
983 case PORT_C:
984 bit = SDE_PORTC_HOTPLUG;
985 break;
986 case PORT_D:
987 bit = SDE_PORTD_HOTPLUG;
988 break;
989 default:
990 return true;
991 }
992 } else {
993 switch (port->port) {
994 case PORT_B:
995 bit = SDE_PORTB_HOTPLUG_CPT;
996 break;
997 case PORT_C:
998 bit = SDE_PORTC_HOTPLUG_CPT;
999 break;
1000 case PORT_D:
1001 bit = SDE_PORTD_HOTPLUG_CPT;
1002 break;
1003 default:
1004 return true;
1005 }
1006 }
1007
1008 return I915_READ(SDEISR) & bit;
1009 }
1010
1011 static const char *state_string(bool enabled)
1012 {
1013 return enabled ? "on" : "off";
1014 }
1015
1016 /* Only for pre-ILK configs */
1017 void assert_pll(struct drm_i915_private *dev_priv,
1018 enum pipe pipe, bool state)
1019 {
1020 int reg;
1021 u32 val;
1022 bool cur_state;
1023
1024 reg = DPLL(pipe);
1025 val = I915_READ(reg);
1026 cur_state = !!(val & DPLL_VCO_ENABLE);
1027 WARN(cur_state != state,
1028 "PLL state assertion failure (expected %s, current %s)\n",
1029 state_string(state), state_string(cur_state));
1030 }
1031
1032 /* XXX: the dsi pll is shared between MIPI DSI ports */
1033 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1034 {
1035 u32 val;
1036 bool cur_state;
1037
1038 mutex_lock(&dev_priv->dpio_lock);
1039 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1040 mutex_unlock(&dev_priv->dpio_lock);
1041
1042 cur_state = val & DSI_PLL_VCO_EN;
1043 WARN(cur_state != state,
1044 "DSI PLL state assertion failure (expected %s, current %s)\n",
1045 state_string(state), state_string(cur_state));
1046 }
1047 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1048 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1049
1050 struct intel_shared_dpll *
1051 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1052 {
1053 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1054
1055 if (crtc->config.shared_dpll < 0)
1056 return NULL;
1057
1058 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1059 }
1060
1061 /* For ILK+ */
1062 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1063 struct intel_shared_dpll *pll,
1064 bool state)
1065 {
1066 bool cur_state;
1067 struct intel_dpll_hw_state hw_state;
1068
1069 if (WARN (!pll,
1070 "asserting DPLL %s with no DPLL\n", state_string(state)))
1071 return;
1072
1073 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1074 WARN(cur_state != state,
1075 "%s assertion failure (expected %s, current %s)\n",
1076 pll->name, state_string(state), state_string(cur_state));
1077 }
1078
1079 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1080 enum pipe pipe, bool state)
1081 {
1082 int reg;
1083 u32 val;
1084 bool cur_state;
1085 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1086 pipe);
1087
1088 if (HAS_DDI(dev_priv->dev)) {
1089 /* DDI does not have a specific FDI_TX register */
1090 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1091 val = I915_READ(reg);
1092 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1093 } else {
1094 reg = FDI_TX_CTL(pipe);
1095 val = I915_READ(reg);
1096 cur_state = !!(val & FDI_TX_ENABLE);
1097 }
1098 WARN(cur_state != state,
1099 "FDI TX state assertion failure (expected %s, current %s)\n",
1100 state_string(state), state_string(cur_state));
1101 }
1102 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1103 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1104
1105 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1106 enum pipe pipe, bool state)
1107 {
1108 int reg;
1109 u32 val;
1110 bool cur_state;
1111
1112 reg = FDI_RX_CTL(pipe);
1113 val = I915_READ(reg);
1114 cur_state = !!(val & FDI_RX_ENABLE);
1115 WARN(cur_state != state,
1116 "FDI RX state assertion failure (expected %s, current %s)\n",
1117 state_string(state), state_string(cur_state));
1118 }
1119 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1120 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1121
1122 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1123 enum pipe pipe)
1124 {
1125 int reg;
1126 u32 val;
1127
1128 /* ILK FDI PLL is always enabled */
1129 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1130 return;
1131
1132 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1133 if (HAS_DDI(dev_priv->dev))
1134 return;
1135
1136 reg = FDI_TX_CTL(pipe);
1137 val = I915_READ(reg);
1138 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1139 }
1140
1141 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1142 enum pipe pipe, bool state)
1143 {
1144 int reg;
1145 u32 val;
1146 bool cur_state;
1147
1148 reg = FDI_RX_CTL(pipe);
1149 val = I915_READ(reg);
1150 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1151 WARN(cur_state != state,
1152 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1153 state_string(state), state_string(cur_state));
1154 }
1155
1156 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1157 enum pipe pipe)
1158 {
1159 struct drm_device *dev = dev_priv->dev;
1160 int pp_reg;
1161 u32 val;
1162 enum pipe panel_pipe = PIPE_A;
1163 bool locked = true;
1164
1165 if (WARN_ON(HAS_DDI(dev)))
1166 return;
1167
1168 if (HAS_PCH_SPLIT(dev)) {
1169 u32 port_sel;
1170
1171 pp_reg = PCH_PP_CONTROL;
1172 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1173
1174 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1175 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1176 panel_pipe = PIPE_B;
1177 /* XXX: else fix for eDP */
1178 } else if (IS_VALLEYVIEW(dev)) {
1179 /* presumably write lock depends on pipe, not port select */
1180 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1181 panel_pipe = pipe;
1182 } else {
1183 pp_reg = PP_CONTROL;
1184 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1185 panel_pipe = PIPE_B;
1186 }
1187
1188 val = I915_READ(pp_reg);
1189 if (!(val & PANEL_POWER_ON) ||
1190 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1191 locked = false;
1192
1193 WARN(panel_pipe == pipe && locked,
1194 "panel assertion failure, pipe %c regs locked\n",
1195 pipe_name(pipe));
1196 }
1197
1198 static void assert_cursor(struct drm_i915_private *dev_priv,
1199 enum pipe pipe, bool state)
1200 {
1201 struct drm_device *dev = dev_priv->dev;
1202 bool cur_state;
1203
1204 if (IS_845G(dev) || IS_I865G(dev))
1205 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1206 else
1207 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1208
1209 WARN(cur_state != state,
1210 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1211 pipe_name(pipe), state_string(state), state_string(cur_state));
1212 }
1213 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1214 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1215
1216 void assert_pipe(struct drm_i915_private *dev_priv,
1217 enum pipe pipe, bool state)
1218 {
1219 int reg;
1220 u32 val;
1221 bool cur_state;
1222 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1223 pipe);
1224
1225 /* if we need the pipe quirk it must be always on */
1226 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1227 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1228 state = true;
1229
1230 if (!intel_display_power_is_enabled(dev_priv,
1231 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1232 cur_state = false;
1233 } else {
1234 reg = PIPECONF(cpu_transcoder);
1235 val = I915_READ(reg);
1236 cur_state = !!(val & PIPECONF_ENABLE);
1237 }
1238
1239 WARN(cur_state != state,
1240 "pipe %c assertion failure (expected %s, current %s)\n",
1241 pipe_name(pipe), state_string(state), state_string(cur_state));
1242 }
1243
1244 static void assert_plane(struct drm_i915_private *dev_priv,
1245 enum plane plane, bool state)
1246 {
1247 int reg;
1248 u32 val;
1249 bool cur_state;
1250
1251 reg = DSPCNTR(plane);
1252 val = I915_READ(reg);
1253 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1254 WARN(cur_state != state,
1255 "plane %c assertion failure (expected %s, current %s)\n",
1256 plane_name(plane), state_string(state), state_string(cur_state));
1257 }
1258
1259 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1260 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1261
1262 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1263 enum pipe pipe)
1264 {
1265 struct drm_device *dev = dev_priv->dev;
1266 int reg, i;
1267 u32 val;
1268 int cur_pipe;
1269
1270 /* Primary planes are fixed to pipes on gen4+ */
1271 if (INTEL_INFO(dev)->gen >= 4) {
1272 reg = DSPCNTR(pipe);
1273 val = I915_READ(reg);
1274 WARN(val & DISPLAY_PLANE_ENABLE,
1275 "plane %c assertion failure, should be disabled but not\n",
1276 plane_name(pipe));
1277 return;
1278 }
1279
1280 /* Need to check both planes against the pipe */
1281 for_each_pipe(dev_priv, i) {
1282 reg = DSPCNTR(i);
1283 val = I915_READ(reg);
1284 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1285 DISPPLANE_SEL_PIPE_SHIFT;
1286 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1287 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1288 plane_name(i), pipe_name(pipe));
1289 }
1290 }
1291
1292 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1293 enum pipe pipe)
1294 {
1295 struct drm_device *dev = dev_priv->dev;
1296 int reg, sprite;
1297 u32 val;
1298
1299 if (INTEL_INFO(dev)->gen >= 9) {
1300 for_each_sprite(pipe, sprite) {
1301 val = I915_READ(PLANE_CTL(pipe, sprite));
1302 WARN(val & PLANE_CTL_ENABLE,
1303 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1304 sprite, pipe_name(pipe));
1305 }
1306 } else if (IS_VALLEYVIEW(dev)) {
1307 for_each_sprite(pipe, sprite) {
1308 reg = SPCNTR(pipe, sprite);
1309 val = I915_READ(reg);
1310 WARN(val & SP_ENABLE,
1311 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1312 sprite_name(pipe, sprite), pipe_name(pipe));
1313 }
1314 } else if (INTEL_INFO(dev)->gen >= 7) {
1315 reg = SPRCTL(pipe);
1316 val = I915_READ(reg);
1317 WARN(val & SPRITE_ENABLE,
1318 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1319 plane_name(pipe), pipe_name(pipe));
1320 } else if (INTEL_INFO(dev)->gen >= 5) {
1321 reg = DVSCNTR(pipe);
1322 val = I915_READ(reg);
1323 WARN(val & DVS_ENABLE,
1324 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1325 plane_name(pipe), pipe_name(pipe));
1326 }
1327 }
1328
1329 static void assert_vblank_disabled(struct drm_crtc *crtc)
1330 {
1331 if (WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1332 drm_crtc_vblank_put(crtc);
1333 }
1334
1335 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1336 {
1337 u32 val;
1338 bool enabled;
1339
1340 WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1341
1342 val = I915_READ(PCH_DREF_CONTROL);
1343 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1344 DREF_SUPERSPREAD_SOURCE_MASK));
1345 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1346 }
1347
1348 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1349 enum pipe pipe)
1350 {
1351 int reg;
1352 u32 val;
1353 bool enabled;
1354
1355 reg = PCH_TRANSCONF(pipe);
1356 val = I915_READ(reg);
1357 enabled = !!(val & TRANS_ENABLE);
1358 WARN(enabled,
1359 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1360 pipe_name(pipe));
1361 }
1362
1363 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1364 enum pipe pipe, u32 port_sel, u32 val)
1365 {
1366 if ((val & DP_PORT_EN) == 0)
1367 return false;
1368
1369 if (HAS_PCH_CPT(dev_priv->dev)) {
1370 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1371 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1372 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1373 return false;
1374 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1375 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1376 return false;
1377 } else {
1378 if ((val & DP_PIPE_MASK) != (pipe << 30))
1379 return false;
1380 }
1381 return true;
1382 }
1383
1384 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1385 enum pipe pipe, u32 val)
1386 {
1387 if ((val & SDVO_ENABLE) == 0)
1388 return false;
1389
1390 if (HAS_PCH_CPT(dev_priv->dev)) {
1391 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1392 return false;
1393 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1394 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1395 return false;
1396 } else {
1397 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1398 return false;
1399 }
1400 return true;
1401 }
1402
1403 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1404 enum pipe pipe, u32 val)
1405 {
1406 if ((val & LVDS_PORT_EN) == 0)
1407 return false;
1408
1409 if (HAS_PCH_CPT(dev_priv->dev)) {
1410 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1411 return false;
1412 } else {
1413 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1414 return false;
1415 }
1416 return true;
1417 }
1418
1419 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1420 enum pipe pipe, u32 val)
1421 {
1422 if ((val & ADPA_DAC_ENABLE) == 0)
1423 return false;
1424 if (HAS_PCH_CPT(dev_priv->dev)) {
1425 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1426 return false;
1427 } else {
1428 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1429 return false;
1430 }
1431 return true;
1432 }
1433
1434 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1435 enum pipe pipe, int reg, u32 port_sel)
1436 {
1437 u32 val = I915_READ(reg);
1438 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1439 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1440 reg, pipe_name(pipe));
1441
1442 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1443 && (val & DP_PIPEB_SELECT),
1444 "IBX PCH dp port still using transcoder B\n");
1445 }
1446
1447 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1448 enum pipe pipe, int reg)
1449 {
1450 u32 val = I915_READ(reg);
1451 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1452 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1453 reg, pipe_name(pipe));
1454
1455 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1456 && (val & SDVO_PIPE_B_SELECT),
1457 "IBX PCH hdmi port still using transcoder B\n");
1458 }
1459
1460 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1461 enum pipe pipe)
1462 {
1463 int reg;
1464 u32 val;
1465
1466 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1467 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1468 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1469
1470 reg = PCH_ADPA;
1471 val = I915_READ(reg);
1472 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1473 "PCH VGA enabled on transcoder %c, should be disabled\n",
1474 pipe_name(pipe));
1475
1476 reg = PCH_LVDS;
1477 val = I915_READ(reg);
1478 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1479 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1480 pipe_name(pipe));
1481
1482 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1483 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1484 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1485 }
1486
1487 static void intel_init_dpio(struct drm_device *dev)
1488 {
1489 struct drm_i915_private *dev_priv = dev->dev_private;
1490
1491 if (!IS_VALLEYVIEW(dev))
1492 return;
1493
1494 /*
1495 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1496 * CHV x1 PHY (DP/HDMI D)
1497 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1498 */
1499 if (IS_CHERRYVIEW(dev)) {
1500 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1501 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1502 } else {
1503 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1504 }
1505 }
1506
1507 static void vlv_enable_pll(struct intel_crtc *crtc,
1508 const struct intel_crtc_config *pipe_config)
1509 {
1510 struct drm_device *dev = crtc->base.dev;
1511 struct drm_i915_private *dev_priv = dev->dev_private;
1512 int reg = DPLL(crtc->pipe);
1513 u32 dpll = pipe_config->dpll_hw_state.dpll;
1514
1515 assert_pipe_disabled(dev_priv, crtc->pipe);
1516
1517 /* No really, not for ILK+ */
1518 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1519
1520 /* PLL is protected by panel, make sure we can write it */
1521 if (IS_MOBILE(dev_priv->dev))
1522 assert_panel_unlocked(dev_priv, crtc->pipe);
1523
1524 I915_WRITE(reg, dpll);
1525 POSTING_READ(reg);
1526 udelay(150);
1527
1528 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1529 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1530
1531 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1532 POSTING_READ(DPLL_MD(crtc->pipe));
1533
1534 /* We do this three times for luck */
1535 I915_WRITE(reg, dpll);
1536 POSTING_READ(reg);
1537 udelay(150); /* wait for warmup */
1538 I915_WRITE(reg, dpll);
1539 POSTING_READ(reg);
1540 udelay(150); /* wait for warmup */
1541 I915_WRITE(reg, dpll);
1542 POSTING_READ(reg);
1543 udelay(150); /* wait for warmup */
1544 }
1545
1546 static void chv_enable_pll(struct intel_crtc *crtc,
1547 const struct intel_crtc_config *pipe_config)
1548 {
1549 struct drm_device *dev = crtc->base.dev;
1550 struct drm_i915_private *dev_priv = dev->dev_private;
1551 int pipe = crtc->pipe;
1552 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1553 u32 tmp;
1554
1555 assert_pipe_disabled(dev_priv, crtc->pipe);
1556
1557 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1558
1559 mutex_lock(&dev_priv->dpio_lock);
1560
1561 /* Enable back the 10bit clock to display controller */
1562 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1563 tmp |= DPIO_DCLKP_EN;
1564 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1565
1566 /*
1567 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1568 */
1569 udelay(1);
1570
1571 /* Enable PLL */
1572 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1573
1574 /* Check PLL is locked */
1575 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1576 DRM_ERROR("PLL %d failed to lock\n", pipe);
1577
1578 /* not sure when this should be written */
1579 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1580 POSTING_READ(DPLL_MD(pipe));
1581
1582 mutex_unlock(&dev_priv->dpio_lock);
1583 }
1584
1585 static int intel_num_dvo_pipes(struct drm_device *dev)
1586 {
1587 struct intel_crtc *crtc;
1588 int count = 0;
1589
1590 for_each_intel_crtc(dev, crtc)
1591 count += crtc->active &&
1592 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1593
1594 return count;
1595 }
1596
1597 static void i9xx_enable_pll(struct intel_crtc *crtc)
1598 {
1599 struct drm_device *dev = crtc->base.dev;
1600 struct drm_i915_private *dev_priv = dev->dev_private;
1601 int reg = DPLL(crtc->pipe);
1602 u32 dpll = crtc->config.dpll_hw_state.dpll;
1603
1604 assert_pipe_disabled(dev_priv, crtc->pipe);
1605
1606 /* No really, not for ILK+ */
1607 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1608
1609 /* PLL is protected by panel, make sure we can write it */
1610 if (IS_MOBILE(dev) && !IS_I830(dev))
1611 assert_panel_unlocked(dev_priv, crtc->pipe);
1612
1613 /* Enable DVO 2x clock on both PLLs if necessary */
1614 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1615 /*
1616 * It appears to be important that we don't enable this
1617 * for the current pipe before otherwise configuring the
1618 * PLL. No idea how this should be handled if multiple
1619 * DVO outputs are enabled simultaneosly.
1620 */
1621 dpll |= DPLL_DVO_2X_MODE;
1622 I915_WRITE(DPLL(!crtc->pipe),
1623 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1624 }
1625
1626 /* Wait for the clocks to stabilize. */
1627 POSTING_READ(reg);
1628 udelay(150);
1629
1630 if (INTEL_INFO(dev)->gen >= 4) {
1631 I915_WRITE(DPLL_MD(crtc->pipe),
1632 crtc->config.dpll_hw_state.dpll_md);
1633 } else {
1634 /* The pixel multiplier can only be updated once the
1635 * DPLL is enabled and the clocks are stable.
1636 *
1637 * So write it again.
1638 */
1639 I915_WRITE(reg, dpll);
1640 }
1641
1642 /* We do this three times for luck */
1643 I915_WRITE(reg, dpll);
1644 POSTING_READ(reg);
1645 udelay(150); /* wait for warmup */
1646 I915_WRITE(reg, dpll);
1647 POSTING_READ(reg);
1648 udelay(150); /* wait for warmup */
1649 I915_WRITE(reg, dpll);
1650 POSTING_READ(reg);
1651 udelay(150); /* wait for warmup */
1652 }
1653
1654 /**
1655 * i9xx_disable_pll - disable a PLL
1656 * @dev_priv: i915 private structure
1657 * @pipe: pipe PLL to disable
1658 *
1659 * Disable the PLL for @pipe, making sure the pipe is off first.
1660 *
1661 * Note! This is for pre-ILK only.
1662 */
1663 static void i9xx_disable_pll(struct intel_crtc *crtc)
1664 {
1665 struct drm_device *dev = crtc->base.dev;
1666 struct drm_i915_private *dev_priv = dev->dev_private;
1667 enum pipe pipe = crtc->pipe;
1668
1669 /* Disable DVO 2x clock on both PLLs if necessary */
1670 if (IS_I830(dev) &&
1671 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1672 intel_num_dvo_pipes(dev) == 1) {
1673 I915_WRITE(DPLL(PIPE_B),
1674 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1675 I915_WRITE(DPLL(PIPE_A),
1676 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1677 }
1678
1679 /* Don't disable pipe or pipe PLLs if needed */
1680 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1681 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1682 return;
1683
1684 /* Make sure the pipe isn't still relying on us */
1685 assert_pipe_disabled(dev_priv, pipe);
1686
1687 I915_WRITE(DPLL(pipe), 0);
1688 POSTING_READ(DPLL(pipe));
1689 }
1690
1691 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1692 {
1693 u32 val = 0;
1694
1695 /* Make sure the pipe isn't still relying on us */
1696 assert_pipe_disabled(dev_priv, pipe);
1697
1698 /*
1699 * Leave integrated clock source and reference clock enabled for pipe B.
1700 * The latter is needed for VGA hotplug / manual detection.
1701 */
1702 if (pipe == PIPE_B)
1703 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1704 I915_WRITE(DPLL(pipe), val);
1705 POSTING_READ(DPLL(pipe));
1706
1707 }
1708
1709 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1710 {
1711 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1712 u32 val;
1713
1714 /* Make sure the pipe isn't still relying on us */
1715 assert_pipe_disabled(dev_priv, pipe);
1716
1717 /* Set PLL en = 0 */
1718 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1719 if (pipe != PIPE_A)
1720 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1721 I915_WRITE(DPLL(pipe), val);
1722 POSTING_READ(DPLL(pipe));
1723
1724 mutex_lock(&dev_priv->dpio_lock);
1725
1726 /* Disable 10bit clock to display controller */
1727 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1728 val &= ~DPIO_DCLKP_EN;
1729 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1730
1731 /* disable left/right clock distribution */
1732 if (pipe != PIPE_B) {
1733 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1734 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1735 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1736 } else {
1737 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1738 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1739 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1740 }
1741
1742 mutex_unlock(&dev_priv->dpio_lock);
1743 }
1744
1745 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1746 struct intel_digital_port *dport)
1747 {
1748 u32 port_mask;
1749 int dpll_reg;
1750
1751 switch (dport->port) {
1752 case PORT_B:
1753 port_mask = DPLL_PORTB_READY_MASK;
1754 dpll_reg = DPLL(0);
1755 break;
1756 case PORT_C:
1757 port_mask = DPLL_PORTC_READY_MASK;
1758 dpll_reg = DPLL(0);
1759 break;
1760 case PORT_D:
1761 port_mask = DPLL_PORTD_READY_MASK;
1762 dpll_reg = DPIO_PHY_STATUS;
1763 break;
1764 default:
1765 BUG();
1766 }
1767
1768 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1769 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1770 port_name(dport->port), I915_READ(dpll_reg));
1771 }
1772
1773 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1774 {
1775 struct drm_device *dev = crtc->base.dev;
1776 struct drm_i915_private *dev_priv = dev->dev_private;
1777 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1778
1779 if (WARN_ON(pll == NULL))
1780 return;
1781
1782 WARN_ON(!pll->config.crtc_mask);
1783 if (pll->active == 0) {
1784 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1785 WARN_ON(pll->on);
1786 assert_shared_dpll_disabled(dev_priv, pll);
1787
1788 pll->mode_set(dev_priv, pll);
1789 }
1790 }
1791
1792 /**
1793 * intel_enable_shared_dpll - enable PCH PLL
1794 * @dev_priv: i915 private structure
1795 * @pipe: pipe PLL to enable
1796 *
1797 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1798 * drives the transcoder clock.
1799 */
1800 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1801 {
1802 struct drm_device *dev = crtc->base.dev;
1803 struct drm_i915_private *dev_priv = dev->dev_private;
1804 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1805
1806 if (WARN_ON(pll == NULL))
1807 return;
1808
1809 if (WARN_ON(pll->config.crtc_mask == 0))
1810 return;
1811
1812 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1813 pll->name, pll->active, pll->on,
1814 crtc->base.base.id);
1815
1816 if (pll->active++) {
1817 WARN_ON(!pll->on);
1818 assert_shared_dpll_enabled(dev_priv, pll);
1819 return;
1820 }
1821 WARN_ON(pll->on);
1822
1823 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1824
1825 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1826 pll->enable(dev_priv, pll);
1827 pll->on = true;
1828 }
1829
1830 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1831 {
1832 struct drm_device *dev = crtc->base.dev;
1833 struct drm_i915_private *dev_priv = dev->dev_private;
1834 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1835
1836 /* PCH only available on ILK+ */
1837 BUG_ON(INTEL_INFO(dev)->gen < 5);
1838 if (WARN_ON(pll == NULL))
1839 return;
1840
1841 if (WARN_ON(pll->config.crtc_mask == 0))
1842 return;
1843
1844 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1845 pll->name, pll->active, pll->on,
1846 crtc->base.base.id);
1847
1848 if (WARN_ON(pll->active == 0)) {
1849 assert_shared_dpll_disabled(dev_priv, pll);
1850 return;
1851 }
1852
1853 assert_shared_dpll_enabled(dev_priv, pll);
1854 WARN_ON(!pll->on);
1855 if (--pll->active)
1856 return;
1857
1858 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1859 pll->disable(dev_priv, pll);
1860 pll->on = false;
1861
1862 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1863 }
1864
1865 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1866 enum pipe pipe)
1867 {
1868 struct drm_device *dev = dev_priv->dev;
1869 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1870 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1871 uint32_t reg, val, pipeconf_val;
1872
1873 /* PCH only available on ILK+ */
1874 BUG_ON(!HAS_PCH_SPLIT(dev));
1875
1876 /* Make sure PCH DPLL is enabled */
1877 assert_shared_dpll_enabled(dev_priv,
1878 intel_crtc_to_shared_dpll(intel_crtc));
1879
1880 /* FDI must be feeding us bits for PCH ports */
1881 assert_fdi_tx_enabled(dev_priv, pipe);
1882 assert_fdi_rx_enabled(dev_priv, pipe);
1883
1884 if (HAS_PCH_CPT(dev)) {
1885 /* Workaround: Set the timing override bit before enabling the
1886 * pch transcoder. */
1887 reg = TRANS_CHICKEN2(pipe);
1888 val = I915_READ(reg);
1889 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1890 I915_WRITE(reg, val);
1891 }
1892
1893 reg = PCH_TRANSCONF(pipe);
1894 val = I915_READ(reg);
1895 pipeconf_val = I915_READ(PIPECONF(pipe));
1896
1897 if (HAS_PCH_IBX(dev_priv->dev)) {
1898 /*
1899 * make the BPC in transcoder be consistent with
1900 * that in pipeconf reg.
1901 */
1902 val &= ~PIPECONF_BPC_MASK;
1903 val |= pipeconf_val & PIPECONF_BPC_MASK;
1904 }
1905
1906 val &= ~TRANS_INTERLACE_MASK;
1907 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1908 if (HAS_PCH_IBX(dev_priv->dev) &&
1909 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1910 val |= TRANS_LEGACY_INTERLACED_ILK;
1911 else
1912 val |= TRANS_INTERLACED;
1913 else
1914 val |= TRANS_PROGRESSIVE;
1915
1916 I915_WRITE(reg, val | TRANS_ENABLE);
1917 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1918 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1919 }
1920
1921 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1922 enum transcoder cpu_transcoder)
1923 {
1924 u32 val, pipeconf_val;
1925
1926 /* PCH only available on ILK+ */
1927 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1928
1929 /* FDI must be feeding us bits for PCH ports */
1930 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1931 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1932
1933 /* Workaround: set timing override bit. */
1934 val = I915_READ(_TRANSA_CHICKEN2);
1935 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1936 I915_WRITE(_TRANSA_CHICKEN2, val);
1937
1938 val = TRANS_ENABLE;
1939 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1940
1941 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1942 PIPECONF_INTERLACED_ILK)
1943 val |= TRANS_INTERLACED;
1944 else
1945 val |= TRANS_PROGRESSIVE;
1946
1947 I915_WRITE(LPT_TRANSCONF, val);
1948 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1949 DRM_ERROR("Failed to enable PCH transcoder\n");
1950 }
1951
1952 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1953 enum pipe pipe)
1954 {
1955 struct drm_device *dev = dev_priv->dev;
1956 uint32_t reg, val;
1957
1958 /* FDI relies on the transcoder */
1959 assert_fdi_tx_disabled(dev_priv, pipe);
1960 assert_fdi_rx_disabled(dev_priv, pipe);
1961
1962 /* Ports must be off as well */
1963 assert_pch_ports_disabled(dev_priv, pipe);
1964
1965 reg = PCH_TRANSCONF(pipe);
1966 val = I915_READ(reg);
1967 val &= ~TRANS_ENABLE;
1968 I915_WRITE(reg, val);
1969 /* wait for PCH transcoder off, transcoder state */
1970 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1971 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1972
1973 if (!HAS_PCH_IBX(dev)) {
1974 /* Workaround: Clear the timing override chicken bit again. */
1975 reg = TRANS_CHICKEN2(pipe);
1976 val = I915_READ(reg);
1977 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1978 I915_WRITE(reg, val);
1979 }
1980 }
1981
1982 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1983 {
1984 u32 val;
1985
1986 val = I915_READ(LPT_TRANSCONF);
1987 val &= ~TRANS_ENABLE;
1988 I915_WRITE(LPT_TRANSCONF, val);
1989 /* wait for PCH transcoder off, transcoder state */
1990 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1991 DRM_ERROR("Failed to disable PCH transcoder\n");
1992
1993 /* Workaround: clear timing override bit. */
1994 val = I915_READ(_TRANSA_CHICKEN2);
1995 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1996 I915_WRITE(_TRANSA_CHICKEN2, val);
1997 }
1998
1999 /**
2000 * intel_enable_pipe - enable a pipe, asserting requirements
2001 * @crtc: crtc responsible for the pipe
2002 *
2003 * Enable @crtc's pipe, making sure that various hardware specific requirements
2004 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2005 */
2006 static void intel_enable_pipe(struct intel_crtc *crtc)
2007 {
2008 struct drm_device *dev = crtc->base.dev;
2009 struct drm_i915_private *dev_priv = dev->dev_private;
2010 enum pipe pipe = crtc->pipe;
2011 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2012 pipe);
2013 enum pipe pch_transcoder;
2014 int reg;
2015 u32 val;
2016
2017 assert_planes_disabled(dev_priv, pipe);
2018 assert_cursor_disabled(dev_priv, pipe);
2019 assert_sprites_disabled(dev_priv, pipe);
2020
2021 if (HAS_PCH_LPT(dev_priv->dev))
2022 pch_transcoder = TRANSCODER_A;
2023 else
2024 pch_transcoder = pipe;
2025
2026 /*
2027 * A pipe without a PLL won't actually be able to drive bits from
2028 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2029 * need the check.
2030 */
2031 if (!HAS_PCH_SPLIT(dev_priv->dev))
2032 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2033 assert_dsi_pll_enabled(dev_priv);
2034 else
2035 assert_pll_enabled(dev_priv, pipe);
2036 else {
2037 if (crtc->config.has_pch_encoder) {
2038 /* if driving the PCH, we need FDI enabled */
2039 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2040 assert_fdi_tx_pll_enabled(dev_priv,
2041 (enum pipe) cpu_transcoder);
2042 }
2043 /* FIXME: assert CPU port conditions for SNB+ */
2044 }
2045
2046 reg = PIPECONF(cpu_transcoder);
2047 val = I915_READ(reg);
2048 if (val & PIPECONF_ENABLE) {
2049 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2050 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2051 return;
2052 }
2053
2054 I915_WRITE(reg, val | PIPECONF_ENABLE);
2055 POSTING_READ(reg);
2056 }
2057
2058 /**
2059 * intel_disable_pipe - disable a pipe, asserting requirements
2060 * @crtc: crtc whose pipes is to be disabled
2061 *
2062 * Disable the pipe of @crtc, making sure that various hardware
2063 * specific requirements are met, if applicable, e.g. plane
2064 * disabled, panel fitter off, etc.
2065 *
2066 * Will wait until the pipe has shut down before returning.
2067 */
2068 static void intel_disable_pipe(struct intel_crtc *crtc)
2069 {
2070 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2071 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2072 enum pipe pipe = crtc->pipe;
2073 int reg;
2074 u32 val;
2075
2076 /*
2077 * Make sure planes won't keep trying to pump pixels to us,
2078 * or we might hang the display.
2079 */
2080 assert_planes_disabled(dev_priv, pipe);
2081 assert_cursor_disabled(dev_priv, pipe);
2082 assert_sprites_disabled(dev_priv, pipe);
2083
2084 reg = PIPECONF(cpu_transcoder);
2085 val = I915_READ(reg);
2086 if ((val & PIPECONF_ENABLE) == 0)
2087 return;
2088
2089 /*
2090 * Double wide has implications for planes
2091 * so best keep it disabled when not needed.
2092 */
2093 if (crtc->config.double_wide)
2094 val &= ~PIPECONF_DOUBLE_WIDE;
2095
2096 /* Don't disable pipe or pipe PLLs if needed */
2097 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2098 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2099 val &= ~PIPECONF_ENABLE;
2100
2101 I915_WRITE(reg, val);
2102 if ((val & PIPECONF_ENABLE) == 0)
2103 intel_wait_for_pipe_off(crtc);
2104 }
2105
2106 /*
2107 * Plane regs are double buffered, going from enabled->disabled needs a
2108 * trigger in order to latch. The display address reg provides this.
2109 */
2110 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2111 enum plane plane)
2112 {
2113 struct drm_device *dev = dev_priv->dev;
2114 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2115
2116 I915_WRITE(reg, I915_READ(reg));
2117 POSTING_READ(reg);
2118 }
2119
2120 /**
2121 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2122 * @plane: plane to be enabled
2123 * @crtc: crtc for the plane
2124 *
2125 * Enable @plane on @crtc, making sure that the pipe is running first.
2126 */
2127 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2128 struct drm_crtc *crtc)
2129 {
2130 struct drm_device *dev = plane->dev;
2131 struct drm_i915_private *dev_priv = dev->dev_private;
2132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2133
2134 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2135 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2136
2137 if (intel_crtc->primary_enabled)
2138 return;
2139
2140 intel_crtc->primary_enabled = true;
2141
2142 dev_priv->display.update_primary_plane(crtc, plane->fb,
2143 crtc->x, crtc->y);
2144
2145 /*
2146 * BDW signals flip done immediately if the plane
2147 * is disabled, even if the plane enable is already
2148 * armed to occur at the next vblank :(
2149 */
2150 if (IS_BROADWELL(dev))
2151 intel_wait_for_vblank(dev, intel_crtc->pipe);
2152 }
2153
2154 /**
2155 * intel_disable_primary_hw_plane - disable the primary hardware plane
2156 * @plane: plane to be disabled
2157 * @crtc: crtc for the plane
2158 *
2159 * Disable @plane on @crtc, making sure that the pipe is running first.
2160 */
2161 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2162 struct drm_crtc *crtc)
2163 {
2164 struct drm_device *dev = plane->dev;
2165 struct drm_i915_private *dev_priv = dev->dev_private;
2166 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2167
2168 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2169
2170 if (!intel_crtc->primary_enabled)
2171 return;
2172
2173 intel_crtc->primary_enabled = false;
2174
2175 dev_priv->display.update_primary_plane(crtc, plane->fb,
2176 crtc->x, crtc->y);
2177 }
2178
2179 static bool need_vtd_wa(struct drm_device *dev)
2180 {
2181 #ifdef CONFIG_INTEL_IOMMU
2182 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2183 return true;
2184 #endif
2185 return false;
2186 }
2187
2188 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2189 {
2190 int tile_height;
2191
2192 tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2193 return ALIGN(height, tile_height);
2194 }
2195
2196 int
2197 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2198 struct drm_framebuffer *fb,
2199 struct intel_engine_cs *pipelined)
2200 {
2201 struct drm_device *dev = fb->dev;
2202 struct drm_i915_private *dev_priv = dev->dev_private;
2203 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2204 u32 alignment;
2205 int ret;
2206
2207 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2208
2209 switch (obj->tiling_mode) {
2210 case I915_TILING_NONE:
2211 if (INTEL_INFO(dev)->gen >= 9)
2212 alignment = 256 * 1024;
2213 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2214 alignment = 128 * 1024;
2215 else if (INTEL_INFO(dev)->gen >= 4)
2216 alignment = 4 * 1024;
2217 else
2218 alignment = 64 * 1024;
2219 break;
2220 case I915_TILING_X:
2221 if (INTEL_INFO(dev)->gen >= 9)
2222 alignment = 256 * 1024;
2223 else {
2224 /* pin() will align the object as required by fence */
2225 alignment = 0;
2226 }
2227 break;
2228 case I915_TILING_Y:
2229 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2230 return -EINVAL;
2231 default:
2232 BUG();
2233 }
2234
2235 /* Note that the w/a also requires 64 PTE of padding following the
2236 * bo. We currently fill all unused PTE with the shadow page and so
2237 * we should always have valid PTE following the scanout preventing
2238 * the VT-d warning.
2239 */
2240 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2241 alignment = 256 * 1024;
2242
2243 /*
2244 * Global gtt pte registers are special registers which actually forward
2245 * writes to a chunk of system memory. Which means that there is no risk
2246 * that the register values disappear as soon as we call
2247 * intel_runtime_pm_put(), so it is correct to wrap only the
2248 * pin/unpin/fence and not more.
2249 */
2250 intel_runtime_pm_get(dev_priv);
2251
2252 dev_priv->mm.interruptible = false;
2253 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2254 if (ret)
2255 goto err_interruptible;
2256
2257 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2258 * fence, whereas 965+ only requires a fence if using
2259 * framebuffer compression. For simplicity, we always install
2260 * a fence as the cost is not that onerous.
2261 */
2262 ret = i915_gem_object_get_fence(obj);
2263 if (ret)
2264 goto err_unpin;
2265
2266 i915_gem_object_pin_fence(obj);
2267
2268 dev_priv->mm.interruptible = true;
2269 intel_runtime_pm_put(dev_priv);
2270 return 0;
2271
2272 err_unpin:
2273 i915_gem_object_unpin_from_display_plane(obj);
2274 err_interruptible:
2275 dev_priv->mm.interruptible = true;
2276 intel_runtime_pm_put(dev_priv);
2277 return ret;
2278 }
2279
2280 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2281 {
2282 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2283
2284 i915_gem_object_unpin_fence(obj);
2285 i915_gem_object_unpin_from_display_plane(obj);
2286 }
2287
2288 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2289 * is assumed to be a power-of-two. */
2290 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2291 unsigned int tiling_mode,
2292 unsigned int cpp,
2293 unsigned int pitch)
2294 {
2295 if (tiling_mode != I915_TILING_NONE) {
2296 unsigned int tile_rows, tiles;
2297
2298 tile_rows = *y / 8;
2299 *y %= 8;
2300
2301 tiles = *x / (512/cpp);
2302 *x %= 512/cpp;
2303
2304 return tile_rows * pitch * 8 + tiles * 4096;
2305 } else {
2306 unsigned int offset;
2307
2308 offset = *y * pitch + *x * cpp;
2309 *y = 0;
2310 *x = (offset & 4095) / cpp;
2311 return offset & -4096;
2312 }
2313 }
2314
2315 int intel_format_to_fourcc(int format)
2316 {
2317 switch (format) {
2318 case DISPPLANE_8BPP:
2319 return DRM_FORMAT_C8;
2320 case DISPPLANE_BGRX555:
2321 return DRM_FORMAT_XRGB1555;
2322 case DISPPLANE_BGRX565:
2323 return DRM_FORMAT_RGB565;
2324 default:
2325 case DISPPLANE_BGRX888:
2326 return DRM_FORMAT_XRGB8888;
2327 case DISPPLANE_RGBX888:
2328 return DRM_FORMAT_XBGR8888;
2329 case DISPPLANE_BGRX101010:
2330 return DRM_FORMAT_XRGB2101010;
2331 case DISPPLANE_RGBX101010:
2332 return DRM_FORMAT_XBGR2101010;
2333 }
2334 }
2335
2336 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2337 struct intel_plane_config *plane_config)
2338 {
2339 struct drm_device *dev = crtc->base.dev;
2340 struct drm_i915_gem_object *obj = NULL;
2341 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2342 u32 base = plane_config->base;
2343
2344 if (plane_config->size == 0)
2345 return false;
2346
2347 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2348 plane_config->size);
2349 if (!obj)
2350 return false;
2351
2352 if (plane_config->tiled) {
2353 obj->tiling_mode = I915_TILING_X;
2354 obj->stride = crtc->base.primary->fb->pitches[0];
2355 }
2356
2357 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2358 mode_cmd.width = crtc->base.primary->fb->width;
2359 mode_cmd.height = crtc->base.primary->fb->height;
2360 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2361
2362 mutex_lock(&dev->struct_mutex);
2363
2364 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2365 &mode_cmd, obj)) {
2366 DRM_DEBUG_KMS("intel fb init failed\n");
2367 goto out_unref_obj;
2368 }
2369
2370 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2371 mutex_unlock(&dev->struct_mutex);
2372
2373 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2374 return true;
2375
2376 out_unref_obj:
2377 drm_gem_object_unreference(&obj->base);
2378 mutex_unlock(&dev->struct_mutex);
2379 return false;
2380 }
2381
2382 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2383 struct intel_plane_config *plane_config)
2384 {
2385 struct drm_device *dev = intel_crtc->base.dev;
2386 struct drm_i915_private *dev_priv = dev->dev_private;
2387 struct drm_crtc *c;
2388 struct intel_crtc *i;
2389 struct drm_i915_gem_object *obj;
2390
2391 if (!intel_crtc->base.primary->fb)
2392 return;
2393
2394 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2395 return;
2396
2397 kfree(intel_crtc->base.primary->fb);
2398 intel_crtc->base.primary->fb = NULL;
2399
2400 /*
2401 * Failed to alloc the obj, check to see if we should share
2402 * an fb with another CRTC instead
2403 */
2404 for_each_crtc(dev, c) {
2405 i = to_intel_crtc(c);
2406
2407 if (c == &intel_crtc->base)
2408 continue;
2409
2410 if (!i->active)
2411 continue;
2412
2413 obj = intel_fb_obj(c->primary->fb);
2414 if (obj == NULL)
2415 continue;
2416
2417 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2418 if (obj->tiling_mode != I915_TILING_NONE)
2419 dev_priv->preserve_bios_swizzle = true;
2420
2421 drm_framebuffer_reference(c->primary->fb);
2422 intel_crtc->base.primary->fb = c->primary->fb;
2423 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2424 break;
2425 }
2426 }
2427 }
2428
2429 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2430 struct drm_framebuffer *fb,
2431 int x, int y)
2432 {
2433 struct drm_device *dev = crtc->dev;
2434 struct drm_i915_private *dev_priv = dev->dev_private;
2435 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2436 struct drm_i915_gem_object *obj;
2437 int plane = intel_crtc->plane;
2438 unsigned long linear_offset;
2439 u32 dspcntr;
2440 u32 reg = DSPCNTR(plane);
2441 int pixel_size;
2442
2443 if (!intel_crtc->primary_enabled) {
2444 I915_WRITE(reg, 0);
2445 if (INTEL_INFO(dev)->gen >= 4)
2446 I915_WRITE(DSPSURF(plane), 0);
2447 else
2448 I915_WRITE(DSPADDR(plane), 0);
2449 POSTING_READ(reg);
2450 return;
2451 }
2452
2453 obj = intel_fb_obj(fb);
2454 if (WARN_ON(obj == NULL))
2455 return;
2456
2457 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2458
2459 dspcntr = DISPPLANE_GAMMA_ENABLE;
2460
2461 dspcntr |= DISPLAY_PLANE_ENABLE;
2462
2463 if (INTEL_INFO(dev)->gen < 4) {
2464 if (intel_crtc->pipe == PIPE_B)
2465 dspcntr |= DISPPLANE_SEL_PIPE_B;
2466
2467 /* pipesrc and dspsize control the size that is scaled from,
2468 * which should always be the user's requested size.
2469 */
2470 I915_WRITE(DSPSIZE(plane),
2471 ((intel_crtc->config.pipe_src_h - 1) << 16) |
2472 (intel_crtc->config.pipe_src_w - 1));
2473 I915_WRITE(DSPPOS(plane), 0);
2474 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2475 I915_WRITE(PRIMSIZE(plane),
2476 ((intel_crtc->config.pipe_src_h - 1) << 16) |
2477 (intel_crtc->config.pipe_src_w - 1));
2478 I915_WRITE(PRIMPOS(plane), 0);
2479 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2480 }
2481
2482 switch (fb->pixel_format) {
2483 case DRM_FORMAT_C8:
2484 dspcntr |= DISPPLANE_8BPP;
2485 break;
2486 case DRM_FORMAT_XRGB1555:
2487 case DRM_FORMAT_ARGB1555:
2488 dspcntr |= DISPPLANE_BGRX555;
2489 break;
2490 case DRM_FORMAT_RGB565:
2491 dspcntr |= DISPPLANE_BGRX565;
2492 break;
2493 case DRM_FORMAT_XRGB8888:
2494 case DRM_FORMAT_ARGB8888:
2495 dspcntr |= DISPPLANE_BGRX888;
2496 break;
2497 case DRM_FORMAT_XBGR8888:
2498 case DRM_FORMAT_ABGR8888:
2499 dspcntr |= DISPPLANE_RGBX888;
2500 break;
2501 case DRM_FORMAT_XRGB2101010:
2502 case DRM_FORMAT_ARGB2101010:
2503 dspcntr |= DISPPLANE_BGRX101010;
2504 break;
2505 case DRM_FORMAT_XBGR2101010:
2506 case DRM_FORMAT_ABGR2101010:
2507 dspcntr |= DISPPLANE_RGBX101010;
2508 break;
2509 default:
2510 BUG();
2511 }
2512
2513 if (INTEL_INFO(dev)->gen >= 4 &&
2514 obj->tiling_mode != I915_TILING_NONE)
2515 dspcntr |= DISPPLANE_TILED;
2516
2517 if (IS_G4X(dev))
2518 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2519
2520 linear_offset = y * fb->pitches[0] + x * pixel_size;
2521
2522 if (INTEL_INFO(dev)->gen >= 4) {
2523 intel_crtc->dspaddr_offset =
2524 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2525 pixel_size,
2526 fb->pitches[0]);
2527 linear_offset -= intel_crtc->dspaddr_offset;
2528 } else {
2529 intel_crtc->dspaddr_offset = linear_offset;
2530 }
2531
2532 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2533 dspcntr |= DISPPLANE_ROTATE_180;
2534
2535 x += (intel_crtc->config.pipe_src_w - 1);
2536 y += (intel_crtc->config.pipe_src_h - 1);
2537
2538 /* Finding the last pixel of the last line of the display
2539 data and adding to linear_offset*/
2540 linear_offset +=
2541 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2542 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2543 }
2544
2545 I915_WRITE(reg, dspcntr);
2546
2547 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2548 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2549 fb->pitches[0]);
2550 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2551 if (INTEL_INFO(dev)->gen >= 4) {
2552 I915_WRITE(DSPSURF(plane),
2553 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2554 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2555 I915_WRITE(DSPLINOFF(plane), linear_offset);
2556 } else
2557 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2558 POSTING_READ(reg);
2559 }
2560
2561 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2562 struct drm_framebuffer *fb,
2563 int x, int y)
2564 {
2565 struct drm_device *dev = crtc->dev;
2566 struct drm_i915_private *dev_priv = dev->dev_private;
2567 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2568 struct drm_i915_gem_object *obj;
2569 int plane = intel_crtc->plane;
2570 unsigned long linear_offset;
2571 u32 dspcntr;
2572 u32 reg = DSPCNTR(plane);
2573 int pixel_size;
2574
2575 if (!intel_crtc->primary_enabled) {
2576 I915_WRITE(reg, 0);
2577 I915_WRITE(DSPSURF(plane), 0);
2578 POSTING_READ(reg);
2579 return;
2580 }
2581
2582 obj = intel_fb_obj(fb);
2583 if (WARN_ON(obj == NULL))
2584 return;
2585
2586 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2587
2588 dspcntr = DISPPLANE_GAMMA_ENABLE;
2589
2590 dspcntr |= DISPLAY_PLANE_ENABLE;
2591
2592 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2593 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2594
2595 switch (fb->pixel_format) {
2596 case DRM_FORMAT_C8:
2597 dspcntr |= DISPPLANE_8BPP;
2598 break;
2599 case DRM_FORMAT_RGB565:
2600 dspcntr |= DISPPLANE_BGRX565;
2601 break;
2602 case DRM_FORMAT_XRGB8888:
2603 case DRM_FORMAT_ARGB8888:
2604 dspcntr |= DISPPLANE_BGRX888;
2605 break;
2606 case DRM_FORMAT_XBGR8888:
2607 case DRM_FORMAT_ABGR8888:
2608 dspcntr |= DISPPLANE_RGBX888;
2609 break;
2610 case DRM_FORMAT_XRGB2101010:
2611 case DRM_FORMAT_ARGB2101010:
2612 dspcntr |= DISPPLANE_BGRX101010;
2613 break;
2614 case DRM_FORMAT_XBGR2101010:
2615 case DRM_FORMAT_ABGR2101010:
2616 dspcntr |= DISPPLANE_RGBX101010;
2617 break;
2618 default:
2619 BUG();
2620 }
2621
2622 if (obj->tiling_mode != I915_TILING_NONE)
2623 dspcntr |= DISPPLANE_TILED;
2624
2625 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2626 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2627
2628 linear_offset = y * fb->pitches[0] + x * pixel_size;
2629 intel_crtc->dspaddr_offset =
2630 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2631 pixel_size,
2632 fb->pitches[0]);
2633 linear_offset -= intel_crtc->dspaddr_offset;
2634 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2635 dspcntr |= DISPPLANE_ROTATE_180;
2636
2637 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2638 x += (intel_crtc->config.pipe_src_w - 1);
2639 y += (intel_crtc->config.pipe_src_h - 1);
2640
2641 /* Finding the last pixel of the last line of the display
2642 data and adding to linear_offset*/
2643 linear_offset +=
2644 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2645 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2646 }
2647 }
2648
2649 I915_WRITE(reg, dspcntr);
2650
2651 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2652 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2653 fb->pitches[0]);
2654 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2655 I915_WRITE(DSPSURF(plane),
2656 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2657 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2658 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2659 } else {
2660 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2661 I915_WRITE(DSPLINOFF(plane), linear_offset);
2662 }
2663 POSTING_READ(reg);
2664 }
2665
2666 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2667 struct drm_framebuffer *fb,
2668 int x, int y)
2669 {
2670 struct drm_device *dev = crtc->dev;
2671 struct drm_i915_private *dev_priv = dev->dev_private;
2672 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2673 struct intel_framebuffer *intel_fb;
2674 struct drm_i915_gem_object *obj;
2675 int pipe = intel_crtc->pipe;
2676 u32 plane_ctl, stride;
2677
2678 if (!intel_crtc->primary_enabled) {
2679 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2680 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2681 POSTING_READ(PLANE_CTL(pipe, 0));
2682 return;
2683 }
2684
2685 plane_ctl = PLANE_CTL_ENABLE |
2686 PLANE_CTL_PIPE_GAMMA_ENABLE |
2687 PLANE_CTL_PIPE_CSC_ENABLE;
2688
2689 switch (fb->pixel_format) {
2690 case DRM_FORMAT_RGB565:
2691 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2692 break;
2693 case DRM_FORMAT_XRGB8888:
2694 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2695 break;
2696 case DRM_FORMAT_XBGR8888:
2697 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2698 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2699 break;
2700 case DRM_FORMAT_XRGB2101010:
2701 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2702 break;
2703 case DRM_FORMAT_XBGR2101010:
2704 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2705 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2706 break;
2707 default:
2708 BUG();
2709 }
2710
2711 intel_fb = to_intel_framebuffer(fb);
2712 obj = intel_fb->obj;
2713
2714 /*
2715 * The stride is either expressed as a multiple of 64 bytes chunks for
2716 * linear buffers or in number of tiles for tiled buffers.
2717 */
2718 switch (obj->tiling_mode) {
2719 case I915_TILING_NONE:
2720 stride = fb->pitches[0] >> 6;
2721 break;
2722 case I915_TILING_X:
2723 plane_ctl |= PLANE_CTL_TILED_X;
2724 stride = fb->pitches[0] >> 9;
2725 break;
2726 default:
2727 BUG();
2728 }
2729
2730 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2731 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180))
2732 plane_ctl |= PLANE_CTL_ROTATE_180;
2733
2734 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2735
2736 DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2737 i915_gem_obj_ggtt_offset(obj),
2738 x, y, fb->width, fb->height,
2739 fb->pitches[0]);
2740
2741 I915_WRITE(PLANE_POS(pipe, 0), 0);
2742 I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2743 I915_WRITE(PLANE_SIZE(pipe, 0),
2744 (intel_crtc->config.pipe_src_h - 1) << 16 |
2745 (intel_crtc->config.pipe_src_w - 1));
2746 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
2747 I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2748
2749 POSTING_READ(PLANE_SURF(pipe, 0));
2750 }
2751
2752 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2753 static int
2754 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2755 int x, int y, enum mode_set_atomic state)
2756 {
2757 struct drm_device *dev = crtc->dev;
2758 struct drm_i915_private *dev_priv = dev->dev_private;
2759
2760 if (dev_priv->display.disable_fbc)
2761 dev_priv->display.disable_fbc(dev);
2762
2763 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2764
2765 return 0;
2766 }
2767
2768 void intel_display_handle_reset(struct drm_device *dev)
2769 {
2770 struct drm_i915_private *dev_priv = dev->dev_private;
2771 struct drm_crtc *crtc;
2772
2773 /*
2774 * Flips in the rings have been nuked by the reset,
2775 * so complete all pending flips so that user space
2776 * will get its events and not get stuck.
2777 *
2778 * Also update the base address of all primary
2779 * planes to the the last fb to make sure we're
2780 * showing the correct fb after a reset.
2781 *
2782 * Need to make two loops over the crtcs so that we
2783 * don't try to grab a crtc mutex before the
2784 * pending_flip_queue really got woken up.
2785 */
2786
2787 for_each_crtc(dev, crtc) {
2788 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2789 enum plane plane = intel_crtc->plane;
2790
2791 intel_prepare_page_flip(dev, plane);
2792 intel_finish_page_flip_plane(dev, plane);
2793 }
2794
2795 for_each_crtc(dev, crtc) {
2796 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2797
2798 drm_modeset_lock(&crtc->mutex, NULL);
2799 /*
2800 * FIXME: Once we have proper support for primary planes (and
2801 * disabling them without disabling the entire crtc) allow again
2802 * a NULL crtc->primary->fb.
2803 */
2804 if (intel_crtc->active && crtc->primary->fb)
2805 dev_priv->display.update_primary_plane(crtc,
2806 crtc->primary->fb,
2807 crtc->x,
2808 crtc->y);
2809 drm_modeset_unlock(&crtc->mutex);
2810 }
2811 }
2812
2813 static int
2814 intel_finish_fb(struct drm_framebuffer *old_fb)
2815 {
2816 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2817 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2818 bool was_interruptible = dev_priv->mm.interruptible;
2819 int ret;
2820
2821 /* Big Hammer, we also need to ensure that any pending
2822 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2823 * current scanout is retired before unpinning the old
2824 * framebuffer.
2825 *
2826 * This should only fail upon a hung GPU, in which case we
2827 * can safely continue.
2828 */
2829 dev_priv->mm.interruptible = false;
2830 ret = i915_gem_object_finish_gpu(obj);
2831 dev_priv->mm.interruptible = was_interruptible;
2832
2833 return ret;
2834 }
2835
2836 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2837 {
2838 struct drm_device *dev = crtc->dev;
2839 struct drm_i915_private *dev_priv = dev->dev_private;
2840 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2841 bool pending;
2842
2843 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2844 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2845 return false;
2846
2847 spin_lock_irq(&dev->event_lock);
2848 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2849 spin_unlock_irq(&dev->event_lock);
2850
2851 return pending;
2852 }
2853
2854 static void intel_update_pipe_size(struct intel_crtc *crtc)
2855 {
2856 struct drm_device *dev = crtc->base.dev;
2857 struct drm_i915_private *dev_priv = dev->dev_private;
2858 const struct drm_display_mode *adjusted_mode;
2859
2860 if (!i915.fastboot)
2861 return;
2862
2863 /*
2864 * Update pipe size and adjust fitter if needed: the reason for this is
2865 * that in compute_mode_changes we check the native mode (not the pfit
2866 * mode) to see if we can flip rather than do a full mode set. In the
2867 * fastboot case, we'll flip, but if we don't update the pipesrc and
2868 * pfit state, we'll end up with a big fb scanned out into the wrong
2869 * sized surface.
2870 *
2871 * To fix this properly, we need to hoist the checks up into
2872 * compute_mode_changes (or above), check the actual pfit state and
2873 * whether the platform allows pfit disable with pipe active, and only
2874 * then update the pipesrc and pfit state, even on the flip path.
2875 */
2876
2877 adjusted_mode = &crtc->config.adjusted_mode;
2878
2879 I915_WRITE(PIPESRC(crtc->pipe),
2880 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2881 (adjusted_mode->crtc_vdisplay - 1));
2882 if (!crtc->config.pch_pfit.enabled &&
2883 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2884 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2885 I915_WRITE(PF_CTL(crtc->pipe), 0);
2886 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
2887 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
2888 }
2889 crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2890 crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2891 }
2892
2893 static int
2894 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2895 struct drm_framebuffer *fb)
2896 {
2897 struct drm_device *dev = crtc->dev;
2898 struct drm_i915_private *dev_priv = dev->dev_private;
2899 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2900 enum pipe pipe = intel_crtc->pipe;
2901 struct drm_framebuffer *old_fb = crtc->primary->fb;
2902 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
2903 int ret;
2904
2905 if (intel_crtc_has_pending_flip(crtc)) {
2906 DRM_ERROR("pipe is still busy with an old pageflip\n");
2907 return -EBUSY;
2908 }
2909
2910 /* no fb bound */
2911 if (!fb) {
2912 DRM_ERROR("No FB bound\n");
2913 return 0;
2914 }
2915
2916 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2917 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2918 plane_name(intel_crtc->plane),
2919 INTEL_INFO(dev)->num_pipes);
2920 return -EINVAL;
2921 }
2922
2923 mutex_lock(&dev->struct_mutex);
2924 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, NULL);
2925 if (ret == 0)
2926 i915_gem_track_fb(old_obj, intel_fb_obj(fb),
2927 INTEL_FRONTBUFFER_PRIMARY(pipe));
2928 mutex_unlock(&dev->struct_mutex);
2929 if (ret != 0) {
2930 DRM_ERROR("pin & fence failed\n");
2931 return ret;
2932 }
2933
2934 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2935
2936 if (intel_crtc->active)
2937 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
2938
2939 crtc->primary->fb = fb;
2940 crtc->x = x;
2941 crtc->y = y;
2942
2943 if (old_fb) {
2944 if (intel_crtc->active && old_fb != fb)
2945 intel_wait_for_vblank(dev, intel_crtc->pipe);
2946 mutex_lock(&dev->struct_mutex);
2947 intel_unpin_fb_obj(old_obj);
2948 mutex_unlock(&dev->struct_mutex);
2949 }
2950
2951 mutex_lock(&dev->struct_mutex);
2952 intel_update_fbc(dev);
2953 mutex_unlock(&dev->struct_mutex);
2954
2955 return 0;
2956 }
2957
2958 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2959 {
2960 struct drm_device *dev = crtc->dev;
2961 struct drm_i915_private *dev_priv = dev->dev_private;
2962 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2963 int pipe = intel_crtc->pipe;
2964 u32 reg, temp;
2965
2966 /* enable normal train */
2967 reg = FDI_TX_CTL(pipe);
2968 temp = I915_READ(reg);
2969 if (IS_IVYBRIDGE(dev)) {
2970 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2971 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2972 } else {
2973 temp &= ~FDI_LINK_TRAIN_NONE;
2974 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2975 }
2976 I915_WRITE(reg, temp);
2977
2978 reg = FDI_RX_CTL(pipe);
2979 temp = I915_READ(reg);
2980 if (HAS_PCH_CPT(dev)) {
2981 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2982 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2983 } else {
2984 temp &= ~FDI_LINK_TRAIN_NONE;
2985 temp |= FDI_LINK_TRAIN_NONE;
2986 }
2987 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2988
2989 /* wait one idle pattern time */
2990 POSTING_READ(reg);
2991 udelay(1000);
2992
2993 /* IVB wants error correction enabled */
2994 if (IS_IVYBRIDGE(dev))
2995 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2996 FDI_FE_ERRC_ENABLE);
2997 }
2998
2999 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
3000 {
3001 return crtc->base.enabled && crtc->active &&
3002 crtc->config.has_pch_encoder;
3003 }
3004
3005 static void ivb_modeset_global_resources(struct drm_device *dev)
3006 {
3007 struct drm_i915_private *dev_priv = dev->dev_private;
3008 struct intel_crtc *pipe_B_crtc =
3009 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3010 struct intel_crtc *pipe_C_crtc =
3011 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
3012 uint32_t temp;
3013
3014 /*
3015 * When everything is off disable fdi C so that we could enable fdi B
3016 * with all lanes. Note that we don't care about enabled pipes without
3017 * an enabled pch encoder.
3018 */
3019 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
3020 !pipe_has_enabled_pch(pipe_C_crtc)) {
3021 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3022 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3023
3024 temp = I915_READ(SOUTH_CHICKEN1);
3025 temp &= ~FDI_BC_BIFURCATION_SELECT;
3026 DRM_DEBUG_KMS("disabling fdi C rx\n");
3027 I915_WRITE(SOUTH_CHICKEN1, temp);
3028 }
3029 }
3030
3031 /* The FDI link training functions for ILK/Ibexpeak. */
3032 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3033 {
3034 struct drm_device *dev = crtc->dev;
3035 struct drm_i915_private *dev_priv = dev->dev_private;
3036 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3037 int pipe = intel_crtc->pipe;
3038 u32 reg, temp, tries;
3039
3040 /* FDI needs bits from pipe first */
3041 assert_pipe_enabled(dev_priv, pipe);
3042
3043 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3044 for train result */
3045 reg = FDI_RX_IMR(pipe);
3046 temp = I915_READ(reg);
3047 temp &= ~FDI_RX_SYMBOL_LOCK;
3048 temp &= ~FDI_RX_BIT_LOCK;
3049 I915_WRITE(reg, temp);
3050 I915_READ(reg);
3051 udelay(150);
3052
3053 /* enable CPU FDI TX and PCH FDI RX */
3054 reg = FDI_TX_CTL(pipe);
3055 temp = I915_READ(reg);
3056 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3057 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3058 temp &= ~FDI_LINK_TRAIN_NONE;
3059 temp |= FDI_LINK_TRAIN_PATTERN_1;
3060 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3061
3062 reg = FDI_RX_CTL(pipe);
3063 temp = I915_READ(reg);
3064 temp &= ~FDI_LINK_TRAIN_NONE;
3065 temp |= FDI_LINK_TRAIN_PATTERN_1;
3066 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3067
3068 POSTING_READ(reg);
3069 udelay(150);
3070
3071 /* Ironlake workaround, enable clock pointer after FDI enable*/
3072 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3073 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3074 FDI_RX_PHASE_SYNC_POINTER_EN);
3075
3076 reg = FDI_RX_IIR(pipe);
3077 for (tries = 0; tries < 5; tries++) {
3078 temp = I915_READ(reg);
3079 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3080
3081 if ((temp & FDI_RX_BIT_LOCK)) {
3082 DRM_DEBUG_KMS("FDI train 1 done.\n");
3083 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3084 break;
3085 }
3086 }
3087 if (tries == 5)
3088 DRM_ERROR("FDI train 1 fail!\n");
3089
3090 /* Train 2 */
3091 reg = FDI_TX_CTL(pipe);
3092 temp = I915_READ(reg);
3093 temp &= ~FDI_LINK_TRAIN_NONE;
3094 temp |= FDI_LINK_TRAIN_PATTERN_2;
3095 I915_WRITE(reg, temp);
3096
3097 reg = FDI_RX_CTL(pipe);
3098 temp = I915_READ(reg);
3099 temp &= ~FDI_LINK_TRAIN_NONE;
3100 temp |= FDI_LINK_TRAIN_PATTERN_2;
3101 I915_WRITE(reg, temp);
3102
3103 POSTING_READ(reg);
3104 udelay(150);
3105
3106 reg = FDI_RX_IIR(pipe);
3107 for (tries = 0; tries < 5; tries++) {
3108 temp = I915_READ(reg);
3109 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3110
3111 if (temp & FDI_RX_SYMBOL_LOCK) {
3112 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3113 DRM_DEBUG_KMS("FDI train 2 done.\n");
3114 break;
3115 }
3116 }
3117 if (tries == 5)
3118 DRM_ERROR("FDI train 2 fail!\n");
3119
3120 DRM_DEBUG_KMS("FDI train done\n");
3121
3122 }
3123
3124 static const int snb_b_fdi_train_param[] = {
3125 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3126 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3127 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3128 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3129 };
3130
3131 /* The FDI link training functions for SNB/Cougarpoint. */
3132 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3133 {
3134 struct drm_device *dev = crtc->dev;
3135 struct drm_i915_private *dev_priv = dev->dev_private;
3136 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3137 int pipe = intel_crtc->pipe;
3138 u32 reg, temp, i, retry;
3139
3140 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3141 for train result */
3142 reg = FDI_RX_IMR(pipe);
3143 temp = I915_READ(reg);
3144 temp &= ~FDI_RX_SYMBOL_LOCK;
3145 temp &= ~FDI_RX_BIT_LOCK;
3146 I915_WRITE(reg, temp);
3147
3148 POSTING_READ(reg);
3149 udelay(150);
3150
3151 /* enable CPU FDI TX and PCH FDI RX */
3152 reg = FDI_TX_CTL(pipe);
3153 temp = I915_READ(reg);
3154 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3155 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3156 temp &= ~FDI_LINK_TRAIN_NONE;
3157 temp |= FDI_LINK_TRAIN_PATTERN_1;
3158 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3159 /* SNB-B */
3160 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3161 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3162
3163 I915_WRITE(FDI_RX_MISC(pipe),
3164 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3165
3166 reg = FDI_RX_CTL(pipe);
3167 temp = I915_READ(reg);
3168 if (HAS_PCH_CPT(dev)) {
3169 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3170 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3171 } else {
3172 temp &= ~FDI_LINK_TRAIN_NONE;
3173 temp |= FDI_LINK_TRAIN_PATTERN_1;
3174 }
3175 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3176
3177 POSTING_READ(reg);
3178 udelay(150);
3179
3180 for (i = 0; i < 4; i++) {
3181 reg = FDI_TX_CTL(pipe);
3182 temp = I915_READ(reg);
3183 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3184 temp |= snb_b_fdi_train_param[i];
3185 I915_WRITE(reg, temp);
3186
3187 POSTING_READ(reg);
3188 udelay(500);
3189
3190 for (retry = 0; retry < 5; retry++) {
3191 reg = FDI_RX_IIR(pipe);
3192 temp = I915_READ(reg);
3193 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3194 if (temp & FDI_RX_BIT_LOCK) {
3195 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3196 DRM_DEBUG_KMS("FDI train 1 done.\n");
3197 break;
3198 }
3199 udelay(50);
3200 }
3201 if (retry < 5)
3202 break;
3203 }
3204 if (i == 4)
3205 DRM_ERROR("FDI train 1 fail!\n");
3206
3207 /* Train 2 */
3208 reg = FDI_TX_CTL(pipe);
3209 temp = I915_READ(reg);
3210 temp &= ~FDI_LINK_TRAIN_NONE;
3211 temp |= FDI_LINK_TRAIN_PATTERN_2;
3212 if (IS_GEN6(dev)) {
3213 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3214 /* SNB-B */
3215 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3216 }
3217 I915_WRITE(reg, temp);
3218
3219 reg = FDI_RX_CTL(pipe);
3220 temp = I915_READ(reg);
3221 if (HAS_PCH_CPT(dev)) {
3222 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3223 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3224 } else {
3225 temp &= ~FDI_LINK_TRAIN_NONE;
3226 temp |= FDI_LINK_TRAIN_PATTERN_2;
3227 }
3228 I915_WRITE(reg, temp);
3229
3230 POSTING_READ(reg);
3231 udelay(150);
3232
3233 for (i = 0; i < 4; i++) {
3234 reg = FDI_TX_CTL(pipe);
3235 temp = I915_READ(reg);
3236 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3237 temp |= snb_b_fdi_train_param[i];
3238 I915_WRITE(reg, temp);
3239
3240 POSTING_READ(reg);
3241 udelay(500);
3242
3243 for (retry = 0; retry < 5; retry++) {
3244 reg = FDI_RX_IIR(pipe);
3245 temp = I915_READ(reg);
3246 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3247 if (temp & FDI_RX_SYMBOL_LOCK) {
3248 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3249 DRM_DEBUG_KMS("FDI train 2 done.\n");
3250 break;
3251 }
3252 udelay(50);
3253 }
3254 if (retry < 5)
3255 break;
3256 }
3257 if (i == 4)
3258 DRM_ERROR("FDI train 2 fail!\n");
3259
3260 DRM_DEBUG_KMS("FDI train done.\n");
3261 }
3262
3263 /* Manual link training for Ivy Bridge A0 parts */
3264 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3265 {
3266 struct drm_device *dev = crtc->dev;
3267 struct drm_i915_private *dev_priv = dev->dev_private;
3268 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3269 int pipe = intel_crtc->pipe;
3270 u32 reg, temp, i, j;
3271
3272 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3273 for train result */
3274 reg = FDI_RX_IMR(pipe);
3275 temp = I915_READ(reg);
3276 temp &= ~FDI_RX_SYMBOL_LOCK;
3277 temp &= ~FDI_RX_BIT_LOCK;
3278 I915_WRITE(reg, temp);
3279
3280 POSTING_READ(reg);
3281 udelay(150);
3282
3283 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3284 I915_READ(FDI_RX_IIR(pipe)));
3285
3286 /* Try each vswing and preemphasis setting twice before moving on */
3287 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3288 /* disable first in case we need to retry */
3289 reg = FDI_TX_CTL(pipe);
3290 temp = I915_READ(reg);
3291 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3292 temp &= ~FDI_TX_ENABLE;
3293 I915_WRITE(reg, temp);
3294
3295 reg = FDI_RX_CTL(pipe);
3296 temp = I915_READ(reg);
3297 temp &= ~FDI_LINK_TRAIN_AUTO;
3298 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3299 temp &= ~FDI_RX_ENABLE;
3300 I915_WRITE(reg, temp);
3301
3302 /* enable CPU FDI TX and PCH FDI RX */
3303 reg = FDI_TX_CTL(pipe);
3304 temp = I915_READ(reg);
3305 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3306 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3307 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3308 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3309 temp |= snb_b_fdi_train_param[j/2];
3310 temp |= FDI_COMPOSITE_SYNC;
3311 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3312
3313 I915_WRITE(FDI_RX_MISC(pipe),
3314 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3315
3316 reg = FDI_RX_CTL(pipe);
3317 temp = I915_READ(reg);
3318 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3319 temp |= FDI_COMPOSITE_SYNC;
3320 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3321
3322 POSTING_READ(reg);
3323 udelay(1); /* should be 0.5us */
3324
3325 for (i = 0; i < 4; i++) {
3326 reg = FDI_RX_IIR(pipe);
3327 temp = I915_READ(reg);
3328 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3329
3330 if (temp & FDI_RX_BIT_LOCK ||
3331 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3332 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3333 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3334 i);
3335 break;
3336 }
3337 udelay(1); /* should be 0.5us */
3338 }
3339 if (i == 4) {
3340 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3341 continue;
3342 }
3343
3344 /* Train 2 */
3345 reg = FDI_TX_CTL(pipe);
3346 temp = I915_READ(reg);
3347 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3348 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3349 I915_WRITE(reg, temp);
3350
3351 reg = FDI_RX_CTL(pipe);
3352 temp = I915_READ(reg);
3353 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3354 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3355 I915_WRITE(reg, temp);
3356
3357 POSTING_READ(reg);
3358 udelay(2); /* should be 1.5us */
3359
3360 for (i = 0; i < 4; i++) {
3361 reg = FDI_RX_IIR(pipe);
3362 temp = I915_READ(reg);
3363 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3364
3365 if (temp & FDI_RX_SYMBOL_LOCK ||
3366 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3367 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3368 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3369 i);
3370 goto train_done;
3371 }
3372 udelay(2); /* should be 1.5us */
3373 }
3374 if (i == 4)
3375 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3376 }
3377
3378 train_done:
3379 DRM_DEBUG_KMS("FDI train done.\n");
3380 }
3381
3382 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3383 {
3384 struct drm_device *dev = intel_crtc->base.dev;
3385 struct drm_i915_private *dev_priv = dev->dev_private;
3386 int pipe = intel_crtc->pipe;
3387 u32 reg, temp;
3388
3389
3390 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3391 reg = FDI_RX_CTL(pipe);
3392 temp = I915_READ(reg);
3393 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3394 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3395 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3396 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3397
3398 POSTING_READ(reg);
3399 udelay(200);
3400
3401 /* Switch from Rawclk to PCDclk */
3402 temp = I915_READ(reg);
3403 I915_WRITE(reg, temp | FDI_PCDCLK);
3404
3405 POSTING_READ(reg);
3406 udelay(200);
3407
3408 /* Enable CPU FDI TX PLL, always on for Ironlake */
3409 reg = FDI_TX_CTL(pipe);
3410 temp = I915_READ(reg);
3411 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3412 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3413
3414 POSTING_READ(reg);
3415 udelay(100);
3416 }
3417 }
3418
3419 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3420 {
3421 struct drm_device *dev = intel_crtc->base.dev;
3422 struct drm_i915_private *dev_priv = dev->dev_private;
3423 int pipe = intel_crtc->pipe;
3424 u32 reg, temp;
3425
3426 /* Switch from PCDclk to Rawclk */
3427 reg = FDI_RX_CTL(pipe);
3428 temp = I915_READ(reg);
3429 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3430
3431 /* Disable CPU FDI TX PLL */
3432 reg = FDI_TX_CTL(pipe);
3433 temp = I915_READ(reg);
3434 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3435
3436 POSTING_READ(reg);
3437 udelay(100);
3438
3439 reg = FDI_RX_CTL(pipe);
3440 temp = I915_READ(reg);
3441 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3442
3443 /* Wait for the clocks to turn off. */
3444 POSTING_READ(reg);
3445 udelay(100);
3446 }
3447
3448 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3449 {
3450 struct drm_device *dev = crtc->dev;
3451 struct drm_i915_private *dev_priv = dev->dev_private;
3452 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3453 int pipe = intel_crtc->pipe;
3454 u32 reg, temp;
3455
3456 /* disable CPU FDI tx and PCH FDI rx */
3457 reg = FDI_TX_CTL(pipe);
3458 temp = I915_READ(reg);
3459 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3460 POSTING_READ(reg);
3461
3462 reg = FDI_RX_CTL(pipe);
3463 temp = I915_READ(reg);
3464 temp &= ~(0x7 << 16);
3465 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3466 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3467
3468 POSTING_READ(reg);
3469 udelay(100);
3470
3471 /* Ironlake workaround, disable clock pointer after downing FDI */
3472 if (HAS_PCH_IBX(dev))
3473 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3474
3475 /* still set train pattern 1 */
3476 reg = FDI_TX_CTL(pipe);
3477 temp = I915_READ(reg);
3478 temp &= ~FDI_LINK_TRAIN_NONE;
3479 temp |= FDI_LINK_TRAIN_PATTERN_1;
3480 I915_WRITE(reg, temp);
3481
3482 reg = FDI_RX_CTL(pipe);
3483 temp = I915_READ(reg);
3484 if (HAS_PCH_CPT(dev)) {
3485 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3486 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3487 } else {
3488 temp &= ~FDI_LINK_TRAIN_NONE;
3489 temp |= FDI_LINK_TRAIN_PATTERN_1;
3490 }
3491 /* BPC in FDI rx is consistent with that in PIPECONF */
3492 temp &= ~(0x07 << 16);
3493 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3494 I915_WRITE(reg, temp);
3495
3496 POSTING_READ(reg);
3497 udelay(100);
3498 }
3499
3500 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3501 {
3502 struct intel_crtc *crtc;
3503
3504 /* Note that we don't need to be called with mode_config.lock here
3505 * as our list of CRTC objects is static for the lifetime of the
3506 * device and so cannot disappear as we iterate. Similarly, we can
3507 * happily treat the predicates as racy, atomic checks as userspace
3508 * cannot claim and pin a new fb without at least acquring the
3509 * struct_mutex and so serialising with us.
3510 */
3511 for_each_intel_crtc(dev, crtc) {
3512 if (atomic_read(&crtc->unpin_work_count) == 0)
3513 continue;
3514
3515 if (crtc->unpin_work)
3516 intel_wait_for_vblank(dev, crtc->pipe);
3517
3518 return true;
3519 }
3520
3521 return false;
3522 }
3523
3524 static void page_flip_completed(struct intel_crtc *intel_crtc)
3525 {
3526 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3527 struct intel_unpin_work *work = intel_crtc->unpin_work;
3528
3529 /* ensure that the unpin work is consistent wrt ->pending. */
3530 smp_rmb();
3531 intel_crtc->unpin_work = NULL;
3532
3533 if (work->event)
3534 drm_send_vblank_event(intel_crtc->base.dev,
3535 intel_crtc->pipe,
3536 work->event);
3537
3538 drm_crtc_vblank_put(&intel_crtc->base);
3539
3540 wake_up_all(&dev_priv->pending_flip_queue);
3541 queue_work(dev_priv->wq, &work->work);
3542
3543 trace_i915_flip_complete(intel_crtc->plane,
3544 work->pending_flip_obj);
3545 }
3546
3547 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3548 {
3549 struct drm_device *dev = crtc->dev;
3550 struct drm_i915_private *dev_priv = dev->dev_private;
3551
3552 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3553 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3554 !intel_crtc_has_pending_flip(crtc),
3555 60*HZ) == 0)) {
3556 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3557
3558 spin_lock_irq(&dev->event_lock);
3559 if (intel_crtc->unpin_work) {
3560 WARN_ONCE(1, "Removing stuck page flip\n");
3561 page_flip_completed(intel_crtc);
3562 }
3563 spin_unlock_irq(&dev->event_lock);
3564 }
3565
3566 if (crtc->primary->fb) {
3567 mutex_lock(&dev->struct_mutex);
3568 intel_finish_fb(crtc->primary->fb);
3569 mutex_unlock(&dev->struct_mutex);
3570 }
3571 }
3572
3573 /* Program iCLKIP clock to the desired frequency */
3574 static void lpt_program_iclkip(struct drm_crtc *crtc)
3575 {
3576 struct drm_device *dev = crtc->dev;
3577 struct drm_i915_private *dev_priv = dev->dev_private;
3578 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3579 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3580 u32 temp;
3581
3582 mutex_lock(&dev_priv->dpio_lock);
3583
3584 /* It is necessary to ungate the pixclk gate prior to programming
3585 * the divisors, and gate it back when it is done.
3586 */
3587 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3588
3589 /* Disable SSCCTL */
3590 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3591 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3592 SBI_SSCCTL_DISABLE,
3593 SBI_ICLK);
3594
3595 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3596 if (clock == 20000) {
3597 auxdiv = 1;
3598 divsel = 0x41;
3599 phaseinc = 0x20;
3600 } else {
3601 /* The iCLK virtual clock root frequency is in MHz,
3602 * but the adjusted_mode->crtc_clock in in KHz. To get the
3603 * divisors, it is necessary to divide one by another, so we
3604 * convert the virtual clock precision to KHz here for higher
3605 * precision.
3606 */
3607 u32 iclk_virtual_root_freq = 172800 * 1000;
3608 u32 iclk_pi_range = 64;
3609 u32 desired_divisor, msb_divisor_value, pi_value;
3610
3611 desired_divisor = (iclk_virtual_root_freq / clock);
3612 msb_divisor_value = desired_divisor / iclk_pi_range;
3613 pi_value = desired_divisor % iclk_pi_range;
3614
3615 auxdiv = 0;
3616 divsel = msb_divisor_value - 2;
3617 phaseinc = pi_value;
3618 }
3619
3620 /* This should not happen with any sane values */
3621 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3622 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3623 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3624 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3625
3626 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3627 clock,
3628 auxdiv,
3629 divsel,
3630 phasedir,
3631 phaseinc);
3632
3633 /* Program SSCDIVINTPHASE6 */
3634 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3635 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3636 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3637 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3638 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3639 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3640 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3641 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3642
3643 /* Program SSCAUXDIV */
3644 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3645 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3646 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3647 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3648
3649 /* Enable modulator and associated divider */
3650 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3651 temp &= ~SBI_SSCCTL_DISABLE;
3652 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3653
3654 /* Wait for initialization time */
3655 udelay(24);
3656
3657 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3658
3659 mutex_unlock(&dev_priv->dpio_lock);
3660 }
3661
3662 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3663 enum pipe pch_transcoder)
3664 {
3665 struct drm_device *dev = crtc->base.dev;
3666 struct drm_i915_private *dev_priv = dev->dev_private;
3667 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3668
3669 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3670 I915_READ(HTOTAL(cpu_transcoder)));
3671 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3672 I915_READ(HBLANK(cpu_transcoder)));
3673 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3674 I915_READ(HSYNC(cpu_transcoder)));
3675
3676 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3677 I915_READ(VTOTAL(cpu_transcoder)));
3678 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3679 I915_READ(VBLANK(cpu_transcoder)));
3680 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3681 I915_READ(VSYNC(cpu_transcoder)));
3682 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3683 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3684 }
3685
3686 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3687 {
3688 struct drm_i915_private *dev_priv = dev->dev_private;
3689 uint32_t temp;
3690
3691 temp = I915_READ(SOUTH_CHICKEN1);
3692 if (temp & FDI_BC_BIFURCATION_SELECT)
3693 return;
3694
3695 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3696 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3697
3698 temp |= FDI_BC_BIFURCATION_SELECT;
3699 DRM_DEBUG_KMS("enabling fdi C rx\n");
3700 I915_WRITE(SOUTH_CHICKEN1, temp);
3701 POSTING_READ(SOUTH_CHICKEN1);
3702 }
3703
3704 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3705 {
3706 struct drm_device *dev = intel_crtc->base.dev;
3707 struct drm_i915_private *dev_priv = dev->dev_private;
3708
3709 switch (intel_crtc->pipe) {
3710 case PIPE_A:
3711 break;
3712 case PIPE_B:
3713 if (intel_crtc->config.fdi_lanes > 2)
3714 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3715 else
3716 cpt_enable_fdi_bc_bifurcation(dev);
3717
3718 break;
3719 case PIPE_C:
3720 cpt_enable_fdi_bc_bifurcation(dev);
3721
3722 break;
3723 default:
3724 BUG();
3725 }
3726 }
3727
3728 /*
3729 * Enable PCH resources required for PCH ports:
3730 * - PCH PLLs
3731 * - FDI training & RX/TX
3732 * - update transcoder timings
3733 * - DP transcoding bits
3734 * - transcoder
3735 */
3736 static void ironlake_pch_enable(struct drm_crtc *crtc)
3737 {
3738 struct drm_device *dev = crtc->dev;
3739 struct drm_i915_private *dev_priv = dev->dev_private;
3740 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3741 int pipe = intel_crtc->pipe;
3742 u32 reg, temp;
3743
3744 assert_pch_transcoder_disabled(dev_priv, pipe);
3745
3746 if (IS_IVYBRIDGE(dev))
3747 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3748
3749 /* Write the TU size bits before fdi link training, so that error
3750 * detection works. */
3751 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3752 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3753
3754 /* For PCH output, training FDI link */
3755 dev_priv->display.fdi_link_train(crtc);
3756
3757 /* We need to program the right clock selection before writing the pixel
3758 * mutliplier into the DPLL. */
3759 if (HAS_PCH_CPT(dev)) {
3760 u32 sel;
3761
3762 temp = I915_READ(PCH_DPLL_SEL);
3763 temp |= TRANS_DPLL_ENABLE(pipe);
3764 sel = TRANS_DPLLB_SEL(pipe);
3765 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3766 temp |= sel;
3767 else
3768 temp &= ~sel;
3769 I915_WRITE(PCH_DPLL_SEL, temp);
3770 }
3771
3772 /* XXX: pch pll's can be enabled any time before we enable the PCH
3773 * transcoder, and we actually should do this to not upset any PCH
3774 * transcoder that already use the clock when we share it.
3775 *
3776 * Note that enable_shared_dpll tries to do the right thing, but
3777 * get_shared_dpll unconditionally resets the pll - we need that to have
3778 * the right LVDS enable sequence. */
3779 intel_enable_shared_dpll(intel_crtc);
3780
3781 /* set transcoder timing, panel must allow it */
3782 assert_panel_unlocked(dev_priv, pipe);
3783 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3784
3785 intel_fdi_normal_train(crtc);
3786
3787 /* For PCH DP, enable TRANS_DP_CTL */
3788 if (HAS_PCH_CPT(dev) && intel_crtc->config.has_dp_encoder) {
3789 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3790 reg = TRANS_DP_CTL(pipe);
3791 temp = I915_READ(reg);
3792 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3793 TRANS_DP_SYNC_MASK |
3794 TRANS_DP_BPC_MASK);
3795 temp |= (TRANS_DP_OUTPUT_ENABLE |
3796 TRANS_DP_ENH_FRAMING);
3797 temp |= bpc << 9; /* same format but at 11:9 */
3798
3799 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3800 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3801 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3802 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3803
3804 switch (intel_trans_dp_port_sel(crtc)) {
3805 case PCH_DP_B:
3806 temp |= TRANS_DP_PORT_SEL_B;
3807 break;
3808 case PCH_DP_C:
3809 temp |= TRANS_DP_PORT_SEL_C;
3810 break;
3811 case PCH_DP_D:
3812 temp |= TRANS_DP_PORT_SEL_D;
3813 break;
3814 default:
3815 BUG();
3816 }
3817
3818 I915_WRITE(reg, temp);
3819 }
3820
3821 ironlake_enable_pch_transcoder(dev_priv, pipe);
3822 }
3823
3824 static void lpt_pch_enable(struct drm_crtc *crtc)
3825 {
3826 struct drm_device *dev = crtc->dev;
3827 struct drm_i915_private *dev_priv = dev->dev_private;
3828 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3829 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3830
3831 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3832
3833 lpt_program_iclkip(crtc);
3834
3835 /* Set transcoder timing. */
3836 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3837
3838 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3839 }
3840
3841 void intel_put_shared_dpll(struct intel_crtc *crtc)
3842 {
3843 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3844
3845 if (pll == NULL)
3846 return;
3847
3848 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
3849 WARN(1, "bad %s crtc mask\n", pll->name);
3850 return;
3851 }
3852
3853 pll->config.crtc_mask &= ~(1 << crtc->pipe);
3854 if (pll->config.crtc_mask == 0) {
3855 WARN_ON(pll->on);
3856 WARN_ON(pll->active);
3857 }
3858
3859 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3860 }
3861
3862 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3863 {
3864 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3865 struct intel_shared_dpll *pll;
3866 enum intel_dpll_id i;
3867
3868 if (HAS_PCH_IBX(dev_priv->dev)) {
3869 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3870 i = (enum intel_dpll_id) crtc->pipe;
3871 pll = &dev_priv->shared_dplls[i];
3872
3873 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3874 crtc->base.base.id, pll->name);
3875
3876 WARN_ON(pll->new_config->crtc_mask);
3877
3878 goto found;
3879 }
3880
3881 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3882 pll = &dev_priv->shared_dplls[i];
3883
3884 /* Only want to check enabled timings first */
3885 if (pll->new_config->crtc_mask == 0)
3886 continue;
3887
3888 if (memcmp(&crtc->new_config->dpll_hw_state,
3889 &pll->new_config->hw_state,
3890 sizeof(pll->new_config->hw_state)) == 0) {
3891 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
3892 crtc->base.base.id, pll->name,
3893 pll->new_config->crtc_mask,
3894 pll->active);
3895 goto found;
3896 }
3897 }
3898
3899 /* Ok no matching timings, maybe there's a free one? */
3900 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3901 pll = &dev_priv->shared_dplls[i];
3902 if (pll->new_config->crtc_mask == 0) {
3903 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3904 crtc->base.base.id, pll->name);
3905 goto found;
3906 }
3907 }
3908
3909 return NULL;
3910
3911 found:
3912 if (pll->new_config->crtc_mask == 0)
3913 pll->new_config->hw_state = crtc->new_config->dpll_hw_state;
3914
3915 crtc->new_config->shared_dpll = i;
3916 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3917 pipe_name(crtc->pipe));
3918
3919 pll->new_config->crtc_mask |= 1 << crtc->pipe;
3920
3921 return pll;
3922 }
3923
3924 /**
3925 * intel_shared_dpll_start_config - start a new PLL staged config
3926 * @dev_priv: DRM device
3927 * @clear_pipes: mask of pipes that will have their PLLs freed
3928 *
3929 * Starts a new PLL staged config, copying the current config but
3930 * releasing the references of pipes specified in clear_pipes.
3931 */
3932 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
3933 unsigned clear_pipes)
3934 {
3935 struct intel_shared_dpll *pll;
3936 enum intel_dpll_id i;
3937
3938 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3939 pll = &dev_priv->shared_dplls[i];
3940
3941 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
3942 GFP_KERNEL);
3943 if (!pll->new_config)
3944 goto cleanup;
3945
3946 pll->new_config->crtc_mask &= ~clear_pipes;
3947 }
3948
3949 return 0;
3950
3951 cleanup:
3952 while (--i >= 0) {
3953 pll = &dev_priv->shared_dplls[i];
3954 kfree(pll->new_config);
3955 pll->new_config = NULL;
3956 }
3957
3958 return -ENOMEM;
3959 }
3960
3961 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
3962 {
3963 struct intel_shared_dpll *pll;
3964 enum intel_dpll_id i;
3965
3966 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3967 pll = &dev_priv->shared_dplls[i];
3968
3969 WARN_ON(pll->new_config == &pll->config);
3970
3971 pll->config = *pll->new_config;
3972 kfree(pll->new_config);
3973 pll->new_config = NULL;
3974 }
3975 }
3976
3977 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
3978 {
3979 struct intel_shared_dpll *pll;
3980 enum intel_dpll_id i;
3981
3982 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3983 pll = &dev_priv->shared_dplls[i];
3984
3985 WARN_ON(pll->new_config == &pll->config);
3986
3987 kfree(pll->new_config);
3988 pll->new_config = NULL;
3989 }
3990 }
3991
3992 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3993 {
3994 struct drm_i915_private *dev_priv = dev->dev_private;
3995 int dslreg = PIPEDSL(pipe);
3996 u32 temp;
3997
3998 temp = I915_READ(dslreg);
3999 udelay(500);
4000 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4001 if (wait_for(I915_READ(dslreg) != temp, 5))
4002 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4003 }
4004 }
4005
4006 static void skylake_pfit_enable(struct intel_crtc *crtc)
4007 {
4008 struct drm_device *dev = crtc->base.dev;
4009 struct drm_i915_private *dev_priv = dev->dev_private;
4010 int pipe = crtc->pipe;
4011
4012 if (crtc->config.pch_pfit.enabled) {
4013 I915_WRITE(PS_CTL(pipe), PS_ENABLE);
4014 I915_WRITE(PS_WIN_POS(pipe), crtc->config.pch_pfit.pos);
4015 I915_WRITE(PS_WIN_SZ(pipe), crtc->config.pch_pfit.size);
4016 }
4017 }
4018
4019 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4020 {
4021 struct drm_device *dev = crtc->base.dev;
4022 struct drm_i915_private *dev_priv = dev->dev_private;
4023 int pipe = crtc->pipe;
4024
4025 if (crtc->config.pch_pfit.enabled) {
4026 /* Force use of hard-coded filter coefficients
4027 * as some pre-programmed values are broken,
4028 * e.g. x201.
4029 */
4030 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4031 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4032 PF_PIPE_SEL_IVB(pipe));
4033 else
4034 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4035 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
4036 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
4037 }
4038 }
4039
4040 static void intel_enable_planes(struct drm_crtc *crtc)
4041 {
4042 struct drm_device *dev = crtc->dev;
4043 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4044 struct drm_plane *plane;
4045 struct intel_plane *intel_plane;
4046
4047 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4048 intel_plane = to_intel_plane(plane);
4049 if (intel_plane->pipe == pipe)
4050 intel_plane_restore(&intel_plane->base);
4051 }
4052 }
4053
4054 static void intel_disable_planes(struct drm_crtc *crtc)
4055 {
4056 struct drm_device *dev = crtc->dev;
4057 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4058 struct drm_plane *plane;
4059 struct intel_plane *intel_plane;
4060
4061 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4062 intel_plane = to_intel_plane(plane);
4063 if (intel_plane->pipe == pipe)
4064 intel_plane_disable(&intel_plane->base);
4065 }
4066 }
4067
4068 void hsw_enable_ips(struct intel_crtc *crtc)
4069 {
4070 struct drm_device *dev = crtc->base.dev;
4071 struct drm_i915_private *dev_priv = dev->dev_private;
4072
4073 if (!crtc->config.ips_enabled)
4074 return;
4075
4076 /* We can only enable IPS after we enable a plane and wait for a vblank */
4077 intel_wait_for_vblank(dev, crtc->pipe);
4078
4079 assert_plane_enabled(dev_priv, crtc->plane);
4080 if (IS_BROADWELL(dev)) {
4081 mutex_lock(&dev_priv->rps.hw_lock);
4082 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4083 mutex_unlock(&dev_priv->rps.hw_lock);
4084 /* Quoting Art Runyan: "its not safe to expect any particular
4085 * value in IPS_CTL bit 31 after enabling IPS through the
4086 * mailbox." Moreover, the mailbox may return a bogus state,
4087 * so we need to just enable it and continue on.
4088 */
4089 } else {
4090 I915_WRITE(IPS_CTL, IPS_ENABLE);
4091 /* The bit only becomes 1 in the next vblank, so this wait here
4092 * is essentially intel_wait_for_vblank. If we don't have this
4093 * and don't wait for vblanks until the end of crtc_enable, then
4094 * the HW state readout code will complain that the expected
4095 * IPS_CTL value is not the one we read. */
4096 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4097 DRM_ERROR("Timed out waiting for IPS enable\n");
4098 }
4099 }
4100
4101 void hsw_disable_ips(struct intel_crtc *crtc)
4102 {
4103 struct drm_device *dev = crtc->base.dev;
4104 struct drm_i915_private *dev_priv = dev->dev_private;
4105
4106 if (!crtc->config.ips_enabled)
4107 return;
4108
4109 assert_plane_enabled(dev_priv, crtc->plane);
4110 if (IS_BROADWELL(dev)) {
4111 mutex_lock(&dev_priv->rps.hw_lock);
4112 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4113 mutex_unlock(&dev_priv->rps.hw_lock);
4114 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4115 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4116 DRM_ERROR("Timed out waiting for IPS disable\n");
4117 } else {
4118 I915_WRITE(IPS_CTL, 0);
4119 POSTING_READ(IPS_CTL);
4120 }
4121
4122 /* We need to wait for a vblank before we can disable the plane. */
4123 intel_wait_for_vblank(dev, crtc->pipe);
4124 }
4125
4126 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4127 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4128 {
4129 struct drm_device *dev = crtc->dev;
4130 struct drm_i915_private *dev_priv = dev->dev_private;
4131 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4132 enum pipe pipe = intel_crtc->pipe;
4133 int palreg = PALETTE(pipe);
4134 int i;
4135 bool reenable_ips = false;
4136
4137 /* The clocks have to be on to load the palette. */
4138 if (!crtc->enabled || !intel_crtc->active)
4139 return;
4140
4141 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4142 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4143 assert_dsi_pll_enabled(dev_priv);
4144 else
4145 assert_pll_enabled(dev_priv, pipe);
4146 }
4147
4148 /* use legacy palette for Ironlake */
4149 if (!HAS_GMCH_DISPLAY(dev))
4150 palreg = LGC_PALETTE(pipe);
4151
4152 /* Workaround : Do not read or write the pipe palette/gamma data while
4153 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4154 */
4155 if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
4156 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4157 GAMMA_MODE_MODE_SPLIT)) {
4158 hsw_disable_ips(intel_crtc);
4159 reenable_ips = true;
4160 }
4161
4162 for (i = 0; i < 256; i++) {
4163 I915_WRITE(palreg + 4 * i,
4164 (intel_crtc->lut_r[i] << 16) |
4165 (intel_crtc->lut_g[i] << 8) |
4166 intel_crtc->lut_b[i]);
4167 }
4168
4169 if (reenable_ips)
4170 hsw_enable_ips(intel_crtc);
4171 }
4172
4173 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4174 {
4175 if (!enable && intel_crtc->overlay) {
4176 struct drm_device *dev = intel_crtc->base.dev;
4177 struct drm_i915_private *dev_priv = dev->dev_private;
4178
4179 mutex_lock(&dev->struct_mutex);
4180 dev_priv->mm.interruptible = false;
4181 (void) intel_overlay_switch_off(intel_crtc->overlay);
4182 dev_priv->mm.interruptible = true;
4183 mutex_unlock(&dev->struct_mutex);
4184 }
4185
4186 /* Let userspace switch the overlay on again. In most cases userspace
4187 * has to recompute where to put it anyway.
4188 */
4189 }
4190
4191 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4192 {
4193 struct drm_device *dev = crtc->dev;
4194 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4195 int pipe = intel_crtc->pipe;
4196
4197 intel_enable_primary_hw_plane(crtc->primary, crtc);
4198 intel_enable_planes(crtc);
4199 intel_crtc_update_cursor(crtc, true);
4200 intel_crtc_dpms_overlay(intel_crtc, true);
4201
4202 hsw_enable_ips(intel_crtc);
4203
4204 mutex_lock(&dev->struct_mutex);
4205 intel_update_fbc(dev);
4206 mutex_unlock(&dev->struct_mutex);
4207
4208 /*
4209 * FIXME: Once we grow proper nuclear flip support out of this we need
4210 * to compute the mask of flip planes precisely. For the time being
4211 * consider this a flip from a NULL plane.
4212 */
4213 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4214 }
4215
4216 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4217 {
4218 struct drm_device *dev = crtc->dev;
4219 struct drm_i915_private *dev_priv = dev->dev_private;
4220 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4221 int pipe = intel_crtc->pipe;
4222 int plane = intel_crtc->plane;
4223
4224 intel_crtc_wait_for_pending_flips(crtc);
4225
4226 if (dev_priv->fbc.plane == plane)
4227 intel_disable_fbc(dev);
4228
4229 hsw_disable_ips(intel_crtc);
4230
4231 intel_crtc_dpms_overlay(intel_crtc, false);
4232 intel_crtc_update_cursor(crtc, false);
4233 intel_disable_planes(crtc);
4234 intel_disable_primary_hw_plane(crtc->primary, crtc);
4235
4236 /*
4237 * FIXME: Once we grow proper nuclear flip support out of this we need
4238 * to compute the mask of flip planes precisely. For the time being
4239 * consider this a flip to a NULL plane.
4240 */
4241 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4242 }
4243
4244 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4245 {
4246 struct drm_device *dev = crtc->dev;
4247 struct drm_i915_private *dev_priv = dev->dev_private;
4248 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4249 struct intel_encoder *encoder;
4250 int pipe = intel_crtc->pipe;
4251
4252 WARN_ON(!crtc->enabled);
4253
4254 if (intel_crtc->active)
4255 return;
4256
4257 if (intel_crtc->config.has_pch_encoder)
4258 intel_prepare_shared_dpll(intel_crtc);
4259
4260 if (intel_crtc->config.has_dp_encoder)
4261 intel_dp_set_m_n(intel_crtc);
4262
4263 intel_set_pipe_timings(intel_crtc);
4264
4265 if (intel_crtc->config.has_pch_encoder) {
4266 intel_cpu_transcoder_set_m_n(intel_crtc,
4267 &intel_crtc->config.fdi_m_n, NULL);
4268 }
4269
4270 ironlake_set_pipeconf(crtc);
4271
4272 intel_crtc->active = true;
4273
4274 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4275 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4276
4277 for_each_encoder_on_crtc(dev, crtc, encoder)
4278 if (encoder->pre_enable)
4279 encoder->pre_enable(encoder);
4280
4281 if (intel_crtc->config.has_pch_encoder) {
4282 /* Note: FDI PLL enabling _must_ be done before we enable the
4283 * cpu pipes, hence this is separate from all the other fdi/pch
4284 * enabling. */
4285 ironlake_fdi_pll_enable(intel_crtc);
4286 } else {
4287 assert_fdi_tx_disabled(dev_priv, pipe);
4288 assert_fdi_rx_disabled(dev_priv, pipe);
4289 }
4290
4291 ironlake_pfit_enable(intel_crtc);
4292
4293 /*
4294 * On ILK+ LUT must be loaded before the pipe is running but with
4295 * clocks enabled
4296 */
4297 intel_crtc_load_lut(crtc);
4298
4299 intel_update_watermarks(crtc);
4300 intel_enable_pipe(intel_crtc);
4301
4302 if (intel_crtc->config.has_pch_encoder)
4303 ironlake_pch_enable(crtc);
4304
4305 for_each_encoder_on_crtc(dev, crtc, encoder)
4306 encoder->enable(encoder);
4307
4308 if (HAS_PCH_CPT(dev))
4309 cpt_verify_modeset(dev, intel_crtc->pipe);
4310
4311 assert_vblank_disabled(crtc);
4312 drm_crtc_vblank_on(crtc);
4313
4314 intel_crtc_enable_planes(crtc);
4315 }
4316
4317 /* IPS only exists on ULT machines and is tied to pipe A. */
4318 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4319 {
4320 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4321 }
4322
4323 /*
4324 * This implements the workaround described in the "notes" section of the mode
4325 * set sequence documentation. When going from no pipes or single pipe to
4326 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4327 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4328 */
4329 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4330 {
4331 struct drm_device *dev = crtc->base.dev;
4332 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4333
4334 /* We want to get the other_active_crtc only if there's only 1 other
4335 * active crtc. */
4336 for_each_intel_crtc(dev, crtc_it) {
4337 if (!crtc_it->active || crtc_it == crtc)
4338 continue;
4339
4340 if (other_active_crtc)
4341 return;
4342
4343 other_active_crtc = crtc_it;
4344 }
4345 if (!other_active_crtc)
4346 return;
4347
4348 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4349 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4350 }
4351
4352 static void haswell_crtc_enable(struct drm_crtc *crtc)
4353 {
4354 struct drm_device *dev = crtc->dev;
4355 struct drm_i915_private *dev_priv = dev->dev_private;
4356 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4357 struct intel_encoder *encoder;
4358 int pipe = intel_crtc->pipe;
4359
4360 WARN_ON(!crtc->enabled);
4361
4362 if (intel_crtc->active)
4363 return;
4364
4365 if (intel_crtc_to_shared_dpll(intel_crtc))
4366 intel_enable_shared_dpll(intel_crtc);
4367
4368 if (intel_crtc->config.has_dp_encoder)
4369 intel_dp_set_m_n(intel_crtc);
4370
4371 intel_set_pipe_timings(intel_crtc);
4372
4373 if (intel_crtc->config.cpu_transcoder != TRANSCODER_EDP) {
4374 I915_WRITE(PIPE_MULT(intel_crtc->config.cpu_transcoder),
4375 intel_crtc->config.pixel_multiplier - 1);
4376 }
4377
4378 if (intel_crtc->config.has_pch_encoder) {
4379 intel_cpu_transcoder_set_m_n(intel_crtc,
4380 &intel_crtc->config.fdi_m_n, NULL);
4381 }
4382
4383 haswell_set_pipeconf(crtc);
4384
4385 intel_set_pipe_csc(crtc);
4386
4387 intel_crtc->active = true;
4388
4389 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4390 for_each_encoder_on_crtc(dev, crtc, encoder)
4391 if (encoder->pre_enable)
4392 encoder->pre_enable(encoder);
4393
4394 if (intel_crtc->config.has_pch_encoder) {
4395 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4396 true);
4397 dev_priv->display.fdi_link_train(crtc);
4398 }
4399
4400 intel_ddi_enable_pipe_clock(intel_crtc);
4401
4402 if (IS_SKYLAKE(dev))
4403 skylake_pfit_enable(intel_crtc);
4404 else
4405 ironlake_pfit_enable(intel_crtc);
4406
4407 /*
4408 * On ILK+ LUT must be loaded before the pipe is running but with
4409 * clocks enabled
4410 */
4411 intel_crtc_load_lut(crtc);
4412
4413 intel_ddi_set_pipe_settings(crtc);
4414 intel_ddi_enable_transcoder_func(crtc);
4415
4416 intel_update_watermarks(crtc);
4417 intel_enable_pipe(intel_crtc);
4418
4419 if (intel_crtc->config.has_pch_encoder)
4420 lpt_pch_enable(crtc);
4421
4422 if (intel_crtc->config.dp_encoder_is_mst)
4423 intel_ddi_set_vc_payload_alloc(crtc, true);
4424
4425 for_each_encoder_on_crtc(dev, crtc, encoder) {
4426 encoder->enable(encoder);
4427 intel_opregion_notify_encoder(encoder, true);
4428 }
4429
4430 assert_vblank_disabled(crtc);
4431 drm_crtc_vblank_on(crtc);
4432
4433 /* If we change the relative order between pipe/planes enabling, we need
4434 * to change the workaround. */
4435 haswell_mode_set_planes_workaround(intel_crtc);
4436 intel_crtc_enable_planes(crtc);
4437 }
4438
4439 static void skylake_pfit_disable(struct intel_crtc *crtc)
4440 {
4441 struct drm_device *dev = crtc->base.dev;
4442 struct drm_i915_private *dev_priv = dev->dev_private;
4443 int pipe = crtc->pipe;
4444
4445 /* To avoid upsetting the power well on haswell only disable the pfit if
4446 * it's in use. The hw state code will make sure we get this right. */
4447 if (crtc->config.pch_pfit.enabled) {
4448 I915_WRITE(PS_CTL(pipe), 0);
4449 I915_WRITE(PS_WIN_POS(pipe), 0);
4450 I915_WRITE(PS_WIN_SZ(pipe), 0);
4451 }
4452 }
4453
4454 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4455 {
4456 struct drm_device *dev = crtc->base.dev;
4457 struct drm_i915_private *dev_priv = dev->dev_private;
4458 int pipe = crtc->pipe;
4459
4460 /* To avoid upsetting the power well on haswell only disable the pfit if
4461 * it's in use. The hw state code will make sure we get this right. */
4462 if (crtc->config.pch_pfit.enabled) {
4463 I915_WRITE(PF_CTL(pipe), 0);
4464 I915_WRITE(PF_WIN_POS(pipe), 0);
4465 I915_WRITE(PF_WIN_SZ(pipe), 0);
4466 }
4467 }
4468
4469 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4470 {
4471 struct drm_device *dev = crtc->dev;
4472 struct drm_i915_private *dev_priv = dev->dev_private;
4473 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4474 struct intel_encoder *encoder;
4475 int pipe = intel_crtc->pipe;
4476 u32 reg, temp;
4477
4478 if (!intel_crtc->active)
4479 return;
4480
4481 intel_crtc_disable_planes(crtc);
4482
4483 drm_crtc_vblank_off(crtc);
4484 assert_vblank_disabled(crtc);
4485
4486 for_each_encoder_on_crtc(dev, crtc, encoder)
4487 encoder->disable(encoder);
4488
4489 if (intel_crtc->config.has_pch_encoder)
4490 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4491
4492 intel_disable_pipe(intel_crtc);
4493
4494 ironlake_pfit_disable(intel_crtc);
4495
4496 for_each_encoder_on_crtc(dev, crtc, encoder)
4497 if (encoder->post_disable)
4498 encoder->post_disable(encoder);
4499
4500 if (intel_crtc->config.has_pch_encoder) {
4501 ironlake_fdi_disable(crtc);
4502
4503 ironlake_disable_pch_transcoder(dev_priv, pipe);
4504 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4505
4506 if (HAS_PCH_CPT(dev)) {
4507 /* disable TRANS_DP_CTL */
4508 reg = TRANS_DP_CTL(pipe);
4509 temp = I915_READ(reg);
4510 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4511 TRANS_DP_PORT_SEL_MASK);
4512 temp |= TRANS_DP_PORT_SEL_NONE;
4513 I915_WRITE(reg, temp);
4514
4515 /* disable DPLL_SEL */
4516 temp = I915_READ(PCH_DPLL_SEL);
4517 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4518 I915_WRITE(PCH_DPLL_SEL, temp);
4519 }
4520
4521 /* disable PCH DPLL */
4522 intel_disable_shared_dpll(intel_crtc);
4523
4524 ironlake_fdi_pll_disable(intel_crtc);
4525 }
4526
4527 intel_crtc->active = false;
4528 intel_update_watermarks(crtc);
4529
4530 mutex_lock(&dev->struct_mutex);
4531 intel_update_fbc(dev);
4532 mutex_unlock(&dev->struct_mutex);
4533 }
4534
4535 static void haswell_crtc_disable(struct drm_crtc *crtc)
4536 {
4537 struct drm_device *dev = crtc->dev;
4538 struct drm_i915_private *dev_priv = dev->dev_private;
4539 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4540 struct intel_encoder *encoder;
4541 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4542
4543 if (!intel_crtc->active)
4544 return;
4545
4546 intel_crtc_disable_planes(crtc);
4547
4548 drm_crtc_vblank_off(crtc);
4549 assert_vblank_disabled(crtc);
4550
4551 for_each_encoder_on_crtc(dev, crtc, encoder) {
4552 intel_opregion_notify_encoder(encoder, false);
4553 encoder->disable(encoder);
4554 }
4555
4556 if (intel_crtc->config.has_pch_encoder)
4557 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4558 false);
4559 intel_disable_pipe(intel_crtc);
4560
4561 if (intel_crtc->config.dp_encoder_is_mst)
4562 intel_ddi_set_vc_payload_alloc(crtc, false);
4563
4564 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4565
4566 if (IS_SKYLAKE(dev))
4567 skylake_pfit_disable(intel_crtc);
4568 else
4569 ironlake_pfit_disable(intel_crtc);
4570
4571 intel_ddi_disable_pipe_clock(intel_crtc);
4572
4573 if (intel_crtc->config.has_pch_encoder) {
4574 lpt_disable_pch_transcoder(dev_priv);
4575 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4576 true);
4577 intel_ddi_fdi_disable(crtc);
4578 }
4579
4580 for_each_encoder_on_crtc(dev, crtc, encoder)
4581 if (encoder->post_disable)
4582 encoder->post_disable(encoder);
4583
4584 intel_crtc->active = false;
4585 intel_update_watermarks(crtc);
4586
4587 mutex_lock(&dev->struct_mutex);
4588 intel_update_fbc(dev);
4589 mutex_unlock(&dev->struct_mutex);
4590
4591 if (intel_crtc_to_shared_dpll(intel_crtc))
4592 intel_disable_shared_dpll(intel_crtc);
4593 }
4594
4595 static void ironlake_crtc_off(struct drm_crtc *crtc)
4596 {
4597 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4598 intel_put_shared_dpll(intel_crtc);
4599 }
4600
4601
4602 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4603 {
4604 struct drm_device *dev = crtc->base.dev;
4605 struct drm_i915_private *dev_priv = dev->dev_private;
4606 struct intel_crtc_config *pipe_config = &crtc->config;
4607
4608 if (!crtc->config.gmch_pfit.control)
4609 return;
4610
4611 /*
4612 * The panel fitter should only be adjusted whilst the pipe is disabled,
4613 * according to register description and PRM.
4614 */
4615 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4616 assert_pipe_disabled(dev_priv, crtc->pipe);
4617
4618 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4619 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4620
4621 /* Border color in case we don't scale up to the full screen. Black by
4622 * default, change to something else for debugging. */
4623 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4624 }
4625
4626 static enum intel_display_power_domain port_to_power_domain(enum port port)
4627 {
4628 switch (port) {
4629 case PORT_A:
4630 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4631 case PORT_B:
4632 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4633 case PORT_C:
4634 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4635 case PORT_D:
4636 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4637 default:
4638 WARN_ON_ONCE(1);
4639 return POWER_DOMAIN_PORT_OTHER;
4640 }
4641 }
4642
4643 #define for_each_power_domain(domain, mask) \
4644 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4645 if ((1 << (domain)) & (mask))
4646
4647 enum intel_display_power_domain
4648 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4649 {
4650 struct drm_device *dev = intel_encoder->base.dev;
4651 struct intel_digital_port *intel_dig_port;
4652
4653 switch (intel_encoder->type) {
4654 case INTEL_OUTPUT_UNKNOWN:
4655 /* Only DDI platforms should ever use this output type */
4656 WARN_ON_ONCE(!HAS_DDI(dev));
4657 case INTEL_OUTPUT_DISPLAYPORT:
4658 case INTEL_OUTPUT_HDMI:
4659 case INTEL_OUTPUT_EDP:
4660 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4661 return port_to_power_domain(intel_dig_port->port);
4662 case INTEL_OUTPUT_DP_MST:
4663 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4664 return port_to_power_domain(intel_dig_port->port);
4665 case INTEL_OUTPUT_ANALOG:
4666 return POWER_DOMAIN_PORT_CRT;
4667 case INTEL_OUTPUT_DSI:
4668 return POWER_DOMAIN_PORT_DSI;
4669 default:
4670 return POWER_DOMAIN_PORT_OTHER;
4671 }
4672 }
4673
4674 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4675 {
4676 struct drm_device *dev = crtc->dev;
4677 struct intel_encoder *intel_encoder;
4678 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4679 enum pipe pipe = intel_crtc->pipe;
4680 unsigned long mask;
4681 enum transcoder transcoder;
4682
4683 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4684
4685 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4686 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4687 if (intel_crtc->config.pch_pfit.enabled ||
4688 intel_crtc->config.pch_pfit.force_thru)
4689 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4690
4691 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4692 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4693
4694 return mask;
4695 }
4696
4697 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4698 {
4699 struct drm_i915_private *dev_priv = dev->dev_private;
4700 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4701 struct intel_crtc *crtc;
4702
4703 /*
4704 * First get all needed power domains, then put all unneeded, to avoid
4705 * any unnecessary toggling of the power wells.
4706 */
4707 for_each_intel_crtc(dev, crtc) {
4708 enum intel_display_power_domain domain;
4709
4710 if (!crtc->base.enabled)
4711 continue;
4712
4713 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4714
4715 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4716 intel_display_power_get(dev_priv, domain);
4717 }
4718
4719 if (dev_priv->display.modeset_global_resources)
4720 dev_priv->display.modeset_global_resources(dev);
4721
4722 for_each_intel_crtc(dev, crtc) {
4723 enum intel_display_power_domain domain;
4724
4725 for_each_power_domain(domain, crtc->enabled_power_domains)
4726 intel_display_power_put(dev_priv, domain);
4727
4728 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4729 }
4730
4731 intel_display_set_init_power(dev_priv, false);
4732 }
4733
4734 /* returns HPLL frequency in kHz */
4735 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4736 {
4737 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4738
4739 /* Obtain SKU information */
4740 mutex_lock(&dev_priv->dpio_lock);
4741 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4742 CCK_FUSE_HPLL_FREQ_MASK;
4743 mutex_unlock(&dev_priv->dpio_lock);
4744
4745 return vco_freq[hpll_freq] * 1000;
4746 }
4747
4748 static void vlv_update_cdclk(struct drm_device *dev)
4749 {
4750 struct drm_i915_private *dev_priv = dev->dev_private;
4751
4752 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4753 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4754 dev_priv->vlv_cdclk_freq);
4755
4756 /*
4757 * Program the gmbus_freq based on the cdclk frequency.
4758 * BSpec erroneously claims we should aim for 4MHz, but
4759 * in fact 1MHz is the correct frequency.
4760 */
4761 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
4762 }
4763
4764 /* Adjust CDclk dividers to allow high res or save power if possible */
4765 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4766 {
4767 struct drm_i915_private *dev_priv = dev->dev_private;
4768 u32 val, cmd;
4769
4770 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4771
4772 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4773 cmd = 2;
4774 else if (cdclk == 266667)
4775 cmd = 1;
4776 else
4777 cmd = 0;
4778
4779 mutex_lock(&dev_priv->rps.hw_lock);
4780 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4781 val &= ~DSPFREQGUAR_MASK;
4782 val |= (cmd << DSPFREQGUAR_SHIFT);
4783 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4784 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4785 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4786 50)) {
4787 DRM_ERROR("timed out waiting for CDclk change\n");
4788 }
4789 mutex_unlock(&dev_priv->rps.hw_lock);
4790
4791 if (cdclk == 400000) {
4792 u32 divider;
4793
4794 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
4795
4796 mutex_lock(&dev_priv->dpio_lock);
4797 /* adjust cdclk divider */
4798 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4799 val &= ~DISPLAY_FREQUENCY_VALUES;
4800 val |= divider;
4801 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4802
4803 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4804 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4805 50))
4806 DRM_ERROR("timed out waiting for CDclk change\n");
4807 mutex_unlock(&dev_priv->dpio_lock);
4808 }
4809
4810 mutex_lock(&dev_priv->dpio_lock);
4811 /* adjust self-refresh exit latency value */
4812 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4813 val &= ~0x7f;
4814
4815 /*
4816 * For high bandwidth configs, we set a higher latency in the bunit
4817 * so that the core display fetch happens in time to avoid underruns.
4818 */
4819 if (cdclk == 400000)
4820 val |= 4500 / 250; /* 4.5 usec */
4821 else
4822 val |= 3000 / 250; /* 3.0 usec */
4823 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4824 mutex_unlock(&dev_priv->dpio_lock);
4825
4826 vlv_update_cdclk(dev);
4827 }
4828
4829 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4830 {
4831 struct drm_i915_private *dev_priv = dev->dev_private;
4832 u32 val, cmd;
4833
4834 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4835
4836 switch (cdclk) {
4837 case 400000:
4838 cmd = 3;
4839 break;
4840 case 333333:
4841 case 320000:
4842 cmd = 2;
4843 break;
4844 case 266667:
4845 cmd = 1;
4846 break;
4847 case 200000:
4848 cmd = 0;
4849 break;
4850 default:
4851 WARN_ON(1);
4852 return;
4853 }
4854
4855 mutex_lock(&dev_priv->rps.hw_lock);
4856 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4857 val &= ~DSPFREQGUAR_MASK_CHV;
4858 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4859 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4860 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4861 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4862 50)) {
4863 DRM_ERROR("timed out waiting for CDclk change\n");
4864 }
4865 mutex_unlock(&dev_priv->rps.hw_lock);
4866
4867 vlv_update_cdclk(dev);
4868 }
4869
4870 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4871 int max_pixclk)
4872 {
4873 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
4874
4875 /* FIXME: Punit isn't quite ready yet */
4876 if (IS_CHERRYVIEW(dev_priv->dev))
4877 return 400000;
4878
4879 /*
4880 * Really only a few cases to deal with, as only 4 CDclks are supported:
4881 * 200MHz
4882 * 267MHz
4883 * 320/333MHz (depends on HPLL freq)
4884 * 400MHz
4885 * So we check to see whether we're above 90% of the lower bin and
4886 * adjust if needed.
4887 *
4888 * We seem to get an unstable or solid color picture at 200MHz.
4889 * Not sure what's wrong. For now use 200MHz only when all pipes
4890 * are off.
4891 */
4892 if (max_pixclk > freq_320*9/10)
4893 return 400000;
4894 else if (max_pixclk > 266667*9/10)
4895 return freq_320;
4896 else if (max_pixclk > 0)
4897 return 266667;
4898 else
4899 return 200000;
4900 }
4901
4902 /* compute the max pixel clock for new configuration */
4903 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4904 {
4905 struct drm_device *dev = dev_priv->dev;
4906 struct intel_crtc *intel_crtc;
4907 int max_pixclk = 0;
4908
4909 for_each_intel_crtc(dev, intel_crtc) {
4910 if (intel_crtc->new_enabled)
4911 max_pixclk = max(max_pixclk,
4912 intel_crtc->new_config->adjusted_mode.crtc_clock);
4913 }
4914
4915 return max_pixclk;
4916 }
4917
4918 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4919 unsigned *prepare_pipes)
4920 {
4921 struct drm_i915_private *dev_priv = dev->dev_private;
4922 struct intel_crtc *intel_crtc;
4923 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4924
4925 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4926 dev_priv->vlv_cdclk_freq)
4927 return;
4928
4929 /* disable/enable all currently active pipes while we change cdclk */
4930 for_each_intel_crtc(dev, intel_crtc)
4931 if (intel_crtc->base.enabled)
4932 *prepare_pipes |= (1 << intel_crtc->pipe);
4933 }
4934
4935 static void valleyview_modeset_global_resources(struct drm_device *dev)
4936 {
4937 struct drm_i915_private *dev_priv = dev->dev_private;
4938 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4939 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4940
4941 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
4942 if (IS_CHERRYVIEW(dev))
4943 cherryview_set_cdclk(dev, req_cdclk);
4944 else
4945 valleyview_set_cdclk(dev, req_cdclk);
4946 }
4947 }
4948
4949 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4950 {
4951 struct drm_device *dev = crtc->dev;
4952 struct drm_i915_private *dev_priv = to_i915(dev);
4953 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4954 struct intel_encoder *encoder;
4955 int pipe = intel_crtc->pipe;
4956 bool is_dsi;
4957
4958 WARN_ON(!crtc->enabled);
4959
4960 if (intel_crtc->active)
4961 return;
4962
4963 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
4964
4965 if (!is_dsi) {
4966 if (IS_CHERRYVIEW(dev))
4967 chv_prepare_pll(intel_crtc, &intel_crtc->config);
4968 else
4969 vlv_prepare_pll(intel_crtc, &intel_crtc->config);
4970 }
4971
4972 if (intel_crtc->config.has_dp_encoder)
4973 intel_dp_set_m_n(intel_crtc);
4974
4975 intel_set_pipe_timings(intel_crtc);
4976
4977 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
4978 struct drm_i915_private *dev_priv = dev->dev_private;
4979
4980 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
4981 I915_WRITE(CHV_CANVAS(pipe), 0);
4982 }
4983
4984 i9xx_set_pipeconf(intel_crtc);
4985
4986 intel_crtc->active = true;
4987
4988 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4989
4990 for_each_encoder_on_crtc(dev, crtc, encoder)
4991 if (encoder->pre_pll_enable)
4992 encoder->pre_pll_enable(encoder);
4993
4994 if (!is_dsi) {
4995 if (IS_CHERRYVIEW(dev))
4996 chv_enable_pll(intel_crtc, &intel_crtc->config);
4997 else
4998 vlv_enable_pll(intel_crtc, &intel_crtc->config);
4999 }
5000
5001 for_each_encoder_on_crtc(dev, crtc, encoder)
5002 if (encoder->pre_enable)
5003 encoder->pre_enable(encoder);
5004
5005 i9xx_pfit_enable(intel_crtc);
5006
5007 intel_crtc_load_lut(crtc);
5008
5009 intel_update_watermarks(crtc);
5010 intel_enable_pipe(intel_crtc);
5011
5012 for_each_encoder_on_crtc(dev, crtc, encoder)
5013 encoder->enable(encoder);
5014
5015 assert_vblank_disabled(crtc);
5016 drm_crtc_vblank_on(crtc);
5017
5018 intel_crtc_enable_planes(crtc);
5019
5020 /* Underruns don't raise interrupts, so check manually. */
5021 i9xx_check_fifo_underruns(dev_priv);
5022 }
5023
5024 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5025 {
5026 struct drm_device *dev = crtc->base.dev;
5027 struct drm_i915_private *dev_priv = dev->dev_private;
5028
5029 I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
5030 I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
5031 }
5032
5033 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5034 {
5035 struct drm_device *dev = crtc->dev;
5036 struct drm_i915_private *dev_priv = to_i915(dev);
5037 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5038 struct intel_encoder *encoder;
5039 int pipe = intel_crtc->pipe;
5040
5041 WARN_ON(!crtc->enabled);
5042
5043 if (intel_crtc->active)
5044 return;
5045
5046 i9xx_set_pll_dividers(intel_crtc);
5047
5048 if (intel_crtc->config.has_dp_encoder)
5049 intel_dp_set_m_n(intel_crtc);
5050
5051 intel_set_pipe_timings(intel_crtc);
5052
5053 i9xx_set_pipeconf(intel_crtc);
5054
5055 intel_crtc->active = true;
5056
5057 if (!IS_GEN2(dev))
5058 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5059
5060 for_each_encoder_on_crtc(dev, crtc, encoder)
5061 if (encoder->pre_enable)
5062 encoder->pre_enable(encoder);
5063
5064 i9xx_enable_pll(intel_crtc);
5065
5066 i9xx_pfit_enable(intel_crtc);
5067
5068 intel_crtc_load_lut(crtc);
5069
5070 intel_update_watermarks(crtc);
5071 intel_enable_pipe(intel_crtc);
5072
5073 for_each_encoder_on_crtc(dev, crtc, encoder)
5074 encoder->enable(encoder);
5075
5076 assert_vblank_disabled(crtc);
5077 drm_crtc_vblank_on(crtc);
5078
5079 intel_crtc_enable_planes(crtc);
5080
5081 /*
5082 * Gen2 reports pipe underruns whenever all planes are disabled.
5083 * So don't enable underrun reporting before at least some planes
5084 * are enabled.
5085 * FIXME: Need to fix the logic to work when we turn off all planes
5086 * but leave the pipe running.
5087 */
5088 if (IS_GEN2(dev))
5089 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5090
5091 /* Underruns don't raise interrupts, so check manually. */
5092 i9xx_check_fifo_underruns(dev_priv);
5093 }
5094
5095 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5096 {
5097 struct drm_device *dev = crtc->base.dev;
5098 struct drm_i915_private *dev_priv = dev->dev_private;
5099
5100 if (!crtc->config.gmch_pfit.control)
5101 return;
5102
5103 assert_pipe_disabled(dev_priv, crtc->pipe);
5104
5105 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5106 I915_READ(PFIT_CONTROL));
5107 I915_WRITE(PFIT_CONTROL, 0);
5108 }
5109
5110 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5111 {
5112 struct drm_device *dev = crtc->dev;
5113 struct drm_i915_private *dev_priv = dev->dev_private;
5114 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5115 struct intel_encoder *encoder;
5116 int pipe = intel_crtc->pipe;
5117
5118 if (!intel_crtc->active)
5119 return;
5120
5121 /*
5122 * Gen2 reports pipe underruns whenever all planes are disabled.
5123 * So diasble underrun reporting before all the planes get disabled.
5124 * FIXME: Need to fix the logic to work when we turn off all planes
5125 * but leave the pipe running.
5126 */
5127 if (IS_GEN2(dev))
5128 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5129
5130 /*
5131 * Vblank time updates from the shadow to live plane control register
5132 * are blocked if the memory self-refresh mode is active at that
5133 * moment. So to make sure the plane gets truly disabled, disable
5134 * first the self-refresh mode. The self-refresh enable bit in turn
5135 * will be checked/applied by the HW only at the next frame start
5136 * event which is after the vblank start event, so we need to have a
5137 * wait-for-vblank between disabling the plane and the pipe.
5138 */
5139 intel_set_memory_cxsr(dev_priv, false);
5140 intel_crtc_disable_planes(crtc);
5141
5142 /*
5143 * On gen2 planes are double buffered but the pipe isn't, so we must
5144 * wait for planes to fully turn off before disabling the pipe.
5145 * We also need to wait on all gmch platforms because of the
5146 * self-refresh mode constraint explained above.
5147 */
5148 intel_wait_for_vblank(dev, pipe);
5149
5150 drm_crtc_vblank_off(crtc);
5151 assert_vblank_disabled(crtc);
5152
5153 for_each_encoder_on_crtc(dev, crtc, encoder)
5154 encoder->disable(encoder);
5155
5156 intel_disable_pipe(intel_crtc);
5157
5158 i9xx_pfit_disable(intel_crtc);
5159
5160 for_each_encoder_on_crtc(dev, crtc, encoder)
5161 if (encoder->post_disable)
5162 encoder->post_disable(encoder);
5163
5164 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5165 if (IS_CHERRYVIEW(dev))
5166 chv_disable_pll(dev_priv, pipe);
5167 else if (IS_VALLEYVIEW(dev))
5168 vlv_disable_pll(dev_priv, pipe);
5169 else
5170 i9xx_disable_pll(intel_crtc);
5171 }
5172
5173 if (!IS_GEN2(dev))
5174 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5175
5176 intel_crtc->active = false;
5177 intel_update_watermarks(crtc);
5178
5179 mutex_lock(&dev->struct_mutex);
5180 intel_update_fbc(dev);
5181 mutex_unlock(&dev->struct_mutex);
5182 }
5183
5184 static void i9xx_crtc_off(struct drm_crtc *crtc)
5185 {
5186 }
5187
5188 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
5189 bool enabled)
5190 {
5191 struct drm_device *dev = crtc->dev;
5192 struct drm_i915_master_private *master_priv;
5193 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5194 int pipe = intel_crtc->pipe;
5195
5196 if (!dev->primary->master)
5197 return;
5198
5199 master_priv = dev->primary->master->driver_priv;
5200 if (!master_priv->sarea_priv)
5201 return;
5202
5203 switch (pipe) {
5204 case 0:
5205 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
5206 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
5207 break;
5208 case 1:
5209 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
5210 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
5211 break;
5212 default:
5213 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
5214 break;
5215 }
5216 }
5217
5218 /* Master function to enable/disable CRTC and corresponding power wells */
5219 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5220 {
5221 struct drm_device *dev = crtc->dev;
5222 struct drm_i915_private *dev_priv = dev->dev_private;
5223 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5224 enum intel_display_power_domain domain;
5225 unsigned long domains;
5226
5227 if (enable) {
5228 if (!intel_crtc->active) {
5229 domains = get_crtc_power_domains(crtc);
5230 for_each_power_domain(domain, domains)
5231 intel_display_power_get(dev_priv, domain);
5232 intel_crtc->enabled_power_domains = domains;
5233
5234 dev_priv->display.crtc_enable(crtc);
5235 }
5236 } else {
5237 if (intel_crtc->active) {
5238 dev_priv->display.crtc_disable(crtc);
5239
5240 domains = intel_crtc->enabled_power_domains;
5241 for_each_power_domain(domain, domains)
5242 intel_display_power_put(dev_priv, domain);
5243 intel_crtc->enabled_power_domains = 0;
5244 }
5245 }
5246 }
5247
5248 /**
5249 * Sets the power management mode of the pipe and plane.
5250 */
5251 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5252 {
5253 struct drm_device *dev = crtc->dev;
5254 struct intel_encoder *intel_encoder;
5255 bool enable = false;
5256
5257 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5258 enable |= intel_encoder->connectors_active;
5259
5260 intel_crtc_control(crtc, enable);
5261
5262 intel_crtc_update_sarea(crtc, enable);
5263 }
5264
5265 static void intel_crtc_disable(struct drm_crtc *crtc)
5266 {
5267 struct drm_device *dev = crtc->dev;
5268 struct drm_connector *connector;
5269 struct drm_i915_private *dev_priv = dev->dev_private;
5270 struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
5271 enum pipe pipe = to_intel_crtc(crtc)->pipe;
5272
5273 /* crtc should still be enabled when we disable it. */
5274 WARN_ON(!crtc->enabled);
5275
5276 dev_priv->display.crtc_disable(crtc);
5277 intel_crtc_update_sarea(crtc, false);
5278 dev_priv->display.off(crtc);
5279
5280 if (crtc->primary->fb) {
5281 mutex_lock(&dev->struct_mutex);
5282 intel_unpin_fb_obj(old_obj);
5283 i915_gem_track_fb(old_obj, NULL,
5284 INTEL_FRONTBUFFER_PRIMARY(pipe));
5285 mutex_unlock(&dev->struct_mutex);
5286 crtc->primary->fb = NULL;
5287 }
5288
5289 /* Update computed state. */
5290 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5291 if (!connector->encoder || !connector->encoder->crtc)
5292 continue;
5293
5294 if (connector->encoder->crtc != crtc)
5295 continue;
5296
5297 connector->dpms = DRM_MODE_DPMS_OFF;
5298 to_intel_encoder(connector->encoder)->connectors_active = false;
5299 }
5300 }
5301
5302 void intel_encoder_destroy(struct drm_encoder *encoder)
5303 {
5304 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5305
5306 drm_encoder_cleanup(encoder);
5307 kfree(intel_encoder);
5308 }
5309
5310 /* Simple dpms helper for encoders with just one connector, no cloning and only
5311 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5312 * state of the entire output pipe. */
5313 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5314 {
5315 if (mode == DRM_MODE_DPMS_ON) {
5316 encoder->connectors_active = true;
5317
5318 intel_crtc_update_dpms(encoder->base.crtc);
5319 } else {
5320 encoder->connectors_active = false;
5321
5322 intel_crtc_update_dpms(encoder->base.crtc);
5323 }
5324 }
5325
5326 /* Cross check the actual hw state with our own modeset state tracking (and it's
5327 * internal consistency). */
5328 static void intel_connector_check_state(struct intel_connector *connector)
5329 {
5330 if (connector->get_hw_state(connector)) {
5331 struct intel_encoder *encoder = connector->encoder;
5332 struct drm_crtc *crtc;
5333 bool encoder_enabled;
5334 enum pipe pipe;
5335
5336 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5337 connector->base.base.id,
5338 connector->base.name);
5339
5340 /* there is no real hw state for MST connectors */
5341 if (connector->mst_port)
5342 return;
5343
5344 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5345 "wrong connector dpms state\n");
5346 WARN(connector->base.encoder != &encoder->base,
5347 "active connector not linked to encoder\n");
5348
5349 if (encoder) {
5350 WARN(!encoder->connectors_active,
5351 "encoder->connectors_active not set\n");
5352
5353 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5354 WARN(!encoder_enabled, "encoder not enabled\n");
5355 if (WARN_ON(!encoder->base.crtc))
5356 return;
5357
5358 crtc = encoder->base.crtc;
5359
5360 WARN(!crtc->enabled, "crtc not enabled\n");
5361 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5362 WARN(pipe != to_intel_crtc(crtc)->pipe,
5363 "encoder active on the wrong pipe\n");
5364 }
5365 }
5366 }
5367
5368 /* Even simpler default implementation, if there's really no special case to
5369 * consider. */
5370 void intel_connector_dpms(struct drm_connector *connector, int mode)
5371 {
5372 /* All the simple cases only support two dpms states. */
5373 if (mode != DRM_MODE_DPMS_ON)
5374 mode = DRM_MODE_DPMS_OFF;
5375
5376 if (mode == connector->dpms)
5377 return;
5378
5379 connector->dpms = mode;
5380
5381 /* Only need to change hw state when actually enabled */
5382 if (connector->encoder)
5383 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5384
5385 intel_modeset_check_state(connector->dev);
5386 }
5387
5388 /* Simple connector->get_hw_state implementation for encoders that support only
5389 * one connector and no cloning and hence the encoder state determines the state
5390 * of the connector. */
5391 bool intel_connector_get_hw_state(struct intel_connector *connector)
5392 {
5393 enum pipe pipe = 0;
5394 struct intel_encoder *encoder = connector->encoder;
5395
5396 return encoder->get_hw_state(encoder, &pipe);
5397 }
5398
5399 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5400 struct intel_crtc_config *pipe_config)
5401 {
5402 struct drm_i915_private *dev_priv = dev->dev_private;
5403 struct intel_crtc *pipe_B_crtc =
5404 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5405
5406 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5407 pipe_name(pipe), pipe_config->fdi_lanes);
5408 if (pipe_config->fdi_lanes > 4) {
5409 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5410 pipe_name(pipe), pipe_config->fdi_lanes);
5411 return false;
5412 }
5413
5414 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5415 if (pipe_config->fdi_lanes > 2) {
5416 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5417 pipe_config->fdi_lanes);
5418 return false;
5419 } else {
5420 return true;
5421 }
5422 }
5423
5424 if (INTEL_INFO(dev)->num_pipes == 2)
5425 return true;
5426
5427 /* Ivybridge 3 pipe is really complicated */
5428 switch (pipe) {
5429 case PIPE_A:
5430 return true;
5431 case PIPE_B:
5432 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5433 pipe_config->fdi_lanes > 2) {
5434 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5435 pipe_name(pipe), pipe_config->fdi_lanes);
5436 return false;
5437 }
5438 return true;
5439 case PIPE_C:
5440 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5441 pipe_B_crtc->config.fdi_lanes <= 2) {
5442 if (pipe_config->fdi_lanes > 2) {
5443 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5444 pipe_name(pipe), pipe_config->fdi_lanes);
5445 return false;
5446 }
5447 } else {
5448 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5449 return false;
5450 }
5451 return true;
5452 default:
5453 BUG();
5454 }
5455 }
5456
5457 #define RETRY 1
5458 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5459 struct intel_crtc_config *pipe_config)
5460 {
5461 struct drm_device *dev = intel_crtc->base.dev;
5462 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5463 int lane, link_bw, fdi_dotclock;
5464 bool setup_ok, needs_recompute = false;
5465
5466 retry:
5467 /* FDI is a binary signal running at ~2.7GHz, encoding
5468 * each output octet as 10 bits. The actual frequency
5469 * is stored as a divider into a 100MHz clock, and the
5470 * mode pixel clock is stored in units of 1KHz.
5471 * Hence the bw of each lane in terms of the mode signal
5472 * is:
5473 */
5474 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5475
5476 fdi_dotclock = adjusted_mode->crtc_clock;
5477
5478 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5479 pipe_config->pipe_bpp);
5480
5481 pipe_config->fdi_lanes = lane;
5482
5483 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5484 link_bw, &pipe_config->fdi_m_n);
5485
5486 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5487 intel_crtc->pipe, pipe_config);
5488 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5489 pipe_config->pipe_bpp -= 2*3;
5490 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5491 pipe_config->pipe_bpp);
5492 needs_recompute = true;
5493 pipe_config->bw_constrained = true;
5494
5495 goto retry;
5496 }
5497
5498 if (needs_recompute)
5499 return RETRY;
5500
5501 return setup_ok ? 0 : -EINVAL;
5502 }
5503
5504 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5505 struct intel_crtc_config *pipe_config)
5506 {
5507 pipe_config->ips_enabled = i915.enable_ips &&
5508 hsw_crtc_supports_ips(crtc) &&
5509 pipe_config->pipe_bpp <= 24;
5510 }
5511
5512 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5513 struct intel_crtc_config *pipe_config)
5514 {
5515 struct drm_device *dev = crtc->base.dev;
5516 struct drm_i915_private *dev_priv = dev->dev_private;
5517 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5518
5519 /* FIXME should check pixel clock limits on all platforms */
5520 if (INTEL_INFO(dev)->gen < 4) {
5521 int clock_limit =
5522 dev_priv->display.get_display_clock_speed(dev);
5523
5524 /*
5525 * Enable pixel doubling when the dot clock
5526 * is > 90% of the (display) core speed.
5527 *
5528 * GDG double wide on either pipe,
5529 * otherwise pipe A only.
5530 */
5531 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5532 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5533 clock_limit *= 2;
5534 pipe_config->double_wide = true;
5535 }
5536
5537 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5538 return -EINVAL;
5539 }
5540
5541 /*
5542 * Pipe horizontal size must be even in:
5543 * - DVO ganged mode
5544 * - LVDS dual channel mode
5545 * - Double wide pipe
5546 */
5547 if ((intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5548 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5549 pipe_config->pipe_src_w &= ~1;
5550
5551 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5552 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5553 */
5554 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5555 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5556 return -EINVAL;
5557
5558 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5559 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5560 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5561 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5562 * for lvds. */
5563 pipe_config->pipe_bpp = 8*3;
5564 }
5565
5566 if (HAS_IPS(dev))
5567 hsw_compute_ips_config(crtc, pipe_config);
5568
5569 if (pipe_config->has_pch_encoder)
5570 return ironlake_fdi_compute_config(crtc, pipe_config);
5571
5572 return 0;
5573 }
5574
5575 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5576 {
5577 struct drm_i915_private *dev_priv = dev->dev_private;
5578 u32 val;
5579 int divider;
5580
5581 /* FIXME: Punit isn't quite ready yet */
5582 if (IS_CHERRYVIEW(dev))
5583 return 400000;
5584
5585 if (dev_priv->hpll_freq == 0)
5586 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5587
5588 mutex_lock(&dev_priv->dpio_lock);
5589 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5590 mutex_unlock(&dev_priv->dpio_lock);
5591
5592 divider = val & DISPLAY_FREQUENCY_VALUES;
5593
5594 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5595 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5596 "cdclk change in progress\n");
5597
5598 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
5599 }
5600
5601 static int i945_get_display_clock_speed(struct drm_device *dev)
5602 {
5603 return 400000;
5604 }
5605
5606 static int i915_get_display_clock_speed(struct drm_device *dev)
5607 {
5608 return 333000;
5609 }
5610
5611 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5612 {
5613 return 200000;
5614 }
5615
5616 static int pnv_get_display_clock_speed(struct drm_device *dev)
5617 {
5618 u16 gcfgc = 0;
5619
5620 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5621
5622 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5623 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5624 return 267000;
5625 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5626 return 333000;
5627 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5628 return 444000;
5629 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5630 return 200000;
5631 default:
5632 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5633 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5634 return 133000;
5635 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5636 return 167000;
5637 }
5638 }
5639
5640 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5641 {
5642 u16 gcfgc = 0;
5643
5644 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5645
5646 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5647 return 133000;
5648 else {
5649 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5650 case GC_DISPLAY_CLOCK_333_MHZ:
5651 return 333000;
5652 default:
5653 case GC_DISPLAY_CLOCK_190_200_MHZ:
5654 return 190000;
5655 }
5656 }
5657 }
5658
5659 static int i865_get_display_clock_speed(struct drm_device *dev)
5660 {
5661 return 266000;
5662 }
5663
5664 static int i855_get_display_clock_speed(struct drm_device *dev)
5665 {
5666 u16 hpllcc = 0;
5667 /* Assume that the hardware is in the high speed state. This
5668 * should be the default.
5669 */
5670 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5671 case GC_CLOCK_133_200:
5672 case GC_CLOCK_100_200:
5673 return 200000;
5674 case GC_CLOCK_166_250:
5675 return 250000;
5676 case GC_CLOCK_100_133:
5677 return 133000;
5678 }
5679
5680 /* Shouldn't happen */
5681 return 0;
5682 }
5683
5684 static int i830_get_display_clock_speed(struct drm_device *dev)
5685 {
5686 return 133000;
5687 }
5688
5689 static void
5690 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5691 {
5692 while (*num > DATA_LINK_M_N_MASK ||
5693 *den > DATA_LINK_M_N_MASK) {
5694 *num >>= 1;
5695 *den >>= 1;
5696 }
5697 }
5698
5699 static void compute_m_n(unsigned int m, unsigned int n,
5700 uint32_t *ret_m, uint32_t *ret_n)
5701 {
5702 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5703 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5704 intel_reduce_m_n_ratio(ret_m, ret_n);
5705 }
5706
5707 void
5708 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5709 int pixel_clock, int link_clock,
5710 struct intel_link_m_n *m_n)
5711 {
5712 m_n->tu = 64;
5713
5714 compute_m_n(bits_per_pixel * pixel_clock,
5715 link_clock * nlanes * 8,
5716 &m_n->gmch_m, &m_n->gmch_n);
5717
5718 compute_m_n(pixel_clock, link_clock,
5719 &m_n->link_m, &m_n->link_n);
5720 }
5721
5722 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5723 {
5724 if (i915.panel_use_ssc >= 0)
5725 return i915.panel_use_ssc != 0;
5726 return dev_priv->vbt.lvds_use_ssc
5727 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5728 }
5729
5730 static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5731 {
5732 struct drm_device *dev = crtc->base.dev;
5733 struct drm_i915_private *dev_priv = dev->dev_private;
5734 int refclk;
5735
5736 if (IS_VALLEYVIEW(dev)) {
5737 refclk = 100000;
5738 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5739 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5740 refclk = dev_priv->vbt.lvds_ssc_freq;
5741 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5742 } else if (!IS_GEN2(dev)) {
5743 refclk = 96000;
5744 } else {
5745 refclk = 48000;
5746 }
5747
5748 return refclk;
5749 }
5750
5751 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5752 {
5753 return (1 << dpll->n) << 16 | dpll->m2;
5754 }
5755
5756 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5757 {
5758 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5759 }
5760
5761 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5762 intel_clock_t *reduced_clock)
5763 {
5764 struct drm_device *dev = crtc->base.dev;
5765 u32 fp, fp2 = 0;
5766
5767 if (IS_PINEVIEW(dev)) {
5768 fp = pnv_dpll_compute_fp(&crtc->new_config->dpll);
5769 if (reduced_clock)
5770 fp2 = pnv_dpll_compute_fp(reduced_clock);
5771 } else {
5772 fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll);
5773 if (reduced_clock)
5774 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5775 }
5776
5777 crtc->new_config->dpll_hw_state.fp0 = fp;
5778
5779 crtc->lowfreq_avail = false;
5780 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5781 reduced_clock && i915.powersave) {
5782 crtc->new_config->dpll_hw_state.fp1 = fp2;
5783 crtc->lowfreq_avail = true;
5784 } else {
5785 crtc->new_config->dpll_hw_state.fp1 = fp;
5786 }
5787 }
5788
5789 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5790 pipe)
5791 {
5792 u32 reg_val;
5793
5794 /*
5795 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5796 * and set it to a reasonable value instead.
5797 */
5798 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5799 reg_val &= 0xffffff00;
5800 reg_val |= 0x00000030;
5801 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5802
5803 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5804 reg_val &= 0x8cffffff;
5805 reg_val = 0x8c000000;
5806 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5807
5808 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5809 reg_val &= 0xffffff00;
5810 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5811
5812 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5813 reg_val &= 0x00ffffff;
5814 reg_val |= 0xb0000000;
5815 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5816 }
5817
5818 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5819 struct intel_link_m_n *m_n)
5820 {
5821 struct drm_device *dev = crtc->base.dev;
5822 struct drm_i915_private *dev_priv = dev->dev_private;
5823 int pipe = crtc->pipe;
5824
5825 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5826 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5827 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5828 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5829 }
5830
5831 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5832 struct intel_link_m_n *m_n,
5833 struct intel_link_m_n *m2_n2)
5834 {
5835 struct drm_device *dev = crtc->base.dev;
5836 struct drm_i915_private *dev_priv = dev->dev_private;
5837 int pipe = crtc->pipe;
5838 enum transcoder transcoder = crtc->config.cpu_transcoder;
5839
5840 if (INTEL_INFO(dev)->gen >= 5) {
5841 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5842 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5843 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5844 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5845 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5846 * for gen < 8) and if DRRS is supported (to make sure the
5847 * registers are not unnecessarily accessed).
5848 */
5849 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5850 crtc->config.has_drrs) {
5851 I915_WRITE(PIPE_DATA_M2(transcoder),
5852 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5853 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5854 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5855 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5856 }
5857 } else {
5858 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5859 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5860 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5861 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5862 }
5863 }
5864
5865 void intel_dp_set_m_n(struct intel_crtc *crtc)
5866 {
5867 if (crtc->config.has_pch_encoder)
5868 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5869 else
5870 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n,
5871 &crtc->config.dp_m2_n2);
5872 }
5873
5874 static void vlv_update_pll(struct intel_crtc *crtc,
5875 struct intel_crtc_config *pipe_config)
5876 {
5877 u32 dpll, dpll_md;
5878
5879 /*
5880 * Enable DPIO clock input. We should never disable the reference
5881 * clock for pipe B, since VGA hotplug / manual detection depends
5882 * on it.
5883 */
5884 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5885 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5886 /* We should never disable this, set it here for state tracking */
5887 if (crtc->pipe == PIPE_B)
5888 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5889 dpll |= DPLL_VCO_ENABLE;
5890 pipe_config->dpll_hw_state.dpll = dpll;
5891
5892 dpll_md = (pipe_config->pixel_multiplier - 1)
5893 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5894 pipe_config->dpll_hw_state.dpll_md = dpll_md;
5895 }
5896
5897 static void vlv_prepare_pll(struct intel_crtc *crtc,
5898 const struct intel_crtc_config *pipe_config)
5899 {
5900 struct drm_device *dev = crtc->base.dev;
5901 struct drm_i915_private *dev_priv = dev->dev_private;
5902 int pipe = crtc->pipe;
5903 u32 mdiv;
5904 u32 bestn, bestm1, bestm2, bestp1, bestp2;
5905 u32 coreclk, reg_val;
5906
5907 mutex_lock(&dev_priv->dpio_lock);
5908
5909 bestn = pipe_config->dpll.n;
5910 bestm1 = pipe_config->dpll.m1;
5911 bestm2 = pipe_config->dpll.m2;
5912 bestp1 = pipe_config->dpll.p1;
5913 bestp2 = pipe_config->dpll.p2;
5914
5915 /* See eDP HDMI DPIO driver vbios notes doc */
5916
5917 /* PLL B needs special handling */
5918 if (pipe == PIPE_B)
5919 vlv_pllb_recal_opamp(dev_priv, pipe);
5920
5921 /* Set up Tx target for periodic Rcomp update */
5922 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5923
5924 /* Disable target IRef on PLL */
5925 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5926 reg_val &= 0x00ffffff;
5927 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5928
5929 /* Disable fast lock */
5930 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5931
5932 /* Set idtafcrecal before PLL is enabled */
5933 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5934 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5935 mdiv |= ((bestn << DPIO_N_SHIFT));
5936 mdiv |= (1 << DPIO_K_SHIFT);
5937
5938 /*
5939 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5940 * but we don't support that).
5941 * Note: don't use the DAC post divider as it seems unstable.
5942 */
5943 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5944 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5945
5946 mdiv |= DPIO_ENABLE_CALIBRATION;
5947 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5948
5949 /* Set HBR and RBR LPF coefficients */
5950 if (pipe_config->port_clock == 162000 ||
5951 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
5952 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
5953 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5954 0x009f0003);
5955 else
5956 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5957 0x00d0000f);
5958
5959 if (crtc->config.has_dp_encoder) {
5960 /* Use SSC source */
5961 if (pipe == PIPE_A)
5962 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5963 0x0df40000);
5964 else
5965 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5966 0x0df70000);
5967 } else { /* HDMI or VGA */
5968 /* Use bend source */
5969 if (pipe == PIPE_A)
5970 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5971 0x0df70000);
5972 else
5973 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5974 0x0df40000);
5975 }
5976
5977 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5978 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5979 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
5980 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
5981 coreclk |= 0x01000000;
5982 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5983
5984 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5985 mutex_unlock(&dev_priv->dpio_lock);
5986 }
5987
5988 static void chv_update_pll(struct intel_crtc *crtc,
5989 struct intel_crtc_config *pipe_config)
5990 {
5991 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5992 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5993 DPLL_VCO_ENABLE;
5994 if (crtc->pipe != PIPE_A)
5995 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5996
5997 pipe_config->dpll_hw_state.dpll_md =
5998 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5999 }
6000
6001 static void chv_prepare_pll(struct intel_crtc *crtc,
6002 const struct intel_crtc_config *pipe_config)
6003 {
6004 struct drm_device *dev = crtc->base.dev;
6005 struct drm_i915_private *dev_priv = dev->dev_private;
6006 int pipe = crtc->pipe;
6007 int dpll_reg = DPLL(crtc->pipe);
6008 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6009 u32 loopfilter, intcoeff;
6010 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6011 int refclk;
6012
6013 bestn = pipe_config->dpll.n;
6014 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6015 bestm1 = pipe_config->dpll.m1;
6016 bestm2 = pipe_config->dpll.m2 >> 22;
6017 bestp1 = pipe_config->dpll.p1;
6018 bestp2 = pipe_config->dpll.p2;
6019
6020 /*
6021 * Enable Refclk and SSC
6022 */
6023 I915_WRITE(dpll_reg,
6024 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6025
6026 mutex_lock(&dev_priv->dpio_lock);
6027
6028 /* p1 and p2 divider */
6029 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6030 5 << DPIO_CHV_S1_DIV_SHIFT |
6031 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6032 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6033 1 << DPIO_CHV_K_DIV_SHIFT);
6034
6035 /* Feedback post-divider - m2 */
6036 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6037
6038 /* Feedback refclk divider - n and m1 */
6039 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6040 DPIO_CHV_M1_DIV_BY_2 |
6041 1 << DPIO_CHV_N_DIV_SHIFT);
6042
6043 /* M2 fraction division */
6044 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6045
6046 /* M2 fraction division enable */
6047 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
6048 DPIO_CHV_FRAC_DIV_EN |
6049 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
6050
6051 /* Loop filter */
6052 refclk = i9xx_get_refclk(crtc, 0);
6053 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
6054 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
6055 if (refclk == 100000)
6056 intcoeff = 11;
6057 else if (refclk == 38400)
6058 intcoeff = 10;
6059 else
6060 intcoeff = 9;
6061 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
6062 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6063
6064 /* AFC Recal */
6065 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6066 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6067 DPIO_AFC_RECAL);
6068
6069 mutex_unlock(&dev_priv->dpio_lock);
6070 }
6071
6072 /**
6073 * vlv_force_pll_on - forcibly enable just the PLL
6074 * @dev_priv: i915 private structure
6075 * @pipe: pipe PLL to enable
6076 * @dpll: PLL configuration
6077 *
6078 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6079 * in cases where we need the PLL enabled even when @pipe is not going to
6080 * be enabled.
6081 */
6082 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6083 const struct dpll *dpll)
6084 {
6085 struct intel_crtc *crtc =
6086 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6087 struct intel_crtc_config pipe_config = {
6088 .pixel_multiplier = 1,
6089 .dpll = *dpll,
6090 };
6091
6092 if (IS_CHERRYVIEW(dev)) {
6093 chv_update_pll(crtc, &pipe_config);
6094 chv_prepare_pll(crtc, &pipe_config);
6095 chv_enable_pll(crtc, &pipe_config);
6096 } else {
6097 vlv_update_pll(crtc, &pipe_config);
6098 vlv_prepare_pll(crtc, &pipe_config);
6099 vlv_enable_pll(crtc, &pipe_config);
6100 }
6101 }
6102
6103 /**
6104 * vlv_force_pll_off - forcibly disable just the PLL
6105 * @dev_priv: i915 private structure
6106 * @pipe: pipe PLL to disable
6107 *
6108 * Disable the PLL for @pipe. To be used in cases where we need
6109 * the PLL enabled even when @pipe is not going to be enabled.
6110 */
6111 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6112 {
6113 if (IS_CHERRYVIEW(dev))
6114 chv_disable_pll(to_i915(dev), pipe);
6115 else
6116 vlv_disable_pll(to_i915(dev), pipe);
6117 }
6118
6119 static void i9xx_update_pll(struct intel_crtc *crtc,
6120 intel_clock_t *reduced_clock,
6121 int num_connectors)
6122 {
6123 struct drm_device *dev = crtc->base.dev;
6124 struct drm_i915_private *dev_priv = dev->dev_private;
6125 u32 dpll;
6126 bool is_sdvo;
6127 struct dpll *clock = &crtc->new_config->dpll;
6128
6129 i9xx_update_pll_dividers(crtc, reduced_clock);
6130
6131 is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6132 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
6133
6134 dpll = DPLL_VGA_MODE_DIS;
6135
6136 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
6137 dpll |= DPLLB_MODE_LVDS;
6138 else
6139 dpll |= DPLLB_MODE_DAC_SERIAL;
6140
6141 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6142 dpll |= (crtc->new_config->pixel_multiplier - 1)
6143 << SDVO_MULTIPLIER_SHIFT_HIRES;
6144 }
6145
6146 if (is_sdvo)
6147 dpll |= DPLL_SDVO_HIGH_SPEED;
6148
6149 if (crtc->new_config->has_dp_encoder)
6150 dpll |= DPLL_SDVO_HIGH_SPEED;
6151
6152 /* compute bitmask from p1 value */
6153 if (IS_PINEVIEW(dev))
6154 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6155 else {
6156 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6157 if (IS_G4X(dev) && reduced_clock)
6158 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6159 }
6160 switch (clock->p2) {
6161 case 5:
6162 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6163 break;
6164 case 7:
6165 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6166 break;
6167 case 10:
6168 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6169 break;
6170 case 14:
6171 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6172 break;
6173 }
6174 if (INTEL_INFO(dev)->gen >= 4)
6175 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6176
6177 if (crtc->new_config->sdvo_tv_clock)
6178 dpll |= PLL_REF_INPUT_TVCLKINBC;
6179 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6180 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6181 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6182 else
6183 dpll |= PLL_REF_INPUT_DREFCLK;
6184
6185 dpll |= DPLL_VCO_ENABLE;
6186 crtc->new_config->dpll_hw_state.dpll = dpll;
6187
6188 if (INTEL_INFO(dev)->gen >= 4) {
6189 u32 dpll_md = (crtc->new_config->pixel_multiplier - 1)
6190 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6191 crtc->new_config->dpll_hw_state.dpll_md = dpll_md;
6192 }
6193 }
6194
6195 static void i8xx_update_pll(struct intel_crtc *crtc,
6196 intel_clock_t *reduced_clock,
6197 int num_connectors)
6198 {
6199 struct drm_device *dev = crtc->base.dev;
6200 struct drm_i915_private *dev_priv = dev->dev_private;
6201 u32 dpll;
6202 struct dpll *clock = &crtc->new_config->dpll;
6203
6204 i9xx_update_pll_dividers(crtc, reduced_clock);
6205
6206 dpll = DPLL_VGA_MODE_DIS;
6207
6208 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
6209 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6210 } else {
6211 if (clock->p1 == 2)
6212 dpll |= PLL_P1_DIVIDE_BY_TWO;
6213 else
6214 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6215 if (clock->p2 == 4)
6216 dpll |= PLL_P2_DIVIDE_BY_4;
6217 }
6218
6219 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
6220 dpll |= DPLL_DVO_2X_MODE;
6221
6222 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6223 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6224 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6225 else
6226 dpll |= PLL_REF_INPUT_DREFCLK;
6227
6228 dpll |= DPLL_VCO_ENABLE;
6229 crtc->new_config->dpll_hw_state.dpll = dpll;
6230 }
6231
6232 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6233 {
6234 struct drm_device *dev = intel_crtc->base.dev;
6235 struct drm_i915_private *dev_priv = dev->dev_private;
6236 enum pipe pipe = intel_crtc->pipe;
6237 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6238 struct drm_display_mode *adjusted_mode =
6239 &intel_crtc->config.adjusted_mode;
6240 uint32_t crtc_vtotal, crtc_vblank_end;
6241 int vsyncshift = 0;
6242
6243 /* We need to be careful not to changed the adjusted mode, for otherwise
6244 * the hw state checker will get angry at the mismatch. */
6245 crtc_vtotal = adjusted_mode->crtc_vtotal;
6246 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6247
6248 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6249 /* the chip adds 2 halflines automatically */
6250 crtc_vtotal -= 1;
6251 crtc_vblank_end -= 1;
6252
6253 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6254 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6255 else
6256 vsyncshift = adjusted_mode->crtc_hsync_start -
6257 adjusted_mode->crtc_htotal / 2;
6258 if (vsyncshift < 0)
6259 vsyncshift += adjusted_mode->crtc_htotal;
6260 }
6261
6262 if (INTEL_INFO(dev)->gen > 3)
6263 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6264
6265 I915_WRITE(HTOTAL(cpu_transcoder),
6266 (adjusted_mode->crtc_hdisplay - 1) |
6267 ((adjusted_mode->crtc_htotal - 1) << 16));
6268 I915_WRITE(HBLANK(cpu_transcoder),
6269 (adjusted_mode->crtc_hblank_start - 1) |
6270 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6271 I915_WRITE(HSYNC(cpu_transcoder),
6272 (adjusted_mode->crtc_hsync_start - 1) |
6273 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6274
6275 I915_WRITE(VTOTAL(cpu_transcoder),
6276 (adjusted_mode->crtc_vdisplay - 1) |
6277 ((crtc_vtotal - 1) << 16));
6278 I915_WRITE(VBLANK(cpu_transcoder),
6279 (adjusted_mode->crtc_vblank_start - 1) |
6280 ((crtc_vblank_end - 1) << 16));
6281 I915_WRITE(VSYNC(cpu_transcoder),
6282 (adjusted_mode->crtc_vsync_start - 1) |
6283 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6284
6285 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6286 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6287 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6288 * bits. */
6289 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6290 (pipe == PIPE_B || pipe == PIPE_C))
6291 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6292
6293 /* pipesrc controls the size that is scaled from, which should
6294 * always be the user's requested size.
6295 */
6296 I915_WRITE(PIPESRC(pipe),
6297 ((intel_crtc->config.pipe_src_w - 1) << 16) |
6298 (intel_crtc->config.pipe_src_h - 1));
6299 }
6300
6301 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6302 struct intel_crtc_config *pipe_config)
6303 {
6304 struct drm_device *dev = crtc->base.dev;
6305 struct drm_i915_private *dev_priv = dev->dev_private;
6306 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6307 uint32_t tmp;
6308
6309 tmp = I915_READ(HTOTAL(cpu_transcoder));
6310 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6311 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6312 tmp = I915_READ(HBLANK(cpu_transcoder));
6313 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6314 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6315 tmp = I915_READ(HSYNC(cpu_transcoder));
6316 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6317 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6318
6319 tmp = I915_READ(VTOTAL(cpu_transcoder));
6320 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6321 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6322 tmp = I915_READ(VBLANK(cpu_transcoder));
6323 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6324 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6325 tmp = I915_READ(VSYNC(cpu_transcoder));
6326 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6327 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6328
6329 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6330 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6331 pipe_config->adjusted_mode.crtc_vtotal += 1;
6332 pipe_config->adjusted_mode.crtc_vblank_end += 1;
6333 }
6334
6335 tmp = I915_READ(PIPESRC(crtc->pipe));
6336 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6337 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6338
6339 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
6340 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
6341 }
6342
6343 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6344 struct intel_crtc_config *pipe_config)
6345 {
6346 mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
6347 mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
6348 mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
6349 mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
6350
6351 mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
6352 mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
6353 mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
6354 mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
6355
6356 mode->flags = pipe_config->adjusted_mode.flags;
6357
6358 mode->clock = pipe_config->adjusted_mode.crtc_clock;
6359 mode->flags |= pipe_config->adjusted_mode.flags;
6360 }
6361
6362 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6363 {
6364 struct drm_device *dev = intel_crtc->base.dev;
6365 struct drm_i915_private *dev_priv = dev->dev_private;
6366 uint32_t pipeconf;
6367
6368 pipeconf = 0;
6369
6370 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6371 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6372 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6373
6374 if (intel_crtc->config.double_wide)
6375 pipeconf |= PIPECONF_DOUBLE_WIDE;
6376
6377 /* only g4x and later have fancy bpc/dither controls */
6378 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6379 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6380 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
6381 pipeconf |= PIPECONF_DITHER_EN |
6382 PIPECONF_DITHER_TYPE_SP;
6383
6384 switch (intel_crtc->config.pipe_bpp) {
6385 case 18:
6386 pipeconf |= PIPECONF_6BPC;
6387 break;
6388 case 24:
6389 pipeconf |= PIPECONF_8BPC;
6390 break;
6391 case 30:
6392 pipeconf |= PIPECONF_10BPC;
6393 break;
6394 default:
6395 /* Case prevented by intel_choose_pipe_bpp_dither. */
6396 BUG();
6397 }
6398 }
6399
6400 if (HAS_PIPE_CXSR(dev)) {
6401 if (intel_crtc->lowfreq_avail) {
6402 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6403 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6404 } else {
6405 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6406 }
6407 }
6408
6409 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6410 if (INTEL_INFO(dev)->gen < 4 ||
6411 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6412 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6413 else
6414 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6415 } else
6416 pipeconf |= PIPECONF_PROGRESSIVE;
6417
6418 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6419 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6420
6421 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6422 POSTING_READ(PIPECONF(intel_crtc->pipe));
6423 }
6424
6425 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc)
6426 {
6427 struct drm_device *dev = crtc->base.dev;
6428 struct drm_i915_private *dev_priv = dev->dev_private;
6429 int refclk, num_connectors = 0;
6430 intel_clock_t clock, reduced_clock;
6431 bool ok, has_reduced_clock = false;
6432 bool is_lvds = false, is_dsi = false;
6433 struct intel_encoder *encoder;
6434 const intel_limit_t *limit;
6435
6436 for_each_intel_encoder(dev, encoder) {
6437 if (encoder->new_crtc != crtc)
6438 continue;
6439
6440 switch (encoder->type) {
6441 case INTEL_OUTPUT_LVDS:
6442 is_lvds = true;
6443 break;
6444 case INTEL_OUTPUT_DSI:
6445 is_dsi = true;
6446 break;
6447 default:
6448 break;
6449 }
6450
6451 num_connectors++;
6452 }
6453
6454 if (is_dsi)
6455 return 0;
6456
6457 if (!crtc->new_config->clock_set) {
6458 refclk = i9xx_get_refclk(crtc, num_connectors);
6459
6460 /*
6461 * Returns a set of divisors for the desired target clock with
6462 * the given refclk, or FALSE. The returned values represent
6463 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6464 * 2) / p1 / p2.
6465 */
6466 limit = intel_limit(crtc, refclk);
6467 ok = dev_priv->display.find_dpll(limit, crtc,
6468 crtc->new_config->port_clock,
6469 refclk, NULL, &clock);
6470 if (!ok) {
6471 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6472 return -EINVAL;
6473 }
6474
6475 if (is_lvds && dev_priv->lvds_downclock_avail) {
6476 /*
6477 * Ensure we match the reduced clock's P to the target
6478 * clock. If the clocks don't match, we can't switch
6479 * the display clock by using the FP0/FP1. In such case
6480 * we will disable the LVDS downclock feature.
6481 */
6482 has_reduced_clock =
6483 dev_priv->display.find_dpll(limit, crtc,
6484 dev_priv->lvds_downclock,
6485 refclk, &clock,
6486 &reduced_clock);
6487 }
6488 /* Compat-code for transition, will disappear. */
6489 crtc->new_config->dpll.n = clock.n;
6490 crtc->new_config->dpll.m1 = clock.m1;
6491 crtc->new_config->dpll.m2 = clock.m2;
6492 crtc->new_config->dpll.p1 = clock.p1;
6493 crtc->new_config->dpll.p2 = clock.p2;
6494 }
6495
6496 if (IS_GEN2(dev)) {
6497 i8xx_update_pll(crtc,
6498 has_reduced_clock ? &reduced_clock : NULL,
6499 num_connectors);
6500 } else if (IS_CHERRYVIEW(dev)) {
6501 chv_update_pll(crtc, crtc->new_config);
6502 } else if (IS_VALLEYVIEW(dev)) {
6503 vlv_update_pll(crtc, crtc->new_config);
6504 } else {
6505 i9xx_update_pll(crtc,
6506 has_reduced_clock ? &reduced_clock : NULL,
6507 num_connectors);
6508 }
6509
6510 return 0;
6511 }
6512
6513 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6514 struct intel_crtc_config *pipe_config)
6515 {
6516 struct drm_device *dev = crtc->base.dev;
6517 struct drm_i915_private *dev_priv = dev->dev_private;
6518 uint32_t tmp;
6519
6520 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6521 return;
6522
6523 tmp = I915_READ(PFIT_CONTROL);
6524 if (!(tmp & PFIT_ENABLE))
6525 return;
6526
6527 /* Check whether the pfit is attached to our pipe. */
6528 if (INTEL_INFO(dev)->gen < 4) {
6529 if (crtc->pipe != PIPE_B)
6530 return;
6531 } else {
6532 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6533 return;
6534 }
6535
6536 pipe_config->gmch_pfit.control = tmp;
6537 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6538 if (INTEL_INFO(dev)->gen < 5)
6539 pipe_config->gmch_pfit.lvds_border_bits =
6540 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6541 }
6542
6543 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6544 struct intel_crtc_config *pipe_config)
6545 {
6546 struct drm_device *dev = crtc->base.dev;
6547 struct drm_i915_private *dev_priv = dev->dev_private;
6548 int pipe = pipe_config->cpu_transcoder;
6549 intel_clock_t clock;
6550 u32 mdiv;
6551 int refclk = 100000;
6552
6553 /* In case of MIPI DPLL will not even be used */
6554 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6555 return;
6556
6557 mutex_lock(&dev_priv->dpio_lock);
6558 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6559 mutex_unlock(&dev_priv->dpio_lock);
6560
6561 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6562 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6563 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6564 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6565 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6566
6567 vlv_clock(refclk, &clock);
6568
6569 /* clock.dot is the fast clock */
6570 pipe_config->port_clock = clock.dot / 5;
6571 }
6572
6573 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6574 struct intel_plane_config *plane_config)
6575 {
6576 struct drm_device *dev = crtc->base.dev;
6577 struct drm_i915_private *dev_priv = dev->dev_private;
6578 u32 val, base, offset;
6579 int pipe = crtc->pipe, plane = crtc->plane;
6580 int fourcc, pixel_format;
6581 int aligned_height;
6582
6583 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6584 if (!crtc->base.primary->fb) {
6585 DRM_DEBUG_KMS("failed to alloc fb\n");
6586 return;
6587 }
6588
6589 val = I915_READ(DSPCNTR(plane));
6590
6591 if (INTEL_INFO(dev)->gen >= 4)
6592 if (val & DISPPLANE_TILED)
6593 plane_config->tiled = true;
6594
6595 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6596 fourcc = intel_format_to_fourcc(pixel_format);
6597 crtc->base.primary->fb->pixel_format = fourcc;
6598 crtc->base.primary->fb->bits_per_pixel =
6599 drm_format_plane_cpp(fourcc, 0) * 8;
6600
6601 if (INTEL_INFO(dev)->gen >= 4) {
6602 if (plane_config->tiled)
6603 offset = I915_READ(DSPTILEOFF(plane));
6604 else
6605 offset = I915_READ(DSPLINOFF(plane));
6606 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6607 } else {
6608 base = I915_READ(DSPADDR(plane));
6609 }
6610 plane_config->base = base;
6611
6612 val = I915_READ(PIPESRC(pipe));
6613 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6614 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6615
6616 val = I915_READ(DSPSTRIDE(pipe));
6617 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
6618
6619 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6620 plane_config->tiled);
6621
6622 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6623 aligned_height);
6624
6625 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6626 pipe, plane, crtc->base.primary->fb->width,
6627 crtc->base.primary->fb->height,
6628 crtc->base.primary->fb->bits_per_pixel, base,
6629 crtc->base.primary->fb->pitches[0],
6630 plane_config->size);
6631
6632 }
6633
6634 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6635 struct intel_crtc_config *pipe_config)
6636 {
6637 struct drm_device *dev = crtc->base.dev;
6638 struct drm_i915_private *dev_priv = dev->dev_private;
6639 int pipe = pipe_config->cpu_transcoder;
6640 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6641 intel_clock_t clock;
6642 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6643 int refclk = 100000;
6644
6645 mutex_lock(&dev_priv->dpio_lock);
6646 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6647 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6648 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6649 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6650 mutex_unlock(&dev_priv->dpio_lock);
6651
6652 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6653 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6654 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6655 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6656 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6657
6658 chv_clock(refclk, &clock);
6659
6660 /* clock.dot is the fast clock */
6661 pipe_config->port_clock = clock.dot / 5;
6662 }
6663
6664 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6665 struct intel_crtc_config *pipe_config)
6666 {
6667 struct drm_device *dev = crtc->base.dev;
6668 struct drm_i915_private *dev_priv = dev->dev_private;
6669 uint32_t tmp;
6670
6671 if (!intel_display_power_is_enabled(dev_priv,
6672 POWER_DOMAIN_PIPE(crtc->pipe)))
6673 return false;
6674
6675 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6676 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6677
6678 tmp = I915_READ(PIPECONF(crtc->pipe));
6679 if (!(tmp & PIPECONF_ENABLE))
6680 return false;
6681
6682 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6683 switch (tmp & PIPECONF_BPC_MASK) {
6684 case PIPECONF_6BPC:
6685 pipe_config->pipe_bpp = 18;
6686 break;
6687 case PIPECONF_8BPC:
6688 pipe_config->pipe_bpp = 24;
6689 break;
6690 case PIPECONF_10BPC:
6691 pipe_config->pipe_bpp = 30;
6692 break;
6693 default:
6694 break;
6695 }
6696 }
6697
6698 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6699 pipe_config->limited_color_range = true;
6700
6701 if (INTEL_INFO(dev)->gen < 4)
6702 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6703
6704 intel_get_pipe_timings(crtc, pipe_config);
6705
6706 i9xx_get_pfit_config(crtc, pipe_config);
6707
6708 if (INTEL_INFO(dev)->gen >= 4) {
6709 tmp = I915_READ(DPLL_MD(crtc->pipe));
6710 pipe_config->pixel_multiplier =
6711 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6712 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6713 pipe_config->dpll_hw_state.dpll_md = tmp;
6714 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6715 tmp = I915_READ(DPLL(crtc->pipe));
6716 pipe_config->pixel_multiplier =
6717 ((tmp & SDVO_MULTIPLIER_MASK)
6718 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6719 } else {
6720 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6721 * port and will be fixed up in the encoder->get_config
6722 * function. */
6723 pipe_config->pixel_multiplier = 1;
6724 }
6725 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6726 if (!IS_VALLEYVIEW(dev)) {
6727 /*
6728 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6729 * on 830. Filter it out here so that we don't
6730 * report errors due to that.
6731 */
6732 if (IS_I830(dev))
6733 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6734
6735 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6736 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6737 } else {
6738 /* Mask out read-only status bits. */
6739 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6740 DPLL_PORTC_READY_MASK |
6741 DPLL_PORTB_READY_MASK);
6742 }
6743
6744 if (IS_CHERRYVIEW(dev))
6745 chv_crtc_clock_get(crtc, pipe_config);
6746 else if (IS_VALLEYVIEW(dev))
6747 vlv_crtc_clock_get(crtc, pipe_config);
6748 else
6749 i9xx_crtc_clock_get(crtc, pipe_config);
6750
6751 return true;
6752 }
6753
6754 static void ironlake_init_pch_refclk(struct drm_device *dev)
6755 {
6756 struct drm_i915_private *dev_priv = dev->dev_private;
6757 struct intel_encoder *encoder;
6758 u32 val, final;
6759 bool has_lvds = false;
6760 bool has_cpu_edp = false;
6761 bool has_panel = false;
6762 bool has_ck505 = false;
6763 bool can_ssc = false;
6764
6765 /* We need to take the global config into account */
6766 for_each_intel_encoder(dev, encoder) {
6767 switch (encoder->type) {
6768 case INTEL_OUTPUT_LVDS:
6769 has_panel = true;
6770 has_lvds = true;
6771 break;
6772 case INTEL_OUTPUT_EDP:
6773 has_panel = true;
6774 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6775 has_cpu_edp = true;
6776 break;
6777 default:
6778 break;
6779 }
6780 }
6781
6782 if (HAS_PCH_IBX(dev)) {
6783 has_ck505 = dev_priv->vbt.display_clock_mode;
6784 can_ssc = has_ck505;
6785 } else {
6786 has_ck505 = false;
6787 can_ssc = true;
6788 }
6789
6790 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6791 has_panel, has_lvds, has_ck505);
6792
6793 /* Ironlake: try to setup display ref clock before DPLL
6794 * enabling. This is only under driver's control after
6795 * PCH B stepping, previous chipset stepping should be
6796 * ignoring this setting.
6797 */
6798 val = I915_READ(PCH_DREF_CONTROL);
6799
6800 /* As we must carefully and slowly disable/enable each source in turn,
6801 * compute the final state we want first and check if we need to
6802 * make any changes at all.
6803 */
6804 final = val;
6805 final &= ~DREF_NONSPREAD_SOURCE_MASK;
6806 if (has_ck505)
6807 final |= DREF_NONSPREAD_CK505_ENABLE;
6808 else
6809 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6810
6811 final &= ~DREF_SSC_SOURCE_MASK;
6812 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6813 final &= ~DREF_SSC1_ENABLE;
6814
6815 if (has_panel) {
6816 final |= DREF_SSC_SOURCE_ENABLE;
6817
6818 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6819 final |= DREF_SSC1_ENABLE;
6820
6821 if (has_cpu_edp) {
6822 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6823 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6824 else
6825 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6826 } else
6827 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6828 } else {
6829 final |= DREF_SSC_SOURCE_DISABLE;
6830 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6831 }
6832
6833 if (final == val)
6834 return;
6835
6836 /* Always enable nonspread source */
6837 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6838
6839 if (has_ck505)
6840 val |= DREF_NONSPREAD_CK505_ENABLE;
6841 else
6842 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6843
6844 if (has_panel) {
6845 val &= ~DREF_SSC_SOURCE_MASK;
6846 val |= DREF_SSC_SOURCE_ENABLE;
6847
6848 /* SSC must be turned on before enabling the CPU output */
6849 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6850 DRM_DEBUG_KMS("Using SSC on panel\n");
6851 val |= DREF_SSC1_ENABLE;
6852 } else
6853 val &= ~DREF_SSC1_ENABLE;
6854
6855 /* Get SSC going before enabling the outputs */
6856 I915_WRITE(PCH_DREF_CONTROL, val);
6857 POSTING_READ(PCH_DREF_CONTROL);
6858 udelay(200);
6859
6860 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6861
6862 /* Enable CPU source on CPU attached eDP */
6863 if (has_cpu_edp) {
6864 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6865 DRM_DEBUG_KMS("Using SSC on eDP\n");
6866 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6867 } else
6868 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6869 } else
6870 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6871
6872 I915_WRITE(PCH_DREF_CONTROL, val);
6873 POSTING_READ(PCH_DREF_CONTROL);
6874 udelay(200);
6875 } else {
6876 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6877
6878 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6879
6880 /* Turn off CPU output */
6881 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6882
6883 I915_WRITE(PCH_DREF_CONTROL, val);
6884 POSTING_READ(PCH_DREF_CONTROL);
6885 udelay(200);
6886
6887 /* Turn off the SSC source */
6888 val &= ~DREF_SSC_SOURCE_MASK;
6889 val |= DREF_SSC_SOURCE_DISABLE;
6890
6891 /* Turn off SSC1 */
6892 val &= ~DREF_SSC1_ENABLE;
6893
6894 I915_WRITE(PCH_DREF_CONTROL, val);
6895 POSTING_READ(PCH_DREF_CONTROL);
6896 udelay(200);
6897 }
6898
6899 BUG_ON(val != final);
6900 }
6901
6902 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6903 {
6904 uint32_t tmp;
6905
6906 tmp = I915_READ(SOUTH_CHICKEN2);
6907 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6908 I915_WRITE(SOUTH_CHICKEN2, tmp);
6909
6910 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6911 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6912 DRM_ERROR("FDI mPHY reset assert timeout\n");
6913
6914 tmp = I915_READ(SOUTH_CHICKEN2);
6915 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6916 I915_WRITE(SOUTH_CHICKEN2, tmp);
6917
6918 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6919 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6920 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6921 }
6922
6923 /* WaMPhyProgramming:hsw */
6924 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6925 {
6926 uint32_t tmp;
6927
6928 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6929 tmp &= ~(0xFF << 24);
6930 tmp |= (0x12 << 24);
6931 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6932
6933 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6934 tmp |= (1 << 11);
6935 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6936
6937 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6938 tmp |= (1 << 11);
6939 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6940
6941 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6942 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6943 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6944
6945 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6946 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6947 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6948
6949 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6950 tmp &= ~(7 << 13);
6951 tmp |= (5 << 13);
6952 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6953
6954 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6955 tmp &= ~(7 << 13);
6956 tmp |= (5 << 13);
6957 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6958
6959 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6960 tmp &= ~0xFF;
6961 tmp |= 0x1C;
6962 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6963
6964 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6965 tmp &= ~0xFF;
6966 tmp |= 0x1C;
6967 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6968
6969 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6970 tmp &= ~(0xFF << 16);
6971 tmp |= (0x1C << 16);
6972 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6973
6974 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6975 tmp &= ~(0xFF << 16);
6976 tmp |= (0x1C << 16);
6977 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6978
6979 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6980 tmp |= (1 << 27);
6981 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6982
6983 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6984 tmp |= (1 << 27);
6985 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6986
6987 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6988 tmp &= ~(0xF << 28);
6989 tmp |= (4 << 28);
6990 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6991
6992 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6993 tmp &= ~(0xF << 28);
6994 tmp |= (4 << 28);
6995 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6996 }
6997
6998 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6999 * Programming" based on the parameters passed:
7000 * - Sequence to enable CLKOUT_DP
7001 * - Sequence to enable CLKOUT_DP without spread
7002 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7003 */
7004 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
7005 bool with_fdi)
7006 {
7007 struct drm_i915_private *dev_priv = dev->dev_private;
7008 uint32_t reg, tmp;
7009
7010 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7011 with_spread = true;
7012 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
7013 with_fdi, "LP PCH doesn't have FDI\n"))
7014 with_fdi = false;
7015
7016 mutex_lock(&dev_priv->dpio_lock);
7017
7018 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7019 tmp &= ~SBI_SSCCTL_DISABLE;
7020 tmp |= SBI_SSCCTL_PATHALT;
7021 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7022
7023 udelay(24);
7024
7025 if (with_spread) {
7026 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7027 tmp &= ~SBI_SSCCTL_PATHALT;
7028 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7029
7030 if (with_fdi) {
7031 lpt_reset_fdi_mphy(dev_priv);
7032 lpt_program_fdi_mphy(dev_priv);
7033 }
7034 }
7035
7036 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7037 SBI_GEN0 : SBI_DBUFF0;
7038 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7039 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7040 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7041
7042 mutex_unlock(&dev_priv->dpio_lock);
7043 }
7044
7045 /* Sequence to disable CLKOUT_DP */
7046 static void lpt_disable_clkout_dp(struct drm_device *dev)
7047 {
7048 struct drm_i915_private *dev_priv = dev->dev_private;
7049 uint32_t reg, tmp;
7050
7051 mutex_lock(&dev_priv->dpio_lock);
7052
7053 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7054 SBI_GEN0 : SBI_DBUFF0;
7055 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7056 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7057 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7058
7059 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7060 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7061 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7062 tmp |= SBI_SSCCTL_PATHALT;
7063 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7064 udelay(32);
7065 }
7066 tmp |= SBI_SSCCTL_DISABLE;
7067 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7068 }
7069
7070 mutex_unlock(&dev_priv->dpio_lock);
7071 }
7072
7073 static void lpt_init_pch_refclk(struct drm_device *dev)
7074 {
7075 struct intel_encoder *encoder;
7076 bool has_vga = false;
7077
7078 for_each_intel_encoder(dev, encoder) {
7079 switch (encoder->type) {
7080 case INTEL_OUTPUT_ANALOG:
7081 has_vga = true;
7082 break;
7083 default:
7084 break;
7085 }
7086 }
7087
7088 if (has_vga)
7089 lpt_enable_clkout_dp(dev, true, true);
7090 else
7091 lpt_disable_clkout_dp(dev);
7092 }
7093
7094 /*
7095 * Initialize reference clocks when the driver loads
7096 */
7097 void intel_init_pch_refclk(struct drm_device *dev)
7098 {
7099 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7100 ironlake_init_pch_refclk(dev);
7101 else if (HAS_PCH_LPT(dev))
7102 lpt_init_pch_refclk(dev);
7103 }
7104
7105 static int ironlake_get_refclk(struct drm_crtc *crtc)
7106 {
7107 struct drm_device *dev = crtc->dev;
7108 struct drm_i915_private *dev_priv = dev->dev_private;
7109 struct intel_encoder *encoder;
7110 int num_connectors = 0;
7111 bool is_lvds = false;
7112
7113 for_each_intel_encoder(dev, encoder) {
7114 if (encoder->new_crtc != to_intel_crtc(crtc))
7115 continue;
7116
7117 switch (encoder->type) {
7118 case INTEL_OUTPUT_LVDS:
7119 is_lvds = true;
7120 break;
7121 default:
7122 break;
7123 }
7124 num_connectors++;
7125 }
7126
7127 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7128 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7129 dev_priv->vbt.lvds_ssc_freq);
7130 return dev_priv->vbt.lvds_ssc_freq;
7131 }
7132
7133 return 120000;
7134 }
7135
7136 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7137 {
7138 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7139 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7140 int pipe = intel_crtc->pipe;
7141 uint32_t val;
7142
7143 val = 0;
7144
7145 switch (intel_crtc->config.pipe_bpp) {
7146 case 18:
7147 val |= PIPECONF_6BPC;
7148 break;
7149 case 24:
7150 val |= PIPECONF_8BPC;
7151 break;
7152 case 30:
7153 val |= PIPECONF_10BPC;
7154 break;
7155 case 36:
7156 val |= PIPECONF_12BPC;
7157 break;
7158 default:
7159 /* Case prevented by intel_choose_pipe_bpp_dither. */
7160 BUG();
7161 }
7162
7163 if (intel_crtc->config.dither)
7164 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7165
7166 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7167 val |= PIPECONF_INTERLACED_ILK;
7168 else
7169 val |= PIPECONF_PROGRESSIVE;
7170
7171 if (intel_crtc->config.limited_color_range)
7172 val |= PIPECONF_COLOR_RANGE_SELECT;
7173
7174 I915_WRITE(PIPECONF(pipe), val);
7175 POSTING_READ(PIPECONF(pipe));
7176 }
7177
7178 /*
7179 * Set up the pipe CSC unit.
7180 *
7181 * Currently only full range RGB to limited range RGB conversion
7182 * is supported, but eventually this should handle various
7183 * RGB<->YCbCr scenarios as well.
7184 */
7185 static void intel_set_pipe_csc(struct drm_crtc *crtc)
7186 {
7187 struct drm_device *dev = crtc->dev;
7188 struct drm_i915_private *dev_priv = dev->dev_private;
7189 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7190 int pipe = intel_crtc->pipe;
7191 uint16_t coeff = 0x7800; /* 1.0 */
7192
7193 /*
7194 * TODO: Check what kind of values actually come out of the pipe
7195 * with these coeff/postoff values and adjust to get the best
7196 * accuracy. Perhaps we even need to take the bpc value into
7197 * consideration.
7198 */
7199
7200 if (intel_crtc->config.limited_color_range)
7201 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7202
7203 /*
7204 * GY/GU and RY/RU should be the other way around according
7205 * to BSpec, but reality doesn't agree. Just set them up in
7206 * a way that results in the correct picture.
7207 */
7208 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7209 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7210
7211 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7212 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7213
7214 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7215 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7216
7217 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7218 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7219 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7220
7221 if (INTEL_INFO(dev)->gen > 6) {
7222 uint16_t postoff = 0;
7223
7224 if (intel_crtc->config.limited_color_range)
7225 postoff = (16 * (1 << 12) / 255) & 0x1fff;
7226
7227 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7228 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7229 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7230
7231 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7232 } else {
7233 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7234
7235 if (intel_crtc->config.limited_color_range)
7236 mode |= CSC_BLACK_SCREEN_OFFSET;
7237
7238 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7239 }
7240 }
7241
7242 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7243 {
7244 struct drm_device *dev = crtc->dev;
7245 struct drm_i915_private *dev_priv = dev->dev_private;
7246 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7247 enum pipe pipe = intel_crtc->pipe;
7248 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7249 uint32_t val;
7250
7251 val = 0;
7252
7253 if (IS_HASWELL(dev) && intel_crtc->config.dither)
7254 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7255
7256 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7257 val |= PIPECONF_INTERLACED_ILK;
7258 else
7259 val |= PIPECONF_PROGRESSIVE;
7260
7261 I915_WRITE(PIPECONF(cpu_transcoder), val);
7262 POSTING_READ(PIPECONF(cpu_transcoder));
7263
7264 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7265 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7266
7267 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7268 val = 0;
7269
7270 switch (intel_crtc->config.pipe_bpp) {
7271 case 18:
7272 val |= PIPEMISC_DITHER_6_BPC;
7273 break;
7274 case 24:
7275 val |= PIPEMISC_DITHER_8_BPC;
7276 break;
7277 case 30:
7278 val |= PIPEMISC_DITHER_10_BPC;
7279 break;
7280 case 36:
7281 val |= PIPEMISC_DITHER_12_BPC;
7282 break;
7283 default:
7284 /* Case prevented by pipe_config_set_bpp. */
7285 BUG();
7286 }
7287
7288 if (intel_crtc->config.dither)
7289 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7290
7291 I915_WRITE(PIPEMISC(pipe), val);
7292 }
7293 }
7294
7295 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7296 intel_clock_t *clock,
7297 bool *has_reduced_clock,
7298 intel_clock_t *reduced_clock)
7299 {
7300 struct drm_device *dev = crtc->dev;
7301 struct drm_i915_private *dev_priv = dev->dev_private;
7302 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7303 int refclk;
7304 const intel_limit_t *limit;
7305 bool ret, is_lvds = false;
7306
7307 is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
7308
7309 refclk = ironlake_get_refclk(crtc);
7310
7311 /*
7312 * Returns a set of divisors for the desired target clock with the given
7313 * refclk, or FALSE. The returned values represent the clock equation:
7314 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7315 */
7316 limit = intel_limit(intel_crtc, refclk);
7317 ret = dev_priv->display.find_dpll(limit, intel_crtc,
7318 intel_crtc->new_config->port_clock,
7319 refclk, NULL, clock);
7320 if (!ret)
7321 return false;
7322
7323 if (is_lvds && dev_priv->lvds_downclock_avail) {
7324 /*
7325 * Ensure we match the reduced clock's P to the target clock.
7326 * If the clocks don't match, we can't switch the display clock
7327 * by using the FP0/FP1. In such case we will disable the LVDS
7328 * downclock feature.
7329 */
7330 *has_reduced_clock =
7331 dev_priv->display.find_dpll(limit, intel_crtc,
7332 dev_priv->lvds_downclock,
7333 refclk, clock,
7334 reduced_clock);
7335 }
7336
7337 return true;
7338 }
7339
7340 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7341 {
7342 /*
7343 * Account for spread spectrum to avoid
7344 * oversubscribing the link. Max center spread
7345 * is 2.5%; use 5% for safety's sake.
7346 */
7347 u32 bps = target_clock * bpp * 21 / 20;
7348 return DIV_ROUND_UP(bps, link_bw * 8);
7349 }
7350
7351 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7352 {
7353 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7354 }
7355
7356 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7357 u32 *fp,
7358 intel_clock_t *reduced_clock, u32 *fp2)
7359 {
7360 struct drm_crtc *crtc = &intel_crtc->base;
7361 struct drm_device *dev = crtc->dev;
7362 struct drm_i915_private *dev_priv = dev->dev_private;
7363 struct intel_encoder *intel_encoder;
7364 uint32_t dpll;
7365 int factor, num_connectors = 0;
7366 bool is_lvds = false, is_sdvo = false;
7367
7368 for_each_intel_encoder(dev, intel_encoder) {
7369 if (intel_encoder->new_crtc != to_intel_crtc(crtc))
7370 continue;
7371
7372 switch (intel_encoder->type) {
7373 case INTEL_OUTPUT_LVDS:
7374 is_lvds = true;
7375 break;
7376 case INTEL_OUTPUT_SDVO:
7377 case INTEL_OUTPUT_HDMI:
7378 is_sdvo = true;
7379 break;
7380 default:
7381 break;
7382 }
7383
7384 num_connectors++;
7385 }
7386
7387 /* Enable autotuning of the PLL clock (if permissible) */
7388 factor = 21;
7389 if (is_lvds) {
7390 if ((intel_panel_use_ssc(dev_priv) &&
7391 dev_priv->vbt.lvds_ssc_freq == 100000) ||
7392 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7393 factor = 25;
7394 } else if (intel_crtc->new_config->sdvo_tv_clock)
7395 factor = 20;
7396
7397 if (ironlake_needs_fb_cb_tune(&intel_crtc->new_config->dpll, factor))
7398 *fp |= FP_CB_TUNE;
7399
7400 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7401 *fp2 |= FP_CB_TUNE;
7402
7403 dpll = 0;
7404
7405 if (is_lvds)
7406 dpll |= DPLLB_MODE_LVDS;
7407 else
7408 dpll |= DPLLB_MODE_DAC_SERIAL;
7409
7410 dpll |= (intel_crtc->new_config->pixel_multiplier - 1)
7411 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7412
7413 if (is_sdvo)
7414 dpll |= DPLL_SDVO_HIGH_SPEED;
7415 if (intel_crtc->new_config->has_dp_encoder)
7416 dpll |= DPLL_SDVO_HIGH_SPEED;
7417
7418 /* compute bitmask from p1 value */
7419 dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7420 /* also FPA1 */
7421 dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7422
7423 switch (intel_crtc->new_config->dpll.p2) {
7424 case 5:
7425 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7426 break;
7427 case 7:
7428 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7429 break;
7430 case 10:
7431 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7432 break;
7433 case 14:
7434 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7435 break;
7436 }
7437
7438 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7439 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7440 else
7441 dpll |= PLL_REF_INPUT_DREFCLK;
7442
7443 return dpll | DPLL_VCO_ENABLE;
7444 }
7445
7446 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc)
7447 {
7448 struct drm_device *dev = crtc->base.dev;
7449 intel_clock_t clock, reduced_clock;
7450 u32 dpll = 0, fp = 0, fp2 = 0;
7451 bool ok, has_reduced_clock = false;
7452 bool is_lvds = false;
7453 struct intel_shared_dpll *pll;
7454
7455 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7456
7457 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7458 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7459
7460 ok = ironlake_compute_clocks(&crtc->base, &clock,
7461 &has_reduced_clock, &reduced_clock);
7462 if (!ok && !crtc->new_config->clock_set) {
7463 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7464 return -EINVAL;
7465 }
7466 /* Compat-code for transition, will disappear. */
7467 if (!crtc->new_config->clock_set) {
7468 crtc->new_config->dpll.n = clock.n;
7469 crtc->new_config->dpll.m1 = clock.m1;
7470 crtc->new_config->dpll.m2 = clock.m2;
7471 crtc->new_config->dpll.p1 = clock.p1;
7472 crtc->new_config->dpll.p2 = clock.p2;
7473 }
7474
7475 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7476 if (crtc->new_config->has_pch_encoder) {
7477 fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll);
7478 if (has_reduced_clock)
7479 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7480
7481 dpll = ironlake_compute_dpll(crtc,
7482 &fp, &reduced_clock,
7483 has_reduced_clock ? &fp2 : NULL);
7484
7485 crtc->new_config->dpll_hw_state.dpll = dpll;
7486 crtc->new_config->dpll_hw_state.fp0 = fp;
7487 if (has_reduced_clock)
7488 crtc->new_config->dpll_hw_state.fp1 = fp2;
7489 else
7490 crtc->new_config->dpll_hw_state.fp1 = fp;
7491
7492 pll = intel_get_shared_dpll(crtc);
7493 if (pll == NULL) {
7494 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7495 pipe_name(crtc->pipe));
7496 return -EINVAL;
7497 }
7498 }
7499
7500 if (is_lvds && has_reduced_clock && i915.powersave)
7501 crtc->lowfreq_avail = true;
7502 else
7503 crtc->lowfreq_avail = false;
7504
7505 return 0;
7506 }
7507
7508 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7509 struct intel_link_m_n *m_n)
7510 {
7511 struct drm_device *dev = crtc->base.dev;
7512 struct drm_i915_private *dev_priv = dev->dev_private;
7513 enum pipe pipe = crtc->pipe;
7514
7515 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7516 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7517 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7518 & ~TU_SIZE_MASK;
7519 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7520 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7521 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7522 }
7523
7524 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7525 enum transcoder transcoder,
7526 struct intel_link_m_n *m_n,
7527 struct intel_link_m_n *m2_n2)
7528 {
7529 struct drm_device *dev = crtc->base.dev;
7530 struct drm_i915_private *dev_priv = dev->dev_private;
7531 enum pipe pipe = crtc->pipe;
7532
7533 if (INTEL_INFO(dev)->gen >= 5) {
7534 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7535 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7536 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7537 & ~TU_SIZE_MASK;
7538 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7539 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7540 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7541 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7542 * gen < 8) and if DRRS is supported (to make sure the
7543 * registers are not unnecessarily read).
7544 */
7545 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7546 crtc->config.has_drrs) {
7547 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7548 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7549 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7550 & ~TU_SIZE_MASK;
7551 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7552 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7553 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7554 }
7555 } else {
7556 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7557 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7558 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7559 & ~TU_SIZE_MASK;
7560 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7561 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7562 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7563 }
7564 }
7565
7566 void intel_dp_get_m_n(struct intel_crtc *crtc,
7567 struct intel_crtc_config *pipe_config)
7568 {
7569 if (crtc->config.has_pch_encoder)
7570 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7571 else
7572 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7573 &pipe_config->dp_m_n,
7574 &pipe_config->dp_m2_n2);
7575 }
7576
7577 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7578 struct intel_crtc_config *pipe_config)
7579 {
7580 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7581 &pipe_config->fdi_m_n, NULL);
7582 }
7583
7584 static void skylake_get_pfit_config(struct intel_crtc *crtc,
7585 struct intel_crtc_config *pipe_config)
7586 {
7587 struct drm_device *dev = crtc->base.dev;
7588 struct drm_i915_private *dev_priv = dev->dev_private;
7589 uint32_t tmp;
7590
7591 tmp = I915_READ(PS_CTL(crtc->pipe));
7592
7593 if (tmp & PS_ENABLE) {
7594 pipe_config->pch_pfit.enabled = true;
7595 pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe));
7596 pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe));
7597 }
7598 }
7599
7600 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7601 struct intel_crtc_config *pipe_config)
7602 {
7603 struct drm_device *dev = crtc->base.dev;
7604 struct drm_i915_private *dev_priv = dev->dev_private;
7605 uint32_t tmp;
7606
7607 tmp = I915_READ(PF_CTL(crtc->pipe));
7608
7609 if (tmp & PF_ENABLE) {
7610 pipe_config->pch_pfit.enabled = true;
7611 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7612 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7613
7614 /* We currently do not free assignements of panel fitters on
7615 * ivb/hsw (since we don't use the higher upscaling modes which
7616 * differentiates them) so just WARN about this case for now. */
7617 if (IS_GEN7(dev)) {
7618 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7619 PF_PIPE_SEL_IVB(crtc->pipe));
7620 }
7621 }
7622 }
7623
7624 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7625 struct intel_plane_config *plane_config)
7626 {
7627 struct drm_device *dev = crtc->base.dev;
7628 struct drm_i915_private *dev_priv = dev->dev_private;
7629 u32 val, base, offset;
7630 int pipe = crtc->pipe, plane = crtc->plane;
7631 int fourcc, pixel_format;
7632 int aligned_height;
7633
7634 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7635 if (!crtc->base.primary->fb) {
7636 DRM_DEBUG_KMS("failed to alloc fb\n");
7637 return;
7638 }
7639
7640 val = I915_READ(DSPCNTR(plane));
7641
7642 if (INTEL_INFO(dev)->gen >= 4)
7643 if (val & DISPPLANE_TILED)
7644 plane_config->tiled = true;
7645
7646 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7647 fourcc = intel_format_to_fourcc(pixel_format);
7648 crtc->base.primary->fb->pixel_format = fourcc;
7649 crtc->base.primary->fb->bits_per_pixel =
7650 drm_format_plane_cpp(fourcc, 0) * 8;
7651
7652 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7653 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7654 offset = I915_READ(DSPOFFSET(plane));
7655 } else {
7656 if (plane_config->tiled)
7657 offset = I915_READ(DSPTILEOFF(plane));
7658 else
7659 offset = I915_READ(DSPLINOFF(plane));
7660 }
7661 plane_config->base = base;
7662
7663 val = I915_READ(PIPESRC(pipe));
7664 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7665 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7666
7667 val = I915_READ(DSPSTRIDE(pipe));
7668 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
7669
7670 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7671 plane_config->tiled);
7672
7673 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7674 aligned_height);
7675
7676 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7677 pipe, plane, crtc->base.primary->fb->width,
7678 crtc->base.primary->fb->height,
7679 crtc->base.primary->fb->bits_per_pixel, base,
7680 crtc->base.primary->fb->pitches[0],
7681 plane_config->size);
7682 }
7683
7684 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7685 struct intel_crtc_config *pipe_config)
7686 {
7687 struct drm_device *dev = crtc->base.dev;
7688 struct drm_i915_private *dev_priv = dev->dev_private;
7689 uint32_t tmp;
7690
7691 if (!intel_display_power_is_enabled(dev_priv,
7692 POWER_DOMAIN_PIPE(crtc->pipe)))
7693 return false;
7694
7695 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7696 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7697
7698 tmp = I915_READ(PIPECONF(crtc->pipe));
7699 if (!(tmp & PIPECONF_ENABLE))
7700 return false;
7701
7702 switch (tmp & PIPECONF_BPC_MASK) {
7703 case PIPECONF_6BPC:
7704 pipe_config->pipe_bpp = 18;
7705 break;
7706 case PIPECONF_8BPC:
7707 pipe_config->pipe_bpp = 24;
7708 break;
7709 case PIPECONF_10BPC:
7710 pipe_config->pipe_bpp = 30;
7711 break;
7712 case PIPECONF_12BPC:
7713 pipe_config->pipe_bpp = 36;
7714 break;
7715 default:
7716 break;
7717 }
7718
7719 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7720 pipe_config->limited_color_range = true;
7721
7722 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7723 struct intel_shared_dpll *pll;
7724
7725 pipe_config->has_pch_encoder = true;
7726
7727 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7728 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7729 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7730
7731 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7732
7733 if (HAS_PCH_IBX(dev_priv->dev)) {
7734 pipe_config->shared_dpll =
7735 (enum intel_dpll_id) crtc->pipe;
7736 } else {
7737 tmp = I915_READ(PCH_DPLL_SEL);
7738 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7739 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7740 else
7741 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7742 }
7743
7744 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7745
7746 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7747 &pipe_config->dpll_hw_state));
7748
7749 tmp = pipe_config->dpll_hw_state.dpll;
7750 pipe_config->pixel_multiplier =
7751 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7752 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7753
7754 ironlake_pch_clock_get(crtc, pipe_config);
7755 } else {
7756 pipe_config->pixel_multiplier = 1;
7757 }
7758
7759 intel_get_pipe_timings(crtc, pipe_config);
7760
7761 ironlake_get_pfit_config(crtc, pipe_config);
7762
7763 return true;
7764 }
7765
7766 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7767 {
7768 struct drm_device *dev = dev_priv->dev;
7769 struct intel_crtc *crtc;
7770
7771 for_each_intel_crtc(dev, crtc)
7772 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7773 pipe_name(crtc->pipe));
7774
7775 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7776 WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7777 WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7778 WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7779 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7780 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7781 "CPU PWM1 enabled\n");
7782 if (IS_HASWELL(dev))
7783 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7784 "CPU PWM2 enabled\n");
7785 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7786 "PCH PWM1 enabled\n");
7787 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7788 "Utility pin enabled\n");
7789 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7790
7791 /*
7792 * In theory we can still leave IRQs enabled, as long as only the HPD
7793 * interrupts remain enabled. We used to check for that, but since it's
7794 * gen-specific and since we only disable LCPLL after we fully disable
7795 * the interrupts, the check below should be enough.
7796 */
7797 WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7798 }
7799
7800 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7801 {
7802 struct drm_device *dev = dev_priv->dev;
7803
7804 if (IS_HASWELL(dev))
7805 return I915_READ(D_COMP_HSW);
7806 else
7807 return I915_READ(D_COMP_BDW);
7808 }
7809
7810 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7811 {
7812 struct drm_device *dev = dev_priv->dev;
7813
7814 if (IS_HASWELL(dev)) {
7815 mutex_lock(&dev_priv->rps.hw_lock);
7816 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7817 val))
7818 DRM_ERROR("Failed to write to D_COMP\n");
7819 mutex_unlock(&dev_priv->rps.hw_lock);
7820 } else {
7821 I915_WRITE(D_COMP_BDW, val);
7822 POSTING_READ(D_COMP_BDW);
7823 }
7824 }
7825
7826 /*
7827 * This function implements pieces of two sequences from BSpec:
7828 * - Sequence for display software to disable LCPLL
7829 * - Sequence for display software to allow package C8+
7830 * The steps implemented here are just the steps that actually touch the LCPLL
7831 * register. Callers should take care of disabling all the display engine
7832 * functions, doing the mode unset, fixing interrupts, etc.
7833 */
7834 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7835 bool switch_to_fclk, bool allow_power_down)
7836 {
7837 uint32_t val;
7838
7839 assert_can_disable_lcpll(dev_priv);
7840
7841 val = I915_READ(LCPLL_CTL);
7842
7843 if (switch_to_fclk) {
7844 val |= LCPLL_CD_SOURCE_FCLK;
7845 I915_WRITE(LCPLL_CTL, val);
7846
7847 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7848 LCPLL_CD_SOURCE_FCLK_DONE, 1))
7849 DRM_ERROR("Switching to FCLK failed\n");
7850
7851 val = I915_READ(LCPLL_CTL);
7852 }
7853
7854 val |= LCPLL_PLL_DISABLE;
7855 I915_WRITE(LCPLL_CTL, val);
7856 POSTING_READ(LCPLL_CTL);
7857
7858 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7859 DRM_ERROR("LCPLL still locked\n");
7860
7861 val = hsw_read_dcomp(dev_priv);
7862 val |= D_COMP_COMP_DISABLE;
7863 hsw_write_dcomp(dev_priv, val);
7864 ndelay(100);
7865
7866 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7867 1))
7868 DRM_ERROR("D_COMP RCOMP still in progress\n");
7869
7870 if (allow_power_down) {
7871 val = I915_READ(LCPLL_CTL);
7872 val |= LCPLL_POWER_DOWN_ALLOW;
7873 I915_WRITE(LCPLL_CTL, val);
7874 POSTING_READ(LCPLL_CTL);
7875 }
7876 }
7877
7878 /*
7879 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7880 * source.
7881 */
7882 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7883 {
7884 uint32_t val;
7885
7886 val = I915_READ(LCPLL_CTL);
7887
7888 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7889 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7890 return;
7891
7892 /*
7893 * Make sure we're not on PC8 state before disabling PC8, otherwise
7894 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7895 *
7896 * The other problem is that hsw_restore_lcpll() is called as part of
7897 * the runtime PM resume sequence, so we can't just call
7898 * gen6_gt_force_wake_get() because that function calls
7899 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7900 * while we are on the resume sequence. So to solve this problem we have
7901 * to call special forcewake code that doesn't touch runtime PM and
7902 * doesn't enable the forcewake delayed work.
7903 */
7904 spin_lock_irq(&dev_priv->uncore.lock);
7905 if (dev_priv->uncore.forcewake_count++ == 0)
7906 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7907 spin_unlock_irq(&dev_priv->uncore.lock);
7908
7909 if (val & LCPLL_POWER_DOWN_ALLOW) {
7910 val &= ~LCPLL_POWER_DOWN_ALLOW;
7911 I915_WRITE(LCPLL_CTL, val);
7912 POSTING_READ(LCPLL_CTL);
7913 }
7914
7915 val = hsw_read_dcomp(dev_priv);
7916 val |= D_COMP_COMP_FORCE;
7917 val &= ~D_COMP_COMP_DISABLE;
7918 hsw_write_dcomp(dev_priv, val);
7919
7920 val = I915_READ(LCPLL_CTL);
7921 val &= ~LCPLL_PLL_DISABLE;
7922 I915_WRITE(LCPLL_CTL, val);
7923
7924 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7925 DRM_ERROR("LCPLL not locked yet\n");
7926
7927 if (val & LCPLL_CD_SOURCE_FCLK) {
7928 val = I915_READ(LCPLL_CTL);
7929 val &= ~LCPLL_CD_SOURCE_FCLK;
7930 I915_WRITE(LCPLL_CTL, val);
7931
7932 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7933 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7934 DRM_ERROR("Switching back to LCPLL failed\n");
7935 }
7936
7937 /* See the big comment above. */
7938 spin_lock_irq(&dev_priv->uncore.lock);
7939 if (--dev_priv->uncore.forcewake_count == 0)
7940 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7941 spin_unlock_irq(&dev_priv->uncore.lock);
7942 }
7943
7944 /*
7945 * Package states C8 and deeper are really deep PC states that can only be
7946 * reached when all the devices on the system allow it, so even if the graphics
7947 * device allows PC8+, it doesn't mean the system will actually get to these
7948 * states. Our driver only allows PC8+ when going into runtime PM.
7949 *
7950 * The requirements for PC8+ are that all the outputs are disabled, the power
7951 * well is disabled and most interrupts are disabled, and these are also
7952 * requirements for runtime PM. When these conditions are met, we manually do
7953 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7954 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7955 * hang the machine.
7956 *
7957 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7958 * the state of some registers, so when we come back from PC8+ we need to
7959 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7960 * need to take care of the registers kept by RC6. Notice that this happens even
7961 * if we don't put the device in PCI D3 state (which is what currently happens
7962 * because of the runtime PM support).
7963 *
7964 * For more, read "Display Sequences for Package C8" on the hardware
7965 * documentation.
7966 */
7967 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7968 {
7969 struct drm_device *dev = dev_priv->dev;
7970 uint32_t val;
7971
7972 DRM_DEBUG_KMS("Enabling package C8+\n");
7973
7974 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7975 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7976 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7977 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7978 }
7979
7980 lpt_disable_clkout_dp(dev);
7981 hsw_disable_lcpll(dev_priv, true, true);
7982 }
7983
7984 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7985 {
7986 struct drm_device *dev = dev_priv->dev;
7987 uint32_t val;
7988
7989 DRM_DEBUG_KMS("Disabling package C8+\n");
7990
7991 hsw_restore_lcpll(dev_priv);
7992 lpt_init_pch_refclk(dev);
7993
7994 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7995 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7996 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7997 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7998 }
7999
8000 intel_prepare_ddi(dev);
8001 }
8002
8003 static int haswell_crtc_compute_clock(struct intel_crtc *crtc)
8004 {
8005 if (!intel_ddi_pll_select(crtc))
8006 return -EINVAL;
8007
8008 crtc->lowfreq_avail = false;
8009
8010 return 0;
8011 }
8012
8013 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8014 enum port port,
8015 struct intel_crtc_config *pipe_config)
8016 {
8017 u32 temp;
8018
8019 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8020 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
8021
8022 switch (pipe_config->ddi_pll_sel) {
8023 case SKL_DPLL1:
8024 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
8025 break;
8026 case SKL_DPLL2:
8027 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
8028 break;
8029 case SKL_DPLL3:
8030 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
8031 break;
8032 }
8033 }
8034
8035 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8036 enum port port,
8037 struct intel_crtc_config *pipe_config)
8038 {
8039 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8040
8041 switch (pipe_config->ddi_pll_sel) {
8042 case PORT_CLK_SEL_WRPLL1:
8043 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
8044 break;
8045 case PORT_CLK_SEL_WRPLL2:
8046 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
8047 break;
8048 }
8049 }
8050
8051 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
8052 struct intel_crtc_config *pipe_config)
8053 {
8054 struct drm_device *dev = crtc->base.dev;
8055 struct drm_i915_private *dev_priv = dev->dev_private;
8056 struct intel_shared_dpll *pll;
8057 enum port port;
8058 uint32_t tmp;
8059
8060 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
8061
8062 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8063
8064 if (IS_SKYLAKE(dev))
8065 skylake_get_ddi_pll(dev_priv, port, pipe_config);
8066 else
8067 haswell_get_ddi_pll(dev_priv, port, pipe_config);
8068
8069 if (pipe_config->shared_dpll >= 0) {
8070 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8071
8072 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8073 &pipe_config->dpll_hw_state));
8074 }
8075
8076 /*
8077 * Haswell has only FDI/PCH transcoder A. It is which is connected to
8078 * DDI E. So just check whether this pipe is wired to DDI E and whether
8079 * the PCH transcoder is on.
8080 */
8081 if (INTEL_INFO(dev)->gen < 9 &&
8082 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
8083 pipe_config->has_pch_encoder = true;
8084
8085 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8086 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8087 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8088
8089 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8090 }
8091 }
8092
8093 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
8094 struct intel_crtc_config *pipe_config)
8095 {
8096 struct drm_device *dev = crtc->base.dev;
8097 struct drm_i915_private *dev_priv = dev->dev_private;
8098 enum intel_display_power_domain pfit_domain;
8099 uint32_t tmp;
8100
8101 if (!intel_display_power_is_enabled(dev_priv,
8102 POWER_DOMAIN_PIPE(crtc->pipe)))
8103 return false;
8104
8105 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8106 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8107
8108 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8109 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8110 enum pipe trans_edp_pipe;
8111 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8112 default:
8113 WARN(1, "unknown pipe linked to edp transcoder\n");
8114 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8115 case TRANS_DDI_EDP_INPUT_A_ON:
8116 trans_edp_pipe = PIPE_A;
8117 break;
8118 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8119 trans_edp_pipe = PIPE_B;
8120 break;
8121 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8122 trans_edp_pipe = PIPE_C;
8123 break;
8124 }
8125
8126 if (trans_edp_pipe == crtc->pipe)
8127 pipe_config->cpu_transcoder = TRANSCODER_EDP;
8128 }
8129
8130 if (!intel_display_power_is_enabled(dev_priv,
8131 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
8132 return false;
8133
8134 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8135 if (!(tmp & PIPECONF_ENABLE))
8136 return false;
8137
8138 haswell_get_ddi_port_state(crtc, pipe_config);
8139
8140 intel_get_pipe_timings(crtc, pipe_config);
8141
8142 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
8143 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
8144 if (IS_SKYLAKE(dev))
8145 skylake_get_pfit_config(crtc, pipe_config);
8146 else
8147 ironlake_get_pfit_config(crtc, pipe_config);
8148 }
8149
8150 if (IS_HASWELL(dev))
8151 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8152 (I915_READ(IPS_CTL) & IPS_ENABLE);
8153
8154 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8155 pipe_config->pixel_multiplier =
8156 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8157 } else {
8158 pipe_config->pixel_multiplier = 1;
8159 }
8160
8161 return true;
8162 }
8163
8164 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8165 {
8166 struct drm_device *dev = crtc->dev;
8167 struct drm_i915_private *dev_priv = dev->dev_private;
8168 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8169 uint32_t cntl = 0, size = 0;
8170
8171 if (base) {
8172 unsigned int width = intel_crtc->cursor_width;
8173 unsigned int height = intel_crtc->cursor_height;
8174 unsigned int stride = roundup_pow_of_two(width) * 4;
8175
8176 switch (stride) {
8177 default:
8178 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8179 width, stride);
8180 stride = 256;
8181 /* fallthrough */
8182 case 256:
8183 case 512:
8184 case 1024:
8185 case 2048:
8186 break;
8187 }
8188
8189 cntl |= CURSOR_ENABLE |
8190 CURSOR_GAMMA_ENABLE |
8191 CURSOR_FORMAT_ARGB |
8192 CURSOR_STRIDE(stride);
8193
8194 size = (height << 12) | width;
8195 }
8196
8197 if (intel_crtc->cursor_cntl != 0 &&
8198 (intel_crtc->cursor_base != base ||
8199 intel_crtc->cursor_size != size ||
8200 intel_crtc->cursor_cntl != cntl)) {
8201 /* On these chipsets we can only modify the base/size/stride
8202 * whilst the cursor is disabled.
8203 */
8204 I915_WRITE(_CURACNTR, 0);
8205 POSTING_READ(_CURACNTR);
8206 intel_crtc->cursor_cntl = 0;
8207 }
8208
8209 if (intel_crtc->cursor_base != base) {
8210 I915_WRITE(_CURABASE, base);
8211 intel_crtc->cursor_base = base;
8212 }
8213
8214 if (intel_crtc->cursor_size != size) {
8215 I915_WRITE(CURSIZE, size);
8216 intel_crtc->cursor_size = size;
8217 }
8218
8219 if (intel_crtc->cursor_cntl != cntl) {
8220 I915_WRITE(_CURACNTR, cntl);
8221 POSTING_READ(_CURACNTR);
8222 intel_crtc->cursor_cntl = cntl;
8223 }
8224 }
8225
8226 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8227 {
8228 struct drm_device *dev = crtc->dev;
8229 struct drm_i915_private *dev_priv = dev->dev_private;
8230 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8231 int pipe = intel_crtc->pipe;
8232 uint32_t cntl;
8233
8234 cntl = 0;
8235 if (base) {
8236 cntl = MCURSOR_GAMMA_ENABLE;
8237 switch (intel_crtc->cursor_width) {
8238 case 64:
8239 cntl |= CURSOR_MODE_64_ARGB_AX;
8240 break;
8241 case 128:
8242 cntl |= CURSOR_MODE_128_ARGB_AX;
8243 break;
8244 case 256:
8245 cntl |= CURSOR_MODE_256_ARGB_AX;
8246 break;
8247 default:
8248 WARN_ON(1);
8249 return;
8250 }
8251 cntl |= pipe << 28; /* Connect to correct pipe */
8252
8253 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8254 cntl |= CURSOR_PIPE_CSC_ENABLE;
8255 }
8256
8257 if (to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180))
8258 cntl |= CURSOR_ROTATE_180;
8259
8260 if (intel_crtc->cursor_cntl != cntl) {
8261 I915_WRITE(CURCNTR(pipe), cntl);
8262 POSTING_READ(CURCNTR(pipe));
8263 intel_crtc->cursor_cntl = cntl;
8264 }
8265
8266 /* and commit changes on next vblank */
8267 I915_WRITE(CURBASE(pipe), base);
8268 POSTING_READ(CURBASE(pipe));
8269
8270 intel_crtc->cursor_base = base;
8271 }
8272
8273 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8274 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8275 bool on)
8276 {
8277 struct drm_device *dev = crtc->dev;
8278 struct drm_i915_private *dev_priv = dev->dev_private;
8279 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8280 int pipe = intel_crtc->pipe;
8281 int x = crtc->cursor_x;
8282 int y = crtc->cursor_y;
8283 u32 base = 0, pos = 0;
8284
8285 if (on)
8286 base = intel_crtc->cursor_addr;
8287
8288 if (x >= intel_crtc->config.pipe_src_w)
8289 base = 0;
8290
8291 if (y >= intel_crtc->config.pipe_src_h)
8292 base = 0;
8293
8294 if (x < 0) {
8295 if (x + intel_crtc->cursor_width <= 0)
8296 base = 0;
8297
8298 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8299 x = -x;
8300 }
8301 pos |= x << CURSOR_X_SHIFT;
8302
8303 if (y < 0) {
8304 if (y + intel_crtc->cursor_height <= 0)
8305 base = 0;
8306
8307 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8308 y = -y;
8309 }
8310 pos |= y << CURSOR_Y_SHIFT;
8311
8312 if (base == 0 && intel_crtc->cursor_base == 0)
8313 return;
8314
8315 I915_WRITE(CURPOS(pipe), pos);
8316
8317 /* ILK+ do this automagically */
8318 if (HAS_GMCH_DISPLAY(dev) &&
8319 to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180)) {
8320 base += (intel_crtc->cursor_height *
8321 intel_crtc->cursor_width - 1) * 4;
8322 }
8323
8324 if (IS_845G(dev) || IS_I865G(dev))
8325 i845_update_cursor(crtc, base);
8326 else
8327 i9xx_update_cursor(crtc, base);
8328 }
8329
8330 static bool cursor_size_ok(struct drm_device *dev,
8331 uint32_t width, uint32_t height)
8332 {
8333 if (width == 0 || height == 0)
8334 return false;
8335
8336 /*
8337 * 845g/865g are special in that they are only limited by
8338 * the width of their cursors, the height is arbitrary up to
8339 * the precision of the register. Everything else requires
8340 * square cursors, limited to a few power-of-two sizes.
8341 */
8342 if (IS_845G(dev) || IS_I865G(dev)) {
8343 if ((width & 63) != 0)
8344 return false;
8345
8346 if (width > (IS_845G(dev) ? 64 : 512))
8347 return false;
8348
8349 if (height > 1023)
8350 return false;
8351 } else {
8352 switch (width | height) {
8353 case 256:
8354 case 128:
8355 if (IS_GEN2(dev))
8356 return false;
8357 case 64:
8358 break;
8359 default:
8360 return false;
8361 }
8362 }
8363
8364 return true;
8365 }
8366
8367 static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8368 struct drm_i915_gem_object *obj,
8369 uint32_t width, uint32_t height)
8370 {
8371 struct drm_device *dev = crtc->dev;
8372 struct drm_i915_private *dev_priv = dev->dev_private;
8373 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8374 enum pipe pipe = intel_crtc->pipe;
8375 unsigned old_width;
8376 uint32_t addr;
8377 int ret;
8378
8379 /* if we want to turn off the cursor ignore width and height */
8380 if (!obj) {
8381 DRM_DEBUG_KMS("cursor off\n");
8382 addr = 0;
8383 mutex_lock(&dev->struct_mutex);
8384 goto finish;
8385 }
8386
8387 /* we only need to pin inside GTT if cursor is non-phy */
8388 mutex_lock(&dev->struct_mutex);
8389 if (!INTEL_INFO(dev)->cursor_needs_physical) {
8390 unsigned alignment;
8391
8392 /*
8393 * Global gtt pte registers are special registers which actually
8394 * forward writes to a chunk of system memory. Which means that
8395 * there is no risk that the register values disappear as soon
8396 * as we call intel_runtime_pm_put(), so it is correct to wrap
8397 * only the pin/unpin/fence and not more.
8398 */
8399 intel_runtime_pm_get(dev_priv);
8400
8401 /* Note that the w/a also requires 2 PTE of padding following
8402 * the bo. We currently fill all unused PTE with the shadow
8403 * page and so we should always have valid PTE following the
8404 * cursor preventing the VT-d warning.
8405 */
8406 alignment = 0;
8407 if (need_vtd_wa(dev))
8408 alignment = 64*1024;
8409
8410 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8411 if (ret) {
8412 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8413 intel_runtime_pm_put(dev_priv);
8414 goto fail_locked;
8415 }
8416
8417 ret = i915_gem_object_put_fence(obj);
8418 if (ret) {
8419 DRM_DEBUG_KMS("failed to release fence for cursor");
8420 intel_runtime_pm_put(dev_priv);
8421 goto fail_unpin;
8422 }
8423
8424 addr = i915_gem_obj_ggtt_offset(obj);
8425
8426 intel_runtime_pm_put(dev_priv);
8427 } else {
8428 int align = IS_I830(dev) ? 16 * 1024 : 256;
8429 ret = i915_gem_object_attach_phys(obj, align);
8430 if (ret) {
8431 DRM_DEBUG_KMS("failed to attach phys object\n");
8432 goto fail_locked;
8433 }
8434 addr = obj->phys_handle->busaddr;
8435 }
8436
8437 finish:
8438 if (intel_crtc->cursor_bo) {
8439 if (!INTEL_INFO(dev)->cursor_needs_physical)
8440 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8441 }
8442
8443 i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8444 INTEL_FRONTBUFFER_CURSOR(pipe));
8445 mutex_unlock(&dev->struct_mutex);
8446
8447 old_width = intel_crtc->cursor_width;
8448
8449 intel_crtc->cursor_addr = addr;
8450 intel_crtc->cursor_bo = obj;
8451 intel_crtc->cursor_width = width;
8452 intel_crtc->cursor_height = height;
8453
8454 if (intel_crtc->active) {
8455 if (old_width != width)
8456 intel_update_watermarks(crtc);
8457 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8458
8459 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
8460 }
8461
8462 return 0;
8463 fail_unpin:
8464 i915_gem_object_unpin_from_display_plane(obj);
8465 fail_locked:
8466 mutex_unlock(&dev->struct_mutex);
8467 return ret;
8468 }
8469
8470 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8471 u16 *blue, uint32_t start, uint32_t size)
8472 {
8473 int end = (start + size > 256) ? 256 : start + size, i;
8474 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8475
8476 for (i = start; i < end; i++) {
8477 intel_crtc->lut_r[i] = red[i] >> 8;
8478 intel_crtc->lut_g[i] = green[i] >> 8;
8479 intel_crtc->lut_b[i] = blue[i] >> 8;
8480 }
8481
8482 intel_crtc_load_lut(crtc);
8483 }
8484
8485 /* VESA 640x480x72Hz mode to set on the pipe */
8486 static struct drm_display_mode load_detect_mode = {
8487 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8488 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8489 };
8490
8491 struct drm_framebuffer *
8492 __intel_framebuffer_create(struct drm_device *dev,
8493 struct drm_mode_fb_cmd2 *mode_cmd,
8494 struct drm_i915_gem_object *obj)
8495 {
8496 struct intel_framebuffer *intel_fb;
8497 int ret;
8498
8499 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8500 if (!intel_fb) {
8501 drm_gem_object_unreference(&obj->base);
8502 return ERR_PTR(-ENOMEM);
8503 }
8504
8505 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8506 if (ret)
8507 goto err;
8508
8509 return &intel_fb->base;
8510 err:
8511 drm_gem_object_unreference(&obj->base);
8512 kfree(intel_fb);
8513
8514 return ERR_PTR(ret);
8515 }
8516
8517 static struct drm_framebuffer *
8518 intel_framebuffer_create(struct drm_device *dev,
8519 struct drm_mode_fb_cmd2 *mode_cmd,
8520 struct drm_i915_gem_object *obj)
8521 {
8522 struct drm_framebuffer *fb;
8523 int ret;
8524
8525 ret = i915_mutex_lock_interruptible(dev);
8526 if (ret)
8527 return ERR_PTR(ret);
8528 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8529 mutex_unlock(&dev->struct_mutex);
8530
8531 return fb;
8532 }
8533
8534 static u32
8535 intel_framebuffer_pitch_for_width(int width, int bpp)
8536 {
8537 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8538 return ALIGN(pitch, 64);
8539 }
8540
8541 static u32
8542 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8543 {
8544 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8545 return PAGE_ALIGN(pitch * mode->vdisplay);
8546 }
8547
8548 static struct drm_framebuffer *
8549 intel_framebuffer_create_for_mode(struct drm_device *dev,
8550 struct drm_display_mode *mode,
8551 int depth, int bpp)
8552 {
8553 struct drm_i915_gem_object *obj;
8554 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8555
8556 obj = i915_gem_alloc_object(dev,
8557 intel_framebuffer_size_for_mode(mode, bpp));
8558 if (obj == NULL)
8559 return ERR_PTR(-ENOMEM);
8560
8561 mode_cmd.width = mode->hdisplay;
8562 mode_cmd.height = mode->vdisplay;
8563 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8564 bpp);
8565 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8566
8567 return intel_framebuffer_create(dev, &mode_cmd, obj);
8568 }
8569
8570 static struct drm_framebuffer *
8571 mode_fits_in_fbdev(struct drm_device *dev,
8572 struct drm_display_mode *mode)
8573 {
8574 #ifdef CONFIG_DRM_I915_FBDEV
8575 struct drm_i915_private *dev_priv = dev->dev_private;
8576 struct drm_i915_gem_object *obj;
8577 struct drm_framebuffer *fb;
8578
8579 if (!dev_priv->fbdev)
8580 return NULL;
8581
8582 if (!dev_priv->fbdev->fb)
8583 return NULL;
8584
8585 obj = dev_priv->fbdev->fb->obj;
8586 BUG_ON(!obj);
8587
8588 fb = &dev_priv->fbdev->fb->base;
8589 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8590 fb->bits_per_pixel))
8591 return NULL;
8592
8593 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8594 return NULL;
8595
8596 return fb;
8597 #else
8598 return NULL;
8599 #endif
8600 }
8601
8602 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8603 struct drm_display_mode *mode,
8604 struct intel_load_detect_pipe *old,
8605 struct drm_modeset_acquire_ctx *ctx)
8606 {
8607 struct intel_crtc *intel_crtc;
8608 struct intel_encoder *intel_encoder =
8609 intel_attached_encoder(connector);
8610 struct drm_crtc *possible_crtc;
8611 struct drm_encoder *encoder = &intel_encoder->base;
8612 struct drm_crtc *crtc = NULL;
8613 struct drm_device *dev = encoder->dev;
8614 struct drm_framebuffer *fb;
8615 struct drm_mode_config *config = &dev->mode_config;
8616 int ret, i = -1;
8617
8618 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8619 connector->base.id, connector->name,
8620 encoder->base.id, encoder->name);
8621
8622 retry:
8623 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8624 if (ret)
8625 goto fail_unlock;
8626
8627 /*
8628 * Algorithm gets a little messy:
8629 *
8630 * - if the connector already has an assigned crtc, use it (but make
8631 * sure it's on first)
8632 *
8633 * - try to find the first unused crtc that can drive this connector,
8634 * and use that if we find one
8635 */
8636
8637 /* See if we already have a CRTC for this connector */
8638 if (encoder->crtc) {
8639 crtc = encoder->crtc;
8640
8641 ret = drm_modeset_lock(&crtc->mutex, ctx);
8642 if (ret)
8643 goto fail_unlock;
8644
8645 old->dpms_mode = connector->dpms;
8646 old->load_detect_temp = false;
8647
8648 /* Make sure the crtc and connector are running */
8649 if (connector->dpms != DRM_MODE_DPMS_ON)
8650 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8651
8652 return true;
8653 }
8654
8655 /* Find an unused one (if possible) */
8656 for_each_crtc(dev, possible_crtc) {
8657 i++;
8658 if (!(encoder->possible_crtcs & (1 << i)))
8659 continue;
8660 if (possible_crtc->enabled)
8661 continue;
8662 /* This can occur when applying the pipe A quirk on resume. */
8663 if (to_intel_crtc(possible_crtc)->new_enabled)
8664 continue;
8665
8666 crtc = possible_crtc;
8667 break;
8668 }
8669
8670 /*
8671 * If we didn't find an unused CRTC, don't use any.
8672 */
8673 if (!crtc) {
8674 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8675 goto fail_unlock;
8676 }
8677
8678 ret = drm_modeset_lock(&crtc->mutex, ctx);
8679 if (ret)
8680 goto fail_unlock;
8681 intel_encoder->new_crtc = to_intel_crtc(crtc);
8682 to_intel_connector(connector)->new_encoder = intel_encoder;
8683
8684 intel_crtc = to_intel_crtc(crtc);
8685 intel_crtc->new_enabled = true;
8686 intel_crtc->new_config = &intel_crtc->config;
8687 old->dpms_mode = connector->dpms;
8688 old->load_detect_temp = true;
8689 old->release_fb = NULL;
8690
8691 if (!mode)
8692 mode = &load_detect_mode;
8693
8694 /* We need a framebuffer large enough to accommodate all accesses
8695 * that the plane may generate whilst we perform load detection.
8696 * We can not rely on the fbcon either being present (we get called
8697 * during its initialisation to detect all boot displays, or it may
8698 * not even exist) or that it is large enough to satisfy the
8699 * requested mode.
8700 */
8701 fb = mode_fits_in_fbdev(dev, mode);
8702 if (fb == NULL) {
8703 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8704 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8705 old->release_fb = fb;
8706 } else
8707 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8708 if (IS_ERR(fb)) {
8709 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8710 goto fail;
8711 }
8712
8713 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8714 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8715 if (old->release_fb)
8716 old->release_fb->funcs->destroy(old->release_fb);
8717 goto fail;
8718 }
8719
8720 /* let the connector get through one full cycle before testing */
8721 intel_wait_for_vblank(dev, intel_crtc->pipe);
8722 return true;
8723
8724 fail:
8725 intel_crtc->new_enabled = crtc->enabled;
8726 if (intel_crtc->new_enabled)
8727 intel_crtc->new_config = &intel_crtc->config;
8728 else
8729 intel_crtc->new_config = NULL;
8730 fail_unlock:
8731 if (ret == -EDEADLK) {
8732 drm_modeset_backoff(ctx);
8733 goto retry;
8734 }
8735
8736 return false;
8737 }
8738
8739 void intel_release_load_detect_pipe(struct drm_connector *connector,
8740 struct intel_load_detect_pipe *old)
8741 {
8742 struct intel_encoder *intel_encoder =
8743 intel_attached_encoder(connector);
8744 struct drm_encoder *encoder = &intel_encoder->base;
8745 struct drm_crtc *crtc = encoder->crtc;
8746 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8747
8748 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8749 connector->base.id, connector->name,
8750 encoder->base.id, encoder->name);
8751
8752 if (old->load_detect_temp) {
8753 to_intel_connector(connector)->new_encoder = NULL;
8754 intel_encoder->new_crtc = NULL;
8755 intel_crtc->new_enabled = false;
8756 intel_crtc->new_config = NULL;
8757 intel_set_mode(crtc, NULL, 0, 0, NULL);
8758
8759 if (old->release_fb) {
8760 drm_framebuffer_unregister_private(old->release_fb);
8761 drm_framebuffer_unreference(old->release_fb);
8762 }
8763
8764 return;
8765 }
8766
8767 /* Switch crtc and encoder back off if necessary */
8768 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8769 connector->funcs->dpms(connector, old->dpms_mode);
8770 }
8771
8772 static int i9xx_pll_refclk(struct drm_device *dev,
8773 const struct intel_crtc_config *pipe_config)
8774 {
8775 struct drm_i915_private *dev_priv = dev->dev_private;
8776 u32 dpll = pipe_config->dpll_hw_state.dpll;
8777
8778 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8779 return dev_priv->vbt.lvds_ssc_freq;
8780 else if (HAS_PCH_SPLIT(dev))
8781 return 120000;
8782 else if (!IS_GEN2(dev))
8783 return 96000;
8784 else
8785 return 48000;
8786 }
8787
8788 /* Returns the clock of the currently programmed mode of the given pipe. */
8789 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8790 struct intel_crtc_config *pipe_config)
8791 {
8792 struct drm_device *dev = crtc->base.dev;
8793 struct drm_i915_private *dev_priv = dev->dev_private;
8794 int pipe = pipe_config->cpu_transcoder;
8795 u32 dpll = pipe_config->dpll_hw_state.dpll;
8796 u32 fp;
8797 intel_clock_t clock;
8798 int refclk = i9xx_pll_refclk(dev, pipe_config);
8799
8800 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8801 fp = pipe_config->dpll_hw_state.fp0;
8802 else
8803 fp = pipe_config->dpll_hw_state.fp1;
8804
8805 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8806 if (IS_PINEVIEW(dev)) {
8807 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8808 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8809 } else {
8810 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8811 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8812 }
8813
8814 if (!IS_GEN2(dev)) {
8815 if (IS_PINEVIEW(dev))
8816 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8817 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8818 else
8819 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8820 DPLL_FPA01_P1_POST_DIV_SHIFT);
8821
8822 switch (dpll & DPLL_MODE_MASK) {
8823 case DPLLB_MODE_DAC_SERIAL:
8824 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8825 5 : 10;
8826 break;
8827 case DPLLB_MODE_LVDS:
8828 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8829 7 : 14;
8830 break;
8831 default:
8832 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8833 "mode\n", (int)(dpll & DPLL_MODE_MASK));
8834 return;
8835 }
8836
8837 if (IS_PINEVIEW(dev))
8838 pineview_clock(refclk, &clock);
8839 else
8840 i9xx_clock(refclk, &clock);
8841 } else {
8842 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8843 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8844
8845 if (is_lvds) {
8846 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8847 DPLL_FPA01_P1_POST_DIV_SHIFT);
8848
8849 if (lvds & LVDS_CLKB_POWER_UP)
8850 clock.p2 = 7;
8851 else
8852 clock.p2 = 14;
8853 } else {
8854 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8855 clock.p1 = 2;
8856 else {
8857 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8858 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8859 }
8860 if (dpll & PLL_P2_DIVIDE_BY_4)
8861 clock.p2 = 4;
8862 else
8863 clock.p2 = 2;
8864 }
8865
8866 i9xx_clock(refclk, &clock);
8867 }
8868
8869 /*
8870 * This value includes pixel_multiplier. We will use
8871 * port_clock to compute adjusted_mode.crtc_clock in the
8872 * encoder's get_config() function.
8873 */
8874 pipe_config->port_clock = clock.dot;
8875 }
8876
8877 int intel_dotclock_calculate(int link_freq,
8878 const struct intel_link_m_n *m_n)
8879 {
8880 /*
8881 * The calculation for the data clock is:
8882 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8883 * But we want to avoid losing precison if possible, so:
8884 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8885 *
8886 * and the link clock is simpler:
8887 * link_clock = (m * link_clock) / n
8888 */
8889
8890 if (!m_n->link_n)
8891 return 0;
8892
8893 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8894 }
8895
8896 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8897 struct intel_crtc_config *pipe_config)
8898 {
8899 struct drm_device *dev = crtc->base.dev;
8900
8901 /* read out port_clock from the DPLL */
8902 i9xx_crtc_clock_get(crtc, pipe_config);
8903
8904 /*
8905 * This value does not include pixel_multiplier.
8906 * We will check that port_clock and adjusted_mode.crtc_clock
8907 * agree once we know their relationship in the encoder's
8908 * get_config() function.
8909 */
8910 pipe_config->adjusted_mode.crtc_clock =
8911 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8912 &pipe_config->fdi_m_n);
8913 }
8914
8915 /** Returns the currently programmed mode of the given pipe. */
8916 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8917 struct drm_crtc *crtc)
8918 {
8919 struct drm_i915_private *dev_priv = dev->dev_private;
8920 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8921 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8922 struct drm_display_mode *mode;
8923 struct intel_crtc_config pipe_config;
8924 int htot = I915_READ(HTOTAL(cpu_transcoder));
8925 int hsync = I915_READ(HSYNC(cpu_transcoder));
8926 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8927 int vsync = I915_READ(VSYNC(cpu_transcoder));
8928 enum pipe pipe = intel_crtc->pipe;
8929
8930 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8931 if (!mode)
8932 return NULL;
8933
8934 /*
8935 * Construct a pipe_config sufficient for getting the clock info
8936 * back out of crtc_clock_get.
8937 *
8938 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8939 * to use a real value here instead.
8940 */
8941 pipe_config.cpu_transcoder = (enum transcoder) pipe;
8942 pipe_config.pixel_multiplier = 1;
8943 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8944 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8945 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8946 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8947
8948 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8949 mode->hdisplay = (htot & 0xffff) + 1;
8950 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8951 mode->hsync_start = (hsync & 0xffff) + 1;
8952 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8953 mode->vdisplay = (vtot & 0xffff) + 1;
8954 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8955 mode->vsync_start = (vsync & 0xffff) + 1;
8956 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8957
8958 drm_mode_set_name(mode);
8959
8960 return mode;
8961 }
8962
8963 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8964 {
8965 struct drm_device *dev = crtc->dev;
8966 struct drm_i915_private *dev_priv = dev->dev_private;
8967 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8968
8969 if (!HAS_GMCH_DISPLAY(dev))
8970 return;
8971
8972 if (!dev_priv->lvds_downclock_avail)
8973 return;
8974
8975 /*
8976 * Since this is called by a timer, we should never get here in
8977 * the manual case.
8978 */
8979 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8980 int pipe = intel_crtc->pipe;
8981 int dpll_reg = DPLL(pipe);
8982 int dpll;
8983
8984 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8985
8986 assert_panel_unlocked(dev_priv, pipe);
8987
8988 dpll = I915_READ(dpll_reg);
8989 dpll |= DISPLAY_RATE_SELECT_FPA1;
8990 I915_WRITE(dpll_reg, dpll);
8991 intel_wait_for_vblank(dev, pipe);
8992 dpll = I915_READ(dpll_reg);
8993 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8994 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8995 }
8996
8997 }
8998
8999 void intel_mark_busy(struct drm_device *dev)
9000 {
9001 struct drm_i915_private *dev_priv = dev->dev_private;
9002
9003 if (dev_priv->mm.busy)
9004 return;
9005
9006 intel_runtime_pm_get(dev_priv);
9007 i915_update_gfx_val(dev_priv);
9008 dev_priv->mm.busy = true;
9009 }
9010
9011 void intel_mark_idle(struct drm_device *dev)
9012 {
9013 struct drm_i915_private *dev_priv = dev->dev_private;
9014 struct drm_crtc *crtc;
9015
9016 if (!dev_priv->mm.busy)
9017 return;
9018
9019 dev_priv->mm.busy = false;
9020
9021 if (!i915.powersave)
9022 goto out;
9023
9024 for_each_crtc(dev, crtc) {
9025 if (!crtc->primary->fb)
9026 continue;
9027
9028 intel_decrease_pllclock(crtc);
9029 }
9030
9031 if (INTEL_INFO(dev)->gen >= 6)
9032 gen6_rps_idle(dev->dev_private);
9033
9034 out:
9035 intel_runtime_pm_put(dev_priv);
9036 }
9037
9038 static void intel_crtc_destroy(struct drm_crtc *crtc)
9039 {
9040 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9041 struct drm_device *dev = crtc->dev;
9042 struct intel_unpin_work *work;
9043
9044 spin_lock_irq(&dev->event_lock);
9045 work = intel_crtc->unpin_work;
9046 intel_crtc->unpin_work = NULL;
9047 spin_unlock_irq(&dev->event_lock);
9048
9049 if (work) {
9050 cancel_work_sync(&work->work);
9051 kfree(work);
9052 }
9053
9054 drm_crtc_cleanup(crtc);
9055
9056 kfree(intel_crtc);
9057 }
9058
9059 static void intel_unpin_work_fn(struct work_struct *__work)
9060 {
9061 struct intel_unpin_work *work =
9062 container_of(__work, struct intel_unpin_work, work);
9063 struct drm_device *dev = work->crtc->dev;
9064 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9065
9066 mutex_lock(&dev->struct_mutex);
9067 intel_unpin_fb_obj(work->old_fb_obj);
9068 drm_gem_object_unreference(&work->pending_flip_obj->base);
9069 drm_gem_object_unreference(&work->old_fb_obj->base);
9070
9071 intel_update_fbc(dev);
9072 mutex_unlock(&dev->struct_mutex);
9073
9074 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9075
9076 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9077 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9078
9079 kfree(work);
9080 }
9081
9082 static void do_intel_finish_page_flip(struct drm_device *dev,
9083 struct drm_crtc *crtc)
9084 {
9085 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9086 struct intel_unpin_work *work;
9087 unsigned long flags;
9088
9089 /* Ignore early vblank irqs */
9090 if (intel_crtc == NULL)
9091 return;
9092
9093 /*
9094 * This is called both by irq handlers and the reset code (to complete
9095 * lost pageflips) so needs the full irqsave spinlocks.
9096 */
9097 spin_lock_irqsave(&dev->event_lock, flags);
9098 work = intel_crtc->unpin_work;
9099
9100 /* Ensure we don't miss a work->pending update ... */
9101 smp_rmb();
9102
9103 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9104 spin_unlock_irqrestore(&dev->event_lock, flags);
9105 return;
9106 }
9107
9108 page_flip_completed(intel_crtc);
9109
9110 spin_unlock_irqrestore(&dev->event_lock, flags);
9111 }
9112
9113 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9114 {
9115 struct drm_i915_private *dev_priv = dev->dev_private;
9116 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9117
9118 do_intel_finish_page_flip(dev, crtc);
9119 }
9120
9121 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9122 {
9123 struct drm_i915_private *dev_priv = dev->dev_private;
9124 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9125
9126 do_intel_finish_page_flip(dev, crtc);
9127 }
9128
9129 /* Is 'a' after or equal to 'b'? */
9130 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9131 {
9132 return !((a - b) & 0x80000000);
9133 }
9134
9135 static bool page_flip_finished(struct intel_crtc *crtc)
9136 {
9137 struct drm_device *dev = crtc->base.dev;
9138 struct drm_i915_private *dev_priv = dev->dev_private;
9139
9140 /*
9141 * The relevant registers doen't exist on pre-ctg.
9142 * As the flip done interrupt doesn't trigger for mmio
9143 * flips on gmch platforms, a flip count check isn't
9144 * really needed there. But since ctg has the registers,
9145 * include it in the check anyway.
9146 */
9147 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9148 return true;
9149
9150 /*
9151 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9152 * used the same base address. In that case the mmio flip might
9153 * have completed, but the CS hasn't even executed the flip yet.
9154 *
9155 * A flip count check isn't enough as the CS might have updated
9156 * the base address just after start of vblank, but before we
9157 * managed to process the interrupt. This means we'd complete the
9158 * CS flip too soon.
9159 *
9160 * Combining both checks should get us a good enough result. It may
9161 * still happen that the CS flip has been executed, but has not
9162 * yet actually completed. But in case the base address is the same
9163 * anyway, we don't really care.
9164 */
9165 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9166 crtc->unpin_work->gtt_offset &&
9167 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9168 crtc->unpin_work->flip_count);
9169 }
9170
9171 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9172 {
9173 struct drm_i915_private *dev_priv = dev->dev_private;
9174 struct intel_crtc *intel_crtc =
9175 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9176 unsigned long flags;
9177
9178
9179 /*
9180 * This is called both by irq handlers and the reset code (to complete
9181 * lost pageflips) so needs the full irqsave spinlocks.
9182 *
9183 * NB: An MMIO update of the plane base pointer will also
9184 * generate a page-flip completion irq, i.e. every modeset
9185 * is also accompanied by a spurious intel_prepare_page_flip().
9186 */
9187 spin_lock_irqsave(&dev->event_lock, flags);
9188 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9189 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9190 spin_unlock_irqrestore(&dev->event_lock, flags);
9191 }
9192
9193 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9194 {
9195 /* Ensure that the work item is consistent when activating it ... */
9196 smp_wmb();
9197 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9198 /* and that it is marked active as soon as the irq could fire. */
9199 smp_wmb();
9200 }
9201
9202 static int intel_gen2_queue_flip(struct drm_device *dev,
9203 struct drm_crtc *crtc,
9204 struct drm_framebuffer *fb,
9205 struct drm_i915_gem_object *obj,
9206 struct intel_engine_cs *ring,
9207 uint32_t flags)
9208 {
9209 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9210 u32 flip_mask;
9211 int ret;
9212
9213 ret = intel_ring_begin(ring, 6);
9214 if (ret)
9215 return ret;
9216
9217 /* Can't queue multiple flips, so wait for the previous
9218 * one to finish before executing the next.
9219 */
9220 if (intel_crtc->plane)
9221 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9222 else
9223 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9224 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9225 intel_ring_emit(ring, MI_NOOP);
9226 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9227 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9228 intel_ring_emit(ring, fb->pitches[0]);
9229 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9230 intel_ring_emit(ring, 0); /* aux display base address, unused */
9231
9232 intel_mark_page_flip_active(intel_crtc);
9233 __intel_ring_advance(ring);
9234 return 0;
9235 }
9236
9237 static int intel_gen3_queue_flip(struct drm_device *dev,
9238 struct drm_crtc *crtc,
9239 struct drm_framebuffer *fb,
9240 struct drm_i915_gem_object *obj,
9241 struct intel_engine_cs *ring,
9242 uint32_t flags)
9243 {
9244 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9245 u32 flip_mask;
9246 int ret;
9247
9248 ret = intel_ring_begin(ring, 6);
9249 if (ret)
9250 return ret;
9251
9252 if (intel_crtc->plane)
9253 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9254 else
9255 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9256 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9257 intel_ring_emit(ring, MI_NOOP);
9258 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9259 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9260 intel_ring_emit(ring, fb->pitches[0]);
9261 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9262 intel_ring_emit(ring, MI_NOOP);
9263
9264 intel_mark_page_flip_active(intel_crtc);
9265 __intel_ring_advance(ring);
9266 return 0;
9267 }
9268
9269 static int intel_gen4_queue_flip(struct drm_device *dev,
9270 struct drm_crtc *crtc,
9271 struct drm_framebuffer *fb,
9272 struct drm_i915_gem_object *obj,
9273 struct intel_engine_cs *ring,
9274 uint32_t flags)
9275 {
9276 struct drm_i915_private *dev_priv = dev->dev_private;
9277 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9278 uint32_t pf, pipesrc;
9279 int ret;
9280
9281 ret = intel_ring_begin(ring, 4);
9282 if (ret)
9283 return ret;
9284
9285 /* i965+ uses the linear or tiled offsets from the
9286 * Display Registers (which do not change across a page-flip)
9287 * so we need only reprogram the base address.
9288 */
9289 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9290 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9291 intel_ring_emit(ring, fb->pitches[0]);
9292 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9293 obj->tiling_mode);
9294
9295 /* XXX Enabling the panel-fitter across page-flip is so far
9296 * untested on non-native modes, so ignore it for now.
9297 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9298 */
9299 pf = 0;
9300 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9301 intel_ring_emit(ring, pf | pipesrc);
9302
9303 intel_mark_page_flip_active(intel_crtc);
9304 __intel_ring_advance(ring);
9305 return 0;
9306 }
9307
9308 static int intel_gen6_queue_flip(struct drm_device *dev,
9309 struct drm_crtc *crtc,
9310 struct drm_framebuffer *fb,
9311 struct drm_i915_gem_object *obj,
9312 struct intel_engine_cs *ring,
9313 uint32_t flags)
9314 {
9315 struct drm_i915_private *dev_priv = dev->dev_private;
9316 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9317 uint32_t pf, pipesrc;
9318 int ret;
9319
9320 ret = intel_ring_begin(ring, 4);
9321 if (ret)
9322 return ret;
9323
9324 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9325 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9326 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9327 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9328
9329 /* Contrary to the suggestions in the documentation,
9330 * "Enable Panel Fitter" does not seem to be required when page
9331 * flipping with a non-native mode, and worse causes a normal
9332 * modeset to fail.
9333 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9334 */
9335 pf = 0;
9336 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9337 intel_ring_emit(ring, pf | pipesrc);
9338
9339 intel_mark_page_flip_active(intel_crtc);
9340 __intel_ring_advance(ring);
9341 return 0;
9342 }
9343
9344 static int intel_gen7_queue_flip(struct drm_device *dev,
9345 struct drm_crtc *crtc,
9346 struct drm_framebuffer *fb,
9347 struct drm_i915_gem_object *obj,
9348 struct intel_engine_cs *ring,
9349 uint32_t flags)
9350 {
9351 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9352 uint32_t plane_bit = 0;
9353 int len, ret;
9354
9355 switch (intel_crtc->plane) {
9356 case PLANE_A:
9357 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9358 break;
9359 case PLANE_B:
9360 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9361 break;
9362 case PLANE_C:
9363 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9364 break;
9365 default:
9366 WARN_ONCE(1, "unknown plane in flip command\n");
9367 return -ENODEV;
9368 }
9369
9370 len = 4;
9371 if (ring->id == RCS) {
9372 len += 6;
9373 /*
9374 * On Gen 8, SRM is now taking an extra dword to accommodate
9375 * 48bits addresses, and we need a NOOP for the batch size to
9376 * stay even.
9377 */
9378 if (IS_GEN8(dev))
9379 len += 2;
9380 }
9381
9382 /*
9383 * BSpec MI_DISPLAY_FLIP for IVB:
9384 * "The full packet must be contained within the same cache line."
9385 *
9386 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9387 * cacheline, if we ever start emitting more commands before
9388 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9389 * then do the cacheline alignment, and finally emit the
9390 * MI_DISPLAY_FLIP.
9391 */
9392 ret = intel_ring_cacheline_align(ring);
9393 if (ret)
9394 return ret;
9395
9396 ret = intel_ring_begin(ring, len);
9397 if (ret)
9398 return ret;
9399
9400 /* Unmask the flip-done completion message. Note that the bspec says that
9401 * we should do this for both the BCS and RCS, and that we must not unmask
9402 * more than one flip event at any time (or ensure that one flip message
9403 * can be sent by waiting for flip-done prior to queueing new flips).
9404 * Experimentation says that BCS works despite DERRMR masking all
9405 * flip-done completion events and that unmasking all planes at once
9406 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9407 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9408 */
9409 if (ring->id == RCS) {
9410 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9411 intel_ring_emit(ring, DERRMR);
9412 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9413 DERRMR_PIPEB_PRI_FLIP_DONE |
9414 DERRMR_PIPEC_PRI_FLIP_DONE));
9415 if (IS_GEN8(dev))
9416 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9417 MI_SRM_LRM_GLOBAL_GTT);
9418 else
9419 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9420 MI_SRM_LRM_GLOBAL_GTT);
9421 intel_ring_emit(ring, DERRMR);
9422 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9423 if (IS_GEN8(dev)) {
9424 intel_ring_emit(ring, 0);
9425 intel_ring_emit(ring, MI_NOOP);
9426 }
9427 }
9428
9429 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9430 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9431 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9432 intel_ring_emit(ring, (MI_NOOP));
9433
9434 intel_mark_page_flip_active(intel_crtc);
9435 __intel_ring_advance(ring);
9436 return 0;
9437 }
9438
9439 static bool use_mmio_flip(struct intel_engine_cs *ring,
9440 struct drm_i915_gem_object *obj)
9441 {
9442 /*
9443 * This is not being used for older platforms, because
9444 * non-availability of flip done interrupt forces us to use
9445 * CS flips. Older platforms derive flip done using some clever
9446 * tricks involving the flip_pending status bits and vblank irqs.
9447 * So using MMIO flips there would disrupt this mechanism.
9448 */
9449
9450 if (ring == NULL)
9451 return true;
9452
9453 if (INTEL_INFO(ring->dev)->gen < 5)
9454 return false;
9455
9456 if (i915.use_mmio_flip < 0)
9457 return false;
9458 else if (i915.use_mmio_flip > 0)
9459 return true;
9460 else if (i915.enable_execlists)
9461 return true;
9462 else
9463 return ring != obj->ring;
9464 }
9465
9466 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9467 {
9468 struct drm_device *dev = intel_crtc->base.dev;
9469 struct drm_i915_private *dev_priv = dev->dev_private;
9470 struct intel_framebuffer *intel_fb =
9471 to_intel_framebuffer(intel_crtc->base.primary->fb);
9472 struct drm_i915_gem_object *obj = intel_fb->obj;
9473 bool atomic_update;
9474 u32 start_vbl_count;
9475 u32 dspcntr;
9476 u32 reg;
9477
9478 intel_mark_page_flip_active(intel_crtc);
9479
9480 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
9481
9482 reg = DSPCNTR(intel_crtc->plane);
9483 dspcntr = I915_READ(reg);
9484
9485 if (obj->tiling_mode != I915_TILING_NONE)
9486 dspcntr |= DISPPLANE_TILED;
9487 else
9488 dspcntr &= ~DISPPLANE_TILED;
9489
9490 I915_WRITE(reg, dspcntr);
9491
9492 I915_WRITE(DSPSURF(intel_crtc->plane),
9493 intel_crtc->unpin_work->gtt_offset);
9494 POSTING_READ(DSPSURF(intel_crtc->plane));
9495
9496 if (atomic_update)
9497 intel_pipe_update_end(intel_crtc, start_vbl_count);
9498 }
9499
9500 static void intel_mmio_flip_work_func(struct work_struct *work)
9501 {
9502 struct intel_crtc *intel_crtc =
9503 container_of(work, struct intel_crtc, mmio_flip.work);
9504 struct intel_engine_cs *ring;
9505 uint32_t seqno;
9506
9507 seqno = intel_crtc->mmio_flip.seqno;
9508 ring = intel_crtc->mmio_flip.ring;
9509
9510 if (seqno)
9511 WARN_ON(__i915_wait_seqno(ring, seqno,
9512 intel_crtc->reset_counter,
9513 false, NULL, NULL) != 0);
9514
9515 intel_do_mmio_flip(intel_crtc);
9516 }
9517
9518 static int intel_queue_mmio_flip(struct drm_device *dev,
9519 struct drm_crtc *crtc,
9520 struct drm_framebuffer *fb,
9521 struct drm_i915_gem_object *obj,
9522 struct intel_engine_cs *ring,
9523 uint32_t flags)
9524 {
9525 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9526
9527 intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
9528 intel_crtc->mmio_flip.ring = obj->ring;
9529
9530 schedule_work(&intel_crtc->mmio_flip.work);
9531
9532 return 0;
9533 }
9534
9535 static int intel_gen9_queue_flip(struct drm_device *dev,
9536 struct drm_crtc *crtc,
9537 struct drm_framebuffer *fb,
9538 struct drm_i915_gem_object *obj,
9539 struct intel_engine_cs *ring,
9540 uint32_t flags)
9541 {
9542 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9543 uint32_t plane = 0, stride;
9544 int ret;
9545
9546 switch(intel_crtc->pipe) {
9547 case PIPE_A:
9548 plane = MI_DISPLAY_FLIP_SKL_PLANE_1_A;
9549 break;
9550 case PIPE_B:
9551 plane = MI_DISPLAY_FLIP_SKL_PLANE_1_B;
9552 break;
9553 case PIPE_C:
9554 plane = MI_DISPLAY_FLIP_SKL_PLANE_1_C;
9555 break;
9556 default:
9557 WARN_ONCE(1, "unknown plane in flip command\n");
9558 return -ENODEV;
9559 }
9560
9561 switch (obj->tiling_mode) {
9562 case I915_TILING_NONE:
9563 stride = fb->pitches[0] >> 6;
9564 break;
9565 case I915_TILING_X:
9566 stride = fb->pitches[0] >> 9;
9567 break;
9568 default:
9569 WARN_ONCE(1, "unknown tiling in flip command\n");
9570 return -ENODEV;
9571 }
9572
9573 ret = intel_ring_begin(ring, 10);
9574 if (ret)
9575 return ret;
9576
9577 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9578 intel_ring_emit(ring, DERRMR);
9579 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9580 DERRMR_PIPEB_PRI_FLIP_DONE |
9581 DERRMR_PIPEC_PRI_FLIP_DONE));
9582 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9583 MI_SRM_LRM_GLOBAL_GTT);
9584 intel_ring_emit(ring, DERRMR);
9585 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9586 intel_ring_emit(ring, 0);
9587
9588 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane);
9589 intel_ring_emit(ring, stride << 6 | obj->tiling_mode);
9590 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9591
9592 intel_mark_page_flip_active(intel_crtc);
9593 __intel_ring_advance(ring);
9594
9595 return 0;
9596 }
9597
9598 static int intel_default_queue_flip(struct drm_device *dev,
9599 struct drm_crtc *crtc,
9600 struct drm_framebuffer *fb,
9601 struct drm_i915_gem_object *obj,
9602 struct intel_engine_cs *ring,
9603 uint32_t flags)
9604 {
9605 return -ENODEV;
9606 }
9607
9608 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9609 struct drm_crtc *crtc)
9610 {
9611 struct drm_i915_private *dev_priv = dev->dev_private;
9612 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9613 struct intel_unpin_work *work = intel_crtc->unpin_work;
9614 u32 addr;
9615
9616 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9617 return true;
9618
9619 if (!work->enable_stall_check)
9620 return false;
9621
9622 if (work->flip_ready_vblank == 0) {
9623 if (work->flip_queued_ring &&
9624 !i915_seqno_passed(work->flip_queued_ring->get_seqno(work->flip_queued_ring, true),
9625 work->flip_queued_seqno))
9626 return false;
9627
9628 work->flip_ready_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9629 }
9630
9631 if (drm_vblank_count(dev, intel_crtc->pipe) - work->flip_ready_vblank < 3)
9632 return false;
9633
9634 /* Potential stall - if we see that the flip has happened,
9635 * assume a missed interrupt. */
9636 if (INTEL_INFO(dev)->gen >= 4)
9637 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9638 else
9639 addr = I915_READ(DSPADDR(intel_crtc->plane));
9640
9641 /* There is a potential issue here with a false positive after a flip
9642 * to the same address. We could address this by checking for a
9643 * non-incrementing frame counter.
9644 */
9645 return addr == work->gtt_offset;
9646 }
9647
9648 void intel_check_page_flip(struct drm_device *dev, int pipe)
9649 {
9650 struct drm_i915_private *dev_priv = dev->dev_private;
9651 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9652 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9653
9654 WARN_ON(!in_irq());
9655
9656 if (crtc == NULL)
9657 return;
9658
9659 spin_lock(&dev->event_lock);
9660 if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9661 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9662 intel_crtc->unpin_work->flip_queued_vblank, drm_vblank_count(dev, pipe));
9663 page_flip_completed(intel_crtc);
9664 }
9665 spin_unlock(&dev->event_lock);
9666 }
9667
9668 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9669 struct drm_framebuffer *fb,
9670 struct drm_pending_vblank_event *event,
9671 uint32_t page_flip_flags)
9672 {
9673 struct drm_device *dev = crtc->dev;
9674 struct drm_i915_private *dev_priv = dev->dev_private;
9675 struct drm_framebuffer *old_fb = crtc->primary->fb;
9676 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9677 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9678 enum pipe pipe = intel_crtc->pipe;
9679 struct intel_unpin_work *work;
9680 struct intel_engine_cs *ring;
9681 int ret;
9682
9683 /*
9684 * drm_mode_page_flip_ioctl() should already catch this, but double
9685 * check to be safe. In the future we may enable pageflipping from
9686 * a disabled primary plane.
9687 */
9688 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9689 return -EBUSY;
9690
9691 /* Can't change pixel format via MI display flips. */
9692 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9693 return -EINVAL;
9694
9695 /*
9696 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9697 * Note that pitch changes could also affect these register.
9698 */
9699 if (INTEL_INFO(dev)->gen > 3 &&
9700 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9701 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9702 return -EINVAL;
9703
9704 if (i915_terminally_wedged(&dev_priv->gpu_error))
9705 goto out_hang;
9706
9707 work = kzalloc(sizeof(*work), GFP_KERNEL);
9708 if (work == NULL)
9709 return -ENOMEM;
9710
9711 work->event = event;
9712 work->crtc = crtc;
9713 work->old_fb_obj = intel_fb_obj(old_fb);
9714 INIT_WORK(&work->work, intel_unpin_work_fn);
9715
9716 ret = drm_crtc_vblank_get(crtc);
9717 if (ret)
9718 goto free_work;
9719
9720 /* We borrow the event spin lock for protecting unpin_work */
9721 spin_lock_irq(&dev->event_lock);
9722 if (intel_crtc->unpin_work) {
9723 /* Before declaring the flip queue wedged, check if
9724 * the hardware completed the operation behind our backs.
9725 */
9726 if (__intel_pageflip_stall_check(dev, crtc)) {
9727 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9728 page_flip_completed(intel_crtc);
9729 } else {
9730 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9731 spin_unlock_irq(&dev->event_lock);
9732
9733 drm_crtc_vblank_put(crtc);
9734 kfree(work);
9735 return -EBUSY;
9736 }
9737 }
9738 intel_crtc->unpin_work = work;
9739 spin_unlock_irq(&dev->event_lock);
9740
9741 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9742 flush_workqueue(dev_priv->wq);
9743
9744 ret = i915_mutex_lock_interruptible(dev);
9745 if (ret)
9746 goto cleanup;
9747
9748 /* Reference the objects for the scheduled work. */
9749 drm_gem_object_reference(&work->old_fb_obj->base);
9750 drm_gem_object_reference(&obj->base);
9751
9752 crtc->primary->fb = fb;
9753
9754 work->pending_flip_obj = obj;
9755
9756 atomic_inc(&intel_crtc->unpin_work_count);
9757 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9758
9759 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9760 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9761
9762 if (IS_VALLEYVIEW(dev)) {
9763 ring = &dev_priv->ring[BCS];
9764 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9765 /* vlv: DISPLAY_FLIP fails to change tiling */
9766 ring = NULL;
9767 } else if (IS_IVYBRIDGE(dev)) {
9768 ring = &dev_priv->ring[BCS];
9769 } else if (INTEL_INFO(dev)->gen >= 7) {
9770 ring = obj->ring;
9771 if (ring == NULL || ring->id != RCS)
9772 ring = &dev_priv->ring[BCS];
9773 } else {
9774 ring = &dev_priv->ring[RCS];
9775 }
9776
9777 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, ring);
9778 if (ret)
9779 goto cleanup_pending;
9780
9781 work->gtt_offset =
9782 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9783
9784 if (use_mmio_flip(ring, obj)) {
9785 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9786 page_flip_flags);
9787 if (ret)
9788 goto cleanup_unpin;
9789
9790 work->flip_queued_seqno = obj->last_write_seqno;
9791 work->flip_queued_ring = obj->ring;
9792 } else {
9793 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9794 page_flip_flags);
9795 if (ret)
9796 goto cleanup_unpin;
9797
9798 work->flip_queued_seqno = intel_ring_get_seqno(ring);
9799 work->flip_queued_ring = ring;
9800 }
9801
9802 work->flip_queued_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9803 work->enable_stall_check = true;
9804
9805 i915_gem_track_fb(work->old_fb_obj, obj,
9806 INTEL_FRONTBUFFER_PRIMARY(pipe));
9807
9808 intel_disable_fbc(dev);
9809 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9810 mutex_unlock(&dev->struct_mutex);
9811
9812 trace_i915_flip_request(intel_crtc->plane, obj);
9813
9814 return 0;
9815
9816 cleanup_unpin:
9817 intel_unpin_fb_obj(obj);
9818 cleanup_pending:
9819 atomic_dec(&intel_crtc->unpin_work_count);
9820 crtc->primary->fb = old_fb;
9821 drm_gem_object_unreference(&work->old_fb_obj->base);
9822 drm_gem_object_unreference(&obj->base);
9823 mutex_unlock(&dev->struct_mutex);
9824
9825 cleanup:
9826 spin_lock_irq(&dev->event_lock);
9827 intel_crtc->unpin_work = NULL;
9828 spin_unlock_irq(&dev->event_lock);
9829
9830 drm_crtc_vblank_put(crtc);
9831 free_work:
9832 kfree(work);
9833
9834 if (ret == -EIO) {
9835 out_hang:
9836 intel_crtc_wait_for_pending_flips(crtc);
9837 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9838 if (ret == 0 && event) {
9839 spin_lock_irq(&dev->event_lock);
9840 drm_send_vblank_event(dev, pipe, event);
9841 spin_unlock_irq(&dev->event_lock);
9842 }
9843 }
9844 return ret;
9845 }
9846
9847 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9848 .mode_set_base_atomic = intel_pipe_set_base_atomic,
9849 .load_lut = intel_crtc_load_lut,
9850 };
9851
9852 /**
9853 * intel_modeset_update_staged_output_state
9854 *
9855 * Updates the staged output configuration state, e.g. after we've read out the
9856 * current hw state.
9857 */
9858 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9859 {
9860 struct intel_crtc *crtc;
9861 struct intel_encoder *encoder;
9862 struct intel_connector *connector;
9863
9864 list_for_each_entry(connector, &dev->mode_config.connector_list,
9865 base.head) {
9866 connector->new_encoder =
9867 to_intel_encoder(connector->base.encoder);
9868 }
9869
9870 for_each_intel_encoder(dev, encoder) {
9871 encoder->new_crtc =
9872 to_intel_crtc(encoder->base.crtc);
9873 }
9874
9875 for_each_intel_crtc(dev, crtc) {
9876 crtc->new_enabled = crtc->base.enabled;
9877
9878 if (crtc->new_enabled)
9879 crtc->new_config = &crtc->config;
9880 else
9881 crtc->new_config = NULL;
9882 }
9883 }
9884
9885 /**
9886 * intel_modeset_commit_output_state
9887 *
9888 * This function copies the stage display pipe configuration to the real one.
9889 */
9890 static void intel_modeset_commit_output_state(struct drm_device *dev)
9891 {
9892 struct intel_crtc *crtc;
9893 struct intel_encoder *encoder;
9894 struct intel_connector *connector;
9895
9896 list_for_each_entry(connector, &dev->mode_config.connector_list,
9897 base.head) {
9898 connector->base.encoder = &connector->new_encoder->base;
9899 }
9900
9901 for_each_intel_encoder(dev, encoder) {
9902 encoder->base.crtc = &encoder->new_crtc->base;
9903 }
9904
9905 for_each_intel_crtc(dev, crtc) {
9906 crtc->base.enabled = crtc->new_enabled;
9907 }
9908 }
9909
9910 static void
9911 connected_sink_compute_bpp(struct intel_connector *connector,
9912 struct intel_crtc_config *pipe_config)
9913 {
9914 int bpp = pipe_config->pipe_bpp;
9915
9916 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9917 connector->base.base.id,
9918 connector->base.name);
9919
9920 /* Don't use an invalid EDID bpc value */
9921 if (connector->base.display_info.bpc &&
9922 connector->base.display_info.bpc * 3 < bpp) {
9923 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9924 bpp, connector->base.display_info.bpc*3);
9925 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9926 }
9927
9928 /* Clamp bpp to 8 on screens without EDID 1.4 */
9929 if (connector->base.display_info.bpc == 0 && bpp > 24) {
9930 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9931 bpp);
9932 pipe_config->pipe_bpp = 24;
9933 }
9934 }
9935
9936 static int
9937 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9938 struct drm_framebuffer *fb,
9939 struct intel_crtc_config *pipe_config)
9940 {
9941 struct drm_device *dev = crtc->base.dev;
9942 struct intel_connector *connector;
9943 int bpp;
9944
9945 switch (fb->pixel_format) {
9946 case DRM_FORMAT_C8:
9947 bpp = 8*3; /* since we go through a colormap */
9948 break;
9949 case DRM_FORMAT_XRGB1555:
9950 case DRM_FORMAT_ARGB1555:
9951 /* checked in intel_framebuffer_init already */
9952 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9953 return -EINVAL;
9954 case DRM_FORMAT_RGB565:
9955 bpp = 6*3; /* min is 18bpp */
9956 break;
9957 case DRM_FORMAT_XBGR8888:
9958 case DRM_FORMAT_ABGR8888:
9959 /* checked in intel_framebuffer_init already */
9960 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9961 return -EINVAL;
9962 case DRM_FORMAT_XRGB8888:
9963 case DRM_FORMAT_ARGB8888:
9964 bpp = 8*3;
9965 break;
9966 case DRM_FORMAT_XRGB2101010:
9967 case DRM_FORMAT_ARGB2101010:
9968 case DRM_FORMAT_XBGR2101010:
9969 case DRM_FORMAT_ABGR2101010:
9970 /* checked in intel_framebuffer_init already */
9971 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9972 return -EINVAL;
9973 bpp = 10*3;
9974 break;
9975 /* TODO: gen4+ supports 16 bpc floating point, too. */
9976 default:
9977 DRM_DEBUG_KMS("unsupported depth\n");
9978 return -EINVAL;
9979 }
9980
9981 pipe_config->pipe_bpp = bpp;
9982
9983 /* Clamp display bpp to EDID value */
9984 list_for_each_entry(connector, &dev->mode_config.connector_list,
9985 base.head) {
9986 if (!connector->new_encoder ||
9987 connector->new_encoder->new_crtc != crtc)
9988 continue;
9989
9990 connected_sink_compute_bpp(connector, pipe_config);
9991 }
9992
9993 return bpp;
9994 }
9995
9996 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9997 {
9998 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9999 "type: 0x%x flags: 0x%x\n",
10000 mode->crtc_clock,
10001 mode->crtc_hdisplay, mode->crtc_hsync_start,
10002 mode->crtc_hsync_end, mode->crtc_htotal,
10003 mode->crtc_vdisplay, mode->crtc_vsync_start,
10004 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10005 }
10006
10007 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10008 struct intel_crtc_config *pipe_config,
10009 const char *context)
10010 {
10011 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10012 context, pipe_name(crtc->pipe));
10013
10014 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10015 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10016 pipe_config->pipe_bpp, pipe_config->dither);
10017 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10018 pipe_config->has_pch_encoder,
10019 pipe_config->fdi_lanes,
10020 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10021 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10022 pipe_config->fdi_m_n.tu);
10023 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10024 pipe_config->has_dp_encoder,
10025 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10026 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10027 pipe_config->dp_m_n.tu);
10028
10029 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10030 pipe_config->has_dp_encoder,
10031 pipe_config->dp_m2_n2.gmch_m,
10032 pipe_config->dp_m2_n2.gmch_n,
10033 pipe_config->dp_m2_n2.link_m,
10034 pipe_config->dp_m2_n2.link_n,
10035 pipe_config->dp_m2_n2.tu);
10036
10037 DRM_DEBUG_KMS("requested mode:\n");
10038 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
10039 DRM_DEBUG_KMS("adjusted mode:\n");
10040 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
10041 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
10042 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10043 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10044 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10045 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10046 pipe_config->gmch_pfit.control,
10047 pipe_config->gmch_pfit.pgm_ratios,
10048 pipe_config->gmch_pfit.lvds_border_bits);
10049 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10050 pipe_config->pch_pfit.pos,
10051 pipe_config->pch_pfit.size,
10052 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10053 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10054 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10055 }
10056
10057 static bool encoders_cloneable(const struct intel_encoder *a,
10058 const struct intel_encoder *b)
10059 {
10060 /* masks could be asymmetric, so check both ways */
10061 return a == b || (a->cloneable & (1 << b->type) &&
10062 b->cloneable & (1 << a->type));
10063 }
10064
10065 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10066 struct intel_encoder *encoder)
10067 {
10068 struct drm_device *dev = crtc->base.dev;
10069 struct intel_encoder *source_encoder;
10070
10071 for_each_intel_encoder(dev, source_encoder) {
10072 if (source_encoder->new_crtc != crtc)
10073 continue;
10074
10075 if (!encoders_cloneable(encoder, source_encoder))
10076 return false;
10077 }
10078
10079 return true;
10080 }
10081
10082 static bool check_encoder_cloning(struct intel_crtc *crtc)
10083 {
10084 struct drm_device *dev = crtc->base.dev;
10085 struct intel_encoder *encoder;
10086
10087 for_each_intel_encoder(dev, encoder) {
10088 if (encoder->new_crtc != crtc)
10089 continue;
10090
10091 if (!check_single_encoder_cloning(crtc, encoder))
10092 return false;
10093 }
10094
10095 return true;
10096 }
10097
10098 static struct intel_crtc_config *
10099 intel_modeset_pipe_config(struct drm_crtc *crtc,
10100 struct drm_framebuffer *fb,
10101 struct drm_display_mode *mode)
10102 {
10103 struct drm_device *dev = crtc->dev;
10104 struct intel_encoder *encoder;
10105 struct intel_crtc_config *pipe_config;
10106 int plane_bpp, ret = -EINVAL;
10107 bool retry = true;
10108
10109 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10110 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10111 return ERR_PTR(-EINVAL);
10112 }
10113
10114 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10115 if (!pipe_config)
10116 return ERR_PTR(-ENOMEM);
10117
10118 drm_mode_copy(&pipe_config->adjusted_mode, mode);
10119 drm_mode_copy(&pipe_config->requested_mode, mode);
10120
10121 pipe_config->cpu_transcoder =
10122 (enum transcoder) to_intel_crtc(crtc)->pipe;
10123 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10124
10125 /*
10126 * Sanitize sync polarity flags based on requested ones. If neither
10127 * positive or negative polarity is requested, treat this as meaning
10128 * negative polarity.
10129 */
10130 if (!(pipe_config->adjusted_mode.flags &
10131 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10132 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10133
10134 if (!(pipe_config->adjusted_mode.flags &
10135 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10136 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10137
10138 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10139 * plane pixel format and any sink constraints into account. Returns the
10140 * source plane bpp so that dithering can be selected on mismatches
10141 * after encoders and crtc also have had their say. */
10142 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10143 fb, pipe_config);
10144 if (plane_bpp < 0)
10145 goto fail;
10146
10147 /*
10148 * Determine the real pipe dimensions. Note that stereo modes can
10149 * increase the actual pipe size due to the frame doubling and
10150 * insertion of additional space for blanks between the frame. This
10151 * is stored in the crtc timings. We use the requested mode to do this
10152 * computation to clearly distinguish it from the adjusted mode, which
10153 * can be changed by the connectors in the below retry loop.
10154 */
10155 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
10156 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
10157 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
10158
10159 encoder_retry:
10160 /* Ensure the port clock defaults are reset when retrying. */
10161 pipe_config->port_clock = 0;
10162 pipe_config->pixel_multiplier = 1;
10163
10164 /* Fill in default crtc timings, allow encoders to overwrite them. */
10165 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
10166
10167 /* Pass our mode to the connectors and the CRTC to give them a chance to
10168 * adjust it according to limitations or connector properties, and also
10169 * a chance to reject the mode entirely.
10170 */
10171 for_each_intel_encoder(dev, encoder) {
10172
10173 if (&encoder->new_crtc->base != crtc)
10174 continue;
10175
10176 if (!(encoder->compute_config(encoder, pipe_config))) {
10177 DRM_DEBUG_KMS("Encoder config failure\n");
10178 goto fail;
10179 }
10180 }
10181
10182 /* Set default port clock if not overwritten by the encoder. Needs to be
10183 * done afterwards in case the encoder adjusts the mode. */
10184 if (!pipe_config->port_clock)
10185 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10186 * pipe_config->pixel_multiplier;
10187
10188 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10189 if (ret < 0) {
10190 DRM_DEBUG_KMS("CRTC fixup failed\n");
10191 goto fail;
10192 }
10193
10194 if (ret == RETRY) {
10195 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10196 ret = -EINVAL;
10197 goto fail;
10198 }
10199
10200 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10201 retry = false;
10202 goto encoder_retry;
10203 }
10204
10205 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10206 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10207 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10208
10209 return pipe_config;
10210 fail:
10211 kfree(pipe_config);
10212 return ERR_PTR(ret);
10213 }
10214
10215 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10216 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10217 static void
10218 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10219 unsigned *prepare_pipes, unsigned *disable_pipes)
10220 {
10221 struct intel_crtc *intel_crtc;
10222 struct drm_device *dev = crtc->dev;
10223 struct intel_encoder *encoder;
10224 struct intel_connector *connector;
10225 struct drm_crtc *tmp_crtc;
10226
10227 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10228
10229 /* Check which crtcs have changed outputs connected to them, these need
10230 * to be part of the prepare_pipes mask. We don't (yet) support global
10231 * modeset across multiple crtcs, so modeset_pipes will only have one
10232 * bit set at most. */
10233 list_for_each_entry(connector, &dev->mode_config.connector_list,
10234 base.head) {
10235 if (connector->base.encoder == &connector->new_encoder->base)
10236 continue;
10237
10238 if (connector->base.encoder) {
10239 tmp_crtc = connector->base.encoder->crtc;
10240
10241 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10242 }
10243
10244 if (connector->new_encoder)
10245 *prepare_pipes |=
10246 1 << connector->new_encoder->new_crtc->pipe;
10247 }
10248
10249 for_each_intel_encoder(dev, encoder) {
10250 if (encoder->base.crtc == &encoder->new_crtc->base)
10251 continue;
10252
10253 if (encoder->base.crtc) {
10254 tmp_crtc = encoder->base.crtc;
10255
10256 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10257 }
10258
10259 if (encoder->new_crtc)
10260 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10261 }
10262
10263 /* Check for pipes that will be enabled/disabled ... */
10264 for_each_intel_crtc(dev, intel_crtc) {
10265 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10266 continue;
10267
10268 if (!intel_crtc->new_enabled)
10269 *disable_pipes |= 1 << intel_crtc->pipe;
10270 else
10271 *prepare_pipes |= 1 << intel_crtc->pipe;
10272 }
10273
10274
10275 /* set_mode is also used to update properties on life display pipes. */
10276 intel_crtc = to_intel_crtc(crtc);
10277 if (intel_crtc->new_enabled)
10278 *prepare_pipes |= 1 << intel_crtc->pipe;
10279
10280 /*
10281 * For simplicity do a full modeset on any pipe where the output routing
10282 * changed. We could be more clever, but that would require us to be
10283 * more careful with calling the relevant encoder->mode_set functions.
10284 */
10285 if (*prepare_pipes)
10286 *modeset_pipes = *prepare_pipes;
10287
10288 /* ... and mask these out. */
10289 *modeset_pipes &= ~(*disable_pipes);
10290 *prepare_pipes &= ~(*disable_pipes);
10291
10292 /*
10293 * HACK: We don't (yet) fully support global modesets. intel_set_config
10294 * obies this rule, but the modeset restore mode of
10295 * intel_modeset_setup_hw_state does not.
10296 */
10297 *modeset_pipes &= 1 << intel_crtc->pipe;
10298 *prepare_pipes &= 1 << intel_crtc->pipe;
10299
10300 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10301 *modeset_pipes, *prepare_pipes, *disable_pipes);
10302 }
10303
10304 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10305 {
10306 struct drm_encoder *encoder;
10307 struct drm_device *dev = crtc->dev;
10308
10309 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10310 if (encoder->crtc == crtc)
10311 return true;
10312
10313 return false;
10314 }
10315
10316 static void
10317 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10318 {
10319 struct drm_i915_private *dev_priv = dev->dev_private;
10320 struct intel_encoder *intel_encoder;
10321 struct intel_crtc *intel_crtc;
10322 struct drm_connector *connector;
10323
10324 intel_shared_dpll_commit(dev_priv);
10325
10326 for_each_intel_encoder(dev, intel_encoder) {
10327 if (!intel_encoder->base.crtc)
10328 continue;
10329
10330 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10331
10332 if (prepare_pipes & (1 << intel_crtc->pipe))
10333 intel_encoder->connectors_active = false;
10334 }
10335
10336 intel_modeset_commit_output_state(dev);
10337
10338 /* Double check state. */
10339 for_each_intel_crtc(dev, intel_crtc) {
10340 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10341 WARN_ON(intel_crtc->new_config &&
10342 intel_crtc->new_config != &intel_crtc->config);
10343 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10344 }
10345
10346 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10347 if (!connector->encoder || !connector->encoder->crtc)
10348 continue;
10349
10350 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10351
10352 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10353 struct drm_property *dpms_property =
10354 dev->mode_config.dpms_property;
10355
10356 connector->dpms = DRM_MODE_DPMS_ON;
10357 drm_object_property_set_value(&connector->base,
10358 dpms_property,
10359 DRM_MODE_DPMS_ON);
10360
10361 intel_encoder = to_intel_encoder(connector->encoder);
10362 intel_encoder->connectors_active = true;
10363 }
10364 }
10365
10366 }
10367
10368 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10369 {
10370 int diff;
10371
10372 if (clock1 == clock2)
10373 return true;
10374
10375 if (!clock1 || !clock2)
10376 return false;
10377
10378 diff = abs(clock1 - clock2);
10379
10380 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10381 return true;
10382
10383 return false;
10384 }
10385
10386 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10387 list_for_each_entry((intel_crtc), \
10388 &(dev)->mode_config.crtc_list, \
10389 base.head) \
10390 if (mask & (1 <<(intel_crtc)->pipe))
10391
10392 static bool
10393 intel_pipe_config_compare(struct drm_device *dev,
10394 struct intel_crtc_config *current_config,
10395 struct intel_crtc_config *pipe_config)
10396 {
10397 #define PIPE_CONF_CHECK_X(name) \
10398 if (current_config->name != pipe_config->name) { \
10399 DRM_ERROR("mismatch in " #name " " \
10400 "(expected 0x%08x, found 0x%08x)\n", \
10401 current_config->name, \
10402 pipe_config->name); \
10403 return false; \
10404 }
10405
10406 #define PIPE_CONF_CHECK_I(name) \
10407 if (current_config->name != pipe_config->name) { \
10408 DRM_ERROR("mismatch in " #name " " \
10409 "(expected %i, found %i)\n", \
10410 current_config->name, \
10411 pipe_config->name); \
10412 return false; \
10413 }
10414
10415 /* This is required for BDW+ where there is only one set of registers for
10416 * switching between high and low RR.
10417 * This macro can be used whenever a comparison has to be made between one
10418 * hw state and multiple sw state variables.
10419 */
10420 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10421 if ((current_config->name != pipe_config->name) && \
10422 (current_config->alt_name != pipe_config->name)) { \
10423 DRM_ERROR("mismatch in " #name " " \
10424 "(expected %i or %i, found %i)\n", \
10425 current_config->name, \
10426 current_config->alt_name, \
10427 pipe_config->name); \
10428 return false; \
10429 }
10430
10431 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10432 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10433 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10434 "(expected %i, found %i)\n", \
10435 current_config->name & (mask), \
10436 pipe_config->name & (mask)); \
10437 return false; \
10438 }
10439
10440 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10441 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10442 DRM_ERROR("mismatch in " #name " " \
10443 "(expected %i, found %i)\n", \
10444 current_config->name, \
10445 pipe_config->name); \
10446 return false; \
10447 }
10448
10449 #define PIPE_CONF_QUIRK(quirk) \
10450 ((current_config->quirks | pipe_config->quirks) & (quirk))
10451
10452 PIPE_CONF_CHECK_I(cpu_transcoder);
10453
10454 PIPE_CONF_CHECK_I(has_pch_encoder);
10455 PIPE_CONF_CHECK_I(fdi_lanes);
10456 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10457 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10458 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10459 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10460 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10461
10462 PIPE_CONF_CHECK_I(has_dp_encoder);
10463
10464 if (INTEL_INFO(dev)->gen < 8) {
10465 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10466 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10467 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10468 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10469 PIPE_CONF_CHECK_I(dp_m_n.tu);
10470
10471 if (current_config->has_drrs) {
10472 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10473 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10474 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10475 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10476 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10477 }
10478 } else {
10479 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10480 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10481 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10482 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10483 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10484 }
10485
10486 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10487 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10488 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10489 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10490 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10491 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10492
10493 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10494 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10495 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10496 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10497 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10498 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10499
10500 PIPE_CONF_CHECK_I(pixel_multiplier);
10501 PIPE_CONF_CHECK_I(has_hdmi_sink);
10502 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10503 IS_VALLEYVIEW(dev))
10504 PIPE_CONF_CHECK_I(limited_color_range);
10505 PIPE_CONF_CHECK_I(has_infoframe);
10506
10507 PIPE_CONF_CHECK_I(has_audio);
10508
10509 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10510 DRM_MODE_FLAG_INTERLACE);
10511
10512 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10513 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10514 DRM_MODE_FLAG_PHSYNC);
10515 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10516 DRM_MODE_FLAG_NHSYNC);
10517 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10518 DRM_MODE_FLAG_PVSYNC);
10519 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10520 DRM_MODE_FLAG_NVSYNC);
10521 }
10522
10523 PIPE_CONF_CHECK_I(pipe_src_w);
10524 PIPE_CONF_CHECK_I(pipe_src_h);
10525
10526 /*
10527 * FIXME: BIOS likes to set up a cloned config with lvds+external
10528 * screen. Since we don't yet re-compute the pipe config when moving
10529 * just the lvds port away to another pipe the sw tracking won't match.
10530 *
10531 * Proper atomic modesets with recomputed global state will fix this.
10532 * Until then just don't check gmch state for inherited modes.
10533 */
10534 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10535 PIPE_CONF_CHECK_I(gmch_pfit.control);
10536 /* pfit ratios are autocomputed by the hw on gen4+ */
10537 if (INTEL_INFO(dev)->gen < 4)
10538 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10539 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10540 }
10541
10542 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10543 if (current_config->pch_pfit.enabled) {
10544 PIPE_CONF_CHECK_I(pch_pfit.pos);
10545 PIPE_CONF_CHECK_I(pch_pfit.size);
10546 }
10547
10548 /* BDW+ don't expose a synchronous way to read the state */
10549 if (IS_HASWELL(dev))
10550 PIPE_CONF_CHECK_I(ips_enabled);
10551
10552 PIPE_CONF_CHECK_I(double_wide);
10553
10554 PIPE_CONF_CHECK_X(ddi_pll_sel);
10555
10556 PIPE_CONF_CHECK_I(shared_dpll);
10557 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10558 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10559 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10560 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10561 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10562 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
10563 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
10564 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
10565
10566 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10567 PIPE_CONF_CHECK_I(pipe_bpp);
10568
10569 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10570 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10571
10572 #undef PIPE_CONF_CHECK_X
10573 #undef PIPE_CONF_CHECK_I
10574 #undef PIPE_CONF_CHECK_I_ALT
10575 #undef PIPE_CONF_CHECK_FLAGS
10576 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10577 #undef PIPE_CONF_QUIRK
10578
10579 return true;
10580 }
10581
10582 static void check_wm_state(struct drm_device *dev)
10583 {
10584 struct drm_i915_private *dev_priv = dev->dev_private;
10585 struct skl_ddb_allocation hw_ddb, *sw_ddb;
10586 struct intel_crtc *intel_crtc;
10587 int plane;
10588
10589 if (INTEL_INFO(dev)->gen < 9)
10590 return;
10591
10592 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
10593 sw_ddb = &dev_priv->wm.skl_hw.ddb;
10594
10595 for_each_intel_crtc(dev, intel_crtc) {
10596 struct skl_ddb_entry *hw_entry, *sw_entry;
10597 const enum pipe pipe = intel_crtc->pipe;
10598
10599 if (!intel_crtc->active)
10600 continue;
10601
10602 /* planes */
10603 for_each_plane(pipe, plane) {
10604 hw_entry = &hw_ddb.plane[pipe][plane];
10605 sw_entry = &sw_ddb->plane[pipe][plane];
10606
10607 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10608 continue;
10609
10610 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
10611 "(expected (%u,%u), found (%u,%u))\n",
10612 pipe_name(pipe), plane + 1,
10613 sw_entry->start, sw_entry->end,
10614 hw_entry->start, hw_entry->end);
10615 }
10616
10617 /* cursor */
10618 hw_entry = &hw_ddb.cursor[pipe];
10619 sw_entry = &sw_ddb->cursor[pipe];
10620
10621 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10622 continue;
10623
10624 DRM_ERROR("mismatch in DDB state pipe %c cursor "
10625 "(expected (%u,%u), found (%u,%u))\n",
10626 pipe_name(pipe),
10627 sw_entry->start, sw_entry->end,
10628 hw_entry->start, hw_entry->end);
10629 }
10630 }
10631
10632 static void
10633 check_connector_state(struct drm_device *dev)
10634 {
10635 struct intel_connector *connector;
10636
10637 list_for_each_entry(connector, &dev->mode_config.connector_list,
10638 base.head) {
10639 /* This also checks the encoder/connector hw state with the
10640 * ->get_hw_state callbacks. */
10641 intel_connector_check_state(connector);
10642
10643 WARN(&connector->new_encoder->base != connector->base.encoder,
10644 "connector's staged encoder doesn't match current encoder\n");
10645 }
10646 }
10647
10648 static void
10649 check_encoder_state(struct drm_device *dev)
10650 {
10651 struct intel_encoder *encoder;
10652 struct intel_connector *connector;
10653
10654 for_each_intel_encoder(dev, encoder) {
10655 bool enabled = false;
10656 bool active = false;
10657 enum pipe pipe, tracked_pipe;
10658
10659 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10660 encoder->base.base.id,
10661 encoder->base.name);
10662
10663 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10664 "encoder's stage crtc doesn't match current crtc\n");
10665 WARN(encoder->connectors_active && !encoder->base.crtc,
10666 "encoder's active_connectors set, but no crtc\n");
10667
10668 list_for_each_entry(connector, &dev->mode_config.connector_list,
10669 base.head) {
10670 if (connector->base.encoder != &encoder->base)
10671 continue;
10672 enabled = true;
10673 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10674 active = true;
10675 }
10676 /*
10677 * for MST connectors if we unplug the connector is gone
10678 * away but the encoder is still connected to a crtc
10679 * until a modeset happens in response to the hotplug.
10680 */
10681 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10682 continue;
10683
10684 WARN(!!encoder->base.crtc != enabled,
10685 "encoder's enabled state mismatch "
10686 "(expected %i, found %i)\n",
10687 !!encoder->base.crtc, enabled);
10688 WARN(active && !encoder->base.crtc,
10689 "active encoder with no crtc\n");
10690
10691 WARN(encoder->connectors_active != active,
10692 "encoder's computed active state doesn't match tracked active state "
10693 "(expected %i, found %i)\n", active, encoder->connectors_active);
10694
10695 active = encoder->get_hw_state(encoder, &pipe);
10696 WARN(active != encoder->connectors_active,
10697 "encoder's hw state doesn't match sw tracking "
10698 "(expected %i, found %i)\n",
10699 encoder->connectors_active, active);
10700
10701 if (!encoder->base.crtc)
10702 continue;
10703
10704 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10705 WARN(active && pipe != tracked_pipe,
10706 "active encoder's pipe doesn't match"
10707 "(expected %i, found %i)\n",
10708 tracked_pipe, pipe);
10709
10710 }
10711 }
10712
10713 static void
10714 check_crtc_state(struct drm_device *dev)
10715 {
10716 struct drm_i915_private *dev_priv = dev->dev_private;
10717 struct intel_crtc *crtc;
10718 struct intel_encoder *encoder;
10719 struct intel_crtc_config pipe_config;
10720
10721 for_each_intel_crtc(dev, crtc) {
10722 bool enabled = false;
10723 bool active = false;
10724
10725 memset(&pipe_config, 0, sizeof(pipe_config));
10726
10727 DRM_DEBUG_KMS("[CRTC:%d]\n",
10728 crtc->base.base.id);
10729
10730 WARN(crtc->active && !crtc->base.enabled,
10731 "active crtc, but not enabled in sw tracking\n");
10732
10733 for_each_intel_encoder(dev, encoder) {
10734 if (encoder->base.crtc != &crtc->base)
10735 continue;
10736 enabled = true;
10737 if (encoder->connectors_active)
10738 active = true;
10739 }
10740
10741 WARN(active != crtc->active,
10742 "crtc's computed active state doesn't match tracked active state "
10743 "(expected %i, found %i)\n", active, crtc->active);
10744 WARN(enabled != crtc->base.enabled,
10745 "crtc's computed enabled state doesn't match tracked enabled state "
10746 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10747
10748 active = dev_priv->display.get_pipe_config(crtc,
10749 &pipe_config);
10750
10751 /* hw state is inconsistent with the pipe quirk */
10752 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10753 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
10754 active = crtc->active;
10755
10756 for_each_intel_encoder(dev, encoder) {
10757 enum pipe pipe;
10758 if (encoder->base.crtc != &crtc->base)
10759 continue;
10760 if (encoder->get_hw_state(encoder, &pipe))
10761 encoder->get_config(encoder, &pipe_config);
10762 }
10763
10764 WARN(crtc->active != active,
10765 "crtc active state doesn't match with hw state "
10766 "(expected %i, found %i)\n", crtc->active, active);
10767
10768 if (active &&
10769 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10770 WARN(1, "pipe state doesn't match!\n");
10771 intel_dump_pipe_config(crtc, &pipe_config,
10772 "[hw state]");
10773 intel_dump_pipe_config(crtc, &crtc->config,
10774 "[sw state]");
10775 }
10776 }
10777 }
10778
10779 static void
10780 check_shared_dpll_state(struct drm_device *dev)
10781 {
10782 struct drm_i915_private *dev_priv = dev->dev_private;
10783 struct intel_crtc *crtc;
10784 struct intel_dpll_hw_state dpll_hw_state;
10785 int i;
10786
10787 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10788 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10789 int enabled_crtcs = 0, active_crtcs = 0;
10790 bool active;
10791
10792 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10793
10794 DRM_DEBUG_KMS("%s\n", pll->name);
10795
10796 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10797
10798 WARN(pll->active > hweight32(pll->config.crtc_mask),
10799 "more active pll users than references: %i vs %i\n",
10800 pll->active, hweight32(pll->config.crtc_mask));
10801 WARN(pll->active && !pll->on,
10802 "pll in active use but not on in sw tracking\n");
10803 WARN(pll->on && !pll->active,
10804 "pll in on but not on in use in sw tracking\n");
10805 WARN(pll->on != active,
10806 "pll on state mismatch (expected %i, found %i)\n",
10807 pll->on, active);
10808
10809 for_each_intel_crtc(dev, crtc) {
10810 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10811 enabled_crtcs++;
10812 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10813 active_crtcs++;
10814 }
10815 WARN(pll->active != active_crtcs,
10816 "pll active crtcs mismatch (expected %i, found %i)\n",
10817 pll->active, active_crtcs);
10818 WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
10819 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10820 hweight32(pll->config.crtc_mask), enabled_crtcs);
10821
10822 WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
10823 sizeof(dpll_hw_state)),
10824 "pll hw state mismatch\n");
10825 }
10826 }
10827
10828 void
10829 intel_modeset_check_state(struct drm_device *dev)
10830 {
10831 check_wm_state(dev);
10832 check_connector_state(dev);
10833 check_encoder_state(dev);
10834 check_crtc_state(dev);
10835 check_shared_dpll_state(dev);
10836 }
10837
10838 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10839 int dotclock)
10840 {
10841 /*
10842 * FDI already provided one idea for the dotclock.
10843 * Yell if the encoder disagrees.
10844 */
10845 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10846 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10847 pipe_config->adjusted_mode.crtc_clock, dotclock);
10848 }
10849
10850 static void update_scanline_offset(struct intel_crtc *crtc)
10851 {
10852 struct drm_device *dev = crtc->base.dev;
10853
10854 /*
10855 * The scanline counter increments at the leading edge of hsync.
10856 *
10857 * On most platforms it starts counting from vtotal-1 on the
10858 * first active line. That means the scanline counter value is
10859 * always one less than what we would expect. Ie. just after
10860 * start of vblank, which also occurs at start of hsync (on the
10861 * last active line), the scanline counter will read vblank_start-1.
10862 *
10863 * On gen2 the scanline counter starts counting from 1 instead
10864 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10865 * to keep the value positive), instead of adding one.
10866 *
10867 * On HSW+ the behaviour of the scanline counter depends on the output
10868 * type. For DP ports it behaves like most other platforms, but on HDMI
10869 * there's an extra 1 line difference. So we need to add two instead of
10870 * one to the value.
10871 */
10872 if (IS_GEN2(dev)) {
10873 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
10874 int vtotal;
10875
10876 vtotal = mode->crtc_vtotal;
10877 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10878 vtotal /= 2;
10879
10880 crtc->scanline_offset = vtotal - 1;
10881 } else if (HAS_DDI(dev) &&
10882 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
10883 crtc->scanline_offset = 2;
10884 } else
10885 crtc->scanline_offset = 1;
10886 }
10887
10888 static struct intel_crtc_config *
10889 intel_modeset_compute_config(struct drm_crtc *crtc,
10890 struct drm_display_mode *mode,
10891 struct drm_framebuffer *fb,
10892 unsigned *modeset_pipes,
10893 unsigned *prepare_pipes,
10894 unsigned *disable_pipes)
10895 {
10896 struct intel_crtc_config *pipe_config = NULL;
10897
10898 intel_modeset_affected_pipes(crtc, modeset_pipes,
10899 prepare_pipes, disable_pipes);
10900
10901 if ((*modeset_pipes) == 0)
10902 goto out;
10903
10904 /*
10905 * Note this needs changes when we start tracking multiple modes
10906 * and crtcs. At that point we'll need to compute the whole config
10907 * (i.e. one pipe_config for each crtc) rather than just the one
10908 * for this crtc.
10909 */
10910 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10911 if (IS_ERR(pipe_config)) {
10912 goto out;
10913 }
10914 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10915 "[modeset]");
10916 to_intel_crtc(crtc)->new_config = pipe_config;
10917
10918 out:
10919 return pipe_config;
10920 }
10921
10922 static int __intel_set_mode(struct drm_crtc *crtc,
10923 struct drm_display_mode *mode,
10924 int x, int y, struct drm_framebuffer *fb,
10925 struct intel_crtc_config *pipe_config,
10926 unsigned modeset_pipes,
10927 unsigned prepare_pipes,
10928 unsigned disable_pipes)
10929 {
10930 struct drm_device *dev = crtc->dev;
10931 struct drm_i915_private *dev_priv = dev->dev_private;
10932 struct drm_display_mode *saved_mode;
10933 struct intel_crtc *intel_crtc;
10934 int ret = 0;
10935
10936 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10937 if (!saved_mode)
10938 return -ENOMEM;
10939
10940 *saved_mode = crtc->mode;
10941
10942 /*
10943 * See if the config requires any additional preparation, e.g.
10944 * to adjust global state with pipes off. We need to do this
10945 * here so we can get the modeset_pipe updated config for the new
10946 * mode set on this crtc. For other crtcs we need to use the
10947 * adjusted_mode bits in the crtc directly.
10948 */
10949 if (IS_VALLEYVIEW(dev)) {
10950 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10951
10952 /* may have added more to prepare_pipes than we should */
10953 prepare_pipes &= ~disable_pipes;
10954 }
10955
10956 if (dev_priv->display.crtc_compute_clock) {
10957 unsigned clear_pipes = modeset_pipes | disable_pipes;
10958
10959 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
10960 if (ret)
10961 goto done;
10962
10963 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10964 ret = dev_priv->display.crtc_compute_clock(intel_crtc);
10965 if (ret) {
10966 intel_shared_dpll_abort_config(dev_priv);
10967 goto done;
10968 }
10969 }
10970 }
10971
10972 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10973 intel_crtc_disable(&intel_crtc->base);
10974
10975 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10976 if (intel_crtc->base.enabled)
10977 dev_priv->display.crtc_disable(&intel_crtc->base);
10978 }
10979
10980 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10981 * to set it here already despite that we pass it down the callchain.
10982 *
10983 * Note we'll need to fix this up when we start tracking multiple
10984 * pipes; here we assume a single modeset_pipe and only track the
10985 * single crtc and mode.
10986 */
10987 if (modeset_pipes) {
10988 crtc->mode = *mode;
10989 /* mode_set/enable/disable functions rely on a correct pipe
10990 * config. */
10991 to_intel_crtc(crtc)->config = *pipe_config;
10992 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10993
10994 /*
10995 * Calculate and store various constants which
10996 * are later needed by vblank and swap-completion
10997 * timestamping. They are derived from true hwmode.
10998 */
10999 drm_calc_timestamping_constants(crtc,
11000 &pipe_config->adjusted_mode);
11001 }
11002
11003 /* Only after disabling all output pipelines that will be changed can we
11004 * update the the output configuration. */
11005 intel_modeset_update_state(dev, prepare_pipes);
11006
11007 modeset_update_crtc_power_domains(dev);
11008
11009 /* Set up the DPLL and any encoders state that needs to adjust or depend
11010 * on the DPLL.
11011 */
11012 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11013 struct drm_framebuffer *old_fb = crtc->primary->fb;
11014 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
11015 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11016
11017 mutex_lock(&dev->struct_mutex);
11018 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, NULL);
11019 if (ret != 0) {
11020 DRM_ERROR("pin & fence failed\n");
11021 mutex_unlock(&dev->struct_mutex);
11022 goto done;
11023 }
11024 if (old_fb)
11025 intel_unpin_fb_obj(old_obj);
11026 i915_gem_track_fb(old_obj, obj,
11027 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11028 mutex_unlock(&dev->struct_mutex);
11029
11030 crtc->primary->fb = fb;
11031 crtc->x = x;
11032 crtc->y = y;
11033 }
11034
11035 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11036 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11037 update_scanline_offset(intel_crtc);
11038
11039 dev_priv->display.crtc_enable(&intel_crtc->base);
11040 }
11041
11042 /* FIXME: add subpixel order */
11043 done:
11044 if (ret && crtc->enabled)
11045 crtc->mode = *saved_mode;
11046
11047 kfree(pipe_config);
11048 kfree(saved_mode);
11049 return ret;
11050 }
11051
11052 static int intel_set_mode_pipes(struct drm_crtc *crtc,
11053 struct drm_display_mode *mode,
11054 int x, int y, struct drm_framebuffer *fb,
11055 struct intel_crtc_config *pipe_config,
11056 unsigned modeset_pipes,
11057 unsigned prepare_pipes,
11058 unsigned disable_pipes)
11059 {
11060 int ret;
11061
11062 ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
11063 prepare_pipes, disable_pipes);
11064
11065 if (ret == 0)
11066 intel_modeset_check_state(crtc->dev);
11067
11068 return ret;
11069 }
11070
11071 static int intel_set_mode(struct drm_crtc *crtc,
11072 struct drm_display_mode *mode,
11073 int x, int y, struct drm_framebuffer *fb)
11074 {
11075 struct intel_crtc_config *pipe_config;
11076 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11077
11078 pipe_config = intel_modeset_compute_config(crtc, mode, fb,
11079 &modeset_pipes,
11080 &prepare_pipes,
11081 &disable_pipes);
11082
11083 if (IS_ERR(pipe_config))
11084 return PTR_ERR(pipe_config);
11085
11086 return intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
11087 modeset_pipes, prepare_pipes,
11088 disable_pipes);
11089 }
11090
11091 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11092 {
11093 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
11094 }
11095
11096 #undef for_each_intel_crtc_masked
11097
11098 static void intel_set_config_free(struct intel_set_config *config)
11099 {
11100 if (!config)
11101 return;
11102
11103 kfree(config->save_connector_encoders);
11104 kfree(config->save_encoder_crtcs);
11105 kfree(config->save_crtc_enabled);
11106 kfree(config);
11107 }
11108
11109 static int intel_set_config_save_state(struct drm_device *dev,
11110 struct intel_set_config *config)
11111 {
11112 struct drm_crtc *crtc;
11113 struct drm_encoder *encoder;
11114 struct drm_connector *connector;
11115 int count;
11116
11117 config->save_crtc_enabled =
11118 kcalloc(dev->mode_config.num_crtc,
11119 sizeof(bool), GFP_KERNEL);
11120 if (!config->save_crtc_enabled)
11121 return -ENOMEM;
11122
11123 config->save_encoder_crtcs =
11124 kcalloc(dev->mode_config.num_encoder,
11125 sizeof(struct drm_crtc *), GFP_KERNEL);
11126 if (!config->save_encoder_crtcs)
11127 return -ENOMEM;
11128
11129 config->save_connector_encoders =
11130 kcalloc(dev->mode_config.num_connector,
11131 sizeof(struct drm_encoder *), GFP_KERNEL);
11132 if (!config->save_connector_encoders)
11133 return -ENOMEM;
11134
11135 /* Copy data. Note that driver private data is not affected.
11136 * Should anything bad happen only the expected state is
11137 * restored, not the drivers personal bookkeeping.
11138 */
11139 count = 0;
11140 for_each_crtc(dev, crtc) {
11141 config->save_crtc_enabled[count++] = crtc->enabled;
11142 }
11143
11144 count = 0;
11145 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11146 config->save_encoder_crtcs[count++] = encoder->crtc;
11147 }
11148
11149 count = 0;
11150 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11151 config->save_connector_encoders[count++] = connector->encoder;
11152 }
11153
11154 return 0;
11155 }
11156
11157 static void intel_set_config_restore_state(struct drm_device *dev,
11158 struct intel_set_config *config)
11159 {
11160 struct intel_crtc *crtc;
11161 struct intel_encoder *encoder;
11162 struct intel_connector *connector;
11163 int count;
11164
11165 count = 0;
11166 for_each_intel_crtc(dev, crtc) {
11167 crtc->new_enabled = config->save_crtc_enabled[count++];
11168
11169 if (crtc->new_enabled)
11170 crtc->new_config = &crtc->config;
11171 else
11172 crtc->new_config = NULL;
11173 }
11174
11175 count = 0;
11176 for_each_intel_encoder(dev, encoder) {
11177 encoder->new_crtc =
11178 to_intel_crtc(config->save_encoder_crtcs[count++]);
11179 }
11180
11181 count = 0;
11182 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11183 connector->new_encoder =
11184 to_intel_encoder(config->save_connector_encoders[count++]);
11185 }
11186 }
11187
11188 static bool
11189 is_crtc_connector_off(struct drm_mode_set *set)
11190 {
11191 int i;
11192
11193 if (set->num_connectors == 0)
11194 return false;
11195
11196 if (WARN_ON(set->connectors == NULL))
11197 return false;
11198
11199 for (i = 0; i < set->num_connectors; i++)
11200 if (set->connectors[i]->encoder &&
11201 set->connectors[i]->encoder->crtc == set->crtc &&
11202 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11203 return true;
11204
11205 return false;
11206 }
11207
11208 static void
11209 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11210 struct intel_set_config *config)
11211 {
11212
11213 /* We should be able to check here if the fb has the same properties
11214 * and then just flip_or_move it */
11215 if (is_crtc_connector_off(set)) {
11216 config->mode_changed = true;
11217 } else if (set->crtc->primary->fb != set->fb) {
11218 /*
11219 * If we have no fb, we can only flip as long as the crtc is
11220 * active, otherwise we need a full mode set. The crtc may
11221 * be active if we've only disabled the primary plane, or
11222 * in fastboot situations.
11223 */
11224 if (set->crtc->primary->fb == NULL) {
11225 struct intel_crtc *intel_crtc =
11226 to_intel_crtc(set->crtc);
11227
11228 if (intel_crtc->active) {
11229 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11230 config->fb_changed = true;
11231 } else {
11232 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11233 config->mode_changed = true;
11234 }
11235 } else if (set->fb == NULL) {
11236 config->mode_changed = true;
11237 } else if (set->fb->pixel_format !=
11238 set->crtc->primary->fb->pixel_format) {
11239 config->mode_changed = true;
11240 } else {
11241 config->fb_changed = true;
11242 }
11243 }
11244
11245 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11246 config->fb_changed = true;
11247
11248 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11249 DRM_DEBUG_KMS("modes are different, full mode set\n");
11250 drm_mode_debug_printmodeline(&set->crtc->mode);
11251 drm_mode_debug_printmodeline(set->mode);
11252 config->mode_changed = true;
11253 }
11254
11255 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11256 set->crtc->base.id, config->mode_changed, config->fb_changed);
11257 }
11258
11259 static int
11260 intel_modeset_stage_output_state(struct drm_device *dev,
11261 struct drm_mode_set *set,
11262 struct intel_set_config *config)
11263 {
11264 struct intel_connector *connector;
11265 struct intel_encoder *encoder;
11266 struct intel_crtc *crtc;
11267 int ro;
11268
11269 /* The upper layers ensure that we either disable a crtc or have a list
11270 * of connectors. For paranoia, double-check this. */
11271 WARN_ON(!set->fb && (set->num_connectors != 0));
11272 WARN_ON(set->fb && (set->num_connectors == 0));
11273
11274 list_for_each_entry(connector, &dev->mode_config.connector_list,
11275 base.head) {
11276 /* Otherwise traverse passed in connector list and get encoders
11277 * for them. */
11278 for (ro = 0; ro < set->num_connectors; ro++) {
11279 if (set->connectors[ro] == &connector->base) {
11280 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11281 break;
11282 }
11283 }
11284
11285 /* If we disable the crtc, disable all its connectors. Also, if
11286 * the connector is on the changing crtc but not on the new
11287 * connector list, disable it. */
11288 if ((!set->fb || ro == set->num_connectors) &&
11289 connector->base.encoder &&
11290 connector->base.encoder->crtc == set->crtc) {
11291 connector->new_encoder = NULL;
11292
11293 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11294 connector->base.base.id,
11295 connector->base.name);
11296 }
11297
11298
11299 if (&connector->new_encoder->base != connector->base.encoder) {
11300 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11301 config->mode_changed = true;
11302 }
11303 }
11304 /* connector->new_encoder is now updated for all connectors. */
11305
11306 /* Update crtc of enabled connectors. */
11307 list_for_each_entry(connector, &dev->mode_config.connector_list,
11308 base.head) {
11309 struct drm_crtc *new_crtc;
11310
11311 if (!connector->new_encoder)
11312 continue;
11313
11314 new_crtc = connector->new_encoder->base.crtc;
11315
11316 for (ro = 0; ro < set->num_connectors; ro++) {
11317 if (set->connectors[ro] == &connector->base)
11318 new_crtc = set->crtc;
11319 }
11320
11321 /* Make sure the new CRTC will work with the encoder */
11322 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11323 new_crtc)) {
11324 return -EINVAL;
11325 }
11326 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11327
11328 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11329 connector->base.base.id,
11330 connector->base.name,
11331 new_crtc->base.id);
11332 }
11333
11334 /* Check for any encoders that needs to be disabled. */
11335 for_each_intel_encoder(dev, encoder) {
11336 int num_connectors = 0;
11337 list_for_each_entry(connector,
11338 &dev->mode_config.connector_list,
11339 base.head) {
11340 if (connector->new_encoder == encoder) {
11341 WARN_ON(!connector->new_encoder->new_crtc);
11342 num_connectors++;
11343 }
11344 }
11345
11346 if (num_connectors == 0)
11347 encoder->new_crtc = NULL;
11348 else if (num_connectors > 1)
11349 return -EINVAL;
11350
11351 /* Only now check for crtc changes so we don't miss encoders
11352 * that will be disabled. */
11353 if (&encoder->new_crtc->base != encoder->base.crtc) {
11354 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11355 config->mode_changed = true;
11356 }
11357 }
11358 /* Now we've also updated encoder->new_crtc for all encoders. */
11359 list_for_each_entry(connector, &dev->mode_config.connector_list,
11360 base.head) {
11361 if (connector->new_encoder)
11362 if (connector->new_encoder != connector->encoder)
11363 connector->encoder = connector->new_encoder;
11364 }
11365 for_each_intel_crtc(dev, crtc) {
11366 crtc->new_enabled = false;
11367
11368 for_each_intel_encoder(dev, encoder) {
11369 if (encoder->new_crtc == crtc) {
11370 crtc->new_enabled = true;
11371 break;
11372 }
11373 }
11374
11375 if (crtc->new_enabled != crtc->base.enabled) {
11376 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11377 crtc->new_enabled ? "en" : "dis");
11378 config->mode_changed = true;
11379 }
11380
11381 if (crtc->new_enabled)
11382 crtc->new_config = &crtc->config;
11383 else
11384 crtc->new_config = NULL;
11385 }
11386
11387 return 0;
11388 }
11389
11390 static void disable_crtc_nofb(struct intel_crtc *crtc)
11391 {
11392 struct drm_device *dev = crtc->base.dev;
11393 struct intel_encoder *encoder;
11394 struct intel_connector *connector;
11395
11396 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11397 pipe_name(crtc->pipe));
11398
11399 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11400 if (connector->new_encoder &&
11401 connector->new_encoder->new_crtc == crtc)
11402 connector->new_encoder = NULL;
11403 }
11404
11405 for_each_intel_encoder(dev, encoder) {
11406 if (encoder->new_crtc == crtc)
11407 encoder->new_crtc = NULL;
11408 }
11409
11410 crtc->new_enabled = false;
11411 crtc->new_config = NULL;
11412 }
11413
11414 static int intel_crtc_set_config(struct drm_mode_set *set)
11415 {
11416 struct drm_device *dev;
11417 struct drm_mode_set save_set;
11418 struct intel_set_config *config;
11419 struct intel_crtc_config *pipe_config;
11420 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11421 int ret;
11422
11423 BUG_ON(!set);
11424 BUG_ON(!set->crtc);
11425 BUG_ON(!set->crtc->helper_private);
11426
11427 /* Enforce sane interface api - has been abused by the fb helper. */
11428 BUG_ON(!set->mode && set->fb);
11429 BUG_ON(set->fb && set->num_connectors == 0);
11430
11431 if (set->fb) {
11432 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11433 set->crtc->base.id, set->fb->base.id,
11434 (int)set->num_connectors, set->x, set->y);
11435 } else {
11436 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11437 }
11438
11439 dev = set->crtc->dev;
11440
11441 ret = -ENOMEM;
11442 config = kzalloc(sizeof(*config), GFP_KERNEL);
11443 if (!config)
11444 goto out_config;
11445
11446 ret = intel_set_config_save_state(dev, config);
11447 if (ret)
11448 goto out_config;
11449
11450 save_set.crtc = set->crtc;
11451 save_set.mode = &set->crtc->mode;
11452 save_set.x = set->crtc->x;
11453 save_set.y = set->crtc->y;
11454 save_set.fb = set->crtc->primary->fb;
11455
11456 /* Compute whether we need a full modeset, only an fb base update or no
11457 * change at all. In the future we might also check whether only the
11458 * mode changed, e.g. for LVDS where we only change the panel fitter in
11459 * such cases. */
11460 intel_set_config_compute_mode_changes(set, config);
11461
11462 ret = intel_modeset_stage_output_state(dev, set, config);
11463 if (ret)
11464 goto fail;
11465
11466 pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
11467 set->fb,
11468 &modeset_pipes,
11469 &prepare_pipes,
11470 &disable_pipes);
11471 if (IS_ERR(pipe_config)) {
11472 ret = PTR_ERR(pipe_config);
11473 goto fail;
11474 } else if (pipe_config) {
11475 if (to_intel_crtc(set->crtc)->new_config->has_audio !=
11476 to_intel_crtc(set->crtc)->config.has_audio)
11477 config->mode_changed = true;
11478
11479 /* Force mode sets for any infoframe stuff */
11480 if (to_intel_crtc(set->crtc)->new_config->has_infoframe ||
11481 to_intel_crtc(set->crtc)->config.has_infoframe)
11482 config->mode_changed = true;
11483 }
11484
11485 /* set_mode will free it in the mode_changed case */
11486 if (!config->mode_changed)
11487 kfree(pipe_config);
11488
11489 intel_update_pipe_size(to_intel_crtc(set->crtc));
11490
11491 if (config->mode_changed) {
11492 ret = intel_set_mode_pipes(set->crtc, set->mode,
11493 set->x, set->y, set->fb, pipe_config,
11494 modeset_pipes, prepare_pipes,
11495 disable_pipes);
11496 } else if (config->fb_changed) {
11497 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11498
11499 intel_crtc_wait_for_pending_flips(set->crtc);
11500
11501 ret = intel_pipe_set_base(set->crtc,
11502 set->x, set->y, set->fb);
11503
11504 /*
11505 * We need to make sure the primary plane is re-enabled if it
11506 * has previously been turned off.
11507 */
11508 if (!intel_crtc->primary_enabled && ret == 0) {
11509 WARN_ON(!intel_crtc->active);
11510 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11511 }
11512
11513 /*
11514 * In the fastboot case this may be our only check of the
11515 * state after boot. It would be better to only do it on
11516 * the first update, but we don't have a nice way of doing that
11517 * (and really, set_config isn't used much for high freq page
11518 * flipping, so increasing its cost here shouldn't be a big
11519 * deal).
11520 */
11521 if (i915.fastboot && ret == 0)
11522 intel_modeset_check_state(set->crtc->dev);
11523 }
11524
11525 if (ret) {
11526 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11527 set->crtc->base.id, ret);
11528 fail:
11529 intel_set_config_restore_state(dev, config);
11530
11531 /*
11532 * HACK: if the pipe was on, but we didn't have a framebuffer,
11533 * force the pipe off to avoid oopsing in the modeset code
11534 * due to fb==NULL. This should only happen during boot since
11535 * we don't yet reconstruct the FB from the hardware state.
11536 */
11537 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11538 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11539
11540 /* Try to restore the config */
11541 if (config->mode_changed &&
11542 intel_set_mode(save_set.crtc, save_set.mode,
11543 save_set.x, save_set.y, save_set.fb))
11544 DRM_ERROR("failed to restore config after modeset failure\n");
11545 }
11546
11547 out_config:
11548 intel_set_config_free(config);
11549 return ret;
11550 }
11551
11552 static const struct drm_crtc_funcs intel_crtc_funcs = {
11553 .gamma_set = intel_crtc_gamma_set,
11554 .set_config = intel_crtc_set_config,
11555 .destroy = intel_crtc_destroy,
11556 .page_flip = intel_crtc_page_flip,
11557 };
11558
11559 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11560 struct intel_shared_dpll *pll,
11561 struct intel_dpll_hw_state *hw_state)
11562 {
11563 uint32_t val;
11564
11565 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
11566 return false;
11567
11568 val = I915_READ(PCH_DPLL(pll->id));
11569 hw_state->dpll = val;
11570 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11571 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11572
11573 return val & DPLL_VCO_ENABLE;
11574 }
11575
11576 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11577 struct intel_shared_dpll *pll)
11578 {
11579 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
11580 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
11581 }
11582
11583 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11584 struct intel_shared_dpll *pll)
11585 {
11586 /* PCH refclock must be enabled first */
11587 ibx_assert_pch_refclk_enabled(dev_priv);
11588
11589 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11590
11591 /* Wait for the clocks to stabilize. */
11592 POSTING_READ(PCH_DPLL(pll->id));
11593 udelay(150);
11594
11595 /* The pixel multiplier can only be updated once the
11596 * DPLL is enabled and the clocks are stable.
11597 *
11598 * So write it again.
11599 */
11600 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11601 POSTING_READ(PCH_DPLL(pll->id));
11602 udelay(200);
11603 }
11604
11605 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11606 struct intel_shared_dpll *pll)
11607 {
11608 struct drm_device *dev = dev_priv->dev;
11609 struct intel_crtc *crtc;
11610
11611 /* Make sure no transcoder isn't still depending on us. */
11612 for_each_intel_crtc(dev, crtc) {
11613 if (intel_crtc_to_shared_dpll(crtc) == pll)
11614 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11615 }
11616
11617 I915_WRITE(PCH_DPLL(pll->id), 0);
11618 POSTING_READ(PCH_DPLL(pll->id));
11619 udelay(200);
11620 }
11621
11622 static char *ibx_pch_dpll_names[] = {
11623 "PCH DPLL A",
11624 "PCH DPLL B",
11625 };
11626
11627 static void ibx_pch_dpll_init(struct drm_device *dev)
11628 {
11629 struct drm_i915_private *dev_priv = dev->dev_private;
11630 int i;
11631
11632 dev_priv->num_shared_dpll = 2;
11633
11634 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11635 dev_priv->shared_dplls[i].id = i;
11636 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11637 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11638 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11639 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11640 dev_priv->shared_dplls[i].get_hw_state =
11641 ibx_pch_dpll_get_hw_state;
11642 }
11643 }
11644
11645 static void intel_shared_dpll_init(struct drm_device *dev)
11646 {
11647 struct drm_i915_private *dev_priv = dev->dev_private;
11648
11649 if (HAS_DDI(dev))
11650 intel_ddi_pll_init(dev);
11651 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11652 ibx_pch_dpll_init(dev);
11653 else
11654 dev_priv->num_shared_dpll = 0;
11655
11656 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11657 }
11658
11659 static int
11660 intel_primary_plane_disable(struct drm_plane *plane)
11661 {
11662 struct drm_device *dev = plane->dev;
11663 struct intel_crtc *intel_crtc;
11664
11665 if (!plane->fb)
11666 return 0;
11667
11668 BUG_ON(!plane->crtc);
11669
11670 intel_crtc = to_intel_crtc(plane->crtc);
11671
11672 /*
11673 * Even though we checked plane->fb above, it's still possible that
11674 * the primary plane has been implicitly disabled because the crtc
11675 * coordinates given weren't visible, or because we detected
11676 * that it was 100% covered by a sprite plane. Or, the CRTC may be
11677 * off and we've set a fb, but haven't actually turned on the CRTC yet.
11678 * In either case, we need to unpin the FB and let the fb pointer get
11679 * updated, but otherwise we don't need to touch the hardware.
11680 */
11681 if (!intel_crtc->primary_enabled)
11682 goto disable_unpin;
11683
11684 intel_crtc_wait_for_pending_flips(plane->crtc);
11685 intel_disable_primary_hw_plane(plane, plane->crtc);
11686
11687 disable_unpin:
11688 mutex_lock(&dev->struct_mutex);
11689 i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
11690 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11691 intel_unpin_fb_obj(intel_fb_obj(plane->fb));
11692 mutex_unlock(&dev->struct_mutex);
11693 plane->fb = NULL;
11694
11695 return 0;
11696 }
11697
11698 static int
11699 intel_check_primary_plane(struct drm_plane *plane,
11700 struct intel_plane_state *state)
11701 {
11702 struct drm_crtc *crtc = state->crtc;
11703 struct drm_framebuffer *fb = state->fb;
11704 struct drm_rect *dest = &state->dst;
11705 struct drm_rect *src = &state->src;
11706 const struct drm_rect *clip = &state->clip;
11707
11708 return drm_plane_helper_check_update(plane, crtc, fb,
11709 src, dest, clip,
11710 DRM_PLANE_HELPER_NO_SCALING,
11711 DRM_PLANE_HELPER_NO_SCALING,
11712 false, true, &state->visible);
11713 }
11714
11715 static int
11716 intel_prepare_primary_plane(struct drm_plane *plane,
11717 struct intel_plane_state *state)
11718 {
11719 struct drm_crtc *crtc = state->crtc;
11720 struct drm_framebuffer *fb = state->fb;
11721 struct drm_device *dev = crtc->dev;
11722 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11723 enum pipe pipe = intel_crtc->pipe;
11724 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11725 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11726 int ret;
11727
11728 intel_crtc_wait_for_pending_flips(crtc);
11729
11730 if (intel_crtc_has_pending_flip(crtc)) {
11731 DRM_ERROR("pipe is still busy with an old pageflip\n");
11732 return -EBUSY;
11733 }
11734
11735 if (old_obj != obj) {
11736 mutex_lock(&dev->struct_mutex);
11737 ret = intel_pin_and_fence_fb_obj(plane, fb, NULL);
11738 if (ret == 0)
11739 i915_gem_track_fb(old_obj, obj,
11740 INTEL_FRONTBUFFER_PRIMARY(pipe));
11741 mutex_unlock(&dev->struct_mutex);
11742 if (ret != 0) {
11743 DRM_DEBUG_KMS("pin & fence failed\n");
11744 return ret;
11745 }
11746 }
11747
11748 return 0;
11749 }
11750
11751 static void
11752 intel_commit_primary_plane(struct drm_plane *plane,
11753 struct intel_plane_state *state)
11754 {
11755 struct drm_crtc *crtc = state->crtc;
11756 struct drm_framebuffer *fb = state->fb;
11757 struct drm_device *dev = crtc->dev;
11758 struct drm_i915_private *dev_priv = dev->dev_private;
11759 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11760 enum pipe pipe = intel_crtc->pipe;
11761 struct drm_framebuffer *old_fb = plane->fb;
11762 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11763 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11764 struct intel_plane *intel_plane = to_intel_plane(plane);
11765 struct drm_rect *src = &state->src;
11766
11767 crtc->primary->fb = fb;
11768 crtc->x = src->x1 >> 16;
11769 crtc->y = src->y1 >> 16;
11770
11771 intel_plane->crtc_x = state->orig_dst.x1;
11772 intel_plane->crtc_y = state->orig_dst.y1;
11773 intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
11774 intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
11775 intel_plane->src_x = state->orig_src.x1;
11776 intel_plane->src_y = state->orig_src.y1;
11777 intel_plane->src_w = drm_rect_width(&state->orig_src);
11778 intel_plane->src_h = drm_rect_height(&state->orig_src);
11779 intel_plane->obj = obj;
11780
11781 if (intel_crtc->active) {
11782 /*
11783 * FBC does not work on some platforms for rotated
11784 * planes, so disable it when rotation is not 0 and
11785 * update it when rotation is set back to 0.
11786 *
11787 * FIXME: This is redundant with the fbc update done in
11788 * the primary plane enable function except that that
11789 * one is done too late. We eventually need to unify
11790 * this.
11791 */
11792 if (intel_crtc->primary_enabled &&
11793 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11794 dev_priv->fbc.plane == intel_crtc->plane &&
11795 intel_plane->rotation != BIT(DRM_ROTATE_0)) {
11796 intel_disable_fbc(dev);
11797 }
11798
11799 if (state->visible) {
11800 bool was_enabled = intel_crtc->primary_enabled;
11801
11802 /* FIXME: kill this fastboot hack */
11803 intel_update_pipe_size(intel_crtc);
11804
11805 intel_crtc->primary_enabled = true;
11806
11807 dev_priv->display.update_primary_plane(crtc, plane->fb,
11808 crtc->x, crtc->y);
11809
11810 /*
11811 * BDW signals flip done immediately if the plane
11812 * is disabled, even if the plane enable is already
11813 * armed to occur at the next vblank :(
11814 */
11815 if (IS_BROADWELL(dev) && !was_enabled)
11816 intel_wait_for_vblank(dev, intel_crtc->pipe);
11817 } else {
11818 /*
11819 * If clipping results in a non-visible primary plane,
11820 * we'll disable the primary plane. Note that this is
11821 * a bit different than what happens if userspace
11822 * explicitly disables the plane by passing fb=0
11823 * because plane->fb still gets set and pinned.
11824 */
11825 intel_disable_primary_hw_plane(plane, crtc);
11826 }
11827
11828 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
11829
11830 mutex_lock(&dev->struct_mutex);
11831 intel_update_fbc(dev);
11832 mutex_unlock(&dev->struct_mutex);
11833 }
11834
11835 if (old_fb && old_fb != fb) {
11836 if (intel_crtc->active)
11837 intel_wait_for_vblank(dev, intel_crtc->pipe);
11838
11839 mutex_lock(&dev->struct_mutex);
11840 intel_unpin_fb_obj(old_obj);
11841 mutex_unlock(&dev->struct_mutex);
11842 }
11843 }
11844
11845 static int
11846 intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11847 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11848 unsigned int crtc_w, unsigned int crtc_h,
11849 uint32_t src_x, uint32_t src_y,
11850 uint32_t src_w, uint32_t src_h)
11851 {
11852 struct intel_plane_state state;
11853 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11854 int ret;
11855
11856 state.crtc = crtc;
11857 state.fb = fb;
11858
11859 /* sample coordinates in 16.16 fixed point */
11860 state.src.x1 = src_x;
11861 state.src.x2 = src_x + src_w;
11862 state.src.y1 = src_y;
11863 state.src.y2 = src_y + src_h;
11864
11865 /* integer pixels */
11866 state.dst.x1 = crtc_x;
11867 state.dst.x2 = crtc_x + crtc_w;
11868 state.dst.y1 = crtc_y;
11869 state.dst.y2 = crtc_y + crtc_h;
11870
11871 state.clip.x1 = 0;
11872 state.clip.y1 = 0;
11873 state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
11874 state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
11875
11876 state.orig_src = state.src;
11877 state.orig_dst = state.dst;
11878
11879 ret = intel_check_primary_plane(plane, &state);
11880 if (ret)
11881 return ret;
11882
11883 ret = intel_prepare_primary_plane(plane, &state);
11884 if (ret)
11885 return ret;
11886
11887 intel_commit_primary_plane(plane, &state);
11888
11889 return 0;
11890 }
11891
11892 /* Common destruction function for both primary and cursor planes */
11893 static void intel_plane_destroy(struct drm_plane *plane)
11894 {
11895 struct intel_plane *intel_plane = to_intel_plane(plane);
11896 drm_plane_cleanup(plane);
11897 kfree(intel_plane);
11898 }
11899
11900 static const struct drm_plane_funcs intel_primary_plane_funcs = {
11901 .update_plane = intel_primary_plane_setplane,
11902 .disable_plane = intel_primary_plane_disable,
11903 .destroy = intel_plane_destroy,
11904 .set_property = intel_plane_set_property
11905 };
11906
11907 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11908 int pipe)
11909 {
11910 struct intel_plane *primary;
11911 const uint32_t *intel_primary_formats;
11912 int num_formats;
11913
11914 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11915 if (primary == NULL)
11916 return NULL;
11917
11918 primary->can_scale = false;
11919 primary->max_downscale = 1;
11920 primary->pipe = pipe;
11921 primary->plane = pipe;
11922 primary->rotation = BIT(DRM_ROTATE_0);
11923 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11924 primary->plane = !pipe;
11925
11926 if (INTEL_INFO(dev)->gen <= 3) {
11927 intel_primary_formats = intel_primary_formats_gen2;
11928 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
11929 } else {
11930 intel_primary_formats = intel_primary_formats_gen4;
11931 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
11932 }
11933
11934 drm_universal_plane_init(dev, &primary->base, 0,
11935 &intel_primary_plane_funcs,
11936 intel_primary_formats, num_formats,
11937 DRM_PLANE_TYPE_PRIMARY);
11938
11939 if (INTEL_INFO(dev)->gen >= 4) {
11940 if (!dev->mode_config.rotation_property)
11941 dev->mode_config.rotation_property =
11942 drm_mode_create_rotation_property(dev,
11943 BIT(DRM_ROTATE_0) |
11944 BIT(DRM_ROTATE_180));
11945 if (dev->mode_config.rotation_property)
11946 drm_object_attach_property(&primary->base.base,
11947 dev->mode_config.rotation_property,
11948 primary->rotation);
11949 }
11950
11951 return &primary->base;
11952 }
11953
11954 static int
11955 intel_cursor_plane_disable(struct drm_plane *plane)
11956 {
11957 if (!plane->fb)
11958 return 0;
11959
11960 BUG_ON(!plane->crtc);
11961
11962 return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
11963 }
11964
11965 static int
11966 intel_check_cursor_plane(struct drm_plane *plane,
11967 struct intel_plane_state *state)
11968 {
11969 struct drm_crtc *crtc = state->crtc;
11970 struct drm_device *dev = crtc->dev;
11971 struct drm_framebuffer *fb = state->fb;
11972 struct drm_rect *dest = &state->dst;
11973 struct drm_rect *src = &state->src;
11974 const struct drm_rect *clip = &state->clip;
11975 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11976 int crtc_w, crtc_h;
11977 unsigned stride;
11978 int ret;
11979
11980 ret = drm_plane_helper_check_update(plane, crtc, fb,
11981 src, dest, clip,
11982 DRM_PLANE_HELPER_NO_SCALING,
11983 DRM_PLANE_HELPER_NO_SCALING,
11984 true, true, &state->visible);
11985 if (ret)
11986 return ret;
11987
11988
11989 /* if we want to turn off the cursor ignore width and height */
11990 if (!obj)
11991 return 0;
11992
11993 /* Check for which cursor types we support */
11994 crtc_w = drm_rect_width(&state->orig_dst);
11995 crtc_h = drm_rect_height(&state->orig_dst);
11996 if (!cursor_size_ok(dev, crtc_w, crtc_h)) {
11997 DRM_DEBUG("Cursor dimension not supported\n");
11998 return -EINVAL;
11999 }
12000
12001 stride = roundup_pow_of_two(crtc_w) * 4;
12002 if (obj->base.size < stride * crtc_h) {
12003 DRM_DEBUG_KMS("buffer is too small\n");
12004 return -ENOMEM;
12005 }
12006
12007 if (fb == crtc->cursor->fb)
12008 return 0;
12009
12010 /* we only need to pin inside GTT if cursor is non-phy */
12011 mutex_lock(&dev->struct_mutex);
12012 if (!INTEL_INFO(dev)->cursor_needs_physical && obj->tiling_mode) {
12013 DRM_DEBUG_KMS("cursor cannot be tiled\n");
12014 ret = -EINVAL;
12015 }
12016 mutex_unlock(&dev->struct_mutex);
12017
12018 return ret;
12019 }
12020
12021 static int
12022 intel_commit_cursor_plane(struct drm_plane *plane,
12023 struct intel_plane_state *state)
12024 {
12025 struct drm_crtc *crtc = state->crtc;
12026 struct drm_framebuffer *fb = state->fb;
12027 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12028 struct intel_plane *intel_plane = to_intel_plane(plane);
12029 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12030 struct drm_i915_gem_object *obj = intel_fb->obj;
12031 int crtc_w, crtc_h;
12032
12033 crtc->cursor_x = state->orig_dst.x1;
12034 crtc->cursor_y = state->orig_dst.y1;
12035
12036 intel_plane->crtc_x = state->orig_dst.x1;
12037 intel_plane->crtc_y = state->orig_dst.y1;
12038 intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
12039 intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
12040 intel_plane->src_x = state->orig_src.x1;
12041 intel_plane->src_y = state->orig_src.y1;
12042 intel_plane->src_w = drm_rect_width(&state->orig_src);
12043 intel_plane->src_h = drm_rect_height(&state->orig_src);
12044 intel_plane->obj = obj;
12045
12046 if (fb != crtc->cursor->fb) {
12047 crtc_w = drm_rect_width(&state->orig_dst);
12048 crtc_h = drm_rect_height(&state->orig_dst);
12049 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
12050 } else {
12051 intel_crtc_update_cursor(crtc, state->visible);
12052
12053 intel_frontbuffer_flip(crtc->dev,
12054 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe));
12055
12056 return 0;
12057 }
12058 }
12059
12060 static int
12061 intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
12062 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
12063 unsigned int crtc_w, unsigned int crtc_h,
12064 uint32_t src_x, uint32_t src_y,
12065 uint32_t src_w, uint32_t src_h)
12066 {
12067 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12068 struct intel_plane_state state;
12069 int ret;
12070
12071 state.crtc = crtc;
12072 state.fb = fb;
12073
12074 /* sample coordinates in 16.16 fixed point */
12075 state.src.x1 = src_x;
12076 state.src.x2 = src_x + src_w;
12077 state.src.y1 = src_y;
12078 state.src.y2 = src_y + src_h;
12079
12080 /* integer pixels */
12081 state.dst.x1 = crtc_x;
12082 state.dst.x2 = crtc_x + crtc_w;
12083 state.dst.y1 = crtc_y;
12084 state.dst.y2 = crtc_y + crtc_h;
12085
12086 state.clip.x1 = 0;
12087 state.clip.y1 = 0;
12088 state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
12089 state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
12090
12091 state.orig_src = state.src;
12092 state.orig_dst = state.dst;
12093
12094 ret = intel_check_cursor_plane(plane, &state);
12095 if (ret)
12096 return ret;
12097
12098 return intel_commit_cursor_plane(plane, &state);
12099 }
12100
12101 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
12102 .update_plane = intel_cursor_plane_update,
12103 .disable_plane = intel_cursor_plane_disable,
12104 .destroy = intel_plane_destroy,
12105 .set_property = intel_plane_set_property,
12106 };
12107
12108 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12109 int pipe)
12110 {
12111 struct intel_plane *cursor;
12112
12113 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12114 if (cursor == NULL)
12115 return NULL;
12116
12117 cursor->can_scale = false;
12118 cursor->max_downscale = 1;
12119 cursor->pipe = pipe;
12120 cursor->plane = pipe;
12121 cursor->rotation = BIT(DRM_ROTATE_0);
12122
12123 drm_universal_plane_init(dev, &cursor->base, 0,
12124 &intel_cursor_plane_funcs,
12125 intel_cursor_formats,
12126 ARRAY_SIZE(intel_cursor_formats),
12127 DRM_PLANE_TYPE_CURSOR);
12128
12129 if (INTEL_INFO(dev)->gen >= 4) {
12130 if (!dev->mode_config.rotation_property)
12131 dev->mode_config.rotation_property =
12132 drm_mode_create_rotation_property(dev,
12133 BIT(DRM_ROTATE_0) |
12134 BIT(DRM_ROTATE_180));
12135 if (dev->mode_config.rotation_property)
12136 drm_object_attach_property(&cursor->base.base,
12137 dev->mode_config.rotation_property,
12138 cursor->rotation);
12139 }
12140
12141 return &cursor->base;
12142 }
12143
12144 static void intel_crtc_init(struct drm_device *dev, int pipe)
12145 {
12146 struct drm_i915_private *dev_priv = dev->dev_private;
12147 struct intel_crtc *intel_crtc;
12148 struct drm_plane *primary = NULL;
12149 struct drm_plane *cursor = NULL;
12150 int i, ret;
12151
12152 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12153 if (intel_crtc == NULL)
12154 return;
12155
12156 primary = intel_primary_plane_create(dev, pipe);
12157 if (!primary)
12158 goto fail;
12159
12160 cursor = intel_cursor_plane_create(dev, pipe);
12161 if (!cursor)
12162 goto fail;
12163
12164 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12165 cursor, &intel_crtc_funcs);
12166 if (ret)
12167 goto fail;
12168
12169 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12170 for (i = 0; i < 256; i++) {
12171 intel_crtc->lut_r[i] = i;
12172 intel_crtc->lut_g[i] = i;
12173 intel_crtc->lut_b[i] = i;
12174 }
12175
12176 /*
12177 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12178 * is hooked to pipe B. Hence we want plane A feeding pipe B.
12179 */
12180 intel_crtc->pipe = pipe;
12181 intel_crtc->plane = pipe;
12182 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12183 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12184 intel_crtc->plane = !pipe;
12185 }
12186
12187 intel_crtc->cursor_base = ~0;
12188 intel_crtc->cursor_cntl = ~0;
12189 intel_crtc->cursor_size = ~0;
12190
12191 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12192 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12193 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12194 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12195
12196 INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
12197
12198 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12199
12200 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12201 return;
12202
12203 fail:
12204 if (primary)
12205 drm_plane_cleanup(primary);
12206 if (cursor)
12207 drm_plane_cleanup(cursor);
12208 kfree(intel_crtc);
12209 }
12210
12211 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12212 {
12213 struct drm_encoder *encoder = connector->base.encoder;
12214 struct drm_device *dev = connector->base.dev;
12215
12216 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12217
12218 if (!encoder || WARN_ON(!encoder->crtc))
12219 return INVALID_PIPE;
12220
12221 return to_intel_crtc(encoder->crtc)->pipe;
12222 }
12223
12224 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12225 struct drm_file *file)
12226 {
12227 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12228 struct drm_crtc *drmmode_crtc;
12229 struct intel_crtc *crtc;
12230
12231 if (!drm_core_check_feature(dev, DRIVER_MODESET))
12232 return -ENODEV;
12233
12234 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12235
12236 if (!drmmode_crtc) {
12237 DRM_ERROR("no such CRTC id\n");
12238 return -ENOENT;
12239 }
12240
12241 crtc = to_intel_crtc(drmmode_crtc);
12242 pipe_from_crtc_id->pipe = crtc->pipe;
12243
12244 return 0;
12245 }
12246
12247 static int intel_encoder_clones(struct intel_encoder *encoder)
12248 {
12249 struct drm_device *dev = encoder->base.dev;
12250 struct intel_encoder *source_encoder;
12251 int index_mask = 0;
12252 int entry = 0;
12253
12254 for_each_intel_encoder(dev, source_encoder) {
12255 if (encoders_cloneable(encoder, source_encoder))
12256 index_mask |= (1 << entry);
12257
12258 entry++;
12259 }
12260
12261 return index_mask;
12262 }
12263
12264 static bool has_edp_a(struct drm_device *dev)
12265 {
12266 struct drm_i915_private *dev_priv = dev->dev_private;
12267
12268 if (!IS_MOBILE(dev))
12269 return false;
12270
12271 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12272 return false;
12273
12274 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12275 return false;
12276
12277 return true;
12278 }
12279
12280 const char *intel_output_name(int output)
12281 {
12282 static const char *names[] = {
12283 [INTEL_OUTPUT_UNUSED] = "Unused",
12284 [INTEL_OUTPUT_ANALOG] = "Analog",
12285 [INTEL_OUTPUT_DVO] = "DVO",
12286 [INTEL_OUTPUT_SDVO] = "SDVO",
12287 [INTEL_OUTPUT_LVDS] = "LVDS",
12288 [INTEL_OUTPUT_TVOUT] = "TV",
12289 [INTEL_OUTPUT_HDMI] = "HDMI",
12290 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
12291 [INTEL_OUTPUT_EDP] = "eDP",
12292 [INTEL_OUTPUT_DSI] = "DSI",
12293 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
12294 };
12295
12296 if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
12297 return "Invalid";
12298
12299 return names[output];
12300 }
12301
12302 static bool intel_crt_present(struct drm_device *dev)
12303 {
12304 struct drm_i915_private *dev_priv = dev->dev_private;
12305
12306 if (INTEL_INFO(dev)->gen >= 9)
12307 return false;
12308
12309 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12310 return false;
12311
12312 if (IS_CHERRYVIEW(dev))
12313 return false;
12314
12315 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12316 return false;
12317
12318 return true;
12319 }
12320
12321 static void intel_setup_outputs(struct drm_device *dev)
12322 {
12323 struct drm_i915_private *dev_priv = dev->dev_private;
12324 struct intel_encoder *encoder;
12325 bool dpd_is_edp = false;
12326
12327 intel_lvds_init(dev);
12328
12329 if (intel_crt_present(dev))
12330 intel_crt_init(dev);
12331
12332 if (HAS_DDI(dev)) {
12333 int found;
12334
12335 /* Haswell uses DDI functions to detect digital outputs */
12336 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12337 /* DDI A only supports eDP */
12338 if (found)
12339 intel_ddi_init(dev, PORT_A);
12340
12341 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12342 * register */
12343 found = I915_READ(SFUSE_STRAP);
12344
12345 if (found & SFUSE_STRAP_DDIB_DETECTED)
12346 intel_ddi_init(dev, PORT_B);
12347 if (found & SFUSE_STRAP_DDIC_DETECTED)
12348 intel_ddi_init(dev, PORT_C);
12349 if (found & SFUSE_STRAP_DDID_DETECTED)
12350 intel_ddi_init(dev, PORT_D);
12351 } else if (HAS_PCH_SPLIT(dev)) {
12352 int found;
12353 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12354
12355 if (has_edp_a(dev))
12356 intel_dp_init(dev, DP_A, PORT_A);
12357
12358 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12359 /* PCH SDVOB multiplex with HDMIB */
12360 found = intel_sdvo_init(dev, PCH_SDVOB, true);
12361 if (!found)
12362 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12363 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12364 intel_dp_init(dev, PCH_DP_B, PORT_B);
12365 }
12366
12367 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12368 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12369
12370 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12371 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12372
12373 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12374 intel_dp_init(dev, PCH_DP_C, PORT_C);
12375
12376 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12377 intel_dp_init(dev, PCH_DP_D, PORT_D);
12378 } else if (IS_VALLEYVIEW(dev)) {
12379 /*
12380 * The DP_DETECTED bit is the latched state of the DDC
12381 * SDA pin at boot. However since eDP doesn't require DDC
12382 * (no way to plug in a DP->HDMI dongle) the DDC pins for
12383 * eDP ports may have been muxed to an alternate function.
12384 * Thus we can't rely on the DP_DETECTED bit alone to detect
12385 * eDP ports. Consult the VBT as well as DP_DETECTED to
12386 * detect eDP ports.
12387 */
12388 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED)
12389 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12390 PORT_B);
12391 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12392 intel_dp_is_edp(dev, PORT_B))
12393 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12394
12395 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED)
12396 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12397 PORT_C);
12398 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12399 intel_dp_is_edp(dev, PORT_C))
12400 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12401
12402 if (IS_CHERRYVIEW(dev)) {
12403 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12404 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12405 PORT_D);
12406 /* eDP not supported on port D, so don't check VBT */
12407 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12408 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12409 }
12410
12411 intel_dsi_init(dev);
12412 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12413 bool found = false;
12414
12415 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12416 DRM_DEBUG_KMS("probing SDVOB\n");
12417 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12418 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12419 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12420 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12421 }
12422
12423 if (!found && SUPPORTS_INTEGRATED_DP(dev))
12424 intel_dp_init(dev, DP_B, PORT_B);
12425 }
12426
12427 /* Before G4X SDVOC doesn't have its own detect register */
12428
12429 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12430 DRM_DEBUG_KMS("probing SDVOC\n");
12431 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12432 }
12433
12434 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12435
12436 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12437 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12438 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12439 }
12440 if (SUPPORTS_INTEGRATED_DP(dev))
12441 intel_dp_init(dev, DP_C, PORT_C);
12442 }
12443
12444 if (SUPPORTS_INTEGRATED_DP(dev) &&
12445 (I915_READ(DP_D) & DP_DETECTED))
12446 intel_dp_init(dev, DP_D, PORT_D);
12447 } else if (IS_GEN2(dev))
12448 intel_dvo_init(dev);
12449
12450 if (SUPPORTS_TV(dev))
12451 intel_tv_init(dev);
12452
12453 intel_psr_init(dev);
12454
12455 for_each_intel_encoder(dev, encoder) {
12456 encoder->base.possible_crtcs = encoder->crtc_mask;
12457 encoder->base.possible_clones =
12458 intel_encoder_clones(encoder);
12459 }
12460
12461 intel_init_pch_refclk(dev);
12462
12463 drm_helper_move_panel_connectors_to_head(dev);
12464 }
12465
12466 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12467 {
12468 struct drm_device *dev = fb->dev;
12469 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12470
12471 drm_framebuffer_cleanup(fb);
12472 mutex_lock(&dev->struct_mutex);
12473 WARN_ON(!intel_fb->obj->framebuffer_references--);
12474 drm_gem_object_unreference(&intel_fb->obj->base);
12475 mutex_unlock(&dev->struct_mutex);
12476 kfree(intel_fb);
12477 }
12478
12479 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12480 struct drm_file *file,
12481 unsigned int *handle)
12482 {
12483 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12484 struct drm_i915_gem_object *obj = intel_fb->obj;
12485
12486 return drm_gem_handle_create(file, &obj->base, handle);
12487 }
12488
12489 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12490 .destroy = intel_user_framebuffer_destroy,
12491 .create_handle = intel_user_framebuffer_create_handle,
12492 };
12493
12494 static int intel_framebuffer_init(struct drm_device *dev,
12495 struct intel_framebuffer *intel_fb,
12496 struct drm_mode_fb_cmd2 *mode_cmd,
12497 struct drm_i915_gem_object *obj)
12498 {
12499 int aligned_height;
12500 int pitch_limit;
12501 int ret;
12502
12503 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12504
12505 if (obj->tiling_mode == I915_TILING_Y) {
12506 DRM_DEBUG("hardware does not support tiling Y\n");
12507 return -EINVAL;
12508 }
12509
12510 if (mode_cmd->pitches[0] & 63) {
12511 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12512 mode_cmd->pitches[0]);
12513 return -EINVAL;
12514 }
12515
12516 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12517 pitch_limit = 32*1024;
12518 } else if (INTEL_INFO(dev)->gen >= 4) {
12519 if (obj->tiling_mode)
12520 pitch_limit = 16*1024;
12521 else
12522 pitch_limit = 32*1024;
12523 } else if (INTEL_INFO(dev)->gen >= 3) {
12524 if (obj->tiling_mode)
12525 pitch_limit = 8*1024;
12526 else
12527 pitch_limit = 16*1024;
12528 } else
12529 /* XXX DSPC is limited to 4k tiled */
12530 pitch_limit = 8*1024;
12531
12532 if (mode_cmd->pitches[0] > pitch_limit) {
12533 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12534 obj->tiling_mode ? "tiled" : "linear",
12535 mode_cmd->pitches[0], pitch_limit);
12536 return -EINVAL;
12537 }
12538
12539 if (obj->tiling_mode != I915_TILING_NONE &&
12540 mode_cmd->pitches[0] != obj->stride) {
12541 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12542 mode_cmd->pitches[0], obj->stride);
12543 return -EINVAL;
12544 }
12545
12546 /* Reject formats not supported by any plane early. */
12547 switch (mode_cmd->pixel_format) {
12548 case DRM_FORMAT_C8:
12549 case DRM_FORMAT_RGB565:
12550 case DRM_FORMAT_XRGB8888:
12551 case DRM_FORMAT_ARGB8888:
12552 break;
12553 case DRM_FORMAT_XRGB1555:
12554 case DRM_FORMAT_ARGB1555:
12555 if (INTEL_INFO(dev)->gen > 3) {
12556 DRM_DEBUG("unsupported pixel format: %s\n",
12557 drm_get_format_name(mode_cmd->pixel_format));
12558 return -EINVAL;
12559 }
12560 break;
12561 case DRM_FORMAT_XBGR8888:
12562 case DRM_FORMAT_ABGR8888:
12563 case DRM_FORMAT_XRGB2101010:
12564 case DRM_FORMAT_ARGB2101010:
12565 case DRM_FORMAT_XBGR2101010:
12566 case DRM_FORMAT_ABGR2101010:
12567 if (INTEL_INFO(dev)->gen < 4) {
12568 DRM_DEBUG("unsupported pixel format: %s\n",
12569 drm_get_format_name(mode_cmd->pixel_format));
12570 return -EINVAL;
12571 }
12572 break;
12573 case DRM_FORMAT_YUYV:
12574 case DRM_FORMAT_UYVY:
12575 case DRM_FORMAT_YVYU:
12576 case DRM_FORMAT_VYUY:
12577 if (INTEL_INFO(dev)->gen < 5) {
12578 DRM_DEBUG("unsupported pixel format: %s\n",
12579 drm_get_format_name(mode_cmd->pixel_format));
12580 return -EINVAL;
12581 }
12582 break;
12583 default:
12584 DRM_DEBUG("unsupported pixel format: %s\n",
12585 drm_get_format_name(mode_cmd->pixel_format));
12586 return -EINVAL;
12587 }
12588
12589 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12590 if (mode_cmd->offsets[0] != 0)
12591 return -EINVAL;
12592
12593 aligned_height = intel_align_height(dev, mode_cmd->height,
12594 obj->tiling_mode);
12595 /* FIXME drm helper for size checks (especially planar formats)? */
12596 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12597 return -EINVAL;
12598
12599 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12600 intel_fb->obj = obj;
12601 intel_fb->obj->framebuffer_references++;
12602
12603 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12604 if (ret) {
12605 DRM_ERROR("framebuffer init failed %d\n", ret);
12606 return ret;
12607 }
12608
12609 return 0;
12610 }
12611
12612 static struct drm_framebuffer *
12613 intel_user_framebuffer_create(struct drm_device *dev,
12614 struct drm_file *filp,
12615 struct drm_mode_fb_cmd2 *mode_cmd)
12616 {
12617 struct drm_i915_gem_object *obj;
12618
12619 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12620 mode_cmd->handles[0]));
12621 if (&obj->base == NULL)
12622 return ERR_PTR(-ENOENT);
12623
12624 return intel_framebuffer_create(dev, mode_cmd, obj);
12625 }
12626
12627 #ifndef CONFIG_DRM_I915_FBDEV
12628 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12629 {
12630 }
12631 #endif
12632
12633 static const struct drm_mode_config_funcs intel_mode_funcs = {
12634 .fb_create = intel_user_framebuffer_create,
12635 .output_poll_changed = intel_fbdev_output_poll_changed,
12636 };
12637
12638 /* Set up chip specific display functions */
12639 static void intel_init_display(struct drm_device *dev)
12640 {
12641 struct drm_i915_private *dev_priv = dev->dev_private;
12642
12643 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12644 dev_priv->display.find_dpll = g4x_find_best_dpll;
12645 else if (IS_CHERRYVIEW(dev))
12646 dev_priv->display.find_dpll = chv_find_best_dpll;
12647 else if (IS_VALLEYVIEW(dev))
12648 dev_priv->display.find_dpll = vlv_find_best_dpll;
12649 else if (IS_PINEVIEW(dev))
12650 dev_priv->display.find_dpll = pnv_find_best_dpll;
12651 else
12652 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12653
12654 if (HAS_DDI(dev)) {
12655 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12656 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12657 dev_priv->display.crtc_compute_clock =
12658 haswell_crtc_compute_clock;
12659 dev_priv->display.crtc_enable = haswell_crtc_enable;
12660 dev_priv->display.crtc_disable = haswell_crtc_disable;
12661 dev_priv->display.off = ironlake_crtc_off;
12662 if (INTEL_INFO(dev)->gen >= 9)
12663 dev_priv->display.update_primary_plane =
12664 skylake_update_primary_plane;
12665 else
12666 dev_priv->display.update_primary_plane =
12667 ironlake_update_primary_plane;
12668 } else if (HAS_PCH_SPLIT(dev)) {
12669 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12670 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12671 dev_priv->display.crtc_compute_clock =
12672 ironlake_crtc_compute_clock;
12673 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12674 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12675 dev_priv->display.off = ironlake_crtc_off;
12676 dev_priv->display.update_primary_plane =
12677 ironlake_update_primary_plane;
12678 } else if (IS_VALLEYVIEW(dev)) {
12679 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12680 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12681 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
12682 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12683 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12684 dev_priv->display.off = i9xx_crtc_off;
12685 dev_priv->display.update_primary_plane =
12686 i9xx_update_primary_plane;
12687 } else {
12688 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12689 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12690 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
12691 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12692 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12693 dev_priv->display.off = i9xx_crtc_off;
12694 dev_priv->display.update_primary_plane =
12695 i9xx_update_primary_plane;
12696 }
12697
12698 /* Returns the core display clock speed */
12699 if (IS_VALLEYVIEW(dev))
12700 dev_priv->display.get_display_clock_speed =
12701 valleyview_get_display_clock_speed;
12702 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12703 dev_priv->display.get_display_clock_speed =
12704 i945_get_display_clock_speed;
12705 else if (IS_I915G(dev))
12706 dev_priv->display.get_display_clock_speed =
12707 i915_get_display_clock_speed;
12708 else if (IS_I945GM(dev) || IS_845G(dev))
12709 dev_priv->display.get_display_clock_speed =
12710 i9xx_misc_get_display_clock_speed;
12711 else if (IS_PINEVIEW(dev))
12712 dev_priv->display.get_display_clock_speed =
12713 pnv_get_display_clock_speed;
12714 else if (IS_I915GM(dev))
12715 dev_priv->display.get_display_clock_speed =
12716 i915gm_get_display_clock_speed;
12717 else if (IS_I865G(dev))
12718 dev_priv->display.get_display_clock_speed =
12719 i865_get_display_clock_speed;
12720 else if (IS_I85X(dev))
12721 dev_priv->display.get_display_clock_speed =
12722 i855_get_display_clock_speed;
12723 else /* 852, 830 */
12724 dev_priv->display.get_display_clock_speed =
12725 i830_get_display_clock_speed;
12726
12727 if (IS_GEN5(dev)) {
12728 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12729 } else if (IS_GEN6(dev)) {
12730 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12731 } else if (IS_IVYBRIDGE(dev)) {
12732 /* FIXME: detect B0+ stepping and use auto training */
12733 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12734 dev_priv->display.modeset_global_resources =
12735 ivb_modeset_global_resources;
12736 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12737 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12738 } else if (IS_VALLEYVIEW(dev)) {
12739 dev_priv->display.modeset_global_resources =
12740 valleyview_modeset_global_resources;
12741 }
12742
12743 /* Default just returns -ENODEV to indicate unsupported */
12744 dev_priv->display.queue_flip = intel_default_queue_flip;
12745
12746 switch (INTEL_INFO(dev)->gen) {
12747 case 2:
12748 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12749 break;
12750
12751 case 3:
12752 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12753 break;
12754
12755 case 4:
12756 case 5:
12757 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12758 break;
12759
12760 case 6:
12761 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12762 break;
12763 case 7:
12764 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12765 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12766 break;
12767 case 9:
12768 dev_priv->display.queue_flip = intel_gen9_queue_flip;
12769 break;
12770 }
12771
12772 intel_panel_init_backlight_funcs(dev);
12773
12774 mutex_init(&dev_priv->pps_mutex);
12775 }
12776
12777 /*
12778 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12779 * resume, or other times. This quirk makes sure that's the case for
12780 * affected systems.
12781 */
12782 static void quirk_pipea_force(struct drm_device *dev)
12783 {
12784 struct drm_i915_private *dev_priv = dev->dev_private;
12785
12786 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12787 DRM_INFO("applying pipe a force quirk\n");
12788 }
12789
12790 static void quirk_pipeb_force(struct drm_device *dev)
12791 {
12792 struct drm_i915_private *dev_priv = dev->dev_private;
12793
12794 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
12795 DRM_INFO("applying pipe b force quirk\n");
12796 }
12797
12798 /*
12799 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12800 */
12801 static void quirk_ssc_force_disable(struct drm_device *dev)
12802 {
12803 struct drm_i915_private *dev_priv = dev->dev_private;
12804 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12805 DRM_INFO("applying lvds SSC disable quirk\n");
12806 }
12807
12808 /*
12809 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12810 * brightness value
12811 */
12812 static void quirk_invert_brightness(struct drm_device *dev)
12813 {
12814 struct drm_i915_private *dev_priv = dev->dev_private;
12815 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
12816 DRM_INFO("applying inverted panel brightness quirk\n");
12817 }
12818
12819 /* Some VBT's incorrectly indicate no backlight is present */
12820 static void quirk_backlight_present(struct drm_device *dev)
12821 {
12822 struct drm_i915_private *dev_priv = dev->dev_private;
12823 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
12824 DRM_INFO("applying backlight present quirk\n");
12825 }
12826
12827 struct intel_quirk {
12828 int device;
12829 int subsystem_vendor;
12830 int subsystem_device;
12831 void (*hook)(struct drm_device *dev);
12832 };
12833
12834 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12835 struct intel_dmi_quirk {
12836 void (*hook)(struct drm_device *dev);
12837 const struct dmi_system_id (*dmi_id_list)[];
12838 };
12839
12840 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12841 {
12842 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12843 return 1;
12844 }
12845
12846 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12847 {
12848 .dmi_id_list = &(const struct dmi_system_id[]) {
12849 {
12850 .callback = intel_dmi_reverse_brightness,
12851 .ident = "NCR Corporation",
12852 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12853 DMI_MATCH(DMI_PRODUCT_NAME, ""),
12854 },
12855 },
12856 { } /* terminating entry */
12857 },
12858 .hook = quirk_invert_brightness,
12859 },
12860 };
12861
12862 static struct intel_quirk intel_quirks[] = {
12863 /* HP Mini needs pipe A force quirk (LP: #322104) */
12864 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
12865
12866 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12867 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12868
12869 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12870 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12871
12872 /* 830 needs to leave pipe A & dpll A up */
12873 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
12874
12875 /* 830 needs to leave pipe B & dpll B up */
12876 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
12877
12878 /* Lenovo U160 cannot use SSC on LVDS */
12879 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
12880
12881 /* Sony Vaio Y cannot use SSC on LVDS */
12882 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
12883
12884 /* Acer Aspire 5734Z must invert backlight brightness */
12885 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12886
12887 /* Acer/eMachines G725 */
12888 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12889
12890 /* Acer/eMachines e725 */
12891 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12892
12893 /* Acer/Packard Bell NCL20 */
12894 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12895
12896 /* Acer Aspire 4736Z */
12897 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
12898
12899 /* Acer Aspire 5336 */
12900 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
12901
12902 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12903 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
12904
12905 /* Acer C720 Chromebook (Core i3 4005U) */
12906 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
12907
12908 /* Apple Macbook 2,1 (Core 2 T7400) */
12909 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
12910
12911 /* Toshiba CB35 Chromebook (Celeron 2955U) */
12912 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
12913
12914 /* HP Chromebook 14 (Celeron 2955U) */
12915 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
12916 };
12917
12918 static void intel_init_quirks(struct drm_device *dev)
12919 {
12920 struct pci_dev *d = dev->pdev;
12921 int i;
12922
12923 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12924 struct intel_quirk *q = &intel_quirks[i];
12925
12926 if (d->device == q->device &&
12927 (d->subsystem_vendor == q->subsystem_vendor ||
12928 q->subsystem_vendor == PCI_ANY_ID) &&
12929 (d->subsystem_device == q->subsystem_device ||
12930 q->subsystem_device == PCI_ANY_ID))
12931 q->hook(dev);
12932 }
12933 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12934 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12935 intel_dmi_quirks[i].hook(dev);
12936 }
12937 }
12938
12939 /* Disable the VGA plane that we never use */
12940 static void i915_disable_vga(struct drm_device *dev)
12941 {
12942 struct drm_i915_private *dev_priv = dev->dev_private;
12943 u8 sr1;
12944 u32 vga_reg = i915_vgacntrl_reg(dev);
12945
12946 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12947 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
12948 outb(SR01, VGA_SR_INDEX);
12949 sr1 = inb(VGA_SR_DATA);
12950 outb(sr1 | 1<<5, VGA_SR_DATA);
12951 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12952 udelay(300);
12953
12954 /*
12955 * Fujitsu-Siemens Lifebook S6010 (830) has problems resuming
12956 * from S3 without preserving (some of?) the other bits.
12957 */
12958 I915_WRITE(vga_reg, dev_priv->bios_vgacntr | VGA_DISP_DISABLE);
12959 POSTING_READ(vga_reg);
12960 }
12961
12962 void intel_modeset_init_hw(struct drm_device *dev)
12963 {
12964 intel_prepare_ddi(dev);
12965
12966 if (IS_VALLEYVIEW(dev))
12967 vlv_update_cdclk(dev);
12968
12969 intel_init_clock_gating(dev);
12970
12971 intel_enable_gt_powersave(dev);
12972 }
12973
12974 void intel_modeset_init(struct drm_device *dev)
12975 {
12976 struct drm_i915_private *dev_priv = dev->dev_private;
12977 int sprite, ret;
12978 enum pipe pipe;
12979 struct intel_crtc *crtc;
12980
12981 drm_mode_config_init(dev);
12982
12983 dev->mode_config.min_width = 0;
12984 dev->mode_config.min_height = 0;
12985
12986 dev->mode_config.preferred_depth = 24;
12987 dev->mode_config.prefer_shadow = 1;
12988
12989 dev->mode_config.funcs = &intel_mode_funcs;
12990
12991 intel_init_quirks(dev);
12992
12993 intel_init_pm(dev);
12994
12995 if (INTEL_INFO(dev)->num_pipes == 0)
12996 return;
12997
12998 intel_init_display(dev);
12999 intel_init_audio(dev);
13000
13001 if (IS_GEN2(dev)) {
13002 dev->mode_config.max_width = 2048;
13003 dev->mode_config.max_height = 2048;
13004 } else if (IS_GEN3(dev)) {
13005 dev->mode_config.max_width = 4096;
13006 dev->mode_config.max_height = 4096;
13007 } else {
13008 dev->mode_config.max_width = 8192;
13009 dev->mode_config.max_height = 8192;
13010 }
13011
13012 if (IS_845G(dev) || IS_I865G(dev)) {
13013 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
13014 dev->mode_config.cursor_height = 1023;
13015 } else if (IS_GEN2(dev)) {
13016 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
13017 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
13018 } else {
13019 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
13020 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
13021 }
13022
13023 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
13024
13025 DRM_DEBUG_KMS("%d display pipe%s available.\n",
13026 INTEL_INFO(dev)->num_pipes,
13027 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
13028
13029 for_each_pipe(dev_priv, pipe) {
13030 intel_crtc_init(dev, pipe);
13031 for_each_sprite(pipe, sprite) {
13032 ret = intel_plane_init(dev, pipe, sprite);
13033 if (ret)
13034 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
13035 pipe_name(pipe), sprite_name(pipe, sprite), ret);
13036 }
13037 }
13038
13039 intel_init_dpio(dev);
13040
13041 intel_shared_dpll_init(dev);
13042
13043 /* save the BIOS value before clobbering it */
13044 dev_priv->bios_vgacntr = I915_READ(i915_vgacntrl_reg(dev));
13045 /* Just disable it once at startup */
13046 i915_disable_vga(dev);
13047 intel_setup_outputs(dev);
13048
13049 /* Just in case the BIOS is doing something questionable. */
13050 intel_disable_fbc(dev);
13051
13052 drm_modeset_lock_all(dev);
13053 intel_modeset_setup_hw_state(dev, false);
13054 drm_modeset_unlock_all(dev);
13055
13056 for_each_intel_crtc(dev, crtc) {
13057 if (!crtc->active)
13058 continue;
13059
13060 /*
13061 * Note that reserving the BIOS fb up front prevents us
13062 * from stuffing other stolen allocations like the ring
13063 * on top. This prevents some ugliness at boot time, and
13064 * can even allow for smooth boot transitions if the BIOS
13065 * fb is large enough for the active pipe configuration.
13066 */
13067 if (dev_priv->display.get_plane_config) {
13068 dev_priv->display.get_plane_config(crtc,
13069 &crtc->plane_config);
13070 /*
13071 * If the fb is shared between multiple heads, we'll
13072 * just get the first one.
13073 */
13074 intel_find_plane_obj(crtc, &crtc->plane_config);
13075 }
13076 }
13077 }
13078
13079 static void intel_enable_pipe_a(struct drm_device *dev)
13080 {
13081 struct intel_connector *connector;
13082 struct drm_connector *crt = NULL;
13083 struct intel_load_detect_pipe load_detect_temp;
13084 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
13085
13086 /* We can't just switch on the pipe A, we need to set things up with a
13087 * proper mode and output configuration. As a gross hack, enable pipe A
13088 * by enabling the load detect pipe once. */
13089 list_for_each_entry(connector,
13090 &dev->mode_config.connector_list,
13091 base.head) {
13092 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13093 crt = &connector->base;
13094 break;
13095 }
13096 }
13097
13098 if (!crt)
13099 return;
13100
13101 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13102 intel_release_load_detect_pipe(crt, &load_detect_temp);
13103 }
13104
13105 static bool
13106 intel_check_plane_mapping(struct intel_crtc *crtc)
13107 {
13108 struct drm_device *dev = crtc->base.dev;
13109 struct drm_i915_private *dev_priv = dev->dev_private;
13110 u32 reg, val;
13111
13112 if (INTEL_INFO(dev)->num_pipes == 1)
13113 return true;
13114
13115 reg = DSPCNTR(!crtc->plane);
13116 val = I915_READ(reg);
13117
13118 if ((val & DISPLAY_PLANE_ENABLE) &&
13119 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13120 return false;
13121
13122 return true;
13123 }
13124
13125 static void intel_sanitize_crtc(struct intel_crtc *crtc)
13126 {
13127 struct drm_device *dev = crtc->base.dev;
13128 struct drm_i915_private *dev_priv = dev->dev_private;
13129 u32 reg;
13130
13131 /* Clear any frame start delays used for debugging left by the BIOS */
13132 reg = PIPECONF(crtc->config.cpu_transcoder);
13133 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13134
13135 /* restore vblank interrupts to correct state */
13136 if (crtc->active) {
13137 update_scanline_offset(crtc);
13138 drm_vblank_on(dev, crtc->pipe);
13139 } else
13140 drm_vblank_off(dev, crtc->pipe);
13141
13142 /* We need to sanitize the plane -> pipe mapping first because this will
13143 * disable the crtc (and hence change the state) if it is wrong. Note
13144 * that gen4+ has a fixed plane -> pipe mapping. */
13145 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13146 struct intel_connector *connector;
13147 bool plane;
13148
13149 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13150 crtc->base.base.id);
13151
13152 /* Pipe has the wrong plane attached and the plane is active.
13153 * Temporarily change the plane mapping and disable everything
13154 * ... */
13155 plane = crtc->plane;
13156 crtc->plane = !plane;
13157 crtc->primary_enabled = true;
13158 dev_priv->display.crtc_disable(&crtc->base);
13159 crtc->plane = plane;
13160
13161 /* ... and break all links. */
13162 list_for_each_entry(connector, &dev->mode_config.connector_list,
13163 base.head) {
13164 if (connector->encoder->base.crtc != &crtc->base)
13165 continue;
13166
13167 connector->base.dpms = DRM_MODE_DPMS_OFF;
13168 connector->base.encoder = NULL;
13169 }
13170 /* multiple connectors may have the same encoder:
13171 * handle them and break crtc link separately */
13172 list_for_each_entry(connector, &dev->mode_config.connector_list,
13173 base.head)
13174 if (connector->encoder->base.crtc == &crtc->base) {
13175 connector->encoder->base.crtc = NULL;
13176 connector->encoder->connectors_active = false;
13177 }
13178
13179 WARN_ON(crtc->active);
13180 crtc->base.enabled = false;
13181 }
13182
13183 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13184 crtc->pipe == PIPE_A && !crtc->active) {
13185 /* BIOS forgot to enable pipe A, this mostly happens after
13186 * resume. Force-enable the pipe to fix this, the update_dpms
13187 * call below we restore the pipe to the right state, but leave
13188 * the required bits on. */
13189 intel_enable_pipe_a(dev);
13190 }
13191
13192 /* Adjust the state of the output pipe according to whether we
13193 * have active connectors/encoders. */
13194 intel_crtc_update_dpms(&crtc->base);
13195
13196 if (crtc->active != crtc->base.enabled) {
13197 struct intel_encoder *encoder;
13198
13199 /* This can happen either due to bugs in the get_hw_state
13200 * functions or because the pipe is force-enabled due to the
13201 * pipe A quirk. */
13202 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13203 crtc->base.base.id,
13204 crtc->base.enabled ? "enabled" : "disabled",
13205 crtc->active ? "enabled" : "disabled");
13206
13207 crtc->base.enabled = crtc->active;
13208
13209 /* Because we only establish the connector -> encoder ->
13210 * crtc links if something is active, this means the
13211 * crtc is now deactivated. Break the links. connector
13212 * -> encoder links are only establish when things are
13213 * actually up, hence no need to break them. */
13214 WARN_ON(crtc->active);
13215
13216 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13217 WARN_ON(encoder->connectors_active);
13218 encoder->base.crtc = NULL;
13219 }
13220 }
13221
13222 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13223 /*
13224 * We start out with underrun reporting disabled to avoid races.
13225 * For correct bookkeeping mark this on active crtcs.
13226 *
13227 * Also on gmch platforms we dont have any hardware bits to
13228 * disable the underrun reporting. Which means we need to start
13229 * out with underrun reporting disabled also on inactive pipes,
13230 * since otherwise we'll complain about the garbage we read when
13231 * e.g. coming up after runtime pm.
13232 *
13233 * No protection against concurrent access is required - at
13234 * worst a fifo underrun happens which also sets this to false.
13235 */
13236 crtc->cpu_fifo_underrun_disabled = true;
13237 crtc->pch_fifo_underrun_disabled = true;
13238 }
13239 }
13240
13241 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13242 {
13243 struct intel_connector *connector;
13244 struct drm_device *dev = encoder->base.dev;
13245
13246 /* We need to check both for a crtc link (meaning that the
13247 * encoder is active and trying to read from a pipe) and the
13248 * pipe itself being active. */
13249 bool has_active_crtc = encoder->base.crtc &&
13250 to_intel_crtc(encoder->base.crtc)->active;
13251
13252 if (encoder->connectors_active && !has_active_crtc) {
13253 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13254 encoder->base.base.id,
13255 encoder->base.name);
13256
13257 /* Connector is active, but has no active pipe. This is
13258 * fallout from our resume register restoring. Disable
13259 * the encoder manually again. */
13260 if (encoder->base.crtc) {
13261 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13262 encoder->base.base.id,
13263 encoder->base.name);
13264 encoder->disable(encoder);
13265 if (encoder->post_disable)
13266 encoder->post_disable(encoder);
13267 }
13268 encoder->base.crtc = NULL;
13269 encoder->connectors_active = false;
13270
13271 /* Inconsistent output/port/pipe state happens presumably due to
13272 * a bug in one of the get_hw_state functions. Or someplace else
13273 * in our code, like the register restore mess on resume. Clamp
13274 * things to off as a safer default. */
13275 list_for_each_entry(connector,
13276 &dev->mode_config.connector_list,
13277 base.head) {
13278 if (connector->encoder != encoder)
13279 continue;
13280 connector->base.dpms = DRM_MODE_DPMS_OFF;
13281 connector->base.encoder = NULL;
13282 }
13283 }
13284 /* Enabled encoders without active connectors will be fixed in
13285 * the crtc fixup. */
13286 }
13287
13288 void i915_redisable_vga_power_on(struct drm_device *dev)
13289 {
13290 struct drm_i915_private *dev_priv = dev->dev_private;
13291 u32 vga_reg = i915_vgacntrl_reg(dev);
13292
13293 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13294 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13295 i915_disable_vga(dev);
13296 }
13297 }
13298
13299 void i915_redisable_vga(struct drm_device *dev)
13300 {
13301 struct drm_i915_private *dev_priv = dev->dev_private;
13302
13303 /* This function can be called both from intel_modeset_setup_hw_state or
13304 * at a very early point in our resume sequence, where the power well
13305 * structures are not yet restored. Since this function is at a very
13306 * paranoid "someone might have enabled VGA while we were not looking"
13307 * level, just check if the power well is enabled instead of trying to
13308 * follow the "don't touch the power well if we don't need it" policy
13309 * the rest of the driver uses. */
13310 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
13311 return;
13312
13313 i915_redisable_vga_power_on(dev);
13314 }
13315
13316 static bool primary_get_hw_state(struct intel_crtc *crtc)
13317 {
13318 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13319
13320 if (!crtc->active)
13321 return false;
13322
13323 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13324 }
13325
13326 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13327 {
13328 struct drm_i915_private *dev_priv = dev->dev_private;
13329 enum pipe pipe;
13330 struct intel_crtc *crtc;
13331 struct intel_encoder *encoder;
13332 struct intel_connector *connector;
13333 int i;
13334
13335 for_each_intel_crtc(dev, crtc) {
13336 memset(&crtc->config, 0, sizeof(crtc->config));
13337
13338 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13339
13340 crtc->active = dev_priv->display.get_pipe_config(crtc,
13341 &crtc->config);
13342
13343 crtc->base.enabled = crtc->active;
13344 crtc->primary_enabled = primary_get_hw_state(crtc);
13345
13346 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13347 crtc->base.base.id,
13348 crtc->active ? "enabled" : "disabled");
13349 }
13350
13351 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13352 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13353
13354 pll->on = pll->get_hw_state(dev_priv, pll,
13355 &pll->config.hw_state);
13356 pll->active = 0;
13357 pll->config.crtc_mask = 0;
13358 for_each_intel_crtc(dev, crtc) {
13359 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
13360 pll->active++;
13361 pll->config.crtc_mask |= 1 << crtc->pipe;
13362 }
13363 }
13364
13365 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
13366 pll->name, pll->config.crtc_mask, pll->on);
13367
13368 if (pll->config.crtc_mask)
13369 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13370 }
13371
13372 for_each_intel_encoder(dev, encoder) {
13373 pipe = 0;
13374
13375 if (encoder->get_hw_state(encoder, &pipe)) {
13376 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13377 encoder->base.crtc = &crtc->base;
13378 encoder->get_config(encoder, &crtc->config);
13379 } else {
13380 encoder->base.crtc = NULL;
13381 }
13382
13383 encoder->connectors_active = false;
13384 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13385 encoder->base.base.id,
13386 encoder->base.name,
13387 encoder->base.crtc ? "enabled" : "disabled",
13388 pipe_name(pipe));
13389 }
13390
13391 list_for_each_entry(connector, &dev->mode_config.connector_list,
13392 base.head) {
13393 if (connector->get_hw_state(connector)) {
13394 connector->base.dpms = DRM_MODE_DPMS_ON;
13395 connector->encoder->connectors_active = true;
13396 connector->base.encoder = &connector->encoder->base;
13397 } else {
13398 connector->base.dpms = DRM_MODE_DPMS_OFF;
13399 connector->base.encoder = NULL;
13400 }
13401 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13402 connector->base.base.id,
13403 connector->base.name,
13404 connector->base.encoder ? "enabled" : "disabled");
13405 }
13406 }
13407
13408 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13409 * and i915 state tracking structures. */
13410 void intel_modeset_setup_hw_state(struct drm_device *dev,
13411 bool force_restore)
13412 {
13413 struct drm_i915_private *dev_priv = dev->dev_private;
13414 enum pipe pipe;
13415 struct intel_crtc *crtc;
13416 struct intel_encoder *encoder;
13417 int i;
13418
13419 intel_modeset_readout_hw_state(dev);
13420
13421 /*
13422 * Now that we have the config, copy it to each CRTC struct
13423 * Note that this could go away if we move to using crtc_config
13424 * checking everywhere.
13425 */
13426 for_each_intel_crtc(dev, crtc) {
13427 if (crtc->active && i915.fastboot) {
13428 intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
13429 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13430 crtc->base.base.id);
13431 drm_mode_debug_printmodeline(&crtc->base.mode);
13432 }
13433 }
13434
13435 /* HW state is read out, now we need to sanitize this mess. */
13436 for_each_intel_encoder(dev, encoder) {
13437 intel_sanitize_encoder(encoder);
13438 }
13439
13440 for_each_pipe(dev_priv, pipe) {
13441 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13442 intel_sanitize_crtc(crtc);
13443 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
13444 }
13445
13446 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13447 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13448
13449 if (!pll->on || pll->active)
13450 continue;
13451
13452 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13453
13454 pll->disable(dev_priv, pll);
13455 pll->on = false;
13456 }
13457
13458 if (IS_GEN9(dev))
13459 skl_wm_get_hw_state(dev);
13460 else if (HAS_PCH_SPLIT(dev))
13461 ilk_wm_get_hw_state(dev);
13462
13463 if (force_restore) {
13464 i915_redisable_vga(dev);
13465
13466 /*
13467 * We need to use raw interfaces for restoring state to avoid
13468 * checking (bogus) intermediate states.
13469 */
13470 for_each_pipe(dev_priv, pipe) {
13471 struct drm_crtc *crtc =
13472 dev_priv->pipe_to_crtc_mapping[pipe];
13473
13474 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13475 crtc->primary->fb);
13476 }
13477 } else {
13478 intel_modeset_update_staged_output_state(dev);
13479 }
13480
13481 intel_modeset_check_state(dev);
13482 }
13483
13484 void intel_modeset_gem_init(struct drm_device *dev)
13485 {
13486 struct drm_i915_private *dev_priv = dev->dev_private;
13487 struct drm_crtc *c;
13488 struct drm_i915_gem_object *obj;
13489
13490 mutex_lock(&dev->struct_mutex);
13491 intel_init_gt_powersave(dev);
13492 mutex_unlock(&dev->struct_mutex);
13493
13494 /*
13495 * There may be no VBT; and if the BIOS enabled SSC we can
13496 * just keep using it to avoid unnecessary flicker. Whereas if the
13497 * BIOS isn't using it, don't assume it will work even if the VBT
13498 * indicates as much.
13499 */
13500 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13501 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
13502 DREF_SSC1_ENABLE);
13503
13504 intel_modeset_init_hw(dev);
13505
13506 intel_setup_overlay(dev);
13507
13508 /*
13509 * Make sure any fbs we allocated at startup are properly
13510 * pinned & fenced. When we do the allocation it's too early
13511 * for this.
13512 */
13513 mutex_lock(&dev->struct_mutex);
13514 for_each_crtc(dev, c) {
13515 obj = intel_fb_obj(c->primary->fb);
13516 if (obj == NULL)
13517 continue;
13518
13519 if (intel_pin_and_fence_fb_obj(c->primary,
13520 c->primary->fb,
13521 NULL)) {
13522 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13523 to_intel_crtc(c)->pipe);
13524 drm_framebuffer_unreference(c->primary->fb);
13525 c->primary->fb = NULL;
13526 }
13527 }
13528 mutex_unlock(&dev->struct_mutex);
13529
13530 intel_backlight_register(dev);
13531 }
13532
13533 void intel_connector_unregister(struct intel_connector *intel_connector)
13534 {
13535 struct drm_connector *connector = &intel_connector->base;
13536
13537 intel_panel_destroy_backlight(connector);
13538 drm_connector_unregister(connector);
13539 }
13540
13541 void intel_modeset_cleanup(struct drm_device *dev)
13542 {
13543 struct drm_i915_private *dev_priv = dev->dev_private;
13544 struct drm_connector *connector;
13545
13546 intel_disable_gt_powersave(dev);
13547
13548 intel_backlight_unregister(dev);
13549
13550 /*
13551 * Interrupts and polling as the first thing to avoid creating havoc.
13552 * Too much stuff here (turning of connectors, ...) would
13553 * experience fancy races otherwise.
13554 */
13555 intel_irq_uninstall(dev_priv);
13556
13557 /*
13558 * Due to the hpd irq storm handling the hotplug work can re-arm the
13559 * poll handlers. Hence disable polling after hpd handling is shut down.
13560 */
13561 drm_kms_helper_poll_fini(dev);
13562
13563 mutex_lock(&dev->struct_mutex);
13564
13565 intel_unregister_dsm_handler();
13566
13567 intel_disable_fbc(dev);
13568
13569 ironlake_teardown_rc6(dev);
13570
13571 mutex_unlock(&dev->struct_mutex);
13572
13573 /* flush any delayed tasks or pending work */
13574 flush_scheduled_work();
13575
13576 /* destroy the backlight and sysfs files before encoders/connectors */
13577 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13578 struct intel_connector *intel_connector;
13579
13580 intel_connector = to_intel_connector(connector);
13581 intel_connector->unregister(intel_connector);
13582 }
13583
13584 drm_mode_config_cleanup(dev);
13585
13586 intel_cleanup_overlay(dev);
13587
13588 mutex_lock(&dev->struct_mutex);
13589 intel_cleanup_gt_powersave(dev);
13590 mutex_unlock(&dev->struct_mutex);
13591 }
13592
13593 /*
13594 * Return which encoder is currently attached for connector.
13595 */
13596 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13597 {
13598 return &intel_attached_encoder(connector)->base;
13599 }
13600
13601 void intel_connector_attach_encoder(struct intel_connector *connector,
13602 struct intel_encoder *encoder)
13603 {
13604 connector->encoder = encoder;
13605 drm_mode_connector_attach_encoder(&connector->base,
13606 &encoder->base);
13607 }
13608
13609 /*
13610 * set vga decode state - true == enable VGA decode
13611 */
13612 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13613 {
13614 struct drm_i915_private *dev_priv = dev->dev_private;
13615 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13616 u16 gmch_ctrl;
13617
13618 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13619 DRM_ERROR("failed to read control word\n");
13620 return -EIO;
13621 }
13622
13623 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13624 return 0;
13625
13626 if (state)
13627 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13628 else
13629 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13630
13631 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13632 DRM_ERROR("failed to write control word\n");
13633 return -EIO;
13634 }
13635
13636 return 0;
13637 }
13638
13639 struct intel_display_error_state {
13640
13641 u32 power_well_driver;
13642
13643 int num_transcoders;
13644
13645 struct intel_cursor_error_state {
13646 u32 control;
13647 u32 position;
13648 u32 base;
13649 u32 size;
13650 } cursor[I915_MAX_PIPES];
13651
13652 struct intel_pipe_error_state {
13653 bool power_domain_on;
13654 u32 source;
13655 u32 stat;
13656 } pipe[I915_MAX_PIPES];
13657
13658 struct intel_plane_error_state {
13659 u32 control;
13660 u32 stride;
13661 u32 size;
13662 u32 pos;
13663 u32 addr;
13664 u32 surface;
13665 u32 tile_offset;
13666 } plane[I915_MAX_PIPES];
13667
13668 struct intel_transcoder_error_state {
13669 bool power_domain_on;
13670 enum transcoder cpu_transcoder;
13671
13672 u32 conf;
13673
13674 u32 htotal;
13675 u32 hblank;
13676 u32 hsync;
13677 u32 vtotal;
13678 u32 vblank;
13679 u32 vsync;
13680 } transcoder[4];
13681 };
13682
13683 struct intel_display_error_state *
13684 intel_display_capture_error_state(struct drm_device *dev)
13685 {
13686 struct drm_i915_private *dev_priv = dev->dev_private;
13687 struct intel_display_error_state *error;
13688 int transcoders[] = {
13689 TRANSCODER_A,
13690 TRANSCODER_B,
13691 TRANSCODER_C,
13692 TRANSCODER_EDP,
13693 };
13694 int i;
13695
13696 if (INTEL_INFO(dev)->num_pipes == 0)
13697 return NULL;
13698
13699 error = kzalloc(sizeof(*error), GFP_ATOMIC);
13700 if (error == NULL)
13701 return NULL;
13702
13703 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13704 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13705
13706 for_each_pipe(dev_priv, i) {
13707 error->pipe[i].power_domain_on =
13708 __intel_display_power_is_enabled(dev_priv,
13709 POWER_DOMAIN_PIPE(i));
13710 if (!error->pipe[i].power_domain_on)
13711 continue;
13712
13713 error->cursor[i].control = I915_READ(CURCNTR(i));
13714 error->cursor[i].position = I915_READ(CURPOS(i));
13715 error->cursor[i].base = I915_READ(CURBASE(i));
13716
13717 error->plane[i].control = I915_READ(DSPCNTR(i));
13718 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13719 if (INTEL_INFO(dev)->gen <= 3) {
13720 error->plane[i].size = I915_READ(DSPSIZE(i));
13721 error->plane[i].pos = I915_READ(DSPPOS(i));
13722 }
13723 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13724 error->plane[i].addr = I915_READ(DSPADDR(i));
13725 if (INTEL_INFO(dev)->gen >= 4) {
13726 error->plane[i].surface = I915_READ(DSPSURF(i));
13727 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13728 }
13729
13730 error->pipe[i].source = I915_READ(PIPESRC(i));
13731
13732 if (HAS_GMCH_DISPLAY(dev))
13733 error->pipe[i].stat = I915_READ(PIPESTAT(i));
13734 }
13735
13736 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13737 if (HAS_DDI(dev_priv->dev))
13738 error->num_transcoders++; /* Account for eDP. */
13739
13740 for (i = 0; i < error->num_transcoders; i++) {
13741 enum transcoder cpu_transcoder = transcoders[i];
13742
13743 error->transcoder[i].power_domain_on =
13744 __intel_display_power_is_enabled(dev_priv,
13745 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13746 if (!error->transcoder[i].power_domain_on)
13747 continue;
13748
13749 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13750
13751 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13752 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13753 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13754 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13755 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13756 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13757 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13758 }
13759
13760 return error;
13761 }
13762
13763 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13764
13765 void
13766 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13767 struct drm_device *dev,
13768 struct intel_display_error_state *error)
13769 {
13770 struct drm_i915_private *dev_priv = dev->dev_private;
13771 int i;
13772
13773 if (!error)
13774 return;
13775
13776 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13777 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13778 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13779 error->power_well_driver);
13780 for_each_pipe(dev_priv, i) {
13781 err_printf(m, "Pipe [%d]:\n", i);
13782 err_printf(m, " Power: %s\n",
13783 error->pipe[i].power_domain_on ? "on" : "off");
13784 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
13785 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
13786
13787 err_printf(m, "Plane [%d]:\n", i);
13788 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
13789 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
13790 if (INTEL_INFO(dev)->gen <= 3) {
13791 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
13792 err_printf(m, " POS: %08x\n", error->plane[i].pos);
13793 }
13794 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13795 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
13796 if (INTEL_INFO(dev)->gen >= 4) {
13797 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
13798 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
13799 }
13800
13801 err_printf(m, "Cursor [%d]:\n", i);
13802 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
13803 err_printf(m, " POS: %08x\n", error->cursor[i].position);
13804 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
13805 }
13806
13807 for (i = 0; i < error->num_transcoders; i++) {
13808 err_printf(m, "CPU transcoder: %c\n",
13809 transcoder_name(error->transcoder[i].cpu_transcoder));
13810 err_printf(m, " Power: %s\n",
13811 error->transcoder[i].power_domain_on ? "on" : "off");
13812 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
13813 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
13814 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
13815 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
13816 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
13817 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
13818 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
13819 }
13820 }
13821
13822 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
13823 {
13824 struct intel_crtc *crtc;
13825
13826 for_each_intel_crtc(dev, crtc) {
13827 struct intel_unpin_work *work;
13828
13829 spin_lock_irq(&dev->event_lock);
13830
13831 work = crtc->unpin_work;
13832
13833 if (work && work->event &&
13834 work->event->base.file_priv == file) {
13835 kfree(work->event);
13836 work->event = NULL;
13837 }
13838
13839 spin_unlock_irq(&dev->event_lock);
13840 }
13841 }
Linux kernel - Deliverables
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