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drm/i915: Remove usage of encoder->new_crtc from clock computations
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
47
48 /* Primary plane formats supported by all gen */
49 #define COMMON_PRIMARY_FORMATS \
50 DRM_FORMAT_C8, \
51 DRM_FORMAT_RGB565, \
52 DRM_FORMAT_XRGB8888, \
53 DRM_FORMAT_ARGB8888
54
55 /* Primary plane formats for gen <= 3 */
56 static const uint32_t intel_primary_formats_gen2[] = {
57 COMMON_PRIMARY_FORMATS,
58 DRM_FORMAT_XRGB1555,
59 DRM_FORMAT_ARGB1555,
60 };
61
62 /* Primary plane formats for gen >= 4 */
63 static const uint32_t intel_primary_formats_gen4[] = {
64 COMMON_PRIMARY_FORMATS, \
65 DRM_FORMAT_XBGR8888,
66 DRM_FORMAT_ABGR8888,
67 DRM_FORMAT_XRGB2101010,
68 DRM_FORMAT_ARGB2101010,
69 DRM_FORMAT_XBGR2101010,
70 DRM_FORMAT_ABGR2101010,
71 };
72
73 /* Cursor formats */
74 static const uint32_t intel_cursor_formats[] = {
75 DRM_FORMAT_ARGB8888,
76 };
77
78 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79
80 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
81 struct intel_crtc_state *pipe_config);
82 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
83 struct intel_crtc_state *pipe_config);
84
85 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
86 int x, int y, struct drm_framebuffer *old_fb,
87 struct drm_atomic_state *state);
88 static int intel_framebuffer_init(struct drm_device *dev,
89 struct intel_framebuffer *ifb,
90 struct drm_mode_fb_cmd2 *mode_cmd,
91 struct drm_i915_gem_object *obj);
92 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
93 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
94 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
95 struct intel_link_m_n *m_n,
96 struct intel_link_m_n *m2_n2);
97 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
98 static void haswell_set_pipeconf(struct drm_crtc *crtc);
99 static void intel_set_pipe_csc(struct drm_crtc *crtc);
100 static void vlv_prepare_pll(struct intel_crtc *crtc,
101 const struct intel_crtc_state *pipe_config);
102 static void chv_prepare_pll(struct intel_crtc *crtc,
103 const struct intel_crtc_state *pipe_config);
104 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
105 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
106
107 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
108 {
109 if (!connector->mst_port)
110 return connector->encoder;
111 else
112 return &connector->mst_port->mst_encoders[pipe]->base;
113 }
114
115 typedef struct {
116 int min, max;
117 } intel_range_t;
118
119 typedef struct {
120 int dot_limit;
121 int p2_slow, p2_fast;
122 } intel_p2_t;
123
124 typedef struct intel_limit intel_limit_t;
125 struct intel_limit {
126 intel_range_t dot, vco, n, m, m1, m2, p, p1;
127 intel_p2_t p2;
128 };
129
130 int
131 intel_pch_rawclk(struct drm_device *dev)
132 {
133 struct drm_i915_private *dev_priv = dev->dev_private;
134
135 WARN_ON(!HAS_PCH_SPLIT(dev));
136
137 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
138 }
139
140 static inline u32 /* units of 100MHz */
141 intel_fdi_link_freq(struct drm_device *dev)
142 {
143 if (IS_GEN5(dev)) {
144 struct drm_i915_private *dev_priv = dev->dev_private;
145 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
146 } else
147 return 27;
148 }
149
150 static const intel_limit_t intel_limits_i8xx_dac = {
151 .dot = { .min = 25000, .max = 350000 },
152 .vco = { .min = 908000, .max = 1512000 },
153 .n = { .min = 2, .max = 16 },
154 .m = { .min = 96, .max = 140 },
155 .m1 = { .min = 18, .max = 26 },
156 .m2 = { .min = 6, .max = 16 },
157 .p = { .min = 4, .max = 128 },
158 .p1 = { .min = 2, .max = 33 },
159 .p2 = { .dot_limit = 165000,
160 .p2_slow = 4, .p2_fast = 2 },
161 };
162
163 static const intel_limit_t intel_limits_i8xx_dvo = {
164 .dot = { .min = 25000, .max = 350000 },
165 .vco = { .min = 908000, .max = 1512000 },
166 .n = { .min = 2, .max = 16 },
167 .m = { .min = 96, .max = 140 },
168 .m1 = { .min = 18, .max = 26 },
169 .m2 = { .min = 6, .max = 16 },
170 .p = { .min = 4, .max = 128 },
171 .p1 = { .min = 2, .max = 33 },
172 .p2 = { .dot_limit = 165000,
173 .p2_slow = 4, .p2_fast = 4 },
174 };
175
176 static const intel_limit_t intel_limits_i8xx_lvds = {
177 .dot = { .min = 25000, .max = 350000 },
178 .vco = { .min = 908000, .max = 1512000 },
179 .n = { .min = 2, .max = 16 },
180 .m = { .min = 96, .max = 140 },
181 .m1 = { .min = 18, .max = 26 },
182 .m2 = { .min = 6, .max = 16 },
183 .p = { .min = 4, .max = 128 },
184 .p1 = { .min = 1, .max = 6 },
185 .p2 = { .dot_limit = 165000,
186 .p2_slow = 14, .p2_fast = 7 },
187 };
188
189 static const intel_limit_t intel_limits_i9xx_sdvo = {
190 .dot = { .min = 20000, .max = 400000 },
191 .vco = { .min = 1400000, .max = 2800000 },
192 .n = { .min = 1, .max = 6 },
193 .m = { .min = 70, .max = 120 },
194 .m1 = { .min = 8, .max = 18 },
195 .m2 = { .min = 3, .max = 7 },
196 .p = { .min = 5, .max = 80 },
197 .p1 = { .min = 1, .max = 8 },
198 .p2 = { .dot_limit = 200000,
199 .p2_slow = 10, .p2_fast = 5 },
200 };
201
202 static const intel_limit_t intel_limits_i9xx_lvds = {
203 .dot = { .min = 20000, .max = 400000 },
204 .vco = { .min = 1400000, .max = 2800000 },
205 .n = { .min = 1, .max = 6 },
206 .m = { .min = 70, .max = 120 },
207 .m1 = { .min = 8, .max = 18 },
208 .m2 = { .min = 3, .max = 7 },
209 .p = { .min = 7, .max = 98 },
210 .p1 = { .min = 1, .max = 8 },
211 .p2 = { .dot_limit = 112000,
212 .p2_slow = 14, .p2_fast = 7 },
213 };
214
215
216 static const intel_limit_t intel_limits_g4x_sdvo = {
217 .dot = { .min = 25000, .max = 270000 },
218 .vco = { .min = 1750000, .max = 3500000},
219 .n = { .min = 1, .max = 4 },
220 .m = { .min = 104, .max = 138 },
221 .m1 = { .min = 17, .max = 23 },
222 .m2 = { .min = 5, .max = 11 },
223 .p = { .min = 10, .max = 30 },
224 .p1 = { .min = 1, .max = 3},
225 .p2 = { .dot_limit = 270000,
226 .p2_slow = 10,
227 .p2_fast = 10
228 },
229 };
230
231 static const intel_limit_t intel_limits_g4x_hdmi = {
232 .dot = { .min = 22000, .max = 400000 },
233 .vco = { .min = 1750000, .max = 3500000},
234 .n = { .min = 1, .max = 4 },
235 .m = { .min = 104, .max = 138 },
236 .m1 = { .min = 16, .max = 23 },
237 .m2 = { .min = 5, .max = 11 },
238 .p = { .min = 5, .max = 80 },
239 .p1 = { .min = 1, .max = 8},
240 .p2 = { .dot_limit = 165000,
241 .p2_slow = 10, .p2_fast = 5 },
242 };
243
244 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
245 .dot = { .min = 20000, .max = 115000 },
246 .vco = { .min = 1750000, .max = 3500000 },
247 .n = { .min = 1, .max = 3 },
248 .m = { .min = 104, .max = 138 },
249 .m1 = { .min = 17, .max = 23 },
250 .m2 = { .min = 5, .max = 11 },
251 .p = { .min = 28, .max = 112 },
252 .p1 = { .min = 2, .max = 8 },
253 .p2 = { .dot_limit = 0,
254 .p2_slow = 14, .p2_fast = 14
255 },
256 };
257
258 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
259 .dot = { .min = 80000, .max = 224000 },
260 .vco = { .min = 1750000, .max = 3500000 },
261 .n = { .min = 1, .max = 3 },
262 .m = { .min = 104, .max = 138 },
263 .m1 = { .min = 17, .max = 23 },
264 .m2 = { .min = 5, .max = 11 },
265 .p = { .min = 14, .max = 42 },
266 .p1 = { .min = 2, .max = 6 },
267 .p2 = { .dot_limit = 0,
268 .p2_slow = 7, .p2_fast = 7
269 },
270 };
271
272 static const intel_limit_t intel_limits_pineview_sdvo = {
273 .dot = { .min = 20000, .max = 400000},
274 .vco = { .min = 1700000, .max = 3500000 },
275 /* Pineview's Ncounter is a ring counter */
276 .n = { .min = 3, .max = 6 },
277 .m = { .min = 2, .max = 256 },
278 /* Pineview only has one combined m divider, which we treat as m2. */
279 .m1 = { .min = 0, .max = 0 },
280 .m2 = { .min = 0, .max = 254 },
281 .p = { .min = 5, .max = 80 },
282 .p1 = { .min = 1, .max = 8 },
283 .p2 = { .dot_limit = 200000,
284 .p2_slow = 10, .p2_fast = 5 },
285 };
286
287 static const intel_limit_t intel_limits_pineview_lvds = {
288 .dot = { .min = 20000, .max = 400000 },
289 .vco = { .min = 1700000, .max = 3500000 },
290 .n = { .min = 3, .max = 6 },
291 .m = { .min = 2, .max = 256 },
292 .m1 = { .min = 0, .max = 0 },
293 .m2 = { .min = 0, .max = 254 },
294 .p = { .min = 7, .max = 112 },
295 .p1 = { .min = 1, .max = 8 },
296 .p2 = { .dot_limit = 112000,
297 .p2_slow = 14, .p2_fast = 14 },
298 };
299
300 /* Ironlake / Sandybridge
301 *
302 * We calculate clock using (register_value + 2) for N/M1/M2, so here
303 * the range value for them is (actual_value - 2).
304 */
305 static const intel_limit_t intel_limits_ironlake_dac = {
306 .dot = { .min = 25000, .max = 350000 },
307 .vco = { .min = 1760000, .max = 3510000 },
308 .n = { .min = 1, .max = 5 },
309 .m = { .min = 79, .max = 127 },
310 .m1 = { .min = 12, .max = 22 },
311 .m2 = { .min = 5, .max = 9 },
312 .p = { .min = 5, .max = 80 },
313 .p1 = { .min = 1, .max = 8 },
314 .p2 = { .dot_limit = 225000,
315 .p2_slow = 10, .p2_fast = 5 },
316 };
317
318 static const intel_limit_t intel_limits_ironlake_single_lvds = {
319 .dot = { .min = 25000, .max = 350000 },
320 .vco = { .min = 1760000, .max = 3510000 },
321 .n = { .min = 1, .max = 3 },
322 .m = { .min = 79, .max = 118 },
323 .m1 = { .min = 12, .max = 22 },
324 .m2 = { .min = 5, .max = 9 },
325 .p = { .min = 28, .max = 112 },
326 .p1 = { .min = 2, .max = 8 },
327 .p2 = { .dot_limit = 225000,
328 .p2_slow = 14, .p2_fast = 14 },
329 };
330
331 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
332 .dot = { .min = 25000, .max = 350000 },
333 .vco = { .min = 1760000, .max = 3510000 },
334 .n = { .min = 1, .max = 3 },
335 .m = { .min = 79, .max = 127 },
336 .m1 = { .min = 12, .max = 22 },
337 .m2 = { .min = 5, .max = 9 },
338 .p = { .min = 14, .max = 56 },
339 .p1 = { .min = 2, .max = 8 },
340 .p2 = { .dot_limit = 225000,
341 .p2_slow = 7, .p2_fast = 7 },
342 };
343
344 /* LVDS 100mhz refclk limits. */
345 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
346 .dot = { .min = 25000, .max = 350000 },
347 .vco = { .min = 1760000, .max = 3510000 },
348 .n = { .min = 1, .max = 2 },
349 .m = { .min = 79, .max = 126 },
350 .m1 = { .min = 12, .max = 22 },
351 .m2 = { .min = 5, .max = 9 },
352 .p = { .min = 28, .max = 112 },
353 .p1 = { .min = 2, .max = 8 },
354 .p2 = { .dot_limit = 225000,
355 .p2_slow = 14, .p2_fast = 14 },
356 };
357
358 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
359 .dot = { .min = 25000, .max = 350000 },
360 .vco = { .min = 1760000, .max = 3510000 },
361 .n = { .min = 1, .max = 3 },
362 .m = { .min = 79, .max = 126 },
363 .m1 = { .min = 12, .max = 22 },
364 .m2 = { .min = 5, .max = 9 },
365 .p = { .min = 14, .max = 42 },
366 .p1 = { .min = 2, .max = 6 },
367 .p2 = { .dot_limit = 225000,
368 .p2_slow = 7, .p2_fast = 7 },
369 };
370
371 static const intel_limit_t intel_limits_vlv = {
372 /*
373 * These are the data rate limits (measured in fast clocks)
374 * since those are the strictest limits we have. The fast
375 * clock and actual rate limits are more relaxed, so checking
376 * them would make no difference.
377 */
378 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
379 .vco = { .min = 4000000, .max = 6000000 },
380 .n = { .min = 1, .max = 7 },
381 .m1 = { .min = 2, .max = 3 },
382 .m2 = { .min = 11, .max = 156 },
383 .p1 = { .min = 2, .max = 3 },
384 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
385 };
386
387 static const intel_limit_t intel_limits_chv = {
388 /*
389 * These are the data rate limits (measured in fast clocks)
390 * since those are the strictest limits we have. The fast
391 * clock and actual rate limits are more relaxed, so checking
392 * them would make no difference.
393 */
394 .dot = { .min = 25000 * 5, .max = 540000 * 5},
395 .vco = { .min = 4800000, .max = 6480000 },
396 .n = { .min = 1, .max = 1 },
397 .m1 = { .min = 2, .max = 2 },
398 .m2 = { .min = 24 << 22, .max = 175 << 22 },
399 .p1 = { .min = 2, .max = 4 },
400 .p2 = { .p2_slow = 1, .p2_fast = 14 },
401 };
402
403 static void vlv_clock(int refclk, intel_clock_t *clock)
404 {
405 clock->m = clock->m1 * clock->m2;
406 clock->p = clock->p1 * clock->p2;
407 if (WARN_ON(clock->n == 0 || clock->p == 0))
408 return;
409 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
410 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
411 }
412
413 /**
414 * Returns whether any output on the specified pipe is of the specified type
415 */
416 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
417 {
418 struct drm_device *dev = crtc->base.dev;
419 struct intel_encoder *encoder;
420
421 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
422 if (encoder->type == type)
423 return true;
424
425 return false;
426 }
427
428 /**
429 * Returns whether any output on the specified pipe will have the specified
430 * type after a staged modeset is complete, i.e., the same as
431 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
432 * encoder->crtc.
433 */
434 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
435 int type)
436 {
437 struct drm_atomic_state *state = crtc_state->base.state;
438 struct drm_connector_state *connector_state;
439 struct intel_encoder *encoder;
440 int i, num_connectors = 0;
441
442 for (i = 0; i < state->num_connector; i++) {
443 if (!state->connectors[i])
444 continue;
445
446 connector_state = state->connector_states[i];
447 if (connector_state->crtc != crtc_state->base.crtc)
448 continue;
449
450 num_connectors++;
451
452 encoder = to_intel_encoder(connector_state->best_encoder);
453 if (encoder->type == type)
454 return true;
455 }
456
457 WARN_ON(num_connectors == 0);
458
459 return false;
460 }
461
462 static const intel_limit_t *
463 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
464 {
465 struct drm_device *dev = crtc_state->base.crtc->dev;
466 const intel_limit_t *limit;
467
468 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
469 if (intel_is_dual_link_lvds(dev)) {
470 if (refclk == 100000)
471 limit = &intel_limits_ironlake_dual_lvds_100m;
472 else
473 limit = &intel_limits_ironlake_dual_lvds;
474 } else {
475 if (refclk == 100000)
476 limit = &intel_limits_ironlake_single_lvds_100m;
477 else
478 limit = &intel_limits_ironlake_single_lvds;
479 }
480 } else
481 limit = &intel_limits_ironlake_dac;
482
483 return limit;
484 }
485
486 static const intel_limit_t *
487 intel_g4x_limit(struct intel_crtc_state *crtc_state)
488 {
489 struct drm_device *dev = crtc_state->base.crtc->dev;
490 const intel_limit_t *limit;
491
492 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
493 if (intel_is_dual_link_lvds(dev))
494 limit = &intel_limits_g4x_dual_channel_lvds;
495 else
496 limit = &intel_limits_g4x_single_channel_lvds;
497 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
498 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
499 limit = &intel_limits_g4x_hdmi;
500 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
501 limit = &intel_limits_g4x_sdvo;
502 } else /* The option is for other outputs */
503 limit = &intel_limits_i9xx_sdvo;
504
505 return limit;
506 }
507
508 static const intel_limit_t *
509 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
510 {
511 struct drm_device *dev = crtc_state->base.crtc->dev;
512 const intel_limit_t *limit;
513
514 if (HAS_PCH_SPLIT(dev))
515 limit = intel_ironlake_limit(crtc_state, refclk);
516 else if (IS_G4X(dev)) {
517 limit = intel_g4x_limit(crtc_state);
518 } else if (IS_PINEVIEW(dev)) {
519 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
520 limit = &intel_limits_pineview_lvds;
521 else
522 limit = &intel_limits_pineview_sdvo;
523 } else if (IS_CHERRYVIEW(dev)) {
524 limit = &intel_limits_chv;
525 } else if (IS_VALLEYVIEW(dev)) {
526 limit = &intel_limits_vlv;
527 } else if (!IS_GEN2(dev)) {
528 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
529 limit = &intel_limits_i9xx_lvds;
530 else
531 limit = &intel_limits_i9xx_sdvo;
532 } else {
533 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
534 limit = &intel_limits_i8xx_lvds;
535 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
536 limit = &intel_limits_i8xx_dvo;
537 else
538 limit = &intel_limits_i8xx_dac;
539 }
540 return limit;
541 }
542
543 /* m1 is reserved as 0 in Pineview, n is a ring counter */
544 static void pineview_clock(int refclk, intel_clock_t *clock)
545 {
546 clock->m = clock->m2 + 2;
547 clock->p = clock->p1 * clock->p2;
548 if (WARN_ON(clock->n == 0 || clock->p == 0))
549 return;
550 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
551 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
552 }
553
554 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
555 {
556 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
557 }
558
559 static void i9xx_clock(int refclk, intel_clock_t *clock)
560 {
561 clock->m = i9xx_dpll_compute_m(clock);
562 clock->p = clock->p1 * clock->p2;
563 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
564 return;
565 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
566 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
567 }
568
569 static void chv_clock(int refclk, intel_clock_t *clock)
570 {
571 clock->m = clock->m1 * clock->m2;
572 clock->p = clock->p1 * clock->p2;
573 if (WARN_ON(clock->n == 0 || clock->p == 0))
574 return;
575 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
576 clock->n << 22);
577 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
578 }
579
580 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
581 /**
582 * Returns whether the given set of divisors are valid for a given refclk with
583 * the given connectors.
584 */
585
586 static bool intel_PLL_is_valid(struct drm_device *dev,
587 const intel_limit_t *limit,
588 const intel_clock_t *clock)
589 {
590 if (clock->n < limit->n.min || limit->n.max < clock->n)
591 INTELPllInvalid("n out of range\n");
592 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
593 INTELPllInvalid("p1 out of range\n");
594 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
595 INTELPllInvalid("m2 out of range\n");
596 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
597 INTELPllInvalid("m1 out of range\n");
598
599 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
600 if (clock->m1 <= clock->m2)
601 INTELPllInvalid("m1 <= m2\n");
602
603 if (!IS_VALLEYVIEW(dev)) {
604 if (clock->p < limit->p.min || limit->p.max < clock->p)
605 INTELPllInvalid("p out of range\n");
606 if (clock->m < limit->m.min || limit->m.max < clock->m)
607 INTELPllInvalid("m out of range\n");
608 }
609
610 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
611 INTELPllInvalid("vco out of range\n");
612 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
613 * connector, etc., rather than just a single range.
614 */
615 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
616 INTELPllInvalid("dot out of range\n");
617
618 return true;
619 }
620
621 static bool
622 i9xx_find_best_dpll(const intel_limit_t *limit,
623 struct intel_crtc_state *crtc_state,
624 int target, int refclk, intel_clock_t *match_clock,
625 intel_clock_t *best_clock)
626 {
627 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
628 struct drm_device *dev = crtc->base.dev;
629 intel_clock_t clock;
630 int err = target;
631
632 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
633 /*
634 * For LVDS just rely on its current settings for dual-channel.
635 * We haven't figured out how to reliably set up different
636 * single/dual channel state, if we even can.
637 */
638 if (intel_is_dual_link_lvds(dev))
639 clock.p2 = limit->p2.p2_fast;
640 else
641 clock.p2 = limit->p2.p2_slow;
642 } else {
643 if (target < limit->p2.dot_limit)
644 clock.p2 = limit->p2.p2_slow;
645 else
646 clock.p2 = limit->p2.p2_fast;
647 }
648
649 memset(best_clock, 0, sizeof(*best_clock));
650
651 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
652 clock.m1++) {
653 for (clock.m2 = limit->m2.min;
654 clock.m2 <= limit->m2.max; clock.m2++) {
655 if (clock.m2 >= clock.m1)
656 break;
657 for (clock.n = limit->n.min;
658 clock.n <= limit->n.max; clock.n++) {
659 for (clock.p1 = limit->p1.min;
660 clock.p1 <= limit->p1.max; clock.p1++) {
661 int this_err;
662
663 i9xx_clock(refclk, &clock);
664 if (!intel_PLL_is_valid(dev, limit,
665 &clock))
666 continue;
667 if (match_clock &&
668 clock.p != match_clock->p)
669 continue;
670
671 this_err = abs(clock.dot - target);
672 if (this_err < err) {
673 *best_clock = clock;
674 err = this_err;
675 }
676 }
677 }
678 }
679 }
680
681 return (err != target);
682 }
683
684 static bool
685 pnv_find_best_dpll(const intel_limit_t *limit,
686 struct intel_crtc_state *crtc_state,
687 int target, int refclk, intel_clock_t *match_clock,
688 intel_clock_t *best_clock)
689 {
690 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
691 struct drm_device *dev = crtc->base.dev;
692 intel_clock_t clock;
693 int err = target;
694
695 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
696 /*
697 * For LVDS just rely on its current settings for dual-channel.
698 * We haven't figured out how to reliably set up different
699 * single/dual channel state, if we even can.
700 */
701 if (intel_is_dual_link_lvds(dev))
702 clock.p2 = limit->p2.p2_fast;
703 else
704 clock.p2 = limit->p2.p2_slow;
705 } else {
706 if (target < limit->p2.dot_limit)
707 clock.p2 = limit->p2.p2_slow;
708 else
709 clock.p2 = limit->p2.p2_fast;
710 }
711
712 memset(best_clock, 0, sizeof(*best_clock));
713
714 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
715 clock.m1++) {
716 for (clock.m2 = limit->m2.min;
717 clock.m2 <= limit->m2.max; clock.m2++) {
718 for (clock.n = limit->n.min;
719 clock.n <= limit->n.max; clock.n++) {
720 for (clock.p1 = limit->p1.min;
721 clock.p1 <= limit->p1.max; clock.p1++) {
722 int this_err;
723
724 pineview_clock(refclk, &clock);
725 if (!intel_PLL_is_valid(dev, limit,
726 &clock))
727 continue;
728 if (match_clock &&
729 clock.p != match_clock->p)
730 continue;
731
732 this_err = abs(clock.dot - target);
733 if (this_err < err) {
734 *best_clock = clock;
735 err = this_err;
736 }
737 }
738 }
739 }
740 }
741
742 return (err != target);
743 }
744
745 static bool
746 g4x_find_best_dpll(const intel_limit_t *limit,
747 struct intel_crtc_state *crtc_state,
748 int target, int refclk, intel_clock_t *match_clock,
749 intel_clock_t *best_clock)
750 {
751 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
752 struct drm_device *dev = crtc->base.dev;
753 intel_clock_t clock;
754 int max_n;
755 bool found;
756 /* approximately equals target * 0.00585 */
757 int err_most = (target >> 8) + (target >> 9);
758 found = false;
759
760 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
761 if (intel_is_dual_link_lvds(dev))
762 clock.p2 = limit->p2.p2_fast;
763 else
764 clock.p2 = limit->p2.p2_slow;
765 } else {
766 if (target < limit->p2.dot_limit)
767 clock.p2 = limit->p2.p2_slow;
768 else
769 clock.p2 = limit->p2.p2_fast;
770 }
771
772 memset(best_clock, 0, sizeof(*best_clock));
773 max_n = limit->n.max;
774 /* based on hardware requirement, prefer smaller n to precision */
775 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
776 /* based on hardware requirement, prefere larger m1,m2 */
777 for (clock.m1 = limit->m1.max;
778 clock.m1 >= limit->m1.min; clock.m1--) {
779 for (clock.m2 = limit->m2.max;
780 clock.m2 >= limit->m2.min; clock.m2--) {
781 for (clock.p1 = limit->p1.max;
782 clock.p1 >= limit->p1.min; clock.p1--) {
783 int this_err;
784
785 i9xx_clock(refclk, &clock);
786 if (!intel_PLL_is_valid(dev, limit,
787 &clock))
788 continue;
789
790 this_err = abs(clock.dot - target);
791 if (this_err < err_most) {
792 *best_clock = clock;
793 err_most = this_err;
794 max_n = clock.n;
795 found = true;
796 }
797 }
798 }
799 }
800 }
801 return found;
802 }
803
804 /*
805 * Check if the calculated PLL configuration is more optimal compared to the
806 * best configuration and error found so far. Return the calculated error.
807 */
808 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
809 const intel_clock_t *calculated_clock,
810 const intel_clock_t *best_clock,
811 unsigned int best_error_ppm,
812 unsigned int *error_ppm)
813 {
814 /*
815 * For CHV ignore the error and consider only the P value.
816 * Prefer a bigger P value based on HW requirements.
817 */
818 if (IS_CHERRYVIEW(dev)) {
819 *error_ppm = 0;
820
821 return calculated_clock->p > best_clock->p;
822 }
823
824 if (WARN_ON_ONCE(!target_freq))
825 return false;
826
827 *error_ppm = div_u64(1000000ULL *
828 abs(target_freq - calculated_clock->dot),
829 target_freq);
830 /*
831 * Prefer a better P value over a better (smaller) error if the error
832 * is small. Ensure this preference for future configurations too by
833 * setting the error to 0.
834 */
835 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
836 *error_ppm = 0;
837
838 return true;
839 }
840
841 return *error_ppm + 10 < best_error_ppm;
842 }
843
844 static bool
845 vlv_find_best_dpll(const intel_limit_t *limit,
846 struct intel_crtc_state *crtc_state,
847 int target, int refclk, intel_clock_t *match_clock,
848 intel_clock_t *best_clock)
849 {
850 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
851 struct drm_device *dev = crtc->base.dev;
852 intel_clock_t clock;
853 unsigned int bestppm = 1000000;
854 /* min update 19.2 MHz */
855 int max_n = min(limit->n.max, refclk / 19200);
856 bool found = false;
857
858 target *= 5; /* fast clock */
859
860 memset(best_clock, 0, sizeof(*best_clock));
861
862 /* based on hardware requirement, prefer smaller n to precision */
863 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
864 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
865 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
866 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
867 clock.p = clock.p1 * clock.p2;
868 /* based on hardware requirement, prefer bigger m1,m2 values */
869 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
870 unsigned int ppm;
871
872 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
873 refclk * clock.m1);
874
875 vlv_clock(refclk, &clock);
876
877 if (!intel_PLL_is_valid(dev, limit,
878 &clock))
879 continue;
880
881 if (!vlv_PLL_is_optimal(dev, target,
882 &clock,
883 best_clock,
884 bestppm, &ppm))
885 continue;
886
887 *best_clock = clock;
888 bestppm = ppm;
889 found = true;
890 }
891 }
892 }
893 }
894
895 return found;
896 }
897
898 static bool
899 chv_find_best_dpll(const intel_limit_t *limit,
900 struct intel_crtc_state *crtc_state,
901 int target, int refclk, intel_clock_t *match_clock,
902 intel_clock_t *best_clock)
903 {
904 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
905 struct drm_device *dev = crtc->base.dev;
906 unsigned int best_error_ppm;
907 intel_clock_t clock;
908 uint64_t m2;
909 int found = false;
910
911 memset(best_clock, 0, sizeof(*best_clock));
912 best_error_ppm = 1000000;
913
914 /*
915 * Based on hardware doc, the n always set to 1, and m1 always
916 * set to 2. If requires to support 200Mhz refclk, we need to
917 * revisit this because n may not 1 anymore.
918 */
919 clock.n = 1, clock.m1 = 2;
920 target *= 5; /* fast clock */
921
922 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
923 for (clock.p2 = limit->p2.p2_fast;
924 clock.p2 >= limit->p2.p2_slow;
925 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
926 unsigned int error_ppm;
927
928 clock.p = clock.p1 * clock.p2;
929
930 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
931 clock.n) << 22, refclk * clock.m1);
932
933 if (m2 > INT_MAX/clock.m1)
934 continue;
935
936 clock.m2 = m2;
937
938 chv_clock(refclk, &clock);
939
940 if (!intel_PLL_is_valid(dev, limit, &clock))
941 continue;
942
943 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
944 best_error_ppm, &error_ppm))
945 continue;
946
947 *best_clock = clock;
948 best_error_ppm = error_ppm;
949 found = true;
950 }
951 }
952
953 return found;
954 }
955
956 bool intel_crtc_active(struct drm_crtc *crtc)
957 {
958 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
959
960 /* Be paranoid as we can arrive here with only partial
961 * state retrieved from the hardware during setup.
962 *
963 * We can ditch the adjusted_mode.crtc_clock check as soon
964 * as Haswell has gained clock readout/fastboot support.
965 *
966 * We can ditch the crtc->primary->fb check as soon as we can
967 * properly reconstruct framebuffers.
968 *
969 * FIXME: The intel_crtc->active here should be switched to
970 * crtc->state->active once we have proper CRTC states wired up
971 * for atomic.
972 */
973 return intel_crtc->active && crtc->primary->state->fb &&
974 intel_crtc->config->base.adjusted_mode.crtc_clock;
975 }
976
977 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
978 enum pipe pipe)
979 {
980 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
981 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
982
983 return intel_crtc->config->cpu_transcoder;
984 }
985
986 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
987 {
988 struct drm_i915_private *dev_priv = dev->dev_private;
989 u32 reg = PIPEDSL(pipe);
990 u32 line1, line2;
991 u32 line_mask;
992
993 if (IS_GEN2(dev))
994 line_mask = DSL_LINEMASK_GEN2;
995 else
996 line_mask = DSL_LINEMASK_GEN3;
997
998 line1 = I915_READ(reg) & line_mask;
999 mdelay(5);
1000 line2 = I915_READ(reg) & line_mask;
1001
1002 return line1 == line2;
1003 }
1004
1005 /*
1006 * intel_wait_for_pipe_off - wait for pipe to turn off
1007 * @crtc: crtc whose pipe to wait for
1008 *
1009 * After disabling a pipe, we can't wait for vblank in the usual way,
1010 * spinning on the vblank interrupt status bit, since we won't actually
1011 * see an interrupt when the pipe is disabled.
1012 *
1013 * On Gen4 and above:
1014 * wait for the pipe register state bit to turn off
1015 *
1016 * Otherwise:
1017 * wait for the display line value to settle (it usually
1018 * ends up stopping at the start of the next frame).
1019 *
1020 */
1021 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1022 {
1023 struct drm_device *dev = crtc->base.dev;
1024 struct drm_i915_private *dev_priv = dev->dev_private;
1025 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1026 enum pipe pipe = crtc->pipe;
1027
1028 if (INTEL_INFO(dev)->gen >= 4) {
1029 int reg = PIPECONF(cpu_transcoder);
1030
1031 /* Wait for the Pipe State to go off */
1032 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1033 100))
1034 WARN(1, "pipe_off wait timed out\n");
1035 } else {
1036 /* Wait for the display line to settle */
1037 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1038 WARN(1, "pipe_off wait timed out\n");
1039 }
1040 }
1041
1042 /*
1043 * ibx_digital_port_connected - is the specified port connected?
1044 * @dev_priv: i915 private structure
1045 * @port: the port to test
1046 *
1047 * Returns true if @port is connected, false otherwise.
1048 */
1049 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1050 struct intel_digital_port *port)
1051 {
1052 u32 bit;
1053
1054 if (HAS_PCH_IBX(dev_priv->dev)) {
1055 switch (port->port) {
1056 case PORT_B:
1057 bit = SDE_PORTB_HOTPLUG;
1058 break;
1059 case PORT_C:
1060 bit = SDE_PORTC_HOTPLUG;
1061 break;
1062 case PORT_D:
1063 bit = SDE_PORTD_HOTPLUG;
1064 break;
1065 default:
1066 return true;
1067 }
1068 } else {
1069 switch (port->port) {
1070 case PORT_B:
1071 bit = SDE_PORTB_HOTPLUG_CPT;
1072 break;
1073 case PORT_C:
1074 bit = SDE_PORTC_HOTPLUG_CPT;
1075 break;
1076 case PORT_D:
1077 bit = SDE_PORTD_HOTPLUG_CPT;
1078 break;
1079 default:
1080 return true;
1081 }
1082 }
1083
1084 return I915_READ(SDEISR) & bit;
1085 }
1086
1087 static const char *state_string(bool enabled)
1088 {
1089 return enabled ? "on" : "off";
1090 }
1091
1092 /* Only for pre-ILK configs */
1093 void assert_pll(struct drm_i915_private *dev_priv,
1094 enum pipe pipe, bool state)
1095 {
1096 int reg;
1097 u32 val;
1098 bool cur_state;
1099
1100 reg = DPLL(pipe);
1101 val = I915_READ(reg);
1102 cur_state = !!(val & DPLL_VCO_ENABLE);
1103 I915_STATE_WARN(cur_state != state,
1104 "PLL state assertion failure (expected %s, current %s)\n",
1105 state_string(state), state_string(cur_state));
1106 }
1107
1108 /* XXX: the dsi pll is shared between MIPI DSI ports */
1109 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1110 {
1111 u32 val;
1112 bool cur_state;
1113
1114 mutex_lock(&dev_priv->dpio_lock);
1115 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1116 mutex_unlock(&dev_priv->dpio_lock);
1117
1118 cur_state = val & DSI_PLL_VCO_EN;
1119 I915_STATE_WARN(cur_state != state,
1120 "DSI PLL state assertion failure (expected %s, current %s)\n",
1121 state_string(state), state_string(cur_state));
1122 }
1123 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1124 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1125
1126 struct intel_shared_dpll *
1127 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1128 {
1129 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1130
1131 if (crtc->config->shared_dpll < 0)
1132 return NULL;
1133
1134 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1135 }
1136
1137 /* For ILK+ */
1138 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1139 struct intel_shared_dpll *pll,
1140 bool state)
1141 {
1142 bool cur_state;
1143 struct intel_dpll_hw_state hw_state;
1144
1145 if (WARN (!pll,
1146 "asserting DPLL %s with no DPLL\n", state_string(state)))
1147 return;
1148
1149 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1150 I915_STATE_WARN(cur_state != state,
1151 "%s assertion failure (expected %s, current %s)\n",
1152 pll->name, state_string(state), state_string(cur_state));
1153 }
1154
1155 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1156 enum pipe pipe, bool state)
1157 {
1158 int reg;
1159 u32 val;
1160 bool cur_state;
1161 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1162 pipe);
1163
1164 if (HAS_DDI(dev_priv->dev)) {
1165 /* DDI does not have a specific FDI_TX register */
1166 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1167 val = I915_READ(reg);
1168 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1169 } else {
1170 reg = FDI_TX_CTL(pipe);
1171 val = I915_READ(reg);
1172 cur_state = !!(val & FDI_TX_ENABLE);
1173 }
1174 I915_STATE_WARN(cur_state != state,
1175 "FDI TX state assertion failure (expected %s, current %s)\n",
1176 state_string(state), state_string(cur_state));
1177 }
1178 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1179 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1180
1181 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1182 enum pipe pipe, bool state)
1183 {
1184 int reg;
1185 u32 val;
1186 bool cur_state;
1187
1188 reg = FDI_RX_CTL(pipe);
1189 val = I915_READ(reg);
1190 cur_state = !!(val & FDI_RX_ENABLE);
1191 I915_STATE_WARN(cur_state != state,
1192 "FDI RX state assertion failure (expected %s, current %s)\n",
1193 state_string(state), state_string(cur_state));
1194 }
1195 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1196 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1197
1198 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1199 enum pipe pipe)
1200 {
1201 int reg;
1202 u32 val;
1203
1204 /* ILK FDI PLL is always enabled */
1205 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1206 return;
1207
1208 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1209 if (HAS_DDI(dev_priv->dev))
1210 return;
1211
1212 reg = FDI_TX_CTL(pipe);
1213 val = I915_READ(reg);
1214 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1215 }
1216
1217 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1218 enum pipe pipe, bool state)
1219 {
1220 int reg;
1221 u32 val;
1222 bool cur_state;
1223
1224 reg = FDI_RX_CTL(pipe);
1225 val = I915_READ(reg);
1226 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1227 I915_STATE_WARN(cur_state != state,
1228 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1229 state_string(state), state_string(cur_state));
1230 }
1231
1232 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1233 enum pipe pipe)
1234 {
1235 struct drm_device *dev = dev_priv->dev;
1236 int pp_reg;
1237 u32 val;
1238 enum pipe panel_pipe = PIPE_A;
1239 bool locked = true;
1240
1241 if (WARN_ON(HAS_DDI(dev)))
1242 return;
1243
1244 if (HAS_PCH_SPLIT(dev)) {
1245 u32 port_sel;
1246
1247 pp_reg = PCH_PP_CONTROL;
1248 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1249
1250 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1251 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1252 panel_pipe = PIPE_B;
1253 /* XXX: else fix for eDP */
1254 } else if (IS_VALLEYVIEW(dev)) {
1255 /* presumably write lock depends on pipe, not port select */
1256 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1257 panel_pipe = pipe;
1258 } else {
1259 pp_reg = PP_CONTROL;
1260 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1261 panel_pipe = PIPE_B;
1262 }
1263
1264 val = I915_READ(pp_reg);
1265 if (!(val & PANEL_POWER_ON) ||
1266 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1267 locked = false;
1268
1269 I915_STATE_WARN(panel_pipe == pipe && locked,
1270 "panel assertion failure, pipe %c regs locked\n",
1271 pipe_name(pipe));
1272 }
1273
1274 static void assert_cursor(struct drm_i915_private *dev_priv,
1275 enum pipe pipe, bool state)
1276 {
1277 struct drm_device *dev = dev_priv->dev;
1278 bool cur_state;
1279
1280 if (IS_845G(dev) || IS_I865G(dev))
1281 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1282 else
1283 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1284
1285 I915_STATE_WARN(cur_state != state,
1286 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1287 pipe_name(pipe), state_string(state), state_string(cur_state));
1288 }
1289 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1290 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1291
1292 void assert_pipe(struct drm_i915_private *dev_priv,
1293 enum pipe pipe, bool state)
1294 {
1295 int reg;
1296 u32 val;
1297 bool cur_state;
1298 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1299 pipe);
1300
1301 /* if we need the pipe quirk it must be always on */
1302 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1303 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1304 state = true;
1305
1306 if (!intel_display_power_is_enabled(dev_priv,
1307 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1308 cur_state = false;
1309 } else {
1310 reg = PIPECONF(cpu_transcoder);
1311 val = I915_READ(reg);
1312 cur_state = !!(val & PIPECONF_ENABLE);
1313 }
1314
1315 I915_STATE_WARN(cur_state != state,
1316 "pipe %c assertion failure (expected %s, current %s)\n",
1317 pipe_name(pipe), state_string(state), state_string(cur_state));
1318 }
1319
1320 static void assert_plane(struct drm_i915_private *dev_priv,
1321 enum plane plane, bool state)
1322 {
1323 int reg;
1324 u32 val;
1325 bool cur_state;
1326
1327 reg = DSPCNTR(plane);
1328 val = I915_READ(reg);
1329 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1330 I915_STATE_WARN(cur_state != state,
1331 "plane %c assertion failure (expected %s, current %s)\n",
1332 plane_name(plane), state_string(state), state_string(cur_state));
1333 }
1334
1335 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1336 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1337
1338 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1339 enum pipe pipe)
1340 {
1341 struct drm_device *dev = dev_priv->dev;
1342 int reg, i;
1343 u32 val;
1344 int cur_pipe;
1345
1346 /* Primary planes are fixed to pipes on gen4+ */
1347 if (INTEL_INFO(dev)->gen >= 4) {
1348 reg = DSPCNTR(pipe);
1349 val = I915_READ(reg);
1350 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1351 "plane %c assertion failure, should be disabled but not\n",
1352 plane_name(pipe));
1353 return;
1354 }
1355
1356 /* Need to check both planes against the pipe */
1357 for_each_pipe(dev_priv, i) {
1358 reg = DSPCNTR(i);
1359 val = I915_READ(reg);
1360 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1361 DISPPLANE_SEL_PIPE_SHIFT;
1362 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1363 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1364 plane_name(i), pipe_name(pipe));
1365 }
1366 }
1367
1368 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1369 enum pipe pipe)
1370 {
1371 struct drm_device *dev = dev_priv->dev;
1372 int reg, sprite;
1373 u32 val;
1374
1375 if (INTEL_INFO(dev)->gen >= 9) {
1376 for_each_sprite(dev_priv, pipe, sprite) {
1377 val = I915_READ(PLANE_CTL(pipe, sprite));
1378 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1379 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1380 sprite, pipe_name(pipe));
1381 }
1382 } else if (IS_VALLEYVIEW(dev)) {
1383 for_each_sprite(dev_priv, pipe, sprite) {
1384 reg = SPCNTR(pipe, sprite);
1385 val = I915_READ(reg);
1386 I915_STATE_WARN(val & SP_ENABLE,
1387 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1388 sprite_name(pipe, sprite), pipe_name(pipe));
1389 }
1390 } else if (INTEL_INFO(dev)->gen >= 7) {
1391 reg = SPRCTL(pipe);
1392 val = I915_READ(reg);
1393 I915_STATE_WARN(val & SPRITE_ENABLE,
1394 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1395 plane_name(pipe), pipe_name(pipe));
1396 } else if (INTEL_INFO(dev)->gen >= 5) {
1397 reg = DVSCNTR(pipe);
1398 val = I915_READ(reg);
1399 I915_STATE_WARN(val & DVS_ENABLE,
1400 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1401 plane_name(pipe), pipe_name(pipe));
1402 }
1403 }
1404
1405 static void assert_vblank_disabled(struct drm_crtc *crtc)
1406 {
1407 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1408 drm_crtc_vblank_put(crtc);
1409 }
1410
1411 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1412 {
1413 u32 val;
1414 bool enabled;
1415
1416 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1417
1418 val = I915_READ(PCH_DREF_CONTROL);
1419 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1420 DREF_SUPERSPREAD_SOURCE_MASK));
1421 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1422 }
1423
1424 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1425 enum pipe pipe)
1426 {
1427 int reg;
1428 u32 val;
1429 bool enabled;
1430
1431 reg = PCH_TRANSCONF(pipe);
1432 val = I915_READ(reg);
1433 enabled = !!(val & TRANS_ENABLE);
1434 I915_STATE_WARN(enabled,
1435 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1436 pipe_name(pipe));
1437 }
1438
1439 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1440 enum pipe pipe, u32 port_sel, u32 val)
1441 {
1442 if ((val & DP_PORT_EN) == 0)
1443 return false;
1444
1445 if (HAS_PCH_CPT(dev_priv->dev)) {
1446 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1447 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1448 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1449 return false;
1450 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1451 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1452 return false;
1453 } else {
1454 if ((val & DP_PIPE_MASK) != (pipe << 30))
1455 return false;
1456 }
1457 return true;
1458 }
1459
1460 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1461 enum pipe pipe, u32 val)
1462 {
1463 if ((val & SDVO_ENABLE) == 0)
1464 return false;
1465
1466 if (HAS_PCH_CPT(dev_priv->dev)) {
1467 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1468 return false;
1469 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1470 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1471 return false;
1472 } else {
1473 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1474 return false;
1475 }
1476 return true;
1477 }
1478
1479 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1480 enum pipe pipe, u32 val)
1481 {
1482 if ((val & LVDS_PORT_EN) == 0)
1483 return false;
1484
1485 if (HAS_PCH_CPT(dev_priv->dev)) {
1486 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1487 return false;
1488 } else {
1489 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1490 return false;
1491 }
1492 return true;
1493 }
1494
1495 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1496 enum pipe pipe, u32 val)
1497 {
1498 if ((val & ADPA_DAC_ENABLE) == 0)
1499 return false;
1500 if (HAS_PCH_CPT(dev_priv->dev)) {
1501 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1502 return false;
1503 } else {
1504 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1505 return false;
1506 }
1507 return true;
1508 }
1509
1510 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1511 enum pipe pipe, int reg, u32 port_sel)
1512 {
1513 u32 val = I915_READ(reg);
1514 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1515 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1516 reg, pipe_name(pipe));
1517
1518 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1519 && (val & DP_PIPEB_SELECT),
1520 "IBX PCH dp port still using transcoder B\n");
1521 }
1522
1523 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1524 enum pipe pipe, int reg)
1525 {
1526 u32 val = I915_READ(reg);
1527 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1528 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1529 reg, pipe_name(pipe));
1530
1531 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1532 && (val & SDVO_PIPE_B_SELECT),
1533 "IBX PCH hdmi port still using transcoder B\n");
1534 }
1535
1536 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1537 enum pipe pipe)
1538 {
1539 int reg;
1540 u32 val;
1541
1542 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1543 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1544 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1545
1546 reg = PCH_ADPA;
1547 val = I915_READ(reg);
1548 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1549 "PCH VGA enabled on transcoder %c, should be disabled\n",
1550 pipe_name(pipe));
1551
1552 reg = PCH_LVDS;
1553 val = I915_READ(reg);
1554 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1555 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1556 pipe_name(pipe));
1557
1558 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1559 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1560 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1561 }
1562
1563 static void intel_init_dpio(struct drm_device *dev)
1564 {
1565 struct drm_i915_private *dev_priv = dev->dev_private;
1566
1567 if (!IS_VALLEYVIEW(dev))
1568 return;
1569
1570 /*
1571 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1572 * CHV x1 PHY (DP/HDMI D)
1573 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1574 */
1575 if (IS_CHERRYVIEW(dev)) {
1576 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1577 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1578 } else {
1579 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1580 }
1581 }
1582
1583 static void vlv_enable_pll(struct intel_crtc *crtc,
1584 const struct intel_crtc_state *pipe_config)
1585 {
1586 struct drm_device *dev = crtc->base.dev;
1587 struct drm_i915_private *dev_priv = dev->dev_private;
1588 int reg = DPLL(crtc->pipe);
1589 u32 dpll = pipe_config->dpll_hw_state.dpll;
1590
1591 assert_pipe_disabled(dev_priv, crtc->pipe);
1592
1593 /* No really, not for ILK+ */
1594 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1595
1596 /* PLL is protected by panel, make sure we can write it */
1597 if (IS_MOBILE(dev_priv->dev))
1598 assert_panel_unlocked(dev_priv, crtc->pipe);
1599
1600 I915_WRITE(reg, dpll);
1601 POSTING_READ(reg);
1602 udelay(150);
1603
1604 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1605 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1606
1607 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1608 POSTING_READ(DPLL_MD(crtc->pipe));
1609
1610 /* We do this three times for luck */
1611 I915_WRITE(reg, dpll);
1612 POSTING_READ(reg);
1613 udelay(150); /* wait for warmup */
1614 I915_WRITE(reg, dpll);
1615 POSTING_READ(reg);
1616 udelay(150); /* wait for warmup */
1617 I915_WRITE(reg, dpll);
1618 POSTING_READ(reg);
1619 udelay(150); /* wait for warmup */
1620 }
1621
1622 static void chv_enable_pll(struct intel_crtc *crtc,
1623 const struct intel_crtc_state *pipe_config)
1624 {
1625 struct drm_device *dev = crtc->base.dev;
1626 struct drm_i915_private *dev_priv = dev->dev_private;
1627 int pipe = crtc->pipe;
1628 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1629 u32 tmp;
1630
1631 assert_pipe_disabled(dev_priv, crtc->pipe);
1632
1633 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1634
1635 mutex_lock(&dev_priv->dpio_lock);
1636
1637 /* Enable back the 10bit clock to display controller */
1638 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1639 tmp |= DPIO_DCLKP_EN;
1640 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1641
1642 /*
1643 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1644 */
1645 udelay(1);
1646
1647 /* Enable PLL */
1648 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1649
1650 /* Check PLL is locked */
1651 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1652 DRM_ERROR("PLL %d failed to lock\n", pipe);
1653
1654 /* not sure when this should be written */
1655 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1656 POSTING_READ(DPLL_MD(pipe));
1657
1658 mutex_unlock(&dev_priv->dpio_lock);
1659 }
1660
1661 static int intel_num_dvo_pipes(struct drm_device *dev)
1662 {
1663 struct intel_crtc *crtc;
1664 int count = 0;
1665
1666 for_each_intel_crtc(dev, crtc)
1667 count += crtc->active &&
1668 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1669
1670 return count;
1671 }
1672
1673 static void i9xx_enable_pll(struct intel_crtc *crtc)
1674 {
1675 struct drm_device *dev = crtc->base.dev;
1676 struct drm_i915_private *dev_priv = dev->dev_private;
1677 int reg = DPLL(crtc->pipe);
1678 u32 dpll = crtc->config->dpll_hw_state.dpll;
1679
1680 assert_pipe_disabled(dev_priv, crtc->pipe);
1681
1682 /* No really, not for ILK+ */
1683 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1684
1685 /* PLL is protected by panel, make sure we can write it */
1686 if (IS_MOBILE(dev) && !IS_I830(dev))
1687 assert_panel_unlocked(dev_priv, crtc->pipe);
1688
1689 /* Enable DVO 2x clock on both PLLs if necessary */
1690 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1691 /*
1692 * It appears to be important that we don't enable this
1693 * for the current pipe before otherwise configuring the
1694 * PLL. No idea how this should be handled if multiple
1695 * DVO outputs are enabled simultaneosly.
1696 */
1697 dpll |= DPLL_DVO_2X_MODE;
1698 I915_WRITE(DPLL(!crtc->pipe),
1699 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1700 }
1701
1702 /* Wait for the clocks to stabilize. */
1703 POSTING_READ(reg);
1704 udelay(150);
1705
1706 if (INTEL_INFO(dev)->gen >= 4) {
1707 I915_WRITE(DPLL_MD(crtc->pipe),
1708 crtc->config->dpll_hw_state.dpll_md);
1709 } else {
1710 /* The pixel multiplier can only be updated once the
1711 * DPLL is enabled and the clocks are stable.
1712 *
1713 * So write it again.
1714 */
1715 I915_WRITE(reg, dpll);
1716 }
1717
1718 /* We do this three times for luck */
1719 I915_WRITE(reg, dpll);
1720 POSTING_READ(reg);
1721 udelay(150); /* wait for warmup */
1722 I915_WRITE(reg, dpll);
1723 POSTING_READ(reg);
1724 udelay(150); /* wait for warmup */
1725 I915_WRITE(reg, dpll);
1726 POSTING_READ(reg);
1727 udelay(150); /* wait for warmup */
1728 }
1729
1730 /**
1731 * i9xx_disable_pll - disable a PLL
1732 * @dev_priv: i915 private structure
1733 * @pipe: pipe PLL to disable
1734 *
1735 * Disable the PLL for @pipe, making sure the pipe is off first.
1736 *
1737 * Note! This is for pre-ILK only.
1738 */
1739 static void i9xx_disable_pll(struct intel_crtc *crtc)
1740 {
1741 struct drm_device *dev = crtc->base.dev;
1742 struct drm_i915_private *dev_priv = dev->dev_private;
1743 enum pipe pipe = crtc->pipe;
1744
1745 /* Disable DVO 2x clock on both PLLs if necessary */
1746 if (IS_I830(dev) &&
1747 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1748 intel_num_dvo_pipes(dev) == 1) {
1749 I915_WRITE(DPLL(PIPE_B),
1750 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1751 I915_WRITE(DPLL(PIPE_A),
1752 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1753 }
1754
1755 /* Don't disable pipe or pipe PLLs if needed */
1756 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1757 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1758 return;
1759
1760 /* Make sure the pipe isn't still relying on us */
1761 assert_pipe_disabled(dev_priv, pipe);
1762
1763 I915_WRITE(DPLL(pipe), 0);
1764 POSTING_READ(DPLL(pipe));
1765 }
1766
1767 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1768 {
1769 u32 val = 0;
1770
1771 /* Make sure the pipe isn't still relying on us */
1772 assert_pipe_disabled(dev_priv, pipe);
1773
1774 /*
1775 * Leave integrated clock source and reference clock enabled for pipe B.
1776 * The latter is needed for VGA hotplug / manual detection.
1777 */
1778 if (pipe == PIPE_B)
1779 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1780 I915_WRITE(DPLL(pipe), val);
1781 POSTING_READ(DPLL(pipe));
1782
1783 }
1784
1785 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1786 {
1787 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1788 u32 val;
1789
1790 /* Make sure the pipe isn't still relying on us */
1791 assert_pipe_disabled(dev_priv, pipe);
1792
1793 /* Set PLL en = 0 */
1794 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1795 if (pipe != PIPE_A)
1796 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1797 I915_WRITE(DPLL(pipe), val);
1798 POSTING_READ(DPLL(pipe));
1799
1800 mutex_lock(&dev_priv->dpio_lock);
1801
1802 /* Disable 10bit clock to display controller */
1803 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1804 val &= ~DPIO_DCLKP_EN;
1805 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1806
1807 /* disable left/right clock distribution */
1808 if (pipe != PIPE_B) {
1809 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1810 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1811 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1812 } else {
1813 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1814 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1815 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1816 }
1817
1818 mutex_unlock(&dev_priv->dpio_lock);
1819 }
1820
1821 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1822 struct intel_digital_port *dport)
1823 {
1824 u32 port_mask;
1825 int dpll_reg;
1826
1827 switch (dport->port) {
1828 case PORT_B:
1829 port_mask = DPLL_PORTB_READY_MASK;
1830 dpll_reg = DPLL(0);
1831 break;
1832 case PORT_C:
1833 port_mask = DPLL_PORTC_READY_MASK;
1834 dpll_reg = DPLL(0);
1835 break;
1836 case PORT_D:
1837 port_mask = DPLL_PORTD_READY_MASK;
1838 dpll_reg = DPIO_PHY_STATUS;
1839 break;
1840 default:
1841 BUG();
1842 }
1843
1844 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1845 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1846 port_name(dport->port), I915_READ(dpll_reg));
1847 }
1848
1849 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1850 {
1851 struct drm_device *dev = crtc->base.dev;
1852 struct drm_i915_private *dev_priv = dev->dev_private;
1853 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1854
1855 if (WARN_ON(pll == NULL))
1856 return;
1857
1858 WARN_ON(!pll->config.crtc_mask);
1859 if (pll->active == 0) {
1860 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1861 WARN_ON(pll->on);
1862 assert_shared_dpll_disabled(dev_priv, pll);
1863
1864 pll->mode_set(dev_priv, pll);
1865 }
1866 }
1867
1868 /**
1869 * intel_enable_shared_dpll - enable PCH PLL
1870 * @dev_priv: i915 private structure
1871 * @pipe: pipe PLL to enable
1872 *
1873 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1874 * drives the transcoder clock.
1875 */
1876 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1877 {
1878 struct drm_device *dev = crtc->base.dev;
1879 struct drm_i915_private *dev_priv = dev->dev_private;
1880 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1881
1882 if (WARN_ON(pll == NULL))
1883 return;
1884
1885 if (WARN_ON(pll->config.crtc_mask == 0))
1886 return;
1887
1888 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1889 pll->name, pll->active, pll->on,
1890 crtc->base.base.id);
1891
1892 if (pll->active++) {
1893 WARN_ON(!pll->on);
1894 assert_shared_dpll_enabled(dev_priv, pll);
1895 return;
1896 }
1897 WARN_ON(pll->on);
1898
1899 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1900
1901 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1902 pll->enable(dev_priv, pll);
1903 pll->on = true;
1904 }
1905
1906 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1907 {
1908 struct drm_device *dev = crtc->base.dev;
1909 struct drm_i915_private *dev_priv = dev->dev_private;
1910 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1911
1912 /* PCH only available on ILK+ */
1913 BUG_ON(INTEL_INFO(dev)->gen < 5);
1914 if (WARN_ON(pll == NULL))
1915 return;
1916
1917 if (WARN_ON(pll->config.crtc_mask == 0))
1918 return;
1919
1920 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1921 pll->name, pll->active, pll->on,
1922 crtc->base.base.id);
1923
1924 if (WARN_ON(pll->active == 0)) {
1925 assert_shared_dpll_disabled(dev_priv, pll);
1926 return;
1927 }
1928
1929 assert_shared_dpll_enabled(dev_priv, pll);
1930 WARN_ON(!pll->on);
1931 if (--pll->active)
1932 return;
1933
1934 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1935 pll->disable(dev_priv, pll);
1936 pll->on = false;
1937
1938 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1939 }
1940
1941 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1942 enum pipe pipe)
1943 {
1944 struct drm_device *dev = dev_priv->dev;
1945 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1946 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1947 uint32_t reg, val, pipeconf_val;
1948
1949 /* PCH only available on ILK+ */
1950 BUG_ON(!HAS_PCH_SPLIT(dev));
1951
1952 /* Make sure PCH DPLL is enabled */
1953 assert_shared_dpll_enabled(dev_priv,
1954 intel_crtc_to_shared_dpll(intel_crtc));
1955
1956 /* FDI must be feeding us bits for PCH ports */
1957 assert_fdi_tx_enabled(dev_priv, pipe);
1958 assert_fdi_rx_enabled(dev_priv, pipe);
1959
1960 if (HAS_PCH_CPT(dev)) {
1961 /* Workaround: Set the timing override bit before enabling the
1962 * pch transcoder. */
1963 reg = TRANS_CHICKEN2(pipe);
1964 val = I915_READ(reg);
1965 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1966 I915_WRITE(reg, val);
1967 }
1968
1969 reg = PCH_TRANSCONF(pipe);
1970 val = I915_READ(reg);
1971 pipeconf_val = I915_READ(PIPECONF(pipe));
1972
1973 if (HAS_PCH_IBX(dev_priv->dev)) {
1974 /*
1975 * make the BPC in transcoder be consistent with
1976 * that in pipeconf reg.
1977 */
1978 val &= ~PIPECONF_BPC_MASK;
1979 val |= pipeconf_val & PIPECONF_BPC_MASK;
1980 }
1981
1982 val &= ~TRANS_INTERLACE_MASK;
1983 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1984 if (HAS_PCH_IBX(dev_priv->dev) &&
1985 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1986 val |= TRANS_LEGACY_INTERLACED_ILK;
1987 else
1988 val |= TRANS_INTERLACED;
1989 else
1990 val |= TRANS_PROGRESSIVE;
1991
1992 I915_WRITE(reg, val | TRANS_ENABLE);
1993 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1994 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1995 }
1996
1997 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1998 enum transcoder cpu_transcoder)
1999 {
2000 u32 val, pipeconf_val;
2001
2002 /* PCH only available on ILK+ */
2003 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2004
2005 /* FDI must be feeding us bits for PCH ports */
2006 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2007 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2008
2009 /* Workaround: set timing override bit. */
2010 val = I915_READ(_TRANSA_CHICKEN2);
2011 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2012 I915_WRITE(_TRANSA_CHICKEN2, val);
2013
2014 val = TRANS_ENABLE;
2015 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2016
2017 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2018 PIPECONF_INTERLACED_ILK)
2019 val |= TRANS_INTERLACED;
2020 else
2021 val |= TRANS_PROGRESSIVE;
2022
2023 I915_WRITE(LPT_TRANSCONF, val);
2024 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2025 DRM_ERROR("Failed to enable PCH transcoder\n");
2026 }
2027
2028 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2029 enum pipe pipe)
2030 {
2031 struct drm_device *dev = dev_priv->dev;
2032 uint32_t reg, val;
2033
2034 /* FDI relies on the transcoder */
2035 assert_fdi_tx_disabled(dev_priv, pipe);
2036 assert_fdi_rx_disabled(dev_priv, pipe);
2037
2038 /* Ports must be off as well */
2039 assert_pch_ports_disabled(dev_priv, pipe);
2040
2041 reg = PCH_TRANSCONF(pipe);
2042 val = I915_READ(reg);
2043 val &= ~TRANS_ENABLE;
2044 I915_WRITE(reg, val);
2045 /* wait for PCH transcoder off, transcoder state */
2046 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2047 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2048
2049 if (!HAS_PCH_IBX(dev)) {
2050 /* Workaround: Clear the timing override chicken bit again. */
2051 reg = TRANS_CHICKEN2(pipe);
2052 val = I915_READ(reg);
2053 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2054 I915_WRITE(reg, val);
2055 }
2056 }
2057
2058 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2059 {
2060 u32 val;
2061
2062 val = I915_READ(LPT_TRANSCONF);
2063 val &= ~TRANS_ENABLE;
2064 I915_WRITE(LPT_TRANSCONF, val);
2065 /* wait for PCH transcoder off, transcoder state */
2066 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2067 DRM_ERROR("Failed to disable PCH transcoder\n");
2068
2069 /* Workaround: clear timing override bit. */
2070 val = I915_READ(_TRANSA_CHICKEN2);
2071 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2072 I915_WRITE(_TRANSA_CHICKEN2, val);
2073 }
2074
2075 /**
2076 * intel_enable_pipe - enable a pipe, asserting requirements
2077 * @crtc: crtc responsible for the pipe
2078 *
2079 * Enable @crtc's pipe, making sure that various hardware specific requirements
2080 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2081 */
2082 static void intel_enable_pipe(struct intel_crtc *crtc)
2083 {
2084 struct drm_device *dev = crtc->base.dev;
2085 struct drm_i915_private *dev_priv = dev->dev_private;
2086 enum pipe pipe = crtc->pipe;
2087 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2088 pipe);
2089 enum pipe pch_transcoder;
2090 int reg;
2091 u32 val;
2092
2093 assert_planes_disabled(dev_priv, pipe);
2094 assert_cursor_disabled(dev_priv, pipe);
2095 assert_sprites_disabled(dev_priv, pipe);
2096
2097 if (HAS_PCH_LPT(dev_priv->dev))
2098 pch_transcoder = TRANSCODER_A;
2099 else
2100 pch_transcoder = pipe;
2101
2102 /*
2103 * A pipe without a PLL won't actually be able to drive bits from
2104 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2105 * need the check.
2106 */
2107 if (!HAS_PCH_SPLIT(dev_priv->dev))
2108 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2109 assert_dsi_pll_enabled(dev_priv);
2110 else
2111 assert_pll_enabled(dev_priv, pipe);
2112 else {
2113 if (crtc->config->has_pch_encoder) {
2114 /* if driving the PCH, we need FDI enabled */
2115 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2116 assert_fdi_tx_pll_enabled(dev_priv,
2117 (enum pipe) cpu_transcoder);
2118 }
2119 /* FIXME: assert CPU port conditions for SNB+ */
2120 }
2121
2122 reg = PIPECONF(cpu_transcoder);
2123 val = I915_READ(reg);
2124 if (val & PIPECONF_ENABLE) {
2125 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2126 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2127 return;
2128 }
2129
2130 I915_WRITE(reg, val | PIPECONF_ENABLE);
2131 POSTING_READ(reg);
2132 }
2133
2134 /**
2135 * intel_disable_pipe - disable a pipe, asserting requirements
2136 * @crtc: crtc whose pipes is to be disabled
2137 *
2138 * Disable the pipe of @crtc, making sure that various hardware
2139 * specific requirements are met, if applicable, e.g. plane
2140 * disabled, panel fitter off, etc.
2141 *
2142 * Will wait until the pipe has shut down before returning.
2143 */
2144 static void intel_disable_pipe(struct intel_crtc *crtc)
2145 {
2146 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2147 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2148 enum pipe pipe = crtc->pipe;
2149 int reg;
2150 u32 val;
2151
2152 /*
2153 * Make sure planes won't keep trying to pump pixels to us,
2154 * or we might hang the display.
2155 */
2156 assert_planes_disabled(dev_priv, pipe);
2157 assert_cursor_disabled(dev_priv, pipe);
2158 assert_sprites_disabled(dev_priv, pipe);
2159
2160 reg = PIPECONF(cpu_transcoder);
2161 val = I915_READ(reg);
2162 if ((val & PIPECONF_ENABLE) == 0)
2163 return;
2164
2165 /*
2166 * Double wide has implications for planes
2167 * so best keep it disabled when not needed.
2168 */
2169 if (crtc->config->double_wide)
2170 val &= ~PIPECONF_DOUBLE_WIDE;
2171
2172 /* Don't disable pipe or pipe PLLs if needed */
2173 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2174 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2175 val &= ~PIPECONF_ENABLE;
2176
2177 I915_WRITE(reg, val);
2178 if ((val & PIPECONF_ENABLE) == 0)
2179 intel_wait_for_pipe_off(crtc);
2180 }
2181
2182 /*
2183 * Plane regs are double buffered, going from enabled->disabled needs a
2184 * trigger in order to latch. The display address reg provides this.
2185 */
2186 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2187 enum plane plane)
2188 {
2189 struct drm_device *dev = dev_priv->dev;
2190 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2191
2192 I915_WRITE(reg, I915_READ(reg));
2193 POSTING_READ(reg);
2194 }
2195
2196 /**
2197 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2198 * @plane: plane to be enabled
2199 * @crtc: crtc for the plane
2200 *
2201 * Enable @plane on @crtc, making sure that the pipe is running first.
2202 */
2203 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2204 struct drm_crtc *crtc)
2205 {
2206 struct drm_device *dev = plane->dev;
2207 struct drm_i915_private *dev_priv = dev->dev_private;
2208 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2209
2210 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2211 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2212
2213 if (intel_crtc->primary_enabled)
2214 return;
2215
2216 intel_crtc->primary_enabled = true;
2217
2218 dev_priv->display.update_primary_plane(crtc, plane->fb,
2219 crtc->x, crtc->y);
2220
2221 /*
2222 * BDW signals flip done immediately if the plane
2223 * is disabled, even if the plane enable is already
2224 * armed to occur at the next vblank :(
2225 */
2226 if (IS_BROADWELL(dev))
2227 intel_wait_for_vblank(dev, intel_crtc->pipe);
2228 }
2229
2230 /**
2231 * intel_disable_primary_hw_plane - disable the primary hardware plane
2232 * @plane: plane to be disabled
2233 * @crtc: crtc for the plane
2234 *
2235 * Disable @plane on @crtc, making sure that the pipe is running first.
2236 */
2237 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2238 struct drm_crtc *crtc)
2239 {
2240 struct drm_device *dev = plane->dev;
2241 struct drm_i915_private *dev_priv = dev->dev_private;
2242 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2243
2244 if (WARN_ON(!intel_crtc->active))
2245 return;
2246
2247 if (!intel_crtc->primary_enabled)
2248 return;
2249
2250 intel_crtc->primary_enabled = false;
2251
2252 dev_priv->display.update_primary_plane(crtc, plane->fb,
2253 crtc->x, crtc->y);
2254 }
2255
2256 static bool need_vtd_wa(struct drm_device *dev)
2257 {
2258 #ifdef CONFIG_INTEL_IOMMU
2259 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2260 return true;
2261 #endif
2262 return false;
2263 }
2264
2265 unsigned int
2266 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2267 uint64_t fb_format_modifier)
2268 {
2269 unsigned int tile_height;
2270 uint32_t pixel_bytes;
2271
2272 switch (fb_format_modifier) {
2273 case DRM_FORMAT_MOD_NONE:
2274 tile_height = 1;
2275 break;
2276 case I915_FORMAT_MOD_X_TILED:
2277 tile_height = IS_GEN2(dev) ? 16 : 8;
2278 break;
2279 case I915_FORMAT_MOD_Y_TILED:
2280 tile_height = 32;
2281 break;
2282 case I915_FORMAT_MOD_Yf_TILED:
2283 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2284 switch (pixel_bytes) {
2285 default:
2286 case 1:
2287 tile_height = 64;
2288 break;
2289 case 2:
2290 case 4:
2291 tile_height = 32;
2292 break;
2293 case 8:
2294 tile_height = 16;
2295 break;
2296 case 16:
2297 WARN_ONCE(1,
2298 "128-bit pixels are not supported for display!");
2299 tile_height = 16;
2300 break;
2301 }
2302 break;
2303 default:
2304 MISSING_CASE(fb_format_modifier);
2305 tile_height = 1;
2306 break;
2307 }
2308
2309 return tile_height;
2310 }
2311
2312 unsigned int
2313 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2314 uint32_t pixel_format, uint64_t fb_format_modifier)
2315 {
2316 return ALIGN(height, intel_tile_height(dev, pixel_format,
2317 fb_format_modifier));
2318 }
2319
2320 static int
2321 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2322 const struct drm_plane_state *plane_state)
2323 {
2324 struct intel_rotation_info *info = &view->rotation_info;
2325 static const struct i915_ggtt_view rotated_view =
2326 { .type = I915_GGTT_VIEW_ROTATED };
2327
2328 *view = i915_ggtt_view_normal;
2329
2330 if (!plane_state)
2331 return 0;
2332
2333 if (!intel_rotation_90_or_270(plane_state->rotation))
2334 return 0;
2335
2336 *view = rotated_view;
2337
2338 info->height = fb->height;
2339 info->pixel_format = fb->pixel_format;
2340 info->pitch = fb->pitches[0];
2341 info->fb_modifier = fb->modifier[0];
2342
2343 if (!(info->fb_modifier == I915_FORMAT_MOD_Y_TILED ||
2344 info->fb_modifier == I915_FORMAT_MOD_Yf_TILED)) {
2345 DRM_DEBUG_KMS(
2346 "Y or Yf tiling is needed for 90/270 rotation!\n");
2347 return -EINVAL;
2348 }
2349
2350 return 0;
2351 }
2352
2353 int
2354 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2355 struct drm_framebuffer *fb,
2356 const struct drm_plane_state *plane_state,
2357 struct intel_engine_cs *pipelined)
2358 {
2359 struct drm_device *dev = fb->dev;
2360 struct drm_i915_private *dev_priv = dev->dev_private;
2361 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2362 struct i915_ggtt_view view;
2363 u32 alignment;
2364 int ret;
2365
2366 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2367
2368 switch (fb->modifier[0]) {
2369 case DRM_FORMAT_MOD_NONE:
2370 if (INTEL_INFO(dev)->gen >= 9)
2371 alignment = 256 * 1024;
2372 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2373 alignment = 128 * 1024;
2374 else if (INTEL_INFO(dev)->gen >= 4)
2375 alignment = 4 * 1024;
2376 else
2377 alignment = 64 * 1024;
2378 break;
2379 case I915_FORMAT_MOD_X_TILED:
2380 if (INTEL_INFO(dev)->gen >= 9)
2381 alignment = 256 * 1024;
2382 else {
2383 /* pin() will align the object as required by fence */
2384 alignment = 0;
2385 }
2386 break;
2387 case I915_FORMAT_MOD_Y_TILED:
2388 case I915_FORMAT_MOD_Yf_TILED:
2389 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2390 "Y tiling bo slipped through, driver bug!\n"))
2391 return -EINVAL;
2392 alignment = 1 * 1024 * 1024;
2393 break;
2394 default:
2395 MISSING_CASE(fb->modifier[0]);
2396 return -EINVAL;
2397 }
2398
2399 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2400 if (ret)
2401 return ret;
2402
2403 /* Note that the w/a also requires 64 PTE of padding following the
2404 * bo. We currently fill all unused PTE with the shadow page and so
2405 * we should always have valid PTE following the scanout preventing
2406 * the VT-d warning.
2407 */
2408 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2409 alignment = 256 * 1024;
2410
2411 /*
2412 * Global gtt pte registers are special registers which actually forward
2413 * writes to a chunk of system memory. Which means that there is no risk
2414 * that the register values disappear as soon as we call
2415 * intel_runtime_pm_put(), so it is correct to wrap only the
2416 * pin/unpin/fence and not more.
2417 */
2418 intel_runtime_pm_get(dev_priv);
2419
2420 dev_priv->mm.interruptible = false;
2421 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2422 &view);
2423 if (ret)
2424 goto err_interruptible;
2425
2426 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2427 * fence, whereas 965+ only requires a fence if using
2428 * framebuffer compression. For simplicity, we always install
2429 * a fence as the cost is not that onerous.
2430 */
2431 ret = i915_gem_object_get_fence(obj);
2432 if (ret)
2433 goto err_unpin;
2434
2435 i915_gem_object_pin_fence(obj);
2436
2437 dev_priv->mm.interruptible = true;
2438 intel_runtime_pm_put(dev_priv);
2439 return 0;
2440
2441 err_unpin:
2442 i915_gem_object_unpin_from_display_plane(obj, &view);
2443 err_interruptible:
2444 dev_priv->mm.interruptible = true;
2445 intel_runtime_pm_put(dev_priv);
2446 return ret;
2447 }
2448
2449 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2450 const struct drm_plane_state *plane_state)
2451 {
2452 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2453 struct i915_ggtt_view view;
2454 int ret;
2455
2456 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2457
2458 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2459 WARN_ONCE(ret, "Couldn't get view from plane state!");
2460
2461 i915_gem_object_unpin_fence(obj);
2462 i915_gem_object_unpin_from_display_plane(obj, &view);
2463 }
2464
2465 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2466 * is assumed to be a power-of-two. */
2467 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2468 unsigned int tiling_mode,
2469 unsigned int cpp,
2470 unsigned int pitch)
2471 {
2472 if (tiling_mode != I915_TILING_NONE) {
2473 unsigned int tile_rows, tiles;
2474
2475 tile_rows = *y / 8;
2476 *y %= 8;
2477
2478 tiles = *x / (512/cpp);
2479 *x %= 512/cpp;
2480
2481 return tile_rows * pitch * 8 + tiles * 4096;
2482 } else {
2483 unsigned int offset;
2484
2485 offset = *y * pitch + *x * cpp;
2486 *y = 0;
2487 *x = (offset & 4095) / cpp;
2488 return offset & -4096;
2489 }
2490 }
2491
2492 static int i9xx_format_to_fourcc(int format)
2493 {
2494 switch (format) {
2495 case DISPPLANE_8BPP:
2496 return DRM_FORMAT_C8;
2497 case DISPPLANE_BGRX555:
2498 return DRM_FORMAT_XRGB1555;
2499 case DISPPLANE_BGRX565:
2500 return DRM_FORMAT_RGB565;
2501 default:
2502 case DISPPLANE_BGRX888:
2503 return DRM_FORMAT_XRGB8888;
2504 case DISPPLANE_RGBX888:
2505 return DRM_FORMAT_XBGR8888;
2506 case DISPPLANE_BGRX101010:
2507 return DRM_FORMAT_XRGB2101010;
2508 case DISPPLANE_RGBX101010:
2509 return DRM_FORMAT_XBGR2101010;
2510 }
2511 }
2512
2513 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2514 {
2515 switch (format) {
2516 case PLANE_CTL_FORMAT_RGB_565:
2517 return DRM_FORMAT_RGB565;
2518 default:
2519 case PLANE_CTL_FORMAT_XRGB_8888:
2520 if (rgb_order) {
2521 if (alpha)
2522 return DRM_FORMAT_ABGR8888;
2523 else
2524 return DRM_FORMAT_XBGR8888;
2525 } else {
2526 if (alpha)
2527 return DRM_FORMAT_ARGB8888;
2528 else
2529 return DRM_FORMAT_XRGB8888;
2530 }
2531 case PLANE_CTL_FORMAT_XRGB_2101010:
2532 if (rgb_order)
2533 return DRM_FORMAT_XBGR2101010;
2534 else
2535 return DRM_FORMAT_XRGB2101010;
2536 }
2537 }
2538
2539 static bool
2540 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2541 struct intel_initial_plane_config *plane_config)
2542 {
2543 struct drm_device *dev = crtc->base.dev;
2544 struct drm_i915_gem_object *obj = NULL;
2545 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2546 struct drm_framebuffer *fb = &plane_config->fb->base;
2547 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2548 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2549 PAGE_SIZE);
2550
2551 size_aligned -= base_aligned;
2552
2553 if (plane_config->size == 0)
2554 return false;
2555
2556 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2557 base_aligned,
2558 base_aligned,
2559 size_aligned);
2560 if (!obj)
2561 return false;
2562
2563 obj->tiling_mode = plane_config->tiling;
2564 if (obj->tiling_mode == I915_TILING_X)
2565 obj->stride = fb->pitches[0];
2566
2567 mode_cmd.pixel_format = fb->pixel_format;
2568 mode_cmd.width = fb->width;
2569 mode_cmd.height = fb->height;
2570 mode_cmd.pitches[0] = fb->pitches[0];
2571 mode_cmd.modifier[0] = fb->modifier[0];
2572 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2573
2574 mutex_lock(&dev->struct_mutex);
2575 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2576 &mode_cmd, obj)) {
2577 DRM_DEBUG_KMS("intel fb init failed\n");
2578 goto out_unref_obj;
2579 }
2580 mutex_unlock(&dev->struct_mutex);
2581
2582 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2583 return true;
2584
2585 out_unref_obj:
2586 drm_gem_object_unreference(&obj->base);
2587 mutex_unlock(&dev->struct_mutex);
2588 return false;
2589 }
2590
2591 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2592 static void
2593 update_state_fb(struct drm_plane *plane)
2594 {
2595 if (plane->fb == plane->state->fb)
2596 return;
2597
2598 if (plane->state->fb)
2599 drm_framebuffer_unreference(plane->state->fb);
2600 plane->state->fb = plane->fb;
2601 if (plane->state->fb)
2602 drm_framebuffer_reference(plane->state->fb);
2603 }
2604
2605 static void
2606 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2607 struct intel_initial_plane_config *plane_config)
2608 {
2609 struct drm_device *dev = intel_crtc->base.dev;
2610 struct drm_i915_private *dev_priv = dev->dev_private;
2611 struct drm_crtc *c;
2612 struct intel_crtc *i;
2613 struct drm_i915_gem_object *obj;
2614 struct drm_plane *primary = intel_crtc->base.primary;
2615 struct drm_framebuffer *fb;
2616
2617 if (!plane_config->fb)
2618 return;
2619
2620 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2621 fb = &plane_config->fb->base;
2622 goto valid_fb;
2623 }
2624
2625 kfree(plane_config->fb);
2626
2627 /*
2628 * Failed to alloc the obj, check to see if we should share
2629 * an fb with another CRTC instead
2630 */
2631 for_each_crtc(dev, c) {
2632 i = to_intel_crtc(c);
2633
2634 if (c == &intel_crtc->base)
2635 continue;
2636
2637 if (!i->active)
2638 continue;
2639
2640 fb = c->primary->fb;
2641 if (!fb)
2642 continue;
2643
2644 obj = intel_fb_obj(fb);
2645 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2646 drm_framebuffer_reference(fb);
2647 goto valid_fb;
2648 }
2649 }
2650
2651 return;
2652
2653 valid_fb:
2654 obj = intel_fb_obj(fb);
2655 if (obj->tiling_mode != I915_TILING_NONE)
2656 dev_priv->preserve_bios_swizzle = true;
2657
2658 primary->fb = fb;
2659 primary->state->crtc = &intel_crtc->base;
2660 primary->crtc = &intel_crtc->base;
2661 update_state_fb(primary);
2662 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2663 }
2664
2665 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2666 struct drm_framebuffer *fb,
2667 int x, int y)
2668 {
2669 struct drm_device *dev = crtc->dev;
2670 struct drm_i915_private *dev_priv = dev->dev_private;
2671 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2672 struct drm_i915_gem_object *obj;
2673 int plane = intel_crtc->plane;
2674 unsigned long linear_offset;
2675 u32 dspcntr;
2676 u32 reg = DSPCNTR(plane);
2677 int pixel_size;
2678
2679 if (!intel_crtc->primary_enabled) {
2680 I915_WRITE(reg, 0);
2681 if (INTEL_INFO(dev)->gen >= 4)
2682 I915_WRITE(DSPSURF(plane), 0);
2683 else
2684 I915_WRITE(DSPADDR(plane), 0);
2685 POSTING_READ(reg);
2686 return;
2687 }
2688
2689 obj = intel_fb_obj(fb);
2690 if (WARN_ON(obj == NULL))
2691 return;
2692
2693 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2694
2695 dspcntr = DISPPLANE_GAMMA_ENABLE;
2696
2697 dspcntr |= DISPLAY_PLANE_ENABLE;
2698
2699 if (INTEL_INFO(dev)->gen < 4) {
2700 if (intel_crtc->pipe == PIPE_B)
2701 dspcntr |= DISPPLANE_SEL_PIPE_B;
2702
2703 /* pipesrc and dspsize control the size that is scaled from,
2704 * which should always be the user's requested size.
2705 */
2706 I915_WRITE(DSPSIZE(plane),
2707 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2708 (intel_crtc->config->pipe_src_w - 1));
2709 I915_WRITE(DSPPOS(plane), 0);
2710 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2711 I915_WRITE(PRIMSIZE(plane),
2712 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2713 (intel_crtc->config->pipe_src_w - 1));
2714 I915_WRITE(PRIMPOS(plane), 0);
2715 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2716 }
2717
2718 switch (fb->pixel_format) {
2719 case DRM_FORMAT_C8:
2720 dspcntr |= DISPPLANE_8BPP;
2721 break;
2722 case DRM_FORMAT_XRGB1555:
2723 case DRM_FORMAT_ARGB1555:
2724 dspcntr |= DISPPLANE_BGRX555;
2725 break;
2726 case DRM_FORMAT_RGB565:
2727 dspcntr |= DISPPLANE_BGRX565;
2728 break;
2729 case DRM_FORMAT_XRGB8888:
2730 case DRM_FORMAT_ARGB8888:
2731 dspcntr |= DISPPLANE_BGRX888;
2732 break;
2733 case DRM_FORMAT_XBGR8888:
2734 case DRM_FORMAT_ABGR8888:
2735 dspcntr |= DISPPLANE_RGBX888;
2736 break;
2737 case DRM_FORMAT_XRGB2101010:
2738 case DRM_FORMAT_ARGB2101010:
2739 dspcntr |= DISPPLANE_BGRX101010;
2740 break;
2741 case DRM_FORMAT_XBGR2101010:
2742 case DRM_FORMAT_ABGR2101010:
2743 dspcntr |= DISPPLANE_RGBX101010;
2744 break;
2745 default:
2746 BUG();
2747 }
2748
2749 if (INTEL_INFO(dev)->gen >= 4 &&
2750 obj->tiling_mode != I915_TILING_NONE)
2751 dspcntr |= DISPPLANE_TILED;
2752
2753 if (IS_G4X(dev))
2754 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2755
2756 linear_offset = y * fb->pitches[0] + x * pixel_size;
2757
2758 if (INTEL_INFO(dev)->gen >= 4) {
2759 intel_crtc->dspaddr_offset =
2760 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2761 pixel_size,
2762 fb->pitches[0]);
2763 linear_offset -= intel_crtc->dspaddr_offset;
2764 } else {
2765 intel_crtc->dspaddr_offset = linear_offset;
2766 }
2767
2768 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2769 dspcntr |= DISPPLANE_ROTATE_180;
2770
2771 x += (intel_crtc->config->pipe_src_w - 1);
2772 y += (intel_crtc->config->pipe_src_h - 1);
2773
2774 /* Finding the last pixel of the last line of the display
2775 data and adding to linear_offset*/
2776 linear_offset +=
2777 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2778 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2779 }
2780
2781 I915_WRITE(reg, dspcntr);
2782
2783 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2784 if (INTEL_INFO(dev)->gen >= 4) {
2785 I915_WRITE(DSPSURF(plane),
2786 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2787 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2788 I915_WRITE(DSPLINOFF(plane), linear_offset);
2789 } else
2790 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2791 POSTING_READ(reg);
2792 }
2793
2794 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2795 struct drm_framebuffer *fb,
2796 int x, int y)
2797 {
2798 struct drm_device *dev = crtc->dev;
2799 struct drm_i915_private *dev_priv = dev->dev_private;
2800 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2801 struct drm_i915_gem_object *obj;
2802 int plane = intel_crtc->plane;
2803 unsigned long linear_offset;
2804 u32 dspcntr;
2805 u32 reg = DSPCNTR(plane);
2806 int pixel_size;
2807
2808 if (!intel_crtc->primary_enabled) {
2809 I915_WRITE(reg, 0);
2810 I915_WRITE(DSPSURF(plane), 0);
2811 POSTING_READ(reg);
2812 return;
2813 }
2814
2815 obj = intel_fb_obj(fb);
2816 if (WARN_ON(obj == NULL))
2817 return;
2818
2819 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2820
2821 dspcntr = DISPPLANE_GAMMA_ENABLE;
2822
2823 dspcntr |= DISPLAY_PLANE_ENABLE;
2824
2825 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2826 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2827
2828 switch (fb->pixel_format) {
2829 case DRM_FORMAT_C8:
2830 dspcntr |= DISPPLANE_8BPP;
2831 break;
2832 case DRM_FORMAT_RGB565:
2833 dspcntr |= DISPPLANE_BGRX565;
2834 break;
2835 case DRM_FORMAT_XRGB8888:
2836 case DRM_FORMAT_ARGB8888:
2837 dspcntr |= DISPPLANE_BGRX888;
2838 break;
2839 case DRM_FORMAT_XBGR8888:
2840 case DRM_FORMAT_ABGR8888:
2841 dspcntr |= DISPPLANE_RGBX888;
2842 break;
2843 case DRM_FORMAT_XRGB2101010:
2844 case DRM_FORMAT_ARGB2101010:
2845 dspcntr |= DISPPLANE_BGRX101010;
2846 break;
2847 case DRM_FORMAT_XBGR2101010:
2848 case DRM_FORMAT_ABGR2101010:
2849 dspcntr |= DISPPLANE_RGBX101010;
2850 break;
2851 default:
2852 BUG();
2853 }
2854
2855 if (obj->tiling_mode != I915_TILING_NONE)
2856 dspcntr |= DISPPLANE_TILED;
2857
2858 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2859 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2860
2861 linear_offset = y * fb->pitches[0] + x * pixel_size;
2862 intel_crtc->dspaddr_offset =
2863 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2864 pixel_size,
2865 fb->pitches[0]);
2866 linear_offset -= intel_crtc->dspaddr_offset;
2867 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2868 dspcntr |= DISPPLANE_ROTATE_180;
2869
2870 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2871 x += (intel_crtc->config->pipe_src_w - 1);
2872 y += (intel_crtc->config->pipe_src_h - 1);
2873
2874 /* Finding the last pixel of the last line of the display
2875 data and adding to linear_offset*/
2876 linear_offset +=
2877 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2878 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2879 }
2880 }
2881
2882 I915_WRITE(reg, dspcntr);
2883
2884 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2885 I915_WRITE(DSPSURF(plane),
2886 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2887 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2888 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2889 } else {
2890 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2891 I915_WRITE(DSPLINOFF(plane), linear_offset);
2892 }
2893 POSTING_READ(reg);
2894 }
2895
2896 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2897 uint32_t pixel_format)
2898 {
2899 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2900
2901 /*
2902 * The stride is either expressed as a multiple of 64 bytes
2903 * chunks for linear buffers or in number of tiles for tiled
2904 * buffers.
2905 */
2906 switch (fb_modifier) {
2907 case DRM_FORMAT_MOD_NONE:
2908 return 64;
2909 case I915_FORMAT_MOD_X_TILED:
2910 if (INTEL_INFO(dev)->gen == 2)
2911 return 128;
2912 return 512;
2913 case I915_FORMAT_MOD_Y_TILED:
2914 /* No need to check for old gens and Y tiling since this is
2915 * about the display engine and those will be blocked before
2916 * we get here.
2917 */
2918 return 128;
2919 case I915_FORMAT_MOD_Yf_TILED:
2920 if (bits_per_pixel == 8)
2921 return 64;
2922 else
2923 return 128;
2924 default:
2925 MISSING_CASE(fb_modifier);
2926 return 64;
2927 }
2928 }
2929
2930 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2931 struct drm_i915_gem_object *obj)
2932 {
2933 enum i915_ggtt_view_type view = I915_GGTT_VIEW_NORMAL;
2934
2935 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2936 view = I915_GGTT_VIEW_ROTATED;
2937
2938 return i915_gem_obj_ggtt_offset_view(obj, view);
2939 }
2940
2941 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2942 struct drm_framebuffer *fb,
2943 int x, int y)
2944 {
2945 struct drm_device *dev = crtc->dev;
2946 struct drm_i915_private *dev_priv = dev->dev_private;
2947 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2948 struct drm_i915_gem_object *obj;
2949 int pipe = intel_crtc->pipe;
2950 u32 plane_ctl, stride_div;
2951 unsigned long surf_addr;
2952
2953 if (!intel_crtc->primary_enabled) {
2954 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2955 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2956 POSTING_READ(PLANE_CTL(pipe, 0));
2957 return;
2958 }
2959
2960 plane_ctl = PLANE_CTL_ENABLE |
2961 PLANE_CTL_PIPE_GAMMA_ENABLE |
2962 PLANE_CTL_PIPE_CSC_ENABLE;
2963
2964 switch (fb->pixel_format) {
2965 case DRM_FORMAT_RGB565:
2966 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2967 break;
2968 case DRM_FORMAT_XRGB8888:
2969 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2970 break;
2971 case DRM_FORMAT_ARGB8888:
2972 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2973 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2974 break;
2975 case DRM_FORMAT_XBGR8888:
2976 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2977 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2978 break;
2979 case DRM_FORMAT_ABGR8888:
2980 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2981 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2982 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2983 break;
2984 case DRM_FORMAT_XRGB2101010:
2985 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2986 break;
2987 case DRM_FORMAT_XBGR2101010:
2988 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2989 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2990 break;
2991 default:
2992 BUG();
2993 }
2994
2995 switch (fb->modifier[0]) {
2996 case DRM_FORMAT_MOD_NONE:
2997 break;
2998 case I915_FORMAT_MOD_X_TILED:
2999 plane_ctl |= PLANE_CTL_TILED_X;
3000 break;
3001 case I915_FORMAT_MOD_Y_TILED:
3002 plane_ctl |= PLANE_CTL_TILED_Y;
3003 break;
3004 case I915_FORMAT_MOD_Yf_TILED:
3005 plane_ctl |= PLANE_CTL_TILED_YF;
3006 break;
3007 default:
3008 MISSING_CASE(fb->modifier[0]);
3009 }
3010
3011 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3012 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180))
3013 plane_ctl |= PLANE_CTL_ROTATE_180;
3014
3015 obj = intel_fb_obj(fb);
3016 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3017 fb->pixel_format);
3018 surf_addr = intel_plane_obj_offset(to_intel_plane(crtc->primary), obj);
3019
3020 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3021 I915_WRITE(PLANE_POS(pipe, 0), 0);
3022 I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
3023 I915_WRITE(PLANE_SIZE(pipe, 0),
3024 (intel_crtc->config->pipe_src_h - 1) << 16 |
3025 (intel_crtc->config->pipe_src_w - 1));
3026 I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div);
3027 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3028
3029 POSTING_READ(PLANE_SURF(pipe, 0));
3030 }
3031
3032 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3033 static int
3034 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3035 int x, int y, enum mode_set_atomic state)
3036 {
3037 struct drm_device *dev = crtc->dev;
3038 struct drm_i915_private *dev_priv = dev->dev_private;
3039
3040 if (dev_priv->display.disable_fbc)
3041 dev_priv->display.disable_fbc(dev);
3042
3043 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3044
3045 return 0;
3046 }
3047
3048 static void intel_complete_page_flips(struct drm_device *dev)
3049 {
3050 struct drm_crtc *crtc;
3051
3052 for_each_crtc(dev, crtc) {
3053 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3054 enum plane plane = intel_crtc->plane;
3055
3056 intel_prepare_page_flip(dev, plane);
3057 intel_finish_page_flip_plane(dev, plane);
3058 }
3059 }
3060
3061 static void intel_update_primary_planes(struct drm_device *dev)
3062 {
3063 struct drm_i915_private *dev_priv = dev->dev_private;
3064 struct drm_crtc *crtc;
3065
3066 for_each_crtc(dev, crtc) {
3067 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3068
3069 drm_modeset_lock(&crtc->mutex, NULL);
3070 /*
3071 * FIXME: Once we have proper support for primary planes (and
3072 * disabling them without disabling the entire crtc) allow again
3073 * a NULL crtc->primary->fb.
3074 */
3075 if (intel_crtc->active && crtc->primary->fb)
3076 dev_priv->display.update_primary_plane(crtc,
3077 crtc->primary->fb,
3078 crtc->x,
3079 crtc->y);
3080 drm_modeset_unlock(&crtc->mutex);
3081 }
3082 }
3083
3084 void intel_prepare_reset(struct drm_device *dev)
3085 {
3086 struct drm_i915_private *dev_priv = to_i915(dev);
3087 struct intel_crtc *crtc;
3088
3089 /* no reset support for gen2 */
3090 if (IS_GEN2(dev))
3091 return;
3092
3093 /* reset doesn't touch the display */
3094 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3095 return;
3096
3097 drm_modeset_lock_all(dev);
3098
3099 /*
3100 * Disabling the crtcs gracefully seems nicer. Also the
3101 * g33 docs say we should at least disable all the planes.
3102 */
3103 for_each_intel_crtc(dev, crtc) {
3104 if (crtc->active)
3105 dev_priv->display.crtc_disable(&crtc->base);
3106 }
3107 }
3108
3109 void intel_finish_reset(struct drm_device *dev)
3110 {
3111 struct drm_i915_private *dev_priv = to_i915(dev);
3112
3113 /*
3114 * Flips in the rings will be nuked by the reset,
3115 * so complete all pending flips so that user space
3116 * will get its events and not get stuck.
3117 */
3118 intel_complete_page_flips(dev);
3119
3120 /* no reset support for gen2 */
3121 if (IS_GEN2(dev))
3122 return;
3123
3124 /* reset doesn't touch the display */
3125 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3126 /*
3127 * Flips in the rings have been nuked by the reset,
3128 * so update the base address of all primary
3129 * planes to the the last fb to make sure we're
3130 * showing the correct fb after a reset.
3131 */
3132 intel_update_primary_planes(dev);
3133 return;
3134 }
3135
3136 /*
3137 * The display has been reset as well,
3138 * so need a full re-initialization.
3139 */
3140 intel_runtime_pm_disable_interrupts(dev_priv);
3141 intel_runtime_pm_enable_interrupts(dev_priv);
3142
3143 intel_modeset_init_hw(dev);
3144
3145 spin_lock_irq(&dev_priv->irq_lock);
3146 if (dev_priv->display.hpd_irq_setup)
3147 dev_priv->display.hpd_irq_setup(dev);
3148 spin_unlock_irq(&dev_priv->irq_lock);
3149
3150 intel_modeset_setup_hw_state(dev, true);
3151
3152 intel_hpd_init(dev_priv);
3153
3154 drm_modeset_unlock_all(dev);
3155 }
3156
3157 static int
3158 intel_finish_fb(struct drm_framebuffer *old_fb)
3159 {
3160 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3161 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3162 bool was_interruptible = dev_priv->mm.interruptible;
3163 int ret;
3164
3165 /* Big Hammer, we also need to ensure that any pending
3166 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3167 * current scanout is retired before unpinning the old
3168 * framebuffer.
3169 *
3170 * This should only fail upon a hung GPU, in which case we
3171 * can safely continue.
3172 */
3173 dev_priv->mm.interruptible = false;
3174 ret = i915_gem_object_finish_gpu(obj);
3175 dev_priv->mm.interruptible = was_interruptible;
3176
3177 return ret;
3178 }
3179
3180 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3181 {
3182 struct drm_device *dev = crtc->dev;
3183 struct drm_i915_private *dev_priv = dev->dev_private;
3184 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3185 bool pending;
3186
3187 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3188 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3189 return false;
3190
3191 spin_lock_irq(&dev->event_lock);
3192 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3193 spin_unlock_irq(&dev->event_lock);
3194
3195 return pending;
3196 }
3197
3198 static void intel_update_pipe_size(struct intel_crtc *crtc)
3199 {
3200 struct drm_device *dev = crtc->base.dev;
3201 struct drm_i915_private *dev_priv = dev->dev_private;
3202 const struct drm_display_mode *adjusted_mode;
3203
3204 if (!i915.fastboot)
3205 return;
3206
3207 /*
3208 * Update pipe size and adjust fitter if needed: the reason for this is
3209 * that in compute_mode_changes we check the native mode (not the pfit
3210 * mode) to see if we can flip rather than do a full mode set. In the
3211 * fastboot case, we'll flip, but if we don't update the pipesrc and
3212 * pfit state, we'll end up with a big fb scanned out into the wrong
3213 * sized surface.
3214 *
3215 * To fix this properly, we need to hoist the checks up into
3216 * compute_mode_changes (or above), check the actual pfit state and
3217 * whether the platform allows pfit disable with pipe active, and only
3218 * then update the pipesrc and pfit state, even on the flip path.
3219 */
3220
3221 adjusted_mode = &crtc->config->base.adjusted_mode;
3222
3223 I915_WRITE(PIPESRC(crtc->pipe),
3224 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3225 (adjusted_mode->crtc_vdisplay - 1));
3226 if (!crtc->config->pch_pfit.enabled &&
3227 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3228 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3229 I915_WRITE(PF_CTL(crtc->pipe), 0);
3230 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3231 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3232 }
3233 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3234 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3235 }
3236
3237 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3238 {
3239 struct drm_device *dev = crtc->dev;
3240 struct drm_i915_private *dev_priv = dev->dev_private;
3241 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3242 int pipe = intel_crtc->pipe;
3243 u32 reg, temp;
3244
3245 /* enable normal train */
3246 reg = FDI_TX_CTL(pipe);
3247 temp = I915_READ(reg);
3248 if (IS_IVYBRIDGE(dev)) {
3249 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3250 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3251 } else {
3252 temp &= ~FDI_LINK_TRAIN_NONE;
3253 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3254 }
3255 I915_WRITE(reg, temp);
3256
3257 reg = FDI_RX_CTL(pipe);
3258 temp = I915_READ(reg);
3259 if (HAS_PCH_CPT(dev)) {
3260 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3261 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3262 } else {
3263 temp &= ~FDI_LINK_TRAIN_NONE;
3264 temp |= FDI_LINK_TRAIN_NONE;
3265 }
3266 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3267
3268 /* wait one idle pattern time */
3269 POSTING_READ(reg);
3270 udelay(1000);
3271
3272 /* IVB wants error correction enabled */
3273 if (IS_IVYBRIDGE(dev))
3274 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3275 FDI_FE_ERRC_ENABLE);
3276 }
3277
3278 /* The FDI link training functions for ILK/Ibexpeak. */
3279 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3280 {
3281 struct drm_device *dev = crtc->dev;
3282 struct drm_i915_private *dev_priv = dev->dev_private;
3283 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3284 int pipe = intel_crtc->pipe;
3285 u32 reg, temp, tries;
3286
3287 /* FDI needs bits from pipe first */
3288 assert_pipe_enabled(dev_priv, pipe);
3289
3290 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3291 for train result */
3292 reg = FDI_RX_IMR(pipe);
3293 temp = I915_READ(reg);
3294 temp &= ~FDI_RX_SYMBOL_LOCK;
3295 temp &= ~FDI_RX_BIT_LOCK;
3296 I915_WRITE(reg, temp);
3297 I915_READ(reg);
3298 udelay(150);
3299
3300 /* enable CPU FDI TX and PCH FDI RX */
3301 reg = FDI_TX_CTL(pipe);
3302 temp = I915_READ(reg);
3303 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3304 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3305 temp &= ~FDI_LINK_TRAIN_NONE;
3306 temp |= FDI_LINK_TRAIN_PATTERN_1;
3307 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3308
3309 reg = FDI_RX_CTL(pipe);
3310 temp = I915_READ(reg);
3311 temp &= ~FDI_LINK_TRAIN_NONE;
3312 temp |= FDI_LINK_TRAIN_PATTERN_1;
3313 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3314
3315 POSTING_READ(reg);
3316 udelay(150);
3317
3318 /* Ironlake workaround, enable clock pointer after FDI enable*/
3319 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3320 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3321 FDI_RX_PHASE_SYNC_POINTER_EN);
3322
3323 reg = FDI_RX_IIR(pipe);
3324 for (tries = 0; tries < 5; tries++) {
3325 temp = I915_READ(reg);
3326 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3327
3328 if ((temp & FDI_RX_BIT_LOCK)) {
3329 DRM_DEBUG_KMS("FDI train 1 done.\n");
3330 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3331 break;
3332 }
3333 }
3334 if (tries == 5)
3335 DRM_ERROR("FDI train 1 fail!\n");
3336
3337 /* Train 2 */
3338 reg = FDI_TX_CTL(pipe);
3339 temp = I915_READ(reg);
3340 temp &= ~FDI_LINK_TRAIN_NONE;
3341 temp |= FDI_LINK_TRAIN_PATTERN_2;
3342 I915_WRITE(reg, temp);
3343
3344 reg = FDI_RX_CTL(pipe);
3345 temp = I915_READ(reg);
3346 temp &= ~FDI_LINK_TRAIN_NONE;
3347 temp |= FDI_LINK_TRAIN_PATTERN_2;
3348 I915_WRITE(reg, temp);
3349
3350 POSTING_READ(reg);
3351 udelay(150);
3352
3353 reg = FDI_RX_IIR(pipe);
3354 for (tries = 0; tries < 5; tries++) {
3355 temp = I915_READ(reg);
3356 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3357
3358 if (temp & FDI_RX_SYMBOL_LOCK) {
3359 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3360 DRM_DEBUG_KMS("FDI train 2 done.\n");
3361 break;
3362 }
3363 }
3364 if (tries == 5)
3365 DRM_ERROR("FDI train 2 fail!\n");
3366
3367 DRM_DEBUG_KMS("FDI train done\n");
3368
3369 }
3370
3371 static const int snb_b_fdi_train_param[] = {
3372 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3373 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3374 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3375 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3376 };
3377
3378 /* The FDI link training functions for SNB/Cougarpoint. */
3379 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3380 {
3381 struct drm_device *dev = crtc->dev;
3382 struct drm_i915_private *dev_priv = dev->dev_private;
3383 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3384 int pipe = intel_crtc->pipe;
3385 u32 reg, temp, i, retry;
3386
3387 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3388 for train result */
3389 reg = FDI_RX_IMR(pipe);
3390 temp = I915_READ(reg);
3391 temp &= ~FDI_RX_SYMBOL_LOCK;
3392 temp &= ~FDI_RX_BIT_LOCK;
3393 I915_WRITE(reg, temp);
3394
3395 POSTING_READ(reg);
3396 udelay(150);
3397
3398 /* enable CPU FDI TX and PCH FDI RX */
3399 reg = FDI_TX_CTL(pipe);
3400 temp = I915_READ(reg);
3401 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3402 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3403 temp &= ~FDI_LINK_TRAIN_NONE;
3404 temp |= FDI_LINK_TRAIN_PATTERN_1;
3405 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3406 /* SNB-B */
3407 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3408 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3409
3410 I915_WRITE(FDI_RX_MISC(pipe),
3411 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3412
3413 reg = FDI_RX_CTL(pipe);
3414 temp = I915_READ(reg);
3415 if (HAS_PCH_CPT(dev)) {
3416 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3417 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3418 } else {
3419 temp &= ~FDI_LINK_TRAIN_NONE;
3420 temp |= FDI_LINK_TRAIN_PATTERN_1;
3421 }
3422 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3423
3424 POSTING_READ(reg);
3425 udelay(150);
3426
3427 for (i = 0; i < 4; i++) {
3428 reg = FDI_TX_CTL(pipe);
3429 temp = I915_READ(reg);
3430 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3431 temp |= snb_b_fdi_train_param[i];
3432 I915_WRITE(reg, temp);
3433
3434 POSTING_READ(reg);
3435 udelay(500);
3436
3437 for (retry = 0; retry < 5; retry++) {
3438 reg = FDI_RX_IIR(pipe);
3439 temp = I915_READ(reg);
3440 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3441 if (temp & FDI_RX_BIT_LOCK) {
3442 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3443 DRM_DEBUG_KMS("FDI train 1 done.\n");
3444 break;
3445 }
3446 udelay(50);
3447 }
3448 if (retry < 5)
3449 break;
3450 }
3451 if (i == 4)
3452 DRM_ERROR("FDI train 1 fail!\n");
3453
3454 /* Train 2 */
3455 reg = FDI_TX_CTL(pipe);
3456 temp = I915_READ(reg);
3457 temp &= ~FDI_LINK_TRAIN_NONE;
3458 temp |= FDI_LINK_TRAIN_PATTERN_2;
3459 if (IS_GEN6(dev)) {
3460 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3461 /* SNB-B */
3462 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3463 }
3464 I915_WRITE(reg, temp);
3465
3466 reg = FDI_RX_CTL(pipe);
3467 temp = I915_READ(reg);
3468 if (HAS_PCH_CPT(dev)) {
3469 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3470 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3471 } else {
3472 temp &= ~FDI_LINK_TRAIN_NONE;
3473 temp |= FDI_LINK_TRAIN_PATTERN_2;
3474 }
3475 I915_WRITE(reg, temp);
3476
3477 POSTING_READ(reg);
3478 udelay(150);
3479
3480 for (i = 0; i < 4; i++) {
3481 reg = FDI_TX_CTL(pipe);
3482 temp = I915_READ(reg);
3483 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3484 temp |= snb_b_fdi_train_param[i];
3485 I915_WRITE(reg, temp);
3486
3487 POSTING_READ(reg);
3488 udelay(500);
3489
3490 for (retry = 0; retry < 5; retry++) {
3491 reg = FDI_RX_IIR(pipe);
3492 temp = I915_READ(reg);
3493 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3494 if (temp & FDI_RX_SYMBOL_LOCK) {
3495 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3496 DRM_DEBUG_KMS("FDI train 2 done.\n");
3497 break;
3498 }
3499 udelay(50);
3500 }
3501 if (retry < 5)
3502 break;
3503 }
3504 if (i == 4)
3505 DRM_ERROR("FDI train 2 fail!\n");
3506
3507 DRM_DEBUG_KMS("FDI train done.\n");
3508 }
3509
3510 /* Manual link training for Ivy Bridge A0 parts */
3511 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3512 {
3513 struct drm_device *dev = crtc->dev;
3514 struct drm_i915_private *dev_priv = dev->dev_private;
3515 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3516 int pipe = intel_crtc->pipe;
3517 u32 reg, temp, i, j;
3518
3519 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3520 for train result */
3521 reg = FDI_RX_IMR(pipe);
3522 temp = I915_READ(reg);
3523 temp &= ~FDI_RX_SYMBOL_LOCK;
3524 temp &= ~FDI_RX_BIT_LOCK;
3525 I915_WRITE(reg, temp);
3526
3527 POSTING_READ(reg);
3528 udelay(150);
3529
3530 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3531 I915_READ(FDI_RX_IIR(pipe)));
3532
3533 /* Try each vswing and preemphasis setting twice before moving on */
3534 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3535 /* disable first in case we need to retry */
3536 reg = FDI_TX_CTL(pipe);
3537 temp = I915_READ(reg);
3538 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3539 temp &= ~FDI_TX_ENABLE;
3540 I915_WRITE(reg, temp);
3541
3542 reg = FDI_RX_CTL(pipe);
3543 temp = I915_READ(reg);
3544 temp &= ~FDI_LINK_TRAIN_AUTO;
3545 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3546 temp &= ~FDI_RX_ENABLE;
3547 I915_WRITE(reg, temp);
3548
3549 /* enable CPU FDI TX and PCH FDI RX */
3550 reg = FDI_TX_CTL(pipe);
3551 temp = I915_READ(reg);
3552 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3553 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3554 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3555 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3556 temp |= snb_b_fdi_train_param[j/2];
3557 temp |= FDI_COMPOSITE_SYNC;
3558 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3559
3560 I915_WRITE(FDI_RX_MISC(pipe),
3561 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3562
3563 reg = FDI_RX_CTL(pipe);
3564 temp = I915_READ(reg);
3565 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3566 temp |= FDI_COMPOSITE_SYNC;
3567 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3568
3569 POSTING_READ(reg);
3570 udelay(1); /* should be 0.5us */
3571
3572 for (i = 0; i < 4; i++) {
3573 reg = FDI_RX_IIR(pipe);
3574 temp = I915_READ(reg);
3575 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3576
3577 if (temp & FDI_RX_BIT_LOCK ||
3578 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3579 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3580 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3581 i);
3582 break;
3583 }
3584 udelay(1); /* should be 0.5us */
3585 }
3586 if (i == 4) {
3587 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3588 continue;
3589 }
3590
3591 /* Train 2 */
3592 reg = FDI_TX_CTL(pipe);
3593 temp = I915_READ(reg);
3594 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3595 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3596 I915_WRITE(reg, temp);
3597
3598 reg = FDI_RX_CTL(pipe);
3599 temp = I915_READ(reg);
3600 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3601 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3602 I915_WRITE(reg, temp);
3603
3604 POSTING_READ(reg);
3605 udelay(2); /* should be 1.5us */
3606
3607 for (i = 0; i < 4; i++) {
3608 reg = FDI_RX_IIR(pipe);
3609 temp = I915_READ(reg);
3610 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3611
3612 if (temp & FDI_RX_SYMBOL_LOCK ||
3613 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3614 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3615 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3616 i);
3617 goto train_done;
3618 }
3619 udelay(2); /* should be 1.5us */
3620 }
3621 if (i == 4)
3622 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3623 }
3624
3625 train_done:
3626 DRM_DEBUG_KMS("FDI train done.\n");
3627 }
3628
3629 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3630 {
3631 struct drm_device *dev = intel_crtc->base.dev;
3632 struct drm_i915_private *dev_priv = dev->dev_private;
3633 int pipe = intel_crtc->pipe;
3634 u32 reg, temp;
3635
3636
3637 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3638 reg = FDI_RX_CTL(pipe);
3639 temp = I915_READ(reg);
3640 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3641 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3642 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3643 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3644
3645 POSTING_READ(reg);
3646 udelay(200);
3647
3648 /* Switch from Rawclk to PCDclk */
3649 temp = I915_READ(reg);
3650 I915_WRITE(reg, temp | FDI_PCDCLK);
3651
3652 POSTING_READ(reg);
3653 udelay(200);
3654
3655 /* Enable CPU FDI TX PLL, always on for Ironlake */
3656 reg = FDI_TX_CTL(pipe);
3657 temp = I915_READ(reg);
3658 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3659 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3660
3661 POSTING_READ(reg);
3662 udelay(100);
3663 }
3664 }
3665
3666 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3667 {
3668 struct drm_device *dev = intel_crtc->base.dev;
3669 struct drm_i915_private *dev_priv = dev->dev_private;
3670 int pipe = intel_crtc->pipe;
3671 u32 reg, temp;
3672
3673 /* Switch from PCDclk to Rawclk */
3674 reg = FDI_RX_CTL(pipe);
3675 temp = I915_READ(reg);
3676 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3677
3678 /* Disable CPU FDI TX PLL */
3679 reg = FDI_TX_CTL(pipe);
3680 temp = I915_READ(reg);
3681 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3682
3683 POSTING_READ(reg);
3684 udelay(100);
3685
3686 reg = FDI_RX_CTL(pipe);
3687 temp = I915_READ(reg);
3688 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3689
3690 /* Wait for the clocks to turn off. */
3691 POSTING_READ(reg);
3692 udelay(100);
3693 }
3694
3695 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3696 {
3697 struct drm_device *dev = crtc->dev;
3698 struct drm_i915_private *dev_priv = dev->dev_private;
3699 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3700 int pipe = intel_crtc->pipe;
3701 u32 reg, temp;
3702
3703 /* disable CPU FDI tx and PCH FDI rx */
3704 reg = FDI_TX_CTL(pipe);
3705 temp = I915_READ(reg);
3706 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3707 POSTING_READ(reg);
3708
3709 reg = FDI_RX_CTL(pipe);
3710 temp = I915_READ(reg);
3711 temp &= ~(0x7 << 16);
3712 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3713 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3714
3715 POSTING_READ(reg);
3716 udelay(100);
3717
3718 /* Ironlake workaround, disable clock pointer after downing FDI */
3719 if (HAS_PCH_IBX(dev))
3720 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3721
3722 /* still set train pattern 1 */
3723 reg = FDI_TX_CTL(pipe);
3724 temp = I915_READ(reg);
3725 temp &= ~FDI_LINK_TRAIN_NONE;
3726 temp |= FDI_LINK_TRAIN_PATTERN_1;
3727 I915_WRITE(reg, temp);
3728
3729 reg = FDI_RX_CTL(pipe);
3730 temp = I915_READ(reg);
3731 if (HAS_PCH_CPT(dev)) {
3732 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3733 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3734 } else {
3735 temp &= ~FDI_LINK_TRAIN_NONE;
3736 temp |= FDI_LINK_TRAIN_PATTERN_1;
3737 }
3738 /* BPC in FDI rx is consistent with that in PIPECONF */
3739 temp &= ~(0x07 << 16);
3740 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3741 I915_WRITE(reg, temp);
3742
3743 POSTING_READ(reg);
3744 udelay(100);
3745 }
3746
3747 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3748 {
3749 struct intel_crtc *crtc;
3750
3751 /* Note that we don't need to be called with mode_config.lock here
3752 * as our list of CRTC objects is static for the lifetime of the
3753 * device and so cannot disappear as we iterate. Similarly, we can
3754 * happily treat the predicates as racy, atomic checks as userspace
3755 * cannot claim and pin a new fb without at least acquring the
3756 * struct_mutex and so serialising with us.
3757 */
3758 for_each_intel_crtc(dev, crtc) {
3759 if (atomic_read(&crtc->unpin_work_count) == 0)
3760 continue;
3761
3762 if (crtc->unpin_work)
3763 intel_wait_for_vblank(dev, crtc->pipe);
3764
3765 return true;
3766 }
3767
3768 return false;
3769 }
3770
3771 static void page_flip_completed(struct intel_crtc *intel_crtc)
3772 {
3773 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3774 struct intel_unpin_work *work = intel_crtc->unpin_work;
3775
3776 /* ensure that the unpin work is consistent wrt ->pending. */
3777 smp_rmb();
3778 intel_crtc->unpin_work = NULL;
3779
3780 if (work->event)
3781 drm_send_vblank_event(intel_crtc->base.dev,
3782 intel_crtc->pipe,
3783 work->event);
3784
3785 drm_crtc_vblank_put(&intel_crtc->base);
3786
3787 wake_up_all(&dev_priv->pending_flip_queue);
3788 queue_work(dev_priv->wq, &work->work);
3789
3790 trace_i915_flip_complete(intel_crtc->plane,
3791 work->pending_flip_obj);
3792 }
3793
3794 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3795 {
3796 struct drm_device *dev = crtc->dev;
3797 struct drm_i915_private *dev_priv = dev->dev_private;
3798
3799 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3800 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3801 !intel_crtc_has_pending_flip(crtc),
3802 60*HZ) == 0)) {
3803 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3804
3805 spin_lock_irq(&dev->event_lock);
3806 if (intel_crtc->unpin_work) {
3807 WARN_ONCE(1, "Removing stuck page flip\n");
3808 page_flip_completed(intel_crtc);
3809 }
3810 spin_unlock_irq(&dev->event_lock);
3811 }
3812
3813 if (crtc->primary->fb) {
3814 mutex_lock(&dev->struct_mutex);
3815 intel_finish_fb(crtc->primary->fb);
3816 mutex_unlock(&dev->struct_mutex);
3817 }
3818 }
3819
3820 /* Program iCLKIP clock to the desired frequency */
3821 static void lpt_program_iclkip(struct drm_crtc *crtc)
3822 {
3823 struct drm_device *dev = crtc->dev;
3824 struct drm_i915_private *dev_priv = dev->dev_private;
3825 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3826 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3827 u32 temp;
3828
3829 mutex_lock(&dev_priv->dpio_lock);
3830
3831 /* It is necessary to ungate the pixclk gate prior to programming
3832 * the divisors, and gate it back when it is done.
3833 */
3834 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3835
3836 /* Disable SSCCTL */
3837 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3838 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3839 SBI_SSCCTL_DISABLE,
3840 SBI_ICLK);
3841
3842 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3843 if (clock == 20000) {
3844 auxdiv = 1;
3845 divsel = 0x41;
3846 phaseinc = 0x20;
3847 } else {
3848 /* The iCLK virtual clock root frequency is in MHz,
3849 * but the adjusted_mode->crtc_clock in in KHz. To get the
3850 * divisors, it is necessary to divide one by another, so we
3851 * convert the virtual clock precision to KHz here for higher
3852 * precision.
3853 */
3854 u32 iclk_virtual_root_freq = 172800 * 1000;
3855 u32 iclk_pi_range = 64;
3856 u32 desired_divisor, msb_divisor_value, pi_value;
3857
3858 desired_divisor = (iclk_virtual_root_freq / clock);
3859 msb_divisor_value = desired_divisor / iclk_pi_range;
3860 pi_value = desired_divisor % iclk_pi_range;
3861
3862 auxdiv = 0;
3863 divsel = msb_divisor_value - 2;
3864 phaseinc = pi_value;
3865 }
3866
3867 /* This should not happen with any sane values */
3868 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3869 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3870 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3871 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3872
3873 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3874 clock,
3875 auxdiv,
3876 divsel,
3877 phasedir,
3878 phaseinc);
3879
3880 /* Program SSCDIVINTPHASE6 */
3881 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3882 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3883 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3884 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3885 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3886 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3887 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3888 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3889
3890 /* Program SSCAUXDIV */
3891 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3892 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3893 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3894 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3895
3896 /* Enable modulator and associated divider */
3897 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3898 temp &= ~SBI_SSCCTL_DISABLE;
3899 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3900
3901 /* Wait for initialization time */
3902 udelay(24);
3903
3904 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3905
3906 mutex_unlock(&dev_priv->dpio_lock);
3907 }
3908
3909 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3910 enum pipe pch_transcoder)
3911 {
3912 struct drm_device *dev = crtc->base.dev;
3913 struct drm_i915_private *dev_priv = dev->dev_private;
3914 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3915
3916 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3917 I915_READ(HTOTAL(cpu_transcoder)));
3918 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3919 I915_READ(HBLANK(cpu_transcoder)));
3920 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3921 I915_READ(HSYNC(cpu_transcoder)));
3922
3923 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3924 I915_READ(VTOTAL(cpu_transcoder)));
3925 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3926 I915_READ(VBLANK(cpu_transcoder)));
3927 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3928 I915_READ(VSYNC(cpu_transcoder)));
3929 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3930 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3931 }
3932
3933 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
3934 {
3935 struct drm_i915_private *dev_priv = dev->dev_private;
3936 uint32_t temp;
3937
3938 temp = I915_READ(SOUTH_CHICKEN1);
3939 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
3940 return;
3941
3942 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3943 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3944
3945 temp &= ~FDI_BC_BIFURCATION_SELECT;
3946 if (enable)
3947 temp |= FDI_BC_BIFURCATION_SELECT;
3948
3949 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
3950 I915_WRITE(SOUTH_CHICKEN1, temp);
3951 POSTING_READ(SOUTH_CHICKEN1);
3952 }
3953
3954 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3955 {
3956 struct drm_device *dev = intel_crtc->base.dev;
3957
3958 switch (intel_crtc->pipe) {
3959 case PIPE_A:
3960 break;
3961 case PIPE_B:
3962 if (intel_crtc->config->fdi_lanes > 2)
3963 cpt_set_fdi_bc_bifurcation(dev, false);
3964 else
3965 cpt_set_fdi_bc_bifurcation(dev, true);
3966
3967 break;
3968 case PIPE_C:
3969 cpt_set_fdi_bc_bifurcation(dev, true);
3970
3971 break;
3972 default:
3973 BUG();
3974 }
3975 }
3976
3977 /*
3978 * Enable PCH resources required for PCH ports:
3979 * - PCH PLLs
3980 * - FDI training & RX/TX
3981 * - update transcoder timings
3982 * - DP transcoding bits
3983 * - transcoder
3984 */
3985 static void ironlake_pch_enable(struct drm_crtc *crtc)
3986 {
3987 struct drm_device *dev = crtc->dev;
3988 struct drm_i915_private *dev_priv = dev->dev_private;
3989 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3990 int pipe = intel_crtc->pipe;
3991 u32 reg, temp;
3992
3993 assert_pch_transcoder_disabled(dev_priv, pipe);
3994
3995 if (IS_IVYBRIDGE(dev))
3996 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3997
3998 /* Write the TU size bits before fdi link training, so that error
3999 * detection works. */
4000 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4001 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4002
4003 /* For PCH output, training FDI link */
4004 dev_priv->display.fdi_link_train(crtc);
4005
4006 /* We need to program the right clock selection before writing the pixel
4007 * mutliplier into the DPLL. */
4008 if (HAS_PCH_CPT(dev)) {
4009 u32 sel;
4010
4011 temp = I915_READ(PCH_DPLL_SEL);
4012 temp |= TRANS_DPLL_ENABLE(pipe);
4013 sel = TRANS_DPLLB_SEL(pipe);
4014 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4015 temp |= sel;
4016 else
4017 temp &= ~sel;
4018 I915_WRITE(PCH_DPLL_SEL, temp);
4019 }
4020
4021 /* XXX: pch pll's can be enabled any time before we enable the PCH
4022 * transcoder, and we actually should do this to not upset any PCH
4023 * transcoder that already use the clock when we share it.
4024 *
4025 * Note that enable_shared_dpll tries to do the right thing, but
4026 * get_shared_dpll unconditionally resets the pll - we need that to have
4027 * the right LVDS enable sequence. */
4028 intel_enable_shared_dpll(intel_crtc);
4029
4030 /* set transcoder timing, panel must allow it */
4031 assert_panel_unlocked(dev_priv, pipe);
4032 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4033
4034 intel_fdi_normal_train(crtc);
4035
4036 /* For PCH DP, enable TRANS_DP_CTL */
4037 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4038 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4039 reg = TRANS_DP_CTL(pipe);
4040 temp = I915_READ(reg);
4041 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4042 TRANS_DP_SYNC_MASK |
4043 TRANS_DP_BPC_MASK);
4044 temp |= (TRANS_DP_OUTPUT_ENABLE |
4045 TRANS_DP_ENH_FRAMING);
4046 temp |= bpc << 9; /* same format but at 11:9 */
4047
4048 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4049 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4050 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4051 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4052
4053 switch (intel_trans_dp_port_sel(crtc)) {
4054 case PCH_DP_B:
4055 temp |= TRANS_DP_PORT_SEL_B;
4056 break;
4057 case PCH_DP_C:
4058 temp |= TRANS_DP_PORT_SEL_C;
4059 break;
4060 case PCH_DP_D:
4061 temp |= TRANS_DP_PORT_SEL_D;
4062 break;
4063 default:
4064 BUG();
4065 }
4066
4067 I915_WRITE(reg, temp);
4068 }
4069
4070 ironlake_enable_pch_transcoder(dev_priv, pipe);
4071 }
4072
4073 static void lpt_pch_enable(struct drm_crtc *crtc)
4074 {
4075 struct drm_device *dev = crtc->dev;
4076 struct drm_i915_private *dev_priv = dev->dev_private;
4077 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4078 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4079
4080 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4081
4082 lpt_program_iclkip(crtc);
4083
4084 /* Set transcoder timing. */
4085 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4086
4087 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4088 }
4089
4090 void intel_put_shared_dpll(struct intel_crtc *crtc)
4091 {
4092 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4093
4094 if (pll == NULL)
4095 return;
4096
4097 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
4098 WARN(1, "bad %s crtc mask\n", pll->name);
4099 return;
4100 }
4101
4102 pll->config.crtc_mask &= ~(1 << crtc->pipe);
4103 if (pll->config.crtc_mask == 0) {
4104 WARN_ON(pll->on);
4105 WARN_ON(pll->active);
4106 }
4107
4108 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
4109 }
4110
4111 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4112 struct intel_crtc_state *crtc_state)
4113 {
4114 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4115 struct intel_shared_dpll *pll;
4116 enum intel_dpll_id i;
4117
4118 if (HAS_PCH_IBX(dev_priv->dev)) {
4119 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4120 i = (enum intel_dpll_id) crtc->pipe;
4121 pll = &dev_priv->shared_dplls[i];
4122
4123 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4124 crtc->base.base.id, pll->name);
4125
4126 WARN_ON(pll->new_config->crtc_mask);
4127
4128 goto found;
4129 }
4130
4131 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4132 pll = &dev_priv->shared_dplls[i];
4133
4134 /* Only want to check enabled timings first */
4135 if (pll->new_config->crtc_mask == 0)
4136 continue;
4137
4138 if (memcmp(&crtc_state->dpll_hw_state,
4139 &pll->new_config->hw_state,
4140 sizeof(pll->new_config->hw_state)) == 0) {
4141 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4142 crtc->base.base.id, pll->name,
4143 pll->new_config->crtc_mask,
4144 pll->active);
4145 goto found;
4146 }
4147 }
4148
4149 /* Ok no matching timings, maybe there's a free one? */
4150 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4151 pll = &dev_priv->shared_dplls[i];
4152 if (pll->new_config->crtc_mask == 0) {
4153 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4154 crtc->base.base.id, pll->name);
4155 goto found;
4156 }
4157 }
4158
4159 return NULL;
4160
4161 found:
4162 if (pll->new_config->crtc_mask == 0)
4163 pll->new_config->hw_state = crtc_state->dpll_hw_state;
4164
4165 crtc_state->shared_dpll = i;
4166 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4167 pipe_name(crtc->pipe));
4168
4169 pll->new_config->crtc_mask |= 1 << crtc->pipe;
4170
4171 return pll;
4172 }
4173
4174 /**
4175 * intel_shared_dpll_start_config - start a new PLL staged config
4176 * @dev_priv: DRM device
4177 * @clear_pipes: mask of pipes that will have their PLLs freed
4178 *
4179 * Starts a new PLL staged config, copying the current config but
4180 * releasing the references of pipes specified in clear_pipes.
4181 */
4182 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4183 unsigned clear_pipes)
4184 {
4185 struct intel_shared_dpll *pll;
4186 enum intel_dpll_id i;
4187
4188 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4189 pll = &dev_priv->shared_dplls[i];
4190
4191 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4192 GFP_KERNEL);
4193 if (!pll->new_config)
4194 goto cleanup;
4195
4196 pll->new_config->crtc_mask &= ~clear_pipes;
4197 }
4198
4199 return 0;
4200
4201 cleanup:
4202 while (--i >= 0) {
4203 pll = &dev_priv->shared_dplls[i];
4204 kfree(pll->new_config);
4205 pll->new_config = NULL;
4206 }
4207
4208 return -ENOMEM;
4209 }
4210
4211 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4212 {
4213 struct intel_shared_dpll *pll;
4214 enum intel_dpll_id i;
4215
4216 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4217 pll = &dev_priv->shared_dplls[i];
4218
4219 WARN_ON(pll->new_config == &pll->config);
4220
4221 pll->config = *pll->new_config;
4222 kfree(pll->new_config);
4223 pll->new_config = NULL;
4224 }
4225 }
4226
4227 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4228 {
4229 struct intel_shared_dpll *pll;
4230 enum intel_dpll_id i;
4231
4232 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4233 pll = &dev_priv->shared_dplls[i];
4234
4235 WARN_ON(pll->new_config == &pll->config);
4236
4237 kfree(pll->new_config);
4238 pll->new_config = NULL;
4239 }
4240 }
4241
4242 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4243 {
4244 struct drm_i915_private *dev_priv = dev->dev_private;
4245 int dslreg = PIPEDSL(pipe);
4246 u32 temp;
4247
4248 temp = I915_READ(dslreg);
4249 udelay(500);
4250 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4251 if (wait_for(I915_READ(dslreg) != temp, 5))
4252 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4253 }
4254 }
4255
4256 static void skylake_pfit_enable(struct intel_crtc *crtc)
4257 {
4258 struct drm_device *dev = crtc->base.dev;
4259 struct drm_i915_private *dev_priv = dev->dev_private;
4260 int pipe = crtc->pipe;
4261
4262 if (crtc->config->pch_pfit.enabled) {
4263 I915_WRITE(PS_CTL(pipe), PS_ENABLE);
4264 I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4265 I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4266 }
4267 }
4268
4269 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4270 {
4271 struct drm_device *dev = crtc->base.dev;
4272 struct drm_i915_private *dev_priv = dev->dev_private;
4273 int pipe = crtc->pipe;
4274
4275 if (crtc->config->pch_pfit.enabled) {
4276 /* Force use of hard-coded filter coefficients
4277 * as some pre-programmed values are broken,
4278 * e.g. x201.
4279 */
4280 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4281 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4282 PF_PIPE_SEL_IVB(pipe));
4283 else
4284 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4285 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4286 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4287 }
4288 }
4289
4290 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4291 {
4292 struct drm_device *dev = crtc->dev;
4293 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4294 struct drm_plane *plane;
4295 struct intel_plane *intel_plane;
4296
4297 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4298 intel_plane = to_intel_plane(plane);
4299 if (intel_plane->pipe == pipe)
4300 intel_plane_restore(&intel_plane->base);
4301 }
4302 }
4303
4304 /*
4305 * Disable a plane internally without actually modifying the plane's state.
4306 * This will allow us to easily restore the plane later by just reprogramming
4307 * its state.
4308 */
4309 static void disable_plane_internal(struct drm_plane *plane)
4310 {
4311 struct intel_plane *intel_plane = to_intel_plane(plane);
4312 struct drm_plane_state *state =
4313 plane->funcs->atomic_duplicate_state(plane);
4314 struct intel_plane_state *intel_state = to_intel_plane_state(state);
4315
4316 intel_state->visible = false;
4317 intel_plane->commit_plane(plane, intel_state);
4318
4319 intel_plane_destroy_state(plane, state);
4320 }
4321
4322 static void intel_disable_sprite_planes(struct drm_crtc *crtc)
4323 {
4324 struct drm_device *dev = crtc->dev;
4325 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4326 struct drm_plane *plane;
4327 struct intel_plane *intel_plane;
4328
4329 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4330 intel_plane = to_intel_plane(plane);
4331 if (plane->fb && intel_plane->pipe == pipe)
4332 disable_plane_internal(plane);
4333 }
4334 }
4335
4336 void hsw_enable_ips(struct intel_crtc *crtc)
4337 {
4338 struct drm_device *dev = crtc->base.dev;
4339 struct drm_i915_private *dev_priv = dev->dev_private;
4340
4341 if (!crtc->config->ips_enabled)
4342 return;
4343
4344 /* We can only enable IPS after we enable a plane and wait for a vblank */
4345 intel_wait_for_vblank(dev, crtc->pipe);
4346
4347 assert_plane_enabled(dev_priv, crtc->plane);
4348 if (IS_BROADWELL(dev)) {
4349 mutex_lock(&dev_priv->rps.hw_lock);
4350 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4351 mutex_unlock(&dev_priv->rps.hw_lock);
4352 /* Quoting Art Runyan: "its not safe to expect any particular
4353 * value in IPS_CTL bit 31 after enabling IPS through the
4354 * mailbox." Moreover, the mailbox may return a bogus state,
4355 * so we need to just enable it and continue on.
4356 */
4357 } else {
4358 I915_WRITE(IPS_CTL, IPS_ENABLE);
4359 /* The bit only becomes 1 in the next vblank, so this wait here
4360 * is essentially intel_wait_for_vblank. If we don't have this
4361 * and don't wait for vblanks until the end of crtc_enable, then
4362 * the HW state readout code will complain that the expected
4363 * IPS_CTL value is not the one we read. */
4364 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4365 DRM_ERROR("Timed out waiting for IPS enable\n");
4366 }
4367 }
4368
4369 void hsw_disable_ips(struct intel_crtc *crtc)
4370 {
4371 struct drm_device *dev = crtc->base.dev;
4372 struct drm_i915_private *dev_priv = dev->dev_private;
4373
4374 if (!crtc->config->ips_enabled)
4375 return;
4376
4377 assert_plane_enabled(dev_priv, crtc->plane);
4378 if (IS_BROADWELL(dev)) {
4379 mutex_lock(&dev_priv->rps.hw_lock);
4380 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4381 mutex_unlock(&dev_priv->rps.hw_lock);
4382 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4383 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4384 DRM_ERROR("Timed out waiting for IPS disable\n");
4385 } else {
4386 I915_WRITE(IPS_CTL, 0);
4387 POSTING_READ(IPS_CTL);
4388 }
4389
4390 /* We need to wait for a vblank before we can disable the plane. */
4391 intel_wait_for_vblank(dev, crtc->pipe);
4392 }
4393
4394 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4395 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4396 {
4397 struct drm_device *dev = crtc->dev;
4398 struct drm_i915_private *dev_priv = dev->dev_private;
4399 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4400 enum pipe pipe = intel_crtc->pipe;
4401 int palreg = PALETTE(pipe);
4402 int i;
4403 bool reenable_ips = false;
4404
4405 /* The clocks have to be on to load the palette. */
4406 if (!crtc->state->enable || !intel_crtc->active)
4407 return;
4408
4409 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4410 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4411 assert_dsi_pll_enabled(dev_priv);
4412 else
4413 assert_pll_enabled(dev_priv, pipe);
4414 }
4415
4416 /* use legacy palette for Ironlake */
4417 if (!HAS_GMCH_DISPLAY(dev))
4418 palreg = LGC_PALETTE(pipe);
4419
4420 /* Workaround : Do not read or write the pipe palette/gamma data while
4421 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4422 */
4423 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4424 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4425 GAMMA_MODE_MODE_SPLIT)) {
4426 hsw_disable_ips(intel_crtc);
4427 reenable_ips = true;
4428 }
4429
4430 for (i = 0; i < 256; i++) {
4431 I915_WRITE(palreg + 4 * i,
4432 (intel_crtc->lut_r[i] << 16) |
4433 (intel_crtc->lut_g[i] << 8) |
4434 intel_crtc->lut_b[i]);
4435 }
4436
4437 if (reenable_ips)
4438 hsw_enable_ips(intel_crtc);
4439 }
4440
4441 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4442 {
4443 if (!enable && intel_crtc->overlay) {
4444 struct drm_device *dev = intel_crtc->base.dev;
4445 struct drm_i915_private *dev_priv = dev->dev_private;
4446
4447 mutex_lock(&dev->struct_mutex);
4448 dev_priv->mm.interruptible = false;
4449 (void) intel_overlay_switch_off(intel_crtc->overlay);
4450 dev_priv->mm.interruptible = true;
4451 mutex_unlock(&dev->struct_mutex);
4452 }
4453
4454 /* Let userspace switch the overlay on again. In most cases userspace
4455 * has to recompute where to put it anyway.
4456 */
4457 }
4458
4459 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4460 {
4461 struct drm_device *dev = crtc->dev;
4462 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4463 int pipe = intel_crtc->pipe;
4464
4465 intel_enable_primary_hw_plane(crtc->primary, crtc);
4466 intel_enable_sprite_planes(crtc);
4467 intel_crtc_update_cursor(crtc, true);
4468 intel_crtc_dpms_overlay(intel_crtc, true);
4469
4470 hsw_enable_ips(intel_crtc);
4471
4472 mutex_lock(&dev->struct_mutex);
4473 intel_fbc_update(dev);
4474 mutex_unlock(&dev->struct_mutex);
4475
4476 /*
4477 * FIXME: Once we grow proper nuclear flip support out of this we need
4478 * to compute the mask of flip planes precisely. For the time being
4479 * consider this a flip from a NULL plane.
4480 */
4481 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4482 }
4483
4484 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4485 {
4486 struct drm_device *dev = crtc->dev;
4487 struct drm_i915_private *dev_priv = dev->dev_private;
4488 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4489 int pipe = intel_crtc->pipe;
4490
4491 intel_crtc_wait_for_pending_flips(crtc);
4492
4493 if (dev_priv->fbc.crtc == intel_crtc)
4494 intel_fbc_disable(dev);
4495
4496 hsw_disable_ips(intel_crtc);
4497
4498 intel_crtc_dpms_overlay(intel_crtc, false);
4499 intel_crtc_update_cursor(crtc, false);
4500 intel_disable_sprite_planes(crtc);
4501 intel_disable_primary_hw_plane(crtc->primary, crtc);
4502
4503 /*
4504 * FIXME: Once we grow proper nuclear flip support out of this we need
4505 * to compute the mask of flip planes precisely. For the time being
4506 * consider this a flip to a NULL plane.
4507 */
4508 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4509 }
4510
4511 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4512 {
4513 struct drm_device *dev = crtc->dev;
4514 struct drm_i915_private *dev_priv = dev->dev_private;
4515 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4516 struct intel_encoder *encoder;
4517 int pipe = intel_crtc->pipe;
4518
4519 WARN_ON(!crtc->state->enable);
4520
4521 if (intel_crtc->active)
4522 return;
4523
4524 if (intel_crtc->config->has_pch_encoder)
4525 intel_prepare_shared_dpll(intel_crtc);
4526
4527 if (intel_crtc->config->has_dp_encoder)
4528 intel_dp_set_m_n(intel_crtc, M1_N1);
4529
4530 intel_set_pipe_timings(intel_crtc);
4531
4532 if (intel_crtc->config->has_pch_encoder) {
4533 intel_cpu_transcoder_set_m_n(intel_crtc,
4534 &intel_crtc->config->fdi_m_n, NULL);
4535 }
4536
4537 ironlake_set_pipeconf(crtc);
4538
4539 intel_crtc->active = true;
4540
4541 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4542 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4543
4544 for_each_encoder_on_crtc(dev, crtc, encoder)
4545 if (encoder->pre_enable)
4546 encoder->pre_enable(encoder);
4547
4548 if (intel_crtc->config->has_pch_encoder) {
4549 /* Note: FDI PLL enabling _must_ be done before we enable the
4550 * cpu pipes, hence this is separate from all the other fdi/pch
4551 * enabling. */
4552 ironlake_fdi_pll_enable(intel_crtc);
4553 } else {
4554 assert_fdi_tx_disabled(dev_priv, pipe);
4555 assert_fdi_rx_disabled(dev_priv, pipe);
4556 }
4557
4558 ironlake_pfit_enable(intel_crtc);
4559
4560 /*
4561 * On ILK+ LUT must be loaded before the pipe is running but with
4562 * clocks enabled
4563 */
4564 intel_crtc_load_lut(crtc);
4565
4566 intel_update_watermarks(crtc);
4567 intel_enable_pipe(intel_crtc);
4568
4569 if (intel_crtc->config->has_pch_encoder)
4570 ironlake_pch_enable(crtc);
4571
4572 assert_vblank_disabled(crtc);
4573 drm_crtc_vblank_on(crtc);
4574
4575 for_each_encoder_on_crtc(dev, crtc, encoder)
4576 encoder->enable(encoder);
4577
4578 if (HAS_PCH_CPT(dev))
4579 cpt_verify_modeset(dev, intel_crtc->pipe);
4580
4581 intel_crtc_enable_planes(crtc);
4582 }
4583
4584 /* IPS only exists on ULT machines and is tied to pipe A. */
4585 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4586 {
4587 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4588 }
4589
4590 /*
4591 * This implements the workaround described in the "notes" section of the mode
4592 * set sequence documentation. When going from no pipes or single pipe to
4593 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4594 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4595 */
4596 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4597 {
4598 struct drm_device *dev = crtc->base.dev;
4599 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4600
4601 /* We want to get the other_active_crtc only if there's only 1 other
4602 * active crtc. */
4603 for_each_intel_crtc(dev, crtc_it) {
4604 if (!crtc_it->active || crtc_it == crtc)
4605 continue;
4606
4607 if (other_active_crtc)
4608 return;
4609
4610 other_active_crtc = crtc_it;
4611 }
4612 if (!other_active_crtc)
4613 return;
4614
4615 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4616 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4617 }
4618
4619 static void haswell_crtc_enable(struct drm_crtc *crtc)
4620 {
4621 struct drm_device *dev = crtc->dev;
4622 struct drm_i915_private *dev_priv = dev->dev_private;
4623 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4624 struct intel_encoder *encoder;
4625 int pipe = intel_crtc->pipe;
4626
4627 WARN_ON(!crtc->state->enable);
4628
4629 if (intel_crtc->active)
4630 return;
4631
4632 if (intel_crtc_to_shared_dpll(intel_crtc))
4633 intel_enable_shared_dpll(intel_crtc);
4634
4635 if (intel_crtc->config->has_dp_encoder)
4636 intel_dp_set_m_n(intel_crtc, M1_N1);
4637
4638 intel_set_pipe_timings(intel_crtc);
4639
4640 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4641 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4642 intel_crtc->config->pixel_multiplier - 1);
4643 }
4644
4645 if (intel_crtc->config->has_pch_encoder) {
4646 intel_cpu_transcoder_set_m_n(intel_crtc,
4647 &intel_crtc->config->fdi_m_n, NULL);
4648 }
4649
4650 haswell_set_pipeconf(crtc);
4651
4652 intel_set_pipe_csc(crtc);
4653
4654 intel_crtc->active = true;
4655
4656 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4657 for_each_encoder_on_crtc(dev, crtc, encoder)
4658 if (encoder->pre_enable)
4659 encoder->pre_enable(encoder);
4660
4661 if (intel_crtc->config->has_pch_encoder) {
4662 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4663 true);
4664 dev_priv->display.fdi_link_train(crtc);
4665 }
4666
4667 intel_ddi_enable_pipe_clock(intel_crtc);
4668
4669 if (IS_SKYLAKE(dev))
4670 skylake_pfit_enable(intel_crtc);
4671 else
4672 ironlake_pfit_enable(intel_crtc);
4673
4674 /*
4675 * On ILK+ LUT must be loaded before the pipe is running but with
4676 * clocks enabled
4677 */
4678 intel_crtc_load_lut(crtc);
4679
4680 intel_ddi_set_pipe_settings(crtc);
4681 intel_ddi_enable_transcoder_func(crtc);
4682
4683 intel_update_watermarks(crtc);
4684 intel_enable_pipe(intel_crtc);
4685
4686 if (intel_crtc->config->has_pch_encoder)
4687 lpt_pch_enable(crtc);
4688
4689 if (intel_crtc->config->dp_encoder_is_mst)
4690 intel_ddi_set_vc_payload_alloc(crtc, true);
4691
4692 assert_vblank_disabled(crtc);
4693 drm_crtc_vblank_on(crtc);
4694
4695 for_each_encoder_on_crtc(dev, crtc, encoder) {
4696 encoder->enable(encoder);
4697 intel_opregion_notify_encoder(encoder, true);
4698 }
4699
4700 /* If we change the relative order between pipe/planes enabling, we need
4701 * to change the workaround. */
4702 haswell_mode_set_planes_workaround(intel_crtc);
4703 intel_crtc_enable_planes(crtc);
4704 }
4705
4706 static void skylake_pfit_disable(struct intel_crtc *crtc)
4707 {
4708 struct drm_device *dev = crtc->base.dev;
4709 struct drm_i915_private *dev_priv = dev->dev_private;
4710 int pipe = crtc->pipe;
4711
4712 /* To avoid upsetting the power well on haswell only disable the pfit if
4713 * it's in use. The hw state code will make sure we get this right. */
4714 if (crtc->config->pch_pfit.enabled) {
4715 I915_WRITE(PS_CTL(pipe), 0);
4716 I915_WRITE(PS_WIN_POS(pipe), 0);
4717 I915_WRITE(PS_WIN_SZ(pipe), 0);
4718 }
4719 }
4720
4721 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4722 {
4723 struct drm_device *dev = crtc->base.dev;
4724 struct drm_i915_private *dev_priv = dev->dev_private;
4725 int pipe = crtc->pipe;
4726
4727 /* To avoid upsetting the power well on haswell only disable the pfit if
4728 * it's in use. The hw state code will make sure we get this right. */
4729 if (crtc->config->pch_pfit.enabled) {
4730 I915_WRITE(PF_CTL(pipe), 0);
4731 I915_WRITE(PF_WIN_POS(pipe), 0);
4732 I915_WRITE(PF_WIN_SZ(pipe), 0);
4733 }
4734 }
4735
4736 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4737 {
4738 struct drm_device *dev = crtc->dev;
4739 struct drm_i915_private *dev_priv = dev->dev_private;
4740 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4741 struct intel_encoder *encoder;
4742 int pipe = intel_crtc->pipe;
4743 u32 reg, temp;
4744
4745 if (!intel_crtc->active)
4746 return;
4747
4748 intel_crtc_disable_planes(crtc);
4749
4750 for_each_encoder_on_crtc(dev, crtc, encoder)
4751 encoder->disable(encoder);
4752
4753 drm_crtc_vblank_off(crtc);
4754 assert_vblank_disabled(crtc);
4755
4756 if (intel_crtc->config->has_pch_encoder)
4757 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4758
4759 intel_disable_pipe(intel_crtc);
4760
4761 ironlake_pfit_disable(intel_crtc);
4762
4763 for_each_encoder_on_crtc(dev, crtc, encoder)
4764 if (encoder->post_disable)
4765 encoder->post_disable(encoder);
4766
4767 if (intel_crtc->config->has_pch_encoder) {
4768 ironlake_fdi_disable(crtc);
4769
4770 ironlake_disable_pch_transcoder(dev_priv, pipe);
4771
4772 if (HAS_PCH_CPT(dev)) {
4773 /* disable TRANS_DP_CTL */
4774 reg = TRANS_DP_CTL(pipe);
4775 temp = I915_READ(reg);
4776 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4777 TRANS_DP_PORT_SEL_MASK);
4778 temp |= TRANS_DP_PORT_SEL_NONE;
4779 I915_WRITE(reg, temp);
4780
4781 /* disable DPLL_SEL */
4782 temp = I915_READ(PCH_DPLL_SEL);
4783 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4784 I915_WRITE(PCH_DPLL_SEL, temp);
4785 }
4786
4787 /* disable PCH DPLL */
4788 intel_disable_shared_dpll(intel_crtc);
4789
4790 ironlake_fdi_pll_disable(intel_crtc);
4791 }
4792
4793 intel_crtc->active = false;
4794 intel_update_watermarks(crtc);
4795
4796 mutex_lock(&dev->struct_mutex);
4797 intel_fbc_update(dev);
4798 mutex_unlock(&dev->struct_mutex);
4799 }
4800
4801 static void haswell_crtc_disable(struct drm_crtc *crtc)
4802 {
4803 struct drm_device *dev = crtc->dev;
4804 struct drm_i915_private *dev_priv = dev->dev_private;
4805 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4806 struct intel_encoder *encoder;
4807 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4808
4809 if (!intel_crtc->active)
4810 return;
4811
4812 intel_crtc_disable_planes(crtc);
4813
4814 for_each_encoder_on_crtc(dev, crtc, encoder) {
4815 intel_opregion_notify_encoder(encoder, false);
4816 encoder->disable(encoder);
4817 }
4818
4819 drm_crtc_vblank_off(crtc);
4820 assert_vblank_disabled(crtc);
4821
4822 if (intel_crtc->config->has_pch_encoder)
4823 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4824 false);
4825 intel_disable_pipe(intel_crtc);
4826
4827 if (intel_crtc->config->dp_encoder_is_mst)
4828 intel_ddi_set_vc_payload_alloc(crtc, false);
4829
4830 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4831
4832 if (IS_SKYLAKE(dev))
4833 skylake_pfit_disable(intel_crtc);
4834 else
4835 ironlake_pfit_disable(intel_crtc);
4836
4837 intel_ddi_disable_pipe_clock(intel_crtc);
4838
4839 if (intel_crtc->config->has_pch_encoder) {
4840 lpt_disable_pch_transcoder(dev_priv);
4841 intel_ddi_fdi_disable(crtc);
4842 }
4843
4844 for_each_encoder_on_crtc(dev, crtc, encoder)
4845 if (encoder->post_disable)
4846 encoder->post_disable(encoder);
4847
4848 intel_crtc->active = false;
4849 intel_update_watermarks(crtc);
4850
4851 mutex_lock(&dev->struct_mutex);
4852 intel_fbc_update(dev);
4853 mutex_unlock(&dev->struct_mutex);
4854
4855 if (intel_crtc_to_shared_dpll(intel_crtc))
4856 intel_disable_shared_dpll(intel_crtc);
4857 }
4858
4859 static void ironlake_crtc_off(struct drm_crtc *crtc)
4860 {
4861 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4862 intel_put_shared_dpll(intel_crtc);
4863 }
4864
4865
4866 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4867 {
4868 struct drm_device *dev = crtc->base.dev;
4869 struct drm_i915_private *dev_priv = dev->dev_private;
4870 struct intel_crtc_state *pipe_config = crtc->config;
4871
4872 if (!pipe_config->gmch_pfit.control)
4873 return;
4874
4875 /*
4876 * The panel fitter should only be adjusted whilst the pipe is disabled,
4877 * according to register description and PRM.
4878 */
4879 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4880 assert_pipe_disabled(dev_priv, crtc->pipe);
4881
4882 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4883 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4884
4885 /* Border color in case we don't scale up to the full screen. Black by
4886 * default, change to something else for debugging. */
4887 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4888 }
4889
4890 static enum intel_display_power_domain port_to_power_domain(enum port port)
4891 {
4892 switch (port) {
4893 case PORT_A:
4894 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4895 case PORT_B:
4896 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4897 case PORT_C:
4898 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4899 case PORT_D:
4900 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4901 default:
4902 WARN_ON_ONCE(1);
4903 return POWER_DOMAIN_PORT_OTHER;
4904 }
4905 }
4906
4907 #define for_each_power_domain(domain, mask) \
4908 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4909 if ((1 << (domain)) & (mask))
4910
4911 enum intel_display_power_domain
4912 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4913 {
4914 struct drm_device *dev = intel_encoder->base.dev;
4915 struct intel_digital_port *intel_dig_port;
4916
4917 switch (intel_encoder->type) {
4918 case INTEL_OUTPUT_UNKNOWN:
4919 /* Only DDI platforms should ever use this output type */
4920 WARN_ON_ONCE(!HAS_DDI(dev));
4921 case INTEL_OUTPUT_DISPLAYPORT:
4922 case INTEL_OUTPUT_HDMI:
4923 case INTEL_OUTPUT_EDP:
4924 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4925 return port_to_power_domain(intel_dig_port->port);
4926 case INTEL_OUTPUT_DP_MST:
4927 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4928 return port_to_power_domain(intel_dig_port->port);
4929 case INTEL_OUTPUT_ANALOG:
4930 return POWER_DOMAIN_PORT_CRT;
4931 case INTEL_OUTPUT_DSI:
4932 return POWER_DOMAIN_PORT_DSI;
4933 default:
4934 return POWER_DOMAIN_PORT_OTHER;
4935 }
4936 }
4937
4938 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4939 {
4940 struct drm_device *dev = crtc->dev;
4941 struct intel_encoder *intel_encoder;
4942 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4943 enum pipe pipe = intel_crtc->pipe;
4944 unsigned long mask;
4945 enum transcoder transcoder;
4946
4947 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4948
4949 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4950 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4951 if (intel_crtc->config->pch_pfit.enabled ||
4952 intel_crtc->config->pch_pfit.force_thru)
4953 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4954
4955 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4956 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4957
4958 return mask;
4959 }
4960
4961 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
4962 {
4963 struct drm_device *dev = state->dev;
4964 struct drm_i915_private *dev_priv = dev->dev_private;
4965 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4966 struct intel_crtc *crtc;
4967
4968 /*
4969 * First get all needed power domains, then put all unneeded, to avoid
4970 * any unnecessary toggling of the power wells.
4971 */
4972 for_each_intel_crtc(dev, crtc) {
4973 enum intel_display_power_domain domain;
4974
4975 if (!crtc->base.state->enable)
4976 continue;
4977
4978 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4979
4980 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4981 intel_display_power_get(dev_priv, domain);
4982 }
4983
4984 if (dev_priv->display.modeset_global_resources)
4985 dev_priv->display.modeset_global_resources(state);
4986
4987 for_each_intel_crtc(dev, crtc) {
4988 enum intel_display_power_domain domain;
4989
4990 for_each_power_domain(domain, crtc->enabled_power_domains)
4991 intel_display_power_put(dev_priv, domain);
4992
4993 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4994 }
4995
4996 intel_display_set_init_power(dev_priv, false);
4997 }
4998
4999 /* returns HPLL frequency in kHz */
5000 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
5001 {
5002 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
5003
5004 /* Obtain SKU information */
5005 mutex_lock(&dev_priv->dpio_lock);
5006 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5007 CCK_FUSE_HPLL_FREQ_MASK;
5008 mutex_unlock(&dev_priv->dpio_lock);
5009
5010 return vco_freq[hpll_freq] * 1000;
5011 }
5012
5013 static void vlv_update_cdclk(struct drm_device *dev)
5014 {
5015 struct drm_i915_private *dev_priv = dev->dev_private;
5016
5017 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5018 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5019 dev_priv->vlv_cdclk_freq);
5020
5021 /*
5022 * Program the gmbus_freq based on the cdclk frequency.
5023 * BSpec erroneously claims we should aim for 4MHz, but
5024 * in fact 1MHz is the correct frequency.
5025 */
5026 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
5027 }
5028
5029 /* Adjust CDclk dividers to allow high res or save power if possible */
5030 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5031 {
5032 struct drm_i915_private *dev_priv = dev->dev_private;
5033 u32 val, cmd;
5034
5035 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
5036
5037 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5038 cmd = 2;
5039 else if (cdclk == 266667)
5040 cmd = 1;
5041 else
5042 cmd = 0;
5043
5044 mutex_lock(&dev_priv->rps.hw_lock);
5045 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5046 val &= ~DSPFREQGUAR_MASK;
5047 val |= (cmd << DSPFREQGUAR_SHIFT);
5048 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5049 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5050 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5051 50)) {
5052 DRM_ERROR("timed out waiting for CDclk change\n");
5053 }
5054 mutex_unlock(&dev_priv->rps.hw_lock);
5055
5056 if (cdclk == 400000) {
5057 u32 divider;
5058
5059 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5060
5061 mutex_lock(&dev_priv->dpio_lock);
5062 /* adjust cdclk divider */
5063 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5064 val &= ~DISPLAY_FREQUENCY_VALUES;
5065 val |= divider;
5066 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5067
5068 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5069 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5070 50))
5071 DRM_ERROR("timed out waiting for CDclk change\n");
5072 mutex_unlock(&dev_priv->dpio_lock);
5073 }
5074
5075 mutex_lock(&dev_priv->dpio_lock);
5076 /* adjust self-refresh exit latency value */
5077 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5078 val &= ~0x7f;
5079
5080 /*
5081 * For high bandwidth configs, we set a higher latency in the bunit
5082 * so that the core display fetch happens in time to avoid underruns.
5083 */
5084 if (cdclk == 400000)
5085 val |= 4500 / 250; /* 4.5 usec */
5086 else
5087 val |= 3000 / 250; /* 3.0 usec */
5088 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5089 mutex_unlock(&dev_priv->dpio_lock);
5090
5091 vlv_update_cdclk(dev);
5092 }
5093
5094 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5095 {
5096 struct drm_i915_private *dev_priv = dev->dev_private;
5097 u32 val, cmd;
5098
5099 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
5100
5101 switch (cdclk) {
5102 case 333333:
5103 case 320000:
5104 case 266667:
5105 case 200000:
5106 break;
5107 default:
5108 MISSING_CASE(cdclk);
5109 return;
5110 }
5111
5112 /*
5113 * Specs are full of misinformation, but testing on actual
5114 * hardware has shown that we just need to write the desired
5115 * CCK divider into the Punit register.
5116 */
5117 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5118
5119 mutex_lock(&dev_priv->rps.hw_lock);
5120 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5121 val &= ~DSPFREQGUAR_MASK_CHV;
5122 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5123 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5124 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5125 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5126 50)) {
5127 DRM_ERROR("timed out waiting for CDclk change\n");
5128 }
5129 mutex_unlock(&dev_priv->rps.hw_lock);
5130
5131 vlv_update_cdclk(dev);
5132 }
5133
5134 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5135 int max_pixclk)
5136 {
5137 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5138 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5139
5140 /*
5141 * Really only a few cases to deal with, as only 4 CDclks are supported:
5142 * 200MHz
5143 * 267MHz
5144 * 320/333MHz (depends on HPLL freq)
5145 * 400MHz (VLV only)
5146 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5147 * of the lower bin and adjust if needed.
5148 *
5149 * We seem to get an unstable or solid color picture at 200MHz.
5150 * Not sure what's wrong. For now use 200MHz only when all pipes
5151 * are off.
5152 */
5153 if (!IS_CHERRYVIEW(dev_priv) &&
5154 max_pixclk > freq_320*limit/100)
5155 return 400000;
5156 else if (max_pixclk > 266667*limit/100)
5157 return freq_320;
5158 else if (max_pixclk > 0)
5159 return 266667;
5160 else
5161 return 200000;
5162 }
5163
5164 /* compute the max pixel clock for new configuration */
5165 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
5166 {
5167 struct drm_device *dev = dev_priv->dev;
5168 struct intel_crtc *intel_crtc;
5169 int max_pixclk = 0;
5170
5171 for_each_intel_crtc(dev, intel_crtc) {
5172 if (intel_crtc->new_enabled)
5173 max_pixclk = max(max_pixclk,
5174 intel_crtc->new_config->base.adjusted_mode.crtc_clock);
5175 }
5176
5177 return max_pixclk;
5178 }
5179
5180 static void valleyview_modeset_global_pipes(struct drm_device *dev,
5181 unsigned *prepare_pipes)
5182 {
5183 struct drm_i915_private *dev_priv = dev->dev_private;
5184 struct intel_crtc *intel_crtc;
5185 int max_pixclk = intel_mode_max_pixclk(dev_priv);
5186
5187 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
5188 dev_priv->vlv_cdclk_freq)
5189 return;
5190
5191 /* disable/enable all currently active pipes while we change cdclk */
5192 for_each_intel_crtc(dev, intel_crtc)
5193 if (intel_crtc->base.state->enable)
5194 *prepare_pipes |= (1 << intel_crtc->pipe);
5195 }
5196
5197 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5198 {
5199 unsigned int credits, default_credits;
5200
5201 if (IS_CHERRYVIEW(dev_priv))
5202 default_credits = PFI_CREDIT(12);
5203 else
5204 default_credits = PFI_CREDIT(8);
5205
5206 if (DIV_ROUND_CLOSEST(dev_priv->vlv_cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5207 /* CHV suggested value is 31 or 63 */
5208 if (IS_CHERRYVIEW(dev_priv))
5209 credits = PFI_CREDIT_31;
5210 else
5211 credits = PFI_CREDIT(15);
5212 } else {
5213 credits = default_credits;
5214 }
5215
5216 /*
5217 * WA - write default credits before re-programming
5218 * FIXME: should we also set the resend bit here?
5219 */
5220 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5221 default_credits);
5222
5223 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5224 credits | PFI_CREDIT_RESEND);
5225
5226 /*
5227 * FIXME is this guaranteed to clear
5228 * immediately or should we poll for it?
5229 */
5230 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5231 }
5232
5233 static void valleyview_modeset_global_resources(struct drm_atomic_state *state)
5234 {
5235 struct drm_device *dev = state->dev;
5236 struct drm_i915_private *dev_priv = dev->dev_private;
5237 int max_pixclk = intel_mode_max_pixclk(dev_priv);
5238 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5239
5240 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
5241 /*
5242 * FIXME: We can end up here with all power domains off, yet
5243 * with a CDCLK frequency other than the minimum. To account
5244 * for this take the PIPE-A power domain, which covers the HW
5245 * blocks needed for the following programming. This can be
5246 * removed once it's guaranteed that we get here either with
5247 * the minimum CDCLK set, or the required power domains
5248 * enabled.
5249 */
5250 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5251
5252 if (IS_CHERRYVIEW(dev))
5253 cherryview_set_cdclk(dev, req_cdclk);
5254 else
5255 valleyview_set_cdclk(dev, req_cdclk);
5256
5257 vlv_program_pfi_credits(dev_priv);
5258
5259 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5260 }
5261 }
5262
5263 static void valleyview_crtc_enable(struct drm_crtc *crtc)
5264 {
5265 struct drm_device *dev = crtc->dev;
5266 struct drm_i915_private *dev_priv = to_i915(dev);
5267 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5268 struct intel_encoder *encoder;
5269 int pipe = intel_crtc->pipe;
5270 bool is_dsi;
5271
5272 WARN_ON(!crtc->state->enable);
5273
5274 if (intel_crtc->active)
5275 return;
5276
5277 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5278
5279 if (!is_dsi) {
5280 if (IS_CHERRYVIEW(dev))
5281 chv_prepare_pll(intel_crtc, intel_crtc->config);
5282 else
5283 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5284 }
5285
5286 if (intel_crtc->config->has_dp_encoder)
5287 intel_dp_set_m_n(intel_crtc, M1_N1);
5288
5289 intel_set_pipe_timings(intel_crtc);
5290
5291 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5292 struct drm_i915_private *dev_priv = dev->dev_private;
5293
5294 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5295 I915_WRITE(CHV_CANVAS(pipe), 0);
5296 }
5297
5298 i9xx_set_pipeconf(intel_crtc);
5299
5300 intel_crtc->active = true;
5301
5302 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5303
5304 for_each_encoder_on_crtc(dev, crtc, encoder)
5305 if (encoder->pre_pll_enable)
5306 encoder->pre_pll_enable(encoder);
5307
5308 if (!is_dsi) {
5309 if (IS_CHERRYVIEW(dev))
5310 chv_enable_pll(intel_crtc, intel_crtc->config);
5311 else
5312 vlv_enable_pll(intel_crtc, intel_crtc->config);
5313 }
5314
5315 for_each_encoder_on_crtc(dev, crtc, encoder)
5316 if (encoder->pre_enable)
5317 encoder->pre_enable(encoder);
5318
5319 i9xx_pfit_enable(intel_crtc);
5320
5321 intel_crtc_load_lut(crtc);
5322
5323 intel_update_watermarks(crtc);
5324 intel_enable_pipe(intel_crtc);
5325
5326 assert_vblank_disabled(crtc);
5327 drm_crtc_vblank_on(crtc);
5328
5329 for_each_encoder_on_crtc(dev, crtc, encoder)
5330 encoder->enable(encoder);
5331
5332 intel_crtc_enable_planes(crtc);
5333
5334 /* Underruns don't raise interrupts, so check manually. */
5335 i9xx_check_fifo_underruns(dev_priv);
5336 }
5337
5338 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5339 {
5340 struct drm_device *dev = crtc->base.dev;
5341 struct drm_i915_private *dev_priv = dev->dev_private;
5342
5343 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5344 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5345 }
5346
5347 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5348 {
5349 struct drm_device *dev = crtc->dev;
5350 struct drm_i915_private *dev_priv = to_i915(dev);
5351 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5352 struct intel_encoder *encoder;
5353 int pipe = intel_crtc->pipe;
5354
5355 WARN_ON(!crtc->state->enable);
5356
5357 if (intel_crtc->active)
5358 return;
5359
5360 i9xx_set_pll_dividers(intel_crtc);
5361
5362 if (intel_crtc->config->has_dp_encoder)
5363 intel_dp_set_m_n(intel_crtc, M1_N1);
5364
5365 intel_set_pipe_timings(intel_crtc);
5366
5367 i9xx_set_pipeconf(intel_crtc);
5368
5369 intel_crtc->active = true;
5370
5371 if (!IS_GEN2(dev))
5372 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5373
5374 for_each_encoder_on_crtc(dev, crtc, encoder)
5375 if (encoder->pre_enable)
5376 encoder->pre_enable(encoder);
5377
5378 i9xx_enable_pll(intel_crtc);
5379
5380 i9xx_pfit_enable(intel_crtc);
5381
5382 intel_crtc_load_lut(crtc);
5383
5384 intel_update_watermarks(crtc);
5385 intel_enable_pipe(intel_crtc);
5386
5387 assert_vblank_disabled(crtc);
5388 drm_crtc_vblank_on(crtc);
5389
5390 for_each_encoder_on_crtc(dev, crtc, encoder)
5391 encoder->enable(encoder);
5392
5393 intel_crtc_enable_planes(crtc);
5394
5395 /*
5396 * Gen2 reports pipe underruns whenever all planes are disabled.
5397 * So don't enable underrun reporting before at least some planes
5398 * are enabled.
5399 * FIXME: Need to fix the logic to work when we turn off all planes
5400 * but leave the pipe running.
5401 */
5402 if (IS_GEN2(dev))
5403 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5404
5405 /* Underruns don't raise interrupts, so check manually. */
5406 i9xx_check_fifo_underruns(dev_priv);
5407 }
5408
5409 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5410 {
5411 struct drm_device *dev = crtc->base.dev;
5412 struct drm_i915_private *dev_priv = dev->dev_private;
5413
5414 if (!crtc->config->gmch_pfit.control)
5415 return;
5416
5417 assert_pipe_disabled(dev_priv, crtc->pipe);
5418
5419 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5420 I915_READ(PFIT_CONTROL));
5421 I915_WRITE(PFIT_CONTROL, 0);
5422 }
5423
5424 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5425 {
5426 struct drm_device *dev = crtc->dev;
5427 struct drm_i915_private *dev_priv = dev->dev_private;
5428 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5429 struct intel_encoder *encoder;
5430 int pipe = intel_crtc->pipe;
5431
5432 if (!intel_crtc->active)
5433 return;
5434
5435 /*
5436 * Gen2 reports pipe underruns whenever all planes are disabled.
5437 * So diasble underrun reporting before all the planes get disabled.
5438 * FIXME: Need to fix the logic to work when we turn off all planes
5439 * but leave the pipe running.
5440 */
5441 if (IS_GEN2(dev))
5442 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5443
5444 /*
5445 * Vblank time updates from the shadow to live plane control register
5446 * are blocked if the memory self-refresh mode is active at that
5447 * moment. So to make sure the plane gets truly disabled, disable
5448 * first the self-refresh mode. The self-refresh enable bit in turn
5449 * will be checked/applied by the HW only at the next frame start
5450 * event which is after the vblank start event, so we need to have a
5451 * wait-for-vblank between disabling the plane and the pipe.
5452 */
5453 intel_set_memory_cxsr(dev_priv, false);
5454 intel_crtc_disable_planes(crtc);
5455
5456 /*
5457 * On gen2 planes are double buffered but the pipe isn't, so we must
5458 * wait for planes to fully turn off before disabling the pipe.
5459 * We also need to wait on all gmch platforms because of the
5460 * self-refresh mode constraint explained above.
5461 */
5462 intel_wait_for_vblank(dev, pipe);
5463
5464 for_each_encoder_on_crtc(dev, crtc, encoder)
5465 encoder->disable(encoder);
5466
5467 drm_crtc_vblank_off(crtc);
5468 assert_vblank_disabled(crtc);
5469
5470 intel_disable_pipe(intel_crtc);
5471
5472 i9xx_pfit_disable(intel_crtc);
5473
5474 for_each_encoder_on_crtc(dev, crtc, encoder)
5475 if (encoder->post_disable)
5476 encoder->post_disable(encoder);
5477
5478 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5479 if (IS_CHERRYVIEW(dev))
5480 chv_disable_pll(dev_priv, pipe);
5481 else if (IS_VALLEYVIEW(dev))
5482 vlv_disable_pll(dev_priv, pipe);
5483 else
5484 i9xx_disable_pll(intel_crtc);
5485 }
5486
5487 if (!IS_GEN2(dev))
5488 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5489
5490 intel_crtc->active = false;
5491 intel_update_watermarks(crtc);
5492
5493 mutex_lock(&dev->struct_mutex);
5494 intel_fbc_update(dev);
5495 mutex_unlock(&dev->struct_mutex);
5496 }
5497
5498 static void i9xx_crtc_off(struct drm_crtc *crtc)
5499 {
5500 }
5501
5502 /* Master function to enable/disable CRTC and corresponding power wells */
5503 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5504 {
5505 struct drm_device *dev = crtc->dev;
5506 struct drm_i915_private *dev_priv = dev->dev_private;
5507 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5508 enum intel_display_power_domain domain;
5509 unsigned long domains;
5510
5511 if (enable) {
5512 if (!intel_crtc->active) {
5513 domains = get_crtc_power_domains(crtc);
5514 for_each_power_domain(domain, domains)
5515 intel_display_power_get(dev_priv, domain);
5516 intel_crtc->enabled_power_domains = domains;
5517
5518 dev_priv->display.crtc_enable(crtc);
5519 }
5520 } else {
5521 if (intel_crtc->active) {
5522 dev_priv->display.crtc_disable(crtc);
5523
5524 domains = intel_crtc->enabled_power_domains;
5525 for_each_power_domain(domain, domains)
5526 intel_display_power_put(dev_priv, domain);
5527 intel_crtc->enabled_power_domains = 0;
5528 }
5529 }
5530 }
5531
5532 /**
5533 * Sets the power management mode of the pipe and plane.
5534 */
5535 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5536 {
5537 struct drm_device *dev = crtc->dev;
5538 struct intel_encoder *intel_encoder;
5539 bool enable = false;
5540
5541 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5542 enable |= intel_encoder->connectors_active;
5543
5544 intel_crtc_control(crtc, enable);
5545 }
5546
5547 static void intel_crtc_disable(struct drm_crtc *crtc)
5548 {
5549 struct drm_device *dev = crtc->dev;
5550 struct drm_connector *connector;
5551 struct drm_i915_private *dev_priv = dev->dev_private;
5552
5553 /* crtc should still be enabled when we disable it. */
5554 WARN_ON(!crtc->state->enable);
5555
5556 dev_priv->display.crtc_disable(crtc);
5557 dev_priv->display.off(crtc);
5558
5559 crtc->primary->funcs->disable_plane(crtc->primary);
5560
5561 /* Update computed state. */
5562 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5563 if (!connector->encoder || !connector->encoder->crtc)
5564 continue;
5565
5566 if (connector->encoder->crtc != crtc)
5567 continue;
5568
5569 connector->dpms = DRM_MODE_DPMS_OFF;
5570 to_intel_encoder(connector->encoder)->connectors_active = false;
5571 }
5572 }
5573
5574 void intel_encoder_destroy(struct drm_encoder *encoder)
5575 {
5576 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5577
5578 drm_encoder_cleanup(encoder);
5579 kfree(intel_encoder);
5580 }
5581
5582 /* Simple dpms helper for encoders with just one connector, no cloning and only
5583 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5584 * state of the entire output pipe. */
5585 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5586 {
5587 if (mode == DRM_MODE_DPMS_ON) {
5588 encoder->connectors_active = true;
5589
5590 intel_crtc_update_dpms(encoder->base.crtc);
5591 } else {
5592 encoder->connectors_active = false;
5593
5594 intel_crtc_update_dpms(encoder->base.crtc);
5595 }
5596 }
5597
5598 /* Cross check the actual hw state with our own modeset state tracking (and it's
5599 * internal consistency). */
5600 static void intel_connector_check_state(struct intel_connector *connector)
5601 {
5602 if (connector->get_hw_state(connector)) {
5603 struct intel_encoder *encoder = connector->encoder;
5604 struct drm_crtc *crtc;
5605 bool encoder_enabled;
5606 enum pipe pipe;
5607
5608 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5609 connector->base.base.id,
5610 connector->base.name);
5611
5612 /* there is no real hw state for MST connectors */
5613 if (connector->mst_port)
5614 return;
5615
5616 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5617 "wrong connector dpms state\n");
5618 I915_STATE_WARN(connector->base.encoder != &encoder->base,
5619 "active connector not linked to encoder\n");
5620
5621 if (encoder) {
5622 I915_STATE_WARN(!encoder->connectors_active,
5623 "encoder->connectors_active not set\n");
5624
5625 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5626 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
5627 if (I915_STATE_WARN_ON(!encoder->base.crtc))
5628 return;
5629
5630 crtc = encoder->base.crtc;
5631
5632 I915_STATE_WARN(!crtc->state->enable,
5633 "crtc not enabled\n");
5634 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5635 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
5636 "encoder active on the wrong pipe\n");
5637 }
5638 }
5639 }
5640
5641 /* Even simpler default implementation, if there's really no special case to
5642 * consider. */
5643 void intel_connector_dpms(struct drm_connector *connector, int mode)
5644 {
5645 /* All the simple cases only support two dpms states. */
5646 if (mode != DRM_MODE_DPMS_ON)
5647 mode = DRM_MODE_DPMS_OFF;
5648
5649 if (mode == connector->dpms)
5650 return;
5651
5652 connector->dpms = mode;
5653
5654 /* Only need to change hw state when actually enabled */
5655 if (connector->encoder)
5656 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5657
5658 intel_modeset_check_state(connector->dev);
5659 }
5660
5661 /* Simple connector->get_hw_state implementation for encoders that support only
5662 * one connector and no cloning and hence the encoder state determines the state
5663 * of the connector. */
5664 bool intel_connector_get_hw_state(struct intel_connector *connector)
5665 {
5666 enum pipe pipe = 0;
5667 struct intel_encoder *encoder = connector->encoder;
5668
5669 return encoder->get_hw_state(encoder, &pipe);
5670 }
5671
5672 static int pipe_required_fdi_lanes(struct drm_device *dev, enum pipe pipe)
5673 {
5674 struct intel_crtc *crtc =
5675 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5676
5677 if (crtc->base.state->enable &&
5678 crtc->config->has_pch_encoder)
5679 return crtc->config->fdi_lanes;
5680
5681 return 0;
5682 }
5683
5684 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5685 struct intel_crtc_state *pipe_config)
5686 {
5687 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5688 pipe_name(pipe), pipe_config->fdi_lanes);
5689 if (pipe_config->fdi_lanes > 4) {
5690 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5691 pipe_name(pipe), pipe_config->fdi_lanes);
5692 return false;
5693 }
5694
5695 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5696 if (pipe_config->fdi_lanes > 2) {
5697 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5698 pipe_config->fdi_lanes);
5699 return false;
5700 } else {
5701 return true;
5702 }
5703 }
5704
5705 if (INTEL_INFO(dev)->num_pipes == 2)
5706 return true;
5707
5708 /* Ivybridge 3 pipe is really complicated */
5709 switch (pipe) {
5710 case PIPE_A:
5711 return true;
5712 case PIPE_B:
5713 if (pipe_config->fdi_lanes > 2 &&
5714 pipe_required_fdi_lanes(dev, PIPE_C) > 0) {
5715 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5716 pipe_name(pipe), pipe_config->fdi_lanes);
5717 return false;
5718 }
5719 return true;
5720 case PIPE_C:
5721 if (pipe_config->fdi_lanes > 2) {
5722 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
5723 pipe_name(pipe), pipe_config->fdi_lanes);
5724 return false;
5725 }
5726 if (pipe_required_fdi_lanes(dev, PIPE_B) > 2) {
5727 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5728 return false;
5729 }
5730 return true;
5731 default:
5732 BUG();
5733 }
5734 }
5735
5736 #define RETRY 1
5737 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5738 struct intel_crtc_state *pipe_config)
5739 {
5740 struct drm_device *dev = intel_crtc->base.dev;
5741 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5742 int lane, link_bw, fdi_dotclock;
5743 bool setup_ok, needs_recompute = false;
5744
5745 retry:
5746 /* FDI is a binary signal running at ~2.7GHz, encoding
5747 * each output octet as 10 bits. The actual frequency
5748 * is stored as a divider into a 100MHz clock, and the
5749 * mode pixel clock is stored in units of 1KHz.
5750 * Hence the bw of each lane in terms of the mode signal
5751 * is:
5752 */
5753 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5754
5755 fdi_dotclock = adjusted_mode->crtc_clock;
5756
5757 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5758 pipe_config->pipe_bpp);
5759
5760 pipe_config->fdi_lanes = lane;
5761
5762 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5763 link_bw, &pipe_config->fdi_m_n);
5764
5765 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5766 intel_crtc->pipe, pipe_config);
5767 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5768 pipe_config->pipe_bpp -= 2*3;
5769 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5770 pipe_config->pipe_bpp);
5771 needs_recompute = true;
5772 pipe_config->bw_constrained = true;
5773
5774 goto retry;
5775 }
5776
5777 if (needs_recompute)
5778 return RETRY;
5779
5780 return setup_ok ? 0 : -EINVAL;
5781 }
5782
5783 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5784 struct intel_crtc_state *pipe_config)
5785 {
5786 pipe_config->ips_enabled = i915.enable_ips &&
5787 hsw_crtc_supports_ips(crtc) &&
5788 pipe_config->pipe_bpp <= 24;
5789 }
5790
5791 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5792 struct intel_crtc_state *pipe_config)
5793 {
5794 struct drm_device *dev = crtc->base.dev;
5795 struct drm_i915_private *dev_priv = dev->dev_private;
5796 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5797
5798 /* FIXME should check pixel clock limits on all platforms */
5799 if (INTEL_INFO(dev)->gen < 4) {
5800 int clock_limit =
5801 dev_priv->display.get_display_clock_speed(dev);
5802
5803 /*
5804 * Enable pixel doubling when the dot clock
5805 * is > 90% of the (display) core speed.
5806 *
5807 * GDG double wide on either pipe,
5808 * otherwise pipe A only.
5809 */
5810 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5811 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5812 clock_limit *= 2;
5813 pipe_config->double_wide = true;
5814 }
5815
5816 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5817 return -EINVAL;
5818 }
5819
5820 /*
5821 * Pipe horizontal size must be even in:
5822 * - DVO ganged mode
5823 * - LVDS dual channel mode
5824 * - Double wide pipe
5825 */
5826 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
5827 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5828 pipe_config->pipe_src_w &= ~1;
5829
5830 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5831 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5832 */
5833 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5834 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5835 return -EINVAL;
5836
5837 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5838 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5839 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5840 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5841 * for lvds. */
5842 pipe_config->pipe_bpp = 8*3;
5843 }
5844
5845 if (HAS_IPS(dev))
5846 hsw_compute_ips_config(crtc, pipe_config);
5847
5848 if (pipe_config->has_pch_encoder)
5849 return ironlake_fdi_compute_config(crtc, pipe_config);
5850
5851 return 0;
5852 }
5853
5854 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5855 {
5856 struct drm_i915_private *dev_priv = dev->dev_private;
5857 u32 val;
5858 int divider;
5859
5860 if (dev_priv->hpll_freq == 0)
5861 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5862
5863 mutex_lock(&dev_priv->dpio_lock);
5864 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5865 mutex_unlock(&dev_priv->dpio_lock);
5866
5867 divider = val & DISPLAY_FREQUENCY_VALUES;
5868
5869 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5870 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5871 "cdclk change in progress\n");
5872
5873 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
5874 }
5875
5876 static int i945_get_display_clock_speed(struct drm_device *dev)
5877 {
5878 return 400000;
5879 }
5880
5881 static int i915_get_display_clock_speed(struct drm_device *dev)
5882 {
5883 return 333000;
5884 }
5885
5886 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5887 {
5888 return 200000;
5889 }
5890
5891 static int pnv_get_display_clock_speed(struct drm_device *dev)
5892 {
5893 u16 gcfgc = 0;
5894
5895 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5896
5897 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5898 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5899 return 267000;
5900 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5901 return 333000;
5902 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5903 return 444000;
5904 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5905 return 200000;
5906 default:
5907 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5908 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5909 return 133000;
5910 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5911 return 167000;
5912 }
5913 }
5914
5915 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5916 {
5917 u16 gcfgc = 0;
5918
5919 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5920
5921 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5922 return 133000;
5923 else {
5924 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5925 case GC_DISPLAY_CLOCK_333_MHZ:
5926 return 333000;
5927 default:
5928 case GC_DISPLAY_CLOCK_190_200_MHZ:
5929 return 190000;
5930 }
5931 }
5932 }
5933
5934 static int i865_get_display_clock_speed(struct drm_device *dev)
5935 {
5936 return 266000;
5937 }
5938
5939 static int i855_get_display_clock_speed(struct drm_device *dev)
5940 {
5941 u16 hpllcc = 0;
5942 /* Assume that the hardware is in the high speed state. This
5943 * should be the default.
5944 */
5945 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5946 case GC_CLOCK_133_200:
5947 case GC_CLOCK_100_200:
5948 return 200000;
5949 case GC_CLOCK_166_250:
5950 return 250000;
5951 case GC_CLOCK_100_133:
5952 return 133000;
5953 }
5954
5955 /* Shouldn't happen */
5956 return 0;
5957 }
5958
5959 static int i830_get_display_clock_speed(struct drm_device *dev)
5960 {
5961 return 133000;
5962 }
5963
5964 static void
5965 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5966 {
5967 while (*num > DATA_LINK_M_N_MASK ||
5968 *den > DATA_LINK_M_N_MASK) {
5969 *num >>= 1;
5970 *den >>= 1;
5971 }
5972 }
5973
5974 static void compute_m_n(unsigned int m, unsigned int n,
5975 uint32_t *ret_m, uint32_t *ret_n)
5976 {
5977 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5978 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5979 intel_reduce_m_n_ratio(ret_m, ret_n);
5980 }
5981
5982 void
5983 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5984 int pixel_clock, int link_clock,
5985 struct intel_link_m_n *m_n)
5986 {
5987 m_n->tu = 64;
5988
5989 compute_m_n(bits_per_pixel * pixel_clock,
5990 link_clock * nlanes * 8,
5991 &m_n->gmch_m, &m_n->gmch_n);
5992
5993 compute_m_n(pixel_clock, link_clock,
5994 &m_n->link_m, &m_n->link_n);
5995 }
5996
5997 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5998 {
5999 if (i915.panel_use_ssc >= 0)
6000 return i915.panel_use_ssc != 0;
6001 return dev_priv->vbt.lvds_use_ssc
6002 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6003 }
6004
6005 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
6006 int num_connectors)
6007 {
6008 struct drm_device *dev = crtc_state->base.crtc->dev;
6009 struct drm_i915_private *dev_priv = dev->dev_private;
6010 int refclk;
6011
6012 WARN_ON(!crtc_state->base.state);
6013
6014 if (IS_VALLEYVIEW(dev)) {
6015 refclk = 100000;
6016 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6017 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6018 refclk = dev_priv->vbt.lvds_ssc_freq;
6019 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
6020 } else if (!IS_GEN2(dev)) {
6021 refclk = 96000;
6022 } else {
6023 refclk = 48000;
6024 }
6025
6026 return refclk;
6027 }
6028
6029 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6030 {
6031 return (1 << dpll->n) << 16 | dpll->m2;
6032 }
6033
6034 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6035 {
6036 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6037 }
6038
6039 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6040 struct intel_crtc_state *crtc_state,
6041 intel_clock_t *reduced_clock)
6042 {
6043 struct drm_device *dev = crtc->base.dev;
6044 u32 fp, fp2 = 0;
6045
6046 if (IS_PINEVIEW(dev)) {
6047 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6048 if (reduced_clock)
6049 fp2 = pnv_dpll_compute_fp(reduced_clock);
6050 } else {
6051 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6052 if (reduced_clock)
6053 fp2 = i9xx_dpll_compute_fp(reduced_clock);
6054 }
6055
6056 crtc_state->dpll_hw_state.fp0 = fp;
6057
6058 crtc->lowfreq_avail = false;
6059 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6060 reduced_clock) {
6061 crtc_state->dpll_hw_state.fp1 = fp2;
6062 crtc->lowfreq_avail = true;
6063 } else {
6064 crtc_state->dpll_hw_state.fp1 = fp;
6065 }
6066 }
6067
6068 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6069 pipe)
6070 {
6071 u32 reg_val;
6072
6073 /*
6074 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6075 * and set it to a reasonable value instead.
6076 */
6077 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6078 reg_val &= 0xffffff00;
6079 reg_val |= 0x00000030;
6080 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6081
6082 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6083 reg_val &= 0x8cffffff;
6084 reg_val = 0x8c000000;
6085 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6086
6087 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6088 reg_val &= 0xffffff00;
6089 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6090
6091 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6092 reg_val &= 0x00ffffff;
6093 reg_val |= 0xb0000000;
6094 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6095 }
6096
6097 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6098 struct intel_link_m_n *m_n)
6099 {
6100 struct drm_device *dev = crtc->base.dev;
6101 struct drm_i915_private *dev_priv = dev->dev_private;
6102 int pipe = crtc->pipe;
6103
6104 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6105 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6106 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6107 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6108 }
6109
6110 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6111 struct intel_link_m_n *m_n,
6112 struct intel_link_m_n *m2_n2)
6113 {
6114 struct drm_device *dev = crtc->base.dev;
6115 struct drm_i915_private *dev_priv = dev->dev_private;
6116 int pipe = crtc->pipe;
6117 enum transcoder transcoder = crtc->config->cpu_transcoder;
6118
6119 if (INTEL_INFO(dev)->gen >= 5) {
6120 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6121 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6122 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6123 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6124 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6125 * for gen < 8) and if DRRS is supported (to make sure the
6126 * registers are not unnecessarily accessed).
6127 */
6128 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6129 crtc->config->has_drrs) {
6130 I915_WRITE(PIPE_DATA_M2(transcoder),
6131 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6132 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6133 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6134 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6135 }
6136 } else {
6137 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6138 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6139 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6140 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6141 }
6142 }
6143
6144 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6145 {
6146 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6147
6148 if (m_n == M1_N1) {
6149 dp_m_n = &crtc->config->dp_m_n;
6150 dp_m2_n2 = &crtc->config->dp_m2_n2;
6151 } else if (m_n == M2_N2) {
6152
6153 /*
6154 * M2_N2 registers are not supported. Hence m2_n2 divider value
6155 * needs to be programmed into M1_N1.
6156 */
6157 dp_m_n = &crtc->config->dp_m2_n2;
6158 } else {
6159 DRM_ERROR("Unsupported divider value\n");
6160 return;
6161 }
6162
6163 if (crtc->config->has_pch_encoder)
6164 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6165 else
6166 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6167 }
6168
6169 static void vlv_update_pll(struct intel_crtc *crtc,
6170 struct intel_crtc_state *pipe_config)
6171 {
6172 u32 dpll, dpll_md;
6173
6174 /*
6175 * Enable DPIO clock input. We should never disable the reference
6176 * clock for pipe B, since VGA hotplug / manual detection depends
6177 * on it.
6178 */
6179 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
6180 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
6181 /* We should never disable this, set it here for state tracking */
6182 if (crtc->pipe == PIPE_B)
6183 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6184 dpll |= DPLL_VCO_ENABLE;
6185 pipe_config->dpll_hw_state.dpll = dpll;
6186
6187 dpll_md = (pipe_config->pixel_multiplier - 1)
6188 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6189 pipe_config->dpll_hw_state.dpll_md = dpll_md;
6190 }
6191
6192 static void vlv_prepare_pll(struct intel_crtc *crtc,
6193 const struct intel_crtc_state *pipe_config)
6194 {
6195 struct drm_device *dev = crtc->base.dev;
6196 struct drm_i915_private *dev_priv = dev->dev_private;
6197 int pipe = crtc->pipe;
6198 u32 mdiv;
6199 u32 bestn, bestm1, bestm2, bestp1, bestp2;
6200 u32 coreclk, reg_val;
6201
6202 mutex_lock(&dev_priv->dpio_lock);
6203
6204 bestn = pipe_config->dpll.n;
6205 bestm1 = pipe_config->dpll.m1;
6206 bestm2 = pipe_config->dpll.m2;
6207 bestp1 = pipe_config->dpll.p1;
6208 bestp2 = pipe_config->dpll.p2;
6209
6210 /* See eDP HDMI DPIO driver vbios notes doc */
6211
6212 /* PLL B needs special handling */
6213 if (pipe == PIPE_B)
6214 vlv_pllb_recal_opamp(dev_priv, pipe);
6215
6216 /* Set up Tx target for periodic Rcomp update */
6217 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6218
6219 /* Disable target IRef on PLL */
6220 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6221 reg_val &= 0x00ffffff;
6222 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6223
6224 /* Disable fast lock */
6225 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6226
6227 /* Set idtafcrecal before PLL is enabled */
6228 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6229 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6230 mdiv |= ((bestn << DPIO_N_SHIFT));
6231 mdiv |= (1 << DPIO_K_SHIFT);
6232
6233 /*
6234 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6235 * but we don't support that).
6236 * Note: don't use the DAC post divider as it seems unstable.
6237 */
6238 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6239 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6240
6241 mdiv |= DPIO_ENABLE_CALIBRATION;
6242 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6243
6244 /* Set HBR and RBR LPF coefficients */
6245 if (pipe_config->port_clock == 162000 ||
6246 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
6247 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
6248 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6249 0x009f0003);
6250 else
6251 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6252 0x00d0000f);
6253
6254 if (pipe_config->has_dp_encoder) {
6255 /* Use SSC source */
6256 if (pipe == PIPE_A)
6257 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6258 0x0df40000);
6259 else
6260 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6261 0x0df70000);
6262 } else { /* HDMI or VGA */
6263 /* Use bend source */
6264 if (pipe == PIPE_A)
6265 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6266 0x0df70000);
6267 else
6268 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6269 0x0df40000);
6270 }
6271
6272 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6273 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6274 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6275 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
6276 coreclk |= 0x01000000;
6277 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6278
6279 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6280 mutex_unlock(&dev_priv->dpio_lock);
6281 }
6282
6283 static void chv_update_pll(struct intel_crtc *crtc,
6284 struct intel_crtc_state *pipe_config)
6285 {
6286 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
6287 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6288 DPLL_VCO_ENABLE;
6289 if (crtc->pipe != PIPE_A)
6290 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6291
6292 pipe_config->dpll_hw_state.dpll_md =
6293 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6294 }
6295
6296 static void chv_prepare_pll(struct intel_crtc *crtc,
6297 const struct intel_crtc_state *pipe_config)
6298 {
6299 struct drm_device *dev = crtc->base.dev;
6300 struct drm_i915_private *dev_priv = dev->dev_private;
6301 int pipe = crtc->pipe;
6302 int dpll_reg = DPLL(crtc->pipe);
6303 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6304 u32 loopfilter, tribuf_calcntr;
6305 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6306 u32 dpio_val;
6307 int vco;
6308
6309 bestn = pipe_config->dpll.n;
6310 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6311 bestm1 = pipe_config->dpll.m1;
6312 bestm2 = pipe_config->dpll.m2 >> 22;
6313 bestp1 = pipe_config->dpll.p1;
6314 bestp2 = pipe_config->dpll.p2;
6315 vco = pipe_config->dpll.vco;
6316 dpio_val = 0;
6317 loopfilter = 0;
6318
6319 /*
6320 * Enable Refclk and SSC
6321 */
6322 I915_WRITE(dpll_reg,
6323 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6324
6325 mutex_lock(&dev_priv->dpio_lock);
6326
6327 /* p1 and p2 divider */
6328 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6329 5 << DPIO_CHV_S1_DIV_SHIFT |
6330 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6331 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6332 1 << DPIO_CHV_K_DIV_SHIFT);
6333
6334 /* Feedback post-divider - m2 */
6335 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6336
6337 /* Feedback refclk divider - n and m1 */
6338 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6339 DPIO_CHV_M1_DIV_BY_2 |
6340 1 << DPIO_CHV_N_DIV_SHIFT);
6341
6342 /* M2 fraction division */
6343 if (bestm2_frac)
6344 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6345
6346 /* M2 fraction division enable */
6347 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6348 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6349 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6350 if (bestm2_frac)
6351 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6352 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
6353
6354 /* Program digital lock detect threshold */
6355 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6356 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6357 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6358 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6359 if (!bestm2_frac)
6360 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6361 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6362
6363 /* Loop filter */
6364 if (vco == 5400000) {
6365 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6366 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6367 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6368 tribuf_calcntr = 0x9;
6369 } else if (vco <= 6200000) {
6370 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6371 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6372 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6373 tribuf_calcntr = 0x9;
6374 } else if (vco <= 6480000) {
6375 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6376 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6377 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6378 tribuf_calcntr = 0x8;
6379 } else {
6380 /* Not supported. Apply the same limits as in the max case */
6381 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6382 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6383 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6384 tribuf_calcntr = 0;
6385 }
6386 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6387
6388 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
6389 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6390 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6391 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6392
6393 /* AFC Recal */
6394 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6395 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6396 DPIO_AFC_RECAL);
6397
6398 mutex_unlock(&dev_priv->dpio_lock);
6399 }
6400
6401 /**
6402 * vlv_force_pll_on - forcibly enable just the PLL
6403 * @dev_priv: i915 private structure
6404 * @pipe: pipe PLL to enable
6405 * @dpll: PLL configuration
6406 *
6407 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6408 * in cases where we need the PLL enabled even when @pipe is not going to
6409 * be enabled.
6410 */
6411 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6412 const struct dpll *dpll)
6413 {
6414 struct intel_crtc *crtc =
6415 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6416 struct intel_crtc_state pipe_config = {
6417 .base.crtc = &crtc->base,
6418 .pixel_multiplier = 1,
6419 .dpll = *dpll,
6420 };
6421
6422 if (IS_CHERRYVIEW(dev)) {
6423 chv_update_pll(crtc, &pipe_config);
6424 chv_prepare_pll(crtc, &pipe_config);
6425 chv_enable_pll(crtc, &pipe_config);
6426 } else {
6427 vlv_update_pll(crtc, &pipe_config);
6428 vlv_prepare_pll(crtc, &pipe_config);
6429 vlv_enable_pll(crtc, &pipe_config);
6430 }
6431 }
6432
6433 /**
6434 * vlv_force_pll_off - forcibly disable just the PLL
6435 * @dev_priv: i915 private structure
6436 * @pipe: pipe PLL to disable
6437 *
6438 * Disable the PLL for @pipe. To be used in cases where we need
6439 * the PLL enabled even when @pipe is not going to be enabled.
6440 */
6441 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6442 {
6443 if (IS_CHERRYVIEW(dev))
6444 chv_disable_pll(to_i915(dev), pipe);
6445 else
6446 vlv_disable_pll(to_i915(dev), pipe);
6447 }
6448
6449 static void i9xx_update_pll(struct intel_crtc *crtc,
6450 struct intel_crtc_state *crtc_state,
6451 intel_clock_t *reduced_clock,
6452 int num_connectors)
6453 {
6454 struct drm_device *dev = crtc->base.dev;
6455 struct drm_i915_private *dev_priv = dev->dev_private;
6456 u32 dpll;
6457 bool is_sdvo;
6458 struct dpll *clock = &crtc_state->dpll;
6459
6460 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6461
6462 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
6463 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
6464
6465 dpll = DPLL_VGA_MODE_DIS;
6466
6467 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
6468 dpll |= DPLLB_MODE_LVDS;
6469 else
6470 dpll |= DPLLB_MODE_DAC_SERIAL;
6471
6472 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6473 dpll |= (crtc_state->pixel_multiplier - 1)
6474 << SDVO_MULTIPLIER_SHIFT_HIRES;
6475 }
6476
6477 if (is_sdvo)
6478 dpll |= DPLL_SDVO_HIGH_SPEED;
6479
6480 if (crtc_state->has_dp_encoder)
6481 dpll |= DPLL_SDVO_HIGH_SPEED;
6482
6483 /* compute bitmask from p1 value */
6484 if (IS_PINEVIEW(dev))
6485 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6486 else {
6487 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6488 if (IS_G4X(dev) && reduced_clock)
6489 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6490 }
6491 switch (clock->p2) {
6492 case 5:
6493 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6494 break;
6495 case 7:
6496 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6497 break;
6498 case 10:
6499 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6500 break;
6501 case 14:
6502 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6503 break;
6504 }
6505 if (INTEL_INFO(dev)->gen >= 4)
6506 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6507
6508 if (crtc_state->sdvo_tv_clock)
6509 dpll |= PLL_REF_INPUT_TVCLKINBC;
6510 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6511 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6512 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6513 else
6514 dpll |= PLL_REF_INPUT_DREFCLK;
6515
6516 dpll |= DPLL_VCO_ENABLE;
6517 crtc_state->dpll_hw_state.dpll = dpll;
6518
6519 if (INTEL_INFO(dev)->gen >= 4) {
6520 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6521 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6522 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6523 }
6524 }
6525
6526 static void i8xx_update_pll(struct intel_crtc *crtc,
6527 struct intel_crtc_state *crtc_state,
6528 intel_clock_t *reduced_clock,
6529 int num_connectors)
6530 {
6531 struct drm_device *dev = crtc->base.dev;
6532 struct drm_i915_private *dev_priv = dev->dev_private;
6533 u32 dpll;
6534 struct dpll *clock = &crtc_state->dpll;
6535
6536 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6537
6538 dpll = DPLL_VGA_MODE_DIS;
6539
6540 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
6541 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6542 } else {
6543 if (clock->p1 == 2)
6544 dpll |= PLL_P1_DIVIDE_BY_TWO;
6545 else
6546 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6547 if (clock->p2 == 4)
6548 dpll |= PLL_P2_DIVIDE_BY_4;
6549 }
6550
6551 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
6552 dpll |= DPLL_DVO_2X_MODE;
6553
6554 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6555 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6556 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6557 else
6558 dpll |= PLL_REF_INPUT_DREFCLK;
6559
6560 dpll |= DPLL_VCO_ENABLE;
6561 crtc_state->dpll_hw_state.dpll = dpll;
6562 }
6563
6564 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6565 {
6566 struct drm_device *dev = intel_crtc->base.dev;
6567 struct drm_i915_private *dev_priv = dev->dev_private;
6568 enum pipe pipe = intel_crtc->pipe;
6569 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6570 struct drm_display_mode *adjusted_mode =
6571 &intel_crtc->config->base.adjusted_mode;
6572 uint32_t crtc_vtotal, crtc_vblank_end;
6573 int vsyncshift = 0;
6574
6575 /* We need to be careful not to changed the adjusted mode, for otherwise
6576 * the hw state checker will get angry at the mismatch. */
6577 crtc_vtotal = adjusted_mode->crtc_vtotal;
6578 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6579
6580 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6581 /* the chip adds 2 halflines automatically */
6582 crtc_vtotal -= 1;
6583 crtc_vblank_end -= 1;
6584
6585 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6586 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6587 else
6588 vsyncshift = adjusted_mode->crtc_hsync_start -
6589 adjusted_mode->crtc_htotal / 2;
6590 if (vsyncshift < 0)
6591 vsyncshift += adjusted_mode->crtc_htotal;
6592 }
6593
6594 if (INTEL_INFO(dev)->gen > 3)
6595 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6596
6597 I915_WRITE(HTOTAL(cpu_transcoder),
6598 (adjusted_mode->crtc_hdisplay - 1) |
6599 ((adjusted_mode->crtc_htotal - 1) << 16));
6600 I915_WRITE(HBLANK(cpu_transcoder),
6601 (adjusted_mode->crtc_hblank_start - 1) |
6602 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6603 I915_WRITE(HSYNC(cpu_transcoder),
6604 (adjusted_mode->crtc_hsync_start - 1) |
6605 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6606
6607 I915_WRITE(VTOTAL(cpu_transcoder),
6608 (adjusted_mode->crtc_vdisplay - 1) |
6609 ((crtc_vtotal - 1) << 16));
6610 I915_WRITE(VBLANK(cpu_transcoder),
6611 (adjusted_mode->crtc_vblank_start - 1) |
6612 ((crtc_vblank_end - 1) << 16));
6613 I915_WRITE(VSYNC(cpu_transcoder),
6614 (adjusted_mode->crtc_vsync_start - 1) |
6615 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6616
6617 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6618 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6619 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6620 * bits. */
6621 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6622 (pipe == PIPE_B || pipe == PIPE_C))
6623 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6624
6625 /* pipesrc controls the size that is scaled from, which should
6626 * always be the user's requested size.
6627 */
6628 I915_WRITE(PIPESRC(pipe),
6629 ((intel_crtc->config->pipe_src_w - 1) << 16) |
6630 (intel_crtc->config->pipe_src_h - 1));
6631 }
6632
6633 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6634 struct intel_crtc_state *pipe_config)
6635 {
6636 struct drm_device *dev = crtc->base.dev;
6637 struct drm_i915_private *dev_priv = dev->dev_private;
6638 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6639 uint32_t tmp;
6640
6641 tmp = I915_READ(HTOTAL(cpu_transcoder));
6642 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6643 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6644 tmp = I915_READ(HBLANK(cpu_transcoder));
6645 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6646 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6647 tmp = I915_READ(HSYNC(cpu_transcoder));
6648 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6649 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6650
6651 tmp = I915_READ(VTOTAL(cpu_transcoder));
6652 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6653 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6654 tmp = I915_READ(VBLANK(cpu_transcoder));
6655 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6656 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6657 tmp = I915_READ(VSYNC(cpu_transcoder));
6658 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6659 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6660
6661 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6662 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6663 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6664 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
6665 }
6666
6667 tmp = I915_READ(PIPESRC(crtc->pipe));
6668 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6669 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6670
6671 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
6672 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
6673 }
6674
6675 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6676 struct intel_crtc_state *pipe_config)
6677 {
6678 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
6679 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
6680 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
6681 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
6682
6683 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
6684 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
6685 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
6686 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
6687
6688 mode->flags = pipe_config->base.adjusted_mode.flags;
6689
6690 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
6691 mode->flags |= pipe_config->base.adjusted_mode.flags;
6692 }
6693
6694 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6695 {
6696 struct drm_device *dev = intel_crtc->base.dev;
6697 struct drm_i915_private *dev_priv = dev->dev_private;
6698 uint32_t pipeconf;
6699
6700 pipeconf = 0;
6701
6702 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6703 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6704 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6705
6706 if (intel_crtc->config->double_wide)
6707 pipeconf |= PIPECONF_DOUBLE_WIDE;
6708
6709 /* only g4x and later have fancy bpc/dither controls */
6710 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6711 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6712 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
6713 pipeconf |= PIPECONF_DITHER_EN |
6714 PIPECONF_DITHER_TYPE_SP;
6715
6716 switch (intel_crtc->config->pipe_bpp) {
6717 case 18:
6718 pipeconf |= PIPECONF_6BPC;
6719 break;
6720 case 24:
6721 pipeconf |= PIPECONF_8BPC;
6722 break;
6723 case 30:
6724 pipeconf |= PIPECONF_10BPC;
6725 break;
6726 default:
6727 /* Case prevented by intel_choose_pipe_bpp_dither. */
6728 BUG();
6729 }
6730 }
6731
6732 if (HAS_PIPE_CXSR(dev)) {
6733 if (intel_crtc->lowfreq_avail) {
6734 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6735 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6736 } else {
6737 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6738 }
6739 }
6740
6741 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6742 if (INTEL_INFO(dev)->gen < 4 ||
6743 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6744 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6745 else
6746 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6747 } else
6748 pipeconf |= PIPECONF_PROGRESSIVE;
6749
6750 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
6751 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6752
6753 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6754 POSTING_READ(PIPECONF(intel_crtc->pipe));
6755 }
6756
6757 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
6758 struct intel_crtc_state *crtc_state)
6759 {
6760 struct drm_device *dev = crtc->base.dev;
6761 struct drm_i915_private *dev_priv = dev->dev_private;
6762 int refclk, num_connectors = 0;
6763 intel_clock_t clock, reduced_clock;
6764 bool ok, has_reduced_clock = false;
6765 bool is_lvds = false, is_dsi = false;
6766 struct intel_encoder *encoder;
6767 const intel_limit_t *limit;
6768 struct drm_atomic_state *state = crtc_state->base.state;
6769 struct drm_connector_state *connector_state;
6770 int i;
6771
6772 for (i = 0; i < state->num_connector; i++) {
6773 if (!state->connectors[i])
6774 continue;
6775
6776 connector_state = state->connector_states[i];
6777 if (connector_state->crtc != &crtc->base)
6778 continue;
6779
6780 encoder = to_intel_encoder(connector_state->best_encoder);
6781
6782 switch (encoder->type) {
6783 case INTEL_OUTPUT_LVDS:
6784 is_lvds = true;
6785 break;
6786 case INTEL_OUTPUT_DSI:
6787 is_dsi = true;
6788 break;
6789 default:
6790 break;
6791 }
6792
6793 num_connectors++;
6794 }
6795
6796 if (is_dsi)
6797 return 0;
6798
6799 if (!crtc_state->clock_set) {
6800 refclk = i9xx_get_refclk(crtc_state, num_connectors);
6801
6802 /*
6803 * Returns a set of divisors for the desired target clock with
6804 * the given refclk, or FALSE. The returned values represent
6805 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6806 * 2) / p1 / p2.
6807 */
6808 limit = intel_limit(crtc_state, refclk);
6809 ok = dev_priv->display.find_dpll(limit, crtc_state,
6810 crtc_state->port_clock,
6811 refclk, NULL, &clock);
6812 if (!ok) {
6813 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6814 return -EINVAL;
6815 }
6816
6817 if (is_lvds && dev_priv->lvds_downclock_avail) {
6818 /*
6819 * Ensure we match the reduced clock's P to the target
6820 * clock. If the clocks don't match, we can't switch
6821 * the display clock by using the FP0/FP1. In such case
6822 * we will disable the LVDS downclock feature.
6823 */
6824 has_reduced_clock =
6825 dev_priv->display.find_dpll(limit, crtc_state,
6826 dev_priv->lvds_downclock,
6827 refclk, &clock,
6828 &reduced_clock);
6829 }
6830 /* Compat-code for transition, will disappear. */
6831 crtc_state->dpll.n = clock.n;
6832 crtc_state->dpll.m1 = clock.m1;
6833 crtc_state->dpll.m2 = clock.m2;
6834 crtc_state->dpll.p1 = clock.p1;
6835 crtc_state->dpll.p2 = clock.p2;
6836 }
6837
6838 if (IS_GEN2(dev)) {
6839 i8xx_update_pll(crtc, crtc_state,
6840 has_reduced_clock ? &reduced_clock : NULL,
6841 num_connectors);
6842 } else if (IS_CHERRYVIEW(dev)) {
6843 chv_update_pll(crtc, crtc_state);
6844 } else if (IS_VALLEYVIEW(dev)) {
6845 vlv_update_pll(crtc, crtc_state);
6846 } else {
6847 i9xx_update_pll(crtc, crtc_state,
6848 has_reduced_clock ? &reduced_clock : NULL,
6849 num_connectors);
6850 }
6851
6852 return 0;
6853 }
6854
6855 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6856 struct intel_crtc_state *pipe_config)
6857 {
6858 struct drm_device *dev = crtc->base.dev;
6859 struct drm_i915_private *dev_priv = dev->dev_private;
6860 uint32_t tmp;
6861
6862 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6863 return;
6864
6865 tmp = I915_READ(PFIT_CONTROL);
6866 if (!(tmp & PFIT_ENABLE))
6867 return;
6868
6869 /* Check whether the pfit is attached to our pipe. */
6870 if (INTEL_INFO(dev)->gen < 4) {
6871 if (crtc->pipe != PIPE_B)
6872 return;
6873 } else {
6874 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6875 return;
6876 }
6877
6878 pipe_config->gmch_pfit.control = tmp;
6879 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6880 if (INTEL_INFO(dev)->gen < 5)
6881 pipe_config->gmch_pfit.lvds_border_bits =
6882 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6883 }
6884
6885 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6886 struct intel_crtc_state *pipe_config)
6887 {
6888 struct drm_device *dev = crtc->base.dev;
6889 struct drm_i915_private *dev_priv = dev->dev_private;
6890 int pipe = pipe_config->cpu_transcoder;
6891 intel_clock_t clock;
6892 u32 mdiv;
6893 int refclk = 100000;
6894
6895 /* In case of MIPI DPLL will not even be used */
6896 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6897 return;
6898
6899 mutex_lock(&dev_priv->dpio_lock);
6900 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6901 mutex_unlock(&dev_priv->dpio_lock);
6902
6903 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6904 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6905 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6906 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6907 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6908
6909 vlv_clock(refclk, &clock);
6910
6911 /* clock.dot is the fast clock */
6912 pipe_config->port_clock = clock.dot / 5;
6913 }
6914
6915 static void
6916 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
6917 struct intel_initial_plane_config *plane_config)
6918 {
6919 struct drm_device *dev = crtc->base.dev;
6920 struct drm_i915_private *dev_priv = dev->dev_private;
6921 u32 val, base, offset;
6922 int pipe = crtc->pipe, plane = crtc->plane;
6923 int fourcc, pixel_format;
6924 unsigned int aligned_height;
6925 struct drm_framebuffer *fb;
6926 struct intel_framebuffer *intel_fb;
6927
6928 val = I915_READ(DSPCNTR(plane));
6929 if (!(val & DISPLAY_PLANE_ENABLE))
6930 return;
6931
6932 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6933 if (!intel_fb) {
6934 DRM_DEBUG_KMS("failed to alloc fb\n");
6935 return;
6936 }
6937
6938 fb = &intel_fb->base;
6939
6940 if (INTEL_INFO(dev)->gen >= 4) {
6941 if (val & DISPPLANE_TILED) {
6942 plane_config->tiling = I915_TILING_X;
6943 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
6944 }
6945 }
6946
6947 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6948 fourcc = i9xx_format_to_fourcc(pixel_format);
6949 fb->pixel_format = fourcc;
6950 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
6951
6952 if (INTEL_INFO(dev)->gen >= 4) {
6953 if (plane_config->tiling)
6954 offset = I915_READ(DSPTILEOFF(plane));
6955 else
6956 offset = I915_READ(DSPLINOFF(plane));
6957 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6958 } else {
6959 base = I915_READ(DSPADDR(plane));
6960 }
6961 plane_config->base = base;
6962
6963 val = I915_READ(PIPESRC(pipe));
6964 fb->width = ((val >> 16) & 0xfff) + 1;
6965 fb->height = ((val >> 0) & 0xfff) + 1;
6966
6967 val = I915_READ(DSPSTRIDE(pipe));
6968 fb->pitches[0] = val & 0xffffffc0;
6969
6970 aligned_height = intel_fb_align_height(dev, fb->height,
6971 fb->pixel_format,
6972 fb->modifier[0]);
6973
6974 plane_config->size = fb->pitches[0] * aligned_height;
6975
6976 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6977 pipe_name(pipe), plane, fb->width, fb->height,
6978 fb->bits_per_pixel, base, fb->pitches[0],
6979 plane_config->size);
6980
6981 plane_config->fb = intel_fb;
6982 }
6983
6984 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6985 struct intel_crtc_state *pipe_config)
6986 {
6987 struct drm_device *dev = crtc->base.dev;
6988 struct drm_i915_private *dev_priv = dev->dev_private;
6989 int pipe = pipe_config->cpu_transcoder;
6990 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6991 intel_clock_t clock;
6992 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6993 int refclk = 100000;
6994
6995 mutex_lock(&dev_priv->dpio_lock);
6996 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6997 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6998 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6999 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7000 mutex_unlock(&dev_priv->dpio_lock);
7001
7002 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7003 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
7004 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7005 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7006 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7007
7008 chv_clock(refclk, &clock);
7009
7010 /* clock.dot is the fast clock */
7011 pipe_config->port_clock = clock.dot / 5;
7012 }
7013
7014 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7015 struct intel_crtc_state *pipe_config)
7016 {
7017 struct drm_device *dev = crtc->base.dev;
7018 struct drm_i915_private *dev_priv = dev->dev_private;
7019 uint32_t tmp;
7020
7021 if (!intel_display_power_is_enabled(dev_priv,
7022 POWER_DOMAIN_PIPE(crtc->pipe)))
7023 return false;
7024
7025 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7026 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7027
7028 tmp = I915_READ(PIPECONF(crtc->pipe));
7029 if (!(tmp & PIPECONF_ENABLE))
7030 return false;
7031
7032 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7033 switch (tmp & PIPECONF_BPC_MASK) {
7034 case PIPECONF_6BPC:
7035 pipe_config->pipe_bpp = 18;
7036 break;
7037 case PIPECONF_8BPC:
7038 pipe_config->pipe_bpp = 24;
7039 break;
7040 case PIPECONF_10BPC:
7041 pipe_config->pipe_bpp = 30;
7042 break;
7043 default:
7044 break;
7045 }
7046 }
7047
7048 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
7049 pipe_config->limited_color_range = true;
7050
7051 if (INTEL_INFO(dev)->gen < 4)
7052 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7053
7054 intel_get_pipe_timings(crtc, pipe_config);
7055
7056 i9xx_get_pfit_config(crtc, pipe_config);
7057
7058 if (INTEL_INFO(dev)->gen >= 4) {
7059 tmp = I915_READ(DPLL_MD(crtc->pipe));
7060 pipe_config->pixel_multiplier =
7061 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7062 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7063 pipe_config->dpll_hw_state.dpll_md = tmp;
7064 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7065 tmp = I915_READ(DPLL(crtc->pipe));
7066 pipe_config->pixel_multiplier =
7067 ((tmp & SDVO_MULTIPLIER_MASK)
7068 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7069 } else {
7070 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7071 * port and will be fixed up in the encoder->get_config
7072 * function. */
7073 pipe_config->pixel_multiplier = 1;
7074 }
7075 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7076 if (!IS_VALLEYVIEW(dev)) {
7077 /*
7078 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7079 * on 830. Filter it out here so that we don't
7080 * report errors due to that.
7081 */
7082 if (IS_I830(dev))
7083 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7084
7085 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7086 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7087 } else {
7088 /* Mask out read-only status bits. */
7089 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7090 DPLL_PORTC_READY_MASK |
7091 DPLL_PORTB_READY_MASK);
7092 }
7093
7094 if (IS_CHERRYVIEW(dev))
7095 chv_crtc_clock_get(crtc, pipe_config);
7096 else if (IS_VALLEYVIEW(dev))
7097 vlv_crtc_clock_get(crtc, pipe_config);
7098 else
7099 i9xx_crtc_clock_get(crtc, pipe_config);
7100
7101 return true;
7102 }
7103
7104 static void ironlake_init_pch_refclk(struct drm_device *dev)
7105 {
7106 struct drm_i915_private *dev_priv = dev->dev_private;
7107 struct intel_encoder *encoder;
7108 u32 val, final;
7109 bool has_lvds = false;
7110 bool has_cpu_edp = false;
7111 bool has_panel = false;
7112 bool has_ck505 = false;
7113 bool can_ssc = false;
7114
7115 /* We need to take the global config into account */
7116 for_each_intel_encoder(dev, encoder) {
7117 switch (encoder->type) {
7118 case INTEL_OUTPUT_LVDS:
7119 has_panel = true;
7120 has_lvds = true;
7121 break;
7122 case INTEL_OUTPUT_EDP:
7123 has_panel = true;
7124 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
7125 has_cpu_edp = true;
7126 break;
7127 default:
7128 break;
7129 }
7130 }
7131
7132 if (HAS_PCH_IBX(dev)) {
7133 has_ck505 = dev_priv->vbt.display_clock_mode;
7134 can_ssc = has_ck505;
7135 } else {
7136 has_ck505 = false;
7137 can_ssc = true;
7138 }
7139
7140 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
7141 has_panel, has_lvds, has_ck505);
7142
7143 /* Ironlake: try to setup display ref clock before DPLL
7144 * enabling. This is only under driver's control after
7145 * PCH B stepping, previous chipset stepping should be
7146 * ignoring this setting.
7147 */
7148 val = I915_READ(PCH_DREF_CONTROL);
7149
7150 /* As we must carefully and slowly disable/enable each source in turn,
7151 * compute the final state we want first and check if we need to
7152 * make any changes at all.
7153 */
7154 final = val;
7155 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7156 if (has_ck505)
7157 final |= DREF_NONSPREAD_CK505_ENABLE;
7158 else
7159 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7160
7161 final &= ~DREF_SSC_SOURCE_MASK;
7162 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7163 final &= ~DREF_SSC1_ENABLE;
7164
7165 if (has_panel) {
7166 final |= DREF_SSC_SOURCE_ENABLE;
7167
7168 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7169 final |= DREF_SSC1_ENABLE;
7170
7171 if (has_cpu_edp) {
7172 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7173 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7174 else
7175 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7176 } else
7177 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7178 } else {
7179 final |= DREF_SSC_SOURCE_DISABLE;
7180 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7181 }
7182
7183 if (final == val)
7184 return;
7185
7186 /* Always enable nonspread source */
7187 val &= ~DREF_NONSPREAD_SOURCE_MASK;
7188
7189 if (has_ck505)
7190 val |= DREF_NONSPREAD_CK505_ENABLE;
7191 else
7192 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7193
7194 if (has_panel) {
7195 val &= ~DREF_SSC_SOURCE_MASK;
7196 val |= DREF_SSC_SOURCE_ENABLE;
7197
7198 /* SSC must be turned on before enabling the CPU output */
7199 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7200 DRM_DEBUG_KMS("Using SSC on panel\n");
7201 val |= DREF_SSC1_ENABLE;
7202 } else
7203 val &= ~DREF_SSC1_ENABLE;
7204
7205 /* Get SSC going before enabling the outputs */
7206 I915_WRITE(PCH_DREF_CONTROL, val);
7207 POSTING_READ(PCH_DREF_CONTROL);
7208 udelay(200);
7209
7210 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7211
7212 /* Enable CPU source on CPU attached eDP */
7213 if (has_cpu_edp) {
7214 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7215 DRM_DEBUG_KMS("Using SSC on eDP\n");
7216 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7217 } else
7218 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7219 } else
7220 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7221
7222 I915_WRITE(PCH_DREF_CONTROL, val);
7223 POSTING_READ(PCH_DREF_CONTROL);
7224 udelay(200);
7225 } else {
7226 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7227
7228 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7229
7230 /* Turn off CPU output */
7231 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7232
7233 I915_WRITE(PCH_DREF_CONTROL, val);
7234 POSTING_READ(PCH_DREF_CONTROL);
7235 udelay(200);
7236
7237 /* Turn off the SSC source */
7238 val &= ~DREF_SSC_SOURCE_MASK;
7239 val |= DREF_SSC_SOURCE_DISABLE;
7240
7241 /* Turn off SSC1 */
7242 val &= ~DREF_SSC1_ENABLE;
7243
7244 I915_WRITE(PCH_DREF_CONTROL, val);
7245 POSTING_READ(PCH_DREF_CONTROL);
7246 udelay(200);
7247 }
7248
7249 BUG_ON(val != final);
7250 }
7251
7252 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7253 {
7254 uint32_t tmp;
7255
7256 tmp = I915_READ(SOUTH_CHICKEN2);
7257 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7258 I915_WRITE(SOUTH_CHICKEN2, tmp);
7259
7260 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
7261 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7262 DRM_ERROR("FDI mPHY reset assert timeout\n");
7263
7264 tmp = I915_READ(SOUTH_CHICKEN2);
7265 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7266 I915_WRITE(SOUTH_CHICKEN2, tmp);
7267
7268 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
7269 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7270 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7271 }
7272
7273 /* WaMPhyProgramming:hsw */
7274 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7275 {
7276 uint32_t tmp;
7277
7278 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7279 tmp &= ~(0xFF << 24);
7280 tmp |= (0x12 << 24);
7281 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7282
7283 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7284 tmp |= (1 << 11);
7285 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7286
7287 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7288 tmp |= (1 << 11);
7289 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7290
7291 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7292 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7293 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7294
7295 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7296 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7297 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7298
7299 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7300 tmp &= ~(7 << 13);
7301 tmp |= (5 << 13);
7302 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7303
7304 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7305 tmp &= ~(7 << 13);
7306 tmp |= (5 << 13);
7307 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7308
7309 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7310 tmp &= ~0xFF;
7311 tmp |= 0x1C;
7312 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7313
7314 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7315 tmp &= ~0xFF;
7316 tmp |= 0x1C;
7317 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7318
7319 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7320 tmp &= ~(0xFF << 16);
7321 tmp |= (0x1C << 16);
7322 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7323
7324 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7325 tmp &= ~(0xFF << 16);
7326 tmp |= (0x1C << 16);
7327 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7328
7329 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7330 tmp |= (1 << 27);
7331 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7332
7333 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7334 tmp |= (1 << 27);
7335 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7336
7337 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7338 tmp &= ~(0xF << 28);
7339 tmp |= (4 << 28);
7340 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7341
7342 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7343 tmp &= ~(0xF << 28);
7344 tmp |= (4 << 28);
7345 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7346 }
7347
7348 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7349 * Programming" based on the parameters passed:
7350 * - Sequence to enable CLKOUT_DP
7351 * - Sequence to enable CLKOUT_DP without spread
7352 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7353 */
7354 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
7355 bool with_fdi)
7356 {
7357 struct drm_i915_private *dev_priv = dev->dev_private;
7358 uint32_t reg, tmp;
7359
7360 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7361 with_spread = true;
7362 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
7363 with_fdi, "LP PCH doesn't have FDI\n"))
7364 with_fdi = false;
7365
7366 mutex_lock(&dev_priv->dpio_lock);
7367
7368 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7369 tmp &= ~SBI_SSCCTL_DISABLE;
7370 tmp |= SBI_SSCCTL_PATHALT;
7371 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7372
7373 udelay(24);
7374
7375 if (with_spread) {
7376 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7377 tmp &= ~SBI_SSCCTL_PATHALT;
7378 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7379
7380 if (with_fdi) {
7381 lpt_reset_fdi_mphy(dev_priv);
7382 lpt_program_fdi_mphy(dev_priv);
7383 }
7384 }
7385
7386 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7387 SBI_GEN0 : SBI_DBUFF0;
7388 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7389 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7390 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7391
7392 mutex_unlock(&dev_priv->dpio_lock);
7393 }
7394
7395 /* Sequence to disable CLKOUT_DP */
7396 static void lpt_disable_clkout_dp(struct drm_device *dev)
7397 {
7398 struct drm_i915_private *dev_priv = dev->dev_private;
7399 uint32_t reg, tmp;
7400
7401 mutex_lock(&dev_priv->dpio_lock);
7402
7403 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7404 SBI_GEN0 : SBI_DBUFF0;
7405 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7406 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7407 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7408
7409 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7410 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7411 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7412 tmp |= SBI_SSCCTL_PATHALT;
7413 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7414 udelay(32);
7415 }
7416 tmp |= SBI_SSCCTL_DISABLE;
7417 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7418 }
7419
7420 mutex_unlock(&dev_priv->dpio_lock);
7421 }
7422
7423 static void lpt_init_pch_refclk(struct drm_device *dev)
7424 {
7425 struct intel_encoder *encoder;
7426 bool has_vga = false;
7427
7428 for_each_intel_encoder(dev, encoder) {
7429 switch (encoder->type) {
7430 case INTEL_OUTPUT_ANALOG:
7431 has_vga = true;
7432 break;
7433 default:
7434 break;
7435 }
7436 }
7437
7438 if (has_vga)
7439 lpt_enable_clkout_dp(dev, true, true);
7440 else
7441 lpt_disable_clkout_dp(dev);
7442 }
7443
7444 /*
7445 * Initialize reference clocks when the driver loads
7446 */
7447 void intel_init_pch_refclk(struct drm_device *dev)
7448 {
7449 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7450 ironlake_init_pch_refclk(dev);
7451 else if (HAS_PCH_LPT(dev))
7452 lpt_init_pch_refclk(dev);
7453 }
7454
7455 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
7456 {
7457 struct drm_device *dev = crtc_state->base.crtc->dev;
7458 struct drm_i915_private *dev_priv = dev->dev_private;
7459 struct drm_atomic_state *state = crtc_state->base.state;
7460 struct drm_connector_state *connector_state;
7461 struct intel_encoder *encoder;
7462 int num_connectors = 0, i;
7463 bool is_lvds = false;
7464
7465 for (i = 0; i < state->num_connector; i++) {
7466 if (!state->connectors[i])
7467 continue;
7468
7469 connector_state = state->connector_states[i];
7470 if (connector_state->crtc != crtc_state->base.crtc)
7471 continue;
7472
7473 encoder = to_intel_encoder(connector_state->best_encoder);
7474
7475 switch (encoder->type) {
7476 case INTEL_OUTPUT_LVDS:
7477 is_lvds = true;
7478 break;
7479 default:
7480 break;
7481 }
7482 num_connectors++;
7483 }
7484
7485 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7486 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7487 dev_priv->vbt.lvds_ssc_freq);
7488 return dev_priv->vbt.lvds_ssc_freq;
7489 }
7490
7491 return 120000;
7492 }
7493
7494 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7495 {
7496 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7497 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7498 int pipe = intel_crtc->pipe;
7499 uint32_t val;
7500
7501 val = 0;
7502
7503 switch (intel_crtc->config->pipe_bpp) {
7504 case 18:
7505 val |= PIPECONF_6BPC;
7506 break;
7507 case 24:
7508 val |= PIPECONF_8BPC;
7509 break;
7510 case 30:
7511 val |= PIPECONF_10BPC;
7512 break;
7513 case 36:
7514 val |= PIPECONF_12BPC;
7515 break;
7516 default:
7517 /* Case prevented by intel_choose_pipe_bpp_dither. */
7518 BUG();
7519 }
7520
7521 if (intel_crtc->config->dither)
7522 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7523
7524 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7525 val |= PIPECONF_INTERLACED_ILK;
7526 else
7527 val |= PIPECONF_PROGRESSIVE;
7528
7529 if (intel_crtc->config->limited_color_range)
7530 val |= PIPECONF_COLOR_RANGE_SELECT;
7531
7532 I915_WRITE(PIPECONF(pipe), val);
7533 POSTING_READ(PIPECONF(pipe));
7534 }
7535
7536 /*
7537 * Set up the pipe CSC unit.
7538 *
7539 * Currently only full range RGB to limited range RGB conversion
7540 * is supported, but eventually this should handle various
7541 * RGB<->YCbCr scenarios as well.
7542 */
7543 static void intel_set_pipe_csc(struct drm_crtc *crtc)
7544 {
7545 struct drm_device *dev = crtc->dev;
7546 struct drm_i915_private *dev_priv = dev->dev_private;
7547 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7548 int pipe = intel_crtc->pipe;
7549 uint16_t coeff = 0x7800; /* 1.0 */
7550
7551 /*
7552 * TODO: Check what kind of values actually come out of the pipe
7553 * with these coeff/postoff values and adjust to get the best
7554 * accuracy. Perhaps we even need to take the bpc value into
7555 * consideration.
7556 */
7557
7558 if (intel_crtc->config->limited_color_range)
7559 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7560
7561 /*
7562 * GY/GU and RY/RU should be the other way around according
7563 * to BSpec, but reality doesn't agree. Just set them up in
7564 * a way that results in the correct picture.
7565 */
7566 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7567 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7568
7569 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7570 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7571
7572 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7573 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7574
7575 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7576 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7577 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7578
7579 if (INTEL_INFO(dev)->gen > 6) {
7580 uint16_t postoff = 0;
7581
7582 if (intel_crtc->config->limited_color_range)
7583 postoff = (16 * (1 << 12) / 255) & 0x1fff;
7584
7585 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7586 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7587 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7588
7589 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7590 } else {
7591 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7592
7593 if (intel_crtc->config->limited_color_range)
7594 mode |= CSC_BLACK_SCREEN_OFFSET;
7595
7596 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7597 }
7598 }
7599
7600 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7601 {
7602 struct drm_device *dev = crtc->dev;
7603 struct drm_i915_private *dev_priv = dev->dev_private;
7604 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7605 enum pipe pipe = intel_crtc->pipe;
7606 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7607 uint32_t val;
7608
7609 val = 0;
7610
7611 if (IS_HASWELL(dev) && intel_crtc->config->dither)
7612 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7613
7614 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7615 val |= PIPECONF_INTERLACED_ILK;
7616 else
7617 val |= PIPECONF_PROGRESSIVE;
7618
7619 I915_WRITE(PIPECONF(cpu_transcoder), val);
7620 POSTING_READ(PIPECONF(cpu_transcoder));
7621
7622 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7623 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7624
7625 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7626 val = 0;
7627
7628 switch (intel_crtc->config->pipe_bpp) {
7629 case 18:
7630 val |= PIPEMISC_DITHER_6_BPC;
7631 break;
7632 case 24:
7633 val |= PIPEMISC_DITHER_8_BPC;
7634 break;
7635 case 30:
7636 val |= PIPEMISC_DITHER_10_BPC;
7637 break;
7638 case 36:
7639 val |= PIPEMISC_DITHER_12_BPC;
7640 break;
7641 default:
7642 /* Case prevented by pipe_config_set_bpp. */
7643 BUG();
7644 }
7645
7646 if (intel_crtc->config->dither)
7647 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7648
7649 I915_WRITE(PIPEMISC(pipe), val);
7650 }
7651 }
7652
7653 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7654 struct intel_crtc_state *crtc_state,
7655 intel_clock_t *clock,
7656 bool *has_reduced_clock,
7657 intel_clock_t *reduced_clock)
7658 {
7659 struct drm_device *dev = crtc->dev;
7660 struct drm_i915_private *dev_priv = dev->dev_private;
7661 int refclk;
7662 const intel_limit_t *limit;
7663 bool ret, is_lvds = false;
7664
7665 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
7666
7667 refclk = ironlake_get_refclk(crtc_state);
7668
7669 /*
7670 * Returns a set of divisors for the desired target clock with the given
7671 * refclk, or FALSE. The returned values represent the clock equation:
7672 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7673 */
7674 limit = intel_limit(crtc_state, refclk);
7675 ret = dev_priv->display.find_dpll(limit, crtc_state,
7676 crtc_state->port_clock,
7677 refclk, NULL, clock);
7678 if (!ret)
7679 return false;
7680
7681 if (is_lvds && dev_priv->lvds_downclock_avail) {
7682 /*
7683 * Ensure we match the reduced clock's P to the target clock.
7684 * If the clocks don't match, we can't switch the display clock
7685 * by using the FP0/FP1. In such case we will disable the LVDS
7686 * downclock feature.
7687 */
7688 *has_reduced_clock =
7689 dev_priv->display.find_dpll(limit, crtc_state,
7690 dev_priv->lvds_downclock,
7691 refclk, clock,
7692 reduced_clock);
7693 }
7694
7695 return true;
7696 }
7697
7698 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7699 {
7700 /*
7701 * Account for spread spectrum to avoid
7702 * oversubscribing the link. Max center spread
7703 * is 2.5%; use 5% for safety's sake.
7704 */
7705 u32 bps = target_clock * bpp * 21 / 20;
7706 return DIV_ROUND_UP(bps, link_bw * 8);
7707 }
7708
7709 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7710 {
7711 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7712 }
7713
7714 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7715 struct intel_crtc_state *crtc_state,
7716 u32 *fp,
7717 intel_clock_t *reduced_clock, u32 *fp2)
7718 {
7719 struct drm_crtc *crtc = &intel_crtc->base;
7720 struct drm_device *dev = crtc->dev;
7721 struct drm_i915_private *dev_priv = dev->dev_private;
7722 struct drm_atomic_state *state = crtc_state->base.state;
7723 struct drm_connector_state *connector_state;
7724 struct intel_encoder *encoder;
7725 uint32_t dpll;
7726 int factor, num_connectors = 0, i;
7727 bool is_lvds = false, is_sdvo = false;
7728
7729 for (i = 0; i < state->num_connector; i++) {
7730 if (!state->connectors[i])
7731 continue;
7732
7733 connector_state = state->connector_states[i];
7734 if (connector_state->crtc != crtc_state->base.crtc)
7735 continue;
7736
7737 encoder = to_intel_encoder(connector_state->best_encoder);
7738
7739 switch (encoder->type) {
7740 case INTEL_OUTPUT_LVDS:
7741 is_lvds = true;
7742 break;
7743 case INTEL_OUTPUT_SDVO:
7744 case INTEL_OUTPUT_HDMI:
7745 is_sdvo = true;
7746 break;
7747 default:
7748 break;
7749 }
7750
7751 num_connectors++;
7752 }
7753
7754 /* Enable autotuning of the PLL clock (if permissible) */
7755 factor = 21;
7756 if (is_lvds) {
7757 if ((intel_panel_use_ssc(dev_priv) &&
7758 dev_priv->vbt.lvds_ssc_freq == 100000) ||
7759 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7760 factor = 25;
7761 } else if (crtc_state->sdvo_tv_clock)
7762 factor = 20;
7763
7764 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7765 *fp |= FP_CB_TUNE;
7766
7767 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7768 *fp2 |= FP_CB_TUNE;
7769
7770 dpll = 0;
7771
7772 if (is_lvds)
7773 dpll |= DPLLB_MODE_LVDS;
7774 else
7775 dpll |= DPLLB_MODE_DAC_SERIAL;
7776
7777 dpll |= (crtc_state->pixel_multiplier - 1)
7778 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7779
7780 if (is_sdvo)
7781 dpll |= DPLL_SDVO_HIGH_SPEED;
7782 if (crtc_state->has_dp_encoder)
7783 dpll |= DPLL_SDVO_HIGH_SPEED;
7784
7785 /* compute bitmask from p1 value */
7786 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7787 /* also FPA1 */
7788 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7789
7790 switch (crtc_state->dpll.p2) {
7791 case 5:
7792 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7793 break;
7794 case 7:
7795 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7796 break;
7797 case 10:
7798 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7799 break;
7800 case 14:
7801 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7802 break;
7803 }
7804
7805 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7806 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7807 else
7808 dpll |= PLL_REF_INPUT_DREFCLK;
7809
7810 return dpll | DPLL_VCO_ENABLE;
7811 }
7812
7813 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
7814 struct intel_crtc_state *crtc_state)
7815 {
7816 struct drm_device *dev = crtc->base.dev;
7817 intel_clock_t clock, reduced_clock;
7818 u32 dpll = 0, fp = 0, fp2 = 0;
7819 bool ok, has_reduced_clock = false;
7820 bool is_lvds = false;
7821 struct intel_shared_dpll *pll;
7822
7823 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7824
7825 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7826 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7827
7828 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
7829 &has_reduced_clock, &reduced_clock);
7830 if (!ok && !crtc_state->clock_set) {
7831 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7832 return -EINVAL;
7833 }
7834 /* Compat-code for transition, will disappear. */
7835 if (!crtc_state->clock_set) {
7836 crtc_state->dpll.n = clock.n;
7837 crtc_state->dpll.m1 = clock.m1;
7838 crtc_state->dpll.m2 = clock.m2;
7839 crtc_state->dpll.p1 = clock.p1;
7840 crtc_state->dpll.p2 = clock.p2;
7841 }
7842
7843 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7844 if (crtc_state->has_pch_encoder) {
7845 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7846 if (has_reduced_clock)
7847 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7848
7849 dpll = ironlake_compute_dpll(crtc, crtc_state,
7850 &fp, &reduced_clock,
7851 has_reduced_clock ? &fp2 : NULL);
7852
7853 crtc_state->dpll_hw_state.dpll = dpll;
7854 crtc_state->dpll_hw_state.fp0 = fp;
7855 if (has_reduced_clock)
7856 crtc_state->dpll_hw_state.fp1 = fp2;
7857 else
7858 crtc_state->dpll_hw_state.fp1 = fp;
7859
7860 pll = intel_get_shared_dpll(crtc, crtc_state);
7861 if (pll == NULL) {
7862 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7863 pipe_name(crtc->pipe));
7864 return -EINVAL;
7865 }
7866 }
7867
7868 if (is_lvds && has_reduced_clock)
7869 crtc->lowfreq_avail = true;
7870 else
7871 crtc->lowfreq_avail = false;
7872
7873 return 0;
7874 }
7875
7876 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7877 struct intel_link_m_n *m_n)
7878 {
7879 struct drm_device *dev = crtc->base.dev;
7880 struct drm_i915_private *dev_priv = dev->dev_private;
7881 enum pipe pipe = crtc->pipe;
7882
7883 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7884 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7885 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7886 & ~TU_SIZE_MASK;
7887 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7888 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7889 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7890 }
7891
7892 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7893 enum transcoder transcoder,
7894 struct intel_link_m_n *m_n,
7895 struct intel_link_m_n *m2_n2)
7896 {
7897 struct drm_device *dev = crtc->base.dev;
7898 struct drm_i915_private *dev_priv = dev->dev_private;
7899 enum pipe pipe = crtc->pipe;
7900
7901 if (INTEL_INFO(dev)->gen >= 5) {
7902 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7903 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7904 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7905 & ~TU_SIZE_MASK;
7906 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7907 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7908 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7909 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7910 * gen < 8) and if DRRS is supported (to make sure the
7911 * registers are not unnecessarily read).
7912 */
7913 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7914 crtc->config->has_drrs) {
7915 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7916 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7917 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7918 & ~TU_SIZE_MASK;
7919 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7920 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7921 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7922 }
7923 } else {
7924 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7925 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7926 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7927 & ~TU_SIZE_MASK;
7928 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7929 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7930 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7931 }
7932 }
7933
7934 void intel_dp_get_m_n(struct intel_crtc *crtc,
7935 struct intel_crtc_state *pipe_config)
7936 {
7937 if (pipe_config->has_pch_encoder)
7938 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7939 else
7940 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7941 &pipe_config->dp_m_n,
7942 &pipe_config->dp_m2_n2);
7943 }
7944
7945 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7946 struct intel_crtc_state *pipe_config)
7947 {
7948 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7949 &pipe_config->fdi_m_n, NULL);
7950 }
7951
7952 static void skylake_get_pfit_config(struct intel_crtc *crtc,
7953 struct intel_crtc_state *pipe_config)
7954 {
7955 struct drm_device *dev = crtc->base.dev;
7956 struct drm_i915_private *dev_priv = dev->dev_private;
7957 uint32_t tmp;
7958
7959 tmp = I915_READ(PS_CTL(crtc->pipe));
7960
7961 if (tmp & PS_ENABLE) {
7962 pipe_config->pch_pfit.enabled = true;
7963 pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe));
7964 pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe));
7965 }
7966 }
7967
7968 static void
7969 skylake_get_initial_plane_config(struct intel_crtc *crtc,
7970 struct intel_initial_plane_config *plane_config)
7971 {
7972 struct drm_device *dev = crtc->base.dev;
7973 struct drm_i915_private *dev_priv = dev->dev_private;
7974 u32 val, base, offset, stride_mult, tiling;
7975 int pipe = crtc->pipe;
7976 int fourcc, pixel_format;
7977 unsigned int aligned_height;
7978 struct drm_framebuffer *fb;
7979 struct intel_framebuffer *intel_fb;
7980
7981 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7982 if (!intel_fb) {
7983 DRM_DEBUG_KMS("failed to alloc fb\n");
7984 return;
7985 }
7986
7987 fb = &intel_fb->base;
7988
7989 val = I915_READ(PLANE_CTL(pipe, 0));
7990 if (!(val & PLANE_CTL_ENABLE))
7991 goto error;
7992
7993 pixel_format = val & PLANE_CTL_FORMAT_MASK;
7994 fourcc = skl_format_to_fourcc(pixel_format,
7995 val & PLANE_CTL_ORDER_RGBX,
7996 val & PLANE_CTL_ALPHA_MASK);
7997 fb->pixel_format = fourcc;
7998 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7999
8000 tiling = val & PLANE_CTL_TILED_MASK;
8001 switch (tiling) {
8002 case PLANE_CTL_TILED_LINEAR:
8003 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
8004 break;
8005 case PLANE_CTL_TILED_X:
8006 plane_config->tiling = I915_TILING_X;
8007 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8008 break;
8009 case PLANE_CTL_TILED_Y:
8010 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
8011 break;
8012 case PLANE_CTL_TILED_YF:
8013 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
8014 break;
8015 default:
8016 MISSING_CASE(tiling);
8017 goto error;
8018 }
8019
8020 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8021 plane_config->base = base;
8022
8023 offset = I915_READ(PLANE_OFFSET(pipe, 0));
8024
8025 val = I915_READ(PLANE_SIZE(pipe, 0));
8026 fb->height = ((val >> 16) & 0xfff) + 1;
8027 fb->width = ((val >> 0) & 0x1fff) + 1;
8028
8029 val = I915_READ(PLANE_STRIDE(pipe, 0));
8030 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
8031 fb->pixel_format);
8032 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8033
8034 aligned_height = intel_fb_align_height(dev, fb->height,
8035 fb->pixel_format,
8036 fb->modifier[0]);
8037
8038 plane_config->size = fb->pitches[0] * aligned_height;
8039
8040 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8041 pipe_name(pipe), fb->width, fb->height,
8042 fb->bits_per_pixel, base, fb->pitches[0],
8043 plane_config->size);
8044
8045 plane_config->fb = intel_fb;
8046 return;
8047
8048 error:
8049 kfree(fb);
8050 }
8051
8052 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8053 struct intel_crtc_state *pipe_config)
8054 {
8055 struct drm_device *dev = crtc->base.dev;
8056 struct drm_i915_private *dev_priv = dev->dev_private;
8057 uint32_t tmp;
8058
8059 tmp = I915_READ(PF_CTL(crtc->pipe));
8060
8061 if (tmp & PF_ENABLE) {
8062 pipe_config->pch_pfit.enabled = true;
8063 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8064 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8065
8066 /* We currently do not free assignements of panel fitters on
8067 * ivb/hsw (since we don't use the higher upscaling modes which
8068 * differentiates them) so just WARN about this case for now. */
8069 if (IS_GEN7(dev)) {
8070 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8071 PF_PIPE_SEL_IVB(crtc->pipe));
8072 }
8073 }
8074 }
8075
8076 static void
8077 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8078 struct intel_initial_plane_config *plane_config)
8079 {
8080 struct drm_device *dev = crtc->base.dev;
8081 struct drm_i915_private *dev_priv = dev->dev_private;
8082 u32 val, base, offset;
8083 int pipe = crtc->pipe;
8084 int fourcc, pixel_format;
8085 unsigned int aligned_height;
8086 struct drm_framebuffer *fb;
8087 struct intel_framebuffer *intel_fb;
8088
8089 val = I915_READ(DSPCNTR(pipe));
8090 if (!(val & DISPLAY_PLANE_ENABLE))
8091 return;
8092
8093 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8094 if (!intel_fb) {
8095 DRM_DEBUG_KMS("failed to alloc fb\n");
8096 return;
8097 }
8098
8099 fb = &intel_fb->base;
8100
8101 if (INTEL_INFO(dev)->gen >= 4) {
8102 if (val & DISPPLANE_TILED) {
8103 plane_config->tiling = I915_TILING_X;
8104 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8105 }
8106 }
8107
8108 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8109 fourcc = i9xx_format_to_fourcc(pixel_format);
8110 fb->pixel_format = fourcc;
8111 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8112
8113 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
8114 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
8115 offset = I915_READ(DSPOFFSET(pipe));
8116 } else {
8117 if (plane_config->tiling)
8118 offset = I915_READ(DSPTILEOFF(pipe));
8119 else
8120 offset = I915_READ(DSPLINOFF(pipe));
8121 }
8122 plane_config->base = base;
8123
8124 val = I915_READ(PIPESRC(pipe));
8125 fb->width = ((val >> 16) & 0xfff) + 1;
8126 fb->height = ((val >> 0) & 0xfff) + 1;
8127
8128 val = I915_READ(DSPSTRIDE(pipe));
8129 fb->pitches[0] = val & 0xffffffc0;
8130
8131 aligned_height = intel_fb_align_height(dev, fb->height,
8132 fb->pixel_format,
8133 fb->modifier[0]);
8134
8135 plane_config->size = fb->pitches[0] * aligned_height;
8136
8137 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8138 pipe_name(pipe), fb->width, fb->height,
8139 fb->bits_per_pixel, base, fb->pitches[0],
8140 plane_config->size);
8141
8142 plane_config->fb = intel_fb;
8143 }
8144
8145 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8146 struct intel_crtc_state *pipe_config)
8147 {
8148 struct drm_device *dev = crtc->base.dev;
8149 struct drm_i915_private *dev_priv = dev->dev_private;
8150 uint32_t tmp;
8151
8152 if (!intel_display_power_is_enabled(dev_priv,
8153 POWER_DOMAIN_PIPE(crtc->pipe)))
8154 return false;
8155
8156 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8157 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8158
8159 tmp = I915_READ(PIPECONF(crtc->pipe));
8160 if (!(tmp & PIPECONF_ENABLE))
8161 return false;
8162
8163 switch (tmp & PIPECONF_BPC_MASK) {
8164 case PIPECONF_6BPC:
8165 pipe_config->pipe_bpp = 18;
8166 break;
8167 case PIPECONF_8BPC:
8168 pipe_config->pipe_bpp = 24;
8169 break;
8170 case PIPECONF_10BPC:
8171 pipe_config->pipe_bpp = 30;
8172 break;
8173 case PIPECONF_12BPC:
8174 pipe_config->pipe_bpp = 36;
8175 break;
8176 default:
8177 break;
8178 }
8179
8180 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8181 pipe_config->limited_color_range = true;
8182
8183 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8184 struct intel_shared_dpll *pll;
8185
8186 pipe_config->has_pch_encoder = true;
8187
8188 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8189 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8190 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8191
8192 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8193
8194 if (HAS_PCH_IBX(dev_priv->dev)) {
8195 pipe_config->shared_dpll =
8196 (enum intel_dpll_id) crtc->pipe;
8197 } else {
8198 tmp = I915_READ(PCH_DPLL_SEL);
8199 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8200 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
8201 else
8202 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
8203 }
8204
8205 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8206
8207 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8208 &pipe_config->dpll_hw_state));
8209
8210 tmp = pipe_config->dpll_hw_state.dpll;
8211 pipe_config->pixel_multiplier =
8212 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8213 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8214
8215 ironlake_pch_clock_get(crtc, pipe_config);
8216 } else {
8217 pipe_config->pixel_multiplier = 1;
8218 }
8219
8220 intel_get_pipe_timings(crtc, pipe_config);
8221
8222 ironlake_get_pfit_config(crtc, pipe_config);
8223
8224 return true;
8225 }
8226
8227 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8228 {
8229 struct drm_device *dev = dev_priv->dev;
8230 struct intel_crtc *crtc;
8231
8232 for_each_intel_crtc(dev, crtc)
8233 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8234 pipe_name(crtc->pipe));
8235
8236 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8237 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8238 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8239 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8240 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
8241 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8242 "CPU PWM1 enabled\n");
8243 if (IS_HASWELL(dev))
8244 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8245 "CPU PWM2 enabled\n");
8246 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8247 "PCH PWM1 enabled\n");
8248 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8249 "Utility pin enabled\n");
8250 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8251
8252 /*
8253 * In theory we can still leave IRQs enabled, as long as only the HPD
8254 * interrupts remain enabled. We used to check for that, but since it's
8255 * gen-specific and since we only disable LCPLL after we fully disable
8256 * the interrupts, the check below should be enough.
8257 */
8258 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8259 }
8260
8261 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8262 {
8263 struct drm_device *dev = dev_priv->dev;
8264
8265 if (IS_HASWELL(dev))
8266 return I915_READ(D_COMP_HSW);
8267 else
8268 return I915_READ(D_COMP_BDW);
8269 }
8270
8271 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8272 {
8273 struct drm_device *dev = dev_priv->dev;
8274
8275 if (IS_HASWELL(dev)) {
8276 mutex_lock(&dev_priv->rps.hw_lock);
8277 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8278 val))
8279 DRM_ERROR("Failed to write to D_COMP\n");
8280 mutex_unlock(&dev_priv->rps.hw_lock);
8281 } else {
8282 I915_WRITE(D_COMP_BDW, val);
8283 POSTING_READ(D_COMP_BDW);
8284 }
8285 }
8286
8287 /*
8288 * This function implements pieces of two sequences from BSpec:
8289 * - Sequence for display software to disable LCPLL
8290 * - Sequence for display software to allow package C8+
8291 * The steps implemented here are just the steps that actually touch the LCPLL
8292 * register. Callers should take care of disabling all the display engine
8293 * functions, doing the mode unset, fixing interrupts, etc.
8294 */
8295 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8296 bool switch_to_fclk, bool allow_power_down)
8297 {
8298 uint32_t val;
8299
8300 assert_can_disable_lcpll(dev_priv);
8301
8302 val = I915_READ(LCPLL_CTL);
8303
8304 if (switch_to_fclk) {
8305 val |= LCPLL_CD_SOURCE_FCLK;
8306 I915_WRITE(LCPLL_CTL, val);
8307
8308 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
8309 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8310 DRM_ERROR("Switching to FCLK failed\n");
8311
8312 val = I915_READ(LCPLL_CTL);
8313 }
8314
8315 val |= LCPLL_PLL_DISABLE;
8316 I915_WRITE(LCPLL_CTL, val);
8317 POSTING_READ(LCPLL_CTL);
8318
8319 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
8320 DRM_ERROR("LCPLL still locked\n");
8321
8322 val = hsw_read_dcomp(dev_priv);
8323 val |= D_COMP_COMP_DISABLE;
8324 hsw_write_dcomp(dev_priv, val);
8325 ndelay(100);
8326
8327 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8328 1))
8329 DRM_ERROR("D_COMP RCOMP still in progress\n");
8330
8331 if (allow_power_down) {
8332 val = I915_READ(LCPLL_CTL);
8333 val |= LCPLL_POWER_DOWN_ALLOW;
8334 I915_WRITE(LCPLL_CTL, val);
8335 POSTING_READ(LCPLL_CTL);
8336 }
8337 }
8338
8339 /*
8340 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8341 * source.
8342 */
8343 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8344 {
8345 uint32_t val;
8346
8347 val = I915_READ(LCPLL_CTL);
8348
8349 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8350 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8351 return;
8352
8353 /*
8354 * Make sure we're not on PC8 state before disabling PC8, otherwise
8355 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8356 */
8357 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8358
8359 if (val & LCPLL_POWER_DOWN_ALLOW) {
8360 val &= ~LCPLL_POWER_DOWN_ALLOW;
8361 I915_WRITE(LCPLL_CTL, val);
8362 POSTING_READ(LCPLL_CTL);
8363 }
8364
8365 val = hsw_read_dcomp(dev_priv);
8366 val |= D_COMP_COMP_FORCE;
8367 val &= ~D_COMP_COMP_DISABLE;
8368 hsw_write_dcomp(dev_priv, val);
8369
8370 val = I915_READ(LCPLL_CTL);
8371 val &= ~LCPLL_PLL_DISABLE;
8372 I915_WRITE(LCPLL_CTL, val);
8373
8374 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
8375 DRM_ERROR("LCPLL not locked yet\n");
8376
8377 if (val & LCPLL_CD_SOURCE_FCLK) {
8378 val = I915_READ(LCPLL_CTL);
8379 val &= ~LCPLL_CD_SOURCE_FCLK;
8380 I915_WRITE(LCPLL_CTL, val);
8381
8382 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
8383 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8384 DRM_ERROR("Switching back to LCPLL failed\n");
8385 }
8386
8387 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8388 }
8389
8390 /*
8391 * Package states C8 and deeper are really deep PC states that can only be
8392 * reached when all the devices on the system allow it, so even if the graphics
8393 * device allows PC8+, it doesn't mean the system will actually get to these
8394 * states. Our driver only allows PC8+ when going into runtime PM.
8395 *
8396 * The requirements for PC8+ are that all the outputs are disabled, the power
8397 * well is disabled and most interrupts are disabled, and these are also
8398 * requirements for runtime PM. When these conditions are met, we manually do
8399 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8400 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8401 * hang the machine.
8402 *
8403 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8404 * the state of some registers, so when we come back from PC8+ we need to
8405 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8406 * need to take care of the registers kept by RC6. Notice that this happens even
8407 * if we don't put the device in PCI D3 state (which is what currently happens
8408 * because of the runtime PM support).
8409 *
8410 * For more, read "Display Sequences for Package C8" on the hardware
8411 * documentation.
8412 */
8413 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8414 {
8415 struct drm_device *dev = dev_priv->dev;
8416 uint32_t val;
8417
8418 DRM_DEBUG_KMS("Enabling package C8+\n");
8419
8420 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8421 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8422 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8423 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8424 }
8425
8426 lpt_disable_clkout_dp(dev);
8427 hsw_disable_lcpll(dev_priv, true, true);
8428 }
8429
8430 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8431 {
8432 struct drm_device *dev = dev_priv->dev;
8433 uint32_t val;
8434
8435 DRM_DEBUG_KMS("Disabling package C8+\n");
8436
8437 hsw_restore_lcpll(dev_priv);
8438 lpt_init_pch_refclk(dev);
8439
8440 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8441 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8442 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8443 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8444 }
8445
8446 intel_prepare_ddi(dev);
8447 }
8448
8449 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8450 struct intel_crtc_state *crtc_state)
8451 {
8452 if (!intel_ddi_pll_select(crtc, crtc_state))
8453 return -EINVAL;
8454
8455 crtc->lowfreq_avail = false;
8456
8457 return 0;
8458 }
8459
8460 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8461 enum port port,
8462 struct intel_crtc_state *pipe_config)
8463 {
8464 u32 temp, dpll_ctl1;
8465
8466 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8467 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
8468
8469 switch (pipe_config->ddi_pll_sel) {
8470 case SKL_DPLL0:
8471 /*
8472 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
8473 * of the shared DPLL framework and thus needs to be read out
8474 * separately
8475 */
8476 dpll_ctl1 = I915_READ(DPLL_CTRL1);
8477 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
8478 break;
8479 case SKL_DPLL1:
8480 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
8481 break;
8482 case SKL_DPLL2:
8483 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
8484 break;
8485 case SKL_DPLL3:
8486 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
8487 break;
8488 }
8489 }
8490
8491 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8492 enum port port,
8493 struct intel_crtc_state *pipe_config)
8494 {
8495 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8496
8497 switch (pipe_config->ddi_pll_sel) {
8498 case PORT_CLK_SEL_WRPLL1:
8499 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
8500 break;
8501 case PORT_CLK_SEL_WRPLL2:
8502 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
8503 break;
8504 }
8505 }
8506
8507 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
8508 struct intel_crtc_state *pipe_config)
8509 {
8510 struct drm_device *dev = crtc->base.dev;
8511 struct drm_i915_private *dev_priv = dev->dev_private;
8512 struct intel_shared_dpll *pll;
8513 enum port port;
8514 uint32_t tmp;
8515
8516 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
8517
8518 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8519
8520 if (IS_SKYLAKE(dev))
8521 skylake_get_ddi_pll(dev_priv, port, pipe_config);
8522 else
8523 haswell_get_ddi_pll(dev_priv, port, pipe_config);
8524
8525 if (pipe_config->shared_dpll >= 0) {
8526 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8527
8528 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8529 &pipe_config->dpll_hw_state));
8530 }
8531
8532 /*
8533 * Haswell has only FDI/PCH transcoder A. It is which is connected to
8534 * DDI E. So just check whether this pipe is wired to DDI E and whether
8535 * the PCH transcoder is on.
8536 */
8537 if (INTEL_INFO(dev)->gen < 9 &&
8538 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
8539 pipe_config->has_pch_encoder = true;
8540
8541 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8542 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8543 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8544
8545 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8546 }
8547 }
8548
8549 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
8550 struct intel_crtc_state *pipe_config)
8551 {
8552 struct drm_device *dev = crtc->base.dev;
8553 struct drm_i915_private *dev_priv = dev->dev_private;
8554 enum intel_display_power_domain pfit_domain;
8555 uint32_t tmp;
8556
8557 if (!intel_display_power_is_enabled(dev_priv,
8558 POWER_DOMAIN_PIPE(crtc->pipe)))
8559 return false;
8560
8561 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8562 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8563
8564 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8565 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8566 enum pipe trans_edp_pipe;
8567 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8568 default:
8569 WARN(1, "unknown pipe linked to edp transcoder\n");
8570 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8571 case TRANS_DDI_EDP_INPUT_A_ON:
8572 trans_edp_pipe = PIPE_A;
8573 break;
8574 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8575 trans_edp_pipe = PIPE_B;
8576 break;
8577 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8578 trans_edp_pipe = PIPE_C;
8579 break;
8580 }
8581
8582 if (trans_edp_pipe == crtc->pipe)
8583 pipe_config->cpu_transcoder = TRANSCODER_EDP;
8584 }
8585
8586 if (!intel_display_power_is_enabled(dev_priv,
8587 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
8588 return false;
8589
8590 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8591 if (!(tmp & PIPECONF_ENABLE))
8592 return false;
8593
8594 haswell_get_ddi_port_state(crtc, pipe_config);
8595
8596 intel_get_pipe_timings(crtc, pipe_config);
8597
8598 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
8599 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
8600 if (IS_SKYLAKE(dev))
8601 skylake_get_pfit_config(crtc, pipe_config);
8602 else
8603 ironlake_get_pfit_config(crtc, pipe_config);
8604 }
8605
8606 if (IS_HASWELL(dev))
8607 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8608 (I915_READ(IPS_CTL) & IPS_ENABLE);
8609
8610 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8611 pipe_config->pixel_multiplier =
8612 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8613 } else {
8614 pipe_config->pixel_multiplier = 1;
8615 }
8616
8617 return true;
8618 }
8619
8620 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8621 {
8622 struct drm_device *dev = crtc->dev;
8623 struct drm_i915_private *dev_priv = dev->dev_private;
8624 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8625 uint32_t cntl = 0, size = 0;
8626
8627 if (base) {
8628 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
8629 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
8630 unsigned int stride = roundup_pow_of_two(width) * 4;
8631
8632 switch (stride) {
8633 default:
8634 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8635 width, stride);
8636 stride = 256;
8637 /* fallthrough */
8638 case 256:
8639 case 512:
8640 case 1024:
8641 case 2048:
8642 break;
8643 }
8644
8645 cntl |= CURSOR_ENABLE |
8646 CURSOR_GAMMA_ENABLE |
8647 CURSOR_FORMAT_ARGB |
8648 CURSOR_STRIDE(stride);
8649
8650 size = (height << 12) | width;
8651 }
8652
8653 if (intel_crtc->cursor_cntl != 0 &&
8654 (intel_crtc->cursor_base != base ||
8655 intel_crtc->cursor_size != size ||
8656 intel_crtc->cursor_cntl != cntl)) {
8657 /* On these chipsets we can only modify the base/size/stride
8658 * whilst the cursor is disabled.
8659 */
8660 I915_WRITE(_CURACNTR, 0);
8661 POSTING_READ(_CURACNTR);
8662 intel_crtc->cursor_cntl = 0;
8663 }
8664
8665 if (intel_crtc->cursor_base != base) {
8666 I915_WRITE(_CURABASE, base);
8667 intel_crtc->cursor_base = base;
8668 }
8669
8670 if (intel_crtc->cursor_size != size) {
8671 I915_WRITE(CURSIZE, size);
8672 intel_crtc->cursor_size = size;
8673 }
8674
8675 if (intel_crtc->cursor_cntl != cntl) {
8676 I915_WRITE(_CURACNTR, cntl);
8677 POSTING_READ(_CURACNTR);
8678 intel_crtc->cursor_cntl = cntl;
8679 }
8680 }
8681
8682 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8683 {
8684 struct drm_device *dev = crtc->dev;
8685 struct drm_i915_private *dev_priv = dev->dev_private;
8686 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8687 int pipe = intel_crtc->pipe;
8688 uint32_t cntl;
8689
8690 cntl = 0;
8691 if (base) {
8692 cntl = MCURSOR_GAMMA_ENABLE;
8693 switch (intel_crtc->base.cursor->state->crtc_w) {
8694 case 64:
8695 cntl |= CURSOR_MODE_64_ARGB_AX;
8696 break;
8697 case 128:
8698 cntl |= CURSOR_MODE_128_ARGB_AX;
8699 break;
8700 case 256:
8701 cntl |= CURSOR_MODE_256_ARGB_AX;
8702 break;
8703 default:
8704 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
8705 return;
8706 }
8707 cntl |= pipe << 28; /* Connect to correct pipe */
8708
8709 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8710 cntl |= CURSOR_PIPE_CSC_ENABLE;
8711 }
8712
8713 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
8714 cntl |= CURSOR_ROTATE_180;
8715
8716 if (intel_crtc->cursor_cntl != cntl) {
8717 I915_WRITE(CURCNTR(pipe), cntl);
8718 POSTING_READ(CURCNTR(pipe));
8719 intel_crtc->cursor_cntl = cntl;
8720 }
8721
8722 /* and commit changes on next vblank */
8723 I915_WRITE(CURBASE(pipe), base);
8724 POSTING_READ(CURBASE(pipe));
8725
8726 intel_crtc->cursor_base = base;
8727 }
8728
8729 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8730 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8731 bool on)
8732 {
8733 struct drm_device *dev = crtc->dev;
8734 struct drm_i915_private *dev_priv = dev->dev_private;
8735 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8736 int pipe = intel_crtc->pipe;
8737 int x = crtc->cursor_x;
8738 int y = crtc->cursor_y;
8739 u32 base = 0, pos = 0;
8740
8741 if (on)
8742 base = intel_crtc->cursor_addr;
8743
8744 if (x >= intel_crtc->config->pipe_src_w)
8745 base = 0;
8746
8747 if (y >= intel_crtc->config->pipe_src_h)
8748 base = 0;
8749
8750 if (x < 0) {
8751 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
8752 base = 0;
8753
8754 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8755 x = -x;
8756 }
8757 pos |= x << CURSOR_X_SHIFT;
8758
8759 if (y < 0) {
8760 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
8761 base = 0;
8762
8763 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8764 y = -y;
8765 }
8766 pos |= y << CURSOR_Y_SHIFT;
8767
8768 if (base == 0 && intel_crtc->cursor_base == 0)
8769 return;
8770
8771 I915_WRITE(CURPOS(pipe), pos);
8772
8773 /* ILK+ do this automagically */
8774 if (HAS_GMCH_DISPLAY(dev) &&
8775 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
8776 base += (intel_crtc->base.cursor->state->crtc_h *
8777 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
8778 }
8779
8780 if (IS_845G(dev) || IS_I865G(dev))
8781 i845_update_cursor(crtc, base);
8782 else
8783 i9xx_update_cursor(crtc, base);
8784 }
8785
8786 static bool cursor_size_ok(struct drm_device *dev,
8787 uint32_t width, uint32_t height)
8788 {
8789 if (width == 0 || height == 0)
8790 return false;
8791
8792 /*
8793 * 845g/865g are special in that they are only limited by
8794 * the width of their cursors, the height is arbitrary up to
8795 * the precision of the register. Everything else requires
8796 * square cursors, limited to a few power-of-two sizes.
8797 */
8798 if (IS_845G(dev) || IS_I865G(dev)) {
8799 if ((width & 63) != 0)
8800 return false;
8801
8802 if (width > (IS_845G(dev) ? 64 : 512))
8803 return false;
8804
8805 if (height > 1023)
8806 return false;
8807 } else {
8808 switch (width | height) {
8809 case 256:
8810 case 128:
8811 if (IS_GEN2(dev))
8812 return false;
8813 case 64:
8814 break;
8815 default:
8816 return false;
8817 }
8818 }
8819
8820 return true;
8821 }
8822
8823 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8824 u16 *blue, uint32_t start, uint32_t size)
8825 {
8826 int end = (start + size > 256) ? 256 : start + size, i;
8827 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8828
8829 for (i = start; i < end; i++) {
8830 intel_crtc->lut_r[i] = red[i] >> 8;
8831 intel_crtc->lut_g[i] = green[i] >> 8;
8832 intel_crtc->lut_b[i] = blue[i] >> 8;
8833 }
8834
8835 intel_crtc_load_lut(crtc);
8836 }
8837
8838 /* VESA 640x480x72Hz mode to set on the pipe */
8839 static struct drm_display_mode load_detect_mode = {
8840 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8841 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8842 };
8843
8844 struct drm_framebuffer *
8845 __intel_framebuffer_create(struct drm_device *dev,
8846 struct drm_mode_fb_cmd2 *mode_cmd,
8847 struct drm_i915_gem_object *obj)
8848 {
8849 struct intel_framebuffer *intel_fb;
8850 int ret;
8851
8852 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8853 if (!intel_fb) {
8854 drm_gem_object_unreference(&obj->base);
8855 return ERR_PTR(-ENOMEM);
8856 }
8857
8858 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8859 if (ret)
8860 goto err;
8861
8862 return &intel_fb->base;
8863 err:
8864 drm_gem_object_unreference(&obj->base);
8865 kfree(intel_fb);
8866
8867 return ERR_PTR(ret);
8868 }
8869
8870 static struct drm_framebuffer *
8871 intel_framebuffer_create(struct drm_device *dev,
8872 struct drm_mode_fb_cmd2 *mode_cmd,
8873 struct drm_i915_gem_object *obj)
8874 {
8875 struct drm_framebuffer *fb;
8876 int ret;
8877
8878 ret = i915_mutex_lock_interruptible(dev);
8879 if (ret)
8880 return ERR_PTR(ret);
8881 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8882 mutex_unlock(&dev->struct_mutex);
8883
8884 return fb;
8885 }
8886
8887 static u32
8888 intel_framebuffer_pitch_for_width(int width, int bpp)
8889 {
8890 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8891 return ALIGN(pitch, 64);
8892 }
8893
8894 static u32
8895 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8896 {
8897 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8898 return PAGE_ALIGN(pitch * mode->vdisplay);
8899 }
8900
8901 static struct drm_framebuffer *
8902 intel_framebuffer_create_for_mode(struct drm_device *dev,
8903 struct drm_display_mode *mode,
8904 int depth, int bpp)
8905 {
8906 struct drm_i915_gem_object *obj;
8907 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8908
8909 obj = i915_gem_alloc_object(dev,
8910 intel_framebuffer_size_for_mode(mode, bpp));
8911 if (obj == NULL)
8912 return ERR_PTR(-ENOMEM);
8913
8914 mode_cmd.width = mode->hdisplay;
8915 mode_cmd.height = mode->vdisplay;
8916 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8917 bpp);
8918 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8919
8920 return intel_framebuffer_create(dev, &mode_cmd, obj);
8921 }
8922
8923 static struct drm_framebuffer *
8924 mode_fits_in_fbdev(struct drm_device *dev,
8925 struct drm_display_mode *mode)
8926 {
8927 #ifdef CONFIG_DRM_I915_FBDEV
8928 struct drm_i915_private *dev_priv = dev->dev_private;
8929 struct drm_i915_gem_object *obj;
8930 struct drm_framebuffer *fb;
8931
8932 if (!dev_priv->fbdev)
8933 return NULL;
8934
8935 if (!dev_priv->fbdev->fb)
8936 return NULL;
8937
8938 obj = dev_priv->fbdev->fb->obj;
8939 BUG_ON(!obj);
8940
8941 fb = &dev_priv->fbdev->fb->base;
8942 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8943 fb->bits_per_pixel))
8944 return NULL;
8945
8946 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8947 return NULL;
8948
8949 return fb;
8950 #else
8951 return NULL;
8952 #endif
8953 }
8954
8955 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8956 struct drm_display_mode *mode,
8957 struct intel_load_detect_pipe *old,
8958 struct drm_modeset_acquire_ctx *ctx)
8959 {
8960 struct intel_crtc *intel_crtc;
8961 struct intel_encoder *intel_encoder =
8962 intel_attached_encoder(connector);
8963 struct drm_crtc *possible_crtc;
8964 struct drm_encoder *encoder = &intel_encoder->base;
8965 struct drm_crtc *crtc = NULL;
8966 struct drm_device *dev = encoder->dev;
8967 struct drm_framebuffer *fb;
8968 struct drm_mode_config *config = &dev->mode_config;
8969 struct drm_atomic_state *state = NULL;
8970 struct drm_connector_state *connector_state;
8971 int ret, i = -1;
8972
8973 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8974 connector->base.id, connector->name,
8975 encoder->base.id, encoder->name);
8976
8977 retry:
8978 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8979 if (ret)
8980 goto fail_unlock;
8981
8982 /*
8983 * Algorithm gets a little messy:
8984 *
8985 * - if the connector already has an assigned crtc, use it (but make
8986 * sure it's on first)
8987 *
8988 * - try to find the first unused crtc that can drive this connector,
8989 * and use that if we find one
8990 */
8991
8992 /* See if we already have a CRTC for this connector */
8993 if (encoder->crtc) {
8994 crtc = encoder->crtc;
8995
8996 ret = drm_modeset_lock(&crtc->mutex, ctx);
8997 if (ret)
8998 goto fail_unlock;
8999 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9000 if (ret)
9001 goto fail_unlock;
9002
9003 old->dpms_mode = connector->dpms;
9004 old->load_detect_temp = false;
9005
9006 /* Make sure the crtc and connector are running */
9007 if (connector->dpms != DRM_MODE_DPMS_ON)
9008 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
9009
9010 return true;
9011 }
9012
9013 /* Find an unused one (if possible) */
9014 for_each_crtc(dev, possible_crtc) {
9015 i++;
9016 if (!(encoder->possible_crtcs & (1 << i)))
9017 continue;
9018 if (possible_crtc->state->enable)
9019 continue;
9020 /* This can occur when applying the pipe A quirk on resume. */
9021 if (to_intel_crtc(possible_crtc)->new_enabled)
9022 continue;
9023
9024 crtc = possible_crtc;
9025 break;
9026 }
9027
9028 /*
9029 * If we didn't find an unused CRTC, don't use any.
9030 */
9031 if (!crtc) {
9032 DRM_DEBUG_KMS("no pipe available for load-detect\n");
9033 goto fail_unlock;
9034 }
9035
9036 ret = drm_modeset_lock(&crtc->mutex, ctx);
9037 if (ret)
9038 goto fail_unlock;
9039 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9040 if (ret)
9041 goto fail_unlock;
9042 intel_encoder->new_crtc = to_intel_crtc(crtc);
9043 to_intel_connector(connector)->new_encoder = intel_encoder;
9044
9045 intel_crtc = to_intel_crtc(crtc);
9046 intel_crtc->new_enabled = true;
9047 intel_crtc->new_config = intel_crtc->config;
9048 old->dpms_mode = connector->dpms;
9049 old->load_detect_temp = true;
9050 old->release_fb = NULL;
9051
9052 state = drm_atomic_state_alloc(dev);
9053 if (!state)
9054 return false;
9055
9056 state->acquire_ctx = ctx;
9057
9058 connector_state = drm_atomic_get_connector_state(state, connector);
9059 if (IS_ERR(connector_state)) {
9060 ret = PTR_ERR(connector_state);
9061 goto fail;
9062 }
9063
9064 connector_state->crtc = crtc;
9065 connector_state->best_encoder = &intel_encoder->base;
9066
9067 if (!mode)
9068 mode = &load_detect_mode;
9069
9070 /* We need a framebuffer large enough to accommodate all accesses
9071 * that the plane may generate whilst we perform load detection.
9072 * We can not rely on the fbcon either being present (we get called
9073 * during its initialisation to detect all boot displays, or it may
9074 * not even exist) or that it is large enough to satisfy the
9075 * requested mode.
9076 */
9077 fb = mode_fits_in_fbdev(dev, mode);
9078 if (fb == NULL) {
9079 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
9080 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9081 old->release_fb = fb;
9082 } else
9083 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
9084 if (IS_ERR(fb)) {
9085 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
9086 goto fail;
9087 }
9088
9089 if (intel_set_mode(crtc, mode, 0, 0, fb, state)) {
9090 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
9091 if (old->release_fb)
9092 old->release_fb->funcs->destroy(old->release_fb);
9093 goto fail;
9094 }
9095 crtc->primary->crtc = crtc;
9096
9097 /* let the connector get through one full cycle before testing */
9098 intel_wait_for_vblank(dev, intel_crtc->pipe);
9099 return true;
9100
9101 fail:
9102 intel_crtc->new_enabled = crtc->state->enable;
9103 if (intel_crtc->new_enabled)
9104 intel_crtc->new_config = intel_crtc->config;
9105 else
9106 intel_crtc->new_config = NULL;
9107 fail_unlock:
9108 if (state) {
9109 drm_atomic_state_free(state);
9110 state = NULL;
9111 }
9112
9113 if (ret == -EDEADLK) {
9114 drm_modeset_backoff(ctx);
9115 goto retry;
9116 }
9117
9118 return false;
9119 }
9120
9121 void intel_release_load_detect_pipe(struct drm_connector *connector,
9122 struct intel_load_detect_pipe *old,
9123 struct drm_modeset_acquire_ctx *ctx)
9124 {
9125 struct drm_device *dev = connector->dev;
9126 struct intel_encoder *intel_encoder =
9127 intel_attached_encoder(connector);
9128 struct drm_encoder *encoder = &intel_encoder->base;
9129 struct drm_crtc *crtc = encoder->crtc;
9130 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9131 struct drm_atomic_state *state;
9132 struct drm_connector_state *connector_state;
9133
9134 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9135 connector->base.id, connector->name,
9136 encoder->base.id, encoder->name);
9137
9138 if (old->load_detect_temp) {
9139 state = drm_atomic_state_alloc(dev);
9140 if (!state)
9141 goto fail;
9142
9143 state->acquire_ctx = ctx;
9144
9145 connector_state = drm_atomic_get_connector_state(state, connector);
9146 if (IS_ERR(connector_state))
9147 goto fail;
9148
9149 to_intel_connector(connector)->new_encoder = NULL;
9150 intel_encoder->new_crtc = NULL;
9151 intel_crtc->new_enabled = false;
9152 intel_crtc->new_config = NULL;
9153
9154 connector_state->best_encoder = NULL;
9155 connector_state->crtc = NULL;
9156
9157 intel_set_mode(crtc, NULL, 0, 0, NULL, state);
9158
9159 drm_atomic_state_free(state);
9160
9161 if (old->release_fb) {
9162 drm_framebuffer_unregister_private(old->release_fb);
9163 drm_framebuffer_unreference(old->release_fb);
9164 }
9165
9166 return;
9167 }
9168
9169 /* Switch crtc and encoder back off if necessary */
9170 if (old->dpms_mode != DRM_MODE_DPMS_ON)
9171 connector->funcs->dpms(connector, old->dpms_mode);
9172
9173 return;
9174 fail:
9175 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
9176 drm_atomic_state_free(state);
9177 }
9178
9179 static int i9xx_pll_refclk(struct drm_device *dev,
9180 const struct intel_crtc_state *pipe_config)
9181 {
9182 struct drm_i915_private *dev_priv = dev->dev_private;
9183 u32 dpll = pipe_config->dpll_hw_state.dpll;
9184
9185 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
9186 return dev_priv->vbt.lvds_ssc_freq;
9187 else if (HAS_PCH_SPLIT(dev))
9188 return 120000;
9189 else if (!IS_GEN2(dev))
9190 return 96000;
9191 else
9192 return 48000;
9193 }
9194
9195 /* Returns the clock of the currently programmed mode of the given pipe. */
9196 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
9197 struct intel_crtc_state *pipe_config)
9198 {
9199 struct drm_device *dev = crtc->base.dev;
9200 struct drm_i915_private *dev_priv = dev->dev_private;
9201 int pipe = pipe_config->cpu_transcoder;
9202 u32 dpll = pipe_config->dpll_hw_state.dpll;
9203 u32 fp;
9204 intel_clock_t clock;
9205 int refclk = i9xx_pll_refclk(dev, pipe_config);
9206
9207 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
9208 fp = pipe_config->dpll_hw_state.fp0;
9209 else
9210 fp = pipe_config->dpll_hw_state.fp1;
9211
9212 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
9213 if (IS_PINEVIEW(dev)) {
9214 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
9215 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
9216 } else {
9217 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
9218 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
9219 }
9220
9221 if (!IS_GEN2(dev)) {
9222 if (IS_PINEVIEW(dev))
9223 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
9224 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
9225 else
9226 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
9227 DPLL_FPA01_P1_POST_DIV_SHIFT);
9228
9229 switch (dpll & DPLL_MODE_MASK) {
9230 case DPLLB_MODE_DAC_SERIAL:
9231 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
9232 5 : 10;
9233 break;
9234 case DPLLB_MODE_LVDS:
9235 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
9236 7 : 14;
9237 break;
9238 default:
9239 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
9240 "mode\n", (int)(dpll & DPLL_MODE_MASK));
9241 return;
9242 }
9243
9244 if (IS_PINEVIEW(dev))
9245 pineview_clock(refclk, &clock);
9246 else
9247 i9xx_clock(refclk, &clock);
9248 } else {
9249 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
9250 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
9251
9252 if (is_lvds) {
9253 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
9254 DPLL_FPA01_P1_POST_DIV_SHIFT);
9255
9256 if (lvds & LVDS_CLKB_POWER_UP)
9257 clock.p2 = 7;
9258 else
9259 clock.p2 = 14;
9260 } else {
9261 if (dpll & PLL_P1_DIVIDE_BY_TWO)
9262 clock.p1 = 2;
9263 else {
9264 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
9265 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
9266 }
9267 if (dpll & PLL_P2_DIVIDE_BY_4)
9268 clock.p2 = 4;
9269 else
9270 clock.p2 = 2;
9271 }
9272
9273 i9xx_clock(refclk, &clock);
9274 }
9275
9276 /*
9277 * This value includes pixel_multiplier. We will use
9278 * port_clock to compute adjusted_mode.crtc_clock in the
9279 * encoder's get_config() function.
9280 */
9281 pipe_config->port_clock = clock.dot;
9282 }
9283
9284 int intel_dotclock_calculate(int link_freq,
9285 const struct intel_link_m_n *m_n)
9286 {
9287 /*
9288 * The calculation for the data clock is:
9289 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
9290 * But we want to avoid losing precison if possible, so:
9291 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
9292 *
9293 * and the link clock is simpler:
9294 * link_clock = (m * link_clock) / n
9295 */
9296
9297 if (!m_n->link_n)
9298 return 0;
9299
9300 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
9301 }
9302
9303 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
9304 struct intel_crtc_state *pipe_config)
9305 {
9306 struct drm_device *dev = crtc->base.dev;
9307
9308 /* read out port_clock from the DPLL */
9309 i9xx_crtc_clock_get(crtc, pipe_config);
9310
9311 /*
9312 * This value does not include pixel_multiplier.
9313 * We will check that port_clock and adjusted_mode.crtc_clock
9314 * agree once we know their relationship in the encoder's
9315 * get_config() function.
9316 */
9317 pipe_config->base.adjusted_mode.crtc_clock =
9318 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
9319 &pipe_config->fdi_m_n);
9320 }
9321
9322 /** Returns the currently programmed mode of the given pipe. */
9323 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
9324 struct drm_crtc *crtc)
9325 {
9326 struct drm_i915_private *dev_priv = dev->dev_private;
9327 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9328 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9329 struct drm_display_mode *mode;
9330 struct intel_crtc_state pipe_config;
9331 int htot = I915_READ(HTOTAL(cpu_transcoder));
9332 int hsync = I915_READ(HSYNC(cpu_transcoder));
9333 int vtot = I915_READ(VTOTAL(cpu_transcoder));
9334 int vsync = I915_READ(VSYNC(cpu_transcoder));
9335 enum pipe pipe = intel_crtc->pipe;
9336
9337 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
9338 if (!mode)
9339 return NULL;
9340
9341 /*
9342 * Construct a pipe_config sufficient for getting the clock info
9343 * back out of crtc_clock_get.
9344 *
9345 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9346 * to use a real value here instead.
9347 */
9348 pipe_config.cpu_transcoder = (enum transcoder) pipe;
9349 pipe_config.pixel_multiplier = 1;
9350 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9351 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9352 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
9353 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
9354
9355 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
9356 mode->hdisplay = (htot & 0xffff) + 1;
9357 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9358 mode->hsync_start = (hsync & 0xffff) + 1;
9359 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9360 mode->vdisplay = (vtot & 0xffff) + 1;
9361 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9362 mode->vsync_start = (vsync & 0xffff) + 1;
9363 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9364
9365 drm_mode_set_name(mode);
9366
9367 return mode;
9368 }
9369
9370 static void intel_decrease_pllclock(struct drm_crtc *crtc)
9371 {
9372 struct drm_device *dev = crtc->dev;
9373 struct drm_i915_private *dev_priv = dev->dev_private;
9374 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9375
9376 if (!HAS_GMCH_DISPLAY(dev))
9377 return;
9378
9379 if (!dev_priv->lvds_downclock_avail)
9380 return;
9381
9382 /*
9383 * Since this is called by a timer, we should never get here in
9384 * the manual case.
9385 */
9386 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
9387 int pipe = intel_crtc->pipe;
9388 int dpll_reg = DPLL(pipe);
9389 int dpll;
9390
9391 DRM_DEBUG_DRIVER("downclocking LVDS\n");
9392
9393 assert_panel_unlocked(dev_priv, pipe);
9394
9395 dpll = I915_READ(dpll_reg);
9396 dpll |= DISPLAY_RATE_SELECT_FPA1;
9397 I915_WRITE(dpll_reg, dpll);
9398 intel_wait_for_vblank(dev, pipe);
9399 dpll = I915_READ(dpll_reg);
9400 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
9401 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
9402 }
9403
9404 }
9405
9406 void intel_mark_busy(struct drm_device *dev)
9407 {
9408 struct drm_i915_private *dev_priv = dev->dev_private;
9409
9410 if (dev_priv->mm.busy)
9411 return;
9412
9413 intel_runtime_pm_get(dev_priv);
9414 i915_update_gfx_val(dev_priv);
9415 if (INTEL_INFO(dev)->gen >= 6)
9416 gen6_rps_busy(dev_priv);
9417 dev_priv->mm.busy = true;
9418 }
9419
9420 void intel_mark_idle(struct drm_device *dev)
9421 {
9422 struct drm_i915_private *dev_priv = dev->dev_private;
9423 struct drm_crtc *crtc;
9424
9425 if (!dev_priv->mm.busy)
9426 return;
9427
9428 dev_priv->mm.busy = false;
9429
9430 for_each_crtc(dev, crtc) {
9431 if (!crtc->primary->fb)
9432 continue;
9433
9434 intel_decrease_pllclock(crtc);
9435 }
9436
9437 if (INTEL_INFO(dev)->gen >= 6)
9438 gen6_rps_idle(dev->dev_private);
9439
9440 intel_runtime_pm_put(dev_priv);
9441 }
9442
9443 static void intel_crtc_set_state(struct intel_crtc *crtc,
9444 struct intel_crtc_state *crtc_state)
9445 {
9446 kfree(crtc->config);
9447 crtc->config = crtc_state;
9448 crtc->base.state = &crtc_state->base;
9449 }
9450
9451 static void intel_crtc_destroy(struct drm_crtc *crtc)
9452 {
9453 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9454 struct drm_device *dev = crtc->dev;
9455 struct intel_unpin_work *work;
9456
9457 spin_lock_irq(&dev->event_lock);
9458 work = intel_crtc->unpin_work;
9459 intel_crtc->unpin_work = NULL;
9460 spin_unlock_irq(&dev->event_lock);
9461
9462 if (work) {
9463 cancel_work_sync(&work->work);
9464 kfree(work);
9465 }
9466
9467 intel_crtc_set_state(intel_crtc, NULL);
9468 drm_crtc_cleanup(crtc);
9469
9470 kfree(intel_crtc);
9471 }
9472
9473 static void intel_unpin_work_fn(struct work_struct *__work)
9474 {
9475 struct intel_unpin_work *work =
9476 container_of(__work, struct intel_unpin_work, work);
9477 struct drm_device *dev = work->crtc->dev;
9478 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9479
9480 mutex_lock(&dev->struct_mutex);
9481 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
9482 drm_gem_object_unreference(&work->pending_flip_obj->base);
9483
9484 intel_fbc_update(dev);
9485
9486 if (work->flip_queued_req)
9487 i915_gem_request_assign(&work->flip_queued_req, NULL);
9488 mutex_unlock(&dev->struct_mutex);
9489
9490 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9491 drm_framebuffer_unreference(work->old_fb);
9492
9493 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9494 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9495
9496 kfree(work);
9497 }
9498
9499 static void do_intel_finish_page_flip(struct drm_device *dev,
9500 struct drm_crtc *crtc)
9501 {
9502 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9503 struct intel_unpin_work *work;
9504 unsigned long flags;
9505
9506 /* Ignore early vblank irqs */
9507 if (intel_crtc == NULL)
9508 return;
9509
9510 /*
9511 * This is called both by irq handlers and the reset code (to complete
9512 * lost pageflips) so needs the full irqsave spinlocks.
9513 */
9514 spin_lock_irqsave(&dev->event_lock, flags);
9515 work = intel_crtc->unpin_work;
9516
9517 /* Ensure we don't miss a work->pending update ... */
9518 smp_rmb();
9519
9520 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9521 spin_unlock_irqrestore(&dev->event_lock, flags);
9522 return;
9523 }
9524
9525 page_flip_completed(intel_crtc);
9526
9527 spin_unlock_irqrestore(&dev->event_lock, flags);
9528 }
9529
9530 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9531 {
9532 struct drm_i915_private *dev_priv = dev->dev_private;
9533 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9534
9535 do_intel_finish_page_flip(dev, crtc);
9536 }
9537
9538 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9539 {
9540 struct drm_i915_private *dev_priv = dev->dev_private;
9541 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9542
9543 do_intel_finish_page_flip(dev, crtc);
9544 }
9545
9546 /* Is 'a' after or equal to 'b'? */
9547 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9548 {
9549 return !((a - b) & 0x80000000);
9550 }
9551
9552 static bool page_flip_finished(struct intel_crtc *crtc)
9553 {
9554 struct drm_device *dev = crtc->base.dev;
9555 struct drm_i915_private *dev_priv = dev->dev_private;
9556
9557 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
9558 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
9559 return true;
9560
9561 /*
9562 * The relevant registers doen't exist on pre-ctg.
9563 * As the flip done interrupt doesn't trigger for mmio
9564 * flips on gmch platforms, a flip count check isn't
9565 * really needed there. But since ctg has the registers,
9566 * include it in the check anyway.
9567 */
9568 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9569 return true;
9570
9571 /*
9572 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9573 * used the same base address. In that case the mmio flip might
9574 * have completed, but the CS hasn't even executed the flip yet.
9575 *
9576 * A flip count check isn't enough as the CS might have updated
9577 * the base address just after start of vblank, but before we
9578 * managed to process the interrupt. This means we'd complete the
9579 * CS flip too soon.
9580 *
9581 * Combining both checks should get us a good enough result. It may
9582 * still happen that the CS flip has been executed, but has not
9583 * yet actually completed. But in case the base address is the same
9584 * anyway, we don't really care.
9585 */
9586 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9587 crtc->unpin_work->gtt_offset &&
9588 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9589 crtc->unpin_work->flip_count);
9590 }
9591
9592 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9593 {
9594 struct drm_i915_private *dev_priv = dev->dev_private;
9595 struct intel_crtc *intel_crtc =
9596 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9597 unsigned long flags;
9598
9599
9600 /*
9601 * This is called both by irq handlers and the reset code (to complete
9602 * lost pageflips) so needs the full irqsave spinlocks.
9603 *
9604 * NB: An MMIO update of the plane base pointer will also
9605 * generate a page-flip completion irq, i.e. every modeset
9606 * is also accompanied by a spurious intel_prepare_page_flip().
9607 */
9608 spin_lock_irqsave(&dev->event_lock, flags);
9609 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9610 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9611 spin_unlock_irqrestore(&dev->event_lock, flags);
9612 }
9613
9614 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9615 {
9616 /* Ensure that the work item is consistent when activating it ... */
9617 smp_wmb();
9618 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9619 /* and that it is marked active as soon as the irq could fire. */
9620 smp_wmb();
9621 }
9622
9623 static int intel_gen2_queue_flip(struct drm_device *dev,
9624 struct drm_crtc *crtc,
9625 struct drm_framebuffer *fb,
9626 struct drm_i915_gem_object *obj,
9627 struct intel_engine_cs *ring,
9628 uint32_t flags)
9629 {
9630 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9631 u32 flip_mask;
9632 int ret;
9633
9634 ret = intel_ring_begin(ring, 6);
9635 if (ret)
9636 return ret;
9637
9638 /* Can't queue multiple flips, so wait for the previous
9639 * one to finish before executing the next.
9640 */
9641 if (intel_crtc->plane)
9642 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9643 else
9644 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9645 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9646 intel_ring_emit(ring, MI_NOOP);
9647 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9648 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9649 intel_ring_emit(ring, fb->pitches[0]);
9650 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9651 intel_ring_emit(ring, 0); /* aux display base address, unused */
9652
9653 intel_mark_page_flip_active(intel_crtc);
9654 __intel_ring_advance(ring);
9655 return 0;
9656 }
9657
9658 static int intel_gen3_queue_flip(struct drm_device *dev,
9659 struct drm_crtc *crtc,
9660 struct drm_framebuffer *fb,
9661 struct drm_i915_gem_object *obj,
9662 struct intel_engine_cs *ring,
9663 uint32_t flags)
9664 {
9665 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9666 u32 flip_mask;
9667 int ret;
9668
9669 ret = intel_ring_begin(ring, 6);
9670 if (ret)
9671 return ret;
9672
9673 if (intel_crtc->plane)
9674 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9675 else
9676 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9677 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9678 intel_ring_emit(ring, MI_NOOP);
9679 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9680 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9681 intel_ring_emit(ring, fb->pitches[0]);
9682 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9683 intel_ring_emit(ring, MI_NOOP);
9684
9685 intel_mark_page_flip_active(intel_crtc);
9686 __intel_ring_advance(ring);
9687 return 0;
9688 }
9689
9690 static int intel_gen4_queue_flip(struct drm_device *dev,
9691 struct drm_crtc *crtc,
9692 struct drm_framebuffer *fb,
9693 struct drm_i915_gem_object *obj,
9694 struct intel_engine_cs *ring,
9695 uint32_t flags)
9696 {
9697 struct drm_i915_private *dev_priv = dev->dev_private;
9698 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9699 uint32_t pf, pipesrc;
9700 int ret;
9701
9702 ret = intel_ring_begin(ring, 4);
9703 if (ret)
9704 return ret;
9705
9706 /* i965+ uses the linear or tiled offsets from the
9707 * Display Registers (which do not change across a page-flip)
9708 * so we need only reprogram the base address.
9709 */
9710 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9711 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9712 intel_ring_emit(ring, fb->pitches[0]);
9713 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9714 obj->tiling_mode);
9715
9716 /* XXX Enabling the panel-fitter across page-flip is so far
9717 * untested on non-native modes, so ignore it for now.
9718 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9719 */
9720 pf = 0;
9721 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9722 intel_ring_emit(ring, pf | pipesrc);
9723
9724 intel_mark_page_flip_active(intel_crtc);
9725 __intel_ring_advance(ring);
9726 return 0;
9727 }
9728
9729 static int intel_gen6_queue_flip(struct drm_device *dev,
9730 struct drm_crtc *crtc,
9731 struct drm_framebuffer *fb,
9732 struct drm_i915_gem_object *obj,
9733 struct intel_engine_cs *ring,
9734 uint32_t flags)
9735 {
9736 struct drm_i915_private *dev_priv = dev->dev_private;
9737 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9738 uint32_t pf, pipesrc;
9739 int ret;
9740
9741 ret = intel_ring_begin(ring, 4);
9742 if (ret)
9743 return ret;
9744
9745 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9746 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9747 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9748 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9749
9750 /* Contrary to the suggestions in the documentation,
9751 * "Enable Panel Fitter" does not seem to be required when page
9752 * flipping with a non-native mode, and worse causes a normal
9753 * modeset to fail.
9754 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9755 */
9756 pf = 0;
9757 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9758 intel_ring_emit(ring, pf | pipesrc);
9759
9760 intel_mark_page_flip_active(intel_crtc);
9761 __intel_ring_advance(ring);
9762 return 0;
9763 }
9764
9765 static int intel_gen7_queue_flip(struct drm_device *dev,
9766 struct drm_crtc *crtc,
9767 struct drm_framebuffer *fb,
9768 struct drm_i915_gem_object *obj,
9769 struct intel_engine_cs *ring,
9770 uint32_t flags)
9771 {
9772 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9773 uint32_t plane_bit = 0;
9774 int len, ret;
9775
9776 switch (intel_crtc->plane) {
9777 case PLANE_A:
9778 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9779 break;
9780 case PLANE_B:
9781 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9782 break;
9783 case PLANE_C:
9784 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9785 break;
9786 default:
9787 WARN_ONCE(1, "unknown plane in flip command\n");
9788 return -ENODEV;
9789 }
9790
9791 len = 4;
9792 if (ring->id == RCS) {
9793 len += 6;
9794 /*
9795 * On Gen 8, SRM is now taking an extra dword to accommodate
9796 * 48bits addresses, and we need a NOOP for the batch size to
9797 * stay even.
9798 */
9799 if (IS_GEN8(dev))
9800 len += 2;
9801 }
9802
9803 /*
9804 * BSpec MI_DISPLAY_FLIP for IVB:
9805 * "The full packet must be contained within the same cache line."
9806 *
9807 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9808 * cacheline, if we ever start emitting more commands before
9809 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9810 * then do the cacheline alignment, and finally emit the
9811 * MI_DISPLAY_FLIP.
9812 */
9813 ret = intel_ring_cacheline_align(ring);
9814 if (ret)
9815 return ret;
9816
9817 ret = intel_ring_begin(ring, len);
9818 if (ret)
9819 return ret;
9820
9821 /* Unmask the flip-done completion message. Note that the bspec says that
9822 * we should do this for both the BCS and RCS, and that we must not unmask
9823 * more than one flip event at any time (or ensure that one flip message
9824 * can be sent by waiting for flip-done prior to queueing new flips).
9825 * Experimentation says that BCS works despite DERRMR masking all
9826 * flip-done completion events and that unmasking all planes at once
9827 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9828 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9829 */
9830 if (ring->id == RCS) {
9831 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9832 intel_ring_emit(ring, DERRMR);
9833 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9834 DERRMR_PIPEB_PRI_FLIP_DONE |
9835 DERRMR_PIPEC_PRI_FLIP_DONE));
9836 if (IS_GEN8(dev))
9837 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9838 MI_SRM_LRM_GLOBAL_GTT);
9839 else
9840 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9841 MI_SRM_LRM_GLOBAL_GTT);
9842 intel_ring_emit(ring, DERRMR);
9843 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9844 if (IS_GEN8(dev)) {
9845 intel_ring_emit(ring, 0);
9846 intel_ring_emit(ring, MI_NOOP);
9847 }
9848 }
9849
9850 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9851 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9852 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9853 intel_ring_emit(ring, (MI_NOOP));
9854
9855 intel_mark_page_flip_active(intel_crtc);
9856 __intel_ring_advance(ring);
9857 return 0;
9858 }
9859
9860 static bool use_mmio_flip(struct intel_engine_cs *ring,
9861 struct drm_i915_gem_object *obj)
9862 {
9863 /*
9864 * This is not being used for older platforms, because
9865 * non-availability of flip done interrupt forces us to use
9866 * CS flips. Older platforms derive flip done using some clever
9867 * tricks involving the flip_pending status bits and vblank irqs.
9868 * So using MMIO flips there would disrupt this mechanism.
9869 */
9870
9871 if (ring == NULL)
9872 return true;
9873
9874 if (INTEL_INFO(ring->dev)->gen < 5)
9875 return false;
9876
9877 if (i915.use_mmio_flip < 0)
9878 return false;
9879 else if (i915.use_mmio_flip > 0)
9880 return true;
9881 else if (i915.enable_execlists)
9882 return true;
9883 else
9884 return ring != i915_gem_request_get_ring(obj->last_read_req);
9885 }
9886
9887 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
9888 {
9889 struct drm_device *dev = intel_crtc->base.dev;
9890 struct drm_i915_private *dev_priv = dev->dev_private;
9891 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
9892 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9893 struct drm_i915_gem_object *obj = intel_fb->obj;
9894 const enum pipe pipe = intel_crtc->pipe;
9895 u32 ctl, stride;
9896
9897 ctl = I915_READ(PLANE_CTL(pipe, 0));
9898 ctl &= ~PLANE_CTL_TILED_MASK;
9899 if (obj->tiling_mode == I915_TILING_X)
9900 ctl |= PLANE_CTL_TILED_X;
9901
9902 /*
9903 * The stride is either expressed as a multiple of 64 bytes chunks for
9904 * linear buffers or in number of tiles for tiled buffers.
9905 */
9906 stride = fb->pitches[0] >> 6;
9907 if (obj->tiling_mode == I915_TILING_X)
9908 stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
9909
9910 /*
9911 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
9912 * PLANE_SURF updates, the update is then guaranteed to be atomic.
9913 */
9914 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
9915 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
9916
9917 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
9918 POSTING_READ(PLANE_SURF(pipe, 0));
9919 }
9920
9921 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
9922 {
9923 struct drm_device *dev = intel_crtc->base.dev;
9924 struct drm_i915_private *dev_priv = dev->dev_private;
9925 struct intel_framebuffer *intel_fb =
9926 to_intel_framebuffer(intel_crtc->base.primary->fb);
9927 struct drm_i915_gem_object *obj = intel_fb->obj;
9928 u32 dspcntr;
9929 u32 reg;
9930
9931 reg = DSPCNTR(intel_crtc->plane);
9932 dspcntr = I915_READ(reg);
9933
9934 if (obj->tiling_mode != I915_TILING_NONE)
9935 dspcntr |= DISPPLANE_TILED;
9936 else
9937 dspcntr &= ~DISPPLANE_TILED;
9938
9939 I915_WRITE(reg, dspcntr);
9940
9941 I915_WRITE(DSPSURF(intel_crtc->plane),
9942 intel_crtc->unpin_work->gtt_offset);
9943 POSTING_READ(DSPSURF(intel_crtc->plane));
9944
9945 }
9946
9947 /*
9948 * XXX: This is the temporary way to update the plane registers until we get
9949 * around to using the usual plane update functions for MMIO flips
9950 */
9951 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9952 {
9953 struct drm_device *dev = intel_crtc->base.dev;
9954 bool atomic_update;
9955 u32 start_vbl_count;
9956
9957 intel_mark_page_flip_active(intel_crtc);
9958
9959 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
9960
9961 if (INTEL_INFO(dev)->gen >= 9)
9962 skl_do_mmio_flip(intel_crtc);
9963 else
9964 /* use_mmio_flip() retricts MMIO flips to ilk+ */
9965 ilk_do_mmio_flip(intel_crtc);
9966
9967 if (atomic_update)
9968 intel_pipe_update_end(intel_crtc, start_vbl_count);
9969 }
9970
9971 static void intel_mmio_flip_work_func(struct work_struct *work)
9972 {
9973 struct intel_crtc *crtc =
9974 container_of(work, struct intel_crtc, mmio_flip.work);
9975 struct intel_mmio_flip *mmio_flip;
9976
9977 mmio_flip = &crtc->mmio_flip;
9978 if (mmio_flip->req)
9979 WARN_ON(__i915_wait_request(mmio_flip->req,
9980 crtc->reset_counter,
9981 false, NULL, NULL) != 0);
9982
9983 intel_do_mmio_flip(crtc);
9984 if (mmio_flip->req) {
9985 mutex_lock(&crtc->base.dev->struct_mutex);
9986 i915_gem_request_assign(&mmio_flip->req, NULL);
9987 mutex_unlock(&crtc->base.dev->struct_mutex);
9988 }
9989 }
9990
9991 static int intel_queue_mmio_flip(struct drm_device *dev,
9992 struct drm_crtc *crtc,
9993 struct drm_framebuffer *fb,
9994 struct drm_i915_gem_object *obj,
9995 struct intel_engine_cs *ring,
9996 uint32_t flags)
9997 {
9998 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9999
10000 i915_gem_request_assign(&intel_crtc->mmio_flip.req,
10001 obj->last_write_req);
10002
10003 schedule_work(&intel_crtc->mmio_flip.work);
10004
10005 return 0;
10006 }
10007
10008 static int intel_default_queue_flip(struct drm_device *dev,
10009 struct drm_crtc *crtc,
10010 struct drm_framebuffer *fb,
10011 struct drm_i915_gem_object *obj,
10012 struct intel_engine_cs *ring,
10013 uint32_t flags)
10014 {
10015 return -ENODEV;
10016 }
10017
10018 static bool __intel_pageflip_stall_check(struct drm_device *dev,
10019 struct drm_crtc *crtc)
10020 {
10021 struct drm_i915_private *dev_priv = dev->dev_private;
10022 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10023 struct intel_unpin_work *work = intel_crtc->unpin_work;
10024 u32 addr;
10025
10026 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
10027 return true;
10028
10029 if (!work->enable_stall_check)
10030 return false;
10031
10032 if (work->flip_ready_vblank == 0) {
10033 if (work->flip_queued_req &&
10034 !i915_gem_request_completed(work->flip_queued_req, true))
10035 return false;
10036
10037 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
10038 }
10039
10040 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
10041 return false;
10042
10043 /* Potential stall - if we see that the flip has happened,
10044 * assume a missed interrupt. */
10045 if (INTEL_INFO(dev)->gen >= 4)
10046 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
10047 else
10048 addr = I915_READ(DSPADDR(intel_crtc->plane));
10049
10050 /* There is a potential issue here with a false positive after a flip
10051 * to the same address. We could address this by checking for a
10052 * non-incrementing frame counter.
10053 */
10054 return addr == work->gtt_offset;
10055 }
10056
10057 void intel_check_page_flip(struct drm_device *dev, int pipe)
10058 {
10059 struct drm_i915_private *dev_priv = dev->dev_private;
10060 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10061 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10062
10063 WARN_ON(!in_interrupt());
10064
10065 if (crtc == NULL)
10066 return;
10067
10068 spin_lock(&dev->event_lock);
10069 if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
10070 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
10071 intel_crtc->unpin_work->flip_queued_vblank,
10072 drm_vblank_count(dev, pipe));
10073 page_flip_completed(intel_crtc);
10074 }
10075 spin_unlock(&dev->event_lock);
10076 }
10077
10078 static int intel_crtc_page_flip(struct drm_crtc *crtc,
10079 struct drm_framebuffer *fb,
10080 struct drm_pending_vblank_event *event,
10081 uint32_t page_flip_flags)
10082 {
10083 struct drm_device *dev = crtc->dev;
10084 struct drm_i915_private *dev_priv = dev->dev_private;
10085 struct drm_framebuffer *old_fb = crtc->primary->fb;
10086 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10087 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10088 struct drm_plane *primary = crtc->primary;
10089 enum pipe pipe = intel_crtc->pipe;
10090 struct intel_unpin_work *work;
10091 struct intel_engine_cs *ring;
10092 int ret;
10093
10094 /*
10095 * drm_mode_page_flip_ioctl() should already catch this, but double
10096 * check to be safe. In the future we may enable pageflipping from
10097 * a disabled primary plane.
10098 */
10099 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
10100 return -EBUSY;
10101
10102 /* Can't change pixel format via MI display flips. */
10103 if (fb->pixel_format != crtc->primary->fb->pixel_format)
10104 return -EINVAL;
10105
10106 /*
10107 * TILEOFF/LINOFF registers can't be changed via MI display flips.
10108 * Note that pitch changes could also affect these register.
10109 */
10110 if (INTEL_INFO(dev)->gen > 3 &&
10111 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
10112 fb->pitches[0] != crtc->primary->fb->pitches[0]))
10113 return -EINVAL;
10114
10115 if (i915_terminally_wedged(&dev_priv->gpu_error))
10116 goto out_hang;
10117
10118 work = kzalloc(sizeof(*work), GFP_KERNEL);
10119 if (work == NULL)
10120 return -ENOMEM;
10121
10122 work->event = event;
10123 work->crtc = crtc;
10124 work->old_fb = old_fb;
10125 INIT_WORK(&work->work, intel_unpin_work_fn);
10126
10127 ret = drm_crtc_vblank_get(crtc);
10128 if (ret)
10129 goto free_work;
10130
10131 /* We borrow the event spin lock for protecting unpin_work */
10132 spin_lock_irq(&dev->event_lock);
10133 if (intel_crtc->unpin_work) {
10134 /* Before declaring the flip queue wedged, check if
10135 * the hardware completed the operation behind our backs.
10136 */
10137 if (__intel_pageflip_stall_check(dev, crtc)) {
10138 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10139 page_flip_completed(intel_crtc);
10140 } else {
10141 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
10142 spin_unlock_irq(&dev->event_lock);
10143
10144 drm_crtc_vblank_put(crtc);
10145 kfree(work);
10146 return -EBUSY;
10147 }
10148 }
10149 intel_crtc->unpin_work = work;
10150 spin_unlock_irq(&dev->event_lock);
10151
10152 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
10153 flush_workqueue(dev_priv->wq);
10154
10155 /* Reference the objects for the scheduled work. */
10156 drm_framebuffer_reference(work->old_fb);
10157 drm_gem_object_reference(&obj->base);
10158
10159 crtc->primary->fb = fb;
10160 update_state_fb(crtc->primary);
10161
10162 work->pending_flip_obj = obj;
10163
10164 ret = i915_mutex_lock_interruptible(dev);
10165 if (ret)
10166 goto cleanup;
10167
10168 atomic_inc(&intel_crtc->unpin_work_count);
10169 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
10170
10171 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
10172 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
10173
10174 if (IS_VALLEYVIEW(dev)) {
10175 ring = &dev_priv->ring[BCS];
10176 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
10177 /* vlv: DISPLAY_FLIP fails to change tiling */
10178 ring = NULL;
10179 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
10180 ring = &dev_priv->ring[BCS];
10181 } else if (INTEL_INFO(dev)->gen >= 7) {
10182 ring = i915_gem_request_get_ring(obj->last_read_req);
10183 if (ring == NULL || ring->id != RCS)
10184 ring = &dev_priv->ring[BCS];
10185 } else {
10186 ring = &dev_priv->ring[RCS];
10187 }
10188
10189 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
10190 crtc->primary->state, ring);
10191 if (ret)
10192 goto cleanup_pending;
10193
10194 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
10195 + intel_crtc->dspaddr_offset;
10196
10197 if (use_mmio_flip(ring, obj)) {
10198 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
10199 page_flip_flags);
10200 if (ret)
10201 goto cleanup_unpin;
10202
10203 i915_gem_request_assign(&work->flip_queued_req,
10204 obj->last_write_req);
10205 } else {
10206 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
10207 page_flip_flags);
10208 if (ret)
10209 goto cleanup_unpin;
10210
10211 i915_gem_request_assign(&work->flip_queued_req,
10212 intel_ring_get_request(ring));
10213 }
10214
10215 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
10216 work->enable_stall_check = true;
10217
10218 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
10219 INTEL_FRONTBUFFER_PRIMARY(pipe));
10220
10221 intel_fbc_disable(dev);
10222 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
10223 mutex_unlock(&dev->struct_mutex);
10224
10225 trace_i915_flip_request(intel_crtc->plane, obj);
10226
10227 return 0;
10228
10229 cleanup_unpin:
10230 intel_unpin_fb_obj(fb, crtc->primary->state);
10231 cleanup_pending:
10232 atomic_dec(&intel_crtc->unpin_work_count);
10233 mutex_unlock(&dev->struct_mutex);
10234 cleanup:
10235 crtc->primary->fb = old_fb;
10236 update_state_fb(crtc->primary);
10237
10238 drm_gem_object_unreference_unlocked(&obj->base);
10239 drm_framebuffer_unreference(work->old_fb);
10240
10241 spin_lock_irq(&dev->event_lock);
10242 intel_crtc->unpin_work = NULL;
10243 spin_unlock_irq(&dev->event_lock);
10244
10245 drm_crtc_vblank_put(crtc);
10246 free_work:
10247 kfree(work);
10248
10249 if (ret == -EIO) {
10250 out_hang:
10251 ret = intel_plane_restore(primary);
10252 if (ret == 0 && event) {
10253 spin_lock_irq(&dev->event_lock);
10254 drm_send_vblank_event(dev, pipe, event);
10255 spin_unlock_irq(&dev->event_lock);
10256 }
10257 }
10258 return ret;
10259 }
10260
10261 static struct drm_crtc_helper_funcs intel_helper_funcs = {
10262 .mode_set_base_atomic = intel_pipe_set_base_atomic,
10263 .load_lut = intel_crtc_load_lut,
10264 .atomic_begin = intel_begin_crtc_commit,
10265 .atomic_flush = intel_finish_crtc_commit,
10266 };
10267
10268 /**
10269 * intel_modeset_update_staged_output_state
10270 *
10271 * Updates the staged output configuration state, e.g. after we've read out the
10272 * current hw state.
10273 */
10274 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
10275 {
10276 struct intel_crtc *crtc;
10277 struct intel_encoder *encoder;
10278 struct intel_connector *connector;
10279
10280 for_each_intel_connector(dev, connector) {
10281 connector->new_encoder =
10282 to_intel_encoder(connector->base.encoder);
10283 }
10284
10285 for_each_intel_encoder(dev, encoder) {
10286 encoder->new_crtc =
10287 to_intel_crtc(encoder->base.crtc);
10288 }
10289
10290 for_each_intel_crtc(dev, crtc) {
10291 crtc->new_enabled = crtc->base.state->enable;
10292
10293 if (crtc->new_enabled)
10294 crtc->new_config = crtc->config;
10295 else
10296 crtc->new_config = NULL;
10297 }
10298 }
10299
10300 /* Transitional helper to copy current connector/encoder state to
10301 * connector->state. This is needed so that code that is partially
10302 * converted to atomic does the right thing.
10303 */
10304 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
10305 {
10306 struct intel_connector *connector;
10307
10308 for_each_intel_connector(dev, connector) {
10309 if (connector->base.encoder) {
10310 connector->base.state->best_encoder =
10311 connector->base.encoder;
10312 connector->base.state->crtc =
10313 connector->base.encoder->crtc;
10314 } else {
10315 connector->base.state->best_encoder = NULL;
10316 connector->base.state->crtc = NULL;
10317 }
10318 }
10319 }
10320
10321 /**
10322 * intel_modeset_commit_output_state
10323 *
10324 * This function copies the stage display pipe configuration to the real one.
10325 */
10326 static void intel_modeset_commit_output_state(struct drm_device *dev)
10327 {
10328 struct intel_crtc *crtc;
10329 struct intel_encoder *encoder;
10330 struct intel_connector *connector;
10331
10332 for_each_intel_connector(dev, connector) {
10333 connector->base.encoder = &connector->new_encoder->base;
10334 }
10335
10336 for_each_intel_encoder(dev, encoder) {
10337 encoder->base.crtc = &encoder->new_crtc->base;
10338 }
10339
10340 for_each_intel_crtc(dev, crtc) {
10341 crtc->base.state->enable = crtc->new_enabled;
10342 crtc->base.enabled = crtc->new_enabled;
10343 }
10344
10345 intel_modeset_update_connector_atomic_state(dev);
10346 }
10347
10348 static void
10349 connected_sink_compute_bpp(struct intel_connector *connector,
10350 struct intel_crtc_state *pipe_config)
10351 {
10352 int bpp = pipe_config->pipe_bpp;
10353
10354 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10355 connector->base.base.id,
10356 connector->base.name);
10357
10358 /* Don't use an invalid EDID bpc value */
10359 if (connector->base.display_info.bpc &&
10360 connector->base.display_info.bpc * 3 < bpp) {
10361 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10362 bpp, connector->base.display_info.bpc*3);
10363 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
10364 }
10365
10366 /* Clamp bpp to 8 on screens without EDID 1.4 */
10367 if (connector->base.display_info.bpc == 0 && bpp > 24) {
10368 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10369 bpp);
10370 pipe_config->pipe_bpp = 24;
10371 }
10372 }
10373
10374 static int
10375 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10376 struct drm_framebuffer *fb,
10377 struct intel_crtc_state *pipe_config)
10378 {
10379 struct drm_device *dev = crtc->base.dev;
10380 struct drm_atomic_state *state;
10381 struct intel_connector *connector;
10382 int bpp, i;
10383
10384 switch (fb->pixel_format) {
10385 case DRM_FORMAT_C8:
10386 bpp = 8*3; /* since we go through a colormap */
10387 break;
10388 case DRM_FORMAT_XRGB1555:
10389 case DRM_FORMAT_ARGB1555:
10390 /* checked in intel_framebuffer_init already */
10391 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10392 return -EINVAL;
10393 case DRM_FORMAT_RGB565:
10394 bpp = 6*3; /* min is 18bpp */
10395 break;
10396 case DRM_FORMAT_XBGR8888:
10397 case DRM_FORMAT_ABGR8888:
10398 /* checked in intel_framebuffer_init already */
10399 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10400 return -EINVAL;
10401 case DRM_FORMAT_XRGB8888:
10402 case DRM_FORMAT_ARGB8888:
10403 bpp = 8*3;
10404 break;
10405 case DRM_FORMAT_XRGB2101010:
10406 case DRM_FORMAT_ARGB2101010:
10407 case DRM_FORMAT_XBGR2101010:
10408 case DRM_FORMAT_ABGR2101010:
10409 /* checked in intel_framebuffer_init already */
10410 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10411 return -EINVAL;
10412 bpp = 10*3;
10413 break;
10414 /* TODO: gen4+ supports 16 bpc floating point, too. */
10415 default:
10416 DRM_DEBUG_KMS("unsupported depth\n");
10417 return -EINVAL;
10418 }
10419
10420 pipe_config->pipe_bpp = bpp;
10421
10422 state = pipe_config->base.state;
10423
10424 /* Clamp display bpp to EDID value */
10425 for (i = 0; i < state->num_connector; i++) {
10426 if (!state->connectors[i])
10427 continue;
10428
10429 connector = to_intel_connector(state->connectors[i]);
10430 if (state->connector_states[i]->crtc != &crtc->base)
10431 continue;
10432
10433 connected_sink_compute_bpp(connector, pipe_config);
10434 }
10435
10436 return bpp;
10437 }
10438
10439 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10440 {
10441 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10442 "type: 0x%x flags: 0x%x\n",
10443 mode->crtc_clock,
10444 mode->crtc_hdisplay, mode->crtc_hsync_start,
10445 mode->crtc_hsync_end, mode->crtc_htotal,
10446 mode->crtc_vdisplay, mode->crtc_vsync_start,
10447 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10448 }
10449
10450 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10451 struct intel_crtc_state *pipe_config,
10452 const char *context)
10453 {
10454 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10455 context, pipe_name(crtc->pipe));
10456
10457 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10458 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10459 pipe_config->pipe_bpp, pipe_config->dither);
10460 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10461 pipe_config->has_pch_encoder,
10462 pipe_config->fdi_lanes,
10463 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10464 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10465 pipe_config->fdi_m_n.tu);
10466 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10467 pipe_config->has_dp_encoder,
10468 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10469 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10470 pipe_config->dp_m_n.tu);
10471
10472 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10473 pipe_config->has_dp_encoder,
10474 pipe_config->dp_m2_n2.gmch_m,
10475 pipe_config->dp_m2_n2.gmch_n,
10476 pipe_config->dp_m2_n2.link_m,
10477 pipe_config->dp_m2_n2.link_n,
10478 pipe_config->dp_m2_n2.tu);
10479
10480 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10481 pipe_config->has_audio,
10482 pipe_config->has_infoframe);
10483
10484 DRM_DEBUG_KMS("requested mode:\n");
10485 drm_mode_debug_printmodeline(&pipe_config->base.mode);
10486 DRM_DEBUG_KMS("adjusted mode:\n");
10487 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10488 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10489 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10490 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10491 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10492 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10493 pipe_config->gmch_pfit.control,
10494 pipe_config->gmch_pfit.pgm_ratios,
10495 pipe_config->gmch_pfit.lvds_border_bits);
10496 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10497 pipe_config->pch_pfit.pos,
10498 pipe_config->pch_pfit.size,
10499 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10500 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10501 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10502 }
10503
10504 static bool encoders_cloneable(const struct intel_encoder *a,
10505 const struct intel_encoder *b)
10506 {
10507 /* masks could be asymmetric, so check both ways */
10508 return a == b || (a->cloneable & (1 << b->type) &&
10509 b->cloneable & (1 << a->type));
10510 }
10511
10512 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10513 struct intel_encoder *encoder)
10514 {
10515 struct drm_device *dev = crtc->base.dev;
10516 struct intel_encoder *source_encoder;
10517
10518 for_each_intel_encoder(dev, source_encoder) {
10519 if (source_encoder->new_crtc != crtc)
10520 continue;
10521
10522 if (!encoders_cloneable(encoder, source_encoder))
10523 return false;
10524 }
10525
10526 return true;
10527 }
10528
10529 static bool check_encoder_cloning(struct intel_crtc *crtc)
10530 {
10531 struct drm_device *dev = crtc->base.dev;
10532 struct intel_encoder *encoder;
10533
10534 for_each_intel_encoder(dev, encoder) {
10535 if (encoder->new_crtc != crtc)
10536 continue;
10537
10538 if (!check_single_encoder_cloning(crtc, encoder))
10539 return false;
10540 }
10541
10542 return true;
10543 }
10544
10545 static bool check_digital_port_conflicts(struct drm_device *dev)
10546 {
10547 struct intel_connector *connector;
10548 unsigned int used_ports = 0;
10549
10550 /*
10551 * Walk the connector list instead of the encoder
10552 * list to detect the problem on ddi platforms
10553 * where there's just one encoder per digital port.
10554 */
10555 for_each_intel_connector(dev, connector) {
10556 struct intel_encoder *encoder = connector->new_encoder;
10557
10558 if (!encoder)
10559 continue;
10560
10561 WARN_ON(!encoder->new_crtc);
10562
10563 switch (encoder->type) {
10564 unsigned int port_mask;
10565 case INTEL_OUTPUT_UNKNOWN:
10566 if (WARN_ON(!HAS_DDI(dev)))
10567 break;
10568 case INTEL_OUTPUT_DISPLAYPORT:
10569 case INTEL_OUTPUT_HDMI:
10570 case INTEL_OUTPUT_EDP:
10571 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10572
10573 /* the same port mustn't appear more than once */
10574 if (used_ports & port_mask)
10575 return false;
10576
10577 used_ports |= port_mask;
10578 default:
10579 break;
10580 }
10581 }
10582
10583 return true;
10584 }
10585
10586 static void
10587 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
10588 {
10589 struct drm_crtc_state tmp_state;
10590
10591 /* Clear only the intel specific part of the crtc state */
10592 tmp_state = crtc_state->base;
10593 memset(crtc_state, 0, sizeof *crtc_state);
10594 crtc_state->base = tmp_state;
10595 }
10596
10597 static struct intel_crtc_state *
10598 intel_modeset_pipe_config(struct drm_crtc *crtc,
10599 struct drm_framebuffer *fb,
10600 struct drm_display_mode *mode,
10601 struct drm_atomic_state *state)
10602 {
10603 struct drm_device *dev = crtc->dev;
10604 struct intel_encoder *encoder;
10605 struct intel_connector *connector;
10606 struct drm_connector_state *connector_state;
10607 struct intel_crtc_state *pipe_config;
10608 int plane_bpp, ret = -EINVAL;
10609 int i;
10610 bool retry = true;
10611
10612 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10613 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10614 return ERR_PTR(-EINVAL);
10615 }
10616
10617 if (!check_digital_port_conflicts(dev)) {
10618 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
10619 return ERR_PTR(-EINVAL);
10620 }
10621
10622 pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
10623 if (IS_ERR(pipe_config))
10624 return pipe_config;
10625
10626 clear_intel_crtc_state(pipe_config);
10627
10628 pipe_config->base.crtc = crtc;
10629 drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
10630 drm_mode_copy(&pipe_config->base.mode, mode);
10631
10632 pipe_config->cpu_transcoder =
10633 (enum transcoder) to_intel_crtc(crtc)->pipe;
10634 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10635
10636 /*
10637 * Sanitize sync polarity flags based on requested ones. If neither
10638 * positive or negative polarity is requested, treat this as meaning
10639 * negative polarity.
10640 */
10641 if (!(pipe_config->base.adjusted_mode.flags &
10642 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10643 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10644
10645 if (!(pipe_config->base.adjusted_mode.flags &
10646 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10647 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10648
10649 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10650 * plane pixel format and any sink constraints into account. Returns the
10651 * source plane bpp so that dithering can be selected on mismatches
10652 * after encoders and crtc also have had their say. */
10653 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10654 fb, pipe_config);
10655 if (plane_bpp < 0)
10656 goto fail;
10657
10658 /*
10659 * Determine the real pipe dimensions. Note that stereo modes can
10660 * increase the actual pipe size due to the frame doubling and
10661 * insertion of additional space for blanks between the frame. This
10662 * is stored in the crtc timings. We use the requested mode to do this
10663 * computation to clearly distinguish it from the adjusted mode, which
10664 * can be changed by the connectors in the below retry loop.
10665 */
10666 drm_crtc_get_hv_timing(&pipe_config->base.mode,
10667 &pipe_config->pipe_src_w,
10668 &pipe_config->pipe_src_h);
10669
10670 encoder_retry:
10671 /* Ensure the port clock defaults are reset when retrying. */
10672 pipe_config->port_clock = 0;
10673 pipe_config->pixel_multiplier = 1;
10674
10675 /* Fill in default crtc timings, allow encoders to overwrite them. */
10676 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10677 CRTC_STEREO_DOUBLE);
10678
10679 /* Pass our mode to the connectors and the CRTC to give them a chance to
10680 * adjust it according to limitations or connector properties, and also
10681 * a chance to reject the mode entirely.
10682 */
10683 for (i = 0; i < state->num_connector; i++) {
10684 connector = to_intel_connector(state->connectors[i]);
10685 if (!connector)
10686 continue;
10687
10688 connector_state = state->connector_states[i];
10689 if (connector_state->crtc != crtc)
10690 continue;
10691
10692 encoder = to_intel_encoder(connector_state->best_encoder);
10693
10694 if (!(encoder->compute_config(encoder, pipe_config))) {
10695 DRM_DEBUG_KMS("Encoder config failure\n");
10696 goto fail;
10697 }
10698 }
10699
10700 /* Set default port clock if not overwritten by the encoder. Needs to be
10701 * done afterwards in case the encoder adjusts the mode. */
10702 if (!pipe_config->port_clock)
10703 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
10704 * pipe_config->pixel_multiplier;
10705
10706 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10707 if (ret < 0) {
10708 DRM_DEBUG_KMS("CRTC fixup failed\n");
10709 goto fail;
10710 }
10711
10712 if (ret == RETRY) {
10713 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10714 ret = -EINVAL;
10715 goto fail;
10716 }
10717
10718 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10719 retry = false;
10720 goto encoder_retry;
10721 }
10722
10723 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10724 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10725 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10726
10727 return pipe_config;
10728 fail:
10729 return ERR_PTR(ret);
10730 }
10731
10732 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10733 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10734 static void
10735 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10736 unsigned *prepare_pipes, unsigned *disable_pipes)
10737 {
10738 struct intel_crtc *intel_crtc;
10739 struct drm_device *dev = crtc->dev;
10740 struct intel_encoder *encoder;
10741 struct intel_connector *connector;
10742 struct drm_crtc *tmp_crtc;
10743
10744 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10745
10746 /* Check which crtcs have changed outputs connected to them, these need
10747 * to be part of the prepare_pipes mask. We don't (yet) support global
10748 * modeset across multiple crtcs, so modeset_pipes will only have one
10749 * bit set at most. */
10750 for_each_intel_connector(dev, connector) {
10751 if (connector->base.encoder == &connector->new_encoder->base)
10752 continue;
10753
10754 if (connector->base.encoder) {
10755 tmp_crtc = connector->base.encoder->crtc;
10756
10757 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10758 }
10759
10760 if (connector->new_encoder)
10761 *prepare_pipes |=
10762 1 << connector->new_encoder->new_crtc->pipe;
10763 }
10764
10765 for_each_intel_encoder(dev, encoder) {
10766 if (encoder->base.crtc == &encoder->new_crtc->base)
10767 continue;
10768
10769 if (encoder->base.crtc) {
10770 tmp_crtc = encoder->base.crtc;
10771
10772 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10773 }
10774
10775 if (encoder->new_crtc)
10776 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10777 }
10778
10779 /* Check for pipes that will be enabled/disabled ... */
10780 for_each_intel_crtc(dev, intel_crtc) {
10781 if (intel_crtc->base.state->enable == intel_crtc->new_enabled)
10782 continue;
10783
10784 if (!intel_crtc->new_enabled)
10785 *disable_pipes |= 1 << intel_crtc->pipe;
10786 else
10787 *prepare_pipes |= 1 << intel_crtc->pipe;
10788 }
10789
10790
10791 /* set_mode is also used to update properties on life display pipes. */
10792 intel_crtc = to_intel_crtc(crtc);
10793 if (intel_crtc->new_enabled)
10794 *prepare_pipes |= 1 << intel_crtc->pipe;
10795
10796 /*
10797 * For simplicity do a full modeset on any pipe where the output routing
10798 * changed. We could be more clever, but that would require us to be
10799 * more careful with calling the relevant encoder->mode_set functions.
10800 */
10801 if (*prepare_pipes)
10802 *modeset_pipes = *prepare_pipes;
10803
10804 /* ... and mask these out. */
10805 *modeset_pipes &= ~(*disable_pipes);
10806 *prepare_pipes &= ~(*disable_pipes);
10807
10808 /*
10809 * HACK: We don't (yet) fully support global modesets. intel_set_config
10810 * obies this rule, but the modeset restore mode of
10811 * intel_modeset_setup_hw_state does not.
10812 */
10813 *modeset_pipes &= 1 << intel_crtc->pipe;
10814 *prepare_pipes &= 1 << intel_crtc->pipe;
10815
10816 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10817 *modeset_pipes, *prepare_pipes, *disable_pipes);
10818 }
10819
10820 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10821 {
10822 struct drm_encoder *encoder;
10823 struct drm_device *dev = crtc->dev;
10824
10825 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10826 if (encoder->crtc == crtc)
10827 return true;
10828
10829 return false;
10830 }
10831
10832 static void
10833 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10834 {
10835 struct drm_i915_private *dev_priv = dev->dev_private;
10836 struct intel_encoder *intel_encoder;
10837 struct intel_crtc *intel_crtc;
10838 struct drm_connector *connector;
10839
10840 intel_shared_dpll_commit(dev_priv);
10841
10842 for_each_intel_encoder(dev, intel_encoder) {
10843 if (!intel_encoder->base.crtc)
10844 continue;
10845
10846 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10847
10848 if (prepare_pipes & (1 << intel_crtc->pipe))
10849 intel_encoder->connectors_active = false;
10850 }
10851
10852 intel_modeset_commit_output_state(dev);
10853
10854 /* Double check state. */
10855 for_each_intel_crtc(dev, intel_crtc) {
10856 WARN_ON(intel_crtc->base.state->enable != intel_crtc_in_use(&intel_crtc->base));
10857 WARN_ON(intel_crtc->new_config &&
10858 intel_crtc->new_config != intel_crtc->config);
10859 WARN_ON(intel_crtc->base.state->enable != !!intel_crtc->new_config);
10860 }
10861
10862 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10863 if (!connector->encoder || !connector->encoder->crtc)
10864 continue;
10865
10866 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10867
10868 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10869 struct drm_property *dpms_property =
10870 dev->mode_config.dpms_property;
10871
10872 connector->dpms = DRM_MODE_DPMS_ON;
10873 drm_object_property_set_value(&connector->base,
10874 dpms_property,
10875 DRM_MODE_DPMS_ON);
10876
10877 intel_encoder = to_intel_encoder(connector->encoder);
10878 intel_encoder->connectors_active = true;
10879 }
10880 }
10881
10882 }
10883
10884 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10885 {
10886 int diff;
10887
10888 if (clock1 == clock2)
10889 return true;
10890
10891 if (!clock1 || !clock2)
10892 return false;
10893
10894 diff = abs(clock1 - clock2);
10895
10896 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10897 return true;
10898
10899 return false;
10900 }
10901
10902 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10903 list_for_each_entry((intel_crtc), \
10904 &(dev)->mode_config.crtc_list, \
10905 base.head) \
10906 if (mask & (1 <<(intel_crtc)->pipe))
10907
10908 static bool
10909 intel_pipe_config_compare(struct drm_device *dev,
10910 struct intel_crtc_state *current_config,
10911 struct intel_crtc_state *pipe_config)
10912 {
10913 #define PIPE_CONF_CHECK_X(name) \
10914 if (current_config->name != pipe_config->name) { \
10915 DRM_ERROR("mismatch in " #name " " \
10916 "(expected 0x%08x, found 0x%08x)\n", \
10917 current_config->name, \
10918 pipe_config->name); \
10919 return false; \
10920 }
10921
10922 #define PIPE_CONF_CHECK_I(name) \
10923 if (current_config->name != pipe_config->name) { \
10924 DRM_ERROR("mismatch in " #name " " \
10925 "(expected %i, found %i)\n", \
10926 current_config->name, \
10927 pipe_config->name); \
10928 return false; \
10929 }
10930
10931 /* This is required for BDW+ where there is only one set of registers for
10932 * switching between high and low RR.
10933 * This macro can be used whenever a comparison has to be made between one
10934 * hw state and multiple sw state variables.
10935 */
10936 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10937 if ((current_config->name != pipe_config->name) && \
10938 (current_config->alt_name != pipe_config->name)) { \
10939 DRM_ERROR("mismatch in " #name " " \
10940 "(expected %i or %i, found %i)\n", \
10941 current_config->name, \
10942 current_config->alt_name, \
10943 pipe_config->name); \
10944 return false; \
10945 }
10946
10947 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10948 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10949 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10950 "(expected %i, found %i)\n", \
10951 current_config->name & (mask), \
10952 pipe_config->name & (mask)); \
10953 return false; \
10954 }
10955
10956 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10957 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10958 DRM_ERROR("mismatch in " #name " " \
10959 "(expected %i, found %i)\n", \
10960 current_config->name, \
10961 pipe_config->name); \
10962 return false; \
10963 }
10964
10965 #define PIPE_CONF_QUIRK(quirk) \
10966 ((current_config->quirks | pipe_config->quirks) & (quirk))
10967
10968 PIPE_CONF_CHECK_I(cpu_transcoder);
10969
10970 PIPE_CONF_CHECK_I(has_pch_encoder);
10971 PIPE_CONF_CHECK_I(fdi_lanes);
10972 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10973 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10974 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10975 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10976 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10977
10978 PIPE_CONF_CHECK_I(has_dp_encoder);
10979
10980 if (INTEL_INFO(dev)->gen < 8) {
10981 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10982 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10983 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10984 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10985 PIPE_CONF_CHECK_I(dp_m_n.tu);
10986
10987 if (current_config->has_drrs) {
10988 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10989 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10990 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10991 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10992 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10993 }
10994 } else {
10995 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10996 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10997 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10998 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10999 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
11000 }
11001
11002 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11003 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11004 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11005 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11006 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11007 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
11008
11009 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11010 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11011 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11012 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11013 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11014 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
11015
11016 PIPE_CONF_CHECK_I(pixel_multiplier);
11017 PIPE_CONF_CHECK_I(has_hdmi_sink);
11018 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
11019 IS_VALLEYVIEW(dev))
11020 PIPE_CONF_CHECK_I(limited_color_range);
11021 PIPE_CONF_CHECK_I(has_infoframe);
11022
11023 PIPE_CONF_CHECK_I(has_audio);
11024
11025 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11026 DRM_MODE_FLAG_INTERLACE);
11027
11028 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
11029 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11030 DRM_MODE_FLAG_PHSYNC);
11031 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11032 DRM_MODE_FLAG_NHSYNC);
11033 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11034 DRM_MODE_FLAG_PVSYNC);
11035 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11036 DRM_MODE_FLAG_NVSYNC);
11037 }
11038
11039 PIPE_CONF_CHECK_I(pipe_src_w);
11040 PIPE_CONF_CHECK_I(pipe_src_h);
11041
11042 /*
11043 * FIXME: BIOS likes to set up a cloned config with lvds+external
11044 * screen. Since we don't yet re-compute the pipe config when moving
11045 * just the lvds port away to another pipe the sw tracking won't match.
11046 *
11047 * Proper atomic modesets with recomputed global state will fix this.
11048 * Until then just don't check gmch state for inherited modes.
11049 */
11050 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
11051 PIPE_CONF_CHECK_I(gmch_pfit.control);
11052 /* pfit ratios are autocomputed by the hw on gen4+ */
11053 if (INTEL_INFO(dev)->gen < 4)
11054 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
11055 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
11056 }
11057
11058 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11059 if (current_config->pch_pfit.enabled) {
11060 PIPE_CONF_CHECK_I(pch_pfit.pos);
11061 PIPE_CONF_CHECK_I(pch_pfit.size);
11062 }
11063
11064 /* BDW+ don't expose a synchronous way to read the state */
11065 if (IS_HASWELL(dev))
11066 PIPE_CONF_CHECK_I(ips_enabled);
11067
11068 PIPE_CONF_CHECK_I(double_wide);
11069
11070 PIPE_CONF_CHECK_X(ddi_pll_sel);
11071
11072 PIPE_CONF_CHECK_I(shared_dpll);
11073 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
11074 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
11075 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11076 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
11077 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
11078 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11079 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11080 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
11081
11082 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
11083 PIPE_CONF_CHECK_I(pipe_bpp);
11084
11085 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
11086 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
11087
11088 #undef PIPE_CONF_CHECK_X
11089 #undef PIPE_CONF_CHECK_I
11090 #undef PIPE_CONF_CHECK_I_ALT
11091 #undef PIPE_CONF_CHECK_FLAGS
11092 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11093 #undef PIPE_CONF_QUIRK
11094
11095 return true;
11096 }
11097
11098 static void check_wm_state(struct drm_device *dev)
11099 {
11100 struct drm_i915_private *dev_priv = dev->dev_private;
11101 struct skl_ddb_allocation hw_ddb, *sw_ddb;
11102 struct intel_crtc *intel_crtc;
11103 int plane;
11104
11105 if (INTEL_INFO(dev)->gen < 9)
11106 return;
11107
11108 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11109 sw_ddb = &dev_priv->wm.skl_hw.ddb;
11110
11111 for_each_intel_crtc(dev, intel_crtc) {
11112 struct skl_ddb_entry *hw_entry, *sw_entry;
11113 const enum pipe pipe = intel_crtc->pipe;
11114
11115 if (!intel_crtc->active)
11116 continue;
11117
11118 /* planes */
11119 for_each_plane(dev_priv, pipe, plane) {
11120 hw_entry = &hw_ddb.plane[pipe][plane];
11121 sw_entry = &sw_ddb->plane[pipe][plane];
11122
11123 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11124 continue;
11125
11126 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
11127 "(expected (%u,%u), found (%u,%u))\n",
11128 pipe_name(pipe), plane + 1,
11129 sw_entry->start, sw_entry->end,
11130 hw_entry->start, hw_entry->end);
11131 }
11132
11133 /* cursor */
11134 hw_entry = &hw_ddb.cursor[pipe];
11135 sw_entry = &sw_ddb->cursor[pipe];
11136
11137 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11138 continue;
11139
11140 DRM_ERROR("mismatch in DDB state pipe %c cursor "
11141 "(expected (%u,%u), found (%u,%u))\n",
11142 pipe_name(pipe),
11143 sw_entry->start, sw_entry->end,
11144 hw_entry->start, hw_entry->end);
11145 }
11146 }
11147
11148 static void
11149 check_connector_state(struct drm_device *dev)
11150 {
11151 struct intel_connector *connector;
11152
11153 for_each_intel_connector(dev, connector) {
11154 /* This also checks the encoder/connector hw state with the
11155 * ->get_hw_state callbacks. */
11156 intel_connector_check_state(connector);
11157
11158 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
11159 "connector's staged encoder doesn't match current encoder\n");
11160 }
11161 }
11162
11163 static void
11164 check_encoder_state(struct drm_device *dev)
11165 {
11166 struct intel_encoder *encoder;
11167 struct intel_connector *connector;
11168
11169 for_each_intel_encoder(dev, encoder) {
11170 bool enabled = false;
11171 bool active = false;
11172 enum pipe pipe, tracked_pipe;
11173
11174 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11175 encoder->base.base.id,
11176 encoder->base.name);
11177
11178 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
11179 "encoder's stage crtc doesn't match current crtc\n");
11180 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
11181 "encoder's active_connectors set, but no crtc\n");
11182
11183 for_each_intel_connector(dev, connector) {
11184 if (connector->base.encoder != &encoder->base)
11185 continue;
11186 enabled = true;
11187 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
11188 active = true;
11189 }
11190 /*
11191 * for MST connectors if we unplug the connector is gone
11192 * away but the encoder is still connected to a crtc
11193 * until a modeset happens in response to the hotplug.
11194 */
11195 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
11196 continue;
11197
11198 I915_STATE_WARN(!!encoder->base.crtc != enabled,
11199 "encoder's enabled state mismatch "
11200 "(expected %i, found %i)\n",
11201 !!encoder->base.crtc, enabled);
11202 I915_STATE_WARN(active && !encoder->base.crtc,
11203 "active encoder with no crtc\n");
11204
11205 I915_STATE_WARN(encoder->connectors_active != active,
11206 "encoder's computed active state doesn't match tracked active state "
11207 "(expected %i, found %i)\n", active, encoder->connectors_active);
11208
11209 active = encoder->get_hw_state(encoder, &pipe);
11210 I915_STATE_WARN(active != encoder->connectors_active,
11211 "encoder's hw state doesn't match sw tracking "
11212 "(expected %i, found %i)\n",
11213 encoder->connectors_active, active);
11214
11215 if (!encoder->base.crtc)
11216 continue;
11217
11218 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
11219 I915_STATE_WARN(active && pipe != tracked_pipe,
11220 "active encoder's pipe doesn't match"
11221 "(expected %i, found %i)\n",
11222 tracked_pipe, pipe);
11223
11224 }
11225 }
11226
11227 static void
11228 check_crtc_state(struct drm_device *dev)
11229 {
11230 struct drm_i915_private *dev_priv = dev->dev_private;
11231 struct intel_crtc *crtc;
11232 struct intel_encoder *encoder;
11233 struct intel_crtc_state pipe_config;
11234
11235 for_each_intel_crtc(dev, crtc) {
11236 bool enabled = false;
11237 bool active = false;
11238
11239 memset(&pipe_config, 0, sizeof(pipe_config));
11240
11241 DRM_DEBUG_KMS("[CRTC:%d]\n",
11242 crtc->base.base.id);
11243
11244 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
11245 "active crtc, but not enabled in sw tracking\n");
11246
11247 for_each_intel_encoder(dev, encoder) {
11248 if (encoder->base.crtc != &crtc->base)
11249 continue;
11250 enabled = true;
11251 if (encoder->connectors_active)
11252 active = true;
11253 }
11254
11255 I915_STATE_WARN(active != crtc->active,
11256 "crtc's computed active state doesn't match tracked active state "
11257 "(expected %i, found %i)\n", active, crtc->active);
11258 I915_STATE_WARN(enabled != crtc->base.state->enable,
11259 "crtc's computed enabled state doesn't match tracked enabled state "
11260 "(expected %i, found %i)\n", enabled,
11261 crtc->base.state->enable);
11262
11263 active = dev_priv->display.get_pipe_config(crtc,
11264 &pipe_config);
11265
11266 /* hw state is inconsistent with the pipe quirk */
11267 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
11268 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
11269 active = crtc->active;
11270
11271 for_each_intel_encoder(dev, encoder) {
11272 enum pipe pipe;
11273 if (encoder->base.crtc != &crtc->base)
11274 continue;
11275 if (encoder->get_hw_state(encoder, &pipe))
11276 encoder->get_config(encoder, &pipe_config);
11277 }
11278
11279 I915_STATE_WARN(crtc->active != active,
11280 "crtc active state doesn't match with hw state "
11281 "(expected %i, found %i)\n", crtc->active, active);
11282
11283 if (active &&
11284 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
11285 I915_STATE_WARN(1, "pipe state doesn't match!\n");
11286 intel_dump_pipe_config(crtc, &pipe_config,
11287 "[hw state]");
11288 intel_dump_pipe_config(crtc, crtc->config,
11289 "[sw state]");
11290 }
11291 }
11292 }
11293
11294 static void
11295 check_shared_dpll_state(struct drm_device *dev)
11296 {
11297 struct drm_i915_private *dev_priv = dev->dev_private;
11298 struct intel_crtc *crtc;
11299 struct intel_dpll_hw_state dpll_hw_state;
11300 int i;
11301
11302 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11303 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11304 int enabled_crtcs = 0, active_crtcs = 0;
11305 bool active;
11306
11307 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11308
11309 DRM_DEBUG_KMS("%s\n", pll->name);
11310
11311 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
11312
11313 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
11314 "more active pll users than references: %i vs %i\n",
11315 pll->active, hweight32(pll->config.crtc_mask));
11316 I915_STATE_WARN(pll->active && !pll->on,
11317 "pll in active use but not on in sw tracking\n");
11318 I915_STATE_WARN(pll->on && !pll->active,
11319 "pll in on but not on in use in sw tracking\n");
11320 I915_STATE_WARN(pll->on != active,
11321 "pll on state mismatch (expected %i, found %i)\n",
11322 pll->on, active);
11323
11324 for_each_intel_crtc(dev, crtc) {
11325 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
11326 enabled_crtcs++;
11327 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11328 active_crtcs++;
11329 }
11330 I915_STATE_WARN(pll->active != active_crtcs,
11331 "pll active crtcs mismatch (expected %i, found %i)\n",
11332 pll->active, active_crtcs);
11333 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
11334 "pll enabled crtcs mismatch (expected %i, found %i)\n",
11335 hweight32(pll->config.crtc_mask), enabled_crtcs);
11336
11337 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
11338 sizeof(dpll_hw_state)),
11339 "pll hw state mismatch\n");
11340 }
11341 }
11342
11343 void
11344 intel_modeset_check_state(struct drm_device *dev)
11345 {
11346 check_wm_state(dev);
11347 check_connector_state(dev);
11348 check_encoder_state(dev);
11349 check_crtc_state(dev);
11350 check_shared_dpll_state(dev);
11351 }
11352
11353 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
11354 int dotclock)
11355 {
11356 /*
11357 * FDI already provided one idea for the dotclock.
11358 * Yell if the encoder disagrees.
11359 */
11360 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
11361 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11362 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
11363 }
11364
11365 static void update_scanline_offset(struct intel_crtc *crtc)
11366 {
11367 struct drm_device *dev = crtc->base.dev;
11368
11369 /*
11370 * The scanline counter increments at the leading edge of hsync.
11371 *
11372 * On most platforms it starts counting from vtotal-1 on the
11373 * first active line. That means the scanline counter value is
11374 * always one less than what we would expect. Ie. just after
11375 * start of vblank, which also occurs at start of hsync (on the
11376 * last active line), the scanline counter will read vblank_start-1.
11377 *
11378 * On gen2 the scanline counter starts counting from 1 instead
11379 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11380 * to keep the value positive), instead of adding one.
11381 *
11382 * On HSW+ the behaviour of the scanline counter depends on the output
11383 * type. For DP ports it behaves like most other platforms, but on HDMI
11384 * there's an extra 1 line difference. So we need to add two instead of
11385 * one to the value.
11386 */
11387 if (IS_GEN2(dev)) {
11388 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
11389 int vtotal;
11390
11391 vtotal = mode->crtc_vtotal;
11392 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
11393 vtotal /= 2;
11394
11395 crtc->scanline_offset = vtotal - 1;
11396 } else if (HAS_DDI(dev) &&
11397 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
11398 crtc->scanline_offset = 2;
11399 } else
11400 crtc->scanline_offset = 1;
11401 }
11402
11403 static struct intel_crtc_state *
11404 intel_modeset_compute_config(struct drm_crtc *crtc,
11405 struct drm_display_mode *mode,
11406 struct drm_framebuffer *fb,
11407 struct drm_atomic_state *state,
11408 unsigned *modeset_pipes,
11409 unsigned *prepare_pipes,
11410 unsigned *disable_pipes)
11411 {
11412 struct drm_device *dev = crtc->dev;
11413 struct intel_crtc_state *pipe_config = NULL;
11414 struct intel_crtc *intel_crtc;
11415 int ret = 0;
11416
11417 ret = drm_atomic_add_affected_connectors(state, crtc);
11418 if (ret)
11419 return ERR_PTR(ret);
11420
11421 intel_modeset_affected_pipes(crtc, modeset_pipes,
11422 prepare_pipes, disable_pipes);
11423
11424 for_each_intel_crtc_masked(dev, *disable_pipes, intel_crtc) {
11425 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
11426 if (IS_ERR(pipe_config))
11427 return pipe_config;
11428
11429 pipe_config->base.enable = false;
11430 }
11431
11432 /*
11433 * Note this needs changes when we start tracking multiple modes
11434 * and crtcs. At that point we'll need to compute the whole config
11435 * (i.e. one pipe_config for each crtc) rather than just the one
11436 * for this crtc.
11437 */
11438 for_each_intel_crtc_masked(dev, *modeset_pipes, intel_crtc) {
11439 /* FIXME: For now we still expect modeset_pipes has at most
11440 * one bit set. */
11441 if (WARN_ON(&intel_crtc->base != crtc))
11442 continue;
11443
11444 pipe_config = intel_modeset_pipe_config(crtc, fb, mode, state);
11445 if (IS_ERR(pipe_config))
11446 return pipe_config;
11447
11448 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11449 "[modeset]");
11450 }
11451
11452 return intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));;
11453 }
11454
11455 static int __intel_set_mode_setup_plls(struct drm_device *dev,
11456 unsigned modeset_pipes,
11457 unsigned disable_pipes)
11458 {
11459 struct drm_i915_private *dev_priv = to_i915(dev);
11460 unsigned clear_pipes = modeset_pipes | disable_pipes;
11461 struct intel_crtc *intel_crtc;
11462 int ret = 0;
11463
11464 if (!dev_priv->display.crtc_compute_clock)
11465 return 0;
11466
11467 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
11468 if (ret)
11469 goto done;
11470
11471 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11472 struct intel_crtc_state *state = intel_crtc->new_config;
11473 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11474 state);
11475 if (ret) {
11476 intel_shared_dpll_abort_config(dev_priv);
11477 goto done;
11478 }
11479 }
11480
11481 done:
11482 return ret;
11483 }
11484
11485 static int __intel_set_mode(struct drm_crtc *crtc,
11486 struct drm_display_mode *mode,
11487 int x, int y, struct drm_framebuffer *fb,
11488 struct intel_crtc_state *pipe_config,
11489 unsigned modeset_pipes,
11490 unsigned prepare_pipes,
11491 unsigned disable_pipes)
11492 {
11493 struct drm_device *dev = crtc->dev;
11494 struct drm_i915_private *dev_priv = dev->dev_private;
11495 struct drm_display_mode *saved_mode;
11496 struct intel_crtc_state *crtc_state_copy = NULL;
11497 struct intel_crtc *intel_crtc;
11498 int ret = 0;
11499
11500 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
11501 if (!saved_mode)
11502 return -ENOMEM;
11503
11504 crtc_state_copy = kmalloc(sizeof(*crtc_state_copy), GFP_KERNEL);
11505 if (!crtc_state_copy) {
11506 ret = -ENOMEM;
11507 goto done;
11508 }
11509
11510 *saved_mode = crtc->mode;
11511
11512 if (modeset_pipes)
11513 to_intel_crtc(crtc)->new_config = pipe_config;
11514
11515 /*
11516 * See if the config requires any additional preparation, e.g.
11517 * to adjust global state with pipes off. We need to do this
11518 * here so we can get the modeset_pipe updated config for the new
11519 * mode set on this crtc. For other crtcs we need to use the
11520 * adjusted_mode bits in the crtc directly.
11521 */
11522 if (IS_VALLEYVIEW(dev)) {
11523 valleyview_modeset_global_pipes(dev, &prepare_pipes);
11524
11525 /* may have added more to prepare_pipes than we should */
11526 prepare_pipes &= ~disable_pipes;
11527 }
11528
11529 ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes);
11530 if (ret)
11531 goto done;
11532
11533 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
11534 intel_crtc_disable(&intel_crtc->base);
11535
11536 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11537 if (intel_crtc->base.state->enable)
11538 dev_priv->display.crtc_disable(&intel_crtc->base);
11539 }
11540
11541 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11542 * to set it here already despite that we pass it down the callchain.
11543 *
11544 * Note we'll need to fix this up when we start tracking multiple
11545 * pipes; here we assume a single modeset_pipe and only track the
11546 * single crtc and mode.
11547 */
11548 if (modeset_pipes) {
11549 crtc->mode = *mode;
11550 /* mode_set/enable/disable functions rely on a correct pipe
11551 * config. */
11552 intel_crtc_set_state(to_intel_crtc(crtc), pipe_config);
11553
11554 /*
11555 * Calculate and store various constants which
11556 * are later needed by vblank and swap-completion
11557 * timestamping. They are derived from true hwmode.
11558 */
11559 drm_calc_timestamping_constants(crtc,
11560 &pipe_config->base.adjusted_mode);
11561 }
11562
11563 /* Only after disabling all output pipelines that will be changed can we
11564 * update the the output configuration. */
11565 intel_modeset_update_state(dev, prepare_pipes);
11566
11567 modeset_update_crtc_power_domains(pipe_config->base.state);
11568
11569 /* Set up the DPLL and any encoders state that needs to adjust or depend
11570 * on the DPLL.
11571 */
11572 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11573 struct drm_plane *primary = intel_crtc->base.primary;
11574 int vdisplay, hdisplay;
11575
11576 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11577 ret = primary->funcs->update_plane(primary, &intel_crtc->base,
11578 fb, 0, 0,
11579 hdisplay, vdisplay,
11580 x << 16, y << 16,
11581 hdisplay << 16, vdisplay << 16);
11582 }
11583
11584 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11585 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11586 update_scanline_offset(intel_crtc);
11587
11588 dev_priv->display.crtc_enable(&intel_crtc->base);
11589 }
11590
11591 /* FIXME: add subpixel order */
11592 done:
11593 if (ret && crtc->state->enable)
11594 crtc->mode = *saved_mode;
11595
11596 if (ret == 0 && pipe_config) {
11597 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11598
11599 /* The pipe_config will be freed with the atomic state, so
11600 * make a copy. */
11601 memcpy(crtc_state_copy, intel_crtc->config,
11602 sizeof *crtc_state_copy);
11603 intel_crtc->config = crtc_state_copy;
11604 intel_crtc->base.state = &crtc_state_copy->base;
11605
11606 if (modeset_pipes)
11607 intel_crtc->new_config = intel_crtc->config;
11608 } else {
11609 kfree(crtc_state_copy);
11610 }
11611
11612 kfree(saved_mode);
11613 return ret;
11614 }
11615
11616 static int intel_set_mode_pipes(struct drm_crtc *crtc,
11617 struct drm_display_mode *mode,
11618 int x, int y, struct drm_framebuffer *fb,
11619 struct intel_crtc_state *pipe_config,
11620 unsigned modeset_pipes,
11621 unsigned prepare_pipes,
11622 unsigned disable_pipes)
11623 {
11624 int ret;
11625
11626 ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
11627 prepare_pipes, disable_pipes);
11628
11629 if (ret == 0)
11630 intel_modeset_check_state(crtc->dev);
11631
11632 return ret;
11633 }
11634
11635 static int intel_set_mode(struct drm_crtc *crtc,
11636 struct drm_display_mode *mode,
11637 int x, int y, struct drm_framebuffer *fb,
11638 struct drm_atomic_state *state)
11639 {
11640 struct intel_crtc_state *pipe_config;
11641 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11642 int ret = 0;
11643
11644 pipe_config = intel_modeset_compute_config(crtc, mode, fb, state,
11645 &modeset_pipes,
11646 &prepare_pipes,
11647 &disable_pipes);
11648
11649 if (IS_ERR(pipe_config)) {
11650 ret = PTR_ERR(pipe_config);
11651 goto out;
11652 }
11653
11654 ret = intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
11655 modeset_pipes, prepare_pipes,
11656 disable_pipes);
11657 if (ret)
11658 goto out;
11659
11660 out:
11661 return ret;
11662 }
11663
11664 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11665 {
11666 struct drm_device *dev = crtc->dev;
11667 struct drm_atomic_state *state;
11668 struct intel_encoder *encoder;
11669 struct intel_connector *connector;
11670 struct drm_connector_state *connector_state;
11671
11672 state = drm_atomic_state_alloc(dev);
11673 if (!state) {
11674 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
11675 crtc->base.id);
11676 return;
11677 }
11678
11679 state->acquire_ctx = dev->mode_config.acquire_ctx;
11680
11681 /* The force restore path in the HW readout code relies on the staged
11682 * config still keeping the user requested config while the actual
11683 * state has been overwritten by the configuration read from HW. We
11684 * need to copy the staged config to the atomic state, otherwise the
11685 * mode set will just reapply the state the HW is already in. */
11686 for_each_intel_encoder(dev, encoder) {
11687 if (&encoder->new_crtc->base != crtc)
11688 continue;
11689
11690 for_each_intel_connector(dev, connector) {
11691 if (connector->new_encoder != encoder)
11692 continue;
11693
11694 connector_state = drm_atomic_get_connector_state(state, &connector->base);
11695 if (IS_ERR(connector_state)) {
11696 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
11697 connector->base.base.id,
11698 connector->base.name,
11699 PTR_ERR(connector_state));
11700 continue;
11701 }
11702
11703 connector_state->crtc = crtc;
11704 connector_state->best_encoder = &encoder->base;
11705 }
11706 }
11707
11708 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb,
11709 state);
11710
11711 drm_atomic_state_free(state);
11712 }
11713
11714 #undef for_each_intel_crtc_masked
11715
11716 static void intel_set_config_free(struct intel_set_config *config)
11717 {
11718 if (!config)
11719 return;
11720
11721 kfree(config->save_connector_encoders);
11722 kfree(config->save_encoder_crtcs);
11723 kfree(config->save_crtc_enabled);
11724 kfree(config);
11725 }
11726
11727 static int intel_set_config_save_state(struct drm_device *dev,
11728 struct intel_set_config *config)
11729 {
11730 struct drm_crtc *crtc;
11731 struct drm_encoder *encoder;
11732 struct drm_connector *connector;
11733 int count;
11734
11735 config->save_crtc_enabled =
11736 kcalloc(dev->mode_config.num_crtc,
11737 sizeof(bool), GFP_KERNEL);
11738 if (!config->save_crtc_enabled)
11739 return -ENOMEM;
11740
11741 config->save_encoder_crtcs =
11742 kcalloc(dev->mode_config.num_encoder,
11743 sizeof(struct drm_crtc *), GFP_KERNEL);
11744 if (!config->save_encoder_crtcs)
11745 return -ENOMEM;
11746
11747 config->save_connector_encoders =
11748 kcalloc(dev->mode_config.num_connector,
11749 sizeof(struct drm_encoder *), GFP_KERNEL);
11750 if (!config->save_connector_encoders)
11751 return -ENOMEM;
11752
11753 /* Copy data. Note that driver private data is not affected.
11754 * Should anything bad happen only the expected state is
11755 * restored, not the drivers personal bookkeeping.
11756 */
11757 count = 0;
11758 for_each_crtc(dev, crtc) {
11759 config->save_crtc_enabled[count++] = crtc->state->enable;
11760 }
11761
11762 count = 0;
11763 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11764 config->save_encoder_crtcs[count++] = encoder->crtc;
11765 }
11766
11767 count = 0;
11768 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11769 config->save_connector_encoders[count++] = connector->encoder;
11770 }
11771
11772 return 0;
11773 }
11774
11775 static void intel_set_config_restore_state(struct drm_device *dev,
11776 struct intel_set_config *config)
11777 {
11778 struct intel_crtc *crtc;
11779 struct intel_encoder *encoder;
11780 struct intel_connector *connector;
11781 int count;
11782
11783 count = 0;
11784 for_each_intel_crtc(dev, crtc) {
11785 crtc->new_enabled = config->save_crtc_enabled[count++];
11786
11787 if (crtc->new_enabled)
11788 crtc->new_config = crtc->config;
11789 else
11790 crtc->new_config = NULL;
11791 }
11792
11793 count = 0;
11794 for_each_intel_encoder(dev, encoder) {
11795 encoder->new_crtc =
11796 to_intel_crtc(config->save_encoder_crtcs[count++]);
11797 }
11798
11799 count = 0;
11800 for_each_intel_connector(dev, connector) {
11801 connector->new_encoder =
11802 to_intel_encoder(config->save_connector_encoders[count++]);
11803 }
11804 }
11805
11806 static bool
11807 is_crtc_connector_off(struct drm_mode_set *set)
11808 {
11809 int i;
11810
11811 if (set->num_connectors == 0)
11812 return false;
11813
11814 if (WARN_ON(set->connectors == NULL))
11815 return false;
11816
11817 for (i = 0; i < set->num_connectors; i++)
11818 if (set->connectors[i]->encoder &&
11819 set->connectors[i]->encoder->crtc == set->crtc &&
11820 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11821 return true;
11822
11823 return false;
11824 }
11825
11826 static void
11827 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11828 struct intel_set_config *config)
11829 {
11830
11831 /* We should be able to check here if the fb has the same properties
11832 * and then just flip_or_move it */
11833 if (is_crtc_connector_off(set)) {
11834 config->mode_changed = true;
11835 } else if (set->crtc->primary->fb != set->fb) {
11836 /*
11837 * If we have no fb, we can only flip as long as the crtc is
11838 * active, otherwise we need a full mode set. The crtc may
11839 * be active if we've only disabled the primary plane, or
11840 * in fastboot situations.
11841 */
11842 if (set->crtc->primary->fb == NULL) {
11843 struct intel_crtc *intel_crtc =
11844 to_intel_crtc(set->crtc);
11845
11846 if (intel_crtc->active) {
11847 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11848 config->fb_changed = true;
11849 } else {
11850 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11851 config->mode_changed = true;
11852 }
11853 } else if (set->fb == NULL) {
11854 config->mode_changed = true;
11855 } else if (set->fb->pixel_format !=
11856 set->crtc->primary->fb->pixel_format) {
11857 config->mode_changed = true;
11858 } else {
11859 config->fb_changed = true;
11860 }
11861 }
11862
11863 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11864 config->fb_changed = true;
11865
11866 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11867 DRM_DEBUG_KMS("modes are different, full mode set\n");
11868 drm_mode_debug_printmodeline(&set->crtc->mode);
11869 drm_mode_debug_printmodeline(set->mode);
11870 config->mode_changed = true;
11871 }
11872
11873 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11874 set->crtc->base.id, config->mode_changed, config->fb_changed);
11875 }
11876
11877 static int
11878 intel_modeset_stage_output_state(struct drm_device *dev,
11879 struct drm_mode_set *set,
11880 struct intel_set_config *config,
11881 struct drm_atomic_state *state)
11882 {
11883 struct intel_connector *connector;
11884 struct drm_connector_state *connector_state;
11885 struct intel_encoder *encoder;
11886 struct intel_crtc *crtc;
11887 int ro;
11888
11889 /* The upper layers ensure that we either disable a crtc or have a list
11890 * of connectors. For paranoia, double-check this. */
11891 WARN_ON(!set->fb && (set->num_connectors != 0));
11892 WARN_ON(set->fb && (set->num_connectors == 0));
11893
11894 for_each_intel_connector(dev, connector) {
11895 /* Otherwise traverse passed in connector list and get encoders
11896 * for them. */
11897 for (ro = 0; ro < set->num_connectors; ro++) {
11898 if (set->connectors[ro] == &connector->base) {
11899 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11900 break;
11901 }
11902 }
11903
11904 /* If we disable the crtc, disable all its connectors. Also, if
11905 * the connector is on the changing crtc but not on the new
11906 * connector list, disable it. */
11907 if ((!set->fb || ro == set->num_connectors) &&
11908 connector->base.encoder &&
11909 connector->base.encoder->crtc == set->crtc) {
11910 connector->new_encoder = NULL;
11911
11912 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11913 connector->base.base.id,
11914 connector->base.name);
11915 }
11916
11917
11918 if (&connector->new_encoder->base != connector->base.encoder) {
11919 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full mode switch\n",
11920 connector->base.base.id,
11921 connector->base.name);
11922 config->mode_changed = true;
11923 }
11924 }
11925 /* connector->new_encoder is now updated for all connectors. */
11926
11927 /* Update crtc of enabled connectors. */
11928 for_each_intel_connector(dev, connector) {
11929 struct drm_crtc *new_crtc;
11930
11931 if (!connector->new_encoder)
11932 continue;
11933
11934 new_crtc = connector->new_encoder->base.crtc;
11935
11936 for (ro = 0; ro < set->num_connectors; ro++) {
11937 if (set->connectors[ro] == &connector->base)
11938 new_crtc = set->crtc;
11939 }
11940
11941 /* Make sure the new CRTC will work with the encoder */
11942 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11943 new_crtc)) {
11944 return -EINVAL;
11945 }
11946 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11947
11948 connector_state =
11949 drm_atomic_get_connector_state(state, &connector->base);
11950 if (IS_ERR(connector_state))
11951 return PTR_ERR(connector_state);
11952
11953 connector_state->crtc = new_crtc;
11954 connector_state->best_encoder = &connector->new_encoder->base;
11955
11956 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11957 connector->base.base.id,
11958 connector->base.name,
11959 new_crtc->base.id);
11960 }
11961
11962 /* Check for any encoders that needs to be disabled. */
11963 for_each_intel_encoder(dev, encoder) {
11964 int num_connectors = 0;
11965 for_each_intel_connector(dev, connector) {
11966 if (connector->new_encoder == encoder) {
11967 WARN_ON(!connector->new_encoder->new_crtc);
11968 num_connectors++;
11969 }
11970 }
11971
11972 if (num_connectors == 0)
11973 encoder->new_crtc = NULL;
11974 else if (num_connectors > 1)
11975 return -EINVAL;
11976
11977 /* Only now check for crtc changes so we don't miss encoders
11978 * that will be disabled. */
11979 if (&encoder->new_crtc->base != encoder->base.crtc) {
11980 DRM_DEBUG_KMS("[ENCODER:%d:%s] crtc changed, full mode switch\n",
11981 encoder->base.base.id,
11982 encoder->base.name);
11983 config->mode_changed = true;
11984 }
11985 }
11986 /* Now we've also updated encoder->new_crtc for all encoders. */
11987 for_each_intel_connector(dev, connector) {
11988 connector_state =
11989 drm_atomic_get_connector_state(state, &connector->base);
11990
11991 if (connector->new_encoder) {
11992 if (connector->new_encoder != connector->encoder)
11993 connector->encoder = connector->new_encoder;
11994 } else {
11995 connector_state->crtc = NULL;
11996 }
11997 }
11998 for_each_intel_crtc(dev, crtc) {
11999 crtc->new_enabled = false;
12000
12001 for_each_intel_encoder(dev, encoder) {
12002 if (encoder->new_crtc == crtc) {
12003 crtc->new_enabled = true;
12004 break;
12005 }
12006 }
12007
12008 if (crtc->new_enabled != crtc->base.state->enable) {
12009 DRM_DEBUG_KMS("[CRTC:%d] %sabled, full mode switch\n",
12010 crtc->base.base.id,
12011 crtc->new_enabled ? "en" : "dis");
12012 config->mode_changed = true;
12013 }
12014
12015 if (crtc->new_enabled)
12016 crtc->new_config = crtc->config;
12017 else
12018 crtc->new_config = NULL;
12019 }
12020
12021 return 0;
12022 }
12023
12024 static void disable_crtc_nofb(struct intel_crtc *crtc)
12025 {
12026 struct drm_device *dev = crtc->base.dev;
12027 struct intel_encoder *encoder;
12028 struct intel_connector *connector;
12029
12030 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
12031 pipe_name(crtc->pipe));
12032
12033 for_each_intel_connector(dev, connector) {
12034 if (connector->new_encoder &&
12035 connector->new_encoder->new_crtc == crtc)
12036 connector->new_encoder = NULL;
12037 }
12038
12039 for_each_intel_encoder(dev, encoder) {
12040 if (encoder->new_crtc == crtc)
12041 encoder->new_crtc = NULL;
12042 }
12043
12044 crtc->new_enabled = false;
12045 crtc->new_config = NULL;
12046 }
12047
12048 static int intel_crtc_set_config(struct drm_mode_set *set)
12049 {
12050 struct drm_device *dev;
12051 struct drm_mode_set save_set;
12052 struct drm_atomic_state *state = NULL;
12053 struct intel_set_config *config;
12054 struct intel_crtc_state *pipe_config;
12055 unsigned modeset_pipes, prepare_pipes, disable_pipes;
12056 int ret;
12057
12058 BUG_ON(!set);
12059 BUG_ON(!set->crtc);
12060 BUG_ON(!set->crtc->helper_private);
12061
12062 /* Enforce sane interface api - has been abused by the fb helper. */
12063 BUG_ON(!set->mode && set->fb);
12064 BUG_ON(set->fb && set->num_connectors == 0);
12065
12066 if (set->fb) {
12067 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
12068 set->crtc->base.id, set->fb->base.id,
12069 (int)set->num_connectors, set->x, set->y);
12070 } else {
12071 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
12072 }
12073
12074 dev = set->crtc->dev;
12075
12076 ret = -ENOMEM;
12077 config = kzalloc(sizeof(*config), GFP_KERNEL);
12078 if (!config)
12079 goto out_config;
12080
12081 ret = intel_set_config_save_state(dev, config);
12082 if (ret)
12083 goto out_config;
12084
12085 save_set.crtc = set->crtc;
12086 save_set.mode = &set->crtc->mode;
12087 save_set.x = set->crtc->x;
12088 save_set.y = set->crtc->y;
12089 save_set.fb = set->crtc->primary->fb;
12090
12091 /* Compute whether we need a full modeset, only an fb base update or no
12092 * change at all. In the future we might also check whether only the
12093 * mode changed, e.g. for LVDS where we only change the panel fitter in
12094 * such cases. */
12095 intel_set_config_compute_mode_changes(set, config);
12096
12097 state = drm_atomic_state_alloc(dev);
12098 if (!state) {
12099 ret = -ENOMEM;
12100 goto out_config;
12101 }
12102
12103 state->acquire_ctx = dev->mode_config.acquire_ctx;
12104
12105 ret = intel_modeset_stage_output_state(dev, set, config, state);
12106 if (ret)
12107 goto fail;
12108
12109 pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
12110 set->fb, state,
12111 &modeset_pipes,
12112 &prepare_pipes,
12113 &disable_pipes);
12114 if (IS_ERR(pipe_config)) {
12115 ret = PTR_ERR(pipe_config);
12116 goto fail;
12117 } else if (pipe_config) {
12118 if (pipe_config->has_audio !=
12119 to_intel_crtc(set->crtc)->config->has_audio)
12120 config->mode_changed = true;
12121
12122 /*
12123 * Note we have an issue here with infoframes: current code
12124 * only updates them on the full mode set path per hw
12125 * requirements. So here we should be checking for any
12126 * required changes and forcing a mode set.
12127 */
12128 }
12129
12130 intel_update_pipe_size(to_intel_crtc(set->crtc));
12131
12132 if (config->mode_changed) {
12133 ret = intel_set_mode_pipes(set->crtc, set->mode,
12134 set->x, set->y, set->fb, pipe_config,
12135 modeset_pipes, prepare_pipes,
12136 disable_pipes);
12137 } else if (config->fb_changed) {
12138 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
12139 struct drm_plane *primary = set->crtc->primary;
12140 int vdisplay, hdisplay;
12141
12142 drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay);
12143 ret = primary->funcs->update_plane(primary, set->crtc, set->fb,
12144 0, 0, hdisplay, vdisplay,
12145 set->x << 16, set->y << 16,
12146 hdisplay << 16, vdisplay << 16);
12147
12148 /*
12149 * We need to make sure the primary plane is re-enabled if it
12150 * has previously been turned off.
12151 */
12152 if (!intel_crtc->primary_enabled && ret == 0) {
12153 WARN_ON(!intel_crtc->active);
12154 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
12155 }
12156
12157 /*
12158 * In the fastboot case this may be our only check of the
12159 * state after boot. It would be better to only do it on
12160 * the first update, but we don't have a nice way of doing that
12161 * (and really, set_config isn't used much for high freq page
12162 * flipping, so increasing its cost here shouldn't be a big
12163 * deal).
12164 */
12165 if (i915.fastboot && ret == 0)
12166 intel_modeset_check_state(set->crtc->dev);
12167 }
12168
12169 if (ret) {
12170 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
12171 set->crtc->base.id, ret);
12172 fail:
12173 intel_set_config_restore_state(dev, config);
12174
12175 drm_atomic_state_clear(state);
12176
12177 /*
12178 * HACK: if the pipe was on, but we didn't have a framebuffer,
12179 * force the pipe off to avoid oopsing in the modeset code
12180 * due to fb==NULL. This should only happen during boot since
12181 * we don't yet reconstruct the FB from the hardware state.
12182 */
12183 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
12184 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
12185
12186 /* Try to restore the config */
12187 if (config->mode_changed &&
12188 intel_set_mode(save_set.crtc, save_set.mode,
12189 save_set.x, save_set.y, save_set.fb,
12190 state))
12191 DRM_ERROR("failed to restore config after modeset failure\n");
12192 }
12193
12194 out_config:
12195 if (state)
12196 drm_atomic_state_free(state);
12197
12198 intel_set_config_free(config);
12199 return ret;
12200 }
12201
12202 static const struct drm_crtc_funcs intel_crtc_funcs = {
12203 .gamma_set = intel_crtc_gamma_set,
12204 .set_config = intel_crtc_set_config,
12205 .destroy = intel_crtc_destroy,
12206 .page_flip = intel_crtc_page_flip,
12207 .atomic_duplicate_state = intel_crtc_duplicate_state,
12208 .atomic_destroy_state = intel_crtc_destroy_state,
12209 };
12210
12211 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
12212 struct intel_shared_dpll *pll,
12213 struct intel_dpll_hw_state *hw_state)
12214 {
12215 uint32_t val;
12216
12217 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
12218 return false;
12219
12220 val = I915_READ(PCH_DPLL(pll->id));
12221 hw_state->dpll = val;
12222 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
12223 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
12224
12225 return val & DPLL_VCO_ENABLE;
12226 }
12227
12228 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
12229 struct intel_shared_dpll *pll)
12230 {
12231 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
12232 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
12233 }
12234
12235 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
12236 struct intel_shared_dpll *pll)
12237 {
12238 /* PCH refclock must be enabled first */
12239 ibx_assert_pch_refclk_enabled(dev_priv);
12240
12241 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
12242
12243 /* Wait for the clocks to stabilize. */
12244 POSTING_READ(PCH_DPLL(pll->id));
12245 udelay(150);
12246
12247 /* The pixel multiplier can only be updated once the
12248 * DPLL is enabled and the clocks are stable.
12249 *
12250 * So write it again.
12251 */
12252 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
12253 POSTING_READ(PCH_DPLL(pll->id));
12254 udelay(200);
12255 }
12256
12257 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
12258 struct intel_shared_dpll *pll)
12259 {
12260 struct drm_device *dev = dev_priv->dev;
12261 struct intel_crtc *crtc;
12262
12263 /* Make sure no transcoder isn't still depending on us. */
12264 for_each_intel_crtc(dev, crtc) {
12265 if (intel_crtc_to_shared_dpll(crtc) == pll)
12266 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
12267 }
12268
12269 I915_WRITE(PCH_DPLL(pll->id), 0);
12270 POSTING_READ(PCH_DPLL(pll->id));
12271 udelay(200);
12272 }
12273
12274 static char *ibx_pch_dpll_names[] = {
12275 "PCH DPLL A",
12276 "PCH DPLL B",
12277 };
12278
12279 static void ibx_pch_dpll_init(struct drm_device *dev)
12280 {
12281 struct drm_i915_private *dev_priv = dev->dev_private;
12282 int i;
12283
12284 dev_priv->num_shared_dpll = 2;
12285
12286 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12287 dev_priv->shared_dplls[i].id = i;
12288 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
12289 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
12290 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
12291 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
12292 dev_priv->shared_dplls[i].get_hw_state =
12293 ibx_pch_dpll_get_hw_state;
12294 }
12295 }
12296
12297 static void intel_shared_dpll_init(struct drm_device *dev)
12298 {
12299 struct drm_i915_private *dev_priv = dev->dev_private;
12300
12301 if (HAS_DDI(dev))
12302 intel_ddi_pll_init(dev);
12303 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
12304 ibx_pch_dpll_init(dev);
12305 else
12306 dev_priv->num_shared_dpll = 0;
12307
12308 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
12309 }
12310
12311 /**
12312 * intel_wm_need_update - Check whether watermarks need updating
12313 * @plane: drm plane
12314 * @state: new plane state
12315 *
12316 * Check current plane state versus the new one to determine whether
12317 * watermarks need to be recalculated.
12318 *
12319 * Returns true or false.
12320 */
12321 bool intel_wm_need_update(struct drm_plane *plane,
12322 struct drm_plane_state *state)
12323 {
12324 /* Update watermarks on tiling changes. */
12325 if (!plane->state->fb || !state->fb ||
12326 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
12327 plane->state->rotation != state->rotation)
12328 return true;
12329
12330 return false;
12331 }
12332
12333 /**
12334 * intel_prepare_plane_fb - Prepare fb for usage on plane
12335 * @plane: drm plane to prepare for
12336 * @fb: framebuffer to prepare for presentation
12337 *
12338 * Prepares a framebuffer for usage on a display plane. Generally this
12339 * involves pinning the underlying object and updating the frontbuffer tracking
12340 * bits. Some older platforms need special physical address handling for
12341 * cursor planes.
12342 *
12343 * Returns 0 on success, negative error code on failure.
12344 */
12345 int
12346 intel_prepare_plane_fb(struct drm_plane *plane,
12347 struct drm_framebuffer *fb,
12348 const struct drm_plane_state *new_state)
12349 {
12350 struct drm_device *dev = plane->dev;
12351 struct intel_plane *intel_plane = to_intel_plane(plane);
12352 enum pipe pipe = intel_plane->pipe;
12353 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12354 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
12355 unsigned frontbuffer_bits = 0;
12356 int ret = 0;
12357
12358 if (!obj)
12359 return 0;
12360
12361 switch (plane->type) {
12362 case DRM_PLANE_TYPE_PRIMARY:
12363 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
12364 break;
12365 case DRM_PLANE_TYPE_CURSOR:
12366 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
12367 break;
12368 case DRM_PLANE_TYPE_OVERLAY:
12369 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
12370 break;
12371 }
12372
12373 mutex_lock(&dev->struct_mutex);
12374
12375 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
12376 INTEL_INFO(dev)->cursor_needs_physical) {
12377 int align = IS_I830(dev) ? 16 * 1024 : 256;
12378 ret = i915_gem_object_attach_phys(obj, align);
12379 if (ret)
12380 DRM_DEBUG_KMS("failed to attach phys object\n");
12381 } else {
12382 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
12383 }
12384
12385 if (ret == 0)
12386 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
12387
12388 mutex_unlock(&dev->struct_mutex);
12389
12390 return ret;
12391 }
12392
12393 /**
12394 * intel_cleanup_plane_fb - Cleans up an fb after plane use
12395 * @plane: drm plane to clean up for
12396 * @fb: old framebuffer that was on plane
12397 *
12398 * Cleans up a framebuffer that has just been removed from a plane.
12399 */
12400 void
12401 intel_cleanup_plane_fb(struct drm_plane *plane,
12402 struct drm_framebuffer *fb,
12403 const struct drm_plane_state *old_state)
12404 {
12405 struct drm_device *dev = plane->dev;
12406 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12407
12408 if (WARN_ON(!obj))
12409 return;
12410
12411 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
12412 !INTEL_INFO(dev)->cursor_needs_physical) {
12413 mutex_lock(&dev->struct_mutex);
12414 intel_unpin_fb_obj(fb, old_state);
12415 mutex_unlock(&dev->struct_mutex);
12416 }
12417 }
12418
12419 static int
12420 intel_check_primary_plane(struct drm_plane *plane,
12421 struct intel_plane_state *state)
12422 {
12423 struct drm_device *dev = plane->dev;
12424 struct drm_i915_private *dev_priv = dev->dev_private;
12425 struct drm_crtc *crtc = state->base.crtc;
12426 struct intel_crtc *intel_crtc;
12427 struct drm_framebuffer *fb = state->base.fb;
12428 struct drm_rect *dest = &state->dst;
12429 struct drm_rect *src = &state->src;
12430 const struct drm_rect *clip = &state->clip;
12431 int ret;
12432
12433 crtc = crtc ? crtc : plane->crtc;
12434 intel_crtc = to_intel_crtc(crtc);
12435
12436 ret = drm_plane_helper_check_update(plane, crtc, fb,
12437 src, dest, clip,
12438 DRM_PLANE_HELPER_NO_SCALING,
12439 DRM_PLANE_HELPER_NO_SCALING,
12440 false, true, &state->visible);
12441 if (ret)
12442 return ret;
12443
12444 if (intel_crtc->active) {
12445 intel_crtc->atomic.wait_for_flips = true;
12446
12447 /*
12448 * FBC does not work on some platforms for rotated
12449 * planes, so disable it when rotation is not 0 and
12450 * update it when rotation is set back to 0.
12451 *
12452 * FIXME: This is redundant with the fbc update done in
12453 * the primary plane enable function except that that
12454 * one is done too late. We eventually need to unify
12455 * this.
12456 */
12457 if (intel_crtc->primary_enabled &&
12458 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
12459 dev_priv->fbc.crtc == intel_crtc &&
12460 state->base.rotation != BIT(DRM_ROTATE_0)) {
12461 intel_crtc->atomic.disable_fbc = true;
12462 }
12463
12464 if (state->visible) {
12465 /*
12466 * BDW signals flip done immediately if the plane
12467 * is disabled, even if the plane enable is already
12468 * armed to occur at the next vblank :(
12469 */
12470 if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled)
12471 intel_crtc->atomic.wait_vblank = true;
12472 }
12473
12474 intel_crtc->atomic.fb_bits |=
12475 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
12476
12477 intel_crtc->atomic.update_fbc = true;
12478
12479 if (intel_wm_need_update(plane, &state->base))
12480 intel_crtc->atomic.update_wm = true;
12481 }
12482
12483 return 0;
12484 }
12485
12486 static void
12487 intel_commit_primary_plane(struct drm_plane *plane,
12488 struct intel_plane_state *state)
12489 {
12490 struct drm_crtc *crtc = state->base.crtc;
12491 struct drm_framebuffer *fb = state->base.fb;
12492 struct drm_device *dev = plane->dev;
12493 struct drm_i915_private *dev_priv = dev->dev_private;
12494 struct intel_crtc *intel_crtc;
12495 struct drm_rect *src = &state->src;
12496
12497 crtc = crtc ? crtc : plane->crtc;
12498 intel_crtc = to_intel_crtc(crtc);
12499
12500 plane->fb = fb;
12501 crtc->x = src->x1 >> 16;
12502 crtc->y = src->y1 >> 16;
12503
12504 if (intel_crtc->active) {
12505 if (state->visible) {
12506 /* FIXME: kill this fastboot hack */
12507 intel_update_pipe_size(intel_crtc);
12508
12509 intel_crtc->primary_enabled = true;
12510
12511 dev_priv->display.update_primary_plane(crtc, plane->fb,
12512 crtc->x, crtc->y);
12513 } else {
12514 /*
12515 * If clipping results in a non-visible primary plane,
12516 * we'll disable the primary plane. Note that this is
12517 * a bit different than what happens if userspace
12518 * explicitly disables the plane by passing fb=0
12519 * because plane->fb still gets set and pinned.
12520 */
12521 intel_disable_primary_hw_plane(plane, crtc);
12522 }
12523 }
12524 }
12525
12526 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
12527 {
12528 struct drm_device *dev = crtc->dev;
12529 struct drm_i915_private *dev_priv = dev->dev_private;
12530 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12531 struct intel_plane *intel_plane;
12532 struct drm_plane *p;
12533 unsigned fb_bits = 0;
12534
12535 /* Track fb's for any planes being disabled */
12536 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
12537 intel_plane = to_intel_plane(p);
12538
12539 if (intel_crtc->atomic.disabled_planes &
12540 (1 << drm_plane_index(p))) {
12541 switch (p->type) {
12542 case DRM_PLANE_TYPE_PRIMARY:
12543 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
12544 break;
12545 case DRM_PLANE_TYPE_CURSOR:
12546 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
12547 break;
12548 case DRM_PLANE_TYPE_OVERLAY:
12549 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
12550 break;
12551 }
12552
12553 mutex_lock(&dev->struct_mutex);
12554 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
12555 mutex_unlock(&dev->struct_mutex);
12556 }
12557 }
12558
12559 if (intel_crtc->atomic.wait_for_flips)
12560 intel_crtc_wait_for_pending_flips(crtc);
12561
12562 if (intel_crtc->atomic.disable_fbc)
12563 intel_fbc_disable(dev);
12564
12565 if (intel_crtc->atomic.pre_disable_primary)
12566 intel_pre_disable_primary(crtc);
12567
12568 if (intel_crtc->atomic.update_wm)
12569 intel_update_watermarks(crtc);
12570
12571 intel_runtime_pm_get(dev_priv);
12572
12573 /* Perform vblank evasion around commit operation */
12574 if (intel_crtc->active)
12575 intel_crtc->atomic.evade =
12576 intel_pipe_update_start(intel_crtc,
12577 &intel_crtc->atomic.start_vbl_count);
12578 }
12579
12580 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
12581 {
12582 struct drm_device *dev = crtc->dev;
12583 struct drm_i915_private *dev_priv = dev->dev_private;
12584 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12585 struct drm_plane *p;
12586
12587 if (intel_crtc->atomic.evade)
12588 intel_pipe_update_end(intel_crtc,
12589 intel_crtc->atomic.start_vbl_count);
12590
12591 intel_runtime_pm_put(dev_priv);
12592
12593 if (intel_crtc->atomic.wait_vblank)
12594 intel_wait_for_vblank(dev, intel_crtc->pipe);
12595
12596 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
12597
12598 if (intel_crtc->atomic.update_fbc) {
12599 mutex_lock(&dev->struct_mutex);
12600 intel_fbc_update(dev);
12601 mutex_unlock(&dev->struct_mutex);
12602 }
12603
12604 if (intel_crtc->atomic.post_enable_primary)
12605 intel_post_enable_primary(crtc);
12606
12607 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
12608 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
12609 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
12610 false, false);
12611
12612 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
12613 }
12614
12615 /**
12616 * intel_plane_destroy - destroy a plane
12617 * @plane: plane to destroy
12618 *
12619 * Common destruction function for all types of planes (primary, cursor,
12620 * sprite).
12621 */
12622 void intel_plane_destroy(struct drm_plane *plane)
12623 {
12624 struct intel_plane *intel_plane = to_intel_plane(plane);
12625 drm_plane_cleanup(plane);
12626 kfree(intel_plane);
12627 }
12628
12629 const struct drm_plane_funcs intel_plane_funcs = {
12630 .update_plane = drm_plane_helper_update,
12631 .disable_plane = drm_plane_helper_disable,
12632 .destroy = intel_plane_destroy,
12633 .set_property = drm_atomic_helper_plane_set_property,
12634 .atomic_get_property = intel_plane_atomic_get_property,
12635 .atomic_set_property = intel_plane_atomic_set_property,
12636 .atomic_duplicate_state = intel_plane_duplicate_state,
12637 .atomic_destroy_state = intel_plane_destroy_state,
12638
12639 };
12640
12641 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
12642 int pipe)
12643 {
12644 struct intel_plane *primary;
12645 struct intel_plane_state *state;
12646 const uint32_t *intel_primary_formats;
12647 int num_formats;
12648
12649 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
12650 if (primary == NULL)
12651 return NULL;
12652
12653 state = intel_create_plane_state(&primary->base);
12654 if (!state) {
12655 kfree(primary);
12656 return NULL;
12657 }
12658 primary->base.state = &state->base;
12659
12660 primary->can_scale = false;
12661 primary->max_downscale = 1;
12662 primary->pipe = pipe;
12663 primary->plane = pipe;
12664 primary->check_plane = intel_check_primary_plane;
12665 primary->commit_plane = intel_commit_primary_plane;
12666 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
12667 primary->plane = !pipe;
12668
12669 if (INTEL_INFO(dev)->gen <= 3) {
12670 intel_primary_formats = intel_primary_formats_gen2;
12671 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
12672 } else {
12673 intel_primary_formats = intel_primary_formats_gen4;
12674 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
12675 }
12676
12677 drm_universal_plane_init(dev, &primary->base, 0,
12678 &intel_plane_funcs,
12679 intel_primary_formats, num_formats,
12680 DRM_PLANE_TYPE_PRIMARY);
12681
12682 if (INTEL_INFO(dev)->gen >= 4) {
12683 if (!dev->mode_config.rotation_property)
12684 dev->mode_config.rotation_property =
12685 drm_mode_create_rotation_property(dev,
12686 BIT(DRM_ROTATE_0) |
12687 BIT(DRM_ROTATE_180));
12688 if (dev->mode_config.rotation_property)
12689 drm_object_attach_property(&primary->base.base,
12690 dev->mode_config.rotation_property,
12691 state->base.rotation);
12692 }
12693
12694 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
12695
12696 return &primary->base;
12697 }
12698
12699 static int
12700 intel_check_cursor_plane(struct drm_plane *plane,
12701 struct intel_plane_state *state)
12702 {
12703 struct drm_crtc *crtc = state->base.crtc;
12704 struct drm_device *dev = plane->dev;
12705 struct drm_framebuffer *fb = state->base.fb;
12706 struct drm_rect *dest = &state->dst;
12707 struct drm_rect *src = &state->src;
12708 const struct drm_rect *clip = &state->clip;
12709 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12710 struct intel_crtc *intel_crtc;
12711 unsigned stride;
12712 int ret;
12713
12714 crtc = crtc ? crtc : plane->crtc;
12715 intel_crtc = to_intel_crtc(crtc);
12716
12717 ret = drm_plane_helper_check_update(plane, crtc, fb,
12718 src, dest, clip,
12719 DRM_PLANE_HELPER_NO_SCALING,
12720 DRM_PLANE_HELPER_NO_SCALING,
12721 true, true, &state->visible);
12722 if (ret)
12723 return ret;
12724
12725
12726 /* if we want to turn off the cursor ignore width and height */
12727 if (!obj)
12728 goto finish;
12729
12730 /* Check for which cursor types we support */
12731 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
12732 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
12733 state->base.crtc_w, state->base.crtc_h);
12734 return -EINVAL;
12735 }
12736
12737 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
12738 if (obj->base.size < stride * state->base.crtc_h) {
12739 DRM_DEBUG_KMS("buffer is too small\n");
12740 return -ENOMEM;
12741 }
12742
12743 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
12744 DRM_DEBUG_KMS("cursor cannot be tiled\n");
12745 ret = -EINVAL;
12746 }
12747
12748 finish:
12749 if (intel_crtc->active) {
12750 if (plane->state->crtc_w != state->base.crtc_w)
12751 intel_crtc->atomic.update_wm = true;
12752
12753 intel_crtc->atomic.fb_bits |=
12754 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
12755 }
12756
12757 return ret;
12758 }
12759
12760 static void
12761 intel_commit_cursor_plane(struct drm_plane *plane,
12762 struct intel_plane_state *state)
12763 {
12764 struct drm_crtc *crtc = state->base.crtc;
12765 struct drm_device *dev = plane->dev;
12766 struct intel_crtc *intel_crtc;
12767 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
12768 uint32_t addr;
12769
12770 crtc = crtc ? crtc : plane->crtc;
12771 intel_crtc = to_intel_crtc(crtc);
12772
12773 plane->fb = state->base.fb;
12774 crtc->cursor_x = state->base.crtc_x;
12775 crtc->cursor_y = state->base.crtc_y;
12776
12777 if (intel_crtc->cursor_bo == obj)
12778 goto update;
12779
12780 if (!obj)
12781 addr = 0;
12782 else if (!INTEL_INFO(dev)->cursor_needs_physical)
12783 addr = i915_gem_obj_ggtt_offset(obj);
12784 else
12785 addr = obj->phys_handle->busaddr;
12786
12787 intel_crtc->cursor_addr = addr;
12788 intel_crtc->cursor_bo = obj;
12789 update:
12790
12791 if (intel_crtc->active)
12792 intel_crtc_update_cursor(crtc, state->visible);
12793 }
12794
12795 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12796 int pipe)
12797 {
12798 struct intel_plane *cursor;
12799 struct intel_plane_state *state;
12800
12801 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12802 if (cursor == NULL)
12803 return NULL;
12804
12805 state = intel_create_plane_state(&cursor->base);
12806 if (!state) {
12807 kfree(cursor);
12808 return NULL;
12809 }
12810 cursor->base.state = &state->base;
12811
12812 cursor->can_scale = false;
12813 cursor->max_downscale = 1;
12814 cursor->pipe = pipe;
12815 cursor->plane = pipe;
12816 cursor->check_plane = intel_check_cursor_plane;
12817 cursor->commit_plane = intel_commit_cursor_plane;
12818
12819 drm_universal_plane_init(dev, &cursor->base, 0,
12820 &intel_plane_funcs,
12821 intel_cursor_formats,
12822 ARRAY_SIZE(intel_cursor_formats),
12823 DRM_PLANE_TYPE_CURSOR);
12824
12825 if (INTEL_INFO(dev)->gen >= 4) {
12826 if (!dev->mode_config.rotation_property)
12827 dev->mode_config.rotation_property =
12828 drm_mode_create_rotation_property(dev,
12829 BIT(DRM_ROTATE_0) |
12830 BIT(DRM_ROTATE_180));
12831 if (dev->mode_config.rotation_property)
12832 drm_object_attach_property(&cursor->base.base,
12833 dev->mode_config.rotation_property,
12834 state->base.rotation);
12835 }
12836
12837 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
12838
12839 return &cursor->base;
12840 }
12841
12842 static void intel_crtc_init(struct drm_device *dev, int pipe)
12843 {
12844 struct drm_i915_private *dev_priv = dev->dev_private;
12845 struct intel_crtc *intel_crtc;
12846 struct intel_crtc_state *crtc_state = NULL;
12847 struct drm_plane *primary = NULL;
12848 struct drm_plane *cursor = NULL;
12849 int i, ret;
12850
12851 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12852 if (intel_crtc == NULL)
12853 return;
12854
12855 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
12856 if (!crtc_state)
12857 goto fail;
12858 intel_crtc_set_state(intel_crtc, crtc_state);
12859 crtc_state->base.crtc = &intel_crtc->base;
12860
12861 primary = intel_primary_plane_create(dev, pipe);
12862 if (!primary)
12863 goto fail;
12864
12865 cursor = intel_cursor_plane_create(dev, pipe);
12866 if (!cursor)
12867 goto fail;
12868
12869 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12870 cursor, &intel_crtc_funcs);
12871 if (ret)
12872 goto fail;
12873
12874 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12875 for (i = 0; i < 256; i++) {
12876 intel_crtc->lut_r[i] = i;
12877 intel_crtc->lut_g[i] = i;
12878 intel_crtc->lut_b[i] = i;
12879 }
12880
12881 /*
12882 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12883 * is hooked to pipe B. Hence we want plane A feeding pipe B.
12884 */
12885 intel_crtc->pipe = pipe;
12886 intel_crtc->plane = pipe;
12887 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12888 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12889 intel_crtc->plane = !pipe;
12890 }
12891
12892 intel_crtc->cursor_base = ~0;
12893 intel_crtc->cursor_cntl = ~0;
12894 intel_crtc->cursor_size = ~0;
12895
12896 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12897 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12898 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12899 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12900
12901 INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
12902
12903 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12904
12905 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12906 return;
12907
12908 fail:
12909 if (primary)
12910 drm_plane_cleanup(primary);
12911 if (cursor)
12912 drm_plane_cleanup(cursor);
12913 kfree(crtc_state);
12914 kfree(intel_crtc);
12915 }
12916
12917 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12918 {
12919 struct drm_encoder *encoder = connector->base.encoder;
12920 struct drm_device *dev = connector->base.dev;
12921
12922 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12923
12924 if (!encoder || WARN_ON(!encoder->crtc))
12925 return INVALID_PIPE;
12926
12927 return to_intel_crtc(encoder->crtc)->pipe;
12928 }
12929
12930 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12931 struct drm_file *file)
12932 {
12933 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12934 struct drm_crtc *drmmode_crtc;
12935 struct intel_crtc *crtc;
12936
12937 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12938
12939 if (!drmmode_crtc) {
12940 DRM_ERROR("no such CRTC id\n");
12941 return -ENOENT;
12942 }
12943
12944 crtc = to_intel_crtc(drmmode_crtc);
12945 pipe_from_crtc_id->pipe = crtc->pipe;
12946
12947 return 0;
12948 }
12949
12950 static int intel_encoder_clones(struct intel_encoder *encoder)
12951 {
12952 struct drm_device *dev = encoder->base.dev;
12953 struct intel_encoder *source_encoder;
12954 int index_mask = 0;
12955 int entry = 0;
12956
12957 for_each_intel_encoder(dev, source_encoder) {
12958 if (encoders_cloneable(encoder, source_encoder))
12959 index_mask |= (1 << entry);
12960
12961 entry++;
12962 }
12963
12964 return index_mask;
12965 }
12966
12967 static bool has_edp_a(struct drm_device *dev)
12968 {
12969 struct drm_i915_private *dev_priv = dev->dev_private;
12970
12971 if (!IS_MOBILE(dev))
12972 return false;
12973
12974 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12975 return false;
12976
12977 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12978 return false;
12979
12980 return true;
12981 }
12982
12983 static bool intel_crt_present(struct drm_device *dev)
12984 {
12985 struct drm_i915_private *dev_priv = dev->dev_private;
12986
12987 if (INTEL_INFO(dev)->gen >= 9)
12988 return false;
12989
12990 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12991 return false;
12992
12993 if (IS_CHERRYVIEW(dev))
12994 return false;
12995
12996 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12997 return false;
12998
12999 return true;
13000 }
13001
13002 static void intel_setup_outputs(struct drm_device *dev)
13003 {
13004 struct drm_i915_private *dev_priv = dev->dev_private;
13005 struct intel_encoder *encoder;
13006 struct drm_connector *connector;
13007 bool dpd_is_edp = false;
13008
13009 intel_lvds_init(dev);
13010
13011 if (intel_crt_present(dev))
13012 intel_crt_init(dev);
13013
13014 if (HAS_DDI(dev)) {
13015 int found;
13016
13017 /*
13018 * Haswell uses DDI functions to detect digital outputs.
13019 * On SKL pre-D0 the strap isn't connected, so we assume
13020 * it's there.
13021 */
13022 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
13023 /* WaIgnoreDDIAStrap: skl */
13024 if (found ||
13025 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
13026 intel_ddi_init(dev, PORT_A);
13027
13028 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13029 * register */
13030 found = I915_READ(SFUSE_STRAP);
13031
13032 if (found & SFUSE_STRAP_DDIB_DETECTED)
13033 intel_ddi_init(dev, PORT_B);
13034 if (found & SFUSE_STRAP_DDIC_DETECTED)
13035 intel_ddi_init(dev, PORT_C);
13036 if (found & SFUSE_STRAP_DDID_DETECTED)
13037 intel_ddi_init(dev, PORT_D);
13038 } else if (HAS_PCH_SPLIT(dev)) {
13039 int found;
13040 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
13041
13042 if (has_edp_a(dev))
13043 intel_dp_init(dev, DP_A, PORT_A);
13044
13045 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
13046 /* PCH SDVOB multiplex with HDMIB */
13047 found = intel_sdvo_init(dev, PCH_SDVOB, true);
13048 if (!found)
13049 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
13050 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
13051 intel_dp_init(dev, PCH_DP_B, PORT_B);
13052 }
13053
13054 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
13055 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
13056
13057 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
13058 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
13059
13060 if (I915_READ(PCH_DP_C) & DP_DETECTED)
13061 intel_dp_init(dev, PCH_DP_C, PORT_C);
13062
13063 if (I915_READ(PCH_DP_D) & DP_DETECTED)
13064 intel_dp_init(dev, PCH_DP_D, PORT_D);
13065 } else if (IS_VALLEYVIEW(dev)) {
13066 /*
13067 * The DP_DETECTED bit is the latched state of the DDC
13068 * SDA pin at boot. However since eDP doesn't require DDC
13069 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13070 * eDP ports may have been muxed to an alternate function.
13071 * Thus we can't rely on the DP_DETECTED bit alone to detect
13072 * eDP ports. Consult the VBT as well as DP_DETECTED to
13073 * detect eDP ports.
13074 */
13075 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
13076 !intel_dp_is_edp(dev, PORT_B))
13077 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
13078 PORT_B);
13079 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
13080 intel_dp_is_edp(dev, PORT_B))
13081 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
13082
13083 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
13084 !intel_dp_is_edp(dev, PORT_C))
13085 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
13086 PORT_C);
13087 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
13088 intel_dp_is_edp(dev, PORT_C))
13089 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
13090
13091 if (IS_CHERRYVIEW(dev)) {
13092 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
13093 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
13094 PORT_D);
13095 /* eDP not supported on port D, so don't check VBT */
13096 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
13097 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
13098 }
13099
13100 intel_dsi_init(dev);
13101 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
13102 bool found = false;
13103
13104 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13105 DRM_DEBUG_KMS("probing SDVOB\n");
13106 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
13107 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
13108 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
13109 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
13110 }
13111
13112 if (!found && SUPPORTS_INTEGRATED_DP(dev))
13113 intel_dp_init(dev, DP_B, PORT_B);
13114 }
13115
13116 /* Before G4X SDVOC doesn't have its own detect register */
13117
13118 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13119 DRM_DEBUG_KMS("probing SDVOC\n");
13120 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
13121 }
13122
13123 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
13124
13125 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
13126 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
13127 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
13128 }
13129 if (SUPPORTS_INTEGRATED_DP(dev))
13130 intel_dp_init(dev, DP_C, PORT_C);
13131 }
13132
13133 if (SUPPORTS_INTEGRATED_DP(dev) &&
13134 (I915_READ(DP_D) & DP_DETECTED))
13135 intel_dp_init(dev, DP_D, PORT_D);
13136 } else if (IS_GEN2(dev))
13137 intel_dvo_init(dev);
13138
13139 if (SUPPORTS_TV(dev))
13140 intel_tv_init(dev);
13141
13142 /*
13143 * FIXME: We don't have full atomic support yet, but we want to be
13144 * able to enable/test plane updates via the atomic interface in the
13145 * meantime. However as soon as we flip DRIVER_ATOMIC on, the DRM core
13146 * will take some atomic codepaths to lookup properties during
13147 * drmModeGetConnector() that unconditionally dereference
13148 * connector->state.
13149 *
13150 * We create a dummy connector state here for each connector to ensure
13151 * the DRM core doesn't try to dereference a NULL connector->state.
13152 * The actual connector properties will never be updated or contain
13153 * useful information, but since we're doing this specifically for
13154 * testing/debug of the plane operations (and only when a specific
13155 * kernel module option is given), that shouldn't really matter.
13156 *
13157 * We are also relying on these states to convert the legacy mode set
13158 * to use a drm_atomic_state struct. The states are kept consistent
13159 * with actual state, so that it is safe to rely on that instead of
13160 * the staged config.
13161 *
13162 * Once atomic support for crtc's + connectors lands, this loop should
13163 * be removed since we'll be setting up real connector state, which
13164 * will contain Intel-specific properties.
13165 */
13166 list_for_each_entry(connector,
13167 &dev->mode_config.connector_list,
13168 head) {
13169 if (!WARN_ON(connector->state)) {
13170 connector->state = kzalloc(sizeof(*connector->state),
13171 GFP_KERNEL);
13172 }
13173 }
13174
13175 intel_psr_init(dev);
13176
13177 for_each_intel_encoder(dev, encoder) {
13178 encoder->base.possible_crtcs = encoder->crtc_mask;
13179 encoder->base.possible_clones =
13180 intel_encoder_clones(encoder);
13181 }
13182
13183 intel_init_pch_refclk(dev);
13184
13185 drm_helper_move_panel_connectors_to_head(dev);
13186 }
13187
13188 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
13189 {
13190 struct drm_device *dev = fb->dev;
13191 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13192
13193 drm_framebuffer_cleanup(fb);
13194 mutex_lock(&dev->struct_mutex);
13195 WARN_ON(!intel_fb->obj->framebuffer_references--);
13196 drm_gem_object_unreference(&intel_fb->obj->base);
13197 mutex_unlock(&dev->struct_mutex);
13198 kfree(intel_fb);
13199 }
13200
13201 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
13202 struct drm_file *file,
13203 unsigned int *handle)
13204 {
13205 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13206 struct drm_i915_gem_object *obj = intel_fb->obj;
13207
13208 return drm_gem_handle_create(file, &obj->base, handle);
13209 }
13210
13211 static const struct drm_framebuffer_funcs intel_fb_funcs = {
13212 .destroy = intel_user_framebuffer_destroy,
13213 .create_handle = intel_user_framebuffer_create_handle,
13214 };
13215
13216 static
13217 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
13218 uint32_t pixel_format)
13219 {
13220 u32 gen = INTEL_INFO(dev)->gen;
13221
13222 if (gen >= 9) {
13223 /* "The stride in bytes must not exceed the of the size of 8K
13224 * pixels and 32K bytes."
13225 */
13226 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
13227 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
13228 return 32*1024;
13229 } else if (gen >= 4) {
13230 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13231 return 16*1024;
13232 else
13233 return 32*1024;
13234 } else if (gen >= 3) {
13235 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13236 return 8*1024;
13237 else
13238 return 16*1024;
13239 } else {
13240 /* XXX DSPC is limited to 4k tiled */
13241 return 8*1024;
13242 }
13243 }
13244
13245 static int intel_framebuffer_init(struct drm_device *dev,
13246 struct intel_framebuffer *intel_fb,
13247 struct drm_mode_fb_cmd2 *mode_cmd,
13248 struct drm_i915_gem_object *obj)
13249 {
13250 unsigned int aligned_height;
13251 int ret;
13252 u32 pitch_limit, stride_alignment;
13253
13254 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
13255
13256 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
13257 /* Enforce that fb modifier and tiling mode match, but only for
13258 * X-tiled. This is needed for FBC. */
13259 if (!!(obj->tiling_mode == I915_TILING_X) !=
13260 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
13261 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
13262 return -EINVAL;
13263 }
13264 } else {
13265 if (obj->tiling_mode == I915_TILING_X)
13266 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
13267 else if (obj->tiling_mode == I915_TILING_Y) {
13268 DRM_DEBUG("No Y tiling for legacy addfb\n");
13269 return -EINVAL;
13270 }
13271 }
13272
13273 /* Passed in modifier sanity checking. */
13274 switch (mode_cmd->modifier[0]) {
13275 case I915_FORMAT_MOD_Y_TILED:
13276 case I915_FORMAT_MOD_Yf_TILED:
13277 if (INTEL_INFO(dev)->gen < 9) {
13278 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
13279 mode_cmd->modifier[0]);
13280 return -EINVAL;
13281 }
13282 case DRM_FORMAT_MOD_NONE:
13283 case I915_FORMAT_MOD_X_TILED:
13284 break;
13285 default:
13286 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
13287 mode_cmd->modifier[0]);
13288 return -EINVAL;
13289 }
13290
13291 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
13292 mode_cmd->pixel_format);
13293 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
13294 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
13295 mode_cmd->pitches[0], stride_alignment);
13296 return -EINVAL;
13297 }
13298
13299 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
13300 mode_cmd->pixel_format);
13301 if (mode_cmd->pitches[0] > pitch_limit) {
13302 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
13303 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
13304 "tiled" : "linear",
13305 mode_cmd->pitches[0], pitch_limit);
13306 return -EINVAL;
13307 }
13308
13309 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
13310 mode_cmd->pitches[0] != obj->stride) {
13311 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
13312 mode_cmd->pitches[0], obj->stride);
13313 return -EINVAL;
13314 }
13315
13316 /* Reject formats not supported by any plane early. */
13317 switch (mode_cmd->pixel_format) {
13318 case DRM_FORMAT_C8:
13319 case DRM_FORMAT_RGB565:
13320 case DRM_FORMAT_XRGB8888:
13321 case DRM_FORMAT_ARGB8888:
13322 break;
13323 case DRM_FORMAT_XRGB1555:
13324 case DRM_FORMAT_ARGB1555:
13325 if (INTEL_INFO(dev)->gen > 3) {
13326 DRM_DEBUG("unsupported pixel format: %s\n",
13327 drm_get_format_name(mode_cmd->pixel_format));
13328 return -EINVAL;
13329 }
13330 break;
13331 case DRM_FORMAT_XBGR8888:
13332 case DRM_FORMAT_ABGR8888:
13333 case DRM_FORMAT_XRGB2101010:
13334 case DRM_FORMAT_ARGB2101010:
13335 case DRM_FORMAT_XBGR2101010:
13336 case DRM_FORMAT_ABGR2101010:
13337 if (INTEL_INFO(dev)->gen < 4) {
13338 DRM_DEBUG("unsupported pixel format: %s\n",
13339 drm_get_format_name(mode_cmd->pixel_format));
13340 return -EINVAL;
13341 }
13342 break;
13343 case DRM_FORMAT_YUYV:
13344 case DRM_FORMAT_UYVY:
13345 case DRM_FORMAT_YVYU:
13346 case DRM_FORMAT_VYUY:
13347 if (INTEL_INFO(dev)->gen < 5) {
13348 DRM_DEBUG("unsupported pixel format: %s\n",
13349 drm_get_format_name(mode_cmd->pixel_format));
13350 return -EINVAL;
13351 }
13352 break;
13353 default:
13354 DRM_DEBUG("unsupported pixel format: %s\n",
13355 drm_get_format_name(mode_cmd->pixel_format));
13356 return -EINVAL;
13357 }
13358
13359 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
13360 if (mode_cmd->offsets[0] != 0)
13361 return -EINVAL;
13362
13363 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
13364 mode_cmd->pixel_format,
13365 mode_cmd->modifier[0]);
13366 /* FIXME drm helper for size checks (especially planar formats)? */
13367 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
13368 return -EINVAL;
13369
13370 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
13371 intel_fb->obj = obj;
13372 intel_fb->obj->framebuffer_references++;
13373
13374 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
13375 if (ret) {
13376 DRM_ERROR("framebuffer init failed %d\n", ret);
13377 return ret;
13378 }
13379
13380 return 0;
13381 }
13382
13383 static struct drm_framebuffer *
13384 intel_user_framebuffer_create(struct drm_device *dev,
13385 struct drm_file *filp,
13386 struct drm_mode_fb_cmd2 *mode_cmd)
13387 {
13388 struct drm_i915_gem_object *obj;
13389
13390 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
13391 mode_cmd->handles[0]));
13392 if (&obj->base == NULL)
13393 return ERR_PTR(-ENOENT);
13394
13395 return intel_framebuffer_create(dev, mode_cmd, obj);
13396 }
13397
13398 #ifndef CONFIG_DRM_I915_FBDEV
13399 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
13400 {
13401 }
13402 #endif
13403
13404 static const struct drm_mode_config_funcs intel_mode_funcs = {
13405 .fb_create = intel_user_framebuffer_create,
13406 .output_poll_changed = intel_fbdev_output_poll_changed,
13407 .atomic_check = intel_atomic_check,
13408 .atomic_commit = intel_atomic_commit,
13409 };
13410
13411 /* Set up chip specific display functions */
13412 static void intel_init_display(struct drm_device *dev)
13413 {
13414 struct drm_i915_private *dev_priv = dev->dev_private;
13415
13416 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
13417 dev_priv->display.find_dpll = g4x_find_best_dpll;
13418 else if (IS_CHERRYVIEW(dev))
13419 dev_priv->display.find_dpll = chv_find_best_dpll;
13420 else if (IS_VALLEYVIEW(dev))
13421 dev_priv->display.find_dpll = vlv_find_best_dpll;
13422 else if (IS_PINEVIEW(dev))
13423 dev_priv->display.find_dpll = pnv_find_best_dpll;
13424 else
13425 dev_priv->display.find_dpll = i9xx_find_best_dpll;
13426
13427 if (INTEL_INFO(dev)->gen >= 9) {
13428 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
13429 dev_priv->display.get_initial_plane_config =
13430 skylake_get_initial_plane_config;
13431 dev_priv->display.crtc_compute_clock =
13432 haswell_crtc_compute_clock;
13433 dev_priv->display.crtc_enable = haswell_crtc_enable;
13434 dev_priv->display.crtc_disable = haswell_crtc_disable;
13435 dev_priv->display.off = ironlake_crtc_off;
13436 dev_priv->display.update_primary_plane =
13437 skylake_update_primary_plane;
13438 } else if (HAS_DDI(dev)) {
13439 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
13440 dev_priv->display.get_initial_plane_config =
13441 ironlake_get_initial_plane_config;
13442 dev_priv->display.crtc_compute_clock =
13443 haswell_crtc_compute_clock;
13444 dev_priv->display.crtc_enable = haswell_crtc_enable;
13445 dev_priv->display.crtc_disable = haswell_crtc_disable;
13446 dev_priv->display.off = ironlake_crtc_off;
13447 dev_priv->display.update_primary_plane =
13448 ironlake_update_primary_plane;
13449 } else if (HAS_PCH_SPLIT(dev)) {
13450 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
13451 dev_priv->display.get_initial_plane_config =
13452 ironlake_get_initial_plane_config;
13453 dev_priv->display.crtc_compute_clock =
13454 ironlake_crtc_compute_clock;
13455 dev_priv->display.crtc_enable = ironlake_crtc_enable;
13456 dev_priv->display.crtc_disable = ironlake_crtc_disable;
13457 dev_priv->display.off = ironlake_crtc_off;
13458 dev_priv->display.update_primary_plane =
13459 ironlake_update_primary_plane;
13460 } else if (IS_VALLEYVIEW(dev)) {
13461 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13462 dev_priv->display.get_initial_plane_config =
13463 i9xx_get_initial_plane_config;
13464 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
13465 dev_priv->display.crtc_enable = valleyview_crtc_enable;
13466 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13467 dev_priv->display.off = i9xx_crtc_off;
13468 dev_priv->display.update_primary_plane =
13469 i9xx_update_primary_plane;
13470 } else {
13471 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13472 dev_priv->display.get_initial_plane_config =
13473 i9xx_get_initial_plane_config;
13474 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
13475 dev_priv->display.crtc_enable = i9xx_crtc_enable;
13476 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13477 dev_priv->display.off = i9xx_crtc_off;
13478 dev_priv->display.update_primary_plane =
13479 i9xx_update_primary_plane;
13480 }
13481
13482 /* Returns the core display clock speed */
13483 if (IS_VALLEYVIEW(dev))
13484 dev_priv->display.get_display_clock_speed =
13485 valleyview_get_display_clock_speed;
13486 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
13487 dev_priv->display.get_display_clock_speed =
13488 i945_get_display_clock_speed;
13489 else if (IS_I915G(dev))
13490 dev_priv->display.get_display_clock_speed =
13491 i915_get_display_clock_speed;
13492 else if (IS_I945GM(dev) || IS_845G(dev))
13493 dev_priv->display.get_display_clock_speed =
13494 i9xx_misc_get_display_clock_speed;
13495 else if (IS_PINEVIEW(dev))
13496 dev_priv->display.get_display_clock_speed =
13497 pnv_get_display_clock_speed;
13498 else if (IS_I915GM(dev))
13499 dev_priv->display.get_display_clock_speed =
13500 i915gm_get_display_clock_speed;
13501 else if (IS_I865G(dev))
13502 dev_priv->display.get_display_clock_speed =
13503 i865_get_display_clock_speed;
13504 else if (IS_I85X(dev))
13505 dev_priv->display.get_display_clock_speed =
13506 i855_get_display_clock_speed;
13507 else /* 852, 830 */
13508 dev_priv->display.get_display_clock_speed =
13509 i830_get_display_clock_speed;
13510
13511 if (IS_GEN5(dev)) {
13512 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
13513 } else if (IS_GEN6(dev)) {
13514 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
13515 } else if (IS_IVYBRIDGE(dev)) {
13516 /* FIXME: detect B0+ stepping and use auto training */
13517 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
13518 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
13519 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
13520 } else if (IS_VALLEYVIEW(dev)) {
13521 dev_priv->display.modeset_global_resources =
13522 valleyview_modeset_global_resources;
13523 }
13524
13525 switch (INTEL_INFO(dev)->gen) {
13526 case 2:
13527 dev_priv->display.queue_flip = intel_gen2_queue_flip;
13528 break;
13529
13530 case 3:
13531 dev_priv->display.queue_flip = intel_gen3_queue_flip;
13532 break;
13533
13534 case 4:
13535 case 5:
13536 dev_priv->display.queue_flip = intel_gen4_queue_flip;
13537 break;
13538
13539 case 6:
13540 dev_priv->display.queue_flip = intel_gen6_queue_flip;
13541 break;
13542 case 7:
13543 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
13544 dev_priv->display.queue_flip = intel_gen7_queue_flip;
13545 break;
13546 case 9:
13547 /* Drop through - unsupported since execlist only. */
13548 default:
13549 /* Default just returns -ENODEV to indicate unsupported */
13550 dev_priv->display.queue_flip = intel_default_queue_flip;
13551 }
13552
13553 intel_panel_init_backlight_funcs(dev);
13554
13555 mutex_init(&dev_priv->pps_mutex);
13556 }
13557
13558 /*
13559 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
13560 * resume, or other times. This quirk makes sure that's the case for
13561 * affected systems.
13562 */
13563 static void quirk_pipea_force(struct drm_device *dev)
13564 {
13565 struct drm_i915_private *dev_priv = dev->dev_private;
13566
13567 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
13568 DRM_INFO("applying pipe a force quirk\n");
13569 }
13570
13571 static void quirk_pipeb_force(struct drm_device *dev)
13572 {
13573 struct drm_i915_private *dev_priv = dev->dev_private;
13574
13575 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
13576 DRM_INFO("applying pipe b force quirk\n");
13577 }
13578
13579 /*
13580 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
13581 */
13582 static void quirk_ssc_force_disable(struct drm_device *dev)
13583 {
13584 struct drm_i915_private *dev_priv = dev->dev_private;
13585 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
13586 DRM_INFO("applying lvds SSC disable quirk\n");
13587 }
13588
13589 /*
13590 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
13591 * brightness value
13592 */
13593 static void quirk_invert_brightness(struct drm_device *dev)
13594 {
13595 struct drm_i915_private *dev_priv = dev->dev_private;
13596 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
13597 DRM_INFO("applying inverted panel brightness quirk\n");
13598 }
13599
13600 /* Some VBT's incorrectly indicate no backlight is present */
13601 static void quirk_backlight_present(struct drm_device *dev)
13602 {
13603 struct drm_i915_private *dev_priv = dev->dev_private;
13604 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
13605 DRM_INFO("applying backlight present quirk\n");
13606 }
13607
13608 struct intel_quirk {
13609 int device;
13610 int subsystem_vendor;
13611 int subsystem_device;
13612 void (*hook)(struct drm_device *dev);
13613 };
13614
13615 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
13616 struct intel_dmi_quirk {
13617 void (*hook)(struct drm_device *dev);
13618 const struct dmi_system_id (*dmi_id_list)[];
13619 };
13620
13621 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
13622 {
13623 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
13624 return 1;
13625 }
13626
13627 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
13628 {
13629 .dmi_id_list = &(const struct dmi_system_id[]) {
13630 {
13631 .callback = intel_dmi_reverse_brightness,
13632 .ident = "NCR Corporation",
13633 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
13634 DMI_MATCH(DMI_PRODUCT_NAME, ""),
13635 },
13636 },
13637 { } /* terminating entry */
13638 },
13639 .hook = quirk_invert_brightness,
13640 },
13641 };
13642
13643 static struct intel_quirk intel_quirks[] = {
13644 /* HP Mini needs pipe A force quirk (LP: #322104) */
13645 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
13646
13647 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
13648 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
13649
13650 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
13651 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
13652
13653 /* 830 needs to leave pipe A & dpll A up */
13654 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
13655
13656 /* 830 needs to leave pipe B & dpll B up */
13657 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
13658
13659 /* Lenovo U160 cannot use SSC on LVDS */
13660 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
13661
13662 /* Sony Vaio Y cannot use SSC on LVDS */
13663 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
13664
13665 /* Acer Aspire 5734Z must invert backlight brightness */
13666 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
13667
13668 /* Acer/eMachines G725 */
13669 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
13670
13671 /* Acer/eMachines e725 */
13672 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
13673
13674 /* Acer/Packard Bell NCL20 */
13675 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
13676
13677 /* Acer Aspire 4736Z */
13678 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
13679
13680 /* Acer Aspire 5336 */
13681 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
13682
13683 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
13684 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
13685
13686 /* Acer C720 Chromebook (Core i3 4005U) */
13687 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
13688
13689 /* Apple Macbook 2,1 (Core 2 T7400) */
13690 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
13691
13692 /* Toshiba CB35 Chromebook (Celeron 2955U) */
13693 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
13694
13695 /* HP Chromebook 14 (Celeron 2955U) */
13696 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
13697
13698 /* Dell Chromebook 11 */
13699 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
13700 };
13701
13702 static void intel_init_quirks(struct drm_device *dev)
13703 {
13704 struct pci_dev *d = dev->pdev;
13705 int i;
13706
13707 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
13708 struct intel_quirk *q = &intel_quirks[i];
13709
13710 if (d->device == q->device &&
13711 (d->subsystem_vendor == q->subsystem_vendor ||
13712 q->subsystem_vendor == PCI_ANY_ID) &&
13713 (d->subsystem_device == q->subsystem_device ||
13714 q->subsystem_device == PCI_ANY_ID))
13715 q->hook(dev);
13716 }
13717 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
13718 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
13719 intel_dmi_quirks[i].hook(dev);
13720 }
13721 }
13722
13723 /* Disable the VGA plane that we never use */
13724 static void i915_disable_vga(struct drm_device *dev)
13725 {
13726 struct drm_i915_private *dev_priv = dev->dev_private;
13727 u8 sr1;
13728 u32 vga_reg = i915_vgacntrl_reg(dev);
13729
13730 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
13731 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
13732 outb(SR01, VGA_SR_INDEX);
13733 sr1 = inb(VGA_SR_DATA);
13734 outb(sr1 | 1<<5, VGA_SR_DATA);
13735 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
13736 udelay(300);
13737
13738 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
13739 POSTING_READ(vga_reg);
13740 }
13741
13742 void intel_modeset_init_hw(struct drm_device *dev)
13743 {
13744 intel_prepare_ddi(dev);
13745
13746 if (IS_VALLEYVIEW(dev))
13747 vlv_update_cdclk(dev);
13748
13749 intel_init_clock_gating(dev);
13750
13751 intel_enable_gt_powersave(dev);
13752 }
13753
13754 void intel_modeset_init(struct drm_device *dev)
13755 {
13756 struct drm_i915_private *dev_priv = dev->dev_private;
13757 int sprite, ret;
13758 enum pipe pipe;
13759 struct intel_crtc *crtc;
13760
13761 drm_mode_config_init(dev);
13762
13763 dev->mode_config.min_width = 0;
13764 dev->mode_config.min_height = 0;
13765
13766 dev->mode_config.preferred_depth = 24;
13767 dev->mode_config.prefer_shadow = 1;
13768
13769 dev->mode_config.allow_fb_modifiers = true;
13770
13771 dev->mode_config.funcs = &intel_mode_funcs;
13772
13773 intel_init_quirks(dev);
13774
13775 intel_init_pm(dev);
13776
13777 if (INTEL_INFO(dev)->num_pipes == 0)
13778 return;
13779
13780 intel_init_display(dev);
13781 intel_init_audio(dev);
13782
13783 if (IS_GEN2(dev)) {
13784 dev->mode_config.max_width = 2048;
13785 dev->mode_config.max_height = 2048;
13786 } else if (IS_GEN3(dev)) {
13787 dev->mode_config.max_width = 4096;
13788 dev->mode_config.max_height = 4096;
13789 } else {
13790 dev->mode_config.max_width = 8192;
13791 dev->mode_config.max_height = 8192;
13792 }
13793
13794 if (IS_845G(dev) || IS_I865G(dev)) {
13795 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
13796 dev->mode_config.cursor_height = 1023;
13797 } else if (IS_GEN2(dev)) {
13798 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
13799 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
13800 } else {
13801 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
13802 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
13803 }
13804
13805 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
13806
13807 DRM_DEBUG_KMS("%d display pipe%s available.\n",
13808 INTEL_INFO(dev)->num_pipes,
13809 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
13810
13811 for_each_pipe(dev_priv, pipe) {
13812 intel_crtc_init(dev, pipe);
13813 for_each_sprite(dev_priv, pipe, sprite) {
13814 ret = intel_plane_init(dev, pipe, sprite);
13815 if (ret)
13816 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
13817 pipe_name(pipe), sprite_name(pipe, sprite), ret);
13818 }
13819 }
13820
13821 intel_init_dpio(dev);
13822
13823 intel_shared_dpll_init(dev);
13824
13825 /* Just disable it once at startup */
13826 i915_disable_vga(dev);
13827 intel_setup_outputs(dev);
13828
13829 /* Just in case the BIOS is doing something questionable. */
13830 intel_fbc_disable(dev);
13831
13832 drm_modeset_lock_all(dev);
13833 intel_modeset_setup_hw_state(dev, false);
13834 drm_modeset_unlock_all(dev);
13835
13836 for_each_intel_crtc(dev, crtc) {
13837 if (!crtc->active)
13838 continue;
13839
13840 /*
13841 * Note that reserving the BIOS fb up front prevents us
13842 * from stuffing other stolen allocations like the ring
13843 * on top. This prevents some ugliness at boot time, and
13844 * can even allow for smooth boot transitions if the BIOS
13845 * fb is large enough for the active pipe configuration.
13846 */
13847 if (dev_priv->display.get_initial_plane_config) {
13848 dev_priv->display.get_initial_plane_config(crtc,
13849 &crtc->plane_config);
13850 /*
13851 * If the fb is shared between multiple heads, we'll
13852 * just get the first one.
13853 */
13854 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
13855 }
13856 }
13857 }
13858
13859 static void intel_enable_pipe_a(struct drm_device *dev)
13860 {
13861 struct intel_connector *connector;
13862 struct drm_connector *crt = NULL;
13863 struct intel_load_detect_pipe load_detect_temp;
13864 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
13865
13866 /* We can't just switch on the pipe A, we need to set things up with a
13867 * proper mode and output configuration. As a gross hack, enable pipe A
13868 * by enabling the load detect pipe once. */
13869 for_each_intel_connector(dev, connector) {
13870 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13871 crt = &connector->base;
13872 break;
13873 }
13874 }
13875
13876 if (!crt)
13877 return;
13878
13879 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13880 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
13881 }
13882
13883 static bool
13884 intel_check_plane_mapping(struct intel_crtc *crtc)
13885 {
13886 struct drm_device *dev = crtc->base.dev;
13887 struct drm_i915_private *dev_priv = dev->dev_private;
13888 u32 reg, val;
13889
13890 if (INTEL_INFO(dev)->num_pipes == 1)
13891 return true;
13892
13893 reg = DSPCNTR(!crtc->plane);
13894 val = I915_READ(reg);
13895
13896 if ((val & DISPLAY_PLANE_ENABLE) &&
13897 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13898 return false;
13899
13900 return true;
13901 }
13902
13903 static void intel_sanitize_crtc(struct intel_crtc *crtc)
13904 {
13905 struct drm_device *dev = crtc->base.dev;
13906 struct drm_i915_private *dev_priv = dev->dev_private;
13907 u32 reg;
13908
13909 /* Clear any frame start delays used for debugging left by the BIOS */
13910 reg = PIPECONF(crtc->config->cpu_transcoder);
13911 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13912
13913 /* restore vblank interrupts to correct state */
13914 drm_crtc_vblank_reset(&crtc->base);
13915 if (crtc->active) {
13916 update_scanline_offset(crtc);
13917 drm_crtc_vblank_on(&crtc->base);
13918 }
13919
13920 /* We need to sanitize the plane -> pipe mapping first because this will
13921 * disable the crtc (and hence change the state) if it is wrong. Note
13922 * that gen4+ has a fixed plane -> pipe mapping. */
13923 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13924 struct intel_connector *connector;
13925 bool plane;
13926
13927 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13928 crtc->base.base.id);
13929
13930 /* Pipe has the wrong plane attached and the plane is active.
13931 * Temporarily change the plane mapping and disable everything
13932 * ... */
13933 plane = crtc->plane;
13934 crtc->plane = !plane;
13935 crtc->primary_enabled = true;
13936 dev_priv->display.crtc_disable(&crtc->base);
13937 crtc->plane = plane;
13938
13939 /* ... and break all links. */
13940 for_each_intel_connector(dev, connector) {
13941 if (connector->encoder->base.crtc != &crtc->base)
13942 continue;
13943
13944 connector->base.dpms = DRM_MODE_DPMS_OFF;
13945 connector->base.encoder = NULL;
13946 }
13947 /* multiple connectors may have the same encoder:
13948 * handle them and break crtc link separately */
13949 for_each_intel_connector(dev, connector)
13950 if (connector->encoder->base.crtc == &crtc->base) {
13951 connector->encoder->base.crtc = NULL;
13952 connector->encoder->connectors_active = false;
13953 }
13954
13955 WARN_ON(crtc->active);
13956 crtc->base.state->enable = false;
13957 crtc->base.enabled = false;
13958 }
13959
13960 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13961 crtc->pipe == PIPE_A && !crtc->active) {
13962 /* BIOS forgot to enable pipe A, this mostly happens after
13963 * resume. Force-enable the pipe to fix this, the update_dpms
13964 * call below we restore the pipe to the right state, but leave
13965 * the required bits on. */
13966 intel_enable_pipe_a(dev);
13967 }
13968
13969 /* Adjust the state of the output pipe according to whether we
13970 * have active connectors/encoders. */
13971 intel_crtc_update_dpms(&crtc->base);
13972
13973 if (crtc->active != crtc->base.state->enable) {
13974 struct intel_encoder *encoder;
13975
13976 /* This can happen either due to bugs in the get_hw_state
13977 * functions or because the pipe is force-enabled due to the
13978 * pipe A quirk. */
13979 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13980 crtc->base.base.id,
13981 crtc->base.state->enable ? "enabled" : "disabled",
13982 crtc->active ? "enabled" : "disabled");
13983
13984 crtc->base.state->enable = crtc->active;
13985 crtc->base.enabled = crtc->active;
13986
13987 /* Because we only establish the connector -> encoder ->
13988 * crtc links if something is active, this means the
13989 * crtc is now deactivated. Break the links. connector
13990 * -> encoder links are only establish when things are
13991 * actually up, hence no need to break them. */
13992 WARN_ON(crtc->active);
13993
13994 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13995 WARN_ON(encoder->connectors_active);
13996 encoder->base.crtc = NULL;
13997 }
13998 }
13999
14000 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
14001 /*
14002 * We start out with underrun reporting disabled to avoid races.
14003 * For correct bookkeeping mark this on active crtcs.
14004 *
14005 * Also on gmch platforms we dont have any hardware bits to
14006 * disable the underrun reporting. Which means we need to start
14007 * out with underrun reporting disabled also on inactive pipes,
14008 * since otherwise we'll complain about the garbage we read when
14009 * e.g. coming up after runtime pm.
14010 *
14011 * No protection against concurrent access is required - at
14012 * worst a fifo underrun happens which also sets this to false.
14013 */
14014 crtc->cpu_fifo_underrun_disabled = true;
14015 crtc->pch_fifo_underrun_disabled = true;
14016 }
14017 }
14018
14019 static void intel_sanitize_encoder(struct intel_encoder *encoder)
14020 {
14021 struct intel_connector *connector;
14022 struct drm_device *dev = encoder->base.dev;
14023
14024 /* We need to check both for a crtc link (meaning that the
14025 * encoder is active and trying to read from a pipe) and the
14026 * pipe itself being active. */
14027 bool has_active_crtc = encoder->base.crtc &&
14028 to_intel_crtc(encoder->base.crtc)->active;
14029
14030 if (encoder->connectors_active && !has_active_crtc) {
14031 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14032 encoder->base.base.id,
14033 encoder->base.name);
14034
14035 /* Connector is active, but has no active pipe. This is
14036 * fallout from our resume register restoring. Disable
14037 * the encoder manually again. */
14038 if (encoder->base.crtc) {
14039 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14040 encoder->base.base.id,
14041 encoder->base.name);
14042 encoder->disable(encoder);
14043 if (encoder->post_disable)
14044 encoder->post_disable(encoder);
14045 }
14046 encoder->base.crtc = NULL;
14047 encoder->connectors_active = false;
14048
14049 /* Inconsistent output/port/pipe state happens presumably due to
14050 * a bug in one of the get_hw_state functions. Or someplace else
14051 * in our code, like the register restore mess on resume. Clamp
14052 * things to off as a safer default. */
14053 for_each_intel_connector(dev, connector) {
14054 if (connector->encoder != encoder)
14055 continue;
14056 connector->base.dpms = DRM_MODE_DPMS_OFF;
14057 connector->base.encoder = NULL;
14058 }
14059 }
14060 /* Enabled encoders without active connectors will be fixed in
14061 * the crtc fixup. */
14062 }
14063
14064 void i915_redisable_vga_power_on(struct drm_device *dev)
14065 {
14066 struct drm_i915_private *dev_priv = dev->dev_private;
14067 u32 vga_reg = i915_vgacntrl_reg(dev);
14068
14069 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
14070 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14071 i915_disable_vga(dev);
14072 }
14073 }
14074
14075 void i915_redisable_vga(struct drm_device *dev)
14076 {
14077 struct drm_i915_private *dev_priv = dev->dev_private;
14078
14079 /* This function can be called both from intel_modeset_setup_hw_state or
14080 * at a very early point in our resume sequence, where the power well
14081 * structures are not yet restored. Since this function is at a very
14082 * paranoid "someone might have enabled VGA while we were not looking"
14083 * level, just check if the power well is enabled instead of trying to
14084 * follow the "don't touch the power well if we don't need it" policy
14085 * the rest of the driver uses. */
14086 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
14087 return;
14088
14089 i915_redisable_vga_power_on(dev);
14090 }
14091
14092 static bool primary_get_hw_state(struct intel_crtc *crtc)
14093 {
14094 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
14095
14096 if (!crtc->active)
14097 return false;
14098
14099 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
14100 }
14101
14102 static void intel_modeset_readout_hw_state(struct drm_device *dev)
14103 {
14104 struct drm_i915_private *dev_priv = dev->dev_private;
14105 enum pipe pipe;
14106 struct intel_crtc *crtc;
14107 struct intel_encoder *encoder;
14108 struct intel_connector *connector;
14109 int i;
14110
14111 for_each_intel_crtc(dev, crtc) {
14112 memset(crtc->config, 0, sizeof(*crtc->config));
14113
14114 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
14115
14116 crtc->active = dev_priv->display.get_pipe_config(crtc,
14117 crtc->config);
14118
14119 crtc->base.state->enable = crtc->active;
14120 crtc->base.enabled = crtc->active;
14121 crtc->primary_enabled = primary_get_hw_state(crtc);
14122
14123 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
14124 crtc->base.base.id,
14125 crtc->active ? "enabled" : "disabled");
14126 }
14127
14128 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14129 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14130
14131 pll->on = pll->get_hw_state(dev_priv, pll,
14132 &pll->config.hw_state);
14133 pll->active = 0;
14134 pll->config.crtc_mask = 0;
14135 for_each_intel_crtc(dev, crtc) {
14136 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
14137 pll->active++;
14138 pll->config.crtc_mask |= 1 << crtc->pipe;
14139 }
14140 }
14141
14142 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
14143 pll->name, pll->config.crtc_mask, pll->on);
14144
14145 if (pll->config.crtc_mask)
14146 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
14147 }
14148
14149 for_each_intel_encoder(dev, encoder) {
14150 pipe = 0;
14151
14152 if (encoder->get_hw_state(encoder, &pipe)) {
14153 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
14154 encoder->base.crtc = &crtc->base;
14155 encoder->get_config(encoder, crtc->config);
14156 } else {
14157 encoder->base.crtc = NULL;
14158 }
14159
14160 encoder->connectors_active = false;
14161 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
14162 encoder->base.base.id,
14163 encoder->base.name,
14164 encoder->base.crtc ? "enabled" : "disabled",
14165 pipe_name(pipe));
14166 }
14167
14168 for_each_intel_connector(dev, connector) {
14169 if (connector->get_hw_state(connector)) {
14170 connector->base.dpms = DRM_MODE_DPMS_ON;
14171 connector->encoder->connectors_active = true;
14172 connector->base.encoder = &connector->encoder->base;
14173 } else {
14174 connector->base.dpms = DRM_MODE_DPMS_OFF;
14175 connector->base.encoder = NULL;
14176 }
14177 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
14178 connector->base.base.id,
14179 connector->base.name,
14180 connector->base.encoder ? "enabled" : "disabled");
14181 }
14182 }
14183
14184 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
14185 * and i915 state tracking structures. */
14186 void intel_modeset_setup_hw_state(struct drm_device *dev,
14187 bool force_restore)
14188 {
14189 struct drm_i915_private *dev_priv = dev->dev_private;
14190 enum pipe pipe;
14191 struct intel_crtc *crtc;
14192 struct intel_encoder *encoder;
14193 int i;
14194
14195 intel_modeset_readout_hw_state(dev);
14196
14197 /*
14198 * Now that we have the config, copy it to each CRTC struct
14199 * Note that this could go away if we move to using crtc_config
14200 * checking everywhere.
14201 */
14202 for_each_intel_crtc(dev, crtc) {
14203 if (crtc->active && i915.fastboot) {
14204 intel_mode_from_pipe_config(&crtc->base.mode,
14205 crtc->config);
14206 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
14207 crtc->base.base.id);
14208 drm_mode_debug_printmodeline(&crtc->base.mode);
14209 }
14210 }
14211
14212 /* HW state is read out, now we need to sanitize this mess. */
14213 for_each_intel_encoder(dev, encoder) {
14214 intel_sanitize_encoder(encoder);
14215 }
14216
14217 for_each_pipe(dev_priv, pipe) {
14218 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
14219 intel_sanitize_crtc(crtc);
14220 intel_dump_pipe_config(crtc, crtc->config,
14221 "[setup_hw_state]");
14222 }
14223
14224 intel_modeset_update_connector_atomic_state(dev);
14225
14226 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14227 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14228
14229 if (!pll->on || pll->active)
14230 continue;
14231
14232 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
14233
14234 pll->disable(dev_priv, pll);
14235 pll->on = false;
14236 }
14237
14238 if (IS_GEN9(dev))
14239 skl_wm_get_hw_state(dev);
14240 else if (HAS_PCH_SPLIT(dev))
14241 ilk_wm_get_hw_state(dev);
14242
14243 if (force_restore) {
14244 i915_redisable_vga(dev);
14245
14246 /*
14247 * We need to use raw interfaces for restoring state to avoid
14248 * checking (bogus) intermediate states.
14249 */
14250 for_each_pipe(dev_priv, pipe) {
14251 struct drm_crtc *crtc =
14252 dev_priv->pipe_to_crtc_mapping[pipe];
14253
14254 intel_crtc_restore_mode(crtc);
14255 }
14256 } else {
14257 intel_modeset_update_staged_output_state(dev);
14258 }
14259
14260 intel_modeset_check_state(dev);
14261 }
14262
14263 void intel_modeset_gem_init(struct drm_device *dev)
14264 {
14265 struct drm_i915_private *dev_priv = dev->dev_private;
14266 struct drm_crtc *c;
14267 struct drm_i915_gem_object *obj;
14268
14269 mutex_lock(&dev->struct_mutex);
14270 intel_init_gt_powersave(dev);
14271 mutex_unlock(&dev->struct_mutex);
14272
14273 /*
14274 * There may be no VBT; and if the BIOS enabled SSC we can
14275 * just keep using it to avoid unnecessary flicker. Whereas if the
14276 * BIOS isn't using it, don't assume it will work even if the VBT
14277 * indicates as much.
14278 */
14279 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
14280 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14281 DREF_SSC1_ENABLE);
14282
14283 intel_modeset_init_hw(dev);
14284
14285 intel_setup_overlay(dev);
14286
14287 /*
14288 * Make sure any fbs we allocated at startup are properly
14289 * pinned & fenced. When we do the allocation it's too early
14290 * for this.
14291 */
14292 mutex_lock(&dev->struct_mutex);
14293 for_each_crtc(dev, c) {
14294 obj = intel_fb_obj(c->primary->fb);
14295 if (obj == NULL)
14296 continue;
14297
14298 if (intel_pin_and_fence_fb_obj(c->primary,
14299 c->primary->fb,
14300 c->primary->state,
14301 NULL)) {
14302 DRM_ERROR("failed to pin boot fb on pipe %d\n",
14303 to_intel_crtc(c)->pipe);
14304 drm_framebuffer_unreference(c->primary->fb);
14305 c->primary->fb = NULL;
14306 update_state_fb(c->primary);
14307 }
14308 }
14309 mutex_unlock(&dev->struct_mutex);
14310
14311 intel_backlight_register(dev);
14312 }
14313
14314 void intel_connector_unregister(struct intel_connector *intel_connector)
14315 {
14316 struct drm_connector *connector = &intel_connector->base;
14317
14318 intel_panel_destroy_backlight(connector);
14319 drm_connector_unregister(connector);
14320 }
14321
14322 void intel_modeset_cleanup(struct drm_device *dev)
14323 {
14324 struct drm_i915_private *dev_priv = dev->dev_private;
14325 struct drm_connector *connector;
14326
14327 intel_disable_gt_powersave(dev);
14328
14329 intel_backlight_unregister(dev);
14330
14331 /*
14332 * Interrupts and polling as the first thing to avoid creating havoc.
14333 * Too much stuff here (turning of connectors, ...) would
14334 * experience fancy races otherwise.
14335 */
14336 intel_irq_uninstall(dev_priv);
14337
14338 /*
14339 * Due to the hpd irq storm handling the hotplug work can re-arm the
14340 * poll handlers. Hence disable polling after hpd handling is shut down.
14341 */
14342 drm_kms_helper_poll_fini(dev);
14343
14344 mutex_lock(&dev->struct_mutex);
14345
14346 intel_unregister_dsm_handler();
14347
14348 intel_fbc_disable(dev);
14349
14350 mutex_unlock(&dev->struct_mutex);
14351
14352 /* flush any delayed tasks or pending work */
14353 flush_scheduled_work();
14354
14355 /* destroy the backlight and sysfs files before encoders/connectors */
14356 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
14357 struct intel_connector *intel_connector;
14358
14359 intel_connector = to_intel_connector(connector);
14360 intel_connector->unregister(intel_connector);
14361 }
14362
14363 drm_mode_config_cleanup(dev);
14364
14365 intel_cleanup_overlay(dev);
14366
14367 mutex_lock(&dev->struct_mutex);
14368 intel_cleanup_gt_powersave(dev);
14369 mutex_unlock(&dev->struct_mutex);
14370 }
14371
14372 /*
14373 * Return which encoder is currently attached for connector.
14374 */
14375 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
14376 {
14377 return &intel_attached_encoder(connector)->base;
14378 }
14379
14380 void intel_connector_attach_encoder(struct intel_connector *connector,
14381 struct intel_encoder *encoder)
14382 {
14383 connector->encoder = encoder;
14384 drm_mode_connector_attach_encoder(&connector->base,
14385 &encoder->base);
14386 }
14387
14388 /*
14389 * set vga decode state - true == enable VGA decode
14390 */
14391 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
14392 {
14393 struct drm_i915_private *dev_priv = dev->dev_private;
14394 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
14395 u16 gmch_ctrl;
14396
14397 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
14398 DRM_ERROR("failed to read control word\n");
14399 return -EIO;
14400 }
14401
14402 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
14403 return 0;
14404
14405 if (state)
14406 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
14407 else
14408 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
14409
14410 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
14411 DRM_ERROR("failed to write control word\n");
14412 return -EIO;
14413 }
14414
14415 return 0;
14416 }
14417
14418 struct intel_display_error_state {
14419
14420 u32 power_well_driver;
14421
14422 int num_transcoders;
14423
14424 struct intel_cursor_error_state {
14425 u32 control;
14426 u32 position;
14427 u32 base;
14428 u32 size;
14429 } cursor[I915_MAX_PIPES];
14430
14431 struct intel_pipe_error_state {
14432 bool power_domain_on;
14433 u32 source;
14434 u32 stat;
14435 } pipe[I915_MAX_PIPES];
14436
14437 struct intel_plane_error_state {
14438 u32 control;
14439 u32 stride;
14440 u32 size;
14441 u32 pos;
14442 u32 addr;
14443 u32 surface;
14444 u32 tile_offset;
14445 } plane[I915_MAX_PIPES];
14446
14447 struct intel_transcoder_error_state {
14448 bool power_domain_on;
14449 enum transcoder cpu_transcoder;
14450
14451 u32 conf;
14452
14453 u32 htotal;
14454 u32 hblank;
14455 u32 hsync;
14456 u32 vtotal;
14457 u32 vblank;
14458 u32 vsync;
14459 } transcoder[4];
14460 };
14461
14462 struct intel_display_error_state *
14463 intel_display_capture_error_state(struct drm_device *dev)
14464 {
14465 struct drm_i915_private *dev_priv = dev->dev_private;
14466 struct intel_display_error_state *error;
14467 int transcoders[] = {
14468 TRANSCODER_A,
14469 TRANSCODER_B,
14470 TRANSCODER_C,
14471 TRANSCODER_EDP,
14472 };
14473 int i;
14474
14475 if (INTEL_INFO(dev)->num_pipes == 0)
14476 return NULL;
14477
14478 error = kzalloc(sizeof(*error), GFP_ATOMIC);
14479 if (error == NULL)
14480 return NULL;
14481
14482 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
14483 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
14484
14485 for_each_pipe(dev_priv, i) {
14486 error->pipe[i].power_domain_on =
14487 __intel_display_power_is_enabled(dev_priv,
14488 POWER_DOMAIN_PIPE(i));
14489 if (!error->pipe[i].power_domain_on)
14490 continue;
14491
14492 error->cursor[i].control = I915_READ(CURCNTR(i));
14493 error->cursor[i].position = I915_READ(CURPOS(i));
14494 error->cursor[i].base = I915_READ(CURBASE(i));
14495
14496 error->plane[i].control = I915_READ(DSPCNTR(i));
14497 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
14498 if (INTEL_INFO(dev)->gen <= 3) {
14499 error->plane[i].size = I915_READ(DSPSIZE(i));
14500 error->plane[i].pos = I915_READ(DSPPOS(i));
14501 }
14502 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14503 error->plane[i].addr = I915_READ(DSPADDR(i));
14504 if (INTEL_INFO(dev)->gen >= 4) {
14505 error->plane[i].surface = I915_READ(DSPSURF(i));
14506 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
14507 }
14508
14509 error->pipe[i].source = I915_READ(PIPESRC(i));
14510
14511 if (HAS_GMCH_DISPLAY(dev))
14512 error->pipe[i].stat = I915_READ(PIPESTAT(i));
14513 }
14514
14515 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
14516 if (HAS_DDI(dev_priv->dev))
14517 error->num_transcoders++; /* Account for eDP. */
14518
14519 for (i = 0; i < error->num_transcoders; i++) {
14520 enum transcoder cpu_transcoder = transcoders[i];
14521
14522 error->transcoder[i].power_domain_on =
14523 __intel_display_power_is_enabled(dev_priv,
14524 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
14525 if (!error->transcoder[i].power_domain_on)
14526 continue;
14527
14528 error->transcoder[i].cpu_transcoder = cpu_transcoder;
14529
14530 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
14531 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
14532 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
14533 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
14534 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
14535 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
14536 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
14537 }
14538
14539 return error;
14540 }
14541
14542 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
14543
14544 void
14545 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
14546 struct drm_device *dev,
14547 struct intel_display_error_state *error)
14548 {
14549 struct drm_i915_private *dev_priv = dev->dev_private;
14550 int i;
14551
14552 if (!error)
14553 return;
14554
14555 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
14556 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
14557 err_printf(m, "PWR_WELL_CTL2: %08x\n",
14558 error->power_well_driver);
14559 for_each_pipe(dev_priv, i) {
14560 err_printf(m, "Pipe [%d]:\n", i);
14561 err_printf(m, " Power: %s\n",
14562 error->pipe[i].power_domain_on ? "on" : "off");
14563 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
14564 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
14565
14566 err_printf(m, "Plane [%d]:\n", i);
14567 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
14568 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
14569 if (INTEL_INFO(dev)->gen <= 3) {
14570 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
14571 err_printf(m, " POS: %08x\n", error->plane[i].pos);
14572 }
14573 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14574 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
14575 if (INTEL_INFO(dev)->gen >= 4) {
14576 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
14577 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
14578 }
14579
14580 err_printf(m, "Cursor [%d]:\n", i);
14581 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
14582 err_printf(m, " POS: %08x\n", error->cursor[i].position);
14583 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
14584 }
14585
14586 for (i = 0; i < error->num_transcoders; i++) {
14587 err_printf(m, "CPU transcoder: %c\n",
14588 transcoder_name(error->transcoder[i].cpu_transcoder));
14589 err_printf(m, " Power: %s\n",
14590 error->transcoder[i].power_domain_on ? "on" : "off");
14591 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
14592 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
14593 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
14594 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
14595 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
14596 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
14597 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
14598 }
14599 }
14600
14601 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
14602 {
14603 struct intel_crtc *crtc;
14604
14605 for_each_intel_crtc(dev, crtc) {
14606 struct intel_unpin_work *work;
14607
14608 spin_lock_irq(&dev->event_lock);
14609
14610 work = crtc->unpin_work;
14611
14612 if (work && work->event &&
14613 work->event->base.file_priv == file) {
14614 kfree(work->event);
14615 work->event = NULL;
14616 }
14617
14618 spin_unlock_irq(&dev->event_lock);
14619 }
14620 }
Linux kernel - Deliverables
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