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drm/i915: Pass intel_crtc to intel_disable_pipe() and intel_wait_for_pipe_off()
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_rect.h>
44 #include <linux/dma_remapping.h>
45
46 /* Primary plane formats supported by all gen */
47 #define COMMON_PRIMARY_FORMATS \
48 DRM_FORMAT_C8, \
49 DRM_FORMAT_RGB565, \
50 DRM_FORMAT_XRGB8888, \
51 DRM_FORMAT_ARGB8888
52
53 /* Primary plane formats for gen <= 3 */
54 static const uint32_t intel_primary_formats_gen2[] = {
55 COMMON_PRIMARY_FORMATS,
56 DRM_FORMAT_XRGB1555,
57 DRM_FORMAT_ARGB1555,
58 };
59
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t intel_primary_formats_gen4[] = {
62 COMMON_PRIMARY_FORMATS, \
63 DRM_FORMAT_XBGR8888,
64 DRM_FORMAT_ABGR8888,
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_ARGB2101010,
67 DRM_FORMAT_XBGR2101010,
68 DRM_FORMAT_ABGR2101010,
69 };
70
71 /* Cursor formats */
72 static const uint32_t intel_cursor_formats[] = {
73 DRM_FORMAT_ARGB8888,
74 };
75
76 #define DIV_ROUND_CLOSEST_ULL(ll, d) \
77 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
78
79 static void intel_increase_pllclock(struct drm_device *dev,
80 enum pipe pipe);
81 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
82
83 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
84 struct intel_crtc_config *pipe_config);
85 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
86 struct intel_crtc_config *pipe_config);
87
88 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
89 int x, int y, struct drm_framebuffer *old_fb);
90 static int intel_framebuffer_init(struct drm_device *dev,
91 struct intel_framebuffer *ifb,
92 struct drm_mode_fb_cmd2 *mode_cmd,
93 struct drm_i915_gem_object *obj);
94 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
95 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
96 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
97 struct intel_link_m_n *m_n,
98 struct intel_link_m_n *m2_n2);
99 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
100 static void haswell_set_pipeconf(struct drm_crtc *crtc);
101 static void intel_set_pipe_csc(struct drm_crtc *crtc);
102 static void vlv_prepare_pll(struct intel_crtc *crtc);
103 static void chv_prepare_pll(struct intel_crtc *crtc);
104
105 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
106 {
107 if (!connector->mst_port)
108 return connector->encoder;
109 else
110 return &connector->mst_port->mst_encoders[pipe]->base;
111 }
112
113 typedef struct {
114 int min, max;
115 } intel_range_t;
116
117 typedef struct {
118 int dot_limit;
119 int p2_slow, p2_fast;
120 } intel_p2_t;
121
122 typedef struct intel_limit intel_limit_t;
123 struct intel_limit {
124 intel_range_t dot, vco, n, m, m1, m2, p, p1;
125 intel_p2_t p2;
126 };
127
128 int
129 intel_pch_rawclk(struct drm_device *dev)
130 {
131 struct drm_i915_private *dev_priv = dev->dev_private;
132
133 WARN_ON(!HAS_PCH_SPLIT(dev));
134
135 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
136 }
137
138 static inline u32 /* units of 100MHz */
139 intel_fdi_link_freq(struct drm_device *dev)
140 {
141 if (IS_GEN5(dev)) {
142 struct drm_i915_private *dev_priv = dev->dev_private;
143 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
144 } else
145 return 27;
146 }
147
148 static const intel_limit_t intel_limits_i8xx_dac = {
149 .dot = { .min = 25000, .max = 350000 },
150 .vco = { .min = 908000, .max = 1512000 },
151 .n = { .min = 2, .max = 16 },
152 .m = { .min = 96, .max = 140 },
153 .m1 = { .min = 18, .max = 26 },
154 .m2 = { .min = 6, .max = 16 },
155 .p = { .min = 4, .max = 128 },
156 .p1 = { .min = 2, .max = 33 },
157 .p2 = { .dot_limit = 165000,
158 .p2_slow = 4, .p2_fast = 2 },
159 };
160
161 static const intel_limit_t intel_limits_i8xx_dvo = {
162 .dot = { .min = 25000, .max = 350000 },
163 .vco = { .min = 908000, .max = 1512000 },
164 .n = { .min = 2, .max = 16 },
165 .m = { .min = 96, .max = 140 },
166 .m1 = { .min = 18, .max = 26 },
167 .m2 = { .min = 6, .max = 16 },
168 .p = { .min = 4, .max = 128 },
169 .p1 = { .min = 2, .max = 33 },
170 .p2 = { .dot_limit = 165000,
171 .p2_slow = 4, .p2_fast = 4 },
172 };
173
174 static const intel_limit_t intel_limits_i8xx_lvds = {
175 .dot = { .min = 25000, .max = 350000 },
176 .vco = { .min = 908000, .max = 1512000 },
177 .n = { .min = 2, .max = 16 },
178 .m = { .min = 96, .max = 140 },
179 .m1 = { .min = 18, .max = 26 },
180 .m2 = { .min = 6, .max = 16 },
181 .p = { .min = 4, .max = 128 },
182 .p1 = { .min = 1, .max = 6 },
183 .p2 = { .dot_limit = 165000,
184 .p2_slow = 14, .p2_fast = 7 },
185 };
186
187 static const intel_limit_t intel_limits_i9xx_sdvo = {
188 .dot = { .min = 20000, .max = 400000 },
189 .vco = { .min = 1400000, .max = 2800000 },
190 .n = { .min = 1, .max = 6 },
191 .m = { .min = 70, .max = 120 },
192 .m1 = { .min = 8, .max = 18 },
193 .m2 = { .min = 3, .max = 7 },
194 .p = { .min = 5, .max = 80 },
195 .p1 = { .min = 1, .max = 8 },
196 .p2 = { .dot_limit = 200000,
197 .p2_slow = 10, .p2_fast = 5 },
198 };
199
200 static const intel_limit_t intel_limits_i9xx_lvds = {
201 .dot = { .min = 20000, .max = 400000 },
202 .vco = { .min = 1400000, .max = 2800000 },
203 .n = { .min = 1, .max = 6 },
204 .m = { .min = 70, .max = 120 },
205 .m1 = { .min = 8, .max = 18 },
206 .m2 = { .min = 3, .max = 7 },
207 .p = { .min = 7, .max = 98 },
208 .p1 = { .min = 1, .max = 8 },
209 .p2 = { .dot_limit = 112000,
210 .p2_slow = 14, .p2_fast = 7 },
211 };
212
213
214 static const intel_limit_t intel_limits_g4x_sdvo = {
215 .dot = { .min = 25000, .max = 270000 },
216 .vco = { .min = 1750000, .max = 3500000},
217 .n = { .min = 1, .max = 4 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 10, .max = 30 },
222 .p1 = { .min = 1, .max = 3},
223 .p2 = { .dot_limit = 270000,
224 .p2_slow = 10,
225 .p2_fast = 10
226 },
227 };
228
229 static const intel_limit_t intel_limits_g4x_hdmi = {
230 .dot = { .min = 22000, .max = 400000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 4 },
233 .m = { .min = 104, .max = 138 },
234 .m1 = { .min = 16, .max = 23 },
235 .m2 = { .min = 5, .max = 11 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8},
238 .p2 = { .dot_limit = 165000,
239 .p2_slow = 10, .p2_fast = 5 },
240 };
241
242 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
243 .dot = { .min = 20000, .max = 115000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 14, .p2_fast = 14
253 },
254 };
255
256 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
257 .dot = { .min = 80000, .max = 224000 },
258 .vco = { .min = 1750000, .max = 3500000 },
259 .n = { .min = 1, .max = 3 },
260 .m = { .min = 104, .max = 138 },
261 .m1 = { .min = 17, .max = 23 },
262 .m2 = { .min = 5, .max = 11 },
263 .p = { .min = 14, .max = 42 },
264 .p1 = { .min = 2, .max = 6 },
265 .p2 = { .dot_limit = 0,
266 .p2_slow = 7, .p2_fast = 7
267 },
268 };
269
270 static const intel_limit_t intel_limits_pineview_sdvo = {
271 .dot = { .min = 20000, .max = 400000},
272 .vco = { .min = 1700000, .max = 3500000 },
273 /* Pineview's Ncounter is a ring counter */
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 /* Pineview only has one combined m divider, which we treat as m2. */
277 .m1 = { .min = 0, .max = 0 },
278 .m2 = { .min = 0, .max = 254 },
279 .p = { .min = 5, .max = 80 },
280 .p1 = { .min = 1, .max = 8 },
281 .p2 = { .dot_limit = 200000,
282 .p2_slow = 10, .p2_fast = 5 },
283 };
284
285 static const intel_limit_t intel_limits_pineview_lvds = {
286 .dot = { .min = 20000, .max = 400000 },
287 .vco = { .min = 1700000, .max = 3500000 },
288 .n = { .min = 3, .max = 6 },
289 .m = { .min = 2, .max = 256 },
290 .m1 = { .min = 0, .max = 0 },
291 .m2 = { .min = 0, .max = 254 },
292 .p = { .min = 7, .max = 112 },
293 .p1 = { .min = 1, .max = 8 },
294 .p2 = { .dot_limit = 112000,
295 .p2_slow = 14, .p2_fast = 14 },
296 };
297
298 /* Ironlake / Sandybridge
299 *
300 * We calculate clock using (register_value + 2) for N/M1/M2, so here
301 * the range value for them is (actual_value - 2).
302 */
303 static const intel_limit_t intel_limits_ironlake_dac = {
304 .dot = { .min = 25000, .max = 350000 },
305 .vco = { .min = 1760000, .max = 3510000 },
306 .n = { .min = 1, .max = 5 },
307 .m = { .min = 79, .max = 127 },
308 .m1 = { .min = 12, .max = 22 },
309 .m2 = { .min = 5, .max = 9 },
310 .p = { .min = 5, .max = 80 },
311 .p1 = { .min = 1, .max = 8 },
312 .p2 = { .dot_limit = 225000,
313 .p2_slow = 10, .p2_fast = 5 },
314 };
315
316 static const intel_limit_t intel_limits_ironlake_single_lvds = {
317 .dot = { .min = 25000, .max = 350000 },
318 .vco = { .min = 1760000, .max = 3510000 },
319 .n = { .min = 1, .max = 3 },
320 .m = { .min = 79, .max = 118 },
321 .m1 = { .min = 12, .max = 22 },
322 .m2 = { .min = 5, .max = 9 },
323 .p = { .min = 28, .max = 112 },
324 .p1 = { .min = 2, .max = 8 },
325 .p2 = { .dot_limit = 225000,
326 .p2_slow = 14, .p2_fast = 14 },
327 };
328
329 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
330 .dot = { .min = 25000, .max = 350000 },
331 .vco = { .min = 1760000, .max = 3510000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 79, .max = 127 },
334 .m1 = { .min = 12, .max = 22 },
335 .m2 = { .min = 5, .max = 9 },
336 .p = { .min = 14, .max = 56 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 225000,
339 .p2_slow = 7, .p2_fast = 7 },
340 };
341
342 /* LVDS 100mhz refclk limits. */
343 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
344 .dot = { .min = 25000, .max = 350000 },
345 .vco = { .min = 1760000, .max = 3510000 },
346 .n = { .min = 1, .max = 2 },
347 .m = { .min = 79, .max = 126 },
348 .m1 = { .min = 12, .max = 22 },
349 .m2 = { .min = 5, .max = 9 },
350 .p = { .min = 28, .max = 112 },
351 .p1 = { .min = 2, .max = 8 },
352 .p2 = { .dot_limit = 225000,
353 .p2_slow = 14, .p2_fast = 14 },
354 };
355
356 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
357 .dot = { .min = 25000, .max = 350000 },
358 .vco = { .min = 1760000, .max = 3510000 },
359 .n = { .min = 1, .max = 3 },
360 .m = { .min = 79, .max = 126 },
361 .m1 = { .min = 12, .max = 22 },
362 .m2 = { .min = 5, .max = 9 },
363 .p = { .min = 14, .max = 42 },
364 .p1 = { .min = 2, .max = 6 },
365 .p2 = { .dot_limit = 225000,
366 .p2_slow = 7, .p2_fast = 7 },
367 };
368
369 static const intel_limit_t intel_limits_vlv = {
370 /*
371 * These are the data rate limits (measured in fast clocks)
372 * since those are the strictest limits we have. The fast
373 * clock and actual rate limits are more relaxed, so checking
374 * them would make no difference.
375 */
376 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m1 = { .min = 2, .max = 3 },
380 .m2 = { .min = 11, .max = 156 },
381 .p1 = { .min = 2, .max = 3 },
382 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
383 };
384
385 static const intel_limit_t intel_limits_chv = {
386 /*
387 * These are the data rate limits (measured in fast clocks)
388 * since those are the strictest limits we have. The fast
389 * clock and actual rate limits are more relaxed, so checking
390 * them would make no difference.
391 */
392 .dot = { .min = 25000 * 5, .max = 540000 * 5},
393 .vco = { .min = 4860000, .max = 6700000 },
394 .n = { .min = 1, .max = 1 },
395 .m1 = { .min = 2, .max = 2 },
396 .m2 = { .min = 24 << 22, .max = 175 << 22 },
397 .p1 = { .min = 2, .max = 4 },
398 .p2 = { .p2_slow = 1, .p2_fast = 14 },
399 };
400
401 static void vlv_clock(int refclk, intel_clock_t *clock)
402 {
403 clock->m = clock->m1 * clock->m2;
404 clock->p = clock->p1 * clock->p2;
405 if (WARN_ON(clock->n == 0 || clock->p == 0))
406 return;
407 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
408 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
409 }
410
411 /**
412 * Returns whether any output on the specified pipe is of the specified type
413 */
414 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
415 {
416 struct drm_device *dev = crtc->dev;
417 struct intel_encoder *encoder;
418
419 for_each_encoder_on_crtc(dev, crtc, encoder)
420 if (encoder->type == type)
421 return true;
422
423 return false;
424 }
425
426 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
427 int refclk)
428 {
429 struct drm_device *dev = crtc->dev;
430 const intel_limit_t *limit;
431
432 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
433 if (intel_is_dual_link_lvds(dev)) {
434 if (refclk == 100000)
435 limit = &intel_limits_ironlake_dual_lvds_100m;
436 else
437 limit = &intel_limits_ironlake_dual_lvds;
438 } else {
439 if (refclk == 100000)
440 limit = &intel_limits_ironlake_single_lvds_100m;
441 else
442 limit = &intel_limits_ironlake_single_lvds;
443 }
444 } else
445 limit = &intel_limits_ironlake_dac;
446
447 return limit;
448 }
449
450 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
451 {
452 struct drm_device *dev = crtc->dev;
453 const intel_limit_t *limit;
454
455 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
456 if (intel_is_dual_link_lvds(dev))
457 limit = &intel_limits_g4x_dual_channel_lvds;
458 else
459 limit = &intel_limits_g4x_single_channel_lvds;
460 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
461 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
462 limit = &intel_limits_g4x_hdmi;
463 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
464 limit = &intel_limits_g4x_sdvo;
465 } else /* The option is for other outputs */
466 limit = &intel_limits_i9xx_sdvo;
467
468 return limit;
469 }
470
471 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
472 {
473 struct drm_device *dev = crtc->dev;
474 const intel_limit_t *limit;
475
476 if (HAS_PCH_SPLIT(dev))
477 limit = intel_ironlake_limit(crtc, refclk);
478 else if (IS_G4X(dev)) {
479 limit = intel_g4x_limit(crtc);
480 } else if (IS_PINEVIEW(dev)) {
481 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
482 limit = &intel_limits_pineview_lvds;
483 else
484 limit = &intel_limits_pineview_sdvo;
485 } else if (IS_CHERRYVIEW(dev)) {
486 limit = &intel_limits_chv;
487 } else if (IS_VALLEYVIEW(dev)) {
488 limit = &intel_limits_vlv;
489 } else if (!IS_GEN2(dev)) {
490 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
491 limit = &intel_limits_i9xx_lvds;
492 else
493 limit = &intel_limits_i9xx_sdvo;
494 } else {
495 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
496 limit = &intel_limits_i8xx_lvds;
497 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
498 limit = &intel_limits_i8xx_dvo;
499 else
500 limit = &intel_limits_i8xx_dac;
501 }
502 return limit;
503 }
504
505 /* m1 is reserved as 0 in Pineview, n is a ring counter */
506 static void pineview_clock(int refclk, intel_clock_t *clock)
507 {
508 clock->m = clock->m2 + 2;
509 clock->p = clock->p1 * clock->p2;
510 if (WARN_ON(clock->n == 0 || clock->p == 0))
511 return;
512 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
513 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
514 }
515
516 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
517 {
518 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
519 }
520
521 static void i9xx_clock(int refclk, intel_clock_t *clock)
522 {
523 clock->m = i9xx_dpll_compute_m(clock);
524 clock->p = clock->p1 * clock->p2;
525 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
526 return;
527 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
528 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
529 }
530
531 static void chv_clock(int refclk, intel_clock_t *clock)
532 {
533 clock->m = clock->m1 * clock->m2;
534 clock->p = clock->p1 * clock->p2;
535 if (WARN_ON(clock->n == 0 || clock->p == 0))
536 return;
537 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
538 clock->n << 22);
539 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
540 }
541
542 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
543 /**
544 * Returns whether the given set of divisors are valid for a given refclk with
545 * the given connectors.
546 */
547
548 static bool intel_PLL_is_valid(struct drm_device *dev,
549 const intel_limit_t *limit,
550 const intel_clock_t *clock)
551 {
552 if (clock->n < limit->n.min || limit->n.max < clock->n)
553 INTELPllInvalid("n out of range\n");
554 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
555 INTELPllInvalid("p1 out of range\n");
556 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
557 INTELPllInvalid("m2 out of range\n");
558 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
559 INTELPllInvalid("m1 out of range\n");
560
561 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
562 if (clock->m1 <= clock->m2)
563 INTELPllInvalid("m1 <= m2\n");
564
565 if (!IS_VALLEYVIEW(dev)) {
566 if (clock->p < limit->p.min || limit->p.max < clock->p)
567 INTELPllInvalid("p out of range\n");
568 if (clock->m < limit->m.min || limit->m.max < clock->m)
569 INTELPllInvalid("m out of range\n");
570 }
571
572 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
573 INTELPllInvalid("vco out of range\n");
574 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
575 * connector, etc., rather than just a single range.
576 */
577 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
578 INTELPllInvalid("dot out of range\n");
579
580 return true;
581 }
582
583 static bool
584 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
585 int target, int refclk, intel_clock_t *match_clock,
586 intel_clock_t *best_clock)
587 {
588 struct drm_device *dev = crtc->dev;
589 intel_clock_t clock;
590 int err = target;
591
592 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
593 /*
594 * For LVDS just rely on its current settings for dual-channel.
595 * We haven't figured out how to reliably set up different
596 * single/dual channel state, if we even can.
597 */
598 if (intel_is_dual_link_lvds(dev))
599 clock.p2 = limit->p2.p2_fast;
600 else
601 clock.p2 = limit->p2.p2_slow;
602 } else {
603 if (target < limit->p2.dot_limit)
604 clock.p2 = limit->p2.p2_slow;
605 else
606 clock.p2 = limit->p2.p2_fast;
607 }
608
609 memset(best_clock, 0, sizeof(*best_clock));
610
611 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
612 clock.m1++) {
613 for (clock.m2 = limit->m2.min;
614 clock.m2 <= limit->m2.max; clock.m2++) {
615 if (clock.m2 >= clock.m1)
616 break;
617 for (clock.n = limit->n.min;
618 clock.n <= limit->n.max; clock.n++) {
619 for (clock.p1 = limit->p1.min;
620 clock.p1 <= limit->p1.max; clock.p1++) {
621 int this_err;
622
623 i9xx_clock(refclk, &clock);
624 if (!intel_PLL_is_valid(dev, limit,
625 &clock))
626 continue;
627 if (match_clock &&
628 clock.p != match_clock->p)
629 continue;
630
631 this_err = abs(clock.dot - target);
632 if (this_err < err) {
633 *best_clock = clock;
634 err = this_err;
635 }
636 }
637 }
638 }
639 }
640
641 return (err != target);
642 }
643
644 static bool
645 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
646 int target, int refclk, intel_clock_t *match_clock,
647 intel_clock_t *best_clock)
648 {
649 struct drm_device *dev = crtc->dev;
650 intel_clock_t clock;
651 int err = target;
652
653 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
654 /*
655 * For LVDS just rely on its current settings for dual-channel.
656 * We haven't figured out how to reliably set up different
657 * single/dual channel state, if we even can.
658 */
659 if (intel_is_dual_link_lvds(dev))
660 clock.p2 = limit->p2.p2_fast;
661 else
662 clock.p2 = limit->p2.p2_slow;
663 } else {
664 if (target < limit->p2.dot_limit)
665 clock.p2 = limit->p2.p2_slow;
666 else
667 clock.p2 = limit->p2.p2_fast;
668 }
669
670 memset(best_clock, 0, sizeof(*best_clock));
671
672 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
673 clock.m1++) {
674 for (clock.m2 = limit->m2.min;
675 clock.m2 <= limit->m2.max; clock.m2++) {
676 for (clock.n = limit->n.min;
677 clock.n <= limit->n.max; clock.n++) {
678 for (clock.p1 = limit->p1.min;
679 clock.p1 <= limit->p1.max; clock.p1++) {
680 int this_err;
681
682 pineview_clock(refclk, &clock);
683 if (!intel_PLL_is_valid(dev, limit,
684 &clock))
685 continue;
686 if (match_clock &&
687 clock.p != match_clock->p)
688 continue;
689
690 this_err = abs(clock.dot - target);
691 if (this_err < err) {
692 *best_clock = clock;
693 err = this_err;
694 }
695 }
696 }
697 }
698 }
699
700 return (err != target);
701 }
702
703 static bool
704 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
705 int target, int refclk, intel_clock_t *match_clock,
706 intel_clock_t *best_clock)
707 {
708 struct drm_device *dev = crtc->dev;
709 intel_clock_t clock;
710 int max_n;
711 bool found;
712 /* approximately equals target * 0.00585 */
713 int err_most = (target >> 8) + (target >> 9);
714 found = false;
715
716 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
717 if (intel_is_dual_link_lvds(dev))
718 clock.p2 = limit->p2.p2_fast;
719 else
720 clock.p2 = limit->p2.p2_slow;
721 } else {
722 if (target < limit->p2.dot_limit)
723 clock.p2 = limit->p2.p2_slow;
724 else
725 clock.p2 = limit->p2.p2_fast;
726 }
727
728 memset(best_clock, 0, sizeof(*best_clock));
729 max_n = limit->n.max;
730 /* based on hardware requirement, prefer smaller n to precision */
731 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
732 /* based on hardware requirement, prefere larger m1,m2 */
733 for (clock.m1 = limit->m1.max;
734 clock.m1 >= limit->m1.min; clock.m1--) {
735 for (clock.m2 = limit->m2.max;
736 clock.m2 >= limit->m2.min; clock.m2--) {
737 for (clock.p1 = limit->p1.max;
738 clock.p1 >= limit->p1.min; clock.p1--) {
739 int this_err;
740
741 i9xx_clock(refclk, &clock);
742 if (!intel_PLL_is_valid(dev, limit,
743 &clock))
744 continue;
745
746 this_err = abs(clock.dot - target);
747 if (this_err < err_most) {
748 *best_clock = clock;
749 err_most = this_err;
750 max_n = clock.n;
751 found = true;
752 }
753 }
754 }
755 }
756 }
757 return found;
758 }
759
760 static bool
761 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
762 int target, int refclk, intel_clock_t *match_clock,
763 intel_clock_t *best_clock)
764 {
765 struct drm_device *dev = crtc->dev;
766 intel_clock_t clock;
767 unsigned int bestppm = 1000000;
768 /* min update 19.2 MHz */
769 int max_n = min(limit->n.max, refclk / 19200);
770 bool found = false;
771
772 target *= 5; /* fast clock */
773
774 memset(best_clock, 0, sizeof(*best_clock));
775
776 /* based on hardware requirement, prefer smaller n to precision */
777 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
778 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
779 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
780 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
781 clock.p = clock.p1 * clock.p2;
782 /* based on hardware requirement, prefer bigger m1,m2 values */
783 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
784 unsigned int ppm, diff;
785
786 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
787 refclk * clock.m1);
788
789 vlv_clock(refclk, &clock);
790
791 if (!intel_PLL_is_valid(dev, limit,
792 &clock))
793 continue;
794
795 diff = abs(clock.dot - target);
796 ppm = div_u64(1000000ULL * diff, target);
797
798 if (ppm < 100 && clock.p > best_clock->p) {
799 bestppm = 0;
800 *best_clock = clock;
801 found = true;
802 }
803
804 if (bestppm >= 10 && ppm < bestppm - 10) {
805 bestppm = ppm;
806 *best_clock = clock;
807 found = true;
808 }
809 }
810 }
811 }
812 }
813
814 return found;
815 }
816
817 static bool
818 chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
819 int target, int refclk, intel_clock_t *match_clock,
820 intel_clock_t *best_clock)
821 {
822 struct drm_device *dev = crtc->dev;
823 intel_clock_t clock;
824 uint64_t m2;
825 int found = false;
826
827 memset(best_clock, 0, sizeof(*best_clock));
828
829 /*
830 * Based on hardware doc, the n always set to 1, and m1 always
831 * set to 2. If requires to support 200Mhz refclk, we need to
832 * revisit this because n may not 1 anymore.
833 */
834 clock.n = 1, clock.m1 = 2;
835 target *= 5; /* fast clock */
836
837 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
838 for (clock.p2 = limit->p2.p2_fast;
839 clock.p2 >= limit->p2.p2_slow;
840 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
841
842 clock.p = clock.p1 * clock.p2;
843
844 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
845 clock.n) << 22, refclk * clock.m1);
846
847 if (m2 > INT_MAX/clock.m1)
848 continue;
849
850 clock.m2 = m2;
851
852 chv_clock(refclk, &clock);
853
854 if (!intel_PLL_is_valid(dev, limit, &clock))
855 continue;
856
857 /* based on hardware requirement, prefer bigger p
858 */
859 if (clock.p > best_clock->p) {
860 *best_clock = clock;
861 found = true;
862 }
863 }
864 }
865
866 return found;
867 }
868
869 bool intel_crtc_active(struct drm_crtc *crtc)
870 {
871 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
872
873 /* Be paranoid as we can arrive here with only partial
874 * state retrieved from the hardware during setup.
875 *
876 * We can ditch the adjusted_mode.crtc_clock check as soon
877 * as Haswell has gained clock readout/fastboot support.
878 *
879 * We can ditch the crtc->primary->fb check as soon as we can
880 * properly reconstruct framebuffers.
881 */
882 return intel_crtc->active && crtc->primary->fb &&
883 intel_crtc->config.adjusted_mode.crtc_clock;
884 }
885
886 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
887 enum pipe pipe)
888 {
889 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
890 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
891
892 return intel_crtc->config.cpu_transcoder;
893 }
894
895 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
896 {
897 struct drm_i915_private *dev_priv = dev->dev_private;
898 u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
899
900 frame = I915_READ(frame_reg);
901
902 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
903 WARN(1, "vblank wait on pipe %c timed out\n",
904 pipe_name(pipe));
905 }
906
907 /**
908 * intel_wait_for_vblank - wait for vblank on a given pipe
909 * @dev: drm device
910 * @pipe: pipe to wait for
911 *
912 * Wait for vblank to occur on a given pipe. Needed for various bits of
913 * mode setting code.
914 */
915 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
916 {
917 struct drm_i915_private *dev_priv = dev->dev_private;
918 int pipestat_reg = PIPESTAT(pipe);
919
920 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
921 g4x_wait_for_vblank(dev, pipe);
922 return;
923 }
924
925 /* Clear existing vblank status. Note this will clear any other
926 * sticky status fields as well.
927 *
928 * This races with i915_driver_irq_handler() with the result
929 * that either function could miss a vblank event. Here it is not
930 * fatal, as we will either wait upon the next vblank interrupt or
931 * timeout. Generally speaking intel_wait_for_vblank() is only
932 * called during modeset at which time the GPU should be idle and
933 * should *not* be performing page flips and thus not waiting on
934 * vblanks...
935 * Currently, the result of us stealing a vblank from the irq
936 * handler is that a single frame will be skipped during swapbuffers.
937 */
938 I915_WRITE(pipestat_reg,
939 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
940
941 /* Wait for vblank interrupt bit to set */
942 if (wait_for(I915_READ(pipestat_reg) &
943 PIPE_VBLANK_INTERRUPT_STATUS,
944 50))
945 DRM_DEBUG_KMS("vblank wait on pipe %c timed out\n",
946 pipe_name(pipe));
947 }
948
949 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
950 {
951 struct drm_i915_private *dev_priv = dev->dev_private;
952 u32 reg = PIPEDSL(pipe);
953 u32 line1, line2;
954 u32 line_mask;
955
956 if (IS_GEN2(dev))
957 line_mask = DSL_LINEMASK_GEN2;
958 else
959 line_mask = DSL_LINEMASK_GEN3;
960
961 line1 = I915_READ(reg) & line_mask;
962 mdelay(5);
963 line2 = I915_READ(reg) & line_mask;
964
965 return line1 == line2;
966 }
967
968 /*
969 * intel_wait_for_pipe_off - wait for pipe to turn off
970 * @crtc: crtc whose pipe to wait for
971 *
972 * After disabling a pipe, we can't wait for vblank in the usual way,
973 * spinning on the vblank interrupt status bit, since we won't actually
974 * see an interrupt when the pipe is disabled.
975 *
976 * On Gen4 and above:
977 * wait for the pipe register state bit to turn off
978 *
979 * Otherwise:
980 * wait for the display line value to settle (it usually
981 * ends up stopping at the start of the next frame).
982 *
983 */
984 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
985 {
986 struct drm_device *dev = crtc->base.dev;
987 struct drm_i915_private *dev_priv = dev->dev_private;
988 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
989 enum pipe pipe = crtc->pipe;
990
991 if (INTEL_INFO(dev)->gen >= 4) {
992 int reg = PIPECONF(cpu_transcoder);
993
994 /* Wait for the Pipe State to go off */
995 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
996 100))
997 WARN(1, "pipe_off wait timed out\n");
998 } else {
999 /* Wait for the display line to settle */
1000 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1001 WARN(1, "pipe_off wait timed out\n");
1002 }
1003 }
1004
1005 /*
1006 * ibx_digital_port_connected - is the specified port connected?
1007 * @dev_priv: i915 private structure
1008 * @port: the port to test
1009 *
1010 * Returns true if @port is connected, false otherwise.
1011 */
1012 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1013 struct intel_digital_port *port)
1014 {
1015 u32 bit;
1016
1017 if (HAS_PCH_IBX(dev_priv->dev)) {
1018 switch (port->port) {
1019 case PORT_B:
1020 bit = SDE_PORTB_HOTPLUG;
1021 break;
1022 case PORT_C:
1023 bit = SDE_PORTC_HOTPLUG;
1024 break;
1025 case PORT_D:
1026 bit = SDE_PORTD_HOTPLUG;
1027 break;
1028 default:
1029 return true;
1030 }
1031 } else {
1032 switch (port->port) {
1033 case PORT_B:
1034 bit = SDE_PORTB_HOTPLUG_CPT;
1035 break;
1036 case PORT_C:
1037 bit = SDE_PORTC_HOTPLUG_CPT;
1038 break;
1039 case PORT_D:
1040 bit = SDE_PORTD_HOTPLUG_CPT;
1041 break;
1042 default:
1043 return true;
1044 }
1045 }
1046
1047 return I915_READ(SDEISR) & bit;
1048 }
1049
1050 static const char *state_string(bool enabled)
1051 {
1052 return enabled ? "on" : "off";
1053 }
1054
1055 /* Only for pre-ILK configs */
1056 void assert_pll(struct drm_i915_private *dev_priv,
1057 enum pipe pipe, bool state)
1058 {
1059 int reg;
1060 u32 val;
1061 bool cur_state;
1062
1063 reg = DPLL(pipe);
1064 val = I915_READ(reg);
1065 cur_state = !!(val & DPLL_VCO_ENABLE);
1066 WARN(cur_state != state,
1067 "PLL state assertion failure (expected %s, current %s)\n",
1068 state_string(state), state_string(cur_state));
1069 }
1070
1071 /* XXX: the dsi pll is shared between MIPI DSI ports */
1072 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1073 {
1074 u32 val;
1075 bool cur_state;
1076
1077 mutex_lock(&dev_priv->dpio_lock);
1078 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1079 mutex_unlock(&dev_priv->dpio_lock);
1080
1081 cur_state = val & DSI_PLL_VCO_EN;
1082 WARN(cur_state != state,
1083 "DSI PLL state assertion failure (expected %s, current %s)\n",
1084 state_string(state), state_string(cur_state));
1085 }
1086 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1087 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1088
1089 struct intel_shared_dpll *
1090 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1091 {
1092 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1093
1094 if (crtc->config.shared_dpll < 0)
1095 return NULL;
1096
1097 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1098 }
1099
1100 /* For ILK+ */
1101 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1102 struct intel_shared_dpll *pll,
1103 bool state)
1104 {
1105 bool cur_state;
1106 struct intel_dpll_hw_state hw_state;
1107
1108 if (WARN (!pll,
1109 "asserting DPLL %s with no DPLL\n", state_string(state)))
1110 return;
1111
1112 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1113 WARN(cur_state != state,
1114 "%s assertion failure (expected %s, current %s)\n",
1115 pll->name, state_string(state), state_string(cur_state));
1116 }
1117
1118 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1119 enum pipe pipe, bool state)
1120 {
1121 int reg;
1122 u32 val;
1123 bool cur_state;
1124 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1125 pipe);
1126
1127 if (HAS_DDI(dev_priv->dev)) {
1128 /* DDI does not have a specific FDI_TX register */
1129 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1130 val = I915_READ(reg);
1131 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1132 } else {
1133 reg = FDI_TX_CTL(pipe);
1134 val = I915_READ(reg);
1135 cur_state = !!(val & FDI_TX_ENABLE);
1136 }
1137 WARN(cur_state != state,
1138 "FDI TX state assertion failure (expected %s, current %s)\n",
1139 state_string(state), state_string(cur_state));
1140 }
1141 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1142 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1143
1144 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1145 enum pipe pipe, bool state)
1146 {
1147 int reg;
1148 u32 val;
1149 bool cur_state;
1150
1151 reg = FDI_RX_CTL(pipe);
1152 val = I915_READ(reg);
1153 cur_state = !!(val & FDI_RX_ENABLE);
1154 WARN(cur_state != state,
1155 "FDI RX state assertion failure (expected %s, current %s)\n",
1156 state_string(state), state_string(cur_state));
1157 }
1158 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1159 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1160
1161 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1162 enum pipe pipe)
1163 {
1164 int reg;
1165 u32 val;
1166
1167 /* ILK FDI PLL is always enabled */
1168 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1169 return;
1170
1171 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1172 if (HAS_DDI(dev_priv->dev))
1173 return;
1174
1175 reg = FDI_TX_CTL(pipe);
1176 val = I915_READ(reg);
1177 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1178 }
1179
1180 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1181 enum pipe pipe, bool state)
1182 {
1183 int reg;
1184 u32 val;
1185 bool cur_state;
1186
1187 reg = FDI_RX_CTL(pipe);
1188 val = I915_READ(reg);
1189 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1190 WARN(cur_state != state,
1191 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1192 state_string(state), state_string(cur_state));
1193 }
1194
1195 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1196 enum pipe pipe)
1197 {
1198 struct drm_device *dev = dev_priv->dev;
1199 int pp_reg;
1200 u32 val;
1201 enum pipe panel_pipe = PIPE_A;
1202 bool locked = true;
1203
1204 if (WARN_ON(HAS_DDI(dev)))
1205 return;
1206
1207 if (HAS_PCH_SPLIT(dev)) {
1208 u32 port_sel;
1209
1210 pp_reg = PCH_PP_CONTROL;
1211 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1212
1213 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1214 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1215 panel_pipe = PIPE_B;
1216 /* XXX: else fix for eDP */
1217 } else if (IS_VALLEYVIEW(dev)) {
1218 /* presumably write lock depends on pipe, not port select */
1219 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1220 panel_pipe = pipe;
1221 } else {
1222 pp_reg = PP_CONTROL;
1223 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1224 panel_pipe = PIPE_B;
1225 }
1226
1227 val = I915_READ(pp_reg);
1228 if (!(val & PANEL_POWER_ON) ||
1229 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1230 locked = false;
1231
1232 WARN(panel_pipe == pipe && locked,
1233 "panel assertion failure, pipe %c regs locked\n",
1234 pipe_name(pipe));
1235 }
1236
1237 static void assert_cursor(struct drm_i915_private *dev_priv,
1238 enum pipe pipe, bool state)
1239 {
1240 struct drm_device *dev = dev_priv->dev;
1241 bool cur_state;
1242
1243 if (IS_845G(dev) || IS_I865G(dev))
1244 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1245 else
1246 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1247
1248 WARN(cur_state != state,
1249 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1250 pipe_name(pipe), state_string(state), state_string(cur_state));
1251 }
1252 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1253 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1254
1255 void assert_pipe(struct drm_i915_private *dev_priv,
1256 enum pipe pipe, bool state)
1257 {
1258 int reg;
1259 u32 val;
1260 bool cur_state;
1261 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1262 pipe);
1263
1264 /* if we need the pipe A quirk it must be always on */
1265 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1266 state = true;
1267
1268 if (!intel_display_power_enabled(dev_priv,
1269 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1270 cur_state = false;
1271 } else {
1272 reg = PIPECONF(cpu_transcoder);
1273 val = I915_READ(reg);
1274 cur_state = !!(val & PIPECONF_ENABLE);
1275 }
1276
1277 WARN(cur_state != state,
1278 "pipe %c assertion failure (expected %s, current %s)\n",
1279 pipe_name(pipe), state_string(state), state_string(cur_state));
1280 }
1281
1282 static void assert_plane(struct drm_i915_private *dev_priv,
1283 enum plane plane, bool state)
1284 {
1285 int reg;
1286 u32 val;
1287 bool cur_state;
1288
1289 reg = DSPCNTR(plane);
1290 val = I915_READ(reg);
1291 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1292 WARN(cur_state != state,
1293 "plane %c assertion failure (expected %s, current %s)\n",
1294 plane_name(plane), state_string(state), state_string(cur_state));
1295 }
1296
1297 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1298 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1299
1300 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1301 enum pipe pipe)
1302 {
1303 struct drm_device *dev = dev_priv->dev;
1304 int reg, i;
1305 u32 val;
1306 int cur_pipe;
1307
1308 /* Primary planes are fixed to pipes on gen4+ */
1309 if (INTEL_INFO(dev)->gen >= 4) {
1310 reg = DSPCNTR(pipe);
1311 val = I915_READ(reg);
1312 WARN(val & DISPLAY_PLANE_ENABLE,
1313 "plane %c assertion failure, should be disabled but not\n",
1314 plane_name(pipe));
1315 return;
1316 }
1317
1318 /* Need to check both planes against the pipe */
1319 for_each_pipe(dev_priv, i) {
1320 reg = DSPCNTR(i);
1321 val = I915_READ(reg);
1322 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1323 DISPPLANE_SEL_PIPE_SHIFT;
1324 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1325 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1326 plane_name(i), pipe_name(pipe));
1327 }
1328 }
1329
1330 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1331 enum pipe pipe)
1332 {
1333 struct drm_device *dev = dev_priv->dev;
1334 int reg, sprite;
1335 u32 val;
1336
1337 if (IS_VALLEYVIEW(dev)) {
1338 for_each_sprite(pipe, sprite) {
1339 reg = SPCNTR(pipe, sprite);
1340 val = I915_READ(reg);
1341 WARN(val & SP_ENABLE,
1342 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1343 sprite_name(pipe, sprite), pipe_name(pipe));
1344 }
1345 } else if (INTEL_INFO(dev)->gen >= 7) {
1346 reg = SPRCTL(pipe);
1347 val = I915_READ(reg);
1348 WARN(val & SPRITE_ENABLE,
1349 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1350 plane_name(pipe), pipe_name(pipe));
1351 } else if (INTEL_INFO(dev)->gen >= 5) {
1352 reg = DVSCNTR(pipe);
1353 val = I915_READ(reg);
1354 WARN(val & DVS_ENABLE,
1355 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1356 plane_name(pipe), pipe_name(pipe));
1357 }
1358 }
1359
1360 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1361 {
1362 u32 val;
1363 bool enabled;
1364
1365 WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1366
1367 val = I915_READ(PCH_DREF_CONTROL);
1368 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1369 DREF_SUPERSPREAD_SOURCE_MASK));
1370 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1371 }
1372
1373 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1374 enum pipe pipe)
1375 {
1376 int reg;
1377 u32 val;
1378 bool enabled;
1379
1380 reg = PCH_TRANSCONF(pipe);
1381 val = I915_READ(reg);
1382 enabled = !!(val & TRANS_ENABLE);
1383 WARN(enabled,
1384 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1385 pipe_name(pipe));
1386 }
1387
1388 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1389 enum pipe pipe, u32 port_sel, u32 val)
1390 {
1391 if ((val & DP_PORT_EN) == 0)
1392 return false;
1393
1394 if (HAS_PCH_CPT(dev_priv->dev)) {
1395 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1396 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1397 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1398 return false;
1399 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1400 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1401 return false;
1402 } else {
1403 if ((val & DP_PIPE_MASK) != (pipe << 30))
1404 return false;
1405 }
1406 return true;
1407 }
1408
1409 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1410 enum pipe pipe, u32 val)
1411 {
1412 if ((val & SDVO_ENABLE) == 0)
1413 return false;
1414
1415 if (HAS_PCH_CPT(dev_priv->dev)) {
1416 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1417 return false;
1418 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1419 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1420 return false;
1421 } else {
1422 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1423 return false;
1424 }
1425 return true;
1426 }
1427
1428 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1429 enum pipe pipe, u32 val)
1430 {
1431 if ((val & LVDS_PORT_EN) == 0)
1432 return false;
1433
1434 if (HAS_PCH_CPT(dev_priv->dev)) {
1435 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1436 return false;
1437 } else {
1438 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1439 return false;
1440 }
1441 return true;
1442 }
1443
1444 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1445 enum pipe pipe, u32 val)
1446 {
1447 if ((val & ADPA_DAC_ENABLE) == 0)
1448 return false;
1449 if (HAS_PCH_CPT(dev_priv->dev)) {
1450 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1451 return false;
1452 } else {
1453 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1454 return false;
1455 }
1456 return true;
1457 }
1458
1459 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1460 enum pipe pipe, int reg, u32 port_sel)
1461 {
1462 u32 val = I915_READ(reg);
1463 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1464 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1465 reg, pipe_name(pipe));
1466
1467 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1468 && (val & DP_PIPEB_SELECT),
1469 "IBX PCH dp port still using transcoder B\n");
1470 }
1471
1472 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1473 enum pipe pipe, int reg)
1474 {
1475 u32 val = I915_READ(reg);
1476 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1477 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1478 reg, pipe_name(pipe));
1479
1480 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1481 && (val & SDVO_PIPE_B_SELECT),
1482 "IBX PCH hdmi port still using transcoder B\n");
1483 }
1484
1485 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1486 enum pipe pipe)
1487 {
1488 int reg;
1489 u32 val;
1490
1491 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1492 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1493 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1494
1495 reg = PCH_ADPA;
1496 val = I915_READ(reg);
1497 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1498 "PCH VGA enabled on transcoder %c, should be disabled\n",
1499 pipe_name(pipe));
1500
1501 reg = PCH_LVDS;
1502 val = I915_READ(reg);
1503 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1504 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1505 pipe_name(pipe));
1506
1507 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1508 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1509 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1510 }
1511
1512 static void intel_init_dpio(struct drm_device *dev)
1513 {
1514 struct drm_i915_private *dev_priv = dev->dev_private;
1515
1516 if (!IS_VALLEYVIEW(dev))
1517 return;
1518
1519 /*
1520 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1521 * CHV x1 PHY (DP/HDMI D)
1522 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1523 */
1524 if (IS_CHERRYVIEW(dev)) {
1525 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1526 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1527 } else {
1528 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1529 }
1530 }
1531
1532 static void vlv_enable_pll(struct intel_crtc *crtc)
1533 {
1534 struct drm_device *dev = crtc->base.dev;
1535 struct drm_i915_private *dev_priv = dev->dev_private;
1536 int reg = DPLL(crtc->pipe);
1537 u32 dpll = crtc->config.dpll_hw_state.dpll;
1538
1539 assert_pipe_disabled(dev_priv, crtc->pipe);
1540
1541 /* No really, not for ILK+ */
1542 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1543
1544 /* PLL is protected by panel, make sure we can write it */
1545 if (IS_MOBILE(dev_priv->dev))
1546 assert_panel_unlocked(dev_priv, crtc->pipe);
1547
1548 I915_WRITE(reg, dpll);
1549 POSTING_READ(reg);
1550 udelay(150);
1551
1552 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1553 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1554
1555 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1556 POSTING_READ(DPLL_MD(crtc->pipe));
1557
1558 /* We do this three times for luck */
1559 I915_WRITE(reg, dpll);
1560 POSTING_READ(reg);
1561 udelay(150); /* wait for warmup */
1562 I915_WRITE(reg, dpll);
1563 POSTING_READ(reg);
1564 udelay(150); /* wait for warmup */
1565 I915_WRITE(reg, dpll);
1566 POSTING_READ(reg);
1567 udelay(150); /* wait for warmup */
1568 }
1569
1570 static void chv_enable_pll(struct intel_crtc *crtc)
1571 {
1572 struct drm_device *dev = crtc->base.dev;
1573 struct drm_i915_private *dev_priv = dev->dev_private;
1574 int pipe = crtc->pipe;
1575 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1576 u32 tmp;
1577
1578 assert_pipe_disabled(dev_priv, crtc->pipe);
1579
1580 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1581
1582 mutex_lock(&dev_priv->dpio_lock);
1583
1584 /* Enable back the 10bit clock to display controller */
1585 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1586 tmp |= DPIO_DCLKP_EN;
1587 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1588
1589 /*
1590 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1591 */
1592 udelay(1);
1593
1594 /* Enable PLL */
1595 I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll);
1596
1597 /* Check PLL is locked */
1598 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1599 DRM_ERROR("PLL %d failed to lock\n", pipe);
1600
1601 /* not sure when this should be written */
1602 I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
1603 POSTING_READ(DPLL_MD(pipe));
1604
1605 mutex_unlock(&dev_priv->dpio_lock);
1606 }
1607
1608 static void i9xx_enable_pll(struct intel_crtc *crtc)
1609 {
1610 struct drm_device *dev = crtc->base.dev;
1611 struct drm_i915_private *dev_priv = dev->dev_private;
1612 int reg = DPLL(crtc->pipe);
1613 u32 dpll = crtc->config.dpll_hw_state.dpll;
1614
1615 assert_pipe_disabled(dev_priv, crtc->pipe);
1616
1617 /* No really, not for ILK+ */
1618 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1619
1620 /* PLL is protected by panel, make sure we can write it */
1621 if (IS_MOBILE(dev) && !IS_I830(dev))
1622 assert_panel_unlocked(dev_priv, crtc->pipe);
1623
1624 I915_WRITE(reg, dpll);
1625
1626 /* Wait for the clocks to stabilize. */
1627 POSTING_READ(reg);
1628 udelay(150);
1629
1630 if (INTEL_INFO(dev)->gen >= 4) {
1631 I915_WRITE(DPLL_MD(crtc->pipe),
1632 crtc->config.dpll_hw_state.dpll_md);
1633 } else {
1634 /* The pixel multiplier can only be updated once the
1635 * DPLL is enabled and the clocks are stable.
1636 *
1637 * So write it again.
1638 */
1639 I915_WRITE(reg, dpll);
1640 }
1641
1642 /* We do this three times for luck */
1643 I915_WRITE(reg, dpll);
1644 POSTING_READ(reg);
1645 udelay(150); /* wait for warmup */
1646 I915_WRITE(reg, dpll);
1647 POSTING_READ(reg);
1648 udelay(150); /* wait for warmup */
1649 I915_WRITE(reg, dpll);
1650 POSTING_READ(reg);
1651 udelay(150); /* wait for warmup */
1652 }
1653
1654 /**
1655 * i9xx_disable_pll - disable a PLL
1656 * @dev_priv: i915 private structure
1657 * @pipe: pipe PLL to disable
1658 *
1659 * Disable the PLL for @pipe, making sure the pipe is off first.
1660 *
1661 * Note! This is for pre-ILK only.
1662 */
1663 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1664 {
1665 /* Don't disable pipe A or pipe A PLLs if needed */
1666 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1667 return;
1668
1669 /* Make sure the pipe isn't still relying on us */
1670 assert_pipe_disabled(dev_priv, pipe);
1671
1672 I915_WRITE(DPLL(pipe), 0);
1673 POSTING_READ(DPLL(pipe));
1674 }
1675
1676 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1677 {
1678 u32 val = 0;
1679
1680 /* Make sure the pipe isn't still relying on us */
1681 assert_pipe_disabled(dev_priv, pipe);
1682
1683 /*
1684 * Leave integrated clock source and reference clock enabled for pipe B.
1685 * The latter is needed for VGA hotplug / manual detection.
1686 */
1687 if (pipe == PIPE_B)
1688 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1689 I915_WRITE(DPLL(pipe), val);
1690 POSTING_READ(DPLL(pipe));
1691
1692 }
1693
1694 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1695 {
1696 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1697 u32 val;
1698
1699 /* Make sure the pipe isn't still relying on us */
1700 assert_pipe_disabled(dev_priv, pipe);
1701
1702 /* Set PLL en = 0 */
1703 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1704 if (pipe != PIPE_A)
1705 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1706 I915_WRITE(DPLL(pipe), val);
1707 POSTING_READ(DPLL(pipe));
1708
1709 mutex_lock(&dev_priv->dpio_lock);
1710
1711 /* Disable 10bit clock to display controller */
1712 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1713 val &= ~DPIO_DCLKP_EN;
1714 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1715
1716 /* disable left/right clock distribution */
1717 if (pipe != PIPE_B) {
1718 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1719 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1720 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1721 } else {
1722 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1723 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1724 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1725 }
1726
1727 mutex_unlock(&dev_priv->dpio_lock);
1728 }
1729
1730 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1731 struct intel_digital_port *dport)
1732 {
1733 u32 port_mask;
1734 int dpll_reg;
1735
1736 switch (dport->port) {
1737 case PORT_B:
1738 port_mask = DPLL_PORTB_READY_MASK;
1739 dpll_reg = DPLL(0);
1740 break;
1741 case PORT_C:
1742 port_mask = DPLL_PORTC_READY_MASK;
1743 dpll_reg = DPLL(0);
1744 break;
1745 case PORT_D:
1746 port_mask = DPLL_PORTD_READY_MASK;
1747 dpll_reg = DPIO_PHY_STATUS;
1748 break;
1749 default:
1750 BUG();
1751 }
1752
1753 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1754 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1755 port_name(dport->port), I915_READ(dpll_reg));
1756 }
1757
1758 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1759 {
1760 struct drm_device *dev = crtc->base.dev;
1761 struct drm_i915_private *dev_priv = dev->dev_private;
1762 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1763
1764 if (WARN_ON(pll == NULL))
1765 return;
1766
1767 WARN_ON(!pll->refcount);
1768 if (pll->active == 0) {
1769 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1770 WARN_ON(pll->on);
1771 assert_shared_dpll_disabled(dev_priv, pll);
1772
1773 pll->mode_set(dev_priv, pll);
1774 }
1775 }
1776
1777 /**
1778 * intel_enable_shared_dpll - enable PCH PLL
1779 * @dev_priv: i915 private structure
1780 * @pipe: pipe PLL to enable
1781 *
1782 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1783 * drives the transcoder clock.
1784 */
1785 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1786 {
1787 struct drm_device *dev = crtc->base.dev;
1788 struct drm_i915_private *dev_priv = dev->dev_private;
1789 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1790
1791 if (WARN_ON(pll == NULL))
1792 return;
1793
1794 if (WARN_ON(pll->refcount == 0))
1795 return;
1796
1797 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1798 pll->name, pll->active, pll->on,
1799 crtc->base.base.id);
1800
1801 if (pll->active++) {
1802 WARN_ON(!pll->on);
1803 assert_shared_dpll_enabled(dev_priv, pll);
1804 return;
1805 }
1806 WARN_ON(pll->on);
1807
1808 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1809
1810 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1811 pll->enable(dev_priv, pll);
1812 pll->on = true;
1813 }
1814
1815 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1816 {
1817 struct drm_device *dev = crtc->base.dev;
1818 struct drm_i915_private *dev_priv = dev->dev_private;
1819 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1820
1821 /* PCH only available on ILK+ */
1822 BUG_ON(INTEL_INFO(dev)->gen < 5);
1823 if (WARN_ON(pll == NULL))
1824 return;
1825
1826 if (WARN_ON(pll->refcount == 0))
1827 return;
1828
1829 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1830 pll->name, pll->active, pll->on,
1831 crtc->base.base.id);
1832
1833 if (WARN_ON(pll->active == 0)) {
1834 assert_shared_dpll_disabled(dev_priv, pll);
1835 return;
1836 }
1837
1838 assert_shared_dpll_enabled(dev_priv, pll);
1839 WARN_ON(!pll->on);
1840 if (--pll->active)
1841 return;
1842
1843 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1844 pll->disable(dev_priv, pll);
1845 pll->on = false;
1846
1847 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1848 }
1849
1850 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1851 enum pipe pipe)
1852 {
1853 struct drm_device *dev = dev_priv->dev;
1854 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1855 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1856 uint32_t reg, val, pipeconf_val;
1857
1858 /* PCH only available on ILK+ */
1859 BUG_ON(INTEL_INFO(dev)->gen < 5);
1860
1861 /* Make sure PCH DPLL is enabled */
1862 assert_shared_dpll_enabled(dev_priv,
1863 intel_crtc_to_shared_dpll(intel_crtc));
1864
1865 /* FDI must be feeding us bits for PCH ports */
1866 assert_fdi_tx_enabled(dev_priv, pipe);
1867 assert_fdi_rx_enabled(dev_priv, pipe);
1868
1869 if (HAS_PCH_CPT(dev)) {
1870 /* Workaround: Set the timing override bit before enabling the
1871 * pch transcoder. */
1872 reg = TRANS_CHICKEN2(pipe);
1873 val = I915_READ(reg);
1874 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1875 I915_WRITE(reg, val);
1876 }
1877
1878 reg = PCH_TRANSCONF(pipe);
1879 val = I915_READ(reg);
1880 pipeconf_val = I915_READ(PIPECONF(pipe));
1881
1882 if (HAS_PCH_IBX(dev_priv->dev)) {
1883 /*
1884 * make the BPC in transcoder be consistent with
1885 * that in pipeconf reg.
1886 */
1887 val &= ~PIPECONF_BPC_MASK;
1888 val |= pipeconf_val & PIPECONF_BPC_MASK;
1889 }
1890
1891 val &= ~TRANS_INTERLACE_MASK;
1892 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1893 if (HAS_PCH_IBX(dev_priv->dev) &&
1894 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1895 val |= TRANS_LEGACY_INTERLACED_ILK;
1896 else
1897 val |= TRANS_INTERLACED;
1898 else
1899 val |= TRANS_PROGRESSIVE;
1900
1901 I915_WRITE(reg, val | TRANS_ENABLE);
1902 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1903 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1904 }
1905
1906 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1907 enum transcoder cpu_transcoder)
1908 {
1909 u32 val, pipeconf_val;
1910
1911 /* PCH only available on ILK+ */
1912 BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
1913
1914 /* FDI must be feeding us bits for PCH ports */
1915 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1916 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1917
1918 /* Workaround: set timing override bit. */
1919 val = I915_READ(_TRANSA_CHICKEN2);
1920 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1921 I915_WRITE(_TRANSA_CHICKEN2, val);
1922
1923 val = TRANS_ENABLE;
1924 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1925
1926 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1927 PIPECONF_INTERLACED_ILK)
1928 val |= TRANS_INTERLACED;
1929 else
1930 val |= TRANS_PROGRESSIVE;
1931
1932 I915_WRITE(LPT_TRANSCONF, val);
1933 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1934 DRM_ERROR("Failed to enable PCH transcoder\n");
1935 }
1936
1937 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1938 enum pipe pipe)
1939 {
1940 struct drm_device *dev = dev_priv->dev;
1941 uint32_t reg, val;
1942
1943 /* FDI relies on the transcoder */
1944 assert_fdi_tx_disabled(dev_priv, pipe);
1945 assert_fdi_rx_disabled(dev_priv, pipe);
1946
1947 /* Ports must be off as well */
1948 assert_pch_ports_disabled(dev_priv, pipe);
1949
1950 reg = PCH_TRANSCONF(pipe);
1951 val = I915_READ(reg);
1952 val &= ~TRANS_ENABLE;
1953 I915_WRITE(reg, val);
1954 /* wait for PCH transcoder off, transcoder state */
1955 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1956 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1957
1958 if (!HAS_PCH_IBX(dev)) {
1959 /* Workaround: Clear the timing override chicken bit again. */
1960 reg = TRANS_CHICKEN2(pipe);
1961 val = I915_READ(reg);
1962 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1963 I915_WRITE(reg, val);
1964 }
1965 }
1966
1967 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1968 {
1969 u32 val;
1970
1971 val = I915_READ(LPT_TRANSCONF);
1972 val &= ~TRANS_ENABLE;
1973 I915_WRITE(LPT_TRANSCONF, val);
1974 /* wait for PCH transcoder off, transcoder state */
1975 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1976 DRM_ERROR("Failed to disable PCH transcoder\n");
1977
1978 /* Workaround: clear timing override bit. */
1979 val = I915_READ(_TRANSA_CHICKEN2);
1980 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1981 I915_WRITE(_TRANSA_CHICKEN2, val);
1982 }
1983
1984 /**
1985 * intel_enable_pipe - enable a pipe, asserting requirements
1986 * @crtc: crtc responsible for the pipe
1987 *
1988 * Enable @crtc's pipe, making sure that various hardware specific requirements
1989 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1990 */
1991 static void intel_enable_pipe(struct intel_crtc *crtc)
1992 {
1993 struct drm_device *dev = crtc->base.dev;
1994 struct drm_i915_private *dev_priv = dev->dev_private;
1995 enum pipe pipe = crtc->pipe;
1996 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1997 pipe);
1998 enum pipe pch_transcoder;
1999 int reg;
2000 u32 val;
2001
2002 assert_planes_disabled(dev_priv, pipe);
2003 assert_cursor_disabled(dev_priv, pipe);
2004 assert_sprites_disabled(dev_priv, pipe);
2005
2006 if (HAS_PCH_LPT(dev_priv->dev))
2007 pch_transcoder = TRANSCODER_A;
2008 else
2009 pch_transcoder = pipe;
2010
2011 /*
2012 * A pipe without a PLL won't actually be able to drive bits from
2013 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2014 * need the check.
2015 */
2016 if (!HAS_PCH_SPLIT(dev_priv->dev))
2017 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
2018 assert_dsi_pll_enabled(dev_priv);
2019 else
2020 assert_pll_enabled(dev_priv, pipe);
2021 else {
2022 if (crtc->config.has_pch_encoder) {
2023 /* if driving the PCH, we need FDI enabled */
2024 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2025 assert_fdi_tx_pll_enabled(dev_priv,
2026 (enum pipe) cpu_transcoder);
2027 }
2028 /* FIXME: assert CPU port conditions for SNB+ */
2029 }
2030
2031 reg = PIPECONF(cpu_transcoder);
2032 val = I915_READ(reg);
2033 if (val & PIPECONF_ENABLE) {
2034 WARN_ON(!(pipe == PIPE_A &&
2035 dev_priv->quirks & QUIRK_PIPEA_FORCE));
2036 return;
2037 }
2038
2039 I915_WRITE(reg, val | PIPECONF_ENABLE);
2040 POSTING_READ(reg);
2041 }
2042
2043 /**
2044 * intel_disable_pipe - disable a pipe, asserting requirements
2045 * @crtc: crtc whose pipes is to be disabled
2046 *
2047 * Disable the pipe of @crtc, making sure that various hardware
2048 * specific requirements are met, if applicable, e.g. plane
2049 * disabled, panel fitter off, etc.
2050 *
2051 * Will wait until the pipe has shut down before returning.
2052 */
2053 static void intel_disable_pipe(struct intel_crtc *crtc)
2054 {
2055 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2056 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2057 enum pipe pipe = crtc->pipe;
2058 int reg;
2059 u32 val;
2060
2061 /*
2062 * Make sure planes won't keep trying to pump pixels to us,
2063 * or we might hang the display.
2064 */
2065 assert_planes_disabled(dev_priv, pipe);
2066 assert_cursor_disabled(dev_priv, pipe);
2067 assert_sprites_disabled(dev_priv, pipe);
2068
2069 /* Don't disable pipe A or pipe A PLLs if needed */
2070 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2071 return;
2072
2073 reg = PIPECONF(cpu_transcoder);
2074 val = I915_READ(reg);
2075 if ((val & PIPECONF_ENABLE) == 0)
2076 return;
2077
2078 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
2079 intel_wait_for_pipe_off(crtc);
2080 }
2081
2082 /*
2083 * Plane regs are double buffered, going from enabled->disabled needs a
2084 * trigger in order to latch. The display address reg provides this.
2085 */
2086 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2087 enum plane plane)
2088 {
2089 struct drm_device *dev = dev_priv->dev;
2090 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2091
2092 I915_WRITE(reg, I915_READ(reg));
2093 POSTING_READ(reg);
2094 }
2095
2096 /**
2097 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2098 * @plane: plane to be enabled
2099 * @crtc: crtc for the plane
2100 *
2101 * Enable @plane on @crtc, making sure that the pipe is running first.
2102 */
2103 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2104 struct drm_crtc *crtc)
2105 {
2106 struct drm_device *dev = plane->dev;
2107 struct drm_i915_private *dev_priv = dev->dev_private;
2108 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2109
2110 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2111 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2112
2113 if (intel_crtc->primary_enabled)
2114 return;
2115
2116 intel_crtc->primary_enabled = true;
2117
2118 dev_priv->display.update_primary_plane(crtc, plane->fb,
2119 crtc->x, crtc->y);
2120
2121 /*
2122 * BDW signals flip done immediately if the plane
2123 * is disabled, even if the plane enable is already
2124 * armed to occur at the next vblank :(
2125 */
2126 if (IS_BROADWELL(dev))
2127 intel_wait_for_vblank(dev, intel_crtc->pipe);
2128 }
2129
2130 /**
2131 * intel_disable_primary_hw_plane - disable the primary hardware plane
2132 * @plane: plane to be disabled
2133 * @crtc: crtc for the plane
2134 *
2135 * Disable @plane on @crtc, making sure that the pipe is running first.
2136 */
2137 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2138 struct drm_crtc *crtc)
2139 {
2140 struct drm_device *dev = plane->dev;
2141 struct drm_i915_private *dev_priv = dev->dev_private;
2142 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2143
2144 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2145
2146 if (!intel_crtc->primary_enabled)
2147 return;
2148
2149 intel_crtc->primary_enabled = false;
2150
2151 dev_priv->display.update_primary_plane(crtc, plane->fb,
2152 crtc->x, crtc->y);
2153 }
2154
2155 static bool need_vtd_wa(struct drm_device *dev)
2156 {
2157 #ifdef CONFIG_INTEL_IOMMU
2158 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2159 return true;
2160 #endif
2161 return false;
2162 }
2163
2164 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2165 {
2166 int tile_height;
2167
2168 tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2169 return ALIGN(height, tile_height);
2170 }
2171
2172 int
2173 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2174 struct drm_i915_gem_object *obj,
2175 struct intel_engine_cs *pipelined)
2176 {
2177 struct drm_i915_private *dev_priv = dev->dev_private;
2178 u32 alignment;
2179 int ret;
2180
2181 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2182
2183 switch (obj->tiling_mode) {
2184 case I915_TILING_NONE:
2185 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2186 alignment = 128 * 1024;
2187 else if (INTEL_INFO(dev)->gen >= 4)
2188 alignment = 4 * 1024;
2189 else
2190 alignment = 64 * 1024;
2191 break;
2192 case I915_TILING_X:
2193 /* pin() will align the object as required by fence */
2194 alignment = 0;
2195 break;
2196 case I915_TILING_Y:
2197 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2198 return -EINVAL;
2199 default:
2200 BUG();
2201 }
2202
2203 /* Note that the w/a also requires 64 PTE of padding following the
2204 * bo. We currently fill all unused PTE with the shadow page and so
2205 * we should always have valid PTE following the scanout preventing
2206 * the VT-d warning.
2207 */
2208 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2209 alignment = 256 * 1024;
2210
2211 dev_priv->mm.interruptible = false;
2212 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2213 if (ret)
2214 goto err_interruptible;
2215
2216 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2217 * fence, whereas 965+ only requires a fence if using
2218 * framebuffer compression. For simplicity, we always install
2219 * a fence as the cost is not that onerous.
2220 */
2221 ret = i915_gem_object_get_fence(obj);
2222 if (ret)
2223 goto err_unpin;
2224
2225 i915_gem_object_pin_fence(obj);
2226
2227 dev_priv->mm.interruptible = true;
2228 return 0;
2229
2230 err_unpin:
2231 i915_gem_object_unpin_from_display_plane(obj);
2232 err_interruptible:
2233 dev_priv->mm.interruptible = true;
2234 return ret;
2235 }
2236
2237 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2238 {
2239 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2240
2241 i915_gem_object_unpin_fence(obj);
2242 i915_gem_object_unpin_from_display_plane(obj);
2243 }
2244
2245 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2246 * is assumed to be a power-of-two. */
2247 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2248 unsigned int tiling_mode,
2249 unsigned int cpp,
2250 unsigned int pitch)
2251 {
2252 if (tiling_mode != I915_TILING_NONE) {
2253 unsigned int tile_rows, tiles;
2254
2255 tile_rows = *y / 8;
2256 *y %= 8;
2257
2258 tiles = *x / (512/cpp);
2259 *x %= 512/cpp;
2260
2261 return tile_rows * pitch * 8 + tiles * 4096;
2262 } else {
2263 unsigned int offset;
2264
2265 offset = *y * pitch + *x * cpp;
2266 *y = 0;
2267 *x = (offset & 4095) / cpp;
2268 return offset & -4096;
2269 }
2270 }
2271
2272 int intel_format_to_fourcc(int format)
2273 {
2274 switch (format) {
2275 case DISPPLANE_8BPP:
2276 return DRM_FORMAT_C8;
2277 case DISPPLANE_BGRX555:
2278 return DRM_FORMAT_XRGB1555;
2279 case DISPPLANE_BGRX565:
2280 return DRM_FORMAT_RGB565;
2281 default:
2282 case DISPPLANE_BGRX888:
2283 return DRM_FORMAT_XRGB8888;
2284 case DISPPLANE_RGBX888:
2285 return DRM_FORMAT_XBGR8888;
2286 case DISPPLANE_BGRX101010:
2287 return DRM_FORMAT_XRGB2101010;
2288 case DISPPLANE_RGBX101010:
2289 return DRM_FORMAT_XBGR2101010;
2290 }
2291 }
2292
2293 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2294 struct intel_plane_config *plane_config)
2295 {
2296 struct drm_device *dev = crtc->base.dev;
2297 struct drm_i915_gem_object *obj = NULL;
2298 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2299 u32 base = plane_config->base;
2300
2301 if (plane_config->size == 0)
2302 return false;
2303
2304 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2305 plane_config->size);
2306 if (!obj)
2307 return false;
2308
2309 if (plane_config->tiled) {
2310 obj->tiling_mode = I915_TILING_X;
2311 obj->stride = crtc->base.primary->fb->pitches[0];
2312 }
2313
2314 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2315 mode_cmd.width = crtc->base.primary->fb->width;
2316 mode_cmd.height = crtc->base.primary->fb->height;
2317 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2318
2319 mutex_lock(&dev->struct_mutex);
2320
2321 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2322 &mode_cmd, obj)) {
2323 DRM_DEBUG_KMS("intel fb init failed\n");
2324 goto out_unref_obj;
2325 }
2326
2327 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2328 mutex_unlock(&dev->struct_mutex);
2329
2330 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2331 return true;
2332
2333 out_unref_obj:
2334 drm_gem_object_unreference(&obj->base);
2335 mutex_unlock(&dev->struct_mutex);
2336 return false;
2337 }
2338
2339 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2340 struct intel_plane_config *plane_config)
2341 {
2342 struct drm_device *dev = intel_crtc->base.dev;
2343 struct drm_crtc *c;
2344 struct intel_crtc *i;
2345 struct drm_i915_gem_object *obj;
2346
2347 if (!intel_crtc->base.primary->fb)
2348 return;
2349
2350 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2351 return;
2352
2353 kfree(intel_crtc->base.primary->fb);
2354 intel_crtc->base.primary->fb = NULL;
2355
2356 /*
2357 * Failed to alloc the obj, check to see if we should share
2358 * an fb with another CRTC instead
2359 */
2360 for_each_crtc(dev, c) {
2361 i = to_intel_crtc(c);
2362
2363 if (c == &intel_crtc->base)
2364 continue;
2365
2366 if (!i->active)
2367 continue;
2368
2369 obj = intel_fb_obj(c->primary->fb);
2370 if (obj == NULL)
2371 continue;
2372
2373 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2374 drm_framebuffer_reference(c->primary->fb);
2375 intel_crtc->base.primary->fb = c->primary->fb;
2376 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2377 break;
2378 }
2379 }
2380 }
2381
2382 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2383 struct drm_framebuffer *fb,
2384 int x, int y)
2385 {
2386 struct drm_device *dev = crtc->dev;
2387 struct drm_i915_private *dev_priv = dev->dev_private;
2388 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2389 struct drm_i915_gem_object *obj;
2390 int plane = intel_crtc->plane;
2391 unsigned long linear_offset;
2392 u32 dspcntr;
2393 u32 reg = DSPCNTR(plane);
2394 int pixel_size;
2395
2396 if (!intel_crtc->primary_enabled) {
2397 I915_WRITE(reg, 0);
2398 if (INTEL_INFO(dev)->gen >= 4)
2399 I915_WRITE(DSPSURF(plane), 0);
2400 else
2401 I915_WRITE(DSPADDR(plane), 0);
2402 POSTING_READ(reg);
2403 return;
2404 }
2405
2406 obj = intel_fb_obj(fb);
2407 if (WARN_ON(obj == NULL))
2408 return;
2409
2410 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2411
2412 dspcntr = DISPPLANE_GAMMA_ENABLE;
2413
2414 dspcntr |= DISPLAY_PLANE_ENABLE;
2415
2416 if (INTEL_INFO(dev)->gen < 4) {
2417 if (intel_crtc->pipe == PIPE_B)
2418 dspcntr |= DISPPLANE_SEL_PIPE_B;
2419
2420 /* pipesrc and dspsize control the size that is scaled from,
2421 * which should always be the user's requested size.
2422 */
2423 I915_WRITE(DSPSIZE(plane),
2424 ((intel_crtc->config.pipe_src_h - 1) << 16) |
2425 (intel_crtc->config.pipe_src_w - 1));
2426 I915_WRITE(DSPPOS(plane), 0);
2427 }
2428
2429 switch (fb->pixel_format) {
2430 case DRM_FORMAT_C8:
2431 dspcntr |= DISPPLANE_8BPP;
2432 break;
2433 case DRM_FORMAT_XRGB1555:
2434 case DRM_FORMAT_ARGB1555:
2435 dspcntr |= DISPPLANE_BGRX555;
2436 break;
2437 case DRM_FORMAT_RGB565:
2438 dspcntr |= DISPPLANE_BGRX565;
2439 break;
2440 case DRM_FORMAT_XRGB8888:
2441 case DRM_FORMAT_ARGB8888:
2442 dspcntr |= DISPPLANE_BGRX888;
2443 break;
2444 case DRM_FORMAT_XBGR8888:
2445 case DRM_FORMAT_ABGR8888:
2446 dspcntr |= DISPPLANE_RGBX888;
2447 break;
2448 case DRM_FORMAT_XRGB2101010:
2449 case DRM_FORMAT_ARGB2101010:
2450 dspcntr |= DISPPLANE_BGRX101010;
2451 break;
2452 case DRM_FORMAT_XBGR2101010:
2453 case DRM_FORMAT_ABGR2101010:
2454 dspcntr |= DISPPLANE_RGBX101010;
2455 break;
2456 default:
2457 BUG();
2458 }
2459
2460 if (INTEL_INFO(dev)->gen >= 4 &&
2461 obj->tiling_mode != I915_TILING_NONE)
2462 dspcntr |= DISPPLANE_TILED;
2463
2464 if (IS_G4X(dev))
2465 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2466
2467 linear_offset = y * fb->pitches[0] + x * pixel_size;
2468
2469 if (INTEL_INFO(dev)->gen >= 4) {
2470 intel_crtc->dspaddr_offset =
2471 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2472 pixel_size,
2473 fb->pitches[0]);
2474 linear_offset -= intel_crtc->dspaddr_offset;
2475 } else {
2476 intel_crtc->dspaddr_offset = linear_offset;
2477 }
2478
2479 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2480 dspcntr |= DISPPLANE_ROTATE_180;
2481
2482 x += (intel_crtc->config.pipe_src_w - 1);
2483 y += (intel_crtc->config.pipe_src_h - 1);
2484
2485 /* Finding the last pixel of the last line of the display
2486 data and adding to linear_offset*/
2487 linear_offset +=
2488 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2489 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2490 }
2491
2492 I915_WRITE(reg, dspcntr);
2493
2494 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2495 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2496 fb->pitches[0]);
2497 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2498 if (INTEL_INFO(dev)->gen >= 4) {
2499 I915_WRITE(DSPSURF(plane),
2500 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2501 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2502 I915_WRITE(DSPLINOFF(plane), linear_offset);
2503 } else
2504 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2505 POSTING_READ(reg);
2506 }
2507
2508 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2509 struct drm_framebuffer *fb,
2510 int x, int y)
2511 {
2512 struct drm_device *dev = crtc->dev;
2513 struct drm_i915_private *dev_priv = dev->dev_private;
2514 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2515 struct drm_i915_gem_object *obj;
2516 int plane = intel_crtc->plane;
2517 unsigned long linear_offset;
2518 u32 dspcntr;
2519 u32 reg = DSPCNTR(plane);
2520 int pixel_size;
2521
2522 if (!intel_crtc->primary_enabled) {
2523 I915_WRITE(reg, 0);
2524 I915_WRITE(DSPSURF(plane), 0);
2525 POSTING_READ(reg);
2526 return;
2527 }
2528
2529 obj = intel_fb_obj(fb);
2530 if (WARN_ON(obj == NULL))
2531 return;
2532
2533 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2534
2535 dspcntr = DISPPLANE_GAMMA_ENABLE;
2536
2537 dspcntr |= DISPLAY_PLANE_ENABLE;
2538
2539 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2540 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2541
2542 switch (fb->pixel_format) {
2543 case DRM_FORMAT_C8:
2544 dspcntr |= DISPPLANE_8BPP;
2545 break;
2546 case DRM_FORMAT_RGB565:
2547 dspcntr |= DISPPLANE_BGRX565;
2548 break;
2549 case DRM_FORMAT_XRGB8888:
2550 case DRM_FORMAT_ARGB8888:
2551 dspcntr |= DISPPLANE_BGRX888;
2552 break;
2553 case DRM_FORMAT_XBGR8888:
2554 case DRM_FORMAT_ABGR8888:
2555 dspcntr |= DISPPLANE_RGBX888;
2556 break;
2557 case DRM_FORMAT_XRGB2101010:
2558 case DRM_FORMAT_ARGB2101010:
2559 dspcntr |= DISPPLANE_BGRX101010;
2560 break;
2561 case DRM_FORMAT_XBGR2101010:
2562 case DRM_FORMAT_ABGR2101010:
2563 dspcntr |= DISPPLANE_RGBX101010;
2564 break;
2565 default:
2566 BUG();
2567 }
2568
2569 if (obj->tiling_mode != I915_TILING_NONE)
2570 dspcntr |= DISPPLANE_TILED;
2571
2572 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2573 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2574
2575 linear_offset = y * fb->pitches[0] + x * pixel_size;
2576 intel_crtc->dspaddr_offset =
2577 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2578 pixel_size,
2579 fb->pitches[0]);
2580 linear_offset -= intel_crtc->dspaddr_offset;
2581 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2582 dspcntr |= DISPPLANE_ROTATE_180;
2583
2584 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2585 x += (intel_crtc->config.pipe_src_w - 1);
2586 y += (intel_crtc->config.pipe_src_h - 1);
2587
2588 /* Finding the last pixel of the last line of the display
2589 data and adding to linear_offset*/
2590 linear_offset +=
2591 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2592 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2593 }
2594 }
2595
2596 I915_WRITE(reg, dspcntr);
2597
2598 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2599 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2600 fb->pitches[0]);
2601 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2602 I915_WRITE(DSPSURF(plane),
2603 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2604 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2605 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2606 } else {
2607 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2608 I915_WRITE(DSPLINOFF(plane), linear_offset);
2609 }
2610 POSTING_READ(reg);
2611 }
2612
2613 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2614 static int
2615 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2616 int x, int y, enum mode_set_atomic state)
2617 {
2618 struct drm_device *dev = crtc->dev;
2619 struct drm_i915_private *dev_priv = dev->dev_private;
2620
2621 if (dev_priv->display.disable_fbc)
2622 dev_priv->display.disable_fbc(dev);
2623 intel_increase_pllclock(dev, to_intel_crtc(crtc)->pipe);
2624
2625 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2626
2627 return 0;
2628 }
2629
2630 void intel_display_handle_reset(struct drm_device *dev)
2631 {
2632 struct drm_i915_private *dev_priv = dev->dev_private;
2633 struct drm_crtc *crtc;
2634
2635 /*
2636 * Flips in the rings have been nuked by the reset,
2637 * so complete all pending flips so that user space
2638 * will get its events and not get stuck.
2639 *
2640 * Also update the base address of all primary
2641 * planes to the the last fb to make sure we're
2642 * showing the correct fb after a reset.
2643 *
2644 * Need to make two loops over the crtcs so that we
2645 * don't try to grab a crtc mutex before the
2646 * pending_flip_queue really got woken up.
2647 */
2648
2649 for_each_crtc(dev, crtc) {
2650 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2651 enum plane plane = intel_crtc->plane;
2652
2653 intel_prepare_page_flip(dev, plane);
2654 intel_finish_page_flip_plane(dev, plane);
2655 }
2656
2657 for_each_crtc(dev, crtc) {
2658 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2659
2660 drm_modeset_lock(&crtc->mutex, NULL);
2661 /*
2662 * FIXME: Once we have proper support for primary planes (and
2663 * disabling them without disabling the entire crtc) allow again
2664 * a NULL crtc->primary->fb.
2665 */
2666 if (intel_crtc->active && crtc->primary->fb)
2667 dev_priv->display.update_primary_plane(crtc,
2668 crtc->primary->fb,
2669 crtc->x,
2670 crtc->y);
2671 drm_modeset_unlock(&crtc->mutex);
2672 }
2673 }
2674
2675 static int
2676 intel_finish_fb(struct drm_framebuffer *old_fb)
2677 {
2678 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2679 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2680 bool was_interruptible = dev_priv->mm.interruptible;
2681 int ret;
2682
2683 /* Big Hammer, we also need to ensure that any pending
2684 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2685 * current scanout is retired before unpinning the old
2686 * framebuffer.
2687 *
2688 * This should only fail upon a hung GPU, in which case we
2689 * can safely continue.
2690 */
2691 dev_priv->mm.interruptible = false;
2692 ret = i915_gem_object_finish_gpu(obj);
2693 dev_priv->mm.interruptible = was_interruptible;
2694
2695 return ret;
2696 }
2697
2698 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2699 {
2700 struct drm_device *dev = crtc->dev;
2701 struct drm_i915_private *dev_priv = dev->dev_private;
2702 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2703 unsigned long flags;
2704 bool pending;
2705
2706 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2707 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2708 return false;
2709
2710 spin_lock_irqsave(&dev->event_lock, flags);
2711 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2712 spin_unlock_irqrestore(&dev->event_lock, flags);
2713
2714 return pending;
2715 }
2716
2717 static int
2718 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2719 struct drm_framebuffer *fb)
2720 {
2721 struct drm_device *dev = crtc->dev;
2722 struct drm_i915_private *dev_priv = dev->dev_private;
2723 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2724 enum pipe pipe = intel_crtc->pipe;
2725 struct drm_framebuffer *old_fb = crtc->primary->fb;
2726 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2727 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
2728 int ret;
2729
2730 if (intel_crtc_has_pending_flip(crtc)) {
2731 DRM_ERROR("pipe is still busy with an old pageflip\n");
2732 return -EBUSY;
2733 }
2734
2735 /* no fb bound */
2736 if (!fb) {
2737 DRM_ERROR("No FB bound\n");
2738 return 0;
2739 }
2740
2741 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2742 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2743 plane_name(intel_crtc->plane),
2744 INTEL_INFO(dev)->num_pipes);
2745 return -EINVAL;
2746 }
2747
2748 mutex_lock(&dev->struct_mutex);
2749 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
2750 if (ret == 0)
2751 i915_gem_track_fb(old_obj, obj,
2752 INTEL_FRONTBUFFER_PRIMARY(pipe));
2753 mutex_unlock(&dev->struct_mutex);
2754 if (ret != 0) {
2755 DRM_ERROR("pin & fence failed\n");
2756 return ret;
2757 }
2758
2759 /*
2760 * Update pipe size and adjust fitter if needed: the reason for this is
2761 * that in compute_mode_changes we check the native mode (not the pfit
2762 * mode) to see if we can flip rather than do a full mode set. In the
2763 * fastboot case, we'll flip, but if we don't update the pipesrc and
2764 * pfit state, we'll end up with a big fb scanned out into the wrong
2765 * sized surface.
2766 *
2767 * To fix this properly, we need to hoist the checks up into
2768 * compute_mode_changes (or above), check the actual pfit state and
2769 * whether the platform allows pfit disable with pipe active, and only
2770 * then update the pipesrc and pfit state, even on the flip path.
2771 */
2772 if (i915.fastboot) {
2773 const struct drm_display_mode *adjusted_mode =
2774 &intel_crtc->config.adjusted_mode;
2775
2776 I915_WRITE(PIPESRC(intel_crtc->pipe),
2777 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2778 (adjusted_mode->crtc_vdisplay - 1));
2779 if (!intel_crtc->config.pch_pfit.enabled &&
2780 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2781 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2782 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2783 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2784 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2785 }
2786 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2787 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2788 }
2789
2790 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2791
2792 if (intel_crtc->active)
2793 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
2794
2795 crtc->primary->fb = fb;
2796 crtc->x = x;
2797 crtc->y = y;
2798
2799 if (old_fb) {
2800 if (intel_crtc->active && old_fb != fb)
2801 intel_wait_for_vblank(dev, intel_crtc->pipe);
2802 mutex_lock(&dev->struct_mutex);
2803 intel_unpin_fb_obj(old_obj);
2804 mutex_unlock(&dev->struct_mutex);
2805 }
2806
2807 mutex_lock(&dev->struct_mutex);
2808 intel_update_fbc(dev);
2809 mutex_unlock(&dev->struct_mutex);
2810
2811 return 0;
2812 }
2813
2814 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2815 {
2816 struct drm_device *dev = crtc->dev;
2817 struct drm_i915_private *dev_priv = dev->dev_private;
2818 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2819 int pipe = intel_crtc->pipe;
2820 u32 reg, temp;
2821
2822 /* enable normal train */
2823 reg = FDI_TX_CTL(pipe);
2824 temp = I915_READ(reg);
2825 if (IS_IVYBRIDGE(dev)) {
2826 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2827 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2828 } else {
2829 temp &= ~FDI_LINK_TRAIN_NONE;
2830 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2831 }
2832 I915_WRITE(reg, temp);
2833
2834 reg = FDI_RX_CTL(pipe);
2835 temp = I915_READ(reg);
2836 if (HAS_PCH_CPT(dev)) {
2837 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2838 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2839 } else {
2840 temp &= ~FDI_LINK_TRAIN_NONE;
2841 temp |= FDI_LINK_TRAIN_NONE;
2842 }
2843 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2844
2845 /* wait one idle pattern time */
2846 POSTING_READ(reg);
2847 udelay(1000);
2848
2849 /* IVB wants error correction enabled */
2850 if (IS_IVYBRIDGE(dev))
2851 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2852 FDI_FE_ERRC_ENABLE);
2853 }
2854
2855 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2856 {
2857 return crtc->base.enabled && crtc->active &&
2858 crtc->config.has_pch_encoder;
2859 }
2860
2861 static void ivb_modeset_global_resources(struct drm_device *dev)
2862 {
2863 struct drm_i915_private *dev_priv = dev->dev_private;
2864 struct intel_crtc *pipe_B_crtc =
2865 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2866 struct intel_crtc *pipe_C_crtc =
2867 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2868 uint32_t temp;
2869
2870 /*
2871 * When everything is off disable fdi C so that we could enable fdi B
2872 * with all lanes. Note that we don't care about enabled pipes without
2873 * an enabled pch encoder.
2874 */
2875 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2876 !pipe_has_enabled_pch(pipe_C_crtc)) {
2877 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2878 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2879
2880 temp = I915_READ(SOUTH_CHICKEN1);
2881 temp &= ~FDI_BC_BIFURCATION_SELECT;
2882 DRM_DEBUG_KMS("disabling fdi C rx\n");
2883 I915_WRITE(SOUTH_CHICKEN1, temp);
2884 }
2885 }
2886
2887 /* The FDI link training functions for ILK/Ibexpeak. */
2888 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2889 {
2890 struct drm_device *dev = crtc->dev;
2891 struct drm_i915_private *dev_priv = dev->dev_private;
2892 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2893 int pipe = intel_crtc->pipe;
2894 u32 reg, temp, tries;
2895
2896 /* FDI needs bits from pipe first */
2897 assert_pipe_enabled(dev_priv, pipe);
2898
2899 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2900 for train result */
2901 reg = FDI_RX_IMR(pipe);
2902 temp = I915_READ(reg);
2903 temp &= ~FDI_RX_SYMBOL_LOCK;
2904 temp &= ~FDI_RX_BIT_LOCK;
2905 I915_WRITE(reg, temp);
2906 I915_READ(reg);
2907 udelay(150);
2908
2909 /* enable CPU FDI TX and PCH FDI RX */
2910 reg = FDI_TX_CTL(pipe);
2911 temp = I915_READ(reg);
2912 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2913 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2914 temp &= ~FDI_LINK_TRAIN_NONE;
2915 temp |= FDI_LINK_TRAIN_PATTERN_1;
2916 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2917
2918 reg = FDI_RX_CTL(pipe);
2919 temp = I915_READ(reg);
2920 temp &= ~FDI_LINK_TRAIN_NONE;
2921 temp |= FDI_LINK_TRAIN_PATTERN_1;
2922 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2923
2924 POSTING_READ(reg);
2925 udelay(150);
2926
2927 /* Ironlake workaround, enable clock pointer after FDI enable*/
2928 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2929 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2930 FDI_RX_PHASE_SYNC_POINTER_EN);
2931
2932 reg = FDI_RX_IIR(pipe);
2933 for (tries = 0; tries < 5; tries++) {
2934 temp = I915_READ(reg);
2935 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2936
2937 if ((temp & FDI_RX_BIT_LOCK)) {
2938 DRM_DEBUG_KMS("FDI train 1 done.\n");
2939 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2940 break;
2941 }
2942 }
2943 if (tries == 5)
2944 DRM_ERROR("FDI train 1 fail!\n");
2945
2946 /* Train 2 */
2947 reg = FDI_TX_CTL(pipe);
2948 temp = I915_READ(reg);
2949 temp &= ~FDI_LINK_TRAIN_NONE;
2950 temp |= FDI_LINK_TRAIN_PATTERN_2;
2951 I915_WRITE(reg, temp);
2952
2953 reg = FDI_RX_CTL(pipe);
2954 temp = I915_READ(reg);
2955 temp &= ~FDI_LINK_TRAIN_NONE;
2956 temp |= FDI_LINK_TRAIN_PATTERN_2;
2957 I915_WRITE(reg, temp);
2958
2959 POSTING_READ(reg);
2960 udelay(150);
2961
2962 reg = FDI_RX_IIR(pipe);
2963 for (tries = 0; tries < 5; tries++) {
2964 temp = I915_READ(reg);
2965 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2966
2967 if (temp & FDI_RX_SYMBOL_LOCK) {
2968 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2969 DRM_DEBUG_KMS("FDI train 2 done.\n");
2970 break;
2971 }
2972 }
2973 if (tries == 5)
2974 DRM_ERROR("FDI train 2 fail!\n");
2975
2976 DRM_DEBUG_KMS("FDI train done\n");
2977
2978 }
2979
2980 static const int snb_b_fdi_train_param[] = {
2981 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2982 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2983 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2984 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2985 };
2986
2987 /* The FDI link training functions for SNB/Cougarpoint. */
2988 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2989 {
2990 struct drm_device *dev = crtc->dev;
2991 struct drm_i915_private *dev_priv = dev->dev_private;
2992 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2993 int pipe = intel_crtc->pipe;
2994 u32 reg, temp, i, retry;
2995
2996 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2997 for train result */
2998 reg = FDI_RX_IMR(pipe);
2999 temp = I915_READ(reg);
3000 temp &= ~FDI_RX_SYMBOL_LOCK;
3001 temp &= ~FDI_RX_BIT_LOCK;
3002 I915_WRITE(reg, temp);
3003
3004 POSTING_READ(reg);
3005 udelay(150);
3006
3007 /* enable CPU FDI TX and PCH FDI RX */
3008 reg = FDI_TX_CTL(pipe);
3009 temp = I915_READ(reg);
3010 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3011 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3012 temp &= ~FDI_LINK_TRAIN_NONE;
3013 temp |= FDI_LINK_TRAIN_PATTERN_1;
3014 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3015 /* SNB-B */
3016 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3017 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3018
3019 I915_WRITE(FDI_RX_MISC(pipe),
3020 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3021
3022 reg = FDI_RX_CTL(pipe);
3023 temp = I915_READ(reg);
3024 if (HAS_PCH_CPT(dev)) {
3025 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3026 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3027 } else {
3028 temp &= ~FDI_LINK_TRAIN_NONE;
3029 temp |= FDI_LINK_TRAIN_PATTERN_1;
3030 }
3031 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3032
3033 POSTING_READ(reg);
3034 udelay(150);
3035
3036 for (i = 0; i < 4; i++) {
3037 reg = FDI_TX_CTL(pipe);
3038 temp = I915_READ(reg);
3039 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3040 temp |= snb_b_fdi_train_param[i];
3041 I915_WRITE(reg, temp);
3042
3043 POSTING_READ(reg);
3044 udelay(500);
3045
3046 for (retry = 0; retry < 5; retry++) {
3047 reg = FDI_RX_IIR(pipe);
3048 temp = I915_READ(reg);
3049 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3050 if (temp & FDI_RX_BIT_LOCK) {
3051 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3052 DRM_DEBUG_KMS("FDI train 1 done.\n");
3053 break;
3054 }
3055 udelay(50);
3056 }
3057 if (retry < 5)
3058 break;
3059 }
3060 if (i == 4)
3061 DRM_ERROR("FDI train 1 fail!\n");
3062
3063 /* Train 2 */
3064 reg = FDI_TX_CTL(pipe);
3065 temp = I915_READ(reg);
3066 temp &= ~FDI_LINK_TRAIN_NONE;
3067 temp |= FDI_LINK_TRAIN_PATTERN_2;
3068 if (IS_GEN6(dev)) {
3069 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3070 /* SNB-B */
3071 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3072 }
3073 I915_WRITE(reg, temp);
3074
3075 reg = FDI_RX_CTL(pipe);
3076 temp = I915_READ(reg);
3077 if (HAS_PCH_CPT(dev)) {
3078 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3079 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3080 } else {
3081 temp &= ~FDI_LINK_TRAIN_NONE;
3082 temp |= FDI_LINK_TRAIN_PATTERN_2;
3083 }
3084 I915_WRITE(reg, temp);
3085
3086 POSTING_READ(reg);
3087 udelay(150);
3088
3089 for (i = 0; i < 4; i++) {
3090 reg = FDI_TX_CTL(pipe);
3091 temp = I915_READ(reg);
3092 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3093 temp |= snb_b_fdi_train_param[i];
3094 I915_WRITE(reg, temp);
3095
3096 POSTING_READ(reg);
3097 udelay(500);
3098
3099 for (retry = 0; retry < 5; retry++) {
3100 reg = FDI_RX_IIR(pipe);
3101 temp = I915_READ(reg);
3102 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3103 if (temp & FDI_RX_SYMBOL_LOCK) {
3104 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3105 DRM_DEBUG_KMS("FDI train 2 done.\n");
3106 break;
3107 }
3108 udelay(50);
3109 }
3110 if (retry < 5)
3111 break;
3112 }
3113 if (i == 4)
3114 DRM_ERROR("FDI train 2 fail!\n");
3115
3116 DRM_DEBUG_KMS("FDI train done.\n");
3117 }
3118
3119 /* Manual link training for Ivy Bridge A0 parts */
3120 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3121 {
3122 struct drm_device *dev = crtc->dev;
3123 struct drm_i915_private *dev_priv = dev->dev_private;
3124 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3125 int pipe = intel_crtc->pipe;
3126 u32 reg, temp, i, j;
3127
3128 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3129 for train result */
3130 reg = FDI_RX_IMR(pipe);
3131 temp = I915_READ(reg);
3132 temp &= ~FDI_RX_SYMBOL_LOCK;
3133 temp &= ~FDI_RX_BIT_LOCK;
3134 I915_WRITE(reg, temp);
3135
3136 POSTING_READ(reg);
3137 udelay(150);
3138
3139 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3140 I915_READ(FDI_RX_IIR(pipe)));
3141
3142 /* Try each vswing and preemphasis setting twice before moving on */
3143 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3144 /* disable first in case we need to retry */
3145 reg = FDI_TX_CTL(pipe);
3146 temp = I915_READ(reg);
3147 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3148 temp &= ~FDI_TX_ENABLE;
3149 I915_WRITE(reg, temp);
3150
3151 reg = FDI_RX_CTL(pipe);
3152 temp = I915_READ(reg);
3153 temp &= ~FDI_LINK_TRAIN_AUTO;
3154 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3155 temp &= ~FDI_RX_ENABLE;
3156 I915_WRITE(reg, temp);
3157
3158 /* enable CPU FDI TX and PCH FDI RX */
3159 reg = FDI_TX_CTL(pipe);
3160 temp = I915_READ(reg);
3161 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3162 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3163 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3164 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3165 temp |= snb_b_fdi_train_param[j/2];
3166 temp |= FDI_COMPOSITE_SYNC;
3167 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3168
3169 I915_WRITE(FDI_RX_MISC(pipe),
3170 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3171
3172 reg = FDI_RX_CTL(pipe);
3173 temp = I915_READ(reg);
3174 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3175 temp |= FDI_COMPOSITE_SYNC;
3176 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3177
3178 POSTING_READ(reg);
3179 udelay(1); /* should be 0.5us */
3180
3181 for (i = 0; i < 4; i++) {
3182 reg = FDI_RX_IIR(pipe);
3183 temp = I915_READ(reg);
3184 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3185
3186 if (temp & FDI_RX_BIT_LOCK ||
3187 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3188 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3189 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3190 i);
3191 break;
3192 }
3193 udelay(1); /* should be 0.5us */
3194 }
3195 if (i == 4) {
3196 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3197 continue;
3198 }
3199
3200 /* Train 2 */
3201 reg = FDI_TX_CTL(pipe);
3202 temp = I915_READ(reg);
3203 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3204 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3205 I915_WRITE(reg, temp);
3206
3207 reg = FDI_RX_CTL(pipe);
3208 temp = I915_READ(reg);
3209 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3210 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3211 I915_WRITE(reg, temp);
3212
3213 POSTING_READ(reg);
3214 udelay(2); /* should be 1.5us */
3215
3216 for (i = 0; i < 4; i++) {
3217 reg = FDI_RX_IIR(pipe);
3218 temp = I915_READ(reg);
3219 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3220
3221 if (temp & FDI_RX_SYMBOL_LOCK ||
3222 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3223 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3224 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3225 i);
3226 goto train_done;
3227 }
3228 udelay(2); /* should be 1.5us */
3229 }
3230 if (i == 4)
3231 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3232 }
3233
3234 train_done:
3235 DRM_DEBUG_KMS("FDI train done.\n");
3236 }
3237
3238 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3239 {
3240 struct drm_device *dev = intel_crtc->base.dev;
3241 struct drm_i915_private *dev_priv = dev->dev_private;
3242 int pipe = intel_crtc->pipe;
3243 u32 reg, temp;
3244
3245
3246 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3247 reg = FDI_RX_CTL(pipe);
3248 temp = I915_READ(reg);
3249 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3250 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3251 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3252 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3253
3254 POSTING_READ(reg);
3255 udelay(200);
3256
3257 /* Switch from Rawclk to PCDclk */
3258 temp = I915_READ(reg);
3259 I915_WRITE(reg, temp | FDI_PCDCLK);
3260
3261 POSTING_READ(reg);
3262 udelay(200);
3263
3264 /* Enable CPU FDI TX PLL, always on for Ironlake */
3265 reg = FDI_TX_CTL(pipe);
3266 temp = I915_READ(reg);
3267 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3268 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3269
3270 POSTING_READ(reg);
3271 udelay(100);
3272 }
3273 }
3274
3275 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3276 {
3277 struct drm_device *dev = intel_crtc->base.dev;
3278 struct drm_i915_private *dev_priv = dev->dev_private;
3279 int pipe = intel_crtc->pipe;
3280 u32 reg, temp;
3281
3282 /* Switch from PCDclk to Rawclk */
3283 reg = FDI_RX_CTL(pipe);
3284 temp = I915_READ(reg);
3285 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3286
3287 /* Disable CPU FDI TX PLL */
3288 reg = FDI_TX_CTL(pipe);
3289 temp = I915_READ(reg);
3290 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3291
3292 POSTING_READ(reg);
3293 udelay(100);
3294
3295 reg = FDI_RX_CTL(pipe);
3296 temp = I915_READ(reg);
3297 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3298
3299 /* Wait for the clocks to turn off. */
3300 POSTING_READ(reg);
3301 udelay(100);
3302 }
3303
3304 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3305 {
3306 struct drm_device *dev = crtc->dev;
3307 struct drm_i915_private *dev_priv = dev->dev_private;
3308 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3309 int pipe = intel_crtc->pipe;
3310 u32 reg, temp;
3311
3312 /* disable CPU FDI tx and PCH FDI rx */
3313 reg = FDI_TX_CTL(pipe);
3314 temp = I915_READ(reg);
3315 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3316 POSTING_READ(reg);
3317
3318 reg = FDI_RX_CTL(pipe);
3319 temp = I915_READ(reg);
3320 temp &= ~(0x7 << 16);
3321 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3322 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3323
3324 POSTING_READ(reg);
3325 udelay(100);
3326
3327 /* Ironlake workaround, disable clock pointer after downing FDI */
3328 if (HAS_PCH_IBX(dev))
3329 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3330
3331 /* still set train pattern 1 */
3332 reg = FDI_TX_CTL(pipe);
3333 temp = I915_READ(reg);
3334 temp &= ~FDI_LINK_TRAIN_NONE;
3335 temp |= FDI_LINK_TRAIN_PATTERN_1;
3336 I915_WRITE(reg, temp);
3337
3338 reg = FDI_RX_CTL(pipe);
3339 temp = I915_READ(reg);
3340 if (HAS_PCH_CPT(dev)) {
3341 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3342 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3343 } else {
3344 temp &= ~FDI_LINK_TRAIN_NONE;
3345 temp |= FDI_LINK_TRAIN_PATTERN_1;
3346 }
3347 /* BPC in FDI rx is consistent with that in PIPECONF */
3348 temp &= ~(0x07 << 16);
3349 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3350 I915_WRITE(reg, temp);
3351
3352 POSTING_READ(reg);
3353 udelay(100);
3354 }
3355
3356 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3357 {
3358 struct intel_crtc *crtc;
3359
3360 /* Note that we don't need to be called with mode_config.lock here
3361 * as our list of CRTC objects is static for the lifetime of the
3362 * device and so cannot disappear as we iterate. Similarly, we can
3363 * happily treat the predicates as racy, atomic checks as userspace
3364 * cannot claim and pin a new fb without at least acquring the
3365 * struct_mutex and so serialising with us.
3366 */
3367 for_each_intel_crtc(dev, crtc) {
3368 if (atomic_read(&crtc->unpin_work_count) == 0)
3369 continue;
3370
3371 if (crtc->unpin_work)
3372 intel_wait_for_vblank(dev, crtc->pipe);
3373
3374 return true;
3375 }
3376
3377 return false;
3378 }
3379
3380 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3381 {
3382 struct drm_device *dev = crtc->dev;
3383 struct drm_i915_private *dev_priv = dev->dev_private;
3384
3385 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3386 WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3387 !intel_crtc_has_pending_flip(crtc),
3388 60*HZ) == 0);
3389
3390 if (crtc->primary->fb) {
3391 mutex_lock(&dev->struct_mutex);
3392 intel_finish_fb(crtc->primary->fb);
3393 mutex_unlock(&dev->struct_mutex);
3394 }
3395 }
3396
3397 /* Program iCLKIP clock to the desired frequency */
3398 static void lpt_program_iclkip(struct drm_crtc *crtc)
3399 {
3400 struct drm_device *dev = crtc->dev;
3401 struct drm_i915_private *dev_priv = dev->dev_private;
3402 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3403 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3404 u32 temp;
3405
3406 mutex_lock(&dev_priv->dpio_lock);
3407
3408 /* It is necessary to ungate the pixclk gate prior to programming
3409 * the divisors, and gate it back when it is done.
3410 */
3411 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3412
3413 /* Disable SSCCTL */
3414 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3415 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3416 SBI_SSCCTL_DISABLE,
3417 SBI_ICLK);
3418
3419 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3420 if (clock == 20000) {
3421 auxdiv = 1;
3422 divsel = 0x41;
3423 phaseinc = 0x20;
3424 } else {
3425 /* The iCLK virtual clock root frequency is in MHz,
3426 * but the adjusted_mode->crtc_clock in in KHz. To get the
3427 * divisors, it is necessary to divide one by another, so we
3428 * convert the virtual clock precision to KHz here for higher
3429 * precision.
3430 */
3431 u32 iclk_virtual_root_freq = 172800 * 1000;
3432 u32 iclk_pi_range = 64;
3433 u32 desired_divisor, msb_divisor_value, pi_value;
3434
3435 desired_divisor = (iclk_virtual_root_freq / clock);
3436 msb_divisor_value = desired_divisor / iclk_pi_range;
3437 pi_value = desired_divisor % iclk_pi_range;
3438
3439 auxdiv = 0;
3440 divsel = msb_divisor_value - 2;
3441 phaseinc = pi_value;
3442 }
3443
3444 /* This should not happen with any sane values */
3445 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3446 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3447 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3448 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3449
3450 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3451 clock,
3452 auxdiv,
3453 divsel,
3454 phasedir,
3455 phaseinc);
3456
3457 /* Program SSCDIVINTPHASE6 */
3458 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3459 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3460 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3461 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3462 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3463 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3464 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3465 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3466
3467 /* Program SSCAUXDIV */
3468 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3469 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3470 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3471 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3472
3473 /* Enable modulator and associated divider */
3474 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3475 temp &= ~SBI_SSCCTL_DISABLE;
3476 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3477
3478 /* Wait for initialization time */
3479 udelay(24);
3480
3481 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3482
3483 mutex_unlock(&dev_priv->dpio_lock);
3484 }
3485
3486 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3487 enum pipe pch_transcoder)
3488 {
3489 struct drm_device *dev = crtc->base.dev;
3490 struct drm_i915_private *dev_priv = dev->dev_private;
3491 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3492
3493 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3494 I915_READ(HTOTAL(cpu_transcoder)));
3495 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3496 I915_READ(HBLANK(cpu_transcoder)));
3497 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3498 I915_READ(HSYNC(cpu_transcoder)));
3499
3500 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3501 I915_READ(VTOTAL(cpu_transcoder)));
3502 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3503 I915_READ(VBLANK(cpu_transcoder)));
3504 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3505 I915_READ(VSYNC(cpu_transcoder)));
3506 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3507 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3508 }
3509
3510 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3511 {
3512 struct drm_i915_private *dev_priv = dev->dev_private;
3513 uint32_t temp;
3514
3515 temp = I915_READ(SOUTH_CHICKEN1);
3516 if (temp & FDI_BC_BIFURCATION_SELECT)
3517 return;
3518
3519 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3520 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3521
3522 temp |= FDI_BC_BIFURCATION_SELECT;
3523 DRM_DEBUG_KMS("enabling fdi C rx\n");
3524 I915_WRITE(SOUTH_CHICKEN1, temp);
3525 POSTING_READ(SOUTH_CHICKEN1);
3526 }
3527
3528 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3529 {
3530 struct drm_device *dev = intel_crtc->base.dev;
3531 struct drm_i915_private *dev_priv = dev->dev_private;
3532
3533 switch (intel_crtc->pipe) {
3534 case PIPE_A:
3535 break;
3536 case PIPE_B:
3537 if (intel_crtc->config.fdi_lanes > 2)
3538 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3539 else
3540 cpt_enable_fdi_bc_bifurcation(dev);
3541
3542 break;
3543 case PIPE_C:
3544 cpt_enable_fdi_bc_bifurcation(dev);
3545
3546 break;
3547 default:
3548 BUG();
3549 }
3550 }
3551
3552 /*
3553 * Enable PCH resources required for PCH ports:
3554 * - PCH PLLs
3555 * - FDI training & RX/TX
3556 * - update transcoder timings
3557 * - DP transcoding bits
3558 * - transcoder
3559 */
3560 static void ironlake_pch_enable(struct drm_crtc *crtc)
3561 {
3562 struct drm_device *dev = crtc->dev;
3563 struct drm_i915_private *dev_priv = dev->dev_private;
3564 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3565 int pipe = intel_crtc->pipe;
3566 u32 reg, temp;
3567
3568 assert_pch_transcoder_disabled(dev_priv, pipe);
3569
3570 if (IS_IVYBRIDGE(dev))
3571 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3572
3573 /* Write the TU size bits before fdi link training, so that error
3574 * detection works. */
3575 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3576 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3577
3578 /* For PCH output, training FDI link */
3579 dev_priv->display.fdi_link_train(crtc);
3580
3581 /* We need to program the right clock selection before writing the pixel
3582 * mutliplier into the DPLL. */
3583 if (HAS_PCH_CPT(dev)) {
3584 u32 sel;
3585
3586 temp = I915_READ(PCH_DPLL_SEL);
3587 temp |= TRANS_DPLL_ENABLE(pipe);
3588 sel = TRANS_DPLLB_SEL(pipe);
3589 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3590 temp |= sel;
3591 else
3592 temp &= ~sel;
3593 I915_WRITE(PCH_DPLL_SEL, temp);
3594 }
3595
3596 /* XXX: pch pll's can be enabled any time before we enable the PCH
3597 * transcoder, and we actually should do this to not upset any PCH
3598 * transcoder that already use the clock when we share it.
3599 *
3600 * Note that enable_shared_dpll tries to do the right thing, but
3601 * get_shared_dpll unconditionally resets the pll - we need that to have
3602 * the right LVDS enable sequence. */
3603 intel_enable_shared_dpll(intel_crtc);
3604
3605 /* set transcoder timing, panel must allow it */
3606 assert_panel_unlocked(dev_priv, pipe);
3607 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3608
3609 intel_fdi_normal_train(crtc);
3610
3611 /* For PCH DP, enable TRANS_DP_CTL */
3612 if (HAS_PCH_CPT(dev) &&
3613 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3614 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3615 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3616 reg = TRANS_DP_CTL(pipe);
3617 temp = I915_READ(reg);
3618 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3619 TRANS_DP_SYNC_MASK |
3620 TRANS_DP_BPC_MASK);
3621 temp |= (TRANS_DP_OUTPUT_ENABLE |
3622 TRANS_DP_ENH_FRAMING);
3623 temp |= bpc << 9; /* same format but at 11:9 */
3624
3625 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3626 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3627 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3628 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3629
3630 switch (intel_trans_dp_port_sel(crtc)) {
3631 case PCH_DP_B:
3632 temp |= TRANS_DP_PORT_SEL_B;
3633 break;
3634 case PCH_DP_C:
3635 temp |= TRANS_DP_PORT_SEL_C;
3636 break;
3637 case PCH_DP_D:
3638 temp |= TRANS_DP_PORT_SEL_D;
3639 break;
3640 default:
3641 BUG();
3642 }
3643
3644 I915_WRITE(reg, temp);
3645 }
3646
3647 ironlake_enable_pch_transcoder(dev_priv, pipe);
3648 }
3649
3650 static void lpt_pch_enable(struct drm_crtc *crtc)
3651 {
3652 struct drm_device *dev = crtc->dev;
3653 struct drm_i915_private *dev_priv = dev->dev_private;
3654 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3655 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3656
3657 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3658
3659 lpt_program_iclkip(crtc);
3660
3661 /* Set transcoder timing. */
3662 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3663
3664 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3665 }
3666
3667 void intel_put_shared_dpll(struct intel_crtc *crtc)
3668 {
3669 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3670
3671 if (pll == NULL)
3672 return;
3673
3674 if (pll->refcount == 0) {
3675 WARN(1, "bad %s refcount\n", pll->name);
3676 return;
3677 }
3678
3679 if (--pll->refcount == 0) {
3680 WARN_ON(pll->on);
3681 WARN_ON(pll->active);
3682 }
3683
3684 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3685 }
3686
3687 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3688 {
3689 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3690 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3691 enum intel_dpll_id i;
3692
3693 if (pll) {
3694 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3695 crtc->base.base.id, pll->name);
3696 intel_put_shared_dpll(crtc);
3697 }
3698
3699 if (HAS_PCH_IBX(dev_priv->dev)) {
3700 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3701 i = (enum intel_dpll_id) crtc->pipe;
3702 pll = &dev_priv->shared_dplls[i];
3703
3704 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3705 crtc->base.base.id, pll->name);
3706
3707 WARN_ON(pll->refcount);
3708
3709 goto found;
3710 }
3711
3712 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3713 pll = &dev_priv->shared_dplls[i];
3714
3715 /* Only want to check enabled timings first */
3716 if (pll->refcount == 0)
3717 continue;
3718
3719 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3720 sizeof(pll->hw_state)) == 0) {
3721 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3722 crtc->base.base.id,
3723 pll->name, pll->refcount, pll->active);
3724
3725 goto found;
3726 }
3727 }
3728
3729 /* Ok no matching timings, maybe there's a free one? */
3730 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3731 pll = &dev_priv->shared_dplls[i];
3732 if (pll->refcount == 0) {
3733 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3734 crtc->base.base.id, pll->name);
3735 goto found;
3736 }
3737 }
3738
3739 return NULL;
3740
3741 found:
3742 if (pll->refcount == 0)
3743 pll->hw_state = crtc->config.dpll_hw_state;
3744
3745 crtc->config.shared_dpll = i;
3746 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3747 pipe_name(crtc->pipe));
3748
3749 pll->refcount++;
3750
3751 return pll;
3752 }
3753
3754 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3755 {
3756 struct drm_i915_private *dev_priv = dev->dev_private;
3757 int dslreg = PIPEDSL(pipe);
3758 u32 temp;
3759
3760 temp = I915_READ(dslreg);
3761 udelay(500);
3762 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3763 if (wait_for(I915_READ(dslreg) != temp, 5))
3764 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3765 }
3766 }
3767
3768 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3769 {
3770 struct drm_device *dev = crtc->base.dev;
3771 struct drm_i915_private *dev_priv = dev->dev_private;
3772 int pipe = crtc->pipe;
3773
3774 if (crtc->config.pch_pfit.enabled) {
3775 /* Force use of hard-coded filter coefficients
3776 * as some pre-programmed values are broken,
3777 * e.g. x201.
3778 */
3779 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3780 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3781 PF_PIPE_SEL_IVB(pipe));
3782 else
3783 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3784 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3785 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3786 }
3787 }
3788
3789 static void intel_enable_planes(struct drm_crtc *crtc)
3790 {
3791 struct drm_device *dev = crtc->dev;
3792 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3793 struct drm_plane *plane;
3794 struct intel_plane *intel_plane;
3795
3796 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3797 intel_plane = to_intel_plane(plane);
3798 if (intel_plane->pipe == pipe)
3799 intel_plane_restore(&intel_plane->base);
3800 }
3801 }
3802
3803 static void intel_disable_planes(struct drm_crtc *crtc)
3804 {
3805 struct drm_device *dev = crtc->dev;
3806 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3807 struct drm_plane *plane;
3808 struct intel_plane *intel_plane;
3809
3810 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3811 intel_plane = to_intel_plane(plane);
3812 if (intel_plane->pipe == pipe)
3813 intel_plane_disable(&intel_plane->base);
3814 }
3815 }
3816
3817 void hsw_enable_ips(struct intel_crtc *crtc)
3818 {
3819 struct drm_device *dev = crtc->base.dev;
3820 struct drm_i915_private *dev_priv = dev->dev_private;
3821
3822 if (!crtc->config.ips_enabled)
3823 return;
3824
3825 /* We can only enable IPS after we enable a plane and wait for a vblank */
3826 intel_wait_for_vblank(dev, crtc->pipe);
3827
3828 assert_plane_enabled(dev_priv, crtc->plane);
3829 if (IS_BROADWELL(dev)) {
3830 mutex_lock(&dev_priv->rps.hw_lock);
3831 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3832 mutex_unlock(&dev_priv->rps.hw_lock);
3833 /* Quoting Art Runyan: "its not safe to expect any particular
3834 * value in IPS_CTL bit 31 after enabling IPS through the
3835 * mailbox." Moreover, the mailbox may return a bogus state,
3836 * so we need to just enable it and continue on.
3837 */
3838 } else {
3839 I915_WRITE(IPS_CTL, IPS_ENABLE);
3840 /* The bit only becomes 1 in the next vblank, so this wait here
3841 * is essentially intel_wait_for_vblank. If we don't have this
3842 * and don't wait for vblanks until the end of crtc_enable, then
3843 * the HW state readout code will complain that the expected
3844 * IPS_CTL value is not the one we read. */
3845 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3846 DRM_ERROR("Timed out waiting for IPS enable\n");
3847 }
3848 }
3849
3850 void hsw_disable_ips(struct intel_crtc *crtc)
3851 {
3852 struct drm_device *dev = crtc->base.dev;
3853 struct drm_i915_private *dev_priv = dev->dev_private;
3854
3855 if (!crtc->config.ips_enabled)
3856 return;
3857
3858 assert_plane_enabled(dev_priv, crtc->plane);
3859 if (IS_BROADWELL(dev)) {
3860 mutex_lock(&dev_priv->rps.hw_lock);
3861 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3862 mutex_unlock(&dev_priv->rps.hw_lock);
3863 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3864 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3865 DRM_ERROR("Timed out waiting for IPS disable\n");
3866 } else {
3867 I915_WRITE(IPS_CTL, 0);
3868 POSTING_READ(IPS_CTL);
3869 }
3870
3871 /* We need to wait for a vblank before we can disable the plane. */
3872 intel_wait_for_vblank(dev, crtc->pipe);
3873 }
3874
3875 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3876 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3877 {
3878 struct drm_device *dev = crtc->dev;
3879 struct drm_i915_private *dev_priv = dev->dev_private;
3880 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3881 enum pipe pipe = intel_crtc->pipe;
3882 int palreg = PALETTE(pipe);
3883 int i;
3884 bool reenable_ips = false;
3885
3886 /* The clocks have to be on to load the palette. */
3887 if (!crtc->enabled || !intel_crtc->active)
3888 return;
3889
3890 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3891 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3892 assert_dsi_pll_enabled(dev_priv);
3893 else
3894 assert_pll_enabled(dev_priv, pipe);
3895 }
3896
3897 /* use legacy palette for Ironlake */
3898 if (!HAS_GMCH_DISPLAY(dev))
3899 palreg = LGC_PALETTE(pipe);
3900
3901 /* Workaround : Do not read or write the pipe palette/gamma data while
3902 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3903 */
3904 if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3905 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3906 GAMMA_MODE_MODE_SPLIT)) {
3907 hsw_disable_ips(intel_crtc);
3908 reenable_ips = true;
3909 }
3910
3911 for (i = 0; i < 256; i++) {
3912 I915_WRITE(palreg + 4 * i,
3913 (intel_crtc->lut_r[i] << 16) |
3914 (intel_crtc->lut_g[i] << 8) |
3915 intel_crtc->lut_b[i]);
3916 }
3917
3918 if (reenable_ips)
3919 hsw_enable_ips(intel_crtc);
3920 }
3921
3922 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3923 {
3924 if (!enable && intel_crtc->overlay) {
3925 struct drm_device *dev = intel_crtc->base.dev;
3926 struct drm_i915_private *dev_priv = dev->dev_private;
3927
3928 mutex_lock(&dev->struct_mutex);
3929 dev_priv->mm.interruptible = false;
3930 (void) intel_overlay_switch_off(intel_crtc->overlay);
3931 dev_priv->mm.interruptible = true;
3932 mutex_unlock(&dev->struct_mutex);
3933 }
3934
3935 /* Let userspace switch the overlay on again. In most cases userspace
3936 * has to recompute where to put it anyway.
3937 */
3938 }
3939
3940 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
3941 {
3942 struct drm_device *dev = crtc->dev;
3943 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3944 int pipe = intel_crtc->pipe;
3945
3946 drm_vblank_on(dev, pipe);
3947
3948 intel_enable_primary_hw_plane(crtc->primary, crtc);
3949 intel_enable_planes(crtc);
3950 intel_crtc_update_cursor(crtc, true);
3951 intel_crtc_dpms_overlay(intel_crtc, true);
3952
3953 hsw_enable_ips(intel_crtc);
3954
3955 mutex_lock(&dev->struct_mutex);
3956 intel_update_fbc(dev);
3957 mutex_unlock(&dev->struct_mutex);
3958
3959 /*
3960 * FIXME: Once we grow proper nuclear flip support out of this we need
3961 * to compute the mask of flip planes precisely. For the time being
3962 * consider this a flip from a NULL plane.
3963 */
3964 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
3965 }
3966
3967 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
3968 {
3969 struct drm_device *dev = crtc->dev;
3970 struct drm_i915_private *dev_priv = dev->dev_private;
3971 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3972 int pipe = intel_crtc->pipe;
3973 int plane = intel_crtc->plane;
3974
3975 intel_crtc_wait_for_pending_flips(crtc);
3976
3977 if (dev_priv->fbc.plane == plane)
3978 intel_disable_fbc(dev);
3979
3980 hsw_disable_ips(intel_crtc);
3981
3982 intel_crtc_dpms_overlay(intel_crtc, false);
3983 intel_crtc_update_cursor(crtc, false);
3984 intel_disable_planes(crtc);
3985 intel_disable_primary_hw_plane(crtc->primary, crtc);
3986
3987 /*
3988 * FIXME: Once we grow proper nuclear flip support out of this we need
3989 * to compute the mask of flip planes precisely. For the time being
3990 * consider this a flip to a NULL plane.
3991 */
3992 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
3993
3994 drm_vblank_off(dev, pipe);
3995 }
3996
3997 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3998 {
3999 struct drm_device *dev = crtc->dev;
4000 struct drm_i915_private *dev_priv = dev->dev_private;
4001 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4002 struct intel_encoder *encoder;
4003 int pipe = intel_crtc->pipe;
4004
4005 WARN_ON(!crtc->enabled);
4006
4007 if (intel_crtc->active)
4008 return;
4009
4010 if (intel_crtc->config.has_pch_encoder)
4011 intel_prepare_shared_dpll(intel_crtc);
4012
4013 if (intel_crtc->config.has_dp_encoder)
4014 intel_dp_set_m_n(intel_crtc);
4015
4016 intel_set_pipe_timings(intel_crtc);
4017
4018 if (intel_crtc->config.has_pch_encoder) {
4019 intel_cpu_transcoder_set_m_n(intel_crtc,
4020 &intel_crtc->config.fdi_m_n, NULL);
4021 }
4022
4023 ironlake_set_pipeconf(crtc);
4024
4025 intel_crtc->active = true;
4026
4027 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4028 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4029
4030 for_each_encoder_on_crtc(dev, crtc, encoder)
4031 if (encoder->pre_enable)
4032 encoder->pre_enable(encoder);
4033
4034 if (intel_crtc->config.has_pch_encoder) {
4035 /* Note: FDI PLL enabling _must_ be done before we enable the
4036 * cpu pipes, hence this is separate from all the other fdi/pch
4037 * enabling. */
4038 ironlake_fdi_pll_enable(intel_crtc);
4039 } else {
4040 assert_fdi_tx_disabled(dev_priv, pipe);
4041 assert_fdi_rx_disabled(dev_priv, pipe);
4042 }
4043
4044 ironlake_pfit_enable(intel_crtc);
4045
4046 /*
4047 * On ILK+ LUT must be loaded before the pipe is running but with
4048 * clocks enabled
4049 */
4050 intel_crtc_load_lut(crtc);
4051
4052 intel_update_watermarks(crtc);
4053 intel_enable_pipe(intel_crtc);
4054
4055 if (intel_crtc->config.has_pch_encoder)
4056 ironlake_pch_enable(crtc);
4057
4058 for_each_encoder_on_crtc(dev, crtc, encoder)
4059 encoder->enable(encoder);
4060
4061 if (HAS_PCH_CPT(dev))
4062 cpt_verify_modeset(dev, intel_crtc->pipe);
4063
4064 intel_crtc_enable_planes(crtc);
4065 }
4066
4067 /* IPS only exists on ULT machines and is tied to pipe A. */
4068 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4069 {
4070 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4071 }
4072
4073 /*
4074 * This implements the workaround described in the "notes" section of the mode
4075 * set sequence documentation. When going from no pipes or single pipe to
4076 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4077 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4078 */
4079 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4080 {
4081 struct drm_device *dev = crtc->base.dev;
4082 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4083
4084 /* We want to get the other_active_crtc only if there's only 1 other
4085 * active crtc. */
4086 for_each_intel_crtc(dev, crtc_it) {
4087 if (!crtc_it->active || crtc_it == crtc)
4088 continue;
4089
4090 if (other_active_crtc)
4091 return;
4092
4093 other_active_crtc = crtc_it;
4094 }
4095 if (!other_active_crtc)
4096 return;
4097
4098 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4099 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4100 }
4101
4102 static void haswell_crtc_enable(struct drm_crtc *crtc)
4103 {
4104 struct drm_device *dev = crtc->dev;
4105 struct drm_i915_private *dev_priv = dev->dev_private;
4106 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4107 struct intel_encoder *encoder;
4108 int pipe = intel_crtc->pipe;
4109
4110 WARN_ON(!crtc->enabled);
4111
4112 if (intel_crtc->active)
4113 return;
4114
4115 if (intel_crtc_to_shared_dpll(intel_crtc))
4116 intel_enable_shared_dpll(intel_crtc);
4117
4118 if (intel_crtc->config.has_dp_encoder)
4119 intel_dp_set_m_n(intel_crtc);
4120
4121 intel_set_pipe_timings(intel_crtc);
4122
4123 if (intel_crtc->config.has_pch_encoder) {
4124 intel_cpu_transcoder_set_m_n(intel_crtc,
4125 &intel_crtc->config.fdi_m_n, NULL);
4126 }
4127
4128 haswell_set_pipeconf(crtc);
4129
4130 intel_set_pipe_csc(crtc);
4131
4132 intel_crtc->active = true;
4133
4134 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4135 for_each_encoder_on_crtc(dev, crtc, encoder)
4136 if (encoder->pre_enable)
4137 encoder->pre_enable(encoder);
4138
4139 if (intel_crtc->config.has_pch_encoder) {
4140 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4141 dev_priv->display.fdi_link_train(crtc);
4142 }
4143
4144 intel_ddi_enable_pipe_clock(intel_crtc);
4145
4146 ironlake_pfit_enable(intel_crtc);
4147
4148 /*
4149 * On ILK+ LUT must be loaded before the pipe is running but with
4150 * clocks enabled
4151 */
4152 intel_crtc_load_lut(crtc);
4153
4154 intel_ddi_set_pipe_settings(crtc);
4155 intel_ddi_enable_transcoder_func(crtc);
4156
4157 intel_update_watermarks(crtc);
4158 intel_enable_pipe(intel_crtc);
4159
4160 if (intel_crtc->config.has_pch_encoder)
4161 lpt_pch_enable(crtc);
4162
4163 if (intel_crtc->config.dp_encoder_is_mst)
4164 intel_ddi_set_vc_payload_alloc(crtc, true);
4165
4166 for_each_encoder_on_crtc(dev, crtc, encoder) {
4167 encoder->enable(encoder);
4168 intel_opregion_notify_encoder(encoder, true);
4169 }
4170
4171 /* If we change the relative order between pipe/planes enabling, we need
4172 * to change the workaround. */
4173 haswell_mode_set_planes_workaround(intel_crtc);
4174 intel_crtc_enable_planes(crtc);
4175 }
4176
4177 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4178 {
4179 struct drm_device *dev = crtc->base.dev;
4180 struct drm_i915_private *dev_priv = dev->dev_private;
4181 int pipe = crtc->pipe;
4182
4183 /* To avoid upsetting the power well on haswell only disable the pfit if
4184 * it's in use. The hw state code will make sure we get this right. */
4185 if (crtc->config.pch_pfit.enabled) {
4186 I915_WRITE(PF_CTL(pipe), 0);
4187 I915_WRITE(PF_WIN_POS(pipe), 0);
4188 I915_WRITE(PF_WIN_SZ(pipe), 0);
4189 }
4190 }
4191
4192 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4193 {
4194 struct drm_device *dev = crtc->dev;
4195 struct drm_i915_private *dev_priv = dev->dev_private;
4196 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4197 struct intel_encoder *encoder;
4198 int pipe = intel_crtc->pipe;
4199 u32 reg, temp;
4200
4201 if (!intel_crtc->active)
4202 return;
4203
4204 intel_crtc_disable_planes(crtc);
4205
4206 for_each_encoder_on_crtc(dev, crtc, encoder)
4207 encoder->disable(encoder);
4208
4209 if (intel_crtc->config.has_pch_encoder)
4210 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
4211
4212 intel_disable_pipe(intel_crtc);
4213
4214 if (intel_crtc->config.dp_encoder_is_mst)
4215 intel_ddi_set_vc_payload_alloc(crtc, false);
4216
4217 ironlake_pfit_disable(intel_crtc);
4218
4219 for_each_encoder_on_crtc(dev, crtc, encoder)
4220 if (encoder->post_disable)
4221 encoder->post_disable(encoder);
4222
4223 if (intel_crtc->config.has_pch_encoder) {
4224 ironlake_fdi_disable(crtc);
4225
4226 ironlake_disable_pch_transcoder(dev_priv, pipe);
4227 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4228
4229 if (HAS_PCH_CPT(dev)) {
4230 /* disable TRANS_DP_CTL */
4231 reg = TRANS_DP_CTL(pipe);
4232 temp = I915_READ(reg);
4233 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4234 TRANS_DP_PORT_SEL_MASK);
4235 temp |= TRANS_DP_PORT_SEL_NONE;
4236 I915_WRITE(reg, temp);
4237
4238 /* disable DPLL_SEL */
4239 temp = I915_READ(PCH_DPLL_SEL);
4240 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4241 I915_WRITE(PCH_DPLL_SEL, temp);
4242 }
4243
4244 /* disable PCH DPLL */
4245 intel_disable_shared_dpll(intel_crtc);
4246
4247 ironlake_fdi_pll_disable(intel_crtc);
4248 }
4249
4250 intel_crtc->active = false;
4251 intel_update_watermarks(crtc);
4252
4253 mutex_lock(&dev->struct_mutex);
4254 intel_update_fbc(dev);
4255 mutex_unlock(&dev->struct_mutex);
4256 }
4257
4258 static void haswell_crtc_disable(struct drm_crtc *crtc)
4259 {
4260 struct drm_device *dev = crtc->dev;
4261 struct drm_i915_private *dev_priv = dev->dev_private;
4262 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4263 struct intel_encoder *encoder;
4264 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4265
4266 if (!intel_crtc->active)
4267 return;
4268
4269 intel_crtc_disable_planes(crtc);
4270
4271 for_each_encoder_on_crtc(dev, crtc, encoder) {
4272 intel_opregion_notify_encoder(encoder, false);
4273 encoder->disable(encoder);
4274 }
4275
4276 if (intel_crtc->config.has_pch_encoder)
4277 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4278 intel_disable_pipe(intel_crtc);
4279
4280 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4281
4282 ironlake_pfit_disable(intel_crtc);
4283
4284 intel_ddi_disable_pipe_clock(intel_crtc);
4285
4286 if (intel_crtc->config.has_pch_encoder) {
4287 lpt_disable_pch_transcoder(dev_priv);
4288 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4289 intel_ddi_fdi_disable(crtc);
4290 }
4291
4292 for_each_encoder_on_crtc(dev, crtc, encoder)
4293 if (encoder->post_disable)
4294 encoder->post_disable(encoder);
4295
4296 intel_crtc->active = false;
4297 intel_update_watermarks(crtc);
4298
4299 mutex_lock(&dev->struct_mutex);
4300 intel_update_fbc(dev);
4301 mutex_unlock(&dev->struct_mutex);
4302
4303 if (intel_crtc_to_shared_dpll(intel_crtc))
4304 intel_disable_shared_dpll(intel_crtc);
4305 }
4306
4307 static void ironlake_crtc_off(struct drm_crtc *crtc)
4308 {
4309 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4310 intel_put_shared_dpll(intel_crtc);
4311 }
4312
4313
4314 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4315 {
4316 struct drm_device *dev = crtc->base.dev;
4317 struct drm_i915_private *dev_priv = dev->dev_private;
4318 struct intel_crtc_config *pipe_config = &crtc->config;
4319
4320 if (!crtc->config.gmch_pfit.control)
4321 return;
4322
4323 /*
4324 * The panel fitter should only be adjusted whilst the pipe is disabled,
4325 * according to register description and PRM.
4326 */
4327 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4328 assert_pipe_disabled(dev_priv, crtc->pipe);
4329
4330 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4331 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4332
4333 /* Border color in case we don't scale up to the full screen. Black by
4334 * default, change to something else for debugging. */
4335 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4336 }
4337
4338 static enum intel_display_power_domain port_to_power_domain(enum port port)
4339 {
4340 switch (port) {
4341 case PORT_A:
4342 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4343 case PORT_B:
4344 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4345 case PORT_C:
4346 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4347 case PORT_D:
4348 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4349 default:
4350 WARN_ON_ONCE(1);
4351 return POWER_DOMAIN_PORT_OTHER;
4352 }
4353 }
4354
4355 #define for_each_power_domain(domain, mask) \
4356 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4357 if ((1 << (domain)) & (mask))
4358
4359 enum intel_display_power_domain
4360 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4361 {
4362 struct drm_device *dev = intel_encoder->base.dev;
4363 struct intel_digital_port *intel_dig_port;
4364
4365 switch (intel_encoder->type) {
4366 case INTEL_OUTPUT_UNKNOWN:
4367 /* Only DDI platforms should ever use this output type */
4368 WARN_ON_ONCE(!HAS_DDI(dev));
4369 case INTEL_OUTPUT_DISPLAYPORT:
4370 case INTEL_OUTPUT_HDMI:
4371 case INTEL_OUTPUT_EDP:
4372 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4373 return port_to_power_domain(intel_dig_port->port);
4374 case INTEL_OUTPUT_DP_MST:
4375 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4376 return port_to_power_domain(intel_dig_port->port);
4377 case INTEL_OUTPUT_ANALOG:
4378 return POWER_DOMAIN_PORT_CRT;
4379 case INTEL_OUTPUT_DSI:
4380 return POWER_DOMAIN_PORT_DSI;
4381 default:
4382 return POWER_DOMAIN_PORT_OTHER;
4383 }
4384 }
4385
4386 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4387 {
4388 struct drm_device *dev = crtc->dev;
4389 struct intel_encoder *intel_encoder;
4390 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4391 enum pipe pipe = intel_crtc->pipe;
4392 unsigned long mask;
4393 enum transcoder transcoder;
4394
4395 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4396
4397 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4398 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4399 if (intel_crtc->config.pch_pfit.enabled ||
4400 intel_crtc->config.pch_pfit.force_thru)
4401 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4402
4403 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4404 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4405
4406 return mask;
4407 }
4408
4409 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4410 bool enable)
4411 {
4412 if (dev_priv->power_domains.init_power_on == enable)
4413 return;
4414
4415 if (enable)
4416 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4417 else
4418 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4419
4420 dev_priv->power_domains.init_power_on = enable;
4421 }
4422
4423 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4424 {
4425 struct drm_i915_private *dev_priv = dev->dev_private;
4426 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4427 struct intel_crtc *crtc;
4428
4429 /*
4430 * First get all needed power domains, then put all unneeded, to avoid
4431 * any unnecessary toggling of the power wells.
4432 */
4433 for_each_intel_crtc(dev, crtc) {
4434 enum intel_display_power_domain domain;
4435
4436 if (!crtc->base.enabled)
4437 continue;
4438
4439 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4440
4441 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4442 intel_display_power_get(dev_priv, domain);
4443 }
4444
4445 for_each_intel_crtc(dev, crtc) {
4446 enum intel_display_power_domain domain;
4447
4448 for_each_power_domain(domain, crtc->enabled_power_domains)
4449 intel_display_power_put(dev_priv, domain);
4450
4451 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4452 }
4453
4454 intel_display_set_init_power(dev_priv, false);
4455 }
4456
4457 /* returns HPLL frequency in kHz */
4458 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4459 {
4460 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4461
4462 /* Obtain SKU information */
4463 mutex_lock(&dev_priv->dpio_lock);
4464 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4465 CCK_FUSE_HPLL_FREQ_MASK;
4466 mutex_unlock(&dev_priv->dpio_lock);
4467
4468 return vco_freq[hpll_freq] * 1000;
4469 }
4470
4471 static void vlv_update_cdclk(struct drm_device *dev)
4472 {
4473 struct drm_i915_private *dev_priv = dev->dev_private;
4474
4475 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4476 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz",
4477 dev_priv->vlv_cdclk_freq);
4478
4479 /*
4480 * Program the gmbus_freq based on the cdclk frequency.
4481 * BSpec erroneously claims we should aim for 4MHz, but
4482 * in fact 1MHz is the correct frequency.
4483 */
4484 I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq);
4485 }
4486
4487 /* Adjust CDclk dividers to allow high res or save power if possible */
4488 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4489 {
4490 struct drm_i915_private *dev_priv = dev->dev_private;
4491 u32 val, cmd;
4492
4493 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4494
4495 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4496 cmd = 2;
4497 else if (cdclk == 266667)
4498 cmd = 1;
4499 else
4500 cmd = 0;
4501
4502 mutex_lock(&dev_priv->rps.hw_lock);
4503 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4504 val &= ~DSPFREQGUAR_MASK;
4505 val |= (cmd << DSPFREQGUAR_SHIFT);
4506 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4507 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4508 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4509 50)) {
4510 DRM_ERROR("timed out waiting for CDclk change\n");
4511 }
4512 mutex_unlock(&dev_priv->rps.hw_lock);
4513
4514 if (cdclk == 400000) {
4515 u32 divider, vco;
4516
4517 vco = valleyview_get_vco(dev_priv);
4518 divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1;
4519
4520 mutex_lock(&dev_priv->dpio_lock);
4521 /* adjust cdclk divider */
4522 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4523 val &= ~DISPLAY_FREQUENCY_VALUES;
4524 val |= divider;
4525 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4526
4527 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4528 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4529 50))
4530 DRM_ERROR("timed out waiting for CDclk change\n");
4531 mutex_unlock(&dev_priv->dpio_lock);
4532 }
4533
4534 mutex_lock(&dev_priv->dpio_lock);
4535 /* adjust self-refresh exit latency value */
4536 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4537 val &= ~0x7f;
4538
4539 /*
4540 * For high bandwidth configs, we set a higher latency in the bunit
4541 * so that the core display fetch happens in time to avoid underruns.
4542 */
4543 if (cdclk == 400000)
4544 val |= 4500 / 250; /* 4.5 usec */
4545 else
4546 val |= 3000 / 250; /* 3.0 usec */
4547 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4548 mutex_unlock(&dev_priv->dpio_lock);
4549
4550 vlv_update_cdclk(dev);
4551 }
4552
4553 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4554 {
4555 struct drm_i915_private *dev_priv = dev->dev_private;
4556 u32 val, cmd;
4557
4558 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4559
4560 switch (cdclk) {
4561 case 400000:
4562 cmd = 3;
4563 break;
4564 case 333333:
4565 case 320000:
4566 cmd = 2;
4567 break;
4568 case 266667:
4569 cmd = 1;
4570 break;
4571 case 200000:
4572 cmd = 0;
4573 break;
4574 default:
4575 WARN_ON(1);
4576 return;
4577 }
4578
4579 mutex_lock(&dev_priv->rps.hw_lock);
4580 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4581 val &= ~DSPFREQGUAR_MASK_CHV;
4582 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4583 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4584 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4585 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4586 50)) {
4587 DRM_ERROR("timed out waiting for CDclk change\n");
4588 }
4589 mutex_unlock(&dev_priv->rps.hw_lock);
4590
4591 vlv_update_cdclk(dev);
4592 }
4593
4594 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4595 int max_pixclk)
4596 {
4597 int vco = valleyview_get_vco(dev_priv);
4598 int freq_320 = (vco << 1) % 320000 != 0 ? 333333 : 320000;
4599
4600 /* FIXME: Punit isn't quite ready yet */
4601 if (IS_CHERRYVIEW(dev_priv->dev))
4602 return 400000;
4603
4604 /*
4605 * Really only a few cases to deal with, as only 4 CDclks are supported:
4606 * 200MHz
4607 * 267MHz
4608 * 320/333MHz (depends on HPLL freq)
4609 * 400MHz
4610 * So we check to see whether we're above 90% of the lower bin and
4611 * adjust if needed.
4612 *
4613 * We seem to get an unstable or solid color picture at 200MHz.
4614 * Not sure what's wrong. For now use 200MHz only when all pipes
4615 * are off.
4616 */
4617 if (max_pixclk > freq_320*9/10)
4618 return 400000;
4619 else if (max_pixclk > 266667*9/10)
4620 return freq_320;
4621 else if (max_pixclk > 0)
4622 return 266667;
4623 else
4624 return 200000;
4625 }
4626
4627 /* compute the max pixel clock for new configuration */
4628 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4629 {
4630 struct drm_device *dev = dev_priv->dev;
4631 struct intel_crtc *intel_crtc;
4632 int max_pixclk = 0;
4633
4634 for_each_intel_crtc(dev, intel_crtc) {
4635 if (intel_crtc->new_enabled)
4636 max_pixclk = max(max_pixclk,
4637 intel_crtc->new_config->adjusted_mode.crtc_clock);
4638 }
4639
4640 return max_pixclk;
4641 }
4642
4643 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4644 unsigned *prepare_pipes)
4645 {
4646 struct drm_i915_private *dev_priv = dev->dev_private;
4647 struct intel_crtc *intel_crtc;
4648 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4649
4650 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4651 dev_priv->vlv_cdclk_freq)
4652 return;
4653
4654 /* disable/enable all currently active pipes while we change cdclk */
4655 for_each_intel_crtc(dev, intel_crtc)
4656 if (intel_crtc->base.enabled)
4657 *prepare_pipes |= (1 << intel_crtc->pipe);
4658 }
4659
4660 static void valleyview_modeset_global_resources(struct drm_device *dev)
4661 {
4662 struct drm_i915_private *dev_priv = dev->dev_private;
4663 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4664 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4665
4666 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
4667 if (IS_CHERRYVIEW(dev))
4668 cherryview_set_cdclk(dev, req_cdclk);
4669 else
4670 valleyview_set_cdclk(dev, req_cdclk);
4671 }
4672
4673 modeset_update_crtc_power_domains(dev);
4674 }
4675
4676 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4677 {
4678 struct drm_device *dev = crtc->dev;
4679 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4680 struct intel_encoder *encoder;
4681 int pipe = intel_crtc->pipe;
4682 bool is_dsi;
4683
4684 WARN_ON(!crtc->enabled);
4685
4686 if (intel_crtc->active)
4687 return;
4688
4689 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4690
4691 if (!is_dsi) {
4692 if (IS_CHERRYVIEW(dev))
4693 chv_prepare_pll(intel_crtc);
4694 else
4695 vlv_prepare_pll(intel_crtc);
4696 }
4697
4698 if (intel_crtc->config.has_dp_encoder)
4699 intel_dp_set_m_n(intel_crtc);
4700
4701 intel_set_pipe_timings(intel_crtc);
4702
4703 i9xx_set_pipeconf(intel_crtc);
4704
4705 intel_crtc->active = true;
4706
4707 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4708
4709 for_each_encoder_on_crtc(dev, crtc, encoder)
4710 if (encoder->pre_pll_enable)
4711 encoder->pre_pll_enable(encoder);
4712
4713 if (!is_dsi) {
4714 if (IS_CHERRYVIEW(dev))
4715 chv_enable_pll(intel_crtc);
4716 else
4717 vlv_enable_pll(intel_crtc);
4718 }
4719
4720 for_each_encoder_on_crtc(dev, crtc, encoder)
4721 if (encoder->pre_enable)
4722 encoder->pre_enable(encoder);
4723
4724 i9xx_pfit_enable(intel_crtc);
4725
4726 intel_crtc_load_lut(crtc);
4727
4728 intel_update_watermarks(crtc);
4729 intel_enable_pipe(intel_crtc);
4730
4731 for_each_encoder_on_crtc(dev, crtc, encoder)
4732 encoder->enable(encoder);
4733
4734 intel_crtc_enable_planes(crtc);
4735
4736 /* Underruns don't raise interrupts, so check manually. */
4737 i9xx_check_fifo_underruns(dev);
4738 }
4739
4740 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4741 {
4742 struct drm_device *dev = crtc->base.dev;
4743 struct drm_i915_private *dev_priv = dev->dev_private;
4744
4745 I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4746 I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4747 }
4748
4749 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4750 {
4751 struct drm_device *dev = crtc->dev;
4752 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4753 struct intel_encoder *encoder;
4754 int pipe = intel_crtc->pipe;
4755
4756 WARN_ON(!crtc->enabled);
4757
4758 if (intel_crtc->active)
4759 return;
4760
4761 i9xx_set_pll_dividers(intel_crtc);
4762
4763 if (intel_crtc->config.has_dp_encoder)
4764 intel_dp_set_m_n(intel_crtc);
4765
4766 intel_set_pipe_timings(intel_crtc);
4767
4768 i9xx_set_pipeconf(intel_crtc);
4769
4770 intel_crtc->active = true;
4771
4772 if (!IS_GEN2(dev))
4773 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4774
4775 for_each_encoder_on_crtc(dev, crtc, encoder)
4776 if (encoder->pre_enable)
4777 encoder->pre_enable(encoder);
4778
4779 i9xx_enable_pll(intel_crtc);
4780
4781 i9xx_pfit_enable(intel_crtc);
4782
4783 intel_crtc_load_lut(crtc);
4784
4785 intel_update_watermarks(crtc);
4786 intel_enable_pipe(intel_crtc);
4787
4788 for_each_encoder_on_crtc(dev, crtc, encoder)
4789 encoder->enable(encoder);
4790
4791 intel_crtc_enable_planes(crtc);
4792
4793 /*
4794 * Gen2 reports pipe underruns whenever all planes are disabled.
4795 * So don't enable underrun reporting before at least some planes
4796 * are enabled.
4797 * FIXME: Need to fix the logic to work when we turn off all planes
4798 * but leave the pipe running.
4799 */
4800 if (IS_GEN2(dev))
4801 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4802
4803 /* Underruns don't raise interrupts, so check manually. */
4804 i9xx_check_fifo_underruns(dev);
4805 }
4806
4807 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4808 {
4809 struct drm_device *dev = crtc->base.dev;
4810 struct drm_i915_private *dev_priv = dev->dev_private;
4811
4812 if (!crtc->config.gmch_pfit.control)
4813 return;
4814
4815 assert_pipe_disabled(dev_priv, crtc->pipe);
4816
4817 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4818 I915_READ(PFIT_CONTROL));
4819 I915_WRITE(PFIT_CONTROL, 0);
4820 }
4821
4822 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4823 {
4824 struct drm_device *dev = crtc->dev;
4825 struct drm_i915_private *dev_priv = dev->dev_private;
4826 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4827 struct intel_encoder *encoder;
4828 int pipe = intel_crtc->pipe;
4829
4830 if (!intel_crtc->active)
4831 return;
4832
4833 /*
4834 * Gen2 reports pipe underruns whenever all planes are disabled.
4835 * So diasble underrun reporting before all the planes get disabled.
4836 * FIXME: Need to fix the logic to work when we turn off all planes
4837 * but leave the pipe running.
4838 */
4839 if (IS_GEN2(dev))
4840 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4841
4842 /*
4843 * Vblank time updates from the shadow to live plane control register
4844 * are blocked if the memory self-refresh mode is active at that
4845 * moment. So to make sure the plane gets truly disabled, disable
4846 * first the self-refresh mode. The self-refresh enable bit in turn
4847 * will be checked/applied by the HW only at the next frame start
4848 * event which is after the vblank start event, so we need to have a
4849 * wait-for-vblank between disabling the plane and the pipe.
4850 */
4851 intel_set_memory_cxsr(dev_priv, false);
4852 intel_crtc_disable_planes(crtc);
4853
4854 for_each_encoder_on_crtc(dev, crtc, encoder)
4855 encoder->disable(encoder);
4856
4857 /*
4858 * On gen2 planes are double buffered but the pipe isn't, so we must
4859 * wait for planes to fully turn off before disabling the pipe.
4860 * We also need to wait on all gmch platforms because of the
4861 * self-refresh mode constraint explained above.
4862 */
4863 intel_wait_for_vblank(dev, pipe);
4864
4865 intel_disable_pipe(intel_crtc);
4866
4867 i9xx_pfit_disable(intel_crtc);
4868
4869 for_each_encoder_on_crtc(dev, crtc, encoder)
4870 if (encoder->post_disable)
4871 encoder->post_disable(encoder);
4872
4873 if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
4874 if (IS_CHERRYVIEW(dev))
4875 chv_disable_pll(dev_priv, pipe);
4876 else if (IS_VALLEYVIEW(dev))
4877 vlv_disable_pll(dev_priv, pipe);
4878 else
4879 i9xx_disable_pll(dev_priv, pipe);
4880 }
4881
4882 if (!IS_GEN2(dev))
4883 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4884
4885 intel_crtc->active = false;
4886 intel_update_watermarks(crtc);
4887
4888 mutex_lock(&dev->struct_mutex);
4889 intel_update_fbc(dev);
4890 mutex_unlock(&dev->struct_mutex);
4891 }
4892
4893 static void i9xx_crtc_off(struct drm_crtc *crtc)
4894 {
4895 }
4896
4897 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4898 bool enabled)
4899 {
4900 struct drm_device *dev = crtc->dev;
4901 struct drm_i915_master_private *master_priv;
4902 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4903 int pipe = intel_crtc->pipe;
4904
4905 if (!dev->primary->master)
4906 return;
4907
4908 master_priv = dev->primary->master->driver_priv;
4909 if (!master_priv->sarea_priv)
4910 return;
4911
4912 switch (pipe) {
4913 case 0:
4914 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4915 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4916 break;
4917 case 1:
4918 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4919 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4920 break;
4921 default:
4922 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4923 break;
4924 }
4925 }
4926
4927 /* Master function to enable/disable CRTC and corresponding power wells */
4928 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
4929 {
4930 struct drm_device *dev = crtc->dev;
4931 struct drm_i915_private *dev_priv = dev->dev_private;
4932 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4933 enum intel_display_power_domain domain;
4934 unsigned long domains;
4935
4936 if (enable) {
4937 if (!intel_crtc->active) {
4938 domains = get_crtc_power_domains(crtc);
4939 for_each_power_domain(domain, domains)
4940 intel_display_power_get(dev_priv, domain);
4941 intel_crtc->enabled_power_domains = domains;
4942
4943 dev_priv->display.crtc_enable(crtc);
4944 }
4945 } else {
4946 if (intel_crtc->active) {
4947 dev_priv->display.crtc_disable(crtc);
4948
4949 domains = intel_crtc->enabled_power_domains;
4950 for_each_power_domain(domain, domains)
4951 intel_display_power_put(dev_priv, domain);
4952 intel_crtc->enabled_power_domains = 0;
4953 }
4954 }
4955 }
4956
4957 /**
4958 * Sets the power management mode of the pipe and plane.
4959 */
4960 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4961 {
4962 struct drm_device *dev = crtc->dev;
4963 struct intel_encoder *intel_encoder;
4964 bool enable = false;
4965
4966 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4967 enable |= intel_encoder->connectors_active;
4968
4969 intel_crtc_control(crtc, enable);
4970
4971 intel_crtc_update_sarea(crtc, enable);
4972 }
4973
4974 static void intel_crtc_disable(struct drm_crtc *crtc)
4975 {
4976 struct drm_device *dev = crtc->dev;
4977 struct drm_connector *connector;
4978 struct drm_i915_private *dev_priv = dev->dev_private;
4979 struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
4980 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4981
4982 /* crtc should still be enabled when we disable it. */
4983 WARN_ON(!crtc->enabled);
4984
4985 dev_priv->display.crtc_disable(crtc);
4986 intel_crtc_update_sarea(crtc, false);
4987 dev_priv->display.off(crtc);
4988
4989 if (crtc->primary->fb) {
4990 mutex_lock(&dev->struct_mutex);
4991 intel_unpin_fb_obj(old_obj);
4992 i915_gem_track_fb(old_obj, NULL,
4993 INTEL_FRONTBUFFER_PRIMARY(pipe));
4994 mutex_unlock(&dev->struct_mutex);
4995 crtc->primary->fb = NULL;
4996 }
4997
4998 /* Update computed state. */
4999 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5000 if (!connector->encoder || !connector->encoder->crtc)
5001 continue;
5002
5003 if (connector->encoder->crtc != crtc)
5004 continue;
5005
5006 connector->dpms = DRM_MODE_DPMS_OFF;
5007 to_intel_encoder(connector->encoder)->connectors_active = false;
5008 }
5009 }
5010
5011 void intel_encoder_destroy(struct drm_encoder *encoder)
5012 {
5013 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5014
5015 drm_encoder_cleanup(encoder);
5016 kfree(intel_encoder);
5017 }
5018
5019 /* Simple dpms helper for encoders with just one connector, no cloning and only
5020 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5021 * state of the entire output pipe. */
5022 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5023 {
5024 if (mode == DRM_MODE_DPMS_ON) {
5025 encoder->connectors_active = true;
5026
5027 intel_crtc_update_dpms(encoder->base.crtc);
5028 } else {
5029 encoder->connectors_active = false;
5030
5031 intel_crtc_update_dpms(encoder->base.crtc);
5032 }
5033 }
5034
5035 /* Cross check the actual hw state with our own modeset state tracking (and it's
5036 * internal consistency). */
5037 static void intel_connector_check_state(struct intel_connector *connector)
5038 {
5039 if (connector->get_hw_state(connector)) {
5040 struct intel_encoder *encoder = connector->encoder;
5041 struct drm_crtc *crtc;
5042 bool encoder_enabled;
5043 enum pipe pipe;
5044
5045 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5046 connector->base.base.id,
5047 connector->base.name);
5048
5049 /* there is no real hw state for MST connectors */
5050 if (connector->mst_port)
5051 return;
5052
5053 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5054 "wrong connector dpms state\n");
5055 WARN(connector->base.encoder != &encoder->base,
5056 "active connector not linked to encoder\n");
5057
5058 if (encoder) {
5059 WARN(!encoder->connectors_active,
5060 "encoder->connectors_active not set\n");
5061
5062 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5063 WARN(!encoder_enabled, "encoder not enabled\n");
5064 if (WARN_ON(!encoder->base.crtc))
5065 return;
5066
5067 crtc = encoder->base.crtc;
5068
5069 WARN(!crtc->enabled, "crtc not enabled\n");
5070 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5071 WARN(pipe != to_intel_crtc(crtc)->pipe,
5072 "encoder active on the wrong pipe\n");
5073 }
5074 }
5075 }
5076
5077 /* Even simpler default implementation, if there's really no special case to
5078 * consider. */
5079 void intel_connector_dpms(struct drm_connector *connector, int mode)
5080 {
5081 /* All the simple cases only support two dpms states. */
5082 if (mode != DRM_MODE_DPMS_ON)
5083 mode = DRM_MODE_DPMS_OFF;
5084
5085 if (mode == connector->dpms)
5086 return;
5087
5088 connector->dpms = mode;
5089
5090 /* Only need to change hw state when actually enabled */
5091 if (connector->encoder)
5092 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5093
5094 intel_modeset_check_state(connector->dev);
5095 }
5096
5097 /* Simple connector->get_hw_state implementation for encoders that support only
5098 * one connector and no cloning and hence the encoder state determines the state
5099 * of the connector. */
5100 bool intel_connector_get_hw_state(struct intel_connector *connector)
5101 {
5102 enum pipe pipe = 0;
5103 struct intel_encoder *encoder = connector->encoder;
5104
5105 return encoder->get_hw_state(encoder, &pipe);
5106 }
5107
5108 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5109 struct intel_crtc_config *pipe_config)
5110 {
5111 struct drm_i915_private *dev_priv = dev->dev_private;
5112 struct intel_crtc *pipe_B_crtc =
5113 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5114
5115 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5116 pipe_name(pipe), pipe_config->fdi_lanes);
5117 if (pipe_config->fdi_lanes > 4) {
5118 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5119 pipe_name(pipe), pipe_config->fdi_lanes);
5120 return false;
5121 }
5122
5123 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5124 if (pipe_config->fdi_lanes > 2) {
5125 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5126 pipe_config->fdi_lanes);
5127 return false;
5128 } else {
5129 return true;
5130 }
5131 }
5132
5133 if (INTEL_INFO(dev)->num_pipes == 2)
5134 return true;
5135
5136 /* Ivybridge 3 pipe is really complicated */
5137 switch (pipe) {
5138 case PIPE_A:
5139 return true;
5140 case PIPE_B:
5141 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5142 pipe_config->fdi_lanes > 2) {
5143 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5144 pipe_name(pipe), pipe_config->fdi_lanes);
5145 return false;
5146 }
5147 return true;
5148 case PIPE_C:
5149 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5150 pipe_B_crtc->config.fdi_lanes <= 2) {
5151 if (pipe_config->fdi_lanes > 2) {
5152 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5153 pipe_name(pipe), pipe_config->fdi_lanes);
5154 return false;
5155 }
5156 } else {
5157 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5158 return false;
5159 }
5160 return true;
5161 default:
5162 BUG();
5163 }
5164 }
5165
5166 #define RETRY 1
5167 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5168 struct intel_crtc_config *pipe_config)
5169 {
5170 struct drm_device *dev = intel_crtc->base.dev;
5171 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5172 int lane, link_bw, fdi_dotclock;
5173 bool setup_ok, needs_recompute = false;
5174
5175 retry:
5176 /* FDI is a binary signal running at ~2.7GHz, encoding
5177 * each output octet as 10 bits. The actual frequency
5178 * is stored as a divider into a 100MHz clock, and the
5179 * mode pixel clock is stored in units of 1KHz.
5180 * Hence the bw of each lane in terms of the mode signal
5181 * is:
5182 */
5183 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5184
5185 fdi_dotclock = adjusted_mode->crtc_clock;
5186
5187 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5188 pipe_config->pipe_bpp);
5189
5190 pipe_config->fdi_lanes = lane;
5191
5192 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5193 link_bw, &pipe_config->fdi_m_n);
5194
5195 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5196 intel_crtc->pipe, pipe_config);
5197 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5198 pipe_config->pipe_bpp -= 2*3;
5199 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5200 pipe_config->pipe_bpp);
5201 needs_recompute = true;
5202 pipe_config->bw_constrained = true;
5203
5204 goto retry;
5205 }
5206
5207 if (needs_recompute)
5208 return RETRY;
5209
5210 return setup_ok ? 0 : -EINVAL;
5211 }
5212
5213 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5214 struct intel_crtc_config *pipe_config)
5215 {
5216 pipe_config->ips_enabled = i915.enable_ips &&
5217 hsw_crtc_supports_ips(crtc) &&
5218 pipe_config->pipe_bpp <= 24;
5219 }
5220
5221 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5222 struct intel_crtc_config *pipe_config)
5223 {
5224 struct drm_device *dev = crtc->base.dev;
5225 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5226
5227 /* FIXME should check pixel clock limits on all platforms */
5228 if (INTEL_INFO(dev)->gen < 4) {
5229 struct drm_i915_private *dev_priv = dev->dev_private;
5230 int clock_limit =
5231 dev_priv->display.get_display_clock_speed(dev);
5232
5233 /*
5234 * Enable pixel doubling when the dot clock
5235 * is > 90% of the (display) core speed.
5236 *
5237 * GDG double wide on either pipe,
5238 * otherwise pipe A only.
5239 */
5240 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5241 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5242 clock_limit *= 2;
5243 pipe_config->double_wide = true;
5244 }
5245
5246 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5247 return -EINVAL;
5248 }
5249
5250 /*
5251 * Pipe horizontal size must be even in:
5252 * - DVO ganged mode
5253 * - LVDS dual channel mode
5254 * - Double wide pipe
5255 */
5256 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5257 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5258 pipe_config->pipe_src_w &= ~1;
5259
5260 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5261 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5262 */
5263 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5264 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5265 return -EINVAL;
5266
5267 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5268 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5269 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5270 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5271 * for lvds. */
5272 pipe_config->pipe_bpp = 8*3;
5273 }
5274
5275 if (HAS_IPS(dev))
5276 hsw_compute_ips_config(crtc, pipe_config);
5277
5278 /*
5279 * XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the
5280 * old clock survives for now.
5281 */
5282 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev) || HAS_DDI(dev))
5283 pipe_config->shared_dpll = crtc->config.shared_dpll;
5284
5285 if (pipe_config->has_pch_encoder)
5286 return ironlake_fdi_compute_config(crtc, pipe_config);
5287
5288 return 0;
5289 }
5290
5291 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5292 {
5293 struct drm_i915_private *dev_priv = dev->dev_private;
5294 int vco = valleyview_get_vco(dev_priv);
5295 u32 val;
5296 int divider;
5297
5298 /* FIXME: Punit isn't quite ready yet */
5299 if (IS_CHERRYVIEW(dev))
5300 return 400000;
5301
5302 mutex_lock(&dev_priv->dpio_lock);
5303 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5304 mutex_unlock(&dev_priv->dpio_lock);
5305
5306 divider = val & DISPLAY_FREQUENCY_VALUES;
5307
5308 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5309 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5310 "cdclk change in progress\n");
5311
5312 return DIV_ROUND_CLOSEST(vco << 1, divider + 1);
5313 }
5314
5315 static int i945_get_display_clock_speed(struct drm_device *dev)
5316 {
5317 return 400000;
5318 }
5319
5320 static int i915_get_display_clock_speed(struct drm_device *dev)
5321 {
5322 return 333000;
5323 }
5324
5325 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5326 {
5327 return 200000;
5328 }
5329
5330 static int pnv_get_display_clock_speed(struct drm_device *dev)
5331 {
5332 u16 gcfgc = 0;
5333
5334 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5335
5336 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5337 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5338 return 267000;
5339 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5340 return 333000;
5341 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5342 return 444000;
5343 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5344 return 200000;
5345 default:
5346 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5347 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5348 return 133000;
5349 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5350 return 167000;
5351 }
5352 }
5353
5354 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5355 {
5356 u16 gcfgc = 0;
5357
5358 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5359
5360 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5361 return 133000;
5362 else {
5363 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5364 case GC_DISPLAY_CLOCK_333_MHZ:
5365 return 333000;
5366 default:
5367 case GC_DISPLAY_CLOCK_190_200_MHZ:
5368 return 190000;
5369 }
5370 }
5371 }
5372
5373 static int i865_get_display_clock_speed(struct drm_device *dev)
5374 {
5375 return 266000;
5376 }
5377
5378 static int i855_get_display_clock_speed(struct drm_device *dev)
5379 {
5380 u16 hpllcc = 0;
5381 /* Assume that the hardware is in the high speed state. This
5382 * should be the default.
5383 */
5384 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5385 case GC_CLOCK_133_200:
5386 case GC_CLOCK_100_200:
5387 return 200000;
5388 case GC_CLOCK_166_250:
5389 return 250000;
5390 case GC_CLOCK_100_133:
5391 return 133000;
5392 }
5393
5394 /* Shouldn't happen */
5395 return 0;
5396 }
5397
5398 static int i830_get_display_clock_speed(struct drm_device *dev)
5399 {
5400 return 133000;
5401 }
5402
5403 static void
5404 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5405 {
5406 while (*num > DATA_LINK_M_N_MASK ||
5407 *den > DATA_LINK_M_N_MASK) {
5408 *num >>= 1;
5409 *den >>= 1;
5410 }
5411 }
5412
5413 static void compute_m_n(unsigned int m, unsigned int n,
5414 uint32_t *ret_m, uint32_t *ret_n)
5415 {
5416 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5417 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5418 intel_reduce_m_n_ratio(ret_m, ret_n);
5419 }
5420
5421 void
5422 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5423 int pixel_clock, int link_clock,
5424 struct intel_link_m_n *m_n)
5425 {
5426 m_n->tu = 64;
5427
5428 compute_m_n(bits_per_pixel * pixel_clock,
5429 link_clock * nlanes * 8,
5430 &m_n->gmch_m, &m_n->gmch_n);
5431
5432 compute_m_n(pixel_clock, link_clock,
5433 &m_n->link_m, &m_n->link_n);
5434 }
5435
5436 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5437 {
5438 if (i915.panel_use_ssc >= 0)
5439 return i915.panel_use_ssc != 0;
5440 return dev_priv->vbt.lvds_use_ssc
5441 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5442 }
5443
5444 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5445 {
5446 struct drm_device *dev = crtc->dev;
5447 struct drm_i915_private *dev_priv = dev->dev_private;
5448 int refclk;
5449
5450 if (IS_VALLEYVIEW(dev)) {
5451 refclk = 100000;
5452 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5453 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5454 refclk = dev_priv->vbt.lvds_ssc_freq;
5455 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5456 } else if (!IS_GEN2(dev)) {
5457 refclk = 96000;
5458 } else {
5459 refclk = 48000;
5460 }
5461
5462 return refclk;
5463 }
5464
5465 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5466 {
5467 return (1 << dpll->n) << 16 | dpll->m2;
5468 }
5469
5470 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5471 {
5472 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5473 }
5474
5475 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5476 intel_clock_t *reduced_clock)
5477 {
5478 struct drm_device *dev = crtc->base.dev;
5479 u32 fp, fp2 = 0;
5480
5481 if (IS_PINEVIEW(dev)) {
5482 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5483 if (reduced_clock)
5484 fp2 = pnv_dpll_compute_fp(reduced_clock);
5485 } else {
5486 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5487 if (reduced_clock)
5488 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5489 }
5490
5491 crtc->config.dpll_hw_state.fp0 = fp;
5492
5493 crtc->lowfreq_avail = false;
5494 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5495 reduced_clock && i915.powersave) {
5496 crtc->config.dpll_hw_state.fp1 = fp2;
5497 crtc->lowfreq_avail = true;
5498 } else {
5499 crtc->config.dpll_hw_state.fp1 = fp;
5500 }
5501 }
5502
5503 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5504 pipe)
5505 {
5506 u32 reg_val;
5507
5508 /*
5509 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5510 * and set it to a reasonable value instead.
5511 */
5512 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5513 reg_val &= 0xffffff00;
5514 reg_val |= 0x00000030;
5515 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5516
5517 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5518 reg_val &= 0x8cffffff;
5519 reg_val = 0x8c000000;
5520 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5521
5522 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5523 reg_val &= 0xffffff00;
5524 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5525
5526 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5527 reg_val &= 0x00ffffff;
5528 reg_val |= 0xb0000000;
5529 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5530 }
5531
5532 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5533 struct intel_link_m_n *m_n)
5534 {
5535 struct drm_device *dev = crtc->base.dev;
5536 struct drm_i915_private *dev_priv = dev->dev_private;
5537 int pipe = crtc->pipe;
5538
5539 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5540 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5541 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5542 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5543 }
5544
5545 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5546 struct intel_link_m_n *m_n,
5547 struct intel_link_m_n *m2_n2)
5548 {
5549 struct drm_device *dev = crtc->base.dev;
5550 struct drm_i915_private *dev_priv = dev->dev_private;
5551 int pipe = crtc->pipe;
5552 enum transcoder transcoder = crtc->config.cpu_transcoder;
5553
5554 if (INTEL_INFO(dev)->gen >= 5) {
5555 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5556 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5557 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5558 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5559 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5560 * for gen < 8) and if DRRS is supported (to make sure the
5561 * registers are not unnecessarily accessed).
5562 */
5563 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5564 crtc->config.has_drrs) {
5565 I915_WRITE(PIPE_DATA_M2(transcoder),
5566 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5567 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5568 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5569 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5570 }
5571 } else {
5572 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5573 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5574 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5575 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5576 }
5577 }
5578
5579 void intel_dp_set_m_n(struct intel_crtc *crtc)
5580 {
5581 if (crtc->config.has_pch_encoder)
5582 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5583 else
5584 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n,
5585 &crtc->config.dp_m2_n2);
5586 }
5587
5588 static void vlv_update_pll(struct intel_crtc *crtc)
5589 {
5590 u32 dpll, dpll_md;
5591
5592 /*
5593 * Enable DPIO clock input. We should never disable the reference
5594 * clock for pipe B, since VGA hotplug / manual detection depends
5595 * on it.
5596 */
5597 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5598 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5599 /* We should never disable this, set it here for state tracking */
5600 if (crtc->pipe == PIPE_B)
5601 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5602 dpll |= DPLL_VCO_ENABLE;
5603 crtc->config.dpll_hw_state.dpll = dpll;
5604
5605 dpll_md = (crtc->config.pixel_multiplier - 1)
5606 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5607 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5608 }
5609
5610 static void vlv_prepare_pll(struct intel_crtc *crtc)
5611 {
5612 struct drm_device *dev = crtc->base.dev;
5613 struct drm_i915_private *dev_priv = dev->dev_private;
5614 int pipe = crtc->pipe;
5615 u32 mdiv;
5616 u32 bestn, bestm1, bestm2, bestp1, bestp2;
5617 u32 coreclk, reg_val;
5618
5619 mutex_lock(&dev_priv->dpio_lock);
5620
5621 bestn = crtc->config.dpll.n;
5622 bestm1 = crtc->config.dpll.m1;
5623 bestm2 = crtc->config.dpll.m2;
5624 bestp1 = crtc->config.dpll.p1;
5625 bestp2 = crtc->config.dpll.p2;
5626
5627 /* See eDP HDMI DPIO driver vbios notes doc */
5628
5629 /* PLL B needs special handling */
5630 if (pipe == PIPE_B)
5631 vlv_pllb_recal_opamp(dev_priv, pipe);
5632
5633 /* Set up Tx target for periodic Rcomp update */
5634 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5635
5636 /* Disable target IRef on PLL */
5637 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5638 reg_val &= 0x00ffffff;
5639 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5640
5641 /* Disable fast lock */
5642 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5643
5644 /* Set idtafcrecal before PLL is enabled */
5645 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5646 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5647 mdiv |= ((bestn << DPIO_N_SHIFT));
5648 mdiv |= (1 << DPIO_K_SHIFT);
5649
5650 /*
5651 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5652 * but we don't support that).
5653 * Note: don't use the DAC post divider as it seems unstable.
5654 */
5655 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5656 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5657
5658 mdiv |= DPIO_ENABLE_CALIBRATION;
5659 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5660
5661 /* Set HBR and RBR LPF coefficients */
5662 if (crtc->config.port_clock == 162000 ||
5663 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5664 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5665 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5666 0x009f0003);
5667 else
5668 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5669 0x00d0000f);
5670
5671 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5672 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5673 /* Use SSC source */
5674 if (pipe == PIPE_A)
5675 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5676 0x0df40000);
5677 else
5678 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5679 0x0df70000);
5680 } else { /* HDMI or VGA */
5681 /* Use bend source */
5682 if (pipe == PIPE_A)
5683 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5684 0x0df70000);
5685 else
5686 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5687 0x0df40000);
5688 }
5689
5690 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5691 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5692 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5693 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5694 coreclk |= 0x01000000;
5695 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5696
5697 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5698 mutex_unlock(&dev_priv->dpio_lock);
5699 }
5700
5701 static void chv_update_pll(struct intel_crtc *crtc)
5702 {
5703 crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5704 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5705 DPLL_VCO_ENABLE;
5706 if (crtc->pipe != PIPE_A)
5707 crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5708
5709 crtc->config.dpll_hw_state.dpll_md =
5710 (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5711 }
5712
5713 static void chv_prepare_pll(struct intel_crtc *crtc)
5714 {
5715 struct drm_device *dev = crtc->base.dev;
5716 struct drm_i915_private *dev_priv = dev->dev_private;
5717 int pipe = crtc->pipe;
5718 int dpll_reg = DPLL(crtc->pipe);
5719 enum dpio_channel port = vlv_pipe_to_channel(pipe);
5720 u32 loopfilter, intcoeff;
5721 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5722 int refclk;
5723
5724 bestn = crtc->config.dpll.n;
5725 bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5726 bestm1 = crtc->config.dpll.m1;
5727 bestm2 = crtc->config.dpll.m2 >> 22;
5728 bestp1 = crtc->config.dpll.p1;
5729 bestp2 = crtc->config.dpll.p2;
5730
5731 /*
5732 * Enable Refclk and SSC
5733 */
5734 I915_WRITE(dpll_reg,
5735 crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5736
5737 mutex_lock(&dev_priv->dpio_lock);
5738
5739 /* p1 and p2 divider */
5740 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5741 5 << DPIO_CHV_S1_DIV_SHIFT |
5742 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5743 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5744 1 << DPIO_CHV_K_DIV_SHIFT);
5745
5746 /* Feedback post-divider - m2 */
5747 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5748
5749 /* Feedback refclk divider - n and m1 */
5750 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5751 DPIO_CHV_M1_DIV_BY_2 |
5752 1 << DPIO_CHV_N_DIV_SHIFT);
5753
5754 /* M2 fraction division */
5755 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5756
5757 /* M2 fraction division enable */
5758 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5759 DPIO_CHV_FRAC_DIV_EN |
5760 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5761
5762 /* Loop filter */
5763 refclk = i9xx_get_refclk(&crtc->base, 0);
5764 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5765 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5766 if (refclk == 100000)
5767 intcoeff = 11;
5768 else if (refclk == 38400)
5769 intcoeff = 10;
5770 else
5771 intcoeff = 9;
5772 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5773 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5774
5775 /* AFC Recal */
5776 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5777 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5778 DPIO_AFC_RECAL);
5779
5780 mutex_unlock(&dev_priv->dpio_lock);
5781 }
5782
5783 static void i9xx_update_pll(struct intel_crtc *crtc,
5784 intel_clock_t *reduced_clock,
5785 int num_connectors)
5786 {
5787 struct drm_device *dev = crtc->base.dev;
5788 struct drm_i915_private *dev_priv = dev->dev_private;
5789 u32 dpll;
5790 bool is_sdvo;
5791 struct dpll *clock = &crtc->config.dpll;
5792
5793 i9xx_update_pll_dividers(crtc, reduced_clock);
5794
5795 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5796 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5797
5798 dpll = DPLL_VGA_MODE_DIS;
5799
5800 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5801 dpll |= DPLLB_MODE_LVDS;
5802 else
5803 dpll |= DPLLB_MODE_DAC_SERIAL;
5804
5805 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5806 dpll |= (crtc->config.pixel_multiplier - 1)
5807 << SDVO_MULTIPLIER_SHIFT_HIRES;
5808 }
5809
5810 if (is_sdvo)
5811 dpll |= DPLL_SDVO_HIGH_SPEED;
5812
5813 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5814 dpll |= DPLL_SDVO_HIGH_SPEED;
5815
5816 /* compute bitmask from p1 value */
5817 if (IS_PINEVIEW(dev))
5818 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5819 else {
5820 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5821 if (IS_G4X(dev) && reduced_clock)
5822 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5823 }
5824 switch (clock->p2) {
5825 case 5:
5826 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5827 break;
5828 case 7:
5829 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5830 break;
5831 case 10:
5832 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5833 break;
5834 case 14:
5835 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5836 break;
5837 }
5838 if (INTEL_INFO(dev)->gen >= 4)
5839 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5840
5841 if (crtc->config.sdvo_tv_clock)
5842 dpll |= PLL_REF_INPUT_TVCLKINBC;
5843 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5844 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5845 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5846 else
5847 dpll |= PLL_REF_INPUT_DREFCLK;
5848
5849 dpll |= DPLL_VCO_ENABLE;
5850 crtc->config.dpll_hw_state.dpll = dpll;
5851
5852 if (INTEL_INFO(dev)->gen >= 4) {
5853 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5854 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5855 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5856 }
5857 }
5858
5859 static void i8xx_update_pll(struct intel_crtc *crtc,
5860 intel_clock_t *reduced_clock,
5861 int num_connectors)
5862 {
5863 struct drm_device *dev = crtc->base.dev;
5864 struct drm_i915_private *dev_priv = dev->dev_private;
5865 u32 dpll;
5866 struct dpll *clock = &crtc->config.dpll;
5867
5868 i9xx_update_pll_dividers(crtc, reduced_clock);
5869
5870 dpll = DPLL_VGA_MODE_DIS;
5871
5872 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5873 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5874 } else {
5875 if (clock->p1 == 2)
5876 dpll |= PLL_P1_DIVIDE_BY_TWO;
5877 else
5878 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5879 if (clock->p2 == 4)
5880 dpll |= PLL_P2_DIVIDE_BY_4;
5881 }
5882
5883 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5884 dpll |= DPLL_DVO_2X_MODE;
5885
5886 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5887 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5888 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5889 else
5890 dpll |= PLL_REF_INPUT_DREFCLK;
5891
5892 dpll |= DPLL_VCO_ENABLE;
5893 crtc->config.dpll_hw_state.dpll = dpll;
5894 }
5895
5896 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5897 {
5898 struct drm_device *dev = intel_crtc->base.dev;
5899 struct drm_i915_private *dev_priv = dev->dev_private;
5900 enum pipe pipe = intel_crtc->pipe;
5901 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5902 struct drm_display_mode *adjusted_mode =
5903 &intel_crtc->config.adjusted_mode;
5904 uint32_t crtc_vtotal, crtc_vblank_end;
5905 int vsyncshift = 0;
5906
5907 /* We need to be careful not to changed the adjusted mode, for otherwise
5908 * the hw state checker will get angry at the mismatch. */
5909 crtc_vtotal = adjusted_mode->crtc_vtotal;
5910 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5911
5912 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5913 /* the chip adds 2 halflines automatically */
5914 crtc_vtotal -= 1;
5915 crtc_vblank_end -= 1;
5916
5917 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5918 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5919 else
5920 vsyncshift = adjusted_mode->crtc_hsync_start -
5921 adjusted_mode->crtc_htotal / 2;
5922 if (vsyncshift < 0)
5923 vsyncshift += adjusted_mode->crtc_htotal;
5924 }
5925
5926 if (INTEL_INFO(dev)->gen > 3)
5927 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5928
5929 I915_WRITE(HTOTAL(cpu_transcoder),
5930 (adjusted_mode->crtc_hdisplay - 1) |
5931 ((adjusted_mode->crtc_htotal - 1) << 16));
5932 I915_WRITE(HBLANK(cpu_transcoder),
5933 (adjusted_mode->crtc_hblank_start - 1) |
5934 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5935 I915_WRITE(HSYNC(cpu_transcoder),
5936 (adjusted_mode->crtc_hsync_start - 1) |
5937 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5938
5939 I915_WRITE(VTOTAL(cpu_transcoder),
5940 (adjusted_mode->crtc_vdisplay - 1) |
5941 ((crtc_vtotal - 1) << 16));
5942 I915_WRITE(VBLANK(cpu_transcoder),
5943 (adjusted_mode->crtc_vblank_start - 1) |
5944 ((crtc_vblank_end - 1) << 16));
5945 I915_WRITE(VSYNC(cpu_transcoder),
5946 (adjusted_mode->crtc_vsync_start - 1) |
5947 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5948
5949 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5950 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5951 * documented on the DDI_FUNC_CTL register description, EDP Input Select
5952 * bits. */
5953 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5954 (pipe == PIPE_B || pipe == PIPE_C))
5955 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5956
5957 /* pipesrc controls the size that is scaled from, which should
5958 * always be the user's requested size.
5959 */
5960 I915_WRITE(PIPESRC(pipe),
5961 ((intel_crtc->config.pipe_src_w - 1) << 16) |
5962 (intel_crtc->config.pipe_src_h - 1));
5963 }
5964
5965 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5966 struct intel_crtc_config *pipe_config)
5967 {
5968 struct drm_device *dev = crtc->base.dev;
5969 struct drm_i915_private *dev_priv = dev->dev_private;
5970 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5971 uint32_t tmp;
5972
5973 tmp = I915_READ(HTOTAL(cpu_transcoder));
5974 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5975 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5976 tmp = I915_READ(HBLANK(cpu_transcoder));
5977 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5978 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5979 tmp = I915_READ(HSYNC(cpu_transcoder));
5980 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5981 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5982
5983 tmp = I915_READ(VTOTAL(cpu_transcoder));
5984 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5985 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5986 tmp = I915_READ(VBLANK(cpu_transcoder));
5987 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5988 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5989 tmp = I915_READ(VSYNC(cpu_transcoder));
5990 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5991 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5992
5993 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5994 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5995 pipe_config->adjusted_mode.crtc_vtotal += 1;
5996 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5997 }
5998
5999 tmp = I915_READ(PIPESRC(crtc->pipe));
6000 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6001 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6002
6003 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
6004 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
6005 }
6006
6007 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6008 struct intel_crtc_config *pipe_config)
6009 {
6010 mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
6011 mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
6012 mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
6013 mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
6014
6015 mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
6016 mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
6017 mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
6018 mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
6019
6020 mode->flags = pipe_config->adjusted_mode.flags;
6021
6022 mode->clock = pipe_config->adjusted_mode.crtc_clock;
6023 mode->flags |= pipe_config->adjusted_mode.flags;
6024 }
6025
6026 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6027 {
6028 struct drm_device *dev = intel_crtc->base.dev;
6029 struct drm_i915_private *dev_priv = dev->dev_private;
6030 uint32_t pipeconf;
6031
6032 pipeconf = 0;
6033
6034 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
6035 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
6036 pipeconf |= PIPECONF_ENABLE;
6037
6038 if (intel_crtc->config.double_wide)
6039 pipeconf |= PIPECONF_DOUBLE_WIDE;
6040
6041 /* only g4x and later have fancy bpc/dither controls */
6042 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6043 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6044 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
6045 pipeconf |= PIPECONF_DITHER_EN |
6046 PIPECONF_DITHER_TYPE_SP;
6047
6048 switch (intel_crtc->config.pipe_bpp) {
6049 case 18:
6050 pipeconf |= PIPECONF_6BPC;
6051 break;
6052 case 24:
6053 pipeconf |= PIPECONF_8BPC;
6054 break;
6055 case 30:
6056 pipeconf |= PIPECONF_10BPC;
6057 break;
6058 default:
6059 /* Case prevented by intel_choose_pipe_bpp_dither. */
6060 BUG();
6061 }
6062 }
6063
6064 if (HAS_PIPE_CXSR(dev)) {
6065 if (intel_crtc->lowfreq_avail) {
6066 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6067 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6068 } else {
6069 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6070 }
6071 }
6072
6073 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6074 if (INTEL_INFO(dev)->gen < 4 ||
6075 intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
6076 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6077 else
6078 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6079 } else
6080 pipeconf |= PIPECONF_PROGRESSIVE;
6081
6082 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6083 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6084
6085 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6086 POSTING_READ(PIPECONF(intel_crtc->pipe));
6087 }
6088
6089 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
6090 int x, int y,
6091 struct drm_framebuffer *fb)
6092 {
6093 struct drm_device *dev = crtc->dev;
6094 struct drm_i915_private *dev_priv = dev->dev_private;
6095 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6096 int refclk, num_connectors = 0;
6097 intel_clock_t clock, reduced_clock;
6098 bool ok, has_reduced_clock = false;
6099 bool is_lvds = false, is_dsi = false;
6100 struct intel_encoder *encoder;
6101 const intel_limit_t *limit;
6102
6103 for_each_encoder_on_crtc(dev, crtc, encoder) {
6104 switch (encoder->type) {
6105 case INTEL_OUTPUT_LVDS:
6106 is_lvds = true;
6107 break;
6108 case INTEL_OUTPUT_DSI:
6109 is_dsi = true;
6110 break;
6111 }
6112
6113 num_connectors++;
6114 }
6115
6116 if (is_dsi)
6117 return 0;
6118
6119 if (!intel_crtc->config.clock_set) {
6120 refclk = i9xx_get_refclk(crtc, num_connectors);
6121
6122 /*
6123 * Returns a set of divisors for the desired target clock with
6124 * the given refclk, or FALSE. The returned values represent
6125 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6126 * 2) / p1 / p2.
6127 */
6128 limit = intel_limit(crtc, refclk);
6129 ok = dev_priv->display.find_dpll(limit, crtc,
6130 intel_crtc->config.port_clock,
6131 refclk, NULL, &clock);
6132 if (!ok) {
6133 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6134 return -EINVAL;
6135 }
6136
6137 if (is_lvds && dev_priv->lvds_downclock_avail) {
6138 /*
6139 * Ensure we match the reduced clock's P to the target
6140 * clock. If the clocks don't match, we can't switch
6141 * the display clock by using the FP0/FP1. In such case
6142 * we will disable the LVDS downclock feature.
6143 */
6144 has_reduced_clock =
6145 dev_priv->display.find_dpll(limit, crtc,
6146 dev_priv->lvds_downclock,
6147 refclk, &clock,
6148 &reduced_clock);
6149 }
6150 /* Compat-code for transition, will disappear. */
6151 intel_crtc->config.dpll.n = clock.n;
6152 intel_crtc->config.dpll.m1 = clock.m1;
6153 intel_crtc->config.dpll.m2 = clock.m2;
6154 intel_crtc->config.dpll.p1 = clock.p1;
6155 intel_crtc->config.dpll.p2 = clock.p2;
6156 }
6157
6158 if (IS_GEN2(dev)) {
6159 i8xx_update_pll(intel_crtc,
6160 has_reduced_clock ? &reduced_clock : NULL,
6161 num_connectors);
6162 } else if (IS_CHERRYVIEW(dev)) {
6163 chv_update_pll(intel_crtc);
6164 } else if (IS_VALLEYVIEW(dev)) {
6165 vlv_update_pll(intel_crtc);
6166 } else {
6167 i9xx_update_pll(intel_crtc,
6168 has_reduced_clock ? &reduced_clock : NULL,
6169 num_connectors);
6170 }
6171
6172 return 0;
6173 }
6174
6175 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6176 struct intel_crtc_config *pipe_config)
6177 {
6178 struct drm_device *dev = crtc->base.dev;
6179 struct drm_i915_private *dev_priv = dev->dev_private;
6180 uint32_t tmp;
6181
6182 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6183 return;
6184
6185 tmp = I915_READ(PFIT_CONTROL);
6186 if (!(tmp & PFIT_ENABLE))
6187 return;
6188
6189 /* Check whether the pfit is attached to our pipe. */
6190 if (INTEL_INFO(dev)->gen < 4) {
6191 if (crtc->pipe != PIPE_B)
6192 return;
6193 } else {
6194 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6195 return;
6196 }
6197
6198 pipe_config->gmch_pfit.control = tmp;
6199 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6200 if (INTEL_INFO(dev)->gen < 5)
6201 pipe_config->gmch_pfit.lvds_border_bits =
6202 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6203 }
6204
6205 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6206 struct intel_crtc_config *pipe_config)
6207 {
6208 struct drm_device *dev = crtc->base.dev;
6209 struct drm_i915_private *dev_priv = dev->dev_private;
6210 int pipe = pipe_config->cpu_transcoder;
6211 intel_clock_t clock;
6212 u32 mdiv;
6213 int refclk = 100000;
6214
6215 /* In case of MIPI DPLL will not even be used */
6216 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6217 return;
6218
6219 mutex_lock(&dev_priv->dpio_lock);
6220 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6221 mutex_unlock(&dev_priv->dpio_lock);
6222
6223 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6224 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6225 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6226 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6227 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6228
6229 vlv_clock(refclk, &clock);
6230
6231 /* clock.dot is the fast clock */
6232 pipe_config->port_clock = clock.dot / 5;
6233 }
6234
6235 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6236 struct intel_plane_config *plane_config)
6237 {
6238 struct drm_device *dev = crtc->base.dev;
6239 struct drm_i915_private *dev_priv = dev->dev_private;
6240 u32 val, base, offset;
6241 int pipe = crtc->pipe, plane = crtc->plane;
6242 int fourcc, pixel_format;
6243 int aligned_height;
6244
6245 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6246 if (!crtc->base.primary->fb) {
6247 DRM_DEBUG_KMS("failed to alloc fb\n");
6248 return;
6249 }
6250
6251 val = I915_READ(DSPCNTR(plane));
6252
6253 if (INTEL_INFO(dev)->gen >= 4)
6254 if (val & DISPPLANE_TILED)
6255 plane_config->tiled = true;
6256
6257 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6258 fourcc = intel_format_to_fourcc(pixel_format);
6259 crtc->base.primary->fb->pixel_format = fourcc;
6260 crtc->base.primary->fb->bits_per_pixel =
6261 drm_format_plane_cpp(fourcc, 0) * 8;
6262
6263 if (INTEL_INFO(dev)->gen >= 4) {
6264 if (plane_config->tiled)
6265 offset = I915_READ(DSPTILEOFF(plane));
6266 else
6267 offset = I915_READ(DSPLINOFF(plane));
6268 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6269 } else {
6270 base = I915_READ(DSPADDR(plane));
6271 }
6272 plane_config->base = base;
6273
6274 val = I915_READ(PIPESRC(pipe));
6275 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6276 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6277
6278 val = I915_READ(DSPSTRIDE(pipe));
6279 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
6280
6281 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6282 plane_config->tiled);
6283
6284 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6285 aligned_height);
6286
6287 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6288 pipe, plane, crtc->base.primary->fb->width,
6289 crtc->base.primary->fb->height,
6290 crtc->base.primary->fb->bits_per_pixel, base,
6291 crtc->base.primary->fb->pitches[0],
6292 plane_config->size);
6293
6294 }
6295
6296 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6297 struct intel_crtc_config *pipe_config)
6298 {
6299 struct drm_device *dev = crtc->base.dev;
6300 struct drm_i915_private *dev_priv = dev->dev_private;
6301 int pipe = pipe_config->cpu_transcoder;
6302 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6303 intel_clock_t clock;
6304 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6305 int refclk = 100000;
6306
6307 mutex_lock(&dev_priv->dpio_lock);
6308 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6309 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6310 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6311 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6312 mutex_unlock(&dev_priv->dpio_lock);
6313
6314 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6315 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6316 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6317 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6318 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6319
6320 chv_clock(refclk, &clock);
6321
6322 /* clock.dot is the fast clock */
6323 pipe_config->port_clock = clock.dot / 5;
6324 }
6325
6326 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6327 struct intel_crtc_config *pipe_config)
6328 {
6329 struct drm_device *dev = crtc->base.dev;
6330 struct drm_i915_private *dev_priv = dev->dev_private;
6331 uint32_t tmp;
6332
6333 if (!intel_display_power_enabled(dev_priv,
6334 POWER_DOMAIN_PIPE(crtc->pipe)))
6335 return false;
6336
6337 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6338 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6339
6340 tmp = I915_READ(PIPECONF(crtc->pipe));
6341 if (!(tmp & PIPECONF_ENABLE))
6342 return false;
6343
6344 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6345 switch (tmp & PIPECONF_BPC_MASK) {
6346 case PIPECONF_6BPC:
6347 pipe_config->pipe_bpp = 18;
6348 break;
6349 case PIPECONF_8BPC:
6350 pipe_config->pipe_bpp = 24;
6351 break;
6352 case PIPECONF_10BPC:
6353 pipe_config->pipe_bpp = 30;
6354 break;
6355 default:
6356 break;
6357 }
6358 }
6359
6360 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6361 pipe_config->limited_color_range = true;
6362
6363 if (INTEL_INFO(dev)->gen < 4)
6364 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6365
6366 intel_get_pipe_timings(crtc, pipe_config);
6367
6368 i9xx_get_pfit_config(crtc, pipe_config);
6369
6370 if (INTEL_INFO(dev)->gen >= 4) {
6371 tmp = I915_READ(DPLL_MD(crtc->pipe));
6372 pipe_config->pixel_multiplier =
6373 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6374 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6375 pipe_config->dpll_hw_state.dpll_md = tmp;
6376 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6377 tmp = I915_READ(DPLL(crtc->pipe));
6378 pipe_config->pixel_multiplier =
6379 ((tmp & SDVO_MULTIPLIER_MASK)
6380 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6381 } else {
6382 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6383 * port and will be fixed up in the encoder->get_config
6384 * function. */
6385 pipe_config->pixel_multiplier = 1;
6386 }
6387 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6388 if (!IS_VALLEYVIEW(dev)) {
6389 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6390 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6391 } else {
6392 /* Mask out read-only status bits. */
6393 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6394 DPLL_PORTC_READY_MASK |
6395 DPLL_PORTB_READY_MASK);
6396 }
6397
6398 if (IS_CHERRYVIEW(dev))
6399 chv_crtc_clock_get(crtc, pipe_config);
6400 else if (IS_VALLEYVIEW(dev))
6401 vlv_crtc_clock_get(crtc, pipe_config);
6402 else
6403 i9xx_crtc_clock_get(crtc, pipe_config);
6404
6405 return true;
6406 }
6407
6408 static void ironlake_init_pch_refclk(struct drm_device *dev)
6409 {
6410 struct drm_i915_private *dev_priv = dev->dev_private;
6411 struct intel_encoder *encoder;
6412 u32 val, final;
6413 bool has_lvds = false;
6414 bool has_cpu_edp = false;
6415 bool has_panel = false;
6416 bool has_ck505 = false;
6417 bool can_ssc = false;
6418
6419 /* We need to take the global config into account */
6420 for_each_intel_encoder(dev, encoder) {
6421 switch (encoder->type) {
6422 case INTEL_OUTPUT_LVDS:
6423 has_panel = true;
6424 has_lvds = true;
6425 break;
6426 case INTEL_OUTPUT_EDP:
6427 has_panel = true;
6428 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6429 has_cpu_edp = true;
6430 break;
6431 }
6432 }
6433
6434 if (HAS_PCH_IBX(dev)) {
6435 has_ck505 = dev_priv->vbt.display_clock_mode;
6436 can_ssc = has_ck505;
6437 } else {
6438 has_ck505 = false;
6439 can_ssc = true;
6440 }
6441
6442 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6443 has_panel, has_lvds, has_ck505);
6444
6445 /* Ironlake: try to setup display ref clock before DPLL
6446 * enabling. This is only under driver's control after
6447 * PCH B stepping, previous chipset stepping should be
6448 * ignoring this setting.
6449 */
6450 val = I915_READ(PCH_DREF_CONTROL);
6451
6452 /* As we must carefully and slowly disable/enable each source in turn,
6453 * compute the final state we want first and check if we need to
6454 * make any changes at all.
6455 */
6456 final = val;
6457 final &= ~DREF_NONSPREAD_SOURCE_MASK;
6458 if (has_ck505)
6459 final |= DREF_NONSPREAD_CK505_ENABLE;
6460 else
6461 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6462
6463 final &= ~DREF_SSC_SOURCE_MASK;
6464 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6465 final &= ~DREF_SSC1_ENABLE;
6466
6467 if (has_panel) {
6468 final |= DREF_SSC_SOURCE_ENABLE;
6469
6470 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6471 final |= DREF_SSC1_ENABLE;
6472
6473 if (has_cpu_edp) {
6474 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6475 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6476 else
6477 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6478 } else
6479 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6480 } else {
6481 final |= DREF_SSC_SOURCE_DISABLE;
6482 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6483 }
6484
6485 if (final == val)
6486 return;
6487
6488 /* Always enable nonspread source */
6489 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6490
6491 if (has_ck505)
6492 val |= DREF_NONSPREAD_CK505_ENABLE;
6493 else
6494 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6495
6496 if (has_panel) {
6497 val &= ~DREF_SSC_SOURCE_MASK;
6498 val |= DREF_SSC_SOURCE_ENABLE;
6499
6500 /* SSC must be turned on before enabling the CPU output */
6501 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6502 DRM_DEBUG_KMS("Using SSC on panel\n");
6503 val |= DREF_SSC1_ENABLE;
6504 } else
6505 val &= ~DREF_SSC1_ENABLE;
6506
6507 /* Get SSC going before enabling the outputs */
6508 I915_WRITE(PCH_DREF_CONTROL, val);
6509 POSTING_READ(PCH_DREF_CONTROL);
6510 udelay(200);
6511
6512 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6513
6514 /* Enable CPU source on CPU attached eDP */
6515 if (has_cpu_edp) {
6516 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6517 DRM_DEBUG_KMS("Using SSC on eDP\n");
6518 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6519 } else
6520 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6521 } else
6522 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6523
6524 I915_WRITE(PCH_DREF_CONTROL, val);
6525 POSTING_READ(PCH_DREF_CONTROL);
6526 udelay(200);
6527 } else {
6528 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6529
6530 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6531
6532 /* Turn off CPU output */
6533 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6534
6535 I915_WRITE(PCH_DREF_CONTROL, val);
6536 POSTING_READ(PCH_DREF_CONTROL);
6537 udelay(200);
6538
6539 /* Turn off the SSC source */
6540 val &= ~DREF_SSC_SOURCE_MASK;
6541 val |= DREF_SSC_SOURCE_DISABLE;
6542
6543 /* Turn off SSC1 */
6544 val &= ~DREF_SSC1_ENABLE;
6545
6546 I915_WRITE(PCH_DREF_CONTROL, val);
6547 POSTING_READ(PCH_DREF_CONTROL);
6548 udelay(200);
6549 }
6550
6551 BUG_ON(val != final);
6552 }
6553
6554 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6555 {
6556 uint32_t tmp;
6557
6558 tmp = I915_READ(SOUTH_CHICKEN2);
6559 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6560 I915_WRITE(SOUTH_CHICKEN2, tmp);
6561
6562 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6563 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6564 DRM_ERROR("FDI mPHY reset assert timeout\n");
6565
6566 tmp = I915_READ(SOUTH_CHICKEN2);
6567 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6568 I915_WRITE(SOUTH_CHICKEN2, tmp);
6569
6570 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6571 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6572 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6573 }
6574
6575 /* WaMPhyProgramming:hsw */
6576 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6577 {
6578 uint32_t tmp;
6579
6580 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6581 tmp &= ~(0xFF << 24);
6582 tmp |= (0x12 << 24);
6583 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6584
6585 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6586 tmp |= (1 << 11);
6587 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6588
6589 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6590 tmp |= (1 << 11);
6591 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6592
6593 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6594 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6595 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6596
6597 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6598 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6599 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6600
6601 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6602 tmp &= ~(7 << 13);
6603 tmp |= (5 << 13);
6604 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6605
6606 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6607 tmp &= ~(7 << 13);
6608 tmp |= (5 << 13);
6609 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6610
6611 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6612 tmp &= ~0xFF;
6613 tmp |= 0x1C;
6614 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6615
6616 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6617 tmp &= ~0xFF;
6618 tmp |= 0x1C;
6619 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6620
6621 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6622 tmp &= ~(0xFF << 16);
6623 tmp |= (0x1C << 16);
6624 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6625
6626 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6627 tmp &= ~(0xFF << 16);
6628 tmp |= (0x1C << 16);
6629 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6630
6631 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6632 tmp |= (1 << 27);
6633 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6634
6635 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6636 tmp |= (1 << 27);
6637 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6638
6639 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6640 tmp &= ~(0xF << 28);
6641 tmp |= (4 << 28);
6642 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6643
6644 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6645 tmp &= ~(0xF << 28);
6646 tmp |= (4 << 28);
6647 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6648 }
6649
6650 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6651 * Programming" based on the parameters passed:
6652 * - Sequence to enable CLKOUT_DP
6653 * - Sequence to enable CLKOUT_DP without spread
6654 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6655 */
6656 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6657 bool with_fdi)
6658 {
6659 struct drm_i915_private *dev_priv = dev->dev_private;
6660 uint32_t reg, tmp;
6661
6662 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6663 with_spread = true;
6664 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6665 with_fdi, "LP PCH doesn't have FDI\n"))
6666 with_fdi = false;
6667
6668 mutex_lock(&dev_priv->dpio_lock);
6669
6670 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6671 tmp &= ~SBI_SSCCTL_DISABLE;
6672 tmp |= SBI_SSCCTL_PATHALT;
6673 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6674
6675 udelay(24);
6676
6677 if (with_spread) {
6678 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6679 tmp &= ~SBI_SSCCTL_PATHALT;
6680 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6681
6682 if (with_fdi) {
6683 lpt_reset_fdi_mphy(dev_priv);
6684 lpt_program_fdi_mphy(dev_priv);
6685 }
6686 }
6687
6688 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6689 SBI_GEN0 : SBI_DBUFF0;
6690 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6691 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6692 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6693
6694 mutex_unlock(&dev_priv->dpio_lock);
6695 }
6696
6697 /* Sequence to disable CLKOUT_DP */
6698 static void lpt_disable_clkout_dp(struct drm_device *dev)
6699 {
6700 struct drm_i915_private *dev_priv = dev->dev_private;
6701 uint32_t reg, tmp;
6702
6703 mutex_lock(&dev_priv->dpio_lock);
6704
6705 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6706 SBI_GEN0 : SBI_DBUFF0;
6707 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6708 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6709 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6710
6711 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6712 if (!(tmp & SBI_SSCCTL_DISABLE)) {
6713 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6714 tmp |= SBI_SSCCTL_PATHALT;
6715 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6716 udelay(32);
6717 }
6718 tmp |= SBI_SSCCTL_DISABLE;
6719 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6720 }
6721
6722 mutex_unlock(&dev_priv->dpio_lock);
6723 }
6724
6725 static void lpt_init_pch_refclk(struct drm_device *dev)
6726 {
6727 struct intel_encoder *encoder;
6728 bool has_vga = false;
6729
6730 for_each_intel_encoder(dev, encoder) {
6731 switch (encoder->type) {
6732 case INTEL_OUTPUT_ANALOG:
6733 has_vga = true;
6734 break;
6735 }
6736 }
6737
6738 if (has_vga)
6739 lpt_enable_clkout_dp(dev, true, true);
6740 else
6741 lpt_disable_clkout_dp(dev);
6742 }
6743
6744 /*
6745 * Initialize reference clocks when the driver loads
6746 */
6747 void intel_init_pch_refclk(struct drm_device *dev)
6748 {
6749 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6750 ironlake_init_pch_refclk(dev);
6751 else if (HAS_PCH_LPT(dev))
6752 lpt_init_pch_refclk(dev);
6753 }
6754
6755 static int ironlake_get_refclk(struct drm_crtc *crtc)
6756 {
6757 struct drm_device *dev = crtc->dev;
6758 struct drm_i915_private *dev_priv = dev->dev_private;
6759 struct intel_encoder *encoder;
6760 int num_connectors = 0;
6761 bool is_lvds = false;
6762
6763 for_each_encoder_on_crtc(dev, crtc, encoder) {
6764 switch (encoder->type) {
6765 case INTEL_OUTPUT_LVDS:
6766 is_lvds = true;
6767 break;
6768 }
6769 num_connectors++;
6770 }
6771
6772 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6773 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6774 dev_priv->vbt.lvds_ssc_freq);
6775 return dev_priv->vbt.lvds_ssc_freq;
6776 }
6777
6778 return 120000;
6779 }
6780
6781 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6782 {
6783 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6784 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6785 int pipe = intel_crtc->pipe;
6786 uint32_t val;
6787
6788 val = 0;
6789
6790 switch (intel_crtc->config.pipe_bpp) {
6791 case 18:
6792 val |= PIPECONF_6BPC;
6793 break;
6794 case 24:
6795 val |= PIPECONF_8BPC;
6796 break;
6797 case 30:
6798 val |= PIPECONF_10BPC;
6799 break;
6800 case 36:
6801 val |= PIPECONF_12BPC;
6802 break;
6803 default:
6804 /* Case prevented by intel_choose_pipe_bpp_dither. */
6805 BUG();
6806 }
6807
6808 if (intel_crtc->config.dither)
6809 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6810
6811 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6812 val |= PIPECONF_INTERLACED_ILK;
6813 else
6814 val |= PIPECONF_PROGRESSIVE;
6815
6816 if (intel_crtc->config.limited_color_range)
6817 val |= PIPECONF_COLOR_RANGE_SELECT;
6818
6819 I915_WRITE(PIPECONF(pipe), val);
6820 POSTING_READ(PIPECONF(pipe));
6821 }
6822
6823 /*
6824 * Set up the pipe CSC unit.
6825 *
6826 * Currently only full range RGB to limited range RGB conversion
6827 * is supported, but eventually this should handle various
6828 * RGB<->YCbCr scenarios as well.
6829 */
6830 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6831 {
6832 struct drm_device *dev = crtc->dev;
6833 struct drm_i915_private *dev_priv = dev->dev_private;
6834 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6835 int pipe = intel_crtc->pipe;
6836 uint16_t coeff = 0x7800; /* 1.0 */
6837
6838 /*
6839 * TODO: Check what kind of values actually come out of the pipe
6840 * with these coeff/postoff values and adjust to get the best
6841 * accuracy. Perhaps we even need to take the bpc value into
6842 * consideration.
6843 */
6844
6845 if (intel_crtc->config.limited_color_range)
6846 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6847
6848 /*
6849 * GY/GU and RY/RU should be the other way around according
6850 * to BSpec, but reality doesn't agree. Just set them up in
6851 * a way that results in the correct picture.
6852 */
6853 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6854 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6855
6856 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6857 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6858
6859 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6860 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6861
6862 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6863 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6864 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6865
6866 if (INTEL_INFO(dev)->gen > 6) {
6867 uint16_t postoff = 0;
6868
6869 if (intel_crtc->config.limited_color_range)
6870 postoff = (16 * (1 << 12) / 255) & 0x1fff;
6871
6872 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6873 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6874 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6875
6876 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6877 } else {
6878 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6879
6880 if (intel_crtc->config.limited_color_range)
6881 mode |= CSC_BLACK_SCREEN_OFFSET;
6882
6883 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6884 }
6885 }
6886
6887 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6888 {
6889 struct drm_device *dev = crtc->dev;
6890 struct drm_i915_private *dev_priv = dev->dev_private;
6891 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6892 enum pipe pipe = intel_crtc->pipe;
6893 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6894 uint32_t val;
6895
6896 val = 0;
6897
6898 if (IS_HASWELL(dev) && intel_crtc->config.dither)
6899 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6900
6901 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6902 val |= PIPECONF_INTERLACED_ILK;
6903 else
6904 val |= PIPECONF_PROGRESSIVE;
6905
6906 I915_WRITE(PIPECONF(cpu_transcoder), val);
6907 POSTING_READ(PIPECONF(cpu_transcoder));
6908
6909 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6910 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6911
6912 if (IS_BROADWELL(dev)) {
6913 val = 0;
6914
6915 switch (intel_crtc->config.pipe_bpp) {
6916 case 18:
6917 val |= PIPEMISC_DITHER_6_BPC;
6918 break;
6919 case 24:
6920 val |= PIPEMISC_DITHER_8_BPC;
6921 break;
6922 case 30:
6923 val |= PIPEMISC_DITHER_10_BPC;
6924 break;
6925 case 36:
6926 val |= PIPEMISC_DITHER_12_BPC;
6927 break;
6928 default:
6929 /* Case prevented by pipe_config_set_bpp. */
6930 BUG();
6931 }
6932
6933 if (intel_crtc->config.dither)
6934 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6935
6936 I915_WRITE(PIPEMISC(pipe), val);
6937 }
6938 }
6939
6940 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6941 intel_clock_t *clock,
6942 bool *has_reduced_clock,
6943 intel_clock_t *reduced_clock)
6944 {
6945 struct drm_device *dev = crtc->dev;
6946 struct drm_i915_private *dev_priv = dev->dev_private;
6947 struct intel_encoder *intel_encoder;
6948 int refclk;
6949 const intel_limit_t *limit;
6950 bool ret, is_lvds = false;
6951
6952 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6953 switch (intel_encoder->type) {
6954 case INTEL_OUTPUT_LVDS:
6955 is_lvds = true;
6956 break;
6957 }
6958 }
6959
6960 refclk = ironlake_get_refclk(crtc);
6961
6962 /*
6963 * Returns a set of divisors for the desired target clock with the given
6964 * refclk, or FALSE. The returned values represent the clock equation:
6965 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6966 */
6967 limit = intel_limit(crtc, refclk);
6968 ret = dev_priv->display.find_dpll(limit, crtc,
6969 to_intel_crtc(crtc)->config.port_clock,
6970 refclk, NULL, clock);
6971 if (!ret)
6972 return false;
6973
6974 if (is_lvds && dev_priv->lvds_downclock_avail) {
6975 /*
6976 * Ensure we match the reduced clock's P to the target clock.
6977 * If the clocks don't match, we can't switch the display clock
6978 * by using the FP0/FP1. In such case we will disable the LVDS
6979 * downclock feature.
6980 */
6981 *has_reduced_clock =
6982 dev_priv->display.find_dpll(limit, crtc,
6983 dev_priv->lvds_downclock,
6984 refclk, clock,
6985 reduced_clock);
6986 }
6987
6988 return true;
6989 }
6990
6991 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6992 {
6993 /*
6994 * Account for spread spectrum to avoid
6995 * oversubscribing the link. Max center spread
6996 * is 2.5%; use 5% for safety's sake.
6997 */
6998 u32 bps = target_clock * bpp * 21 / 20;
6999 return DIV_ROUND_UP(bps, link_bw * 8);
7000 }
7001
7002 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7003 {
7004 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7005 }
7006
7007 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7008 u32 *fp,
7009 intel_clock_t *reduced_clock, u32 *fp2)
7010 {
7011 struct drm_crtc *crtc = &intel_crtc->base;
7012 struct drm_device *dev = crtc->dev;
7013 struct drm_i915_private *dev_priv = dev->dev_private;
7014 struct intel_encoder *intel_encoder;
7015 uint32_t dpll;
7016 int factor, num_connectors = 0;
7017 bool is_lvds = false, is_sdvo = false;
7018
7019 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
7020 switch (intel_encoder->type) {
7021 case INTEL_OUTPUT_LVDS:
7022 is_lvds = true;
7023 break;
7024 case INTEL_OUTPUT_SDVO:
7025 case INTEL_OUTPUT_HDMI:
7026 is_sdvo = true;
7027 break;
7028 }
7029
7030 num_connectors++;
7031 }
7032
7033 /* Enable autotuning of the PLL clock (if permissible) */
7034 factor = 21;
7035 if (is_lvds) {
7036 if ((intel_panel_use_ssc(dev_priv) &&
7037 dev_priv->vbt.lvds_ssc_freq == 100000) ||
7038 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7039 factor = 25;
7040 } else if (intel_crtc->config.sdvo_tv_clock)
7041 factor = 20;
7042
7043 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7044 *fp |= FP_CB_TUNE;
7045
7046 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7047 *fp2 |= FP_CB_TUNE;
7048
7049 dpll = 0;
7050
7051 if (is_lvds)
7052 dpll |= DPLLB_MODE_LVDS;
7053 else
7054 dpll |= DPLLB_MODE_DAC_SERIAL;
7055
7056 dpll |= (intel_crtc->config.pixel_multiplier - 1)
7057 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7058
7059 if (is_sdvo)
7060 dpll |= DPLL_SDVO_HIGH_SPEED;
7061 if (intel_crtc->config.has_dp_encoder)
7062 dpll |= DPLL_SDVO_HIGH_SPEED;
7063
7064 /* compute bitmask from p1 value */
7065 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7066 /* also FPA1 */
7067 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7068
7069 switch (intel_crtc->config.dpll.p2) {
7070 case 5:
7071 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7072 break;
7073 case 7:
7074 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7075 break;
7076 case 10:
7077 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7078 break;
7079 case 14:
7080 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7081 break;
7082 }
7083
7084 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7085 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7086 else
7087 dpll |= PLL_REF_INPUT_DREFCLK;
7088
7089 return dpll | DPLL_VCO_ENABLE;
7090 }
7091
7092 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
7093 int x, int y,
7094 struct drm_framebuffer *fb)
7095 {
7096 struct drm_device *dev = crtc->dev;
7097 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7098 int num_connectors = 0;
7099 intel_clock_t clock, reduced_clock;
7100 u32 dpll = 0, fp = 0, fp2 = 0;
7101 bool ok, has_reduced_clock = false;
7102 bool is_lvds = false;
7103 struct intel_encoder *encoder;
7104 struct intel_shared_dpll *pll;
7105
7106 for_each_encoder_on_crtc(dev, crtc, encoder) {
7107 switch (encoder->type) {
7108 case INTEL_OUTPUT_LVDS:
7109 is_lvds = true;
7110 break;
7111 }
7112
7113 num_connectors++;
7114 }
7115
7116 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7117 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7118
7119 ok = ironlake_compute_clocks(crtc, &clock,
7120 &has_reduced_clock, &reduced_clock);
7121 if (!ok && !intel_crtc->config.clock_set) {
7122 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7123 return -EINVAL;
7124 }
7125 /* Compat-code for transition, will disappear. */
7126 if (!intel_crtc->config.clock_set) {
7127 intel_crtc->config.dpll.n = clock.n;
7128 intel_crtc->config.dpll.m1 = clock.m1;
7129 intel_crtc->config.dpll.m2 = clock.m2;
7130 intel_crtc->config.dpll.p1 = clock.p1;
7131 intel_crtc->config.dpll.p2 = clock.p2;
7132 }
7133
7134 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7135 if (intel_crtc->config.has_pch_encoder) {
7136 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
7137 if (has_reduced_clock)
7138 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7139
7140 dpll = ironlake_compute_dpll(intel_crtc,
7141 &fp, &reduced_clock,
7142 has_reduced_clock ? &fp2 : NULL);
7143
7144 intel_crtc->config.dpll_hw_state.dpll = dpll;
7145 intel_crtc->config.dpll_hw_state.fp0 = fp;
7146 if (has_reduced_clock)
7147 intel_crtc->config.dpll_hw_state.fp1 = fp2;
7148 else
7149 intel_crtc->config.dpll_hw_state.fp1 = fp;
7150
7151 pll = intel_get_shared_dpll(intel_crtc);
7152 if (pll == NULL) {
7153 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7154 pipe_name(intel_crtc->pipe));
7155 return -EINVAL;
7156 }
7157 } else
7158 intel_put_shared_dpll(intel_crtc);
7159
7160 if (is_lvds && has_reduced_clock && i915.powersave)
7161 intel_crtc->lowfreq_avail = true;
7162 else
7163 intel_crtc->lowfreq_avail = false;
7164
7165 return 0;
7166 }
7167
7168 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7169 struct intel_link_m_n *m_n)
7170 {
7171 struct drm_device *dev = crtc->base.dev;
7172 struct drm_i915_private *dev_priv = dev->dev_private;
7173 enum pipe pipe = crtc->pipe;
7174
7175 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7176 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7177 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7178 & ~TU_SIZE_MASK;
7179 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7180 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7181 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7182 }
7183
7184 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7185 enum transcoder transcoder,
7186 struct intel_link_m_n *m_n,
7187 struct intel_link_m_n *m2_n2)
7188 {
7189 struct drm_device *dev = crtc->base.dev;
7190 struct drm_i915_private *dev_priv = dev->dev_private;
7191 enum pipe pipe = crtc->pipe;
7192
7193 if (INTEL_INFO(dev)->gen >= 5) {
7194 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7195 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7196 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7197 & ~TU_SIZE_MASK;
7198 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7199 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7200 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7201 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7202 * gen < 8) and if DRRS is supported (to make sure the
7203 * registers are not unnecessarily read).
7204 */
7205 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7206 crtc->config.has_drrs) {
7207 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7208 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7209 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7210 & ~TU_SIZE_MASK;
7211 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7212 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7213 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7214 }
7215 } else {
7216 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7217 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7218 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7219 & ~TU_SIZE_MASK;
7220 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7221 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7222 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7223 }
7224 }
7225
7226 void intel_dp_get_m_n(struct intel_crtc *crtc,
7227 struct intel_crtc_config *pipe_config)
7228 {
7229 if (crtc->config.has_pch_encoder)
7230 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7231 else
7232 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7233 &pipe_config->dp_m_n,
7234 &pipe_config->dp_m2_n2);
7235 }
7236
7237 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7238 struct intel_crtc_config *pipe_config)
7239 {
7240 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7241 &pipe_config->fdi_m_n, NULL);
7242 }
7243
7244 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7245 struct intel_crtc_config *pipe_config)
7246 {
7247 struct drm_device *dev = crtc->base.dev;
7248 struct drm_i915_private *dev_priv = dev->dev_private;
7249 uint32_t tmp;
7250
7251 tmp = I915_READ(PF_CTL(crtc->pipe));
7252
7253 if (tmp & PF_ENABLE) {
7254 pipe_config->pch_pfit.enabled = true;
7255 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7256 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7257
7258 /* We currently do not free assignements of panel fitters on
7259 * ivb/hsw (since we don't use the higher upscaling modes which
7260 * differentiates them) so just WARN about this case for now. */
7261 if (IS_GEN7(dev)) {
7262 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7263 PF_PIPE_SEL_IVB(crtc->pipe));
7264 }
7265 }
7266 }
7267
7268 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7269 struct intel_plane_config *plane_config)
7270 {
7271 struct drm_device *dev = crtc->base.dev;
7272 struct drm_i915_private *dev_priv = dev->dev_private;
7273 u32 val, base, offset;
7274 int pipe = crtc->pipe, plane = crtc->plane;
7275 int fourcc, pixel_format;
7276 int aligned_height;
7277
7278 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7279 if (!crtc->base.primary->fb) {
7280 DRM_DEBUG_KMS("failed to alloc fb\n");
7281 return;
7282 }
7283
7284 val = I915_READ(DSPCNTR(plane));
7285
7286 if (INTEL_INFO(dev)->gen >= 4)
7287 if (val & DISPPLANE_TILED)
7288 plane_config->tiled = true;
7289
7290 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7291 fourcc = intel_format_to_fourcc(pixel_format);
7292 crtc->base.primary->fb->pixel_format = fourcc;
7293 crtc->base.primary->fb->bits_per_pixel =
7294 drm_format_plane_cpp(fourcc, 0) * 8;
7295
7296 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7297 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7298 offset = I915_READ(DSPOFFSET(plane));
7299 } else {
7300 if (plane_config->tiled)
7301 offset = I915_READ(DSPTILEOFF(plane));
7302 else
7303 offset = I915_READ(DSPLINOFF(plane));
7304 }
7305 plane_config->base = base;
7306
7307 val = I915_READ(PIPESRC(pipe));
7308 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7309 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7310
7311 val = I915_READ(DSPSTRIDE(pipe));
7312 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
7313
7314 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7315 plane_config->tiled);
7316
7317 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7318 aligned_height);
7319
7320 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7321 pipe, plane, crtc->base.primary->fb->width,
7322 crtc->base.primary->fb->height,
7323 crtc->base.primary->fb->bits_per_pixel, base,
7324 crtc->base.primary->fb->pitches[0],
7325 plane_config->size);
7326 }
7327
7328 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7329 struct intel_crtc_config *pipe_config)
7330 {
7331 struct drm_device *dev = crtc->base.dev;
7332 struct drm_i915_private *dev_priv = dev->dev_private;
7333 uint32_t tmp;
7334
7335 if (!intel_display_power_enabled(dev_priv,
7336 POWER_DOMAIN_PIPE(crtc->pipe)))
7337 return false;
7338
7339 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7340 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7341
7342 tmp = I915_READ(PIPECONF(crtc->pipe));
7343 if (!(tmp & PIPECONF_ENABLE))
7344 return false;
7345
7346 switch (tmp & PIPECONF_BPC_MASK) {
7347 case PIPECONF_6BPC:
7348 pipe_config->pipe_bpp = 18;
7349 break;
7350 case PIPECONF_8BPC:
7351 pipe_config->pipe_bpp = 24;
7352 break;
7353 case PIPECONF_10BPC:
7354 pipe_config->pipe_bpp = 30;
7355 break;
7356 case PIPECONF_12BPC:
7357 pipe_config->pipe_bpp = 36;
7358 break;
7359 default:
7360 break;
7361 }
7362
7363 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7364 pipe_config->limited_color_range = true;
7365
7366 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7367 struct intel_shared_dpll *pll;
7368
7369 pipe_config->has_pch_encoder = true;
7370
7371 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7372 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7373 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7374
7375 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7376
7377 if (HAS_PCH_IBX(dev_priv->dev)) {
7378 pipe_config->shared_dpll =
7379 (enum intel_dpll_id) crtc->pipe;
7380 } else {
7381 tmp = I915_READ(PCH_DPLL_SEL);
7382 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7383 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7384 else
7385 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7386 }
7387
7388 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7389
7390 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7391 &pipe_config->dpll_hw_state));
7392
7393 tmp = pipe_config->dpll_hw_state.dpll;
7394 pipe_config->pixel_multiplier =
7395 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7396 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7397
7398 ironlake_pch_clock_get(crtc, pipe_config);
7399 } else {
7400 pipe_config->pixel_multiplier = 1;
7401 }
7402
7403 intel_get_pipe_timings(crtc, pipe_config);
7404
7405 ironlake_get_pfit_config(crtc, pipe_config);
7406
7407 return true;
7408 }
7409
7410 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7411 {
7412 struct drm_device *dev = dev_priv->dev;
7413 struct intel_crtc *crtc;
7414
7415 for_each_intel_crtc(dev, crtc)
7416 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7417 pipe_name(crtc->pipe));
7418
7419 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7420 WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7421 WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7422 WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7423 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7424 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7425 "CPU PWM1 enabled\n");
7426 if (IS_HASWELL(dev))
7427 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7428 "CPU PWM2 enabled\n");
7429 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7430 "PCH PWM1 enabled\n");
7431 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7432 "Utility pin enabled\n");
7433 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7434
7435 /*
7436 * In theory we can still leave IRQs enabled, as long as only the HPD
7437 * interrupts remain enabled. We used to check for that, but since it's
7438 * gen-specific and since we only disable LCPLL after we fully disable
7439 * the interrupts, the check below should be enough.
7440 */
7441 WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7442 }
7443
7444 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7445 {
7446 struct drm_device *dev = dev_priv->dev;
7447
7448 if (IS_HASWELL(dev))
7449 return I915_READ(D_COMP_HSW);
7450 else
7451 return I915_READ(D_COMP_BDW);
7452 }
7453
7454 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7455 {
7456 struct drm_device *dev = dev_priv->dev;
7457
7458 if (IS_HASWELL(dev)) {
7459 mutex_lock(&dev_priv->rps.hw_lock);
7460 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7461 val))
7462 DRM_ERROR("Failed to write to D_COMP\n");
7463 mutex_unlock(&dev_priv->rps.hw_lock);
7464 } else {
7465 I915_WRITE(D_COMP_BDW, val);
7466 POSTING_READ(D_COMP_BDW);
7467 }
7468 }
7469
7470 /*
7471 * This function implements pieces of two sequences from BSpec:
7472 * - Sequence for display software to disable LCPLL
7473 * - Sequence for display software to allow package C8+
7474 * The steps implemented here are just the steps that actually touch the LCPLL
7475 * register. Callers should take care of disabling all the display engine
7476 * functions, doing the mode unset, fixing interrupts, etc.
7477 */
7478 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7479 bool switch_to_fclk, bool allow_power_down)
7480 {
7481 uint32_t val;
7482
7483 assert_can_disable_lcpll(dev_priv);
7484
7485 val = I915_READ(LCPLL_CTL);
7486
7487 if (switch_to_fclk) {
7488 val |= LCPLL_CD_SOURCE_FCLK;
7489 I915_WRITE(LCPLL_CTL, val);
7490
7491 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7492 LCPLL_CD_SOURCE_FCLK_DONE, 1))
7493 DRM_ERROR("Switching to FCLK failed\n");
7494
7495 val = I915_READ(LCPLL_CTL);
7496 }
7497
7498 val |= LCPLL_PLL_DISABLE;
7499 I915_WRITE(LCPLL_CTL, val);
7500 POSTING_READ(LCPLL_CTL);
7501
7502 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7503 DRM_ERROR("LCPLL still locked\n");
7504
7505 val = hsw_read_dcomp(dev_priv);
7506 val |= D_COMP_COMP_DISABLE;
7507 hsw_write_dcomp(dev_priv, val);
7508 ndelay(100);
7509
7510 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7511 1))
7512 DRM_ERROR("D_COMP RCOMP still in progress\n");
7513
7514 if (allow_power_down) {
7515 val = I915_READ(LCPLL_CTL);
7516 val |= LCPLL_POWER_DOWN_ALLOW;
7517 I915_WRITE(LCPLL_CTL, val);
7518 POSTING_READ(LCPLL_CTL);
7519 }
7520 }
7521
7522 /*
7523 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7524 * source.
7525 */
7526 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7527 {
7528 uint32_t val;
7529 unsigned long irqflags;
7530
7531 val = I915_READ(LCPLL_CTL);
7532
7533 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7534 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7535 return;
7536
7537 /*
7538 * Make sure we're not on PC8 state before disabling PC8, otherwise
7539 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7540 *
7541 * The other problem is that hsw_restore_lcpll() is called as part of
7542 * the runtime PM resume sequence, so we can't just call
7543 * gen6_gt_force_wake_get() because that function calls
7544 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7545 * while we are on the resume sequence. So to solve this problem we have
7546 * to call special forcewake code that doesn't touch runtime PM and
7547 * doesn't enable the forcewake delayed work.
7548 */
7549 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7550 if (dev_priv->uncore.forcewake_count++ == 0)
7551 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7552 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7553
7554 if (val & LCPLL_POWER_DOWN_ALLOW) {
7555 val &= ~LCPLL_POWER_DOWN_ALLOW;
7556 I915_WRITE(LCPLL_CTL, val);
7557 POSTING_READ(LCPLL_CTL);
7558 }
7559
7560 val = hsw_read_dcomp(dev_priv);
7561 val |= D_COMP_COMP_FORCE;
7562 val &= ~D_COMP_COMP_DISABLE;
7563 hsw_write_dcomp(dev_priv, val);
7564
7565 val = I915_READ(LCPLL_CTL);
7566 val &= ~LCPLL_PLL_DISABLE;
7567 I915_WRITE(LCPLL_CTL, val);
7568
7569 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7570 DRM_ERROR("LCPLL not locked yet\n");
7571
7572 if (val & LCPLL_CD_SOURCE_FCLK) {
7573 val = I915_READ(LCPLL_CTL);
7574 val &= ~LCPLL_CD_SOURCE_FCLK;
7575 I915_WRITE(LCPLL_CTL, val);
7576
7577 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7578 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7579 DRM_ERROR("Switching back to LCPLL failed\n");
7580 }
7581
7582 /* See the big comment above. */
7583 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7584 if (--dev_priv->uncore.forcewake_count == 0)
7585 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7586 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7587 }
7588
7589 /*
7590 * Package states C8 and deeper are really deep PC states that can only be
7591 * reached when all the devices on the system allow it, so even if the graphics
7592 * device allows PC8+, it doesn't mean the system will actually get to these
7593 * states. Our driver only allows PC8+ when going into runtime PM.
7594 *
7595 * The requirements for PC8+ are that all the outputs are disabled, the power
7596 * well is disabled and most interrupts are disabled, and these are also
7597 * requirements for runtime PM. When these conditions are met, we manually do
7598 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7599 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7600 * hang the machine.
7601 *
7602 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7603 * the state of some registers, so when we come back from PC8+ we need to
7604 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7605 * need to take care of the registers kept by RC6. Notice that this happens even
7606 * if we don't put the device in PCI D3 state (which is what currently happens
7607 * because of the runtime PM support).
7608 *
7609 * For more, read "Display Sequences for Package C8" on the hardware
7610 * documentation.
7611 */
7612 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7613 {
7614 struct drm_device *dev = dev_priv->dev;
7615 uint32_t val;
7616
7617 DRM_DEBUG_KMS("Enabling package C8+\n");
7618
7619 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7620 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7621 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7622 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7623 }
7624
7625 lpt_disable_clkout_dp(dev);
7626 hsw_disable_lcpll(dev_priv, true, true);
7627 }
7628
7629 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7630 {
7631 struct drm_device *dev = dev_priv->dev;
7632 uint32_t val;
7633
7634 DRM_DEBUG_KMS("Disabling package C8+\n");
7635
7636 hsw_restore_lcpll(dev_priv);
7637 lpt_init_pch_refclk(dev);
7638
7639 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7640 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7641 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7642 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7643 }
7644
7645 intel_prepare_ddi(dev);
7646 }
7647
7648 static void snb_modeset_global_resources(struct drm_device *dev)
7649 {
7650 modeset_update_crtc_power_domains(dev);
7651 }
7652
7653 static void haswell_modeset_global_resources(struct drm_device *dev)
7654 {
7655 modeset_update_crtc_power_domains(dev);
7656 }
7657
7658 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7659 int x, int y,
7660 struct drm_framebuffer *fb)
7661 {
7662 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7663
7664 if (!intel_ddi_pll_select(intel_crtc))
7665 return -EINVAL;
7666
7667 intel_crtc->lowfreq_avail = false;
7668
7669 return 0;
7670 }
7671
7672 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
7673 enum port port,
7674 struct intel_crtc_config *pipe_config)
7675 {
7676 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
7677
7678 switch (pipe_config->ddi_pll_sel) {
7679 case PORT_CLK_SEL_WRPLL1:
7680 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
7681 break;
7682 case PORT_CLK_SEL_WRPLL2:
7683 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
7684 break;
7685 }
7686 }
7687
7688 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
7689 struct intel_crtc_config *pipe_config)
7690 {
7691 struct drm_device *dev = crtc->base.dev;
7692 struct drm_i915_private *dev_priv = dev->dev_private;
7693 struct intel_shared_dpll *pll;
7694 enum port port;
7695 uint32_t tmp;
7696
7697 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7698
7699 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
7700
7701 haswell_get_ddi_pll(dev_priv, port, pipe_config);
7702
7703 if (pipe_config->shared_dpll >= 0) {
7704 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7705
7706 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7707 &pipe_config->dpll_hw_state));
7708 }
7709
7710 /*
7711 * Haswell has only FDI/PCH transcoder A. It is which is connected to
7712 * DDI E. So just check whether this pipe is wired to DDI E and whether
7713 * the PCH transcoder is on.
7714 */
7715 if ((port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7716 pipe_config->has_pch_encoder = true;
7717
7718 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7719 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7720 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7721
7722 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7723 }
7724 }
7725
7726 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7727 struct intel_crtc_config *pipe_config)
7728 {
7729 struct drm_device *dev = crtc->base.dev;
7730 struct drm_i915_private *dev_priv = dev->dev_private;
7731 enum intel_display_power_domain pfit_domain;
7732 uint32_t tmp;
7733
7734 if (!intel_display_power_enabled(dev_priv,
7735 POWER_DOMAIN_PIPE(crtc->pipe)))
7736 return false;
7737
7738 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7739 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7740
7741 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7742 if (tmp & TRANS_DDI_FUNC_ENABLE) {
7743 enum pipe trans_edp_pipe;
7744 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7745 default:
7746 WARN(1, "unknown pipe linked to edp transcoder\n");
7747 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7748 case TRANS_DDI_EDP_INPUT_A_ON:
7749 trans_edp_pipe = PIPE_A;
7750 break;
7751 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7752 trans_edp_pipe = PIPE_B;
7753 break;
7754 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7755 trans_edp_pipe = PIPE_C;
7756 break;
7757 }
7758
7759 if (trans_edp_pipe == crtc->pipe)
7760 pipe_config->cpu_transcoder = TRANSCODER_EDP;
7761 }
7762
7763 if (!intel_display_power_enabled(dev_priv,
7764 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7765 return false;
7766
7767 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7768 if (!(tmp & PIPECONF_ENABLE))
7769 return false;
7770
7771 haswell_get_ddi_port_state(crtc, pipe_config);
7772
7773 intel_get_pipe_timings(crtc, pipe_config);
7774
7775 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7776 if (intel_display_power_enabled(dev_priv, pfit_domain))
7777 ironlake_get_pfit_config(crtc, pipe_config);
7778
7779 if (IS_HASWELL(dev))
7780 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7781 (I915_READ(IPS_CTL) & IPS_ENABLE);
7782
7783 pipe_config->pixel_multiplier = 1;
7784
7785 return true;
7786 }
7787
7788 static struct {
7789 int clock;
7790 u32 config;
7791 } hdmi_audio_clock[] = {
7792 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7793 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7794 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7795 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7796 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7797 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7798 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7799 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7800 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7801 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7802 };
7803
7804 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7805 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7806 {
7807 int i;
7808
7809 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7810 if (mode->clock == hdmi_audio_clock[i].clock)
7811 break;
7812 }
7813
7814 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7815 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7816 i = 1;
7817 }
7818
7819 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7820 hdmi_audio_clock[i].clock,
7821 hdmi_audio_clock[i].config);
7822
7823 return hdmi_audio_clock[i].config;
7824 }
7825
7826 static bool intel_eld_uptodate(struct drm_connector *connector,
7827 int reg_eldv, uint32_t bits_eldv,
7828 int reg_elda, uint32_t bits_elda,
7829 int reg_edid)
7830 {
7831 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7832 uint8_t *eld = connector->eld;
7833 uint32_t i;
7834
7835 i = I915_READ(reg_eldv);
7836 i &= bits_eldv;
7837
7838 if (!eld[0])
7839 return !i;
7840
7841 if (!i)
7842 return false;
7843
7844 i = I915_READ(reg_elda);
7845 i &= ~bits_elda;
7846 I915_WRITE(reg_elda, i);
7847
7848 for (i = 0; i < eld[2]; i++)
7849 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7850 return false;
7851
7852 return true;
7853 }
7854
7855 static void g4x_write_eld(struct drm_connector *connector,
7856 struct drm_crtc *crtc,
7857 struct drm_display_mode *mode)
7858 {
7859 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7860 uint8_t *eld = connector->eld;
7861 uint32_t eldv;
7862 uint32_t len;
7863 uint32_t i;
7864
7865 i = I915_READ(G4X_AUD_VID_DID);
7866
7867 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7868 eldv = G4X_ELDV_DEVCL_DEVBLC;
7869 else
7870 eldv = G4X_ELDV_DEVCTG;
7871
7872 if (intel_eld_uptodate(connector,
7873 G4X_AUD_CNTL_ST, eldv,
7874 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7875 G4X_HDMIW_HDMIEDID))
7876 return;
7877
7878 i = I915_READ(G4X_AUD_CNTL_ST);
7879 i &= ~(eldv | G4X_ELD_ADDR);
7880 len = (i >> 9) & 0x1f; /* ELD buffer size */
7881 I915_WRITE(G4X_AUD_CNTL_ST, i);
7882
7883 if (!eld[0])
7884 return;
7885
7886 len = min_t(uint8_t, eld[2], len);
7887 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7888 for (i = 0; i < len; i++)
7889 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7890
7891 i = I915_READ(G4X_AUD_CNTL_ST);
7892 i |= eldv;
7893 I915_WRITE(G4X_AUD_CNTL_ST, i);
7894 }
7895
7896 static void haswell_write_eld(struct drm_connector *connector,
7897 struct drm_crtc *crtc,
7898 struct drm_display_mode *mode)
7899 {
7900 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7901 uint8_t *eld = connector->eld;
7902 uint32_t eldv;
7903 uint32_t i;
7904 int len;
7905 int pipe = to_intel_crtc(crtc)->pipe;
7906 int tmp;
7907
7908 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7909 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7910 int aud_config = HSW_AUD_CFG(pipe);
7911 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7912
7913 /* Audio output enable */
7914 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7915 tmp = I915_READ(aud_cntrl_st2);
7916 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7917 I915_WRITE(aud_cntrl_st2, tmp);
7918 POSTING_READ(aud_cntrl_st2);
7919
7920 assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
7921
7922 /* Set ELD valid state */
7923 tmp = I915_READ(aud_cntrl_st2);
7924 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7925 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7926 I915_WRITE(aud_cntrl_st2, tmp);
7927 tmp = I915_READ(aud_cntrl_st2);
7928 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7929
7930 /* Enable HDMI mode */
7931 tmp = I915_READ(aud_config);
7932 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7933 /* clear N_programing_enable and N_value_index */
7934 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7935 I915_WRITE(aud_config, tmp);
7936
7937 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7938
7939 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7940
7941 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7942 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7943 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7944 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7945 } else {
7946 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7947 }
7948
7949 if (intel_eld_uptodate(connector,
7950 aud_cntrl_st2, eldv,
7951 aud_cntl_st, IBX_ELD_ADDRESS,
7952 hdmiw_hdmiedid))
7953 return;
7954
7955 i = I915_READ(aud_cntrl_st2);
7956 i &= ~eldv;
7957 I915_WRITE(aud_cntrl_st2, i);
7958
7959 if (!eld[0])
7960 return;
7961
7962 i = I915_READ(aud_cntl_st);
7963 i &= ~IBX_ELD_ADDRESS;
7964 I915_WRITE(aud_cntl_st, i);
7965 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
7966 DRM_DEBUG_DRIVER("port num:%d\n", i);
7967
7968 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7969 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7970 for (i = 0; i < len; i++)
7971 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7972
7973 i = I915_READ(aud_cntrl_st2);
7974 i |= eldv;
7975 I915_WRITE(aud_cntrl_st2, i);
7976
7977 }
7978
7979 static void ironlake_write_eld(struct drm_connector *connector,
7980 struct drm_crtc *crtc,
7981 struct drm_display_mode *mode)
7982 {
7983 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7984 uint8_t *eld = connector->eld;
7985 uint32_t eldv;
7986 uint32_t i;
7987 int len;
7988 int hdmiw_hdmiedid;
7989 int aud_config;
7990 int aud_cntl_st;
7991 int aud_cntrl_st2;
7992 int pipe = to_intel_crtc(crtc)->pipe;
7993
7994 if (HAS_PCH_IBX(connector->dev)) {
7995 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7996 aud_config = IBX_AUD_CFG(pipe);
7997 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7998 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7999 } else if (IS_VALLEYVIEW(connector->dev)) {
8000 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
8001 aud_config = VLV_AUD_CFG(pipe);
8002 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
8003 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
8004 } else {
8005 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
8006 aud_config = CPT_AUD_CFG(pipe);
8007 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
8008 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
8009 }
8010
8011 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
8012
8013 if (IS_VALLEYVIEW(connector->dev)) {
8014 struct intel_encoder *intel_encoder;
8015 struct intel_digital_port *intel_dig_port;
8016
8017 intel_encoder = intel_attached_encoder(connector);
8018 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
8019 i = intel_dig_port->port;
8020 } else {
8021 i = I915_READ(aud_cntl_st);
8022 i = (i >> 29) & DIP_PORT_SEL_MASK;
8023 /* DIP_Port_Select, 0x1 = PortB */
8024 }
8025
8026 if (!i) {
8027 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
8028 /* operate blindly on all ports */
8029 eldv = IBX_ELD_VALIDB;
8030 eldv |= IBX_ELD_VALIDB << 4;
8031 eldv |= IBX_ELD_VALIDB << 8;
8032 } else {
8033 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
8034 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
8035 }
8036
8037 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
8038 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
8039 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
8040 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
8041 } else {
8042 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
8043 }
8044
8045 if (intel_eld_uptodate(connector,
8046 aud_cntrl_st2, eldv,
8047 aud_cntl_st, IBX_ELD_ADDRESS,
8048 hdmiw_hdmiedid))
8049 return;
8050
8051 i = I915_READ(aud_cntrl_st2);
8052 i &= ~eldv;
8053 I915_WRITE(aud_cntrl_st2, i);
8054
8055 if (!eld[0])
8056 return;
8057
8058 i = I915_READ(aud_cntl_st);
8059 i &= ~IBX_ELD_ADDRESS;
8060 I915_WRITE(aud_cntl_st, i);
8061
8062 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
8063 DRM_DEBUG_DRIVER("ELD size %d\n", len);
8064 for (i = 0; i < len; i++)
8065 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
8066
8067 i = I915_READ(aud_cntrl_st2);
8068 i |= eldv;
8069 I915_WRITE(aud_cntrl_st2, i);
8070 }
8071
8072 void intel_write_eld(struct drm_encoder *encoder,
8073 struct drm_display_mode *mode)
8074 {
8075 struct drm_crtc *crtc = encoder->crtc;
8076 struct drm_connector *connector;
8077 struct drm_device *dev = encoder->dev;
8078 struct drm_i915_private *dev_priv = dev->dev_private;
8079
8080 connector = drm_select_eld(encoder, mode);
8081 if (!connector)
8082 return;
8083
8084 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8085 connector->base.id,
8086 connector->name,
8087 connector->encoder->base.id,
8088 connector->encoder->name);
8089
8090 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
8091
8092 if (dev_priv->display.write_eld)
8093 dev_priv->display.write_eld(connector, crtc, mode);
8094 }
8095
8096 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8097 {
8098 struct drm_device *dev = crtc->dev;
8099 struct drm_i915_private *dev_priv = dev->dev_private;
8100 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8101 uint32_t cntl = 0, size = 0;
8102
8103 if (base) {
8104 unsigned int width = intel_crtc->cursor_width;
8105 unsigned int height = intel_crtc->cursor_height;
8106 unsigned int stride = roundup_pow_of_two(width) * 4;
8107
8108 switch (stride) {
8109 default:
8110 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8111 width, stride);
8112 stride = 256;
8113 /* fallthrough */
8114 case 256:
8115 case 512:
8116 case 1024:
8117 case 2048:
8118 break;
8119 }
8120
8121 cntl |= CURSOR_ENABLE |
8122 CURSOR_GAMMA_ENABLE |
8123 CURSOR_FORMAT_ARGB |
8124 CURSOR_STRIDE(stride);
8125
8126 size = (height << 12) | width;
8127 }
8128
8129 if (intel_crtc->cursor_cntl != 0 &&
8130 (intel_crtc->cursor_base != base ||
8131 intel_crtc->cursor_size != size ||
8132 intel_crtc->cursor_cntl != cntl)) {
8133 /* On these chipsets we can only modify the base/size/stride
8134 * whilst the cursor is disabled.
8135 */
8136 I915_WRITE(_CURACNTR, 0);
8137 POSTING_READ(_CURACNTR);
8138 intel_crtc->cursor_cntl = 0;
8139 }
8140
8141 if (intel_crtc->cursor_base != base)
8142 I915_WRITE(_CURABASE, base);
8143
8144 if (intel_crtc->cursor_size != size) {
8145 I915_WRITE(CURSIZE, size);
8146 intel_crtc->cursor_size = size;
8147 }
8148
8149 if (intel_crtc->cursor_cntl != cntl) {
8150 I915_WRITE(_CURACNTR, cntl);
8151 POSTING_READ(_CURACNTR);
8152 intel_crtc->cursor_cntl = cntl;
8153 }
8154 }
8155
8156 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8157 {
8158 struct drm_device *dev = crtc->dev;
8159 struct drm_i915_private *dev_priv = dev->dev_private;
8160 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8161 int pipe = intel_crtc->pipe;
8162 uint32_t cntl;
8163
8164 cntl = 0;
8165 if (base) {
8166 cntl = MCURSOR_GAMMA_ENABLE;
8167 switch (intel_crtc->cursor_width) {
8168 case 64:
8169 cntl |= CURSOR_MODE_64_ARGB_AX;
8170 break;
8171 case 128:
8172 cntl |= CURSOR_MODE_128_ARGB_AX;
8173 break;
8174 case 256:
8175 cntl |= CURSOR_MODE_256_ARGB_AX;
8176 break;
8177 default:
8178 WARN_ON(1);
8179 return;
8180 }
8181 cntl |= pipe << 28; /* Connect to correct pipe */
8182 }
8183 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8184 cntl |= CURSOR_PIPE_CSC_ENABLE;
8185
8186 if (intel_crtc->cursor_cntl != cntl) {
8187 I915_WRITE(CURCNTR(pipe), cntl);
8188 POSTING_READ(CURCNTR(pipe));
8189 intel_crtc->cursor_cntl = cntl;
8190 }
8191
8192 /* and commit changes on next vblank */
8193 I915_WRITE(CURBASE(pipe), base);
8194 POSTING_READ(CURBASE(pipe));
8195 }
8196
8197 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8198 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8199 bool on)
8200 {
8201 struct drm_device *dev = crtc->dev;
8202 struct drm_i915_private *dev_priv = dev->dev_private;
8203 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8204 int pipe = intel_crtc->pipe;
8205 int x = crtc->cursor_x;
8206 int y = crtc->cursor_y;
8207 u32 base = 0, pos = 0;
8208
8209 if (on)
8210 base = intel_crtc->cursor_addr;
8211
8212 if (x >= intel_crtc->config.pipe_src_w)
8213 base = 0;
8214
8215 if (y >= intel_crtc->config.pipe_src_h)
8216 base = 0;
8217
8218 if (x < 0) {
8219 if (x + intel_crtc->cursor_width <= 0)
8220 base = 0;
8221
8222 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8223 x = -x;
8224 }
8225 pos |= x << CURSOR_X_SHIFT;
8226
8227 if (y < 0) {
8228 if (y + intel_crtc->cursor_height <= 0)
8229 base = 0;
8230
8231 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8232 y = -y;
8233 }
8234 pos |= y << CURSOR_Y_SHIFT;
8235
8236 if (base == 0 && intel_crtc->cursor_base == 0)
8237 return;
8238
8239 I915_WRITE(CURPOS(pipe), pos);
8240
8241 if (IS_845G(dev) || IS_I865G(dev))
8242 i845_update_cursor(crtc, base);
8243 else
8244 i9xx_update_cursor(crtc, base);
8245 intel_crtc->cursor_base = base;
8246 }
8247
8248 static bool cursor_size_ok(struct drm_device *dev,
8249 uint32_t width, uint32_t height)
8250 {
8251 if (width == 0 || height == 0)
8252 return false;
8253
8254 /*
8255 * 845g/865g are special in that they are only limited by
8256 * the width of their cursors, the height is arbitrary up to
8257 * the precision of the register. Everything else requires
8258 * square cursors, limited to a few power-of-two sizes.
8259 */
8260 if (IS_845G(dev) || IS_I865G(dev)) {
8261 if ((width & 63) != 0)
8262 return false;
8263
8264 if (width > (IS_845G(dev) ? 64 : 512))
8265 return false;
8266
8267 if (height > 1023)
8268 return false;
8269 } else {
8270 switch (width | height) {
8271 case 256:
8272 case 128:
8273 if (IS_GEN2(dev))
8274 return false;
8275 case 64:
8276 break;
8277 default:
8278 return false;
8279 }
8280 }
8281
8282 return true;
8283 }
8284
8285 /*
8286 * intel_crtc_cursor_set_obj - Set cursor to specified GEM object
8287 *
8288 * Note that the object's reference will be consumed if the update fails. If
8289 * the update succeeds, the reference of the old object (if any) will be
8290 * consumed.
8291 */
8292 static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8293 struct drm_i915_gem_object *obj,
8294 uint32_t width, uint32_t height)
8295 {
8296 struct drm_device *dev = crtc->dev;
8297 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8298 enum pipe pipe = intel_crtc->pipe;
8299 unsigned old_width, stride;
8300 uint32_t addr;
8301 int ret;
8302
8303 /* if we want to turn off the cursor ignore width and height */
8304 if (!obj) {
8305 DRM_DEBUG_KMS("cursor off\n");
8306 addr = 0;
8307 mutex_lock(&dev->struct_mutex);
8308 goto finish;
8309 }
8310
8311 /* Check for which cursor types we support */
8312 if (!cursor_size_ok(dev, width, height)) {
8313 DRM_DEBUG("Cursor dimension not supported\n");
8314 return -EINVAL;
8315 }
8316
8317 stride = roundup_pow_of_two(width) * 4;
8318 if (obj->base.size < stride * height) {
8319 DRM_DEBUG_KMS("buffer is too small\n");
8320 ret = -ENOMEM;
8321 goto fail;
8322 }
8323
8324 /* we only need to pin inside GTT if cursor is non-phy */
8325 mutex_lock(&dev->struct_mutex);
8326 if (!INTEL_INFO(dev)->cursor_needs_physical) {
8327 unsigned alignment;
8328
8329 if (obj->tiling_mode) {
8330 DRM_DEBUG_KMS("cursor cannot be tiled\n");
8331 ret = -EINVAL;
8332 goto fail_locked;
8333 }
8334
8335 /* Note that the w/a also requires 2 PTE of padding following
8336 * the bo. We currently fill all unused PTE with the shadow
8337 * page and so we should always have valid PTE following the
8338 * cursor preventing the VT-d warning.
8339 */
8340 alignment = 0;
8341 if (need_vtd_wa(dev))
8342 alignment = 64*1024;
8343
8344 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8345 if (ret) {
8346 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8347 goto fail_locked;
8348 }
8349
8350 ret = i915_gem_object_put_fence(obj);
8351 if (ret) {
8352 DRM_DEBUG_KMS("failed to release fence for cursor");
8353 goto fail_unpin;
8354 }
8355
8356 addr = i915_gem_obj_ggtt_offset(obj);
8357 } else {
8358 int align = IS_I830(dev) ? 16 * 1024 : 256;
8359 ret = i915_gem_object_attach_phys(obj, align);
8360 if (ret) {
8361 DRM_DEBUG_KMS("failed to attach phys object\n");
8362 goto fail_locked;
8363 }
8364 addr = obj->phys_handle->busaddr;
8365 }
8366
8367 finish:
8368 if (intel_crtc->cursor_bo) {
8369 if (!INTEL_INFO(dev)->cursor_needs_physical)
8370 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8371 }
8372
8373 i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8374 INTEL_FRONTBUFFER_CURSOR(pipe));
8375 mutex_unlock(&dev->struct_mutex);
8376
8377 old_width = intel_crtc->cursor_width;
8378
8379 intel_crtc->cursor_addr = addr;
8380 intel_crtc->cursor_bo = obj;
8381 intel_crtc->cursor_width = width;
8382 intel_crtc->cursor_height = height;
8383
8384 if (intel_crtc->active) {
8385 if (old_width != width)
8386 intel_update_watermarks(crtc);
8387 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8388 }
8389
8390 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
8391
8392 return 0;
8393 fail_unpin:
8394 i915_gem_object_unpin_from_display_plane(obj);
8395 fail_locked:
8396 mutex_unlock(&dev->struct_mutex);
8397 fail:
8398 drm_gem_object_unreference_unlocked(&obj->base);
8399 return ret;
8400 }
8401
8402 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8403 u16 *blue, uint32_t start, uint32_t size)
8404 {
8405 int end = (start + size > 256) ? 256 : start + size, i;
8406 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8407
8408 for (i = start; i < end; i++) {
8409 intel_crtc->lut_r[i] = red[i] >> 8;
8410 intel_crtc->lut_g[i] = green[i] >> 8;
8411 intel_crtc->lut_b[i] = blue[i] >> 8;
8412 }
8413
8414 intel_crtc_load_lut(crtc);
8415 }
8416
8417 /* VESA 640x480x72Hz mode to set on the pipe */
8418 static struct drm_display_mode load_detect_mode = {
8419 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8420 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8421 };
8422
8423 struct drm_framebuffer *
8424 __intel_framebuffer_create(struct drm_device *dev,
8425 struct drm_mode_fb_cmd2 *mode_cmd,
8426 struct drm_i915_gem_object *obj)
8427 {
8428 struct intel_framebuffer *intel_fb;
8429 int ret;
8430
8431 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8432 if (!intel_fb) {
8433 drm_gem_object_unreference_unlocked(&obj->base);
8434 return ERR_PTR(-ENOMEM);
8435 }
8436
8437 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8438 if (ret)
8439 goto err;
8440
8441 return &intel_fb->base;
8442 err:
8443 drm_gem_object_unreference_unlocked(&obj->base);
8444 kfree(intel_fb);
8445
8446 return ERR_PTR(ret);
8447 }
8448
8449 static struct drm_framebuffer *
8450 intel_framebuffer_create(struct drm_device *dev,
8451 struct drm_mode_fb_cmd2 *mode_cmd,
8452 struct drm_i915_gem_object *obj)
8453 {
8454 struct drm_framebuffer *fb;
8455 int ret;
8456
8457 ret = i915_mutex_lock_interruptible(dev);
8458 if (ret)
8459 return ERR_PTR(ret);
8460 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8461 mutex_unlock(&dev->struct_mutex);
8462
8463 return fb;
8464 }
8465
8466 static u32
8467 intel_framebuffer_pitch_for_width(int width, int bpp)
8468 {
8469 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8470 return ALIGN(pitch, 64);
8471 }
8472
8473 static u32
8474 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8475 {
8476 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8477 return PAGE_ALIGN(pitch * mode->vdisplay);
8478 }
8479
8480 static struct drm_framebuffer *
8481 intel_framebuffer_create_for_mode(struct drm_device *dev,
8482 struct drm_display_mode *mode,
8483 int depth, int bpp)
8484 {
8485 struct drm_i915_gem_object *obj;
8486 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8487
8488 obj = i915_gem_alloc_object(dev,
8489 intel_framebuffer_size_for_mode(mode, bpp));
8490 if (obj == NULL)
8491 return ERR_PTR(-ENOMEM);
8492
8493 mode_cmd.width = mode->hdisplay;
8494 mode_cmd.height = mode->vdisplay;
8495 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8496 bpp);
8497 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8498
8499 return intel_framebuffer_create(dev, &mode_cmd, obj);
8500 }
8501
8502 static struct drm_framebuffer *
8503 mode_fits_in_fbdev(struct drm_device *dev,
8504 struct drm_display_mode *mode)
8505 {
8506 #ifdef CONFIG_DRM_I915_FBDEV
8507 struct drm_i915_private *dev_priv = dev->dev_private;
8508 struct drm_i915_gem_object *obj;
8509 struct drm_framebuffer *fb;
8510
8511 if (!dev_priv->fbdev)
8512 return NULL;
8513
8514 if (!dev_priv->fbdev->fb)
8515 return NULL;
8516
8517 obj = dev_priv->fbdev->fb->obj;
8518 BUG_ON(!obj);
8519
8520 fb = &dev_priv->fbdev->fb->base;
8521 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8522 fb->bits_per_pixel))
8523 return NULL;
8524
8525 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8526 return NULL;
8527
8528 return fb;
8529 #else
8530 return NULL;
8531 #endif
8532 }
8533
8534 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8535 struct drm_display_mode *mode,
8536 struct intel_load_detect_pipe *old,
8537 struct drm_modeset_acquire_ctx *ctx)
8538 {
8539 struct intel_crtc *intel_crtc;
8540 struct intel_encoder *intel_encoder =
8541 intel_attached_encoder(connector);
8542 struct drm_crtc *possible_crtc;
8543 struct drm_encoder *encoder = &intel_encoder->base;
8544 struct drm_crtc *crtc = NULL;
8545 struct drm_device *dev = encoder->dev;
8546 struct drm_framebuffer *fb;
8547 struct drm_mode_config *config = &dev->mode_config;
8548 int ret, i = -1;
8549
8550 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8551 connector->base.id, connector->name,
8552 encoder->base.id, encoder->name);
8553
8554 retry:
8555 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8556 if (ret)
8557 goto fail_unlock;
8558
8559 /*
8560 * Algorithm gets a little messy:
8561 *
8562 * - if the connector already has an assigned crtc, use it (but make
8563 * sure it's on first)
8564 *
8565 * - try to find the first unused crtc that can drive this connector,
8566 * and use that if we find one
8567 */
8568
8569 /* See if we already have a CRTC for this connector */
8570 if (encoder->crtc) {
8571 crtc = encoder->crtc;
8572
8573 ret = drm_modeset_lock(&crtc->mutex, ctx);
8574 if (ret)
8575 goto fail_unlock;
8576
8577 old->dpms_mode = connector->dpms;
8578 old->load_detect_temp = false;
8579
8580 /* Make sure the crtc and connector are running */
8581 if (connector->dpms != DRM_MODE_DPMS_ON)
8582 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8583
8584 return true;
8585 }
8586
8587 /* Find an unused one (if possible) */
8588 for_each_crtc(dev, possible_crtc) {
8589 i++;
8590 if (!(encoder->possible_crtcs & (1 << i)))
8591 continue;
8592 if (possible_crtc->enabled)
8593 continue;
8594 /* This can occur when applying the pipe A quirk on resume. */
8595 if (to_intel_crtc(possible_crtc)->new_enabled)
8596 continue;
8597
8598 crtc = possible_crtc;
8599 break;
8600 }
8601
8602 /*
8603 * If we didn't find an unused CRTC, don't use any.
8604 */
8605 if (!crtc) {
8606 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8607 goto fail_unlock;
8608 }
8609
8610 ret = drm_modeset_lock(&crtc->mutex, ctx);
8611 if (ret)
8612 goto fail_unlock;
8613 intel_encoder->new_crtc = to_intel_crtc(crtc);
8614 to_intel_connector(connector)->new_encoder = intel_encoder;
8615
8616 intel_crtc = to_intel_crtc(crtc);
8617 intel_crtc->new_enabled = true;
8618 intel_crtc->new_config = &intel_crtc->config;
8619 old->dpms_mode = connector->dpms;
8620 old->load_detect_temp = true;
8621 old->release_fb = NULL;
8622
8623 if (!mode)
8624 mode = &load_detect_mode;
8625
8626 /* We need a framebuffer large enough to accommodate all accesses
8627 * that the plane may generate whilst we perform load detection.
8628 * We can not rely on the fbcon either being present (we get called
8629 * during its initialisation to detect all boot displays, or it may
8630 * not even exist) or that it is large enough to satisfy the
8631 * requested mode.
8632 */
8633 fb = mode_fits_in_fbdev(dev, mode);
8634 if (fb == NULL) {
8635 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8636 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8637 old->release_fb = fb;
8638 } else
8639 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8640 if (IS_ERR(fb)) {
8641 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8642 goto fail;
8643 }
8644
8645 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8646 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8647 if (old->release_fb)
8648 old->release_fb->funcs->destroy(old->release_fb);
8649 goto fail;
8650 }
8651
8652 /* let the connector get through one full cycle before testing */
8653 intel_wait_for_vblank(dev, intel_crtc->pipe);
8654 return true;
8655
8656 fail:
8657 intel_crtc->new_enabled = crtc->enabled;
8658 if (intel_crtc->new_enabled)
8659 intel_crtc->new_config = &intel_crtc->config;
8660 else
8661 intel_crtc->new_config = NULL;
8662 fail_unlock:
8663 if (ret == -EDEADLK) {
8664 drm_modeset_backoff(ctx);
8665 goto retry;
8666 }
8667
8668 return false;
8669 }
8670
8671 void intel_release_load_detect_pipe(struct drm_connector *connector,
8672 struct intel_load_detect_pipe *old)
8673 {
8674 struct intel_encoder *intel_encoder =
8675 intel_attached_encoder(connector);
8676 struct drm_encoder *encoder = &intel_encoder->base;
8677 struct drm_crtc *crtc = encoder->crtc;
8678 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8679
8680 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8681 connector->base.id, connector->name,
8682 encoder->base.id, encoder->name);
8683
8684 if (old->load_detect_temp) {
8685 to_intel_connector(connector)->new_encoder = NULL;
8686 intel_encoder->new_crtc = NULL;
8687 intel_crtc->new_enabled = false;
8688 intel_crtc->new_config = NULL;
8689 intel_set_mode(crtc, NULL, 0, 0, NULL);
8690
8691 if (old->release_fb) {
8692 drm_framebuffer_unregister_private(old->release_fb);
8693 drm_framebuffer_unreference(old->release_fb);
8694 }
8695
8696 return;
8697 }
8698
8699 /* Switch crtc and encoder back off if necessary */
8700 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8701 connector->funcs->dpms(connector, old->dpms_mode);
8702 }
8703
8704 static int i9xx_pll_refclk(struct drm_device *dev,
8705 const struct intel_crtc_config *pipe_config)
8706 {
8707 struct drm_i915_private *dev_priv = dev->dev_private;
8708 u32 dpll = pipe_config->dpll_hw_state.dpll;
8709
8710 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8711 return dev_priv->vbt.lvds_ssc_freq;
8712 else if (HAS_PCH_SPLIT(dev))
8713 return 120000;
8714 else if (!IS_GEN2(dev))
8715 return 96000;
8716 else
8717 return 48000;
8718 }
8719
8720 /* Returns the clock of the currently programmed mode of the given pipe. */
8721 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8722 struct intel_crtc_config *pipe_config)
8723 {
8724 struct drm_device *dev = crtc->base.dev;
8725 struct drm_i915_private *dev_priv = dev->dev_private;
8726 int pipe = pipe_config->cpu_transcoder;
8727 u32 dpll = pipe_config->dpll_hw_state.dpll;
8728 u32 fp;
8729 intel_clock_t clock;
8730 int refclk = i9xx_pll_refclk(dev, pipe_config);
8731
8732 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8733 fp = pipe_config->dpll_hw_state.fp0;
8734 else
8735 fp = pipe_config->dpll_hw_state.fp1;
8736
8737 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8738 if (IS_PINEVIEW(dev)) {
8739 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8740 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8741 } else {
8742 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8743 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8744 }
8745
8746 if (!IS_GEN2(dev)) {
8747 if (IS_PINEVIEW(dev))
8748 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8749 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8750 else
8751 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8752 DPLL_FPA01_P1_POST_DIV_SHIFT);
8753
8754 switch (dpll & DPLL_MODE_MASK) {
8755 case DPLLB_MODE_DAC_SERIAL:
8756 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8757 5 : 10;
8758 break;
8759 case DPLLB_MODE_LVDS:
8760 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8761 7 : 14;
8762 break;
8763 default:
8764 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8765 "mode\n", (int)(dpll & DPLL_MODE_MASK));
8766 return;
8767 }
8768
8769 if (IS_PINEVIEW(dev))
8770 pineview_clock(refclk, &clock);
8771 else
8772 i9xx_clock(refclk, &clock);
8773 } else {
8774 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8775 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8776
8777 if (is_lvds) {
8778 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8779 DPLL_FPA01_P1_POST_DIV_SHIFT);
8780
8781 if (lvds & LVDS_CLKB_POWER_UP)
8782 clock.p2 = 7;
8783 else
8784 clock.p2 = 14;
8785 } else {
8786 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8787 clock.p1 = 2;
8788 else {
8789 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8790 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8791 }
8792 if (dpll & PLL_P2_DIVIDE_BY_4)
8793 clock.p2 = 4;
8794 else
8795 clock.p2 = 2;
8796 }
8797
8798 i9xx_clock(refclk, &clock);
8799 }
8800
8801 /*
8802 * This value includes pixel_multiplier. We will use
8803 * port_clock to compute adjusted_mode.crtc_clock in the
8804 * encoder's get_config() function.
8805 */
8806 pipe_config->port_clock = clock.dot;
8807 }
8808
8809 int intel_dotclock_calculate(int link_freq,
8810 const struct intel_link_m_n *m_n)
8811 {
8812 /*
8813 * The calculation for the data clock is:
8814 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8815 * But we want to avoid losing precison if possible, so:
8816 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8817 *
8818 * and the link clock is simpler:
8819 * link_clock = (m * link_clock) / n
8820 */
8821
8822 if (!m_n->link_n)
8823 return 0;
8824
8825 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8826 }
8827
8828 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8829 struct intel_crtc_config *pipe_config)
8830 {
8831 struct drm_device *dev = crtc->base.dev;
8832
8833 /* read out port_clock from the DPLL */
8834 i9xx_crtc_clock_get(crtc, pipe_config);
8835
8836 /*
8837 * This value does not include pixel_multiplier.
8838 * We will check that port_clock and adjusted_mode.crtc_clock
8839 * agree once we know their relationship in the encoder's
8840 * get_config() function.
8841 */
8842 pipe_config->adjusted_mode.crtc_clock =
8843 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8844 &pipe_config->fdi_m_n);
8845 }
8846
8847 /** Returns the currently programmed mode of the given pipe. */
8848 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8849 struct drm_crtc *crtc)
8850 {
8851 struct drm_i915_private *dev_priv = dev->dev_private;
8852 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8853 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8854 struct drm_display_mode *mode;
8855 struct intel_crtc_config pipe_config;
8856 int htot = I915_READ(HTOTAL(cpu_transcoder));
8857 int hsync = I915_READ(HSYNC(cpu_transcoder));
8858 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8859 int vsync = I915_READ(VSYNC(cpu_transcoder));
8860 enum pipe pipe = intel_crtc->pipe;
8861
8862 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8863 if (!mode)
8864 return NULL;
8865
8866 /*
8867 * Construct a pipe_config sufficient for getting the clock info
8868 * back out of crtc_clock_get.
8869 *
8870 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8871 * to use a real value here instead.
8872 */
8873 pipe_config.cpu_transcoder = (enum transcoder) pipe;
8874 pipe_config.pixel_multiplier = 1;
8875 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8876 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8877 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8878 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8879
8880 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8881 mode->hdisplay = (htot & 0xffff) + 1;
8882 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8883 mode->hsync_start = (hsync & 0xffff) + 1;
8884 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8885 mode->vdisplay = (vtot & 0xffff) + 1;
8886 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8887 mode->vsync_start = (vsync & 0xffff) + 1;
8888 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8889
8890 drm_mode_set_name(mode);
8891
8892 return mode;
8893 }
8894
8895 static void intel_increase_pllclock(struct drm_device *dev,
8896 enum pipe pipe)
8897 {
8898 struct drm_i915_private *dev_priv = dev->dev_private;
8899 int dpll_reg = DPLL(pipe);
8900 int dpll;
8901
8902 if (!HAS_GMCH_DISPLAY(dev))
8903 return;
8904
8905 if (!dev_priv->lvds_downclock_avail)
8906 return;
8907
8908 dpll = I915_READ(dpll_reg);
8909 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8910 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8911
8912 assert_panel_unlocked(dev_priv, pipe);
8913
8914 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8915 I915_WRITE(dpll_reg, dpll);
8916 intel_wait_for_vblank(dev, pipe);
8917
8918 dpll = I915_READ(dpll_reg);
8919 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8920 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8921 }
8922 }
8923
8924 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8925 {
8926 struct drm_device *dev = crtc->dev;
8927 struct drm_i915_private *dev_priv = dev->dev_private;
8928 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8929
8930 if (!HAS_GMCH_DISPLAY(dev))
8931 return;
8932
8933 if (!dev_priv->lvds_downclock_avail)
8934 return;
8935
8936 /*
8937 * Since this is called by a timer, we should never get here in
8938 * the manual case.
8939 */
8940 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8941 int pipe = intel_crtc->pipe;
8942 int dpll_reg = DPLL(pipe);
8943 int dpll;
8944
8945 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8946
8947 assert_panel_unlocked(dev_priv, pipe);
8948
8949 dpll = I915_READ(dpll_reg);
8950 dpll |= DISPLAY_RATE_SELECT_FPA1;
8951 I915_WRITE(dpll_reg, dpll);
8952 intel_wait_for_vblank(dev, pipe);
8953 dpll = I915_READ(dpll_reg);
8954 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8955 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8956 }
8957
8958 }
8959
8960 void intel_mark_busy(struct drm_device *dev)
8961 {
8962 struct drm_i915_private *dev_priv = dev->dev_private;
8963
8964 if (dev_priv->mm.busy)
8965 return;
8966
8967 intel_runtime_pm_get(dev_priv);
8968 i915_update_gfx_val(dev_priv);
8969 dev_priv->mm.busy = true;
8970 }
8971
8972 void intel_mark_idle(struct drm_device *dev)
8973 {
8974 struct drm_i915_private *dev_priv = dev->dev_private;
8975 struct drm_crtc *crtc;
8976
8977 if (!dev_priv->mm.busy)
8978 return;
8979
8980 dev_priv->mm.busy = false;
8981
8982 if (!i915.powersave)
8983 goto out;
8984
8985 for_each_crtc(dev, crtc) {
8986 if (!crtc->primary->fb)
8987 continue;
8988
8989 intel_decrease_pllclock(crtc);
8990 }
8991
8992 if (INTEL_INFO(dev)->gen >= 6)
8993 gen6_rps_idle(dev->dev_private);
8994
8995 out:
8996 intel_runtime_pm_put(dev_priv);
8997 }
8998
8999
9000 /**
9001 * intel_mark_fb_busy - mark given planes as busy
9002 * @dev: DRM device
9003 * @frontbuffer_bits: bits for the affected planes
9004 * @ring: optional ring for asynchronous commands
9005 *
9006 * This function gets called every time the screen contents change. It can be
9007 * used to keep e.g. the update rate at the nominal refresh rate with DRRS.
9008 */
9009 static void intel_mark_fb_busy(struct drm_device *dev,
9010 unsigned frontbuffer_bits,
9011 struct intel_engine_cs *ring)
9012 {
9013 struct drm_i915_private *dev_priv = dev->dev_private;
9014 enum pipe pipe;
9015
9016 if (!i915.powersave)
9017 return;
9018
9019 for_each_pipe(dev_priv, pipe) {
9020 if (!(frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe)))
9021 continue;
9022
9023 intel_increase_pllclock(dev, pipe);
9024 if (ring && intel_fbc_enabled(dev))
9025 ring->fbc_dirty = true;
9026 }
9027 }
9028
9029 /**
9030 * intel_fb_obj_invalidate - invalidate frontbuffer object
9031 * @obj: GEM object to invalidate
9032 * @ring: set for asynchronous rendering
9033 *
9034 * This function gets called every time rendering on the given object starts and
9035 * frontbuffer caching (fbc, low refresh rate for DRRS, panel self refresh) must
9036 * be invalidated. If @ring is non-NULL any subsequent invalidation will be delayed
9037 * until the rendering completes or a flip on this frontbuffer plane is
9038 * scheduled.
9039 */
9040 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
9041 struct intel_engine_cs *ring)
9042 {
9043 struct drm_device *dev = obj->base.dev;
9044 struct drm_i915_private *dev_priv = dev->dev_private;
9045
9046 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
9047
9048 if (!obj->frontbuffer_bits)
9049 return;
9050
9051 if (ring) {
9052 mutex_lock(&dev_priv->fb_tracking.lock);
9053 dev_priv->fb_tracking.busy_bits
9054 |= obj->frontbuffer_bits;
9055 dev_priv->fb_tracking.flip_bits
9056 &= ~obj->frontbuffer_bits;
9057 mutex_unlock(&dev_priv->fb_tracking.lock);
9058 }
9059
9060 intel_mark_fb_busy(dev, obj->frontbuffer_bits, ring);
9061
9062 intel_edp_psr_invalidate(dev, obj->frontbuffer_bits);
9063 }
9064
9065 /**
9066 * intel_frontbuffer_flush - flush frontbuffer
9067 * @dev: DRM device
9068 * @frontbuffer_bits: frontbuffer plane tracking bits
9069 *
9070 * This function gets called every time rendering on the given planes has
9071 * completed and frontbuffer caching can be started again. Flushes will get
9072 * delayed if they're blocked by some oustanding asynchronous rendering.
9073 *
9074 * Can be called without any locks held.
9075 */
9076 void intel_frontbuffer_flush(struct drm_device *dev,
9077 unsigned frontbuffer_bits)
9078 {
9079 struct drm_i915_private *dev_priv = dev->dev_private;
9080
9081 /* Delay flushing when rings are still busy.*/
9082 mutex_lock(&dev_priv->fb_tracking.lock);
9083 frontbuffer_bits &= ~dev_priv->fb_tracking.busy_bits;
9084 mutex_unlock(&dev_priv->fb_tracking.lock);
9085
9086 intel_mark_fb_busy(dev, frontbuffer_bits, NULL);
9087
9088 intel_edp_psr_flush(dev, frontbuffer_bits);
9089
9090 if (IS_GEN8(dev))
9091 gen8_fbc_sw_flush(dev, FBC_REND_CACHE_CLEAN);
9092 }
9093
9094 /**
9095 * intel_fb_obj_flush - flush frontbuffer object
9096 * @obj: GEM object to flush
9097 * @retire: set when retiring asynchronous rendering
9098 *
9099 * This function gets called every time rendering on the given object has
9100 * completed and frontbuffer caching can be started again. If @retire is true
9101 * then any delayed flushes will be unblocked.
9102 */
9103 void intel_fb_obj_flush(struct drm_i915_gem_object *obj,
9104 bool retire)
9105 {
9106 struct drm_device *dev = obj->base.dev;
9107 struct drm_i915_private *dev_priv = dev->dev_private;
9108 unsigned frontbuffer_bits;
9109
9110 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
9111
9112 if (!obj->frontbuffer_bits)
9113 return;
9114
9115 frontbuffer_bits = obj->frontbuffer_bits;
9116
9117 if (retire) {
9118 mutex_lock(&dev_priv->fb_tracking.lock);
9119 /* Filter out new bits since rendering started. */
9120 frontbuffer_bits &= dev_priv->fb_tracking.busy_bits;
9121
9122 dev_priv->fb_tracking.busy_bits &= ~frontbuffer_bits;
9123 mutex_unlock(&dev_priv->fb_tracking.lock);
9124 }
9125
9126 intel_frontbuffer_flush(dev, frontbuffer_bits);
9127 }
9128
9129 /**
9130 * intel_frontbuffer_flip_prepare - prepare asnychronous frontbuffer flip
9131 * @dev: DRM device
9132 * @frontbuffer_bits: frontbuffer plane tracking bits
9133 *
9134 * This function gets called after scheduling a flip on @obj. The actual
9135 * frontbuffer flushing will be delayed until completion is signalled with
9136 * intel_frontbuffer_flip_complete. If an invalidate happens in between this
9137 * flush will be cancelled.
9138 *
9139 * Can be called without any locks held.
9140 */
9141 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
9142 unsigned frontbuffer_bits)
9143 {
9144 struct drm_i915_private *dev_priv = dev->dev_private;
9145
9146 mutex_lock(&dev_priv->fb_tracking.lock);
9147 dev_priv->fb_tracking.flip_bits
9148 |= frontbuffer_bits;
9149 mutex_unlock(&dev_priv->fb_tracking.lock);
9150 }
9151
9152 /**
9153 * intel_frontbuffer_flip_complete - complete asynchronous frontbuffer flush
9154 * @dev: DRM device
9155 * @frontbuffer_bits: frontbuffer plane tracking bits
9156 *
9157 * This function gets called after the flip has been latched and will complete
9158 * on the next vblank. It will execute the fush if it hasn't been cancalled yet.
9159 *
9160 * Can be called without any locks held.
9161 */
9162 void intel_frontbuffer_flip_complete(struct drm_device *dev,
9163 unsigned frontbuffer_bits)
9164 {
9165 struct drm_i915_private *dev_priv = dev->dev_private;
9166
9167 mutex_lock(&dev_priv->fb_tracking.lock);
9168 /* Mask any cancelled flips. */
9169 frontbuffer_bits &= dev_priv->fb_tracking.flip_bits;
9170 dev_priv->fb_tracking.flip_bits &= ~frontbuffer_bits;
9171 mutex_unlock(&dev_priv->fb_tracking.lock);
9172
9173 intel_frontbuffer_flush(dev, frontbuffer_bits);
9174 }
9175
9176 static void intel_crtc_destroy(struct drm_crtc *crtc)
9177 {
9178 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9179 struct drm_device *dev = crtc->dev;
9180 struct intel_unpin_work *work;
9181 unsigned long flags;
9182
9183 spin_lock_irqsave(&dev->event_lock, flags);
9184 work = intel_crtc->unpin_work;
9185 intel_crtc->unpin_work = NULL;
9186 spin_unlock_irqrestore(&dev->event_lock, flags);
9187
9188 if (work) {
9189 cancel_work_sync(&work->work);
9190 kfree(work);
9191 }
9192
9193 drm_crtc_cleanup(crtc);
9194
9195 kfree(intel_crtc);
9196 }
9197
9198 static void intel_unpin_work_fn(struct work_struct *__work)
9199 {
9200 struct intel_unpin_work *work =
9201 container_of(__work, struct intel_unpin_work, work);
9202 struct drm_device *dev = work->crtc->dev;
9203 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9204
9205 mutex_lock(&dev->struct_mutex);
9206 intel_unpin_fb_obj(work->old_fb_obj);
9207 drm_gem_object_unreference(&work->pending_flip_obj->base);
9208 drm_gem_object_unreference(&work->old_fb_obj->base);
9209
9210 intel_update_fbc(dev);
9211 mutex_unlock(&dev->struct_mutex);
9212
9213 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9214
9215 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9216 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9217
9218 kfree(work);
9219 }
9220
9221 static void do_intel_finish_page_flip(struct drm_device *dev,
9222 struct drm_crtc *crtc)
9223 {
9224 struct drm_i915_private *dev_priv = dev->dev_private;
9225 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9226 struct intel_unpin_work *work;
9227 unsigned long flags;
9228
9229 /* Ignore early vblank irqs */
9230 if (intel_crtc == NULL)
9231 return;
9232
9233 spin_lock_irqsave(&dev->event_lock, flags);
9234 work = intel_crtc->unpin_work;
9235
9236 /* Ensure we don't miss a work->pending update ... */
9237 smp_rmb();
9238
9239 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9240 spin_unlock_irqrestore(&dev->event_lock, flags);
9241 return;
9242 }
9243
9244 /* and that the unpin work is consistent wrt ->pending. */
9245 smp_rmb();
9246
9247 intel_crtc->unpin_work = NULL;
9248
9249 if (work->event)
9250 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
9251
9252 drm_crtc_vblank_put(crtc);
9253
9254 spin_unlock_irqrestore(&dev->event_lock, flags);
9255
9256 wake_up_all(&dev_priv->pending_flip_queue);
9257
9258 queue_work(dev_priv->wq, &work->work);
9259
9260 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
9261 }
9262
9263 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9264 {
9265 struct drm_i915_private *dev_priv = dev->dev_private;
9266 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9267
9268 do_intel_finish_page_flip(dev, crtc);
9269 }
9270
9271 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9272 {
9273 struct drm_i915_private *dev_priv = dev->dev_private;
9274 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9275
9276 do_intel_finish_page_flip(dev, crtc);
9277 }
9278
9279 /* Is 'a' after or equal to 'b'? */
9280 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9281 {
9282 return !((a - b) & 0x80000000);
9283 }
9284
9285 static bool page_flip_finished(struct intel_crtc *crtc)
9286 {
9287 struct drm_device *dev = crtc->base.dev;
9288 struct drm_i915_private *dev_priv = dev->dev_private;
9289
9290 /*
9291 * The relevant registers doen't exist on pre-ctg.
9292 * As the flip done interrupt doesn't trigger for mmio
9293 * flips on gmch platforms, a flip count check isn't
9294 * really needed there. But since ctg has the registers,
9295 * include it in the check anyway.
9296 */
9297 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9298 return true;
9299
9300 /*
9301 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9302 * used the same base address. In that case the mmio flip might
9303 * have completed, but the CS hasn't even executed the flip yet.
9304 *
9305 * A flip count check isn't enough as the CS might have updated
9306 * the base address just after start of vblank, but before we
9307 * managed to process the interrupt. This means we'd complete the
9308 * CS flip too soon.
9309 *
9310 * Combining both checks should get us a good enough result. It may
9311 * still happen that the CS flip has been executed, but has not
9312 * yet actually completed. But in case the base address is the same
9313 * anyway, we don't really care.
9314 */
9315 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9316 crtc->unpin_work->gtt_offset &&
9317 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9318 crtc->unpin_work->flip_count);
9319 }
9320
9321 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9322 {
9323 struct drm_i915_private *dev_priv = dev->dev_private;
9324 struct intel_crtc *intel_crtc =
9325 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9326 unsigned long flags;
9327
9328 /* NB: An MMIO update of the plane base pointer will also
9329 * generate a page-flip completion irq, i.e. every modeset
9330 * is also accompanied by a spurious intel_prepare_page_flip().
9331 */
9332 spin_lock_irqsave(&dev->event_lock, flags);
9333 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9334 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9335 spin_unlock_irqrestore(&dev->event_lock, flags);
9336 }
9337
9338 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9339 {
9340 /* Ensure that the work item is consistent when activating it ... */
9341 smp_wmb();
9342 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9343 /* and that it is marked active as soon as the irq could fire. */
9344 smp_wmb();
9345 }
9346
9347 static int intel_gen2_queue_flip(struct drm_device *dev,
9348 struct drm_crtc *crtc,
9349 struct drm_framebuffer *fb,
9350 struct drm_i915_gem_object *obj,
9351 struct intel_engine_cs *ring,
9352 uint32_t flags)
9353 {
9354 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9355 u32 flip_mask;
9356 int ret;
9357
9358 ret = intel_ring_begin(ring, 6);
9359 if (ret)
9360 return ret;
9361
9362 /* Can't queue multiple flips, so wait for the previous
9363 * one to finish before executing the next.
9364 */
9365 if (intel_crtc->plane)
9366 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9367 else
9368 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9369 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9370 intel_ring_emit(ring, MI_NOOP);
9371 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9372 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9373 intel_ring_emit(ring, fb->pitches[0]);
9374 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9375 intel_ring_emit(ring, 0); /* aux display base address, unused */
9376
9377 intel_mark_page_flip_active(intel_crtc);
9378 __intel_ring_advance(ring);
9379 return 0;
9380 }
9381
9382 static int intel_gen3_queue_flip(struct drm_device *dev,
9383 struct drm_crtc *crtc,
9384 struct drm_framebuffer *fb,
9385 struct drm_i915_gem_object *obj,
9386 struct intel_engine_cs *ring,
9387 uint32_t flags)
9388 {
9389 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9390 u32 flip_mask;
9391 int ret;
9392
9393 ret = intel_ring_begin(ring, 6);
9394 if (ret)
9395 return ret;
9396
9397 if (intel_crtc->plane)
9398 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9399 else
9400 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9401 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9402 intel_ring_emit(ring, MI_NOOP);
9403 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9404 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9405 intel_ring_emit(ring, fb->pitches[0]);
9406 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9407 intel_ring_emit(ring, MI_NOOP);
9408
9409 intel_mark_page_flip_active(intel_crtc);
9410 __intel_ring_advance(ring);
9411 return 0;
9412 }
9413
9414 static int intel_gen4_queue_flip(struct drm_device *dev,
9415 struct drm_crtc *crtc,
9416 struct drm_framebuffer *fb,
9417 struct drm_i915_gem_object *obj,
9418 struct intel_engine_cs *ring,
9419 uint32_t flags)
9420 {
9421 struct drm_i915_private *dev_priv = dev->dev_private;
9422 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9423 uint32_t pf, pipesrc;
9424 int ret;
9425
9426 ret = intel_ring_begin(ring, 4);
9427 if (ret)
9428 return ret;
9429
9430 /* i965+ uses the linear or tiled offsets from the
9431 * Display Registers (which do not change across a page-flip)
9432 * so we need only reprogram the base address.
9433 */
9434 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9435 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9436 intel_ring_emit(ring, fb->pitches[0]);
9437 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9438 obj->tiling_mode);
9439
9440 /* XXX Enabling the panel-fitter across page-flip is so far
9441 * untested on non-native modes, so ignore it for now.
9442 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9443 */
9444 pf = 0;
9445 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9446 intel_ring_emit(ring, pf | pipesrc);
9447
9448 intel_mark_page_flip_active(intel_crtc);
9449 __intel_ring_advance(ring);
9450 return 0;
9451 }
9452
9453 static int intel_gen6_queue_flip(struct drm_device *dev,
9454 struct drm_crtc *crtc,
9455 struct drm_framebuffer *fb,
9456 struct drm_i915_gem_object *obj,
9457 struct intel_engine_cs *ring,
9458 uint32_t flags)
9459 {
9460 struct drm_i915_private *dev_priv = dev->dev_private;
9461 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9462 uint32_t pf, pipesrc;
9463 int ret;
9464
9465 ret = intel_ring_begin(ring, 4);
9466 if (ret)
9467 return ret;
9468
9469 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9470 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9471 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9472 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9473
9474 /* Contrary to the suggestions in the documentation,
9475 * "Enable Panel Fitter" does not seem to be required when page
9476 * flipping with a non-native mode, and worse causes a normal
9477 * modeset to fail.
9478 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9479 */
9480 pf = 0;
9481 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9482 intel_ring_emit(ring, pf | pipesrc);
9483
9484 intel_mark_page_flip_active(intel_crtc);
9485 __intel_ring_advance(ring);
9486 return 0;
9487 }
9488
9489 static int intel_gen7_queue_flip(struct drm_device *dev,
9490 struct drm_crtc *crtc,
9491 struct drm_framebuffer *fb,
9492 struct drm_i915_gem_object *obj,
9493 struct intel_engine_cs *ring,
9494 uint32_t flags)
9495 {
9496 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9497 uint32_t plane_bit = 0;
9498 int len, ret;
9499
9500 switch (intel_crtc->plane) {
9501 case PLANE_A:
9502 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9503 break;
9504 case PLANE_B:
9505 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9506 break;
9507 case PLANE_C:
9508 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9509 break;
9510 default:
9511 WARN_ONCE(1, "unknown plane in flip command\n");
9512 return -ENODEV;
9513 }
9514
9515 len = 4;
9516 if (ring->id == RCS) {
9517 len += 6;
9518 /*
9519 * On Gen 8, SRM is now taking an extra dword to accommodate
9520 * 48bits addresses, and we need a NOOP for the batch size to
9521 * stay even.
9522 */
9523 if (IS_GEN8(dev))
9524 len += 2;
9525 }
9526
9527 /*
9528 * BSpec MI_DISPLAY_FLIP for IVB:
9529 * "The full packet must be contained within the same cache line."
9530 *
9531 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9532 * cacheline, if we ever start emitting more commands before
9533 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9534 * then do the cacheline alignment, and finally emit the
9535 * MI_DISPLAY_FLIP.
9536 */
9537 ret = intel_ring_cacheline_align(ring);
9538 if (ret)
9539 return ret;
9540
9541 ret = intel_ring_begin(ring, len);
9542 if (ret)
9543 return ret;
9544
9545 /* Unmask the flip-done completion message. Note that the bspec says that
9546 * we should do this for both the BCS and RCS, and that we must not unmask
9547 * more than one flip event at any time (or ensure that one flip message
9548 * can be sent by waiting for flip-done prior to queueing new flips).
9549 * Experimentation says that BCS works despite DERRMR masking all
9550 * flip-done completion events and that unmasking all planes at once
9551 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9552 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9553 */
9554 if (ring->id == RCS) {
9555 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9556 intel_ring_emit(ring, DERRMR);
9557 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9558 DERRMR_PIPEB_PRI_FLIP_DONE |
9559 DERRMR_PIPEC_PRI_FLIP_DONE));
9560 if (IS_GEN8(dev))
9561 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9562 MI_SRM_LRM_GLOBAL_GTT);
9563 else
9564 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9565 MI_SRM_LRM_GLOBAL_GTT);
9566 intel_ring_emit(ring, DERRMR);
9567 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9568 if (IS_GEN8(dev)) {
9569 intel_ring_emit(ring, 0);
9570 intel_ring_emit(ring, MI_NOOP);
9571 }
9572 }
9573
9574 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9575 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9576 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9577 intel_ring_emit(ring, (MI_NOOP));
9578
9579 intel_mark_page_flip_active(intel_crtc);
9580 __intel_ring_advance(ring);
9581 return 0;
9582 }
9583
9584 static bool use_mmio_flip(struct intel_engine_cs *ring,
9585 struct drm_i915_gem_object *obj)
9586 {
9587 /*
9588 * This is not being used for older platforms, because
9589 * non-availability of flip done interrupt forces us to use
9590 * CS flips. Older platforms derive flip done using some clever
9591 * tricks involving the flip_pending status bits and vblank irqs.
9592 * So using MMIO flips there would disrupt this mechanism.
9593 */
9594
9595 if (ring == NULL)
9596 return true;
9597
9598 if (INTEL_INFO(ring->dev)->gen < 5)
9599 return false;
9600
9601 if (i915.use_mmio_flip < 0)
9602 return false;
9603 else if (i915.use_mmio_flip > 0)
9604 return true;
9605 else if (i915.enable_execlists)
9606 return true;
9607 else
9608 return ring != obj->ring;
9609 }
9610
9611 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9612 {
9613 struct drm_device *dev = intel_crtc->base.dev;
9614 struct drm_i915_private *dev_priv = dev->dev_private;
9615 struct intel_framebuffer *intel_fb =
9616 to_intel_framebuffer(intel_crtc->base.primary->fb);
9617 struct drm_i915_gem_object *obj = intel_fb->obj;
9618 u32 dspcntr;
9619 u32 reg;
9620
9621 intel_mark_page_flip_active(intel_crtc);
9622
9623 reg = DSPCNTR(intel_crtc->plane);
9624 dspcntr = I915_READ(reg);
9625
9626 if (INTEL_INFO(dev)->gen >= 4) {
9627 if (obj->tiling_mode != I915_TILING_NONE)
9628 dspcntr |= DISPPLANE_TILED;
9629 else
9630 dspcntr &= ~DISPPLANE_TILED;
9631 }
9632 I915_WRITE(reg, dspcntr);
9633
9634 I915_WRITE(DSPSURF(intel_crtc->plane),
9635 intel_crtc->unpin_work->gtt_offset);
9636 POSTING_READ(DSPSURF(intel_crtc->plane));
9637 }
9638
9639 static int intel_postpone_flip(struct drm_i915_gem_object *obj)
9640 {
9641 struct intel_engine_cs *ring;
9642 int ret;
9643
9644 lockdep_assert_held(&obj->base.dev->struct_mutex);
9645
9646 if (!obj->last_write_seqno)
9647 return 0;
9648
9649 ring = obj->ring;
9650
9651 if (i915_seqno_passed(ring->get_seqno(ring, true),
9652 obj->last_write_seqno))
9653 return 0;
9654
9655 ret = i915_gem_check_olr(ring, obj->last_write_seqno);
9656 if (ret)
9657 return ret;
9658
9659 if (WARN_ON(!ring->irq_get(ring)))
9660 return 0;
9661
9662 return 1;
9663 }
9664
9665 void intel_notify_mmio_flip(struct intel_engine_cs *ring)
9666 {
9667 struct drm_i915_private *dev_priv = to_i915(ring->dev);
9668 struct intel_crtc *intel_crtc;
9669 unsigned long irq_flags;
9670 u32 seqno;
9671
9672 seqno = ring->get_seqno(ring, false);
9673
9674 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9675 for_each_intel_crtc(ring->dev, intel_crtc) {
9676 struct intel_mmio_flip *mmio_flip;
9677
9678 mmio_flip = &intel_crtc->mmio_flip;
9679 if (mmio_flip->seqno == 0)
9680 continue;
9681
9682 if (ring->id != mmio_flip->ring_id)
9683 continue;
9684
9685 if (i915_seqno_passed(seqno, mmio_flip->seqno)) {
9686 intel_do_mmio_flip(intel_crtc);
9687 mmio_flip->seqno = 0;
9688 ring->irq_put(ring);
9689 }
9690 }
9691 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9692 }
9693
9694 static int intel_queue_mmio_flip(struct drm_device *dev,
9695 struct drm_crtc *crtc,
9696 struct drm_framebuffer *fb,
9697 struct drm_i915_gem_object *obj,
9698 struct intel_engine_cs *ring,
9699 uint32_t flags)
9700 {
9701 struct drm_i915_private *dev_priv = dev->dev_private;
9702 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9703 unsigned long irq_flags;
9704 int ret;
9705
9706 if (WARN_ON(intel_crtc->mmio_flip.seqno))
9707 return -EBUSY;
9708
9709 ret = intel_postpone_flip(obj);
9710 if (ret < 0)
9711 return ret;
9712 if (ret == 0) {
9713 intel_do_mmio_flip(intel_crtc);
9714 return 0;
9715 }
9716
9717 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9718 intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
9719 intel_crtc->mmio_flip.ring_id = obj->ring->id;
9720 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9721
9722 /*
9723 * Double check to catch cases where irq fired before
9724 * mmio flip data was ready
9725 */
9726 intel_notify_mmio_flip(obj->ring);
9727 return 0;
9728 }
9729
9730 static int intel_default_queue_flip(struct drm_device *dev,
9731 struct drm_crtc *crtc,
9732 struct drm_framebuffer *fb,
9733 struct drm_i915_gem_object *obj,
9734 struct intel_engine_cs *ring,
9735 uint32_t flags)
9736 {
9737 return -ENODEV;
9738 }
9739
9740 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9741 struct drm_framebuffer *fb,
9742 struct drm_pending_vblank_event *event,
9743 uint32_t page_flip_flags)
9744 {
9745 struct drm_device *dev = crtc->dev;
9746 struct drm_i915_private *dev_priv = dev->dev_private;
9747 struct drm_framebuffer *old_fb = crtc->primary->fb;
9748 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9749 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9750 enum pipe pipe = intel_crtc->pipe;
9751 struct intel_unpin_work *work;
9752 struct intel_engine_cs *ring;
9753 unsigned long flags;
9754 int ret;
9755
9756 //trigger software GT busyness calculation
9757 gen8_flip_interrupt(dev);
9758
9759 /*
9760 * drm_mode_page_flip_ioctl() should already catch this, but double
9761 * check to be safe. In the future we may enable pageflipping from
9762 * a disabled primary plane.
9763 */
9764 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9765 return -EBUSY;
9766
9767 /* Can't change pixel format via MI display flips. */
9768 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9769 return -EINVAL;
9770
9771 /*
9772 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9773 * Note that pitch changes could also affect these register.
9774 */
9775 if (INTEL_INFO(dev)->gen > 3 &&
9776 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9777 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9778 return -EINVAL;
9779
9780 if (i915_terminally_wedged(&dev_priv->gpu_error))
9781 goto out_hang;
9782
9783 work = kzalloc(sizeof(*work), GFP_KERNEL);
9784 if (work == NULL)
9785 return -ENOMEM;
9786
9787 work->event = event;
9788 work->crtc = crtc;
9789 work->old_fb_obj = intel_fb_obj(old_fb);
9790 INIT_WORK(&work->work, intel_unpin_work_fn);
9791
9792 ret = drm_crtc_vblank_get(crtc);
9793 if (ret)
9794 goto free_work;
9795
9796 /* We borrow the event spin lock for protecting unpin_work */
9797 spin_lock_irqsave(&dev->event_lock, flags);
9798 if (intel_crtc->unpin_work) {
9799 spin_unlock_irqrestore(&dev->event_lock, flags);
9800 kfree(work);
9801 drm_crtc_vblank_put(crtc);
9802
9803 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9804 return -EBUSY;
9805 }
9806 intel_crtc->unpin_work = work;
9807 spin_unlock_irqrestore(&dev->event_lock, flags);
9808
9809 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9810 flush_workqueue(dev_priv->wq);
9811
9812 ret = i915_mutex_lock_interruptible(dev);
9813 if (ret)
9814 goto cleanup;
9815
9816 /* Reference the objects for the scheduled work. */
9817 drm_gem_object_reference(&work->old_fb_obj->base);
9818 drm_gem_object_reference(&obj->base);
9819
9820 crtc->primary->fb = fb;
9821
9822 work->pending_flip_obj = obj;
9823
9824 work->enable_stall_check = true;
9825
9826 atomic_inc(&intel_crtc->unpin_work_count);
9827 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9828
9829 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9830 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9831
9832 if (IS_VALLEYVIEW(dev)) {
9833 ring = &dev_priv->ring[BCS];
9834 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9835 /* vlv: DISPLAY_FLIP fails to change tiling */
9836 ring = NULL;
9837 } else if (IS_IVYBRIDGE(dev)) {
9838 ring = &dev_priv->ring[BCS];
9839 } else if (INTEL_INFO(dev)->gen >= 7) {
9840 ring = obj->ring;
9841 if (ring == NULL || ring->id != RCS)
9842 ring = &dev_priv->ring[BCS];
9843 } else {
9844 ring = &dev_priv->ring[RCS];
9845 }
9846
9847 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9848 if (ret)
9849 goto cleanup_pending;
9850
9851 work->gtt_offset =
9852 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9853
9854 if (use_mmio_flip(ring, obj))
9855 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9856 page_flip_flags);
9857 else
9858 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9859 page_flip_flags);
9860 if (ret)
9861 goto cleanup_unpin;
9862
9863 i915_gem_track_fb(work->old_fb_obj, obj,
9864 INTEL_FRONTBUFFER_PRIMARY(pipe));
9865
9866 intel_disable_fbc(dev);
9867 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9868 mutex_unlock(&dev->struct_mutex);
9869
9870 trace_i915_flip_request(intel_crtc->plane, obj);
9871
9872 return 0;
9873
9874 cleanup_unpin:
9875 intel_unpin_fb_obj(obj);
9876 cleanup_pending:
9877 atomic_dec(&intel_crtc->unpin_work_count);
9878 crtc->primary->fb = old_fb;
9879 drm_gem_object_unreference(&work->old_fb_obj->base);
9880 drm_gem_object_unreference(&obj->base);
9881 mutex_unlock(&dev->struct_mutex);
9882
9883 cleanup:
9884 spin_lock_irqsave(&dev->event_lock, flags);
9885 intel_crtc->unpin_work = NULL;
9886 spin_unlock_irqrestore(&dev->event_lock, flags);
9887
9888 drm_crtc_vblank_put(crtc);
9889 free_work:
9890 kfree(work);
9891
9892 if (ret == -EIO) {
9893 out_hang:
9894 intel_crtc_wait_for_pending_flips(crtc);
9895 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9896 if (ret == 0 && event)
9897 drm_send_vblank_event(dev, pipe, event);
9898 }
9899 return ret;
9900 }
9901
9902 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9903 .mode_set_base_atomic = intel_pipe_set_base_atomic,
9904 .load_lut = intel_crtc_load_lut,
9905 };
9906
9907 /**
9908 * intel_modeset_update_staged_output_state
9909 *
9910 * Updates the staged output configuration state, e.g. after we've read out the
9911 * current hw state.
9912 */
9913 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9914 {
9915 struct intel_crtc *crtc;
9916 struct intel_encoder *encoder;
9917 struct intel_connector *connector;
9918
9919 list_for_each_entry(connector, &dev->mode_config.connector_list,
9920 base.head) {
9921 connector->new_encoder =
9922 to_intel_encoder(connector->base.encoder);
9923 }
9924
9925 for_each_intel_encoder(dev, encoder) {
9926 encoder->new_crtc =
9927 to_intel_crtc(encoder->base.crtc);
9928 }
9929
9930 for_each_intel_crtc(dev, crtc) {
9931 crtc->new_enabled = crtc->base.enabled;
9932
9933 if (crtc->new_enabled)
9934 crtc->new_config = &crtc->config;
9935 else
9936 crtc->new_config = NULL;
9937 }
9938 }
9939
9940 /**
9941 * intel_modeset_commit_output_state
9942 *
9943 * This function copies the stage display pipe configuration to the real one.
9944 */
9945 static void intel_modeset_commit_output_state(struct drm_device *dev)
9946 {
9947 struct intel_crtc *crtc;
9948 struct intel_encoder *encoder;
9949 struct intel_connector *connector;
9950
9951 list_for_each_entry(connector, &dev->mode_config.connector_list,
9952 base.head) {
9953 connector->base.encoder = &connector->new_encoder->base;
9954 }
9955
9956 for_each_intel_encoder(dev, encoder) {
9957 encoder->base.crtc = &encoder->new_crtc->base;
9958 }
9959
9960 for_each_intel_crtc(dev, crtc) {
9961 crtc->base.enabled = crtc->new_enabled;
9962 }
9963 }
9964
9965 static void
9966 connected_sink_compute_bpp(struct intel_connector *connector,
9967 struct intel_crtc_config *pipe_config)
9968 {
9969 int bpp = pipe_config->pipe_bpp;
9970
9971 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9972 connector->base.base.id,
9973 connector->base.name);
9974
9975 /* Don't use an invalid EDID bpc value */
9976 if (connector->base.display_info.bpc &&
9977 connector->base.display_info.bpc * 3 < bpp) {
9978 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9979 bpp, connector->base.display_info.bpc*3);
9980 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9981 }
9982
9983 /* Clamp bpp to 8 on screens without EDID 1.4 */
9984 if (connector->base.display_info.bpc == 0 && bpp > 24) {
9985 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9986 bpp);
9987 pipe_config->pipe_bpp = 24;
9988 }
9989 }
9990
9991 static int
9992 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9993 struct drm_framebuffer *fb,
9994 struct intel_crtc_config *pipe_config)
9995 {
9996 struct drm_device *dev = crtc->base.dev;
9997 struct intel_connector *connector;
9998 int bpp;
9999
10000 switch (fb->pixel_format) {
10001 case DRM_FORMAT_C8:
10002 bpp = 8*3; /* since we go through a colormap */
10003 break;
10004 case DRM_FORMAT_XRGB1555:
10005 case DRM_FORMAT_ARGB1555:
10006 /* checked in intel_framebuffer_init already */
10007 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10008 return -EINVAL;
10009 case DRM_FORMAT_RGB565:
10010 bpp = 6*3; /* min is 18bpp */
10011 break;
10012 case DRM_FORMAT_XBGR8888:
10013 case DRM_FORMAT_ABGR8888:
10014 /* checked in intel_framebuffer_init already */
10015 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10016 return -EINVAL;
10017 case DRM_FORMAT_XRGB8888:
10018 case DRM_FORMAT_ARGB8888:
10019 bpp = 8*3;
10020 break;
10021 case DRM_FORMAT_XRGB2101010:
10022 case DRM_FORMAT_ARGB2101010:
10023 case DRM_FORMAT_XBGR2101010:
10024 case DRM_FORMAT_ABGR2101010:
10025 /* checked in intel_framebuffer_init already */
10026 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10027 return -EINVAL;
10028 bpp = 10*3;
10029 break;
10030 /* TODO: gen4+ supports 16 bpc floating point, too. */
10031 default:
10032 DRM_DEBUG_KMS("unsupported depth\n");
10033 return -EINVAL;
10034 }
10035
10036 pipe_config->pipe_bpp = bpp;
10037
10038 /* Clamp display bpp to EDID value */
10039 list_for_each_entry(connector, &dev->mode_config.connector_list,
10040 base.head) {
10041 if (!connector->new_encoder ||
10042 connector->new_encoder->new_crtc != crtc)
10043 continue;
10044
10045 connected_sink_compute_bpp(connector, pipe_config);
10046 }
10047
10048 return bpp;
10049 }
10050
10051 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10052 {
10053 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10054 "type: 0x%x flags: 0x%x\n",
10055 mode->crtc_clock,
10056 mode->crtc_hdisplay, mode->crtc_hsync_start,
10057 mode->crtc_hsync_end, mode->crtc_htotal,
10058 mode->crtc_vdisplay, mode->crtc_vsync_start,
10059 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10060 }
10061
10062 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10063 struct intel_crtc_config *pipe_config,
10064 const char *context)
10065 {
10066 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10067 context, pipe_name(crtc->pipe));
10068
10069 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10070 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10071 pipe_config->pipe_bpp, pipe_config->dither);
10072 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10073 pipe_config->has_pch_encoder,
10074 pipe_config->fdi_lanes,
10075 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10076 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10077 pipe_config->fdi_m_n.tu);
10078 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10079 pipe_config->has_dp_encoder,
10080 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10081 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10082 pipe_config->dp_m_n.tu);
10083
10084 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10085 pipe_config->has_dp_encoder,
10086 pipe_config->dp_m2_n2.gmch_m,
10087 pipe_config->dp_m2_n2.gmch_n,
10088 pipe_config->dp_m2_n2.link_m,
10089 pipe_config->dp_m2_n2.link_n,
10090 pipe_config->dp_m2_n2.tu);
10091
10092 DRM_DEBUG_KMS("requested mode:\n");
10093 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
10094 DRM_DEBUG_KMS("adjusted mode:\n");
10095 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
10096 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
10097 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10098 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10099 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10100 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10101 pipe_config->gmch_pfit.control,
10102 pipe_config->gmch_pfit.pgm_ratios,
10103 pipe_config->gmch_pfit.lvds_border_bits);
10104 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10105 pipe_config->pch_pfit.pos,
10106 pipe_config->pch_pfit.size,
10107 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10108 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10109 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10110 }
10111
10112 static bool encoders_cloneable(const struct intel_encoder *a,
10113 const struct intel_encoder *b)
10114 {
10115 /* masks could be asymmetric, so check both ways */
10116 return a == b || (a->cloneable & (1 << b->type) &&
10117 b->cloneable & (1 << a->type));
10118 }
10119
10120 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10121 struct intel_encoder *encoder)
10122 {
10123 struct drm_device *dev = crtc->base.dev;
10124 struct intel_encoder *source_encoder;
10125
10126 for_each_intel_encoder(dev, source_encoder) {
10127 if (source_encoder->new_crtc != crtc)
10128 continue;
10129
10130 if (!encoders_cloneable(encoder, source_encoder))
10131 return false;
10132 }
10133
10134 return true;
10135 }
10136
10137 static bool check_encoder_cloning(struct intel_crtc *crtc)
10138 {
10139 struct drm_device *dev = crtc->base.dev;
10140 struct intel_encoder *encoder;
10141
10142 for_each_intel_encoder(dev, encoder) {
10143 if (encoder->new_crtc != crtc)
10144 continue;
10145
10146 if (!check_single_encoder_cloning(crtc, encoder))
10147 return false;
10148 }
10149
10150 return true;
10151 }
10152
10153 static struct intel_crtc_config *
10154 intel_modeset_pipe_config(struct drm_crtc *crtc,
10155 struct drm_framebuffer *fb,
10156 struct drm_display_mode *mode)
10157 {
10158 struct drm_device *dev = crtc->dev;
10159 struct intel_encoder *encoder;
10160 struct intel_crtc_config *pipe_config;
10161 int plane_bpp, ret = -EINVAL;
10162 bool retry = true;
10163
10164 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10165 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10166 return ERR_PTR(-EINVAL);
10167 }
10168
10169 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10170 if (!pipe_config)
10171 return ERR_PTR(-ENOMEM);
10172
10173 drm_mode_copy(&pipe_config->adjusted_mode, mode);
10174 drm_mode_copy(&pipe_config->requested_mode, mode);
10175
10176 pipe_config->cpu_transcoder =
10177 (enum transcoder) to_intel_crtc(crtc)->pipe;
10178 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10179
10180 /*
10181 * Sanitize sync polarity flags based on requested ones. If neither
10182 * positive or negative polarity is requested, treat this as meaning
10183 * negative polarity.
10184 */
10185 if (!(pipe_config->adjusted_mode.flags &
10186 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10187 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10188
10189 if (!(pipe_config->adjusted_mode.flags &
10190 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10191 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10192
10193 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10194 * plane pixel format and any sink constraints into account. Returns the
10195 * source plane bpp so that dithering can be selected on mismatches
10196 * after encoders and crtc also have had their say. */
10197 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10198 fb, pipe_config);
10199 if (plane_bpp < 0)
10200 goto fail;
10201
10202 /*
10203 * Determine the real pipe dimensions. Note that stereo modes can
10204 * increase the actual pipe size due to the frame doubling and
10205 * insertion of additional space for blanks between the frame. This
10206 * is stored in the crtc timings. We use the requested mode to do this
10207 * computation to clearly distinguish it from the adjusted mode, which
10208 * can be changed by the connectors in the below retry loop.
10209 */
10210 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
10211 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
10212 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
10213
10214 encoder_retry:
10215 /* Ensure the port clock defaults are reset when retrying. */
10216 pipe_config->port_clock = 0;
10217 pipe_config->pixel_multiplier = 1;
10218
10219 /* Fill in default crtc timings, allow encoders to overwrite them. */
10220 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
10221
10222 /* Pass our mode to the connectors and the CRTC to give them a chance to
10223 * adjust it according to limitations or connector properties, and also
10224 * a chance to reject the mode entirely.
10225 */
10226 for_each_intel_encoder(dev, encoder) {
10227
10228 if (&encoder->new_crtc->base != crtc)
10229 continue;
10230
10231 if (!(encoder->compute_config(encoder, pipe_config))) {
10232 DRM_DEBUG_KMS("Encoder config failure\n");
10233 goto fail;
10234 }
10235 }
10236
10237 /* Set default port clock if not overwritten by the encoder. Needs to be
10238 * done afterwards in case the encoder adjusts the mode. */
10239 if (!pipe_config->port_clock)
10240 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10241 * pipe_config->pixel_multiplier;
10242
10243 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10244 if (ret < 0) {
10245 DRM_DEBUG_KMS("CRTC fixup failed\n");
10246 goto fail;
10247 }
10248
10249 if (ret == RETRY) {
10250 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10251 ret = -EINVAL;
10252 goto fail;
10253 }
10254
10255 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10256 retry = false;
10257 goto encoder_retry;
10258 }
10259
10260 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10261 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10262 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10263
10264 return pipe_config;
10265 fail:
10266 kfree(pipe_config);
10267 return ERR_PTR(ret);
10268 }
10269
10270 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10271 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10272 static void
10273 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10274 unsigned *prepare_pipes, unsigned *disable_pipes)
10275 {
10276 struct intel_crtc *intel_crtc;
10277 struct drm_device *dev = crtc->dev;
10278 struct intel_encoder *encoder;
10279 struct intel_connector *connector;
10280 struct drm_crtc *tmp_crtc;
10281
10282 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10283
10284 /* Check which crtcs have changed outputs connected to them, these need
10285 * to be part of the prepare_pipes mask. We don't (yet) support global
10286 * modeset across multiple crtcs, so modeset_pipes will only have one
10287 * bit set at most. */
10288 list_for_each_entry(connector, &dev->mode_config.connector_list,
10289 base.head) {
10290 if (connector->base.encoder == &connector->new_encoder->base)
10291 continue;
10292
10293 if (connector->base.encoder) {
10294 tmp_crtc = connector->base.encoder->crtc;
10295
10296 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10297 }
10298
10299 if (connector->new_encoder)
10300 *prepare_pipes |=
10301 1 << connector->new_encoder->new_crtc->pipe;
10302 }
10303
10304 for_each_intel_encoder(dev, encoder) {
10305 if (encoder->base.crtc == &encoder->new_crtc->base)
10306 continue;
10307
10308 if (encoder->base.crtc) {
10309 tmp_crtc = encoder->base.crtc;
10310
10311 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10312 }
10313
10314 if (encoder->new_crtc)
10315 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10316 }
10317
10318 /* Check for pipes that will be enabled/disabled ... */
10319 for_each_intel_crtc(dev, intel_crtc) {
10320 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10321 continue;
10322
10323 if (!intel_crtc->new_enabled)
10324 *disable_pipes |= 1 << intel_crtc->pipe;
10325 else
10326 *prepare_pipes |= 1 << intel_crtc->pipe;
10327 }
10328
10329
10330 /* set_mode is also used to update properties on life display pipes. */
10331 intel_crtc = to_intel_crtc(crtc);
10332 if (intel_crtc->new_enabled)
10333 *prepare_pipes |= 1 << intel_crtc->pipe;
10334
10335 /*
10336 * For simplicity do a full modeset on any pipe where the output routing
10337 * changed. We could be more clever, but that would require us to be
10338 * more careful with calling the relevant encoder->mode_set functions.
10339 */
10340 if (*prepare_pipes)
10341 *modeset_pipes = *prepare_pipes;
10342
10343 /* ... and mask these out. */
10344 *modeset_pipes &= ~(*disable_pipes);
10345 *prepare_pipes &= ~(*disable_pipes);
10346
10347 /*
10348 * HACK: We don't (yet) fully support global modesets. intel_set_config
10349 * obies this rule, but the modeset restore mode of
10350 * intel_modeset_setup_hw_state does not.
10351 */
10352 *modeset_pipes &= 1 << intel_crtc->pipe;
10353 *prepare_pipes &= 1 << intel_crtc->pipe;
10354
10355 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10356 *modeset_pipes, *prepare_pipes, *disable_pipes);
10357 }
10358
10359 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10360 {
10361 struct drm_encoder *encoder;
10362 struct drm_device *dev = crtc->dev;
10363
10364 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10365 if (encoder->crtc == crtc)
10366 return true;
10367
10368 return false;
10369 }
10370
10371 static void
10372 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10373 {
10374 struct intel_encoder *intel_encoder;
10375 struct intel_crtc *intel_crtc;
10376 struct drm_connector *connector;
10377
10378 for_each_intel_encoder(dev, intel_encoder) {
10379 if (!intel_encoder->base.crtc)
10380 continue;
10381
10382 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10383
10384 if (prepare_pipes & (1 << intel_crtc->pipe))
10385 intel_encoder->connectors_active = false;
10386 }
10387
10388 intel_modeset_commit_output_state(dev);
10389
10390 /* Double check state. */
10391 for_each_intel_crtc(dev, intel_crtc) {
10392 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10393 WARN_ON(intel_crtc->new_config &&
10394 intel_crtc->new_config != &intel_crtc->config);
10395 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10396 }
10397
10398 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10399 if (!connector->encoder || !connector->encoder->crtc)
10400 continue;
10401
10402 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10403
10404 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10405 struct drm_property *dpms_property =
10406 dev->mode_config.dpms_property;
10407
10408 connector->dpms = DRM_MODE_DPMS_ON;
10409 drm_object_property_set_value(&connector->base,
10410 dpms_property,
10411 DRM_MODE_DPMS_ON);
10412
10413 intel_encoder = to_intel_encoder(connector->encoder);
10414 intel_encoder->connectors_active = true;
10415 }
10416 }
10417
10418 }
10419
10420 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10421 {
10422 int diff;
10423
10424 if (clock1 == clock2)
10425 return true;
10426
10427 if (!clock1 || !clock2)
10428 return false;
10429
10430 diff = abs(clock1 - clock2);
10431
10432 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10433 return true;
10434
10435 return false;
10436 }
10437
10438 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10439 list_for_each_entry((intel_crtc), \
10440 &(dev)->mode_config.crtc_list, \
10441 base.head) \
10442 if (mask & (1 <<(intel_crtc)->pipe))
10443
10444 static bool
10445 intel_pipe_config_compare(struct drm_device *dev,
10446 struct intel_crtc_config *current_config,
10447 struct intel_crtc_config *pipe_config)
10448 {
10449 #define PIPE_CONF_CHECK_X(name) \
10450 if (current_config->name != pipe_config->name) { \
10451 DRM_ERROR("mismatch in " #name " " \
10452 "(expected 0x%08x, found 0x%08x)\n", \
10453 current_config->name, \
10454 pipe_config->name); \
10455 return false; \
10456 }
10457
10458 #define PIPE_CONF_CHECK_I(name) \
10459 if (current_config->name != pipe_config->name) { \
10460 DRM_ERROR("mismatch in " #name " " \
10461 "(expected %i, found %i)\n", \
10462 current_config->name, \
10463 pipe_config->name); \
10464 return false; \
10465 }
10466
10467 /* This is required for BDW+ where there is only one set of registers for
10468 * switching between high and low RR.
10469 * This macro can be used whenever a comparison has to be made between one
10470 * hw state and multiple sw state variables.
10471 */
10472 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10473 if ((current_config->name != pipe_config->name) && \
10474 (current_config->alt_name != pipe_config->name)) { \
10475 DRM_ERROR("mismatch in " #name " " \
10476 "(expected %i or %i, found %i)\n", \
10477 current_config->name, \
10478 current_config->alt_name, \
10479 pipe_config->name); \
10480 return false; \
10481 }
10482
10483 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10484 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10485 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10486 "(expected %i, found %i)\n", \
10487 current_config->name & (mask), \
10488 pipe_config->name & (mask)); \
10489 return false; \
10490 }
10491
10492 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10493 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10494 DRM_ERROR("mismatch in " #name " " \
10495 "(expected %i, found %i)\n", \
10496 current_config->name, \
10497 pipe_config->name); \
10498 return false; \
10499 }
10500
10501 #define PIPE_CONF_QUIRK(quirk) \
10502 ((current_config->quirks | pipe_config->quirks) & (quirk))
10503
10504 PIPE_CONF_CHECK_I(cpu_transcoder);
10505
10506 PIPE_CONF_CHECK_I(has_pch_encoder);
10507 PIPE_CONF_CHECK_I(fdi_lanes);
10508 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10509 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10510 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10511 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10512 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10513
10514 PIPE_CONF_CHECK_I(has_dp_encoder);
10515
10516 if (INTEL_INFO(dev)->gen < 8) {
10517 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10518 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10519 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10520 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10521 PIPE_CONF_CHECK_I(dp_m_n.tu);
10522
10523 if (current_config->has_drrs) {
10524 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10525 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10526 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10527 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10528 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10529 }
10530 } else {
10531 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10532 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10533 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10534 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10535 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10536 }
10537
10538 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10539 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10540 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10541 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10542 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10543 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10544
10545 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10546 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10547 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10548 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10549 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10550 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10551
10552 PIPE_CONF_CHECK_I(pixel_multiplier);
10553 PIPE_CONF_CHECK_I(has_hdmi_sink);
10554 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10555 IS_VALLEYVIEW(dev))
10556 PIPE_CONF_CHECK_I(limited_color_range);
10557
10558 PIPE_CONF_CHECK_I(has_audio);
10559
10560 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10561 DRM_MODE_FLAG_INTERLACE);
10562
10563 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10564 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10565 DRM_MODE_FLAG_PHSYNC);
10566 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10567 DRM_MODE_FLAG_NHSYNC);
10568 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10569 DRM_MODE_FLAG_PVSYNC);
10570 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10571 DRM_MODE_FLAG_NVSYNC);
10572 }
10573
10574 PIPE_CONF_CHECK_I(pipe_src_w);
10575 PIPE_CONF_CHECK_I(pipe_src_h);
10576
10577 /*
10578 * FIXME: BIOS likes to set up a cloned config with lvds+external
10579 * screen. Since we don't yet re-compute the pipe config when moving
10580 * just the lvds port away to another pipe the sw tracking won't match.
10581 *
10582 * Proper atomic modesets with recomputed global state will fix this.
10583 * Until then just don't check gmch state for inherited modes.
10584 */
10585 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10586 PIPE_CONF_CHECK_I(gmch_pfit.control);
10587 /* pfit ratios are autocomputed by the hw on gen4+ */
10588 if (INTEL_INFO(dev)->gen < 4)
10589 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10590 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10591 }
10592
10593 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10594 if (current_config->pch_pfit.enabled) {
10595 PIPE_CONF_CHECK_I(pch_pfit.pos);
10596 PIPE_CONF_CHECK_I(pch_pfit.size);
10597 }
10598
10599 /* BDW+ don't expose a synchronous way to read the state */
10600 if (IS_HASWELL(dev))
10601 PIPE_CONF_CHECK_I(ips_enabled);
10602
10603 PIPE_CONF_CHECK_I(double_wide);
10604
10605 PIPE_CONF_CHECK_X(ddi_pll_sel);
10606
10607 PIPE_CONF_CHECK_I(shared_dpll);
10608 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10609 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10610 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10611 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10612 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10613
10614 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10615 PIPE_CONF_CHECK_I(pipe_bpp);
10616
10617 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10618 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10619
10620 #undef PIPE_CONF_CHECK_X
10621 #undef PIPE_CONF_CHECK_I
10622 #undef PIPE_CONF_CHECK_I_ALT
10623 #undef PIPE_CONF_CHECK_FLAGS
10624 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10625 #undef PIPE_CONF_QUIRK
10626
10627 return true;
10628 }
10629
10630 static void
10631 check_connector_state(struct drm_device *dev)
10632 {
10633 struct intel_connector *connector;
10634
10635 list_for_each_entry(connector, &dev->mode_config.connector_list,
10636 base.head) {
10637 /* This also checks the encoder/connector hw state with the
10638 * ->get_hw_state callbacks. */
10639 intel_connector_check_state(connector);
10640
10641 WARN(&connector->new_encoder->base != connector->base.encoder,
10642 "connector's staged encoder doesn't match current encoder\n");
10643 }
10644 }
10645
10646 static void
10647 check_encoder_state(struct drm_device *dev)
10648 {
10649 struct intel_encoder *encoder;
10650 struct intel_connector *connector;
10651
10652 for_each_intel_encoder(dev, encoder) {
10653 bool enabled = false;
10654 bool active = false;
10655 enum pipe pipe, tracked_pipe;
10656
10657 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10658 encoder->base.base.id,
10659 encoder->base.name);
10660
10661 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10662 "encoder's stage crtc doesn't match current crtc\n");
10663 WARN(encoder->connectors_active && !encoder->base.crtc,
10664 "encoder's active_connectors set, but no crtc\n");
10665
10666 list_for_each_entry(connector, &dev->mode_config.connector_list,
10667 base.head) {
10668 if (connector->base.encoder != &encoder->base)
10669 continue;
10670 enabled = true;
10671 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10672 active = true;
10673 }
10674 /*
10675 * for MST connectors if we unplug the connector is gone
10676 * away but the encoder is still connected to a crtc
10677 * until a modeset happens in response to the hotplug.
10678 */
10679 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10680 continue;
10681
10682 WARN(!!encoder->base.crtc != enabled,
10683 "encoder's enabled state mismatch "
10684 "(expected %i, found %i)\n",
10685 !!encoder->base.crtc, enabled);
10686 WARN(active && !encoder->base.crtc,
10687 "active encoder with no crtc\n");
10688
10689 WARN(encoder->connectors_active != active,
10690 "encoder's computed active state doesn't match tracked active state "
10691 "(expected %i, found %i)\n", active, encoder->connectors_active);
10692
10693 active = encoder->get_hw_state(encoder, &pipe);
10694 WARN(active != encoder->connectors_active,
10695 "encoder's hw state doesn't match sw tracking "
10696 "(expected %i, found %i)\n",
10697 encoder->connectors_active, active);
10698
10699 if (!encoder->base.crtc)
10700 continue;
10701
10702 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10703 WARN(active && pipe != tracked_pipe,
10704 "active encoder's pipe doesn't match"
10705 "(expected %i, found %i)\n",
10706 tracked_pipe, pipe);
10707
10708 }
10709 }
10710
10711 static void
10712 check_crtc_state(struct drm_device *dev)
10713 {
10714 struct drm_i915_private *dev_priv = dev->dev_private;
10715 struct intel_crtc *crtc;
10716 struct intel_encoder *encoder;
10717 struct intel_crtc_config pipe_config;
10718
10719 for_each_intel_crtc(dev, crtc) {
10720 bool enabled = false;
10721 bool active = false;
10722
10723 memset(&pipe_config, 0, sizeof(pipe_config));
10724
10725 DRM_DEBUG_KMS("[CRTC:%d]\n",
10726 crtc->base.base.id);
10727
10728 WARN(crtc->active && !crtc->base.enabled,
10729 "active crtc, but not enabled in sw tracking\n");
10730
10731 for_each_intel_encoder(dev, encoder) {
10732 if (encoder->base.crtc != &crtc->base)
10733 continue;
10734 enabled = true;
10735 if (encoder->connectors_active)
10736 active = true;
10737 }
10738
10739 WARN(active != crtc->active,
10740 "crtc's computed active state doesn't match tracked active state "
10741 "(expected %i, found %i)\n", active, crtc->active);
10742 WARN(enabled != crtc->base.enabled,
10743 "crtc's computed enabled state doesn't match tracked enabled state "
10744 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10745
10746 active = dev_priv->display.get_pipe_config(crtc,
10747 &pipe_config);
10748
10749 /* hw state is inconsistent with the pipe A quirk */
10750 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
10751 active = crtc->active;
10752
10753 for_each_intel_encoder(dev, encoder) {
10754 enum pipe pipe;
10755 if (encoder->base.crtc != &crtc->base)
10756 continue;
10757 if (encoder->get_hw_state(encoder, &pipe))
10758 encoder->get_config(encoder, &pipe_config);
10759 }
10760
10761 WARN(crtc->active != active,
10762 "crtc active state doesn't match with hw state "
10763 "(expected %i, found %i)\n", crtc->active, active);
10764
10765 if (active &&
10766 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10767 WARN(1, "pipe state doesn't match!\n");
10768 intel_dump_pipe_config(crtc, &pipe_config,
10769 "[hw state]");
10770 intel_dump_pipe_config(crtc, &crtc->config,
10771 "[sw state]");
10772 }
10773 }
10774 }
10775
10776 static void
10777 check_shared_dpll_state(struct drm_device *dev)
10778 {
10779 struct drm_i915_private *dev_priv = dev->dev_private;
10780 struct intel_crtc *crtc;
10781 struct intel_dpll_hw_state dpll_hw_state;
10782 int i;
10783
10784 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10785 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10786 int enabled_crtcs = 0, active_crtcs = 0;
10787 bool active;
10788
10789 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10790
10791 DRM_DEBUG_KMS("%s\n", pll->name);
10792
10793 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10794
10795 WARN(pll->active > pll->refcount,
10796 "more active pll users than references: %i vs %i\n",
10797 pll->active, pll->refcount);
10798 WARN(pll->active && !pll->on,
10799 "pll in active use but not on in sw tracking\n");
10800 WARN(pll->on && !pll->active,
10801 "pll in on but not on in use in sw tracking\n");
10802 WARN(pll->on != active,
10803 "pll on state mismatch (expected %i, found %i)\n",
10804 pll->on, active);
10805
10806 for_each_intel_crtc(dev, crtc) {
10807 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10808 enabled_crtcs++;
10809 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10810 active_crtcs++;
10811 }
10812 WARN(pll->active != active_crtcs,
10813 "pll active crtcs mismatch (expected %i, found %i)\n",
10814 pll->active, active_crtcs);
10815 WARN(pll->refcount != enabled_crtcs,
10816 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10817 pll->refcount, enabled_crtcs);
10818
10819 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
10820 sizeof(dpll_hw_state)),
10821 "pll hw state mismatch\n");
10822 }
10823 }
10824
10825 void
10826 intel_modeset_check_state(struct drm_device *dev)
10827 {
10828 check_connector_state(dev);
10829 check_encoder_state(dev);
10830 check_crtc_state(dev);
10831 check_shared_dpll_state(dev);
10832 }
10833
10834 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10835 int dotclock)
10836 {
10837 /*
10838 * FDI already provided one idea for the dotclock.
10839 * Yell if the encoder disagrees.
10840 */
10841 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10842 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10843 pipe_config->adjusted_mode.crtc_clock, dotclock);
10844 }
10845
10846 static void update_scanline_offset(struct intel_crtc *crtc)
10847 {
10848 struct drm_device *dev = crtc->base.dev;
10849
10850 /*
10851 * The scanline counter increments at the leading edge of hsync.
10852 *
10853 * On most platforms it starts counting from vtotal-1 on the
10854 * first active line. That means the scanline counter value is
10855 * always one less than what we would expect. Ie. just after
10856 * start of vblank, which also occurs at start of hsync (on the
10857 * last active line), the scanline counter will read vblank_start-1.
10858 *
10859 * On gen2 the scanline counter starts counting from 1 instead
10860 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10861 * to keep the value positive), instead of adding one.
10862 *
10863 * On HSW+ the behaviour of the scanline counter depends on the output
10864 * type. For DP ports it behaves like most other platforms, but on HDMI
10865 * there's an extra 1 line difference. So we need to add two instead of
10866 * one to the value.
10867 */
10868 if (IS_GEN2(dev)) {
10869 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
10870 int vtotal;
10871
10872 vtotal = mode->crtc_vtotal;
10873 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10874 vtotal /= 2;
10875
10876 crtc->scanline_offset = vtotal - 1;
10877 } else if (HAS_DDI(dev) &&
10878 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {
10879 crtc->scanline_offset = 2;
10880 } else
10881 crtc->scanline_offset = 1;
10882 }
10883
10884 static int __intel_set_mode(struct drm_crtc *crtc,
10885 struct drm_display_mode *mode,
10886 int x, int y, struct drm_framebuffer *fb)
10887 {
10888 struct drm_device *dev = crtc->dev;
10889 struct drm_i915_private *dev_priv = dev->dev_private;
10890 struct drm_display_mode *saved_mode;
10891 struct intel_crtc_config *pipe_config = NULL;
10892 struct intel_crtc *intel_crtc;
10893 unsigned disable_pipes, prepare_pipes, modeset_pipes;
10894 int ret = 0;
10895
10896 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10897 if (!saved_mode)
10898 return -ENOMEM;
10899
10900 intel_modeset_affected_pipes(crtc, &modeset_pipes,
10901 &prepare_pipes, &disable_pipes);
10902
10903 *saved_mode = crtc->mode;
10904
10905 /* Hack: Because we don't (yet) support global modeset on multiple
10906 * crtcs, we don't keep track of the new mode for more than one crtc.
10907 * Hence simply check whether any bit is set in modeset_pipes in all the
10908 * pieces of code that are not yet converted to deal with mutliple crtcs
10909 * changing their mode at the same time. */
10910 if (modeset_pipes) {
10911 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10912 if (IS_ERR(pipe_config)) {
10913 ret = PTR_ERR(pipe_config);
10914 pipe_config = NULL;
10915
10916 goto out;
10917 }
10918 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10919 "[modeset]");
10920 to_intel_crtc(crtc)->new_config = pipe_config;
10921 }
10922
10923 /*
10924 * See if the config requires any additional preparation, e.g.
10925 * to adjust global state with pipes off. We need to do this
10926 * here so we can get the modeset_pipe updated config for the new
10927 * mode set on this crtc. For other crtcs we need to use the
10928 * adjusted_mode bits in the crtc directly.
10929 */
10930 if (IS_VALLEYVIEW(dev)) {
10931 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10932
10933 /* may have added more to prepare_pipes than we should */
10934 prepare_pipes &= ~disable_pipes;
10935 }
10936
10937 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10938 intel_crtc_disable(&intel_crtc->base);
10939
10940 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10941 if (intel_crtc->base.enabled)
10942 dev_priv->display.crtc_disable(&intel_crtc->base);
10943 }
10944
10945 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10946 * to set it here already despite that we pass it down the callchain.
10947 */
10948 if (modeset_pipes) {
10949 crtc->mode = *mode;
10950 /* mode_set/enable/disable functions rely on a correct pipe
10951 * config. */
10952 to_intel_crtc(crtc)->config = *pipe_config;
10953 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10954
10955 /*
10956 * Calculate and store various constants which
10957 * are later needed by vblank and swap-completion
10958 * timestamping. They are derived from true hwmode.
10959 */
10960 drm_calc_timestamping_constants(crtc,
10961 &pipe_config->adjusted_mode);
10962 }
10963
10964 /* Only after disabling all output pipelines that will be changed can we
10965 * update the the output configuration. */
10966 intel_modeset_update_state(dev, prepare_pipes);
10967
10968 if (dev_priv->display.modeset_global_resources)
10969 dev_priv->display.modeset_global_resources(dev);
10970
10971 /* Set up the DPLL and any encoders state that needs to adjust or depend
10972 * on the DPLL.
10973 */
10974 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10975 struct drm_framebuffer *old_fb = crtc->primary->fb;
10976 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
10977 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10978
10979 mutex_lock(&dev->struct_mutex);
10980 ret = intel_pin_and_fence_fb_obj(dev,
10981 obj,
10982 NULL);
10983 if (ret != 0) {
10984 DRM_ERROR("pin & fence failed\n");
10985 mutex_unlock(&dev->struct_mutex);
10986 goto done;
10987 }
10988 if (old_fb)
10989 intel_unpin_fb_obj(old_obj);
10990 i915_gem_track_fb(old_obj, obj,
10991 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
10992 mutex_unlock(&dev->struct_mutex);
10993
10994 crtc->primary->fb = fb;
10995 crtc->x = x;
10996 crtc->y = y;
10997
10998 ret = dev_priv->display.crtc_mode_set(&intel_crtc->base,
10999 x, y, fb);
11000 if (ret)
11001 goto done;
11002 }
11003
11004 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11005 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11006 update_scanline_offset(intel_crtc);
11007
11008 dev_priv->display.crtc_enable(&intel_crtc->base);
11009 }
11010
11011 /* FIXME: add subpixel order */
11012 done:
11013 if (ret && crtc->enabled)
11014 crtc->mode = *saved_mode;
11015
11016 out:
11017 kfree(pipe_config);
11018 kfree(saved_mode);
11019 return ret;
11020 }
11021
11022 static int intel_set_mode(struct drm_crtc *crtc,
11023 struct drm_display_mode *mode,
11024 int x, int y, struct drm_framebuffer *fb)
11025 {
11026 int ret;
11027
11028 ret = __intel_set_mode(crtc, mode, x, y, fb);
11029
11030 if (ret == 0)
11031 intel_modeset_check_state(crtc->dev);
11032
11033 return ret;
11034 }
11035
11036 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11037 {
11038 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
11039 }
11040
11041 #undef for_each_intel_crtc_masked
11042
11043 static void intel_set_config_free(struct intel_set_config *config)
11044 {
11045 if (!config)
11046 return;
11047
11048 kfree(config->save_connector_encoders);
11049 kfree(config->save_encoder_crtcs);
11050 kfree(config->save_crtc_enabled);
11051 kfree(config);
11052 }
11053
11054 static int intel_set_config_save_state(struct drm_device *dev,
11055 struct intel_set_config *config)
11056 {
11057 struct drm_crtc *crtc;
11058 struct drm_encoder *encoder;
11059 struct drm_connector *connector;
11060 int count;
11061
11062 config->save_crtc_enabled =
11063 kcalloc(dev->mode_config.num_crtc,
11064 sizeof(bool), GFP_KERNEL);
11065 if (!config->save_crtc_enabled)
11066 return -ENOMEM;
11067
11068 config->save_encoder_crtcs =
11069 kcalloc(dev->mode_config.num_encoder,
11070 sizeof(struct drm_crtc *), GFP_KERNEL);
11071 if (!config->save_encoder_crtcs)
11072 return -ENOMEM;
11073
11074 config->save_connector_encoders =
11075 kcalloc(dev->mode_config.num_connector,
11076 sizeof(struct drm_encoder *), GFP_KERNEL);
11077 if (!config->save_connector_encoders)
11078 return -ENOMEM;
11079
11080 /* Copy data. Note that driver private data is not affected.
11081 * Should anything bad happen only the expected state is
11082 * restored, not the drivers personal bookkeeping.
11083 */
11084 count = 0;
11085 for_each_crtc(dev, crtc) {
11086 config->save_crtc_enabled[count++] = crtc->enabled;
11087 }
11088
11089 count = 0;
11090 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11091 config->save_encoder_crtcs[count++] = encoder->crtc;
11092 }
11093
11094 count = 0;
11095 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11096 config->save_connector_encoders[count++] = connector->encoder;
11097 }
11098
11099 return 0;
11100 }
11101
11102 static void intel_set_config_restore_state(struct drm_device *dev,
11103 struct intel_set_config *config)
11104 {
11105 struct intel_crtc *crtc;
11106 struct intel_encoder *encoder;
11107 struct intel_connector *connector;
11108 int count;
11109
11110 count = 0;
11111 for_each_intel_crtc(dev, crtc) {
11112 crtc->new_enabled = config->save_crtc_enabled[count++];
11113
11114 if (crtc->new_enabled)
11115 crtc->new_config = &crtc->config;
11116 else
11117 crtc->new_config = NULL;
11118 }
11119
11120 count = 0;
11121 for_each_intel_encoder(dev, encoder) {
11122 encoder->new_crtc =
11123 to_intel_crtc(config->save_encoder_crtcs[count++]);
11124 }
11125
11126 count = 0;
11127 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11128 connector->new_encoder =
11129 to_intel_encoder(config->save_connector_encoders[count++]);
11130 }
11131 }
11132
11133 static bool
11134 is_crtc_connector_off(struct drm_mode_set *set)
11135 {
11136 int i;
11137
11138 if (set->num_connectors == 0)
11139 return false;
11140
11141 if (WARN_ON(set->connectors == NULL))
11142 return false;
11143
11144 for (i = 0; i < set->num_connectors; i++)
11145 if (set->connectors[i]->encoder &&
11146 set->connectors[i]->encoder->crtc == set->crtc &&
11147 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11148 return true;
11149
11150 return false;
11151 }
11152
11153 static void
11154 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11155 struct intel_set_config *config)
11156 {
11157
11158 /* We should be able to check here if the fb has the same properties
11159 * and then just flip_or_move it */
11160 if (is_crtc_connector_off(set)) {
11161 config->mode_changed = true;
11162 } else if (set->crtc->primary->fb != set->fb) {
11163 /*
11164 * If we have no fb, we can only flip as long as the crtc is
11165 * active, otherwise we need a full mode set. The crtc may
11166 * be active if we've only disabled the primary plane, or
11167 * in fastboot situations.
11168 */
11169 if (set->crtc->primary->fb == NULL) {
11170 struct intel_crtc *intel_crtc =
11171 to_intel_crtc(set->crtc);
11172
11173 if (intel_crtc->active) {
11174 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11175 config->fb_changed = true;
11176 } else {
11177 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11178 config->mode_changed = true;
11179 }
11180 } else if (set->fb == NULL) {
11181 config->mode_changed = true;
11182 } else if (set->fb->pixel_format !=
11183 set->crtc->primary->fb->pixel_format) {
11184 config->mode_changed = true;
11185 } else {
11186 config->fb_changed = true;
11187 }
11188 }
11189
11190 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11191 config->fb_changed = true;
11192
11193 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11194 DRM_DEBUG_KMS("modes are different, full mode set\n");
11195 drm_mode_debug_printmodeline(&set->crtc->mode);
11196 drm_mode_debug_printmodeline(set->mode);
11197 config->mode_changed = true;
11198 }
11199
11200 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11201 set->crtc->base.id, config->mode_changed, config->fb_changed);
11202 }
11203
11204 static int
11205 intel_modeset_stage_output_state(struct drm_device *dev,
11206 struct drm_mode_set *set,
11207 struct intel_set_config *config)
11208 {
11209 struct intel_connector *connector;
11210 struct intel_encoder *encoder;
11211 struct intel_crtc *crtc;
11212 int ro;
11213
11214 /* The upper layers ensure that we either disable a crtc or have a list
11215 * of connectors. For paranoia, double-check this. */
11216 WARN_ON(!set->fb && (set->num_connectors != 0));
11217 WARN_ON(set->fb && (set->num_connectors == 0));
11218
11219 list_for_each_entry(connector, &dev->mode_config.connector_list,
11220 base.head) {
11221 /* Otherwise traverse passed in connector list and get encoders
11222 * for them. */
11223 for (ro = 0; ro < set->num_connectors; ro++) {
11224 if (set->connectors[ro] == &connector->base) {
11225 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11226 break;
11227 }
11228 }
11229
11230 /* If we disable the crtc, disable all its connectors. Also, if
11231 * the connector is on the changing crtc but not on the new
11232 * connector list, disable it. */
11233 if ((!set->fb || ro == set->num_connectors) &&
11234 connector->base.encoder &&
11235 connector->base.encoder->crtc == set->crtc) {
11236 connector->new_encoder = NULL;
11237
11238 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11239 connector->base.base.id,
11240 connector->base.name);
11241 }
11242
11243
11244 if (&connector->new_encoder->base != connector->base.encoder) {
11245 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11246 config->mode_changed = true;
11247 }
11248 }
11249 /* connector->new_encoder is now updated for all connectors. */
11250
11251 /* Update crtc of enabled connectors. */
11252 list_for_each_entry(connector, &dev->mode_config.connector_list,
11253 base.head) {
11254 struct drm_crtc *new_crtc;
11255
11256 if (!connector->new_encoder)
11257 continue;
11258
11259 new_crtc = connector->new_encoder->base.crtc;
11260
11261 for (ro = 0; ro < set->num_connectors; ro++) {
11262 if (set->connectors[ro] == &connector->base)
11263 new_crtc = set->crtc;
11264 }
11265
11266 /* Make sure the new CRTC will work with the encoder */
11267 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11268 new_crtc)) {
11269 return -EINVAL;
11270 }
11271 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11272
11273 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11274 connector->base.base.id,
11275 connector->base.name,
11276 new_crtc->base.id);
11277 }
11278
11279 /* Check for any encoders that needs to be disabled. */
11280 for_each_intel_encoder(dev, encoder) {
11281 int num_connectors = 0;
11282 list_for_each_entry(connector,
11283 &dev->mode_config.connector_list,
11284 base.head) {
11285 if (connector->new_encoder == encoder) {
11286 WARN_ON(!connector->new_encoder->new_crtc);
11287 num_connectors++;
11288 }
11289 }
11290
11291 if (num_connectors == 0)
11292 encoder->new_crtc = NULL;
11293 else if (num_connectors > 1)
11294 return -EINVAL;
11295
11296 /* Only now check for crtc changes so we don't miss encoders
11297 * that will be disabled. */
11298 if (&encoder->new_crtc->base != encoder->base.crtc) {
11299 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11300 config->mode_changed = true;
11301 }
11302 }
11303 /* Now we've also updated encoder->new_crtc for all encoders. */
11304 list_for_each_entry(connector, &dev->mode_config.connector_list,
11305 base.head) {
11306 if (connector->new_encoder)
11307 if (connector->new_encoder != connector->encoder)
11308 connector->encoder = connector->new_encoder;
11309 }
11310 for_each_intel_crtc(dev, crtc) {
11311 crtc->new_enabled = false;
11312
11313 for_each_intel_encoder(dev, encoder) {
11314 if (encoder->new_crtc == crtc) {
11315 crtc->new_enabled = true;
11316 break;
11317 }
11318 }
11319
11320 if (crtc->new_enabled != crtc->base.enabled) {
11321 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11322 crtc->new_enabled ? "en" : "dis");
11323 config->mode_changed = true;
11324 }
11325
11326 if (crtc->new_enabled)
11327 crtc->new_config = &crtc->config;
11328 else
11329 crtc->new_config = NULL;
11330 }
11331
11332 return 0;
11333 }
11334
11335 static void disable_crtc_nofb(struct intel_crtc *crtc)
11336 {
11337 struct drm_device *dev = crtc->base.dev;
11338 struct intel_encoder *encoder;
11339 struct intel_connector *connector;
11340
11341 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11342 pipe_name(crtc->pipe));
11343
11344 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11345 if (connector->new_encoder &&
11346 connector->new_encoder->new_crtc == crtc)
11347 connector->new_encoder = NULL;
11348 }
11349
11350 for_each_intel_encoder(dev, encoder) {
11351 if (encoder->new_crtc == crtc)
11352 encoder->new_crtc = NULL;
11353 }
11354
11355 crtc->new_enabled = false;
11356 crtc->new_config = NULL;
11357 }
11358
11359 static int intel_crtc_set_config(struct drm_mode_set *set)
11360 {
11361 struct drm_device *dev;
11362 struct drm_mode_set save_set;
11363 struct intel_set_config *config;
11364 int ret;
11365
11366 BUG_ON(!set);
11367 BUG_ON(!set->crtc);
11368 BUG_ON(!set->crtc->helper_private);
11369
11370 /* Enforce sane interface api - has been abused by the fb helper. */
11371 BUG_ON(!set->mode && set->fb);
11372 BUG_ON(set->fb && set->num_connectors == 0);
11373
11374 if (set->fb) {
11375 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11376 set->crtc->base.id, set->fb->base.id,
11377 (int)set->num_connectors, set->x, set->y);
11378 } else {
11379 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11380 }
11381
11382 dev = set->crtc->dev;
11383
11384 ret = -ENOMEM;
11385 config = kzalloc(sizeof(*config), GFP_KERNEL);
11386 if (!config)
11387 goto out_config;
11388
11389 ret = intel_set_config_save_state(dev, config);
11390 if (ret)
11391 goto out_config;
11392
11393 save_set.crtc = set->crtc;
11394 save_set.mode = &set->crtc->mode;
11395 save_set.x = set->crtc->x;
11396 save_set.y = set->crtc->y;
11397 save_set.fb = set->crtc->primary->fb;
11398
11399 /* Compute whether we need a full modeset, only an fb base update or no
11400 * change at all. In the future we might also check whether only the
11401 * mode changed, e.g. for LVDS where we only change the panel fitter in
11402 * such cases. */
11403 intel_set_config_compute_mode_changes(set, config);
11404
11405 ret = intel_modeset_stage_output_state(dev, set, config);
11406 if (ret)
11407 goto fail;
11408
11409 if (config->mode_changed) {
11410 ret = intel_set_mode(set->crtc, set->mode,
11411 set->x, set->y, set->fb);
11412 } else if (config->fb_changed) {
11413 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11414
11415 intel_crtc_wait_for_pending_flips(set->crtc);
11416
11417 ret = intel_pipe_set_base(set->crtc,
11418 set->x, set->y, set->fb);
11419
11420 /*
11421 * We need to make sure the primary plane is re-enabled if it
11422 * has previously been turned off.
11423 */
11424 if (!intel_crtc->primary_enabled && ret == 0) {
11425 WARN_ON(!intel_crtc->active);
11426 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11427 }
11428
11429 /*
11430 * In the fastboot case this may be our only check of the
11431 * state after boot. It would be better to only do it on
11432 * the first update, but we don't have a nice way of doing that
11433 * (and really, set_config isn't used much for high freq page
11434 * flipping, so increasing its cost here shouldn't be a big
11435 * deal).
11436 */
11437 if (i915.fastboot && ret == 0)
11438 intel_modeset_check_state(set->crtc->dev);
11439 }
11440
11441 if (ret) {
11442 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11443 set->crtc->base.id, ret);
11444 fail:
11445 intel_set_config_restore_state(dev, config);
11446
11447 /*
11448 * HACK: if the pipe was on, but we didn't have a framebuffer,
11449 * force the pipe off to avoid oopsing in the modeset code
11450 * due to fb==NULL. This should only happen during boot since
11451 * we don't yet reconstruct the FB from the hardware state.
11452 */
11453 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11454 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11455
11456 /* Try to restore the config */
11457 if (config->mode_changed &&
11458 intel_set_mode(save_set.crtc, save_set.mode,
11459 save_set.x, save_set.y, save_set.fb))
11460 DRM_ERROR("failed to restore config after modeset failure\n");
11461 }
11462
11463 out_config:
11464 intel_set_config_free(config);
11465 return ret;
11466 }
11467
11468 static const struct drm_crtc_funcs intel_crtc_funcs = {
11469 .gamma_set = intel_crtc_gamma_set,
11470 .set_config = intel_crtc_set_config,
11471 .destroy = intel_crtc_destroy,
11472 .page_flip = intel_crtc_page_flip,
11473 };
11474
11475 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11476 struct intel_shared_dpll *pll,
11477 struct intel_dpll_hw_state *hw_state)
11478 {
11479 uint32_t val;
11480
11481 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_PLLS))
11482 return false;
11483
11484 val = I915_READ(PCH_DPLL(pll->id));
11485 hw_state->dpll = val;
11486 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11487 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11488
11489 return val & DPLL_VCO_ENABLE;
11490 }
11491
11492 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11493 struct intel_shared_dpll *pll)
11494 {
11495 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
11496 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
11497 }
11498
11499 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11500 struct intel_shared_dpll *pll)
11501 {
11502 /* PCH refclock must be enabled first */
11503 ibx_assert_pch_refclk_enabled(dev_priv);
11504
11505 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11506
11507 /* Wait for the clocks to stabilize. */
11508 POSTING_READ(PCH_DPLL(pll->id));
11509 udelay(150);
11510
11511 /* The pixel multiplier can only be updated once the
11512 * DPLL is enabled and the clocks are stable.
11513 *
11514 * So write it again.
11515 */
11516 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11517 POSTING_READ(PCH_DPLL(pll->id));
11518 udelay(200);
11519 }
11520
11521 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11522 struct intel_shared_dpll *pll)
11523 {
11524 struct drm_device *dev = dev_priv->dev;
11525 struct intel_crtc *crtc;
11526
11527 /* Make sure no transcoder isn't still depending on us. */
11528 for_each_intel_crtc(dev, crtc) {
11529 if (intel_crtc_to_shared_dpll(crtc) == pll)
11530 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11531 }
11532
11533 I915_WRITE(PCH_DPLL(pll->id), 0);
11534 POSTING_READ(PCH_DPLL(pll->id));
11535 udelay(200);
11536 }
11537
11538 static char *ibx_pch_dpll_names[] = {
11539 "PCH DPLL A",
11540 "PCH DPLL B",
11541 };
11542
11543 static void ibx_pch_dpll_init(struct drm_device *dev)
11544 {
11545 struct drm_i915_private *dev_priv = dev->dev_private;
11546 int i;
11547
11548 dev_priv->num_shared_dpll = 2;
11549
11550 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11551 dev_priv->shared_dplls[i].id = i;
11552 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11553 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11554 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11555 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11556 dev_priv->shared_dplls[i].get_hw_state =
11557 ibx_pch_dpll_get_hw_state;
11558 }
11559 }
11560
11561 static void intel_shared_dpll_init(struct drm_device *dev)
11562 {
11563 struct drm_i915_private *dev_priv = dev->dev_private;
11564
11565 if (HAS_DDI(dev))
11566 intel_ddi_pll_init(dev);
11567 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11568 ibx_pch_dpll_init(dev);
11569 else
11570 dev_priv->num_shared_dpll = 0;
11571
11572 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11573 }
11574
11575 static int
11576 intel_primary_plane_disable(struct drm_plane *plane)
11577 {
11578 struct drm_device *dev = plane->dev;
11579 struct intel_crtc *intel_crtc;
11580
11581 if (!plane->fb)
11582 return 0;
11583
11584 BUG_ON(!plane->crtc);
11585
11586 intel_crtc = to_intel_crtc(plane->crtc);
11587
11588 /*
11589 * Even though we checked plane->fb above, it's still possible that
11590 * the primary plane has been implicitly disabled because the crtc
11591 * coordinates given weren't visible, or because we detected
11592 * that it was 100% covered by a sprite plane. Or, the CRTC may be
11593 * off and we've set a fb, but haven't actually turned on the CRTC yet.
11594 * In either case, we need to unpin the FB and let the fb pointer get
11595 * updated, but otherwise we don't need to touch the hardware.
11596 */
11597 if (!intel_crtc->primary_enabled)
11598 goto disable_unpin;
11599
11600 intel_crtc_wait_for_pending_flips(plane->crtc);
11601 intel_disable_primary_hw_plane(plane, plane->crtc);
11602
11603 disable_unpin:
11604 mutex_lock(&dev->struct_mutex);
11605 i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
11606 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11607 intel_unpin_fb_obj(intel_fb_obj(plane->fb));
11608 mutex_unlock(&dev->struct_mutex);
11609 plane->fb = NULL;
11610
11611 return 0;
11612 }
11613
11614 static int
11615 intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11616 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11617 unsigned int crtc_w, unsigned int crtc_h,
11618 uint32_t src_x, uint32_t src_y,
11619 uint32_t src_w, uint32_t src_h)
11620 {
11621 struct drm_device *dev = crtc->dev;
11622 struct drm_i915_private *dev_priv = dev->dev_private;
11623 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11624 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11625 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11626 struct drm_rect dest = {
11627 /* integer pixels */
11628 .x1 = crtc_x,
11629 .y1 = crtc_y,
11630 .x2 = crtc_x + crtc_w,
11631 .y2 = crtc_y + crtc_h,
11632 };
11633 struct drm_rect src = {
11634 /* 16.16 fixed point */
11635 .x1 = src_x,
11636 .y1 = src_y,
11637 .x2 = src_x + src_w,
11638 .y2 = src_y + src_h,
11639 };
11640 const struct drm_rect clip = {
11641 /* integer pixels */
11642 .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
11643 .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
11644 };
11645 const struct {
11646 int crtc_x, crtc_y;
11647 unsigned int crtc_w, crtc_h;
11648 uint32_t src_x, src_y, src_w, src_h;
11649 } orig = {
11650 .crtc_x = crtc_x,
11651 .crtc_y = crtc_y,
11652 .crtc_w = crtc_w,
11653 .crtc_h = crtc_h,
11654 .src_x = src_x,
11655 .src_y = src_y,
11656 .src_w = src_w,
11657 .src_h = src_h,
11658 };
11659 struct intel_plane *intel_plane = to_intel_plane(plane);
11660 bool visible;
11661 int ret;
11662
11663 ret = drm_plane_helper_check_update(plane, crtc, fb,
11664 &src, &dest, &clip,
11665 DRM_PLANE_HELPER_NO_SCALING,
11666 DRM_PLANE_HELPER_NO_SCALING,
11667 false, true, &visible);
11668
11669 if (ret)
11670 return ret;
11671
11672 /*
11673 * If the CRTC isn't enabled, we're just pinning the framebuffer,
11674 * updating the fb pointer, and returning without touching the
11675 * hardware. This allows us to later do a drmModeSetCrtc with fb=-1 to
11676 * turn on the display with all planes setup as desired.
11677 */
11678 if (!crtc->enabled) {
11679 mutex_lock(&dev->struct_mutex);
11680
11681 /*
11682 * If we already called setplane while the crtc was disabled,
11683 * we may have an fb pinned; unpin it.
11684 */
11685 if (plane->fb)
11686 intel_unpin_fb_obj(old_obj);
11687
11688 i915_gem_track_fb(old_obj, obj,
11689 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11690
11691 /* Pin and return without programming hardware */
11692 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11693 mutex_unlock(&dev->struct_mutex);
11694
11695 return ret;
11696 }
11697
11698 intel_crtc_wait_for_pending_flips(crtc);
11699
11700 /*
11701 * If clipping results in a non-visible primary plane, we'll disable
11702 * the primary plane. Note that this is a bit different than what
11703 * happens if userspace explicitly disables the plane by passing fb=0
11704 * because plane->fb still gets set and pinned.
11705 */
11706 if (!visible) {
11707 mutex_lock(&dev->struct_mutex);
11708
11709 /*
11710 * Try to pin the new fb first so that we can bail out if we
11711 * fail.
11712 */
11713 if (plane->fb != fb) {
11714 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11715 if (ret) {
11716 mutex_unlock(&dev->struct_mutex);
11717 return ret;
11718 }
11719 }
11720
11721 i915_gem_track_fb(old_obj, obj,
11722 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11723
11724 if (intel_crtc->primary_enabled)
11725 intel_disable_primary_hw_plane(plane, crtc);
11726
11727
11728 if (plane->fb != fb)
11729 if (plane->fb)
11730 intel_unpin_fb_obj(old_obj);
11731
11732 mutex_unlock(&dev->struct_mutex);
11733
11734 } else {
11735 if (intel_crtc && intel_crtc->active &&
11736 intel_crtc->primary_enabled) {
11737 /*
11738 * FBC does not work on some platforms for rotated
11739 * planes, so disable it when rotation is not 0 and
11740 * update it when rotation is set back to 0.
11741 *
11742 * FIXME: This is redundant with the fbc update done in
11743 * the primary plane enable function except that that
11744 * one is done too late. We eventually need to unify
11745 * this.
11746 */
11747 if (INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11748 dev_priv->fbc.plane == intel_crtc->plane &&
11749 intel_plane->rotation != BIT(DRM_ROTATE_0)) {
11750 intel_disable_fbc(dev);
11751 }
11752 }
11753 ret = intel_pipe_set_base(crtc, src.x1, src.y1, fb);
11754 if (ret)
11755 return ret;
11756
11757 if (!intel_crtc->primary_enabled)
11758 intel_enable_primary_hw_plane(plane, crtc);
11759 }
11760
11761 intel_plane->crtc_x = orig.crtc_x;
11762 intel_plane->crtc_y = orig.crtc_y;
11763 intel_plane->crtc_w = orig.crtc_w;
11764 intel_plane->crtc_h = orig.crtc_h;
11765 intel_plane->src_x = orig.src_x;
11766 intel_plane->src_y = orig.src_y;
11767 intel_plane->src_w = orig.src_w;
11768 intel_plane->src_h = orig.src_h;
11769 intel_plane->obj = obj;
11770
11771 return 0;
11772 }
11773
11774 /* Common destruction function for both primary and cursor planes */
11775 static void intel_plane_destroy(struct drm_plane *plane)
11776 {
11777 struct intel_plane *intel_plane = to_intel_plane(plane);
11778 drm_plane_cleanup(plane);
11779 kfree(intel_plane);
11780 }
11781
11782 static const struct drm_plane_funcs intel_primary_plane_funcs = {
11783 .update_plane = intel_primary_plane_setplane,
11784 .disable_plane = intel_primary_plane_disable,
11785 .destroy = intel_plane_destroy,
11786 .set_property = intel_plane_set_property
11787 };
11788
11789 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11790 int pipe)
11791 {
11792 struct intel_plane *primary;
11793 const uint32_t *intel_primary_formats;
11794 int num_formats;
11795
11796 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11797 if (primary == NULL)
11798 return NULL;
11799
11800 primary->can_scale = false;
11801 primary->max_downscale = 1;
11802 primary->pipe = pipe;
11803 primary->plane = pipe;
11804 primary->rotation = BIT(DRM_ROTATE_0);
11805 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11806 primary->plane = !pipe;
11807
11808 if (INTEL_INFO(dev)->gen <= 3) {
11809 intel_primary_formats = intel_primary_formats_gen2;
11810 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
11811 } else {
11812 intel_primary_formats = intel_primary_formats_gen4;
11813 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
11814 }
11815
11816 drm_universal_plane_init(dev, &primary->base, 0,
11817 &intel_primary_plane_funcs,
11818 intel_primary_formats, num_formats,
11819 DRM_PLANE_TYPE_PRIMARY);
11820
11821 if (INTEL_INFO(dev)->gen >= 4) {
11822 if (!dev->mode_config.rotation_property)
11823 dev->mode_config.rotation_property =
11824 drm_mode_create_rotation_property(dev,
11825 BIT(DRM_ROTATE_0) |
11826 BIT(DRM_ROTATE_180));
11827 if (dev->mode_config.rotation_property)
11828 drm_object_attach_property(&primary->base.base,
11829 dev->mode_config.rotation_property,
11830 primary->rotation);
11831 }
11832
11833 return &primary->base;
11834 }
11835
11836 static int
11837 intel_cursor_plane_disable(struct drm_plane *plane)
11838 {
11839 if (!plane->fb)
11840 return 0;
11841
11842 BUG_ON(!plane->crtc);
11843
11844 return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
11845 }
11846
11847 static int
11848 intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
11849 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11850 unsigned int crtc_w, unsigned int crtc_h,
11851 uint32_t src_x, uint32_t src_y,
11852 uint32_t src_w, uint32_t src_h)
11853 {
11854 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11855 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11856 struct drm_i915_gem_object *obj = intel_fb->obj;
11857 struct drm_rect dest = {
11858 /* integer pixels */
11859 .x1 = crtc_x,
11860 .y1 = crtc_y,
11861 .x2 = crtc_x + crtc_w,
11862 .y2 = crtc_y + crtc_h,
11863 };
11864 struct drm_rect src = {
11865 /* 16.16 fixed point */
11866 .x1 = src_x,
11867 .y1 = src_y,
11868 .x2 = src_x + src_w,
11869 .y2 = src_y + src_h,
11870 };
11871 const struct drm_rect clip = {
11872 /* integer pixels */
11873 .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
11874 .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
11875 };
11876 bool visible;
11877 int ret;
11878
11879 ret = drm_plane_helper_check_update(plane, crtc, fb,
11880 &src, &dest, &clip,
11881 DRM_PLANE_HELPER_NO_SCALING,
11882 DRM_PLANE_HELPER_NO_SCALING,
11883 true, true, &visible);
11884 if (ret)
11885 return ret;
11886
11887 crtc->cursor_x = crtc_x;
11888 crtc->cursor_y = crtc_y;
11889 if (fb != crtc->cursor->fb) {
11890 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
11891 } else {
11892 intel_crtc_update_cursor(crtc, visible);
11893
11894 intel_frontbuffer_flip(crtc->dev,
11895 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe));
11896
11897 return 0;
11898 }
11899 }
11900 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
11901 .update_plane = intel_cursor_plane_update,
11902 .disable_plane = intel_cursor_plane_disable,
11903 .destroy = intel_plane_destroy,
11904 };
11905
11906 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
11907 int pipe)
11908 {
11909 struct intel_plane *cursor;
11910
11911 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
11912 if (cursor == NULL)
11913 return NULL;
11914
11915 cursor->can_scale = false;
11916 cursor->max_downscale = 1;
11917 cursor->pipe = pipe;
11918 cursor->plane = pipe;
11919
11920 drm_universal_plane_init(dev, &cursor->base, 0,
11921 &intel_cursor_plane_funcs,
11922 intel_cursor_formats,
11923 ARRAY_SIZE(intel_cursor_formats),
11924 DRM_PLANE_TYPE_CURSOR);
11925 return &cursor->base;
11926 }
11927
11928 static void intel_crtc_init(struct drm_device *dev, int pipe)
11929 {
11930 struct drm_i915_private *dev_priv = dev->dev_private;
11931 struct intel_crtc *intel_crtc;
11932 struct drm_plane *primary = NULL;
11933 struct drm_plane *cursor = NULL;
11934 int i, ret;
11935
11936 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
11937 if (intel_crtc == NULL)
11938 return;
11939
11940 primary = intel_primary_plane_create(dev, pipe);
11941 if (!primary)
11942 goto fail;
11943
11944 cursor = intel_cursor_plane_create(dev, pipe);
11945 if (!cursor)
11946 goto fail;
11947
11948 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
11949 cursor, &intel_crtc_funcs);
11950 if (ret)
11951 goto fail;
11952
11953 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
11954 for (i = 0; i < 256; i++) {
11955 intel_crtc->lut_r[i] = i;
11956 intel_crtc->lut_g[i] = i;
11957 intel_crtc->lut_b[i] = i;
11958 }
11959
11960 /*
11961 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
11962 * is hooked to pipe B. Hence we want plane A feeding pipe B.
11963 */
11964 intel_crtc->pipe = pipe;
11965 intel_crtc->plane = pipe;
11966 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
11967 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
11968 intel_crtc->plane = !pipe;
11969 }
11970
11971 intel_crtc->cursor_base = ~0;
11972 intel_crtc->cursor_cntl = ~0;
11973 intel_crtc->cursor_size = ~0;
11974
11975 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
11976 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
11977 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
11978 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
11979
11980 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
11981
11982 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
11983 return;
11984
11985 fail:
11986 if (primary)
11987 drm_plane_cleanup(primary);
11988 if (cursor)
11989 drm_plane_cleanup(cursor);
11990 kfree(intel_crtc);
11991 }
11992
11993 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
11994 {
11995 struct drm_encoder *encoder = connector->base.encoder;
11996 struct drm_device *dev = connector->base.dev;
11997
11998 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
11999
12000 if (!encoder)
12001 return INVALID_PIPE;
12002
12003 return to_intel_crtc(encoder->crtc)->pipe;
12004 }
12005
12006 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12007 struct drm_file *file)
12008 {
12009 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12010 struct drm_crtc *drmmode_crtc;
12011 struct intel_crtc *crtc;
12012
12013 if (!drm_core_check_feature(dev, DRIVER_MODESET))
12014 return -ENODEV;
12015
12016 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12017
12018 if (!drmmode_crtc) {
12019 DRM_ERROR("no such CRTC id\n");
12020 return -ENOENT;
12021 }
12022
12023 crtc = to_intel_crtc(drmmode_crtc);
12024 pipe_from_crtc_id->pipe = crtc->pipe;
12025
12026 return 0;
12027 }
12028
12029 static int intel_encoder_clones(struct intel_encoder *encoder)
12030 {
12031 struct drm_device *dev = encoder->base.dev;
12032 struct intel_encoder *source_encoder;
12033 int index_mask = 0;
12034 int entry = 0;
12035
12036 for_each_intel_encoder(dev, source_encoder) {
12037 if (encoders_cloneable(encoder, source_encoder))
12038 index_mask |= (1 << entry);
12039
12040 entry++;
12041 }
12042
12043 return index_mask;
12044 }
12045
12046 static bool has_edp_a(struct drm_device *dev)
12047 {
12048 struct drm_i915_private *dev_priv = dev->dev_private;
12049
12050 if (!IS_MOBILE(dev))
12051 return false;
12052
12053 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12054 return false;
12055
12056 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12057 return false;
12058
12059 return true;
12060 }
12061
12062 const char *intel_output_name(int output)
12063 {
12064 static const char *names[] = {
12065 [INTEL_OUTPUT_UNUSED] = "Unused",
12066 [INTEL_OUTPUT_ANALOG] = "Analog",
12067 [INTEL_OUTPUT_DVO] = "DVO",
12068 [INTEL_OUTPUT_SDVO] = "SDVO",
12069 [INTEL_OUTPUT_LVDS] = "LVDS",
12070 [INTEL_OUTPUT_TVOUT] = "TV",
12071 [INTEL_OUTPUT_HDMI] = "HDMI",
12072 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
12073 [INTEL_OUTPUT_EDP] = "eDP",
12074 [INTEL_OUTPUT_DSI] = "DSI",
12075 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
12076 };
12077
12078 if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
12079 return "Invalid";
12080
12081 return names[output];
12082 }
12083
12084 static bool intel_crt_present(struct drm_device *dev)
12085 {
12086 struct drm_i915_private *dev_priv = dev->dev_private;
12087
12088 if (IS_ULT(dev))
12089 return false;
12090
12091 if (IS_CHERRYVIEW(dev))
12092 return false;
12093
12094 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12095 return false;
12096
12097 return true;
12098 }
12099
12100 static void intel_setup_outputs(struct drm_device *dev)
12101 {
12102 struct drm_i915_private *dev_priv = dev->dev_private;
12103 struct intel_encoder *encoder;
12104 bool dpd_is_edp = false;
12105
12106 intel_lvds_init(dev);
12107
12108 if (intel_crt_present(dev))
12109 intel_crt_init(dev);
12110
12111 if (HAS_DDI(dev)) {
12112 int found;
12113
12114 /* Haswell uses DDI functions to detect digital outputs */
12115 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12116 /* DDI A only supports eDP */
12117 if (found)
12118 intel_ddi_init(dev, PORT_A);
12119
12120 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12121 * register */
12122 found = I915_READ(SFUSE_STRAP);
12123
12124 if (found & SFUSE_STRAP_DDIB_DETECTED)
12125 intel_ddi_init(dev, PORT_B);
12126 if (found & SFUSE_STRAP_DDIC_DETECTED)
12127 intel_ddi_init(dev, PORT_C);
12128 if (found & SFUSE_STRAP_DDID_DETECTED)
12129 intel_ddi_init(dev, PORT_D);
12130 } else if (HAS_PCH_SPLIT(dev)) {
12131 int found;
12132 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12133
12134 if (has_edp_a(dev))
12135 intel_dp_init(dev, DP_A, PORT_A);
12136
12137 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12138 /* PCH SDVOB multiplex with HDMIB */
12139 found = intel_sdvo_init(dev, PCH_SDVOB, true);
12140 if (!found)
12141 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12142 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12143 intel_dp_init(dev, PCH_DP_B, PORT_B);
12144 }
12145
12146 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12147 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12148
12149 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12150 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12151
12152 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12153 intel_dp_init(dev, PCH_DP_C, PORT_C);
12154
12155 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12156 intel_dp_init(dev, PCH_DP_D, PORT_D);
12157 } else if (IS_VALLEYVIEW(dev)) {
12158 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
12159 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12160 PORT_B);
12161 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
12162 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12163 }
12164
12165 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
12166 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12167 PORT_C);
12168 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
12169 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12170 }
12171
12172 if (IS_CHERRYVIEW(dev)) {
12173 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) {
12174 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12175 PORT_D);
12176 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12177 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12178 }
12179 }
12180
12181 intel_dsi_init(dev);
12182 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12183 bool found = false;
12184
12185 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12186 DRM_DEBUG_KMS("probing SDVOB\n");
12187 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12188 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12189 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12190 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12191 }
12192
12193 if (!found && SUPPORTS_INTEGRATED_DP(dev))
12194 intel_dp_init(dev, DP_B, PORT_B);
12195 }
12196
12197 /* Before G4X SDVOC doesn't have its own detect register */
12198
12199 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12200 DRM_DEBUG_KMS("probing SDVOC\n");
12201 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12202 }
12203
12204 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12205
12206 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12207 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12208 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12209 }
12210 if (SUPPORTS_INTEGRATED_DP(dev))
12211 intel_dp_init(dev, DP_C, PORT_C);
12212 }
12213
12214 if (SUPPORTS_INTEGRATED_DP(dev) &&
12215 (I915_READ(DP_D) & DP_DETECTED))
12216 intel_dp_init(dev, DP_D, PORT_D);
12217 } else if (IS_GEN2(dev))
12218 intel_dvo_init(dev);
12219
12220 if (SUPPORTS_TV(dev))
12221 intel_tv_init(dev);
12222
12223 intel_edp_psr_init(dev);
12224
12225 for_each_intel_encoder(dev, encoder) {
12226 encoder->base.possible_crtcs = encoder->crtc_mask;
12227 encoder->base.possible_clones =
12228 intel_encoder_clones(encoder);
12229 }
12230
12231 intel_init_pch_refclk(dev);
12232
12233 drm_helper_move_panel_connectors_to_head(dev);
12234 }
12235
12236 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12237 {
12238 struct drm_device *dev = fb->dev;
12239 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12240
12241 drm_framebuffer_cleanup(fb);
12242 mutex_lock(&dev->struct_mutex);
12243 WARN_ON(!intel_fb->obj->framebuffer_references--);
12244 drm_gem_object_unreference(&intel_fb->obj->base);
12245 mutex_unlock(&dev->struct_mutex);
12246 kfree(intel_fb);
12247 }
12248
12249 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12250 struct drm_file *file,
12251 unsigned int *handle)
12252 {
12253 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12254 struct drm_i915_gem_object *obj = intel_fb->obj;
12255
12256 return drm_gem_handle_create(file, &obj->base, handle);
12257 }
12258
12259 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12260 .destroy = intel_user_framebuffer_destroy,
12261 .create_handle = intel_user_framebuffer_create_handle,
12262 };
12263
12264 static int intel_framebuffer_init(struct drm_device *dev,
12265 struct intel_framebuffer *intel_fb,
12266 struct drm_mode_fb_cmd2 *mode_cmd,
12267 struct drm_i915_gem_object *obj)
12268 {
12269 int aligned_height;
12270 int pitch_limit;
12271 int ret;
12272
12273 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12274
12275 if (obj->tiling_mode == I915_TILING_Y) {
12276 DRM_DEBUG("hardware does not support tiling Y\n");
12277 return -EINVAL;
12278 }
12279
12280 if (mode_cmd->pitches[0] & 63) {
12281 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12282 mode_cmd->pitches[0]);
12283 return -EINVAL;
12284 }
12285
12286 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12287 pitch_limit = 32*1024;
12288 } else if (INTEL_INFO(dev)->gen >= 4) {
12289 if (obj->tiling_mode)
12290 pitch_limit = 16*1024;
12291 else
12292 pitch_limit = 32*1024;
12293 } else if (INTEL_INFO(dev)->gen >= 3) {
12294 if (obj->tiling_mode)
12295 pitch_limit = 8*1024;
12296 else
12297 pitch_limit = 16*1024;
12298 } else
12299 /* XXX DSPC is limited to 4k tiled */
12300 pitch_limit = 8*1024;
12301
12302 if (mode_cmd->pitches[0] > pitch_limit) {
12303 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12304 obj->tiling_mode ? "tiled" : "linear",
12305 mode_cmd->pitches[0], pitch_limit);
12306 return -EINVAL;
12307 }
12308
12309 if (obj->tiling_mode != I915_TILING_NONE &&
12310 mode_cmd->pitches[0] != obj->stride) {
12311 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12312 mode_cmd->pitches[0], obj->stride);
12313 return -EINVAL;
12314 }
12315
12316 /* Reject formats not supported by any plane early. */
12317 switch (mode_cmd->pixel_format) {
12318 case DRM_FORMAT_C8:
12319 case DRM_FORMAT_RGB565:
12320 case DRM_FORMAT_XRGB8888:
12321 case DRM_FORMAT_ARGB8888:
12322 break;
12323 case DRM_FORMAT_XRGB1555:
12324 case DRM_FORMAT_ARGB1555:
12325 if (INTEL_INFO(dev)->gen > 3) {
12326 DRM_DEBUG("unsupported pixel format: %s\n",
12327 drm_get_format_name(mode_cmd->pixel_format));
12328 return -EINVAL;
12329 }
12330 break;
12331 case DRM_FORMAT_XBGR8888:
12332 case DRM_FORMAT_ABGR8888:
12333 case DRM_FORMAT_XRGB2101010:
12334 case DRM_FORMAT_ARGB2101010:
12335 case DRM_FORMAT_XBGR2101010:
12336 case DRM_FORMAT_ABGR2101010:
12337 if (INTEL_INFO(dev)->gen < 4) {
12338 DRM_DEBUG("unsupported pixel format: %s\n",
12339 drm_get_format_name(mode_cmd->pixel_format));
12340 return -EINVAL;
12341 }
12342 break;
12343 case DRM_FORMAT_YUYV:
12344 case DRM_FORMAT_UYVY:
12345 case DRM_FORMAT_YVYU:
12346 case DRM_FORMAT_VYUY:
12347 if (INTEL_INFO(dev)->gen < 5) {
12348 DRM_DEBUG("unsupported pixel format: %s\n",
12349 drm_get_format_name(mode_cmd->pixel_format));
12350 return -EINVAL;
12351 }
12352 break;
12353 default:
12354 DRM_DEBUG("unsupported pixel format: %s\n",
12355 drm_get_format_name(mode_cmd->pixel_format));
12356 return -EINVAL;
12357 }
12358
12359 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12360 if (mode_cmd->offsets[0] != 0)
12361 return -EINVAL;
12362
12363 aligned_height = intel_align_height(dev, mode_cmd->height,
12364 obj->tiling_mode);
12365 /* FIXME drm helper for size checks (especially planar formats)? */
12366 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12367 return -EINVAL;
12368
12369 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12370 intel_fb->obj = obj;
12371 intel_fb->obj->framebuffer_references++;
12372
12373 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12374 if (ret) {
12375 DRM_ERROR("framebuffer init failed %d\n", ret);
12376 return ret;
12377 }
12378
12379 return 0;
12380 }
12381
12382 static struct drm_framebuffer *
12383 intel_user_framebuffer_create(struct drm_device *dev,
12384 struct drm_file *filp,
12385 struct drm_mode_fb_cmd2 *mode_cmd)
12386 {
12387 struct drm_i915_gem_object *obj;
12388
12389 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12390 mode_cmd->handles[0]));
12391 if (&obj->base == NULL)
12392 return ERR_PTR(-ENOENT);
12393
12394 return intel_framebuffer_create(dev, mode_cmd, obj);
12395 }
12396
12397 #ifndef CONFIG_DRM_I915_FBDEV
12398 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12399 {
12400 }
12401 #endif
12402
12403 static const struct drm_mode_config_funcs intel_mode_funcs = {
12404 .fb_create = intel_user_framebuffer_create,
12405 .output_poll_changed = intel_fbdev_output_poll_changed,
12406 };
12407
12408 /* Set up chip specific display functions */
12409 static void intel_init_display(struct drm_device *dev)
12410 {
12411 struct drm_i915_private *dev_priv = dev->dev_private;
12412
12413 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12414 dev_priv->display.find_dpll = g4x_find_best_dpll;
12415 else if (IS_CHERRYVIEW(dev))
12416 dev_priv->display.find_dpll = chv_find_best_dpll;
12417 else if (IS_VALLEYVIEW(dev))
12418 dev_priv->display.find_dpll = vlv_find_best_dpll;
12419 else if (IS_PINEVIEW(dev))
12420 dev_priv->display.find_dpll = pnv_find_best_dpll;
12421 else
12422 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12423
12424 if (HAS_DDI(dev)) {
12425 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12426 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12427 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
12428 dev_priv->display.crtc_enable = haswell_crtc_enable;
12429 dev_priv->display.crtc_disable = haswell_crtc_disable;
12430 dev_priv->display.off = ironlake_crtc_off;
12431 dev_priv->display.update_primary_plane =
12432 ironlake_update_primary_plane;
12433 } else if (HAS_PCH_SPLIT(dev)) {
12434 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12435 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12436 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
12437 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12438 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12439 dev_priv->display.off = ironlake_crtc_off;
12440 dev_priv->display.update_primary_plane =
12441 ironlake_update_primary_plane;
12442 } else if (IS_VALLEYVIEW(dev)) {
12443 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12444 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12445 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12446 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12447 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12448 dev_priv->display.off = i9xx_crtc_off;
12449 dev_priv->display.update_primary_plane =
12450 i9xx_update_primary_plane;
12451 } else {
12452 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12453 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12454 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12455 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12456 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12457 dev_priv->display.off = i9xx_crtc_off;
12458 dev_priv->display.update_primary_plane =
12459 i9xx_update_primary_plane;
12460 }
12461
12462 /* Returns the core display clock speed */
12463 if (IS_VALLEYVIEW(dev))
12464 dev_priv->display.get_display_clock_speed =
12465 valleyview_get_display_clock_speed;
12466 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12467 dev_priv->display.get_display_clock_speed =
12468 i945_get_display_clock_speed;
12469 else if (IS_I915G(dev))
12470 dev_priv->display.get_display_clock_speed =
12471 i915_get_display_clock_speed;
12472 else if (IS_I945GM(dev) || IS_845G(dev))
12473 dev_priv->display.get_display_clock_speed =
12474 i9xx_misc_get_display_clock_speed;
12475 else if (IS_PINEVIEW(dev))
12476 dev_priv->display.get_display_clock_speed =
12477 pnv_get_display_clock_speed;
12478 else if (IS_I915GM(dev))
12479 dev_priv->display.get_display_clock_speed =
12480 i915gm_get_display_clock_speed;
12481 else if (IS_I865G(dev))
12482 dev_priv->display.get_display_clock_speed =
12483 i865_get_display_clock_speed;
12484 else if (IS_I85X(dev))
12485 dev_priv->display.get_display_clock_speed =
12486 i855_get_display_clock_speed;
12487 else /* 852, 830 */
12488 dev_priv->display.get_display_clock_speed =
12489 i830_get_display_clock_speed;
12490
12491 if (IS_G4X(dev)) {
12492 dev_priv->display.write_eld = g4x_write_eld;
12493 } else if (IS_GEN5(dev)) {
12494 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12495 dev_priv->display.write_eld = ironlake_write_eld;
12496 } else if (IS_GEN6(dev)) {
12497 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12498 dev_priv->display.write_eld = ironlake_write_eld;
12499 dev_priv->display.modeset_global_resources =
12500 snb_modeset_global_resources;
12501 } else if (IS_IVYBRIDGE(dev)) {
12502 /* FIXME: detect B0+ stepping and use auto training */
12503 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12504 dev_priv->display.write_eld = ironlake_write_eld;
12505 dev_priv->display.modeset_global_resources =
12506 ivb_modeset_global_resources;
12507 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
12508 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12509 dev_priv->display.write_eld = haswell_write_eld;
12510 dev_priv->display.modeset_global_resources =
12511 haswell_modeset_global_resources;
12512 } else if (IS_VALLEYVIEW(dev)) {
12513 dev_priv->display.modeset_global_resources =
12514 valleyview_modeset_global_resources;
12515 dev_priv->display.write_eld = ironlake_write_eld;
12516 }
12517
12518 /* Default just returns -ENODEV to indicate unsupported */
12519 dev_priv->display.queue_flip = intel_default_queue_flip;
12520
12521 switch (INTEL_INFO(dev)->gen) {
12522 case 2:
12523 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12524 break;
12525
12526 case 3:
12527 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12528 break;
12529
12530 case 4:
12531 case 5:
12532 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12533 break;
12534
12535 case 6:
12536 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12537 break;
12538 case 7:
12539 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12540 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12541 break;
12542 }
12543
12544 intel_panel_init_backlight_funcs(dev);
12545 }
12546
12547 /*
12548 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12549 * resume, or other times. This quirk makes sure that's the case for
12550 * affected systems.
12551 */
12552 static void quirk_pipea_force(struct drm_device *dev)
12553 {
12554 struct drm_i915_private *dev_priv = dev->dev_private;
12555
12556 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12557 DRM_INFO("applying pipe a force quirk\n");
12558 }
12559
12560 /*
12561 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12562 */
12563 static void quirk_ssc_force_disable(struct drm_device *dev)
12564 {
12565 struct drm_i915_private *dev_priv = dev->dev_private;
12566 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12567 DRM_INFO("applying lvds SSC disable quirk\n");
12568 }
12569
12570 /*
12571 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12572 * brightness value
12573 */
12574 static void quirk_invert_brightness(struct drm_device *dev)
12575 {
12576 struct drm_i915_private *dev_priv = dev->dev_private;
12577 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
12578 DRM_INFO("applying inverted panel brightness quirk\n");
12579 }
12580
12581 /* Some VBT's incorrectly indicate no backlight is present */
12582 static void quirk_backlight_present(struct drm_device *dev)
12583 {
12584 struct drm_i915_private *dev_priv = dev->dev_private;
12585 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
12586 DRM_INFO("applying backlight present quirk\n");
12587 }
12588
12589 struct intel_quirk {
12590 int device;
12591 int subsystem_vendor;
12592 int subsystem_device;
12593 void (*hook)(struct drm_device *dev);
12594 };
12595
12596 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12597 struct intel_dmi_quirk {
12598 void (*hook)(struct drm_device *dev);
12599 const struct dmi_system_id (*dmi_id_list)[];
12600 };
12601
12602 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12603 {
12604 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12605 return 1;
12606 }
12607
12608 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12609 {
12610 .dmi_id_list = &(const struct dmi_system_id[]) {
12611 {
12612 .callback = intel_dmi_reverse_brightness,
12613 .ident = "NCR Corporation",
12614 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12615 DMI_MATCH(DMI_PRODUCT_NAME, ""),
12616 },
12617 },
12618 { } /* terminating entry */
12619 },
12620 .hook = quirk_invert_brightness,
12621 },
12622 };
12623
12624 static struct intel_quirk intel_quirks[] = {
12625 /* HP Mini needs pipe A force quirk (LP: #322104) */
12626 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
12627
12628 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12629 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12630
12631 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12632 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12633
12634 /* Lenovo U160 cannot use SSC on LVDS */
12635 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
12636
12637 /* Sony Vaio Y cannot use SSC on LVDS */
12638 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
12639
12640 /* Acer Aspire 5734Z must invert backlight brightness */
12641 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12642
12643 /* Acer/eMachines G725 */
12644 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12645
12646 /* Acer/eMachines e725 */
12647 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12648
12649 /* Acer/Packard Bell NCL20 */
12650 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12651
12652 /* Acer Aspire 4736Z */
12653 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
12654
12655 /* Acer Aspire 5336 */
12656 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
12657
12658 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12659 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
12660
12661 /* Toshiba CB35 Chromebook (Celeron 2955U) */
12662 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
12663
12664 /* HP Chromebook 14 (Celeron 2955U) */
12665 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
12666 };
12667
12668 static void intel_init_quirks(struct drm_device *dev)
12669 {
12670 struct pci_dev *d = dev->pdev;
12671 int i;
12672
12673 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12674 struct intel_quirk *q = &intel_quirks[i];
12675
12676 if (d->device == q->device &&
12677 (d->subsystem_vendor == q->subsystem_vendor ||
12678 q->subsystem_vendor == PCI_ANY_ID) &&
12679 (d->subsystem_device == q->subsystem_device ||
12680 q->subsystem_device == PCI_ANY_ID))
12681 q->hook(dev);
12682 }
12683 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12684 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12685 intel_dmi_quirks[i].hook(dev);
12686 }
12687 }
12688
12689 /* Disable the VGA plane that we never use */
12690 static void i915_disable_vga(struct drm_device *dev)
12691 {
12692 struct drm_i915_private *dev_priv = dev->dev_private;
12693 u8 sr1;
12694 u32 vga_reg = i915_vgacntrl_reg(dev);
12695
12696 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12697 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
12698 outb(SR01, VGA_SR_INDEX);
12699 sr1 = inb(VGA_SR_DATA);
12700 outb(sr1 | 1<<5, VGA_SR_DATA);
12701 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12702 udelay(300);
12703
12704 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
12705 POSTING_READ(vga_reg);
12706 }
12707
12708 void intel_modeset_init_hw(struct drm_device *dev)
12709 {
12710 intel_prepare_ddi(dev);
12711
12712 if (IS_VALLEYVIEW(dev))
12713 vlv_update_cdclk(dev);
12714
12715 intel_init_clock_gating(dev);
12716
12717 intel_enable_gt_powersave(dev);
12718 }
12719
12720 void intel_modeset_suspend_hw(struct drm_device *dev)
12721 {
12722 intel_suspend_hw(dev);
12723 }
12724
12725 void intel_modeset_init(struct drm_device *dev)
12726 {
12727 struct drm_i915_private *dev_priv = dev->dev_private;
12728 int sprite, ret;
12729 enum pipe pipe;
12730 struct intel_crtc *crtc;
12731
12732 drm_mode_config_init(dev);
12733
12734 dev->mode_config.min_width = 0;
12735 dev->mode_config.min_height = 0;
12736
12737 dev->mode_config.preferred_depth = 24;
12738 dev->mode_config.prefer_shadow = 1;
12739
12740 dev->mode_config.funcs = &intel_mode_funcs;
12741
12742 intel_init_quirks(dev);
12743
12744 intel_init_pm(dev);
12745
12746 if (INTEL_INFO(dev)->num_pipes == 0)
12747 return;
12748
12749 intel_init_display(dev);
12750
12751 if (IS_GEN2(dev)) {
12752 dev->mode_config.max_width = 2048;
12753 dev->mode_config.max_height = 2048;
12754 } else if (IS_GEN3(dev)) {
12755 dev->mode_config.max_width = 4096;
12756 dev->mode_config.max_height = 4096;
12757 } else {
12758 dev->mode_config.max_width = 8192;
12759 dev->mode_config.max_height = 8192;
12760 }
12761
12762 if (IS_845G(dev) || IS_I865G(dev)) {
12763 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
12764 dev->mode_config.cursor_height = 1023;
12765 } else if (IS_GEN2(dev)) {
12766 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
12767 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
12768 } else {
12769 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
12770 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
12771 }
12772
12773 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
12774
12775 DRM_DEBUG_KMS("%d display pipe%s available.\n",
12776 INTEL_INFO(dev)->num_pipes,
12777 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
12778
12779 for_each_pipe(dev_priv, pipe) {
12780 intel_crtc_init(dev, pipe);
12781 for_each_sprite(pipe, sprite) {
12782 ret = intel_plane_init(dev, pipe, sprite);
12783 if (ret)
12784 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
12785 pipe_name(pipe), sprite_name(pipe, sprite), ret);
12786 }
12787 }
12788
12789 intel_init_dpio(dev);
12790
12791 intel_shared_dpll_init(dev);
12792
12793 /* Just disable it once at startup */
12794 i915_disable_vga(dev);
12795 intel_setup_outputs(dev);
12796
12797 /* Just in case the BIOS is doing something questionable. */
12798 intel_disable_fbc(dev);
12799
12800 drm_modeset_lock_all(dev);
12801 intel_modeset_setup_hw_state(dev, false);
12802 drm_modeset_unlock_all(dev);
12803
12804 for_each_intel_crtc(dev, crtc) {
12805 if (!crtc->active)
12806 continue;
12807
12808 /*
12809 * Note that reserving the BIOS fb up front prevents us
12810 * from stuffing other stolen allocations like the ring
12811 * on top. This prevents some ugliness at boot time, and
12812 * can even allow for smooth boot transitions if the BIOS
12813 * fb is large enough for the active pipe configuration.
12814 */
12815 if (dev_priv->display.get_plane_config) {
12816 dev_priv->display.get_plane_config(crtc,
12817 &crtc->plane_config);
12818 /*
12819 * If the fb is shared between multiple heads, we'll
12820 * just get the first one.
12821 */
12822 intel_find_plane_obj(crtc, &crtc->plane_config);
12823 }
12824 }
12825 }
12826
12827 static void intel_enable_pipe_a(struct drm_device *dev)
12828 {
12829 struct intel_connector *connector;
12830 struct drm_connector *crt = NULL;
12831 struct intel_load_detect_pipe load_detect_temp;
12832 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
12833
12834 /* We can't just switch on the pipe A, we need to set things up with a
12835 * proper mode and output configuration. As a gross hack, enable pipe A
12836 * by enabling the load detect pipe once. */
12837 list_for_each_entry(connector,
12838 &dev->mode_config.connector_list,
12839 base.head) {
12840 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
12841 crt = &connector->base;
12842 break;
12843 }
12844 }
12845
12846 if (!crt)
12847 return;
12848
12849 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
12850 intel_release_load_detect_pipe(crt, &load_detect_temp);
12851 }
12852
12853 static bool
12854 intel_check_plane_mapping(struct intel_crtc *crtc)
12855 {
12856 struct drm_device *dev = crtc->base.dev;
12857 struct drm_i915_private *dev_priv = dev->dev_private;
12858 u32 reg, val;
12859
12860 if (INTEL_INFO(dev)->num_pipes == 1)
12861 return true;
12862
12863 reg = DSPCNTR(!crtc->plane);
12864 val = I915_READ(reg);
12865
12866 if ((val & DISPLAY_PLANE_ENABLE) &&
12867 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
12868 return false;
12869
12870 return true;
12871 }
12872
12873 static void intel_sanitize_crtc(struct intel_crtc *crtc)
12874 {
12875 struct drm_device *dev = crtc->base.dev;
12876 struct drm_i915_private *dev_priv = dev->dev_private;
12877 u32 reg;
12878
12879 /* Clear any frame start delays used for debugging left by the BIOS */
12880 reg = PIPECONF(crtc->config.cpu_transcoder);
12881 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
12882
12883 /* restore vblank interrupts to correct state */
12884 if (crtc->active)
12885 drm_vblank_on(dev, crtc->pipe);
12886 else
12887 drm_vblank_off(dev, crtc->pipe);
12888
12889 /* We need to sanitize the plane -> pipe mapping first because this will
12890 * disable the crtc (and hence change the state) if it is wrong. Note
12891 * that gen4+ has a fixed plane -> pipe mapping. */
12892 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
12893 struct intel_connector *connector;
12894 bool plane;
12895
12896 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
12897 crtc->base.base.id);
12898
12899 /* Pipe has the wrong plane attached and the plane is active.
12900 * Temporarily change the plane mapping and disable everything
12901 * ... */
12902 plane = crtc->plane;
12903 crtc->plane = !plane;
12904 crtc->primary_enabled = true;
12905 dev_priv->display.crtc_disable(&crtc->base);
12906 crtc->plane = plane;
12907
12908 /* ... and break all links. */
12909 list_for_each_entry(connector, &dev->mode_config.connector_list,
12910 base.head) {
12911 if (connector->encoder->base.crtc != &crtc->base)
12912 continue;
12913
12914 connector->base.dpms = DRM_MODE_DPMS_OFF;
12915 connector->base.encoder = NULL;
12916 }
12917 /* multiple connectors may have the same encoder:
12918 * handle them and break crtc link separately */
12919 list_for_each_entry(connector, &dev->mode_config.connector_list,
12920 base.head)
12921 if (connector->encoder->base.crtc == &crtc->base) {
12922 connector->encoder->base.crtc = NULL;
12923 connector->encoder->connectors_active = false;
12924 }
12925
12926 WARN_ON(crtc->active);
12927 crtc->base.enabled = false;
12928 }
12929
12930 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
12931 crtc->pipe == PIPE_A && !crtc->active) {
12932 /* BIOS forgot to enable pipe A, this mostly happens after
12933 * resume. Force-enable the pipe to fix this, the update_dpms
12934 * call below we restore the pipe to the right state, but leave
12935 * the required bits on. */
12936 intel_enable_pipe_a(dev);
12937 }
12938
12939 /* Adjust the state of the output pipe according to whether we
12940 * have active connectors/encoders. */
12941 intel_crtc_update_dpms(&crtc->base);
12942
12943 if (crtc->active != crtc->base.enabled) {
12944 struct intel_encoder *encoder;
12945
12946 /* This can happen either due to bugs in the get_hw_state
12947 * functions or because the pipe is force-enabled due to the
12948 * pipe A quirk. */
12949 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
12950 crtc->base.base.id,
12951 crtc->base.enabled ? "enabled" : "disabled",
12952 crtc->active ? "enabled" : "disabled");
12953
12954 crtc->base.enabled = crtc->active;
12955
12956 /* Because we only establish the connector -> encoder ->
12957 * crtc links if something is active, this means the
12958 * crtc is now deactivated. Break the links. connector
12959 * -> encoder links are only establish when things are
12960 * actually up, hence no need to break them. */
12961 WARN_ON(crtc->active);
12962
12963 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
12964 WARN_ON(encoder->connectors_active);
12965 encoder->base.crtc = NULL;
12966 }
12967 }
12968
12969 if (crtc->active || IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen < 5) {
12970 /*
12971 * We start out with underrun reporting disabled to avoid races.
12972 * For correct bookkeeping mark this on active crtcs.
12973 *
12974 * Also on gmch platforms we dont have any hardware bits to
12975 * disable the underrun reporting. Which means we need to start
12976 * out with underrun reporting disabled also on inactive pipes,
12977 * since otherwise we'll complain about the garbage we read when
12978 * e.g. coming up after runtime pm.
12979 *
12980 * No protection against concurrent access is required - at
12981 * worst a fifo underrun happens which also sets this to false.
12982 */
12983 crtc->cpu_fifo_underrun_disabled = true;
12984 crtc->pch_fifo_underrun_disabled = true;
12985
12986 update_scanline_offset(crtc);
12987 }
12988 }
12989
12990 static void intel_sanitize_encoder(struct intel_encoder *encoder)
12991 {
12992 struct intel_connector *connector;
12993 struct drm_device *dev = encoder->base.dev;
12994
12995 /* We need to check both for a crtc link (meaning that the
12996 * encoder is active and trying to read from a pipe) and the
12997 * pipe itself being active. */
12998 bool has_active_crtc = encoder->base.crtc &&
12999 to_intel_crtc(encoder->base.crtc)->active;
13000
13001 if (encoder->connectors_active && !has_active_crtc) {
13002 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13003 encoder->base.base.id,
13004 encoder->base.name);
13005
13006 /* Connector is active, but has no active pipe. This is
13007 * fallout from our resume register restoring. Disable
13008 * the encoder manually again. */
13009 if (encoder->base.crtc) {
13010 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13011 encoder->base.base.id,
13012 encoder->base.name);
13013 encoder->disable(encoder);
13014 if (encoder->post_disable)
13015 encoder->post_disable(encoder);
13016 }
13017 encoder->base.crtc = NULL;
13018 encoder->connectors_active = false;
13019
13020 /* Inconsistent output/port/pipe state happens presumably due to
13021 * a bug in one of the get_hw_state functions. Or someplace else
13022 * in our code, like the register restore mess on resume. Clamp
13023 * things to off as a safer default. */
13024 list_for_each_entry(connector,
13025 &dev->mode_config.connector_list,
13026 base.head) {
13027 if (connector->encoder != encoder)
13028 continue;
13029 connector->base.dpms = DRM_MODE_DPMS_OFF;
13030 connector->base.encoder = NULL;
13031 }
13032 }
13033 /* Enabled encoders without active connectors will be fixed in
13034 * the crtc fixup. */
13035 }
13036
13037 void i915_redisable_vga_power_on(struct drm_device *dev)
13038 {
13039 struct drm_i915_private *dev_priv = dev->dev_private;
13040 u32 vga_reg = i915_vgacntrl_reg(dev);
13041
13042 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13043 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13044 i915_disable_vga(dev);
13045 }
13046 }
13047
13048 void i915_redisable_vga(struct drm_device *dev)
13049 {
13050 struct drm_i915_private *dev_priv = dev->dev_private;
13051
13052 /* This function can be called both from intel_modeset_setup_hw_state or
13053 * at a very early point in our resume sequence, where the power well
13054 * structures are not yet restored. Since this function is at a very
13055 * paranoid "someone might have enabled VGA while we were not looking"
13056 * level, just check if the power well is enabled instead of trying to
13057 * follow the "don't touch the power well if we don't need it" policy
13058 * the rest of the driver uses. */
13059 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
13060 return;
13061
13062 i915_redisable_vga_power_on(dev);
13063 }
13064
13065 static bool primary_get_hw_state(struct intel_crtc *crtc)
13066 {
13067 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13068
13069 if (!crtc->active)
13070 return false;
13071
13072 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13073 }
13074
13075 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13076 {
13077 struct drm_i915_private *dev_priv = dev->dev_private;
13078 enum pipe pipe;
13079 struct intel_crtc *crtc;
13080 struct intel_encoder *encoder;
13081 struct intel_connector *connector;
13082 int i;
13083
13084 for_each_intel_crtc(dev, crtc) {
13085 memset(&crtc->config, 0, sizeof(crtc->config));
13086
13087 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13088
13089 crtc->active = dev_priv->display.get_pipe_config(crtc,
13090 &crtc->config);
13091
13092 crtc->base.enabled = crtc->active;
13093 crtc->primary_enabled = primary_get_hw_state(crtc);
13094
13095 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13096 crtc->base.base.id,
13097 crtc->active ? "enabled" : "disabled");
13098 }
13099
13100 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13101 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13102
13103 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
13104 pll->active = 0;
13105 for_each_intel_crtc(dev, crtc) {
13106 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
13107 pll->active++;
13108 }
13109 pll->refcount = pll->active;
13110
13111 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
13112 pll->name, pll->refcount, pll->on);
13113
13114 if (pll->refcount)
13115 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13116 }
13117
13118 for_each_intel_encoder(dev, encoder) {
13119 pipe = 0;
13120
13121 if (encoder->get_hw_state(encoder, &pipe)) {
13122 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13123 encoder->base.crtc = &crtc->base;
13124 encoder->get_config(encoder, &crtc->config);
13125 } else {
13126 encoder->base.crtc = NULL;
13127 }
13128
13129 encoder->connectors_active = false;
13130 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13131 encoder->base.base.id,
13132 encoder->base.name,
13133 encoder->base.crtc ? "enabled" : "disabled",
13134 pipe_name(pipe));
13135 }
13136
13137 list_for_each_entry(connector, &dev->mode_config.connector_list,
13138 base.head) {
13139 if (connector->get_hw_state(connector)) {
13140 connector->base.dpms = DRM_MODE_DPMS_ON;
13141 connector->encoder->connectors_active = true;
13142 connector->base.encoder = &connector->encoder->base;
13143 } else {
13144 connector->base.dpms = DRM_MODE_DPMS_OFF;
13145 connector->base.encoder = NULL;
13146 }
13147 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13148 connector->base.base.id,
13149 connector->base.name,
13150 connector->base.encoder ? "enabled" : "disabled");
13151 }
13152 }
13153
13154 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13155 * and i915 state tracking structures. */
13156 void intel_modeset_setup_hw_state(struct drm_device *dev,
13157 bool force_restore)
13158 {
13159 struct drm_i915_private *dev_priv = dev->dev_private;
13160 enum pipe pipe;
13161 struct intel_crtc *crtc;
13162 struct intel_encoder *encoder;
13163 int i;
13164
13165 intel_modeset_readout_hw_state(dev);
13166
13167 /*
13168 * Now that we have the config, copy it to each CRTC struct
13169 * Note that this could go away if we move to using crtc_config
13170 * checking everywhere.
13171 */
13172 for_each_intel_crtc(dev, crtc) {
13173 if (crtc->active && i915.fastboot) {
13174 intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
13175 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13176 crtc->base.base.id);
13177 drm_mode_debug_printmodeline(&crtc->base.mode);
13178 }
13179 }
13180
13181 /* HW state is read out, now we need to sanitize this mess. */
13182 for_each_intel_encoder(dev, encoder) {
13183 intel_sanitize_encoder(encoder);
13184 }
13185
13186 for_each_pipe(dev_priv, pipe) {
13187 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13188 intel_sanitize_crtc(crtc);
13189 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
13190 }
13191
13192 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13193 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13194
13195 if (!pll->on || pll->active)
13196 continue;
13197
13198 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13199
13200 pll->disable(dev_priv, pll);
13201 pll->on = false;
13202 }
13203
13204 if (HAS_PCH_SPLIT(dev))
13205 ilk_wm_get_hw_state(dev);
13206
13207 if (force_restore) {
13208 i915_redisable_vga(dev);
13209
13210 /*
13211 * We need to use raw interfaces for restoring state to avoid
13212 * checking (bogus) intermediate states.
13213 */
13214 for_each_pipe(dev_priv, pipe) {
13215 struct drm_crtc *crtc =
13216 dev_priv->pipe_to_crtc_mapping[pipe];
13217
13218 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13219 crtc->primary->fb);
13220 }
13221 } else {
13222 intel_modeset_update_staged_output_state(dev);
13223 }
13224
13225 intel_modeset_check_state(dev);
13226 }
13227
13228 void intel_modeset_gem_init(struct drm_device *dev)
13229 {
13230 struct drm_crtc *c;
13231 struct drm_i915_gem_object *obj;
13232
13233 mutex_lock(&dev->struct_mutex);
13234 intel_init_gt_powersave(dev);
13235 mutex_unlock(&dev->struct_mutex);
13236
13237 intel_modeset_init_hw(dev);
13238
13239 intel_setup_overlay(dev);
13240
13241 /*
13242 * Make sure any fbs we allocated at startup are properly
13243 * pinned & fenced. When we do the allocation it's too early
13244 * for this.
13245 */
13246 mutex_lock(&dev->struct_mutex);
13247 for_each_crtc(dev, c) {
13248 obj = intel_fb_obj(c->primary->fb);
13249 if (obj == NULL)
13250 continue;
13251
13252 if (intel_pin_and_fence_fb_obj(dev, obj, NULL)) {
13253 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13254 to_intel_crtc(c)->pipe);
13255 drm_framebuffer_unreference(c->primary->fb);
13256 c->primary->fb = NULL;
13257 }
13258 }
13259 mutex_unlock(&dev->struct_mutex);
13260 }
13261
13262 void intel_connector_unregister(struct intel_connector *intel_connector)
13263 {
13264 struct drm_connector *connector = &intel_connector->base;
13265
13266 intel_panel_destroy_backlight(connector);
13267 drm_connector_unregister(connector);
13268 }
13269
13270 void intel_modeset_cleanup(struct drm_device *dev)
13271 {
13272 struct drm_i915_private *dev_priv = dev->dev_private;
13273 struct drm_connector *connector;
13274
13275 /*
13276 * Interrupts and polling as the first thing to avoid creating havoc.
13277 * Too much stuff here (turning of rps, connectors, ...) would
13278 * experience fancy races otherwise.
13279 */
13280 drm_irq_uninstall(dev);
13281 intel_hpd_cancel_work(dev_priv);
13282 dev_priv->pm._irqs_disabled = true;
13283
13284 /*
13285 * Due to the hpd irq storm handling the hotplug work can re-arm the
13286 * poll handlers. Hence disable polling after hpd handling is shut down.
13287 */
13288 drm_kms_helper_poll_fini(dev);
13289
13290 mutex_lock(&dev->struct_mutex);
13291
13292 intel_unregister_dsm_handler();
13293
13294 intel_disable_fbc(dev);
13295
13296 intel_disable_gt_powersave(dev);
13297
13298 ironlake_teardown_rc6(dev);
13299
13300 mutex_unlock(&dev->struct_mutex);
13301
13302 /* flush any delayed tasks or pending work */
13303 flush_scheduled_work();
13304
13305 /* destroy the backlight and sysfs files before encoders/connectors */
13306 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13307 struct intel_connector *intel_connector;
13308
13309 intel_connector = to_intel_connector(connector);
13310 intel_connector->unregister(intel_connector);
13311 }
13312
13313 drm_mode_config_cleanup(dev);
13314
13315 intel_cleanup_overlay(dev);
13316
13317 mutex_lock(&dev->struct_mutex);
13318 intel_cleanup_gt_powersave(dev);
13319 mutex_unlock(&dev->struct_mutex);
13320 }
13321
13322 /*
13323 * Return which encoder is currently attached for connector.
13324 */
13325 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13326 {
13327 return &intel_attached_encoder(connector)->base;
13328 }
13329
13330 void intel_connector_attach_encoder(struct intel_connector *connector,
13331 struct intel_encoder *encoder)
13332 {
13333 connector->encoder = encoder;
13334 drm_mode_connector_attach_encoder(&connector->base,
13335 &encoder->base);
13336 }
13337
13338 /*
13339 * set vga decode state - true == enable VGA decode
13340 */
13341 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13342 {
13343 struct drm_i915_private *dev_priv = dev->dev_private;
13344 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13345 u16 gmch_ctrl;
13346
13347 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13348 DRM_ERROR("failed to read control word\n");
13349 return -EIO;
13350 }
13351
13352 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13353 return 0;
13354
13355 if (state)
13356 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13357 else
13358 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13359
13360 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13361 DRM_ERROR("failed to write control word\n");
13362 return -EIO;
13363 }
13364
13365 return 0;
13366 }
13367
13368 struct intel_display_error_state {
13369
13370 u32 power_well_driver;
13371
13372 int num_transcoders;
13373
13374 struct intel_cursor_error_state {
13375 u32 control;
13376 u32 position;
13377 u32 base;
13378 u32 size;
13379 } cursor[I915_MAX_PIPES];
13380
13381 struct intel_pipe_error_state {
13382 bool power_domain_on;
13383 u32 source;
13384 u32 stat;
13385 } pipe[I915_MAX_PIPES];
13386
13387 struct intel_plane_error_state {
13388 u32 control;
13389 u32 stride;
13390 u32 size;
13391 u32 pos;
13392 u32 addr;
13393 u32 surface;
13394 u32 tile_offset;
13395 } plane[I915_MAX_PIPES];
13396
13397 struct intel_transcoder_error_state {
13398 bool power_domain_on;
13399 enum transcoder cpu_transcoder;
13400
13401 u32 conf;
13402
13403 u32 htotal;
13404 u32 hblank;
13405 u32 hsync;
13406 u32 vtotal;
13407 u32 vblank;
13408 u32 vsync;
13409 } transcoder[4];
13410 };
13411
13412 struct intel_display_error_state *
13413 intel_display_capture_error_state(struct drm_device *dev)
13414 {
13415 struct drm_i915_private *dev_priv = dev->dev_private;
13416 struct intel_display_error_state *error;
13417 int transcoders[] = {
13418 TRANSCODER_A,
13419 TRANSCODER_B,
13420 TRANSCODER_C,
13421 TRANSCODER_EDP,
13422 };
13423 int i;
13424
13425 if (INTEL_INFO(dev)->num_pipes == 0)
13426 return NULL;
13427
13428 error = kzalloc(sizeof(*error), GFP_ATOMIC);
13429 if (error == NULL)
13430 return NULL;
13431
13432 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13433 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13434
13435 for_each_pipe(dev_priv, i) {
13436 error->pipe[i].power_domain_on =
13437 intel_display_power_enabled_unlocked(dev_priv,
13438 POWER_DOMAIN_PIPE(i));
13439 if (!error->pipe[i].power_domain_on)
13440 continue;
13441
13442 error->cursor[i].control = I915_READ(CURCNTR(i));
13443 error->cursor[i].position = I915_READ(CURPOS(i));
13444 error->cursor[i].base = I915_READ(CURBASE(i));
13445
13446 error->plane[i].control = I915_READ(DSPCNTR(i));
13447 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13448 if (INTEL_INFO(dev)->gen <= 3) {
13449 error->plane[i].size = I915_READ(DSPSIZE(i));
13450 error->plane[i].pos = I915_READ(DSPPOS(i));
13451 }
13452 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13453 error->plane[i].addr = I915_READ(DSPADDR(i));
13454 if (INTEL_INFO(dev)->gen >= 4) {
13455 error->plane[i].surface = I915_READ(DSPSURF(i));
13456 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13457 }
13458
13459 error->pipe[i].source = I915_READ(PIPESRC(i));
13460
13461 if (HAS_GMCH_DISPLAY(dev))
13462 error->pipe[i].stat = I915_READ(PIPESTAT(i));
13463 }
13464
13465 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13466 if (HAS_DDI(dev_priv->dev))
13467 error->num_transcoders++; /* Account for eDP. */
13468
13469 for (i = 0; i < error->num_transcoders; i++) {
13470 enum transcoder cpu_transcoder = transcoders[i];
13471
13472 error->transcoder[i].power_domain_on =
13473 intel_display_power_enabled_unlocked(dev_priv,
13474 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13475 if (!error->transcoder[i].power_domain_on)
13476 continue;
13477
13478 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13479
13480 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13481 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13482 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13483 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13484 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13485 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13486 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13487 }
13488
13489 return error;
13490 }
13491
13492 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13493
13494 void
13495 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13496 struct drm_device *dev,
13497 struct intel_display_error_state *error)
13498 {
13499 struct drm_i915_private *dev_priv = dev->dev_private;
13500 int i;
13501
13502 if (!error)
13503 return;
13504
13505 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13506 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13507 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13508 error->power_well_driver);
13509 for_each_pipe(dev_priv, i) {
13510 err_printf(m, "Pipe [%d]:\n", i);
13511 err_printf(m, " Power: %s\n",
13512 error->pipe[i].power_domain_on ? "on" : "off");
13513 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
13514 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
13515
13516 err_printf(m, "Plane [%d]:\n", i);
13517 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
13518 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
13519 if (INTEL_INFO(dev)->gen <= 3) {
13520 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
13521 err_printf(m, " POS: %08x\n", error->plane[i].pos);
13522 }
13523 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13524 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
13525 if (INTEL_INFO(dev)->gen >= 4) {
13526 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
13527 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
13528 }
13529
13530 err_printf(m, "Cursor [%d]:\n", i);
13531 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
13532 err_printf(m, " POS: %08x\n", error->cursor[i].position);
13533 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
13534 }
13535
13536 for (i = 0; i < error->num_transcoders; i++) {
13537 err_printf(m, "CPU transcoder: %c\n",
13538 transcoder_name(error->transcoder[i].cpu_transcoder));
13539 err_printf(m, " Power: %s\n",
13540 error->transcoder[i].power_domain_on ? "on" : "off");
13541 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
13542 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
13543 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
13544 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
13545 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
13546 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
13547 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
13548 }
13549 }
13550
13551 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
13552 {
13553 struct intel_crtc *crtc;
13554
13555 for_each_intel_crtc(dev, crtc) {
13556 struct intel_unpin_work *work;
13557 unsigned long irqflags;
13558
13559 spin_lock_irqsave(&dev->event_lock, irqflags);
13560
13561 work = crtc->unpin_work;
13562
13563 if (work && work->event &&
13564 work->event->base.file_priv == file) {
13565 kfree(work->event);
13566 work->event = NULL;
13567 }
13568
13569 spin_unlock_irqrestore(&dev->event_lock, irqflags);
13570 }
13571 }
Linux kernel - Deliverables
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