projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
drm/i915: Clarify event_lock locking, process context
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_rect.h>
44 #include <linux/dma_remapping.h>
45
46 /* Primary plane formats supported by all gen */
47 #define COMMON_PRIMARY_FORMATS \
48 DRM_FORMAT_C8, \
49 DRM_FORMAT_RGB565, \
50 DRM_FORMAT_XRGB8888, \
51 DRM_FORMAT_ARGB8888
52
53 /* Primary plane formats for gen <= 3 */
54 static const uint32_t intel_primary_formats_gen2[] = {
55 COMMON_PRIMARY_FORMATS,
56 DRM_FORMAT_XRGB1555,
57 DRM_FORMAT_ARGB1555,
58 };
59
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t intel_primary_formats_gen4[] = {
62 COMMON_PRIMARY_FORMATS, \
63 DRM_FORMAT_XBGR8888,
64 DRM_FORMAT_ABGR8888,
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_ARGB2101010,
67 DRM_FORMAT_XBGR2101010,
68 DRM_FORMAT_ABGR2101010,
69 };
70
71 /* Cursor formats */
72 static const uint32_t intel_cursor_formats[] = {
73 DRM_FORMAT_ARGB8888,
74 };
75
76 #define DIV_ROUND_CLOSEST_ULL(ll, d) \
77 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
78
79 static void intel_increase_pllclock(struct drm_device *dev,
80 enum pipe pipe);
81 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
82
83 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
84 struct intel_crtc_config *pipe_config);
85 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
86 struct intel_crtc_config *pipe_config);
87
88 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
89 int x, int y, struct drm_framebuffer *old_fb);
90 static int intel_framebuffer_init(struct drm_device *dev,
91 struct intel_framebuffer *ifb,
92 struct drm_mode_fb_cmd2 *mode_cmd,
93 struct drm_i915_gem_object *obj);
94 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
95 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
96 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
97 struct intel_link_m_n *m_n,
98 struct intel_link_m_n *m2_n2);
99 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
100 static void haswell_set_pipeconf(struct drm_crtc *crtc);
101 static void intel_set_pipe_csc(struct drm_crtc *crtc);
102 static void vlv_prepare_pll(struct intel_crtc *crtc);
103 static void chv_prepare_pll(struct intel_crtc *crtc);
104
105 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
106 {
107 if (!connector->mst_port)
108 return connector->encoder;
109 else
110 return &connector->mst_port->mst_encoders[pipe]->base;
111 }
112
113 typedef struct {
114 int min, max;
115 } intel_range_t;
116
117 typedef struct {
118 int dot_limit;
119 int p2_slow, p2_fast;
120 } intel_p2_t;
121
122 typedef struct intel_limit intel_limit_t;
123 struct intel_limit {
124 intel_range_t dot, vco, n, m, m1, m2, p, p1;
125 intel_p2_t p2;
126 };
127
128 int
129 intel_pch_rawclk(struct drm_device *dev)
130 {
131 struct drm_i915_private *dev_priv = dev->dev_private;
132
133 WARN_ON(!HAS_PCH_SPLIT(dev));
134
135 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
136 }
137
138 static inline u32 /* units of 100MHz */
139 intel_fdi_link_freq(struct drm_device *dev)
140 {
141 if (IS_GEN5(dev)) {
142 struct drm_i915_private *dev_priv = dev->dev_private;
143 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
144 } else
145 return 27;
146 }
147
148 static const intel_limit_t intel_limits_i8xx_dac = {
149 .dot = { .min = 25000, .max = 350000 },
150 .vco = { .min = 908000, .max = 1512000 },
151 .n = { .min = 2, .max = 16 },
152 .m = { .min = 96, .max = 140 },
153 .m1 = { .min = 18, .max = 26 },
154 .m2 = { .min = 6, .max = 16 },
155 .p = { .min = 4, .max = 128 },
156 .p1 = { .min = 2, .max = 33 },
157 .p2 = { .dot_limit = 165000,
158 .p2_slow = 4, .p2_fast = 2 },
159 };
160
161 static const intel_limit_t intel_limits_i8xx_dvo = {
162 .dot = { .min = 25000, .max = 350000 },
163 .vco = { .min = 908000, .max = 1512000 },
164 .n = { .min = 2, .max = 16 },
165 .m = { .min = 96, .max = 140 },
166 .m1 = { .min = 18, .max = 26 },
167 .m2 = { .min = 6, .max = 16 },
168 .p = { .min = 4, .max = 128 },
169 .p1 = { .min = 2, .max = 33 },
170 .p2 = { .dot_limit = 165000,
171 .p2_slow = 4, .p2_fast = 4 },
172 };
173
174 static const intel_limit_t intel_limits_i8xx_lvds = {
175 .dot = { .min = 25000, .max = 350000 },
176 .vco = { .min = 908000, .max = 1512000 },
177 .n = { .min = 2, .max = 16 },
178 .m = { .min = 96, .max = 140 },
179 .m1 = { .min = 18, .max = 26 },
180 .m2 = { .min = 6, .max = 16 },
181 .p = { .min = 4, .max = 128 },
182 .p1 = { .min = 1, .max = 6 },
183 .p2 = { .dot_limit = 165000,
184 .p2_slow = 14, .p2_fast = 7 },
185 };
186
187 static const intel_limit_t intel_limits_i9xx_sdvo = {
188 .dot = { .min = 20000, .max = 400000 },
189 .vco = { .min = 1400000, .max = 2800000 },
190 .n = { .min = 1, .max = 6 },
191 .m = { .min = 70, .max = 120 },
192 .m1 = { .min = 8, .max = 18 },
193 .m2 = { .min = 3, .max = 7 },
194 .p = { .min = 5, .max = 80 },
195 .p1 = { .min = 1, .max = 8 },
196 .p2 = { .dot_limit = 200000,
197 .p2_slow = 10, .p2_fast = 5 },
198 };
199
200 static const intel_limit_t intel_limits_i9xx_lvds = {
201 .dot = { .min = 20000, .max = 400000 },
202 .vco = { .min = 1400000, .max = 2800000 },
203 .n = { .min = 1, .max = 6 },
204 .m = { .min = 70, .max = 120 },
205 .m1 = { .min = 8, .max = 18 },
206 .m2 = { .min = 3, .max = 7 },
207 .p = { .min = 7, .max = 98 },
208 .p1 = { .min = 1, .max = 8 },
209 .p2 = { .dot_limit = 112000,
210 .p2_slow = 14, .p2_fast = 7 },
211 };
212
213
214 static const intel_limit_t intel_limits_g4x_sdvo = {
215 .dot = { .min = 25000, .max = 270000 },
216 .vco = { .min = 1750000, .max = 3500000},
217 .n = { .min = 1, .max = 4 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 10, .max = 30 },
222 .p1 = { .min = 1, .max = 3},
223 .p2 = { .dot_limit = 270000,
224 .p2_slow = 10,
225 .p2_fast = 10
226 },
227 };
228
229 static const intel_limit_t intel_limits_g4x_hdmi = {
230 .dot = { .min = 22000, .max = 400000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 4 },
233 .m = { .min = 104, .max = 138 },
234 .m1 = { .min = 16, .max = 23 },
235 .m2 = { .min = 5, .max = 11 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8},
238 .p2 = { .dot_limit = 165000,
239 .p2_slow = 10, .p2_fast = 5 },
240 };
241
242 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
243 .dot = { .min = 20000, .max = 115000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 14, .p2_fast = 14
253 },
254 };
255
256 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
257 .dot = { .min = 80000, .max = 224000 },
258 .vco = { .min = 1750000, .max = 3500000 },
259 .n = { .min = 1, .max = 3 },
260 .m = { .min = 104, .max = 138 },
261 .m1 = { .min = 17, .max = 23 },
262 .m2 = { .min = 5, .max = 11 },
263 .p = { .min = 14, .max = 42 },
264 .p1 = { .min = 2, .max = 6 },
265 .p2 = { .dot_limit = 0,
266 .p2_slow = 7, .p2_fast = 7
267 },
268 };
269
270 static const intel_limit_t intel_limits_pineview_sdvo = {
271 .dot = { .min = 20000, .max = 400000},
272 .vco = { .min = 1700000, .max = 3500000 },
273 /* Pineview's Ncounter is a ring counter */
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 /* Pineview only has one combined m divider, which we treat as m2. */
277 .m1 = { .min = 0, .max = 0 },
278 .m2 = { .min = 0, .max = 254 },
279 .p = { .min = 5, .max = 80 },
280 .p1 = { .min = 1, .max = 8 },
281 .p2 = { .dot_limit = 200000,
282 .p2_slow = 10, .p2_fast = 5 },
283 };
284
285 static const intel_limit_t intel_limits_pineview_lvds = {
286 .dot = { .min = 20000, .max = 400000 },
287 .vco = { .min = 1700000, .max = 3500000 },
288 .n = { .min = 3, .max = 6 },
289 .m = { .min = 2, .max = 256 },
290 .m1 = { .min = 0, .max = 0 },
291 .m2 = { .min = 0, .max = 254 },
292 .p = { .min = 7, .max = 112 },
293 .p1 = { .min = 1, .max = 8 },
294 .p2 = { .dot_limit = 112000,
295 .p2_slow = 14, .p2_fast = 14 },
296 };
297
298 /* Ironlake / Sandybridge
299 *
300 * We calculate clock using (register_value + 2) for N/M1/M2, so here
301 * the range value for them is (actual_value - 2).
302 */
303 static const intel_limit_t intel_limits_ironlake_dac = {
304 .dot = { .min = 25000, .max = 350000 },
305 .vco = { .min = 1760000, .max = 3510000 },
306 .n = { .min = 1, .max = 5 },
307 .m = { .min = 79, .max = 127 },
308 .m1 = { .min = 12, .max = 22 },
309 .m2 = { .min = 5, .max = 9 },
310 .p = { .min = 5, .max = 80 },
311 .p1 = { .min = 1, .max = 8 },
312 .p2 = { .dot_limit = 225000,
313 .p2_slow = 10, .p2_fast = 5 },
314 };
315
316 static const intel_limit_t intel_limits_ironlake_single_lvds = {
317 .dot = { .min = 25000, .max = 350000 },
318 .vco = { .min = 1760000, .max = 3510000 },
319 .n = { .min = 1, .max = 3 },
320 .m = { .min = 79, .max = 118 },
321 .m1 = { .min = 12, .max = 22 },
322 .m2 = { .min = 5, .max = 9 },
323 .p = { .min = 28, .max = 112 },
324 .p1 = { .min = 2, .max = 8 },
325 .p2 = { .dot_limit = 225000,
326 .p2_slow = 14, .p2_fast = 14 },
327 };
328
329 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
330 .dot = { .min = 25000, .max = 350000 },
331 .vco = { .min = 1760000, .max = 3510000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 79, .max = 127 },
334 .m1 = { .min = 12, .max = 22 },
335 .m2 = { .min = 5, .max = 9 },
336 .p = { .min = 14, .max = 56 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 225000,
339 .p2_slow = 7, .p2_fast = 7 },
340 };
341
342 /* LVDS 100mhz refclk limits. */
343 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
344 .dot = { .min = 25000, .max = 350000 },
345 .vco = { .min = 1760000, .max = 3510000 },
346 .n = { .min = 1, .max = 2 },
347 .m = { .min = 79, .max = 126 },
348 .m1 = { .min = 12, .max = 22 },
349 .m2 = { .min = 5, .max = 9 },
350 .p = { .min = 28, .max = 112 },
351 .p1 = { .min = 2, .max = 8 },
352 .p2 = { .dot_limit = 225000,
353 .p2_slow = 14, .p2_fast = 14 },
354 };
355
356 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
357 .dot = { .min = 25000, .max = 350000 },
358 .vco = { .min = 1760000, .max = 3510000 },
359 .n = { .min = 1, .max = 3 },
360 .m = { .min = 79, .max = 126 },
361 .m1 = { .min = 12, .max = 22 },
362 .m2 = { .min = 5, .max = 9 },
363 .p = { .min = 14, .max = 42 },
364 .p1 = { .min = 2, .max = 6 },
365 .p2 = { .dot_limit = 225000,
366 .p2_slow = 7, .p2_fast = 7 },
367 };
368
369 static const intel_limit_t intel_limits_vlv = {
370 /*
371 * These are the data rate limits (measured in fast clocks)
372 * since those are the strictest limits we have. The fast
373 * clock and actual rate limits are more relaxed, so checking
374 * them would make no difference.
375 */
376 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m1 = { .min = 2, .max = 3 },
380 .m2 = { .min = 11, .max = 156 },
381 .p1 = { .min = 2, .max = 3 },
382 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
383 };
384
385 static const intel_limit_t intel_limits_chv = {
386 /*
387 * These are the data rate limits (measured in fast clocks)
388 * since those are the strictest limits we have. The fast
389 * clock and actual rate limits are more relaxed, so checking
390 * them would make no difference.
391 */
392 .dot = { .min = 25000 * 5, .max = 540000 * 5},
393 .vco = { .min = 4860000, .max = 6700000 },
394 .n = { .min = 1, .max = 1 },
395 .m1 = { .min = 2, .max = 2 },
396 .m2 = { .min = 24 << 22, .max = 175 << 22 },
397 .p1 = { .min = 2, .max = 4 },
398 .p2 = { .p2_slow = 1, .p2_fast = 14 },
399 };
400
401 static void vlv_clock(int refclk, intel_clock_t *clock)
402 {
403 clock->m = clock->m1 * clock->m2;
404 clock->p = clock->p1 * clock->p2;
405 if (WARN_ON(clock->n == 0 || clock->p == 0))
406 return;
407 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
408 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
409 }
410
411 /**
412 * Returns whether any output on the specified pipe is of the specified type
413 */
414 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
415 {
416 struct drm_device *dev = crtc->dev;
417 struct intel_encoder *encoder;
418
419 for_each_encoder_on_crtc(dev, crtc, encoder)
420 if (encoder->type == type)
421 return true;
422
423 return false;
424 }
425
426 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
427 int refclk)
428 {
429 struct drm_device *dev = crtc->dev;
430 const intel_limit_t *limit;
431
432 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
433 if (intel_is_dual_link_lvds(dev)) {
434 if (refclk == 100000)
435 limit = &intel_limits_ironlake_dual_lvds_100m;
436 else
437 limit = &intel_limits_ironlake_dual_lvds;
438 } else {
439 if (refclk == 100000)
440 limit = &intel_limits_ironlake_single_lvds_100m;
441 else
442 limit = &intel_limits_ironlake_single_lvds;
443 }
444 } else
445 limit = &intel_limits_ironlake_dac;
446
447 return limit;
448 }
449
450 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
451 {
452 struct drm_device *dev = crtc->dev;
453 const intel_limit_t *limit;
454
455 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
456 if (intel_is_dual_link_lvds(dev))
457 limit = &intel_limits_g4x_dual_channel_lvds;
458 else
459 limit = &intel_limits_g4x_single_channel_lvds;
460 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
461 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
462 limit = &intel_limits_g4x_hdmi;
463 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
464 limit = &intel_limits_g4x_sdvo;
465 } else /* The option is for other outputs */
466 limit = &intel_limits_i9xx_sdvo;
467
468 return limit;
469 }
470
471 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
472 {
473 struct drm_device *dev = crtc->dev;
474 const intel_limit_t *limit;
475
476 if (HAS_PCH_SPLIT(dev))
477 limit = intel_ironlake_limit(crtc, refclk);
478 else if (IS_G4X(dev)) {
479 limit = intel_g4x_limit(crtc);
480 } else if (IS_PINEVIEW(dev)) {
481 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
482 limit = &intel_limits_pineview_lvds;
483 else
484 limit = &intel_limits_pineview_sdvo;
485 } else if (IS_CHERRYVIEW(dev)) {
486 limit = &intel_limits_chv;
487 } else if (IS_VALLEYVIEW(dev)) {
488 limit = &intel_limits_vlv;
489 } else if (!IS_GEN2(dev)) {
490 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
491 limit = &intel_limits_i9xx_lvds;
492 else
493 limit = &intel_limits_i9xx_sdvo;
494 } else {
495 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
496 limit = &intel_limits_i8xx_lvds;
497 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
498 limit = &intel_limits_i8xx_dvo;
499 else
500 limit = &intel_limits_i8xx_dac;
501 }
502 return limit;
503 }
504
505 /* m1 is reserved as 0 in Pineview, n is a ring counter */
506 static void pineview_clock(int refclk, intel_clock_t *clock)
507 {
508 clock->m = clock->m2 + 2;
509 clock->p = clock->p1 * clock->p2;
510 if (WARN_ON(clock->n == 0 || clock->p == 0))
511 return;
512 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
513 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
514 }
515
516 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
517 {
518 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
519 }
520
521 static void i9xx_clock(int refclk, intel_clock_t *clock)
522 {
523 clock->m = i9xx_dpll_compute_m(clock);
524 clock->p = clock->p1 * clock->p2;
525 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
526 return;
527 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
528 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
529 }
530
531 static void chv_clock(int refclk, intel_clock_t *clock)
532 {
533 clock->m = clock->m1 * clock->m2;
534 clock->p = clock->p1 * clock->p2;
535 if (WARN_ON(clock->n == 0 || clock->p == 0))
536 return;
537 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
538 clock->n << 22);
539 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
540 }
541
542 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
543 /**
544 * Returns whether the given set of divisors are valid for a given refclk with
545 * the given connectors.
546 */
547
548 static bool intel_PLL_is_valid(struct drm_device *dev,
549 const intel_limit_t *limit,
550 const intel_clock_t *clock)
551 {
552 if (clock->n < limit->n.min || limit->n.max < clock->n)
553 INTELPllInvalid("n out of range\n");
554 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
555 INTELPllInvalid("p1 out of range\n");
556 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
557 INTELPllInvalid("m2 out of range\n");
558 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
559 INTELPllInvalid("m1 out of range\n");
560
561 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
562 if (clock->m1 <= clock->m2)
563 INTELPllInvalid("m1 <= m2\n");
564
565 if (!IS_VALLEYVIEW(dev)) {
566 if (clock->p < limit->p.min || limit->p.max < clock->p)
567 INTELPllInvalid("p out of range\n");
568 if (clock->m < limit->m.min || limit->m.max < clock->m)
569 INTELPllInvalid("m out of range\n");
570 }
571
572 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
573 INTELPllInvalid("vco out of range\n");
574 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
575 * connector, etc., rather than just a single range.
576 */
577 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
578 INTELPllInvalid("dot out of range\n");
579
580 return true;
581 }
582
583 static bool
584 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
585 int target, int refclk, intel_clock_t *match_clock,
586 intel_clock_t *best_clock)
587 {
588 struct drm_device *dev = crtc->dev;
589 intel_clock_t clock;
590 int err = target;
591
592 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
593 /*
594 * For LVDS just rely on its current settings for dual-channel.
595 * We haven't figured out how to reliably set up different
596 * single/dual channel state, if we even can.
597 */
598 if (intel_is_dual_link_lvds(dev))
599 clock.p2 = limit->p2.p2_fast;
600 else
601 clock.p2 = limit->p2.p2_slow;
602 } else {
603 if (target < limit->p2.dot_limit)
604 clock.p2 = limit->p2.p2_slow;
605 else
606 clock.p2 = limit->p2.p2_fast;
607 }
608
609 memset(best_clock, 0, sizeof(*best_clock));
610
611 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
612 clock.m1++) {
613 for (clock.m2 = limit->m2.min;
614 clock.m2 <= limit->m2.max; clock.m2++) {
615 if (clock.m2 >= clock.m1)
616 break;
617 for (clock.n = limit->n.min;
618 clock.n <= limit->n.max; clock.n++) {
619 for (clock.p1 = limit->p1.min;
620 clock.p1 <= limit->p1.max; clock.p1++) {
621 int this_err;
622
623 i9xx_clock(refclk, &clock);
624 if (!intel_PLL_is_valid(dev, limit,
625 &clock))
626 continue;
627 if (match_clock &&
628 clock.p != match_clock->p)
629 continue;
630
631 this_err = abs(clock.dot - target);
632 if (this_err < err) {
633 *best_clock = clock;
634 err = this_err;
635 }
636 }
637 }
638 }
639 }
640
641 return (err != target);
642 }
643
644 static bool
645 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
646 int target, int refclk, intel_clock_t *match_clock,
647 intel_clock_t *best_clock)
648 {
649 struct drm_device *dev = crtc->dev;
650 intel_clock_t clock;
651 int err = target;
652
653 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
654 /*
655 * For LVDS just rely on its current settings for dual-channel.
656 * We haven't figured out how to reliably set up different
657 * single/dual channel state, if we even can.
658 */
659 if (intel_is_dual_link_lvds(dev))
660 clock.p2 = limit->p2.p2_fast;
661 else
662 clock.p2 = limit->p2.p2_slow;
663 } else {
664 if (target < limit->p2.dot_limit)
665 clock.p2 = limit->p2.p2_slow;
666 else
667 clock.p2 = limit->p2.p2_fast;
668 }
669
670 memset(best_clock, 0, sizeof(*best_clock));
671
672 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
673 clock.m1++) {
674 for (clock.m2 = limit->m2.min;
675 clock.m2 <= limit->m2.max; clock.m2++) {
676 for (clock.n = limit->n.min;
677 clock.n <= limit->n.max; clock.n++) {
678 for (clock.p1 = limit->p1.min;
679 clock.p1 <= limit->p1.max; clock.p1++) {
680 int this_err;
681
682 pineview_clock(refclk, &clock);
683 if (!intel_PLL_is_valid(dev, limit,
684 &clock))
685 continue;
686 if (match_clock &&
687 clock.p != match_clock->p)
688 continue;
689
690 this_err = abs(clock.dot - target);
691 if (this_err < err) {
692 *best_clock = clock;
693 err = this_err;
694 }
695 }
696 }
697 }
698 }
699
700 return (err != target);
701 }
702
703 static bool
704 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
705 int target, int refclk, intel_clock_t *match_clock,
706 intel_clock_t *best_clock)
707 {
708 struct drm_device *dev = crtc->dev;
709 intel_clock_t clock;
710 int max_n;
711 bool found;
712 /* approximately equals target * 0.00585 */
713 int err_most = (target >> 8) + (target >> 9);
714 found = false;
715
716 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
717 if (intel_is_dual_link_lvds(dev))
718 clock.p2 = limit->p2.p2_fast;
719 else
720 clock.p2 = limit->p2.p2_slow;
721 } else {
722 if (target < limit->p2.dot_limit)
723 clock.p2 = limit->p2.p2_slow;
724 else
725 clock.p2 = limit->p2.p2_fast;
726 }
727
728 memset(best_clock, 0, sizeof(*best_clock));
729 max_n = limit->n.max;
730 /* based on hardware requirement, prefer smaller n to precision */
731 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
732 /* based on hardware requirement, prefere larger m1,m2 */
733 for (clock.m1 = limit->m1.max;
734 clock.m1 >= limit->m1.min; clock.m1--) {
735 for (clock.m2 = limit->m2.max;
736 clock.m2 >= limit->m2.min; clock.m2--) {
737 for (clock.p1 = limit->p1.max;
738 clock.p1 >= limit->p1.min; clock.p1--) {
739 int this_err;
740
741 i9xx_clock(refclk, &clock);
742 if (!intel_PLL_is_valid(dev, limit,
743 &clock))
744 continue;
745
746 this_err = abs(clock.dot - target);
747 if (this_err < err_most) {
748 *best_clock = clock;
749 err_most = this_err;
750 max_n = clock.n;
751 found = true;
752 }
753 }
754 }
755 }
756 }
757 return found;
758 }
759
760 static bool
761 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
762 int target, int refclk, intel_clock_t *match_clock,
763 intel_clock_t *best_clock)
764 {
765 struct drm_device *dev = crtc->dev;
766 intel_clock_t clock;
767 unsigned int bestppm = 1000000;
768 /* min update 19.2 MHz */
769 int max_n = min(limit->n.max, refclk / 19200);
770 bool found = false;
771
772 target *= 5; /* fast clock */
773
774 memset(best_clock, 0, sizeof(*best_clock));
775
776 /* based on hardware requirement, prefer smaller n to precision */
777 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
778 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
779 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
780 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
781 clock.p = clock.p1 * clock.p2;
782 /* based on hardware requirement, prefer bigger m1,m2 values */
783 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
784 unsigned int ppm, diff;
785
786 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
787 refclk * clock.m1);
788
789 vlv_clock(refclk, &clock);
790
791 if (!intel_PLL_is_valid(dev, limit,
792 &clock))
793 continue;
794
795 diff = abs(clock.dot - target);
796 ppm = div_u64(1000000ULL * diff, target);
797
798 if (ppm < 100 && clock.p > best_clock->p) {
799 bestppm = 0;
800 *best_clock = clock;
801 found = true;
802 }
803
804 if (bestppm >= 10 && ppm < bestppm - 10) {
805 bestppm = ppm;
806 *best_clock = clock;
807 found = true;
808 }
809 }
810 }
811 }
812 }
813
814 return found;
815 }
816
817 static bool
818 chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
819 int target, int refclk, intel_clock_t *match_clock,
820 intel_clock_t *best_clock)
821 {
822 struct drm_device *dev = crtc->dev;
823 intel_clock_t clock;
824 uint64_t m2;
825 int found = false;
826
827 memset(best_clock, 0, sizeof(*best_clock));
828
829 /*
830 * Based on hardware doc, the n always set to 1, and m1 always
831 * set to 2. If requires to support 200Mhz refclk, we need to
832 * revisit this because n may not 1 anymore.
833 */
834 clock.n = 1, clock.m1 = 2;
835 target *= 5; /* fast clock */
836
837 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
838 for (clock.p2 = limit->p2.p2_fast;
839 clock.p2 >= limit->p2.p2_slow;
840 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
841
842 clock.p = clock.p1 * clock.p2;
843
844 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
845 clock.n) << 22, refclk * clock.m1);
846
847 if (m2 > INT_MAX/clock.m1)
848 continue;
849
850 clock.m2 = m2;
851
852 chv_clock(refclk, &clock);
853
854 if (!intel_PLL_is_valid(dev, limit, &clock))
855 continue;
856
857 /* based on hardware requirement, prefer bigger p
858 */
859 if (clock.p > best_clock->p) {
860 *best_clock = clock;
861 found = true;
862 }
863 }
864 }
865
866 return found;
867 }
868
869 bool intel_crtc_active(struct drm_crtc *crtc)
870 {
871 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
872
873 /* Be paranoid as we can arrive here with only partial
874 * state retrieved from the hardware during setup.
875 *
876 * We can ditch the adjusted_mode.crtc_clock check as soon
877 * as Haswell has gained clock readout/fastboot support.
878 *
879 * We can ditch the crtc->primary->fb check as soon as we can
880 * properly reconstruct framebuffers.
881 */
882 return intel_crtc->active && crtc->primary->fb &&
883 intel_crtc->config.adjusted_mode.crtc_clock;
884 }
885
886 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
887 enum pipe pipe)
888 {
889 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
890 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
891
892 return intel_crtc->config.cpu_transcoder;
893 }
894
895 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
896 {
897 struct drm_i915_private *dev_priv = dev->dev_private;
898 u32 reg = PIPEDSL(pipe);
899 u32 line1, line2;
900 u32 line_mask;
901
902 if (IS_GEN2(dev))
903 line_mask = DSL_LINEMASK_GEN2;
904 else
905 line_mask = DSL_LINEMASK_GEN3;
906
907 line1 = I915_READ(reg) & line_mask;
908 mdelay(5);
909 line2 = I915_READ(reg) & line_mask;
910
911 return line1 == line2;
912 }
913
914 /*
915 * intel_wait_for_pipe_off - wait for pipe to turn off
916 * @crtc: crtc whose pipe to wait for
917 *
918 * After disabling a pipe, we can't wait for vblank in the usual way,
919 * spinning on the vblank interrupt status bit, since we won't actually
920 * see an interrupt when the pipe is disabled.
921 *
922 * On Gen4 and above:
923 * wait for the pipe register state bit to turn off
924 *
925 * Otherwise:
926 * wait for the display line value to settle (it usually
927 * ends up stopping at the start of the next frame).
928 *
929 */
930 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
931 {
932 struct drm_device *dev = crtc->base.dev;
933 struct drm_i915_private *dev_priv = dev->dev_private;
934 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
935 enum pipe pipe = crtc->pipe;
936
937 if (INTEL_INFO(dev)->gen >= 4) {
938 int reg = PIPECONF(cpu_transcoder);
939
940 /* Wait for the Pipe State to go off */
941 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
942 100))
943 WARN(1, "pipe_off wait timed out\n");
944 } else {
945 /* Wait for the display line to settle */
946 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
947 WARN(1, "pipe_off wait timed out\n");
948 }
949 }
950
951 /*
952 * ibx_digital_port_connected - is the specified port connected?
953 * @dev_priv: i915 private structure
954 * @port: the port to test
955 *
956 * Returns true if @port is connected, false otherwise.
957 */
958 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
959 struct intel_digital_port *port)
960 {
961 u32 bit;
962
963 if (HAS_PCH_IBX(dev_priv->dev)) {
964 switch (port->port) {
965 case PORT_B:
966 bit = SDE_PORTB_HOTPLUG;
967 break;
968 case PORT_C:
969 bit = SDE_PORTC_HOTPLUG;
970 break;
971 case PORT_D:
972 bit = SDE_PORTD_HOTPLUG;
973 break;
974 default:
975 return true;
976 }
977 } else {
978 switch (port->port) {
979 case PORT_B:
980 bit = SDE_PORTB_HOTPLUG_CPT;
981 break;
982 case PORT_C:
983 bit = SDE_PORTC_HOTPLUG_CPT;
984 break;
985 case PORT_D:
986 bit = SDE_PORTD_HOTPLUG_CPT;
987 break;
988 default:
989 return true;
990 }
991 }
992
993 return I915_READ(SDEISR) & bit;
994 }
995
996 static const char *state_string(bool enabled)
997 {
998 return enabled ? "on" : "off";
999 }
1000
1001 /* Only for pre-ILK configs */
1002 void assert_pll(struct drm_i915_private *dev_priv,
1003 enum pipe pipe, bool state)
1004 {
1005 int reg;
1006 u32 val;
1007 bool cur_state;
1008
1009 reg = DPLL(pipe);
1010 val = I915_READ(reg);
1011 cur_state = !!(val & DPLL_VCO_ENABLE);
1012 WARN(cur_state != state,
1013 "PLL state assertion failure (expected %s, current %s)\n",
1014 state_string(state), state_string(cur_state));
1015 }
1016
1017 /* XXX: the dsi pll is shared between MIPI DSI ports */
1018 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1019 {
1020 u32 val;
1021 bool cur_state;
1022
1023 mutex_lock(&dev_priv->dpio_lock);
1024 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1025 mutex_unlock(&dev_priv->dpio_lock);
1026
1027 cur_state = val & DSI_PLL_VCO_EN;
1028 WARN(cur_state != state,
1029 "DSI PLL state assertion failure (expected %s, current %s)\n",
1030 state_string(state), state_string(cur_state));
1031 }
1032 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1033 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1034
1035 struct intel_shared_dpll *
1036 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1037 {
1038 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1039
1040 if (crtc->config.shared_dpll < 0)
1041 return NULL;
1042
1043 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1044 }
1045
1046 /* For ILK+ */
1047 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1048 struct intel_shared_dpll *pll,
1049 bool state)
1050 {
1051 bool cur_state;
1052 struct intel_dpll_hw_state hw_state;
1053
1054 if (WARN (!pll,
1055 "asserting DPLL %s with no DPLL\n", state_string(state)))
1056 return;
1057
1058 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1059 WARN(cur_state != state,
1060 "%s assertion failure (expected %s, current %s)\n",
1061 pll->name, state_string(state), state_string(cur_state));
1062 }
1063
1064 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1065 enum pipe pipe, bool state)
1066 {
1067 int reg;
1068 u32 val;
1069 bool cur_state;
1070 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1071 pipe);
1072
1073 if (HAS_DDI(dev_priv->dev)) {
1074 /* DDI does not have a specific FDI_TX register */
1075 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1076 val = I915_READ(reg);
1077 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1078 } else {
1079 reg = FDI_TX_CTL(pipe);
1080 val = I915_READ(reg);
1081 cur_state = !!(val & FDI_TX_ENABLE);
1082 }
1083 WARN(cur_state != state,
1084 "FDI TX state assertion failure (expected %s, current %s)\n",
1085 state_string(state), state_string(cur_state));
1086 }
1087 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1088 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1089
1090 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1091 enum pipe pipe, bool state)
1092 {
1093 int reg;
1094 u32 val;
1095 bool cur_state;
1096
1097 reg = FDI_RX_CTL(pipe);
1098 val = I915_READ(reg);
1099 cur_state = !!(val & FDI_RX_ENABLE);
1100 WARN(cur_state != state,
1101 "FDI RX state assertion failure (expected %s, current %s)\n",
1102 state_string(state), state_string(cur_state));
1103 }
1104 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1105 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1106
1107 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1108 enum pipe pipe)
1109 {
1110 int reg;
1111 u32 val;
1112
1113 /* ILK FDI PLL is always enabled */
1114 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1115 return;
1116
1117 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1118 if (HAS_DDI(dev_priv->dev))
1119 return;
1120
1121 reg = FDI_TX_CTL(pipe);
1122 val = I915_READ(reg);
1123 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1124 }
1125
1126 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1127 enum pipe pipe, bool state)
1128 {
1129 int reg;
1130 u32 val;
1131 bool cur_state;
1132
1133 reg = FDI_RX_CTL(pipe);
1134 val = I915_READ(reg);
1135 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1136 WARN(cur_state != state,
1137 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1138 state_string(state), state_string(cur_state));
1139 }
1140
1141 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1142 enum pipe pipe)
1143 {
1144 struct drm_device *dev = dev_priv->dev;
1145 int pp_reg;
1146 u32 val;
1147 enum pipe panel_pipe = PIPE_A;
1148 bool locked = true;
1149
1150 if (WARN_ON(HAS_DDI(dev)))
1151 return;
1152
1153 if (HAS_PCH_SPLIT(dev)) {
1154 u32 port_sel;
1155
1156 pp_reg = PCH_PP_CONTROL;
1157 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1158
1159 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1160 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1161 panel_pipe = PIPE_B;
1162 /* XXX: else fix for eDP */
1163 } else if (IS_VALLEYVIEW(dev)) {
1164 /* presumably write lock depends on pipe, not port select */
1165 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1166 panel_pipe = pipe;
1167 } else {
1168 pp_reg = PP_CONTROL;
1169 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1170 panel_pipe = PIPE_B;
1171 }
1172
1173 val = I915_READ(pp_reg);
1174 if (!(val & PANEL_POWER_ON) ||
1175 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1176 locked = false;
1177
1178 WARN(panel_pipe == pipe && locked,
1179 "panel assertion failure, pipe %c regs locked\n",
1180 pipe_name(pipe));
1181 }
1182
1183 static void assert_cursor(struct drm_i915_private *dev_priv,
1184 enum pipe pipe, bool state)
1185 {
1186 struct drm_device *dev = dev_priv->dev;
1187 bool cur_state;
1188
1189 if (IS_845G(dev) || IS_I865G(dev))
1190 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1191 else
1192 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1193
1194 WARN(cur_state != state,
1195 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1196 pipe_name(pipe), state_string(state), state_string(cur_state));
1197 }
1198 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1199 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1200
1201 void assert_pipe(struct drm_i915_private *dev_priv,
1202 enum pipe pipe, bool state)
1203 {
1204 int reg;
1205 u32 val;
1206 bool cur_state;
1207 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1208 pipe);
1209
1210 /* if we need the pipe quirk it must be always on */
1211 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1212 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1213 state = true;
1214
1215 if (!intel_display_power_enabled(dev_priv,
1216 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1217 cur_state = false;
1218 } else {
1219 reg = PIPECONF(cpu_transcoder);
1220 val = I915_READ(reg);
1221 cur_state = !!(val & PIPECONF_ENABLE);
1222 }
1223
1224 WARN(cur_state != state,
1225 "pipe %c assertion failure (expected %s, current %s)\n",
1226 pipe_name(pipe), state_string(state), state_string(cur_state));
1227 }
1228
1229 static void assert_plane(struct drm_i915_private *dev_priv,
1230 enum plane plane, bool state)
1231 {
1232 int reg;
1233 u32 val;
1234 bool cur_state;
1235
1236 reg = DSPCNTR(plane);
1237 val = I915_READ(reg);
1238 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1239 WARN(cur_state != state,
1240 "plane %c assertion failure (expected %s, current %s)\n",
1241 plane_name(plane), state_string(state), state_string(cur_state));
1242 }
1243
1244 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1245 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1246
1247 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1248 enum pipe pipe)
1249 {
1250 struct drm_device *dev = dev_priv->dev;
1251 int reg, i;
1252 u32 val;
1253 int cur_pipe;
1254
1255 /* Primary planes are fixed to pipes on gen4+ */
1256 if (INTEL_INFO(dev)->gen >= 4) {
1257 reg = DSPCNTR(pipe);
1258 val = I915_READ(reg);
1259 WARN(val & DISPLAY_PLANE_ENABLE,
1260 "plane %c assertion failure, should be disabled but not\n",
1261 plane_name(pipe));
1262 return;
1263 }
1264
1265 /* Need to check both planes against the pipe */
1266 for_each_pipe(dev_priv, i) {
1267 reg = DSPCNTR(i);
1268 val = I915_READ(reg);
1269 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1270 DISPPLANE_SEL_PIPE_SHIFT;
1271 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1272 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1273 plane_name(i), pipe_name(pipe));
1274 }
1275 }
1276
1277 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1278 enum pipe pipe)
1279 {
1280 struct drm_device *dev = dev_priv->dev;
1281 int reg, sprite;
1282 u32 val;
1283
1284 if (IS_VALLEYVIEW(dev)) {
1285 for_each_sprite(pipe, sprite) {
1286 reg = SPCNTR(pipe, sprite);
1287 val = I915_READ(reg);
1288 WARN(val & SP_ENABLE,
1289 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1290 sprite_name(pipe, sprite), pipe_name(pipe));
1291 }
1292 } else if (INTEL_INFO(dev)->gen >= 7) {
1293 reg = SPRCTL(pipe);
1294 val = I915_READ(reg);
1295 WARN(val & SPRITE_ENABLE,
1296 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1297 plane_name(pipe), pipe_name(pipe));
1298 } else if (INTEL_INFO(dev)->gen >= 5) {
1299 reg = DVSCNTR(pipe);
1300 val = I915_READ(reg);
1301 WARN(val & DVS_ENABLE,
1302 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1303 plane_name(pipe), pipe_name(pipe));
1304 }
1305 }
1306
1307 static void assert_vblank_disabled(struct drm_crtc *crtc)
1308 {
1309 if (WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1310 drm_crtc_vblank_put(crtc);
1311 }
1312
1313 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1314 {
1315 u32 val;
1316 bool enabled;
1317
1318 WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1319
1320 val = I915_READ(PCH_DREF_CONTROL);
1321 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1322 DREF_SUPERSPREAD_SOURCE_MASK));
1323 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1324 }
1325
1326 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1327 enum pipe pipe)
1328 {
1329 int reg;
1330 u32 val;
1331 bool enabled;
1332
1333 reg = PCH_TRANSCONF(pipe);
1334 val = I915_READ(reg);
1335 enabled = !!(val & TRANS_ENABLE);
1336 WARN(enabled,
1337 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1338 pipe_name(pipe));
1339 }
1340
1341 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1342 enum pipe pipe, u32 port_sel, u32 val)
1343 {
1344 if ((val & DP_PORT_EN) == 0)
1345 return false;
1346
1347 if (HAS_PCH_CPT(dev_priv->dev)) {
1348 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1349 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1350 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1351 return false;
1352 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1353 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1354 return false;
1355 } else {
1356 if ((val & DP_PIPE_MASK) != (pipe << 30))
1357 return false;
1358 }
1359 return true;
1360 }
1361
1362 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1363 enum pipe pipe, u32 val)
1364 {
1365 if ((val & SDVO_ENABLE) == 0)
1366 return false;
1367
1368 if (HAS_PCH_CPT(dev_priv->dev)) {
1369 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1370 return false;
1371 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1372 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1373 return false;
1374 } else {
1375 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1376 return false;
1377 }
1378 return true;
1379 }
1380
1381 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1382 enum pipe pipe, u32 val)
1383 {
1384 if ((val & LVDS_PORT_EN) == 0)
1385 return false;
1386
1387 if (HAS_PCH_CPT(dev_priv->dev)) {
1388 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1389 return false;
1390 } else {
1391 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1392 return false;
1393 }
1394 return true;
1395 }
1396
1397 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1398 enum pipe pipe, u32 val)
1399 {
1400 if ((val & ADPA_DAC_ENABLE) == 0)
1401 return false;
1402 if (HAS_PCH_CPT(dev_priv->dev)) {
1403 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1404 return false;
1405 } else {
1406 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1407 return false;
1408 }
1409 return true;
1410 }
1411
1412 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1413 enum pipe pipe, int reg, u32 port_sel)
1414 {
1415 u32 val = I915_READ(reg);
1416 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1417 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1418 reg, pipe_name(pipe));
1419
1420 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1421 && (val & DP_PIPEB_SELECT),
1422 "IBX PCH dp port still using transcoder B\n");
1423 }
1424
1425 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1426 enum pipe pipe, int reg)
1427 {
1428 u32 val = I915_READ(reg);
1429 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1430 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1431 reg, pipe_name(pipe));
1432
1433 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1434 && (val & SDVO_PIPE_B_SELECT),
1435 "IBX PCH hdmi port still using transcoder B\n");
1436 }
1437
1438 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1439 enum pipe pipe)
1440 {
1441 int reg;
1442 u32 val;
1443
1444 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1445 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1446 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1447
1448 reg = PCH_ADPA;
1449 val = I915_READ(reg);
1450 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1451 "PCH VGA enabled on transcoder %c, should be disabled\n",
1452 pipe_name(pipe));
1453
1454 reg = PCH_LVDS;
1455 val = I915_READ(reg);
1456 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1457 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1458 pipe_name(pipe));
1459
1460 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1461 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1462 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1463 }
1464
1465 static void intel_init_dpio(struct drm_device *dev)
1466 {
1467 struct drm_i915_private *dev_priv = dev->dev_private;
1468
1469 if (!IS_VALLEYVIEW(dev))
1470 return;
1471
1472 /*
1473 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1474 * CHV x1 PHY (DP/HDMI D)
1475 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1476 */
1477 if (IS_CHERRYVIEW(dev)) {
1478 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1479 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1480 } else {
1481 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1482 }
1483 }
1484
1485 static void vlv_enable_pll(struct intel_crtc *crtc)
1486 {
1487 struct drm_device *dev = crtc->base.dev;
1488 struct drm_i915_private *dev_priv = dev->dev_private;
1489 int reg = DPLL(crtc->pipe);
1490 u32 dpll = crtc->config.dpll_hw_state.dpll;
1491
1492 assert_pipe_disabled(dev_priv, crtc->pipe);
1493
1494 /* No really, not for ILK+ */
1495 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1496
1497 /* PLL is protected by panel, make sure we can write it */
1498 if (IS_MOBILE(dev_priv->dev))
1499 assert_panel_unlocked(dev_priv, crtc->pipe);
1500
1501 I915_WRITE(reg, dpll);
1502 POSTING_READ(reg);
1503 udelay(150);
1504
1505 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1506 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1507
1508 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1509 POSTING_READ(DPLL_MD(crtc->pipe));
1510
1511 /* We do this three times for luck */
1512 I915_WRITE(reg, dpll);
1513 POSTING_READ(reg);
1514 udelay(150); /* wait for warmup */
1515 I915_WRITE(reg, dpll);
1516 POSTING_READ(reg);
1517 udelay(150); /* wait for warmup */
1518 I915_WRITE(reg, dpll);
1519 POSTING_READ(reg);
1520 udelay(150); /* wait for warmup */
1521 }
1522
1523 static void chv_enable_pll(struct intel_crtc *crtc)
1524 {
1525 struct drm_device *dev = crtc->base.dev;
1526 struct drm_i915_private *dev_priv = dev->dev_private;
1527 int pipe = crtc->pipe;
1528 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1529 u32 tmp;
1530
1531 assert_pipe_disabled(dev_priv, crtc->pipe);
1532
1533 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1534
1535 mutex_lock(&dev_priv->dpio_lock);
1536
1537 /* Enable back the 10bit clock to display controller */
1538 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1539 tmp |= DPIO_DCLKP_EN;
1540 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1541
1542 /*
1543 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1544 */
1545 udelay(1);
1546
1547 /* Enable PLL */
1548 I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll);
1549
1550 /* Check PLL is locked */
1551 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1552 DRM_ERROR("PLL %d failed to lock\n", pipe);
1553
1554 /* not sure when this should be written */
1555 I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
1556 POSTING_READ(DPLL_MD(pipe));
1557
1558 mutex_unlock(&dev_priv->dpio_lock);
1559 }
1560
1561 static int intel_num_dvo_pipes(struct drm_device *dev)
1562 {
1563 struct intel_crtc *crtc;
1564 int count = 0;
1565
1566 for_each_intel_crtc(dev, crtc)
1567 count += crtc->active &&
1568 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO);
1569
1570 return count;
1571 }
1572
1573 static void i9xx_enable_pll(struct intel_crtc *crtc)
1574 {
1575 struct drm_device *dev = crtc->base.dev;
1576 struct drm_i915_private *dev_priv = dev->dev_private;
1577 int reg = DPLL(crtc->pipe);
1578 u32 dpll = crtc->config.dpll_hw_state.dpll;
1579
1580 assert_pipe_disabled(dev_priv, crtc->pipe);
1581
1582 /* No really, not for ILK+ */
1583 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1584
1585 /* PLL is protected by panel, make sure we can write it */
1586 if (IS_MOBILE(dev) && !IS_I830(dev))
1587 assert_panel_unlocked(dev_priv, crtc->pipe);
1588
1589 /* Enable DVO 2x clock on both PLLs if necessary */
1590 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1591 /*
1592 * It appears to be important that we don't enable this
1593 * for the current pipe before otherwise configuring the
1594 * PLL. No idea how this should be handled if multiple
1595 * DVO outputs are enabled simultaneosly.
1596 */
1597 dpll |= DPLL_DVO_2X_MODE;
1598 I915_WRITE(DPLL(!crtc->pipe),
1599 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1600 }
1601
1602 /* Wait for the clocks to stabilize. */
1603 POSTING_READ(reg);
1604 udelay(150);
1605
1606 if (INTEL_INFO(dev)->gen >= 4) {
1607 I915_WRITE(DPLL_MD(crtc->pipe),
1608 crtc->config.dpll_hw_state.dpll_md);
1609 } else {
1610 /* The pixel multiplier can only be updated once the
1611 * DPLL is enabled and the clocks are stable.
1612 *
1613 * So write it again.
1614 */
1615 I915_WRITE(reg, dpll);
1616 }
1617
1618 /* We do this three times for luck */
1619 I915_WRITE(reg, dpll);
1620 POSTING_READ(reg);
1621 udelay(150); /* wait for warmup */
1622 I915_WRITE(reg, dpll);
1623 POSTING_READ(reg);
1624 udelay(150); /* wait for warmup */
1625 I915_WRITE(reg, dpll);
1626 POSTING_READ(reg);
1627 udelay(150); /* wait for warmup */
1628 }
1629
1630 /**
1631 * i9xx_disable_pll - disable a PLL
1632 * @dev_priv: i915 private structure
1633 * @pipe: pipe PLL to disable
1634 *
1635 * Disable the PLL for @pipe, making sure the pipe is off first.
1636 *
1637 * Note! This is for pre-ILK only.
1638 */
1639 static void i9xx_disable_pll(struct intel_crtc *crtc)
1640 {
1641 struct drm_device *dev = crtc->base.dev;
1642 struct drm_i915_private *dev_priv = dev->dev_private;
1643 enum pipe pipe = crtc->pipe;
1644
1645 /* Disable DVO 2x clock on both PLLs if necessary */
1646 if (IS_I830(dev) &&
1647 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO) &&
1648 intel_num_dvo_pipes(dev) == 1) {
1649 I915_WRITE(DPLL(PIPE_B),
1650 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1651 I915_WRITE(DPLL(PIPE_A),
1652 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1653 }
1654
1655 /* Don't disable pipe or pipe PLLs if needed */
1656 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1657 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1658 return;
1659
1660 /* Make sure the pipe isn't still relying on us */
1661 assert_pipe_disabled(dev_priv, pipe);
1662
1663 I915_WRITE(DPLL(pipe), 0);
1664 POSTING_READ(DPLL(pipe));
1665 }
1666
1667 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1668 {
1669 u32 val = 0;
1670
1671 /* Make sure the pipe isn't still relying on us */
1672 assert_pipe_disabled(dev_priv, pipe);
1673
1674 /*
1675 * Leave integrated clock source and reference clock enabled for pipe B.
1676 * The latter is needed for VGA hotplug / manual detection.
1677 */
1678 if (pipe == PIPE_B)
1679 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1680 I915_WRITE(DPLL(pipe), val);
1681 POSTING_READ(DPLL(pipe));
1682
1683 }
1684
1685 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1686 {
1687 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1688 u32 val;
1689
1690 /* Make sure the pipe isn't still relying on us */
1691 assert_pipe_disabled(dev_priv, pipe);
1692
1693 /* Set PLL en = 0 */
1694 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1695 if (pipe != PIPE_A)
1696 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1697 I915_WRITE(DPLL(pipe), val);
1698 POSTING_READ(DPLL(pipe));
1699
1700 mutex_lock(&dev_priv->dpio_lock);
1701
1702 /* Disable 10bit clock to display controller */
1703 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1704 val &= ~DPIO_DCLKP_EN;
1705 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1706
1707 /* disable left/right clock distribution */
1708 if (pipe != PIPE_B) {
1709 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1710 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1711 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1712 } else {
1713 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1714 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1715 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1716 }
1717
1718 mutex_unlock(&dev_priv->dpio_lock);
1719 }
1720
1721 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1722 struct intel_digital_port *dport)
1723 {
1724 u32 port_mask;
1725 int dpll_reg;
1726
1727 switch (dport->port) {
1728 case PORT_B:
1729 port_mask = DPLL_PORTB_READY_MASK;
1730 dpll_reg = DPLL(0);
1731 break;
1732 case PORT_C:
1733 port_mask = DPLL_PORTC_READY_MASK;
1734 dpll_reg = DPLL(0);
1735 break;
1736 case PORT_D:
1737 port_mask = DPLL_PORTD_READY_MASK;
1738 dpll_reg = DPIO_PHY_STATUS;
1739 break;
1740 default:
1741 BUG();
1742 }
1743
1744 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1745 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1746 port_name(dport->port), I915_READ(dpll_reg));
1747 }
1748
1749 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1750 {
1751 struct drm_device *dev = crtc->base.dev;
1752 struct drm_i915_private *dev_priv = dev->dev_private;
1753 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1754
1755 if (WARN_ON(pll == NULL))
1756 return;
1757
1758 WARN_ON(!pll->refcount);
1759 if (pll->active == 0) {
1760 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1761 WARN_ON(pll->on);
1762 assert_shared_dpll_disabled(dev_priv, pll);
1763
1764 pll->mode_set(dev_priv, pll);
1765 }
1766 }
1767
1768 /**
1769 * intel_enable_shared_dpll - enable PCH PLL
1770 * @dev_priv: i915 private structure
1771 * @pipe: pipe PLL to enable
1772 *
1773 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1774 * drives the transcoder clock.
1775 */
1776 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1777 {
1778 struct drm_device *dev = crtc->base.dev;
1779 struct drm_i915_private *dev_priv = dev->dev_private;
1780 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1781
1782 if (WARN_ON(pll == NULL))
1783 return;
1784
1785 if (WARN_ON(pll->refcount == 0))
1786 return;
1787
1788 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1789 pll->name, pll->active, pll->on,
1790 crtc->base.base.id);
1791
1792 if (pll->active++) {
1793 WARN_ON(!pll->on);
1794 assert_shared_dpll_enabled(dev_priv, pll);
1795 return;
1796 }
1797 WARN_ON(pll->on);
1798
1799 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1800
1801 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1802 pll->enable(dev_priv, pll);
1803 pll->on = true;
1804 }
1805
1806 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1807 {
1808 struct drm_device *dev = crtc->base.dev;
1809 struct drm_i915_private *dev_priv = dev->dev_private;
1810 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1811
1812 /* PCH only available on ILK+ */
1813 BUG_ON(INTEL_INFO(dev)->gen < 5);
1814 if (WARN_ON(pll == NULL))
1815 return;
1816
1817 if (WARN_ON(pll->refcount == 0))
1818 return;
1819
1820 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1821 pll->name, pll->active, pll->on,
1822 crtc->base.base.id);
1823
1824 if (WARN_ON(pll->active == 0)) {
1825 assert_shared_dpll_disabled(dev_priv, pll);
1826 return;
1827 }
1828
1829 assert_shared_dpll_enabled(dev_priv, pll);
1830 WARN_ON(!pll->on);
1831 if (--pll->active)
1832 return;
1833
1834 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1835 pll->disable(dev_priv, pll);
1836 pll->on = false;
1837
1838 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1839 }
1840
1841 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1842 enum pipe pipe)
1843 {
1844 struct drm_device *dev = dev_priv->dev;
1845 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1846 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1847 uint32_t reg, val, pipeconf_val;
1848
1849 /* PCH only available on ILK+ */
1850 BUG_ON(!HAS_PCH_SPLIT(dev));
1851
1852 /* Make sure PCH DPLL is enabled */
1853 assert_shared_dpll_enabled(dev_priv,
1854 intel_crtc_to_shared_dpll(intel_crtc));
1855
1856 /* FDI must be feeding us bits for PCH ports */
1857 assert_fdi_tx_enabled(dev_priv, pipe);
1858 assert_fdi_rx_enabled(dev_priv, pipe);
1859
1860 if (HAS_PCH_CPT(dev)) {
1861 /* Workaround: Set the timing override bit before enabling the
1862 * pch transcoder. */
1863 reg = TRANS_CHICKEN2(pipe);
1864 val = I915_READ(reg);
1865 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1866 I915_WRITE(reg, val);
1867 }
1868
1869 reg = PCH_TRANSCONF(pipe);
1870 val = I915_READ(reg);
1871 pipeconf_val = I915_READ(PIPECONF(pipe));
1872
1873 if (HAS_PCH_IBX(dev_priv->dev)) {
1874 /*
1875 * make the BPC in transcoder be consistent with
1876 * that in pipeconf reg.
1877 */
1878 val &= ~PIPECONF_BPC_MASK;
1879 val |= pipeconf_val & PIPECONF_BPC_MASK;
1880 }
1881
1882 val &= ~TRANS_INTERLACE_MASK;
1883 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1884 if (HAS_PCH_IBX(dev_priv->dev) &&
1885 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1886 val |= TRANS_LEGACY_INTERLACED_ILK;
1887 else
1888 val |= TRANS_INTERLACED;
1889 else
1890 val |= TRANS_PROGRESSIVE;
1891
1892 I915_WRITE(reg, val | TRANS_ENABLE);
1893 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1894 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1895 }
1896
1897 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1898 enum transcoder cpu_transcoder)
1899 {
1900 u32 val, pipeconf_val;
1901
1902 /* PCH only available on ILK+ */
1903 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1904
1905 /* FDI must be feeding us bits for PCH ports */
1906 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1907 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1908
1909 /* Workaround: set timing override bit. */
1910 val = I915_READ(_TRANSA_CHICKEN2);
1911 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1912 I915_WRITE(_TRANSA_CHICKEN2, val);
1913
1914 val = TRANS_ENABLE;
1915 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1916
1917 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1918 PIPECONF_INTERLACED_ILK)
1919 val |= TRANS_INTERLACED;
1920 else
1921 val |= TRANS_PROGRESSIVE;
1922
1923 I915_WRITE(LPT_TRANSCONF, val);
1924 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1925 DRM_ERROR("Failed to enable PCH transcoder\n");
1926 }
1927
1928 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1929 enum pipe pipe)
1930 {
1931 struct drm_device *dev = dev_priv->dev;
1932 uint32_t reg, val;
1933
1934 /* FDI relies on the transcoder */
1935 assert_fdi_tx_disabled(dev_priv, pipe);
1936 assert_fdi_rx_disabled(dev_priv, pipe);
1937
1938 /* Ports must be off as well */
1939 assert_pch_ports_disabled(dev_priv, pipe);
1940
1941 reg = PCH_TRANSCONF(pipe);
1942 val = I915_READ(reg);
1943 val &= ~TRANS_ENABLE;
1944 I915_WRITE(reg, val);
1945 /* wait for PCH transcoder off, transcoder state */
1946 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1947 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1948
1949 if (!HAS_PCH_IBX(dev)) {
1950 /* Workaround: Clear the timing override chicken bit again. */
1951 reg = TRANS_CHICKEN2(pipe);
1952 val = I915_READ(reg);
1953 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1954 I915_WRITE(reg, val);
1955 }
1956 }
1957
1958 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1959 {
1960 u32 val;
1961
1962 val = I915_READ(LPT_TRANSCONF);
1963 val &= ~TRANS_ENABLE;
1964 I915_WRITE(LPT_TRANSCONF, val);
1965 /* wait for PCH transcoder off, transcoder state */
1966 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1967 DRM_ERROR("Failed to disable PCH transcoder\n");
1968
1969 /* Workaround: clear timing override bit. */
1970 val = I915_READ(_TRANSA_CHICKEN2);
1971 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1972 I915_WRITE(_TRANSA_CHICKEN2, val);
1973 }
1974
1975 /**
1976 * intel_enable_pipe - enable a pipe, asserting requirements
1977 * @crtc: crtc responsible for the pipe
1978 *
1979 * Enable @crtc's pipe, making sure that various hardware specific requirements
1980 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1981 */
1982 static void intel_enable_pipe(struct intel_crtc *crtc)
1983 {
1984 struct drm_device *dev = crtc->base.dev;
1985 struct drm_i915_private *dev_priv = dev->dev_private;
1986 enum pipe pipe = crtc->pipe;
1987 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1988 pipe);
1989 enum pipe pch_transcoder;
1990 int reg;
1991 u32 val;
1992
1993 assert_planes_disabled(dev_priv, pipe);
1994 assert_cursor_disabled(dev_priv, pipe);
1995 assert_sprites_disabled(dev_priv, pipe);
1996
1997 if (HAS_PCH_LPT(dev_priv->dev))
1998 pch_transcoder = TRANSCODER_A;
1999 else
2000 pch_transcoder = pipe;
2001
2002 /*
2003 * A pipe without a PLL won't actually be able to drive bits from
2004 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2005 * need the check.
2006 */
2007 if (!HAS_PCH_SPLIT(dev_priv->dev))
2008 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
2009 assert_dsi_pll_enabled(dev_priv);
2010 else
2011 assert_pll_enabled(dev_priv, pipe);
2012 else {
2013 if (crtc->config.has_pch_encoder) {
2014 /* if driving the PCH, we need FDI enabled */
2015 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2016 assert_fdi_tx_pll_enabled(dev_priv,
2017 (enum pipe) cpu_transcoder);
2018 }
2019 /* FIXME: assert CPU port conditions for SNB+ */
2020 }
2021
2022 reg = PIPECONF(cpu_transcoder);
2023 val = I915_READ(reg);
2024 if (val & PIPECONF_ENABLE) {
2025 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2026 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2027 return;
2028 }
2029
2030 I915_WRITE(reg, val | PIPECONF_ENABLE);
2031 POSTING_READ(reg);
2032 }
2033
2034 /**
2035 * intel_disable_pipe - disable a pipe, asserting requirements
2036 * @crtc: crtc whose pipes is to be disabled
2037 *
2038 * Disable the pipe of @crtc, making sure that various hardware
2039 * specific requirements are met, if applicable, e.g. plane
2040 * disabled, panel fitter off, etc.
2041 *
2042 * Will wait until the pipe has shut down before returning.
2043 */
2044 static void intel_disable_pipe(struct intel_crtc *crtc)
2045 {
2046 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2047 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2048 enum pipe pipe = crtc->pipe;
2049 int reg;
2050 u32 val;
2051
2052 /*
2053 * Make sure planes won't keep trying to pump pixels to us,
2054 * or we might hang the display.
2055 */
2056 assert_planes_disabled(dev_priv, pipe);
2057 assert_cursor_disabled(dev_priv, pipe);
2058 assert_sprites_disabled(dev_priv, pipe);
2059
2060 reg = PIPECONF(cpu_transcoder);
2061 val = I915_READ(reg);
2062 if ((val & PIPECONF_ENABLE) == 0)
2063 return;
2064
2065 /*
2066 * Double wide has implications for planes
2067 * so best keep it disabled when not needed.
2068 */
2069 if (crtc->config.double_wide)
2070 val &= ~PIPECONF_DOUBLE_WIDE;
2071
2072 /* Don't disable pipe or pipe PLLs if needed */
2073 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2074 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2075 val &= ~PIPECONF_ENABLE;
2076
2077 I915_WRITE(reg, val);
2078 if ((val & PIPECONF_ENABLE) == 0)
2079 intel_wait_for_pipe_off(crtc);
2080 }
2081
2082 /*
2083 * Plane regs are double buffered, going from enabled->disabled needs a
2084 * trigger in order to latch. The display address reg provides this.
2085 */
2086 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2087 enum plane plane)
2088 {
2089 struct drm_device *dev = dev_priv->dev;
2090 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2091
2092 I915_WRITE(reg, I915_READ(reg));
2093 POSTING_READ(reg);
2094 }
2095
2096 /**
2097 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2098 * @plane: plane to be enabled
2099 * @crtc: crtc for the plane
2100 *
2101 * Enable @plane on @crtc, making sure that the pipe is running first.
2102 */
2103 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2104 struct drm_crtc *crtc)
2105 {
2106 struct drm_device *dev = plane->dev;
2107 struct drm_i915_private *dev_priv = dev->dev_private;
2108 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2109
2110 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2111 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2112
2113 if (intel_crtc->primary_enabled)
2114 return;
2115
2116 intel_crtc->primary_enabled = true;
2117
2118 dev_priv->display.update_primary_plane(crtc, plane->fb,
2119 crtc->x, crtc->y);
2120
2121 /*
2122 * BDW signals flip done immediately if the plane
2123 * is disabled, even if the plane enable is already
2124 * armed to occur at the next vblank :(
2125 */
2126 if (IS_BROADWELL(dev))
2127 intel_wait_for_vblank(dev, intel_crtc->pipe);
2128 }
2129
2130 /**
2131 * intel_disable_primary_hw_plane - disable the primary hardware plane
2132 * @plane: plane to be disabled
2133 * @crtc: crtc for the plane
2134 *
2135 * Disable @plane on @crtc, making sure that the pipe is running first.
2136 */
2137 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2138 struct drm_crtc *crtc)
2139 {
2140 struct drm_device *dev = plane->dev;
2141 struct drm_i915_private *dev_priv = dev->dev_private;
2142 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2143
2144 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2145
2146 if (!intel_crtc->primary_enabled)
2147 return;
2148
2149 intel_crtc->primary_enabled = false;
2150
2151 dev_priv->display.update_primary_plane(crtc, plane->fb,
2152 crtc->x, crtc->y);
2153 }
2154
2155 static bool need_vtd_wa(struct drm_device *dev)
2156 {
2157 #ifdef CONFIG_INTEL_IOMMU
2158 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2159 return true;
2160 #endif
2161 return false;
2162 }
2163
2164 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2165 {
2166 int tile_height;
2167
2168 tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2169 return ALIGN(height, tile_height);
2170 }
2171
2172 int
2173 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2174 struct drm_i915_gem_object *obj,
2175 struct intel_engine_cs *pipelined)
2176 {
2177 struct drm_i915_private *dev_priv = dev->dev_private;
2178 u32 alignment;
2179 int ret;
2180
2181 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2182
2183 switch (obj->tiling_mode) {
2184 case I915_TILING_NONE:
2185 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2186 alignment = 128 * 1024;
2187 else if (INTEL_INFO(dev)->gen >= 4)
2188 alignment = 4 * 1024;
2189 else
2190 alignment = 64 * 1024;
2191 break;
2192 case I915_TILING_X:
2193 /* pin() will align the object as required by fence */
2194 alignment = 0;
2195 break;
2196 case I915_TILING_Y:
2197 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2198 return -EINVAL;
2199 default:
2200 BUG();
2201 }
2202
2203 /* Note that the w/a also requires 64 PTE of padding following the
2204 * bo. We currently fill all unused PTE with the shadow page and so
2205 * we should always have valid PTE following the scanout preventing
2206 * the VT-d warning.
2207 */
2208 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2209 alignment = 256 * 1024;
2210
2211 /*
2212 * Global gtt pte registers are special registers which actually forward
2213 * writes to a chunk of system memory. Which means that there is no risk
2214 * that the register values disappear as soon as we call
2215 * intel_runtime_pm_put(), so it is correct to wrap only the
2216 * pin/unpin/fence and not more.
2217 */
2218 intel_runtime_pm_get(dev_priv);
2219
2220 dev_priv->mm.interruptible = false;
2221 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2222 if (ret)
2223 goto err_interruptible;
2224
2225 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2226 * fence, whereas 965+ only requires a fence if using
2227 * framebuffer compression. For simplicity, we always install
2228 * a fence as the cost is not that onerous.
2229 */
2230 ret = i915_gem_object_get_fence(obj);
2231 if (ret)
2232 goto err_unpin;
2233
2234 i915_gem_object_pin_fence(obj);
2235
2236 dev_priv->mm.interruptible = true;
2237 intel_runtime_pm_put(dev_priv);
2238 return 0;
2239
2240 err_unpin:
2241 i915_gem_object_unpin_from_display_plane(obj);
2242 err_interruptible:
2243 dev_priv->mm.interruptible = true;
2244 intel_runtime_pm_put(dev_priv);
2245 return ret;
2246 }
2247
2248 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2249 {
2250 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2251
2252 i915_gem_object_unpin_fence(obj);
2253 i915_gem_object_unpin_from_display_plane(obj);
2254 }
2255
2256 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2257 * is assumed to be a power-of-two. */
2258 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2259 unsigned int tiling_mode,
2260 unsigned int cpp,
2261 unsigned int pitch)
2262 {
2263 if (tiling_mode != I915_TILING_NONE) {
2264 unsigned int tile_rows, tiles;
2265
2266 tile_rows = *y / 8;
2267 *y %= 8;
2268
2269 tiles = *x / (512/cpp);
2270 *x %= 512/cpp;
2271
2272 return tile_rows * pitch * 8 + tiles * 4096;
2273 } else {
2274 unsigned int offset;
2275
2276 offset = *y * pitch + *x * cpp;
2277 *y = 0;
2278 *x = (offset & 4095) / cpp;
2279 return offset & -4096;
2280 }
2281 }
2282
2283 int intel_format_to_fourcc(int format)
2284 {
2285 switch (format) {
2286 case DISPPLANE_8BPP:
2287 return DRM_FORMAT_C8;
2288 case DISPPLANE_BGRX555:
2289 return DRM_FORMAT_XRGB1555;
2290 case DISPPLANE_BGRX565:
2291 return DRM_FORMAT_RGB565;
2292 default:
2293 case DISPPLANE_BGRX888:
2294 return DRM_FORMAT_XRGB8888;
2295 case DISPPLANE_RGBX888:
2296 return DRM_FORMAT_XBGR8888;
2297 case DISPPLANE_BGRX101010:
2298 return DRM_FORMAT_XRGB2101010;
2299 case DISPPLANE_RGBX101010:
2300 return DRM_FORMAT_XBGR2101010;
2301 }
2302 }
2303
2304 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2305 struct intel_plane_config *plane_config)
2306 {
2307 struct drm_device *dev = crtc->base.dev;
2308 struct drm_i915_gem_object *obj = NULL;
2309 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2310 u32 base = plane_config->base;
2311
2312 if (plane_config->size == 0)
2313 return false;
2314
2315 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2316 plane_config->size);
2317 if (!obj)
2318 return false;
2319
2320 if (plane_config->tiled) {
2321 obj->tiling_mode = I915_TILING_X;
2322 obj->stride = crtc->base.primary->fb->pitches[0];
2323 }
2324
2325 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2326 mode_cmd.width = crtc->base.primary->fb->width;
2327 mode_cmd.height = crtc->base.primary->fb->height;
2328 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2329
2330 mutex_lock(&dev->struct_mutex);
2331
2332 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2333 &mode_cmd, obj)) {
2334 DRM_DEBUG_KMS("intel fb init failed\n");
2335 goto out_unref_obj;
2336 }
2337
2338 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2339 mutex_unlock(&dev->struct_mutex);
2340
2341 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2342 return true;
2343
2344 out_unref_obj:
2345 drm_gem_object_unreference(&obj->base);
2346 mutex_unlock(&dev->struct_mutex);
2347 return false;
2348 }
2349
2350 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2351 struct intel_plane_config *plane_config)
2352 {
2353 struct drm_device *dev = intel_crtc->base.dev;
2354 struct drm_crtc *c;
2355 struct intel_crtc *i;
2356 struct drm_i915_gem_object *obj;
2357
2358 if (!intel_crtc->base.primary->fb)
2359 return;
2360
2361 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2362 return;
2363
2364 kfree(intel_crtc->base.primary->fb);
2365 intel_crtc->base.primary->fb = NULL;
2366
2367 /*
2368 * Failed to alloc the obj, check to see if we should share
2369 * an fb with another CRTC instead
2370 */
2371 for_each_crtc(dev, c) {
2372 i = to_intel_crtc(c);
2373
2374 if (c == &intel_crtc->base)
2375 continue;
2376
2377 if (!i->active)
2378 continue;
2379
2380 obj = intel_fb_obj(c->primary->fb);
2381 if (obj == NULL)
2382 continue;
2383
2384 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2385 drm_framebuffer_reference(c->primary->fb);
2386 intel_crtc->base.primary->fb = c->primary->fb;
2387 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2388 break;
2389 }
2390 }
2391 }
2392
2393 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2394 struct drm_framebuffer *fb,
2395 int x, int y)
2396 {
2397 struct drm_device *dev = crtc->dev;
2398 struct drm_i915_private *dev_priv = dev->dev_private;
2399 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2400 struct drm_i915_gem_object *obj;
2401 int plane = intel_crtc->plane;
2402 unsigned long linear_offset;
2403 u32 dspcntr;
2404 u32 reg = DSPCNTR(plane);
2405 int pixel_size;
2406
2407 if (!intel_crtc->primary_enabled) {
2408 I915_WRITE(reg, 0);
2409 if (INTEL_INFO(dev)->gen >= 4)
2410 I915_WRITE(DSPSURF(plane), 0);
2411 else
2412 I915_WRITE(DSPADDR(plane), 0);
2413 POSTING_READ(reg);
2414 return;
2415 }
2416
2417 obj = intel_fb_obj(fb);
2418 if (WARN_ON(obj == NULL))
2419 return;
2420
2421 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2422
2423 dspcntr = DISPPLANE_GAMMA_ENABLE;
2424
2425 dspcntr |= DISPLAY_PLANE_ENABLE;
2426
2427 if (INTEL_INFO(dev)->gen < 4) {
2428 if (intel_crtc->pipe == PIPE_B)
2429 dspcntr |= DISPPLANE_SEL_PIPE_B;
2430
2431 /* pipesrc and dspsize control the size that is scaled from,
2432 * which should always be the user's requested size.
2433 */
2434 I915_WRITE(DSPSIZE(plane),
2435 ((intel_crtc->config.pipe_src_h - 1) << 16) |
2436 (intel_crtc->config.pipe_src_w - 1));
2437 I915_WRITE(DSPPOS(plane), 0);
2438 }
2439
2440 switch (fb->pixel_format) {
2441 case DRM_FORMAT_C8:
2442 dspcntr |= DISPPLANE_8BPP;
2443 break;
2444 case DRM_FORMAT_XRGB1555:
2445 case DRM_FORMAT_ARGB1555:
2446 dspcntr |= DISPPLANE_BGRX555;
2447 break;
2448 case DRM_FORMAT_RGB565:
2449 dspcntr |= DISPPLANE_BGRX565;
2450 break;
2451 case DRM_FORMAT_XRGB8888:
2452 case DRM_FORMAT_ARGB8888:
2453 dspcntr |= DISPPLANE_BGRX888;
2454 break;
2455 case DRM_FORMAT_XBGR8888:
2456 case DRM_FORMAT_ABGR8888:
2457 dspcntr |= DISPPLANE_RGBX888;
2458 break;
2459 case DRM_FORMAT_XRGB2101010:
2460 case DRM_FORMAT_ARGB2101010:
2461 dspcntr |= DISPPLANE_BGRX101010;
2462 break;
2463 case DRM_FORMAT_XBGR2101010:
2464 case DRM_FORMAT_ABGR2101010:
2465 dspcntr |= DISPPLANE_RGBX101010;
2466 break;
2467 default:
2468 BUG();
2469 }
2470
2471 if (INTEL_INFO(dev)->gen >= 4 &&
2472 obj->tiling_mode != I915_TILING_NONE)
2473 dspcntr |= DISPPLANE_TILED;
2474
2475 if (IS_G4X(dev))
2476 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2477
2478 linear_offset = y * fb->pitches[0] + x * pixel_size;
2479
2480 if (INTEL_INFO(dev)->gen >= 4) {
2481 intel_crtc->dspaddr_offset =
2482 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2483 pixel_size,
2484 fb->pitches[0]);
2485 linear_offset -= intel_crtc->dspaddr_offset;
2486 } else {
2487 intel_crtc->dspaddr_offset = linear_offset;
2488 }
2489
2490 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2491 dspcntr |= DISPPLANE_ROTATE_180;
2492
2493 x += (intel_crtc->config.pipe_src_w - 1);
2494 y += (intel_crtc->config.pipe_src_h - 1);
2495
2496 /* Finding the last pixel of the last line of the display
2497 data and adding to linear_offset*/
2498 linear_offset +=
2499 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2500 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2501 }
2502
2503 I915_WRITE(reg, dspcntr);
2504
2505 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2506 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2507 fb->pitches[0]);
2508 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2509 if (INTEL_INFO(dev)->gen >= 4) {
2510 I915_WRITE(DSPSURF(plane),
2511 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2512 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2513 I915_WRITE(DSPLINOFF(plane), linear_offset);
2514 } else
2515 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2516 POSTING_READ(reg);
2517 }
2518
2519 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2520 struct drm_framebuffer *fb,
2521 int x, int y)
2522 {
2523 struct drm_device *dev = crtc->dev;
2524 struct drm_i915_private *dev_priv = dev->dev_private;
2525 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2526 struct drm_i915_gem_object *obj;
2527 int plane = intel_crtc->plane;
2528 unsigned long linear_offset;
2529 u32 dspcntr;
2530 u32 reg = DSPCNTR(plane);
2531 int pixel_size;
2532
2533 if (!intel_crtc->primary_enabled) {
2534 I915_WRITE(reg, 0);
2535 I915_WRITE(DSPSURF(plane), 0);
2536 POSTING_READ(reg);
2537 return;
2538 }
2539
2540 obj = intel_fb_obj(fb);
2541 if (WARN_ON(obj == NULL))
2542 return;
2543
2544 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2545
2546 dspcntr = DISPPLANE_GAMMA_ENABLE;
2547
2548 dspcntr |= DISPLAY_PLANE_ENABLE;
2549
2550 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2551 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2552
2553 switch (fb->pixel_format) {
2554 case DRM_FORMAT_C8:
2555 dspcntr |= DISPPLANE_8BPP;
2556 break;
2557 case DRM_FORMAT_RGB565:
2558 dspcntr |= DISPPLANE_BGRX565;
2559 break;
2560 case DRM_FORMAT_XRGB8888:
2561 case DRM_FORMAT_ARGB8888:
2562 dspcntr |= DISPPLANE_BGRX888;
2563 break;
2564 case DRM_FORMAT_XBGR8888:
2565 case DRM_FORMAT_ABGR8888:
2566 dspcntr |= DISPPLANE_RGBX888;
2567 break;
2568 case DRM_FORMAT_XRGB2101010:
2569 case DRM_FORMAT_ARGB2101010:
2570 dspcntr |= DISPPLANE_BGRX101010;
2571 break;
2572 case DRM_FORMAT_XBGR2101010:
2573 case DRM_FORMAT_ABGR2101010:
2574 dspcntr |= DISPPLANE_RGBX101010;
2575 break;
2576 default:
2577 BUG();
2578 }
2579
2580 if (obj->tiling_mode != I915_TILING_NONE)
2581 dspcntr |= DISPPLANE_TILED;
2582
2583 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2584 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2585
2586 linear_offset = y * fb->pitches[0] + x * pixel_size;
2587 intel_crtc->dspaddr_offset =
2588 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2589 pixel_size,
2590 fb->pitches[0]);
2591 linear_offset -= intel_crtc->dspaddr_offset;
2592 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2593 dspcntr |= DISPPLANE_ROTATE_180;
2594
2595 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2596 x += (intel_crtc->config.pipe_src_w - 1);
2597 y += (intel_crtc->config.pipe_src_h - 1);
2598
2599 /* Finding the last pixel of the last line of the display
2600 data and adding to linear_offset*/
2601 linear_offset +=
2602 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2603 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2604 }
2605 }
2606
2607 I915_WRITE(reg, dspcntr);
2608
2609 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2610 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2611 fb->pitches[0]);
2612 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2613 I915_WRITE(DSPSURF(plane),
2614 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2615 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2616 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2617 } else {
2618 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2619 I915_WRITE(DSPLINOFF(plane), linear_offset);
2620 }
2621 POSTING_READ(reg);
2622 }
2623
2624 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2625 static int
2626 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2627 int x, int y, enum mode_set_atomic state)
2628 {
2629 struct drm_device *dev = crtc->dev;
2630 struct drm_i915_private *dev_priv = dev->dev_private;
2631
2632 if (dev_priv->display.disable_fbc)
2633 dev_priv->display.disable_fbc(dev);
2634 intel_increase_pllclock(dev, to_intel_crtc(crtc)->pipe);
2635
2636 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2637
2638 return 0;
2639 }
2640
2641 void intel_display_handle_reset(struct drm_device *dev)
2642 {
2643 struct drm_i915_private *dev_priv = dev->dev_private;
2644 struct drm_crtc *crtc;
2645
2646 /*
2647 * Flips in the rings have been nuked by the reset,
2648 * so complete all pending flips so that user space
2649 * will get its events and not get stuck.
2650 *
2651 * Also update the base address of all primary
2652 * planes to the the last fb to make sure we're
2653 * showing the correct fb after a reset.
2654 *
2655 * Need to make two loops over the crtcs so that we
2656 * don't try to grab a crtc mutex before the
2657 * pending_flip_queue really got woken up.
2658 */
2659
2660 for_each_crtc(dev, crtc) {
2661 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2662 enum plane plane = intel_crtc->plane;
2663
2664 intel_prepare_page_flip(dev, plane);
2665 intel_finish_page_flip_plane(dev, plane);
2666 }
2667
2668 for_each_crtc(dev, crtc) {
2669 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2670
2671 drm_modeset_lock(&crtc->mutex, NULL);
2672 /*
2673 * FIXME: Once we have proper support for primary planes (and
2674 * disabling them without disabling the entire crtc) allow again
2675 * a NULL crtc->primary->fb.
2676 */
2677 if (intel_crtc->active && crtc->primary->fb)
2678 dev_priv->display.update_primary_plane(crtc,
2679 crtc->primary->fb,
2680 crtc->x,
2681 crtc->y);
2682 drm_modeset_unlock(&crtc->mutex);
2683 }
2684 }
2685
2686 static int
2687 intel_finish_fb(struct drm_framebuffer *old_fb)
2688 {
2689 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2690 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2691 bool was_interruptible = dev_priv->mm.interruptible;
2692 int ret;
2693
2694 /* Big Hammer, we also need to ensure that any pending
2695 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2696 * current scanout is retired before unpinning the old
2697 * framebuffer.
2698 *
2699 * This should only fail upon a hung GPU, in which case we
2700 * can safely continue.
2701 */
2702 dev_priv->mm.interruptible = false;
2703 ret = i915_gem_object_finish_gpu(obj);
2704 dev_priv->mm.interruptible = was_interruptible;
2705
2706 return ret;
2707 }
2708
2709 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2710 {
2711 struct drm_device *dev = crtc->dev;
2712 struct drm_i915_private *dev_priv = dev->dev_private;
2713 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2714 bool pending;
2715
2716 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2717 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2718 return false;
2719
2720 spin_lock_irq(&dev->event_lock);
2721 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2722 spin_unlock_irq(&dev->event_lock);
2723
2724 return pending;
2725 }
2726
2727 static void intel_update_pipe_size(struct intel_crtc *crtc)
2728 {
2729 struct drm_device *dev = crtc->base.dev;
2730 struct drm_i915_private *dev_priv = dev->dev_private;
2731 const struct drm_display_mode *adjusted_mode;
2732
2733 if (!i915.fastboot)
2734 return;
2735
2736 /*
2737 * Update pipe size and adjust fitter if needed: the reason for this is
2738 * that in compute_mode_changes we check the native mode (not the pfit
2739 * mode) to see if we can flip rather than do a full mode set. In the
2740 * fastboot case, we'll flip, but if we don't update the pipesrc and
2741 * pfit state, we'll end up with a big fb scanned out into the wrong
2742 * sized surface.
2743 *
2744 * To fix this properly, we need to hoist the checks up into
2745 * compute_mode_changes (or above), check the actual pfit state and
2746 * whether the platform allows pfit disable with pipe active, and only
2747 * then update the pipesrc and pfit state, even on the flip path.
2748 */
2749
2750 adjusted_mode = &crtc->config.adjusted_mode;
2751
2752 I915_WRITE(PIPESRC(crtc->pipe),
2753 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2754 (adjusted_mode->crtc_vdisplay - 1));
2755 if (!crtc->config.pch_pfit.enabled &&
2756 (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) ||
2757 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))) {
2758 I915_WRITE(PF_CTL(crtc->pipe), 0);
2759 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
2760 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
2761 }
2762 crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2763 crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2764 }
2765
2766 static int
2767 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2768 struct drm_framebuffer *fb)
2769 {
2770 struct drm_device *dev = crtc->dev;
2771 struct drm_i915_private *dev_priv = dev->dev_private;
2772 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2773 enum pipe pipe = intel_crtc->pipe;
2774 struct drm_framebuffer *old_fb = crtc->primary->fb;
2775 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2776 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
2777 int ret;
2778
2779 if (intel_crtc_has_pending_flip(crtc)) {
2780 DRM_ERROR("pipe is still busy with an old pageflip\n");
2781 return -EBUSY;
2782 }
2783
2784 /* no fb bound */
2785 if (!fb) {
2786 DRM_ERROR("No FB bound\n");
2787 return 0;
2788 }
2789
2790 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2791 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2792 plane_name(intel_crtc->plane),
2793 INTEL_INFO(dev)->num_pipes);
2794 return -EINVAL;
2795 }
2796
2797 mutex_lock(&dev->struct_mutex);
2798 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
2799 if (ret == 0)
2800 i915_gem_track_fb(old_obj, obj,
2801 INTEL_FRONTBUFFER_PRIMARY(pipe));
2802 mutex_unlock(&dev->struct_mutex);
2803 if (ret != 0) {
2804 DRM_ERROR("pin & fence failed\n");
2805 return ret;
2806 }
2807
2808 intel_update_pipe_size(intel_crtc);
2809
2810 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2811
2812 if (intel_crtc->active)
2813 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
2814
2815 crtc->primary->fb = fb;
2816 crtc->x = x;
2817 crtc->y = y;
2818
2819 if (old_fb) {
2820 if (intel_crtc->active && old_fb != fb)
2821 intel_wait_for_vblank(dev, intel_crtc->pipe);
2822 mutex_lock(&dev->struct_mutex);
2823 intel_unpin_fb_obj(old_obj);
2824 mutex_unlock(&dev->struct_mutex);
2825 }
2826
2827 mutex_lock(&dev->struct_mutex);
2828 intel_update_fbc(dev);
2829 mutex_unlock(&dev->struct_mutex);
2830
2831 return 0;
2832 }
2833
2834 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2835 {
2836 struct drm_device *dev = crtc->dev;
2837 struct drm_i915_private *dev_priv = dev->dev_private;
2838 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2839 int pipe = intel_crtc->pipe;
2840 u32 reg, temp;
2841
2842 /* enable normal train */
2843 reg = FDI_TX_CTL(pipe);
2844 temp = I915_READ(reg);
2845 if (IS_IVYBRIDGE(dev)) {
2846 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2847 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2848 } else {
2849 temp &= ~FDI_LINK_TRAIN_NONE;
2850 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2851 }
2852 I915_WRITE(reg, temp);
2853
2854 reg = FDI_RX_CTL(pipe);
2855 temp = I915_READ(reg);
2856 if (HAS_PCH_CPT(dev)) {
2857 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2858 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2859 } else {
2860 temp &= ~FDI_LINK_TRAIN_NONE;
2861 temp |= FDI_LINK_TRAIN_NONE;
2862 }
2863 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2864
2865 /* wait one idle pattern time */
2866 POSTING_READ(reg);
2867 udelay(1000);
2868
2869 /* IVB wants error correction enabled */
2870 if (IS_IVYBRIDGE(dev))
2871 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2872 FDI_FE_ERRC_ENABLE);
2873 }
2874
2875 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2876 {
2877 return crtc->base.enabled && crtc->active &&
2878 crtc->config.has_pch_encoder;
2879 }
2880
2881 static void ivb_modeset_global_resources(struct drm_device *dev)
2882 {
2883 struct drm_i915_private *dev_priv = dev->dev_private;
2884 struct intel_crtc *pipe_B_crtc =
2885 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2886 struct intel_crtc *pipe_C_crtc =
2887 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2888 uint32_t temp;
2889
2890 /*
2891 * When everything is off disable fdi C so that we could enable fdi B
2892 * with all lanes. Note that we don't care about enabled pipes without
2893 * an enabled pch encoder.
2894 */
2895 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2896 !pipe_has_enabled_pch(pipe_C_crtc)) {
2897 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2898 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2899
2900 temp = I915_READ(SOUTH_CHICKEN1);
2901 temp &= ~FDI_BC_BIFURCATION_SELECT;
2902 DRM_DEBUG_KMS("disabling fdi C rx\n");
2903 I915_WRITE(SOUTH_CHICKEN1, temp);
2904 }
2905 }
2906
2907 /* The FDI link training functions for ILK/Ibexpeak. */
2908 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2909 {
2910 struct drm_device *dev = crtc->dev;
2911 struct drm_i915_private *dev_priv = dev->dev_private;
2912 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2913 int pipe = intel_crtc->pipe;
2914 u32 reg, temp, tries;
2915
2916 /* FDI needs bits from pipe first */
2917 assert_pipe_enabled(dev_priv, pipe);
2918
2919 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2920 for train result */
2921 reg = FDI_RX_IMR(pipe);
2922 temp = I915_READ(reg);
2923 temp &= ~FDI_RX_SYMBOL_LOCK;
2924 temp &= ~FDI_RX_BIT_LOCK;
2925 I915_WRITE(reg, temp);
2926 I915_READ(reg);
2927 udelay(150);
2928
2929 /* enable CPU FDI TX and PCH FDI RX */
2930 reg = FDI_TX_CTL(pipe);
2931 temp = I915_READ(reg);
2932 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2933 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2934 temp &= ~FDI_LINK_TRAIN_NONE;
2935 temp |= FDI_LINK_TRAIN_PATTERN_1;
2936 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2937
2938 reg = FDI_RX_CTL(pipe);
2939 temp = I915_READ(reg);
2940 temp &= ~FDI_LINK_TRAIN_NONE;
2941 temp |= FDI_LINK_TRAIN_PATTERN_1;
2942 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2943
2944 POSTING_READ(reg);
2945 udelay(150);
2946
2947 /* Ironlake workaround, enable clock pointer after FDI enable*/
2948 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2949 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2950 FDI_RX_PHASE_SYNC_POINTER_EN);
2951
2952 reg = FDI_RX_IIR(pipe);
2953 for (tries = 0; tries < 5; tries++) {
2954 temp = I915_READ(reg);
2955 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2956
2957 if ((temp & FDI_RX_BIT_LOCK)) {
2958 DRM_DEBUG_KMS("FDI train 1 done.\n");
2959 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2960 break;
2961 }
2962 }
2963 if (tries == 5)
2964 DRM_ERROR("FDI train 1 fail!\n");
2965
2966 /* Train 2 */
2967 reg = FDI_TX_CTL(pipe);
2968 temp = I915_READ(reg);
2969 temp &= ~FDI_LINK_TRAIN_NONE;
2970 temp |= FDI_LINK_TRAIN_PATTERN_2;
2971 I915_WRITE(reg, temp);
2972
2973 reg = FDI_RX_CTL(pipe);
2974 temp = I915_READ(reg);
2975 temp &= ~FDI_LINK_TRAIN_NONE;
2976 temp |= FDI_LINK_TRAIN_PATTERN_2;
2977 I915_WRITE(reg, temp);
2978
2979 POSTING_READ(reg);
2980 udelay(150);
2981
2982 reg = FDI_RX_IIR(pipe);
2983 for (tries = 0; tries < 5; tries++) {
2984 temp = I915_READ(reg);
2985 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2986
2987 if (temp & FDI_RX_SYMBOL_LOCK) {
2988 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2989 DRM_DEBUG_KMS("FDI train 2 done.\n");
2990 break;
2991 }
2992 }
2993 if (tries == 5)
2994 DRM_ERROR("FDI train 2 fail!\n");
2995
2996 DRM_DEBUG_KMS("FDI train done\n");
2997
2998 }
2999
3000 static const int snb_b_fdi_train_param[] = {
3001 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3002 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3003 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3004 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3005 };
3006
3007 /* The FDI link training functions for SNB/Cougarpoint. */
3008 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3009 {
3010 struct drm_device *dev = crtc->dev;
3011 struct drm_i915_private *dev_priv = dev->dev_private;
3012 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3013 int pipe = intel_crtc->pipe;
3014 u32 reg, temp, i, retry;
3015
3016 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3017 for train result */
3018 reg = FDI_RX_IMR(pipe);
3019 temp = I915_READ(reg);
3020 temp &= ~FDI_RX_SYMBOL_LOCK;
3021 temp &= ~FDI_RX_BIT_LOCK;
3022 I915_WRITE(reg, temp);
3023
3024 POSTING_READ(reg);
3025 udelay(150);
3026
3027 /* enable CPU FDI TX and PCH FDI RX */
3028 reg = FDI_TX_CTL(pipe);
3029 temp = I915_READ(reg);
3030 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3031 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3032 temp &= ~FDI_LINK_TRAIN_NONE;
3033 temp |= FDI_LINK_TRAIN_PATTERN_1;
3034 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3035 /* SNB-B */
3036 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3037 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3038
3039 I915_WRITE(FDI_RX_MISC(pipe),
3040 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3041
3042 reg = FDI_RX_CTL(pipe);
3043 temp = I915_READ(reg);
3044 if (HAS_PCH_CPT(dev)) {
3045 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3046 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3047 } else {
3048 temp &= ~FDI_LINK_TRAIN_NONE;
3049 temp |= FDI_LINK_TRAIN_PATTERN_1;
3050 }
3051 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3052
3053 POSTING_READ(reg);
3054 udelay(150);
3055
3056 for (i = 0; i < 4; i++) {
3057 reg = FDI_TX_CTL(pipe);
3058 temp = I915_READ(reg);
3059 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3060 temp |= snb_b_fdi_train_param[i];
3061 I915_WRITE(reg, temp);
3062
3063 POSTING_READ(reg);
3064 udelay(500);
3065
3066 for (retry = 0; retry < 5; retry++) {
3067 reg = FDI_RX_IIR(pipe);
3068 temp = I915_READ(reg);
3069 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3070 if (temp & FDI_RX_BIT_LOCK) {
3071 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3072 DRM_DEBUG_KMS("FDI train 1 done.\n");
3073 break;
3074 }
3075 udelay(50);
3076 }
3077 if (retry < 5)
3078 break;
3079 }
3080 if (i == 4)
3081 DRM_ERROR("FDI train 1 fail!\n");
3082
3083 /* Train 2 */
3084 reg = FDI_TX_CTL(pipe);
3085 temp = I915_READ(reg);
3086 temp &= ~FDI_LINK_TRAIN_NONE;
3087 temp |= FDI_LINK_TRAIN_PATTERN_2;
3088 if (IS_GEN6(dev)) {
3089 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3090 /* SNB-B */
3091 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3092 }
3093 I915_WRITE(reg, temp);
3094
3095 reg = FDI_RX_CTL(pipe);
3096 temp = I915_READ(reg);
3097 if (HAS_PCH_CPT(dev)) {
3098 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3099 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3100 } else {
3101 temp &= ~FDI_LINK_TRAIN_NONE;
3102 temp |= FDI_LINK_TRAIN_PATTERN_2;
3103 }
3104 I915_WRITE(reg, temp);
3105
3106 POSTING_READ(reg);
3107 udelay(150);
3108
3109 for (i = 0; i < 4; i++) {
3110 reg = FDI_TX_CTL(pipe);
3111 temp = I915_READ(reg);
3112 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3113 temp |= snb_b_fdi_train_param[i];
3114 I915_WRITE(reg, temp);
3115
3116 POSTING_READ(reg);
3117 udelay(500);
3118
3119 for (retry = 0; retry < 5; retry++) {
3120 reg = FDI_RX_IIR(pipe);
3121 temp = I915_READ(reg);
3122 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3123 if (temp & FDI_RX_SYMBOL_LOCK) {
3124 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3125 DRM_DEBUG_KMS("FDI train 2 done.\n");
3126 break;
3127 }
3128 udelay(50);
3129 }
3130 if (retry < 5)
3131 break;
3132 }
3133 if (i == 4)
3134 DRM_ERROR("FDI train 2 fail!\n");
3135
3136 DRM_DEBUG_KMS("FDI train done.\n");
3137 }
3138
3139 /* Manual link training for Ivy Bridge A0 parts */
3140 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3141 {
3142 struct drm_device *dev = crtc->dev;
3143 struct drm_i915_private *dev_priv = dev->dev_private;
3144 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3145 int pipe = intel_crtc->pipe;
3146 u32 reg, temp, i, j;
3147
3148 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3149 for train result */
3150 reg = FDI_RX_IMR(pipe);
3151 temp = I915_READ(reg);
3152 temp &= ~FDI_RX_SYMBOL_LOCK;
3153 temp &= ~FDI_RX_BIT_LOCK;
3154 I915_WRITE(reg, temp);
3155
3156 POSTING_READ(reg);
3157 udelay(150);
3158
3159 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3160 I915_READ(FDI_RX_IIR(pipe)));
3161
3162 /* Try each vswing and preemphasis setting twice before moving on */
3163 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3164 /* disable first in case we need to retry */
3165 reg = FDI_TX_CTL(pipe);
3166 temp = I915_READ(reg);
3167 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3168 temp &= ~FDI_TX_ENABLE;
3169 I915_WRITE(reg, temp);
3170
3171 reg = FDI_RX_CTL(pipe);
3172 temp = I915_READ(reg);
3173 temp &= ~FDI_LINK_TRAIN_AUTO;
3174 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3175 temp &= ~FDI_RX_ENABLE;
3176 I915_WRITE(reg, temp);
3177
3178 /* enable CPU FDI TX and PCH FDI RX */
3179 reg = FDI_TX_CTL(pipe);
3180 temp = I915_READ(reg);
3181 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3182 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3183 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3184 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3185 temp |= snb_b_fdi_train_param[j/2];
3186 temp |= FDI_COMPOSITE_SYNC;
3187 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3188
3189 I915_WRITE(FDI_RX_MISC(pipe),
3190 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3191
3192 reg = FDI_RX_CTL(pipe);
3193 temp = I915_READ(reg);
3194 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3195 temp |= FDI_COMPOSITE_SYNC;
3196 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3197
3198 POSTING_READ(reg);
3199 udelay(1); /* should be 0.5us */
3200
3201 for (i = 0; i < 4; i++) {
3202 reg = FDI_RX_IIR(pipe);
3203 temp = I915_READ(reg);
3204 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3205
3206 if (temp & FDI_RX_BIT_LOCK ||
3207 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3208 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3209 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3210 i);
3211 break;
3212 }
3213 udelay(1); /* should be 0.5us */
3214 }
3215 if (i == 4) {
3216 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3217 continue;
3218 }
3219
3220 /* Train 2 */
3221 reg = FDI_TX_CTL(pipe);
3222 temp = I915_READ(reg);
3223 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3224 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3225 I915_WRITE(reg, temp);
3226
3227 reg = FDI_RX_CTL(pipe);
3228 temp = I915_READ(reg);
3229 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3230 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3231 I915_WRITE(reg, temp);
3232
3233 POSTING_READ(reg);
3234 udelay(2); /* should be 1.5us */
3235
3236 for (i = 0; i < 4; i++) {
3237 reg = FDI_RX_IIR(pipe);
3238 temp = I915_READ(reg);
3239 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3240
3241 if (temp & FDI_RX_SYMBOL_LOCK ||
3242 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3243 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3244 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3245 i);
3246 goto train_done;
3247 }
3248 udelay(2); /* should be 1.5us */
3249 }
3250 if (i == 4)
3251 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3252 }
3253
3254 train_done:
3255 DRM_DEBUG_KMS("FDI train done.\n");
3256 }
3257
3258 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3259 {
3260 struct drm_device *dev = intel_crtc->base.dev;
3261 struct drm_i915_private *dev_priv = dev->dev_private;
3262 int pipe = intel_crtc->pipe;
3263 u32 reg, temp;
3264
3265
3266 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3267 reg = FDI_RX_CTL(pipe);
3268 temp = I915_READ(reg);
3269 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3270 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3271 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3272 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3273
3274 POSTING_READ(reg);
3275 udelay(200);
3276
3277 /* Switch from Rawclk to PCDclk */
3278 temp = I915_READ(reg);
3279 I915_WRITE(reg, temp | FDI_PCDCLK);
3280
3281 POSTING_READ(reg);
3282 udelay(200);
3283
3284 /* Enable CPU FDI TX PLL, always on for Ironlake */
3285 reg = FDI_TX_CTL(pipe);
3286 temp = I915_READ(reg);
3287 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3288 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3289
3290 POSTING_READ(reg);
3291 udelay(100);
3292 }
3293 }
3294
3295 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3296 {
3297 struct drm_device *dev = intel_crtc->base.dev;
3298 struct drm_i915_private *dev_priv = dev->dev_private;
3299 int pipe = intel_crtc->pipe;
3300 u32 reg, temp;
3301
3302 /* Switch from PCDclk to Rawclk */
3303 reg = FDI_RX_CTL(pipe);
3304 temp = I915_READ(reg);
3305 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3306
3307 /* Disable CPU FDI TX PLL */
3308 reg = FDI_TX_CTL(pipe);
3309 temp = I915_READ(reg);
3310 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3311
3312 POSTING_READ(reg);
3313 udelay(100);
3314
3315 reg = FDI_RX_CTL(pipe);
3316 temp = I915_READ(reg);
3317 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3318
3319 /* Wait for the clocks to turn off. */
3320 POSTING_READ(reg);
3321 udelay(100);
3322 }
3323
3324 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3325 {
3326 struct drm_device *dev = crtc->dev;
3327 struct drm_i915_private *dev_priv = dev->dev_private;
3328 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3329 int pipe = intel_crtc->pipe;
3330 u32 reg, temp;
3331
3332 /* disable CPU FDI tx and PCH FDI rx */
3333 reg = FDI_TX_CTL(pipe);
3334 temp = I915_READ(reg);
3335 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3336 POSTING_READ(reg);
3337
3338 reg = FDI_RX_CTL(pipe);
3339 temp = I915_READ(reg);
3340 temp &= ~(0x7 << 16);
3341 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3342 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3343
3344 POSTING_READ(reg);
3345 udelay(100);
3346
3347 /* Ironlake workaround, disable clock pointer after downing FDI */
3348 if (HAS_PCH_IBX(dev))
3349 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3350
3351 /* still set train pattern 1 */
3352 reg = FDI_TX_CTL(pipe);
3353 temp = I915_READ(reg);
3354 temp &= ~FDI_LINK_TRAIN_NONE;
3355 temp |= FDI_LINK_TRAIN_PATTERN_1;
3356 I915_WRITE(reg, temp);
3357
3358 reg = FDI_RX_CTL(pipe);
3359 temp = I915_READ(reg);
3360 if (HAS_PCH_CPT(dev)) {
3361 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3362 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3363 } else {
3364 temp &= ~FDI_LINK_TRAIN_NONE;
3365 temp |= FDI_LINK_TRAIN_PATTERN_1;
3366 }
3367 /* BPC in FDI rx is consistent with that in PIPECONF */
3368 temp &= ~(0x07 << 16);
3369 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3370 I915_WRITE(reg, temp);
3371
3372 POSTING_READ(reg);
3373 udelay(100);
3374 }
3375
3376 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3377 {
3378 struct intel_crtc *crtc;
3379
3380 /* Note that we don't need to be called with mode_config.lock here
3381 * as our list of CRTC objects is static for the lifetime of the
3382 * device and so cannot disappear as we iterate. Similarly, we can
3383 * happily treat the predicates as racy, atomic checks as userspace
3384 * cannot claim and pin a new fb without at least acquring the
3385 * struct_mutex and so serialising with us.
3386 */
3387 for_each_intel_crtc(dev, crtc) {
3388 if (atomic_read(&crtc->unpin_work_count) == 0)
3389 continue;
3390
3391 if (crtc->unpin_work)
3392 intel_wait_for_vblank(dev, crtc->pipe);
3393
3394 return true;
3395 }
3396
3397 return false;
3398 }
3399
3400 static void page_flip_completed(struct intel_crtc *intel_crtc)
3401 {
3402 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3403 struct intel_unpin_work *work = intel_crtc->unpin_work;
3404
3405 /* ensure that the unpin work is consistent wrt ->pending. */
3406 smp_rmb();
3407 intel_crtc->unpin_work = NULL;
3408
3409 if (work->event)
3410 drm_send_vblank_event(intel_crtc->base.dev,
3411 intel_crtc->pipe,
3412 work->event);
3413
3414 drm_crtc_vblank_put(&intel_crtc->base);
3415
3416 wake_up_all(&dev_priv->pending_flip_queue);
3417 queue_work(dev_priv->wq, &work->work);
3418
3419 trace_i915_flip_complete(intel_crtc->plane,
3420 work->pending_flip_obj);
3421 }
3422
3423 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3424 {
3425 struct drm_device *dev = crtc->dev;
3426 struct drm_i915_private *dev_priv = dev->dev_private;
3427
3428 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3429 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3430 !intel_crtc_has_pending_flip(crtc),
3431 60*HZ) == 0)) {
3432 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3433
3434 spin_lock_irq(&dev->event_lock);
3435 if (intel_crtc->unpin_work) {
3436 WARN_ONCE(1, "Removing stuck page flip\n");
3437 page_flip_completed(intel_crtc);
3438 }
3439 spin_unlock_irq(&dev->event_lock);
3440 }
3441
3442 if (crtc->primary->fb) {
3443 mutex_lock(&dev->struct_mutex);
3444 intel_finish_fb(crtc->primary->fb);
3445 mutex_unlock(&dev->struct_mutex);
3446 }
3447 }
3448
3449 /* Program iCLKIP clock to the desired frequency */
3450 static void lpt_program_iclkip(struct drm_crtc *crtc)
3451 {
3452 struct drm_device *dev = crtc->dev;
3453 struct drm_i915_private *dev_priv = dev->dev_private;
3454 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3455 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3456 u32 temp;
3457
3458 mutex_lock(&dev_priv->dpio_lock);
3459
3460 /* It is necessary to ungate the pixclk gate prior to programming
3461 * the divisors, and gate it back when it is done.
3462 */
3463 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3464
3465 /* Disable SSCCTL */
3466 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3467 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3468 SBI_SSCCTL_DISABLE,
3469 SBI_ICLK);
3470
3471 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3472 if (clock == 20000) {
3473 auxdiv = 1;
3474 divsel = 0x41;
3475 phaseinc = 0x20;
3476 } else {
3477 /* The iCLK virtual clock root frequency is in MHz,
3478 * but the adjusted_mode->crtc_clock in in KHz. To get the
3479 * divisors, it is necessary to divide one by another, so we
3480 * convert the virtual clock precision to KHz here for higher
3481 * precision.
3482 */
3483 u32 iclk_virtual_root_freq = 172800 * 1000;
3484 u32 iclk_pi_range = 64;
3485 u32 desired_divisor, msb_divisor_value, pi_value;
3486
3487 desired_divisor = (iclk_virtual_root_freq / clock);
3488 msb_divisor_value = desired_divisor / iclk_pi_range;
3489 pi_value = desired_divisor % iclk_pi_range;
3490
3491 auxdiv = 0;
3492 divsel = msb_divisor_value - 2;
3493 phaseinc = pi_value;
3494 }
3495
3496 /* This should not happen with any sane values */
3497 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3498 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3499 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3500 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3501
3502 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3503 clock,
3504 auxdiv,
3505 divsel,
3506 phasedir,
3507 phaseinc);
3508
3509 /* Program SSCDIVINTPHASE6 */
3510 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3511 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3512 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3513 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3514 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3515 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3516 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3517 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3518
3519 /* Program SSCAUXDIV */
3520 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3521 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3522 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3523 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3524
3525 /* Enable modulator and associated divider */
3526 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3527 temp &= ~SBI_SSCCTL_DISABLE;
3528 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3529
3530 /* Wait for initialization time */
3531 udelay(24);
3532
3533 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3534
3535 mutex_unlock(&dev_priv->dpio_lock);
3536 }
3537
3538 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3539 enum pipe pch_transcoder)
3540 {
3541 struct drm_device *dev = crtc->base.dev;
3542 struct drm_i915_private *dev_priv = dev->dev_private;
3543 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3544
3545 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3546 I915_READ(HTOTAL(cpu_transcoder)));
3547 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3548 I915_READ(HBLANK(cpu_transcoder)));
3549 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3550 I915_READ(HSYNC(cpu_transcoder)));
3551
3552 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3553 I915_READ(VTOTAL(cpu_transcoder)));
3554 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3555 I915_READ(VBLANK(cpu_transcoder)));
3556 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3557 I915_READ(VSYNC(cpu_transcoder)));
3558 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3559 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3560 }
3561
3562 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3563 {
3564 struct drm_i915_private *dev_priv = dev->dev_private;
3565 uint32_t temp;
3566
3567 temp = I915_READ(SOUTH_CHICKEN1);
3568 if (temp & FDI_BC_BIFURCATION_SELECT)
3569 return;
3570
3571 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3572 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3573
3574 temp |= FDI_BC_BIFURCATION_SELECT;
3575 DRM_DEBUG_KMS("enabling fdi C rx\n");
3576 I915_WRITE(SOUTH_CHICKEN1, temp);
3577 POSTING_READ(SOUTH_CHICKEN1);
3578 }
3579
3580 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3581 {
3582 struct drm_device *dev = intel_crtc->base.dev;
3583 struct drm_i915_private *dev_priv = dev->dev_private;
3584
3585 switch (intel_crtc->pipe) {
3586 case PIPE_A:
3587 break;
3588 case PIPE_B:
3589 if (intel_crtc->config.fdi_lanes > 2)
3590 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3591 else
3592 cpt_enable_fdi_bc_bifurcation(dev);
3593
3594 break;
3595 case PIPE_C:
3596 cpt_enable_fdi_bc_bifurcation(dev);
3597
3598 break;
3599 default:
3600 BUG();
3601 }
3602 }
3603
3604 /*
3605 * Enable PCH resources required for PCH ports:
3606 * - PCH PLLs
3607 * - FDI training & RX/TX
3608 * - update transcoder timings
3609 * - DP transcoding bits
3610 * - transcoder
3611 */
3612 static void ironlake_pch_enable(struct drm_crtc *crtc)
3613 {
3614 struct drm_device *dev = crtc->dev;
3615 struct drm_i915_private *dev_priv = dev->dev_private;
3616 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3617 int pipe = intel_crtc->pipe;
3618 u32 reg, temp;
3619
3620 assert_pch_transcoder_disabled(dev_priv, pipe);
3621
3622 if (IS_IVYBRIDGE(dev))
3623 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3624
3625 /* Write the TU size bits before fdi link training, so that error
3626 * detection works. */
3627 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3628 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3629
3630 /* For PCH output, training FDI link */
3631 dev_priv->display.fdi_link_train(crtc);
3632
3633 /* We need to program the right clock selection before writing the pixel
3634 * mutliplier into the DPLL. */
3635 if (HAS_PCH_CPT(dev)) {
3636 u32 sel;
3637
3638 temp = I915_READ(PCH_DPLL_SEL);
3639 temp |= TRANS_DPLL_ENABLE(pipe);
3640 sel = TRANS_DPLLB_SEL(pipe);
3641 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3642 temp |= sel;
3643 else
3644 temp &= ~sel;
3645 I915_WRITE(PCH_DPLL_SEL, temp);
3646 }
3647
3648 /* XXX: pch pll's can be enabled any time before we enable the PCH
3649 * transcoder, and we actually should do this to not upset any PCH
3650 * transcoder that already use the clock when we share it.
3651 *
3652 * Note that enable_shared_dpll tries to do the right thing, but
3653 * get_shared_dpll unconditionally resets the pll - we need that to have
3654 * the right LVDS enable sequence. */
3655 intel_enable_shared_dpll(intel_crtc);
3656
3657 /* set transcoder timing, panel must allow it */
3658 assert_panel_unlocked(dev_priv, pipe);
3659 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3660
3661 intel_fdi_normal_train(crtc);
3662
3663 /* For PCH DP, enable TRANS_DP_CTL */
3664 if (HAS_PCH_CPT(dev) &&
3665 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3666 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3667 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3668 reg = TRANS_DP_CTL(pipe);
3669 temp = I915_READ(reg);
3670 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3671 TRANS_DP_SYNC_MASK |
3672 TRANS_DP_BPC_MASK);
3673 temp |= (TRANS_DP_OUTPUT_ENABLE |
3674 TRANS_DP_ENH_FRAMING);
3675 temp |= bpc << 9; /* same format but at 11:9 */
3676
3677 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3678 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3679 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3680 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3681
3682 switch (intel_trans_dp_port_sel(crtc)) {
3683 case PCH_DP_B:
3684 temp |= TRANS_DP_PORT_SEL_B;
3685 break;
3686 case PCH_DP_C:
3687 temp |= TRANS_DP_PORT_SEL_C;
3688 break;
3689 case PCH_DP_D:
3690 temp |= TRANS_DP_PORT_SEL_D;
3691 break;
3692 default:
3693 BUG();
3694 }
3695
3696 I915_WRITE(reg, temp);
3697 }
3698
3699 ironlake_enable_pch_transcoder(dev_priv, pipe);
3700 }
3701
3702 static void lpt_pch_enable(struct drm_crtc *crtc)
3703 {
3704 struct drm_device *dev = crtc->dev;
3705 struct drm_i915_private *dev_priv = dev->dev_private;
3706 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3707 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3708
3709 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3710
3711 lpt_program_iclkip(crtc);
3712
3713 /* Set transcoder timing. */
3714 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3715
3716 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3717 }
3718
3719 void intel_put_shared_dpll(struct intel_crtc *crtc)
3720 {
3721 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3722
3723 if (pll == NULL)
3724 return;
3725
3726 if (pll->refcount == 0) {
3727 WARN(1, "bad %s refcount\n", pll->name);
3728 return;
3729 }
3730
3731 if (--pll->refcount == 0) {
3732 WARN_ON(pll->on);
3733 WARN_ON(pll->active);
3734 }
3735
3736 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3737 }
3738
3739 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3740 {
3741 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3742 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3743 enum intel_dpll_id i;
3744
3745 if (pll) {
3746 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3747 crtc->base.base.id, pll->name);
3748 intel_put_shared_dpll(crtc);
3749 }
3750
3751 if (HAS_PCH_IBX(dev_priv->dev)) {
3752 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3753 i = (enum intel_dpll_id) crtc->pipe;
3754 pll = &dev_priv->shared_dplls[i];
3755
3756 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3757 crtc->base.base.id, pll->name);
3758
3759 WARN_ON(pll->refcount);
3760
3761 goto found;
3762 }
3763
3764 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3765 pll = &dev_priv->shared_dplls[i];
3766
3767 /* Only want to check enabled timings first */
3768 if (pll->refcount == 0)
3769 continue;
3770
3771 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3772 sizeof(pll->hw_state)) == 0) {
3773 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3774 crtc->base.base.id,
3775 pll->name, pll->refcount, pll->active);
3776
3777 goto found;
3778 }
3779 }
3780
3781 /* Ok no matching timings, maybe there's a free one? */
3782 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3783 pll = &dev_priv->shared_dplls[i];
3784 if (pll->refcount == 0) {
3785 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3786 crtc->base.base.id, pll->name);
3787 goto found;
3788 }
3789 }
3790
3791 return NULL;
3792
3793 found:
3794 if (pll->refcount == 0)
3795 pll->hw_state = crtc->config.dpll_hw_state;
3796
3797 crtc->config.shared_dpll = i;
3798 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3799 pipe_name(crtc->pipe));
3800
3801 pll->refcount++;
3802
3803 return pll;
3804 }
3805
3806 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3807 {
3808 struct drm_i915_private *dev_priv = dev->dev_private;
3809 int dslreg = PIPEDSL(pipe);
3810 u32 temp;
3811
3812 temp = I915_READ(dslreg);
3813 udelay(500);
3814 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3815 if (wait_for(I915_READ(dslreg) != temp, 5))
3816 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3817 }
3818 }
3819
3820 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3821 {
3822 struct drm_device *dev = crtc->base.dev;
3823 struct drm_i915_private *dev_priv = dev->dev_private;
3824 int pipe = crtc->pipe;
3825
3826 if (crtc->config.pch_pfit.enabled) {
3827 /* Force use of hard-coded filter coefficients
3828 * as some pre-programmed values are broken,
3829 * e.g. x201.
3830 */
3831 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3832 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3833 PF_PIPE_SEL_IVB(pipe));
3834 else
3835 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3836 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3837 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3838 }
3839 }
3840
3841 static void intel_enable_planes(struct drm_crtc *crtc)
3842 {
3843 struct drm_device *dev = crtc->dev;
3844 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3845 struct drm_plane *plane;
3846 struct intel_plane *intel_plane;
3847
3848 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3849 intel_plane = to_intel_plane(plane);
3850 if (intel_plane->pipe == pipe)
3851 intel_plane_restore(&intel_plane->base);
3852 }
3853 }
3854
3855 static void intel_disable_planes(struct drm_crtc *crtc)
3856 {
3857 struct drm_device *dev = crtc->dev;
3858 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3859 struct drm_plane *plane;
3860 struct intel_plane *intel_plane;
3861
3862 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3863 intel_plane = to_intel_plane(plane);
3864 if (intel_plane->pipe == pipe)
3865 intel_plane_disable(&intel_plane->base);
3866 }
3867 }
3868
3869 void hsw_enable_ips(struct intel_crtc *crtc)
3870 {
3871 struct drm_device *dev = crtc->base.dev;
3872 struct drm_i915_private *dev_priv = dev->dev_private;
3873
3874 if (!crtc->config.ips_enabled)
3875 return;
3876
3877 /* We can only enable IPS after we enable a plane and wait for a vblank */
3878 intel_wait_for_vblank(dev, crtc->pipe);
3879
3880 assert_plane_enabled(dev_priv, crtc->plane);
3881 if (IS_BROADWELL(dev)) {
3882 mutex_lock(&dev_priv->rps.hw_lock);
3883 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3884 mutex_unlock(&dev_priv->rps.hw_lock);
3885 /* Quoting Art Runyan: "its not safe to expect any particular
3886 * value in IPS_CTL bit 31 after enabling IPS through the
3887 * mailbox." Moreover, the mailbox may return a bogus state,
3888 * so we need to just enable it and continue on.
3889 */
3890 } else {
3891 I915_WRITE(IPS_CTL, IPS_ENABLE);
3892 /* The bit only becomes 1 in the next vblank, so this wait here
3893 * is essentially intel_wait_for_vblank. If we don't have this
3894 * and don't wait for vblanks until the end of crtc_enable, then
3895 * the HW state readout code will complain that the expected
3896 * IPS_CTL value is not the one we read. */
3897 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3898 DRM_ERROR("Timed out waiting for IPS enable\n");
3899 }
3900 }
3901
3902 void hsw_disable_ips(struct intel_crtc *crtc)
3903 {
3904 struct drm_device *dev = crtc->base.dev;
3905 struct drm_i915_private *dev_priv = dev->dev_private;
3906
3907 if (!crtc->config.ips_enabled)
3908 return;
3909
3910 assert_plane_enabled(dev_priv, crtc->plane);
3911 if (IS_BROADWELL(dev)) {
3912 mutex_lock(&dev_priv->rps.hw_lock);
3913 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3914 mutex_unlock(&dev_priv->rps.hw_lock);
3915 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3916 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3917 DRM_ERROR("Timed out waiting for IPS disable\n");
3918 } else {
3919 I915_WRITE(IPS_CTL, 0);
3920 POSTING_READ(IPS_CTL);
3921 }
3922
3923 /* We need to wait for a vblank before we can disable the plane. */
3924 intel_wait_for_vblank(dev, crtc->pipe);
3925 }
3926
3927 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3928 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3929 {
3930 struct drm_device *dev = crtc->dev;
3931 struct drm_i915_private *dev_priv = dev->dev_private;
3932 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3933 enum pipe pipe = intel_crtc->pipe;
3934 int palreg = PALETTE(pipe);
3935 int i;
3936 bool reenable_ips = false;
3937
3938 /* The clocks have to be on to load the palette. */
3939 if (!crtc->enabled || !intel_crtc->active)
3940 return;
3941
3942 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3943 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3944 assert_dsi_pll_enabled(dev_priv);
3945 else
3946 assert_pll_enabled(dev_priv, pipe);
3947 }
3948
3949 /* use legacy palette for Ironlake */
3950 if (!HAS_GMCH_DISPLAY(dev))
3951 palreg = LGC_PALETTE(pipe);
3952
3953 /* Workaround : Do not read or write the pipe palette/gamma data while
3954 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3955 */
3956 if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3957 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3958 GAMMA_MODE_MODE_SPLIT)) {
3959 hsw_disable_ips(intel_crtc);
3960 reenable_ips = true;
3961 }
3962
3963 for (i = 0; i < 256; i++) {
3964 I915_WRITE(palreg + 4 * i,
3965 (intel_crtc->lut_r[i] << 16) |
3966 (intel_crtc->lut_g[i] << 8) |
3967 intel_crtc->lut_b[i]);
3968 }
3969
3970 if (reenable_ips)
3971 hsw_enable_ips(intel_crtc);
3972 }
3973
3974 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3975 {
3976 if (!enable && intel_crtc->overlay) {
3977 struct drm_device *dev = intel_crtc->base.dev;
3978 struct drm_i915_private *dev_priv = dev->dev_private;
3979
3980 mutex_lock(&dev->struct_mutex);
3981 dev_priv->mm.interruptible = false;
3982 (void) intel_overlay_switch_off(intel_crtc->overlay);
3983 dev_priv->mm.interruptible = true;
3984 mutex_unlock(&dev->struct_mutex);
3985 }
3986
3987 /* Let userspace switch the overlay on again. In most cases userspace
3988 * has to recompute where to put it anyway.
3989 */
3990 }
3991
3992 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
3993 {
3994 struct drm_device *dev = crtc->dev;
3995 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3996 int pipe = intel_crtc->pipe;
3997
3998 intel_enable_primary_hw_plane(crtc->primary, crtc);
3999 intel_enable_planes(crtc);
4000 intel_crtc_update_cursor(crtc, true);
4001 intel_crtc_dpms_overlay(intel_crtc, true);
4002
4003 hsw_enable_ips(intel_crtc);
4004
4005 mutex_lock(&dev->struct_mutex);
4006 intel_update_fbc(dev);
4007 mutex_unlock(&dev->struct_mutex);
4008
4009 /*
4010 * FIXME: Once we grow proper nuclear flip support out of this we need
4011 * to compute the mask of flip planes precisely. For the time being
4012 * consider this a flip from a NULL plane.
4013 */
4014 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4015 }
4016
4017 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4018 {
4019 struct drm_device *dev = crtc->dev;
4020 struct drm_i915_private *dev_priv = dev->dev_private;
4021 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4022 int pipe = intel_crtc->pipe;
4023 int plane = intel_crtc->plane;
4024
4025 intel_crtc_wait_for_pending_flips(crtc);
4026
4027 if (dev_priv->fbc.plane == plane)
4028 intel_disable_fbc(dev);
4029
4030 hsw_disable_ips(intel_crtc);
4031
4032 intel_crtc_dpms_overlay(intel_crtc, false);
4033 intel_crtc_update_cursor(crtc, false);
4034 intel_disable_planes(crtc);
4035 intel_disable_primary_hw_plane(crtc->primary, crtc);
4036
4037 /*
4038 * FIXME: Once we grow proper nuclear flip support out of this we need
4039 * to compute the mask of flip planes precisely. For the time being
4040 * consider this a flip to a NULL plane.
4041 */
4042 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4043 }
4044
4045 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4046 {
4047 struct drm_device *dev = crtc->dev;
4048 struct drm_i915_private *dev_priv = dev->dev_private;
4049 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4050 struct intel_encoder *encoder;
4051 int pipe = intel_crtc->pipe;
4052
4053 WARN_ON(!crtc->enabled);
4054
4055 if (intel_crtc->active)
4056 return;
4057
4058 if (intel_crtc->config.has_pch_encoder)
4059 intel_prepare_shared_dpll(intel_crtc);
4060
4061 if (intel_crtc->config.has_dp_encoder)
4062 intel_dp_set_m_n(intel_crtc);
4063
4064 intel_set_pipe_timings(intel_crtc);
4065
4066 if (intel_crtc->config.has_pch_encoder) {
4067 intel_cpu_transcoder_set_m_n(intel_crtc,
4068 &intel_crtc->config.fdi_m_n, NULL);
4069 }
4070
4071 ironlake_set_pipeconf(crtc);
4072
4073 intel_crtc->active = true;
4074
4075 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4076 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4077
4078 for_each_encoder_on_crtc(dev, crtc, encoder)
4079 if (encoder->pre_enable)
4080 encoder->pre_enable(encoder);
4081
4082 if (intel_crtc->config.has_pch_encoder) {
4083 /* Note: FDI PLL enabling _must_ be done before we enable the
4084 * cpu pipes, hence this is separate from all the other fdi/pch
4085 * enabling. */
4086 ironlake_fdi_pll_enable(intel_crtc);
4087 } else {
4088 assert_fdi_tx_disabled(dev_priv, pipe);
4089 assert_fdi_rx_disabled(dev_priv, pipe);
4090 }
4091
4092 ironlake_pfit_enable(intel_crtc);
4093
4094 /*
4095 * On ILK+ LUT must be loaded before the pipe is running but with
4096 * clocks enabled
4097 */
4098 intel_crtc_load_lut(crtc);
4099
4100 intel_update_watermarks(crtc);
4101 intel_enable_pipe(intel_crtc);
4102
4103 if (intel_crtc->config.has_pch_encoder)
4104 ironlake_pch_enable(crtc);
4105
4106 for_each_encoder_on_crtc(dev, crtc, encoder)
4107 encoder->enable(encoder);
4108
4109 if (HAS_PCH_CPT(dev))
4110 cpt_verify_modeset(dev, intel_crtc->pipe);
4111
4112 assert_vblank_disabled(crtc);
4113 drm_crtc_vblank_on(crtc);
4114
4115 intel_crtc_enable_planes(crtc);
4116 }
4117
4118 /* IPS only exists on ULT machines and is tied to pipe A. */
4119 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4120 {
4121 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4122 }
4123
4124 /*
4125 * This implements the workaround described in the "notes" section of the mode
4126 * set sequence documentation. When going from no pipes or single pipe to
4127 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4128 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4129 */
4130 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4131 {
4132 struct drm_device *dev = crtc->base.dev;
4133 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4134
4135 /* We want to get the other_active_crtc only if there's only 1 other
4136 * active crtc. */
4137 for_each_intel_crtc(dev, crtc_it) {
4138 if (!crtc_it->active || crtc_it == crtc)
4139 continue;
4140
4141 if (other_active_crtc)
4142 return;
4143
4144 other_active_crtc = crtc_it;
4145 }
4146 if (!other_active_crtc)
4147 return;
4148
4149 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4150 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4151 }
4152
4153 static void haswell_crtc_enable(struct drm_crtc *crtc)
4154 {
4155 struct drm_device *dev = crtc->dev;
4156 struct drm_i915_private *dev_priv = dev->dev_private;
4157 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4158 struct intel_encoder *encoder;
4159 int pipe = intel_crtc->pipe;
4160
4161 WARN_ON(!crtc->enabled);
4162
4163 if (intel_crtc->active)
4164 return;
4165
4166 if (intel_crtc_to_shared_dpll(intel_crtc))
4167 intel_enable_shared_dpll(intel_crtc);
4168
4169 if (intel_crtc->config.has_dp_encoder)
4170 intel_dp_set_m_n(intel_crtc);
4171
4172 intel_set_pipe_timings(intel_crtc);
4173
4174 if (intel_crtc->config.has_pch_encoder) {
4175 intel_cpu_transcoder_set_m_n(intel_crtc,
4176 &intel_crtc->config.fdi_m_n, NULL);
4177 }
4178
4179 haswell_set_pipeconf(crtc);
4180
4181 intel_set_pipe_csc(crtc);
4182
4183 intel_crtc->active = true;
4184
4185 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4186 for_each_encoder_on_crtc(dev, crtc, encoder)
4187 if (encoder->pre_enable)
4188 encoder->pre_enable(encoder);
4189
4190 if (intel_crtc->config.has_pch_encoder) {
4191 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4192 dev_priv->display.fdi_link_train(crtc);
4193 }
4194
4195 intel_ddi_enable_pipe_clock(intel_crtc);
4196
4197 ironlake_pfit_enable(intel_crtc);
4198
4199 /*
4200 * On ILK+ LUT must be loaded before the pipe is running but with
4201 * clocks enabled
4202 */
4203 intel_crtc_load_lut(crtc);
4204
4205 intel_ddi_set_pipe_settings(crtc);
4206 intel_ddi_enable_transcoder_func(crtc);
4207
4208 intel_update_watermarks(crtc);
4209 intel_enable_pipe(intel_crtc);
4210
4211 if (intel_crtc->config.has_pch_encoder)
4212 lpt_pch_enable(crtc);
4213
4214 if (intel_crtc->config.dp_encoder_is_mst)
4215 intel_ddi_set_vc_payload_alloc(crtc, true);
4216
4217 for_each_encoder_on_crtc(dev, crtc, encoder) {
4218 encoder->enable(encoder);
4219 intel_opregion_notify_encoder(encoder, true);
4220 }
4221
4222 assert_vblank_disabled(crtc);
4223 drm_crtc_vblank_on(crtc);
4224
4225 /* If we change the relative order between pipe/planes enabling, we need
4226 * to change the workaround. */
4227 haswell_mode_set_planes_workaround(intel_crtc);
4228 intel_crtc_enable_planes(crtc);
4229 }
4230
4231 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4232 {
4233 struct drm_device *dev = crtc->base.dev;
4234 struct drm_i915_private *dev_priv = dev->dev_private;
4235 int pipe = crtc->pipe;
4236
4237 /* To avoid upsetting the power well on haswell only disable the pfit if
4238 * it's in use. The hw state code will make sure we get this right. */
4239 if (crtc->config.pch_pfit.enabled) {
4240 I915_WRITE(PF_CTL(pipe), 0);
4241 I915_WRITE(PF_WIN_POS(pipe), 0);
4242 I915_WRITE(PF_WIN_SZ(pipe), 0);
4243 }
4244 }
4245
4246 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4247 {
4248 struct drm_device *dev = crtc->dev;
4249 struct drm_i915_private *dev_priv = dev->dev_private;
4250 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4251 struct intel_encoder *encoder;
4252 int pipe = intel_crtc->pipe;
4253 u32 reg, temp;
4254
4255 if (!intel_crtc->active)
4256 return;
4257
4258 intel_crtc_disable_planes(crtc);
4259
4260 drm_crtc_vblank_off(crtc);
4261 assert_vblank_disabled(crtc);
4262
4263 for_each_encoder_on_crtc(dev, crtc, encoder)
4264 encoder->disable(encoder);
4265
4266 if (intel_crtc->config.has_pch_encoder)
4267 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
4268
4269 intel_disable_pipe(intel_crtc);
4270
4271 ironlake_pfit_disable(intel_crtc);
4272
4273 for_each_encoder_on_crtc(dev, crtc, encoder)
4274 if (encoder->post_disable)
4275 encoder->post_disable(encoder);
4276
4277 if (intel_crtc->config.has_pch_encoder) {
4278 ironlake_fdi_disable(crtc);
4279
4280 ironlake_disable_pch_transcoder(dev_priv, pipe);
4281 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4282
4283 if (HAS_PCH_CPT(dev)) {
4284 /* disable TRANS_DP_CTL */
4285 reg = TRANS_DP_CTL(pipe);
4286 temp = I915_READ(reg);
4287 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4288 TRANS_DP_PORT_SEL_MASK);
4289 temp |= TRANS_DP_PORT_SEL_NONE;
4290 I915_WRITE(reg, temp);
4291
4292 /* disable DPLL_SEL */
4293 temp = I915_READ(PCH_DPLL_SEL);
4294 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4295 I915_WRITE(PCH_DPLL_SEL, temp);
4296 }
4297
4298 /* disable PCH DPLL */
4299 intel_disable_shared_dpll(intel_crtc);
4300
4301 ironlake_fdi_pll_disable(intel_crtc);
4302 }
4303
4304 intel_crtc->active = false;
4305 intel_update_watermarks(crtc);
4306
4307 mutex_lock(&dev->struct_mutex);
4308 intel_update_fbc(dev);
4309 mutex_unlock(&dev->struct_mutex);
4310 }
4311
4312 static void haswell_crtc_disable(struct drm_crtc *crtc)
4313 {
4314 struct drm_device *dev = crtc->dev;
4315 struct drm_i915_private *dev_priv = dev->dev_private;
4316 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4317 struct intel_encoder *encoder;
4318 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4319
4320 if (!intel_crtc->active)
4321 return;
4322
4323 intel_crtc_disable_planes(crtc);
4324
4325 drm_crtc_vblank_off(crtc);
4326 assert_vblank_disabled(crtc);
4327
4328 for_each_encoder_on_crtc(dev, crtc, encoder) {
4329 intel_opregion_notify_encoder(encoder, false);
4330 encoder->disable(encoder);
4331 }
4332
4333 if (intel_crtc->config.has_pch_encoder)
4334 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4335 intel_disable_pipe(intel_crtc);
4336
4337 if (intel_crtc->config.dp_encoder_is_mst)
4338 intel_ddi_set_vc_payload_alloc(crtc, false);
4339
4340 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4341
4342 ironlake_pfit_disable(intel_crtc);
4343
4344 intel_ddi_disable_pipe_clock(intel_crtc);
4345
4346 if (intel_crtc->config.has_pch_encoder) {
4347 lpt_disable_pch_transcoder(dev_priv);
4348 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4349 intel_ddi_fdi_disable(crtc);
4350 }
4351
4352 for_each_encoder_on_crtc(dev, crtc, encoder)
4353 if (encoder->post_disable)
4354 encoder->post_disable(encoder);
4355
4356 intel_crtc->active = false;
4357 intel_update_watermarks(crtc);
4358
4359 mutex_lock(&dev->struct_mutex);
4360 intel_update_fbc(dev);
4361 mutex_unlock(&dev->struct_mutex);
4362
4363 if (intel_crtc_to_shared_dpll(intel_crtc))
4364 intel_disable_shared_dpll(intel_crtc);
4365 }
4366
4367 static void ironlake_crtc_off(struct drm_crtc *crtc)
4368 {
4369 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4370 intel_put_shared_dpll(intel_crtc);
4371 }
4372
4373
4374 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4375 {
4376 struct drm_device *dev = crtc->base.dev;
4377 struct drm_i915_private *dev_priv = dev->dev_private;
4378 struct intel_crtc_config *pipe_config = &crtc->config;
4379
4380 if (!crtc->config.gmch_pfit.control)
4381 return;
4382
4383 /*
4384 * The panel fitter should only be adjusted whilst the pipe is disabled,
4385 * according to register description and PRM.
4386 */
4387 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4388 assert_pipe_disabled(dev_priv, crtc->pipe);
4389
4390 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4391 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4392
4393 /* Border color in case we don't scale up to the full screen. Black by
4394 * default, change to something else for debugging. */
4395 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4396 }
4397
4398 static enum intel_display_power_domain port_to_power_domain(enum port port)
4399 {
4400 switch (port) {
4401 case PORT_A:
4402 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4403 case PORT_B:
4404 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4405 case PORT_C:
4406 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4407 case PORT_D:
4408 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4409 default:
4410 WARN_ON_ONCE(1);
4411 return POWER_DOMAIN_PORT_OTHER;
4412 }
4413 }
4414
4415 #define for_each_power_domain(domain, mask) \
4416 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4417 if ((1 << (domain)) & (mask))
4418
4419 enum intel_display_power_domain
4420 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4421 {
4422 struct drm_device *dev = intel_encoder->base.dev;
4423 struct intel_digital_port *intel_dig_port;
4424
4425 switch (intel_encoder->type) {
4426 case INTEL_OUTPUT_UNKNOWN:
4427 /* Only DDI platforms should ever use this output type */
4428 WARN_ON_ONCE(!HAS_DDI(dev));
4429 case INTEL_OUTPUT_DISPLAYPORT:
4430 case INTEL_OUTPUT_HDMI:
4431 case INTEL_OUTPUT_EDP:
4432 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4433 return port_to_power_domain(intel_dig_port->port);
4434 case INTEL_OUTPUT_DP_MST:
4435 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4436 return port_to_power_domain(intel_dig_port->port);
4437 case INTEL_OUTPUT_ANALOG:
4438 return POWER_DOMAIN_PORT_CRT;
4439 case INTEL_OUTPUT_DSI:
4440 return POWER_DOMAIN_PORT_DSI;
4441 default:
4442 return POWER_DOMAIN_PORT_OTHER;
4443 }
4444 }
4445
4446 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4447 {
4448 struct drm_device *dev = crtc->dev;
4449 struct intel_encoder *intel_encoder;
4450 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4451 enum pipe pipe = intel_crtc->pipe;
4452 unsigned long mask;
4453 enum transcoder transcoder;
4454
4455 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4456
4457 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4458 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4459 if (intel_crtc->config.pch_pfit.enabled ||
4460 intel_crtc->config.pch_pfit.force_thru)
4461 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4462
4463 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4464 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4465
4466 return mask;
4467 }
4468
4469 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4470 bool enable)
4471 {
4472 if (dev_priv->power_domains.init_power_on == enable)
4473 return;
4474
4475 if (enable)
4476 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4477 else
4478 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4479
4480 dev_priv->power_domains.init_power_on = enable;
4481 }
4482
4483 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4484 {
4485 struct drm_i915_private *dev_priv = dev->dev_private;
4486 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4487 struct intel_crtc *crtc;
4488
4489 /*
4490 * First get all needed power domains, then put all unneeded, to avoid
4491 * any unnecessary toggling of the power wells.
4492 */
4493 for_each_intel_crtc(dev, crtc) {
4494 enum intel_display_power_domain domain;
4495
4496 if (!crtc->base.enabled)
4497 continue;
4498
4499 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4500
4501 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4502 intel_display_power_get(dev_priv, domain);
4503 }
4504
4505 for_each_intel_crtc(dev, crtc) {
4506 enum intel_display_power_domain domain;
4507
4508 for_each_power_domain(domain, crtc->enabled_power_domains)
4509 intel_display_power_put(dev_priv, domain);
4510
4511 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4512 }
4513
4514 intel_display_set_init_power(dev_priv, false);
4515 }
4516
4517 /* returns HPLL frequency in kHz */
4518 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4519 {
4520 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4521
4522 /* Obtain SKU information */
4523 mutex_lock(&dev_priv->dpio_lock);
4524 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4525 CCK_FUSE_HPLL_FREQ_MASK;
4526 mutex_unlock(&dev_priv->dpio_lock);
4527
4528 return vco_freq[hpll_freq] * 1000;
4529 }
4530
4531 static void vlv_update_cdclk(struct drm_device *dev)
4532 {
4533 struct drm_i915_private *dev_priv = dev->dev_private;
4534
4535 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4536 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz",
4537 dev_priv->vlv_cdclk_freq);
4538
4539 /*
4540 * Program the gmbus_freq based on the cdclk frequency.
4541 * BSpec erroneously claims we should aim for 4MHz, but
4542 * in fact 1MHz is the correct frequency.
4543 */
4544 I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq);
4545 }
4546
4547 /* Adjust CDclk dividers to allow high res or save power if possible */
4548 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4549 {
4550 struct drm_i915_private *dev_priv = dev->dev_private;
4551 u32 val, cmd;
4552
4553 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4554
4555 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4556 cmd = 2;
4557 else if (cdclk == 266667)
4558 cmd = 1;
4559 else
4560 cmd = 0;
4561
4562 mutex_lock(&dev_priv->rps.hw_lock);
4563 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4564 val &= ~DSPFREQGUAR_MASK;
4565 val |= (cmd << DSPFREQGUAR_SHIFT);
4566 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4567 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4568 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4569 50)) {
4570 DRM_ERROR("timed out waiting for CDclk change\n");
4571 }
4572 mutex_unlock(&dev_priv->rps.hw_lock);
4573
4574 if (cdclk == 400000) {
4575 u32 divider, vco;
4576
4577 vco = valleyview_get_vco(dev_priv);
4578 divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1;
4579
4580 mutex_lock(&dev_priv->dpio_lock);
4581 /* adjust cdclk divider */
4582 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4583 val &= ~DISPLAY_FREQUENCY_VALUES;
4584 val |= divider;
4585 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4586
4587 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4588 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4589 50))
4590 DRM_ERROR("timed out waiting for CDclk change\n");
4591 mutex_unlock(&dev_priv->dpio_lock);
4592 }
4593
4594 mutex_lock(&dev_priv->dpio_lock);
4595 /* adjust self-refresh exit latency value */
4596 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4597 val &= ~0x7f;
4598
4599 /*
4600 * For high bandwidth configs, we set a higher latency in the bunit
4601 * so that the core display fetch happens in time to avoid underruns.
4602 */
4603 if (cdclk == 400000)
4604 val |= 4500 / 250; /* 4.5 usec */
4605 else
4606 val |= 3000 / 250; /* 3.0 usec */
4607 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4608 mutex_unlock(&dev_priv->dpio_lock);
4609
4610 vlv_update_cdclk(dev);
4611 }
4612
4613 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4614 {
4615 struct drm_i915_private *dev_priv = dev->dev_private;
4616 u32 val, cmd;
4617
4618 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4619
4620 switch (cdclk) {
4621 case 400000:
4622 cmd = 3;
4623 break;
4624 case 333333:
4625 case 320000:
4626 cmd = 2;
4627 break;
4628 case 266667:
4629 cmd = 1;
4630 break;
4631 case 200000:
4632 cmd = 0;
4633 break;
4634 default:
4635 WARN_ON(1);
4636 return;
4637 }
4638
4639 mutex_lock(&dev_priv->rps.hw_lock);
4640 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4641 val &= ~DSPFREQGUAR_MASK_CHV;
4642 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4643 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4644 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4645 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4646 50)) {
4647 DRM_ERROR("timed out waiting for CDclk change\n");
4648 }
4649 mutex_unlock(&dev_priv->rps.hw_lock);
4650
4651 vlv_update_cdclk(dev);
4652 }
4653
4654 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4655 int max_pixclk)
4656 {
4657 int vco = valleyview_get_vco(dev_priv);
4658 int freq_320 = (vco << 1) % 320000 != 0 ? 333333 : 320000;
4659
4660 /* FIXME: Punit isn't quite ready yet */
4661 if (IS_CHERRYVIEW(dev_priv->dev))
4662 return 400000;
4663
4664 /*
4665 * Really only a few cases to deal with, as only 4 CDclks are supported:
4666 * 200MHz
4667 * 267MHz
4668 * 320/333MHz (depends on HPLL freq)
4669 * 400MHz
4670 * So we check to see whether we're above 90% of the lower bin and
4671 * adjust if needed.
4672 *
4673 * We seem to get an unstable or solid color picture at 200MHz.
4674 * Not sure what's wrong. For now use 200MHz only when all pipes
4675 * are off.
4676 */
4677 if (max_pixclk > freq_320*9/10)
4678 return 400000;
4679 else if (max_pixclk > 266667*9/10)
4680 return freq_320;
4681 else if (max_pixclk > 0)
4682 return 266667;
4683 else
4684 return 200000;
4685 }
4686
4687 /* compute the max pixel clock for new configuration */
4688 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4689 {
4690 struct drm_device *dev = dev_priv->dev;
4691 struct intel_crtc *intel_crtc;
4692 int max_pixclk = 0;
4693
4694 for_each_intel_crtc(dev, intel_crtc) {
4695 if (intel_crtc->new_enabled)
4696 max_pixclk = max(max_pixclk,
4697 intel_crtc->new_config->adjusted_mode.crtc_clock);
4698 }
4699
4700 return max_pixclk;
4701 }
4702
4703 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4704 unsigned *prepare_pipes)
4705 {
4706 struct drm_i915_private *dev_priv = dev->dev_private;
4707 struct intel_crtc *intel_crtc;
4708 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4709
4710 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4711 dev_priv->vlv_cdclk_freq)
4712 return;
4713
4714 /* disable/enable all currently active pipes while we change cdclk */
4715 for_each_intel_crtc(dev, intel_crtc)
4716 if (intel_crtc->base.enabled)
4717 *prepare_pipes |= (1 << intel_crtc->pipe);
4718 }
4719
4720 static void valleyview_modeset_global_resources(struct drm_device *dev)
4721 {
4722 struct drm_i915_private *dev_priv = dev->dev_private;
4723 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4724 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4725
4726 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
4727 if (IS_CHERRYVIEW(dev))
4728 cherryview_set_cdclk(dev, req_cdclk);
4729 else
4730 valleyview_set_cdclk(dev, req_cdclk);
4731 }
4732
4733 modeset_update_crtc_power_domains(dev);
4734 }
4735
4736 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4737 {
4738 struct drm_device *dev = crtc->dev;
4739 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4740 struct intel_encoder *encoder;
4741 int pipe = intel_crtc->pipe;
4742 bool is_dsi;
4743
4744 WARN_ON(!crtc->enabled);
4745
4746 if (intel_crtc->active)
4747 return;
4748
4749 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4750
4751 if (!is_dsi) {
4752 if (IS_CHERRYVIEW(dev))
4753 chv_prepare_pll(intel_crtc);
4754 else
4755 vlv_prepare_pll(intel_crtc);
4756 }
4757
4758 if (intel_crtc->config.has_dp_encoder)
4759 intel_dp_set_m_n(intel_crtc);
4760
4761 intel_set_pipe_timings(intel_crtc);
4762
4763 i9xx_set_pipeconf(intel_crtc);
4764
4765 intel_crtc->active = true;
4766
4767 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4768
4769 for_each_encoder_on_crtc(dev, crtc, encoder)
4770 if (encoder->pre_pll_enable)
4771 encoder->pre_pll_enable(encoder);
4772
4773 if (!is_dsi) {
4774 if (IS_CHERRYVIEW(dev))
4775 chv_enable_pll(intel_crtc);
4776 else
4777 vlv_enable_pll(intel_crtc);
4778 }
4779
4780 for_each_encoder_on_crtc(dev, crtc, encoder)
4781 if (encoder->pre_enable)
4782 encoder->pre_enable(encoder);
4783
4784 i9xx_pfit_enable(intel_crtc);
4785
4786 intel_crtc_load_lut(crtc);
4787
4788 intel_update_watermarks(crtc);
4789 intel_enable_pipe(intel_crtc);
4790
4791 for_each_encoder_on_crtc(dev, crtc, encoder)
4792 encoder->enable(encoder);
4793
4794 assert_vblank_disabled(crtc);
4795 drm_crtc_vblank_on(crtc);
4796
4797 intel_crtc_enable_planes(crtc);
4798
4799 /* Underruns don't raise interrupts, so check manually. */
4800 i9xx_check_fifo_underruns(dev);
4801 }
4802
4803 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4804 {
4805 struct drm_device *dev = crtc->base.dev;
4806 struct drm_i915_private *dev_priv = dev->dev_private;
4807
4808 I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4809 I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4810 }
4811
4812 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4813 {
4814 struct drm_device *dev = crtc->dev;
4815 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4816 struct intel_encoder *encoder;
4817 int pipe = intel_crtc->pipe;
4818
4819 WARN_ON(!crtc->enabled);
4820
4821 if (intel_crtc->active)
4822 return;
4823
4824 i9xx_set_pll_dividers(intel_crtc);
4825
4826 if (intel_crtc->config.has_dp_encoder)
4827 intel_dp_set_m_n(intel_crtc);
4828
4829 intel_set_pipe_timings(intel_crtc);
4830
4831 i9xx_set_pipeconf(intel_crtc);
4832
4833 intel_crtc->active = true;
4834
4835 if (!IS_GEN2(dev))
4836 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4837
4838 for_each_encoder_on_crtc(dev, crtc, encoder)
4839 if (encoder->pre_enable)
4840 encoder->pre_enable(encoder);
4841
4842 i9xx_enable_pll(intel_crtc);
4843
4844 i9xx_pfit_enable(intel_crtc);
4845
4846 intel_crtc_load_lut(crtc);
4847
4848 intel_update_watermarks(crtc);
4849 intel_enable_pipe(intel_crtc);
4850
4851 for_each_encoder_on_crtc(dev, crtc, encoder)
4852 encoder->enable(encoder);
4853
4854 assert_vblank_disabled(crtc);
4855 drm_crtc_vblank_on(crtc);
4856
4857 intel_crtc_enable_planes(crtc);
4858
4859 /*
4860 * Gen2 reports pipe underruns whenever all planes are disabled.
4861 * So don't enable underrun reporting before at least some planes
4862 * are enabled.
4863 * FIXME: Need to fix the logic to work when we turn off all planes
4864 * but leave the pipe running.
4865 */
4866 if (IS_GEN2(dev))
4867 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4868
4869 /* Underruns don't raise interrupts, so check manually. */
4870 i9xx_check_fifo_underruns(dev);
4871 }
4872
4873 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4874 {
4875 struct drm_device *dev = crtc->base.dev;
4876 struct drm_i915_private *dev_priv = dev->dev_private;
4877
4878 if (!crtc->config.gmch_pfit.control)
4879 return;
4880
4881 assert_pipe_disabled(dev_priv, crtc->pipe);
4882
4883 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4884 I915_READ(PFIT_CONTROL));
4885 I915_WRITE(PFIT_CONTROL, 0);
4886 }
4887
4888 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4889 {
4890 struct drm_device *dev = crtc->dev;
4891 struct drm_i915_private *dev_priv = dev->dev_private;
4892 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4893 struct intel_encoder *encoder;
4894 int pipe = intel_crtc->pipe;
4895
4896 if (!intel_crtc->active)
4897 return;
4898
4899 /*
4900 * Gen2 reports pipe underruns whenever all planes are disabled.
4901 * So diasble underrun reporting before all the planes get disabled.
4902 * FIXME: Need to fix the logic to work when we turn off all planes
4903 * but leave the pipe running.
4904 */
4905 if (IS_GEN2(dev))
4906 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4907
4908 /*
4909 * Vblank time updates from the shadow to live plane control register
4910 * are blocked if the memory self-refresh mode is active at that
4911 * moment. So to make sure the plane gets truly disabled, disable
4912 * first the self-refresh mode. The self-refresh enable bit in turn
4913 * will be checked/applied by the HW only at the next frame start
4914 * event which is after the vblank start event, so we need to have a
4915 * wait-for-vblank between disabling the plane and the pipe.
4916 */
4917 intel_set_memory_cxsr(dev_priv, false);
4918 intel_crtc_disable_planes(crtc);
4919
4920 /*
4921 * On gen2 planes are double buffered but the pipe isn't, so we must
4922 * wait for planes to fully turn off before disabling the pipe.
4923 * We also need to wait on all gmch platforms because of the
4924 * self-refresh mode constraint explained above.
4925 */
4926 intel_wait_for_vblank(dev, pipe);
4927
4928 drm_crtc_vblank_off(crtc);
4929 assert_vblank_disabled(crtc);
4930
4931 for_each_encoder_on_crtc(dev, crtc, encoder)
4932 encoder->disable(encoder);
4933
4934 intel_disable_pipe(intel_crtc);
4935
4936 i9xx_pfit_disable(intel_crtc);
4937
4938 for_each_encoder_on_crtc(dev, crtc, encoder)
4939 if (encoder->post_disable)
4940 encoder->post_disable(encoder);
4941
4942 if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
4943 if (IS_CHERRYVIEW(dev))
4944 chv_disable_pll(dev_priv, pipe);
4945 else if (IS_VALLEYVIEW(dev))
4946 vlv_disable_pll(dev_priv, pipe);
4947 else
4948 i9xx_disable_pll(intel_crtc);
4949 }
4950
4951 if (!IS_GEN2(dev))
4952 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4953
4954 intel_crtc->active = false;
4955 intel_update_watermarks(crtc);
4956
4957 mutex_lock(&dev->struct_mutex);
4958 intel_update_fbc(dev);
4959 mutex_unlock(&dev->struct_mutex);
4960 }
4961
4962 static void i9xx_crtc_off(struct drm_crtc *crtc)
4963 {
4964 }
4965
4966 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4967 bool enabled)
4968 {
4969 struct drm_device *dev = crtc->dev;
4970 struct drm_i915_master_private *master_priv;
4971 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4972 int pipe = intel_crtc->pipe;
4973
4974 if (!dev->primary->master)
4975 return;
4976
4977 master_priv = dev->primary->master->driver_priv;
4978 if (!master_priv->sarea_priv)
4979 return;
4980
4981 switch (pipe) {
4982 case 0:
4983 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4984 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4985 break;
4986 case 1:
4987 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4988 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4989 break;
4990 default:
4991 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4992 break;
4993 }
4994 }
4995
4996 /* Master function to enable/disable CRTC and corresponding power wells */
4997 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
4998 {
4999 struct drm_device *dev = crtc->dev;
5000 struct drm_i915_private *dev_priv = dev->dev_private;
5001 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5002 enum intel_display_power_domain domain;
5003 unsigned long domains;
5004
5005 if (enable) {
5006 if (!intel_crtc->active) {
5007 domains = get_crtc_power_domains(crtc);
5008 for_each_power_domain(domain, domains)
5009 intel_display_power_get(dev_priv, domain);
5010 intel_crtc->enabled_power_domains = domains;
5011
5012 dev_priv->display.crtc_enable(crtc);
5013 }
5014 } else {
5015 if (intel_crtc->active) {
5016 dev_priv->display.crtc_disable(crtc);
5017
5018 domains = intel_crtc->enabled_power_domains;
5019 for_each_power_domain(domain, domains)
5020 intel_display_power_put(dev_priv, domain);
5021 intel_crtc->enabled_power_domains = 0;
5022 }
5023 }
5024 }
5025
5026 /**
5027 * Sets the power management mode of the pipe and plane.
5028 */
5029 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5030 {
5031 struct drm_device *dev = crtc->dev;
5032 struct intel_encoder *intel_encoder;
5033 bool enable = false;
5034
5035 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5036 enable |= intel_encoder->connectors_active;
5037
5038 intel_crtc_control(crtc, enable);
5039
5040 intel_crtc_update_sarea(crtc, enable);
5041 }
5042
5043 static void intel_crtc_disable(struct drm_crtc *crtc)
5044 {
5045 struct drm_device *dev = crtc->dev;
5046 struct drm_connector *connector;
5047 struct drm_i915_private *dev_priv = dev->dev_private;
5048 struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
5049 enum pipe pipe = to_intel_crtc(crtc)->pipe;
5050
5051 /* crtc should still be enabled when we disable it. */
5052 WARN_ON(!crtc->enabled);
5053
5054 dev_priv->display.crtc_disable(crtc);
5055 intel_crtc_update_sarea(crtc, false);
5056 dev_priv->display.off(crtc);
5057
5058 if (crtc->primary->fb) {
5059 mutex_lock(&dev->struct_mutex);
5060 intel_unpin_fb_obj(old_obj);
5061 i915_gem_track_fb(old_obj, NULL,
5062 INTEL_FRONTBUFFER_PRIMARY(pipe));
5063 mutex_unlock(&dev->struct_mutex);
5064 crtc->primary->fb = NULL;
5065 }
5066
5067 /* Update computed state. */
5068 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5069 if (!connector->encoder || !connector->encoder->crtc)
5070 continue;
5071
5072 if (connector->encoder->crtc != crtc)
5073 continue;
5074
5075 connector->dpms = DRM_MODE_DPMS_OFF;
5076 to_intel_encoder(connector->encoder)->connectors_active = false;
5077 }
5078 }
5079
5080 void intel_encoder_destroy(struct drm_encoder *encoder)
5081 {
5082 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5083
5084 drm_encoder_cleanup(encoder);
5085 kfree(intel_encoder);
5086 }
5087
5088 /* Simple dpms helper for encoders with just one connector, no cloning and only
5089 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5090 * state of the entire output pipe. */
5091 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5092 {
5093 if (mode == DRM_MODE_DPMS_ON) {
5094 encoder->connectors_active = true;
5095
5096 intel_crtc_update_dpms(encoder->base.crtc);
5097 } else {
5098 encoder->connectors_active = false;
5099
5100 intel_crtc_update_dpms(encoder->base.crtc);
5101 }
5102 }
5103
5104 /* Cross check the actual hw state with our own modeset state tracking (and it's
5105 * internal consistency). */
5106 static void intel_connector_check_state(struct intel_connector *connector)
5107 {
5108 if (connector->get_hw_state(connector)) {
5109 struct intel_encoder *encoder = connector->encoder;
5110 struct drm_crtc *crtc;
5111 bool encoder_enabled;
5112 enum pipe pipe;
5113
5114 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5115 connector->base.base.id,
5116 connector->base.name);
5117
5118 /* there is no real hw state for MST connectors */
5119 if (connector->mst_port)
5120 return;
5121
5122 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5123 "wrong connector dpms state\n");
5124 WARN(connector->base.encoder != &encoder->base,
5125 "active connector not linked to encoder\n");
5126
5127 if (encoder) {
5128 WARN(!encoder->connectors_active,
5129 "encoder->connectors_active not set\n");
5130
5131 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5132 WARN(!encoder_enabled, "encoder not enabled\n");
5133 if (WARN_ON(!encoder->base.crtc))
5134 return;
5135
5136 crtc = encoder->base.crtc;
5137
5138 WARN(!crtc->enabled, "crtc not enabled\n");
5139 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5140 WARN(pipe != to_intel_crtc(crtc)->pipe,
5141 "encoder active on the wrong pipe\n");
5142 }
5143 }
5144 }
5145
5146 /* Even simpler default implementation, if there's really no special case to
5147 * consider. */
5148 void intel_connector_dpms(struct drm_connector *connector, int mode)
5149 {
5150 /* All the simple cases only support two dpms states. */
5151 if (mode != DRM_MODE_DPMS_ON)
5152 mode = DRM_MODE_DPMS_OFF;
5153
5154 if (mode == connector->dpms)
5155 return;
5156
5157 connector->dpms = mode;
5158
5159 /* Only need to change hw state when actually enabled */
5160 if (connector->encoder)
5161 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5162
5163 intel_modeset_check_state(connector->dev);
5164 }
5165
5166 /* Simple connector->get_hw_state implementation for encoders that support only
5167 * one connector and no cloning and hence the encoder state determines the state
5168 * of the connector. */
5169 bool intel_connector_get_hw_state(struct intel_connector *connector)
5170 {
5171 enum pipe pipe = 0;
5172 struct intel_encoder *encoder = connector->encoder;
5173
5174 return encoder->get_hw_state(encoder, &pipe);
5175 }
5176
5177 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5178 struct intel_crtc_config *pipe_config)
5179 {
5180 struct drm_i915_private *dev_priv = dev->dev_private;
5181 struct intel_crtc *pipe_B_crtc =
5182 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5183
5184 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5185 pipe_name(pipe), pipe_config->fdi_lanes);
5186 if (pipe_config->fdi_lanes > 4) {
5187 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5188 pipe_name(pipe), pipe_config->fdi_lanes);
5189 return false;
5190 }
5191
5192 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5193 if (pipe_config->fdi_lanes > 2) {
5194 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5195 pipe_config->fdi_lanes);
5196 return false;
5197 } else {
5198 return true;
5199 }
5200 }
5201
5202 if (INTEL_INFO(dev)->num_pipes == 2)
5203 return true;
5204
5205 /* Ivybridge 3 pipe is really complicated */
5206 switch (pipe) {
5207 case PIPE_A:
5208 return true;
5209 case PIPE_B:
5210 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5211 pipe_config->fdi_lanes > 2) {
5212 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5213 pipe_name(pipe), pipe_config->fdi_lanes);
5214 return false;
5215 }
5216 return true;
5217 case PIPE_C:
5218 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5219 pipe_B_crtc->config.fdi_lanes <= 2) {
5220 if (pipe_config->fdi_lanes > 2) {
5221 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5222 pipe_name(pipe), pipe_config->fdi_lanes);
5223 return false;
5224 }
5225 } else {
5226 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5227 return false;
5228 }
5229 return true;
5230 default:
5231 BUG();
5232 }
5233 }
5234
5235 #define RETRY 1
5236 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5237 struct intel_crtc_config *pipe_config)
5238 {
5239 struct drm_device *dev = intel_crtc->base.dev;
5240 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5241 int lane, link_bw, fdi_dotclock;
5242 bool setup_ok, needs_recompute = false;
5243
5244 retry:
5245 /* FDI is a binary signal running at ~2.7GHz, encoding
5246 * each output octet as 10 bits. The actual frequency
5247 * is stored as a divider into a 100MHz clock, and the
5248 * mode pixel clock is stored in units of 1KHz.
5249 * Hence the bw of each lane in terms of the mode signal
5250 * is:
5251 */
5252 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5253
5254 fdi_dotclock = adjusted_mode->crtc_clock;
5255
5256 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5257 pipe_config->pipe_bpp);
5258
5259 pipe_config->fdi_lanes = lane;
5260
5261 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5262 link_bw, &pipe_config->fdi_m_n);
5263
5264 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5265 intel_crtc->pipe, pipe_config);
5266 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5267 pipe_config->pipe_bpp -= 2*3;
5268 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5269 pipe_config->pipe_bpp);
5270 needs_recompute = true;
5271 pipe_config->bw_constrained = true;
5272
5273 goto retry;
5274 }
5275
5276 if (needs_recompute)
5277 return RETRY;
5278
5279 return setup_ok ? 0 : -EINVAL;
5280 }
5281
5282 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5283 struct intel_crtc_config *pipe_config)
5284 {
5285 pipe_config->ips_enabled = i915.enable_ips &&
5286 hsw_crtc_supports_ips(crtc) &&
5287 pipe_config->pipe_bpp <= 24;
5288 }
5289
5290 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5291 struct intel_crtc_config *pipe_config)
5292 {
5293 struct drm_device *dev = crtc->base.dev;
5294 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5295
5296 /* FIXME should check pixel clock limits on all platforms */
5297 if (INTEL_INFO(dev)->gen < 4) {
5298 struct drm_i915_private *dev_priv = dev->dev_private;
5299 int clock_limit =
5300 dev_priv->display.get_display_clock_speed(dev);
5301
5302 /*
5303 * Enable pixel doubling when the dot clock
5304 * is > 90% of the (display) core speed.
5305 *
5306 * GDG double wide on either pipe,
5307 * otherwise pipe A only.
5308 */
5309 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5310 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5311 clock_limit *= 2;
5312 pipe_config->double_wide = true;
5313 }
5314
5315 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5316 return -EINVAL;
5317 }
5318
5319 /*
5320 * Pipe horizontal size must be even in:
5321 * - DVO ganged mode
5322 * - LVDS dual channel mode
5323 * - Double wide pipe
5324 */
5325 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5326 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5327 pipe_config->pipe_src_w &= ~1;
5328
5329 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5330 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5331 */
5332 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5333 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5334 return -EINVAL;
5335
5336 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5337 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5338 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5339 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5340 * for lvds. */
5341 pipe_config->pipe_bpp = 8*3;
5342 }
5343
5344 if (HAS_IPS(dev))
5345 hsw_compute_ips_config(crtc, pipe_config);
5346
5347 /*
5348 * XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the
5349 * old clock survives for now.
5350 */
5351 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev) || HAS_DDI(dev))
5352 pipe_config->shared_dpll = crtc->config.shared_dpll;
5353
5354 if (pipe_config->has_pch_encoder)
5355 return ironlake_fdi_compute_config(crtc, pipe_config);
5356
5357 return 0;
5358 }
5359
5360 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5361 {
5362 struct drm_i915_private *dev_priv = dev->dev_private;
5363 int vco = valleyview_get_vco(dev_priv);
5364 u32 val;
5365 int divider;
5366
5367 /* FIXME: Punit isn't quite ready yet */
5368 if (IS_CHERRYVIEW(dev))
5369 return 400000;
5370
5371 mutex_lock(&dev_priv->dpio_lock);
5372 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5373 mutex_unlock(&dev_priv->dpio_lock);
5374
5375 divider = val & DISPLAY_FREQUENCY_VALUES;
5376
5377 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5378 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5379 "cdclk change in progress\n");
5380
5381 return DIV_ROUND_CLOSEST(vco << 1, divider + 1);
5382 }
5383
5384 static int i945_get_display_clock_speed(struct drm_device *dev)
5385 {
5386 return 400000;
5387 }
5388
5389 static int i915_get_display_clock_speed(struct drm_device *dev)
5390 {
5391 return 333000;
5392 }
5393
5394 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5395 {
5396 return 200000;
5397 }
5398
5399 static int pnv_get_display_clock_speed(struct drm_device *dev)
5400 {
5401 u16 gcfgc = 0;
5402
5403 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5404
5405 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5406 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5407 return 267000;
5408 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5409 return 333000;
5410 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5411 return 444000;
5412 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5413 return 200000;
5414 default:
5415 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5416 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5417 return 133000;
5418 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5419 return 167000;
5420 }
5421 }
5422
5423 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5424 {
5425 u16 gcfgc = 0;
5426
5427 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5428
5429 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5430 return 133000;
5431 else {
5432 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5433 case GC_DISPLAY_CLOCK_333_MHZ:
5434 return 333000;
5435 default:
5436 case GC_DISPLAY_CLOCK_190_200_MHZ:
5437 return 190000;
5438 }
5439 }
5440 }
5441
5442 static int i865_get_display_clock_speed(struct drm_device *dev)
5443 {
5444 return 266000;
5445 }
5446
5447 static int i855_get_display_clock_speed(struct drm_device *dev)
5448 {
5449 u16 hpllcc = 0;
5450 /* Assume that the hardware is in the high speed state. This
5451 * should be the default.
5452 */
5453 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5454 case GC_CLOCK_133_200:
5455 case GC_CLOCK_100_200:
5456 return 200000;
5457 case GC_CLOCK_166_250:
5458 return 250000;
5459 case GC_CLOCK_100_133:
5460 return 133000;
5461 }
5462
5463 /* Shouldn't happen */
5464 return 0;
5465 }
5466
5467 static int i830_get_display_clock_speed(struct drm_device *dev)
5468 {
5469 return 133000;
5470 }
5471
5472 static void
5473 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5474 {
5475 while (*num > DATA_LINK_M_N_MASK ||
5476 *den > DATA_LINK_M_N_MASK) {
5477 *num >>= 1;
5478 *den >>= 1;
5479 }
5480 }
5481
5482 static void compute_m_n(unsigned int m, unsigned int n,
5483 uint32_t *ret_m, uint32_t *ret_n)
5484 {
5485 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5486 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5487 intel_reduce_m_n_ratio(ret_m, ret_n);
5488 }
5489
5490 void
5491 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5492 int pixel_clock, int link_clock,
5493 struct intel_link_m_n *m_n)
5494 {
5495 m_n->tu = 64;
5496
5497 compute_m_n(bits_per_pixel * pixel_clock,
5498 link_clock * nlanes * 8,
5499 &m_n->gmch_m, &m_n->gmch_n);
5500
5501 compute_m_n(pixel_clock, link_clock,
5502 &m_n->link_m, &m_n->link_n);
5503 }
5504
5505 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5506 {
5507 if (i915.panel_use_ssc >= 0)
5508 return i915.panel_use_ssc != 0;
5509 return dev_priv->vbt.lvds_use_ssc
5510 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5511 }
5512
5513 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5514 {
5515 struct drm_device *dev = crtc->dev;
5516 struct drm_i915_private *dev_priv = dev->dev_private;
5517 int refclk;
5518
5519 if (IS_VALLEYVIEW(dev)) {
5520 refclk = 100000;
5521 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5522 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5523 refclk = dev_priv->vbt.lvds_ssc_freq;
5524 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5525 } else if (!IS_GEN2(dev)) {
5526 refclk = 96000;
5527 } else {
5528 refclk = 48000;
5529 }
5530
5531 return refclk;
5532 }
5533
5534 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5535 {
5536 return (1 << dpll->n) << 16 | dpll->m2;
5537 }
5538
5539 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5540 {
5541 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5542 }
5543
5544 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5545 intel_clock_t *reduced_clock)
5546 {
5547 struct drm_device *dev = crtc->base.dev;
5548 u32 fp, fp2 = 0;
5549
5550 if (IS_PINEVIEW(dev)) {
5551 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5552 if (reduced_clock)
5553 fp2 = pnv_dpll_compute_fp(reduced_clock);
5554 } else {
5555 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5556 if (reduced_clock)
5557 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5558 }
5559
5560 crtc->config.dpll_hw_state.fp0 = fp;
5561
5562 crtc->lowfreq_avail = false;
5563 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5564 reduced_clock && i915.powersave) {
5565 crtc->config.dpll_hw_state.fp1 = fp2;
5566 crtc->lowfreq_avail = true;
5567 } else {
5568 crtc->config.dpll_hw_state.fp1 = fp;
5569 }
5570 }
5571
5572 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5573 pipe)
5574 {
5575 u32 reg_val;
5576
5577 /*
5578 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5579 * and set it to a reasonable value instead.
5580 */
5581 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5582 reg_val &= 0xffffff00;
5583 reg_val |= 0x00000030;
5584 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5585
5586 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5587 reg_val &= 0x8cffffff;
5588 reg_val = 0x8c000000;
5589 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5590
5591 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5592 reg_val &= 0xffffff00;
5593 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5594
5595 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5596 reg_val &= 0x00ffffff;
5597 reg_val |= 0xb0000000;
5598 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5599 }
5600
5601 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5602 struct intel_link_m_n *m_n)
5603 {
5604 struct drm_device *dev = crtc->base.dev;
5605 struct drm_i915_private *dev_priv = dev->dev_private;
5606 int pipe = crtc->pipe;
5607
5608 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5609 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5610 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5611 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5612 }
5613
5614 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5615 struct intel_link_m_n *m_n,
5616 struct intel_link_m_n *m2_n2)
5617 {
5618 struct drm_device *dev = crtc->base.dev;
5619 struct drm_i915_private *dev_priv = dev->dev_private;
5620 int pipe = crtc->pipe;
5621 enum transcoder transcoder = crtc->config.cpu_transcoder;
5622
5623 if (INTEL_INFO(dev)->gen >= 5) {
5624 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5625 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5626 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5627 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5628 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5629 * for gen < 8) and if DRRS is supported (to make sure the
5630 * registers are not unnecessarily accessed).
5631 */
5632 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5633 crtc->config.has_drrs) {
5634 I915_WRITE(PIPE_DATA_M2(transcoder),
5635 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5636 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5637 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5638 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5639 }
5640 } else {
5641 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5642 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5643 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5644 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5645 }
5646 }
5647
5648 void intel_dp_set_m_n(struct intel_crtc *crtc)
5649 {
5650 if (crtc->config.has_pch_encoder)
5651 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5652 else
5653 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n,
5654 &crtc->config.dp_m2_n2);
5655 }
5656
5657 static void vlv_update_pll(struct intel_crtc *crtc)
5658 {
5659 u32 dpll, dpll_md;
5660
5661 /*
5662 * Enable DPIO clock input. We should never disable the reference
5663 * clock for pipe B, since VGA hotplug / manual detection depends
5664 * on it.
5665 */
5666 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5667 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5668 /* We should never disable this, set it here for state tracking */
5669 if (crtc->pipe == PIPE_B)
5670 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5671 dpll |= DPLL_VCO_ENABLE;
5672 crtc->config.dpll_hw_state.dpll = dpll;
5673
5674 dpll_md = (crtc->config.pixel_multiplier - 1)
5675 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5676 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5677 }
5678
5679 static void vlv_prepare_pll(struct intel_crtc *crtc)
5680 {
5681 struct drm_device *dev = crtc->base.dev;
5682 struct drm_i915_private *dev_priv = dev->dev_private;
5683 int pipe = crtc->pipe;
5684 u32 mdiv;
5685 u32 bestn, bestm1, bestm2, bestp1, bestp2;
5686 u32 coreclk, reg_val;
5687
5688 mutex_lock(&dev_priv->dpio_lock);
5689
5690 bestn = crtc->config.dpll.n;
5691 bestm1 = crtc->config.dpll.m1;
5692 bestm2 = crtc->config.dpll.m2;
5693 bestp1 = crtc->config.dpll.p1;
5694 bestp2 = crtc->config.dpll.p2;
5695
5696 /* See eDP HDMI DPIO driver vbios notes doc */
5697
5698 /* PLL B needs special handling */
5699 if (pipe == PIPE_B)
5700 vlv_pllb_recal_opamp(dev_priv, pipe);
5701
5702 /* Set up Tx target for periodic Rcomp update */
5703 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5704
5705 /* Disable target IRef on PLL */
5706 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5707 reg_val &= 0x00ffffff;
5708 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5709
5710 /* Disable fast lock */
5711 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5712
5713 /* Set idtafcrecal before PLL is enabled */
5714 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5715 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5716 mdiv |= ((bestn << DPIO_N_SHIFT));
5717 mdiv |= (1 << DPIO_K_SHIFT);
5718
5719 /*
5720 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5721 * but we don't support that).
5722 * Note: don't use the DAC post divider as it seems unstable.
5723 */
5724 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5725 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5726
5727 mdiv |= DPIO_ENABLE_CALIBRATION;
5728 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5729
5730 /* Set HBR and RBR LPF coefficients */
5731 if (crtc->config.port_clock == 162000 ||
5732 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5733 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5734 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5735 0x009f0003);
5736 else
5737 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5738 0x00d0000f);
5739
5740 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5741 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5742 /* Use SSC source */
5743 if (pipe == PIPE_A)
5744 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5745 0x0df40000);
5746 else
5747 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5748 0x0df70000);
5749 } else { /* HDMI or VGA */
5750 /* Use bend source */
5751 if (pipe == PIPE_A)
5752 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5753 0x0df70000);
5754 else
5755 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5756 0x0df40000);
5757 }
5758
5759 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5760 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5761 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5762 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5763 coreclk |= 0x01000000;
5764 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5765
5766 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5767 mutex_unlock(&dev_priv->dpio_lock);
5768 }
5769
5770 static void chv_update_pll(struct intel_crtc *crtc)
5771 {
5772 crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5773 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5774 DPLL_VCO_ENABLE;
5775 if (crtc->pipe != PIPE_A)
5776 crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5777
5778 crtc->config.dpll_hw_state.dpll_md =
5779 (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5780 }
5781
5782 static void chv_prepare_pll(struct intel_crtc *crtc)
5783 {
5784 struct drm_device *dev = crtc->base.dev;
5785 struct drm_i915_private *dev_priv = dev->dev_private;
5786 int pipe = crtc->pipe;
5787 int dpll_reg = DPLL(crtc->pipe);
5788 enum dpio_channel port = vlv_pipe_to_channel(pipe);
5789 u32 loopfilter, intcoeff;
5790 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5791 int refclk;
5792
5793 bestn = crtc->config.dpll.n;
5794 bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5795 bestm1 = crtc->config.dpll.m1;
5796 bestm2 = crtc->config.dpll.m2 >> 22;
5797 bestp1 = crtc->config.dpll.p1;
5798 bestp2 = crtc->config.dpll.p2;
5799
5800 /*
5801 * Enable Refclk and SSC
5802 */
5803 I915_WRITE(dpll_reg,
5804 crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5805
5806 mutex_lock(&dev_priv->dpio_lock);
5807
5808 /* p1 and p2 divider */
5809 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5810 5 << DPIO_CHV_S1_DIV_SHIFT |
5811 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5812 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5813 1 << DPIO_CHV_K_DIV_SHIFT);
5814
5815 /* Feedback post-divider - m2 */
5816 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5817
5818 /* Feedback refclk divider - n and m1 */
5819 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5820 DPIO_CHV_M1_DIV_BY_2 |
5821 1 << DPIO_CHV_N_DIV_SHIFT);
5822
5823 /* M2 fraction division */
5824 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5825
5826 /* M2 fraction division enable */
5827 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5828 DPIO_CHV_FRAC_DIV_EN |
5829 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5830
5831 /* Loop filter */
5832 refclk = i9xx_get_refclk(&crtc->base, 0);
5833 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5834 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5835 if (refclk == 100000)
5836 intcoeff = 11;
5837 else if (refclk == 38400)
5838 intcoeff = 10;
5839 else
5840 intcoeff = 9;
5841 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5842 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5843
5844 /* AFC Recal */
5845 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5846 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5847 DPIO_AFC_RECAL);
5848
5849 mutex_unlock(&dev_priv->dpio_lock);
5850 }
5851
5852 static void i9xx_update_pll(struct intel_crtc *crtc,
5853 intel_clock_t *reduced_clock,
5854 int num_connectors)
5855 {
5856 struct drm_device *dev = crtc->base.dev;
5857 struct drm_i915_private *dev_priv = dev->dev_private;
5858 u32 dpll;
5859 bool is_sdvo;
5860 struct dpll *clock = &crtc->config.dpll;
5861
5862 i9xx_update_pll_dividers(crtc, reduced_clock);
5863
5864 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5865 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5866
5867 dpll = DPLL_VGA_MODE_DIS;
5868
5869 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5870 dpll |= DPLLB_MODE_LVDS;
5871 else
5872 dpll |= DPLLB_MODE_DAC_SERIAL;
5873
5874 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5875 dpll |= (crtc->config.pixel_multiplier - 1)
5876 << SDVO_MULTIPLIER_SHIFT_HIRES;
5877 }
5878
5879 if (is_sdvo)
5880 dpll |= DPLL_SDVO_HIGH_SPEED;
5881
5882 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5883 dpll |= DPLL_SDVO_HIGH_SPEED;
5884
5885 /* compute bitmask from p1 value */
5886 if (IS_PINEVIEW(dev))
5887 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5888 else {
5889 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5890 if (IS_G4X(dev) && reduced_clock)
5891 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5892 }
5893 switch (clock->p2) {
5894 case 5:
5895 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5896 break;
5897 case 7:
5898 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5899 break;
5900 case 10:
5901 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5902 break;
5903 case 14:
5904 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5905 break;
5906 }
5907 if (INTEL_INFO(dev)->gen >= 4)
5908 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5909
5910 if (crtc->config.sdvo_tv_clock)
5911 dpll |= PLL_REF_INPUT_TVCLKINBC;
5912 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5913 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5914 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5915 else
5916 dpll |= PLL_REF_INPUT_DREFCLK;
5917
5918 dpll |= DPLL_VCO_ENABLE;
5919 crtc->config.dpll_hw_state.dpll = dpll;
5920
5921 if (INTEL_INFO(dev)->gen >= 4) {
5922 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5923 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5924 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5925 }
5926 }
5927
5928 static void i8xx_update_pll(struct intel_crtc *crtc,
5929 intel_clock_t *reduced_clock,
5930 int num_connectors)
5931 {
5932 struct drm_device *dev = crtc->base.dev;
5933 struct drm_i915_private *dev_priv = dev->dev_private;
5934 u32 dpll;
5935 struct dpll *clock = &crtc->config.dpll;
5936
5937 i9xx_update_pll_dividers(crtc, reduced_clock);
5938
5939 dpll = DPLL_VGA_MODE_DIS;
5940
5941 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5942 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5943 } else {
5944 if (clock->p1 == 2)
5945 dpll |= PLL_P1_DIVIDE_BY_TWO;
5946 else
5947 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5948 if (clock->p2 == 4)
5949 dpll |= PLL_P2_DIVIDE_BY_4;
5950 }
5951
5952 if (!IS_I830(dev) && intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5953 dpll |= DPLL_DVO_2X_MODE;
5954
5955 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5956 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5957 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5958 else
5959 dpll |= PLL_REF_INPUT_DREFCLK;
5960
5961 dpll |= DPLL_VCO_ENABLE;
5962 crtc->config.dpll_hw_state.dpll = dpll;
5963 }
5964
5965 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5966 {
5967 struct drm_device *dev = intel_crtc->base.dev;
5968 struct drm_i915_private *dev_priv = dev->dev_private;
5969 enum pipe pipe = intel_crtc->pipe;
5970 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5971 struct drm_display_mode *adjusted_mode =
5972 &intel_crtc->config.adjusted_mode;
5973 uint32_t crtc_vtotal, crtc_vblank_end;
5974 int vsyncshift = 0;
5975
5976 /* We need to be careful not to changed the adjusted mode, for otherwise
5977 * the hw state checker will get angry at the mismatch. */
5978 crtc_vtotal = adjusted_mode->crtc_vtotal;
5979 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5980
5981 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5982 /* the chip adds 2 halflines automatically */
5983 crtc_vtotal -= 1;
5984 crtc_vblank_end -= 1;
5985
5986 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5987 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5988 else
5989 vsyncshift = adjusted_mode->crtc_hsync_start -
5990 adjusted_mode->crtc_htotal / 2;
5991 if (vsyncshift < 0)
5992 vsyncshift += adjusted_mode->crtc_htotal;
5993 }
5994
5995 if (INTEL_INFO(dev)->gen > 3)
5996 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5997
5998 I915_WRITE(HTOTAL(cpu_transcoder),
5999 (adjusted_mode->crtc_hdisplay - 1) |
6000 ((adjusted_mode->crtc_htotal - 1) << 16));
6001 I915_WRITE(HBLANK(cpu_transcoder),
6002 (adjusted_mode->crtc_hblank_start - 1) |
6003 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6004 I915_WRITE(HSYNC(cpu_transcoder),
6005 (adjusted_mode->crtc_hsync_start - 1) |
6006 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6007
6008 I915_WRITE(VTOTAL(cpu_transcoder),
6009 (adjusted_mode->crtc_vdisplay - 1) |
6010 ((crtc_vtotal - 1) << 16));
6011 I915_WRITE(VBLANK(cpu_transcoder),
6012 (adjusted_mode->crtc_vblank_start - 1) |
6013 ((crtc_vblank_end - 1) << 16));
6014 I915_WRITE(VSYNC(cpu_transcoder),
6015 (adjusted_mode->crtc_vsync_start - 1) |
6016 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6017
6018 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6019 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6020 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6021 * bits. */
6022 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6023 (pipe == PIPE_B || pipe == PIPE_C))
6024 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6025
6026 /* pipesrc controls the size that is scaled from, which should
6027 * always be the user's requested size.
6028 */
6029 I915_WRITE(PIPESRC(pipe),
6030 ((intel_crtc->config.pipe_src_w - 1) << 16) |
6031 (intel_crtc->config.pipe_src_h - 1));
6032 }
6033
6034 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6035 struct intel_crtc_config *pipe_config)
6036 {
6037 struct drm_device *dev = crtc->base.dev;
6038 struct drm_i915_private *dev_priv = dev->dev_private;
6039 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6040 uint32_t tmp;
6041
6042 tmp = I915_READ(HTOTAL(cpu_transcoder));
6043 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6044 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6045 tmp = I915_READ(HBLANK(cpu_transcoder));
6046 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6047 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6048 tmp = I915_READ(HSYNC(cpu_transcoder));
6049 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6050 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6051
6052 tmp = I915_READ(VTOTAL(cpu_transcoder));
6053 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6054 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6055 tmp = I915_READ(VBLANK(cpu_transcoder));
6056 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6057 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6058 tmp = I915_READ(VSYNC(cpu_transcoder));
6059 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6060 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6061
6062 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6063 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6064 pipe_config->adjusted_mode.crtc_vtotal += 1;
6065 pipe_config->adjusted_mode.crtc_vblank_end += 1;
6066 }
6067
6068 tmp = I915_READ(PIPESRC(crtc->pipe));
6069 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6070 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6071
6072 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
6073 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
6074 }
6075
6076 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6077 struct intel_crtc_config *pipe_config)
6078 {
6079 mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
6080 mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
6081 mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
6082 mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
6083
6084 mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
6085 mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
6086 mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
6087 mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
6088
6089 mode->flags = pipe_config->adjusted_mode.flags;
6090
6091 mode->clock = pipe_config->adjusted_mode.crtc_clock;
6092 mode->flags |= pipe_config->adjusted_mode.flags;
6093 }
6094
6095 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6096 {
6097 struct drm_device *dev = intel_crtc->base.dev;
6098 struct drm_i915_private *dev_priv = dev->dev_private;
6099 uint32_t pipeconf;
6100
6101 pipeconf = 0;
6102
6103 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6104 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6105 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6106
6107 if (intel_crtc->config.double_wide)
6108 pipeconf |= PIPECONF_DOUBLE_WIDE;
6109
6110 /* only g4x and later have fancy bpc/dither controls */
6111 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6112 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6113 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
6114 pipeconf |= PIPECONF_DITHER_EN |
6115 PIPECONF_DITHER_TYPE_SP;
6116
6117 switch (intel_crtc->config.pipe_bpp) {
6118 case 18:
6119 pipeconf |= PIPECONF_6BPC;
6120 break;
6121 case 24:
6122 pipeconf |= PIPECONF_8BPC;
6123 break;
6124 case 30:
6125 pipeconf |= PIPECONF_10BPC;
6126 break;
6127 default:
6128 /* Case prevented by intel_choose_pipe_bpp_dither. */
6129 BUG();
6130 }
6131 }
6132
6133 if (HAS_PIPE_CXSR(dev)) {
6134 if (intel_crtc->lowfreq_avail) {
6135 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6136 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6137 } else {
6138 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6139 }
6140 }
6141
6142 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6143 if (INTEL_INFO(dev)->gen < 4 ||
6144 intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
6145 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6146 else
6147 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6148 } else
6149 pipeconf |= PIPECONF_PROGRESSIVE;
6150
6151 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6152 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6153
6154 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6155 POSTING_READ(PIPECONF(intel_crtc->pipe));
6156 }
6157
6158 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
6159 int x, int y,
6160 struct drm_framebuffer *fb)
6161 {
6162 struct drm_device *dev = crtc->dev;
6163 struct drm_i915_private *dev_priv = dev->dev_private;
6164 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6165 int refclk, num_connectors = 0;
6166 intel_clock_t clock, reduced_clock;
6167 bool ok, has_reduced_clock = false;
6168 bool is_lvds = false, is_dsi = false;
6169 struct intel_encoder *encoder;
6170 const intel_limit_t *limit;
6171
6172 for_each_encoder_on_crtc(dev, crtc, encoder) {
6173 switch (encoder->type) {
6174 case INTEL_OUTPUT_LVDS:
6175 is_lvds = true;
6176 break;
6177 case INTEL_OUTPUT_DSI:
6178 is_dsi = true;
6179 break;
6180 }
6181
6182 num_connectors++;
6183 }
6184
6185 if (is_dsi)
6186 return 0;
6187
6188 if (!intel_crtc->config.clock_set) {
6189 refclk = i9xx_get_refclk(crtc, num_connectors);
6190
6191 /*
6192 * Returns a set of divisors for the desired target clock with
6193 * the given refclk, or FALSE. The returned values represent
6194 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6195 * 2) / p1 / p2.
6196 */
6197 limit = intel_limit(crtc, refclk);
6198 ok = dev_priv->display.find_dpll(limit, crtc,
6199 intel_crtc->config.port_clock,
6200 refclk, NULL, &clock);
6201 if (!ok) {
6202 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6203 return -EINVAL;
6204 }
6205
6206 if (is_lvds && dev_priv->lvds_downclock_avail) {
6207 /*
6208 * Ensure we match the reduced clock's P to the target
6209 * clock. If the clocks don't match, we can't switch
6210 * the display clock by using the FP0/FP1. In such case
6211 * we will disable the LVDS downclock feature.
6212 */
6213 has_reduced_clock =
6214 dev_priv->display.find_dpll(limit, crtc,
6215 dev_priv->lvds_downclock,
6216 refclk, &clock,
6217 &reduced_clock);
6218 }
6219 /* Compat-code for transition, will disappear. */
6220 intel_crtc->config.dpll.n = clock.n;
6221 intel_crtc->config.dpll.m1 = clock.m1;
6222 intel_crtc->config.dpll.m2 = clock.m2;
6223 intel_crtc->config.dpll.p1 = clock.p1;
6224 intel_crtc->config.dpll.p2 = clock.p2;
6225 }
6226
6227 if (IS_GEN2(dev)) {
6228 i8xx_update_pll(intel_crtc,
6229 has_reduced_clock ? &reduced_clock : NULL,
6230 num_connectors);
6231 } else if (IS_CHERRYVIEW(dev)) {
6232 chv_update_pll(intel_crtc);
6233 } else if (IS_VALLEYVIEW(dev)) {
6234 vlv_update_pll(intel_crtc);
6235 } else {
6236 i9xx_update_pll(intel_crtc,
6237 has_reduced_clock ? &reduced_clock : NULL,
6238 num_connectors);
6239 }
6240
6241 return 0;
6242 }
6243
6244 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6245 struct intel_crtc_config *pipe_config)
6246 {
6247 struct drm_device *dev = crtc->base.dev;
6248 struct drm_i915_private *dev_priv = dev->dev_private;
6249 uint32_t tmp;
6250
6251 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6252 return;
6253
6254 tmp = I915_READ(PFIT_CONTROL);
6255 if (!(tmp & PFIT_ENABLE))
6256 return;
6257
6258 /* Check whether the pfit is attached to our pipe. */
6259 if (INTEL_INFO(dev)->gen < 4) {
6260 if (crtc->pipe != PIPE_B)
6261 return;
6262 } else {
6263 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6264 return;
6265 }
6266
6267 pipe_config->gmch_pfit.control = tmp;
6268 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6269 if (INTEL_INFO(dev)->gen < 5)
6270 pipe_config->gmch_pfit.lvds_border_bits =
6271 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6272 }
6273
6274 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6275 struct intel_crtc_config *pipe_config)
6276 {
6277 struct drm_device *dev = crtc->base.dev;
6278 struct drm_i915_private *dev_priv = dev->dev_private;
6279 int pipe = pipe_config->cpu_transcoder;
6280 intel_clock_t clock;
6281 u32 mdiv;
6282 int refclk = 100000;
6283
6284 /* In case of MIPI DPLL will not even be used */
6285 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6286 return;
6287
6288 mutex_lock(&dev_priv->dpio_lock);
6289 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6290 mutex_unlock(&dev_priv->dpio_lock);
6291
6292 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6293 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6294 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6295 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6296 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6297
6298 vlv_clock(refclk, &clock);
6299
6300 /* clock.dot is the fast clock */
6301 pipe_config->port_clock = clock.dot / 5;
6302 }
6303
6304 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6305 struct intel_plane_config *plane_config)
6306 {
6307 struct drm_device *dev = crtc->base.dev;
6308 struct drm_i915_private *dev_priv = dev->dev_private;
6309 u32 val, base, offset;
6310 int pipe = crtc->pipe, plane = crtc->plane;
6311 int fourcc, pixel_format;
6312 int aligned_height;
6313
6314 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6315 if (!crtc->base.primary->fb) {
6316 DRM_DEBUG_KMS("failed to alloc fb\n");
6317 return;
6318 }
6319
6320 val = I915_READ(DSPCNTR(plane));
6321
6322 if (INTEL_INFO(dev)->gen >= 4)
6323 if (val & DISPPLANE_TILED)
6324 plane_config->tiled = true;
6325
6326 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6327 fourcc = intel_format_to_fourcc(pixel_format);
6328 crtc->base.primary->fb->pixel_format = fourcc;
6329 crtc->base.primary->fb->bits_per_pixel =
6330 drm_format_plane_cpp(fourcc, 0) * 8;
6331
6332 if (INTEL_INFO(dev)->gen >= 4) {
6333 if (plane_config->tiled)
6334 offset = I915_READ(DSPTILEOFF(plane));
6335 else
6336 offset = I915_READ(DSPLINOFF(plane));
6337 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6338 } else {
6339 base = I915_READ(DSPADDR(plane));
6340 }
6341 plane_config->base = base;
6342
6343 val = I915_READ(PIPESRC(pipe));
6344 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6345 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6346
6347 val = I915_READ(DSPSTRIDE(pipe));
6348 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
6349
6350 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6351 plane_config->tiled);
6352
6353 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6354 aligned_height);
6355
6356 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6357 pipe, plane, crtc->base.primary->fb->width,
6358 crtc->base.primary->fb->height,
6359 crtc->base.primary->fb->bits_per_pixel, base,
6360 crtc->base.primary->fb->pitches[0],
6361 plane_config->size);
6362
6363 }
6364
6365 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6366 struct intel_crtc_config *pipe_config)
6367 {
6368 struct drm_device *dev = crtc->base.dev;
6369 struct drm_i915_private *dev_priv = dev->dev_private;
6370 int pipe = pipe_config->cpu_transcoder;
6371 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6372 intel_clock_t clock;
6373 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6374 int refclk = 100000;
6375
6376 mutex_lock(&dev_priv->dpio_lock);
6377 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6378 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6379 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6380 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6381 mutex_unlock(&dev_priv->dpio_lock);
6382
6383 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6384 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6385 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6386 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6387 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6388
6389 chv_clock(refclk, &clock);
6390
6391 /* clock.dot is the fast clock */
6392 pipe_config->port_clock = clock.dot / 5;
6393 }
6394
6395 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6396 struct intel_crtc_config *pipe_config)
6397 {
6398 struct drm_device *dev = crtc->base.dev;
6399 struct drm_i915_private *dev_priv = dev->dev_private;
6400 uint32_t tmp;
6401
6402 if (!intel_display_power_enabled(dev_priv,
6403 POWER_DOMAIN_PIPE(crtc->pipe)))
6404 return false;
6405
6406 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6407 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6408
6409 tmp = I915_READ(PIPECONF(crtc->pipe));
6410 if (!(tmp & PIPECONF_ENABLE))
6411 return false;
6412
6413 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6414 switch (tmp & PIPECONF_BPC_MASK) {
6415 case PIPECONF_6BPC:
6416 pipe_config->pipe_bpp = 18;
6417 break;
6418 case PIPECONF_8BPC:
6419 pipe_config->pipe_bpp = 24;
6420 break;
6421 case PIPECONF_10BPC:
6422 pipe_config->pipe_bpp = 30;
6423 break;
6424 default:
6425 break;
6426 }
6427 }
6428
6429 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6430 pipe_config->limited_color_range = true;
6431
6432 if (INTEL_INFO(dev)->gen < 4)
6433 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6434
6435 intel_get_pipe_timings(crtc, pipe_config);
6436
6437 i9xx_get_pfit_config(crtc, pipe_config);
6438
6439 if (INTEL_INFO(dev)->gen >= 4) {
6440 tmp = I915_READ(DPLL_MD(crtc->pipe));
6441 pipe_config->pixel_multiplier =
6442 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6443 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6444 pipe_config->dpll_hw_state.dpll_md = tmp;
6445 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6446 tmp = I915_READ(DPLL(crtc->pipe));
6447 pipe_config->pixel_multiplier =
6448 ((tmp & SDVO_MULTIPLIER_MASK)
6449 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6450 } else {
6451 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6452 * port and will be fixed up in the encoder->get_config
6453 * function. */
6454 pipe_config->pixel_multiplier = 1;
6455 }
6456 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6457 if (!IS_VALLEYVIEW(dev)) {
6458 /*
6459 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6460 * on 830. Filter it out here so that we don't
6461 * report errors due to that.
6462 */
6463 if (IS_I830(dev))
6464 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6465
6466 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6467 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6468 } else {
6469 /* Mask out read-only status bits. */
6470 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6471 DPLL_PORTC_READY_MASK |
6472 DPLL_PORTB_READY_MASK);
6473 }
6474
6475 if (IS_CHERRYVIEW(dev))
6476 chv_crtc_clock_get(crtc, pipe_config);
6477 else if (IS_VALLEYVIEW(dev))
6478 vlv_crtc_clock_get(crtc, pipe_config);
6479 else
6480 i9xx_crtc_clock_get(crtc, pipe_config);
6481
6482 return true;
6483 }
6484
6485 static void ironlake_init_pch_refclk(struct drm_device *dev)
6486 {
6487 struct drm_i915_private *dev_priv = dev->dev_private;
6488 struct intel_encoder *encoder;
6489 u32 val, final;
6490 bool has_lvds = false;
6491 bool has_cpu_edp = false;
6492 bool has_panel = false;
6493 bool has_ck505 = false;
6494 bool can_ssc = false;
6495
6496 /* We need to take the global config into account */
6497 for_each_intel_encoder(dev, encoder) {
6498 switch (encoder->type) {
6499 case INTEL_OUTPUT_LVDS:
6500 has_panel = true;
6501 has_lvds = true;
6502 break;
6503 case INTEL_OUTPUT_EDP:
6504 has_panel = true;
6505 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6506 has_cpu_edp = true;
6507 break;
6508 }
6509 }
6510
6511 if (HAS_PCH_IBX(dev)) {
6512 has_ck505 = dev_priv->vbt.display_clock_mode;
6513 can_ssc = has_ck505;
6514 } else {
6515 has_ck505 = false;
6516 can_ssc = true;
6517 }
6518
6519 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6520 has_panel, has_lvds, has_ck505);
6521
6522 /* Ironlake: try to setup display ref clock before DPLL
6523 * enabling. This is only under driver's control after
6524 * PCH B stepping, previous chipset stepping should be
6525 * ignoring this setting.
6526 */
6527 val = I915_READ(PCH_DREF_CONTROL);
6528
6529 /* As we must carefully and slowly disable/enable each source in turn,
6530 * compute the final state we want first and check if we need to
6531 * make any changes at all.
6532 */
6533 final = val;
6534 final &= ~DREF_NONSPREAD_SOURCE_MASK;
6535 if (has_ck505)
6536 final |= DREF_NONSPREAD_CK505_ENABLE;
6537 else
6538 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6539
6540 final &= ~DREF_SSC_SOURCE_MASK;
6541 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6542 final &= ~DREF_SSC1_ENABLE;
6543
6544 if (has_panel) {
6545 final |= DREF_SSC_SOURCE_ENABLE;
6546
6547 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6548 final |= DREF_SSC1_ENABLE;
6549
6550 if (has_cpu_edp) {
6551 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6552 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6553 else
6554 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6555 } else
6556 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6557 } else {
6558 final |= DREF_SSC_SOURCE_DISABLE;
6559 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6560 }
6561
6562 if (final == val)
6563 return;
6564
6565 /* Always enable nonspread source */
6566 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6567
6568 if (has_ck505)
6569 val |= DREF_NONSPREAD_CK505_ENABLE;
6570 else
6571 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6572
6573 if (has_panel) {
6574 val &= ~DREF_SSC_SOURCE_MASK;
6575 val |= DREF_SSC_SOURCE_ENABLE;
6576
6577 /* SSC must be turned on before enabling the CPU output */
6578 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6579 DRM_DEBUG_KMS("Using SSC on panel\n");
6580 val |= DREF_SSC1_ENABLE;
6581 } else
6582 val &= ~DREF_SSC1_ENABLE;
6583
6584 /* Get SSC going before enabling the outputs */
6585 I915_WRITE(PCH_DREF_CONTROL, val);
6586 POSTING_READ(PCH_DREF_CONTROL);
6587 udelay(200);
6588
6589 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6590
6591 /* Enable CPU source on CPU attached eDP */
6592 if (has_cpu_edp) {
6593 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6594 DRM_DEBUG_KMS("Using SSC on eDP\n");
6595 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6596 } else
6597 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6598 } else
6599 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6600
6601 I915_WRITE(PCH_DREF_CONTROL, val);
6602 POSTING_READ(PCH_DREF_CONTROL);
6603 udelay(200);
6604 } else {
6605 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6606
6607 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6608
6609 /* Turn off CPU output */
6610 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6611
6612 I915_WRITE(PCH_DREF_CONTROL, val);
6613 POSTING_READ(PCH_DREF_CONTROL);
6614 udelay(200);
6615
6616 /* Turn off the SSC source */
6617 val &= ~DREF_SSC_SOURCE_MASK;
6618 val |= DREF_SSC_SOURCE_DISABLE;
6619
6620 /* Turn off SSC1 */
6621 val &= ~DREF_SSC1_ENABLE;
6622
6623 I915_WRITE(PCH_DREF_CONTROL, val);
6624 POSTING_READ(PCH_DREF_CONTROL);
6625 udelay(200);
6626 }
6627
6628 BUG_ON(val != final);
6629 }
6630
6631 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6632 {
6633 uint32_t tmp;
6634
6635 tmp = I915_READ(SOUTH_CHICKEN2);
6636 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6637 I915_WRITE(SOUTH_CHICKEN2, tmp);
6638
6639 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6640 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6641 DRM_ERROR("FDI mPHY reset assert timeout\n");
6642
6643 tmp = I915_READ(SOUTH_CHICKEN2);
6644 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6645 I915_WRITE(SOUTH_CHICKEN2, tmp);
6646
6647 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6648 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6649 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6650 }
6651
6652 /* WaMPhyProgramming:hsw */
6653 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6654 {
6655 uint32_t tmp;
6656
6657 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6658 tmp &= ~(0xFF << 24);
6659 tmp |= (0x12 << 24);
6660 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6661
6662 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6663 tmp |= (1 << 11);
6664 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6665
6666 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6667 tmp |= (1 << 11);
6668 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6669
6670 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6671 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6672 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6673
6674 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6675 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6676 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6677
6678 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6679 tmp &= ~(7 << 13);
6680 tmp |= (5 << 13);
6681 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6682
6683 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6684 tmp &= ~(7 << 13);
6685 tmp |= (5 << 13);
6686 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6687
6688 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6689 tmp &= ~0xFF;
6690 tmp |= 0x1C;
6691 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6692
6693 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6694 tmp &= ~0xFF;
6695 tmp |= 0x1C;
6696 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6697
6698 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6699 tmp &= ~(0xFF << 16);
6700 tmp |= (0x1C << 16);
6701 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6702
6703 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6704 tmp &= ~(0xFF << 16);
6705 tmp |= (0x1C << 16);
6706 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6707
6708 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6709 tmp |= (1 << 27);
6710 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6711
6712 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6713 tmp |= (1 << 27);
6714 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6715
6716 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6717 tmp &= ~(0xF << 28);
6718 tmp |= (4 << 28);
6719 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6720
6721 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6722 tmp &= ~(0xF << 28);
6723 tmp |= (4 << 28);
6724 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6725 }
6726
6727 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6728 * Programming" based on the parameters passed:
6729 * - Sequence to enable CLKOUT_DP
6730 * - Sequence to enable CLKOUT_DP without spread
6731 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6732 */
6733 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6734 bool with_fdi)
6735 {
6736 struct drm_i915_private *dev_priv = dev->dev_private;
6737 uint32_t reg, tmp;
6738
6739 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6740 with_spread = true;
6741 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6742 with_fdi, "LP PCH doesn't have FDI\n"))
6743 with_fdi = false;
6744
6745 mutex_lock(&dev_priv->dpio_lock);
6746
6747 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6748 tmp &= ~SBI_SSCCTL_DISABLE;
6749 tmp |= SBI_SSCCTL_PATHALT;
6750 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6751
6752 udelay(24);
6753
6754 if (with_spread) {
6755 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6756 tmp &= ~SBI_SSCCTL_PATHALT;
6757 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6758
6759 if (with_fdi) {
6760 lpt_reset_fdi_mphy(dev_priv);
6761 lpt_program_fdi_mphy(dev_priv);
6762 }
6763 }
6764
6765 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6766 SBI_GEN0 : SBI_DBUFF0;
6767 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6768 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6769 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6770
6771 mutex_unlock(&dev_priv->dpio_lock);
6772 }
6773
6774 /* Sequence to disable CLKOUT_DP */
6775 static void lpt_disable_clkout_dp(struct drm_device *dev)
6776 {
6777 struct drm_i915_private *dev_priv = dev->dev_private;
6778 uint32_t reg, tmp;
6779
6780 mutex_lock(&dev_priv->dpio_lock);
6781
6782 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6783 SBI_GEN0 : SBI_DBUFF0;
6784 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6785 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6786 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6787
6788 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6789 if (!(tmp & SBI_SSCCTL_DISABLE)) {
6790 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6791 tmp |= SBI_SSCCTL_PATHALT;
6792 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6793 udelay(32);
6794 }
6795 tmp |= SBI_SSCCTL_DISABLE;
6796 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6797 }
6798
6799 mutex_unlock(&dev_priv->dpio_lock);
6800 }
6801
6802 static void lpt_init_pch_refclk(struct drm_device *dev)
6803 {
6804 struct intel_encoder *encoder;
6805 bool has_vga = false;
6806
6807 for_each_intel_encoder(dev, encoder) {
6808 switch (encoder->type) {
6809 case INTEL_OUTPUT_ANALOG:
6810 has_vga = true;
6811 break;
6812 }
6813 }
6814
6815 if (has_vga)
6816 lpt_enable_clkout_dp(dev, true, true);
6817 else
6818 lpt_disable_clkout_dp(dev);
6819 }
6820
6821 /*
6822 * Initialize reference clocks when the driver loads
6823 */
6824 void intel_init_pch_refclk(struct drm_device *dev)
6825 {
6826 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6827 ironlake_init_pch_refclk(dev);
6828 else if (HAS_PCH_LPT(dev))
6829 lpt_init_pch_refclk(dev);
6830 }
6831
6832 static int ironlake_get_refclk(struct drm_crtc *crtc)
6833 {
6834 struct drm_device *dev = crtc->dev;
6835 struct drm_i915_private *dev_priv = dev->dev_private;
6836 struct intel_encoder *encoder;
6837 int num_connectors = 0;
6838 bool is_lvds = false;
6839
6840 for_each_encoder_on_crtc(dev, crtc, encoder) {
6841 switch (encoder->type) {
6842 case INTEL_OUTPUT_LVDS:
6843 is_lvds = true;
6844 break;
6845 }
6846 num_connectors++;
6847 }
6848
6849 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6850 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6851 dev_priv->vbt.lvds_ssc_freq);
6852 return dev_priv->vbt.lvds_ssc_freq;
6853 }
6854
6855 return 120000;
6856 }
6857
6858 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6859 {
6860 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6861 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6862 int pipe = intel_crtc->pipe;
6863 uint32_t val;
6864
6865 val = 0;
6866
6867 switch (intel_crtc->config.pipe_bpp) {
6868 case 18:
6869 val |= PIPECONF_6BPC;
6870 break;
6871 case 24:
6872 val |= PIPECONF_8BPC;
6873 break;
6874 case 30:
6875 val |= PIPECONF_10BPC;
6876 break;
6877 case 36:
6878 val |= PIPECONF_12BPC;
6879 break;
6880 default:
6881 /* Case prevented by intel_choose_pipe_bpp_dither. */
6882 BUG();
6883 }
6884
6885 if (intel_crtc->config.dither)
6886 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6887
6888 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6889 val |= PIPECONF_INTERLACED_ILK;
6890 else
6891 val |= PIPECONF_PROGRESSIVE;
6892
6893 if (intel_crtc->config.limited_color_range)
6894 val |= PIPECONF_COLOR_RANGE_SELECT;
6895
6896 I915_WRITE(PIPECONF(pipe), val);
6897 POSTING_READ(PIPECONF(pipe));
6898 }
6899
6900 /*
6901 * Set up the pipe CSC unit.
6902 *
6903 * Currently only full range RGB to limited range RGB conversion
6904 * is supported, but eventually this should handle various
6905 * RGB<->YCbCr scenarios as well.
6906 */
6907 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6908 {
6909 struct drm_device *dev = crtc->dev;
6910 struct drm_i915_private *dev_priv = dev->dev_private;
6911 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6912 int pipe = intel_crtc->pipe;
6913 uint16_t coeff = 0x7800; /* 1.0 */
6914
6915 /*
6916 * TODO: Check what kind of values actually come out of the pipe
6917 * with these coeff/postoff values and adjust to get the best
6918 * accuracy. Perhaps we even need to take the bpc value into
6919 * consideration.
6920 */
6921
6922 if (intel_crtc->config.limited_color_range)
6923 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6924
6925 /*
6926 * GY/GU and RY/RU should be the other way around according
6927 * to BSpec, but reality doesn't agree. Just set them up in
6928 * a way that results in the correct picture.
6929 */
6930 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6931 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6932
6933 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6934 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6935
6936 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6937 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6938
6939 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6940 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6941 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6942
6943 if (INTEL_INFO(dev)->gen > 6) {
6944 uint16_t postoff = 0;
6945
6946 if (intel_crtc->config.limited_color_range)
6947 postoff = (16 * (1 << 12) / 255) & 0x1fff;
6948
6949 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6950 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6951 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6952
6953 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6954 } else {
6955 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6956
6957 if (intel_crtc->config.limited_color_range)
6958 mode |= CSC_BLACK_SCREEN_OFFSET;
6959
6960 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6961 }
6962 }
6963
6964 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6965 {
6966 struct drm_device *dev = crtc->dev;
6967 struct drm_i915_private *dev_priv = dev->dev_private;
6968 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6969 enum pipe pipe = intel_crtc->pipe;
6970 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6971 uint32_t val;
6972
6973 val = 0;
6974
6975 if (IS_HASWELL(dev) && intel_crtc->config.dither)
6976 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6977
6978 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6979 val |= PIPECONF_INTERLACED_ILK;
6980 else
6981 val |= PIPECONF_PROGRESSIVE;
6982
6983 I915_WRITE(PIPECONF(cpu_transcoder), val);
6984 POSTING_READ(PIPECONF(cpu_transcoder));
6985
6986 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6987 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6988
6989 if (IS_BROADWELL(dev)) {
6990 val = 0;
6991
6992 switch (intel_crtc->config.pipe_bpp) {
6993 case 18:
6994 val |= PIPEMISC_DITHER_6_BPC;
6995 break;
6996 case 24:
6997 val |= PIPEMISC_DITHER_8_BPC;
6998 break;
6999 case 30:
7000 val |= PIPEMISC_DITHER_10_BPC;
7001 break;
7002 case 36:
7003 val |= PIPEMISC_DITHER_12_BPC;
7004 break;
7005 default:
7006 /* Case prevented by pipe_config_set_bpp. */
7007 BUG();
7008 }
7009
7010 if (intel_crtc->config.dither)
7011 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7012
7013 I915_WRITE(PIPEMISC(pipe), val);
7014 }
7015 }
7016
7017 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7018 intel_clock_t *clock,
7019 bool *has_reduced_clock,
7020 intel_clock_t *reduced_clock)
7021 {
7022 struct drm_device *dev = crtc->dev;
7023 struct drm_i915_private *dev_priv = dev->dev_private;
7024 struct intel_encoder *intel_encoder;
7025 int refclk;
7026 const intel_limit_t *limit;
7027 bool ret, is_lvds = false;
7028
7029 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
7030 switch (intel_encoder->type) {
7031 case INTEL_OUTPUT_LVDS:
7032 is_lvds = true;
7033 break;
7034 }
7035 }
7036
7037 refclk = ironlake_get_refclk(crtc);
7038
7039 /*
7040 * Returns a set of divisors for the desired target clock with the given
7041 * refclk, or FALSE. The returned values represent the clock equation:
7042 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7043 */
7044 limit = intel_limit(crtc, refclk);
7045 ret = dev_priv->display.find_dpll(limit, crtc,
7046 to_intel_crtc(crtc)->config.port_clock,
7047 refclk, NULL, clock);
7048 if (!ret)
7049 return false;
7050
7051 if (is_lvds && dev_priv->lvds_downclock_avail) {
7052 /*
7053 * Ensure we match the reduced clock's P to the target clock.
7054 * If the clocks don't match, we can't switch the display clock
7055 * by using the FP0/FP1. In such case we will disable the LVDS
7056 * downclock feature.
7057 */
7058 *has_reduced_clock =
7059 dev_priv->display.find_dpll(limit, crtc,
7060 dev_priv->lvds_downclock,
7061 refclk, clock,
7062 reduced_clock);
7063 }
7064
7065 return true;
7066 }
7067
7068 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7069 {
7070 /*
7071 * Account for spread spectrum to avoid
7072 * oversubscribing the link. Max center spread
7073 * is 2.5%; use 5% for safety's sake.
7074 */
7075 u32 bps = target_clock * bpp * 21 / 20;
7076 return DIV_ROUND_UP(bps, link_bw * 8);
7077 }
7078
7079 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7080 {
7081 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7082 }
7083
7084 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7085 u32 *fp,
7086 intel_clock_t *reduced_clock, u32 *fp2)
7087 {
7088 struct drm_crtc *crtc = &intel_crtc->base;
7089 struct drm_device *dev = crtc->dev;
7090 struct drm_i915_private *dev_priv = dev->dev_private;
7091 struct intel_encoder *intel_encoder;
7092 uint32_t dpll;
7093 int factor, num_connectors = 0;
7094 bool is_lvds = false, is_sdvo = false;
7095
7096 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
7097 switch (intel_encoder->type) {
7098 case INTEL_OUTPUT_LVDS:
7099 is_lvds = true;
7100 break;
7101 case INTEL_OUTPUT_SDVO:
7102 case INTEL_OUTPUT_HDMI:
7103 is_sdvo = true;
7104 break;
7105 }
7106
7107 num_connectors++;
7108 }
7109
7110 /* Enable autotuning of the PLL clock (if permissible) */
7111 factor = 21;
7112 if (is_lvds) {
7113 if ((intel_panel_use_ssc(dev_priv) &&
7114 dev_priv->vbt.lvds_ssc_freq == 100000) ||
7115 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7116 factor = 25;
7117 } else if (intel_crtc->config.sdvo_tv_clock)
7118 factor = 20;
7119
7120 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7121 *fp |= FP_CB_TUNE;
7122
7123 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7124 *fp2 |= FP_CB_TUNE;
7125
7126 dpll = 0;
7127
7128 if (is_lvds)
7129 dpll |= DPLLB_MODE_LVDS;
7130 else
7131 dpll |= DPLLB_MODE_DAC_SERIAL;
7132
7133 dpll |= (intel_crtc->config.pixel_multiplier - 1)
7134 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7135
7136 if (is_sdvo)
7137 dpll |= DPLL_SDVO_HIGH_SPEED;
7138 if (intel_crtc->config.has_dp_encoder)
7139 dpll |= DPLL_SDVO_HIGH_SPEED;
7140
7141 /* compute bitmask from p1 value */
7142 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7143 /* also FPA1 */
7144 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7145
7146 switch (intel_crtc->config.dpll.p2) {
7147 case 5:
7148 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7149 break;
7150 case 7:
7151 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7152 break;
7153 case 10:
7154 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7155 break;
7156 case 14:
7157 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7158 break;
7159 }
7160
7161 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7162 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7163 else
7164 dpll |= PLL_REF_INPUT_DREFCLK;
7165
7166 return dpll | DPLL_VCO_ENABLE;
7167 }
7168
7169 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
7170 int x, int y,
7171 struct drm_framebuffer *fb)
7172 {
7173 struct drm_device *dev = crtc->dev;
7174 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7175 int num_connectors = 0;
7176 intel_clock_t clock, reduced_clock;
7177 u32 dpll = 0, fp = 0, fp2 = 0;
7178 bool ok, has_reduced_clock = false;
7179 bool is_lvds = false;
7180 struct intel_encoder *encoder;
7181 struct intel_shared_dpll *pll;
7182
7183 for_each_encoder_on_crtc(dev, crtc, encoder) {
7184 switch (encoder->type) {
7185 case INTEL_OUTPUT_LVDS:
7186 is_lvds = true;
7187 break;
7188 }
7189
7190 num_connectors++;
7191 }
7192
7193 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7194 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7195
7196 ok = ironlake_compute_clocks(crtc, &clock,
7197 &has_reduced_clock, &reduced_clock);
7198 if (!ok && !intel_crtc->config.clock_set) {
7199 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7200 return -EINVAL;
7201 }
7202 /* Compat-code for transition, will disappear. */
7203 if (!intel_crtc->config.clock_set) {
7204 intel_crtc->config.dpll.n = clock.n;
7205 intel_crtc->config.dpll.m1 = clock.m1;
7206 intel_crtc->config.dpll.m2 = clock.m2;
7207 intel_crtc->config.dpll.p1 = clock.p1;
7208 intel_crtc->config.dpll.p2 = clock.p2;
7209 }
7210
7211 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7212 if (intel_crtc->config.has_pch_encoder) {
7213 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
7214 if (has_reduced_clock)
7215 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7216
7217 dpll = ironlake_compute_dpll(intel_crtc,
7218 &fp, &reduced_clock,
7219 has_reduced_clock ? &fp2 : NULL);
7220
7221 intel_crtc->config.dpll_hw_state.dpll = dpll;
7222 intel_crtc->config.dpll_hw_state.fp0 = fp;
7223 if (has_reduced_clock)
7224 intel_crtc->config.dpll_hw_state.fp1 = fp2;
7225 else
7226 intel_crtc->config.dpll_hw_state.fp1 = fp;
7227
7228 pll = intel_get_shared_dpll(intel_crtc);
7229 if (pll == NULL) {
7230 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7231 pipe_name(intel_crtc->pipe));
7232 return -EINVAL;
7233 }
7234 } else
7235 intel_put_shared_dpll(intel_crtc);
7236
7237 if (is_lvds && has_reduced_clock && i915.powersave)
7238 intel_crtc->lowfreq_avail = true;
7239 else
7240 intel_crtc->lowfreq_avail = false;
7241
7242 return 0;
7243 }
7244
7245 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7246 struct intel_link_m_n *m_n)
7247 {
7248 struct drm_device *dev = crtc->base.dev;
7249 struct drm_i915_private *dev_priv = dev->dev_private;
7250 enum pipe pipe = crtc->pipe;
7251
7252 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7253 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7254 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7255 & ~TU_SIZE_MASK;
7256 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7257 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7258 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7259 }
7260
7261 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7262 enum transcoder transcoder,
7263 struct intel_link_m_n *m_n,
7264 struct intel_link_m_n *m2_n2)
7265 {
7266 struct drm_device *dev = crtc->base.dev;
7267 struct drm_i915_private *dev_priv = dev->dev_private;
7268 enum pipe pipe = crtc->pipe;
7269
7270 if (INTEL_INFO(dev)->gen >= 5) {
7271 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7272 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7273 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7274 & ~TU_SIZE_MASK;
7275 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7276 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7277 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7278 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7279 * gen < 8) and if DRRS is supported (to make sure the
7280 * registers are not unnecessarily read).
7281 */
7282 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7283 crtc->config.has_drrs) {
7284 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7285 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7286 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7287 & ~TU_SIZE_MASK;
7288 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7289 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7290 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7291 }
7292 } else {
7293 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7294 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7295 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7296 & ~TU_SIZE_MASK;
7297 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7298 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7299 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7300 }
7301 }
7302
7303 void intel_dp_get_m_n(struct intel_crtc *crtc,
7304 struct intel_crtc_config *pipe_config)
7305 {
7306 if (crtc->config.has_pch_encoder)
7307 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7308 else
7309 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7310 &pipe_config->dp_m_n,
7311 &pipe_config->dp_m2_n2);
7312 }
7313
7314 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7315 struct intel_crtc_config *pipe_config)
7316 {
7317 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7318 &pipe_config->fdi_m_n, NULL);
7319 }
7320
7321 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7322 struct intel_crtc_config *pipe_config)
7323 {
7324 struct drm_device *dev = crtc->base.dev;
7325 struct drm_i915_private *dev_priv = dev->dev_private;
7326 uint32_t tmp;
7327
7328 tmp = I915_READ(PF_CTL(crtc->pipe));
7329
7330 if (tmp & PF_ENABLE) {
7331 pipe_config->pch_pfit.enabled = true;
7332 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7333 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7334
7335 /* We currently do not free assignements of panel fitters on
7336 * ivb/hsw (since we don't use the higher upscaling modes which
7337 * differentiates them) so just WARN about this case for now. */
7338 if (IS_GEN7(dev)) {
7339 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7340 PF_PIPE_SEL_IVB(crtc->pipe));
7341 }
7342 }
7343 }
7344
7345 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7346 struct intel_plane_config *plane_config)
7347 {
7348 struct drm_device *dev = crtc->base.dev;
7349 struct drm_i915_private *dev_priv = dev->dev_private;
7350 u32 val, base, offset;
7351 int pipe = crtc->pipe, plane = crtc->plane;
7352 int fourcc, pixel_format;
7353 int aligned_height;
7354
7355 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7356 if (!crtc->base.primary->fb) {
7357 DRM_DEBUG_KMS("failed to alloc fb\n");
7358 return;
7359 }
7360
7361 val = I915_READ(DSPCNTR(plane));
7362
7363 if (INTEL_INFO(dev)->gen >= 4)
7364 if (val & DISPPLANE_TILED)
7365 plane_config->tiled = true;
7366
7367 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7368 fourcc = intel_format_to_fourcc(pixel_format);
7369 crtc->base.primary->fb->pixel_format = fourcc;
7370 crtc->base.primary->fb->bits_per_pixel =
7371 drm_format_plane_cpp(fourcc, 0) * 8;
7372
7373 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7374 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7375 offset = I915_READ(DSPOFFSET(plane));
7376 } else {
7377 if (plane_config->tiled)
7378 offset = I915_READ(DSPTILEOFF(plane));
7379 else
7380 offset = I915_READ(DSPLINOFF(plane));
7381 }
7382 plane_config->base = base;
7383
7384 val = I915_READ(PIPESRC(pipe));
7385 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7386 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7387
7388 val = I915_READ(DSPSTRIDE(pipe));
7389 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
7390
7391 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7392 plane_config->tiled);
7393
7394 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7395 aligned_height);
7396
7397 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7398 pipe, plane, crtc->base.primary->fb->width,
7399 crtc->base.primary->fb->height,
7400 crtc->base.primary->fb->bits_per_pixel, base,
7401 crtc->base.primary->fb->pitches[0],
7402 plane_config->size);
7403 }
7404
7405 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7406 struct intel_crtc_config *pipe_config)
7407 {
7408 struct drm_device *dev = crtc->base.dev;
7409 struct drm_i915_private *dev_priv = dev->dev_private;
7410 uint32_t tmp;
7411
7412 if (!intel_display_power_enabled(dev_priv,
7413 POWER_DOMAIN_PIPE(crtc->pipe)))
7414 return false;
7415
7416 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7417 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7418
7419 tmp = I915_READ(PIPECONF(crtc->pipe));
7420 if (!(tmp & PIPECONF_ENABLE))
7421 return false;
7422
7423 switch (tmp & PIPECONF_BPC_MASK) {
7424 case PIPECONF_6BPC:
7425 pipe_config->pipe_bpp = 18;
7426 break;
7427 case PIPECONF_8BPC:
7428 pipe_config->pipe_bpp = 24;
7429 break;
7430 case PIPECONF_10BPC:
7431 pipe_config->pipe_bpp = 30;
7432 break;
7433 case PIPECONF_12BPC:
7434 pipe_config->pipe_bpp = 36;
7435 break;
7436 default:
7437 break;
7438 }
7439
7440 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7441 pipe_config->limited_color_range = true;
7442
7443 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7444 struct intel_shared_dpll *pll;
7445
7446 pipe_config->has_pch_encoder = true;
7447
7448 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7449 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7450 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7451
7452 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7453
7454 if (HAS_PCH_IBX(dev_priv->dev)) {
7455 pipe_config->shared_dpll =
7456 (enum intel_dpll_id) crtc->pipe;
7457 } else {
7458 tmp = I915_READ(PCH_DPLL_SEL);
7459 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7460 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7461 else
7462 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7463 }
7464
7465 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7466
7467 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7468 &pipe_config->dpll_hw_state));
7469
7470 tmp = pipe_config->dpll_hw_state.dpll;
7471 pipe_config->pixel_multiplier =
7472 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7473 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7474
7475 ironlake_pch_clock_get(crtc, pipe_config);
7476 } else {
7477 pipe_config->pixel_multiplier = 1;
7478 }
7479
7480 intel_get_pipe_timings(crtc, pipe_config);
7481
7482 ironlake_get_pfit_config(crtc, pipe_config);
7483
7484 return true;
7485 }
7486
7487 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7488 {
7489 struct drm_device *dev = dev_priv->dev;
7490 struct intel_crtc *crtc;
7491
7492 for_each_intel_crtc(dev, crtc)
7493 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7494 pipe_name(crtc->pipe));
7495
7496 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7497 WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7498 WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7499 WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7500 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7501 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7502 "CPU PWM1 enabled\n");
7503 if (IS_HASWELL(dev))
7504 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7505 "CPU PWM2 enabled\n");
7506 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7507 "PCH PWM1 enabled\n");
7508 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7509 "Utility pin enabled\n");
7510 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7511
7512 /*
7513 * In theory we can still leave IRQs enabled, as long as only the HPD
7514 * interrupts remain enabled. We used to check for that, but since it's
7515 * gen-specific and since we only disable LCPLL after we fully disable
7516 * the interrupts, the check below should be enough.
7517 */
7518 WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7519 }
7520
7521 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7522 {
7523 struct drm_device *dev = dev_priv->dev;
7524
7525 if (IS_HASWELL(dev))
7526 return I915_READ(D_COMP_HSW);
7527 else
7528 return I915_READ(D_COMP_BDW);
7529 }
7530
7531 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7532 {
7533 struct drm_device *dev = dev_priv->dev;
7534
7535 if (IS_HASWELL(dev)) {
7536 mutex_lock(&dev_priv->rps.hw_lock);
7537 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7538 val))
7539 DRM_ERROR("Failed to write to D_COMP\n");
7540 mutex_unlock(&dev_priv->rps.hw_lock);
7541 } else {
7542 I915_WRITE(D_COMP_BDW, val);
7543 POSTING_READ(D_COMP_BDW);
7544 }
7545 }
7546
7547 /*
7548 * This function implements pieces of two sequences from BSpec:
7549 * - Sequence for display software to disable LCPLL
7550 * - Sequence for display software to allow package C8+
7551 * The steps implemented here are just the steps that actually touch the LCPLL
7552 * register. Callers should take care of disabling all the display engine
7553 * functions, doing the mode unset, fixing interrupts, etc.
7554 */
7555 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7556 bool switch_to_fclk, bool allow_power_down)
7557 {
7558 uint32_t val;
7559
7560 assert_can_disable_lcpll(dev_priv);
7561
7562 val = I915_READ(LCPLL_CTL);
7563
7564 if (switch_to_fclk) {
7565 val |= LCPLL_CD_SOURCE_FCLK;
7566 I915_WRITE(LCPLL_CTL, val);
7567
7568 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7569 LCPLL_CD_SOURCE_FCLK_DONE, 1))
7570 DRM_ERROR("Switching to FCLK failed\n");
7571
7572 val = I915_READ(LCPLL_CTL);
7573 }
7574
7575 val |= LCPLL_PLL_DISABLE;
7576 I915_WRITE(LCPLL_CTL, val);
7577 POSTING_READ(LCPLL_CTL);
7578
7579 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7580 DRM_ERROR("LCPLL still locked\n");
7581
7582 val = hsw_read_dcomp(dev_priv);
7583 val |= D_COMP_COMP_DISABLE;
7584 hsw_write_dcomp(dev_priv, val);
7585 ndelay(100);
7586
7587 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7588 1))
7589 DRM_ERROR("D_COMP RCOMP still in progress\n");
7590
7591 if (allow_power_down) {
7592 val = I915_READ(LCPLL_CTL);
7593 val |= LCPLL_POWER_DOWN_ALLOW;
7594 I915_WRITE(LCPLL_CTL, val);
7595 POSTING_READ(LCPLL_CTL);
7596 }
7597 }
7598
7599 /*
7600 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7601 * source.
7602 */
7603 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7604 {
7605 uint32_t val;
7606 unsigned long irqflags;
7607
7608 val = I915_READ(LCPLL_CTL);
7609
7610 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7611 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7612 return;
7613
7614 /*
7615 * Make sure we're not on PC8 state before disabling PC8, otherwise
7616 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7617 *
7618 * The other problem is that hsw_restore_lcpll() is called as part of
7619 * the runtime PM resume sequence, so we can't just call
7620 * gen6_gt_force_wake_get() because that function calls
7621 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7622 * while we are on the resume sequence. So to solve this problem we have
7623 * to call special forcewake code that doesn't touch runtime PM and
7624 * doesn't enable the forcewake delayed work.
7625 */
7626 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7627 if (dev_priv->uncore.forcewake_count++ == 0)
7628 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7629 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7630
7631 if (val & LCPLL_POWER_DOWN_ALLOW) {
7632 val &= ~LCPLL_POWER_DOWN_ALLOW;
7633 I915_WRITE(LCPLL_CTL, val);
7634 POSTING_READ(LCPLL_CTL);
7635 }
7636
7637 val = hsw_read_dcomp(dev_priv);
7638 val |= D_COMP_COMP_FORCE;
7639 val &= ~D_COMP_COMP_DISABLE;
7640 hsw_write_dcomp(dev_priv, val);
7641
7642 val = I915_READ(LCPLL_CTL);
7643 val &= ~LCPLL_PLL_DISABLE;
7644 I915_WRITE(LCPLL_CTL, val);
7645
7646 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7647 DRM_ERROR("LCPLL not locked yet\n");
7648
7649 if (val & LCPLL_CD_SOURCE_FCLK) {
7650 val = I915_READ(LCPLL_CTL);
7651 val &= ~LCPLL_CD_SOURCE_FCLK;
7652 I915_WRITE(LCPLL_CTL, val);
7653
7654 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7655 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7656 DRM_ERROR("Switching back to LCPLL failed\n");
7657 }
7658
7659 /* See the big comment above. */
7660 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7661 if (--dev_priv->uncore.forcewake_count == 0)
7662 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7663 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7664 }
7665
7666 /*
7667 * Package states C8 and deeper are really deep PC states that can only be
7668 * reached when all the devices on the system allow it, so even if the graphics
7669 * device allows PC8+, it doesn't mean the system will actually get to these
7670 * states. Our driver only allows PC8+ when going into runtime PM.
7671 *
7672 * The requirements for PC8+ are that all the outputs are disabled, the power
7673 * well is disabled and most interrupts are disabled, and these are also
7674 * requirements for runtime PM. When these conditions are met, we manually do
7675 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7676 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7677 * hang the machine.
7678 *
7679 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7680 * the state of some registers, so when we come back from PC8+ we need to
7681 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7682 * need to take care of the registers kept by RC6. Notice that this happens even
7683 * if we don't put the device in PCI D3 state (which is what currently happens
7684 * because of the runtime PM support).
7685 *
7686 * For more, read "Display Sequences for Package C8" on the hardware
7687 * documentation.
7688 */
7689 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7690 {
7691 struct drm_device *dev = dev_priv->dev;
7692 uint32_t val;
7693
7694 DRM_DEBUG_KMS("Enabling package C8+\n");
7695
7696 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7697 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7698 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7699 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7700 }
7701
7702 lpt_disable_clkout_dp(dev);
7703 hsw_disable_lcpll(dev_priv, true, true);
7704 }
7705
7706 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7707 {
7708 struct drm_device *dev = dev_priv->dev;
7709 uint32_t val;
7710
7711 DRM_DEBUG_KMS("Disabling package C8+\n");
7712
7713 hsw_restore_lcpll(dev_priv);
7714 lpt_init_pch_refclk(dev);
7715
7716 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7717 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7718 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7719 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7720 }
7721
7722 intel_prepare_ddi(dev);
7723 }
7724
7725 static void snb_modeset_global_resources(struct drm_device *dev)
7726 {
7727 modeset_update_crtc_power_domains(dev);
7728 }
7729
7730 static void haswell_modeset_global_resources(struct drm_device *dev)
7731 {
7732 modeset_update_crtc_power_domains(dev);
7733 }
7734
7735 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7736 int x, int y,
7737 struct drm_framebuffer *fb)
7738 {
7739 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7740
7741 if (!intel_ddi_pll_select(intel_crtc))
7742 return -EINVAL;
7743
7744 intel_crtc->lowfreq_avail = false;
7745
7746 return 0;
7747 }
7748
7749 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
7750 enum port port,
7751 struct intel_crtc_config *pipe_config)
7752 {
7753 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
7754
7755 switch (pipe_config->ddi_pll_sel) {
7756 case PORT_CLK_SEL_WRPLL1:
7757 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
7758 break;
7759 case PORT_CLK_SEL_WRPLL2:
7760 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
7761 break;
7762 }
7763 }
7764
7765 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
7766 struct intel_crtc_config *pipe_config)
7767 {
7768 struct drm_device *dev = crtc->base.dev;
7769 struct drm_i915_private *dev_priv = dev->dev_private;
7770 struct intel_shared_dpll *pll;
7771 enum port port;
7772 uint32_t tmp;
7773
7774 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7775
7776 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
7777
7778 haswell_get_ddi_pll(dev_priv, port, pipe_config);
7779
7780 if (pipe_config->shared_dpll >= 0) {
7781 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7782
7783 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7784 &pipe_config->dpll_hw_state));
7785 }
7786
7787 /*
7788 * Haswell has only FDI/PCH transcoder A. It is which is connected to
7789 * DDI E. So just check whether this pipe is wired to DDI E and whether
7790 * the PCH transcoder is on.
7791 */
7792 if ((port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7793 pipe_config->has_pch_encoder = true;
7794
7795 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7796 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7797 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7798
7799 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7800 }
7801 }
7802
7803 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7804 struct intel_crtc_config *pipe_config)
7805 {
7806 struct drm_device *dev = crtc->base.dev;
7807 struct drm_i915_private *dev_priv = dev->dev_private;
7808 enum intel_display_power_domain pfit_domain;
7809 uint32_t tmp;
7810
7811 if (!intel_display_power_enabled(dev_priv,
7812 POWER_DOMAIN_PIPE(crtc->pipe)))
7813 return false;
7814
7815 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7816 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7817
7818 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7819 if (tmp & TRANS_DDI_FUNC_ENABLE) {
7820 enum pipe trans_edp_pipe;
7821 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7822 default:
7823 WARN(1, "unknown pipe linked to edp transcoder\n");
7824 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7825 case TRANS_DDI_EDP_INPUT_A_ON:
7826 trans_edp_pipe = PIPE_A;
7827 break;
7828 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7829 trans_edp_pipe = PIPE_B;
7830 break;
7831 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7832 trans_edp_pipe = PIPE_C;
7833 break;
7834 }
7835
7836 if (trans_edp_pipe == crtc->pipe)
7837 pipe_config->cpu_transcoder = TRANSCODER_EDP;
7838 }
7839
7840 if (!intel_display_power_enabled(dev_priv,
7841 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7842 return false;
7843
7844 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7845 if (!(tmp & PIPECONF_ENABLE))
7846 return false;
7847
7848 haswell_get_ddi_port_state(crtc, pipe_config);
7849
7850 intel_get_pipe_timings(crtc, pipe_config);
7851
7852 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7853 if (intel_display_power_enabled(dev_priv, pfit_domain))
7854 ironlake_get_pfit_config(crtc, pipe_config);
7855
7856 if (IS_HASWELL(dev))
7857 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7858 (I915_READ(IPS_CTL) & IPS_ENABLE);
7859
7860 pipe_config->pixel_multiplier = 1;
7861
7862 return true;
7863 }
7864
7865 static struct {
7866 int clock;
7867 u32 config;
7868 } hdmi_audio_clock[] = {
7869 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7870 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7871 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7872 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7873 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7874 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7875 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7876 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7877 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7878 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7879 };
7880
7881 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7882 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7883 {
7884 int i;
7885
7886 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7887 if (mode->clock == hdmi_audio_clock[i].clock)
7888 break;
7889 }
7890
7891 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7892 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7893 i = 1;
7894 }
7895
7896 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7897 hdmi_audio_clock[i].clock,
7898 hdmi_audio_clock[i].config);
7899
7900 return hdmi_audio_clock[i].config;
7901 }
7902
7903 static bool intel_eld_uptodate(struct drm_connector *connector,
7904 int reg_eldv, uint32_t bits_eldv,
7905 int reg_elda, uint32_t bits_elda,
7906 int reg_edid)
7907 {
7908 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7909 uint8_t *eld = connector->eld;
7910 uint32_t i;
7911
7912 i = I915_READ(reg_eldv);
7913 i &= bits_eldv;
7914
7915 if (!eld[0])
7916 return !i;
7917
7918 if (!i)
7919 return false;
7920
7921 i = I915_READ(reg_elda);
7922 i &= ~bits_elda;
7923 I915_WRITE(reg_elda, i);
7924
7925 for (i = 0; i < eld[2]; i++)
7926 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7927 return false;
7928
7929 return true;
7930 }
7931
7932 static void g4x_write_eld(struct drm_connector *connector,
7933 struct drm_crtc *crtc,
7934 struct drm_display_mode *mode)
7935 {
7936 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7937 uint8_t *eld = connector->eld;
7938 uint32_t eldv;
7939 uint32_t len;
7940 uint32_t i;
7941
7942 i = I915_READ(G4X_AUD_VID_DID);
7943
7944 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7945 eldv = G4X_ELDV_DEVCL_DEVBLC;
7946 else
7947 eldv = G4X_ELDV_DEVCTG;
7948
7949 if (intel_eld_uptodate(connector,
7950 G4X_AUD_CNTL_ST, eldv,
7951 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7952 G4X_HDMIW_HDMIEDID))
7953 return;
7954
7955 i = I915_READ(G4X_AUD_CNTL_ST);
7956 i &= ~(eldv | G4X_ELD_ADDR);
7957 len = (i >> 9) & 0x1f; /* ELD buffer size */
7958 I915_WRITE(G4X_AUD_CNTL_ST, i);
7959
7960 if (!eld[0])
7961 return;
7962
7963 len = min_t(uint8_t, eld[2], len);
7964 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7965 for (i = 0; i < len; i++)
7966 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7967
7968 i = I915_READ(G4X_AUD_CNTL_ST);
7969 i |= eldv;
7970 I915_WRITE(G4X_AUD_CNTL_ST, i);
7971 }
7972
7973 static void haswell_write_eld(struct drm_connector *connector,
7974 struct drm_crtc *crtc,
7975 struct drm_display_mode *mode)
7976 {
7977 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7978 uint8_t *eld = connector->eld;
7979 uint32_t eldv;
7980 uint32_t i;
7981 int len;
7982 int pipe = to_intel_crtc(crtc)->pipe;
7983 int tmp;
7984
7985 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7986 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7987 int aud_config = HSW_AUD_CFG(pipe);
7988 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7989
7990 /* Audio output enable */
7991 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7992 tmp = I915_READ(aud_cntrl_st2);
7993 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7994 I915_WRITE(aud_cntrl_st2, tmp);
7995 POSTING_READ(aud_cntrl_st2);
7996
7997 assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
7998
7999 /* Set ELD valid state */
8000 tmp = I915_READ(aud_cntrl_st2);
8001 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
8002 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
8003 I915_WRITE(aud_cntrl_st2, tmp);
8004 tmp = I915_READ(aud_cntrl_st2);
8005 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
8006
8007 /* Enable HDMI mode */
8008 tmp = I915_READ(aud_config);
8009 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
8010 /* clear N_programing_enable and N_value_index */
8011 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
8012 I915_WRITE(aud_config, tmp);
8013
8014 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
8015
8016 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
8017
8018 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
8019 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
8020 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
8021 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
8022 } else {
8023 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
8024 }
8025
8026 if (intel_eld_uptodate(connector,
8027 aud_cntrl_st2, eldv,
8028 aud_cntl_st, IBX_ELD_ADDRESS,
8029 hdmiw_hdmiedid))
8030 return;
8031
8032 i = I915_READ(aud_cntrl_st2);
8033 i &= ~eldv;
8034 I915_WRITE(aud_cntrl_st2, i);
8035
8036 if (!eld[0])
8037 return;
8038
8039 i = I915_READ(aud_cntl_st);
8040 i &= ~IBX_ELD_ADDRESS;
8041 I915_WRITE(aud_cntl_st, i);
8042 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
8043 DRM_DEBUG_DRIVER("port num:%d\n", i);
8044
8045 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
8046 DRM_DEBUG_DRIVER("ELD size %d\n", len);
8047 for (i = 0; i < len; i++)
8048 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
8049
8050 i = I915_READ(aud_cntrl_st2);
8051 i |= eldv;
8052 I915_WRITE(aud_cntrl_st2, i);
8053
8054 }
8055
8056 static void ironlake_write_eld(struct drm_connector *connector,
8057 struct drm_crtc *crtc,
8058 struct drm_display_mode *mode)
8059 {
8060 struct drm_i915_private *dev_priv = connector->dev->dev_private;
8061 uint8_t *eld = connector->eld;
8062 uint32_t eldv;
8063 uint32_t i;
8064 int len;
8065 int hdmiw_hdmiedid;
8066 int aud_config;
8067 int aud_cntl_st;
8068 int aud_cntrl_st2;
8069 int pipe = to_intel_crtc(crtc)->pipe;
8070
8071 if (HAS_PCH_IBX(connector->dev)) {
8072 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
8073 aud_config = IBX_AUD_CFG(pipe);
8074 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
8075 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
8076 } else if (IS_VALLEYVIEW(connector->dev)) {
8077 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
8078 aud_config = VLV_AUD_CFG(pipe);
8079 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
8080 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
8081 } else {
8082 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
8083 aud_config = CPT_AUD_CFG(pipe);
8084 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
8085 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
8086 }
8087
8088 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
8089
8090 if (IS_VALLEYVIEW(connector->dev)) {
8091 struct intel_encoder *intel_encoder;
8092 struct intel_digital_port *intel_dig_port;
8093
8094 intel_encoder = intel_attached_encoder(connector);
8095 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
8096 i = intel_dig_port->port;
8097 } else {
8098 i = I915_READ(aud_cntl_st);
8099 i = (i >> 29) & DIP_PORT_SEL_MASK;
8100 /* DIP_Port_Select, 0x1 = PortB */
8101 }
8102
8103 if (!i) {
8104 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
8105 /* operate blindly on all ports */
8106 eldv = IBX_ELD_VALIDB;
8107 eldv |= IBX_ELD_VALIDB << 4;
8108 eldv |= IBX_ELD_VALIDB << 8;
8109 } else {
8110 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
8111 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
8112 }
8113
8114 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
8115 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
8116 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
8117 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
8118 } else {
8119 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
8120 }
8121
8122 if (intel_eld_uptodate(connector,
8123 aud_cntrl_st2, eldv,
8124 aud_cntl_st, IBX_ELD_ADDRESS,
8125 hdmiw_hdmiedid))
8126 return;
8127
8128 i = I915_READ(aud_cntrl_st2);
8129 i &= ~eldv;
8130 I915_WRITE(aud_cntrl_st2, i);
8131
8132 if (!eld[0])
8133 return;
8134
8135 i = I915_READ(aud_cntl_st);
8136 i &= ~IBX_ELD_ADDRESS;
8137 I915_WRITE(aud_cntl_st, i);
8138
8139 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
8140 DRM_DEBUG_DRIVER("ELD size %d\n", len);
8141 for (i = 0; i < len; i++)
8142 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
8143
8144 i = I915_READ(aud_cntrl_st2);
8145 i |= eldv;
8146 I915_WRITE(aud_cntrl_st2, i);
8147 }
8148
8149 void intel_write_eld(struct drm_encoder *encoder,
8150 struct drm_display_mode *mode)
8151 {
8152 struct drm_crtc *crtc = encoder->crtc;
8153 struct drm_connector *connector;
8154 struct drm_device *dev = encoder->dev;
8155 struct drm_i915_private *dev_priv = dev->dev_private;
8156
8157 connector = drm_select_eld(encoder, mode);
8158 if (!connector)
8159 return;
8160
8161 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8162 connector->base.id,
8163 connector->name,
8164 connector->encoder->base.id,
8165 connector->encoder->name);
8166
8167 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
8168
8169 if (dev_priv->display.write_eld)
8170 dev_priv->display.write_eld(connector, crtc, mode);
8171 }
8172
8173 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8174 {
8175 struct drm_device *dev = crtc->dev;
8176 struct drm_i915_private *dev_priv = dev->dev_private;
8177 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8178 uint32_t cntl = 0, size = 0;
8179
8180 if (base) {
8181 unsigned int width = intel_crtc->cursor_width;
8182 unsigned int height = intel_crtc->cursor_height;
8183 unsigned int stride = roundup_pow_of_two(width) * 4;
8184
8185 switch (stride) {
8186 default:
8187 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8188 width, stride);
8189 stride = 256;
8190 /* fallthrough */
8191 case 256:
8192 case 512:
8193 case 1024:
8194 case 2048:
8195 break;
8196 }
8197
8198 cntl |= CURSOR_ENABLE |
8199 CURSOR_GAMMA_ENABLE |
8200 CURSOR_FORMAT_ARGB |
8201 CURSOR_STRIDE(stride);
8202
8203 size = (height << 12) | width;
8204 }
8205
8206 if (intel_crtc->cursor_cntl != 0 &&
8207 (intel_crtc->cursor_base != base ||
8208 intel_crtc->cursor_size != size ||
8209 intel_crtc->cursor_cntl != cntl)) {
8210 /* On these chipsets we can only modify the base/size/stride
8211 * whilst the cursor is disabled.
8212 */
8213 I915_WRITE(_CURACNTR, 0);
8214 POSTING_READ(_CURACNTR);
8215 intel_crtc->cursor_cntl = 0;
8216 }
8217
8218 if (intel_crtc->cursor_base != base) {
8219 I915_WRITE(_CURABASE, base);
8220 intel_crtc->cursor_base = base;
8221 }
8222
8223 if (intel_crtc->cursor_size != size) {
8224 I915_WRITE(CURSIZE, size);
8225 intel_crtc->cursor_size = size;
8226 }
8227
8228 if (intel_crtc->cursor_cntl != cntl) {
8229 I915_WRITE(_CURACNTR, cntl);
8230 POSTING_READ(_CURACNTR);
8231 intel_crtc->cursor_cntl = cntl;
8232 }
8233 }
8234
8235 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8236 {
8237 struct drm_device *dev = crtc->dev;
8238 struct drm_i915_private *dev_priv = dev->dev_private;
8239 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8240 int pipe = intel_crtc->pipe;
8241 uint32_t cntl;
8242
8243 cntl = 0;
8244 if (base) {
8245 cntl = MCURSOR_GAMMA_ENABLE;
8246 switch (intel_crtc->cursor_width) {
8247 case 64:
8248 cntl |= CURSOR_MODE_64_ARGB_AX;
8249 break;
8250 case 128:
8251 cntl |= CURSOR_MODE_128_ARGB_AX;
8252 break;
8253 case 256:
8254 cntl |= CURSOR_MODE_256_ARGB_AX;
8255 break;
8256 default:
8257 WARN_ON(1);
8258 return;
8259 }
8260 cntl |= pipe << 28; /* Connect to correct pipe */
8261
8262 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8263 cntl |= CURSOR_PIPE_CSC_ENABLE;
8264 }
8265
8266 if (intel_crtc->cursor_cntl != cntl) {
8267 I915_WRITE(CURCNTR(pipe), cntl);
8268 POSTING_READ(CURCNTR(pipe));
8269 intel_crtc->cursor_cntl = cntl;
8270 }
8271
8272 /* and commit changes on next vblank */
8273 I915_WRITE(CURBASE(pipe), base);
8274 POSTING_READ(CURBASE(pipe));
8275
8276 intel_crtc->cursor_base = base;
8277 }
8278
8279 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8280 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8281 bool on)
8282 {
8283 struct drm_device *dev = crtc->dev;
8284 struct drm_i915_private *dev_priv = dev->dev_private;
8285 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8286 int pipe = intel_crtc->pipe;
8287 int x = crtc->cursor_x;
8288 int y = crtc->cursor_y;
8289 u32 base = 0, pos = 0;
8290
8291 if (on)
8292 base = intel_crtc->cursor_addr;
8293
8294 if (x >= intel_crtc->config.pipe_src_w)
8295 base = 0;
8296
8297 if (y >= intel_crtc->config.pipe_src_h)
8298 base = 0;
8299
8300 if (x < 0) {
8301 if (x + intel_crtc->cursor_width <= 0)
8302 base = 0;
8303
8304 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8305 x = -x;
8306 }
8307 pos |= x << CURSOR_X_SHIFT;
8308
8309 if (y < 0) {
8310 if (y + intel_crtc->cursor_height <= 0)
8311 base = 0;
8312
8313 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8314 y = -y;
8315 }
8316 pos |= y << CURSOR_Y_SHIFT;
8317
8318 if (base == 0 && intel_crtc->cursor_base == 0)
8319 return;
8320
8321 I915_WRITE(CURPOS(pipe), pos);
8322
8323 if (IS_845G(dev) || IS_I865G(dev))
8324 i845_update_cursor(crtc, base);
8325 else
8326 i9xx_update_cursor(crtc, base);
8327 }
8328
8329 static bool cursor_size_ok(struct drm_device *dev,
8330 uint32_t width, uint32_t height)
8331 {
8332 if (width == 0 || height == 0)
8333 return false;
8334
8335 /*
8336 * 845g/865g are special in that they are only limited by
8337 * the width of their cursors, the height is arbitrary up to
8338 * the precision of the register. Everything else requires
8339 * square cursors, limited to a few power-of-two sizes.
8340 */
8341 if (IS_845G(dev) || IS_I865G(dev)) {
8342 if ((width & 63) != 0)
8343 return false;
8344
8345 if (width > (IS_845G(dev) ? 64 : 512))
8346 return false;
8347
8348 if (height > 1023)
8349 return false;
8350 } else {
8351 switch (width | height) {
8352 case 256:
8353 case 128:
8354 if (IS_GEN2(dev))
8355 return false;
8356 case 64:
8357 break;
8358 default:
8359 return false;
8360 }
8361 }
8362
8363 return true;
8364 }
8365
8366 /*
8367 * intel_crtc_cursor_set_obj - Set cursor to specified GEM object
8368 *
8369 * Note that the object's reference will be consumed if the update fails. If
8370 * the update succeeds, the reference of the old object (if any) will be
8371 * consumed.
8372 */
8373 static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8374 struct drm_i915_gem_object *obj,
8375 uint32_t width, uint32_t height)
8376 {
8377 struct drm_device *dev = crtc->dev;
8378 struct drm_i915_private *dev_priv = dev->dev_private;
8379 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8380 enum pipe pipe = intel_crtc->pipe;
8381 unsigned old_width, stride;
8382 uint32_t addr;
8383 int ret;
8384
8385 /* if we want to turn off the cursor ignore width and height */
8386 if (!obj) {
8387 DRM_DEBUG_KMS("cursor off\n");
8388 addr = 0;
8389 mutex_lock(&dev->struct_mutex);
8390 goto finish;
8391 }
8392
8393 /* Check for which cursor types we support */
8394 if (!cursor_size_ok(dev, width, height)) {
8395 DRM_DEBUG("Cursor dimension not supported\n");
8396 return -EINVAL;
8397 }
8398
8399 stride = roundup_pow_of_two(width) * 4;
8400 if (obj->base.size < stride * height) {
8401 DRM_DEBUG_KMS("buffer is too small\n");
8402 ret = -ENOMEM;
8403 goto fail;
8404 }
8405
8406 /* we only need to pin inside GTT if cursor is non-phy */
8407 mutex_lock(&dev->struct_mutex);
8408 if (!INTEL_INFO(dev)->cursor_needs_physical) {
8409 unsigned alignment;
8410
8411 if (obj->tiling_mode) {
8412 DRM_DEBUG_KMS("cursor cannot be tiled\n");
8413 ret = -EINVAL;
8414 goto fail_locked;
8415 }
8416
8417 /*
8418 * Global gtt pte registers are special registers which actually
8419 * forward writes to a chunk of system memory. Which means that
8420 * there is no risk that the register values disappear as soon
8421 * as we call intel_runtime_pm_put(), so it is correct to wrap
8422 * only the pin/unpin/fence and not more.
8423 */
8424 intel_runtime_pm_get(dev_priv);
8425
8426 /* Note that the w/a also requires 2 PTE of padding following
8427 * the bo. We currently fill all unused PTE with the shadow
8428 * page and so we should always have valid PTE following the
8429 * cursor preventing the VT-d warning.
8430 */
8431 alignment = 0;
8432 if (need_vtd_wa(dev))
8433 alignment = 64*1024;
8434
8435 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8436 if (ret) {
8437 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8438 intel_runtime_pm_put(dev_priv);
8439 goto fail_locked;
8440 }
8441
8442 ret = i915_gem_object_put_fence(obj);
8443 if (ret) {
8444 DRM_DEBUG_KMS("failed to release fence for cursor");
8445 intel_runtime_pm_put(dev_priv);
8446 goto fail_unpin;
8447 }
8448
8449 addr = i915_gem_obj_ggtt_offset(obj);
8450
8451 intel_runtime_pm_put(dev_priv);
8452 } else {
8453 int align = IS_I830(dev) ? 16 * 1024 : 256;
8454 ret = i915_gem_object_attach_phys(obj, align);
8455 if (ret) {
8456 DRM_DEBUG_KMS("failed to attach phys object\n");
8457 goto fail_locked;
8458 }
8459 addr = obj->phys_handle->busaddr;
8460 }
8461
8462 finish:
8463 if (intel_crtc->cursor_bo) {
8464 if (!INTEL_INFO(dev)->cursor_needs_physical)
8465 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8466 }
8467
8468 i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8469 INTEL_FRONTBUFFER_CURSOR(pipe));
8470 mutex_unlock(&dev->struct_mutex);
8471
8472 old_width = intel_crtc->cursor_width;
8473
8474 intel_crtc->cursor_addr = addr;
8475 intel_crtc->cursor_bo = obj;
8476 intel_crtc->cursor_width = width;
8477 intel_crtc->cursor_height = height;
8478
8479 if (intel_crtc->active) {
8480 if (old_width != width)
8481 intel_update_watermarks(crtc);
8482 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8483 }
8484
8485 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
8486
8487 return 0;
8488 fail_unpin:
8489 i915_gem_object_unpin_from_display_plane(obj);
8490 fail_locked:
8491 mutex_unlock(&dev->struct_mutex);
8492 fail:
8493 drm_gem_object_unreference_unlocked(&obj->base);
8494 return ret;
8495 }
8496
8497 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8498 u16 *blue, uint32_t start, uint32_t size)
8499 {
8500 int end = (start + size > 256) ? 256 : start + size, i;
8501 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8502
8503 for (i = start; i < end; i++) {
8504 intel_crtc->lut_r[i] = red[i] >> 8;
8505 intel_crtc->lut_g[i] = green[i] >> 8;
8506 intel_crtc->lut_b[i] = blue[i] >> 8;
8507 }
8508
8509 intel_crtc_load_lut(crtc);
8510 }
8511
8512 /* VESA 640x480x72Hz mode to set on the pipe */
8513 static struct drm_display_mode load_detect_mode = {
8514 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8515 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8516 };
8517
8518 struct drm_framebuffer *
8519 __intel_framebuffer_create(struct drm_device *dev,
8520 struct drm_mode_fb_cmd2 *mode_cmd,
8521 struct drm_i915_gem_object *obj)
8522 {
8523 struct intel_framebuffer *intel_fb;
8524 int ret;
8525
8526 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8527 if (!intel_fb) {
8528 drm_gem_object_unreference_unlocked(&obj->base);
8529 return ERR_PTR(-ENOMEM);
8530 }
8531
8532 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8533 if (ret)
8534 goto err;
8535
8536 return &intel_fb->base;
8537 err:
8538 drm_gem_object_unreference_unlocked(&obj->base);
8539 kfree(intel_fb);
8540
8541 return ERR_PTR(ret);
8542 }
8543
8544 static struct drm_framebuffer *
8545 intel_framebuffer_create(struct drm_device *dev,
8546 struct drm_mode_fb_cmd2 *mode_cmd,
8547 struct drm_i915_gem_object *obj)
8548 {
8549 struct drm_framebuffer *fb;
8550 int ret;
8551
8552 ret = i915_mutex_lock_interruptible(dev);
8553 if (ret)
8554 return ERR_PTR(ret);
8555 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8556 mutex_unlock(&dev->struct_mutex);
8557
8558 return fb;
8559 }
8560
8561 static u32
8562 intel_framebuffer_pitch_for_width(int width, int bpp)
8563 {
8564 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8565 return ALIGN(pitch, 64);
8566 }
8567
8568 static u32
8569 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8570 {
8571 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8572 return PAGE_ALIGN(pitch * mode->vdisplay);
8573 }
8574
8575 static struct drm_framebuffer *
8576 intel_framebuffer_create_for_mode(struct drm_device *dev,
8577 struct drm_display_mode *mode,
8578 int depth, int bpp)
8579 {
8580 struct drm_i915_gem_object *obj;
8581 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8582
8583 obj = i915_gem_alloc_object(dev,
8584 intel_framebuffer_size_for_mode(mode, bpp));
8585 if (obj == NULL)
8586 return ERR_PTR(-ENOMEM);
8587
8588 mode_cmd.width = mode->hdisplay;
8589 mode_cmd.height = mode->vdisplay;
8590 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8591 bpp);
8592 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8593
8594 return intel_framebuffer_create(dev, &mode_cmd, obj);
8595 }
8596
8597 static struct drm_framebuffer *
8598 mode_fits_in_fbdev(struct drm_device *dev,
8599 struct drm_display_mode *mode)
8600 {
8601 #ifdef CONFIG_DRM_I915_FBDEV
8602 struct drm_i915_private *dev_priv = dev->dev_private;
8603 struct drm_i915_gem_object *obj;
8604 struct drm_framebuffer *fb;
8605
8606 if (!dev_priv->fbdev)
8607 return NULL;
8608
8609 if (!dev_priv->fbdev->fb)
8610 return NULL;
8611
8612 obj = dev_priv->fbdev->fb->obj;
8613 BUG_ON(!obj);
8614
8615 fb = &dev_priv->fbdev->fb->base;
8616 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8617 fb->bits_per_pixel))
8618 return NULL;
8619
8620 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8621 return NULL;
8622
8623 return fb;
8624 #else
8625 return NULL;
8626 #endif
8627 }
8628
8629 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8630 struct drm_display_mode *mode,
8631 struct intel_load_detect_pipe *old,
8632 struct drm_modeset_acquire_ctx *ctx)
8633 {
8634 struct intel_crtc *intel_crtc;
8635 struct intel_encoder *intel_encoder =
8636 intel_attached_encoder(connector);
8637 struct drm_crtc *possible_crtc;
8638 struct drm_encoder *encoder = &intel_encoder->base;
8639 struct drm_crtc *crtc = NULL;
8640 struct drm_device *dev = encoder->dev;
8641 struct drm_framebuffer *fb;
8642 struct drm_mode_config *config = &dev->mode_config;
8643 int ret, i = -1;
8644
8645 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8646 connector->base.id, connector->name,
8647 encoder->base.id, encoder->name);
8648
8649 retry:
8650 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8651 if (ret)
8652 goto fail_unlock;
8653
8654 /*
8655 * Algorithm gets a little messy:
8656 *
8657 * - if the connector already has an assigned crtc, use it (but make
8658 * sure it's on first)
8659 *
8660 * - try to find the first unused crtc that can drive this connector,
8661 * and use that if we find one
8662 */
8663
8664 /* See if we already have a CRTC for this connector */
8665 if (encoder->crtc) {
8666 crtc = encoder->crtc;
8667
8668 ret = drm_modeset_lock(&crtc->mutex, ctx);
8669 if (ret)
8670 goto fail_unlock;
8671
8672 old->dpms_mode = connector->dpms;
8673 old->load_detect_temp = false;
8674
8675 /* Make sure the crtc and connector are running */
8676 if (connector->dpms != DRM_MODE_DPMS_ON)
8677 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8678
8679 return true;
8680 }
8681
8682 /* Find an unused one (if possible) */
8683 for_each_crtc(dev, possible_crtc) {
8684 i++;
8685 if (!(encoder->possible_crtcs & (1 << i)))
8686 continue;
8687 if (possible_crtc->enabled)
8688 continue;
8689 /* This can occur when applying the pipe A quirk on resume. */
8690 if (to_intel_crtc(possible_crtc)->new_enabled)
8691 continue;
8692
8693 crtc = possible_crtc;
8694 break;
8695 }
8696
8697 /*
8698 * If we didn't find an unused CRTC, don't use any.
8699 */
8700 if (!crtc) {
8701 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8702 goto fail_unlock;
8703 }
8704
8705 ret = drm_modeset_lock(&crtc->mutex, ctx);
8706 if (ret)
8707 goto fail_unlock;
8708 intel_encoder->new_crtc = to_intel_crtc(crtc);
8709 to_intel_connector(connector)->new_encoder = intel_encoder;
8710
8711 intel_crtc = to_intel_crtc(crtc);
8712 intel_crtc->new_enabled = true;
8713 intel_crtc->new_config = &intel_crtc->config;
8714 old->dpms_mode = connector->dpms;
8715 old->load_detect_temp = true;
8716 old->release_fb = NULL;
8717
8718 if (!mode)
8719 mode = &load_detect_mode;
8720
8721 /* We need a framebuffer large enough to accommodate all accesses
8722 * that the plane may generate whilst we perform load detection.
8723 * We can not rely on the fbcon either being present (we get called
8724 * during its initialisation to detect all boot displays, or it may
8725 * not even exist) or that it is large enough to satisfy the
8726 * requested mode.
8727 */
8728 fb = mode_fits_in_fbdev(dev, mode);
8729 if (fb == NULL) {
8730 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8731 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8732 old->release_fb = fb;
8733 } else
8734 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8735 if (IS_ERR(fb)) {
8736 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8737 goto fail;
8738 }
8739
8740 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8741 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8742 if (old->release_fb)
8743 old->release_fb->funcs->destroy(old->release_fb);
8744 goto fail;
8745 }
8746
8747 /* let the connector get through one full cycle before testing */
8748 intel_wait_for_vblank(dev, intel_crtc->pipe);
8749 return true;
8750
8751 fail:
8752 intel_crtc->new_enabled = crtc->enabled;
8753 if (intel_crtc->new_enabled)
8754 intel_crtc->new_config = &intel_crtc->config;
8755 else
8756 intel_crtc->new_config = NULL;
8757 fail_unlock:
8758 if (ret == -EDEADLK) {
8759 drm_modeset_backoff(ctx);
8760 goto retry;
8761 }
8762
8763 return false;
8764 }
8765
8766 void intel_release_load_detect_pipe(struct drm_connector *connector,
8767 struct intel_load_detect_pipe *old)
8768 {
8769 struct intel_encoder *intel_encoder =
8770 intel_attached_encoder(connector);
8771 struct drm_encoder *encoder = &intel_encoder->base;
8772 struct drm_crtc *crtc = encoder->crtc;
8773 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8774
8775 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8776 connector->base.id, connector->name,
8777 encoder->base.id, encoder->name);
8778
8779 if (old->load_detect_temp) {
8780 to_intel_connector(connector)->new_encoder = NULL;
8781 intel_encoder->new_crtc = NULL;
8782 intel_crtc->new_enabled = false;
8783 intel_crtc->new_config = NULL;
8784 intel_set_mode(crtc, NULL, 0, 0, NULL);
8785
8786 if (old->release_fb) {
8787 drm_framebuffer_unregister_private(old->release_fb);
8788 drm_framebuffer_unreference(old->release_fb);
8789 }
8790
8791 return;
8792 }
8793
8794 /* Switch crtc and encoder back off if necessary */
8795 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8796 connector->funcs->dpms(connector, old->dpms_mode);
8797 }
8798
8799 static int i9xx_pll_refclk(struct drm_device *dev,
8800 const struct intel_crtc_config *pipe_config)
8801 {
8802 struct drm_i915_private *dev_priv = dev->dev_private;
8803 u32 dpll = pipe_config->dpll_hw_state.dpll;
8804
8805 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8806 return dev_priv->vbt.lvds_ssc_freq;
8807 else if (HAS_PCH_SPLIT(dev))
8808 return 120000;
8809 else if (!IS_GEN2(dev))
8810 return 96000;
8811 else
8812 return 48000;
8813 }
8814
8815 /* Returns the clock of the currently programmed mode of the given pipe. */
8816 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8817 struct intel_crtc_config *pipe_config)
8818 {
8819 struct drm_device *dev = crtc->base.dev;
8820 struct drm_i915_private *dev_priv = dev->dev_private;
8821 int pipe = pipe_config->cpu_transcoder;
8822 u32 dpll = pipe_config->dpll_hw_state.dpll;
8823 u32 fp;
8824 intel_clock_t clock;
8825 int refclk = i9xx_pll_refclk(dev, pipe_config);
8826
8827 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8828 fp = pipe_config->dpll_hw_state.fp0;
8829 else
8830 fp = pipe_config->dpll_hw_state.fp1;
8831
8832 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8833 if (IS_PINEVIEW(dev)) {
8834 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8835 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8836 } else {
8837 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8838 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8839 }
8840
8841 if (!IS_GEN2(dev)) {
8842 if (IS_PINEVIEW(dev))
8843 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8844 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8845 else
8846 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8847 DPLL_FPA01_P1_POST_DIV_SHIFT);
8848
8849 switch (dpll & DPLL_MODE_MASK) {
8850 case DPLLB_MODE_DAC_SERIAL:
8851 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8852 5 : 10;
8853 break;
8854 case DPLLB_MODE_LVDS:
8855 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8856 7 : 14;
8857 break;
8858 default:
8859 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8860 "mode\n", (int)(dpll & DPLL_MODE_MASK));
8861 return;
8862 }
8863
8864 if (IS_PINEVIEW(dev))
8865 pineview_clock(refclk, &clock);
8866 else
8867 i9xx_clock(refclk, &clock);
8868 } else {
8869 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8870 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8871
8872 if (is_lvds) {
8873 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8874 DPLL_FPA01_P1_POST_DIV_SHIFT);
8875
8876 if (lvds & LVDS_CLKB_POWER_UP)
8877 clock.p2 = 7;
8878 else
8879 clock.p2 = 14;
8880 } else {
8881 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8882 clock.p1 = 2;
8883 else {
8884 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8885 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8886 }
8887 if (dpll & PLL_P2_DIVIDE_BY_4)
8888 clock.p2 = 4;
8889 else
8890 clock.p2 = 2;
8891 }
8892
8893 i9xx_clock(refclk, &clock);
8894 }
8895
8896 /*
8897 * This value includes pixel_multiplier. We will use
8898 * port_clock to compute adjusted_mode.crtc_clock in the
8899 * encoder's get_config() function.
8900 */
8901 pipe_config->port_clock = clock.dot;
8902 }
8903
8904 int intel_dotclock_calculate(int link_freq,
8905 const struct intel_link_m_n *m_n)
8906 {
8907 /*
8908 * The calculation for the data clock is:
8909 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8910 * But we want to avoid losing precison if possible, so:
8911 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8912 *
8913 * and the link clock is simpler:
8914 * link_clock = (m * link_clock) / n
8915 */
8916
8917 if (!m_n->link_n)
8918 return 0;
8919
8920 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8921 }
8922
8923 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8924 struct intel_crtc_config *pipe_config)
8925 {
8926 struct drm_device *dev = crtc->base.dev;
8927
8928 /* read out port_clock from the DPLL */
8929 i9xx_crtc_clock_get(crtc, pipe_config);
8930
8931 /*
8932 * This value does not include pixel_multiplier.
8933 * We will check that port_clock and adjusted_mode.crtc_clock
8934 * agree once we know their relationship in the encoder's
8935 * get_config() function.
8936 */
8937 pipe_config->adjusted_mode.crtc_clock =
8938 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8939 &pipe_config->fdi_m_n);
8940 }
8941
8942 /** Returns the currently programmed mode of the given pipe. */
8943 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8944 struct drm_crtc *crtc)
8945 {
8946 struct drm_i915_private *dev_priv = dev->dev_private;
8947 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8948 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8949 struct drm_display_mode *mode;
8950 struct intel_crtc_config pipe_config;
8951 int htot = I915_READ(HTOTAL(cpu_transcoder));
8952 int hsync = I915_READ(HSYNC(cpu_transcoder));
8953 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8954 int vsync = I915_READ(VSYNC(cpu_transcoder));
8955 enum pipe pipe = intel_crtc->pipe;
8956
8957 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8958 if (!mode)
8959 return NULL;
8960
8961 /*
8962 * Construct a pipe_config sufficient for getting the clock info
8963 * back out of crtc_clock_get.
8964 *
8965 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8966 * to use a real value here instead.
8967 */
8968 pipe_config.cpu_transcoder = (enum transcoder) pipe;
8969 pipe_config.pixel_multiplier = 1;
8970 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8971 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8972 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8973 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8974
8975 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8976 mode->hdisplay = (htot & 0xffff) + 1;
8977 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8978 mode->hsync_start = (hsync & 0xffff) + 1;
8979 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8980 mode->vdisplay = (vtot & 0xffff) + 1;
8981 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8982 mode->vsync_start = (vsync & 0xffff) + 1;
8983 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8984
8985 drm_mode_set_name(mode);
8986
8987 return mode;
8988 }
8989
8990 static void intel_increase_pllclock(struct drm_device *dev,
8991 enum pipe pipe)
8992 {
8993 struct drm_i915_private *dev_priv = dev->dev_private;
8994 int dpll_reg = DPLL(pipe);
8995 int dpll;
8996
8997 if (!HAS_GMCH_DISPLAY(dev))
8998 return;
8999
9000 if (!dev_priv->lvds_downclock_avail)
9001 return;
9002
9003 dpll = I915_READ(dpll_reg);
9004 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
9005 DRM_DEBUG_DRIVER("upclocking LVDS\n");
9006
9007 assert_panel_unlocked(dev_priv, pipe);
9008
9009 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
9010 I915_WRITE(dpll_reg, dpll);
9011 intel_wait_for_vblank(dev, pipe);
9012
9013 dpll = I915_READ(dpll_reg);
9014 if (dpll & DISPLAY_RATE_SELECT_FPA1)
9015 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
9016 }
9017 }
9018
9019 static void intel_decrease_pllclock(struct drm_crtc *crtc)
9020 {
9021 struct drm_device *dev = crtc->dev;
9022 struct drm_i915_private *dev_priv = dev->dev_private;
9023 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9024
9025 if (!HAS_GMCH_DISPLAY(dev))
9026 return;
9027
9028 if (!dev_priv->lvds_downclock_avail)
9029 return;
9030
9031 /*
9032 * Since this is called by a timer, we should never get here in
9033 * the manual case.
9034 */
9035 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
9036 int pipe = intel_crtc->pipe;
9037 int dpll_reg = DPLL(pipe);
9038 int dpll;
9039
9040 DRM_DEBUG_DRIVER("downclocking LVDS\n");
9041
9042 assert_panel_unlocked(dev_priv, pipe);
9043
9044 dpll = I915_READ(dpll_reg);
9045 dpll |= DISPLAY_RATE_SELECT_FPA1;
9046 I915_WRITE(dpll_reg, dpll);
9047 intel_wait_for_vblank(dev, pipe);
9048 dpll = I915_READ(dpll_reg);
9049 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
9050 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
9051 }
9052
9053 }
9054
9055 void intel_mark_busy(struct drm_device *dev)
9056 {
9057 struct drm_i915_private *dev_priv = dev->dev_private;
9058
9059 if (dev_priv->mm.busy)
9060 return;
9061
9062 intel_runtime_pm_get(dev_priv);
9063 i915_update_gfx_val(dev_priv);
9064 dev_priv->mm.busy = true;
9065 }
9066
9067 void intel_mark_idle(struct drm_device *dev)
9068 {
9069 struct drm_i915_private *dev_priv = dev->dev_private;
9070 struct drm_crtc *crtc;
9071
9072 if (!dev_priv->mm.busy)
9073 return;
9074
9075 dev_priv->mm.busy = false;
9076
9077 if (!i915.powersave)
9078 goto out;
9079
9080 for_each_crtc(dev, crtc) {
9081 if (!crtc->primary->fb)
9082 continue;
9083
9084 intel_decrease_pllclock(crtc);
9085 }
9086
9087 if (INTEL_INFO(dev)->gen >= 6)
9088 gen6_rps_idle(dev->dev_private);
9089
9090 out:
9091 intel_runtime_pm_put(dev_priv);
9092 }
9093
9094
9095 /**
9096 * intel_mark_fb_busy - mark given planes as busy
9097 * @dev: DRM device
9098 * @frontbuffer_bits: bits for the affected planes
9099 * @ring: optional ring for asynchronous commands
9100 *
9101 * This function gets called every time the screen contents change. It can be
9102 * used to keep e.g. the update rate at the nominal refresh rate with DRRS.
9103 */
9104 static void intel_mark_fb_busy(struct drm_device *dev,
9105 unsigned frontbuffer_bits,
9106 struct intel_engine_cs *ring)
9107 {
9108 struct drm_i915_private *dev_priv = dev->dev_private;
9109 enum pipe pipe;
9110
9111 if (!i915.powersave)
9112 return;
9113
9114 for_each_pipe(dev_priv, pipe) {
9115 if (!(frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe)))
9116 continue;
9117
9118 intel_increase_pllclock(dev, pipe);
9119 if (ring && intel_fbc_enabled(dev))
9120 ring->fbc_dirty = true;
9121 }
9122 }
9123
9124 /**
9125 * intel_fb_obj_invalidate - invalidate frontbuffer object
9126 * @obj: GEM object to invalidate
9127 * @ring: set for asynchronous rendering
9128 *
9129 * This function gets called every time rendering on the given object starts and
9130 * frontbuffer caching (fbc, low refresh rate for DRRS, panel self refresh) must
9131 * be invalidated. If @ring is non-NULL any subsequent invalidation will be delayed
9132 * until the rendering completes or a flip on this frontbuffer plane is
9133 * scheduled.
9134 */
9135 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
9136 struct intel_engine_cs *ring)
9137 {
9138 struct drm_device *dev = obj->base.dev;
9139 struct drm_i915_private *dev_priv = dev->dev_private;
9140
9141 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
9142
9143 if (!obj->frontbuffer_bits)
9144 return;
9145
9146 if (ring) {
9147 mutex_lock(&dev_priv->fb_tracking.lock);
9148 dev_priv->fb_tracking.busy_bits
9149 |= obj->frontbuffer_bits;
9150 dev_priv->fb_tracking.flip_bits
9151 &= ~obj->frontbuffer_bits;
9152 mutex_unlock(&dev_priv->fb_tracking.lock);
9153 }
9154
9155 intel_mark_fb_busy(dev, obj->frontbuffer_bits, ring);
9156
9157 intel_edp_psr_invalidate(dev, obj->frontbuffer_bits);
9158 }
9159
9160 /**
9161 * intel_frontbuffer_flush - flush frontbuffer
9162 * @dev: DRM device
9163 * @frontbuffer_bits: frontbuffer plane tracking bits
9164 *
9165 * This function gets called every time rendering on the given planes has
9166 * completed and frontbuffer caching can be started again. Flushes will get
9167 * delayed if they're blocked by some oustanding asynchronous rendering.
9168 *
9169 * Can be called without any locks held.
9170 */
9171 void intel_frontbuffer_flush(struct drm_device *dev,
9172 unsigned frontbuffer_bits)
9173 {
9174 struct drm_i915_private *dev_priv = dev->dev_private;
9175
9176 /* Delay flushing when rings are still busy.*/
9177 mutex_lock(&dev_priv->fb_tracking.lock);
9178 frontbuffer_bits &= ~dev_priv->fb_tracking.busy_bits;
9179 mutex_unlock(&dev_priv->fb_tracking.lock);
9180
9181 intel_mark_fb_busy(dev, frontbuffer_bits, NULL);
9182
9183 intel_edp_psr_flush(dev, frontbuffer_bits);
9184
9185 /*
9186 * FIXME: Unconditional fbc flushing here is a rather gross hack and
9187 * needs to be reworked into a proper frontbuffer tracking scheme like
9188 * psr employs.
9189 */
9190 if (IS_BROADWELL(dev))
9191 gen8_fbc_sw_flush(dev, FBC_REND_CACHE_CLEAN);
9192 }
9193
9194 /**
9195 * intel_fb_obj_flush - flush frontbuffer object
9196 * @obj: GEM object to flush
9197 * @retire: set when retiring asynchronous rendering
9198 *
9199 * This function gets called every time rendering on the given object has
9200 * completed and frontbuffer caching can be started again. If @retire is true
9201 * then any delayed flushes will be unblocked.
9202 */
9203 void intel_fb_obj_flush(struct drm_i915_gem_object *obj,
9204 bool retire)
9205 {
9206 struct drm_device *dev = obj->base.dev;
9207 struct drm_i915_private *dev_priv = dev->dev_private;
9208 unsigned frontbuffer_bits;
9209
9210 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
9211
9212 if (!obj->frontbuffer_bits)
9213 return;
9214
9215 frontbuffer_bits = obj->frontbuffer_bits;
9216
9217 if (retire) {
9218 mutex_lock(&dev_priv->fb_tracking.lock);
9219 /* Filter out new bits since rendering started. */
9220 frontbuffer_bits &= dev_priv->fb_tracking.busy_bits;
9221
9222 dev_priv->fb_tracking.busy_bits &= ~frontbuffer_bits;
9223 mutex_unlock(&dev_priv->fb_tracking.lock);
9224 }
9225
9226 intel_frontbuffer_flush(dev, frontbuffer_bits);
9227 }
9228
9229 /**
9230 * intel_frontbuffer_flip_prepare - prepare asnychronous frontbuffer flip
9231 * @dev: DRM device
9232 * @frontbuffer_bits: frontbuffer plane tracking bits
9233 *
9234 * This function gets called after scheduling a flip on @obj. The actual
9235 * frontbuffer flushing will be delayed until completion is signalled with
9236 * intel_frontbuffer_flip_complete. If an invalidate happens in between this
9237 * flush will be cancelled.
9238 *
9239 * Can be called without any locks held.
9240 */
9241 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
9242 unsigned frontbuffer_bits)
9243 {
9244 struct drm_i915_private *dev_priv = dev->dev_private;
9245
9246 mutex_lock(&dev_priv->fb_tracking.lock);
9247 dev_priv->fb_tracking.flip_bits
9248 |= frontbuffer_bits;
9249 mutex_unlock(&dev_priv->fb_tracking.lock);
9250 }
9251
9252 /**
9253 * intel_frontbuffer_flip_complete - complete asynchronous frontbuffer flush
9254 * @dev: DRM device
9255 * @frontbuffer_bits: frontbuffer plane tracking bits
9256 *
9257 * This function gets called after the flip has been latched and will complete
9258 * on the next vblank. It will execute the fush if it hasn't been cancalled yet.
9259 *
9260 * Can be called without any locks held.
9261 */
9262 void intel_frontbuffer_flip_complete(struct drm_device *dev,
9263 unsigned frontbuffer_bits)
9264 {
9265 struct drm_i915_private *dev_priv = dev->dev_private;
9266
9267 mutex_lock(&dev_priv->fb_tracking.lock);
9268 /* Mask any cancelled flips. */
9269 frontbuffer_bits &= dev_priv->fb_tracking.flip_bits;
9270 dev_priv->fb_tracking.flip_bits &= ~frontbuffer_bits;
9271 mutex_unlock(&dev_priv->fb_tracking.lock);
9272
9273 intel_frontbuffer_flush(dev, frontbuffer_bits);
9274 }
9275
9276 static void intel_crtc_destroy(struct drm_crtc *crtc)
9277 {
9278 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9279 struct drm_device *dev = crtc->dev;
9280 struct intel_unpin_work *work;
9281
9282 spin_lock_irq(&dev->event_lock);
9283 work = intel_crtc->unpin_work;
9284 intel_crtc->unpin_work = NULL;
9285 spin_unlock_irq(&dev->event_lock);
9286
9287 if (work) {
9288 cancel_work_sync(&work->work);
9289 kfree(work);
9290 }
9291
9292 drm_crtc_cleanup(crtc);
9293
9294 kfree(intel_crtc);
9295 }
9296
9297 static void intel_unpin_work_fn(struct work_struct *__work)
9298 {
9299 struct intel_unpin_work *work =
9300 container_of(__work, struct intel_unpin_work, work);
9301 struct drm_device *dev = work->crtc->dev;
9302 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9303
9304 mutex_lock(&dev->struct_mutex);
9305 intel_unpin_fb_obj(work->old_fb_obj);
9306 drm_gem_object_unreference(&work->pending_flip_obj->base);
9307 drm_gem_object_unreference(&work->old_fb_obj->base);
9308
9309 intel_update_fbc(dev);
9310 mutex_unlock(&dev->struct_mutex);
9311
9312 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9313
9314 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9315 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9316
9317 kfree(work);
9318 }
9319
9320 static void do_intel_finish_page_flip(struct drm_device *dev,
9321 struct drm_crtc *crtc)
9322 {
9323 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9324 struct intel_unpin_work *work;
9325 unsigned long flags;
9326
9327 /* Ignore early vblank irqs */
9328 if (intel_crtc == NULL)
9329 return;
9330
9331 spin_lock_irqsave(&dev->event_lock, flags);
9332 work = intel_crtc->unpin_work;
9333
9334 /* Ensure we don't miss a work->pending update ... */
9335 smp_rmb();
9336
9337 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9338 spin_unlock_irqrestore(&dev->event_lock, flags);
9339 return;
9340 }
9341
9342 page_flip_completed(intel_crtc);
9343
9344 spin_unlock_irqrestore(&dev->event_lock, flags);
9345 }
9346
9347 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9348 {
9349 struct drm_i915_private *dev_priv = dev->dev_private;
9350 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9351
9352 do_intel_finish_page_flip(dev, crtc);
9353 }
9354
9355 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9356 {
9357 struct drm_i915_private *dev_priv = dev->dev_private;
9358 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9359
9360 do_intel_finish_page_flip(dev, crtc);
9361 }
9362
9363 /* Is 'a' after or equal to 'b'? */
9364 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9365 {
9366 return !((a - b) & 0x80000000);
9367 }
9368
9369 static bool page_flip_finished(struct intel_crtc *crtc)
9370 {
9371 struct drm_device *dev = crtc->base.dev;
9372 struct drm_i915_private *dev_priv = dev->dev_private;
9373
9374 /*
9375 * The relevant registers doen't exist on pre-ctg.
9376 * As the flip done interrupt doesn't trigger for mmio
9377 * flips on gmch platforms, a flip count check isn't
9378 * really needed there. But since ctg has the registers,
9379 * include it in the check anyway.
9380 */
9381 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9382 return true;
9383
9384 /*
9385 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9386 * used the same base address. In that case the mmio flip might
9387 * have completed, but the CS hasn't even executed the flip yet.
9388 *
9389 * A flip count check isn't enough as the CS might have updated
9390 * the base address just after start of vblank, but before we
9391 * managed to process the interrupt. This means we'd complete the
9392 * CS flip too soon.
9393 *
9394 * Combining both checks should get us a good enough result. It may
9395 * still happen that the CS flip has been executed, but has not
9396 * yet actually completed. But in case the base address is the same
9397 * anyway, we don't really care.
9398 */
9399 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9400 crtc->unpin_work->gtt_offset &&
9401 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9402 crtc->unpin_work->flip_count);
9403 }
9404
9405 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9406 {
9407 struct drm_i915_private *dev_priv = dev->dev_private;
9408 struct intel_crtc *intel_crtc =
9409 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9410 unsigned long flags;
9411
9412 /* NB: An MMIO update of the plane base pointer will also
9413 * generate a page-flip completion irq, i.e. every modeset
9414 * is also accompanied by a spurious intel_prepare_page_flip().
9415 */
9416 spin_lock_irqsave(&dev->event_lock, flags);
9417 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9418 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9419 spin_unlock_irqrestore(&dev->event_lock, flags);
9420 }
9421
9422 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9423 {
9424 /* Ensure that the work item is consistent when activating it ... */
9425 smp_wmb();
9426 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9427 /* and that it is marked active as soon as the irq could fire. */
9428 smp_wmb();
9429 }
9430
9431 static int intel_gen2_queue_flip(struct drm_device *dev,
9432 struct drm_crtc *crtc,
9433 struct drm_framebuffer *fb,
9434 struct drm_i915_gem_object *obj,
9435 struct intel_engine_cs *ring,
9436 uint32_t flags)
9437 {
9438 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9439 u32 flip_mask;
9440 int ret;
9441
9442 ret = intel_ring_begin(ring, 6);
9443 if (ret)
9444 return ret;
9445
9446 /* Can't queue multiple flips, so wait for the previous
9447 * one to finish before executing the next.
9448 */
9449 if (intel_crtc->plane)
9450 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9451 else
9452 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9453 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9454 intel_ring_emit(ring, MI_NOOP);
9455 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9456 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9457 intel_ring_emit(ring, fb->pitches[0]);
9458 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9459 intel_ring_emit(ring, 0); /* aux display base address, unused */
9460
9461 intel_mark_page_flip_active(intel_crtc);
9462 __intel_ring_advance(ring);
9463 return 0;
9464 }
9465
9466 static int intel_gen3_queue_flip(struct drm_device *dev,
9467 struct drm_crtc *crtc,
9468 struct drm_framebuffer *fb,
9469 struct drm_i915_gem_object *obj,
9470 struct intel_engine_cs *ring,
9471 uint32_t flags)
9472 {
9473 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9474 u32 flip_mask;
9475 int ret;
9476
9477 ret = intel_ring_begin(ring, 6);
9478 if (ret)
9479 return ret;
9480
9481 if (intel_crtc->plane)
9482 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9483 else
9484 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9485 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9486 intel_ring_emit(ring, MI_NOOP);
9487 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9488 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9489 intel_ring_emit(ring, fb->pitches[0]);
9490 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9491 intel_ring_emit(ring, MI_NOOP);
9492
9493 intel_mark_page_flip_active(intel_crtc);
9494 __intel_ring_advance(ring);
9495 return 0;
9496 }
9497
9498 static int intel_gen4_queue_flip(struct drm_device *dev,
9499 struct drm_crtc *crtc,
9500 struct drm_framebuffer *fb,
9501 struct drm_i915_gem_object *obj,
9502 struct intel_engine_cs *ring,
9503 uint32_t flags)
9504 {
9505 struct drm_i915_private *dev_priv = dev->dev_private;
9506 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9507 uint32_t pf, pipesrc;
9508 int ret;
9509
9510 ret = intel_ring_begin(ring, 4);
9511 if (ret)
9512 return ret;
9513
9514 /* i965+ uses the linear or tiled offsets from the
9515 * Display Registers (which do not change across a page-flip)
9516 * so we need only reprogram the base address.
9517 */
9518 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9519 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9520 intel_ring_emit(ring, fb->pitches[0]);
9521 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9522 obj->tiling_mode);
9523
9524 /* XXX Enabling the panel-fitter across page-flip is so far
9525 * untested on non-native modes, so ignore it for now.
9526 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9527 */
9528 pf = 0;
9529 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9530 intel_ring_emit(ring, pf | pipesrc);
9531
9532 intel_mark_page_flip_active(intel_crtc);
9533 __intel_ring_advance(ring);
9534 return 0;
9535 }
9536
9537 static int intel_gen6_queue_flip(struct drm_device *dev,
9538 struct drm_crtc *crtc,
9539 struct drm_framebuffer *fb,
9540 struct drm_i915_gem_object *obj,
9541 struct intel_engine_cs *ring,
9542 uint32_t flags)
9543 {
9544 struct drm_i915_private *dev_priv = dev->dev_private;
9545 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9546 uint32_t pf, pipesrc;
9547 int ret;
9548
9549 ret = intel_ring_begin(ring, 4);
9550 if (ret)
9551 return ret;
9552
9553 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9554 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9555 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9556 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9557
9558 /* Contrary to the suggestions in the documentation,
9559 * "Enable Panel Fitter" does not seem to be required when page
9560 * flipping with a non-native mode, and worse causes a normal
9561 * modeset to fail.
9562 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9563 */
9564 pf = 0;
9565 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9566 intel_ring_emit(ring, pf | pipesrc);
9567
9568 intel_mark_page_flip_active(intel_crtc);
9569 __intel_ring_advance(ring);
9570 return 0;
9571 }
9572
9573 static int intel_gen7_queue_flip(struct drm_device *dev,
9574 struct drm_crtc *crtc,
9575 struct drm_framebuffer *fb,
9576 struct drm_i915_gem_object *obj,
9577 struct intel_engine_cs *ring,
9578 uint32_t flags)
9579 {
9580 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9581 uint32_t plane_bit = 0;
9582 int len, ret;
9583
9584 switch (intel_crtc->plane) {
9585 case PLANE_A:
9586 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9587 break;
9588 case PLANE_B:
9589 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9590 break;
9591 case PLANE_C:
9592 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9593 break;
9594 default:
9595 WARN_ONCE(1, "unknown plane in flip command\n");
9596 return -ENODEV;
9597 }
9598
9599 len = 4;
9600 if (ring->id == RCS) {
9601 len += 6;
9602 /*
9603 * On Gen 8, SRM is now taking an extra dword to accommodate
9604 * 48bits addresses, and we need a NOOP for the batch size to
9605 * stay even.
9606 */
9607 if (IS_GEN8(dev))
9608 len += 2;
9609 }
9610
9611 /*
9612 * BSpec MI_DISPLAY_FLIP for IVB:
9613 * "The full packet must be contained within the same cache line."
9614 *
9615 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9616 * cacheline, if we ever start emitting more commands before
9617 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9618 * then do the cacheline alignment, and finally emit the
9619 * MI_DISPLAY_FLIP.
9620 */
9621 ret = intel_ring_cacheline_align(ring);
9622 if (ret)
9623 return ret;
9624
9625 ret = intel_ring_begin(ring, len);
9626 if (ret)
9627 return ret;
9628
9629 /* Unmask the flip-done completion message. Note that the bspec says that
9630 * we should do this for both the BCS and RCS, and that we must not unmask
9631 * more than one flip event at any time (or ensure that one flip message
9632 * can be sent by waiting for flip-done prior to queueing new flips).
9633 * Experimentation says that BCS works despite DERRMR masking all
9634 * flip-done completion events and that unmasking all planes at once
9635 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9636 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9637 */
9638 if (ring->id == RCS) {
9639 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9640 intel_ring_emit(ring, DERRMR);
9641 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9642 DERRMR_PIPEB_PRI_FLIP_DONE |
9643 DERRMR_PIPEC_PRI_FLIP_DONE));
9644 if (IS_GEN8(dev))
9645 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9646 MI_SRM_LRM_GLOBAL_GTT);
9647 else
9648 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9649 MI_SRM_LRM_GLOBAL_GTT);
9650 intel_ring_emit(ring, DERRMR);
9651 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9652 if (IS_GEN8(dev)) {
9653 intel_ring_emit(ring, 0);
9654 intel_ring_emit(ring, MI_NOOP);
9655 }
9656 }
9657
9658 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9659 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9660 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9661 intel_ring_emit(ring, (MI_NOOP));
9662
9663 intel_mark_page_flip_active(intel_crtc);
9664 __intel_ring_advance(ring);
9665 return 0;
9666 }
9667
9668 static bool use_mmio_flip(struct intel_engine_cs *ring,
9669 struct drm_i915_gem_object *obj)
9670 {
9671 /*
9672 * This is not being used for older platforms, because
9673 * non-availability of flip done interrupt forces us to use
9674 * CS flips. Older platforms derive flip done using some clever
9675 * tricks involving the flip_pending status bits and vblank irqs.
9676 * So using MMIO flips there would disrupt this mechanism.
9677 */
9678
9679 if (ring == NULL)
9680 return true;
9681
9682 if (INTEL_INFO(ring->dev)->gen < 5)
9683 return false;
9684
9685 if (i915.use_mmio_flip < 0)
9686 return false;
9687 else if (i915.use_mmio_flip > 0)
9688 return true;
9689 else if (i915.enable_execlists)
9690 return true;
9691 else
9692 return ring != obj->ring;
9693 }
9694
9695 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9696 {
9697 struct drm_device *dev = intel_crtc->base.dev;
9698 struct drm_i915_private *dev_priv = dev->dev_private;
9699 struct intel_framebuffer *intel_fb =
9700 to_intel_framebuffer(intel_crtc->base.primary->fb);
9701 struct drm_i915_gem_object *obj = intel_fb->obj;
9702 u32 dspcntr;
9703 u32 reg;
9704
9705 intel_mark_page_flip_active(intel_crtc);
9706
9707 reg = DSPCNTR(intel_crtc->plane);
9708 dspcntr = I915_READ(reg);
9709
9710 if (INTEL_INFO(dev)->gen >= 4) {
9711 if (obj->tiling_mode != I915_TILING_NONE)
9712 dspcntr |= DISPPLANE_TILED;
9713 else
9714 dspcntr &= ~DISPPLANE_TILED;
9715 }
9716 I915_WRITE(reg, dspcntr);
9717
9718 I915_WRITE(DSPSURF(intel_crtc->plane),
9719 intel_crtc->unpin_work->gtt_offset);
9720 POSTING_READ(DSPSURF(intel_crtc->plane));
9721 }
9722
9723 static int intel_postpone_flip(struct drm_i915_gem_object *obj)
9724 {
9725 struct intel_engine_cs *ring;
9726 int ret;
9727
9728 lockdep_assert_held(&obj->base.dev->struct_mutex);
9729
9730 if (!obj->last_write_seqno)
9731 return 0;
9732
9733 ring = obj->ring;
9734
9735 if (i915_seqno_passed(ring->get_seqno(ring, true),
9736 obj->last_write_seqno))
9737 return 0;
9738
9739 ret = i915_gem_check_olr(ring, obj->last_write_seqno);
9740 if (ret)
9741 return ret;
9742
9743 if (WARN_ON(!ring->irq_get(ring)))
9744 return 0;
9745
9746 return 1;
9747 }
9748
9749 void intel_notify_mmio_flip(struct intel_engine_cs *ring)
9750 {
9751 struct drm_i915_private *dev_priv = to_i915(ring->dev);
9752 struct intel_crtc *intel_crtc;
9753 unsigned long irq_flags;
9754 u32 seqno;
9755
9756 seqno = ring->get_seqno(ring, false);
9757
9758 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9759 for_each_intel_crtc(ring->dev, intel_crtc) {
9760 struct intel_mmio_flip *mmio_flip;
9761
9762 mmio_flip = &intel_crtc->mmio_flip;
9763 if (mmio_flip->seqno == 0)
9764 continue;
9765
9766 if (ring->id != mmio_flip->ring_id)
9767 continue;
9768
9769 if (i915_seqno_passed(seqno, mmio_flip->seqno)) {
9770 intel_do_mmio_flip(intel_crtc);
9771 mmio_flip->seqno = 0;
9772 ring->irq_put(ring);
9773 }
9774 }
9775 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9776 }
9777
9778 static int intel_queue_mmio_flip(struct drm_device *dev,
9779 struct drm_crtc *crtc,
9780 struct drm_framebuffer *fb,
9781 struct drm_i915_gem_object *obj,
9782 struct intel_engine_cs *ring,
9783 uint32_t flags)
9784 {
9785 struct drm_i915_private *dev_priv = dev->dev_private;
9786 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9787 unsigned long irq_flags;
9788 int ret;
9789
9790 if (WARN_ON(intel_crtc->mmio_flip.seqno))
9791 return -EBUSY;
9792
9793 ret = intel_postpone_flip(obj);
9794 if (ret < 0)
9795 return ret;
9796 if (ret == 0) {
9797 intel_do_mmio_flip(intel_crtc);
9798 return 0;
9799 }
9800
9801 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9802 intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
9803 intel_crtc->mmio_flip.ring_id = obj->ring->id;
9804 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9805
9806 /*
9807 * Double check to catch cases where irq fired before
9808 * mmio flip data was ready
9809 */
9810 intel_notify_mmio_flip(obj->ring);
9811 return 0;
9812 }
9813
9814 static int intel_default_queue_flip(struct drm_device *dev,
9815 struct drm_crtc *crtc,
9816 struct drm_framebuffer *fb,
9817 struct drm_i915_gem_object *obj,
9818 struct intel_engine_cs *ring,
9819 uint32_t flags)
9820 {
9821 return -ENODEV;
9822 }
9823
9824 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9825 struct drm_crtc *crtc)
9826 {
9827 struct drm_i915_private *dev_priv = dev->dev_private;
9828 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9829 struct intel_unpin_work *work = intel_crtc->unpin_work;
9830 u32 addr;
9831
9832 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9833 return true;
9834
9835 if (!work->enable_stall_check)
9836 return false;
9837
9838 if (work->flip_ready_vblank == 0) {
9839 if (work->flip_queued_ring &&
9840 !i915_seqno_passed(work->flip_queued_ring->get_seqno(work->flip_queued_ring, true),
9841 work->flip_queued_seqno))
9842 return false;
9843
9844 work->flip_ready_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9845 }
9846
9847 if (drm_vblank_count(dev, intel_crtc->pipe) - work->flip_ready_vblank < 3)
9848 return false;
9849
9850 /* Potential stall - if we see that the flip has happened,
9851 * assume a missed interrupt. */
9852 if (INTEL_INFO(dev)->gen >= 4)
9853 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9854 else
9855 addr = I915_READ(DSPADDR(intel_crtc->plane));
9856
9857 /* There is a potential issue here with a false positive after a flip
9858 * to the same address. We could address this by checking for a
9859 * non-incrementing frame counter.
9860 */
9861 return addr == work->gtt_offset;
9862 }
9863
9864 void intel_check_page_flip(struct drm_device *dev, int pipe)
9865 {
9866 struct drm_i915_private *dev_priv = dev->dev_private;
9867 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9868 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9869 unsigned long flags;
9870
9871 if (crtc == NULL)
9872 return;
9873
9874 spin_lock_irqsave(&dev->event_lock, flags);
9875 if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9876 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9877 intel_crtc->unpin_work->flip_queued_vblank, drm_vblank_count(dev, pipe));
9878 page_flip_completed(intel_crtc);
9879 }
9880 spin_unlock_irqrestore(&dev->event_lock, flags);
9881 }
9882
9883 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9884 struct drm_framebuffer *fb,
9885 struct drm_pending_vblank_event *event,
9886 uint32_t page_flip_flags)
9887 {
9888 struct drm_device *dev = crtc->dev;
9889 struct drm_i915_private *dev_priv = dev->dev_private;
9890 struct drm_framebuffer *old_fb = crtc->primary->fb;
9891 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9892 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9893 enum pipe pipe = intel_crtc->pipe;
9894 struct intel_unpin_work *work;
9895 struct intel_engine_cs *ring;
9896 int ret;
9897
9898 //trigger software GT busyness calculation
9899 gen8_flip_interrupt(dev);
9900
9901 /*
9902 * drm_mode_page_flip_ioctl() should already catch this, but double
9903 * check to be safe. In the future we may enable pageflipping from
9904 * a disabled primary plane.
9905 */
9906 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9907 return -EBUSY;
9908
9909 /* Can't change pixel format via MI display flips. */
9910 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9911 return -EINVAL;
9912
9913 /*
9914 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9915 * Note that pitch changes could also affect these register.
9916 */
9917 if (INTEL_INFO(dev)->gen > 3 &&
9918 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9919 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9920 return -EINVAL;
9921
9922 if (i915_terminally_wedged(&dev_priv->gpu_error))
9923 goto out_hang;
9924
9925 work = kzalloc(sizeof(*work), GFP_KERNEL);
9926 if (work == NULL)
9927 return -ENOMEM;
9928
9929 work->event = event;
9930 work->crtc = crtc;
9931 work->old_fb_obj = intel_fb_obj(old_fb);
9932 INIT_WORK(&work->work, intel_unpin_work_fn);
9933
9934 ret = drm_crtc_vblank_get(crtc);
9935 if (ret)
9936 goto free_work;
9937
9938 /* We borrow the event spin lock for protecting unpin_work */
9939 spin_lock_irq(&dev->event_lock);
9940 if (intel_crtc->unpin_work) {
9941 /* Before declaring the flip queue wedged, check if
9942 * the hardware completed the operation behind our backs.
9943 */
9944 if (__intel_pageflip_stall_check(dev, crtc)) {
9945 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9946 page_flip_completed(intel_crtc);
9947 } else {
9948 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9949 spin_unlock_irq(&dev->event_lock);
9950
9951 drm_crtc_vblank_put(crtc);
9952 kfree(work);
9953 return -EBUSY;
9954 }
9955 }
9956 intel_crtc->unpin_work = work;
9957 spin_unlock_irq(&dev->event_lock);
9958
9959 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9960 flush_workqueue(dev_priv->wq);
9961
9962 ret = i915_mutex_lock_interruptible(dev);
9963 if (ret)
9964 goto cleanup;
9965
9966 /* Reference the objects for the scheduled work. */
9967 drm_gem_object_reference(&work->old_fb_obj->base);
9968 drm_gem_object_reference(&obj->base);
9969
9970 crtc->primary->fb = fb;
9971
9972 work->pending_flip_obj = obj;
9973
9974 atomic_inc(&intel_crtc->unpin_work_count);
9975 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9976
9977 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9978 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9979
9980 if (IS_VALLEYVIEW(dev)) {
9981 ring = &dev_priv->ring[BCS];
9982 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9983 /* vlv: DISPLAY_FLIP fails to change tiling */
9984 ring = NULL;
9985 } else if (IS_IVYBRIDGE(dev)) {
9986 ring = &dev_priv->ring[BCS];
9987 } else if (INTEL_INFO(dev)->gen >= 7) {
9988 ring = obj->ring;
9989 if (ring == NULL || ring->id != RCS)
9990 ring = &dev_priv->ring[BCS];
9991 } else {
9992 ring = &dev_priv->ring[RCS];
9993 }
9994
9995 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9996 if (ret)
9997 goto cleanup_pending;
9998
9999 work->gtt_offset =
10000 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
10001
10002 if (use_mmio_flip(ring, obj)) {
10003 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
10004 page_flip_flags);
10005 if (ret)
10006 goto cleanup_unpin;
10007
10008 work->flip_queued_seqno = obj->last_write_seqno;
10009 work->flip_queued_ring = obj->ring;
10010 } else {
10011 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
10012 page_flip_flags);
10013 if (ret)
10014 goto cleanup_unpin;
10015
10016 work->flip_queued_seqno = intel_ring_get_seqno(ring);
10017 work->flip_queued_ring = ring;
10018 }
10019
10020 work->flip_queued_vblank = drm_vblank_count(dev, intel_crtc->pipe);
10021 work->enable_stall_check = true;
10022
10023 i915_gem_track_fb(work->old_fb_obj, obj,
10024 INTEL_FRONTBUFFER_PRIMARY(pipe));
10025
10026 intel_disable_fbc(dev);
10027 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
10028 mutex_unlock(&dev->struct_mutex);
10029
10030 trace_i915_flip_request(intel_crtc->plane, obj);
10031
10032 return 0;
10033
10034 cleanup_unpin:
10035 intel_unpin_fb_obj(obj);
10036 cleanup_pending:
10037 atomic_dec(&intel_crtc->unpin_work_count);
10038 crtc->primary->fb = old_fb;
10039 drm_gem_object_unreference(&work->old_fb_obj->base);
10040 drm_gem_object_unreference(&obj->base);
10041 mutex_unlock(&dev->struct_mutex);
10042
10043 cleanup:
10044 spin_lock_irq(&dev->event_lock);
10045 intel_crtc->unpin_work = NULL;
10046 spin_unlock_irq(&dev->event_lock);
10047
10048 drm_crtc_vblank_put(crtc);
10049 free_work:
10050 kfree(work);
10051
10052 if (ret == -EIO) {
10053 out_hang:
10054 intel_crtc_wait_for_pending_flips(crtc);
10055 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
10056 if (ret == 0 && event) {
10057 spin_lock_irq(&dev->event_lock);
10058 drm_send_vblank_event(dev, pipe, event);
10059 spin_unlock_irq(&dev->event_lock);
10060 }
10061 }
10062 return ret;
10063 }
10064
10065 static struct drm_crtc_helper_funcs intel_helper_funcs = {
10066 .mode_set_base_atomic = intel_pipe_set_base_atomic,
10067 .load_lut = intel_crtc_load_lut,
10068 };
10069
10070 /**
10071 * intel_modeset_update_staged_output_state
10072 *
10073 * Updates the staged output configuration state, e.g. after we've read out the
10074 * current hw state.
10075 */
10076 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
10077 {
10078 struct intel_crtc *crtc;
10079 struct intel_encoder *encoder;
10080 struct intel_connector *connector;
10081
10082 list_for_each_entry(connector, &dev->mode_config.connector_list,
10083 base.head) {
10084 connector->new_encoder =
10085 to_intel_encoder(connector->base.encoder);
10086 }
10087
10088 for_each_intel_encoder(dev, encoder) {
10089 encoder->new_crtc =
10090 to_intel_crtc(encoder->base.crtc);
10091 }
10092
10093 for_each_intel_crtc(dev, crtc) {
10094 crtc->new_enabled = crtc->base.enabled;
10095
10096 if (crtc->new_enabled)
10097 crtc->new_config = &crtc->config;
10098 else
10099 crtc->new_config = NULL;
10100 }
10101 }
10102
10103 /**
10104 * intel_modeset_commit_output_state
10105 *
10106 * This function copies the stage display pipe configuration to the real one.
10107 */
10108 static void intel_modeset_commit_output_state(struct drm_device *dev)
10109 {
10110 struct intel_crtc *crtc;
10111 struct intel_encoder *encoder;
10112 struct intel_connector *connector;
10113
10114 list_for_each_entry(connector, &dev->mode_config.connector_list,
10115 base.head) {
10116 connector->base.encoder = &connector->new_encoder->base;
10117 }
10118
10119 for_each_intel_encoder(dev, encoder) {
10120 encoder->base.crtc = &encoder->new_crtc->base;
10121 }
10122
10123 for_each_intel_crtc(dev, crtc) {
10124 crtc->base.enabled = crtc->new_enabled;
10125 }
10126 }
10127
10128 static void
10129 connected_sink_compute_bpp(struct intel_connector *connector,
10130 struct intel_crtc_config *pipe_config)
10131 {
10132 int bpp = pipe_config->pipe_bpp;
10133
10134 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10135 connector->base.base.id,
10136 connector->base.name);
10137
10138 /* Don't use an invalid EDID bpc value */
10139 if (connector->base.display_info.bpc &&
10140 connector->base.display_info.bpc * 3 < bpp) {
10141 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10142 bpp, connector->base.display_info.bpc*3);
10143 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
10144 }
10145
10146 /* Clamp bpp to 8 on screens without EDID 1.4 */
10147 if (connector->base.display_info.bpc == 0 && bpp > 24) {
10148 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10149 bpp);
10150 pipe_config->pipe_bpp = 24;
10151 }
10152 }
10153
10154 static int
10155 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10156 struct drm_framebuffer *fb,
10157 struct intel_crtc_config *pipe_config)
10158 {
10159 struct drm_device *dev = crtc->base.dev;
10160 struct intel_connector *connector;
10161 int bpp;
10162
10163 switch (fb->pixel_format) {
10164 case DRM_FORMAT_C8:
10165 bpp = 8*3; /* since we go through a colormap */
10166 break;
10167 case DRM_FORMAT_XRGB1555:
10168 case DRM_FORMAT_ARGB1555:
10169 /* checked in intel_framebuffer_init already */
10170 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10171 return -EINVAL;
10172 case DRM_FORMAT_RGB565:
10173 bpp = 6*3; /* min is 18bpp */
10174 break;
10175 case DRM_FORMAT_XBGR8888:
10176 case DRM_FORMAT_ABGR8888:
10177 /* checked in intel_framebuffer_init already */
10178 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10179 return -EINVAL;
10180 case DRM_FORMAT_XRGB8888:
10181 case DRM_FORMAT_ARGB8888:
10182 bpp = 8*3;
10183 break;
10184 case DRM_FORMAT_XRGB2101010:
10185 case DRM_FORMAT_ARGB2101010:
10186 case DRM_FORMAT_XBGR2101010:
10187 case DRM_FORMAT_ABGR2101010:
10188 /* checked in intel_framebuffer_init already */
10189 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10190 return -EINVAL;
10191 bpp = 10*3;
10192 break;
10193 /* TODO: gen4+ supports 16 bpc floating point, too. */
10194 default:
10195 DRM_DEBUG_KMS("unsupported depth\n");
10196 return -EINVAL;
10197 }
10198
10199 pipe_config->pipe_bpp = bpp;
10200
10201 /* Clamp display bpp to EDID value */
10202 list_for_each_entry(connector, &dev->mode_config.connector_list,
10203 base.head) {
10204 if (!connector->new_encoder ||
10205 connector->new_encoder->new_crtc != crtc)
10206 continue;
10207
10208 connected_sink_compute_bpp(connector, pipe_config);
10209 }
10210
10211 return bpp;
10212 }
10213
10214 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10215 {
10216 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10217 "type: 0x%x flags: 0x%x\n",
10218 mode->crtc_clock,
10219 mode->crtc_hdisplay, mode->crtc_hsync_start,
10220 mode->crtc_hsync_end, mode->crtc_htotal,
10221 mode->crtc_vdisplay, mode->crtc_vsync_start,
10222 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10223 }
10224
10225 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10226 struct intel_crtc_config *pipe_config,
10227 const char *context)
10228 {
10229 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10230 context, pipe_name(crtc->pipe));
10231
10232 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10233 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10234 pipe_config->pipe_bpp, pipe_config->dither);
10235 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10236 pipe_config->has_pch_encoder,
10237 pipe_config->fdi_lanes,
10238 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10239 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10240 pipe_config->fdi_m_n.tu);
10241 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10242 pipe_config->has_dp_encoder,
10243 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10244 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10245 pipe_config->dp_m_n.tu);
10246
10247 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10248 pipe_config->has_dp_encoder,
10249 pipe_config->dp_m2_n2.gmch_m,
10250 pipe_config->dp_m2_n2.gmch_n,
10251 pipe_config->dp_m2_n2.link_m,
10252 pipe_config->dp_m2_n2.link_n,
10253 pipe_config->dp_m2_n2.tu);
10254
10255 DRM_DEBUG_KMS("requested mode:\n");
10256 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
10257 DRM_DEBUG_KMS("adjusted mode:\n");
10258 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
10259 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
10260 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10261 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10262 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10263 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10264 pipe_config->gmch_pfit.control,
10265 pipe_config->gmch_pfit.pgm_ratios,
10266 pipe_config->gmch_pfit.lvds_border_bits);
10267 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10268 pipe_config->pch_pfit.pos,
10269 pipe_config->pch_pfit.size,
10270 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10271 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10272 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10273 }
10274
10275 static bool encoders_cloneable(const struct intel_encoder *a,
10276 const struct intel_encoder *b)
10277 {
10278 /* masks could be asymmetric, so check both ways */
10279 return a == b || (a->cloneable & (1 << b->type) &&
10280 b->cloneable & (1 << a->type));
10281 }
10282
10283 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10284 struct intel_encoder *encoder)
10285 {
10286 struct drm_device *dev = crtc->base.dev;
10287 struct intel_encoder *source_encoder;
10288
10289 for_each_intel_encoder(dev, source_encoder) {
10290 if (source_encoder->new_crtc != crtc)
10291 continue;
10292
10293 if (!encoders_cloneable(encoder, source_encoder))
10294 return false;
10295 }
10296
10297 return true;
10298 }
10299
10300 static bool check_encoder_cloning(struct intel_crtc *crtc)
10301 {
10302 struct drm_device *dev = crtc->base.dev;
10303 struct intel_encoder *encoder;
10304
10305 for_each_intel_encoder(dev, encoder) {
10306 if (encoder->new_crtc != crtc)
10307 continue;
10308
10309 if (!check_single_encoder_cloning(crtc, encoder))
10310 return false;
10311 }
10312
10313 return true;
10314 }
10315
10316 static struct intel_crtc_config *
10317 intel_modeset_pipe_config(struct drm_crtc *crtc,
10318 struct drm_framebuffer *fb,
10319 struct drm_display_mode *mode)
10320 {
10321 struct drm_device *dev = crtc->dev;
10322 struct intel_encoder *encoder;
10323 struct intel_crtc_config *pipe_config;
10324 int plane_bpp, ret = -EINVAL;
10325 bool retry = true;
10326
10327 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10328 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10329 return ERR_PTR(-EINVAL);
10330 }
10331
10332 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10333 if (!pipe_config)
10334 return ERR_PTR(-ENOMEM);
10335
10336 drm_mode_copy(&pipe_config->adjusted_mode, mode);
10337 drm_mode_copy(&pipe_config->requested_mode, mode);
10338
10339 pipe_config->cpu_transcoder =
10340 (enum transcoder) to_intel_crtc(crtc)->pipe;
10341 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10342
10343 /*
10344 * Sanitize sync polarity flags based on requested ones. If neither
10345 * positive or negative polarity is requested, treat this as meaning
10346 * negative polarity.
10347 */
10348 if (!(pipe_config->adjusted_mode.flags &
10349 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10350 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10351
10352 if (!(pipe_config->adjusted_mode.flags &
10353 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10354 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10355
10356 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10357 * plane pixel format and any sink constraints into account. Returns the
10358 * source plane bpp so that dithering can be selected on mismatches
10359 * after encoders and crtc also have had their say. */
10360 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10361 fb, pipe_config);
10362 if (plane_bpp < 0)
10363 goto fail;
10364
10365 /*
10366 * Determine the real pipe dimensions. Note that stereo modes can
10367 * increase the actual pipe size due to the frame doubling and
10368 * insertion of additional space for blanks between the frame. This
10369 * is stored in the crtc timings. We use the requested mode to do this
10370 * computation to clearly distinguish it from the adjusted mode, which
10371 * can be changed by the connectors in the below retry loop.
10372 */
10373 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
10374 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
10375 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
10376
10377 encoder_retry:
10378 /* Ensure the port clock defaults are reset when retrying. */
10379 pipe_config->port_clock = 0;
10380 pipe_config->pixel_multiplier = 1;
10381
10382 /* Fill in default crtc timings, allow encoders to overwrite them. */
10383 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
10384
10385 /* Pass our mode to the connectors and the CRTC to give them a chance to
10386 * adjust it according to limitations or connector properties, and also
10387 * a chance to reject the mode entirely.
10388 */
10389 for_each_intel_encoder(dev, encoder) {
10390
10391 if (&encoder->new_crtc->base != crtc)
10392 continue;
10393
10394 if (!(encoder->compute_config(encoder, pipe_config))) {
10395 DRM_DEBUG_KMS("Encoder config failure\n");
10396 goto fail;
10397 }
10398 }
10399
10400 /* Set default port clock if not overwritten by the encoder. Needs to be
10401 * done afterwards in case the encoder adjusts the mode. */
10402 if (!pipe_config->port_clock)
10403 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10404 * pipe_config->pixel_multiplier;
10405
10406 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10407 if (ret < 0) {
10408 DRM_DEBUG_KMS("CRTC fixup failed\n");
10409 goto fail;
10410 }
10411
10412 if (ret == RETRY) {
10413 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10414 ret = -EINVAL;
10415 goto fail;
10416 }
10417
10418 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10419 retry = false;
10420 goto encoder_retry;
10421 }
10422
10423 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10424 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10425 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10426
10427 return pipe_config;
10428 fail:
10429 kfree(pipe_config);
10430 return ERR_PTR(ret);
10431 }
10432
10433 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10434 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10435 static void
10436 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10437 unsigned *prepare_pipes, unsigned *disable_pipes)
10438 {
10439 struct intel_crtc *intel_crtc;
10440 struct drm_device *dev = crtc->dev;
10441 struct intel_encoder *encoder;
10442 struct intel_connector *connector;
10443 struct drm_crtc *tmp_crtc;
10444
10445 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10446
10447 /* Check which crtcs have changed outputs connected to them, these need
10448 * to be part of the prepare_pipes mask. We don't (yet) support global
10449 * modeset across multiple crtcs, so modeset_pipes will only have one
10450 * bit set at most. */
10451 list_for_each_entry(connector, &dev->mode_config.connector_list,
10452 base.head) {
10453 if (connector->base.encoder == &connector->new_encoder->base)
10454 continue;
10455
10456 if (connector->base.encoder) {
10457 tmp_crtc = connector->base.encoder->crtc;
10458
10459 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10460 }
10461
10462 if (connector->new_encoder)
10463 *prepare_pipes |=
10464 1 << connector->new_encoder->new_crtc->pipe;
10465 }
10466
10467 for_each_intel_encoder(dev, encoder) {
10468 if (encoder->base.crtc == &encoder->new_crtc->base)
10469 continue;
10470
10471 if (encoder->base.crtc) {
10472 tmp_crtc = encoder->base.crtc;
10473
10474 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10475 }
10476
10477 if (encoder->new_crtc)
10478 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10479 }
10480
10481 /* Check for pipes that will be enabled/disabled ... */
10482 for_each_intel_crtc(dev, intel_crtc) {
10483 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10484 continue;
10485
10486 if (!intel_crtc->new_enabled)
10487 *disable_pipes |= 1 << intel_crtc->pipe;
10488 else
10489 *prepare_pipes |= 1 << intel_crtc->pipe;
10490 }
10491
10492
10493 /* set_mode is also used to update properties on life display pipes. */
10494 intel_crtc = to_intel_crtc(crtc);
10495 if (intel_crtc->new_enabled)
10496 *prepare_pipes |= 1 << intel_crtc->pipe;
10497
10498 /*
10499 * For simplicity do a full modeset on any pipe where the output routing
10500 * changed. We could be more clever, but that would require us to be
10501 * more careful with calling the relevant encoder->mode_set functions.
10502 */
10503 if (*prepare_pipes)
10504 *modeset_pipes = *prepare_pipes;
10505
10506 /* ... and mask these out. */
10507 *modeset_pipes &= ~(*disable_pipes);
10508 *prepare_pipes &= ~(*disable_pipes);
10509
10510 /*
10511 * HACK: We don't (yet) fully support global modesets. intel_set_config
10512 * obies this rule, but the modeset restore mode of
10513 * intel_modeset_setup_hw_state does not.
10514 */
10515 *modeset_pipes &= 1 << intel_crtc->pipe;
10516 *prepare_pipes &= 1 << intel_crtc->pipe;
10517
10518 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10519 *modeset_pipes, *prepare_pipes, *disable_pipes);
10520 }
10521
10522 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10523 {
10524 struct drm_encoder *encoder;
10525 struct drm_device *dev = crtc->dev;
10526
10527 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10528 if (encoder->crtc == crtc)
10529 return true;
10530
10531 return false;
10532 }
10533
10534 static void
10535 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10536 {
10537 struct intel_encoder *intel_encoder;
10538 struct intel_crtc *intel_crtc;
10539 struct drm_connector *connector;
10540
10541 for_each_intel_encoder(dev, intel_encoder) {
10542 if (!intel_encoder->base.crtc)
10543 continue;
10544
10545 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10546
10547 if (prepare_pipes & (1 << intel_crtc->pipe))
10548 intel_encoder->connectors_active = false;
10549 }
10550
10551 intel_modeset_commit_output_state(dev);
10552
10553 /* Double check state. */
10554 for_each_intel_crtc(dev, intel_crtc) {
10555 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10556 WARN_ON(intel_crtc->new_config &&
10557 intel_crtc->new_config != &intel_crtc->config);
10558 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10559 }
10560
10561 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10562 if (!connector->encoder || !connector->encoder->crtc)
10563 continue;
10564
10565 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10566
10567 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10568 struct drm_property *dpms_property =
10569 dev->mode_config.dpms_property;
10570
10571 connector->dpms = DRM_MODE_DPMS_ON;
10572 drm_object_property_set_value(&connector->base,
10573 dpms_property,
10574 DRM_MODE_DPMS_ON);
10575
10576 intel_encoder = to_intel_encoder(connector->encoder);
10577 intel_encoder->connectors_active = true;
10578 }
10579 }
10580
10581 }
10582
10583 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10584 {
10585 int diff;
10586
10587 if (clock1 == clock2)
10588 return true;
10589
10590 if (!clock1 || !clock2)
10591 return false;
10592
10593 diff = abs(clock1 - clock2);
10594
10595 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10596 return true;
10597
10598 return false;
10599 }
10600
10601 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10602 list_for_each_entry((intel_crtc), \
10603 &(dev)->mode_config.crtc_list, \
10604 base.head) \
10605 if (mask & (1 <<(intel_crtc)->pipe))
10606
10607 static bool
10608 intel_pipe_config_compare(struct drm_device *dev,
10609 struct intel_crtc_config *current_config,
10610 struct intel_crtc_config *pipe_config)
10611 {
10612 #define PIPE_CONF_CHECK_X(name) \
10613 if (current_config->name != pipe_config->name) { \
10614 DRM_ERROR("mismatch in " #name " " \
10615 "(expected 0x%08x, found 0x%08x)\n", \
10616 current_config->name, \
10617 pipe_config->name); \
10618 return false; \
10619 }
10620
10621 #define PIPE_CONF_CHECK_I(name) \
10622 if (current_config->name != pipe_config->name) { \
10623 DRM_ERROR("mismatch in " #name " " \
10624 "(expected %i, found %i)\n", \
10625 current_config->name, \
10626 pipe_config->name); \
10627 return false; \
10628 }
10629
10630 /* This is required for BDW+ where there is only one set of registers for
10631 * switching between high and low RR.
10632 * This macro can be used whenever a comparison has to be made between one
10633 * hw state and multiple sw state variables.
10634 */
10635 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10636 if ((current_config->name != pipe_config->name) && \
10637 (current_config->alt_name != pipe_config->name)) { \
10638 DRM_ERROR("mismatch in " #name " " \
10639 "(expected %i or %i, found %i)\n", \
10640 current_config->name, \
10641 current_config->alt_name, \
10642 pipe_config->name); \
10643 return false; \
10644 }
10645
10646 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10647 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10648 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10649 "(expected %i, found %i)\n", \
10650 current_config->name & (mask), \
10651 pipe_config->name & (mask)); \
10652 return false; \
10653 }
10654
10655 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10656 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10657 DRM_ERROR("mismatch in " #name " " \
10658 "(expected %i, found %i)\n", \
10659 current_config->name, \
10660 pipe_config->name); \
10661 return false; \
10662 }
10663
10664 #define PIPE_CONF_QUIRK(quirk) \
10665 ((current_config->quirks | pipe_config->quirks) & (quirk))
10666
10667 PIPE_CONF_CHECK_I(cpu_transcoder);
10668
10669 PIPE_CONF_CHECK_I(has_pch_encoder);
10670 PIPE_CONF_CHECK_I(fdi_lanes);
10671 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10672 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10673 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10674 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10675 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10676
10677 PIPE_CONF_CHECK_I(has_dp_encoder);
10678
10679 if (INTEL_INFO(dev)->gen < 8) {
10680 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10681 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10682 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10683 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10684 PIPE_CONF_CHECK_I(dp_m_n.tu);
10685
10686 if (current_config->has_drrs) {
10687 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10688 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10689 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10690 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10691 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10692 }
10693 } else {
10694 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10695 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10696 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10697 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10698 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10699 }
10700
10701 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10702 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10703 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10704 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10705 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10706 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10707
10708 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10709 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10710 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10711 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10712 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10713 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10714
10715 PIPE_CONF_CHECK_I(pixel_multiplier);
10716 PIPE_CONF_CHECK_I(has_hdmi_sink);
10717 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10718 IS_VALLEYVIEW(dev))
10719 PIPE_CONF_CHECK_I(limited_color_range);
10720
10721 PIPE_CONF_CHECK_I(has_audio);
10722
10723 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10724 DRM_MODE_FLAG_INTERLACE);
10725
10726 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10727 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10728 DRM_MODE_FLAG_PHSYNC);
10729 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10730 DRM_MODE_FLAG_NHSYNC);
10731 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10732 DRM_MODE_FLAG_PVSYNC);
10733 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10734 DRM_MODE_FLAG_NVSYNC);
10735 }
10736
10737 PIPE_CONF_CHECK_I(pipe_src_w);
10738 PIPE_CONF_CHECK_I(pipe_src_h);
10739
10740 /*
10741 * FIXME: BIOS likes to set up a cloned config with lvds+external
10742 * screen. Since we don't yet re-compute the pipe config when moving
10743 * just the lvds port away to another pipe the sw tracking won't match.
10744 *
10745 * Proper atomic modesets with recomputed global state will fix this.
10746 * Until then just don't check gmch state for inherited modes.
10747 */
10748 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10749 PIPE_CONF_CHECK_I(gmch_pfit.control);
10750 /* pfit ratios are autocomputed by the hw on gen4+ */
10751 if (INTEL_INFO(dev)->gen < 4)
10752 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10753 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10754 }
10755
10756 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10757 if (current_config->pch_pfit.enabled) {
10758 PIPE_CONF_CHECK_I(pch_pfit.pos);
10759 PIPE_CONF_CHECK_I(pch_pfit.size);
10760 }
10761
10762 /* BDW+ don't expose a synchronous way to read the state */
10763 if (IS_HASWELL(dev))
10764 PIPE_CONF_CHECK_I(ips_enabled);
10765
10766 PIPE_CONF_CHECK_I(double_wide);
10767
10768 PIPE_CONF_CHECK_X(ddi_pll_sel);
10769
10770 PIPE_CONF_CHECK_I(shared_dpll);
10771 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10772 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10773 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10774 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10775 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10776
10777 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10778 PIPE_CONF_CHECK_I(pipe_bpp);
10779
10780 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10781 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10782
10783 #undef PIPE_CONF_CHECK_X
10784 #undef PIPE_CONF_CHECK_I
10785 #undef PIPE_CONF_CHECK_I_ALT
10786 #undef PIPE_CONF_CHECK_FLAGS
10787 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10788 #undef PIPE_CONF_QUIRK
10789
10790 return true;
10791 }
10792
10793 static void
10794 check_connector_state(struct drm_device *dev)
10795 {
10796 struct intel_connector *connector;
10797
10798 list_for_each_entry(connector, &dev->mode_config.connector_list,
10799 base.head) {
10800 /* This also checks the encoder/connector hw state with the
10801 * ->get_hw_state callbacks. */
10802 intel_connector_check_state(connector);
10803
10804 WARN(&connector->new_encoder->base != connector->base.encoder,
10805 "connector's staged encoder doesn't match current encoder\n");
10806 }
10807 }
10808
10809 static void
10810 check_encoder_state(struct drm_device *dev)
10811 {
10812 struct intel_encoder *encoder;
10813 struct intel_connector *connector;
10814
10815 for_each_intel_encoder(dev, encoder) {
10816 bool enabled = false;
10817 bool active = false;
10818 enum pipe pipe, tracked_pipe;
10819
10820 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10821 encoder->base.base.id,
10822 encoder->base.name);
10823
10824 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10825 "encoder's stage crtc doesn't match current crtc\n");
10826 WARN(encoder->connectors_active && !encoder->base.crtc,
10827 "encoder's active_connectors set, but no crtc\n");
10828
10829 list_for_each_entry(connector, &dev->mode_config.connector_list,
10830 base.head) {
10831 if (connector->base.encoder != &encoder->base)
10832 continue;
10833 enabled = true;
10834 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10835 active = true;
10836 }
10837 /*
10838 * for MST connectors if we unplug the connector is gone
10839 * away but the encoder is still connected to a crtc
10840 * until a modeset happens in response to the hotplug.
10841 */
10842 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10843 continue;
10844
10845 WARN(!!encoder->base.crtc != enabled,
10846 "encoder's enabled state mismatch "
10847 "(expected %i, found %i)\n",
10848 !!encoder->base.crtc, enabled);
10849 WARN(active && !encoder->base.crtc,
10850 "active encoder with no crtc\n");
10851
10852 WARN(encoder->connectors_active != active,
10853 "encoder's computed active state doesn't match tracked active state "
10854 "(expected %i, found %i)\n", active, encoder->connectors_active);
10855
10856 active = encoder->get_hw_state(encoder, &pipe);
10857 WARN(active != encoder->connectors_active,
10858 "encoder's hw state doesn't match sw tracking "
10859 "(expected %i, found %i)\n",
10860 encoder->connectors_active, active);
10861
10862 if (!encoder->base.crtc)
10863 continue;
10864
10865 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10866 WARN(active && pipe != tracked_pipe,
10867 "active encoder's pipe doesn't match"
10868 "(expected %i, found %i)\n",
10869 tracked_pipe, pipe);
10870
10871 }
10872 }
10873
10874 static void
10875 check_crtc_state(struct drm_device *dev)
10876 {
10877 struct drm_i915_private *dev_priv = dev->dev_private;
10878 struct intel_crtc *crtc;
10879 struct intel_encoder *encoder;
10880 struct intel_crtc_config pipe_config;
10881
10882 for_each_intel_crtc(dev, crtc) {
10883 bool enabled = false;
10884 bool active = false;
10885
10886 memset(&pipe_config, 0, sizeof(pipe_config));
10887
10888 DRM_DEBUG_KMS("[CRTC:%d]\n",
10889 crtc->base.base.id);
10890
10891 WARN(crtc->active && !crtc->base.enabled,
10892 "active crtc, but not enabled in sw tracking\n");
10893
10894 for_each_intel_encoder(dev, encoder) {
10895 if (encoder->base.crtc != &crtc->base)
10896 continue;
10897 enabled = true;
10898 if (encoder->connectors_active)
10899 active = true;
10900 }
10901
10902 WARN(active != crtc->active,
10903 "crtc's computed active state doesn't match tracked active state "
10904 "(expected %i, found %i)\n", active, crtc->active);
10905 WARN(enabled != crtc->base.enabled,
10906 "crtc's computed enabled state doesn't match tracked enabled state "
10907 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10908
10909 active = dev_priv->display.get_pipe_config(crtc,
10910 &pipe_config);
10911
10912 /* hw state is inconsistent with the pipe quirk */
10913 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10914 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
10915 active = crtc->active;
10916
10917 for_each_intel_encoder(dev, encoder) {
10918 enum pipe pipe;
10919 if (encoder->base.crtc != &crtc->base)
10920 continue;
10921 if (encoder->get_hw_state(encoder, &pipe))
10922 encoder->get_config(encoder, &pipe_config);
10923 }
10924
10925 WARN(crtc->active != active,
10926 "crtc active state doesn't match with hw state "
10927 "(expected %i, found %i)\n", crtc->active, active);
10928
10929 if (active &&
10930 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10931 WARN(1, "pipe state doesn't match!\n");
10932 intel_dump_pipe_config(crtc, &pipe_config,
10933 "[hw state]");
10934 intel_dump_pipe_config(crtc, &crtc->config,
10935 "[sw state]");
10936 }
10937 }
10938 }
10939
10940 static void
10941 check_shared_dpll_state(struct drm_device *dev)
10942 {
10943 struct drm_i915_private *dev_priv = dev->dev_private;
10944 struct intel_crtc *crtc;
10945 struct intel_dpll_hw_state dpll_hw_state;
10946 int i;
10947
10948 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10949 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10950 int enabled_crtcs = 0, active_crtcs = 0;
10951 bool active;
10952
10953 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10954
10955 DRM_DEBUG_KMS("%s\n", pll->name);
10956
10957 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10958
10959 WARN(pll->active > pll->refcount,
10960 "more active pll users than references: %i vs %i\n",
10961 pll->active, pll->refcount);
10962 WARN(pll->active && !pll->on,
10963 "pll in active use but not on in sw tracking\n");
10964 WARN(pll->on && !pll->active,
10965 "pll in on but not on in use in sw tracking\n");
10966 WARN(pll->on != active,
10967 "pll on state mismatch (expected %i, found %i)\n",
10968 pll->on, active);
10969
10970 for_each_intel_crtc(dev, crtc) {
10971 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10972 enabled_crtcs++;
10973 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10974 active_crtcs++;
10975 }
10976 WARN(pll->active != active_crtcs,
10977 "pll active crtcs mismatch (expected %i, found %i)\n",
10978 pll->active, active_crtcs);
10979 WARN(pll->refcount != enabled_crtcs,
10980 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10981 pll->refcount, enabled_crtcs);
10982
10983 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
10984 sizeof(dpll_hw_state)),
10985 "pll hw state mismatch\n");
10986 }
10987 }
10988
10989 void
10990 intel_modeset_check_state(struct drm_device *dev)
10991 {
10992 check_connector_state(dev);
10993 check_encoder_state(dev);
10994 check_crtc_state(dev);
10995 check_shared_dpll_state(dev);
10996 }
10997
10998 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10999 int dotclock)
11000 {
11001 /*
11002 * FDI already provided one idea for the dotclock.
11003 * Yell if the encoder disagrees.
11004 */
11005 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
11006 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11007 pipe_config->adjusted_mode.crtc_clock, dotclock);
11008 }
11009
11010 static void update_scanline_offset(struct intel_crtc *crtc)
11011 {
11012 struct drm_device *dev = crtc->base.dev;
11013
11014 /*
11015 * The scanline counter increments at the leading edge of hsync.
11016 *
11017 * On most platforms it starts counting from vtotal-1 on the
11018 * first active line. That means the scanline counter value is
11019 * always one less than what we would expect. Ie. just after
11020 * start of vblank, which also occurs at start of hsync (on the
11021 * last active line), the scanline counter will read vblank_start-1.
11022 *
11023 * On gen2 the scanline counter starts counting from 1 instead
11024 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11025 * to keep the value positive), instead of adding one.
11026 *
11027 * On HSW+ the behaviour of the scanline counter depends on the output
11028 * type. For DP ports it behaves like most other platforms, but on HDMI
11029 * there's an extra 1 line difference. So we need to add two instead of
11030 * one to the value.
11031 */
11032 if (IS_GEN2(dev)) {
11033 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
11034 int vtotal;
11035
11036 vtotal = mode->crtc_vtotal;
11037 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
11038 vtotal /= 2;
11039
11040 crtc->scanline_offset = vtotal - 1;
11041 } else if (HAS_DDI(dev) &&
11042 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {
11043 crtc->scanline_offset = 2;
11044 } else
11045 crtc->scanline_offset = 1;
11046 }
11047
11048 static int __intel_set_mode(struct drm_crtc *crtc,
11049 struct drm_display_mode *mode,
11050 int x, int y, struct drm_framebuffer *fb)
11051 {
11052 struct drm_device *dev = crtc->dev;
11053 struct drm_i915_private *dev_priv = dev->dev_private;
11054 struct drm_display_mode *saved_mode;
11055 struct intel_crtc_config *pipe_config = NULL;
11056 struct intel_crtc *intel_crtc;
11057 unsigned disable_pipes, prepare_pipes, modeset_pipes;
11058 int ret = 0;
11059
11060 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
11061 if (!saved_mode)
11062 return -ENOMEM;
11063
11064 intel_modeset_affected_pipes(crtc, &modeset_pipes,
11065 &prepare_pipes, &disable_pipes);
11066
11067 *saved_mode = crtc->mode;
11068
11069 /* Hack: Because we don't (yet) support global modeset on multiple
11070 * crtcs, we don't keep track of the new mode for more than one crtc.
11071 * Hence simply check whether any bit is set in modeset_pipes in all the
11072 * pieces of code that are not yet converted to deal with mutliple crtcs
11073 * changing their mode at the same time. */
11074 if (modeset_pipes) {
11075 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
11076 if (IS_ERR(pipe_config)) {
11077 ret = PTR_ERR(pipe_config);
11078 pipe_config = NULL;
11079
11080 goto out;
11081 }
11082 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11083 "[modeset]");
11084 to_intel_crtc(crtc)->new_config = pipe_config;
11085 }
11086
11087 /*
11088 * See if the config requires any additional preparation, e.g.
11089 * to adjust global state with pipes off. We need to do this
11090 * here so we can get the modeset_pipe updated config for the new
11091 * mode set on this crtc. For other crtcs we need to use the
11092 * adjusted_mode bits in the crtc directly.
11093 */
11094 if (IS_VALLEYVIEW(dev)) {
11095 valleyview_modeset_global_pipes(dev, &prepare_pipes);
11096
11097 /* may have added more to prepare_pipes than we should */
11098 prepare_pipes &= ~disable_pipes;
11099 }
11100
11101 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
11102 intel_crtc_disable(&intel_crtc->base);
11103
11104 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11105 if (intel_crtc->base.enabled)
11106 dev_priv->display.crtc_disable(&intel_crtc->base);
11107 }
11108
11109 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11110 * to set it here already despite that we pass it down the callchain.
11111 */
11112 if (modeset_pipes) {
11113 crtc->mode = *mode;
11114 /* mode_set/enable/disable functions rely on a correct pipe
11115 * config. */
11116 to_intel_crtc(crtc)->config = *pipe_config;
11117 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
11118
11119 /*
11120 * Calculate and store various constants which
11121 * are later needed by vblank and swap-completion
11122 * timestamping. They are derived from true hwmode.
11123 */
11124 drm_calc_timestamping_constants(crtc,
11125 &pipe_config->adjusted_mode);
11126 }
11127
11128 /* Only after disabling all output pipelines that will be changed can we
11129 * update the the output configuration. */
11130 intel_modeset_update_state(dev, prepare_pipes);
11131
11132 if (dev_priv->display.modeset_global_resources)
11133 dev_priv->display.modeset_global_resources(dev);
11134
11135 /* Set up the DPLL and any encoders state that needs to adjust or depend
11136 * on the DPLL.
11137 */
11138 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11139 struct drm_framebuffer *old_fb = crtc->primary->fb;
11140 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
11141 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11142
11143 mutex_lock(&dev->struct_mutex);
11144 ret = intel_pin_and_fence_fb_obj(dev,
11145 obj,
11146 NULL);
11147 if (ret != 0) {
11148 DRM_ERROR("pin & fence failed\n");
11149 mutex_unlock(&dev->struct_mutex);
11150 goto done;
11151 }
11152 if (old_fb)
11153 intel_unpin_fb_obj(old_obj);
11154 i915_gem_track_fb(old_obj, obj,
11155 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11156 mutex_unlock(&dev->struct_mutex);
11157
11158 crtc->primary->fb = fb;
11159 crtc->x = x;
11160 crtc->y = y;
11161
11162 ret = dev_priv->display.crtc_mode_set(&intel_crtc->base,
11163 x, y, fb);
11164 if (ret)
11165 goto done;
11166 }
11167
11168 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11169 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11170 update_scanline_offset(intel_crtc);
11171
11172 dev_priv->display.crtc_enable(&intel_crtc->base);
11173 }
11174
11175 /* FIXME: add subpixel order */
11176 done:
11177 if (ret && crtc->enabled)
11178 crtc->mode = *saved_mode;
11179
11180 out:
11181 kfree(pipe_config);
11182 kfree(saved_mode);
11183 return ret;
11184 }
11185
11186 static int intel_set_mode(struct drm_crtc *crtc,
11187 struct drm_display_mode *mode,
11188 int x, int y, struct drm_framebuffer *fb)
11189 {
11190 int ret;
11191
11192 ret = __intel_set_mode(crtc, mode, x, y, fb);
11193
11194 if (ret == 0)
11195 intel_modeset_check_state(crtc->dev);
11196
11197 return ret;
11198 }
11199
11200 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11201 {
11202 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
11203 }
11204
11205 #undef for_each_intel_crtc_masked
11206
11207 static void intel_set_config_free(struct intel_set_config *config)
11208 {
11209 if (!config)
11210 return;
11211
11212 kfree(config->save_connector_encoders);
11213 kfree(config->save_encoder_crtcs);
11214 kfree(config->save_crtc_enabled);
11215 kfree(config);
11216 }
11217
11218 static int intel_set_config_save_state(struct drm_device *dev,
11219 struct intel_set_config *config)
11220 {
11221 struct drm_crtc *crtc;
11222 struct drm_encoder *encoder;
11223 struct drm_connector *connector;
11224 int count;
11225
11226 config->save_crtc_enabled =
11227 kcalloc(dev->mode_config.num_crtc,
11228 sizeof(bool), GFP_KERNEL);
11229 if (!config->save_crtc_enabled)
11230 return -ENOMEM;
11231
11232 config->save_encoder_crtcs =
11233 kcalloc(dev->mode_config.num_encoder,
11234 sizeof(struct drm_crtc *), GFP_KERNEL);
11235 if (!config->save_encoder_crtcs)
11236 return -ENOMEM;
11237
11238 config->save_connector_encoders =
11239 kcalloc(dev->mode_config.num_connector,
11240 sizeof(struct drm_encoder *), GFP_KERNEL);
11241 if (!config->save_connector_encoders)
11242 return -ENOMEM;
11243
11244 /* Copy data. Note that driver private data is not affected.
11245 * Should anything bad happen only the expected state is
11246 * restored, not the drivers personal bookkeeping.
11247 */
11248 count = 0;
11249 for_each_crtc(dev, crtc) {
11250 config->save_crtc_enabled[count++] = crtc->enabled;
11251 }
11252
11253 count = 0;
11254 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11255 config->save_encoder_crtcs[count++] = encoder->crtc;
11256 }
11257
11258 count = 0;
11259 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11260 config->save_connector_encoders[count++] = connector->encoder;
11261 }
11262
11263 return 0;
11264 }
11265
11266 static void intel_set_config_restore_state(struct drm_device *dev,
11267 struct intel_set_config *config)
11268 {
11269 struct intel_crtc *crtc;
11270 struct intel_encoder *encoder;
11271 struct intel_connector *connector;
11272 int count;
11273
11274 count = 0;
11275 for_each_intel_crtc(dev, crtc) {
11276 crtc->new_enabled = config->save_crtc_enabled[count++];
11277
11278 if (crtc->new_enabled)
11279 crtc->new_config = &crtc->config;
11280 else
11281 crtc->new_config = NULL;
11282 }
11283
11284 count = 0;
11285 for_each_intel_encoder(dev, encoder) {
11286 encoder->new_crtc =
11287 to_intel_crtc(config->save_encoder_crtcs[count++]);
11288 }
11289
11290 count = 0;
11291 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11292 connector->new_encoder =
11293 to_intel_encoder(config->save_connector_encoders[count++]);
11294 }
11295 }
11296
11297 static bool
11298 is_crtc_connector_off(struct drm_mode_set *set)
11299 {
11300 int i;
11301
11302 if (set->num_connectors == 0)
11303 return false;
11304
11305 if (WARN_ON(set->connectors == NULL))
11306 return false;
11307
11308 for (i = 0; i < set->num_connectors; i++)
11309 if (set->connectors[i]->encoder &&
11310 set->connectors[i]->encoder->crtc == set->crtc &&
11311 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11312 return true;
11313
11314 return false;
11315 }
11316
11317 static void
11318 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11319 struct intel_set_config *config)
11320 {
11321
11322 /* We should be able to check here if the fb has the same properties
11323 * and then just flip_or_move it */
11324 if (is_crtc_connector_off(set)) {
11325 config->mode_changed = true;
11326 } else if (set->crtc->primary->fb != set->fb) {
11327 /*
11328 * If we have no fb, we can only flip as long as the crtc is
11329 * active, otherwise we need a full mode set. The crtc may
11330 * be active if we've only disabled the primary plane, or
11331 * in fastboot situations.
11332 */
11333 if (set->crtc->primary->fb == NULL) {
11334 struct intel_crtc *intel_crtc =
11335 to_intel_crtc(set->crtc);
11336
11337 if (intel_crtc->active) {
11338 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11339 config->fb_changed = true;
11340 } else {
11341 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11342 config->mode_changed = true;
11343 }
11344 } else if (set->fb == NULL) {
11345 config->mode_changed = true;
11346 } else if (set->fb->pixel_format !=
11347 set->crtc->primary->fb->pixel_format) {
11348 config->mode_changed = true;
11349 } else {
11350 config->fb_changed = true;
11351 }
11352 }
11353
11354 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11355 config->fb_changed = true;
11356
11357 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11358 DRM_DEBUG_KMS("modes are different, full mode set\n");
11359 drm_mode_debug_printmodeline(&set->crtc->mode);
11360 drm_mode_debug_printmodeline(set->mode);
11361 config->mode_changed = true;
11362 }
11363
11364 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11365 set->crtc->base.id, config->mode_changed, config->fb_changed);
11366 }
11367
11368 static int
11369 intel_modeset_stage_output_state(struct drm_device *dev,
11370 struct drm_mode_set *set,
11371 struct intel_set_config *config)
11372 {
11373 struct intel_connector *connector;
11374 struct intel_encoder *encoder;
11375 struct intel_crtc *crtc;
11376 int ro;
11377
11378 /* The upper layers ensure that we either disable a crtc or have a list
11379 * of connectors. For paranoia, double-check this. */
11380 WARN_ON(!set->fb && (set->num_connectors != 0));
11381 WARN_ON(set->fb && (set->num_connectors == 0));
11382
11383 list_for_each_entry(connector, &dev->mode_config.connector_list,
11384 base.head) {
11385 /* Otherwise traverse passed in connector list and get encoders
11386 * for them. */
11387 for (ro = 0; ro < set->num_connectors; ro++) {
11388 if (set->connectors[ro] == &connector->base) {
11389 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11390 break;
11391 }
11392 }
11393
11394 /* If we disable the crtc, disable all its connectors. Also, if
11395 * the connector is on the changing crtc but not on the new
11396 * connector list, disable it. */
11397 if ((!set->fb || ro == set->num_connectors) &&
11398 connector->base.encoder &&
11399 connector->base.encoder->crtc == set->crtc) {
11400 connector->new_encoder = NULL;
11401
11402 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11403 connector->base.base.id,
11404 connector->base.name);
11405 }
11406
11407
11408 if (&connector->new_encoder->base != connector->base.encoder) {
11409 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11410 config->mode_changed = true;
11411 }
11412 }
11413 /* connector->new_encoder is now updated for all connectors. */
11414
11415 /* Update crtc of enabled connectors. */
11416 list_for_each_entry(connector, &dev->mode_config.connector_list,
11417 base.head) {
11418 struct drm_crtc *new_crtc;
11419
11420 if (!connector->new_encoder)
11421 continue;
11422
11423 new_crtc = connector->new_encoder->base.crtc;
11424
11425 for (ro = 0; ro < set->num_connectors; ro++) {
11426 if (set->connectors[ro] == &connector->base)
11427 new_crtc = set->crtc;
11428 }
11429
11430 /* Make sure the new CRTC will work with the encoder */
11431 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11432 new_crtc)) {
11433 return -EINVAL;
11434 }
11435 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11436
11437 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11438 connector->base.base.id,
11439 connector->base.name,
11440 new_crtc->base.id);
11441 }
11442
11443 /* Check for any encoders that needs to be disabled. */
11444 for_each_intel_encoder(dev, encoder) {
11445 int num_connectors = 0;
11446 list_for_each_entry(connector,
11447 &dev->mode_config.connector_list,
11448 base.head) {
11449 if (connector->new_encoder == encoder) {
11450 WARN_ON(!connector->new_encoder->new_crtc);
11451 num_connectors++;
11452 }
11453 }
11454
11455 if (num_connectors == 0)
11456 encoder->new_crtc = NULL;
11457 else if (num_connectors > 1)
11458 return -EINVAL;
11459
11460 /* Only now check for crtc changes so we don't miss encoders
11461 * that will be disabled. */
11462 if (&encoder->new_crtc->base != encoder->base.crtc) {
11463 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11464 config->mode_changed = true;
11465 }
11466 }
11467 /* Now we've also updated encoder->new_crtc for all encoders. */
11468 list_for_each_entry(connector, &dev->mode_config.connector_list,
11469 base.head) {
11470 if (connector->new_encoder)
11471 if (connector->new_encoder != connector->encoder)
11472 connector->encoder = connector->new_encoder;
11473 }
11474 for_each_intel_crtc(dev, crtc) {
11475 crtc->new_enabled = false;
11476
11477 for_each_intel_encoder(dev, encoder) {
11478 if (encoder->new_crtc == crtc) {
11479 crtc->new_enabled = true;
11480 break;
11481 }
11482 }
11483
11484 if (crtc->new_enabled != crtc->base.enabled) {
11485 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11486 crtc->new_enabled ? "en" : "dis");
11487 config->mode_changed = true;
11488 }
11489
11490 if (crtc->new_enabled)
11491 crtc->new_config = &crtc->config;
11492 else
11493 crtc->new_config = NULL;
11494 }
11495
11496 return 0;
11497 }
11498
11499 static void disable_crtc_nofb(struct intel_crtc *crtc)
11500 {
11501 struct drm_device *dev = crtc->base.dev;
11502 struct intel_encoder *encoder;
11503 struct intel_connector *connector;
11504
11505 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11506 pipe_name(crtc->pipe));
11507
11508 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11509 if (connector->new_encoder &&
11510 connector->new_encoder->new_crtc == crtc)
11511 connector->new_encoder = NULL;
11512 }
11513
11514 for_each_intel_encoder(dev, encoder) {
11515 if (encoder->new_crtc == crtc)
11516 encoder->new_crtc = NULL;
11517 }
11518
11519 crtc->new_enabled = false;
11520 crtc->new_config = NULL;
11521 }
11522
11523 static int intel_crtc_set_config(struct drm_mode_set *set)
11524 {
11525 struct drm_device *dev;
11526 struct drm_mode_set save_set;
11527 struct intel_set_config *config;
11528 int ret;
11529
11530 BUG_ON(!set);
11531 BUG_ON(!set->crtc);
11532 BUG_ON(!set->crtc->helper_private);
11533
11534 /* Enforce sane interface api - has been abused by the fb helper. */
11535 BUG_ON(!set->mode && set->fb);
11536 BUG_ON(set->fb && set->num_connectors == 0);
11537
11538 if (set->fb) {
11539 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11540 set->crtc->base.id, set->fb->base.id,
11541 (int)set->num_connectors, set->x, set->y);
11542 } else {
11543 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11544 }
11545
11546 dev = set->crtc->dev;
11547
11548 ret = -ENOMEM;
11549 config = kzalloc(sizeof(*config), GFP_KERNEL);
11550 if (!config)
11551 goto out_config;
11552
11553 ret = intel_set_config_save_state(dev, config);
11554 if (ret)
11555 goto out_config;
11556
11557 save_set.crtc = set->crtc;
11558 save_set.mode = &set->crtc->mode;
11559 save_set.x = set->crtc->x;
11560 save_set.y = set->crtc->y;
11561 save_set.fb = set->crtc->primary->fb;
11562
11563 /* Compute whether we need a full modeset, only an fb base update or no
11564 * change at all. In the future we might also check whether only the
11565 * mode changed, e.g. for LVDS where we only change the panel fitter in
11566 * such cases. */
11567 intel_set_config_compute_mode_changes(set, config);
11568
11569 ret = intel_modeset_stage_output_state(dev, set, config);
11570 if (ret)
11571 goto fail;
11572
11573 if (config->mode_changed) {
11574 ret = intel_set_mode(set->crtc, set->mode,
11575 set->x, set->y, set->fb);
11576 } else if (config->fb_changed) {
11577 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11578
11579 intel_crtc_wait_for_pending_flips(set->crtc);
11580
11581 ret = intel_pipe_set_base(set->crtc,
11582 set->x, set->y, set->fb);
11583
11584 /*
11585 * We need to make sure the primary plane is re-enabled if it
11586 * has previously been turned off.
11587 */
11588 if (!intel_crtc->primary_enabled && ret == 0) {
11589 WARN_ON(!intel_crtc->active);
11590 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11591 }
11592
11593 /*
11594 * In the fastboot case this may be our only check of the
11595 * state after boot. It would be better to only do it on
11596 * the first update, but we don't have a nice way of doing that
11597 * (and really, set_config isn't used much for high freq page
11598 * flipping, so increasing its cost here shouldn't be a big
11599 * deal).
11600 */
11601 if (i915.fastboot && ret == 0)
11602 intel_modeset_check_state(set->crtc->dev);
11603 }
11604
11605 if (ret) {
11606 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11607 set->crtc->base.id, ret);
11608 fail:
11609 intel_set_config_restore_state(dev, config);
11610
11611 /*
11612 * HACK: if the pipe was on, but we didn't have a framebuffer,
11613 * force the pipe off to avoid oopsing in the modeset code
11614 * due to fb==NULL. This should only happen during boot since
11615 * we don't yet reconstruct the FB from the hardware state.
11616 */
11617 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11618 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11619
11620 /* Try to restore the config */
11621 if (config->mode_changed &&
11622 intel_set_mode(save_set.crtc, save_set.mode,
11623 save_set.x, save_set.y, save_set.fb))
11624 DRM_ERROR("failed to restore config after modeset failure\n");
11625 }
11626
11627 out_config:
11628 intel_set_config_free(config);
11629 return ret;
11630 }
11631
11632 static const struct drm_crtc_funcs intel_crtc_funcs = {
11633 .gamma_set = intel_crtc_gamma_set,
11634 .set_config = intel_crtc_set_config,
11635 .destroy = intel_crtc_destroy,
11636 .page_flip = intel_crtc_page_flip,
11637 };
11638
11639 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11640 struct intel_shared_dpll *pll,
11641 struct intel_dpll_hw_state *hw_state)
11642 {
11643 uint32_t val;
11644
11645 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_PLLS))
11646 return false;
11647
11648 val = I915_READ(PCH_DPLL(pll->id));
11649 hw_state->dpll = val;
11650 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11651 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11652
11653 return val & DPLL_VCO_ENABLE;
11654 }
11655
11656 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11657 struct intel_shared_dpll *pll)
11658 {
11659 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
11660 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
11661 }
11662
11663 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11664 struct intel_shared_dpll *pll)
11665 {
11666 /* PCH refclock must be enabled first */
11667 ibx_assert_pch_refclk_enabled(dev_priv);
11668
11669 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11670
11671 /* Wait for the clocks to stabilize. */
11672 POSTING_READ(PCH_DPLL(pll->id));
11673 udelay(150);
11674
11675 /* The pixel multiplier can only be updated once the
11676 * DPLL is enabled and the clocks are stable.
11677 *
11678 * So write it again.
11679 */
11680 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11681 POSTING_READ(PCH_DPLL(pll->id));
11682 udelay(200);
11683 }
11684
11685 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11686 struct intel_shared_dpll *pll)
11687 {
11688 struct drm_device *dev = dev_priv->dev;
11689 struct intel_crtc *crtc;
11690
11691 /* Make sure no transcoder isn't still depending on us. */
11692 for_each_intel_crtc(dev, crtc) {
11693 if (intel_crtc_to_shared_dpll(crtc) == pll)
11694 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11695 }
11696
11697 I915_WRITE(PCH_DPLL(pll->id), 0);
11698 POSTING_READ(PCH_DPLL(pll->id));
11699 udelay(200);
11700 }
11701
11702 static char *ibx_pch_dpll_names[] = {
11703 "PCH DPLL A",
11704 "PCH DPLL B",
11705 };
11706
11707 static void ibx_pch_dpll_init(struct drm_device *dev)
11708 {
11709 struct drm_i915_private *dev_priv = dev->dev_private;
11710 int i;
11711
11712 dev_priv->num_shared_dpll = 2;
11713
11714 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11715 dev_priv->shared_dplls[i].id = i;
11716 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11717 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11718 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11719 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11720 dev_priv->shared_dplls[i].get_hw_state =
11721 ibx_pch_dpll_get_hw_state;
11722 }
11723 }
11724
11725 static void intel_shared_dpll_init(struct drm_device *dev)
11726 {
11727 struct drm_i915_private *dev_priv = dev->dev_private;
11728
11729 if (HAS_DDI(dev))
11730 intel_ddi_pll_init(dev);
11731 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11732 ibx_pch_dpll_init(dev);
11733 else
11734 dev_priv->num_shared_dpll = 0;
11735
11736 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11737 }
11738
11739 static int
11740 intel_primary_plane_disable(struct drm_plane *plane)
11741 {
11742 struct drm_device *dev = plane->dev;
11743 struct intel_crtc *intel_crtc;
11744
11745 if (!plane->fb)
11746 return 0;
11747
11748 BUG_ON(!plane->crtc);
11749
11750 intel_crtc = to_intel_crtc(plane->crtc);
11751
11752 /*
11753 * Even though we checked plane->fb above, it's still possible that
11754 * the primary plane has been implicitly disabled because the crtc
11755 * coordinates given weren't visible, or because we detected
11756 * that it was 100% covered by a sprite plane. Or, the CRTC may be
11757 * off and we've set a fb, but haven't actually turned on the CRTC yet.
11758 * In either case, we need to unpin the FB and let the fb pointer get
11759 * updated, but otherwise we don't need to touch the hardware.
11760 */
11761 if (!intel_crtc->primary_enabled)
11762 goto disable_unpin;
11763
11764 intel_crtc_wait_for_pending_flips(plane->crtc);
11765 intel_disable_primary_hw_plane(plane, plane->crtc);
11766
11767 disable_unpin:
11768 mutex_lock(&dev->struct_mutex);
11769 i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
11770 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11771 intel_unpin_fb_obj(intel_fb_obj(plane->fb));
11772 mutex_unlock(&dev->struct_mutex);
11773 plane->fb = NULL;
11774
11775 return 0;
11776 }
11777
11778 static int
11779 intel_check_primary_plane(struct drm_plane *plane,
11780 struct intel_plane_state *state)
11781 {
11782 struct drm_crtc *crtc = state->crtc;
11783 struct drm_framebuffer *fb = state->fb;
11784 struct drm_rect *dest = &state->dst;
11785 struct drm_rect *src = &state->src;
11786 const struct drm_rect *clip = &state->clip;
11787
11788 return drm_plane_helper_check_update(plane, crtc, fb,
11789 src, dest, clip,
11790 DRM_PLANE_HELPER_NO_SCALING,
11791 DRM_PLANE_HELPER_NO_SCALING,
11792 false, true, &state->visible);
11793 }
11794
11795 static int
11796 intel_commit_primary_plane(struct drm_plane *plane,
11797 struct intel_plane_state *state)
11798 {
11799 struct drm_crtc *crtc = state->crtc;
11800 struct drm_framebuffer *fb = state->fb;
11801 struct drm_device *dev = crtc->dev;
11802 struct drm_i915_private *dev_priv = dev->dev_private;
11803 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11804 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11805 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11806 struct intel_plane *intel_plane = to_intel_plane(plane);
11807 struct drm_rect *src = &state->src;
11808 int ret;
11809
11810 intel_crtc_wait_for_pending_flips(crtc);
11811
11812 /*
11813 * If clipping results in a non-visible primary plane, we'll disable
11814 * the primary plane. Note that this is a bit different than what
11815 * happens if userspace explicitly disables the plane by passing fb=0
11816 * because plane->fb still gets set and pinned.
11817 */
11818 if (!state->visible) {
11819 mutex_lock(&dev->struct_mutex);
11820
11821 /*
11822 * Try to pin the new fb first so that we can bail out if we
11823 * fail.
11824 */
11825 if (plane->fb != fb) {
11826 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11827 if (ret) {
11828 mutex_unlock(&dev->struct_mutex);
11829 return ret;
11830 }
11831 }
11832
11833 i915_gem_track_fb(old_obj, obj,
11834 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11835
11836 if (intel_crtc->primary_enabled)
11837 intel_disable_primary_hw_plane(plane, crtc);
11838
11839
11840 if (plane->fb != fb)
11841 if (plane->fb)
11842 intel_unpin_fb_obj(old_obj);
11843
11844 mutex_unlock(&dev->struct_mutex);
11845
11846 } else {
11847 if (intel_crtc && intel_crtc->active &&
11848 intel_crtc->primary_enabled) {
11849 /*
11850 * FBC does not work on some platforms for rotated
11851 * planes, so disable it when rotation is not 0 and
11852 * update it when rotation is set back to 0.
11853 *
11854 * FIXME: This is redundant with the fbc update done in
11855 * the primary plane enable function except that that
11856 * one is done too late. We eventually need to unify
11857 * this.
11858 */
11859 if (INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11860 dev_priv->fbc.plane == intel_crtc->plane &&
11861 intel_plane->rotation != BIT(DRM_ROTATE_0)) {
11862 intel_disable_fbc(dev);
11863 }
11864 }
11865 ret = intel_pipe_set_base(crtc, src->x1, src->y1, fb);
11866 if (ret)
11867 return ret;
11868
11869 if (!intel_crtc->primary_enabled)
11870 intel_enable_primary_hw_plane(plane, crtc);
11871 }
11872
11873 intel_plane->crtc_x = state->orig_dst.x1;
11874 intel_plane->crtc_y = state->orig_dst.y1;
11875 intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
11876 intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
11877 intel_plane->src_x = state->orig_src.x1;
11878 intel_plane->src_y = state->orig_src.y1;
11879 intel_plane->src_w = drm_rect_width(&state->orig_src);
11880 intel_plane->src_h = drm_rect_height(&state->orig_src);
11881 intel_plane->obj = obj;
11882
11883 return 0;
11884 }
11885
11886 static int
11887 intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11888 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11889 unsigned int crtc_w, unsigned int crtc_h,
11890 uint32_t src_x, uint32_t src_y,
11891 uint32_t src_w, uint32_t src_h)
11892 {
11893 struct intel_plane_state state;
11894 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11895 int ret;
11896
11897 state.crtc = crtc;
11898 state.fb = fb;
11899
11900 /* sample coordinates in 16.16 fixed point */
11901 state.src.x1 = src_x;
11902 state.src.x2 = src_x + src_w;
11903 state.src.y1 = src_y;
11904 state.src.y2 = src_y + src_h;
11905
11906 /* integer pixels */
11907 state.dst.x1 = crtc_x;
11908 state.dst.x2 = crtc_x + crtc_w;
11909 state.dst.y1 = crtc_y;
11910 state.dst.y2 = crtc_y + crtc_h;
11911
11912 state.clip.x1 = 0;
11913 state.clip.y1 = 0;
11914 state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
11915 state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
11916
11917 state.orig_src = state.src;
11918 state.orig_dst = state.dst;
11919
11920 ret = intel_check_primary_plane(plane, &state);
11921 if (ret)
11922 return ret;
11923
11924 intel_commit_primary_plane(plane, &state);
11925
11926 return 0;
11927 }
11928
11929 /* Common destruction function for both primary and cursor planes */
11930 static void intel_plane_destroy(struct drm_plane *plane)
11931 {
11932 struct intel_plane *intel_plane = to_intel_plane(plane);
11933 drm_plane_cleanup(plane);
11934 kfree(intel_plane);
11935 }
11936
11937 static const struct drm_plane_funcs intel_primary_plane_funcs = {
11938 .update_plane = intel_primary_plane_setplane,
11939 .disable_plane = intel_primary_plane_disable,
11940 .destroy = intel_plane_destroy,
11941 .set_property = intel_plane_set_property
11942 };
11943
11944 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11945 int pipe)
11946 {
11947 struct intel_plane *primary;
11948 const uint32_t *intel_primary_formats;
11949 int num_formats;
11950
11951 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11952 if (primary == NULL)
11953 return NULL;
11954
11955 primary->can_scale = false;
11956 primary->max_downscale = 1;
11957 primary->pipe = pipe;
11958 primary->plane = pipe;
11959 primary->rotation = BIT(DRM_ROTATE_0);
11960 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11961 primary->plane = !pipe;
11962
11963 if (INTEL_INFO(dev)->gen <= 3) {
11964 intel_primary_formats = intel_primary_formats_gen2;
11965 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
11966 } else {
11967 intel_primary_formats = intel_primary_formats_gen4;
11968 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
11969 }
11970
11971 drm_universal_plane_init(dev, &primary->base, 0,
11972 &intel_primary_plane_funcs,
11973 intel_primary_formats, num_formats,
11974 DRM_PLANE_TYPE_PRIMARY);
11975
11976 if (INTEL_INFO(dev)->gen >= 4) {
11977 if (!dev->mode_config.rotation_property)
11978 dev->mode_config.rotation_property =
11979 drm_mode_create_rotation_property(dev,
11980 BIT(DRM_ROTATE_0) |
11981 BIT(DRM_ROTATE_180));
11982 if (dev->mode_config.rotation_property)
11983 drm_object_attach_property(&primary->base.base,
11984 dev->mode_config.rotation_property,
11985 primary->rotation);
11986 }
11987
11988 return &primary->base;
11989 }
11990
11991 static int
11992 intel_cursor_plane_disable(struct drm_plane *plane)
11993 {
11994 if (!plane->fb)
11995 return 0;
11996
11997 BUG_ON(!plane->crtc);
11998
11999 return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
12000 }
12001
12002 static int
12003 intel_check_cursor_plane(struct drm_plane *plane,
12004 struct intel_plane_state *state)
12005 {
12006 struct drm_crtc *crtc = state->crtc;
12007 struct drm_framebuffer *fb = state->fb;
12008 struct drm_rect *dest = &state->dst;
12009 struct drm_rect *src = &state->src;
12010 const struct drm_rect *clip = &state->clip;
12011
12012 return drm_plane_helper_check_update(plane, crtc, fb,
12013 src, dest, clip,
12014 DRM_PLANE_HELPER_NO_SCALING,
12015 DRM_PLANE_HELPER_NO_SCALING,
12016 true, true, &state->visible);
12017 }
12018
12019 static int
12020 intel_commit_cursor_plane(struct drm_plane *plane,
12021 struct intel_plane_state *state)
12022 {
12023 struct drm_crtc *crtc = state->crtc;
12024 struct drm_framebuffer *fb = state->fb;
12025 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12026 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12027 struct drm_i915_gem_object *obj = intel_fb->obj;
12028 int crtc_w, crtc_h;
12029
12030 crtc->cursor_x = state->orig_dst.x1;
12031 crtc->cursor_y = state->orig_dst.y1;
12032 if (fb != crtc->cursor->fb) {
12033 crtc_w = drm_rect_width(&state->orig_dst);
12034 crtc_h = drm_rect_height(&state->orig_dst);
12035 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
12036 } else {
12037 intel_crtc_update_cursor(crtc, state->visible);
12038
12039 intel_frontbuffer_flip(crtc->dev,
12040 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe));
12041
12042 return 0;
12043 }
12044 }
12045
12046 static int
12047 intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
12048 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
12049 unsigned int crtc_w, unsigned int crtc_h,
12050 uint32_t src_x, uint32_t src_y,
12051 uint32_t src_w, uint32_t src_h)
12052 {
12053 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12054 struct intel_plane_state state;
12055 int ret;
12056
12057 state.crtc = crtc;
12058 state.fb = fb;
12059
12060 /* sample coordinates in 16.16 fixed point */
12061 state.src.x1 = src_x;
12062 state.src.x2 = src_x + src_w;
12063 state.src.y1 = src_y;
12064 state.src.y2 = src_y + src_h;
12065
12066 /* integer pixels */
12067 state.dst.x1 = crtc_x;
12068 state.dst.x2 = crtc_x + crtc_w;
12069 state.dst.y1 = crtc_y;
12070 state.dst.y2 = crtc_y + crtc_h;
12071
12072 state.clip.x1 = 0;
12073 state.clip.y1 = 0;
12074 state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
12075 state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
12076
12077 state.orig_src = state.src;
12078 state.orig_dst = state.dst;
12079
12080 ret = intel_check_cursor_plane(plane, &state);
12081 if (ret)
12082 return ret;
12083
12084 return intel_commit_cursor_plane(plane, &state);
12085 }
12086
12087 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
12088 .update_plane = intel_cursor_plane_update,
12089 .disable_plane = intel_cursor_plane_disable,
12090 .destroy = intel_plane_destroy,
12091 };
12092
12093 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12094 int pipe)
12095 {
12096 struct intel_plane *cursor;
12097
12098 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12099 if (cursor == NULL)
12100 return NULL;
12101
12102 cursor->can_scale = false;
12103 cursor->max_downscale = 1;
12104 cursor->pipe = pipe;
12105 cursor->plane = pipe;
12106
12107 drm_universal_plane_init(dev, &cursor->base, 0,
12108 &intel_cursor_plane_funcs,
12109 intel_cursor_formats,
12110 ARRAY_SIZE(intel_cursor_formats),
12111 DRM_PLANE_TYPE_CURSOR);
12112 return &cursor->base;
12113 }
12114
12115 static void intel_crtc_init(struct drm_device *dev, int pipe)
12116 {
12117 struct drm_i915_private *dev_priv = dev->dev_private;
12118 struct intel_crtc *intel_crtc;
12119 struct drm_plane *primary = NULL;
12120 struct drm_plane *cursor = NULL;
12121 int i, ret;
12122
12123 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12124 if (intel_crtc == NULL)
12125 return;
12126
12127 primary = intel_primary_plane_create(dev, pipe);
12128 if (!primary)
12129 goto fail;
12130
12131 cursor = intel_cursor_plane_create(dev, pipe);
12132 if (!cursor)
12133 goto fail;
12134
12135 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12136 cursor, &intel_crtc_funcs);
12137 if (ret)
12138 goto fail;
12139
12140 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12141 for (i = 0; i < 256; i++) {
12142 intel_crtc->lut_r[i] = i;
12143 intel_crtc->lut_g[i] = i;
12144 intel_crtc->lut_b[i] = i;
12145 }
12146
12147 /*
12148 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12149 * is hooked to pipe B. Hence we want plane A feeding pipe B.
12150 */
12151 intel_crtc->pipe = pipe;
12152 intel_crtc->plane = pipe;
12153 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12154 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12155 intel_crtc->plane = !pipe;
12156 }
12157
12158 intel_crtc->cursor_base = ~0;
12159 intel_crtc->cursor_cntl = ~0;
12160 intel_crtc->cursor_size = ~0;
12161
12162 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12163 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12164 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12165 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12166
12167 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12168
12169 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12170 return;
12171
12172 fail:
12173 if (primary)
12174 drm_plane_cleanup(primary);
12175 if (cursor)
12176 drm_plane_cleanup(cursor);
12177 kfree(intel_crtc);
12178 }
12179
12180 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12181 {
12182 struct drm_encoder *encoder = connector->base.encoder;
12183 struct drm_device *dev = connector->base.dev;
12184
12185 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12186
12187 if (!encoder)
12188 return INVALID_PIPE;
12189
12190 return to_intel_crtc(encoder->crtc)->pipe;
12191 }
12192
12193 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12194 struct drm_file *file)
12195 {
12196 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12197 struct drm_crtc *drmmode_crtc;
12198 struct intel_crtc *crtc;
12199
12200 if (!drm_core_check_feature(dev, DRIVER_MODESET))
12201 return -ENODEV;
12202
12203 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12204
12205 if (!drmmode_crtc) {
12206 DRM_ERROR("no such CRTC id\n");
12207 return -ENOENT;
12208 }
12209
12210 crtc = to_intel_crtc(drmmode_crtc);
12211 pipe_from_crtc_id->pipe = crtc->pipe;
12212
12213 return 0;
12214 }
12215
12216 static int intel_encoder_clones(struct intel_encoder *encoder)
12217 {
12218 struct drm_device *dev = encoder->base.dev;
12219 struct intel_encoder *source_encoder;
12220 int index_mask = 0;
12221 int entry = 0;
12222
12223 for_each_intel_encoder(dev, source_encoder) {
12224 if (encoders_cloneable(encoder, source_encoder))
12225 index_mask |= (1 << entry);
12226
12227 entry++;
12228 }
12229
12230 return index_mask;
12231 }
12232
12233 static bool has_edp_a(struct drm_device *dev)
12234 {
12235 struct drm_i915_private *dev_priv = dev->dev_private;
12236
12237 if (!IS_MOBILE(dev))
12238 return false;
12239
12240 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12241 return false;
12242
12243 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12244 return false;
12245
12246 return true;
12247 }
12248
12249 const char *intel_output_name(int output)
12250 {
12251 static const char *names[] = {
12252 [INTEL_OUTPUT_UNUSED] = "Unused",
12253 [INTEL_OUTPUT_ANALOG] = "Analog",
12254 [INTEL_OUTPUT_DVO] = "DVO",
12255 [INTEL_OUTPUT_SDVO] = "SDVO",
12256 [INTEL_OUTPUT_LVDS] = "LVDS",
12257 [INTEL_OUTPUT_TVOUT] = "TV",
12258 [INTEL_OUTPUT_HDMI] = "HDMI",
12259 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
12260 [INTEL_OUTPUT_EDP] = "eDP",
12261 [INTEL_OUTPUT_DSI] = "DSI",
12262 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
12263 };
12264
12265 if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
12266 return "Invalid";
12267
12268 return names[output];
12269 }
12270
12271 static bool intel_crt_present(struct drm_device *dev)
12272 {
12273 struct drm_i915_private *dev_priv = dev->dev_private;
12274
12275 if (IS_ULT(dev))
12276 return false;
12277
12278 if (IS_CHERRYVIEW(dev))
12279 return false;
12280
12281 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12282 return false;
12283
12284 return true;
12285 }
12286
12287 static void intel_setup_outputs(struct drm_device *dev)
12288 {
12289 struct drm_i915_private *dev_priv = dev->dev_private;
12290 struct intel_encoder *encoder;
12291 bool dpd_is_edp = false;
12292
12293 intel_lvds_init(dev);
12294
12295 if (intel_crt_present(dev))
12296 intel_crt_init(dev);
12297
12298 if (HAS_DDI(dev)) {
12299 int found;
12300
12301 /* Haswell uses DDI functions to detect digital outputs */
12302 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12303 /* DDI A only supports eDP */
12304 if (found)
12305 intel_ddi_init(dev, PORT_A);
12306
12307 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12308 * register */
12309 found = I915_READ(SFUSE_STRAP);
12310
12311 if (found & SFUSE_STRAP_DDIB_DETECTED)
12312 intel_ddi_init(dev, PORT_B);
12313 if (found & SFUSE_STRAP_DDIC_DETECTED)
12314 intel_ddi_init(dev, PORT_C);
12315 if (found & SFUSE_STRAP_DDID_DETECTED)
12316 intel_ddi_init(dev, PORT_D);
12317 } else if (HAS_PCH_SPLIT(dev)) {
12318 int found;
12319 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12320
12321 if (has_edp_a(dev))
12322 intel_dp_init(dev, DP_A, PORT_A);
12323
12324 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12325 /* PCH SDVOB multiplex with HDMIB */
12326 found = intel_sdvo_init(dev, PCH_SDVOB, true);
12327 if (!found)
12328 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12329 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12330 intel_dp_init(dev, PCH_DP_B, PORT_B);
12331 }
12332
12333 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12334 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12335
12336 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12337 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12338
12339 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12340 intel_dp_init(dev, PCH_DP_C, PORT_C);
12341
12342 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12343 intel_dp_init(dev, PCH_DP_D, PORT_D);
12344 } else if (IS_VALLEYVIEW(dev)) {
12345 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
12346 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12347 PORT_B);
12348 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
12349 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12350 }
12351
12352 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
12353 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12354 PORT_C);
12355 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
12356 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12357 }
12358
12359 if (IS_CHERRYVIEW(dev)) {
12360 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) {
12361 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12362 PORT_D);
12363 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12364 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12365 }
12366 }
12367
12368 intel_dsi_init(dev);
12369 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12370 bool found = false;
12371
12372 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12373 DRM_DEBUG_KMS("probing SDVOB\n");
12374 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12375 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12376 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12377 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12378 }
12379
12380 if (!found && SUPPORTS_INTEGRATED_DP(dev))
12381 intel_dp_init(dev, DP_B, PORT_B);
12382 }
12383
12384 /* Before G4X SDVOC doesn't have its own detect register */
12385
12386 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12387 DRM_DEBUG_KMS("probing SDVOC\n");
12388 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12389 }
12390
12391 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12392
12393 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12394 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12395 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12396 }
12397 if (SUPPORTS_INTEGRATED_DP(dev))
12398 intel_dp_init(dev, DP_C, PORT_C);
12399 }
12400
12401 if (SUPPORTS_INTEGRATED_DP(dev) &&
12402 (I915_READ(DP_D) & DP_DETECTED))
12403 intel_dp_init(dev, DP_D, PORT_D);
12404 } else if (IS_GEN2(dev))
12405 intel_dvo_init(dev);
12406
12407 if (SUPPORTS_TV(dev))
12408 intel_tv_init(dev);
12409
12410 intel_edp_psr_init(dev);
12411
12412 for_each_intel_encoder(dev, encoder) {
12413 encoder->base.possible_crtcs = encoder->crtc_mask;
12414 encoder->base.possible_clones =
12415 intel_encoder_clones(encoder);
12416 }
12417
12418 intel_init_pch_refclk(dev);
12419
12420 drm_helper_move_panel_connectors_to_head(dev);
12421 }
12422
12423 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12424 {
12425 struct drm_device *dev = fb->dev;
12426 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12427
12428 drm_framebuffer_cleanup(fb);
12429 mutex_lock(&dev->struct_mutex);
12430 WARN_ON(!intel_fb->obj->framebuffer_references--);
12431 drm_gem_object_unreference(&intel_fb->obj->base);
12432 mutex_unlock(&dev->struct_mutex);
12433 kfree(intel_fb);
12434 }
12435
12436 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12437 struct drm_file *file,
12438 unsigned int *handle)
12439 {
12440 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12441 struct drm_i915_gem_object *obj = intel_fb->obj;
12442
12443 return drm_gem_handle_create(file, &obj->base, handle);
12444 }
12445
12446 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12447 .destroy = intel_user_framebuffer_destroy,
12448 .create_handle = intel_user_framebuffer_create_handle,
12449 };
12450
12451 static int intel_framebuffer_init(struct drm_device *dev,
12452 struct intel_framebuffer *intel_fb,
12453 struct drm_mode_fb_cmd2 *mode_cmd,
12454 struct drm_i915_gem_object *obj)
12455 {
12456 int aligned_height;
12457 int pitch_limit;
12458 int ret;
12459
12460 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12461
12462 if (obj->tiling_mode == I915_TILING_Y) {
12463 DRM_DEBUG("hardware does not support tiling Y\n");
12464 return -EINVAL;
12465 }
12466
12467 if (mode_cmd->pitches[0] & 63) {
12468 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12469 mode_cmd->pitches[0]);
12470 return -EINVAL;
12471 }
12472
12473 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12474 pitch_limit = 32*1024;
12475 } else if (INTEL_INFO(dev)->gen >= 4) {
12476 if (obj->tiling_mode)
12477 pitch_limit = 16*1024;
12478 else
12479 pitch_limit = 32*1024;
12480 } else if (INTEL_INFO(dev)->gen >= 3) {
12481 if (obj->tiling_mode)
12482 pitch_limit = 8*1024;
12483 else
12484 pitch_limit = 16*1024;
12485 } else
12486 /* XXX DSPC is limited to 4k tiled */
12487 pitch_limit = 8*1024;
12488
12489 if (mode_cmd->pitches[0] > pitch_limit) {
12490 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12491 obj->tiling_mode ? "tiled" : "linear",
12492 mode_cmd->pitches[0], pitch_limit);
12493 return -EINVAL;
12494 }
12495
12496 if (obj->tiling_mode != I915_TILING_NONE &&
12497 mode_cmd->pitches[0] != obj->stride) {
12498 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12499 mode_cmd->pitches[0], obj->stride);
12500 return -EINVAL;
12501 }
12502
12503 /* Reject formats not supported by any plane early. */
12504 switch (mode_cmd->pixel_format) {
12505 case DRM_FORMAT_C8:
12506 case DRM_FORMAT_RGB565:
12507 case DRM_FORMAT_XRGB8888:
12508 case DRM_FORMAT_ARGB8888:
12509 break;
12510 case DRM_FORMAT_XRGB1555:
12511 case DRM_FORMAT_ARGB1555:
12512 if (INTEL_INFO(dev)->gen > 3) {
12513 DRM_DEBUG("unsupported pixel format: %s\n",
12514 drm_get_format_name(mode_cmd->pixel_format));
12515 return -EINVAL;
12516 }
12517 break;
12518 case DRM_FORMAT_XBGR8888:
12519 case DRM_FORMAT_ABGR8888:
12520 case DRM_FORMAT_XRGB2101010:
12521 case DRM_FORMAT_ARGB2101010:
12522 case DRM_FORMAT_XBGR2101010:
12523 case DRM_FORMAT_ABGR2101010:
12524 if (INTEL_INFO(dev)->gen < 4) {
12525 DRM_DEBUG("unsupported pixel format: %s\n",
12526 drm_get_format_name(mode_cmd->pixel_format));
12527 return -EINVAL;
12528 }
12529 break;
12530 case DRM_FORMAT_YUYV:
12531 case DRM_FORMAT_UYVY:
12532 case DRM_FORMAT_YVYU:
12533 case DRM_FORMAT_VYUY:
12534 if (INTEL_INFO(dev)->gen < 5) {
12535 DRM_DEBUG("unsupported pixel format: %s\n",
12536 drm_get_format_name(mode_cmd->pixel_format));
12537 return -EINVAL;
12538 }
12539 break;
12540 default:
12541 DRM_DEBUG("unsupported pixel format: %s\n",
12542 drm_get_format_name(mode_cmd->pixel_format));
12543 return -EINVAL;
12544 }
12545
12546 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12547 if (mode_cmd->offsets[0] != 0)
12548 return -EINVAL;
12549
12550 aligned_height = intel_align_height(dev, mode_cmd->height,
12551 obj->tiling_mode);
12552 /* FIXME drm helper for size checks (especially planar formats)? */
12553 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12554 return -EINVAL;
12555
12556 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12557 intel_fb->obj = obj;
12558 intel_fb->obj->framebuffer_references++;
12559
12560 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12561 if (ret) {
12562 DRM_ERROR("framebuffer init failed %d\n", ret);
12563 return ret;
12564 }
12565
12566 return 0;
12567 }
12568
12569 static struct drm_framebuffer *
12570 intel_user_framebuffer_create(struct drm_device *dev,
12571 struct drm_file *filp,
12572 struct drm_mode_fb_cmd2 *mode_cmd)
12573 {
12574 struct drm_i915_gem_object *obj;
12575
12576 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12577 mode_cmd->handles[0]));
12578 if (&obj->base == NULL)
12579 return ERR_PTR(-ENOENT);
12580
12581 return intel_framebuffer_create(dev, mode_cmd, obj);
12582 }
12583
12584 #ifndef CONFIG_DRM_I915_FBDEV
12585 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12586 {
12587 }
12588 #endif
12589
12590 static const struct drm_mode_config_funcs intel_mode_funcs = {
12591 .fb_create = intel_user_framebuffer_create,
12592 .output_poll_changed = intel_fbdev_output_poll_changed,
12593 };
12594
12595 /* Set up chip specific display functions */
12596 static void intel_init_display(struct drm_device *dev)
12597 {
12598 struct drm_i915_private *dev_priv = dev->dev_private;
12599
12600 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12601 dev_priv->display.find_dpll = g4x_find_best_dpll;
12602 else if (IS_CHERRYVIEW(dev))
12603 dev_priv->display.find_dpll = chv_find_best_dpll;
12604 else if (IS_VALLEYVIEW(dev))
12605 dev_priv->display.find_dpll = vlv_find_best_dpll;
12606 else if (IS_PINEVIEW(dev))
12607 dev_priv->display.find_dpll = pnv_find_best_dpll;
12608 else
12609 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12610
12611 if (HAS_DDI(dev)) {
12612 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12613 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12614 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
12615 dev_priv->display.crtc_enable = haswell_crtc_enable;
12616 dev_priv->display.crtc_disable = haswell_crtc_disable;
12617 dev_priv->display.off = ironlake_crtc_off;
12618 dev_priv->display.update_primary_plane =
12619 ironlake_update_primary_plane;
12620 } else if (HAS_PCH_SPLIT(dev)) {
12621 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12622 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12623 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
12624 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12625 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12626 dev_priv->display.off = ironlake_crtc_off;
12627 dev_priv->display.update_primary_plane =
12628 ironlake_update_primary_plane;
12629 } else if (IS_VALLEYVIEW(dev)) {
12630 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12631 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12632 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12633 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12634 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12635 dev_priv->display.off = i9xx_crtc_off;
12636 dev_priv->display.update_primary_plane =
12637 i9xx_update_primary_plane;
12638 } else {
12639 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12640 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12641 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12642 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12643 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12644 dev_priv->display.off = i9xx_crtc_off;
12645 dev_priv->display.update_primary_plane =
12646 i9xx_update_primary_plane;
12647 }
12648
12649 /* Returns the core display clock speed */
12650 if (IS_VALLEYVIEW(dev))
12651 dev_priv->display.get_display_clock_speed =
12652 valleyview_get_display_clock_speed;
12653 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12654 dev_priv->display.get_display_clock_speed =
12655 i945_get_display_clock_speed;
12656 else if (IS_I915G(dev))
12657 dev_priv->display.get_display_clock_speed =
12658 i915_get_display_clock_speed;
12659 else if (IS_I945GM(dev) || IS_845G(dev))
12660 dev_priv->display.get_display_clock_speed =
12661 i9xx_misc_get_display_clock_speed;
12662 else if (IS_PINEVIEW(dev))
12663 dev_priv->display.get_display_clock_speed =
12664 pnv_get_display_clock_speed;
12665 else if (IS_I915GM(dev))
12666 dev_priv->display.get_display_clock_speed =
12667 i915gm_get_display_clock_speed;
12668 else if (IS_I865G(dev))
12669 dev_priv->display.get_display_clock_speed =
12670 i865_get_display_clock_speed;
12671 else if (IS_I85X(dev))
12672 dev_priv->display.get_display_clock_speed =
12673 i855_get_display_clock_speed;
12674 else /* 852, 830 */
12675 dev_priv->display.get_display_clock_speed =
12676 i830_get_display_clock_speed;
12677
12678 if (IS_G4X(dev)) {
12679 dev_priv->display.write_eld = g4x_write_eld;
12680 } else if (IS_GEN5(dev)) {
12681 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12682 dev_priv->display.write_eld = ironlake_write_eld;
12683 } else if (IS_GEN6(dev)) {
12684 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12685 dev_priv->display.write_eld = ironlake_write_eld;
12686 dev_priv->display.modeset_global_resources =
12687 snb_modeset_global_resources;
12688 } else if (IS_IVYBRIDGE(dev)) {
12689 /* FIXME: detect B0+ stepping and use auto training */
12690 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12691 dev_priv->display.write_eld = ironlake_write_eld;
12692 dev_priv->display.modeset_global_resources =
12693 ivb_modeset_global_resources;
12694 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12695 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12696 dev_priv->display.write_eld = haswell_write_eld;
12697 dev_priv->display.modeset_global_resources =
12698 haswell_modeset_global_resources;
12699 } else if (IS_VALLEYVIEW(dev)) {
12700 dev_priv->display.modeset_global_resources =
12701 valleyview_modeset_global_resources;
12702 dev_priv->display.write_eld = ironlake_write_eld;
12703 }
12704
12705 /* Default just returns -ENODEV to indicate unsupported */
12706 dev_priv->display.queue_flip = intel_default_queue_flip;
12707
12708 switch (INTEL_INFO(dev)->gen) {
12709 case 2:
12710 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12711 break;
12712
12713 case 3:
12714 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12715 break;
12716
12717 case 4:
12718 case 5:
12719 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12720 break;
12721
12722 case 6:
12723 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12724 break;
12725 case 7:
12726 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12727 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12728 break;
12729 }
12730
12731 intel_panel_init_backlight_funcs(dev);
12732
12733 mutex_init(&dev_priv->pps_mutex);
12734 }
12735
12736 /*
12737 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12738 * resume, or other times. This quirk makes sure that's the case for
12739 * affected systems.
12740 */
12741 static void quirk_pipea_force(struct drm_device *dev)
12742 {
12743 struct drm_i915_private *dev_priv = dev->dev_private;
12744
12745 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12746 DRM_INFO("applying pipe a force quirk\n");
12747 }
12748
12749 static void quirk_pipeb_force(struct drm_device *dev)
12750 {
12751 struct drm_i915_private *dev_priv = dev->dev_private;
12752
12753 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
12754 DRM_INFO("applying pipe b force quirk\n");
12755 }
12756
12757 /*
12758 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12759 */
12760 static void quirk_ssc_force_disable(struct drm_device *dev)
12761 {
12762 struct drm_i915_private *dev_priv = dev->dev_private;
12763 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12764 DRM_INFO("applying lvds SSC disable quirk\n");
12765 }
12766
12767 /*
12768 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12769 * brightness value
12770 */
12771 static void quirk_invert_brightness(struct drm_device *dev)
12772 {
12773 struct drm_i915_private *dev_priv = dev->dev_private;
12774 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
12775 DRM_INFO("applying inverted panel brightness quirk\n");
12776 }
12777
12778 /* Some VBT's incorrectly indicate no backlight is present */
12779 static void quirk_backlight_present(struct drm_device *dev)
12780 {
12781 struct drm_i915_private *dev_priv = dev->dev_private;
12782 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
12783 DRM_INFO("applying backlight present quirk\n");
12784 }
12785
12786 struct intel_quirk {
12787 int device;
12788 int subsystem_vendor;
12789 int subsystem_device;
12790 void (*hook)(struct drm_device *dev);
12791 };
12792
12793 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12794 struct intel_dmi_quirk {
12795 void (*hook)(struct drm_device *dev);
12796 const struct dmi_system_id (*dmi_id_list)[];
12797 };
12798
12799 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12800 {
12801 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12802 return 1;
12803 }
12804
12805 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12806 {
12807 .dmi_id_list = &(const struct dmi_system_id[]) {
12808 {
12809 .callback = intel_dmi_reverse_brightness,
12810 .ident = "NCR Corporation",
12811 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12812 DMI_MATCH(DMI_PRODUCT_NAME, ""),
12813 },
12814 },
12815 { } /* terminating entry */
12816 },
12817 .hook = quirk_invert_brightness,
12818 },
12819 };
12820
12821 static struct intel_quirk intel_quirks[] = {
12822 /* HP Mini needs pipe A force quirk (LP: #322104) */
12823 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
12824
12825 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12826 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12827
12828 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12829 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12830
12831 /* 830 needs to leave pipe A & dpll A up */
12832 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
12833
12834 /* 830 needs to leave pipe B & dpll B up */
12835 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
12836
12837 /* Lenovo U160 cannot use SSC on LVDS */
12838 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
12839
12840 /* Sony Vaio Y cannot use SSC on LVDS */
12841 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
12842
12843 /* Acer Aspire 5734Z must invert backlight brightness */
12844 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12845
12846 /* Acer/eMachines G725 */
12847 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12848
12849 /* Acer/eMachines e725 */
12850 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12851
12852 /* Acer/Packard Bell NCL20 */
12853 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12854
12855 /* Acer Aspire 4736Z */
12856 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
12857
12858 /* Acer Aspire 5336 */
12859 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
12860
12861 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12862 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
12863
12864 /* Acer C720 Chromebook (Core i3 4005U) */
12865 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
12866
12867 /* Toshiba CB35 Chromebook (Celeron 2955U) */
12868 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
12869
12870 /* HP Chromebook 14 (Celeron 2955U) */
12871 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
12872 };
12873
12874 static void intel_init_quirks(struct drm_device *dev)
12875 {
12876 struct pci_dev *d = dev->pdev;
12877 int i;
12878
12879 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12880 struct intel_quirk *q = &intel_quirks[i];
12881
12882 if (d->device == q->device &&
12883 (d->subsystem_vendor == q->subsystem_vendor ||
12884 q->subsystem_vendor == PCI_ANY_ID) &&
12885 (d->subsystem_device == q->subsystem_device ||
12886 q->subsystem_device == PCI_ANY_ID))
12887 q->hook(dev);
12888 }
12889 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12890 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12891 intel_dmi_quirks[i].hook(dev);
12892 }
12893 }
12894
12895 /* Disable the VGA plane that we never use */
12896 static void i915_disable_vga(struct drm_device *dev)
12897 {
12898 struct drm_i915_private *dev_priv = dev->dev_private;
12899 u8 sr1;
12900 u32 vga_reg = i915_vgacntrl_reg(dev);
12901
12902 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12903 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
12904 outb(SR01, VGA_SR_INDEX);
12905 sr1 = inb(VGA_SR_DATA);
12906 outb(sr1 | 1<<5, VGA_SR_DATA);
12907 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12908 udelay(300);
12909
12910 /*
12911 * Fujitsu-Siemens Lifebook S6010 (830) has problems resuming
12912 * from S3 without preserving (some of?) the other bits.
12913 */
12914 I915_WRITE(vga_reg, dev_priv->bios_vgacntr | VGA_DISP_DISABLE);
12915 POSTING_READ(vga_reg);
12916 }
12917
12918 void intel_modeset_init_hw(struct drm_device *dev)
12919 {
12920 intel_prepare_ddi(dev);
12921
12922 if (IS_VALLEYVIEW(dev))
12923 vlv_update_cdclk(dev);
12924
12925 intel_init_clock_gating(dev);
12926
12927 intel_enable_gt_powersave(dev);
12928 }
12929
12930 void intel_modeset_suspend_hw(struct drm_device *dev)
12931 {
12932 intel_suspend_hw(dev);
12933 }
12934
12935 void intel_modeset_init(struct drm_device *dev)
12936 {
12937 struct drm_i915_private *dev_priv = dev->dev_private;
12938 int sprite, ret;
12939 enum pipe pipe;
12940 struct intel_crtc *crtc;
12941
12942 drm_mode_config_init(dev);
12943
12944 dev->mode_config.min_width = 0;
12945 dev->mode_config.min_height = 0;
12946
12947 dev->mode_config.preferred_depth = 24;
12948 dev->mode_config.prefer_shadow = 1;
12949
12950 dev->mode_config.funcs = &intel_mode_funcs;
12951
12952 intel_init_quirks(dev);
12953
12954 intel_init_pm(dev);
12955
12956 if (INTEL_INFO(dev)->num_pipes == 0)
12957 return;
12958
12959 intel_init_display(dev);
12960
12961 if (IS_GEN2(dev)) {
12962 dev->mode_config.max_width = 2048;
12963 dev->mode_config.max_height = 2048;
12964 } else if (IS_GEN3(dev)) {
12965 dev->mode_config.max_width = 4096;
12966 dev->mode_config.max_height = 4096;
12967 } else {
12968 dev->mode_config.max_width = 8192;
12969 dev->mode_config.max_height = 8192;
12970 }
12971
12972 if (IS_845G(dev) || IS_I865G(dev)) {
12973 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
12974 dev->mode_config.cursor_height = 1023;
12975 } else if (IS_GEN2(dev)) {
12976 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
12977 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
12978 } else {
12979 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
12980 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
12981 }
12982
12983 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
12984
12985 DRM_DEBUG_KMS("%d display pipe%s available.\n",
12986 INTEL_INFO(dev)->num_pipes,
12987 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
12988
12989 for_each_pipe(dev_priv, pipe) {
12990 intel_crtc_init(dev, pipe);
12991 for_each_sprite(pipe, sprite) {
12992 ret = intel_plane_init(dev, pipe, sprite);
12993 if (ret)
12994 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
12995 pipe_name(pipe), sprite_name(pipe, sprite), ret);
12996 }
12997 }
12998
12999 intel_init_dpio(dev);
13000
13001 intel_shared_dpll_init(dev);
13002
13003 /* save the BIOS value before clobbering it */
13004 dev_priv->bios_vgacntr = I915_READ(i915_vgacntrl_reg(dev));
13005 /* Just disable it once at startup */
13006 i915_disable_vga(dev);
13007 intel_setup_outputs(dev);
13008
13009 /* Just in case the BIOS is doing something questionable. */
13010 intel_disable_fbc(dev);
13011
13012 drm_modeset_lock_all(dev);
13013 intel_modeset_setup_hw_state(dev, false);
13014 drm_modeset_unlock_all(dev);
13015
13016 for_each_intel_crtc(dev, crtc) {
13017 if (!crtc->active)
13018 continue;
13019
13020 /*
13021 * Note that reserving the BIOS fb up front prevents us
13022 * from stuffing other stolen allocations like the ring
13023 * on top. This prevents some ugliness at boot time, and
13024 * can even allow for smooth boot transitions if the BIOS
13025 * fb is large enough for the active pipe configuration.
13026 */
13027 if (dev_priv->display.get_plane_config) {
13028 dev_priv->display.get_plane_config(crtc,
13029 &crtc->plane_config);
13030 /*
13031 * If the fb is shared between multiple heads, we'll
13032 * just get the first one.
13033 */
13034 intel_find_plane_obj(crtc, &crtc->plane_config);
13035 }
13036 }
13037 }
13038
13039 static void intel_enable_pipe_a(struct drm_device *dev)
13040 {
13041 struct intel_connector *connector;
13042 struct drm_connector *crt = NULL;
13043 struct intel_load_detect_pipe load_detect_temp;
13044 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
13045
13046 /* We can't just switch on the pipe A, we need to set things up with a
13047 * proper mode and output configuration. As a gross hack, enable pipe A
13048 * by enabling the load detect pipe once. */
13049 list_for_each_entry(connector,
13050 &dev->mode_config.connector_list,
13051 base.head) {
13052 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13053 crt = &connector->base;
13054 break;
13055 }
13056 }
13057
13058 if (!crt)
13059 return;
13060
13061 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13062 intel_release_load_detect_pipe(crt, &load_detect_temp);
13063 }
13064
13065 static bool
13066 intel_check_plane_mapping(struct intel_crtc *crtc)
13067 {
13068 struct drm_device *dev = crtc->base.dev;
13069 struct drm_i915_private *dev_priv = dev->dev_private;
13070 u32 reg, val;
13071
13072 if (INTEL_INFO(dev)->num_pipes == 1)
13073 return true;
13074
13075 reg = DSPCNTR(!crtc->plane);
13076 val = I915_READ(reg);
13077
13078 if ((val & DISPLAY_PLANE_ENABLE) &&
13079 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13080 return false;
13081
13082 return true;
13083 }
13084
13085 static void intel_sanitize_crtc(struct intel_crtc *crtc)
13086 {
13087 struct drm_device *dev = crtc->base.dev;
13088 struct drm_i915_private *dev_priv = dev->dev_private;
13089 u32 reg;
13090
13091 /* Clear any frame start delays used for debugging left by the BIOS */
13092 reg = PIPECONF(crtc->config.cpu_transcoder);
13093 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13094
13095 /* restore vblank interrupts to correct state */
13096 if (crtc->active) {
13097 update_scanline_offset(crtc);
13098 drm_vblank_on(dev, crtc->pipe);
13099 } else
13100 drm_vblank_off(dev, crtc->pipe);
13101
13102 /* We need to sanitize the plane -> pipe mapping first because this will
13103 * disable the crtc (and hence change the state) if it is wrong. Note
13104 * that gen4+ has a fixed plane -> pipe mapping. */
13105 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13106 struct intel_connector *connector;
13107 bool plane;
13108
13109 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13110 crtc->base.base.id);
13111
13112 /* Pipe has the wrong plane attached and the plane is active.
13113 * Temporarily change the plane mapping and disable everything
13114 * ... */
13115 plane = crtc->plane;
13116 crtc->plane = !plane;
13117 crtc->primary_enabled = true;
13118 dev_priv->display.crtc_disable(&crtc->base);
13119 crtc->plane = plane;
13120
13121 /* ... and break all links. */
13122 list_for_each_entry(connector, &dev->mode_config.connector_list,
13123 base.head) {
13124 if (connector->encoder->base.crtc != &crtc->base)
13125 continue;
13126
13127 connector->base.dpms = DRM_MODE_DPMS_OFF;
13128 connector->base.encoder = NULL;
13129 }
13130 /* multiple connectors may have the same encoder:
13131 * handle them and break crtc link separately */
13132 list_for_each_entry(connector, &dev->mode_config.connector_list,
13133 base.head)
13134 if (connector->encoder->base.crtc == &crtc->base) {
13135 connector->encoder->base.crtc = NULL;
13136 connector->encoder->connectors_active = false;
13137 }
13138
13139 WARN_ON(crtc->active);
13140 crtc->base.enabled = false;
13141 }
13142
13143 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13144 crtc->pipe == PIPE_A && !crtc->active) {
13145 /* BIOS forgot to enable pipe A, this mostly happens after
13146 * resume. Force-enable the pipe to fix this, the update_dpms
13147 * call below we restore the pipe to the right state, but leave
13148 * the required bits on. */
13149 intel_enable_pipe_a(dev);
13150 }
13151
13152 /* Adjust the state of the output pipe according to whether we
13153 * have active connectors/encoders. */
13154 intel_crtc_update_dpms(&crtc->base);
13155
13156 if (crtc->active != crtc->base.enabled) {
13157 struct intel_encoder *encoder;
13158
13159 /* This can happen either due to bugs in the get_hw_state
13160 * functions or because the pipe is force-enabled due to the
13161 * pipe A quirk. */
13162 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13163 crtc->base.base.id,
13164 crtc->base.enabled ? "enabled" : "disabled",
13165 crtc->active ? "enabled" : "disabled");
13166
13167 crtc->base.enabled = crtc->active;
13168
13169 /* Because we only establish the connector -> encoder ->
13170 * crtc links if something is active, this means the
13171 * crtc is now deactivated. Break the links. connector
13172 * -> encoder links are only establish when things are
13173 * actually up, hence no need to break them. */
13174 WARN_ON(crtc->active);
13175
13176 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13177 WARN_ON(encoder->connectors_active);
13178 encoder->base.crtc = NULL;
13179 }
13180 }
13181
13182 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13183 /*
13184 * We start out with underrun reporting disabled to avoid races.
13185 * For correct bookkeeping mark this on active crtcs.
13186 *
13187 * Also on gmch platforms we dont have any hardware bits to
13188 * disable the underrun reporting. Which means we need to start
13189 * out with underrun reporting disabled also on inactive pipes,
13190 * since otherwise we'll complain about the garbage we read when
13191 * e.g. coming up after runtime pm.
13192 *
13193 * No protection against concurrent access is required - at
13194 * worst a fifo underrun happens which also sets this to false.
13195 */
13196 crtc->cpu_fifo_underrun_disabled = true;
13197 crtc->pch_fifo_underrun_disabled = true;
13198 }
13199 }
13200
13201 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13202 {
13203 struct intel_connector *connector;
13204 struct drm_device *dev = encoder->base.dev;
13205
13206 /* We need to check both for a crtc link (meaning that the
13207 * encoder is active and trying to read from a pipe) and the
13208 * pipe itself being active. */
13209 bool has_active_crtc = encoder->base.crtc &&
13210 to_intel_crtc(encoder->base.crtc)->active;
13211
13212 if (encoder->connectors_active && !has_active_crtc) {
13213 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13214 encoder->base.base.id,
13215 encoder->base.name);
13216
13217 /* Connector is active, but has no active pipe. This is
13218 * fallout from our resume register restoring. Disable
13219 * the encoder manually again. */
13220 if (encoder->base.crtc) {
13221 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13222 encoder->base.base.id,
13223 encoder->base.name);
13224 encoder->disable(encoder);
13225 if (encoder->post_disable)
13226 encoder->post_disable(encoder);
13227 }
13228 encoder->base.crtc = NULL;
13229 encoder->connectors_active = false;
13230
13231 /* Inconsistent output/port/pipe state happens presumably due to
13232 * a bug in one of the get_hw_state functions. Or someplace else
13233 * in our code, like the register restore mess on resume. Clamp
13234 * things to off as a safer default. */
13235 list_for_each_entry(connector,
13236 &dev->mode_config.connector_list,
13237 base.head) {
13238 if (connector->encoder != encoder)
13239 continue;
13240 connector->base.dpms = DRM_MODE_DPMS_OFF;
13241 connector->base.encoder = NULL;
13242 }
13243 }
13244 /* Enabled encoders without active connectors will be fixed in
13245 * the crtc fixup. */
13246 }
13247
13248 void i915_redisable_vga_power_on(struct drm_device *dev)
13249 {
13250 struct drm_i915_private *dev_priv = dev->dev_private;
13251 u32 vga_reg = i915_vgacntrl_reg(dev);
13252
13253 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13254 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13255 i915_disable_vga(dev);
13256 }
13257 }
13258
13259 void i915_redisable_vga(struct drm_device *dev)
13260 {
13261 struct drm_i915_private *dev_priv = dev->dev_private;
13262
13263 /* This function can be called both from intel_modeset_setup_hw_state or
13264 * at a very early point in our resume sequence, where the power well
13265 * structures are not yet restored. Since this function is at a very
13266 * paranoid "someone might have enabled VGA while we were not looking"
13267 * level, just check if the power well is enabled instead of trying to
13268 * follow the "don't touch the power well if we don't need it" policy
13269 * the rest of the driver uses. */
13270 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
13271 return;
13272
13273 i915_redisable_vga_power_on(dev);
13274 }
13275
13276 static bool primary_get_hw_state(struct intel_crtc *crtc)
13277 {
13278 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13279
13280 if (!crtc->active)
13281 return false;
13282
13283 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13284 }
13285
13286 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13287 {
13288 struct drm_i915_private *dev_priv = dev->dev_private;
13289 enum pipe pipe;
13290 struct intel_crtc *crtc;
13291 struct intel_encoder *encoder;
13292 struct intel_connector *connector;
13293 int i;
13294
13295 for_each_intel_crtc(dev, crtc) {
13296 memset(&crtc->config, 0, sizeof(crtc->config));
13297
13298 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13299
13300 crtc->active = dev_priv->display.get_pipe_config(crtc,
13301 &crtc->config);
13302
13303 crtc->base.enabled = crtc->active;
13304 crtc->primary_enabled = primary_get_hw_state(crtc);
13305
13306 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13307 crtc->base.base.id,
13308 crtc->active ? "enabled" : "disabled");
13309 }
13310
13311 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13312 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13313
13314 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
13315 pll->active = 0;
13316 for_each_intel_crtc(dev, crtc) {
13317 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
13318 pll->active++;
13319 }
13320 pll->refcount = pll->active;
13321
13322 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
13323 pll->name, pll->refcount, pll->on);
13324
13325 if (pll->refcount)
13326 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13327 }
13328
13329 for_each_intel_encoder(dev, encoder) {
13330 pipe = 0;
13331
13332 if (encoder->get_hw_state(encoder, &pipe)) {
13333 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13334 encoder->base.crtc = &crtc->base;
13335 encoder->get_config(encoder, &crtc->config);
13336 } else {
13337 encoder->base.crtc = NULL;
13338 }
13339
13340 encoder->connectors_active = false;
13341 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13342 encoder->base.base.id,
13343 encoder->base.name,
13344 encoder->base.crtc ? "enabled" : "disabled",
13345 pipe_name(pipe));
13346 }
13347
13348 list_for_each_entry(connector, &dev->mode_config.connector_list,
13349 base.head) {
13350 if (connector->get_hw_state(connector)) {
13351 connector->base.dpms = DRM_MODE_DPMS_ON;
13352 connector->encoder->connectors_active = true;
13353 connector->base.encoder = &connector->encoder->base;
13354 } else {
13355 connector->base.dpms = DRM_MODE_DPMS_OFF;
13356 connector->base.encoder = NULL;
13357 }
13358 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13359 connector->base.base.id,
13360 connector->base.name,
13361 connector->base.encoder ? "enabled" : "disabled");
13362 }
13363 }
13364
13365 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13366 * and i915 state tracking structures. */
13367 void intel_modeset_setup_hw_state(struct drm_device *dev,
13368 bool force_restore)
13369 {
13370 struct drm_i915_private *dev_priv = dev->dev_private;
13371 enum pipe pipe;
13372 struct intel_crtc *crtc;
13373 struct intel_encoder *encoder;
13374 int i;
13375
13376 intel_modeset_readout_hw_state(dev);
13377
13378 /*
13379 * Now that we have the config, copy it to each CRTC struct
13380 * Note that this could go away if we move to using crtc_config
13381 * checking everywhere.
13382 */
13383 for_each_intel_crtc(dev, crtc) {
13384 if (crtc->active && i915.fastboot) {
13385 intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
13386 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13387 crtc->base.base.id);
13388 drm_mode_debug_printmodeline(&crtc->base.mode);
13389 }
13390 }
13391
13392 /* HW state is read out, now we need to sanitize this mess. */
13393 for_each_intel_encoder(dev, encoder) {
13394 intel_sanitize_encoder(encoder);
13395 }
13396
13397 for_each_pipe(dev_priv, pipe) {
13398 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13399 intel_sanitize_crtc(crtc);
13400 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
13401 }
13402
13403 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13404 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13405
13406 if (!pll->on || pll->active)
13407 continue;
13408
13409 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13410
13411 pll->disable(dev_priv, pll);
13412 pll->on = false;
13413 }
13414
13415 if (HAS_PCH_SPLIT(dev))
13416 ilk_wm_get_hw_state(dev);
13417
13418 if (force_restore) {
13419 i915_redisable_vga(dev);
13420
13421 /*
13422 * We need to use raw interfaces for restoring state to avoid
13423 * checking (bogus) intermediate states.
13424 */
13425 for_each_pipe(dev_priv, pipe) {
13426 struct drm_crtc *crtc =
13427 dev_priv->pipe_to_crtc_mapping[pipe];
13428
13429 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13430 crtc->primary->fb);
13431 }
13432 } else {
13433 intel_modeset_update_staged_output_state(dev);
13434 }
13435
13436 intel_modeset_check_state(dev);
13437 }
13438
13439 void intel_modeset_gem_init(struct drm_device *dev)
13440 {
13441 struct drm_crtc *c;
13442 struct drm_i915_gem_object *obj;
13443
13444 mutex_lock(&dev->struct_mutex);
13445 intel_init_gt_powersave(dev);
13446 mutex_unlock(&dev->struct_mutex);
13447
13448 intel_modeset_init_hw(dev);
13449
13450 intel_setup_overlay(dev);
13451
13452 /*
13453 * Make sure any fbs we allocated at startup are properly
13454 * pinned & fenced. When we do the allocation it's too early
13455 * for this.
13456 */
13457 mutex_lock(&dev->struct_mutex);
13458 for_each_crtc(dev, c) {
13459 obj = intel_fb_obj(c->primary->fb);
13460 if (obj == NULL)
13461 continue;
13462
13463 if (intel_pin_and_fence_fb_obj(dev, obj, NULL)) {
13464 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13465 to_intel_crtc(c)->pipe);
13466 drm_framebuffer_unreference(c->primary->fb);
13467 c->primary->fb = NULL;
13468 }
13469 }
13470 mutex_unlock(&dev->struct_mutex);
13471 }
13472
13473 void intel_connector_unregister(struct intel_connector *intel_connector)
13474 {
13475 struct drm_connector *connector = &intel_connector->base;
13476
13477 intel_panel_destroy_backlight(connector);
13478 drm_connector_unregister(connector);
13479 }
13480
13481 void intel_modeset_cleanup(struct drm_device *dev)
13482 {
13483 struct drm_i915_private *dev_priv = dev->dev_private;
13484 struct drm_connector *connector;
13485
13486 /*
13487 * Interrupts and polling as the first thing to avoid creating havoc.
13488 * Too much stuff here (turning of rps, connectors, ...) would
13489 * experience fancy races otherwise.
13490 */
13491 drm_irq_uninstall(dev);
13492 intel_hpd_cancel_work(dev_priv);
13493 dev_priv->pm._irqs_disabled = true;
13494
13495 /*
13496 * Due to the hpd irq storm handling the hotplug work can re-arm the
13497 * poll handlers. Hence disable polling after hpd handling is shut down.
13498 */
13499 drm_kms_helper_poll_fini(dev);
13500
13501 mutex_lock(&dev->struct_mutex);
13502
13503 intel_unregister_dsm_handler();
13504
13505 intel_disable_fbc(dev);
13506
13507 intel_disable_gt_powersave(dev);
13508
13509 ironlake_teardown_rc6(dev);
13510
13511 mutex_unlock(&dev->struct_mutex);
13512
13513 /* flush any delayed tasks or pending work */
13514 flush_scheduled_work();
13515
13516 /* destroy the backlight and sysfs files before encoders/connectors */
13517 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13518 struct intel_connector *intel_connector;
13519
13520 intel_connector = to_intel_connector(connector);
13521 intel_connector->unregister(intel_connector);
13522 }
13523
13524 drm_mode_config_cleanup(dev);
13525
13526 intel_cleanup_overlay(dev);
13527
13528 mutex_lock(&dev->struct_mutex);
13529 intel_cleanup_gt_powersave(dev);
13530 mutex_unlock(&dev->struct_mutex);
13531 }
13532
13533 /*
13534 * Return which encoder is currently attached for connector.
13535 */
13536 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13537 {
13538 return &intel_attached_encoder(connector)->base;
13539 }
13540
13541 void intel_connector_attach_encoder(struct intel_connector *connector,
13542 struct intel_encoder *encoder)
13543 {
13544 connector->encoder = encoder;
13545 drm_mode_connector_attach_encoder(&connector->base,
13546 &encoder->base);
13547 }
13548
13549 /*
13550 * set vga decode state - true == enable VGA decode
13551 */
13552 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13553 {
13554 struct drm_i915_private *dev_priv = dev->dev_private;
13555 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13556 u16 gmch_ctrl;
13557
13558 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13559 DRM_ERROR("failed to read control word\n");
13560 return -EIO;
13561 }
13562
13563 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13564 return 0;
13565
13566 if (state)
13567 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13568 else
13569 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13570
13571 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13572 DRM_ERROR("failed to write control word\n");
13573 return -EIO;
13574 }
13575
13576 return 0;
13577 }
13578
13579 struct intel_display_error_state {
13580
13581 u32 power_well_driver;
13582
13583 int num_transcoders;
13584
13585 struct intel_cursor_error_state {
13586 u32 control;
13587 u32 position;
13588 u32 base;
13589 u32 size;
13590 } cursor[I915_MAX_PIPES];
13591
13592 struct intel_pipe_error_state {
13593 bool power_domain_on;
13594 u32 source;
13595 u32 stat;
13596 } pipe[I915_MAX_PIPES];
13597
13598 struct intel_plane_error_state {
13599 u32 control;
13600 u32 stride;
13601 u32 size;
13602 u32 pos;
13603 u32 addr;
13604 u32 surface;
13605 u32 tile_offset;
13606 } plane[I915_MAX_PIPES];
13607
13608 struct intel_transcoder_error_state {
13609 bool power_domain_on;
13610 enum transcoder cpu_transcoder;
13611
13612 u32 conf;
13613
13614 u32 htotal;
13615 u32 hblank;
13616 u32 hsync;
13617 u32 vtotal;
13618 u32 vblank;
13619 u32 vsync;
13620 } transcoder[4];
13621 };
13622
13623 struct intel_display_error_state *
13624 intel_display_capture_error_state(struct drm_device *dev)
13625 {
13626 struct drm_i915_private *dev_priv = dev->dev_private;
13627 struct intel_display_error_state *error;
13628 int transcoders[] = {
13629 TRANSCODER_A,
13630 TRANSCODER_B,
13631 TRANSCODER_C,
13632 TRANSCODER_EDP,
13633 };
13634 int i;
13635
13636 if (INTEL_INFO(dev)->num_pipes == 0)
13637 return NULL;
13638
13639 error = kzalloc(sizeof(*error), GFP_ATOMIC);
13640 if (error == NULL)
13641 return NULL;
13642
13643 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13644 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13645
13646 for_each_pipe(dev_priv, i) {
13647 error->pipe[i].power_domain_on =
13648 intel_display_power_enabled_unlocked(dev_priv,
13649 POWER_DOMAIN_PIPE(i));
13650 if (!error->pipe[i].power_domain_on)
13651 continue;
13652
13653 error->cursor[i].control = I915_READ(CURCNTR(i));
13654 error->cursor[i].position = I915_READ(CURPOS(i));
13655 error->cursor[i].base = I915_READ(CURBASE(i));
13656
13657 error->plane[i].control = I915_READ(DSPCNTR(i));
13658 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13659 if (INTEL_INFO(dev)->gen <= 3) {
13660 error->plane[i].size = I915_READ(DSPSIZE(i));
13661 error->plane[i].pos = I915_READ(DSPPOS(i));
13662 }
13663 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13664 error->plane[i].addr = I915_READ(DSPADDR(i));
13665 if (INTEL_INFO(dev)->gen >= 4) {
13666 error->plane[i].surface = I915_READ(DSPSURF(i));
13667 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13668 }
13669
13670 error->pipe[i].source = I915_READ(PIPESRC(i));
13671
13672 if (HAS_GMCH_DISPLAY(dev))
13673 error->pipe[i].stat = I915_READ(PIPESTAT(i));
13674 }
13675
13676 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13677 if (HAS_DDI(dev_priv->dev))
13678 error->num_transcoders++; /* Account for eDP. */
13679
13680 for (i = 0; i < error->num_transcoders; i++) {
13681 enum transcoder cpu_transcoder = transcoders[i];
13682
13683 error->transcoder[i].power_domain_on =
13684 intel_display_power_enabled_unlocked(dev_priv,
13685 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13686 if (!error->transcoder[i].power_domain_on)
13687 continue;
13688
13689 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13690
13691 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13692 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13693 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13694 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13695 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13696 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13697 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13698 }
13699
13700 return error;
13701 }
13702
13703 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13704
13705 void
13706 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13707 struct drm_device *dev,
13708 struct intel_display_error_state *error)
13709 {
13710 struct drm_i915_private *dev_priv = dev->dev_private;
13711 int i;
13712
13713 if (!error)
13714 return;
13715
13716 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13717 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13718 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13719 error->power_well_driver);
13720 for_each_pipe(dev_priv, i) {
13721 err_printf(m, "Pipe [%d]:\n", i);
13722 err_printf(m, " Power: %s\n",
13723 error->pipe[i].power_domain_on ? "on" : "off");
13724 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
13725 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
13726
13727 err_printf(m, "Plane [%d]:\n", i);
13728 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
13729 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
13730 if (INTEL_INFO(dev)->gen <= 3) {
13731 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
13732 err_printf(m, " POS: %08x\n", error->plane[i].pos);
13733 }
13734 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13735 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
13736 if (INTEL_INFO(dev)->gen >= 4) {
13737 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
13738 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
13739 }
13740
13741 err_printf(m, "Cursor [%d]:\n", i);
13742 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
13743 err_printf(m, " POS: %08x\n", error->cursor[i].position);
13744 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
13745 }
13746
13747 for (i = 0; i < error->num_transcoders; i++) {
13748 err_printf(m, "CPU transcoder: %c\n",
13749 transcoder_name(error->transcoder[i].cpu_transcoder));
13750 err_printf(m, " Power: %s\n",
13751 error->transcoder[i].power_domain_on ? "on" : "off");
13752 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
13753 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
13754 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
13755 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
13756 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
13757 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
13758 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
13759 }
13760 }
13761
13762 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
13763 {
13764 struct intel_crtc *crtc;
13765
13766 for_each_intel_crtc(dev, crtc) {
13767 struct intel_unpin_work *work;
13768
13769 spin_lock_irq(&dev->event_lock);
13770
13771 work = crtc->unpin_work;
13772
13773 if (work && work->event &&
13774 work->event->base.file_priv == file) {
13775 kfree(work->event);
13776 work->event = NULL;
13777 }
13778
13779 spin_unlock_irq(&dev->event_lock);
13780 }
13781 }
Linux kernel - Deliverables
This page took 0.588327 seconds and 6 git commands to generate.