2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_rect.h>
44 #include <linux/dma_remapping.h>
46 /* Primary plane formats supported by all gen */
47 #define COMMON_PRIMARY_FORMATS \
50 DRM_FORMAT_XRGB8888, \
53 /* Primary plane formats for gen <= 3 */
54 static const uint32_t intel_primary_formats_gen2
[] = {
55 COMMON_PRIMARY_FORMATS
,
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t intel_primary_formats_gen4
[] = {
62 COMMON_PRIMARY_FORMATS
, \
65 DRM_FORMAT_XRGB2101010
,
66 DRM_FORMAT_ARGB2101010
,
67 DRM_FORMAT_XBGR2101010
,
68 DRM_FORMAT_ABGR2101010
,
72 static const uint32_t intel_cursor_formats
[] = {
76 #define DIV_ROUND_CLOSEST_ULL(ll, d) \
77 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
79 static void intel_increase_pllclock(struct drm_device
*dev
,
81 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
83 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
84 struct intel_crtc_config
*pipe_config
);
85 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
86 struct intel_crtc_config
*pipe_config
);
88 static int intel_set_mode(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
,
89 int x
, int y
, struct drm_framebuffer
*old_fb
);
90 static int intel_framebuffer_init(struct drm_device
*dev
,
91 struct intel_framebuffer
*ifb
,
92 struct drm_mode_fb_cmd2
*mode_cmd
,
93 struct drm_i915_gem_object
*obj
);
94 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
);
95 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
);
96 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
97 struct intel_link_m_n
*m_n
,
98 struct intel_link_m_n
*m2_n2
);
99 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
);
100 static void haswell_set_pipeconf(struct drm_crtc
*crtc
);
101 static void intel_set_pipe_csc(struct drm_crtc
*crtc
);
102 static void vlv_prepare_pll(struct intel_crtc
*crtc
);
103 static void chv_prepare_pll(struct intel_crtc
*crtc
);
105 static struct intel_encoder
*intel_find_encoder(struct intel_connector
*connector
, int pipe
)
107 if (!connector
->mst_port
)
108 return connector
->encoder
;
110 return &connector
->mst_port
->mst_encoders
[pipe
]->base
;
119 int p2_slow
, p2_fast
;
122 typedef struct intel_limit intel_limit_t
;
124 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
129 intel_pch_rawclk(struct drm_device
*dev
)
131 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
133 WARN_ON(!HAS_PCH_SPLIT(dev
));
135 return I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
;
138 static inline u32
/* units of 100MHz */
139 intel_fdi_link_freq(struct drm_device
*dev
)
142 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
143 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
148 static const intel_limit_t intel_limits_i8xx_dac
= {
149 .dot
= { .min
= 25000, .max
= 350000 },
150 .vco
= { .min
= 908000, .max
= 1512000 },
151 .n
= { .min
= 2, .max
= 16 },
152 .m
= { .min
= 96, .max
= 140 },
153 .m1
= { .min
= 18, .max
= 26 },
154 .m2
= { .min
= 6, .max
= 16 },
155 .p
= { .min
= 4, .max
= 128 },
156 .p1
= { .min
= 2, .max
= 33 },
157 .p2
= { .dot_limit
= 165000,
158 .p2_slow
= 4, .p2_fast
= 2 },
161 static const intel_limit_t intel_limits_i8xx_dvo
= {
162 .dot
= { .min
= 25000, .max
= 350000 },
163 .vco
= { .min
= 908000, .max
= 1512000 },
164 .n
= { .min
= 2, .max
= 16 },
165 .m
= { .min
= 96, .max
= 140 },
166 .m1
= { .min
= 18, .max
= 26 },
167 .m2
= { .min
= 6, .max
= 16 },
168 .p
= { .min
= 4, .max
= 128 },
169 .p1
= { .min
= 2, .max
= 33 },
170 .p2
= { .dot_limit
= 165000,
171 .p2_slow
= 4, .p2_fast
= 4 },
174 static const intel_limit_t intel_limits_i8xx_lvds
= {
175 .dot
= { .min
= 25000, .max
= 350000 },
176 .vco
= { .min
= 908000, .max
= 1512000 },
177 .n
= { .min
= 2, .max
= 16 },
178 .m
= { .min
= 96, .max
= 140 },
179 .m1
= { .min
= 18, .max
= 26 },
180 .m2
= { .min
= 6, .max
= 16 },
181 .p
= { .min
= 4, .max
= 128 },
182 .p1
= { .min
= 1, .max
= 6 },
183 .p2
= { .dot_limit
= 165000,
184 .p2_slow
= 14, .p2_fast
= 7 },
187 static const intel_limit_t intel_limits_i9xx_sdvo
= {
188 .dot
= { .min
= 20000, .max
= 400000 },
189 .vco
= { .min
= 1400000, .max
= 2800000 },
190 .n
= { .min
= 1, .max
= 6 },
191 .m
= { .min
= 70, .max
= 120 },
192 .m1
= { .min
= 8, .max
= 18 },
193 .m2
= { .min
= 3, .max
= 7 },
194 .p
= { .min
= 5, .max
= 80 },
195 .p1
= { .min
= 1, .max
= 8 },
196 .p2
= { .dot_limit
= 200000,
197 .p2_slow
= 10, .p2_fast
= 5 },
200 static const intel_limit_t intel_limits_i9xx_lvds
= {
201 .dot
= { .min
= 20000, .max
= 400000 },
202 .vco
= { .min
= 1400000, .max
= 2800000 },
203 .n
= { .min
= 1, .max
= 6 },
204 .m
= { .min
= 70, .max
= 120 },
205 .m1
= { .min
= 8, .max
= 18 },
206 .m2
= { .min
= 3, .max
= 7 },
207 .p
= { .min
= 7, .max
= 98 },
208 .p1
= { .min
= 1, .max
= 8 },
209 .p2
= { .dot_limit
= 112000,
210 .p2_slow
= 14, .p2_fast
= 7 },
214 static const intel_limit_t intel_limits_g4x_sdvo
= {
215 .dot
= { .min
= 25000, .max
= 270000 },
216 .vco
= { .min
= 1750000, .max
= 3500000},
217 .n
= { .min
= 1, .max
= 4 },
218 .m
= { .min
= 104, .max
= 138 },
219 .m1
= { .min
= 17, .max
= 23 },
220 .m2
= { .min
= 5, .max
= 11 },
221 .p
= { .min
= 10, .max
= 30 },
222 .p1
= { .min
= 1, .max
= 3},
223 .p2
= { .dot_limit
= 270000,
229 static const intel_limit_t intel_limits_g4x_hdmi
= {
230 .dot
= { .min
= 22000, .max
= 400000 },
231 .vco
= { .min
= 1750000, .max
= 3500000},
232 .n
= { .min
= 1, .max
= 4 },
233 .m
= { .min
= 104, .max
= 138 },
234 .m1
= { .min
= 16, .max
= 23 },
235 .m2
= { .min
= 5, .max
= 11 },
236 .p
= { .min
= 5, .max
= 80 },
237 .p1
= { .min
= 1, .max
= 8},
238 .p2
= { .dot_limit
= 165000,
239 .p2_slow
= 10, .p2_fast
= 5 },
242 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
243 .dot
= { .min
= 20000, .max
= 115000 },
244 .vco
= { .min
= 1750000, .max
= 3500000 },
245 .n
= { .min
= 1, .max
= 3 },
246 .m
= { .min
= 104, .max
= 138 },
247 .m1
= { .min
= 17, .max
= 23 },
248 .m2
= { .min
= 5, .max
= 11 },
249 .p
= { .min
= 28, .max
= 112 },
250 .p1
= { .min
= 2, .max
= 8 },
251 .p2
= { .dot_limit
= 0,
252 .p2_slow
= 14, .p2_fast
= 14
256 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
257 .dot
= { .min
= 80000, .max
= 224000 },
258 .vco
= { .min
= 1750000, .max
= 3500000 },
259 .n
= { .min
= 1, .max
= 3 },
260 .m
= { .min
= 104, .max
= 138 },
261 .m1
= { .min
= 17, .max
= 23 },
262 .m2
= { .min
= 5, .max
= 11 },
263 .p
= { .min
= 14, .max
= 42 },
264 .p1
= { .min
= 2, .max
= 6 },
265 .p2
= { .dot_limit
= 0,
266 .p2_slow
= 7, .p2_fast
= 7
270 static const intel_limit_t intel_limits_pineview_sdvo
= {
271 .dot
= { .min
= 20000, .max
= 400000},
272 .vco
= { .min
= 1700000, .max
= 3500000 },
273 /* Pineview's Ncounter is a ring counter */
274 .n
= { .min
= 3, .max
= 6 },
275 .m
= { .min
= 2, .max
= 256 },
276 /* Pineview only has one combined m divider, which we treat as m2. */
277 .m1
= { .min
= 0, .max
= 0 },
278 .m2
= { .min
= 0, .max
= 254 },
279 .p
= { .min
= 5, .max
= 80 },
280 .p1
= { .min
= 1, .max
= 8 },
281 .p2
= { .dot_limit
= 200000,
282 .p2_slow
= 10, .p2_fast
= 5 },
285 static const intel_limit_t intel_limits_pineview_lvds
= {
286 .dot
= { .min
= 20000, .max
= 400000 },
287 .vco
= { .min
= 1700000, .max
= 3500000 },
288 .n
= { .min
= 3, .max
= 6 },
289 .m
= { .min
= 2, .max
= 256 },
290 .m1
= { .min
= 0, .max
= 0 },
291 .m2
= { .min
= 0, .max
= 254 },
292 .p
= { .min
= 7, .max
= 112 },
293 .p1
= { .min
= 1, .max
= 8 },
294 .p2
= { .dot_limit
= 112000,
295 .p2_slow
= 14, .p2_fast
= 14 },
298 /* Ironlake / Sandybridge
300 * We calculate clock using (register_value + 2) for N/M1/M2, so here
301 * the range value for them is (actual_value - 2).
303 static const intel_limit_t intel_limits_ironlake_dac
= {
304 .dot
= { .min
= 25000, .max
= 350000 },
305 .vco
= { .min
= 1760000, .max
= 3510000 },
306 .n
= { .min
= 1, .max
= 5 },
307 .m
= { .min
= 79, .max
= 127 },
308 .m1
= { .min
= 12, .max
= 22 },
309 .m2
= { .min
= 5, .max
= 9 },
310 .p
= { .min
= 5, .max
= 80 },
311 .p1
= { .min
= 1, .max
= 8 },
312 .p2
= { .dot_limit
= 225000,
313 .p2_slow
= 10, .p2_fast
= 5 },
316 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
317 .dot
= { .min
= 25000, .max
= 350000 },
318 .vco
= { .min
= 1760000, .max
= 3510000 },
319 .n
= { .min
= 1, .max
= 3 },
320 .m
= { .min
= 79, .max
= 118 },
321 .m1
= { .min
= 12, .max
= 22 },
322 .m2
= { .min
= 5, .max
= 9 },
323 .p
= { .min
= 28, .max
= 112 },
324 .p1
= { .min
= 2, .max
= 8 },
325 .p2
= { .dot_limit
= 225000,
326 .p2_slow
= 14, .p2_fast
= 14 },
329 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
330 .dot
= { .min
= 25000, .max
= 350000 },
331 .vco
= { .min
= 1760000, .max
= 3510000 },
332 .n
= { .min
= 1, .max
= 3 },
333 .m
= { .min
= 79, .max
= 127 },
334 .m1
= { .min
= 12, .max
= 22 },
335 .m2
= { .min
= 5, .max
= 9 },
336 .p
= { .min
= 14, .max
= 56 },
337 .p1
= { .min
= 2, .max
= 8 },
338 .p2
= { .dot_limit
= 225000,
339 .p2_slow
= 7, .p2_fast
= 7 },
342 /* LVDS 100mhz refclk limits. */
343 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
344 .dot
= { .min
= 25000, .max
= 350000 },
345 .vco
= { .min
= 1760000, .max
= 3510000 },
346 .n
= { .min
= 1, .max
= 2 },
347 .m
= { .min
= 79, .max
= 126 },
348 .m1
= { .min
= 12, .max
= 22 },
349 .m2
= { .min
= 5, .max
= 9 },
350 .p
= { .min
= 28, .max
= 112 },
351 .p1
= { .min
= 2, .max
= 8 },
352 .p2
= { .dot_limit
= 225000,
353 .p2_slow
= 14, .p2_fast
= 14 },
356 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
357 .dot
= { .min
= 25000, .max
= 350000 },
358 .vco
= { .min
= 1760000, .max
= 3510000 },
359 .n
= { .min
= 1, .max
= 3 },
360 .m
= { .min
= 79, .max
= 126 },
361 .m1
= { .min
= 12, .max
= 22 },
362 .m2
= { .min
= 5, .max
= 9 },
363 .p
= { .min
= 14, .max
= 42 },
364 .p1
= { .min
= 2, .max
= 6 },
365 .p2
= { .dot_limit
= 225000,
366 .p2_slow
= 7, .p2_fast
= 7 },
369 static const intel_limit_t intel_limits_vlv
= {
371 * These are the data rate limits (measured in fast clocks)
372 * since those are the strictest limits we have. The fast
373 * clock and actual rate limits are more relaxed, so checking
374 * them would make no difference.
376 .dot
= { .min
= 25000 * 5, .max
= 270000 * 5 },
377 .vco
= { .min
= 4000000, .max
= 6000000 },
378 .n
= { .min
= 1, .max
= 7 },
379 .m1
= { .min
= 2, .max
= 3 },
380 .m2
= { .min
= 11, .max
= 156 },
381 .p1
= { .min
= 2, .max
= 3 },
382 .p2
= { .p2_slow
= 2, .p2_fast
= 20 }, /* slow=min, fast=max */
385 static const intel_limit_t intel_limits_chv
= {
387 * These are the data rate limits (measured in fast clocks)
388 * since those are the strictest limits we have. The fast
389 * clock and actual rate limits are more relaxed, so checking
390 * them would make no difference.
392 .dot
= { .min
= 25000 * 5, .max
= 540000 * 5},
393 .vco
= { .min
= 4860000, .max
= 6700000 },
394 .n
= { .min
= 1, .max
= 1 },
395 .m1
= { .min
= 2, .max
= 2 },
396 .m2
= { .min
= 24 << 22, .max
= 175 << 22 },
397 .p1
= { .min
= 2, .max
= 4 },
398 .p2
= { .p2_slow
= 1, .p2_fast
= 14 },
401 static void vlv_clock(int refclk
, intel_clock_t
*clock
)
403 clock
->m
= clock
->m1
* clock
->m2
;
404 clock
->p
= clock
->p1
* clock
->p2
;
405 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
407 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
408 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
412 * Returns whether any output on the specified pipe is of the specified type
414 static bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
)
416 struct drm_device
*dev
= crtc
->dev
;
417 struct intel_encoder
*encoder
;
419 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
420 if (encoder
->type
== type
)
426 static const intel_limit_t
*intel_ironlake_limit(struct drm_crtc
*crtc
,
429 struct drm_device
*dev
= crtc
->dev
;
430 const intel_limit_t
*limit
;
432 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
433 if (intel_is_dual_link_lvds(dev
)) {
434 if (refclk
== 100000)
435 limit
= &intel_limits_ironlake_dual_lvds_100m
;
437 limit
= &intel_limits_ironlake_dual_lvds
;
439 if (refclk
== 100000)
440 limit
= &intel_limits_ironlake_single_lvds_100m
;
442 limit
= &intel_limits_ironlake_single_lvds
;
445 limit
= &intel_limits_ironlake_dac
;
450 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
452 struct drm_device
*dev
= crtc
->dev
;
453 const intel_limit_t
*limit
;
455 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
456 if (intel_is_dual_link_lvds(dev
))
457 limit
= &intel_limits_g4x_dual_channel_lvds
;
459 limit
= &intel_limits_g4x_single_channel_lvds
;
460 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
461 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
462 limit
= &intel_limits_g4x_hdmi
;
463 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
464 limit
= &intel_limits_g4x_sdvo
;
465 } else /* The option is for other outputs */
466 limit
= &intel_limits_i9xx_sdvo
;
471 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
, int refclk
)
473 struct drm_device
*dev
= crtc
->dev
;
474 const intel_limit_t
*limit
;
476 if (HAS_PCH_SPLIT(dev
))
477 limit
= intel_ironlake_limit(crtc
, refclk
);
478 else if (IS_G4X(dev
)) {
479 limit
= intel_g4x_limit(crtc
);
480 } else if (IS_PINEVIEW(dev
)) {
481 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
482 limit
= &intel_limits_pineview_lvds
;
484 limit
= &intel_limits_pineview_sdvo
;
485 } else if (IS_CHERRYVIEW(dev
)) {
486 limit
= &intel_limits_chv
;
487 } else if (IS_VALLEYVIEW(dev
)) {
488 limit
= &intel_limits_vlv
;
489 } else if (!IS_GEN2(dev
)) {
490 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
491 limit
= &intel_limits_i9xx_lvds
;
493 limit
= &intel_limits_i9xx_sdvo
;
495 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
496 limit
= &intel_limits_i8xx_lvds
;
497 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
))
498 limit
= &intel_limits_i8xx_dvo
;
500 limit
= &intel_limits_i8xx_dac
;
505 /* m1 is reserved as 0 in Pineview, n is a ring counter */
506 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
508 clock
->m
= clock
->m2
+ 2;
509 clock
->p
= clock
->p1
* clock
->p2
;
510 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
512 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
513 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
516 static uint32_t i9xx_dpll_compute_m(struct dpll
*dpll
)
518 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
521 static void i9xx_clock(int refclk
, intel_clock_t
*clock
)
523 clock
->m
= i9xx_dpll_compute_m(clock
);
524 clock
->p
= clock
->p1
* clock
->p2
;
525 if (WARN_ON(clock
->n
+ 2 == 0 || clock
->p
== 0))
527 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
+ 2);
528 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
531 static void chv_clock(int refclk
, intel_clock_t
*clock
)
533 clock
->m
= clock
->m1
* clock
->m2
;
534 clock
->p
= clock
->p1
* clock
->p2
;
535 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
537 clock
->vco
= DIV_ROUND_CLOSEST_ULL((uint64_t)refclk
* clock
->m
,
539 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
542 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
544 * Returns whether the given set of divisors are valid for a given refclk with
545 * the given connectors.
548 static bool intel_PLL_is_valid(struct drm_device
*dev
,
549 const intel_limit_t
*limit
,
550 const intel_clock_t
*clock
)
552 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
553 INTELPllInvalid("n out of range\n");
554 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
555 INTELPllInvalid("p1 out of range\n");
556 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
557 INTELPllInvalid("m2 out of range\n");
558 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
559 INTELPllInvalid("m1 out of range\n");
561 if (!IS_PINEVIEW(dev
) && !IS_VALLEYVIEW(dev
))
562 if (clock
->m1
<= clock
->m2
)
563 INTELPllInvalid("m1 <= m2\n");
565 if (!IS_VALLEYVIEW(dev
)) {
566 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
567 INTELPllInvalid("p out of range\n");
568 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
569 INTELPllInvalid("m out of range\n");
572 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
573 INTELPllInvalid("vco out of range\n");
574 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
575 * connector, etc., rather than just a single range.
577 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
578 INTELPllInvalid("dot out of range\n");
584 i9xx_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
585 int target
, int refclk
, intel_clock_t
*match_clock
,
586 intel_clock_t
*best_clock
)
588 struct drm_device
*dev
= crtc
->dev
;
592 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
594 * For LVDS just rely on its current settings for dual-channel.
595 * We haven't figured out how to reliably set up different
596 * single/dual channel state, if we even can.
598 if (intel_is_dual_link_lvds(dev
))
599 clock
.p2
= limit
->p2
.p2_fast
;
601 clock
.p2
= limit
->p2
.p2_slow
;
603 if (target
< limit
->p2
.dot_limit
)
604 clock
.p2
= limit
->p2
.p2_slow
;
606 clock
.p2
= limit
->p2
.p2_fast
;
609 memset(best_clock
, 0, sizeof(*best_clock
));
611 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
613 for (clock
.m2
= limit
->m2
.min
;
614 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
615 if (clock
.m2
>= clock
.m1
)
617 for (clock
.n
= limit
->n
.min
;
618 clock
.n
<= limit
->n
.max
; clock
.n
++) {
619 for (clock
.p1
= limit
->p1
.min
;
620 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
623 i9xx_clock(refclk
, &clock
);
624 if (!intel_PLL_is_valid(dev
, limit
,
628 clock
.p
!= match_clock
->p
)
631 this_err
= abs(clock
.dot
- target
);
632 if (this_err
< err
) {
641 return (err
!= target
);
645 pnv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
646 int target
, int refclk
, intel_clock_t
*match_clock
,
647 intel_clock_t
*best_clock
)
649 struct drm_device
*dev
= crtc
->dev
;
653 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
655 * For LVDS just rely on its current settings for dual-channel.
656 * We haven't figured out how to reliably set up different
657 * single/dual channel state, if we even can.
659 if (intel_is_dual_link_lvds(dev
))
660 clock
.p2
= limit
->p2
.p2_fast
;
662 clock
.p2
= limit
->p2
.p2_slow
;
664 if (target
< limit
->p2
.dot_limit
)
665 clock
.p2
= limit
->p2
.p2_slow
;
667 clock
.p2
= limit
->p2
.p2_fast
;
670 memset(best_clock
, 0, sizeof(*best_clock
));
672 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
674 for (clock
.m2
= limit
->m2
.min
;
675 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
676 for (clock
.n
= limit
->n
.min
;
677 clock
.n
<= limit
->n
.max
; clock
.n
++) {
678 for (clock
.p1
= limit
->p1
.min
;
679 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
682 pineview_clock(refclk
, &clock
);
683 if (!intel_PLL_is_valid(dev
, limit
,
687 clock
.p
!= match_clock
->p
)
690 this_err
= abs(clock
.dot
- target
);
691 if (this_err
< err
) {
700 return (err
!= target
);
704 g4x_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
705 int target
, int refclk
, intel_clock_t
*match_clock
,
706 intel_clock_t
*best_clock
)
708 struct drm_device
*dev
= crtc
->dev
;
712 /* approximately equals target * 0.00585 */
713 int err_most
= (target
>> 8) + (target
>> 9);
716 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
717 if (intel_is_dual_link_lvds(dev
))
718 clock
.p2
= limit
->p2
.p2_fast
;
720 clock
.p2
= limit
->p2
.p2_slow
;
722 if (target
< limit
->p2
.dot_limit
)
723 clock
.p2
= limit
->p2
.p2_slow
;
725 clock
.p2
= limit
->p2
.p2_fast
;
728 memset(best_clock
, 0, sizeof(*best_clock
));
729 max_n
= limit
->n
.max
;
730 /* based on hardware requirement, prefer smaller n to precision */
731 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
732 /* based on hardware requirement, prefere larger m1,m2 */
733 for (clock
.m1
= limit
->m1
.max
;
734 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
735 for (clock
.m2
= limit
->m2
.max
;
736 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
737 for (clock
.p1
= limit
->p1
.max
;
738 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
741 i9xx_clock(refclk
, &clock
);
742 if (!intel_PLL_is_valid(dev
, limit
,
746 this_err
= abs(clock
.dot
- target
);
747 if (this_err
< err_most
) {
761 vlv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
762 int target
, int refclk
, intel_clock_t
*match_clock
,
763 intel_clock_t
*best_clock
)
765 struct drm_device
*dev
= crtc
->dev
;
767 unsigned int bestppm
= 1000000;
768 /* min update 19.2 MHz */
769 int max_n
= min(limit
->n
.max
, refclk
/ 19200);
772 target
*= 5; /* fast clock */
774 memset(best_clock
, 0, sizeof(*best_clock
));
776 /* based on hardware requirement, prefer smaller n to precision */
777 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
778 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
779 for (clock
.p2
= limit
->p2
.p2_fast
; clock
.p2
>= limit
->p2
.p2_slow
;
780 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
781 clock
.p
= clock
.p1
* clock
.p2
;
782 /* based on hardware requirement, prefer bigger m1,m2 values */
783 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
; clock
.m1
++) {
784 unsigned int ppm
, diff
;
786 clock
.m2
= DIV_ROUND_CLOSEST(target
* clock
.p
* clock
.n
,
789 vlv_clock(refclk
, &clock
);
791 if (!intel_PLL_is_valid(dev
, limit
,
795 diff
= abs(clock
.dot
- target
);
796 ppm
= div_u64(1000000ULL * diff
, target
);
798 if (ppm
< 100 && clock
.p
> best_clock
->p
) {
804 if (bestppm
>= 10 && ppm
< bestppm
- 10) {
818 chv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
819 int target
, int refclk
, intel_clock_t
*match_clock
,
820 intel_clock_t
*best_clock
)
822 struct drm_device
*dev
= crtc
->dev
;
827 memset(best_clock
, 0, sizeof(*best_clock
));
830 * Based on hardware doc, the n always set to 1, and m1 always
831 * set to 2. If requires to support 200Mhz refclk, we need to
832 * revisit this because n may not 1 anymore.
834 clock
.n
= 1, clock
.m1
= 2;
835 target
*= 5; /* fast clock */
837 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
838 for (clock
.p2
= limit
->p2
.p2_fast
;
839 clock
.p2
>= limit
->p2
.p2_slow
;
840 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
842 clock
.p
= clock
.p1
* clock
.p2
;
844 m2
= DIV_ROUND_CLOSEST_ULL(((uint64_t)target
* clock
.p
*
845 clock
.n
) << 22, refclk
* clock
.m1
);
847 if (m2
> INT_MAX
/clock
.m1
)
852 chv_clock(refclk
, &clock
);
854 if (!intel_PLL_is_valid(dev
, limit
, &clock
))
857 /* based on hardware requirement, prefer bigger p
859 if (clock
.p
> best_clock
->p
) {
869 bool intel_crtc_active(struct drm_crtc
*crtc
)
871 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
873 /* Be paranoid as we can arrive here with only partial
874 * state retrieved from the hardware during setup.
876 * We can ditch the adjusted_mode.crtc_clock check as soon
877 * as Haswell has gained clock readout/fastboot support.
879 * We can ditch the crtc->primary->fb check as soon as we can
880 * properly reconstruct framebuffers.
882 return intel_crtc
->active
&& crtc
->primary
->fb
&&
883 intel_crtc
->config
.adjusted_mode
.crtc_clock
;
886 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
889 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
890 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
892 return intel_crtc
->config
.cpu_transcoder
;
895 static void g4x_wait_for_vblank(struct drm_device
*dev
, int pipe
)
897 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
898 u32 frame
, frame_reg
= PIPE_FRMCOUNT_GM45(pipe
);
900 frame
= I915_READ(frame_reg
);
902 if (wait_for(I915_READ_NOTRACE(frame_reg
) != frame
, 50))
903 WARN(1, "vblank wait on pipe %c timed out\n",
908 * intel_wait_for_vblank - wait for vblank on a given pipe
910 * @pipe: pipe to wait for
912 * Wait for vblank to occur on a given pipe. Needed for various bits of
915 void intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
917 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
918 int pipestat_reg
= PIPESTAT(pipe
);
920 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
921 g4x_wait_for_vblank(dev
, pipe
);
925 /* Clear existing vblank status. Note this will clear any other
926 * sticky status fields as well.
928 * This races with i915_driver_irq_handler() with the result
929 * that either function could miss a vblank event. Here it is not
930 * fatal, as we will either wait upon the next vblank interrupt or
931 * timeout. Generally speaking intel_wait_for_vblank() is only
932 * called during modeset at which time the GPU should be idle and
933 * should *not* be performing page flips and thus not waiting on
935 * Currently, the result of us stealing a vblank from the irq
936 * handler is that a single frame will be skipped during swapbuffers.
938 I915_WRITE(pipestat_reg
,
939 I915_READ(pipestat_reg
) | PIPE_VBLANK_INTERRUPT_STATUS
);
941 /* Wait for vblank interrupt bit to set */
942 if (wait_for(I915_READ(pipestat_reg
) &
943 PIPE_VBLANK_INTERRUPT_STATUS
,
945 DRM_DEBUG_KMS("vblank wait on pipe %c timed out\n",
949 static bool pipe_dsl_stopped(struct drm_device
*dev
, enum pipe pipe
)
951 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
952 u32 reg
= PIPEDSL(pipe
);
957 line_mask
= DSL_LINEMASK_GEN2
;
959 line_mask
= DSL_LINEMASK_GEN3
;
961 line1
= I915_READ(reg
) & line_mask
;
963 line2
= I915_READ(reg
) & line_mask
;
965 return line1
== line2
;
969 * intel_wait_for_pipe_off - wait for pipe to turn off
970 * @crtc: crtc whose pipe to wait for
972 * After disabling a pipe, we can't wait for vblank in the usual way,
973 * spinning on the vblank interrupt status bit, since we won't actually
974 * see an interrupt when the pipe is disabled.
977 * wait for the pipe register state bit to turn off
980 * wait for the display line value to settle (it usually
981 * ends up stopping at the start of the next frame).
984 static void intel_wait_for_pipe_off(struct intel_crtc
*crtc
)
986 struct drm_device
*dev
= crtc
->base
.dev
;
987 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
988 enum transcoder cpu_transcoder
= crtc
->config
.cpu_transcoder
;
989 enum pipe pipe
= crtc
->pipe
;
991 if (INTEL_INFO(dev
)->gen
>= 4) {
992 int reg
= PIPECONF(cpu_transcoder
);
994 /* Wait for the Pipe State to go off */
995 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
997 WARN(1, "pipe_off wait timed out\n");
999 /* Wait for the display line to settle */
1000 if (wait_for(pipe_dsl_stopped(dev
, pipe
), 100))
1001 WARN(1, "pipe_off wait timed out\n");
1006 * ibx_digital_port_connected - is the specified port connected?
1007 * @dev_priv: i915 private structure
1008 * @port: the port to test
1010 * Returns true if @port is connected, false otherwise.
1012 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
1013 struct intel_digital_port
*port
)
1017 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1018 switch (port
->port
) {
1020 bit
= SDE_PORTB_HOTPLUG
;
1023 bit
= SDE_PORTC_HOTPLUG
;
1026 bit
= SDE_PORTD_HOTPLUG
;
1032 switch (port
->port
) {
1034 bit
= SDE_PORTB_HOTPLUG_CPT
;
1037 bit
= SDE_PORTC_HOTPLUG_CPT
;
1040 bit
= SDE_PORTD_HOTPLUG_CPT
;
1047 return I915_READ(SDEISR
) & bit
;
1050 static const char *state_string(bool enabled
)
1052 return enabled
? "on" : "off";
1055 /* Only for pre-ILK configs */
1056 void assert_pll(struct drm_i915_private
*dev_priv
,
1057 enum pipe pipe
, bool state
)
1064 val
= I915_READ(reg
);
1065 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1066 WARN(cur_state
!= state
,
1067 "PLL state assertion failure (expected %s, current %s)\n",
1068 state_string(state
), state_string(cur_state
));
1071 /* XXX: the dsi pll is shared between MIPI DSI ports */
1072 static void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
)
1077 mutex_lock(&dev_priv
->dpio_lock
);
1078 val
= vlv_cck_read(dev_priv
, CCK_REG_DSI_PLL_CONTROL
);
1079 mutex_unlock(&dev_priv
->dpio_lock
);
1081 cur_state
= val
& DSI_PLL_VCO_EN
;
1082 WARN(cur_state
!= state
,
1083 "DSI PLL state assertion failure (expected %s, current %s)\n",
1084 state_string(state
), state_string(cur_state
));
1086 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1087 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1089 struct intel_shared_dpll
*
1090 intel_crtc_to_shared_dpll(struct intel_crtc
*crtc
)
1092 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1094 if (crtc
->config
.shared_dpll
< 0)
1097 return &dev_priv
->shared_dplls
[crtc
->config
.shared_dpll
];
1101 void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
1102 struct intel_shared_dpll
*pll
,
1106 struct intel_dpll_hw_state hw_state
;
1109 "asserting DPLL %s with no DPLL\n", state_string(state
)))
1112 cur_state
= pll
->get_hw_state(dev_priv
, pll
, &hw_state
);
1113 WARN(cur_state
!= state
,
1114 "%s assertion failure (expected %s, current %s)\n",
1115 pll
->name
, state_string(state
), state_string(cur_state
));
1118 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1119 enum pipe pipe
, bool state
)
1124 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1127 if (HAS_DDI(dev_priv
->dev
)) {
1128 /* DDI does not have a specific FDI_TX register */
1129 reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1130 val
= I915_READ(reg
);
1131 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
1133 reg
= FDI_TX_CTL(pipe
);
1134 val
= I915_READ(reg
);
1135 cur_state
= !!(val
& FDI_TX_ENABLE
);
1137 WARN(cur_state
!= state
,
1138 "FDI TX state assertion failure (expected %s, current %s)\n",
1139 state_string(state
), state_string(cur_state
));
1141 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1142 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1144 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1145 enum pipe pipe
, bool state
)
1151 reg
= FDI_RX_CTL(pipe
);
1152 val
= I915_READ(reg
);
1153 cur_state
= !!(val
& FDI_RX_ENABLE
);
1154 WARN(cur_state
!= state
,
1155 "FDI RX state assertion failure (expected %s, current %s)\n",
1156 state_string(state
), state_string(cur_state
));
1158 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1159 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1161 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1167 /* ILK FDI PLL is always enabled */
1168 if (INTEL_INFO(dev_priv
->dev
)->gen
== 5)
1171 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1172 if (HAS_DDI(dev_priv
->dev
))
1175 reg
= FDI_TX_CTL(pipe
);
1176 val
= I915_READ(reg
);
1177 WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1180 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1181 enum pipe pipe
, bool state
)
1187 reg
= FDI_RX_CTL(pipe
);
1188 val
= I915_READ(reg
);
1189 cur_state
= !!(val
& FDI_RX_PLL_ENABLE
);
1190 WARN(cur_state
!= state
,
1191 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1192 state_string(state
), state_string(cur_state
));
1195 static void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1198 struct drm_device
*dev
= dev_priv
->dev
;
1201 enum pipe panel_pipe
= PIPE_A
;
1204 if (WARN_ON(HAS_DDI(dev
)))
1207 if (HAS_PCH_SPLIT(dev
)) {
1210 pp_reg
= PCH_PP_CONTROL
;
1211 port_sel
= I915_READ(PCH_PP_ON_DELAYS
) & PANEL_PORT_SELECT_MASK
;
1213 if (port_sel
== PANEL_PORT_SELECT_LVDS
&&
1214 I915_READ(PCH_LVDS
) & LVDS_PIPEB_SELECT
)
1215 panel_pipe
= PIPE_B
;
1216 /* XXX: else fix for eDP */
1217 } else if (IS_VALLEYVIEW(dev
)) {
1218 /* presumably write lock depends on pipe, not port select */
1219 pp_reg
= VLV_PIPE_PP_CONTROL(pipe
);
1222 pp_reg
= PP_CONTROL
;
1223 if (I915_READ(LVDS
) & LVDS_PIPEB_SELECT
)
1224 panel_pipe
= PIPE_B
;
1227 val
= I915_READ(pp_reg
);
1228 if (!(val
& PANEL_POWER_ON
) ||
1229 ((val
& PANEL_UNLOCK_MASK
) == PANEL_UNLOCK_REGS
))
1232 WARN(panel_pipe
== pipe
&& locked
,
1233 "panel assertion failure, pipe %c regs locked\n",
1237 static void assert_cursor(struct drm_i915_private
*dev_priv
,
1238 enum pipe pipe
, bool state
)
1240 struct drm_device
*dev
= dev_priv
->dev
;
1243 if (IS_845G(dev
) || IS_I865G(dev
))
1244 cur_state
= I915_READ(_CURACNTR
) & CURSOR_ENABLE
;
1246 cur_state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
1248 WARN(cur_state
!= state
,
1249 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1250 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1252 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1253 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1255 void assert_pipe(struct drm_i915_private
*dev_priv
,
1256 enum pipe pipe
, bool state
)
1261 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1264 /* if we need the pipe A quirk it must be always on */
1265 if (pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
1268 if (!intel_display_power_enabled(dev_priv
,
1269 POWER_DOMAIN_TRANSCODER(cpu_transcoder
))) {
1272 reg
= PIPECONF(cpu_transcoder
);
1273 val
= I915_READ(reg
);
1274 cur_state
= !!(val
& PIPECONF_ENABLE
);
1277 WARN(cur_state
!= state
,
1278 "pipe %c assertion failure (expected %s, current %s)\n",
1279 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1282 static void assert_plane(struct drm_i915_private
*dev_priv
,
1283 enum plane plane
, bool state
)
1289 reg
= DSPCNTR(plane
);
1290 val
= I915_READ(reg
);
1291 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1292 WARN(cur_state
!= state
,
1293 "plane %c assertion failure (expected %s, current %s)\n",
1294 plane_name(plane
), state_string(state
), state_string(cur_state
));
1297 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1298 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1300 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1303 struct drm_device
*dev
= dev_priv
->dev
;
1308 /* Primary planes are fixed to pipes on gen4+ */
1309 if (INTEL_INFO(dev
)->gen
>= 4) {
1310 reg
= DSPCNTR(pipe
);
1311 val
= I915_READ(reg
);
1312 WARN(val
& DISPLAY_PLANE_ENABLE
,
1313 "plane %c assertion failure, should be disabled but not\n",
1318 /* Need to check both planes against the pipe */
1319 for_each_pipe(dev_priv
, i
) {
1321 val
= I915_READ(reg
);
1322 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1323 DISPPLANE_SEL_PIPE_SHIFT
;
1324 WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1325 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1326 plane_name(i
), pipe_name(pipe
));
1330 static void assert_sprites_disabled(struct drm_i915_private
*dev_priv
,
1333 struct drm_device
*dev
= dev_priv
->dev
;
1337 if (IS_VALLEYVIEW(dev
)) {
1338 for_each_sprite(pipe
, sprite
) {
1339 reg
= SPCNTR(pipe
, sprite
);
1340 val
= I915_READ(reg
);
1341 WARN(val
& SP_ENABLE
,
1342 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1343 sprite_name(pipe
, sprite
), pipe_name(pipe
));
1345 } else if (INTEL_INFO(dev
)->gen
>= 7) {
1347 val
= I915_READ(reg
);
1348 WARN(val
& SPRITE_ENABLE
,
1349 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1350 plane_name(pipe
), pipe_name(pipe
));
1351 } else if (INTEL_INFO(dev
)->gen
>= 5) {
1352 reg
= DVSCNTR(pipe
);
1353 val
= I915_READ(reg
);
1354 WARN(val
& DVS_ENABLE
,
1355 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1356 plane_name(pipe
), pipe_name(pipe
));
1360 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1365 WARN_ON(!(HAS_PCH_IBX(dev_priv
->dev
) || HAS_PCH_CPT(dev_priv
->dev
)));
1367 val
= I915_READ(PCH_DREF_CONTROL
);
1368 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1369 DREF_SUPERSPREAD_SOURCE_MASK
));
1370 WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1373 static void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1380 reg
= PCH_TRANSCONF(pipe
);
1381 val
= I915_READ(reg
);
1382 enabled
= !!(val
& TRANS_ENABLE
);
1384 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1388 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1389 enum pipe pipe
, u32 port_sel
, u32 val
)
1391 if ((val
& DP_PORT_EN
) == 0)
1394 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1395 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1396 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1397 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1399 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1400 if ((val
& DP_PIPE_MASK_CHV
) != DP_PIPE_SELECT_CHV(pipe
))
1403 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1409 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1410 enum pipe pipe
, u32 val
)
1412 if ((val
& SDVO_ENABLE
) == 0)
1415 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1416 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1418 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1419 if ((val
& SDVO_PIPE_SEL_MASK_CHV
) != SDVO_PIPE_SEL_CHV(pipe
))
1422 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1428 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1429 enum pipe pipe
, u32 val
)
1431 if ((val
& LVDS_PORT_EN
) == 0)
1434 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1435 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1438 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1444 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1445 enum pipe pipe
, u32 val
)
1447 if ((val
& ADPA_DAC_ENABLE
) == 0)
1449 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1450 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1453 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1459 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1460 enum pipe pipe
, int reg
, u32 port_sel
)
1462 u32 val
= I915_READ(reg
);
1463 WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1464 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1465 reg
, pipe_name(pipe
));
1467 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& DP_PORT_EN
) == 0
1468 && (val
& DP_PIPEB_SELECT
),
1469 "IBX PCH dp port still using transcoder B\n");
1472 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1473 enum pipe pipe
, int reg
)
1475 u32 val
= I915_READ(reg
);
1476 WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1477 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1478 reg
, pipe_name(pipe
));
1480 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& SDVO_ENABLE
) == 0
1481 && (val
& SDVO_PIPE_B_SELECT
),
1482 "IBX PCH hdmi port still using transcoder B\n");
1485 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1491 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1492 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1493 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1496 val
= I915_READ(reg
);
1497 WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1498 "PCH VGA enabled on transcoder %c, should be disabled\n",
1502 val
= I915_READ(reg
);
1503 WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1504 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1507 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1508 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1509 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1512 static void intel_init_dpio(struct drm_device
*dev
)
1514 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1516 if (!IS_VALLEYVIEW(dev
))
1520 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1521 * CHV x1 PHY (DP/HDMI D)
1522 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1524 if (IS_CHERRYVIEW(dev
)) {
1525 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO_2
;
1526 DPIO_PHY_IOSF_PORT(DPIO_PHY1
) = IOSF_PORT_DPIO
;
1528 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO
;
1532 static void vlv_enable_pll(struct intel_crtc
*crtc
)
1534 struct drm_device
*dev
= crtc
->base
.dev
;
1535 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1536 int reg
= DPLL(crtc
->pipe
);
1537 u32 dpll
= crtc
->config
.dpll_hw_state
.dpll
;
1539 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1541 /* No really, not for ILK+ */
1542 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
));
1544 /* PLL is protected by panel, make sure we can write it */
1545 if (IS_MOBILE(dev_priv
->dev
))
1546 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1548 I915_WRITE(reg
, dpll
);
1552 if (wait_for(((I915_READ(reg
) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1553 DRM_ERROR("DPLL %d failed to lock\n", crtc
->pipe
);
1555 I915_WRITE(DPLL_MD(crtc
->pipe
), crtc
->config
.dpll_hw_state
.dpll_md
);
1556 POSTING_READ(DPLL_MD(crtc
->pipe
));
1558 /* We do this three times for luck */
1559 I915_WRITE(reg
, dpll
);
1561 udelay(150); /* wait for warmup */
1562 I915_WRITE(reg
, dpll
);
1564 udelay(150); /* wait for warmup */
1565 I915_WRITE(reg
, dpll
);
1567 udelay(150); /* wait for warmup */
1570 static void chv_enable_pll(struct intel_crtc
*crtc
)
1572 struct drm_device
*dev
= crtc
->base
.dev
;
1573 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1574 int pipe
= crtc
->pipe
;
1575 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1578 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1580 BUG_ON(!IS_CHERRYVIEW(dev_priv
->dev
));
1582 mutex_lock(&dev_priv
->dpio_lock
);
1584 /* Enable back the 10bit clock to display controller */
1585 tmp
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1586 tmp
|= DPIO_DCLKP_EN
;
1587 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), tmp
);
1590 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1595 I915_WRITE(DPLL(pipe
), crtc
->config
.dpll_hw_state
.dpll
);
1597 /* Check PLL is locked */
1598 if (wait_for(((I915_READ(DPLL(pipe
)) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1599 DRM_ERROR("PLL %d failed to lock\n", pipe
);
1601 /* not sure when this should be written */
1602 I915_WRITE(DPLL_MD(pipe
), crtc
->config
.dpll_hw_state
.dpll_md
);
1603 POSTING_READ(DPLL_MD(pipe
));
1605 mutex_unlock(&dev_priv
->dpio_lock
);
1608 static void i9xx_enable_pll(struct intel_crtc
*crtc
)
1610 struct drm_device
*dev
= crtc
->base
.dev
;
1611 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1612 int reg
= DPLL(crtc
->pipe
);
1613 u32 dpll
= crtc
->config
.dpll_hw_state
.dpll
;
1615 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1617 /* No really, not for ILK+ */
1618 BUG_ON(INTEL_INFO(dev
)->gen
>= 5);
1620 /* PLL is protected by panel, make sure we can write it */
1621 if (IS_MOBILE(dev
) && !IS_I830(dev
))
1622 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1624 I915_WRITE(reg
, dpll
);
1626 /* Wait for the clocks to stabilize. */
1630 if (INTEL_INFO(dev
)->gen
>= 4) {
1631 I915_WRITE(DPLL_MD(crtc
->pipe
),
1632 crtc
->config
.dpll_hw_state
.dpll_md
);
1634 /* The pixel multiplier can only be updated once the
1635 * DPLL is enabled and the clocks are stable.
1637 * So write it again.
1639 I915_WRITE(reg
, dpll
);
1642 /* We do this three times for luck */
1643 I915_WRITE(reg
, dpll
);
1645 udelay(150); /* wait for warmup */
1646 I915_WRITE(reg
, dpll
);
1648 udelay(150); /* wait for warmup */
1649 I915_WRITE(reg
, dpll
);
1651 udelay(150); /* wait for warmup */
1655 * i9xx_disable_pll - disable a PLL
1656 * @dev_priv: i915 private structure
1657 * @pipe: pipe PLL to disable
1659 * Disable the PLL for @pipe, making sure the pipe is off first.
1661 * Note! This is for pre-ILK only.
1663 static void i9xx_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1665 /* Don't disable pipe A or pipe A PLLs if needed */
1666 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1669 /* Make sure the pipe isn't still relying on us */
1670 assert_pipe_disabled(dev_priv
, pipe
);
1672 I915_WRITE(DPLL(pipe
), 0);
1673 POSTING_READ(DPLL(pipe
));
1676 static void vlv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1680 /* Make sure the pipe isn't still relying on us */
1681 assert_pipe_disabled(dev_priv
, pipe
);
1684 * Leave integrated clock source and reference clock enabled for pipe B.
1685 * The latter is needed for VGA hotplug / manual detection.
1688 val
= DPLL_INTEGRATED_CRI_CLK_VLV
| DPLL_REFA_CLK_ENABLE_VLV
;
1689 I915_WRITE(DPLL(pipe
), val
);
1690 POSTING_READ(DPLL(pipe
));
1694 static void chv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1696 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1699 /* Make sure the pipe isn't still relying on us */
1700 assert_pipe_disabled(dev_priv
, pipe
);
1702 /* Set PLL en = 0 */
1703 val
= DPLL_SSC_REF_CLOCK_CHV
| DPLL_REFA_CLK_ENABLE_VLV
;
1705 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
1706 I915_WRITE(DPLL(pipe
), val
);
1707 POSTING_READ(DPLL(pipe
));
1709 mutex_lock(&dev_priv
->dpio_lock
);
1711 /* Disable 10bit clock to display controller */
1712 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1713 val
&= ~DPIO_DCLKP_EN
;
1714 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), val
);
1716 /* disable left/right clock distribution */
1717 if (pipe
!= PIPE_B
) {
1718 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
);
1719 val
&= ~(CHV_BUFLEFTENA1_MASK
| CHV_BUFRIGHTENA1_MASK
);
1720 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
, val
);
1722 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
);
1723 val
&= ~(CHV_BUFLEFTENA2_MASK
| CHV_BUFRIGHTENA2_MASK
);
1724 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
, val
);
1727 mutex_unlock(&dev_priv
->dpio_lock
);
1730 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1731 struct intel_digital_port
*dport
)
1736 switch (dport
->port
) {
1738 port_mask
= DPLL_PORTB_READY_MASK
;
1742 port_mask
= DPLL_PORTC_READY_MASK
;
1746 port_mask
= DPLL_PORTD_READY_MASK
;
1747 dpll_reg
= DPIO_PHY_STATUS
;
1753 if (wait_for((I915_READ(dpll_reg
) & port_mask
) == 0, 1000))
1754 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1755 port_name(dport
->port
), I915_READ(dpll_reg
));
1758 static void intel_prepare_shared_dpll(struct intel_crtc
*crtc
)
1760 struct drm_device
*dev
= crtc
->base
.dev
;
1761 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1762 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1764 if (WARN_ON(pll
== NULL
))
1767 WARN_ON(!pll
->refcount
);
1768 if (pll
->active
== 0) {
1769 DRM_DEBUG_DRIVER("setting up %s\n", pll
->name
);
1771 assert_shared_dpll_disabled(dev_priv
, pll
);
1773 pll
->mode_set(dev_priv
, pll
);
1778 * intel_enable_shared_dpll - enable PCH PLL
1779 * @dev_priv: i915 private structure
1780 * @pipe: pipe PLL to enable
1782 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1783 * drives the transcoder clock.
1785 static void intel_enable_shared_dpll(struct intel_crtc
*crtc
)
1787 struct drm_device
*dev
= crtc
->base
.dev
;
1788 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1789 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1791 if (WARN_ON(pll
== NULL
))
1794 if (WARN_ON(pll
->refcount
== 0))
1797 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1798 pll
->name
, pll
->active
, pll
->on
,
1799 crtc
->base
.base
.id
);
1801 if (pll
->active
++) {
1803 assert_shared_dpll_enabled(dev_priv
, pll
);
1808 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
1810 DRM_DEBUG_KMS("enabling %s\n", pll
->name
);
1811 pll
->enable(dev_priv
, pll
);
1815 static void intel_disable_shared_dpll(struct intel_crtc
*crtc
)
1817 struct drm_device
*dev
= crtc
->base
.dev
;
1818 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1819 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1821 /* PCH only available on ILK+ */
1822 BUG_ON(INTEL_INFO(dev
)->gen
< 5);
1823 if (WARN_ON(pll
== NULL
))
1826 if (WARN_ON(pll
->refcount
== 0))
1829 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1830 pll
->name
, pll
->active
, pll
->on
,
1831 crtc
->base
.base
.id
);
1833 if (WARN_ON(pll
->active
== 0)) {
1834 assert_shared_dpll_disabled(dev_priv
, pll
);
1838 assert_shared_dpll_enabled(dev_priv
, pll
);
1843 DRM_DEBUG_KMS("disabling %s\n", pll
->name
);
1844 pll
->disable(dev_priv
, pll
);
1847 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
1850 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1853 struct drm_device
*dev
= dev_priv
->dev
;
1854 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1855 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1856 uint32_t reg
, val
, pipeconf_val
;
1858 /* PCH only available on ILK+ */
1859 BUG_ON(INTEL_INFO(dev
)->gen
< 5);
1861 /* Make sure PCH DPLL is enabled */
1862 assert_shared_dpll_enabled(dev_priv
,
1863 intel_crtc_to_shared_dpll(intel_crtc
));
1865 /* FDI must be feeding us bits for PCH ports */
1866 assert_fdi_tx_enabled(dev_priv
, pipe
);
1867 assert_fdi_rx_enabled(dev_priv
, pipe
);
1869 if (HAS_PCH_CPT(dev
)) {
1870 /* Workaround: Set the timing override bit before enabling the
1871 * pch transcoder. */
1872 reg
= TRANS_CHICKEN2(pipe
);
1873 val
= I915_READ(reg
);
1874 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1875 I915_WRITE(reg
, val
);
1878 reg
= PCH_TRANSCONF(pipe
);
1879 val
= I915_READ(reg
);
1880 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1882 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1884 * make the BPC in transcoder be consistent with
1885 * that in pipeconf reg.
1887 val
&= ~PIPECONF_BPC_MASK
;
1888 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
1891 val
&= ~TRANS_INTERLACE_MASK
;
1892 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1893 if (HAS_PCH_IBX(dev_priv
->dev
) &&
1894 intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
))
1895 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1897 val
|= TRANS_INTERLACED
;
1899 val
|= TRANS_PROGRESSIVE
;
1901 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1902 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1903 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
1906 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1907 enum transcoder cpu_transcoder
)
1909 u32 val
, pipeconf_val
;
1911 /* PCH only available on ILK+ */
1912 BUG_ON(INTEL_INFO(dev_priv
->dev
)->gen
< 5);
1914 /* FDI must be feeding us bits for PCH ports */
1915 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
1916 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
1918 /* Workaround: set timing override bit. */
1919 val
= I915_READ(_TRANSA_CHICKEN2
);
1920 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1921 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1924 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
1926 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
1927 PIPECONF_INTERLACED_ILK
)
1928 val
|= TRANS_INTERLACED
;
1930 val
|= TRANS_PROGRESSIVE
;
1932 I915_WRITE(LPT_TRANSCONF
, val
);
1933 if (wait_for(I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
, 100))
1934 DRM_ERROR("Failed to enable PCH transcoder\n");
1937 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1940 struct drm_device
*dev
= dev_priv
->dev
;
1943 /* FDI relies on the transcoder */
1944 assert_fdi_tx_disabled(dev_priv
, pipe
);
1945 assert_fdi_rx_disabled(dev_priv
, pipe
);
1947 /* Ports must be off as well */
1948 assert_pch_ports_disabled(dev_priv
, pipe
);
1950 reg
= PCH_TRANSCONF(pipe
);
1951 val
= I915_READ(reg
);
1952 val
&= ~TRANS_ENABLE
;
1953 I915_WRITE(reg
, val
);
1954 /* wait for PCH transcoder off, transcoder state */
1955 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
1956 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
1958 if (!HAS_PCH_IBX(dev
)) {
1959 /* Workaround: Clear the timing override chicken bit again. */
1960 reg
= TRANS_CHICKEN2(pipe
);
1961 val
= I915_READ(reg
);
1962 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1963 I915_WRITE(reg
, val
);
1967 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
1971 val
= I915_READ(LPT_TRANSCONF
);
1972 val
&= ~TRANS_ENABLE
;
1973 I915_WRITE(LPT_TRANSCONF
, val
);
1974 /* wait for PCH transcoder off, transcoder state */
1975 if (wait_for((I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
) == 0, 50))
1976 DRM_ERROR("Failed to disable PCH transcoder\n");
1978 /* Workaround: clear timing override bit. */
1979 val
= I915_READ(_TRANSA_CHICKEN2
);
1980 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1981 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1985 * intel_enable_pipe - enable a pipe, asserting requirements
1986 * @crtc: crtc responsible for the pipe
1988 * Enable @crtc's pipe, making sure that various hardware specific requirements
1989 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1991 static void intel_enable_pipe(struct intel_crtc
*crtc
)
1993 struct drm_device
*dev
= crtc
->base
.dev
;
1994 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1995 enum pipe pipe
= crtc
->pipe
;
1996 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1998 enum pipe pch_transcoder
;
2002 assert_planes_disabled(dev_priv
, pipe
);
2003 assert_cursor_disabled(dev_priv
, pipe
);
2004 assert_sprites_disabled(dev_priv
, pipe
);
2006 if (HAS_PCH_LPT(dev_priv
->dev
))
2007 pch_transcoder
= TRANSCODER_A
;
2009 pch_transcoder
= pipe
;
2012 * A pipe without a PLL won't actually be able to drive bits from
2013 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2016 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
2017 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DSI
))
2018 assert_dsi_pll_enabled(dev_priv
);
2020 assert_pll_enabled(dev_priv
, pipe
);
2022 if (crtc
->config
.has_pch_encoder
) {
2023 /* if driving the PCH, we need FDI enabled */
2024 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
2025 assert_fdi_tx_pll_enabled(dev_priv
,
2026 (enum pipe
) cpu_transcoder
);
2028 /* FIXME: assert CPU port conditions for SNB+ */
2031 reg
= PIPECONF(cpu_transcoder
);
2032 val
= I915_READ(reg
);
2033 if (val
& PIPECONF_ENABLE
) {
2034 WARN_ON(!(pipe
== PIPE_A
&&
2035 dev_priv
->quirks
& QUIRK_PIPEA_FORCE
));
2039 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
2044 * intel_disable_pipe - disable a pipe, asserting requirements
2045 * @crtc: crtc whose pipes is to be disabled
2047 * Disable the pipe of @crtc, making sure that various hardware
2048 * specific requirements are met, if applicable, e.g. plane
2049 * disabled, panel fitter off, etc.
2051 * Will wait until the pipe has shut down before returning.
2053 static void intel_disable_pipe(struct intel_crtc
*crtc
)
2055 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
2056 enum transcoder cpu_transcoder
= crtc
->config
.cpu_transcoder
;
2057 enum pipe pipe
= crtc
->pipe
;
2062 * Make sure planes won't keep trying to pump pixels to us,
2063 * or we might hang the display.
2065 assert_planes_disabled(dev_priv
, pipe
);
2066 assert_cursor_disabled(dev_priv
, pipe
);
2067 assert_sprites_disabled(dev_priv
, pipe
);
2069 reg
= PIPECONF(cpu_transcoder
);
2070 val
= I915_READ(reg
);
2071 if ((val
& PIPECONF_ENABLE
) == 0)
2075 * Double wide has implications for planes
2076 * so best keep it disabled when not needed.
2078 if (crtc
->config
.double_wide
)
2079 val
&= ~PIPECONF_DOUBLE_WIDE
;
2081 /* Don't disable pipe or pipe PLLs if needed */
2082 if (!(pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
2083 val
&= ~PIPECONF_ENABLE
;
2085 I915_WRITE(reg
, val
);
2086 if ((val
& PIPECONF_ENABLE
) == 0)
2087 intel_wait_for_pipe_off(crtc
);
2091 * Plane regs are double buffered, going from enabled->disabled needs a
2092 * trigger in order to latch. The display address reg provides this.
2094 void intel_flush_primary_plane(struct drm_i915_private
*dev_priv
,
2097 struct drm_device
*dev
= dev_priv
->dev
;
2098 u32 reg
= INTEL_INFO(dev
)->gen
>= 4 ? DSPSURF(plane
) : DSPADDR(plane
);
2100 I915_WRITE(reg
, I915_READ(reg
));
2105 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2106 * @plane: plane to be enabled
2107 * @crtc: crtc for the plane
2109 * Enable @plane on @crtc, making sure that the pipe is running first.
2111 static void intel_enable_primary_hw_plane(struct drm_plane
*plane
,
2112 struct drm_crtc
*crtc
)
2114 struct drm_device
*dev
= plane
->dev
;
2115 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2116 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2118 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2119 assert_pipe_enabled(dev_priv
, intel_crtc
->pipe
);
2121 if (intel_crtc
->primary_enabled
)
2124 intel_crtc
->primary_enabled
= true;
2126 dev_priv
->display
.update_primary_plane(crtc
, plane
->fb
,
2130 * BDW signals flip done immediately if the plane
2131 * is disabled, even if the plane enable is already
2132 * armed to occur at the next vblank :(
2134 if (IS_BROADWELL(dev
))
2135 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2139 * intel_disable_primary_hw_plane - disable the primary hardware plane
2140 * @plane: plane to be disabled
2141 * @crtc: crtc for the plane
2143 * Disable @plane on @crtc, making sure that the pipe is running first.
2145 static void intel_disable_primary_hw_plane(struct drm_plane
*plane
,
2146 struct drm_crtc
*crtc
)
2148 struct drm_device
*dev
= plane
->dev
;
2149 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2150 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2152 assert_pipe_enabled(dev_priv
, intel_crtc
->pipe
);
2154 if (!intel_crtc
->primary_enabled
)
2157 intel_crtc
->primary_enabled
= false;
2159 dev_priv
->display
.update_primary_plane(crtc
, plane
->fb
,
2163 static bool need_vtd_wa(struct drm_device
*dev
)
2165 #ifdef CONFIG_INTEL_IOMMU
2166 if (INTEL_INFO(dev
)->gen
>= 6 && intel_iommu_gfx_mapped
)
2172 static int intel_align_height(struct drm_device
*dev
, int height
, bool tiled
)
2176 tile_height
= tiled
? (IS_GEN2(dev
) ? 16 : 8) : 1;
2177 return ALIGN(height
, tile_height
);
2181 intel_pin_and_fence_fb_obj(struct drm_device
*dev
,
2182 struct drm_i915_gem_object
*obj
,
2183 struct intel_engine_cs
*pipelined
)
2185 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2189 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
2191 switch (obj
->tiling_mode
) {
2192 case I915_TILING_NONE
:
2193 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
2194 alignment
= 128 * 1024;
2195 else if (INTEL_INFO(dev
)->gen
>= 4)
2196 alignment
= 4 * 1024;
2198 alignment
= 64 * 1024;
2201 /* pin() will align the object as required by fence */
2205 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2211 /* Note that the w/a also requires 64 PTE of padding following the
2212 * bo. We currently fill all unused PTE with the shadow page and so
2213 * we should always have valid PTE following the scanout preventing
2216 if (need_vtd_wa(dev
) && alignment
< 256 * 1024)
2217 alignment
= 256 * 1024;
2219 dev_priv
->mm
.interruptible
= false;
2220 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
);
2222 goto err_interruptible
;
2224 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2225 * fence, whereas 965+ only requires a fence if using
2226 * framebuffer compression. For simplicity, we always install
2227 * a fence as the cost is not that onerous.
2229 ret
= i915_gem_object_get_fence(obj
);
2233 i915_gem_object_pin_fence(obj
);
2235 dev_priv
->mm
.interruptible
= true;
2239 i915_gem_object_unpin_from_display_plane(obj
);
2241 dev_priv
->mm
.interruptible
= true;
2245 void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
)
2247 WARN_ON(!mutex_is_locked(&obj
->base
.dev
->struct_mutex
));
2249 i915_gem_object_unpin_fence(obj
);
2250 i915_gem_object_unpin_from_display_plane(obj
);
2253 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2254 * is assumed to be a power-of-two. */
2255 unsigned long intel_gen4_compute_page_offset(int *x
, int *y
,
2256 unsigned int tiling_mode
,
2260 if (tiling_mode
!= I915_TILING_NONE
) {
2261 unsigned int tile_rows
, tiles
;
2266 tiles
= *x
/ (512/cpp
);
2269 return tile_rows
* pitch
* 8 + tiles
* 4096;
2271 unsigned int offset
;
2273 offset
= *y
* pitch
+ *x
* cpp
;
2275 *x
= (offset
& 4095) / cpp
;
2276 return offset
& -4096;
2280 int intel_format_to_fourcc(int format
)
2283 case DISPPLANE_8BPP
:
2284 return DRM_FORMAT_C8
;
2285 case DISPPLANE_BGRX555
:
2286 return DRM_FORMAT_XRGB1555
;
2287 case DISPPLANE_BGRX565
:
2288 return DRM_FORMAT_RGB565
;
2290 case DISPPLANE_BGRX888
:
2291 return DRM_FORMAT_XRGB8888
;
2292 case DISPPLANE_RGBX888
:
2293 return DRM_FORMAT_XBGR8888
;
2294 case DISPPLANE_BGRX101010
:
2295 return DRM_FORMAT_XRGB2101010
;
2296 case DISPPLANE_RGBX101010
:
2297 return DRM_FORMAT_XBGR2101010
;
2301 static bool intel_alloc_plane_obj(struct intel_crtc
*crtc
,
2302 struct intel_plane_config
*plane_config
)
2304 struct drm_device
*dev
= crtc
->base
.dev
;
2305 struct drm_i915_gem_object
*obj
= NULL
;
2306 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
2307 u32 base
= plane_config
->base
;
2309 if (plane_config
->size
== 0)
2312 obj
= i915_gem_object_create_stolen_for_preallocated(dev
, base
, base
,
2313 plane_config
->size
);
2317 if (plane_config
->tiled
) {
2318 obj
->tiling_mode
= I915_TILING_X
;
2319 obj
->stride
= crtc
->base
.primary
->fb
->pitches
[0];
2322 mode_cmd
.pixel_format
= crtc
->base
.primary
->fb
->pixel_format
;
2323 mode_cmd
.width
= crtc
->base
.primary
->fb
->width
;
2324 mode_cmd
.height
= crtc
->base
.primary
->fb
->height
;
2325 mode_cmd
.pitches
[0] = crtc
->base
.primary
->fb
->pitches
[0];
2327 mutex_lock(&dev
->struct_mutex
);
2329 if (intel_framebuffer_init(dev
, to_intel_framebuffer(crtc
->base
.primary
->fb
),
2331 DRM_DEBUG_KMS("intel fb init failed\n");
2335 obj
->frontbuffer_bits
= INTEL_FRONTBUFFER_PRIMARY(crtc
->pipe
);
2336 mutex_unlock(&dev
->struct_mutex
);
2338 DRM_DEBUG_KMS("plane fb obj %p\n", obj
);
2342 drm_gem_object_unreference(&obj
->base
);
2343 mutex_unlock(&dev
->struct_mutex
);
2347 static void intel_find_plane_obj(struct intel_crtc
*intel_crtc
,
2348 struct intel_plane_config
*plane_config
)
2350 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2352 struct intel_crtc
*i
;
2353 struct drm_i915_gem_object
*obj
;
2355 if (!intel_crtc
->base
.primary
->fb
)
2358 if (intel_alloc_plane_obj(intel_crtc
, plane_config
))
2361 kfree(intel_crtc
->base
.primary
->fb
);
2362 intel_crtc
->base
.primary
->fb
= NULL
;
2365 * Failed to alloc the obj, check to see if we should share
2366 * an fb with another CRTC instead
2368 for_each_crtc(dev
, c
) {
2369 i
= to_intel_crtc(c
);
2371 if (c
== &intel_crtc
->base
)
2377 obj
= intel_fb_obj(c
->primary
->fb
);
2381 if (i915_gem_obj_ggtt_offset(obj
) == plane_config
->base
) {
2382 drm_framebuffer_reference(c
->primary
->fb
);
2383 intel_crtc
->base
.primary
->fb
= c
->primary
->fb
;
2384 obj
->frontbuffer_bits
|= INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
);
2390 static void i9xx_update_primary_plane(struct drm_crtc
*crtc
,
2391 struct drm_framebuffer
*fb
,
2394 struct drm_device
*dev
= crtc
->dev
;
2395 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2396 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2397 struct drm_i915_gem_object
*obj
;
2398 int plane
= intel_crtc
->plane
;
2399 unsigned long linear_offset
;
2401 u32 reg
= DSPCNTR(plane
);
2404 if (!intel_crtc
->primary_enabled
) {
2406 if (INTEL_INFO(dev
)->gen
>= 4)
2407 I915_WRITE(DSPSURF(plane
), 0);
2409 I915_WRITE(DSPADDR(plane
), 0);
2414 obj
= intel_fb_obj(fb
);
2415 if (WARN_ON(obj
== NULL
))
2418 pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2420 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2422 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2424 if (INTEL_INFO(dev
)->gen
< 4) {
2425 if (intel_crtc
->pipe
== PIPE_B
)
2426 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
2428 /* pipesrc and dspsize control the size that is scaled from,
2429 * which should always be the user's requested size.
2431 I915_WRITE(DSPSIZE(plane
),
2432 ((intel_crtc
->config
.pipe_src_h
- 1) << 16) |
2433 (intel_crtc
->config
.pipe_src_w
- 1));
2434 I915_WRITE(DSPPOS(plane
), 0);
2437 switch (fb
->pixel_format
) {
2439 dspcntr
|= DISPPLANE_8BPP
;
2441 case DRM_FORMAT_XRGB1555
:
2442 case DRM_FORMAT_ARGB1555
:
2443 dspcntr
|= DISPPLANE_BGRX555
;
2445 case DRM_FORMAT_RGB565
:
2446 dspcntr
|= DISPPLANE_BGRX565
;
2448 case DRM_FORMAT_XRGB8888
:
2449 case DRM_FORMAT_ARGB8888
:
2450 dspcntr
|= DISPPLANE_BGRX888
;
2452 case DRM_FORMAT_XBGR8888
:
2453 case DRM_FORMAT_ABGR8888
:
2454 dspcntr
|= DISPPLANE_RGBX888
;
2456 case DRM_FORMAT_XRGB2101010
:
2457 case DRM_FORMAT_ARGB2101010
:
2458 dspcntr
|= DISPPLANE_BGRX101010
;
2460 case DRM_FORMAT_XBGR2101010
:
2461 case DRM_FORMAT_ABGR2101010
:
2462 dspcntr
|= DISPPLANE_RGBX101010
;
2468 if (INTEL_INFO(dev
)->gen
>= 4 &&
2469 obj
->tiling_mode
!= I915_TILING_NONE
)
2470 dspcntr
|= DISPPLANE_TILED
;
2473 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2475 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
2477 if (INTEL_INFO(dev
)->gen
>= 4) {
2478 intel_crtc
->dspaddr_offset
=
2479 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2482 linear_offset
-= intel_crtc
->dspaddr_offset
;
2484 intel_crtc
->dspaddr_offset
= linear_offset
;
2487 if (to_intel_plane(crtc
->primary
)->rotation
== BIT(DRM_ROTATE_180
)) {
2488 dspcntr
|= DISPPLANE_ROTATE_180
;
2490 x
+= (intel_crtc
->config
.pipe_src_w
- 1);
2491 y
+= (intel_crtc
->config
.pipe_src_h
- 1);
2493 /* Finding the last pixel of the last line of the display
2494 data and adding to linear_offset*/
2496 (intel_crtc
->config
.pipe_src_h
- 1) * fb
->pitches
[0] +
2497 (intel_crtc
->config
.pipe_src_w
- 1) * pixel_size
;
2500 I915_WRITE(reg
, dspcntr
);
2502 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2503 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2505 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2506 if (INTEL_INFO(dev
)->gen
>= 4) {
2507 I915_WRITE(DSPSURF(plane
),
2508 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2509 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2510 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2512 I915_WRITE(DSPADDR(plane
), i915_gem_obj_ggtt_offset(obj
) + linear_offset
);
2516 static void ironlake_update_primary_plane(struct drm_crtc
*crtc
,
2517 struct drm_framebuffer
*fb
,
2520 struct drm_device
*dev
= crtc
->dev
;
2521 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2522 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2523 struct drm_i915_gem_object
*obj
;
2524 int plane
= intel_crtc
->plane
;
2525 unsigned long linear_offset
;
2527 u32 reg
= DSPCNTR(plane
);
2530 if (!intel_crtc
->primary_enabled
) {
2532 I915_WRITE(DSPSURF(plane
), 0);
2537 obj
= intel_fb_obj(fb
);
2538 if (WARN_ON(obj
== NULL
))
2541 pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2543 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2545 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2547 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2548 dspcntr
|= DISPPLANE_PIPE_CSC_ENABLE
;
2550 switch (fb
->pixel_format
) {
2552 dspcntr
|= DISPPLANE_8BPP
;
2554 case DRM_FORMAT_RGB565
:
2555 dspcntr
|= DISPPLANE_BGRX565
;
2557 case DRM_FORMAT_XRGB8888
:
2558 case DRM_FORMAT_ARGB8888
:
2559 dspcntr
|= DISPPLANE_BGRX888
;
2561 case DRM_FORMAT_XBGR8888
:
2562 case DRM_FORMAT_ABGR8888
:
2563 dspcntr
|= DISPPLANE_RGBX888
;
2565 case DRM_FORMAT_XRGB2101010
:
2566 case DRM_FORMAT_ARGB2101010
:
2567 dspcntr
|= DISPPLANE_BGRX101010
;
2569 case DRM_FORMAT_XBGR2101010
:
2570 case DRM_FORMAT_ABGR2101010
:
2571 dspcntr
|= DISPPLANE_RGBX101010
;
2577 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2578 dspcntr
|= DISPPLANE_TILED
;
2580 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
))
2581 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2583 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
2584 intel_crtc
->dspaddr_offset
=
2585 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2588 linear_offset
-= intel_crtc
->dspaddr_offset
;
2589 if (to_intel_plane(crtc
->primary
)->rotation
== BIT(DRM_ROTATE_180
)) {
2590 dspcntr
|= DISPPLANE_ROTATE_180
;
2592 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
)) {
2593 x
+= (intel_crtc
->config
.pipe_src_w
- 1);
2594 y
+= (intel_crtc
->config
.pipe_src_h
- 1);
2596 /* Finding the last pixel of the last line of the display
2597 data and adding to linear_offset*/
2599 (intel_crtc
->config
.pipe_src_h
- 1) * fb
->pitches
[0] +
2600 (intel_crtc
->config
.pipe_src_w
- 1) * pixel_size
;
2604 I915_WRITE(reg
, dspcntr
);
2606 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2607 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2609 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2610 I915_WRITE(DSPSURF(plane
),
2611 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2612 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2613 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2615 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2616 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2621 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2623 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2624 int x
, int y
, enum mode_set_atomic state
)
2626 struct drm_device
*dev
= crtc
->dev
;
2627 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2629 if (dev_priv
->display
.disable_fbc
)
2630 dev_priv
->display
.disable_fbc(dev
);
2631 intel_increase_pllclock(dev
, to_intel_crtc(crtc
)->pipe
);
2633 dev_priv
->display
.update_primary_plane(crtc
, fb
, x
, y
);
2638 void intel_display_handle_reset(struct drm_device
*dev
)
2640 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2641 struct drm_crtc
*crtc
;
2644 * Flips in the rings have been nuked by the reset,
2645 * so complete all pending flips so that user space
2646 * will get its events and not get stuck.
2648 * Also update the base address of all primary
2649 * planes to the the last fb to make sure we're
2650 * showing the correct fb after a reset.
2652 * Need to make two loops over the crtcs so that we
2653 * don't try to grab a crtc mutex before the
2654 * pending_flip_queue really got woken up.
2657 for_each_crtc(dev
, crtc
) {
2658 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2659 enum plane plane
= intel_crtc
->plane
;
2661 intel_prepare_page_flip(dev
, plane
);
2662 intel_finish_page_flip_plane(dev
, plane
);
2665 for_each_crtc(dev
, crtc
) {
2666 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2668 drm_modeset_lock(&crtc
->mutex
, NULL
);
2670 * FIXME: Once we have proper support for primary planes (and
2671 * disabling them without disabling the entire crtc) allow again
2672 * a NULL crtc->primary->fb.
2674 if (intel_crtc
->active
&& crtc
->primary
->fb
)
2675 dev_priv
->display
.update_primary_plane(crtc
,
2679 drm_modeset_unlock(&crtc
->mutex
);
2684 intel_finish_fb(struct drm_framebuffer
*old_fb
)
2686 struct drm_i915_gem_object
*obj
= intel_fb_obj(old_fb
);
2687 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2688 bool was_interruptible
= dev_priv
->mm
.interruptible
;
2691 /* Big Hammer, we also need to ensure that any pending
2692 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2693 * current scanout is retired before unpinning the old
2696 * This should only fail upon a hung GPU, in which case we
2697 * can safely continue.
2699 dev_priv
->mm
.interruptible
= false;
2700 ret
= i915_gem_object_finish_gpu(obj
);
2701 dev_priv
->mm
.interruptible
= was_interruptible
;
2706 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
2708 struct drm_device
*dev
= crtc
->dev
;
2709 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2710 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2711 unsigned long flags
;
2714 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
2715 intel_crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
2718 spin_lock_irqsave(&dev
->event_lock
, flags
);
2719 pending
= to_intel_crtc(crtc
)->unpin_work
!= NULL
;
2720 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
2726 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2727 struct drm_framebuffer
*fb
)
2729 struct drm_device
*dev
= crtc
->dev
;
2730 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2731 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2732 enum pipe pipe
= intel_crtc
->pipe
;
2733 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
2734 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2735 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(old_fb
);
2738 if (intel_crtc_has_pending_flip(crtc
)) {
2739 DRM_ERROR("pipe is still busy with an old pageflip\n");
2745 DRM_ERROR("No FB bound\n");
2749 if (intel_crtc
->plane
> INTEL_INFO(dev
)->num_pipes
) {
2750 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2751 plane_name(intel_crtc
->plane
),
2752 INTEL_INFO(dev
)->num_pipes
);
2756 mutex_lock(&dev
->struct_mutex
);
2757 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, NULL
);
2759 i915_gem_track_fb(old_obj
, obj
,
2760 INTEL_FRONTBUFFER_PRIMARY(pipe
));
2761 mutex_unlock(&dev
->struct_mutex
);
2763 DRM_ERROR("pin & fence failed\n");
2768 * Update pipe size and adjust fitter if needed: the reason for this is
2769 * that in compute_mode_changes we check the native mode (not the pfit
2770 * mode) to see if we can flip rather than do a full mode set. In the
2771 * fastboot case, we'll flip, but if we don't update the pipesrc and
2772 * pfit state, we'll end up with a big fb scanned out into the wrong
2775 * To fix this properly, we need to hoist the checks up into
2776 * compute_mode_changes (or above), check the actual pfit state and
2777 * whether the platform allows pfit disable with pipe active, and only
2778 * then update the pipesrc and pfit state, even on the flip path.
2780 if (i915
.fastboot
) {
2781 const struct drm_display_mode
*adjusted_mode
=
2782 &intel_crtc
->config
.adjusted_mode
;
2784 I915_WRITE(PIPESRC(intel_crtc
->pipe
),
2785 ((adjusted_mode
->crtc_hdisplay
- 1) << 16) |
2786 (adjusted_mode
->crtc_vdisplay
- 1));
2787 if (!intel_crtc
->config
.pch_pfit
.enabled
&&
2788 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) ||
2789 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
2790 I915_WRITE(PF_CTL(intel_crtc
->pipe
), 0);
2791 I915_WRITE(PF_WIN_POS(intel_crtc
->pipe
), 0);
2792 I915_WRITE(PF_WIN_SZ(intel_crtc
->pipe
), 0);
2794 intel_crtc
->config
.pipe_src_w
= adjusted_mode
->crtc_hdisplay
;
2795 intel_crtc
->config
.pipe_src_h
= adjusted_mode
->crtc_vdisplay
;
2798 dev_priv
->display
.update_primary_plane(crtc
, fb
, x
, y
);
2800 if (intel_crtc
->active
)
2801 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
2803 crtc
->primary
->fb
= fb
;
2808 if (intel_crtc
->active
&& old_fb
!= fb
)
2809 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2810 mutex_lock(&dev
->struct_mutex
);
2811 intel_unpin_fb_obj(old_obj
);
2812 mutex_unlock(&dev
->struct_mutex
);
2815 mutex_lock(&dev
->struct_mutex
);
2816 intel_update_fbc(dev
);
2817 mutex_unlock(&dev
->struct_mutex
);
2822 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
2824 struct drm_device
*dev
= crtc
->dev
;
2825 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2826 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2827 int pipe
= intel_crtc
->pipe
;
2830 /* enable normal train */
2831 reg
= FDI_TX_CTL(pipe
);
2832 temp
= I915_READ(reg
);
2833 if (IS_IVYBRIDGE(dev
)) {
2834 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2835 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2837 temp
&= ~FDI_LINK_TRAIN_NONE
;
2838 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2840 I915_WRITE(reg
, temp
);
2842 reg
= FDI_RX_CTL(pipe
);
2843 temp
= I915_READ(reg
);
2844 if (HAS_PCH_CPT(dev
)) {
2845 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2846 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
2848 temp
&= ~FDI_LINK_TRAIN_NONE
;
2849 temp
|= FDI_LINK_TRAIN_NONE
;
2851 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
2853 /* wait one idle pattern time */
2857 /* IVB wants error correction enabled */
2858 if (IS_IVYBRIDGE(dev
))
2859 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
2860 FDI_FE_ERRC_ENABLE
);
2863 static bool pipe_has_enabled_pch(struct intel_crtc
*crtc
)
2865 return crtc
->base
.enabled
&& crtc
->active
&&
2866 crtc
->config
.has_pch_encoder
;
2869 static void ivb_modeset_global_resources(struct drm_device
*dev
)
2871 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2872 struct intel_crtc
*pipe_B_crtc
=
2873 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
2874 struct intel_crtc
*pipe_C_crtc
=
2875 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]);
2879 * When everything is off disable fdi C so that we could enable fdi B
2880 * with all lanes. Note that we don't care about enabled pipes without
2881 * an enabled pch encoder.
2883 if (!pipe_has_enabled_pch(pipe_B_crtc
) &&
2884 !pipe_has_enabled_pch(pipe_C_crtc
)) {
2885 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
2886 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
2888 temp
= I915_READ(SOUTH_CHICKEN1
);
2889 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
2890 DRM_DEBUG_KMS("disabling fdi C rx\n");
2891 I915_WRITE(SOUTH_CHICKEN1
, temp
);
2895 /* The FDI link training functions for ILK/Ibexpeak. */
2896 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
2898 struct drm_device
*dev
= crtc
->dev
;
2899 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2900 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2901 int pipe
= intel_crtc
->pipe
;
2902 u32 reg
, temp
, tries
;
2904 /* FDI needs bits from pipe first */
2905 assert_pipe_enabled(dev_priv
, pipe
);
2907 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2909 reg
= FDI_RX_IMR(pipe
);
2910 temp
= I915_READ(reg
);
2911 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2912 temp
&= ~FDI_RX_BIT_LOCK
;
2913 I915_WRITE(reg
, temp
);
2917 /* enable CPU FDI TX and PCH FDI RX */
2918 reg
= FDI_TX_CTL(pipe
);
2919 temp
= I915_READ(reg
);
2920 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
2921 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2922 temp
&= ~FDI_LINK_TRAIN_NONE
;
2923 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2924 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2926 reg
= FDI_RX_CTL(pipe
);
2927 temp
= I915_READ(reg
);
2928 temp
&= ~FDI_LINK_TRAIN_NONE
;
2929 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2930 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2935 /* Ironlake workaround, enable clock pointer after FDI enable*/
2936 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2937 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
2938 FDI_RX_PHASE_SYNC_POINTER_EN
);
2940 reg
= FDI_RX_IIR(pipe
);
2941 for (tries
= 0; tries
< 5; tries
++) {
2942 temp
= I915_READ(reg
);
2943 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2945 if ((temp
& FDI_RX_BIT_LOCK
)) {
2946 DRM_DEBUG_KMS("FDI train 1 done.\n");
2947 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2952 DRM_ERROR("FDI train 1 fail!\n");
2955 reg
= FDI_TX_CTL(pipe
);
2956 temp
= I915_READ(reg
);
2957 temp
&= ~FDI_LINK_TRAIN_NONE
;
2958 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2959 I915_WRITE(reg
, temp
);
2961 reg
= FDI_RX_CTL(pipe
);
2962 temp
= I915_READ(reg
);
2963 temp
&= ~FDI_LINK_TRAIN_NONE
;
2964 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2965 I915_WRITE(reg
, temp
);
2970 reg
= FDI_RX_IIR(pipe
);
2971 for (tries
= 0; tries
< 5; tries
++) {
2972 temp
= I915_READ(reg
);
2973 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2975 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2976 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2977 DRM_DEBUG_KMS("FDI train 2 done.\n");
2982 DRM_ERROR("FDI train 2 fail!\n");
2984 DRM_DEBUG_KMS("FDI train done\n");
2988 static const int snb_b_fdi_train_param
[] = {
2989 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
2990 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
2991 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
2992 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
2995 /* The FDI link training functions for SNB/Cougarpoint. */
2996 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
2998 struct drm_device
*dev
= crtc
->dev
;
2999 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3000 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3001 int pipe
= intel_crtc
->pipe
;
3002 u32 reg
, temp
, i
, retry
;
3004 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3006 reg
= FDI_RX_IMR(pipe
);
3007 temp
= I915_READ(reg
);
3008 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3009 temp
&= ~FDI_RX_BIT_LOCK
;
3010 I915_WRITE(reg
, temp
);
3015 /* enable CPU FDI TX and PCH FDI RX */
3016 reg
= FDI_TX_CTL(pipe
);
3017 temp
= I915_READ(reg
);
3018 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3019 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
3020 temp
&= ~FDI_LINK_TRAIN_NONE
;
3021 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3022 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3024 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3025 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3027 I915_WRITE(FDI_RX_MISC(pipe
),
3028 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3030 reg
= FDI_RX_CTL(pipe
);
3031 temp
= I915_READ(reg
);
3032 if (HAS_PCH_CPT(dev
)) {
3033 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3034 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3036 temp
&= ~FDI_LINK_TRAIN_NONE
;
3037 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3039 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3044 for (i
= 0; i
< 4; i
++) {
3045 reg
= FDI_TX_CTL(pipe
);
3046 temp
= I915_READ(reg
);
3047 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3048 temp
|= snb_b_fdi_train_param
[i
];
3049 I915_WRITE(reg
, temp
);
3054 for (retry
= 0; retry
< 5; retry
++) {
3055 reg
= FDI_RX_IIR(pipe
);
3056 temp
= I915_READ(reg
);
3057 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3058 if (temp
& FDI_RX_BIT_LOCK
) {
3059 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3060 DRM_DEBUG_KMS("FDI train 1 done.\n");
3069 DRM_ERROR("FDI train 1 fail!\n");
3072 reg
= FDI_TX_CTL(pipe
);
3073 temp
= I915_READ(reg
);
3074 temp
&= ~FDI_LINK_TRAIN_NONE
;
3075 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3077 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3079 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3081 I915_WRITE(reg
, temp
);
3083 reg
= FDI_RX_CTL(pipe
);
3084 temp
= I915_READ(reg
);
3085 if (HAS_PCH_CPT(dev
)) {
3086 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3087 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3089 temp
&= ~FDI_LINK_TRAIN_NONE
;
3090 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3092 I915_WRITE(reg
, temp
);
3097 for (i
= 0; i
< 4; i
++) {
3098 reg
= FDI_TX_CTL(pipe
);
3099 temp
= I915_READ(reg
);
3100 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3101 temp
|= snb_b_fdi_train_param
[i
];
3102 I915_WRITE(reg
, temp
);
3107 for (retry
= 0; retry
< 5; retry
++) {
3108 reg
= FDI_RX_IIR(pipe
);
3109 temp
= I915_READ(reg
);
3110 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3111 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3112 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3113 DRM_DEBUG_KMS("FDI train 2 done.\n");
3122 DRM_ERROR("FDI train 2 fail!\n");
3124 DRM_DEBUG_KMS("FDI train done.\n");
3127 /* Manual link training for Ivy Bridge A0 parts */
3128 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
3130 struct drm_device
*dev
= crtc
->dev
;
3131 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3132 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3133 int pipe
= intel_crtc
->pipe
;
3134 u32 reg
, temp
, i
, j
;
3136 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3138 reg
= FDI_RX_IMR(pipe
);
3139 temp
= I915_READ(reg
);
3140 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3141 temp
&= ~FDI_RX_BIT_LOCK
;
3142 I915_WRITE(reg
, temp
);
3147 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3148 I915_READ(FDI_RX_IIR(pipe
)));
3150 /* Try each vswing and preemphasis setting twice before moving on */
3151 for (j
= 0; j
< ARRAY_SIZE(snb_b_fdi_train_param
) * 2; j
++) {
3152 /* disable first in case we need to retry */
3153 reg
= FDI_TX_CTL(pipe
);
3154 temp
= I915_READ(reg
);
3155 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
3156 temp
&= ~FDI_TX_ENABLE
;
3157 I915_WRITE(reg
, temp
);
3159 reg
= FDI_RX_CTL(pipe
);
3160 temp
= I915_READ(reg
);
3161 temp
&= ~FDI_LINK_TRAIN_AUTO
;
3162 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3163 temp
&= ~FDI_RX_ENABLE
;
3164 I915_WRITE(reg
, temp
);
3166 /* enable CPU FDI TX and PCH FDI RX */
3167 reg
= FDI_TX_CTL(pipe
);
3168 temp
= I915_READ(reg
);
3169 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3170 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
3171 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
3172 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3173 temp
|= snb_b_fdi_train_param
[j
/2];
3174 temp
|= FDI_COMPOSITE_SYNC
;
3175 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3177 I915_WRITE(FDI_RX_MISC(pipe
),
3178 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3180 reg
= FDI_RX_CTL(pipe
);
3181 temp
= I915_READ(reg
);
3182 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3183 temp
|= FDI_COMPOSITE_SYNC
;
3184 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3187 udelay(1); /* should be 0.5us */
3189 for (i
= 0; i
< 4; i
++) {
3190 reg
= FDI_RX_IIR(pipe
);
3191 temp
= I915_READ(reg
);
3192 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3194 if (temp
& FDI_RX_BIT_LOCK
||
3195 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
3196 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3197 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3201 udelay(1); /* should be 0.5us */
3204 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j
/ 2);
3209 reg
= FDI_TX_CTL(pipe
);
3210 temp
= I915_READ(reg
);
3211 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3212 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
3213 I915_WRITE(reg
, temp
);
3215 reg
= FDI_RX_CTL(pipe
);
3216 temp
= I915_READ(reg
);
3217 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3218 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3219 I915_WRITE(reg
, temp
);
3222 udelay(2); /* should be 1.5us */
3224 for (i
= 0; i
< 4; i
++) {
3225 reg
= FDI_RX_IIR(pipe
);
3226 temp
= I915_READ(reg
);
3227 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3229 if (temp
& FDI_RX_SYMBOL_LOCK
||
3230 (I915_READ(reg
) & FDI_RX_SYMBOL_LOCK
)) {
3231 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3232 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3236 udelay(2); /* should be 1.5us */
3239 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j
/ 2);
3243 DRM_DEBUG_KMS("FDI train done.\n");
3246 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
3248 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3249 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3250 int pipe
= intel_crtc
->pipe
;
3254 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3255 reg
= FDI_RX_CTL(pipe
);
3256 temp
= I915_READ(reg
);
3257 temp
&= ~(FDI_DP_PORT_WIDTH_MASK
| (0x7 << 16));
3258 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
3259 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3260 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
3265 /* Switch from Rawclk to PCDclk */
3266 temp
= I915_READ(reg
);
3267 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
3272 /* Enable CPU FDI TX PLL, always on for Ironlake */
3273 reg
= FDI_TX_CTL(pipe
);
3274 temp
= I915_READ(reg
);
3275 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
3276 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
3283 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
3285 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3286 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3287 int pipe
= intel_crtc
->pipe
;
3290 /* Switch from PCDclk to Rawclk */
3291 reg
= FDI_RX_CTL(pipe
);
3292 temp
= I915_READ(reg
);
3293 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
3295 /* Disable CPU FDI TX PLL */
3296 reg
= FDI_TX_CTL(pipe
);
3297 temp
= I915_READ(reg
);
3298 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
3303 reg
= FDI_RX_CTL(pipe
);
3304 temp
= I915_READ(reg
);
3305 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
3307 /* Wait for the clocks to turn off. */
3312 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
3314 struct drm_device
*dev
= crtc
->dev
;
3315 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3316 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3317 int pipe
= intel_crtc
->pipe
;
3320 /* disable CPU FDI tx and PCH FDI rx */
3321 reg
= FDI_TX_CTL(pipe
);
3322 temp
= I915_READ(reg
);
3323 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
3326 reg
= FDI_RX_CTL(pipe
);
3327 temp
= I915_READ(reg
);
3328 temp
&= ~(0x7 << 16);
3329 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3330 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
3335 /* Ironlake workaround, disable clock pointer after downing FDI */
3336 if (HAS_PCH_IBX(dev
))
3337 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3339 /* still set train pattern 1 */
3340 reg
= FDI_TX_CTL(pipe
);
3341 temp
= I915_READ(reg
);
3342 temp
&= ~FDI_LINK_TRAIN_NONE
;
3343 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3344 I915_WRITE(reg
, temp
);
3346 reg
= FDI_RX_CTL(pipe
);
3347 temp
= I915_READ(reg
);
3348 if (HAS_PCH_CPT(dev
)) {
3349 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3350 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3352 temp
&= ~FDI_LINK_TRAIN_NONE
;
3353 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3355 /* BPC in FDI rx is consistent with that in PIPECONF */
3356 temp
&= ~(0x07 << 16);
3357 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3358 I915_WRITE(reg
, temp
);
3364 bool intel_has_pending_fb_unpin(struct drm_device
*dev
)
3366 struct intel_crtc
*crtc
;
3368 /* Note that we don't need to be called with mode_config.lock here
3369 * as our list of CRTC objects is static for the lifetime of the
3370 * device and so cannot disappear as we iterate. Similarly, we can
3371 * happily treat the predicates as racy, atomic checks as userspace
3372 * cannot claim and pin a new fb without at least acquring the
3373 * struct_mutex and so serialising with us.
3375 for_each_intel_crtc(dev
, crtc
) {
3376 if (atomic_read(&crtc
->unpin_work_count
) == 0)
3379 if (crtc
->unpin_work
)
3380 intel_wait_for_vblank(dev
, crtc
->pipe
);
3388 void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
3390 struct drm_device
*dev
= crtc
->dev
;
3391 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3393 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
3394 WARN_ON(wait_event_timeout(dev_priv
->pending_flip_queue
,
3395 !intel_crtc_has_pending_flip(crtc
),
3398 if (crtc
->primary
->fb
) {
3399 mutex_lock(&dev
->struct_mutex
);
3400 intel_finish_fb(crtc
->primary
->fb
);
3401 mutex_unlock(&dev
->struct_mutex
);
3405 /* Program iCLKIP clock to the desired frequency */
3406 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
3408 struct drm_device
*dev
= crtc
->dev
;
3409 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3410 int clock
= to_intel_crtc(crtc
)->config
.adjusted_mode
.crtc_clock
;
3411 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
3414 mutex_lock(&dev_priv
->dpio_lock
);
3416 /* It is necessary to ungate the pixclk gate prior to programming
3417 * the divisors, and gate it back when it is done.
3419 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
3421 /* Disable SSCCTL */
3422 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
3423 intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
) |
3427 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3428 if (clock
== 20000) {
3433 /* The iCLK virtual clock root frequency is in MHz,
3434 * but the adjusted_mode->crtc_clock in in KHz. To get the
3435 * divisors, it is necessary to divide one by another, so we
3436 * convert the virtual clock precision to KHz here for higher
3439 u32 iclk_virtual_root_freq
= 172800 * 1000;
3440 u32 iclk_pi_range
= 64;
3441 u32 desired_divisor
, msb_divisor_value
, pi_value
;
3443 desired_divisor
= (iclk_virtual_root_freq
/ clock
);
3444 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
3445 pi_value
= desired_divisor
% iclk_pi_range
;
3448 divsel
= msb_divisor_value
- 2;
3449 phaseinc
= pi_value
;
3452 /* This should not happen with any sane values */
3453 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
3454 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
3455 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
3456 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
3458 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3465 /* Program SSCDIVINTPHASE6 */
3466 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
3467 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
3468 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
3469 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
3470 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
3471 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
3472 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
3473 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
3475 /* Program SSCAUXDIV */
3476 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
3477 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3478 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
3479 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
3481 /* Enable modulator and associated divider */
3482 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
3483 temp
&= ~SBI_SSCCTL_DISABLE
;
3484 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
3486 /* Wait for initialization time */
3489 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
3491 mutex_unlock(&dev_priv
->dpio_lock
);
3494 static void ironlake_pch_transcoder_set_timings(struct intel_crtc
*crtc
,
3495 enum pipe pch_transcoder
)
3497 struct drm_device
*dev
= crtc
->base
.dev
;
3498 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3499 enum transcoder cpu_transcoder
= crtc
->config
.cpu_transcoder
;
3501 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder
),
3502 I915_READ(HTOTAL(cpu_transcoder
)));
3503 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder
),
3504 I915_READ(HBLANK(cpu_transcoder
)));
3505 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder
),
3506 I915_READ(HSYNC(cpu_transcoder
)));
3508 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder
),
3509 I915_READ(VTOTAL(cpu_transcoder
)));
3510 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder
),
3511 I915_READ(VBLANK(cpu_transcoder
)));
3512 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder
),
3513 I915_READ(VSYNC(cpu_transcoder
)));
3514 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder
),
3515 I915_READ(VSYNCSHIFT(cpu_transcoder
)));
3518 static void cpt_enable_fdi_bc_bifurcation(struct drm_device
*dev
)
3520 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3523 temp
= I915_READ(SOUTH_CHICKEN1
);
3524 if (temp
& FDI_BC_BIFURCATION_SELECT
)
3527 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
3528 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
3530 temp
|= FDI_BC_BIFURCATION_SELECT
;
3531 DRM_DEBUG_KMS("enabling fdi C rx\n");
3532 I915_WRITE(SOUTH_CHICKEN1
, temp
);
3533 POSTING_READ(SOUTH_CHICKEN1
);
3536 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc
*intel_crtc
)
3538 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3539 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3541 switch (intel_crtc
->pipe
) {
3545 if (intel_crtc
->config
.fdi_lanes
> 2)
3546 WARN_ON(I915_READ(SOUTH_CHICKEN1
) & FDI_BC_BIFURCATION_SELECT
);
3548 cpt_enable_fdi_bc_bifurcation(dev
);
3552 cpt_enable_fdi_bc_bifurcation(dev
);
3561 * Enable PCH resources required for PCH ports:
3563 * - FDI training & RX/TX
3564 * - update transcoder timings
3565 * - DP transcoding bits
3568 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
3570 struct drm_device
*dev
= crtc
->dev
;
3571 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3572 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3573 int pipe
= intel_crtc
->pipe
;
3576 assert_pch_transcoder_disabled(dev_priv
, pipe
);
3578 if (IS_IVYBRIDGE(dev
))
3579 ivybridge_update_fdi_bc_bifurcation(intel_crtc
);
3581 /* Write the TU size bits before fdi link training, so that error
3582 * detection works. */
3583 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
3584 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
3586 /* For PCH output, training FDI link */
3587 dev_priv
->display
.fdi_link_train(crtc
);
3589 /* We need to program the right clock selection before writing the pixel
3590 * mutliplier into the DPLL. */
3591 if (HAS_PCH_CPT(dev
)) {
3594 temp
= I915_READ(PCH_DPLL_SEL
);
3595 temp
|= TRANS_DPLL_ENABLE(pipe
);
3596 sel
= TRANS_DPLLB_SEL(pipe
);
3597 if (intel_crtc
->config
.shared_dpll
== DPLL_ID_PCH_PLL_B
)
3601 I915_WRITE(PCH_DPLL_SEL
, temp
);
3604 /* XXX: pch pll's can be enabled any time before we enable the PCH
3605 * transcoder, and we actually should do this to not upset any PCH
3606 * transcoder that already use the clock when we share it.
3608 * Note that enable_shared_dpll tries to do the right thing, but
3609 * get_shared_dpll unconditionally resets the pll - we need that to have
3610 * the right LVDS enable sequence. */
3611 intel_enable_shared_dpll(intel_crtc
);
3613 /* set transcoder timing, panel must allow it */
3614 assert_panel_unlocked(dev_priv
, pipe
);
3615 ironlake_pch_transcoder_set_timings(intel_crtc
, pipe
);
3617 intel_fdi_normal_train(crtc
);
3619 /* For PCH DP, enable TRANS_DP_CTL */
3620 if (HAS_PCH_CPT(dev
) &&
3621 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
3622 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3623 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
3624 reg
= TRANS_DP_CTL(pipe
);
3625 temp
= I915_READ(reg
);
3626 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
3627 TRANS_DP_SYNC_MASK
|
3629 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
3630 TRANS_DP_ENH_FRAMING
);
3631 temp
|= bpc
<< 9; /* same format but at 11:9 */
3633 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
3634 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
3635 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
3636 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
3638 switch (intel_trans_dp_port_sel(crtc
)) {
3640 temp
|= TRANS_DP_PORT_SEL_B
;
3643 temp
|= TRANS_DP_PORT_SEL_C
;
3646 temp
|= TRANS_DP_PORT_SEL_D
;
3652 I915_WRITE(reg
, temp
);
3655 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
3658 static void lpt_pch_enable(struct drm_crtc
*crtc
)
3660 struct drm_device
*dev
= crtc
->dev
;
3661 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3662 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3663 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
3665 assert_pch_transcoder_disabled(dev_priv
, TRANSCODER_A
);
3667 lpt_program_iclkip(crtc
);
3669 /* Set transcoder timing. */
3670 ironlake_pch_transcoder_set_timings(intel_crtc
, PIPE_A
);
3672 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
3675 void intel_put_shared_dpll(struct intel_crtc
*crtc
)
3677 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
3682 if (pll
->refcount
== 0) {
3683 WARN(1, "bad %s refcount\n", pll
->name
);
3687 if (--pll
->refcount
== 0) {
3689 WARN_ON(pll
->active
);
3692 crtc
->config
.shared_dpll
= DPLL_ID_PRIVATE
;
3695 struct intel_shared_dpll
*intel_get_shared_dpll(struct intel_crtc
*crtc
)
3697 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
3698 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
3699 enum intel_dpll_id i
;
3702 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3703 crtc
->base
.base
.id
, pll
->name
);
3704 intel_put_shared_dpll(crtc
);
3707 if (HAS_PCH_IBX(dev_priv
->dev
)) {
3708 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3709 i
= (enum intel_dpll_id
) crtc
->pipe
;
3710 pll
= &dev_priv
->shared_dplls
[i
];
3712 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3713 crtc
->base
.base
.id
, pll
->name
);
3715 WARN_ON(pll
->refcount
);
3720 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3721 pll
= &dev_priv
->shared_dplls
[i
];
3723 /* Only want to check enabled timings first */
3724 if (pll
->refcount
== 0)
3727 if (memcmp(&crtc
->config
.dpll_hw_state
, &pll
->hw_state
,
3728 sizeof(pll
->hw_state
)) == 0) {
3729 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3731 pll
->name
, pll
->refcount
, pll
->active
);
3737 /* Ok no matching timings, maybe there's a free one? */
3738 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3739 pll
= &dev_priv
->shared_dplls
[i
];
3740 if (pll
->refcount
== 0) {
3741 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3742 crtc
->base
.base
.id
, pll
->name
);
3750 if (pll
->refcount
== 0)
3751 pll
->hw_state
= crtc
->config
.dpll_hw_state
;
3753 crtc
->config
.shared_dpll
= i
;
3754 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll
->name
,
3755 pipe_name(crtc
->pipe
));
3762 static void cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
3764 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3765 int dslreg
= PIPEDSL(pipe
);
3768 temp
= I915_READ(dslreg
);
3770 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
3771 if (wait_for(I915_READ(dslreg
) != temp
, 5))
3772 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
3776 static void ironlake_pfit_enable(struct intel_crtc
*crtc
)
3778 struct drm_device
*dev
= crtc
->base
.dev
;
3779 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3780 int pipe
= crtc
->pipe
;
3782 if (crtc
->config
.pch_pfit
.enabled
) {
3783 /* Force use of hard-coded filter coefficients
3784 * as some pre-programmed values are broken,
3787 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
3788 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
3789 PF_PIPE_SEL_IVB(pipe
));
3791 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
3792 I915_WRITE(PF_WIN_POS(pipe
), crtc
->config
.pch_pfit
.pos
);
3793 I915_WRITE(PF_WIN_SZ(pipe
), crtc
->config
.pch_pfit
.size
);
3797 static void intel_enable_planes(struct drm_crtc
*crtc
)
3799 struct drm_device
*dev
= crtc
->dev
;
3800 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
3801 struct drm_plane
*plane
;
3802 struct intel_plane
*intel_plane
;
3804 drm_for_each_legacy_plane(plane
, &dev
->mode_config
.plane_list
) {
3805 intel_plane
= to_intel_plane(plane
);
3806 if (intel_plane
->pipe
== pipe
)
3807 intel_plane_restore(&intel_plane
->base
);
3811 static void intel_disable_planes(struct drm_crtc
*crtc
)
3813 struct drm_device
*dev
= crtc
->dev
;
3814 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
3815 struct drm_plane
*plane
;
3816 struct intel_plane
*intel_plane
;
3818 drm_for_each_legacy_plane(plane
, &dev
->mode_config
.plane_list
) {
3819 intel_plane
= to_intel_plane(plane
);
3820 if (intel_plane
->pipe
== pipe
)
3821 intel_plane_disable(&intel_plane
->base
);
3825 void hsw_enable_ips(struct intel_crtc
*crtc
)
3827 struct drm_device
*dev
= crtc
->base
.dev
;
3828 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3830 if (!crtc
->config
.ips_enabled
)
3833 /* We can only enable IPS after we enable a plane and wait for a vblank */
3834 intel_wait_for_vblank(dev
, crtc
->pipe
);
3836 assert_plane_enabled(dev_priv
, crtc
->plane
);
3837 if (IS_BROADWELL(dev
)) {
3838 mutex_lock(&dev_priv
->rps
.hw_lock
);
3839 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0xc0000000));
3840 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3841 /* Quoting Art Runyan: "its not safe to expect any particular
3842 * value in IPS_CTL bit 31 after enabling IPS through the
3843 * mailbox." Moreover, the mailbox may return a bogus state,
3844 * so we need to just enable it and continue on.
3847 I915_WRITE(IPS_CTL
, IPS_ENABLE
);
3848 /* The bit only becomes 1 in the next vblank, so this wait here
3849 * is essentially intel_wait_for_vblank. If we don't have this
3850 * and don't wait for vblanks until the end of crtc_enable, then
3851 * the HW state readout code will complain that the expected
3852 * IPS_CTL value is not the one we read. */
3853 if (wait_for(I915_READ_NOTRACE(IPS_CTL
) & IPS_ENABLE
, 50))
3854 DRM_ERROR("Timed out waiting for IPS enable\n");
3858 void hsw_disable_ips(struct intel_crtc
*crtc
)
3860 struct drm_device
*dev
= crtc
->base
.dev
;
3861 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3863 if (!crtc
->config
.ips_enabled
)
3866 assert_plane_enabled(dev_priv
, crtc
->plane
);
3867 if (IS_BROADWELL(dev
)) {
3868 mutex_lock(&dev_priv
->rps
.hw_lock
);
3869 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0));
3870 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3871 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3872 if (wait_for((I915_READ(IPS_CTL
) & IPS_ENABLE
) == 0, 42))
3873 DRM_ERROR("Timed out waiting for IPS disable\n");
3875 I915_WRITE(IPS_CTL
, 0);
3876 POSTING_READ(IPS_CTL
);
3879 /* We need to wait for a vblank before we can disable the plane. */
3880 intel_wait_for_vblank(dev
, crtc
->pipe
);
3883 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3884 static void intel_crtc_load_lut(struct drm_crtc
*crtc
)
3886 struct drm_device
*dev
= crtc
->dev
;
3887 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3888 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3889 enum pipe pipe
= intel_crtc
->pipe
;
3890 int palreg
= PALETTE(pipe
);
3892 bool reenable_ips
= false;
3894 /* The clocks have to be on to load the palette. */
3895 if (!crtc
->enabled
|| !intel_crtc
->active
)
3898 if (!HAS_PCH_SPLIT(dev_priv
->dev
)) {
3899 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
))
3900 assert_dsi_pll_enabled(dev_priv
);
3902 assert_pll_enabled(dev_priv
, pipe
);
3905 /* use legacy palette for Ironlake */
3906 if (!HAS_GMCH_DISPLAY(dev
))
3907 palreg
= LGC_PALETTE(pipe
);
3909 /* Workaround : Do not read or write the pipe palette/gamma data while
3910 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3912 if (IS_HASWELL(dev
) && intel_crtc
->config
.ips_enabled
&&
3913 ((I915_READ(GAMMA_MODE(pipe
)) & GAMMA_MODE_MODE_MASK
) ==
3914 GAMMA_MODE_MODE_SPLIT
)) {
3915 hsw_disable_ips(intel_crtc
);
3916 reenable_ips
= true;
3919 for (i
= 0; i
< 256; i
++) {
3920 I915_WRITE(palreg
+ 4 * i
,
3921 (intel_crtc
->lut_r
[i
] << 16) |
3922 (intel_crtc
->lut_g
[i
] << 8) |
3923 intel_crtc
->lut_b
[i
]);
3927 hsw_enable_ips(intel_crtc
);
3930 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
3932 if (!enable
&& intel_crtc
->overlay
) {
3933 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3934 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3936 mutex_lock(&dev
->struct_mutex
);
3937 dev_priv
->mm
.interruptible
= false;
3938 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
3939 dev_priv
->mm
.interruptible
= true;
3940 mutex_unlock(&dev
->struct_mutex
);
3943 /* Let userspace switch the overlay on again. In most cases userspace
3944 * has to recompute where to put it anyway.
3948 static void intel_crtc_enable_planes(struct drm_crtc
*crtc
)
3950 struct drm_device
*dev
= crtc
->dev
;
3951 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3952 int pipe
= intel_crtc
->pipe
;
3954 drm_vblank_on(dev
, pipe
);
3956 intel_enable_primary_hw_plane(crtc
->primary
, crtc
);
3957 intel_enable_planes(crtc
);
3958 intel_crtc_update_cursor(crtc
, true);
3959 intel_crtc_dpms_overlay(intel_crtc
, true);
3961 hsw_enable_ips(intel_crtc
);
3963 mutex_lock(&dev
->struct_mutex
);
3964 intel_update_fbc(dev
);
3965 mutex_unlock(&dev
->struct_mutex
);
3968 * FIXME: Once we grow proper nuclear flip support out of this we need
3969 * to compute the mask of flip planes precisely. For the time being
3970 * consider this a flip from a NULL plane.
3972 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_ALL_MASK(pipe
));
3975 static void intel_crtc_disable_planes(struct drm_crtc
*crtc
)
3977 struct drm_device
*dev
= crtc
->dev
;
3978 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3979 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3980 int pipe
= intel_crtc
->pipe
;
3981 int plane
= intel_crtc
->plane
;
3983 intel_crtc_wait_for_pending_flips(crtc
);
3985 if (dev_priv
->fbc
.plane
== plane
)
3986 intel_disable_fbc(dev
);
3988 hsw_disable_ips(intel_crtc
);
3990 intel_crtc_dpms_overlay(intel_crtc
, false);
3991 intel_crtc_update_cursor(crtc
, false);
3992 intel_disable_planes(crtc
);
3993 intel_disable_primary_hw_plane(crtc
->primary
, crtc
);
3996 * FIXME: Once we grow proper nuclear flip support out of this we need
3997 * to compute the mask of flip planes precisely. For the time being
3998 * consider this a flip to a NULL plane.
4000 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_ALL_MASK(pipe
));
4002 drm_vblank_off(dev
, pipe
);
4005 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
4007 struct drm_device
*dev
= crtc
->dev
;
4008 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4009 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4010 struct intel_encoder
*encoder
;
4011 int pipe
= intel_crtc
->pipe
;
4013 WARN_ON(!crtc
->enabled
);
4015 if (intel_crtc
->active
)
4018 if (intel_crtc
->config
.has_pch_encoder
)
4019 intel_prepare_shared_dpll(intel_crtc
);
4021 if (intel_crtc
->config
.has_dp_encoder
)
4022 intel_dp_set_m_n(intel_crtc
);
4024 intel_set_pipe_timings(intel_crtc
);
4026 if (intel_crtc
->config
.has_pch_encoder
) {
4027 intel_cpu_transcoder_set_m_n(intel_crtc
,
4028 &intel_crtc
->config
.fdi_m_n
, NULL
);
4031 ironlake_set_pipeconf(crtc
);
4033 intel_crtc
->active
= true;
4035 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
4036 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, true);
4038 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4039 if (encoder
->pre_enable
)
4040 encoder
->pre_enable(encoder
);
4042 if (intel_crtc
->config
.has_pch_encoder
) {
4043 /* Note: FDI PLL enabling _must_ be done before we enable the
4044 * cpu pipes, hence this is separate from all the other fdi/pch
4046 ironlake_fdi_pll_enable(intel_crtc
);
4048 assert_fdi_tx_disabled(dev_priv
, pipe
);
4049 assert_fdi_rx_disabled(dev_priv
, pipe
);
4052 ironlake_pfit_enable(intel_crtc
);
4055 * On ILK+ LUT must be loaded before the pipe is running but with
4058 intel_crtc_load_lut(crtc
);
4060 intel_update_watermarks(crtc
);
4061 intel_enable_pipe(intel_crtc
);
4063 if (intel_crtc
->config
.has_pch_encoder
)
4064 ironlake_pch_enable(crtc
);
4066 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4067 encoder
->enable(encoder
);
4069 if (HAS_PCH_CPT(dev
))
4070 cpt_verify_modeset(dev
, intel_crtc
->pipe
);
4072 intel_crtc_enable_planes(crtc
);
4075 /* IPS only exists on ULT machines and is tied to pipe A. */
4076 static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc
)
4078 return HAS_IPS(crtc
->base
.dev
) && crtc
->pipe
== PIPE_A
;
4082 * This implements the workaround described in the "notes" section of the mode
4083 * set sequence documentation. When going from no pipes or single pipe to
4084 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4085 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4087 static void haswell_mode_set_planes_workaround(struct intel_crtc
*crtc
)
4089 struct drm_device
*dev
= crtc
->base
.dev
;
4090 struct intel_crtc
*crtc_it
, *other_active_crtc
= NULL
;
4092 /* We want to get the other_active_crtc only if there's only 1 other
4094 for_each_intel_crtc(dev
, crtc_it
) {
4095 if (!crtc_it
->active
|| crtc_it
== crtc
)
4098 if (other_active_crtc
)
4101 other_active_crtc
= crtc_it
;
4103 if (!other_active_crtc
)
4106 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
4107 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
4110 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
4112 struct drm_device
*dev
= crtc
->dev
;
4113 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4114 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4115 struct intel_encoder
*encoder
;
4116 int pipe
= intel_crtc
->pipe
;
4118 WARN_ON(!crtc
->enabled
);
4120 if (intel_crtc
->active
)
4123 if (intel_crtc_to_shared_dpll(intel_crtc
))
4124 intel_enable_shared_dpll(intel_crtc
);
4126 if (intel_crtc
->config
.has_dp_encoder
)
4127 intel_dp_set_m_n(intel_crtc
);
4129 intel_set_pipe_timings(intel_crtc
);
4131 if (intel_crtc
->config
.has_pch_encoder
) {
4132 intel_cpu_transcoder_set_m_n(intel_crtc
,
4133 &intel_crtc
->config
.fdi_m_n
, NULL
);
4136 haswell_set_pipeconf(crtc
);
4138 intel_set_pipe_csc(crtc
);
4140 intel_crtc
->active
= true;
4142 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
4143 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4144 if (encoder
->pre_enable
)
4145 encoder
->pre_enable(encoder
);
4147 if (intel_crtc
->config
.has_pch_encoder
) {
4148 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, true);
4149 dev_priv
->display
.fdi_link_train(crtc
);
4152 intel_ddi_enable_pipe_clock(intel_crtc
);
4154 ironlake_pfit_enable(intel_crtc
);
4157 * On ILK+ LUT must be loaded before the pipe is running but with
4160 intel_crtc_load_lut(crtc
);
4162 intel_ddi_set_pipe_settings(crtc
);
4163 intel_ddi_enable_transcoder_func(crtc
);
4165 intel_update_watermarks(crtc
);
4166 intel_enable_pipe(intel_crtc
);
4168 if (intel_crtc
->config
.has_pch_encoder
)
4169 lpt_pch_enable(crtc
);
4171 if (intel_crtc
->config
.dp_encoder_is_mst
)
4172 intel_ddi_set_vc_payload_alloc(crtc
, true);
4174 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4175 encoder
->enable(encoder
);
4176 intel_opregion_notify_encoder(encoder
, true);
4179 /* If we change the relative order between pipe/planes enabling, we need
4180 * to change the workaround. */
4181 haswell_mode_set_planes_workaround(intel_crtc
);
4182 intel_crtc_enable_planes(crtc
);
4185 static void ironlake_pfit_disable(struct intel_crtc
*crtc
)
4187 struct drm_device
*dev
= crtc
->base
.dev
;
4188 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4189 int pipe
= crtc
->pipe
;
4191 /* To avoid upsetting the power well on haswell only disable the pfit if
4192 * it's in use. The hw state code will make sure we get this right. */
4193 if (crtc
->config
.pch_pfit
.enabled
) {
4194 I915_WRITE(PF_CTL(pipe
), 0);
4195 I915_WRITE(PF_WIN_POS(pipe
), 0);
4196 I915_WRITE(PF_WIN_SZ(pipe
), 0);
4200 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
4202 struct drm_device
*dev
= crtc
->dev
;
4203 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4204 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4205 struct intel_encoder
*encoder
;
4206 int pipe
= intel_crtc
->pipe
;
4209 if (!intel_crtc
->active
)
4212 intel_crtc_disable_planes(crtc
);
4214 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4215 encoder
->disable(encoder
);
4217 if (intel_crtc
->config
.has_pch_encoder
)
4218 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, false);
4220 intel_disable_pipe(intel_crtc
);
4222 if (intel_crtc
->config
.dp_encoder_is_mst
)
4223 intel_ddi_set_vc_payload_alloc(crtc
, false);
4225 ironlake_pfit_disable(intel_crtc
);
4227 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4228 if (encoder
->post_disable
)
4229 encoder
->post_disable(encoder
);
4231 if (intel_crtc
->config
.has_pch_encoder
) {
4232 ironlake_fdi_disable(crtc
);
4234 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
4235 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, true);
4237 if (HAS_PCH_CPT(dev
)) {
4238 /* disable TRANS_DP_CTL */
4239 reg
= TRANS_DP_CTL(pipe
);
4240 temp
= I915_READ(reg
);
4241 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
|
4242 TRANS_DP_PORT_SEL_MASK
);
4243 temp
|= TRANS_DP_PORT_SEL_NONE
;
4244 I915_WRITE(reg
, temp
);
4246 /* disable DPLL_SEL */
4247 temp
= I915_READ(PCH_DPLL_SEL
);
4248 temp
&= ~(TRANS_DPLL_ENABLE(pipe
) | TRANS_DPLLB_SEL(pipe
));
4249 I915_WRITE(PCH_DPLL_SEL
, temp
);
4252 /* disable PCH DPLL */
4253 intel_disable_shared_dpll(intel_crtc
);
4255 ironlake_fdi_pll_disable(intel_crtc
);
4258 intel_crtc
->active
= false;
4259 intel_update_watermarks(crtc
);
4261 mutex_lock(&dev
->struct_mutex
);
4262 intel_update_fbc(dev
);
4263 mutex_unlock(&dev
->struct_mutex
);
4266 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
4268 struct drm_device
*dev
= crtc
->dev
;
4269 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4270 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4271 struct intel_encoder
*encoder
;
4272 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
4274 if (!intel_crtc
->active
)
4277 intel_crtc_disable_planes(crtc
);
4279 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4280 intel_opregion_notify_encoder(encoder
, false);
4281 encoder
->disable(encoder
);
4284 if (intel_crtc
->config
.has_pch_encoder
)
4285 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, false);
4286 intel_disable_pipe(intel_crtc
);
4288 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
4290 ironlake_pfit_disable(intel_crtc
);
4292 intel_ddi_disable_pipe_clock(intel_crtc
);
4294 if (intel_crtc
->config
.has_pch_encoder
) {
4295 lpt_disable_pch_transcoder(dev_priv
);
4296 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, true);
4297 intel_ddi_fdi_disable(crtc
);
4300 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4301 if (encoder
->post_disable
)
4302 encoder
->post_disable(encoder
);
4304 intel_crtc
->active
= false;
4305 intel_update_watermarks(crtc
);
4307 mutex_lock(&dev
->struct_mutex
);
4308 intel_update_fbc(dev
);
4309 mutex_unlock(&dev
->struct_mutex
);
4311 if (intel_crtc_to_shared_dpll(intel_crtc
))
4312 intel_disable_shared_dpll(intel_crtc
);
4315 static void ironlake_crtc_off(struct drm_crtc
*crtc
)
4317 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4318 intel_put_shared_dpll(intel_crtc
);
4322 static void i9xx_pfit_enable(struct intel_crtc
*crtc
)
4324 struct drm_device
*dev
= crtc
->base
.dev
;
4325 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4326 struct intel_crtc_config
*pipe_config
= &crtc
->config
;
4328 if (!crtc
->config
.gmch_pfit
.control
)
4332 * The panel fitter should only be adjusted whilst the pipe is disabled,
4333 * according to register description and PRM.
4335 WARN_ON(I915_READ(PFIT_CONTROL
) & PFIT_ENABLE
);
4336 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
4338 I915_WRITE(PFIT_PGM_RATIOS
, pipe_config
->gmch_pfit
.pgm_ratios
);
4339 I915_WRITE(PFIT_CONTROL
, pipe_config
->gmch_pfit
.control
);
4341 /* Border color in case we don't scale up to the full screen. Black by
4342 * default, change to something else for debugging. */
4343 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
4346 static enum intel_display_power_domain
port_to_power_domain(enum port port
)
4350 return POWER_DOMAIN_PORT_DDI_A_4_LANES
;
4352 return POWER_DOMAIN_PORT_DDI_B_4_LANES
;
4354 return POWER_DOMAIN_PORT_DDI_C_4_LANES
;
4356 return POWER_DOMAIN_PORT_DDI_D_4_LANES
;
4359 return POWER_DOMAIN_PORT_OTHER
;
4363 #define for_each_power_domain(domain, mask) \
4364 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4365 if ((1 << (domain)) & (mask))
4367 enum intel_display_power_domain
4368 intel_display_port_power_domain(struct intel_encoder
*intel_encoder
)
4370 struct drm_device
*dev
= intel_encoder
->base
.dev
;
4371 struct intel_digital_port
*intel_dig_port
;
4373 switch (intel_encoder
->type
) {
4374 case INTEL_OUTPUT_UNKNOWN
:
4375 /* Only DDI platforms should ever use this output type */
4376 WARN_ON_ONCE(!HAS_DDI(dev
));
4377 case INTEL_OUTPUT_DISPLAYPORT
:
4378 case INTEL_OUTPUT_HDMI
:
4379 case INTEL_OUTPUT_EDP
:
4380 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
4381 return port_to_power_domain(intel_dig_port
->port
);
4382 case INTEL_OUTPUT_DP_MST
:
4383 intel_dig_port
= enc_to_mst(&intel_encoder
->base
)->primary
;
4384 return port_to_power_domain(intel_dig_port
->port
);
4385 case INTEL_OUTPUT_ANALOG
:
4386 return POWER_DOMAIN_PORT_CRT
;
4387 case INTEL_OUTPUT_DSI
:
4388 return POWER_DOMAIN_PORT_DSI
;
4390 return POWER_DOMAIN_PORT_OTHER
;
4394 static unsigned long get_crtc_power_domains(struct drm_crtc
*crtc
)
4396 struct drm_device
*dev
= crtc
->dev
;
4397 struct intel_encoder
*intel_encoder
;
4398 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4399 enum pipe pipe
= intel_crtc
->pipe
;
4401 enum transcoder transcoder
;
4403 transcoder
= intel_pipe_to_cpu_transcoder(dev
->dev_private
, pipe
);
4405 mask
= BIT(POWER_DOMAIN_PIPE(pipe
));
4406 mask
|= BIT(POWER_DOMAIN_TRANSCODER(transcoder
));
4407 if (intel_crtc
->config
.pch_pfit
.enabled
||
4408 intel_crtc
->config
.pch_pfit
.force_thru
)
4409 mask
|= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe
));
4411 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
4412 mask
|= BIT(intel_display_port_power_domain(intel_encoder
));
4417 void intel_display_set_init_power(struct drm_i915_private
*dev_priv
,
4420 if (dev_priv
->power_domains
.init_power_on
== enable
)
4424 intel_display_power_get(dev_priv
, POWER_DOMAIN_INIT
);
4426 intel_display_power_put(dev_priv
, POWER_DOMAIN_INIT
);
4428 dev_priv
->power_domains
.init_power_on
= enable
;
4431 static void modeset_update_crtc_power_domains(struct drm_device
*dev
)
4433 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4434 unsigned long pipe_domains
[I915_MAX_PIPES
] = { 0, };
4435 struct intel_crtc
*crtc
;
4438 * First get all needed power domains, then put all unneeded, to avoid
4439 * any unnecessary toggling of the power wells.
4441 for_each_intel_crtc(dev
, crtc
) {
4442 enum intel_display_power_domain domain
;
4444 if (!crtc
->base
.enabled
)
4447 pipe_domains
[crtc
->pipe
] = get_crtc_power_domains(&crtc
->base
);
4449 for_each_power_domain(domain
, pipe_domains
[crtc
->pipe
])
4450 intel_display_power_get(dev_priv
, domain
);
4453 for_each_intel_crtc(dev
, crtc
) {
4454 enum intel_display_power_domain domain
;
4456 for_each_power_domain(domain
, crtc
->enabled_power_domains
)
4457 intel_display_power_put(dev_priv
, domain
);
4459 crtc
->enabled_power_domains
= pipe_domains
[crtc
->pipe
];
4462 intel_display_set_init_power(dev_priv
, false);
4465 /* returns HPLL frequency in kHz */
4466 static int valleyview_get_vco(struct drm_i915_private
*dev_priv
)
4468 int hpll_freq
, vco_freq
[] = { 800, 1600, 2000, 2400 };
4470 /* Obtain SKU information */
4471 mutex_lock(&dev_priv
->dpio_lock
);
4472 hpll_freq
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
) &
4473 CCK_FUSE_HPLL_FREQ_MASK
;
4474 mutex_unlock(&dev_priv
->dpio_lock
);
4476 return vco_freq
[hpll_freq
] * 1000;
4479 static void vlv_update_cdclk(struct drm_device
*dev
)
4481 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4483 dev_priv
->vlv_cdclk_freq
= dev_priv
->display
.get_display_clock_speed(dev
);
4484 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz",
4485 dev_priv
->vlv_cdclk_freq
);
4488 * Program the gmbus_freq based on the cdclk frequency.
4489 * BSpec erroneously claims we should aim for 4MHz, but
4490 * in fact 1MHz is the correct frequency.
4492 I915_WRITE(GMBUSFREQ_VLV
, dev_priv
->vlv_cdclk_freq
);
4495 /* Adjust CDclk dividers to allow high res or save power if possible */
4496 static void valleyview_set_cdclk(struct drm_device
*dev
, int cdclk
)
4498 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4501 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
) != dev_priv
->vlv_cdclk_freq
);
4503 if (cdclk
>= 320000) /* jump to highest voltage for 400MHz too */
4505 else if (cdclk
== 266667)
4510 mutex_lock(&dev_priv
->rps
.hw_lock
);
4511 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
4512 val
&= ~DSPFREQGUAR_MASK
;
4513 val
|= (cmd
<< DSPFREQGUAR_SHIFT
);
4514 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
4515 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
4516 DSPFREQSTAT_MASK
) == (cmd
<< DSPFREQSTAT_SHIFT
),
4518 DRM_ERROR("timed out waiting for CDclk change\n");
4520 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4522 if (cdclk
== 400000) {
4525 vco
= valleyview_get_vco(dev_priv
);
4526 divider
= DIV_ROUND_CLOSEST(vco
<< 1, cdclk
) - 1;
4528 mutex_lock(&dev_priv
->dpio_lock
);
4529 /* adjust cdclk divider */
4530 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
4531 val
&= ~DISPLAY_FREQUENCY_VALUES
;
4533 vlv_cck_write(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
, val
);
4535 if (wait_for((vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
) &
4536 DISPLAY_FREQUENCY_STATUS
) == (divider
<< DISPLAY_FREQUENCY_STATUS_SHIFT
),
4538 DRM_ERROR("timed out waiting for CDclk change\n");
4539 mutex_unlock(&dev_priv
->dpio_lock
);
4542 mutex_lock(&dev_priv
->dpio_lock
);
4543 /* adjust self-refresh exit latency value */
4544 val
= vlv_bunit_read(dev_priv
, BUNIT_REG_BISOC
);
4548 * For high bandwidth configs, we set a higher latency in the bunit
4549 * so that the core display fetch happens in time to avoid underruns.
4551 if (cdclk
== 400000)
4552 val
|= 4500 / 250; /* 4.5 usec */
4554 val
|= 3000 / 250; /* 3.0 usec */
4555 vlv_bunit_write(dev_priv
, BUNIT_REG_BISOC
, val
);
4556 mutex_unlock(&dev_priv
->dpio_lock
);
4558 vlv_update_cdclk(dev
);
4561 static void cherryview_set_cdclk(struct drm_device
*dev
, int cdclk
)
4563 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4566 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
) != dev_priv
->vlv_cdclk_freq
);
4587 mutex_lock(&dev_priv
->rps
.hw_lock
);
4588 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
4589 val
&= ~DSPFREQGUAR_MASK_CHV
;
4590 val
|= (cmd
<< DSPFREQGUAR_SHIFT_CHV
);
4591 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
4592 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
4593 DSPFREQSTAT_MASK_CHV
) == (cmd
<< DSPFREQSTAT_SHIFT_CHV
),
4595 DRM_ERROR("timed out waiting for CDclk change\n");
4597 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4599 vlv_update_cdclk(dev
);
4602 static int valleyview_calc_cdclk(struct drm_i915_private
*dev_priv
,
4605 int vco
= valleyview_get_vco(dev_priv
);
4606 int freq_320
= (vco
<< 1) % 320000 != 0 ? 333333 : 320000;
4608 /* FIXME: Punit isn't quite ready yet */
4609 if (IS_CHERRYVIEW(dev_priv
->dev
))
4613 * Really only a few cases to deal with, as only 4 CDclks are supported:
4616 * 320/333MHz (depends on HPLL freq)
4618 * So we check to see whether we're above 90% of the lower bin and
4621 * We seem to get an unstable or solid color picture at 200MHz.
4622 * Not sure what's wrong. For now use 200MHz only when all pipes
4625 if (max_pixclk
> freq_320
*9/10)
4627 else if (max_pixclk
> 266667*9/10)
4629 else if (max_pixclk
> 0)
4635 /* compute the max pixel clock for new configuration */
4636 static int intel_mode_max_pixclk(struct drm_i915_private
*dev_priv
)
4638 struct drm_device
*dev
= dev_priv
->dev
;
4639 struct intel_crtc
*intel_crtc
;
4642 for_each_intel_crtc(dev
, intel_crtc
) {
4643 if (intel_crtc
->new_enabled
)
4644 max_pixclk
= max(max_pixclk
,
4645 intel_crtc
->new_config
->adjusted_mode
.crtc_clock
);
4651 static void valleyview_modeset_global_pipes(struct drm_device
*dev
,
4652 unsigned *prepare_pipes
)
4654 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4655 struct intel_crtc
*intel_crtc
;
4656 int max_pixclk
= intel_mode_max_pixclk(dev_priv
);
4658 if (valleyview_calc_cdclk(dev_priv
, max_pixclk
) ==
4659 dev_priv
->vlv_cdclk_freq
)
4662 /* disable/enable all currently active pipes while we change cdclk */
4663 for_each_intel_crtc(dev
, intel_crtc
)
4664 if (intel_crtc
->base
.enabled
)
4665 *prepare_pipes
|= (1 << intel_crtc
->pipe
);
4668 static void valleyview_modeset_global_resources(struct drm_device
*dev
)
4670 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4671 int max_pixclk
= intel_mode_max_pixclk(dev_priv
);
4672 int req_cdclk
= valleyview_calc_cdclk(dev_priv
, max_pixclk
);
4674 if (req_cdclk
!= dev_priv
->vlv_cdclk_freq
) {
4675 if (IS_CHERRYVIEW(dev
))
4676 cherryview_set_cdclk(dev
, req_cdclk
);
4678 valleyview_set_cdclk(dev
, req_cdclk
);
4681 modeset_update_crtc_power_domains(dev
);
4684 static void valleyview_crtc_enable(struct drm_crtc
*crtc
)
4686 struct drm_device
*dev
= crtc
->dev
;
4687 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4688 struct intel_encoder
*encoder
;
4689 int pipe
= intel_crtc
->pipe
;
4692 WARN_ON(!crtc
->enabled
);
4694 if (intel_crtc
->active
)
4697 is_dsi
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
);
4700 if (IS_CHERRYVIEW(dev
))
4701 chv_prepare_pll(intel_crtc
);
4703 vlv_prepare_pll(intel_crtc
);
4706 if (intel_crtc
->config
.has_dp_encoder
)
4707 intel_dp_set_m_n(intel_crtc
);
4709 intel_set_pipe_timings(intel_crtc
);
4711 i9xx_set_pipeconf(intel_crtc
);
4713 intel_crtc
->active
= true;
4715 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
4717 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4718 if (encoder
->pre_pll_enable
)
4719 encoder
->pre_pll_enable(encoder
);
4722 if (IS_CHERRYVIEW(dev
))
4723 chv_enable_pll(intel_crtc
);
4725 vlv_enable_pll(intel_crtc
);
4728 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4729 if (encoder
->pre_enable
)
4730 encoder
->pre_enable(encoder
);
4732 i9xx_pfit_enable(intel_crtc
);
4734 intel_crtc_load_lut(crtc
);
4736 intel_update_watermarks(crtc
);
4737 intel_enable_pipe(intel_crtc
);
4739 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4740 encoder
->enable(encoder
);
4742 intel_crtc_enable_planes(crtc
);
4744 /* Underruns don't raise interrupts, so check manually. */
4745 i9xx_check_fifo_underruns(dev
);
4748 static void i9xx_set_pll_dividers(struct intel_crtc
*crtc
)
4750 struct drm_device
*dev
= crtc
->base
.dev
;
4751 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4753 I915_WRITE(FP0(crtc
->pipe
), crtc
->config
.dpll_hw_state
.fp0
);
4754 I915_WRITE(FP1(crtc
->pipe
), crtc
->config
.dpll_hw_state
.fp1
);
4757 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
4759 struct drm_device
*dev
= crtc
->dev
;
4760 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4761 struct intel_encoder
*encoder
;
4762 int pipe
= intel_crtc
->pipe
;
4764 WARN_ON(!crtc
->enabled
);
4766 if (intel_crtc
->active
)
4769 i9xx_set_pll_dividers(intel_crtc
);
4771 if (intel_crtc
->config
.has_dp_encoder
)
4772 intel_dp_set_m_n(intel_crtc
);
4774 intel_set_pipe_timings(intel_crtc
);
4776 i9xx_set_pipeconf(intel_crtc
);
4778 intel_crtc
->active
= true;
4781 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
4783 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4784 if (encoder
->pre_enable
)
4785 encoder
->pre_enable(encoder
);
4787 i9xx_enable_pll(intel_crtc
);
4789 i9xx_pfit_enable(intel_crtc
);
4791 intel_crtc_load_lut(crtc
);
4793 intel_update_watermarks(crtc
);
4794 intel_enable_pipe(intel_crtc
);
4796 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4797 encoder
->enable(encoder
);
4799 intel_crtc_enable_planes(crtc
);
4802 * Gen2 reports pipe underruns whenever all planes are disabled.
4803 * So don't enable underrun reporting before at least some planes
4805 * FIXME: Need to fix the logic to work when we turn off all planes
4806 * but leave the pipe running.
4809 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
4811 /* Underruns don't raise interrupts, so check manually. */
4812 i9xx_check_fifo_underruns(dev
);
4815 static void i9xx_pfit_disable(struct intel_crtc
*crtc
)
4817 struct drm_device
*dev
= crtc
->base
.dev
;
4818 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4820 if (!crtc
->config
.gmch_pfit
.control
)
4823 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
4825 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4826 I915_READ(PFIT_CONTROL
));
4827 I915_WRITE(PFIT_CONTROL
, 0);
4830 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
4832 struct drm_device
*dev
= crtc
->dev
;
4833 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4834 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4835 struct intel_encoder
*encoder
;
4836 int pipe
= intel_crtc
->pipe
;
4838 if (!intel_crtc
->active
)
4842 * Gen2 reports pipe underruns whenever all planes are disabled.
4843 * So diasble underrun reporting before all the planes get disabled.
4844 * FIXME: Need to fix the logic to work when we turn off all planes
4845 * but leave the pipe running.
4848 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, false);
4851 * Vblank time updates from the shadow to live plane control register
4852 * are blocked if the memory self-refresh mode is active at that
4853 * moment. So to make sure the plane gets truly disabled, disable
4854 * first the self-refresh mode. The self-refresh enable bit in turn
4855 * will be checked/applied by the HW only at the next frame start
4856 * event which is after the vblank start event, so we need to have a
4857 * wait-for-vblank between disabling the plane and the pipe.
4859 intel_set_memory_cxsr(dev_priv
, false);
4860 intel_crtc_disable_planes(crtc
);
4862 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4863 encoder
->disable(encoder
);
4866 * On gen2 planes are double buffered but the pipe isn't, so we must
4867 * wait for planes to fully turn off before disabling the pipe.
4868 * We also need to wait on all gmch platforms because of the
4869 * self-refresh mode constraint explained above.
4871 intel_wait_for_vblank(dev
, pipe
);
4873 intel_disable_pipe(intel_crtc
);
4875 i9xx_pfit_disable(intel_crtc
);
4877 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4878 if (encoder
->post_disable
)
4879 encoder
->post_disable(encoder
);
4881 if (!intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
)) {
4882 if (IS_CHERRYVIEW(dev
))
4883 chv_disable_pll(dev_priv
, pipe
);
4884 else if (IS_VALLEYVIEW(dev
))
4885 vlv_disable_pll(dev_priv
, pipe
);
4887 i9xx_disable_pll(dev_priv
, pipe
);
4891 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, false);
4893 intel_crtc
->active
= false;
4894 intel_update_watermarks(crtc
);
4896 mutex_lock(&dev
->struct_mutex
);
4897 intel_update_fbc(dev
);
4898 mutex_unlock(&dev
->struct_mutex
);
4901 static void i9xx_crtc_off(struct drm_crtc
*crtc
)
4905 static void intel_crtc_update_sarea(struct drm_crtc
*crtc
,
4908 struct drm_device
*dev
= crtc
->dev
;
4909 struct drm_i915_master_private
*master_priv
;
4910 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4911 int pipe
= intel_crtc
->pipe
;
4913 if (!dev
->primary
->master
)
4916 master_priv
= dev
->primary
->master
->driver_priv
;
4917 if (!master_priv
->sarea_priv
)
4922 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
4923 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
4926 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
4927 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
4930 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe
));
4935 /* Master function to enable/disable CRTC and corresponding power wells */
4936 void intel_crtc_control(struct drm_crtc
*crtc
, bool enable
)
4938 struct drm_device
*dev
= crtc
->dev
;
4939 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4940 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4941 enum intel_display_power_domain domain
;
4942 unsigned long domains
;
4945 if (!intel_crtc
->active
) {
4946 domains
= get_crtc_power_domains(crtc
);
4947 for_each_power_domain(domain
, domains
)
4948 intel_display_power_get(dev_priv
, domain
);
4949 intel_crtc
->enabled_power_domains
= domains
;
4951 dev_priv
->display
.crtc_enable(crtc
);
4954 if (intel_crtc
->active
) {
4955 dev_priv
->display
.crtc_disable(crtc
);
4957 domains
= intel_crtc
->enabled_power_domains
;
4958 for_each_power_domain(domain
, domains
)
4959 intel_display_power_put(dev_priv
, domain
);
4960 intel_crtc
->enabled_power_domains
= 0;
4966 * Sets the power management mode of the pipe and plane.
4968 void intel_crtc_update_dpms(struct drm_crtc
*crtc
)
4970 struct drm_device
*dev
= crtc
->dev
;
4971 struct intel_encoder
*intel_encoder
;
4972 bool enable
= false;
4974 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
4975 enable
|= intel_encoder
->connectors_active
;
4977 intel_crtc_control(crtc
, enable
);
4979 intel_crtc_update_sarea(crtc
, enable
);
4982 static void intel_crtc_disable(struct drm_crtc
*crtc
)
4984 struct drm_device
*dev
= crtc
->dev
;
4985 struct drm_connector
*connector
;
4986 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4987 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(crtc
->primary
->fb
);
4988 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
4990 /* crtc should still be enabled when we disable it. */
4991 WARN_ON(!crtc
->enabled
);
4993 dev_priv
->display
.crtc_disable(crtc
);
4994 intel_crtc_update_sarea(crtc
, false);
4995 dev_priv
->display
.off(crtc
);
4997 if (crtc
->primary
->fb
) {
4998 mutex_lock(&dev
->struct_mutex
);
4999 intel_unpin_fb_obj(old_obj
);
5000 i915_gem_track_fb(old_obj
, NULL
,
5001 INTEL_FRONTBUFFER_PRIMARY(pipe
));
5002 mutex_unlock(&dev
->struct_mutex
);
5003 crtc
->primary
->fb
= NULL
;
5006 /* Update computed state. */
5007 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
5008 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
5011 if (connector
->encoder
->crtc
!= crtc
)
5014 connector
->dpms
= DRM_MODE_DPMS_OFF
;
5015 to_intel_encoder(connector
->encoder
)->connectors_active
= false;
5019 void intel_encoder_destroy(struct drm_encoder
*encoder
)
5021 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
5023 drm_encoder_cleanup(encoder
);
5024 kfree(intel_encoder
);
5027 /* Simple dpms helper for encoders with just one connector, no cloning and only
5028 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5029 * state of the entire output pipe. */
5030 static void intel_encoder_dpms(struct intel_encoder
*encoder
, int mode
)
5032 if (mode
== DRM_MODE_DPMS_ON
) {
5033 encoder
->connectors_active
= true;
5035 intel_crtc_update_dpms(encoder
->base
.crtc
);
5037 encoder
->connectors_active
= false;
5039 intel_crtc_update_dpms(encoder
->base
.crtc
);
5043 /* Cross check the actual hw state with our own modeset state tracking (and it's
5044 * internal consistency). */
5045 static void intel_connector_check_state(struct intel_connector
*connector
)
5047 if (connector
->get_hw_state(connector
)) {
5048 struct intel_encoder
*encoder
= connector
->encoder
;
5049 struct drm_crtc
*crtc
;
5050 bool encoder_enabled
;
5053 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5054 connector
->base
.base
.id
,
5055 connector
->base
.name
);
5057 /* there is no real hw state for MST connectors */
5058 if (connector
->mst_port
)
5061 WARN(connector
->base
.dpms
== DRM_MODE_DPMS_OFF
,
5062 "wrong connector dpms state\n");
5063 WARN(connector
->base
.encoder
!= &encoder
->base
,
5064 "active connector not linked to encoder\n");
5067 WARN(!encoder
->connectors_active
,
5068 "encoder->connectors_active not set\n");
5070 encoder_enabled
= encoder
->get_hw_state(encoder
, &pipe
);
5071 WARN(!encoder_enabled
, "encoder not enabled\n");
5072 if (WARN_ON(!encoder
->base
.crtc
))
5075 crtc
= encoder
->base
.crtc
;
5077 WARN(!crtc
->enabled
, "crtc not enabled\n");
5078 WARN(!to_intel_crtc(crtc
)->active
, "crtc not active\n");
5079 WARN(pipe
!= to_intel_crtc(crtc
)->pipe
,
5080 "encoder active on the wrong pipe\n");
5085 /* Even simpler default implementation, if there's really no special case to
5087 void intel_connector_dpms(struct drm_connector
*connector
, int mode
)
5089 /* All the simple cases only support two dpms states. */
5090 if (mode
!= DRM_MODE_DPMS_ON
)
5091 mode
= DRM_MODE_DPMS_OFF
;
5093 if (mode
== connector
->dpms
)
5096 connector
->dpms
= mode
;
5098 /* Only need to change hw state when actually enabled */
5099 if (connector
->encoder
)
5100 intel_encoder_dpms(to_intel_encoder(connector
->encoder
), mode
);
5102 intel_modeset_check_state(connector
->dev
);
5105 /* Simple connector->get_hw_state implementation for encoders that support only
5106 * one connector and no cloning and hence the encoder state determines the state
5107 * of the connector. */
5108 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
5111 struct intel_encoder
*encoder
= connector
->encoder
;
5113 return encoder
->get_hw_state(encoder
, &pipe
);
5116 static bool ironlake_check_fdi_lanes(struct drm_device
*dev
, enum pipe pipe
,
5117 struct intel_crtc_config
*pipe_config
)
5119 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5120 struct intel_crtc
*pipe_B_crtc
=
5121 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
5123 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5124 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5125 if (pipe_config
->fdi_lanes
> 4) {
5126 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5127 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5131 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
5132 if (pipe_config
->fdi_lanes
> 2) {
5133 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5134 pipe_config
->fdi_lanes
);
5141 if (INTEL_INFO(dev
)->num_pipes
== 2)
5144 /* Ivybridge 3 pipe is really complicated */
5149 if (dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]->enabled
&&
5150 pipe_config
->fdi_lanes
> 2) {
5151 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5152 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5157 if (!pipe_has_enabled_pch(pipe_B_crtc
) ||
5158 pipe_B_crtc
->config
.fdi_lanes
<= 2) {
5159 if (pipe_config
->fdi_lanes
> 2) {
5160 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5161 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5165 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5175 static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc
,
5176 struct intel_crtc_config
*pipe_config
)
5178 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5179 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
5180 int lane
, link_bw
, fdi_dotclock
;
5181 bool setup_ok
, needs_recompute
= false;
5184 /* FDI is a binary signal running at ~2.7GHz, encoding
5185 * each output octet as 10 bits. The actual frequency
5186 * is stored as a divider into a 100MHz clock, and the
5187 * mode pixel clock is stored in units of 1KHz.
5188 * Hence the bw of each lane in terms of the mode signal
5191 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
5193 fdi_dotclock
= adjusted_mode
->crtc_clock
;
5195 lane
= ironlake_get_lanes_required(fdi_dotclock
, link_bw
,
5196 pipe_config
->pipe_bpp
);
5198 pipe_config
->fdi_lanes
= lane
;
5200 intel_link_compute_m_n(pipe_config
->pipe_bpp
, lane
, fdi_dotclock
,
5201 link_bw
, &pipe_config
->fdi_m_n
);
5203 setup_ok
= ironlake_check_fdi_lanes(intel_crtc
->base
.dev
,
5204 intel_crtc
->pipe
, pipe_config
);
5205 if (!setup_ok
&& pipe_config
->pipe_bpp
> 6*3) {
5206 pipe_config
->pipe_bpp
-= 2*3;
5207 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5208 pipe_config
->pipe_bpp
);
5209 needs_recompute
= true;
5210 pipe_config
->bw_constrained
= true;
5215 if (needs_recompute
)
5218 return setup_ok
? 0 : -EINVAL
;
5221 static void hsw_compute_ips_config(struct intel_crtc
*crtc
,
5222 struct intel_crtc_config
*pipe_config
)
5224 pipe_config
->ips_enabled
= i915
.enable_ips
&&
5225 hsw_crtc_supports_ips(crtc
) &&
5226 pipe_config
->pipe_bpp
<= 24;
5229 static int intel_crtc_compute_config(struct intel_crtc
*crtc
,
5230 struct intel_crtc_config
*pipe_config
)
5232 struct drm_device
*dev
= crtc
->base
.dev
;
5233 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
5235 /* FIXME should check pixel clock limits on all platforms */
5236 if (INTEL_INFO(dev
)->gen
< 4) {
5237 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5239 dev_priv
->display
.get_display_clock_speed(dev
);
5242 * Enable pixel doubling when the dot clock
5243 * is > 90% of the (display) core speed.
5245 * GDG double wide on either pipe,
5246 * otherwise pipe A only.
5248 if ((crtc
->pipe
== PIPE_A
|| IS_I915G(dev
)) &&
5249 adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10) {
5251 pipe_config
->double_wide
= true;
5254 if (adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10)
5259 * Pipe horizontal size must be even in:
5261 * - LVDS dual channel mode
5262 * - Double wide pipe
5264 if ((intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
5265 intel_is_dual_link_lvds(dev
)) || pipe_config
->double_wide
)
5266 pipe_config
->pipe_src_w
&= ~1;
5268 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5269 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5271 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
5272 adjusted_mode
->hsync_start
== adjusted_mode
->hdisplay
)
5275 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) && pipe_config
->pipe_bpp
> 10*3) {
5276 pipe_config
->pipe_bpp
= 10*3; /* 12bpc is gen5+ */
5277 } else if (INTEL_INFO(dev
)->gen
<= 4 && pipe_config
->pipe_bpp
> 8*3) {
5278 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5280 pipe_config
->pipe_bpp
= 8*3;
5284 hsw_compute_ips_config(crtc
, pipe_config
);
5287 * XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the
5288 * old clock survives for now.
5290 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
) || HAS_DDI(dev
))
5291 pipe_config
->shared_dpll
= crtc
->config
.shared_dpll
;
5293 if (pipe_config
->has_pch_encoder
)
5294 return ironlake_fdi_compute_config(crtc
, pipe_config
);
5299 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
5301 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5302 int vco
= valleyview_get_vco(dev_priv
);
5306 /* FIXME: Punit isn't quite ready yet */
5307 if (IS_CHERRYVIEW(dev
))
5310 mutex_lock(&dev_priv
->dpio_lock
);
5311 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
5312 mutex_unlock(&dev_priv
->dpio_lock
);
5314 divider
= val
& DISPLAY_FREQUENCY_VALUES
;
5316 WARN((val
& DISPLAY_FREQUENCY_STATUS
) !=
5317 (divider
<< DISPLAY_FREQUENCY_STATUS_SHIFT
),
5318 "cdclk change in progress\n");
5320 return DIV_ROUND_CLOSEST(vco
<< 1, divider
+ 1);
5323 static int i945_get_display_clock_speed(struct drm_device
*dev
)
5328 static int i915_get_display_clock_speed(struct drm_device
*dev
)
5333 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
5338 static int pnv_get_display_clock_speed(struct drm_device
*dev
)
5342 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
5344 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
5345 case GC_DISPLAY_CLOCK_267_MHZ_PNV
:
5347 case GC_DISPLAY_CLOCK_333_MHZ_PNV
:
5349 case GC_DISPLAY_CLOCK_444_MHZ_PNV
:
5351 case GC_DISPLAY_CLOCK_200_MHZ_PNV
:
5354 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc
);
5355 case GC_DISPLAY_CLOCK_133_MHZ_PNV
:
5357 case GC_DISPLAY_CLOCK_167_MHZ_PNV
:
5362 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
5366 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
5368 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
5371 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
5372 case GC_DISPLAY_CLOCK_333_MHZ
:
5375 case GC_DISPLAY_CLOCK_190_200_MHZ
:
5381 static int i865_get_display_clock_speed(struct drm_device
*dev
)
5386 static int i855_get_display_clock_speed(struct drm_device
*dev
)
5389 /* Assume that the hardware is in the high speed state. This
5390 * should be the default.
5392 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
5393 case GC_CLOCK_133_200
:
5394 case GC_CLOCK_100_200
:
5396 case GC_CLOCK_166_250
:
5398 case GC_CLOCK_100_133
:
5402 /* Shouldn't happen */
5406 static int i830_get_display_clock_speed(struct drm_device
*dev
)
5412 intel_reduce_m_n_ratio(uint32_t *num
, uint32_t *den
)
5414 while (*num
> DATA_LINK_M_N_MASK
||
5415 *den
> DATA_LINK_M_N_MASK
) {
5421 static void compute_m_n(unsigned int m
, unsigned int n
,
5422 uint32_t *ret_m
, uint32_t *ret_n
)
5424 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
5425 *ret_m
= div_u64((uint64_t) m
* *ret_n
, n
);
5426 intel_reduce_m_n_ratio(ret_m
, ret_n
);
5430 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
5431 int pixel_clock
, int link_clock
,
5432 struct intel_link_m_n
*m_n
)
5436 compute_m_n(bits_per_pixel
* pixel_clock
,
5437 link_clock
* nlanes
* 8,
5438 &m_n
->gmch_m
, &m_n
->gmch_n
);
5440 compute_m_n(pixel_clock
, link_clock
,
5441 &m_n
->link_m
, &m_n
->link_n
);
5444 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
5446 if (i915
.panel_use_ssc
>= 0)
5447 return i915
.panel_use_ssc
!= 0;
5448 return dev_priv
->vbt
.lvds_use_ssc
5449 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
5452 static int i9xx_get_refclk(struct drm_crtc
*crtc
, int num_connectors
)
5454 struct drm_device
*dev
= crtc
->dev
;
5455 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5458 if (IS_VALLEYVIEW(dev
)) {
5460 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
5461 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
5462 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
5463 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
5464 } else if (!IS_GEN2(dev
)) {
5473 static uint32_t pnv_dpll_compute_fp(struct dpll
*dpll
)
5475 return (1 << dpll
->n
) << 16 | dpll
->m2
;
5478 static uint32_t i9xx_dpll_compute_fp(struct dpll
*dpll
)
5480 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
5483 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
5484 intel_clock_t
*reduced_clock
)
5486 struct drm_device
*dev
= crtc
->base
.dev
;
5489 if (IS_PINEVIEW(dev
)) {
5490 fp
= pnv_dpll_compute_fp(&crtc
->config
.dpll
);
5492 fp2
= pnv_dpll_compute_fp(reduced_clock
);
5494 fp
= i9xx_dpll_compute_fp(&crtc
->config
.dpll
);
5496 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
5499 crtc
->config
.dpll_hw_state
.fp0
= fp
;
5501 crtc
->lowfreq_avail
= false;
5502 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
5503 reduced_clock
&& i915
.powersave
) {
5504 crtc
->config
.dpll_hw_state
.fp1
= fp2
;
5505 crtc
->lowfreq_avail
= true;
5507 crtc
->config
.dpll_hw_state
.fp1
= fp
;
5511 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
, enum pipe
5517 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5518 * and set it to a reasonable value instead.
5520 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
5521 reg_val
&= 0xffffff00;
5522 reg_val
|= 0x00000030;
5523 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
5525 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
5526 reg_val
&= 0x8cffffff;
5527 reg_val
= 0x8c000000;
5528 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
5530 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
5531 reg_val
&= 0xffffff00;
5532 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
5534 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
5535 reg_val
&= 0x00ffffff;
5536 reg_val
|= 0xb0000000;
5537 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
5540 static void intel_pch_transcoder_set_m_n(struct intel_crtc
*crtc
,
5541 struct intel_link_m_n
*m_n
)
5543 struct drm_device
*dev
= crtc
->base
.dev
;
5544 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5545 int pipe
= crtc
->pipe
;
5547 I915_WRITE(PCH_TRANS_DATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5548 I915_WRITE(PCH_TRANS_DATA_N1(pipe
), m_n
->gmch_n
);
5549 I915_WRITE(PCH_TRANS_LINK_M1(pipe
), m_n
->link_m
);
5550 I915_WRITE(PCH_TRANS_LINK_N1(pipe
), m_n
->link_n
);
5553 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
5554 struct intel_link_m_n
*m_n
,
5555 struct intel_link_m_n
*m2_n2
)
5557 struct drm_device
*dev
= crtc
->base
.dev
;
5558 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5559 int pipe
= crtc
->pipe
;
5560 enum transcoder transcoder
= crtc
->config
.cpu_transcoder
;
5562 if (INTEL_INFO(dev
)->gen
>= 5) {
5563 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5564 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
5565 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
5566 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
5567 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5568 * for gen < 8) and if DRRS is supported (to make sure the
5569 * registers are not unnecessarily accessed).
5571 if (m2_n2
&& INTEL_INFO(dev
)->gen
< 8 &&
5572 crtc
->config
.has_drrs
) {
5573 I915_WRITE(PIPE_DATA_M2(transcoder
),
5574 TU_SIZE(m2_n2
->tu
) | m2_n2
->gmch_m
);
5575 I915_WRITE(PIPE_DATA_N2(transcoder
), m2_n2
->gmch_n
);
5576 I915_WRITE(PIPE_LINK_M2(transcoder
), m2_n2
->link_m
);
5577 I915_WRITE(PIPE_LINK_N2(transcoder
), m2_n2
->link_n
);
5580 I915_WRITE(PIPE_DATA_M_G4X(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5581 I915_WRITE(PIPE_DATA_N_G4X(pipe
), m_n
->gmch_n
);
5582 I915_WRITE(PIPE_LINK_M_G4X(pipe
), m_n
->link_m
);
5583 I915_WRITE(PIPE_LINK_N_G4X(pipe
), m_n
->link_n
);
5587 void intel_dp_set_m_n(struct intel_crtc
*crtc
)
5589 if (crtc
->config
.has_pch_encoder
)
5590 intel_pch_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
);
5592 intel_cpu_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
,
5593 &crtc
->config
.dp_m2_n2
);
5596 static void vlv_update_pll(struct intel_crtc
*crtc
)
5601 * Enable DPIO clock input. We should never disable the reference
5602 * clock for pipe B, since VGA hotplug / manual detection depends
5605 dpll
= DPLL_EXT_BUFFER_ENABLE_VLV
| DPLL_REFA_CLK_ENABLE_VLV
|
5606 DPLL_VGA_MODE_DIS
| DPLL_INTEGRATED_CLOCK_VLV
;
5607 /* We should never disable this, set it here for state tracking */
5608 if (crtc
->pipe
== PIPE_B
)
5609 dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
5610 dpll
|= DPLL_VCO_ENABLE
;
5611 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
5613 dpll_md
= (crtc
->config
.pixel_multiplier
- 1)
5614 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
5615 crtc
->config
.dpll_hw_state
.dpll_md
= dpll_md
;
5618 static void vlv_prepare_pll(struct intel_crtc
*crtc
)
5620 struct drm_device
*dev
= crtc
->base
.dev
;
5621 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5622 int pipe
= crtc
->pipe
;
5624 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
5625 u32 coreclk
, reg_val
;
5627 mutex_lock(&dev_priv
->dpio_lock
);
5629 bestn
= crtc
->config
.dpll
.n
;
5630 bestm1
= crtc
->config
.dpll
.m1
;
5631 bestm2
= crtc
->config
.dpll
.m2
;
5632 bestp1
= crtc
->config
.dpll
.p1
;
5633 bestp2
= crtc
->config
.dpll
.p2
;
5635 /* See eDP HDMI DPIO driver vbios notes doc */
5637 /* PLL B needs special handling */
5639 vlv_pllb_recal_opamp(dev_priv
, pipe
);
5641 /* Set up Tx target for periodic Rcomp update */
5642 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9_BCAST
, 0x0100000f);
5644 /* Disable target IRef on PLL */
5645 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW8(pipe
));
5646 reg_val
&= 0x00ffffff;
5647 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW8(pipe
), reg_val
);
5649 /* Disable fast lock */
5650 vlv_dpio_write(dev_priv
, pipe
, VLV_CMN_DW0
, 0x610);
5652 /* Set idtafcrecal before PLL is enabled */
5653 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
5654 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
5655 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
5656 mdiv
|= (1 << DPIO_K_SHIFT
);
5659 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5660 * but we don't support that).
5661 * Note: don't use the DAC post divider as it seems unstable.
5663 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
5664 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
5666 mdiv
|= DPIO_ENABLE_CALIBRATION
;
5667 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
5669 /* Set HBR and RBR LPF coefficients */
5670 if (crtc
->config
.port_clock
== 162000 ||
5671 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_ANALOG
) ||
5672 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
))
5673 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
5676 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
5679 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
) ||
5680 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
)) {
5681 /* Use SSC source */
5683 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5686 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5688 } else { /* HDMI or VGA */
5689 /* Use bend source */
5691 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5694 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5698 coreclk
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW7(pipe
));
5699 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
5700 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
) ||
5701 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
))
5702 coreclk
|= 0x01000000;
5703 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW7(pipe
), coreclk
);
5705 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW11(pipe
), 0x87871000);
5706 mutex_unlock(&dev_priv
->dpio_lock
);
5709 static void chv_update_pll(struct intel_crtc
*crtc
)
5711 crtc
->config
.dpll_hw_state
.dpll
= DPLL_SSC_REF_CLOCK_CHV
|
5712 DPLL_REFA_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
|
5714 if (crtc
->pipe
!= PIPE_A
)
5715 crtc
->config
.dpll_hw_state
.dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
5717 crtc
->config
.dpll_hw_state
.dpll_md
=
5718 (crtc
->config
.pixel_multiplier
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
5721 static void chv_prepare_pll(struct intel_crtc
*crtc
)
5723 struct drm_device
*dev
= crtc
->base
.dev
;
5724 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5725 int pipe
= crtc
->pipe
;
5726 int dpll_reg
= DPLL(crtc
->pipe
);
5727 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
5728 u32 loopfilter
, intcoeff
;
5729 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
, bestm2_frac
;
5732 bestn
= crtc
->config
.dpll
.n
;
5733 bestm2_frac
= crtc
->config
.dpll
.m2
& 0x3fffff;
5734 bestm1
= crtc
->config
.dpll
.m1
;
5735 bestm2
= crtc
->config
.dpll
.m2
>> 22;
5736 bestp1
= crtc
->config
.dpll
.p1
;
5737 bestp2
= crtc
->config
.dpll
.p2
;
5740 * Enable Refclk and SSC
5742 I915_WRITE(dpll_reg
,
5743 crtc
->config
.dpll_hw_state
.dpll
& ~DPLL_VCO_ENABLE
);
5745 mutex_lock(&dev_priv
->dpio_lock
);
5747 /* p1 and p2 divider */
5748 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW13(port
),
5749 5 << DPIO_CHV_S1_DIV_SHIFT
|
5750 bestp1
<< DPIO_CHV_P1_DIV_SHIFT
|
5751 bestp2
<< DPIO_CHV_P2_DIV_SHIFT
|
5752 1 << DPIO_CHV_K_DIV_SHIFT
);
5754 /* Feedback post-divider - m2 */
5755 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW0(port
), bestm2
);
5757 /* Feedback refclk divider - n and m1 */
5758 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW1(port
),
5759 DPIO_CHV_M1_DIV_BY_2
|
5760 1 << DPIO_CHV_N_DIV_SHIFT
);
5762 /* M2 fraction division */
5763 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW2(port
), bestm2_frac
);
5765 /* M2 fraction division enable */
5766 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW3(port
),
5767 DPIO_CHV_FRAC_DIV_EN
|
5768 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT
));
5771 refclk
= i9xx_get_refclk(&crtc
->base
, 0);
5772 loopfilter
= 5 << DPIO_CHV_PROP_COEFF_SHIFT
|
5773 2 << DPIO_CHV_GAIN_CTRL_SHIFT
;
5774 if (refclk
== 100000)
5776 else if (refclk
== 38400)
5780 loopfilter
|= intcoeff
<< DPIO_CHV_INT_COEFF_SHIFT
;
5781 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW6(port
), loopfilter
);
5784 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
),
5785 vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
)) |
5788 mutex_unlock(&dev_priv
->dpio_lock
);
5791 static void i9xx_update_pll(struct intel_crtc
*crtc
,
5792 intel_clock_t
*reduced_clock
,
5795 struct drm_device
*dev
= crtc
->base
.dev
;
5796 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5799 struct dpll
*clock
= &crtc
->config
.dpll
;
5801 i9xx_update_pll_dividers(crtc
, reduced_clock
);
5803 is_sdvo
= intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_SDVO
) ||
5804 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
);
5806 dpll
= DPLL_VGA_MODE_DIS
;
5808 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
))
5809 dpll
|= DPLLB_MODE_LVDS
;
5811 dpll
|= DPLLB_MODE_DAC_SERIAL
;
5813 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
5814 dpll
|= (crtc
->config
.pixel_multiplier
- 1)
5815 << SDVO_MULTIPLIER_SHIFT_HIRES
;
5819 dpll
|= DPLL_SDVO_HIGH_SPEED
;
5821 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
))
5822 dpll
|= DPLL_SDVO_HIGH_SPEED
;
5824 /* compute bitmask from p1 value */
5825 if (IS_PINEVIEW(dev
))
5826 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
5828 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5829 if (IS_G4X(dev
) && reduced_clock
)
5830 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
5832 switch (clock
->p2
) {
5834 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
5837 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
5840 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
5843 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
5846 if (INTEL_INFO(dev
)->gen
>= 4)
5847 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
5849 if (crtc
->config
.sdvo_tv_clock
)
5850 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
5851 else if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
5852 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
5853 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
5855 dpll
|= PLL_REF_INPUT_DREFCLK
;
5857 dpll
|= DPLL_VCO_ENABLE
;
5858 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
5860 if (INTEL_INFO(dev
)->gen
>= 4) {
5861 u32 dpll_md
= (crtc
->config
.pixel_multiplier
- 1)
5862 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
5863 crtc
->config
.dpll_hw_state
.dpll_md
= dpll_md
;
5867 static void i8xx_update_pll(struct intel_crtc
*crtc
,
5868 intel_clock_t
*reduced_clock
,
5871 struct drm_device
*dev
= crtc
->base
.dev
;
5872 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5874 struct dpll
*clock
= &crtc
->config
.dpll
;
5876 i9xx_update_pll_dividers(crtc
, reduced_clock
);
5878 dpll
= DPLL_VGA_MODE_DIS
;
5880 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
)) {
5881 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5884 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
5886 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5888 dpll
|= PLL_P2_DIVIDE_BY_4
;
5891 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DVO
))
5892 dpll
|= DPLL_DVO_2X_MODE
;
5894 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
5895 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
5896 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
5898 dpll
|= PLL_REF_INPUT_DREFCLK
;
5900 dpll
|= DPLL_VCO_ENABLE
;
5901 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
5904 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
)
5906 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5907 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5908 enum pipe pipe
= intel_crtc
->pipe
;
5909 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
5910 struct drm_display_mode
*adjusted_mode
=
5911 &intel_crtc
->config
.adjusted_mode
;
5912 uint32_t crtc_vtotal
, crtc_vblank_end
;
5915 /* We need to be careful not to changed the adjusted mode, for otherwise
5916 * the hw state checker will get angry at the mismatch. */
5917 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
5918 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
5920 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
5921 /* the chip adds 2 halflines automatically */
5923 crtc_vblank_end
-= 1;
5925 if (intel_pipe_has_type(&intel_crtc
->base
, INTEL_OUTPUT_SDVO
))
5926 vsyncshift
= (adjusted_mode
->crtc_htotal
- 1) / 2;
5928 vsyncshift
= adjusted_mode
->crtc_hsync_start
-
5929 adjusted_mode
->crtc_htotal
/ 2;
5931 vsyncshift
+= adjusted_mode
->crtc_htotal
;
5934 if (INTEL_INFO(dev
)->gen
> 3)
5935 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
5937 I915_WRITE(HTOTAL(cpu_transcoder
),
5938 (adjusted_mode
->crtc_hdisplay
- 1) |
5939 ((adjusted_mode
->crtc_htotal
- 1) << 16));
5940 I915_WRITE(HBLANK(cpu_transcoder
),
5941 (adjusted_mode
->crtc_hblank_start
- 1) |
5942 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
5943 I915_WRITE(HSYNC(cpu_transcoder
),
5944 (adjusted_mode
->crtc_hsync_start
- 1) |
5945 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
5947 I915_WRITE(VTOTAL(cpu_transcoder
),
5948 (adjusted_mode
->crtc_vdisplay
- 1) |
5949 ((crtc_vtotal
- 1) << 16));
5950 I915_WRITE(VBLANK(cpu_transcoder
),
5951 (adjusted_mode
->crtc_vblank_start
- 1) |
5952 ((crtc_vblank_end
- 1) << 16));
5953 I915_WRITE(VSYNC(cpu_transcoder
),
5954 (adjusted_mode
->crtc_vsync_start
- 1) |
5955 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
5957 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5958 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5959 * documented on the DDI_FUNC_CTL register description, EDP Input Select
5961 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
5962 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
5963 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
5965 /* pipesrc controls the size that is scaled from, which should
5966 * always be the user's requested size.
5968 I915_WRITE(PIPESRC(pipe
),
5969 ((intel_crtc
->config
.pipe_src_w
- 1) << 16) |
5970 (intel_crtc
->config
.pipe_src_h
- 1));
5973 static void intel_get_pipe_timings(struct intel_crtc
*crtc
,
5974 struct intel_crtc_config
*pipe_config
)
5976 struct drm_device
*dev
= crtc
->base
.dev
;
5977 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5978 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
5981 tmp
= I915_READ(HTOTAL(cpu_transcoder
));
5982 pipe_config
->adjusted_mode
.crtc_hdisplay
= (tmp
& 0xffff) + 1;
5983 pipe_config
->adjusted_mode
.crtc_htotal
= ((tmp
>> 16) & 0xffff) + 1;
5984 tmp
= I915_READ(HBLANK(cpu_transcoder
));
5985 pipe_config
->adjusted_mode
.crtc_hblank_start
= (tmp
& 0xffff) + 1;
5986 pipe_config
->adjusted_mode
.crtc_hblank_end
= ((tmp
>> 16) & 0xffff) + 1;
5987 tmp
= I915_READ(HSYNC(cpu_transcoder
));
5988 pipe_config
->adjusted_mode
.crtc_hsync_start
= (tmp
& 0xffff) + 1;
5989 pipe_config
->adjusted_mode
.crtc_hsync_end
= ((tmp
>> 16) & 0xffff) + 1;
5991 tmp
= I915_READ(VTOTAL(cpu_transcoder
));
5992 pipe_config
->adjusted_mode
.crtc_vdisplay
= (tmp
& 0xffff) + 1;
5993 pipe_config
->adjusted_mode
.crtc_vtotal
= ((tmp
>> 16) & 0xffff) + 1;
5994 tmp
= I915_READ(VBLANK(cpu_transcoder
));
5995 pipe_config
->adjusted_mode
.crtc_vblank_start
= (tmp
& 0xffff) + 1;
5996 pipe_config
->adjusted_mode
.crtc_vblank_end
= ((tmp
>> 16) & 0xffff) + 1;
5997 tmp
= I915_READ(VSYNC(cpu_transcoder
));
5998 pipe_config
->adjusted_mode
.crtc_vsync_start
= (tmp
& 0xffff) + 1;
5999 pipe_config
->adjusted_mode
.crtc_vsync_end
= ((tmp
>> 16) & 0xffff) + 1;
6001 if (I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_INTERLACE_MASK
) {
6002 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
6003 pipe_config
->adjusted_mode
.crtc_vtotal
+= 1;
6004 pipe_config
->adjusted_mode
.crtc_vblank_end
+= 1;
6007 tmp
= I915_READ(PIPESRC(crtc
->pipe
));
6008 pipe_config
->pipe_src_h
= (tmp
& 0xffff) + 1;
6009 pipe_config
->pipe_src_w
= ((tmp
>> 16) & 0xffff) + 1;
6011 pipe_config
->requested_mode
.vdisplay
= pipe_config
->pipe_src_h
;
6012 pipe_config
->requested_mode
.hdisplay
= pipe_config
->pipe_src_w
;
6015 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
6016 struct intel_crtc_config
*pipe_config
)
6018 mode
->hdisplay
= pipe_config
->adjusted_mode
.crtc_hdisplay
;
6019 mode
->htotal
= pipe_config
->adjusted_mode
.crtc_htotal
;
6020 mode
->hsync_start
= pipe_config
->adjusted_mode
.crtc_hsync_start
;
6021 mode
->hsync_end
= pipe_config
->adjusted_mode
.crtc_hsync_end
;
6023 mode
->vdisplay
= pipe_config
->adjusted_mode
.crtc_vdisplay
;
6024 mode
->vtotal
= pipe_config
->adjusted_mode
.crtc_vtotal
;
6025 mode
->vsync_start
= pipe_config
->adjusted_mode
.crtc_vsync_start
;
6026 mode
->vsync_end
= pipe_config
->adjusted_mode
.crtc_vsync_end
;
6028 mode
->flags
= pipe_config
->adjusted_mode
.flags
;
6030 mode
->clock
= pipe_config
->adjusted_mode
.crtc_clock
;
6031 mode
->flags
|= pipe_config
->adjusted_mode
.flags
;
6034 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
)
6036 struct drm_device
*dev
= intel_crtc
->base
.dev
;
6037 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6042 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
6043 I915_READ(PIPECONF(intel_crtc
->pipe
)) & PIPECONF_ENABLE
)
6044 pipeconf
|= PIPECONF_ENABLE
;
6046 if (intel_crtc
->config
.double_wide
)
6047 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
6049 /* only g4x and later have fancy bpc/dither controls */
6050 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
6051 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6052 if (intel_crtc
->config
.dither
&& intel_crtc
->config
.pipe_bpp
!= 30)
6053 pipeconf
|= PIPECONF_DITHER_EN
|
6054 PIPECONF_DITHER_TYPE_SP
;
6056 switch (intel_crtc
->config
.pipe_bpp
) {
6058 pipeconf
|= PIPECONF_6BPC
;
6061 pipeconf
|= PIPECONF_8BPC
;
6064 pipeconf
|= PIPECONF_10BPC
;
6067 /* Case prevented by intel_choose_pipe_bpp_dither. */
6072 if (HAS_PIPE_CXSR(dev
)) {
6073 if (intel_crtc
->lowfreq_avail
) {
6074 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6075 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
6077 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6081 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
6082 if (INTEL_INFO(dev
)->gen
< 4 ||
6083 intel_pipe_has_type(&intel_crtc
->base
, INTEL_OUTPUT_SDVO
))
6084 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
6086 pipeconf
|= PIPECONF_INTERLACE_W_SYNC_SHIFT
;
6088 pipeconf
|= PIPECONF_PROGRESSIVE
;
6090 if (IS_VALLEYVIEW(dev
) && intel_crtc
->config
.limited_color_range
)
6091 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
6093 I915_WRITE(PIPECONF(intel_crtc
->pipe
), pipeconf
);
6094 POSTING_READ(PIPECONF(intel_crtc
->pipe
));
6097 static int i9xx_crtc_mode_set(struct drm_crtc
*crtc
,
6099 struct drm_framebuffer
*fb
)
6101 struct drm_device
*dev
= crtc
->dev
;
6102 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6103 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6104 int refclk
, num_connectors
= 0;
6105 intel_clock_t clock
, reduced_clock
;
6106 bool ok
, has_reduced_clock
= false;
6107 bool is_lvds
= false, is_dsi
= false;
6108 struct intel_encoder
*encoder
;
6109 const intel_limit_t
*limit
;
6111 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
6112 switch (encoder
->type
) {
6113 case INTEL_OUTPUT_LVDS
:
6116 case INTEL_OUTPUT_DSI
:
6127 if (!intel_crtc
->config
.clock_set
) {
6128 refclk
= i9xx_get_refclk(crtc
, num_connectors
);
6131 * Returns a set of divisors for the desired target clock with
6132 * the given refclk, or FALSE. The returned values represent
6133 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6136 limit
= intel_limit(crtc
, refclk
);
6137 ok
= dev_priv
->display
.find_dpll(limit
, crtc
,
6138 intel_crtc
->config
.port_clock
,
6139 refclk
, NULL
, &clock
);
6141 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6145 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
6147 * Ensure we match the reduced clock's P to the target
6148 * clock. If the clocks don't match, we can't switch
6149 * the display clock by using the FP0/FP1. In such case
6150 * we will disable the LVDS downclock feature.
6153 dev_priv
->display
.find_dpll(limit
, crtc
,
6154 dev_priv
->lvds_downclock
,
6158 /* Compat-code for transition, will disappear. */
6159 intel_crtc
->config
.dpll
.n
= clock
.n
;
6160 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
6161 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
6162 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
6163 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
6167 i8xx_update_pll(intel_crtc
,
6168 has_reduced_clock
? &reduced_clock
: NULL
,
6170 } else if (IS_CHERRYVIEW(dev
)) {
6171 chv_update_pll(intel_crtc
);
6172 } else if (IS_VALLEYVIEW(dev
)) {
6173 vlv_update_pll(intel_crtc
);
6175 i9xx_update_pll(intel_crtc
,
6176 has_reduced_clock
? &reduced_clock
: NULL
,
6183 static void i9xx_get_pfit_config(struct intel_crtc
*crtc
,
6184 struct intel_crtc_config
*pipe_config
)
6186 struct drm_device
*dev
= crtc
->base
.dev
;
6187 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6190 if (INTEL_INFO(dev
)->gen
<= 3 && (IS_I830(dev
) || !IS_MOBILE(dev
)))
6193 tmp
= I915_READ(PFIT_CONTROL
);
6194 if (!(tmp
& PFIT_ENABLE
))
6197 /* Check whether the pfit is attached to our pipe. */
6198 if (INTEL_INFO(dev
)->gen
< 4) {
6199 if (crtc
->pipe
!= PIPE_B
)
6202 if ((tmp
& PFIT_PIPE_MASK
) != (crtc
->pipe
<< PFIT_PIPE_SHIFT
))
6206 pipe_config
->gmch_pfit
.control
= tmp
;
6207 pipe_config
->gmch_pfit
.pgm_ratios
= I915_READ(PFIT_PGM_RATIOS
);
6208 if (INTEL_INFO(dev
)->gen
< 5)
6209 pipe_config
->gmch_pfit
.lvds_border_bits
=
6210 I915_READ(LVDS
) & LVDS_BORDER_ENABLE
;
6213 static void vlv_crtc_clock_get(struct intel_crtc
*crtc
,
6214 struct intel_crtc_config
*pipe_config
)
6216 struct drm_device
*dev
= crtc
->base
.dev
;
6217 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6218 int pipe
= pipe_config
->cpu_transcoder
;
6219 intel_clock_t clock
;
6221 int refclk
= 100000;
6223 /* In case of MIPI DPLL will not even be used */
6224 if (!(pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
))
6227 mutex_lock(&dev_priv
->dpio_lock
);
6228 mdiv
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW3(pipe
));
6229 mutex_unlock(&dev_priv
->dpio_lock
);
6231 clock
.m1
= (mdiv
>> DPIO_M1DIV_SHIFT
) & 7;
6232 clock
.m2
= mdiv
& DPIO_M2DIV_MASK
;
6233 clock
.n
= (mdiv
>> DPIO_N_SHIFT
) & 0xf;
6234 clock
.p1
= (mdiv
>> DPIO_P1_SHIFT
) & 7;
6235 clock
.p2
= (mdiv
>> DPIO_P2_SHIFT
) & 0x1f;
6237 vlv_clock(refclk
, &clock
);
6239 /* clock.dot is the fast clock */
6240 pipe_config
->port_clock
= clock
.dot
/ 5;
6243 static void i9xx_get_plane_config(struct intel_crtc
*crtc
,
6244 struct intel_plane_config
*plane_config
)
6246 struct drm_device
*dev
= crtc
->base
.dev
;
6247 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6248 u32 val
, base
, offset
;
6249 int pipe
= crtc
->pipe
, plane
= crtc
->plane
;
6250 int fourcc
, pixel_format
;
6253 crtc
->base
.primary
->fb
= kzalloc(sizeof(struct intel_framebuffer
), GFP_KERNEL
);
6254 if (!crtc
->base
.primary
->fb
) {
6255 DRM_DEBUG_KMS("failed to alloc fb\n");
6259 val
= I915_READ(DSPCNTR(plane
));
6261 if (INTEL_INFO(dev
)->gen
>= 4)
6262 if (val
& DISPPLANE_TILED
)
6263 plane_config
->tiled
= true;
6265 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
6266 fourcc
= intel_format_to_fourcc(pixel_format
);
6267 crtc
->base
.primary
->fb
->pixel_format
= fourcc
;
6268 crtc
->base
.primary
->fb
->bits_per_pixel
=
6269 drm_format_plane_cpp(fourcc
, 0) * 8;
6271 if (INTEL_INFO(dev
)->gen
>= 4) {
6272 if (plane_config
->tiled
)
6273 offset
= I915_READ(DSPTILEOFF(plane
));
6275 offset
= I915_READ(DSPLINOFF(plane
));
6276 base
= I915_READ(DSPSURF(plane
)) & 0xfffff000;
6278 base
= I915_READ(DSPADDR(plane
));
6280 plane_config
->base
= base
;
6282 val
= I915_READ(PIPESRC(pipe
));
6283 crtc
->base
.primary
->fb
->width
= ((val
>> 16) & 0xfff) + 1;
6284 crtc
->base
.primary
->fb
->height
= ((val
>> 0) & 0xfff) + 1;
6286 val
= I915_READ(DSPSTRIDE(pipe
));
6287 crtc
->base
.primary
->fb
->pitches
[0] = val
& 0xffffffc0;
6289 aligned_height
= intel_align_height(dev
, crtc
->base
.primary
->fb
->height
,
6290 plane_config
->tiled
);
6292 plane_config
->size
= PAGE_ALIGN(crtc
->base
.primary
->fb
->pitches
[0] *
6295 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6296 pipe
, plane
, crtc
->base
.primary
->fb
->width
,
6297 crtc
->base
.primary
->fb
->height
,
6298 crtc
->base
.primary
->fb
->bits_per_pixel
, base
,
6299 crtc
->base
.primary
->fb
->pitches
[0],
6300 plane_config
->size
);
6304 static void chv_crtc_clock_get(struct intel_crtc
*crtc
,
6305 struct intel_crtc_config
*pipe_config
)
6307 struct drm_device
*dev
= crtc
->base
.dev
;
6308 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6309 int pipe
= pipe_config
->cpu_transcoder
;
6310 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
6311 intel_clock_t clock
;
6312 u32 cmn_dw13
, pll_dw0
, pll_dw1
, pll_dw2
;
6313 int refclk
= 100000;
6315 mutex_lock(&dev_priv
->dpio_lock
);
6316 cmn_dw13
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW13(port
));
6317 pll_dw0
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW0(port
));
6318 pll_dw1
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW1(port
));
6319 pll_dw2
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW2(port
));
6320 mutex_unlock(&dev_priv
->dpio_lock
);
6322 clock
.m1
= (pll_dw1
& 0x7) == DPIO_CHV_M1_DIV_BY_2
? 2 : 0;
6323 clock
.m2
= ((pll_dw0
& 0xff) << 22) | (pll_dw2
& 0x3fffff);
6324 clock
.n
= (pll_dw1
>> DPIO_CHV_N_DIV_SHIFT
) & 0xf;
6325 clock
.p1
= (cmn_dw13
>> DPIO_CHV_P1_DIV_SHIFT
) & 0x7;
6326 clock
.p2
= (cmn_dw13
>> DPIO_CHV_P2_DIV_SHIFT
) & 0x1f;
6328 chv_clock(refclk
, &clock
);
6330 /* clock.dot is the fast clock */
6331 pipe_config
->port_clock
= clock
.dot
/ 5;
6334 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
6335 struct intel_crtc_config
*pipe_config
)
6337 struct drm_device
*dev
= crtc
->base
.dev
;
6338 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6341 if (!intel_display_power_enabled(dev_priv
,
6342 POWER_DOMAIN_PIPE(crtc
->pipe
)))
6345 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
6346 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
6348 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
6349 if (!(tmp
& PIPECONF_ENABLE
))
6352 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
6353 switch (tmp
& PIPECONF_BPC_MASK
) {
6355 pipe_config
->pipe_bpp
= 18;
6358 pipe_config
->pipe_bpp
= 24;
6360 case PIPECONF_10BPC
:
6361 pipe_config
->pipe_bpp
= 30;
6368 if (IS_VALLEYVIEW(dev
) && (tmp
& PIPECONF_COLOR_RANGE_SELECT
))
6369 pipe_config
->limited_color_range
= true;
6371 if (INTEL_INFO(dev
)->gen
< 4)
6372 pipe_config
->double_wide
= tmp
& PIPECONF_DOUBLE_WIDE
;
6374 intel_get_pipe_timings(crtc
, pipe_config
);
6376 i9xx_get_pfit_config(crtc
, pipe_config
);
6378 if (INTEL_INFO(dev
)->gen
>= 4) {
6379 tmp
= I915_READ(DPLL_MD(crtc
->pipe
));
6380 pipe_config
->pixel_multiplier
=
6381 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
6382 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
6383 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
6384 } else if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
6385 tmp
= I915_READ(DPLL(crtc
->pipe
));
6386 pipe_config
->pixel_multiplier
=
6387 ((tmp
& SDVO_MULTIPLIER_MASK
)
6388 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
6390 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6391 * port and will be fixed up in the encoder->get_config
6393 pipe_config
->pixel_multiplier
= 1;
6395 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(crtc
->pipe
));
6396 if (!IS_VALLEYVIEW(dev
)) {
6397 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(crtc
->pipe
));
6398 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(crtc
->pipe
));
6400 /* Mask out read-only status bits. */
6401 pipe_config
->dpll_hw_state
.dpll
&= ~(DPLL_LOCK_VLV
|
6402 DPLL_PORTC_READY_MASK
|
6403 DPLL_PORTB_READY_MASK
);
6406 if (IS_CHERRYVIEW(dev
))
6407 chv_crtc_clock_get(crtc
, pipe_config
);
6408 else if (IS_VALLEYVIEW(dev
))
6409 vlv_crtc_clock_get(crtc
, pipe_config
);
6411 i9xx_crtc_clock_get(crtc
, pipe_config
);
6416 static void ironlake_init_pch_refclk(struct drm_device
*dev
)
6418 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6419 struct intel_encoder
*encoder
;
6421 bool has_lvds
= false;
6422 bool has_cpu_edp
= false;
6423 bool has_panel
= false;
6424 bool has_ck505
= false;
6425 bool can_ssc
= false;
6427 /* We need to take the global config into account */
6428 for_each_intel_encoder(dev
, encoder
) {
6429 switch (encoder
->type
) {
6430 case INTEL_OUTPUT_LVDS
:
6434 case INTEL_OUTPUT_EDP
:
6436 if (enc_to_dig_port(&encoder
->base
)->port
== PORT_A
)
6442 if (HAS_PCH_IBX(dev
)) {
6443 has_ck505
= dev_priv
->vbt
.display_clock_mode
;
6444 can_ssc
= has_ck505
;
6450 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6451 has_panel
, has_lvds
, has_ck505
);
6453 /* Ironlake: try to setup display ref clock before DPLL
6454 * enabling. This is only under driver's control after
6455 * PCH B stepping, previous chipset stepping should be
6456 * ignoring this setting.
6458 val
= I915_READ(PCH_DREF_CONTROL
);
6460 /* As we must carefully and slowly disable/enable each source in turn,
6461 * compute the final state we want first and check if we need to
6462 * make any changes at all.
6465 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
6467 final
|= DREF_NONSPREAD_CK505_ENABLE
;
6469 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
6471 final
&= ~DREF_SSC_SOURCE_MASK
;
6472 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
6473 final
&= ~DREF_SSC1_ENABLE
;
6476 final
|= DREF_SSC_SOURCE_ENABLE
;
6478 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
6479 final
|= DREF_SSC1_ENABLE
;
6482 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
6483 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
6485 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
6487 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6489 final
|= DREF_SSC_SOURCE_DISABLE
;
6490 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6496 /* Always enable nonspread source */
6497 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
6500 val
|= DREF_NONSPREAD_CK505_ENABLE
;
6502 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
6505 val
&= ~DREF_SSC_SOURCE_MASK
;
6506 val
|= DREF_SSC_SOURCE_ENABLE
;
6508 /* SSC must be turned on before enabling the CPU output */
6509 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
6510 DRM_DEBUG_KMS("Using SSC on panel\n");
6511 val
|= DREF_SSC1_ENABLE
;
6513 val
&= ~DREF_SSC1_ENABLE
;
6515 /* Get SSC going before enabling the outputs */
6516 I915_WRITE(PCH_DREF_CONTROL
, val
);
6517 POSTING_READ(PCH_DREF_CONTROL
);
6520 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
6522 /* Enable CPU source on CPU attached eDP */
6524 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
6525 DRM_DEBUG_KMS("Using SSC on eDP\n");
6526 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
6528 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
6530 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6532 I915_WRITE(PCH_DREF_CONTROL
, val
);
6533 POSTING_READ(PCH_DREF_CONTROL
);
6536 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6538 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
6540 /* Turn off CPU output */
6541 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6543 I915_WRITE(PCH_DREF_CONTROL
, val
);
6544 POSTING_READ(PCH_DREF_CONTROL
);
6547 /* Turn off the SSC source */
6548 val
&= ~DREF_SSC_SOURCE_MASK
;
6549 val
|= DREF_SSC_SOURCE_DISABLE
;
6552 val
&= ~DREF_SSC1_ENABLE
;
6554 I915_WRITE(PCH_DREF_CONTROL
, val
);
6555 POSTING_READ(PCH_DREF_CONTROL
);
6559 BUG_ON(val
!= final
);
6562 static void lpt_reset_fdi_mphy(struct drm_i915_private
*dev_priv
)
6566 tmp
= I915_READ(SOUTH_CHICKEN2
);
6567 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
6568 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
6570 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2
) &
6571 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
6572 DRM_ERROR("FDI mPHY reset assert timeout\n");
6574 tmp
= I915_READ(SOUTH_CHICKEN2
);
6575 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
6576 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
6578 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2
) &
6579 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0, 100))
6580 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6583 /* WaMPhyProgramming:hsw */
6584 static void lpt_program_fdi_mphy(struct drm_i915_private
*dev_priv
)
6588 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
6589 tmp
&= ~(0xFF << 24);
6590 tmp
|= (0x12 << 24);
6591 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
6593 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
6595 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
6597 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
6599 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
6601 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
6602 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
6603 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
6605 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
6606 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
6607 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
6609 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
6612 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
6614 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
6617 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
6619 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
6622 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
6624 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
6627 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
6629 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
6630 tmp
&= ~(0xFF << 16);
6631 tmp
|= (0x1C << 16);
6632 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
6634 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
6635 tmp
&= ~(0xFF << 16);
6636 tmp
|= (0x1C << 16);
6637 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
6639 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
6641 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
6643 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
6645 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
6647 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
6648 tmp
&= ~(0xF << 28);
6650 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
6652 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
6653 tmp
&= ~(0xF << 28);
6655 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
6658 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6659 * Programming" based on the parameters passed:
6660 * - Sequence to enable CLKOUT_DP
6661 * - Sequence to enable CLKOUT_DP without spread
6662 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6664 static void lpt_enable_clkout_dp(struct drm_device
*dev
, bool with_spread
,
6667 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6670 if (WARN(with_fdi
&& !with_spread
, "FDI requires downspread\n"))
6672 if (WARN(dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
&&
6673 with_fdi
, "LP PCH doesn't have FDI\n"))
6676 mutex_lock(&dev_priv
->dpio_lock
);
6678 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
6679 tmp
&= ~SBI_SSCCTL_DISABLE
;
6680 tmp
|= SBI_SSCCTL_PATHALT
;
6681 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
6686 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
6687 tmp
&= ~SBI_SSCCTL_PATHALT
;
6688 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
6691 lpt_reset_fdi_mphy(dev_priv
);
6692 lpt_program_fdi_mphy(dev_priv
);
6696 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
6697 SBI_GEN0
: SBI_DBUFF0
;
6698 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
6699 tmp
|= SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
6700 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
6702 mutex_unlock(&dev_priv
->dpio_lock
);
6705 /* Sequence to disable CLKOUT_DP */
6706 static void lpt_disable_clkout_dp(struct drm_device
*dev
)
6708 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6711 mutex_lock(&dev_priv
->dpio_lock
);
6713 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
6714 SBI_GEN0
: SBI_DBUFF0
;
6715 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
6716 tmp
&= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
6717 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
6719 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
6720 if (!(tmp
& SBI_SSCCTL_DISABLE
)) {
6721 if (!(tmp
& SBI_SSCCTL_PATHALT
)) {
6722 tmp
|= SBI_SSCCTL_PATHALT
;
6723 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
6726 tmp
|= SBI_SSCCTL_DISABLE
;
6727 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
6730 mutex_unlock(&dev_priv
->dpio_lock
);
6733 static void lpt_init_pch_refclk(struct drm_device
*dev
)
6735 struct intel_encoder
*encoder
;
6736 bool has_vga
= false;
6738 for_each_intel_encoder(dev
, encoder
) {
6739 switch (encoder
->type
) {
6740 case INTEL_OUTPUT_ANALOG
:
6747 lpt_enable_clkout_dp(dev
, true, true);
6749 lpt_disable_clkout_dp(dev
);
6753 * Initialize reference clocks when the driver loads
6755 void intel_init_pch_refclk(struct drm_device
*dev
)
6757 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
6758 ironlake_init_pch_refclk(dev
);
6759 else if (HAS_PCH_LPT(dev
))
6760 lpt_init_pch_refclk(dev
);
6763 static int ironlake_get_refclk(struct drm_crtc
*crtc
)
6765 struct drm_device
*dev
= crtc
->dev
;
6766 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6767 struct intel_encoder
*encoder
;
6768 int num_connectors
= 0;
6769 bool is_lvds
= false;
6771 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
6772 switch (encoder
->type
) {
6773 case INTEL_OUTPUT_LVDS
:
6780 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
6781 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6782 dev_priv
->vbt
.lvds_ssc_freq
);
6783 return dev_priv
->vbt
.lvds_ssc_freq
;
6789 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
)
6791 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
6792 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6793 int pipe
= intel_crtc
->pipe
;
6798 switch (intel_crtc
->config
.pipe_bpp
) {
6800 val
|= PIPECONF_6BPC
;
6803 val
|= PIPECONF_8BPC
;
6806 val
|= PIPECONF_10BPC
;
6809 val
|= PIPECONF_12BPC
;
6812 /* Case prevented by intel_choose_pipe_bpp_dither. */
6816 if (intel_crtc
->config
.dither
)
6817 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
6819 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
6820 val
|= PIPECONF_INTERLACED_ILK
;
6822 val
|= PIPECONF_PROGRESSIVE
;
6824 if (intel_crtc
->config
.limited_color_range
)
6825 val
|= PIPECONF_COLOR_RANGE_SELECT
;
6827 I915_WRITE(PIPECONF(pipe
), val
);
6828 POSTING_READ(PIPECONF(pipe
));
6832 * Set up the pipe CSC unit.
6834 * Currently only full range RGB to limited range RGB conversion
6835 * is supported, but eventually this should handle various
6836 * RGB<->YCbCr scenarios as well.
6838 static void intel_set_pipe_csc(struct drm_crtc
*crtc
)
6840 struct drm_device
*dev
= crtc
->dev
;
6841 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6842 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6843 int pipe
= intel_crtc
->pipe
;
6844 uint16_t coeff
= 0x7800; /* 1.0 */
6847 * TODO: Check what kind of values actually come out of the pipe
6848 * with these coeff/postoff values and adjust to get the best
6849 * accuracy. Perhaps we even need to take the bpc value into
6853 if (intel_crtc
->config
.limited_color_range
)
6854 coeff
= ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6857 * GY/GU and RY/RU should be the other way around according
6858 * to BSpec, but reality doesn't agree. Just set them up in
6859 * a way that results in the correct picture.
6861 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe
), coeff
<< 16);
6862 I915_WRITE(PIPE_CSC_COEFF_BY(pipe
), 0);
6864 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe
), coeff
);
6865 I915_WRITE(PIPE_CSC_COEFF_BU(pipe
), 0);
6867 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe
), 0);
6868 I915_WRITE(PIPE_CSC_COEFF_BV(pipe
), coeff
<< 16);
6870 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe
), 0);
6871 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe
), 0);
6872 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe
), 0);
6874 if (INTEL_INFO(dev
)->gen
> 6) {
6875 uint16_t postoff
= 0;
6877 if (intel_crtc
->config
.limited_color_range
)
6878 postoff
= (16 * (1 << 12) / 255) & 0x1fff;
6880 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe
), postoff
);
6881 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe
), postoff
);
6882 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe
), postoff
);
6884 I915_WRITE(PIPE_CSC_MODE(pipe
), 0);
6886 uint32_t mode
= CSC_MODE_YUV_TO_RGB
;
6888 if (intel_crtc
->config
.limited_color_range
)
6889 mode
|= CSC_BLACK_SCREEN_OFFSET
;
6891 I915_WRITE(PIPE_CSC_MODE(pipe
), mode
);
6895 static void haswell_set_pipeconf(struct drm_crtc
*crtc
)
6897 struct drm_device
*dev
= crtc
->dev
;
6898 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6899 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6900 enum pipe pipe
= intel_crtc
->pipe
;
6901 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
6906 if (IS_HASWELL(dev
) && intel_crtc
->config
.dither
)
6907 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
6909 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
6910 val
|= PIPECONF_INTERLACED_ILK
;
6912 val
|= PIPECONF_PROGRESSIVE
;
6914 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
6915 POSTING_READ(PIPECONF(cpu_transcoder
));
6917 I915_WRITE(GAMMA_MODE(intel_crtc
->pipe
), GAMMA_MODE_MODE_8BIT
);
6918 POSTING_READ(GAMMA_MODE(intel_crtc
->pipe
));
6920 if (IS_BROADWELL(dev
)) {
6923 switch (intel_crtc
->config
.pipe_bpp
) {
6925 val
|= PIPEMISC_DITHER_6_BPC
;
6928 val
|= PIPEMISC_DITHER_8_BPC
;
6931 val
|= PIPEMISC_DITHER_10_BPC
;
6934 val
|= PIPEMISC_DITHER_12_BPC
;
6937 /* Case prevented by pipe_config_set_bpp. */
6941 if (intel_crtc
->config
.dither
)
6942 val
|= PIPEMISC_DITHER_ENABLE
| PIPEMISC_DITHER_TYPE_SP
;
6944 I915_WRITE(PIPEMISC(pipe
), val
);
6948 static bool ironlake_compute_clocks(struct drm_crtc
*crtc
,
6949 intel_clock_t
*clock
,
6950 bool *has_reduced_clock
,
6951 intel_clock_t
*reduced_clock
)
6953 struct drm_device
*dev
= crtc
->dev
;
6954 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6955 struct intel_encoder
*intel_encoder
;
6957 const intel_limit_t
*limit
;
6958 bool ret
, is_lvds
= false;
6960 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
6961 switch (intel_encoder
->type
) {
6962 case INTEL_OUTPUT_LVDS
:
6968 refclk
= ironlake_get_refclk(crtc
);
6971 * Returns a set of divisors for the desired target clock with the given
6972 * refclk, or FALSE. The returned values represent the clock equation:
6973 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6975 limit
= intel_limit(crtc
, refclk
);
6976 ret
= dev_priv
->display
.find_dpll(limit
, crtc
,
6977 to_intel_crtc(crtc
)->config
.port_clock
,
6978 refclk
, NULL
, clock
);
6982 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
6984 * Ensure we match the reduced clock's P to the target clock.
6985 * If the clocks don't match, we can't switch the display clock
6986 * by using the FP0/FP1. In such case we will disable the LVDS
6987 * downclock feature.
6989 *has_reduced_clock
=
6990 dev_priv
->display
.find_dpll(limit
, crtc
,
6991 dev_priv
->lvds_downclock
,
6999 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
7002 * Account for spread spectrum to avoid
7003 * oversubscribing the link. Max center spread
7004 * is 2.5%; use 5% for safety's sake.
7006 u32 bps
= target_clock
* bpp
* 21 / 20;
7007 return DIV_ROUND_UP(bps
, link_bw
* 8);
7010 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
7012 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
7015 static uint32_t ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
7017 intel_clock_t
*reduced_clock
, u32
*fp2
)
7019 struct drm_crtc
*crtc
= &intel_crtc
->base
;
7020 struct drm_device
*dev
= crtc
->dev
;
7021 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7022 struct intel_encoder
*intel_encoder
;
7024 int factor
, num_connectors
= 0;
7025 bool is_lvds
= false, is_sdvo
= false;
7027 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
7028 switch (intel_encoder
->type
) {
7029 case INTEL_OUTPUT_LVDS
:
7032 case INTEL_OUTPUT_SDVO
:
7033 case INTEL_OUTPUT_HDMI
:
7041 /* Enable autotuning of the PLL clock (if permissible) */
7044 if ((intel_panel_use_ssc(dev_priv
) &&
7045 dev_priv
->vbt
.lvds_ssc_freq
== 100000) ||
7046 (HAS_PCH_IBX(dev
) && intel_is_dual_link_lvds(dev
)))
7048 } else if (intel_crtc
->config
.sdvo_tv_clock
)
7051 if (ironlake_needs_fb_cb_tune(&intel_crtc
->config
.dpll
, factor
))
7054 if (fp2
&& (reduced_clock
->m
< factor
* reduced_clock
->n
))
7060 dpll
|= DPLLB_MODE_LVDS
;
7062 dpll
|= DPLLB_MODE_DAC_SERIAL
;
7064 dpll
|= (intel_crtc
->config
.pixel_multiplier
- 1)
7065 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
7068 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7069 if (intel_crtc
->config
.has_dp_encoder
)
7070 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7072 /* compute bitmask from p1 value */
7073 dpll
|= (1 << (intel_crtc
->config
.dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7075 dpll
|= (1 << (intel_crtc
->config
.dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
7077 switch (intel_crtc
->config
.dpll
.p2
) {
7079 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
7082 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
7085 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
7088 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
7092 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
7093 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
7095 dpll
|= PLL_REF_INPUT_DREFCLK
;
7097 return dpll
| DPLL_VCO_ENABLE
;
7100 static int ironlake_crtc_mode_set(struct drm_crtc
*crtc
,
7102 struct drm_framebuffer
*fb
)
7104 struct drm_device
*dev
= crtc
->dev
;
7105 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7106 int num_connectors
= 0;
7107 intel_clock_t clock
, reduced_clock
;
7108 u32 dpll
= 0, fp
= 0, fp2
= 0;
7109 bool ok
, has_reduced_clock
= false;
7110 bool is_lvds
= false;
7111 struct intel_encoder
*encoder
;
7112 struct intel_shared_dpll
*pll
;
7114 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
7115 switch (encoder
->type
) {
7116 case INTEL_OUTPUT_LVDS
:
7124 WARN(!(HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)),
7125 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev
));
7127 ok
= ironlake_compute_clocks(crtc
, &clock
,
7128 &has_reduced_clock
, &reduced_clock
);
7129 if (!ok
&& !intel_crtc
->config
.clock_set
) {
7130 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7133 /* Compat-code for transition, will disappear. */
7134 if (!intel_crtc
->config
.clock_set
) {
7135 intel_crtc
->config
.dpll
.n
= clock
.n
;
7136 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
7137 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
7138 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
7139 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
7142 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7143 if (intel_crtc
->config
.has_pch_encoder
) {
7144 fp
= i9xx_dpll_compute_fp(&intel_crtc
->config
.dpll
);
7145 if (has_reduced_clock
)
7146 fp2
= i9xx_dpll_compute_fp(&reduced_clock
);
7148 dpll
= ironlake_compute_dpll(intel_crtc
,
7149 &fp
, &reduced_clock
,
7150 has_reduced_clock
? &fp2
: NULL
);
7152 intel_crtc
->config
.dpll_hw_state
.dpll
= dpll
;
7153 intel_crtc
->config
.dpll_hw_state
.fp0
= fp
;
7154 if (has_reduced_clock
)
7155 intel_crtc
->config
.dpll_hw_state
.fp1
= fp2
;
7157 intel_crtc
->config
.dpll_hw_state
.fp1
= fp
;
7159 pll
= intel_get_shared_dpll(intel_crtc
);
7161 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7162 pipe_name(intel_crtc
->pipe
));
7166 intel_put_shared_dpll(intel_crtc
);
7168 if (is_lvds
&& has_reduced_clock
&& i915
.powersave
)
7169 intel_crtc
->lowfreq_avail
= true;
7171 intel_crtc
->lowfreq_avail
= false;
7176 static void intel_pch_transcoder_get_m_n(struct intel_crtc
*crtc
,
7177 struct intel_link_m_n
*m_n
)
7179 struct drm_device
*dev
= crtc
->base
.dev
;
7180 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7181 enum pipe pipe
= crtc
->pipe
;
7183 m_n
->link_m
= I915_READ(PCH_TRANS_LINK_M1(pipe
));
7184 m_n
->link_n
= I915_READ(PCH_TRANS_LINK_N1(pipe
));
7185 m_n
->gmch_m
= I915_READ(PCH_TRANS_DATA_M1(pipe
))
7187 m_n
->gmch_n
= I915_READ(PCH_TRANS_DATA_N1(pipe
));
7188 m_n
->tu
= ((I915_READ(PCH_TRANS_DATA_M1(pipe
))
7189 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7192 static void intel_cpu_transcoder_get_m_n(struct intel_crtc
*crtc
,
7193 enum transcoder transcoder
,
7194 struct intel_link_m_n
*m_n
,
7195 struct intel_link_m_n
*m2_n2
)
7197 struct drm_device
*dev
= crtc
->base
.dev
;
7198 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7199 enum pipe pipe
= crtc
->pipe
;
7201 if (INTEL_INFO(dev
)->gen
>= 5) {
7202 m_n
->link_m
= I915_READ(PIPE_LINK_M1(transcoder
));
7203 m_n
->link_n
= I915_READ(PIPE_LINK_N1(transcoder
));
7204 m_n
->gmch_m
= I915_READ(PIPE_DATA_M1(transcoder
))
7206 m_n
->gmch_n
= I915_READ(PIPE_DATA_N1(transcoder
));
7207 m_n
->tu
= ((I915_READ(PIPE_DATA_M1(transcoder
))
7208 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7209 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7210 * gen < 8) and if DRRS is supported (to make sure the
7211 * registers are not unnecessarily read).
7213 if (m2_n2
&& INTEL_INFO(dev
)->gen
< 8 &&
7214 crtc
->config
.has_drrs
) {
7215 m2_n2
->link_m
= I915_READ(PIPE_LINK_M2(transcoder
));
7216 m2_n2
->link_n
= I915_READ(PIPE_LINK_N2(transcoder
));
7217 m2_n2
->gmch_m
= I915_READ(PIPE_DATA_M2(transcoder
))
7219 m2_n2
->gmch_n
= I915_READ(PIPE_DATA_N2(transcoder
));
7220 m2_n2
->tu
= ((I915_READ(PIPE_DATA_M2(transcoder
))
7221 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7224 m_n
->link_m
= I915_READ(PIPE_LINK_M_G4X(pipe
));
7225 m_n
->link_n
= I915_READ(PIPE_LINK_N_G4X(pipe
));
7226 m_n
->gmch_m
= I915_READ(PIPE_DATA_M_G4X(pipe
))
7228 m_n
->gmch_n
= I915_READ(PIPE_DATA_N_G4X(pipe
));
7229 m_n
->tu
= ((I915_READ(PIPE_DATA_M_G4X(pipe
))
7230 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7234 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
7235 struct intel_crtc_config
*pipe_config
)
7237 if (crtc
->config
.has_pch_encoder
)
7238 intel_pch_transcoder_get_m_n(crtc
, &pipe_config
->dp_m_n
);
7240 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
7241 &pipe_config
->dp_m_n
,
7242 &pipe_config
->dp_m2_n2
);
7245 static void ironlake_get_fdi_m_n_config(struct intel_crtc
*crtc
,
7246 struct intel_crtc_config
*pipe_config
)
7248 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
7249 &pipe_config
->fdi_m_n
, NULL
);
7252 static void ironlake_get_pfit_config(struct intel_crtc
*crtc
,
7253 struct intel_crtc_config
*pipe_config
)
7255 struct drm_device
*dev
= crtc
->base
.dev
;
7256 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7259 tmp
= I915_READ(PF_CTL(crtc
->pipe
));
7261 if (tmp
& PF_ENABLE
) {
7262 pipe_config
->pch_pfit
.enabled
= true;
7263 pipe_config
->pch_pfit
.pos
= I915_READ(PF_WIN_POS(crtc
->pipe
));
7264 pipe_config
->pch_pfit
.size
= I915_READ(PF_WIN_SZ(crtc
->pipe
));
7266 /* We currently do not free assignements of panel fitters on
7267 * ivb/hsw (since we don't use the higher upscaling modes which
7268 * differentiates them) so just WARN about this case for now. */
7270 WARN_ON((tmp
& PF_PIPE_SEL_MASK_IVB
) !=
7271 PF_PIPE_SEL_IVB(crtc
->pipe
));
7276 static void ironlake_get_plane_config(struct intel_crtc
*crtc
,
7277 struct intel_plane_config
*plane_config
)
7279 struct drm_device
*dev
= crtc
->base
.dev
;
7280 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7281 u32 val
, base
, offset
;
7282 int pipe
= crtc
->pipe
, plane
= crtc
->plane
;
7283 int fourcc
, pixel_format
;
7286 crtc
->base
.primary
->fb
= kzalloc(sizeof(struct intel_framebuffer
), GFP_KERNEL
);
7287 if (!crtc
->base
.primary
->fb
) {
7288 DRM_DEBUG_KMS("failed to alloc fb\n");
7292 val
= I915_READ(DSPCNTR(plane
));
7294 if (INTEL_INFO(dev
)->gen
>= 4)
7295 if (val
& DISPPLANE_TILED
)
7296 plane_config
->tiled
= true;
7298 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
7299 fourcc
= intel_format_to_fourcc(pixel_format
);
7300 crtc
->base
.primary
->fb
->pixel_format
= fourcc
;
7301 crtc
->base
.primary
->fb
->bits_per_pixel
=
7302 drm_format_plane_cpp(fourcc
, 0) * 8;
7304 base
= I915_READ(DSPSURF(plane
)) & 0xfffff000;
7305 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
7306 offset
= I915_READ(DSPOFFSET(plane
));
7308 if (plane_config
->tiled
)
7309 offset
= I915_READ(DSPTILEOFF(plane
));
7311 offset
= I915_READ(DSPLINOFF(plane
));
7313 plane_config
->base
= base
;
7315 val
= I915_READ(PIPESRC(pipe
));
7316 crtc
->base
.primary
->fb
->width
= ((val
>> 16) & 0xfff) + 1;
7317 crtc
->base
.primary
->fb
->height
= ((val
>> 0) & 0xfff) + 1;
7319 val
= I915_READ(DSPSTRIDE(pipe
));
7320 crtc
->base
.primary
->fb
->pitches
[0] = val
& 0xffffffc0;
7322 aligned_height
= intel_align_height(dev
, crtc
->base
.primary
->fb
->height
,
7323 plane_config
->tiled
);
7325 plane_config
->size
= PAGE_ALIGN(crtc
->base
.primary
->fb
->pitches
[0] *
7328 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7329 pipe
, plane
, crtc
->base
.primary
->fb
->width
,
7330 crtc
->base
.primary
->fb
->height
,
7331 crtc
->base
.primary
->fb
->bits_per_pixel
, base
,
7332 crtc
->base
.primary
->fb
->pitches
[0],
7333 plane_config
->size
);
7336 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
7337 struct intel_crtc_config
*pipe_config
)
7339 struct drm_device
*dev
= crtc
->base
.dev
;
7340 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7343 if (!intel_display_power_enabled(dev_priv
,
7344 POWER_DOMAIN_PIPE(crtc
->pipe
)))
7347 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
7348 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
7350 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
7351 if (!(tmp
& PIPECONF_ENABLE
))
7354 switch (tmp
& PIPECONF_BPC_MASK
) {
7356 pipe_config
->pipe_bpp
= 18;
7359 pipe_config
->pipe_bpp
= 24;
7361 case PIPECONF_10BPC
:
7362 pipe_config
->pipe_bpp
= 30;
7364 case PIPECONF_12BPC
:
7365 pipe_config
->pipe_bpp
= 36;
7371 if (tmp
& PIPECONF_COLOR_RANGE_SELECT
)
7372 pipe_config
->limited_color_range
= true;
7374 if (I915_READ(PCH_TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
) {
7375 struct intel_shared_dpll
*pll
;
7377 pipe_config
->has_pch_encoder
= true;
7379 tmp
= I915_READ(FDI_RX_CTL(crtc
->pipe
));
7380 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
7381 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
7383 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
7385 if (HAS_PCH_IBX(dev_priv
->dev
)) {
7386 pipe_config
->shared_dpll
=
7387 (enum intel_dpll_id
) crtc
->pipe
;
7389 tmp
= I915_READ(PCH_DPLL_SEL
);
7390 if (tmp
& TRANS_DPLLB_SEL(crtc
->pipe
))
7391 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_B
;
7393 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_A
;
7396 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
7398 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
7399 &pipe_config
->dpll_hw_state
));
7401 tmp
= pipe_config
->dpll_hw_state
.dpll
;
7402 pipe_config
->pixel_multiplier
=
7403 ((tmp
& PLL_REF_SDVO_HDMI_MULTIPLIER_MASK
)
7404 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
) + 1;
7406 ironlake_pch_clock_get(crtc
, pipe_config
);
7408 pipe_config
->pixel_multiplier
= 1;
7411 intel_get_pipe_timings(crtc
, pipe_config
);
7413 ironlake_get_pfit_config(crtc
, pipe_config
);
7418 static void assert_can_disable_lcpll(struct drm_i915_private
*dev_priv
)
7420 struct drm_device
*dev
= dev_priv
->dev
;
7421 struct intel_crtc
*crtc
;
7423 for_each_intel_crtc(dev
, crtc
)
7424 WARN(crtc
->active
, "CRTC for pipe %c enabled\n",
7425 pipe_name(crtc
->pipe
));
7427 WARN(I915_READ(HSW_PWR_WELL_DRIVER
), "Power well on\n");
7428 WARN(I915_READ(SPLL_CTL
) & SPLL_PLL_ENABLE
, "SPLL enabled\n");
7429 WARN(I915_READ(WRPLL_CTL1
) & WRPLL_PLL_ENABLE
, "WRPLL1 enabled\n");
7430 WARN(I915_READ(WRPLL_CTL2
) & WRPLL_PLL_ENABLE
, "WRPLL2 enabled\n");
7431 WARN(I915_READ(PCH_PP_STATUS
) & PP_ON
, "Panel power on\n");
7432 WARN(I915_READ(BLC_PWM_CPU_CTL2
) & BLM_PWM_ENABLE
,
7433 "CPU PWM1 enabled\n");
7434 if (IS_HASWELL(dev
))
7435 WARN(I915_READ(HSW_BLC_PWM2_CTL
) & BLM_PWM_ENABLE
,
7436 "CPU PWM2 enabled\n");
7437 WARN(I915_READ(BLC_PWM_PCH_CTL1
) & BLM_PCH_PWM_ENABLE
,
7438 "PCH PWM1 enabled\n");
7439 WARN(I915_READ(UTIL_PIN_CTL
) & UTIL_PIN_ENABLE
,
7440 "Utility pin enabled\n");
7441 WARN(I915_READ(PCH_GTC_CTL
) & PCH_GTC_ENABLE
, "PCH GTC enabled\n");
7444 * In theory we can still leave IRQs enabled, as long as only the HPD
7445 * interrupts remain enabled. We used to check for that, but since it's
7446 * gen-specific and since we only disable LCPLL after we fully disable
7447 * the interrupts, the check below should be enough.
7449 WARN(intel_irqs_enabled(dev_priv
), "IRQs enabled\n");
7452 static uint32_t hsw_read_dcomp(struct drm_i915_private
*dev_priv
)
7454 struct drm_device
*dev
= dev_priv
->dev
;
7456 if (IS_HASWELL(dev
))
7457 return I915_READ(D_COMP_HSW
);
7459 return I915_READ(D_COMP_BDW
);
7462 static void hsw_write_dcomp(struct drm_i915_private
*dev_priv
, uint32_t val
)
7464 struct drm_device
*dev
= dev_priv
->dev
;
7466 if (IS_HASWELL(dev
)) {
7467 mutex_lock(&dev_priv
->rps
.hw_lock
);
7468 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
,
7470 DRM_ERROR("Failed to write to D_COMP\n");
7471 mutex_unlock(&dev_priv
->rps
.hw_lock
);
7473 I915_WRITE(D_COMP_BDW
, val
);
7474 POSTING_READ(D_COMP_BDW
);
7479 * This function implements pieces of two sequences from BSpec:
7480 * - Sequence for display software to disable LCPLL
7481 * - Sequence for display software to allow package C8+
7482 * The steps implemented here are just the steps that actually touch the LCPLL
7483 * register. Callers should take care of disabling all the display engine
7484 * functions, doing the mode unset, fixing interrupts, etc.
7486 static void hsw_disable_lcpll(struct drm_i915_private
*dev_priv
,
7487 bool switch_to_fclk
, bool allow_power_down
)
7491 assert_can_disable_lcpll(dev_priv
);
7493 val
= I915_READ(LCPLL_CTL
);
7495 if (switch_to_fclk
) {
7496 val
|= LCPLL_CD_SOURCE_FCLK
;
7497 I915_WRITE(LCPLL_CTL
, val
);
7499 if (wait_for_atomic_us(I915_READ(LCPLL_CTL
) &
7500 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
7501 DRM_ERROR("Switching to FCLK failed\n");
7503 val
= I915_READ(LCPLL_CTL
);
7506 val
|= LCPLL_PLL_DISABLE
;
7507 I915_WRITE(LCPLL_CTL
, val
);
7508 POSTING_READ(LCPLL_CTL
);
7510 if (wait_for((I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
) == 0, 1))
7511 DRM_ERROR("LCPLL still locked\n");
7513 val
= hsw_read_dcomp(dev_priv
);
7514 val
|= D_COMP_COMP_DISABLE
;
7515 hsw_write_dcomp(dev_priv
, val
);
7518 if (wait_for((hsw_read_dcomp(dev_priv
) & D_COMP_RCOMP_IN_PROGRESS
) == 0,
7520 DRM_ERROR("D_COMP RCOMP still in progress\n");
7522 if (allow_power_down
) {
7523 val
= I915_READ(LCPLL_CTL
);
7524 val
|= LCPLL_POWER_DOWN_ALLOW
;
7525 I915_WRITE(LCPLL_CTL
, val
);
7526 POSTING_READ(LCPLL_CTL
);
7531 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7534 static void hsw_restore_lcpll(struct drm_i915_private
*dev_priv
)
7537 unsigned long irqflags
;
7539 val
= I915_READ(LCPLL_CTL
);
7541 if ((val
& (LCPLL_PLL_LOCK
| LCPLL_PLL_DISABLE
| LCPLL_CD_SOURCE_FCLK
|
7542 LCPLL_POWER_DOWN_ALLOW
)) == LCPLL_PLL_LOCK
)
7546 * Make sure we're not on PC8 state before disabling PC8, otherwise
7547 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7549 * The other problem is that hsw_restore_lcpll() is called as part of
7550 * the runtime PM resume sequence, so we can't just call
7551 * gen6_gt_force_wake_get() because that function calls
7552 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7553 * while we are on the resume sequence. So to solve this problem we have
7554 * to call special forcewake code that doesn't touch runtime PM and
7555 * doesn't enable the forcewake delayed work.
7557 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
7558 if (dev_priv
->uncore
.forcewake_count
++ == 0)
7559 dev_priv
->uncore
.funcs
.force_wake_get(dev_priv
, FORCEWAKE_ALL
);
7560 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
7562 if (val
& LCPLL_POWER_DOWN_ALLOW
) {
7563 val
&= ~LCPLL_POWER_DOWN_ALLOW
;
7564 I915_WRITE(LCPLL_CTL
, val
);
7565 POSTING_READ(LCPLL_CTL
);
7568 val
= hsw_read_dcomp(dev_priv
);
7569 val
|= D_COMP_COMP_FORCE
;
7570 val
&= ~D_COMP_COMP_DISABLE
;
7571 hsw_write_dcomp(dev_priv
, val
);
7573 val
= I915_READ(LCPLL_CTL
);
7574 val
&= ~LCPLL_PLL_DISABLE
;
7575 I915_WRITE(LCPLL_CTL
, val
);
7577 if (wait_for(I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
, 5))
7578 DRM_ERROR("LCPLL not locked yet\n");
7580 if (val
& LCPLL_CD_SOURCE_FCLK
) {
7581 val
= I915_READ(LCPLL_CTL
);
7582 val
&= ~LCPLL_CD_SOURCE_FCLK
;
7583 I915_WRITE(LCPLL_CTL
, val
);
7585 if (wait_for_atomic_us((I915_READ(LCPLL_CTL
) &
7586 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
7587 DRM_ERROR("Switching back to LCPLL failed\n");
7590 /* See the big comment above. */
7591 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
7592 if (--dev_priv
->uncore
.forcewake_count
== 0)
7593 dev_priv
->uncore
.funcs
.force_wake_put(dev_priv
, FORCEWAKE_ALL
);
7594 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
7598 * Package states C8 and deeper are really deep PC states that can only be
7599 * reached when all the devices on the system allow it, so even if the graphics
7600 * device allows PC8+, it doesn't mean the system will actually get to these
7601 * states. Our driver only allows PC8+ when going into runtime PM.
7603 * The requirements for PC8+ are that all the outputs are disabled, the power
7604 * well is disabled and most interrupts are disabled, and these are also
7605 * requirements for runtime PM. When these conditions are met, we manually do
7606 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7607 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7610 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7611 * the state of some registers, so when we come back from PC8+ we need to
7612 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7613 * need to take care of the registers kept by RC6. Notice that this happens even
7614 * if we don't put the device in PCI D3 state (which is what currently happens
7615 * because of the runtime PM support).
7617 * For more, read "Display Sequences for Package C8" on the hardware
7620 void hsw_enable_pc8(struct drm_i915_private
*dev_priv
)
7622 struct drm_device
*dev
= dev_priv
->dev
;
7625 DRM_DEBUG_KMS("Enabling package C8+\n");
7627 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
7628 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
7629 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
7630 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
7633 lpt_disable_clkout_dp(dev
);
7634 hsw_disable_lcpll(dev_priv
, true, true);
7637 void hsw_disable_pc8(struct drm_i915_private
*dev_priv
)
7639 struct drm_device
*dev
= dev_priv
->dev
;
7642 DRM_DEBUG_KMS("Disabling package C8+\n");
7644 hsw_restore_lcpll(dev_priv
);
7645 lpt_init_pch_refclk(dev
);
7647 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
7648 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
7649 val
|= PCH_LP_PARTITION_LEVEL_DISABLE
;
7650 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
7653 intel_prepare_ddi(dev
);
7656 static void snb_modeset_global_resources(struct drm_device
*dev
)
7658 modeset_update_crtc_power_domains(dev
);
7661 static void haswell_modeset_global_resources(struct drm_device
*dev
)
7663 modeset_update_crtc_power_domains(dev
);
7666 static int haswell_crtc_mode_set(struct drm_crtc
*crtc
,
7668 struct drm_framebuffer
*fb
)
7670 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7672 if (!intel_ddi_pll_select(intel_crtc
))
7675 intel_crtc
->lowfreq_avail
= false;
7680 static void haswell_get_ddi_pll(struct drm_i915_private
*dev_priv
,
7682 struct intel_crtc_config
*pipe_config
)
7684 pipe_config
->ddi_pll_sel
= I915_READ(PORT_CLK_SEL(port
));
7686 switch (pipe_config
->ddi_pll_sel
) {
7687 case PORT_CLK_SEL_WRPLL1
:
7688 pipe_config
->shared_dpll
= DPLL_ID_WRPLL1
;
7690 case PORT_CLK_SEL_WRPLL2
:
7691 pipe_config
->shared_dpll
= DPLL_ID_WRPLL2
;
7696 static void haswell_get_ddi_port_state(struct intel_crtc
*crtc
,
7697 struct intel_crtc_config
*pipe_config
)
7699 struct drm_device
*dev
= crtc
->base
.dev
;
7700 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7701 struct intel_shared_dpll
*pll
;
7705 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
7707 port
= (tmp
& TRANS_DDI_PORT_MASK
) >> TRANS_DDI_PORT_SHIFT
;
7709 haswell_get_ddi_pll(dev_priv
, port
, pipe_config
);
7711 if (pipe_config
->shared_dpll
>= 0) {
7712 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
7714 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
7715 &pipe_config
->dpll_hw_state
));
7719 * Haswell has only FDI/PCH transcoder A. It is which is connected to
7720 * DDI E. So just check whether this pipe is wired to DDI E and whether
7721 * the PCH transcoder is on.
7723 if ((port
== PORT_E
) && I915_READ(LPT_TRANSCONF
) & TRANS_ENABLE
) {
7724 pipe_config
->has_pch_encoder
= true;
7726 tmp
= I915_READ(FDI_RX_CTL(PIPE_A
));
7727 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
7728 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
7730 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
7734 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
7735 struct intel_crtc_config
*pipe_config
)
7737 struct drm_device
*dev
= crtc
->base
.dev
;
7738 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7739 enum intel_display_power_domain pfit_domain
;
7742 if (!intel_display_power_enabled(dev_priv
,
7743 POWER_DOMAIN_PIPE(crtc
->pipe
)))
7746 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
7747 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
7749 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
7750 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
7751 enum pipe trans_edp_pipe
;
7752 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
7754 WARN(1, "unknown pipe linked to edp transcoder\n");
7755 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
7756 case TRANS_DDI_EDP_INPUT_A_ON
:
7757 trans_edp_pipe
= PIPE_A
;
7759 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
7760 trans_edp_pipe
= PIPE_B
;
7762 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
7763 trans_edp_pipe
= PIPE_C
;
7767 if (trans_edp_pipe
== crtc
->pipe
)
7768 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
7771 if (!intel_display_power_enabled(dev_priv
,
7772 POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
)))
7775 tmp
= I915_READ(PIPECONF(pipe_config
->cpu_transcoder
));
7776 if (!(tmp
& PIPECONF_ENABLE
))
7779 haswell_get_ddi_port_state(crtc
, pipe_config
);
7781 intel_get_pipe_timings(crtc
, pipe_config
);
7783 pfit_domain
= POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
);
7784 if (intel_display_power_enabled(dev_priv
, pfit_domain
))
7785 ironlake_get_pfit_config(crtc
, pipe_config
);
7787 if (IS_HASWELL(dev
))
7788 pipe_config
->ips_enabled
= hsw_crtc_supports_ips(crtc
) &&
7789 (I915_READ(IPS_CTL
) & IPS_ENABLE
);
7791 pipe_config
->pixel_multiplier
= 1;
7799 } hdmi_audio_clock
[] = {
7800 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175
},
7801 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200
}, /* default per bspec */
7802 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000
},
7803 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027
},
7804 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000
},
7805 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054
},
7806 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176
},
7807 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250
},
7808 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352
},
7809 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500
},
7812 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7813 static u32
audio_config_hdmi_pixel_clock(struct drm_display_mode
*mode
)
7817 for (i
= 0; i
< ARRAY_SIZE(hdmi_audio_clock
); i
++) {
7818 if (mode
->clock
== hdmi_audio_clock
[i
].clock
)
7822 if (i
== ARRAY_SIZE(hdmi_audio_clock
)) {
7823 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode
->clock
);
7827 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7828 hdmi_audio_clock
[i
].clock
,
7829 hdmi_audio_clock
[i
].config
);
7831 return hdmi_audio_clock
[i
].config
;
7834 static bool intel_eld_uptodate(struct drm_connector
*connector
,
7835 int reg_eldv
, uint32_t bits_eldv
,
7836 int reg_elda
, uint32_t bits_elda
,
7839 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
7840 uint8_t *eld
= connector
->eld
;
7843 i
= I915_READ(reg_eldv
);
7852 i
= I915_READ(reg_elda
);
7854 I915_WRITE(reg_elda
, i
);
7856 for (i
= 0; i
< eld
[2]; i
++)
7857 if (I915_READ(reg_edid
) != *((uint32_t *)eld
+ i
))
7863 static void g4x_write_eld(struct drm_connector
*connector
,
7864 struct drm_crtc
*crtc
,
7865 struct drm_display_mode
*mode
)
7867 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
7868 uint8_t *eld
= connector
->eld
;
7873 i
= I915_READ(G4X_AUD_VID_DID
);
7875 if (i
== INTEL_AUDIO_DEVBLC
|| i
== INTEL_AUDIO_DEVCL
)
7876 eldv
= G4X_ELDV_DEVCL_DEVBLC
;
7878 eldv
= G4X_ELDV_DEVCTG
;
7880 if (intel_eld_uptodate(connector
,
7881 G4X_AUD_CNTL_ST
, eldv
,
7882 G4X_AUD_CNTL_ST
, G4X_ELD_ADDR
,
7883 G4X_HDMIW_HDMIEDID
))
7886 i
= I915_READ(G4X_AUD_CNTL_ST
);
7887 i
&= ~(eldv
| G4X_ELD_ADDR
);
7888 len
= (i
>> 9) & 0x1f; /* ELD buffer size */
7889 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
7894 len
= min_t(uint8_t, eld
[2], len
);
7895 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
7896 for (i
= 0; i
< len
; i
++)
7897 I915_WRITE(G4X_HDMIW_HDMIEDID
, *((uint32_t *)eld
+ i
));
7899 i
= I915_READ(G4X_AUD_CNTL_ST
);
7901 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
7904 static void haswell_write_eld(struct drm_connector
*connector
,
7905 struct drm_crtc
*crtc
,
7906 struct drm_display_mode
*mode
)
7908 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
7909 uint8_t *eld
= connector
->eld
;
7913 int pipe
= to_intel_crtc(crtc
)->pipe
;
7916 int hdmiw_hdmiedid
= HSW_AUD_EDID_DATA(pipe
);
7917 int aud_cntl_st
= HSW_AUD_DIP_ELD_CTRL(pipe
);
7918 int aud_config
= HSW_AUD_CFG(pipe
);
7919 int aud_cntrl_st2
= HSW_AUD_PIN_ELD_CP_VLD
;
7921 /* Audio output enable */
7922 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7923 tmp
= I915_READ(aud_cntrl_st2
);
7924 tmp
|= (AUDIO_OUTPUT_ENABLE_A
<< (pipe
* 4));
7925 I915_WRITE(aud_cntrl_st2
, tmp
);
7926 POSTING_READ(aud_cntrl_st2
);
7928 assert_pipe_disabled(dev_priv
, to_intel_crtc(crtc
)->pipe
);
7930 /* Set ELD valid state */
7931 tmp
= I915_READ(aud_cntrl_st2
);
7932 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp
);
7933 tmp
|= (AUDIO_ELD_VALID_A
<< (pipe
* 4));
7934 I915_WRITE(aud_cntrl_st2
, tmp
);
7935 tmp
= I915_READ(aud_cntrl_st2
);
7936 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp
);
7938 /* Enable HDMI mode */
7939 tmp
= I915_READ(aud_config
);
7940 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp
);
7941 /* clear N_programing_enable and N_value_index */
7942 tmp
&= ~(AUD_CONFIG_N_VALUE_INDEX
| AUD_CONFIG_N_PROG_ENABLE
);
7943 I915_WRITE(aud_config
, tmp
);
7945 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
7947 eldv
= AUDIO_ELD_VALID_A
<< (pipe
* 4);
7949 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
7950 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7951 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7952 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
7954 I915_WRITE(aud_config
, audio_config_hdmi_pixel_clock(mode
));
7957 if (intel_eld_uptodate(connector
,
7958 aud_cntrl_st2
, eldv
,
7959 aud_cntl_st
, IBX_ELD_ADDRESS
,
7963 i
= I915_READ(aud_cntrl_st2
);
7965 I915_WRITE(aud_cntrl_st2
, i
);
7970 i
= I915_READ(aud_cntl_st
);
7971 i
&= ~IBX_ELD_ADDRESS
;
7972 I915_WRITE(aud_cntl_st
, i
);
7973 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
7974 DRM_DEBUG_DRIVER("port num:%d\n", i
);
7976 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
7977 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
7978 for (i
= 0; i
< len
; i
++)
7979 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
7981 i
= I915_READ(aud_cntrl_st2
);
7983 I915_WRITE(aud_cntrl_st2
, i
);
7987 static void ironlake_write_eld(struct drm_connector
*connector
,
7988 struct drm_crtc
*crtc
,
7989 struct drm_display_mode
*mode
)
7991 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
7992 uint8_t *eld
= connector
->eld
;
8000 int pipe
= to_intel_crtc(crtc
)->pipe
;
8002 if (HAS_PCH_IBX(connector
->dev
)) {
8003 hdmiw_hdmiedid
= IBX_HDMIW_HDMIEDID(pipe
);
8004 aud_config
= IBX_AUD_CFG(pipe
);
8005 aud_cntl_st
= IBX_AUD_CNTL_ST(pipe
);
8006 aud_cntrl_st2
= IBX_AUD_CNTL_ST2
;
8007 } else if (IS_VALLEYVIEW(connector
->dev
)) {
8008 hdmiw_hdmiedid
= VLV_HDMIW_HDMIEDID(pipe
);
8009 aud_config
= VLV_AUD_CFG(pipe
);
8010 aud_cntl_st
= VLV_AUD_CNTL_ST(pipe
);
8011 aud_cntrl_st2
= VLV_AUD_CNTL_ST2
;
8013 hdmiw_hdmiedid
= CPT_HDMIW_HDMIEDID(pipe
);
8014 aud_config
= CPT_AUD_CFG(pipe
);
8015 aud_cntl_st
= CPT_AUD_CNTL_ST(pipe
);
8016 aud_cntrl_st2
= CPT_AUD_CNTRL_ST2
;
8019 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
8021 if (IS_VALLEYVIEW(connector
->dev
)) {
8022 struct intel_encoder
*intel_encoder
;
8023 struct intel_digital_port
*intel_dig_port
;
8025 intel_encoder
= intel_attached_encoder(connector
);
8026 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
8027 i
= intel_dig_port
->port
;
8029 i
= I915_READ(aud_cntl_st
);
8030 i
= (i
>> 29) & DIP_PORT_SEL_MASK
;
8031 /* DIP_Port_Select, 0x1 = PortB */
8035 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
8036 /* operate blindly on all ports */
8037 eldv
= IBX_ELD_VALIDB
;
8038 eldv
|= IBX_ELD_VALIDB
<< 4;
8039 eldv
|= IBX_ELD_VALIDB
<< 8;
8041 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i
));
8042 eldv
= IBX_ELD_VALIDB
<< ((i
- 1) * 4);
8045 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
8046 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
8047 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
8048 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
8050 I915_WRITE(aud_config
, audio_config_hdmi_pixel_clock(mode
));
8053 if (intel_eld_uptodate(connector
,
8054 aud_cntrl_st2
, eldv
,
8055 aud_cntl_st
, IBX_ELD_ADDRESS
,
8059 i
= I915_READ(aud_cntrl_st2
);
8061 I915_WRITE(aud_cntrl_st2
, i
);
8066 i
= I915_READ(aud_cntl_st
);
8067 i
&= ~IBX_ELD_ADDRESS
;
8068 I915_WRITE(aud_cntl_st
, i
);
8070 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
8071 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
8072 for (i
= 0; i
< len
; i
++)
8073 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
8075 i
= I915_READ(aud_cntrl_st2
);
8077 I915_WRITE(aud_cntrl_st2
, i
);
8080 void intel_write_eld(struct drm_encoder
*encoder
,
8081 struct drm_display_mode
*mode
)
8083 struct drm_crtc
*crtc
= encoder
->crtc
;
8084 struct drm_connector
*connector
;
8085 struct drm_device
*dev
= encoder
->dev
;
8086 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8088 connector
= drm_select_eld(encoder
, mode
);
8092 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8095 connector
->encoder
->base
.id
,
8096 connector
->encoder
->name
);
8098 connector
->eld
[6] = drm_av_sync_delay(connector
, mode
) / 2;
8100 if (dev_priv
->display
.write_eld
)
8101 dev_priv
->display
.write_eld(connector
, crtc
, mode
);
8104 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
8106 struct drm_device
*dev
= crtc
->dev
;
8107 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8108 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8109 uint32_t cntl
= 0, size
= 0;
8112 unsigned int width
= intel_crtc
->cursor_width
;
8113 unsigned int height
= intel_crtc
->cursor_height
;
8114 unsigned int stride
= roundup_pow_of_two(width
) * 4;
8118 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8129 cntl
|= CURSOR_ENABLE
|
8130 CURSOR_GAMMA_ENABLE
|
8131 CURSOR_FORMAT_ARGB
|
8132 CURSOR_STRIDE(stride
);
8134 size
= (height
<< 12) | width
;
8137 if (intel_crtc
->cursor_cntl
!= 0 &&
8138 (intel_crtc
->cursor_base
!= base
||
8139 intel_crtc
->cursor_size
!= size
||
8140 intel_crtc
->cursor_cntl
!= cntl
)) {
8141 /* On these chipsets we can only modify the base/size/stride
8142 * whilst the cursor is disabled.
8144 I915_WRITE(_CURACNTR
, 0);
8145 POSTING_READ(_CURACNTR
);
8146 intel_crtc
->cursor_cntl
= 0;
8149 if (intel_crtc
->cursor_base
!= base
)
8150 I915_WRITE(_CURABASE
, base
);
8152 if (intel_crtc
->cursor_size
!= size
) {
8153 I915_WRITE(CURSIZE
, size
);
8154 intel_crtc
->cursor_size
= size
;
8157 if (intel_crtc
->cursor_cntl
!= cntl
) {
8158 I915_WRITE(_CURACNTR
, cntl
);
8159 POSTING_READ(_CURACNTR
);
8160 intel_crtc
->cursor_cntl
= cntl
;
8164 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
8166 struct drm_device
*dev
= crtc
->dev
;
8167 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8168 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8169 int pipe
= intel_crtc
->pipe
;
8174 cntl
= MCURSOR_GAMMA_ENABLE
;
8175 switch (intel_crtc
->cursor_width
) {
8177 cntl
|= CURSOR_MODE_64_ARGB_AX
;
8180 cntl
|= CURSOR_MODE_128_ARGB_AX
;
8183 cntl
|= CURSOR_MODE_256_ARGB_AX
;
8189 cntl
|= pipe
<< 28; /* Connect to correct pipe */
8191 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
8192 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
8194 if (intel_crtc
->cursor_cntl
!= cntl
) {
8195 I915_WRITE(CURCNTR(pipe
), cntl
);
8196 POSTING_READ(CURCNTR(pipe
));
8197 intel_crtc
->cursor_cntl
= cntl
;
8200 /* and commit changes on next vblank */
8201 I915_WRITE(CURBASE(pipe
), base
);
8202 POSTING_READ(CURBASE(pipe
));
8205 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8206 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
8209 struct drm_device
*dev
= crtc
->dev
;
8210 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8211 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8212 int pipe
= intel_crtc
->pipe
;
8213 int x
= crtc
->cursor_x
;
8214 int y
= crtc
->cursor_y
;
8215 u32 base
= 0, pos
= 0;
8218 base
= intel_crtc
->cursor_addr
;
8220 if (x
>= intel_crtc
->config
.pipe_src_w
)
8223 if (y
>= intel_crtc
->config
.pipe_src_h
)
8227 if (x
+ intel_crtc
->cursor_width
<= 0)
8230 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
8233 pos
|= x
<< CURSOR_X_SHIFT
;
8236 if (y
+ intel_crtc
->cursor_height
<= 0)
8239 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
8242 pos
|= y
<< CURSOR_Y_SHIFT
;
8244 if (base
== 0 && intel_crtc
->cursor_base
== 0)
8247 I915_WRITE(CURPOS(pipe
), pos
);
8249 if (IS_845G(dev
) || IS_I865G(dev
))
8250 i845_update_cursor(crtc
, base
);
8252 i9xx_update_cursor(crtc
, base
);
8253 intel_crtc
->cursor_base
= base
;
8256 static bool cursor_size_ok(struct drm_device
*dev
,
8257 uint32_t width
, uint32_t height
)
8259 if (width
== 0 || height
== 0)
8263 * 845g/865g are special in that they are only limited by
8264 * the width of their cursors, the height is arbitrary up to
8265 * the precision of the register. Everything else requires
8266 * square cursors, limited to a few power-of-two sizes.
8268 if (IS_845G(dev
) || IS_I865G(dev
)) {
8269 if ((width
& 63) != 0)
8272 if (width
> (IS_845G(dev
) ? 64 : 512))
8278 switch (width
| height
) {
8294 * intel_crtc_cursor_set_obj - Set cursor to specified GEM object
8296 * Note that the object's reference will be consumed if the update fails. If
8297 * the update succeeds, the reference of the old object (if any) will be
8300 static int intel_crtc_cursor_set_obj(struct drm_crtc
*crtc
,
8301 struct drm_i915_gem_object
*obj
,
8302 uint32_t width
, uint32_t height
)
8304 struct drm_device
*dev
= crtc
->dev
;
8305 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8306 enum pipe pipe
= intel_crtc
->pipe
;
8307 unsigned old_width
, stride
;
8311 /* if we want to turn off the cursor ignore width and height */
8313 DRM_DEBUG_KMS("cursor off\n");
8315 mutex_lock(&dev
->struct_mutex
);
8319 /* Check for which cursor types we support */
8320 if (!cursor_size_ok(dev
, width
, height
)) {
8321 DRM_DEBUG("Cursor dimension not supported\n");
8325 stride
= roundup_pow_of_two(width
) * 4;
8326 if (obj
->base
.size
< stride
* height
) {
8327 DRM_DEBUG_KMS("buffer is too small\n");
8332 /* we only need to pin inside GTT if cursor is non-phy */
8333 mutex_lock(&dev
->struct_mutex
);
8334 if (!INTEL_INFO(dev
)->cursor_needs_physical
) {
8337 if (obj
->tiling_mode
) {
8338 DRM_DEBUG_KMS("cursor cannot be tiled\n");
8343 /* Note that the w/a also requires 2 PTE of padding following
8344 * the bo. We currently fill all unused PTE with the shadow
8345 * page and so we should always have valid PTE following the
8346 * cursor preventing the VT-d warning.
8349 if (need_vtd_wa(dev
))
8350 alignment
= 64*1024;
8352 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, NULL
);
8354 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8358 ret
= i915_gem_object_put_fence(obj
);
8360 DRM_DEBUG_KMS("failed to release fence for cursor");
8364 addr
= i915_gem_obj_ggtt_offset(obj
);
8366 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
8367 ret
= i915_gem_object_attach_phys(obj
, align
);
8369 DRM_DEBUG_KMS("failed to attach phys object\n");
8372 addr
= obj
->phys_handle
->busaddr
;
8376 if (intel_crtc
->cursor_bo
) {
8377 if (!INTEL_INFO(dev
)->cursor_needs_physical
)
8378 i915_gem_object_unpin_from_display_plane(intel_crtc
->cursor_bo
);
8381 i915_gem_track_fb(intel_crtc
->cursor_bo
, obj
,
8382 INTEL_FRONTBUFFER_CURSOR(pipe
));
8383 mutex_unlock(&dev
->struct_mutex
);
8385 old_width
= intel_crtc
->cursor_width
;
8387 intel_crtc
->cursor_addr
= addr
;
8388 intel_crtc
->cursor_bo
= obj
;
8389 intel_crtc
->cursor_width
= width
;
8390 intel_crtc
->cursor_height
= height
;
8392 if (intel_crtc
->active
) {
8393 if (old_width
!= width
)
8394 intel_update_watermarks(crtc
);
8395 intel_crtc_update_cursor(crtc
, intel_crtc
->cursor_bo
!= NULL
);
8398 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_CURSOR(pipe
));
8402 i915_gem_object_unpin_from_display_plane(obj
);
8404 mutex_unlock(&dev
->struct_mutex
);
8406 drm_gem_object_unreference_unlocked(&obj
->base
);
8410 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
8411 u16
*blue
, uint32_t start
, uint32_t size
)
8413 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
8414 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8416 for (i
= start
; i
< end
; i
++) {
8417 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
8418 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
8419 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
8422 intel_crtc_load_lut(crtc
);
8425 /* VESA 640x480x72Hz mode to set on the pipe */
8426 static struct drm_display_mode load_detect_mode
= {
8427 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
8428 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
8431 struct drm_framebuffer
*
8432 __intel_framebuffer_create(struct drm_device
*dev
,
8433 struct drm_mode_fb_cmd2
*mode_cmd
,
8434 struct drm_i915_gem_object
*obj
)
8436 struct intel_framebuffer
*intel_fb
;
8439 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
8441 drm_gem_object_unreference_unlocked(&obj
->base
);
8442 return ERR_PTR(-ENOMEM
);
8445 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
8449 return &intel_fb
->base
;
8451 drm_gem_object_unreference_unlocked(&obj
->base
);
8454 return ERR_PTR(ret
);
8457 static struct drm_framebuffer
*
8458 intel_framebuffer_create(struct drm_device
*dev
,
8459 struct drm_mode_fb_cmd2
*mode_cmd
,
8460 struct drm_i915_gem_object
*obj
)
8462 struct drm_framebuffer
*fb
;
8465 ret
= i915_mutex_lock_interruptible(dev
);
8467 return ERR_PTR(ret
);
8468 fb
= __intel_framebuffer_create(dev
, mode_cmd
, obj
);
8469 mutex_unlock(&dev
->struct_mutex
);
8475 intel_framebuffer_pitch_for_width(int width
, int bpp
)
8477 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
8478 return ALIGN(pitch
, 64);
8482 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
8484 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
8485 return PAGE_ALIGN(pitch
* mode
->vdisplay
);
8488 static struct drm_framebuffer
*
8489 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
8490 struct drm_display_mode
*mode
,
8493 struct drm_i915_gem_object
*obj
;
8494 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
8496 obj
= i915_gem_alloc_object(dev
,
8497 intel_framebuffer_size_for_mode(mode
, bpp
));
8499 return ERR_PTR(-ENOMEM
);
8501 mode_cmd
.width
= mode
->hdisplay
;
8502 mode_cmd
.height
= mode
->vdisplay
;
8503 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
8505 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
8507 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
8510 static struct drm_framebuffer
*
8511 mode_fits_in_fbdev(struct drm_device
*dev
,
8512 struct drm_display_mode
*mode
)
8514 #ifdef CONFIG_DRM_I915_FBDEV
8515 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8516 struct drm_i915_gem_object
*obj
;
8517 struct drm_framebuffer
*fb
;
8519 if (!dev_priv
->fbdev
)
8522 if (!dev_priv
->fbdev
->fb
)
8525 obj
= dev_priv
->fbdev
->fb
->obj
;
8528 fb
= &dev_priv
->fbdev
->fb
->base
;
8529 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
8530 fb
->bits_per_pixel
))
8533 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
8542 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
8543 struct drm_display_mode
*mode
,
8544 struct intel_load_detect_pipe
*old
,
8545 struct drm_modeset_acquire_ctx
*ctx
)
8547 struct intel_crtc
*intel_crtc
;
8548 struct intel_encoder
*intel_encoder
=
8549 intel_attached_encoder(connector
);
8550 struct drm_crtc
*possible_crtc
;
8551 struct drm_encoder
*encoder
= &intel_encoder
->base
;
8552 struct drm_crtc
*crtc
= NULL
;
8553 struct drm_device
*dev
= encoder
->dev
;
8554 struct drm_framebuffer
*fb
;
8555 struct drm_mode_config
*config
= &dev
->mode_config
;
8558 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8559 connector
->base
.id
, connector
->name
,
8560 encoder
->base
.id
, encoder
->name
);
8563 ret
= drm_modeset_lock(&config
->connection_mutex
, ctx
);
8568 * Algorithm gets a little messy:
8570 * - if the connector already has an assigned crtc, use it (but make
8571 * sure it's on first)
8573 * - try to find the first unused crtc that can drive this connector,
8574 * and use that if we find one
8577 /* See if we already have a CRTC for this connector */
8578 if (encoder
->crtc
) {
8579 crtc
= encoder
->crtc
;
8581 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
8585 old
->dpms_mode
= connector
->dpms
;
8586 old
->load_detect_temp
= false;
8588 /* Make sure the crtc and connector are running */
8589 if (connector
->dpms
!= DRM_MODE_DPMS_ON
)
8590 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
8595 /* Find an unused one (if possible) */
8596 for_each_crtc(dev
, possible_crtc
) {
8598 if (!(encoder
->possible_crtcs
& (1 << i
)))
8600 if (possible_crtc
->enabled
)
8602 /* This can occur when applying the pipe A quirk on resume. */
8603 if (to_intel_crtc(possible_crtc
)->new_enabled
)
8606 crtc
= possible_crtc
;
8611 * If we didn't find an unused CRTC, don't use any.
8614 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8618 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
8621 intel_encoder
->new_crtc
= to_intel_crtc(crtc
);
8622 to_intel_connector(connector
)->new_encoder
= intel_encoder
;
8624 intel_crtc
= to_intel_crtc(crtc
);
8625 intel_crtc
->new_enabled
= true;
8626 intel_crtc
->new_config
= &intel_crtc
->config
;
8627 old
->dpms_mode
= connector
->dpms
;
8628 old
->load_detect_temp
= true;
8629 old
->release_fb
= NULL
;
8632 mode
= &load_detect_mode
;
8634 /* We need a framebuffer large enough to accommodate all accesses
8635 * that the plane may generate whilst we perform load detection.
8636 * We can not rely on the fbcon either being present (we get called
8637 * during its initialisation to detect all boot displays, or it may
8638 * not even exist) or that it is large enough to satisfy the
8641 fb
= mode_fits_in_fbdev(dev
, mode
);
8643 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8644 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
8645 old
->release_fb
= fb
;
8647 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8649 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8653 if (intel_set_mode(crtc
, mode
, 0, 0, fb
)) {
8654 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8655 if (old
->release_fb
)
8656 old
->release_fb
->funcs
->destroy(old
->release_fb
);
8660 /* let the connector get through one full cycle before testing */
8661 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
8665 intel_crtc
->new_enabled
= crtc
->enabled
;
8666 if (intel_crtc
->new_enabled
)
8667 intel_crtc
->new_config
= &intel_crtc
->config
;
8669 intel_crtc
->new_config
= NULL
;
8671 if (ret
== -EDEADLK
) {
8672 drm_modeset_backoff(ctx
);
8679 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
8680 struct intel_load_detect_pipe
*old
)
8682 struct intel_encoder
*intel_encoder
=
8683 intel_attached_encoder(connector
);
8684 struct drm_encoder
*encoder
= &intel_encoder
->base
;
8685 struct drm_crtc
*crtc
= encoder
->crtc
;
8686 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8688 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8689 connector
->base
.id
, connector
->name
,
8690 encoder
->base
.id
, encoder
->name
);
8692 if (old
->load_detect_temp
) {
8693 to_intel_connector(connector
)->new_encoder
= NULL
;
8694 intel_encoder
->new_crtc
= NULL
;
8695 intel_crtc
->new_enabled
= false;
8696 intel_crtc
->new_config
= NULL
;
8697 intel_set_mode(crtc
, NULL
, 0, 0, NULL
);
8699 if (old
->release_fb
) {
8700 drm_framebuffer_unregister_private(old
->release_fb
);
8701 drm_framebuffer_unreference(old
->release_fb
);
8707 /* Switch crtc and encoder back off if necessary */
8708 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
)
8709 connector
->funcs
->dpms(connector
, old
->dpms_mode
);
8712 static int i9xx_pll_refclk(struct drm_device
*dev
,
8713 const struct intel_crtc_config
*pipe_config
)
8715 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8716 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
8718 if ((dpll
& PLL_REF_INPUT_MASK
) == PLLB_REF_INPUT_SPREADSPECTRUMIN
)
8719 return dev_priv
->vbt
.lvds_ssc_freq
;
8720 else if (HAS_PCH_SPLIT(dev
))
8722 else if (!IS_GEN2(dev
))
8728 /* Returns the clock of the currently programmed mode of the given pipe. */
8729 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
8730 struct intel_crtc_config
*pipe_config
)
8732 struct drm_device
*dev
= crtc
->base
.dev
;
8733 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8734 int pipe
= pipe_config
->cpu_transcoder
;
8735 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
8737 intel_clock_t clock
;
8738 int refclk
= i9xx_pll_refclk(dev
, pipe_config
);
8740 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
8741 fp
= pipe_config
->dpll_hw_state
.fp0
;
8743 fp
= pipe_config
->dpll_hw_state
.fp1
;
8745 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
8746 if (IS_PINEVIEW(dev
)) {
8747 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
8748 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
8750 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
8751 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
8754 if (!IS_GEN2(dev
)) {
8755 if (IS_PINEVIEW(dev
))
8756 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
8757 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
8759 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
8760 DPLL_FPA01_P1_POST_DIV_SHIFT
);
8762 switch (dpll
& DPLL_MODE_MASK
) {
8763 case DPLLB_MODE_DAC_SERIAL
:
8764 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
8767 case DPLLB_MODE_LVDS
:
8768 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
8772 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8773 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
8777 if (IS_PINEVIEW(dev
))
8778 pineview_clock(refclk
, &clock
);
8780 i9xx_clock(refclk
, &clock
);
8782 u32 lvds
= IS_I830(dev
) ? 0 : I915_READ(LVDS
);
8783 bool is_lvds
= (pipe
== 1) && (lvds
& LVDS_PORT_EN
);
8786 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
8787 DPLL_FPA01_P1_POST_DIV_SHIFT
);
8789 if (lvds
& LVDS_CLKB_POWER_UP
)
8794 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
8797 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
8798 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
8800 if (dpll
& PLL_P2_DIVIDE_BY_4
)
8806 i9xx_clock(refclk
, &clock
);
8810 * This value includes pixel_multiplier. We will use
8811 * port_clock to compute adjusted_mode.crtc_clock in the
8812 * encoder's get_config() function.
8814 pipe_config
->port_clock
= clock
.dot
;
8817 int intel_dotclock_calculate(int link_freq
,
8818 const struct intel_link_m_n
*m_n
)
8821 * The calculation for the data clock is:
8822 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8823 * But we want to avoid losing precison if possible, so:
8824 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8826 * and the link clock is simpler:
8827 * link_clock = (m * link_clock) / n
8833 return div_u64((u64
)m_n
->link_m
* link_freq
, m_n
->link_n
);
8836 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
8837 struct intel_crtc_config
*pipe_config
)
8839 struct drm_device
*dev
= crtc
->base
.dev
;
8841 /* read out port_clock from the DPLL */
8842 i9xx_crtc_clock_get(crtc
, pipe_config
);
8845 * This value does not include pixel_multiplier.
8846 * We will check that port_clock and adjusted_mode.crtc_clock
8847 * agree once we know their relationship in the encoder's
8848 * get_config() function.
8850 pipe_config
->adjusted_mode
.crtc_clock
=
8851 intel_dotclock_calculate(intel_fdi_link_freq(dev
) * 10000,
8852 &pipe_config
->fdi_m_n
);
8855 /** Returns the currently programmed mode of the given pipe. */
8856 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
8857 struct drm_crtc
*crtc
)
8859 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8860 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8861 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
8862 struct drm_display_mode
*mode
;
8863 struct intel_crtc_config pipe_config
;
8864 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
8865 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
8866 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
8867 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
8868 enum pipe pipe
= intel_crtc
->pipe
;
8870 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
8875 * Construct a pipe_config sufficient for getting the clock info
8876 * back out of crtc_clock_get.
8878 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8879 * to use a real value here instead.
8881 pipe_config
.cpu_transcoder
= (enum transcoder
) pipe
;
8882 pipe_config
.pixel_multiplier
= 1;
8883 pipe_config
.dpll_hw_state
.dpll
= I915_READ(DPLL(pipe
));
8884 pipe_config
.dpll_hw_state
.fp0
= I915_READ(FP0(pipe
));
8885 pipe_config
.dpll_hw_state
.fp1
= I915_READ(FP1(pipe
));
8886 i9xx_crtc_clock_get(intel_crtc
, &pipe_config
);
8888 mode
->clock
= pipe_config
.port_clock
/ pipe_config
.pixel_multiplier
;
8889 mode
->hdisplay
= (htot
& 0xffff) + 1;
8890 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
8891 mode
->hsync_start
= (hsync
& 0xffff) + 1;
8892 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
8893 mode
->vdisplay
= (vtot
& 0xffff) + 1;
8894 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
8895 mode
->vsync_start
= (vsync
& 0xffff) + 1;
8896 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
8898 drm_mode_set_name(mode
);
8903 static void intel_increase_pllclock(struct drm_device
*dev
,
8906 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8907 int dpll_reg
= DPLL(pipe
);
8910 if (!HAS_GMCH_DISPLAY(dev
))
8913 if (!dev_priv
->lvds_downclock_avail
)
8916 dpll
= I915_READ(dpll_reg
);
8917 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
8918 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8920 assert_panel_unlocked(dev_priv
, pipe
);
8922 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
8923 I915_WRITE(dpll_reg
, dpll
);
8924 intel_wait_for_vblank(dev
, pipe
);
8926 dpll
= I915_READ(dpll_reg
);
8927 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
8928 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8932 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
8934 struct drm_device
*dev
= crtc
->dev
;
8935 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8936 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8938 if (!HAS_GMCH_DISPLAY(dev
))
8941 if (!dev_priv
->lvds_downclock_avail
)
8945 * Since this is called by a timer, we should never get here in
8948 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
8949 int pipe
= intel_crtc
->pipe
;
8950 int dpll_reg
= DPLL(pipe
);
8953 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8955 assert_panel_unlocked(dev_priv
, pipe
);
8957 dpll
= I915_READ(dpll_reg
);
8958 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
8959 I915_WRITE(dpll_reg
, dpll
);
8960 intel_wait_for_vblank(dev
, pipe
);
8961 dpll
= I915_READ(dpll_reg
);
8962 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
8963 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8968 void intel_mark_busy(struct drm_device
*dev
)
8970 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8972 if (dev_priv
->mm
.busy
)
8975 intel_runtime_pm_get(dev_priv
);
8976 i915_update_gfx_val(dev_priv
);
8977 dev_priv
->mm
.busy
= true;
8980 void intel_mark_idle(struct drm_device
*dev
)
8982 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8983 struct drm_crtc
*crtc
;
8985 if (!dev_priv
->mm
.busy
)
8988 dev_priv
->mm
.busy
= false;
8990 if (!i915
.powersave
)
8993 for_each_crtc(dev
, crtc
) {
8994 if (!crtc
->primary
->fb
)
8997 intel_decrease_pllclock(crtc
);
9000 if (INTEL_INFO(dev
)->gen
>= 6)
9001 gen6_rps_idle(dev
->dev_private
);
9004 intel_runtime_pm_put(dev_priv
);
9009 * intel_mark_fb_busy - mark given planes as busy
9011 * @frontbuffer_bits: bits for the affected planes
9012 * @ring: optional ring for asynchronous commands
9014 * This function gets called every time the screen contents change. It can be
9015 * used to keep e.g. the update rate at the nominal refresh rate with DRRS.
9017 static void intel_mark_fb_busy(struct drm_device
*dev
,
9018 unsigned frontbuffer_bits
,
9019 struct intel_engine_cs
*ring
)
9021 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9024 if (!i915
.powersave
)
9027 for_each_pipe(dev_priv
, pipe
) {
9028 if (!(frontbuffer_bits
& INTEL_FRONTBUFFER_ALL_MASK(pipe
)))
9031 intel_increase_pllclock(dev
, pipe
);
9032 if (ring
&& intel_fbc_enabled(dev
))
9033 ring
->fbc_dirty
= true;
9038 * intel_fb_obj_invalidate - invalidate frontbuffer object
9039 * @obj: GEM object to invalidate
9040 * @ring: set for asynchronous rendering
9042 * This function gets called every time rendering on the given object starts and
9043 * frontbuffer caching (fbc, low refresh rate for DRRS, panel self refresh) must
9044 * be invalidated. If @ring is non-NULL any subsequent invalidation will be delayed
9045 * until the rendering completes or a flip on this frontbuffer plane is
9048 void intel_fb_obj_invalidate(struct drm_i915_gem_object
*obj
,
9049 struct intel_engine_cs
*ring
)
9051 struct drm_device
*dev
= obj
->base
.dev
;
9052 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9054 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
9056 if (!obj
->frontbuffer_bits
)
9060 mutex_lock(&dev_priv
->fb_tracking
.lock
);
9061 dev_priv
->fb_tracking
.busy_bits
9062 |= obj
->frontbuffer_bits
;
9063 dev_priv
->fb_tracking
.flip_bits
9064 &= ~obj
->frontbuffer_bits
;
9065 mutex_unlock(&dev_priv
->fb_tracking
.lock
);
9068 intel_mark_fb_busy(dev
, obj
->frontbuffer_bits
, ring
);
9070 intel_edp_psr_invalidate(dev
, obj
->frontbuffer_bits
);
9074 * intel_frontbuffer_flush - flush frontbuffer
9076 * @frontbuffer_bits: frontbuffer plane tracking bits
9078 * This function gets called every time rendering on the given planes has
9079 * completed and frontbuffer caching can be started again. Flushes will get
9080 * delayed if they're blocked by some oustanding asynchronous rendering.
9082 * Can be called without any locks held.
9084 void intel_frontbuffer_flush(struct drm_device
*dev
,
9085 unsigned frontbuffer_bits
)
9087 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9089 /* Delay flushing when rings are still busy.*/
9090 mutex_lock(&dev_priv
->fb_tracking
.lock
);
9091 frontbuffer_bits
&= ~dev_priv
->fb_tracking
.busy_bits
;
9092 mutex_unlock(&dev_priv
->fb_tracking
.lock
);
9094 intel_mark_fb_busy(dev
, frontbuffer_bits
, NULL
);
9096 intel_edp_psr_flush(dev
, frontbuffer_bits
);
9099 gen8_fbc_sw_flush(dev
, FBC_REND_CACHE_CLEAN
);
9103 * intel_fb_obj_flush - flush frontbuffer object
9104 * @obj: GEM object to flush
9105 * @retire: set when retiring asynchronous rendering
9107 * This function gets called every time rendering on the given object has
9108 * completed and frontbuffer caching can be started again. If @retire is true
9109 * then any delayed flushes will be unblocked.
9111 void intel_fb_obj_flush(struct drm_i915_gem_object
*obj
,
9114 struct drm_device
*dev
= obj
->base
.dev
;
9115 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9116 unsigned frontbuffer_bits
;
9118 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
9120 if (!obj
->frontbuffer_bits
)
9123 frontbuffer_bits
= obj
->frontbuffer_bits
;
9126 mutex_lock(&dev_priv
->fb_tracking
.lock
);
9127 /* Filter out new bits since rendering started. */
9128 frontbuffer_bits
&= dev_priv
->fb_tracking
.busy_bits
;
9130 dev_priv
->fb_tracking
.busy_bits
&= ~frontbuffer_bits
;
9131 mutex_unlock(&dev_priv
->fb_tracking
.lock
);
9134 intel_frontbuffer_flush(dev
, frontbuffer_bits
);
9138 * intel_frontbuffer_flip_prepare - prepare asnychronous frontbuffer flip
9140 * @frontbuffer_bits: frontbuffer plane tracking bits
9142 * This function gets called after scheduling a flip on @obj. The actual
9143 * frontbuffer flushing will be delayed until completion is signalled with
9144 * intel_frontbuffer_flip_complete. If an invalidate happens in between this
9145 * flush will be cancelled.
9147 * Can be called without any locks held.
9149 void intel_frontbuffer_flip_prepare(struct drm_device
*dev
,
9150 unsigned frontbuffer_bits
)
9152 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9154 mutex_lock(&dev_priv
->fb_tracking
.lock
);
9155 dev_priv
->fb_tracking
.flip_bits
9156 |= frontbuffer_bits
;
9157 mutex_unlock(&dev_priv
->fb_tracking
.lock
);
9161 * intel_frontbuffer_flip_complete - complete asynchronous frontbuffer flush
9163 * @frontbuffer_bits: frontbuffer plane tracking bits
9165 * This function gets called after the flip has been latched and will complete
9166 * on the next vblank. It will execute the fush if it hasn't been cancalled yet.
9168 * Can be called without any locks held.
9170 void intel_frontbuffer_flip_complete(struct drm_device
*dev
,
9171 unsigned frontbuffer_bits
)
9173 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9175 mutex_lock(&dev_priv
->fb_tracking
.lock
);
9176 /* Mask any cancelled flips. */
9177 frontbuffer_bits
&= dev_priv
->fb_tracking
.flip_bits
;
9178 dev_priv
->fb_tracking
.flip_bits
&= ~frontbuffer_bits
;
9179 mutex_unlock(&dev_priv
->fb_tracking
.lock
);
9181 intel_frontbuffer_flush(dev
, frontbuffer_bits
);
9184 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
9186 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9187 struct drm_device
*dev
= crtc
->dev
;
9188 struct intel_unpin_work
*work
;
9189 unsigned long flags
;
9191 spin_lock_irqsave(&dev
->event_lock
, flags
);
9192 work
= intel_crtc
->unpin_work
;
9193 intel_crtc
->unpin_work
= NULL
;
9194 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9197 cancel_work_sync(&work
->work
);
9201 drm_crtc_cleanup(crtc
);
9206 static void intel_unpin_work_fn(struct work_struct
*__work
)
9208 struct intel_unpin_work
*work
=
9209 container_of(__work
, struct intel_unpin_work
, work
);
9210 struct drm_device
*dev
= work
->crtc
->dev
;
9211 enum pipe pipe
= to_intel_crtc(work
->crtc
)->pipe
;
9213 mutex_lock(&dev
->struct_mutex
);
9214 intel_unpin_fb_obj(work
->old_fb_obj
);
9215 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
9216 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
9218 intel_update_fbc(dev
);
9219 mutex_unlock(&dev
->struct_mutex
);
9221 intel_frontbuffer_flip_complete(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
9223 BUG_ON(atomic_read(&to_intel_crtc(work
->crtc
)->unpin_work_count
) == 0);
9224 atomic_dec(&to_intel_crtc(work
->crtc
)->unpin_work_count
);
9229 static void do_intel_finish_page_flip(struct drm_device
*dev
,
9230 struct drm_crtc
*crtc
)
9232 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9233 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9234 struct intel_unpin_work
*work
;
9235 unsigned long flags
;
9237 /* Ignore early vblank irqs */
9238 if (intel_crtc
== NULL
)
9241 spin_lock_irqsave(&dev
->event_lock
, flags
);
9242 work
= intel_crtc
->unpin_work
;
9244 /* Ensure we don't miss a work->pending update ... */
9247 if (work
== NULL
|| atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
9248 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9252 /* and that the unpin work is consistent wrt ->pending. */
9255 intel_crtc
->unpin_work
= NULL
;
9258 drm_send_vblank_event(dev
, intel_crtc
->pipe
, work
->event
);
9260 drm_crtc_vblank_put(crtc
);
9262 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9264 wake_up_all(&dev_priv
->pending_flip_queue
);
9266 queue_work(dev_priv
->wq
, &work
->work
);
9268 trace_i915_flip_complete(intel_crtc
->plane
, work
->pending_flip_obj
);
9271 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
9273 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9274 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
9276 do_intel_finish_page_flip(dev
, crtc
);
9279 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
9281 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9282 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
9284 do_intel_finish_page_flip(dev
, crtc
);
9287 /* Is 'a' after or equal to 'b'? */
9288 static bool g4x_flip_count_after_eq(u32 a
, u32 b
)
9290 return !((a
- b
) & 0x80000000);
9293 static bool page_flip_finished(struct intel_crtc
*crtc
)
9295 struct drm_device
*dev
= crtc
->base
.dev
;
9296 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9299 * The relevant registers doen't exist on pre-ctg.
9300 * As the flip done interrupt doesn't trigger for mmio
9301 * flips on gmch platforms, a flip count check isn't
9302 * really needed there. But since ctg has the registers,
9303 * include it in the check anyway.
9305 if (INTEL_INFO(dev
)->gen
< 5 && !IS_G4X(dev
))
9309 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9310 * used the same base address. In that case the mmio flip might
9311 * have completed, but the CS hasn't even executed the flip yet.
9313 * A flip count check isn't enough as the CS might have updated
9314 * the base address just after start of vblank, but before we
9315 * managed to process the interrupt. This means we'd complete the
9318 * Combining both checks should get us a good enough result. It may
9319 * still happen that the CS flip has been executed, but has not
9320 * yet actually completed. But in case the base address is the same
9321 * anyway, we don't really care.
9323 return (I915_READ(DSPSURFLIVE(crtc
->plane
)) & ~0xfff) ==
9324 crtc
->unpin_work
->gtt_offset
&&
9325 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc
->pipe
)),
9326 crtc
->unpin_work
->flip_count
);
9329 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
9331 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9332 struct intel_crtc
*intel_crtc
=
9333 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
9334 unsigned long flags
;
9336 /* NB: An MMIO update of the plane base pointer will also
9337 * generate a page-flip completion irq, i.e. every modeset
9338 * is also accompanied by a spurious intel_prepare_page_flip().
9340 spin_lock_irqsave(&dev
->event_lock
, flags
);
9341 if (intel_crtc
->unpin_work
&& page_flip_finished(intel_crtc
))
9342 atomic_inc_not_zero(&intel_crtc
->unpin_work
->pending
);
9343 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9346 static inline void intel_mark_page_flip_active(struct intel_crtc
*intel_crtc
)
9348 /* Ensure that the work item is consistent when activating it ... */
9350 atomic_set(&intel_crtc
->unpin_work
->pending
, INTEL_FLIP_PENDING
);
9351 /* and that it is marked active as soon as the irq could fire. */
9355 static int intel_gen2_queue_flip(struct drm_device
*dev
,
9356 struct drm_crtc
*crtc
,
9357 struct drm_framebuffer
*fb
,
9358 struct drm_i915_gem_object
*obj
,
9359 struct intel_engine_cs
*ring
,
9362 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9366 ret
= intel_ring_begin(ring
, 6);
9370 /* Can't queue multiple flips, so wait for the previous
9371 * one to finish before executing the next.
9373 if (intel_crtc
->plane
)
9374 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
9376 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
9377 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
9378 intel_ring_emit(ring
, MI_NOOP
);
9379 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
9380 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9381 intel_ring_emit(ring
, fb
->pitches
[0]);
9382 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9383 intel_ring_emit(ring
, 0); /* aux display base address, unused */
9385 intel_mark_page_flip_active(intel_crtc
);
9386 __intel_ring_advance(ring
);
9390 static int intel_gen3_queue_flip(struct drm_device
*dev
,
9391 struct drm_crtc
*crtc
,
9392 struct drm_framebuffer
*fb
,
9393 struct drm_i915_gem_object
*obj
,
9394 struct intel_engine_cs
*ring
,
9397 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9401 ret
= intel_ring_begin(ring
, 6);
9405 if (intel_crtc
->plane
)
9406 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
9408 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
9409 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
9410 intel_ring_emit(ring
, MI_NOOP
);
9411 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
9412 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9413 intel_ring_emit(ring
, fb
->pitches
[0]);
9414 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9415 intel_ring_emit(ring
, MI_NOOP
);
9417 intel_mark_page_flip_active(intel_crtc
);
9418 __intel_ring_advance(ring
);
9422 static int intel_gen4_queue_flip(struct drm_device
*dev
,
9423 struct drm_crtc
*crtc
,
9424 struct drm_framebuffer
*fb
,
9425 struct drm_i915_gem_object
*obj
,
9426 struct intel_engine_cs
*ring
,
9429 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9430 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9431 uint32_t pf
, pipesrc
;
9434 ret
= intel_ring_begin(ring
, 4);
9438 /* i965+ uses the linear or tiled offsets from the
9439 * Display Registers (which do not change across a page-flip)
9440 * so we need only reprogram the base address.
9442 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
9443 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9444 intel_ring_emit(ring
, fb
->pitches
[0]);
9445 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
|
9448 /* XXX Enabling the panel-fitter across page-flip is so far
9449 * untested on non-native modes, so ignore it for now.
9450 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9453 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
9454 intel_ring_emit(ring
, pf
| pipesrc
);
9456 intel_mark_page_flip_active(intel_crtc
);
9457 __intel_ring_advance(ring
);
9461 static int intel_gen6_queue_flip(struct drm_device
*dev
,
9462 struct drm_crtc
*crtc
,
9463 struct drm_framebuffer
*fb
,
9464 struct drm_i915_gem_object
*obj
,
9465 struct intel_engine_cs
*ring
,
9468 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9469 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9470 uint32_t pf
, pipesrc
;
9473 ret
= intel_ring_begin(ring
, 4);
9477 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
9478 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9479 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
9480 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9482 /* Contrary to the suggestions in the documentation,
9483 * "Enable Panel Fitter" does not seem to be required when page
9484 * flipping with a non-native mode, and worse causes a normal
9486 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9489 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
9490 intel_ring_emit(ring
, pf
| pipesrc
);
9492 intel_mark_page_flip_active(intel_crtc
);
9493 __intel_ring_advance(ring
);
9497 static int intel_gen7_queue_flip(struct drm_device
*dev
,
9498 struct drm_crtc
*crtc
,
9499 struct drm_framebuffer
*fb
,
9500 struct drm_i915_gem_object
*obj
,
9501 struct intel_engine_cs
*ring
,
9504 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9505 uint32_t plane_bit
= 0;
9508 switch (intel_crtc
->plane
) {
9510 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
9513 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
9516 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
9519 WARN_ONCE(1, "unknown plane in flip command\n");
9524 if (ring
->id
== RCS
) {
9527 * On Gen 8, SRM is now taking an extra dword to accommodate
9528 * 48bits addresses, and we need a NOOP for the batch size to
9536 * BSpec MI_DISPLAY_FLIP for IVB:
9537 * "The full packet must be contained within the same cache line."
9539 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9540 * cacheline, if we ever start emitting more commands before
9541 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9542 * then do the cacheline alignment, and finally emit the
9545 ret
= intel_ring_cacheline_align(ring
);
9549 ret
= intel_ring_begin(ring
, len
);
9553 /* Unmask the flip-done completion message. Note that the bspec says that
9554 * we should do this for both the BCS and RCS, and that we must not unmask
9555 * more than one flip event at any time (or ensure that one flip message
9556 * can be sent by waiting for flip-done prior to queueing new flips).
9557 * Experimentation says that BCS works despite DERRMR masking all
9558 * flip-done completion events and that unmasking all planes at once
9559 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9560 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9562 if (ring
->id
== RCS
) {
9563 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
9564 intel_ring_emit(ring
, DERRMR
);
9565 intel_ring_emit(ring
, ~(DERRMR_PIPEA_PRI_FLIP_DONE
|
9566 DERRMR_PIPEB_PRI_FLIP_DONE
|
9567 DERRMR_PIPEC_PRI_FLIP_DONE
));
9569 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM_GEN8(1) |
9570 MI_SRM_LRM_GLOBAL_GTT
);
9572 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM(1) |
9573 MI_SRM_LRM_GLOBAL_GTT
);
9574 intel_ring_emit(ring
, DERRMR
);
9575 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
+ 256);
9577 intel_ring_emit(ring
, 0);
9578 intel_ring_emit(ring
, MI_NOOP
);
9582 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
9583 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
9584 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9585 intel_ring_emit(ring
, (MI_NOOP
));
9587 intel_mark_page_flip_active(intel_crtc
);
9588 __intel_ring_advance(ring
);
9592 static bool use_mmio_flip(struct intel_engine_cs
*ring
,
9593 struct drm_i915_gem_object
*obj
)
9596 * This is not being used for older platforms, because
9597 * non-availability of flip done interrupt forces us to use
9598 * CS flips. Older platforms derive flip done using some clever
9599 * tricks involving the flip_pending status bits and vblank irqs.
9600 * So using MMIO flips there would disrupt this mechanism.
9606 if (INTEL_INFO(ring
->dev
)->gen
< 5)
9609 if (i915
.use_mmio_flip
< 0)
9611 else if (i915
.use_mmio_flip
> 0)
9613 else if (i915
.enable_execlists
)
9616 return ring
!= obj
->ring
;
9619 static void intel_do_mmio_flip(struct intel_crtc
*intel_crtc
)
9621 struct drm_device
*dev
= intel_crtc
->base
.dev
;
9622 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9623 struct intel_framebuffer
*intel_fb
=
9624 to_intel_framebuffer(intel_crtc
->base
.primary
->fb
);
9625 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
9629 intel_mark_page_flip_active(intel_crtc
);
9631 reg
= DSPCNTR(intel_crtc
->plane
);
9632 dspcntr
= I915_READ(reg
);
9634 if (INTEL_INFO(dev
)->gen
>= 4) {
9635 if (obj
->tiling_mode
!= I915_TILING_NONE
)
9636 dspcntr
|= DISPPLANE_TILED
;
9638 dspcntr
&= ~DISPPLANE_TILED
;
9640 I915_WRITE(reg
, dspcntr
);
9642 I915_WRITE(DSPSURF(intel_crtc
->plane
),
9643 intel_crtc
->unpin_work
->gtt_offset
);
9644 POSTING_READ(DSPSURF(intel_crtc
->plane
));
9647 static int intel_postpone_flip(struct drm_i915_gem_object
*obj
)
9649 struct intel_engine_cs
*ring
;
9652 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
9654 if (!obj
->last_write_seqno
)
9659 if (i915_seqno_passed(ring
->get_seqno(ring
, true),
9660 obj
->last_write_seqno
))
9663 ret
= i915_gem_check_olr(ring
, obj
->last_write_seqno
);
9667 if (WARN_ON(!ring
->irq_get(ring
)))
9673 void intel_notify_mmio_flip(struct intel_engine_cs
*ring
)
9675 struct drm_i915_private
*dev_priv
= to_i915(ring
->dev
);
9676 struct intel_crtc
*intel_crtc
;
9677 unsigned long irq_flags
;
9680 seqno
= ring
->get_seqno(ring
, false);
9682 spin_lock_irqsave(&dev_priv
->mmio_flip_lock
, irq_flags
);
9683 for_each_intel_crtc(ring
->dev
, intel_crtc
) {
9684 struct intel_mmio_flip
*mmio_flip
;
9686 mmio_flip
= &intel_crtc
->mmio_flip
;
9687 if (mmio_flip
->seqno
== 0)
9690 if (ring
->id
!= mmio_flip
->ring_id
)
9693 if (i915_seqno_passed(seqno
, mmio_flip
->seqno
)) {
9694 intel_do_mmio_flip(intel_crtc
);
9695 mmio_flip
->seqno
= 0;
9696 ring
->irq_put(ring
);
9699 spin_unlock_irqrestore(&dev_priv
->mmio_flip_lock
, irq_flags
);
9702 static int intel_queue_mmio_flip(struct drm_device
*dev
,
9703 struct drm_crtc
*crtc
,
9704 struct drm_framebuffer
*fb
,
9705 struct drm_i915_gem_object
*obj
,
9706 struct intel_engine_cs
*ring
,
9709 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9710 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9711 unsigned long irq_flags
;
9714 if (WARN_ON(intel_crtc
->mmio_flip
.seqno
))
9717 ret
= intel_postpone_flip(obj
);
9721 intel_do_mmio_flip(intel_crtc
);
9725 spin_lock_irqsave(&dev_priv
->mmio_flip_lock
, irq_flags
);
9726 intel_crtc
->mmio_flip
.seqno
= obj
->last_write_seqno
;
9727 intel_crtc
->mmio_flip
.ring_id
= obj
->ring
->id
;
9728 spin_unlock_irqrestore(&dev_priv
->mmio_flip_lock
, irq_flags
);
9731 * Double check to catch cases where irq fired before
9732 * mmio flip data was ready
9734 intel_notify_mmio_flip(obj
->ring
);
9738 static int intel_default_queue_flip(struct drm_device
*dev
,
9739 struct drm_crtc
*crtc
,
9740 struct drm_framebuffer
*fb
,
9741 struct drm_i915_gem_object
*obj
,
9742 struct intel_engine_cs
*ring
,
9748 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
9749 struct drm_framebuffer
*fb
,
9750 struct drm_pending_vblank_event
*event
,
9751 uint32_t page_flip_flags
)
9753 struct drm_device
*dev
= crtc
->dev
;
9754 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9755 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
9756 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
9757 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9758 enum pipe pipe
= intel_crtc
->pipe
;
9759 struct intel_unpin_work
*work
;
9760 struct intel_engine_cs
*ring
;
9761 unsigned long flags
;
9764 //trigger software GT busyness calculation
9765 gen8_flip_interrupt(dev
);
9768 * drm_mode_page_flip_ioctl() should already catch this, but double
9769 * check to be safe. In the future we may enable pageflipping from
9770 * a disabled primary plane.
9772 if (WARN_ON(intel_fb_obj(old_fb
) == NULL
))
9775 /* Can't change pixel format via MI display flips. */
9776 if (fb
->pixel_format
!= crtc
->primary
->fb
->pixel_format
)
9780 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9781 * Note that pitch changes could also affect these register.
9783 if (INTEL_INFO(dev
)->gen
> 3 &&
9784 (fb
->offsets
[0] != crtc
->primary
->fb
->offsets
[0] ||
9785 fb
->pitches
[0] != crtc
->primary
->fb
->pitches
[0]))
9788 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
9791 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
9795 work
->event
= event
;
9797 work
->old_fb_obj
= intel_fb_obj(old_fb
);
9798 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
9800 ret
= drm_crtc_vblank_get(crtc
);
9804 /* We borrow the event spin lock for protecting unpin_work */
9805 spin_lock_irqsave(&dev
->event_lock
, flags
);
9806 if (intel_crtc
->unpin_work
) {
9807 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9809 drm_crtc_vblank_put(crtc
);
9811 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9814 intel_crtc
->unpin_work
= work
;
9815 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9817 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
9818 flush_workqueue(dev_priv
->wq
);
9820 ret
= i915_mutex_lock_interruptible(dev
);
9824 /* Reference the objects for the scheduled work. */
9825 drm_gem_object_reference(&work
->old_fb_obj
->base
);
9826 drm_gem_object_reference(&obj
->base
);
9828 crtc
->primary
->fb
= fb
;
9830 work
->pending_flip_obj
= obj
;
9832 work
->enable_stall_check
= true;
9834 atomic_inc(&intel_crtc
->unpin_work_count
);
9835 intel_crtc
->reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
9837 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
9838 work
->flip_count
= I915_READ(PIPE_FLIPCOUNT_GM45(pipe
)) + 1;
9840 if (IS_VALLEYVIEW(dev
)) {
9841 ring
= &dev_priv
->ring
[BCS
];
9842 if (obj
->tiling_mode
!= work
->old_fb_obj
->tiling_mode
)
9843 /* vlv: DISPLAY_FLIP fails to change tiling */
9845 } else if (IS_IVYBRIDGE(dev
)) {
9846 ring
= &dev_priv
->ring
[BCS
];
9847 } else if (INTEL_INFO(dev
)->gen
>= 7) {
9849 if (ring
== NULL
|| ring
->id
!= RCS
)
9850 ring
= &dev_priv
->ring
[BCS
];
9852 ring
= &dev_priv
->ring
[RCS
];
9855 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
9857 goto cleanup_pending
;
9860 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
;
9862 if (use_mmio_flip(ring
, obj
))
9863 ret
= intel_queue_mmio_flip(dev
, crtc
, fb
, obj
, ring
,
9866 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
, ring
,
9871 i915_gem_track_fb(work
->old_fb_obj
, obj
,
9872 INTEL_FRONTBUFFER_PRIMARY(pipe
));
9874 intel_disable_fbc(dev
);
9875 intel_frontbuffer_flip_prepare(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
9876 mutex_unlock(&dev
->struct_mutex
);
9878 trace_i915_flip_request(intel_crtc
->plane
, obj
);
9883 intel_unpin_fb_obj(obj
);
9885 atomic_dec(&intel_crtc
->unpin_work_count
);
9886 crtc
->primary
->fb
= old_fb
;
9887 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
9888 drm_gem_object_unreference(&obj
->base
);
9889 mutex_unlock(&dev
->struct_mutex
);
9892 spin_lock_irqsave(&dev
->event_lock
, flags
);
9893 intel_crtc
->unpin_work
= NULL
;
9894 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9896 drm_crtc_vblank_put(crtc
);
9902 intel_crtc_wait_for_pending_flips(crtc
);
9903 ret
= intel_pipe_set_base(crtc
, crtc
->x
, crtc
->y
, fb
);
9904 if (ret
== 0 && event
)
9905 drm_send_vblank_event(dev
, pipe
, event
);
9910 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
9911 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
9912 .load_lut
= intel_crtc_load_lut
,
9916 * intel_modeset_update_staged_output_state
9918 * Updates the staged output configuration state, e.g. after we've read out the
9921 static void intel_modeset_update_staged_output_state(struct drm_device
*dev
)
9923 struct intel_crtc
*crtc
;
9924 struct intel_encoder
*encoder
;
9925 struct intel_connector
*connector
;
9927 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9929 connector
->new_encoder
=
9930 to_intel_encoder(connector
->base
.encoder
);
9933 for_each_intel_encoder(dev
, encoder
) {
9935 to_intel_crtc(encoder
->base
.crtc
);
9938 for_each_intel_crtc(dev
, crtc
) {
9939 crtc
->new_enabled
= crtc
->base
.enabled
;
9941 if (crtc
->new_enabled
)
9942 crtc
->new_config
= &crtc
->config
;
9944 crtc
->new_config
= NULL
;
9949 * intel_modeset_commit_output_state
9951 * This function copies the stage display pipe configuration to the real one.
9953 static void intel_modeset_commit_output_state(struct drm_device
*dev
)
9955 struct intel_crtc
*crtc
;
9956 struct intel_encoder
*encoder
;
9957 struct intel_connector
*connector
;
9959 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9961 connector
->base
.encoder
= &connector
->new_encoder
->base
;
9964 for_each_intel_encoder(dev
, encoder
) {
9965 encoder
->base
.crtc
= &encoder
->new_crtc
->base
;
9968 for_each_intel_crtc(dev
, crtc
) {
9969 crtc
->base
.enabled
= crtc
->new_enabled
;
9974 connected_sink_compute_bpp(struct intel_connector
*connector
,
9975 struct intel_crtc_config
*pipe_config
)
9977 int bpp
= pipe_config
->pipe_bpp
;
9979 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9980 connector
->base
.base
.id
,
9981 connector
->base
.name
);
9983 /* Don't use an invalid EDID bpc value */
9984 if (connector
->base
.display_info
.bpc
&&
9985 connector
->base
.display_info
.bpc
* 3 < bpp
) {
9986 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9987 bpp
, connector
->base
.display_info
.bpc
*3);
9988 pipe_config
->pipe_bpp
= connector
->base
.display_info
.bpc
*3;
9991 /* Clamp bpp to 8 on screens without EDID 1.4 */
9992 if (connector
->base
.display_info
.bpc
== 0 && bpp
> 24) {
9993 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9995 pipe_config
->pipe_bpp
= 24;
10000 compute_baseline_pipe_bpp(struct intel_crtc
*crtc
,
10001 struct drm_framebuffer
*fb
,
10002 struct intel_crtc_config
*pipe_config
)
10004 struct drm_device
*dev
= crtc
->base
.dev
;
10005 struct intel_connector
*connector
;
10008 switch (fb
->pixel_format
) {
10009 case DRM_FORMAT_C8
:
10010 bpp
= 8*3; /* since we go through a colormap */
10012 case DRM_FORMAT_XRGB1555
:
10013 case DRM_FORMAT_ARGB1555
:
10014 /* checked in intel_framebuffer_init already */
10015 if (WARN_ON(INTEL_INFO(dev
)->gen
> 3))
10017 case DRM_FORMAT_RGB565
:
10018 bpp
= 6*3; /* min is 18bpp */
10020 case DRM_FORMAT_XBGR8888
:
10021 case DRM_FORMAT_ABGR8888
:
10022 /* checked in intel_framebuffer_init already */
10023 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
10025 case DRM_FORMAT_XRGB8888
:
10026 case DRM_FORMAT_ARGB8888
:
10029 case DRM_FORMAT_XRGB2101010
:
10030 case DRM_FORMAT_ARGB2101010
:
10031 case DRM_FORMAT_XBGR2101010
:
10032 case DRM_FORMAT_ABGR2101010
:
10033 /* checked in intel_framebuffer_init already */
10034 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
10038 /* TODO: gen4+ supports 16 bpc floating point, too. */
10040 DRM_DEBUG_KMS("unsupported depth\n");
10044 pipe_config
->pipe_bpp
= bpp
;
10046 /* Clamp display bpp to EDID value */
10047 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10049 if (!connector
->new_encoder
||
10050 connector
->new_encoder
->new_crtc
!= crtc
)
10053 connected_sink_compute_bpp(connector
, pipe_config
);
10059 static void intel_dump_crtc_timings(const struct drm_display_mode
*mode
)
10061 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10062 "type: 0x%x flags: 0x%x\n",
10064 mode
->crtc_hdisplay
, mode
->crtc_hsync_start
,
10065 mode
->crtc_hsync_end
, mode
->crtc_htotal
,
10066 mode
->crtc_vdisplay
, mode
->crtc_vsync_start
,
10067 mode
->crtc_vsync_end
, mode
->crtc_vtotal
, mode
->type
, mode
->flags
);
10070 static void intel_dump_pipe_config(struct intel_crtc
*crtc
,
10071 struct intel_crtc_config
*pipe_config
,
10072 const char *context
)
10074 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc
->base
.base
.id
,
10075 context
, pipe_name(crtc
->pipe
));
10077 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config
->cpu_transcoder
));
10078 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10079 pipe_config
->pipe_bpp
, pipe_config
->dither
);
10080 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10081 pipe_config
->has_pch_encoder
,
10082 pipe_config
->fdi_lanes
,
10083 pipe_config
->fdi_m_n
.gmch_m
, pipe_config
->fdi_m_n
.gmch_n
,
10084 pipe_config
->fdi_m_n
.link_m
, pipe_config
->fdi_m_n
.link_n
,
10085 pipe_config
->fdi_m_n
.tu
);
10086 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10087 pipe_config
->has_dp_encoder
,
10088 pipe_config
->dp_m_n
.gmch_m
, pipe_config
->dp_m_n
.gmch_n
,
10089 pipe_config
->dp_m_n
.link_m
, pipe_config
->dp_m_n
.link_n
,
10090 pipe_config
->dp_m_n
.tu
);
10092 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10093 pipe_config
->has_dp_encoder
,
10094 pipe_config
->dp_m2_n2
.gmch_m
,
10095 pipe_config
->dp_m2_n2
.gmch_n
,
10096 pipe_config
->dp_m2_n2
.link_m
,
10097 pipe_config
->dp_m2_n2
.link_n
,
10098 pipe_config
->dp_m2_n2
.tu
);
10100 DRM_DEBUG_KMS("requested mode:\n");
10101 drm_mode_debug_printmodeline(&pipe_config
->requested_mode
);
10102 DRM_DEBUG_KMS("adjusted mode:\n");
10103 drm_mode_debug_printmodeline(&pipe_config
->adjusted_mode
);
10104 intel_dump_crtc_timings(&pipe_config
->adjusted_mode
);
10105 DRM_DEBUG_KMS("port clock: %d\n", pipe_config
->port_clock
);
10106 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10107 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
);
10108 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10109 pipe_config
->gmch_pfit
.control
,
10110 pipe_config
->gmch_pfit
.pgm_ratios
,
10111 pipe_config
->gmch_pfit
.lvds_border_bits
);
10112 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10113 pipe_config
->pch_pfit
.pos
,
10114 pipe_config
->pch_pfit
.size
,
10115 pipe_config
->pch_pfit
.enabled
? "enabled" : "disabled");
10116 DRM_DEBUG_KMS("ips: %i\n", pipe_config
->ips_enabled
);
10117 DRM_DEBUG_KMS("double wide: %i\n", pipe_config
->double_wide
);
10120 static bool encoders_cloneable(const struct intel_encoder
*a
,
10121 const struct intel_encoder
*b
)
10123 /* masks could be asymmetric, so check both ways */
10124 return a
== b
|| (a
->cloneable
& (1 << b
->type
) &&
10125 b
->cloneable
& (1 << a
->type
));
10128 static bool check_single_encoder_cloning(struct intel_crtc
*crtc
,
10129 struct intel_encoder
*encoder
)
10131 struct drm_device
*dev
= crtc
->base
.dev
;
10132 struct intel_encoder
*source_encoder
;
10134 for_each_intel_encoder(dev
, source_encoder
) {
10135 if (source_encoder
->new_crtc
!= crtc
)
10138 if (!encoders_cloneable(encoder
, source_encoder
))
10145 static bool check_encoder_cloning(struct intel_crtc
*crtc
)
10147 struct drm_device
*dev
= crtc
->base
.dev
;
10148 struct intel_encoder
*encoder
;
10150 for_each_intel_encoder(dev
, encoder
) {
10151 if (encoder
->new_crtc
!= crtc
)
10154 if (!check_single_encoder_cloning(crtc
, encoder
))
10161 static struct intel_crtc_config
*
10162 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
10163 struct drm_framebuffer
*fb
,
10164 struct drm_display_mode
*mode
)
10166 struct drm_device
*dev
= crtc
->dev
;
10167 struct intel_encoder
*encoder
;
10168 struct intel_crtc_config
*pipe_config
;
10169 int plane_bpp
, ret
= -EINVAL
;
10172 if (!check_encoder_cloning(to_intel_crtc(crtc
))) {
10173 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10174 return ERR_PTR(-EINVAL
);
10177 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
10179 return ERR_PTR(-ENOMEM
);
10181 drm_mode_copy(&pipe_config
->adjusted_mode
, mode
);
10182 drm_mode_copy(&pipe_config
->requested_mode
, mode
);
10184 pipe_config
->cpu_transcoder
=
10185 (enum transcoder
) to_intel_crtc(crtc
)->pipe
;
10186 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
10189 * Sanitize sync polarity flags based on requested ones. If neither
10190 * positive or negative polarity is requested, treat this as meaning
10191 * negative polarity.
10193 if (!(pipe_config
->adjusted_mode
.flags
&
10194 (DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NHSYNC
)))
10195 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
10197 if (!(pipe_config
->adjusted_mode
.flags
&
10198 (DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_NVSYNC
)))
10199 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
10201 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10202 * plane pixel format and any sink constraints into account. Returns the
10203 * source plane bpp so that dithering can be selected on mismatches
10204 * after encoders and crtc also have had their say. */
10205 plane_bpp
= compute_baseline_pipe_bpp(to_intel_crtc(crtc
),
10211 * Determine the real pipe dimensions. Note that stereo modes can
10212 * increase the actual pipe size due to the frame doubling and
10213 * insertion of additional space for blanks between the frame. This
10214 * is stored in the crtc timings. We use the requested mode to do this
10215 * computation to clearly distinguish it from the adjusted mode, which
10216 * can be changed by the connectors in the below retry loop.
10218 drm_mode_set_crtcinfo(&pipe_config
->requested_mode
, CRTC_STEREO_DOUBLE
);
10219 pipe_config
->pipe_src_w
= pipe_config
->requested_mode
.crtc_hdisplay
;
10220 pipe_config
->pipe_src_h
= pipe_config
->requested_mode
.crtc_vdisplay
;
10223 /* Ensure the port clock defaults are reset when retrying. */
10224 pipe_config
->port_clock
= 0;
10225 pipe_config
->pixel_multiplier
= 1;
10227 /* Fill in default crtc timings, allow encoders to overwrite them. */
10228 drm_mode_set_crtcinfo(&pipe_config
->adjusted_mode
, CRTC_STEREO_DOUBLE
);
10230 /* Pass our mode to the connectors and the CRTC to give them a chance to
10231 * adjust it according to limitations or connector properties, and also
10232 * a chance to reject the mode entirely.
10234 for_each_intel_encoder(dev
, encoder
) {
10236 if (&encoder
->new_crtc
->base
!= crtc
)
10239 if (!(encoder
->compute_config(encoder
, pipe_config
))) {
10240 DRM_DEBUG_KMS("Encoder config failure\n");
10245 /* Set default port clock if not overwritten by the encoder. Needs to be
10246 * done afterwards in case the encoder adjusts the mode. */
10247 if (!pipe_config
->port_clock
)
10248 pipe_config
->port_clock
= pipe_config
->adjusted_mode
.crtc_clock
10249 * pipe_config
->pixel_multiplier
;
10251 ret
= intel_crtc_compute_config(to_intel_crtc(crtc
), pipe_config
);
10253 DRM_DEBUG_KMS("CRTC fixup failed\n");
10257 if (ret
== RETRY
) {
10258 if (WARN(!retry
, "loop in pipe configuration computation\n")) {
10263 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10265 goto encoder_retry
;
10268 pipe_config
->dither
= pipe_config
->pipe_bpp
!= plane_bpp
;
10269 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10270 plane_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
10272 return pipe_config
;
10274 kfree(pipe_config
);
10275 return ERR_PTR(ret
);
10278 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10279 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10281 intel_modeset_affected_pipes(struct drm_crtc
*crtc
, unsigned *modeset_pipes
,
10282 unsigned *prepare_pipes
, unsigned *disable_pipes
)
10284 struct intel_crtc
*intel_crtc
;
10285 struct drm_device
*dev
= crtc
->dev
;
10286 struct intel_encoder
*encoder
;
10287 struct intel_connector
*connector
;
10288 struct drm_crtc
*tmp_crtc
;
10290 *disable_pipes
= *modeset_pipes
= *prepare_pipes
= 0;
10292 /* Check which crtcs have changed outputs connected to them, these need
10293 * to be part of the prepare_pipes mask. We don't (yet) support global
10294 * modeset across multiple crtcs, so modeset_pipes will only have one
10295 * bit set at most. */
10296 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10298 if (connector
->base
.encoder
== &connector
->new_encoder
->base
)
10301 if (connector
->base
.encoder
) {
10302 tmp_crtc
= connector
->base
.encoder
->crtc
;
10304 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
10307 if (connector
->new_encoder
)
10309 1 << connector
->new_encoder
->new_crtc
->pipe
;
10312 for_each_intel_encoder(dev
, encoder
) {
10313 if (encoder
->base
.crtc
== &encoder
->new_crtc
->base
)
10316 if (encoder
->base
.crtc
) {
10317 tmp_crtc
= encoder
->base
.crtc
;
10319 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
10322 if (encoder
->new_crtc
)
10323 *prepare_pipes
|= 1 << encoder
->new_crtc
->pipe
;
10326 /* Check for pipes that will be enabled/disabled ... */
10327 for_each_intel_crtc(dev
, intel_crtc
) {
10328 if (intel_crtc
->base
.enabled
== intel_crtc
->new_enabled
)
10331 if (!intel_crtc
->new_enabled
)
10332 *disable_pipes
|= 1 << intel_crtc
->pipe
;
10334 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
10338 /* set_mode is also used to update properties on life display pipes. */
10339 intel_crtc
= to_intel_crtc(crtc
);
10340 if (intel_crtc
->new_enabled
)
10341 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
10344 * For simplicity do a full modeset on any pipe where the output routing
10345 * changed. We could be more clever, but that would require us to be
10346 * more careful with calling the relevant encoder->mode_set functions.
10348 if (*prepare_pipes
)
10349 *modeset_pipes
= *prepare_pipes
;
10351 /* ... and mask these out. */
10352 *modeset_pipes
&= ~(*disable_pipes
);
10353 *prepare_pipes
&= ~(*disable_pipes
);
10356 * HACK: We don't (yet) fully support global modesets. intel_set_config
10357 * obies this rule, but the modeset restore mode of
10358 * intel_modeset_setup_hw_state does not.
10360 *modeset_pipes
&= 1 << intel_crtc
->pipe
;
10361 *prepare_pipes
&= 1 << intel_crtc
->pipe
;
10363 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10364 *modeset_pipes
, *prepare_pipes
, *disable_pipes
);
10367 static bool intel_crtc_in_use(struct drm_crtc
*crtc
)
10369 struct drm_encoder
*encoder
;
10370 struct drm_device
*dev
= crtc
->dev
;
10372 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
)
10373 if (encoder
->crtc
== crtc
)
10380 intel_modeset_update_state(struct drm_device
*dev
, unsigned prepare_pipes
)
10382 struct intel_encoder
*intel_encoder
;
10383 struct intel_crtc
*intel_crtc
;
10384 struct drm_connector
*connector
;
10386 for_each_intel_encoder(dev
, intel_encoder
) {
10387 if (!intel_encoder
->base
.crtc
)
10390 intel_crtc
= to_intel_crtc(intel_encoder
->base
.crtc
);
10392 if (prepare_pipes
& (1 << intel_crtc
->pipe
))
10393 intel_encoder
->connectors_active
= false;
10396 intel_modeset_commit_output_state(dev
);
10398 /* Double check state. */
10399 for_each_intel_crtc(dev
, intel_crtc
) {
10400 WARN_ON(intel_crtc
->base
.enabled
!= intel_crtc_in_use(&intel_crtc
->base
));
10401 WARN_ON(intel_crtc
->new_config
&&
10402 intel_crtc
->new_config
!= &intel_crtc
->config
);
10403 WARN_ON(intel_crtc
->base
.enabled
!= !!intel_crtc
->new_config
);
10406 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
10407 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
10410 intel_crtc
= to_intel_crtc(connector
->encoder
->crtc
);
10412 if (prepare_pipes
& (1 << intel_crtc
->pipe
)) {
10413 struct drm_property
*dpms_property
=
10414 dev
->mode_config
.dpms_property
;
10416 connector
->dpms
= DRM_MODE_DPMS_ON
;
10417 drm_object_property_set_value(&connector
->base
,
10421 intel_encoder
= to_intel_encoder(connector
->encoder
);
10422 intel_encoder
->connectors_active
= true;
10428 static bool intel_fuzzy_clock_check(int clock1
, int clock2
)
10432 if (clock1
== clock2
)
10435 if (!clock1
|| !clock2
)
10438 diff
= abs(clock1
- clock2
);
10440 if (((((diff
+ clock1
+ clock2
) * 100)) / (clock1
+ clock2
)) < 105)
10446 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10447 list_for_each_entry((intel_crtc), \
10448 &(dev)->mode_config.crtc_list, \
10450 if (mask & (1 <<(intel_crtc)->pipe))
10453 intel_pipe_config_compare(struct drm_device
*dev
,
10454 struct intel_crtc_config
*current_config
,
10455 struct intel_crtc_config
*pipe_config
)
10457 #define PIPE_CONF_CHECK_X(name) \
10458 if (current_config->name != pipe_config->name) { \
10459 DRM_ERROR("mismatch in " #name " " \
10460 "(expected 0x%08x, found 0x%08x)\n", \
10461 current_config->name, \
10462 pipe_config->name); \
10466 #define PIPE_CONF_CHECK_I(name) \
10467 if (current_config->name != pipe_config->name) { \
10468 DRM_ERROR("mismatch in " #name " " \
10469 "(expected %i, found %i)\n", \
10470 current_config->name, \
10471 pipe_config->name); \
10475 /* This is required for BDW+ where there is only one set of registers for
10476 * switching between high and low RR.
10477 * This macro can be used whenever a comparison has to be made between one
10478 * hw state and multiple sw state variables.
10480 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10481 if ((current_config->name != pipe_config->name) && \
10482 (current_config->alt_name != pipe_config->name)) { \
10483 DRM_ERROR("mismatch in " #name " " \
10484 "(expected %i or %i, found %i)\n", \
10485 current_config->name, \
10486 current_config->alt_name, \
10487 pipe_config->name); \
10491 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10492 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10493 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10494 "(expected %i, found %i)\n", \
10495 current_config->name & (mask), \
10496 pipe_config->name & (mask)); \
10500 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10501 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10502 DRM_ERROR("mismatch in " #name " " \
10503 "(expected %i, found %i)\n", \
10504 current_config->name, \
10505 pipe_config->name); \
10509 #define PIPE_CONF_QUIRK(quirk) \
10510 ((current_config->quirks | pipe_config->quirks) & (quirk))
10512 PIPE_CONF_CHECK_I(cpu_transcoder
);
10514 PIPE_CONF_CHECK_I(has_pch_encoder
);
10515 PIPE_CONF_CHECK_I(fdi_lanes
);
10516 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_m
);
10517 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_n
);
10518 PIPE_CONF_CHECK_I(fdi_m_n
.link_m
);
10519 PIPE_CONF_CHECK_I(fdi_m_n
.link_n
);
10520 PIPE_CONF_CHECK_I(fdi_m_n
.tu
);
10522 PIPE_CONF_CHECK_I(has_dp_encoder
);
10524 if (INTEL_INFO(dev
)->gen
< 8) {
10525 PIPE_CONF_CHECK_I(dp_m_n
.gmch_m
);
10526 PIPE_CONF_CHECK_I(dp_m_n
.gmch_n
);
10527 PIPE_CONF_CHECK_I(dp_m_n
.link_m
);
10528 PIPE_CONF_CHECK_I(dp_m_n
.link_n
);
10529 PIPE_CONF_CHECK_I(dp_m_n
.tu
);
10531 if (current_config
->has_drrs
) {
10532 PIPE_CONF_CHECK_I(dp_m2_n2
.gmch_m
);
10533 PIPE_CONF_CHECK_I(dp_m2_n2
.gmch_n
);
10534 PIPE_CONF_CHECK_I(dp_m2_n2
.link_m
);
10535 PIPE_CONF_CHECK_I(dp_m2_n2
.link_n
);
10536 PIPE_CONF_CHECK_I(dp_m2_n2
.tu
);
10539 PIPE_CONF_CHECK_I_ALT(dp_m_n
.gmch_m
, dp_m2_n2
.gmch_m
);
10540 PIPE_CONF_CHECK_I_ALT(dp_m_n
.gmch_n
, dp_m2_n2
.gmch_n
);
10541 PIPE_CONF_CHECK_I_ALT(dp_m_n
.link_m
, dp_m2_n2
.link_m
);
10542 PIPE_CONF_CHECK_I_ALT(dp_m_n
.link_n
, dp_m2_n2
.link_n
);
10543 PIPE_CONF_CHECK_I_ALT(dp_m_n
.tu
, dp_m2_n2
.tu
);
10546 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hdisplay
);
10547 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_htotal
);
10548 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hblank_start
);
10549 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hblank_end
);
10550 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hsync_start
);
10551 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hsync_end
);
10553 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vdisplay
);
10554 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vtotal
);
10555 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vblank_start
);
10556 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vblank_end
);
10557 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vsync_start
);
10558 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vsync_end
);
10560 PIPE_CONF_CHECK_I(pixel_multiplier
);
10561 PIPE_CONF_CHECK_I(has_hdmi_sink
);
10562 if ((INTEL_INFO(dev
)->gen
< 8 && !IS_HASWELL(dev
)) ||
10563 IS_VALLEYVIEW(dev
))
10564 PIPE_CONF_CHECK_I(limited_color_range
);
10566 PIPE_CONF_CHECK_I(has_audio
);
10568 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10569 DRM_MODE_FLAG_INTERLACE
);
10571 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
10572 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10573 DRM_MODE_FLAG_PHSYNC
);
10574 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10575 DRM_MODE_FLAG_NHSYNC
);
10576 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10577 DRM_MODE_FLAG_PVSYNC
);
10578 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10579 DRM_MODE_FLAG_NVSYNC
);
10582 PIPE_CONF_CHECK_I(pipe_src_w
);
10583 PIPE_CONF_CHECK_I(pipe_src_h
);
10586 * FIXME: BIOS likes to set up a cloned config with lvds+external
10587 * screen. Since we don't yet re-compute the pipe config when moving
10588 * just the lvds port away to another pipe the sw tracking won't match.
10590 * Proper atomic modesets with recomputed global state will fix this.
10591 * Until then just don't check gmch state for inherited modes.
10593 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE
)) {
10594 PIPE_CONF_CHECK_I(gmch_pfit
.control
);
10595 /* pfit ratios are autocomputed by the hw on gen4+ */
10596 if (INTEL_INFO(dev
)->gen
< 4)
10597 PIPE_CONF_CHECK_I(gmch_pfit
.pgm_ratios
);
10598 PIPE_CONF_CHECK_I(gmch_pfit
.lvds_border_bits
);
10601 PIPE_CONF_CHECK_I(pch_pfit
.enabled
);
10602 if (current_config
->pch_pfit
.enabled
) {
10603 PIPE_CONF_CHECK_I(pch_pfit
.pos
);
10604 PIPE_CONF_CHECK_I(pch_pfit
.size
);
10607 /* BDW+ don't expose a synchronous way to read the state */
10608 if (IS_HASWELL(dev
))
10609 PIPE_CONF_CHECK_I(ips_enabled
);
10611 PIPE_CONF_CHECK_I(double_wide
);
10613 PIPE_CONF_CHECK_X(ddi_pll_sel
);
10615 PIPE_CONF_CHECK_I(shared_dpll
);
10616 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll
);
10617 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll_md
);
10618 PIPE_CONF_CHECK_X(dpll_hw_state
.fp0
);
10619 PIPE_CONF_CHECK_X(dpll_hw_state
.fp1
);
10620 PIPE_CONF_CHECK_X(dpll_hw_state
.wrpll
);
10622 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5)
10623 PIPE_CONF_CHECK_I(pipe_bpp
);
10625 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode
.crtc_clock
);
10626 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock
);
10628 #undef PIPE_CONF_CHECK_X
10629 #undef PIPE_CONF_CHECK_I
10630 #undef PIPE_CONF_CHECK_I_ALT
10631 #undef PIPE_CONF_CHECK_FLAGS
10632 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10633 #undef PIPE_CONF_QUIRK
10639 check_connector_state(struct drm_device
*dev
)
10641 struct intel_connector
*connector
;
10643 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10645 /* This also checks the encoder/connector hw state with the
10646 * ->get_hw_state callbacks. */
10647 intel_connector_check_state(connector
);
10649 WARN(&connector
->new_encoder
->base
!= connector
->base
.encoder
,
10650 "connector's staged encoder doesn't match current encoder\n");
10655 check_encoder_state(struct drm_device
*dev
)
10657 struct intel_encoder
*encoder
;
10658 struct intel_connector
*connector
;
10660 for_each_intel_encoder(dev
, encoder
) {
10661 bool enabled
= false;
10662 bool active
= false;
10663 enum pipe pipe
, tracked_pipe
;
10665 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10666 encoder
->base
.base
.id
,
10667 encoder
->base
.name
);
10669 WARN(&encoder
->new_crtc
->base
!= encoder
->base
.crtc
,
10670 "encoder's stage crtc doesn't match current crtc\n");
10671 WARN(encoder
->connectors_active
&& !encoder
->base
.crtc
,
10672 "encoder's active_connectors set, but no crtc\n");
10674 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10676 if (connector
->base
.encoder
!= &encoder
->base
)
10679 if (connector
->base
.dpms
!= DRM_MODE_DPMS_OFF
)
10683 * for MST connectors if we unplug the connector is gone
10684 * away but the encoder is still connected to a crtc
10685 * until a modeset happens in response to the hotplug.
10687 if (!enabled
&& encoder
->base
.encoder_type
== DRM_MODE_ENCODER_DPMST
)
10690 WARN(!!encoder
->base
.crtc
!= enabled
,
10691 "encoder's enabled state mismatch "
10692 "(expected %i, found %i)\n",
10693 !!encoder
->base
.crtc
, enabled
);
10694 WARN(active
&& !encoder
->base
.crtc
,
10695 "active encoder with no crtc\n");
10697 WARN(encoder
->connectors_active
!= active
,
10698 "encoder's computed active state doesn't match tracked active state "
10699 "(expected %i, found %i)\n", active
, encoder
->connectors_active
);
10701 active
= encoder
->get_hw_state(encoder
, &pipe
);
10702 WARN(active
!= encoder
->connectors_active
,
10703 "encoder's hw state doesn't match sw tracking "
10704 "(expected %i, found %i)\n",
10705 encoder
->connectors_active
, active
);
10707 if (!encoder
->base
.crtc
)
10710 tracked_pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
10711 WARN(active
&& pipe
!= tracked_pipe
,
10712 "active encoder's pipe doesn't match"
10713 "(expected %i, found %i)\n",
10714 tracked_pipe
, pipe
);
10720 check_crtc_state(struct drm_device
*dev
)
10722 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10723 struct intel_crtc
*crtc
;
10724 struct intel_encoder
*encoder
;
10725 struct intel_crtc_config pipe_config
;
10727 for_each_intel_crtc(dev
, crtc
) {
10728 bool enabled
= false;
10729 bool active
= false;
10731 memset(&pipe_config
, 0, sizeof(pipe_config
));
10733 DRM_DEBUG_KMS("[CRTC:%d]\n",
10734 crtc
->base
.base
.id
);
10736 WARN(crtc
->active
&& !crtc
->base
.enabled
,
10737 "active crtc, but not enabled in sw tracking\n");
10739 for_each_intel_encoder(dev
, encoder
) {
10740 if (encoder
->base
.crtc
!= &crtc
->base
)
10743 if (encoder
->connectors_active
)
10747 WARN(active
!= crtc
->active
,
10748 "crtc's computed active state doesn't match tracked active state "
10749 "(expected %i, found %i)\n", active
, crtc
->active
);
10750 WARN(enabled
!= crtc
->base
.enabled
,
10751 "crtc's computed enabled state doesn't match tracked enabled state "
10752 "(expected %i, found %i)\n", enabled
, crtc
->base
.enabled
);
10754 active
= dev_priv
->display
.get_pipe_config(crtc
,
10757 /* hw state is inconsistent with the pipe A quirk */
10758 if (crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
10759 active
= crtc
->active
;
10761 for_each_intel_encoder(dev
, encoder
) {
10763 if (encoder
->base
.crtc
!= &crtc
->base
)
10765 if (encoder
->get_hw_state(encoder
, &pipe
))
10766 encoder
->get_config(encoder
, &pipe_config
);
10769 WARN(crtc
->active
!= active
,
10770 "crtc active state doesn't match with hw state "
10771 "(expected %i, found %i)\n", crtc
->active
, active
);
10774 !intel_pipe_config_compare(dev
, &crtc
->config
, &pipe_config
)) {
10775 WARN(1, "pipe state doesn't match!\n");
10776 intel_dump_pipe_config(crtc
, &pipe_config
,
10778 intel_dump_pipe_config(crtc
, &crtc
->config
,
10785 check_shared_dpll_state(struct drm_device
*dev
)
10787 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10788 struct intel_crtc
*crtc
;
10789 struct intel_dpll_hw_state dpll_hw_state
;
10792 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
10793 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
10794 int enabled_crtcs
= 0, active_crtcs
= 0;
10797 memset(&dpll_hw_state
, 0, sizeof(dpll_hw_state
));
10799 DRM_DEBUG_KMS("%s\n", pll
->name
);
10801 active
= pll
->get_hw_state(dev_priv
, pll
, &dpll_hw_state
);
10803 WARN(pll
->active
> pll
->refcount
,
10804 "more active pll users than references: %i vs %i\n",
10805 pll
->active
, pll
->refcount
);
10806 WARN(pll
->active
&& !pll
->on
,
10807 "pll in active use but not on in sw tracking\n");
10808 WARN(pll
->on
&& !pll
->active
,
10809 "pll in on but not on in use in sw tracking\n");
10810 WARN(pll
->on
!= active
,
10811 "pll on state mismatch (expected %i, found %i)\n",
10814 for_each_intel_crtc(dev
, crtc
) {
10815 if (crtc
->base
.enabled
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
10817 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
10820 WARN(pll
->active
!= active_crtcs
,
10821 "pll active crtcs mismatch (expected %i, found %i)\n",
10822 pll
->active
, active_crtcs
);
10823 WARN(pll
->refcount
!= enabled_crtcs
,
10824 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10825 pll
->refcount
, enabled_crtcs
);
10827 WARN(pll
->on
&& memcmp(&pll
->hw_state
, &dpll_hw_state
,
10828 sizeof(dpll_hw_state
)),
10829 "pll hw state mismatch\n");
10834 intel_modeset_check_state(struct drm_device
*dev
)
10836 check_connector_state(dev
);
10837 check_encoder_state(dev
);
10838 check_crtc_state(dev
);
10839 check_shared_dpll_state(dev
);
10842 void ironlake_check_encoder_dotclock(const struct intel_crtc_config
*pipe_config
,
10846 * FDI already provided one idea for the dotclock.
10847 * Yell if the encoder disagrees.
10849 WARN(!intel_fuzzy_clock_check(pipe_config
->adjusted_mode
.crtc_clock
, dotclock
),
10850 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10851 pipe_config
->adjusted_mode
.crtc_clock
, dotclock
);
10854 static void update_scanline_offset(struct intel_crtc
*crtc
)
10856 struct drm_device
*dev
= crtc
->base
.dev
;
10859 * The scanline counter increments at the leading edge of hsync.
10861 * On most platforms it starts counting from vtotal-1 on the
10862 * first active line. That means the scanline counter value is
10863 * always one less than what we would expect. Ie. just after
10864 * start of vblank, which also occurs at start of hsync (on the
10865 * last active line), the scanline counter will read vblank_start-1.
10867 * On gen2 the scanline counter starts counting from 1 instead
10868 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10869 * to keep the value positive), instead of adding one.
10871 * On HSW+ the behaviour of the scanline counter depends on the output
10872 * type. For DP ports it behaves like most other platforms, but on HDMI
10873 * there's an extra 1 line difference. So we need to add two instead of
10874 * one to the value.
10876 if (IS_GEN2(dev
)) {
10877 const struct drm_display_mode
*mode
= &crtc
->config
.adjusted_mode
;
10880 vtotal
= mode
->crtc_vtotal
;
10881 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
10884 crtc
->scanline_offset
= vtotal
- 1;
10885 } else if (HAS_DDI(dev
) &&
10886 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
)) {
10887 crtc
->scanline_offset
= 2;
10889 crtc
->scanline_offset
= 1;
10892 static int __intel_set_mode(struct drm_crtc
*crtc
,
10893 struct drm_display_mode
*mode
,
10894 int x
, int y
, struct drm_framebuffer
*fb
)
10896 struct drm_device
*dev
= crtc
->dev
;
10897 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10898 struct drm_display_mode
*saved_mode
;
10899 struct intel_crtc_config
*pipe_config
= NULL
;
10900 struct intel_crtc
*intel_crtc
;
10901 unsigned disable_pipes
, prepare_pipes
, modeset_pipes
;
10904 saved_mode
= kmalloc(sizeof(*saved_mode
), GFP_KERNEL
);
10908 intel_modeset_affected_pipes(crtc
, &modeset_pipes
,
10909 &prepare_pipes
, &disable_pipes
);
10911 *saved_mode
= crtc
->mode
;
10913 /* Hack: Because we don't (yet) support global modeset on multiple
10914 * crtcs, we don't keep track of the new mode for more than one crtc.
10915 * Hence simply check whether any bit is set in modeset_pipes in all the
10916 * pieces of code that are not yet converted to deal with mutliple crtcs
10917 * changing their mode at the same time. */
10918 if (modeset_pipes
) {
10919 pipe_config
= intel_modeset_pipe_config(crtc
, fb
, mode
);
10920 if (IS_ERR(pipe_config
)) {
10921 ret
= PTR_ERR(pipe_config
);
10922 pipe_config
= NULL
;
10926 intel_dump_pipe_config(to_intel_crtc(crtc
), pipe_config
,
10928 to_intel_crtc(crtc
)->new_config
= pipe_config
;
10932 * See if the config requires any additional preparation, e.g.
10933 * to adjust global state with pipes off. We need to do this
10934 * here so we can get the modeset_pipe updated config for the new
10935 * mode set on this crtc. For other crtcs we need to use the
10936 * adjusted_mode bits in the crtc directly.
10938 if (IS_VALLEYVIEW(dev
)) {
10939 valleyview_modeset_global_pipes(dev
, &prepare_pipes
);
10941 /* may have added more to prepare_pipes than we should */
10942 prepare_pipes
&= ~disable_pipes
;
10945 for_each_intel_crtc_masked(dev
, disable_pipes
, intel_crtc
)
10946 intel_crtc_disable(&intel_crtc
->base
);
10948 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
10949 if (intel_crtc
->base
.enabled
)
10950 dev_priv
->display
.crtc_disable(&intel_crtc
->base
);
10953 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10954 * to set it here already despite that we pass it down the callchain.
10956 if (modeset_pipes
) {
10957 crtc
->mode
= *mode
;
10958 /* mode_set/enable/disable functions rely on a correct pipe
10960 to_intel_crtc(crtc
)->config
= *pipe_config
;
10961 to_intel_crtc(crtc
)->new_config
= &to_intel_crtc(crtc
)->config
;
10964 * Calculate and store various constants which
10965 * are later needed by vblank and swap-completion
10966 * timestamping. They are derived from true hwmode.
10968 drm_calc_timestamping_constants(crtc
,
10969 &pipe_config
->adjusted_mode
);
10972 /* Only after disabling all output pipelines that will be changed can we
10973 * update the the output configuration. */
10974 intel_modeset_update_state(dev
, prepare_pipes
);
10976 if (dev_priv
->display
.modeset_global_resources
)
10977 dev_priv
->display
.modeset_global_resources(dev
);
10979 /* Set up the DPLL and any encoders state that needs to adjust or depend
10982 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
10983 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
10984 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(old_fb
);
10985 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
10987 mutex_lock(&dev
->struct_mutex
);
10988 ret
= intel_pin_and_fence_fb_obj(dev
,
10992 DRM_ERROR("pin & fence failed\n");
10993 mutex_unlock(&dev
->struct_mutex
);
10997 intel_unpin_fb_obj(old_obj
);
10998 i915_gem_track_fb(old_obj
, obj
,
10999 INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
));
11000 mutex_unlock(&dev
->struct_mutex
);
11002 crtc
->primary
->fb
= fb
;
11006 ret
= dev_priv
->display
.crtc_mode_set(&intel_crtc
->base
,
11012 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11013 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
11014 update_scanline_offset(intel_crtc
);
11016 dev_priv
->display
.crtc_enable(&intel_crtc
->base
);
11019 /* FIXME: add subpixel order */
11021 if (ret
&& crtc
->enabled
)
11022 crtc
->mode
= *saved_mode
;
11025 kfree(pipe_config
);
11030 static int intel_set_mode(struct drm_crtc
*crtc
,
11031 struct drm_display_mode
*mode
,
11032 int x
, int y
, struct drm_framebuffer
*fb
)
11036 ret
= __intel_set_mode(crtc
, mode
, x
, y
, fb
);
11039 intel_modeset_check_state(crtc
->dev
);
11044 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
11046 intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
, crtc
->primary
->fb
);
11049 #undef for_each_intel_crtc_masked
11051 static void intel_set_config_free(struct intel_set_config
*config
)
11056 kfree(config
->save_connector_encoders
);
11057 kfree(config
->save_encoder_crtcs
);
11058 kfree(config
->save_crtc_enabled
);
11062 static int intel_set_config_save_state(struct drm_device
*dev
,
11063 struct intel_set_config
*config
)
11065 struct drm_crtc
*crtc
;
11066 struct drm_encoder
*encoder
;
11067 struct drm_connector
*connector
;
11070 config
->save_crtc_enabled
=
11071 kcalloc(dev
->mode_config
.num_crtc
,
11072 sizeof(bool), GFP_KERNEL
);
11073 if (!config
->save_crtc_enabled
)
11076 config
->save_encoder_crtcs
=
11077 kcalloc(dev
->mode_config
.num_encoder
,
11078 sizeof(struct drm_crtc
*), GFP_KERNEL
);
11079 if (!config
->save_encoder_crtcs
)
11082 config
->save_connector_encoders
=
11083 kcalloc(dev
->mode_config
.num_connector
,
11084 sizeof(struct drm_encoder
*), GFP_KERNEL
);
11085 if (!config
->save_connector_encoders
)
11088 /* Copy data. Note that driver private data is not affected.
11089 * Should anything bad happen only the expected state is
11090 * restored, not the drivers personal bookkeeping.
11093 for_each_crtc(dev
, crtc
) {
11094 config
->save_crtc_enabled
[count
++] = crtc
->enabled
;
11098 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
11099 config
->save_encoder_crtcs
[count
++] = encoder
->crtc
;
11103 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
11104 config
->save_connector_encoders
[count
++] = connector
->encoder
;
11110 static void intel_set_config_restore_state(struct drm_device
*dev
,
11111 struct intel_set_config
*config
)
11113 struct intel_crtc
*crtc
;
11114 struct intel_encoder
*encoder
;
11115 struct intel_connector
*connector
;
11119 for_each_intel_crtc(dev
, crtc
) {
11120 crtc
->new_enabled
= config
->save_crtc_enabled
[count
++];
11122 if (crtc
->new_enabled
)
11123 crtc
->new_config
= &crtc
->config
;
11125 crtc
->new_config
= NULL
;
11129 for_each_intel_encoder(dev
, encoder
) {
11130 encoder
->new_crtc
=
11131 to_intel_crtc(config
->save_encoder_crtcs
[count
++]);
11135 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
11136 connector
->new_encoder
=
11137 to_intel_encoder(config
->save_connector_encoders
[count
++]);
11142 is_crtc_connector_off(struct drm_mode_set
*set
)
11146 if (set
->num_connectors
== 0)
11149 if (WARN_ON(set
->connectors
== NULL
))
11152 for (i
= 0; i
< set
->num_connectors
; i
++)
11153 if (set
->connectors
[i
]->encoder
&&
11154 set
->connectors
[i
]->encoder
->crtc
== set
->crtc
&&
11155 set
->connectors
[i
]->dpms
!= DRM_MODE_DPMS_ON
)
11162 intel_set_config_compute_mode_changes(struct drm_mode_set
*set
,
11163 struct intel_set_config
*config
)
11166 /* We should be able to check here if the fb has the same properties
11167 * and then just flip_or_move it */
11168 if (is_crtc_connector_off(set
)) {
11169 config
->mode_changed
= true;
11170 } else if (set
->crtc
->primary
->fb
!= set
->fb
) {
11172 * If we have no fb, we can only flip as long as the crtc is
11173 * active, otherwise we need a full mode set. The crtc may
11174 * be active if we've only disabled the primary plane, or
11175 * in fastboot situations.
11177 if (set
->crtc
->primary
->fb
== NULL
) {
11178 struct intel_crtc
*intel_crtc
=
11179 to_intel_crtc(set
->crtc
);
11181 if (intel_crtc
->active
) {
11182 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11183 config
->fb_changed
= true;
11185 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11186 config
->mode_changed
= true;
11188 } else if (set
->fb
== NULL
) {
11189 config
->mode_changed
= true;
11190 } else if (set
->fb
->pixel_format
!=
11191 set
->crtc
->primary
->fb
->pixel_format
) {
11192 config
->mode_changed
= true;
11194 config
->fb_changed
= true;
11198 if (set
->fb
&& (set
->x
!= set
->crtc
->x
|| set
->y
!= set
->crtc
->y
))
11199 config
->fb_changed
= true;
11201 if (set
->mode
&& !drm_mode_equal(set
->mode
, &set
->crtc
->mode
)) {
11202 DRM_DEBUG_KMS("modes are different, full mode set\n");
11203 drm_mode_debug_printmodeline(&set
->crtc
->mode
);
11204 drm_mode_debug_printmodeline(set
->mode
);
11205 config
->mode_changed
= true;
11208 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11209 set
->crtc
->base
.id
, config
->mode_changed
, config
->fb_changed
);
11213 intel_modeset_stage_output_state(struct drm_device
*dev
,
11214 struct drm_mode_set
*set
,
11215 struct intel_set_config
*config
)
11217 struct intel_connector
*connector
;
11218 struct intel_encoder
*encoder
;
11219 struct intel_crtc
*crtc
;
11222 /* The upper layers ensure that we either disable a crtc or have a list
11223 * of connectors. For paranoia, double-check this. */
11224 WARN_ON(!set
->fb
&& (set
->num_connectors
!= 0));
11225 WARN_ON(set
->fb
&& (set
->num_connectors
== 0));
11227 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
11229 /* Otherwise traverse passed in connector list and get encoders
11231 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
11232 if (set
->connectors
[ro
] == &connector
->base
) {
11233 connector
->new_encoder
= intel_find_encoder(connector
, to_intel_crtc(set
->crtc
)->pipe
);
11238 /* If we disable the crtc, disable all its connectors. Also, if
11239 * the connector is on the changing crtc but not on the new
11240 * connector list, disable it. */
11241 if ((!set
->fb
|| ro
== set
->num_connectors
) &&
11242 connector
->base
.encoder
&&
11243 connector
->base
.encoder
->crtc
== set
->crtc
) {
11244 connector
->new_encoder
= NULL
;
11246 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11247 connector
->base
.base
.id
,
11248 connector
->base
.name
);
11252 if (&connector
->new_encoder
->base
!= connector
->base
.encoder
) {
11253 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11254 config
->mode_changed
= true;
11257 /* connector->new_encoder is now updated for all connectors. */
11259 /* Update crtc of enabled connectors. */
11260 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
11262 struct drm_crtc
*new_crtc
;
11264 if (!connector
->new_encoder
)
11267 new_crtc
= connector
->new_encoder
->base
.crtc
;
11269 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
11270 if (set
->connectors
[ro
] == &connector
->base
)
11271 new_crtc
= set
->crtc
;
11274 /* Make sure the new CRTC will work with the encoder */
11275 if (!drm_encoder_crtc_ok(&connector
->new_encoder
->base
,
11279 connector
->new_encoder
->new_crtc
= to_intel_crtc(new_crtc
);
11281 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11282 connector
->base
.base
.id
,
11283 connector
->base
.name
,
11284 new_crtc
->base
.id
);
11287 /* Check for any encoders that needs to be disabled. */
11288 for_each_intel_encoder(dev
, encoder
) {
11289 int num_connectors
= 0;
11290 list_for_each_entry(connector
,
11291 &dev
->mode_config
.connector_list
,
11293 if (connector
->new_encoder
== encoder
) {
11294 WARN_ON(!connector
->new_encoder
->new_crtc
);
11299 if (num_connectors
== 0)
11300 encoder
->new_crtc
= NULL
;
11301 else if (num_connectors
> 1)
11304 /* Only now check for crtc changes so we don't miss encoders
11305 * that will be disabled. */
11306 if (&encoder
->new_crtc
->base
!= encoder
->base
.crtc
) {
11307 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11308 config
->mode_changed
= true;
11311 /* Now we've also updated encoder->new_crtc for all encoders. */
11312 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
11314 if (connector
->new_encoder
)
11315 if (connector
->new_encoder
!= connector
->encoder
)
11316 connector
->encoder
= connector
->new_encoder
;
11318 for_each_intel_crtc(dev
, crtc
) {
11319 crtc
->new_enabled
= false;
11321 for_each_intel_encoder(dev
, encoder
) {
11322 if (encoder
->new_crtc
== crtc
) {
11323 crtc
->new_enabled
= true;
11328 if (crtc
->new_enabled
!= crtc
->base
.enabled
) {
11329 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11330 crtc
->new_enabled
? "en" : "dis");
11331 config
->mode_changed
= true;
11334 if (crtc
->new_enabled
)
11335 crtc
->new_config
= &crtc
->config
;
11337 crtc
->new_config
= NULL
;
11343 static void disable_crtc_nofb(struct intel_crtc
*crtc
)
11345 struct drm_device
*dev
= crtc
->base
.dev
;
11346 struct intel_encoder
*encoder
;
11347 struct intel_connector
*connector
;
11349 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11350 pipe_name(crtc
->pipe
));
11352 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
11353 if (connector
->new_encoder
&&
11354 connector
->new_encoder
->new_crtc
== crtc
)
11355 connector
->new_encoder
= NULL
;
11358 for_each_intel_encoder(dev
, encoder
) {
11359 if (encoder
->new_crtc
== crtc
)
11360 encoder
->new_crtc
= NULL
;
11363 crtc
->new_enabled
= false;
11364 crtc
->new_config
= NULL
;
11367 static int intel_crtc_set_config(struct drm_mode_set
*set
)
11369 struct drm_device
*dev
;
11370 struct drm_mode_set save_set
;
11371 struct intel_set_config
*config
;
11375 BUG_ON(!set
->crtc
);
11376 BUG_ON(!set
->crtc
->helper_private
);
11378 /* Enforce sane interface api - has been abused by the fb helper. */
11379 BUG_ON(!set
->mode
&& set
->fb
);
11380 BUG_ON(set
->fb
&& set
->num_connectors
== 0);
11383 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11384 set
->crtc
->base
.id
, set
->fb
->base
.id
,
11385 (int)set
->num_connectors
, set
->x
, set
->y
);
11387 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set
->crtc
->base
.id
);
11390 dev
= set
->crtc
->dev
;
11393 config
= kzalloc(sizeof(*config
), GFP_KERNEL
);
11397 ret
= intel_set_config_save_state(dev
, config
);
11401 save_set
.crtc
= set
->crtc
;
11402 save_set
.mode
= &set
->crtc
->mode
;
11403 save_set
.x
= set
->crtc
->x
;
11404 save_set
.y
= set
->crtc
->y
;
11405 save_set
.fb
= set
->crtc
->primary
->fb
;
11407 /* Compute whether we need a full modeset, only an fb base update or no
11408 * change at all. In the future we might also check whether only the
11409 * mode changed, e.g. for LVDS where we only change the panel fitter in
11411 intel_set_config_compute_mode_changes(set
, config
);
11413 ret
= intel_modeset_stage_output_state(dev
, set
, config
);
11417 if (config
->mode_changed
) {
11418 ret
= intel_set_mode(set
->crtc
, set
->mode
,
11419 set
->x
, set
->y
, set
->fb
);
11420 } else if (config
->fb_changed
) {
11421 struct intel_crtc
*intel_crtc
= to_intel_crtc(set
->crtc
);
11423 intel_crtc_wait_for_pending_flips(set
->crtc
);
11425 ret
= intel_pipe_set_base(set
->crtc
,
11426 set
->x
, set
->y
, set
->fb
);
11429 * We need to make sure the primary plane is re-enabled if it
11430 * has previously been turned off.
11432 if (!intel_crtc
->primary_enabled
&& ret
== 0) {
11433 WARN_ON(!intel_crtc
->active
);
11434 intel_enable_primary_hw_plane(set
->crtc
->primary
, set
->crtc
);
11438 * In the fastboot case this may be our only check of the
11439 * state after boot. It would be better to only do it on
11440 * the first update, but we don't have a nice way of doing that
11441 * (and really, set_config isn't used much for high freq page
11442 * flipping, so increasing its cost here shouldn't be a big
11445 if (i915
.fastboot
&& ret
== 0)
11446 intel_modeset_check_state(set
->crtc
->dev
);
11450 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11451 set
->crtc
->base
.id
, ret
);
11453 intel_set_config_restore_state(dev
, config
);
11456 * HACK: if the pipe was on, but we didn't have a framebuffer,
11457 * force the pipe off to avoid oopsing in the modeset code
11458 * due to fb==NULL. This should only happen during boot since
11459 * we don't yet reconstruct the FB from the hardware state.
11461 if (to_intel_crtc(save_set
.crtc
)->new_enabled
&& !save_set
.fb
)
11462 disable_crtc_nofb(to_intel_crtc(save_set
.crtc
));
11464 /* Try to restore the config */
11465 if (config
->mode_changed
&&
11466 intel_set_mode(save_set
.crtc
, save_set
.mode
,
11467 save_set
.x
, save_set
.y
, save_set
.fb
))
11468 DRM_ERROR("failed to restore config after modeset failure\n");
11472 intel_set_config_free(config
);
11476 static const struct drm_crtc_funcs intel_crtc_funcs
= {
11477 .gamma_set
= intel_crtc_gamma_set
,
11478 .set_config
= intel_crtc_set_config
,
11479 .destroy
= intel_crtc_destroy
,
11480 .page_flip
= intel_crtc_page_flip
,
11483 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private
*dev_priv
,
11484 struct intel_shared_dpll
*pll
,
11485 struct intel_dpll_hw_state
*hw_state
)
11489 if (!intel_display_power_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
11492 val
= I915_READ(PCH_DPLL(pll
->id
));
11493 hw_state
->dpll
= val
;
11494 hw_state
->fp0
= I915_READ(PCH_FP0(pll
->id
));
11495 hw_state
->fp1
= I915_READ(PCH_FP1(pll
->id
));
11497 return val
& DPLL_VCO_ENABLE
;
11500 static void ibx_pch_dpll_mode_set(struct drm_i915_private
*dev_priv
,
11501 struct intel_shared_dpll
*pll
)
11503 I915_WRITE(PCH_FP0(pll
->id
), pll
->hw_state
.fp0
);
11504 I915_WRITE(PCH_FP1(pll
->id
), pll
->hw_state
.fp1
);
11507 static void ibx_pch_dpll_enable(struct drm_i915_private
*dev_priv
,
11508 struct intel_shared_dpll
*pll
)
11510 /* PCH refclock must be enabled first */
11511 ibx_assert_pch_refclk_enabled(dev_priv
);
11513 I915_WRITE(PCH_DPLL(pll
->id
), pll
->hw_state
.dpll
);
11515 /* Wait for the clocks to stabilize. */
11516 POSTING_READ(PCH_DPLL(pll
->id
));
11519 /* The pixel multiplier can only be updated once the
11520 * DPLL is enabled and the clocks are stable.
11522 * So write it again.
11524 I915_WRITE(PCH_DPLL(pll
->id
), pll
->hw_state
.dpll
);
11525 POSTING_READ(PCH_DPLL(pll
->id
));
11529 static void ibx_pch_dpll_disable(struct drm_i915_private
*dev_priv
,
11530 struct intel_shared_dpll
*pll
)
11532 struct drm_device
*dev
= dev_priv
->dev
;
11533 struct intel_crtc
*crtc
;
11535 /* Make sure no transcoder isn't still depending on us. */
11536 for_each_intel_crtc(dev
, crtc
) {
11537 if (intel_crtc_to_shared_dpll(crtc
) == pll
)
11538 assert_pch_transcoder_disabled(dev_priv
, crtc
->pipe
);
11541 I915_WRITE(PCH_DPLL(pll
->id
), 0);
11542 POSTING_READ(PCH_DPLL(pll
->id
));
11546 static char *ibx_pch_dpll_names
[] = {
11551 static void ibx_pch_dpll_init(struct drm_device
*dev
)
11553 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11556 dev_priv
->num_shared_dpll
= 2;
11558 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
11559 dev_priv
->shared_dplls
[i
].id
= i
;
11560 dev_priv
->shared_dplls
[i
].name
= ibx_pch_dpll_names
[i
];
11561 dev_priv
->shared_dplls
[i
].mode_set
= ibx_pch_dpll_mode_set
;
11562 dev_priv
->shared_dplls
[i
].enable
= ibx_pch_dpll_enable
;
11563 dev_priv
->shared_dplls
[i
].disable
= ibx_pch_dpll_disable
;
11564 dev_priv
->shared_dplls
[i
].get_hw_state
=
11565 ibx_pch_dpll_get_hw_state
;
11569 static void intel_shared_dpll_init(struct drm_device
*dev
)
11571 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11574 intel_ddi_pll_init(dev
);
11575 else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
11576 ibx_pch_dpll_init(dev
);
11578 dev_priv
->num_shared_dpll
= 0;
11580 BUG_ON(dev_priv
->num_shared_dpll
> I915_NUM_PLLS
);
11584 intel_primary_plane_disable(struct drm_plane
*plane
)
11586 struct drm_device
*dev
= plane
->dev
;
11587 struct intel_crtc
*intel_crtc
;
11592 BUG_ON(!plane
->crtc
);
11594 intel_crtc
= to_intel_crtc(plane
->crtc
);
11597 * Even though we checked plane->fb above, it's still possible that
11598 * the primary plane has been implicitly disabled because the crtc
11599 * coordinates given weren't visible, or because we detected
11600 * that it was 100% covered by a sprite plane. Or, the CRTC may be
11601 * off and we've set a fb, but haven't actually turned on the CRTC yet.
11602 * In either case, we need to unpin the FB and let the fb pointer get
11603 * updated, but otherwise we don't need to touch the hardware.
11605 if (!intel_crtc
->primary_enabled
)
11606 goto disable_unpin
;
11608 intel_crtc_wait_for_pending_flips(plane
->crtc
);
11609 intel_disable_primary_hw_plane(plane
, plane
->crtc
);
11612 mutex_lock(&dev
->struct_mutex
);
11613 i915_gem_track_fb(intel_fb_obj(plane
->fb
), NULL
,
11614 INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
));
11615 intel_unpin_fb_obj(intel_fb_obj(plane
->fb
));
11616 mutex_unlock(&dev
->struct_mutex
);
11623 intel_primary_plane_setplane(struct drm_plane
*plane
, struct drm_crtc
*crtc
,
11624 struct drm_framebuffer
*fb
, int crtc_x
, int crtc_y
,
11625 unsigned int crtc_w
, unsigned int crtc_h
,
11626 uint32_t src_x
, uint32_t src_y
,
11627 uint32_t src_w
, uint32_t src_h
)
11629 struct drm_device
*dev
= crtc
->dev
;
11630 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11631 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11632 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
11633 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(plane
->fb
);
11634 struct drm_rect dest
= {
11635 /* integer pixels */
11638 .x2
= crtc_x
+ crtc_w
,
11639 .y2
= crtc_y
+ crtc_h
,
11641 struct drm_rect src
= {
11642 /* 16.16 fixed point */
11645 .x2
= src_x
+ src_w
,
11646 .y2
= src_y
+ src_h
,
11648 const struct drm_rect clip
= {
11649 /* integer pixels */
11650 .x2
= intel_crtc
->active
? intel_crtc
->config
.pipe_src_w
: 0,
11651 .y2
= intel_crtc
->active
? intel_crtc
->config
.pipe_src_h
: 0,
11654 int crtc_x
, crtc_y
;
11655 unsigned int crtc_w
, crtc_h
;
11656 uint32_t src_x
, src_y
, src_w
, src_h
;
11667 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
11671 ret
= drm_plane_helper_check_update(plane
, crtc
, fb
,
11672 &src
, &dest
, &clip
,
11673 DRM_PLANE_HELPER_NO_SCALING
,
11674 DRM_PLANE_HELPER_NO_SCALING
,
11675 false, true, &visible
);
11681 * If the CRTC isn't enabled, we're just pinning the framebuffer,
11682 * updating the fb pointer, and returning without touching the
11683 * hardware. This allows us to later do a drmModeSetCrtc with fb=-1 to
11684 * turn on the display with all planes setup as desired.
11686 if (!crtc
->enabled
) {
11687 mutex_lock(&dev
->struct_mutex
);
11690 * If we already called setplane while the crtc was disabled,
11691 * we may have an fb pinned; unpin it.
11694 intel_unpin_fb_obj(old_obj
);
11696 i915_gem_track_fb(old_obj
, obj
,
11697 INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
));
11699 /* Pin and return without programming hardware */
11700 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, NULL
);
11701 mutex_unlock(&dev
->struct_mutex
);
11706 intel_crtc_wait_for_pending_flips(crtc
);
11709 * If clipping results in a non-visible primary plane, we'll disable
11710 * the primary plane. Note that this is a bit different than what
11711 * happens if userspace explicitly disables the plane by passing fb=0
11712 * because plane->fb still gets set and pinned.
11715 mutex_lock(&dev
->struct_mutex
);
11718 * Try to pin the new fb first so that we can bail out if we
11721 if (plane
->fb
!= fb
) {
11722 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, NULL
);
11724 mutex_unlock(&dev
->struct_mutex
);
11729 i915_gem_track_fb(old_obj
, obj
,
11730 INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
));
11732 if (intel_crtc
->primary_enabled
)
11733 intel_disable_primary_hw_plane(plane
, crtc
);
11736 if (plane
->fb
!= fb
)
11738 intel_unpin_fb_obj(old_obj
);
11740 mutex_unlock(&dev
->struct_mutex
);
11743 if (intel_crtc
&& intel_crtc
->active
&&
11744 intel_crtc
->primary_enabled
) {
11746 * FBC does not work on some platforms for rotated
11747 * planes, so disable it when rotation is not 0 and
11748 * update it when rotation is set back to 0.
11750 * FIXME: This is redundant with the fbc update done in
11751 * the primary plane enable function except that that
11752 * one is done too late. We eventually need to unify
11755 if (INTEL_INFO(dev
)->gen
<= 4 && !IS_G4X(dev
) &&
11756 dev_priv
->fbc
.plane
== intel_crtc
->plane
&&
11757 intel_plane
->rotation
!= BIT(DRM_ROTATE_0
)) {
11758 intel_disable_fbc(dev
);
11761 ret
= intel_pipe_set_base(crtc
, src
.x1
, src
.y1
, fb
);
11765 if (!intel_crtc
->primary_enabled
)
11766 intel_enable_primary_hw_plane(plane
, crtc
);
11769 intel_plane
->crtc_x
= orig
.crtc_x
;
11770 intel_plane
->crtc_y
= orig
.crtc_y
;
11771 intel_plane
->crtc_w
= orig
.crtc_w
;
11772 intel_plane
->crtc_h
= orig
.crtc_h
;
11773 intel_plane
->src_x
= orig
.src_x
;
11774 intel_plane
->src_y
= orig
.src_y
;
11775 intel_plane
->src_w
= orig
.src_w
;
11776 intel_plane
->src_h
= orig
.src_h
;
11777 intel_plane
->obj
= obj
;
11782 /* Common destruction function for both primary and cursor planes */
11783 static void intel_plane_destroy(struct drm_plane
*plane
)
11785 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
11786 drm_plane_cleanup(plane
);
11787 kfree(intel_plane
);
11790 static const struct drm_plane_funcs intel_primary_plane_funcs
= {
11791 .update_plane
= intel_primary_plane_setplane
,
11792 .disable_plane
= intel_primary_plane_disable
,
11793 .destroy
= intel_plane_destroy
,
11794 .set_property
= intel_plane_set_property
11797 static struct drm_plane
*intel_primary_plane_create(struct drm_device
*dev
,
11800 struct intel_plane
*primary
;
11801 const uint32_t *intel_primary_formats
;
11804 primary
= kzalloc(sizeof(*primary
), GFP_KERNEL
);
11805 if (primary
== NULL
)
11808 primary
->can_scale
= false;
11809 primary
->max_downscale
= 1;
11810 primary
->pipe
= pipe
;
11811 primary
->plane
= pipe
;
11812 primary
->rotation
= BIT(DRM_ROTATE_0
);
11813 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4)
11814 primary
->plane
= !pipe
;
11816 if (INTEL_INFO(dev
)->gen
<= 3) {
11817 intel_primary_formats
= intel_primary_formats_gen2
;
11818 num_formats
= ARRAY_SIZE(intel_primary_formats_gen2
);
11820 intel_primary_formats
= intel_primary_formats_gen4
;
11821 num_formats
= ARRAY_SIZE(intel_primary_formats_gen4
);
11824 drm_universal_plane_init(dev
, &primary
->base
, 0,
11825 &intel_primary_plane_funcs
,
11826 intel_primary_formats
, num_formats
,
11827 DRM_PLANE_TYPE_PRIMARY
);
11829 if (INTEL_INFO(dev
)->gen
>= 4) {
11830 if (!dev
->mode_config
.rotation_property
)
11831 dev
->mode_config
.rotation_property
=
11832 drm_mode_create_rotation_property(dev
,
11833 BIT(DRM_ROTATE_0
) |
11834 BIT(DRM_ROTATE_180
));
11835 if (dev
->mode_config
.rotation_property
)
11836 drm_object_attach_property(&primary
->base
.base
,
11837 dev
->mode_config
.rotation_property
,
11838 primary
->rotation
);
11841 return &primary
->base
;
11845 intel_cursor_plane_disable(struct drm_plane
*plane
)
11850 BUG_ON(!plane
->crtc
);
11852 return intel_crtc_cursor_set_obj(plane
->crtc
, NULL
, 0, 0);
11856 intel_cursor_plane_update(struct drm_plane
*plane
, struct drm_crtc
*crtc
,
11857 struct drm_framebuffer
*fb
, int crtc_x
, int crtc_y
,
11858 unsigned int crtc_w
, unsigned int crtc_h
,
11859 uint32_t src_x
, uint32_t src_y
,
11860 uint32_t src_w
, uint32_t src_h
)
11862 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11863 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
11864 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
11865 struct drm_rect dest
= {
11866 /* integer pixels */
11869 .x2
= crtc_x
+ crtc_w
,
11870 .y2
= crtc_y
+ crtc_h
,
11872 struct drm_rect src
= {
11873 /* 16.16 fixed point */
11876 .x2
= src_x
+ src_w
,
11877 .y2
= src_y
+ src_h
,
11879 const struct drm_rect clip
= {
11880 /* integer pixels */
11881 .x2
= intel_crtc
->active
? intel_crtc
->config
.pipe_src_w
: 0,
11882 .y2
= intel_crtc
->active
? intel_crtc
->config
.pipe_src_h
: 0,
11887 ret
= drm_plane_helper_check_update(plane
, crtc
, fb
,
11888 &src
, &dest
, &clip
,
11889 DRM_PLANE_HELPER_NO_SCALING
,
11890 DRM_PLANE_HELPER_NO_SCALING
,
11891 true, true, &visible
);
11895 crtc
->cursor_x
= crtc_x
;
11896 crtc
->cursor_y
= crtc_y
;
11897 if (fb
!= crtc
->cursor
->fb
) {
11898 return intel_crtc_cursor_set_obj(crtc
, obj
, crtc_w
, crtc_h
);
11900 intel_crtc_update_cursor(crtc
, visible
);
11902 intel_frontbuffer_flip(crtc
->dev
,
11903 INTEL_FRONTBUFFER_CURSOR(intel_crtc
->pipe
));
11908 static const struct drm_plane_funcs intel_cursor_plane_funcs
= {
11909 .update_plane
= intel_cursor_plane_update
,
11910 .disable_plane
= intel_cursor_plane_disable
,
11911 .destroy
= intel_plane_destroy
,
11914 static struct drm_plane
*intel_cursor_plane_create(struct drm_device
*dev
,
11917 struct intel_plane
*cursor
;
11919 cursor
= kzalloc(sizeof(*cursor
), GFP_KERNEL
);
11920 if (cursor
== NULL
)
11923 cursor
->can_scale
= false;
11924 cursor
->max_downscale
= 1;
11925 cursor
->pipe
= pipe
;
11926 cursor
->plane
= pipe
;
11928 drm_universal_plane_init(dev
, &cursor
->base
, 0,
11929 &intel_cursor_plane_funcs
,
11930 intel_cursor_formats
,
11931 ARRAY_SIZE(intel_cursor_formats
),
11932 DRM_PLANE_TYPE_CURSOR
);
11933 return &cursor
->base
;
11936 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
11938 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11939 struct intel_crtc
*intel_crtc
;
11940 struct drm_plane
*primary
= NULL
;
11941 struct drm_plane
*cursor
= NULL
;
11944 intel_crtc
= kzalloc(sizeof(*intel_crtc
), GFP_KERNEL
);
11945 if (intel_crtc
== NULL
)
11948 primary
= intel_primary_plane_create(dev
, pipe
);
11952 cursor
= intel_cursor_plane_create(dev
, pipe
);
11956 ret
= drm_crtc_init_with_planes(dev
, &intel_crtc
->base
, primary
,
11957 cursor
, &intel_crtc_funcs
);
11961 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
11962 for (i
= 0; i
< 256; i
++) {
11963 intel_crtc
->lut_r
[i
] = i
;
11964 intel_crtc
->lut_g
[i
] = i
;
11965 intel_crtc
->lut_b
[i
] = i
;
11969 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
11970 * is hooked to pipe B. Hence we want plane A feeding pipe B.
11972 intel_crtc
->pipe
= pipe
;
11973 intel_crtc
->plane
= pipe
;
11974 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4) {
11975 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
11976 intel_crtc
->plane
= !pipe
;
11979 intel_crtc
->cursor_base
= ~0;
11980 intel_crtc
->cursor_cntl
= ~0;
11981 intel_crtc
->cursor_size
= ~0;
11983 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
11984 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
11985 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
11986 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
11988 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
11990 WARN_ON(drm_crtc_index(&intel_crtc
->base
) != intel_crtc
->pipe
);
11995 drm_plane_cleanup(primary
);
11997 drm_plane_cleanup(cursor
);
12001 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
)
12003 struct drm_encoder
*encoder
= connector
->base
.encoder
;
12004 struct drm_device
*dev
= connector
->base
.dev
;
12006 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
12009 return INVALID_PIPE
;
12011 return to_intel_crtc(encoder
->crtc
)->pipe
;
12014 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
12015 struct drm_file
*file
)
12017 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
12018 struct drm_crtc
*drmmode_crtc
;
12019 struct intel_crtc
*crtc
;
12021 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
12024 drmmode_crtc
= drm_crtc_find(dev
, pipe_from_crtc_id
->crtc_id
);
12026 if (!drmmode_crtc
) {
12027 DRM_ERROR("no such CRTC id\n");
12031 crtc
= to_intel_crtc(drmmode_crtc
);
12032 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
12037 static int intel_encoder_clones(struct intel_encoder
*encoder
)
12039 struct drm_device
*dev
= encoder
->base
.dev
;
12040 struct intel_encoder
*source_encoder
;
12041 int index_mask
= 0;
12044 for_each_intel_encoder(dev
, source_encoder
) {
12045 if (encoders_cloneable(encoder
, source_encoder
))
12046 index_mask
|= (1 << entry
);
12054 static bool has_edp_a(struct drm_device
*dev
)
12056 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12058 if (!IS_MOBILE(dev
))
12061 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
12064 if (IS_GEN5(dev
) && (I915_READ(FUSE_STRAP
) & ILK_eDP_A_DISABLE
))
12070 const char *intel_output_name(int output
)
12072 static const char *names
[] = {
12073 [INTEL_OUTPUT_UNUSED
] = "Unused",
12074 [INTEL_OUTPUT_ANALOG
] = "Analog",
12075 [INTEL_OUTPUT_DVO
] = "DVO",
12076 [INTEL_OUTPUT_SDVO
] = "SDVO",
12077 [INTEL_OUTPUT_LVDS
] = "LVDS",
12078 [INTEL_OUTPUT_TVOUT
] = "TV",
12079 [INTEL_OUTPUT_HDMI
] = "HDMI",
12080 [INTEL_OUTPUT_DISPLAYPORT
] = "DisplayPort",
12081 [INTEL_OUTPUT_EDP
] = "eDP",
12082 [INTEL_OUTPUT_DSI
] = "DSI",
12083 [INTEL_OUTPUT_UNKNOWN
] = "Unknown",
12086 if (output
< 0 || output
>= ARRAY_SIZE(names
) || !names
[output
])
12089 return names
[output
];
12092 static bool intel_crt_present(struct drm_device
*dev
)
12094 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12099 if (IS_CHERRYVIEW(dev
))
12102 if (IS_VALLEYVIEW(dev
) && !dev_priv
->vbt
.int_crt_support
)
12108 static void intel_setup_outputs(struct drm_device
*dev
)
12110 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12111 struct intel_encoder
*encoder
;
12112 bool dpd_is_edp
= false;
12114 intel_lvds_init(dev
);
12116 if (intel_crt_present(dev
))
12117 intel_crt_init(dev
);
12119 if (HAS_DDI(dev
)) {
12122 /* Haswell uses DDI functions to detect digital outputs */
12123 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
12124 /* DDI A only supports eDP */
12126 intel_ddi_init(dev
, PORT_A
);
12128 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12130 found
= I915_READ(SFUSE_STRAP
);
12132 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
12133 intel_ddi_init(dev
, PORT_B
);
12134 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
12135 intel_ddi_init(dev
, PORT_C
);
12136 if (found
& SFUSE_STRAP_DDID_DETECTED
)
12137 intel_ddi_init(dev
, PORT_D
);
12138 } else if (HAS_PCH_SPLIT(dev
)) {
12140 dpd_is_edp
= intel_dp_is_edp(dev
, PORT_D
);
12142 if (has_edp_a(dev
))
12143 intel_dp_init(dev
, DP_A
, PORT_A
);
12145 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
12146 /* PCH SDVOB multiplex with HDMIB */
12147 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
12149 intel_hdmi_init(dev
, PCH_HDMIB
, PORT_B
);
12150 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
12151 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
12154 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
12155 intel_hdmi_init(dev
, PCH_HDMIC
, PORT_C
);
12157 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
12158 intel_hdmi_init(dev
, PCH_HDMID
, PORT_D
);
12160 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
12161 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
12163 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
12164 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
12165 } else if (IS_VALLEYVIEW(dev
)) {
12166 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIB
) & SDVO_DETECTED
) {
12167 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIB
,
12169 if (I915_READ(VLV_DISPLAY_BASE
+ DP_B
) & DP_DETECTED
)
12170 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_B
, PORT_B
);
12173 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIC
) & SDVO_DETECTED
) {
12174 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIC
,
12176 if (I915_READ(VLV_DISPLAY_BASE
+ DP_C
) & DP_DETECTED
)
12177 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_C
, PORT_C
);
12180 if (IS_CHERRYVIEW(dev
)) {
12181 if (I915_READ(VLV_DISPLAY_BASE
+ CHV_HDMID
) & SDVO_DETECTED
) {
12182 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ CHV_HDMID
,
12184 if (I915_READ(VLV_DISPLAY_BASE
+ DP_D
) & DP_DETECTED
)
12185 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_D
, PORT_D
);
12189 intel_dsi_init(dev
);
12190 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
12191 bool found
= false;
12193 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
12194 DRM_DEBUG_KMS("probing SDVOB\n");
12195 found
= intel_sdvo_init(dev
, GEN3_SDVOB
, true);
12196 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
12197 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12198 intel_hdmi_init(dev
, GEN4_HDMIB
, PORT_B
);
12201 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
))
12202 intel_dp_init(dev
, DP_B
, PORT_B
);
12205 /* Before G4X SDVOC doesn't have its own detect register */
12207 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
12208 DRM_DEBUG_KMS("probing SDVOC\n");
12209 found
= intel_sdvo_init(dev
, GEN3_SDVOC
, false);
12212 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
12214 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
12215 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12216 intel_hdmi_init(dev
, GEN4_HDMIC
, PORT_C
);
12218 if (SUPPORTS_INTEGRATED_DP(dev
))
12219 intel_dp_init(dev
, DP_C
, PORT_C
);
12222 if (SUPPORTS_INTEGRATED_DP(dev
) &&
12223 (I915_READ(DP_D
) & DP_DETECTED
))
12224 intel_dp_init(dev
, DP_D
, PORT_D
);
12225 } else if (IS_GEN2(dev
))
12226 intel_dvo_init(dev
);
12228 if (SUPPORTS_TV(dev
))
12229 intel_tv_init(dev
);
12231 intel_edp_psr_init(dev
);
12233 for_each_intel_encoder(dev
, encoder
) {
12234 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
12235 encoder
->base
.possible_clones
=
12236 intel_encoder_clones(encoder
);
12239 intel_init_pch_refclk(dev
);
12241 drm_helper_move_panel_connectors_to_head(dev
);
12244 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
12246 struct drm_device
*dev
= fb
->dev
;
12247 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
12249 drm_framebuffer_cleanup(fb
);
12250 mutex_lock(&dev
->struct_mutex
);
12251 WARN_ON(!intel_fb
->obj
->framebuffer_references
--);
12252 drm_gem_object_unreference(&intel_fb
->obj
->base
);
12253 mutex_unlock(&dev
->struct_mutex
);
12257 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
12258 struct drm_file
*file
,
12259 unsigned int *handle
)
12261 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
12262 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
12264 return drm_gem_handle_create(file
, &obj
->base
, handle
);
12267 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
12268 .destroy
= intel_user_framebuffer_destroy
,
12269 .create_handle
= intel_user_framebuffer_create_handle
,
12272 static int intel_framebuffer_init(struct drm_device
*dev
,
12273 struct intel_framebuffer
*intel_fb
,
12274 struct drm_mode_fb_cmd2
*mode_cmd
,
12275 struct drm_i915_gem_object
*obj
)
12277 int aligned_height
;
12281 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
12283 if (obj
->tiling_mode
== I915_TILING_Y
) {
12284 DRM_DEBUG("hardware does not support tiling Y\n");
12288 if (mode_cmd
->pitches
[0] & 63) {
12289 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12290 mode_cmd
->pitches
[0]);
12294 if (INTEL_INFO(dev
)->gen
>= 5 && !IS_VALLEYVIEW(dev
)) {
12295 pitch_limit
= 32*1024;
12296 } else if (INTEL_INFO(dev
)->gen
>= 4) {
12297 if (obj
->tiling_mode
)
12298 pitch_limit
= 16*1024;
12300 pitch_limit
= 32*1024;
12301 } else if (INTEL_INFO(dev
)->gen
>= 3) {
12302 if (obj
->tiling_mode
)
12303 pitch_limit
= 8*1024;
12305 pitch_limit
= 16*1024;
12307 /* XXX DSPC is limited to 4k tiled */
12308 pitch_limit
= 8*1024;
12310 if (mode_cmd
->pitches
[0] > pitch_limit
) {
12311 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12312 obj
->tiling_mode
? "tiled" : "linear",
12313 mode_cmd
->pitches
[0], pitch_limit
);
12317 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
12318 mode_cmd
->pitches
[0] != obj
->stride
) {
12319 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12320 mode_cmd
->pitches
[0], obj
->stride
);
12324 /* Reject formats not supported by any plane early. */
12325 switch (mode_cmd
->pixel_format
) {
12326 case DRM_FORMAT_C8
:
12327 case DRM_FORMAT_RGB565
:
12328 case DRM_FORMAT_XRGB8888
:
12329 case DRM_FORMAT_ARGB8888
:
12331 case DRM_FORMAT_XRGB1555
:
12332 case DRM_FORMAT_ARGB1555
:
12333 if (INTEL_INFO(dev
)->gen
> 3) {
12334 DRM_DEBUG("unsupported pixel format: %s\n",
12335 drm_get_format_name(mode_cmd
->pixel_format
));
12339 case DRM_FORMAT_XBGR8888
:
12340 case DRM_FORMAT_ABGR8888
:
12341 case DRM_FORMAT_XRGB2101010
:
12342 case DRM_FORMAT_ARGB2101010
:
12343 case DRM_FORMAT_XBGR2101010
:
12344 case DRM_FORMAT_ABGR2101010
:
12345 if (INTEL_INFO(dev
)->gen
< 4) {
12346 DRM_DEBUG("unsupported pixel format: %s\n",
12347 drm_get_format_name(mode_cmd
->pixel_format
));
12351 case DRM_FORMAT_YUYV
:
12352 case DRM_FORMAT_UYVY
:
12353 case DRM_FORMAT_YVYU
:
12354 case DRM_FORMAT_VYUY
:
12355 if (INTEL_INFO(dev
)->gen
< 5) {
12356 DRM_DEBUG("unsupported pixel format: %s\n",
12357 drm_get_format_name(mode_cmd
->pixel_format
));
12362 DRM_DEBUG("unsupported pixel format: %s\n",
12363 drm_get_format_name(mode_cmd
->pixel_format
));
12367 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12368 if (mode_cmd
->offsets
[0] != 0)
12371 aligned_height
= intel_align_height(dev
, mode_cmd
->height
,
12373 /* FIXME drm helper for size checks (especially planar formats)? */
12374 if (obj
->base
.size
< aligned_height
* mode_cmd
->pitches
[0])
12377 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
12378 intel_fb
->obj
= obj
;
12379 intel_fb
->obj
->framebuffer_references
++;
12381 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
12383 DRM_ERROR("framebuffer init failed %d\n", ret
);
12390 static struct drm_framebuffer
*
12391 intel_user_framebuffer_create(struct drm_device
*dev
,
12392 struct drm_file
*filp
,
12393 struct drm_mode_fb_cmd2
*mode_cmd
)
12395 struct drm_i915_gem_object
*obj
;
12397 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
12398 mode_cmd
->handles
[0]));
12399 if (&obj
->base
== NULL
)
12400 return ERR_PTR(-ENOENT
);
12402 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
12405 #ifndef CONFIG_DRM_I915_FBDEV
12406 static inline void intel_fbdev_output_poll_changed(struct drm_device
*dev
)
12411 static const struct drm_mode_config_funcs intel_mode_funcs
= {
12412 .fb_create
= intel_user_framebuffer_create
,
12413 .output_poll_changed
= intel_fbdev_output_poll_changed
,
12416 /* Set up chip specific display functions */
12417 static void intel_init_display(struct drm_device
*dev
)
12419 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12421 if (HAS_PCH_SPLIT(dev
) || IS_G4X(dev
))
12422 dev_priv
->display
.find_dpll
= g4x_find_best_dpll
;
12423 else if (IS_CHERRYVIEW(dev
))
12424 dev_priv
->display
.find_dpll
= chv_find_best_dpll
;
12425 else if (IS_VALLEYVIEW(dev
))
12426 dev_priv
->display
.find_dpll
= vlv_find_best_dpll
;
12427 else if (IS_PINEVIEW(dev
))
12428 dev_priv
->display
.find_dpll
= pnv_find_best_dpll
;
12430 dev_priv
->display
.find_dpll
= i9xx_find_best_dpll
;
12432 if (HAS_DDI(dev
)) {
12433 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
12434 dev_priv
->display
.get_plane_config
= ironlake_get_plane_config
;
12435 dev_priv
->display
.crtc_mode_set
= haswell_crtc_mode_set
;
12436 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
12437 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
12438 dev_priv
->display
.off
= ironlake_crtc_off
;
12439 dev_priv
->display
.update_primary_plane
=
12440 ironlake_update_primary_plane
;
12441 } else if (HAS_PCH_SPLIT(dev
)) {
12442 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
12443 dev_priv
->display
.get_plane_config
= ironlake_get_plane_config
;
12444 dev_priv
->display
.crtc_mode_set
= ironlake_crtc_mode_set
;
12445 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
12446 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
12447 dev_priv
->display
.off
= ironlake_crtc_off
;
12448 dev_priv
->display
.update_primary_plane
=
12449 ironlake_update_primary_plane
;
12450 } else if (IS_VALLEYVIEW(dev
)) {
12451 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
12452 dev_priv
->display
.get_plane_config
= i9xx_get_plane_config
;
12453 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
12454 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
12455 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
12456 dev_priv
->display
.off
= i9xx_crtc_off
;
12457 dev_priv
->display
.update_primary_plane
=
12458 i9xx_update_primary_plane
;
12460 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
12461 dev_priv
->display
.get_plane_config
= i9xx_get_plane_config
;
12462 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
12463 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
12464 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
12465 dev_priv
->display
.off
= i9xx_crtc_off
;
12466 dev_priv
->display
.update_primary_plane
=
12467 i9xx_update_primary_plane
;
12470 /* Returns the core display clock speed */
12471 if (IS_VALLEYVIEW(dev
))
12472 dev_priv
->display
.get_display_clock_speed
=
12473 valleyview_get_display_clock_speed
;
12474 else if (IS_I945G(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
12475 dev_priv
->display
.get_display_clock_speed
=
12476 i945_get_display_clock_speed
;
12477 else if (IS_I915G(dev
))
12478 dev_priv
->display
.get_display_clock_speed
=
12479 i915_get_display_clock_speed
;
12480 else if (IS_I945GM(dev
) || IS_845G(dev
))
12481 dev_priv
->display
.get_display_clock_speed
=
12482 i9xx_misc_get_display_clock_speed
;
12483 else if (IS_PINEVIEW(dev
))
12484 dev_priv
->display
.get_display_clock_speed
=
12485 pnv_get_display_clock_speed
;
12486 else if (IS_I915GM(dev
))
12487 dev_priv
->display
.get_display_clock_speed
=
12488 i915gm_get_display_clock_speed
;
12489 else if (IS_I865G(dev
))
12490 dev_priv
->display
.get_display_clock_speed
=
12491 i865_get_display_clock_speed
;
12492 else if (IS_I85X(dev
))
12493 dev_priv
->display
.get_display_clock_speed
=
12494 i855_get_display_clock_speed
;
12495 else /* 852, 830 */
12496 dev_priv
->display
.get_display_clock_speed
=
12497 i830_get_display_clock_speed
;
12500 dev_priv
->display
.write_eld
= g4x_write_eld
;
12501 } else if (IS_GEN5(dev
)) {
12502 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
12503 dev_priv
->display
.write_eld
= ironlake_write_eld
;
12504 } else if (IS_GEN6(dev
)) {
12505 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
12506 dev_priv
->display
.write_eld
= ironlake_write_eld
;
12507 dev_priv
->display
.modeset_global_resources
=
12508 snb_modeset_global_resources
;
12509 } else if (IS_IVYBRIDGE(dev
)) {
12510 /* FIXME: detect B0+ stepping and use auto training */
12511 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
12512 dev_priv
->display
.write_eld
= ironlake_write_eld
;
12513 dev_priv
->display
.modeset_global_resources
=
12514 ivb_modeset_global_resources
;
12515 } else if (IS_HASWELL(dev
) || IS_GEN8(dev
)) {
12516 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
12517 dev_priv
->display
.write_eld
= haswell_write_eld
;
12518 dev_priv
->display
.modeset_global_resources
=
12519 haswell_modeset_global_resources
;
12520 } else if (IS_VALLEYVIEW(dev
)) {
12521 dev_priv
->display
.modeset_global_resources
=
12522 valleyview_modeset_global_resources
;
12523 dev_priv
->display
.write_eld
= ironlake_write_eld
;
12526 /* Default just returns -ENODEV to indicate unsupported */
12527 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
12529 switch (INTEL_INFO(dev
)->gen
) {
12531 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
12535 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
12540 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
12544 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
12547 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12548 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
12552 intel_panel_init_backlight_funcs(dev
);
12556 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12557 * resume, or other times. This quirk makes sure that's the case for
12558 * affected systems.
12560 static void quirk_pipea_force(struct drm_device
*dev
)
12562 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12564 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
12565 DRM_INFO("applying pipe a force quirk\n");
12569 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12571 static void quirk_ssc_force_disable(struct drm_device
*dev
)
12573 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12574 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
12575 DRM_INFO("applying lvds SSC disable quirk\n");
12579 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12582 static void quirk_invert_brightness(struct drm_device
*dev
)
12584 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12585 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
12586 DRM_INFO("applying inverted panel brightness quirk\n");
12589 /* Some VBT's incorrectly indicate no backlight is present */
12590 static void quirk_backlight_present(struct drm_device
*dev
)
12592 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12593 dev_priv
->quirks
|= QUIRK_BACKLIGHT_PRESENT
;
12594 DRM_INFO("applying backlight present quirk\n");
12597 struct intel_quirk
{
12599 int subsystem_vendor
;
12600 int subsystem_device
;
12601 void (*hook
)(struct drm_device
*dev
);
12604 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12605 struct intel_dmi_quirk
{
12606 void (*hook
)(struct drm_device
*dev
);
12607 const struct dmi_system_id (*dmi_id_list
)[];
12610 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
12612 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
12616 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
12618 .dmi_id_list
= &(const struct dmi_system_id
[]) {
12620 .callback
= intel_dmi_reverse_brightness
,
12621 .ident
= "NCR Corporation",
12622 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
12623 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
12626 { } /* terminating entry */
12628 .hook
= quirk_invert_brightness
,
12632 static struct intel_quirk intel_quirks
[] = {
12633 /* HP Mini needs pipe A force quirk (LP: #322104) */
12634 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force
},
12636 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12637 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
12639 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12640 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
12642 /* 830 needs to leave pipe A & dpll A up */
12643 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
12645 /* Lenovo U160 cannot use SSC on LVDS */
12646 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
12648 /* Sony Vaio Y cannot use SSC on LVDS */
12649 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
12651 /* Acer Aspire 5734Z must invert backlight brightness */
12652 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
12654 /* Acer/eMachines G725 */
12655 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness
},
12657 /* Acer/eMachines e725 */
12658 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness
},
12660 /* Acer/Packard Bell NCL20 */
12661 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness
},
12663 /* Acer Aspire 4736Z */
12664 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness
},
12666 /* Acer Aspire 5336 */
12667 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness
},
12669 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12670 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present
},
12672 /* Toshiba CB35 Chromebook (Celeron 2955U) */
12673 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present
},
12675 /* HP Chromebook 14 (Celeron 2955U) */
12676 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present
},
12679 static void intel_init_quirks(struct drm_device
*dev
)
12681 struct pci_dev
*d
= dev
->pdev
;
12684 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
12685 struct intel_quirk
*q
= &intel_quirks
[i
];
12687 if (d
->device
== q
->device
&&
12688 (d
->subsystem_vendor
== q
->subsystem_vendor
||
12689 q
->subsystem_vendor
== PCI_ANY_ID
) &&
12690 (d
->subsystem_device
== q
->subsystem_device
||
12691 q
->subsystem_device
== PCI_ANY_ID
))
12694 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
12695 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
12696 intel_dmi_quirks
[i
].hook(dev
);
12700 /* Disable the VGA plane that we never use */
12701 static void i915_disable_vga(struct drm_device
*dev
)
12703 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12705 u32 vga_reg
= i915_vgacntrl_reg(dev
);
12707 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12708 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
12709 outb(SR01
, VGA_SR_INDEX
);
12710 sr1
= inb(VGA_SR_DATA
);
12711 outb(sr1
| 1<<5, VGA_SR_DATA
);
12712 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
12715 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
12716 POSTING_READ(vga_reg
);
12719 void intel_modeset_init_hw(struct drm_device
*dev
)
12721 intel_prepare_ddi(dev
);
12723 if (IS_VALLEYVIEW(dev
))
12724 vlv_update_cdclk(dev
);
12726 intel_init_clock_gating(dev
);
12728 intel_enable_gt_powersave(dev
);
12731 void intel_modeset_suspend_hw(struct drm_device
*dev
)
12733 intel_suspend_hw(dev
);
12736 void intel_modeset_init(struct drm_device
*dev
)
12738 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12741 struct intel_crtc
*crtc
;
12743 drm_mode_config_init(dev
);
12745 dev
->mode_config
.min_width
= 0;
12746 dev
->mode_config
.min_height
= 0;
12748 dev
->mode_config
.preferred_depth
= 24;
12749 dev
->mode_config
.prefer_shadow
= 1;
12751 dev
->mode_config
.funcs
= &intel_mode_funcs
;
12753 intel_init_quirks(dev
);
12755 intel_init_pm(dev
);
12757 if (INTEL_INFO(dev
)->num_pipes
== 0)
12760 intel_init_display(dev
);
12762 if (IS_GEN2(dev
)) {
12763 dev
->mode_config
.max_width
= 2048;
12764 dev
->mode_config
.max_height
= 2048;
12765 } else if (IS_GEN3(dev
)) {
12766 dev
->mode_config
.max_width
= 4096;
12767 dev
->mode_config
.max_height
= 4096;
12769 dev
->mode_config
.max_width
= 8192;
12770 dev
->mode_config
.max_height
= 8192;
12773 if (IS_845G(dev
) || IS_I865G(dev
)) {
12774 dev
->mode_config
.cursor_width
= IS_845G(dev
) ? 64 : 512;
12775 dev
->mode_config
.cursor_height
= 1023;
12776 } else if (IS_GEN2(dev
)) {
12777 dev
->mode_config
.cursor_width
= GEN2_CURSOR_WIDTH
;
12778 dev
->mode_config
.cursor_height
= GEN2_CURSOR_HEIGHT
;
12780 dev
->mode_config
.cursor_width
= MAX_CURSOR_WIDTH
;
12781 dev
->mode_config
.cursor_height
= MAX_CURSOR_HEIGHT
;
12784 dev
->mode_config
.fb_base
= dev_priv
->gtt
.mappable_base
;
12786 DRM_DEBUG_KMS("%d display pipe%s available.\n",
12787 INTEL_INFO(dev
)->num_pipes
,
12788 INTEL_INFO(dev
)->num_pipes
> 1 ? "s" : "");
12790 for_each_pipe(dev_priv
, pipe
) {
12791 intel_crtc_init(dev
, pipe
);
12792 for_each_sprite(pipe
, sprite
) {
12793 ret
= intel_plane_init(dev
, pipe
, sprite
);
12795 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
12796 pipe_name(pipe
), sprite_name(pipe
, sprite
), ret
);
12800 intel_init_dpio(dev
);
12802 intel_shared_dpll_init(dev
);
12804 /* Just disable it once at startup */
12805 i915_disable_vga(dev
);
12806 intel_setup_outputs(dev
);
12808 /* Just in case the BIOS is doing something questionable. */
12809 intel_disable_fbc(dev
);
12811 drm_modeset_lock_all(dev
);
12812 intel_modeset_setup_hw_state(dev
, false);
12813 drm_modeset_unlock_all(dev
);
12815 for_each_intel_crtc(dev
, crtc
) {
12820 * Note that reserving the BIOS fb up front prevents us
12821 * from stuffing other stolen allocations like the ring
12822 * on top. This prevents some ugliness at boot time, and
12823 * can even allow for smooth boot transitions if the BIOS
12824 * fb is large enough for the active pipe configuration.
12826 if (dev_priv
->display
.get_plane_config
) {
12827 dev_priv
->display
.get_plane_config(crtc
,
12828 &crtc
->plane_config
);
12830 * If the fb is shared between multiple heads, we'll
12831 * just get the first one.
12833 intel_find_plane_obj(crtc
, &crtc
->plane_config
);
12838 static void intel_enable_pipe_a(struct drm_device
*dev
)
12840 struct intel_connector
*connector
;
12841 struct drm_connector
*crt
= NULL
;
12842 struct intel_load_detect_pipe load_detect_temp
;
12843 struct drm_modeset_acquire_ctx
*ctx
= dev
->mode_config
.acquire_ctx
;
12845 /* We can't just switch on the pipe A, we need to set things up with a
12846 * proper mode and output configuration. As a gross hack, enable pipe A
12847 * by enabling the load detect pipe once. */
12848 list_for_each_entry(connector
,
12849 &dev
->mode_config
.connector_list
,
12851 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
12852 crt
= &connector
->base
;
12860 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
, ctx
))
12861 intel_release_load_detect_pipe(crt
, &load_detect_temp
);
12865 intel_check_plane_mapping(struct intel_crtc
*crtc
)
12867 struct drm_device
*dev
= crtc
->base
.dev
;
12868 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12871 if (INTEL_INFO(dev
)->num_pipes
== 1)
12874 reg
= DSPCNTR(!crtc
->plane
);
12875 val
= I915_READ(reg
);
12877 if ((val
& DISPLAY_PLANE_ENABLE
) &&
12878 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
12884 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
12886 struct drm_device
*dev
= crtc
->base
.dev
;
12887 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12890 /* Clear any frame start delays used for debugging left by the BIOS */
12891 reg
= PIPECONF(crtc
->config
.cpu_transcoder
);
12892 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
12894 /* restore vblank interrupts to correct state */
12896 drm_vblank_on(dev
, crtc
->pipe
);
12898 drm_vblank_off(dev
, crtc
->pipe
);
12900 /* We need to sanitize the plane -> pipe mapping first because this will
12901 * disable the crtc (and hence change the state) if it is wrong. Note
12902 * that gen4+ has a fixed plane -> pipe mapping. */
12903 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
12904 struct intel_connector
*connector
;
12907 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
12908 crtc
->base
.base
.id
);
12910 /* Pipe has the wrong plane attached and the plane is active.
12911 * Temporarily change the plane mapping and disable everything
12913 plane
= crtc
->plane
;
12914 crtc
->plane
= !plane
;
12915 crtc
->primary_enabled
= true;
12916 dev_priv
->display
.crtc_disable(&crtc
->base
);
12917 crtc
->plane
= plane
;
12919 /* ... and break all links. */
12920 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
12922 if (connector
->encoder
->base
.crtc
!= &crtc
->base
)
12925 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
12926 connector
->base
.encoder
= NULL
;
12928 /* multiple connectors may have the same encoder:
12929 * handle them and break crtc link separately */
12930 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
12932 if (connector
->encoder
->base
.crtc
== &crtc
->base
) {
12933 connector
->encoder
->base
.crtc
= NULL
;
12934 connector
->encoder
->connectors_active
= false;
12937 WARN_ON(crtc
->active
);
12938 crtc
->base
.enabled
= false;
12941 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
12942 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
12943 /* BIOS forgot to enable pipe A, this mostly happens after
12944 * resume. Force-enable the pipe to fix this, the update_dpms
12945 * call below we restore the pipe to the right state, but leave
12946 * the required bits on. */
12947 intel_enable_pipe_a(dev
);
12950 /* Adjust the state of the output pipe according to whether we
12951 * have active connectors/encoders. */
12952 intel_crtc_update_dpms(&crtc
->base
);
12954 if (crtc
->active
!= crtc
->base
.enabled
) {
12955 struct intel_encoder
*encoder
;
12957 /* This can happen either due to bugs in the get_hw_state
12958 * functions or because the pipe is force-enabled due to the
12960 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
12961 crtc
->base
.base
.id
,
12962 crtc
->base
.enabled
? "enabled" : "disabled",
12963 crtc
->active
? "enabled" : "disabled");
12965 crtc
->base
.enabled
= crtc
->active
;
12967 /* Because we only establish the connector -> encoder ->
12968 * crtc links if something is active, this means the
12969 * crtc is now deactivated. Break the links. connector
12970 * -> encoder links are only establish when things are
12971 * actually up, hence no need to break them. */
12972 WARN_ON(crtc
->active
);
12974 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
12975 WARN_ON(encoder
->connectors_active
);
12976 encoder
->base
.crtc
= NULL
;
12980 if (crtc
->active
|| IS_VALLEYVIEW(dev
) || INTEL_INFO(dev
)->gen
< 5) {
12982 * We start out with underrun reporting disabled to avoid races.
12983 * For correct bookkeeping mark this on active crtcs.
12985 * Also on gmch platforms we dont have any hardware bits to
12986 * disable the underrun reporting. Which means we need to start
12987 * out with underrun reporting disabled also on inactive pipes,
12988 * since otherwise we'll complain about the garbage we read when
12989 * e.g. coming up after runtime pm.
12991 * No protection against concurrent access is required - at
12992 * worst a fifo underrun happens which also sets this to false.
12994 crtc
->cpu_fifo_underrun_disabled
= true;
12995 crtc
->pch_fifo_underrun_disabled
= true;
12997 update_scanline_offset(crtc
);
13001 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
13003 struct intel_connector
*connector
;
13004 struct drm_device
*dev
= encoder
->base
.dev
;
13006 /* We need to check both for a crtc link (meaning that the
13007 * encoder is active and trying to read from a pipe) and the
13008 * pipe itself being active. */
13009 bool has_active_crtc
= encoder
->base
.crtc
&&
13010 to_intel_crtc(encoder
->base
.crtc
)->active
;
13012 if (encoder
->connectors_active
&& !has_active_crtc
) {
13013 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13014 encoder
->base
.base
.id
,
13015 encoder
->base
.name
);
13017 /* Connector is active, but has no active pipe. This is
13018 * fallout from our resume register restoring. Disable
13019 * the encoder manually again. */
13020 if (encoder
->base
.crtc
) {
13021 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13022 encoder
->base
.base
.id
,
13023 encoder
->base
.name
);
13024 encoder
->disable(encoder
);
13025 if (encoder
->post_disable
)
13026 encoder
->post_disable(encoder
);
13028 encoder
->base
.crtc
= NULL
;
13029 encoder
->connectors_active
= false;
13031 /* Inconsistent output/port/pipe state happens presumably due to
13032 * a bug in one of the get_hw_state functions. Or someplace else
13033 * in our code, like the register restore mess on resume. Clamp
13034 * things to off as a safer default. */
13035 list_for_each_entry(connector
,
13036 &dev
->mode_config
.connector_list
,
13038 if (connector
->encoder
!= encoder
)
13040 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
13041 connector
->base
.encoder
= NULL
;
13044 /* Enabled encoders without active connectors will be fixed in
13045 * the crtc fixup. */
13048 void i915_redisable_vga_power_on(struct drm_device
*dev
)
13050 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13051 u32 vga_reg
= i915_vgacntrl_reg(dev
);
13053 if (!(I915_READ(vga_reg
) & VGA_DISP_DISABLE
)) {
13054 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13055 i915_disable_vga(dev
);
13059 void i915_redisable_vga(struct drm_device
*dev
)
13061 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13063 /* This function can be called both from intel_modeset_setup_hw_state or
13064 * at a very early point in our resume sequence, where the power well
13065 * structures are not yet restored. Since this function is at a very
13066 * paranoid "someone might have enabled VGA while we were not looking"
13067 * level, just check if the power well is enabled instead of trying to
13068 * follow the "don't touch the power well if we don't need it" policy
13069 * the rest of the driver uses. */
13070 if (!intel_display_power_enabled(dev_priv
, POWER_DOMAIN_VGA
))
13073 i915_redisable_vga_power_on(dev
);
13076 static bool primary_get_hw_state(struct intel_crtc
*crtc
)
13078 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
13083 return I915_READ(DSPCNTR(crtc
->plane
)) & DISPLAY_PLANE_ENABLE
;
13086 static void intel_modeset_readout_hw_state(struct drm_device
*dev
)
13088 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13090 struct intel_crtc
*crtc
;
13091 struct intel_encoder
*encoder
;
13092 struct intel_connector
*connector
;
13095 for_each_intel_crtc(dev
, crtc
) {
13096 memset(&crtc
->config
, 0, sizeof(crtc
->config
));
13098 crtc
->config
.quirks
|= PIPE_CONFIG_QUIRK_INHERITED_MODE
;
13100 crtc
->active
= dev_priv
->display
.get_pipe_config(crtc
,
13103 crtc
->base
.enabled
= crtc
->active
;
13104 crtc
->primary_enabled
= primary_get_hw_state(crtc
);
13106 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13107 crtc
->base
.base
.id
,
13108 crtc
->active
? "enabled" : "disabled");
13111 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
13112 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
13114 pll
->on
= pll
->get_hw_state(dev_priv
, pll
, &pll
->hw_state
);
13116 for_each_intel_crtc(dev
, crtc
) {
13117 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
13120 pll
->refcount
= pll
->active
;
13122 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
13123 pll
->name
, pll
->refcount
, pll
->on
);
13126 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
13129 for_each_intel_encoder(dev
, encoder
) {
13132 if (encoder
->get_hw_state(encoder
, &pipe
)) {
13133 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
13134 encoder
->base
.crtc
= &crtc
->base
;
13135 encoder
->get_config(encoder
, &crtc
->config
);
13137 encoder
->base
.crtc
= NULL
;
13140 encoder
->connectors_active
= false;
13141 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13142 encoder
->base
.base
.id
,
13143 encoder
->base
.name
,
13144 encoder
->base
.crtc
? "enabled" : "disabled",
13148 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
13150 if (connector
->get_hw_state(connector
)) {
13151 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
13152 connector
->encoder
->connectors_active
= true;
13153 connector
->base
.encoder
= &connector
->encoder
->base
;
13155 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
13156 connector
->base
.encoder
= NULL
;
13158 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13159 connector
->base
.base
.id
,
13160 connector
->base
.name
,
13161 connector
->base
.encoder
? "enabled" : "disabled");
13165 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13166 * and i915 state tracking structures. */
13167 void intel_modeset_setup_hw_state(struct drm_device
*dev
,
13168 bool force_restore
)
13170 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13172 struct intel_crtc
*crtc
;
13173 struct intel_encoder
*encoder
;
13176 intel_modeset_readout_hw_state(dev
);
13179 * Now that we have the config, copy it to each CRTC struct
13180 * Note that this could go away if we move to using crtc_config
13181 * checking everywhere.
13183 for_each_intel_crtc(dev
, crtc
) {
13184 if (crtc
->active
&& i915
.fastboot
) {
13185 intel_mode_from_pipe_config(&crtc
->base
.mode
, &crtc
->config
);
13186 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13187 crtc
->base
.base
.id
);
13188 drm_mode_debug_printmodeline(&crtc
->base
.mode
);
13192 /* HW state is read out, now we need to sanitize this mess. */
13193 for_each_intel_encoder(dev
, encoder
) {
13194 intel_sanitize_encoder(encoder
);
13197 for_each_pipe(dev_priv
, pipe
) {
13198 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
13199 intel_sanitize_crtc(crtc
);
13200 intel_dump_pipe_config(crtc
, &crtc
->config
, "[setup_hw_state]");
13203 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
13204 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
13206 if (!pll
->on
|| pll
->active
)
13209 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll
->name
);
13211 pll
->disable(dev_priv
, pll
);
13215 if (HAS_PCH_SPLIT(dev
))
13216 ilk_wm_get_hw_state(dev
);
13218 if (force_restore
) {
13219 i915_redisable_vga(dev
);
13222 * We need to use raw interfaces for restoring state to avoid
13223 * checking (bogus) intermediate states.
13225 for_each_pipe(dev_priv
, pipe
) {
13226 struct drm_crtc
*crtc
=
13227 dev_priv
->pipe_to_crtc_mapping
[pipe
];
13229 __intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
,
13230 crtc
->primary
->fb
);
13233 intel_modeset_update_staged_output_state(dev
);
13236 intel_modeset_check_state(dev
);
13239 void intel_modeset_gem_init(struct drm_device
*dev
)
13241 struct drm_crtc
*c
;
13242 struct drm_i915_gem_object
*obj
;
13244 mutex_lock(&dev
->struct_mutex
);
13245 intel_init_gt_powersave(dev
);
13246 mutex_unlock(&dev
->struct_mutex
);
13248 intel_modeset_init_hw(dev
);
13250 intel_setup_overlay(dev
);
13253 * Make sure any fbs we allocated at startup are properly
13254 * pinned & fenced. When we do the allocation it's too early
13257 mutex_lock(&dev
->struct_mutex
);
13258 for_each_crtc(dev
, c
) {
13259 obj
= intel_fb_obj(c
->primary
->fb
);
13263 if (intel_pin_and_fence_fb_obj(dev
, obj
, NULL
)) {
13264 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13265 to_intel_crtc(c
)->pipe
);
13266 drm_framebuffer_unreference(c
->primary
->fb
);
13267 c
->primary
->fb
= NULL
;
13270 mutex_unlock(&dev
->struct_mutex
);
13273 void intel_connector_unregister(struct intel_connector
*intel_connector
)
13275 struct drm_connector
*connector
= &intel_connector
->base
;
13277 intel_panel_destroy_backlight(connector
);
13278 drm_connector_unregister(connector
);
13281 void intel_modeset_cleanup(struct drm_device
*dev
)
13283 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13284 struct drm_connector
*connector
;
13287 * Interrupts and polling as the first thing to avoid creating havoc.
13288 * Too much stuff here (turning of rps, connectors, ...) would
13289 * experience fancy races otherwise.
13291 drm_irq_uninstall(dev
);
13292 intel_hpd_cancel_work(dev_priv
);
13293 dev_priv
->pm
._irqs_disabled
= true;
13296 * Due to the hpd irq storm handling the hotplug work can re-arm the
13297 * poll handlers. Hence disable polling after hpd handling is shut down.
13299 drm_kms_helper_poll_fini(dev
);
13301 mutex_lock(&dev
->struct_mutex
);
13303 intel_unregister_dsm_handler();
13305 intel_disable_fbc(dev
);
13307 intel_disable_gt_powersave(dev
);
13309 ironlake_teardown_rc6(dev
);
13311 mutex_unlock(&dev
->struct_mutex
);
13313 /* flush any delayed tasks or pending work */
13314 flush_scheduled_work();
13316 /* destroy the backlight and sysfs files before encoders/connectors */
13317 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
13318 struct intel_connector
*intel_connector
;
13320 intel_connector
= to_intel_connector(connector
);
13321 intel_connector
->unregister(intel_connector
);
13324 drm_mode_config_cleanup(dev
);
13326 intel_cleanup_overlay(dev
);
13328 mutex_lock(&dev
->struct_mutex
);
13329 intel_cleanup_gt_powersave(dev
);
13330 mutex_unlock(&dev
->struct_mutex
);
13334 * Return which encoder is currently attached for connector.
13336 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
13338 return &intel_attached_encoder(connector
)->base
;
13341 void intel_connector_attach_encoder(struct intel_connector
*connector
,
13342 struct intel_encoder
*encoder
)
13344 connector
->encoder
= encoder
;
13345 drm_mode_connector_attach_encoder(&connector
->base
,
13350 * set vga decode state - true == enable VGA decode
13352 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
13354 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13355 unsigned reg
= INTEL_INFO(dev
)->gen
>= 6 ? SNB_GMCH_CTRL
: INTEL_GMCH_CTRL
;
13358 if (pci_read_config_word(dev_priv
->bridge_dev
, reg
, &gmch_ctrl
)) {
13359 DRM_ERROR("failed to read control word\n");
13363 if (!!(gmch_ctrl
& INTEL_GMCH_VGA_DISABLE
) == !state
)
13367 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
13369 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
13371 if (pci_write_config_word(dev_priv
->bridge_dev
, reg
, gmch_ctrl
)) {
13372 DRM_ERROR("failed to write control word\n");
13379 struct intel_display_error_state
{
13381 u32 power_well_driver
;
13383 int num_transcoders
;
13385 struct intel_cursor_error_state
{
13390 } cursor
[I915_MAX_PIPES
];
13392 struct intel_pipe_error_state
{
13393 bool power_domain_on
;
13396 } pipe
[I915_MAX_PIPES
];
13398 struct intel_plane_error_state
{
13406 } plane
[I915_MAX_PIPES
];
13408 struct intel_transcoder_error_state
{
13409 bool power_domain_on
;
13410 enum transcoder cpu_transcoder
;
13423 struct intel_display_error_state
*
13424 intel_display_capture_error_state(struct drm_device
*dev
)
13426 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13427 struct intel_display_error_state
*error
;
13428 int transcoders
[] = {
13436 if (INTEL_INFO(dev
)->num_pipes
== 0)
13439 error
= kzalloc(sizeof(*error
), GFP_ATOMIC
);
13443 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
13444 error
->power_well_driver
= I915_READ(HSW_PWR_WELL_DRIVER
);
13446 for_each_pipe(dev_priv
, i
) {
13447 error
->pipe
[i
].power_domain_on
=
13448 intel_display_power_enabled_unlocked(dev_priv
,
13449 POWER_DOMAIN_PIPE(i
));
13450 if (!error
->pipe
[i
].power_domain_on
)
13453 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
13454 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
13455 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
13457 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
13458 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
13459 if (INTEL_INFO(dev
)->gen
<= 3) {
13460 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
13461 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
13463 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
13464 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
13465 if (INTEL_INFO(dev
)->gen
>= 4) {
13466 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
13467 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
13470 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
13472 if (HAS_GMCH_DISPLAY(dev
))
13473 error
->pipe
[i
].stat
= I915_READ(PIPESTAT(i
));
13476 error
->num_transcoders
= INTEL_INFO(dev
)->num_pipes
;
13477 if (HAS_DDI(dev_priv
->dev
))
13478 error
->num_transcoders
++; /* Account for eDP. */
13480 for (i
= 0; i
< error
->num_transcoders
; i
++) {
13481 enum transcoder cpu_transcoder
= transcoders
[i
];
13483 error
->transcoder
[i
].power_domain_on
=
13484 intel_display_power_enabled_unlocked(dev_priv
,
13485 POWER_DOMAIN_TRANSCODER(cpu_transcoder
));
13486 if (!error
->transcoder
[i
].power_domain_on
)
13489 error
->transcoder
[i
].cpu_transcoder
= cpu_transcoder
;
13491 error
->transcoder
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
13492 error
->transcoder
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
13493 error
->transcoder
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
13494 error
->transcoder
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
13495 error
->transcoder
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
13496 error
->transcoder
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
13497 error
->transcoder
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
13503 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13506 intel_display_print_error_state(struct drm_i915_error_state_buf
*m
,
13507 struct drm_device
*dev
,
13508 struct intel_display_error_state
*error
)
13510 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13516 err_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev
)->num_pipes
);
13517 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
13518 err_printf(m
, "PWR_WELL_CTL2: %08x\n",
13519 error
->power_well_driver
);
13520 for_each_pipe(dev_priv
, i
) {
13521 err_printf(m
, "Pipe [%d]:\n", i
);
13522 err_printf(m
, " Power: %s\n",
13523 error
->pipe
[i
].power_domain_on
? "on" : "off");
13524 err_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
13525 err_printf(m
, " STAT: %08x\n", error
->pipe
[i
].stat
);
13527 err_printf(m
, "Plane [%d]:\n", i
);
13528 err_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
13529 err_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
13530 if (INTEL_INFO(dev
)->gen
<= 3) {
13531 err_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
13532 err_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
13534 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
13535 err_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
13536 if (INTEL_INFO(dev
)->gen
>= 4) {
13537 err_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
13538 err_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
13541 err_printf(m
, "Cursor [%d]:\n", i
);
13542 err_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
13543 err_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
13544 err_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);
13547 for (i
= 0; i
< error
->num_transcoders
; i
++) {
13548 err_printf(m
, "CPU transcoder: %c\n",
13549 transcoder_name(error
->transcoder
[i
].cpu_transcoder
));
13550 err_printf(m
, " Power: %s\n",
13551 error
->transcoder
[i
].power_domain_on
? "on" : "off");
13552 err_printf(m
, " CONF: %08x\n", error
->transcoder
[i
].conf
);
13553 err_printf(m
, " HTOTAL: %08x\n", error
->transcoder
[i
].htotal
);
13554 err_printf(m
, " HBLANK: %08x\n", error
->transcoder
[i
].hblank
);
13555 err_printf(m
, " HSYNC: %08x\n", error
->transcoder
[i
].hsync
);
13556 err_printf(m
, " VTOTAL: %08x\n", error
->transcoder
[i
].vtotal
);
13557 err_printf(m
, " VBLANK: %08x\n", error
->transcoder
[i
].vblank
);
13558 err_printf(m
, " VSYNC: %08x\n", error
->transcoder
[i
].vsync
);
13562 void intel_modeset_preclose(struct drm_device
*dev
, struct drm_file
*file
)
13564 struct intel_crtc
*crtc
;
13566 for_each_intel_crtc(dev
, crtc
) {
13567 struct intel_unpin_work
*work
;
13568 unsigned long irqflags
;
13570 spin_lock_irqsave(&dev
->event_lock
, irqflags
);
13572 work
= crtc
->unpin_work
;
13574 if (work
&& work
->event
&&
13575 work
->event
->base
.file_priv
== file
) {
13576 kfree(work
->event
);
13577 work
->event
= NULL
;
13580 spin_unlock_irqrestore(&dev
->event_lock
, irqflags
);