2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_rect.h>
44 #include <linux/dma_remapping.h>
46 /* Primary plane formats supported by all gen */
47 #define COMMON_PRIMARY_FORMATS \
50 DRM_FORMAT_XRGB8888, \
53 /* Primary plane formats for gen <= 3 */
54 static const uint32_t intel_primary_formats_gen2
[] = {
55 COMMON_PRIMARY_FORMATS
,
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t intel_primary_formats_gen4
[] = {
62 COMMON_PRIMARY_FORMATS
, \
65 DRM_FORMAT_XRGB2101010
,
66 DRM_FORMAT_ARGB2101010
,
67 DRM_FORMAT_XBGR2101010
,
68 DRM_FORMAT_ABGR2101010
,
72 static const uint32_t intel_cursor_formats
[] = {
76 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
78 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
79 struct intel_crtc_config
*pipe_config
);
80 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
81 struct intel_crtc_config
*pipe_config
);
83 static int intel_set_mode(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
,
84 int x
, int y
, struct drm_framebuffer
*old_fb
);
85 static int intel_framebuffer_init(struct drm_device
*dev
,
86 struct intel_framebuffer
*ifb
,
87 struct drm_mode_fb_cmd2
*mode_cmd
,
88 struct drm_i915_gem_object
*obj
);
89 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
);
90 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
);
91 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
92 struct intel_link_m_n
*m_n
,
93 struct intel_link_m_n
*m2_n2
);
94 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
);
95 static void haswell_set_pipeconf(struct drm_crtc
*crtc
);
96 static void intel_set_pipe_csc(struct drm_crtc
*crtc
);
97 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
98 const struct intel_crtc_config
*pipe_config
);
99 static void chv_prepare_pll(struct intel_crtc
*crtc
,
100 const struct intel_crtc_config
*pipe_config
);
102 static struct intel_encoder
*intel_find_encoder(struct intel_connector
*connector
, int pipe
)
104 if (!connector
->mst_port
)
105 return connector
->encoder
;
107 return &connector
->mst_port
->mst_encoders
[pipe
]->base
;
116 int p2_slow
, p2_fast
;
119 typedef struct intel_limit intel_limit_t
;
121 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
126 intel_pch_rawclk(struct drm_device
*dev
)
128 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
130 WARN_ON(!HAS_PCH_SPLIT(dev
));
132 return I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
;
135 static inline u32
/* units of 100MHz */
136 intel_fdi_link_freq(struct drm_device
*dev
)
139 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
140 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
145 static const intel_limit_t intel_limits_i8xx_dac
= {
146 .dot
= { .min
= 25000, .max
= 350000 },
147 .vco
= { .min
= 908000, .max
= 1512000 },
148 .n
= { .min
= 2, .max
= 16 },
149 .m
= { .min
= 96, .max
= 140 },
150 .m1
= { .min
= 18, .max
= 26 },
151 .m2
= { .min
= 6, .max
= 16 },
152 .p
= { .min
= 4, .max
= 128 },
153 .p1
= { .min
= 2, .max
= 33 },
154 .p2
= { .dot_limit
= 165000,
155 .p2_slow
= 4, .p2_fast
= 2 },
158 static const intel_limit_t intel_limits_i8xx_dvo
= {
159 .dot
= { .min
= 25000, .max
= 350000 },
160 .vco
= { .min
= 908000, .max
= 1512000 },
161 .n
= { .min
= 2, .max
= 16 },
162 .m
= { .min
= 96, .max
= 140 },
163 .m1
= { .min
= 18, .max
= 26 },
164 .m2
= { .min
= 6, .max
= 16 },
165 .p
= { .min
= 4, .max
= 128 },
166 .p1
= { .min
= 2, .max
= 33 },
167 .p2
= { .dot_limit
= 165000,
168 .p2_slow
= 4, .p2_fast
= 4 },
171 static const intel_limit_t intel_limits_i8xx_lvds
= {
172 .dot
= { .min
= 25000, .max
= 350000 },
173 .vco
= { .min
= 908000, .max
= 1512000 },
174 .n
= { .min
= 2, .max
= 16 },
175 .m
= { .min
= 96, .max
= 140 },
176 .m1
= { .min
= 18, .max
= 26 },
177 .m2
= { .min
= 6, .max
= 16 },
178 .p
= { .min
= 4, .max
= 128 },
179 .p1
= { .min
= 1, .max
= 6 },
180 .p2
= { .dot_limit
= 165000,
181 .p2_slow
= 14, .p2_fast
= 7 },
184 static const intel_limit_t intel_limits_i9xx_sdvo
= {
185 .dot
= { .min
= 20000, .max
= 400000 },
186 .vco
= { .min
= 1400000, .max
= 2800000 },
187 .n
= { .min
= 1, .max
= 6 },
188 .m
= { .min
= 70, .max
= 120 },
189 .m1
= { .min
= 8, .max
= 18 },
190 .m2
= { .min
= 3, .max
= 7 },
191 .p
= { .min
= 5, .max
= 80 },
192 .p1
= { .min
= 1, .max
= 8 },
193 .p2
= { .dot_limit
= 200000,
194 .p2_slow
= 10, .p2_fast
= 5 },
197 static const intel_limit_t intel_limits_i9xx_lvds
= {
198 .dot
= { .min
= 20000, .max
= 400000 },
199 .vco
= { .min
= 1400000, .max
= 2800000 },
200 .n
= { .min
= 1, .max
= 6 },
201 .m
= { .min
= 70, .max
= 120 },
202 .m1
= { .min
= 8, .max
= 18 },
203 .m2
= { .min
= 3, .max
= 7 },
204 .p
= { .min
= 7, .max
= 98 },
205 .p1
= { .min
= 1, .max
= 8 },
206 .p2
= { .dot_limit
= 112000,
207 .p2_slow
= 14, .p2_fast
= 7 },
211 static const intel_limit_t intel_limits_g4x_sdvo
= {
212 .dot
= { .min
= 25000, .max
= 270000 },
213 .vco
= { .min
= 1750000, .max
= 3500000},
214 .n
= { .min
= 1, .max
= 4 },
215 .m
= { .min
= 104, .max
= 138 },
216 .m1
= { .min
= 17, .max
= 23 },
217 .m2
= { .min
= 5, .max
= 11 },
218 .p
= { .min
= 10, .max
= 30 },
219 .p1
= { .min
= 1, .max
= 3},
220 .p2
= { .dot_limit
= 270000,
226 static const intel_limit_t intel_limits_g4x_hdmi
= {
227 .dot
= { .min
= 22000, .max
= 400000 },
228 .vco
= { .min
= 1750000, .max
= 3500000},
229 .n
= { .min
= 1, .max
= 4 },
230 .m
= { .min
= 104, .max
= 138 },
231 .m1
= { .min
= 16, .max
= 23 },
232 .m2
= { .min
= 5, .max
= 11 },
233 .p
= { .min
= 5, .max
= 80 },
234 .p1
= { .min
= 1, .max
= 8},
235 .p2
= { .dot_limit
= 165000,
236 .p2_slow
= 10, .p2_fast
= 5 },
239 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
240 .dot
= { .min
= 20000, .max
= 115000 },
241 .vco
= { .min
= 1750000, .max
= 3500000 },
242 .n
= { .min
= 1, .max
= 3 },
243 .m
= { .min
= 104, .max
= 138 },
244 .m1
= { .min
= 17, .max
= 23 },
245 .m2
= { .min
= 5, .max
= 11 },
246 .p
= { .min
= 28, .max
= 112 },
247 .p1
= { .min
= 2, .max
= 8 },
248 .p2
= { .dot_limit
= 0,
249 .p2_slow
= 14, .p2_fast
= 14
253 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
254 .dot
= { .min
= 80000, .max
= 224000 },
255 .vco
= { .min
= 1750000, .max
= 3500000 },
256 .n
= { .min
= 1, .max
= 3 },
257 .m
= { .min
= 104, .max
= 138 },
258 .m1
= { .min
= 17, .max
= 23 },
259 .m2
= { .min
= 5, .max
= 11 },
260 .p
= { .min
= 14, .max
= 42 },
261 .p1
= { .min
= 2, .max
= 6 },
262 .p2
= { .dot_limit
= 0,
263 .p2_slow
= 7, .p2_fast
= 7
267 static const intel_limit_t intel_limits_pineview_sdvo
= {
268 .dot
= { .min
= 20000, .max
= 400000},
269 .vco
= { .min
= 1700000, .max
= 3500000 },
270 /* Pineview's Ncounter is a ring counter */
271 .n
= { .min
= 3, .max
= 6 },
272 .m
= { .min
= 2, .max
= 256 },
273 /* Pineview only has one combined m divider, which we treat as m2. */
274 .m1
= { .min
= 0, .max
= 0 },
275 .m2
= { .min
= 0, .max
= 254 },
276 .p
= { .min
= 5, .max
= 80 },
277 .p1
= { .min
= 1, .max
= 8 },
278 .p2
= { .dot_limit
= 200000,
279 .p2_slow
= 10, .p2_fast
= 5 },
282 static const intel_limit_t intel_limits_pineview_lvds
= {
283 .dot
= { .min
= 20000, .max
= 400000 },
284 .vco
= { .min
= 1700000, .max
= 3500000 },
285 .n
= { .min
= 3, .max
= 6 },
286 .m
= { .min
= 2, .max
= 256 },
287 .m1
= { .min
= 0, .max
= 0 },
288 .m2
= { .min
= 0, .max
= 254 },
289 .p
= { .min
= 7, .max
= 112 },
290 .p1
= { .min
= 1, .max
= 8 },
291 .p2
= { .dot_limit
= 112000,
292 .p2_slow
= 14, .p2_fast
= 14 },
295 /* Ironlake / Sandybridge
297 * We calculate clock using (register_value + 2) for N/M1/M2, so here
298 * the range value for them is (actual_value - 2).
300 static const intel_limit_t intel_limits_ironlake_dac
= {
301 .dot
= { .min
= 25000, .max
= 350000 },
302 .vco
= { .min
= 1760000, .max
= 3510000 },
303 .n
= { .min
= 1, .max
= 5 },
304 .m
= { .min
= 79, .max
= 127 },
305 .m1
= { .min
= 12, .max
= 22 },
306 .m2
= { .min
= 5, .max
= 9 },
307 .p
= { .min
= 5, .max
= 80 },
308 .p1
= { .min
= 1, .max
= 8 },
309 .p2
= { .dot_limit
= 225000,
310 .p2_slow
= 10, .p2_fast
= 5 },
313 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
314 .dot
= { .min
= 25000, .max
= 350000 },
315 .vco
= { .min
= 1760000, .max
= 3510000 },
316 .n
= { .min
= 1, .max
= 3 },
317 .m
= { .min
= 79, .max
= 118 },
318 .m1
= { .min
= 12, .max
= 22 },
319 .m2
= { .min
= 5, .max
= 9 },
320 .p
= { .min
= 28, .max
= 112 },
321 .p1
= { .min
= 2, .max
= 8 },
322 .p2
= { .dot_limit
= 225000,
323 .p2_slow
= 14, .p2_fast
= 14 },
326 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
327 .dot
= { .min
= 25000, .max
= 350000 },
328 .vco
= { .min
= 1760000, .max
= 3510000 },
329 .n
= { .min
= 1, .max
= 3 },
330 .m
= { .min
= 79, .max
= 127 },
331 .m1
= { .min
= 12, .max
= 22 },
332 .m2
= { .min
= 5, .max
= 9 },
333 .p
= { .min
= 14, .max
= 56 },
334 .p1
= { .min
= 2, .max
= 8 },
335 .p2
= { .dot_limit
= 225000,
336 .p2_slow
= 7, .p2_fast
= 7 },
339 /* LVDS 100mhz refclk limits. */
340 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
341 .dot
= { .min
= 25000, .max
= 350000 },
342 .vco
= { .min
= 1760000, .max
= 3510000 },
343 .n
= { .min
= 1, .max
= 2 },
344 .m
= { .min
= 79, .max
= 126 },
345 .m1
= { .min
= 12, .max
= 22 },
346 .m2
= { .min
= 5, .max
= 9 },
347 .p
= { .min
= 28, .max
= 112 },
348 .p1
= { .min
= 2, .max
= 8 },
349 .p2
= { .dot_limit
= 225000,
350 .p2_slow
= 14, .p2_fast
= 14 },
353 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
354 .dot
= { .min
= 25000, .max
= 350000 },
355 .vco
= { .min
= 1760000, .max
= 3510000 },
356 .n
= { .min
= 1, .max
= 3 },
357 .m
= { .min
= 79, .max
= 126 },
358 .m1
= { .min
= 12, .max
= 22 },
359 .m2
= { .min
= 5, .max
= 9 },
360 .p
= { .min
= 14, .max
= 42 },
361 .p1
= { .min
= 2, .max
= 6 },
362 .p2
= { .dot_limit
= 225000,
363 .p2_slow
= 7, .p2_fast
= 7 },
366 static const intel_limit_t intel_limits_vlv
= {
368 * These are the data rate limits (measured in fast clocks)
369 * since those are the strictest limits we have. The fast
370 * clock and actual rate limits are more relaxed, so checking
371 * them would make no difference.
373 .dot
= { .min
= 25000 * 5, .max
= 270000 * 5 },
374 .vco
= { .min
= 4000000, .max
= 6000000 },
375 .n
= { .min
= 1, .max
= 7 },
376 .m1
= { .min
= 2, .max
= 3 },
377 .m2
= { .min
= 11, .max
= 156 },
378 .p1
= { .min
= 2, .max
= 3 },
379 .p2
= { .p2_slow
= 2, .p2_fast
= 20 }, /* slow=min, fast=max */
382 static const intel_limit_t intel_limits_chv
= {
384 * These are the data rate limits (measured in fast clocks)
385 * since those are the strictest limits we have. The fast
386 * clock and actual rate limits are more relaxed, so checking
387 * them would make no difference.
389 .dot
= { .min
= 25000 * 5, .max
= 540000 * 5},
390 .vco
= { .min
= 4860000, .max
= 6700000 },
391 .n
= { .min
= 1, .max
= 1 },
392 .m1
= { .min
= 2, .max
= 2 },
393 .m2
= { .min
= 24 << 22, .max
= 175 << 22 },
394 .p1
= { .min
= 2, .max
= 4 },
395 .p2
= { .p2_slow
= 1, .p2_fast
= 14 },
398 static void vlv_clock(int refclk
, intel_clock_t
*clock
)
400 clock
->m
= clock
->m1
* clock
->m2
;
401 clock
->p
= clock
->p1
* clock
->p2
;
402 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
404 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
405 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
409 * Returns whether any output on the specified pipe is of the specified type
411 bool intel_pipe_has_type(struct intel_crtc
*crtc
, enum intel_output_type type
)
413 struct drm_device
*dev
= crtc
->base
.dev
;
414 struct intel_encoder
*encoder
;
416 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
)
417 if (encoder
->type
== type
)
424 * Returns whether any output on the specified pipe will have the specified
425 * type after a staged modeset is complete, i.e., the same as
426 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
429 static bool intel_pipe_will_have_type(struct intel_crtc
*crtc
, int type
)
431 struct drm_device
*dev
= crtc
->base
.dev
;
432 struct intel_encoder
*encoder
;
434 for_each_intel_encoder(dev
, encoder
)
435 if (encoder
->new_crtc
== crtc
&& encoder
->type
== type
)
441 static const intel_limit_t
*intel_ironlake_limit(struct intel_crtc
*crtc
,
444 struct drm_device
*dev
= crtc
->base
.dev
;
445 const intel_limit_t
*limit
;
447 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
)) {
448 if (intel_is_dual_link_lvds(dev
)) {
449 if (refclk
== 100000)
450 limit
= &intel_limits_ironlake_dual_lvds_100m
;
452 limit
= &intel_limits_ironlake_dual_lvds
;
454 if (refclk
== 100000)
455 limit
= &intel_limits_ironlake_single_lvds_100m
;
457 limit
= &intel_limits_ironlake_single_lvds
;
460 limit
= &intel_limits_ironlake_dac
;
465 static const intel_limit_t
*intel_g4x_limit(struct intel_crtc
*crtc
)
467 struct drm_device
*dev
= crtc
->base
.dev
;
468 const intel_limit_t
*limit
;
470 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
)) {
471 if (intel_is_dual_link_lvds(dev
))
472 limit
= &intel_limits_g4x_dual_channel_lvds
;
474 limit
= &intel_limits_g4x_single_channel_lvds
;
475 } else if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_HDMI
) ||
476 intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
477 limit
= &intel_limits_g4x_hdmi
;
478 } else if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_SDVO
)) {
479 limit
= &intel_limits_g4x_sdvo
;
480 } else /* The option is for other outputs */
481 limit
= &intel_limits_i9xx_sdvo
;
486 static const intel_limit_t
*intel_limit(struct intel_crtc
*crtc
, int refclk
)
488 struct drm_device
*dev
= crtc
->base
.dev
;
489 const intel_limit_t
*limit
;
491 if (HAS_PCH_SPLIT(dev
))
492 limit
= intel_ironlake_limit(crtc
, refclk
);
493 else if (IS_G4X(dev
)) {
494 limit
= intel_g4x_limit(crtc
);
495 } else if (IS_PINEVIEW(dev
)) {
496 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
))
497 limit
= &intel_limits_pineview_lvds
;
499 limit
= &intel_limits_pineview_sdvo
;
500 } else if (IS_CHERRYVIEW(dev
)) {
501 limit
= &intel_limits_chv
;
502 } else if (IS_VALLEYVIEW(dev
)) {
503 limit
= &intel_limits_vlv
;
504 } else if (!IS_GEN2(dev
)) {
505 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
))
506 limit
= &intel_limits_i9xx_lvds
;
508 limit
= &intel_limits_i9xx_sdvo
;
510 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
))
511 limit
= &intel_limits_i8xx_lvds
;
512 else if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_DVO
))
513 limit
= &intel_limits_i8xx_dvo
;
515 limit
= &intel_limits_i8xx_dac
;
520 /* m1 is reserved as 0 in Pineview, n is a ring counter */
521 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
523 clock
->m
= clock
->m2
+ 2;
524 clock
->p
= clock
->p1
* clock
->p2
;
525 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
527 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
528 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
531 static uint32_t i9xx_dpll_compute_m(struct dpll
*dpll
)
533 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
536 static void i9xx_clock(int refclk
, intel_clock_t
*clock
)
538 clock
->m
= i9xx_dpll_compute_m(clock
);
539 clock
->p
= clock
->p1
* clock
->p2
;
540 if (WARN_ON(clock
->n
+ 2 == 0 || clock
->p
== 0))
542 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
+ 2);
543 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
546 static void chv_clock(int refclk
, intel_clock_t
*clock
)
548 clock
->m
= clock
->m1
* clock
->m2
;
549 clock
->p
= clock
->p1
* clock
->p2
;
550 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
552 clock
->vco
= DIV_ROUND_CLOSEST_ULL((uint64_t)refclk
* clock
->m
,
554 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
557 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
559 * Returns whether the given set of divisors are valid for a given refclk with
560 * the given connectors.
563 static bool intel_PLL_is_valid(struct drm_device
*dev
,
564 const intel_limit_t
*limit
,
565 const intel_clock_t
*clock
)
567 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
568 INTELPllInvalid("n out of range\n");
569 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
570 INTELPllInvalid("p1 out of range\n");
571 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
572 INTELPllInvalid("m2 out of range\n");
573 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
574 INTELPllInvalid("m1 out of range\n");
576 if (!IS_PINEVIEW(dev
) && !IS_VALLEYVIEW(dev
))
577 if (clock
->m1
<= clock
->m2
)
578 INTELPllInvalid("m1 <= m2\n");
580 if (!IS_VALLEYVIEW(dev
)) {
581 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
582 INTELPllInvalid("p out of range\n");
583 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
584 INTELPllInvalid("m out of range\n");
587 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
588 INTELPllInvalid("vco out of range\n");
589 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
590 * connector, etc., rather than just a single range.
592 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
593 INTELPllInvalid("dot out of range\n");
599 i9xx_find_best_dpll(const intel_limit_t
*limit
, struct intel_crtc
*crtc
,
600 int target
, int refclk
, intel_clock_t
*match_clock
,
601 intel_clock_t
*best_clock
)
603 struct drm_device
*dev
= crtc
->base
.dev
;
607 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
)) {
609 * For LVDS just rely on its current settings for dual-channel.
610 * We haven't figured out how to reliably set up different
611 * single/dual channel state, if we even can.
613 if (intel_is_dual_link_lvds(dev
))
614 clock
.p2
= limit
->p2
.p2_fast
;
616 clock
.p2
= limit
->p2
.p2_slow
;
618 if (target
< limit
->p2
.dot_limit
)
619 clock
.p2
= limit
->p2
.p2_slow
;
621 clock
.p2
= limit
->p2
.p2_fast
;
624 memset(best_clock
, 0, sizeof(*best_clock
));
626 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
628 for (clock
.m2
= limit
->m2
.min
;
629 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
630 if (clock
.m2
>= clock
.m1
)
632 for (clock
.n
= limit
->n
.min
;
633 clock
.n
<= limit
->n
.max
; clock
.n
++) {
634 for (clock
.p1
= limit
->p1
.min
;
635 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
638 i9xx_clock(refclk
, &clock
);
639 if (!intel_PLL_is_valid(dev
, limit
,
643 clock
.p
!= match_clock
->p
)
646 this_err
= abs(clock
.dot
- target
);
647 if (this_err
< err
) {
656 return (err
!= target
);
660 pnv_find_best_dpll(const intel_limit_t
*limit
, struct intel_crtc
*crtc
,
661 int target
, int refclk
, intel_clock_t
*match_clock
,
662 intel_clock_t
*best_clock
)
664 struct drm_device
*dev
= crtc
->base
.dev
;
668 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
)) {
670 * For LVDS just rely on its current settings for dual-channel.
671 * We haven't figured out how to reliably set up different
672 * single/dual channel state, if we even can.
674 if (intel_is_dual_link_lvds(dev
))
675 clock
.p2
= limit
->p2
.p2_fast
;
677 clock
.p2
= limit
->p2
.p2_slow
;
679 if (target
< limit
->p2
.dot_limit
)
680 clock
.p2
= limit
->p2
.p2_slow
;
682 clock
.p2
= limit
->p2
.p2_fast
;
685 memset(best_clock
, 0, sizeof(*best_clock
));
687 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
689 for (clock
.m2
= limit
->m2
.min
;
690 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
691 for (clock
.n
= limit
->n
.min
;
692 clock
.n
<= limit
->n
.max
; clock
.n
++) {
693 for (clock
.p1
= limit
->p1
.min
;
694 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
697 pineview_clock(refclk
, &clock
);
698 if (!intel_PLL_is_valid(dev
, limit
,
702 clock
.p
!= match_clock
->p
)
705 this_err
= abs(clock
.dot
- target
);
706 if (this_err
< err
) {
715 return (err
!= target
);
719 g4x_find_best_dpll(const intel_limit_t
*limit
, struct intel_crtc
*crtc
,
720 int target
, int refclk
, intel_clock_t
*match_clock
,
721 intel_clock_t
*best_clock
)
723 struct drm_device
*dev
= crtc
->base
.dev
;
727 /* approximately equals target * 0.00585 */
728 int err_most
= (target
>> 8) + (target
>> 9);
731 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
)) {
732 if (intel_is_dual_link_lvds(dev
))
733 clock
.p2
= limit
->p2
.p2_fast
;
735 clock
.p2
= limit
->p2
.p2_slow
;
737 if (target
< limit
->p2
.dot_limit
)
738 clock
.p2
= limit
->p2
.p2_slow
;
740 clock
.p2
= limit
->p2
.p2_fast
;
743 memset(best_clock
, 0, sizeof(*best_clock
));
744 max_n
= limit
->n
.max
;
745 /* based on hardware requirement, prefer smaller n to precision */
746 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
747 /* based on hardware requirement, prefere larger m1,m2 */
748 for (clock
.m1
= limit
->m1
.max
;
749 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
750 for (clock
.m2
= limit
->m2
.max
;
751 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
752 for (clock
.p1
= limit
->p1
.max
;
753 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
756 i9xx_clock(refclk
, &clock
);
757 if (!intel_PLL_is_valid(dev
, limit
,
761 this_err
= abs(clock
.dot
- target
);
762 if (this_err
< err_most
) {
776 vlv_find_best_dpll(const intel_limit_t
*limit
, struct intel_crtc
*crtc
,
777 int target
, int refclk
, intel_clock_t
*match_clock
,
778 intel_clock_t
*best_clock
)
780 struct drm_device
*dev
= crtc
->base
.dev
;
782 unsigned int bestppm
= 1000000;
783 /* min update 19.2 MHz */
784 int max_n
= min(limit
->n
.max
, refclk
/ 19200);
787 target
*= 5; /* fast clock */
789 memset(best_clock
, 0, sizeof(*best_clock
));
791 /* based on hardware requirement, prefer smaller n to precision */
792 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
793 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
794 for (clock
.p2
= limit
->p2
.p2_fast
; clock
.p2
>= limit
->p2
.p2_slow
;
795 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
796 clock
.p
= clock
.p1
* clock
.p2
;
797 /* based on hardware requirement, prefer bigger m1,m2 values */
798 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
; clock
.m1
++) {
799 unsigned int ppm
, diff
;
801 clock
.m2
= DIV_ROUND_CLOSEST(target
* clock
.p
* clock
.n
,
804 vlv_clock(refclk
, &clock
);
806 if (!intel_PLL_is_valid(dev
, limit
,
810 diff
= abs(clock
.dot
- target
);
811 ppm
= div_u64(1000000ULL * diff
, target
);
813 if (ppm
< 100 && clock
.p
> best_clock
->p
) {
819 if (bestppm
>= 10 && ppm
< bestppm
- 10) {
833 chv_find_best_dpll(const intel_limit_t
*limit
, struct intel_crtc
*crtc
,
834 int target
, int refclk
, intel_clock_t
*match_clock
,
835 intel_clock_t
*best_clock
)
837 struct drm_device
*dev
= crtc
->base
.dev
;
842 memset(best_clock
, 0, sizeof(*best_clock
));
845 * Based on hardware doc, the n always set to 1, and m1 always
846 * set to 2. If requires to support 200Mhz refclk, we need to
847 * revisit this because n may not 1 anymore.
849 clock
.n
= 1, clock
.m1
= 2;
850 target
*= 5; /* fast clock */
852 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
853 for (clock
.p2
= limit
->p2
.p2_fast
;
854 clock
.p2
>= limit
->p2
.p2_slow
;
855 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
857 clock
.p
= clock
.p1
* clock
.p2
;
859 m2
= DIV_ROUND_CLOSEST_ULL(((uint64_t)target
* clock
.p
*
860 clock
.n
) << 22, refclk
* clock
.m1
);
862 if (m2
> INT_MAX
/clock
.m1
)
867 chv_clock(refclk
, &clock
);
869 if (!intel_PLL_is_valid(dev
, limit
, &clock
))
872 /* based on hardware requirement, prefer bigger p
874 if (clock
.p
> best_clock
->p
) {
884 bool intel_crtc_active(struct drm_crtc
*crtc
)
886 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
888 /* Be paranoid as we can arrive here with only partial
889 * state retrieved from the hardware during setup.
891 * We can ditch the adjusted_mode.crtc_clock check as soon
892 * as Haswell has gained clock readout/fastboot support.
894 * We can ditch the crtc->primary->fb check as soon as we can
895 * properly reconstruct framebuffers.
897 return intel_crtc
->active
&& crtc
->primary
->fb
&&
898 intel_crtc
->config
.adjusted_mode
.crtc_clock
;
901 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
904 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
905 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
907 return intel_crtc
->config
.cpu_transcoder
;
910 static bool pipe_dsl_stopped(struct drm_device
*dev
, enum pipe pipe
)
912 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
913 u32 reg
= PIPEDSL(pipe
);
918 line_mask
= DSL_LINEMASK_GEN2
;
920 line_mask
= DSL_LINEMASK_GEN3
;
922 line1
= I915_READ(reg
) & line_mask
;
924 line2
= I915_READ(reg
) & line_mask
;
926 return line1
== line2
;
930 * intel_wait_for_pipe_off - wait for pipe to turn off
931 * @crtc: crtc whose pipe to wait for
933 * After disabling a pipe, we can't wait for vblank in the usual way,
934 * spinning on the vblank interrupt status bit, since we won't actually
935 * see an interrupt when the pipe is disabled.
938 * wait for the pipe register state bit to turn off
941 * wait for the display line value to settle (it usually
942 * ends up stopping at the start of the next frame).
945 static void intel_wait_for_pipe_off(struct intel_crtc
*crtc
)
947 struct drm_device
*dev
= crtc
->base
.dev
;
948 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
949 enum transcoder cpu_transcoder
= crtc
->config
.cpu_transcoder
;
950 enum pipe pipe
= crtc
->pipe
;
952 if (INTEL_INFO(dev
)->gen
>= 4) {
953 int reg
= PIPECONF(cpu_transcoder
);
955 /* Wait for the Pipe State to go off */
956 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
958 WARN(1, "pipe_off wait timed out\n");
960 /* Wait for the display line to settle */
961 if (wait_for(pipe_dsl_stopped(dev
, pipe
), 100))
962 WARN(1, "pipe_off wait timed out\n");
967 * ibx_digital_port_connected - is the specified port connected?
968 * @dev_priv: i915 private structure
969 * @port: the port to test
971 * Returns true if @port is connected, false otherwise.
973 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
974 struct intel_digital_port
*port
)
978 if (HAS_PCH_IBX(dev_priv
->dev
)) {
979 switch (port
->port
) {
981 bit
= SDE_PORTB_HOTPLUG
;
984 bit
= SDE_PORTC_HOTPLUG
;
987 bit
= SDE_PORTD_HOTPLUG
;
993 switch (port
->port
) {
995 bit
= SDE_PORTB_HOTPLUG_CPT
;
998 bit
= SDE_PORTC_HOTPLUG_CPT
;
1001 bit
= SDE_PORTD_HOTPLUG_CPT
;
1008 return I915_READ(SDEISR
) & bit
;
1011 static const char *state_string(bool enabled
)
1013 return enabled
? "on" : "off";
1016 /* Only for pre-ILK configs */
1017 void assert_pll(struct drm_i915_private
*dev_priv
,
1018 enum pipe pipe
, bool state
)
1025 val
= I915_READ(reg
);
1026 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1027 WARN(cur_state
!= state
,
1028 "PLL state assertion failure (expected %s, current %s)\n",
1029 state_string(state
), state_string(cur_state
));
1032 /* XXX: the dsi pll is shared between MIPI DSI ports */
1033 static void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
)
1038 mutex_lock(&dev_priv
->dpio_lock
);
1039 val
= vlv_cck_read(dev_priv
, CCK_REG_DSI_PLL_CONTROL
);
1040 mutex_unlock(&dev_priv
->dpio_lock
);
1042 cur_state
= val
& DSI_PLL_VCO_EN
;
1043 WARN(cur_state
!= state
,
1044 "DSI PLL state assertion failure (expected %s, current %s)\n",
1045 state_string(state
), state_string(cur_state
));
1047 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1048 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1050 struct intel_shared_dpll
*
1051 intel_crtc_to_shared_dpll(struct intel_crtc
*crtc
)
1053 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1055 if (crtc
->config
.shared_dpll
< 0)
1058 return &dev_priv
->shared_dplls
[crtc
->config
.shared_dpll
];
1062 void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
1063 struct intel_shared_dpll
*pll
,
1067 struct intel_dpll_hw_state hw_state
;
1070 "asserting DPLL %s with no DPLL\n", state_string(state
)))
1073 cur_state
= pll
->get_hw_state(dev_priv
, pll
, &hw_state
);
1074 WARN(cur_state
!= state
,
1075 "%s assertion failure (expected %s, current %s)\n",
1076 pll
->name
, state_string(state
), state_string(cur_state
));
1079 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1080 enum pipe pipe
, bool state
)
1085 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1088 if (HAS_DDI(dev_priv
->dev
)) {
1089 /* DDI does not have a specific FDI_TX register */
1090 reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1091 val
= I915_READ(reg
);
1092 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
1094 reg
= FDI_TX_CTL(pipe
);
1095 val
= I915_READ(reg
);
1096 cur_state
= !!(val
& FDI_TX_ENABLE
);
1098 WARN(cur_state
!= state
,
1099 "FDI TX state assertion failure (expected %s, current %s)\n",
1100 state_string(state
), state_string(cur_state
));
1102 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1103 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1105 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1106 enum pipe pipe
, bool state
)
1112 reg
= FDI_RX_CTL(pipe
);
1113 val
= I915_READ(reg
);
1114 cur_state
= !!(val
& FDI_RX_ENABLE
);
1115 WARN(cur_state
!= state
,
1116 "FDI RX state assertion failure (expected %s, current %s)\n",
1117 state_string(state
), state_string(cur_state
));
1119 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1120 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1122 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1128 /* ILK FDI PLL is always enabled */
1129 if (INTEL_INFO(dev_priv
->dev
)->gen
== 5)
1132 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1133 if (HAS_DDI(dev_priv
->dev
))
1136 reg
= FDI_TX_CTL(pipe
);
1137 val
= I915_READ(reg
);
1138 WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1141 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1142 enum pipe pipe
, bool state
)
1148 reg
= FDI_RX_CTL(pipe
);
1149 val
= I915_READ(reg
);
1150 cur_state
= !!(val
& FDI_RX_PLL_ENABLE
);
1151 WARN(cur_state
!= state
,
1152 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1153 state_string(state
), state_string(cur_state
));
1156 void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1159 struct drm_device
*dev
= dev_priv
->dev
;
1162 enum pipe panel_pipe
= PIPE_A
;
1165 if (WARN_ON(HAS_DDI(dev
)))
1168 if (HAS_PCH_SPLIT(dev
)) {
1171 pp_reg
= PCH_PP_CONTROL
;
1172 port_sel
= I915_READ(PCH_PP_ON_DELAYS
) & PANEL_PORT_SELECT_MASK
;
1174 if (port_sel
== PANEL_PORT_SELECT_LVDS
&&
1175 I915_READ(PCH_LVDS
) & LVDS_PIPEB_SELECT
)
1176 panel_pipe
= PIPE_B
;
1177 /* XXX: else fix for eDP */
1178 } else if (IS_VALLEYVIEW(dev
)) {
1179 /* presumably write lock depends on pipe, not port select */
1180 pp_reg
= VLV_PIPE_PP_CONTROL(pipe
);
1183 pp_reg
= PP_CONTROL
;
1184 if (I915_READ(LVDS
) & LVDS_PIPEB_SELECT
)
1185 panel_pipe
= PIPE_B
;
1188 val
= I915_READ(pp_reg
);
1189 if (!(val
& PANEL_POWER_ON
) ||
1190 ((val
& PANEL_UNLOCK_MASK
) == PANEL_UNLOCK_REGS
))
1193 WARN(panel_pipe
== pipe
&& locked
,
1194 "panel assertion failure, pipe %c regs locked\n",
1198 static void assert_cursor(struct drm_i915_private
*dev_priv
,
1199 enum pipe pipe
, bool state
)
1201 struct drm_device
*dev
= dev_priv
->dev
;
1204 if (IS_845G(dev
) || IS_I865G(dev
))
1205 cur_state
= I915_READ(_CURACNTR
) & CURSOR_ENABLE
;
1207 cur_state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
1209 WARN(cur_state
!= state
,
1210 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1211 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1213 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1214 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1216 void assert_pipe(struct drm_i915_private
*dev_priv
,
1217 enum pipe pipe
, bool state
)
1222 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1225 /* if we need the pipe quirk it must be always on */
1226 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1227 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1230 if (!intel_display_power_is_enabled(dev_priv
,
1231 POWER_DOMAIN_TRANSCODER(cpu_transcoder
))) {
1234 reg
= PIPECONF(cpu_transcoder
);
1235 val
= I915_READ(reg
);
1236 cur_state
= !!(val
& PIPECONF_ENABLE
);
1239 WARN(cur_state
!= state
,
1240 "pipe %c assertion failure (expected %s, current %s)\n",
1241 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1244 static void assert_plane(struct drm_i915_private
*dev_priv
,
1245 enum plane plane
, bool state
)
1251 reg
= DSPCNTR(plane
);
1252 val
= I915_READ(reg
);
1253 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1254 WARN(cur_state
!= state
,
1255 "plane %c assertion failure (expected %s, current %s)\n",
1256 plane_name(plane
), state_string(state
), state_string(cur_state
));
1259 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1260 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1262 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1265 struct drm_device
*dev
= dev_priv
->dev
;
1270 /* Primary planes are fixed to pipes on gen4+ */
1271 if (INTEL_INFO(dev
)->gen
>= 4) {
1272 reg
= DSPCNTR(pipe
);
1273 val
= I915_READ(reg
);
1274 WARN(val
& DISPLAY_PLANE_ENABLE
,
1275 "plane %c assertion failure, should be disabled but not\n",
1280 /* Need to check both planes against the pipe */
1281 for_each_pipe(dev_priv
, i
) {
1283 val
= I915_READ(reg
);
1284 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1285 DISPPLANE_SEL_PIPE_SHIFT
;
1286 WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1287 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1288 plane_name(i
), pipe_name(pipe
));
1292 static void assert_sprites_disabled(struct drm_i915_private
*dev_priv
,
1295 struct drm_device
*dev
= dev_priv
->dev
;
1299 if (INTEL_INFO(dev
)->gen
>= 9) {
1300 for_each_sprite(pipe
, sprite
) {
1301 val
= I915_READ(PLANE_CTL(pipe
, sprite
));
1302 WARN(val
& PLANE_CTL_ENABLE
,
1303 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1304 sprite
, pipe_name(pipe
));
1306 } else if (IS_VALLEYVIEW(dev
)) {
1307 for_each_sprite(pipe
, sprite
) {
1308 reg
= SPCNTR(pipe
, sprite
);
1309 val
= I915_READ(reg
);
1310 WARN(val
& SP_ENABLE
,
1311 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1312 sprite_name(pipe
, sprite
), pipe_name(pipe
));
1314 } else if (INTEL_INFO(dev
)->gen
>= 7) {
1316 val
= I915_READ(reg
);
1317 WARN(val
& SPRITE_ENABLE
,
1318 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1319 plane_name(pipe
), pipe_name(pipe
));
1320 } else if (INTEL_INFO(dev
)->gen
>= 5) {
1321 reg
= DVSCNTR(pipe
);
1322 val
= I915_READ(reg
);
1323 WARN(val
& DVS_ENABLE
,
1324 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1325 plane_name(pipe
), pipe_name(pipe
));
1329 static void assert_vblank_disabled(struct drm_crtc
*crtc
)
1331 if (WARN_ON(drm_crtc_vblank_get(crtc
) == 0))
1332 drm_crtc_vblank_put(crtc
);
1335 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1340 WARN_ON(!(HAS_PCH_IBX(dev_priv
->dev
) || HAS_PCH_CPT(dev_priv
->dev
)));
1342 val
= I915_READ(PCH_DREF_CONTROL
);
1343 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1344 DREF_SUPERSPREAD_SOURCE_MASK
));
1345 WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1348 static void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1355 reg
= PCH_TRANSCONF(pipe
);
1356 val
= I915_READ(reg
);
1357 enabled
= !!(val
& TRANS_ENABLE
);
1359 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1363 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1364 enum pipe pipe
, u32 port_sel
, u32 val
)
1366 if ((val
& DP_PORT_EN
) == 0)
1369 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1370 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1371 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1372 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1374 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1375 if ((val
& DP_PIPE_MASK_CHV
) != DP_PIPE_SELECT_CHV(pipe
))
1378 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1384 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1385 enum pipe pipe
, u32 val
)
1387 if ((val
& SDVO_ENABLE
) == 0)
1390 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1391 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1393 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1394 if ((val
& SDVO_PIPE_SEL_MASK_CHV
) != SDVO_PIPE_SEL_CHV(pipe
))
1397 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1403 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1404 enum pipe pipe
, u32 val
)
1406 if ((val
& LVDS_PORT_EN
) == 0)
1409 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1410 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1413 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1419 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1420 enum pipe pipe
, u32 val
)
1422 if ((val
& ADPA_DAC_ENABLE
) == 0)
1424 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1425 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1428 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1434 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1435 enum pipe pipe
, int reg
, u32 port_sel
)
1437 u32 val
= I915_READ(reg
);
1438 WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1439 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1440 reg
, pipe_name(pipe
));
1442 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& DP_PORT_EN
) == 0
1443 && (val
& DP_PIPEB_SELECT
),
1444 "IBX PCH dp port still using transcoder B\n");
1447 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1448 enum pipe pipe
, int reg
)
1450 u32 val
= I915_READ(reg
);
1451 WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1452 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1453 reg
, pipe_name(pipe
));
1455 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& SDVO_ENABLE
) == 0
1456 && (val
& SDVO_PIPE_B_SELECT
),
1457 "IBX PCH hdmi port still using transcoder B\n");
1460 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1466 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1467 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1468 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1471 val
= I915_READ(reg
);
1472 WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1473 "PCH VGA enabled on transcoder %c, should be disabled\n",
1477 val
= I915_READ(reg
);
1478 WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1479 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1482 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1483 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1484 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1487 static void intel_init_dpio(struct drm_device
*dev
)
1489 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1491 if (!IS_VALLEYVIEW(dev
))
1495 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1496 * CHV x1 PHY (DP/HDMI D)
1497 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1499 if (IS_CHERRYVIEW(dev
)) {
1500 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO_2
;
1501 DPIO_PHY_IOSF_PORT(DPIO_PHY1
) = IOSF_PORT_DPIO
;
1503 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO
;
1507 static void vlv_enable_pll(struct intel_crtc
*crtc
,
1508 const struct intel_crtc_config
*pipe_config
)
1510 struct drm_device
*dev
= crtc
->base
.dev
;
1511 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1512 int reg
= DPLL(crtc
->pipe
);
1513 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
1515 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1517 /* No really, not for ILK+ */
1518 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
));
1520 /* PLL is protected by panel, make sure we can write it */
1521 if (IS_MOBILE(dev_priv
->dev
))
1522 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1524 I915_WRITE(reg
, dpll
);
1528 if (wait_for(((I915_READ(reg
) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1529 DRM_ERROR("DPLL %d failed to lock\n", crtc
->pipe
);
1531 I915_WRITE(DPLL_MD(crtc
->pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1532 POSTING_READ(DPLL_MD(crtc
->pipe
));
1534 /* We do this three times for luck */
1535 I915_WRITE(reg
, dpll
);
1537 udelay(150); /* wait for warmup */
1538 I915_WRITE(reg
, dpll
);
1540 udelay(150); /* wait for warmup */
1541 I915_WRITE(reg
, dpll
);
1543 udelay(150); /* wait for warmup */
1546 static void chv_enable_pll(struct intel_crtc
*crtc
,
1547 const struct intel_crtc_config
*pipe_config
)
1549 struct drm_device
*dev
= crtc
->base
.dev
;
1550 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1551 int pipe
= crtc
->pipe
;
1552 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1555 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1557 BUG_ON(!IS_CHERRYVIEW(dev_priv
->dev
));
1559 mutex_lock(&dev_priv
->dpio_lock
);
1561 /* Enable back the 10bit clock to display controller */
1562 tmp
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1563 tmp
|= DPIO_DCLKP_EN
;
1564 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), tmp
);
1567 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1572 I915_WRITE(DPLL(pipe
), pipe_config
->dpll_hw_state
.dpll
);
1574 /* Check PLL is locked */
1575 if (wait_for(((I915_READ(DPLL(pipe
)) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1576 DRM_ERROR("PLL %d failed to lock\n", pipe
);
1578 /* not sure when this should be written */
1579 I915_WRITE(DPLL_MD(pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1580 POSTING_READ(DPLL_MD(pipe
));
1582 mutex_unlock(&dev_priv
->dpio_lock
);
1585 static int intel_num_dvo_pipes(struct drm_device
*dev
)
1587 struct intel_crtc
*crtc
;
1590 for_each_intel_crtc(dev
, crtc
)
1591 count
+= crtc
->active
&&
1592 intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
);
1597 static void i9xx_enable_pll(struct intel_crtc
*crtc
)
1599 struct drm_device
*dev
= crtc
->base
.dev
;
1600 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1601 int reg
= DPLL(crtc
->pipe
);
1602 u32 dpll
= crtc
->config
.dpll_hw_state
.dpll
;
1604 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1606 /* No really, not for ILK+ */
1607 BUG_ON(INTEL_INFO(dev
)->gen
>= 5);
1609 /* PLL is protected by panel, make sure we can write it */
1610 if (IS_MOBILE(dev
) && !IS_I830(dev
))
1611 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1613 /* Enable DVO 2x clock on both PLLs if necessary */
1614 if (IS_I830(dev
) && intel_num_dvo_pipes(dev
) > 0) {
1616 * It appears to be important that we don't enable this
1617 * for the current pipe before otherwise configuring the
1618 * PLL. No idea how this should be handled if multiple
1619 * DVO outputs are enabled simultaneosly.
1621 dpll
|= DPLL_DVO_2X_MODE
;
1622 I915_WRITE(DPLL(!crtc
->pipe
),
1623 I915_READ(DPLL(!crtc
->pipe
)) | DPLL_DVO_2X_MODE
);
1626 /* Wait for the clocks to stabilize. */
1630 if (INTEL_INFO(dev
)->gen
>= 4) {
1631 I915_WRITE(DPLL_MD(crtc
->pipe
),
1632 crtc
->config
.dpll_hw_state
.dpll_md
);
1634 /* The pixel multiplier can only be updated once the
1635 * DPLL is enabled and the clocks are stable.
1637 * So write it again.
1639 I915_WRITE(reg
, dpll
);
1642 /* We do this three times for luck */
1643 I915_WRITE(reg
, dpll
);
1645 udelay(150); /* wait for warmup */
1646 I915_WRITE(reg
, dpll
);
1648 udelay(150); /* wait for warmup */
1649 I915_WRITE(reg
, dpll
);
1651 udelay(150); /* wait for warmup */
1655 * i9xx_disable_pll - disable a PLL
1656 * @dev_priv: i915 private structure
1657 * @pipe: pipe PLL to disable
1659 * Disable the PLL for @pipe, making sure the pipe is off first.
1661 * Note! This is for pre-ILK only.
1663 static void i9xx_disable_pll(struct intel_crtc
*crtc
)
1665 struct drm_device
*dev
= crtc
->base
.dev
;
1666 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1667 enum pipe pipe
= crtc
->pipe
;
1669 /* Disable DVO 2x clock on both PLLs if necessary */
1671 intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
) &&
1672 intel_num_dvo_pipes(dev
) == 1) {
1673 I915_WRITE(DPLL(PIPE_B
),
1674 I915_READ(DPLL(PIPE_B
)) & ~DPLL_DVO_2X_MODE
);
1675 I915_WRITE(DPLL(PIPE_A
),
1676 I915_READ(DPLL(PIPE_A
)) & ~DPLL_DVO_2X_MODE
);
1679 /* Don't disable pipe or pipe PLLs if needed */
1680 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1681 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1684 /* Make sure the pipe isn't still relying on us */
1685 assert_pipe_disabled(dev_priv
, pipe
);
1687 I915_WRITE(DPLL(pipe
), 0);
1688 POSTING_READ(DPLL(pipe
));
1691 static void vlv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1695 /* Make sure the pipe isn't still relying on us */
1696 assert_pipe_disabled(dev_priv
, pipe
);
1699 * Leave integrated clock source and reference clock enabled for pipe B.
1700 * The latter is needed for VGA hotplug / manual detection.
1703 val
= DPLL_INTEGRATED_CRI_CLK_VLV
| DPLL_REFA_CLK_ENABLE_VLV
;
1704 I915_WRITE(DPLL(pipe
), val
);
1705 POSTING_READ(DPLL(pipe
));
1709 static void chv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1711 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1714 /* Make sure the pipe isn't still relying on us */
1715 assert_pipe_disabled(dev_priv
, pipe
);
1717 /* Set PLL en = 0 */
1718 val
= DPLL_SSC_REF_CLOCK_CHV
| DPLL_REFA_CLK_ENABLE_VLV
;
1720 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
1721 I915_WRITE(DPLL(pipe
), val
);
1722 POSTING_READ(DPLL(pipe
));
1724 mutex_lock(&dev_priv
->dpio_lock
);
1726 /* Disable 10bit clock to display controller */
1727 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1728 val
&= ~DPIO_DCLKP_EN
;
1729 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), val
);
1731 /* disable left/right clock distribution */
1732 if (pipe
!= PIPE_B
) {
1733 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
);
1734 val
&= ~(CHV_BUFLEFTENA1_MASK
| CHV_BUFRIGHTENA1_MASK
);
1735 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
, val
);
1737 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
);
1738 val
&= ~(CHV_BUFLEFTENA2_MASK
| CHV_BUFRIGHTENA2_MASK
);
1739 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
, val
);
1742 mutex_unlock(&dev_priv
->dpio_lock
);
1745 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1746 struct intel_digital_port
*dport
)
1751 switch (dport
->port
) {
1753 port_mask
= DPLL_PORTB_READY_MASK
;
1757 port_mask
= DPLL_PORTC_READY_MASK
;
1761 port_mask
= DPLL_PORTD_READY_MASK
;
1762 dpll_reg
= DPIO_PHY_STATUS
;
1768 if (wait_for((I915_READ(dpll_reg
) & port_mask
) == 0, 1000))
1769 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1770 port_name(dport
->port
), I915_READ(dpll_reg
));
1773 static void intel_prepare_shared_dpll(struct intel_crtc
*crtc
)
1775 struct drm_device
*dev
= crtc
->base
.dev
;
1776 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1777 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1779 if (WARN_ON(pll
== NULL
))
1782 WARN_ON(!pll
->config
.crtc_mask
);
1783 if (pll
->active
== 0) {
1784 DRM_DEBUG_DRIVER("setting up %s\n", pll
->name
);
1786 assert_shared_dpll_disabled(dev_priv
, pll
);
1788 pll
->mode_set(dev_priv
, pll
);
1793 * intel_enable_shared_dpll - enable PCH PLL
1794 * @dev_priv: i915 private structure
1795 * @pipe: pipe PLL to enable
1797 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1798 * drives the transcoder clock.
1800 static void intel_enable_shared_dpll(struct intel_crtc
*crtc
)
1802 struct drm_device
*dev
= crtc
->base
.dev
;
1803 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1804 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1806 if (WARN_ON(pll
== NULL
))
1809 if (WARN_ON(pll
->config
.crtc_mask
== 0))
1812 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1813 pll
->name
, pll
->active
, pll
->on
,
1814 crtc
->base
.base
.id
);
1816 if (pll
->active
++) {
1818 assert_shared_dpll_enabled(dev_priv
, pll
);
1823 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
1825 DRM_DEBUG_KMS("enabling %s\n", pll
->name
);
1826 pll
->enable(dev_priv
, pll
);
1830 static void intel_disable_shared_dpll(struct intel_crtc
*crtc
)
1832 struct drm_device
*dev
= crtc
->base
.dev
;
1833 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1834 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1836 /* PCH only available on ILK+ */
1837 BUG_ON(INTEL_INFO(dev
)->gen
< 5);
1838 if (WARN_ON(pll
== NULL
))
1841 if (WARN_ON(pll
->config
.crtc_mask
== 0))
1844 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1845 pll
->name
, pll
->active
, pll
->on
,
1846 crtc
->base
.base
.id
);
1848 if (WARN_ON(pll
->active
== 0)) {
1849 assert_shared_dpll_disabled(dev_priv
, pll
);
1853 assert_shared_dpll_enabled(dev_priv
, pll
);
1858 DRM_DEBUG_KMS("disabling %s\n", pll
->name
);
1859 pll
->disable(dev_priv
, pll
);
1862 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
1865 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1868 struct drm_device
*dev
= dev_priv
->dev
;
1869 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1870 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1871 uint32_t reg
, val
, pipeconf_val
;
1873 /* PCH only available on ILK+ */
1874 BUG_ON(!HAS_PCH_SPLIT(dev
));
1876 /* Make sure PCH DPLL is enabled */
1877 assert_shared_dpll_enabled(dev_priv
,
1878 intel_crtc_to_shared_dpll(intel_crtc
));
1880 /* FDI must be feeding us bits for PCH ports */
1881 assert_fdi_tx_enabled(dev_priv
, pipe
);
1882 assert_fdi_rx_enabled(dev_priv
, pipe
);
1884 if (HAS_PCH_CPT(dev
)) {
1885 /* Workaround: Set the timing override bit before enabling the
1886 * pch transcoder. */
1887 reg
= TRANS_CHICKEN2(pipe
);
1888 val
= I915_READ(reg
);
1889 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1890 I915_WRITE(reg
, val
);
1893 reg
= PCH_TRANSCONF(pipe
);
1894 val
= I915_READ(reg
);
1895 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1897 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1899 * make the BPC in transcoder be consistent with
1900 * that in pipeconf reg.
1902 val
&= ~PIPECONF_BPC_MASK
;
1903 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
1906 val
&= ~TRANS_INTERLACE_MASK
;
1907 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1908 if (HAS_PCH_IBX(dev_priv
->dev
) &&
1909 intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
1910 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1912 val
|= TRANS_INTERLACED
;
1914 val
|= TRANS_PROGRESSIVE
;
1916 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1917 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1918 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
1921 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1922 enum transcoder cpu_transcoder
)
1924 u32 val
, pipeconf_val
;
1926 /* PCH only available on ILK+ */
1927 BUG_ON(!HAS_PCH_SPLIT(dev_priv
->dev
));
1929 /* FDI must be feeding us bits for PCH ports */
1930 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
1931 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
1933 /* Workaround: set timing override bit. */
1934 val
= I915_READ(_TRANSA_CHICKEN2
);
1935 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1936 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1939 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
1941 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
1942 PIPECONF_INTERLACED_ILK
)
1943 val
|= TRANS_INTERLACED
;
1945 val
|= TRANS_PROGRESSIVE
;
1947 I915_WRITE(LPT_TRANSCONF
, val
);
1948 if (wait_for(I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
, 100))
1949 DRM_ERROR("Failed to enable PCH transcoder\n");
1952 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1955 struct drm_device
*dev
= dev_priv
->dev
;
1958 /* FDI relies on the transcoder */
1959 assert_fdi_tx_disabled(dev_priv
, pipe
);
1960 assert_fdi_rx_disabled(dev_priv
, pipe
);
1962 /* Ports must be off as well */
1963 assert_pch_ports_disabled(dev_priv
, pipe
);
1965 reg
= PCH_TRANSCONF(pipe
);
1966 val
= I915_READ(reg
);
1967 val
&= ~TRANS_ENABLE
;
1968 I915_WRITE(reg
, val
);
1969 /* wait for PCH transcoder off, transcoder state */
1970 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
1971 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
1973 if (!HAS_PCH_IBX(dev
)) {
1974 /* Workaround: Clear the timing override chicken bit again. */
1975 reg
= TRANS_CHICKEN2(pipe
);
1976 val
= I915_READ(reg
);
1977 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1978 I915_WRITE(reg
, val
);
1982 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
1986 val
= I915_READ(LPT_TRANSCONF
);
1987 val
&= ~TRANS_ENABLE
;
1988 I915_WRITE(LPT_TRANSCONF
, val
);
1989 /* wait for PCH transcoder off, transcoder state */
1990 if (wait_for((I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
) == 0, 50))
1991 DRM_ERROR("Failed to disable PCH transcoder\n");
1993 /* Workaround: clear timing override bit. */
1994 val
= I915_READ(_TRANSA_CHICKEN2
);
1995 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1996 I915_WRITE(_TRANSA_CHICKEN2
, val
);
2000 * intel_enable_pipe - enable a pipe, asserting requirements
2001 * @crtc: crtc responsible for the pipe
2003 * Enable @crtc's pipe, making sure that various hardware specific requirements
2004 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2006 static void intel_enable_pipe(struct intel_crtc
*crtc
)
2008 struct drm_device
*dev
= crtc
->base
.dev
;
2009 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2010 enum pipe pipe
= crtc
->pipe
;
2011 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
2013 enum pipe pch_transcoder
;
2017 assert_planes_disabled(dev_priv
, pipe
);
2018 assert_cursor_disabled(dev_priv
, pipe
);
2019 assert_sprites_disabled(dev_priv
, pipe
);
2021 if (HAS_PCH_LPT(dev_priv
->dev
))
2022 pch_transcoder
= TRANSCODER_A
;
2024 pch_transcoder
= pipe
;
2027 * A pipe without a PLL won't actually be able to drive bits from
2028 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2031 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
2032 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
))
2033 assert_dsi_pll_enabled(dev_priv
);
2035 assert_pll_enabled(dev_priv
, pipe
);
2037 if (crtc
->config
.has_pch_encoder
) {
2038 /* if driving the PCH, we need FDI enabled */
2039 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
2040 assert_fdi_tx_pll_enabled(dev_priv
,
2041 (enum pipe
) cpu_transcoder
);
2043 /* FIXME: assert CPU port conditions for SNB+ */
2046 reg
= PIPECONF(cpu_transcoder
);
2047 val
= I915_READ(reg
);
2048 if (val
& PIPECONF_ENABLE
) {
2049 WARN_ON(!((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
2050 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
)));
2054 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
2059 * intel_disable_pipe - disable a pipe, asserting requirements
2060 * @crtc: crtc whose pipes is to be disabled
2062 * Disable the pipe of @crtc, making sure that various hardware
2063 * specific requirements are met, if applicable, e.g. plane
2064 * disabled, panel fitter off, etc.
2066 * Will wait until the pipe has shut down before returning.
2068 static void intel_disable_pipe(struct intel_crtc
*crtc
)
2070 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
2071 enum transcoder cpu_transcoder
= crtc
->config
.cpu_transcoder
;
2072 enum pipe pipe
= crtc
->pipe
;
2077 * Make sure planes won't keep trying to pump pixels to us,
2078 * or we might hang the display.
2080 assert_planes_disabled(dev_priv
, pipe
);
2081 assert_cursor_disabled(dev_priv
, pipe
);
2082 assert_sprites_disabled(dev_priv
, pipe
);
2084 reg
= PIPECONF(cpu_transcoder
);
2085 val
= I915_READ(reg
);
2086 if ((val
& PIPECONF_ENABLE
) == 0)
2090 * Double wide has implications for planes
2091 * so best keep it disabled when not needed.
2093 if (crtc
->config
.double_wide
)
2094 val
&= ~PIPECONF_DOUBLE_WIDE
;
2096 /* Don't disable pipe or pipe PLLs if needed */
2097 if (!(pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) &&
2098 !(pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
2099 val
&= ~PIPECONF_ENABLE
;
2101 I915_WRITE(reg
, val
);
2102 if ((val
& PIPECONF_ENABLE
) == 0)
2103 intel_wait_for_pipe_off(crtc
);
2107 * Plane regs are double buffered, going from enabled->disabled needs a
2108 * trigger in order to latch. The display address reg provides this.
2110 void intel_flush_primary_plane(struct drm_i915_private
*dev_priv
,
2113 struct drm_device
*dev
= dev_priv
->dev
;
2114 u32 reg
= INTEL_INFO(dev
)->gen
>= 4 ? DSPSURF(plane
) : DSPADDR(plane
);
2116 I915_WRITE(reg
, I915_READ(reg
));
2121 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2122 * @plane: plane to be enabled
2123 * @crtc: crtc for the plane
2125 * Enable @plane on @crtc, making sure that the pipe is running first.
2127 static void intel_enable_primary_hw_plane(struct drm_plane
*plane
,
2128 struct drm_crtc
*crtc
)
2130 struct drm_device
*dev
= plane
->dev
;
2131 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2132 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2134 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2135 assert_pipe_enabled(dev_priv
, intel_crtc
->pipe
);
2137 if (intel_crtc
->primary_enabled
)
2140 intel_crtc
->primary_enabled
= true;
2142 dev_priv
->display
.update_primary_plane(crtc
, plane
->fb
,
2146 * BDW signals flip done immediately if the plane
2147 * is disabled, even if the plane enable is already
2148 * armed to occur at the next vblank :(
2150 if (IS_BROADWELL(dev
))
2151 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2155 * intel_disable_primary_hw_plane - disable the primary hardware plane
2156 * @plane: plane to be disabled
2157 * @crtc: crtc for the plane
2159 * Disable @plane on @crtc, making sure that the pipe is running first.
2161 static void intel_disable_primary_hw_plane(struct drm_plane
*plane
,
2162 struct drm_crtc
*crtc
)
2164 struct drm_device
*dev
= plane
->dev
;
2165 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2166 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2168 assert_pipe_enabled(dev_priv
, intel_crtc
->pipe
);
2170 if (!intel_crtc
->primary_enabled
)
2173 intel_crtc
->primary_enabled
= false;
2175 dev_priv
->display
.update_primary_plane(crtc
, plane
->fb
,
2179 static bool need_vtd_wa(struct drm_device
*dev
)
2181 #ifdef CONFIG_INTEL_IOMMU
2182 if (INTEL_INFO(dev
)->gen
>= 6 && intel_iommu_gfx_mapped
)
2188 static int intel_align_height(struct drm_device
*dev
, int height
, bool tiled
)
2192 tile_height
= tiled
? (IS_GEN2(dev
) ? 16 : 8) : 1;
2193 return ALIGN(height
, tile_height
);
2197 intel_pin_and_fence_fb_obj(struct drm_plane
*plane
,
2198 struct drm_framebuffer
*fb
,
2199 struct intel_engine_cs
*pipelined
)
2201 struct drm_device
*dev
= fb
->dev
;
2202 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2203 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2207 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
2209 switch (obj
->tiling_mode
) {
2210 case I915_TILING_NONE
:
2211 if (INTEL_INFO(dev
)->gen
>= 9)
2212 alignment
= 256 * 1024;
2213 else if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
2214 alignment
= 128 * 1024;
2215 else if (INTEL_INFO(dev
)->gen
>= 4)
2216 alignment
= 4 * 1024;
2218 alignment
= 64 * 1024;
2221 if (INTEL_INFO(dev
)->gen
>= 9)
2222 alignment
= 256 * 1024;
2224 /* pin() will align the object as required by fence */
2229 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2235 /* Note that the w/a also requires 64 PTE of padding following the
2236 * bo. We currently fill all unused PTE with the shadow page and so
2237 * we should always have valid PTE following the scanout preventing
2240 if (need_vtd_wa(dev
) && alignment
< 256 * 1024)
2241 alignment
= 256 * 1024;
2244 * Global gtt pte registers are special registers which actually forward
2245 * writes to a chunk of system memory. Which means that there is no risk
2246 * that the register values disappear as soon as we call
2247 * intel_runtime_pm_put(), so it is correct to wrap only the
2248 * pin/unpin/fence and not more.
2250 intel_runtime_pm_get(dev_priv
);
2252 dev_priv
->mm
.interruptible
= false;
2253 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
);
2255 goto err_interruptible
;
2257 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2258 * fence, whereas 965+ only requires a fence if using
2259 * framebuffer compression. For simplicity, we always install
2260 * a fence as the cost is not that onerous.
2262 ret
= i915_gem_object_get_fence(obj
);
2266 i915_gem_object_pin_fence(obj
);
2268 dev_priv
->mm
.interruptible
= true;
2269 intel_runtime_pm_put(dev_priv
);
2273 i915_gem_object_unpin_from_display_plane(obj
);
2275 dev_priv
->mm
.interruptible
= true;
2276 intel_runtime_pm_put(dev_priv
);
2280 void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
)
2282 WARN_ON(!mutex_is_locked(&obj
->base
.dev
->struct_mutex
));
2284 i915_gem_object_unpin_fence(obj
);
2285 i915_gem_object_unpin_from_display_plane(obj
);
2288 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2289 * is assumed to be a power-of-two. */
2290 unsigned long intel_gen4_compute_page_offset(int *x
, int *y
,
2291 unsigned int tiling_mode
,
2295 if (tiling_mode
!= I915_TILING_NONE
) {
2296 unsigned int tile_rows
, tiles
;
2301 tiles
= *x
/ (512/cpp
);
2304 return tile_rows
* pitch
* 8 + tiles
* 4096;
2306 unsigned int offset
;
2308 offset
= *y
* pitch
+ *x
* cpp
;
2310 *x
= (offset
& 4095) / cpp
;
2311 return offset
& -4096;
2315 int intel_format_to_fourcc(int format
)
2318 case DISPPLANE_8BPP
:
2319 return DRM_FORMAT_C8
;
2320 case DISPPLANE_BGRX555
:
2321 return DRM_FORMAT_XRGB1555
;
2322 case DISPPLANE_BGRX565
:
2323 return DRM_FORMAT_RGB565
;
2325 case DISPPLANE_BGRX888
:
2326 return DRM_FORMAT_XRGB8888
;
2327 case DISPPLANE_RGBX888
:
2328 return DRM_FORMAT_XBGR8888
;
2329 case DISPPLANE_BGRX101010
:
2330 return DRM_FORMAT_XRGB2101010
;
2331 case DISPPLANE_RGBX101010
:
2332 return DRM_FORMAT_XBGR2101010
;
2336 static bool intel_alloc_plane_obj(struct intel_crtc
*crtc
,
2337 struct intel_plane_config
*plane_config
)
2339 struct drm_device
*dev
= crtc
->base
.dev
;
2340 struct drm_i915_gem_object
*obj
= NULL
;
2341 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
2342 u32 base
= plane_config
->base
;
2344 if (plane_config
->size
== 0)
2347 obj
= i915_gem_object_create_stolen_for_preallocated(dev
, base
, base
,
2348 plane_config
->size
);
2352 if (plane_config
->tiled
) {
2353 obj
->tiling_mode
= I915_TILING_X
;
2354 obj
->stride
= crtc
->base
.primary
->fb
->pitches
[0];
2357 mode_cmd
.pixel_format
= crtc
->base
.primary
->fb
->pixel_format
;
2358 mode_cmd
.width
= crtc
->base
.primary
->fb
->width
;
2359 mode_cmd
.height
= crtc
->base
.primary
->fb
->height
;
2360 mode_cmd
.pitches
[0] = crtc
->base
.primary
->fb
->pitches
[0];
2362 mutex_lock(&dev
->struct_mutex
);
2364 if (intel_framebuffer_init(dev
, to_intel_framebuffer(crtc
->base
.primary
->fb
),
2366 DRM_DEBUG_KMS("intel fb init failed\n");
2370 obj
->frontbuffer_bits
= INTEL_FRONTBUFFER_PRIMARY(crtc
->pipe
);
2371 mutex_unlock(&dev
->struct_mutex
);
2373 DRM_DEBUG_KMS("plane fb obj %p\n", obj
);
2377 drm_gem_object_unreference(&obj
->base
);
2378 mutex_unlock(&dev
->struct_mutex
);
2382 static void intel_find_plane_obj(struct intel_crtc
*intel_crtc
,
2383 struct intel_plane_config
*plane_config
)
2385 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2386 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2388 struct intel_crtc
*i
;
2389 struct drm_i915_gem_object
*obj
;
2391 if (!intel_crtc
->base
.primary
->fb
)
2394 if (intel_alloc_plane_obj(intel_crtc
, plane_config
))
2397 kfree(intel_crtc
->base
.primary
->fb
);
2398 intel_crtc
->base
.primary
->fb
= NULL
;
2401 * Failed to alloc the obj, check to see if we should share
2402 * an fb with another CRTC instead
2404 for_each_crtc(dev
, c
) {
2405 i
= to_intel_crtc(c
);
2407 if (c
== &intel_crtc
->base
)
2413 obj
= intel_fb_obj(c
->primary
->fb
);
2417 if (i915_gem_obj_ggtt_offset(obj
) == plane_config
->base
) {
2418 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2419 dev_priv
->preserve_bios_swizzle
= true;
2421 drm_framebuffer_reference(c
->primary
->fb
);
2422 intel_crtc
->base
.primary
->fb
= c
->primary
->fb
;
2423 obj
->frontbuffer_bits
|= INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
);
2429 static void i9xx_update_primary_plane(struct drm_crtc
*crtc
,
2430 struct drm_framebuffer
*fb
,
2433 struct drm_device
*dev
= crtc
->dev
;
2434 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2435 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2436 struct drm_i915_gem_object
*obj
;
2437 int plane
= intel_crtc
->plane
;
2438 unsigned long linear_offset
;
2440 u32 reg
= DSPCNTR(plane
);
2443 if (!intel_crtc
->primary_enabled
) {
2445 if (INTEL_INFO(dev
)->gen
>= 4)
2446 I915_WRITE(DSPSURF(plane
), 0);
2448 I915_WRITE(DSPADDR(plane
), 0);
2453 obj
= intel_fb_obj(fb
);
2454 if (WARN_ON(obj
== NULL
))
2457 pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2459 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2461 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2463 if (INTEL_INFO(dev
)->gen
< 4) {
2464 if (intel_crtc
->pipe
== PIPE_B
)
2465 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
2467 /* pipesrc and dspsize control the size that is scaled from,
2468 * which should always be the user's requested size.
2470 I915_WRITE(DSPSIZE(plane
),
2471 ((intel_crtc
->config
.pipe_src_h
- 1) << 16) |
2472 (intel_crtc
->config
.pipe_src_w
- 1));
2473 I915_WRITE(DSPPOS(plane
), 0);
2474 } else if (IS_CHERRYVIEW(dev
) && plane
== PLANE_B
) {
2475 I915_WRITE(PRIMSIZE(plane
),
2476 ((intel_crtc
->config
.pipe_src_h
- 1) << 16) |
2477 (intel_crtc
->config
.pipe_src_w
- 1));
2478 I915_WRITE(PRIMPOS(plane
), 0);
2479 I915_WRITE(PRIMCNSTALPHA(plane
), 0);
2482 switch (fb
->pixel_format
) {
2484 dspcntr
|= DISPPLANE_8BPP
;
2486 case DRM_FORMAT_XRGB1555
:
2487 case DRM_FORMAT_ARGB1555
:
2488 dspcntr
|= DISPPLANE_BGRX555
;
2490 case DRM_FORMAT_RGB565
:
2491 dspcntr
|= DISPPLANE_BGRX565
;
2493 case DRM_FORMAT_XRGB8888
:
2494 case DRM_FORMAT_ARGB8888
:
2495 dspcntr
|= DISPPLANE_BGRX888
;
2497 case DRM_FORMAT_XBGR8888
:
2498 case DRM_FORMAT_ABGR8888
:
2499 dspcntr
|= DISPPLANE_RGBX888
;
2501 case DRM_FORMAT_XRGB2101010
:
2502 case DRM_FORMAT_ARGB2101010
:
2503 dspcntr
|= DISPPLANE_BGRX101010
;
2505 case DRM_FORMAT_XBGR2101010
:
2506 case DRM_FORMAT_ABGR2101010
:
2507 dspcntr
|= DISPPLANE_RGBX101010
;
2513 if (INTEL_INFO(dev
)->gen
>= 4 &&
2514 obj
->tiling_mode
!= I915_TILING_NONE
)
2515 dspcntr
|= DISPPLANE_TILED
;
2518 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2520 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
2522 if (INTEL_INFO(dev
)->gen
>= 4) {
2523 intel_crtc
->dspaddr_offset
=
2524 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2527 linear_offset
-= intel_crtc
->dspaddr_offset
;
2529 intel_crtc
->dspaddr_offset
= linear_offset
;
2532 if (to_intel_plane(crtc
->primary
)->rotation
== BIT(DRM_ROTATE_180
)) {
2533 dspcntr
|= DISPPLANE_ROTATE_180
;
2535 x
+= (intel_crtc
->config
.pipe_src_w
- 1);
2536 y
+= (intel_crtc
->config
.pipe_src_h
- 1);
2538 /* Finding the last pixel of the last line of the display
2539 data and adding to linear_offset*/
2541 (intel_crtc
->config
.pipe_src_h
- 1) * fb
->pitches
[0] +
2542 (intel_crtc
->config
.pipe_src_w
- 1) * pixel_size
;
2545 I915_WRITE(reg
, dspcntr
);
2547 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2548 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2550 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2551 if (INTEL_INFO(dev
)->gen
>= 4) {
2552 I915_WRITE(DSPSURF(plane
),
2553 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2554 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2555 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2557 I915_WRITE(DSPADDR(plane
), i915_gem_obj_ggtt_offset(obj
) + linear_offset
);
2561 static void ironlake_update_primary_plane(struct drm_crtc
*crtc
,
2562 struct drm_framebuffer
*fb
,
2565 struct drm_device
*dev
= crtc
->dev
;
2566 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2567 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2568 struct drm_i915_gem_object
*obj
;
2569 int plane
= intel_crtc
->plane
;
2570 unsigned long linear_offset
;
2572 u32 reg
= DSPCNTR(plane
);
2575 if (!intel_crtc
->primary_enabled
) {
2577 I915_WRITE(DSPSURF(plane
), 0);
2582 obj
= intel_fb_obj(fb
);
2583 if (WARN_ON(obj
== NULL
))
2586 pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2588 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2590 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2592 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2593 dspcntr
|= DISPPLANE_PIPE_CSC_ENABLE
;
2595 switch (fb
->pixel_format
) {
2597 dspcntr
|= DISPPLANE_8BPP
;
2599 case DRM_FORMAT_RGB565
:
2600 dspcntr
|= DISPPLANE_BGRX565
;
2602 case DRM_FORMAT_XRGB8888
:
2603 case DRM_FORMAT_ARGB8888
:
2604 dspcntr
|= DISPPLANE_BGRX888
;
2606 case DRM_FORMAT_XBGR8888
:
2607 case DRM_FORMAT_ABGR8888
:
2608 dspcntr
|= DISPPLANE_RGBX888
;
2610 case DRM_FORMAT_XRGB2101010
:
2611 case DRM_FORMAT_ARGB2101010
:
2612 dspcntr
|= DISPPLANE_BGRX101010
;
2614 case DRM_FORMAT_XBGR2101010
:
2615 case DRM_FORMAT_ABGR2101010
:
2616 dspcntr
|= DISPPLANE_RGBX101010
;
2622 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2623 dspcntr
|= DISPPLANE_TILED
;
2625 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
))
2626 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2628 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
2629 intel_crtc
->dspaddr_offset
=
2630 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2633 linear_offset
-= intel_crtc
->dspaddr_offset
;
2634 if (to_intel_plane(crtc
->primary
)->rotation
== BIT(DRM_ROTATE_180
)) {
2635 dspcntr
|= DISPPLANE_ROTATE_180
;
2637 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
)) {
2638 x
+= (intel_crtc
->config
.pipe_src_w
- 1);
2639 y
+= (intel_crtc
->config
.pipe_src_h
- 1);
2641 /* Finding the last pixel of the last line of the display
2642 data and adding to linear_offset*/
2644 (intel_crtc
->config
.pipe_src_h
- 1) * fb
->pitches
[0] +
2645 (intel_crtc
->config
.pipe_src_w
- 1) * pixel_size
;
2649 I915_WRITE(reg
, dspcntr
);
2651 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2652 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2654 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2655 I915_WRITE(DSPSURF(plane
),
2656 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2657 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2658 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2660 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2661 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2666 static void skylake_update_primary_plane(struct drm_crtc
*crtc
,
2667 struct drm_framebuffer
*fb
,
2670 struct drm_device
*dev
= crtc
->dev
;
2671 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2672 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2673 struct intel_framebuffer
*intel_fb
;
2674 struct drm_i915_gem_object
*obj
;
2675 int pipe
= intel_crtc
->pipe
;
2676 u32 plane_ctl
, stride
;
2678 if (!intel_crtc
->primary_enabled
) {
2679 I915_WRITE(PLANE_CTL(pipe
, 0), 0);
2680 I915_WRITE(PLANE_SURF(pipe
, 0), 0);
2681 POSTING_READ(PLANE_CTL(pipe
, 0));
2685 plane_ctl
= PLANE_CTL_ENABLE
|
2686 PLANE_CTL_PIPE_GAMMA_ENABLE
|
2687 PLANE_CTL_PIPE_CSC_ENABLE
;
2689 switch (fb
->pixel_format
) {
2690 case DRM_FORMAT_RGB565
:
2691 plane_ctl
|= PLANE_CTL_FORMAT_RGB_565
;
2693 case DRM_FORMAT_XRGB8888
:
2694 plane_ctl
|= PLANE_CTL_FORMAT_XRGB_8888
;
2696 case DRM_FORMAT_XBGR8888
:
2697 plane_ctl
|= PLANE_CTL_ORDER_RGBX
;
2698 plane_ctl
|= PLANE_CTL_FORMAT_XRGB_8888
;
2700 case DRM_FORMAT_XRGB2101010
:
2701 plane_ctl
|= PLANE_CTL_FORMAT_XRGB_2101010
;
2703 case DRM_FORMAT_XBGR2101010
:
2704 plane_ctl
|= PLANE_CTL_ORDER_RGBX
;
2705 plane_ctl
|= PLANE_CTL_FORMAT_XRGB_2101010
;
2711 intel_fb
= to_intel_framebuffer(fb
);
2712 obj
= intel_fb
->obj
;
2715 * The stride is either expressed as a multiple of 64 bytes chunks for
2716 * linear buffers or in number of tiles for tiled buffers.
2718 switch (obj
->tiling_mode
) {
2719 case I915_TILING_NONE
:
2720 stride
= fb
->pitches
[0] >> 6;
2723 plane_ctl
|= PLANE_CTL_TILED_X
;
2724 stride
= fb
->pitches
[0] >> 9;
2730 plane_ctl
|= PLANE_CTL_PLANE_GAMMA_DISABLE
;
2731 if (to_intel_plane(crtc
->primary
)->rotation
== BIT(DRM_ROTATE_180
))
2732 plane_ctl
|= PLANE_CTL_ROTATE_180
;
2734 I915_WRITE(PLANE_CTL(pipe
, 0), plane_ctl
);
2736 DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2737 i915_gem_obj_ggtt_offset(obj
),
2738 x
, y
, fb
->width
, fb
->height
,
2741 I915_WRITE(PLANE_POS(pipe
, 0), 0);
2742 I915_WRITE(PLANE_OFFSET(pipe
, 0), (y
<< 16) | x
);
2743 I915_WRITE(PLANE_SIZE(pipe
, 0),
2744 (intel_crtc
->config
.pipe_src_h
- 1) << 16 |
2745 (intel_crtc
->config
.pipe_src_w
- 1));
2746 I915_WRITE(PLANE_STRIDE(pipe
, 0), stride
);
2747 I915_WRITE(PLANE_SURF(pipe
, 0), i915_gem_obj_ggtt_offset(obj
));
2749 POSTING_READ(PLANE_SURF(pipe
, 0));
2752 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2754 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2755 int x
, int y
, enum mode_set_atomic state
)
2757 struct drm_device
*dev
= crtc
->dev
;
2758 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2760 if (dev_priv
->display
.disable_fbc
)
2761 dev_priv
->display
.disable_fbc(dev
);
2763 dev_priv
->display
.update_primary_plane(crtc
, fb
, x
, y
);
2768 static void intel_complete_page_flips(struct drm_device
*dev
)
2770 struct drm_crtc
*crtc
;
2772 for_each_crtc(dev
, crtc
) {
2773 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2774 enum plane plane
= intel_crtc
->plane
;
2776 intel_prepare_page_flip(dev
, plane
);
2777 intel_finish_page_flip_plane(dev
, plane
);
2781 static void intel_update_primary_planes(struct drm_device
*dev
)
2783 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2784 struct drm_crtc
*crtc
;
2786 for_each_crtc(dev
, crtc
) {
2787 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2789 drm_modeset_lock(&crtc
->mutex
, NULL
);
2791 * FIXME: Once we have proper support for primary planes (and
2792 * disabling them without disabling the entire crtc) allow again
2793 * a NULL crtc->primary->fb.
2795 if (intel_crtc
->active
&& crtc
->primary
->fb
)
2796 dev_priv
->display
.update_primary_plane(crtc
,
2800 drm_modeset_unlock(&crtc
->mutex
);
2804 void intel_prepare_reset(struct drm_device
*dev
)
2806 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2807 struct intel_crtc
*crtc
;
2809 /* no reset support for gen2 */
2813 /* reset doesn't touch the display */
2814 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
2817 drm_modeset_lock_all(dev
);
2820 * Disabling the crtcs gracefully seems nicer. Also the
2821 * g33 docs say we should at least disable all the planes.
2823 for_each_intel_crtc(dev
, crtc
) {
2825 dev_priv
->display
.crtc_disable(&crtc
->base
);
2829 void intel_finish_reset(struct drm_device
*dev
)
2831 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2834 * Flips in the rings will be nuked by the reset,
2835 * so complete all pending flips so that user space
2836 * will get its events and not get stuck.
2838 intel_complete_page_flips(dev
);
2840 /* no reset support for gen2 */
2844 /* reset doesn't touch the display */
2845 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
)) {
2847 * Flips in the rings have been nuked by the reset,
2848 * so update the base address of all primary
2849 * planes to the the last fb to make sure we're
2850 * showing the correct fb after a reset.
2852 intel_update_primary_planes(dev
);
2857 * The display has been reset as well,
2858 * so need a full re-initialization.
2860 intel_runtime_pm_disable_interrupts(dev_priv
);
2861 intel_runtime_pm_enable_interrupts(dev_priv
);
2863 intel_modeset_init_hw(dev
);
2865 spin_lock_irq(&dev_priv
->irq_lock
);
2866 if (dev_priv
->display
.hpd_irq_setup
)
2867 dev_priv
->display
.hpd_irq_setup(dev
);
2868 spin_unlock_irq(&dev_priv
->irq_lock
);
2870 intel_modeset_setup_hw_state(dev
, true);
2872 intel_hpd_init(dev_priv
);
2874 drm_modeset_unlock_all(dev
);
2878 intel_finish_fb(struct drm_framebuffer
*old_fb
)
2880 struct drm_i915_gem_object
*obj
= intel_fb_obj(old_fb
);
2881 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2882 bool was_interruptible
= dev_priv
->mm
.interruptible
;
2885 /* Big Hammer, we also need to ensure that any pending
2886 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2887 * current scanout is retired before unpinning the old
2890 * This should only fail upon a hung GPU, in which case we
2891 * can safely continue.
2893 dev_priv
->mm
.interruptible
= false;
2894 ret
= i915_gem_object_finish_gpu(obj
);
2895 dev_priv
->mm
.interruptible
= was_interruptible
;
2900 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
2902 struct drm_device
*dev
= crtc
->dev
;
2903 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2904 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2907 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
2908 intel_crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
2911 spin_lock_irq(&dev
->event_lock
);
2912 pending
= to_intel_crtc(crtc
)->unpin_work
!= NULL
;
2913 spin_unlock_irq(&dev
->event_lock
);
2918 static void intel_update_pipe_size(struct intel_crtc
*crtc
)
2920 struct drm_device
*dev
= crtc
->base
.dev
;
2921 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2922 const struct drm_display_mode
*adjusted_mode
;
2928 * Update pipe size and adjust fitter if needed: the reason for this is
2929 * that in compute_mode_changes we check the native mode (not the pfit
2930 * mode) to see if we can flip rather than do a full mode set. In the
2931 * fastboot case, we'll flip, but if we don't update the pipesrc and
2932 * pfit state, we'll end up with a big fb scanned out into the wrong
2935 * To fix this properly, we need to hoist the checks up into
2936 * compute_mode_changes (or above), check the actual pfit state and
2937 * whether the platform allows pfit disable with pipe active, and only
2938 * then update the pipesrc and pfit state, even on the flip path.
2941 adjusted_mode
= &crtc
->config
.adjusted_mode
;
2943 I915_WRITE(PIPESRC(crtc
->pipe
),
2944 ((adjusted_mode
->crtc_hdisplay
- 1) << 16) |
2945 (adjusted_mode
->crtc_vdisplay
- 1));
2946 if (!crtc
->config
.pch_pfit
.enabled
&&
2947 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) ||
2948 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
2949 I915_WRITE(PF_CTL(crtc
->pipe
), 0);
2950 I915_WRITE(PF_WIN_POS(crtc
->pipe
), 0);
2951 I915_WRITE(PF_WIN_SZ(crtc
->pipe
), 0);
2953 crtc
->config
.pipe_src_w
= adjusted_mode
->crtc_hdisplay
;
2954 crtc
->config
.pipe_src_h
= adjusted_mode
->crtc_vdisplay
;
2958 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2959 struct drm_framebuffer
*fb
)
2961 struct drm_device
*dev
= crtc
->dev
;
2962 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2963 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2964 enum pipe pipe
= intel_crtc
->pipe
;
2965 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
2966 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(old_fb
);
2969 if (intel_crtc_has_pending_flip(crtc
)) {
2970 DRM_ERROR("pipe is still busy with an old pageflip\n");
2976 DRM_ERROR("No FB bound\n");
2980 if (intel_crtc
->plane
> INTEL_INFO(dev
)->num_pipes
) {
2981 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2982 plane_name(intel_crtc
->plane
),
2983 INTEL_INFO(dev
)->num_pipes
);
2987 mutex_lock(&dev
->struct_mutex
);
2988 ret
= intel_pin_and_fence_fb_obj(crtc
->primary
, fb
, NULL
);
2990 i915_gem_track_fb(old_obj
, intel_fb_obj(fb
),
2991 INTEL_FRONTBUFFER_PRIMARY(pipe
));
2992 mutex_unlock(&dev
->struct_mutex
);
2994 DRM_ERROR("pin & fence failed\n");
2998 dev_priv
->display
.update_primary_plane(crtc
, fb
, x
, y
);
3000 if (intel_crtc
->active
)
3001 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
3003 crtc
->primary
->fb
= fb
;
3008 if (intel_crtc
->active
&& old_fb
!= fb
)
3009 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3010 mutex_lock(&dev
->struct_mutex
);
3011 intel_unpin_fb_obj(old_obj
);
3012 mutex_unlock(&dev
->struct_mutex
);
3015 mutex_lock(&dev
->struct_mutex
);
3016 intel_update_fbc(dev
);
3017 mutex_unlock(&dev
->struct_mutex
);
3022 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
3024 struct drm_device
*dev
= crtc
->dev
;
3025 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3026 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3027 int pipe
= intel_crtc
->pipe
;
3030 /* enable normal train */
3031 reg
= FDI_TX_CTL(pipe
);
3032 temp
= I915_READ(reg
);
3033 if (IS_IVYBRIDGE(dev
)) {
3034 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3035 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
3037 temp
&= ~FDI_LINK_TRAIN_NONE
;
3038 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
3040 I915_WRITE(reg
, temp
);
3042 reg
= FDI_RX_CTL(pipe
);
3043 temp
= I915_READ(reg
);
3044 if (HAS_PCH_CPT(dev
)) {
3045 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3046 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
3048 temp
&= ~FDI_LINK_TRAIN_NONE
;
3049 temp
|= FDI_LINK_TRAIN_NONE
;
3051 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
3053 /* wait one idle pattern time */
3057 /* IVB wants error correction enabled */
3058 if (IS_IVYBRIDGE(dev
))
3059 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
3060 FDI_FE_ERRC_ENABLE
);
3063 static bool pipe_has_enabled_pch(struct intel_crtc
*crtc
)
3065 return crtc
->base
.enabled
&& crtc
->active
&&
3066 crtc
->config
.has_pch_encoder
;
3069 static void ivb_modeset_global_resources(struct drm_device
*dev
)
3071 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3072 struct intel_crtc
*pipe_B_crtc
=
3073 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
3074 struct intel_crtc
*pipe_C_crtc
=
3075 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]);
3079 * When everything is off disable fdi C so that we could enable fdi B
3080 * with all lanes. Note that we don't care about enabled pipes without
3081 * an enabled pch encoder.
3083 if (!pipe_has_enabled_pch(pipe_B_crtc
) &&
3084 !pipe_has_enabled_pch(pipe_C_crtc
)) {
3085 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
3086 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
3088 temp
= I915_READ(SOUTH_CHICKEN1
);
3089 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
3090 DRM_DEBUG_KMS("disabling fdi C rx\n");
3091 I915_WRITE(SOUTH_CHICKEN1
, temp
);
3095 /* The FDI link training functions for ILK/Ibexpeak. */
3096 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
3098 struct drm_device
*dev
= crtc
->dev
;
3099 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3100 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3101 int pipe
= intel_crtc
->pipe
;
3102 u32 reg
, temp
, tries
;
3104 /* FDI needs bits from pipe first */
3105 assert_pipe_enabled(dev_priv
, pipe
);
3107 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3109 reg
= FDI_RX_IMR(pipe
);
3110 temp
= I915_READ(reg
);
3111 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3112 temp
&= ~FDI_RX_BIT_LOCK
;
3113 I915_WRITE(reg
, temp
);
3117 /* enable CPU FDI TX and PCH FDI RX */
3118 reg
= FDI_TX_CTL(pipe
);
3119 temp
= I915_READ(reg
);
3120 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3121 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
3122 temp
&= ~FDI_LINK_TRAIN_NONE
;
3123 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3124 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3126 reg
= FDI_RX_CTL(pipe
);
3127 temp
= I915_READ(reg
);
3128 temp
&= ~FDI_LINK_TRAIN_NONE
;
3129 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3130 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3135 /* Ironlake workaround, enable clock pointer after FDI enable*/
3136 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3137 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
3138 FDI_RX_PHASE_SYNC_POINTER_EN
);
3140 reg
= FDI_RX_IIR(pipe
);
3141 for (tries
= 0; tries
< 5; tries
++) {
3142 temp
= I915_READ(reg
);
3143 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3145 if ((temp
& FDI_RX_BIT_LOCK
)) {
3146 DRM_DEBUG_KMS("FDI train 1 done.\n");
3147 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3152 DRM_ERROR("FDI train 1 fail!\n");
3155 reg
= FDI_TX_CTL(pipe
);
3156 temp
= I915_READ(reg
);
3157 temp
&= ~FDI_LINK_TRAIN_NONE
;
3158 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3159 I915_WRITE(reg
, temp
);
3161 reg
= FDI_RX_CTL(pipe
);
3162 temp
= I915_READ(reg
);
3163 temp
&= ~FDI_LINK_TRAIN_NONE
;
3164 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3165 I915_WRITE(reg
, temp
);
3170 reg
= FDI_RX_IIR(pipe
);
3171 for (tries
= 0; tries
< 5; tries
++) {
3172 temp
= I915_READ(reg
);
3173 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3175 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3176 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3177 DRM_DEBUG_KMS("FDI train 2 done.\n");
3182 DRM_ERROR("FDI train 2 fail!\n");
3184 DRM_DEBUG_KMS("FDI train done\n");
3188 static const int snb_b_fdi_train_param
[] = {
3189 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
3190 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
3191 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
3192 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
3195 /* The FDI link training functions for SNB/Cougarpoint. */
3196 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
3198 struct drm_device
*dev
= crtc
->dev
;
3199 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3200 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3201 int pipe
= intel_crtc
->pipe
;
3202 u32 reg
, temp
, i
, retry
;
3204 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3206 reg
= FDI_RX_IMR(pipe
);
3207 temp
= I915_READ(reg
);
3208 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3209 temp
&= ~FDI_RX_BIT_LOCK
;
3210 I915_WRITE(reg
, temp
);
3215 /* enable CPU FDI TX and PCH FDI RX */
3216 reg
= FDI_TX_CTL(pipe
);
3217 temp
= I915_READ(reg
);
3218 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3219 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
3220 temp
&= ~FDI_LINK_TRAIN_NONE
;
3221 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3222 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3224 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3225 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3227 I915_WRITE(FDI_RX_MISC(pipe
),
3228 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3230 reg
= FDI_RX_CTL(pipe
);
3231 temp
= I915_READ(reg
);
3232 if (HAS_PCH_CPT(dev
)) {
3233 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3234 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3236 temp
&= ~FDI_LINK_TRAIN_NONE
;
3237 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3239 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3244 for (i
= 0; i
< 4; i
++) {
3245 reg
= FDI_TX_CTL(pipe
);
3246 temp
= I915_READ(reg
);
3247 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3248 temp
|= snb_b_fdi_train_param
[i
];
3249 I915_WRITE(reg
, temp
);
3254 for (retry
= 0; retry
< 5; retry
++) {
3255 reg
= FDI_RX_IIR(pipe
);
3256 temp
= I915_READ(reg
);
3257 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3258 if (temp
& FDI_RX_BIT_LOCK
) {
3259 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3260 DRM_DEBUG_KMS("FDI train 1 done.\n");
3269 DRM_ERROR("FDI train 1 fail!\n");
3272 reg
= FDI_TX_CTL(pipe
);
3273 temp
= I915_READ(reg
);
3274 temp
&= ~FDI_LINK_TRAIN_NONE
;
3275 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3277 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3279 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3281 I915_WRITE(reg
, temp
);
3283 reg
= FDI_RX_CTL(pipe
);
3284 temp
= I915_READ(reg
);
3285 if (HAS_PCH_CPT(dev
)) {
3286 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3287 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3289 temp
&= ~FDI_LINK_TRAIN_NONE
;
3290 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3292 I915_WRITE(reg
, temp
);
3297 for (i
= 0; i
< 4; i
++) {
3298 reg
= FDI_TX_CTL(pipe
);
3299 temp
= I915_READ(reg
);
3300 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3301 temp
|= snb_b_fdi_train_param
[i
];
3302 I915_WRITE(reg
, temp
);
3307 for (retry
= 0; retry
< 5; retry
++) {
3308 reg
= FDI_RX_IIR(pipe
);
3309 temp
= I915_READ(reg
);
3310 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3311 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3312 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3313 DRM_DEBUG_KMS("FDI train 2 done.\n");
3322 DRM_ERROR("FDI train 2 fail!\n");
3324 DRM_DEBUG_KMS("FDI train done.\n");
3327 /* Manual link training for Ivy Bridge A0 parts */
3328 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
3330 struct drm_device
*dev
= crtc
->dev
;
3331 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3332 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3333 int pipe
= intel_crtc
->pipe
;
3334 u32 reg
, temp
, i
, j
;
3336 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3338 reg
= FDI_RX_IMR(pipe
);
3339 temp
= I915_READ(reg
);
3340 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3341 temp
&= ~FDI_RX_BIT_LOCK
;
3342 I915_WRITE(reg
, temp
);
3347 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3348 I915_READ(FDI_RX_IIR(pipe
)));
3350 /* Try each vswing and preemphasis setting twice before moving on */
3351 for (j
= 0; j
< ARRAY_SIZE(snb_b_fdi_train_param
) * 2; j
++) {
3352 /* disable first in case we need to retry */
3353 reg
= FDI_TX_CTL(pipe
);
3354 temp
= I915_READ(reg
);
3355 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
3356 temp
&= ~FDI_TX_ENABLE
;
3357 I915_WRITE(reg
, temp
);
3359 reg
= FDI_RX_CTL(pipe
);
3360 temp
= I915_READ(reg
);
3361 temp
&= ~FDI_LINK_TRAIN_AUTO
;
3362 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3363 temp
&= ~FDI_RX_ENABLE
;
3364 I915_WRITE(reg
, temp
);
3366 /* enable CPU FDI TX and PCH FDI RX */
3367 reg
= FDI_TX_CTL(pipe
);
3368 temp
= I915_READ(reg
);
3369 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3370 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
3371 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
3372 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3373 temp
|= snb_b_fdi_train_param
[j
/2];
3374 temp
|= FDI_COMPOSITE_SYNC
;
3375 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3377 I915_WRITE(FDI_RX_MISC(pipe
),
3378 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3380 reg
= FDI_RX_CTL(pipe
);
3381 temp
= I915_READ(reg
);
3382 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3383 temp
|= FDI_COMPOSITE_SYNC
;
3384 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3387 udelay(1); /* should be 0.5us */
3389 for (i
= 0; i
< 4; i
++) {
3390 reg
= FDI_RX_IIR(pipe
);
3391 temp
= I915_READ(reg
);
3392 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3394 if (temp
& FDI_RX_BIT_LOCK
||
3395 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
3396 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3397 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3401 udelay(1); /* should be 0.5us */
3404 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j
/ 2);
3409 reg
= FDI_TX_CTL(pipe
);
3410 temp
= I915_READ(reg
);
3411 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3412 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
3413 I915_WRITE(reg
, temp
);
3415 reg
= FDI_RX_CTL(pipe
);
3416 temp
= I915_READ(reg
);
3417 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3418 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3419 I915_WRITE(reg
, temp
);
3422 udelay(2); /* should be 1.5us */
3424 for (i
= 0; i
< 4; i
++) {
3425 reg
= FDI_RX_IIR(pipe
);
3426 temp
= I915_READ(reg
);
3427 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3429 if (temp
& FDI_RX_SYMBOL_LOCK
||
3430 (I915_READ(reg
) & FDI_RX_SYMBOL_LOCK
)) {
3431 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3432 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3436 udelay(2); /* should be 1.5us */
3439 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j
/ 2);
3443 DRM_DEBUG_KMS("FDI train done.\n");
3446 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
3448 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3449 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3450 int pipe
= intel_crtc
->pipe
;
3454 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3455 reg
= FDI_RX_CTL(pipe
);
3456 temp
= I915_READ(reg
);
3457 temp
&= ~(FDI_DP_PORT_WIDTH_MASK
| (0x7 << 16));
3458 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
3459 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3460 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
3465 /* Switch from Rawclk to PCDclk */
3466 temp
= I915_READ(reg
);
3467 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
3472 /* Enable CPU FDI TX PLL, always on for Ironlake */
3473 reg
= FDI_TX_CTL(pipe
);
3474 temp
= I915_READ(reg
);
3475 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
3476 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
3483 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
3485 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3486 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3487 int pipe
= intel_crtc
->pipe
;
3490 /* Switch from PCDclk to Rawclk */
3491 reg
= FDI_RX_CTL(pipe
);
3492 temp
= I915_READ(reg
);
3493 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
3495 /* Disable CPU FDI TX PLL */
3496 reg
= FDI_TX_CTL(pipe
);
3497 temp
= I915_READ(reg
);
3498 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
3503 reg
= FDI_RX_CTL(pipe
);
3504 temp
= I915_READ(reg
);
3505 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
3507 /* Wait for the clocks to turn off. */
3512 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
3514 struct drm_device
*dev
= crtc
->dev
;
3515 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3516 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3517 int pipe
= intel_crtc
->pipe
;
3520 /* disable CPU FDI tx and PCH FDI rx */
3521 reg
= FDI_TX_CTL(pipe
);
3522 temp
= I915_READ(reg
);
3523 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
3526 reg
= FDI_RX_CTL(pipe
);
3527 temp
= I915_READ(reg
);
3528 temp
&= ~(0x7 << 16);
3529 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3530 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
3535 /* Ironlake workaround, disable clock pointer after downing FDI */
3536 if (HAS_PCH_IBX(dev
))
3537 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3539 /* still set train pattern 1 */
3540 reg
= FDI_TX_CTL(pipe
);
3541 temp
= I915_READ(reg
);
3542 temp
&= ~FDI_LINK_TRAIN_NONE
;
3543 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3544 I915_WRITE(reg
, temp
);
3546 reg
= FDI_RX_CTL(pipe
);
3547 temp
= I915_READ(reg
);
3548 if (HAS_PCH_CPT(dev
)) {
3549 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3550 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3552 temp
&= ~FDI_LINK_TRAIN_NONE
;
3553 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3555 /* BPC in FDI rx is consistent with that in PIPECONF */
3556 temp
&= ~(0x07 << 16);
3557 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3558 I915_WRITE(reg
, temp
);
3564 bool intel_has_pending_fb_unpin(struct drm_device
*dev
)
3566 struct intel_crtc
*crtc
;
3568 /* Note that we don't need to be called with mode_config.lock here
3569 * as our list of CRTC objects is static for the lifetime of the
3570 * device and so cannot disappear as we iterate. Similarly, we can
3571 * happily treat the predicates as racy, atomic checks as userspace
3572 * cannot claim and pin a new fb without at least acquring the
3573 * struct_mutex and so serialising with us.
3575 for_each_intel_crtc(dev
, crtc
) {
3576 if (atomic_read(&crtc
->unpin_work_count
) == 0)
3579 if (crtc
->unpin_work
)
3580 intel_wait_for_vblank(dev
, crtc
->pipe
);
3588 static void page_flip_completed(struct intel_crtc
*intel_crtc
)
3590 struct drm_i915_private
*dev_priv
= to_i915(intel_crtc
->base
.dev
);
3591 struct intel_unpin_work
*work
= intel_crtc
->unpin_work
;
3593 /* ensure that the unpin work is consistent wrt ->pending. */
3595 intel_crtc
->unpin_work
= NULL
;
3598 drm_send_vblank_event(intel_crtc
->base
.dev
,
3602 drm_crtc_vblank_put(&intel_crtc
->base
);
3604 wake_up_all(&dev_priv
->pending_flip_queue
);
3605 queue_work(dev_priv
->wq
, &work
->work
);
3607 trace_i915_flip_complete(intel_crtc
->plane
,
3608 work
->pending_flip_obj
);
3611 void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
3613 struct drm_device
*dev
= crtc
->dev
;
3614 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3616 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
3617 if (WARN_ON(wait_event_timeout(dev_priv
->pending_flip_queue
,
3618 !intel_crtc_has_pending_flip(crtc
),
3620 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3622 spin_lock_irq(&dev
->event_lock
);
3623 if (intel_crtc
->unpin_work
) {
3624 WARN_ONCE(1, "Removing stuck page flip\n");
3625 page_flip_completed(intel_crtc
);
3627 spin_unlock_irq(&dev
->event_lock
);
3630 if (crtc
->primary
->fb
) {
3631 mutex_lock(&dev
->struct_mutex
);
3632 intel_finish_fb(crtc
->primary
->fb
);
3633 mutex_unlock(&dev
->struct_mutex
);
3637 /* Program iCLKIP clock to the desired frequency */
3638 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
3640 struct drm_device
*dev
= crtc
->dev
;
3641 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3642 int clock
= to_intel_crtc(crtc
)->config
.adjusted_mode
.crtc_clock
;
3643 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
3646 mutex_lock(&dev_priv
->dpio_lock
);
3648 /* It is necessary to ungate the pixclk gate prior to programming
3649 * the divisors, and gate it back when it is done.
3651 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
3653 /* Disable SSCCTL */
3654 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
3655 intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
) |
3659 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3660 if (clock
== 20000) {
3665 /* The iCLK virtual clock root frequency is in MHz,
3666 * but the adjusted_mode->crtc_clock in in KHz. To get the
3667 * divisors, it is necessary to divide one by another, so we
3668 * convert the virtual clock precision to KHz here for higher
3671 u32 iclk_virtual_root_freq
= 172800 * 1000;
3672 u32 iclk_pi_range
= 64;
3673 u32 desired_divisor
, msb_divisor_value
, pi_value
;
3675 desired_divisor
= (iclk_virtual_root_freq
/ clock
);
3676 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
3677 pi_value
= desired_divisor
% iclk_pi_range
;
3680 divsel
= msb_divisor_value
- 2;
3681 phaseinc
= pi_value
;
3684 /* This should not happen with any sane values */
3685 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
3686 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
3687 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
3688 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
3690 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3697 /* Program SSCDIVINTPHASE6 */
3698 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
3699 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
3700 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
3701 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
3702 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
3703 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
3704 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
3705 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
3707 /* Program SSCAUXDIV */
3708 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
3709 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3710 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
3711 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
3713 /* Enable modulator and associated divider */
3714 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
3715 temp
&= ~SBI_SSCCTL_DISABLE
;
3716 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
3718 /* Wait for initialization time */
3721 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
3723 mutex_unlock(&dev_priv
->dpio_lock
);
3726 static void ironlake_pch_transcoder_set_timings(struct intel_crtc
*crtc
,
3727 enum pipe pch_transcoder
)
3729 struct drm_device
*dev
= crtc
->base
.dev
;
3730 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3731 enum transcoder cpu_transcoder
= crtc
->config
.cpu_transcoder
;
3733 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder
),
3734 I915_READ(HTOTAL(cpu_transcoder
)));
3735 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder
),
3736 I915_READ(HBLANK(cpu_transcoder
)));
3737 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder
),
3738 I915_READ(HSYNC(cpu_transcoder
)));
3740 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder
),
3741 I915_READ(VTOTAL(cpu_transcoder
)));
3742 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder
),
3743 I915_READ(VBLANK(cpu_transcoder
)));
3744 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder
),
3745 I915_READ(VSYNC(cpu_transcoder
)));
3746 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder
),
3747 I915_READ(VSYNCSHIFT(cpu_transcoder
)));
3750 static void cpt_enable_fdi_bc_bifurcation(struct drm_device
*dev
)
3752 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3755 temp
= I915_READ(SOUTH_CHICKEN1
);
3756 if (temp
& FDI_BC_BIFURCATION_SELECT
)
3759 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
3760 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
3762 temp
|= FDI_BC_BIFURCATION_SELECT
;
3763 DRM_DEBUG_KMS("enabling fdi C rx\n");
3764 I915_WRITE(SOUTH_CHICKEN1
, temp
);
3765 POSTING_READ(SOUTH_CHICKEN1
);
3768 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc
*intel_crtc
)
3770 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3771 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3773 switch (intel_crtc
->pipe
) {
3777 if (intel_crtc
->config
.fdi_lanes
> 2)
3778 WARN_ON(I915_READ(SOUTH_CHICKEN1
) & FDI_BC_BIFURCATION_SELECT
);
3780 cpt_enable_fdi_bc_bifurcation(dev
);
3784 cpt_enable_fdi_bc_bifurcation(dev
);
3793 * Enable PCH resources required for PCH ports:
3795 * - FDI training & RX/TX
3796 * - update transcoder timings
3797 * - DP transcoding bits
3800 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
3802 struct drm_device
*dev
= crtc
->dev
;
3803 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3804 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3805 int pipe
= intel_crtc
->pipe
;
3808 assert_pch_transcoder_disabled(dev_priv
, pipe
);
3810 if (IS_IVYBRIDGE(dev
))
3811 ivybridge_update_fdi_bc_bifurcation(intel_crtc
);
3813 /* Write the TU size bits before fdi link training, so that error
3814 * detection works. */
3815 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
3816 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
3818 /* For PCH output, training FDI link */
3819 dev_priv
->display
.fdi_link_train(crtc
);
3821 /* We need to program the right clock selection before writing the pixel
3822 * mutliplier into the DPLL. */
3823 if (HAS_PCH_CPT(dev
)) {
3826 temp
= I915_READ(PCH_DPLL_SEL
);
3827 temp
|= TRANS_DPLL_ENABLE(pipe
);
3828 sel
= TRANS_DPLLB_SEL(pipe
);
3829 if (intel_crtc
->config
.shared_dpll
== DPLL_ID_PCH_PLL_B
)
3833 I915_WRITE(PCH_DPLL_SEL
, temp
);
3836 /* XXX: pch pll's can be enabled any time before we enable the PCH
3837 * transcoder, and we actually should do this to not upset any PCH
3838 * transcoder that already use the clock when we share it.
3840 * Note that enable_shared_dpll tries to do the right thing, but
3841 * get_shared_dpll unconditionally resets the pll - we need that to have
3842 * the right LVDS enable sequence. */
3843 intel_enable_shared_dpll(intel_crtc
);
3845 /* set transcoder timing, panel must allow it */
3846 assert_panel_unlocked(dev_priv
, pipe
);
3847 ironlake_pch_transcoder_set_timings(intel_crtc
, pipe
);
3849 intel_fdi_normal_train(crtc
);
3851 /* For PCH DP, enable TRANS_DP_CTL */
3852 if (HAS_PCH_CPT(dev
) && intel_crtc
->config
.has_dp_encoder
) {
3853 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
3854 reg
= TRANS_DP_CTL(pipe
);
3855 temp
= I915_READ(reg
);
3856 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
3857 TRANS_DP_SYNC_MASK
|
3859 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
3860 TRANS_DP_ENH_FRAMING
);
3861 temp
|= bpc
<< 9; /* same format but at 11:9 */
3863 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
3864 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
3865 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
3866 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
3868 switch (intel_trans_dp_port_sel(crtc
)) {
3870 temp
|= TRANS_DP_PORT_SEL_B
;
3873 temp
|= TRANS_DP_PORT_SEL_C
;
3876 temp
|= TRANS_DP_PORT_SEL_D
;
3882 I915_WRITE(reg
, temp
);
3885 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
3888 static void lpt_pch_enable(struct drm_crtc
*crtc
)
3890 struct drm_device
*dev
= crtc
->dev
;
3891 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3892 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3893 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
3895 assert_pch_transcoder_disabled(dev_priv
, TRANSCODER_A
);
3897 lpt_program_iclkip(crtc
);
3899 /* Set transcoder timing. */
3900 ironlake_pch_transcoder_set_timings(intel_crtc
, PIPE_A
);
3902 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
3905 void intel_put_shared_dpll(struct intel_crtc
*crtc
)
3907 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
3912 if (!(pll
->config
.crtc_mask
& (1 << crtc
->pipe
))) {
3913 WARN(1, "bad %s crtc mask\n", pll
->name
);
3917 pll
->config
.crtc_mask
&= ~(1 << crtc
->pipe
);
3918 if (pll
->config
.crtc_mask
== 0) {
3920 WARN_ON(pll
->active
);
3923 crtc
->config
.shared_dpll
= DPLL_ID_PRIVATE
;
3926 struct intel_shared_dpll
*intel_get_shared_dpll(struct intel_crtc
*crtc
)
3928 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
3929 struct intel_shared_dpll
*pll
;
3930 enum intel_dpll_id i
;
3932 if (HAS_PCH_IBX(dev_priv
->dev
)) {
3933 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3934 i
= (enum intel_dpll_id
) crtc
->pipe
;
3935 pll
= &dev_priv
->shared_dplls
[i
];
3937 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3938 crtc
->base
.base
.id
, pll
->name
);
3940 WARN_ON(pll
->new_config
->crtc_mask
);
3945 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3946 pll
= &dev_priv
->shared_dplls
[i
];
3948 /* Only want to check enabled timings first */
3949 if (pll
->new_config
->crtc_mask
== 0)
3952 if (memcmp(&crtc
->new_config
->dpll_hw_state
,
3953 &pll
->new_config
->hw_state
,
3954 sizeof(pll
->new_config
->hw_state
)) == 0) {
3955 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
3956 crtc
->base
.base
.id
, pll
->name
,
3957 pll
->new_config
->crtc_mask
,
3963 /* Ok no matching timings, maybe there's a free one? */
3964 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3965 pll
= &dev_priv
->shared_dplls
[i
];
3966 if (pll
->new_config
->crtc_mask
== 0) {
3967 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3968 crtc
->base
.base
.id
, pll
->name
);
3976 if (pll
->new_config
->crtc_mask
== 0)
3977 pll
->new_config
->hw_state
= crtc
->new_config
->dpll_hw_state
;
3979 crtc
->new_config
->shared_dpll
= i
;
3980 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll
->name
,
3981 pipe_name(crtc
->pipe
));
3983 pll
->new_config
->crtc_mask
|= 1 << crtc
->pipe
;
3989 * intel_shared_dpll_start_config - start a new PLL staged config
3990 * @dev_priv: DRM device
3991 * @clear_pipes: mask of pipes that will have their PLLs freed
3993 * Starts a new PLL staged config, copying the current config but
3994 * releasing the references of pipes specified in clear_pipes.
3996 static int intel_shared_dpll_start_config(struct drm_i915_private
*dev_priv
,
3997 unsigned clear_pipes
)
3999 struct intel_shared_dpll
*pll
;
4000 enum intel_dpll_id i
;
4002 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4003 pll
= &dev_priv
->shared_dplls
[i
];
4005 pll
->new_config
= kmemdup(&pll
->config
, sizeof pll
->config
,
4007 if (!pll
->new_config
)
4010 pll
->new_config
->crtc_mask
&= ~clear_pipes
;
4017 pll
= &dev_priv
->shared_dplls
[i
];
4018 kfree(pll
->new_config
);
4019 pll
->new_config
= NULL
;
4025 static void intel_shared_dpll_commit(struct drm_i915_private
*dev_priv
)
4027 struct intel_shared_dpll
*pll
;
4028 enum intel_dpll_id i
;
4030 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4031 pll
= &dev_priv
->shared_dplls
[i
];
4033 WARN_ON(pll
->new_config
== &pll
->config
);
4035 pll
->config
= *pll
->new_config
;
4036 kfree(pll
->new_config
);
4037 pll
->new_config
= NULL
;
4041 static void intel_shared_dpll_abort_config(struct drm_i915_private
*dev_priv
)
4043 struct intel_shared_dpll
*pll
;
4044 enum intel_dpll_id i
;
4046 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4047 pll
= &dev_priv
->shared_dplls
[i
];
4049 WARN_ON(pll
->new_config
== &pll
->config
);
4051 kfree(pll
->new_config
);
4052 pll
->new_config
= NULL
;
4056 static void cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
4058 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4059 int dslreg
= PIPEDSL(pipe
);
4062 temp
= I915_READ(dslreg
);
4064 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
4065 if (wait_for(I915_READ(dslreg
) != temp
, 5))
4066 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
4070 static void skylake_pfit_enable(struct intel_crtc
*crtc
)
4072 struct drm_device
*dev
= crtc
->base
.dev
;
4073 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4074 int pipe
= crtc
->pipe
;
4076 if (crtc
->config
.pch_pfit
.enabled
) {
4077 I915_WRITE(PS_CTL(pipe
), PS_ENABLE
);
4078 I915_WRITE(PS_WIN_POS(pipe
), crtc
->config
.pch_pfit
.pos
);
4079 I915_WRITE(PS_WIN_SZ(pipe
), crtc
->config
.pch_pfit
.size
);
4083 static void ironlake_pfit_enable(struct intel_crtc
*crtc
)
4085 struct drm_device
*dev
= crtc
->base
.dev
;
4086 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4087 int pipe
= crtc
->pipe
;
4089 if (crtc
->config
.pch_pfit
.enabled
) {
4090 /* Force use of hard-coded filter coefficients
4091 * as some pre-programmed values are broken,
4094 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
4095 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
4096 PF_PIPE_SEL_IVB(pipe
));
4098 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
4099 I915_WRITE(PF_WIN_POS(pipe
), crtc
->config
.pch_pfit
.pos
);
4100 I915_WRITE(PF_WIN_SZ(pipe
), crtc
->config
.pch_pfit
.size
);
4104 static void intel_enable_planes(struct drm_crtc
*crtc
)
4106 struct drm_device
*dev
= crtc
->dev
;
4107 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
4108 struct drm_plane
*plane
;
4109 struct intel_plane
*intel_plane
;
4111 drm_for_each_legacy_plane(plane
, &dev
->mode_config
.plane_list
) {
4112 intel_plane
= to_intel_plane(plane
);
4113 if (intel_plane
->pipe
== pipe
)
4114 intel_plane_restore(&intel_plane
->base
);
4118 static void intel_disable_planes(struct drm_crtc
*crtc
)
4120 struct drm_device
*dev
= crtc
->dev
;
4121 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
4122 struct drm_plane
*plane
;
4123 struct intel_plane
*intel_plane
;
4125 drm_for_each_legacy_plane(plane
, &dev
->mode_config
.plane_list
) {
4126 intel_plane
= to_intel_plane(plane
);
4127 if (intel_plane
->pipe
== pipe
)
4128 intel_plane_disable(&intel_plane
->base
);
4132 void hsw_enable_ips(struct intel_crtc
*crtc
)
4134 struct drm_device
*dev
= crtc
->base
.dev
;
4135 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4137 if (!crtc
->config
.ips_enabled
)
4140 /* We can only enable IPS after we enable a plane and wait for a vblank */
4141 intel_wait_for_vblank(dev
, crtc
->pipe
);
4143 assert_plane_enabled(dev_priv
, crtc
->plane
);
4144 if (IS_BROADWELL(dev
)) {
4145 mutex_lock(&dev_priv
->rps
.hw_lock
);
4146 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0xc0000000));
4147 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4148 /* Quoting Art Runyan: "its not safe to expect any particular
4149 * value in IPS_CTL bit 31 after enabling IPS through the
4150 * mailbox." Moreover, the mailbox may return a bogus state,
4151 * so we need to just enable it and continue on.
4154 I915_WRITE(IPS_CTL
, IPS_ENABLE
);
4155 /* The bit only becomes 1 in the next vblank, so this wait here
4156 * is essentially intel_wait_for_vblank. If we don't have this
4157 * and don't wait for vblanks until the end of crtc_enable, then
4158 * the HW state readout code will complain that the expected
4159 * IPS_CTL value is not the one we read. */
4160 if (wait_for(I915_READ_NOTRACE(IPS_CTL
) & IPS_ENABLE
, 50))
4161 DRM_ERROR("Timed out waiting for IPS enable\n");
4165 void hsw_disable_ips(struct intel_crtc
*crtc
)
4167 struct drm_device
*dev
= crtc
->base
.dev
;
4168 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4170 if (!crtc
->config
.ips_enabled
)
4173 assert_plane_enabled(dev_priv
, crtc
->plane
);
4174 if (IS_BROADWELL(dev
)) {
4175 mutex_lock(&dev_priv
->rps
.hw_lock
);
4176 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0));
4177 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4178 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4179 if (wait_for((I915_READ(IPS_CTL
) & IPS_ENABLE
) == 0, 42))
4180 DRM_ERROR("Timed out waiting for IPS disable\n");
4182 I915_WRITE(IPS_CTL
, 0);
4183 POSTING_READ(IPS_CTL
);
4186 /* We need to wait for a vblank before we can disable the plane. */
4187 intel_wait_for_vblank(dev
, crtc
->pipe
);
4190 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4191 static void intel_crtc_load_lut(struct drm_crtc
*crtc
)
4193 struct drm_device
*dev
= crtc
->dev
;
4194 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4195 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4196 enum pipe pipe
= intel_crtc
->pipe
;
4197 int palreg
= PALETTE(pipe
);
4199 bool reenable_ips
= false;
4201 /* The clocks have to be on to load the palette. */
4202 if (!crtc
->enabled
|| !intel_crtc
->active
)
4205 if (!HAS_PCH_SPLIT(dev_priv
->dev
)) {
4206 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
))
4207 assert_dsi_pll_enabled(dev_priv
);
4209 assert_pll_enabled(dev_priv
, pipe
);
4212 /* use legacy palette for Ironlake */
4213 if (!HAS_GMCH_DISPLAY(dev
))
4214 palreg
= LGC_PALETTE(pipe
);
4216 /* Workaround : Do not read or write the pipe palette/gamma data while
4217 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4219 if (IS_HASWELL(dev
) && intel_crtc
->config
.ips_enabled
&&
4220 ((I915_READ(GAMMA_MODE(pipe
)) & GAMMA_MODE_MODE_MASK
) ==
4221 GAMMA_MODE_MODE_SPLIT
)) {
4222 hsw_disable_ips(intel_crtc
);
4223 reenable_ips
= true;
4226 for (i
= 0; i
< 256; i
++) {
4227 I915_WRITE(palreg
+ 4 * i
,
4228 (intel_crtc
->lut_r
[i
] << 16) |
4229 (intel_crtc
->lut_g
[i
] << 8) |
4230 intel_crtc
->lut_b
[i
]);
4234 hsw_enable_ips(intel_crtc
);
4237 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
4239 if (!enable
&& intel_crtc
->overlay
) {
4240 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4241 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4243 mutex_lock(&dev
->struct_mutex
);
4244 dev_priv
->mm
.interruptible
= false;
4245 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
4246 dev_priv
->mm
.interruptible
= true;
4247 mutex_unlock(&dev
->struct_mutex
);
4250 /* Let userspace switch the overlay on again. In most cases userspace
4251 * has to recompute where to put it anyway.
4255 static void intel_crtc_enable_planes(struct drm_crtc
*crtc
)
4257 struct drm_device
*dev
= crtc
->dev
;
4258 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4259 int pipe
= intel_crtc
->pipe
;
4261 intel_enable_primary_hw_plane(crtc
->primary
, crtc
);
4262 intel_enable_planes(crtc
);
4263 intel_crtc_update_cursor(crtc
, true);
4264 intel_crtc_dpms_overlay(intel_crtc
, true);
4266 hsw_enable_ips(intel_crtc
);
4268 mutex_lock(&dev
->struct_mutex
);
4269 intel_update_fbc(dev
);
4270 mutex_unlock(&dev
->struct_mutex
);
4273 * FIXME: Once we grow proper nuclear flip support out of this we need
4274 * to compute the mask of flip planes precisely. For the time being
4275 * consider this a flip from a NULL plane.
4277 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_ALL_MASK(pipe
));
4280 static void intel_crtc_disable_planes(struct drm_crtc
*crtc
)
4282 struct drm_device
*dev
= crtc
->dev
;
4283 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4284 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4285 int pipe
= intel_crtc
->pipe
;
4286 int plane
= intel_crtc
->plane
;
4288 intel_crtc_wait_for_pending_flips(crtc
);
4290 if (dev_priv
->fbc
.plane
== plane
)
4291 intel_disable_fbc(dev
);
4293 hsw_disable_ips(intel_crtc
);
4295 intel_crtc_dpms_overlay(intel_crtc
, false);
4296 intel_crtc_update_cursor(crtc
, false);
4297 intel_disable_planes(crtc
);
4298 intel_disable_primary_hw_plane(crtc
->primary
, crtc
);
4301 * FIXME: Once we grow proper nuclear flip support out of this we need
4302 * to compute the mask of flip planes precisely. For the time being
4303 * consider this a flip to a NULL plane.
4305 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_ALL_MASK(pipe
));
4308 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
4310 struct drm_device
*dev
= crtc
->dev
;
4311 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4312 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4313 struct intel_encoder
*encoder
;
4314 int pipe
= intel_crtc
->pipe
;
4316 WARN_ON(!crtc
->enabled
);
4318 if (intel_crtc
->active
)
4321 if (intel_crtc
->config
.has_pch_encoder
)
4322 intel_prepare_shared_dpll(intel_crtc
);
4324 if (intel_crtc
->config
.has_dp_encoder
)
4325 intel_dp_set_m_n(intel_crtc
);
4327 intel_set_pipe_timings(intel_crtc
);
4329 if (intel_crtc
->config
.has_pch_encoder
) {
4330 intel_cpu_transcoder_set_m_n(intel_crtc
,
4331 &intel_crtc
->config
.fdi_m_n
, NULL
);
4334 ironlake_set_pipeconf(crtc
);
4336 intel_crtc
->active
= true;
4338 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4339 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, true);
4341 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4342 if (encoder
->pre_enable
)
4343 encoder
->pre_enable(encoder
);
4345 if (intel_crtc
->config
.has_pch_encoder
) {
4346 /* Note: FDI PLL enabling _must_ be done before we enable the
4347 * cpu pipes, hence this is separate from all the other fdi/pch
4349 ironlake_fdi_pll_enable(intel_crtc
);
4351 assert_fdi_tx_disabled(dev_priv
, pipe
);
4352 assert_fdi_rx_disabled(dev_priv
, pipe
);
4355 ironlake_pfit_enable(intel_crtc
);
4358 * On ILK+ LUT must be loaded before the pipe is running but with
4361 intel_crtc_load_lut(crtc
);
4363 intel_update_watermarks(crtc
);
4364 intel_enable_pipe(intel_crtc
);
4366 if (intel_crtc
->config
.has_pch_encoder
)
4367 ironlake_pch_enable(crtc
);
4369 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4370 encoder
->enable(encoder
);
4372 if (HAS_PCH_CPT(dev
))
4373 cpt_verify_modeset(dev
, intel_crtc
->pipe
);
4375 assert_vblank_disabled(crtc
);
4376 drm_crtc_vblank_on(crtc
);
4378 intel_crtc_enable_planes(crtc
);
4381 /* IPS only exists on ULT machines and is tied to pipe A. */
4382 static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc
)
4384 return HAS_IPS(crtc
->base
.dev
) && crtc
->pipe
== PIPE_A
;
4388 * This implements the workaround described in the "notes" section of the mode
4389 * set sequence documentation. When going from no pipes or single pipe to
4390 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4391 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4393 static void haswell_mode_set_planes_workaround(struct intel_crtc
*crtc
)
4395 struct drm_device
*dev
= crtc
->base
.dev
;
4396 struct intel_crtc
*crtc_it
, *other_active_crtc
= NULL
;
4398 /* We want to get the other_active_crtc only if there's only 1 other
4400 for_each_intel_crtc(dev
, crtc_it
) {
4401 if (!crtc_it
->active
|| crtc_it
== crtc
)
4404 if (other_active_crtc
)
4407 other_active_crtc
= crtc_it
;
4409 if (!other_active_crtc
)
4412 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
4413 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
4416 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
4418 struct drm_device
*dev
= crtc
->dev
;
4419 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4420 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4421 struct intel_encoder
*encoder
;
4422 int pipe
= intel_crtc
->pipe
;
4424 WARN_ON(!crtc
->enabled
);
4426 if (intel_crtc
->active
)
4429 if (intel_crtc_to_shared_dpll(intel_crtc
))
4430 intel_enable_shared_dpll(intel_crtc
);
4432 if (intel_crtc
->config
.has_dp_encoder
)
4433 intel_dp_set_m_n(intel_crtc
);
4435 intel_set_pipe_timings(intel_crtc
);
4437 if (intel_crtc
->config
.cpu_transcoder
!= TRANSCODER_EDP
) {
4438 I915_WRITE(PIPE_MULT(intel_crtc
->config
.cpu_transcoder
),
4439 intel_crtc
->config
.pixel_multiplier
- 1);
4442 if (intel_crtc
->config
.has_pch_encoder
) {
4443 intel_cpu_transcoder_set_m_n(intel_crtc
,
4444 &intel_crtc
->config
.fdi_m_n
, NULL
);
4447 haswell_set_pipeconf(crtc
);
4449 intel_set_pipe_csc(crtc
);
4451 intel_crtc
->active
= true;
4453 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4454 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4455 if (encoder
->pre_enable
)
4456 encoder
->pre_enable(encoder
);
4458 if (intel_crtc
->config
.has_pch_encoder
) {
4459 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
4461 dev_priv
->display
.fdi_link_train(crtc
);
4464 intel_ddi_enable_pipe_clock(intel_crtc
);
4466 if (IS_SKYLAKE(dev
))
4467 skylake_pfit_enable(intel_crtc
);
4469 ironlake_pfit_enable(intel_crtc
);
4472 * On ILK+ LUT must be loaded before the pipe is running but with
4475 intel_crtc_load_lut(crtc
);
4477 intel_ddi_set_pipe_settings(crtc
);
4478 intel_ddi_enable_transcoder_func(crtc
);
4480 intel_update_watermarks(crtc
);
4481 intel_enable_pipe(intel_crtc
);
4483 if (intel_crtc
->config
.has_pch_encoder
)
4484 lpt_pch_enable(crtc
);
4486 if (intel_crtc
->config
.dp_encoder_is_mst
)
4487 intel_ddi_set_vc_payload_alloc(crtc
, true);
4489 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4490 encoder
->enable(encoder
);
4491 intel_opregion_notify_encoder(encoder
, true);
4494 assert_vblank_disabled(crtc
);
4495 drm_crtc_vblank_on(crtc
);
4497 /* If we change the relative order between pipe/planes enabling, we need
4498 * to change the workaround. */
4499 haswell_mode_set_planes_workaround(intel_crtc
);
4500 intel_crtc_enable_planes(crtc
);
4503 static void skylake_pfit_disable(struct intel_crtc
*crtc
)
4505 struct drm_device
*dev
= crtc
->base
.dev
;
4506 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4507 int pipe
= crtc
->pipe
;
4509 /* To avoid upsetting the power well on haswell only disable the pfit if
4510 * it's in use. The hw state code will make sure we get this right. */
4511 if (crtc
->config
.pch_pfit
.enabled
) {
4512 I915_WRITE(PS_CTL(pipe
), 0);
4513 I915_WRITE(PS_WIN_POS(pipe
), 0);
4514 I915_WRITE(PS_WIN_SZ(pipe
), 0);
4518 static void ironlake_pfit_disable(struct intel_crtc
*crtc
)
4520 struct drm_device
*dev
= crtc
->base
.dev
;
4521 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4522 int pipe
= crtc
->pipe
;
4524 /* To avoid upsetting the power well on haswell only disable the pfit if
4525 * it's in use. The hw state code will make sure we get this right. */
4526 if (crtc
->config
.pch_pfit
.enabled
) {
4527 I915_WRITE(PF_CTL(pipe
), 0);
4528 I915_WRITE(PF_WIN_POS(pipe
), 0);
4529 I915_WRITE(PF_WIN_SZ(pipe
), 0);
4533 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
4535 struct drm_device
*dev
= crtc
->dev
;
4536 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4537 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4538 struct intel_encoder
*encoder
;
4539 int pipe
= intel_crtc
->pipe
;
4542 if (!intel_crtc
->active
)
4545 intel_crtc_disable_planes(crtc
);
4547 drm_crtc_vblank_off(crtc
);
4548 assert_vblank_disabled(crtc
);
4550 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4551 encoder
->disable(encoder
);
4553 if (intel_crtc
->config
.has_pch_encoder
)
4554 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, false);
4556 intel_disable_pipe(intel_crtc
);
4558 ironlake_pfit_disable(intel_crtc
);
4560 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4561 if (encoder
->post_disable
)
4562 encoder
->post_disable(encoder
);
4564 if (intel_crtc
->config
.has_pch_encoder
) {
4565 ironlake_fdi_disable(crtc
);
4567 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
4569 if (HAS_PCH_CPT(dev
)) {
4570 /* disable TRANS_DP_CTL */
4571 reg
= TRANS_DP_CTL(pipe
);
4572 temp
= I915_READ(reg
);
4573 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
|
4574 TRANS_DP_PORT_SEL_MASK
);
4575 temp
|= TRANS_DP_PORT_SEL_NONE
;
4576 I915_WRITE(reg
, temp
);
4578 /* disable DPLL_SEL */
4579 temp
= I915_READ(PCH_DPLL_SEL
);
4580 temp
&= ~(TRANS_DPLL_ENABLE(pipe
) | TRANS_DPLLB_SEL(pipe
));
4581 I915_WRITE(PCH_DPLL_SEL
, temp
);
4584 /* disable PCH DPLL */
4585 intel_disable_shared_dpll(intel_crtc
);
4587 ironlake_fdi_pll_disable(intel_crtc
);
4590 intel_crtc
->active
= false;
4591 intel_update_watermarks(crtc
);
4593 mutex_lock(&dev
->struct_mutex
);
4594 intel_update_fbc(dev
);
4595 mutex_unlock(&dev
->struct_mutex
);
4598 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
4600 struct drm_device
*dev
= crtc
->dev
;
4601 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4602 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4603 struct intel_encoder
*encoder
;
4604 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
4606 if (!intel_crtc
->active
)
4609 intel_crtc_disable_planes(crtc
);
4611 drm_crtc_vblank_off(crtc
);
4612 assert_vblank_disabled(crtc
);
4614 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4615 intel_opregion_notify_encoder(encoder
, false);
4616 encoder
->disable(encoder
);
4619 if (intel_crtc
->config
.has_pch_encoder
)
4620 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
4622 intel_disable_pipe(intel_crtc
);
4624 if (intel_crtc
->config
.dp_encoder_is_mst
)
4625 intel_ddi_set_vc_payload_alloc(crtc
, false);
4627 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
4629 if (IS_SKYLAKE(dev
))
4630 skylake_pfit_disable(intel_crtc
);
4632 ironlake_pfit_disable(intel_crtc
);
4634 intel_ddi_disable_pipe_clock(intel_crtc
);
4636 if (intel_crtc
->config
.has_pch_encoder
) {
4637 lpt_disable_pch_transcoder(dev_priv
);
4638 intel_ddi_fdi_disable(crtc
);
4641 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4642 if (encoder
->post_disable
)
4643 encoder
->post_disable(encoder
);
4645 intel_crtc
->active
= false;
4646 intel_update_watermarks(crtc
);
4648 mutex_lock(&dev
->struct_mutex
);
4649 intel_update_fbc(dev
);
4650 mutex_unlock(&dev
->struct_mutex
);
4652 if (intel_crtc_to_shared_dpll(intel_crtc
))
4653 intel_disable_shared_dpll(intel_crtc
);
4656 static void ironlake_crtc_off(struct drm_crtc
*crtc
)
4658 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4659 intel_put_shared_dpll(intel_crtc
);
4663 static void i9xx_pfit_enable(struct intel_crtc
*crtc
)
4665 struct drm_device
*dev
= crtc
->base
.dev
;
4666 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4667 struct intel_crtc_config
*pipe_config
= &crtc
->config
;
4669 if (!crtc
->config
.gmch_pfit
.control
)
4673 * The panel fitter should only be adjusted whilst the pipe is disabled,
4674 * according to register description and PRM.
4676 WARN_ON(I915_READ(PFIT_CONTROL
) & PFIT_ENABLE
);
4677 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
4679 I915_WRITE(PFIT_PGM_RATIOS
, pipe_config
->gmch_pfit
.pgm_ratios
);
4680 I915_WRITE(PFIT_CONTROL
, pipe_config
->gmch_pfit
.control
);
4682 /* Border color in case we don't scale up to the full screen. Black by
4683 * default, change to something else for debugging. */
4684 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
4687 static enum intel_display_power_domain
port_to_power_domain(enum port port
)
4691 return POWER_DOMAIN_PORT_DDI_A_4_LANES
;
4693 return POWER_DOMAIN_PORT_DDI_B_4_LANES
;
4695 return POWER_DOMAIN_PORT_DDI_C_4_LANES
;
4697 return POWER_DOMAIN_PORT_DDI_D_4_LANES
;
4700 return POWER_DOMAIN_PORT_OTHER
;
4704 #define for_each_power_domain(domain, mask) \
4705 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4706 if ((1 << (domain)) & (mask))
4708 enum intel_display_power_domain
4709 intel_display_port_power_domain(struct intel_encoder
*intel_encoder
)
4711 struct drm_device
*dev
= intel_encoder
->base
.dev
;
4712 struct intel_digital_port
*intel_dig_port
;
4714 switch (intel_encoder
->type
) {
4715 case INTEL_OUTPUT_UNKNOWN
:
4716 /* Only DDI platforms should ever use this output type */
4717 WARN_ON_ONCE(!HAS_DDI(dev
));
4718 case INTEL_OUTPUT_DISPLAYPORT
:
4719 case INTEL_OUTPUT_HDMI
:
4720 case INTEL_OUTPUT_EDP
:
4721 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
4722 return port_to_power_domain(intel_dig_port
->port
);
4723 case INTEL_OUTPUT_DP_MST
:
4724 intel_dig_port
= enc_to_mst(&intel_encoder
->base
)->primary
;
4725 return port_to_power_domain(intel_dig_port
->port
);
4726 case INTEL_OUTPUT_ANALOG
:
4727 return POWER_DOMAIN_PORT_CRT
;
4728 case INTEL_OUTPUT_DSI
:
4729 return POWER_DOMAIN_PORT_DSI
;
4731 return POWER_DOMAIN_PORT_OTHER
;
4735 static unsigned long get_crtc_power_domains(struct drm_crtc
*crtc
)
4737 struct drm_device
*dev
= crtc
->dev
;
4738 struct intel_encoder
*intel_encoder
;
4739 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4740 enum pipe pipe
= intel_crtc
->pipe
;
4742 enum transcoder transcoder
;
4744 transcoder
= intel_pipe_to_cpu_transcoder(dev
->dev_private
, pipe
);
4746 mask
= BIT(POWER_DOMAIN_PIPE(pipe
));
4747 mask
|= BIT(POWER_DOMAIN_TRANSCODER(transcoder
));
4748 if (intel_crtc
->config
.pch_pfit
.enabled
||
4749 intel_crtc
->config
.pch_pfit
.force_thru
)
4750 mask
|= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe
));
4752 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
4753 mask
|= BIT(intel_display_port_power_domain(intel_encoder
));
4758 static void modeset_update_crtc_power_domains(struct drm_device
*dev
)
4760 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4761 unsigned long pipe_domains
[I915_MAX_PIPES
] = { 0, };
4762 struct intel_crtc
*crtc
;
4765 * First get all needed power domains, then put all unneeded, to avoid
4766 * any unnecessary toggling of the power wells.
4768 for_each_intel_crtc(dev
, crtc
) {
4769 enum intel_display_power_domain domain
;
4771 if (!crtc
->base
.enabled
)
4774 pipe_domains
[crtc
->pipe
] = get_crtc_power_domains(&crtc
->base
);
4776 for_each_power_domain(domain
, pipe_domains
[crtc
->pipe
])
4777 intel_display_power_get(dev_priv
, domain
);
4780 if (dev_priv
->display
.modeset_global_resources
)
4781 dev_priv
->display
.modeset_global_resources(dev
);
4783 for_each_intel_crtc(dev
, crtc
) {
4784 enum intel_display_power_domain domain
;
4786 for_each_power_domain(domain
, crtc
->enabled_power_domains
)
4787 intel_display_power_put(dev_priv
, domain
);
4789 crtc
->enabled_power_domains
= pipe_domains
[crtc
->pipe
];
4792 intel_display_set_init_power(dev_priv
, false);
4795 /* returns HPLL frequency in kHz */
4796 static int valleyview_get_vco(struct drm_i915_private
*dev_priv
)
4798 int hpll_freq
, vco_freq
[] = { 800, 1600, 2000, 2400 };
4800 /* Obtain SKU information */
4801 mutex_lock(&dev_priv
->dpio_lock
);
4802 hpll_freq
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
) &
4803 CCK_FUSE_HPLL_FREQ_MASK
;
4804 mutex_unlock(&dev_priv
->dpio_lock
);
4806 return vco_freq
[hpll_freq
] * 1000;
4809 static void vlv_update_cdclk(struct drm_device
*dev
)
4811 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4813 dev_priv
->vlv_cdclk_freq
= dev_priv
->display
.get_display_clock_speed(dev
);
4814 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4815 dev_priv
->vlv_cdclk_freq
);
4818 * Program the gmbus_freq based on the cdclk frequency.
4819 * BSpec erroneously claims we should aim for 4MHz, but
4820 * in fact 1MHz is the correct frequency.
4822 I915_WRITE(GMBUSFREQ_VLV
, DIV_ROUND_UP(dev_priv
->vlv_cdclk_freq
, 1000));
4825 /* Adjust CDclk dividers to allow high res or save power if possible */
4826 static void valleyview_set_cdclk(struct drm_device
*dev
, int cdclk
)
4828 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4831 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
) != dev_priv
->vlv_cdclk_freq
);
4833 if (cdclk
>= 320000) /* jump to highest voltage for 400MHz too */
4835 else if (cdclk
== 266667)
4840 mutex_lock(&dev_priv
->rps
.hw_lock
);
4841 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
4842 val
&= ~DSPFREQGUAR_MASK
;
4843 val
|= (cmd
<< DSPFREQGUAR_SHIFT
);
4844 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
4845 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
4846 DSPFREQSTAT_MASK
) == (cmd
<< DSPFREQSTAT_SHIFT
),
4848 DRM_ERROR("timed out waiting for CDclk change\n");
4850 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4852 if (cdclk
== 400000) {
4855 divider
= DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, cdclk
) - 1;
4857 mutex_lock(&dev_priv
->dpio_lock
);
4858 /* adjust cdclk divider */
4859 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
4860 val
&= ~DISPLAY_FREQUENCY_VALUES
;
4862 vlv_cck_write(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
, val
);
4864 if (wait_for((vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
) &
4865 DISPLAY_FREQUENCY_STATUS
) == (divider
<< DISPLAY_FREQUENCY_STATUS_SHIFT
),
4867 DRM_ERROR("timed out waiting for CDclk change\n");
4868 mutex_unlock(&dev_priv
->dpio_lock
);
4871 mutex_lock(&dev_priv
->dpio_lock
);
4872 /* adjust self-refresh exit latency value */
4873 val
= vlv_bunit_read(dev_priv
, BUNIT_REG_BISOC
);
4877 * For high bandwidth configs, we set a higher latency in the bunit
4878 * so that the core display fetch happens in time to avoid underruns.
4880 if (cdclk
== 400000)
4881 val
|= 4500 / 250; /* 4.5 usec */
4883 val
|= 3000 / 250; /* 3.0 usec */
4884 vlv_bunit_write(dev_priv
, BUNIT_REG_BISOC
, val
);
4885 mutex_unlock(&dev_priv
->dpio_lock
);
4887 vlv_update_cdclk(dev
);
4890 static void cherryview_set_cdclk(struct drm_device
*dev
, int cdclk
)
4892 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4895 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
) != dev_priv
->vlv_cdclk_freq
);
4916 mutex_lock(&dev_priv
->rps
.hw_lock
);
4917 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
4918 val
&= ~DSPFREQGUAR_MASK_CHV
;
4919 val
|= (cmd
<< DSPFREQGUAR_SHIFT_CHV
);
4920 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
4921 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
4922 DSPFREQSTAT_MASK_CHV
) == (cmd
<< DSPFREQSTAT_SHIFT_CHV
),
4924 DRM_ERROR("timed out waiting for CDclk change\n");
4926 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4928 vlv_update_cdclk(dev
);
4931 static int valleyview_calc_cdclk(struct drm_i915_private
*dev_priv
,
4934 int freq_320
= (dev_priv
->hpll_freq
<< 1) % 320000 != 0 ? 333333 : 320000;
4936 /* FIXME: Punit isn't quite ready yet */
4937 if (IS_CHERRYVIEW(dev_priv
->dev
))
4941 * Really only a few cases to deal with, as only 4 CDclks are supported:
4944 * 320/333MHz (depends on HPLL freq)
4946 * So we check to see whether we're above 90% of the lower bin and
4949 * We seem to get an unstable or solid color picture at 200MHz.
4950 * Not sure what's wrong. For now use 200MHz only when all pipes
4953 if (max_pixclk
> freq_320
*9/10)
4955 else if (max_pixclk
> 266667*9/10)
4957 else if (max_pixclk
> 0)
4963 /* compute the max pixel clock for new configuration */
4964 static int intel_mode_max_pixclk(struct drm_i915_private
*dev_priv
)
4966 struct drm_device
*dev
= dev_priv
->dev
;
4967 struct intel_crtc
*intel_crtc
;
4970 for_each_intel_crtc(dev
, intel_crtc
) {
4971 if (intel_crtc
->new_enabled
)
4972 max_pixclk
= max(max_pixclk
,
4973 intel_crtc
->new_config
->adjusted_mode
.crtc_clock
);
4979 static void valleyview_modeset_global_pipes(struct drm_device
*dev
,
4980 unsigned *prepare_pipes
)
4982 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4983 struct intel_crtc
*intel_crtc
;
4984 int max_pixclk
= intel_mode_max_pixclk(dev_priv
);
4986 if (valleyview_calc_cdclk(dev_priv
, max_pixclk
) ==
4987 dev_priv
->vlv_cdclk_freq
)
4990 /* disable/enable all currently active pipes while we change cdclk */
4991 for_each_intel_crtc(dev
, intel_crtc
)
4992 if (intel_crtc
->base
.enabled
)
4993 *prepare_pipes
|= (1 << intel_crtc
->pipe
);
4996 static void valleyview_modeset_global_resources(struct drm_device
*dev
)
4998 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4999 int max_pixclk
= intel_mode_max_pixclk(dev_priv
);
5000 int req_cdclk
= valleyview_calc_cdclk(dev_priv
, max_pixclk
);
5002 if (req_cdclk
!= dev_priv
->vlv_cdclk_freq
) {
5004 * FIXME: We can end up here with all power domains off, yet
5005 * with a CDCLK frequency other than the minimum. To account
5006 * for this take the PIPE-A power domain, which covers the HW
5007 * blocks needed for the following programming. This can be
5008 * removed once it's guaranteed that we get here either with
5009 * the minimum CDCLK set, or the required power domains
5012 intel_display_power_get(dev_priv
, POWER_DOMAIN_PIPE_A
);
5014 if (IS_CHERRYVIEW(dev
))
5015 cherryview_set_cdclk(dev
, req_cdclk
);
5017 valleyview_set_cdclk(dev
, req_cdclk
);
5019 intel_display_power_put(dev_priv
, POWER_DOMAIN_PIPE_A
);
5023 static void valleyview_crtc_enable(struct drm_crtc
*crtc
)
5025 struct drm_device
*dev
= crtc
->dev
;
5026 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5027 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5028 struct intel_encoder
*encoder
;
5029 int pipe
= intel_crtc
->pipe
;
5032 WARN_ON(!crtc
->enabled
);
5034 if (intel_crtc
->active
)
5037 is_dsi
= intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
);
5040 if (IS_CHERRYVIEW(dev
))
5041 chv_prepare_pll(intel_crtc
, &intel_crtc
->config
);
5043 vlv_prepare_pll(intel_crtc
, &intel_crtc
->config
);
5046 if (intel_crtc
->config
.has_dp_encoder
)
5047 intel_dp_set_m_n(intel_crtc
);
5049 intel_set_pipe_timings(intel_crtc
);
5051 if (IS_CHERRYVIEW(dev
) && pipe
== PIPE_B
) {
5052 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5054 I915_WRITE(CHV_BLEND(pipe
), CHV_BLEND_LEGACY
);
5055 I915_WRITE(CHV_CANVAS(pipe
), 0);
5058 i9xx_set_pipeconf(intel_crtc
);
5060 intel_crtc
->active
= true;
5062 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5064 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5065 if (encoder
->pre_pll_enable
)
5066 encoder
->pre_pll_enable(encoder
);
5069 if (IS_CHERRYVIEW(dev
))
5070 chv_enable_pll(intel_crtc
, &intel_crtc
->config
);
5072 vlv_enable_pll(intel_crtc
, &intel_crtc
->config
);
5075 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5076 if (encoder
->pre_enable
)
5077 encoder
->pre_enable(encoder
);
5079 i9xx_pfit_enable(intel_crtc
);
5081 intel_crtc_load_lut(crtc
);
5083 intel_update_watermarks(crtc
);
5084 intel_enable_pipe(intel_crtc
);
5086 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5087 encoder
->enable(encoder
);
5089 assert_vblank_disabled(crtc
);
5090 drm_crtc_vblank_on(crtc
);
5092 intel_crtc_enable_planes(crtc
);
5094 /* Underruns don't raise interrupts, so check manually. */
5095 i9xx_check_fifo_underruns(dev_priv
);
5098 static void i9xx_set_pll_dividers(struct intel_crtc
*crtc
)
5100 struct drm_device
*dev
= crtc
->base
.dev
;
5101 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5103 I915_WRITE(FP0(crtc
->pipe
), crtc
->config
.dpll_hw_state
.fp0
);
5104 I915_WRITE(FP1(crtc
->pipe
), crtc
->config
.dpll_hw_state
.fp1
);
5107 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
5109 struct drm_device
*dev
= crtc
->dev
;
5110 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5111 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5112 struct intel_encoder
*encoder
;
5113 int pipe
= intel_crtc
->pipe
;
5115 WARN_ON(!crtc
->enabled
);
5117 if (intel_crtc
->active
)
5120 i9xx_set_pll_dividers(intel_crtc
);
5122 if (intel_crtc
->config
.has_dp_encoder
)
5123 intel_dp_set_m_n(intel_crtc
);
5125 intel_set_pipe_timings(intel_crtc
);
5127 i9xx_set_pipeconf(intel_crtc
);
5129 intel_crtc
->active
= true;
5132 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5134 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5135 if (encoder
->pre_enable
)
5136 encoder
->pre_enable(encoder
);
5138 i9xx_enable_pll(intel_crtc
);
5140 i9xx_pfit_enable(intel_crtc
);
5142 intel_crtc_load_lut(crtc
);
5144 intel_update_watermarks(crtc
);
5145 intel_enable_pipe(intel_crtc
);
5147 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5148 encoder
->enable(encoder
);
5150 assert_vblank_disabled(crtc
);
5151 drm_crtc_vblank_on(crtc
);
5153 intel_crtc_enable_planes(crtc
);
5156 * Gen2 reports pipe underruns whenever all planes are disabled.
5157 * So don't enable underrun reporting before at least some planes
5159 * FIXME: Need to fix the logic to work when we turn off all planes
5160 * but leave the pipe running.
5163 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5165 /* Underruns don't raise interrupts, so check manually. */
5166 i9xx_check_fifo_underruns(dev_priv
);
5169 static void i9xx_pfit_disable(struct intel_crtc
*crtc
)
5171 struct drm_device
*dev
= crtc
->base
.dev
;
5172 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5174 if (!crtc
->config
.gmch_pfit
.control
)
5177 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
5179 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5180 I915_READ(PFIT_CONTROL
));
5181 I915_WRITE(PFIT_CONTROL
, 0);
5184 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
5186 struct drm_device
*dev
= crtc
->dev
;
5187 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5188 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5189 struct intel_encoder
*encoder
;
5190 int pipe
= intel_crtc
->pipe
;
5192 if (!intel_crtc
->active
)
5196 * Gen2 reports pipe underruns whenever all planes are disabled.
5197 * So diasble underrun reporting before all the planes get disabled.
5198 * FIXME: Need to fix the logic to work when we turn off all planes
5199 * but leave the pipe running.
5202 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
5205 * Vblank time updates from the shadow to live plane control register
5206 * are blocked if the memory self-refresh mode is active at that
5207 * moment. So to make sure the plane gets truly disabled, disable
5208 * first the self-refresh mode. The self-refresh enable bit in turn
5209 * will be checked/applied by the HW only at the next frame start
5210 * event which is after the vblank start event, so we need to have a
5211 * wait-for-vblank between disabling the plane and the pipe.
5213 intel_set_memory_cxsr(dev_priv
, false);
5214 intel_crtc_disable_planes(crtc
);
5217 * On gen2 planes are double buffered but the pipe isn't, so we must
5218 * wait for planes to fully turn off before disabling the pipe.
5219 * We also need to wait on all gmch platforms because of the
5220 * self-refresh mode constraint explained above.
5222 intel_wait_for_vblank(dev
, pipe
);
5224 drm_crtc_vblank_off(crtc
);
5225 assert_vblank_disabled(crtc
);
5227 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5228 encoder
->disable(encoder
);
5230 intel_disable_pipe(intel_crtc
);
5232 i9xx_pfit_disable(intel_crtc
);
5234 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5235 if (encoder
->post_disable
)
5236 encoder
->post_disable(encoder
);
5238 if (!intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
)) {
5239 if (IS_CHERRYVIEW(dev
))
5240 chv_disable_pll(dev_priv
, pipe
);
5241 else if (IS_VALLEYVIEW(dev
))
5242 vlv_disable_pll(dev_priv
, pipe
);
5244 i9xx_disable_pll(intel_crtc
);
5248 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
5250 intel_crtc
->active
= false;
5251 intel_update_watermarks(crtc
);
5253 mutex_lock(&dev
->struct_mutex
);
5254 intel_update_fbc(dev
);
5255 mutex_unlock(&dev
->struct_mutex
);
5258 static void i9xx_crtc_off(struct drm_crtc
*crtc
)
5262 /* Master function to enable/disable CRTC and corresponding power wells */
5263 void intel_crtc_control(struct drm_crtc
*crtc
, bool enable
)
5265 struct drm_device
*dev
= crtc
->dev
;
5266 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5267 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5268 enum intel_display_power_domain domain
;
5269 unsigned long domains
;
5272 if (!intel_crtc
->active
) {
5273 domains
= get_crtc_power_domains(crtc
);
5274 for_each_power_domain(domain
, domains
)
5275 intel_display_power_get(dev_priv
, domain
);
5276 intel_crtc
->enabled_power_domains
= domains
;
5278 dev_priv
->display
.crtc_enable(crtc
);
5281 if (intel_crtc
->active
) {
5282 dev_priv
->display
.crtc_disable(crtc
);
5284 domains
= intel_crtc
->enabled_power_domains
;
5285 for_each_power_domain(domain
, domains
)
5286 intel_display_power_put(dev_priv
, domain
);
5287 intel_crtc
->enabled_power_domains
= 0;
5293 * Sets the power management mode of the pipe and plane.
5295 void intel_crtc_update_dpms(struct drm_crtc
*crtc
)
5297 struct drm_device
*dev
= crtc
->dev
;
5298 struct intel_encoder
*intel_encoder
;
5299 bool enable
= false;
5301 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
5302 enable
|= intel_encoder
->connectors_active
;
5304 intel_crtc_control(crtc
, enable
);
5307 static void intel_crtc_disable(struct drm_crtc
*crtc
)
5309 struct drm_device
*dev
= crtc
->dev
;
5310 struct drm_connector
*connector
;
5311 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5312 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(crtc
->primary
->fb
);
5313 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
5315 /* crtc should still be enabled when we disable it. */
5316 WARN_ON(!crtc
->enabled
);
5318 dev_priv
->display
.crtc_disable(crtc
);
5319 dev_priv
->display
.off(crtc
);
5321 if (crtc
->primary
->fb
) {
5322 mutex_lock(&dev
->struct_mutex
);
5323 intel_unpin_fb_obj(old_obj
);
5324 i915_gem_track_fb(old_obj
, NULL
,
5325 INTEL_FRONTBUFFER_PRIMARY(pipe
));
5326 mutex_unlock(&dev
->struct_mutex
);
5327 crtc
->primary
->fb
= NULL
;
5330 /* Update computed state. */
5331 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
5332 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
5335 if (connector
->encoder
->crtc
!= crtc
)
5338 connector
->dpms
= DRM_MODE_DPMS_OFF
;
5339 to_intel_encoder(connector
->encoder
)->connectors_active
= false;
5343 void intel_encoder_destroy(struct drm_encoder
*encoder
)
5345 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
5347 drm_encoder_cleanup(encoder
);
5348 kfree(intel_encoder
);
5351 /* Simple dpms helper for encoders with just one connector, no cloning and only
5352 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5353 * state of the entire output pipe. */
5354 static void intel_encoder_dpms(struct intel_encoder
*encoder
, int mode
)
5356 if (mode
== DRM_MODE_DPMS_ON
) {
5357 encoder
->connectors_active
= true;
5359 intel_crtc_update_dpms(encoder
->base
.crtc
);
5361 encoder
->connectors_active
= false;
5363 intel_crtc_update_dpms(encoder
->base
.crtc
);
5367 /* Cross check the actual hw state with our own modeset state tracking (and it's
5368 * internal consistency). */
5369 static void intel_connector_check_state(struct intel_connector
*connector
)
5371 if (connector
->get_hw_state(connector
)) {
5372 struct intel_encoder
*encoder
= connector
->encoder
;
5373 struct drm_crtc
*crtc
;
5374 bool encoder_enabled
;
5377 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5378 connector
->base
.base
.id
,
5379 connector
->base
.name
);
5381 /* there is no real hw state for MST connectors */
5382 if (connector
->mst_port
)
5385 WARN(connector
->base
.dpms
== DRM_MODE_DPMS_OFF
,
5386 "wrong connector dpms state\n");
5387 WARN(connector
->base
.encoder
!= &encoder
->base
,
5388 "active connector not linked to encoder\n");
5391 WARN(!encoder
->connectors_active
,
5392 "encoder->connectors_active not set\n");
5394 encoder_enabled
= encoder
->get_hw_state(encoder
, &pipe
);
5395 WARN(!encoder_enabled
, "encoder not enabled\n");
5396 if (WARN_ON(!encoder
->base
.crtc
))
5399 crtc
= encoder
->base
.crtc
;
5401 WARN(!crtc
->enabled
, "crtc not enabled\n");
5402 WARN(!to_intel_crtc(crtc
)->active
, "crtc not active\n");
5403 WARN(pipe
!= to_intel_crtc(crtc
)->pipe
,
5404 "encoder active on the wrong pipe\n");
5409 /* Even simpler default implementation, if there's really no special case to
5411 void intel_connector_dpms(struct drm_connector
*connector
, int mode
)
5413 /* All the simple cases only support two dpms states. */
5414 if (mode
!= DRM_MODE_DPMS_ON
)
5415 mode
= DRM_MODE_DPMS_OFF
;
5417 if (mode
== connector
->dpms
)
5420 connector
->dpms
= mode
;
5422 /* Only need to change hw state when actually enabled */
5423 if (connector
->encoder
)
5424 intel_encoder_dpms(to_intel_encoder(connector
->encoder
), mode
);
5426 intel_modeset_check_state(connector
->dev
);
5429 /* Simple connector->get_hw_state implementation for encoders that support only
5430 * one connector and no cloning and hence the encoder state determines the state
5431 * of the connector. */
5432 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
5435 struct intel_encoder
*encoder
= connector
->encoder
;
5437 return encoder
->get_hw_state(encoder
, &pipe
);
5440 static bool ironlake_check_fdi_lanes(struct drm_device
*dev
, enum pipe pipe
,
5441 struct intel_crtc_config
*pipe_config
)
5443 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5444 struct intel_crtc
*pipe_B_crtc
=
5445 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
5447 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5448 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5449 if (pipe_config
->fdi_lanes
> 4) {
5450 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5451 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5455 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
5456 if (pipe_config
->fdi_lanes
> 2) {
5457 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5458 pipe_config
->fdi_lanes
);
5465 if (INTEL_INFO(dev
)->num_pipes
== 2)
5468 /* Ivybridge 3 pipe is really complicated */
5473 if (dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]->enabled
&&
5474 pipe_config
->fdi_lanes
> 2) {
5475 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5476 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5481 if (!pipe_has_enabled_pch(pipe_B_crtc
) ||
5482 pipe_B_crtc
->config
.fdi_lanes
<= 2) {
5483 if (pipe_config
->fdi_lanes
> 2) {
5484 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5485 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5489 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5499 static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc
,
5500 struct intel_crtc_config
*pipe_config
)
5502 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5503 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
5504 int lane
, link_bw
, fdi_dotclock
;
5505 bool setup_ok
, needs_recompute
= false;
5508 /* FDI is a binary signal running at ~2.7GHz, encoding
5509 * each output octet as 10 bits. The actual frequency
5510 * is stored as a divider into a 100MHz clock, and the
5511 * mode pixel clock is stored in units of 1KHz.
5512 * Hence the bw of each lane in terms of the mode signal
5515 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
5517 fdi_dotclock
= adjusted_mode
->crtc_clock
;
5519 lane
= ironlake_get_lanes_required(fdi_dotclock
, link_bw
,
5520 pipe_config
->pipe_bpp
);
5522 pipe_config
->fdi_lanes
= lane
;
5524 intel_link_compute_m_n(pipe_config
->pipe_bpp
, lane
, fdi_dotclock
,
5525 link_bw
, &pipe_config
->fdi_m_n
);
5527 setup_ok
= ironlake_check_fdi_lanes(intel_crtc
->base
.dev
,
5528 intel_crtc
->pipe
, pipe_config
);
5529 if (!setup_ok
&& pipe_config
->pipe_bpp
> 6*3) {
5530 pipe_config
->pipe_bpp
-= 2*3;
5531 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5532 pipe_config
->pipe_bpp
);
5533 needs_recompute
= true;
5534 pipe_config
->bw_constrained
= true;
5539 if (needs_recompute
)
5542 return setup_ok
? 0 : -EINVAL
;
5545 static void hsw_compute_ips_config(struct intel_crtc
*crtc
,
5546 struct intel_crtc_config
*pipe_config
)
5548 pipe_config
->ips_enabled
= i915
.enable_ips
&&
5549 hsw_crtc_supports_ips(crtc
) &&
5550 pipe_config
->pipe_bpp
<= 24;
5553 static int intel_crtc_compute_config(struct intel_crtc
*crtc
,
5554 struct intel_crtc_config
*pipe_config
)
5556 struct drm_device
*dev
= crtc
->base
.dev
;
5557 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5558 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
5560 /* FIXME should check pixel clock limits on all platforms */
5561 if (INTEL_INFO(dev
)->gen
< 4) {
5563 dev_priv
->display
.get_display_clock_speed(dev
);
5566 * Enable pixel doubling when the dot clock
5567 * is > 90% of the (display) core speed.
5569 * GDG double wide on either pipe,
5570 * otherwise pipe A only.
5572 if ((crtc
->pipe
== PIPE_A
|| IS_I915G(dev
)) &&
5573 adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10) {
5575 pipe_config
->double_wide
= true;
5578 if (adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10)
5583 * Pipe horizontal size must be even in:
5585 * - LVDS dual channel mode
5586 * - Double wide pipe
5588 if ((intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
5589 intel_is_dual_link_lvds(dev
)) || pipe_config
->double_wide
)
5590 pipe_config
->pipe_src_w
&= ~1;
5592 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5593 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5595 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
5596 adjusted_mode
->hsync_start
== adjusted_mode
->hdisplay
)
5599 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) && pipe_config
->pipe_bpp
> 10*3) {
5600 pipe_config
->pipe_bpp
= 10*3; /* 12bpc is gen5+ */
5601 } else if (INTEL_INFO(dev
)->gen
<= 4 && pipe_config
->pipe_bpp
> 8*3) {
5602 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5604 pipe_config
->pipe_bpp
= 8*3;
5608 hsw_compute_ips_config(crtc
, pipe_config
);
5610 if (pipe_config
->has_pch_encoder
)
5611 return ironlake_fdi_compute_config(crtc
, pipe_config
);
5616 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
5618 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5622 /* FIXME: Punit isn't quite ready yet */
5623 if (IS_CHERRYVIEW(dev
))
5626 if (dev_priv
->hpll_freq
== 0)
5627 dev_priv
->hpll_freq
= valleyview_get_vco(dev_priv
);
5629 mutex_lock(&dev_priv
->dpio_lock
);
5630 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
5631 mutex_unlock(&dev_priv
->dpio_lock
);
5633 divider
= val
& DISPLAY_FREQUENCY_VALUES
;
5635 WARN((val
& DISPLAY_FREQUENCY_STATUS
) !=
5636 (divider
<< DISPLAY_FREQUENCY_STATUS_SHIFT
),
5637 "cdclk change in progress\n");
5639 return DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, divider
+ 1);
5642 static int i945_get_display_clock_speed(struct drm_device
*dev
)
5647 static int i915_get_display_clock_speed(struct drm_device
*dev
)
5652 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
5657 static int pnv_get_display_clock_speed(struct drm_device
*dev
)
5661 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
5663 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
5664 case GC_DISPLAY_CLOCK_267_MHZ_PNV
:
5666 case GC_DISPLAY_CLOCK_333_MHZ_PNV
:
5668 case GC_DISPLAY_CLOCK_444_MHZ_PNV
:
5670 case GC_DISPLAY_CLOCK_200_MHZ_PNV
:
5673 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc
);
5674 case GC_DISPLAY_CLOCK_133_MHZ_PNV
:
5676 case GC_DISPLAY_CLOCK_167_MHZ_PNV
:
5681 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
5685 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
5687 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
5690 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
5691 case GC_DISPLAY_CLOCK_333_MHZ
:
5694 case GC_DISPLAY_CLOCK_190_200_MHZ
:
5700 static int i865_get_display_clock_speed(struct drm_device
*dev
)
5705 static int i855_get_display_clock_speed(struct drm_device
*dev
)
5708 /* Assume that the hardware is in the high speed state. This
5709 * should be the default.
5711 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
5712 case GC_CLOCK_133_200
:
5713 case GC_CLOCK_100_200
:
5715 case GC_CLOCK_166_250
:
5717 case GC_CLOCK_100_133
:
5721 /* Shouldn't happen */
5725 static int i830_get_display_clock_speed(struct drm_device
*dev
)
5731 intel_reduce_m_n_ratio(uint32_t *num
, uint32_t *den
)
5733 while (*num
> DATA_LINK_M_N_MASK
||
5734 *den
> DATA_LINK_M_N_MASK
) {
5740 static void compute_m_n(unsigned int m
, unsigned int n
,
5741 uint32_t *ret_m
, uint32_t *ret_n
)
5743 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
5744 *ret_m
= div_u64((uint64_t) m
* *ret_n
, n
);
5745 intel_reduce_m_n_ratio(ret_m
, ret_n
);
5749 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
5750 int pixel_clock
, int link_clock
,
5751 struct intel_link_m_n
*m_n
)
5755 compute_m_n(bits_per_pixel
* pixel_clock
,
5756 link_clock
* nlanes
* 8,
5757 &m_n
->gmch_m
, &m_n
->gmch_n
);
5759 compute_m_n(pixel_clock
, link_clock
,
5760 &m_n
->link_m
, &m_n
->link_n
);
5763 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
5765 if (i915
.panel_use_ssc
>= 0)
5766 return i915
.panel_use_ssc
!= 0;
5767 return dev_priv
->vbt
.lvds_use_ssc
5768 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
5771 static int i9xx_get_refclk(struct intel_crtc
*crtc
, int num_connectors
)
5773 struct drm_device
*dev
= crtc
->base
.dev
;
5774 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5777 if (IS_VALLEYVIEW(dev
)) {
5779 } else if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
) &&
5780 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
5781 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
5782 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
5783 } else if (!IS_GEN2(dev
)) {
5792 static uint32_t pnv_dpll_compute_fp(struct dpll
*dpll
)
5794 return (1 << dpll
->n
) << 16 | dpll
->m2
;
5797 static uint32_t i9xx_dpll_compute_fp(struct dpll
*dpll
)
5799 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
5802 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
5803 intel_clock_t
*reduced_clock
)
5805 struct drm_device
*dev
= crtc
->base
.dev
;
5808 if (IS_PINEVIEW(dev
)) {
5809 fp
= pnv_dpll_compute_fp(&crtc
->new_config
->dpll
);
5811 fp2
= pnv_dpll_compute_fp(reduced_clock
);
5813 fp
= i9xx_dpll_compute_fp(&crtc
->new_config
->dpll
);
5815 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
5818 crtc
->new_config
->dpll_hw_state
.fp0
= fp
;
5820 crtc
->lowfreq_avail
= false;
5821 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
) &&
5822 reduced_clock
&& i915
.powersave
) {
5823 crtc
->new_config
->dpll_hw_state
.fp1
= fp2
;
5824 crtc
->lowfreq_avail
= true;
5826 crtc
->new_config
->dpll_hw_state
.fp1
= fp
;
5830 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
, enum pipe
5836 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5837 * and set it to a reasonable value instead.
5839 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
5840 reg_val
&= 0xffffff00;
5841 reg_val
|= 0x00000030;
5842 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
5844 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
5845 reg_val
&= 0x8cffffff;
5846 reg_val
= 0x8c000000;
5847 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
5849 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
5850 reg_val
&= 0xffffff00;
5851 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
5853 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
5854 reg_val
&= 0x00ffffff;
5855 reg_val
|= 0xb0000000;
5856 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
5859 static void intel_pch_transcoder_set_m_n(struct intel_crtc
*crtc
,
5860 struct intel_link_m_n
*m_n
)
5862 struct drm_device
*dev
= crtc
->base
.dev
;
5863 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5864 int pipe
= crtc
->pipe
;
5866 I915_WRITE(PCH_TRANS_DATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5867 I915_WRITE(PCH_TRANS_DATA_N1(pipe
), m_n
->gmch_n
);
5868 I915_WRITE(PCH_TRANS_LINK_M1(pipe
), m_n
->link_m
);
5869 I915_WRITE(PCH_TRANS_LINK_N1(pipe
), m_n
->link_n
);
5872 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
5873 struct intel_link_m_n
*m_n
,
5874 struct intel_link_m_n
*m2_n2
)
5876 struct drm_device
*dev
= crtc
->base
.dev
;
5877 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5878 int pipe
= crtc
->pipe
;
5879 enum transcoder transcoder
= crtc
->config
.cpu_transcoder
;
5881 if (INTEL_INFO(dev
)->gen
>= 5) {
5882 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5883 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
5884 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
5885 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
5886 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5887 * for gen < 8) and if DRRS is supported (to make sure the
5888 * registers are not unnecessarily accessed).
5890 if (m2_n2
&& INTEL_INFO(dev
)->gen
< 8 &&
5891 crtc
->config
.has_drrs
) {
5892 I915_WRITE(PIPE_DATA_M2(transcoder
),
5893 TU_SIZE(m2_n2
->tu
) | m2_n2
->gmch_m
);
5894 I915_WRITE(PIPE_DATA_N2(transcoder
), m2_n2
->gmch_n
);
5895 I915_WRITE(PIPE_LINK_M2(transcoder
), m2_n2
->link_m
);
5896 I915_WRITE(PIPE_LINK_N2(transcoder
), m2_n2
->link_n
);
5899 I915_WRITE(PIPE_DATA_M_G4X(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5900 I915_WRITE(PIPE_DATA_N_G4X(pipe
), m_n
->gmch_n
);
5901 I915_WRITE(PIPE_LINK_M_G4X(pipe
), m_n
->link_m
);
5902 I915_WRITE(PIPE_LINK_N_G4X(pipe
), m_n
->link_n
);
5906 void intel_dp_set_m_n(struct intel_crtc
*crtc
)
5908 if (crtc
->config
.has_pch_encoder
)
5909 intel_pch_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
);
5911 intel_cpu_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
,
5912 &crtc
->config
.dp_m2_n2
);
5915 static void vlv_update_pll(struct intel_crtc
*crtc
,
5916 struct intel_crtc_config
*pipe_config
)
5921 * Enable DPIO clock input. We should never disable the reference
5922 * clock for pipe B, since VGA hotplug / manual detection depends
5925 dpll
= DPLL_EXT_BUFFER_ENABLE_VLV
| DPLL_REFA_CLK_ENABLE_VLV
|
5926 DPLL_VGA_MODE_DIS
| DPLL_INTEGRATED_CLOCK_VLV
;
5927 /* We should never disable this, set it here for state tracking */
5928 if (crtc
->pipe
== PIPE_B
)
5929 dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
5930 dpll
|= DPLL_VCO_ENABLE
;
5931 pipe_config
->dpll_hw_state
.dpll
= dpll
;
5933 dpll_md
= (pipe_config
->pixel_multiplier
- 1)
5934 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
5935 pipe_config
->dpll_hw_state
.dpll_md
= dpll_md
;
5938 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
5939 const struct intel_crtc_config
*pipe_config
)
5941 struct drm_device
*dev
= crtc
->base
.dev
;
5942 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5943 int pipe
= crtc
->pipe
;
5945 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
5946 u32 coreclk
, reg_val
;
5948 mutex_lock(&dev_priv
->dpio_lock
);
5950 bestn
= pipe_config
->dpll
.n
;
5951 bestm1
= pipe_config
->dpll
.m1
;
5952 bestm2
= pipe_config
->dpll
.m2
;
5953 bestp1
= pipe_config
->dpll
.p1
;
5954 bestp2
= pipe_config
->dpll
.p2
;
5956 /* See eDP HDMI DPIO driver vbios notes doc */
5958 /* PLL B needs special handling */
5960 vlv_pllb_recal_opamp(dev_priv
, pipe
);
5962 /* Set up Tx target for periodic Rcomp update */
5963 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9_BCAST
, 0x0100000f);
5965 /* Disable target IRef on PLL */
5966 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW8(pipe
));
5967 reg_val
&= 0x00ffffff;
5968 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW8(pipe
), reg_val
);
5970 /* Disable fast lock */
5971 vlv_dpio_write(dev_priv
, pipe
, VLV_CMN_DW0
, 0x610);
5973 /* Set idtafcrecal before PLL is enabled */
5974 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
5975 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
5976 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
5977 mdiv
|= (1 << DPIO_K_SHIFT
);
5980 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5981 * but we don't support that).
5982 * Note: don't use the DAC post divider as it seems unstable.
5984 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
5985 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
5987 mdiv
|= DPIO_ENABLE_CALIBRATION
;
5988 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
5990 /* Set HBR and RBR LPF coefficients */
5991 if (pipe_config
->port_clock
== 162000 ||
5992 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
) ||
5993 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
))
5994 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
5997 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
6000 if (crtc
->config
.has_dp_encoder
) {
6001 /* Use SSC source */
6003 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
6006 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
6008 } else { /* HDMI or VGA */
6009 /* Use bend source */
6011 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
6014 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
6018 coreclk
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW7(pipe
));
6019 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
6020 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
6021 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))
6022 coreclk
|= 0x01000000;
6023 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW7(pipe
), coreclk
);
6025 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW11(pipe
), 0x87871000);
6026 mutex_unlock(&dev_priv
->dpio_lock
);
6029 static void chv_update_pll(struct intel_crtc
*crtc
,
6030 struct intel_crtc_config
*pipe_config
)
6032 pipe_config
->dpll_hw_state
.dpll
= DPLL_SSC_REF_CLOCK_CHV
|
6033 DPLL_REFA_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
|
6035 if (crtc
->pipe
!= PIPE_A
)
6036 pipe_config
->dpll_hw_state
.dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
6038 pipe_config
->dpll_hw_state
.dpll_md
=
6039 (pipe_config
->pixel_multiplier
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
6042 static void chv_prepare_pll(struct intel_crtc
*crtc
,
6043 const struct intel_crtc_config
*pipe_config
)
6045 struct drm_device
*dev
= crtc
->base
.dev
;
6046 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6047 int pipe
= crtc
->pipe
;
6048 int dpll_reg
= DPLL(crtc
->pipe
);
6049 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
6050 u32 loopfilter
, intcoeff
;
6051 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
, bestm2_frac
;
6054 bestn
= pipe_config
->dpll
.n
;
6055 bestm2_frac
= pipe_config
->dpll
.m2
& 0x3fffff;
6056 bestm1
= pipe_config
->dpll
.m1
;
6057 bestm2
= pipe_config
->dpll
.m2
>> 22;
6058 bestp1
= pipe_config
->dpll
.p1
;
6059 bestp2
= pipe_config
->dpll
.p2
;
6062 * Enable Refclk and SSC
6064 I915_WRITE(dpll_reg
,
6065 pipe_config
->dpll_hw_state
.dpll
& ~DPLL_VCO_ENABLE
);
6067 mutex_lock(&dev_priv
->dpio_lock
);
6069 /* p1 and p2 divider */
6070 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW13(port
),
6071 5 << DPIO_CHV_S1_DIV_SHIFT
|
6072 bestp1
<< DPIO_CHV_P1_DIV_SHIFT
|
6073 bestp2
<< DPIO_CHV_P2_DIV_SHIFT
|
6074 1 << DPIO_CHV_K_DIV_SHIFT
);
6076 /* Feedback post-divider - m2 */
6077 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW0(port
), bestm2
);
6079 /* Feedback refclk divider - n and m1 */
6080 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW1(port
),
6081 DPIO_CHV_M1_DIV_BY_2
|
6082 1 << DPIO_CHV_N_DIV_SHIFT
);
6084 /* M2 fraction division */
6085 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW2(port
), bestm2_frac
);
6087 /* M2 fraction division enable */
6088 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW3(port
),
6089 DPIO_CHV_FRAC_DIV_EN
|
6090 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT
));
6093 refclk
= i9xx_get_refclk(crtc
, 0);
6094 loopfilter
= 5 << DPIO_CHV_PROP_COEFF_SHIFT
|
6095 2 << DPIO_CHV_GAIN_CTRL_SHIFT
;
6096 if (refclk
== 100000)
6098 else if (refclk
== 38400)
6102 loopfilter
|= intcoeff
<< DPIO_CHV_INT_COEFF_SHIFT
;
6103 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW6(port
), loopfilter
);
6106 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
),
6107 vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
)) |
6110 mutex_unlock(&dev_priv
->dpio_lock
);
6114 * vlv_force_pll_on - forcibly enable just the PLL
6115 * @dev_priv: i915 private structure
6116 * @pipe: pipe PLL to enable
6117 * @dpll: PLL configuration
6119 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6120 * in cases where we need the PLL enabled even when @pipe is not going to
6123 void vlv_force_pll_on(struct drm_device
*dev
, enum pipe pipe
,
6124 const struct dpll
*dpll
)
6126 struct intel_crtc
*crtc
=
6127 to_intel_crtc(intel_get_crtc_for_pipe(dev
, pipe
));
6128 struct intel_crtc_config pipe_config
= {
6129 .pixel_multiplier
= 1,
6133 if (IS_CHERRYVIEW(dev
)) {
6134 chv_update_pll(crtc
, &pipe_config
);
6135 chv_prepare_pll(crtc
, &pipe_config
);
6136 chv_enable_pll(crtc
, &pipe_config
);
6138 vlv_update_pll(crtc
, &pipe_config
);
6139 vlv_prepare_pll(crtc
, &pipe_config
);
6140 vlv_enable_pll(crtc
, &pipe_config
);
6145 * vlv_force_pll_off - forcibly disable just the PLL
6146 * @dev_priv: i915 private structure
6147 * @pipe: pipe PLL to disable
6149 * Disable the PLL for @pipe. To be used in cases where we need
6150 * the PLL enabled even when @pipe is not going to be enabled.
6152 void vlv_force_pll_off(struct drm_device
*dev
, enum pipe pipe
)
6154 if (IS_CHERRYVIEW(dev
))
6155 chv_disable_pll(to_i915(dev
), pipe
);
6157 vlv_disable_pll(to_i915(dev
), pipe
);
6160 static void i9xx_update_pll(struct intel_crtc
*crtc
,
6161 intel_clock_t
*reduced_clock
,
6164 struct drm_device
*dev
= crtc
->base
.dev
;
6165 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6168 struct dpll
*clock
= &crtc
->new_config
->dpll
;
6170 i9xx_update_pll_dividers(crtc
, reduced_clock
);
6172 is_sdvo
= intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_SDVO
) ||
6173 intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_HDMI
);
6175 dpll
= DPLL_VGA_MODE_DIS
;
6177 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
))
6178 dpll
|= DPLLB_MODE_LVDS
;
6180 dpll
|= DPLLB_MODE_DAC_SERIAL
;
6182 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
6183 dpll
|= (crtc
->new_config
->pixel_multiplier
- 1)
6184 << SDVO_MULTIPLIER_SHIFT_HIRES
;
6188 dpll
|= DPLL_SDVO_HIGH_SPEED
;
6190 if (crtc
->new_config
->has_dp_encoder
)
6191 dpll
|= DPLL_SDVO_HIGH_SPEED
;
6193 /* compute bitmask from p1 value */
6194 if (IS_PINEVIEW(dev
))
6195 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
6197 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
6198 if (IS_G4X(dev
) && reduced_clock
)
6199 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
6201 switch (clock
->p2
) {
6203 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
6206 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
6209 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
6212 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
6215 if (INTEL_INFO(dev
)->gen
>= 4)
6216 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
6218 if (crtc
->new_config
->sdvo_tv_clock
)
6219 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
6220 else if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
) &&
6221 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
6222 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
6224 dpll
|= PLL_REF_INPUT_DREFCLK
;
6226 dpll
|= DPLL_VCO_ENABLE
;
6227 crtc
->new_config
->dpll_hw_state
.dpll
= dpll
;
6229 if (INTEL_INFO(dev
)->gen
>= 4) {
6230 u32 dpll_md
= (crtc
->new_config
->pixel_multiplier
- 1)
6231 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
6232 crtc
->new_config
->dpll_hw_state
.dpll_md
= dpll_md
;
6236 static void i8xx_update_pll(struct intel_crtc
*crtc
,
6237 intel_clock_t
*reduced_clock
,
6240 struct drm_device
*dev
= crtc
->base
.dev
;
6241 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6243 struct dpll
*clock
= &crtc
->new_config
->dpll
;
6245 i9xx_update_pll_dividers(crtc
, reduced_clock
);
6247 dpll
= DPLL_VGA_MODE_DIS
;
6249 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
)) {
6250 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
6253 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
6255 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
6257 dpll
|= PLL_P2_DIVIDE_BY_4
;
6260 if (!IS_I830(dev
) && intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_DVO
))
6261 dpll
|= DPLL_DVO_2X_MODE
;
6263 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
) &&
6264 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
6265 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
6267 dpll
|= PLL_REF_INPUT_DREFCLK
;
6269 dpll
|= DPLL_VCO_ENABLE
;
6270 crtc
->new_config
->dpll_hw_state
.dpll
= dpll
;
6273 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
)
6275 struct drm_device
*dev
= intel_crtc
->base
.dev
;
6276 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6277 enum pipe pipe
= intel_crtc
->pipe
;
6278 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
6279 struct drm_display_mode
*adjusted_mode
=
6280 &intel_crtc
->config
.adjusted_mode
;
6281 uint32_t crtc_vtotal
, crtc_vblank_end
;
6284 /* We need to be careful not to changed the adjusted mode, for otherwise
6285 * the hw state checker will get angry at the mismatch. */
6286 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
6287 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
6289 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
6290 /* the chip adds 2 halflines automatically */
6292 crtc_vblank_end
-= 1;
6294 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
6295 vsyncshift
= (adjusted_mode
->crtc_htotal
- 1) / 2;
6297 vsyncshift
= adjusted_mode
->crtc_hsync_start
-
6298 adjusted_mode
->crtc_htotal
/ 2;
6300 vsyncshift
+= adjusted_mode
->crtc_htotal
;
6303 if (INTEL_INFO(dev
)->gen
> 3)
6304 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
6306 I915_WRITE(HTOTAL(cpu_transcoder
),
6307 (adjusted_mode
->crtc_hdisplay
- 1) |
6308 ((adjusted_mode
->crtc_htotal
- 1) << 16));
6309 I915_WRITE(HBLANK(cpu_transcoder
),
6310 (adjusted_mode
->crtc_hblank_start
- 1) |
6311 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
6312 I915_WRITE(HSYNC(cpu_transcoder
),
6313 (adjusted_mode
->crtc_hsync_start
- 1) |
6314 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
6316 I915_WRITE(VTOTAL(cpu_transcoder
),
6317 (adjusted_mode
->crtc_vdisplay
- 1) |
6318 ((crtc_vtotal
- 1) << 16));
6319 I915_WRITE(VBLANK(cpu_transcoder
),
6320 (adjusted_mode
->crtc_vblank_start
- 1) |
6321 ((crtc_vblank_end
- 1) << 16));
6322 I915_WRITE(VSYNC(cpu_transcoder
),
6323 (adjusted_mode
->crtc_vsync_start
- 1) |
6324 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
6326 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6327 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6328 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6330 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
6331 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
6332 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
6334 /* pipesrc controls the size that is scaled from, which should
6335 * always be the user's requested size.
6337 I915_WRITE(PIPESRC(pipe
),
6338 ((intel_crtc
->config
.pipe_src_w
- 1) << 16) |
6339 (intel_crtc
->config
.pipe_src_h
- 1));
6342 static void intel_get_pipe_timings(struct intel_crtc
*crtc
,
6343 struct intel_crtc_config
*pipe_config
)
6345 struct drm_device
*dev
= crtc
->base
.dev
;
6346 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6347 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
6350 tmp
= I915_READ(HTOTAL(cpu_transcoder
));
6351 pipe_config
->adjusted_mode
.crtc_hdisplay
= (tmp
& 0xffff) + 1;
6352 pipe_config
->adjusted_mode
.crtc_htotal
= ((tmp
>> 16) & 0xffff) + 1;
6353 tmp
= I915_READ(HBLANK(cpu_transcoder
));
6354 pipe_config
->adjusted_mode
.crtc_hblank_start
= (tmp
& 0xffff) + 1;
6355 pipe_config
->adjusted_mode
.crtc_hblank_end
= ((tmp
>> 16) & 0xffff) + 1;
6356 tmp
= I915_READ(HSYNC(cpu_transcoder
));
6357 pipe_config
->adjusted_mode
.crtc_hsync_start
= (tmp
& 0xffff) + 1;
6358 pipe_config
->adjusted_mode
.crtc_hsync_end
= ((tmp
>> 16) & 0xffff) + 1;
6360 tmp
= I915_READ(VTOTAL(cpu_transcoder
));
6361 pipe_config
->adjusted_mode
.crtc_vdisplay
= (tmp
& 0xffff) + 1;
6362 pipe_config
->adjusted_mode
.crtc_vtotal
= ((tmp
>> 16) & 0xffff) + 1;
6363 tmp
= I915_READ(VBLANK(cpu_transcoder
));
6364 pipe_config
->adjusted_mode
.crtc_vblank_start
= (tmp
& 0xffff) + 1;
6365 pipe_config
->adjusted_mode
.crtc_vblank_end
= ((tmp
>> 16) & 0xffff) + 1;
6366 tmp
= I915_READ(VSYNC(cpu_transcoder
));
6367 pipe_config
->adjusted_mode
.crtc_vsync_start
= (tmp
& 0xffff) + 1;
6368 pipe_config
->adjusted_mode
.crtc_vsync_end
= ((tmp
>> 16) & 0xffff) + 1;
6370 if (I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_INTERLACE_MASK
) {
6371 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
6372 pipe_config
->adjusted_mode
.crtc_vtotal
+= 1;
6373 pipe_config
->adjusted_mode
.crtc_vblank_end
+= 1;
6376 tmp
= I915_READ(PIPESRC(crtc
->pipe
));
6377 pipe_config
->pipe_src_h
= (tmp
& 0xffff) + 1;
6378 pipe_config
->pipe_src_w
= ((tmp
>> 16) & 0xffff) + 1;
6380 pipe_config
->requested_mode
.vdisplay
= pipe_config
->pipe_src_h
;
6381 pipe_config
->requested_mode
.hdisplay
= pipe_config
->pipe_src_w
;
6384 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
6385 struct intel_crtc_config
*pipe_config
)
6387 mode
->hdisplay
= pipe_config
->adjusted_mode
.crtc_hdisplay
;
6388 mode
->htotal
= pipe_config
->adjusted_mode
.crtc_htotal
;
6389 mode
->hsync_start
= pipe_config
->adjusted_mode
.crtc_hsync_start
;
6390 mode
->hsync_end
= pipe_config
->adjusted_mode
.crtc_hsync_end
;
6392 mode
->vdisplay
= pipe_config
->adjusted_mode
.crtc_vdisplay
;
6393 mode
->vtotal
= pipe_config
->adjusted_mode
.crtc_vtotal
;
6394 mode
->vsync_start
= pipe_config
->adjusted_mode
.crtc_vsync_start
;
6395 mode
->vsync_end
= pipe_config
->adjusted_mode
.crtc_vsync_end
;
6397 mode
->flags
= pipe_config
->adjusted_mode
.flags
;
6399 mode
->clock
= pipe_config
->adjusted_mode
.crtc_clock
;
6400 mode
->flags
|= pipe_config
->adjusted_mode
.flags
;
6403 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
)
6405 struct drm_device
*dev
= intel_crtc
->base
.dev
;
6406 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6411 if ((intel_crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
6412 (intel_crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
6413 pipeconf
|= I915_READ(PIPECONF(intel_crtc
->pipe
)) & PIPECONF_ENABLE
;
6415 if (intel_crtc
->config
.double_wide
)
6416 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
6418 /* only g4x and later have fancy bpc/dither controls */
6419 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
6420 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6421 if (intel_crtc
->config
.dither
&& intel_crtc
->config
.pipe_bpp
!= 30)
6422 pipeconf
|= PIPECONF_DITHER_EN
|
6423 PIPECONF_DITHER_TYPE_SP
;
6425 switch (intel_crtc
->config
.pipe_bpp
) {
6427 pipeconf
|= PIPECONF_6BPC
;
6430 pipeconf
|= PIPECONF_8BPC
;
6433 pipeconf
|= PIPECONF_10BPC
;
6436 /* Case prevented by intel_choose_pipe_bpp_dither. */
6441 if (HAS_PIPE_CXSR(dev
)) {
6442 if (intel_crtc
->lowfreq_avail
) {
6443 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6444 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
6446 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6450 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
6451 if (INTEL_INFO(dev
)->gen
< 4 ||
6452 intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
6453 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
6455 pipeconf
|= PIPECONF_INTERLACE_W_SYNC_SHIFT
;
6457 pipeconf
|= PIPECONF_PROGRESSIVE
;
6459 if (IS_VALLEYVIEW(dev
) && intel_crtc
->config
.limited_color_range
)
6460 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
6462 I915_WRITE(PIPECONF(intel_crtc
->pipe
), pipeconf
);
6463 POSTING_READ(PIPECONF(intel_crtc
->pipe
));
6466 static int i9xx_crtc_compute_clock(struct intel_crtc
*crtc
)
6468 struct drm_device
*dev
= crtc
->base
.dev
;
6469 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6470 int refclk
, num_connectors
= 0;
6471 intel_clock_t clock
, reduced_clock
;
6472 bool ok
, has_reduced_clock
= false;
6473 bool is_lvds
= false, is_dsi
= false;
6474 struct intel_encoder
*encoder
;
6475 const intel_limit_t
*limit
;
6477 for_each_intel_encoder(dev
, encoder
) {
6478 if (encoder
->new_crtc
!= crtc
)
6481 switch (encoder
->type
) {
6482 case INTEL_OUTPUT_LVDS
:
6485 case INTEL_OUTPUT_DSI
:
6498 if (!crtc
->new_config
->clock_set
) {
6499 refclk
= i9xx_get_refclk(crtc
, num_connectors
);
6502 * Returns a set of divisors for the desired target clock with
6503 * the given refclk, or FALSE. The returned values represent
6504 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6507 limit
= intel_limit(crtc
, refclk
);
6508 ok
= dev_priv
->display
.find_dpll(limit
, crtc
,
6509 crtc
->new_config
->port_clock
,
6510 refclk
, NULL
, &clock
);
6512 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6516 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
6518 * Ensure we match the reduced clock's P to the target
6519 * clock. If the clocks don't match, we can't switch
6520 * the display clock by using the FP0/FP1. In such case
6521 * we will disable the LVDS downclock feature.
6524 dev_priv
->display
.find_dpll(limit
, crtc
,
6525 dev_priv
->lvds_downclock
,
6529 /* Compat-code for transition, will disappear. */
6530 crtc
->new_config
->dpll
.n
= clock
.n
;
6531 crtc
->new_config
->dpll
.m1
= clock
.m1
;
6532 crtc
->new_config
->dpll
.m2
= clock
.m2
;
6533 crtc
->new_config
->dpll
.p1
= clock
.p1
;
6534 crtc
->new_config
->dpll
.p2
= clock
.p2
;
6538 i8xx_update_pll(crtc
,
6539 has_reduced_clock
? &reduced_clock
: NULL
,
6541 } else if (IS_CHERRYVIEW(dev
)) {
6542 chv_update_pll(crtc
, crtc
->new_config
);
6543 } else if (IS_VALLEYVIEW(dev
)) {
6544 vlv_update_pll(crtc
, crtc
->new_config
);
6546 i9xx_update_pll(crtc
,
6547 has_reduced_clock
? &reduced_clock
: NULL
,
6554 static void i9xx_get_pfit_config(struct intel_crtc
*crtc
,
6555 struct intel_crtc_config
*pipe_config
)
6557 struct drm_device
*dev
= crtc
->base
.dev
;
6558 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6561 if (INTEL_INFO(dev
)->gen
<= 3 && (IS_I830(dev
) || !IS_MOBILE(dev
)))
6564 tmp
= I915_READ(PFIT_CONTROL
);
6565 if (!(tmp
& PFIT_ENABLE
))
6568 /* Check whether the pfit is attached to our pipe. */
6569 if (INTEL_INFO(dev
)->gen
< 4) {
6570 if (crtc
->pipe
!= PIPE_B
)
6573 if ((tmp
& PFIT_PIPE_MASK
) != (crtc
->pipe
<< PFIT_PIPE_SHIFT
))
6577 pipe_config
->gmch_pfit
.control
= tmp
;
6578 pipe_config
->gmch_pfit
.pgm_ratios
= I915_READ(PFIT_PGM_RATIOS
);
6579 if (INTEL_INFO(dev
)->gen
< 5)
6580 pipe_config
->gmch_pfit
.lvds_border_bits
=
6581 I915_READ(LVDS
) & LVDS_BORDER_ENABLE
;
6584 static void vlv_crtc_clock_get(struct intel_crtc
*crtc
,
6585 struct intel_crtc_config
*pipe_config
)
6587 struct drm_device
*dev
= crtc
->base
.dev
;
6588 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6589 int pipe
= pipe_config
->cpu_transcoder
;
6590 intel_clock_t clock
;
6592 int refclk
= 100000;
6594 /* In case of MIPI DPLL will not even be used */
6595 if (!(pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
))
6598 mutex_lock(&dev_priv
->dpio_lock
);
6599 mdiv
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW3(pipe
));
6600 mutex_unlock(&dev_priv
->dpio_lock
);
6602 clock
.m1
= (mdiv
>> DPIO_M1DIV_SHIFT
) & 7;
6603 clock
.m2
= mdiv
& DPIO_M2DIV_MASK
;
6604 clock
.n
= (mdiv
>> DPIO_N_SHIFT
) & 0xf;
6605 clock
.p1
= (mdiv
>> DPIO_P1_SHIFT
) & 7;
6606 clock
.p2
= (mdiv
>> DPIO_P2_SHIFT
) & 0x1f;
6608 vlv_clock(refclk
, &clock
);
6610 /* clock.dot is the fast clock */
6611 pipe_config
->port_clock
= clock
.dot
/ 5;
6614 static void i9xx_get_plane_config(struct intel_crtc
*crtc
,
6615 struct intel_plane_config
*plane_config
)
6617 struct drm_device
*dev
= crtc
->base
.dev
;
6618 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6619 u32 val
, base
, offset
;
6620 int pipe
= crtc
->pipe
, plane
= crtc
->plane
;
6621 int fourcc
, pixel_format
;
6624 crtc
->base
.primary
->fb
= kzalloc(sizeof(struct intel_framebuffer
), GFP_KERNEL
);
6625 if (!crtc
->base
.primary
->fb
) {
6626 DRM_DEBUG_KMS("failed to alloc fb\n");
6630 val
= I915_READ(DSPCNTR(plane
));
6632 if (INTEL_INFO(dev
)->gen
>= 4)
6633 if (val
& DISPPLANE_TILED
)
6634 plane_config
->tiled
= true;
6636 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
6637 fourcc
= intel_format_to_fourcc(pixel_format
);
6638 crtc
->base
.primary
->fb
->pixel_format
= fourcc
;
6639 crtc
->base
.primary
->fb
->bits_per_pixel
=
6640 drm_format_plane_cpp(fourcc
, 0) * 8;
6642 if (INTEL_INFO(dev
)->gen
>= 4) {
6643 if (plane_config
->tiled
)
6644 offset
= I915_READ(DSPTILEOFF(plane
));
6646 offset
= I915_READ(DSPLINOFF(plane
));
6647 base
= I915_READ(DSPSURF(plane
)) & 0xfffff000;
6649 base
= I915_READ(DSPADDR(plane
));
6651 plane_config
->base
= base
;
6653 val
= I915_READ(PIPESRC(pipe
));
6654 crtc
->base
.primary
->fb
->width
= ((val
>> 16) & 0xfff) + 1;
6655 crtc
->base
.primary
->fb
->height
= ((val
>> 0) & 0xfff) + 1;
6657 val
= I915_READ(DSPSTRIDE(pipe
));
6658 crtc
->base
.primary
->fb
->pitches
[0] = val
& 0xffffffc0;
6660 aligned_height
= intel_align_height(dev
, crtc
->base
.primary
->fb
->height
,
6661 plane_config
->tiled
);
6663 plane_config
->size
= PAGE_ALIGN(crtc
->base
.primary
->fb
->pitches
[0] *
6666 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6667 pipe
, plane
, crtc
->base
.primary
->fb
->width
,
6668 crtc
->base
.primary
->fb
->height
,
6669 crtc
->base
.primary
->fb
->bits_per_pixel
, base
,
6670 crtc
->base
.primary
->fb
->pitches
[0],
6671 plane_config
->size
);
6675 static void chv_crtc_clock_get(struct intel_crtc
*crtc
,
6676 struct intel_crtc_config
*pipe_config
)
6678 struct drm_device
*dev
= crtc
->base
.dev
;
6679 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6680 int pipe
= pipe_config
->cpu_transcoder
;
6681 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
6682 intel_clock_t clock
;
6683 u32 cmn_dw13
, pll_dw0
, pll_dw1
, pll_dw2
;
6684 int refclk
= 100000;
6686 mutex_lock(&dev_priv
->dpio_lock
);
6687 cmn_dw13
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW13(port
));
6688 pll_dw0
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW0(port
));
6689 pll_dw1
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW1(port
));
6690 pll_dw2
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW2(port
));
6691 mutex_unlock(&dev_priv
->dpio_lock
);
6693 clock
.m1
= (pll_dw1
& 0x7) == DPIO_CHV_M1_DIV_BY_2
? 2 : 0;
6694 clock
.m2
= ((pll_dw0
& 0xff) << 22) | (pll_dw2
& 0x3fffff);
6695 clock
.n
= (pll_dw1
>> DPIO_CHV_N_DIV_SHIFT
) & 0xf;
6696 clock
.p1
= (cmn_dw13
>> DPIO_CHV_P1_DIV_SHIFT
) & 0x7;
6697 clock
.p2
= (cmn_dw13
>> DPIO_CHV_P2_DIV_SHIFT
) & 0x1f;
6699 chv_clock(refclk
, &clock
);
6701 /* clock.dot is the fast clock */
6702 pipe_config
->port_clock
= clock
.dot
/ 5;
6705 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
6706 struct intel_crtc_config
*pipe_config
)
6708 struct drm_device
*dev
= crtc
->base
.dev
;
6709 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6712 if (!intel_display_power_is_enabled(dev_priv
,
6713 POWER_DOMAIN_PIPE(crtc
->pipe
)))
6716 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
6717 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
6719 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
6720 if (!(tmp
& PIPECONF_ENABLE
))
6723 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
6724 switch (tmp
& PIPECONF_BPC_MASK
) {
6726 pipe_config
->pipe_bpp
= 18;
6729 pipe_config
->pipe_bpp
= 24;
6731 case PIPECONF_10BPC
:
6732 pipe_config
->pipe_bpp
= 30;
6739 if (IS_VALLEYVIEW(dev
) && (tmp
& PIPECONF_COLOR_RANGE_SELECT
))
6740 pipe_config
->limited_color_range
= true;
6742 if (INTEL_INFO(dev
)->gen
< 4)
6743 pipe_config
->double_wide
= tmp
& PIPECONF_DOUBLE_WIDE
;
6745 intel_get_pipe_timings(crtc
, pipe_config
);
6747 i9xx_get_pfit_config(crtc
, pipe_config
);
6749 if (INTEL_INFO(dev
)->gen
>= 4) {
6750 tmp
= I915_READ(DPLL_MD(crtc
->pipe
));
6751 pipe_config
->pixel_multiplier
=
6752 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
6753 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
6754 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
6755 } else if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
6756 tmp
= I915_READ(DPLL(crtc
->pipe
));
6757 pipe_config
->pixel_multiplier
=
6758 ((tmp
& SDVO_MULTIPLIER_MASK
)
6759 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
6761 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6762 * port and will be fixed up in the encoder->get_config
6764 pipe_config
->pixel_multiplier
= 1;
6766 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(crtc
->pipe
));
6767 if (!IS_VALLEYVIEW(dev
)) {
6769 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6770 * on 830. Filter it out here so that we don't
6771 * report errors due to that.
6774 pipe_config
->dpll_hw_state
.dpll
&= ~DPLL_DVO_2X_MODE
;
6776 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(crtc
->pipe
));
6777 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(crtc
->pipe
));
6779 /* Mask out read-only status bits. */
6780 pipe_config
->dpll_hw_state
.dpll
&= ~(DPLL_LOCK_VLV
|
6781 DPLL_PORTC_READY_MASK
|
6782 DPLL_PORTB_READY_MASK
);
6785 if (IS_CHERRYVIEW(dev
))
6786 chv_crtc_clock_get(crtc
, pipe_config
);
6787 else if (IS_VALLEYVIEW(dev
))
6788 vlv_crtc_clock_get(crtc
, pipe_config
);
6790 i9xx_crtc_clock_get(crtc
, pipe_config
);
6795 static void ironlake_init_pch_refclk(struct drm_device
*dev
)
6797 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6798 struct intel_encoder
*encoder
;
6800 bool has_lvds
= false;
6801 bool has_cpu_edp
= false;
6802 bool has_panel
= false;
6803 bool has_ck505
= false;
6804 bool can_ssc
= false;
6806 /* We need to take the global config into account */
6807 for_each_intel_encoder(dev
, encoder
) {
6808 switch (encoder
->type
) {
6809 case INTEL_OUTPUT_LVDS
:
6813 case INTEL_OUTPUT_EDP
:
6815 if (enc_to_dig_port(&encoder
->base
)->port
== PORT_A
)
6823 if (HAS_PCH_IBX(dev
)) {
6824 has_ck505
= dev_priv
->vbt
.display_clock_mode
;
6825 can_ssc
= has_ck505
;
6831 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6832 has_panel
, has_lvds
, has_ck505
);
6834 /* Ironlake: try to setup display ref clock before DPLL
6835 * enabling. This is only under driver's control after
6836 * PCH B stepping, previous chipset stepping should be
6837 * ignoring this setting.
6839 val
= I915_READ(PCH_DREF_CONTROL
);
6841 /* As we must carefully and slowly disable/enable each source in turn,
6842 * compute the final state we want first and check if we need to
6843 * make any changes at all.
6846 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
6848 final
|= DREF_NONSPREAD_CK505_ENABLE
;
6850 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
6852 final
&= ~DREF_SSC_SOURCE_MASK
;
6853 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
6854 final
&= ~DREF_SSC1_ENABLE
;
6857 final
|= DREF_SSC_SOURCE_ENABLE
;
6859 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
6860 final
|= DREF_SSC1_ENABLE
;
6863 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
6864 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
6866 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
6868 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6870 final
|= DREF_SSC_SOURCE_DISABLE
;
6871 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6877 /* Always enable nonspread source */
6878 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
6881 val
|= DREF_NONSPREAD_CK505_ENABLE
;
6883 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
6886 val
&= ~DREF_SSC_SOURCE_MASK
;
6887 val
|= DREF_SSC_SOURCE_ENABLE
;
6889 /* SSC must be turned on before enabling the CPU output */
6890 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
6891 DRM_DEBUG_KMS("Using SSC on panel\n");
6892 val
|= DREF_SSC1_ENABLE
;
6894 val
&= ~DREF_SSC1_ENABLE
;
6896 /* Get SSC going before enabling the outputs */
6897 I915_WRITE(PCH_DREF_CONTROL
, val
);
6898 POSTING_READ(PCH_DREF_CONTROL
);
6901 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
6903 /* Enable CPU source on CPU attached eDP */
6905 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
6906 DRM_DEBUG_KMS("Using SSC on eDP\n");
6907 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
6909 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
6911 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6913 I915_WRITE(PCH_DREF_CONTROL
, val
);
6914 POSTING_READ(PCH_DREF_CONTROL
);
6917 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6919 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
6921 /* Turn off CPU output */
6922 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6924 I915_WRITE(PCH_DREF_CONTROL
, val
);
6925 POSTING_READ(PCH_DREF_CONTROL
);
6928 /* Turn off the SSC source */
6929 val
&= ~DREF_SSC_SOURCE_MASK
;
6930 val
|= DREF_SSC_SOURCE_DISABLE
;
6933 val
&= ~DREF_SSC1_ENABLE
;
6935 I915_WRITE(PCH_DREF_CONTROL
, val
);
6936 POSTING_READ(PCH_DREF_CONTROL
);
6940 BUG_ON(val
!= final
);
6943 static void lpt_reset_fdi_mphy(struct drm_i915_private
*dev_priv
)
6947 tmp
= I915_READ(SOUTH_CHICKEN2
);
6948 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
6949 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
6951 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2
) &
6952 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
6953 DRM_ERROR("FDI mPHY reset assert timeout\n");
6955 tmp
= I915_READ(SOUTH_CHICKEN2
);
6956 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
6957 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
6959 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2
) &
6960 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0, 100))
6961 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6964 /* WaMPhyProgramming:hsw */
6965 static void lpt_program_fdi_mphy(struct drm_i915_private
*dev_priv
)
6969 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
6970 tmp
&= ~(0xFF << 24);
6971 tmp
|= (0x12 << 24);
6972 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
6974 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
6976 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
6978 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
6980 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
6982 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
6983 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
6984 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
6986 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
6987 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
6988 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
6990 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
6993 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
6995 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
6998 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
7000 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
7003 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
7005 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
7008 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
7010 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
7011 tmp
&= ~(0xFF << 16);
7012 tmp
|= (0x1C << 16);
7013 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
7015 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
7016 tmp
&= ~(0xFF << 16);
7017 tmp
|= (0x1C << 16);
7018 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
7020 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
7022 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
7024 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
7026 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
7028 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
7029 tmp
&= ~(0xF << 28);
7031 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
7033 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
7034 tmp
&= ~(0xF << 28);
7036 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
7039 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7040 * Programming" based on the parameters passed:
7041 * - Sequence to enable CLKOUT_DP
7042 * - Sequence to enable CLKOUT_DP without spread
7043 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7045 static void lpt_enable_clkout_dp(struct drm_device
*dev
, bool with_spread
,
7048 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7051 if (WARN(with_fdi
&& !with_spread
, "FDI requires downspread\n"))
7053 if (WARN(dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
&&
7054 with_fdi
, "LP PCH doesn't have FDI\n"))
7057 mutex_lock(&dev_priv
->dpio_lock
);
7059 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
7060 tmp
&= ~SBI_SSCCTL_DISABLE
;
7061 tmp
|= SBI_SSCCTL_PATHALT
;
7062 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
7067 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
7068 tmp
&= ~SBI_SSCCTL_PATHALT
;
7069 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
7072 lpt_reset_fdi_mphy(dev_priv
);
7073 lpt_program_fdi_mphy(dev_priv
);
7077 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
7078 SBI_GEN0
: SBI_DBUFF0
;
7079 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
7080 tmp
|= SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
7081 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
7083 mutex_unlock(&dev_priv
->dpio_lock
);
7086 /* Sequence to disable CLKOUT_DP */
7087 static void lpt_disable_clkout_dp(struct drm_device
*dev
)
7089 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7092 mutex_lock(&dev_priv
->dpio_lock
);
7094 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
7095 SBI_GEN0
: SBI_DBUFF0
;
7096 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
7097 tmp
&= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
7098 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
7100 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
7101 if (!(tmp
& SBI_SSCCTL_DISABLE
)) {
7102 if (!(tmp
& SBI_SSCCTL_PATHALT
)) {
7103 tmp
|= SBI_SSCCTL_PATHALT
;
7104 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
7107 tmp
|= SBI_SSCCTL_DISABLE
;
7108 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
7111 mutex_unlock(&dev_priv
->dpio_lock
);
7114 static void lpt_init_pch_refclk(struct drm_device
*dev
)
7116 struct intel_encoder
*encoder
;
7117 bool has_vga
= false;
7119 for_each_intel_encoder(dev
, encoder
) {
7120 switch (encoder
->type
) {
7121 case INTEL_OUTPUT_ANALOG
:
7130 lpt_enable_clkout_dp(dev
, true, true);
7132 lpt_disable_clkout_dp(dev
);
7136 * Initialize reference clocks when the driver loads
7138 void intel_init_pch_refclk(struct drm_device
*dev
)
7140 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
7141 ironlake_init_pch_refclk(dev
);
7142 else if (HAS_PCH_LPT(dev
))
7143 lpt_init_pch_refclk(dev
);
7146 static int ironlake_get_refclk(struct drm_crtc
*crtc
)
7148 struct drm_device
*dev
= crtc
->dev
;
7149 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7150 struct intel_encoder
*encoder
;
7151 int num_connectors
= 0;
7152 bool is_lvds
= false;
7154 for_each_intel_encoder(dev
, encoder
) {
7155 if (encoder
->new_crtc
!= to_intel_crtc(crtc
))
7158 switch (encoder
->type
) {
7159 case INTEL_OUTPUT_LVDS
:
7168 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
7169 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7170 dev_priv
->vbt
.lvds_ssc_freq
);
7171 return dev_priv
->vbt
.lvds_ssc_freq
;
7177 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
)
7179 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
7180 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7181 int pipe
= intel_crtc
->pipe
;
7186 switch (intel_crtc
->config
.pipe_bpp
) {
7188 val
|= PIPECONF_6BPC
;
7191 val
|= PIPECONF_8BPC
;
7194 val
|= PIPECONF_10BPC
;
7197 val
|= PIPECONF_12BPC
;
7200 /* Case prevented by intel_choose_pipe_bpp_dither. */
7204 if (intel_crtc
->config
.dither
)
7205 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
7207 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
7208 val
|= PIPECONF_INTERLACED_ILK
;
7210 val
|= PIPECONF_PROGRESSIVE
;
7212 if (intel_crtc
->config
.limited_color_range
)
7213 val
|= PIPECONF_COLOR_RANGE_SELECT
;
7215 I915_WRITE(PIPECONF(pipe
), val
);
7216 POSTING_READ(PIPECONF(pipe
));
7220 * Set up the pipe CSC unit.
7222 * Currently only full range RGB to limited range RGB conversion
7223 * is supported, but eventually this should handle various
7224 * RGB<->YCbCr scenarios as well.
7226 static void intel_set_pipe_csc(struct drm_crtc
*crtc
)
7228 struct drm_device
*dev
= crtc
->dev
;
7229 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7230 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7231 int pipe
= intel_crtc
->pipe
;
7232 uint16_t coeff
= 0x7800; /* 1.0 */
7235 * TODO: Check what kind of values actually come out of the pipe
7236 * with these coeff/postoff values and adjust to get the best
7237 * accuracy. Perhaps we even need to take the bpc value into
7241 if (intel_crtc
->config
.limited_color_range
)
7242 coeff
= ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7245 * GY/GU and RY/RU should be the other way around according
7246 * to BSpec, but reality doesn't agree. Just set them up in
7247 * a way that results in the correct picture.
7249 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe
), coeff
<< 16);
7250 I915_WRITE(PIPE_CSC_COEFF_BY(pipe
), 0);
7252 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe
), coeff
);
7253 I915_WRITE(PIPE_CSC_COEFF_BU(pipe
), 0);
7255 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe
), 0);
7256 I915_WRITE(PIPE_CSC_COEFF_BV(pipe
), coeff
<< 16);
7258 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe
), 0);
7259 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe
), 0);
7260 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe
), 0);
7262 if (INTEL_INFO(dev
)->gen
> 6) {
7263 uint16_t postoff
= 0;
7265 if (intel_crtc
->config
.limited_color_range
)
7266 postoff
= (16 * (1 << 12) / 255) & 0x1fff;
7268 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe
), postoff
);
7269 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe
), postoff
);
7270 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe
), postoff
);
7272 I915_WRITE(PIPE_CSC_MODE(pipe
), 0);
7274 uint32_t mode
= CSC_MODE_YUV_TO_RGB
;
7276 if (intel_crtc
->config
.limited_color_range
)
7277 mode
|= CSC_BLACK_SCREEN_OFFSET
;
7279 I915_WRITE(PIPE_CSC_MODE(pipe
), mode
);
7283 static void haswell_set_pipeconf(struct drm_crtc
*crtc
)
7285 struct drm_device
*dev
= crtc
->dev
;
7286 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7287 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7288 enum pipe pipe
= intel_crtc
->pipe
;
7289 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
7294 if (IS_HASWELL(dev
) && intel_crtc
->config
.dither
)
7295 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
7297 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
7298 val
|= PIPECONF_INTERLACED_ILK
;
7300 val
|= PIPECONF_PROGRESSIVE
;
7302 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
7303 POSTING_READ(PIPECONF(cpu_transcoder
));
7305 I915_WRITE(GAMMA_MODE(intel_crtc
->pipe
), GAMMA_MODE_MODE_8BIT
);
7306 POSTING_READ(GAMMA_MODE(intel_crtc
->pipe
));
7308 if (IS_BROADWELL(dev
) || INTEL_INFO(dev
)->gen
>= 9) {
7311 switch (intel_crtc
->config
.pipe_bpp
) {
7313 val
|= PIPEMISC_DITHER_6_BPC
;
7316 val
|= PIPEMISC_DITHER_8_BPC
;
7319 val
|= PIPEMISC_DITHER_10_BPC
;
7322 val
|= PIPEMISC_DITHER_12_BPC
;
7325 /* Case prevented by pipe_config_set_bpp. */
7329 if (intel_crtc
->config
.dither
)
7330 val
|= PIPEMISC_DITHER_ENABLE
| PIPEMISC_DITHER_TYPE_SP
;
7332 I915_WRITE(PIPEMISC(pipe
), val
);
7336 static bool ironlake_compute_clocks(struct drm_crtc
*crtc
,
7337 intel_clock_t
*clock
,
7338 bool *has_reduced_clock
,
7339 intel_clock_t
*reduced_clock
)
7341 struct drm_device
*dev
= crtc
->dev
;
7342 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7343 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7345 const intel_limit_t
*limit
;
7346 bool ret
, is_lvds
= false;
7348 is_lvds
= intel_pipe_will_have_type(intel_crtc
, INTEL_OUTPUT_LVDS
);
7350 refclk
= ironlake_get_refclk(crtc
);
7353 * Returns a set of divisors for the desired target clock with the given
7354 * refclk, or FALSE. The returned values represent the clock equation:
7355 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7357 limit
= intel_limit(intel_crtc
, refclk
);
7358 ret
= dev_priv
->display
.find_dpll(limit
, intel_crtc
,
7359 intel_crtc
->new_config
->port_clock
,
7360 refclk
, NULL
, clock
);
7364 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
7366 * Ensure we match the reduced clock's P to the target clock.
7367 * If the clocks don't match, we can't switch the display clock
7368 * by using the FP0/FP1. In such case we will disable the LVDS
7369 * downclock feature.
7371 *has_reduced_clock
=
7372 dev_priv
->display
.find_dpll(limit
, intel_crtc
,
7373 dev_priv
->lvds_downclock
,
7381 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
7384 * Account for spread spectrum to avoid
7385 * oversubscribing the link. Max center spread
7386 * is 2.5%; use 5% for safety's sake.
7388 u32 bps
= target_clock
* bpp
* 21 / 20;
7389 return DIV_ROUND_UP(bps
, link_bw
* 8);
7392 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
7394 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
7397 static uint32_t ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
7399 intel_clock_t
*reduced_clock
, u32
*fp2
)
7401 struct drm_crtc
*crtc
= &intel_crtc
->base
;
7402 struct drm_device
*dev
= crtc
->dev
;
7403 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7404 struct intel_encoder
*intel_encoder
;
7406 int factor
, num_connectors
= 0;
7407 bool is_lvds
= false, is_sdvo
= false;
7409 for_each_intel_encoder(dev
, intel_encoder
) {
7410 if (intel_encoder
->new_crtc
!= to_intel_crtc(crtc
))
7413 switch (intel_encoder
->type
) {
7414 case INTEL_OUTPUT_LVDS
:
7417 case INTEL_OUTPUT_SDVO
:
7418 case INTEL_OUTPUT_HDMI
:
7428 /* Enable autotuning of the PLL clock (if permissible) */
7431 if ((intel_panel_use_ssc(dev_priv
) &&
7432 dev_priv
->vbt
.lvds_ssc_freq
== 100000) ||
7433 (HAS_PCH_IBX(dev
) && intel_is_dual_link_lvds(dev
)))
7435 } else if (intel_crtc
->new_config
->sdvo_tv_clock
)
7438 if (ironlake_needs_fb_cb_tune(&intel_crtc
->new_config
->dpll
, factor
))
7441 if (fp2
&& (reduced_clock
->m
< factor
* reduced_clock
->n
))
7447 dpll
|= DPLLB_MODE_LVDS
;
7449 dpll
|= DPLLB_MODE_DAC_SERIAL
;
7451 dpll
|= (intel_crtc
->new_config
->pixel_multiplier
- 1)
7452 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
7455 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7456 if (intel_crtc
->new_config
->has_dp_encoder
)
7457 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7459 /* compute bitmask from p1 value */
7460 dpll
|= (1 << (intel_crtc
->new_config
->dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7462 dpll
|= (1 << (intel_crtc
->new_config
->dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
7464 switch (intel_crtc
->new_config
->dpll
.p2
) {
7466 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
7469 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
7472 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
7475 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
7479 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
7480 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
7482 dpll
|= PLL_REF_INPUT_DREFCLK
;
7484 return dpll
| DPLL_VCO_ENABLE
;
7487 static int ironlake_crtc_compute_clock(struct intel_crtc
*crtc
)
7489 struct drm_device
*dev
= crtc
->base
.dev
;
7490 intel_clock_t clock
, reduced_clock
;
7491 u32 dpll
= 0, fp
= 0, fp2
= 0;
7492 bool ok
, has_reduced_clock
= false;
7493 bool is_lvds
= false;
7494 struct intel_shared_dpll
*pll
;
7496 is_lvds
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
);
7498 WARN(!(HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)),
7499 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev
));
7501 ok
= ironlake_compute_clocks(&crtc
->base
, &clock
,
7502 &has_reduced_clock
, &reduced_clock
);
7503 if (!ok
&& !crtc
->new_config
->clock_set
) {
7504 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7507 /* Compat-code for transition, will disappear. */
7508 if (!crtc
->new_config
->clock_set
) {
7509 crtc
->new_config
->dpll
.n
= clock
.n
;
7510 crtc
->new_config
->dpll
.m1
= clock
.m1
;
7511 crtc
->new_config
->dpll
.m2
= clock
.m2
;
7512 crtc
->new_config
->dpll
.p1
= clock
.p1
;
7513 crtc
->new_config
->dpll
.p2
= clock
.p2
;
7516 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7517 if (crtc
->new_config
->has_pch_encoder
) {
7518 fp
= i9xx_dpll_compute_fp(&crtc
->new_config
->dpll
);
7519 if (has_reduced_clock
)
7520 fp2
= i9xx_dpll_compute_fp(&reduced_clock
);
7522 dpll
= ironlake_compute_dpll(crtc
,
7523 &fp
, &reduced_clock
,
7524 has_reduced_clock
? &fp2
: NULL
);
7526 crtc
->new_config
->dpll_hw_state
.dpll
= dpll
;
7527 crtc
->new_config
->dpll_hw_state
.fp0
= fp
;
7528 if (has_reduced_clock
)
7529 crtc
->new_config
->dpll_hw_state
.fp1
= fp2
;
7531 crtc
->new_config
->dpll_hw_state
.fp1
= fp
;
7533 pll
= intel_get_shared_dpll(crtc
);
7535 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7536 pipe_name(crtc
->pipe
));
7541 if (is_lvds
&& has_reduced_clock
&& i915
.powersave
)
7542 crtc
->lowfreq_avail
= true;
7544 crtc
->lowfreq_avail
= false;
7549 static void intel_pch_transcoder_get_m_n(struct intel_crtc
*crtc
,
7550 struct intel_link_m_n
*m_n
)
7552 struct drm_device
*dev
= crtc
->base
.dev
;
7553 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7554 enum pipe pipe
= crtc
->pipe
;
7556 m_n
->link_m
= I915_READ(PCH_TRANS_LINK_M1(pipe
));
7557 m_n
->link_n
= I915_READ(PCH_TRANS_LINK_N1(pipe
));
7558 m_n
->gmch_m
= I915_READ(PCH_TRANS_DATA_M1(pipe
))
7560 m_n
->gmch_n
= I915_READ(PCH_TRANS_DATA_N1(pipe
));
7561 m_n
->tu
= ((I915_READ(PCH_TRANS_DATA_M1(pipe
))
7562 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7565 static void intel_cpu_transcoder_get_m_n(struct intel_crtc
*crtc
,
7566 enum transcoder transcoder
,
7567 struct intel_link_m_n
*m_n
,
7568 struct intel_link_m_n
*m2_n2
)
7570 struct drm_device
*dev
= crtc
->base
.dev
;
7571 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7572 enum pipe pipe
= crtc
->pipe
;
7574 if (INTEL_INFO(dev
)->gen
>= 5) {
7575 m_n
->link_m
= I915_READ(PIPE_LINK_M1(transcoder
));
7576 m_n
->link_n
= I915_READ(PIPE_LINK_N1(transcoder
));
7577 m_n
->gmch_m
= I915_READ(PIPE_DATA_M1(transcoder
))
7579 m_n
->gmch_n
= I915_READ(PIPE_DATA_N1(transcoder
));
7580 m_n
->tu
= ((I915_READ(PIPE_DATA_M1(transcoder
))
7581 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7582 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7583 * gen < 8) and if DRRS is supported (to make sure the
7584 * registers are not unnecessarily read).
7586 if (m2_n2
&& INTEL_INFO(dev
)->gen
< 8 &&
7587 crtc
->config
.has_drrs
) {
7588 m2_n2
->link_m
= I915_READ(PIPE_LINK_M2(transcoder
));
7589 m2_n2
->link_n
= I915_READ(PIPE_LINK_N2(transcoder
));
7590 m2_n2
->gmch_m
= I915_READ(PIPE_DATA_M2(transcoder
))
7592 m2_n2
->gmch_n
= I915_READ(PIPE_DATA_N2(transcoder
));
7593 m2_n2
->tu
= ((I915_READ(PIPE_DATA_M2(transcoder
))
7594 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7597 m_n
->link_m
= I915_READ(PIPE_LINK_M_G4X(pipe
));
7598 m_n
->link_n
= I915_READ(PIPE_LINK_N_G4X(pipe
));
7599 m_n
->gmch_m
= I915_READ(PIPE_DATA_M_G4X(pipe
))
7601 m_n
->gmch_n
= I915_READ(PIPE_DATA_N_G4X(pipe
));
7602 m_n
->tu
= ((I915_READ(PIPE_DATA_M_G4X(pipe
))
7603 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7607 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
7608 struct intel_crtc_config
*pipe_config
)
7610 if (crtc
->config
.has_pch_encoder
)
7611 intel_pch_transcoder_get_m_n(crtc
, &pipe_config
->dp_m_n
);
7613 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
7614 &pipe_config
->dp_m_n
,
7615 &pipe_config
->dp_m2_n2
);
7618 static void ironlake_get_fdi_m_n_config(struct intel_crtc
*crtc
,
7619 struct intel_crtc_config
*pipe_config
)
7621 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
7622 &pipe_config
->fdi_m_n
, NULL
);
7625 static void skylake_get_pfit_config(struct intel_crtc
*crtc
,
7626 struct intel_crtc_config
*pipe_config
)
7628 struct drm_device
*dev
= crtc
->base
.dev
;
7629 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7632 tmp
= I915_READ(PS_CTL(crtc
->pipe
));
7634 if (tmp
& PS_ENABLE
) {
7635 pipe_config
->pch_pfit
.enabled
= true;
7636 pipe_config
->pch_pfit
.pos
= I915_READ(PS_WIN_POS(crtc
->pipe
));
7637 pipe_config
->pch_pfit
.size
= I915_READ(PS_WIN_SZ(crtc
->pipe
));
7641 static void ironlake_get_pfit_config(struct intel_crtc
*crtc
,
7642 struct intel_crtc_config
*pipe_config
)
7644 struct drm_device
*dev
= crtc
->base
.dev
;
7645 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7648 tmp
= I915_READ(PF_CTL(crtc
->pipe
));
7650 if (tmp
& PF_ENABLE
) {
7651 pipe_config
->pch_pfit
.enabled
= true;
7652 pipe_config
->pch_pfit
.pos
= I915_READ(PF_WIN_POS(crtc
->pipe
));
7653 pipe_config
->pch_pfit
.size
= I915_READ(PF_WIN_SZ(crtc
->pipe
));
7655 /* We currently do not free assignements of panel fitters on
7656 * ivb/hsw (since we don't use the higher upscaling modes which
7657 * differentiates them) so just WARN about this case for now. */
7659 WARN_ON((tmp
& PF_PIPE_SEL_MASK_IVB
) !=
7660 PF_PIPE_SEL_IVB(crtc
->pipe
));
7665 static void ironlake_get_plane_config(struct intel_crtc
*crtc
,
7666 struct intel_plane_config
*plane_config
)
7668 struct drm_device
*dev
= crtc
->base
.dev
;
7669 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7670 u32 val
, base
, offset
;
7671 int pipe
= crtc
->pipe
, plane
= crtc
->plane
;
7672 int fourcc
, pixel_format
;
7675 crtc
->base
.primary
->fb
= kzalloc(sizeof(struct intel_framebuffer
), GFP_KERNEL
);
7676 if (!crtc
->base
.primary
->fb
) {
7677 DRM_DEBUG_KMS("failed to alloc fb\n");
7681 val
= I915_READ(DSPCNTR(plane
));
7683 if (INTEL_INFO(dev
)->gen
>= 4)
7684 if (val
& DISPPLANE_TILED
)
7685 plane_config
->tiled
= true;
7687 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
7688 fourcc
= intel_format_to_fourcc(pixel_format
);
7689 crtc
->base
.primary
->fb
->pixel_format
= fourcc
;
7690 crtc
->base
.primary
->fb
->bits_per_pixel
=
7691 drm_format_plane_cpp(fourcc
, 0) * 8;
7693 base
= I915_READ(DSPSURF(plane
)) & 0xfffff000;
7694 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
7695 offset
= I915_READ(DSPOFFSET(plane
));
7697 if (plane_config
->tiled
)
7698 offset
= I915_READ(DSPTILEOFF(plane
));
7700 offset
= I915_READ(DSPLINOFF(plane
));
7702 plane_config
->base
= base
;
7704 val
= I915_READ(PIPESRC(pipe
));
7705 crtc
->base
.primary
->fb
->width
= ((val
>> 16) & 0xfff) + 1;
7706 crtc
->base
.primary
->fb
->height
= ((val
>> 0) & 0xfff) + 1;
7708 val
= I915_READ(DSPSTRIDE(pipe
));
7709 crtc
->base
.primary
->fb
->pitches
[0] = val
& 0xffffffc0;
7711 aligned_height
= intel_align_height(dev
, crtc
->base
.primary
->fb
->height
,
7712 plane_config
->tiled
);
7714 plane_config
->size
= PAGE_ALIGN(crtc
->base
.primary
->fb
->pitches
[0] *
7717 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7718 pipe
, plane
, crtc
->base
.primary
->fb
->width
,
7719 crtc
->base
.primary
->fb
->height
,
7720 crtc
->base
.primary
->fb
->bits_per_pixel
, base
,
7721 crtc
->base
.primary
->fb
->pitches
[0],
7722 plane_config
->size
);
7725 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
7726 struct intel_crtc_config
*pipe_config
)
7728 struct drm_device
*dev
= crtc
->base
.dev
;
7729 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7732 if (!intel_display_power_is_enabled(dev_priv
,
7733 POWER_DOMAIN_PIPE(crtc
->pipe
)))
7736 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
7737 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
7739 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
7740 if (!(tmp
& PIPECONF_ENABLE
))
7743 switch (tmp
& PIPECONF_BPC_MASK
) {
7745 pipe_config
->pipe_bpp
= 18;
7748 pipe_config
->pipe_bpp
= 24;
7750 case PIPECONF_10BPC
:
7751 pipe_config
->pipe_bpp
= 30;
7753 case PIPECONF_12BPC
:
7754 pipe_config
->pipe_bpp
= 36;
7760 if (tmp
& PIPECONF_COLOR_RANGE_SELECT
)
7761 pipe_config
->limited_color_range
= true;
7763 if (I915_READ(PCH_TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
) {
7764 struct intel_shared_dpll
*pll
;
7766 pipe_config
->has_pch_encoder
= true;
7768 tmp
= I915_READ(FDI_RX_CTL(crtc
->pipe
));
7769 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
7770 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
7772 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
7774 if (HAS_PCH_IBX(dev_priv
->dev
)) {
7775 pipe_config
->shared_dpll
=
7776 (enum intel_dpll_id
) crtc
->pipe
;
7778 tmp
= I915_READ(PCH_DPLL_SEL
);
7779 if (tmp
& TRANS_DPLLB_SEL(crtc
->pipe
))
7780 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_B
;
7782 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_A
;
7785 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
7787 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
7788 &pipe_config
->dpll_hw_state
));
7790 tmp
= pipe_config
->dpll_hw_state
.dpll
;
7791 pipe_config
->pixel_multiplier
=
7792 ((tmp
& PLL_REF_SDVO_HDMI_MULTIPLIER_MASK
)
7793 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
) + 1;
7795 ironlake_pch_clock_get(crtc
, pipe_config
);
7797 pipe_config
->pixel_multiplier
= 1;
7800 intel_get_pipe_timings(crtc
, pipe_config
);
7802 ironlake_get_pfit_config(crtc
, pipe_config
);
7807 static void assert_can_disable_lcpll(struct drm_i915_private
*dev_priv
)
7809 struct drm_device
*dev
= dev_priv
->dev
;
7810 struct intel_crtc
*crtc
;
7812 for_each_intel_crtc(dev
, crtc
)
7813 WARN(crtc
->active
, "CRTC for pipe %c enabled\n",
7814 pipe_name(crtc
->pipe
));
7816 WARN(I915_READ(HSW_PWR_WELL_DRIVER
), "Power well on\n");
7817 WARN(I915_READ(SPLL_CTL
) & SPLL_PLL_ENABLE
, "SPLL enabled\n");
7818 WARN(I915_READ(WRPLL_CTL1
) & WRPLL_PLL_ENABLE
, "WRPLL1 enabled\n");
7819 WARN(I915_READ(WRPLL_CTL2
) & WRPLL_PLL_ENABLE
, "WRPLL2 enabled\n");
7820 WARN(I915_READ(PCH_PP_STATUS
) & PP_ON
, "Panel power on\n");
7821 WARN(I915_READ(BLC_PWM_CPU_CTL2
) & BLM_PWM_ENABLE
,
7822 "CPU PWM1 enabled\n");
7823 if (IS_HASWELL(dev
))
7824 WARN(I915_READ(HSW_BLC_PWM2_CTL
) & BLM_PWM_ENABLE
,
7825 "CPU PWM2 enabled\n");
7826 WARN(I915_READ(BLC_PWM_PCH_CTL1
) & BLM_PCH_PWM_ENABLE
,
7827 "PCH PWM1 enabled\n");
7828 WARN(I915_READ(UTIL_PIN_CTL
) & UTIL_PIN_ENABLE
,
7829 "Utility pin enabled\n");
7830 WARN(I915_READ(PCH_GTC_CTL
) & PCH_GTC_ENABLE
, "PCH GTC enabled\n");
7833 * In theory we can still leave IRQs enabled, as long as only the HPD
7834 * interrupts remain enabled. We used to check for that, but since it's
7835 * gen-specific and since we only disable LCPLL after we fully disable
7836 * the interrupts, the check below should be enough.
7838 WARN(intel_irqs_enabled(dev_priv
), "IRQs enabled\n");
7841 static uint32_t hsw_read_dcomp(struct drm_i915_private
*dev_priv
)
7843 struct drm_device
*dev
= dev_priv
->dev
;
7845 if (IS_HASWELL(dev
))
7846 return I915_READ(D_COMP_HSW
);
7848 return I915_READ(D_COMP_BDW
);
7851 static void hsw_write_dcomp(struct drm_i915_private
*dev_priv
, uint32_t val
)
7853 struct drm_device
*dev
= dev_priv
->dev
;
7855 if (IS_HASWELL(dev
)) {
7856 mutex_lock(&dev_priv
->rps
.hw_lock
);
7857 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
,
7859 DRM_ERROR("Failed to write to D_COMP\n");
7860 mutex_unlock(&dev_priv
->rps
.hw_lock
);
7862 I915_WRITE(D_COMP_BDW
, val
);
7863 POSTING_READ(D_COMP_BDW
);
7868 * This function implements pieces of two sequences from BSpec:
7869 * - Sequence for display software to disable LCPLL
7870 * - Sequence for display software to allow package C8+
7871 * The steps implemented here are just the steps that actually touch the LCPLL
7872 * register. Callers should take care of disabling all the display engine
7873 * functions, doing the mode unset, fixing interrupts, etc.
7875 static void hsw_disable_lcpll(struct drm_i915_private
*dev_priv
,
7876 bool switch_to_fclk
, bool allow_power_down
)
7880 assert_can_disable_lcpll(dev_priv
);
7882 val
= I915_READ(LCPLL_CTL
);
7884 if (switch_to_fclk
) {
7885 val
|= LCPLL_CD_SOURCE_FCLK
;
7886 I915_WRITE(LCPLL_CTL
, val
);
7888 if (wait_for_atomic_us(I915_READ(LCPLL_CTL
) &
7889 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
7890 DRM_ERROR("Switching to FCLK failed\n");
7892 val
= I915_READ(LCPLL_CTL
);
7895 val
|= LCPLL_PLL_DISABLE
;
7896 I915_WRITE(LCPLL_CTL
, val
);
7897 POSTING_READ(LCPLL_CTL
);
7899 if (wait_for((I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
) == 0, 1))
7900 DRM_ERROR("LCPLL still locked\n");
7902 val
= hsw_read_dcomp(dev_priv
);
7903 val
|= D_COMP_COMP_DISABLE
;
7904 hsw_write_dcomp(dev_priv
, val
);
7907 if (wait_for((hsw_read_dcomp(dev_priv
) & D_COMP_RCOMP_IN_PROGRESS
) == 0,
7909 DRM_ERROR("D_COMP RCOMP still in progress\n");
7911 if (allow_power_down
) {
7912 val
= I915_READ(LCPLL_CTL
);
7913 val
|= LCPLL_POWER_DOWN_ALLOW
;
7914 I915_WRITE(LCPLL_CTL
, val
);
7915 POSTING_READ(LCPLL_CTL
);
7920 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7923 static void hsw_restore_lcpll(struct drm_i915_private
*dev_priv
)
7927 val
= I915_READ(LCPLL_CTL
);
7929 if ((val
& (LCPLL_PLL_LOCK
| LCPLL_PLL_DISABLE
| LCPLL_CD_SOURCE_FCLK
|
7930 LCPLL_POWER_DOWN_ALLOW
)) == LCPLL_PLL_LOCK
)
7934 * Make sure we're not on PC8 state before disabling PC8, otherwise
7935 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7937 * The other problem is that hsw_restore_lcpll() is called as part of
7938 * the runtime PM resume sequence, so we can't just call
7939 * gen6_gt_force_wake_get() because that function calls
7940 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7941 * while we are on the resume sequence. So to solve this problem we have
7942 * to call special forcewake code that doesn't touch runtime PM and
7943 * doesn't enable the forcewake delayed work.
7945 spin_lock_irq(&dev_priv
->uncore
.lock
);
7946 if (dev_priv
->uncore
.forcewake_count
++ == 0)
7947 dev_priv
->uncore
.funcs
.force_wake_get(dev_priv
, FORCEWAKE_ALL
);
7948 spin_unlock_irq(&dev_priv
->uncore
.lock
);
7950 if (val
& LCPLL_POWER_DOWN_ALLOW
) {
7951 val
&= ~LCPLL_POWER_DOWN_ALLOW
;
7952 I915_WRITE(LCPLL_CTL
, val
);
7953 POSTING_READ(LCPLL_CTL
);
7956 val
= hsw_read_dcomp(dev_priv
);
7957 val
|= D_COMP_COMP_FORCE
;
7958 val
&= ~D_COMP_COMP_DISABLE
;
7959 hsw_write_dcomp(dev_priv
, val
);
7961 val
= I915_READ(LCPLL_CTL
);
7962 val
&= ~LCPLL_PLL_DISABLE
;
7963 I915_WRITE(LCPLL_CTL
, val
);
7965 if (wait_for(I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
, 5))
7966 DRM_ERROR("LCPLL not locked yet\n");
7968 if (val
& LCPLL_CD_SOURCE_FCLK
) {
7969 val
= I915_READ(LCPLL_CTL
);
7970 val
&= ~LCPLL_CD_SOURCE_FCLK
;
7971 I915_WRITE(LCPLL_CTL
, val
);
7973 if (wait_for_atomic_us((I915_READ(LCPLL_CTL
) &
7974 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
7975 DRM_ERROR("Switching back to LCPLL failed\n");
7978 /* See the big comment above. */
7979 spin_lock_irq(&dev_priv
->uncore
.lock
);
7980 if (--dev_priv
->uncore
.forcewake_count
== 0)
7981 dev_priv
->uncore
.funcs
.force_wake_put(dev_priv
, FORCEWAKE_ALL
);
7982 spin_unlock_irq(&dev_priv
->uncore
.lock
);
7986 * Package states C8 and deeper are really deep PC states that can only be
7987 * reached when all the devices on the system allow it, so even if the graphics
7988 * device allows PC8+, it doesn't mean the system will actually get to these
7989 * states. Our driver only allows PC8+ when going into runtime PM.
7991 * The requirements for PC8+ are that all the outputs are disabled, the power
7992 * well is disabled and most interrupts are disabled, and these are also
7993 * requirements for runtime PM. When these conditions are met, we manually do
7994 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7995 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7998 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7999 * the state of some registers, so when we come back from PC8+ we need to
8000 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8001 * need to take care of the registers kept by RC6. Notice that this happens even
8002 * if we don't put the device in PCI D3 state (which is what currently happens
8003 * because of the runtime PM support).
8005 * For more, read "Display Sequences for Package C8" on the hardware
8008 void hsw_enable_pc8(struct drm_i915_private
*dev_priv
)
8010 struct drm_device
*dev
= dev_priv
->dev
;
8013 DRM_DEBUG_KMS("Enabling package C8+\n");
8015 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
8016 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
8017 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
8018 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
8021 lpt_disable_clkout_dp(dev
);
8022 hsw_disable_lcpll(dev_priv
, true, true);
8025 void hsw_disable_pc8(struct drm_i915_private
*dev_priv
)
8027 struct drm_device
*dev
= dev_priv
->dev
;
8030 DRM_DEBUG_KMS("Disabling package C8+\n");
8032 hsw_restore_lcpll(dev_priv
);
8033 lpt_init_pch_refclk(dev
);
8035 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
8036 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
8037 val
|= PCH_LP_PARTITION_LEVEL_DISABLE
;
8038 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
8041 intel_prepare_ddi(dev
);
8044 static int haswell_crtc_compute_clock(struct intel_crtc
*crtc
)
8046 if (!intel_ddi_pll_select(crtc
))
8049 crtc
->lowfreq_avail
= false;
8054 static void skylake_get_ddi_pll(struct drm_i915_private
*dev_priv
,
8056 struct intel_crtc_config
*pipe_config
)
8060 temp
= I915_READ(DPLL_CTRL2
) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port
);
8061 pipe_config
->ddi_pll_sel
= temp
>> (port
* 3 + 1);
8063 switch (pipe_config
->ddi_pll_sel
) {
8065 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL1
;
8068 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL2
;
8071 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL3
;
8076 static void haswell_get_ddi_pll(struct drm_i915_private
*dev_priv
,
8078 struct intel_crtc_config
*pipe_config
)
8080 pipe_config
->ddi_pll_sel
= I915_READ(PORT_CLK_SEL(port
));
8082 switch (pipe_config
->ddi_pll_sel
) {
8083 case PORT_CLK_SEL_WRPLL1
:
8084 pipe_config
->shared_dpll
= DPLL_ID_WRPLL1
;
8086 case PORT_CLK_SEL_WRPLL2
:
8087 pipe_config
->shared_dpll
= DPLL_ID_WRPLL2
;
8092 static void haswell_get_ddi_port_state(struct intel_crtc
*crtc
,
8093 struct intel_crtc_config
*pipe_config
)
8095 struct drm_device
*dev
= crtc
->base
.dev
;
8096 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8097 struct intel_shared_dpll
*pll
;
8101 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
8103 port
= (tmp
& TRANS_DDI_PORT_MASK
) >> TRANS_DDI_PORT_SHIFT
;
8105 if (IS_SKYLAKE(dev
))
8106 skylake_get_ddi_pll(dev_priv
, port
, pipe_config
);
8108 haswell_get_ddi_pll(dev_priv
, port
, pipe_config
);
8110 if (pipe_config
->shared_dpll
>= 0) {
8111 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
8113 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
8114 &pipe_config
->dpll_hw_state
));
8118 * Haswell has only FDI/PCH transcoder A. It is which is connected to
8119 * DDI E. So just check whether this pipe is wired to DDI E and whether
8120 * the PCH transcoder is on.
8122 if (INTEL_INFO(dev
)->gen
< 9 &&
8123 (port
== PORT_E
) && I915_READ(LPT_TRANSCONF
) & TRANS_ENABLE
) {
8124 pipe_config
->has_pch_encoder
= true;
8126 tmp
= I915_READ(FDI_RX_CTL(PIPE_A
));
8127 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
8128 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
8130 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
8134 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
8135 struct intel_crtc_config
*pipe_config
)
8137 struct drm_device
*dev
= crtc
->base
.dev
;
8138 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8139 enum intel_display_power_domain pfit_domain
;
8142 if (!intel_display_power_is_enabled(dev_priv
,
8143 POWER_DOMAIN_PIPE(crtc
->pipe
)))
8146 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
8147 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
8149 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
8150 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
8151 enum pipe trans_edp_pipe
;
8152 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
8154 WARN(1, "unknown pipe linked to edp transcoder\n");
8155 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
8156 case TRANS_DDI_EDP_INPUT_A_ON
:
8157 trans_edp_pipe
= PIPE_A
;
8159 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
8160 trans_edp_pipe
= PIPE_B
;
8162 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
8163 trans_edp_pipe
= PIPE_C
;
8167 if (trans_edp_pipe
== crtc
->pipe
)
8168 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
8171 if (!intel_display_power_is_enabled(dev_priv
,
8172 POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
)))
8175 tmp
= I915_READ(PIPECONF(pipe_config
->cpu_transcoder
));
8176 if (!(tmp
& PIPECONF_ENABLE
))
8179 haswell_get_ddi_port_state(crtc
, pipe_config
);
8181 intel_get_pipe_timings(crtc
, pipe_config
);
8183 pfit_domain
= POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
);
8184 if (intel_display_power_is_enabled(dev_priv
, pfit_domain
)) {
8185 if (IS_SKYLAKE(dev
))
8186 skylake_get_pfit_config(crtc
, pipe_config
);
8188 ironlake_get_pfit_config(crtc
, pipe_config
);
8191 if (IS_HASWELL(dev
))
8192 pipe_config
->ips_enabled
= hsw_crtc_supports_ips(crtc
) &&
8193 (I915_READ(IPS_CTL
) & IPS_ENABLE
);
8195 if (pipe_config
->cpu_transcoder
!= TRANSCODER_EDP
) {
8196 pipe_config
->pixel_multiplier
=
8197 I915_READ(PIPE_MULT(pipe_config
->cpu_transcoder
)) + 1;
8199 pipe_config
->pixel_multiplier
= 1;
8205 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
8207 struct drm_device
*dev
= crtc
->dev
;
8208 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8209 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8210 uint32_t cntl
= 0, size
= 0;
8213 unsigned int width
= intel_crtc
->cursor_width
;
8214 unsigned int height
= intel_crtc
->cursor_height
;
8215 unsigned int stride
= roundup_pow_of_two(width
) * 4;
8219 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8230 cntl
|= CURSOR_ENABLE
|
8231 CURSOR_GAMMA_ENABLE
|
8232 CURSOR_FORMAT_ARGB
|
8233 CURSOR_STRIDE(stride
);
8235 size
= (height
<< 12) | width
;
8238 if (intel_crtc
->cursor_cntl
!= 0 &&
8239 (intel_crtc
->cursor_base
!= base
||
8240 intel_crtc
->cursor_size
!= size
||
8241 intel_crtc
->cursor_cntl
!= cntl
)) {
8242 /* On these chipsets we can only modify the base/size/stride
8243 * whilst the cursor is disabled.
8245 I915_WRITE(_CURACNTR
, 0);
8246 POSTING_READ(_CURACNTR
);
8247 intel_crtc
->cursor_cntl
= 0;
8250 if (intel_crtc
->cursor_base
!= base
) {
8251 I915_WRITE(_CURABASE
, base
);
8252 intel_crtc
->cursor_base
= base
;
8255 if (intel_crtc
->cursor_size
!= size
) {
8256 I915_WRITE(CURSIZE
, size
);
8257 intel_crtc
->cursor_size
= size
;
8260 if (intel_crtc
->cursor_cntl
!= cntl
) {
8261 I915_WRITE(_CURACNTR
, cntl
);
8262 POSTING_READ(_CURACNTR
);
8263 intel_crtc
->cursor_cntl
= cntl
;
8267 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
8269 struct drm_device
*dev
= crtc
->dev
;
8270 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8271 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8272 int pipe
= intel_crtc
->pipe
;
8277 cntl
= MCURSOR_GAMMA_ENABLE
;
8278 switch (intel_crtc
->cursor_width
) {
8280 cntl
|= CURSOR_MODE_64_ARGB_AX
;
8283 cntl
|= CURSOR_MODE_128_ARGB_AX
;
8286 cntl
|= CURSOR_MODE_256_ARGB_AX
;
8292 cntl
|= pipe
<< 28; /* Connect to correct pipe */
8294 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
8295 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
8298 if (to_intel_plane(crtc
->cursor
)->rotation
== BIT(DRM_ROTATE_180
))
8299 cntl
|= CURSOR_ROTATE_180
;
8301 if (intel_crtc
->cursor_cntl
!= cntl
) {
8302 I915_WRITE(CURCNTR(pipe
), cntl
);
8303 POSTING_READ(CURCNTR(pipe
));
8304 intel_crtc
->cursor_cntl
= cntl
;
8307 /* and commit changes on next vblank */
8308 I915_WRITE(CURBASE(pipe
), base
);
8309 POSTING_READ(CURBASE(pipe
));
8311 intel_crtc
->cursor_base
= base
;
8314 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8315 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
8318 struct drm_device
*dev
= crtc
->dev
;
8319 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8320 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8321 int pipe
= intel_crtc
->pipe
;
8322 int x
= crtc
->cursor_x
;
8323 int y
= crtc
->cursor_y
;
8324 u32 base
= 0, pos
= 0;
8327 base
= intel_crtc
->cursor_addr
;
8329 if (x
>= intel_crtc
->config
.pipe_src_w
)
8332 if (y
>= intel_crtc
->config
.pipe_src_h
)
8336 if (x
+ intel_crtc
->cursor_width
<= 0)
8339 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
8342 pos
|= x
<< CURSOR_X_SHIFT
;
8345 if (y
+ intel_crtc
->cursor_height
<= 0)
8348 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
8351 pos
|= y
<< CURSOR_Y_SHIFT
;
8353 if (base
== 0 && intel_crtc
->cursor_base
== 0)
8356 I915_WRITE(CURPOS(pipe
), pos
);
8358 /* ILK+ do this automagically */
8359 if (HAS_GMCH_DISPLAY(dev
) &&
8360 to_intel_plane(crtc
->cursor
)->rotation
== BIT(DRM_ROTATE_180
)) {
8361 base
+= (intel_crtc
->cursor_height
*
8362 intel_crtc
->cursor_width
- 1) * 4;
8365 if (IS_845G(dev
) || IS_I865G(dev
))
8366 i845_update_cursor(crtc
, base
);
8368 i9xx_update_cursor(crtc
, base
);
8371 static bool cursor_size_ok(struct drm_device
*dev
,
8372 uint32_t width
, uint32_t height
)
8374 if (width
== 0 || height
== 0)
8378 * 845g/865g are special in that they are only limited by
8379 * the width of their cursors, the height is arbitrary up to
8380 * the precision of the register. Everything else requires
8381 * square cursors, limited to a few power-of-two sizes.
8383 if (IS_845G(dev
) || IS_I865G(dev
)) {
8384 if ((width
& 63) != 0)
8387 if (width
> (IS_845G(dev
) ? 64 : 512))
8393 switch (width
| height
) {
8408 static int intel_crtc_cursor_set_obj(struct drm_crtc
*crtc
,
8409 struct drm_i915_gem_object
*obj
,
8410 uint32_t width
, uint32_t height
)
8412 struct drm_device
*dev
= crtc
->dev
;
8413 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8414 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8415 enum pipe pipe
= intel_crtc
->pipe
;
8420 /* if we want to turn off the cursor ignore width and height */
8422 DRM_DEBUG_KMS("cursor off\n");
8424 mutex_lock(&dev
->struct_mutex
);
8428 /* we only need to pin inside GTT if cursor is non-phy */
8429 mutex_lock(&dev
->struct_mutex
);
8430 if (!INTEL_INFO(dev
)->cursor_needs_physical
) {
8434 * Global gtt pte registers are special registers which actually
8435 * forward writes to a chunk of system memory. Which means that
8436 * there is no risk that the register values disappear as soon
8437 * as we call intel_runtime_pm_put(), so it is correct to wrap
8438 * only the pin/unpin/fence and not more.
8440 intel_runtime_pm_get(dev_priv
);
8442 /* Note that the w/a also requires 2 PTE of padding following
8443 * the bo. We currently fill all unused PTE with the shadow
8444 * page and so we should always have valid PTE following the
8445 * cursor preventing the VT-d warning.
8448 if (need_vtd_wa(dev
))
8449 alignment
= 64*1024;
8451 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, NULL
);
8453 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8454 intel_runtime_pm_put(dev_priv
);
8458 ret
= i915_gem_object_put_fence(obj
);
8460 DRM_DEBUG_KMS("failed to release fence for cursor");
8461 intel_runtime_pm_put(dev_priv
);
8465 addr
= i915_gem_obj_ggtt_offset(obj
);
8467 intel_runtime_pm_put(dev_priv
);
8469 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
8470 ret
= i915_gem_object_attach_phys(obj
, align
);
8472 DRM_DEBUG_KMS("failed to attach phys object\n");
8475 addr
= obj
->phys_handle
->busaddr
;
8479 if (intel_crtc
->cursor_bo
) {
8480 if (!INTEL_INFO(dev
)->cursor_needs_physical
)
8481 i915_gem_object_unpin_from_display_plane(intel_crtc
->cursor_bo
);
8484 i915_gem_track_fb(intel_crtc
->cursor_bo
, obj
,
8485 INTEL_FRONTBUFFER_CURSOR(pipe
));
8486 mutex_unlock(&dev
->struct_mutex
);
8488 old_width
= intel_crtc
->cursor_width
;
8490 intel_crtc
->cursor_addr
= addr
;
8491 intel_crtc
->cursor_bo
= obj
;
8492 intel_crtc
->cursor_width
= width
;
8493 intel_crtc
->cursor_height
= height
;
8495 if (intel_crtc
->active
) {
8496 if (old_width
!= width
)
8497 intel_update_watermarks(crtc
);
8498 intel_crtc_update_cursor(crtc
, intel_crtc
->cursor_bo
!= NULL
);
8500 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_CURSOR(pipe
));
8505 i915_gem_object_unpin_from_display_plane(obj
);
8507 mutex_unlock(&dev
->struct_mutex
);
8511 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
8512 u16
*blue
, uint32_t start
, uint32_t size
)
8514 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
8515 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8517 for (i
= start
; i
< end
; i
++) {
8518 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
8519 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
8520 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
8523 intel_crtc_load_lut(crtc
);
8526 /* VESA 640x480x72Hz mode to set on the pipe */
8527 static struct drm_display_mode load_detect_mode
= {
8528 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
8529 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
8532 struct drm_framebuffer
*
8533 __intel_framebuffer_create(struct drm_device
*dev
,
8534 struct drm_mode_fb_cmd2
*mode_cmd
,
8535 struct drm_i915_gem_object
*obj
)
8537 struct intel_framebuffer
*intel_fb
;
8540 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
8542 drm_gem_object_unreference(&obj
->base
);
8543 return ERR_PTR(-ENOMEM
);
8546 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
8550 return &intel_fb
->base
;
8552 drm_gem_object_unreference(&obj
->base
);
8555 return ERR_PTR(ret
);
8558 static struct drm_framebuffer
*
8559 intel_framebuffer_create(struct drm_device
*dev
,
8560 struct drm_mode_fb_cmd2
*mode_cmd
,
8561 struct drm_i915_gem_object
*obj
)
8563 struct drm_framebuffer
*fb
;
8566 ret
= i915_mutex_lock_interruptible(dev
);
8568 return ERR_PTR(ret
);
8569 fb
= __intel_framebuffer_create(dev
, mode_cmd
, obj
);
8570 mutex_unlock(&dev
->struct_mutex
);
8576 intel_framebuffer_pitch_for_width(int width
, int bpp
)
8578 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
8579 return ALIGN(pitch
, 64);
8583 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
8585 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
8586 return PAGE_ALIGN(pitch
* mode
->vdisplay
);
8589 static struct drm_framebuffer
*
8590 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
8591 struct drm_display_mode
*mode
,
8594 struct drm_i915_gem_object
*obj
;
8595 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
8597 obj
= i915_gem_alloc_object(dev
,
8598 intel_framebuffer_size_for_mode(mode
, bpp
));
8600 return ERR_PTR(-ENOMEM
);
8602 mode_cmd
.width
= mode
->hdisplay
;
8603 mode_cmd
.height
= mode
->vdisplay
;
8604 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
8606 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
8608 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
8611 static struct drm_framebuffer
*
8612 mode_fits_in_fbdev(struct drm_device
*dev
,
8613 struct drm_display_mode
*mode
)
8615 #ifdef CONFIG_DRM_I915_FBDEV
8616 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8617 struct drm_i915_gem_object
*obj
;
8618 struct drm_framebuffer
*fb
;
8620 if (!dev_priv
->fbdev
)
8623 if (!dev_priv
->fbdev
->fb
)
8626 obj
= dev_priv
->fbdev
->fb
->obj
;
8629 fb
= &dev_priv
->fbdev
->fb
->base
;
8630 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
8631 fb
->bits_per_pixel
))
8634 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
8643 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
8644 struct drm_display_mode
*mode
,
8645 struct intel_load_detect_pipe
*old
,
8646 struct drm_modeset_acquire_ctx
*ctx
)
8648 struct intel_crtc
*intel_crtc
;
8649 struct intel_encoder
*intel_encoder
=
8650 intel_attached_encoder(connector
);
8651 struct drm_crtc
*possible_crtc
;
8652 struct drm_encoder
*encoder
= &intel_encoder
->base
;
8653 struct drm_crtc
*crtc
= NULL
;
8654 struct drm_device
*dev
= encoder
->dev
;
8655 struct drm_framebuffer
*fb
;
8656 struct drm_mode_config
*config
= &dev
->mode_config
;
8659 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8660 connector
->base
.id
, connector
->name
,
8661 encoder
->base
.id
, encoder
->name
);
8664 ret
= drm_modeset_lock(&config
->connection_mutex
, ctx
);
8669 * Algorithm gets a little messy:
8671 * - if the connector already has an assigned crtc, use it (but make
8672 * sure it's on first)
8674 * - try to find the first unused crtc that can drive this connector,
8675 * and use that if we find one
8678 /* See if we already have a CRTC for this connector */
8679 if (encoder
->crtc
) {
8680 crtc
= encoder
->crtc
;
8682 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
8685 ret
= drm_modeset_lock(&crtc
->primary
->mutex
, ctx
);
8689 old
->dpms_mode
= connector
->dpms
;
8690 old
->load_detect_temp
= false;
8692 /* Make sure the crtc and connector are running */
8693 if (connector
->dpms
!= DRM_MODE_DPMS_ON
)
8694 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
8699 /* Find an unused one (if possible) */
8700 for_each_crtc(dev
, possible_crtc
) {
8702 if (!(encoder
->possible_crtcs
& (1 << i
)))
8704 if (possible_crtc
->enabled
)
8706 /* This can occur when applying the pipe A quirk on resume. */
8707 if (to_intel_crtc(possible_crtc
)->new_enabled
)
8710 crtc
= possible_crtc
;
8715 * If we didn't find an unused CRTC, don't use any.
8718 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8722 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
8725 ret
= drm_modeset_lock(&crtc
->primary
->mutex
, ctx
);
8728 intel_encoder
->new_crtc
= to_intel_crtc(crtc
);
8729 to_intel_connector(connector
)->new_encoder
= intel_encoder
;
8731 intel_crtc
= to_intel_crtc(crtc
);
8732 intel_crtc
->new_enabled
= true;
8733 intel_crtc
->new_config
= &intel_crtc
->config
;
8734 old
->dpms_mode
= connector
->dpms
;
8735 old
->load_detect_temp
= true;
8736 old
->release_fb
= NULL
;
8739 mode
= &load_detect_mode
;
8741 /* We need a framebuffer large enough to accommodate all accesses
8742 * that the plane may generate whilst we perform load detection.
8743 * We can not rely on the fbcon either being present (we get called
8744 * during its initialisation to detect all boot displays, or it may
8745 * not even exist) or that it is large enough to satisfy the
8748 fb
= mode_fits_in_fbdev(dev
, mode
);
8750 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8751 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
8752 old
->release_fb
= fb
;
8754 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8756 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8760 if (intel_set_mode(crtc
, mode
, 0, 0, fb
)) {
8761 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8762 if (old
->release_fb
)
8763 old
->release_fb
->funcs
->destroy(old
->release_fb
);
8767 /* let the connector get through one full cycle before testing */
8768 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
8772 intel_crtc
->new_enabled
= crtc
->enabled
;
8773 if (intel_crtc
->new_enabled
)
8774 intel_crtc
->new_config
= &intel_crtc
->config
;
8776 intel_crtc
->new_config
= NULL
;
8778 if (ret
== -EDEADLK
) {
8779 drm_modeset_backoff(ctx
);
8786 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
8787 struct intel_load_detect_pipe
*old
)
8789 struct intel_encoder
*intel_encoder
=
8790 intel_attached_encoder(connector
);
8791 struct drm_encoder
*encoder
= &intel_encoder
->base
;
8792 struct drm_crtc
*crtc
= encoder
->crtc
;
8793 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8795 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8796 connector
->base
.id
, connector
->name
,
8797 encoder
->base
.id
, encoder
->name
);
8799 if (old
->load_detect_temp
) {
8800 to_intel_connector(connector
)->new_encoder
= NULL
;
8801 intel_encoder
->new_crtc
= NULL
;
8802 intel_crtc
->new_enabled
= false;
8803 intel_crtc
->new_config
= NULL
;
8804 intel_set_mode(crtc
, NULL
, 0, 0, NULL
);
8806 if (old
->release_fb
) {
8807 drm_framebuffer_unregister_private(old
->release_fb
);
8808 drm_framebuffer_unreference(old
->release_fb
);
8814 /* Switch crtc and encoder back off if necessary */
8815 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
)
8816 connector
->funcs
->dpms(connector
, old
->dpms_mode
);
8819 static int i9xx_pll_refclk(struct drm_device
*dev
,
8820 const struct intel_crtc_config
*pipe_config
)
8822 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8823 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
8825 if ((dpll
& PLL_REF_INPUT_MASK
) == PLLB_REF_INPUT_SPREADSPECTRUMIN
)
8826 return dev_priv
->vbt
.lvds_ssc_freq
;
8827 else if (HAS_PCH_SPLIT(dev
))
8829 else if (!IS_GEN2(dev
))
8835 /* Returns the clock of the currently programmed mode of the given pipe. */
8836 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
8837 struct intel_crtc_config
*pipe_config
)
8839 struct drm_device
*dev
= crtc
->base
.dev
;
8840 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8841 int pipe
= pipe_config
->cpu_transcoder
;
8842 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
8844 intel_clock_t clock
;
8845 int refclk
= i9xx_pll_refclk(dev
, pipe_config
);
8847 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
8848 fp
= pipe_config
->dpll_hw_state
.fp0
;
8850 fp
= pipe_config
->dpll_hw_state
.fp1
;
8852 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
8853 if (IS_PINEVIEW(dev
)) {
8854 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
8855 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
8857 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
8858 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
8861 if (!IS_GEN2(dev
)) {
8862 if (IS_PINEVIEW(dev
))
8863 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
8864 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
8866 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
8867 DPLL_FPA01_P1_POST_DIV_SHIFT
);
8869 switch (dpll
& DPLL_MODE_MASK
) {
8870 case DPLLB_MODE_DAC_SERIAL
:
8871 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
8874 case DPLLB_MODE_LVDS
:
8875 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
8879 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8880 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
8884 if (IS_PINEVIEW(dev
))
8885 pineview_clock(refclk
, &clock
);
8887 i9xx_clock(refclk
, &clock
);
8889 u32 lvds
= IS_I830(dev
) ? 0 : I915_READ(LVDS
);
8890 bool is_lvds
= (pipe
== 1) && (lvds
& LVDS_PORT_EN
);
8893 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
8894 DPLL_FPA01_P1_POST_DIV_SHIFT
);
8896 if (lvds
& LVDS_CLKB_POWER_UP
)
8901 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
8904 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
8905 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
8907 if (dpll
& PLL_P2_DIVIDE_BY_4
)
8913 i9xx_clock(refclk
, &clock
);
8917 * This value includes pixel_multiplier. We will use
8918 * port_clock to compute adjusted_mode.crtc_clock in the
8919 * encoder's get_config() function.
8921 pipe_config
->port_clock
= clock
.dot
;
8924 int intel_dotclock_calculate(int link_freq
,
8925 const struct intel_link_m_n
*m_n
)
8928 * The calculation for the data clock is:
8929 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8930 * But we want to avoid losing precison if possible, so:
8931 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8933 * and the link clock is simpler:
8934 * link_clock = (m * link_clock) / n
8940 return div_u64((u64
)m_n
->link_m
* link_freq
, m_n
->link_n
);
8943 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
8944 struct intel_crtc_config
*pipe_config
)
8946 struct drm_device
*dev
= crtc
->base
.dev
;
8948 /* read out port_clock from the DPLL */
8949 i9xx_crtc_clock_get(crtc
, pipe_config
);
8952 * This value does not include pixel_multiplier.
8953 * We will check that port_clock and adjusted_mode.crtc_clock
8954 * agree once we know their relationship in the encoder's
8955 * get_config() function.
8957 pipe_config
->adjusted_mode
.crtc_clock
=
8958 intel_dotclock_calculate(intel_fdi_link_freq(dev
) * 10000,
8959 &pipe_config
->fdi_m_n
);
8962 /** Returns the currently programmed mode of the given pipe. */
8963 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
8964 struct drm_crtc
*crtc
)
8966 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8967 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8968 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
8969 struct drm_display_mode
*mode
;
8970 struct intel_crtc_config pipe_config
;
8971 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
8972 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
8973 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
8974 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
8975 enum pipe pipe
= intel_crtc
->pipe
;
8977 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
8982 * Construct a pipe_config sufficient for getting the clock info
8983 * back out of crtc_clock_get.
8985 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8986 * to use a real value here instead.
8988 pipe_config
.cpu_transcoder
= (enum transcoder
) pipe
;
8989 pipe_config
.pixel_multiplier
= 1;
8990 pipe_config
.dpll_hw_state
.dpll
= I915_READ(DPLL(pipe
));
8991 pipe_config
.dpll_hw_state
.fp0
= I915_READ(FP0(pipe
));
8992 pipe_config
.dpll_hw_state
.fp1
= I915_READ(FP1(pipe
));
8993 i9xx_crtc_clock_get(intel_crtc
, &pipe_config
);
8995 mode
->clock
= pipe_config
.port_clock
/ pipe_config
.pixel_multiplier
;
8996 mode
->hdisplay
= (htot
& 0xffff) + 1;
8997 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
8998 mode
->hsync_start
= (hsync
& 0xffff) + 1;
8999 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
9000 mode
->vdisplay
= (vtot
& 0xffff) + 1;
9001 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
9002 mode
->vsync_start
= (vsync
& 0xffff) + 1;
9003 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
9005 drm_mode_set_name(mode
);
9010 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
9012 struct drm_device
*dev
= crtc
->dev
;
9013 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9014 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9016 if (!HAS_GMCH_DISPLAY(dev
))
9019 if (!dev_priv
->lvds_downclock_avail
)
9023 * Since this is called by a timer, we should never get here in
9026 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
9027 int pipe
= intel_crtc
->pipe
;
9028 int dpll_reg
= DPLL(pipe
);
9031 DRM_DEBUG_DRIVER("downclocking LVDS\n");
9033 assert_panel_unlocked(dev_priv
, pipe
);
9035 dpll
= I915_READ(dpll_reg
);
9036 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
9037 I915_WRITE(dpll_reg
, dpll
);
9038 intel_wait_for_vblank(dev
, pipe
);
9039 dpll
= I915_READ(dpll_reg
);
9040 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
9041 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
9046 void intel_mark_busy(struct drm_device
*dev
)
9048 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9050 if (dev_priv
->mm
.busy
)
9053 intel_runtime_pm_get(dev_priv
);
9054 i915_update_gfx_val(dev_priv
);
9055 dev_priv
->mm
.busy
= true;
9058 void intel_mark_idle(struct drm_device
*dev
)
9060 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9061 struct drm_crtc
*crtc
;
9063 if (!dev_priv
->mm
.busy
)
9066 dev_priv
->mm
.busy
= false;
9068 if (!i915
.powersave
)
9071 for_each_crtc(dev
, crtc
) {
9072 if (!crtc
->primary
->fb
)
9075 intel_decrease_pllclock(crtc
);
9078 if (INTEL_INFO(dev
)->gen
>= 6)
9079 gen6_rps_idle(dev
->dev_private
);
9082 intel_runtime_pm_put(dev_priv
);
9085 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
9087 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9088 struct drm_device
*dev
= crtc
->dev
;
9089 struct intel_unpin_work
*work
;
9091 spin_lock_irq(&dev
->event_lock
);
9092 work
= intel_crtc
->unpin_work
;
9093 intel_crtc
->unpin_work
= NULL
;
9094 spin_unlock_irq(&dev
->event_lock
);
9097 cancel_work_sync(&work
->work
);
9101 drm_crtc_cleanup(crtc
);
9106 static void intel_unpin_work_fn(struct work_struct
*__work
)
9108 struct intel_unpin_work
*work
=
9109 container_of(__work
, struct intel_unpin_work
, work
);
9110 struct drm_device
*dev
= work
->crtc
->dev
;
9111 enum pipe pipe
= to_intel_crtc(work
->crtc
)->pipe
;
9113 mutex_lock(&dev
->struct_mutex
);
9114 intel_unpin_fb_obj(work
->old_fb_obj
);
9115 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
9116 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
9118 intel_update_fbc(dev
);
9119 mutex_unlock(&dev
->struct_mutex
);
9121 intel_frontbuffer_flip_complete(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
9123 BUG_ON(atomic_read(&to_intel_crtc(work
->crtc
)->unpin_work_count
) == 0);
9124 atomic_dec(&to_intel_crtc(work
->crtc
)->unpin_work_count
);
9129 static void do_intel_finish_page_flip(struct drm_device
*dev
,
9130 struct drm_crtc
*crtc
)
9132 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9133 struct intel_unpin_work
*work
;
9134 unsigned long flags
;
9136 /* Ignore early vblank irqs */
9137 if (intel_crtc
== NULL
)
9141 * This is called both by irq handlers and the reset code (to complete
9142 * lost pageflips) so needs the full irqsave spinlocks.
9144 spin_lock_irqsave(&dev
->event_lock
, flags
);
9145 work
= intel_crtc
->unpin_work
;
9147 /* Ensure we don't miss a work->pending update ... */
9150 if (work
== NULL
|| atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
9151 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9155 page_flip_completed(intel_crtc
);
9157 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9160 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
9162 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9163 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
9165 do_intel_finish_page_flip(dev
, crtc
);
9168 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
9170 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9171 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
9173 do_intel_finish_page_flip(dev
, crtc
);
9176 /* Is 'a' after or equal to 'b'? */
9177 static bool g4x_flip_count_after_eq(u32 a
, u32 b
)
9179 return !((a
- b
) & 0x80000000);
9182 static bool page_flip_finished(struct intel_crtc
*crtc
)
9184 struct drm_device
*dev
= crtc
->base
.dev
;
9185 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9187 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
9188 crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
9192 * The relevant registers doen't exist on pre-ctg.
9193 * As the flip done interrupt doesn't trigger for mmio
9194 * flips on gmch platforms, a flip count check isn't
9195 * really needed there. But since ctg has the registers,
9196 * include it in the check anyway.
9198 if (INTEL_INFO(dev
)->gen
< 5 && !IS_G4X(dev
))
9202 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9203 * used the same base address. In that case the mmio flip might
9204 * have completed, but the CS hasn't even executed the flip yet.
9206 * A flip count check isn't enough as the CS might have updated
9207 * the base address just after start of vblank, but before we
9208 * managed to process the interrupt. This means we'd complete the
9211 * Combining both checks should get us a good enough result. It may
9212 * still happen that the CS flip has been executed, but has not
9213 * yet actually completed. But in case the base address is the same
9214 * anyway, we don't really care.
9216 return (I915_READ(DSPSURFLIVE(crtc
->plane
)) & ~0xfff) ==
9217 crtc
->unpin_work
->gtt_offset
&&
9218 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc
->pipe
)),
9219 crtc
->unpin_work
->flip_count
);
9222 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
9224 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9225 struct intel_crtc
*intel_crtc
=
9226 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
9227 unsigned long flags
;
9231 * This is called both by irq handlers and the reset code (to complete
9232 * lost pageflips) so needs the full irqsave spinlocks.
9234 * NB: An MMIO update of the plane base pointer will also
9235 * generate a page-flip completion irq, i.e. every modeset
9236 * is also accompanied by a spurious intel_prepare_page_flip().
9238 spin_lock_irqsave(&dev
->event_lock
, flags
);
9239 if (intel_crtc
->unpin_work
&& page_flip_finished(intel_crtc
))
9240 atomic_inc_not_zero(&intel_crtc
->unpin_work
->pending
);
9241 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9244 static inline void intel_mark_page_flip_active(struct intel_crtc
*intel_crtc
)
9246 /* Ensure that the work item is consistent when activating it ... */
9248 atomic_set(&intel_crtc
->unpin_work
->pending
, INTEL_FLIP_PENDING
);
9249 /* and that it is marked active as soon as the irq could fire. */
9253 static int intel_gen2_queue_flip(struct drm_device
*dev
,
9254 struct drm_crtc
*crtc
,
9255 struct drm_framebuffer
*fb
,
9256 struct drm_i915_gem_object
*obj
,
9257 struct intel_engine_cs
*ring
,
9260 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9264 ret
= intel_ring_begin(ring
, 6);
9268 /* Can't queue multiple flips, so wait for the previous
9269 * one to finish before executing the next.
9271 if (intel_crtc
->plane
)
9272 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
9274 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
9275 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
9276 intel_ring_emit(ring
, MI_NOOP
);
9277 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
9278 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9279 intel_ring_emit(ring
, fb
->pitches
[0]);
9280 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9281 intel_ring_emit(ring
, 0); /* aux display base address, unused */
9283 intel_mark_page_flip_active(intel_crtc
);
9284 __intel_ring_advance(ring
);
9288 static int intel_gen3_queue_flip(struct drm_device
*dev
,
9289 struct drm_crtc
*crtc
,
9290 struct drm_framebuffer
*fb
,
9291 struct drm_i915_gem_object
*obj
,
9292 struct intel_engine_cs
*ring
,
9295 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9299 ret
= intel_ring_begin(ring
, 6);
9303 if (intel_crtc
->plane
)
9304 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
9306 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
9307 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
9308 intel_ring_emit(ring
, MI_NOOP
);
9309 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
9310 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9311 intel_ring_emit(ring
, fb
->pitches
[0]);
9312 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9313 intel_ring_emit(ring
, MI_NOOP
);
9315 intel_mark_page_flip_active(intel_crtc
);
9316 __intel_ring_advance(ring
);
9320 static int intel_gen4_queue_flip(struct drm_device
*dev
,
9321 struct drm_crtc
*crtc
,
9322 struct drm_framebuffer
*fb
,
9323 struct drm_i915_gem_object
*obj
,
9324 struct intel_engine_cs
*ring
,
9327 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9328 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9329 uint32_t pf
, pipesrc
;
9332 ret
= intel_ring_begin(ring
, 4);
9336 /* i965+ uses the linear or tiled offsets from the
9337 * Display Registers (which do not change across a page-flip)
9338 * so we need only reprogram the base address.
9340 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
9341 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9342 intel_ring_emit(ring
, fb
->pitches
[0]);
9343 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
|
9346 /* XXX Enabling the panel-fitter across page-flip is so far
9347 * untested on non-native modes, so ignore it for now.
9348 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9351 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
9352 intel_ring_emit(ring
, pf
| pipesrc
);
9354 intel_mark_page_flip_active(intel_crtc
);
9355 __intel_ring_advance(ring
);
9359 static int intel_gen6_queue_flip(struct drm_device
*dev
,
9360 struct drm_crtc
*crtc
,
9361 struct drm_framebuffer
*fb
,
9362 struct drm_i915_gem_object
*obj
,
9363 struct intel_engine_cs
*ring
,
9366 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9367 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9368 uint32_t pf
, pipesrc
;
9371 ret
= intel_ring_begin(ring
, 4);
9375 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
9376 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9377 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
9378 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9380 /* Contrary to the suggestions in the documentation,
9381 * "Enable Panel Fitter" does not seem to be required when page
9382 * flipping with a non-native mode, and worse causes a normal
9384 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9387 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
9388 intel_ring_emit(ring
, pf
| pipesrc
);
9390 intel_mark_page_flip_active(intel_crtc
);
9391 __intel_ring_advance(ring
);
9395 static int intel_gen7_queue_flip(struct drm_device
*dev
,
9396 struct drm_crtc
*crtc
,
9397 struct drm_framebuffer
*fb
,
9398 struct drm_i915_gem_object
*obj
,
9399 struct intel_engine_cs
*ring
,
9402 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9403 uint32_t plane_bit
= 0;
9406 switch (intel_crtc
->plane
) {
9408 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
9411 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
9414 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
9417 WARN_ONCE(1, "unknown plane in flip command\n");
9422 if (ring
->id
== RCS
) {
9425 * On Gen 8, SRM is now taking an extra dword to accommodate
9426 * 48bits addresses, and we need a NOOP for the batch size to
9434 * BSpec MI_DISPLAY_FLIP for IVB:
9435 * "The full packet must be contained within the same cache line."
9437 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9438 * cacheline, if we ever start emitting more commands before
9439 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9440 * then do the cacheline alignment, and finally emit the
9443 ret
= intel_ring_cacheline_align(ring
);
9447 ret
= intel_ring_begin(ring
, len
);
9451 /* Unmask the flip-done completion message. Note that the bspec says that
9452 * we should do this for both the BCS and RCS, and that we must not unmask
9453 * more than one flip event at any time (or ensure that one flip message
9454 * can be sent by waiting for flip-done prior to queueing new flips).
9455 * Experimentation says that BCS works despite DERRMR masking all
9456 * flip-done completion events and that unmasking all planes at once
9457 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9458 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9460 if (ring
->id
== RCS
) {
9461 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
9462 intel_ring_emit(ring
, DERRMR
);
9463 intel_ring_emit(ring
, ~(DERRMR_PIPEA_PRI_FLIP_DONE
|
9464 DERRMR_PIPEB_PRI_FLIP_DONE
|
9465 DERRMR_PIPEC_PRI_FLIP_DONE
));
9467 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM_GEN8(1) |
9468 MI_SRM_LRM_GLOBAL_GTT
);
9470 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM(1) |
9471 MI_SRM_LRM_GLOBAL_GTT
);
9472 intel_ring_emit(ring
, DERRMR
);
9473 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
+ 256);
9475 intel_ring_emit(ring
, 0);
9476 intel_ring_emit(ring
, MI_NOOP
);
9480 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
9481 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
9482 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9483 intel_ring_emit(ring
, (MI_NOOP
));
9485 intel_mark_page_flip_active(intel_crtc
);
9486 __intel_ring_advance(ring
);
9490 static bool use_mmio_flip(struct intel_engine_cs
*ring
,
9491 struct drm_i915_gem_object
*obj
)
9494 * This is not being used for older platforms, because
9495 * non-availability of flip done interrupt forces us to use
9496 * CS flips. Older platforms derive flip done using some clever
9497 * tricks involving the flip_pending status bits and vblank irqs.
9498 * So using MMIO flips there would disrupt this mechanism.
9504 if (INTEL_INFO(ring
->dev
)->gen
< 5)
9507 if (i915
.use_mmio_flip
< 0)
9509 else if (i915
.use_mmio_flip
> 0)
9511 else if (i915
.enable_execlists
)
9514 return ring
!= obj
->ring
;
9517 static void intel_do_mmio_flip(struct intel_crtc
*intel_crtc
)
9519 struct drm_device
*dev
= intel_crtc
->base
.dev
;
9520 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9521 struct intel_framebuffer
*intel_fb
=
9522 to_intel_framebuffer(intel_crtc
->base
.primary
->fb
);
9523 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
9525 u32 start_vbl_count
;
9529 intel_mark_page_flip_active(intel_crtc
);
9531 atomic_update
= intel_pipe_update_start(intel_crtc
, &start_vbl_count
);
9533 reg
= DSPCNTR(intel_crtc
->plane
);
9534 dspcntr
= I915_READ(reg
);
9536 if (obj
->tiling_mode
!= I915_TILING_NONE
)
9537 dspcntr
|= DISPPLANE_TILED
;
9539 dspcntr
&= ~DISPPLANE_TILED
;
9541 I915_WRITE(reg
, dspcntr
);
9543 I915_WRITE(DSPSURF(intel_crtc
->plane
),
9544 intel_crtc
->unpin_work
->gtt_offset
);
9545 POSTING_READ(DSPSURF(intel_crtc
->plane
));
9548 intel_pipe_update_end(intel_crtc
, start_vbl_count
);
9551 static void intel_mmio_flip_work_func(struct work_struct
*work
)
9553 struct intel_crtc
*intel_crtc
=
9554 container_of(work
, struct intel_crtc
, mmio_flip
.work
);
9555 struct intel_engine_cs
*ring
;
9558 seqno
= intel_crtc
->mmio_flip
.seqno
;
9559 ring
= intel_crtc
->mmio_flip
.ring
;
9562 WARN_ON(__i915_wait_seqno(ring
, seqno
,
9563 intel_crtc
->reset_counter
,
9564 false, NULL
, NULL
) != 0);
9566 intel_do_mmio_flip(intel_crtc
);
9569 static int intel_queue_mmio_flip(struct drm_device
*dev
,
9570 struct drm_crtc
*crtc
,
9571 struct drm_framebuffer
*fb
,
9572 struct drm_i915_gem_object
*obj
,
9573 struct intel_engine_cs
*ring
,
9576 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9578 intel_crtc
->mmio_flip
.seqno
= obj
->last_write_seqno
;
9579 intel_crtc
->mmio_flip
.ring
= obj
->ring
;
9581 schedule_work(&intel_crtc
->mmio_flip
.work
);
9586 static int intel_gen9_queue_flip(struct drm_device
*dev
,
9587 struct drm_crtc
*crtc
,
9588 struct drm_framebuffer
*fb
,
9589 struct drm_i915_gem_object
*obj
,
9590 struct intel_engine_cs
*ring
,
9593 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9594 uint32_t plane
= 0, stride
;
9597 switch(intel_crtc
->pipe
) {
9599 plane
= MI_DISPLAY_FLIP_SKL_PLANE_1_A
;
9602 plane
= MI_DISPLAY_FLIP_SKL_PLANE_1_B
;
9605 plane
= MI_DISPLAY_FLIP_SKL_PLANE_1_C
;
9608 WARN_ONCE(1, "unknown plane in flip command\n");
9612 switch (obj
->tiling_mode
) {
9613 case I915_TILING_NONE
:
9614 stride
= fb
->pitches
[0] >> 6;
9617 stride
= fb
->pitches
[0] >> 9;
9620 WARN_ONCE(1, "unknown tiling in flip command\n");
9624 ret
= intel_ring_begin(ring
, 10);
9628 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
9629 intel_ring_emit(ring
, DERRMR
);
9630 intel_ring_emit(ring
, ~(DERRMR_PIPEA_PRI_FLIP_DONE
|
9631 DERRMR_PIPEB_PRI_FLIP_DONE
|
9632 DERRMR_PIPEC_PRI_FLIP_DONE
));
9633 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM_GEN8(1) |
9634 MI_SRM_LRM_GLOBAL_GTT
);
9635 intel_ring_emit(ring
, DERRMR
);
9636 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
+ 256);
9637 intel_ring_emit(ring
, 0);
9639 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane
);
9640 intel_ring_emit(ring
, stride
<< 6 | obj
->tiling_mode
);
9641 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9643 intel_mark_page_flip_active(intel_crtc
);
9644 __intel_ring_advance(ring
);
9649 static int intel_default_queue_flip(struct drm_device
*dev
,
9650 struct drm_crtc
*crtc
,
9651 struct drm_framebuffer
*fb
,
9652 struct drm_i915_gem_object
*obj
,
9653 struct intel_engine_cs
*ring
,
9659 static bool __intel_pageflip_stall_check(struct drm_device
*dev
,
9660 struct drm_crtc
*crtc
)
9662 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9663 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9664 struct intel_unpin_work
*work
= intel_crtc
->unpin_work
;
9667 if (atomic_read(&work
->pending
) >= INTEL_FLIP_COMPLETE
)
9670 if (!work
->enable_stall_check
)
9673 if (work
->flip_ready_vblank
== 0) {
9674 if (work
->flip_queued_ring
&&
9675 !i915_seqno_passed(work
->flip_queued_ring
->get_seqno(work
->flip_queued_ring
, true),
9676 work
->flip_queued_seqno
))
9679 work
->flip_ready_vblank
= drm_vblank_count(dev
, intel_crtc
->pipe
);
9682 if (drm_vblank_count(dev
, intel_crtc
->pipe
) - work
->flip_ready_vblank
< 3)
9685 /* Potential stall - if we see that the flip has happened,
9686 * assume a missed interrupt. */
9687 if (INTEL_INFO(dev
)->gen
>= 4)
9688 addr
= I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc
->plane
)));
9690 addr
= I915_READ(DSPADDR(intel_crtc
->plane
));
9692 /* There is a potential issue here with a false positive after a flip
9693 * to the same address. We could address this by checking for a
9694 * non-incrementing frame counter.
9696 return addr
== work
->gtt_offset
;
9699 void intel_check_page_flip(struct drm_device
*dev
, int pipe
)
9701 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9702 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
9703 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9710 spin_lock(&dev
->event_lock
);
9711 if (intel_crtc
->unpin_work
&& __intel_pageflip_stall_check(dev
, crtc
)) {
9712 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9713 intel_crtc
->unpin_work
->flip_queued_vblank
, drm_vblank_count(dev
, pipe
));
9714 page_flip_completed(intel_crtc
);
9716 spin_unlock(&dev
->event_lock
);
9719 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
9720 struct drm_framebuffer
*fb
,
9721 struct drm_pending_vblank_event
*event
,
9722 uint32_t page_flip_flags
)
9724 struct drm_device
*dev
= crtc
->dev
;
9725 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9726 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
9727 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
9728 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9729 enum pipe pipe
= intel_crtc
->pipe
;
9730 struct intel_unpin_work
*work
;
9731 struct intel_engine_cs
*ring
;
9735 * drm_mode_page_flip_ioctl() should already catch this, but double
9736 * check to be safe. In the future we may enable pageflipping from
9737 * a disabled primary plane.
9739 if (WARN_ON(intel_fb_obj(old_fb
) == NULL
))
9742 /* Can't change pixel format via MI display flips. */
9743 if (fb
->pixel_format
!= crtc
->primary
->fb
->pixel_format
)
9747 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9748 * Note that pitch changes could also affect these register.
9750 if (INTEL_INFO(dev
)->gen
> 3 &&
9751 (fb
->offsets
[0] != crtc
->primary
->fb
->offsets
[0] ||
9752 fb
->pitches
[0] != crtc
->primary
->fb
->pitches
[0]))
9755 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
9758 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
9762 work
->event
= event
;
9764 work
->old_fb_obj
= intel_fb_obj(old_fb
);
9765 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
9767 ret
= drm_crtc_vblank_get(crtc
);
9771 /* We borrow the event spin lock for protecting unpin_work */
9772 spin_lock_irq(&dev
->event_lock
);
9773 if (intel_crtc
->unpin_work
) {
9774 /* Before declaring the flip queue wedged, check if
9775 * the hardware completed the operation behind our backs.
9777 if (__intel_pageflip_stall_check(dev
, crtc
)) {
9778 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9779 page_flip_completed(intel_crtc
);
9781 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9782 spin_unlock_irq(&dev
->event_lock
);
9784 drm_crtc_vblank_put(crtc
);
9789 intel_crtc
->unpin_work
= work
;
9790 spin_unlock_irq(&dev
->event_lock
);
9792 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
9793 flush_workqueue(dev_priv
->wq
);
9795 ret
= i915_mutex_lock_interruptible(dev
);
9799 /* Reference the objects for the scheduled work. */
9800 drm_gem_object_reference(&work
->old_fb_obj
->base
);
9801 drm_gem_object_reference(&obj
->base
);
9803 crtc
->primary
->fb
= fb
;
9805 work
->pending_flip_obj
= obj
;
9807 atomic_inc(&intel_crtc
->unpin_work_count
);
9808 intel_crtc
->reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
9810 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
9811 work
->flip_count
= I915_READ(PIPE_FLIPCOUNT_GM45(pipe
)) + 1;
9813 if (IS_VALLEYVIEW(dev
)) {
9814 ring
= &dev_priv
->ring
[BCS
];
9815 if (obj
->tiling_mode
!= work
->old_fb_obj
->tiling_mode
)
9816 /* vlv: DISPLAY_FLIP fails to change tiling */
9818 } else if (IS_IVYBRIDGE(dev
)) {
9819 ring
= &dev_priv
->ring
[BCS
];
9820 } else if (INTEL_INFO(dev
)->gen
>= 7) {
9822 if (ring
== NULL
|| ring
->id
!= RCS
)
9823 ring
= &dev_priv
->ring
[BCS
];
9825 ring
= &dev_priv
->ring
[RCS
];
9828 ret
= intel_pin_and_fence_fb_obj(crtc
->primary
, fb
, ring
);
9830 goto cleanup_pending
;
9833 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
;
9835 if (use_mmio_flip(ring
, obj
)) {
9836 ret
= intel_queue_mmio_flip(dev
, crtc
, fb
, obj
, ring
,
9841 work
->flip_queued_seqno
= obj
->last_write_seqno
;
9842 work
->flip_queued_ring
= obj
->ring
;
9844 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
, ring
,
9849 work
->flip_queued_seqno
= intel_ring_get_seqno(ring
);
9850 work
->flip_queued_ring
= ring
;
9853 work
->flip_queued_vblank
= drm_vblank_count(dev
, intel_crtc
->pipe
);
9854 work
->enable_stall_check
= true;
9856 i915_gem_track_fb(work
->old_fb_obj
, obj
,
9857 INTEL_FRONTBUFFER_PRIMARY(pipe
));
9859 intel_disable_fbc(dev
);
9860 intel_frontbuffer_flip_prepare(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
9861 mutex_unlock(&dev
->struct_mutex
);
9863 trace_i915_flip_request(intel_crtc
->plane
, obj
);
9868 intel_unpin_fb_obj(obj
);
9870 atomic_dec(&intel_crtc
->unpin_work_count
);
9871 crtc
->primary
->fb
= old_fb
;
9872 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
9873 drm_gem_object_unreference(&obj
->base
);
9874 mutex_unlock(&dev
->struct_mutex
);
9877 spin_lock_irq(&dev
->event_lock
);
9878 intel_crtc
->unpin_work
= NULL
;
9879 spin_unlock_irq(&dev
->event_lock
);
9881 drm_crtc_vblank_put(crtc
);
9887 intel_crtc_wait_for_pending_flips(crtc
);
9888 ret
= intel_pipe_set_base(crtc
, crtc
->x
, crtc
->y
, fb
);
9889 if (ret
== 0 && event
) {
9890 spin_lock_irq(&dev
->event_lock
);
9891 drm_send_vblank_event(dev
, pipe
, event
);
9892 spin_unlock_irq(&dev
->event_lock
);
9898 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
9899 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
9900 .load_lut
= intel_crtc_load_lut
,
9904 * intel_modeset_update_staged_output_state
9906 * Updates the staged output configuration state, e.g. after we've read out the
9909 static void intel_modeset_update_staged_output_state(struct drm_device
*dev
)
9911 struct intel_crtc
*crtc
;
9912 struct intel_encoder
*encoder
;
9913 struct intel_connector
*connector
;
9915 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9917 connector
->new_encoder
=
9918 to_intel_encoder(connector
->base
.encoder
);
9921 for_each_intel_encoder(dev
, encoder
) {
9923 to_intel_crtc(encoder
->base
.crtc
);
9926 for_each_intel_crtc(dev
, crtc
) {
9927 crtc
->new_enabled
= crtc
->base
.enabled
;
9929 if (crtc
->new_enabled
)
9930 crtc
->new_config
= &crtc
->config
;
9932 crtc
->new_config
= NULL
;
9937 * intel_modeset_commit_output_state
9939 * This function copies the stage display pipe configuration to the real one.
9941 static void intel_modeset_commit_output_state(struct drm_device
*dev
)
9943 struct intel_crtc
*crtc
;
9944 struct intel_encoder
*encoder
;
9945 struct intel_connector
*connector
;
9947 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9949 connector
->base
.encoder
= &connector
->new_encoder
->base
;
9952 for_each_intel_encoder(dev
, encoder
) {
9953 encoder
->base
.crtc
= &encoder
->new_crtc
->base
;
9956 for_each_intel_crtc(dev
, crtc
) {
9957 crtc
->base
.enabled
= crtc
->new_enabled
;
9962 connected_sink_compute_bpp(struct intel_connector
*connector
,
9963 struct intel_crtc_config
*pipe_config
)
9965 int bpp
= pipe_config
->pipe_bpp
;
9967 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9968 connector
->base
.base
.id
,
9969 connector
->base
.name
);
9971 /* Don't use an invalid EDID bpc value */
9972 if (connector
->base
.display_info
.bpc
&&
9973 connector
->base
.display_info
.bpc
* 3 < bpp
) {
9974 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9975 bpp
, connector
->base
.display_info
.bpc
*3);
9976 pipe_config
->pipe_bpp
= connector
->base
.display_info
.bpc
*3;
9979 /* Clamp bpp to 8 on screens without EDID 1.4 */
9980 if (connector
->base
.display_info
.bpc
== 0 && bpp
> 24) {
9981 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9983 pipe_config
->pipe_bpp
= 24;
9988 compute_baseline_pipe_bpp(struct intel_crtc
*crtc
,
9989 struct drm_framebuffer
*fb
,
9990 struct intel_crtc_config
*pipe_config
)
9992 struct drm_device
*dev
= crtc
->base
.dev
;
9993 struct intel_connector
*connector
;
9996 switch (fb
->pixel_format
) {
9998 bpp
= 8*3; /* since we go through a colormap */
10000 case DRM_FORMAT_XRGB1555
:
10001 case DRM_FORMAT_ARGB1555
:
10002 /* checked in intel_framebuffer_init already */
10003 if (WARN_ON(INTEL_INFO(dev
)->gen
> 3))
10005 case DRM_FORMAT_RGB565
:
10006 bpp
= 6*3; /* min is 18bpp */
10008 case DRM_FORMAT_XBGR8888
:
10009 case DRM_FORMAT_ABGR8888
:
10010 /* checked in intel_framebuffer_init already */
10011 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
10013 case DRM_FORMAT_XRGB8888
:
10014 case DRM_FORMAT_ARGB8888
:
10017 case DRM_FORMAT_XRGB2101010
:
10018 case DRM_FORMAT_ARGB2101010
:
10019 case DRM_FORMAT_XBGR2101010
:
10020 case DRM_FORMAT_ABGR2101010
:
10021 /* checked in intel_framebuffer_init already */
10022 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
10026 /* TODO: gen4+ supports 16 bpc floating point, too. */
10028 DRM_DEBUG_KMS("unsupported depth\n");
10032 pipe_config
->pipe_bpp
= bpp
;
10034 /* Clamp display bpp to EDID value */
10035 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10037 if (!connector
->new_encoder
||
10038 connector
->new_encoder
->new_crtc
!= crtc
)
10041 connected_sink_compute_bpp(connector
, pipe_config
);
10047 static void intel_dump_crtc_timings(const struct drm_display_mode
*mode
)
10049 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10050 "type: 0x%x flags: 0x%x\n",
10052 mode
->crtc_hdisplay
, mode
->crtc_hsync_start
,
10053 mode
->crtc_hsync_end
, mode
->crtc_htotal
,
10054 mode
->crtc_vdisplay
, mode
->crtc_vsync_start
,
10055 mode
->crtc_vsync_end
, mode
->crtc_vtotal
, mode
->type
, mode
->flags
);
10058 static void intel_dump_pipe_config(struct intel_crtc
*crtc
,
10059 struct intel_crtc_config
*pipe_config
,
10060 const char *context
)
10062 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc
->base
.base
.id
,
10063 context
, pipe_name(crtc
->pipe
));
10065 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config
->cpu_transcoder
));
10066 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10067 pipe_config
->pipe_bpp
, pipe_config
->dither
);
10068 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10069 pipe_config
->has_pch_encoder
,
10070 pipe_config
->fdi_lanes
,
10071 pipe_config
->fdi_m_n
.gmch_m
, pipe_config
->fdi_m_n
.gmch_n
,
10072 pipe_config
->fdi_m_n
.link_m
, pipe_config
->fdi_m_n
.link_n
,
10073 pipe_config
->fdi_m_n
.tu
);
10074 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10075 pipe_config
->has_dp_encoder
,
10076 pipe_config
->dp_m_n
.gmch_m
, pipe_config
->dp_m_n
.gmch_n
,
10077 pipe_config
->dp_m_n
.link_m
, pipe_config
->dp_m_n
.link_n
,
10078 pipe_config
->dp_m_n
.tu
);
10080 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10081 pipe_config
->has_dp_encoder
,
10082 pipe_config
->dp_m2_n2
.gmch_m
,
10083 pipe_config
->dp_m2_n2
.gmch_n
,
10084 pipe_config
->dp_m2_n2
.link_m
,
10085 pipe_config
->dp_m2_n2
.link_n
,
10086 pipe_config
->dp_m2_n2
.tu
);
10088 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10089 pipe_config
->has_audio
,
10090 pipe_config
->has_infoframe
);
10092 DRM_DEBUG_KMS("requested mode:\n");
10093 drm_mode_debug_printmodeline(&pipe_config
->requested_mode
);
10094 DRM_DEBUG_KMS("adjusted mode:\n");
10095 drm_mode_debug_printmodeline(&pipe_config
->adjusted_mode
);
10096 intel_dump_crtc_timings(&pipe_config
->adjusted_mode
);
10097 DRM_DEBUG_KMS("port clock: %d\n", pipe_config
->port_clock
);
10098 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10099 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
);
10100 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10101 pipe_config
->gmch_pfit
.control
,
10102 pipe_config
->gmch_pfit
.pgm_ratios
,
10103 pipe_config
->gmch_pfit
.lvds_border_bits
);
10104 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10105 pipe_config
->pch_pfit
.pos
,
10106 pipe_config
->pch_pfit
.size
,
10107 pipe_config
->pch_pfit
.enabled
? "enabled" : "disabled");
10108 DRM_DEBUG_KMS("ips: %i\n", pipe_config
->ips_enabled
);
10109 DRM_DEBUG_KMS("double wide: %i\n", pipe_config
->double_wide
);
10112 static bool encoders_cloneable(const struct intel_encoder
*a
,
10113 const struct intel_encoder
*b
)
10115 /* masks could be asymmetric, so check both ways */
10116 return a
== b
|| (a
->cloneable
& (1 << b
->type
) &&
10117 b
->cloneable
& (1 << a
->type
));
10120 static bool check_single_encoder_cloning(struct intel_crtc
*crtc
,
10121 struct intel_encoder
*encoder
)
10123 struct drm_device
*dev
= crtc
->base
.dev
;
10124 struct intel_encoder
*source_encoder
;
10126 for_each_intel_encoder(dev
, source_encoder
) {
10127 if (source_encoder
->new_crtc
!= crtc
)
10130 if (!encoders_cloneable(encoder
, source_encoder
))
10137 static bool check_encoder_cloning(struct intel_crtc
*crtc
)
10139 struct drm_device
*dev
= crtc
->base
.dev
;
10140 struct intel_encoder
*encoder
;
10142 for_each_intel_encoder(dev
, encoder
) {
10143 if (encoder
->new_crtc
!= crtc
)
10146 if (!check_single_encoder_cloning(crtc
, encoder
))
10153 static bool check_digital_port_conflicts(struct drm_device
*dev
)
10155 struct intel_connector
*connector
;
10156 unsigned int used_ports
= 0;
10159 * Walk the connector list instead of the encoder
10160 * list to detect the problem on ddi platforms
10161 * where there's just one encoder per digital port.
10163 list_for_each_entry(connector
,
10164 &dev
->mode_config
.connector_list
, base
.head
) {
10165 struct intel_encoder
*encoder
= connector
->new_encoder
;
10170 WARN_ON(!encoder
->new_crtc
);
10172 switch (encoder
->type
) {
10173 unsigned int port_mask
;
10174 case INTEL_OUTPUT_UNKNOWN
:
10175 if (WARN_ON(!HAS_DDI(dev
)))
10177 case INTEL_OUTPUT_DISPLAYPORT
:
10178 case INTEL_OUTPUT_HDMI
:
10179 case INTEL_OUTPUT_EDP
:
10180 port_mask
= 1 << enc_to_dig_port(&encoder
->base
)->port
;
10182 /* the same port mustn't appear more than once */
10183 if (used_ports
& port_mask
)
10186 used_ports
|= port_mask
;
10195 static struct intel_crtc_config
*
10196 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
10197 struct drm_framebuffer
*fb
,
10198 struct drm_display_mode
*mode
)
10200 struct drm_device
*dev
= crtc
->dev
;
10201 struct intel_encoder
*encoder
;
10202 struct intel_crtc_config
*pipe_config
;
10203 int plane_bpp
, ret
= -EINVAL
;
10206 if (!check_encoder_cloning(to_intel_crtc(crtc
))) {
10207 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10208 return ERR_PTR(-EINVAL
);
10211 if (!check_digital_port_conflicts(dev
)) {
10212 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
10213 return ERR_PTR(-EINVAL
);
10216 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
10218 return ERR_PTR(-ENOMEM
);
10220 drm_mode_copy(&pipe_config
->adjusted_mode
, mode
);
10221 drm_mode_copy(&pipe_config
->requested_mode
, mode
);
10223 pipe_config
->cpu_transcoder
=
10224 (enum transcoder
) to_intel_crtc(crtc
)->pipe
;
10225 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
10228 * Sanitize sync polarity flags based on requested ones. If neither
10229 * positive or negative polarity is requested, treat this as meaning
10230 * negative polarity.
10232 if (!(pipe_config
->adjusted_mode
.flags
&
10233 (DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NHSYNC
)))
10234 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
10236 if (!(pipe_config
->adjusted_mode
.flags
&
10237 (DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_NVSYNC
)))
10238 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
10240 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10241 * plane pixel format and any sink constraints into account. Returns the
10242 * source plane bpp so that dithering can be selected on mismatches
10243 * after encoders and crtc also have had their say. */
10244 plane_bpp
= compute_baseline_pipe_bpp(to_intel_crtc(crtc
),
10250 * Determine the real pipe dimensions. Note that stereo modes can
10251 * increase the actual pipe size due to the frame doubling and
10252 * insertion of additional space for blanks between the frame. This
10253 * is stored in the crtc timings. We use the requested mode to do this
10254 * computation to clearly distinguish it from the adjusted mode, which
10255 * can be changed by the connectors in the below retry loop.
10257 drm_mode_set_crtcinfo(&pipe_config
->requested_mode
, CRTC_STEREO_DOUBLE
);
10258 pipe_config
->pipe_src_w
= pipe_config
->requested_mode
.crtc_hdisplay
;
10259 pipe_config
->pipe_src_h
= pipe_config
->requested_mode
.crtc_vdisplay
;
10262 /* Ensure the port clock defaults are reset when retrying. */
10263 pipe_config
->port_clock
= 0;
10264 pipe_config
->pixel_multiplier
= 1;
10266 /* Fill in default crtc timings, allow encoders to overwrite them. */
10267 drm_mode_set_crtcinfo(&pipe_config
->adjusted_mode
, CRTC_STEREO_DOUBLE
);
10269 /* Pass our mode to the connectors and the CRTC to give them a chance to
10270 * adjust it according to limitations or connector properties, and also
10271 * a chance to reject the mode entirely.
10273 for_each_intel_encoder(dev
, encoder
) {
10275 if (&encoder
->new_crtc
->base
!= crtc
)
10278 if (!(encoder
->compute_config(encoder
, pipe_config
))) {
10279 DRM_DEBUG_KMS("Encoder config failure\n");
10284 /* Set default port clock if not overwritten by the encoder. Needs to be
10285 * done afterwards in case the encoder adjusts the mode. */
10286 if (!pipe_config
->port_clock
)
10287 pipe_config
->port_clock
= pipe_config
->adjusted_mode
.crtc_clock
10288 * pipe_config
->pixel_multiplier
;
10290 ret
= intel_crtc_compute_config(to_intel_crtc(crtc
), pipe_config
);
10292 DRM_DEBUG_KMS("CRTC fixup failed\n");
10296 if (ret
== RETRY
) {
10297 if (WARN(!retry
, "loop in pipe configuration computation\n")) {
10302 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10304 goto encoder_retry
;
10307 pipe_config
->dither
= pipe_config
->pipe_bpp
!= plane_bpp
;
10308 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10309 plane_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
10311 return pipe_config
;
10313 kfree(pipe_config
);
10314 return ERR_PTR(ret
);
10317 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10318 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10320 intel_modeset_affected_pipes(struct drm_crtc
*crtc
, unsigned *modeset_pipes
,
10321 unsigned *prepare_pipes
, unsigned *disable_pipes
)
10323 struct intel_crtc
*intel_crtc
;
10324 struct drm_device
*dev
= crtc
->dev
;
10325 struct intel_encoder
*encoder
;
10326 struct intel_connector
*connector
;
10327 struct drm_crtc
*tmp_crtc
;
10329 *disable_pipes
= *modeset_pipes
= *prepare_pipes
= 0;
10331 /* Check which crtcs have changed outputs connected to them, these need
10332 * to be part of the prepare_pipes mask. We don't (yet) support global
10333 * modeset across multiple crtcs, so modeset_pipes will only have one
10334 * bit set at most. */
10335 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10337 if (connector
->base
.encoder
== &connector
->new_encoder
->base
)
10340 if (connector
->base
.encoder
) {
10341 tmp_crtc
= connector
->base
.encoder
->crtc
;
10343 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
10346 if (connector
->new_encoder
)
10348 1 << connector
->new_encoder
->new_crtc
->pipe
;
10351 for_each_intel_encoder(dev
, encoder
) {
10352 if (encoder
->base
.crtc
== &encoder
->new_crtc
->base
)
10355 if (encoder
->base
.crtc
) {
10356 tmp_crtc
= encoder
->base
.crtc
;
10358 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
10361 if (encoder
->new_crtc
)
10362 *prepare_pipes
|= 1 << encoder
->new_crtc
->pipe
;
10365 /* Check for pipes that will be enabled/disabled ... */
10366 for_each_intel_crtc(dev
, intel_crtc
) {
10367 if (intel_crtc
->base
.enabled
== intel_crtc
->new_enabled
)
10370 if (!intel_crtc
->new_enabled
)
10371 *disable_pipes
|= 1 << intel_crtc
->pipe
;
10373 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
10377 /* set_mode is also used to update properties on life display pipes. */
10378 intel_crtc
= to_intel_crtc(crtc
);
10379 if (intel_crtc
->new_enabled
)
10380 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
10383 * For simplicity do a full modeset on any pipe where the output routing
10384 * changed. We could be more clever, but that would require us to be
10385 * more careful with calling the relevant encoder->mode_set functions.
10387 if (*prepare_pipes
)
10388 *modeset_pipes
= *prepare_pipes
;
10390 /* ... and mask these out. */
10391 *modeset_pipes
&= ~(*disable_pipes
);
10392 *prepare_pipes
&= ~(*disable_pipes
);
10395 * HACK: We don't (yet) fully support global modesets. intel_set_config
10396 * obies this rule, but the modeset restore mode of
10397 * intel_modeset_setup_hw_state does not.
10399 *modeset_pipes
&= 1 << intel_crtc
->pipe
;
10400 *prepare_pipes
&= 1 << intel_crtc
->pipe
;
10402 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10403 *modeset_pipes
, *prepare_pipes
, *disable_pipes
);
10406 static bool intel_crtc_in_use(struct drm_crtc
*crtc
)
10408 struct drm_encoder
*encoder
;
10409 struct drm_device
*dev
= crtc
->dev
;
10411 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
)
10412 if (encoder
->crtc
== crtc
)
10419 intel_modeset_update_state(struct drm_device
*dev
, unsigned prepare_pipes
)
10421 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10422 struct intel_encoder
*intel_encoder
;
10423 struct intel_crtc
*intel_crtc
;
10424 struct drm_connector
*connector
;
10426 intel_shared_dpll_commit(dev_priv
);
10428 for_each_intel_encoder(dev
, intel_encoder
) {
10429 if (!intel_encoder
->base
.crtc
)
10432 intel_crtc
= to_intel_crtc(intel_encoder
->base
.crtc
);
10434 if (prepare_pipes
& (1 << intel_crtc
->pipe
))
10435 intel_encoder
->connectors_active
= false;
10438 intel_modeset_commit_output_state(dev
);
10440 /* Double check state. */
10441 for_each_intel_crtc(dev
, intel_crtc
) {
10442 WARN_ON(intel_crtc
->base
.enabled
!= intel_crtc_in_use(&intel_crtc
->base
));
10443 WARN_ON(intel_crtc
->new_config
&&
10444 intel_crtc
->new_config
!= &intel_crtc
->config
);
10445 WARN_ON(intel_crtc
->base
.enabled
!= !!intel_crtc
->new_config
);
10448 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
10449 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
10452 intel_crtc
= to_intel_crtc(connector
->encoder
->crtc
);
10454 if (prepare_pipes
& (1 << intel_crtc
->pipe
)) {
10455 struct drm_property
*dpms_property
=
10456 dev
->mode_config
.dpms_property
;
10458 connector
->dpms
= DRM_MODE_DPMS_ON
;
10459 drm_object_property_set_value(&connector
->base
,
10463 intel_encoder
= to_intel_encoder(connector
->encoder
);
10464 intel_encoder
->connectors_active
= true;
10470 static bool intel_fuzzy_clock_check(int clock1
, int clock2
)
10474 if (clock1
== clock2
)
10477 if (!clock1
|| !clock2
)
10480 diff
= abs(clock1
- clock2
);
10482 if (((((diff
+ clock1
+ clock2
) * 100)) / (clock1
+ clock2
)) < 105)
10488 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10489 list_for_each_entry((intel_crtc), \
10490 &(dev)->mode_config.crtc_list, \
10492 if (mask & (1 <<(intel_crtc)->pipe))
10495 intel_pipe_config_compare(struct drm_device
*dev
,
10496 struct intel_crtc_config
*current_config
,
10497 struct intel_crtc_config
*pipe_config
)
10499 #define PIPE_CONF_CHECK_X(name) \
10500 if (current_config->name != pipe_config->name) { \
10501 DRM_ERROR("mismatch in " #name " " \
10502 "(expected 0x%08x, found 0x%08x)\n", \
10503 current_config->name, \
10504 pipe_config->name); \
10508 #define PIPE_CONF_CHECK_I(name) \
10509 if (current_config->name != pipe_config->name) { \
10510 DRM_ERROR("mismatch in " #name " " \
10511 "(expected %i, found %i)\n", \
10512 current_config->name, \
10513 pipe_config->name); \
10517 /* This is required for BDW+ where there is only one set of registers for
10518 * switching between high and low RR.
10519 * This macro can be used whenever a comparison has to be made between one
10520 * hw state and multiple sw state variables.
10522 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10523 if ((current_config->name != pipe_config->name) && \
10524 (current_config->alt_name != pipe_config->name)) { \
10525 DRM_ERROR("mismatch in " #name " " \
10526 "(expected %i or %i, found %i)\n", \
10527 current_config->name, \
10528 current_config->alt_name, \
10529 pipe_config->name); \
10533 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10534 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10535 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10536 "(expected %i, found %i)\n", \
10537 current_config->name & (mask), \
10538 pipe_config->name & (mask)); \
10542 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10543 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10544 DRM_ERROR("mismatch in " #name " " \
10545 "(expected %i, found %i)\n", \
10546 current_config->name, \
10547 pipe_config->name); \
10551 #define PIPE_CONF_QUIRK(quirk) \
10552 ((current_config->quirks | pipe_config->quirks) & (quirk))
10554 PIPE_CONF_CHECK_I(cpu_transcoder
);
10556 PIPE_CONF_CHECK_I(has_pch_encoder
);
10557 PIPE_CONF_CHECK_I(fdi_lanes
);
10558 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_m
);
10559 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_n
);
10560 PIPE_CONF_CHECK_I(fdi_m_n
.link_m
);
10561 PIPE_CONF_CHECK_I(fdi_m_n
.link_n
);
10562 PIPE_CONF_CHECK_I(fdi_m_n
.tu
);
10564 PIPE_CONF_CHECK_I(has_dp_encoder
);
10566 if (INTEL_INFO(dev
)->gen
< 8) {
10567 PIPE_CONF_CHECK_I(dp_m_n
.gmch_m
);
10568 PIPE_CONF_CHECK_I(dp_m_n
.gmch_n
);
10569 PIPE_CONF_CHECK_I(dp_m_n
.link_m
);
10570 PIPE_CONF_CHECK_I(dp_m_n
.link_n
);
10571 PIPE_CONF_CHECK_I(dp_m_n
.tu
);
10573 if (current_config
->has_drrs
) {
10574 PIPE_CONF_CHECK_I(dp_m2_n2
.gmch_m
);
10575 PIPE_CONF_CHECK_I(dp_m2_n2
.gmch_n
);
10576 PIPE_CONF_CHECK_I(dp_m2_n2
.link_m
);
10577 PIPE_CONF_CHECK_I(dp_m2_n2
.link_n
);
10578 PIPE_CONF_CHECK_I(dp_m2_n2
.tu
);
10581 PIPE_CONF_CHECK_I_ALT(dp_m_n
.gmch_m
, dp_m2_n2
.gmch_m
);
10582 PIPE_CONF_CHECK_I_ALT(dp_m_n
.gmch_n
, dp_m2_n2
.gmch_n
);
10583 PIPE_CONF_CHECK_I_ALT(dp_m_n
.link_m
, dp_m2_n2
.link_m
);
10584 PIPE_CONF_CHECK_I_ALT(dp_m_n
.link_n
, dp_m2_n2
.link_n
);
10585 PIPE_CONF_CHECK_I_ALT(dp_m_n
.tu
, dp_m2_n2
.tu
);
10588 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hdisplay
);
10589 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_htotal
);
10590 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hblank_start
);
10591 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hblank_end
);
10592 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hsync_start
);
10593 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hsync_end
);
10595 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vdisplay
);
10596 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vtotal
);
10597 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vblank_start
);
10598 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vblank_end
);
10599 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vsync_start
);
10600 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vsync_end
);
10602 PIPE_CONF_CHECK_I(pixel_multiplier
);
10603 PIPE_CONF_CHECK_I(has_hdmi_sink
);
10604 if ((INTEL_INFO(dev
)->gen
< 8 && !IS_HASWELL(dev
)) ||
10605 IS_VALLEYVIEW(dev
))
10606 PIPE_CONF_CHECK_I(limited_color_range
);
10607 PIPE_CONF_CHECK_I(has_infoframe
);
10609 PIPE_CONF_CHECK_I(has_audio
);
10611 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10612 DRM_MODE_FLAG_INTERLACE
);
10614 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
10615 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10616 DRM_MODE_FLAG_PHSYNC
);
10617 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10618 DRM_MODE_FLAG_NHSYNC
);
10619 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10620 DRM_MODE_FLAG_PVSYNC
);
10621 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10622 DRM_MODE_FLAG_NVSYNC
);
10625 PIPE_CONF_CHECK_I(pipe_src_w
);
10626 PIPE_CONF_CHECK_I(pipe_src_h
);
10629 * FIXME: BIOS likes to set up a cloned config with lvds+external
10630 * screen. Since we don't yet re-compute the pipe config when moving
10631 * just the lvds port away to another pipe the sw tracking won't match.
10633 * Proper atomic modesets with recomputed global state will fix this.
10634 * Until then just don't check gmch state for inherited modes.
10636 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE
)) {
10637 PIPE_CONF_CHECK_I(gmch_pfit
.control
);
10638 /* pfit ratios are autocomputed by the hw on gen4+ */
10639 if (INTEL_INFO(dev
)->gen
< 4)
10640 PIPE_CONF_CHECK_I(gmch_pfit
.pgm_ratios
);
10641 PIPE_CONF_CHECK_I(gmch_pfit
.lvds_border_bits
);
10644 PIPE_CONF_CHECK_I(pch_pfit
.enabled
);
10645 if (current_config
->pch_pfit
.enabled
) {
10646 PIPE_CONF_CHECK_I(pch_pfit
.pos
);
10647 PIPE_CONF_CHECK_I(pch_pfit
.size
);
10650 /* BDW+ don't expose a synchronous way to read the state */
10651 if (IS_HASWELL(dev
))
10652 PIPE_CONF_CHECK_I(ips_enabled
);
10654 PIPE_CONF_CHECK_I(double_wide
);
10656 PIPE_CONF_CHECK_X(ddi_pll_sel
);
10658 PIPE_CONF_CHECK_I(shared_dpll
);
10659 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll
);
10660 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll_md
);
10661 PIPE_CONF_CHECK_X(dpll_hw_state
.fp0
);
10662 PIPE_CONF_CHECK_X(dpll_hw_state
.fp1
);
10663 PIPE_CONF_CHECK_X(dpll_hw_state
.wrpll
);
10664 PIPE_CONF_CHECK_X(dpll_hw_state
.ctrl1
);
10665 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr1
);
10666 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr2
);
10668 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5)
10669 PIPE_CONF_CHECK_I(pipe_bpp
);
10671 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode
.crtc_clock
);
10672 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock
);
10674 #undef PIPE_CONF_CHECK_X
10675 #undef PIPE_CONF_CHECK_I
10676 #undef PIPE_CONF_CHECK_I_ALT
10677 #undef PIPE_CONF_CHECK_FLAGS
10678 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10679 #undef PIPE_CONF_QUIRK
10684 static void check_wm_state(struct drm_device
*dev
)
10686 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10687 struct skl_ddb_allocation hw_ddb
, *sw_ddb
;
10688 struct intel_crtc
*intel_crtc
;
10691 if (INTEL_INFO(dev
)->gen
< 9)
10694 skl_ddb_get_hw_state(dev_priv
, &hw_ddb
);
10695 sw_ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
10697 for_each_intel_crtc(dev
, intel_crtc
) {
10698 struct skl_ddb_entry
*hw_entry
, *sw_entry
;
10699 const enum pipe pipe
= intel_crtc
->pipe
;
10701 if (!intel_crtc
->active
)
10705 for_each_plane(pipe
, plane
) {
10706 hw_entry
= &hw_ddb
.plane
[pipe
][plane
];
10707 sw_entry
= &sw_ddb
->plane
[pipe
][plane
];
10709 if (skl_ddb_entry_equal(hw_entry
, sw_entry
))
10712 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
10713 "(expected (%u,%u), found (%u,%u))\n",
10714 pipe_name(pipe
), plane
+ 1,
10715 sw_entry
->start
, sw_entry
->end
,
10716 hw_entry
->start
, hw_entry
->end
);
10720 hw_entry
= &hw_ddb
.cursor
[pipe
];
10721 sw_entry
= &sw_ddb
->cursor
[pipe
];
10723 if (skl_ddb_entry_equal(hw_entry
, sw_entry
))
10726 DRM_ERROR("mismatch in DDB state pipe %c cursor "
10727 "(expected (%u,%u), found (%u,%u))\n",
10729 sw_entry
->start
, sw_entry
->end
,
10730 hw_entry
->start
, hw_entry
->end
);
10735 check_connector_state(struct drm_device
*dev
)
10737 struct intel_connector
*connector
;
10739 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10741 /* This also checks the encoder/connector hw state with the
10742 * ->get_hw_state callbacks. */
10743 intel_connector_check_state(connector
);
10745 WARN(&connector
->new_encoder
->base
!= connector
->base
.encoder
,
10746 "connector's staged encoder doesn't match current encoder\n");
10751 check_encoder_state(struct drm_device
*dev
)
10753 struct intel_encoder
*encoder
;
10754 struct intel_connector
*connector
;
10756 for_each_intel_encoder(dev
, encoder
) {
10757 bool enabled
= false;
10758 bool active
= false;
10759 enum pipe pipe
, tracked_pipe
;
10761 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10762 encoder
->base
.base
.id
,
10763 encoder
->base
.name
);
10765 WARN(&encoder
->new_crtc
->base
!= encoder
->base
.crtc
,
10766 "encoder's stage crtc doesn't match current crtc\n");
10767 WARN(encoder
->connectors_active
&& !encoder
->base
.crtc
,
10768 "encoder's active_connectors set, but no crtc\n");
10770 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10772 if (connector
->base
.encoder
!= &encoder
->base
)
10775 if (connector
->base
.dpms
!= DRM_MODE_DPMS_OFF
)
10779 * for MST connectors if we unplug the connector is gone
10780 * away but the encoder is still connected to a crtc
10781 * until a modeset happens in response to the hotplug.
10783 if (!enabled
&& encoder
->base
.encoder_type
== DRM_MODE_ENCODER_DPMST
)
10786 WARN(!!encoder
->base
.crtc
!= enabled
,
10787 "encoder's enabled state mismatch "
10788 "(expected %i, found %i)\n",
10789 !!encoder
->base
.crtc
, enabled
);
10790 WARN(active
&& !encoder
->base
.crtc
,
10791 "active encoder with no crtc\n");
10793 WARN(encoder
->connectors_active
!= active
,
10794 "encoder's computed active state doesn't match tracked active state "
10795 "(expected %i, found %i)\n", active
, encoder
->connectors_active
);
10797 active
= encoder
->get_hw_state(encoder
, &pipe
);
10798 WARN(active
!= encoder
->connectors_active
,
10799 "encoder's hw state doesn't match sw tracking "
10800 "(expected %i, found %i)\n",
10801 encoder
->connectors_active
, active
);
10803 if (!encoder
->base
.crtc
)
10806 tracked_pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
10807 WARN(active
&& pipe
!= tracked_pipe
,
10808 "active encoder's pipe doesn't match"
10809 "(expected %i, found %i)\n",
10810 tracked_pipe
, pipe
);
10816 check_crtc_state(struct drm_device
*dev
)
10818 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10819 struct intel_crtc
*crtc
;
10820 struct intel_encoder
*encoder
;
10821 struct intel_crtc_config pipe_config
;
10823 for_each_intel_crtc(dev
, crtc
) {
10824 bool enabled
= false;
10825 bool active
= false;
10827 memset(&pipe_config
, 0, sizeof(pipe_config
));
10829 DRM_DEBUG_KMS("[CRTC:%d]\n",
10830 crtc
->base
.base
.id
);
10832 WARN(crtc
->active
&& !crtc
->base
.enabled
,
10833 "active crtc, but not enabled in sw tracking\n");
10835 for_each_intel_encoder(dev
, encoder
) {
10836 if (encoder
->base
.crtc
!= &crtc
->base
)
10839 if (encoder
->connectors_active
)
10843 WARN(active
!= crtc
->active
,
10844 "crtc's computed active state doesn't match tracked active state "
10845 "(expected %i, found %i)\n", active
, crtc
->active
);
10846 WARN(enabled
!= crtc
->base
.enabled
,
10847 "crtc's computed enabled state doesn't match tracked enabled state "
10848 "(expected %i, found %i)\n", enabled
, crtc
->base
.enabled
);
10850 active
= dev_priv
->display
.get_pipe_config(crtc
,
10853 /* hw state is inconsistent with the pipe quirk */
10854 if ((crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
10855 (crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
10856 active
= crtc
->active
;
10858 for_each_intel_encoder(dev
, encoder
) {
10860 if (encoder
->base
.crtc
!= &crtc
->base
)
10862 if (encoder
->get_hw_state(encoder
, &pipe
))
10863 encoder
->get_config(encoder
, &pipe_config
);
10866 WARN(crtc
->active
!= active
,
10867 "crtc active state doesn't match with hw state "
10868 "(expected %i, found %i)\n", crtc
->active
, active
);
10871 !intel_pipe_config_compare(dev
, &crtc
->config
, &pipe_config
)) {
10872 WARN(1, "pipe state doesn't match!\n");
10873 intel_dump_pipe_config(crtc
, &pipe_config
,
10875 intel_dump_pipe_config(crtc
, &crtc
->config
,
10882 check_shared_dpll_state(struct drm_device
*dev
)
10884 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10885 struct intel_crtc
*crtc
;
10886 struct intel_dpll_hw_state dpll_hw_state
;
10889 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
10890 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
10891 int enabled_crtcs
= 0, active_crtcs
= 0;
10894 memset(&dpll_hw_state
, 0, sizeof(dpll_hw_state
));
10896 DRM_DEBUG_KMS("%s\n", pll
->name
);
10898 active
= pll
->get_hw_state(dev_priv
, pll
, &dpll_hw_state
);
10900 WARN(pll
->active
> hweight32(pll
->config
.crtc_mask
),
10901 "more active pll users than references: %i vs %i\n",
10902 pll
->active
, hweight32(pll
->config
.crtc_mask
));
10903 WARN(pll
->active
&& !pll
->on
,
10904 "pll in active use but not on in sw tracking\n");
10905 WARN(pll
->on
&& !pll
->active
,
10906 "pll in on but not on in use in sw tracking\n");
10907 WARN(pll
->on
!= active
,
10908 "pll on state mismatch (expected %i, found %i)\n",
10911 for_each_intel_crtc(dev
, crtc
) {
10912 if (crtc
->base
.enabled
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
10914 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
10917 WARN(pll
->active
!= active_crtcs
,
10918 "pll active crtcs mismatch (expected %i, found %i)\n",
10919 pll
->active
, active_crtcs
);
10920 WARN(hweight32(pll
->config
.crtc_mask
) != enabled_crtcs
,
10921 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10922 hweight32(pll
->config
.crtc_mask
), enabled_crtcs
);
10924 WARN(pll
->on
&& memcmp(&pll
->config
.hw_state
, &dpll_hw_state
,
10925 sizeof(dpll_hw_state
)),
10926 "pll hw state mismatch\n");
10931 intel_modeset_check_state(struct drm_device
*dev
)
10933 check_wm_state(dev
);
10934 check_connector_state(dev
);
10935 check_encoder_state(dev
);
10936 check_crtc_state(dev
);
10937 check_shared_dpll_state(dev
);
10940 void ironlake_check_encoder_dotclock(const struct intel_crtc_config
*pipe_config
,
10944 * FDI already provided one idea for the dotclock.
10945 * Yell if the encoder disagrees.
10947 WARN(!intel_fuzzy_clock_check(pipe_config
->adjusted_mode
.crtc_clock
, dotclock
),
10948 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10949 pipe_config
->adjusted_mode
.crtc_clock
, dotclock
);
10952 static void update_scanline_offset(struct intel_crtc
*crtc
)
10954 struct drm_device
*dev
= crtc
->base
.dev
;
10957 * The scanline counter increments at the leading edge of hsync.
10959 * On most platforms it starts counting from vtotal-1 on the
10960 * first active line. That means the scanline counter value is
10961 * always one less than what we would expect. Ie. just after
10962 * start of vblank, which also occurs at start of hsync (on the
10963 * last active line), the scanline counter will read vblank_start-1.
10965 * On gen2 the scanline counter starts counting from 1 instead
10966 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10967 * to keep the value positive), instead of adding one.
10969 * On HSW+ the behaviour of the scanline counter depends on the output
10970 * type. For DP ports it behaves like most other platforms, but on HDMI
10971 * there's an extra 1 line difference. So we need to add two instead of
10972 * one to the value.
10974 if (IS_GEN2(dev
)) {
10975 const struct drm_display_mode
*mode
= &crtc
->config
.adjusted_mode
;
10978 vtotal
= mode
->crtc_vtotal
;
10979 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
10982 crtc
->scanline_offset
= vtotal
- 1;
10983 } else if (HAS_DDI(dev
) &&
10984 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
)) {
10985 crtc
->scanline_offset
= 2;
10987 crtc
->scanline_offset
= 1;
10990 static struct intel_crtc_config
*
10991 intel_modeset_compute_config(struct drm_crtc
*crtc
,
10992 struct drm_display_mode
*mode
,
10993 struct drm_framebuffer
*fb
,
10994 unsigned *modeset_pipes
,
10995 unsigned *prepare_pipes
,
10996 unsigned *disable_pipes
)
10998 struct intel_crtc_config
*pipe_config
= NULL
;
11000 intel_modeset_affected_pipes(crtc
, modeset_pipes
,
11001 prepare_pipes
, disable_pipes
);
11003 if ((*modeset_pipes
) == 0)
11007 * Note this needs changes when we start tracking multiple modes
11008 * and crtcs. At that point we'll need to compute the whole config
11009 * (i.e. one pipe_config for each crtc) rather than just the one
11012 pipe_config
= intel_modeset_pipe_config(crtc
, fb
, mode
);
11013 if (IS_ERR(pipe_config
)) {
11016 intel_dump_pipe_config(to_intel_crtc(crtc
), pipe_config
,
11020 return pipe_config
;
11023 static int __intel_set_mode(struct drm_crtc
*crtc
,
11024 struct drm_display_mode
*mode
,
11025 int x
, int y
, struct drm_framebuffer
*fb
,
11026 struct intel_crtc_config
*pipe_config
,
11027 unsigned modeset_pipes
,
11028 unsigned prepare_pipes
,
11029 unsigned disable_pipes
)
11031 struct drm_device
*dev
= crtc
->dev
;
11032 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11033 struct drm_display_mode
*saved_mode
;
11034 struct intel_crtc
*intel_crtc
;
11037 saved_mode
= kmalloc(sizeof(*saved_mode
), GFP_KERNEL
);
11041 *saved_mode
= crtc
->mode
;
11044 to_intel_crtc(crtc
)->new_config
= pipe_config
;
11047 * See if the config requires any additional preparation, e.g.
11048 * to adjust global state with pipes off. We need to do this
11049 * here so we can get the modeset_pipe updated config for the new
11050 * mode set on this crtc. For other crtcs we need to use the
11051 * adjusted_mode bits in the crtc directly.
11053 if (IS_VALLEYVIEW(dev
)) {
11054 valleyview_modeset_global_pipes(dev
, &prepare_pipes
);
11056 /* may have added more to prepare_pipes than we should */
11057 prepare_pipes
&= ~disable_pipes
;
11060 if (dev_priv
->display
.crtc_compute_clock
) {
11061 unsigned clear_pipes
= modeset_pipes
| disable_pipes
;
11063 ret
= intel_shared_dpll_start_config(dev_priv
, clear_pipes
);
11067 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
11068 ret
= dev_priv
->display
.crtc_compute_clock(intel_crtc
);
11070 intel_shared_dpll_abort_config(dev_priv
);
11076 for_each_intel_crtc_masked(dev
, disable_pipes
, intel_crtc
)
11077 intel_crtc_disable(&intel_crtc
->base
);
11079 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
11080 if (intel_crtc
->base
.enabled
)
11081 dev_priv
->display
.crtc_disable(&intel_crtc
->base
);
11084 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11085 * to set it here already despite that we pass it down the callchain.
11087 * Note we'll need to fix this up when we start tracking multiple
11088 * pipes; here we assume a single modeset_pipe and only track the
11089 * single crtc and mode.
11091 if (modeset_pipes
) {
11092 crtc
->mode
= *mode
;
11093 /* mode_set/enable/disable functions rely on a correct pipe
11095 to_intel_crtc(crtc
)->config
= *pipe_config
;
11096 to_intel_crtc(crtc
)->new_config
= &to_intel_crtc(crtc
)->config
;
11099 * Calculate and store various constants which
11100 * are later needed by vblank and swap-completion
11101 * timestamping. They are derived from true hwmode.
11103 drm_calc_timestamping_constants(crtc
,
11104 &pipe_config
->adjusted_mode
);
11107 /* Only after disabling all output pipelines that will be changed can we
11108 * update the the output configuration. */
11109 intel_modeset_update_state(dev
, prepare_pipes
);
11111 modeset_update_crtc_power_domains(dev
);
11113 /* Set up the DPLL and any encoders state that needs to adjust or depend
11116 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
11117 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
11118 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(old_fb
);
11119 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
11121 mutex_lock(&dev
->struct_mutex
);
11122 ret
= intel_pin_and_fence_fb_obj(crtc
->primary
, fb
, NULL
);
11124 DRM_ERROR("pin & fence failed\n");
11125 mutex_unlock(&dev
->struct_mutex
);
11129 intel_unpin_fb_obj(old_obj
);
11130 i915_gem_track_fb(old_obj
, obj
,
11131 INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
));
11132 mutex_unlock(&dev
->struct_mutex
);
11134 crtc
->primary
->fb
= fb
;
11139 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11140 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
11141 update_scanline_offset(intel_crtc
);
11143 dev_priv
->display
.crtc_enable(&intel_crtc
->base
);
11146 /* FIXME: add subpixel order */
11148 if (ret
&& crtc
->enabled
)
11149 crtc
->mode
= *saved_mode
;
11151 kfree(pipe_config
);
11156 static int intel_set_mode_pipes(struct drm_crtc
*crtc
,
11157 struct drm_display_mode
*mode
,
11158 int x
, int y
, struct drm_framebuffer
*fb
,
11159 struct intel_crtc_config
*pipe_config
,
11160 unsigned modeset_pipes
,
11161 unsigned prepare_pipes
,
11162 unsigned disable_pipes
)
11166 ret
= __intel_set_mode(crtc
, mode
, x
, y
, fb
, pipe_config
, modeset_pipes
,
11167 prepare_pipes
, disable_pipes
);
11170 intel_modeset_check_state(crtc
->dev
);
11175 static int intel_set_mode(struct drm_crtc
*crtc
,
11176 struct drm_display_mode
*mode
,
11177 int x
, int y
, struct drm_framebuffer
*fb
)
11179 struct intel_crtc_config
*pipe_config
;
11180 unsigned modeset_pipes
, prepare_pipes
, disable_pipes
;
11182 pipe_config
= intel_modeset_compute_config(crtc
, mode
, fb
,
11187 if (IS_ERR(pipe_config
))
11188 return PTR_ERR(pipe_config
);
11190 return intel_set_mode_pipes(crtc
, mode
, x
, y
, fb
, pipe_config
,
11191 modeset_pipes
, prepare_pipes
,
11195 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
11197 intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
, crtc
->primary
->fb
);
11200 #undef for_each_intel_crtc_masked
11202 static void intel_set_config_free(struct intel_set_config
*config
)
11207 kfree(config
->save_connector_encoders
);
11208 kfree(config
->save_encoder_crtcs
);
11209 kfree(config
->save_crtc_enabled
);
11213 static int intel_set_config_save_state(struct drm_device
*dev
,
11214 struct intel_set_config
*config
)
11216 struct drm_crtc
*crtc
;
11217 struct drm_encoder
*encoder
;
11218 struct drm_connector
*connector
;
11221 config
->save_crtc_enabled
=
11222 kcalloc(dev
->mode_config
.num_crtc
,
11223 sizeof(bool), GFP_KERNEL
);
11224 if (!config
->save_crtc_enabled
)
11227 config
->save_encoder_crtcs
=
11228 kcalloc(dev
->mode_config
.num_encoder
,
11229 sizeof(struct drm_crtc
*), GFP_KERNEL
);
11230 if (!config
->save_encoder_crtcs
)
11233 config
->save_connector_encoders
=
11234 kcalloc(dev
->mode_config
.num_connector
,
11235 sizeof(struct drm_encoder
*), GFP_KERNEL
);
11236 if (!config
->save_connector_encoders
)
11239 /* Copy data. Note that driver private data is not affected.
11240 * Should anything bad happen only the expected state is
11241 * restored, not the drivers personal bookkeeping.
11244 for_each_crtc(dev
, crtc
) {
11245 config
->save_crtc_enabled
[count
++] = crtc
->enabled
;
11249 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
11250 config
->save_encoder_crtcs
[count
++] = encoder
->crtc
;
11254 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
11255 config
->save_connector_encoders
[count
++] = connector
->encoder
;
11261 static void intel_set_config_restore_state(struct drm_device
*dev
,
11262 struct intel_set_config
*config
)
11264 struct intel_crtc
*crtc
;
11265 struct intel_encoder
*encoder
;
11266 struct intel_connector
*connector
;
11270 for_each_intel_crtc(dev
, crtc
) {
11271 crtc
->new_enabled
= config
->save_crtc_enabled
[count
++];
11273 if (crtc
->new_enabled
)
11274 crtc
->new_config
= &crtc
->config
;
11276 crtc
->new_config
= NULL
;
11280 for_each_intel_encoder(dev
, encoder
) {
11281 encoder
->new_crtc
=
11282 to_intel_crtc(config
->save_encoder_crtcs
[count
++]);
11286 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
11287 connector
->new_encoder
=
11288 to_intel_encoder(config
->save_connector_encoders
[count
++]);
11293 is_crtc_connector_off(struct drm_mode_set
*set
)
11297 if (set
->num_connectors
== 0)
11300 if (WARN_ON(set
->connectors
== NULL
))
11303 for (i
= 0; i
< set
->num_connectors
; i
++)
11304 if (set
->connectors
[i
]->encoder
&&
11305 set
->connectors
[i
]->encoder
->crtc
== set
->crtc
&&
11306 set
->connectors
[i
]->dpms
!= DRM_MODE_DPMS_ON
)
11313 intel_set_config_compute_mode_changes(struct drm_mode_set
*set
,
11314 struct intel_set_config
*config
)
11317 /* We should be able to check here if the fb has the same properties
11318 * and then just flip_or_move it */
11319 if (is_crtc_connector_off(set
)) {
11320 config
->mode_changed
= true;
11321 } else if (set
->crtc
->primary
->fb
!= set
->fb
) {
11323 * If we have no fb, we can only flip as long as the crtc is
11324 * active, otherwise we need a full mode set. The crtc may
11325 * be active if we've only disabled the primary plane, or
11326 * in fastboot situations.
11328 if (set
->crtc
->primary
->fb
== NULL
) {
11329 struct intel_crtc
*intel_crtc
=
11330 to_intel_crtc(set
->crtc
);
11332 if (intel_crtc
->active
) {
11333 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11334 config
->fb_changed
= true;
11336 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11337 config
->mode_changed
= true;
11339 } else if (set
->fb
== NULL
) {
11340 config
->mode_changed
= true;
11341 } else if (set
->fb
->pixel_format
!=
11342 set
->crtc
->primary
->fb
->pixel_format
) {
11343 config
->mode_changed
= true;
11345 config
->fb_changed
= true;
11349 if (set
->fb
&& (set
->x
!= set
->crtc
->x
|| set
->y
!= set
->crtc
->y
))
11350 config
->fb_changed
= true;
11352 if (set
->mode
&& !drm_mode_equal(set
->mode
, &set
->crtc
->mode
)) {
11353 DRM_DEBUG_KMS("modes are different, full mode set\n");
11354 drm_mode_debug_printmodeline(&set
->crtc
->mode
);
11355 drm_mode_debug_printmodeline(set
->mode
);
11356 config
->mode_changed
= true;
11359 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11360 set
->crtc
->base
.id
, config
->mode_changed
, config
->fb_changed
);
11364 intel_modeset_stage_output_state(struct drm_device
*dev
,
11365 struct drm_mode_set
*set
,
11366 struct intel_set_config
*config
)
11368 struct intel_connector
*connector
;
11369 struct intel_encoder
*encoder
;
11370 struct intel_crtc
*crtc
;
11373 /* The upper layers ensure that we either disable a crtc or have a list
11374 * of connectors. For paranoia, double-check this. */
11375 WARN_ON(!set
->fb
&& (set
->num_connectors
!= 0));
11376 WARN_ON(set
->fb
&& (set
->num_connectors
== 0));
11378 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
11380 /* Otherwise traverse passed in connector list and get encoders
11382 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
11383 if (set
->connectors
[ro
] == &connector
->base
) {
11384 connector
->new_encoder
= intel_find_encoder(connector
, to_intel_crtc(set
->crtc
)->pipe
);
11389 /* If we disable the crtc, disable all its connectors. Also, if
11390 * the connector is on the changing crtc but not on the new
11391 * connector list, disable it. */
11392 if ((!set
->fb
|| ro
== set
->num_connectors
) &&
11393 connector
->base
.encoder
&&
11394 connector
->base
.encoder
->crtc
== set
->crtc
) {
11395 connector
->new_encoder
= NULL
;
11397 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11398 connector
->base
.base
.id
,
11399 connector
->base
.name
);
11403 if (&connector
->new_encoder
->base
!= connector
->base
.encoder
) {
11404 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11405 config
->mode_changed
= true;
11408 /* connector->new_encoder is now updated for all connectors. */
11410 /* Update crtc of enabled connectors. */
11411 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
11413 struct drm_crtc
*new_crtc
;
11415 if (!connector
->new_encoder
)
11418 new_crtc
= connector
->new_encoder
->base
.crtc
;
11420 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
11421 if (set
->connectors
[ro
] == &connector
->base
)
11422 new_crtc
= set
->crtc
;
11425 /* Make sure the new CRTC will work with the encoder */
11426 if (!drm_encoder_crtc_ok(&connector
->new_encoder
->base
,
11430 connector
->new_encoder
->new_crtc
= to_intel_crtc(new_crtc
);
11432 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11433 connector
->base
.base
.id
,
11434 connector
->base
.name
,
11435 new_crtc
->base
.id
);
11438 /* Check for any encoders that needs to be disabled. */
11439 for_each_intel_encoder(dev
, encoder
) {
11440 int num_connectors
= 0;
11441 list_for_each_entry(connector
,
11442 &dev
->mode_config
.connector_list
,
11444 if (connector
->new_encoder
== encoder
) {
11445 WARN_ON(!connector
->new_encoder
->new_crtc
);
11450 if (num_connectors
== 0)
11451 encoder
->new_crtc
= NULL
;
11452 else if (num_connectors
> 1)
11455 /* Only now check for crtc changes so we don't miss encoders
11456 * that will be disabled. */
11457 if (&encoder
->new_crtc
->base
!= encoder
->base
.crtc
) {
11458 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11459 config
->mode_changed
= true;
11462 /* Now we've also updated encoder->new_crtc for all encoders. */
11463 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
11465 if (connector
->new_encoder
)
11466 if (connector
->new_encoder
!= connector
->encoder
)
11467 connector
->encoder
= connector
->new_encoder
;
11469 for_each_intel_crtc(dev
, crtc
) {
11470 crtc
->new_enabled
= false;
11472 for_each_intel_encoder(dev
, encoder
) {
11473 if (encoder
->new_crtc
== crtc
) {
11474 crtc
->new_enabled
= true;
11479 if (crtc
->new_enabled
!= crtc
->base
.enabled
) {
11480 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11481 crtc
->new_enabled
? "en" : "dis");
11482 config
->mode_changed
= true;
11485 if (crtc
->new_enabled
)
11486 crtc
->new_config
= &crtc
->config
;
11488 crtc
->new_config
= NULL
;
11494 static void disable_crtc_nofb(struct intel_crtc
*crtc
)
11496 struct drm_device
*dev
= crtc
->base
.dev
;
11497 struct intel_encoder
*encoder
;
11498 struct intel_connector
*connector
;
11500 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11501 pipe_name(crtc
->pipe
));
11503 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
11504 if (connector
->new_encoder
&&
11505 connector
->new_encoder
->new_crtc
== crtc
)
11506 connector
->new_encoder
= NULL
;
11509 for_each_intel_encoder(dev
, encoder
) {
11510 if (encoder
->new_crtc
== crtc
)
11511 encoder
->new_crtc
= NULL
;
11514 crtc
->new_enabled
= false;
11515 crtc
->new_config
= NULL
;
11518 static int intel_crtc_set_config(struct drm_mode_set
*set
)
11520 struct drm_device
*dev
;
11521 struct drm_mode_set save_set
;
11522 struct intel_set_config
*config
;
11523 struct intel_crtc_config
*pipe_config
;
11524 unsigned modeset_pipes
, prepare_pipes
, disable_pipes
;
11528 BUG_ON(!set
->crtc
);
11529 BUG_ON(!set
->crtc
->helper_private
);
11531 /* Enforce sane interface api - has been abused by the fb helper. */
11532 BUG_ON(!set
->mode
&& set
->fb
);
11533 BUG_ON(set
->fb
&& set
->num_connectors
== 0);
11536 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11537 set
->crtc
->base
.id
, set
->fb
->base
.id
,
11538 (int)set
->num_connectors
, set
->x
, set
->y
);
11540 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set
->crtc
->base
.id
);
11543 dev
= set
->crtc
->dev
;
11546 config
= kzalloc(sizeof(*config
), GFP_KERNEL
);
11550 ret
= intel_set_config_save_state(dev
, config
);
11554 save_set
.crtc
= set
->crtc
;
11555 save_set
.mode
= &set
->crtc
->mode
;
11556 save_set
.x
= set
->crtc
->x
;
11557 save_set
.y
= set
->crtc
->y
;
11558 save_set
.fb
= set
->crtc
->primary
->fb
;
11560 /* Compute whether we need a full modeset, only an fb base update or no
11561 * change at all. In the future we might also check whether only the
11562 * mode changed, e.g. for LVDS where we only change the panel fitter in
11564 intel_set_config_compute_mode_changes(set
, config
);
11566 ret
= intel_modeset_stage_output_state(dev
, set
, config
);
11570 pipe_config
= intel_modeset_compute_config(set
->crtc
, set
->mode
,
11575 if (IS_ERR(pipe_config
)) {
11576 ret
= PTR_ERR(pipe_config
);
11578 } else if (pipe_config
) {
11579 if (pipe_config
->has_audio
!=
11580 to_intel_crtc(set
->crtc
)->config
.has_audio
)
11581 config
->mode_changed
= true;
11584 * Note we have an issue here with infoframes: current code
11585 * only updates them on the full mode set path per hw
11586 * requirements. So here we should be checking for any
11587 * required changes and forcing a mode set.
11591 /* set_mode will free it in the mode_changed case */
11592 if (!config
->mode_changed
)
11593 kfree(pipe_config
);
11595 intel_update_pipe_size(to_intel_crtc(set
->crtc
));
11597 if (config
->mode_changed
) {
11598 ret
= intel_set_mode_pipes(set
->crtc
, set
->mode
,
11599 set
->x
, set
->y
, set
->fb
, pipe_config
,
11600 modeset_pipes
, prepare_pipes
,
11602 } else if (config
->fb_changed
) {
11603 struct intel_crtc
*intel_crtc
= to_intel_crtc(set
->crtc
);
11605 intel_crtc_wait_for_pending_flips(set
->crtc
);
11607 ret
= intel_pipe_set_base(set
->crtc
,
11608 set
->x
, set
->y
, set
->fb
);
11611 * We need to make sure the primary plane is re-enabled if it
11612 * has previously been turned off.
11614 if (!intel_crtc
->primary_enabled
&& ret
== 0) {
11615 WARN_ON(!intel_crtc
->active
);
11616 intel_enable_primary_hw_plane(set
->crtc
->primary
, set
->crtc
);
11620 * In the fastboot case this may be our only check of the
11621 * state after boot. It would be better to only do it on
11622 * the first update, but we don't have a nice way of doing that
11623 * (and really, set_config isn't used much for high freq page
11624 * flipping, so increasing its cost here shouldn't be a big
11627 if (i915
.fastboot
&& ret
== 0)
11628 intel_modeset_check_state(set
->crtc
->dev
);
11632 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11633 set
->crtc
->base
.id
, ret
);
11635 intel_set_config_restore_state(dev
, config
);
11638 * HACK: if the pipe was on, but we didn't have a framebuffer,
11639 * force the pipe off to avoid oopsing in the modeset code
11640 * due to fb==NULL. This should only happen during boot since
11641 * we don't yet reconstruct the FB from the hardware state.
11643 if (to_intel_crtc(save_set
.crtc
)->new_enabled
&& !save_set
.fb
)
11644 disable_crtc_nofb(to_intel_crtc(save_set
.crtc
));
11646 /* Try to restore the config */
11647 if (config
->mode_changed
&&
11648 intel_set_mode(save_set
.crtc
, save_set
.mode
,
11649 save_set
.x
, save_set
.y
, save_set
.fb
))
11650 DRM_ERROR("failed to restore config after modeset failure\n");
11654 intel_set_config_free(config
);
11658 static const struct drm_crtc_funcs intel_crtc_funcs
= {
11659 .gamma_set
= intel_crtc_gamma_set
,
11660 .set_config
= intel_crtc_set_config
,
11661 .destroy
= intel_crtc_destroy
,
11662 .page_flip
= intel_crtc_page_flip
,
11665 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private
*dev_priv
,
11666 struct intel_shared_dpll
*pll
,
11667 struct intel_dpll_hw_state
*hw_state
)
11671 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
11674 val
= I915_READ(PCH_DPLL(pll
->id
));
11675 hw_state
->dpll
= val
;
11676 hw_state
->fp0
= I915_READ(PCH_FP0(pll
->id
));
11677 hw_state
->fp1
= I915_READ(PCH_FP1(pll
->id
));
11679 return val
& DPLL_VCO_ENABLE
;
11682 static void ibx_pch_dpll_mode_set(struct drm_i915_private
*dev_priv
,
11683 struct intel_shared_dpll
*pll
)
11685 I915_WRITE(PCH_FP0(pll
->id
), pll
->config
.hw_state
.fp0
);
11686 I915_WRITE(PCH_FP1(pll
->id
), pll
->config
.hw_state
.fp1
);
11689 static void ibx_pch_dpll_enable(struct drm_i915_private
*dev_priv
,
11690 struct intel_shared_dpll
*pll
)
11692 /* PCH refclock must be enabled first */
11693 ibx_assert_pch_refclk_enabled(dev_priv
);
11695 I915_WRITE(PCH_DPLL(pll
->id
), pll
->config
.hw_state
.dpll
);
11697 /* Wait for the clocks to stabilize. */
11698 POSTING_READ(PCH_DPLL(pll
->id
));
11701 /* The pixel multiplier can only be updated once the
11702 * DPLL is enabled and the clocks are stable.
11704 * So write it again.
11706 I915_WRITE(PCH_DPLL(pll
->id
), pll
->config
.hw_state
.dpll
);
11707 POSTING_READ(PCH_DPLL(pll
->id
));
11711 static void ibx_pch_dpll_disable(struct drm_i915_private
*dev_priv
,
11712 struct intel_shared_dpll
*pll
)
11714 struct drm_device
*dev
= dev_priv
->dev
;
11715 struct intel_crtc
*crtc
;
11717 /* Make sure no transcoder isn't still depending on us. */
11718 for_each_intel_crtc(dev
, crtc
) {
11719 if (intel_crtc_to_shared_dpll(crtc
) == pll
)
11720 assert_pch_transcoder_disabled(dev_priv
, crtc
->pipe
);
11723 I915_WRITE(PCH_DPLL(pll
->id
), 0);
11724 POSTING_READ(PCH_DPLL(pll
->id
));
11728 static char *ibx_pch_dpll_names
[] = {
11733 static void ibx_pch_dpll_init(struct drm_device
*dev
)
11735 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11738 dev_priv
->num_shared_dpll
= 2;
11740 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
11741 dev_priv
->shared_dplls
[i
].id
= i
;
11742 dev_priv
->shared_dplls
[i
].name
= ibx_pch_dpll_names
[i
];
11743 dev_priv
->shared_dplls
[i
].mode_set
= ibx_pch_dpll_mode_set
;
11744 dev_priv
->shared_dplls
[i
].enable
= ibx_pch_dpll_enable
;
11745 dev_priv
->shared_dplls
[i
].disable
= ibx_pch_dpll_disable
;
11746 dev_priv
->shared_dplls
[i
].get_hw_state
=
11747 ibx_pch_dpll_get_hw_state
;
11751 static void intel_shared_dpll_init(struct drm_device
*dev
)
11753 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11756 intel_ddi_pll_init(dev
);
11757 else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
11758 ibx_pch_dpll_init(dev
);
11760 dev_priv
->num_shared_dpll
= 0;
11762 BUG_ON(dev_priv
->num_shared_dpll
> I915_NUM_PLLS
);
11766 intel_primary_plane_disable(struct drm_plane
*plane
)
11768 struct drm_device
*dev
= plane
->dev
;
11769 struct intel_crtc
*intel_crtc
;
11774 BUG_ON(!plane
->crtc
);
11776 intel_crtc
= to_intel_crtc(plane
->crtc
);
11779 * Even though we checked plane->fb above, it's still possible that
11780 * the primary plane has been implicitly disabled because the crtc
11781 * coordinates given weren't visible, or because we detected
11782 * that it was 100% covered by a sprite plane. Or, the CRTC may be
11783 * off and we've set a fb, but haven't actually turned on the CRTC yet.
11784 * In either case, we need to unpin the FB and let the fb pointer get
11785 * updated, but otherwise we don't need to touch the hardware.
11787 if (!intel_crtc
->primary_enabled
)
11788 goto disable_unpin
;
11790 intel_crtc_wait_for_pending_flips(plane
->crtc
);
11791 intel_disable_primary_hw_plane(plane
, plane
->crtc
);
11794 mutex_lock(&dev
->struct_mutex
);
11795 i915_gem_track_fb(intel_fb_obj(plane
->fb
), NULL
,
11796 INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
));
11797 intel_unpin_fb_obj(intel_fb_obj(plane
->fb
));
11798 mutex_unlock(&dev
->struct_mutex
);
11805 intel_check_primary_plane(struct drm_plane
*plane
,
11806 struct intel_plane_state
*state
)
11808 struct drm_crtc
*crtc
= state
->crtc
;
11809 struct drm_framebuffer
*fb
= state
->fb
;
11810 struct drm_rect
*dest
= &state
->dst
;
11811 struct drm_rect
*src
= &state
->src
;
11812 const struct drm_rect
*clip
= &state
->clip
;
11814 return drm_plane_helper_check_update(plane
, crtc
, fb
,
11816 DRM_PLANE_HELPER_NO_SCALING
,
11817 DRM_PLANE_HELPER_NO_SCALING
,
11818 false, true, &state
->visible
);
11822 intel_prepare_primary_plane(struct drm_plane
*plane
,
11823 struct intel_plane_state
*state
)
11825 struct drm_crtc
*crtc
= state
->crtc
;
11826 struct drm_framebuffer
*fb
= state
->fb
;
11827 struct drm_device
*dev
= crtc
->dev
;
11828 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11829 enum pipe pipe
= intel_crtc
->pipe
;
11830 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
11831 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(plane
->fb
);
11834 intel_crtc_wait_for_pending_flips(crtc
);
11836 if (intel_crtc_has_pending_flip(crtc
)) {
11837 DRM_ERROR("pipe is still busy with an old pageflip\n");
11841 if (old_obj
!= obj
) {
11842 mutex_lock(&dev
->struct_mutex
);
11843 ret
= intel_pin_and_fence_fb_obj(plane
, fb
, NULL
);
11845 i915_gem_track_fb(old_obj
, obj
,
11846 INTEL_FRONTBUFFER_PRIMARY(pipe
));
11847 mutex_unlock(&dev
->struct_mutex
);
11849 DRM_DEBUG_KMS("pin & fence failed\n");
11858 intel_commit_primary_plane(struct drm_plane
*plane
,
11859 struct intel_plane_state
*state
)
11861 struct drm_crtc
*crtc
= state
->crtc
;
11862 struct drm_framebuffer
*fb
= state
->fb
;
11863 struct drm_device
*dev
= crtc
->dev
;
11864 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11865 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11866 enum pipe pipe
= intel_crtc
->pipe
;
11867 struct drm_framebuffer
*old_fb
= plane
->fb
;
11868 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
11869 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(plane
->fb
);
11870 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
11871 struct drm_rect
*src
= &state
->src
;
11873 crtc
->primary
->fb
= fb
;
11874 crtc
->x
= src
->x1
>> 16;
11875 crtc
->y
= src
->y1
>> 16;
11877 intel_plane
->crtc_x
= state
->orig_dst
.x1
;
11878 intel_plane
->crtc_y
= state
->orig_dst
.y1
;
11879 intel_plane
->crtc_w
= drm_rect_width(&state
->orig_dst
);
11880 intel_plane
->crtc_h
= drm_rect_height(&state
->orig_dst
);
11881 intel_plane
->src_x
= state
->orig_src
.x1
;
11882 intel_plane
->src_y
= state
->orig_src
.y1
;
11883 intel_plane
->src_w
= drm_rect_width(&state
->orig_src
);
11884 intel_plane
->src_h
= drm_rect_height(&state
->orig_src
);
11885 intel_plane
->obj
= obj
;
11887 if (intel_crtc
->active
) {
11889 * FBC does not work on some platforms for rotated
11890 * planes, so disable it when rotation is not 0 and
11891 * update it when rotation is set back to 0.
11893 * FIXME: This is redundant with the fbc update done in
11894 * the primary plane enable function except that that
11895 * one is done too late. We eventually need to unify
11898 if (intel_crtc
->primary_enabled
&&
11899 INTEL_INFO(dev
)->gen
<= 4 && !IS_G4X(dev
) &&
11900 dev_priv
->fbc
.plane
== intel_crtc
->plane
&&
11901 intel_plane
->rotation
!= BIT(DRM_ROTATE_0
)) {
11902 intel_disable_fbc(dev
);
11905 if (state
->visible
) {
11906 bool was_enabled
= intel_crtc
->primary_enabled
;
11908 /* FIXME: kill this fastboot hack */
11909 intel_update_pipe_size(intel_crtc
);
11911 intel_crtc
->primary_enabled
= true;
11913 dev_priv
->display
.update_primary_plane(crtc
, plane
->fb
,
11917 * BDW signals flip done immediately if the plane
11918 * is disabled, even if the plane enable is already
11919 * armed to occur at the next vblank :(
11921 if (IS_BROADWELL(dev
) && !was_enabled
)
11922 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
11925 * If clipping results in a non-visible primary plane,
11926 * we'll disable the primary plane. Note that this is
11927 * a bit different than what happens if userspace
11928 * explicitly disables the plane by passing fb=0
11929 * because plane->fb still gets set and pinned.
11931 intel_disable_primary_hw_plane(plane
, crtc
);
11934 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
11936 mutex_lock(&dev
->struct_mutex
);
11937 intel_update_fbc(dev
);
11938 mutex_unlock(&dev
->struct_mutex
);
11941 if (old_fb
&& old_fb
!= fb
) {
11942 if (intel_crtc
->active
)
11943 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
11945 mutex_lock(&dev
->struct_mutex
);
11946 intel_unpin_fb_obj(old_obj
);
11947 mutex_unlock(&dev
->struct_mutex
);
11952 intel_primary_plane_setplane(struct drm_plane
*plane
, struct drm_crtc
*crtc
,
11953 struct drm_framebuffer
*fb
, int crtc_x
, int crtc_y
,
11954 unsigned int crtc_w
, unsigned int crtc_h
,
11955 uint32_t src_x
, uint32_t src_y
,
11956 uint32_t src_w
, uint32_t src_h
)
11958 struct intel_plane_state state
;
11959 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11965 /* sample coordinates in 16.16 fixed point */
11966 state
.src
.x1
= src_x
;
11967 state
.src
.x2
= src_x
+ src_w
;
11968 state
.src
.y1
= src_y
;
11969 state
.src
.y2
= src_y
+ src_h
;
11971 /* integer pixels */
11972 state
.dst
.x1
= crtc_x
;
11973 state
.dst
.x2
= crtc_x
+ crtc_w
;
11974 state
.dst
.y1
= crtc_y
;
11975 state
.dst
.y2
= crtc_y
+ crtc_h
;
11979 state
.clip
.x2
= intel_crtc
->active
? intel_crtc
->config
.pipe_src_w
: 0;
11980 state
.clip
.y2
= intel_crtc
->active
? intel_crtc
->config
.pipe_src_h
: 0;
11982 state
.orig_src
= state
.src
;
11983 state
.orig_dst
= state
.dst
;
11985 ret
= intel_check_primary_plane(plane
, &state
);
11989 ret
= intel_prepare_primary_plane(plane
, &state
);
11993 intel_commit_primary_plane(plane
, &state
);
11998 /* Common destruction function for both primary and cursor planes */
11999 static void intel_plane_destroy(struct drm_plane
*plane
)
12001 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
12002 drm_plane_cleanup(plane
);
12003 kfree(intel_plane
);
12006 static const struct drm_plane_funcs intel_primary_plane_funcs
= {
12007 .update_plane
= intel_primary_plane_setplane
,
12008 .disable_plane
= intel_primary_plane_disable
,
12009 .destroy
= intel_plane_destroy
,
12010 .set_property
= intel_plane_set_property
12013 static struct drm_plane
*intel_primary_plane_create(struct drm_device
*dev
,
12016 struct intel_plane
*primary
;
12017 const uint32_t *intel_primary_formats
;
12020 primary
= kzalloc(sizeof(*primary
), GFP_KERNEL
);
12021 if (primary
== NULL
)
12024 primary
->can_scale
= false;
12025 primary
->max_downscale
= 1;
12026 primary
->pipe
= pipe
;
12027 primary
->plane
= pipe
;
12028 primary
->rotation
= BIT(DRM_ROTATE_0
);
12029 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4)
12030 primary
->plane
= !pipe
;
12032 if (INTEL_INFO(dev
)->gen
<= 3) {
12033 intel_primary_formats
= intel_primary_formats_gen2
;
12034 num_formats
= ARRAY_SIZE(intel_primary_formats_gen2
);
12036 intel_primary_formats
= intel_primary_formats_gen4
;
12037 num_formats
= ARRAY_SIZE(intel_primary_formats_gen4
);
12040 drm_universal_plane_init(dev
, &primary
->base
, 0,
12041 &intel_primary_plane_funcs
,
12042 intel_primary_formats
, num_formats
,
12043 DRM_PLANE_TYPE_PRIMARY
);
12045 if (INTEL_INFO(dev
)->gen
>= 4) {
12046 if (!dev
->mode_config
.rotation_property
)
12047 dev
->mode_config
.rotation_property
=
12048 drm_mode_create_rotation_property(dev
,
12049 BIT(DRM_ROTATE_0
) |
12050 BIT(DRM_ROTATE_180
));
12051 if (dev
->mode_config
.rotation_property
)
12052 drm_object_attach_property(&primary
->base
.base
,
12053 dev
->mode_config
.rotation_property
,
12054 primary
->rotation
);
12057 return &primary
->base
;
12061 intel_cursor_plane_disable(struct drm_plane
*plane
)
12066 BUG_ON(!plane
->crtc
);
12068 return intel_crtc_cursor_set_obj(plane
->crtc
, NULL
, 0, 0);
12072 intel_check_cursor_plane(struct drm_plane
*plane
,
12073 struct intel_plane_state
*state
)
12075 struct drm_crtc
*crtc
= state
->crtc
;
12076 struct drm_device
*dev
= crtc
->dev
;
12077 struct drm_framebuffer
*fb
= state
->fb
;
12078 struct drm_rect
*dest
= &state
->dst
;
12079 struct drm_rect
*src
= &state
->src
;
12080 const struct drm_rect
*clip
= &state
->clip
;
12081 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
12082 int crtc_w
, crtc_h
;
12086 ret
= drm_plane_helper_check_update(plane
, crtc
, fb
,
12088 DRM_PLANE_HELPER_NO_SCALING
,
12089 DRM_PLANE_HELPER_NO_SCALING
,
12090 true, true, &state
->visible
);
12095 /* if we want to turn off the cursor ignore width and height */
12099 /* Check for which cursor types we support */
12100 crtc_w
= drm_rect_width(&state
->orig_dst
);
12101 crtc_h
= drm_rect_height(&state
->orig_dst
);
12102 if (!cursor_size_ok(dev
, crtc_w
, crtc_h
)) {
12103 DRM_DEBUG("Cursor dimension not supported\n");
12107 stride
= roundup_pow_of_two(crtc_w
) * 4;
12108 if (obj
->base
.size
< stride
* crtc_h
) {
12109 DRM_DEBUG_KMS("buffer is too small\n");
12113 if (fb
== crtc
->cursor
->fb
)
12116 /* we only need to pin inside GTT if cursor is non-phy */
12117 mutex_lock(&dev
->struct_mutex
);
12118 if (!INTEL_INFO(dev
)->cursor_needs_physical
&& obj
->tiling_mode
) {
12119 DRM_DEBUG_KMS("cursor cannot be tiled\n");
12122 mutex_unlock(&dev
->struct_mutex
);
12128 intel_commit_cursor_plane(struct drm_plane
*plane
,
12129 struct intel_plane_state
*state
)
12131 struct drm_crtc
*crtc
= state
->crtc
;
12132 struct drm_framebuffer
*fb
= state
->fb
;
12133 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
12134 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
12135 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
12136 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
12137 int crtc_w
, crtc_h
;
12139 crtc
->cursor_x
= state
->orig_dst
.x1
;
12140 crtc
->cursor_y
= state
->orig_dst
.y1
;
12142 intel_plane
->crtc_x
= state
->orig_dst
.x1
;
12143 intel_plane
->crtc_y
= state
->orig_dst
.y1
;
12144 intel_plane
->crtc_w
= drm_rect_width(&state
->orig_dst
);
12145 intel_plane
->crtc_h
= drm_rect_height(&state
->orig_dst
);
12146 intel_plane
->src_x
= state
->orig_src
.x1
;
12147 intel_plane
->src_y
= state
->orig_src
.y1
;
12148 intel_plane
->src_w
= drm_rect_width(&state
->orig_src
);
12149 intel_plane
->src_h
= drm_rect_height(&state
->orig_src
);
12150 intel_plane
->obj
= obj
;
12152 if (fb
!= crtc
->cursor
->fb
) {
12153 crtc_w
= drm_rect_width(&state
->orig_dst
);
12154 crtc_h
= drm_rect_height(&state
->orig_dst
);
12155 return intel_crtc_cursor_set_obj(crtc
, obj
, crtc_w
, crtc_h
);
12157 intel_crtc_update_cursor(crtc
, state
->visible
);
12159 intel_frontbuffer_flip(crtc
->dev
,
12160 INTEL_FRONTBUFFER_CURSOR(intel_crtc
->pipe
));
12167 intel_cursor_plane_update(struct drm_plane
*plane
, struct drm_crtc
*crtc
,
12168 struct drm_framebuffer
*fb
, int crtc_x
, int crtc_y
,
12169 unsigned int crtc_w
, unsigned int crtc_h
,
12170 uint32_t src_x
, uint32_t src_y
,
12171 uint32_t src_w
, uint32_t src_h
)
12173 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
12174 struct intel_plane_state state
;
12180 /* sample coordinates in 16.16 fixed point */
12181 state
.src
.x1
= src_x
;
12182 state
.src
.x2
= src_x
+ src_w
;
12183 state
.src
.y1
= src_y
;
12184 state
.src
.y2
= src_y
+ src_h
;
12186 /* integer pixels */
12187 state
.dst
.x1
= crtc_x
;
12188 state
.dst
.x2
= crtc_x
+ crtc_w
;
12189 state
.dst
.y1
= crtc_y
;
12190 state
.dst
.y2
= crtc_y
+ crtc_h
;
12194 state
.clip
.x2
= intel_crtc
->active
? intel_crtc
->config
.pipe_src_w
: 0;
12195 state
.clip
.y2
= intel_crtc
->active
? intel_crtc
->config
.pipe_src_h
: 0;
12197 state
.orig_src
= state
.src
;
12198 state
.orig_dst
= state
.dst
;
12200 ret
= intel_check_cursor_plane(plane
, &state
);
12204 return intel_commit_cursor_plane(plane
, &state
);
12207 static const struct drm_plane_funcs intel_cursor_plane_funcs
= {
12208 .update_plane
= intel_cursor_plane_update
,
12209 .disable_plane
= intel_cursor_plane_disable
,
12210 .destroy
= intel_plane_destroy
,
12211 .set_property
= intel_plane_set_property
,
12214 static struct drm_plane
*intel_cursor_plane_create(struct drm_device
*dev
,
12217 struct intel_plane
*cursor
;
12219 cursor
= kzalloc(sizeof(*cursor
), GFP_KERNEL
);
12220 if (cursor
== NULL
)
12223 cursor
->can_scale
= false;
12224 cursor
->max_downscale
= 1;
12225 cursor
->pipe
= pipe
;
12226 cursor
->plane
= pipe
;
12227 cursor
->rotation
= BIT(DRM_ROTATE_0
);
12229 drm_universal_plane_init(dev
, &cursor
->base
, 0,
12230 &intel_cursor_plane_funcs
,
12231 intel_cursor_formats
,
12232 ARRAY_SIZE(intel_cursor_formats
),
12233 DRM_PLANE_TYPE_CURSOR
);
12235 if (INTEL_INFO(dev
)->gen
>= 4) {
12236 if (!dev
->mode_config
.rotation_property
)
12237 dev
->mode_config
.rotation_property
=
12238 drm_mode_create_rotation_property(dev
,
12239 BIT(DRM_ROTATE_0
) |
12240 BIT(DRM_ROTATE_180
));
12241 if (dev
->mode_config
.rotation_property
)
12242 drm_object_attach_property(&cursor
->base
.base
,
12243 dev
->mode_config
.rotation_property
,
12247 return &cursor
->base
;
12250 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
12252 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12253 struct intel_crtc
*intel_crtc
;
12254 struct drm_plane
*primary
= NULL
;
12255 struct drm_plane
*cursor
= NULL
;
12258 intel_crtc
= kzalloc(sizeof(*intel_crtc
), GFP_KERNEL
);
12259 if (intel_crtc
== NULL
)
12262 primary
= intel_primary_plane_create(dev
, pipe
);
12266 cursor
= intel_cursor_plane_create(dev
, pipe
);
12270 ret
= drm_crtc_init_with_planes(dev
, &intel_crtc
->base
, primary
,
12271 cursor
, &intel_crtc_funcs
);
12275 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
12276 for (i
= 0; i
< 256; i
++) {
12277 intel_crtc
->lut_r
[i
] = i
;
12278 intel_crtc
->lut_g
[i
] = i
;
12279 intel_crtc
->lut_b
[i
] = i
;
12283 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12284 * is hooked to pipe B. Hence we want plane A feeding pipe B.
12286 intel_crtc
->pipe
= pipe
;
12287 intel_crtc
->plane
= pipe
;
12288 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4) {
12289 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12290 intel_crtc
->plane
= !pipe
;
12293 intel_crtc
->cursor_base
= ~0;
12294 intel_crtc
->cursor_cntl
= ~0;
12295 intel_crtc
->cursor_size
= ~0;
12297 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
12298 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
12299 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
12300 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
12302 INIT_WORK(&intel_crtc
->mmio_flip
.work
, intel_mmio_flip_work_func
);
12304 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
12306 WARN_ON(drm_crtc_index(&intel_crtc
->base
) != intel_crtc
->pipe
);
12311 drm_plane_cleanup(primary
);
12313 drm_plane_cleanup(cursor
);
12317 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
)
12319 struct drm_encoder
*encoder
= connector
->base
.encoder
;
12320 struct drm_device
*dev
= connector
->base
.dev
;
12322 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
12324 if (!encoder
|| WARN_ON(!encoder
->crtc
))
12325 return INVALID_PIPE
;
12327 return to_intel_crtc(encoder
->crtc
)->pipe
;
12330 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
12331 struct drm_file
*file
)
12333 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
12334 struct drm_crtc
*drmmode_crtc
;
12335 struct intel_crtc
*crtc
;
12337 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
12340 drmmode_crtc
= drm_crtc_find(dev
, pipe_from_crtc_id
->crtc_id
);
12342 if (!drmmode_crtc
) {
12343 DRM_ERROR("no such CRTC id\n");
12347 crtc
= to_intel_crtc(drmmode_crtc
);
12348 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
12353 static int intel_encoder_clones(struct intel_encoder
*encoder
)
12355 struct drm_device
*dev
= encoder
->base
.dev
;
12356 struct intel_encoder
*source_encoder
;
12357 int index_mask
= 0;
12360 for_each_intel_encoder(dev
, source_encoder
) {
12361 if (encoders_cloneable(encoder
, source_encoder
))
12362 index_mask
|= (1 << entry
);
12370 static bool has_edp_a(struct drm_device
*dev
)
12372 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12374 if (!IS_MOBILE(dev
))
12377 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
12380 if (IS_GEN5(dev
) && (I915_READ(FUSE_STRAP
) & ILK_eDP_A_DISABLE
))
12386 const char *intel_output_name(int output
)
12388 static const char *names
[] = {
12389 [INTEL_OUTPUT_UNUSED
] = "Unused",
12390 [INTEL_OUTPUT_ANALOG
] = "Analog",
12391 [INTEL_OUTPUT_DVO
] = "DVO",
12392 [INTEL_OUTPUT_SDVO
] = "SDVO",
12393 [INTEL_OUTPUT_LVDS
] = "LVDS",
12394 [INTEL_OUTPUT_TVOUT
] = "TV",
12395 [INTEL_OUTPUT_HDMI
] = "HDMI",
12396 [INTEL_OUTPUT_DISPLAYPORT
] = "DisplayPort",
12397 [INTEL_OUTPUT_EDP
] = "eDP",
12398 [INTEL_OUTPUT_DSI
] = "DSI",
12399 [INTEL_OUTPUT_UNKNOWN
] = "Unknown",
12402 if (output
< 0 || output
>= ARRAY_SIZE(names
) || !names
[output
])
12405 return names
[output
];
12408 static bool intel_crt_present(struct drm_device
*dev
)
12410 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12412 if (INTEL_INFO(dev
)->gen
>= 9)
12415 if (IS_HSW_ULT(dev
) || IS_BDW_ULT(dev
))
12418 if (IS_CHERRYVIEW(dev
))
12421 if (IS_VALLEYVIEW(dev
) && !dev_priv
->vbt
.int_crt_support
)
12427 static void intel_setup_outputs(struct drm_device
*dev
)
12429 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12430 struct intel_encoder
*encoder
;
12431 bool dpd_is_edp
= false;
12433 intel_lvds_init(dev
);
12435 if (intel_crt_present(dev
))
12436 intel_crt_init(dev
);
12438 if (HAS_DDI(dev
)) {
12441 /* Haswell uses DDI functions to detect digital outputs */
12442 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
12443 /* DDI A only supports eDP */
12445 intel_ddi_init(dev
, PORT_A
);
12447 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12449 found
= I915_READ(SFUSE_STRAP
);
12451 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
12452 intel_ddi_init(dev
, PORT_B
);
12453 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
12454 intel_ddi_init(dev
, PORT_C
);
12455 if (found
& SFUSE_STRAP_DDID_DETECTED
)
12456 intel_ddi_init(dev
, PORT_D
);
12457 } else if (HAS_PCH_SPLIT(dev
)) {
12459 dpd_is_edp
= intel_dp_is_edp(dev
, PORT_D
);
12461 if (has_edp_a(dev
))
12462 intel_dp_init(dev
, DP_A
, PORT_A
);
12464 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
12465 /* PCH SDVOB multiplex with HDMIB */
12466 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
12468 intel_hdmi_init(dev
, PCH_HDMIB
, PORT_B
);
12469 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
12470 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
12473 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
12474 intel_hdmi_init(dev
, PCH_HDMIC
, PORT_C
);
12476 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
12477 intel_hdmi_init(dev
, PCH_HDMID
, PORT_D
);
12479 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
12480 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
12482 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
12483 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
12484 } else if (IS_VALLEYVIEW(dev
)) {
12486 * The DP_DETECTED bit is the latched state of the DDC
12487 * SDA pin at boot. However since eDP doesn't require DDC
12488 * (no way to plug in a DP->HDMI dongle) the DDC pins for
12489 * eDP ports may have been muxed to an alternate function.
12490 * Thus we can't rely on the DP_DETECTED bit alone to detect
12491 * eDP ports. Consult the VBT as well as DP_DETECTED to
12492 * detect eDP ports.
12494 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIB
) & SDVO_DETECTED
)
12495 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIB
,
12497 if (I915_READ(VLV_DISPLAY_BASE
+ DP_B
) & DP_DETECTED
||
12498 intel_dp_is_edp(dev
, PORT_B
))
12499 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_B
, PORT_B
);
12501 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIC
) & SDVO_DETECTED
)
12502 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIC
,
12504 if (I915_READ(VLV_DISPLAY_BASE
+ DP_C
) & DP_DETECTED
||
12505 intel_dp_is_edp(dev
, PORT_C
))
12506 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_C
, PORT_C
);
12508 if (IS_CHERRYVIEW(dev
)) {
12509 if (I915_READ(VLV_DISPLAY_BASE
+ CHV_HDMID
) & SDVO_DETECTED
)
12510 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ CHV_HDMID
,
12512 /* eDP not supported on port D, so don't check VBT */
12513 if (I915_READ(VLV_DISPLAY_BASE
+ DP_D
) & DP_DETECTED
)
12514 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_D
, PORT_D
);
12517 intel_dsi_init(dev
);
12518 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
12519 bool found
= false;
12521 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
12522 DRM_DEBUG_KMS("probing SDVOB\n");
12523 found
= intel_sdvo_init(dev
, GEN3_SDVOB
, true);
12524 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
12525 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12526 intel_hdmi_init(dev
, GEN4_HDMIB
, PORT_B
);
12529 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
))
12530 intel_dp_init(dev
, DP_B
, PORT_B
);
12533 /* Before G4X SDVOC doesn't have its own detect register */
12535 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
12536 DRM_DEBUG_KMS("probing SDVOC\n");
12537 found
= intel_sdvo_init(dev
, GEN3_SDVOC
, false);
12540 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
12542 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
12543 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12544 intel_hdmi_init(dev
, GEN4_HDMIC
, PORT_C
);
12546 if (SUPPORTS_INTEGRATED_DP(dev
))
12547 intel_dp_init(dev
, DP_C
, PORT_C
);
12550 if (SUPPORTS_INTEGRATED_DP(dev
) &&
12551 (I915_READ(DP_D
) & DP_DETECTED
))
12552 intel_dp_init(dev
, DP_D
, PORT_D
);
12553 } else if (IS_GEN2(dev
))
12554 intel_dvo_init(dev
);
12556 if (SUPPORTS_TV(dev
))
12557 intel_tv_init(dev
);
12559 intel_psr_init(dev
);
12561 for_each_intel_encoder(dev
, encoder
) {
12562 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
12563 encoder
->base
.possible_clones
=
12564 intel_encoder_clones(encoder
);
12567 intel_init_pch_refclk(dev
);
12569 drm_helper_move_panel_connectors_to_head(dev
);
12572 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
12574 struct drm_device
*dev
= fb
->dev
;
12575 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
12577 drm_framebuffer_cleanup(fb
);
12578 mutex_lock(&dev
->struct_mutex
);
12579 WARN_ON(!intel_fb
->obj
->framebuffer_references
--);
12580 drm_gem_object_unreference(&intel_fb
->obj
->base
);
12581 mutex_unlock(&dev
->struct_mutex
);
12585 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
12586 struct drm_file
*file
,
12587 unsigned int *handle
)
12589 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
12590 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
12592 return drm_gem_handle_create(file
, &obj
->base
, handle
);
12595 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
12596 .destroy
= intel_user_framebuffer_destroy
,
12597 .create_handle
= intel_user_framebuffer_create_handle
,
12600 static int intel_framebuffer_init(struct drm_device
*dev
,
12601 struct intel_framebuffer
*intel_fb
,
12602 struct drm_mode_fb_cmd2
*mode_cmd
,
12603 struct drm_i915_gem_object
*obj
)
12605 int aligned_height
;
12609 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
12611 if (obj
->tiling_mode
== I915_TILING_Y
) {
12612 DRM_DEBUG("hardware does not support tiling Y\n");
12616 if (mode_cmd
->pitches
[0] & 63) {
12617 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12618 mode_cmd
->pitches
[0]);
12622 if (INTEL_INFO(dev
)->gen
>= 5 && !IS_VALLEYVIEW(dev
)) {
12623 pitch_limit
= 32*1024;
12624 } else if (INTEL_INFO(dev
)->gen
>= 4) {
12625 if (obj
->tiling_mode
)
12626 pitch_limit
= 16*1024;
12628 pitch_limit
= 32*1024;
12629 } else if (INTEL_INFO(dev
)->gen
>= 3) {
12630 if (obj
->tiling_mode
)
12631 pitch_limit
= 8*1024;
12633 pitch_limit
= 16*1024;
12635 /* XXX DSPC is limited to 4k tiled */
12636 pitch_limit
= 8*1024;
12638 if (mode_cmd
->pitches
[0] > pitch_limit
) {
12639 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12640 obj
->tiling_mode
? "tiled" : "linear",
12641 mode_cmd
->pitches
[0], pitch_limit
);
12645 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
12646 mode_cmd
->pitches
[0] != obj
->stride
) {
12647 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12648 mode_cmd
->pitches
[0], obj
->stride
);
12652 /* Reject formats not supported by any plane early. */
12653 switch (mode_cmd
->pixel_format
) {
12654 case DRM_FORMAT_C8
:
12655 case DRM_FORMAT_RGB565
:
12656 case DRM_FORMAT_XRGB8888
:
12657 case DRM_FORMAT_ARGB8888
:
12659 case DRM_FORMAT_XRGB1555
:
12660 case DRM_FORMAT_ARGB1555
:
12661 if (INTEL_INFO(dev
)->gen
> 3) {
12662 DRM_DEBUG("unsupported pixel format: %s\n",
12663 drm_get_format_name(mode_cmd
->pixel_format
));
12667 case DRM_FORMAT_XBGR8888
:
12668 case DRM_FORMAT_ABGR8888
:
12669 case DRM_FORMAT_XRGB2101010
:
12670 case DRM_FORMAT_ARGB2101010
:
12671 case DRM_FORMAT_XBGR2101010
:
12672 case DRM_FORMAT_ABGR2101010
:
12673 if (INTEL_INFO(dev
)->gen
< 4) {
12674 DRM_DEBUG("unsupported pixel format: %s\n",
12675 drm_get_format_name(mode_cmd
->pixel_format
));
12679 case DRM_FORMAT_YUYV
:
12680 case DRM_FORMAT_UYVY
:
12681 case DRM_FORMAT_YVYU
:
12682 case DRM_FORMAT_VYUY
:
12683 if (INTEL_INFO(dev
)->gen
< 5) {
12684 DRM_DEBUG("unsupported pixel format: %s\n",
12685 drm_get_format_name(mode_cmd
->pixel_format
));
12690 DRM_DEBUG("unsupported pixel format: %s\n",
12691 drm_get_format_name(mode_cmd
->pixel_format
));
12695 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12696 if (mode_cmd
->offsets
[0] != 0)
12699 aligned_height
= intel_align_height(dev
, mode_cmd
->height
,
12701 /* FIXME drm helper for size checks (especially planar formats)? */
12702 if (obj
->base
.size
< aligned_height
* mode_cmd
->pitches
[0])
12705 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
12706 intel_fb
->obj
= obj
;
12707 intel_fb
->obj
->framebuffer_references
++;
12709 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
12711 DRM_ERROR("framebuffer init failed %d\n", ret
);
12718 static struct drm_framebuffer
*
12719 intel_user_framebuffer_create(struct drm_device
*dev
,
12720 struct drm_file
*filp
,
12721 struct drm_mode_fb_cmd2
*mode_cmd
)
12723 struct drm_i915_gem_object
*obj
;
12725 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
12726 mode_cmd
->handles
[0]));
12727 if (&obj
->base
== NULL
)
12728 return ERR_PTR(-ENOENT
);
12730 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
12733 #ifndef CONFIG_DRM_I915_FBDEV
12734 static inline void intel_fbdev_output_poll_changed(struct drm_device
*dev
)
12739 static const struct drm_mode_config_funcs intel_mode_funcs
= {
12740 .fb_create
= intel_user_framebuffer_create
,
12741 .output_poll_changed
= intel_fbdev_output_poll_changed
,
12744 /* Set up chip specific display functions */
12745 static void intel_init_display(struct drm_device
*dev
)
12747 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12749 if (HAS_PCH_SPLIT(dev
) || IS_G4X(dev
))
12750 dev_priv
->display
.find_dpll
= g4x_find_best_dpll
;
12751 else if (IS_CHERRYVIEW(dev
))
12752 dev_priv
->display
.find_dpll
= chv_find_best_dpll
;
12753 else if (IS_VALLEYVIEW(dev
))
12754 dev_priv
->display
.find_dpll
= vlv_find_best_dpll
;
12755 else if (IS_PINEVIEW(dev
))
12756 dev_priv
->display
.find_dpll
= pnv_find_best_dpll
;
12758 dev_priv
->display
.find_dpll
= i9xx_find_best_dpll
;
12760 if (HAS_DDI(dev
)) {
12761 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
12762 dev_priv
->display
.get_plane_config
= ironlake_get_plane_config
;
12763 dev_priv
->display
.crtc_compute_clock
=
12764 haswell_crtc_compute_clock
;
12765 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
12766 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
12767 dev_priv
->display
.off
= ironlake_crtc_off
;
12768 if (INTEL_INFO(dev
)->gen
>= 9)
12769 dev_priv
->display
.update_primary_plane
=
12770 skylake_update_primary_plane
;
12772 dev_priv
->display
.update_primary_plane
=
12773 ironlake_update_primary_plane
;
12774 } else if (HAS_PCH_SPLIT(dev
)) {
12775 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
12776 dev_priv
->display
.get_plane_config
= ironlake_get_plane_config
;
12777 dev_priv
->display
.crtc_compute_clock
=
12778 ironlake_crtc_compute_clock
;
12779 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
12780 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
12781 dev_priv
->display
.off
= ironlake_crtc_off
;
12782 dev_priv
->display
.update_primary_plane
=
12783 ironlake_update_primary_plane
;
12784 } else if (IS_VALLEYVIEW(dev
)) {
12785 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
12786 dev_priv
->display
.get_plane_config
= i9xx_get_plane_config
;
12787 dev_priv
->display
.crtc_compute_clock
= i9xx_crtc_compute_clock
;
12788 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
12789 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
12790 dev_priv
->display
.off
= i9xx_crtc_off
;
12791 dev_priv
->display
.update_primary_plane
=
12792 i9xx_update_primary_plane
;
12794 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
12795 dev_priv
->display
.get_plane_config
= i9xx_get_plane_config
;
12796 dev_priv
->display
.crtc_compute_clock
= i9xx_crtc_compute_clock
;
12797 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
12798 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
12799 dev_priv
->display
.off
= i9xx_crtc_off
;
12800 dev_priv
->display
.update_primary_plane
=
12801 i9xx_update_primary_plane
;
12804 /* Returns the core display clock speed */
12805 if (IS_VALLEYVIEW(dev
))
12806 dev_priv
->display
.get_display_clock_speed
=
12807 valleyview_get_display_clock_speed
;
12808 else if (IS_I945G(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
12809 dev_priv
->display
.get_display_clock_speed
=
12810 i945_get_display_clock_speed
;
12811 else if (IS_I915G(dev
))
12812 dev_priv
->display
.get_display_clock_speed
=
12813 i915_get_display_clock_speed
;
12814 else if (IS_I945GM(dev
) || IS_845G(dev
))
12815 dev_priv
->display
.get_display_clock_speed
=
12816 i9xx_misc_get_display_clock_speed
;
12817 else if (IS_PINEVIEW(dev
))
12818 dev_priv
->display
.get_display_clock_speed
=
12819 pnv_get_display_clock_speed
;
12820 else if (IS_I915GM(dev
))
12821 dev_priv
->display
.get_display_clock_speed
=
12822 i915gm_get_display_clock_speed
;
12823 else if (IS_I865G(dev
))
12824 dev_priv
->display
.get_display_clock_speed
=
12825 i865_get_display_clock_speed
;
12826 else if (IS_I85X(dev
))
12827 dev_priv
->display
.get_display_clock_speed
=
12828 i855_get_display_clock_speed
;
12829 else /* 852, 830 */
12830 dev_priv
->display
.get_display_clock_speed
=
12831 i830_get_display_clock_speed
;
12833 if (IS_GEN5(dev
)) {
12834 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
12835 } else if (IS_GEN6(dev
)) {
12836 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
12837 } else if (IS_IVYBRIDGE(dev
)) {
12838 /* FIXME: detect B0+ stepping and use auto training */
12839 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
12840 dev_priv
->display
.modeset_global_resources
=
12841 ivb_modeset_global_resources
;
12842 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
12843 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
12844 } else if (IS_VALLEYVIEW(dev
)) {
12845 dev_priv
->display
.modeset_global_resources
=
12846 valleyview_modeset_global_resources
;
12849 /* Default just returns -ENODEV to indicate unsupported */
12850 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
12852 switch (INTEL_INFO(dev
)->gen
) {
12854 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
12858 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
12863 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
12867 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
12870 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12871 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
12874 dev_priv
->display
.queue_flip
= intel_gen9_queue_flip
;
12878 intel_panel_init_backlight_funcs(dev
);
12880 mutex_init(&dev_priv
->pps_mutex
);
12884 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12885 * resume, or other times. This quirk makes sure that's the case for
12886 * affected systems.
12888 static void quirk_pipea_force(struct drm_device
*dev
)
12890 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12892 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
12893 DRM_INFO("applying pipe a force quirk\n");
12896 static void quirk_pipeb_force(struct drm_device
*dev
)
12898 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12900 dev_priv
->quirks
|= QUIRK_PIPEB_FORCE
;
12901 DRM_INFO("applying pipe b force quirk\n");
12905 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12907 static void quirk_ssc_force_disable(struct drm_device
*dev
)
12909 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12910 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
12911 DRM_INFO("applying lvds SSC disable quirk\n");
12915 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12918 static void quirk_invert_brightness(struct drm_device
*dev
)
12920 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12921 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
12922 DRM_INFO("applying inverted panel brightness quirk\n");
12925 /* Some VBT's incorrectly indicate no backlight is present */
12926 static void quirk_backlight_present(struct drm_device
*dev
)
12928 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12929 dev_priv
->quirks
|= QUIRK_BACKLIGHT_PRESENT
;
12930 DRM_INFO("applying backlight present quirk\n");
12933 struct intel_quirk
{
12935 int subsystem_vendor
;
12936 int subsystem_device
;
12937 void (*hook
)(struct drm_device
*dev
);
12940 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12941 struct intel_dmi_quirk
{
12942 void (*hook
)(struct drm_device
*dev
);
12943 const struct dmi_system_id (*dmi_id_list
)[];
12946 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
12948 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
12952 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
12954 .dmi_id_list
= &(const struct dmi_system_id
[]) {
12956 .callback
= intel_dmi_reverse_brightness
,
12957 .ident
= "NCR Corporation",
12958 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
12959 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
12962 { } /* terminating entry */
12964 .hook
= quirk_invert_brightness
,
12968 static struct intel_quirk intel_quirks
[] = {
12969 /* HP Mini needs pipe A force quirk (LP: #322104) */
12970 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force
},
12972 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12973 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
12975 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12976 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
12978 /* 830 needs to leave pipe A & dpll A up */
12979 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
12981 /* 830 needs to leave pipe B & dpll B up */
12982 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipeb_force
},
12984 /* Lenovo U160 cannot use SSC on LVDS */
12985 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
12987 /* Sony Vaio Y cannot use SSC on LVDS */
12988 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
12990 /* Acer Aspire 5734Z must invert backlight brightness */
12991 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
12993 /* Acer/eMachines G725 */
12994 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness
},
12996 /* Acer/eMachines e725 */
12997 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness
},
12999 /* Acer/Packard Bell NCL20 */
13000 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness
},
13002 /* Acer Aspire 4736Z */
13003 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness
},
13005 /* Acer Aspire 5336 */
13006 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness
},
13008 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
13009 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present
},
13011 /* Acer C720 Chromebook (Core i3 4005U) */
13012 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present
},
13014 /* Apple Macbook 2,1 (Core 2 T7400) */
13015 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present
},
13017 /* Toshiba CB35 Chromebook (Celeron 2955U) */
13018 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present
},
13020 /* HP Chromebook 14 (Celeron 2955U) */
13021 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present
},
13024 static void intel_init_quirks(struct drm_device
*dev
)
13026 struct pci_dev
*d
= dev
->pdev
;
13029 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
13030 struct intel_quirk
*q
= &intel_quirks
[i
];
13032 if (d
->device
== q
->device
&&
13033 (d
->subsystem_vendor
== q
->subsystem_vendor
||
13034 q
->subsystem_vendor
== PCI_ANY_ID
) &&
13035 (d
->subsystem_device
== q
->subsystem_device
||
13036 q
->subsystem_device
== PCI_ANY_ID
))
13039 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
13040 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
13041 intel_dmi_quirks
[i
].hook(dev
);
13045 /* Disable the VGA plane that we never use */
13046 static void i915_disable_vga(struct drm_device
*dev
)
13048 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13050 u32 vga_reg
= i915_vgacntrl_reg(dev
);
13052 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
13053 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
13054 outb(SR01
, VGA_SR_INDEX
);
13055 sr1
= inb(VGA_SR_DATA
);
13056 outb(sr1
| 1<<5, VGA_SR_DATA
);
13057 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
13060 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
13061 POSTING_READ(vga_reg
);
13064 void intel_modeset_init_hw(struct drm_device
*dev
)
13066 intel_prepare_ddi(dev
);
13068 if (IS_VALLEYVIEW(dev
))
13069 vlv_update_cdclk(dev
);
13071 intel_init_clock_gating(dev
);
13073 intel_enable_gt_powersave(dev
);
13076 void intel_modeset_init(struct drm_device
*dev
)
13078 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13081 struct intel_crtc
*crtc
;
13083 drm_mode_config_init(dev
);
13085 dev
->mode_config
.min_width
= 0;
13086 dev
->mode_config
.min_height
= 0;
13088 dev
->mode_config
.preferred_depth
= 24;
13089 dev
->mode_config
.prefer_shadow
= 1;
13091 dev
->mode_config
.funcs
= &intel_mode_funcs
;
13093 intel_init_quirks(dev
);
13095 intel_init_pm(dev
);
13097 if (INTEL_INFO(dev
)->num_pipes
== 0)
13100 intel_init_display(dev
);
13101 intel_init_audio(dev
);
13103 if (IS_GEN2(dev
)) {
13104 dev
->mode_config
.max_width
= 2048;
13105 dev
->mode_config
.max_height
= 2048;
13106 } else if (IS_GEN3(dev
)) {
13107 dev
->mode_config
.max_width
= 4096;
13108 dev
->mode_config
.max_height
= 4096;
13110 dev
->mode_config
.max_width
= 8192;
13111 dev
->mode_config
.max_height
= 8192;
13114 if (IS_845G(dev
) || IS_I865G(dev
)) {
13115 dev
->mode_config
.cursor_width
= IS_845G(dev
) ? 64 : 512;
13116 dev
->mode_config
.cursor_height
= 1023;
13117 } else if (IS_GEN2(dev
)) {
13118 dev
->mode_config
.cursor_width
= GEN2_CURSOR_WIDTH
;
13119 dev
->mode_config
.cursor_height
= GEN2_CURSOR_HEIGHT
;
13121 dev
->mode_config
.cursor_width
= MAX_CURSOR_WIDTH
;
13122 dev
->mode_config
.cursor_height
= MAX_CURSOR_HEIGHT
;
13125 dev
->mode_config
.fb_base
= dev_priv
->gtt
.mappable_base
;
13127 DRM_DEBUG_KMS("%d display pipe%s available.\n",
13128 INTEL_INFO(dev
)->num_pipes
,
13129 INTEL_INFO(dev
)->num_pipes
> 1 ? "s" : "");
13131 for_each_pipe(dev_priv
, pipe
) {
13132 intel_crtc_init(dev
, pipe
);
13133 for_each_sprite(pipe
, sprite
) {
13134 ret
= intel_plane_init(dev
, pipe
, sprite
);
13136 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
13137 pipe_name(pipe
), sprite_name(pipe
, sprite
), ret
);
13141 intel_init_dpio(dev
);
13143 intel_shared_dpll_init(dev
);
13145 /* Just disable it once at startup */
13146 i915_disable_vga(dev
);
13147 intel_setup_outputs(dev
);
13149 /* Just in case the BIOS is doing something questionable. */
13150 intel_disable_fbc(dev
);
13152 drm_modeset_lock_all(dev
);
13153 intel_modeset_setup_hw_state(dev
, false);
13154 drm_modeset_unlock_all(dev
);
13156 for_each_intel_crtc(dev
, crtc
) {
13161 * Note that reserving the BIOS fb up front prevents us
13162 * from stuffing other stolen allocations like the ring
13163 * on top. This prevents some ugliness at boot time, and
13164 * can even allow for smooth boot transitions if the BIOS
13165 * fb is large enough for the active pipe configuration.
13167 if (dev_priv
->display
.get_plane_config
) {
13168 dev_priv
->display
.get_plane_config(crtc
,
13169 &crtc
->plane_config
);
13171 * If the fb is shared between multiple heads, we'll
13172 * just get the first one.
13174 intel_find_plane_obj(crtc
, &crtc
->plane_config
);
13179 static void intel_enable_pipe_a(struct drm_device
*dev
)
13181 struct intel_connector
*connector
;
13182 struct drm_connector
*crt
= NULL
;
13183 struct intel_load_detect_pipe load_detect_temp
;
13184 struct drm_modeset_acquire_ctx
*ctx
= dev
->mode_config
.acquire_ctx
;
13186 /* We can't just switch on the pipe A, we need to set things up with a
13187 * proper mode and output configuration. As a gross hack, enable pipe A
13188 * by enabling the load detect pipe once. */
13189 list_for_each_entry(connector
,
13190 &dev
->mode_config
.connector_list
,
13192 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
13193 crt
= &connector
->base
;
13201 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
, ctx
))
13202 intel_release_load_detect_pipe(crt
, &load_detect_temp
);
13206 intel_check_plane_mapping(struct intel_crtc
*crtc
)
13208 struct drm_device
*dev
= crtc
->base
.dev
;
13209 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13212 if (INTEL_INFO(dev
)->num_pipes
== 1)
13215 reg
= DSPCNTR(!crtc
->plane
);
13216 val
= I915_READ(reg
);
13218 if ((val
& DISPLAY_PLANE_ENABLE
) &&
13219 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
13225 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
13227 struct drm_device
*dev
= crtc
->base
.dev
;
13228 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13231 /* Clear any frame start delays used for debugging left by the BIOS */
13232 reg
= PIPECONF(crtc
->config
.cpu_transcoder
);
13233 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
13235 /* restore vblank interrupts to correct state */
13236 if (crtc
->active
) {
13237 update_scanline_offset(crtc
);
13238 drm_vblank_on(dev
, crtc
->pipe
);
13240 drm_vblank_off(dev
, crtc
->pipe
);
13242 /* We need to sanitize the plane -> pipe mapping first because this will
13243 * disable the crtc (and hence change the state) if it is wrong. Note
13244 * that gen4+ has a fixed plane -> pipe mapping. */
13245 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
13246 struct intel_connector
*connector
;
13249 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13250 crtc
->base
.base
.id
);
13252 /* Pipe has the wrong plane attached and the plane is active.
13253 * Temporarily change the plane mapping and disable everything
13255 plane
= crtc
->plane
;
13256 crtc
->plane
= !plane
;
13257 crtc
->primary_enabled
= true;
13258 dev_priv
->display
.crtc_disable(&crtc
->base
);
13259 crtc
->plane
= plane
;
13261 /* ... and break all links. */
13262 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
13264 if (connector
->encoder
->base
.crtc
!= &crtc
->base
)
13267 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
13268 connector
->base
.encoder
= NULL
;
13270 /* multiple connectors may have the same encoder:
13271 * handle them and break crtc link separately */
13272 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
13274 if (connector
->encoder
->base
.crtc
== &crtc
->base
) {
13275 connector
->encoder
->base
.crtc
= NULL
;
13276 connector
->encoder
->connectors_active
= false;
13279 WARN_ON(crtc
->active
);
13280 crtc
->base
.enabled
= false;
13283 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
13284 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
13285 /* BIOS forgot to enable pipe A, this mostly happens after
13286 * resume. Force-enable the pipe to fix this, the update_dpms
13287 * call below we restore the pipe to the right state, but leave
13288 * the required bits on. */
13289 intel_enable_pipe_a(dev
);
13292 /* Adjust the state of the output pipe according to whether we
13293 * have active connectors/encoders. */
13294 intel_crtc_update_dpms(&crtc
->base
);
13296 if (crtc
->active
!= crtc
->base
.enabled
) {
13297 struct intel_encoder
*encoder
;
13299 /* This can happen either due to bugs in the get_hw_state
13300 * functions or because the pipe is force-enabled due to the
13302 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13303 crtc
->base
.base
.id
,
13304 crtc
->base
.enabled
? "enabled" : "disabled",
13305 crtc
->active
? "enabled" : "disabled");
13307 crtc
->base
.enabled
= crtc
->active
;
13309 /* Because we only establish the connector -> encoder ->
13310 * crtc links if something is active, this means the
13311 * crtc is now deactivated. Break the links. connector
13312 * -> encoder links are only establish when things are
13313 * actually up, hence no need to break them. */
13314 WARN_ON(crtc
->active
);
13316 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
13317 WARN_ON(encoder
->connectors_active
);
13318 encoder
->base
.crtc
= NULL
;
13322 if (crtc
->active
|| HAS_GMCH_DISPLAY(dev
)) {
13324 * We start out with underrun reporting disabled to avoid races.
13325 * For correct bookkeeping mark this on active crtcs.
13327 * Also on gmch platforms we dont have any hardware bits to
13328 * disable the underrun reporting. Which means we need to start
13329 * out with underrun reporting disabled also on inactive pipes,
13330 * since otherwise we'll complain about the garbage we read when
13331 * e.g. coming up after runtime pm.
13333 * No protection against concurrent access is required - at
13334 * worst a fifo underrun happens which also sets this to false.
13336 crtc
->cpu_fifo_underrun_disabled
= true;
13337 crtc
->pch_fifo_underrun_disabled
= true;
13341 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
13343 struct intel_connector
*connector
;
13344 struct drm_device
*dev
= encoder
->base
.dev
;
13346 /* We need to check both for a crtc link (meaning that the
13347 * encoder is active and trying to read from a pipe) and the
13348 * pipe itself being active. */
13349 bool has_active_crtc
= encoder
->base
.crtc
&&
13350 to_intel_crtc(encoder
->base
.crtc
)->active
;
13352 if (encoder
->connectors_active
&& !has_active_crtc
) {
13353 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13354 encoder
->base
.base
.id
,
13355 encoder
->base
.name
);
13357 /* Connector is active, but has no active pipe. This is
13358 * fallout from our resume register restoring. Disable
13359 * the encoder manually again. */
13360 if (encoder
->base
.crtc
) {
13361 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13362 encoder
->base
.base
.id
,
13363 encoder
->base
.name
);
13364 encoder
->disable(encoder
);
13365 if (encoder
->post_disable
)
13366 encoder
->post_disable(encoder
);
13368 encoder
->base
.crtc
= NULL
;
13369 encoder
->connectors_active
= false;
13371 /* Inconsistent output/port/pipe state happens presumably due to
13372 * a bug in one of the get_hw_state functions. Or someplace else
13373 * in our code, like the register restore mess on resume. Clamp
13374 * things to off as a safer default. */
13375 list_for_each_entry(connector
,
13376 &dev
->mode_config
.connector_list
,
13378 if (connector
->encoder
!= encoder
)
13380 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
13381 connector
->base
.encoder
= NULL
;
13384 /* Enabled encoders without active connectors will be fixed in
13385 * the crtc fixup. */
13388 void i915_redisable_vga_power_on(struct drm_device
*dev
)
13390 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13391 u32 vga_reg
= i915_vgacntrl_reg(dev
);
13393 if (!(I915_READ(vga_reg
) & VGA_DISP_DISABLE
)) {
13394 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13395 i915_disable_vga(dev
);
13399 void i915_redisable_vga(struct drm_device
*dev
)
13401 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13403 /* This function can be called both from intel_modeset_setup_hw_state or
13404 * at a very early point in our resume sequence, where the power well
13405 * structures are not yet restored. Since this function is at a very
13406 * paranoid "someone might have enabled VGA while we were not looking"
13407 * level, just check if the power well is enabled instead of trying to
13408 * follow the "don't touch the power well if we don't need it" policy
13409 * the rest of the driver uses. */
13410 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_VGA
))
13413 i915_redisable_vga_power_on(dev
);
13416 static bool primary_get_hw_state(struct intel_crtc
*crtc
)
13418 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
13423 return I915_READ(DSPCNTR(crtc
->plane
)) & DISPLAY_PLANE_ENABLE
;
13426 static void intel_modeset_readout_hw_state(struct drm_device
*dev
)
13428 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13430 struct intel_crtc
*crtc
;
13431 struct intel_encoder
*encoder
;
13432 struct intel_connector
*connector
;
13435 for_each_intel_crtc(dev
, crtc
) {
13436 memset(&crtc
->config
, 0, sizeof(crtc
->config
));
13438 crtc
->config
.quirks
|= PIPE_CONFIG_QUIRK_INHERITED_MODE
;
13440 crtc
->active
= dev_priv
->display
.get_pipe_config(crtc
,
13443 crtc
->base
.enabled
= crtc
->active
;
13444 crtc
->primary_enabled
= primary_get_hw_state(crtc
);
13446 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13447 crtc
->base
.base
.id
,
13448 crtc
->active
? "enabled" : "disabled");
13451 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
13452 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
13454 pll
->on
= pll
->get_hw_state(dev_priv
, pll
,
13455 &pll
->config
.hw_state
);
13457 pll
->config
.crtc_mask
= 0;
13458 for_each_intel_crtc(dev
, crtc
) {
13459 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
) {
13461 pll
->config
.crtc_mask
|= 1 << crtc
->pipe
;
13465 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
13466 pll
->name
, pll
->config
.crtc_mask
, pll
->on
);
13468 if (pll
->config
.crtc_mask
)
13469 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
13472 for_each_intel_encoder(dev
, encoder
) {
13475 if (encoder
->get_hw_state(encoder
, &pipe
)) {
13476 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
13477 encoder
->base
.crtc
= &crtc
->base
;
13478 encoder
->get_config(encoder
, &crtc
->config
);
13480 encoder
->base
.crtc
= NULL
;
13483 encoder
->connectors_active
= false;
13484 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13485 encoder
->base
.base
.id
,
13486 encoder
->base
.name
,
13487 encoder
->base
.crtc
? "enabled" : "disabled",
13491 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
13493 if (connector
->get_hw_state(connector
)) {
13494 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
13495 connector
->encoder
->connectors_active
= true;
13496 connector
->base
.encoder
= &connector
->encoder
->base
;
13498 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
13499 connector
->base
.encoder
= NULL
;
13501 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13502 connector
->base
.base
.id
,
13503 connector
->base
.name
,
13504 connector
->base
.encoder
? "enabled" : "disabled");
13508 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13509 * and i915 state tracking structures. */
13510 void intel_modeset_setup_hw_state(struct drm_device
*dev
,
13511 bool force_restore
)
13513 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13515 struct intel_crtc
*crtc
;
13516 struct intel_encoder
*encoder
;
13519 intel_modeset_readout_hw_state(dev
);
13522 * Now that we have the config, copy it to each CRTC struct
13523 * Note that this could go away if we move to using crtc_config
13524 * checking everywhere.
13526 for_each_intel_crtc(dev
, crtc
) {
13527 if (crtc
->active
&& i915
.fastboot
) {
13528 intel_mode_from_pipe_config(&crtc
->base
.mode
, &crtc
->config
);
13529 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13530 crtc
->base
.base
.id
);
13531 drm_mode_debug_printmodeline(&crtc
->base
.mode
);
13535 /* HW state is read out, now we need to sanitize this mess. */
13536 for_each_intel_encoder(dev
, encoder
) {
13537 intel_sanitize_encoder(encoder
);
13540 for_each_pipe(dev_priv
, pipe
) {
13541 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
13542 intel_sanitize_crtc(crtc
);
13543 intel_dump_pipe_config(crtc
, &crtc
->config
, "[setup_hw_state]");
13546 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
13547 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
13549 if (!pll
->on
|| pll
->active
)
13552 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll
->name
);
13554 pll
->disable(dev_priv
, pll
);
13559 skl_wm_get_hw_state(dev
);
13560 else if (HAS_PCH_SPLIT(dev
))
13561 ilk_wm_get_hw_state(dev
);
13563 if (force_restore
) {
13564 i915_redisable_vga(dev
);
13567 * We need to use raw interfaces for restoring state to avoid
13568 * checking (bogus) intermediate states.
13570 for_each_pipe(dev_priv
, pipe
) {
13571 struct drm_crtc
*crtc
=
13572 dev_priv
->pipe_to_crtc_mapping
[pipe
];
13574 intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
,
13575 crtc
->primary
->fb
);
13578 intel_modeset_update_staged_output_state(dev
);
13581 intel_modeset_check_state(dev
);
13584 void intel_modeset_gem_init(struct drm_device
*dev
)
13586 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13587 struct drm_crtc
*c
;
13588 struct drm_i915_gem_object
*obj
;
13590 mutex_lock(&dev
->struct_mutex
);
13591 intel_init_gt_powersave(dev
);
13592 mutex_unlock(&dev
->struct_mutex
);
13595 * There may be no VBT; and if the BIOS enabled SSC we can
13596 * just keep using it to avoid unnecessary flicker. Whereas if the
13597 * BIOS isn't using it, don't assume it will work even if the VBT
13598 * indicates as much.
13600 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
13601 dev_priv
->vbt
.lvds_use_ssc
= !!(I915_READ(PCH_DREF_CONTROL
) &
13604 intel_modeset_init_hw(dev
);
13606 intel_setup_overlay(dev
);
13609 * Make sure any fbs we allocated at startup are properly
13610 * pinned & fenced. When we do the allocation it's too early
13613 mutex_lock(&dev
->struct_mutex
);
13614 for_each_crtc(dev
, c
) {
13615 obj
= intel_fb_obj(c
->primary
->fb
);
13619 if (intel_pin_and_fence_fb_obj(c
->primary
,
13622 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13623 to_intel_crtc(c
)->pipe
);
13624 drm_framebuffer_unreference(c
->primary
->fb
);
13625 c
->primary
->fb
= NULL
;
13628 mutex_unlock(&dev
->struct_mutex
);
13630 intel_backlight_register(dev
);
13633 void intel_connector_unregister(struct intel_connector
*intel_connector
)
13635 struct drm_connector
*connector
= &intel_connector
->base
;
13637 intel_panel_destroy_backlight(connector
);
13638 drm_connector_unregister(connector
);
13641 void intel_modeset_cleanup(struct drm_device
*dev
)
13643 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13644 struct drm_connector
*connector
;
13646 intel_disable_gt_powersave(dev
);
13648 intel_backlight_unregister(dev
);
13651 * Interrupts and polling as the first thing to avoid creating havoc.
13652 * Too much stuff here (turning of connectors, ...) would
13653 * experience fancy races otherwise.
13655 intel_irq_uninstall(dev_priv
);
13658 * Due to the hpd irq storm handling the hotplug work can re-arm the
13659 * poll handlers. Hence disable polling after hpd handling is shut down.
13661 drm_kms_helper_poll_fini(dev
);
13663 mutex_lock(&dev
->struct_mutex
);
13665 intel_unregister_dsm_handler();
13667 intel_disable_fbc(dev
);
13669 ironlake_teardown_rc6(dev
);
13671 mutex_unlock(&dev
->struct_mutex
);
13673 /* flush any delayed tasks or pending work */
13674 flush_scheduled_work();
13676 /* destroy the backlight and sysfs files before encoders/connectors */
13677 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
13678 struct intel_connector
*intel_connector
;
13680 intel_connector
= to_intel_connector(connector
);
13681 intel_connector
->unregister(intel_connector
);
13684 drm_mode_config_cleanup(dev
);
13686 intel_cleanup_overlay(dev
);
13688 mutex_lock(&dev
->struct_mutex
);
13689 intel_cleanup_gt_powersave(dev
);
13690 mutex_unlock(&dev
->struct_mutex
);
13694 * Return which encoder is currently attached for connector.
13696 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
13698 return &intel_attached_encoder(connector
)->base
;
13701 void intel_connector_attach_encoder(struct intel_connector
*connector
,
13702 struct intel_encoder
*encoder
)
13704 connector
->encoder
= encoder
;
13705 drm_mode_connector_attach_encoder(&connector
->base
,
13710 * set vga decode state - true == enable VGA decode
13712 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
13714 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13715 unsigned reg
= INTEL_INFO(dev
)->gen
>= 6 ? SNB_GMCH_CTRL
: INTEL_GMCH_CTRL
;
13718 if (pci_read_config_word(dev_priv
->bridge_dev
, reg
, &gmch_ctrl
)) {
13719 DRM_ERROR("failed to read control word\n");
13723 if (!!(gmch_ctrl
& INTEL_GMCH_VGA_DISABLE
) == !state
)
13727 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
13729 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
13731 if (pci_write_config_word(dev_priv
->bridge_dev
, reg
, gmch_ctrl
)) {
13732 DRM_ERROR("failed to write control word\n");
13739 struct intel_display_error_state
{
13741 u32 power_well_driver
;
13743 int num_transcoders
;
13745 struct intel_cursor_error_state
{
13750 } cursor
[I915_MAX_PIPES
];
13752 struct intel_pipe_error_state
{
13753 bool power_domain_on
;
13756 } pipe
[I915_MAX_PIPES
];
13758 struct intel_plane_error_state
{
13766 } plane
[I915_MAX_PIPES
];
13768 struct intel_transcoder_error_state
{
13769 bool power_domain_on
;
13770 enum transcoder cpu_transcoder
;
13783 struct intel_display_error_state
*
13784 intel_display_capture_error_state(struct drm_device
*dev
)
13786 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13787 struct intel_display_error_state
*error
;
13788 int transcoders
[] = {
13796 if (INTEL_INFO(dev
)->num_pipes
== 0)
13799 error
= kzalloc(sizeof(*error
), GFP_ATOMIC
);
13803 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
13804 error
->power_well_driver
= I915_READ(HSW_PWR_WELL_DRIVER
);
13806 for_each_pipe(dev_priv
, i
) {
13807 error
->pipe
[i
].power_domain_on
=
13808 __intel_display_power_is_enabled(dev_priv
,
13809 POWER_DOMAIN_PIPE(i
));
13810 if (!error
->pipe
[i
].power_domain_on
)
13813 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
13814 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
13815 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
13817 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
13818 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
13819 if (INTEL_INFO(dev
)->gen
<= 3) {
13820 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
13821 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
13823 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
13824 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
13825 if (INTEL_INFO(dev
)->gen
>= 4) {
13826 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
13827 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
13830 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
13832 if (HAS_GMCH_DISPLAY(dev
))
13833 error
->pipe
[i
].stat
= I915_READ(PIPESTAT(i
));
13836 error
->num_transcoders
= INTEL_INFO(dev
)->num_pipes
;
13837 if (HAS_DDI(dev_priv
->dev
))
13838 error
->num_transcoders
++; /* Account for eDP. */
13840 for (i
= 0; i
< error
->num_transcoders
; i
++) {
13841 enum transcoder cpu_transcoder
= transcoders
[i
];
13843 error
->transcoder
[i
].power_domain_on
=
13844 __intel_display_power_is_enabled(dev_priv
,
13845 POWER_DOMAIN_TRANSCODER(cpu_transcoder
));
13846 if (!error
->transcoder
[i
].power_domain_on
)
13849 error
->transcoder
[i
].cpu_transcoder
= cpu_transcoder
;
13851 error
->transcoder
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
13852 error
->transcoder
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
13853 error
->transcoder
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
13854 error
->transcoder
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
13855 error
->transcoder
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
13856 error
->transcoder
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
13857 error
->transcoder
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
13863 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13866 intel_display_print_error_state(struct drm_i915_error_state_buf
*m
,
13867 struct drm_device
*dev
,
13868 struct intel_display_error_state
*error
)
13870 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13876 err_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev
)->num_pipes
);
13877 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
13878 err_printf(m
, "PWR_WELL_CTL2: %08x\n",
13879 error
->power_well_driver
);
13880 for_each_pipe(dev_priv
, i
) {
13881 err_printf(m
, "Pipe [%d]:\n", i
);
13882 err_printf(m
, " Power: %s\n",
13883 error
->pipe
[i
].power_domain_on
? "on" : "off");
13884 err_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
13885 err_printf(m
, " STAT: %08x\n", error
->pipe
[i
].stat
);
13887 err_printf(m
, "Plane [%d]:\n", i
);
13888 err_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
13889 err_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
13890 if (INTEL_INFO(dev
)->gen
<= 3) {
13891 err_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
13892 err_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
13894 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
13895 err_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
13896 if (INTEL_INFO(dev
)->gen
>= 4) {
13897 err_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
13898 err_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
13901 err_printf(m
, "Cursor [%d]:\n", i
);
13902 err_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
13903 err_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
13904 err_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);
13907 for (i
= 0; i
< error
->num_transcoders
; i
++) {
13908 err_printf(m
, "CPU transcoder: %c\n",
13909 transcoder_name(error
->transcoder
[i
].cpu_transcoder
));
13910 err_printf(m
, " Power: %s\n",
13911 error
->transcoder
[i
].power_domain_on
? "on" : "off");
13912 err_printf(m
, " CONF: %08x\n", error
->transcoder
[i
].conf
);
13913 err_printf(m
, " HTOTAL: %08x\n", error
->transcoder
[i
].htotal
);
13914 err_printf(m
, " HBLANK: %08x\n", error
->transcoder
[i
].hblank
);
13915 err_printf(m
, " HSYNC: %08x\n", error
->transcoder
[i
].hsync
);
13916 err_printf(m
, " VTOTAL: %08x\n", error
->transcoder
[i
].vtotal
);
13917 err_printf(m
, " VBLANK: %08x\n", error
->transcoder
[i
].vblank
);
13918 err_printf(m
, " VSYNC: %08x\n", error
->transcoder
[i
].vsync
);
13922 void intel_modeset_preclose(struct drm_device
*dev
, struct drm_file
*file
)
13924 struct intel_crtc
*crtc
;
13926 for_each_intel_crtc(dev
, crtc
) {
13927 struct intel_unpin_work
*work
;
13929 spin_lock_irq(&dev
->event_lock
);
13931 work
= crtc
->unpin_work
;
13933 if (work
&& work
->event
&&
13934 work
->event
->base
.file_priv
== file
) {
13935 kfree(work
->event
);
13936 work
->event
= NULL
;
13939 spin_unlock_irq(&dev
->event_lock
);