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drm/i915: Disable SSC for outputs other than LVDS or DP
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/module.h>
28 #include <linux/input.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include <linux/vgaarb.h>
33 #include "drmP.h"
34 #include "intel_drv.h"
35 #include "i915_drm.h"
36 #include "i915_drv.h"
37 #include "i915_trace.h"
38 #include "drm_dp_helper.h"
39
40 #include "drm_crtc_helper.h"
41
42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
43
44 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
45 static void intel_update_watermarks(struct drm_device *dev);
46 static void intel_increase_pllclock(struct drm_crtc *crtc);
47 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
48
49 typedef struct {
50 /* given values */
51 int n;
52 int m1, m2;
53 int p1, p2;
54 /* derived values */
55 int dot;
56 int vco;
57 int m;
58 int p;
59 } intel_clock_t;
60
61 typedef struct {
62 int min, max;
63 } intel_range_t;
64
65 typedef struct {
66 int dot_limit;
67 int p2_slow, p2_fast;
68 } intel_p2_t;
69
70 #define INTEL_P2_NUM 2
71 typedef struct intel_limit intel_limit_t;
72 struct intel_limit {
73 intel_range_t dot, vco, n, m, m1, m2, p, p1;
74 intel_p2_t p2;
75 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
76 int, int, intel_clock_t *);
77 };
78
79 #define I8XX_DOT_MIN 25000
80 #define I8XX_DOT_MAX 350000
81 #define I8XX_VCO_MIN 930000
82 #define I8XX_VCO_MAX 1400000
83 #define I8XX_N_MIN 3
84 #define I8XX_N_MAX 16
85 #define I8XX_M_MIN 96
86 #define I8XX_M_MAX 140
87 #define I8XX_M1_MIN 18
88 #define I8XX_M1_MAX 26
89 #define I8XX_M2_MIN 6
90 #define I8XX_M2_MAX 16
91 #define I8XX_P_MIN 4
92 #define I8XX_P_MAX 128
93 #define I8XX_P1_MIN 2
94 #define I8XX_P1_MAX 33
95 #define I8XX_P1_LVDS_MIN 1
96 #define I8XX_P1_LVDS_MAX 6
97 #define I8XX_P2_SLOW 4
98 #define I8XX_P2_FAST 2
99 #define I8XX_P2_LVDS_SLOW 14
100 #define I8XX_P2_LVDS_FAST 7
101 #define I8XX_P2_SLOW_LIMIT 165000
102
103 #define I9XX_DOT_MIN 20000
104 #define I9XX_DOT_MAX 400000
105 #define I9XX_VCO_MIN 1400000
106 #define I9XX_VCO_MAX 2800000
107 #define PINEVIEW_VCO_MIN 1700000
108 #define PINEVIEW_VCO_MAX 3500000
109 #define I9XX_N_MIN 1
110 #define I9XX_N_MAX 6
111 /* Pineview's Ncounter is a ring counter */
112 #define PINEVIEW_N_MIN 3
113 #define PINEVIEW_N_MAX 6
114 #define I9XX_M_MIN 70
115 #define I9XX_M_MAX 120
116 #define PINEVIEW_M_MIN 2
117 #define PINEVIEW_M_MAX 256
118 #define I9XX_M1_MIN 10
119 #define I9XX_M1_MAX 22
120 #define I9XX_M2_MIN 5
121 #define I9XX_M2_MAX 9
122 /* Pineview M1 is reserved, and must be 0 */
123 #define PINEVIEW_M1_MIN 0
124 #define PINEVIEW_M1_MAX 0
125 #define PINEVIEW_M2_MIN 0
126 #define PINEVIEW_M2_MAX 254
127 #define I9XX_P_SDVO_DAC_MIN 5
128 #define I9XX_P_SDVO_DAC_MAX 80
129 #define I9XX_P_LVDS_MIN 7
130 #define I9XX_P_LVDS_MAX 98
131 #define PINEVIEW_P_LVDS_MIN 7
132 #define PINEVIEW_P_LVDS_MAX 112
133 #define I9XX_P1_MIN 1
134 #define I9XX_P1_MAX 8
135 #define I9XX_P2_SDVO_DAC_SLOW 10
136 #define I9XX_P2_SDVO_DAC_FAST 5
137 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
138 #define I9XX_P2_LVDS_SLOW 14
139 #define I9XX_P2_LVDS_FAST 7
140 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
141
142 /*The parameter is for SDVO on G4x platform*/
143 #define G4X_DOT_SDVO_MIN 25000
144 #define G4X_DOT_SDVO_MAX 270000
145 #define G4X_VCO_MIN 1750000
146 #define G4X_VCO_MAX 3500000
147 #define G4X_N_SDVO_MIN 1
148 #define G4X_N_SDVO_MAX 4
149 #define G4X_M_SDVO_MIN 104
150 #define G4X_M_SDVO_MAX 138
151 #define G4X_M1_SDVO_MIN 17
152 #define G4X_M1_SDVO_MAX 23
153 #define G4X_M2_SDVO_MIN 5
154 #define G4X_M2_SDVO_MAX 11
155 #define G4X_P_SDVO_MIN 10
156 #define G4X_P_SDVO_MAX 30
157 #define G4X_P1_SDVO_MIN 1
158 #define G4X_P1_SDVO_MAX 3
159 #define G4X_P2_SDVO_SLOW 10
160 #define G4X_P2_SDVO_FAST 10
161 #define G4X_P2_SDVO_LIMIT 270000
162
163 /*The parameter is for HDMI_DAC on G4x platform*/
164 #define G4X_DOT_HDMI_DAC_MIN 22000
165 #define G4X_DOT_HDMI_DAC_MAX 400000
166 #define G4X_N_HDMI_DAC_MIN 1
167 #define G4X_N_HDMI_DAC_MAX 4
168 #define G4X_M_HDMI_DAC_MIN 104
169 #define G4X_M_HDMI_DAC_MAX 138
170 #define G4X_M1_HDMI_DAC_MIN 16
171 #define G4X_M1_HDMI_DAC_MAX 23
172 #define G4X_M2_HDMI_DAC_MIN 5
173 #define G4X_M2_HDMI_DAC_MAX 11
174 #define G4X_P_HDMI_DAC_MIN 5
175 #define G4X_P_HDMI_DAC_MAX 80
176 #define G4X_P1_HDMI_DAC_MIN 1
177 #define G4X_P1_HDMI_DAC_MAX 8
178 #define G4X_P2_HDMI_DAC_SLOW 10
179 #define G4X_P2_HDMI_DAC_FAST 5
180 #define G4X_P2_HDMI_DAC_LIMIT 165000
181
182 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
184 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
185 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
186 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
187 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
188 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
190 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
192 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
193 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
194 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
196 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
197 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
198 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
199 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
200
201 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
203 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
204 #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
205 #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
206 #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
207 #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
208 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
209 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
210 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
211 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
212 #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
213 #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
214 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
215 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
216 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
217 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
218 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
219
220 /*The parameter is for DISPLAY PORT on G4x platform*/
221 #define G4X_DOT_DISPLAY_PORT_MIN 161670
222 #define G4X_DOT_DISPLAY_PORT_MAX 227000
223 #define G4X_N_DISPLAY_PORT_MIN 1
224 #define G4X_N_DISPLAY_PORT_MAX 2
225 #define G4X_M_DISPLAY_PORT_MIN 97
226 #define G4X_M_DISPLAY_PORT_MAX 108
227 #define G4X_M1_DISPLAY_PORT_MIN 0x10
228 #define G4X_M1_DISPLAY_PORT_MAX 0x12
229 #define G4X_M2_DISPLAY_PORT_MIN 0x05
230 #define G4X_M2_DISPLAY_PORT_MAX 0x06
231 #define G4X_P_DISPLAY_PORT_MIN 10
232 #define G4X_P_DISPLAY_PORT_MAX 20
233 #define G4X_P1_DISPLAY_PORT_MIN 1
234 #define G4X_P1_DISPLAY_PORT_MAX 2
235 #define G4X_P2_DISPLAY_PORT_SLOW 10
236 #define G4X_P2_DISPLAY_PORT_FAST 10
237 #define G4X_P2_DISPLAY_PORT_LIMIT 0
238
239 /* Ironlake / Sandybridge */
240 /* as we calculate clock using (register_value + 2) for
241 N/M1/M2, so here the range value for them is (actual_value-2).
242 */
243 #define IRONLAKE_DOT_MIN 25000
244 #define IRONLAKE_DOT_MAX 350000
245 #define IRONLAKE_VCO_MIN 1760000
246 #define IRONLAKE_VCO_MAX 3510000
247 #define IRONLAKE_M1_MIN 12
248 #define IRONLAKE_M1_MAX 22
249 #define IRONLAKE_M2_MIN 5
250 #define IRONLAKE_M2_MAX 9
251 #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
252
253 /* We have parameter ranges for different type of outputs. */
254
255 /* DAC & HDMI Refclk 120Mhz */
256 #define IRONLAKE_DAC_N_MIN 1
257 #define IRONLAKE_DAC_N_MAX 5
258 #define IRONLAKE_DAC_M_MIN 79
259 #define IRONLAKE_DAC_M_MAX 127
260 #define IRONLAKE_DAC_P_MIN 5
261 #define IRONLAKE_DAC_P_MAX 80
262 #define IRONLAKE_DAC_P1_MIN 1
263 #define IRONLAKE_DAC_P1_MAX 8
264 #define IRONLAKE_DAC_P2_SLOW 10
265 #define IRONLAKE_DAC_P2_FAST 5
266
267 /* LVDS single-channel 120Mhz refclk */
268 #define IRONLAKE_LVDS_S_N_MIN 1
269 #define IRONLAKE_LVDS_S_N_MAX 3
270 #define IRONLAKE_LVDS_S_M_MIN 79
271 #define IRONLAKE_LVDS_S_M_MAX 118
272 #define IRONLAKE_LVDS_S_P_MIN 28
273 #define IRONLAKE_LVDS_S_P_MAX 112
274 #define IRONLAKE_LVDS_S_P1_MIN 2
275 #define IRONLAKE_LVDS_S_P1_MAX 8
276 #define IRONLAKE_LVDS_S_P2_SLOW 14
277 #define IRONLAKE_LVDS_S_P2_FAST 14
278
279 /* LVDS dual-channel 120Mhz refclk */
280 #define IRONLAKE_LVDS_D_N_MIN 1
281 #define IRONLAKE_LVDS_D_N_MAX 3
282 #define IRONLAKE_LVDS_D_M_MIN 79
283 #define IRONLAKE_LVDS_D_M_MAX 127
284 #define IRONLAKE_LVDS_D_P_MIN 14
285 #define IRONLAKE_LVDS_D_P_MAX 56
286 #define IRONLAKE_LVDS_D_P1_MIN 2
287 #define IRONLAKE_LVDS_D_P1_MAX 8
288 #define IRONLAKE_LVDS_D_P2_SLOW 7
289 #define IRONLAKE_LVDS_D_P2_FAST 7
290
291 /* LVDS single-channel 100Mhz refclk */
292 #define IRONLAKE_LVDS_S_SSC_N_MIN 1
293 #define IRONLAKE_LVDS_S_SSC_N_MAX 2
294 #define IRONLAKE_LVDS_S_SSC_M_MIN 79
295 #define IRONLAKE_LVDS_S_SSC_M_MAX 126
296 #define IRONLAKE_LVDS_S_SSC_P_MIN 28
297 #define IRONLAKE_LVDS_S_SSC_P_MAX 112
298 #define IRONLAKE_LVDS_S_SSC_P1_MIN 2
299 #define IRONLAKE_LVDS_S_SSC_P1_MAX 8
300 #define IRONLAKE_LVDS_S_SSC_P2_SLOW 14
301 #define IRONLAKE_LVDS_S_SSC_P2_FAST 14
302
303 /* LVDS dual-channel 100Mhz refclk */
304 #define IRONLAKE_LVDS_D_SSC_N_MIN 1
305 #define IRONLAKE_LVDS_D_SSC_N_MAX 3
306 #define IRONLAKE_LVDS_D_SSC_M_MIN 79
307 #define IRONLAKE_LVDS_D_SSC_M_MAX 126
308 #define IRONLAKE_LVDS_D_SSC_P_MIN 14
309 #define IRONLAKE_LVDS_D_SSC_P_MAX 42
310 #define IRONLAKE_LVDS_D_SSC_P1_MIN 2
311 #define IRONLAKE_LVDS_D_SSC_P1_MAX 6
312 #define IRONLAKE_LVDS_D_SSC_P2_SLOW 7
313 #define IRONLAKE_LVDS_D_SSC_P2_FAST 7
314
315 /* DisplayPort */
316 #define IRONLAKE_DP_N_MIN 1
317 #define IRONLAKE_DP_N_MAX 2
318 #define IRONLAKE_DP_M_MIN 81
319 #define IRONLAKE_DP_M_MAX 90
320 #define IRONLAKE_DP_P_MIN 10
321 #define IRONLAKE_DP_P_MAX 20
322 #define IRONLAKE_DP_P2_FAST 10
323 #define IRONLAKE_DP_P2_SLOW 10
324 #define IRONLAKE_DP_P2_LIMIT 0
325 #define IRONLAKE_DP_P1_MIN 1
326 #define IRONLAKE_DP_P1_MAX 2
327
328 /* FDI */
329 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
330
331 static bool
332 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
333 int target, int refclk, intel_clock_t *best_clock);
334 static bool
335 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
336 int target, int refclk, intel_clock_t *best_clock);
337
338 static bool
339 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
340 int target, int refclk, intel_clock_t *best_clock);
341 static bool
342 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
343 int target, int refclk, intel_clock_t *best_clock);
344
345 static inline u32 /* units of 100MHz */
346 intel_fdi_link_freq(struct drm_device *dev)
347 {
348 if (IS_GEN5(dev)) {
349 struct drm_i915_private *dev_priv = dev->dev_private;
350 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
351 } else
352 return 27;
353 }
354
355 static const intel_limit_t intel_limits_i8xx_dvo = {
356 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
357 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
358 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
359 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
360 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
361 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
362 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
363 .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
364 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
365 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
366 .find_pll = intel_find_best_PLL,
367 };
368
369 static const intel_limit_t intel_limits_i8xx_lvds = {
370 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
371 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
372 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
373 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
374 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
375 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
376 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
377 .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
378 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
379 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
380 .find_pll = intel_find_best_PLL,
381 };
382
383 static const intel_limit_t intel_limits_i9xx_sdvo = {
384 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
385 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
386 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
387 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
388 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
389 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
390 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
391 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
392 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
393 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
394 .find_pll = intel_find_best_PLL,
395 };
396
397 static const intel_limit_t intel_limits_i9xx_lvds = {
398 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
399 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
400 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
401 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
402 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
403 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
404 .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
405 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
406 /* The single-channel range is 25-112Mhz, and dual-channel
407 * is 80-224Mhz. Prefer single channel as much as possible.
408 */
409 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
410 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
411 .find_pll = intel_find_best_PLL,
412 };
413
414 /* below parameter and function is for G4X Chipset Family*/
415 static const intel_limit_t intel_limits_g4x_sdvo = {
416 .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
417 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
418 .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },
419 .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },
420 .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },
421 .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },
422 .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },
423 .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
424 .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,
425 .p2_slow = G4X_P2_SDVO_SLOW,
426 .p2_fast = G4X_P2_SDVO_FAST
427 },
428 .find_pll = intel_g4x_find_best_PLL,
429 };
430
431 static const intel_limit_t intel_limits_g4x_hdmi = {
432 .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },
433 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
434 .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },
435 .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },
436 .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },
437 .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },
438 .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },
439 .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
440 .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
441 .p2_slow = G4X_P2_HDMI_DAC_SLOW,
442 .p2_fast = G4X_P2_HDMI_DAC_FAST
443 },
444 .find_pll = intel_g4x_find_best_PLL,
445 };
446
447 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
448 .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
449 .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
450 .vco = { .min = G4X_VCO_MIN,
451 .max = G4X_VCO_MAX },
452 .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
453 .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
454 .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
455 .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
456 .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
457 .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
458 .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
459 .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
460 .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
461 .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
462 .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
463 .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
464 .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
465 .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
466 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
467 },
468 .find_pll = intel_g4x_find_best_PLL,
469 };
470
471 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
472 .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
473 .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
474 .vco = { .min = G4X_VCO_MIN,
475 .max = G4X_VCO_MAX },
476 .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
477 .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
478 .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
479 .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
480 .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
481 .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
482 .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
483 .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
484 .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
485 .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
486 .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
487 .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
488 .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
489 .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
490 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
491 },
492 .find_pll = intel_g4x_find_best_PLL,
493 };
494
495 static const intel_limit_t intel_limits_g4x_display_port = {
496 .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
497 .max = G4X_DOT_DISPLAY_PORT_MAX },
498 .vco = { .min = G4X_VCO_MIN,
499 .max = G4X_VCO_MAX},
500 .n = { .min = G4X_N_DISPLAY_PORT_MIN,
501 .max = G4X_N_DISPLAY_PORT_MAX },
502 .m = { .min = G4X_M_DISPLAY_PORT_MIN,
503 .max = G4X_M_DISPLAY_PORT_MAX },
504 .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN,
505 .max = G4X_M1_DISPLAY_PORT_MAX },
506 .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,
507 .max = G4X_M2_DISPLAY_PORT_MAX },
508 .p = { .min = G4X_P_DISPLAY_PORT_MIN,
509 .max = G4X_P_DISPLAY_PORT_MAX },
510 .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
511 .max = G4X_P1_DISPLAY_PORT_MAX},
512 .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
513 .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
514 .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
515 .find_pll = intel_find_pll_g4x_dp,
516 };
517
518 static const intel_limit_t intel_limits_pineview_sdvo = {
519 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
520 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
521 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
522 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
523 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
524 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
525 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
526 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
527 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
528 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
529 .find_pll = intel_find_best_PLL,
530 };
531
532 static const intel_limit_t intel_limits_pineview_lvds = {
533 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
534 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
535 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
536 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
537 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
538 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
539 .p = { .min = PINEVIEW_P_LVDS_MIN, .max = PINEVIEW_P_LVDS_MAX },
540 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
541 /* Pineview only supports single-channel mode. */
542 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
543 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
544 .find_pll = intel_find_best_PLL,
545 };
546
547 static const intel_limit_t intel_limits_ironlake_dac = {
548 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
549 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
550 .n = { .min = IRONLAKE_DAC_N_MIN, .max = IRONLAKE_DAC_N_MAX },
551 .m = { .min = IRONLAKE_DAC_M_MIN, .max = IRONLAKE_DAC_M_MAX },
552 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
553 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
554 .p = { .min = IRONLAKE_DAC_P_MIN, .max = IRONLAKE_DAC_P_MAX },
555 .p1 = { .min = IRONLAKE_DAC_P1_MIN, .max = IRONLAKE_DAC_P1_MAX },
556 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
557 .p2_slow = IRONLAKE_DAC_P2_SLOW,
558 .p2_fast = IRONLAKE_DAC_P2_FAST },
559 .find_pll = intel_g4x_find_best_PLL,
560 };
561
562 static const intel_limit_t intel_limits_ironlake_single_lvds = {
563 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
564 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
565 .n = { .min = IRONLAKE_LVDS_S_N_MIN, .max = IRONLAKE_LVDS_S_N_MAX },
566 .m = { .min = IRONLAKE_LVDS_S_M_MIN, .max = IRONLAKE_LVDS_S_M_MAX },
567 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
568 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
569 .p = { .min = IRONLAKE_LVDS_S_P_MIN, .max = IRONLAKE_LVDS_S_P_MAX },
570 .p1 = { .min = IRONLAKE_LVDS_S_P1_MIN, .max = IRONLAKE_LVDS_S_P1_MAX },
571 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
572 .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
573 .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
574 .find_pll = intel_g4x_find_best_PLL,
575 };
576
577 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
578 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
579 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
580 .n = { .min = IRONLAKE_LVDS_D_N_MIN, .max = IRONLAKE_LVDS_D_N_MAX },
581 .m = { .min = IRONLAKE_LVDS_D_M_MIN, .max = IRONLAKE_LVDS_D_M_MAX },
582 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
583 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
584 .p = { .min = IRONLAKE_LVDS_D_P_MIN, .max = IRONLAKE_LVDS_D_P_MAX },
585 .p1 = { .min = IRONLAKE_LVDS_D_P1_MIN, .max = IRONLAKE_LVDS_D_P1_MAX },
586 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
587 .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
588 .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
589 .find_pll = intel_g4x_find_best_PLL,
590 };
591
592 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
593 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
594 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
595 .n = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
596 .m = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
597 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
598 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
599 .p = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
600 .p1 = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
601 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
602 .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
603 .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
604 .find_pll = intel_g4x_find_best_PLL,
605 };
606
607 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
608 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
609 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
610 .n = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
611 .m = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
612 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
613 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
614 .p = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
615 .p1 = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
616 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
617 .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
618 .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
619 .find_pll = intel_g4x_find_best_PLL,
620 };
621
622 static const intel_limit_t intel_limits_ironlake_display_port = {
623 .dot = { .min = IRONLAKE_DOT_MIN,
624 .max = IRONLAKE_DOT_MAX },
625 .vco = { .min = IRONLAKE_VCO_MIN,
626 .max = IRONLAKE_VCO_MAX},
627 .n = { .min = IRONLAKE_DP_N_MIN,
628 .max = IRONLAKE_DP_N_MAX },
629 .m = { .min = IRONLAKE_DP_M_MIN,
630 .max = IRONLAKE_DP_M_MAX },
631 .m1 = { .min = IRONLAKE_M1_MIN,
632 .max = IRONLAKE_M1_MAX },
633 .m2 = { .min = IRONLAKE_M2_MIN,
634 .max = IRONLAKE_M2_MAX },
635 .p = { .min = IRONLAKE_DP_P_MIN,
636 .max = IRONLAKE_DP_P_MAX },
637 .p1 = { .min = IRONLAKE_DP_P1_MIN,
638 .max = IRONLAKE_DP_P1_MAX},
639 .p2 = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
640 .p2_slow = IRONLAKE_DP_P2_SLOW,
641 .p2_fast = IRONLAKE_DP_P2_FAST },
642 .find_pll = intel_find_pll_ironlake_dp,
643 };
644
645 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
646 int refclk)
647 {
648 struct drm_device *dev = crtc->dev;
649 struct drm_i915_private *dev_priv = dev->dev_private;
650 const intel_limit_t *limit;
651
652 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
653 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
654 LVDS_CLKB_POWER_UP) {
655 /* LVDS dual channel */
656 if (refclk == 100000)
657 limit = &intel_limits_ironlake_dual_lvds_100m;
658 else
659 limit = &intel_limits_ironlake_dual_lvds;
660 } else {
661 if (refclk == 100000)
662 limit = &intel_limits_ironlake_single_lvds_100m;
663 else
664 limit = &intel_limits_ironlake_single_lvds;
665 }
666 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
667 HAS_eDP)
668 limit = &intel_limits_ironlake_display_port;
669 else
670 limit = &intel_limits_ironlake_dac;
671
672 return limit;
673 }
674
675 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
676 {
677 struct drm_device *dev = crtc->dev;
678 struct drm_i915_private *dev_priv = dev->dev_private;
679 const intel_limit_t *limit;
680
681 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
682 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
683 LVDS_CLKB_POWER_UP)
684 /* LVDS with dual channel */
685 limit = &intel_limits_g4x_dual_channel_lvds;
686 else
687 /* LVDS with dual channel */
688 limit = &intel_limits_g4x_single_channel_lvds;
689 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
690 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
691 limit = &intel_limits_g4x_hdmi;
692 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
693 limit = &intel_limits_g4x_sdvo;
694 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
695 limit = &intel_limits_g4x_display_port;
696 } else /* The option is for other outputs */
697 limit = &intel_limits_i9xx_sdvo;
698
699 return limit;
700 }
701
702 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
703 {
704 struct drm_device *dev = crtc->dev;
705 const intel_limit_t *limit;
706
707 if (HAS_PCH_SPLIT(dev))
708 limit = intel_ironlake_limit(crtc, refclk);
709 else if (IS_G4X(dev)) {
710 limit = intel_g4x_limit(crtc);
711 } else if (IS_PINEVIEW(dev)) {
712 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
713 limit = &intel_limits_pineview_lvds;
714 else
715 limit = &intel_limits_pineview_sdvo;
716 } else if (!IS_GEN2(dev)) {
717 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
718 limit = &intel_limits_i9xx_lvds;
719 else
720 limit = &intel_limits_i9xx_sdvo;
721 } else {
722 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
723 limit = &intel_limits_i8xx_lvds;
724 else
725 limit = &intel_limits_i8xx_dvo;
726 }
727 return limit;
728 }
729
730 /* m1 is reserved as 0 in Pineview, n is a ring counter */
731 static void pineview_clock(int refclk, intel_clock_t *clock)
732 {
733 clock->m = clock->m2 + 2;
734 clock->p = clock->p1 * clock->p2;
735 clock->vco = refclk * clock->m / clock->n;
736 clock->dot = clock->vco / clock->p;
737 }
738
739 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
740 {
741 if (IS_PINEVIEW(dev)) {
742 pineview_clock(refclk, clock);
743 return;
744 }
745 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
746 clock->p = clock->p1 * clock->p2;
747 clock->vco = refclk * clock->m / (clock->n + 2);
748 clock->dot = clock->vco / clock->p;
749 }
750
751 /**
752 * Returns whether any output on the specified pipe is of the specified type
753 */
754 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
755 {
756 struct drm_device *dev = crtc->dev;
757 struct drm_mode_config *mode_config = &dev->mode_config;
758 struct intel_encoder *encoder;
759
760 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
761 if (encoder->base.crtc == crtc && encoder->type == type)
762 return true;
763
764 return false;
765 }
766
767 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
768 /**
769 * Returns whether the given set of divisors are valid for a given refclk with
770 * the given connectors.
771 */
772
773 static bool intel_PLL_is_valid(struct drm_device *dev,
774 const intel_limit_t *limit,
775 const intel_clock_t *clock)
776 {
777 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
778 INTELPllInvalid ("p1 out of range\n");
779 if (clock->p < limit->p.min || limit->p.max < clock->p)
780 INTELPllInvalid ("p out of range\n");
781 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
782 INTELPllInvalid ("m2 out of range\n");
783 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
784 INTELPllInvalid ("m1 out of range\n");
785 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
786 INTELPllInvalid ("m1 <= m2\n");
787 if (clock->m < limit->m.min || limit->m.max < clock->m)
788 INTELPllInvalid ("m out of range\n");
789 if (clock->n < limit->n.min || limit->n.max < clock->n)
790 INTELPllInvalid ("n out of range\n");
791 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
792 INTELPllInvalid ("vco out of range\n");
793 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
794 * connector, etc., rather than just a single range.
795 */
796 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
797 INTELPllInvalid ("dot out of range\n");
798
799 return true;
800 }
801
802 static bool
803 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
804 int target, int refclk, intel_clock_t *best_clock)
805
806 {
807 struct drm_device *dev = crtc->dev;
808 struct drm_i915_private *dev_priv = dev->dev_private;
809 intel_clock_t clock;
810 int err = target;
811
812 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
813 (I915_READ(LVDS)) != 0) {
814 /*
815 * For LVDS, if the panel is on, just rely on its current
816 * settings for dual-channel. We haven't figured out how to
817 * reliably set up different single/dual channel state, if we
818 * even can.
819 */
820 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
821 LVDS_CLKB_POWER_UP)
822 clock.p2 = limit->p2.p2_fast;
823 else
824 clock.p2 = limit->p2.p2_slow;
825 } else {
826 if (target < limit->p2.dot_limit)
827 clock.p2 = limit->p2.p2_slow;
828 else
829 clock.p2 = limit->p2.p2_fast;
830 }
831
832 memset (best_clock, 0, sizeof (*best_clock));
833
834 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
835 clock.m1++) {
836 for (clock.m2 = limit->m2.min;
837 clock.m2 <= limit->m2.max; clock.m2++) {
838 /* m1 is always 0 in Pineview */
839 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
840 break;
841 for (clock.n = limit->n.min;
842 clock.n <= limit->n.max; clock.n++) {
843 for (clock.p1 = limit->p1.min;
844 clock.p1 <= limit->p1.max; clock.p1++) {
845 int this_err;
846
847 intel_clock(dev, refclk, &clock);
848 if (!intel_PLL_is_valid(dev, limit,
849 &clock))
850 continue;
851
852 this_err = abs(clock.dot - target);
853 if (this_err < err) {
854 *best_clock = clock;
855 err = this_err;
856 }
857 }
858 }
859 }
860 }
861
862 return (err != target);
863 }
864
865 static bool
866 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
867 int target, int refclk, intel_clock_t *best_clock)
868 {
869 struct drm_device *dev = crtc->dev;
870 struct drm_i915_private *dev_priv = dev->dev_private;
871 intel_clock_t clock;
872 int max_n;
873 bool found;
874 /* approximately equals target * 0.00585 */
875 int err_most = (target >> 8) + (target >> 9);
876 found = false;
877
878 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
879 int lvds_reg;
880
881 if (HAS_PCH_SPLIT(dev))
882 lvds_reg = PCH_LVDS;
883 else
884 lvds_reg = LVDS;
885 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
886 LVDS_CLKB_POWER_UP)
887 clock.p2 = limit->p2.p2_fast;
888 else
889 clock.p2 = limit->p2.p2_slow;
890 } else {
891 if (target < limit->p2.dot_limit)
892 clock.p2 = limit->p2.p2_slow;
893 else
894 clock.p2 = limit->p2.p2_fast;
895 }
896
897 memset(best_clock, 0, sizeof(*best_clock));
898 max_n = limit->n.max;
899 /* based on hardware requirement, prefer smaller n to precision */
900 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
901 /* based on hardware requirement, prefere larger m1,m2 */
902 for (clock.m1 = limit->m1.max;
903 clock.m1 >= limit->m1.min; clock.m1--) {
904 for (clock.m2 = limit->m2.max;
905 clock.m2 >= limit->m2.min; clock.m2--) {
906 for (clock.p1 = limit->p1.max;
907 clock.p1 >= limit->p1.min; clock.p1--) {
908 int this_err;
909
910 intel_clock(dev, refclk, &clock);
911 if (!intel_PLL_is_valid(dev, limit,
912 &clock))
913 continue;
914
915 this_err = abs(clock.dot - target);
916 if (this_err < err_most) {
917 *best_clock = clock;
918 err_most = this_err;
919 max_n = clock.n;
920 found = true;
921 }
922 }
923 }
924 }
925 }
926 return found;
927 }
928
929 static bool
930 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
931 int target, int refclk, intel_clock_t *best_clock)
932 {
933 struct drm_device *dev = crtc->dev;
934 intel_clock_t clock;
935
936 if (target < 200000) {
937 clock.n = 1;
938 clock.p1 = 2;
939 clock.p2 = 10;
940 clock.m1 = 12;
941 clock.m2 = 9;
942 } else {
943 clock.n = 2;
944 clock.p1 = 1;
945 clock.p2 = 10;
946 clock.m1 = 14;
947 clock.m2 = 8;
948 }
949 intel_clock(dev, refclk, &clock);
950 memcpy(best_clock, &clock, sizeof(intel_clock_t));
951 return true;
952 }
953
954 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
955 static bool
956 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
957 int target, int refclk, intel_clock_t *best_clock)
958 {
959 intel_clock_t clock;
960 if (target < 200000) {
961 clock.p1 = 2;
962 clock.p2 = 10;
963 clock.n = 2;
964 clock.m1 = 23;
965 clock.m2 = 8;
966 } else {
967 clock.p1 = 1;
968 clock.p2 = 10;
969 clock.n = 1;
970 clock.m1 = 14;
971 clock.m2 = 2;
972 }
973 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
974 clock.p = (clock.p1 * clock.p2);
975 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
976 clock.vco = 0;
977 memcpy(best_clock, &clock, sizeof(intel_clock_t));
978 return true;
979 }
980
981 /**
982 * intel_wait_for_vblank - wait for vblank on a given pipe
983 * @dev: drm device
984 * @pipe: pipe to wait for
985 *
986 * Wait for vblank to occur on a given pipe. Needed for various bits of
987 * mode setting code.
988 */
989 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
990 {
991 struct drm_i915_private *dev_priv = dev->dev_private;
992 int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT);
993
994 /* Clear existing vblank status. Note this will clear any other
995 * sticky status fields as well.
996 *
997 * This races with i915_driver_irq_handler() with the result
998 * that either function could miss a vblank event. Here it is not
999 * fatal, as we will either wait upon the next vblank interrupt or
1000 * timeout. Generally speaking intel_wait_for_vblank() is only
1001 * called during modeset at which time the GPU should be idle and
1002 * should *not* be performing page flips and thus not waiting on
1003 * vblanks...
1004 * Currently, the result of us stealing a vblank from the irq
1005 * handler is that a single frame will be skipped during swapbuffers.
1006 */
1007 I915_WRITE(pipestat_reg,
1008 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
1009
1010 /* Wait for vblank interrupt bit to set */
1011 if (wait_for(I915_READ(pipestat_reg) &
1012 PIPE_VBLANK_INTERRUPT_STATUS,
1013 50))
1014 DRM_DEBUG_KMS("vblank wait timed out\n");
1015 }
1016
1017 /*
1018 * intel_wait_for_pipe_off - wait for pipe to turn off
1019 * @dev: drm device
1020 * @pipe: pipe to wait for
1021 *
1022 * After disabling a pipe, we can't wait for vblank in the usual way,
1023 * spinning on the vblank interrupt status bit, since we won't actually
1024 * see an interrupt when the pipe is disabled.
1025 *
1026 * On Gen4 and above:
1027 * wait for the pipe register state bit to turn off
1028 *
1029 * Otherwise:
1030 * wait for the display line value to settle (it usually
1031 * ends up stopping at the start of the next frame).
1032 *
1033 */
1034 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1035 {
1036 struct drm_i915_private *dev_priv = dev->dev_private;
1037
1038 if (INTEL_INFO(dev)->gen >= 4) {
1039 int reg = PIPECONF(pipe);
1040
1041 /* Wait for the Pipe State to go off */
1042 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1043 100))
1044 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1045 } else {
1046 u32 last_line;
1047 int reg = PIPEDSL(pipe);
1048 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1049
1050 /* Wait for the display line to settle */
1051 do {
1052 last_line = I915_READ(reg) & DSL_LINEMASK;
1053 mdelay(5);
1054 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
1055 time_after(timeout, jiffies));
1056 if (time_after(jiffies, timeout))
1057 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1058 }
1059 }
1060
1061 static const char *state_string(bool enabled)
1062 {
1063 return enabled ? "on" : "off";
1064 }
1065
1066 /* Only for pre-ILK configs */
1067 static void assert_pll(struct drm_i915_private *dev_priv,
1068 enum pipe pipe, bool state)
1069 {
1070 int reg;
1071 u32 val;
1072 bool cur_state;
1073
1074 reg = DPLL(pipe);
1075 val = I915_READ(reg);
1076 cur_state = !!(val & DPLL_VCO_ENABLE);
1077 WARN(cur_state != state,
1078 "PLL state assertion failure (expected %s, current %s)\n",
1079 state_string(state), state_string(cur_state));
1080 }
1081 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1082 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1083
1084 /* For ILK+ */
1085 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1086 enum pipe pipe, bool state)
1087 {
1088 int reg;
1089 u32 val;
1090 bool cur_state;
1091
1092 reg = PCH_DPLL(pipe);
1093 val = I915_READ(reg);
1094 cur_state = !!(val & DPLL_VCO_ENABLE);
1095 WARN(cur_state != state,
1096 "PCH PLL state assertion failure (expected %s, current %s)\n",
1097 state_string(state), state_string(cur_state));
1098 }
1099 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
1100 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
1101
1102 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1103 enum pipe pipe, bool state)
1104 {
1105 int reg;
1106 u32 val;
1107 bool cur_state;
1108
1109 reg = FDI_TX_CTL(pipe);
1110 val = I915_READ(reg);
1111 cur_state = !!(val & FDI_TX_ENABLE);
1112 WARN(cur_state != state,
1113 "FDI TX state assertion failure (expected %s, current %s)\n",
1114 state_string(state), state_string(cur_state));
1115 }
1116 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1117 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1118
1119 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1120 enum pipe pipe, bool state)
1121 {
1122 int reg;
1123 u32 val;
1124 bool cur_state;
1125
1126 reg = FDI_RX_CTL(pipe);
1127 val = I915_READ(reg);
1128 cur_state = !!(val & FDI_RX_ENABLE);
1129 WARN(cur_state != state,
1130 "FDI RX state assertion failure (expected %s, current %s)\n",
1131 state_string(state), state_string(cur_state));
1132 }
1133 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1134 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1135
1136 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1137 enum pipe pipe)
1138 {
1139 int reg;
1140 u32 val;
1141
1142 /* ILK FDI PLL is always enabled */
1143 if (dev_priv->info->gen == 5)
1144 return;
1145
1146 reg = FDI_TX_CTL(pipe);
1147 val = I915_READ(reg);
1148 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1149 }
1150
1151 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1152 enum pipe pipe)
1153 {
1154 int reg;
1155 u32 val;
1156
1157 reg = FDI_RX_CTL(pipe);
1158 val = I915_READ(reg);
1159 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1160 }
1161
1162 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1163 enum pipe pipe)
1164 {
1165 int pp_reg, lvds_reg;
1166 u32 val;
1167 enum pipe panel_pipe = PIPE_A;
1168 bool locked = locked;
1169
1170 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1171 pp_reg = PCH_PP_CONTROL;
1172 lvds_reg = PCH_LVDS;
1173 } else {
1174 pp_reg = PP_CONTROL;
1175 lvds_reg = LVDS;
1176 }
1177
1178 val = I915_READ(pp_reg);
1179 if (!(val & PANEL_POWER_ON) ||
1180 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1181 locked = false;
1182
1183 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1184 panel_pipe = PIPE_B;
1185
1186 WARN(panel_pipe == pipe && locked,
1187 "panel assertion failure, pipe %c regs locked\n",
1188 pipe ? 'B' : 'A');
1189 }
1190
1191 static void assert_pipe(struct drm_i915_private *dev_priv,
1192 enum pipe pipe, bool state)
1193 {
1194 int reg;
1195 u32 val;
1196 bool cur_state;
1197
1198 reg = PIPECONF(pipe);
1199 val = I915_READ(reg);
1200 cur_state = !!(val & PIPECONF_ENABLE);
1201 WARN(cur_state != state,
1202 "pipe %c assertion failure (expected %s, current %s)\n",
1203 pipe ? 'B' : 'A', state_string(state), state_string(cur_state));
1204 }
1205 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1206 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1207
1208 static void assert_plane_enabled(struct drm_i915_private *dev_priv,
1209 enum plane plane)
1210 {
1211 int reg;
1212 u32 val;
1213
1214 reg = DSPCNTR(plane);
1215 val = I915_READ(reg);
1216 WARN(!(val & DISPLAY_PLANE_ENABLE),
1217 "plane %c assertion failure, should be active but is disabled\n",
1218 plane ? 'B' : 'A');
1219 }
1220
1221 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1222 enum pipe pipe)
1223 {
1224 int reg, i;
1225 u32 val;
1226 int cur_pipe;
1227
1228 /* Need to check both planes against the pipe */
1229 for (i = 0; i < 2; i++) {
1230 reg = DSPCNTR(i);
1231 val = I915_READ(reg);
1232 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1233 DISPPLANE_SEL_PIPE_SHIFT;
1234 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1235 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1236 i, pipe ? 'B' : 'A');
1237 }
1238 }
1239
1240 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1241 {
1242 u32 val;
1243 bool enabled;
1244
1245 val = I915_READ(PCH_DREF_CONTROL);
1246 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1247 DREF_SUPERSPREAD_SOURCE_MASK));
1248 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1249 }
1250
1251 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1252 enum pipe pipe)
1253 {
1254 int reg;
1255 u32 val;
1256 bool enabled;
1257
1258 reg = TRANSCONF(pipe);
1259 val = I915_READ(reg);
1260 enabled = !!(val & TRANS_ENABLE);
1261 WARN(enabled, "transcoder assertion failed, should be off on pipe %c but is still active\n", pipe ? 'B' :'A');
1262 }
1263
1264 /**
1265 * intel_enable_pll - enable a PLL
1266 * @dev_priv: i915 private structure
1267 * @pipe: pipe PLL to enable
1268 *
1269 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1270 * make sure the PLL reg is writable first though, since the panel write
1271 * protect mechanism may be enabled.
1272 *
1273 * Note! This is for pre-ILK only.
1274 */
1275 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1276 {
1277 int reg;
1278 u32 val;
1279
1280 /* No really, not for ILK+ */
1281 BUG_ON(dev_priv->info->gen >= 5);
1282
1283 /* PLL is protected by panel, make sure we can write it */
1284 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1285 assert_panel_unlocked(dev_priv, pipe);
1286
1287 reg = DPLL(pipe);
1288 val = I915_READ(reg);
1289 val |= DPLL_VCO_ENABLE;
1290
1291 /* We do this three times for luck */
1292 I915_WRITE(reg, val);
1293 POSTING_READ(reg);
1294 udelay(150); /* wait for warmup */
1295 I915_WRITE(reg, val);
1296 POSTING_READ(reg);
1297 udelay(150); /* wait for warmup */
1298 I915_WRITE(reg, val);
1299 POSTING_READ(reg);
1300 udelay(150); /* wait for warmup */
1301 }
1302
1303 /**
1304 * intel_disable_pll - disable a PLL
1305 * @dev_priv: i915 private structure
1306 * @pipe: pipe PLL to disable
1307 *
1308 * Disable the PLL for @pipe, making sure the pipe is off first.
1309 *
1310 * Note! This is for pre-ILK only.
1311 */
1312 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1313 {
1314 int reg;
1315 u32 val;
1316
1317 /* Don't disable pipe A or pipe A PLLs if needed */
1318 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1319 return;
1320
1321 /* Make sure the pipe isn't still relying on us */
1322 assert_pipe_disabled(dev_priv, pipe);
1323
1324 reg = DPLL(pipe);
1325 val = I915_READ(reg);
1326 val &= ~DPLL_VCO_ENABLE;
1327 I915_WRITE(reg, val);
1328 POSTING_READ(reg);
1329 }
1330
1331 /**
1332 * intel_enable_pch_pll - enable PCH PLL
1333 * @dev_priv: i915 private structure
1334 * @pipe: pipe PLL to enable
1335 *
1336 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1337 * drives the transcoder clock.
1338 */
1339 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1340 enum pipe pipe)
1341 {
1342 int reg;
1343 u32 val;
1344
1345 /* PCH only available on ILK+ */
1346 BUG_ON(dev_priv->info->gen < 5);
1347
1348 /* PCH refclock must be enabled first */
1349 assert_pch_refclk_enabled(dev_priv);
1350
1351 reg = PCH_DPLL(pipe);
1352 val = I915_READ(reg);
1353 val |= DPLL_VCO_ENABLE;
1354 I915_WRITE(reg, val);
1355 POSTING_READ(reg);
1356 udelay(200);
1357 }
1358
1359 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1360 enum pipe pipe)
1361 {
1362 int reg;
1363 u32 val;
1364
1365 /* PCH only available on ILK+ */
1366 BUG_ON(dev_priv->info->gen < 5);
1367
1368 /* Make sure transcoder isn't still depending on us */
1369 assert_transcoder_disabled(dev_priv, pipe);
1370
1371 reg = PCH_DPLL(pipe);
1372 val = I915_READ(reg);
1373 val &= ~DPLL_VCO_ENABLE;
1374 I915_WRITE(reg, val);
1375 POSTING_READ(reg);
1376 udelay(200);
1377 }
1378
1379 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1380 enum pipe pipe)
1381 {
1382 int reg;
1383 u32 val;
1384
1385 /* PCH only available on ILK+ */
1386 BUG_ON(dev_priv->info->gen < 5);
1387
1388 /* Make sure PCH DPLL is enabled */
1389 assert_pch_pll_enabled(dev_priv, pipe);
1390
1391 /* FDI must be feeding us bits for PCH ports */
1392 assert_fdi_tx_enabled(dev_priv, pipe);
1393 assert_fdi_rx_enabled(dev_priv, pipe);
1394
1395 reg = TRANSCONF(pipe);
1396 val = I915_READ(reg);
1397 /*
1398 * make the BPC in transcoder be consistent with
1399 * that in pipeconf reg.
1400 */
1401 val &= ~PIPE_BPC_MASK;
1402 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1403 I915_WRITE(reg, val | TRANS_ENABLE);
1404 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1405 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1406 }
1407
1408 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1409 enum pipe pipe)
1410 {
1411 int reg;
1412 u32 val;
1413
1414 /* FDI relies on the transcoder */
1415 assert_fdi_tx_disabled(dev_priv, pipe);
1416 assert_fdi_rx_disabled(dev_priv, pipe);
1417
1418 reg = TRANSCONF(pipe);
1419 val = I915_READ(reg);
1420 val &= ~TRANS_ENABLE;
1421 I915_WRITE(reg, val);
1422 /* wait for PCH transcoder off, transcoder state */
1423 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1424 DRM_ERROR("failed to disable transcoder\n");
1425 }
1426
1427 /**
1428 * intel_enable_pipe - enable a pipe, assertiing requirements
1429 * @dev_priv: i915 private structure
1430 * @pipe: pipe to enable
1431 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1432 *
1433 * Enable @pipe, making sure that various hardware specific requirements
1434 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1435 *
1436 * @pipe should be %PIPE_A or %PIPE_B.
1437 *
1438 * Will wait until the pipe is actually running (i.e. first vblank) before
1439 * returning.
1440 */
1441 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1442 bool pch_port)
1443 {
1444 int reg;
1445 u32 val;
1446
1447 /*
1448 * A pipe without a PLL won't actually be able to drive bits from
1449 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1450 * need the check.
1451 */
1452 if (!HAS_PCH_SPLIT(dev_priv->dev))
1453 assert_pll_enabled(dev_priv, pipe);
1454 else {
1455 if (pch_port) {
1456 /* if driving the PCH, we need FDI enabled */
1457 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1458 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1459 }
1460 /* FIXME: assert CPU port conditions for SNB+ */
1461 }
1462
1463 reg = PIPECONF(pipe);
1464 val = I915_READ(reg);
1465 val |= PIPECONF_ENABLE;
1466 I915_WRITE(reg, val);
1467 POSTING_READ(reg);
1468 intel_wait_for_vblank(dev_priv->dev, pipe);
1469 }
1470
1471 /**
1472 * intel_disable_pipe - disable a pipe, assertiing requirements
1473 * @dev_priv: i915 private structure
1474 * @pipe: pipe to disable
1475 *
1476 * Disable @pipe, making sure that various hardware specific requirements
1477 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1478 *
1479 * @pipe should be %PIPE_A or %PIPE_B.
1480 *
1481 * Will wait until the pipe has shut down before returning.
1482 */
1483 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1484 enum pipe pipe)
1485 {
1486 int reg;
1487 u32 val;
1488
1489 /*
1490 * Make sure planes won't keep trying to pump pixels to us,
1491 * or we might hang the display.
1492 */
1493 assert_planes_disabled(dev_priv, pipe);
1494
1495 /* Don't disable pipe A or pipe A PLLs if needed */
1496 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1497 return;
1498
1499 reg = PIPECONF(pipe);
1500 val = I915_READ(reg);
1501 val &= ~PIPECONF_ENABLE;
1502 I915_WRITE(reg, val);
1503 POSTING_READ(reg);
1504 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1505 }
1506
1507 /**
1508 * intel_enable_plane - enable a display plane on a given pipe
1509 * @dev_priv: i915 private structure
1510 * @plane: plane to enable
1511 * @pipe: pipe being fed
1512 *
1513 * Enable @plane on @pipe, making sure that @pipe is running first.
1514 */
1515 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1516 enum plane plane, enum pipe pipe)
1517 {
1518 int reg;
1519 u32 val;
1520
1521 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1522 assert_pipe_enabled(dev_priv, pipe);
1523
1524 reg = DSPCNTR(plane);
1525 val = I915_READ(reg);
1526 val |= DISPLAY_PLANE_ENABLE;
1527 I915_WRITE(reg, val);
1528 POSTING_READ(reg);
1529 intel_wait_for_vblank(dev_priv->dev, pipe);
1530 }
1531
1532 /*
1533 * Plane regs are double buffered, going from enabled->disabled needs a
1534 * trigger in order to latch. The display address reg provides this.
1535 */
1536 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1537 enum plane plane)
1538 {
1539 u32 reg = DSPADDR(plane);
1540 I915_WRITE(reg, I915_READ(reg));
1541 }
1542
1543 /**
1544 * intel_disable_plane - disable a display plane
1545 * @dev_priv: i915 private structure
1546 * @plane: plane to disable
1547 * @pipe: pipe consuming the data
1548 *
1549 * Disable @plane; should be an independent operation.
1550 */
1551 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1552 enum plane plane, enum pipe pipe)
1553 {
1554 int reg;
1555 u32 val;
1556
1557 reg = DSPCNTR(plane);
1558 val = I915_READ(reg);
1559 val &= ~DISPLAY_PLANE_ENABLE;
1560 I915_WRITE(reg, val);
1561 POSTING_READ(reg);
1562 intel_flush_display_plane(dev_priv, plane);
1563 intel_wait_for_vblank(dev_priv->dev, pipe);
1564 }
1565
1566 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1567 {
1568 struct drm_device *dev = crtc->dev;
1569 struct drm_i915_private *dev_priv = dev->dev_private;
1570 struct drm_framebuffer *fb = crtc->fb;
1571 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1572 struct drm_i915_gem_object *obj = intel_fb->obj;
1573 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1574 int plane, i;
1575 u32 fbc_ctl, fbc_ctl2;
1576
1577 if (fb->pitch == dev_priv->cfb_pitch &&
1578 obj->fence_reg == dev_priv->cfb_fence &&
1579 intel_crtc->plane == dev_priv->cfb_plane &&
1580 I915_READ(FBC_CONTROL) & FBC_CTL_EN)
1581 return;
1582
1583 i8xx_disable_fbc(dev);
1584
1585 dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1586
1587 if (fb->pitch < dev_priv->cfb_pitch)
1588 dev_priv->cfb_pitch = fb->pitch;
1589
1590 /* FBC_CTL wants 64B units */
1591 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1592 dev_priv->cfb_fence = obj->fence_reg;
1593 dev_priv->cfb_plane = intel_crtc->plane;
1594 plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1595
1596 /* Clear old tags */
1597 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1598 I915_WRITE(FBC_TAG + (i * 4), 0);
1599
1600 /* Set it up... */
1601 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1602 if (obj->tiling_mode != I915_TILING_NONE)
1603 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1604 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1605 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1606
1607 /* enable it... */
1608 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1609 if (IS_I945GM(dev))
1610 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1611 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1612 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1613 if (obj->tiling_mode != I915_TILING_NONE)
1614 fbc_ctl |= dev_priv->cfb_fence;
1615 I915_WRITE(FBC_CONTROL, fbc_ctl);
1616
1617 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1618 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1619 }
1620
1621 void i8xx_disable_fbc(struct drm_device *dev)
1622 {
1623 struct drm_i915_private *dev_priv = dev->dev_private;
1624 u32 fbc_ctl;
1625
1626 /* Disable compression */
1627 fbc_ctl = I915_READ(FBC_CONTROL);
1628 if ((fbc_ctl & FBC_CTL_EN) == 0)
1629 return;
1630
1631 fbc_ctl &= ~FBC_CTL_EN;
1632 I915_WRITE(FBC_CONTROL, fbc_ctl);
1633
1634 /* Wait for compressing bit to clear */
1635 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1636 DRM_DEBUG_KMS("FBC idle timed out\n");
1637 return;
1638 }
1639
1640 DRM_DEBUG_KMS("disabled FBC\n");
1641 }
1642
1643 static bool i8xx_fbc_enabled(struct drm_device *dev)
1644 {
1645 struct drm_i915_private *dev_priv = dev->dev_private;
1646
1647 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1648 }
1649
1650 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1651 {
1652 struct drm_device *dev = crtc->dev;
1653 struct drm_i915_private *dev_priv = dev->dev_private;
1654 struct drm_framebuffer *fb = crtc->fb;
1655 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1656 struct drm_i915_gem_object *obj = intel_fb->obj;
1657 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1658 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1659 unsigned long stall_watermark = 200;
1660 u32 dpfc_ctl;
1661
1662 dpfc_ctl = I915_READ(DPFC_CONTROL);
1663 if (dpfc_ctl & DPFC_CTL_EN) {
1664 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1665 dev_priv->cfb_fence == obj->fence_reg &&
1666 dev_priv->cfb_plane == intel_crtc->plane &&
1667 dev_priv->cfb_y == crtc->y)
1668 return;
1669
1670 I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1671 POSTING_READ(DPFC_CONTROL);
1672 intel_wait_for_vblank(dev, intel_crtc->pipe);
1673 }
1674
1675 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1676 dev_priv->cfb_fence = obj->fence_reg;
1677 dev_priv->cfb_plane = intel_crtc->plane;
1678 dev_priv->cfb_y = crtc->y;
1679
1680 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1681 if (obj->tiling_mode != I915_TILING_NONE) {
1682 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1683 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1684 } else {
1685 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1686 }
1687
1688 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1689 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1690 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1691 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1692
1693 /* enable it... */
1694 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1695
1696 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1697 }
1698
1699 void g4x_disable_fbc(struct drm_device *dev)
1700 {
1701 struct drm_i915_private *dev_priv = dev->dev_private;
1702 u32 dpfc_ctl;
1703
1704 /* Disable compression */
1705 dpfc_ctl = I915_READ(DPFC_CONTROL);
1706 if (dpfc_ctl & DPFC_CTL_EN) {
1707 dpfc_ctl &= ~DPFC_CTL_EN;
1708 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1709
1710 DRM_DEBUG_KMS("disabled FBC\n");
1711 }
1712 }
1713
1714 static bool g4x_fbc_enabled(struct drm_device *dev)
1715 {
1716 struct drm_i915_private *dev_priv = dev->dev_private;
1717
1718 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1719 }
1720
1721 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1722 {
1723 struct drm_device *dev = crtc->dev;
1724 struct drm_i915_private *dev_priv = dev->dev_private;
1725 struct drm_framebuffer *fb = crtc->fb;
1726 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1727 struct drm_i915_gem_object *obj = intel_fb->obj;
1728 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1729 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1730 unsigned long stall_watermark = 200;
1731 u32 dpfc_ctl;
1732
1733 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1734 if (dpfc_ctl & DPFC_CTL_EN) {
1735 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1736 dev_priv->cfb_fence == obj->fence_reg &&
1737 dev_priv->cfb_plane == intel_crtc->plane &&
1738 dev_priv->cfb_offset == obj->gtt_offset &&
1739 dev_priv->cfb_y == crtc->y)
1740 return;
1741
1742 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1743 POSTING_READ(ILK_DPFC_CONTROL);
1744 intel_wait_for_vblank(dev, intel_crtc->pipe);
1745 }
1746
1747 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1748 dev_priv->cfb_fence = obj->fence_reg;
1749 dev_priv->cfb_plane = intel_crtc->plane;
1750 dev_priv->cfb_offset = obj->gtt_offset;
1751 dev_priv->cfb_y = crtc->y;
1752
1753 dpfc_ctl &= DPFC_RESERVED;
1754 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1755 if (obj->tiling_mode != I915_TILING_NONE) {
1756 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1757 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1758 } else {
1759 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1760 }
1761
1762 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1763 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1764 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1765 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1766 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1767 /* enable it... */
1768 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1769
1770 if (IS_GEN6(dev)) {
1771 I915_WRITE(SNB_DPFC_CTL_SA,
1772 SNB_CPU_FENCE_ENABLE | dev_priv->cfb_fence);
1773 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1774 }
1775
1776 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1777 }
1778
1779 void ironlake_disable_fbc(struct drm_device *dev)
1780 {
1781 struct drm_i915_private *dev_priv = dev->dev_private;
1782 u32 dpfc_ctl;
1783
1784 /* Disable compression */
1785 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1786 if (dpfc_ctl & DPFC_CTL_EN) {
1787 dpfc_ctl &= ~DPFC_CTL_EN;
1788 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1789
1790 DRM_DEBUG_KMS("disabled FBC\n");
1791 }
1792 }
1793
1794 static bool ironlake_fbc_enabled(struct drm_device *dev)
1795 {
1796 struct drm_i915_private *dev_priv = dev->dev_private;
1797
1798 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1799 }
1800
1801 bool intel_fbc_enabled(struct drm_device *dev)
1802 {
1803 struct drm_i915_private *dev_priv = dev->dev_private;
1804
1805 if (!dev_priv->display.fbc_enabled)
1806 return false;
1807
1808 return dev_priv->display.fbc_enabled(dev);
1809 }
1810
1811 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1812 {
1813 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1814
1815 if (!dev_priv->display.enable_fbc)
1816 return;
1817
1818 dev_priv->display.enable_fbc(crtc, interval);
1819 }
1820
1821 void intel_disable_fbc(struct drm_device *dev)
1822 {
1823 struct drm_i915_private *dev_priv = dev->dev_private;
1824
1825 if (!dev_priv->display.disable_fbc)
1826 return;
1827
1828 dev_priv->display.disable_fbc(dev);
1829 }
1830
1831 /**
1832 * intel_update_fbc - enable/disable FBC as needed
1833 * @dev: the drm_device
1834 *
1835 * Set up the framebuffer compression hardware at mode set time. We
1836 * enable it if possible:
1837 * - plane A only (on pre-965)
1838 * - no pixel mulitply/line duplication
1839 * - no alpha buffer discard
1840 * - no dual wide
1841 * - framebuffer <= 2048 in width, 1536 in height
1842 *
1843 * We can't assume that any compression will take place (worst case),
1844 * so the compressed buffer has to be the same size as the uncompressed
1845 * one. It also must reside (along with the line length buffer) in
1846 * stolen memory.
1847 *
1848 * We need to enable/disable FBC on a global basis.
1849 */
1850 static void intel_update_fbc(struct drm_device *dev)
1851 {
1852 struct drm_i915_private *dev_priv = dev->dev_private;
1853 struct drm_crtc *crtc = NULL, *tmp_crtc;
1854 struct intel_crtc *intel_crtc;
1855 struct drm_framebuffer *fb;
1856 struct intel_framebuffer *intel_fb;
1857 struct drm_i915_gem_object *obj;
1858
1859 DRM_DEBUG_KMS("\n");
1860
1861 if (!i915_powersave)
1862 return;
1863
1864 if (!I915_HAS_FBC(dev))
1865 return;
1866
1867 /*
1868 * If FBC is already on, we just have to verify that we can
1869 * keep it that way...
1870 * Need to disable if:
1871 * - more than one pipe is active
1872 * - changing FBC params (stride, fence, mode)
1873 * - new fb is too large to fit in compressed buffer
1874 * - going to an unsupported config (interlace, pixel multiply, etc.)
1875 */
1876 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1877 if (tmp_crtc->enabled) {
1878 if (crtc) {
1879 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1880 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1881 goto out_disable;
1882 }
1883 crtc = tmp_crtc;
1884 }
1885 }
1886
1887 if (!crtc || crtc->fb == NULL) {
1888 DRM_DEBUG_KMS("no output, disabling\n");
1889 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1890 goto out_disable;
1891 }
1892
1893 intel_crtc = to_intel_crtc(crtc);
1894 fb = crtc->fb;
1895 intel_fb = to_intel_framebuffer(fb);
1896 obj = intel_fb->obj;
1897
1898 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1899 DRM_DEBUG_KMS("framebuffer too large, disabling "
1900 "compression\n");
1901 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1902 goto out_disable;
1903 }
1904 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1905 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1906 DRM_DEBUG_KMS("mode incompatible with compression, "
1907 "disabling\n");
1908 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1909 goto out_disable;
1910 }
1911 if ((crtc->mode.hdisplay > 2048) ||
1912 (crtc->mode.vdisplay > 1536)) {
1913 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1914 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1915 goto out_disable;
1916 }
1917 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1918 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1919 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1920 goto out_disable;
1921 }
1922 if (obj->tiling_mode != I915_TILING_X) {
1923 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1924 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1925 goto out_disable;
1926 }
1927
1928 /* If the kernel debugger is active, always disable compression */
1929 if (in_dbg_master())
1930 goto out_disable;
1931
1932 intel_enable_fbc(crtc, 500);
1933 return;
1934
1935 out_disable:
1936 /* Multiple disables should be harmless */
1937 if (intel_fbc_enabled(dev)) {
1938 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1939 intel_disable_fbc(dev);
1940 }
1941 }
1942
1943 int
1944 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1945 struct drm_i915_gem_object *obj,
1946 struct intel_ring_buffer *pipelined)
1947 {
1948 u32 alignment;
1949 int ret;
1950
1951 switch (obj->tiling_mode) {
1952 case I915_TILING_NONE:
1953 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1954 alignment = 128 * 1024;
1955 else if (INTEL_INFO(dev)->gen >= 4)
1956 alignment = 4 * 1024;
1957 else
1958 alignment = 64 * 1024;
1959 break;
1960 case I915_TILING_X:
1961 /* pin() will align the object as required by fence */
1962 alignment = 0;
1963 break;
1964 case I915_TILING_Y:
1965 /* FIXME: Is this true? */
1966 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1967 return -EINVAL;
1968 default:
1969 BUG();
1970 }
1971
1972 ret = i915_gem_object_pin(obj, alignment, true);
1973 if (ret)
1974 return ret;
1975
1976 ret = i915_gem_object_set_to_display_plane(obj, pipelined);
1977 if (ret)
1978 goto err_unpin;
1979
1980 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1981 * fence, whereas 965+ only requires a fence if using
1982 * framebuffer compression. For simplicity, we always install
1983 * a fence as the cost is not that onerous.
1984 */
1985 if (obj->tiling_mode != I915_TILING_NONE) {
1986 ret = i915_gem_object_get_fence(obj, pipelined, false);
1987 if (ret)
1988 goto err_unpin;
1989 }
1990
1991 return 0;
1992
1993 err_unpin:
1994 i915_gem_object_unpin(obj);
1995 return ret;
1996 }
1997
1998 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1999 static int
2000 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2001 int x, int y, enum mode_set_atomic state)
2002 {
2003 struct drm_device *dev = crtc->dev;
2004 struct drm_i915_private *dev_priv = dev->dev_private;
2005 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2006 struct intel_framebuffer *intel_fb;
2007 struct drm_i915_gem_object *obj;
2008 int plane = intel_crtc->plane;
2009 unsigned long Start, Offset;
2010 u32 dspcntr;
2011 u32 reg;
2012
2013 switch (plane) {
2014 case 0:
2015 case 1:
2016 break;
2017 default:
2018 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2019 return -EINVAL;
2020 }
2021
2022 intel_fb = to_intel_framebuffer(fb);
2023 obj = intel_fb->obj;
2024
2025 reg = DSPCNTR(plane);
2026 dspcntr = I915_READ(reg);
2027 /* Mask out pixel format bits in case we change it */
2028 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2029 switch (fb->bits_per_pixel) {
2030 case 8:
2031 dspcntr |= DISPPLANE_8BPP;
2032 break;
2033 case 16:
2034 if (fb->depth == 15)
2035 dspcntr |= DISPPLANE_15_16BPP;
2036 else
2037 dspcntr |= DISPPLANE_16BPP;
2038 break;
2039 case 24:
2040 case 32:
2041 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2042 break;
2043 default:
2044 DRM_ERROR("Unknown color depth\n");
2045 return -EINVAL;
2046 }
2047 if (INTEL_INFO(dev)->gen >= 4) {
2048 if (obj->tiling_mode != I915_TILING_NONE)
2049 dspcntr |= DISPPLANE_TILED;
2050 else
2051 dspcntr &= ~DISPPLANE_TILED;
2052 }
2053
2054 if (HAS_PCH_SPLIT(dev))
2055 /* must disable */
2056 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2057
2058 I915_WRITE(reg, dspcntr);
2059
2060 Start = obj->gtt_offset;
2061 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2062
2063 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2064 Start, Offset, x, y, fb->pitch);
2065 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
2066 if (INTEL_INFO(dev)->gen >= 4) {
2067 I915_WRITE(DSPSURF(plane), Start);
2068 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2069 I915_WRITE(DSPADDR(plane), Offset);
2070 } else
2071 I915_WRITE(DSPADDR(plane), Start + Offset);
2072 POSTING_READ(reg);
2073
2074 intel_update_fbc(dev);
2075 intel_increase_pllclock(crtc);
2076
2077 return 0;
2078 }
2079
2080 static int
2081 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2082 struct drm_framebuffer *old_fb)
2083 {
2084 struct drm_device *dev = crtc->dev;
2085 struct drm_i915_master_private *master_priv;
2086 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2087 int ret;
2088
2089 /* no fb bound */
2090 if (!crtc->fb) {
2091 DRM_DEBUG_KMS("No FB bound\n");
2092 return 0;
2093 }
2094
2095 switch (intel_crtc->plane) {
2096 case 0:
2097 case 1:
2098 break;
2099 default:
2100 return -EINVAL;
2101 }
2102
2103 mutex_lock(&dev->struct_mutex);
2104 ret = intel_pin_and_fence_fb_obj(dev,
2105 to_intel_framebuffer(crtc->fb)->obj,
2106 NULL);
2107 if (ret != 0) {
2108 mutex_unlock(&dev->struct_mutex);
2109 return ret;
2110 }
2111
2112 if (old_fb) {
2113 struct drm_i915_private *dev_priv = dev->dev_private;
2114 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2115
2116 wait_event(dev_priv->pending_flip_queue,
2117 atomic_read(&obj->pending_flip) == 0);
2118
2119 /* Big Hammer, we also need to ensure that any pending
2120 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2121 * current scanout is retired before unpinning the old
2122 * framebuffer.
2123 */
2124 ret = i915_gem_object_flush_gpu(obj, false);
2125 if (ret) {
2126 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2127 mutex_unlock(&dev->struct_mutex);
2128 return ret;
2129 }
2130 }
2131
2132 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2133 LEAVE_ATOMIC_MODE_SET);
2134 if (ret) {
2135 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2136 mutex_unlock(&dev->struct_mutex);
2137 return ret;
2138 }
2139
2140 if (old_fb) {
2141 intel_wait_for_vblank(dev, intel_crtc->pipe);
2142 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
2143 }
2144
2145 mutex_unlock(&dev->struct_mutex);
2146
2147 if (!dev->primary->master)
2148 return 0;
2149
2150 master_priv = dev->primary->master->driver_priv;
2151 if (!master_priv->sarea_priv)
2152 return 0;
2153
2154 if (intel_crtc->pipe) {
2155 master_priv->sarea_priv->pipeB_x = x;
2156 master_priv->sarea_priv->pipeB_y = y;
2157 } else {
2158 master_priv->sarea_priv->pipeA_x = x;
2159 master_priv->sarea_priv->pipeA_y = y;
2160 }
2161
2162 return 0;
2163 }
2164
2165 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2166 {
2167 struct drm_device *dev = crtc->dev;
2168 struct drm_i915_private *dev_priv = dev->dev_private;
2169 u32 dpa_ctl;
2170
2171 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2172 dpa_ctl = I915_READ(DP_A);
2173 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2174
2175 if (clock < 200000) {
2176 u32 temp;
2177 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2178 /* workaround for 160Mhz:
2179 1) program 0x4600c bits 15:0 = 0x8124
2180 2) program 0x46010 bit 0 = 1
2181 3) program 0x46034 bit 24 = 1
2182 4) program 0x64000 bit 14 = 1
2183 */
2184 temp = I915_READ(0x4600c);
2185 temp &= 0xffff0000;
2186 I915_WRITE(0x4600c, temp | 0x8124);
2187
2188 temp = I915_READ(0x46010);
2189 I915_WRITE(0x46010, temp | 1);
2190
2191 temp = I915_READ(0x46034);
2192 I915_WRITE(0x46034, temp | (1 << 24));
2193 } else {
2194 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2195 }
2196 I915_WRITE(DP_A, dpa_ctl);
2197
2198 POSTING_READ(DP_A);
2199 udelay(500);
2200 }
2201
2202 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2203 {
2204 struct drm_device *dev = crtc->dev;
2205 struct drm_i915_private *dev_priv = dev->dev_private;
2206 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2207 int pipe = intel_crtc->pipe;
2208 u32 reg, temp;
2209
2210 /* enable normal train */
2211 reg = FDI_TX_CTL(pipe);
2212 temp = I915_READ(reg);
2213 temp &= ~FDI_LINK_TRAIN_NONE;
2214 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2215 I915_WRITE(reg, temp);
2216
2217 reg = FDI_RX_CTL(pipe);
2218 temp = I915_READ(reg);
2219 if (HAS_PCH_CPT(dev)) {
2220 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2221 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2222 } else {
2223 temp &= ~FDI_LINK_TRAIN_NONE;
2224 temp |= FDI_LINK_TRAIN_NONE;
2225 }
2226 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2227
2228 /* wait one idle pattern time */
2229 POSTING_READ(reg);
2230 udelay(1000);
2231 }
2232
2233 /* The FDI link training functions for ILK/Ibexpeak. */
2234 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2235 {
2236 struct drm_device *dev = crtc->dev;
2237 struct drm_i915_private *dev_priv = dev->dev_private;
2238 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2239 int pipe = intel_crtc->pipe;
2240 int plane = intel_crtc->plane;
2241 u32 reg, temp, tries;
2242
2243 /* FDI needs bits from pipe & plane first */
2244 assert_pipe_enabled(dev_priv, pipe);
2245 assert_plane_enabled(dev_priv, plane);
2246
2247 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2248 for train result */
2249 reg = FDI_RX_IMR(pipe);
2250 temp = I915_READ(reg);
2251 temp &= ~FDI_RX_SYMBOL_LOCK;
2252 temp &= ~FDI_RX_BIT_LOCK;
2253 I915_WRITE(reg, temp);
2254 I915_READ(reg);
2255 udelay(150);
2256
2257 /* enable CPU FDI TX and PCH FDI RX */
2258 reg = FDI_TX_CTL(pipe);
2259 temp = I915_READ(reg);
2260 temp &= ~(7 << 19);
2261 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2262 temp &= ~FDI_LINK_TRAIN_NONE;
2263 temp |= FDI_LINK_TRAIN_PATTERN_1;
2264 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2265
2266 reg = FDI_RX_CTL(pipe);
2267 temp = I915_READ(reg);
2268 temp &= ~FDI_LINK_TRAIN_NONE;
2269 temp |= FDI_LINK_TRAIN_PATTERN_1;
2270 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2271
2272 POSTING_READ(reg);
2273 udelay(150);
2274
2275 /* Ironlake workaround, enable clock pointer after FDI enable*/
2276 if (HAS_PCH_IBX(dev)) {
2277 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2278 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2279 FDI_RX_PHASE_SYNC_POINTER_EN);
2280 }
2281
2282 reg = FDI_RX_IIR(pipe);
2283 for (tries = 0; tries < 5; tries++) {
2284 temp = I915_READ(reg);
2285 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2286
2287 if ((temp & FDI_RX_BIT_LOCK)) {
2288 DRM_DEBUG_KMS("FDI train 1 done.\n");
2289 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2290 break;
2291 }
2292 }
2293 if (tries == 5)
2294 DRM_ERROR("FDI train 1 fail!\n");
2295
2296 /* Train 2 */
2297 reg = FDI_TX_CTL(pipe);
2298 temp = I915_READ(reg);
2299 temp &= ~FDI_LINK_TRAIN_NONE;
2300 temp |= FDI_LINK_TRAIN_PATTERN_2;
2301 I915_WRITE(reg, temp);
2302
2303 reg = FDI_RX_CTL(pipe);
2304 temp = I915_READ(reg);
2305 temp &= ~FDI_LINK_TRAIN_NONE;
2306 temp |= FDI_LINK_TRAIN_PATTERN_2;
2307 I915_WRITE(reg, temp);
2308
2309 POSTING_READ(reg);
2310 udelay(150);
2311
2312 reg = FDI_RX_IIR(pipe);
2313 for (tries = 0; tries < 5; tries++) {
2314 temp = I915_READ(reg);
2315 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2316
2317 if (temp & FDI_RX_SYMBOL_LOCK) {
2318 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2319 DRM_DEBUG_KMS("FDI train 2 done.\n");
2320 break;
2321 }
2322 }
2323 if (tries == 5)
2324 DRM_ERROR("FDI train 2 fail!\n");
2325
2326 DRM_DEBUG_KMS("FDI train done\n");
2327
2328 }
2329
2330 static const int snb_b_fdi_train_param [] = {
2331 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2332 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2333 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2334 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2335 };
2336
2337 /* The FDI link training functions for SNB/Cougarpoint. */
2338 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2339 {
2340 struct drm_device *dev = crtc->dev;
2341 struct drm_i915_private *dev_priv = dev->dev_private;
2342 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2343 int pipe = intel_crtc->pipe;
2344 u32 reg, temp, i;
2345
2346 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2347 for train result */
2348 reg = FDI_RX_IMR(pipe);
2349 temp = I915_READ(reg);
2350 temp &= ~FDI_RX_SYMBOL_LOCK;
2351 temp &= ~FDI_RX_BIT_LOCK;
2352 I915_WRITE(reg, temp);
2353
2354 POSTING_READ(reg);
2355 udelay(150);
2356
2357 /* enable CPU FDI TX and PCH FDI RX */
2358 reg = FDI_TX_CTL(pipe);
2359 temp = I915_READ(reg);
2360 temp &= ~(7 << 19);
2361 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2362 temp &= ~FDI_LINK_TRAIN_NONE;
2363 temp |= FDI_LINK_TRAIN_PATTERN_1;
2364 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2365 /* SNB-B */
2366 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2367 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2368
2369 reg = FDI_RX_CTL(pipe);
2370 temp = I915_READ(reg);
2371 if (HAS_PCH_CPT(dev)) {
2372 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2373 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2374 } else {
2375 temp &= ~FDI_LINK_TRAIN_NONE;
2376 temp |= FDI_LINK_TRAIN_PATTERN_1;
2377 }
2378 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2379
2380 POSTING_READ(reg);
2381 udelay(150);
2382
2383 for (i = 0; i < 4; i++ ) {
2384 reg = FDI_TX_CTL(pipe);
2385 temp = I915_READ(reg);
2386 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2387 temp |= snb_b_fdi_train_param[i];
2388 I915_WRITE(reg, temp);
2389
2390 POSTING_READ(reg);
2391 udelay(500);
2392
2393 reg = FDI_RX_IIR(pipe);
2394 temp = I915_READ(reg);
2395 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2396
2397 if (temp & FDI_RX_BIT_LOCK) {
2398 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2399 DRM_DEBUG_KMS("FDI train 1 done.\n");
2400 break;
2401 }
2402 }
2403 if (i == 4)
2404 DRM_ERROR("FDI train 1 fail!\n");
2405
2406 /* Train 2 */
2407 reg = FDI_TX_CTL(pipe);
2408 temp = I915_READ(reg);
2409 temp &= ~FDI_LINK_TRAIN_NONE;
2410 temp |= FDI_LINK_TRAIN_PATTERN_2;
2411 if (IS_GEN6(dev)) {
2412 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2413 /* SNB-B */
2414 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2415 }
2416 I915_WRITE(reg, temp);
2417
2418 reg = FDI_RX_CTL(pipe);
2419 temp = I915_READ(reg);
2420 if (HAS_PCH_CPT(dev)) {
2421 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2422 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2423 } else {
2424 temp &= ~FDI_LINK_TRAIN_NONE;
2425 temp |= FDI_LINK_TRAIN_PATTERN_2;
2426 }
2427 I915_WRITE(reg, temp);
2428
2429 POSTING_READ(reg);
2430 udelay(150);
2431
2432 for (i = 0; i < 4; i++ ) {
2433 reg = FDI_TX_CTL(pipe);
2434 temp = I915_READ(reg);
2435 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2436 temp |= snb_b_fdi_train_param[i];
2437 I915_WRITE(reg, temp);
2438
2439 POSTING_READ(reg);
2440 udelay(500);
2441
2442 reg = FDI_RX_IIR(pipe);
2443 temp = I915_READ(reg);
2444 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2445
2446 if (temp & FDI_RX_SYMBOL_LOCK) {
2447 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2448 DRM_DEBUG_KMS("FDI train 2 done.\n");
2449 break;
2450 }
2451 }
2452 if (i == 4)
2453 DRM_ERROR("FDI train 2 fail!\n");
2454
2455 DRM_DEBUG_KMS("FDI train done.\n");
2456 }
2457
2458 static void ironlake_fdi_enable(struct drm_crtc *crtc)
2459 {
2460 struct drm_device *dev = crtc->dev;
2461 struct drm_i915_private *dev_priv = dev->dev_private;
2462 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2463 int pipe = intel_crtc->pipe;
2464 u32 reg, temp;
2465
2466 /* Write the TU size bits so error detection works */
2467 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2468 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2469
2470 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2471 reg = FDI_RX_CTL(pipe);
2472 temp = I915_READ(reg);
2473 temp &= ~((0x7 << 19) | (0x7 << 16));
2474 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2475 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2476 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2477
2478 POSTING_READ(reg);
2479 udelay(200);
2480
2481 /* Switch from Rawclk to PCDclk */
2482 temp = I915_READ(reg);
2483 I915_WRITE(reg, temp | FDI_PCDCLK);
2484
2485 POSTING_READ(reg);
2486 udelay(200);
2487
2488 /* Enable CPU FDI TX PLL, always on for Ironlake */
2489 reg = FDI_TX_CTL(pipe);
2490 temp = I915_READ(reg);
2491 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2492 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2493
2494 POSTING_READ(reg);
2495 udelay(100);
2496 }
2497 }
2498
2499 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2500 {
2501 struct drm_device *dev = crtc->dev;
2502 struct drm_i915_private *dev_priv = dev->dev_private;
2503 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2504 int pipe = intel_crtc->pipe;
2505 u32 reg, temp;
2506
2507 /* disable CPU FDI tx and PCH FDI rx */
2508 reg = FDI_TX_CTL(pipe);
2509 temp = I915_READ(reg);
2510 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2511 POSTING_READ(reg);
2512
2513 reg = FDI_RX_CTL(pipe);
2514 temp = I915_READ(reg);
2515 temp &= ~(0x7 << 16);
2516 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2517 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2518
2519 POSTING_READ(reg);
2520 udelay(100);
2521
2522 /* Ironlake workaround, disable clock pointer after downing FDI */
2523 if (HAS_PCH_IBX(dev)) {
2524 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2525 I915_WRITE(FDI_RX_CHICKEN(pipe),
2526 I915_READ(FDI_RX_CHICKEN(pipe) &
2527 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2528 }
2529
2530 /* still set train pattern 1 */
2531 reg = FDI_TX_CTL(pipe);
2532 temp = I915_READ(reg);
2533 temp &= ~FDI_LINK_TRAIN_NONE;
2534 temp |= FDI_LINK_TRAIN_PATTERN_1;
2535 I915_WRITE(reg, temp);
2536
2537 reg = FDI_RX_CTL(pipe);
2538 temp = I915_READ(reg);
2539 if (HAS_PCH_CPT(dev)) {
2540 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2541 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2542 } else {
2543 temp &= ~FDI_LINK_TRAIN_NONE;
2544 temp |= FDI_LINK_TRAIN_PATTERN_1;
2545 }
2546 /* BPC in FDI rx is consistent with that in PIPECONF */
2547 temp &= ~(0x07 << 16);
2548 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2549 I915_WRITE(reg, temp);
2550
2551 POSTING_READ(reg);
2552 udelay(100);
2553 }
2554
2555 /*
2556 * When we disable a pipe, we need to clear any pending scanline wait events
2557 * to avoid hanging the ring, which we assume we are waiting on.
2558 */
2559 static void intel_clear_scanline_wait(struct drm_device *dev)
2560 {
2561 struct drm_i915_private *dev_priv = dev->dev_private;
2562 struct intel_ring_buffer *ring;
2563 u32 tmp;
2564
2565 if (IS_GEN2(dev))
2566 /* Can't break the hang on i8xx */
2567 return;
2568
2569 ring = LP_RING(dev_priv);
2570 tmp = I915_READ_CTL(ring);
2571 if (tmp & RING_WAIT)
2572 I915_WRITE_CTL(ring, tmp);
2573 }
2574
2575 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2576 {
2577 struct drm_i915_gem_object *obj;
2578 struct drm_i915_private *dev_priv;
2579
2580 if (crtc->fb == NULL)
2581 return;
2582
2583 obj = to_intel_framebuffer(crtc->fb)->obj;
2584 dev_priv = crtc->dev->dev_private;
2585 wait_event(dev_priv->pending_flip_queue,
2586 atomic_read(&obj->pending_flip) == 0);
2587 }
2588
2589 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2590 {
2591 struct drm_device *dev = crtc->dev;
2592 struct drm_mode_config *mode_config = &dev->mode_config;
2593 struct intel_encoder *encoder;
2594
2595 /*
2596 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2597 * must be driven by its own crtc; no sharing is possible.
2598 */
2599 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2600 if (encoder->base.crtc != crtc)
2601 continue;
2602
2603 switch (encoder->type) {
2604 case INTEL_OUTPUT_EDP:
2605 if (!intel_encoder_is_pch_edp(&encoder->base))
2606 return false;
2607 continue;
2608 }
2609 }
2610
2611 return true;
2612 }
2613
2614 /*
2615 * Enable PCH resources required for PCH ports:
2616 * - PCH PLLs
2617 * - FDI training & RX/TX
2618 * - update transcoder timings
2619 * - DP transcoding bits
2620 * - transcoder
2621 */
2622 static void ironlake_pch_enable(struct drm_crtc *crtc)
2623 {
2624 struct drm_device *dev = crtc->dev;
2625 struct drm_i915_private *dev_priv = dev->dev_private;
2626 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2627 int pipe = intel_crtc->pipe;
2628 u32 reg, temp;
2629
2630 /* For PCH output, training FDI link */
2631 if (IS_GEN6(dev))
2632 gen6_fdi_link_train(crtc);
2633 else
2634 ironlake_fdi_link_train(crtc);
2635
2636 intel_enable_pch_pll(dev_priv, pipe);
2637
2638 if (HAS_PCH_CPT(dev)) {
2639 /* Be sure PCH DPLL SEL is set */
2640 temp = I915_READ(PCH_DPLL_SEL);
2641 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
2642 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2643 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
2644 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2645 I915_WRITE(PCH_DPLL_SEL, temp);
2646 }
2647
2648 /* set transcoder timing, panel must allow it */
2649 assert_panel_unlocked(dev_priv, pipe);
2650 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2651 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2652 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
2653
2654 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2655 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2656 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
2657
2658 intel_fdi_normal_train(crtc);
2659
2660 /* For PCH DP, enable TRANS_DP_CTL */
2661 if (HAS_PCH_CPT(dev) &&
2662 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2663 reg = TRANS_DP_CTL(pipe);
2664 temp = I915_READ(reg);
2665 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2666 TRANS_DP_SYNC_MASK |
2667 TRANS_DP_BPC_MASK);
2668 temp |= (TRANS_DP_OUTPUT_ENABLE |
2669 TRANS_DP_ENH_FRAMING);
2670 temp |= TRANS_DP_8BPC;
2671
2672 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2673 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2674 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2675 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2676
2677 switch (intel_trans_dp_port_sel(crtc)) {
2678 case PCH_DP_B:
2679 temp |= TRANS_DP_PORT_SEL_B;
2680 break;
2681 case PCH_DP_C:
2682 temp |= TRANS_DP_PORT_SEL_C;
2683 break;
2684 case PCH_DP_D:
2685 temp |= TRANS_DP_PORT_SEL_D;
2686 break;
2687 default:
2688 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2689 temp |= TRANS_DP_PORT_SEL_B;
2690 break;
2691 }
2692
2693 I915_WRITE(reg, temp);
2694 }
2695
2696 intel_enable_transcoder(dev_priv, pipe);
2697 }
2698
2699 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2700 {
2701 struct drm_device *dev = crtc->dev;
2702 struct drm_i915_private *dev_priv = dev->dev_private;
2703 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2704 int pipe = intel_crtc->pipe;
2705 int plane = intel_crtc->plane;
2706 u32 temp;
2707 bool is_pch_port;
2708
2709 if (intel_crtc->active)
2710 return;
2711
2712 intel_crtc->active = true;
2713 intel_update_watermarks(dev);
2714
2715 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2716 temp = I915_READ(PCH_LVDS);
2717 if ((temp & LVDS_PORT_EN) == 0)
2718 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2719 }
2720
2721 is_pch_port = intel_crtc_driving_pch(crtc);
2722
2723 if (is_pch_port)
2724 ironlake_fdi_enable(crtc);
2725 else
2726 ironlake_fdi_disable(crtc);
2727
2728 /* Enable panel fitting for LVDS */
2729 if (dev_priv->pch_pf_size &&
2730 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2731 /* Force use of hard-coded filter coefficients
2732 * as some pre-programmed values are broken,
2733 * e.g. x201.
2734 */
2735 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1,
2736 PF_ENABLE | PF_FILTER_MED_3x3);
2737 I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS,
2738 dev_priv->pch_pf_pos);
2739 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ,
2740 dev_priv->pch_pf_size);
2741 }
2742
2743 intel_enable_pipe(dev_priv, pipe, is_pch_port);
2744 intel_enable_plane(dev_priv, plane, pipe);
2745
2746 if (is_pch_port)
2747 ironlake_pch_enable(crtc);
2748
2749 intel_crtc_load_lut(crtc);
2750 intel_update_fbc(dev);
2751 intel_crtc_update_cursor(crtc, true);
2752 }
2753
2754 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2755 {
2756 struct drm_device *dev = crtc->dev;
2757 struct drm_i915_private *dev_priv = dev->dev_private;
2758 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2759 int pipe = intel_crtc->pipe;
2760 int plane = intel_crtc->plane;
2761 u32 reg, temp;
2762
2763 if (!intel_crtc->active)
2764 return;
2765
2766 intel_crtc_wait_for_pending_flips(crtc);
2767 drm_vblank_off(dev, pipe);
2768 intel_crtc_update_cursor(crtc, false);
2769
2770 intel_disable_plane(dev_priv, plane, pipe);
2771
2772 if (dev_priv->cfb_plane == plane &&
2773 dev_priv->display.disable_fbc)
2774 dev_priv->display.disable_fbc(dev);
2775
2776 intel_disable_pipe(dev_priv, pipe);
2777
2778 /* Disable PF */
2779 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0);
2780 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0);
2781
2782 ironlake_fdi_disable(crtc);
2783
2784 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2785 temp = I915_READ(PCH_LVDS);
2786 if (temp & LVDS_PORT_EN) {
2787 I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2788 POSTING_READ(PCH_LVDS);
2789 udelay(100);
2790 }
2791 }
2792
2793 intel_disable_transcoder(dev_priv, pipe);
2794
2795 if (HAS_PCH_CPT(dev)) {
2796 /* disable TRANS_DP_CTL */
2797 reg = TRANS_DP_CTL(pipe);
2798 temp = I915_READ(reg);
2799 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2800 I915_WRITE(reg, temp);
2801
2802 /* disable DPLL_SEL */
2803 temp = I915_READ(PCH_DPLL_SEL);
2804 if (pipe == 0)
2805 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2806 else
2807 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2808 I915_WRITE(PCH_DPLL_SEL, temp);
2809 }
2810
2811 /* disable PCH DPLL */
2812 intel_disable_pch_pll(dev_priv, pipe);
2813
2814 /* Switch from PCDclk to Rawclk */
2815 reg = FDI_RX_CTL(pipe);
2816 temp = I915_READ(reg);
2817 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2818
2819 /* Disable CPU FDI TX PLL */
2820 reg = FDI_TX_CTL(pipe);
2821 temp = I915_READ(reg);
2822 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2823
2824 POSTING_READ(reg);
2825 udelay(100);
2826
2827 reg = FDI_RX_CTL(pipe);
2828 temp = I915_READ(reg);
2829 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2830
2831 /* Wait for the clocks to turn off. */
2832 POSTING_READ(reg);
2833 udelay(100);
2834
2835 intel_crtc->active = false;
2836 intel_update_watermarks(dev);
2837 intel_update_fbc(dev);
2838 intel_clear_scanline_wait(dev);
2839 }
2840
2841 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2842 {
2843 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2844 int pipe = intel_crtc->pipe;
2845 int plane = intel_crtc->plane;
2846
2847 /* XXX: When our outputs are all unaware of DPMS modes other than off
2848 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2849 */
2850 switch (mode) {
2851 case DRM_MODE_DPMS_ON:
2852 case DRM_MODE_DPMS_STANDBY:
2853 case DRM_MODE_DPMS_SUSPEND:
2854 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2855 ironlake_crtc_enable(crtc);
2856 break;
2857
2858 case DRM_MODE_DPMS_OFF:
2859 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2860 ironlake_crtc_disable(crtc);
2861 break;
2862 }
2863 }
2864
2865 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2866 {
2867 if (!enable && intel_crtc->overlay) {
2868 struct drm_device *dev = intel_crtc->base.dev;
2869
2870 mutex_lock(&dev->struct_mutex);
2871 (void) intel_overlay_switch_off(intel_crtc->overlay, false);
2872 mutex_unlock(&dev->struct_mutex);
2873 }
2874
2875 /* Let userspace switch the overlay on again. In most cases userspace
2876 * has to recompute where to put it anyway.
2877 */
2878 }
2879
2880 static void i9xx_crtc_enable(struct drm_crtc *crtc)
2881 {
2882 struct drm_device *dev = crtc->dev;
2883 struct drm_i915_private *dev_priv = dev->dev_private;
2884 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2885 int pipe = intel_crtc->pipe;
2886 int plane = intel_crtc->plane;
2887
2888 if (intel_crtc->active)
2889 return;
2890
2891 intel_crtc->active = true;
2892 intel_update_watermarks(dev);
2893
2894 intel_enable_pll(dev_priv, pipe);
2895 intel_enable_pipe(dev_priv, pipe, false);
2896 intel_enable_plane(dev_priv, plane, pipe);
2897
2898 intel_crtc_load_lut(crtc);
2899 intel_update_fbc(dev);
2900
2901 /* Give the overlay scaler a chance to enable if it's on this pipe */
2902 intel_crtc_dpms_overlay(intel_crtc, true);
2903 intel_crtc_update_cursor(crtc, true);
2904 }
2905
2906 static void i9xx_crtc_disable(struct drm_crtc *crtc)
2907 {
2908 struct drm_device *dev = crtc->dev;
2909 struct drm_i915_private *dev_priv = dev->dev_private;
2910 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2911 int pipe = intel_crtc->pipe;
2912 int plane = intel_crtc->plane;
2913
2914 if (!intel_crtc->active)
2915 return;
2916
2917 /* Give the overlay scaler a chance to disable if it's on this pipe */
2918 intel_crtc_wait_for_pending_flips(crtc);
2919 drm_vblank_off(dev, pipe);
2920 intel_crtc_dpms_overlay(intel_crtc, false);
2921 intel_crtc_update_cursor(crtc, false);
2922
2923 if (dev_priv->cfb_plane == plane &&
2924 dev_priv->display.disable_fbc)
2925 dev_priv->display.disable_fbc(dev);
2926
2927 intel_disable_plane(dev_priv, plane, pipe);
2928 intel_disable_pipe(dev_priv, pipe);
2929 intel_disable_pll(dev_priv, pipe);
2930
2931 intel_crtc->active = false;
2932 intel_update_fbc(dev);
2933 intel_update_watermarks(dev);
2934 intel_clear_scanline_wait(dev);
2935 }
2936
2937 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2938 {
2939 /* XXX: When our outputs are all unaware of DPMS modes other than off
2940 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2941 */
2942 switch (mode) {
2943 case DRM_MODE_DPMS_ON:
2944 case DRM_MODE_DPMS_STANDBY:
2945 case DRM_MODE_DPMS_SUSPEND:
2946 i9xx_crtc_enable(crtc);
2947 break;
2948 case DRM_MODE_DPMS_OFF:
2949 i9xx_crtc_disable(crtc);
2950 break;
2951 }
2952 }
2953
2954 /**
2955 * Sets the power management mode of the pipe and plane.
2956 */
2957 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2958 {
2959 struct drm_device *dev = crtc->dev;
2960 struct drm_i915_private *dev_priv = dev->dev_private;
2961 struct drm_i915_master_private *master_priv;
2962 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2963 int pipe = intel_crtc->pipe;
2964 bool enabled;
2965
2966 if (intel_crtc->dpms_mode == mode)
2967 return;
2968
2969 intel_crtc->dpms_mode = mode;
2970
2971 dev_priv->display.dpms(crtc, mode);
2972
2973 if (!dev->primary->master)
2974 return;
2975
2976 master_priv = dev->primary->master->driver_priv;
2977 if (!master_priv->sarea_priv)
2978 return;
2979
2980 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2981
2982 switch (pipe) {
2983 case 0:
2984 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2985 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2986 break;
2987 case 1:
2988 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2989 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2990 break;
2991 default:
2992 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2993 break;
2994 }
2995 }
2996
2997 static void intel_crtc_disable(struct drm_crtc *crtc)
2998 {
2999 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3000 struct drm_device *dev = crtc->dev;
3001
3002 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3003
3004 if (crtc->fb) {
3005 mutex_lock(&dev->struct_mutex);
3006 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
3007 mutex_unlock(&dev->struct_mutex);
3008 }
3009 }
3010
3011 /* Prepare for a mode set.
3012 *
3013 * Note we could be a lot smarter here. We need to figure out which outputs
3014 * will be enabled, which disabled (in short, how the config will changes)
3015 * and perform the minimum necessary steps to accomplish that, e.g. updating
3016 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3017 * panel fitting is in the proper state, etc.
3018 */
3019 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3020 {
3021 i9xx_crtc_disable(crtc);
3022 }
3023
3024 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3025 {
3026 i9xx_crtc_enable(crtc);
3027 }
3028
3029 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3030 {
3031 ironlake_crtc_disable(crtc);
3032 }
3033
3034 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3035 {
3036 ironlake_crtc_enable(crtc);
3037 }
3038
3039 void intel_encoder_prepare (struct drm_encoder *encoder)
3040 {
3041 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3042 /* lvds has its own version of prepare see intel_lvds_prepare */
3043 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3044 }
3045
3046 void intel_encoder_commit (struct drm_encoder *encoder)
3047 {
3048 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3049 /* lvds has its own version of commit see intel_lvds_commit */
3050 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3051 }
3052
3053 void intel_encoder_destroy(struct drm_encoder *encoder)
3054 {
3055 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3056
3057 drm_encoder_cleanup(encoder);
3058 kfree(intel_encoder);
3059 }
3060
3061 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3062 struct drm_display_mode *mode,
3063 struct drm_display_mode *adjusted_mode)
3064 {
3065 struct drm_device *dev = crtc->dev;
3066
3067 if (HAS_PCH_SPLIT(dev)) {
3068 /* FDI link clock is fixed at 2.7G */
3069 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3070 return false;
3071 }
3072
3073 /* XXX some encoders set the crtcinfo, others don't.
3074 * Obviously we need some form of conflict resolution here...
3075 */
3076 if (adjusted_mode->crtc_htotal == 0)
3077 drm_mode_set_crtcinfo(adjusted_mode, 0);
3078
3079 return true;
3080 }
3081
3082 static int i945_get_display_clock_speed(struct drm_device *dev)
3083 {
3084 return 400000;
3085 }
3086
3087 static int i915_get_display_clock_speed(struct drm_device *dev)
3088 {
3089 return 333000;
3090 }
3091
3092 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3093 {
3094 return 200000;
3095 }
3096
3097 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3098 {
3099 u16 gcfgc = 0;
3100
3101 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3102
3103 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3104 return 133000;
3105 else {
3106 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3107 case GC_DISPLAY_CLOCK_333_MHZ:
3108 return 333000;
3109 default:
3110 case GC_DISPLAY_CLOCK_190_200_MHZ:
3111 return 190000;
3112 }
3113 }
3114 }
3115
3116 static int i865_get_display_clock_speed(struct drm_device *dev)
3117 {
3118 return 266000;
3119 }
3120
3121 static int i855_get_display_clock_speed(struct drm_device *dev)
3122 {
3123 u16 hpllcc = 0;
3124 /* Assume that the hardware is in the high speed state. This
3125 * should be the default.
3126 */
3127 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3128 case GC_CLOCK_133_200:
3129 case GC_CLOCK_100_200:
3130 return 200000;
3131 case GC_CLOCK_166_250:
3132 return 250000;
3133 case GC_CLOCK_100_133:
3134 return 133000;
3135 }
3136
3137 /* Shouldn't happen */
3138 return 0;
3139 }
3140
3141 static int i830_get_display_clock_speed(struct drm_device *dev)
3142 {
3143 return 133000;
3144 }
3145
3146 struct fdi_m_n {
3147 u32 tu;
3148 u32 gmch_m;
3149 u32 gmch_n;
3150 u32 link_m;
3151 u32 link_n;
3152 };
3153
3154 static void
3155 fdi_reduce_ratio(u32 *num, u32 *den)
3156 {
3157 while (*num > 0xffffff || *den > 0xffffff) {
3158 *num >>= 1;
3159 *den >>= 1;
3160 }
3161 }
3162
3163 static void
3164 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3165 int link_clock, struct fdi_m_n *m_n)
3166 {
3167 m_n->tu = 64; /* default size */
3168
3169 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3170 m_n->gmch_m = bits_per_pixel * pixel_clock;
3171 m_n->gmch_n = link_clock * nlanes * 8;
3172 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3173
3174 m_n->link_m = pixel_clock;
3175 m_n->link_n = link_clock;
3176 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3177 }
3178
3179
3180 struct intel_watermark_params {
3181 unsigned long fifo_size;
3182 unsigned long max_wm;
3183 unsigned long default_wm;
3184 unsigned long guard_size;
3185 unsigned long cacheline_size;
3186 };
3187
3188 /* Pineview has different values for various configs */
3189 static struct intel_watermark_params pineview_display_wm = {
3190 PINEVIEW_DISPLAY_FIFO,
3191 PINEVIEW_MAX_WM,
3192 PINEVIEW_DFT_WM,
3193 PINEVIEW_GUARD_WM,
3194 PINEVIEW_FIFO_LINE_SIZE
3195 };
3196 static struct intel_watermark_params pineview_display_hplloff_wm = {
3197 PINEVIEW_DISPLAY_FIFO,
3198 PINEVIEW_MAX_WM,
3199 PINEVIEW_DFT_HPLLOFF_WM,
3200 PINEVIEW_GUARD_WM,
3201 PINEVIEW_FIFO_LINE_SIZE
3202 };
3203 static struct intel_watermark_params pineview_cursor_wm = {
3204 PINEVIEW_CURSOR_FIFO,
3205 PINEVIEW_CURSOR_MAX_WM,
3206 PINEVIEW_CURSOR_DFT_WM,
3207 PINEVIEW_CURSOR_GUARD_WM,
3208 PINEVIEW_FIFO_LINE_SIZE,
3209 };
3210 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
3211 PINEVIEW_CURSOR_FIFO,
3212 PINEVIEW_CURSOR_MAX_WM,
3213 PINEVIEW_CURSOR_DFT_WM,
3214 PINEVIEW_CURSOR_GUARD_WM,
3215 PINEVIEW_FIFO_LINE_SIZE
3216 };
3217 static struct intel_watermark_params g4x_wm_info = {
3218 G4X_FIFO_SIZE,
3219 G4X_MAX_WM,
3220 G4X_MAX_WM,
3221 2,
3222 G4X_FIFO_LINE_SIZE,
3223 };
3224 static struct intel_watermark_params g4x_cursor_wm_info = {
3225 I965_CURSOR_FIFO,
3226 I965_CURSOR_MAX_WM,
3227 I965_CURSOR_DFT_WM,
3228 2,
3229 G4X_FIFO_LINE_SIZE,
3230 };
3231 static struct intel_watermark_params i965_cursor_wm_info = {
3232 I965_CURSOR_FIFO,
3233 I965_CURSOR_MAX_WM,
3234 I965_CURSOR_DFT_WM,
3235 2,
3236 I915_FIFO_LINE_SIZE,
3237 };
3238 static struct intel_watermark_params i945_wm_info = {
3239 I945_FIFO_SIZE,
3240 I915_MAX_WM,
3241 1,
3242 2,
3243 I915_FIFO_LINE_SIZE
3244 };
3245 static struct intel_watermark_params i915_wm_info = {
3246 I915_FIFO_SIZE,
3247 I915_MAX_WM,
3248 1,
3249 2,
3250 I915_FIFO_LINE_SIZE
3251 };
3252 static struct intel_watermark_params i855_wm_info = {
3253 I855GM_FIFO_SIZE,
3254 I915_MAX_WM,
3255 1,
3256 2,
3257 I830_FIFO_LINE_SIZE
3258 };
3259 static struct intel_watermark_params i830_wm_info = {
3260 I830_FIFO_SIZE,
3261 I915_MAX_WM,
3262 1,
3263 2,
3264 I830_FIFO_LINE_SIZE
3265 };
3266
3267 static struct intel_watermark_params ironlake_display_wm_info = {
3268 ILK_DISPLAY_FIFO,
3269 ILK_DISPLAY_MAXWM,
3270 ILK_DISPLAY_DFTWM,
3271 2,
3272 ILK_FIFO_LINE_SIZE
3273 };
3274
3275 static struct intel_watermark_params ironlake_cursor_wm_info = {
3276 ILK_CURSOR_FIFO,
3277 ILK_CURSOR_MAXWM,
3278 ILK_CURSOR_DFTWM,
3279 2,
3280 ILK_FIFO_LINE_SIZE
3281 };
3282
3283 static struct intel_watermark_params ironlake_display_srwm_info = {
3284 ILK_DISPLAY_SR_FIFO,
3285 ILK_DISPLAY_MAX_SRWM,
3286 ILK_DISPLAY_DFT_SRWM,
3287 2,
3288 ILK_FIFO_LINE_SIZE
3289 };
3290
3291 static struct intel_watermark_params ironlake_cursor_srwm_info = {
3292 ILK_CURSOR_SR_FIFO,
3293 ILK_CURSOR_MAX_SRWM,
3294 ILK_CURSOR_DFT_SRWM,
3295 2,
3296 ILK_FIFO_LINE_SIZE
3297 };
3298
3299 static struct intel_watermark_params sandybridge_display_wm_info = {
3300 SNB_DISPLAY_FIFO,
3301 SNB_DISPLAY_MAXWM,
3302 SNB_DISPLAY_DFTWM,
3303 2,
3304 SNB_FIFO_LINE_SIZE
3305 };
3306
3307 static struct intel_watermark_params sandybridge_cursor_wm_info = {
3308 SNB_CURSOR_FIFO,
3309 SNB_CURSOR_MAXWM,
3310 SNB_CURSOR_DFTWM,
3311 2,
3312 SNB_FIFO_LINE_SIZE
3313 };
3314
3315 static struct intel_watermark_params sandybridge_display_srwm_info = {
3316 SNB_DISPLAY_SR_FIFO,
3317 SNB_DISPLAY_MAX_SRWM,
3318 SNB_DISPLAY_DFT_SRWM,
3319 2,
3320 SNB_FIFO_LINE_SIZE
3321 };
3322
3323 static struct intel_watermark_params sandybridge_cursor_srwm_info = {
3324 SNB_CURSOR_SR_FIFO,
3325 SNB_CURSOR_MAX_SRWM,
3326 SNB_CURSOR_DFT_SRWM,
3327 2,
3328 SNB_FIFO_LINE_SIZE
3329 };
3330
3331
3332 /**
3333 * intel_calculate_wm - calculate watermark level
3334 * @clock_in_khz: pixel clock
3335 * @wm: chip FIFO params
3336 * @pixel_size: display pixel size
3337 * @latency_ns: memory latency for the platform
3338 *
3339 * Calculate the watermark level (the level at which the display plane will
3340 * start fetching from memory again). Each chip has a different display
3341 * FIFO size and allocation, so the caller needs to figure that out and pass
3342 * in the correct intel_watermark_params structure.
3343 *
3344 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3345 * on the pixel size. When it reaches the watermark level, it'll start
3346 * fetching FIFO line sized based chunks from memory until the FIFO fills
3347 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3348 * will occur, and a display engine hang could result.
3349 */
3350 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3351 struct intel_watermark_params *wm,
3352 int pixel_size,
3353 unsigned long latency_ns)
3354 {
3355 long entries_required, wm_size;
3356
3357 /*
3358 * Note: we need to make sure we don't overflow for various clock &
3359 * latency values.
3360 * clocks go from a few thousand to several hundred thousand.
3361 * latency is usually a few thousand
3362 */
3363 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3364 1000;
3365 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3366
3367 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
3368
3369 wm_size = wm->fifo_size - (entries_required + wm->guard_size);
3370
3371 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
3372
3373 /* Don't promote wm_size to unsigned... */
3374 if (wm_size > (long)wm->max_wm)
3375 wm_size = wm->max_wm;
3376 if (wm_size <= 0)
3377 wm_size = wm->default_wm;
3378 return wm_size;
3379 }
3380
3381 struct cxsr_latency {
3382 int is_desktop;
3383 int is_ddr3;
3384 unsigned long fsb_freq;
3385 unsigned long mem_freq;
3386 unsigned long display_sr;
3387 unsigned long display_hpll_disable;
3388 unsigned long cursor_sr;
3389 unsigned long cursor_hpll_disable;
3390 };
3391
3392 static const struct cxsr_latency cxsr_latency_table[] = {
3393 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3394 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3395 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3396 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3397 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
3398
3399 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3400 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3401 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3402 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3403 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
3404
3405 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3406 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3407 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3408 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3409 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
3410
3411 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3412 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3413 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3414 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3415 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
3416
3417 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3418 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3419 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3420 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3421 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
3422
3423 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3424 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3425 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3426 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3427 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
3428 };
3429
3430 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3431 int is_ddr3,
3432 int fsb,
3433 int mem)
3434 {
3435 const struct cxsr_latency *latency;
3436 int i;
3437
3438 if (fsb == 0 || mem == 0)
3439 return NULL;
3440
3441 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3442 latency = &cxsr_latency_table[i];
3443 if (is_desktop == latency->is_desktop &&
3444 is_ddr3 == latency->is_ddr3 &&
3445 fsb == latency->fsb_freq && mem == latency->mem_freq)
3446 return latency;
3447 }
3448
3449 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3450
3451 return NULL;
3452 }
3453
3454 static void pineview_disable_cxsr(struct drm_device *dev)
3455 {
3456 struct drm_i915_private *dev_priv = dev->dev_private;
3457
3458 /* deactivate cxsr */
3459 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3460 }
3461
3462 /*
3463 * Latency for FIFO fetches is dependent on several factors:
3464 * - memory configuration (speed, channels)
3465 * - chipset
3466 * - current MCH state
3467 * It can be fairly high in some situations, so here we assume a fairly
3468 * pessimal value. It's a tradeoff between extra memory fetches (if we
3469 * set this value too high, the FIFO will fetch frequently to stay full)
3470 * and power consumption (set it too low to save power and we might see
3471 * FIFO underruns and display "flicker").
3472 *
3473 * A value of 5us seems to be a good balance; safe for very low end
3474 * platforms but not overly aggressive on lower latency configs.
3475 */
3476 static const int latency_ns = 5000;
3477
3478 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3479 {
3480 struct drm_i915_private *dev_priv = dev->dev_private;
3481 uint32_t dsparb = I915_READ(DSPARB);
3482 int size;
3483
3484 size = dsparb & 0x7f;
3485 if (plane)
3486 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3487
3488 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3489 plane ? "B" : "A", size);
3490
3491 return size;
3492 }
3493
3494 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3495 {
3496 struct drm_i915_private *dev_priv = dev->dev_private;
3497 uint32_t dsparb = I915_READ(DSPARB);
3498 int size;
3499
3500 size = dsparb & 0x1ff;
3501 if (plane)
3502 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3503 size >>= 1; /* Convert to cachelines */
3504
3505 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3506 plane ? "B" : "A", size);
3507
3508 return size;
3509 }
3510
3511 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3512 {
3513 struct drm_i915_private *dev_priv = dev->dev_private;
3514 uint32_t dsparb = I915_READ(DSPARB);
3515 int size;
3516
3517 size = dsparb & 0x7f;
3518 size >>= 2; /* Convert to cachelines */
3519
3520 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3521 plane ? "B" : "A",
3522 size);
3523
3524 return size;
3525 }
3526
3527 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3528 {
3529 struct drm_i915_private *dev_priv = dev->dev_private;
3530 uint32_t dsparb = I915_READ(DSPARB);
3531 int size;
3532
3533 size = dsparb & 0x7f;
3534 size >>= 1; /* Convert to cachelines */
3535
3536 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3537 plane ? "B" : "A", size);
3538
3539 return size;
3540 }
3541
3542 static void pineview_update_wm(struct drm_device *dev, int planea_clock,
3543 int planeb_clock, int sr_hdisplay, int unused,
3544 int pixel_size)
3545 {
3546 struct drm_i915_private *dev_priv = dev->dev_private;
3547 const struct cxsr_latency *latency;
3548 u32 reg;
3549 unsigned long wm;
3550 int sr_clock;
3551
3552 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3553 dev_priv->fsb_freq, dev_priv->mem_freq);
3554 if (!latency) {
3555 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3556 pineview_disable_cxsr(dev);
3557 return;
3558 }
3559
3560 if (!planea_clock || !planeb_clock) {
3561 sr_clock = planea_clock ? planea_clock : planeb_clock;
3562
3563 /* Display SR */
3564 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
3565 pixel_size, latency->display_sr);
3566 reg = I915_READ(DSPFW1);
3567 reg &= ~DSPFW_SR_MASK;
3568 reg |= wm << DSPFW_SR_SHIFT;
3569 I915_WRITE(DSPFW1, reg);
3570 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3571
3572 /* cursor SR */
3573 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
3574 pixel_size, latency->cursor_sr);
3575 reg = I915_READ(DSPFW3);
3576 reg &= ~DSPFW_CURSOR_SR_MASK;
3577 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3578 I915_WRITE(DSPFW3, reg);
3579
3580 /* Display HPLL off SR */
3581 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
3582 pixel_size, latency->display_hpll_disable);
3583 reg = I915_READ(DSPFW3);
3584 reg &= ~DSPFW_HPLL_SR_MASK;
3585 reg |= wm & DSPFW_HPLL_SR_MASK;
3586 I915_WRITE(DSPFW3, reg);
3587
3588 /* cursor HPLL off SR */
3589 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
3590 pixel_size, latency->cursor_hpll_disable);
3591 reg = I915_READ(DSPFW3);
3592 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3593 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3594 I915_WRITE(DSPFW3, reg);
3595 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3596
3597 /* activate cxsr */
3598 I915_WRITE(DSPFW3,
3599 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3600 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3601 } else {
3602 pineview_disable_cxsr(dev);
3603 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3604 }
3605 }
3606
3607 static void g4x_update_wm(struct drm_device *dev, int planea_clock,
3608 int planeb_clock, int sr_hdisplay, int sr_htotal,
3609 int pixel_size)
3610 {
3611 struct drm_i915_private *dev_priv = dev->dev_private;
3612 int total_size, cacheline_size;
3613 int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
3614 struct intel_watermark_params planea_params, planeb_params;
3615 unsigned long line_time_us;
3616 int sr_clock, sr_entries = 0, entries_required;
3617
3618 /* Create copies of the base settings for each pipe */
3619 planea_params = planeb_params = g4x_wm_info;
3620
3621 /* Grab a couple of global values before we overwrite them */
3622 total_size = planea_params.fifo_size;
3623 cacheline_size = planea_params.cacheline_size;
3624
3625 /*
3626 * Note: we need to make sure we don't overflow for various clock &
3627 * latency values.
3628 * clocks go from a few thousand to several hundred thousand.
3629 * latency is usually a few thousand
3630 */
3631 entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
3632 1000;
3633 entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3634 planea_wm = entries_required + planea_params.guard_size;
3635
3636 entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
3637 1000;
3638 entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3639 planeb_wm = entries_required + planeb_params.guard_size;
3640
3641 cursora_wm = cursorb_wm = 16;
3642 cursor_sr = 32;
3643
3644 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3645
3646 /* Calc sr entries for one plane configs */
3647 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3648 /* self-refresh has much higher latency */
3649 static const int sr_latency_ns = 12000;
3650
3651 sr_clock = planea_clock ? planea_clock : planeb_clock;
3652 line_time_us = ((sr_htotal * 1000) / sr_clock);
3653
3654 /* Use ns/us then divide to preserve precision */
3655 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3656 pixel_size * sr_hdisplay;
3657 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3658
3659 entries_required = (((sr_latency_ns / line_time_us) +
3660 1000) / 1000) * pixel_size * 64;
3661 entries_required = DIV_ROUND_UP(entries_required,
3662 g4x_cursor_wm_info.cacheline_size);
3663 cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
3664
3665 if (cursor_sr > g4x_cursor_wm_info.max_wm)
3666 cursor_sr = g4x_cursor_wm_info.max_wm;
3667 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3668 "cursor %d\n", sr_entries, cursor_sr);
3669
3670 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3671 } else {
3672 /* Turn off self refresh if both pipes are enabled */
3673 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3674 & ~FW_BLC_SELF_EN);
3675 }
3676
3677 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3678 planea_wm, planeb_wm, sr_entries);
3679
3680 planea_wm &= 0x3f;
3681 planeb_wm &= 0x3f;
3682
3683 I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
3684 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3685 (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
3686 I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3687 (cursora_wm << DSPFW_CURSORA_SHIFT));
3688 /* HPLL off in SR has some issues on G4x... disable it */
3689 I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3690 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3691 }
3692
3693 static void i965_update_wm(struct drm_device *dev, int planea_clock,
3694 int planeb_clock, int sr_hdisplay, int sr_htotal,
3695 int pixel_size)
3696 {
3697 struct drm_i915_private *dev_priv = dev->dev_private;
3698 unsigned long line_time_us;
3699 int sr_clock, sr_entries, srwm = 1;
3700 int cursor_sr = 16;
3701
3702 /* Calc sr entries for one plane configs */
3703 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3704 /* self-refresh has much higher latency */
3705 static const int sr_latency_ns = 12000;
3706
3707 sr_clock = planea_clock ? planea_clock : planeb_clock;
3708 line_time_us = ((sr_htotal * 1000) / sr_clock);
3709
3710 /* Use ns/us then divide to preserve precision */
3711 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3712 pixel_size * sr_hdisplay;
3713 sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE);
3714 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
3715 srwm = I965_FIFO_SIZE - sr_entries;
3716 if (srwm < 0)
3717 srwm = 1;
3718 srwm &= 0x1ff;
3719
3720 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3721 pixel_size * 64;
3722 sr_entries = DIV_ROUND_UP(sr_entries,
3723 i965_cursor_wm_info.cacheline_size);
3724 cursor_sr = i965_cursor_wm_info.fifo_size -
3725 (sr_entries + i965_cursor_wm_info.guard_size);
3726
3727 if (cursor_sr > i965_cursor_wm_info.max_wm)
3728 cursor_sr = i965_cursor_wm_info.max_wm;
3729
3730 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3731 "cursor %d\n", srwm, cursor_sr);
3732
3733 if (IS_CRESTLINE(dev))
3734 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3735 } else {
3736 /* Turn off self refresh if both pipes are enabled */
3737 if (IS_CRESTLINE(dev))
3738 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3739 & ~FW_BLC_SELF_EN);
3740 }
3741
3742 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3743 srwm);
3744
3745 /* 965 has limitations... */
3746 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
3747 (8 << 0));
3748 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3749 /* update cursor SR watermark */
3750 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3751 }
3752
3753 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
3754 int planeb_clock, int sr_hdisplay, int sr_htotal,
3755 int pixel_size)
3756 {
3757 struct drm_i915_private *dev_priv = dev->dev_private;
3758 uint32_t fwater_lo;
3759 uint32_t fwater_hi;
3760 int total_size, cacheline_size, cwm, srwm = 1;
3761 int planea_wm, planeb_wm;
3762 struct intel_watermark_params planea_params, planeb_params;
3763 unsigned long line_time_us;
3764 int sr_clock, sr_entries = 0, sr_enabled = 0;
3765
3766 /* Create copies of the base settings for each pipe */
3767 if (IS_CRESTLINE(dev) || IS_I945GM(dev))
3768 planea_params = planeb_params = i945_wm_info;
3769 else if (!IS_GEN2(dev))
3770 planea_params = planeb_params = i915_wm_info;
3771 else
3772 planea_params = planeb_params = i855_wm_info;
3773
3774 /* Grab a couple of global values before we overwrite them */
3775 total_size = planea_params.fifo_size;
3776 cacheline_size = planea_params.cacheline_size;
3777
3778 /* Update per-plane FIFO sizes */
3779 planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3780 planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3781
3782 planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3783 pixel_size, latency_ns);
3784 planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3785 pixel_size, latency_ns);
3786 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3787
3788 /*
3789 * Overlay gets an aggressive default since video jitter is bad.
3790 */
3791 cwm = 2;
3792
3793 /* Play safe and disable self-refresh before adjusting watermarks. */
3794 if (IS_I945G(dev) || IS_I945GM(dev))
3795 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
3796 else if (IS_I915GM(dev))
3797 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3798
3799 /* Calc sr entries for one plane configs */
3800 if (HAS_FW_BLC(dev) && sr_hdisplay &&
3801 (!planea_clock || !planeb_clock)) {
3802 /* self-refresh has much higher latency */
3803 static const int sr_latency_ns = 6000;
3804
3805 sr_clock = planea_clock ? planea_clock : planeb_clock;
3806 line_time_us = ((sr_htotal * 1000) / sr_clock);
3807
3808 /* Use ns/us then divide to preserve precision */
3809 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3810 pixel_size * sr_hdisplay;
3811 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3812 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3813 srwm = total_size - sr_entries;
3814 if (srwm < 0)
3815 srwm = 1;
3816
3817 if (IS_I945G(dev) || IS_I945GM(dev))
3818 I915_WRITE(FW_BLC_SELF,
3819 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3820 else if (IS_I915GM(dev))
3821 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3822
3823 sr_enabled = 1;
3824 }
3825
3826 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3827 planea_wm, planeb_wm, cwm, srwm);
3828
3829 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3830 fwater_hi = (cwm & 0x1f);
3831
3832 /* Set request length to 8 cachelines per fetch */
3833 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3834 fwater_hi = fwater_hi | (1 << 8);
3835
3836 I915_WRITE(FW_BLC, fwater_lo);
3837 I915_WRITE(FW_BLC2, fwater_hi);
3838
3839 if (sr_enabled) {
3840 if (IS_I945G(dev) || IS_I945GM(dev))
3841 I915_WRITE(FW_BLC_SELF,
3842 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
3843 else if (IS_I915GM(dev))
3844 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3845 DRM_DEBUG_KMS("memory self refresh enabled\n");
3846 } else
3847 DRM_DEBUG_KMS("memory self refresh disabled\n");
3848 }
3849
3850 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3851 int unused2, int unused3, int pixel_size)
3852 {
3853 struct drm_i915_private *dev_priv = dev->dev_private;
3854 uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3855 int planea_wm;
3856
3857 i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3858
3859 planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3860 pixel_size, latency_ns);
3861 fwater_lo |= (3<<8) | planea_wm;
3862
3863 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3864
3865 I915_WRITE(FW_BLC, fwater_lo);
3866 }
3867
3868 #define ILK_LP0_PLANE_LATENCY 700
3869 #define ILK_LP0_CURSOR_LATENCY 1300
3870
3871 static bool ironlake_compute_wm0(struct drm_device *dev,
3872 int pipe,
3873 const struct intel_watermark_params *display,
3874 int display_latency_ns,
3875 const struct intel_watermark_params *cursor,
3876 int cursor_latency_ns,
3877 int *plane_wm,
3878 int *cursor_wm)
3879 {
3880 struct drm_crtc *crtc;
3881 int htotal, hdisplay, clock, pixel_size;
3882 int line_time_us, line_count;
3883 int entries, tlb_miss;
3884
3885 crtc = intel_get_crtc_for_pipe(dev, pipe);
3886 if (crtc->fb == NULL || !crtc->enabled)
3887 return false;
3888
3889 htotal = crtc->mode.htotal;
3890 hdisplay = crtc->mode.hdisplay;
3891 clock = crtc->mode.clock;
3892 pixel_size = crtc->fb->bits_per_pixel / 8;
3893
3894 /* Use the small buffer method to calculate plane watermark */
3895 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3896 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3897 if (tlb_miss > 0)
3898 entries += tlb_miss;
3899 entries = DIV_ROUND_UP(entries, display->cacheline_size);
3900 *plane_wm = entries + display->guard_size;
3901 if (*plane_wm > (int)display->max_wm)
3902 *plane_wm = display->max_wm;
3903
3904 /* Use the large buffer method to calculate cursor watermark */
3905 line_time_us = ((htotal * 1000) / clock);
3906 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3907 entries = line_count * 64 * pixel_size;
3908 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3909 if (tlb_miss > 0)
3910 entries += tlb_miss;
3911 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3912 *cursor_wm = entries + cursor->guard_size;
3913 if (*cursor_wm > (int)cursor->max_wm)
3914 *cursor_wm = (int)cursor->max_wm;
3915
3916 return true;
3917 }
3918
3919 /*
3920 * Check the wm result.
3921 *
3922 * If any calculated watermark values is larger than the maximum value that
3923 * can be programmed into the associated watermark register, that watermark
3924 * must be disabled.
3925 */
3926 static bool ironlake_check_srwm(struct drm_device *dev, int level,
3927 int fbc_wm, int display_wm, int cursor_wm,
3928 const struct intel_watermark_params *display,
3929 const struct intel_watermark_params *cursor)
3930 {
3931 struct drm_i915_private *dev_priv = dev->dev_private;
3932
3933 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
3934 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
3935
3936 if (fbc_wm > SNB_FBC_MAX_SRWM) {
3937 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
3938 fbc_wm, SNB_FBC_MAX_SRWM, level);
3939
3940 /* fbc has it's own way to disable FBC WM */
3941 I915_WRITE(DISP_ARB_CTL,
3942 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
3943 return false;
3944 }
3945
3946 if (display_wm > display->max_wm) {
3947 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
3948 display_wm, SNB_DISPLAY_MAX_SRWM, level);
3949 return false;
3950 }
3951
3952 if (cursor_wm > cursor->max_wm) {
3953 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
3954 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
3955 return false;
3956 }
3957
3958 if (!(fbc_wm || display_wm || cursor_wm)) {
3959 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
3960 return false;
3961 }
3962
3963 return true;
3964 }
3965
3966 /*
3967 * Compute watermark values of WM[1-3],
3968 */
3969 static bool ironlake_compute_srwm(struct drm_device *dev, int level,
3970 int hdisplay, int htotal,
3971 int pixel_size, int clock, int latency_ns,
3972 const struct intel_watermark_params *display,
3973 const struct intel_watermark_params *cursor,
3974 int *fbc_wm, int *display_wm, int *cursor_wm)
3975 {
3976
3977 unsigned long line_time_us;
3978 int line_count, line_size;
3979 int small, large;
3980 int entries;
3981
3982 if (!latency_ns) {
3983 *fbc_wm = *display_wm = *cursor_wm = 0;
3984 return false;
3985 }
3986
3987 line_time_us = (htotal * 1000) / clock;
3988 line_count = (latency_ns / line_time_us + 1000) / 1000;
3989 line_size = hdisplay * pixel_size;
3990
3991 /* Use the minimum of the small and large buffer method for primary */
3992 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3993 large = line_count * line_size;
3994
3995 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3996 *display_wm = entries + display->guard_size;
3997
3998 /*
3999 * Spec says:
4000 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4001 */
4002 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4003
4004 /* calculate the self-refresh watermark for display cursor */
4005 entries = line_count * pixel_size * 64;
4006 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4007 *cursor_wm = entries + cursor->guard_size;
4008
4009 return ironlake_check_srwm(dev, level,
4010 *fbc_wm, *display_wm, *cursor_wm,
4011 display, cursor);
4012 }
4013
4014 static void ironlake_update_wm(struct drm_device *dev,
4015 int planea_clock, int planeb_clock,
4016 int hdisplay, int htotal,
4017 int pixel_size)
4018 {
4019 struct drm_i915_private *dev_priv = dev->dev_private;
4020 int fbc_wm, plane_wm, cursor_wm, enabled;
4021 int clock;
4022
4023 enabled = 0;
4024 if (ironlake_compute_wm0(dev, 0,
4025 &ironlake_display_wm_info,
4026 ILK_LP0_PLANE_LATENCY,
4027 &ironlake_cursor_wm_info,
4028 ILK_LP0_CURSOR_LATENCY,
4029 &plane_wm, &cursor_wm)) {
4030 I915_WRITE(WM0_PIPEA_ILK,
4031 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4032 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4033 " plane %d, " "cursor: %d\n",
4034 plane_wm, cursor_wm);
4035 enabled++;
4036 }
4037
4038 if (ironlake_compute_wm0(dev, 1,
4039 &ironlake_display_wm_info,
4040 ILK_LP0_PLANE_LATENCY,
4041 &ironlake_cursor_wm_info,
4042 ILK_LP0_CURSOR_LATENCY,
4043 &plane_wm, &cursor_wm)) {
4044 I915_WRITE(WM0_PIPEB_ILK,
4045 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4046 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4047 " plane %d, cursor: %d\n",
4048 plane_wm, cursor_wm);
4049 enabled++;
4050 }
4051
4052 /*
4053 * Calculate and update the self-refresh watermark only when one
4054 * display plane is used.
4055 */
4056 I915_WRITE(WM3_LP_ILK, 0);
4057 I915_WRITE(WM2_LP_ILK, 0);
4058 I915_WRITE(WM1_LP_ILK, 0);
4059
4060 if (enabled != 1)
4061 return;
4062
4063 clock = planea_clock ? planea_clock : planeb_clock;
4064
4065 /* WM1 */
4066 if (!ironlake_compute_srwm(dev, 1, hdisplay, htotal, pixel_size,
4067 clock, ILK_READ_WM1_LATENCY() * 500,
4068 &ironlake_display_srwm_info,
4069 &ironlake_cursor_srwm_info,
4070 &fbc_wm, &plane_wm, &cursor_wm))
4071 return;
4072
4073 I915_WRITE(WM1_LP_ILK,
4074 WM1_LP_SR_EN |
4075 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4076 (fbc_wm << WM1_LP_FBC_SHIFT) |
4077 (plane_wm << WM1_LP_SR_SHIFT) |
4078 cursor_wm);
4079
4080 /* WM2 */
4081 if (!ironlake_compute_srwm(dev, 2, hdisplay, htotal, pixel_size,
4082 clock, ILK_READ_WM2_LATENCY() * 500,
4083 &ironlake_display_srwm_info,
4084 &ironlake_cursor_srwm_info,
4085 &fbc_wm, &plane_wm, &cursor_wm))
4086 return;
4087
4088 I915_WRITE(WM2_LP_ILK,
4089 WM2_LP_EN |
4090 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4091 (fbc_wm << WM1_LP_FBC_SHIFT) |
4092 (plane_wm << WM1_LP_SR_SHIFT) |
4093 cursor_wm);
4094
4095 /*
4096 * WM3 is unsupported on ILK, probably because we don't have latency
4097 * data for that power state
4098 */
4099 }
4100
4101 static void sandybridge_update_wm(struct drm_device *dev,
4102 int planea_clock, int planeb_clock,
4103 int hdisplay, int htotal,
4104 int pixel_size)
4105 {
4106 struct drm_i915_private *dev_priv = dev->dev_private;
4107 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
4108 int fbc_wm, plane_wm, cursor_wm, enabled;
4109 int clock;
4110
4111 enabled = 0;
4112 if (ironlake_compute_wm0(dev, 0,
4113 &sandybridge_display_wm_info, latency,
4114 &sandybridge_cursor_wm_info, latency,
4115 &plane_wm, &cursor_wm)) {
4116 I915_WRITE(WM0_PIPEA_ILK,
4117 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4118 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4119 " plane %d, " "cursor: %d\n",
4120 plane_wm, cursor_wm);
4121 enabled++;
4122 }
4123
4124 if (ironlake_compute_wm0(dev, 1,
4125 &sandybridge_display_wm_info, latency,
4126 &sandybridge_cursor_wm_info, latency,
4127 &plane_wm, &cursor_wm)) {
4128 I915_WRITE(WM0_PIPEB_ILK,
4129 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4130 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4131 " plane %d, cursor: %d\n",
4132 plane_wm, cursor_wm);
4133 enabled++;
4134 }
4135
4136 /*
4137 * Calculate and update the self-refresh watermark only when one
4138 * display plane is used.
4139 *
4140 * SNB support 3 levels of watermark.
4141 *
4142 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4143 * and disabled in the descending order
4144 *
4145 */
4146 I915_WRITE(WM3_LP_ILK, 0);
4147 I915_WRITE(WM2_LP_ILK, 0);
4148 I915_WRITE(WM1_LP_ILK, 0);
4149
4150 if (enabled != 1)
4151 return;
4152
4153 clock = planea_clock ? planea_clock : planeb_clock;
4154
4155 /* WM1 */
4156 if (!ironlake_compute_srwm(dev, 1, hdisplay, htotal, pixel_size,
4157 clock, SNB_READ_WM1_LATENCY() * 500,
4158 &sandybridge_display_srwm_info,
4159 &sandybridge_cursor_srwm_info,
4160 &fbc_wm, &plane_wm, &cursor_wm))
4161 return;
4162
4163 I915_WRITE(WM1_LP_ILK,
4164 WM1_LP_SR_EN |
4165 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4166 (fbc_wm << WM1_LP_FBC_SHIFT) |
4167 (plane_wm << WM1_LP_SR_SHIFT) |
4168 cursor_wm);
4169
4170 /* WM2 */
4171 if (!ironlake_compute_srwm(dev, 2,
4172 hdisplay, htotal, pixel_size,
4173 clock, SNB_READ_WM2_LATENCY() * 500,
4174 &sandybridge_display_srwm_info,
4175 &sandybridge_cursor_srwm_info,
4176 &fbc_wm, &plane_wm, &cursor_wm))
4177 return;
4178
4179 I915_WRITE(WM2_LP_ILK,
4180 WM2_LP_EN |
4181 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4182 (fbc_wm << WM1_LP_FBC_SHIFT) |
4183 (plane_wm << WM1_LP_SR_SHIFT) |
4184 cursor_wm);
4185
4186 /* WM3 */
4187 if (!ironlake_compute_srwm(dev, 3,
4188 hdisplay, htotal, pixel_size,
4189 clock, SNB_READ_WM3_LATENCY() * 500,
4190 &sandybridge_display_srwm_info,
4191 &sandybridge_cursor_srwm_info,
4192 &fbc_wm, &plane_wm, &cursor_wm))
4193 return;
4194
4195 I915_WRITE(WM3_LP_ILK,
4196 WM3_LP_EN |
4197 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4198 (fbc_wm << WM1_LP_FBC_SHIFT) |
4199 (plane_wm << WM1_LP_SR_SHIFT) |
4200 cursor_wm);
4201 }
4202
4203 /**
4204 * intel_update_watermarks - update FIFO watermark values based on current modes
4205 *
4206 * Calculate watermark values for the various WM regs based on current mode
4207 * and plane configuration.
4208 *
4209 * There are several cases to deal with here:
4210 * - normal (i.e. non-self-refresh)
4211 * - self-refresh (SR) mode
4212 * - lines are large relative to FIFO size (buffer can hold up to 2)
4213 * - lines are small relative to FIFO size (buffer can hold more than 2
4214 * lines), so need to account for TLB latency
4215 *
4216 * The normal calculation is:
4217 * watermark = dotclock * bytes per pixel * latency
4218 * where latency is platform & configuration dependent (we assume pessimal
4219 * values here).
4220 *
4221 * The SR calculation is:
4222 * watermark = (trunc(latency/line time)+1) * surface width *
4223 * bytes per pixel
4224 * where
4225 * line time = htotal / dotclock
4226 * surface width = hdisplay for normal plane and 64 for cursor
4227 * and latency is assumed to be high, as above.
4228 *
4229 * The final value programmed to the register should always be rounded up,
4230 * and include an extra 2 entries to account for clock crossings.
4231 *
4232 * We don't use the sprite, so we can ignore that. And on Crestline we have
4233 * to set the non-SR watermarks to 8.
4234 */
4235 static void intel_update_watermarks(struct drm_device *dev)
4236 {
4237 struct drm_i915_private *dev_priv = dev->dev_private;
4238 struct drm_crtc *crtc;
4239 int sr_hdisplay = 0;
4240 unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
4241 int enabled = 0, pixel_size = 0;
4242 int sr_htotal = 0;
4243
4244 if (!dev_priv->display.update_wm)
4245 return;
4246
4247 /* Get the clock config from both planes */
4248 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4249 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4250 if (intel_crtc->active) {
4251 enabled++;
4252 if (intel_crtc->plane == 0) {
4253 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
4254 intel_crtc->pipe, crtc->mode.clock);
4255 planea_clock = crtc->mode.clock;
4256 } else {
4257 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
4258 intel_crtc->pipe, crtc->mode.clock);
4259 planeb_clock = crtc->mode.clock;
4260 }
4261 sr_hdisplay = crtc->mode.hdisplay;
4262 sr_clock = crtc->mode.clock;
4263 sr_htotal = crtc->mode.htotal;
4264 if (crtc->fb)
4265 pixel_size = crtc->fb->bits_per_pixel / 8;
4266 else
4267 pixel_size = 4; /* by default */
4268 }
4269 }
4270
4271 if (enabled <= 0)
4272 return;
4273
4274 dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
4275 sr_hdisplay, sr_htotal, pixel_size);
4276 }
4277
4278 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4279 {
4280 return dev_priv->lvds_use_ssc && i915_panel_use_ssc;
4281 }
4282
4283 static int intel_crtc_mode_set(struct drm_crtc *crtc,
4284 struct drm_display_mode *mode,
4285 struct drm_display_mode *adjusted_mode,
4286 int x, int y,
4287 struct drm_framebuffer *old_fb)
4288 {
4289 struct drm_device *dev = crtc->dev;
4290 struct drm_i915_private *dev_priv = dev->dev_private;
4291 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4292 int pipe = intel_crtc->pipe;
4293 int plane = intel_crtc->plane;
4294 u32 fp_reg, dpll_reg;
4295 int refclk, num_connectors = 0;
4296 intel_clock_t clock, reduced_clock;
4297 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4298 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
4299 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4300 struct intel_encoder *has_edp_encoder = NULL;
4301 struct drm_mode_config *mode_config = &dev->mode_config;
4302 struct intel_encoder *encoder;
4303 const intel_limit_t *limit;
4304 int ret;
4305 struct fdi_m_n m_n = {0};
4306 u32 reg, temp;
4307 u32 lvds_sync = 0;
4308 int target_clock;
4309
4310 drm_vblank_pre_modeset(dev, pipe);
4311
4312 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4313 if (encoder->base.crtc != crtc)
4314 continue;
4315
4316 switch (encoder->type) {
4317 case INTEL_OUTPUT_LVDS:
4318 is_lvds = true;
4319 break;
4320 case INTEL_OUTPUT_SDVO:
4321 case INTEL_OUTPUT_HDMI:
4322 is_sdvo = true;
4323 if (encoder->needs_tv_clock)
4324 is_tv = true;
4325 break;
4326 case INTEL_OUTPUT_DVO:
4327 is_dvo = true;
4328 break;
4329 case INTEL_OUTPUT_TVOUT:
4330 is_tv = true;
4331 break;
4332 case INTEL_OUTPUT_ANALOG:
4333 is_crt = true;
4334 break;
4335 case INTEL_OUTPUT_DISPLAYPORT:
4336 is_dp = true;
4337 break;
4338 case INTEL_OUTPUT_EDP:
4339 has_edp_encoder = encoder;
4340 break;
4341 }
4342
4343 num_connectors++;
4344 }
4345
4346 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4347 refclk = dev_priv->lvds_ssc_freq * 1000;
4348 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4349 refclk / 1000);
4350 } else if (!IS_GEN2(dev)) {
4351 refclk = 96000;
4352 if (HAS_PCH_SPLIT(dev) &&
4353 (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)))
4354 refclk = 120000; /* 120Mhz refclk */
4355 } else {
4356 refclk = 48000;
4357 }
4358
4359 /*
4360 * Returns a set of divisors for the desired target clock with the given
4361 * refclk, or FALSE. The returned values represent the clock equation:
4362 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4363 */
4364 limit = intel_limit(crtc, refclk);
4365 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
4366 if (!ok) {
4367 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4368 drm_vblank_post_modeset(dev, pipe);
4369 return -EINVAL;
4370 }
4371
4372 /* Ensure that the cursor is valid for the new mode before changing... */
4373 intel_crtc_update_cursor(crtc, true);
4374
4375 if (is_lvds && dev_priv->lvds_downclock_avail) {
4376 has_reduced_clock = limit->find_pll(limit, crtc,
4377 dev_priv->lvds_downclock,
4378 refclk,
4379 &reduced_clock);
4380 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4381 /*
4382 * If the different P is found, it means that we can't
4383 * switch the display clock by using the FP0/FP1.
4384 * In such case we will disable the LVDS downclock
4385 * feature.
4386 */
4387 DRM_DEBUG_KMS("Different P is found for "
4388 "LVDS clock/downclock\n");
4389 has_reduced_clock = 0;
4390 }
4391 }
4392 /* SDVO TV has fixed PLL values depend on its clock range,
4393 this mirrors vbios setting. */
4394 if (is_sdvo && is_tv) {
4395 if (adjusted_mode->clock >= 100000
4396 && adjusted_mode->clock < 140500) {
4397 clock.p1 = 2;
4398 clock.p2 = 10;
4399 clock.n = 3;
4400 clock.m1 = 16;
4401 clock.m2 = 8;
4402 } else if (adjusted_mode->clock >= 140500
4403 && adjusted_mode->clock <= 200000) {
4404 clock.p1 = 1;
4405 clock.p2 = 10;
4406 clock.n = 6;
4407 clock.m1 = 12;
4408 clock.m2 = 8;
4409 }
4410 }
4411
4412 /* FDI link */
4413 if (HAS_PCH_SPLIT(dev)) {
4414 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4415 int lane = 0, link_bw, bpp;
4416 /* CPU eDP doesn't require FDI link, so just set DP M/N
4417 according to current link config */
4418 if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4419 target_clock = mode->clock;
4420 intel_edp_link_config(has_edp_encoder,
4421 &lane, &link_bw);
4422 } else {
4423 /* [e]DP over FDI requires target mode clock
4424 instead of link clock */
4425 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
4426 target_clock = mode->clock;
4427 else
4428 target_clock = adjusted_mode->clock;
4429
4430 /* FDI is a binary signal running at ~2.7GHz, encoding
4431 * each output octet as 10 bits. The actual frequency
4432 * is stored as a divider into a 100MHz clock, and the
4433 * mode pixel clock is stored in units of 1KHz.
4434 * Hence the bw of each lane in terms of the mode signal
4435 * is:
4436 */
4437 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4438 }
4439
4440 /* determine panel color depth */
4441 temp = I915_READ(PIPECONF(pipe));
4442 temp &= ~PIPE_BPC_MASK;
4443 if (is_lvds) {
4444 /* the BPC will be 6 if it is 18-bit LVDS panel */
4445 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
4446 temp |= PIPE_8BPC;
4447 else
4448 temp |= PIPE_6BPC;
4449 } else if (has_edp_encoder) {
4450 switch (dev_priv->edp.bpp/3) {
4451 case 8:
4452 temp |= PIPE_8BPC;
4453 break;
4454 case 10:
4455 temp |= PIPE_10BPC;
4456 break;
4457 case 6:
4458 temp |= PIPE_6BPC;
4459 break;
4460 case 12:
4461 temp |= PIPE_12BPC;
4462 break;
4463 }
4464 } else
4465 temp |= PIPE_8BPC;
4466 I915_WRITE(PIPECONF(pipe), temp);
4467
4468 switch (temp & PIPE_BPC_MASK) {
4469 case PIPE_8BPC:
4470 bpp = 24;
4471 break;
4472 case PIPE_10BPC:
4473 bpp = 30;
4474 break;
4475 case PIPE_6BPC:
4476 bpp = 18;
4477 break;
4478 case PIPE_12BPC:
4479 bpp = 36;
4480 break;
4481 default:
4482 DRM_ERROR("unknown pipe bpc value\n");
4483 bpp = 24;
4484 }
4485
4486 if (!lane) {
4487 /*
4488 * Account for spread spectrum to avoid
4489 * oversubscribing the link. Max center spread
4490 * is 2.5%; use 5% for safety's sake.
4491 */
4492 u32 bps = target_clock * bpp * 21 / 20;
4493 lane = bps / (link_bw * 8) + 1;
4494 }
4495
4496 intel_crtc->fdi_lanes = lane;
4497
4498 if (pixel_multiplier > 1)
4499 link_bw *= pixel_multiplier;
4500 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
4501 }
4502
4503 /* Ironlake: try to setup display ref clock before DPLL
4504 * enabling. This is only under driver's control after
4505 * PCH B stepping, previous chipset stepping should be
4506 * ignoring this setting.
4507 */
4508 if (HAS_PCH_SPLIT(dev)) {
4509 /*XXX BIOS treats 16:31 as a mask for 0:15 */
4510
4511 temp = I915_READ(PCH_DREF_CONTROL);
4512
4513 /* First clear the current state for output switching */
4514 temp &= ~DREF_SSC1_ENABLE;
4515 temp &= ~DREF_SSC4_ENABLE;
4516 temp &= ~DREF_SUPERSPREAD_SOURCE_MASK;
4517 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4518 temp &= ~DREF_SSC_SOURCE_MASK;
4519 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4520 I915_WRITE(PCH_DREF_CONTROL, temp);
4521
4522 POSTING_READ(PCH_DREF_CONTROL);
4523 udelay(200);
4524
4525 if ((is_lvds || has_edp_encoder) &&
4526 intel_panel_use_ssc(dev_priv)) {
4527 temp |= DREF_SSC_SOURCE_ENABLE;
4528 if (has_edp_encoder) {
4529 if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4530 /* Enable CPU source on CPU attached eDP */
4531 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4532 } else {
4533 /* Enable SSC on PCH eDP if needed */
4534 temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
4535 }
4536 I915_WRITE(PCH_DREF_CONTROL, temp);
4537 }
4538 if (!dev_priv->display_clock_mode)
4539 temp |= DREF_SSC1_ENABLE;
4540 } else {
4541 if (dev_priv->display_clock_mode)
4542 temp |= DREF_NONSPREAD_CK505_ENABLE;
4543 else
4544 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4545 if (has_edp_encoder &&
4546 !intel_encoder_is_pch_edp(&has_edp_encoder->base))
4547 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4548 }
4549
4550 I915_WRITE(PCH_DREF_CONTROL, temp);
4551 POSTING_READ(PCH_DREF_CONTROL);
4552 udelay(200);
4553 }
4554
4555 if (IS_PINEVIEW(dev)) {
4556 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
4557 if (has_reduced_clock)
4558 fp2 = (1 << reduced_clock.n) << 16 |
4559 reduced_clock.m1 << 8 | reduced_clock.m2;
4560 } else {
4561 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4562 if (has_reduced_clock)
4563 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4564 reduced_clock.m2;
4565 }
4566
4567 /* Enable autotuning of the PLL clock (if permissible) */
4568 if (HAS_PCH_SPLIT(dev)) {
4569 int factor = 21;
4570
4571 if (is_lvds) {
4572 if ((intel_panel_use_ssc(dev_priv) &&
4573 dev_priv->lvds_ssc_freq == 100) ||
4574 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4575 factor = 25;
4576 } else if (is_sdvo && is_tv)
4577 factor = 20;
4578
4579 if (clock.m1 < factor * clock.n)
4580 fp |= FP_CB_TUNE;
4581 }
4582
4583 dpll = 0;
4584 if (!HAS_PCH_SPLIT(dev))
4585 dpll = DPLL_VGA_MODE_DIS;
4586
4587 if (!IS_GEN2(dev)) {
4588 if (is_lvds)
4589 dpll |= DPLLB_MODE_LVDS;
4590 else
4591 dpll |= DPLLB_MODE_DAC_SERIAL;
4592 if (is_sdvo) {
4593 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4594 if (pixel_multiplier > 1) {
4595 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4596 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4597 else if (HAS_PCH_SPLIT(dev))
4598 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4599 }
4600 dpll |= DPLL_DVO_HIGH_SPEED;
4601 }
4602 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
4603 dpll |= DPLL_DVO_HIGH_SPEED;
4604
4605 /* compute bitmask from p1 value */
4606 if (IS_PINEVIEW(dev))
4607 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4608 else {
4609 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4610 /* also FPA1 */
4611 if (HAS_PCH_SPLIT(dev))
4612 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4613 if (IS_G4X(dev) && has_reduced_clock)
4614 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4615 }
4616 switch (clock.p2) {
4617 case 5:
4618 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4619 break;
4620 case 7:
4621 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4622 break;
4623 case 10:
4624 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4625 break;
4626 case 14:
4627 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4628 break;
4629 }
4630 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
4631 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4632 } else {
4633 if (is_lvds) {
4634 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4635 } else {
4636 if (clock.p1 == 2)
4637 dpll |= PLL_P1_DIVIDE_BY_TWO;
4638 else
4639 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4640 if (clock.p2 == 4)
4641 dpll |= PLL_P2_DIVIDE_BY_4;
4642 }
4643 }
4644
4645 if (is_sdvo && is_tv)
4646 dpll |= PLL_REF_INPUT_TVCLKINBC;
4647 else if (is_tv)
4648 /* XXX: just matching BIOS for now */
4649 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4650 dpll |= 3;
4651 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4652 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4653 else
4654 dpll |= PLL_REF_INPUT_DREFCLK;
4655
4656 /* setup pipeconf */
4657 pipeconf = I915_READ(PIPECONF(pipe));
4658
4659 /* Set up the display plane register */
4660 dspcntr = DISPPLANE_GAMMA_ENABLE;
4661
4662 /* Ironlake's plane is forced to pipe, bit 24 is to
4663 enable color space conversion */
4664 if (!HAS_PCH_SPLIT(dev)) {
4665 if (pipe == 0)
4666 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4667 else
4668 dspcntr |= DISPPLANE_SEL_PIPE_B;
4669 }
4670
4671 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4672 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4673 * core speed.
4674 *
4675 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4676 * pipe == 0 check?
4677 */
4678 if (mode->clock >
4679 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4680 pipeconf |= PIPECONF_DOUBLE_WIDE;
4681 else
4682 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4683 }
4684
4685 if (!HAS_PCH_SPLIT(dev))
4686 dpll |= DPLL_VCO_ENABLE;
4687
4688 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4689 drm_mode_debug_printmodeline(mode);
4690
4691 /* assign to Ironlake registers */
4692 if (HAS_PCH_SPLIT(dev)) {
4693 fp_reg = PCH_FP0(pipe);
4694 dpll_reg = PCH_DPLL(pipe);
4695 } else {
4696 fp_reg = FP0(pipe);
4697 dpll_reg = DPLL(pipe);
4698 }
4699
4700 /* PCH eDP needs FDI, but CPU eDP does not */
4701 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4702 I915_WRITE(fp_reg, fp);
4703 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
4704
4705 POSTING_READ(dpll_reg);
4706 udelay(150);
4707 }
4708
4709 /* enable transcoder DPLL */
4710 if (HAS_PCH_CPT(dev)) {
4711 temp = I915_READ(PCH_DPLL_SEL);
4712 if (pipe == 0)
4713 temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
4714 else
4715 temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
4716 I915_WRITE(PCH_DPLL_SEL, temp);
4717
4718 POSTING_READ(PCH_DPLL_SEL);
4719 udelay(150);
4720 }
4721
4722 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4723 * This is an exception to the general rule that mode_set doesn't turn
4724 * things on.
4725 */
4726 if (is_lvds) {
4727 reg = LVDS;
4728 if (HAS_PCH_SPLIT(dev))
4729 reg = PCH_LVDS;
4730
4731 temp = I915_READ(reg);
4732 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4733 if (pipe == 1) {
4734 if (HAS_PCH_CPT(dev))
4735 temp |= PORT_TRANS_B_SEL_CPT;
4736 else
4737 temp |= LVDS_PIPEB_SELECT;
4738 } else {
4739 if (HAS_PCH_CPT(dev))
4740 temp &= ~PORT_TRANS_SEL_MASK;
4741 else
4742 temp &= ~LVDS_PIPEB_SELECT;
4743 }
4744 /* set the corresponsding LVDS_BORDER bit */
4745 temp |= dev_priv->lvds_border_bits;
4746 /* Set the B0-B3 data pairs corresponding to whether we're going to
4747 * set the DPLLs for dual-channel mode or not.
4748 */
4749 if (clock.p2 == 7)
4750 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4751 else
4752 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4753
4754 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4755 * appropriately here, but we need to look more thoroughly into how
4756 * panels behave in the two modes.
4757 */
4758 /* set the dithering flag on non-PCH LVDS as needed */
4759 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
4760 if (dev_priv->lvds_dither)
4761 temp |= LVDS_ENABLE_DITHER;
4762 else
4763 temp &= ~LVDS_ENABLE_DITHER;
4764 }
4765 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4766 lvds_sync |= LVDS_HSYNC_POLARITY;
4767 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4768 lvds_sync |= LVDS_VSYNC_POLARITY;
4769 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
4770 != lvds_sync) {
4771 char flags[2] = "-+";
4772 DRM_INFO("Changing LVDS panel from "
4773 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
4774 flags[!(temp & LVDS_HSYNC_POLARITY)],
4775 flags[!(temp & LVDS_VSYNC_POLARITY)],
4776 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
4777 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
4778 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4779 temp |= lvds_sync;
4780 }
4781 I915_WRITE(reg, temp);
4782 }
4783
4784 /* set the dithering flag and clear for anything other than a panel. */
4785 if (HAS_PCH_SPLIT(dev)) {
4786 pipeconf &= ~PIPECONF_DITHER_EN;
4787 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
4788 if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
4789 pipeconf |= PIPECONF_DITHER_EN;
4790 pipeconf |= PIPECONF_DITHER_TYPE_ST1;
4791 }
4792 }
4793
4794 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4795 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4796 } else if (HAS_PCH_SPLIT(dev)) {
4797 /* For non-DP output, clear any trans DP clock recovery setting.*/
4798 if (pipe == 0) {
4799 I915_WRITE(TRANSA_DATA_M1, 0);
4800 I915_WRITE(TRANSA_DATA_N1, 0);
4801 I915_WRITE(TRANSA_DP_LINK_M1, 0);
4802 I915_WRITE(TRANSA_DP_LINK_N1, 0);
4803 } else {
4804 I915_WRITE(TRANSB_DATA_M1, 0);
4805 I915_WRITE(TRANSB_DATA_N1, 0);
4806 I915_WRITE(TRANSB_DP_LINK_M1, 0);
4807 I915_WRITE(TRANSB_DP_LINK_N1, 0);
4808 }
4809 }
4810
4811 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4812 I915_WRITE(dpll_reg, dpll);
4813
4814 /* Wait for the clocks to stabilize. */
4815 POSTING_READ(dpll_reg);
4816 udelay(150);
4817
4818 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
4819 temp = 0;
4820 if (is_sdvo) {
4821 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4822 if (temp > 1)
4823 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4824 else
4825 temp = 0;
4826 }
4827 I915_WRITE(DPLL_MD(pipe), temp);
4828 } else {
4829 /* The pixel multiplier can only be updated once the
4830 * DPLL is enabled and the clocks are stable.
4831 *
4832 * So write it again.
4833 */
4834 I915_WRITE(dpll_reg, dpll);
4835 }
4836 }
4837
4838 intel_crtc->lowfreq_avail = false;
4839 if (is_lvds && has_reduced_clock && i915_powersave) {
4840 I915_WRITE(fp_reg + 4, fp2);
4841 intel_crtc->lowfreq_avail = true;
4842 if (HAS_PIPE_CXSR(dev)) {
4843 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4844 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4845 }
4846 } else {
4847 I915_WRITE(fp_reg + 4, fp);
4848 if (HAS_PIPE_CXSR(dev)) {
4849 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4850 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4851 }
4852 }
4853
4854 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4855 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4856 /* the chip adds 2 halflines automatically */
4857 adjusted_mode->crtc_vdisplay -= 1;
4858 adjusted_mode->crtc_vtotal -= 1;
4859 adjusted_mode->crtc_vblank_start -= 1;
4860 adjusted_mode->crtc_vblank_end -= 1;
4861 adjusted_mode->crtc_vsync_end -= 1;
4862 adjusted_mode->crtc_vsync_start -= 1;
4863 } else
4864 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4865
4866 I915_WRITE(HTOTAL(pipe),
4867 (adjusted_mode->crtc_hdisplay - 1) |
4868 ((adjusted_mode->crtc_htotal - 1) << 16));
4869 I915_WRITE(HBLANK(pipe),
4870 (adjusted_mode->crtc_hblank_start - 1) |
4871 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4872 I915_WRITE(HSYNC(pipe),
4873 (adjusted_mode->crtc_hsync_start - 1) |
4874 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4875
4876 I915_WRITE(VTOTAL(pipe),
4877 (adjusted_mode->crtc_vdisplay - 1) |
4878 ((adjusted_mode->crtc_vtotal - 1) << 16));
4879 I915_WRITE(VBLANK(pipe),
4880 (adjusted_mode->crtc_vblank_start - 1) |
4881 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4882 I915_WRITE(VSYNC(pipe),
4883 (adjusted_mode->crtc_vsync_start - 1) |
4884 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4885
4886 /* pipesrc and dspsize control the size that is scaled from,
4887 * which should always be the user's requested size.
4888 */
4889 if (!HAS_PCH_SPLIT(dev)) {
4890 I915_WRITE(DSPSIZE(plane),
4891 ((mode->vdisplay - 1) << 16) |
4892 (mode->hdisplay - 1));
4893 I915_WRITE(DSPPOS(plane), 0);
4894 }
4895 I915_WRITE(PIPESRC(pipe),
4896 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4897
4898 if (HAS_PCH_SPLIT(dev)) {
4899 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4900 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4901 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4902 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4903
4904 if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4905 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4906 }
4907 }
4908
4909 I915_WRITE(PIPECONF(pipe), pipeconf);
4910 POSTING_READ(PIPECONF(pipe));
4911 if (!HAS_PCH_SPLIT(dev))
4912 intel_enable_pipe(dev_priv, pipe, false);
4913
4914 intel_wait_for_vblank(dev, pipe);
4915
4916 if (IS_GEN5(dev)) {
4917 /* enable address swizzle for tiling buffer */
4918 temp = I915_READ(DISP_ARB_CTL);
4919 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
4920 }
4921
4922 I915_WRITE(DSPCNTR(plane), dspcntr);
4923 POSTING_READ(DSPCNTR(plane));
4924 if (!HAS_PCH_SPLIT(dev))
4925 intel_enable_plane(dev_priv, plane, pipe);
4926
4927 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4928
4929 intel_update_watermarks(dev);
4930
4931 drm_vblank_post_modeset(dev, pipe);
4932
4933 return ret;
4934 }
4935
4936 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4937 void intel_crtc_load_lut(struct drm_crtc *crtc)
4938 {
4939 struct drm_device *dev = crtc->dev;
4940 struct drm_i915_private *dev_priv = dev->dev_private;
4941 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4942 int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
4943 int i;
4944
4945 /* The clocks have to be on to load the palette. */
4946 if (!crtc->enabled)
4947 return;
4948
4949 /* use legacy palette for Ironlake */
4950 if (HAS_PCH_SPLIT(dev))
4951 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
4952 LGC_PALETTE_B;
4953
4954 for (i = 0; i < 256; i++) {
4955 I915_WRITE(palreg + 4 * i,
4956 (intel_crtc->lut_r[i] << 16) |
4957 (intel_crtc->lut_g[i] << 8) |
4958 intel_crtc->lut_b[i]);
4959 }
4960 }
4961
4962 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4963 {
4964 struct drm_device *dev = crtc->dev;
4965 struct drm_i915_private *dev_priv = dev->dev_private;
4966 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4967 bool visible = base != 0;
4968 u32 cntl;
4969
4970 if (intel_crtc->cursor_visible == visible)
4971 return;
4972
4973 cntl = I915_READ(CURACNTR);
4974 if (visible) {
4975 /* On these chipsets we can only modify the base whilst
4976 * the cursor is disabled.
4977 */
4978 I915_WRITE(CURABASE, base);
4979
4980 cntl &= ~(CURSOR_FORMAT_MASK);
4981 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4982 cntl |= CURSOR_ENABLE |
4983 CURSOR_GAMMA_ENABLE |
4984 CURSOR_FORMAT_ARGB;
4985 } else
4986 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4987 I915_WRITE(CURACNTR, cntl);
4988
4989 intel_crtc->cursor_visible = visible;
4990 }
4991
4992 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4993 {
4994 struct drm_device *dev = crtc->dev;
4995 struct drm_i915_private *dev_priv = dev->dev_private;
4996 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4997 int pipe = intel_crtc->pipe;
4998 bool visible = base != 0;
4999
5000 if (intel_crtc->cursor_visible != visible) {
5001 uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
5002 if (base) {
5003 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5004 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5005 cntl |= pipe << 28; /* Connect to correct pipe */
5006 } else {
5007 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5008 cntl |= CURSOR_MODE_DISABLE;
5009 }
5010 I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
5011
5012 intel_crtc->cursor_visible = visible;
5013 }
5014 /* and commit changes on next vblank */
5015 I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
5016 }
5017
5018 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5019 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5020 bool on)
5021 {
5022 struct drm_device *dev = crtc->dev;
5023 struct drm_i915_private *dev_priv = dev->dev_private;
5024 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5025 int pipe = intel_crtc->pipe;
5026 int x = intel_crtc->cursor_x;
5027 int y = intel_crtc->cursor_y;
5028 u32 base, pos;
5029 bool visible;
5030
5031 pos = 0;
5032
5033 if (on && crtc->enabled && crtc->fb) {
5034 base = intel_crtc->cursor_addr;
5035 if (x > (int) crtc->fb->width)
5036 base = 0;
5037
5038 if (y > (int) crtc->fb->height)
5039 base = 0;
5040 } else
5041 base = 0;
5042
5043 if (x < 0) {
5044 if (x + intel_crtc->cursor_width < 0)
5045 base = 0;
5046
5047 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5048 x = -x;
5049 }
5050 pos |= x << CURSOR_X_SHIFT;
5051
5052 if (y < 0) {
5053 if (y + intel_crtc->cursor_height < 0)
5054 base = 0;
5055
5056 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5057 y = -y;
5058 }
5059 pos |= y << CURSOR_Y_SHIFT;
5060
5061 visible = base != 0;
5062 if (!visible && !intel_crtc->cursor_visible)
5063 return;
5064
5065 I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
5066 if (IS_845G(dev) || IS_I865G(dev))
5067 i845_update_cursor(crtc, base);
5068 else
5069 i9xx_update_cursor(crtc, base);
5070
5071 if (visible)
5072 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
5073 }
5074
5075 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5076 struct drm_file *file,
5077 uint32_t handle,
5078 uint32_t width, uint32_t height)
5079 {
5080 struct drm_device *dev = crtc->dev;
5081 struct drm_i915_private *dev_priv = dev->dev_private;
5082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5083 struct drm_i915_gem_object *obj;
5084 uint32_t addr;
5085 int ret;
5086
5087 DRM_DEBUG_KMS("\n");
5088
5089 /* if we want to turn off the cursor ignore width and height */
5090 if (!handle) {
5091 DRM_DEBUG_KMS("cursor off\n");
5092 addr = 0;
5093 obj = NULL;
5094 mutex_lock(&dev->struct_mutex);
5095 goto finish;
5096 }
5097
5098 /* Currently we only support 64x64 cursors */
5099 if (width != 64 || height != 64) {
5100 DRM_ERROR("we currently only support 64x64 cursors\n");
5101 return -EINVAL;
5102 }
5103
5104 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
5105 if (!obj)
5106 return -ENOENT;
5107
5108 if (obj->base.size < width * height * 4) {
5109 DRM_ERROR("buffer is to small\n");
5110 ret = -ENOMEM;
5111 goto fail;
5112 }
5113
5114 /* we only need to pin inside GTT if cursor is non-phy */
5115 mutex_lock(&dev->struct_mutex);
5116 if (!dev_priv->info->cursor_needs_physical) {
5117 if (obj->tiling_mode) {
5118 DRM_ERROR("cursor cannot be tiled\n");
5119 ret = -EINVAL;
5120 goto fail_locked;
5121 }
5122
5123 ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
5124 if (ret) {
5125 DRM_ERROR("failed to pin cursor bo\n");
5126 goto fail_locked;
5127 }
5128
5129 ret = i915_gem_object_set_to_gtt_domain(obj, 0);
5130 if (ret) {
5131 DRM_ERROR("failed to move cursor bo into the GTT\n");
5132 goto fail_unpin;
5133 }
5134
5135 ret = i915_gem_object_put_fence(obj);
5136 if (ret) {
5137 DRM_ERROR("failed to move cursor bo into the GTT\n");
5138 goto fail_unpin;
5139 }
5140
5141 addr = obj->gtt_offset;
5142 } else {
5143 int align = IS_I830(dev) ? 16 * 1024 : 256;
5144 ret = i915_gem_attach_phys_object(dev, obj,
5145 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5146 align);
5147 if (ret) {
5148 DRM_ERROR("failed to attach phys object\n");
5149 goto fail_locked;
5150 }
5151 addr = obj->phys_obj->handle->busaddr;
5152 }
5153
5154 if (IS_GEN2(dev))
5155 I915_WRITE(CURSIZE, (height << 12) | width);
5156
5157 finish:
5158 if (intel_crtc->cursor_bo) {
5159 if (dev_priv->info->cursor_needs_physical) {
5160 if (intel_crtc->cursor_bo != obj)
5161 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5162 } else
5163 i915_gem_object_unpin(intel_crtc->cursor_bo);
5164 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
5165 }
5166
5167 mutex_unlock(&dev->struct_mutex);
5168
5169 intel_crtc->cursor_addr = addr;
5170 intel_crtc->cursor_bo = obj;
5171 intel_crtc->cursor_width = width;
5172 intel_crtc->cursor_height = height;
5173
5174 intel_crtc_update_cursor(crtc, true);
5175
5176 return 0;
5177 fail_unpin:
5178 i915_gem_object_unpin(obj);
5179 fail_locked:
5180 mutex_unlock(&dev->struct_mutex);
5181 fail:
5182 drm_gem_object_unreference_unlocked(&obj->base);
5183 return ret;
5184 }
5185
5186 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5187 {
5188 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5189
5190 intel_crtc->cursor_x = x;
5191 intel_crtc->cursor_y = y;
5192
5193 intel_crtc_update_cursor(crtc, true);
5194
5195 return 0;
5196 }
5197
5198 /** Sets the color ramps on behalf of RandR */
5199 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5200 u16 blue, int regno)
5201 {
5202 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5203
5204 intel_crtc->lut_r[regno] = red >> 8;
5205 intel_crtc->lut_g[regno] = green >> 8;
5206 intel_crtc->lut_b[regno] = blue >> 8;
5207 }
5208
5209 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5210 u16 *blue, int regno)
5211 {
5212 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5213
5214 *red = intel_crtc->lut_r[regno] << 8;
5215 *green = intel_crtc->lut_g[regno] << 8;
5216 *blue = intel_crtc->lut_b[regno] << 8;
5217 }
5218
5219 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
5220 u16 *blue, uint32_t start, uint32_t size)
5221 {
5222 int end = (start + size > 256) ? 256 : start + size, i;
5223 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5224
5225 for (i = start; i < end; i++) {
5226 intel_crtc->lut_r[i] = red[i] >> 8;
5227 intel_crtc->lut_g[i] = green[i] >> 8;
5228 intel_crtc->lut_b[i] = blue[i] >> 8;
5229 }
5230
5231 intel_crtc_load_lut(crtc);
5232 }
5233
5234 /**
5235 * Get a pipe with a simple mode set on it for doing load-based monitor
5236 * detection.
5237 *
5238 * It will be up to the load-detect code to adjust the pipe as appropriate for
5239 * its requirements. The pipe will be connected to no other encoders.
5240 *
5241 * Currently this code will only succeed if there is a pipe with no encoders
5242 * configured for it. In the future, it could choose to temporarily disable
5243 * some outputs to free up a pipe for its use.
5244 *
5245 * \return crtc, or NULL if no pipes are available.
5246 */
5247
5248 /* VESA 640x480x72Hz mode to set on the pipe */
5249 static struct drm_display_mode load_detect_mode = {
5250 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5251 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5252 };
5253
5254 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5255 struct drm_connector *connector,
5256 struct drm_display_mode *mode,
5257 int *dpms_mode)
5258 {
5259 struct intel_crtc *intel_crtc;
5260 struct drm_crtc *possible_crtc;
5261 struct drm_crtc *supported_crtc =NULL;
5262 struct drm_encoder *encoder = &intel_encoder->base;
5263 struct drm_crtc *crtc = NULL;
5264 struct drm_device *dev = encoder->dev;
5265 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5266 struct drm_crtc_helper_funcs *crtc_funcs;
5267 int i = -1;
5268
5269 /*
5270 * Algorithm gets a little messy:
5271 * - if the connector already has an assigned crtc, use it (but make
5272 * sure it's on first)
5273 * - try to find the first unused crtc that can drive this connector,
5274 * and use that if we find one
5275 * - if there are no unused crtcs available, try to use the first
5276 * one we found that supports the connector
5277 */
5278
5279 /* See if we already have a CRTC for this connector */
5280 if (encoder->crtc) {
5281 crtc = encoder->crtc;
5282 /* Make sure the crtc and connector are running */
5283 intel_crtc = to_intel_crtc(crtc);
5284 *dpms_mode = intel_crtc->dpms_mode;
5285 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
5286 crtc_funcs = crtc->helper_private;
5287 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
5288 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5289 }
5290 return crtc;
5291 }
5292
5293 /* Find an unused one (if possible) */
5294 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5295 i++;
5296 if (!(encoder->possible_crtcs & (1 << i)))
5297 continue;
5298 if (!possible_crtc->enabled) {
5299 crtc = possible_crtc;
5300 break;
5301 }
5302 if (!supported_crtc)
5303 supported_crtc = possible_crtc;
5304 }
5305
5306 /*
5307 * If we didn't find an unused CRTC, don't use any.
5308 */
5309 if (!crtc) {
5310 return NULL;
5311 }
5312
5313 encoder->crtc = crtc;
5314 connector->encoder = encoder;
5315 intel_encoder->load_detect_temp = true;
5316
5317 intel_crtc = to_intel_crtc(crtc);
5318 *dpms_mode = intel_crtc->dpms_mode;
5319
5320 if (!crtc->enabled) {
5321 if (!mode)
5322 mode = &load_detect_mode;
5323 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
5324 } else {
5325 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
5326 crtc_funcs = crtc->helper_private;
5327 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
5328 }
5329
5330 /* Add this connector to the crtc */
5331 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
5332 encoder_funcs->commit(encoder);
5333 }
5334 /* let the connector get through one full cycle before testing */
5335 intel_wait_for_vblank(dev, intel_crtc->pipe);
5336
5337 return crtc;
5338 }
5339
5340 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
5341 struct drm_connector *connector, int dpms_mode)
5342 {
5343 struct drm_encoder *encoder = &intel_encoder->base;
5344 struct drm_device *dev = encoder->dev;
5345 struct drm_crtc *crtc = encoder->crtc;
5346 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5347 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5348
5349 if (intel_encoder->load_detect_temp) {
5350 encoder->crtc = NULL;
5351 connector->encoder = NULL;
5352 intel_encoder->load_detect_temp = false;
5353 crtc->enabled = drm_helper_crtc_in_use(crtc);
5354 drm_helper_disable_unused_functions(dev);
5355 }
5356
5357 /* Switch crtc and encoder back off if necessary */
5358 if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
5359 if (encoder->crtc == crtc)
5360 encoder_funcs->dpms(encoder, dpms_mode);
5361 crtc_funcs->dpms(crtc, dpms_mode);
5362 }
5363 }
5364
5365 /* Returns the clock of the currently programmed mode of the given pipe. */
5366 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5367 {
5368 struct drm_i915_private *dev_priv = dev->dev_private;
5369 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5370 int pipe = intel_crtc->pipe;
5371 u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
5372 u32 fp;
5373 intel_clock_t clock;
5374
5375 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
5376 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
5377 else
5378 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
5379
5380 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
5381 if (IS_PINEVIEW(dev)) {
5382 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5383 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
5384 } else {
5385 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5386 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5387 }
5388
5389 if (!IS_GEN2(dev)) {
5390 if (IS_PINEVIEW(dev))
5391 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5392 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
5393 else
5394 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
5395 DPLL_FPA01_P1_POST_DIV_SHIFT);
5396
5397 switch (dpll & DPLL_MODE_MASK) {
5398 case DPLLB_MODE_DAC_SERIAL:
5399 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5400 5 : 10;
5401 break;
5402 case DPLLB_MODE_LVDS:
5403 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5404 7 : 14;
5405 break;
5406 default:
5407 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5408 "mode\n", (int)(dpll & DPLL_MODE_MASK));
5409 return 0;
5410 }
5411
5412 /* XXX: Handle the 100Mhz refclk */
5413 intel_clock(dev, 96000, &clock);
5414 } else {
5415 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5416
5417 if (is_lvds) {
5418 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5419 DPLL_FPA01_P1_POST_DIV_SHIFT);
5420 clock.p2 = 14;
5421
5422 if ((dpll & PLL_REF_INPUT_MASK) ==
5423 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5424 /* XXX: might not be 66MHz */
5425 intel_clock(dev, 66000, &clock);
5426 } else
5427 intel_clock(dev, 48000, &clock);
5428 } else {
5429 if (dpll & PLL_P1_DIVIDE_BY_TWO)
5430 clock.p1 = 2;
5431 else {
5432 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5433 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5434 }
5435 if (dpll & PLL_P2_DIVIDE_BY_4)
5436 clock.p2 = 4;
5437 else
5438 clock.p2 = 2;
5439
5440 intel_clock(dev, 48000, &clock);
5441 }
5442 }
5443
5444 /* XXX: It would be nice to validate the clocks, but we can't reuse
5445 * i830PllIsValid() because it relies on the xf86_config connector
5446 * configuration being accurate, which it isn't necessarily.
5447 */
5448
5449 return clock.dot;
5450 }
5451
5452 /** Returns the currently programmed mode of the given pipe. */
5453 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5454 struct drm_crtc *crtc)
5455 {
5456 struct drm_i915_private *dev_priv = dev->dev_private;
5457 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5458 int pipe = intel_crtc->pipe;
5459 struct drm_display_mode *mode;
5460 int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
5461 int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
5462 int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
5463 int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
5464
5465 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5466 if (!mode)
5467 return NULL;
5468
5469 mode->clock = intel_crtc_clock_get(dev, crtc);
5470 mode->hdisplay = (htot & 0xffff) + 1;
5471 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5472 mode->hsync_start = (hsync & 0xffff) + 1;
5473 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5474 mode->vdisplay = (vtot & 0xffff) + 1;
5475 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5476 mode->vsync_start = (vsync & 0xffff) + 1;
5477 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5478
5479 drm_mode_set_name(mode);
5480 drm_mode_set_crtcinfo(mode, 0);
5481
5482 return mode;
5483 }
5484
5485 #define GPU_IDLE_TIMEOUT 500 /* ms */
5486
5487 /* When this timer fires, we've been idle for awhile */
5488 static void intel_gpu_idle_timer(unsigned long arg)
5489 {
5490 struct drm_device *dev = (struct drm_device *)arg;
5491 drm_i915_private_t *dev_priv = dev->dev_private;
5492
5493 if (!list_empty(&dev_priv->mm.active_list)) {
5494 /* Still processing requests, so just re-arm the timer. */
5495 mod_timer(&dev_priv->idle_timer, jiffies +
5496 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5497 return;
5498 }
5499
5500 dev_priv->busy = false;
5501 queue_work(dev_priv->wq, &dev_priv->idle_work);
5502 }
5503
5504 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
5505
5506 static void intel_crtc_idle_timer(unsigned long arg)
5507 {
5508 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
5509 struct drm_crtc *crtc = &intel_crtc->base;
5510 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
5511 struct intel_framebuffer *intel_fb;
5512
5513 intel_fb = to_intel_framebuffer(crtc->fb);
5514 if (intel_fb && intel_fb->obj->active) {
5515 /* The framebuffer is still being accessed by the GPU. */
5516 mod_timer(&intel_crtc->idle_timer, jiffies +
5517 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5518 return;
5519 }
5520
5521 intel_crtc->busy = false;
5522 queue_work(dev_priv->wq, &dev_priv->idle_work);
5523 }
5524
5525 static void intel_increase_pllclock(struct drm_crtc *crtc)
5526 {
5527 struct drm_device *dev = crtc->dev;
5528 drm_i915_private_t *dev_priv = dev->dev_private;
5529 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5530 int pipe = intel_crtc->pipe;
5531 int dpll_reg = DPLL(pipe);
5532 int dpll;
5533
5534 if (HAS_PCH_SPLIT(dev))
5535 return;
5536
5537 if (!dev_priv->lvds_downclock_avail)
5538 return;
5539
5540 dpll = I915_READ(dpll_reg);
5541 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
5542 DRM_DEBUG_DRIVER("upclocking LVDS\n");
5543
5544 /* Unlock panel regs */
5545 I915_WRITE(PP_CONTROL,
5546 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
5547
5548 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5549 I915_WRITE(dpll_reg, dpll);
5550 POSTING_READ(dpll_reg);
5551 intel_wait_for_vblank(dev, pipe);
5552
5553 dpll = I915_READ(dpll_reg);
5554 if (dpll & DISPLAY_RATE_SELECT_FPA1)
5555 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
5556
5557 /* ...and lock them again */
5558 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
5559 }
5560
5561 /* Schedule downclock */
5562 mod_timer(&intel_crtc->idle_timer, jiffies +
5563 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5564 }
5565
5566 static void intel_decrease_pllclock(struct drm_crtc *crtc)
5567 {
5568 struct drm_device *dev = crtc->dev;
5569 drm_i915_private_t *dev_priv = dev->dev_private;
5570 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5571 int pipe = intel_crtc->pipe;
5572 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
5573 int dpll = I915_READ(dpll_reg);
5574
5575 if (HAS_PCH_SPLIT(dev))
5576 return;
5577
5578 if (!dev_priv->lvds_downclock_avail)
5579 return;
5580
5581 /*
5582 * Since this is called by a timer, we should never get here in
5583 * the manual case.
5584 */
5585 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
5586 DRM_DEBUG_DRIVER("downclocking LVDS\n");
5587
5588 /* Unlock panel regs */
5589 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
5590 PANEL_UNLOCK_REGS);
5591
5592 dpll |= DISPLAY_RATE_SELECT_FPA1;
5593 I915_WRITE(dpll_reg, dpll);
5594 dpll = I915_READ(dpll_reg);
5595 intel_wait_for_vblank(dev, pipe);
5596 dpll = I915_READ(dpll_reg);
5597 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
5598 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
5599
5600 /* ...and lock them again */
5601 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
5602 }
5603
5604 }
5605
5606 /**
5607 * intel_idle_update - adjust clocks for idleness
5608 * @work: work struct
5609 *
5610 * Either the GPU or display (or both) went idle. Check the busy status
5611 * here and adjust the CRTC and GPU clocks as necessary.
5612 */
5613 static void intel_idle_update(struct work_struct *work)
5614 {
5615 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
5616 idle_work);
5617 struct drm_device *dev = dev_priv->dev;
5618 struct drm_crtc *crtc;
5619 struct intel_crtc *intel_crtc;
5620
5621 if (!i915_powersave)
5622 return;
5623
5624 mutex_lock(&dev->struct_mutex);
5625
5626 i915_update_gfx_val(dev_priv);
5627
5628 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5629 /* Skip inactive CRTCs */
5630 if (!crtc->fb)
5631 continue;
5632
5633 intel_crtc = to_intel_crtc(crtc);
5634 if (!intel_crtc->busy)
5635 intel_decrease_pllclock(crtc);
5636 }
5637
5638
5639 mutex_unlock(&dev->struct_mutex);
5640 }
5641
5642 /**
5643 * intel_mark_busy - mark the GPU and possibly the display busy
5644 * @dev: drm device
5645 * @obj: object we're operating on
5646 *
5647 * Callers can use this function to indicate that the GPU is busy processing
5648 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
5649 * buffer), we'll also mark the display as busy, so we know to increase its
5650 * clock frequency.
5651 */
5652 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
5653 {
5654 drm_i915_private_t *dev_priv = dev->dev_private;
5655 struct drm_crtc *crtc = NULL;
5656 struct intel_framebuffer *intel_fb;
5657 struct intel_crtc *intel_crtc;
5658
5659 if (!drm_core_check_feature(dev, DRIVER_MODESET))
5660 return;
5661
5662 if (!dev_priv->busy)
5663 dev_priv->busy = true;
5664 else
5665 mod_timer(&dev_priv->idle_timer, jiffies +
5666 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5667
5668 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5669 if (!crtc->fb)
5670 continue;
5671
5672 intel_crtc = to_intel_crtc(crtc);
5673 intel_fb = to_intel_framebuffer(crtc->fb);
5674 if (intel_fb->obj == obj) {
5675 if (!intel_crtc->busy) {
5676 /* Non-busy -> busy, upclock */
5677 intel_increase_pllclock(crtc);
5678 intel_crtc->busy = true;
5679 } else {
5680 /* Busy -> busy, put off timer */
5681 mod_timer(&intel_crtc->idle_timer, jiffies +
5682 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5683 }
5684 }
5685 }
5686 }
5687
5688 static void intel_crtc_destroy(struct drm_crtc *crtc)
5689 {
5690 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5691 struct drm_device *dev = crtc->dev;
5692 struct intel_unpin_work *work;
5693 unsigned long flags;
5694
5695 spin_lock_irqsave(&dev->event_lock, flags);
5696 work = intel_crtc->unpin_work;
5697 intel_crtc->unpin_work = NULL;
5698 spin_unlock_irqrestore(&dev->event_lock, flags);
5699
5700 if (work) {
5701 cancel_work_sync(&work->work);
5702 kfree(work);
5703 }
5704
5705 drm_crtc_cleanup(crtc);
5706
5707 kfree(intel_crtc);
5708 }
5709
5710 static void intel_unpin_work_fn(struct work_struct *__work)
5711 {
5712 struct intel_unpin_work *work =
5713 container_of(__work, struct intel_unpin_work, work);
5714
5715 mutex_lock(&work->dev->struct_mutex);
5716 i915_gem_object_unpin(work->old_fb_obj);
5717 drm_gem_object_unreference(&work->pending_flip_obj->base);
5718 drm_gem_object_unreference(&work->old_fb_obj->base);
5719
5720 mutex_unlock(&work->dev->struct_mutex);
5721 kfree(work);
5722 }
5723
5724 static void do_intel_finish_page_flip(struct drm_device *dev,
5725 struct drm_crtc *crtc)
5726 {
5727 drm_i915_private_t *dev_priv = dev->dev_private;
5728 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5729 struct intel_unpin_work *work;
5730 struct drm_i915_gem_object *obj;
5731 struct drm_pending_vblank_event *e;
5732 struct timeval tnow, tvbl;
5733 unsigned long flags;
5734
5735 /* Ignore early vblank irqs */
5736 if (intel_crtc == NULL)
5737 return;
5738
5739 do_gettimeofday(&tnow);
5740
5741 spin_lock_irqsave(&dev->event_lock, flags);
5742 work = intel_crtc->unpin_work;
5743 if (work == NULL || !work->pending) {
5744 spin_unlock_irqrestore(&dev->event_lock, flags);
5745 return;
5746 }
5747
5748 intel_crtc->unpin_work = NULL;
5749
5750 if (work->event) {
5751 e = work->event;
5752 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
5753
5754 /* Called before vblank count and timestamps have
5755 * been updated for the vblank interval of flip
5756 * completion? Need to increment vblank count and
5757 * add one videorefresh duration to returned timestamp
5758 * to account for this. We assume this happened if we
5759 * get called over 0.9 frame durations after the last
5760 * timestamped vblank.
5761 *
5762 * This calculation can not be used with vrefresh rates
5763 * below 5Hz (10Hz to be on the safe side) without
5764 * promoting to 64 integers.
5765 */
5766 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
5767 9 * crtc->framedur_ns) {
5768 e->event.sequence++;
5769 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
5770 crtc->framedur_ns);
5771 }
5772
5773 e->event.tv_sec = tvbl.tv_sec;
5774 e->event.tv_usec = tvbl.tv_usec;
5775
5776 list_add_tail(&e->base.link,
5777 &e->base.file_priv->event_list);
5778 wake_up_interruptible(&e->base.file_priv->event_wait);
5779 }
5780
5781 drm_vblank_put(dev, intel_crtc->pipe);
5782
5783 spin_unlock_irqrestore(&dev->event_lock, flags);
5784
5785 obj = work->old_fb_obj;
5786
5787 atomic_clear_mask(1 << intel_crtc->plane,
5788 &obj->pending_flip.counter);
5789 if (atomic_read(&obj->pending_flip) == 0)
5790 wake_up(&dev_priv->pending_flip_queue);
5791
5792 schedule_work(&work->work);
5793
5794 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
5795 }
5796
5797 void intel_finish_page_flip(struct drm_device *dev, int pipe)
5798 {
5799 drm_i915_private_t *dev_priv = dev->dev_private;
5800 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
5801
5802 do_intel_finish_page_flip(dev, crtc);
5803 }
5804
5805 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5806 {
5807 drm_i915_private_t *dev_priv = dev->dev_private;
5808 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5809
5810 do_intel_finish_page_flip(dev, crtc);
5811 }
5812
5813 void intel_prepare_page_flip(struct drm_device *dev, int plane)
5814 {
5815 drm_i915_private_t *dev_priv = dev->dev_private;
5816 struct intel_crtc *intel_crtc =
5817 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5818 unsigned long flags;
5819
5820 spin_lock_irqsave(&dev->event_lock, flags);
5821 if (intel_crtc->unpin_work) {
5822 if ((++intel_crtc->unpin_work->pending) > 1)
5823 DRM_ERROR("Prepared flip multiple times\n");
5824 } else {
5825 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5826 }
5827 spin_unlock_irqrestore(&dev->event_lock, flags);
5828 }
5829
5830 static int intel_crtc_page_flip(struct drm_crtc *crtc,
5831 struct drm_framebuffer *fb,
5832 struct drm_pending_vblank_event *event)
5833 {
5834 struct drm_device *dev = crtc->dev;
5835 struct drm_i915_private *dev_priv = dev->dev_private;
5836 struct intel_framebuffer *intel_fb;
5837 struct drm_i915_gem_object *obj;
5838 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5839 struct intel_unpin_work *work;
5840 unsigned long flags, offset;
5841 int pipe = intel_crtc->pipe;
5842 u32 pf, pipesrc;
5843 int ret;
5844
5845 work = kzalloc(sizeof *work, GFP_KERNEL);
5846 if (work == NULL)
5847 return -ENOMEM;
5848
5849 work->event = event;
5850 work->dev = crtc->dev;
5851 intel_fb = to_intel_framebuffer(crtc->fb);
5852 work->old_fb_obj = intel_fb->obj;
5853 INIT_WORK(&work->work, intel_unpin_work_fn);
5854
5855 /* We borrow the event spin lock for protecting unpin_work */
5856 spin_lock_irqsave(&dev->event_lock, flags);
5857 if (intel_crtc->unpin_work) {
5858 spin_unlock_irqrestore(&dev->event_lock, flags);
5859 kfree(work);
5860
5861 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5862 return -EBUSY;
5863 }
5864 intel_crtc->unpin_work = work;
5865 spin_unlock_irqrestore(&dev->event_lock, flags);
5866
5867 intel_fb = to_intel_framebuffer(fb);
5868 obj = intel_fb->obj;
5869
5870 mutex_lock(&dev->struct_mutex);
5871 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
5872 if (ret)
5873 goto cleanup_work;
5874
5875 /* Reference the objects for the scheduled work. */
5876 drm_gem_object_reference(&work->old_fb_obj->base);
5877 drm_gem_object_reference(&obj->base);
5878
5879 crtc->fb = fb;
5880
5881 ret = drm_vblank_get(dev, intel_crtc->pipe);
5882 if (ret)
5883 goto cleanup_objs;
5884
5885 if (IS_GEN3(dev) || IS_GEN2(dev)) {
5886 u32 flip_mask;
5887
5888 /* Can't queue multiple flips, so wait for the previous
5889 * one to finish before executing the next.
5890 */
5891 ret = BEGIN_LP_RING(2);
5892 if (ret)
5893 goto cleanup_objs;
5894
5895 if (intel_crtc->plane)
5896 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5897 else
5898 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5899 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5900 OUT_RING(MI_NOOP);
5901 ADVANCE_LP_RING();
5902 }
5903
5904 work->pending_flip_obj = obj;
5905
5906 work->enable_stall_check = true;
5907
5908 /* Offset into the new buffer for cases of shared fbs between CRTCs */
5909 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
5910
5911 ret = BEGIN_LP_RING(4);
5912 if (ret)
5913 goto cleanup_objs;
5914
5915 /* Block clients from rendering to the new back buffer until
5916 * the flip occurs and the object is no longer visible.
5917 */
5918 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
5919
5920 switch (INTEL_INFO(dev)->gen) {
5921 case 2:
5922 OUT_RING(MI_DISPLAY_FLIP |
5923 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5924 OUT_RING(fb->pitch);
5925 OUT_RING(obj->gtt_offset + offset);
5926 OUT_RING(MI_NOOP);
5927 break;
5928
5929 case 3:
5930 OUT_RING(MI_DISPLAY_FLIP_I915 |
5931 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5932 OUT_RING(fb->pitch);
5933 OUT_RING(obj->gtt_offset + offset);
5934 OUT_RING(MI_NOOP);
5935 break;
5936
5937 case 4:
5938 case 5:
5939 /* i965+ uses the linear or tiled offsets from the
5940 * Display Registers (which do not change across a page-flip)
5941 * so we need only reprogram the base address.
5942 */
5943 OUT_RING(MI_DISPLAY_FLIP |
5944 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5945 OUT_RING(fb->pitch);
5946 OUT_RING(obj->gtt_offset | obj->tiling_mode);
5947
5948 /* XXX Enabling the panel-fitter across page-flip is so far
5949 * untested on non-native modes, so ignore it for now.
5950 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5951 */
5952 pf = 0;
5953 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5954 OUT_RING(pf | pipesrc);
5955 break;
5956
5957 case 6:
5958 OUT_RING(MI_DISPLAY_FLIP |
5959 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5960 OUT_RING(fb->pitch | obj->tiling_mode);
5961 OUT_RING(obj->gtt_offset);
5962
5963 pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5964 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5965 OUT_RING(pf | pipesrc);
5966 break;
5967 }
5968 ADVANCE_LP_RING();
5969
5970 mutex_unlock(&dev->struct_mutex);
5971
5972 trace_i915_flip_request(intel_crtc->plane, obj);
5973
5974 return 0;
5975
5976 cleanup_objs:
5977 drm_gem_object_unreference(&work->old_fb_obj->base);
5978 drm_gem_object_unreference(&obj->base);
5979 cleanup_work:
5980 mutex_unlock(&dev->struct_mutex);
5981
5982 spin_lock_irqsave(&dev->event_lock, flags);
5983 intel_crtc->unpin_work = NULL;
5984 spin_unlock_irqrestore(&dev->event_lock, flags);
5985
5986 kfree(work);
5987
5988 return ret;
5989 }
5990
5991 static struct drm_crtc_helper_funcs intel_helper_funcs = {
5992 .dpms = intel_crtc_dpms,
5993 .mode_fixup = intel_crtc_mode_fixup,
5994 .mode_set = intel_crtc_mode_set,
5995 .mode_set_base = intel_pipe_set_base,
5996 .mode_set_base_atomic = intel_pipe_set_base_atomic,
5997 .load_lut = intel_crtc_load_lut,
5998 .disable = intel_crtc_disable,
5999 };
6000
6001 static const struct drm_crtc_funcs intel_crtc_funcs = {
6002 .cursor_set = intel_crtc_cursor_set,
6003 .cursor_move = intel_crtc_cursor_move,
6004 .gamma_set = intel_crtc_gamma_set,
6005 .set_config = drm_crtc_helper_set_config,
6006 .destroy = intel_crtc_destroy,
6007 .page_flip = intel_crtc_page_flip,
6008 };
6009
6010 static void intel_sanitize_modesetting(struct drm_device *dev,
6011 int pipe, int plane)
6012 {
6013 struct drm_i915_private *dev_priv = dev->dev_private;
6014 u32 reg, val;
6015
6016 if (HAS_PCH_SPLIT(dev))
6017 return;
6018
6019 /* Who knows what state these registers were left in by the BIOS or
6020 * grub?
6021 *
6022 * If we leave the registers in a conflicting state (e.g. with the
6023 * display plane reading from the other pipe than the one we intend
6024 * to use) then when we attempt to teardown the active mode, we will
6025 * not disable the pipes and planes in the correct order -- leaving
6026 * a plane reading from a disabled pipe and possibly leading to
6027 * undefined behaviour.
6028 */
6029
6030 reg = DSPCNTR(plane);
6031 val = I915_READ(reg);
6032
6033 if ((val & DISPLAY_PLANE_ENABLE) == 0)
6034 return;
6035 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6036 return;
6037
6038 /* This display plane is active and attached to the other CPU pipe. */
6039 pipe = !pipe;
6040
6041 /* Disable the plane and wait for it to stop reading from the pipe. */
6042 intel_disable_plane(dev_priv, plane, pipe);
6043 intel_disable_pipe(dev_priv, pipe);
6044 }
6045
6046 static void intel_crtc_init(struct drm_device *dev, int pipe)
6047 {
6048 drm_i915_private_t *dev_priv = dev->dev_private;
6049 struct intel_crtc *intel_crtc;
6050 int i;
6051
6052 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6053 if (intel_crtc == NULL)
6054 return;
6055
6056 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6057
6058 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
6059 for (i = 0; i < 256; i++) {
6060 intel_crtc->lut_r[i] = i;
6061 intel_crtc->lut_g[i] = i;
6062 intel_crtc->lut_b[i] = i;
6063 }
6064
6065 /* Swap pipes & planes for FBC on pre-965 */
6066 intel_crtc->pipe = pipe;
6067 intel_crtc->plane = pipe;
6068 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
6069 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
6070 intel_crtc->plane = !pipe;
6071 }
6072
6073 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6074 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6075 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6076 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6077
6078 intel_crtc->cursor_addr = 0;
6079 intel_crtc->dpms_mode = -1;
6080 intel_crtc->active = true; /* force the pipe off on setup_init_config */
6081
6082 if (HAS_PCH_SPLIT(dev)) {
6083 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6084 intel_helper_funcs.commit = ironlake_crtc_commit;
6085 } else {
6086 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6087 intel_helper_funcs.commit = i9xx_crtc_commit;
6088 }
6089
6090 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6091
6092 intel_crtc->busy = false;
6093
6094 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6095 (unsigned long)intel_crtc);
6096
6097 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6098 }
6099
6100 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
6101 struct drm_file *file)
6102 {
6103 drm_i915_private_t *dev_priv = dev->dev_private;
6104 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
6105 struct drm_mode_object *drmmode_obj;
6106 struct intel_crtc *crtc;
6107
6108 if (!dev_priv) {
6109 DRM_ERROR("called with no initialization\n");
6110 return -EINVAL;
6111 }
6112
6113 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6114 DRM_MODE_OBJECT_CRTC);
6115
6116 if (!drmmode_obj) {
6117 DRM_ERROR("no such CRTC id\n");
6118 return -EINVAL;
6119 }
6120
6121 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6122 pipe_from_crtc_id->pipe = crtc->pipe;
6123
6124 return 0;
6125 }
6126
6127 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
6128 {
6129 struct intel_encoder *encoder;
6130 int index_mask = 0;
6131 int entry = 0;
6132
6133 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6134 if (type_mask & encoder->clone_mask)
6135 index_mask |= (1 << entry);
6136 entry++;
6137 }
6138
6139 return index_mask;
6140 }
6141
6142 static bool has_edp_a(struct drm_device *dev)
6143 {
6144 struct drm_i915_private *dev_priv = dev->dev_private;
6145
6146 if (!IS_MOBILE(dev))
6147 return false;
6148
6149 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6150 return false;
6151
6152 if (IS_GEN5(dev) &&
6153 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6154 return false;
6155
6156 return true;
6157 }
6158
6159 static void intel_setup_outputs(struct drm_device *dev)
6160 {
6161 struct drm_i915_private *dev_priv = dev->dev_private;
6162 struct intel_encoder *encoder;
6163 bool dpd_is_edp = false;
6164 bool has_lvds = false;
6165
6166 if (IS_MOBILE(dev) && !IS_I830(dev))
6167 has_lvds = intel_lvds_init(dev);
6168 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6169 /* disable the panel fitter on everything but LVDS */
6170 I915_WRITE(PFIT_CONTROL, 0);
6171 }
6172
6173 if (HAS_PCH_SPLIT(dev)) {
6174 dpd_is_edp = intel_dpd_is_edp(dev);
6175
6176 if (has_edp_a(dev))
6177 intel_dp_init(dev, DP_A);
6178
6179 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6180 intel_dp_init(dev, PCH_DP_D);
6181 }
6182
6183 intel_crt_init(dev);
6184
6185 if (HAS_PCH_SPLIT(dev)) {
6186 int found;
6187
6188 if (I915_READ(HDMIB) & PORT_DETECTED) {
6189 /* PCH SDVOB multiplex with HDMIB */
6190 found = intel_sdvo_init(dev, PCH_SDVOB);
6191 if (!found)
6192 intel_hdmi_init(dev, HDMIB);
6193 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6194 intel_dp_init(dev, PCH_DP_B);
6195 }
6196
6197 if (I915_READ(HDMIC) & PORT_DETECTED)
6198 intel_hdmi_init(dev, HDMIC);
6199
6200 if (I915_READ(HDMID) & PORT_DETECTED)
6201 intel_hdmi_init(dev, HDMID);
6202
6203 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6204 intel_dp_init(dev, PCH_DP_C);
6205
6206 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6207 intel_dp_init(dev, PCH_DP_D);
6208
6209 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
6210 bool found = false;
6211
6212 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6213 DRM_DEBUG_KMS("probing SDVOB\n");
6214 found = intel_sdvo_init(dev, SDVOB);
6215 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6216 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
6217 intel_hdmi_init(dev, SDVOB);
6218 }
6219
6220 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6221 DRM_DEBUG_KMS("probing DP_B\n");
6222 intel_dp_init(dev, DP_B);
6223 }
6224 }
6225
6226 /* Before G4X SDVOC doesn't have its own detect register */
6227
6228 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6229 DRM_DEBUG_KMS("probing SDVOC\n");
6230 found = intel_sdvo_init(dev, SDVOC);
6231 }
6232
6233 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6234
6235 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6236 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
6237 intel_hdmi_init(dev, SDVOC);
6238 }
6239 if (SUPPORTS_INTEGRATED_DP(dev)) {
6240 DRM_DEBUG_KMS("probing DP_C\n");
6241 intel_dp_init(dev, DP_C);
6242 }
6243 }
6244
6245 if (SUPPORTS_INTEGRATED_DP(dev) &&
6246 (I915_READ(DP_D) & DP_DETECTED)) {
6247 DRM_DEBUG_KMS("probing DP_D\n");
6248 intel_dp_init(dev, DP_D);
6249 }
6250 } else if (IS_GEN2(dev))
6251 intel_dvo_init(dev);
6252
6253 if (SUPPORTS_TV(dev))
6254 intel_tv_init(dev);
6255
6256 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6257 encoder->base.possible_crtcs = encoder->crtc_mask;
6258 encoder->base.possible_clones =
6259 intel_encoder_clones(dev, encoder->clone_mask);
6260 }
6261
6262 intel_panel_setup_backlight(dev);
6263 }
6264
6265 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6266 {
6267 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6268
6269 drm_framebuffer_cleanup(fb);
6270 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
6271
6272 kfree(intel_fb);
6273 }
6274
6275 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
6276 struct drm_file *file,
6277 unsigned int *handle)
6278 {
6279 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6280 struct drm_i915_gem_object *obj = intel_fb->obj;
6281
6282 return drm_gem_handle_create(file, &obj->base, handle);
6283 }
6284
6285 static const struct drm_framebuffer_funcs intel_fb_funcs = {
6286 .destroy = intel_user_framebuffer_destroy,
6287 .create_handle = intel_user_framebuffer_create_handle,
6288 };
6289
6290 int intel_framebuffer_init(struct drm_device *dev,
6291 struct intel_framebuffer *intel_fb,
6292 struct drm_mode_fb_cmd *mode_cmd,
6293 struct drm_i915_gem_object *obj)
6294 {
6295 int ret;
6296
6297 if (obj->tiling_mode == I915_TILING_Y)
6298 return -EINVAL;
6299
6300 if (mode_cmd->pitch & 63)
6301 return -EINVAL;
6302
6303 switch (mode_cmd->bpp) {
6304 case 8:
6305 case 16:
6306 case 24:
6307 case 32:
6308 break;
6309 default:
6310 return -EINVAL;
6311 }
6312
6313 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6314 if (ret) {
6315 DRM_ERROR("framebuffer init failed %d\n", ret);
6316 return ret;
6317 }
6318
6319 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
6320 intel_fb->obj = obj;
6321 return 0;
6322 }
6323
6324 static struct drm_framebuffer *
6325 intel_user_framebuffer_create(struct drm_device *dev,
6326 struct drm_file *filp,
6327 struct drm_mode_fb_cmd *mode_cmd)
6328 {
6329 struct drm_i915_gem_object *obj;
6330 struct intel_framebuffer *intel_fb;
6331 int ret;
6332
6333 obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
6334 if (!obj)
6335 return ERR_PTR(-ENOENT);
6336
6337 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6338 if (!intel_fb)
6339 return ERR_PTR(-ENOMEM);
6340
6341 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6342 if (ret) {
6343 drm_gem_object_unreference_unlocked(&obj->base);
6344 kfree(intel_fb);
6345 return ERR_PTR(ret);
6346 }
6347
6348 return &intel_fb->base;
6349 }
6350
6351 static const struct drm_mode_config_funcs intel_mode_funcs = {
6352 .fb_create = intel_user_framebuffer_create,
6353 .output_poll_changed = intel_fb_output_poll_changed,
6354 };
6355
6356 static struct drm_i915_gem_object *
6357 intel_alloc_context_page(struct drm_device *dev)
6358 {
6359 struct drm_i915_gem_object *ctx;
6360 int ret;
6361
6362 ctx = i915_gem_alloc_object(dev, 4096);
6363 if (!ctx) {
6364 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
6365 return NULL;
6366 }
6367
6368 mutex_lock(&dev->struct_mutex);
6369 ret = i915_gem_object_pin(ctx, 4096, true);
6370 if (ret) {
6371 DRM_ERROR("failed to pin power context: %d\n", ret);
6372 goto err_unref;
6373 }
6374
6375 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
6376 if (ret) {
6377 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
6378 goto err_unpin;
6379 }
6380 mutex_unlock(&dev->struct_mutex);
6381
6382 return ctx;
6383
6384 err_unpin:
6385 i915_gem_object_unpin(ctx);
6386 err_unref:
6387 drm_gem_object_unreference(&ctx->base);
6388 mutex_unlock(&dev->struct_mutex);
6389 return NULL;
6390 }
6391
6392 bool ironlake_set_drps(struct drm_device *dev, u8 val)
6393 {
6394 struct drm_i915_private *dev_priv = dev->dev_private;
6395 u16 rgvswctl;
6396
6397 rgvswctl = I915_READ16(MEMSWCTL);
6398 if (rgvswctl & MEMCTL_CMD_STS) {
6399 DRM_DEBUG("gpu busy, RCS change rejected\n");
6400 return false; /* still busy with another command */
6401 }
6402
6403 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
6404 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
6405 I915_WRITE16(MEMSWCTL, rgvswctl);
6406 POSTING_READ16(MEMSWCTL);
6407
6408 rgvswctl |= MEMCTL_CMD_STS;
6409 I915_WRITE16(MEMSWCTL, rgvswctl);
6410
6411 return true;
6412 }
6413
6414 void ironlake_enable_drps(struct drm_device *dev)
6415 {
6416 struct drm_i915_private *dev_priv = dev->dev_private;
6417 u32 rgvmodectl = I915_READ(MEMMODECTL);
6418 u8 fmax, fmin, fstart, vstart;
6419
6420 /* Enable temp reporting */
6421 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
6422 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
6423
6424 /* 100ms RC evaluation intervals */
6425 I915_WRITE(RCUPEI, 100000);
6426 I915_WRITE(RCDNEI, 100000);
6427
6428 /* Set max/min thresholds to 90ms and 80ms respectively */
6429 I915_WRITE(RCBMAXAVG, 90000);
6430 I915_WRITE(RCBMINAVG, 80000);
6431
6432 I915_WRITE(MEMIHYST, 1);
6433
6434 /* Set up min, max, and cur for interrupt handling */
6435 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
6436 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
6437 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
6438 MEMMODE_FSTART_SHIFT;
6439
6440 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
6441 PXVFREQ_PX_SHIFT;
6442
6443 dev_priv->fmax = fmax; /* IPS callback will increase this */
6444 dev_priv->fstart = fstart;
6445
6446 dev_priv->max_delay = fstart;
6447 dev_priv->min_delay = fmin;
6448 dev_priv->cur_delay = fstart;
6449
6450 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
6451 fmax, fmin, fstart);
6452
6453 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
6454
6455 /*
6456 * Interrupts will be enabled in ironlake_irq_postinstall
6457 */
6458
6459 I915_WRITE(VIDSTART, vstart);
6460 POSTING_READ(VIDSTART);
6461
6462 rgvmodectl |= MEMMODE_SWMODE_EN;
6463 I915_WRITE(MEMMODECTL, rgvmodectl);
6464
6465 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
6466 DRM_ERROR("stuck trying to change perf mode\n");
6467 msleep(1);
6468
6469 ironlake_set_drps(dev, fstart);
6470
6471 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
6472 I915_READ(0x112e0);
6473 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
6474 dev_priv->last_count2 = I915_READ(0x112f4);
6475 getrawmonotonic(&dev_priv->last_time2);
6476 }
6477
6478 void ironlake_disable_drps(struct drm_device *dev)
6479 {
6480 struct drm_i915_private *dev_priv = dev->dev_private;
6481 u16 rgvswctl = I915_READ16(MEMSWCTL);
6482
6483 /* Ack interrupts, disable EFC interrupt */
6484 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
6485 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
6486 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
6487 I915_WRITE(DEIIR, DE_PCU_EVENT);
6488 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
6489
6490 /* Go back to the starting frequency */
6491 ironlake_set_drps(dev, dev_priv->fstart);
6492 msleep(1);
6493 rgvswctl |= MEMCTL_CMD_STS;
6494 I915_WRITE(MEMSWCTL, rgvswctl);
6495 msleep(1);
6496
6497 }
6498
6499 void gen6_set_rps(struct drm_device *dev, u8 val)
6500 {
6501 struct drm_i915_private *dev_priv = dev->dev_private;
6502 u32 swreq;
6503
6504 swreq = (val & 0x3ff) << 25;
6505 I915_WRITE(GEN6_RPNSWREQ, swreq);
6506 }
6507
6508 void gen6_disable_rps(struct drm_device *dev)
6509 {
6510 struct drm_i915_private *dev_priv = dev->dev_private;
6511
6512 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
6513 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
6514 I915_WRITE(GEN6_PMIER, 0);
6515 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
6516 }
6517
6518 static unsigned long intel_pxfreq(u32 vidfreq)
6519 {
6520 unsigned long freq;
6521 int div = (vidfreq & 0x3f0000) >> 16;
6522 int post = (vidfreq & 0x3000) >> 12;
6523 int pre = (vidfreq & 0x7);
6524
6525 if (!pre)
6526 return 0;
6527
6528 freq = ((div * 133333) / ((1<<post) * pre));
6529
6530 return freq;
6531 }
6532
6533 void intel_init_emon(struct drm_device *dev)
6534 {
6535 struct drm_i915_private *dev_priv = dev->dev_private;
6536 u32 lcfuse;
6537 u8 pxw[16];
6538 int i;
6539
6540 /* Disable to program */
6541 I915_WRITE(ECR, 0);
6542 POSTING_READ(ECR);
6543
6544 /* Program energy weights for various events */
6545 I915_WRITE(SDEW, 0x15040d00);
6546 I915_WRITE(CSIEW0, 0x007f0000);
6547 I915_WRITE(CSIEW1, 0x1e220004);
6548 I915_WRITE(CSIEW2, 0x04000004);
6549
6550 for (i = 0; i < 5; i++)
6551 I915_WRITE(PEW + (i * 4), 0);
6552 for (i = 0; i < 3; i++)
6553 I915_WRITE(DEW + (i * 4), 0);
6554
6555 /* Program P-state weights to account for frequency power adjustment */
6556 for (i = 0; i < 16; i++) {
6557 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
6558 unsigned long freq = intel_pxfreq(pxvidfreq);
6559 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6560 PXVFREQ_PX_SHIFT;
6561 unsigned long val;
6562
6563 val = vid * vid;
6564 val *= (freq / 1000);
6565 val *= 255;
6566 val /= (127*127*900);
6567 if (val > 0xff)
6568 DRM_ERROR("bad pxval: %ld\n", val);
6569 pxw[i] = val;
6570 }
6571 /* Render standby states get 0 weight */
6572 pxw[14] = 0;
6573 pxw[15] = 0;
6574
6575 for (i = 0; i < 4; i++) {
6576 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6577 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6578 I915_WRITE(PXW + (i * 4), val);
6579 }
6580
6581 /* Adjust magic regs to magic values (more experimental results) */
6582 I915_WRITE(OGW0, 0);
6583 I915_WRITE(OGW1, 0);
6584 I915_WRITE(EG0, 0x00007f00);
6585 I915_WRITE(EG1, 0x0000000e);
6586 I915_WRITE(EG2, 0x000e0000);
6587 I915_WRITE(EG3, 0x68000300);
6588 I915_WRITE(EG4, 0x42000000);
6589 I915_WRITE(EG5, 0x00140031);
6590 I915_WRITE(EG6, 0);
6591 I915_WRITE(EG7, 0);
6592
6593 for (i = 0; i < 8; i++)
6594 I915_WRITE(PXWL + (i * 4), 0);
6595
6596 /* Enable PMON + select events */
6597 I915_WRITE(ECR, 0x80000019);
6598
6599 lcfuse = I915_READ(LCFUSE02);
6600
6601 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
6602 }
6603
6604 void gen6_enable_rps(struct drm_i915_private *dev_priv)
6605 {
6606 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
6607 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
6608 u32 pcu_mbox;
6609 int cur_freq, min_freq, max_freq;
6610 int i;
6611
6612 /* Here begins a magic sequence of register writes to enable
6613 * auto-downclocking.
6614 *
6615 * Perhaps there might be some value in exposing these to
6616 * userspace...
6617 */
6618 I915_WRITE(GEN6_RC_STATE, 0);
6619 __gen6_force_wake_get(dev_priv);
6620
6621 /* disable the counters and set deterministic thresholds */
6622 I915_WRITE(GEN6_RC_CONTROL, 0);
6623
6624 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
6625 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
6626 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
6627 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6628 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6629
6630 for (i = 0; i < I915_NUM_RINGS; i++)
6631 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
6632
6633 I915_WRITE(GEN6_RC_SLEEP, 0);
6634 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
6635 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
6636 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
6637 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
6638
6639 I915_WRITE(GEN6_RC_CONTROL,
6640 GEN6_RC_CTL_RC6p_ENABLE |
6641 GEN6_RC_CTL_RC6_ENABLE |
6642 GEN6_RC_CTL_EI_MODE(1) |
6643 GEN6_RC_CTL_HW_ENABLE);
6644
6645 I915_WRITE(GEN6_RPNSWREQ,
6646 GEN6_FREQUENCY(10) |
6647 GEN6_OFFSET(0) |
6648 GEN6_AGGRESSIVE_TURBO);
6649 I915_WRITE(GEN6_RC_VIDEO_FREQ,
6650 GEN6_FREQUENCY(12));
6651
6652 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
6653 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
6654 18 << 24 |
6655 6 << 16);
6656 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
6657 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
6658 I915_WRITE(GEN6_RP_UP_EI, 100000);
6659 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
6660 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6661 I915_WRITE(GEN6_RP_CONTROL,
6662 GEN6_RP_MEDIA_TURBO |
6663 GEN6_RP_USE_NORMAL_FREQ |
6664 GEN6_RP_MEDIA_IS_GFX |
6665 GEN6_RP_ENABLE |
6666 GEN6_RP_UP_BUSY_AVG |
6667 GEN6_RP_DOWN_IDLE_CONT);
6668
6669 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6670 500))
6671 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
6672
6673 I915_WRITE(GEN6_PCODE_DATA, 0);
6674 I915_WRITE(GEN6_PCODE_MAILBOX,
6675 GEN6_PCODE_READY |
6676 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
6677 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6678 500))
6679 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
6680
6681 min_freq = (rp_state_cap & 0xff0000) >> 16;
6682 max_freq = rp_state_cap & 0xff;
6683 cur_freq = (gt_perf_status & 0xff00) >> 8;
6684
6685 /* Check for overclock support */
6686 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6687 500))
6688 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
6689 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
6690 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
6691 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6692 500))
6693 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
6694 if (pcu_mbox & (1<<31)) { /* OC supported */
6695 max_freq = pcu_mbox & 0xff;
6696 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 100);
6697 }
6698
6699 /* In units of 100MHz */
6700 dev_priv->max_delay = max_freq;
6701 dev_priv->min_delay = min_freq;
6702 dev_priv->cur_delay = cur_freq;
6703
6704 /* requires MSI enabled */
6705 I915_WRITE(GEN6_PMIER,
6706 GEN6_PM_MBOX_EVENT |
6707 GEN6_PM_THERMAL_EVENT |
6708 GEN6_PM_RP_DOWN_TIMEOUT |
6709 GEN6_PM_RP_UP_THRESHOLD |
6710 GEN6_PM_RP_DOWN_THRESHOLD |
6711 GEN6_PM_RP_UP_EI_EXPIRED |
6712 GEN6_PM_RP_DOWN_EI_EXPIRED);
6713 I915_WRITE(GEN6_PMIMR, 0);
6714 /* enable all PM interrupts */
6715 I915_WRITE(GEN6_PMINTRMSK, 0);
6716
6717 __gen6_force_wake_put(dev_priv);
6718 }
6719
6720 void intel_enable_clock_gating(struct drm_device *dev)
6721 {
6722 struct drm_i915_private *dev_priv = dev->dev_private;
6723
6724 /*
6725 * Disable clock gating reported to work incorrectly according to the
6726 * specs, but enable as much else as we can.
6727 */
6728 if (HAS_PCH_SPLIT(dev)) {
6729 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
6730
6731 if (IS_GEN5(dev)) {
6732 /* Required for FBC */
6733 dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
6734 /* Required for CxSR */
6735 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
6736
6737 I915_WRITE(PCH_3DCGDIS0,
6738 MARIUNIT_CLOCK_GATE_DISABLE |
6739 SVSMUNIT_CLOCK_GATE_DISABLE);
6740 I915_WRITE(PCH_3DCGDIS1,
6741 VFMUNIT_CLOCK_GATE_DISABLE);
6742 }
6743
6744 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
6745
6746 /*
6747 * On Ibex Peak and Cougar Point, we need to disable clock
6748 * gating for the panel power sequencer or it will fail to
6749 * start up when no ports are active.
6750 */
6751 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6752
6753 /*
6754 * According to the spec the following bits should be set in
6755 * order to enable memory self-refresh
6756 * The bit 22/21 of 0x42004
6757 * The bit 5 of 0x42020
6758 * The bit 15 of 0x45000
6759 */
6760 if (IS_GEN5(dev)) {
6761 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6762 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6763 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6764 I915_WRITE(ILK_DSPCLK_GATE,
6765 (I915_READ(ILK_DSPCLK_GATE) |
6766 ILK_DPARB_CLK_GATE));
6767 I915_WRITE(DISP_ARB_CTL,
6768 (I915_READ(DISP_ARB_CTL) |
6769 DISP_FBC_WM_DIS));
6770 I915_WRITE(WM3_LP_ILK, 0);
6771 I915_WRITE(WM2_LP_ILK, 0);
6772 I915_WRITE(WM1_LP_ILK, 0);
6773 }
6774 /*
6775 * Based on the document from hardware guys the following bits
6776 * should be set unconditionally in order to enable FBC.
6777 * The bit 22 of 0x42000
6778 * The bit 22 of 0x42004
6779 * The bit 7,8,9 of 0x42020.
6780 */
6781 if (IS_IRONLAKE_M(dev)) {
6782 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6783 I915_READ(ILK_DISPLAY_CHICKEN1) |
6784 ILK_FBCQ_DIS);
6785 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6786 I915_READ(ILK_DISPLAY_CHICKEN2) |
6787 ILK_DPARB_GATE);
6788 I915_WRITE(ILK_DSPCLK_GATE,
6789 I915_READ(ILK_DSPCLK_GATE) |
6790 ILK_DPFC_DIS1 |
6791 ILK_DPFC_DIS2 |
6792 ILK_CLK_FBC);
6793 }
6794
6795 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6796 I915_READ(ILK_DISPLAY_CHICKEN2) |
6797 ILK_ELPIN_409_SELECT);
6798
6799 if (IS_GEN5(dev)) {
6800 I915_WRITE(_3D_CHICKEN2,
6801 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6802 _3D_CHICKEN2_WM_READ_PIPELINED);
6803 }
6804
6805 if (IS_GEN6(dev)) {
6806 I915_WRITE(WM3_LP_ILK, 0);
6807 I915_WRITE(WM2_LP_ILK, 0);
6808 I915_WRITE(WM1_LP_ILK, 0);
6809
6810 /*
6811 * According to the spec the following bits should be
6812 * set in order to enable memory self-refresh and fbc:
6813 * The bit21 and bit22 of 0x42000
6814 * The bit21 and bit22 of 0x42004
6815 * The bit5 and bit7 of 0x42020
6816 * The bit14 of 0x70180
6817 * The bit14 of 0x71180
6818 */
6819 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6820 I915_READ(ILK_DISPLAY_CHICKEN1) |
6821 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6822 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6823 I915_READ(ILK_DISPLAY_CHICKEN2) |
6824 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
6825 I915_WRITE(ILK_DSPCLK_GATE,
6826 I915_READ(ILK_DSPCLK_GATE) |
6827 ILK_DPARB_CLK_GATE |
6828 ILK_DPFD_CLK_GATE);
6829
6830 I915_WRITE(DSPACNTR,
6831 I915_READ(DSPACNTR) |
6832 DISPPLANE_TRICKLE_FEED_DISABLE);
6833 I915_WRITE(DSPBCNTR,
6834 I915_READ(DSPBCNTR) |
6835 DISPPLANE_TRICKLE_FEED_DISABLE);
6836 }
6837 } else if (IS_G4X(dev)) {
6838 uint32_t dspclk_gate;
6839 I915_WRITE(RENCLK_GATE_D1, 0);
6840 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6841 GS_UNIT_CLOCK_GATE_DISABLE |
6842 CL_UNIT_CLOCK_GATE_DISABLE);
6843 I915_WRITE(RAMCLK_GATE_D, 0);
6844 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6845 OVRUNIT_CLOCK_GATE_DISABLE |
6846 OVCUNIT_CLOCK_GATE_DISABLE;
6847 if (IS_GM45(dev))
6848 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6849 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
6850 } else if (IS_CRESTLINE(dev)) {
6851 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6852 I915_WRITE(RENCLK_GATE_D2, 0);
6853 I915_WRITE(DSPCLK_GATE_D, 0);
6854 I915_WRITE(RAMCLK_GATE_D, 0);
6855 I915_WRITE16(DEUC, 0);
6856 } else if (IS_BROADWATER(dev)) {
6857 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6858 I965_RCC_CLOCK_GATE_DISABLE |
6859 I965_RCPB_CLOCK_GATE_DISABLE |
6860 I965_ISC_CLOCK_GATE_DISABLE |
6861 I965_FBC_CLOCK_GATE_DISABLE);
6862 I915_WRITE(RENCLK_GATE_D2, 0);
6863 } else if (IS_GEN3(dev)) {
6864 u32 dstate = I915_READ(D_STATE);
6865
6866 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6867 DSTATE_DOT_CLOCK_GATING;
6868 I915_WRITE(D_STATE, dstate);
6869 } else if (IS_I85X(dev) || IS_I865G(dev)) {
6870 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
6871 } else if (IS_I830(dev)) {
6872 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
6873 }
6874 }
6875
6876 void intel_disable_clock_gating(struct drm_device *dev)
6877 {
6878 struct drm_i915_private *dev_priv = dev->dev_private;
6879
6880 if (dev_priv->renderctx) {
6881 struct drm_i915_gem_object *obj = dev_priv->renderctx;
6882
6883 I915_WRITE(CCID, 0);
6884 POSTING_READ(CCID);
6885
6886 i915_gem_object_unpin(obj);
6887 drm_gem_object_unreference(&obj->base);
6888 dev_priv->renderctx = NULL;
6889 }
6890
6891 if (dev_priv->pwrctx) {
6892 struct drm_i915_gem_object *obj = dev_priv->pwrctx;
6893
6894 I915_WRITE(PWRCTXA, 0);
6895 POSTING_READ(PWRCTXA);
6896
6897 i915_gem_object_unpin(obj);
6898 drm_gem_object_unreference(&obj->base);
6899 dev_priv->pwrctx = NULL;
6900 }
6901 }
6902
6903 static void ironlake_disable_rc6(struct drm_device *dev)
6904 {
6905 struct drm_i915_private *dev_priv = dev->dev_private;
6906
6907 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
6908 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
6909 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
6910 10);
6911 POSTING_READ(CCID);
6912 I915_WRITE(PWRCTXA, 0);
6913 POSTING_READ(PWRCTXA);
6914 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
6915 POSTING_READ(RSTDBYCTL);
6916 i915_gem_object_unpin(dev_priv->renderctx);
6917 drm_gem_object_unreference(&dev_priv->renderctx->base);
6918 dev_priv->renderctx = NULL;
6919 i915_gem_object_unpin(dev_priv->pwrctx);
6920 drm_gem_object_unreference(&dev_priv->pwrctx->base);
6921 dev_priv->pwrctx = NULL;
6922 }
6923
6924 void ironlake_enable_rc6(struct drm_device *dev)
6925 {
6926 struct drm_i915_private *dev_priv = dev->dev_private;
6927 int ret;
6928
6929 /*
6930 * GPU can automatically power down the render unit if given a page
6931 * to save state.
6932 */
6933 ret = BEGIN_LP_RING(6);
6934 if (ret) {
6935 ironlake_disable_rc6(dev);
6936 return;
6937 }
6938 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
6939 OUT_RING(MI_SET_CONTEXT);
6940 OUT_RING(dev_priv->renderctx->gtt_offset |
6941 MI_MM_SPACE_GTT |
6942 MI_SAVE_EXT_STATE_EN |
6943 MI_RESTORE_EXT_STATE_EN |
6944 MI_RESTORE_INHIBIT);
6945 OUT_RING(MI_SUSPEND_FLUSH);
6946 OUT_RING(MI_NOOP);
6947 OUT_RING(MI_FLUSH);
6948 ADVANCE_LP_RING();
6949
6950 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
6951 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
6952 }
6953
6954 /* Set up chip specific display functions */
6955 static void intel_init_display(struct drm_device *dev)
6956 {
6957 struct drm_i915_private *dev_priv = dev->dev_private;
6958
6959 /* We always want a DPMS function */
6960 if (HAS_PCH_SPLIT(dev))
6961 dev_priv->display.dpms = ironlake_crtc_dpms;
6962 else
6963 dev_priv->display.dpms = i9xx_crtc_dpms;
6964
6965 if (I915_HAS_FBC(dev)) {
6966 if (HAS_PCH_SPLIT(dev)) {
6967 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6968 dev_priv->display.enable_fbc = ironlake_enable_fbc;
6969 dev_priv->display.disable_fbc = ironlake_disable_fbc;
6970 } else if (IS_GM45(dev)) {
6971 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
6972 dev_priv->display.enable_fbc = g4x_enable_fbc;
6973 dev_priv->display.disable_fbc = g4x_disable_fbc;
6974 } else if (IS_CRESTLINE(dev)) {
6975 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
6976 dev_priv->display.enable_fbc = i8xx_enable_fbc;
6977 dev_priv->display.disable_fbc = i8xx_disable_fbc;
6978 }
6979 /* 855GM needs testing */
6980 }
6981
6982 /* Returns the core display clock speed */
6983 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
6984 dev_priv->display.get_display_clock_speed =
6985 i945_get_display_clock_speed;
6986 else if (IS_I915G(dev))
6987 dev_priv->display.get_display_clock_speed =
6988 i915_get_display_clock_speed;
6989 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
6990 dev_priv->display.get_display_clock_speed =
6991 i9xx_misc_get_display_clock_speed;
6992 else if (IS_I915GM(dev))
6993 dev_priv->display.get_display_clock_speed =
6994 i915gm_get_display_clock_speed;
6995 else if (IS_I865G(dev))
6996 dev_priv->display.get_display_clock_speed =
6997 i865_get_display_clock_speed;
6998 else if (IS_I85X(dev))
6999 dev_priv->display.get_display_clock_speed =
7000 i855_get_display_clock_speed;
7001 else /* 852, 830 */
7002 dev_priv->display.get_display_clock_speed =
7003 i830_get_display_clock_speed;
7004
7005 /* For FIFO watermark updates */
7006 if (HAS_PCH_SPLIT(dev)) {
7007 if (IS_GEN5(dev)) {
7008 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
7009 dev_priv->display.update_wm = ironlake_update_wm;
7010 else {
7011 DRM_DEBUG_KMS("Failed to get proper latency. "
7012 "Disable CxSR\n");
7013 dev_priv->display.update_wm = NULL;
7014 }
7015 } else if (IS_GEN6(dev)) {
7016 if (SNB_READ_WM0_LATENCY()) {
7017 dev_priv->display.update_wm = sandybridge_update_wm;
7018 } else {
7019 DRM_DEBUG_KMS("Failed to read display plane latency. "
7020 "Disable CxSR\n");
7021 dev_priv->display.update_wm = NULL;
7022 }
7023 } else
7024 dev_priv->display.update_wm = NULL;
7025 } else if (IS_PINEVIEW(dev)) {
7026 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7027 dev_priv->is_ddr3,
7028 dev_priv->fsb_freq,
7029 dev_priv->mem_freq)) {
7030 DRM_INFO("failed to find known CxSR latency "
7031 "(found ddr%s fsb freq %d, mem freq %d), "
7032 "disabling CxSR\n",
7033 (dev_priv->is_ddr3 == 1) ? "3": "2",
7034 dev_priv->fsb_freq, dev_priv->mem_freq);
7035 /* Disable CxSR and never update its watermark again */
7036 pineview_disable_cxsr(dev);
7037 dev_priv->display.update_wm = NULL;
7038 } else
7039 dev_priv->display.update_wm = pineview_update_wm;
7040 } else if (IS_G4X(dev))
7041 dev_priv->display.update_wm = g4x_update_wm;
7042 else if (IS_GEN4(dev))
7043 dev_priv->display.update_wm = i965_update_wm;
7044 else if (IS_GEN3(dev)) {
7045 dev_priv->display.update_wm = i9xx_update_wm;
7046 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7047 } else if (IS_I85X(dev)) {
7048 dev_priv->display.update_wm = i9xx_update_wm;
7049 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
7050 } else {
7051 dev_priv->display.update_wm = i830_update_wm;
7052 if (IS_845G(dev))
7053 dev_priv->display.get_fifo_size = i845_get_fifo_size;
7054 else
7055 dev_priv->display.get_fifo_size = i830_get_fifo_size;
7056 }
7057 }
7058
7059 /*
7060 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7061 * resume, or other times. This quirk makes sure that's the case for
7062 * affected systems.
7063 */
7064 static void quirk_pipea_force (struct drm_device *dev)
7065 {
7066 struct drm_i915_private *dev_priv = dev->dev_private;
7067
7068 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
7069 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
7070 }
7071
7072 struct intel_quirk {
7073 int device;
7074 int subsystem_vendor;
7075 int subsystem_device;
7076 void (*hook)(struct drm_device *dev);
7077 };
7078
7079 struct intel_quirk intel_quirks[] = {
7080 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
7081 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
7082 /* HP Mini needs pipe A force quirk (LP: #322104) */
7083 { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
7084
7085 /* Thinkpad R31 needs pipe A force quirk */
7086 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
7087 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7088 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
7089
7090 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
7091 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
7092 /* ThinkPad X40 needs pipe A force quirk */
7093
7094 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7095 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
7096
7097 /* 855 & before need to leave pipe A & dpll A up */
7098 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7099 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7100 };
7101
7102 static void intel_init_quirks(struct drm_device *dev)
7103 {
7104 struct pci_dev *d = dev->pdev;
7105 int i;
7106
7107 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
7108 struct intel_quirk *q = &intel_quirks[i];
7109
7110 if (d->device == q->device &&
7111 (d->subsystem_vendor == q->subsystem_vendor ||
7112 q->subsystem_vendor == PCI_ANY_ID) &&
7113 (d->subsystem_device == q->subsystem_device ||
7114 q->subsystem_device == PCI_ANY_ID))
7115 q->hook(dev);
7116 }
7117 }
7118
7119 /* Disable the VGA plane that we never use */
7120 static void i915_disable_vga(struct drm_device *dev)
7121 {
7122 struct drm_i915_private *dev_priv = dev->dev_private;
7123 u8 sr1;
7124 u32 vga_reg;
7125
7126 if (HAS_PCH_SPLIT(dev))
7127 vga_reg = CPU_VGACNTRL;
7128 else
7129 vga_reg = VGACNTRL;
7130
7131 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
7132 outb(1, VGA_SR_INDEX);
7133 sr1 = inb(VGA_SR_DATA);
7134 outb(sr1 | 1<<5, VGA_SR_DATA);
7135 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
7136 udelay(300);
7137
7138 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
7139 POSTING_READ(vga_reg);
7140 }
7141
7142 void intel_modeset_init(struct drm_device *dev)
7143 {
7144 struct drm_i915_private *dev_priv = dev->dev_private;
7145 int i;
7146
7147 drm_mode_config_init(dev);
7148
7149 dev->mode_config.min_width = 0;
7150 dev->mode_config.min_height = 0;
7151
7152 dev->mode_config.funcs = (void *)&intel_mode_funcs;
7153
7154 intel_init_quirks(dev);
7155
7156 intel_init_display(dev);
7157
7158 if (IS_GEN2(dev)) {
7159 dev->mode_config.max_width = 2048;
7160 dev->mode_config.max_height = 2048;
7161 } else if (IS_GEN3(dev)) {
7162 dev->mode_config.max_width = 4096;
7163 dev->mode_config.max_height = 4096;
7164 } else {
7165 dev->mode_config.max_width = 8192;
7166 dev->mode_config.max_height = 8192;
7167 }
7168 dev->mode_config.fb_base = dev->agp->base;
7169
7170 if (IS_MOBILE(dev) || !IS_GEN2(dev))
7171 dev_priv->num_pipe = 2;
7172 else
7173 dev_priv->num_pipe = 1;
7174 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7175 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
7176
7177 for (i = 0; i < dev_priv->num_pipe; i++) {
7178 intel_crtc_init(dev, i);
7179 }
7180
7181 intel_setup_outputs(dev);
7182
7183 intel_enable_clock_gating(dev);
7184
7185 /* Just disable it once at startup */
7186 i915_disable_vga(dev);
7187
7188 if (IS_IRONLAKE_M(dev)) {
7189 ironlake_enable_drps(dev);
7190 intel_init_emon(dev);
7191 }
7192
7193 if (IS_GEN6(dev))
7194 gen6_enable_rps(dev_priv);
7195
7196 if (IS_IRONLAKE_M(dev)) {
7197 dev_priv->renderctx = intel_alloc_context_page(dev);
7198 if (!dev_priv->renderctx)
7199 goto skip_rc6;
7200 dev_priv->pwrctx = intel_alloc_context_page(dev);
7201 if (!dev_priv->pwrctx) {
7202 i915_gem_object_unpin(dev_priv->renderctx);
7203 drm_gem_object_unreference(&dev_priv->renderctx->base);
7204 dev_priv->renderctx = NULL;
7205 goto skip_rc6;
7206 }
7207 ironlake_enable_rc6(dev);
7208 }
7209
7210 skip_rc6:
7211 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
7212 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
7213 (unsigned long)dev);
7214
7215 intel_setup_overlay(dev);
7216 }
7217
7218 void intel_modeset_cleanup(struct drm_device *dev)
7219 {
7220 struct drm_i915_private *dev_priv = dev->dev_private;
7221 struct drm_crtc *crtc;
7222 struct intel_crtc *intel_crtc;
7223
7224 drm_kms_helper_poll_fini(dev);
7225 mutex_lock(&dev->struct_mutex);
7226
7227 intel_unregister_dsm_handler();
7228
7229
7230 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7231 /* Skip inactive CRTCs */
7232 if (!crtc->fb)
7233 continue;
7234
7235 intel_crtc = to_intel_crtc(crtc);
7236 intel_increase_pllclock(crtc);
7237 }
7238
7239 if (dev_priv->display.disable_fbc)
7240 dev_priv->display.disable_fbc(dev);
7241
7242 if (IS_IRONLAKE_M(dev))
7243 ironlake_disable_drps(dev);
7244 if (IS_GEN6(dev))
7245 gen6_disable_rps(dev);
7246
7247 if (IS_IRONLAKE_M(dev))
7248 ironlake_disable_rc6(dev);
7249
7250 mutex_unlock(&dev->struct_mutex);
7251
7252 /* Disable the irq before mode object teardown, for the irq might
7253 * enqueue unpin/hotplug work. */
7254 drm_irq_uninstall(dev);
7255 cancel_work_sync(&dev_priv->hotplug_work);
7256
7257 /* Shut off idle work before the crtcs get freed. */
7258 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7259 intel_crtc = to_intel_crtc(crtc);
7260 del_timer_sync(&intel_crtc->idle_timer);
7261 }
7262 del_timer_sync(&dev_priv->idle_timer);
7263 cancel_work_sync(&dev_priv->idle_work);
7264
7265 drm_mode_config_cleanup(dev);
7266 }
7267
7268 /*
7269 * Return which encoder is currently attached for connector.
7270 */
7271 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
7272 {
7273 return &intel_attached_encoder(connector)->base;
7274 }
7275
7276 void intel_connector_attach_encoder(struct intel_connector *connector,
7277 struct intel_encoder *encoder)
7278 {
7279 connector->encoder = encoder;
7280 drm_mode_connector_attach_encoder(&connector->base,
7281 &encoder->base);
7282 }
7283
7284 /*
7285 * set vga decode state - true == enable VGA decode
7286 */
7287 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
7288 {
7289 struct drm_i915_private *dev_priv = dev->dev_private;
7290 u16 gmch_ctrl;
7291
7292 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
7293 if (state)
7294 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
7295 else
7296 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
7297 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
7298 return 0;
7299 }
7300
7301 #ifdef CONFIG_DEBUG_FS
7302 #include <linux/seq_file.h>
7303
7304 struct intel_display_error_state {
7305 struct intel_cursor_error_state {
7306 u32 control;
7307 u32 position;
7308 u32 base;
7309 u32 size;
7310 } cursor[2];
7311
7312 struct intel_pipe_error_state {
7313 u32 conf;
7314 u32 source;
7315
7316 u32 htotal;
7317 u32 hblank;
7318 u32 hsync;
7319 u32 vtotal;
7320 u32 vblank;
7321 u32 vsync;
7322 } pipe[2];
7323
7324 struct intel_plane_error_state {
7325 u32 control;
7326 u32 stride;
7327 u32 size;
7328 u32 pos;
7329 u32 addr;
7330 u32 surface;
7331 u32 tile_offset;
7332 } plane[2];
7333 };
7334
7335 struct intel_display_error_state *
7336 intel_display_capture_error_state(struct drm_device *dev)
7337 {
7338 drm_i915_private_t *dev_priv = dev->dev_private;
7339 struct intel_display_error_state *error;
7340 int i;
7341
7342 error = kmalloc(sizeof(*error), GFP_ATOMIC);
7343 if (error == NULL)
7344 return NULL;
7345
7346 for (i = 0; i < 2; i++) {
7347 error->cursor[i].control = I915_READ(CURCNTR(i));
7348 error->cursor[i].position = I915_READ(CURPOS(i));
7349 error->cursor[i].base = I915_READ(CURBASE(i));
7350
7351 error->plane[i].control = I915_READ(DSPCNTR(i));
7352 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
7353 error->plane[i].size = I915_READ(DSPSIZE(i));
7354 error->plane[i].pos= I915_READ(DSPPOS(i));
7355 error->plane[i].addr = I915_READ(DSPADDR(i));
7356 if (INTEL_INFO(dev)->gen >= 4) {
7357 error->plane[i].surface = I915_READ(DSPSURF(i));
7358 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
7359 }
7360
7361 error->pipe[i].conf = I915_READ(PIPECONF(i));
7362 error->pipe[i].source = I915_READ(PIPESRC(i));
7363 error->pipe[i].htotal = I915_READ(HTOTAL(i));
7364 error->pipe[i].hblank = I915_READ(HBLANK(i));
7365 error->pipe[i].hsync = I915_READ(HSYNC(i));
7366 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
7367 error->pipe[i].vblank = I915_READ(VBLANK(i));
7368 error->pipe[i].vsync = I915_READ(VSYNC(i));
7369 }
7370
7371 return error;
7372 }
7373
7374 void
7375 intel_display_print_error_state(struct seq_file *m,
7376 struct drm_device *dev,
7377 struct intel_display_error_state *error)
7378 {
7379 int i;
7380
7381 for (i = 0; i < 2; i++) {
7382 seq_printf(m, "Pipe [%d]:\n", i);
7383 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
7384 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
7385 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
7386 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
7387 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
7388 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
7389 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
7390 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
7391
7392 seq_printf(m, "Plane [%d]:\n", i);
7393 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
7394 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
7395 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
7396 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
7397 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
7398 if (INTEL_INFO(dev)->gen >= 4) {
7399 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
7400 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
7401 }
7402
7403 seq_printf(m, "Cursor [%d]:\n", i);
7404 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
7405 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
7406 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
7407 }
7408 }
7409 #endif
Linux kernel - Deliverables
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