2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_rect.h>
44 #include <linux/dma_remapping.h>
46 /* Primary plane formats supported by all gen */
47 #define COMMON_PRIMARY_FORMATS \
50 DRM_FORMAT_XRGB8888, \
53 /* Primary plane formats for gen <= 3 */
54 static const uint32_t intel_primary_formats_gen2
[] = {
55 COMMON_PRIMARY_FORMATS
,
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t intel_primary_formats_gen4
[] = {
62 COMMON_PRIMARY_FORMATS
, \
65 DRM_FORMAT_XRGB2101010
,
66 DRM_FORMAT_ARGB2101010
,
67 DRM_FORMAT_XBGR2101010
,
68 DRM_FORMAT_ABGR2101010
,
72 static const uint32_t intel_cursor_formats
[] = {
76 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
78 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
79 struct intel_crtc_state
*pipe_config
);
80 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
81 struct intel_crtc_state
*pipe_config
);
83 static int intel_set_mode(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
,
84 int x
, int y
, struct drm_framebuffer
*old_fb
);
85 static int intel_framebuffer_init(struct drm_device
*dev
,
86 struct intel_framebuffer
*ifb
,
87 struct drm_mode_fb_cmd2
*mode_cmd
,
88 struct drm_i915_gem_object
*obj
);
89 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
);
90 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
);
91 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
92 struct intel_link_m_n
*m_n
,
93 struct intel_link_m_n
*m2_n2
);
94 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
);
95 static void haswell_set_pipeconf(struct drm_crtc
*crtc
);
96 static void intel_set_pipe_csc(struct drm_crtc
*crtc
);
97 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
98 const struct intel_crtc_state
*pipe_config
);
99 static void chv_prepare_pll(struct intel_crtc
*crtc
,
100 const struct intel_crtc_state
*pipe_config
);
101 static void intel_begin_crtc_commit(struct drm_crtc
*crtc
);
102 static void intel_finish_crtc_commit(struct drm_crtc
*crtc
);
104 static struct intel_encoder
*intel_find_encoder(struct intel_connector
*connector
, int pipe
)
106 if (!connector
->mst_port
)
107 return connector
->encoder
;
109 return &connector
->mst_port
->mst_encoders
[pipe
]->base
;
118 int p2_slow
, p2_fast
;
121 typedef struct intel_limit intel_limit_t
;
123 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
128 intel_pch_rawclk(struct drm_device
*dev
)
130 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
132 WARN_ON(!HAS_PCH_SPLIT(dev
));
134 return I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
;
137 static inline u32
/* units of 100MHz */
138 intel_fdi_link_freq(struct drm_device
*dev
)
141 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
142 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
147 static const intel_limit_t intel_limits_i8xx_dac
= {
148 .dot
= { .min
= 25000, .max
= 350000 },
149 .vco
= { .min
= 908000, .max
= 1512000 },
150 .n
= { .min
= 2, .max
= 16 },
151 .m
= { .min
= 96, .max
= 140 },
152 .m1
= { .min
= 18, .max
= 26 },
153 .m2
= { .min
= 6, .max
= 16 },
154 .p
= { .min
= 4, .max
= 128 },
155 .p1
= { .min
= 2, .max
= 33 },
156 .p2
= { .dot_limit
= 165000,
157 .p2_slow
= 4, .p2_fast
= 2 },
160 static const intel_limit_t intel_limits_i8xx_dvo
= {
161 .dot
= { .min
= 25000, .max
= 350000 },
162 .vco
= { .min
= 908000, .max
= 1512000 },
163 .n
= { .min
= 2, .max
= 16 },
164 .m
= { .min
= 96, .max
= 140 },
165 .m1
= { .min
= 18, .max
= 26 },
166 .m2
= { .min
= 6, .max
= 16 },
167 .p
= { .min
= 4, .max
= 128 },
168 .p1
= { .min
= 2, .max
= 33 },
169 .p2
= { .dot_limit
= 165000,
170 .p2_slow
= 4, .p2_fast
= 4 },
173 static const intel_limit_t intel_limits_i8xx_lvds
= {
174 .dot
= { .min
= 25000, .max
= 350000 },
175 .vco
= { .min
= 908000, .max
= 1512000 },
176 .n
= { .min
= 2, .max
= 16 },
177 .m
= { .min
= 96, .max
= 140 },
178 .m1
= { .min
= 18, .max
= 26 },
179 .m2
= { .min
= 6, .max
= 16 },
180 .p
= { .min
= 4, .max
= 128 },
181 .p1
= { .min
= 1, .max
= 6 },
182 .p2
= { .dot_limit
= 165000,
183 .p2_slow
= 14, .p2_fast
= 7 },
186 static const intel_limit_t intel_limits_i9xx_sdvo
= {
187 .dot
= { .min
= 20000, .max
= 400000 },
188 .vco
= { .min
= 1400000, .max
= 2800000 },
189 .n
= { .min
= 1, .max
= 6 },
190 .m
= { .min
= 70, .max
= 120 },
191 .m1
= { .min
= 8, .max
= 18 },
192 .m2
= { .min
= 3, .max
= 7 },
193 .p
= { .min
= 5, .max
= 80 },
194 .p1
= { .min
= 1, .max
= 8 },
195 .p2
= { .dot_limit
= 200000,
196 .p2_slow
= 10, .p2_fast
= 5 },
199 static const intel_limit_t intel_limits_i9xx_lvds
= {
200 .dot
= { .min
= 20000, .max
= 400000 },
201 .vco
= { .min
= 1400000, .max
= 2800000 },
202 .n
= { .min
= 1, .max
= 6 },
203 .m
= { .min
= 70, .max
= 120 },
204 .m1
= { .min
= 8, .max
= 18 },
205 .m2
= { .min
= 3, .max
= 7 },
206 .p
= { .min
= 7, .max
= 98 },
207 .p1
= { .min
= 1, .max
= 8 },
208 .p2
= { .dot_limit
= 112000,
209 .p2_slow
= 14, .p2_fast
= 7 },
213 static const intel_limit_t intel_limits_g4x_sdvo
= {
214 .dot
= { .min
= 25000, .max
= 270000 },
215 .vco
= { .min
= 1750000, .max
= 3500000},
216 .n
= { .min
= 1, .max
= 4 },
217 .m
= { .min
= 104, .max
= 138 },
218 .m1
= { .min
= 17, .max
= 23 },
219 .m2
= { .min
= 5, .max
= 11 },
220 .p
= { .min
= 10, .max
= 30 },
221 .p1
= { .min
= 1, .max
= 3},
222 .p2
= { .dot_limit
= 270000,
228 static const intel_limit_t intel_limits_g4x_hdmi
= {
229 .dot
= { .min
= 22000, .max
= 400000 },
230 .vco
= { .min
= 1750000, .max
= 3500000},
231 .n
= { .min
= 1, .max
= 4 },
232 .m
= { .min
= 104, .max
= 138 },
233 .m1
= { .min
= 16, .max
= 23 },
234 .m2
= { .min
= 5, .max
= 11 },
235 .p
= { .min
= 5, .max
= 80 },
236 .p1
= { .min
= 1, .max
= 8},
237 .p2
= { .dot_limit
= 165000,
238 .p2_slow
= 10, .p2_fast
= 5 },
241 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
242 .dot
= { .min
= 20000, .max
= 115000 },
243 .vco
= { .min
= 1750000, .max
= 3500000 },
244 .n
= { .min
= 1, .max
= 3 },
245 .m
= { .min
= 104, .max
= 138 },
246 .m1
= { .min
= 17, .max
= 23 },
247 .m2
= { .min
= 5, .max
= 11 },
248 .p
= { .min
= 28, .max
= 112 },
249 .p1
= { .min
= 2, .max
= 8 },
250 .p2
= { .dot_limit
= 0,
251 .p2_slow
= 14, .p2_fast
= 14
255 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
256 .dot
= { .min
= 80000, .max
= 224000 },
257 .vco
= { .min
= 1750000, .max
= 3500000 },
258 .n
= { .min
= 1, .max
= 3 },
259 .m
= { .min
= 104, .max
= 138 },
260 .m1
= { .min
= 17, .max
= 23 },
261 .m2
= { .min
= 5, .max
= 11 },
262 .p
= { .min
= 14, .max
= 42 },
263 .p1
= { .min
= 2, .max
= 6 },
264 .p2
= { .dot_limit
= 0,
265 .p2_slow
= 7, .p2_fast
= 7
269 static const intel_limit_t intel_limits_pineview_sdvo
= {
270 .dot
= { .min
= 20000, .max
= 400000},
271 .vco
= { .min
= 1700000, .max
= 3500000 },
272 /* Pineview's Ncounter is a ring counter */
273 .n
= { .min
= 3, .max
= 6 },
274 .m
= { .min
= 2, .max
= 256 },
275 /* Pineview only has one combined m divider, which we treat as m2. */
276 .m1
= { .min
= 0, .max
= 0 },
277 .m2
= { .min
= 0, .max
= 254 },
278 .p
= { .min
= 5, .max
= 80 },
279 .p1
= { .min
= 1, .max
= 8 },
280 .p2
= { .dot_limit
= 200000,
281 .p2_slow
= 10, .p2_fast
= 5 },
284 static const intel_limit_t intel_limits_pineview_lvds
= {
285 .dot
= { .min
= 20000, .max
= 400000 },
286 .vco
= { .min
= 1700000, .max
= 3500000 },
287 .n
= { .min
= 3, .max
= 6 },
288 .m
= { .min
= 2, .max
= 256 },
289 .m1
= { .min
= 0, .max
= 0 },
290 .m2
= { .min
= 0, .max
= 254 },
291 .p
= { .min
= 7, .max
= 112 },
292 .p1
= { .min
= 1, .max
= 8 },
293 .p2
= { .dot_limit
= 112000,
294 .p2_slow
= 14, .p2_fast
= 14 },
297 /* Ironlake / Sandybridge
299 * We calculate clock using (register_value + 2) for N/M1/M2, so here
300 * the range value for them is (actual_value - 2).
302 static const intel_limit_t intel_limits_ironlake_dac
= {
303 .dot
= { .min
= 25000, .max
= 350000 },
304 .vco
= { .min
= 1760000, .max
= 3510000 },
305 .n
= { .min
= 1, .max
= 5 },
306 .m
= { .min
= 79, .max
= 127 },
307 .m1
= { .min
= 12, .max
= 22 },
308 .m2
= { .min
= 5, .max
= 9 },
309 .p
= { .min
= 5, .max
= 80 },
310 .p1
= { .min
= 1, .max
= 8 },
311 .p2
= { .dot_limit
= 225000,
312 .p2_slow
= 10, .p2_fast
= 5 },
315 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
316 .dot
= { .min
= 25000, .max
= 350000 },
317 .vco
= { .min
= 1760000, .max
= 3510000 },
318 .n
= { .min
= 1, .max
= 3 },
319 .m
= { .min
= 79, .max
= 118 },
320 .m1
= { .min
= 12, .max
= 22 },
321 .m2
= { .min
= 5, .max
= 9 },
322 .p
= { .min
= 28, .max
= 112 },
323 .p1
= { .min
= 2, .max
= 8 },
324 .p2
= { .dot_limit
= 225000,
325 .p2_slow
= 14, .p2_fast
= 14 },
328 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
329 .dot
= { .min
= 25000, .max
= 350000 },
330 .vco
= { .min
= 1760000, .max
= 3510000 },
331 .n
= { .min
= 1, .max
= 3 },
332 .m
= { .min
= 79, .max
= 127 },
333 .m1
= { .min
= 12, .max
= 22 },
334 .m2
= { .min
= 5, .max
= 9 },
335 .p
= { .min
= 14, .max
= 56 },
336 .p1
= { .min
= 2, .max
= 8 },
337 .p2
= { .dot_limit
= 225000,
338 .p2_slow
= 7, .p2_fast
= 7 },
341 /* LVDS 100mhz refclk limits. */
342 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
343 .dot
= { .min
= 25000, .max
= 350000 },
344 .vco
= { .min
= 1760000, .max
= 3510000 },
345 .n
= { .min
= 1, .max
= 2 },
346 .m
= { .min
= 79, .max
= 126 },
347 .m1
= { .min
= 12, .max
= 22 },
348 .m2
= { .min
= 5, .max
= 9 },
349 .p
= { .min
= 28, .max
= 112 },
350 .p1
= { .min
= 2, .max
= 8 },
351 .p2
= { .dot_limit
= 225000,
352 .p2_slow
= 14, .p2_fast
= 14 },
355 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
356 .dot
= { .min
= 25000, .max
= 350000 },
357 .vco
= { .min
= 1760000, .max
= 3510000 },
358 .n
= { .min
= 1, .max
= 3 },
359 .m
= { .min
= 79, .max
= 126 },
360 .m1
= { .min
= 12, .max
= 22 },
361 .m2
= { .min
= 5, .max
= 9 },
362 .p
= { .min
= 14, .max
= 42 },
363 .p1
= { .min
= 2, .max
= 6 },
364 .p2
= { .dot_limit
= 225000,
365 .p2_slow
= 7, .p2_fast
= 7 },
368 static const intel_limit_t intel_limits_vlv
= {
370 * These are the data rate limits (measured in fast clocks)
371 * since those are the strictest limits we have. The fast
372 * clock and actual rate limits are more relaxed, so checking
373 * them would make no difference.
375 .dot
= { .min
= 25000 * 5, .max
= 270000 * 5 },
376 .vco
= { .min
= 4000000, .max
= 6000000 },
377 .n
= { .min
= 1, .max
= 7 },
378 .m1
= { .min
= 2, .max
= 3 },
379 .m2
= { .min
= 11, .max
= 156 },
380 .p1
= { .min
= 2, .max
= 3 },
381 .p2
= { .p2_slow
= 2, .p2_fast
= 20 }, /* slow=min, fast=max */
384 static const intel_limit_t intel_limits_chv
= {
386 * These are the data rate limits (measured in fast clocks)
387 * since those are the strictest limits we have. The fast
388 * clock and actual rate limits are more relaxed, so checking
389 * them would make no difference.
391 .dot
= { .min
= 25000 * 5, .max
= 540000 * 5},
392 .vco
= { .min
= 4860000, .max
= 6700000 },
393 .n
= { .min
= 1, .max
= 1 },
394 .m1
= { .min
= 2, .max
= 2 },
395 .m2
= { .min
= 24 << 22, .max
= 175 << 22 },
396 .p1
= { .min
= 2, .max
= 4 },
397 .p2
= { .p2_slow
= 1, .p2_fast
= 14 },
400 static void vlv_clock(int refclk
, intel_clock_t
*clock
)
402 clock
->m
= clock
->m1
* clock
->m2
;
403 clock
->p
= clock
->p1
* clock
->p2
;
404 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
406 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
407 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
411 * Returns whether any output on the specified pipe is of the specified type
413 bool intel_pipe_has_type(struct intel_crtc
*crtc
, enum intel_output_type type
)
415 struct drm_device
*dev
= crtc
->base
.dev
;
416 struct intel_encoder
*encoder
;
418 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
)
419 if (encoder
->type
== type
)
426 * Returns whether any output on the specified pipe will have the specified
427 * type after a staged modeset is complete, i.e., the same as
428 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
431 static bool intel_pipe_will_have_type(struct intel_crtc
*crtc
, int type
)
433 struct drm_device
*dev
= crtc
->base
.dev
;
434 struct intel_encoder
*encoder
;
436 for_each_intel_encoder(dev
, encoder
)
437 if (encoder
->new_crtc
== crtc
&& encoder
->type
== type
)
443 static const intel_limit_t
*intel_ironlake_limit(struct intel_crtc
*crtc
,
446 struct drm_device
*dev
= crtc
->base
.dev
;
447 const intel_limit_t
*limit
;
449 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
)) {
450 if (intel_is_dual_link_lvds(dev
)) {
451 if (refclk
== 100000)
452 limit
= &intel_limits_ironlake_dual_lvds_100m
;
454 limit
= &intel_limits_ironlake_dual_lvds
;
456 if (refclk
== 100000)
457 limit
= &intel_limits_ironlake_single_lvds_100m
;
459 limit
= &intel_limits_ironlake_single_lvds
;
462 limit
= &intel_limits_ironlake_dac
;
467 static const intel_limit_t
*intel_g4x_limit(struct intel_crtc
*crtc
)
469 struct drm_device
*dev
= crtc
->base
.dev
;
470 const intel_limit_t
*limit
;
472 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
)) {
473 if (intel_is_dual_link_lvds(dev
))
474 limit
= &intel_limits_g4x_dual_channel_lvds
;
476 limit
= &intel_limits_g4x_single_channel_lvds
;
477 } else if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_HDMI
) ||
478 intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
479 limit
= &intel_limits_g4x_hdmi
;
480 } else if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_SDVO
)) {
481 limit
= &intel_limits_g4x_sdvo
;
482 } else /* The option is for other outputs */
483 limit
= &intel_limits_i9xx_sdvo
;
488 static const intel_limit_t
*intel_limit(struct intel_crtc
*crtc
, int refclk
)
490 struct drm_device
*dev
= crtc
->base
.dev
;
491 const intel_limit_t
*limit
;
493 if (HAS_PCH_SPLIT(dev
))
494 limit
= intel_ironlake_limit(crtc
, refclk
);
495 else if (IS_G4X(dev
)) {
496 limit
= intel_g4x_limit(crtc
);
497 } else if (IS_PINEVIEW(dev
)) {
498 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
))
499 limit
= &intel_limits_pineview_lvds
;
501 limit
= &intel_limits_pineview_sdvo
;
502 } else if (IS_CHERRYVIEW(dev
)) {
503 limit
= &intel_limits_chv
;
504 } else if (IS_VALLEYVIEW(dev
)) {
505 limit
= &intel_limits_vlv
;
506 } else if (!IS_GEN2(dev
)) {
507 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
))
508 limit
= &intel_limits_i9xx_lvds
;
510 limit
= &intel_limits_i9xx_sdvo
;
512 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
))
513 limit
= &intel_limits_i8xx_lvds
;
514 else if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_DVO
))
515 limit
= &intel_limits_i8xx_dvo
;
517 limit
= &intel_limits_i8xx_dac
;
522 /* m1 is reserved as 0 in Pineview, n is a ring counter */
523 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
525 clock
->m
= clock
->m2
+ 2;
526 clock
->p
= clock
->p1
* clock
->p2
;
527 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
529 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
530 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
533 static uint32_t i9xx_dpll_compute_m(struct dpll
*dpll
)
535 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
538 static void i9xx_clock(int refclk
, intel_clock_t
*clock
)
540 clock
->m
= i9xx_dpll_compute_m(clock
);
541 clock
->p
= clock
->p1
* clock
->p2
;
542 if (WARN_ON(clock
->n
+ 2 == 0 || clock
->p
== 0))
544 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
+ 2);
545 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
548 static void chv_clock(int refclk
, intel_clock_t
*clock
)
550 clock
->m
= clock
->m1
* clock
->m2
;
551 clock
->p
= clock
->p1
* clock
->p2
;
552 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
554 clock
->vco
= DIV_ROUND_CLOSEST_ULL((uint64_t)refclk
* clock
->m
,
556 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
559 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
561 * Returns whether the given set of divisors are valid for a given refclk with
562 * the given connectors.
565 static bool intel_PLL_is_valid(struct drm_device
*dev
,
566 const intel_limit_t
*limit
,
567 const intel_clock_t
*clock
)
569 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
570 INTELPllInvalid("n out of range\n");
571 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
572 INTELPllInvalid("p1 out of range\n");
573 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
574 INTELPllInvalid("m2 out of range\n");
575 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
576 INTELPllInvalid("m1 out of range\n");
578 if (!IS_PINEVIEW(dev
) && !IS_VALLEYVIEW(dev
))
579 if (clock
->m1
<= clock
->m2
)
580 INTELPllInvalid("m1 <= m2\n");
582 if (!IS_VALLEYVIEW(dev
)) {
583 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
584 INTELPllInvalid("p out of range\n");
585 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
586 INTELPllInvalid("m out of range\n");
589 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
590 INTELPllInvalid("vco out of range\n");
591 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
592 * connector, etc., rather than just a single range.
594 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
595 INTELPllInvalid("dot out of range\n");
601 i9xx_find_best_dpll(const intel_limit_t
*limit
, struct intel_crtc
*crtc
,
602 int target
, int refclk
, intel_clock_t
*match_clock
,
603 intel_clock_t
*best_clock
)
605 struct drm_device
*dev
= crtc
->base
.dev
;
609 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
)) {
611 * For LVDS just rely on its current settings for dual-channel.
612 * We haven't figured out how to reliably set up different
613 * single/dual channel state, if we even can.
615 if (intel_is_dual_link_lvds(dev
))
616 clock
.p2
= limit
->p2
.p2_fast
;
618 clock
.p2
= limit
->p2
.p2_slow
;
620 if (target
< limit
->p2
.dot_limit
)
621 clock
.p2
= limit
->p2
.p2_slow
;
623 clock
.p2
= limit
->p2
.p2_fast
;
626 memset(best_clock
, 0, sizeof(*best_clock
));
628 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
630 for (clock
.m2
= limit
->m2
.min
;
631 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
632 if (clock
.m2
>= clock
.m1
)
634 for (clock
.n
= limit
->n
.min
;
635 clock
.n
<= limit
->n
.max
; clock
.n
++) {
636 for (clock
.p1
= limit
->p1
.min
;
637 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
640 i9xx_clock(refclk
, &clock
);
641 if (!intel_PLL_is_valid(dev
, limit
,
645 clock
.p
!= match_clock
->p
)
648 this_err
= abs(clock
.dot
- target
);
649 if (this_err
< err
) {
658 return (err
!= target
);
662 pnv_find_best_dpll(const intel_limit_t
*limit
, struct intel_crtc
*crtc
,
663 int target
, int refclk
, intel_clock_t
*match_clock
,
664 intel_clock_t
*best_clock
)
666 struct drm_device
*dev
= crtc
->base
.dev
;
670 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
)) {
672 * For LVDS just rely on its current settings for dual-channel.
673 * We haven't figured out how to reliably set up different
674 * single/dual channel state, if we even can.
676 if (intel_is_dual_link_lvds(dev
))
677 clock
.p2
= limit
->p2
.p2_fast
;
679 clock
.p2
= limit
->p2
.p2_slow
;
681 if (target
< limit
->p2
.dot_limit
)
682 clock
.p2
= limit
->p2
.p2_slow
;
684 clock
.p2
= limit
->p2
.p2_fast
;
687 memset(best_clock
, 0, sizeof(*best_clock
));
689 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
691 for (clock
.m2
= limit
->m2
.min
;
692 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
693 for (clock
.n
= limit
->n
.min
;
694 clock
.n
<= limit
->n
.max
; clock
.n
++) {
695 for (clock
.p1
= limit
->p1
.min
;
696 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
699 pineview_clock(refclk
, &clock
);
700 if (!intel_PLL_is_valid(dev
, limit
,
704 clock
.p
!= match_clock
->p
)
707 this_err
= abs(clock
.dot
- target
);
708 if (this_err
< err
) {
717 return (err
!= target
);
721 g4x_find_best_dpll(const intel_limit_t
*limit
, struct intel_crtc
*crtc
,
722 int target
, int refclk
, intel_clock_t
*match_clock
,
723 intel_clock_t
*best_clock
)
725 struct drm_device
*dev
= crtc
->base
.dev
;
729 /* approximately equals target * 0.00585 */
730 int err_most
= (target
>> 8) + (target
>> 9);
733 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
)) {
734 if (intel_is_dual_link_lvds(dev
))
735 clock
.p2
= limit
->p2
.p2_fast
;
737 clock
.p2
= limit
->p2
.p2_slow
;
739 if (target
< limit
->p2
.dot_limit
)
740 clock
.p2
= limit
->p2
.p2_slow
;
742 clock
.p2
= limit
->p2
.p2_fast
;
745 memset(best_clock
, 0, sizeof(*best_clock
));
746 max_n
= limit
->n
.max
;
747 /* based on hardware requirement, prefer smaller n to precision */
748 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
749 /* based on hardware requirement, prefere larger m1,m2 */
750 for (clock
.m1
= limit
->m1
.max
;
751 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
752 for (clock
.m2
= limit
->m2
.max
;
753 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
754 for (clock
.p1
= limit
->p1
.max
;
755 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
758 i9xx_clock(refclk
, &clock
);
759 if (!intel_PLL_is_valid(dev
, limit
,
763 this_err
= abs(clock
.dot
- target
);
764 if (this_err
< err_most
) {
778 vlv_find_best_dpll(const intel_limit_t
*limit
, struct intel_crtc
*crtc
,
779 int target
, int refclk
, intel_clock_t
*match_clock
,
780 intel_clock_t
*best_clock
)
782 struct drm_device
*dev
= crtc
->base
.dev
;
784 unsigned int bestppm
= 1000000;
785 /* min update 19.2 MHz */
786 int max_n
= min(limit
->n
.max
, refclk
/ 19200);
789 target
*= 5; /* fast clock */
791 memset(best_clock
, 0, sizeof(*best_clock
));
793 /* based on hardware requirement, prefer smaller n to precision */
794 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
795 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
796 for (clock
.p2
= limit
->p2
.p2_fast
; clock
.p2
>= limit
->p2
.p2_slow
;
797 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
798 clock
.p
= clock
.p1
* clock
.p2
;
799 /* based on hardware requirement, prefer bigger m1,m2 values */
800 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
; clock
.m1
++) {
801 unsigned int ppm
, diff
;
803 clock
.m2
= DIV_ROUND_CLOSEST(target
* clock
.p
* clock
.n
,
806 vlv_clock(refclk
, &clock
);
808 if (!intel_PLL_is_valid(dev
, limit
,
812 diff
= abs(clock
.dot
- target
);
813 ppm
= div_u64(1000000ULL * diff
, target
);
815 if (ppm
< 100 && clock
.p
> best_clock
->p
) {
821 if (bestppm
>= 10 && ppm
< bestppm
- 10) {
835 chv_find_best_dpll(const intel_limit_t
*limit
, struct intel_crtc
*crtc
,
836 int target
, int refclk
, intel_clock_t
*match_clock
,
837 intel_clock_t
*best_clock
)
839 struct drm_device
*dev
= crtc
->base
.dev
;
844 memset(best_clock
, 0, sizeof(*best_clock
));
847 * Based on hardware doc, the n always set to 1, and m1 always
848 * set to 2. If requires to support 200Mhz refclk, we need to
849 * revisit this because n may not 1 anymore.
851 clock
.n
= 1, clock
.m1
= 2;
852 target
*= 5; /* fast clock */
854 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
855 for (clock
.p2
= limit
->p2
.p2_fast
;
856 clock
.p2
>= limit
->p2
.p2_slow
;
857 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
859 clock
.p
= clock
.p1
* clock
.p2
;
861 m2
= DIV_ROUND_CLOSEST_ULL(((uint64_t)target
* clock
.p
*
862 clock
.n
) << 22, refclk
* clock
.m1
);
864 if (m2
> INT_MAX
/clock
.m1
)
869 chv_clock(refclk
, &clock
);
871 if (!intel_PLL_is_valid(dev
, limit
, &clock
))
874 /* based on hardware requirement, prefer bigger p
876 if (clock
.p
> best_clock
->p
) {
886 bool intel_crtc_active(struct drm_crtc
*crtc
)
888 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
890 /* Be paranoid as we can arrive here with only partial
891 * state retrieved from the hardware during setup.
893 * We can ditch the adjusted_mode.crtc_clock check as soon
894 * as Haswell has gained clock readout/fastboot support.
896 * We can ditch the crtc->primary->fb check as soon as we can
897 * properly reconstruct framebuffers.
899 return intel_crtc
->active
&& crtc
->primary
->fb
&&
900 intel_crtc
->config
->base
.adjusted_mode
.crtc_clock
;
903 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
906 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
907 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
909 return intel_crtc
->config
->cpu_transcoder
;
912 static bool pipe_dsl_stopped(struct drm_device
*dev
, enum pipe pipe
)
914 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
915 u32 reg
= PIPEDSL(pipe
);
920 line_mask
= DSL_LINEMASK_GEN2
;
922 line_mask
= DSL_LINEMASK_GEN3
;
924 line1
= I915_READ(reg
) & line_mask
;
926 line2
= I915_READ(reg
) & line_mask
;
928 return line1
== line2
;
932 * intel_wait_for_pipe_off - wait for pipe to turn off
933 * @crtc: crtc whose pipe to wait for
935 * After disabling a pipe, we can't wait for vblank in the usual way,
936 * spinning on the vblank interrupt status bit, since we won't actually
937 * see an interrupt when the pipe is disabled.
940 * wait for the pipe register state bit to turn off
943 * wait for the display line value to settle (it usually
944 * ends up stopping at the start of the next frame).
947 static void intel_wait_for_pipe_off(struct intel_crtc
*crtc
)
949 struct drm_device
*dev
= crtc
->base
.dev
;
950 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
951 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
952 enum pipe pipe
= crtc
->pipe
;
954 if (INTEL_INFO(dev
)->gen
>= 4) {
955 int reg
= PIPECONF(cpu_transcoder
);
957 /* Wait for the Pipe State to go off */
958 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
960 WARN(1, "pipe_off wait timed out\n");
962 /* Wait for the display line to settle */
963 if (wait_for(pipe_dsl_stopped(dev
, pipe
), 100))
964 WARN(1, "pipe_off wait timed out\n");
969 * ibx_digital_port_connected - is the specified port connected?
970 * @dev_priv: i915 private structure
971 * @port: the port to test
973 * Returns true if @port is connected, false otherwise.
975 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
976 struct intel_digital_port
*port
)
980 if (HAS_PCH_IBX(dev_priv
->dev
)) {
981 switch (port
->port
) {
983 bit
= SDE_PORTB_HOTPLUG
;
986 bit
= SDE_PORTC_HOTPLUG
;
989 bit
= SDE_PORTD_HOTPLUG
;
995 switch (port
->port
) {
997 bit
= SDE_PORTB_HOTPLUG_CPT
;
1000 bit
= SDE_PORTC_HOTPLUG_CPT
;
1003 bit
= SDE_PORTD_HOTPLUG_CPT
;
1010 return I915_READ(SDEISR
) & bit
;
1013 static const char *state_string(bool enabled
)
1015 return enabled
? "on" : "off";
1018 /* Only for pre-ILK configs */
1019 void assert_pll(struct drm_i915_private
*dev_priv
,
1020 enum pipe pipe
, bool state
)
1027 val
= I915_READ(reg
);
1028 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1029 I915_STATE_WARN(cur_state
!= state
,
1030 "PLL state assertion failure (expected %s, current %s)\n",
1031 state_string(state
), state_string(cur_state
));
1034 /* XXX: the dsi pll is shared between MIPI DSI ports */
1035 static void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
)
1040 mutex_lock(&dev_priv
->dpio_lock
);
1041 val
= vlv_cck_read(dev_priv
, CCK_REG_DSI_PLL_CONTROL
);
1042 mutex_unlock(&dev_priv
->dpio_lock
);
1044 cur_state
= val
& DSI_PLL_VCO_EN
;
1045 I915_STATE_WARN(cur_state
!= state
,
1046 "DSI PLL state assertion failure (expected %s, current %s)\n",
1047 state_string(state
), state_string(cur_state
));
1049 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1050 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1052 struct intel_shared_dpll
*
1053 intel_crtc_to_shared_dpll(struct intel_crtc
*crtc
)
1055 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1057 if (crtc
->config
->shared_dpll
< 0)
1060 return &dev_priv
->shared_dplls
[crtc
->config
->shared_dpll
];
1064 void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
1065 struct intel_shared_dpll
*pll
,
1069 struct intel_dpll_hw_state hw_state
;
1072 "asserting DPLL %s with no DPLL\n", state_string(state
)))
1075 cur_state
= pll
->get_hw_state(dev_priv
, pll
, &hw_state
);
1076 I915_STATE_WARN(cur_state
!= state
,
1077 "%s assertion failure (expected %s, current %s)\n",
1078 pll
->name
, state_string(state
), state_string(cur_state
));
1081 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1082 enum pipe pipe
, bool state
)
1087 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1090 if (HAS_DDI(dev_priv
->dev
)) {
1091 /* DDI does not have a specific FDI_TX register */
1092 reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1093 val
= I915_READ(reg
);
1094 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
1096 reg
= FDI_TX_CTL(pipe
);
1097 val
= I915_READ(reg
);
1098 cur_state
= !!(val
& FDI_TX_ENABLE
);
1100 I915_STATE_WARN(cur_state
!= state
,
1101 "FDI TX state assertion failure (expected %s, current %s)\n",
1102 state_string(state
), state_string(cur_state
));
1104 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1105 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1107 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1108 enum pipe pipe
, bool state
)
1114 reg
= FDI_RX_CTL(pipe
);
1115 val
= I915_READ(reg
);
1116 cur_state
= !!(val
& FDI_RX_ENABLE
);
1117 I915_STATE_WARN(cur_state
!= state
,
1118 "FDI RX state assertion failure (expected %s, current %s)\n",
1119 state_string(state
), state_string(cur_state
));
1121 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1122 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1124 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1130 /* ILK FDI PLL is always enabled */
1131 if (INTEL_INFO(dev_priv
->dev
)->gen
== 5)
1134 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1135 if (HAS_DDI(dev_priv
->dev
))
1138 reg
= FDI_TX_CTL(pipe
);
1139 val
= I915_READ(reg
);
1140 I915_STATE_WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1143 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1144 enum pipe pipe
, bool state
)
1150 reg
= FDI_RX_CTL(pipe
);
1151 val
= I915_READ(reg
);
1152 cur_state
= !!(val
& FDI_RX_PLL_ENABLE
);
1153 I915_STATE_WARN(cur_state
!= state
,
1154 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1155 state_string(state
), state_string(cur_state
));
1158 void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1161 struct drm_device
*dev
= dev_priv
->dev
;
1164 enum pipe panel_pipe
= PIPE_A
;
1167 if (WARN_ON(HAS_DDI(dev
)))
1170 if (HAS_PCH_SPLIT(dev
)) {
1173 pp_reg
= PCH_PP_CONTROL
;
1174 port_sel
= I915_READ(PCH_PP_ON_DELAYS
) & PANEL_PORT_SELECT_MASK
;
1176 if (port_sel
== PANEL_PORT_SELECT_LVDS
&&
1177 I915_READ(PCH_LVDS
) & LVDS_PIPEB_SELECT
)
1178 panel_pipe
= PIPE_B
;
1179 /* XXX: else fix for eDP */
1180 } else if (IS_VALLEYVIEW(dev
)) {
1181 /* presumably write lock depends on pipe, not port select */
1182 pp_reg
= VLV_PIPE_PP_CONTROL(pipe
);
1185 pp_reg
= PP_CONTROL
;
1186 if (I915_READ(LVDS
) & LVDS_PIPEB_SELECT
)
1187 panel_pipe
= PIPE_B
;
1190 val
= I915_READ(pp_reg
);
1191 if (!(val
& PANEL_POWER_ON
) ||
1192 ((val
& PANEL_UNLOCK_MASK
) == PANEL_UNLOCK_REGS
))
1195 I915_STATE_WARN(panel_pipe
== pipe
&& locked
,
1196 "panel assertion failure, pipe %c regs locked\n",
1200 static void assert_cursor(struct drm_i915_private
*dev_priv
,
1201 enum pipe pipe
, bool state
)
1203 struct drm_device
*dev
= dev_priv
->dev
;
1206 if (IS_845G(dev
) || IS_I865G(dev
))
1207 cur_state
= I915_READ(_CURACNTR
) & CURSOR_ENABLE
;
1209 cur_state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
1211 I915_STATE_WARN(cur_state
!= state
,
1212 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1213 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1215 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1216 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1218 void assert_pipe(struct drm_i915_private
*dev_priv
,
1219 enum pipe pipe
, bool state
)
1224 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1227 /* if we need the pipe quirk it must be always on */
1228 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1229 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1232 if (!intel_display_power_is_enabled(dev_priv
,
1233 POWER_DOMAIN_TRANSCODER(cpu_transcoder
))) {
1236 reg
= PIPECONF(cpu_transcoder
);
1237 val
= I915_READ(reg
);
1238 cur_state
= !!(val
& PIPECONF_ENABLE
);
1241 I915_STATE_WARN(cur_state
!= state
,
1242 "pipe %c assertion failure (expected %s, current %s)\n",
1243 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1246 static void assert_plane(struct drm_i915_private
*dev_priv
,
1247 enum plane plane
, bool state
)
1253 reg
= DSPCNTR(plane
);
1254 val
= I915_READ(reg
);
1255 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1256 I915_STATE_WARN(cur_state
!= state
,
1257 "plane %c assertion failure (expected %s, current %s)\n",
1258 plane_name(plane
), state_string(state
), state_string(cur_state
));
1261 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1262 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1264 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1267 struct drm_device
*dev
= dev_priv
->dev
;
1272 /* Primary planes are fixed to pipes on gen4+ */
1273 if (INTEL_INFO(dev
)->gen
>= 4) {
1274 reg
= DSPCNTR(pipe
);
1275 val
= I915_READ(reg
);
1276 I915_STATE_WARN(val
& DISPLAY_PLANE_ENABLE
,
1277 "plane %c assertion failure, should be disabled but not\n",
1282 /* Need to check both planes against the pipe */
1283 for_each_pipe(dev_priv
, i
) {
1285 val
= I915_READ(reg
);
1286 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1287 DISPPLANE_SEL_PIPE_SHIFT
;
1288 I915_STATE_WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1289 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1290 plane_name(i
), pipe_name(pipe
));
1294 static void assert_sprites_disabled(struct drm_i915_private
*dev_priv
,
1297 struct drm_device
*dev
= dev_priv
->dev
;
1301 if (INTEL_INFO(dev
)->gen
>= 9) {
1302 for_each_sprite(pipe
, sprite
) {
1303 val
= I915_READ(PLANE_CTL(pipe
, sprite
));
1304 I915_STATE_WARN(val
& PLANE_CTL_ENABLE
,
1305 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1306 sprite
, pipe_name(pipe
));
1308 } else if (IS_VALLEYVIEW(dev
)) {
1309 for_each_sprite(pipe
, sprite
) {
1310 reg
= SPCNTR(pipe
, sprite
);
1311 val
= I915_READ(reg
);
1312 I915_STATE_WARN(val
& SP_ENABLE
,
1313 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1314 sprite_name(pipe
, sprite
), pipe_name(pipe
));
1316 } else if (INTEL_INFO(dev
)->gen
>= 7) {
1318 val
= I915_READ(reg
);
1319 I915_STATE_WARN(val
& SPRITE_ENABLE
,
1320 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1321 plane_name(pipe
), pipe_name(pipe
));
1322 } else if (INTEL_INFO(dev
)->gen
>= 5) {
1323 reg
= DVSCNTR(pipe
);
1324 val
= I915_READ(reg
);
1325 I915_STATE_WARN(val
& DVS_ENABLE
,
1326 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1327 plane_name(pipe
), pipe_name(pipe
));
1331 static void assert_vblank_disabled(struct drm_crtc
*crtc
)
1333 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc
) == 0))
1334 drm_crtc_vblank_put(crtc
);
1337 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1342 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv
->dev
) || HAS_PCH_CPT(dev_priv
->dev
)));
1344 val
= I915_READ(PCH_DREF_CONTROL
);
1345 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1346 DREF_SUPERSPREAD_SOURCE_MASK
));
1347 I915_STATE_WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1350 static void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1357 reg
= PCH_TRANSCONF(pipe
);
1358 val
= I915_READ(reg
);
1359 enabled
= !!(val
& TRANS_ENABLE
);
1360 I915_STATE_WARN(enabled
,
1361 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1365 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1366 enum pipe pipe
, u32 port_sel
, u32 val
)
1368 if ((val
& DP_PORT_EN
) == 0)
1371 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1372 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1373 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1374 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1376 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1377 if ((val
& DP_PIPE_MASK_CHV
) != DP_PIPE_SELECT_CHV(pipe
))
1380 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1386 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1387 enum pipe pipe
, u32 val
)
1389 if ((val
& SDVO_ENABLE
) == 0)
1392 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1393 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1395 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1396 if ((val
& SDVO_PIPE_SEL_MASK_CHV
) != SDVO_PIPE_SEL_CHV(pipe
))
1399 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1405 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1406 enum pipe pipe
, u32 val
)
1408 if ((val
& LVDS_PORT_EN
) == 0)
1411 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1412 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1415 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1421 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1422 enum pipe pipe
, u32 val
)
1424 if ((val
& ADPA_DAC_ENABLE
) == 0)
1426 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1427 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1430 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1436 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1437 enum pipe pipe
, int reg
, u32 port_sel
)
1439 u32 val
= I915_READ(reg
);
1440 I915_STATE_WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1441 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1442 reg
, pipe_name(pipe
));
1444 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& DP_PORT_EN
) == 0
1445 && (val
& DP_PIPEB_SELECT
),
1446 "IBX PCH dp port still using transcoder B\n");
1449 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1450 enum pipe pipe
, int reg
)
1452 u32 val
= I915_READ(reg
);
1453 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1454 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1455 reg
, pipe_name(pipe
));
1457 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& SDVO_ENABLE
) == 0
1458 && (val
& SDVO_PIPE_B_SELECT
),
1459 "IBX PCH hdmi port still using transcoder B\n");
1462 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1468 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1469 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1470 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1473 val
= I915_READ(reg
);
1474 I915_STATE_WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1475 "PCH VGA enabled on transcoder %c, should be disabled\n",
1479 val
= I915_READ(reg
);
1480 I915_STATE_WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1481 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1484 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1485 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1486 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1489 static void intel_init_dpio(struct drm_device
*dev
)
1491 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1493 if (!IS_VALLEYVIEW(dev
))
1497 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1498 * CHV x1 PHY (DP/HDMI D)
1499 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1501 if (IS_CHERRYVIEW(dev
)) {
1502 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO_2
;
1503 DPIO_PHY_IOSF_PORT(DPIO_PHY1
) = IOSF_PORT_DPIO
;
1505 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO
;
1509 static void vlv_enable_pll(struct intel_crtc
*crtc
,
1510 const struct intel_crtc_state
*pipe_config
)
1512 struct drm_device
*dev
= crtc
->base
.dev
;
1513 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1514 int reg
= DPLL(crtc
->pipe
);
1515 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
1517 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1519 /* No really, not for ILK+ */
1520 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
));
1522 /* PLL is protected by panel, make sure we can write it */
1523 if (IS_MOBILE(dev_priv
->dev
))
1524 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1526 I915_WRITE(reg
, dpll
);
1530 if (wait_for(((I915_READ(reg
) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1531 DRM_ERROR("DPLL %d failed to lock\n", crtc
->pipe
);
1533 I915_WRITE(DPLL_MD(crtc
->pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1534 POSTING_READ(DPLL_MD(crtc
->pipe
));
1536 /* We do this three times for luck */
1537 I915_WRITE(reg
, dpll
);
1539 udelay(150); /* wait for warmup */
1540 I915_WRITE(reg
, dpll
);
1542 udelay(150); /* wait for warmup */
1543 I915_WRITE(reg
, dpll
);
1545 udelay(150); /* wait for warmup */
1548 static void chv_enable_pll(struct intel_crtc
*crtc
,
1549 const struct intel_crtc_state
*pipe_config
)
1551 struct drm_device
*dev
= crtc
->base
.dev
;
1552 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1553 int pipe
= crtc
->pipe
;
1554 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1557 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1559 BUG_ON(!IS_CHERRYVIEW(dev_priv
->dev
));
1561 mutex_lock(&dev_priv
->dpio_lock
);
1563 /* Enable back the 10bit clock to display controller */
1564 tmp
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1565 tmp
|= DPIO_DCLKP_EN
;
1566 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), tmp
);
1569 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1574 I915_WRITE(DPLL(pipe
), pipe_config
->dpll_hw_state
.dpll
);
1576 /* Check PLL is locked */
1577 if (wait_for(((I915_READ(DPLL(pipe
)) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1578 DRM_ERROR("PLL %d failed to lock\n", pipe
);
1580 /* not sure when this should be written */
1581 I915_WRITE(DPLL_MD(pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1582 POSTING_READ(DPLL_MD(pipe
));
1584 mutex_unlock(&dev_priv
->dpio_lock
);
1587 static int intel_num_dvo_pipes(struct drm_device
*dev
)
1589 struct intel_crtc
*crtc
;
1592 for_each_intel_crtc(dev
, crtc
)
1593 count
+= crtc
->active
&&
1594 intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
);
1599 static void i9xx_enable_pll(struct intel_crtc
*crtc
)
1601 struct drm_device
*dev
= crtc
->base
.dev
;
1602 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1603 int reg
= DPLL(crtc
->pipe
);
1604 u32 dpll
= crtc
->config
->dpll_hw_state
.dpll
;
1606 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1608 /* No really, not for ILK+ */
1609 BUG_ON(INTEL_INFO(dev
)->gen
>= 5);
1611 /* PLL is protected by panel, make sure we can write it */
1612 if (IS_MOBILE(dev
) && !IS_I830(dev
))
1613 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1615 /* Enable DVO 2x clock on both PLLs if necessary */
1616 if (IS_I830(dev
) && intel_num_dvo_pipes(dev
) > 0) {
1618 * It appears to be important that we don't enable this
1619 * for the current pipe before otherwise configuring the
1620 * PLL. No idea how this should be handled if multiple
1621 * DVO outputs are enabled simultaneosly.
1623 dpll
|= DPLL_DVO_2X_MODE
;
1624 I915_WRITE(DPLL(!crtc
->pipe
),
1625 I915_READ(DPLL(!crtc
->pipe
)) | DPLL_DVO_2X_MODE
);
1628 /* Wait for the clocks to stabilize. */
1632 if (INTEL_INFO(dev
)->gen
>= 4) {
1633 I915_WRITE(DPLL_MD(crtc
->pipe
),
1634 crtc
->config
->dpll_hw_state
.dpll_md
);
1636 /* The pixel multiplier can only be updated once the
1637 * DPLL is enabled and the clocks are stable.
1639 * So write it again.
1641 I915_WRITE(reg
, dpll
);
1644 /* We do this three times for luck */
1645 I915_WRITE(reg
, dpll
);
1647 udelay(150); /* wait for warmup */
1648 I915_WRITE(reg
, dpll
);
1650 udelay(150); /* wait for warmup */
1651 I915_WRITE(reg
, dpll
);
1653 udelay(150); /* wait for warmup */
1657 * i9xx_disable_pll - disable a PLL
1658 * @dev_priv: i915 private structure
1659 * @pipe: pipe PLL to disable
1661 * Disable the PLL for @pipe, making sure the pipe is off first.
1663 * Note! This is for pre-ILK only.
1665 static void i9xx_disable_pll(struct intel_crtc
*crtc
)
1667 struct drm_device
*dev
= crtc
->base
.dev
;
1668 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1669 enum pipe pipe
= crtc
->pipe
;
1671 /* Disable DVO 2x clock on both PLLs if necessary */
1673 intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
) &&
1674 intel_num_dvo_pipes(dev
) == 1) {
1675 I915_WRITE(DPLL(PIPE_B
),
1676 I915_READ(DPLL(PIPE_B
)) & ~DPLL_DVO_2X_MODE
);
1677 I915_WRITE(DPLL(PIPE_A
),
1678 I915_READ(DPLL(PIPE_A
)) & ~DPLL_DVO_2X_MODE
);
1681 /* Don't disable pipe or pipe PLLs if needed */
1682 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1683 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1686 /* Make sure the pipe isn't still relying on us */
1687 assert_pipe_disabled(dev_priv
, pipe
);
1689 I915_WRITE(DPLL(pipe
), 0);
1690 POSTING_READ(DPLL(pipe
));
1693 static void vlv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1697 /* Make sure the pipe isn't still relying on us */
1698 assert_pipe_disabled(dev_priv
, pipe
);
1701 * Leave integrated clock source and reference clock enabled for pipe B.
1702 * The latter is needed for VGA hotplug / manual detection.
1705 val
= DPLL_INTEGRATED_CRI_CLK_VLV
| DPLL_REFA_CLK_ENABLE_VLV
;
1706 I915_WRITE(DPLL(pipe
), val
);
1707 POSTING_READ(DPLL(pipe
));
1711 static void chv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1713 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1716 /* Make sure the pipe isn't still relying on us */
1717 assert_pipe_disabled(dev_priv
, pipe
);
1719 /* Set PLL en = 0 */
1720 val
= DPLL_SSC_REF_CLOCK_CHV
| DPLL_REFA_CLK_ENABLE_VLV
;
1722 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
1723 I915_WRITE(DPLL(pipe
), val
);
1724 POSTING_READ(DPLL(pipe
));
1726 mutex_lock(&dev_priv
->dpio_lock
);
1728 /* Disable 10bit clock to display controller */
1729 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1730 val
&= ~DPIO_DCLKP_EN
;
1731 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), val
);
1733 /* disable left/right clock distribution */
1734 if (pipe
!= PIPE_B
) {
1735 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
);
1736 val
&= ~(CHV_BUFLEFTENA1_MASK
| CHV_BUFRIGHTENA1_MASK
);
1737 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
, val
);
1739 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
);
1740 val
&= ~(CHV_BUFLEFTENA2_MASK
| CHV_BUFRIGHTENA2_MASK
);
1741 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
, val
);
1744 mutex_unlock(&dev_priv
->dpio_lock
);
1747 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1748 struct intel_digital_port
*dport
)
1753 switch (dport
->port
) {
1755 port_mask
= DPLL_PORTB_READY_MASK
;
1759 port_mask
= DPLL_PORTC_READY_MASK
;
1763 port_mask
= DPLL_PORTD_READY_MASK
;
1764 dpll_reg
= DPIO_PHY_STATUS
;
1770 if (wait_for((I915_READ(dpll_reg
) & port_mask
) == 0, 1000))
1771 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1772 port_name(dport
->port
), I915_READ(dpll_reg
));
1775 static void intel_prepare_shared_dpll(struct intel_crtc
*crtc
)
1777 struct drm_device
*dev
= crtc
->base
.dev
;
1778 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1779 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1781 if (WARN_ON(pll
== NULL
))
1784 WARN_ON(!pll
->config
.crtc_mask
);
1785 if (pll
->active
== 0) {
1786 DRM_DEBUG_DRIVER("setting up %s\n", pll
->name
);
1788 assert_shared_dpll_disabled(dev_priv
, pll
);
1790 pll
->mode_set(dev_priv
, pll
);
1795 * intel_enable_shared_dpll - enable PCH PLL
1796 * @dev_priv: i915 private structure
1797 * @pipe: pipe PLL to enable
1799 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1800 * drives the transcoder clock.
1802 static void intel_enable_shared_dpll(struct intel_crtc
*crtc
)
1804 struct drm_device
*dev
= crtc
->base
.dev
;
1805 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1806 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1808 if (WARN_ON(pll
== NULL
))
1811 if (WARN_ON(pll
->config
.crtc_mask
== 0))
1814 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1815 pll
->name
, pll
->active
, pll
->on
,
1816 crtc
->base
.base
.id
);
1818 if (pll
->active
++) {
1820 assert_shared_dpll_enabled(dev_priv
, pll
);
1825 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
1827 DRM_DEBUG_KMS("enabling %s\n", pll
->name
);
1828 pll
->enable(dev_priv
, pll
);
1832 static void intel_disable_shared_dpll(struct intel_crtc
*crtc
)
1834 struct drm_device
*dev
= crtc
->base
.dev
;
1835 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1836 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1838 /* PCH only available on ILK+ */
1839 BUG_ON(INTEL_INFO(dev
)->gen
< 5);
1840 if (WARN_ON(pll
== NULL
))
1843 if (WARN_ON(pll
->config
.crtc_mask
== 0))
1846 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1847 pll
->name
, pll
->active
, pll
->on
,
1848 crtc
->base
.base
.id
);
1850 if (WARN_ON(pll
->active
== 0)) {
1851 assert_shared_dpll_disabled(dev_priv
, pll
);
1855 assert_shared_dpll_enabled(dev_priv
, pll
);
1860 DRM_DEBUG_KMS("disabling %s\n", pll
->name
);
1861 pll
->disable(dev_priv
, pll
);
1864 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
1867 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1870 struct drm_device
*dev
= dev_priv
->dev
;
1871 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1872 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1873 uint32_t reg
, val
, pipeconf_val
;
1875 /* PCH only available on ILK+ */
1876 BUG_ON(!HAS_PCH_SPLIT(dev
));
1878 /* Make sure PCH DPLL is enabled */
1879 assert_shared_dpll_enabled(dev_priv
,
1880 intel_crtc_to_shared_dpll(intel_crtc
));
1882 /* FDI must be feeding us bits for PCH ports */
1883 assert_fdi_tx_enabled(dev_priv
, pipe
);
1884 assert_fdi_rx_enabled(dev_priv
, pipe
);
1886 if (HAS_PCH_CPT(dev
)) {
1887 /* Workaround: Set the timing override bit before enabling the
1888 * pch transcoder. */
1889 reg
= TRANS_CHICKEN2(pipe
);
1890 val
= I915_READ(reg
);
1891 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1892 I915_WRITE(reg
, val
);
1895 reg
= PCH_TRANSCONF(pipe
);
1896 val
= I915_READ(reg
);
1897 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1899 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1901 * make the BPC in transcoder be consistent with
1902 * that in pipeconf reg.
1904 val
&= ~PIPECONF_BPC_MASK
;
1905 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
1908 val
&= ~TRANS_INTERLACE_MASK
;
1909 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1910 if (HAS_PCH_IBX(dev_priv
->dev
) &&
1911 intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
1912 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1914 val
|= TRANS_INTERLACED
;
1916 val
|= TRANS_PROGRESSIVE
;
1918 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1919 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1920 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
1923 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1924 enum transcoder cpu_transcoder
)
1926 u32 val
, pipeconf_val
;
1928 /* PCH only available on ILK+ */
1929 BUG_ON(!HAS_PCH_SPLIT(dev_priv
->dev
));
1931 /* FDI must be feeding us bits for PCH ports */
1932 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
1933 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
1935 /* Workaround: set timing override bit. */
1936 val
= I915_READ(_TRANSA_CHICKEN2
);
1937 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1938 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1941 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
1943 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
1944 PIPECONF_INTERLACED_ILK
)
1945 val
|= TRANS_INTERLACED
;
1947 val
|= TRANS_PROGRESSIVE
;
1949 I915_WRITE(LPT_TRANSCONF
, val
);
1950 if (wait_for(I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
, 100))
1951 DRM_ERROR("Failed to enable PCH transcoder\n");
1954 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1957 struct drm_device
*dev
= dev_priv
->dev
;
1960 /* FDI relies on the transcoder */
1961 assert_fdi_tx_disabled(dev_priv
, pipe
);
1962 assert_fdi_rx_disabled(dev_priv
, pipe
);
1964 /* Ports must be off as well */
1965 assert_pch_ports_disabled(dev_priv
, pipe
);
1967 reg
= PCH_TRANSCONF(pipe
);
1968 val
= I915_READ(reg
);
1969 val
&= ~TRANS_ENABLE
;
1970 I915_WRITE(reg
, val
);
1971 /* wait for PCH transcoder off, transcoder state */
1972 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
1973 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
1975 if (!HAS_PCH_IBX(dev
)) {
1976 /* Workaround: Clear the timing override chicken bit again. */
1977 reg
= TRANS_CHICKEN2(pipe
);
1978 val
= I915_READ(reg
);
1979 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1980 I915_WRITE(reg
, val
);
1984 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
1988 val
= I915_READ(LPT_TRANSCONF
);
1989 val
&= ~TRANS_ENABLE
;
1990 I915_WRITE(LPT_TRANSCONF
, val
);
1991 /* wait for PCH transcoder off, transcoder state */
1992 if (wait_for((I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
) == 0, 50))
1993 DRM_ERROR("Failed to disable PCH transcoder\n");
1995 /* Workaround: clear timing override bit. */
1996 val
= I915_READ(_TRANSA_CHICKEN2
);
1997 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1998 I915_WRITE(_TRANSA_CHICKEN2
, val
);
2002 * intel_enable_pipe - enable a pipe, asserting requirements
2003 * @crtc: crtc responsible for the pipe
2005 * Enable @crtc's pipe, making sure that various hardware specific requirements
2006 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2008 static void intel_enable_pipe(struct intel_crtc
*crtc
)
2010 struct drm_device
*dev
= crtc
->base
.dev
;
2011 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2012 enum pipe pipe
= crtc
->pipe
;
2013 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
2015 enum pipe pch_transcoder
;
2019 assert_planes_disabled(dev_priv
, pipe
);
2020 assert_cursor_disabled(dev_priv
, pipe
);
2021 assert_sprites_disabled(dev_priv
, pipe
);
2023 if (HAS_PCH_LPT(dev_priv
->dev
))
2024 pch_transcoder
= TRANSCODER_A
;
2026 pch_transcoder
= pipe
;
2029 * A pipe without a PLL won't actually be able to drive bits from
2030 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2033 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
2034 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
))
2035 assert_dsi_pll_enabled(dev_priv
);
2037 assert_pll_enabled(dev_priv
, pipe
);
2039 if (crtc
->config
->has_pch_encoder
) {
2040 /* if driving the PCH, we need FDI enabled */
2041 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
2042 assert_fdi_tx_pll_enabled(dev_priv
,
2043 (enum pipe
) cpu_transcoder
);
2045 /* FIXME: assert CPU port conditions for SNB+ */
2048 reg
= PIPECONF(cpu_transcoder
);
2049 val
= I915_READ(reg
);
2050 if (val
& PIPECONF_ENABLE
) {
2051 WARN_ON(!((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
2052 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
)));
2056 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
2061 * intel_disable_pipe - disable a pipe, asserting requirements
2062 * @crtc: crtc whose pipes is to be disabled
2064 * Disable the pipe of @crtc, making sure that various hardware
2065 * specific requirements are met, if applicable, e.g. plane
2066 * disabled, panel fitter off, etc.
2068 * Will wait until the pipe has shut down before returning.
2070 static void intel_disable_pipe(struct intel_crtc
*crtc
)
2072 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
2073 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
2074 enum pipe pipe
= crtc
->pipe
;
2079 * Make sure planes won't keep trying to pump pixels to us,
2080 * or we might hang the display.
2082 assert_planes_disabled(dev_priv
, pipe
);
2083 assert_cursor_disabled(dev_priv
, pipe
);
2084 assert_sprites_disabled(dev_priv
, pipe
);
2086 reg
= PIPECONF(cpu_transcoder
);
2087 val
= I915_READ(reg
);
2088 if ((val
& PIPECONF_ENABLE
) == 0)
2092 * Double wide has implications for planes
2093 * so best keep it disabled when not needed.
2095 if (crtc
->config
->double_wide
)
2096 val
&= ~PIPECONF_DOUBLE_WIDE
;
2098 /* Don't disable pipe or pipe PLLs if needed */
2099 if (!(pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) &&
2100 !(pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
2101 val
&= ~PIPECONF_ENABLE
;
2103 I915_WRITE(reg
, val
);
2104 if ((val
& PIPECONF_ENABLE
) == 0)
2105 intel_wait_for_pipe_off(crtc
);
2109 * Plane regs are double buffered, going from enabled->disabled needs a
2110 * trigger in order to latch. The display address reg provides this.
2112 void intel_flush_primary_plane(struct drm_i915_private
*dev_priv
,
2115 struct drm_device
*dev
= dev_priv
->dev
;
2116 u32 reg
= INTEL_INFO(dev
)->gen
>= 4 ? DSPSURF(plane
) : DSPADDR(plane
);
2118 I915_WRITE(reg
, I915_READ(reg
));
2123 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2124 * @plane: plane to be enabled
2125 * @crtc: crtc for the plane
2127 * Enable @plane on @crtc, making sure that the pipe is running first.
2129 static void intel_enable_primary_hw_plane(struct drm_plane
*plane
,
2130 struct drm_crtc
*crtc
)
2132 struct drm_device
*dev
= plane
->dev
;
2133 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2134 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2136 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2137 assert_pipe_enabled(dev_priv
, intel_crtc
->pipe
);
2139 if (intel_crtc
->primary_enabled
)
2142 intel_crtc
->primary_enabled
= true;
2144 dev_priv
->display
.update_primary_plane(crtc
, plane
->fb
,
2148 * BDW signals flip done immediately if the plane
2149 * is disabled, even if the plane enable is already
2150 * armed to occur at the next vblank :(
2152 if (IS_BROADWELL(dev
))
2153 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2157 * intel_disable_primary_hw_plane - disable the primary hardware plane
2158 * @plane: plane to be disabled
2159 * @crtc: crtc for the plane
2161 * Disable @plane on @crtc, making sure that the pipe is running first.
2163 static void intel_disable_primary_hw_plane(struct drm_plane
*plane
,
2164 struct drm_crtc
*crtc
)
2166 struct drm_device
*dev
= plane
->dev
;
2167 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2168 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2170 if (WARN_ON(!intel_crtc
->active
))
2173 if (!intel_crtc
->primary_enabled
)
2176 intel_crtc
->primary_enabled
= false;
2178 dev_priv
->display
.update_primary_plane(crtc
, plane
->fb
,
2182 static bool need_vtd_wa(struct drm_device
*dev
)
2184 #ifdef CONFIG_INTEL_IOMMU
2185 if (INTEL_INFO(dev
)->gen
>= 6 && intel_iommu_gfx_mapped
)
2192 intel_fb_align_height(struct drm_device
*dev
, int height
, unsigned int tiling
)
2196 tile_height
= tiling
? (IS_GEN2(dev
) ? 16 : 8) : 1;
2197 return ALIGN(height
, tile_height
);
2201 intel_pin_and_fence_fb_obj(struct drm_plane
*plane
,
2202 struct drm_framebuffer
*fb
,
2203 struct intel_engine_cs
*pipelined
)
2205 struct drm_device
*dev
= fb
->dev
;
2206 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2207 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2211 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
2213 switch (obj
->tiling_mode
) {
2214 case I915_TILING_NONE
:
2215 if (INTEL_INFO(dev
)->gen
>= 9)
2216 alignment
= 256 * 1024;
2217 else if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
2218 alignment
= 128 * 1024;
2219 else if (INTEL_INFO(dev
)->gen
>= 4)
2220 alignment
= 4 * 1024;
2222 alignment
= 64 * 1024;
2225 if (INTEL_INFO(dev
)->gen
>= 9)
2226 alignment
= 256 * 1024;
2228 /* pin() will align the object as required by fence */
2233 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2239 /* Note that the w/a also requires 64 PTE of padding following the
2240 * bo. We currently fill all unused PTE with the shadow page and so
2241 * we should always have valid PTE following the scanout preventing
2244 if (need_vtd_wa(dev
) && alignment
< 256 * 1024)
2245 alignment
= 256 * 1024;
2248 * Global gtt pte registers are special registers which actually forward
2249 * writes to a chunk of system memory. Which means that there is no risk
2250 * that the register values disappear as soon as we call
2251 * intel_runtime_pm_put(), so it is correct to wrap only the
2252 * pin/unpin/fence and not more.
2254 intel_runtime_pm_get(dev_priv
);
2256 dev_priv
->mm
.interruptible
= false;
2257 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
);
2259 goto err_interruptible
;
2261 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2262 * fence, whereas 965+ only requires a fence if using
2263 * framebuffer compression. For simplicity, we always install
2264 * a fence as the cost is not that onerous.
2266 ret
= i915_gem_object_get_fence(obj
);
2270 i915_gem_object_pin_fence(obj
);
2272 dev_priv
->mm
.interruptible
= true;
2273 intel_runtime_pm_put(dev_priv
);
2277 i915_gem_object_unpin_from_display_plane(obj
);
2279 dev_priv
->mm
.interruptible
= true;
2280 intel_runtime_pm_put(dev_priv
);
2284 void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
)
2286 WARN_ON(!mutex_is_locked(&obj
->base
.dev
->struct_mutex
));
2288 i915_gem_object_unpin_fence(obj
);
2289 i915_gem_object_unpin_from_display_plane(obj
);
2292 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2293 * is assumed to be a power-of-two. */
2294 unsigned long intel_gen4_compute_page_offset(int *x
, int *y
,
2295 unsigned int tiling_mode
,
2299 if (tiling_mode
!= I915_TILING_NONE
) {
2300 unsigned int tile_rows
, tiles
;
2305 tiles
= *x
/ (512/cpp
);
2308 return tile_rows
* pitch
* 8 + tiles
* 4096;
2310 unsigned int offset
;
2312 offset
= *y
* pitch
+ *x
* cpp
;
2314 *x
= (offset
& 4095) / cpp
;
2315 return offset
& -4096;
2319 static int i9xx_format_to_fourcc(int format
)
2322 case DISPPLANE_8BPP
:
2323 return DRM_FORMAT_C8
;
2324 case DISPPLANE_BGRX555
:
2325 return DRM_FORMAT_XRGB1555
;
2326 case DISPPLANE_BGRX565
:
2327 return DRM_FORMAT_RGB565
;
2329 case DISPPLANE_BGRX888
:
2330 return DRM_FORMAT_XRGB8888
;
2331 case DISPPLANE_RGBX888
:
2332 return DRM_FORMAT_XBGR8888
;
2333 case DISPPLANE_BGRX101010
:
2334 return DRM_FORMAT_XRGB2101010
;
2335 case DISPPLANE_RGBX101010
:
2336 return DRM_FORMAT_XBGR2101010
;
2340 static int skl_format_to_fourcc(int format
, bool rgb_order
, bool alpha
)
2343 case PLANE_CTL_FORMAT_RGB_565
:
2344 return DRM_FORMAT_RGB565
;
2346 case PLANE_CTL_FORMAT_XRGB_8888
:
2349 return DRM_FORMAT_ABGR8888
;
2351 return DRM_FORMAT_XBGR8888
;
2354 return DRM_FORMAT_ARGB8888
;
2356 return DRM_FORMAT_XRGB8888
;
2358 case PLANE_CTL_FORMAT_XRGB_2101010
:
2360 return DRM_FORMAT_XBGR2101010
;
2362 return DRM_FORMAT_XRGB2101010
;
2367 intel_alloc_plane_obj(struct intel_crtc
*crtc
,
2368 struct intel_initial_plane_config
*plane_config
)
2370 struct drm_device
*dev
= crtc
->base
.dev
;
2371 struct drm_i915_gem_object
*obj
= NULL
;
2372 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
2373 u32 base
= plane_config
->base
;
2375 if (plane_config
->size
== 0)
2378 obj
= i915_gem_object_create_stolen_for_preallocated(dev
, base
, base
,
2379 plane_config
->size
);
2383 obj
->tiling_mode
= plane_config
->tiling
;
2384 if (obj
->tiling_mode
== I915_TILING_X
)
2385 obj
->stride
= crtc
->base
.primary
->fb
->pitches
[0];
2387 mode_cmd
.pixel_format
= crtc
->base
.primary
->fb
->pixel_format
;
2388 mode_cmd
.width
= crtc
->base
.primary
->fb
->width
;
2389 mode_cmd
.height
= crtc
->base
.primary
->fb
->height
;
2390 mode_cmd
.pitches
[0] = crtc
->base
.primary
->fb
->pitches
[0];
2392 mutex_lock(&dev
->struct_mutex
);
2394 if (intel_framebuffer_init(dev
, to_intel_framebuffer(crtc
->base
.primary
->fb
),
2396 DRM_DEBUG_KMS("intel fb init failed\n");
2400 obj
->frontbuffer_bits
= INTEL_FRONTBUFFER_PRIMARY(crtc
->pipe
);
2401 mutex_unlock(&dev
->struct_mutex
);
2403 DRM_DEBUG_KMS("plane fb obj %p\n", obj
);
2407 drm_gem_object_unreference(&obj
->base
);
2408 mutex_unlock(&dev
->struct_mutex
);
2413 intel_find_plane_obj(struct intel_crtc
*intel_crtc
,
2414 struct intel_initial_plane_config
*plane_config
)
2416 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2417 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2419 struct intel_crtc
*i
;
2420 struct drm_i915_gem_object
*obj
;
2422 if (!intel_crtc
->base
.primary
->fb
)
2425 if (intel_alloc_plane_obj(intel_crtc
, plane_config
))
2428 kfree(intel_crtc
->base
.primary
->fb
);
2429 intel_crtc
->base
.primary
->fb
= NULL
;
2432 * Failed to alloc the obj, check to see if we should share
2433 * an fb with another CRTC instead
2435 for_each_crtc(dev
, c
) {
2436 i
= to_intel_crtc(c
);
2438 if (c
== &intel_crtc
->base
)
2444 obj
= intel_fb_obj(c
->primary
->fb
);
2448 if (i915_gem_obj_ggtt_offset(obj
) == plane_config
->base
) {
2449 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2450 dev_priv
->preserve_bios_swizzle
= true;
2452 drm_framebuffer_reference(c
->primary
->fb
);
2453 intel_crtc
->base
.primary
->fb
= c
->primary
->fb
;
2454 obj
->frontbuffer_bits
|= INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
);
2460 static void i9xx_update_primary_plane(struct drm_crtc
*crtc
,
2461 struct drm_framebuffer
*fb
,
2464 struct drm_device
*dev
= crtc
->dev
;
2465 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2466 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2467 struct drm_i915_gem_object
*obj
;
2468 int plane
= intel_crtc
->plane
;
2469 unsigned long linear_offset
;
2471 u32 reg
= DSPCNTR(plane
);
2474 if (!intel_crtc
->primary_enabled
) {
2476 if (INTEL_INFO(dev
)->gen
>= 4)
2477 I915_WRITE(DSPSURF(plane
), 0);
2479 I915_WRITE(DSPADDR(plane
), 0);
2484 obj
= intel_fb_obj(fb
);
2485 if (WARN_ON(obj
== NULL
))
2488 pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2490 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2492 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2494 if (INTEL_INFO(dev
)->gen
< 4) {
2495 if (intel_crtc
->pipe
== PIPE_B
)
2496 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
2498 /* pipesrc and dspsize control the size that is scaled from,
2499 * which should always be the user's requested size.
2501 I915_WRITE(DSPSIZE(plane
),
2502 ((intel_crtc
->config
->pipe_src_h
- 1) << 16) |
2503 (intel_crtc
->config
->pipe_src_w
- 1));
2504 I915_WRITE(DSPPOS(plane
), 0);
2505 } else if (IS_CHERRYVIEW(dev
) && plane
== PLANE_B
) {
2506 I915_WRITE(PRIMSIZE(plane
),
2507 ((intel_crtc
->config
->pipe_src_h
- 1) << 16) |
2508 (intel_crtc
->config
->pipe_src_w
- 1));
2509 I915_WRITE(PRIMPOS(plane
), 0);
2510 I915_WRITE(PRIMCNSTALPHA(plane
), 0);
2513 switch (fb
->pixel_format
) {
2515 dspcntr
|= DISPPLANE_8BPP
;
2517 case DRM_FORMAT_XRGB1555
:
2518 case DRM_FORMAT_ARGB1555
:
2519 dspcntr
|= DISPPLANE_BGRX555
;
2521 case DRM_FORMAT_RGB565
:
2522 dspcntr
|= DISPPLANE_BGRX565
;
2524 case DRM_FORMAT_XRGB8888
:
2525 case DRM_FORMAT_ARGB8888
:
2526 dspcntr
|= DISPPLANE_BGRX888
;
2528 case DRM_FORMAT_XBGR8888
:
2529 case DRM_FORMAT_ABGR8888
:
2530 dspcntr
|= DISPPLANE_RGBX888
;
2532 case DRM_FORMAT_XRGB2101010
:
2533 case DRM_FORMAT_ARGB2101010
:
2534 dspcntr
|= DISPPLANE_BGRX101010
;
2536 case DRM_FORMAT_XBGR2101010
:
2537 case DRM_FORMAT_ABGR2101010
:
2538 dspcntr
|= DISPPLANE_RGBX101010
;
2544 if (INTEL_INFO(dev
)->gen
>= 4 &&
2545 obj
->tiling_mode
!= I915_TILING_NONE
)
2546 dspcntr
|= DISPPLANE_TILED
;
2549 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2551 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
2553 if (INTEL_INFO(dev
)->gen
>= 4) {
2554 intel_crtc
->dspaddr_offset
=
2555 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2558 linear_offset
-= intel_crtc
->dspaddr_offset
;
2560 intel_crtc
->dspaddr_offset
= linear_offset
;
2563 if (crtc
->primary
->state
->rotation
== BIT(DRM_ROTATE_180
)) {
2564 dspcntr
|= DISPPLANE_ROTATE_180
;
2566 x
+= (intel_crtc
->config
->pipe_src_w
- 1);
2567 y
+= (intel_crtc
->config
->pipe_src_h
- 1);
2569 /* Finding the last pixel of the last line of the display
2570 data and adding to linear_offset*/
2572 (intel_crtc
->config
->pipe_src_h
- 1) * fb
->pitches
[0] +
2573 (intel_crtc
->config
->pipe_src_w
- 1) * pixel_size
;
2576 I915_WRITE(reg
, dspcntr
);
2578 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2579 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2581 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2582 if (INTEL_INFO(dev
)->gen
>= 4) {
2583 I915_WRITE(DSPSURF(plane
),
2584 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2585 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2586 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2588 I915_WRITE(DSPADDR(plane
), i915_gem_obj_ggtt_offset(obj
) + linear_offset
);
2592 static void ironlake_update_primary_plane(struct drm_crtc
*crtc
,
2593 struct drm_framebuffer
*fb
,
2596 struct drm_device
*dev
= crtc
->dev
;
2597 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2598 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2599 struct drm_i915_gem_object
*obj
;
2600 int plane
= intel_crtc
->plane
;
2601 unsigned long linear_offset
;
2603 u32 reg
= DSPCNTR(plane
);
2606 if (!intel_crtc
->primary_enabled
) {
2608 I915_WRITE(DSPSURF(plane
), 0);
2613 obj
= intel_fb_obj(fb
);
2614 if (WARN_ON(obj
== NULL
))
2617 pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2619 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2621 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2623 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2624 dspcntr
|= DISPPLANE_PIPE_CSC_ENABLE
;
2626 switch (fb
->pixel_format
) {
2628 dspcntr
|= DISPPLANE_8BPP
;
2630 case DRM_FORMAT_RGB565
:
2631 dspcntr
|= DISPPLANE_BGRX565
;
2633 case DRM_FORMAT_XRGB8888
:
2634 case DRM_FORMAT_ARGB8888
:
2635 dspcntr
|= DISPPLANE_BGRX888
;
2637 case DRM_FORMAT_XBGR8888
:
2638 case DRM_FORMAT_ABGR8888
:
2639 dspcntr
|= DISPPLANE_RGBX888
;
2641 case DRM_FORMAT_XRGB2101010
:
2642 case DRM_FORMAT_ARGB2101010
:
2643 dspcntr
|= DISPPLANE_BGRX101010
;
2645 case DRM_FORMAT_XBGR2101010
:
2646 case DRM_FORMAT_ABGR2101010
:
2647 dspcntr
|= DISPPLANE_RGBX101010
;
2653 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2654 dspcntr
|= DISPPLANE_TILED
;
2656 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
))
2657 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2659 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
2660 intel_crtc
->dspaddr_offset
=
2661 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2664 linear_offset
-= intel_crtc
->dspaddr_offset
;
2665 if (crtc
->primary
->state
->rotation
== BIT(DRM_ROTATE_180
)) {
2666 dspcntr
|= DISPPLANE_ROTATE_180
;
2668 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
)) {
2669 x
+= (intel_crtc
->config
->pipe_src_w
- 1);
2670 y
+= (intel_crtc
->config
->pipe_src_h
- 1);
2672 /* Finding the last pixel of the last line of the display
2673 data and adding to linear_offset*/
2675 (intel_crtc
->config
->pipe_src_h
- 1) * fb
->pitches
[0] +
2676 (intel_crtc
->config
->pipe_src_w
- 1) * pixel_size
;
2680 I915_WRITE(reg
, dspcntr
);
2682 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2683 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2685 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2686 I915_WRITE(DSPSURF(plane
),
2687 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2688 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2689 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2691 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2692 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2697 static void skylake_update_primary_plane(struct drm_crtc
*crtc
,
2698 struct drm_framebuffer
*fb
,
2701 struct drm_device
*dev
= crtc
->dev
;
2702 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2703 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2704 struct intel_framebuffer
*intel_fb
;
2705 struct drm_i915_gem_object
*obj
;
2706 int pipe
= intel_crtc
->pipe
;
2707 u32 plane_ctl
, stride
;
2709 if (!intel_crtc
->primary_enabled
) {
2710 I915_WRITE(PLANE_CTL(pipe
, 0), 0);
2711 I915_WRITE(PLANE_SURF(pipe
, 0), 0);
2712 POSTING_READ(PLANE_CTL(pipe
, 0));
2716 plane_ctl
= PLANE_CTL_ENABLE
|
2717 PLANE_CTL_PIPE_GAMMA_ENABLE
|
2718 PLANE_CTL_PIPE_CSC_ENABLE
;
2720 switch (fb
->pixel_format
) {
2721 case DRM_FORMAT_RGB565
:
2722 plane_ctl
|= PLANE_CTL_FORMAT_RGB_565
;
2724 case DRM_FORMAT_XRGB8888
:
2725 plane_ctl
|= PLANE_CTL_FORMAT_XRGB_8888
;
2727 case DRM_FORMAT_XBGR8888
:
2728 plane_ctl
|= PLANE_CTL_ORDER_RGBX
;
2729 plane_ctl
|= PLANE_CTL_FORMAT_XRGB_8888
;
2731 case DRM_FORMAT_XRGB2101010
:
2732 plane_ctl
|= PLANE_CTL_FORMAT_XRGB_2101010
;
2734 case DRM_FORMAT_XBGR2101010
:
2735 plane_ctl
|= PLANE_CTL_ORDER_RGBX
;
2736 plane_ctl
|= PLANE_CTL_FORMAT_XRGB_2101010
;
2742 intel_fb
= to_intel_framebuffer(fb
);
2743 obj
= intel_fb
->obj
;
2746 * The stride is either expressed as a multiple of 64 bytes chunks for
2747 * linear buffers or in number of tiles for tiled buffers.
2749 switch (obj
->tiling_mode
) {
2750 case I915_TILING_NONE
:
2751 stride
= fb
->pitches
[0] >> 6;
2754 plane_ctl
|= PLANE_CTL_TILED_X
;
2755 stride
= fb
->pitches
[0] >> 9;
2761 plane_ctl
|= PLANE_CTL_PLANE_GAMMA_DISABLE
;
2762 if (crtc
->primary
->state
->rotation
== BIT(DRM_ROTATE_180
))
2763 plane_ctl
|= PLANE_CTL_ROTATE_180
;
2765 I915_WRITE(PLANE_CTL(pipe
, 0), plane_ctl
);
2767 DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2768 i915_gem_obj_ggtt_offset(obj
),
2769 x
, y
, fb
->width
, fb
->height
,
2772 I915_WRITE(PLANE_POS(pipe
, 0), 0);
2773 I915_WRITE(PLANE_OFFSET(pipe
, 0), (y
<< 16) | x
);
2774 I915_WRITE(PLANE_SIZE(pipe
, 0),
2775 (intel_crtc
->config
->pipe_src_h
- 1) << 16 |
2776 (intel_crtc
->config
->pipe_src_w
- 1));
2777 I915_WRITE(PLANE_STRIDE(pipe
, 0), stride
);
2778 I915_WRITE(PLANE_SURF(pipe
, 0), i915_gem_obj_ggtt_offset(obj
));
2780 POSTING_READ(PLANE_SURF(pipe
, 0));
2783 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2785 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2786 int x
, int y
, enum mode_set_atomic state
)
2788 struct drm_device
*dev
= crtc
->dev
;
2789 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2791 if (dev_priv
->display
.disable_fbc
)
2792 dev_priv
->display
.disable_fbc(dev
);
2794 dev_priv
->display
.update_primary_plane(crtc
, fb
, x
, y
);
2799 static void intel_complete_page_flips(struct drm_device
*dev
)
2801 struct drm_crtc
*crtc
;
2803 for_each_crtc(dev
, crtc
) {
2804 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2805 enum plane plane
= intel_crtc
->plane
;
2807 intel_prepare_page_flip(dev
, plane
);
2808 intel_finish_page_flip_plane(dev
, plane
);
2812 static void intel_update_primary_planes(struct drm_device
*dev
)
2814 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2815 struct drm_crtc
*crtc
;
2817 for_each_crtc(dev
, crtc
) {
2818 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2820 drm_modeset_lock(&crtc
->mutex
, NULL
);
2822 * FIXME: Once we have proper support for primary planes (and
2823 * disabling them without disabling the entire crtc) allow again
2824 * a NULL crtc->primary->fb.
2826 if (intel_crtc
->active
&& crtc
->primary
->fb
)
2827 dev_priv
->display
.update_primary_plane(crtc
,
2831 drm_modeset_unlock(&crtc
->mutex
);
2835 void intel_prepare_reset(struct drm_device
*dev
)
2837 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2838 struct intel_crtc
*crtc
;
2840 /* no reset support for gen2 */
2844 /* reset doesn't touch the display */
2845 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
2848 drm_modeset_lock_all(dev
);
2851 * Disabling the crtcs gracefully seems nicer. Also the
2852 * g33 docs say we should at least disable all the planes.
2854 for_each_intel_crtc(dev
, crtc
) {
2856 dev_priv
->display
.crtc_disable(&crtc
->base
);
2860 void intel_finish_reset(struct drm_device
*dev
)
2862 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2865 * Flips in the rings will be nuked by the reset,
2866 * so complete all pending flips so that user space
2867 * will get its events and not get stuck.
2869 intel_complete_page_flips(dev
);
2871 /* no reset support for gen2 */
2875 /* reset doesn't touch the display */
2876 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
)) {
2878 * Flips in the rings have been nuked by the reset,
2879 * so update the base address of all primary
2880 * planes to the the last fb to make sure we're
2881 * showing the correct fb after a reset.
2883 intel_update_primary_planes(dev
);
2888 * The display has been reset as well,
2889 * so need a full re-initialization.
2891 intel_runtime_pm_disable_interrupts(dev_priv
);
2892 intel_runtime_pm_enable_interrupts(dev_priv
);
2894 intel_modeset_init_hw(dev
);
2896 spin_lock_irq(&dev_priv
->irq_lock
);
2897 if (dev_priv
->display
.hpd_irq_setup
)
2898 dev_priv
->display
.hpd_irq_setup(dev
);
2899 spin_unlock_irq(&dev_priv
->irq_lock
);
2901 intel_modeset_setup_hw_state(dev
, true);
2903 intel_hpd_init(dev_priv
);
2905 drm_modeset_unlock_all(dev
);
2909 intel_finish_fb(struct drm_framebuffer
*old_fb
)
2911 struct drm_i915_gem_object
*obj
= intel_fb_obj(old_fb
);
2912 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2913 bool was_interruptible
= dev_priv
->mm
.interruptible
;
2916 /* Big Hammer, we also need to ensure that any pending
2917 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2918 * current scanout is retired before unpinning the old
2921 * This should only fail upon a hung GPU, in which case we
2922 * can safely continue.
2924 dev_priv
->mm
.interruptible
= false;
2925 ret
= i915_gem_object_finish_gpu(obj
);
2926 dev_priv
->mm
.interruptible
= was_interruptible
;
2931 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
2933 struct drm_device
*dev
= crtc
->dev
;
2934 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2935 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2938 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
2939 intel_crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
2942 spin_lock_irq(&dev
->event_lock
);
2943 pending
= to_intel_crtc(crtc
)->unpin_work
!= NULL
;
2944 spin_unlock_irq(&dev
->event_lock
);
2949 static void intel_update_pipe_size(struct intel_crtc
*crtc
)
2951 struct drm_device
*dev
= crtc
->base
.dev
;
2952 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2953 const struct drm_display_mode
*adjusted_mode
;
2959 * Update pipe size and adjust fitter if needed: the reason for this is
2960 * that in compute_mode_changes we check the native mode (not the pfit
2961 * mode) to see if we can flip rather than do a full mode set. In the
2962 * fastboot case, we'll flip, but if we don't update the pipesrc and
2963 * pfit state, we'll end up with a big fb scanned out into the wrong
2966 * To fix this properly, we need to hoist the checks up into
2967 * compute_mode_changes (or above), check the actual pfit state and
2968 * whether the platform allows pfit disable with pipe active, and only
2969 * then update the pipesrc and pfit state, even on the flip path.
2972 adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
2974 I915_WRITE(PIPESRC(crtc
->pipe
),
2975 ((adjusted_mode
->crtc_hdisplay
- 1) << 16) |
2976 (adjusted_mode
->crtc_vdisplay
- 1));
2977 if (!crtc
->config
->pch_pfit
.enabled
&&
2978 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) ||
2979 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
2980 I915_WRITE(PF_CTL(crtc
->pipe
), 0);
2981 I915_WRITE(PF_WIN_POS(crtc
->pipe
), 0);
2982 I915_WRITE(PF_WIN_SZ(crtc
->pipe
), 0);
2984 crtc
->config
->pipe_src_w
= adjusted_mode
->crtc_hdisplay
;
2985 crtc
->config
->pipe_src_h
= adjusted_mode
->crtc_vdisplay
;
2988 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
2990 struct drm_device
*dev
= crtc
->dev
;
2991 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2992 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2993 int pipe
= intel_crtc
->pipe
;
2996 /* enable normal train */
2997 reg
= FDI_TX_CTL(pipe
);
2998 temp
= I915_READ(reg
);
2999 if (IS_IVYBRIDGE(dev
)) {
3000 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3001 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
3003 temp
&= ~FDI_LINK_TRAIN_NONE
;
3004 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
3006 I915_WRITE(reg
, temp
);
3008 reg
= FDI_RX_CTL(pipe
);
3009 temp
= I915_READ(reg
);
3010 if (HAS_PCH_CPT(dev
)) {
3011 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3012 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
3014 temp
&= ~FDI_LINK_TRAIN_NONE
;
3015 temp
|= FDI_LINK_TRAIN_NONE
;
3017 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
3019 /* wait one idle pattern time */
3023 /* IVB wants error correction enabled */
3024 if (IS_IVYBRIDGE(dev
))
3025 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
3026 FDI_FE_ERRC_ENABLE
);
3029 static bool pipe_has_enabled_pch(struct intel_crtc
*crtc
)
3031 return crtc
->base
.enabled
&& crtc
->active
&&
3032 crtc
->config
->has_pch_encoder
;
3035 static void ivb_modeset_global_resources(struct drm_device
*dev
)
3037 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3038 struct intel_crtc
*pipe_B_crtc
=
3039 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
3040 struct intel_crtc
*pipe_C_crtc
=
3041 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]);
3045 * When everything is off disable fdi C so that we could enable fdi B
3046 * with all lanes. Note that we don't care about enabled pipes without
3047 * an enabled pch encoder.
3049 if (!pipe_has_enabled_pch(pipe_B_crtc
) &&
3050 !pipe_has_enabled_pch(pipe_C_crtc
)) {
3051 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
3052 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
3054 temp
= I915_READ(SOUTH_CHICKEN1
);
3055 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
3056 DRM_DEBUG_KMS("disabling fdi C rx\n");
3057 I915_WRITE(SOUTH_CHICKEN1
, temp
);
3061 /* The FDI link training functions for ILK/Ibexpeak. */
3062 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
3064 struct drm_device
*dev
= crtc
->dev
;
3065 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3066 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3067 int pipe
= intel_crtc
->pipe
;
3068 u32 reg
, temp
, tries
;
3070 /* FDI needs bits from pipe first */
3071 assert_pipe_enabled(dev_priv
, pipe
);
3073 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3075 reg
= FDI_RX_IMR(pipe
);
3076 temp
= I915_READ(reg
);
3077 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3078 temp
&= ~FDI_RX_BIT_LOCK
;
3079 I915_WRITE(reg
, temp
);
3083 /* enable CPU FDI TX and PCH FDI RX */
3084 reg
= FDI_TX_CTL(pipe
);
3085 temp
= I915_READ(reg
);
3086 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3087 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3088 temp
&= ~FDI_LINK_TRAIN_NONE
;
3089 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3090 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3092 reg
= FDI_RX_CTL(pipe
);
3093 temp
= I915_READ(reg
);
3094 temp
&= ~FDI_LINK_TRAIN_NONE
;
3095 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3096 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3101 /* Ironlake workaround, enable clock pointer after FDI enable*/
3102 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3103 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
3104 FDI_RX_PHASE_SYNC_POINTER_EN
);
3106 reg
= FDI_RX_IIR(pipe
);
3107 for (tries
= 0; tries
< 5; tries
++) {
3108 temp
= I915_READ(reg
);
3109 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3111 if ((temp
& FDI_RX_BIT_LOCK
)) {
3112 DRM_DEBUG_KMS("FDI train 1 done.\n");
3113 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3118 DRM_ERROR("FDI train 1 fail!\n");
3121 reg
= FDI_TX_CTL(pipe
);
3122 temp
= I915_READ(reg
);
3123 temp
&= ~FDI_LINK_TRAIN_NONE
;
3124 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3125 I915_WRITE(reg
, temp
);
3127 reg
= FDI_RX_CTL(pipe
);
3128 temp
= I915_READ(reg
);
3129 temp
&= ~FDI_LINK_TRAIN_NONE
;
3130 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3131 I915_WRITE(reg
, temp
);
3136 reg
= FDI_RX_IIR(pipe
);
3137 for (tries
= 0; tries
< 5; tries
++) {
3138 temp
= I915_READ(reg
);
3139 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3141 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3142 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3143 DRM_DEBUG_KMS("FDI train 2 done.\n");
3148 DRM_ERROR("FDI train 2 fail!\n");
3150 DRM_DEBUG_KMS("FDI train done\n");
3154 static const int snb_b_fdi_train_param
[] = {
3155 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
3156 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
3157 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
3158 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
3161 /* The FDI link training functions for SNB/Cougarpoint. */
3162 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
3164 struct drm_device
*dev
= crtc
->dev
;
3165 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3166 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3167 int pipe
= intel_crtc
->pipe
;
3168 u32 reg
, temp
, i
, retry
;
3170 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3172 reg
= FDI_RX_IMR(pipe
);
3173 temp
= I915_READ(reg
);
3174 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3175 temp
&= ~FDI_RX_BIT_LOCK
;
3176 I915_WRITE(reg
, temp
);
3181 /* enable CPU FDI TX and PCH FDI RX */
3182 reg
= FDI_TX_CTL(pipe
);
3183 temp
= I915_READ(reg
);
3184 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3185 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3186 temp
&= ~FDI_LINK_TRAIN_NONE
;
3187 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3188 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3190 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3191 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3193 I915_WRITE(FDI_RX_MISC(pipe
),
3194 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3196 reg
= FDI_RX_CTL(pipe
);
3197 temp
= I915_READ(reg
);
3198 if (HAS_PCH_CPT(dev
)) {
3199 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3200 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3202 temp
&= ~FDI_LINK_TRAIN_NONE
;
3203 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3205 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3210 for (i
= 0; i
< 4; i
++) {
3211 reg
= FDI_TX_CTL(pipe
);
3212 temp
= I915_READ(reg
);
3213 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3214 temp
|= snb_b_fdi_train_param
[i
];
3215 I915_WRITE(reg
, temp
);
3220 for (retry
= 0; retry
< 5; retry
++) {
3221 reg
= FDI_RX_IIR(pipe
);
3222 temp
= I915_READ(reg
);
3223 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3224 if (temp
& FDI_RX_BIT_LOCK
) {
3225 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3226 DRM_DEBUG_KMS("FDI train 1 done.\n");
3235 DRM_ERROR("FDI train 1 fail!\n");
3238 reg
= FDI_TX_CTL(pipe
);
3239 temp
= I915_READ(reg
);
3240 temp
&= ~FDI_LINK_TRAIN_NONE
;
3241 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3243 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3245 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3247 I915_WRITE(reg
, temp
);
3249 reg
= FDI_RX_CTL(pipe
);
3250 temp
= I915_READ(reg
);
3251 if (HAS_PCH_CPT(dev
)) {
3252 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3253 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3255 temp
&= ~FDI_LINK_TRAIN_NONE
;
3256 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3258 I915_WRITE(reg
, temp
);
3263 for (i
= 0; i
< 4; i
++) {
3264 reg
= FDI_TX_CTL(pipe
);
3265 temp
= I915_READ(reg
);
3266 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3267 temp
|= snb_b_fdi_train_param
[i
];
3268 I915_WRITE(reg
, temp
);
3273 for (retry
= 0; retry
< 5; retry
++) {
3274 reg
= FDI_RX_IIR(pipe
);
3275 temp
= I915_READ(reg
);
3276 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3277 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3278 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3279 DRM_DEBUG_KMS("FDI train 2 done.\n");
3288 DRM_ERROR("FDI train 2 fail!\n");
3290 DRM_DEBUG_KMS("FDI train done.\n");
3293 /* Manual link training for Ivy Bridge A0 parts */
3294 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
3296 struct drm_device
*dev
= crtc
->dev
;
3297 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3298 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3299 int pipe
= intel_crtc
->pipe
;
3300 u32 reg
, temp
, i
, j
;
3302 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3304 reg
= FDI_RX_IMR(pipe
);
3305 temp
= I915_READ(reg
);
3306 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3307 temp
&= ~FDI_RX_BIT_LOCK
;
3308 I915_WRITE(reg
, temp
);
3313 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3314 I915_READ(FDI_RX_IIR(pipe
)));
3316 /* Try each vswing and preemphasis setting twice before moving on */
3317 for (j
= 0; j
< ARRAY_SIZE(snb_b_fdi_train_param
) * 2; j
++) {
3318 /* disable first in case we need to retry */
3319 reg
= FDI_TX_CTL(pipe
);
3320 temp
= I915_READ(reg
);
3321 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
3322 temp
&= ~FDI_TX_ENABLE
;
3323 I915_WRITE(reg
, temp
);
3325 reg
= FDI_RX_CTL(pipe
);
3326 temp
= I915_READ(reg
);
3327 temp
&= ~FDI_LINK_TRAIN_AUTO
;
3328 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3329 temp
&= ~FDI_RX_ENABLE
;
3330 I915_WRITE(reg
, temp
);
3332 /* enable CPU FDI TX and PCH FDI RX */
3333 reg
= FDI_TX_CTL(pipe
);
3334 temp
= I915_READ(reg
);
3335 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3336 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3337 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
3338 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3339 temp
|= snb_b_fdi_train_param
[j
/2];
3340 temp
|= FDI_COMPOSITE_SYNC
;
3341 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3343 I915_WRITE(FDI_RX_MISC(pipe
),
3344 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3346 reg
= FDI_RX_CTL(pipe
);
3347 temp
= I915_READ(reg
);
3348 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3349 temp
|= FDI_COMPOSITE_SYNC
;
3350 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3353 udelay(1); /* should be 0.5us */
3355 for (i
= 0; i
< 4; i
++) {
3356 reg
= FDI_RX_IIR(pipe
);
3357 temp
= I915_READ(reg
);
3358 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3360 if (temp
& FDI_RX_BIT_LOCK
||
3361 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
3362 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3363 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3367 udelay(1); /* should be 0.5us */
3370 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j
/ 2);
3375 reg
= FDI_TX_CTL(pipe
);
3376 temp
= I915_READ(reg
);
3377 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3378 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
3379 I915_WRITE(reg
, temp
);
3381 reg
= FDI_RX_CTL(pipe
);
3382 temp
= I915_READ(reg
);
3383 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3384 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3385 I915_WRITE(reg
, temp
);
3388 udelay(2); /* should be 1.5us */
3390 for (i
= 0; i
< 4; i
++) {
3391 reg
= FDI_RX_IIR(pipe
);
3392 temp
= I915_READ(reg
);
3393 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3395 if (temp
& FDI_RX_SYMBOL_LOCK
||
3396 (I915_READ(reg
) & FDI_RX_SYMBOL_LOCK
)) {
3397 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3398 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3402 udelay(2); /* should be 1.5us */
3405 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j
/ 2);
3409 DRM_DEBUG_KMS("FDI train done.\n");
3412 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
3414 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3415 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3416 int pipe
= intel_crtc
->pipe
;
3420 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3421 reg
= FDI_RX_CTL(pipe
);
3422 temp
= I915_READ(reg
);
3423 temp
&= ~(FDI_DP_PORT_WIDTH_MASK
| (0x7 << 16));
3424 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3425 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3426 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
3431 /* Switch from Rawclk to PCDclk */
3432 temp
= I915_READ(reg
);
3433 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
3438 /* Enable CPU FDI TX PLL, always on for Ironlake */
3439 reg
= FDI_TX_CTL(pipe
);
3440 temp
= I915_READ(reg
);
3441 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
3442 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
3449 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
3451 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3452 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3453 int pipe
= intel_crtc
->pipe
;
3456 /* Switch from PCDclk to Rawclk */
3457 reg
= FDI_RX_CTL(pipe
);
3458 temp
= I915_READ(reg
);
3459 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
3461 /* Disable CPU FDI TX PLL */
3462 reg
= FDI_TX_CTL(pipe
);
3463 temp
= I915_READ(reg
);
3464 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
3469 reg
= FDI_RX_CTL(pipe
);
3470 temp
= I915_READ(reg
);
3471 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
3473 /* Wait for the clocks to turn off. */
3478 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
3480 struct drm_device
*dev
= crtc
->dev
;
3481 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3482 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3483 int pipe
= intel_crtc
->pipe
;
3486 /* disable CPU FDI tx and PCH FDI rx */
3487 reg
= FDI_TX_CTL(pipe
);
3488 temp
= I915_READ(reg
);
3489 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
3492 reg
= FDI_RX_CTL(pipe
);
3493 temp
= I915_READ(reg
);
3494 temp
&= ~(0x7 << 16);
3495 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3496 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
3501 /* Ironlake workaround, disable clock pointer after downing FDI */
3502 if (HAS_PCH_IBX(dev
))
3503 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3505 /* still set train pattern 1 */
3506 reg
= FDI_TX_CTL(pipe
);
3507 temp
= I915_READ(reg
);
3508 temp
&= ~FDI_LINK_TRAIN_NONE
;
3509 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3510 I915_WRITE(reg
, temp
);
3512 reg
= FDI_RX_CTL(pipe
);
3513 temp
= I915_READ(reg
);
3514 if (HAS_PCH_CPT(dev
)) {
3515 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3516 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3518 temp
&= ~FDI_LINK_TRAIN_NONE
;
3519 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3521 /* BPC in FDI rx is consistent with that in PIPECONF */
3522 temp
&= ~(0x07 << 16);
3523 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3524 I915_WRITE(reg
, temp
);
3530 bool intel_has_pending_fb_unpin(struct drm_device
*dev
)
3532 struct intel_crtc
*crtc
;
3534 /* Note that we don't need to be called with mode_config.lock here
3535 * as our list of CRTC objects is static for the lifetime of the
3536 * device and so cannot disappear as we iterate. Similarly, we can
3537 * happily treat the predicates as racy, atomic checks as userspace
3538 * cannot claim and pin a new fb without at least acquring the
3539 * struct_mutex and so serialising with us.
3541 for_each_intel_crtc(dev
, crtc
) {
3542 if (atomic_read(&crtc
->unpin_work_count
) == 0)
3545 if (crtc
->unpin_work
)
3546 intel_wait_for_vblank(dev
, crtc
->pipe
);
3554 static void page_flip_completed(struct intel_crtc
*intel_crtc
)
3556 struct drm_i915_private
*dev_priv
= to_i915(intel_crtc
->base
.dev
);
3557 struct intel_unpin_work
*work
= intel_crtc
->unpin_work
;
3559 /* ensure that the unpin work is consistent wrt ->pending. */
3561 intel_crtc
->unpin_work
= NULL
;
3564 drm_send_vblank_event(intel_crtc
->base
.dev
,
3568 drm_crtc_vblank_put(&intel_crtc
->base
);
3570 wake_up_all(&dev_priv
->pending_flip_queue
);
3571 queue_work(dev_priv
->wq
, &work
->work
);
3573 trace_i915_flip_complete(intel_crtc
->plane
,
3574 work
->pending_flip_obj
);
3577 void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
3579 struct drm_device
*dev
= crtc
->dev
;
3580 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3582 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
3583 if (WARN_ON(wait_event_timeout(dev_priv
->pending_flip_queue
,
3584 !intel_crtc_has_pending_flip(crtc
),
3586 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3588 spin_lock_irq(&dev
->event_lock
);
3589 if (intel_crtc
->unpin_work
) {
3590 WARN_ONCE(1, "Removing stuck page flip\n");
3591 page_flip_completed(intel_crtc
);
3593 spin_unlock_irq(&dev
->event_lock
);
3596 if (crtc
->primary
->fb
) {
3597 mutex_lock(&dev
->struct_mutex
);
3598 intel_finish_fb(crtc
->primary
->fb
);
3599 mutex_unlock(&dev
->struct_mutex
);
3603 /* Program iCLKIP clock to the desired frequency */
3604 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
3606 struct drm_device
*dev
= crtc
->dev
;
3607 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3608 int clock
= to_intel_crtc(crtc
)->config
->base
.adjusted_mode
.crtc_clock
;
3609 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
3612 mutex_lock(&dev_priv
->dpio_lock
);
3614 /* It is necessary to ungate the pixclk gate prior to programming
3615 * the divisors, and gate it back when it is done.
3617 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
3619 /* Disable SSCCTL */
3620 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
3621 intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
) |
3625 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3626 if (clock
== 20000) {
3631 /* The iCLK virtual clock root frequency is in MHz,
3632 * but the adjusted_mode->crtc_clock in in KHz. To get the
3633 * divisors, it is necessary to divide one by another, so we
3634 * convert the virtual clock precision to KHz here for higher
3637 u32 iclk_virtual_root_freq
= 172800 * 1000;
3638 u32 iclk_pi_range
= 64;
3639 u32 desired_divisor
, msb_divisor_value
, pi_value
;
3641 desired_divisor
= (iclk_virtual_root_freq
/ clock
);
3642 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
3643 pi_value
= desired_divisor
% iclk_pi_range
;
3646 divsel
= msb_divisor_value
- 2;
3647 phaseinc
= pi_value
;
3650 /* This should not happen with any sane values */
3651 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
3652 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
3653 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
3654 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
3656 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3663 /* Program SSCDIVINTPHASE6 */
3664 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
3665 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
3666 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
3667 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
3668 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
3669 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
3670 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
3671 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
3673 /* Program SSCAUXDIV */
3674 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
3675 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3676 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
3677 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
3679 /* Enable modulator and associated divider */
3680 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
3681 temp
&= ~SBI_SSCCTL_DISABLE
;
3682 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
3684 /* Wait for initialization time */
3687 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
3689 mutex_unlock(&dev_priv
->dpio_lock
);
3692 static void ironlake_pch_transcoder_set_timings(struct intel_crtc
*crtc
,
3693 enum pipe pch_transcoder
)
3695 struct drm_device
*dev
= crtc
->base
.dev
;
3696 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3697 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
3699 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder
),
3700 I915_READ(HTOTAL(cpu_transcoder
)));
3701 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder
),
3702 I915_READ(HBLANK(cpu_transcoder
)));
3703 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder
),
3704 I915_READ(HSYNC(cpu_transcoder
)));
3706 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder
),
3707 I915_READ(VTOTAL(cpu_transcoder
)));
3708 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder
),
3709 I915_READ(VBLANK(cpu_transcoder
)));
3710 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder
),
3711 I915_READ(VSYNC(cpu_transcoder
)));
3712 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder
),
3713 I915_READ(VSYNCSHIFT(cpu_transcoder
)));
3716 static void cpt_enable_fdi_bc_bifurcation(struct drm_device
*dev
)
3718 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3721 temp
= I915_READ(SOUTH_CHICKEN1
);
3722 if (temp
& FDI_BC_BIFURCATION_SELECT
)
3725 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
3726 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
3728 temp
|= FDI_BC_BIFURCATION_SELECT
;
3729 DRM_DEBUG_KMS("enabling fdi C rx\n");
3730 I915_WRITE(SOUTH_CHICKEN1
, temp
);
3731 POSTING_READ(SOUTH_CHICKEN1
);
3734 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc
*intel_crtc
)
3736 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3737 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3739 switch (intel_crtc
->pipe
) {
3743 if (intel_crtc
->config
->fdi_lanes
> 2)
3744 WARN_ON(I915_READ(SOUTH_CHICKEN1
) & FDI_BC_BIFURCATION_SELECT
);
3746 cpt_enable_fdi_bc_bifurcation(dev
);
3750 cpt_enable_fdi_bc_bifurcation(dev
);
3759 * Enable PCH resources required for PCH ports:
3761 * - FDI training & RX/TX
3762 * - update transcoder timings
3763 * - DP transcoding bits
3766 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
3768 struct drm_device
*dev
= crtc
->dev
;
3769 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3770 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3771 int pipe
= intel_crtc
->pipe
;
3774 assert_pch_transcoder_disabled(dev_priv
, pipe
);
3776 if (IS_IVYBRIDGE(dev
))
3777 ivybridge_update_fdi_bc_bifurcation(intel_crtc
);
3779 /* Write the TU size bits before fdi link training, so that error
3780 * detection works. */
3781 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
3782 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
3784 /* For PCH output, training FDI link */
3785 dev_priv
->display
.fdi_link_train(crtc
);
3787 /* We need to program the right clock selection before writing the pixel
3788 * mutliplier into the DPLL. */
3789 if (HAS_PCH_CPT(dev
)) {
3792 temp
= I915_READ(PCH_DPLL_SEL
);
3793 temp
|= TRANS_DPLL_ENABLE(pipe
);
3794 sel
= TRANS_DPLLB_SEL(pipe
);
3795 if (intel_crtc
->config
->shared_dpll
== DPLL_ID_PCH_PLL_B
)
3799 I915_WRITE(PCH_DPLL_SEL
, temp
);
3802 /* XXX: pch pll's can be enabled any time before we enable the PCH
3803 * transcoder, and we actually should do this to not upset any PCH
3804 * transcoder that already use the clock when we share it.
3806 * Note that enable_shared_dpll tries to do the right thing, but
3807 * get_shared_dpll unconditionally resets the pll - we need that to have
3808 * the right LVDS enable sequence. */
3809 intel_enable_shared_dpll(intel_crtc
);
3811 /* set transcoder timing, panel must allow it */
3812 assert_panel_unlocked(dev_priv
, pipe
);
3813 ironlake_pch_transcoder_set_timings(intel_crtc
, pipe
);
3815 intel_fdi_normal_train(crtc
);
3817 /* For PCH DP, enable TRANS_DP_CTL */
3818 if (HAS_PCH_CPT(dev
) && intel_crtc
->config
->has_dp_encoder
) {
3819 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
3820 reg
= TRANS_DP_CTL(pipe
);
3821 temp
= I915_READ(reg
);
3822 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
3823 TRANS_DP_SYNC_MASK
|
3825 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
3826 TRANS_DP_ENH_FRAMING
);
3827 temp
|= bpc
<< 9; /* same format but at 11:9 */
3829 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
3830 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
3831 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
3832 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
3834 switch (intel_trans_dp_port_sel(crtc
)) {
3836 temp
|= TRANS_DP_PORT_SEL_B
;
3839 temp
|= TRANS_DP_PORT_SEL_C
;
3842 temp
|= TRANS_DP_PORT_SEL_D
;
3848 I915_WRITE(reg
, temp
);
3851 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
3854 static void lpt_pch_enable(struct drm_crtc
*crtc
)
3856 struct drm_device
*dev
= crtc
->dev
;
3857 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3858 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3859 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
3861 assert_pch_transcoder_disabled(dev_priv
, TRANSCODER_A
);
3863 lpt_program_iclkip(crtc
);
3865 /* Set transcoder timing. */
3866 ironlake_pch_transcoder_set_timings(intel_crtc
, PIPE_A
);
3868 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
3871 void intel_put_shared_dpll(struct intel_crtc
*crtc
)
3873 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
3878 if (!(pll
->config
.crtc_mask
& (1 << crtc
->pipe
))) {
3879 WARN(1, "bad %s crtc mask\n", pll
->name
);
3883 pll
->config
.crtc_mask
&= ~(1 << crtc
->pipe
);
3884 if (pll
->config
.crtc_mask
== 0) {
3886 WARN_ON(pll
->active
);
3889 crtc
->config
->shared_dpll
= DPLL_ID_PRIVATE
;
3892 struct intel_shared_dpll
*intel_get_shared_dpll(struct intel_crtc
*crtc
,
3893 struct intel_crtc_state
*crtc_state
)
3895 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
3896 struct intel_shared_dpll
*pll
;
3897 enum intel_dpll_id i
;
3899 if (HAS_PCH_IBX(dev_priv
->dev
)) {
3900 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3901 i
= (enum intel_dpll_id
) crtc
->pipe
;
3902 pll
= &dev_priv
->shared_dplls
[i
];
3904 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3905 crtc
->base
.base
.id
, pll
->name
);
3907 WARN_ON(pll
->new_config
->crtc_mask
);
3912 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3913 pll
= &dev_priv
->shared_dplls
[i
];
3915 /* Only want to check enabled timings first */
3916 if (pll
->new_config
->crtc_mask
== 0)
3919 if (memcmp(&crtc_state
->dpll_hw_state
,
3920 &pll
->new_config
->hw_state
,
3921 sizeof(pll
->new_config
->hw_state
)) == 0) {
3922 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
3923 crtc
->base
.base
.id
, pll
->name
,
3924 pll
->new_config
->crtc_mask
,
3930 /* Ok no matching timings, maybe there's a free one? */
3931 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3932 pll
= &dev_priv
->shared_dplls
[i
];
3933 if (pll
->new_config
->crtc_mask
== 0) {
3934 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3935 crtc
->base
.base
.id
, pll
->name
);
3943 if (pll
->new_config
->crtc_mask
== 0)
3944 pll
->new_config
->hw_state
= crtc_state
->dpll_hw_state
;
3946 crtc_state
->shared_dpll
= i
;
3947 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll
->name
,
3948 pipe_name(crtc
->pipe
));
3950 pll
->new_config
->crtc_mask
|= 1 << crtc
->pipe
;
3956 * intel_shared_dpll_start_config - start a new PLL staged config
3957 * @dev_priv: DRM device
3958 * @clear_pipes: mask of pipes that will have their PLLs freed
3960 * Starts a new PLL staged config, copying the current config but
3961 * releasing the references of pipes specified in clear_pipes.
3963 static int intel_shared_dpll_start_config(struct drm_i915_private
*dev_priv
,
3964 unsigned clear_pipes
)
3966 struct intel_shared_dpll
*pll
;
3967 enum intel_dpll_id i
;
3969 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3970 pll
= &dev_priv
->shared_dplls
[i
];
3972 pll
->new_config
= kmemdup(&pll
->config
, sizeof pll
->config
,
3974 if (!pll
->new_config
)
3977 pll
->new_config
->crtc_mask
&= ~clear_pipes
;
3984 pll
= &dev_priv
->shared_dplls
[i
];
3985 kfree(pll
->new_config
);
3986 pll
->new_config
= NULL
;
3992 static void intel_shared_dpll_commit(struct drm_i915_private
*dev_priv
)
3994 struct intel_shared_dpll
*pll
;
3995 enum intel_dpll_id i
;
3997 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3998 pll
= &dev_priv
->shared_dplls
[i
];
4000 WARN_ON(pll
->new_config
== &pll
->config
);
4002 pll
->config
= *pll
->new_config
;
4003 kfree(pll
->new_config
);
4004 pll
->new_config
= NULL
;
4008 static void intel_shared_dpll_abort_config(struct drm_i915_private
*dev_priv
)
4010 struct intel_shared_dpll
*pll
;
4011 enum intel_dpll_id i
;
4013 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4014 pll
= &dev_priv
->shared_dplls
[i
];
4016 WARN_ON(pll
->new_config
== &pll
->config
);
4018 kfree(pll
->new_config
);
4019 pll
->new_config
= NULL
;
4023 static void cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
4025 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4026 int dslreg
= PIPEDSL(pipe
);
4029 temp
= I915_READ(dslreg
);
4031 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
4032 if (wait_for(I915_READ(dslreg
) != temp
, 5))
4033 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
4037 static void skylake_pfit_enable(struct intel_crtc
*crtc
)
4039 struct drm_device
*dev
= crtc
->base
.dev
;
4040 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4041 int pipe
= crtc
->pipe
;
4043 if (crtc
->config
->pch_pfit
.enabled
) {
4044 I915_WRITE(PS_CTL(pipe
), PS_ENABLE
);
4045 I915_WRITE(PS_WIN_POS(pipe
), crtc
->config
->pch_pfit
.pos
);
4046 I915_WRITE(PS_WIN_SZ(pipe
), crtc
->config
->pch_pfit
.size
);
4050 static void ironlake_pfit_enable(struct intel_crtc
*crtc
)
4052 struct drm_device
*dev
= crtc
->base
.dev
;
4053 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4054 int pipe
= crtc
->pipe
;
4056 if (crtc
->config
->pch_pfit
.enabled
) {
4057 /* Force use of hard-coded filter coefficients
4058 * as some pre-programmed values are broken,
4061 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
4062 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
4063 PF_PIPE_SEL_IVB(pipe
));
4065 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
4066 I915_WRITE(PF_WIN_POS(pipe
), crtc
->config
->pch_pfit
.pos
);
4067 I915_WRITE(PF_WIN_SZ(pipe
), crtc
->config
->pch_pfit
.size
);
4071 static void intel_enable_sprite_planes(struct drm_crtc
*crtc
)
4073 struct drm_device
*dev
= crtc
->dev
;
4074 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
4075 struct drm_plane
*plane
;
4076 struct intel_plane
*intel_plane
;
4078 drm_for_each_legacy_plane(plane
, &dev
->mode_config
.plane_list
) {
4079 intel_plane
= to_intel_plane(plane
);
4080 if (intel_plane
->pipe
== pipe
)
4081 intel_plane_restore(&intel_plane
->base
);
4085 static void intel_disable_sprite_planes(struct drm_crtc
*crtc
)
4087 struct drm_device
*dev
= crtc
->dev
;
4088 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
4089 struct drm_plane
*plane
;
4090 struct intel_plane
*intel_plane
;
4092 drm_for_each_legacy_plane(plane
, &dev
->mode_config
.plane_list
) {
4093 intel_plane
= to_intel_plane(plane
);
4094 if (intel_plane
->pipe
== pipe
)
4095 plane
->funcs
->disable_plane(plane
);
4099 void hsw_enable_ips(struct intel_crtc
*crtc
)
4101 struct drm_device
*dev
= crtc
->base
.dev
;
4102 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4104 if (!crtc
->config
->ips_enabled
)
4107 /* We can only enable IPS after we enable a plane and wait for a vblank */
4108 intel_wait_for_vblank(dev
, crtc
->pipe
);
4110 assert_plane_enabled(dev_priv
, crtc
->plane
);
4111 if (IS_BROADWELL(dev
)) {
4112 mutex_lock(&dev_priv
->rps
.hw_lock
);
4113 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0xc0000000));
4114 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4115 /* Quoting Art Runyan: "its not safe to expect any particular
4116 * value in IPS_CTL bit 31 after enabling IPS through the
4117 * mailbox." Moreover, the mailbox may return a bogus state,
4118 * so we need to just enable it and continue on.
4121 I915_WRITE(IPS_CTL
, IPS_ENABLE
);
4122 /* The bit only becomes 1 in the next vblank, so this wait here
4123 * is essentially intel_wait_for_vblank. If we don't have this
4124 * and don't wait for vblanks until the end of crtc_enable, then
4125 * the HW state readout code will complain that the expected
4126 * IPS_CTL value is not the one we read. */
4127 if (wait_for(I915_READ_NOTRACE(IPS_CTL
) & IPS_ENABLE
, 50))
4128 DRM_ERROR("Timed out waiting for IPS enable\n");
4132 void hsw_disable_ips(struct intel_crtc
*crtc
)
4134 struct drm_device
*dev
= crtc
->base
.dev
;
4135 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4137 if (!crtc
->config
->ips_enabled
)
4140 assert_plane_enabled(dev_priv
, crtc
->plane
);
4141 if (IS_BROADWELL(dev
)) {
4142 mutex_lock(&dev_priv
->rps
.hw_lock
);
4143 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0));
4144 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4145 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4146 if (wait_for((I915_READ(IPS_CTL
) & IPS_ENABLE
) == 0, 42))
4147 DRM_ERROR("Timed out waiting for IPS disable\n");
4149 I915_WRITE(IPS_CTL
, 0);
4150 POSTING_READ(IPS_CTL
);
4153 /* We need to wait for a vblank before we can disable the plane. */
4154 intel_wait_for_vblank(dev
, crtc
->pipe
);
4157 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4158 static void intel_crtc_load_lut(struct drm_crtc
*crtc
)
4160 struct drm_device
*dev
= crtc
->dev
;
4161 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4162 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4163 enum pipe pipe
= intel_crtc
->pipe
;
4164 int palreg
= PALETTE(pipe
);
4166 bool reenable_ips
= false;
4168 /* The clocks have to be on to load the palette. */
4169 if (!crtc
->enabled
|| !intel_crtc
->active
)
4172 if (!HAS_PCH_SPLIT(dev_priv
->dev
)) {
4173 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
))
4174 assert_dsi_pll_enabled(dev_priv
);
4176 assert_pll_enabled(dev_priv
, pipe
);
4179 /* use legacy palette for Ironlake */
4180 if (!HAS_GMCH_DISPLAY(dev
))
4181 palreg
= LGC_PALETTE(pipe
);
4183 /* Workaround : Do not read or write the pipe palette/gamma data while
4184 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4186 if (IS_HASWELL(dev
) && intel_crtc
->config
->ips_enabled
&&
4187 ((I915_READ(GAMMA_MODE(pipe
)) & GAMMA_MODE_MODE_MASK
) ==
4188 GAMMA_MODE_MODE_SPLIT
)) {
4189 hsw_disable_ips(intel_crtc
);
4190 reenable_ips
= true;
4193 for (i
= 0; i
< 256; i
++) {
4194 I915_WRITE(palreg
+ 4 * i
,
4195 (intel_crtc
->lut_r
[i
] << 16) |
4196 (intel_crtc
->lut_g
[i
] << 8) |
4197 intel_crtc
->lut_b
[i
]);
4201 hsw_enable_ips(intel_crtc
);
4204 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
4206 if (!enable
&& intel_crtc
->overlay
) {
4207 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4208 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4210 mutex_lock(&dev
->struct_mutex
);
4211 dev_priv
->mm
.interruptible
= false;
4212 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
4213 dev_priv
->mm
.interruptible
= true;
4214 mutex_unlock(&dev
->struct_mutex
);
4217 /* Let userspace switch the overlay on again. In most cases userspace
4218 * has to recompute where to put it anyway.
4222 static void intel_crtc_enable_planes(struct drm_crtc
*crtc
)
4224 struct drm_device
*dev
= crtc
->dev
;
4225 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4226 int pipe
= intel_crtc
->pipe
;
4228 intel_enable_primary_hw_plane(crtc
->primary
, crtc
);
4229 intel_enable_sprite_planes(crtc
);
4230 intel_crtc_update_cursor(crtc
, true);
4231 intel_crtc_dpms_overlay(intel_crtc
, true);
4233 hsw_enable_ips(intel_crtc
);
4235 mutex_lock(&dev
->struct_mutex
);
4236 intel_fbc_update(dev
);
4237 mutex_unlock(&dev
->struct_mutex
);
4240 * FIXME: Once we grow proper nuclear flip support out of this we need
4241 * to compute the mask of flip planes precisely. For the time being
4242 * consider this a flip from a NULL plane.
4244 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_ALL_MASK(pipe
));
4247 static void intel_crtc_disable_planes(struct drm_crtc
*crtc
)
4249 struct drm_device
*dev
= crtc
->dev
;
4250 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4251 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4252 int pipe
= intel_crtc
->pipe
;
4253 int plane
= intel_crtc
->plane
;
4255 intel_crtc_wait_for_pending_flips(crtc
);
4257 if (dev_priv
->fbc
.plane
== plane
)
4258 intel_fbc_disable(dev
);
4260 hsw_disable_ips(intel_crtc
);
4262 intel_crtc_dpms_overlay(intel_crtc
, false);
4263 intel_crtc_update_cursor(crtc
, false);
4264 intel_disable_sprite_planes(crtc
);
4265 intel_disable_primary_hw_plane(crtc
->primary
, crtc
);
4268 * FIXME: Once we grow proper nuclear flip support out of this we need
4269 * to compute the mask of flip planes precisely. For the time being
4270 * consider this a flip to a NULL plane.
4272 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_ALL_MASK(pipe
));
4275 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
4277 struct drm_device
*dev
= crtc
->dev
;
4278 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4279 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4280 struct intel_encoder
*encoder
;
4281 int pipe
= intel_crtc
->pipe
;
4283 WARN_ON(!crtc
->enabled
);
4285 if (intel_crtc
->active
)
4288 if (intel_crtc
->config
->has_pch_encoder
)
4289 intel_prepare_shared_dpll(intel_crtc
);
4291 if (intel_crtc
->config
->has_dp_encoder
)
4292 intel_dp_set_m_n(intel_crtc
);
4294 intel_set_pipe_timings(intel_crtc
);
4296 if (intel_crtc
->config
->has_pch_encoder
) {
4297 intel_cpu_transcoder_set_m_n(intel_crtc
,
4298 &intel_crtc
->config
->fdi_m_n
, NULL
);
4301 ironlake_set_pipeconf(crtc
);
4303 intel_crtc
->active
= true;
4305 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4306 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, true);
4308 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4309 if (encoder
->pre_enable
)
4310 encoder
->pre_enable(encoder
);
4312 if (intel_crtc
->config
->has_pch_encoder
) {
4313 /* Note: FDI PLL enabling _must_ be done before we enable the
4314 * cpu pipes, hence this is separate from all the other fdi/pch
4316 ironlake_fdi_pll_enable(intel_crtc
);
4318 assert_fdi_tx_disabled(dev_priv
, pipe
);
4319 assert_fdi_rx_disabled(dev_priv
, pipe
);
4322 ironlake_pfit_enable(intel_crtc
);
4325 * On ILK+ LUT must be loaded before the pipe is running but with
4328 intel_crtc_load_lut(crtc
);
4330 intel_update_watermarks(crtc
);
4331 intel_enable_pipe(intel_crtc
);
4333 if (intel_crtc
->config
->has_pch_encoder
)
4334 ironlake_pch_enable(crtc
);
4336 assert_vblank_disabled(crtc
);
4337 drm_crtc_vblank_on(crtc
);
4339 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4340 encoder
->enable(encoder
);
4342 if (HAS_PCH_CPT(dev
))
4343 cpt_verify_modeset(dev
, intel_crtc
->pipe
);
4345 intel_crtc_enable_planes(crtc
);
4348 /* IPS only exists on ULT machines and is tied to pipe A. */
4349 static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc
)
4351 return HAS_IPS(crtc
->base
.dev
) && crtc
->pipe
== PIPE_A
;
4355 * This implements the workaround described in the "notes" section of the mode
4356 * set sequence documentation. When going from no pipes or single pipe to
4357 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4358 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4360 static void haswell_mode_set_planes_workaround(struct intel_crtc
*crtc
)
4362 struct drm_device
*dev
= crtc
->base
.dev
;
4363 struct intel_crtc
*crtc_it
, *other_active_crtc
= NULL
;
4365 /* We want to get the other_active_crtc only if there's only 1 other
4367 for_each_intel_crtc(dev
, crtc_it
) {
4368 if (!crtc_it
->active
|| crtc_it
== crtc
)
4371 if (other_active_crtc
)
4374 other_active_crtc
= crtc_it
;
4376 if (!other_active_crtc
)
4379 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
4380 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
4383 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
4385 struct drm_device
*dev
= crtc
->dev
;
4386 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4387 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4388 struct intel_encoder
*encoder
;
4389 int pipe
= intel_crtc
->pipe
;
4391 WARN_ON(!crtc
->enabled
);
4393 if (intel_crtc
->active
)
4396 if (intel_crtc_to_shared_dpll(intel_crtc
))
4397 intel_enable_shared_dpll(intel_crtc
);
4399 if (intel_crtc
->config
->has_dp_encoder
)
4400 intel_dp_set_m_n(intel_crtc
);
4402 intel_set_pipe_timings(intel_crtc
);
4404 if (intel_crtc
->config
->cpu_transcoder
!= TRANSCODER_EDP
) {
4405 I915_WRITE(PIPE_MULT(intel_crtc
->config
->cpu_transcoder
),
4406 intel_crtc
->config
->pixel_multiplier
- 1);
4409 if (intel_crtc
->config
->has_pch_encoder
) {
4410 intel_cpu_transcoder_set_m_n(intel_crtc
,
4411 &intel_crtc
->config
->fdi_m_n
, NULL
);
4414 haswell_set_pipeconf(crtc
);
4416 intel_set_pipe_csc(crtc
);
4418 intel_crtc
->active
= true;
4420 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4421 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4422 if (encoder
->pre_enable
)
4423 encoder
->pre_enable(encoder
);
4425 if (intel_crtc
->config
->has_pch_encoder
) {
4426 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
4428 dev_priv
->display
.fdi_link_train(crtc
);
4431 intel_ddi_enable_pipe_clock(intel_crtc
);
4433 if (IS_SKYLAKE(dev
))
4434 skylake_pfit_enable(intel_crtc
);
4436 ironlake_pfit_enable(intel_crtc
);
4439 * On ILK+ LUT must be loaded before the pipe is running but with
4442 intel_crtc_load_lut(crtc
);
4444 intel_ddi_set_pipe_settings(crtc
);
4445 intel_ddi_enable_transcoder_func(crtc
);
4447 intel_update_watermarks(crtc
);
4448 intel_enable_pipe(intel_crtc
);
4450 if (intel_crtc
->config
->has_pch_encoder
)
4451 lpt_pch_enable(crtc
);
4453 if (intel_crtc
->config
->dp_encoder_is_mst
)
4454 intel_ddi_set_vc_payload_alloc(crtc
, true);
4456 assert_vblank_disabled(crtc
);
4457 drm_crtc_vblank_on(crtc
);
4459 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4460 encoder
->enable(encoder
);
4461 intel_opregion_notify_encoder(encoder
, true);
4464 /* If we change the relative order between pipe/planes enabling, we need
4465 * to change the workaround. */
4466 haswell_mode_set_planes_workaround(intel_crtc
);
4467 intel_crtc_enable_planes(crtc
);
4470 static void skylake_pfit_disable(struct intel_crtc
*crtc
)
4472 struct drm_device
*dev
= crtc
->base
.dev
;
4473 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4474 int pipe
= crtc
->pipe
;
4476 /* To avoid upsetting the power well on haswell only disable the pfit if
4477 * it's in use. The hw state code will make sure we get this right. */
4478 if (crtc
->config
->pch_pfit
.enabled
) {
4479 I915_WRITE(PS_CTL(pipe
), 0);
4480 I915_WRITE(PS_WIN_POS(pipe
), 0);
4481 I915_WRITE(PS_WIN_SZ(pipe
), 0);
4485 static void ironlake_pfit_disable(struct intel_crtc
*crtc
)
4487 struct drm_device
*dev
= crtc
->base
.dev
;
4488 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4489 int pipe
= crtc
->pipe
;
4491 /* To avoid upsetting the power well on haswell only disable the pfit if
4492 * it's in use. The hw state code will make sure we get this right. */
4493 if (crtc
->config
->pch_pfit
.enabled
) {
4494 I915_WRITE(PF_CTL(pipe
), 0);
4495 I915_WRITE(PF_WIN_POS(pipe
), 0);
4496 I915_WRITE(PF_WIN_SZ(pipe
), 0);
4500 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
4502 struct drm_device
*dev
= crtc
->dev
;
4503 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4504 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4505 struct intel_encoder
*encoder
;
4506 int pipe
= intel_crtc
->pipe
;
4509 if (!intel_crtc
->active
)
4512 intel_crtc_disable_planes(crtc
);
4514 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4515 encoder
->disable(encoder
);
4517 drm_crtc_vblank_off(crtc
);
4518 assert_vblank_disabled(crtc
);
4520 if (intel_crtc
->config
->has_pch_encoder
)
4521 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, false);
4523 intel_disable_pipe(intel_crtc
);
4525 ironlake_pfit_disable(intel_crtc
);
4527 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4528 if (encoder
->post_disable
)
4529 encoder
->post_disable(encoder
);
4531 if (intel_crtc
->config
->has_pch_encoder
) {
4532 ironlake_fdi_disable(crtc
);
4534 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
4536 if (HAS_PCH_CPT(dev
)) {
4537 /* disable TRANS_DP_CTL */
4538 reg
= TRANS_DP_CTL(pipe
);
4539 temp
= I915_READ(reg
);
4540 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
|
4541 TRANS_DP_PORT_SEL_MASK
);
4542 temp
|= TRANS_DP_PORT_SEL_NONE
;
4543 I915_WRITE(reg
, temp
);
4545 /* disable DPLL_SEL */
4546 temp
= I915_READ(PCH_DPLL_SEL
);
4547 temp
&= ~(TRANS_DPLL_ENABLE(pipe
) | TRANS_DPLLB_SEL(pipe
));
4548 I915_WRITE(PCH_DPLL_SEL
, temp
);
4551 /* disable PCH DPLL */
4552 intel_disable_shared_dpll(intel_crtc
);
4554 ironlake_fdi_pll_disable(intel_crtc
);
4557 intel_crtc
->active
= false;
4558 intel_update_watermarks(crtc
);
4560 mutex_lock(&dev
->struct_mutex
);
4561 intel_fbc_update(dev
);
4562 mutex_unlock(&dev
->struct_mutex
);
4565 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
4567 struct drm_device
*dev
= crtc
->dev
;
4568 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4569 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4570 struct intel_encoder
*encoder
;
4571 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
4573 if (!intel_crtc
->active
)
4576 intel_crtc_disable_planes(crtc
);
4578 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4579 intel_opregion_notify_encoder(encoder
, false);
4580 encoder
->disable(encoder
);
4583 drm_crtc_vblank_off(crtc
);
4584 assert_vblank_disabled(crtc
);
4586 if (intel_crtc
->config
->has_pch_encoder
)
4587 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
4589 intel_disable_pipe(intel_crtc
);
4591 if (intel_crtc
->config
->dp_encoder_is_mst
)
4592 intel_ddi_set_vc_payload_alloc(crtc
, false);
4594 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
4596 if (IS_SKYLAKE(dev
))
4597 skylake_pfit_disable(intel_crtc
);
4599 ironlake_pfit_disable(intel_crtc
);
4601 intel_ddi_disable_pipe_clock(intel_crtc
);
4603 if (intel_crtc
->config
->has_pch_encoder
) {
4604 lpt_disable_pch_transcoder(dev_priv
);
4605 intel_ddi_fdi_disable(crtc
);
4608 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4609 if (encoder
->post_disable
)
4610 encoder
->post_disable(encoder
);
4612 intel_crtc
->active
= false;
4613 intel_update_watermarks(crtc
);
4615 mutex_lock(&dev
->struct_mutex
);
4616 intel_fbc_update(dev
);
4617 mutex_unlock(&dev
->struct_mutex
);
4619 if (intel_crtc_to_shared_dpll(intel_crtc
))
4620 intel_disable_shared_dpll(intel_crtc
);
4623 static void ironlake_crtc_off(struct drm_crtc
*crtc
)
4625 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4626 intel_put_shared_dpll(intel_crtc
);
4630 static void i9xx_pfit_enable(struct intel_crtc
*crtc
)
4632 struct drm_device
*dev
= crtc
->base
.dev
;
4633 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4634 struct intel_crtc_state
*pipe_config
= crtc
->config
;
4636 if (!pipe_config
->gmch_pfit
.control
)
4640 * The panel fitter should only be adjusted whilst the pipe is disabled,
4641 * according to register description and PRM.
4643 WARN_ON(I915_READ(PFIT_CONTROL
) & PFIT_ENABLE
);
4644 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
4646 I915_WRITE(PFIT_PGM_RATIOS
, pipe_config
->gmch_pfit
.pgm_ratios
);
4647 I915_WRITE(PFIT_CONTROL
, pipe_config
->gmch_pfit
.control
);
4649 /* Border color in case we don't scale up to the full screen. Black by
4650 * default, change to something else for debugging. */
4651 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
4654 static enum intel_display_power_domain
port_to_power_domain(enum port port
)
4658 return POWER_DOMAIN_PORT_DDI_A_4_LANES
;
4660 return POWER_DOMAIN_PORT_DDI_B_4_LANES
;
4662 return POWER_DOMAIN_PORT_DDI_C_4_LANES
;
4664 return POWER_DOMAIN_PORT_DDI_D_4_LANES
;
4667 return POWER_DOMAIN_PORT_OTHER
;
4671 #define for_each_power_domain(domain, mask) \
4672 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4673 if ((1 << (domain)) & (mask))
4675 enum intel_display_power_domain
4676 intel_display_port_power_domain(struct intel_encoder
*intel_encoder
)
4678 struct drm_device
*dev
= intel_encoder
->base
.dev
;
4679 struct intel_digital_port
*intel_dig_port
;
4681 switch (intel_encoder
->type
) {
4682 case INTEL_OUTPUT_UNKNOWN
:
4683 /* Only DDI platforms should ever use this output type */
4684 WARN_ON_ONCE(!HAS_DDI(dev
));
4685 case INTEL_OUTPUT_DISPLAYPORT
:
4686 case INTEL_OUTPUT_HDMI
:
4687 case INTEL_OUTPUT_EDP
:
4688 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
4689 return port_to_power_domain(intel_dig_port
->port
);
4690 case INTEL_OUTPUT_DP_MST
:
4691 intel_dig_port
= enc_to_mst(&intel_encoder
->base
)->primary
;
4692 return port_to_power_domain(intel_dig_port
->port
);
4693 case INTEL_OUTPUT_ANALOG
:
4694 return POWER_DOMAIN_PORT_CRT
;
4695 case INTEL_OUTPUT_DSI
:
4696 return POWER_DOMAIN_PORT_DSI
;
4698 return POWER_DOMAIN_PORT_OTHER
;
4702 static unsigned long get_crtc_power_domains(struct drm_crtc
*crtc
)
4704 struct drm_device
*dev
= crtc
->dev
;
4705 struct intel_encoder
*intel_encoder
;
4706 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4707 enum pipe pipe
= intel_crtc
->pipe
;
4709 enum transcoder transcoder
;
4711 transcoder
= intel_pipe_to_cpu_transcoder(dev
->dev_private
, pipe
);
4713 mask
= BIT(POWER_DOMAIN_PIPE(pipe
));
4714 mask
|= BIT(POWER_DOMAIN_TRANSCODER(transcoder
));
4715 if (intel_crtc
->config
->pch_pfit
.enabled
||
4716 intel_crtc
->config
->pch_pfit
.force_thru
)
4717 mask
|= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe
));
4719 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
4720 mask
|= BIT(intel_display_port_power_domain(intel_encoder
));
4725 static void modeset_update_crtc_power_domains(struct drm_device
*dev
)
4727 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4728 unsigned long pipe_domains
[I915_MAX_PIPES
] = { 0, };
4729 struct intel_crtc
*crtc
;
4732 * First get all needed power domains, then put all unneeded, to avoid
4733 * any unnecessary toggling of the power wells.
4735 for_each_intel_crtc(dev
, crtc
) {
4736 enum intel_display_power_domain domain
;
4738 if (!crtc
->base
.enabled
)
4741 pipe_domains
[crtc
->pipe
] = get_crtc_power_domains(&crtc
->base
);
4743 for_each_power_domain(domain
, pipe_domains
[crtc
->pipe
])
4744 intel_display_power_get(dev_priv
, domain
);
4747 if (dev_priv
->display
.modeset_global_resources
)
4748 dev_priv
->display
.modeset_global_resources(dev
);
4750 for_each_intel_crtc(dev
, crtc
) {
4751 enum intel_display_power_domain domain
;
4753 for_each_power_domain(domain
, crtc
->enabled_power_domains
)
4754 intel_display_power_put(dev_priv
, domain
);
4756 crtc
->enabled_power_domains
= pipe_domains
[crtc
->pipe
];
4759 intel_display_set_init_power(dev_priv
, false);
4762 /* returns HPLL frequency in kHz */
4763 static int valleyview_get_vco(struct drm_i915_private
*dev_priv
)
4765 int hpll_freq
, vco_freq
[] = { 800, 1600, 2000, 2400 };
4767 /* Obtain SKU information */
4768 mutex_lock(&dev_priv
->dpio_lock
);
4769 hpll_freq
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
) &
4770 CCK_FUSE_HPLL_FREQ_MASK
;
4771 mutex_unlock(&dev_priv
->dpio_lock
);
4773 return vco_freq
[hpll_freq
] * 1000;
4776 static void vlv_update_cdclk(struct drm_device
*dev
)
4778 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4780 dev_priv
->vlv_cdclk_freq
= dev_priv
->display
.get_display_clock_speed(dev
);
4781 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4782 dev_priv
->vlv_cdclk_freq
);
4785 * Program the gmbus_freq based on the cdclk frequency.
4786 * BSpec erroneously claims we should aim for 4MHz, but
4787 * in fact 1MHz is the correct frequency.
4789 I915_WRITE(GMBUSFREQ_VLV
, DIV_ROUND_UP(dev_priv
->vlv_cdclk_freq
, 1000));
4792 /* Adjust CDclk dividers to allow high res or save power if possible */
4793 static void valleyview_set_cdclk(struct drm_device
*dev
, int cdclk
)
4795 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4798 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
) != dev_priv
->vlv_cdclk_freq
);
4800 if (cdclk
>= 320000) /* jump to highest voltage for 400MHz too */
4802 else if (cdclk
== 266667)
4807 mutex_lock(&dev_priv
->rps
.hw_lock
);
4808 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
4809 val
&= ~DSPFREQGUAR_MASK
;
4810 val
|= (cmd
<< DSPFREQGUAR_SHIFT
);
4811 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
4812 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
4813 DSPFREQSTAT_MASK
) == (cmd
<< DSPFREQSTAT_SHIFT
),
4815 DRM_ERROR("timed out waiting for CDclk change\n");
4817 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4819 if (cdclk
== 400000) {
4822 divider
= DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, cdclk
) - 1;
4824 mutex_lock(&dev_priv
->dpio_lock
);
4825 /* adjust cdclk divider */
4826 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
4827 val
&= ~DISPLAY_FREQUENCY_VALUES
;
4829 vlv_cck_write(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
, val
);
4831 if (wait_for((vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
) &
4832 DISPLAY_FREQUENCY_STATUS
) == (divider
<< DISPLAY_FREQUENCY_STATUS_SHIFT
),
4834 DRM_ERROR("timed out waiting for CDclk change\n");
4835 mutex_unlock(&dev_priv
->dpio_lock
);
4838 mutex_lock(&dev_priv
->dpio_lock
);
4839 /* adjust self-refresh exit latency value */
4840 val
= vlv_bunit_read(dev_priv
, BUNIT_REG_BISOC
);
4844 * For high bandwidth configs, we set a higher latency in the bunit
4845 * so that the core display fetch happens in time to avoid underruns.
4847 if (cdclk
== 400000)
4848 val
|= 4500 / 250; /* 4.5 usec */
4850 val
|= 3000 / 250; /* 3.0 usec */
4851 vlv_bunit_write(dev_priv
, BUNIT_REG_BISOC
, val
);
4852 mutex_unlock(&dev_priv
->dpio_lock
);
4854 vlv_update_cdclk(dev
);
4857 static void cherryview_set_cdclk(struct drm_device
*dev
, int cdclk
)
4859 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4862 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
) != dev_priv
->vlv_cdclk_freq
);
4879 MISSING_CASE(cdclk
);
4883 mutex_lock(&dev_priv
->rps
.hw_lock
);
4884 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
4885 val
&= ~DSPFREQGUAR_MASK_CHV
;
4886 val
|= (cmd
<< DSPFREQGUAR_SHIFT_CHV
);
4887 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
4888 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
4889 DSPFREQSTAT_MASK_CHV
) == (cmd
<< DSPFREQSTAT_SHIFT_CHV
),
4891 DRM_ERROR("timed out waiting for CDclk change\n");
4893 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4895 vlv_update_cdclk(dev
);
4898 static int valleyview_calc_cdclk(struct drm_i915_private
*dev_priv
,
4901 int freq_320
= (dev_priv
->hpll_freq
<< 1) % 320000 != 0 ? 333333 : 320000;
4903 /* FIXME: Punit isn't quite ready yet */
4904 if (IS_CHERRYVIEW(dev_priv
->dev
))
4908 * Really only a few cases to deal with, as only 4 CDclks are supported:
4911 * 320/333MHz (depends on HPLL freq)
4913 * So we check to see whether we're above 90% of the lower bin and
4916 * We seem to get an unstable or solid color picture at 200MHz.
4917 * Not sure what's wrong. For now use 200MHz only when all pipes
4920 if (max_pixclk
> freq_320
*9/10)
4922 else if (max_pixclk
> 266667*9/10)
4924 else if (max_pixclk
> 0)
4930 /* compute the max pixel clock for new configuration */
4931 static int intel_mode_max_pixclk(struct drm_i915_private
*dev_priv
)
4933 struct drm_device
*dev
= dev_priv
->dev
;
4934 struct intel_crtc
*intel_crtc
;
4937 for_each_intel_crtc(dev
, intel_crtc
) {
4938 if (intel_crtc
->new_enabled
)
4939 max_pixclk
= max(max_pixclk
,
4940 intel_crtc
->new_config
->base
.adjusted_mode
.crtc_clock
);
4946 static void valleyview_modeset_global_pipes(struct drm_device
*dev
,
4947 unsigned *prepare_pipes
)
4949 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4950 struct intel_crtc
*intel_crtc
;
4951 int max_pixclk
= intel_mode_max_pixclk(dev_priv
);
4953 if (valleyview_calc_cdclk(dev_priv
, max_pixclk
) ==
4954 dev_priv
->vlv_cdclk_freq
)
4957 /* disable/enable all currently active pipes while we change cdclk */
4958 for_each_intel_crtc(dev
, intel_crtc
)
4959 if (intel_crtc
->base
.enabled
)
4960 *prepare_pipes
|= (1 << intel_crtc
->pipe
);
4963 static void valleyview_modeset_global_resources(struct drm_device
*dev
)
4965 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4966 int max_pixclk
= intel_mode_max_pixclk(dev_priv
);
4967 int req_cdclk
= valleyview_calc_cdclk(dev_priv
, max_pixclk
);
4969 if (req_cdclk
!= dev_priv
->vlv_cdclk_freq
) {
4971 * FIXME: We can end up here with all power domains off, yet
4972 * with a CDCLK frequency other than the minimum. To account
4973 * for this take the PIPE-A power domain, which covers the HW
4974 * blocks needed for the following programming. This can be
4975 * removed once it's guaranteed that we get here either with
4976 * the minimum CDCLK set, or the required power domains
4979 intel_display_power_get(dev_priv
, POWER_DOMAIN_PIPE_A
);
4981 if (IS_CHERRYVIEW(dev
))
4982 cherryview_set_cdclk(dev
, req_cdclk
);
4984 valleyview_set_cdclk(dev
, req_cdclk
);
4986 intel_display_power_put(dev_priv
, POWER_DOMAIN_PIPE_A
);
4990 static void valleyview_crtc_enable(struct drm_crtc
*crtc
)
4992 struct drm_device
*dev
= crtc
->dev
;
4993 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4994 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4995 struct intel_encoder
*encoder
;
4996 int pipe
= intel_crtc
->pipe
;
4999 WARN_ON(!crtc
->enabled
);
5001 if (intel_crtc
->active
)
5004 is_dsi
= intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
);
5007 if (IS_CHERRYVIEW(dev
))
5008 chv_prepare_pll(intel_crtc
, intel_crtc
->config
);
5010 vlv_prepare_pll(intel_crtc
, intel_crtc
->config
);
5013 if (intel_crtc
->config
->has_dp_encoder
)
5014 intel_dp_set_m_n(intel_crtc
);
5016 intel_set_pipe_timings(intel_crtc
);
5018 if (IS_CHERRYVIEW(dev
) && pipe
== PIPE_B
) {
5019 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5021 I915_WRITE(CHV_BLEND(pipe
), CHV_BLEND_LEGACY
);
5022 I915_WRITE(CHV_CANVAS(pipe
), 0);
5025 i9xx_set_pipeconf(intel_crtc
);
5027 intel_crtc
->active
= true;
5029 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5031 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5032 if (encoder
->pre_pll_enable
)
5033 encoder
->pre_pll_enable(encoder
);
5036 if (IS_CHERRYVIEW(dev
))
5037 chv_enable_pll(intel_crtc
, intel_crtc
->config
);
5039 vlv_enable_pll(intel_crtc
, intel_crtc
->config
);
5042 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5043 if (encoder
->pre_enable
)
5044 encoder
->pre_enable(encoder
);
5046 i9xx_pfit_enable(intel_crtc
);
5048 intel_crtc_load_lut(crtc
);
5050 intel_update_watermarks(crtc
);
5051 intel_enable_pipe(intel_crtc
);
5053 assert_vblank_disabled(crtc
);
5054 drm_crtc_vblank_on(crtc
);
5056 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5057 encoder
->enable(encoder
);
5059 intel_crtc_enable_planes(crtc
);
5061 /* Underruns don't raise interrupts, so check manually. */
5062 i9xx_check_fifo_underruns(dev_priv
);
5065 static void i9xx_set_pll_dividers(struct intel_crtc
*crtc
)
5067 struct drm_device
*dev
= crtc
->base
.dev
;
5068 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5070 I915_WRITE(FP0(crtc
->pipe
), crtc
->config
->dpll_hw_state
.fp0
);
5071 I915_WRITE(FP1(crtc
->pipe
), crtc
->config
->dpll_hw_state
.fp1
);
5074 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
5076 struct drm_device
*dev
= crtc
->dev
;
5077 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5078 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5079 struct intel_encoder
*encoder
;
5080 int pipe
= intel_crtc
->pipe
;
5082 WARN_ON(!crtc
->enabled
);
5084 if (intel_crtc
->active
)
5087 i9xx_set_pll_dividers(intel_crtc
);
5089 if (intel_crtc
->config
->has_dp_encoder
)
5090 intel_dp_set_m_n(intel_crtc
);
5092 intel_set_pipe_timings(intel_crtc
);
5094 i9xx_set_pipeconf(intel_crtc
);
5096 intel_crtc
->active
= true;
5099 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5101 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5102 if (encoder
->pre_enable
)
5103 encoder
->pre_enable(encoder
);
5105 i9xx_enable_pll(intel_crtc
);
5107 i9xx_pfit_enable(intel_crtc
);
5109 intel_crtc_load_lut(crtc
);
5111 intel_update_watermarks(crtc
);
5112 intel_enable_pipe(intel_crtc
);
5114 assert_vblank_disabled(crtc
);
5115 drm_crtc_vblank_on(crtc
);
5117 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5118 encoder
->enable(encoder
);
5120 intel_crtc_enable_planes(crtc
);
5123 * Gen2 reports pipe underruns whenever all planes are disabled.
5124 * So don't enable underrun reporting before at least some planes
5126 * FIXME: Need to fix the logic to work when we turn off all planes
5127 * but leave the pipe running.
5130 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5132 /* Underruns don't raise interrupts, so check manually. */
5133 i9xx_check_fifo_underruns(dev_priv
);
5136 static void i9xx_pfit_disable(struct intel_crtc
*crtc
)
5138 struct drm_device
*dev
= crtc
->base
.dev
;
5139 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5141 if (!crtc
->config
->gmch_pfit
.control
)
5144 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
5146 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5147 I915_READ(PFIT_CONTROL
));
5148 I915_WRITE(PFIT_CONTROL
, 0);
5151 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
5153 struct drm_device
*dev
= crtc
->dev
;
5154 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5155 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5156 struct intel_encoder
*encoder
;
5157 int pipe
= intel_crtc
->pipe
;
5159 if (!intel_crtc
->active
)
5163 * Gen2 reports pipe underruns whenever all planes are disabled.
5164 * So diasble underrun reporting before all the planes get disabled.
5165 * FIXME: Need to fix the logic to work when we turn off all planes
5166 * but leave the pipe running.
5169 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
5172 * Vblank time updates from the shadow to live plane control register
5173 * are blocked if the memory self-refresh mode is active at that
5174 * moment. So to make sure the plane gets truly disabled, disable
5175 * first the self-refresh mode. The self-refresh enable bit in turn
5176 * will be checked/applied by the HW only at the next frame start
5177 * event which is after the vblank start event, so we need to have a
5178 * wait-for-vblank between disabling the plane and the pipe.
5180 intel_set_memory_cxsr(dev_priv
, false);
5181 intel_crtc_disable_planes(crtc
);
5184 * On gen2 planes are double buffered but the pipe isn't, so we must
5185 * wait for planes to fully turn off before disabling the pipe.
5186 * We also need to wait on all gmch platforms because of the
5187 * self-refresh mode constraint explained above.
5189 intel_wait_for_vblank(dev
, pipe
);
5191 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5192 encoder
->disable(encoder
);
5194 drm_crtc_vblank_off(crtc
);
5195 assert_vblank_disabled(crtc
);
5197 intel_disable_pipe(intel_crtc
);
5199 i9xx_pfit_disable(intel_crtc
);
5201 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5202 if (encoder
->post_disable
)
5203 encoder
->post_disable(encoder
);
5205 if (!intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
)) {
5206 if (IS_CHERRYVIEW(dev
))
5207 chv_disable_pll(dev_priv
, pipe
);
5208 else if (IS_VALLEYVIEW(dev
))
5209 vlv_disable_pll(dev_priv
, pipe
);
5211 i9xx_disable_pll(intel_crtc
);
5215 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
5217 intel_crtc
->active
= false;
5218 intel_update_watermarks(crtc
);
5220 mutex_lock(&dev
->struct_mutex
);
5221 intel_fbc_update(dev
);
5222 mutex_unlock(&dev
->struct_mutex
);
5225 static void i9xx_crtc_off(struct drm_crtc
*crtc
)
5229 /* Master function to enable/disable CRTC and corresponding power wells */
5230 void intel_crtc_control(struct drm_crtc
*crtc
, bool enable
)
5232 struct drm_device
*dev
= crtc
->dev
;
5233 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5234 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5235 enum intel_display_power_domain domain
;
5236 unsigned long domains
;
5239 if (!intel_crtc
->active
) {
5240 domains
= get_crtc_power_domains(crtc
);
5241 for_each_power_domain(domain
, domains
)
5242 intel_display_power_get(dev_priv
, domain
);
5243 intel_crtc
->enabled_power_domains
= domains
;
5245 dev_priv
->display
.crtc_enable(crtc
);
5248 if (intel_crtc
->active
) {
5249 dev_priv
->display
.crtc_disable(crtc
);
5251 domains
= intel_crtc
->enabled_power_domains
;
5252 for_each_power_domain(domain
, domains
)
5253 intel_display_power_put(dev_priv
, domain
);
5254 intel_crtc
->enabled_power_domains
= 0;
5260 * Sets the power management mode of the pipe and plane.
5262 void intel_crtc_update_dpms(struct drm_crtc
*crtc
)
5264 struct drm_device
*dev
= crtc
->dev
;
5265 struct intel_encoder
*intel_encoder
;
5266 bool enable
= false;
5268 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
5269 enable
|= intel_encoder
->connectors_active
;
5271 intel_crtc_control(crtc
, enable
);
5274 static void intel_crtc_disable(struct drm_crtc
*crtc
)
5276 struct drm_device
*dev
= crtc
->dev
;
5277 struct drm_connector
*connector
;
5278 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5280 /* crtc should still be enabled when we disable it. */
5281 WARN_ON(!crtc
->enabled
);
5283 dev_priv
->display
.crtc_disable(crtc
);
5284 dev_priv
->display
.off(crtc
);
5286 crtc
->primary
->funcs
->disable_plane(crtc
->primary
);
5288 /* Update computed state. */
5289 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
5290 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
5293 if (connector
->encoder
->crtc
!= crtc
)
5296 connector
->dpms
= DRM_MODE_DPMS_OFF
;
5297 to_intel_encoder(connector
->encoder
)->connectors_active
= false;
5301 void intel_encoder_destroy(struct drm_encoder
*encoder
)
5303 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
5305 drm_encoder_cleanup(encoder
);
5306 kfree(intel_encoder
);
5309 /* Simple dpms helper for encoders with just one connector, no cloning and only
5310 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5311 * state of the entire output pipe. */
5312 static void intel_encoder_dpms(struct intel_encoder
*encoder
, int mode
)
5314 if (mode
== DRM_MODE_DPMS_ON
) {
5315 encoder
->connectors_active
= true;
5317 intel_crtc_update_dpms(encoder
->base
.crtc
);
5319 encoder
->connectors_active
= false;
5321 intel_crtc_update_dpms(encoder
->base
.crtc
);
5325 /* Cross check the actual hw state with our own modeset state tracking (and it's
5326 * internal consistency). */
5327 static void intel_connector_check_state(struct intel_connector
*connector
)
5329 if (connector
->get_hw_state(connector
)) {
5330 struct intel_encoder
*encoder
= connector
->encoder
;
5331 struct drm_crtc
*crtc
;
5332 bool encoder_enabled
;
5335 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5336 connector
->base
.base
.id
,
5337 connector
->base
.name
);
5339 /* there is no real hw state for MST connectors */
5340 if (connector
->mst_port
)
5343 I915_STATE_WARN(connector
->base
.dpms
== DRM_MODE_DPMS_OFF
,
5344 "wrong connector dpms state\n");
5345 I915_STATE_WARN(connector
->base
.encoder
!= &encoder
->base
,
5346 "active connector not linked to encoder\n");
5349 I915_STATE_WARN(!encoder
->connectors_active
,
5350 "encoder->connectors_active not set\n");
5352 encoder_enabled
= encoder
->get_hw_state(encoder
, &pipe
);
5353 I915_STATE_WARN(!encoder_enabled
, "encoder not enabled\n");
5354 if (I915_STATE_WARN_ON(!encoder
->base
.crtc
))
5357 crtc
= encoder
->base
.crtc
;
5359 I915_STATE_WARN(!crtc
->enabled
, "crtc not enabled\n");
5360 I915_STATE_WARN(!to_intel_crtc(crtc
)->active
, "crtc not active\n");
5361 I915_STATE_WARN(pipe
!= to_intel_crtc(crtc
)->pipe
,
5362 "encoder active on the wrong pipe\n");
5367 /* Even simpler default implementation, if there's really no special case to
5369 void intel_connector_dpms(struct drm_connector
*connector
, int mode
)
5371 /* All the simple cases only support two dpms states. */
5372 if (mode
!= DRM_MODE_DPMS_ON
)
5373 mode
= DRM_MODE_DPMS_OFF
;
5375 if (mode
== connector
->dpms
)
5378 connector
->dpms
= mode
;
5380 /* Only need to change hw state when actually enabled */
5381 if (connector
->encoder
)
5382 intel_encoder_dpms(to_intel_encoder(connector
->encoder
), mode
);
5384 intel_modeset_check_state(connector
->dev
);
5387 /* Simple connector->get_hw_state implementation for encoders that support only
5388 * one connector and no cloning and hence the encoder state determines the state
5389 * of the connector. */
5390 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
5393 struct intel_encoder
*encoder
= connector
->encoder
;
5395 return encoder
->get_hw_state(encoder
, &pipe
);
5398 static bool ironlake_check_fdi_lanes(struct drm_device
*dev
, enum pipe pipe
,
5399 struct intel_crtc_state
*pipe_config
)
5401 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5402 struct intel_crtc
*pipe_B_crtc
=
5403 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
5405 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5406 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5407 if (pipe_config
->fdi_lanes
> 4) {
5408 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5409 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5413 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
5414 if (pipe_config
->fdi_lanes
> 2) {
5415 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5416 pipe_config
->fdi_lanes
);
5423 if (INTEL_INFO(dev
)->num_pipes
== 2)
5426 /* Ivybridge 3 pipe is really complicated */
5431 if (dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]->enabled
&&
5432 pipe_config
->fdi_lanes
> 2) {
5433 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5434 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5439 if (!pipe_has_enabled_pch(pipe_B_crtc
) ||
5440 pipe_B_crtc
->config
->fdi_lanes
<= 2) {
5441 if (pipe_config
->fdi_lanes
> 2) {
5442 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5443 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5447 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5457 static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc
,
5458 struct intel_crtc_state
*pipe_config
)
5460 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5461 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
5462 int lane
, link_bw
, fdi_dotclock
;
5463 bool setup_ok
, needs_recompute
= false;
5466 /* FDI is a binary signal running at ~2.7GHz, encoding
5467 * each output octet as 10 bits. The actual frequency
5468 * is stored as a divider into a 100MHz clock, and the
5469 * mode pixel clock is stored in units of 1KHz.
5470 * Hence the bw of each lane in terms of the mode signal
5473 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
5475 fdi_dotclock
= adjusted_mode
->crtc_clock
;
5477 lane
= ironlake_get_lanes_required(fdi_dotclock
, link_bw
,
5478 pipe_config
->pipe_bpp
);
5480 pipe_config
->fdi_lanes
= lane
;
5482 intel_link_compute_m_n(pipe_config
->pipe_bpp
, lane
, fdi_dotclock
,
5483 link_bw
, &pipe_config
->fdi_m_n
);
5485 setup_ok
= ironlake_check_fdi_lanes(intel_crtc
->base
.dev
,
5486 intel_crtc
->pipe
, pipe_config
);
5487 if (!setup_ok
&& pipe_config
->pipe_bpp
> 6*3) {
5488 pipe_config
->pipe_bpp
-= 2*3;
5489 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5490 pipe_config
->pipe_bpp
);
5491 needs_recompute
= true;
5492 pipe_config
->bw_constrained
= true;
5497 if (needs_recompute
)
5500 return setup_ok
? 0 : -EINVAL
;
5503 static void hsw_compute_ips_config(struct intel_crtc
*crtc
,
5504 struct intel_crtc_state
*pipe_config
)
5506 pipe_config
->ips_enabled
= i915
.enable_ips
&&
5507 hsw_crtc_supports_ips(crtc
) &&
5508 pipe_config
->pipe_bpp
<= 24;
5511 static int intel_crtc_compute_config(struct intel_crtc
*crtc
,
5512 struct intel_crtc_state
*pipe_config
)
5514 struct drm_device
*dev
= crtc
->base
.dev
;
5515 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5516 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
5518 /* FIXME should check pixel clock limits on all platforms */
5519 if (INTEL_INFO(dev
)->gen
< 4) {
5521 dev_priv
->display
.get_display_clock_speed(dev
);
5524 * Enable pixel doubling when the dot clock
5525 * is > 90% of the (display) core speed.
5527 * GDG double wide on either pipe,
5528 * otherwise pipe A only.
5530 if ((crtc
->pipe
== PIPE_A
|| IS_I915G(dev
)) &&
5531 adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10) {
5533 pipe_config
->double_wide
= true;
5536 if (adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10)
5541 * Pipe horizontal size must be even in:
5543 * - LVDS dual channel mode
5544 * - Double wide pipe
5546 if ((intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
5547 intel_is_dual_link_lvds(dev
)) || pipe_config
->double_wide
)
5548 pipe_config
->pipe_src_w
&= ~1;
5550 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5551 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5553 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
5554 adjusted_mode
->hsync_start
== adjusted_mode
->hdisplay
)
5557 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) && pipe_config
->pipe_bpp
> 10*3) {
5558 pipe_config
->pipe_bpp
= 10*3; /* 12bpc is gen5+ */
5559 } else if (INTEL_INFO(dev
)->gen
<= 4 && pipe_config
->pipe_bpp
> 8*3) {
5560 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5562 pipe_config
->pipe_bpp
= 8*3;
5566 hsw_compute_ips_config(crtc
, pipe_config
);
5568 if (pipe_config
->has_pch_encoder
)
5569 return ironlake_fdi_compute_config(crtc
, pipe_config
);
5574 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
5576 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5580 /* FIXME: Punit isn't quite ready yet */
5581 if (IS_CHERRYVIEW(dev
))
5584 if (dev_priv
->hpll_freq
== 0)
5585 dev_priv
->hpll_freq
= valleyview_get_vco(dev_priv
);
5587 mutex_lock(&dev_priv
->dpio_lock
);
5588 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
5589 mutex_unlock(&dev_priv
->dpio_lock
);
5591 divider
= val
& DISPLAY_FREQUENCY_VALUES
;
5593 WARN((val
& DISPLAY_FREQUENCY_STATUS
) !=
5594 (divider
<< DISPLAY_FREQUENCY_STATUS_SHIFT
),
5595 "cdclk change in progress\n");
5597 return DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, divider
+ 1);
5600 static int i945_get_display_clock_speed(struct drm_device
*dev
)
5605 static int i915_get_display_clock_speed(struct drm_device
*dev
)
5610 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
5615 static int pnv_get_display_clock_speed(struct drm_device
*dev
)
5619 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
5621 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
5622 case GC_DISPLAY_CLOCK_267_MHZ_PNV
:
5624 case GC_DISPLAY_CLOCK_333_MHZ_PNV
:
5626 case GC_DISPLAY_CLOCK_444_MHZ_PNV
:
5628 case GC_DISPLAY_CLOCK_200_MHZ_PNV
:
5631 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc
);
5632 case GC_DISPLAY_CLOCK_133_MHZ_PNV
:
5634 case GC_DISPLAY_CLOCK_167_MHZ_PNV
:
5639 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
5643 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
5645 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
5648 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
5649 case GC_DISPLAY_CLOCK_333_MHZ
:
5652 case GC_DISPLAY_CLOCK_190_200_MHZ
:
5658 static int i865_get_display_clock_speed(struct drm_device
*dev
)
5663 static int i855_get_display_clock_speed(struct drm_device
*dev
)
5666 /* Assume that the hardware is in the high speed state. This
5667 * should be the default.
5669 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
5670 case GC_CLOCK_133_200
:
5671 case GC_CLOCK_100_200
:
5673 case GC_CLOCK_166_250
:
5675 case GC_CLOCK_100_133
:
5679 /* Shouldn't happen */
5683 static int i830_get_display_clock_speed(struct drm_device
*dev
)
5689 intel_reduce_m_n_ratio(uint32_t *num
, uint32_t *den
)
5691 while (*num
> DATA_LINK_M_N_MASK
||
5692 *den
> DATA_LINK_M_N_MASK
) {
5698 static void compute_m_n(unsigned int m
, unsigned int n
,
5699 uint32_t *ret_m
, uint32_t *ret_n
)
5701 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
5702 *ret_m
= div_u64((uint64_t) m
* *ret_n
, n
);
5703 intel_reduce_m_n_ratio(ret_m
, ret_n
);
5707 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
5708 int pixel_clock
, int link_clock
,
5709 struct intel_link_m_n
*m_n
)
5713 compute_m_n(bits_per_pixel
* pixel_clock
,
5714 link_clock
* nlanes
* 8,
5715 &m_n
->gmch_m
, &m_n
->gmch_n
);
5717 compute_m_n(pixel_clock
, link_clock
,
5718 &m_n
->link_m
, &m_n
->link_n
);
5721 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
5723 if (i915
.panel_use_ssc
>= 0)
5724 return i915
.panel_use_ssc
!= 0;
5725 return dev_priv
->vbt
.lvds_use_ssc
5726 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
5729 static int i9xx_get_refclk(struct intel_crtc
*crtc
, int num_connectors
)
5731 struct drm_device
*dev
= crtc
->base
.dev
;
5732 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5735 if (IS_VALLEYVIEW(dev
)) {
5737 } else if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
) &&
5738 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
5739 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
5740 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
5741 } else if (!IS_GEN2(dev
)) {
5750 static uint32_t pnv_dpll_compute_fp(struct dpll
*dpll
)
5752 return (1 << dpll
->n
) << 16 | dpll
->m2
;
5755 static uint32_t i9xx_dpll_compute_fp(struct dpll
*dpll
)
5757 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
5760 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
5761 struct intel_crtc_state
*crtc_state
,
5762 intel_clock_t
*reduced_clock
)
5764 struct drm_device
*dev
= crtc
->base
.dev
;
5767 if (IS_PINEVIEW(dev
)) {
5768 fp
= pnv_dpll_compute_fp(&crtc_state
->dpll
);
5770 fp2
= pnv_dpll_compute_fp(reduced_clock
);
5772 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
5774 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
5777 crtc_state
->dpll_hw_state
.fp0
= fp
;
5779 crtc
->lowfreq_avail
= false;
5780 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
) &&
5781 reduced_clock
&& i915
.powersave
) {
5782 crtc_state
->dpll_hw_state
.fp1
= fp2
;
5783 crtc
->lowfreq_avail
= true;
5785 crtc_state
->dpll_hw_state
.fp1
= fp
;
5789 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
, enum pipe
5795 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5796 * and set it to a reasonable value instead.
5798 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
5799 reg_val
&= 0xffffff00;
5800 reg_val
|= 0x00000030;
5801 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
5803 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
5804 reg_val
&= 0x8cffffff;
5805 reg_val
= 0x8c000000;
5806 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
5808 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
5809 reg_val
&= 0xffffff00;
5810 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
5812 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
5813 reg_val
&= 0x00ffffff;
5814 reg_val
|= 0xb0000000;
5815 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
5818 static void intel_pch_transcoder_set_m_n(struct intel_crtc
*crtc
,
5819 struct intel_link_m_n
*m_n
)
5821 struct drm_device
*dev
= crtc
->base
.dev
;
5822 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5823 int pipe
= crtc
->pipe
;
5825 I915_WRITE(PCH_TRANS_DATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5826 I915_WRITE(PCH_TRANS_DATA_N1(pipe
), m_n
->gmch_n
);
5827 I915_WRITE(PCH_TRANS_LINK_M1(pipe
), m_n
->link_m
);
5828 I915_WRITE(PCH_TRANS_LINK_N1(pipe
), m_n
->link_n
);
5831 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
5832 struct intel_link_m_n
*m_n
,
5833 struct intel_link_m_n
*m2_n2
)
5835 struct drm_device
*dev
= crtc
->base
.dev
;
5836 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5837 int pipe
= crtc
->pipe
;
5838 enum transcoder transcoder
= crtc
->config
->cpu_transcoder
;
5840 if (INTEL_INFO(dev
)->gen
>= 5) {
5841 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5842 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
5843 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
5844 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
5845 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5846 * for gen < 8) and if DRRS is supported (to make sure the
5847 * registers are not unnecessarily accessed).
5849 if (m2_n2
&& INTEL_INFO(dev
)->gen
< 8 &&
5850 crtc
->config
->has_drrs
) {
5851 I915_WRITE(PIPE_DATA_M2(transcoder
),
5852 TU_SIZE(m2_n2
->tu
) | m2_n2
->gmch_m
);
5853 I915_WRITE(PIPE_DATA_N2(transcoder
), m2_n2
->gmch_n
);
5854 I915_WRITE(PIPE_LINK_M2(transcoder
), m2_n2
->link_m
);
5855 I915_WRITE(PIPE_LINK_N2(transcoder
), m2_n2
->link_n
);
5858 I915_WRITE(PIPE_DATA_M_G4X(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5859 I915_WRITE(PIPE_DATA_N_G4X(pipe
), m_n
->gmch_n
);
5860 I915_WRITE(PIPE_LINK_M_G4X(pipe
), m_n
->link_m
);
5861 I915_WRITE(PIPE_LINK_N_G4X(pipe
), m_n
->link_n
);
5865 void intel_dp_set_m_n(struct intel_crtc
*crtc
)
5867 if (crtc
->config
->has_pch_encoder
)
5868 intel_pch_transcoder_set_m_n(crtc
, &crtc
->config
->dp_m_n
);
5870 intel_cpu_transcoder_set_m_n(crtc
, &crtc
->config
->dp_m_n
,
5871 &crtc
->config
->dp_m2_n2
);
5874 static void vlv_update_pll(struct intel_crtc
*crtc
,
5875 struct intel_crtc_state
*pipe_config
)
5880 * Enable DPIO clock input. We should never disable the reference
5881 * clock for pipe B, since VGA hotplug / manual detection depends
5884 dpll
= DPLL_EXT_BUFFER_ENABLE_VLV
| DPLL_REFA_CLK_ENABLE_VLV
|
5885 DPLL_VGA_MODE_DIS
| DPLL_INTEGRATED_CLOCK_VLV
;
5886 /* We should never disable this, set it here for state tracking */
5887 if (crtc
->pipe
== PIPE_B
)
5888 dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
5889 dpll
|= DPLL_VCO_ENABLE
;
5890 pipe_config
->dpll_hw_state
.dpll
= dpll
;
5892 dpll_md
= (pipe_config
->pixel_multiplier
- 1)
5893 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
5894 pipe_config
->dpll_hw_state
.dpll_md
= dpll_md
;
5897 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
5898 const struct intel_crtc_state
*pipe_config
)
5900 struct drm_device
*dev
= crtc
->base
.dev
;
5901 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5902 int pipe
= crtc
->pipe
;
5904 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
5905 u32 coreclk
, reg_val
;
5907 mutex_lock(&dev_priv
->dpio_lock
);
5909 bestn
= pipe_config
->dpll
.n
;
5910 bestm1
= pipe_config
->dpll
.m1
;
5911 bestm2
= pipe_config
->dpll
.m2
;
5912 bestp1
= pipe_config
->dpll
.p1
;
5913 bestp2
= pipe_config
->dpll
.p2
;
5915 /* See eDP HDMI DPIO driver vbios notes doc */
5917 /* PLL B needs special handling */
5919 vlv_pllb_recal_opamp(dev_priv
, pipe
);
5921 /* Set up Tx target for periodic Rcomp update */
5922 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9_BCAST
, 0x0100000f);
5924 /* Disable target IRef on PLL */
5925 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW8(pipe
));
5926 reg_val
&= 0x00ffffff;
5927 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW8(pipe
), reg_val
);
5929 /* Disable fast lock */
5930 vlv_dpio_write(dev_priv
, pipe
, VLV_CMN_DW0
, 0x610);
5932 /* Set idtafcrecal before PLL is enabled */
5933 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
5934 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
5935 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
5936 mdiv
|= (1 << DPIO_K_SHIFT
);
5939 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5940 * but we don't support that).
5941 * Note: don't use the DAC post divider as it seems unstable.
5943 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
5944 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
5946 mdiv
|= DPIO_ENABLE_CALIBRATION
;
5947 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
5949 /* Set HBR and RBR LPF coefficients */
5950 if (pipe_config
->port_clock
== 162000 ||
5951 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
) ||
5952 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
))
5953 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
5956 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
5959 if (pipe_config
->has_dp_encoder
) {
5960 /* Use SSC source */
5962 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5965 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5967 } else { /* HDMI or VGA */
5968 /* Use bend source */
5970 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5973 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5977 coreclk
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW7(pipe
));
5978 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
5979 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
5980 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))
5981 coreclk
|= 0x01000000;
5982 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW7(pipe
), coreclk
);
5984 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW11(pipe
), 0x87871000);
5985 mutex_unlock(&dev_priv
->dpio_lock
);
5988 static void chv_update_pll(struct intel_crtc
*crtc
,
5989 struct intel_crtc_state
*pipe_config
)
5991 pipe_config
->dpll_hw_state
.dpll
= DPLL_SSC_REF_CLOCK_CHV
|
5992 DPLL_REFA_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
|
5994 if (crtc
->pipe
!= PIPE_A
)
5995 pipe_config
->dpll_hw_state
.dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
5997 pipe_config
->dpll_hw_state
.dpll_md
=
5998 (pipe_config
->pixel_multiplier
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
6001 static void chv_prepare_pll(struct intel_crtc
*crtc
,
6002 const struct intel_crtc_state
*pipe_config
)
6004 struct drm_device
*dev
= crtc
->base
.dev
;
6005 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6006 int pipe
= crtc
->pipe
;
6007 int dpll_reg
= DPLL(crtc
->pipe
);
6008 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
6009 u32 loopfilter
, intcoeff
;
6010 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
, bestm2_frac
;
6013 bestn
= pipe_config
->dpll
.n
;
6014 bestm2_frac
= pipe_config
->dpll
.m2
& 0x3fffff;
6015 bestm1
= pipe_config
->dpll
.m1
;
6016 bestm2
= pipe_config
->dpll
.m2
>> 22;
6017 bestp1
= pipe_config
->dpll
.p1
;
6018 bestp2
= pipe_config
->dpll
.p2
;
6021 * Enable Refclk and SSC
6023 I915_WRITE(dpll_reg
,
6024 pipe_config
->dpll_hw_state
.dpll
& ~DPLL_VCO_ENABLE
);
6026 mutex_lock(&dev_priv
->dpio_lock
);
6028 /* p1 and p2 divider */
6029 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW13(port
),
6030 5 << DPIO_CHV_S1_DIV_SHIFT
|
6031 bestp1
<< DPIO_CHV_P1_DIV_SHIFT
|
6032 bestp2
<< DPIO_CHV_P2_DIV_SHIFT
|
6033 1 << DPIO_CHV_K_DIV_SHIFT
);
6035 /* Feedback post-divider - m2 */
6036 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW0(port
), bestm2
);
6038 /* Feedback refclk divider - n and m1 */
6039 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW1(port
),
6040 DPIO_CHV_M1_DIV_BY_2
|
6041 1 << DPIO_CHV_N_DIV_SHIFT
);
6043 /* M2 fraction division */
6044 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW2(port
), bestm2_frac
);
6046 /* M2 fraction division enable */
6047 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW3(port
),
6048 DPIO_CHV_FRAC_DIV_EN
|
6049 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT
));
6052 refclk
= i9xx_get_refclk(crtc
, 0);
6053 loopfilter
= 5 << DPIO_CHV_PROP_COEFF_SHIFT
|
6054 2 << DPIO_CHV_GAIN_CTRL_SHIFT
;
6055 if (refclk
== 100000)
6057 else if (refclk
== 38400)
6061 loopfilter
|= intcoeff
<< DPIO_CHV_INT_COEFF_SHIFT
;
6062 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW6(port
), loopfilter
);
6065 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
),
6066 vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
)) |
6069 mutex_unlock(&dev_priv
->dpio_lock
);
6073 * vlv_force_pll_on - forcibly enable just the PLL
6074 * @dev_priv: i915 private structure
6075 * @pipe: pipe PLL to enable
6076 * @dpll: PLL configuration
6078 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6079 * in cases where we need the PLL enabled even when @pipe is not going to
6082 void vlv_force_pll_on(struct drm_device
*dev
, enum pipe pipe
,
6083 const struct dpll
*dpll
)
6085 struct intel_crtc
*crtc
=
6086 to_intel_crtc(intel_get_crtc_for_pipe(dev
, pipe
));
6087 struct intel_crtc_state pipe_config
= {
6088 .pixel_multiplier
= 1,
6092 if (IS_CHERRYVIEW(dev
)) {
6093 chv_update_pll(crtc
, &pipe_config
);
6094 chv_prepare_pll(crtc
, &pipe_config
);
6095 chv_enable_pll(crtc
, &pipe_config
);
6097 vlv_update_pll(crtc
, &pipe_config
);
6098 vlv_prepare_pll(crtc
, &pipe_config
);
6099 vlv_enable_pll(crtc
, &pipe_config
);
6104 * vlv_force_pll_off - forcibly disable just the PLL
6105 * @dev_priv: i915 private structure
6106 * @pipe: pipe PLL to disable
6108 * Disable the PLL for @pipe. To be used in cases where we need
6109 * the PLL enabled even when @pipe is not going to be enabled.
6111 void vlv_force_pll_off(struct drm_device
*dev
, enum pipe pipe
)
6113 if (IS_CHERRYVIEW(dev
))
6114 chv_disable_pll(to_i915(dev
), pipe
);
6116 vlv_disable_pll(to_i915(dev
), pipe
);
6119 static void i9xx_update_pll(struct intel_crtc
*crtc
,
6120 struct intel_crtc_state
*crtc_state
,
6121 intel_clock_t
*reduced_clock
,
6124 struct drm_device
*dev
= crtc
->base
.dev
;
6125 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6128 struct dpll
*clock
= &crtc_state
->dpll
;
6130 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
6132 is_sdvo
= intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_SDVO
) ||
6133 intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_HDMI
);
6135 dpll
= DPLL_VGA_MODE_DIS
;
6137 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
))
6138 dpll
|= DPLLB_MODE_LVDS
;
6140 dpll
|= DPLLB_MODE_DAC_SERIAL
;
6142 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
6143 dpll
|= (crtc_state
->pixel_multiplier
- 1)
6144 << SDVO_MULTIPLIER_SHIFT_HIRES
;
6148 dpll
|= DPLL_SDVO_HIGH_SPEED
;
6150 if (crtc_state
->has_dp_encoder
)
6151 dpll
|= DPLL_SDVO_HIGH_SPEED
;
6153 /* compute bitmask from p1 value */
6154 if (IS_PINEVIEW(dev
))
6155 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
6157 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
6158 if (IS_G4X(dev
) && reduced_clock
)
6159 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
6161 switch (clock
->p2
) {
6163 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
6166 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
6169 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
6172 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
6175 if (INTEL_INFO(dev
)->gen
>= 4)
6176 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
6178 if (crtc_state
->sdvo_tv_clock
)
6179 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
6180 else if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
) &&
6181 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
6182 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
6184 dpll
|= PLL_REF_INPUT_DREFCLK
;
6186 dpll
|= DPLL_VCO_ENABLE
;
6187 crtc_state
->dpll_hw_state
.dpll
= dpll
;
6189 if (INTEL_INFO(dev
)->gen
>= 4) {
6190 u32 dpll_md
= (crtc_state
->pixel_multiplier
- 1)
6191 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
6192 crtc_state
->dpll_hw_state
.dpll_md
= dpll_md
;
6196 static void i8xx_update_pll(struct intel_crtc
*crtc
,
6197 struct intel_crtc_state
*crtc_state
,
6198 intel_clock_t
*reduced_clock
,
6201 struct drm_device
*dev
= crtc
->base
.dev
;
6202 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6204 struct dpll
*clock
= &crtc_state
->dpll
;
6206 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
6208 dpll
= DPLL_VGA_MODE_DIS
;
6210 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
)) {
6211 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
6214 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
6216 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
6218 dpll
|= PLL_P2_DIVIDE_BY_4
;
6221 if (!IS_I830(dev
) && intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_DVO
))
6222 dpll
|= DPLL_DVO_2X_MODE
;
6224 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
) &&
6225 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
6226 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
6228 dpll
|= PLL_REF_INPUT_DREFCLK
;
6230 dpll
|= DPLL_VCO_ENABLE
;
6231 crtc_state
->dpll_hw_state
.dpll
= dpll
;
6234 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
)
6236 struct drm_device
*dev
= intel_crtc
->base
.dev
;
6237 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6238 enum pipe pipe
= intel_crtc
->pipe
;
6239 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
6240 struct drm_display_mode
*adjusted_mode
=
6241 &intel_crtc
->config
->base
.adjusted_mode
;
6242 uint32_t crtc_vtotal
, crtc_vblank_end
;
6245 /* We need to be careful not to changed the adjusted mode, for otherwise
6246 * the hw state checker will get angry at the mismatch. */
6247 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
6248 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
6250 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
6251 /* the chip adds 2 halflines automatically */
6253 crtc_vblank_end
-= 1;
6255 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
6256 vsyncshift
= (adjusted_mode
->crtc_htotal
- 1) / 2;
6258 vsyncshift
= adjusted_mode
->crtc_hsync_start
-
6259 adjusted_mode
->crtc_htotal
/ 2;
6261 vsyncshift
+= adjusted_mode
->crtc_htotal
;
6264 if (INTEL_INFO(dev
)->gen
> 3)
6265 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
6267 I915_WRITE(HTOTAL(cpu_transcoder
),
6268 (adjusted_mode
->crtc_hdisplay
- 1) |
6269 ((adjusted_mode
->crtc_htotal
- 1) << 16));
6270 I915_WRITE(HBLANK(cpu_transcoder
),
6271 (adjusted_mode
->crtc_hblank_start
- 1) |
6272 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
6273 I915_WRITE(HSYNC(cpu_transcoder
),
6274 (adjusted_mode
->crtc_hsync_start
- 1) |
6275 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
6277 I915_WRITE(VTOTAL(cpu_transcoder
),
6278 (adjusted_mode
->crtc_vdisplay
- 1) |
6279 ((crtc_vtotal
- 1) << 16));
6280 I915_WRITE(VBLANK(cpu_transcoder
),
6281 (adjusted_mode
->crtc_vblank_start
- 1) |
6282 ((crtc_vblank_end
- 1) << 16));
6283 I915_WRITE(VSYNC(cpu_transcoder
),
6284 (adjusted_mode
->crtc_vsync_start
- 1) |
6285 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
6287 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6288 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6289 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6291 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
6292 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
6293 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
6295 /* pipesrc controls the size that is scaled from, which should
6296 * always be the user's requested size.
6298 I915_WRITE(PIPESRC(pipe
),
6299 ((intel_crtc
->config
->pipe_src_w
- 1) << 16) |
6300 (intel_crtc
->config
->pipe_src_h
- 1));
6303 static void intel_get_pipe_timings(struct intel_crtc
*crtc
,
6304 struct intel_crtc_state
*pipe_config
)
6306 struct drm_device
*dev
= crtc
->base
.dev
;
6307 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6308 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
6311 tmp
= I915_READ(HTOTAL(cpu_transcoder
));
6312 pipe_config
->base
.adjusted_mode
.crtc_hdisplay
= (tmp
& 0xffff) + 1;
6313 pipe_config
->base
.adjusted_mode
.crtc_htotal
= ((tmp
>> 16) & 0xffff) + 1;
6314 tmp
= I915_READ(HBLANK(cpu_transcoder
));
6315 pipe_config
->base
.adjusted_mode
.crtc_hblank_start
= (tmp
& 0xffff) + 1;
6316 pipe_config
->base
.adjusted_mode
.crtc_hblank_end
= ((tmp
>> 16) & 0xffff) + 1;
6317 tmp
= I915_READ(HSYNC(cpu_transcoder
));
6318 pipe_config
->base
.adjusted_mode
.crtc_hsync_start
= (tmp
& 0xffff) + 1;
6319 pipe_config
->base
.adjusted_mode
.crtc_hsync_end
= ((tmp
>> 16) & 0xffff) + 1;
6321 tmp
= I915_READ(VTOTAL(cpu_transcoder
));
6322 pipe_config
->base
.adjusted_mode
.crtc_vdisplay
= (tmp
& 0xffff) + 1;
6323 pipe_config
->base
.adjusted_mode
.crtc_vtotal
= ((tmp
>> 16) & 0xffff) + 1;
6324 tmp
= I915_READ(VBLANK(cpu_transcoder
));
6325 pipe_config
->base
.adjusted_mode
.crtc_vblank_start
= (tmp
& 0xffff) + 1;
6326 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
= ((tmp
>> 16) & 0xffff) + 1;
6327 tmp
= I915_READ(VSYNC(cpu_transcoder
));
6328 pipe_config
->base
.adjusted_mode
.crtc_vsync_start
= (tmp
& 0xffff) + 1;
6329 pipe_config
->base
.adjusted_mode
.crtc_vsync_end
= ((tmp
>> 16) & 0xffff) + 1;
6331 if (I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_INTERLACE_MASK
) {
6332 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
6333 pipe_config
->base
.adjusted_mode
.crtc_vtotal
+= 1;
6334 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
+= 1;
6337 tmp
= I915_READ(PIPESRC(crtc
->pipe
));
6338 pipe_config
->pipe_src_h
= (tmp
& 0xffff) + 1;
6339 pipe_config
->pipe_src_w
= ((tmp
>> 16) & 0xffff) + 1;
6341 pipe_config
->base
.mode
.vdisplay
= pipe_config
->pipe_src_h
;
6342 pipe_config
->base
.mode
.hdisplay
= pipe_config
->pipe_src_w
;
6345 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
6346 struct intel_crtc_state
*pipe_config
)
6348 mode
->hdisplay
= pipe_config
->base
.adjusted_mode
.crtc_hdisplay
;
6349 mode
->htotal
= pipe_config
->base
.adjusted_mode
.crtc_htotal
;
6350 mode
->hsync_start
= pipe_config
->base
.adjusted_mode
.crtc_hsync_start
;
6351 mode
->hsync_end
= pipe_config
->base
.adjusted_mode
.crtc_hsync_end
;
6353 mode
->vdisplay
= pipe_config
->base
.adjusted_mode
.crtc_vdisplay
;
6354 mode
->vtotal
= pipe_config
->base
.adjusted_mode
.crtc_vtotal
;
6355 mode
->vsync_start
= pipe_config
->base
.adjusted_mode
.crtc_vsync_start
;
6356 mode
->vsync_end
= pipe_config
->base
.adjusted_mode
.crtc_vsync_end
;
6358 mode
->flags
= pipe_config
->base
.adjusted_mode
.flags
;
6360 mode
->clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
6361 mode
->flags
|= pipe_config
->base
.adjusted_mode
.flags
;
6364 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
)
6366 struct drm_device
*dev
= intel_crtc
->base
.dev
;
6367 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6372 if ((intel_crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
6373 (intel_crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
6374 pipeconf
|= I915_READ(PIPECONF(intel_crtc
->pipe
)) & PIPECONF_ENABLE
;
6376 if (intel_crtc
->config
->double_wide
)
6377 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
6379 /* only g4x and later have fancy bpc/dither controls */
6380 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
6381 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6382 if (intel_crtc
->config
->dither
&& intel_crtc
->config
->pipe_bpp
!= 30)
6383 pipeconf
|= PIPECONF_DITHER_EN
|
6384 PIPECONF_DITHER_TYPE_SP
;
6386 switch (intel_crtc
->config
->pipe_bpp
) {
6388 pipeconf
|= PIPECONF_6BPC
;
6391 pipeconf
|= PIPECONF_8BPC
;
6394 pipeconf
|= PIPECONF_10BPC
;
6397 /* Case prevented by intel_choose_pipe_bpp_dither. */
6402 if (HAS_PIPE_CXSR(dev
)) {
6403 if (intel_crtc
->lowfreq_avail
) {
6404 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6405 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
6407 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6411 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
6412 if (INTEL_INFO(dev
)->gen
< 4 ||
6413 intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
6414 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
6416 pipeconf
|= PIPECONF_INTERLACE_W_SYNC_SHIFT
;
6418 pipeconf
|= PIPECONF_PROGRESSIVE
;
6420 if (IS_VALLEYVIEW(dev
) && intel_crtc
->config
->limited_color_range
)
6421 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
6423 I915_WRITE(PIPECONF(intel_crtc
->pipe
), pipeconf
);
6424 POSTING_READ(PIPECONF(intel_crtc
->pipe
));
6427 static int i9xx_crtc_compute_clock(struct intel_crtc
*crtc
,
6428 struct intel_crtc_state
*crtc_state
)
6430 struct drm_device
*dev
= crtc
->base
.dev
;
6431 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6432 int refclk
, num_connectors
= 0;
6433 intel_clock_t clock
, reduced_clock
;
6434 bool ok
, has_reduced_clock
= false;
6435 bool is_lvds
= false, is_dsi
= false;
6436 struct intel_encoder
*encoder
;
6437 const intel_limit_t
*limit
;
6439 for_each_intel_encoder(dev
, encoder
) {
6440 if (encoder
->new_crtc
!= crtc
)
6443 switch (encoder
->type
) {
6444 case INTEL_OUTPUT_LVDS
:
6447 case INTEL_OUTPUT_DSI
:
6460 if (!crtc_state
->clock_set
) {
6461 refclk
= i9xx_get_refclk(crtc
, num_connectors
);
6464 * Returns a set of divisors for the desired target clock with
6465 * the given refclk, or FALSE. The returned values represent
6466 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6469 limit
= intel_limit(crtc
, refclk
);
6470 ok
= dev_priv
->display
.find_dpll(limit
, crtc
,
6471 crtc_state
->port_clock
,
6472 refclk
, NULL
, &clock
);
6474 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6478 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
6480 * Ensure we match the reduced clock's P to the target
6481 * clock. If the clocks don't match, we can't switch
6482 * the display clock by using the FP0/FP1. In such case
6483 * we will disable the LVDS downclock feature.
6486 dev_priv
->display
.find_dpll(limit
, crtc
,
6487 dev_priv
->lvds_downclock
,
6491 /* Compat-code for transition, will disappear. */
6492 crtc_state
->dpll
.n
= clock
.n
;
6493 crtc_state
->dpll
.m1
= clock
.m1
;
6494 crtc_state
->dpll
.m2
= clock
.m2
;
6495 crtc_state
->dpll
.p1
= clock
.p1
;
6496 crtc_state
->dpll
.p2
= clock
.p2
;
6500 i8xx_update_pll(crtc
, crtc_state
,
6501 has_reduced_clock
? &reduced_clock
: NULL
,
6503 } else if (IS_CHERRYVIEW(dev
)) {
6504 chv_update_pll(crtc
, crtc_state
);
6505 } else if (IS_VALLEYVIEW(dev
)) {
6506 vlv_update_pll(crtc
, crtc_state
);
6508 i9xx_update_pll(crtc
, crtc_state
,
6509 has_reduced_clock
? &reduced_clock
: NULL
,
6516 static void i9xx_get_pfit_config(struct intel_crtc
*crtc
,
6517 struct intel_crtc_state
*pipe_config
)
6519 struct drm_device
*dev
= crtc
->base
.dev
;
6520 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6523 if (INTEL_INFO(dev
)->gen
<= 3 && (IS_I830(dev
) || !IS_MOBILE(dev
)))
6526 tmp
= I915_READ(PFIT_CONTROL
);
6527 if (!(tmp
& PFIT_ENABLE
))
6530 /* Check whether the pfit is attached to our pipe. */
6531 if (INTEL_INFO(dev
)->gen
< 4) {
6532 if (crtc
->pipe
!= PIPE_B
)
6535 if ((tmp
& PFIT_PIPE_MASK
) != (crtc
->pipe
<< PFIT_PIPE_SHIFT
))
6539 pipe_config
->gmch_pfit
.control
= tmp
;
6540 pipe_config
->gmch_pfit
.pgm_ratios
= I915_READ(PFIT_PGM_RATIOS
);
6541 if (INTEL_INFO(dev
)->gen
< 5)
6542 pipe_config
->gmch_pfit
.lvds_border_bits
=
6543 I915_READ(LVDS
) & LVDS_BORDER_ENABLE
;
6546 static void vlv_crtc_clock_get(struct intel_crtc
*crtc
,
6547 struct intel_crtc_state
*pipe_config
)
6549 struct drm_device
*dev
= crtc
->base
.dev
;
6550 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6551 int pipe
= pipe_config
->cpu_transcoder
;
6552 intel_clock_t clock
;
6554 int refclk
= 100000;
6556 /* In case of MIPI DPLL will not even be used */
6557 if (!(pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
))
6560 mutex_lock(&dev_priv
->dpio_lock
);
6561 mdiv
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW3(pipe
));
6562 mutex_unlock(&dev_priv
->dpio_lock
);
6564 clock
.m1
= (mdiv
>> DPIO_M1DIV_SHIFT
) & 7;
6565 clock
.m2
= mdiv
& DPIO_M2DIV_MASK
;
6566 clock
.n
= (mdiv
>> DPIO_N_SHIFT
) & 0xf;
6567 clock
.p1
= (mdiv
>> DPIO_P1_SHIFT
) & 7;
6568 clock
.p2
= (mdiv
>> DPIO_P2_SHIFT
) & 0x1f;
6570 vlv_clock(refclk
, &clock
);
6572 /* clock.dot is the fast clock */
6573 pipe_config
->port_clock
= clock
.dot
/ 5;
6577 i9xx_get_initial_plane_config(struct intel_crtc
*crtc
,
6578 struct intel_initial_plane_config
*plane_config
)
6580 struct drm_device
*dev
= crtc
->base
.dev
;
6581 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6582 u32 val
, base
, offset
;
6583 int pipe
= crtc
->pipe
, plane
= crtc
->plane
;
6584 int fourcc
, pixel_format
;
6586 struct drm_framebuffer
*fb
;
6587 struct intel_framebuffer
*intel_fb
;
6589 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
6591 DRM_DEBUG_KMS("failed to alloc fb\n");
6595 fb
= &intel_fb
->base
;
6597 val
= I915_READ(DSPCNTR(plane
));
6599 if (INTEL_INFO(dev
)->gen
>= 4)
6600 if (val
& DISPPLANE_TILED
)
6601 plane_config
->tiling
= I915_TILING_X
;
6603 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
6604 fourcc
= i9xx_format_to_fourcc(pixel_format
);
6605 fb
->pixel_format
= fourcc
;
6606 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
6608 if (INTEL_INFO(dev
)->gen
>= 4) {
6609 if (plane_config
->tiling
)
6610 offset
= I915_READ(DSPTILEOFF(plane
));
6612 offset
= I915_READ(DSPLINOFF(plane
));
6613 base
= I915_READ(DSPSURF(plane
)) & 0xfffff000;
6615 base
= I915_READ(DSPADDR(plane
));
6617 plane_config
->base
= base
;
6619 val
= I915_READ(PIPESRC(pipe
));
6620 fb
->width
= ((val
>> 16) & 0xfff) + 1;
6621 fb
->height
= ((val
>> 0) & 0xfff) + 1;
6623 val
= I915_READ(DSPSTRIDE(pipe
));
6624 fb
->pitches
[0] = val
& 0xffffffc0;
6626 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
6627 plane_config
->tiling
);
6629 plane_config
->size
= PAGE_ALIGN(fb
->pitches
[0] * aligned_height
);
6631 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6632 pipe_name(pipe
), plane
, fb
->width
, fb
->height
,
6633 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
6634 plane_config
->size
);
6636 crtc
->base
.primary
->fb
= fb
;
6639 static void chv_crtc_clock_get(struct intel_crtc
*crtc
,
6640 struct intel_crtc_state
*pipe_config
)
6642 struct drm_device
*dev
= crtc
->base
.dev
;
6643 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6644 int pipe
= pipe_config
->cpu_transcoder
;
6645 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
6646 intel_clock_t clock
;
6647 u32 cmn_dw13
, pll_dw0
, pll_dw1
, pll_dw2
;
6648 int refclk
= 100000;
6650 mutex_lock(&dev_priv
->dpio_lock
);
6651 cmn_dw13
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW13(port
));
6652 pll_dw0
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW0(port
));
6653 pll_dw1
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW1(port
));
6654 pll_dw2
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW2(port
));
6655 mutex_unlock(&dev_priv
->dpio_lock
);
6657 clock
.m1
= (pll_dw1
& 0x7) == DPIO_CHV_M1_DIV_BY_2
? 2 : 0;
6658 clock
.m2
= ((pll_dw0
& 0xff) << 22) | (pll_dw2
& 0x3fffff);
6659 clock
.n
= (pll_dw1
>> DPIO_CHV_N_DIV_SHIFT
) & 0xf;
6660 clock
.p1
= (cmn_dw13
>> DPIO_CHV_P1_DIV_SHIFT
) & 0x7;
6661 clock
.p2
= (cmn_dw13
>> DPIO_CHV_P2_DIV_SHIFT
) & 0x1f;
6663 chv_clock(refclk
, &clock
);
6665 /* clock.dot is the fast clock */
6666 pipe_config
->port_clock
= clock
.dot
/ 5;
6669 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
6670 struct intel_crtc_state
*pipe_config
)
6672 struct drm_device
*dev
= crtc
->base
.dev
;
6673 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6676 if (!intel_display_power_is_enabled(dev_priv
,
6677 POWER_DOMAIN_PIPE(crtc
->pipe
)))
6680 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
6681 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
6683 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
6684 if (!(tmp
& PIPECONF_ENABLE
))
6687 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
6688 switch (tmp
& PIPECONF_BPC_MASK
) {
6690 pipe_config
->pipe_bpp
= 18;
6693 pipe_config
->pipe_bpp
= 24;
6695 case PIPECONF_10BPC
:
6696 pipe_config
->pipe_bpp
= 30;
6703 if (IS_VALLEYVIEW(dev
) && (tmp
& PIPECONF_COLOR_RANGE_SELECT
))
6704 pipe_config
->limited_color_range
= true;
6706 if (INTEL_INFO(dev
)->gen
< 4)
6707 pipe_config
->double_wide
= tmp
& PIPECONF_DOUBLE_WIDE
;
6709 intel_get_pipe_timings(crtc
, pipe_config
);
6711 i9xx_get_pfit_config(crtc
, pipe_config
);
6713 if (INTEL_INFO(dev
)->gen
>= 4) {
6714 tmp
= I915_READ(DPLL_MD(crtc
->pipe
));
6715 pipe_config
->pixel_multiplier
=
6716 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
6717 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
6718 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
6719 } else if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
6720 tmp
= I915_READ(DPLL(crtc
->pipe
));
6721 pipe_config
->pixel_multiplier
=
6722 ((tmp
& SDVO_MULTIPLIER_MASK
)
6723 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
6725 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6726 * port and will be fixed up in the encoder->get_config
6728 pipe_config
->pixel_multiplier
= 1;
6730 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(crtc
->pipe
));
6731 if (!IS_VALLEYVIEW(dev
)) {
6733 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6734 * on 830. Filter it out here so that we don't
6735 * report errors due to that.
6738 pipe_config
->dpll_hw_state
.dpll
&= ~DPLL_DVO_2X_MODE
;
6740 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(crtc
->pipe
));
6741 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(crtc
->pipe
));
6743 /* Mask out read-only status bits. */
6744 pipe_config
->dpll_hw_state
.dpll
&= ~(DPLL_LOCK_VLV
|
6745 DPLL_PORTC_READY_MASK
|
6746 DPLL_PORTB_READY_MASK
);
6749 if (IS_CHERRYVIEW(dev
))
6750 chv_crtc_clock_get(crtc
, pipe_config
);
6751 else if (IS_VALLEYVIEW(dev
))
6752 vlv_crtc_clock_get(crtc
, pipe_config
);
6754 i9xx_crtc_clock_get(crtc
, pipe_config
);
6759 static void ironlake_init_pch_refclk(struct drm_device
*dev
)
6761 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6762 struct intel_encoder
*encoder
;
6764 bool has_lvds
= false;
6765 bool has_cpu_edp
= false;
6766 bool has_panel
= false;
6767 bool has_ck505
= false;
6768 bool can_ssc
= false;
6770 /* We need to take the global config into account */
6771 for_each_intel_encoder(dev
, encoder
) {
6772 switch (encoder
->type
) {
6773 case INTEL_OUTPUT_LVDS
:
6777 case INTEL_OUTPUT_EDP
:
6779 if (enc_to_dig_port(&encoder
->base
)->port
== PORT_A
)
6787 if (HAS_PCH_IBX(dev
)) {
6788 has_ck505
= dev_priv
->vbt
.display_clock_mode
;
6789 can_ssc
= has_ck505
;
6795 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6796 has_panel
, has_lvds
, has_ck505
);
6798 /* Ironlake: try to setup display ref clock before DPLL
6799 * enabling. This is only under driver's control after
6800 * PCH B stepping, previous chipset stepping should be
6801 * ignoring this setting.
6803 val
= I915_READ(PCH_DREF_CONTROL
);
6805 /* As we must carefully and slowly disable/enable each source in turn,
6806 * compute the final state we want first and check if we need to
6807 * make any changes at all.
6810 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
6812 final
|= DREF_NONSPREAD_CK505_ENABLE
;
6814 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
6816 final
&= ~DREF_SSC_SOURCE_MASK
;
6817 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
6818 final
&= ~DREF_SSC1_ENABLE
;
6821 final
|= DREF_SSC_SOURCE_ENABLE
;
6823 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
6824 final
|= DREF_SSC1_ENABLE
;
6827 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
6828 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
6830 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
6832 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6834 final
|= DREF_SSC_SOURCE_DISABLE
;
6835 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6841 /* Always enable nonspread source */
6842 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
6845 val
|= DREF_NONSPREAD_CK505_ENABLE
;
6847 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
6850 val
&= ~DREF_SSC_SOURCE_MASK
;
6851 val
|= DREF_SSC_SOURCE_ENABLE
;
6853 /* SSC must be turned on before enabling the CPU output */
6854 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
6855 DRM_DEBUG_KMS("Using SSC on panel\n");
6856 val
|= DREF_SSC1_ENABLE
;
6858 val
&= ~DREF_SSC1_ENABLE
;
6860 /* Get SSC going before enabling the outputs */
6861 I915_WRITE(PCH_DREF_CONTROL
, val
);
6862 POSTING_READ(PCH_DREF_CONTROL
);
6865 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
6867 /* Enable CPU source on CPU attached eDP */
6869 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
6870 DRM_DEBUG_KMS("Using SSC on eDP\n");
6871 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
6873 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
6875 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6877 I915_WRITE(PCH_DREF_CONTROL
, val
);
6878 POSTING_READ(PCH_DREF_CONTROL
);
6881 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6883 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
6885 /* Turn off CPU output */
6886 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6888 I915_WRITE(PCH_DREF_CONTROL
, val
);
6889 POSTING_READ(PCH_DREF_CONTROL
);
6892 /* Turn off the SSC source */
6893 val
&= ~DREF_SSC_SOURCE_MASK
;
6894 val
|= DREF_SSC_SOURCE_DISABLE
;
6897 val
&= ~DREF_SSC1_ENABLE
;
6899 I915_WRITE(PCH_DREF_CONTROL
, val
);
6900 POSTING_READ(PCH_DREF_CONTROL
);
6904 BUG_ON(val
!= final
);
6907 static void lpt_reset_fdi_mphy(struct drm_i915_private
*dev_priv
)
6911 tmp
= I915_READ(SOUTH_CHICKEN2
);
6912 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
6913 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
6915 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2
) &
6916 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
6917 DRM_ERROR("FDI mPHY reset assert timeout\n");
6919 tmp
= I915_READ(SOUTH_CHICKEN2
);
6920 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
6921 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
6923 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2
) &
6924 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0, 100))
6925 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6928 /* WaMPhyProgramming:hsw */
6929 static void lpt_program_fdi_mphy(struct drm_i915_private
*dev_priv
)
6933 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
6934 tmp
&= ~(0xFF << 24);
6935 tmp
|= (0x12 << 24);
6936 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
6938 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
6940 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
6942 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
6944 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
6946 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
6947 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
6948 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
6950 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
6951 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
6952 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
6954 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
6957 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
6959 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
6962 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
6964 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
6967 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
6969 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
6972 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
6974 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
6975 tmp
&= ~(0xFF << 16);
6976 tmp
|= (0x1C << 16);
6977 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
6979 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
6980 tmp
&= ~(0xFF << 16);
6981 tmp
|= (0x1C << 16);
6982 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
6984 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
6986 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
6988 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
6990 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
6992 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
6993 tmp
&= ~(0xF << 28);
6995 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
6997 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
6998 tmp
&= ~(0xF << 28);
7000 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
7003 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7004 * Programming" based on the parameters passed:
7005 * - Sequence to enable CLKOUT_DP
7006 * - Sequence to enable CLKOUT_DP without spread
7007 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7009 static void lpt_enable_clkout_dp(struct drm_device
*dev
, bool with_spread
,
7012 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7015 if (WARN(with_fdi
&& !with_spread
, "FDI requires downspread\n"))
7017 if (WARN(dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
&&
7018 with_fdi
, "LP PCH doesn't have FDI\n"))
7021 mutex_lock(&dev_priv
->dpio_lock
);
7023 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
7024 tmp
&= ~SBI_SSCCTL_DISABLE
;
7025 tmp
|= SBI_SSCCTL_PATHALT
;
7026 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
7031 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
7032 tmp
&= ~SBI_SSCCTL_PATHALT
;
7033 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
7036 lpt_reset_fdi_mphy(dev_priv
);
7037 lpt_program_fdi_mphy(dev_priv
);
7041 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
7042 SBI_GEN0
: SBI_DBUFF0
;
7043 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
7044 tmp
|= SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
7045 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
7047 mutex_unlock(&dev_priv
->dpio_lock
);
7050 /* Sequence to disable CLKOUT_DP */
7051 static void lpt_disable_clkout_dp(struct drm_device
*dev
)
7053 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7056 mutex_lock(&dev_priv
->dpio_lock
);
7058 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
7059 SBI_GEN0
: SBI_DBUFF0
;
7060 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
7061 tmp
&= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
7062 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
7064 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
7065 if (!(tmp
& SBI_SSCCTL_DISABLE
)) {
7066 if (!(tmp
& SBI_SSCCTL_PATHALT
)) {
7067 tmp
|= SBI_SSCCTL_PATHALT
;
7068 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
7071 tmp
|= SBI_SSCCTL_DISABLE
;
7072 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
7075 mutex_unlock(&dev_priv
->dpio_lock
);
7078 static void lpt_init_pch_refclk(struct drm_device
*dev
)
7080 struct intel_encoder
*encoder
;
7081 bool has_vga
= false;
7083 for_each_intel_encoder(dev
, encoder
) {
7084 switch (encoder
->type
) {
7085 case INTEL_OUTPUT_ANALOG
:
7094 lpt_enable_clkout_dp(dev
, true, true);
7096 lpt_disable_clkout_dp(dev
);
7100 * Initialize reference clocks when the driver loads
7102 void intel_init_pch_refclk(struct drm_device
*dev
)
7104 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
7105 ironlake_init_pch_refclk(dev
);
7106 else if (HAS_PCH_LPT(dev
))
7107 lpt_init_pch_refclk(dev
);
7110 static int ironlake_get_refclk(struct drm_crtc
*crtc
)
7112 struct drm_device
*dev
= crtc
->dev
;
7113 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7114 struct intel_encoder
*encoder
;
7115 int num_connectors
= 0;
7116 bool is_lvds
= false;
7118 for_each_intel_encoder(dev
, encoder
) {
7119 if (encoder
->new_crtc
!= to_intel_crtc(crtc
))
7122 switch (encoder
->type
) {
7123 case INTEL_OUTPUT_LVDS
:
7132 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
7133 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7134 dev_priv
->vbt
.lvds_ssc_freq
);
7135 return dev_priv
->vbt
.lvds_ssc_freq
;
7141 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
)
7143 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
7144 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7145 int pipe
= intel_crtc
->pipe
;
7150 switch (intel_crtc
->config
->pipe_bpp
) {
7152 val
|= PIPECONF_6BPC
;
7155 val
|= PIPECONF_8BPC
;
7158 val
|= PIPECONF_10BPC
;
7161 val
|= PIPECONF_12BPC
;
7164 /* Case prevented by intel_choose_pipe_bpp_dither. */
7168 if (intel_crtc
->config
->dither
)
7169 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
7171 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
7172 val
|= PIPECONF_INTERLACED_ILK
;
7174 val
|= PIPECONF_PROGRESSIVE
;
7176 if (intel_crtc
->config
->limited_color_range
)
7177 val
|= PIPECONF_COLOR_RANGE_SELECT
;
7179 I915_WRITE(PIPECONF(pipe
), val
);
7180 POSTING_READ(PIPECONF(pipe
));
7184 * Set up the pipe CSC unit.
7186 * Currently only full range RGB to limited range RGB conversion
7187 * is supported, but eventually this should handle various
7188 * RGB<->YCbCr scenarios as well.
7190 static void intel_set_pipe_csc(struct drm_crtc
*crtc
)
7192 struct drm_device
*dev
= crtc
->dev
;
7193 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7194 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7195 int pipe
= intel_crtc
->pipe
;
7196 uint16_t coeff
= 0x7800; /* 1.0 */
7199 * TODO: Check what kind of values actually come out of the pipe
7200 * with these coeff/postoff values and adjust to get the best
7201 * accuracy. Perhaps we even need to take the bpc value into
7205 if (intel_crtc
->config
->limited_color_range
)
7206 coeff
= ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7209 * GY/GU and RY/RU should be the other way around according
7210 * to BSpec, but reality doesn't agree. Just set them up in
7211 * a way that results in the correct picture.
7213 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe
), coeff
<< 16);
7214 I915_WRITE(PIPE_CSC_COEFF_BY(pipe
), 0);
7216 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe
), coeff
);
7217 I915_WRITE(PIPE_CSC_COEFF_BU(pipe
), 0);
7219 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe
), 0);
7220 I915_WRITE(PIPE_CSC_COEFF_BV(pipe
), coeff
<< 16);
7222 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe
), 0);
7223 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe
), 0);
7224 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe
), 0);
7226 if (INTEL_INFO(dev
)->gen
> 6) {
7227 uint16_t postoff
= 0;
7229 if (intel_crtc
->config
->limited_color_range
)
7230 postoff
= (16 * (1 << 12) / 255) & 0x1fff;
7232 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe
), postoff
);
7233 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe
), postoff
);
7234 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe
), postoff
);
7236 I915_WRITE(PIPE_CSC_MODE(pipe
), 0);
7238 uint32_t mode
= CSC_MODE_YUV_TO_RGB
;
7240 if (intel_crtc
->config
->limited_color_range
)
7241 mode
|= CSC_BLACK_SCREEN_OFFSET
;
7243 I915_WRITE(PIPE_CSC_MODE(pipe
), mode
);
7247 static void haswell_set_pipeconf(struct drm_crtc
*crtc
)
7249 struct drm_device
*dev
= crtc
->dev
;
7250 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7251 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7252 enum pipe pipe
= intel_crtc
->pipe
;
7253 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
7258 if (IS_HASWELL(dev
) && intel_crtc
->config
->dither
)
7259 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
7261 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
7262 val
|= PIPECONF_INTERLACED_ILK
;
7264 val
|= PIPECONF_PROGRESSIVE
;
7266 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
7267 POSTING_READ(PIPECONF(cpu_transcoder
));
7269 I915_WRITE(GAMMA_MODE(intel_crtc
->pipe
), GAMMA_MODE_MODE_8BIT
);
7270 POSTING_READ(GAMMA_MODE(intel_crtc
->pipe
));
7272 if (IS_BROADWELL(dev
) || INTEL_INFO(dev
)->gen
>= 9) {
7275 switch (intel_crtc
->config
->pipe_bpp
) {
7277 val
|= PIPEMISC_DITHER_6_BPC
;
7280 val
|= PIPEMISC_DITHER_8_BPC
;
7283 val
|= PIPEMISC_DITHER_10_BPC
;
7286 val
|= PIPEMISC_DITHER_12_BPC
;
7289 /* Case prevented by pipe_config_set_bpp. */
7293 if (intel_crtc
->config
->dither
)
7294 val
|= PIPEMISC_DITHER_ENABLE
| PIPEMISC_DITHER_TYPE_SP
;
7296 I915_WRITE(PIPEMISC(pipe
), val
);
7300 static bool ironlake_compute_clocks(struct drm_crtc
*crtc
,
7301 struct intel_crtc_state
*crtc_state
,
7302 intel_clock_t
*clock
,
7303 bool *has_reduced_clock
,
7304 intel_clock_t
*reduced_clock
)
7306 struct drm_device
*dev
= crtc
->dev
;
7307 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7308 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7310 const intel_limit_t
*limit
;
7311 bool ret
, is_lvds
= false;
7313 is_lvds
= intel_pipe_will_have_type(intel_crtc
, INTEL_OUTPUT_LVDS
);
7315 refclk
= ironlake_get_refclk(crtc
);
7318 * Returns a set of divisors for the desired target clock with the given
7319 * refclk, or FALSE. The returned values represent the clock equation:
7320 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7322 limit
= intel_limit(intel_crtc
, refclk
);
7323 ret
= dev_priv
->display
.find_dpll(limit
, intel_crtc
,
7324 crtc_state
->port_clock
,
7325 refclk
, NULL
, clock
);
7329 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
7331 * Ensure we match the reduced clock's P to the target clock.
7332 * If the clocks don't match, we can't switch the display clock
7333 * by using the FP0/FP1. In such case we will disable the LVDS
7334 * downclock feature.
7336 *has_reduced_clock
=
7337 dev_priv
->display
.find_dpll(limit
, intel_crtc
,
7338 dev_priv
->lvds_downclock
,
7346 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
7349 * Account for spread spectrum to avoid
7350 * oversubscribing the link. Max center spread
7351 * is 2.5%; use 5% for safety's sake.
7353 u32 bps
= target_clock
* bpp
* 21 / 20;
7354 return DIV_ROUND_UP(bps
, link_bw
* 8);
7357 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
7359 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
7362 static uint32_t ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
7363 struct intel_crtc_state
*crtc_state
,
7365 intel_clock_t
*reduced_clock
, u32
*fp2
)
7367 struct drm_crtc
*crtc
= &intel_crtc
->base
;
7368 struct drm_device
*dev
= crtc
->dev
;
7369 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7370 struct intel_encoder
*intel_encoder
;
7372 int factor
, num_connectors
= 0;
7373 bool is_lvds
= false, is_sdvo
= false;
7375 for_each_intel_encoder(dev
, intel_encoder
) {
7376 if (intel_encoder
->new_crtc
!= to_intel_crtc(crtc
))
7379 switch (intel_encoder
->type
) {
7380 case INTEL_OUTPUT_LVDS
:
7383 case INTEL_OUTPUT_SDVO
:
7384 case INTEL_OUTPUT_HDMI
:
7394 /* Enable autotuning of the PLL clock (if permissible) */
7397 if ((intel_panel_use_ssc(dev_priv
) &&
7398 dev_priv
->vbt
.lvds_ssc_freq
== 100000) ||
7399 (HAS_PCH_IBX(dev
) && intel_is_dual_link_lvds(dev
)))
7401 } else if (crtc_state
->sdvo_tv_clock
)
7404 if (ironlake_needs_fb_cb_tune(&crtc_state
->dpll
, factor
))
7407 if (fp2
&& (reduced_clock
->m
< factor
* reduced_clock
->n
))
7413 dpll
|= DPLLB_MODE_LVDS
;
7415 dpll
|= DPLLB_MODE_DAC_SERIAL
;
7417 dpll
|= (crtc_state
->pixel_multiplier
- 1)
7418 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
7421 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7422 if (crtc_state
->has_dp_encoder
)
7423 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7425 /* compute bitmask from p1 value */
7426 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7428 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
7430 switch (crtc_state
->dpll
.p2
) {
7432 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
7435 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
7438 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
7441 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
7445 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
7446 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
7448 dpll
|= PLL_REF_INPUT_DREFCLK
;
7450 return dpll
| DPLL_VCO_ENABLE
;
7453 static int ironlake_crtc_compute_clock(struct intel_crtc
*crtc
,
7454 struct intel_crtc_state
*crtc_state
)
7456 struct drm_device
*dev
= crtc
->base
.dev
;
7457 intel_clock_t clock
, reduced_clock
;
7458 u32 dpll
= 0, fp
= 0, fp2
= 0;
7459 bool ok
, has_reduced_clock
= false;
7460 bool is_lvds
= false;
7461 struct intel_shared_dpll
*pll
;
7463 is_lvds
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
);
7465 WARN(!(HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)),
7466 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev
));
7468 ok
= ironlake_compute_clocks(&crtc
->base
, crtc_state
, &clock
,
7469 &has_reduced_clock
, &reduced_clock
);
7470 if (!ok
&& !crtc_state
->clock_set
) {
7471 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7474 /* Compat-code for transition, will disappear. */
7475 if (!crtc_state
->clock_set
) {
7476 crtc_state
->dpll
.n
= clock
.n
;
7477 crtc_state
->dpll
.m1
= clock
.m1
;
7478 crtc_state
->dpll
.m2
= clock
.m2
;
7479 crtc_state
->dpll
.p1
= clock
.p1
;
7480 crtc_state
->dpll
.p2
= clock
.p2
;
7483 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7484 if (crtc_state
->has_pch_encoder
) {
7485 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
7486 if (has_reduced_clock
)
7487 fp2
= i9xx_dpll_compute_fp(&reduced_clock
);
7489 dpll
= ironlake_compute_dpll(crtc
, crtc_state
,
7490 &fp
, &reduced_clock
,
7491 has_reduced_clock
? &fp2
: NULL
);
7493 crtc_state
->dpll_hw_state
.dpll
= dpll
;
7494 crtc_state
->dpll_hw_state
.fp0
= fp
;
7495 if (has_reduced_clock
)
7496 crtc_state
->dpll_hw_state
.fp1
= fp2
;
7498 crtc_state
->dpll_hw_state
.fp1
= fp
;
7500 pll
= intel_get_shared_dpll(crtc
, crtc_state
);
7502 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7503 pipe_name(crtc
->pipe
));
7508 if (is_lvds
&& has_reduced_clock
&& i915
.powersave
)
7509 crtc
->lowfreq_avail
= true;
7511 crtc
->lowfreq_avail
= false;
7516 static void intel_pch_transcoder_get_m_n(struct intel_crtc
*crtc
,
7517 struct intel_link_m_n
*m_n
)
7519 struct drm_device
*dev
= crtc
->base
.dev
;
7520 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7521 enum pipe pipe
= crtc
->pipe
;
7523 m_n
->link_m
= I915_READ(PCH_TRANS_LINK_M1(pipe
));
7524 m_n
->link_n
= I915_READ(PCH_TRANS_LINK_N1(pipe
));
7525 m_n
->gmch_m
= I915_READ(PCH_TRANS_DATA_M1(pipe
))
7527 m_n
->gmch_n
= I915_READ(PCH_TRANS_DATA_N1(pipe
));
7528 m_n
->tu
= ((I915_READ(PCH_TRANS_DATA_M1(pipe
))
7529 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7532 static void intel_cpu_transcoder_get_m_n(struct intel_crtc
*crtc
,
7533 enum transcoder transcoder
,
7534 struct intel_link_m_n
*m_n
,
7535 struct intel_link_m_n
*m2_n2
)
7537 struct drm_device
*dev
= crtc
->base
.dev
;
7538 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7539 enum pipe pipe
= crtc
->pipe
;
7541 if (INTEL_INFO(dev
)->gen
>= 5) {
7542 m_n
->link_m
= I915_READ(PIPE_LINK_M1(transcoder
));
7543 m_n
->link_n
= I915_READ(PIPE_LINK_N1(transcoder
));
7544 m_n
->gmch_m
= I915_READ(PIPE_DATA_M1(transcoder
))
7546 m_n
->gmch_n
= I915_READ(PIPE_DATA_N1(transcoder
));
7547 m_n
->tu
= ((I915_READ(PIPE_DATA_M1(transcoder
))
7548 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7549 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7550 * gen < 8) and if DRRS is supported (to make sure the
7551 * registers are not unnecessarily read).
7553 if (m2_n2
&& INTEL_INFO(dev
)->gen
< 8 &&
7554 crtc
->config
->has_drrs
) {
7555 m2_n2
->link_m
= I915_READ(PIPE_LINK_M2(transcoder
));
7556 m2_n2
->link_n
= I915_READ(PIPE_LINK_N2(transcoder
));
7557 m2_n2
->gmch_m
= I915_READ(PIPE_DATA_M2(transcoder
))
7559 m2_n2
->gmch_n
= I915_READ(PIPE_DATA_N2(transcoder
));
7560 m2_n2
->tu
= ((I915_READ(PIPE_DATA_M2(transcoder
))
7561 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7564 m_n
->link_m
= I915_READ(PIPE_LINK_M_G4X(pipe
));
7565 m_n
->link_n
= I915_READ(PIPE_LINK_N_G4X(pipe
));
7566 m_n
->gmch_m
= I915_READ(PIPE_DATA_M_G4X(pipe
))
7568 m_n
->gmch_n
= I915_READ(PIPE_DATA_N_G4X(pipe
));
7569 m_n
->tu
= ((I915_READ(PIPE_DATA_M_G4X(pipe
))
7570 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7574 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
7575 struct intel_crtc_state
*pipe_config
)
7577 if (pipe_config
->has_pch_encoder
)
7578 intel_pch_transcoder_get_m_n(crtc
, &pipe_config
->dp_m_n
);
7580 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
7581 &pipe_config
->dp_m_n
,
7582 &pipe_config
->dp_m2_n2
);
7585 static void ironlake_get_fdi_m_n_config(struct intel_crtc
*crtc
,
7586 struct intel_crtc_state
*pipe_config
)
7588 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
7589 &pipe_config
->fdi_m_n
, NULL
);
7592 static void skylake_get_pfit_config(struct intel_crtc
*crtc
,
7593 struct intel_crtc_state
*pipe_config
)
7595 struct drm_device
*dev
= crtc
->base
.dev
;
7596 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7599 tmp
= I915_READ(PS_CTL(crtc
->pipe
));
7601 if (tmp
& PS_ENABLE
) {
7602 pipe_config
->pch_pfit
.enabled
= true;
7603 pipe_config
->pch_pfit
.pos
= I915_READ(PS_WIN_POS(crtc
->pipe
));
7604 pipe_config
->pch_pfit
.size
= I915_READ(PS_WIN_SZ(crtc
->pipe
));
7609 skylake_get_initial_plane_config(struct intel_crtc
*crtc
,
7610 struct intel_initial_plane_config
*plane_config
)
7612 struct drm_device
*dev
= crtc
->base
.dev
;
7613 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7614 u32 val
, base
, offset
, stride_mult
;
7615 int pipe
= crtc
->pipe
;
7616 int fourcc
, pixel_format
;
7618 struct drm_framebuffer
*fb
;
7619 struct intel_framebuffer
*intel_fb
;
7621 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
7623 DRM_DEBUG_KMS("failed to alloc fb\n");
7627 fb
= &intel_fb
->base
;
7629 val
= I915_READ(PLANE_CTL(pipe
, 0));
7630 if (val
& PLANE_CTL_TILED_MASK
)
7631 plane_config
->tiling
= I915_TILING_X
;
7633 pixel_format
= val
& PLANE_CTL_FORMAT_MASK
;
7634 fourcc
= skl_format_to_fourcc(pixel_format
,
7635 val
& PLANE_CTL_ORDER_RGBX
,
7636 val
& PLANE_CTL_ALPHA_MASK
);
7637 fb
->pixel_format
= fourcc
;
7638 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
7640 base
= I915_READ(PLANE_SURF(pipe
, 0)) & 0xfffff000;
7641 plane_config
->base
= base
;
7643 offset
= I915_READ(PLANE_OFFSET(pipe
, 0));
7645 val
= I915_READ(PLANE_SIZE(pipe
, 0));
7646 fb
->height
= ((val
>> 16) & 0xfff) + 1;
7647 fb
->width
= ((val
>> 0) & 0x1fff) + 1;
7649 val
= I915_READ(PLANE_STRIDE(pipe
, 0));
7650 switch (plane_config
->tiling
) {
7651 case I915_TILING_NONE
:
7658 MISSING_CASE(plane_config
->tiling
);
7661 fb
->pitches
[0] = (val
& 0x3ff) * stride_mult
;
7663 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
7664 plane_config
->tiling
);
7666 plane_config
->size
= ALIGN(fb
->pitches
[0] * aligned_height
, PAGE_SIZE
);
7668 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7669 pipe_name(pipe
), fb
->width
, fb
->height
,
7670 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
7671 plane_config
->size
);
7673 crtc
->base
.primary
->fb
= fb
;
7680 static void ironlake_get_pfit_config(struct intel_crtc
*crtc
,
7681 struct intel_crtc_state
*pipe_config
)
7683 struct drm_device
*dev
= crtc
->base
.dev
;
7684 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7687 tmp
= I915_READ(PF_CTL(crtc
->pipe
));
7689 if (tmp
& PF_ENABLE
) {
7690 pipe_config
->pch_pfit
.enabled
= true;
7691 pipe_config
->pch_pfit
.pos
= I915_READ(PF_WIN_POS(crtc
->pipe
));
7692 pipe_config
->pch_pfit
.size
= I915_READ(PF_WIN_SZ(crtc
->pipe
));
7694 /* We currently do not free assignements of panel fitters on
7695 * ivb/hsw (since we don't use the higher upscaling modes which
7696 * differentiates them) so just WARN about this case for now. */
7698 WARN_ON((tmp
& PF_PIPE_SEL_MASK_IVB
) !=
7699 PF_PIPE_SEL_IVB(crtc
->pipe
));
7705 ironlake_get_initial_plane_config(struct intel_crtc
*crtc
,
7706 struct intel_initial_plane_config
*plane_config
)
7708 struct drm_device
*dev
= crtc
->base
.dev
;
7709 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7710 u32 val
, base
, offset
;
7711 int pipe
= crtc
->pipe
;
7712 int fourcc
, pixel_format
;
7714 struct drm_framebuffer
*fb
;
7715 struct intel_framebuffer
*intel_fb
;
7717 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
7719 DRM_DEBUG_KMS("failed to alloc fb\n");
7723 fb
= &intel_fb
->base
;
7725 val
= I915_READ(DSPCNTR(pipe
));
7727 if (INTEL_INFO(dev
)->gen
>= 4)
7728 if (val
& DISPPLANE_TILED
)
7729 plane_config
->tiling
= I915_TILING_X
;
7731 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
7732 fourcc
= i9xx_format_to_fourcc(pixel_format
);
7733 fb
->pixel_format
= fourcc
;
7734 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
7736 base
= I915_READ(DSPSURF(pipe
)) & 0xfffff000;
7737 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
7738 offset
= I915_READ(DSPOFFSET(pipe
));
7740 if (plane_config
->tiling
)
7741 offset
= I915_READ(DSPTILEOFF(pipe
));
7743 offset
= I915_READ(DSPLINOFF(pipe
));
7745 plane_config
->base
= base
;
7747 val
= I915_READ(PIPESRC(pipe
));
7748 fb
->width
= ((val
>> 16) & 0xfff) + 1;
7749 fb
->height
= ((val
>> 0) & 0xfff) + 1;
7751 val
= I915_READ(DSPSTRIDE(pipe
));
7752 fb
->pitches
[0] = val
& 0xffffffc0;
7754 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
7755 plane_config
->tiling
);
7757 plane_config
->size
= PAGE_ALIGN(fb
->pitches
[0] * aligned_height
);
7759 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7760 pipe_name(pipe
), fb
->width
, fb
->height
,
7761 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
7762 plane_config
->size
);
7764 crtc
->base
.primary
->fb
= fb
;
7767 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
7768 struct intel_crtc_state
*pipe_config
)
7770 struct drm_device
*dev
= crtc
->base
.dev
;
7771 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7774 if (!intel_display_power_is_enabled(dev_priv
,
7775 POWER_DOMAIN_PIPE(crtc
->pipe
)))
7778 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
7779 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
7781 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
7782 if (!(tmp
& PIPECONF_ENABLE
))
7785 switch (tmp
& PIPECONF_BPC_MASK
) {
7787 pipe_config
->pipe_bpp
= 18;
7790 pipe_config
->pipe_bpp
= 24;
7792 case PIPECONF_10BPC
:
7793 pipe_config
->pipe_bpp
= 30;
7795 case PIPECONF_12BPC
:
7796 pipe_config
->pipe_bpp
= 36;
7802 if (tmp
& PIPECONF_COLOR_RANGE_SELECT
)
7803 pipe_config
->limited_color_range
= true;
7805 if (I915_READ(PCH_TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
) {
7806 struct intel_shared_dpll
*pll
;
7808 pipe_config
->has_pch_encoder
= true;
7810 tmp
= I915_READ(FDI_RX_CTL(crtc
->pipe
));
7811 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
7812 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
7814 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
7816 if (HAS_PCH_IBX(dev_priv
->dev
)) {
7817 pipe_config
->shared_dpll
=
7818 (enum intel_dpll_id
) crtc
->pipe
;
7820 tmp
= I915_READ(PCH_DPLL_SEL
);
7821 if (tmp
& TRANS_DPLLB_SEL(crtc
->pipe
))
7822 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_B
;
7824 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_A
;
7827 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
7829 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
7830 &pipe_config
->dpll_hw_state
));
7832 tmp
= pipe_config
->dpll_hw_state
.dpll
;
7833 pipe_config
->pixel_multiplier
=
7834 ((tmp
& PLL_REF_SDVO_HDMI_MULTIPLIER_MASK
)
7835 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
) + 1;
7837 ironlake_pch_clock_get(crtc
, pipe_config
);
7839 pipe_config
->pixel_multiplier
= 1;
7842 intel_get_pipe_timings(crtc
, pipe_config
);
7844 ironlake_get_pfit_config(crtc
, pipe_config
);
7849 static void assert_can_disable_lcpll(struct drm_i915_private
*dev_priv
)
7851 struct drm_device
*dev
= dev_priv
->dev
;
7852 struct intel_crtc
*crtc
;
7854 for_each_intel_crtc(dev
, crtc
)
7855 I915_STATE_WARN(crtc
->active
, "CRTC for pipe %c enabled\n",
7856 pipe_name(crtc
->pipe
));
7858 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER
), "Power well on\n");
7859 I915_STATE_WARN(I915_READ(SPLL_CTL
) & SPLL_PLL_ENABLE
, "SPLL enabled\n");
7860 I915_STATE_WARN(I915_READ(WRPLL_CTL1
) & WRPLL_PLL_ENABLE
, "WRPLL1 enabled\n");
7861 I915_STATE_WARN(I915_READ(WRPLL_CTL2
) & WRPLL_PLL_ENABLE
, "WRPLL2 enabled\n");
7862 I915_STATE_WARN(I915_READ(PCH_PP_STATUS
) & PP_ON
, "Panel power on\n");
7863 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2
) & BLM_PWM_ENABLE
,
7864 "CPU PWM1 enabled\n");
7865 if (IS_HASWELL(dev
))
7866 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL
) & BLM_PWM_ENABLE
,
7867 "CPU PWM2 enabled\n");
7868 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1
) & BLM_PCH_PWM_ENABLE
,
7869 "PCH PWM1 enabled\n");
7870 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL
) & UTIL_PIN_ENABLE
,
7871 "Utility pin enabled\n");
7872 I915_STATE_WARN(I915_READ(PCH_GTC_CTL
) & PCH_GTC_ENABLE
, "PCH GTC enabled\n");
7875 * In theory we can still leave IRQs enabled, as long as only the HPD
7876 * interrupts remain enabled. We used to check for that, but since it's
7877 * gen-specific and since we only disable LCPLL after we fully disable
7878 * the interrupts, the check below should be enough.
7880 I915_STATE_WARN(intel_irqs_enabled(dev_priv
), "IRQs enabled\n");
7883 static uint32_t hsw_read_dcomp(struct drm_i915_private
*dev_priv
)
7885 struct drm_device
*dev
= dev_priv
->dev
;
7887 if (IS_HASWELL(dev
))
7888 return I915_READ(D_COMP_HSW
);
7890 return I915_READ(D_COMP_BDW
);
7893 static void hsw_write_dcomp(struct drm_i915_private
*dev_priv
, uint32_t val
)
7895 struct drm_device
*dev
= dev_priv
->dev
;
7897 if (IS_HASWELL(dev
)) {
7898 mutex_lock(&dev_priv
->rps
.hw_lock
);
7899 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
,
7901 DRM_ERROR("Failed to write to D_COMP\n");
7902 mutex_unlock(&dev_priv
->rps
.hw_lock
);
7904 I915_WRITE(D_COMP_BDW
, val
);
7905 POSTING_READ(D_COMP_BDW
);
7910 * This function implements pieces of two sequences from BSpec:
7911 * - Sequence for display software to disable LCPLL
7912 * - Sequence for display software to allow package C8+
7913 * The steps implemented here are just the steps that actually touch the LCPLL
7914 * register. Callers should take care of disabling all the display engine
7915 * functions, doing the mode unset, fixing interrupts, etc.
7917 static void hsw_disable_lcpll(struct drm_i915_private
*dev_priv
,
7918 bool switch_to_fclk
, bool allow_power_down
)
7922 assert_can_disable_lcpll(dev_priv
);
7924 val
= I915_READ(LCPLL_CTL
);
7926 if (switch_to_fclk
) {
7927 val
|= LCPLL_CD_SOURCE_FCLK
;
7928 I915_WRITE(LCPLL_CTL
, val
);
7930 if (wait_for_atomic_us(I915_READ(LCPLL_CTL
) &
7931 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
7932 DRM_ERROR("Switching to FCLK failed\n");
7934 val
= I915_READ(LCPLL_CTL
);
7937 val
|= LCPLL_PLL_DISABLE
;
7938 I915_WRITE(LCPLL_CTL
, val
);
7939 POSTING_READ(LCPLL_CTL
);
7941 if (wait_for((I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
) == 0, 1))
7942 DRM_ERROR("LCPLL still locked\n");
7944 val
= hsw_read_dcomp(dev_priv
);
7945 val
|= D_COMP_COMP_DISABLE
;
7946 hsw_write_dcomp(dev_priv
, val
);
7949 if (wait_for((hsw_read_dcomp(dev_priv
) & D_COMP_RCOMP_IN_PROGRESS
) == 0,
7951 DRM_ERROR("D_COMP RCOMP still in progress\n");
7953 if (allow_power_down
) {
7954 val
= I915_READ(LCPLL_CTL
);
7955 val
|= LCPLL_POWER_DOWN_ALLOW
;
7956 I915_WRITE(LCPLL_CTL
, val
);
7957 POSTING_READ(LCPLL_CTL
);
7962 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7965 static void hsw_restore_lcpll(struct drm_i915_private
*dev_priv
)
7969 val
= I915_READ(LCPLL_CTL
);
7971 if ((val
& (LCPLL_PLL_LOCK
| LCPLL_PLL_DISABLE
| LCPLL_CD_SOURCE_FCLK
|
7972 LCPLL_POWER_DOWN_ALLOW
)) == LCPLL_PLL_LOCK
)
7976 * Make sure we're not on PC8 state before disabling PC8, otherwise
7977 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7979 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
7981 if (val
& LCPLL_POWER_DOWN_ALLOW
) {
7982 val
&= ~LCPLL_POWER_DOWN_ALLOW
;
7983 I915_WRITE(LCPLL_CTL
, val
);
7984 POSTING_READ(LCPLL_CTL
);
7987 val
= hsw_read_dcomp(dev_priv
);
7988 val
|= D_COMP_COMP_FORCE
;
7989 val
&= ~D_COMP_COMP_DISABLE
;
7990 hsw_write_dcomp(dev_priv
, val
);
7992 val
= I915_READ(LCPLL_CTL
);
7993 val
&= ~LCPLL_PLL_DISABLE
;
7994 I915_WRITE(LCPLL_CTL
, val
);
7996 if (wait_for(I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
, 5))
7997 DRM_ERROR("LCPLL not locked yet\n");
7999 if (val
& LCPLL_CD_SOURCE_FCLK
) {
8000 val
= I915_READ(LCPLL_CTL
);
8001 val
&= ~LCPLL_CD_SOURCE_FCLK
;
8002 I915_WRITE(LCPLL_CTL
, val
);
8004 if (wait_for_atomic_us((I915_READ(LCPLL_CTL
) &
8005 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
8006 DRM_ERROR("Switching back to LCPLL failed\n");
8009 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
8013 * Package states C8 and deeper are really deep PC states that can only be
8014 * reached when all the devices on the system allow it, so even if the graphics
8015 * device allows PC8+, it doesn't mean the system will actually get to these
8016 * states. Our driver only allows PC8+ when going into runtime PM.
8018 * The requirements for PC8+ are that all the outputs are disabled, the power
8019 * well is disabled and most interrupts are disabled, and these are also
8020 * requirements for runtime PM. When these conditions are met, we manually do
8021 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8022 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8025 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8026 * the state of some registers, so when we come back from PC8+ we need to
8027 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8028 * need to take care of the registers kept by RC6. Notice that this happens even
8029 * if we don't put the device in PCI D3 state (which is what currently happens
8030 * because of the runtime PM support).
8032 * For more, read "Display Sequences for Package C8" on the hardware
8035 void hsw_enable_pc8(struct drm_i915_private
*dev_priv
)
8037 struct drm_device
*dev
= dev_priv
->dev
;
8040 DRM_DEBUG_KMS("Enabling package C8+\n");
8042 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
8043 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
8044 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
8045 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
8048 lpt_disable_clkout_dp(dev
);
8049 hsw_disable_lcpll(dev_priv
, true, true);
8052 void hsw_disable_pc8(struct drm_i915_private
*dev_priv
)
8054 struct drm_device
*dev
= dev_priv
->dev
;
8057 DRM_DEBUG_KMS("Disabling package C8+\n");
8059 hsw_restore_lcpll(dev_priv
);
8060 lpt_init_pch_refclk(dev
);
8062 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
8063 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
8064 val
|= PCH_LP_PARTITION_LEVEL_DISABLE
;
8065 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
8068 intel_prepare_ddi(dev
);
8071 static int haswell_crtc_compute_clock(struct intel_crtc
*crtc
,
8072 struct intel_crtc_state
*crtc_state
)
8074 if (!intel_ddi_pll_select(crtc
, crtc_state
))
8077 crtc
->lowfreq_avail
= false;
8082 static void skylake_get_ddi_pll(struct drm_i915_private
*dev_priv
,
8084 struct intel_crtc_state
*pipe_config
)
8086 u32 temp
, dpll_ctl1
;
8088 temp
= I915_READ(DPLL_CTRL2
) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port
);
8089 pipe_config
->ddi_pll_sel
= temp
>> (port
* 3 + 1);
8091 switch (pipe_config
->ddi_pll_sel
) {
8094 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
8095 * of the shared DPLL framework and thus needs to be read out
8098 dpll_ctl1
= I915_READ(DPLL_CTRL1
);
8099 pipe_config
->dpll_hw_state
.ctrl1
= dpll_ctl1
& 0x3f;
8102 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL1
;
8105 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL2
;
8108 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL3
;
8113 static void haswell_get_ddi_pll(struct drm_i915_private
*dev_priv
,
8115 struct intel_crtc_state
*pipe_config
)
8117 pipe_config
->ddi_pll_sel
= I915_READ(PORT_CLK_SEL(port
));
8119 switch (pipe_config
->ddi_pll_sel
) {
8120 case PORT_CLK_SEL_WRPLL1
:
8121 pipe_config
->shared_dpll
= DPLL_ID_WRPLL1
;
8123 case PORT_CLK_SEL_WRPLL2
:
8124 pipe_config
->shared_dpll
= DPLL_ID_WRPLL2
;
8129 static void haswell_get_ddi_port_state(struct intel_crtc
*crtc
,
8130 struct intel_crtc_state
*pipe_config
)
8132 struct drm_device
*dev
= crtc
->base
.dev
;
8133 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8134 struct intel_shared_dpll
*pll
;
8138 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
8140 port
= (tmp
& TRANS_DDI_PORT_MASK
) >> TRANS_DDI_PORT_SHIFT
;
8142 if (IS_SKYLAKE(dev
))
8143 skylake_get_ddi_pll(dev_priv
, port
, pipe_config
);
8145 haswell_get_ddi_pll(dev_priv
, port
, pipe_config
);
8147 if (pipe_config
->shared_dpll
>= 0) {
8148 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
8150 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
8151 &pipe_config
->dpll_hw_state
));
8155 * Haswell has only FDI/PCH transcoder A. It is which is connected to
8156 * DDI E. So just check whether this pipe is wired to DDI E and whether
8157 * the PCH transcoder is on.
8159 if (INTEL_INFO(dev
)->gen
< 9 &&
8160 (port
== PORT_E
) && I915_READ(LPT_TRANSCONF
) & TRANS_ENABLE
) {
8161 pipe_config
->has_pch_encoder
= true;
8163 tmp
= I915_READ(FDI_RX_CTL(PIPE_A
));
8164 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
8165 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
8167 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
8171 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
8172 struct intel_crtc_state
*pipe_config
)
8174 struct drm_device
*dev
= crtc
->base
.dev
;
8175 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8176 enum intel_display_power_domain pfit_domain
;
8179 if (!intel_display_power_is_enabled(dev_priv
,
8180 POWER_DOMAIN_PIPE(crtc
->pipe
)))
8183 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
8184 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
8186 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
8187 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
8188 enum pipe trans_edp_pipe
;
8189 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
8191 WARN(1, "unknown pipe linked to edp transcoder\n");
8192 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
8193 case TRANS_DDI_EDP_INPUT_A_ON
:
8194 trans_edp_pipe
= PIPE_A
;
8196 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
8197 trans_edp_pipe
= PIPE_B
;
8199 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
8200 trans_edp_pipe
= PIPE_C
;
8204 if (trans_edp_pipe
== crtc
->pipe
)
8205 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
8208 if (!intel_display_power_is_enabled(dev_priv
,
8209 POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
)))
8212 tmp
= I915_READ(PIPECONF(pipe_config
->cpu_transcoder
));
8213 if (!(tmp
& PIPECONF_ENABLE
))
8216 haswell_get_ddi_port_state(crtc
, pipe_config
);
8218 intel_get_pipe_timings(crtc
, pipe_config
);
8220 pfit_domain
= POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
);
8221 if (intel_display_power_is_enabled(dev_priv
, pfit_domain
)) {
8222 if (IS_SKYLAKE(dev
))
8223 skylake_get_pfit_config(crtc
, pipe_config
);
8225 ironlake_get_pfit_config(crtc
, pipe_config
);
8228 if (IS_HASWELL(dev
))
8229 pipe_config
->ips_enabled
= hsw_crtc_supports_ips(crtc
) &&
8230 (I915_READ(IPS_CTL
) & IPS_ENABLE
);
8232 if (pipe_config
->cpu_transcoder
!= TRANSCODER_EDP
) {
8233 pipe_config
->pixel_multiplier
=
8234 I915_READ(PIPE_MULT(pipe_config
->cpu_transcoder
)) + 1;
8236 pipe_config
->pixel_multiplier
= 1;
8242 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
8244 struct drm_device
*dev
= crtc
->dev
;
8245 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8246 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8247 uint32_t cntl
= 0, size
= 0;
8250 unsigned int width
= intel_crtc
->cursor_width
;
8251 unsigned int height
= intel_crtc
->cursor_height
;
8252 unsigned int stride
= roundup_pow_of_two(width
) * 4;
8256 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8267 cntl
|= CURSOR_ENABLE
|
8268 CURSOR_GAMMA_ENABLE
|
8269 CURSOR_FORMAT_ARGB
|
8270 CURSOR_STRIDE(stride
);
8272 size
= (height
<< 12) | width
;
8275 if (intel_crtc
->cursor_cntl
!= 0 &&
8276 (intel_crtc
->cursor_base
!= base
||
8277 intel_crtc
->cursor_size
!= size
||
8278 intel_crtc
->cursor_cntl
!= cntl
)) {
8279 /* On these chipsets we can only modify the base/size/stride
8280 * whilst the cursor is disabled.
8282 I915_WRITE(_CURACNTR
, 0);
8283 POSTING_READ(_CURACNTR
);
8284 intel_crtc
->cursor_cntl
= 0;
8287 if (intel_crtc
->cursor_base
!= base
) {
8288 I915_WRITE(_CURABASE
, base
);
8289 intel_crtc
->cursor_base
= base
;
8292 if (intel_crtc
->cursor_size
!= size
) {
8293 I915_WRITE(CURSIZE
, size
);
8294 intel_crtc
->cursor_size
= size
;
8297 if (intel_crtc
->cursor_cntl
!= cntl
) {
8298 I915_WRITE(_CURACNTR
, cntl
);
8299 POSTING_READ(_CURACNTR
);
8300 intel_crtc
->cursor_cntl
= cntl
;
8304 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
8306 struct drm_device
*dev
= crtc
->dev
;
8307 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8308 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8309 int pipe
= intel_crtc
->pipe
;
8314 cntl
= MCURSOR_GAMMA_ENABLE
;
8315 switch (intel_crtc
->cursor_width
) {
8317 cntl
|= CURSOR_MODE_64_ARGB_AX
;
8320 cntl
|= CURSOR_MODE_128_ARGB_AX
;
8323 cntl
|= CURSOR_MODE_256_ARGB_AX
;
8326 MISSING_CASE(intel_crtc
->cursor_width
);
8329 cntl
|= pipe
<< 28; /* Connect to correct pipe */
8331 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
8332 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
8335 if (crtc
->cursor
->state
->rotation
== BIT(DRM_ROTATE_180
))
8336 cntl
|= CURSOR_ROTATE_180
;
8338 if (intel_crtc
->cursor_cntl
!= cntl
) {
8339 I915_WRITE(CURCNTR(pipe
), cntl
);
8340 POSTING_READ(CURCNTR(pipe
));
8341 intel_crtc
->cursor_cntl
= cntl
;
8344 /* and commit changes on next vblank */
8345 I915_WRITE(CURBASE(pipe
), base
);
8346 POSTING_READ(CURBASE(pipe
));
8348 intel_crtc
->cursor_base
= base
;
8351 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8352 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
8355 struct drm_device
*dev
= crtc
->dev
;
8356 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8357 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8358 int pipe
= intel_crtc
->pipe
;
8359 int x
= crtc
->cursor_x
;
8360 int y
= crtc
->cursor_y
;
8361 u32 base
= 0, pos
= 0;
8364 base
= intel_crtc
->cursor_addr
;
8366 if (x
>= intel_crtc
->config
->pipe_src_w
)
8369 if (y
>= intel_crtc
->config
->pipe_src_h
)
8373 if (x
+ intel_crtc
->cursor_width
<= 0)
8376 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
8379 pos
|= x
<< CURSOR_X_SHIFT
;
8382 if (y
+ intel_crtc
->cursor_height
<= 0)
8385 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
8388 pos
|= y
<< CURSOR_Y_SHIFT
;
8390 if (base
== 0 && intel_crtc
->cursor_base
== 0)
8393 I915_WRITE(CURPOS(pipe
), pos
);
8395 /* ILK+ do this automagically */
8396 if (HAS_GMCH_DISPLAY(dev
) &&
8397 crtc
->cursor
->state
->rotation
== BIT(DRM_ROTATE_180
)) {
8398 base
+= (intel_crtc
->cursor_height
*
8399 intel_crtc
->cursor_width
- 1) * 4;
8402 if (IS_845G(dev
) || IS_I865G(dev
))
8403 i845_update_cursor(crtc
, base
);
8405 i9xx_update_cursor(crtc
, base
);
8408 static bool cursor_size_ok(struct drm_device
*dev
,
8409 uint32_t width
, uint32_t height
)
8411 if (width
== 0 || height
== 0)
8415 * 845g/865g are special in that they are only limited by
8416 * the width of their cursors, the height is arbitrary up to
8417 * the precision of the register. Everything else requires
8418 * square cursors, limited to a few power-of-two sizes.
8420 if (IS_845G(dev
) || IS_I865G(dev
)) {
8421 if ((width
& 63) != 0)
8424 if (width
> (IS_845G(dev
) ? 64 : 512))
8430 switch (width
| height
) {
8445 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
8446 u16
*blue
, uint32_t start
, uint32_t size
)
8448 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
8449 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8451 for (i
= start
; i
< end
; i
++) {
8452 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
8453 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
8454 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
8457 intel_crtc_load_lut(crtc
);
8460 /* VESA 640x480x72Hz mode to set on the pipe */
8461 static struct drm_display_mode load_detect_mode
= {
8462 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
8463 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
8466 struct drm_framebuffer
*
8467 __intel_framebuffer_create(struct drm_device
*dev
,
8468 struct drm_mode_fb_cmd2
*mode_cmd
,
8469 struct drm_i915_gem_object
*obj
)
8471 struct intel_framebuffer
*intel_fb
;
8474 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
8476 drm_gem_object_unreference(&obj
->base
);
8477 return ERR_PTR(-ENOMEM
);
8480 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
8484 return &intel_fb
->base
;
8486 drm_gem_object_unreference(&obj
->base
);
8489 return ERR_PTR(ret
);
8492 static struct drm_framebuffer
*
8493 intel_framebuffer_create(struct drm_device
*dev
,
8494 struct drm_mode_fb_cmd2
*mode_cmd
,
8495 struct drm_i915_gem_object
*obj
)
8497 struct drm_framebuffer
*fb
;
8500 ret
= i915_mutex_lock_interruptible(dev
);
8502 return ERR_PTR(ret
);
8503 fb
= __intel_framebuffer_create(dev
, mode_cmd
, obj
);
8504 mutex_unlock(&dev
->struct_mutex
);
8510 intel_framebuffer_pitch_for_width(int width
, int bpp
)
8512 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
8513 return ALIGN(pitch
, 64);
8517 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
8519 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
8520 return PAGE_ALIGN(pitch
* mode
->vdisplay
);
8523 static struct drm_framebuffer
*
8524 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
8525 struct drm_display_mode
*mode
,
8528 struct drm_i915_gem_object
*obj
;
8529 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
8531 obj
= i915_gem_alloc_object(dev
,
8532 intel_framebuffer_size_for_mode(mode
, bpp
));
8534 return ERR_PTR(-ENOMEM
);
8536 mode_cmd
.width
= mode
->hdisplay
;
8537 mode_cmd
.height
= mode
->vdisplay
;
8538 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
8540 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
8542 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
8545 static struct drm_framebuffer
*
8546 mode_fits_in_fbdev(struct drm_device
*dev
,
8547 struct drm_display_mode
*mode
)
8549 #ifdef CONFIG_DRM_I915_FBDEV
8550 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8551 struct drm_i915_gem_object
*obj
;
8552 struct drm_framebuffer
*fb
;
8554 if (!dev_priv
->fbdev
)
8557 if (!dev_priv
->fbdev
->fb
)
8560 obj
= dev_priv
->fbdev
->fb
->obj
;
8563 fb
= &dev_priv
->fbdev
->fb
->base
;
8564 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
8565 fb
->bits_per_pixel
))
8568 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
8577 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
8578 struct drm_display_mode
*mode
,
8579 struct intel_load_detect_pipe
*old
,
8580 struct drm_modeset_acquire_ctx
*ctx
)
8582 struct intel_crtc
*intel_crtc
;
8583 struct intel_encoder
*intel_encoder
=
8584 intel_attached_encoder(connector
);
8585 struct drm_crtc
*possible_crtc
;
8586 struct drm_encoder
*encoder
= &intel_encoder
->base
;
8587 struct drm_crtc
*crtc
= NULL
;
8588 struct drm_device
*dev
= encoder
->dev
;
8589 struct drm_framebuffer
*fb
;
8590 struct drm_mode_config
*config
= &dev
->mode_config
;
8593 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8594 connector
->base
.id
, connector
->name
,
8595 encoder
->base
.id
, encoder
->name
);
8598 ret
= drm_modeset_lock(&config
->connection_mutex
, ctx
);
8603 * Algorithm gets a little messy:
8605 * - if the connector already has an assigned crtc, use it (but make
8606 * sure it's on first)
8608 * - try to find the first unused crtc that can drive this connector,
8609 * and use that if we find one
8612 /* See if we already have a CRTC for this connector */
8613 if (encoder
->crtc
) {
8614 crtc
= encoder
->crtc
;
8616 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
8619 ret
= drm_modeset_lock(&crtc
->primary
->mutex
, ctx
);
8623 old
->dpms_mode
= connector
->dpms
;
8624 old
->load_detect_temp
= false;
8626 /* Make sure the crtc and connector are running */
8627 if (connector
->dpms
!= DRM_MODE_DPMS_ON
)
8628 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
8633 /* Find an unused one (if possible) */
8634 for_each_crtc(dev
, possible_crtc
) {
8636 if (!(encoder
->possible_crtcs
& (1 << i
)))
8638 if (possible_crtc
->enabled
)
8640 /* This can occur when applying the pipe A quirk on resume. */
8641 if (to_intel_crtc(possible_crtc
)->new_enabled
)
8644 crtc
= possible_crtc
;
8649 * If we didn't find an unused CRTC, don't use any.
8652 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8656 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
8659 ret
= drm_modeset_lock(&crtc
->primary
->mutex
, ctx
);
8662 intel_encoder
->new_crtc
= to_intel_crtc(crtc
);
8663 to_intel_connector(connector
)->new_encoder
= intel_encoder
;
8665 intel_crtc
= to_intel_crtc(crtc
);
8666 intel_crtc
->new_enabled
= true;
8667 intel_crtc
->new_config
= intel_crtc
->config
;
8668 old
->dpms_mode
= connector
->dpms
;
8669 old
->load_detect_temp
= true;
8670 old
->release_fb
= NULL
;
8673 mode
= &load_detect_mode
;
8675 /* We need a framebuffer large enough to accommodate all accesses
8676 * that the plane may generate whilst we perform load detection.
8677 * We can not rely on the fbcon either being present (we get called
8678 * during its initialisation to detect all boot displays, or it may
8679 * not even exist) or that it is large enough to satisfy the
8682 fb
= mode_fits_in_fbdev(dev
, mode
);
8684 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8685 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
8686 old
->release_fb
= fb
;
8688 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8690 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8694 if (intel_set_mode(crtc
, mode
, 0, 0, fb
)) {
8695 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8696 if (old
->release_fb
)
8697 old
->release_fb
->funcs
->destroy(old
->release_fb
);
8701 /* let the connector get through one full cycle before testing */
8702 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
8706 intel_crtc
->new_enabled
= crtc
->enabled
;
8707 if (intel_crtc
->new_enabled
)
8708 intel_crtc
->new_config
= intel_crtc
->config
;
8710 intel_crtc
->new_config
= NULL
;
8712 if (ret
== -EDEADLK
) {
8713 drm_modeset_backoff(ctx
);
8720 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
8721 struct intel_load_detect_pipe
*old
)
8723 struct intel_encoder
*intel_encoder
=
8724 intel_attached_encoder(connector
);
8725 struct drm_encoder
*encoder
= &intel_encoder
->base
;
8726 struct drm_crtc
*crtc
= encoder
->crtc
;
8727 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8729 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8730 connector
->base
.id
, connector
->name
,
8731 encoder
->base
.id
, encoder
->name
);
8733 if (old
->load_detect_temp
) {
8734 to_intel_connector(connector
)->new_encoder
= NULL
;
8735 intel_encoder
->new_crtc
= NULL
;
8736 intel_crtc
->new_enabled
= false;
8737 intel_crtc
->new_config
= NULL
;
8738 intel_set_mode(crtc
, NULL
, 0, 0, NULL
);
8740 if (old
->release_fb
) {
8741 drm_framebuffer_unregister_private(old
->release_fb
);
8742 drm_framebuffer_unreference(old
->release_fb
);
8748 /* Switch crtc and encoder back off if necessary */
8749 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
)
8750 connector
->funcs
->dpms(connector
, old
->dpms_mode
);
8753 static int i9xx_pll_refclk(struct drm_device
*dev
,
8754 const struct intel_crtc_state
*pipe_config
)
8756 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8757 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
8759 if ((dpll
& PLL_REF_INPUT_MASK
) == PLLB_REF_INPUT_SPREADSPECTRUMIN
)
8760 return dev_priv
->vbt
.lvds_ssc_freq
;
8761 else if (HAS_PCH_SPLIT(dev
))
8763 else if (!IS_GEN2(dev
))
8769 /* Returns the clock of the currently programmed mode of the given pipe. */
8770 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
8771 struct intel_crtc_state
*pipe_config
)
8773 struct drm_device
*dev
= crtc
->base
.dev
;
8774 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8775 int pipe
= pipe_config
->cpu_transcoder
;
8776 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
8778 intel_clock_t clock
;
8779 int refclk
= i9xx_pll_refclk(dev
, pipe_config
);
8781 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
8782 fp
= pipe_config
->dpll_hw_state
.fp0
;
8784 fp
= pipe_config
->dpll_hw_state
.fp1
;
8786 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
8787 if (IS_PINEVIEW(dev
)) {
8788 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
8789 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
8791 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
8792 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
8795 if (!IS_GEN2(dev
)) {
8796 if (IS_PINEVIEW(dev
))
8797 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
8798 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
8800 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
8801 DPLL_FPA01_P1_POST_DIV_SHIFT
);
8803 switch (dpll
& DPLL_MODE_MASK
) {
8804 case DPLLB_MODE_DAC_SERIAL
:
8805 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
8808 case DPLLB_MODE_LVDS
:
8809 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
8813 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8814 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
8818 if (IS_PINEVIEW(dev
))
8819 pineview_clock(refclk
, &clock
);
8821 i9xx_clock(refclk
, &clock
);
8823 u32 lvds
= IS_I830(dev
) ? 0 : I915_READ(LVDS
);
8824 bool is_lvds
= (pipe
== 1) && (lvds
& LVDS_PORT_EN
);
8827 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
8828 DPLL_FPA01_P1_POST_DIV_SHIFT
);
8830 if (lvds
& LVDS_CLKB_POWER_UP
)
8835 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
8838 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
8839 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
8841 if (dpll
& PLL_P2_DIVIDE_BY_4
)
8847 i9xx_clock(refclk
, &clock
);
8851 * This value includes pixel_multiplier. We will use
8852 * port_clock to compute adjusted_mode.crtc_clock in the
8853 * encoder's get_config() function.
8855 pipe_config
->port_clock
= clock
.dot
;
8858 int intel_dotclock_calculate(int link_freq
,
8859 const struct intel_link_m_n
*m_n
)
8862 * The calculation for the data clock is:
8863 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8864 * But we want to avoid losing precison if possible, so:
8865 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8867 * and the link clock is simpler:
8868 * link_clock = (m * link_clock) / n
8874 return div_u64((u64
)m_n
->link_m
* link_freq
, m_n
->link_n
);
8877 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
8878 struct intel_crtc_state
*pipe_config
)
8880 struct drm_device
*dev
= crtc
->base
.dev
;
8882 /* read out port_clock from the DPLL */
8883 i9xx_crtc_clock_get(crtc
, pipe_config
);
8886 * This value does not include pixel_multiplier.
8887 * We will check that port_clock and adjusted_mode.crtc_clock
8888 * agree once we know their relationship in the encoder's
8889 * get_config() function.
8891 pipe_config
->base
.adjusted_mode
.crtc_clock
=
8892 intel_dotclock_calculate(intel_fdi_link_freq(dev
) * 10000,
8893 &pipe_config
->fdi_m_n
);
8896 /** Returns the currently programmed mode of the given pipe. */
8897 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
8898 struct drm_crtc
*crtc
)
8900 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8901 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8902 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
8903 struct drm_display_mode
*mode
;
8904 struct intel_crtc_state pipe_config
;
8905 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
8906 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
8907 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
8908 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
8909 enum pipe pipe
= intel_crtc
->pipe
;
8911 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
8916 * Construct a pipe_config sufficient for getting the clock info
8917 * back out of crtc_clock_get.
8919 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8920 * to use a real value here instead.
8922 pipe_config
.cpu_transcoder
= (enum transcoder
) pipe
;
8923 pipe_config
.pixel_multiplier
= 1;
8924 pipe_config
.dpll_hw_state
.dpll
= I915_READ(DPLL(pipe
));
8925 pipe_config
.dpll_hw_state
.fp0
= I915_READ(FP0(pipe
));
8926 pipe_config
.dpll_hw_state
.fp1
= I915_READ(FP1(pipe
));
8927 i9xx_crtc_clock_get(intel_crtc
, &pipe_config
);
8929 mode
->clock
= pipe_config
.port_clock
/ pipe_config
.pixel_multiplier
;
8930 mode
->hdisplay
= (htot
& 0xffff) + 1;
8931 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
8932 mode
->hsync_start
= (hsync
& 0xffff) + 1;
8933 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
8934 mode
->vdisplay
= (vtot
& 0xffff) + 1;
8935 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
8936 mode
->vsync_start
= (vsync
& 0xffff) + 1;
8937 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
8939 drm_mode_set_name(mode
);
8944 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
8946 struct drm_device
*dev
= crtc
->dev
;
8947 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8948 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8950 if (!HAS_GMCH_DISPLAY(dev
))
8953 if (!dev_priv
->lvds_downclock_avail
)
8957 * Since this is called by a timer, we should never get here in
8960 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
8961 int pipe
= intel_crtc
->pipe
;
8962 int dpll_reg
= DPLL(pipe
);
8965 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8967 assert_panel_unlocked(dev_priv
, pipe
);
8969 dpll
= I915_READ(dpll_reg
);
8970 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
8971 I915_WRITE(dpll_reg
, dpll
);
8972 intel_wait_for_vblank(dev
, pipe
);
8973 dpll
= I915_READ(dpll_reg
);
8974 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
8975 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8980 void intel_mark_busy(struct drm_device
*dev
)
8982 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8984 if (dev_priv
->mm
.busy
)
8987 intel_runtime_pm_get(dev_priv
);
8988 i915_update_gfx_val(dev_priv
);
8989 dev_priv
->mm
.busy
= true;
8992 void intel_mark_idle(struct drm_device
*dev
)
8994 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8995 struct drm_crtc
*crtc
;
8997 if (!dev_priv
->mm
.busy
)
9000 dev_priv
->mm
.busy
= false;
9002 if (!i915
.powersave
)
9005 for_each_crtc(dev
, crtc
) {
9006 if (!crtc
->primary
->fb
)
9009 intel_decrease_pllclock(crtc
);
9012 if (INTEL_INFO(dev
)->gen
>= 6)
9013 gen6_rps_idle(dev
->dev_private
);
9016 intel_runtime_pm_put(dev_priv
);
9019 static void intel_crtc_set_state(struct intel_crtc
*crtc
,
9020 struct intel_crtc_state
*crtc_state
)
9022 kfree(crtc
->config
);
9023 crtc
->config
= crtc_state
;
9024 crtc
->base
.state
= &crtc_state
->base
;
9027 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
9029 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9030 struct drm_device
*dev
= crtc
->dev
;
9031 struct intel_unpin_work
*work
;
9033 spin_lock_irq(&dev
->event_lock
);
9034 work
= intel_crtc
->unpin_work
;
9035 intel_crtc
->unpin_work
= NULL
;
9036 spin_unlock_irq(&dev
->event_lock
);
9039 cancel_work_sync(&work
->work
);
9043 intel_crtc_set_state(intel_crtc
, NULL
);
9044 drm_crtc_cleanup(crtc
);
9049 static void intel_unpin_work_fn(struct work_struct
*__work
)
9051 struct intel_unpin_work
*work
=
9052 container_of(__work
, struct intel_unpin_work
, work
);
9053 struct drm_device
*dev
= work
->crtc
->dev
;
9054 enum pipe pipe
= to_intel_crtc(work
->crtc
)->pipe
;
9056 mutex_lock(&dev
->struct_mutex
);
9057 intel_unpin_fb_obj(work
->old_fb_obj
);
9058 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
9059 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
9061 intel_fbc_update(dev
);
9063 if (work
->flip_queued_req
)
9064 i915_gem_request_assign(&work
->flip_queued_req
, NULL
);
9065 mutex_unlock(&dev
->struct_mutex
);
9067 intel_frontbuffer_flip_complete(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
9069 BUG_ON(atomic_read(&to_intel_crtc(work
->crtc
)->unpin_work_count
) == 0);
9070 atomic_dec(&to_intel_crtc(work
->crtc
)->unpin_work_count
);
9075 static void do_intel_finish_page_flip(struct drm_device
*dev
,
9076 struct drm_crtc
*crtc
)
9078 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9079 struct intel_unpin_work
*work
;
9080 unsigned long flags
;
9082 /* Ignore early vblank irqs */
9083 if (intel_crtc
== NULL
)
9087 * This is called both by irq handlers and the reset code (to complete
9088 * lost pageflips) so needs the full irqsave spinlocks.
9090 spin_lock_irqsave(&dev
->event_lock
, flags
);
9091 work
= intel_crtc
->unpin_work
;
9093 /* Ensure we don't miss a work->pending update ... */
9096 if (work
== NULL
|| atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
9097 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9101 page_flip_completed(intel_crtc
);
9103 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9106 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
9108 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9109 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
9111 do_intel_finish_page_flip(dev
, crtc
);
9114 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
9116 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9117 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
9119 do_intel_finish_page_flip(dev
, crtc
);
9122 /* Is 'a' after or equal to 'b'? */
9123 static bool g4x_flip_count_after_eq(u32 a
, u32 b
)
9125 return !((a
- b
) & 0x80000000);
9128 static bool page_flip_finished(struct intel_crtc
*crtc
)
9130 struct drm_device
*dev
= crtc
->base
.dev
;
9131 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9133 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
9134 crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
9138 * The relevant registers doen't exist on pre-ctg.
9139 * As the flip done interrupt doesn't trigger for mmio
9140 * flips on gmch platforms, a flip count check isn't
9141 * really needed there. But since ctg has the registers,
9142 * include it in the check anyway.
9144 if (INTEL_INFO(dev
)->gen
< 5 && !IS_G4X(dev
))
9148 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9149 * used the same base address. In that case the mmio flip might
9150 * have completed, but the CS hasn't even executed the flip yet.
9152 * A flip count check isn't enough as the CS might have updated
9153 * the base address just after start of vblank, but before we
9154 * managed to process the interrupt. This means we'd complete the
9157 * Combining both checks should get us a good enough result. It may
9158 * still happen that the CS flip has been executed, but has not
9159 * yet actually completed. But in case the base address is the same
9160 * anyway, we don't really care.
9162 return (I915_READ(DSPSURFLIVE(crtc
->plane
)) & ~0xfff) ==
9163 crtc
->unpin_work
->gtt_offset
&&
9164 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc
->pipe
)),
9165 crtc
->unpin_work
->flip_count
);
9168 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
9170 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9171 struct intel_crtc
*intel_crtc
=
9172 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
9173 unsigned long flags
;
9177 * This is called both by irq handlers and the reset code (to complete
9178 * lost pageflips) so needs the full irqsave spinlocks.
9180 * NB: An MMIO update of the plane base pointer will also
9181 * generate a page-flip completion irq, i.e. every modeset
9182 * is also accompanied by a spurious intel_prepare_page_flip().
9184 spin_lock_irqsave(&dev
->event_lock
, flags
);
9185 if (intel_crtc
->unpin_work
&& page_flip_finished(intel_crtc
))
9186 atomic_inc_not_zero(&intel_crtc
->unpin_work
->pending
);
9187 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9190 static inline void intel_mark_page_flip_active(struct intel_crtc
*intel_crtc
)
9192 /* Ensure that the work item is consistent when activating it ... */
9194 atomic_set(&intel_crtc
->unpin_work
->pending
, INTEL_FLIP_PENDING
);
9195 /* and that it is marked active as soon as the irq could fire. */
9199 static int intel_gen2_queue_flip(struct drm_device
*dev
,
9200 struct drm_crtc
*crtc
,
9201 struct drm_framebuffer
*fb
,
9202 struct drm_i915_gem_object
*obj
,
9203 struct intel_engine_cs
*ring
,
9206 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9210 ret
= intel_ring_begin(ring
, 6);
9214 /* Can't queue multiple flips, so wait for the previous
9215 * one to finish before executing the next.
9217 if (intel_crtc
->plane
)
9218 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
9220 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
9221 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
9222 intel_ring_emit(ring
, MI_NOOP
);
9223 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
9224 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9225 intel_ring_emit(ring
, fb
->pitches
[0]);
9226 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9227 intel_ring_emit(ring
, 0); /* aux display base address, unused */
9229 intel_mark_page_flip_active(intel_crtc
);
9230 __intel_ring_advance(ring
);
9234 static int intel_gen3_queue_flip(struct drm_device
*dev
,
9235 struct drm_crtc
*crtc
,
9236 struct drm_framebuffer
*fb
,
9237 struct drm_i915_gem_object
*obj
,
9238 struct intel_engine_cs
*ring
,
9241 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9245 ret
= intel_ring_begin(ring
, 6);
9249 if (intel_crtc
->plane
)
9250 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
9252 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
9253 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
9254 intel_ring_emit(ring
, MI_NOOP
);
9255 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
9256 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9257 intel_ring_emit(ring
, fb
->pitches
[0]);
9258 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9259 intel_ring_emit(ring
, MI_NOOP
);
9261 intel_mark_page_flip_active(intel_crtc
);
9262 __intel_ring_advance(ring
);
9266 static int intel_gen4_queue_flip(struct drm_device
*dev
,
9267 struct drm_crtc
*crtc
,
9268 struct drm_framebuffer
*fb
,
9269 struct drm_i915_gem_object
*obj
,
9270 struct intel_engine_cs
*ring
,
9273 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9274 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9275 uint32_t pf
, pipesrc
;
9278 ret
= intel_ring_begin(ring
, 4);
9282 /* i965+ uses the linear or tiled offsets from the
9283 * Display Registers (which do not change across a page-flip)
9284 * so we need only reprogram the base address.
9286 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
9287 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9288 intel_ring_emit(ring
, fb
->pitches
[0]);
9289 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
|
9292 /* XXX Enabling the panel-fitter across page-flip is so far
9293 * untested on non-native modes, so ignore it for now.
9294 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9297 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
9298 intel_ring_emit(ring
, pf
| pipesrc
);
9300 intel_mark_page_flip_active(intel_crtc
);
9301 __intel_ring_advance(ring
);
9305 static int intel_gen6_queue_flip(struct drm_device
*dev
,
9306 struct drm_crtc
*crtc
,
9307 struct drm_framebuffer
*fb
,
9308 struct drm_i915_gem_object
*obj
,
9309 struct intel_engine_cs
*ring
,
9312 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9313 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9314 uint32_t pf
, pipesrc
;
9317 ret
= intel_ring_begin(ring
, 4);
9321 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
9322 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9323 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
9324 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9326 /* Contrary to the suggestions in the documentation,
9327 * "Enable Panel Fitter" does not seem to be required when page
9328 * flipping with a non-native mode, and worse causes a normal
9330 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9333 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
9334 intel_ring_emit(ring
, pf
| pipesrc
);
9336 intel_mark_page_flip_active(intel_crtc
);
9337 __intel_ring_advance(ring
);
9341 static int intel_gen7_queue_flip(struct drm_device
*dev
,
9342 struct drm_crtc
*crtc
,
9343 struct drm_framebuffer
*fb
,
9344 struct drm_i915_gem_object
*obj
,
9345 struct intel_engine_cs
*ring
,
9348 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9349 uint32_t plane_bit
= 0;
9352 switch (intel_crtc
->plane
) {
9354 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
9357 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
9360 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
9363 WARN_ONCE(1, "unknown plane in flip command\n");
9368 if (ring
->id
== RCS
) {
9371 * On Gen 8, SRM is now taking an extra dword to accommodate
9372 * 48bits addresses, and we need a NOOP for the batch size to
9380 * BSpec MI_DISPLAY_FLIP for IVB:
9381 * "The full packet must be contained within the same cache line."
9383 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9384 * cacheline, if we ever start emitting more commands before
9385 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9386 * then do the cacheline alignment, and finally emit the
9389 ret
= intel_ring_cacheline_align(ring
);
9393 ret
= intel_ring_begin(ring
, len
);
9397 /* Unmask the flip-done completion message. Note that the bspec says that
9398 * we should do this for both the BCS and RCS, and that we must not unmask
9399 * more than one flip event at any time (or ensure that one flip message
9400 * can be sent by waiting for flip-done prior to queueing new flips).
9401 * Experimentation says that BCS works despite DERRMR masking all
9402 * flip-done completion events and that unmasking all planes at once
9403 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9404 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9406 if (ring
->id
== RCS
) {
9407 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
9408 intel_ring_emit(ring
, DERRMR
);
9409 intel_ring_emit(ring
, ~(DERRMR_PIPEA_PRI_FLIP_DONE
|
9410 DERRMR_PIPEB_PRI_FLIP_DONE
|
9411 DERRMR_PIPEC_PRI_FLIP_DONE
));
9413 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM_GEN8(1) |
9414 MI_SRM_LRM_GLOBAL_GTT
);
9416 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM(1) |
9417 MI_SRM_LRM_GLOBAL_GTT
);
9418 intel_ring_emit(ring
, DERRMR
);
9419 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
+ 256);
9421 intel_ring_emit(ring
, 0);
9422 intel_ring_emit(ring
, MI_NOOP
);
9426 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
9427 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
9428 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9429 intel_ring_emit(ring
, (MI_NOOP
));
9431 intel_mark_page_flip_active(intel_crtc
);
9432 __intel_ring_advance(ring
);
9436 static bool use_mmio_flip(struct intel_engine_cs
*ring
,
9437 struct drm_i915_gem_object
*obj
)
9440 * This is not being used for older platforms, because
9441 * non-availability of flip done interrupt forces us to use
9442 * CS flips. Older platforms derive flip done using some clever
9443 * tricks involving the flip_pending status bits and vblank irqs.
9444 * So using MMIO flips there would disrupt this mechanism.
9450 if (INTEL_INFO(ring
->dev
)->gen
< 5)
9453 if (i915
.use_mmio_flip
< 0)
9455 else if (i915
.use_mmio_flip
> 0)
9457 else if (i915
.enable_execlists
)
9460 return ring
!= i915_gem_request_get_ring(obj
->last_read_req
);
9463 static void skl_do_mmio_flip(struct intel_crtc
*intel_crtc
)
9465 struct drm_device
*dev
= intel_crtc
->base
.dev
;
9466 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9467 struct drm_framebuffer
*fb
= intel_crtc
->base
.primary
->fb
;
9468 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
9469 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
9470 const enum pipe pipe
= intel_crtc
->pipe
;
9473 ctl
= I915_READ(PLANE_CTL(pipe
, 0));
9474 ctl
&= ~PLANE_CTL_TILED_MASK
;
9475 if (obj
->tiling_mode
== I915_TILING_X
)
9476 ctl
|= PLANE_CTL_TILED_X
;
9479 * The stride is either expressed as a multiple of 64 bytes chunks for
9480 * linear buffers or in number of tiles for tiled buffers.
9482 stride
= fb
->pitches
[0] >> 6;
9483 if (obj
->tiling_mode
== I915_TILING_X
)
9484 stride
= fb
->pitches
[0] >> 9; /* X tiles are 512 bytes wide */
9487 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
9488 * PLANE_SURF updates, the update is then guaranteed to be atomic.
9490 I915_WRITE(PLANE_CTL(pipe
, 0), ctl
);
9491 I915_WRITE(PLANE_STRIDE(pipe
, 0), stride
);
9493 I915_WRITE(PLANE_SURF(pipe
, 0), intel_crtc
->unpin_work
->gtt_offset
);
9494 POSTING_READ(PLANE_SURF(pipe
, 0));
9497 static void ilk_do_mmio_flip(struct intel_crtc
*intel_crtc
)
9499 struct drm_device
*dev
= intel_crtc
->base
.dev
;
9500 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9501 struct intel_framebuffer
*intel_fb
=
9502 to_intel_framebuffer(intel_crtc
->base
.primary
->fb
);
9503 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
9507 reg
= DSPCNTR(intel_crtc
->plane
);
9508 dspcntr
= I915_READ(reg
);
9510 if (obj
->tiling_mode
!= I915_TILING_NONE
)
9511 dspcntr
|= DISPPLANE_TILED
;
9513 dspcntr
&= ~DISPPLANE_TILED
;
9515 I915_WRITE(reg
, dspcntr
);
9517 I915_WRITE(DSPSURF(intel_crtc
->plane
),
9518 intel_crtc
->unpin_work
->gtt_offset
);
9519 POSTING_READ(DSPSURF(intel_crtc
->plane
));
9524 * XXX: This is the temporary way to update the plane registers until we get
9525 * around to using the usual plane update functions for MMIO flips
9527 static void intel_do_mmio_flip(struct intel_crtc
*intel_crtc
)
9529 struct drm_device
*dev
= intel_crtc
->base
.dev
;
9531 u32 start_vbl_count
;
9533 intel_mark_page_flip_active(intel_crtc
);
9535 atomic_update
= intel_pipe_update_start(intel_crtc
, &start_vbl_count
);
9537 if (INTEL_INFO(dev
)->gen
>= 9)
9538 skl_do_mmio_flip(intel_crtc
);
9540 /* use_mmio_flip() retricts MMIO flips to ilk+ */
9541 ilk_do_mmio_flip(intel_crtc
);
9544 intel_pipe_update_end(intel_crtc
, start_vbl_count
);
9547 static void intel_mmio_flip_work_func(struct work_struct
*work
)
9549 struct intel_crtc
*crtc
=
9550 container_of(work
, struct intel_crtc
, mmio_flip
.work
);
9551 struct intel_mmio_flip
*mmio_flip
;
9553 mmio_flip
= &crtc
->mmio_flip
;
9555 WARN_ON(__i915_wait_request(mmio_flip
->req
,
9556 crtc
->reset_counter
,
9557 false, NULL
, NULL
) != 0);
9559 intel_do_mmio_flip(crtc
);
9560 if (mmio_flip
->req
) {
9561 mutex_lock(&crtc
->base
.dev
->struct_mutex
);
9562 i915_gem_request_assign(&mmio_flip
->req
, NULL
);
9563 mutex_unlock(&crtc
->base
.dev
->struct_mutex
);
9567 static int intel_queue_mmio_flip(struct drm_device
*dev
,
9568 struct drm_crtc
*crtc
,
9569 struct drm_framebuffer
*fb
,
9570 struct drm_i915_gem_object
*obj
,
9571 struct intel_engine_cs
*ring
,
9574 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9576 i915_gem_request_assign(&intel_crtc
->mmio_flip
.req
,
9577 obj
->last_write_req
);
9579 schedule_work(&intel_crtc
->mmio_flip
.work
);
9584 static int intel_gen9_queue_flip(struct drm_device
*dev
,
9585 struct drm_crtc
*crtc
,
9586 struct drm_framebuffer
*fb
,
9587 struct drm_i915_gem_object
*obj
,
9588 struct intel_engine_cs
*ring
,
9591 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9592 uint32_t plane
= 0, stride
;
9595 switch(intel_crtc
->pipe
) {
9597 plane
= MI_DISPLAY_FLIP_SKL_PLANE_1_A
;
9600 plane
= MI_DISPLAY_FLIP_SKL_PLANE_1_B
;
9603 plane
= MI_DISPLAY_FLIP_SKL_PLANE_1_C
;
9606 WARN_ONCE(1, "unknown plane in flip command\n");
9610 switch (obj
->tiling_mode
) {
9611 case I915_TILING_NONE
:
9612 stride
= fb
->pitches
[0] >> 6;
9615 stride
= fb
->pitches
[0] >> 9;
9618 WARN_ONCE(1, "unknown tiling in flip command\n");
9622 ret
= intel_ring_begin(ring
, 10);
9626 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
9627 intel_ring_emit(ring
, DERRMR
);
9628 intel_ring_emit(ring
, ~(DERRMR_PIPEA_PRI_FLIP_DONE
|
9629 DERRMR_PIPEB_PRI_FLIP_DONE
|
9630 DERRMR_PIPEC_PRI_FLIP_DONE
));
9631 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM_GEN8(1) |
9632 MI_SRM_LRM_GLOBAL_GTT
);
9633 intel_ring_emit(ring
, DERRMR
);
9634 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
+ 256);
9635 intel_ring_emit(ring
, 0);
9637 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane
);
9638 intel_ring_emit(ring
, stride
<< 6 | obj
->tiling_mode
);
9639 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9641 intel_mark_page_flip_active(intel_crtc
);
9642 __intel_ring_advance(ring
);
9647 static int intel_default_queue_flip(struct drm_device
*dev
,
9648 struct drm_crtc
*crtc
,
9649 struct drm_framebuffer
*fb
,
9650 struct drm_i915_gem_object
*obj
,
9651 struct intel_engine_cs
*ring
,
9657 static bool __intel_pageflip_stall_check(struct drm_device
*dev
,
9658 struct drm_crtc
*crtc
)
9660 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9661 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9662 struct intel_unpin_work
*work
= intel_crtc
->unpin_work
;
9665 if (atomic_read(&work
->pending
) >= INTEL_FLIP_COMPLETE
)
9668 if (!work
->enable_stall_check
)
9671 if (work
->flip_ready_vblank
== 0) {
9672 if (work
->flip_queued_req
&&
9673 !i915_gem_request_completed(work
->flip_queued_req
, true))
9676 work
->flip_ready_vblank
= drm_vblank_count(dev
, intel_crtc
->pipe
);
9679 if (drm_vblank_count(dev
, intel_crtc
->pipe
) - work
->flip_ready_vblank
< 3)
9682 /* Potential stall - if we see that the flip has happened,
9683 * assume a missed interrupt. */
9684 if (INTEL_INFO(dev
)->gen
>= 4)
9685 addr
= I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc
->plane
)));
9687 addr
= I915_READ(DSPADDR(intel_crtc
->plane
));
9689 /* There is a potential issue here with a false positive after a flip
9690 * to the same address. We could address this by checking for a
9691 * non-incrementing frame counter.
9693 return addr
== work
->gtt_offset
;
9696 void intel_check_page_flip(struct drm_device
*dev
, int pipe
)
9698 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9699 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
9700 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9707 spin_lock(&dev
->event_lock
);
9708 if (intel_crtc
->unpin_work
&& __intel_pageflip_stall_check(dev
, crtc
)) {
9709 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9710 intel_crtc
->unpin_work
->flip_queued_vblank
, drm_vblank_count(dev
, pipe
));
9711 page_flip_completed(intel_crtc
);
9713 spin_unlock(&dev
->event_lock
);
9716 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
9717 struct drm_framebuffer
*fb
,
9718 struct drm_pending_vblank_event
*event
,
9719 uint32_t page_flip_flags
)
9721 struct drm_device
*dev
= crtc
->dev
;
9722 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9723 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
9724 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
9725 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9726 struct drm_plane
*primary
= crtc
->primary
;
9727 enum pipe pipe
= intel_crtc
->pipe
;
9728 struct intel_unpin_work
*work
;
9729 struct intel_engine_cs
*ring
;
9733 * drm_mode_page_flip_ioctl() should already catch this, but double
9734 * check to be safe. In the future we may enable pageflipping from
9735 * a disabled primary plane.
9737 if (WARN_ON(intel_fb_obj(old_fb
) == NULL
))
9740 /* Can't change pixel format via MI display flips. */
9741 if (fb
->pixel_format
!= crtc
->primary
->fb
->pixel_format
)
9745 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9746 * Note that pitch changes could also affect these register.
9748 if (INTEL_INFO(dev
)->gen
> 3 &&
9749 (fb
->offsets
[0] != crtc
->primary
->fb
->offsets
[0] ||
9750 fb
->pitches
[0] != crtc
->primary
->fb
->pitches
[0]))
9753 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
9756 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
9760 work
->event
= event
;
9762 work
->old_fb_obj
= intel_fb_obj(old_fb
);
9763 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
9765 ret
= drm_crtc_vblank_get(crtc
);
9769 /* We borrow the event spin lock for protecting unpin_work */
9770 spin_lock_irq(&dev
->event_lock
);
9771 if (intel_crtc
->unpin_work
) {
9772 /* Before declaring the flip queue wedged, check if
9773 * the hardware completed the operation behind our backs.
9775 if (__intel_pageflip_stall_check(dev
, crtc
)) {
9776 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9777 page_flip_completed(intel_crtc
);
9779 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9780 spin_unlock_irq(&dev
->event_lock
);
9782 drm_crtc_vblank_put(crtc
);
9787 intel_crtc
->unpin_work
= work
;
9788 spin_unlock_irq(&dev
->event_lock
);
9790 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
9791 flush_workqueue(dev_priv
->wq
);
9793 ret
= i915_mutex_lock_interruptible(dev
);
9797 /* Reference the objects for the scheduled work. */
9798 drm_gem_object_reference(&work
->old_fb_obj
->base
);
9799 drm_gem_object_reference(&obj
->base
);
9801 crtc
->primary
->fb
= fb
;
9803 work
->pending_flip_obj
= obj
;
9805 atomic_inc(&intel_crtc
->unpin_work_count
);
9806 intel_crtc
->reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
9808 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
9809 work
->flip_count
= I915_READ(PIPE_FLIPCOUNT_GM45(pipe
)) + 1;
9811 if (IS_VALLEYVIEW(dev
)) {
9812 ring
= &dev_priv
->ring
[BCS
];
9813 if (obj
->tiling_mode
!= work
->old_fb_obj
->tiling_mode
)
9814 /* vlv: DISPLAY_FLIP fails to change tiling */
9816 } else if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
9817 ring
= &dev_priv
->ring
[BCS
];
9818 } else if (INTEL_INFO(dev
)->gen
>= 7) {
9819 ring
= i915_gem_request_get_ring(obj
->last_read_req
);
9820 if (ring
== NULL
|| ring
->id
!= RCS
)
9821 ring
= &dev_priv
->ring
[BCS
];
9823 ring
= &dev_priv
->ring
[RCS
];
9826 ret
= intel_pin_and_fence_fb_obj(crtc
->primary
, fb
, ring
);
9828 goto cleanup_pending
;
9831 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
;
9833 if (use_mmio_flip(ring
, obj
)) {
9834 ret
= intel_queue_mmio_flip(dev
, crtc
, fb
, obj
, ring
,
9839 i915_gem_request_assign(&work
->flip_queued_req
,
9840 obj
->last_write_req
);
9842 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
, ring
,
9847 i915_gem_request_assign(&work
->flip_queued_req
,
9848 intel_ring_get_request(ring
));
9851 work
->flip_queued_vblank
= drm_vblank_count(dev
, intel_crtc
->pipe
);
9852 work
->enable_stall_check
= true;
9854 i915_gem_track_fb(work
->old_fb_obj
, obj
,
9855 INTEL_FRONTBUFFER_PRIMARY(pipe
));
9857 intel_fbc_disable(dev
);
9858 intel_frontbuffer_flip_prepare(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
9859 mutex_unlock(&dev
->struct_mutex
);
9861 trace_i915_flip_request(intel_crtc
->plane
, obj
);
9866 intel_unpin_fb_obj(obj
);
9868 atomic_dec(&intel_crtc
->unpin_work_count
);
9869 crtc
->primary
->fb
= old_fb
;
9870 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
9871 drm_gem_object_unreference(&obj
->base
);
9872 mutex_unlock(&dev
->struct_mutex
);
9875 spin_lock_irq(&dev
->event_lock
);
9876 intel_crtc
->unpin_work
= NULL
;
9877 spin_unlock_irq(&dev
->event_lock
);
9879 drm_crtc_vblank_put(crtc
);
9885 ret
= intel_plane_restore(primary
);
9886 if (ret
== 0 && event
) {
9887 spin_lock_irq(&dev
->event_lock
);
9888 drm_send_vblank_event(dev
, pipe
, event
);
9889 spin_unlock_irq(&dev
->event_lock
);
9895 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
9896 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
9897 .load_lut
= intel_crtc_load_lut
,
9898 .atomic_begin
= intel_begin_crtc_commit
,
9899 .atomic_flush
= intel_finish_crtc_commit
,
9903 * intel_modeset_update_staged_output_state
9905 * Updates the staged output configuration state, e.g. after we've read out the
9908 static void intel_modeset_update_staged_output_state(struct drm_device
*dev
)
9910 struct intel_crtc
*crtc
;
9911 struct intel_encoder
*encoder
;
9912 struct intel_connector
*connector
;
9914 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9916 connector
->new_encoder
=
9917 to_intel_encoder(connector
->base
.encoder
);
9920 for_each_intel_encoder(dev
, encoder
) {
9922 to_intel_crtc(encoder
->base
.crtc
);
9925 for_each_intel_crtc(dev
, crtc
) {
9926 crtc
->new_enabled
= crtc
->base
.enabled
;
9928 if (crtc
->new_enabled
)
9929 crtc
->new_config
= crtc
->config
;
9931 crtc
->new_config
= NULL
;
9936 * intel_modeset_commit_output_state
9938 * This function copies the stage display pipe configuration to the real one.
9940 static void intel_modeset_commit_output_state(struct drm_device
*dev
)
9942 struct intel_crtc
*crtc
;
9943 struct intel_encoder
*encoder
;
9944 struct intel_connector
*connector
;
9946 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9948 connector
->base
.encoder
= &connector
->new_encoder
->base
;
9951 for_each_intel_encoder(dev
, encoder
) {
9952 encoder
->base
.crtc
= &encoder
->new_crtc
->base
;
9955 for_each_intel_crtc(dev
, crtc
) {
9956 crtc
->base
.enabled
= crtc
->new_enabled
;
9961 connected_sink_compute_bpp(struct intel_connector
*connector
,
9962 struct intel_crtc_state
*pipe_config
)
9964 int bpp
= pipe_config
->pipe_bpp
;
9966 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9967 connector
->base
.base
.id
,
9968 connector
->base
.name
);
9970 /* Don't use an invalid EDID bpc value */
9971 if (connector
->base
.display_info
.bpc
&&
9972 connector
->base
.display_info
.bpc
* 3 < bpp
) {
9973 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9974 bpp
, connector
->base
.display_info
.bpc
*3);
9975 pipe_config
->pipe_bpp
= connector
->base
.display_info
.bpc
*3;
9978 /* Clamp bpp to 8 on screens without EDID 1.4 */
9979 if (connector
->base
.display_info
.bpc
== 0 && bpp
> 24) {
9980 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9982 pipe_config
->pipe_bpp
= 24;
9987 compute_baseline_pipe_bpp(struct intel_crtc
*crtc
,
9988 struct drm_framebuffer
*fb
,
9989 struct intel_crtc_state
*pipe_config
)
9991 struct drm_device
*dev
= crtc
->base
.dev
;
9992 struct intel_connector
*connector
;
9995 switch (fb
->pixel_format
) {
9997 bpp
= 8*3; /* since we go through a colormap */
9999 case DRM_FORMAT_XRGB1555
:
10000 case DRM_FORMAT_ARGB1555
:
10001 /* checked in intel_framebuffer_init already */
10002 if (WARN_ON(INTEL_INFO(dev
)->gen
> 3))
10004 case DRM_FORMAT_RGB565
:
10005 bpp
= 6*3; /* min is 18bpp */
10007 case DRM_FORMAT_XBGR8888
:
10008 case DRM_FORMAT_ABGR8888
:
10009 /* checked in intel_framebuffer_init already */
10010 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
10012 case DRM_FORMAT_XRGB8888
:
10013 case DRM_FORMAT_ARGB8888
:
10016 case DRM_FORMAT_XRGB2101010
:
10017 case DRM_FORMAT_ARGB2101010
:
10018 case DRM_FORMAT_XBGR2101010
:
10019 case DRM_FORMAT_ABGR2101010
:
10020 /* checked in intel_framebuffer_init already */
10021 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
10025 /* TODO: gen4+ supports 16 bpc floating point, too. */
10027 DRM_DEBUG_KMS("unsupported depth\n");
10031 pipe_config
->pipe_bpp
= bpp
;
10033 /* Clamp display bpp to EDID value */
10034 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10036 if (!connector
->new_encoder
||
10037 connector
->new_encoder
->new_crtc
!= crtc
)
10040 connected_sink_compute_bpp(connector
, pipe_config
);
10046 static void intel_dump_crtc_timings(const struct drm_display_mode
*mode
)
10048 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10049 "type: 0x%x flags: 0x%x\n",
10051 mode
->crtc_hdisplay
, mode
->crtc_hsync_start
,
10052 mode
->crtc_hsync_end
, mode
->crtc_htotal
,
10053 mode
->crtc_vdisplay
, mode
->crtc_vsync_start
,
10054 mode
->crtc_vsync_end
, mode
->crtc_vtotal
, mode
->type
, mode
->flags
);
10057 static void intel_dump_pipe_config(struct intel_crtc
*crtc
,
10058 struct intel_crtc_state
*pipe_config
,
10059 const char *context
)
10061 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc
->base
.base
.id
,
10062 context
, pipe_name(crtc
->pipe
));
10064 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config
->cpu_transcoder
));
10065 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10066 pipe_config
->pipe_bpp
, pipe_config
->dither
);
10067 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10068 pipe_config
->has_pch_encoder
,
10069 pipe_config
->fdi_lanes
,
10070 pipe_config
->fdi_m_n
.gmch_m
, pipe_config
->fdi_m_n
.gmch_n
,
10071 pipe_config
->fdi_m_n
.link_m
, pipe_config
->fdi_m_n
.link_n
,
10072 pipe_config
->fdi_m_n
.tu
);
10073 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10074 pipe_config
->has_dp_encoder
,
10075 pipe_config
->dp_m_n
.gmch_m
, pipe_config
->dp_m_n
.gmch_n
,
10076 pipe_config
->dp_m_n
.link_m
, pipe_config
->dp_m_n
.link_n
,
10077 pipe_config
->dp_m_n
.tu
);
10079 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10080 pipe_config
->has_dp_encoder
,
10081 pipe_config
->dp_m2_n2
.gmch_m
,
10082 pipe_config
->dp_m2_n2
.gmch_n
,
10083 pipe_config
->dp_m2_n2
.link_m
,
10084 pipe_config
->dp_m2_n2
.link_n
,
10085 pipe_config
->dp_m2_n2
.tu
);
10087 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10088 pipe_config
->has_audio
,
10089 pipe_config
->has_infoframe
);
10091 DRM_DEBUG_KMS("requested mode:\n");
10092 drm_mode_debug_printmodeline(&pipe_config
->base
.mode
);
10093 DRM_DEBUG_KMS("adjusted mode:\n");
10094 drm_mode_debug_printmodeline(&pipe_config
->base
.adjusted_mode
);
10095 intel_dump_crtc_timings(&pipe_config
->base
.adjusted_mode
);
10096 DRM_DEBUG_KMS("port clock: %d\n", pipe_config
->port_clock
);
10097 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10098 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
);
10099 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10100 pipe_config
->gmch_pfit
.control
,
10101 pipe_config
->gmch_pfit
.pgm_ratios
,
10102 pipe_config
->gmch_pfit
.lvds_border_bits
);
10103 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10104 pipe_config
->pch_pfit
.pos
,
10105 pipe_config
->pch_pfit
.size
,
10106 pipe_config
->pch_pfit
.enabled
? "enabled" : "disabled");
10107 DRM_DEBUG_KMS("ips: %i\n", pipe_config
->ips_enabled
);
10108 DRM_DEBUG_KMS("double wide: %i\n", pipe_config
->double_wide
);
10111 static bool encoders_cloneable(const struct intel_encoder
*a
,
10112 const struct intel_encoder
*b
)
10114 /* masks could be asymmetric, so check both ways */
10115 return a
== b
|| (a
->cloneable
& (1 << b
->type
) &&
10116 b
->cloneable
& (1 << a
->type
));
10119 static bool check_single_encoder_cloning(struct intel_crtc
*crtc
,
10120 struct intel_encoder
*encoder
)
10122 struct drm_device
*dev
= crtc
->base
.dev
;
10123 struct intel_encoder
*source_encoder
;
10125 for_each_intel_encoder(dev
, source_encoder
) {
10126 if (source_encoder
->new_crtc
!= crtc
)
10129 if (!encoders_cloneable(encoder
, source_encoder
))
10136 static bool check_encoder_cloning(struct intel_crtc
*crtc
)
10138 struct drm_device
*dev
= crtc
->base
.dev
;
10139 struct intel_encoder
*encoder
;
10141 for_each_intel_encoder(dev
, encoder
) {
10142 if (encoder
->new_crtc
!= crtc
)
10145 if (!check_single_encoder_cloning(crtc
, encoder
))
10152 static bool check_digital_port_conflicts(struct drm_device
*dev
)
10154 struct intel_connector
*connector
;
10155 unsigned int used_ports
= 0;
10158 * Walk the connector list instead of the encoder
10159 * list to detect the problem on ddi platforms
10160 * where there's just one encoder per digital port.
10162 list_for_each_entry(connector
,
10163 &dev
->mode_config
.connector_list
, base
.head
) {
10164 struct intel_encoder
*encoder
= connector
->new_encoder
;
10169 WARN_ON(!encoder
->new_crtc
);
10171 switch (encoder
->type
) {
10172 unsigned int port_mask
;
10173 case INTEL_OUTPUT_UNKNOWN
:
10174 if (WARN_ON(!HAS_DDI(dev
)))
10176 case INTEL_OUTPUT_DISPLAYPORT
:
10177 case INTEL_OUTPUT_HDMI
:
10178 case INTEL_OUTPUT_EDP
:
10179 port_mask
= 1 << enc_to_dig_port(&encoder
->base
)->port
;
10181 /* the same port mustn't appear more than once */
10182 if (used_ports
& port_mask
)
10185 used_ports
|= port_mask
;
10194 static struct intel_crtc_state
*
10195 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
10196 struct drm_framebuffer
*fb
,
10197 struct drm_display_mode
*mode
)
10199 struct drm_device
*dev
= crtc
->dev
;
10200 struct intel_encoder
*encoder
;
10201 struct intel_crtc_state
*pipe_config
;
10202 int plane_bpp
, ret
= -EINVAL
;
10205 if (!check_encoder_cloning(to_intel_crtc(crtc
))) {
10206 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10207 return ERR_PTR(-EINVAL
);
10210 if (!check_digital_port_conflicts(dev
)) {
10211 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
10212 return ERR_PTR(-EINVAL
);
10215 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
10217 return ERR_PTR(-ENOMEM
);
10219 drm_mode_copy(&pipe_config
->base
.adjusted_mode
, mode
);
10220 drm_mode_copy(&pipe_config
->base
.mode
, mode
);
10222 pipe_config
->cpu_transcoder
=
10223 (enum transcoder
) to_intel_crtc(crtc
)->pipe
;
10224 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
10227 * Sanitize sync polarity flags based on requested ones. If neither
10228 * positive or negative polarity is requested, treat this as meaning
10229 * negative polarity.
10231 if (!(pipe_config
->base
.adjusted_mode
.flags
&
10232 (DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NHSYNC
)))
10233 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
10235 if (!(pipe_config
->base
.adjusted_mode
.flags
&
10236 (DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_NVSYNC
)))
10237 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
10239 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10240 * plane pixel format and any sink constraints into account. Returns the
10241 * source plane bpp so that dithering can be selected on mismatches
10242 * after encoders and crtc also have had their say. */
10243 plane_bpp
= compute_baseline_pipe_bpp(to_intel_crtc(crtc
),
10249 * Determine the real pipe dimensions. Note that stereo modes can
10250 * increase the actual pipe size due to the frame doubling and
10251 * insertion of additional space for blanks between the frame. This
10252 * is stored in the crtc timings. We use the requested mode to do this
10253 * computation to clearly distinguish it from the adjusted mode, which
10254 * can be changed by the connectors in the below retry loop.
10256 drm_crtc_get_hv_timing(&pipe_config
->base
.mode
,
10257 &pipe_config
->pipe_src_w
,
10258 &pipe_config
->pipe_src_h
);
10261 /* Ensure the port clock defaults are reset when retrying. */
10262 pipe_config
->port_clock
= 0;
10263 pipe_config
->pixel_multiplier
= 1;
10265 /* Fill in default crtc timings, allow encoders to overwrite them. */
10266 drm_mode_set_crtcinfo(&pipe_config
->base
.adjusted_mode
,
10267 CRTC_STEREO_DOUBLE
);
10269 /* Pass our mode to the connectors and the CRTC to give them a chance to
10270 * adjust it according to limitations or connector properties, and also
10271 * a chance to reject the mode entirely.
10273 for_each_intel_encoder(dev
, encoder
) {
10275 if (&encoder
->new_crtc
->base
!= crtc
)
10278 if (!(encoder
->compute_config(encoder
, pipe_config
))) {
10279 DRM_DEBUG_KMS("Encoder config failure\n");
10284 /* Set default port clock if not overwritten by the encoder. Needs to be
10285 * done afterwards in case the encoder adjusts the mode. */
10286 if (!pipe_config
->port_clock
)
10287 pipe_config
->port_clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
10288 * pipe_config
->pixel_multiplier
;
10290 ret
= intel_crtc_compute_config(to_intel_crtc(crtc
), pipe_config
);
10292 DRM_DEBUG_KMS("CRTC fixup failed\n");
10296 if (ret
== RETRY
) {
10297 if (WARN(!retry
, "loop in pipe configuration computation\n")) {
10302 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10304 goto encoder_retry
;
10307 pipe_config
->dither
= pipe_config
->pipe_bpp
!= plane_bpp
;
10308 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10309 plane_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
10311 return pipe_config
;
10313 kfree(pipe_config
);
10314 return ERR_PTR(ret
);
10317 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10318 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10320 intel_modeset_affected_pipes(struct drm_crtc
*crtc
, unsigned *modeset_pipes
,
10321 unsigned *prepare_pipes
, unsigned *disable_pipes
)
10323 struct intel_crtc
*intel_crtc
;
10324 struct drm_device
*dev
= crtc
->dev
;
10325 struct intel_encoder
*encoder
;
10326 struct intel_connector
*connector
;
10327 struct drm_crtc
*tmp_crtc
;
10329 *disable_pipes
= *modeset_pipes
= *prepare_pipes
= 0;
10331 /* Check which crtcs have changed outputs connected to them, these need
10332 * to be part of the prepare_pipes mask. We don't (yet) support global
10333 * modeset across multiple crtcs, so modeset_pipes will only have one
10334 * bit set at most. */
10335 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10337 if (connector
->base
.encoder
== &connector
->new_encoder
->base
)
10340 if (connector
->base
.encoder
) {
10341 tmp_crtc
= connector
->base
.encoder
->crtc
;
10343 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
10346 if (connector
->new_encoder
)
10348 1 << connector
->new_encoder
->new_crtc
->pipe
;
10351 for_each_intel_encoder(dev
, encoder
) {
10352 if (encoder
->base
.crtc
== &encoder
->new_crtc
->base
)
10355 if (encoder
->base
.crtc
) {
10356 tmp_crtc
= encoder
->base
.crtc
;
10358 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
10361 if (encoder
->new_crtc
)
10362 *prepare_pipes
|= 1 << encoder
->new_crtc
->pipe
;
10365 /* Check for pipes that will be enabled/disabled ... */
10366 for_each_intel_crtc(dev
, intel_crtc
) {
10367 if (intel_crtc
->base
.enabled
== intel_crtc
->new_enabled
)
10370 if (!intel_crtc
->new_enabled
)
10371 *disable_pipes
|= 1 << intel_crtc
->pipe
;
10373 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
10377 /* set_mode is also used to update properties on life display pipes. */
10378 intel_crtc
= to_intel_crtc(crtc
);
10379 if (intel_crtc
->new_enabled
)
10380 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
10383 * For simplicity do a full modeset on any pipe where the output routing
10384 * changed. We could be more clever, but that would require us to be
10385 * more careful with calling the relevant encoder->mode_set functions.
10387 if (*prepare_pipes
)
10388 *modeset_pipes
= *prepare_pipes
;
10390 /* ... and mask these out. */
10391 *modeset_pipes
&= ~(*disable_pipes
);
10392 *prepare_pipes
&= ~(*disable_pipes
);
10395 * HACK: We don't (yet) fully support global modesets. intel_set_config
10396 * obies this rule, but the modeset restore mode of
10397 * intel_modeset_setup_hw_state does not.
10399 *modeset_pipes
&= 1 << intel_crtc
->pipe
;
10400 *prepare_pipes
&= 1 << intel_crtc
->pipe
;
10402 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10403 *modeset_pipes
, *prepare_pipes
, *disable_pipes
);
10406 static bool intel_crtc_in_use(struct drm_crtc
*crtc
)
10408 struct drm_encoder
*encoder
;
10409 struct drm_device
*dev
= crtc
->dev
;
10411 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
)
10412 if (encoder
->crtc
== crtc
)
10419 intel_modeset_update_state(struct drm_device
*dev
, unsigned prepare_pipes
)
10421 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10422 struct intel_encoder
*intel_encoder
;
10423 struct intel_crtc
*intel_crtc
;
10424 struct drm_connector
*connector
;
10426 intel_shared_dpll_commit(dev_priv
);
10428 for_each_intel_encoder(dev
, intel_encoder
) {
10429 if (!intel_encoder
->base
.crtc
)
10432 intel_crtc
= to_intel_crtc(intel_encoder
->base
.crtc
);
10434 if (prepare_pipes
& (1 << intel_crtc
->pipe
))
10435 intel_encoder
->connectors_active
= false;
10438 intel_modeset_commit_output_state(dev
);
10440 /* Double check state. */
10441 for_each_intel_crtc(dev
, intel_crtc
) {
10442 WARN_ON(intel_crtc
->base
.enabled
!= intel_crtc_in_use(&intel_crtc
->base
));
10443 WARN_ON(intel_crtc
->new_config
&&
10444 intel_crtc
->new_config
!= intel_crtc
->config
);
10445 WARN_ON(intel_crtc
->base
.enabled
!= !!intel_crtc
->new_config
);
10448 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
10449 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
10452 intel_crtc
= to_intel_crtc(connector
->encoder
->crtc
);
10454 if (prepare_pipes
& (1 << intel_crtc
->pipe
)) {
10455 struct drm_property
*dpms_property
=
10456 dev
->mode_config
.dpms_property
;
10458 connector
->dpms
= DRM_MODE_DPMS_ON
;
10459 drm_object_property_set_value(&connector
->base
,
10463 intel_encoder
= to_intel_encoder(connector
->encoder
);
10464 intel_encoder
->connectors_active
= true;
10470 static bool intel_fuzzy_clock_check(int clock1
, int clock2
)
10474 if (clock1
== clock2
)
10477 if (!clock1
|| !clock2
)
10480 diff
= abs(clock1
- clock2
);
10482 if (((((diff
+ clock1
+ clock2
) * 100)) / (clock1
+ clock2
)) < 105)
10488 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10489 list_for_each_entry((intel_crtc), \
10490 &(dev)->mode_config.crtc_list, \
10492 if (mask & (1 <<(intel_crtc)->pipe))
10495 intel_pipe_config_compare(struct drm_device
*dev
,
10496 struct intel_crtc_state
*current_config
,
10497 struct intel_crtc_state
*pipe_config
)
10499 #define PIPE_CONF_CHECK_X(name) \
10500 if (current_config->name != pipe_config->name) { \
10501 DRM_ERROR("mismatch in " #name " " \
10502 "(expected 0x%08x, found 0x%08x)\n", \
10503 current_config->name, \
10504 pipe_config->name); \
10508 #define PIPE_CONF_CHECK_I(name) \
10509 if (current_config->name != pipe_config->name) { \
10510 DRM_ERROR("mismatch in " #name " " \
10511 "(expected %i, found %i)\n", \
10512 current_config->name, \
10513 pipe_config->name); \
10517 /* This is required for BDW+ where there is only one set of registers for
10518 * switching between high and low RR.
10519 * This macro can be used whenever a comparison has to be made between one
10520 * hw state and multiple sw state variables.
10522 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10523 if ((current_config->name != pipe_config->name) && \
10524 (current_config->alt_name != pipe_config->name)) { \
10525 DRM_ERROR("mismatch in " #name " " \
10526 "(expected %i or %i, found %i)\n", \
10527 current_config->name, \
10528 current_config->alt_name, \
10529 pipe_config->name); \
10533 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10534 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10535 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10536 "(expected %i, found %i)\n", \
10537 current_config->name & (mask), \
10538 pipe_config->name & (mask)); \
10542 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10543 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10544 DRM_ERROR("mismatch in " #name " " \
10545 "(expected %i, found %i)\n", \
10546 current_config->name, \
10547 pipe_config->name); \
10551 #define PIPE_CONF_QUIRK(quirk) \
10552 ((current_config->quirks | pipe_config->quirks) & (quirk))
10554 PIPE_CONF_CHECK_I(cpu_transcoder
);
10556 PIPE_CONF_CHECK_I(has_pch_encoder
);
10557 PIPE_CONF_CHECK_I(fdi_lanes
);
10558 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_m
);
10559 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_n
);
10560 PIPE_CONF_CHECK_I(fdi_m_n
.link_m
);
10561 PIPE_CONF_CHECK_I(fdi_m_n
.link_n
);
10562 PIPE_CONF_CHECK_I(fdi_m_n
.tu
);
10564 PIPE_CONF_CHECK_I(has_dp_encoder
);
10566 if (INTEL_INFO(dev
)->gen
< 8) {
10567 PIPE_CONF_CHECK_I(dp_m_n
.gmch_m
);
10568 PIPE_CONF_CHECK_I(dp_m_n
.gmch_n
);
10569 PIPE_CONF_CHECK_I(dp_m_n
.link_m
);
10570 PIPE_CONF_CHECK_I(dp_m_n
.link_n
);
10571 PIPE_CONF_CHECK_I(dp_m_n
.tu
);
10573 if (current_config
->has_drrs
) {
10574 PIPE_CONF_CHECK_I(dp_m2_n2
.gmch_m
);
10575 PIPE_CONF_CHECK_I(dp_m2_n2
.gmch_n
);
10576 PIPE_CONF_CHECK_I(dp_m2_n2
.link_m
);
10577 PIPE_CONF_CHECK_I(dp_m2_n2
.link_n
);
10578 PIPE_CONF_CHECK_I(dp_m2_n2
.tu
);
10581 PIPE_CONF_CHECK_I_ALT(dp_m_n
.gmch_m
, dp_m2_n2
.gmch_m
);
10582 PIPE_CONF_CHECK_I_ALT(dp_m_n
.gmch_n
, dp_m2_n2
.gmch_n
);
10583 PIPE_CONF_CHECK_I_ALT(dp_m_n
.link_m
, dp_m2_n2
.link_m
);
10584 PIPE_CONF_CHECK_I_ALT(dp_m_n
.link_n
, dp_m2_n2
.link_n
);
10585 PIPE_CONF_CHECK_I_ALT(dp_m_n
.tu
, dp_m2_n2
.tu
);
10588 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hdisplay
);
10589 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_htotal
);
10590 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_start
);
10591 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_end
);
10592 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_start
);
10593 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_end
);
10595 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vdisplay
);
10596 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vtotal
);
10597 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_start
);
10598 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_end
);
10599 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_start
);
10600 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_end
);
10602 PIPE_CONF_CHECK_I(pixel_multiplier
);
10603 PIPE_CONF_CHECK_I(has_hdmi_sink
);
10604 if ((INTEL_INFO(dev
)->gen
< 8 && !IS_HASWELL(dev
)) ||
10605 IS_VALLEYVIEW(dev
))
10606 PIPE_CONF_CHECK_I(limited_color_range
);
10607 PIPE_CONF_CHECK_I(has_infoframe
);
10609 PIPE_CONF_CHECK_I(has_audio
);
10611 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
10612 DRM_MODE_FLAG_INTERLACE
);
10614 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
10615 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
10616 DRM_MODE_FLAG_PHSYNC
);
10617 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
10618 DRM_MODE_FLAG_NHSYNC
);
10619 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
10620 DRM_MODE_FLAG_PVSYNC
);
10621 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
10622 DRM_MODE_FLAG_NVSYNC
);
10625 PIPE_CONF_CHECK_I(pipe_src_w
);
10626 PIPE_CONF_CHECK_I(pipe_src_h
);
10629 * FIXME: BIOS likes to set up a cloned config with lvds+external
10630 * screen. Since we don't yet re-compute the pipe config when moving
10631 * just the lvds port away to another pipe the sw tracking won't match.
10633 * Proper atomic modesets with recomputed global state will fix this.
10634 * Until then just don't check gmch state for inherited modes.
10636 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE
)) {
10637 PIPE_CONF_CHECK_I(gmch_pfit
.control
);
10638 /* pfit ratios are autocomputed by the hw on gen4+ */
10639 if (INTEL_INFO(dev
)->gen
< 4)
10640 PIPE_CONF_CHECK_I(gmch_pfit
.pgm_ratios
);
10641 PIPE_CONF_CHECK_I(gmch_pfit
.lvds_border_bits
);
10644 PIPE_CONF_CHECK_I(pch_pfit
.enabled
);
10645 if (current_config
->pch_pfit
.enabled
) {
10646 PIPE_CONF_CHECK_I(pch_pfit
.pos
);
10647 PIPE_CONF_CHECK_I(pch_pfit
.size
);
10650 /* BDW+ don't expose a synchronous way to read the state */
10651 if (IS_HASWELL(dev
))
10652 PIPE_CONF_CHECK_I(ips_enabled
);
10654 PIPE_CONF_CHECK_I(double_wide
);
10656 PIPE_CONF_CHECK_X(ddi_pll_sel
);
10658 PIPE_CONF_CHECK_I(shared_dpll
);
10659 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll
);
10660 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll_md
);
10661 PIPE_CONF_CHECK_X(dpll_hw_state
.fp0
);
10662 PIPE_CONF_CHECK_X(dpll_hw_state
.fp1
);
10663 PIPE_CONF_CHECK_X(dpll_hw_state
.wrpll
);
10664 PIPE_CONF_CHECK_X(dpll_hw_state
.ctrl1
);
10665 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr1
);
10666 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr2
);
10668 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5)
10669 PIPE_CONF_CHECK_I(pipe_bpp
);
10671 PIPE_CONF_CHECK_CLOCK_FUZZY(base
.adjusted_mode
.crtc_clock
);
10672 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock
);
10674 #undef PIPE_CONF_CHECK_X
10675 #undef PIPE_CONF_CHECK_I
10676 #undef PIPE_CONF_CHECK_I_ALT
10677 #undef PIPE_CONF_CHECK_FLAGS
10678 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10679 #undef PIPE_CONF_QUIRK
10684 static void check_wm_state(struct drm_device
*dev
)
10686 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10687 struct skl_ddb_allocation hw_ddb
, *sw_ddb
;
10688 struct intel_crtc
*intel_crtc
;
10691 if (INTEL_INFO(dev
)->gen
< 9)
10694 skl_ddb_get_hw_state(dev_priv
, &hw_ddb
);
10695 sw_ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
10697 for_each_intel_crtc(dev
, intel_crtc
) {
10698 struct skl_ddb_entry
*hw_entry
, *sw_entry
;
10699 const enum pipe pipe
= intel_crtc
->pipe
;
10701 if (!intel_crtc
->active
)
10705 for_each_plane(pipe
, plane
) {
10706 hw_entry
= &hw_ddb
.plane
[pipe
][plane
];
10707 sw_entry
= &sw_ddb
->plane
[pipe
][plane
];
10709 if (skl_ddb_entry_equal(hw_entry
, sw_entry
))
10712 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
10713 "(expected (%u,%u), found (%u,%u))\n",
10714 pipe_name(pipe
), plane
+ 1,
10715 sw_entry
->start
, sw_entry
->end
,
10716 hw_entry
->start
, hw_entry
->end
);
10720 hw_entry
= &hw_ddb
.cursor
[pipe
];
10721 sw_entry
= &sw_ddb
->cursor
[pipe
];
10723 if (skl_ddb_entry_equal(hw_entry
, sw_entry
))
10726 DRM_ERROR("mismatch in DDB state pipe %c cursor "
10727 "(expected (%u,%u), found (%u,%u))\n",
10729 sw_entry
->start
, sw_entry
->end
,
10730 hw_entry
->start
, hw_entry
->end
);
10735 check_connector_state(struct drm_device
*dev
)
10737 struct intel_connector
*connector
;
10739 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10741 /* This also checks the encoder/connector hw state with the
10742 * ->get_hw_state callbacks. */
10743 intel_connector_check_state(connector
);
10745 I915_STATE_WARN(&connector
->new_encoder
->base
!= connector
->base
.encoder
,
10746 "connector's staged encoder doesn't match current encoder\n");
10751 check_encoder_state(struct drm_device
*dev
)
10753 struct intel_encoder
*encoder
;
10754 struct intel_connector
*connector
;
10756 for_each_intel_encoder(dev
, encoder
) {
10757 bool enabled
= false;
10758 bool active
= false;
10759 enum pipe pipe
, tracked_pipe
;
10761 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10762 encoder
->base
.base
.id
,
10763 encoder
->base
.name
);
10765 I915_STATE_WARN(&encoder
->new_crtc
->base
!= encoder
->base
.crtc
,
10766 "encoder's stage crtc doesn't match current crtc\n");
10767 I915_STATE_WARN(encoder
->connectors_active
&& !encoder
->base
.crtc
,
10768 "encoder's active_connectors set, but no crtc\n");
10770 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10772 if (connector
->base
.encoder
!= &encoder
->base
)
10775 if (connector
->base
.dpms
!= DRM_MODE_DPMS_OFF
)
10779 * for MST connectors if we unplug the connector is gone
10780 * away but the encoder is still connected to a crtc
10781 * until a modeset happens in response to the hotplug.
10783 if (!enabled
&& encoder
->base
.encoder_type
== DRM_MODE_ENCODER_DPMST
)
10786 I915_STATE_WARN(!!encoder
->base
.crtc
!= enabled
,
10787 "encoder's enabled state mismatch "
10788 "(expected %i, found %i)\n",
10789 !!encoder
->base
.crtc
, enabled
);
10790 I915_STATE_WARN(active
&& !encoder
->base
.crtc
,
10791 "active encoder with no crtc\n");
10793 I915_STATE_WARN(encoder
->connectors_active
!= active
,
10794 "encoder's computed active state doesn't match tracked active state "
10795 "(expected %i, found %i)\n", active
, encoder
->connectors_active
);
10797 active
= encoder
->get_hw_state(encoder
, &pipe
);
10798 I915_STATE_WARN(active
!= encoder
->connectors_active
,
10799 "encoder's hw state doesn't match sw tracking "
10800 "(expected %i, found %i)\n",
10801 encoder
->connectors_active
, active
);
10803 if (!encoder
->base
.crtc
)
10806 tracked_pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
10807 I915_STATE_WARN(active
&& pipe
!= tracked_pipe
,
10808 "active encoder's pipe doesn't match"
10809 "(expected %i, found %i)\n",
10810 tracked_pipe
, pipe
);
10816 check_crtc_state(struct drm_device
*dev
)
10818 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10819 struct intel_crtc
*crtc
;
10820 struct intel_encoder
*encoder
;
10821 struct intel_crtc_state pipe_config
;
10823 for_each_intel_crtc(dev
, crtc
) {
10824 bool enabled
= false;
10825 bool active
= false;
10827 memset(&pipe_config
, 0, sizeof(pipe_config
));
10829 DRM_DEBUG_KMS("[CRTC:%d]\n",
10830 crtc
->base
.base
.id
);
10832 I915_STATE_WARN(crtc
->active
&& !crtc
->base
.enabled
,
10833 "active crtc, but not enabled in sw tracking\n");
10835 for_each_intel_encoder(dev
, encoder
) {
10836 if (encoder
->base
.crtc
!= &crtc
->base
)
10839 if (encoder
->connectors_active
)
10843 I915_STATE_WARN(active
!= crtc
->active
,
10844 "crtc's computed active state doesn't match tracked active state "
10845 "(expected %i, found %i)\n", active
, crtc
->active
);
10846 I915_STATE_WARN(enabled
!= crtc
->base
.enabled
,
10847 "crtc's computed enabled state doesn't match tracked enabled state "
10848 "(expected %i, found %i)\n", enabled
, crtc
->base
.enabled
);
10850 active
= dev_priv
->display
.get_pipe_config(crtc
,
10853 /* hw state is inconsistent with the pipe quirk */
10854 if ((crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
10855 (crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
10856 active
= crtc
->active
;
10858 for_each_intel_encoder(dev
, encoder
) {
10860 if (encoder
->base
.crtc
!= &crtc
->base
)
10862 if (encoder
->get_hw_state(encoder
, &pipe
))
10863 encoder
->get_config(encoder
, &pipe_config
);
10866 I915_STATE_WARN(crtc
->active
!= active
,
10867 "crtc active state doesn't match with hw state "
10868 "(expected %i, found %i)\n", crtc
->active
, active
);
10871 !intel_pipe_config_compare(dev
, crtc
->config
, &pipe_config
)) {
10872 I915_STATE_WARN(1, "pipe state doesn't match!\n");
10873 intel_dump_pipe_config(crtc
, &pipe_config
,
10875 intel_dump_pipe_config(crtc
, crtc
->config
,
10882 check_shared_dpll_state(struct drm_device
*dev
)
10884 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10885 struct intel_crtc
*crtc
;
10886 struct intel_dpll_hw_state dpll_hw_state
;
10889 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
10890 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
10891 int enabled_crtcs
= 0, active_crtcs
= 0;
10894 memset(&dpll_hw_state
, 0, sizeof(dpll_hw_state
));
10896 DRM_DEBUG_KMS("%s\n", pll
->name
);
10898 active
= pll
->get_hw_state(dev_priv
, pll
, &dpll_hw_state
);
10900 I915_STATE_WARN(pll
->active
> hweight32(pll
->config
.crtc_mask
),
10901 "more active pll users than references: %i vs %i\n",
10902 pll
->active
, hweight32(pll
->config
.crtc_mask
));
10903 I915_STATE_WARN(pll
->active
&& !pll
->on
,
10904 "pll in active use but not on in sw tracking\n");
10905 I915_STATE_WARN(pll
->on
&& !pll
->active
,
10906 "pll in on but not on in use in sw tracking\n");
10907 I915_STATE_WARN(pll
->on
!= active
,
10908 "pll on state mismatch (expected %i, found %i)\n",
10911 for_each_intel_crtc(dev
, crtc
) {
10912 if (crtc
->base
.enabled
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
10914 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
10917 I915_STATE_WARN(pll
->active
!= active_crtcs
,
10918 "pll active crtcs mismatch (expected %i, found %i)\n",
10919 pll
->active
, active_crtcs
);
10920 I915_STATE_WARN(hweight32(pll
->config
.crtc_mask
) != enabled_crtcs
,
10921 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10922 hweight32(pll
->config
.crtc_mask
), enabled_crtcs
);
10924 I915_STATE_WARN(pll
->on
&& memcmp(&pll
->config
.hw_state
, &dpll_hw_state
,
10925 sizeof(dpll_hw_state
)),
10926 "pll hw state mismatch\n");
10931 intel_modeset_check_state(struct drm_device
*dev
)
10933 check_wm_state(dev
);
10934 check_connector_state(dev
);
10935 check_encoder_state(dev
);
10936 check_crtc_state(dev
);
10937 check_shared_dpll_state(dev
);
10940 void ironlake_check_encoder_dotclock(const struct intel_crtc_state
*pipe_config
,
10944 * FDI already provided one idea for the dotclock.
10945 * Yell if the encoder disagrees.
10947 WARN(!intel_fuzzy_clock_check(pipe_config
->base
.adjusted_mode
.crtc_clock
, dotclock
),
10948 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10949 pipe_config
->base
.adjusted_mode
.crtc_clock
, dotclock
);
10952 static void update_scanline_offset(struct intel_crtc
*crtc
)
10954 struct drm_device
*dev
= crtc
->base
.dev
;
10957 * The scanline counter increments at the leading edge of hsync.
10959 * On most platforms it starts counting from vtotal-1 on the
10960 * first active line. That means the scanline counter value is
10961 * always one less than what we would expect. Ie. just after
10962 * start of vblank, which also occurs at start of hsync (on the
10963 * last active line), the scanline counter will read vblank_start-1.
10965 * On gen2 the scanline counter starts counting from 1 instead
10966 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10967 * to keep the value positive), instead of adding one.
10969 * On HSW+ the behaviour of the scanline counter depends on the output
10970 * type. For DP ports it behaves like most other platforms, but on HDMI
10971 * there's an extra 1 line difference. So we need to add two instead of
10972 * one to the value.
10974 if (IS_GEN2(dev
)) {
10975 const struct drm_display_mode
*mode
= &crtc
->config
->base
.adjusted_mode
;
10978 vtotal
= mode
->crtc_vtotal
;
10979 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
10982 crtc
->scanline_offset
= vtotal
- 1;
10983 } else if (HAS_DDI(dev
) &&
10984 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
)) {
10985 crtc
->scanline_offset
= 2;
10987 crtc
->scanline_offset
= 1;
10990 static struct intel_crtc_state
*
10991 intel_modeset_compute_config(struct drm_crtc
*crtc
,
10992 struct drm_display_mode
*mode
,
10993 struct drm_framebuffer
*fb
,
10994 unsigned *modeset_pipes
,
10995 unsigned *prepare_pipes
,
10996 unsigned *disable_pipes
)
10998 struct intel_crtc_state
*pipe_config
= NULL
;
11000 intel_modeset_affected_pipes(crtc
, modeset_pipes
,
11001 prepare_pipes
, disable_pipes
);
11003 if ((*modeset_pipes
) == 0)
11007 * Note this needs changes when we start tracking multiple modes
11008 * and crtcs. At that point we'll need to compute the whole config
11009 * (i.e. one pipe_config for each crtc) rather than just the one
11012 pipe_config
= intel_modeset_pipe_config(crtc
, fb
, mode
);
11013 if (IS_ERR(pipe_config
)) {
11016 intel_dump_pipe_config(to_intel_crtc(crtc
), pipe_config
,
11020 return pipe_config
;
11023 static int __intel_set_mode(struct drm_crtc
*crtc
,
11024 struct drm_display_mode
*mode
,
11025 int x
, int y
, struct drm_framebuffer
*fb
,
11026 struct intel_crtc_state
*pipe_config
,
11027 unsigned modeset_pipes
,
11028 unsigned prepare_pipes
,
11029 unsigned disable_pipes
)
11031 struct drm_device
*dev
= crtc
->dev
;
11032 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11033 struct drm_display_mode
*saved_mode
;
11034 struct intel_crtc
*intel_crtc
;
11037 saved_mode
= kmalloc(sizeof(*saved_mode
), GFP_KERNEL
);
11041 *saved_mode
= crtc
->mode
;
11044 to_intel_crtc(crtc
)->new_config
= pipe_config
;
11047 * See if the config requires any additional preparation, e.g.
11048 * to adjust global state with pipes off. We need to do this
11049 * here so we can get the modeset_pipe updated config for the new
11050 * mode set on this crtc. For other crtcs we need to use the
11051 * adjusted_mode bits in the crtc directly.
11053 if (IS_VALLEYVIEW(dev
)) {
11054 valleyview_modeset_global_pipes(dev
, &prepare_pipes
);
11056 /* may have added more to prepare_pipes than we should */
11057 prepare_pipes
&= ~disable_pipes
;
11060 if (dev_priv
->display
.crtc_compute_clock
) {
11061 unsigned clear_pipes
= modeset_pipes
| disable_pipes
;
11063 ret
= intel_shared_dpll_start_config(dev_priv
, clear_pipes
);
11067 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
11068 struct intel_crtc_state
*state
= intel_crtc
->new_config
;
11069 ret
= dev_priv
->display
.crtc_compute_clock(intel_crtc
,
11072 intel_shared_dpll_abort_config(dev_priv
);
11078 for_each_intel_crtc_masked(dev
, disable_pipes
, intel_crtc
)
11079 intel_crtc_disable(&intel_crtc
->base
);
11081 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
11082 if (intel_crtc
->base
.enabled
)
11083 dev_priv
->display
.crtc_disable(&intel_crtc
->base
);
11086 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11087 * to set it here already despite that we pass it down the callchain.
11089 * Note we'll need to fix this up when we start tracking multiple
11090 * pipes; here we assume a single modeset_pipe and only track the
11091 * single crtc and mode.
11093 if (modeset_pipes
) {
11094 crtc
->mode
= *mode
;
11095 /* mode_set/enable/disable functions rely on a correct pipe
11097 intel_crtc_set_state(to_intel_crtc(crtc
), pipe_config
);
11100 * Calculate and store various constants which
11101 * are later needed by vblank and swap-completion
11102 * timestamping. They are derived from true hwmode.
11104 drm_calc_timestamping_constants(crtc
,
11105 &pipe_config
->base
.adjusted_mode
);
11108 /* Only after disabling all output pipelines that will be changed can we
11109 * update the the output configuration. */
11110 intel_modeset_update_state(dev
, prepare_pipes
);
11112 modeset_update_crtc_power_domains(dev
);
11114 /* Set up the DPLL and any encoders state that needs to adjust or depend
11117 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
11118 struct drm_plane
*primary
= intel_crtc
->base
.primary
;
11119 int vdisplay
, hdisplay
;
11121 drm_crtc_get_hv_timing(mode
, &hdisplay
, &vdisplay
);
11122 ret
= primary
->funcs
->update_plane(primary
, &intel_crtc
->base
,
11124 hdisplay
, vdisplay
,
11126 hdisplay
<< 16, vdisplay
<< 16);
11129 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11130 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
11131 update_scanline_offset(intel_crtc
);
11133 dev_priv
->display
.crtc_enable(&intel_crtc
->base
);
11136 /* FIXME: add subpixel order */
11138 if (ret
&& crtc
->enabled
)
11139 crtc
->mode
= *saved_mode
;
11145 static int intel_set_mode_pipes(struct drm_crtc
*crtc
,
11146 struct drm_display_mode
*mode
,
11147 int x
, int y
, struct drm_framebuffer
*fb
,
11148 struct intel_crtc_state
*pipe_config
,
11149 unsigned modeset_pipes
,
11150 unsigned prepare_pipes
,
11151 unsigned disable_pipes
)
11155 ret
= __intel_set_mode(crtc
, mode
, x
, y
, fb
, pipe_config
, modeset_pipes
,
11156 prepare_pipes
, disable_pipes
);
11159 intel_modeset_check_state(crtc
->dev
);
11164 static int intel_set_mode(struct drm_crtc
*crtc
,
11165 struct drm_display_mode
*mode
,
11166 int x
, int y
, struct drm_framebuffer
*fb
)
11168 struct intel_crtc_state
*pipe_config
;
11169 unsigned modeset_pipes
, prepare_pipes
, disable_pipes
;
11171 pipe_config
= intel_modeset_compute_config(crtc
, mode
, fb
,
11176 if (IS_ERR(pipe_config
))
11177 return PTR_ERR(pipe_config
);
11179 return intel_set_mode_pipes(crtc
, mode
, x
, y
, fb
, pipe_config
,
11180 modeset_pipes
, prepare_pipes
,
11184 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
11186 intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
, crtc
->primary
->fb
);
11189 #undef for_each_intel_crtc_masked
11191 static void intel_set_config_free(struct intel_set_config
*config
)
11196 kfree(config
->save_connector_encoders
);
11197 kfree(config
->save_encoder_crtcs
);
11198 kfree(config
->save_crtc_enabled
);
11202 static int intel_set_config_save_state(struct drm_device
*dev
,
11203 struct intel_set_config
*config
)
11205 struct drm_crtc
*crtc
;
11206 struct drm_encoder
*encoder
;
11207 struct drm_connector
*connector
;
11210 config
->save_crtc_enabled
=
11211 kcalloc(dev
->mode_config
.num_crtc
,
11212 sizeof(bool), GFP_KERNEL
);
11213 if (!config
->save_crtc_enabled
)
11216 config
->save_encoder_crtcs
=
11217 kcalloc(dev
->mode_config
.num_encoder
,
11218 sizeof(struct drm_crtc
*), GFP_KERNEL
);
11219 if (!config
->save_encoder_crtcs
)
11222 config
->save_connector_encoders
=
11223 kcalloc(dev
->mode_config
.num_connector
,
11224 sizeof(struct drm_encoder
*), GFP_KERNEL
);
11225 if (!config
->save_connector_encoders
)
11228 /* Copy data. Note that driver private data is not affected.
11229 * Should anything bad happen only the expected state is
11230 * restored, not the drivers personal bookkeeping.
11233 for_each_crtc(dev
, crtc
) {
11234 config
->save_crtc_enabled
[count
++] = crtc
->enabled
;
11238 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
11239 config
->save_encoder_crtcs
[count
++] = encoder
->crtc
;
11243 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
11244 config
->save_connector_encoders
[count
++] = connector
->encoder
;
11250 static void intel_set_config_restore_state(struct drm_device
*dev
,
11251 struct intel_set_config
*config
)
11253 struct intel_crtc
*crtc
;
11254 struct intel_encoder
*encoder
;
11255 struct intel_connector
*connector
;
11259 for_each_intel_crtc(dev
, crtc
) {
11260 crtc
->new_enabled
= config
->save_crtc_enabled
[count
++];
11262 if (crtc
->new_enabled
)
11263 crtc
->new_config
= crtc
->config
;
11265 crtc
->new_config
= NULL
;
11269 for_each_intel_encoder(dev
, encoder
) {
11270 encoder
->new_crtc
=
11271 to_intel_crtc(config
->save_encoder_crtcs
[count
++]);
11275 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
11276 connector
->new_encoder
=
11277 to_intel_encoder(config
->save_connector_encoders
[count
++]);
11282 is_crtc_connector_off(struct drm_mode_set
*set
)
11286 if (set
->num_connectors
== 0)
11289 if (WARN_ON(set
->connectors
== NULL
))
11292 for (i
= 0; i
< set
->num_connectors
; i
++)
11293 if (set
->connectors
[i
]->encoder
&&
11294 set
->connectors
[i
]->encoder
->crtc
== set
->crtc
&&
11295 set
->connectors
[i
]->dpms
!= DRM_MODE_DPMS_ON
)
11302 intel_set_config_compute_mode_changes(struct drm_mode_set
*set
,
11303 struct intel_set_config
*config
)
11306 /* We should be able to check here if the fb has the same properties
11307 * and then just flip_or_move it */
11308 if (is_crtc_connector_off(set
)) {
11309 config
->mode_changed
= true;
11310 } else if (set
->crtc
->primary
->fb
!= set
->fb
) {
11312 * If we have no fb, we can only flip as long as the crtc is
11313 * active, otherwise we need a full mode set. The crtc may
11314 * be active if we've only disabled the primary plane, or
11315 * in fastboot situations.
11317 if (set
->crtc
->primary
->fb
== NULL
) {
11318 struct intel_crtc
*intel_crtc
=
11319 to_intel_crtc(set
->crtc
);
11321 if (intel_crtc
->active
) {
11322 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11323 config
->fb_changed
= true;
11325 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11326 config
->mode_changed
= true;
11328 } else if (set
->fb
== NULL
) {
11329 config
->mode_changed
= true;
11330 } else if (set
->fb
->pixel_format
!=
11331 set
->crtc
->primary
->fb
->pixel_format
) {
11332 config
->mode_changed
= true;
11334 config
->fb_changed
= true;
11338 if (set
->fb
&& (set
->x
!= set
->crtc
->x
|| set
->y
!= set
->crtc
->y
))
11339 config
->fb_changed
= true;
11341 if (set
->mode
&& !drm_mode_equal(set
->mode
, &set
->crtc
->mode
)) {
11342 DRM_DEBUG_KMS("modes are different, full mode set\n");
11343 drm_mode_debug_printmodeline(&set
->crtc
->mode
);
11344 drm_mode_debug_printmodeline(set
->mode
);
11345 config
->mode_changed
= true;
11348 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11349 set
->crtc
->base
.id
, config
->mode_changed
, config
->fb_changed
);
11353 intel_modeset_stage_output_state(struct drm_device
*dev
,
11354 struct drm_mode_set
*set
,
11355 struct intel_set_config
*config
)
11357 struct intel_connector
*connector
;
11358 struct intel_encoder
*encoder
;
11359 struct intel_crtc
*crtc
;
11362 /* The upper layers ensure that we either disable a crtc or have a list
11363 * of connectors. For paranoia, double-check this. */
11364 WARN_ON(!set
->fb
&& (set
->num_connectors
!= 0));
11365 WARN_ON(set
->fb
&& (set
->num_connectors
== 0));
11367 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
11369 /* Otherwise traverse passed in connector list and get encoders
11371 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
11372 if (set
->connectors
[ro
] == &connector
->base
) {
11373 connector
->new_encoder
= intel_find_encoder(connector
, to_intel_crtc(set
->crtc
)->pipe
);
11378 /* If we disable the crtc, disable all its connectors. Also, if
11379 * the connector is on the changing crtc but not on the new
11380 * connector list, disable it. */
11381 if ((!set
->fb
|| ro
== set
->num_connectors
) &&
11382 connector
->base
.encoder
&&
11383 connector
->base
.encoder
->crtc
== set
->crtc
) {
11384 connector
->new_encoder
= NULL
;
11386 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11387 connector
->base
.base
.id
,
11388 connector
->base
.name
);
11392 if (&connector
->new_encoder
->base
!= connector
->base
.encoder
) {
11393 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11394 config
->mode_changed
= true;
11397 /* connector->new_encoder is now updated for all connectors. */
11399 /* Update crtc of enabled connectors. */
11400 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
11402 struct drm_crtc
*new_crtc
;
11404 if (!connector
->new_encoder
)
11407 new_crtc
= connector
->new_encoder
->base
.crtc
;
11409 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
11410 if (set
->connectors
[ro
] == &connector
->base
)
11411 new_crtc
= set
->crtc
;
11414 /* Make sure the new CRTC will work with the encoder */
11415 if (!drm_encoder_crtc_ok(&connector
->new_encoder
->base
,
11419 connector
->new_encoder
->new_crtc
= to_intel_crtc(new_crtc
);
11421 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11422 connector
->base
.base
.id
,
11423 connector
->base
.name
,
11424 new_crtc
->base
.id
);
11427 /* Check for any encoders that needs to be disabled. */
11428 for_each_intel_encoder(dev
, encoder
) {
11429 int num_connectors
= 0;
11430 list_for_each_entry(connector
,
11431 &dev
->mode_config
.connector_list
,
11433 if (connector
->new_encoder
== encoder
) {
11434 WARN_ON(!connector
->new_encoder
->new_crtc
);
11439 if (num_connectors
== 0)
11440 encoder
->new_crtc
= NULL
;
11441 else if (num_connectors
> 1)
11444 /* Only now check for crtc changes so we don't miss encoders
11445 * that will be disabled. */
11446 if (&encoder
->new_crtc
->base
!= encoder
->base
.crtc
) {
11447 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11448 config
->mode_changed
= true;
11451 /* Now we've also updated encoder->new_crtc for all encoders. */
11452 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
11454 if (connector
->new_encoder
)
11455 if (connector
->new_encoder
!= connector
->encoder
)
11456 connector
->encoder
= connector
->new_encoder
;
11458 for_each_intel_crtc(dev
, crtc
) {
11459 crtc
->new_enabled
= false;
11461 for_each_intel_encoder(dev
, encoder
) {
11462 if (encoder
->new_crtc
== crtc
) {
11463 crtc
->new_enabled
= true;
11468 if (crtc
->new_enabled
!= crtc
->base
.enabled
) {
11469 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11470 crtc
->new_enabled
? "en" : "dis");
11471 config
->mode_changed
= true;
11474 if (crtc
->new_enabled
)
11475 crtc
->new_config
= crtc
->config
;
11477 crtc
->new_config
= NULL
;
11483 static void disable_crtc_nofb(struct intel_crtc
*crtc
)
11485 struct drm_device
*dev
= crtc
->base
.dev
;
11486 struct intel_encoder
*encoder
;
11487 struct intel_connector
*connector
;
11489 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11490 pipe_name(crtc
->pipe
));
11492 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
11493 if (connector
->new_encoder
&&
11494 connector
->new_encoder
->new_crtc
== crtc
)
11495 connector
->new_encoder
= NULL
;
11498 for_each_intel_encoder(dev
, encoder
) {
11499 if (encoder
->new_crtc
== crtc
)
11500 encoder
->new_crtc
= NULL
;
11503 crtc
->new_enabled
= false;
11504 crtc
->new_config
= NULL
;
11507 static int intel_crtc_set_config(struct drm_mode_set
*set
)
11509 struct drm_device
*dev
;
11510 struct drm_mode_set save_set
;
11511 struct intel_set_config
*config
;
11512 struct intel_crtc_state
*pipe_config
;
11513 unsigned modeset_pipes
, prepare_pipes
, disable_pipes
;
11517 BUG_ON(!set
->crtc
);
11518 BUG_ON(!set
->crtc
->helper_private
);
11520 /* Enforce sane interface api - has been abused by the fb helper. */
11521 BUG_ON(!set
->mode
&& set
->fb
);
11522 BUG_ON(set
->fb
&& set
->num_connectors
== 0);
11525 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11526 set
->crtc
->base
.id
, set
->fb
->base
.id
,
11527 (int)set
->num_connectors
, set
->x
, set
->y
);
11529 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set
->crtc
->base
.id
);
11532 dev
= set
->crtc
->dev
;
11535 config
= kzalloc(sizeof(*config
), GFP_KERNEL
);
11539 ret
= intel_set_config_save_state(dev
, config
);
11543 save_set
.crtc
= set
->crtc
;
11544 save_set
.mode
= &set
->crtc
->mode
;
11545 save_set
.x
= set
->crtc
->x
;
11546 save_set
.y
= set
->crtc
->y
;
11547 save_set
.fb
= set
->crtc
->primary
->fb
;
11549 /* Compute whether we need a full modeset, only an fb base update or no
11550 * change at all. In the future we might also check whether only the
11551 * mode changed, e.g. for LVDS where we only change the panel fitter in
11553 intel_set_config_compute_mode_changes(set
, config
);
11555 ret
= intel_modeset_stage_output_state(dev
, set
, config
);
11559 pipe_config
= intel_modeset_compute_config(set
->crtc
, set
->mode
,
11564 if (IS_ERR(pipe_config
)) {
11565 ret
= PTR_ERR(pipe_config
);
11567 } else if (pipe_config
) {
11568 if (pipe_config
->has_audio
!=
11569 to_intel_crtc(set
->crtc
)->config
->has_audio
)
11570 config
->mode_changed
= true;
11573 * Note we have an issue here with infoframes: current code
11574 * only updates them on the full mode set path per hw
11575 * requirements. So here we should be checking for any
11576 * required changes and forcing a mode set.
11580 /* set_mode will free it in the mode_changed case */
11581 if (!config
->mode_changed
)
11582 kfree(pipe_config
);
11584 intel_update_pipe_size(to_intel_crtc(set
->crtc
));
11586 if (config
->mode_changed
) {
11587 ret
= intel_set_mode_pipes(set
->crtc
, set
->mode
,
11588 set
->x
, set
->y
, set
->fb
, pipe_config
,
11589 modeset_pipes
, prepare_pipes
,
11591 } else if (config
->fb_changed
) {
11592 struct intel_crtc
*intel_crtc
= to_intel_crtc(set
->crtc
);
11593 struct drm_plane
*primary
= set
->crtc
->primary
;
11594 int vdisplay
, hdisplay
;
11596 drm_crtc_get_hv_timing(set
->mode
, &hdisplay
, &vdisplay
);
11597 ret
= primary
->funcs
->update_plane(primary
, set
->crtc
, set
->fb
,
11598 0, 0, hdisplay
, vdisplay
,
11599 set
->x
<< 16, set
->y
<< 16,
11600 hdisplay
<< 16, vdisplay
<< 16);
11603 * We need to make sure the primary plane is re-enabled if it
11604 * has previously been turned off.
11606 if (!intel_crtc
->primary_enabled
&& ret
== 0) {
11607 WARN_ON(!intel_crtc
->active
);
11608 intel_enable_primary_hw_plane(set
->crtc
->primary
, set
->crtc
);
11612 * In the fastboot case this may be our only check of the
11613 * state after boot. It would be better to only do it on
11614 * the first update, but we don't have a nice way of doing that
11615 * (and really, set_config isn't used much for high freq page
11616 * flipping, so increasing its cost here shouldn't be a big
11619 if (i915
.fastboot
&& ret
== 0)
11620 intel_modeset_check_state(set
->crtc
->dev
);
11624 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11625 set
->crtc
->base
.id
, ret
);
11627 intel_set_config_restore_state(dev
, config
);
11630 * HACK: if the pipe was on, but we didn't have a framebuffer,
11631 * force the pipe off to avoid oopsing in the modeset code
11632 * due to fb==NULL. This should only happen during boot since
11633 * we don't yet reconstruct the FB from the hardware state.
11635 if (to_intel_crtc(save_set
.crtc
)->new_enabled
&& !save_set
.fb
)
11636 disable_crtc_nofb(to_intel_crtc(save_set
.crtc
));
11638 /* Try to restore the config */
11639 if (config
->mode_changed
&&
11640 intel_set_mode(save_set
.crtc
, save_set
.mode
,
11641 save_set
.x
, save_set
.y
, save_set
.fb
))
11642 DRM_ERROR("failed to restore config after modeset failure\n");
11646 intel_set_config_free(config
);
11650 static const struct drm_crtc_funcs intel_crtc_funcs
= {
11651 .gamma_set
= intel_crtc_gamma_set
,
11652 .set_config
= intel_crtc_set_config
,
11653 .destroy
= intel_crtc_destroy
,
11654 .page_flip
= intel_crtc_page_flip
,
11657 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private
*dev_priv
,
11658 struct intel_shared_dpll
*pll
,
11659 struct intel_dpll_hw_state
*hw_state
)
11663 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
11666 val
= I915_READ(PCH_DPLL(pll
->id
));
11667 hw_state
->dpll
= val
;
11668 hw_state
->fp0
= I915_READ(PCH_FP0(pll
->id
));
11669 hw_state
->fp1
= I915_READ(PCH_FP1(pll
->id
));
11671 return val
& DPLL_VCO_ENABLE
;
11674 static void ibx_pch_dpll_mode_set(struct drm_i915_private
*dev_priv
,
11675 struct intel_shared_dpll
*pll
)
11677 I915_WRITE(PCH_FP0(pll
->id
), pll
->config
.hw_state
.fp0
);
11678 I915_WRITE(PCH_FP1(pll
->id
), pll
->config
.hw_state
.fp1
);
11681 static void ibx_pch_dpll_enable(struct drm_i915_private
*dev_priv
,
11682 struct intel_shared_dpll
*pll
)
11684 /* PCH refclock must be enabled first */
11685 ibx_assert_pch_refclk_enabled(dev_priv
);
11687 I915_WRITE(PCH_DPLL(pll
->id
), pll
->config
.hw_state
.dpll
);
11689 /* Wait for the clocks to stabilize. */
11690 POSTING_READ(PCH_DPLL(pll
->id
));
11693 /* The pixel multiplier can only be updated once the
11694 * DPLL is enabled and the clocks are stable.
11696 * So write it again.
11698 I915_WRITE(PCH_DPLL(pll
->id
), pll
->config
.hw_state
.dpll
);
11699 POSTING_READ(PCH_DPLL(pll
->id
));
11703 static void ibx_pch_dpll_disable(struct drm_i915_private
*dev_priv
,
11704 struct intel_shared_dpll
*pll
)
11706 struct drm_device
*dev
= dev_priv
->dev
;
11707 struct intel_crtc
*crtc
;
11709 /* Make sure no transcoder isn't still depending on us. */
11710 for_each_intel_crtc(dev
, crtc
) {
11711 if (intel_crtc_to_shared_dpll(crtc
) == pll
)
11712 assert_pch_transcoder_disabled(dev_priv
, crtc
->pipe
);
11715 I915_WRITE(PCH_DPLL(pll
->id
), 0);
11716 POSTING_READ(PCH_DPLL(pll
->id
));
11720 static char *ibx_pch_dpll_names
[] = {
11725 static void ibx_pch_dpll_init(struct drm_device
*dev
)
11727 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11730 dev_priv
->num_shared_dpll
= 2;
11732 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
11733 dev_priv
->shared_dplls
[i
].id
= i
;
11734 dev_priv
->shared_dplls
[i
].name
= ibx_pch_dpll_names
[i
];
11735 dev_priv
->shared_dplls
[i
].mode_set
= ibx_pch_dpll_mode_set
;
11736 dev_priv
->shared_dplls
[i
].enable
= ibx_pch_dpll_enable
;
11737 dev_priv
->shared_dplls
[i
].disable
= ibx_pch_dpll_disable
;
11738 dev_priv
->shared_dplls
[i
].get_hw_state
=
11739 ibx_pch_dpll_get_hw_state
;
11743 static void intel_shared_dpll_init(struct drm_device
*dev
)
11745 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11748 intel_ddi_pll_init(dev
);
11749 else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
11750 ibx_pch_dpll_init(dev
);
11752 dev_priv
->num_shared_dpll
= 0;
11754 BUG_ON(dev_priv
->num_shared_dpll
> I915_NUM_PLLS
);
11758 * intel_prepare_plane_fb - Prepare fb for usage on plane
11759 * @plane: drm plane to prepare for
11760 * @fb: framebuffer to prepare for presentation
11762 * Prepares a framebuffer for usage on a display plane. Generally this
11763 * involves pinning the underlying object and updating the frontbuffer tracking
11764 * bits. Some older platforms need special physical address handling for
11767 * Returns 0 on success, negative error code on failure.
11770 intel_prepare_plane_fb(struct drm_plane
*plane
,
11771 struct drm_framebuffer
*fb
)
11773 struct drm_device
*dev
= plane
->dev
;
11774 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
11775 enum pipe pipe
= intel_plane
->pipe
;
11776 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
11777 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(plane
->fb
);
11778 unsigned frontbuffer_bits
= 0;
11784 switch (plane
->type
) {
11785 case DRM_PLANE_TYPE_PRIMARY
:
11786 frontbuffer_bits
= INTEL_FRONTBUFFER_PRIMARY(pipe
);
11788 case DRM_PLANE_TYPE_CURSOR
:
11789 frontbuffer_bits
= INTEL_FRONTBUFFER_CURSOR(pipe
);
11791 case DRM_PLANE_TYPE_OVERLAY
:
11792 frontbuffer_bits
= INTEL_FRONTBUFFER_SPRITE(pipe
);
11796 mutex_lock(&dev
->struct_mutex
);
11798 if (plane
->type
== DRM_PLANE_TYPE_CURSOR
&&
11799 INTEL_INFO(dev
)->cursor_needs_physical
) {
11800 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
11801 ret
= i915_gem_object_attach_phys(obj
, align
);
11803 DRM_DEBUG_KMS("failed to attach phys object\n");
11805 ret
= intel_pin_and_fence_fb_obj(plane
, fb
, NULL
);
11809 i915_gem_track_fb(old_obj
, obj
, frontbuffer_bits
);
11811 mutex_unlock(&dev
->struct_mutex
);
11817 * intel_cleanup_plane_fb - Cleans up an fb after plane use
11818 * @plane: drm plane to clean up for
11819 * @fb: old framebuffer that was on plane
11821 * Cleans up a framebuffer that has just been removed from a plane.
11824 intel_cleanup_plane_fb(struct drm_plane
*plane
,
11825 struct drm_framebuffer
*fb
)
11827 struct drm_device
*dev
= plane
->dev
;
11828 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
11833 if (plane
->type
!= DRM_PLANE_TYPE_CURSOR
||
11834 !INTEL_INFO(dev
)->cursor_needs_physical
) {
11835 mutex_lock(&dev
->struct_mutex
);
11836 intel_unpin_fb_obj(obj
);
11837 mutex_unlock(&dev
->struct_mutex
);
11842 intel_check_primary_plane(struct drm_plane
*plane
,
11843 struct intel_plane_state
*state
)
11845 struct drm_device
*dev
= plane
->dev
;
11846 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11847 struct drm_crtc
*crtc
= state
->base
.crtc
;
11848 struct intel_crtc
*intel_crtc
;
11849 struct drm_framebuffer
*fb
= state
->base
.fb
;
11850 struct drm_rect
*dest
= &state
->dst
;
11851 struct drm_rect
*src
= &state
->src
;
11852 const struct drm_rect
*clip
= &state
->clip
;
11855 crtc
= crtc
? crtc
: plane
->crtc
;
11856 intel_crtc
= to_intel_crtc(crtc
);
11858 ret
= drm_plane_helper_check_update(plane
, crtc
, fb
,
11860 DRM_PLANE_HELPER_NO_SCALING
,
11861 DRM_PLANE_HELPER_NO_SCALING
,
11862 false, true, &state
->visible
);
11866 if (intel_crtc
->active
) {
11867 intel_crtc
->atomic
.wait_for_flips
= true;
11870 * FBC does not work on some platforms for rotated
11871 * planes, so disable it when rotation is not 0 and
11872 * update it when rotation is set back to 0.
11874 * FIXME: This is redundant with the fbc update done in
11875 * the primary plane enable function except that that
11876 * one is done too late. We eventually need to unify
11879 if (intel_crtc
->primary_enabled
&&
11880 INTEL_INFO(dev
)->gen
<= 4 && !IS_G4X(dev
) &&
11881 dev_priv
->fbc
.plane
== intel_crtc
->plane
&&
11882 state
->base
.rotation
!= BIT(DRM_ROTATE_0
)) {
11883 intel_crtc
->atomic
.disable_fbc
= true;
11886 if (state
->visible
) {
11888 * BDW signals flip done immediately if the plane
11889 * is disabled, even if the plane enable is already
11890 * armed to occur at the next vblank :(
11892 if (IS_BROADWELL(dev
) && !intel_crtc
->primary_enabled
)
11893 intel_crtc
->atomic
.wait_vblank
= true;
11896 intel_crtc
->atomic
.fb_bits
|=
11897 INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
);
11899 intel_crtc
->atomic
.update_fbc
= true;
11906 intel_commit_primary_plane(struct drm_plane
*plane
,
11907 struct intel_plane_state
*state
)
11909 struct drm_crtc
*crtc
= state
->base
.crtc
;
11910 struct drm_framebuffer
*fb
= state
->base
.fb
;
11911 struct drm_device
*dev
= plane
->dev
;
11912 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11913 struct intel_crtc
*intel_crtc
;
11914 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
11915 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
11916 struct drm_rect
*src
= &state
->src
;
11918 crtc
= crtc
? crtc
: plane
->crtc
;
11919 intel_crtc
= to_intel_crtc(crtc
);
11922 crtc
->x
= src
->x1
>> 16;
11923 crtc
->y
= src
->y1
>> 16;
11925 intel_plane
->obj
= obj
;
11927 if (intel_crtc
->active
) {
11928 if (state
->visible
) {
11929 /* FIXME: kill this fastboot hack */
11930 intel_update_pipe_size(intel_crtc
);
11932 intel_crtc
->primary_enabled
= true;
11934 dev_priv
->display
.update_primary_plane(crtc
, plane
->fb
,
11938 * If clipping results in a non-visible primary plane,
11939 * we'll disable the primary plane. Note that this is
11940 * a bit different than what happens if userspace
11941 * explicitly disables the plane by passing fb=0
11942 * because plane->fb still gets set and pinned.
11944 intel_disable_primary_hw_plane(plane
, crtc
);
11949 static void intel_begin_crtc_commit(struct drm_crtc
*crtc
)
11951 struct drm_device
*dev
= crtc
->dev
;
11952 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11953 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11954 struct intel_plane
*intel_plane
;
11955 struct drm_plane
*p
;
11956 unsigned fb_bits
= 0;
11958 /* Track fb's for any planes being disabled */
11959 list_for_each_entry(p
, &dev
->mode_config
.plane_list
, head
) {
11960 intel_plane
= to_intel_plane(p
);
11962 if (intel_crtc
->atomic
.disabled_planes
&
11963 (1 << drm_plane_index(p
))) {
11965 case DRM_PLANE_TYPE_PRIMARY
:
11966 fb_bits
= INTEL_FRONTBUFFER_PRIMARY(intel_plane
->pipe
);
11968 case DRM_PLANE_TYPE_CURSOR
:
11969 fb_bits
= INTEL_FRONTBUFFER_CURSOR(intel_plane
->pipe
);
11971 case DRM_PLANE_TYPE_OVERLAY
:
11972 fb_bits
= INTEL_FRONTBUFFER_SPRITE(intel_plane
->pipe
);
11976 mutex_lock(&dev
->struct_mutex
);
11977 i915_gem_track_fb(intel_fb_obj(p
->fb
), NULL
, fb_bits
);
11978 mutex_unlock(&dev
->struct_mutex
);
11982 if (intel_crtc
->atomic
.wait_for_flips
)
11983 intel_crtc_wait_for_pending_flips(crtc
);
11985 if (intel_crtc
->atomic
.disable_fbc
)
11986 intel_fbc_disable(dev
);
11988 if (intel_crtc
->atomic
.pre_disable_primary
)
11989 intel_pre_disable_primary(crtc
);
11991 if (intel_crtc
->atomic
.update_wm
)
11992 intel_update_watermarks(crtc
);
11994 intel_runtime_pm_get(dev_priv
);
11996 /* Perform vblank evasion around commit operation */
11997 if (intel_crtc
->active
)
11998 intel_crtc
->atomic
.evade
=
11999 intel_pipe_update_start(intel_crtc
,
12000 &intel_crtc
->atomic
.start_vbl_count
);
12003 static void intel_finish_crtc_commit(struct drm_crtc
*crtc
)
12005 struct drm_device
*dev
= crtc
->dev
;
12006 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12007 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
12008 struct drm_plane
*p
;
12010 if (intel_crtc
->atomic
.evade
)
12011 intel_pipe_update_end(intel_crtc
,
12012 intel_crtc
->atomic
.start_vbl_count
);
12014 intel_runtime_pm_put(dev_priv
);
12016 if (intel_crtc
->atomic
.wait_vblank
)
12017 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
12019 intel_frontbuffer_flip(dev
, intel_crtc
->atomic
.fb_bits
);
12021 if (intel_crtc
->atomic
.update_fbc
) {
12022 mutex_lock(&dev
->struct_mutex
);
12023 intel_fbc_update(dev
);
12024 mutex_unlock(&dev
->struct_mutex
);
12027 if (intel_crtc
->atomic
.post_enable_primary
)
12028 intel_post_enable_primary(crtc
);
12030 drm_for_each_legacy_plane(p
, &dev
->mode_config
.plane_list
)
12031 if (intel_crtc
->atomic
.update_sprite_watermarks
& drm_plane_index(p
))
12032 intel_update_sprite_watermarks(p
, crtc
, 0, 0, 0,
12035 memset(&intel_crtc
->atomic
, 0, sizeof(intel_crtc
->atomic
));
12039 * intel_plane_destroy - destroy a plane
12040 * @plane: plane to destroy
12042 * Common destruction function for all types of planes (primary, cursor,
12045 void intel_plane_destroy(struct drm_plane
*plane
)
12047 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
12048 drm_plane_cleanup(plane
);
12049 kfree(intel_plane
);
12052 const struct drm_plane_funcs intel_plane_funcs
= {
12053 .update_plane
= drm_plane_helper_update
,
12054 .disable_plane
= drm_plane_helper_disable
,
12055 .destroy
= intel_plane_destroy
,
12056 .set_property
= intel_plane_set_property
,
12057 .atomic_duplicate_state
= intel_plane_duplicate_state
,
12058 .atomic_destroy_state
= intel_plane_destroy_state
,
12062 static struct drm_plane
*intel_primary_plane_create(struct drm_device
*dev
,
12065 struct intel_plane
*primary
;
12066 struct intel_plane_state
*state
;
12067 const uint32_t *intel_primary_formats
;
12070 primary
= kzalloc(sizeof(*primary
), GFP_KERNEL
);
12071 if (primary
== NULL
)
12074 state
= intel_create_plane_state(&primary
->base
);
12079 primary
->base
.state
= &state
->base
;
12081 primary
->can_scale
= false;
12082 primary
->max_downscale
= 1;
12083 primary
->pipe
= pipe
;
12084 primary
->plane
= pipe
;
12085 primary
->check_plane
= intel_check_primary_plane
;
12086 primary
->commit_plane
= intel_commit_primary_plane
;
12087 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4)
12088 primary
->plane
= !pipe
;
12090 if (INTEL_INFO(dev
)->gen
<= 3) {
12091 intel_primary_formats
= intel_primary_formats_gen2
;
12092 num_formats
= ARRAY_SIZE(intel_primary_formats_gen2
);
12094 intel_primary_formats
= intel_primary_formats_gen4
;
12095 num_formats
= ARRAY_SIZE(intel_primary_formats_gen4
);
12098 drm_universal_plane_init(dev
, &primary
->base
, 0,
12099 &intel_plane_funcs
,
12100 intel_primary_formats
, num_formats
,
12101 DRM_PLANE_TYPE_PRIMARY
);
12103 if (INTEL_INFO(dev
)->gen
>= 4) {
12104 if (!dev
->mode_config
.rotation_property
)
12105 dev
->mode_config
.rotation_property
=
12106 drm_mode_create_rotation_property(dev
,
12107 BIT(DRM_ROTATE_0
) |
12108 BIT(DRM_ROTATE_180
));
12109 if (dev
->mode_config
.rotation_property
)
12110 drm_object_attach_property(&primary
->base
.base
,
12111 dev
->mode_config
.rotation_property
,
12112 state
->base
.rotation
);
12115 drm_plane_helper_add(&primary
->base
, &intel_plane_helper_funcs
);
12117 return &primary
->base
;
12121 intel_check_cursor_plane(struct drm_plane
*plane
,
12122 struct intel_plane_state
*state
)
12124 struct drm_crtc
*crtc
= state
->base
.crtc
;
12125 struct drm_device
*dev
= plane
->dev
;
12126 struct drm_framebuffer
*fb
= state
->base
.fb
;
12127 struct drm_rect
*dest
= &state
->dst
;
12128 struct drm_rect
*src
= &state
->src
;
12129 const struct drm_rect
*clip
= &state
->clip
;
12130 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
12131 struct intel_crtc
*intel_crtc
;
12135 crtc
= crtc
? crtc
: plane
->crtc
;
12136 intel_crtc
= to_intel_crtc(crtc
);
12138 ret
= drm_plane_helper_check_update(plane
, crtc
, fb
,
12140 DRM_PLANE_HELPER_NO_SCALING
,
12141 DRM_PLANE_HELPER_NO_SCALING
,
12142 true, true, &state
->visible
);
12147 /* if we want to turn off the cursor ignore width and height */
12151 /* Check for which cursor types we support */
12152 if (!cursor_size_ok(dev
, state
->base
.crtc_w
, state
->base
.crtc_h
)) {
12153 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
12154 state
->base
.crtc_w
, state
->base
.crtc_h
);
12158 stride
= roundup_pow_of_two(state
->base
.crtc_w
) * 4;
12159 if (obj
->base
.size
< stride
* state
->base
.crtc_h
) {
12160 DRM_DEBUG_KMS("buffer is too small\n");
12164 if (fb
== crtc
->cursor
->fb
)
12167 /* we only need to pin inside GTT if cursor is non-phy */
12168 mutex_lock(&dev
->struct_mutex
);
12169 if (!INTEL_INFO(dev
)->cursor_needs_physical
&& obj
->tiling_mode
) {
12170 DRM_DEBUG_KMS("cursor cannot be tiled\n");
12173 mutex_unlock(&dev
->struct_mutex
);
12176 if (intel_crtc
->active
) {
12177 if (intel_crtc
->cursor_width
!= state
->base
.crtc_w
)
12178 intel_crtc
->atomic
.update_wm
= true;
12180 intel_crtc
->atomic
.fb_bits
|=
12181 INTEL_FRONTBUFFER_CURSOR(intel_crtc
->pipe
);
12188 intel_commit_cursor_plane(struct drm_plane
*plane
,
12189 struct intel_plane_state
*state
)
12191 struct drm_crtc
*crtc
= state
->base
.crtc
;
12192 struct drm_device
*dev
= plane
->dev
;
12193 struct intel_crtc
*intel_crtc
;
12194 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
12195 struct drm_i915_gem_object
*obj
= intel_fb_obj(state
->base
.fb
);
12198 crtc
= crtc
? crtc
: plane
->crtc
;
12199 intel_crtc
= to_intel_crtc(crtc
);
12201 plane
->fb
= state
->base
.fb
;
12202 crtc
->cursor_x
= state
->base
.crtc_x
;
12203 crtc
->cursor_y
= state
->base
.crtc_y
;
12205 intel_plane
->obj
= obj
;
12207 if (intel_crtc
->cursor_bo
== obj
)
12212 else if (!INTEL_INFO(dev
)->cursor_needs_physical
)
12213 addr
= i915_gem_obj_ggtt_offset(obj
);
12215 addr
= obj
->phys_handle
->busaddr
;
12217 intel_crtc
->cursor_addr
= addr
;
12218 intel_crtc
->cursor_bo
= obj
;
12220 intel_crtc
->cursor_width
= state
->base
.crtc_w
;
12221 intel_crtc
->cursor_height
= state
->base
.crtc_h
;
12223 if (intel_crtc
->active
)
12224 intel_crtc_update_cursor(crtc
, state
->visible
);
12227 static struct drm_plane
*intel_cursor_plane_create(struct drm_device
*dev
,
12230 struct intel_plane
*cursor
;
12231 struct intel_plane_state
*state
;
12233 cursor
= kzalloc(sizeof(*cursor
), GFP_KERNEL
);
12234 if (cursor
== NULL
)
12237 state
= intel_create_plane_state(&cursor
->base
);
12242 cursor
->base
.state
= &state
->base
;
12244 cursor
->can_scale
= false;
12245 cursor
->max_downscale
= 1;
12246 cursor
->pipe
= pipe
;
12247 cursor
->plane
= pipe
;
12248 cursor
->check_plane
= intel_check_cursor_plane
;
12249 cursor
->commit_plane
= intel_commit_cursor_plane
;
12251 drm_universal_plane_init(dev
, &cursor
->base
, 0,
12252 &intel_plane_funcs
,
12253 intel_cursor_formats
,
12254 ARRAY_SIZE(intel_cursor_formats
),
12255 DRM_PLANE_TYPE_CURSOR
);
12257 if (INTEL_INFO(dev
)->gen
>= 4) {
12258 if (!dev
->mode_config
.rotation_property
)
12259 dev
->mode_config
.rotation_property
=
12260 drm_mode_create_rotation_property(dev
,
12261 BIT(DRM_ROTATE_0
) |
12262 BIT(DRM_ROTATE_180
));
12263 if (dev
->mode_config
.rotation_property
)
12264 drm_object_attach_property(&cursor
->base
.base
,
12265 dev
->mode_config
.rotation_property
,
12266 state
->base
.rotation
);
12269 drm_plane_helper_add(&cursor
->base
, &intel_plane_helper_funcs
);
12271 return &cursor
->base
;
12274 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
12276 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12277 struct intel_crtc
*intel_crtc
;
12278 struct intel_crtc_state
*crtc_state
= NULL
;
12279 struct drm_plane
*primary
= NULL
;
12280 struct drm_plane
*cursor
= NULL
;
12283 intel_crtc
= kzalloc(sizeof(*intel_crtc
), GFP_KERNEL
);
12284 if (intel_crtc
== NULL
)
12287 crtc_state
= kzalloc(sizeof(*crtc_state
), GFP_KERNEL
);
12290 intel_crtc_set_state(intel_crtc
, crtc_state
);
12292 primary
= intel_primary_plane_create(dev
, pipe
);
12296 cursor
= intel_cursor_plane_create(dev
, pipe
);
12300 ret
= drm_crtc_init_with_planes(dev
, &intel_crtc
->base
, primary
,
12301 cursor
, &intel_crtc_funcs
);
12305 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
12306 for (i
= 0; i
< 256; i
++) {
12307 intel_crtc
->lut_r
[i
] = i
;
12308 intel_crtc
->lut_g
[i
] = i
;
12309 intel_crtc
->lut_b
[i
] = i
;
12313 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12314 * is hooked to pipe B. Hence we want plane A feeding pipe B.
12316 intel_crtc
->pipe
= pipe
;
12317 intel_crtc
->plane
= pipe
;
12318 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4) {
12319 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12320 intel_crtc
->plane
= !pipe
;
12323 intel_crtc
->cursor_base
= ~0;
12324 intel_crtc
->cursor_cntl
= ~0;
12325 intel_crtc
->cursor_size
= ~0;
12327 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
12328 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
12329 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
12330 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
12332 INIT_WORK(&intel_crtc
->mmio_flip
.work
, intel_mmio_flip_work_func
);
12334 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
12336 WARN_ON(drm_crtc_index(&intel_crtc
->base
) != intel_crtc
->pipe
);
12341 drm_plane_cleanup(primary
);
12343 drm_plane_cleanup(cursor
);
12348 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
)
12350 struct drm_encoder
*encoder
= connector
->base
.encoder
;
12351 struct drm_device
*dev
= connector
->base
.dev
;
12353 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
12355 if (!encoder
|| WARN_ON(!encoder
->crtc
))
12356 return INVALID_PIPE
;
12358 return to_intel_crtc(encoder
->crtc
)->pipe
;
12361 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
12362 struct drm_file
*file
)
12364 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
12365 struct drm_crtc
*drmmode_crtc
;
12366 struct intel_crtc
*crtc
;
12368 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
12371 drmmode_crtc
= drm_crtc_find(dev
, pipe_from_crtc_id
->crtc_id
);
12373 if (!drmmode_crtc
) {
12374 DRM_ERROR("no such CRTC id\n");
12378 crtc
= to_intel_crtc(drmmode_crtc
);
12379 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
12384 static int intel_encoder_clones(struct intel_encoder
*encoder
)
12386 struct drm_device
*dev
= encoder
->base
.dev
;
12387 struct intel_encoder
*source_encoder
;
12388 int index_mask
= 0;
12391 for_each_intel_encoder(dev
, source_encoder
) {
12392 if (encoders_cloneable(encoder
, source_encoder
))
12393 index_mask
|= (1 << entry
);
12401 static bool has_edp_a(struct drm_device
*dev
)
12403 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12405 if (!IS_MOBILE(dev
))
12408 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
12411 if (IS_GEN5(dev
) && (I915_READ(FUSE_STRAP
) & ILK_eDP_A_DISABLE
))
12417 static bool intel_crt_present(struct drm_device
*dev
)
12419 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12421 if (INTEL_INFO(dev
)->gen
>= 9)
12424 if (IS_HSW_ULT(dev
) || IS_BDW_ULT(dev
))
12427 if (IS_CHERRYVIEW(dev
))
12430 if (IS_VALLEYVIEW(dev
) && !dev_priv
->vbt
.int_crt_support
)
12436 static void intel_setup_outputs(struct drm_device
*dev
)
12438 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12439 struct intel_encoder
*encoder
;
12440 bool dpd_is_edp
= false;
12442 intel_lvds_init(dev
);
12444 if (intel_crt_present(dev
))
12445 intel_crt_init(dev
);
12447 if (HAS_DDI(dev
)) {
12450 /* Haswell uses DDI functions to detect digital outputs */
12451 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
12452 /* DDI A only supports eDP */
12454 intel_ddi_init(dev
, PORT_A
);
12456 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12458 found
= I915_READ(SFUSE_STRAP
);
12460 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
12461 intel_ddi_init(dev
, PORT_B
);
12462 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
12463 intel_ddi_init(dev
, PORT_C
);
12464 if (found
& SFUSE_STRAP_DDID_DETECTED
)
12465 intel_ddi_init(dev
, PORT_D
);
12466 } else if (HAS_PCH_SPLIT(dev
)) {
12468 dpd_is_edp
= intel_dp_is_edp(dev
, PORT_D
);
12470 if (has_edp_a(dev
))
12471 intel_dp_init(dev
, DP_A
, PORT_A
);
12473 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
12474 /* PCH SDVOB multiplex with HDMIB */
12475 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
12477 intel_hdmi_init(dev
, PCH_HDMIB
, PORT_B
);
12478 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
12479 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
12482 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
12483 intel_hdmi_init(dev
, PCH_HDMIC
, PORT_C
);
12485 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
12486 intel_hdmi_init(dev
, PCH_HDMID
, PORT_D
);
12488 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
12489 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
12491 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
12492 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
12493 } else if (IS_VALLEYVIEW(dev
)) {
12495 * The DP_DETECTED bit is the latched state of the DDC
12496 * SDA pin at boot. However since eDP doesn't require DDC
12497 * (no way to plug in a DP->HDMI dongle) the DDC pins for
12498 * eDP ports may have been muxed to an alternate function.
12499 * Thus we can't rely on the DP_DETECTED bit alone to detect
12500 * eDP ports. Consult the VBT as well as DP_DETECTED to
12501 * detect eDP ports.
12503 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIB
) & SDVO_DETECTED
&&
12504 !intel_dp_is_edp(dev
, PORT_B
))
12505 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIB
,
12507 if (I915_READ(VLV_DISPLAY_BASE
+ DP_B
) & DP_DETECTED
||
12508 intel_dp_is_edp(dev
, PORT_B
))
12509 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_B
, PORT_B
);
12511 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIC
) & SDVO_DETECTED
&&
12512 !intel_dp_is_edp(dev
, PORT_C
))
12513 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIC
,
12515 if (I915_READ(VLV_DISPLAY_BASE
+ DP_C
) & DP_DETECTED
||
12516 intel_dp_is_edp(dev
, PORT_C
))
12517 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_C
, PORT_C
);
12519 if (IS_CHERRYVIEW(dev
)) {
12520 if (I915_READ(VLV_DISPLAY_BASE
+ CHV_HDMID
) & SDVO_DETECTED
)
12521 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ CHV_HDMID
,
12523 /* eDP not supported on port D, so don't check VBT */
12524 if (I915_READ(VLV_DISPLAY_BASE
+ DP_D
) & DP_DETECTED
)
12525 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_D
, PORT_D
);
12528 intel_dsi_init(dev
);
12529 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
12530 bool found
= false;
12532 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
12533 DRM_DEBUG_KMS("probing SDVOB\n");
12534 found
= intel_sdvo_init(dev
, GEN3_SDVOB
, true);
12535 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
12536 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12537 intel_hdmi_init(dev
, GEN4_HDMIB
, PORT_B
);
12540 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
))
12541 intel_dp_init(dev
, DP_B
, PORT_B
);
12544 /* Before G4X SDVOC doesn't have its own detect register */
12546 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
12547 DRM_DEBUG_KMS("probing SDVOC\n");
12548 found
= intel_sdvo_init(dev
, GEN3_SDVOC
, false);
12551 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
12553 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
12554 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12555 intel_hdmi_init(dev
, GEN4_HDMIC
, PORT_C
);
12557 if (SUPPORTS_INTEGRATED_DP(dev
))
12558 intel_dp_init(dev
, DP_C
, PORT_C
);
12561 if (SUPPORTS_INTEGRATED_DP(dev
) &&
12562 (I915_READ(DP_D
) & DP_DETECTED
))
12563 intel_dp_init(dev
, DP_D
, PORT_D
);
12564 } else if (IS_GEN2(dev
))
12565 intel_dvo_init(dev
);
12567 if (SUPPORTS_TV(dev
))
12568 intel_tv_init(dev
);
12570 intel_psr_init(dev
);
12572 for_each_intel_encoder(dev
, encoder
) {
12573 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
12574 encoder
->base
.possible_clones
=
12575 intel_encoder_clones(encoder
);
12578 intel_init_pch_refclk(dev
);
12580 drm_helper_move_panel_connectors_to_head(dev
);
12583 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
12585 struct drm_device
*dev
= fb
->dev
;
12586 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
12588 drm_framebuffer_cleanup(fb
);
12589 mutex_lock(&dev
->struct_mutex
);
12590 WARN_ON(!intel_fb
->obj
->framebuffer_references
--);
12591 drm_gem_object_unreference(&intel_fb
->obj
->base
);
12592 mutex_unlock(&dev
->struct_mutex
);
12596 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
12597 struct drm_file
*file
,
12598 unsigned int *handle
)
12600 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
12601 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
12603 return drm_gem_handle_create(file
, &obj
->base
, handle
);
12606 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
12607 .destroy
= intel_user_framebuffer_destroy
,
12608 .create_handle
= intel_user_framebuffer_create_handle
,
12611 static int intel_framebuffer_init(struct drm_device
*dev
,
12612 struct intel_framebuffer
*intel_fb
,
12613 struct drm_mode_fb_cmd2
*mode_cmd
,
12614 struct drm_i915_gem_object
*obj
)
12616 int aligned_height
;
12620 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
12622 if (obj
->tiling_mode
== I915_TILING_Y
) {
12623 DRM_DEBUG("hardware does not support tiling Y\n");
12627 if (mode_cmd
->pitches
[0] & 63) {
12628 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12629 mode_cmd
->pitches
[0]);
12633 if (INTEL_INFO(dev
)->gen
>= 5 && !IS_VALLEYVIEW(dev
)) {
12634 pitch_limit
= 32*1024;
12635 } else if (INTEL_INFO(dev
)->gen
>= 4) {
12636 if (obj
->tiling_mode
)
12637 pitch_limit
= 16*1024;
12639 pitch_limit
= 32*1024;
12640 } else if (INTEL_INFO(dev
)->gen
>= 3) {
12641 if (obj
->tiling_mode
)
12642 pitch_limit
= 8*1024;
12644 pitch_limit
= 16*1024;
12646 /* XXX DSPC is limited to 4k tiled */
12647 pitch_limit
= 8*1024;
12649 if (mode_cmd
->pitches
[0] > pitch_limit
) {
12650 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12651 obj
->tiling_mode
? "tiled" : "linear",
12652 mode_cmd
->pitches
[0], pitch_limit
);
12656 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
12657 mode_cmd
->pitches
[0] != obj
->stride
) {
12658 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12659 mode_cmd
->pitches
[0], obj
->stride
);
12663 /* Reject formats not supported by any plane early. */
12664 switch (mode_cmd
->pixel_format
) {
12665 case DRM_FORMAT_C8
:
12666 case DRM_FORMAT_RGB565
:
12667 case DRM_FORMAT_XRGB8888
:
12668 case DRM_FORMAT_ARGB8888
:
12670 case DRM_FORMAT_XRGB1555
:
12671 case DRM_FORMAT_ARGB1555
:
12672 if (INTEL_INFO(dev
)->gen
> 3) {
12673 DRM_DEBUG("unsupported pixel format: %s\n",
12674 drm_get_format_name(mode_cmd
->pixel_format
));
12678 case DRM_FORMAT_XBGR8888
:
12679 case DRM_FORMAT_ABGR8888
:
12680 case DRM_FORMAT_XRGB2101010
:
12681 case DRM_FORMAT_ARGB2101010
:
12682 case DRM_FORMAT_XBGR2101010
:
12683 case DRM_FORMAT_ABGR2101010
:
12684 if (INTEL_INFO(dev
)->gen
< 4) {
12685 DRM_DEBUG("unsupported pixel format: %s\n",
12686 drm_get_format_name(mode_cmd
->pixel_format
));
12690 case DRM_FORMAT_YUYV
:
12691 case DRM_FORMAT_UYVY
:
12692 case DRM_FORMAT_YVYU
:
12693 case DRM_FORMAT_VYUY
:
12694 if (INTEL_INFO(dev
)->gen
< 5) {
12695 DRM_DEBUG("unsupported pixel format: %s\n",
12696 drm_get_format_name(mode_cmd
->pixel_format
));
12701 DRM_DEBUG("unsupported pixel format: %s\n",
12702 drm_get_format_name(mode_cmd
->pixel_format
));
12706 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12707 if (mode_cmd
->offsets
[0] != 0)
12710 aligned_height
= intel_fb_align_height(dev
, mode_cmd
->height
,
12712 /* FIXME drm helper for size checks (especially planar formats)? */
12713 if (obj
->base
.size
< aligned_height
* mode_cmd
->pitches
[0])
12716 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
12717 intel_fb
->obj
= obj
;
12718 intel_fb
->obj
->framebuffer_references
++;
12720 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
12722 DRM_ERROR("framebuffer init failed %d\n", ret
);
12729 static struct drm_framebuffer
*
12730 intel_user_framebuffer_create(struct drm_device
*dev
,
12731 struct drm_file
*filp
,
12732 struct drm_mode_fb_cmd2
*mode_cmd
)
12734 struct drm_i915_gem_object
*obj
;
12736 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
12737 mode_cmd
->handles
[0]));
12738 if (&obj
->base
== NULL
)
12739 return ERR_PTR(-ENOENT
);
12741 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
12744 #ifndef CONFIG_DRM_I915_FBDEV
12745 static inline void intel_fbdev_output_poll_changed(struct drm_device
*dev
)
12750 static const struct drm_mode_config_funcs intel_mode_funcs
= {
12751 .fb_create
= intel_user_framebuffer_create
,
12752 .output_poll_changed
= intel_fbdev_output_poll_changed
,
12755 /* Set up chip specific display functions */
12756 static void intel_init_display(struct drm_device
*dev
)
12758 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12760 if (HAS_PCH_SPLIT(dev
) || IS_G4X(dev
))
12761 dev_priv
->display
.find_dpll
= g4x_find_best_dpll
;
12762 else if (IS_CHERRYVIEW(dev
))
12763 dev_priv
->display
.find_dpll
= chv_find_best_dpll
;
12764 else if (IS_VALLEYVIEW(dev
))
12765 dev_priv
->display
.find_dpll
= vlv_find_best_dpll
;
12766 else if (IS_PINEVIEW(dev
))
12767 dev_priv
->display
.find_dpll
= pnv_find_best_dpll
;
12769 dev_priv
->display
.find_dpll
= i9xx_find_best_dpll
;
12771 if (INTEL_INFO(dev
)->gen
>= 9) {
12772 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
12773 dev_priv
->display
.get_initial_plane_config
=
12774 skylake_get_initial_plane_config
;
12775 dev_priv
->display
.crtc_compute_clock
=
12776 haswell_crtc_compute_clock
;
12777 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
12778 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
12779 dev_priv
->display
.off
= ironlake_crtc_off
;
12780 dev_priv
->display
.update_primary_plane
=
12781 skylake_update_primary_plane
;
12782 } else if (HAS_DDI(dev
)) {
12783 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
12784 dev_priv
->display
.get_initial_plane_config
=
12785 ironlake_get_initial_plane_config
;
12786 dev_priv
->display
.crtc_compute_clock
=
12787 haswell_crtc_compute_clock
;
12788 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
12789 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
12790 dev_priv
->display
.off
= ironlake_crtc_off
;
12791 dev_priv
->display
.update_primary_plane
=
12792 ironlake_update_primary_plane
;
12793 } else if (HAS_PCH_SPLIT(dev
)) {
12794 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
12795 dev_priv
->display
.get_initial_plane_config
=
12796 ironlake_get_initial_plane_config
;
12797 dev_priv
->display
.crtc_compute_clock
=
12798 ironlake_crtc_compute_clock
;
12799 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
12800 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
12801 dev_priv
->display
.off
= ironlake_crtc_off
;
12802 dev_priv
->display
.update_primary_plane
=
12803 ironlake_update_primary_plane
;
12804 } else if (IS_VALLEYVIEW(dev
)) {
12805 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
12806 dev_priv
->display
.get_initial_plane_config
=
12807 i9xx_get_initial_plane_config
;
12808 dev_priv
->display
.crtc_compute_clock
= i9xx_crtc_compute_clock
;
12809 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
12810 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
12811 dev_priv
->display
.off
= i9xx_crtc_off
;
12812 dev_priv
->display
.update_primary_plane
=
12813 i9xx_update_primary_plane
;
12815 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
12816 dev_priv
->display
.get_initial_plane_config
=
12817 i9xx_get_initial_plane_config
;
12818 dev_priv
->display
.crtc_compute_clock
= i9xx_crtc_compute_clock
;
12819 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
12820 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
12821 dev_priv
->display
.off
= i9xx_crtc_off
;
12822 dev_priv
->display
.update_primary_plane
=
12823 i9xx_update_primary_plane
;
12826 /* Returns the core display clock speed */
12827 if (IS_VALLEYVIEW(dev
))
12828 dev_priv
->display
.get_display_clock_speed
=
12829 valleyview_get_display_clock_speed
;
12830 else if (IS_I945G(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
12831 dev_priv
->display
.get_display_clock_speed
=
12832 i945_get_display_clock_speed
;
12833 else if (IS_I915G(dev
))
12834 dev_priv
->display
.get_display_clock_speed
=
12835 i915_get_display_clock_speed
;
12836 else if (IS_I945GM(dev
) || IS_845G(dev
))
12837 dev_priv
->display
.get_display_clock_speed
=
12838 i9xx_misc_get_display_clock_speed
;
12839 else if (IS_PINEVIEW(dev
))
12840 dev_priv
->display
.get_display_clock_speed
=
12841 pnv_get_display_clock_speed
;
12842 else if (IS_I915GM(dev
))
12843 dev_priv
->display
.get_display_clock_speed
=
12844 i915gm_get_display_clock_speed
;
12845 else if (IS_I865G(dev
))
12846 dev_priv
->display
.get_display_clock_speed
=
12847 i865_get_display_clock_speed
;
12848 else if (IS_I85X(dev
))
12849 dev_priv
->display
.get_display_clock_speed
=
12850 i855_get_display_clock_speed
;
12851 else /* 852, 830 */
12852 dev_priv
->display
.get_display_clock_speed
=
12853 i830_get_display_clock_speed
;
12855 if (IS_GEN5(dev
)) {
12856 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
12857 } else if (IS_GEN6(dev
)) {
12858 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
12859 } else if (IS_IVYBRIDGE(dev
)) {
12860 /* FIXME: detect B0+ stepping and use auto training */
12861 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
12862 dev_priv
->display
.modeset_global_resources
=
12863 ivb_modeset_global_resources
;
12864 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
12865 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
12866 } else if (IS_VALLEYVIEW(dev
)) {
12867 dev_priv
->display
.modeset_global_resources
=
12868 valleyview_modeset_global_resources
;
12871 /* Default just returns -ENODEV to indicate unsupported */
12872 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
12874 switch (INTEL_INFO(dev
)->gen
) {
12876 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
12880 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
12885 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
12889 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
12892 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12893 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
12896 dev_priv
->display
.queue_flip
= intel_gen9_queue_flip
;
12900 intel_panel_init_backlight_funcs(dev
);
12902 mutex_init(&dev_priv
->pps_mutex
);
12906 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12907 * resume, or other times. This quirk makes sure that's the case for
12908 * affected systems.
12910 static void quirk_pipea_force(struct drm_device
*dev
)
12912 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12914 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
12915 DRM_INFO("applying pipe a force quirk\n");
12918 static void quirk_pipeb_force(struct drm_device
*dev
)
12920 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12922 dev_priv
->quirks
|= QUIRK_PIPEB_FORCE
;
12923 DRM_INFO("applying pipe b force quirk\n");
12927 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12929 static void quirk_ssc_force_disable(struct drm_device
*dev
)
12931 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12932 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
12933 DRM_INFO("applying lvds SSC disable quirk\n");
12937 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12940 static void quirk_invert_brightness(struct drm_device
*dev
)
12942 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12943 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
12944 DRM_INFO("applying inverted panel brightness quirk\n");
12947 /* Some VBT's incorrectly indicate no backlight is present */
12948 static void quirk_backlight_present(struct drm_device
*dev
)
12950 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12951 dev_priv
->quirks
|= QUIRK_BACKLIGHT_PRESENT
;
12952 DRM_INFO("applying backlight present quirk\n");
12955 struct intel_quirk
{
12957 int subsystem_vendor
;
12958 int subsystem_device
;
12959 void (*hook
)(struct drm_device
*dev
);
12962 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12963 struct intel_dmi_quirk
{
12964 void (*hook
)(struct drm_device
*dev
);
12965 const struct dmi_system_id (*dmi_id_list
)[];
12968 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
12970 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
12974 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
12976 .dmi_id_list
= &(const struct dmi_system_id
[]) {
12978 .callback
= intel_dmi_reverse_brightness
,
12979 .ident
= "NCR Corporation",
12980 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
12981 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
12984 { } /* terminating entry */
12986 .hook
= quirk_invert_brightness
,
12990 static struct intel_quirk intel_quirks
[] = {
12991 /* HP Mini needs pipe A force quirk (LP: #322104) */
12992 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force
},
12994 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12995 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
12997 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12998 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
13000 /* 830 needs to leave pipe A & dpll A up */
13001 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
13003 /* 830 needs to leave pipe B & dpll B up */
13004 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipeb_force
},
13006 /* Lenovo U160 cannot use SSC on LVDS */
13007 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
13009 /* Sony Vaio Y cannot use SSC on LVDS */
13010 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
13012 /* Acer Aspire 5734Z must invert backlight brightness */
13013 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
13015 /* Acer/eMachines G725 */
13016 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness
},
13018 /* Acer/eMachines e725 */
13019 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness
},
13021 /* Acer/Packard Bell NCL20 */
13022 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness
},
13024 /* Acer Aspire 4736Z */
13025 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness
},
13027 /* Acer Aspire 5336 */
13028 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness
},
13030 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
13031 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present
},
13033 /* Acer C720 Chromebook (Core i3 4005U) */
13034 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present
},
13036 /* Apple Macbook 2,1 (Core 2 T7400) */
13037 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present
},
13039 /* Toshiba CB35 Chromebook (Celeron 2955U) */
13040 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present
},
13042 /* HP Chromebook 14 (Celeron 2955U) */
13043 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present
},
13046 static void intel_init_quirks(struct drm_device
*dev
)
13048 struct pci_dev
*d
= dev
->pdev
;
13051 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
13052 struct intel_quirk
*q
= &intel_quirks
[i
];
13054 if (d
->device
== q
->device
&&
13055 (d
->subsystem_vendor
== q
->subsystem_vendor
||
13056 q
->subsystem_vendor
== PCI_ANY_ID
) &&
13057 (d
->subsystem_device
== q
->subsystem_device
||
13058 q
->subsystem_device
== PCI_ANY_ID
))
13061 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
13062 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
13063 intel_dmi_quirks
[i
].hook(dev
);
13067 /* Disable the VGA plane that we never use */
13068 static void i915_disable_vga(struct drm_device
*dev
)
13070 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13072 u32 vga_reg
= i915_vgacntrl_reg(dev
);
13074 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
13075 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
13076 outb(SR01
, VGA_SR_INDEX
);
13077 sr1
= inb(VGA_SR_DATA
);
13078 outb(sr1
| 1<<5, VGA_SR_DATA
);
13079 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
13082 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
13083 POSTING_READ(vga_reg
);
13086 void intel_modeset_init_hw(struct drm_device
*dev
)
13088 intel_prepare_ddi(dev
);
13090 if (IS_VALLEYVIEW(dev
))
13091 vlv_update_cdclk(dev
);
13093 intel_init_clock_gating(dev
);
13095 intel_enable_gt_powersave(dev
);
13098 void intel_modeset_init(struct drm_device
*dev
)
13100 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13103 struct intel_crtc
*crtc
;
13105 drm_mode_config_init(dev
);
13107 dev
->mode_config
.min_width
= 0;
13108 dev
->mode_config
.min_height
= 0;
13110 dev
->mode_config
.preferred_depth
= 24;
13111 dev
->mode_config
.prefer_shadow
= 1;
13113 dev
->mode_config
.funcs
= &intel_mode_funcs
;
13115 intel_init_quirks(dev
);
13117 intel_init_pm(dev
);
13119 if (INTEL_INFO(dev
)->num_pipes
== 0)
13122 intel_init_display(dev
);
13123 intel_init_audio(dev
);
13125 if (IS_GEN2(dev
)) {
13126 dev
->mode_config
.max_width
= 2048;
13127 dev
->mode_config
.max_height
= 2048;
13128 } else if (IS_GEN3(dev
)) {
13129 dev
->mode_config
.max_width
= 4096;
13130 dev
->mode_config
.max_height
= 4096;
13132 dev
->mode_config
.max_width
= 8192;
13133 dev
->mode_config
.max_height
= 8192;
13136 if (IS_845G(dev
) || IS_I865G(dev
)) {
13137 dev
->mode_config
.cursor_width
= IS_845G(dev
) ? 64 : 512;
13138 dev
->mode_config
.cursor_height
= 1023;
13139 } else if (IS_GEN2(dev
)) {
13140 dev
->mode_config
.cursor_width
= GEN2_CURSOR_WIDTH
;
13141 dev
->mode_config
.cursor_height
= GEN2_CURSOR_HEIGHT
;
13143 dev
->mode_config
.cursor_width
= MAX_CURSOR_WIDTH
;
13144 dev
->mode_config
.cursor_height
= MAX_CURSOR_HEIGHT
;
13147 dev
->mode_config
.fb_base
= dev_priv
->gtt
.mappable_base
;
13149 DRM_DEBUG_KMS("%d display pipe%s available.\n",
13150 INTEL_INFO(dev
)->num_pipes
,
13151 INTEL_INFO(dev
)->num_pipes
> 1 ? "s" : "");
13153 for_each_pipe(dev_priv
, pipe
) {
13154 intel_crtc_init(dev
, pipe
);
13155 for_each_sprite(pipe
, sprite
) {
13156 ret
= intel_plane_init(dev
, pipe
, sprite
);
13158 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
13159 pipe_name(pipe
), sprite_name(pipe
, sprite
), ret
);
13163 intel_init_dpio(dev
);
13165 intel_shared_dpll_init(dev
);
13167 /* Just disable it once at startup */
13168 i915_disable_vga(dev
);
13169 intel_setup_outputs(dev
);
13171 /* Just in case the BIOS is doing something questionable. */
13172 intel_fbc_disable(dev
);
13174 drm_modeset_lock_all(dev
);
13175 intel_modeset_setup_hw_state(dev
, false);
13176 drm_modeset_unlock_all(dev
);
13178 for_each_intel_crtc(dev
, crtc
) {
13183 * Note that reserving the BIOS fb up front prevents us
13184 * from stuffing other stolen allocations like the ring
13185 * on top. This prevents some ugliness at boot time, and
13186 * can even allow for smooth boot transitions if the BIOS
13187 * fb is large enough for the active pipe configuration.
13189 if (dev_priv
->display
.get_initial_plane_config
) {
13190 dev_priv
->display
.get_initial_plane_config(crtc
,
13191 &crtc
->plane_config
);
13193 * If the fb is shared between multiple heads, we'll
13194 * just get the first one.
13196 intel_find_plane_obj(crtc
, &crtc
->plane_config
);
13201 static void intel_enable_pipe_a(struct drm_device
*dev
)
13203 struct intel_connector
*connector
;
13204 struct drm_connector
*crt
= NULL
;
13205 struct intel_load_detect_pipe load_detect_temp
;
13206 struct drm_modeset_acquire_ctx
*ctx
= dev
->mode_config
.acquire_ctx
;
13208 /* We can't just switch on the pipe A, we need to set things up with a
13209 * proper mode and output configuration. As a gross hack, enable pipe A
13210 * by enabling the load detect pipe once. */
13211 list_for_each_entry(connector
,
13212 &dev
->mode_config
.connector_list
,
13214 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
13215 crt
= &connector
->base
;
13223 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
, ctx
))
13224 intel_release_load_detect_pipe(crt
, &load_detect_temp
);
13228 intel_check_plane_mapping(struct intel_crtc
*crtc
)
13230 struct drm_device
*dev
= crtc
->base
.dev
;
13231 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13234 if (INTEL_INFO(dev
)->num_pipes
== 1)
13237 reg
= DSPCNTR(!crtc
->plane
);
13238 val
= I915_READ(reg
);
13240 if ((val
& DISPLAY_PLANE_ENABLE
) &&
13241 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
13247 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
13249 struct drm_device
*dev
= crtc
->base
.dev
;
13250 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13253 /* Clear any frame start delays used for debugging left by the BIOS */
13254 reg
= PIPECONF(crtc
->config
->cpu_transcoder
);
13255 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
13257 /* restore vblank interrupts to correct state */
13258 if (crtc
->active
) {
13259 update_scanline_offset(crtc
);
13260 drm_vblank_on(dev
, crtc
->pipe
);
13262 drm_vblank_off(dev
, crtc
->pipe
);
13264 /* We need to sanitize the plane -> pipe mapping first because this will
13265 * disable the crtc (and hence change the state) if it is wrong. Note
13266 * that gen4+ has a fixed plane -> pipe mapping. */
13267 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
13268 struct intel_connector
*connector
;
13271 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13272 crtc
->base
.base
.id
);
13274 /* Pipe has the wrong plane attached and the plane is active.
13275 * Temporarily change the plane mapping and disable everything
13277 plane
= crtc
->plane
;
13278 crtc
->plane
= !plane
;
13279 crtc
->primary_enabled
= true;
13280 dev_priv
->display
.crtc_disable(&crtc
->base
);
13281 crtc
->plane
= plane
;
13283 /* ... and break all links. */
13284 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
13286 if (connector
->encoder
->base
.crtc
!= &crtc
->base
)
13289 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
13290 connector
->base
.encoder
= NULL
;
13292 /* multiple connectors may have the same encoder:
13293 * handle them and break crtc link separately */
13294 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
13296 if (connector
->encoder
->base
.crtc
== &crtc
->base
) {
13297 connector
->encoder
->base
.crtc
= NULL
;
13298 connector
->encoder
->connectors_active
= false;
13301 WARN_ON(crtc
->active
);
13302 crtc
->base
.enabled
= false;
13305 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
13306 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
13307 /* BIOS forgot to enable pipe A, this mostly happens after
13308 * resume. Force-enable the pipe to fix this, the update_dpms
13309 * call below we restore the pipe to the right state, but leave
13310 * the required bits on. */
13311 intel_enable_pipe_a(dev
);
13314 /* Adjust the state of the output pipe according to whether we
13315 * have active connectors/encoders. */
13316 intel_crtc_update_dpms(&crtc
->base
);
13318 if (crtc
->active
!= crtc
->base
.enabled
) {
13319 struct intel_encoder
*encoder
;
13321 /* This can happen either due to bugs in the get_hw_state
13322 * functions or because the pipe is force-enabled due to the
13324 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13325 crtc
->base
.base
.id
,
13326 crtc
->base
.enabled
? "enabled" : "disabled",
13327 crtc
->active
? "enabled" : "disabled");
13329 crtc
->base
.enabled
= crtc
->active
;
13331 /* Because we only establish the connector -> encoder ->
13332 * crtc links if something is active, this means the
13333 * crtc is now deactivated. Break the links. connector
13334 * -> encoder links are only establish when things are
13335 * actually up, hence no need to break them. */
13336 WARN_ON(crtc
->active
);
13338 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
13339 WARN_ON(encoder
->connectors_active
);
13340 encoder
->base
.crtc
= NULL
;
13344 if (crtc
->active
|| HAS_GMCH_DISPLAY(dev
)) {
13346 * We start out with underrun reporting disabled to avoid races.
13347 * For correct bookkeeping mark this on active crtcs.
13349 * Also on gmch platforms we dont have any hardware bits to
13350 * disable the underrun reporting. Which means we need to start
13351 * out with underrun reporting disabled also on inactive pipes,
13352 * since otherwise we'll complain about the garbage we read when
13353 * e.g. coming up after runtime pm.
13355 * No protection against concurrent access is required - at
13356 * worst a fifo underrun happens which also sets this to false.
13358 crtc
->cpu_fifo_underrun_disabled
= true;
13359 crtc
->pch_fifo_underrun_disabled
= true;
13363 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
13365 struct intel_connector
*connector
;
13366 struct drm_device
*dev
= encoder
->base
.dev
;
13368 /* We need to check both for a crtc link (meaning that the
13369 * encoder is active and trying to read from a pipe) and the
13370 * pipe itself being active. */
13371 bool has_active_crtc
= encoder
->base
.crtc
&&
13372 to_intel_crtc(encoder
->base
.crtc
)->active
;
13374 if (encoder
->connectors_active
&& !has_active_crtc
) {
13375 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13376 encoder
->base
.base
.id
,
13377 encoder
->base
.name
);
13379 /* Connector is active, but has no active pipe. This is
13380 * fallout from our resume register restoring. Disable
13381 * the encoder manually again. */
13382 if (encoder
->base
.crtc
) {
13383 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13384 encoder
->base
.base
.id
,
13385 encoder
->base
.name
);
13386 encoder
->disable(encoder
);
13387 if (encoder
->post_disable
)
13388 encoder
->post_disable(encoder
);
13390 encoder
->base
.crtc
= NULL
;
13391 encoder
->connectors_active
= false;
13393 /* Inconsistent output/port/pipe state happens presumably due to
13394 * a bug in one of the get_hw_state functions. Or someplace else
13395 * in our code, like the register restore mess on resume. Clamp
13396 * things to off as a safer default. */
13397 list_for_each_entry(connector
,
13398 &dev
->mode_config
.connector_list
,
13400 if (connector
->encoder
!= encoder
)
13402 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
13403 connector
->base
.encoder
= NULL
;
13406 /* Enabled encoders without active connectors will be fixed in
13407 * the crtc fixup. */
13410 void i915_redisable_vga_power_on(struct drm_device
*dev
)
13412 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13413 u32 vga_reg
= i915_vgacntrl_reg(dev
);
13415 if (!(I915_READ(vga_reg
) & VGA_DISP_DISABLE
)) {
13416 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13417 i915_disable_vga(dev
);
13421 void i915_redisable_vga(struct drm_device
*dev
)
13423 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13425 /* This function can be called both from intel_modeset_setup_hw_state or
13426 * at a very early point in our resume sequence, where the power well
13427 * structures are not yet restored. Since this function is at a very
13428 * paranoid "someone might have enabled VGA while we were not looking"
13429 * level, just check if the power well is enabled instead of trying to
13430 * follow the "don't touch the power well if we don't need it" policy
13431 * the rest of the driver uses. */
13432 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_VGA
))
13435 i915_redisable_vga_power_on(dev
);
13438 static bool primary_get_hw_state(struct intel_crtc
*crtc
)
13440 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
13445 return I915_READ(DSPCNTR(crtc
->plane
)) & DISPLAY_PLANE_ENABLE
;
13448 static void intel_modeset_readout_hw_state(struct drm_device
*dev
)
13450 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13452 struct intel_crtc
*crtc
;
13453 struct intel_encoder
*encoder
;
13454 struct intel_connector
*connector
;
13457 for_each_intel_crtc(dev
, crtc
) {
13458 memset(crtc
->config
, 0, sizeof(*crtc
->config
));
13460 crtc
->config
->quirks
|= PIPE_CONFIG_QUIRK_INHERITED_MODE
;
13462 crtc
->active
= dev_priv
->display
.get_pipe_config(crtc
,
13465 crtc
->base
.enabled
= crtc
->active
;
13466 crtc
->primary_enabled
= primary_get_hw_state(crtc
);
13468 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13469 crtc
->base
.base
.id
,
13470 crtc
->active
? "enabled" : "disabled");
13473 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
13474 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
13476 pll
->on
= pll
->get_hw_state(dev_priv
, pll
,
13477 &pll
->config
.hw_state
);
13479 pll
->config
.crtc_mask
= 0;
13480 for_each_intel_crtc(dev
, crtc
) {
13481 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
) {
13483 pll
->config
.crtc_mask
|= 1 << crtc
->pipe
;
13487 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
13488 pll
->name
, pll
->config
.crtc_mask
, pll
->on
);
13490 if (pll
->config
.crtc_mask
)
13491 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
13494 for_each_intel_encoder(dev
, encoder
) {
13497 if (encoder
->get_hw_state(encoder
, &pipe
)) {
13498 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
13499 encoder
->base
.crtc
= &crtc
->base
;
13500 encoder
->get_config(encoder
, crtc
->config
);
13502 encoder
->base
.crtc
= NULL
;
13505 encoder
->connectors_active
= false;
13506 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13507 encoder
->base
.base
.id
,
13508 encoder
->base
.name
,
13509 encoder
->base
.crtc
? "enabled" : "disabled",
13513 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
13515 if (connector
->get_hw_state(connector
)) {
13516 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
13517 connector
->encoder
->connectors_active
= true;
13518 connector
->base
.encoder
= &connector
->encoder
->base
;
13520 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
13521 connector
->base
.encoder
= NULL
;
13523 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13524 connector
->base
.base
.id
,
13525 connector
->base
.name
,
13526 connector
->base
.encoder
? "enabled" : "disabled");
13530 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13531 * and i915 state tracking structures. */
13532 void intel_modeset_setup_hw_state(struct drm_device
*dev
,
13533 bool force_restore
)
13535 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13537 struct intel_crtc
*crtc
;
13538 struct intel_encoder
*encoder
;
13541 intel_modeset_readout_hw_state(dev
);
13544 * Now that we have the config, copy it to each CRTC struct
13545 * Note that this could go away if we move to using crtc_config
13546 * checking everywhere.
13548 for_each_intel_crtc(dev
, crtc
) {
13549 if (crtc
->active
&& i915
.fastboot
) {
13550 intel_mode_from_pipe_config(&crtc
->base
.mode
,
13552 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13553 crtc
->base
.base
.id
);
13554 drm_mode_debug_printmodeline(&crtc
->base
.mode
);
13558 /* HW state is read out, now we need to sanitize this mess. */
13559 for_each_intel_encoder(dev
, encoder
) {
13560 intel_sanitize_encoder(encoder
);
13563 for_each_pipe(dev_priv
, pipe
) {
13564 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
13565 intel_sanitize_crtc(crtc
);
13566 intel_dump_pipe_config(crtc
, crtc
->config
,
13567 "[setup_hw_state]");
13570 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
13571 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
13573 if (!pll
->on
|| pll
->active
)
13576 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll
->name
);
13578 pll
->disable(dev_priv
, pll
);
13583 skl_wm_get_hw_state(dev
);
13584 else if (HAS_PCH_SPLIT(dev
))
13585 ilk_wm_get_hw_state(dev
);
13587 if (force_restore
) {
13588 i915_redisable_vga(dev
);
13591 * We need to use raw interfaces for restoring state to avoid
13592 * checking (bogus) intermediate states.
13594 for_each_pipe(dev_priv
, pipe
) {
13595 struct drm_crtc
*crtc
=
13596 dev_priv
->pipe_to_crtc_mapping
[pipe
];
13598 intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
,
13599 crtc
->primary
->fb
);
13602 intel_modeset_update_staged_output_state(dev
);
13605 intel_modeset_check_state(dev
);
13608 void intel_modeset_gem_init(struct drm_device
*dev
)
13610 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13611 struct drm_crtc
*c
;
13612 struct drm_i915_gem_object
*obj
;
13614 mutex_lock(&dev
->struct_mutex
);
13615 intel_init_gt_powersave(dev
);
13616 mutex_unlock(&dev
->struct_mutex
);
13619 * There may be no VBT; and if the BIOS enabled SSC we can
13620 * just keep using it to avoid unnecessary flicker. Whereas if the
13621 * BIOS isn't using it, don't assume it will work even if the VBT
13622 * indicates as much.
13624 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
13625 dev_priv
->vbt
.lvds_use_ssc
= !!(I915_READ(PCH_DREF_CONTROL
) &
13628 intel_modeset_init_hw(dev
);
13630 intel_setup_overlay(dev
);
13633 * Make sure any fbs we allocated at startup are properly
13634 * pinned & fenced. When we do the allocation it's too early
13637 mutex_lock(&dev
->struct_mutex
);
13638 for_each_crtc(dev
, c
) {
13639 obj
= intel_fb_obj(c
->primary
->fb
);
13643 if (intel_pin_and_fence_fb_obj(c
->primary
,
13646 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13647 to_intel_crtc(c
)->pipe
);
13648 drm_framebuffer_unreference(c
->primary
->fb
);
13649 c
->primary
->fb
= NULL
;
13652 mutex_unlock(&dev
->struct_mutex
);
13654 intel_backlight_register(dev
);
13657 void intel_connector_unregister(struct intel_connector
*intel_connector
)
13659 struct drm_connector
*connector
= &intel_connector
->base
;
13661 intel_panel_destroy_backlight(connector
);
13662 drm_connector_unregister(connector
);
13665 void intel_modeset_cleanup(struct drm_device
*dev
)
13667 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13668 struct drm_connector
*connector
;
13670 intel_disable_gt_powersave(dev
);
13672 intel_backlight_unregister(dev
);
13675 * Interrupts and polling as the first thing to avoid creating havoc.
13676 * Too much stuff here (turning of connectors, ...) would
13677 * experience fancy races otherwise.
13679 intel_irq_uninstall(dev_priv
);
13682 * Due to the hpd irq storm handling the hotplug work can re-arm the
13683 * poll handlers. Hence disable polling after hpd handling is shut down.
13685 drm_kms_helper_poll_fini(dev
);
13687 mutex_lock(&dev
->struct_mutex
);
13689 intel_unregister_dsm_handler();
13691 intel_fbc_disable(dev
);
13693 ironlake_teardown_rc6(dev
);
13695 mutex_unlock(&dev
->struct_mutex
);
13697 /* flush any delayed tasks or pending work */
13698 flush_scheduled_work();
13700 /* destroy the backlight and sysfs files before encoders/connectors */
13701 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
13702 struct intel_connector
*intel_connector
;
13704 intel_connector
= to_intel_connector(connector
);
13705 intel_connector
->unregister(intel_connector
);
13708 drm_mode_config_cleanup(dev
);
13710 intel_cleanup_overlay(dev
);
13712 mutex_lock(&dev
->struct_mutex
);
13713 intel_cleanup_gt_powersave(dev
);
13714 mutex_unlock(&dev
->struct_mutex
);
13718 * Return which encoder is currently attached for connector.
13720 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
13722 return &intel_attached_encoder(connector
)->base
;
13725 void intel_connector_attach_encoder(struct intel_connector
*connector
,
13726 struct intel_encoder
*encoder
)
13728 connector
->encoder
= encoder
;
13729 drm_mode_connector_attach_encoder(&connector
->base
,
13734 * set vga decode state - true == enable VGA decode
13736 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
13738 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13739 unsigned reg
= INTEL_INFO(dev
)->gen
>= 6 ? SNB_GMCH_CTRL
: INTEL_GMCH_CTRL
;
13742 if (pci_read_config_word(dev_priv
->bridge_dev
, reg
, &gmch_ctrl
)) {
13743 DRM_ERROR("failed to read control word\n");
13747 if (!!(gmch_ctrl
& INTEL_GMCH_VGA_DISABLE
) == !state
)
13751 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
13753 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
13755 if (pci_write_config_word(dev_priv
->bridge_dev
, reg
, gmch_ctrl
)) {
13756 DRM_ERROR("failed to write control word\n");
13763 struct intel_display_error_state
{
13765 u32 power_well_driver
;
13767 int num_transcoders
;
13769 struct intel_cursor_error_state
{
13774 } cursor
[I915_MAX_PIPES
];
13776 struct intel_pipe_error_state
{
13777 bool power_domain_on
;
13780 } pipe
[I915_MAX_PIPES
];
13782 struct intel_plane_error_state
{
13790 } plane
[I915_MAX_PIPES
];
13792 struct intel_transcoder_error_state
{
13793 bool power_domain_on
;
13794 enum transcoder cpu_transcoder
;
13807 struct intel_display_error_state
*
13808 intel_display_capture_error_state(struct drm_device
*dev
)
13810 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13811 struct intel_display_error_state
*error
;
13812 int transcoders
[] = {
13820 if (INTEL_INFO(dev
)->num_pipes
== 0)
13823 error
= kzalloc(sizeof(*error
), GFP_ATOMIC
);
13827 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
13828 error
->power_well_driver
= I915_READ(HSW_PWR_WELL_DRIVER
);
13830 for_each_pipe(dev_priv
, i
) {
13831 error
->pipe
[i
].power_domain_on
=
13832 __intel_display_power_is_enabled(dev_priv
,
13833 POWER_DOMAIN_PIPE(i
));
13834 if (!error
->pipe
[i
].power_domain_on
)
13837 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
13838 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
13839 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
13841 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
13842 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
13843 if (INTEL_INFO(dev
)->gen
<= 3) {
13844 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
13845 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
13847 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
13848 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
13849 if (INTEL_INFO(dev
)->gen
>= 4) {
13850 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
13851 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
13854 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
13856 if (HAS_GMCH_DISPLAY(dev
))
13857 error
->pipe
[i
].stat
= I915_READ(PIPESTAT(i
));
13860 error
->num_transcoders
= INTEL_INFO(dev
)->num_pipes
;
13861 if (HAS_DDI(dev_priv
->dev
))
13862 error
->num_transcoders
++; /* Account for eDP. */
13864 for (i
= 0; i
< error
->num_transcoders
; i
++) {
13865 enum transcoder cpu_transcoder
= transcoders
[i
];
13867 error
->transcoder
[i
].power_domain_on
=
13868 __intel_display_power_is_enabled(dev_priv
,
13869 POWER_DOMAIN_TRANSCODER(cpu_transcoder
));
13870 if (!error
->transcoder
[i
].power_domain_on
)
13873 error
->transcoder
[i
].cpu_transcoder
= cpu_transcoder
;
13875 error
->transcoder
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
13876 error
->transcoder
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
13877 error
->transcoder
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
13878 error
->transcoder
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
13879 error
->transcoder
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
13880 error
->transcoder
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
13881 error
->transcoder
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
13887 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13890 intel_display_print_error_state(struct drm_i915_error_state_buf
*m
,
13891 struct drm_device
*dev
,
13892 struct intel_display_error_state
*error
)
13894 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13900 err_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev
)->num_pipes
);
13901 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
13902 err_printf(m
, "PWR_WELL_CTL2: %08x\n",
13903 error
->power_well_driver
);
13904 for_each_pipe(dev_priv
, i
) {
13905 err_printf(m
, "Pipe [%d]:\n", i
);
13906 err_printf(m
, " Power: %s\n",
13907 error
->pipe
[i
].power_domain_on
? "on" : "off");
13908 err_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
13909 err_printf(m
, " STAT: %08x\n", error
->pipe
[i
].stat
);
13911 err_printf(m
, "Plane [%d]:\n", i
);
13912 err_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
13913 err_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
13914 if (INTEL_INFO(dev
)->gen
<= 3) {
13915 err_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
13916 err_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
13918 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
13919 err_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
13920 if (INTEL_INFO(dev
)->gen
>= 4) {
13921 err_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
13922 err_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
13925 err_printf(m
, "Cursor [%d]:\n", i
);
13926 err_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
13927 err_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
13928 err_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);
13931 for (i
= 0; i
< error
->num_transcoders
; i
++) {
13932 err_printf(m
, "CPU transcoder: %c\n",
13933 transcoder_name(error
->transcoder
[i
].cpu_transcoder
));
13934 err_printf(m
, " Power: %s\n",
13935 error
->transcoder
[i
].power_domain_on
? "on" : "off");
13936 err_printf(m
, " CONF: %08x\n", error
->transcoder
[i
].conf
);
13937 err_printf(m
, " HTOTAL: %08x\n", error
->transcoder
[i
].htotal
);
13938 err_printf(m
, " HBLANK: %08x\n", error
->transcoder
[i
].hblank
);
13939 err_printf(m
, " HSYNC: %08x\n", error
->transcoder
[i
].hsync
);
13940 err_printf(m
, " VTOTAL: %08x\n", error
->transcoder
[i
].vtotal
);
13941 err_printf(m
, " VBLANK: %08x\n", error
->transcoder
[i
].vblank
);
13942 err_printf(m
, " VSYNC: %08x\n", error
->transcoder
[i
].vsync
);
13946 void intel_modeset_preclose(struct drm_device
*dev
, struct drm_file
*file
)
13948 struct intel_crtc
*crtc
;
13950 for_each_intel_crtc(dev
, crtc
) {
13951 struct intel_unpin_work
*work
;
13953 spin_lock_irq(&dev
->event_lock
);
13955 work
= crtc
->unpin_work
;
13957 if (work
&& work
->event
&&
13958 work
->event
->base
.file_priv
== file
) {
13959 kfree(work
->event
);
13960 work
->event
= NULL
;
13963 spin_unlock_irq(&dev
->event_lock
);