2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
44 bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
);
45 static void intel_increase_pllclock(struct drm_crtc
*crtc
);
46 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
57 #define INTEL_P2_NUM 2
58 typedef struct intel_limit intel_limit_t
;
60 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
65 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
68 intel_pch_rawclk(struct drm_device
*dev
)
70 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
72 WARN_ON(!HAS_PCH_SPLIT(dev
));
74 return I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
;
77 static inline u32
/* units of 100MHz */
78 intel_fdi_link_freq(struct drm_device
*dev
)
81 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
82 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
87 static const intel_limit_t intel_limits_i8xx_dvo
= {
88 .dot
= { .min
= 25000, .max
= 350000 },
89 .vco
= { .min
= 930000, .max
= 1400000 },
90 .n
= { .min
= 3, .max
= 16 },
91 .m
= { .min
= 96, .max
= 140 },
92 .m1
= { .min
= 18, .max
= 26 },
93 .m2
= { .min
= 6, .max
= 16 },
94 .p
= { .min
= 4, .max
= 128 },
95 .p1
= { .min
= 2, .max
= 33 },
96 .p2
= { .dot_limit
= 165000,
97 .p2_slow
= 4, .p2_fast
= 2 },
100 static const intel_limit_t intel_limits_i8xx_lvds
= {
101 .dot
= { .min
= 25000, .max
= 350000 },
102 .vco
= { .min
= 930000, .max
= 1400000 },
103 .n
= { .min
= 3, .max
= 16 },
104 .m
= { .min
= 96, .max
= 140 },
105 .m1
= { .min
= 18, .max
= 26 },
106 .m2
= { .min
= 6, .max
= 16 },
107 .p
= { .min
= 4, .max
= 128 },
108 .p1
= { .min
= 1, .max
= 6 },
109 .p2
= { .dot_limit
= 165000,
110 .p2_slow
= 14, .p2_fast
= 7 },
113 static const intel_limit_t intel_limits_i9xx_sdvo
= {
114 .dot
= { .min
= 20000, .max
= 400000 },
115 .vco
= { .min
= 1400000, .max
= 2800000 },
116 .n
= { .min
= 1, .max
= 6 },
117 .m
= { .min
= 70, .max
= 120 },
118 .m1
= { .min
= 8, .max
= 18 },
119 .m2
= { .min
= 3, .max
= 7 },
120 .p
= { .min
= 5, .max
= 80 },
121 .p1
= { .min
= 1, .max
= 8 },
122 .p2
= { .dot_limit
= 200000,
123 .p2_slow
= 10, .p2_fast
= 5 },
126 static const intel_limit_t intel_limits_i9xx_lvds
= {
127 .dot
= { .min
= 20000, .max
= 400000 },
128 .vco
= { .min
= 1400000, .max
= 2800000 },
129 .n
= { .min
= 1, .max
= 6 },
130 .m
= { .min
= 70, .max
= 120 },
131 .m1
= { .min
= 8, .max
= 18 },
132 .m2
= { .min
= 3, .max
= 7 },
133 .p
= { .min
= 7, .max
= 98 },
134 .p1
= { .min
= 1, .max
= 8 },
135 .p2
= { .dot_limit
= 112000,
136 .p2_slow
= 14, .p2_fast
= 7 },
140 static const intel_limit_t intel_limits_g4x_sdvo
= {
141 .dot
= { .min
= 25000, .max
= 270000 },
142 .vco
= { .min
= 1750000, .max
= 3500000},
143 .n
= { .min
= 1, .max
= 4 },
144 .m
= { .min
= 104, .max
= 138 },
145 .m1
= { .min
= 17, .max
= 23 },
146 .m2
= { .min
= 5, .max
= 11 },
147 .p
= { .min
= 10, .max
= 30 },
148 .p1
= { .min
= 1, .max
= 3},
149 .p2
= { .dot_limit
= 270000,
155 static const intel_limit_t intel_limits_g4x_hdmi
= {
156 .dot
= { .min
= 22000, .max
= 400000 },
157 .vco
= { .min
= 1750000, .max
= 3500000},
158 .n
= { .min
= 1, .max
= 4 },
159 .m
= { .min
= 104, .max
= 138 },
160 .m1
= { .min
= 16, .max
= 23 },
161 .m2
= { .min
= 5, .max
= 11 },
162 .p
= { .min
= 5, .max
= 80 },
163 .p1
= { .min
= 1, .max
= 8},
164 .p2
= { .dot_limit
= 165000,
165 .p2_slow
= 10, .p2_fast
= 5 },
168 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
169 .dot
= { .min
= 20000, .max
= 115000 },
170 .vco
= { .min
= 1750000, .max
= 3500000 },
171 .n
= { .min
= 1, .max
= 3 },
172 .m
= { .min
= 104, .max
= 138 },
173 .m1
= { .min
= 17, .max
= 23 },
174 .m2
= { .min
= 5, .max
= 11 },
175 .p
= { .min
= 28, .max
= 112 },
176 .p1
= { .min
= 2, .max
= 8 },
177 .p2
= { .dot_limit
= 0,
178 .p2_slow
= 14, .p2_fast
= 14
182 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
183 .dot
= { .min
= 80000, .max
= 224000 },
184 .vco
= { .min
= 1750000, .max
= 3500000 },
185 .n
= { .min
= 1, .max
= 3 },
186 .m
= { .min
= 104, .max
= 138 },
187 .m1
= { .min
= 17, .max
= 23 },
188 .m2
= { .min
= 5, .max
= 11 },
189 .p
= { .min
= 14, .max
= 42 },
190 .p1
= { .min
= 2, .max
= 6 },
191 .p2
= { .dot_limit
= 0,
192 .p2_slow
= 7, .p2_fast
= 7
196 static const intel_limit_t intel_limits_pineview_sdvo
= {
197 .dot
= { .min
= 20000, .max
= 400000},
198 .vco
= { .min
= 1700000, .max
= 3500000 },
199 /* Pineview's Ncounter is a ring counter */
200 .n
= { .min
= 3, .max
= 6 },
201 .m
= { .min
= 2, .max
= 256 },
202 /* Pineview only has one combined m divider, which we treat as m2. */
203 .m1
= { .min
= 0, .max
= 0 },
204 .m2
= { .min
= 0, .max
= 254 },
205 .p
= { .min
= 5, .max
= 80 },
206 .p1
= { .min
= 1, .max
= 8 },
207 .p2
= { .dot_limit
= 200000,
208 .p2_slow
= 10, .p2_fast
= 5 },
211 static const intel_limit_t intel_limits_pineview_lvds
= {
212 .dot
= { .min
= 20000, .max
= 400000 },
213 .vco
= { .min
= 1700000, .max
= 3500000 },
214 .n
= { .min
= 3, .max
= 6 },
215 .m
= { .min
= 2, .max
= 256 },
216 .m1
= { .min
= 0, .max
= 0 },
217 .m2
= { .min
= 0, .max
= 254 },
218 .p
= { .min
= 7, .max
= 112 },
219 .p1
= { .min
= 1, .max
= 8 },
220 .p2
= { .dot_limit
= 112000,
221 .p2_slow
= 14, .p2_fast
= 14 },
224 /* Ironlake / Sandybridge
226 * We calculate clock using (register_value + 2) for N/M1/M2, so here
227 * the range value for them is (actual_value - 2).
229 static const intel_limit_t intel_limits_ironlake_dac
= {
230 .dot
= { .min
= 25000, .max
= 350000 },
231 .vco
= { .min
= 1760000, .max
= 3510000 },
232 .n
= { .min
= 1, .max
= 5 },
233 .m
= { .min
= 79, .max
= 127 },
234 .m1
= { .min
= 12, .max
= 22 },
235 .m2
= { .min
= 5, .max
= 9 },
236 .p
= { .min
= 5, .max
= 80 },
237 .p1
= { .min
= 1, .max
= 8 },
238 .p2
= { .dot_limit
= 225000,
239 .p2_slow
= 10, .p2_fast
= 5 },
242 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
243 .dot
= { .min
= 25000, .max
= 350000 },
244 .vco
= { .min
= 1760000, .max
= 3510000 },
245 .n
= { .min
= 1, .max
= 3 },
246 .m
= { .min
= 79, .max
= 118 },
247 .m1
= { .min
= 12, .max
= 22 },
248 .m2
= { .min
= 5, .max
= 9 },
249 .p
= { .min
= 28, .max
= 112 },
250 .p1
= { .min
= 2, .max
= 8 },
251 .p2
= { .dot_limit
= 225000,
252 .p2_slow
= 14, .p2_fast
= 14 },
255 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
256 .dot
= { .min
= 25000, .max
= 350000 },
257 .vco
= { .min
= 1760000, .max
= 3510000 },
258 .n
= { .min
= 1, .max
= 3 },
259 .m
= { .min
= 79, .max
= 127 },
260 .m1
= { .min
= 12, .max
= 22 },
261 .m2
= { .min
= 5, .max
= 9 },
262 .p
= { .min
= 14, .max
= 56 },
263 .p1
= { .min
= 2, .max
= 8 },
264 .p2
= { .dot_limit
= 225000,
265 .p2_slow
= 7, .p2_fast
= 7 },
268 /* LVDS 100mhz refclk limits. */
269 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
270 .dot
= { .min
= 25000, .max
= 350000 },
271 .vco
= { .min
= 1760000, .max
= 3510000 },
272 .n
= { .min
= 1, .max
= 2 },
273 .m
= { .min
= 79, .max
= 126 },
274 .m1
= { .min
= 12, .max
= 22 },
275 .m2
= { .min
= 5, .max
= 9 },
276 .p
= { .min
= 28, .max
= 112 },
277 .p1
= { .min
= 2, .max
= 8 },
278 .p2
= { .dot_limit
= 225000,
279 .p2_slow
= 14, .p2_fast
= 14 },
282 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
283 .dot
= { .min
= 25000, .max
= 350000 },
284 .vco
= { .min
= 1760000, .max
= 3510000 },
285 .n
= { .min
= 1, .max
= 3 },
286 .m
= { .min
= 79, .max
= 126 },
287 .m1
= { .min
= 12, .max
= 22 },
288 .m2
= { .min
= 5, .max
= 9 },
289 .p
= { .min
= 14, .max
= 42 },
290 .p1
= { .min
= 2, .max
= 6 },
291 .p2
= { .dot_limit
= 225000,
292 .p2_slow
= 7, .p2_fast
= 7 },
295 static const intel_limit_t intel_limits_vlv_dac
= {
296 .dot
= { .min
= 25000, .max
= 270000 },
297 .vco
= { .min
= 4000000, .max
= 6000000 },
298 .n
= { .min
= 1, .max
= 7 },
299 .m
= { .min
= 22, .max
= 450 }, /* guess */
300 .m1
= { .min
= 2, .max
= 3 },
301 .m2
= { .min
= 11, .max
= 156 },
302 .p
= { .min
= 10, .max
= 30 },
303 .p1
= { .min
= 1, .max
= 3 },
304 .p2
= { .dot_limit
= 270000,
305 .p2_slow
= 2, .p2_fast
= 20 },
308 static const intel_limit_t intel_limits_vlv_hdmi
= {
309 .dot
= { .min
= 25000, .max
= 270000 },
310 .vco
= { .min
= 4000000, .max
= 6000000 },
311 .n
= { .min
= 1, .max
= 7 },
312 .m
= { .min
= 60, .max
= 300 }, /* guess */
313 .m1
= { .min
= 2, .max
= 3 },
314 .m2
= { .min
= 11, .max
= 156 },
315 .p
= { .min
= 10, .max
= 30 },
316 .p1
= { .min
= 2, .max
= 3 },
317 .p2
= { .dot_limit
= 270000,
318 .p2_slow
= 2, .p2_fast
= 20 },
321 static const intel_limit_t intel_limits_vlv_dp
= {
322 .dot
= { .min
= 25000, .max
= 270000 },
323 .vco
= { .min
= 4000000, .max
= 6000000 },
324 .n
= { .min
= 1, .max
= 7 },
325 .m
= { .min
= 22, .max
= 450 },
326 .m1
= { .min
= 2, .max
= 3 },
327 .m2
= { .min
= 11, .max
= 156 },
328 .p
= { .min
= 10, .max
= 30 },
329 .p1
= { .min
= 1, .max
= 3 },
330 .p2
= { .dot_limit
= 270000,
331 .p2_slow
= 2, .p2_fast
= 20 },
334 static const intel_limit_t
*intel_ironlake_limit(struct drm_crtc
*crtc
,
337 struct drm_device
*dev
= crtc
->dev
;
338 const intel_limit_t
*limit
;
340 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
341 if (intel_is_dual_link_lvds(dev
)) {
342 if (refclk
== 100000)
343 limit
= &intel_limits_ironlake_dual_lvds_100m
;
345 limit
= &intel_limits_ironlake_dual_lvds
;
347 if (refclk
== 100000)
348 limit
= &intel_limits_ironlake_single_lvds_100m
;
350 limit
= &intel_limits_ironlake_single_lvds
;
353 limit
= &intel_limits_ironlake_dac
;
358 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
360 struct drm_device
*dev
= crtc
->dev
;
361 const intel_limit_t
*limit
;
363 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
364 if (intel_is_dual_link_lvds(dev
))
365 limit
= &intel_limits_g4x_dual_channel_lvds
;
367 limit
= &intel_limits_g4x_single_channel_lvds
;
368 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
369 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
370 limit
= &intel_limits_g4x_hdmi
;
371 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
372 limit
= &intel_limits_g4x_sdvo
;
373 } else /* The option is for other outputs */
374 limit
= &intel_limits_i9xx_sdvo
;
379 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
, int refclk
)
381 struct drm_device
*dev
= crtc
->dev
;
382 const intel_limit_t
*limit
;
384 if (HAS_PCH_SPLIT(dev
))
385 limit
= intel_ironlake_limit(crtc
, refclk
);
386 else if (IS_G4X(dev
)) {
387 limit
= intel_g4x_limit(crtc
);
388 } else if (IS_PINEVIEW(dev
)) {
389 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
390 limit
= &intel_limits_pineview_lvds
;
392 limit
= &intel_limits_pineview_sdvo
;
393 } else if (IS_VALLEYVIEW(dev
)) {
394 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
))
395 limit
= &intel_limits_vlv_dac
;
396 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
))
397 limit
= &intel_limits_vlv_hdmi
;
399 limit
= &intel_limits_vlv_dp
;
400 } else if (!IS_GEN2(dev
)) {
401 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
402 limit
= &intel_limits_i9xx_lvds
;
404 limit
= &intel_limits_i9xx_sdvo
;
406 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
407 limit
= &intel_limits_i8xx_lvds
;
409 limit
= &intel_limits_i8xx_dvo
;
414 /* m1 is reserved as 0 in Pineview, n is a ring counter */
415 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
417 clock
->m
= clock
->m2
+ 2;
418 clock
->p
= clock
->p1
* clock
->p2
;
419 clock
->vco
= refclk
* clock
->m
/ clock
->n
;
420 clock
->dot
= clock
->vco
/ clock
->p
;
423 static uint32_t i9xx_dpll_compute_m(struct dpll
*dpll
)
425 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
428 static void i9xx_clock(int refclk
, intel_clock_t
*clock
)
430 clock
->m
= i9xx_dpll_compute_m(clock
);
431 clock
->p
= clock
->p1
* clock
->p2
;
432 clock
->vco
= refclk
* clock
->m
/ (clock
->n
+ 2);
433 clock
->dot
= clock
->vco
/ clock
->p
;
437 * Returns whether any output on the specified pipe is of the specified type
439 bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
)
441 struct drm_device
*dev
= crtc
->dev
;
442 struct intel_encoder
*encoder
;
444 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
445 if (encoder
->type
== type
)
451 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
453 * Returns whether the given set of divisors are valid for a given refclk with
454 * the given connectors.
457 static bool intel_PLL_is_valid(struct drm_device
*dev
,
458 const intel_limit_t
*limit
,
459 const intel_clock_t
*clock
)
461 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
462 INTELPllInvalid("p1 out of range\n");
463 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
464 INTELPllInvalid("p out of range\n");
465 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
466 INTELPllInvalid("m2 out of range\n");
467 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
468 INTELPllInvalid("m1 out of range\n");
469 if (clock
->m1
<= clock
->m2
&& !IS_PINEVIEW(dev
))
470 INTELPllInvalid("m1 <= m2\n");
471 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
472 INTELPllInvalid("m out of range\n");
473 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
474 INTELPllInvalid("n out of range\n");
475 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
476 INTELPllInvalid("vco out of range\n");
477 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
478 * connector, etc., rather than just a single range.
480 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
481 INTELPllInvalid("dot out of range\n");
487 i9xx_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
488 int target
, int refclk
, intel_clock_t
*match_clock
,
489 intel_clock_t
*best_clock
)
491 struct drm_device
*dev
= crtc
->dev
;
495 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
497 * For LVDS just rely on its current settings for dual-channel.
498 * We haven't figured out how to reliably set up different
499 * single/dual channel state, if we even can.
501 if (intel_is_dual_link_lvds(dev
))
502 clock
.p2
= limit
->p2
.p2_fast
;
504 clock
.p2
= limit
->p2
.p2_slow
;
506 if (target
< limit
->p2
.dot_limit
)
507 clock
.p2
= limit
->p2
.p2_slow
;
509 clock
.p2
= limit
->p2
.p2_fast
;
512 memset(best_clock
, 0, sizeof(*best_clock
));
514 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
516 for (clock
.m2
= limit
->m2
.min
;
517 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
518 if (clock
.m2
>= clock
.m1
)
520 for (clock
.n
= limit
->n
.min
;
521 clock
.n
<= limit
->n
.max
; clock
.n
++) {
522 for (clock
.p1
= limit
->p1
.min
;
523 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
526 i9xx_clock(refclk
, &clock
);
527 if (!intel_PLL_is_valid(dev
, limit
,
531 clock
.p
!= match_clock
->p
)
534 this_err
= abs(clock
.dot
- target
);
535 if (this_err
< err
) {
544 return (err
!= target
);
548 pnv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
549 int target
, int refclk
, intel_clock_t
*match_clock
,
550 intel_clock_t
*best_clock
)
552 struct drm_device
*dev
= crtc
->dev
;
556 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
558 * For LVDS just rely on its current settings for dual-channel.
559 * We haven't figured out how to reliably set up different
560 * single/dual channel state, if we even can.
562 if (intel_is_dual_link_lvds(dev
))
563 clock
.p2
= limit
->p2
.p2_fast
;
565 clock
.p2
= limit
->p2
.p2_slow
;
567 if (target
< limit
->p2
.dot_limit
)
568 clock
.p2
= limit
->p2
.p2_slow
;
570 clock
.p2
= limit
->p2
.p2_fast
;
573 memset(best_clock
, 0, sizeof(*best_clock
));
575 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
577 for (clock
.m2
= limit
->m2
.min
;
578 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
579 for (clock
.n
= limit
->n
.min
;
580 clock
.n
<= limit
->n
.max
; clock
.n
++) {
581 for (clock
.p1
= limit
->p1
.min
;
582 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
585 pineview_clock(refclk
, &clock
);
586 if (!intel_PLL_is_valid(dev
, limit
,
590 clock
.p
!= match_clock
->p
)
593 this_err
= abs(clock
.dot
- target
);
594 if (this_err
< err
) {
603 return (err
!= target
);
607 g4x_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
608 int target
, int refclk
, intel_clock_t
*match_clock
,
609 intel_clock_t
*best_clock
)
611 struct drm_device
*dev
= crtc
->dev
;
615 /* approximately equals target * 0.00585 */
616 int err_most
= (target
>> 8) + (target
>> 9);
619 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
620 if (intel_is_dual_link_lvds(dev
))
621 clock
.p2
= limit
->p2
.p2_fast
;
623 clock
.p2
= limit
->p2
.p2_slow
;
625 if (target
< limit
->p2
.dot_limit
)
626 clock
.p2
= limit
->p2
.p2_slow
;
628 clock
.p2
= limit
->p2
.p2_fast
;
631 memset(best_clock
, 0, sizeof(*best_clock
));
632 max_n
= limit
->n
.max
;
633 /* based on hardware requirement, prefer smaller n to precision */
634 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
635 /* based on hardware requirement, prefere larger m1,m2 */
636 for (clock
.m1
= limit
->m1
.max
;
637 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
638 for (clock
.m2
= limit
->m2
.max
;
639 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
640 for (clock
.p1
= limit
->p1
.max
;
641 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
644 i9xx_clock(refclk
, &clock
);
645 if (!intel_PLL_is_valid(dev
, limit
,
649 this_err
= abs(clock
.dot
- target
);
650 if (this_err
< err_most
) {
664 vlv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
665 int target
, int refclk
, intel_clock_t
*match_clock
,
666 intel_clock_t
*best_clock
)
668 u32 p1
, p2
, m1
, m2
, vco
, bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
670 u32 updrate
, minupdate
, fracbits
, p
;
671 unsigned long bestppm
, ppm
, absppm
;
675 dotclk
= target
* 1000;
678 fastclk
= dotclk
/ (2*100);
682 n
= p
= p1
= p2
= m
= m1
= m2
= vco
= bestn
= 0;
683 bestm1
= bestm2
= bestp1
= bestp2
= 0;
685 /* based on hardware requirement, prefer smaller n to precision */
686 for (n
= limit
->n
.min
; n
<= ((refclk
) / minupdate
); n
++) {
687 updrate
= refclk
/ n
;
688 for (p1
= limit
->p1
.max
; p1
> limit
->p1
.min
; p1
--) {
689 for (p2
= limit
->p2
.p2_fast
+1; p2
> 0; p2
--) {
693 /* based on hardware requirement, prefer bigger m1,m2 values */
694 for (m1
= limit
->m1
.min
; m1
<= limit
->m1
.max
; m1
++) {
695 m2
= (((2*(fastclk
* p
* n
/ m1
)) +
696 refclk
) / (2*refclk
));
699 if (vco
>= limit
->vco
.min
&& vco
< limit
->vco
.max
) {
700 ppm
= 1000000 * ((vco
/ p
) - fastclk
) / fastclk
;
701 absppm
= (ppm
> 0) ? ppm
: (-ppm
);
702 if (absppm
< 100 && ((p1
* p2
) > (bestp1
* bestp2
))) {
706 if (absppm
< bestppm
- 10) {
723 best_clock
->n
= bestn
;
724 best_clock
->m1
= bestm1
;
725 best_clock
->m2
= bestm2
;
726 best_clock
->p1
= bestp1
;
727 best_clock
->p2
= bestp2
;
732 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
735 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
736 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
738 return intel_crtc
->config
.cpu_transcoder
;
741 static void ironlake_wait_for_vblank(struct drm_device
*dev
, int pipe
)
743 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
744 u32 frame
, frame_reg
= PIPEFRAME(pipe
);
746 frame
= I915_READ(frame_reg
);
748 if (wait_for(I915_READ_NOTRACE(frame_reg
) != frame
, 50))
749 DRM_DEBUG_KMS("vblank wait timed out\n");
753 * intel_wait_for_vblank - wait for vblank on a given pipe
755 * @pipe: pipe to wait for
757 * Wait for vblank to occur on a given pipe. Needed for various bits of
760 void intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
762 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
763 int pipestat_reg
= PIPESTAT(pipe
);
765 if (INTEL_INFO(dev
)->gen
>= 5) {
766 ironlake_wait_for_vblank(dev
, pipe
);
770 /* Clear existing vblank status. Note this will clear any other
771 * sticky status fields as well.
773 * This races with i915_driver_irq_handler() with the result
774 * that either function could miss a vblank event. Here it is not
775 * fatal, as we will either wait upon the next vblank interrupt or
776 * timeout. Generally speaking intel_wait_for_vblank() is only
777 * called during modeset at which time the GPU should be idle and
778 * should *not* be performing page flips and thus not waiting on
780 * Currently, the result of us stealing a vblank from the irq
781 * handler is that a single frame will be skipped during swapbuffers.
783 I915_WRITE(pipestat_reg
,
784 I915_READ(pipestat_reg
) | PIPE_VBLANK_INTERRUPT_STATUS
);
786 /* Wait for vblank interrupt bit to set */
787 if (wait_for(I915_READ(pipestat_reg
) &
788 PIPE_VBLANK_INTERRUPT_STATUS
,
790 DRM_DEBUG_KMS("vblank wait timed out\n");
794 * intel_wait_for_pipe_off - wait for pipe to turn off
796 * @pipe: pipe to wait for
798 * After disabling a pipe, we can't wait for vblank in the usual way,
799 * spinning on the vblank interrupt status bit, since we won't actually
800 * see an interrupt when the pipe is disabled.
803 * wait for the pipe register state bit to turn off
806 * wait for the display line value to settle (it usually
807 * ends up stopping at the start of the next frame).
810 void intel_wait_for_pipe_off(struct drm_device
*dev
, int pipe
)
812 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
813 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
816 if (INTEL_INFO(dev
)->gen
>= 4) {
817 int reg
= PIPECONF(cpu_transcoder
);
819 /* Wait for the Pipe State to go off */
820 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
822 WARN(1, "pipe_off wait timed out\n");
824 u32 last_line
, line_mask
;
825 int reg
= PIPEDSL(pipe
);
826 unsigned long timeout
= jiffies
+ msecs_to_jiffies(100);
829 line_mask
= DSL_LINEMASK_GEN2
;
831 line_mask
= DSL_LINEMASK_GEN3
;
833 /* Wait for the display line to settle */
835 last_line
= I915_READ(reg
) & line_mask
;
837 } while (((I915_READ(reg
) & line_mask
) != last_line
) &&
838 time_after(timeout
, jiffies
));
839 if (time_after(jiffies
, timeout
))
840 WARN(1, "pipe_off wait timed out\n");
845 * ibx_digital_port_connected - is the specified port connected?
846 * @dev_priv: i915 private structure
847 * @port: the port to test
849 * Returns true if @port is connected, false otherwise.
851 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
852 struct intel_digital_port
*port
)
856 if (HAS_PCH_IBX(dev_priv
->dev
)) {
859 bit
= SDE_PORTB_HOTPLUG
;
862 bit
= SDE_PORTC_HOTPLUG
;
865 bit
= SDE_PORTD_HOTPLUG
;
873 bit
= SDE_PORTB_HOTPLUG_CPT
;
876 bit
= SDE_PORTC_HOTPLUG_CPT
;
879 bit
= SDE_PORTD_HOTPLUG_CPT
;
886 return I915_READ(SDEISR
) & bit
;
889 static const char *state_string(bool enabled
)
891 return enabled
? "on" : "off";
894 /* Only for pre-ILK configs */
895 void assert_pll(struct drm_i915_private
*dev_priv
,
896 enum pipe pipe
, bool state
)
903 val
= I915_READ(reg
);
904 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
905 WARN(cur_state
!= state
,
906 "PLL state assertion failure (expected %s, current %s)\n",
907 state_string(state
), state_string(cur_state
));
910 struct intel_shared_dpll
*
911 intel_crtc_to_shared_dpll(struct intel_crtc
*crtc
)
913 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
915 if (crtc
->config
.shared_dpll
< 0)
918 return &dev_priv
->shared_dplls
[crtc
->config
.shared_dpll
];
922 void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
923 struct intel_shared_dpll
*pll
,
927 struct intel_dpll_hw_state hw_state
;
929 if (HAS_PCH_LPT(dev_priv
->dev
)) {
930 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
935 "asserting DPLL %s with no DPLL\n", state_string(state
)))
938 cur_state
= pll
->get_hw_state(dev_priv
, pll
, &hw_state
);
939 WARN(cur_state
!= state
,
940 "%s assertion failure (expected %s, current %s)\n",
941 pll
->name
, state_string(state
), state_string(cur_state
));
944 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
945 enum pipe pipe
, bool state
)
950 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
953 if (HAS_DDI(dev_priv
->dev
)) {
954 /* DDI does not have a specific FDI_TX register */
955 reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
956 val
= I915_READ(reg
);
957 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
959 reg
= FDI_TX_CTL(pipe
);
960 val
= I915_READ(reg
);
961 cur_state
= !!(val
& FDI_TX_ENABLE
);
963 WARN(cur_state
!= state
,
964 "FDI TX state assertion failure (expected %s, current %s)\n",
965 state_string(state
), state_string(cur_state
));
967 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
968 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
970 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
971 enum pipe pipe
, bool state
)
977 reg
= FDI_RX_CTL(pipe
);
978 val
= I915_READ(reg
);
979 cur_state
= !!(val
& FDI_RX_ENABLE
);
980 WARN(cur_state
!= state
,
981 "FDI RX state assertion failure (expected %s, current %s)\n",
982 state_string(state
), state_string(cur_state
));
984 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
985 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
987 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
993 /* ILK FDI PLL is always enabled */
994 if (dev_priv
->info
->gen
== 5)
997 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
998 if (HAS_DDI(dev_priv
->dev
))
1001 reg
= FDI_TX_CTL(pipe
);
1002 val
= I915_READ(reg
);
1003 WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1006 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1007 enum pipe pipe
, bool state
)
1013 reg
= FDI_RX_CTL(pipe
);
1014 val
= I915_READ(reg
);
1015 cur_state
= !!(val
& FDI_RX_PLL_ENABLE
);
1016 WARN(cur_state
!= state
,
1017 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1018 state_string(state
), state_string(cur_state
));
1021 static void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1024 int pp_reg
, lvds_reg
;
1026 enum pipe panel_pipe
= PIPE_A
;
1029 if (HAS_PCH_SPLIT(dev_priv
->dev
)) {
1030 pp_reg
= PCH_PP_CONTROL
;
1031 lvds_reg
= PCH_LVDS
;
1033 pp_reg
= PP_CONTROL
;
1037 val
= I915_READ(pp_reg
);
1038 if (!(val
& PANEL_POWER_ON
) ||
1039 ((val
& PANEL_UNLOCK_REGS
) == PANEL_UNLOCK_REGS
))
1042 if (I915_READ(lvds_reg
) & LVDS_PIPEB_SELECT
)
1043 panel_pipe
= PIPE_B
;
1045 WARN(panel_pipe
== pipe
&& locked
,
1046 "panel assertion failure, pipe %c regs locked\n",
1050 void assert_pipe(struct drm_i915_private
*dev_priv
,
1051 enum pipe pipe
, bool state
)
1056 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1059 /* if we need the pipe A quirk it must be always on */
1060 if (pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
1063 if (!intel_display_power_enabled(dev_priv
->dev
,
1064 POWER_DOMAIN_TRANSCODER(cpu_transcoder
))) {
1067 reg
= PIPECONF(cpu_transcoder
);
1068 val
= I915_READ(reg
);
1069 cur_state
= !!(val
& PIPECONF_ENABLE
);
1072 WARN(cur_state
!= state
,
1073 "pipe %c assertion failure (expected %s, current %s)\n",
1074 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1077 static void assert_plane(struct drm_i915_private
*dev_priv
,
1078 enum plane plane
, bool state
)
1084 reg
= DSPCNTR(plane
);
1085 val
= I915_READ(reg
);
1086 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1087 WARN(cur_state
!= state
,
1088 "plane %c assertion failure (expected %s, current %s)\n",
1089 plane_name(plane
), state_string(state
), state_string(cur_state
));
1092 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1093 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1095 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1098 struct drm_device
*dev
= dev_priv
->dev
;
1103 /* Primary planes are fixed to pipes on gen4+ */
1104 if (INTEL_INFO(dev
)->gen
>= 4) {
1105 reg
= DSPCNTR(pipe
);
1106 val
= I915_READ(reg
);
1107 WARN((val
& DISPLAY_PLANE_ENABLE
),
1108 "plane %c assertion failure, should be disabled but not\n",
1113 /* Need to check both planes against the pipe */
1114 for (i
= 0; i
< INTEL_INFO(dev
)->num_pipes
; i
++) {
1116 val
= I915_READ(reg
);
1117 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1118 DISPPLANE_SEL_PIPE_SHIFT
;
1119 WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1120 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1121 plane_name(i
), pipe_name(pipe
));
1125 static void assert_sprites_disabled(struct drm_i915_private
*dev_priv
,
1128 struct drm_device
*dev
= dev_priv
->dev
;
1132 if (IS_VALLEYVIEW(dev
)) {
1133 for (i
= 0; i
< dev_priv
->num_plane
; i
++) {
1134 reg
= SPCNTR(pipe
, i
);
1135 val
= I915_READ(reg
);
1136 WARN((val
& SP_ENABLE
),
1137 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1138 sprite_name(pipe
, i
), pipe_name(pipe
));
1140 } else if (INTEL_INFO(dev
)->gen
>= 7) {
1142 val
= I915_READ(reg
);
1143 WARN((val
& SPRITE_ENABLE
),
1144 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1145 plane_name(pipe
), pipe_name(pipe
));
1146 } else if (INTEL_INFO(dev
)->gen
>= 5) {
1147 reg
= DVSCNTR(pipe
);
1148 val
= I915_READ(reg
);
1149 WARN((val
& DVS_ENABLE
),
1150 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1151 plane_name(pipe
), pipe_name(pipe
));
1155 static void assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1160 if (HAS_PCH_LPT(dev_priv
->dev
)) {
1161 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1165 val
= I915_READ(PCH_DREF_CONTROL
);
1166 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1167 DREF_SUPERSPREAD_SOURCE_MASK
));
1168 WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1171 static void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1178 reg
= PCH_TRANSCONF(pipe
);
1179 val
= I915_READ(reg
);
1180 enabled
= !!(val
& TRANS_ENABLE
);
1182 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1186 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1187 enum pipe pipe
, u32 port_sel
, u32 val
)
1189 if ((val
& DP_PORT_EN
) == 0)
1192 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1193 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1194 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1195 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1198 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1204 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1205 enum pipe pipe
, u32 val
)
1207 if ((val
& SDVO_ENABLE
) == 0)
1210 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1211 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1214 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1220 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1221 enum pipe pipe
, u32 val
)
1223 if ((val
& LVDS_PORT_EN
) == 0)
1226 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1227 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1230 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1236 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1237 enum pipe pipe
, u32 val
)
1239 if ((val
& ADPA_DAC_ENABLE
) == 0)
1241 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1242 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1245 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1251 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1252 enum pipe pipe
, int reg
, u32 port_sel
)
1254 u32 val
= I915_READ(reg
);
1255 WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1256 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1257 reg
, pipe_name(pipe
));
1259 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& DP_PORT_EN
) == 0
1260 && (val
& DP_PIPEB_SELECT
),
1261 "IBX PCH dp port still using transcoder B\n");
1264 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1265 enum pipe pipe
, int reg
)
1267 u32 val
= I915_READ(reg
);
1268 WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1269 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1270 reg
, pipe_name(pipe
));
1272 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& SDVO_ENABLE
) == 0
1273 && (val
& SDVO_PIPE_B_SELECT
),
1274 "IBX PCH hdmi port still using transcoder B\n");
1277 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1283 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1284 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1285 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1288 val
= I915_READ(reg
);
1289 WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1290 "PCH VGA enabled on transcoder %c, should be disabled\n",
1294 val
= I915_READ(reg
);
1295 WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1296 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1299 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1300 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1301 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1304 static void vlv_enable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1309 assert_pipe_disabled(dev_priv
, pipe
);
1311 /* No really, not for ILK+ */
1312 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
));
1314 /* PLL is protected by panel, make sure we can write it */
1315 if (IS_MOBILE(dev_priv
->dev
) && !IS_I830(dev_priv
->dev
))
1316 assert_panel_unlocked(dev_priv
, pipe
);
1319 val
= I915_READ(reg
);
1320 val
|= DPLL_VCO_ENABLE
;
1322 /* We do this three times for luck */
1323 I915_WRITE(reg
, val
);
1325 udelay(150); /* wait for warmup */
1326 I915_WRITE(reg
, val
);
1328 udelay(150); /* wait for warmup */
1329 I915_WRITE(reg
, val
);
1331 udelay(150); /* wait for warmup */
1334 static void i9xx_enable_pll(struct intel_crtc
*crtc
)
1336 struct drm_device
*dev
= crtc
->base
.dev
;
1337 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1338 int reg
= DPLL(crtc
->pipe
);
1339 u32 dpll
= crtc
->config
.dpll_hw_state
.dpll
;
1341 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1343 /* No really, not for ILK+ */
1344 BUG_ON(dev_priv
->info
->gen
>= 5);
1346 /* PLL is protected by panel, make sure we can write it */
1347 if (IS_MOBILE(dev
) && !IS_I830(dev
))
1348 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1350 I915_WRITE(reg
, dpll
);
1352 /* Wait for the clocks to stabilize. */
1356 if (INTEL_INFO(dev
)->gen
>= 4) {
1357 I915_WRITE(DPLL_MD(crtc
->pipe
),
1358 crtc
->config
.dpll_hw_state
.dpll_md
);
1360 /* The pixel multiplier can only be updated once the
1361 * DPLL is enabled and the clocks are stable.
1363 * So write it again.
1365 I915_WRITE(reg
, dpll
);
1368 /* We do this three times for luck */
1369 I915_WRITE(reg
, dpll
);
1371 udelay(150); /* wait for warmup */
1372 I915_WRITE(reg
, dpll
);
1374 udelay(150); /* wait for warmup */
1375 I915_WRITE(reg
, dpll
);
1377 udelay(150); /* wait for warmup */
1381 * intel_disable_pll - disable a PLL
1382 * @dev_priv: i915 private structure
1383 * @pipe: pipe PLL to disable
1385 * Disable the PLL for @pipe, making sure the pipe is off first.
1387 * Note! This is for pre-ILK only.
1389 static void intel_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1394 /* Don't disable pipe A or pipe A PLLs if needed */
1395 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1398 /* Make sure the pipe isn't still relying on us */
1399 assert_pipe_disabled(dev_priv
, pipe
);
1402 val
= I915_READ(reg
);
1403 val
&= ~DPLL_VCO_ENABLE
;
1404 I915_WRITE(reg
, val
);
1408 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
, int port
)
1413 port_mask
= DPLL_PORTB_READY_MASK
;
1415 port_mask
= DPLL_PORTC_READY_MASK
;
1417 if (wait_for((I915_READ(DPLL(0)) & port_mask
) == 0, 1000))
1418 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1419 'B' + port
, I915_READ(DPLL(0)));
1423 * ironlake_enable_shared_dpll - enable PCH PLL
1424 * @dev_priv: i915 private structure
1425 * @pipe: pipe PLL to enable
1427 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1428 * drives the transcoder clock.
1430 static void ironlake_enable_shared_dpll(struct intel_crtc
*crtc
)
1432 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1433 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1435 /* PCH PLLs only available on ILK, SNB and IVB */
1436 BUG_ON(dev_priv
->info
->gen
< 5);
1437 if (WARN_ON(pll
== NULL
))
1440 if (WARN_ON(pll
->refcount
== 0))
1443 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1444 pll
->name
, pll
->active
, pll
->on
,
1445 crtc
->base
.base
.id
);
1447 if (pll
->active
++) {
1449 assert_shared_dpll_enabled(dev_priv
, pll
);
1454 DRM_DEBUG_KMS("enabling %s\n", pll
->name
);
1455 pll
->enable(dev_priv
, pll
);
1459 static void intel_disable_shared_dpll(struct intel_crtc
*crtc
)
1461 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1462 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1464 /* PCH only available on ILK+ */
1465 BUG_ON(dev_priv
->info
->gen
< 5);
1466 if (WARN_ON(pll
== NULL
))
1469 if (WARN_ON(pll
->refcount
== 0))
1472 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1473 pll
->name
, pll
->active
, pll
->on
,
1474 crtc
->base
.base
.id
);
1476 if (WARN_ON(pll
->active
== 0)) {
1477 assert_shared_dpll_disabled(dev_priv
, pll
);
1481 assert_shared_dpll_enabled(dev_priv
, pll
);
1486 DRM_DEBUG_KMS("disabling %s\n", pll
->name
);
1487 pll
->disable(dev_priv
, pll
);
1491 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1494 struct drm_device
*dev
= dev_priv
->dev
;
1495 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1496 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1497 uint32_t reg
, val
, pipeconf_val
;
1499 /* PCH only available on ILK+ */
1500 BUG_ON(dev_priv
->info
->gen
< 5);
1502 /* Make sure PCH DPLL is enabled */
1503 assert_shared_dpll_enabled(dev_priv
,
1504 intel_crtc_to_shared_dpll(intel_crtc
));
1506 /* FDI must be feeding us bits for PCH ports */
1507 assert_fdi_tx_enabled(dev_priv
, pipe
);
1508 assert_fdi_rx_enabled(dev_priv
, pipe
);
1510 if (HAS_PCH_CPT(dev
)) {
1511 /* Workaround: Set the timing override bit before enabling the
1512 * pch transcoder. */
1513 reg
= TRANS_CHICKEN2(pipe
);
1514 val
= I915_READ(reg
);
1515 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1516 I915_WRITE(reg
, val
);
1519 reg
= PCH_TRANSCONF(pipe
);
1520 val
= I915_READ(reg
);
1521 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1523 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1525 * make the BPC in transcoder be consistent with
1526 * that in pipeconf reg.
1528 val
&= ~PIPECONF_BPC_MASK
;
1529 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
1532 val
&= ~TRANS_INTERLACE_MASK
;
1533 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1534 if (HAS_PCH_IBX(dev_priv
->dev
) &&
1535 intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
))
1536 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1538 val
|= TRANS_INTERLACED
;
1540 val
|= TRANS_PROGRESSIVE
;
1542 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1543 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1544 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
1547 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1548 enum transcoder cpu_transcoder
)
1550 u32 val
, pipeconf_val
;
1552 /* PCH only available on ILK+ */
1553 BUG_ON(dev_priv
->info
->gen
< 5);
1555 /* FDI must be feeding us bits for PCH ports */
1556 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
1557 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
1559 /* Workaround: set timing override bit. */
1560 val
= I915_READ(_TRANSA_CHICKEN2
);
1561 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1562 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1565 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
1567 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
1568 PIPECONF_INTERLACED_ILK
)
1569 val
|= TRANS_INTERLACED
;
1571 val
|= TRANS_PROGRESSIVE
;
1573 I915_WRITE(LPT_TRANSCONF
, val
);
1574 if (wait_for(I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
, 100))
1575 DRM_ERROR("Failed to enable PCH transcoder\n");
1578 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1581 struct drm_device
*dev
= dev_priv
->dev
;
1584 /* FDI relies on the transcoder */
1585 assert_fdi_tx_disabled(dev_priv
, pipe
);
1586 assert_fdi_rx_disabled(dev_priv
, pipe
);
1588 /* Ports must be off as well */
1589 assert_pch_ports_disabled(dev_priv
, pipe
);
1591 reg
= PCH_TRANSCONF(pipe
);
1592 val
= I915_READ(reg
);
1593 val
&= ~TRANS_ENABLE
;
1594 I915_WRITE(reg
, val
);
1595 /* wait for PCH transcoder off, transcoder state */
1596 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
1597 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
1599 if (!HAS_PCH_IBX(dev
)) {
1600 /* Workaround: Clear the timing override chicken bit again. */
1601 reg
= TRANS_CHICKEN2(pipe
);
1602 val
= I915_READ(reg
);
1603 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1604 I915_WRITE(reg
, val
);
1608 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
1612 val
= I915_READ(LPT_TRANSCONF
);
1613 val
&= ~TRANS_ENABLE
;
1614 I915_WRITE(LPT_TRANSCONF
, val
);
1615 /* wait for PCH transcoder off, transcoder state */
1616 if (wait_for((I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
) == 0, 50))
1617 DRM_ERROR("Failed to disable PCH transcoder\n");
1619 /* Workaround: clear timing override bit. */
1620 val
= I915_READ(_TRANSA_CHICKEN2
);
1621 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1622 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1626 * intel_enable_pipe - enable a pipe, asserting requirements
1627 * @dev_priv: i915 private structure
1628 * @pipe: pipe to enable
1629 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1631 * Enable @pipe, making sure that various hardware specific requirements
1632 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1634 * @pipe should be %PIPE_A or %PIPE_B.
1636 * Will wait until the pipe is actually running (i.e. first vblank) before
1639 static void intel_enable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
1642 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1644 enum pipe pch_transcoder
;
1648 assert_planes_disabled(dev_priv
, pipe
);
1649 assert_sprites_disabled(dev_priv
, pipe
);
1651 if (HAS_PCH_LPT(dev_priv
->dev
))
1652 pch_transcoder
= TRANSCODER_A
;
1654 pch_transcoder
= pipe
;
1657 * A pipe without a PLL won't actually be able to drive bits from
1658 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1661 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
1662 assert_pll_enabled(dev_priv
, pipe
);
1665 /* if driving the PCH, we need FDI enabled */
1666 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
1667 assert_fdi_tx_pll_enabled(dev_priv
,
1668 (enum pipe
) cpu_transcoder
);
1670 /* FIXME: assert CPU port conditions for SNB+ */
1673 reg
= PIPECONF(cpu_transcoder
);
1674 val
= I915_READ(reg
);
1675 if (val
& PIPECONF_ENABLE
)
1678 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
1679 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1683 * intel_disable_pipe - disable a pipe, asserting requirements
1684 * @dev_priv: i915 private structure
1685 * @pipe: pipe to disable
1687 * Disable @pipe, making sure that various hardware specific requirements
1688 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1690 * @pipe should be %PIPE_A or %PIPE_B.
1692 * Will wait until the pipe has shut down before returning.
1694 static void intel_disable_pipe(struct drm_i915_private
*dev_priv
,
1697 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1703 * Make sure planes won't keep trying to pump pixels to us,
1704 * or we might hang the display.
1706 assert_planes_disabled(dev_priv
, pipe
);
1707 assert_sprites_disabled(dev_priv
, pipe
);
1709 /* Don't disable pipe A or pipe A PLLs if needed */
1710 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1713 reg
= PIPECONF(cpu_transcoder
);
1714 val
= I915_READ(reg
);
1715 if ((val
& PIPECONF_ENABLE
) == 0)
1718 I915_WRITE(reg
, val
& ~PIPECONF_ENABLE
);
1719 intel_wait_for_pipe_off(dev_priv
->dev
, pipe
);
1723 * Plane regs are double buffered, going from enabled->disabled needs a
1724 * trigger in order to latch. The display address reg provides this.
1726 void intel_flush_display_plane(struct drm_i915_private
*dev_priv
,
1729 if (dev_priv
->info
->gen
>= 4)
1730 I915_WRITE(DSPSURF(plane
), I915_READ(DSPSURF(plane
)));
1732 I915_WRITE(DSPADDR(plane
), I915_READ(DSPADDR(plane
)));
1736 * intel_enable_plane - enable a display plane on a given pipe
1737 * @dev_priv: i915 private structure
1738 * @plane: plane to enable
1739 * @pipe: pipe being fed
1741 * Enable @plane on @pipe, making sure that @pipe is running first.
1743 static void intel_enable_plane(struct drm_i915_private
*dev_priv
,
1744 enum plane plane
, enum pipe pipe
)
1749 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1750 assert_pipe_enabled(dev_priv
, pipe
);
1752 reg
= DSPCNTR(plane
);
1753 val
= I915_READ(reg
);
1754 if (val
& DISPLAY_PLANE_ENABLE
)
1757 I915_WRITE(reg
, val
| DISPLAY_PLANE_ENABLE
);
1758 intel_flush_display_plane(dev_priv
, plane
);
1759 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1763 * intel_disable_plane - disable a display plane
1764 * @dev_priv: i915 private structure
1765 * @plane: plane to disable
1766 * @pipe: pipe consuming the data
1768 * Disable @plane; should be an independent operation.
1770 static void intel_disable_plane(struct drm_i915_private
*dev_priv
,
1771 enum plane plane
, enum pipe pipe
)
1776 reg
= DSPCNTR(plane
);
1777 val
= I915_READ(reg
);
1778 if ((val
& DISPLAY_PLANE_ENABLE
) == 0)
1781 I915_WRITE(reg
, val
& ~DISPLAY_PLANE_ENABLE
);
1782 intel_flush_display_plane(dev_priv
, plane
);
1783 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1786 static bool need_vtd_wa(struct drm_device
*dev
)
1788 #ifdef CONFIG_INTEL_IOMMU
1789 if (INTEL_INFO(dev
)->gen
>= 6 && intel_iommu_gfx_mapped
)
1796 intel_pin_and_fence_fb_obj(struct drm_device
*dev
,
1797 struct drm_i915_gem_object
*obj
,
1798 struct intel_ring_buffer
*pipelined
)
1800 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1804 switch (obj
->tiling_mode
) {
1805 case I915_TILING_NONE
:
1806 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
1807 alignment
= 128 * 1024;
1808 else if (INTEL_INFO(dev
)->gen
>= 4)
1809 alignment
= 4 * 1024;
1811 alignment
= 64 * 1024;
1814 /* pin() will align the object as required by fence */
1818 /* Despite that we check this in framebuffer_init userspace can
1819 * screw us over and change the tiling after the fact. Only
1820 * pinned buffers can't change their tiling. */
1821 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1827 /* Note that the w/a also requires 64 PTE of padding following the
1828 * bo. We currently fill all unused PTE with the shadow page and so
1829 * we should always have valid PTE following the scanout preventing
1832 if (need_vtd_wa(dev
) && alignment
< 256 * 1024)
1833 alignment
= 256 * 1024;
1835 dev_priv
->mm
.interruptible
= false;
1836 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
);
1838 goto err_interruptible
;
1840 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1841 * fence, whereas 965+ only requires a fence if using
1842 * framebuffer compression. For simplicity, we always install
1843 * a fence as the cost is not that onerous.
1845 ret
= i915_gem_object_get_fence(obj
);
1849 i915_gem_object_pin_fence(obj
);
1851 dev_priv
->mm
.interruptible
= true;
1855 i915_gem_object_unpin(obj
);
1857 dev_priv
->mm
.interruptible
= true;
1861 void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
)
1863 i915_gem_object_unpin_fence(obj
);
1864 i915_gem_object_unpin(obj
);
1867 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1868 * is assumed to be a power-of-two. */
1869 unsigned long intel_gen4_compute_page_offset(int *x
, int *y
,
1870 unsigned int tiling_mode
,
1874 if (tiling_mode
!= I915_TILING_NONE
) {
1875 unsigned int tile_rows
, tiles
;
1880 tiles
= *x
/ (512/cpp
);
1883 return tile_rows
* pitch
* 8 + tiles
* 4096;
1885 unsigned int offset
;
1887 offset
= *y
* pitch
+ *x
* cpp
;
1889 *x
= (offset
& 4095) / cpp
;
1890 return offset
& -4096;
1894 static int i9xx_update_plane(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
1897 struct drm_device
*dev
= crtc
->dev
;
1898 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1899 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1900 struct intel_framebuffer
*intel_fb
;
1901 struct drm_i915_gem_object
*obj
;
1902 int plane
= intel_crtc
->plane
;
1903 unsigned long linear_offset
;
1912 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane
));
1916 intel_fb
= to_intel_framebuffer(fb
);
1917 obj
= intel_fb
->obj
;
1919 reg
= DSPCNTR(plane
);
1920 dspcntr
= I915_READ(reg
);
1921 /* Mask out pixel format bits in case we change it */
1922 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
1923 switch (fb
->pixel_format
) {
1925 dspcntr
|= DISPPLANE_8BPP
;
1927 case DRM_FORMAT_XRGB1555
:
1928 case DRM_FORMAT_ARGB1555
:
1929 dspcntr
|= DISPPLANE_BGRX555
;
1931 case DRM_FORMAT_RGB565
:
1932 dspcntr
|= DISPPLANE_BGRX565
;
1934 case DRM_FORMAT_XRGB8888
:
1935 case DRM_FORMAT_ARGB8888
:
1936 dspcntr
|= DISPPLANE_BGRX888
;
1938 case DRM_FORMAT_XBGR8888
:
1939 case DRM_FORMAT_ABGR8888
:
1940 dspcntr
|= DISPPLANE_RGBX888
;
1942 case DRM_FORMAT_XRGB2101010
:
1943 case DRM_FORMAT_ARGB2101010
:
1944 dspcntr
|= DISPPLANE_BGRX101010
;
1946 case DRM_FORMAT_XBGR2101010
:
1947 case DRM_FORMAT_ABGR2101010
:
1948 dspcntr
|= DISPPLANE_RGBX101010
;
1954 if (INTEL_INFO(dev
)->gen
>= 4) {
1955 if (obj
->tiling_mode
!= I915_TILING_NONE
)
1956 dspcntr
|= DISPPLANE_TILED
;
1958 dspcntr
&= ~DISPPLANE_TILED
;
1962 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
1964 I915_WRITE(reg
, dspcntr
);
1966 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
1968 if (INTEL_INFO(dev
)->gen
>= 4) {
1969 intel_crtc
->dspaddr_offset
=
1970 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
1971 fb
->bits_per_pixel
/ 8,
1973 linear_offset
-= intel_crtc
->dspaddr_offset
;
1975 intel_crtc
->dspaddr_offset
= linear_offset
;
1978 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
1979 obj
->gtt_offset
, linear_offset
, x
, y
, fb
->pitches
[0]);
1980 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
1981 if (INTEL_INFO(dev
)->gen
>= 4) {
1982 I915_MODIFY_DISPBASE(DSPSURF(plane
),
1983 obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
1984 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
1985 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
1987 I915_WRITE(DSPADDR(plane
), obj
->gtt_offset
+ linear_offset
);
1993 static int ironlake_update_plane(struct drm_crtc
*crtc
,
1994 struct drm_framebuffer
*fb
, int x
, int y
)
1996 struct drm_device
*dev
= crtc
->dev
;
1997 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1998 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1999 struct intel_framebuffer
*intel_fb
;
2000 struct drm_i915_gem_object
*obj
;
2001 int plane
= intel_crtc
->plane
;
2002 unsigned long linear_offset
;
2012 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane
));
2016 intel_fb
= to_intel_framebuffer(fb
);
2017 obj
= intel_fb
->obj
;
2019 reg
= DSPCNTR(plane
);
2020 dspcntr
= I915_READ(reg
);
2021 /* Mask out pixel format bits in case we change it */
2022 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2023 switch (fb
->pixel_format
) {
2025 dspcntr
|= DISPPLANE_8BPP
;
2027 case DRM_FORMAT_RGB565
:
2028 dspcntr
|= DISPPLANE_BGRX565
;
2030 case DRM_FORMAT_XRGB8888
:
2031 case DRM_FORMAT_ARGB8888
:
2032 dspcntr
|= DISPPLANE_BGRX888
;
2034 case DRM_FORMAT_XBGR8888
:
2035 case DRM_FORMAT_ABGR8888
:
2036 dspcntr
|= DISPPLANE_RGBX888
;
2038 case DRM_FORMAT_XRGB2101010
:
2039 case DRM_FORMAT_ARGB2101010
:
2040 dspcntr
|= DISPPLANE_BGRX101010
;
2042 case DRM_FORMAT_XBGR2101010
:
2043 case DRM_FORMAT_ABGR2101010
:
2044 dspcntr
|= DISPPLANE_RGBX101010
;
2050 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2051 dspcntr
|= DISPPLANE_TILED
;
2053 dspcntr
&= ~DISPPLANE_TILED
;
2056 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2058 I915_WRITE(reg
, dspcntr
);
2060 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2061 intel_crtc
->dspaddr_offset
=
2062 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2063 fb
->bits_per_pixel
/ 8,
2065 linear_offset
-= intel_crtc
->dspaddr_offset
;
2067 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2068 obj
->gtt_offset
, linear_offset
, x
, y
, fb
->pitches
[0]);
2069 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2070 I915_MODIFY_DISPBASE(DSPSURF(plane
),
2071 obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
2072 if (IS_HASWELL(dev
)) {
2073 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2075 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2076 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2083 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2085 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2086 int x
, int y
, enum mode_set_atomic state
)
2088 struct drm_device
*dev
= crtc
->dev
;
2089 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2091 if (dev_priv
->display
.disable_fbc
)
2092 dev_priv
->display
.disable_fbc(dev
);
2093 intel_increase_pllclock(crtc
);
2095 return dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2098 void intel_display_handle_reset(struct drm_device
*dev
)
2100 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2101 struct drm_crtc
*crtc
;
2104 * Flips in the rings have been nuked by the reset,
2105 * so complete all pending flips so that user space
2106 * will get its events and not get stuck.
2108 * Also update the base address of all primary
2109 * planes to the the last fb to make sure we're
2110 * showing the correct fb after a reset.
2112 * Need to make two loops over the crtcs so that we
2113 * don't try to grab a crtc mutex before the
2114 * pending_flip_queue really got woken up.
2117 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2118 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2119 enum plane plane
= intel_crtc
->plane
;
2121 intel_prepare_page_flip(dev
, plane
);
2122 intel_finish_page_flip_plane(dev
, plane
);
2125 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2126 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2128 mutex_lock(&crtc
->mutex
);
2129 if (intel_crtc
->active
)
2130 dev_priv
->display
.update_plane(crtc
, crtc
->fb
,
2132 mutex_unlock(&crtc
->mutex
);
2137 intel_finish_fb(struct drm_framebuffer
*old_fb
)
2139 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(old_fb
)->obj
;
2140 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2141 bool was_interruptible
= dev_priv
->mm
.interruptible
;
2144 /* Big Hammer, we also need to ensure that any pending
2145 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2146 * current scanout is retired before unpinning the old
2149 * This should only fail upon a hung GPU, in which case we
2150 * can safely continue.
2152 dev_priv
->mm
.interruptible
= false;
2153 ret
= i915_gem_object_finish_gpu(obj
);
2154 dev_priv
->mm
.interruptible
= was_interruptible
;
2159 static void intel_crtc_update_sarea_pos(struct drm_crtc
*crtc
, int x
, int y
)
2161 struct drm_device
*dev
= crtc
->dev
;
2162 struct drm_i915_master_private
*master_priv
;
2163 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2165 if (!dev
->primary
->master
)
2168 master_priv
= dev
->primary
->master
->driver_priv
;
2169 if (!master_priv
->sarea_priv
)
2172 switch (intel_crtc
->pipe
) {
2174 master_priv
->sarea_priv
->pipeA_x
= x
;
2175 master_priv
->sarea_priv
->pipeA_y
= y
;
2178 master_priv
->sarea_priv
->pipeB_x
= x
;
2179 master_priv
->sarea_priv
->pipeB_y
= y
;
2187 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2188 struct drm_framebuffer
*fb
)
2190 struct drm_device
*dev
= crtc
->dev
;
2191 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2192 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2193 struct drm_framebuffer
*old_fb
;
2198 DRM_ERROR("No FB bound\n");
2202 if (intel_crtc
->plane
> INTEL_INFO(dev
)->num_pipes
) {
2203 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2204 plane_name(intel_crtc
->plane
),
2205 INTEL_INFO(dev
)->num_pipes
);
2209 mutex_lock(&dev
->struct_mutex
);
2210 ret
= intel_pin_and_fence_fb_obj(dev
,
2211 to_intel_framebuffer(fb
)->obj
,
2214 mutex_unlock(&dev
->struct_mutex
);
2215 DRM_ERROR("pin & fence failed\n");
2219 ret
= dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2221 intel_unpin_fb_obj(to_intel_framebuffer(fb
)->obj
);
2222 mutex_unlock(&dev
->struct_mutex
);
2223 DRM_ERROR("failed to update base address\n");
2233 if (intel_crtc
->active
&& old_fb
!= fb
)
2234 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2235 intel_unpin_fb_obj(to_intel_framebuffer(old_fb
)->obj
);
2238 intel_update_fbc(dev
);
2239 mutex_unlock(&dev
->struct_mutex
);
2241 intel_crtc_update_sarea_pos(crtc
, x
, y
);
2246 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
2248 struct drm_device
*dev
= crtc
->dev
;
2249 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2250 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2251 int pipe
= intel_crtc
->pipe
;
2254 /* enable normal train */
2255 reg
= FDI_TX_CTL(pipe
);
2256 temp
= I915_READ(reg
);
2257 if (IS_IVYBRIDGE(dev
)) {
2258 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2259 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2261 temp
&= ~FDI_LINK_TRAIN_NONE
;
2262 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2264 I915_WRITE(reg
, temp
);
2266 reg
= FDI_RX_CTL(pipe
);
2267 temp
= I915_READ(reg
);
2268 if (HAS_PCH_CPT(dev
)) {
2269 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2270 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
2272 temp
&= ~FDI_LINK_TRAIN_NONE
;
2273 temp
|= FDI_LINK_TRAIN_NONE
;
2275 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
2277 /* wait one idle pattern time */
2281 /* IVB wants error correction enabled */
2282 if (IS_IVYBRIDGE(dev
))
2283 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
2284 FDI_FE_ERRC_ENABLE
);
2287 static bool pipe_has_enabled_pch(struct intel_crtc
*intel_crtc
)
2289 return intel_crtc
->base
.enabled
&& intel_crtc
->config
.has_pch_encoder
;
2292 static void ivb_modeset_global_resources(struct drm_device
*dev
)
2294 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2295 struct intel_crtc
*pipe_B_crtc
=
2296 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
2297 struct intel_crtc
*pipe_C_crtc
=
2298 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]);
2302 * When everything is off disable fdi C so that we could enable fdi B
2303 * with all lanes. Note that we don't care about enabled pipes without
2304 * an enabled pch encoder.
2306 if (!pipe_has_enabled_pch(pipe_B_crtc
) &&
2307 !pipe_has_enabled_pch(pipe_C_crtc
)) {
2308 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
2309 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
2311 temp
= I915_READ(SOUTH_CHICKEN1
);
2312 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
2313 DRM_DEBUG_KMS("disabling fdi C rx\n");
2314 I915_WRITE(SOUTH_CHICKEN1
, temp
);
2318 /* The FDI link training functions for ILK/Ibexpeak. */
2319 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
2321 struct drm_device
*dev
= crtc
->dev
;
2322 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2323 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2324 int pipe
= intel_crtc
->pipe
;
2325 int plane
= intel_crtc
->plane
;
2326 u32 reg
, temp
, tries
;
2328 /* FDI needs bits from pipe & plane first */
2329 assert_pipe_enabled(dev_priv
, pipe
);
2330 assert_plane_enabled(dev_priv
, plane
);
2332 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2334 reg
= FDI_RX_IMR(pipe
);
2335 temp
= I915_READ(reg
);
2336 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2337 temp
&= ~FDI_RX_BIT_LOCK
;
2338 I915_WRITE(reg
, temp
);
2342 /* enable CPU FDI TX and PCH FDI RX */
2343 reg
= FDI_TX_CTL(pipe
);
2344 temp
= I915_READ(reg
);
2345 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
2346 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2347 temp
&= ~FDI_LINK_TRAIN_NONE
;
2348 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2349 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2351 reg
= FDI_RX_CTL(pipe
);
2352 temp
= I915_READ(reg
);
2353 temp
&= ~FDI_LINK_TRAIN_NONE
;
2354 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2355 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2360 /* Ironlake workaround, enable clock pointer after FDI enable*/
2361 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2362 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
2363 FDI_RX_PHASE_SYNC_POINTER_EN
);
2365 reg
= FDI_RX_IIR(pipe
);
2366 for (tries
= 0; tries
< 5; tries
++) {
2367 temp
= I915_READ(reg
);
2368 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2370 if ((temp
& FDI_RX_BIT_LOCK
)) {
2371 DRM_DEBUG_KMS("FDI train 1 done.\n");
2372 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2377 DRM_ERROR("FDI train 1 fail!\n");
2380 reg
= FDI_TX_CTL(pipe
);
2381 temp
= I915_READ(reg
);
2382 temp
&= ~FDI_LINK_TRAIN_NONE
;
2383 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2384 I915_WRITE(reg
, temp
);
2386 reg
= FDI_RX_CTL(pipe
);
2387 temp
= I915_READ(reg
);
2388 temp
&= ~FDI_LINK_TRAIN_NONE
;
2389 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2390 I915_WRITE(reg
, temp
);
2395 reg
= FDI_RX_IIR(pipe
);
2396 for (tries
= 0; tries
< 5; tries
++) {
2397 temp
= I915_READ(reg
);
2398 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2400 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2401 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2402 DRM_DEBUG_KMS("FDI train 2 done.\n");
2407 DRM_ERROR("FDI train 2 fail!\n");
2409 DRM_DEBUG_KMS("FDI train done\n");
2413 static const int snb_b_fdi_train_param
[] = {
2414 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
2415 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
2416 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
2417 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
2420 /* The FDI link training functions for SNB/Cougarpoint. */
2421 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
2423 struct drm_device
*dev
= crtc
->dev
;
2424 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2425 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2426 int pipe
= intel_crtc
->pipe
;
2427 u32 reg
, temp
, i
, retry
;
2429 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2431 reg
= FDI_RX_IMR(pipe
);
2432 temp
= I915_READ(reg
);
2433 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2434 temp
&= ~FDI_RX_BIT_LOCK
;
2435 I915_WRITE(reg
, temp
);
2440 /* enable CPU FDI TX and PCH FDI RX */
2441 reg
= FDI_TX_CTL(pipe
);
2442 temp
= I915_READ(reg
);
2443 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
2444 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2445 temp
&= ~FDI_LINK_TRAIN_NONE
;
2446 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2447 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2449 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2450 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2452 I915_WRITE(FDI_RX_MISC(pipe
),
2453 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
2455 reg
= FDI_RX_CTL(pipe
);
2456 temp
= I915_READ(reg
);
2457 if (HAS_PCH_CPT(dev
)) {
2458 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2459 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2461 temp
&= ~FDI_LINK_TRAIN_NONE
;
2462 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2464 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2469 for (i
= 0; i
< 4; i
++) {
2470 reg
= FDI_TX_CTL(pipe
);
2471 temp
= I915_READ(reg
);
2472 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2473 temp
|= snb_b_fdi_train_param
[i
];
2474 I915_WRITE(reg
, temp
);
2479 for (retry
= 0; retry
< 5; retry
++) {
2480 reg
= FDI_RX_IIR(pipe
);
2481 temp
= I915_READ(reg
);
2482 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2483 if (temp
& FDI_RX_BIT_LOCK
) {
2484 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2485 DRM_DEBUG_KMS("FDI train 1 done.\n");
2494 DRM_ERROR("FDI train 1 fail!\n");
2497 reg
= FDI_TX_CTL(pipe
);
2498 temp
= I915_READ(reg
);
2499 temp
&= ~FDI_LINK_TRAIN_NONE
;
2500 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2502 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2504 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2506 I915_WRITE(reg
, temp
);
2508 reg
= FDI_RX_CTL(pipe
);
2509 temp
= I915_READ(reg
);
2510 if (HAS_PCH_CPT(dev
)) {
2511 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2512 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2514 temp
&= ~FDI_LINK_TRAIN_NONE
;
2515 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2517 I915_WRITE(reg
, temp
);
2522 for (i
= 0; i
< 4; i
++) {
2523 reg
= FDI_TX_CTL(pipe
);
2524 temp
= I915_READ(reg
);
2525 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2526 temp
|= snb_b_fdi_train_param
[i
];
2527 I915_WRITE(reg
, temp
);
2532 for (retry
= 0; retry
< 5; retry
++) {
2533 reg
= FDI_RX_IIR(pipe
);
2534 temp
= I915_READ(reg
);
2535 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2536 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2537 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2538 DRM_DEBUG_KMS("FDI train 2 done.\n");
2547 DRM_ERROR("FDI train 2 fail!\n");
2549 DRM_DEBUG_KMS("FDI train done.\n");
2552 /* Manual link training for Ivy Bridge A0 parts */
2553 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
2555 struct drm_device
*dev
= crtc
->dev
;
2556 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2557 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2558 int pipe
= intel_crtc
->pipe
;
2561 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2563 reg
= FDI_RX_IMR(pipe
);
2564 temp
= I915_READ(reg
);
2565 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2566 temp
&= ~FDI_RX_BIT_LOCK
;
2567 I915_WRITE(reg
, temp
);
2572 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2573 I915_READ(FDI_RX_IIR(pipe
)));
2575 /* enable CPU FDI TX and PCH FDI RX */
2576 reg
= FDI_TX_CTL(pipe
);
2577 temp
= I915_READ(reg
);
2578 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
2579 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2580 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
2581 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
2582 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2583 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2584 temp
|= FDI_COMPOSITE_SYNC
;
2585 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2587 I915_WRITE(FDI_RX_MISC(pipe
),
2588 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
2590 reg
= FDI_RX_CTL(pipe
);
2591 temp
= I915_READ(reg
);
2592 temp
&= ~FDI_LINK_TRAIN_AUTO
;
2593 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2594 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2595 temp
|= FDI_COMPOSITE_SYNC
;
2596 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2601 for (i
= 0; i
< 4; i
++) {
2602 reg
= FDI_TX_CTL(pipe
);
2603 temp
= I915_READ(reg
);
2604 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2605 temp
|= snb_b_fdi_train_param
[i
];
2606 I915_WRITE(reg
, temp
);
2611 reg
= FDI_RX_IIR(pipe
);
2612 temp
= I915_READ(reg
);
2613 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2615 if (temp
& FDI_RX_BIT_LOCK
||
2616 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
2617 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2618 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i
);
2623 DRM_ERROR("FDI train 1 fail!\n");
2626 reg
= FDI_TX_CTL(pipe
);
2627 temp
= I915_READ(reg
);
2628 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2629 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
2630 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2631 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2632 I915_WRITE(reg
, temp
);
2634 reg
= FDI_RX_CTL(pipe
);
2635 temp
= I915_READ(reg
);
2636 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2637 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2638 I915_WRITE(reg
, temp
);
2643 for (i
= 0; i
< 4; i
++) {
2644 reg
= FDI_TX_CTL(pipe
);
2645 temp
= I915_READ(reg
);
2646 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2647 temp
|= snb_b_fdi_train_param
[i
];
2648 I915_WRITE(reg
, temp
);
2653 reg
= FDI_RX_IIR(pipe
);
2654 temp
= I915_READ(reg
);
2655 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2657 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2658 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2659 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i
);
2664 DRM_ERROR("FDI train 2 fail!\n");
2666 DRM_DEBUG_KMS("FDI train done.\n");
2669 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
2671 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2672 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2673 int pipe
= intel_crtc
->pipe
;
2677 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2678 reg
= FDI_RX_CTL(pipe
);
2679 temp
= I915_READ(reg
);
2680 temp
&= ~(FDI_DP_PORT_WIDTH_MASK
| (0x7 << 16));
2681 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2682 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2683 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
2688 /* Switch from Rawclk to PCDclk */
2689 temp
= I915_READ(reg
);
2690 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
2695 /* Enable CPU FDI TX PLL, always on for Ironlake */
2696 reg
= FDI_TX_CTL(pipe
);
2697 temp
= I915_READ(reg
);
2698 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
2699 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
2706 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
2708 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2709 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2710 int pipe
= intel_crtc
->pipe
;
2713 /* Switch from PCDclk to Rawclk */
2714 reg
= FDI_RX_CTL(pipe
);
2715 temp
= I915_READ(reg
);
2716 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
2718 /* Disable CPU FDI TX PLL */
2719 reg
= FDI_TX_CTL(pipe
);
2720 temp
= I915_READ(reg
);
2721 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
2726 reg
= FDI_RX_CTL(pipe
);
2727 temp
= I915_READ(reg
);
2728 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
2730 /* Wait for the clocks to turn off. */
2735 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
2737 struct drm_device
*dev
= crtc
->dev
;
2738 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2739 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2740 int pipe
= intel_crtc
->pipe
;
2743 /* disable CPU FDI tx and PCH FDI rx */
2744 reg
= FDI_TX_CTL(pipe
);
2745 temp
= I915_READ(reg
);
2746 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
2749 reg
= FDI_RX_CTL(pipe
);
2750 temp
= I915_READ(reg
);
2751 temp
&= ~(0x7 << 16);
2752 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2753 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
2758 /* Ironlake workaround, disable clock pointer after downing FDI */
2759 if (HAS_PCH_IBX(dev
)) {
2760 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2763 /* still set train pattern 1 */
2764 reg
= FDI_TX_CTL(pipe
);
2765 temp
= I915_READ(reg
);
2766 temp
&= ~FDI_LINK_TRAIN_NONE
;
2767 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2768 I915_WRITE(reg
, temp
);
2770 reg
= FDI_RX_CTL(pipe
);
2771 temp
= I915_READ(reg
);
2772 if (HAS_PCH_CPT(dev
)) {
2773 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2774 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2776 temp
&= ~FDI_LINK_TRAIN_NONE
;
2777 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2779 /* BPC in FDI rx is consistent with that in PIPECONF */
2780 temp
&= ~(0x07 << 16);
2781 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2782 I915_WRITE(reg
, temp
);
2788 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
2790 struct drm_device
*dev
= crtc
->dev
;
2791 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2792 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2793 unsigned long flags
;
2796 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
2797 intel_crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
2800 spin_lock_irqsave(&dev
->event_lock
, flags
);
2801 pending
= to_intel_crtc(crtc
)->unpin_work
!= NULL
;
2802 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
2807 static void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
2809 struct drm_device
*dev
= crtc
->dev
;
2810 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2812 if (crtc
->fb
== NULL
)
2815 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
2817 wait_event(dev_priv
->pending_flip_queue
,
2818 !intel_crtc_has_pending_flip(crtc
));
2820 mutex_lock(&dev
->struct_mutex
);
2821 intel_finish_fb(crtc
->fb
);
2822 mutex_unlock(&dev
->struct_mutex
);
2825 /* Program iCLKIP clock to the desired frequency */
2826 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
2828 struct drm_device
*dev
= crtc
->dev
;
2829 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2830 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
2833 mutex_lock(&dev_priv
->dpio_lock
);
2835 /* It is necessary to ungate the pixclk gate prior to programming
2836 * the divisors, and gate it back when it is done.
2838 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
2840 /* Disable SSCCTL */
2841 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
2842 intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
) |
2846 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2847 if (crtc
->mode
.clock
== 20000) {
2852 /* The iCLK virtual clock root frequency is in MHz,
2853 * but the crtc->mode.clock in in KHz. To get the divisors,
2854 * it is necessary to divide one by another, so we
2855 * convert the virtual clock precision to KHz here for higher
2858 u32 iclk_virtual_root_freq
= 172800 * 1000;
2859 u32 iclk_pi_range
= 64;
2860 u32 desired_divisor
, msb_divisor_value
, pi_value
;
2862 desired_divisor
= (iclk_virtual_root_freq
/ crtc
->mode
.clock
);
2863 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
2864 pi_value
= desired_divisor
% iclk_pi_range
;
2867 divsel
= msb_divisor_value
- 2;
2868 phaseinc
= pi_value
;
2871 /* This should not happen with any sane values */
2872 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
2873 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
2874 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
2875 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
2877 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2884 /* Program SSCDIVINTPHASE6 */
2885 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
2886 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
2887 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
2888 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
2889 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
2890 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
2891 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
2892 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
2894 /* Program SSCAUXDIV */
2895 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
2896 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2897 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
2898 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
2900 /* Enable modulator and associated divider */
2901 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
2902 temp
&= ~SBI_SSCCTL_DISABLE
;
2903 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
2905 /* Wait for initialization time */
2908 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
2910 mutex_unlock(&dev_priv
->dpio_lock
);
2913 static void ironlake_pch_transcoder_set_timings(struct intel_crtc
*crtc
,
2914 enum pipe pch_transcoder
)
2916 struct drm_device
*dev
= crtc
->base
.dev
;
2917 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2918 enum transcoder cpu_transcoder
= crtc
->config
.cpu_transcoder
;
2920 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder
),
2921 I915_READ(HTOTAL(cpu_transcoder
)));
2922 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder
),
2923 I915_READ(HBLANK(cpu_transcoder
)));
2924 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder
),
2925 I915_READ(HSYNC(cpu_transcoder
)));
2927 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder
),
2928 I915_READ(VTOTAL(cpu_transcoder
)));
2929 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder
),
2930 I915_READ(VBLANK(cpu_transcoder
)));
2931 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder
),
2932 I915_READ(VSYNC(cpu_transcoder
)));
2933 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder
),
2934 I915_READ(VSYNCSHIFT(cpu_transcoder
)));
2938 * Enable PCH resources required for PCH ports:
2940 * - FDI training & RX/TX
2941 * - update transcoder timings
2942 * - DP transcoding bits
2945 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
2947 struct drm_device
*dev
= crtc
->dev
;
2948 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2949 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2950 int pipe
= intel_crtc
->pipe
;
2953 assert_pch_transcoder_disabled(dev_priv
, pipe
);
2955 /* Write the TU size bits before fdi link training, so that error
2956 * detection works. */
2957 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
2958 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
2960 /* For PCH output, training FDI link */
2961 dev_priv
->display
.fdi_link_train(crtc
);
2963 /* XXX: pch pll's can be enabled any time before we enable the PCH
2964 * transcoder, and we actually should do this to not upset any PCH
2965 * transcoder that already use the clock when we share it.
2967 * Note that enable_shared_dpll tries to do the right thing, but
2968 * get_shared_dpll unconditionally resets the pll - we need that to have
2969 * the right LVDS enable sequence. */
2970 ironlake_enable_shared_dpll(intel_crtc
);
2972 if (HAS_PCH_CPT(dev
)) {
2975 temp
= I915_READ(PCH_DPLL_SEL
);
2976 temp
|= TRANS_DPLL_ENABLE(pipe
);
2977 sel
= TRANS_DPLLB_SEL(pipe
);
2978 if (intel_crtc
->config
.shared_dpll
== DPLL_ID_PCH_PLL_B
)
2982 I915_WRITE(PCH_DPLL_SEL
, temp
);
2985 /* set transcoder timing, panel must allow it */
2986 assert_panel_unlocked(dev_priv
, pipe
);
2987 ironlake_pch_transcoder_set_timings(intel_crtc
, pipe
);
2989 intel_fdi_normal_train(crtc
);
2991 /* For PCH DP, enable TRANS_DP_CTL */
2992 if (HAS_PCH_CPT(dev
) &&
2993 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
2994 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
2995 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
2996 reg
= TRANS_DP_CTL(pipe
);
2997 temp
= I915_READ(reg
);
2998 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
2999 TRANS_DP_SYNC_MASK
|
3001 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
3002 TRANS_DP_ENH_FRAMING
);
3003 temp
|= bpc
<< 9; /* same format but at 11:9 */
3005 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
3006 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
3007 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
3008 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
3010 switch (intel_trans_dp_port_sel(crtc
)) {
3012 temp
|= TRANS_DP_PORT_SEL_B
;
3015 temp
|= TRANS_DP_PORT_SEL_C
;
3018 temp
|= TRANS_DP_PORT_SEL_D
;
3024 I915_WRITE(reg
, temp
);
3027 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
3030 static void lpt_pch_enable(struct drm_crtc
*crtc
)
3032 struct drm_device
*dev
= crtc
->dev
;
3033 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3034 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3035 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
3037 assert_pch_transcoder_disabled(dev_priv
, TRANSCODER_A
);
3039 lpt_program_iclkip(crtc
);
3041 /* Set transcoder timing. */
3042 ironlake_pch_transcoder_set_timings(intel_crtc
, PIPE_A
);
3044 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
3047 static void intel_put_shared_dpll(struct intel_crtc
*crtc
)
3049 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
3054 if (pll
->refcount
== 0) {
3055 WARN(1, "bad %s refcount\n", pll
->name
);
3059 if (--pll
->refcount
== 0) {
3061 WARN_ON(pll
->active
);
3064 crtc
->config
.shared_dpll
= DPLL_ID_PRIVATE
;
3067 static struct intel_shared_dpll
*intel_get_shared_dpll(struct intel_crtc
*crtc
)
3069 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
3070 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
3071 enum intel_dpll_id i
;
3074 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3075 crtc
->base
.base
.id
, pll
->name
);
3076 intel_put_shared_dpll(crtc
);
3079 if (HAS_PCH_IBX(dev_priv
->dev
)) {
3080 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3082 pll
= &dev_priv
->shared_dplls
[i
];
3084 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3085 crtc
->base
.base
.id
, pll
->name
);
3090 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3091 pll
= &dev_priv
->shared_dplls
[i
];
3093 /* Only want to check enabled timings first */
3094 if (pll
->refcount
== 0)
3097 if (memcmp(&crtc
->config
.dpll_hw_state
, &pll
->hw_state
,
3098 sizeof(pll
->hw_state
)) == 0) {
3099 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3101 pll
->name
, pll
->refcount
, pll
->active
);
3107 /* Ok no matching timings, maybe there's a free one? */
3108 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3109 pll
= &dev_priv
->shared_dplls
[i
];
3110 if (pll
->refcount
== 0) {
3111 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3112 crtc
->base
.base
.id
, pll
->name
);
3120 crtc
->config
.shared_dpll
= i
;
3121 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll
->name
,
3122 pipe_name(crtc
->pipe
));
3124 if (pll
->active
== 0) {
3125 memcpy(&pll
->hw_state
, &crtc
->config
.dpll_hw_state
,
3126 sizeof(pll
->hw_state
));
3128 DRM_DEBUG_DRIVER("setting up %s\n", pll
->name
);
3130 assert_shared_dpll_disabled(dev_priv
, pll
);
3132 pll
->mode_set(dev_priv
, pll
);
3139 static void cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
3141 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3142 int dslreg
= PIPEDSL(pipe
);
3145 temp
= I915_READ(dslreg
);
3147 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
3148 if (wait_for(I915_READ(dslreg
) != temp
, 5))
3149 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
3153 static void ironlake_pfit_enable(struct intel_crtc
*crtc
)
3155 struct drm_device
*dev
= crtc
->base
.dev
;
3156 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3157 int pipe
= crtc
->pipe
;
3159 if (crtc
->config
.pch_pfit
.size
) {
3160 /* Force use of hard-coded filter coefficients
3161 * as some pre-programmed values are broken,
3164 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
3165 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
3166 PF_PIPE_SEL_IVB(pipe
));
3168 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
3169 I915_WRITE(PF_WIN_POS(pipe
), crtc
->config
.pch_pfit
.pos
);
3170 I915_WRITE(PF_WIN_SZ(pipe
), crtc
->config
.pch_pfit
.size
);
3174 static void intel_enable_planes(struct drm_crtc
*crtc
)
3176 struct drm_device
*dev
= crtc
->dev
;
3177 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
3178 struct intel_plane
*intel_plane
;
3180 list_for_each_entry(intel_plane
, &dev
->mode_config
.plane_list
, base
.head
)
3181 if (intel_plane
->pipe
== pipe
)
3182 intel_plane_restore(&intel_plane
->base
);
3185 static void intel_disable_planes(struct drm_crtc
*crtc
)
3187 struct drm_device
*dev
= crtc
->dev
;
3188 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
3189 struct intel_plane
*intel_plane
;
3191 list_for_each_entry(intel_plane
, &dev
->mode_config
.plane_list
, base
.head
)
3192 if (intel_plane
->pipe
== pipe
)
3193 intel_plane_disable(&intel_plane
->base
);
3196 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
3198 struct drm_device
*dev
= crtc
->dev
;
3199 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3200 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3201 struct intel_encoder
*encoder
;
3202 int pipe
= intel_crtc
->pipe
;
3203 int plane
= intel_crtc
->plane
;
3205 WARN_ON(!crtc
->enabled
);
3207 if (intel_crtc
->active
)
3210 intel_crtc
->active
= true;
3212 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
3213 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, true);
3215 intel_update_watermarks(dev
);
3217 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
3218 if (encoder
->pre_pll_enable
)
3219 encoder
->pre_pll_enable(encoder
);
3220 if (encoder
->pre_enable
)
3221 encoder
->pre_enable(encoder
);
3224 if (intel_crtc
->config
.has_pch_encoder
) {
3225 /* Note: FDI PLL enabling _must_ be done before we enable the
3226 * cpu pipes, hence this is separate from all the other fdi/pch
3228 ironlake_fdi_pll_enable(intel_crtc
);
3230 assert_fdi_tx_disabled(dev_priv
, pipe
);
3231 assert_fdi_rx_disabled(dev_priv
, pipe
);
3234 ironlake_pfit_enable(intel_crtc
);
3237 * On ILK+ LUT must be loaded before the pipe is running but with
3240 intel_crtc_load_lut(crtc
);
3242 intel_enable_pipe(dev_priv
, pipe
,
3243 intel_crtc
->config
.has_pch_encoder
);
3244 intel_enable_plane(dev_priv
, plane
, pipe
);
3245 intel_enable_planes(crtc
);
3246 intel_crtc_update_cursor(crtc
, true);
3248 if (intel_crtc
->config
.has_pch_encoder
)
3249 ironlake_pch_enable(crtc
);
3251 mutex_lock(&dev
->struct_mutex
);
3252 intel_update_fbc(dev
);
3253 mutex_unlock(&dev
->struct_mutex
);
3255 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3256 encoder
->enable(encoder
);
3258 if (HAS_PCH_CPT(dev
))
3259 cpt_verify_modeset(dev
, intel_crtc
->pipe
);
3262 * There seems to be a race in PCH platform hw (at least on some
3263 * outputs) where an enabled pipe still completes any pageflip right
3264 * away (as if the pipe is off) instead of waiting for vblank. As soon
3265 * as the first vblank happend, everything works as expected. Hence just
3266 * wait for one vblank before returning to avoid strange things
3269 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3272 /* IPS only exists on ULT machines and is tied to pipe A. */
3273 static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc
)
3275 return HAS_IPS(crtc
->base
.dev
) && crtc
->pipe
== PIPE_A
;
3278 static void hsw_enable_ips(struct intel_crtc
*crtc
)
3280 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
3282 if (!crtc
->config
.ips_enabled
)
3285 /* We can only enable IPS after we enable a plane and wait for a vblank.
3286 * We guarantee that the plane is enabled by calling intel_enable_ips
3287 * only after intel_enable_plane. And intel_enable_plane already waits
3288 * for a vblank, so all we need to do here is to enable the IPS bit. */
3289 assert_plane_enabled(dev_priv
, crtc
->plane
);
3290 I915_WRITE(IPS_CTL
, IPS_ENABLE
);
3293 static void hsw_disable_ips(struct intel_crtc
*crtc
)
3295 struct drm_device
*dev
= crtc
->base
.dev
;
3296 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3298 if (!crtc
->config
.ips_enabled
)
3301 assert_plane_enabled(dev_priv
, crtc
->plane
);
3302 I915_WRITE(IPS_CTL
, 0);
3304 /* We need to wait for a vblank before we can disable the plane. */
3305 intel_wait_for_vblank(dev
, crtc
->pipe
);
3308 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
3310 struct drm_device
*dev
= crtc
->dev
;
3311 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3312 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3313 struct intel_encoder
*encoder
;
3314 int pipe
= intel_crtc
->pipe
;
3315 int plane
= intel_crtc
->plane
;
3317 WARN_ON(!crtc
->enabled
);
3319 if (intel_crtc
->active
)
3322 intel_crtc
->active
= true;
3324 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
3325 if (intel_crtc
->config
.has_pch_encoder
)
3326 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, true);
3328 intel_update_watermarks(dev
);
3330 if (intel_crtc
->config
.has_pch_encoder
)
3331 dev_priv
->display
.fdi_link_train(crtc
);
3333 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3334 if (encoder
->pre_enable
)
3335 encoder
->pre_enable(encoder
);
3337 intel_ddi_enable_pipe_clock(intel_crtc
);
3339 ironlake_pfit_enable(intel_crtc
);
3342 * On ILK+ LUT must be loaded before the pipe is running but with
3345 intel_crtc_load_lut(crtc
);
3347 intel_ddi_set_pipe_settings(crtc
);
3348 intel_ddi_enable_transcoder_func(crtc
);
3350 intel_enable_pipe(dev_priv
, pipe
,
3351 intel_crtc
->config
.has_pch_encoder
);
3352 intel_enable_plane(dev_priv
, plane
, pipe
);
3353 intel_enable_planes(crtc
);
3354 intel_crtc_update_cursor(crtc
, true);
3356 hsw_enable_ips(intel_crtc
);
3358 if (intel_crtc
->config
.has_pch_encoder
)
3359 lpt_pch_enable(crtc
);
3361 mutex_lock(&dev
->struct_mutex
);
3362 intel_update_fbc(dev
);
3363 mutex_unlock(&dev
->struct_mutex
);
3365 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3366 encoder
->enable(encoder
);
3369 * There seems to be a race in PCH platform hw (at least on some
3370 * outputs) where an enabled pipe still completes any pageflip right
3371 * away (as if the pipe is off) instead of waiting for vblank. As soon
3372 * as the first vblank happend, everything works as expected. Hence just
3373 * wait for one vblank before returning to avoid strange things
3376 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3379 static void ironlake_pfit_disable(struct intel_crtc
*crtc
)
3381 struct drm_device
*dev
= crtc
->base
.dev
;
3382 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3383 int pipe
= crtc
->pipe
;
3385 /* To avoid upsetting the power well on haswell only disable the pfit if
3386 * it's in use. The hw state code will make sure we get this right. */
3387 if (crtc
->config
.pch_pfit
.size
) {
3388 I915_WRITE(PF_CTL(pipe
), 0);
3389 I915_WRITE(PF_WIN_POS(pipe
), 0);
3390 I915_WRITE(PF_WIN_SZ(pipe
), 0);
3394 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
3396 struct drm_device
*dev
= crtc
->dev
;
3397 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3398 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3399 struct intel_encoder
*encoder
;
3400 int pipe
= intel_crtc
->pipe
;
3401 int plane
= intel_crtc
->plane
;
3405 if (!intel_crtc
->active
)
3408 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3409 encoder
->disable(encoder
);
3411 intel_crtc_wait_for_pending_flips(crtc
);
3412 drm_vblank_off(dev
, pipe
);
3414 if (dev_priv
->cfb_plane
== plane
)
3415 intel_disable_fbc(dev
);
3417 intel_crtc_update_cursor(crtc
, false);
3418 intel_disable_planes(crtc
);
3419 intel_disable_plane(dev_priv
, plane
, pipe
);
3421 if (intel_crtc
->config
.has_pch_encoder
)
3422 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, false);
3424 intel_disable_pipe(dev_priv
, pipe
);
3426 ironlake_pfit_disable(intel_crtc
);
3428 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3429 if (encoder
->post_disable
)
3430 encoder
->post_disable(encoder
);
3432 if (intel_crtc
->config
.has_pch_encoder
) {
3433 ironlake_fdi_disable(crtc
);
3435 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
3436 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, true);
3438 if (HAS_PCH_CPT(dev
)) {
3439 /* disable TRANS_DP_CTL */
3440 reg
= TRANS_DP_CTL(pipe
);
3441 temp
= I915_READ(reg
);
3442 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
|
3443 TRANS_DP_PORT_SEL_MASK
);
3444 temp
|= TRANS_DP_PORT_SEL_NONE
;
3445 I915_WRITE(reg
, temp
);
3447 /* disable DPLL_SEL */
3448 temp
= I915_READ(PCH_DPLL_SEL
);
3449 temp
&= ~(TRANS_DPLL_ENABLE(pipe
) | TRANS_DPLLB_SEL(pipe
));
3450 I915_WRITE(PCH_DPLL_SEL
, temp
);
3453 /* disable PCH DPLL */
3454 intel_disable_shared_dpll(intel_crtc
);
3456 ironlake_fdi_pll_disable(intel_crtc
);
3459 intel_crtc
->active
= false;
3460 intel_update_watermarks(dev
);
3462 mutex_lock(&dev
->struct_mutex
);
3463 intel_update_fbc(dev
);
3464 mutex_unlock(&dev
->struct_mutex
);
3467 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
3469 struct drm_device
*dev
= crtc
->dev
;
3470 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3471 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3472 struct intel_encoder
*encoder
;
3473 int pipe
= intel_crtc
->pipe
;
3474 int plane
= intel_crtc
->plane
;
3475 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
3477 if (!intel_crtc
->active
)
3480 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3481 encoder
->disable(encoder
);
3483 intel_crtc_wait_for_pending_flips(crtc
);
3484 drm_vblank_off(dev
, pipe
);
3486 /* FBC must be disabled before disabling the plane on HSW. */
3487 if (dev_priv
->cfb_plane
== plane
)
3488 intel_disable_fbc(dev
);
3490 hsw_disable_ips(intel_crtc
);
3492 intel_crtc_update_cursor(crtc
, false);
3493 intel_disable_planes(crtc
);
3494 intel_disable_plane(dev_priv
, plane
, pipe
);
3496 if (intel_crtc
->config
.has_pch_encoder
)
3497 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, false);
3498 intel_disable_pipe(dev_priv
, pipe
);
3500 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
3502 ironlake_pfit_disable(intel_crtc
);
3504 intel_ddi_disable_pipe_clock(intel_crtc
);
3506 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3507 if (encoder
->post_disable
)
3508 encoder
->post_disable(encoder
);
3510 if (intel_crtc
->config
.has_pch_encoder
) {
3511 lpt_disable_pch_transcoder(dev_priv
);
3512 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, true);
3513 intel_ddi_fdi_disable(crtc
);
3516 intel_crtc
->active
= false;
3517 intel_update_watermarks(dev
);
3519 mutex_lock(&dev
->struct_mutex
);
3520 intel_update_fbc(dev
);
3521 mutex_unlock(&dev
->struct_mutex
);
3524 static void ironlake_crtc_off(struct drm_crtc
*crtc
)
3526 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3527 intel_put_shared_dpll(intel_crtc
);
3530 static void haswell_crtc_off(struct drm_crtc
*crtc
)
3532 intel_ddi_put_crtc_pll(crtc
);
3535 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
3537 if (!enable
&& intel_crtc
->overlay
) {
3538 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3539 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3541 mutex_lock(&dev
->struct_mutex
);
3542 dev_priv
->mm
.interruptible
= false;
3543 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
3544 dev_priv
->mm
.interruptible
= true;
3545 mutex_unlock(&dev
->struct_mutex
);
3548 /* Let userspace switch the overlay on again. In most cases userspace
3549 * has to recompute where to put it anyway.
3554 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3555 * cursor plane briefly if not already running after enabling the display
3557 * This workaround avoids occasional blank screens when self refresh is
3561 g4x_fixup_plane(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
3563 u32 cntl
= I915_READ(CURCNTR(pipe
));
3565 if ((cntl
& CURSOR_MODE
) == 0) {
3566 u32 fw_bcl_self
= I915_READ(FW_BLC_SELF
);
3568 I915_WRITE(FW_BLC_SELF
, fw_bcl_self
& ~FW_BLC_SELF_EN
);
3569 I915_WRITE(CURCNTR(pipe
), CURSOR_MODE_64_ARGB_AX
);
3570 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
3571 I915_WRITE(CURCNTR(pipe
), cntl
);
3572 I915_WRITE(CURBASE(pipe
), I915_READ(CURBASE(pipe
)));
3573 I915_WRITE(FW_BLC_SELF
, fw_bcl_self
);
3577 static void i9xx_pfit_enable(struct intel_crtc
*crtc
)
3579 struct drm_device
*dev
= crtc
->base
.dev
;
3580 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3581 struct intel_crtc_config
*pipe_config
= &crtc
->config
;
3583 if (!crtc
->config
.gmch_pfit
.control
)
3587 * The panel fitter should only be adjusted whilst the pipe is disabled,
3588 * according to register description and PRM.
3590 WARN_ON(I915_READ(PFIT_CONTROL
) & PFIT_ENABLE
);
3591 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
3593 I915_WRITE(PFIT_PGM_RATIOS
, pipe_config
->gmch_pfit
.pgm_ratios
);
3594 I915_WRITE(PFIT_CONTROL
, pipe_config
->gmch_pfit
.control
);
3596 /* Border color in case we don't scale up to the full screen. Black by
3597 * default, change to something else for debugging. */
3598 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
3601 static void valleyview_crtc_enable(struct drm_crtc
*crtc
)
3603 struct drm_device
*dev
= crtc
->dev
;
3604 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3605 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3606 struct intel_encoder
*encoder
;
3607 int pipe
= intel_crtc
->pipe
;
3608 int plane
= intel_crtc
->plane
;
3610 WARN_ON(!crtc
->enabled
);
3612 if (intel_crtc
->active
)
3615 intel_crtc
->active
= true;
3616 intel_update_watermarks(dev
);
3618 mutex_lock(&dev_priv
->dpio_lock
);
3620 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3621 if (encoder
->pre_pll_enable
)
3622 encoder
->pre_pll_enable(encoder
);
3624 vlv_enable_pll(dev_priv
, pipe
);
3626 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3627 if (encoder
->pre_enable
)
3628 encoder
->pre_enable(encoder
);
3630 /* VLV wants encoder enabling _before_ the pipe is up. */
3631 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3632 encoder
->enable(encoder
);
3634 i9xx_pfit_enable(intel_crtc
);
3636 intel_crtc_load_lut(crtc
);
3638 intel_enable_pipe(dev_priv
, pipe
, false);
3639 intel_enable_plane(dev_priv
, plane
, pipe
);
3640 intel_enable_planes(crtc
);
3641 intel_crtc_update_cursor(crtc
, true);
3643 intel_update_fbc(dev
);
3645 mutex_unlock(&dev_priv
->dpio_lock
);
3648 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
3650 struct drm_device
*dev
= crtc
->dev
;
3651 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3652 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3653 struct intel_encoder
*encoder
;
3654 int pipe
= intel_crtc
->pipe
;
3655 int plane
= intel_crtc
->plane
;
3657 WARN_ON(!crtc
->enabled
);
3659 if (intel_crtc
->active
)
3662 intel_crtc
->active
= true;
3663 intel_update_watermarks(dev
);
3665 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3666 if (encoder
->pre_pll_enable
)
3667 encoder
->pre_pll_enable(encoder
);
3669 i9xx_enable_pll(intel_crtc
);
3671 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3672 if (encoder
->pre_enable
)
3673 encoder
->pre_enable(encoder
);
3675 i9xx_pfit_enable(intel_crtc
);
3677 intel_crtc_load_lut(crtc
);
3679 intel_enable_pipe(dev_priv
, pipe
, false);
3680 intel_enable_plane(dev_priv
, plane
, pipe
);
3681 intel_enable_planes(crtc
);
3682 /* The fixup needs to happen before cursor is enabled */
3684 g4x_fixup_plane(dev_priv
, pipe
);
3685 intel_crtc_update_cursor(crtc
, true);
3687 /* Give the overlay scaler a chance to enable if it's on this pipe */
3688 intel_crtc_dpms_overlay(intel_crtc
, true);
3690 intel_update_fbc(dev
);
3692 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3693 encoder
->enable(encoder
);
3696 static void i9xx_pfit_disable(struct intel_crtc
*crtc
)
3698 struct drm_device
*dev
= crtc
->base
.dev
;
3699 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3701 if (!crtc
->config
.gmch_pfit
.control
)
3704 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
3706 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3707 I915_READ(PFIT_CONTROL
));
3708 I915_WRITE(PFIT_CONTROL
, 0);
3711 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
3713 struct drm_device
*dev
= crtc
->dev
;
3714 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3715 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3716 struct intel_encoder
*encoder
;
3717 int pipe
= intel_crtc
->pipe
;
3718 int plane
= intel_crtc
->plane
;
3720 if (!intel_crtc
->active
)
3723 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3724 encoder
->disable(encoder
);
3726 /* Give the overlay scaler a chance to disable if it's on this pipe */
3727 intel_crtc_wait_for_pending_flips(crtc
);
3728 drm_vblank_off(dev
, pipe
);
3730 if (dev_priv
->cfb_plane
== plane
)
3731 intel_disable_fbc(dev
);
3733 intel_crtc_dpms_overlay(intel_crtc
, false);
3734 intel_crtc_update_cursor(crtc
, false);
3735 intel_disable_planes(crtc
);
3736 intel_disable_plane(dev_priv
, plane
, pipe
);
3738 intel_disable_pipe(dev_priv
, pipe
);
3740 i9xx_pfit_disable(intel_crtc
);
3742 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3743 if (encoder
->post_disable
)
3744 encoder
->post_disable(encoder
);
3746 intel_disable_pll(dev_priv
, pipe
);
3748 intel_crtc
->active
= false;
3749 intel_update_fbc(dev
);
3750 intel_update_watermarks(dev
);
3753 static void i9xx_crtc_off(struct drm_crtc
*crtc
)
3757 static void intel_crtc_update_sarea(struct drm_crtc
*crtc
,
3760 struct drm_device
*dev
= crtc
->dev
;
3761 struct drm_i915_master_private
*master_priv
;
3762 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3763 int pipe
= intel_crtc
->pipe
;
3765 if (!dev
->primary
->master
)
3768 master_priv
= dev
->primary
->master
->driver_priv
;
3769 if (!master_priv
->sarea_priv
)
3774 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3775 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3778 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3779 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3782 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe
));
3788 * Sets the power management mode of the pipe and plane.
3790 void intel_crtc_update_dpms(struct drm_crtc
*crtc
)
3792 struct drm_device
*dev
= crtc
->dev
;
3793 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3794 struct intel_encoder
*intel_encoder
;
3795 bool enable
= false;
3797 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
3798 enable
|= intel_encoder
->connectors_active
;
3801 dev_priv
->display
.crtc_enable(crtc
);
3803 dev_priv
->display
.crtc_disable(crtc
);
3805 intel_crtc_update_sarea(crtc
, enable
);
3808 static void intel_crtc_disable(struct drm_crtc
*crtc
)
3810 struct drm_device
*dev
= crtc
->dev
;
3811 struct drm_connector
*connector
;
3812 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3813 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3815 /* crtc should still be enabled when we disable it. */
3816 WARN_ON(!crtc
->enabled
);
3818 dev_priv
->display
.crtc_disable(crtc
);
3819 intel_crtc
->eld_vld
= false;
3820 intel_crtc_update_sarea(crtc
, false);
3821 dev_priv
->display
.off(crtc
);
3823 assert_plane_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->plane
);
3824 assert_pipe_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->pipe
);
3827 mutex_lock(&dev
->struct_mutex
);
3828 intel_unpin_fb_obj(to_intel_framebuffer(crtc
->fb
)->obj
);
3829 mutex_unlock(&dev
->struct_mutex
);
3833 /* Update computed state. */
3834 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
3835 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
3838 if (connector
->encoder
->crtc
!= crtc
)
3841 connector
->dpms
= DRM_MODE_DPMS_OFF
;
3842 to_intel_encoder(connector
->encoder
)->connectors_active
= false;
3846 void intel_modeset_disable(struct drm_device
*dev
)
3848 struct drm_crtc
*crtc
;
3850 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
3852 intel_crtc_disable(crtc
);
3856 void intel_encoder_destroy(struct drm_encoder
*encoder
)
3858 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
3860 drm_encoder_cleanup(encoder
);
3861 kfree(intel_encoder
);
3864 /* Simple dpms helper for encodres with just one connector, no cloning and only
3865 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3866 * state of the entire output pipe. */
3867 void intel_encoder_dpms(struct intel_encoder
*encoder
, int mode
)
3869 if (mode
== DRM_MODE_DPMS_ON
) {
3870 encoder
->connectors_active
= true;
3872 intel_crtc_update_dpms(encoder
->base
.crtc
);
3874 encoder
->connectors_active
= false;
3876 intel_crtc_update_dpms(encoder
->base
.crtc
);
3880 /* Cross check the actual hw state with our own modeset state tracking (and it's
3881 * internal consistency). */
3882 static void intel_connector_check_state(struct intel_connector
*connector
)
3884 if (connector
->get_hw_state(connector
)) {
3885 struct intel_encoder
*encoder
= connector
->encoder
;
3886 struct drm_crtc
*crtc
;
3887 bool encoder_enabled
;
3890 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3891 connector
->base
.base
.id
,
3892 drm_get_connector_name(&connector
->base
));
3894 WARN(connector
->base
.dpms
== DRM_MODE_DPMS_OFF
,
3895 "wrong connector dpms state\n");
3896 WARN(connector
->base
.encoder
!= &encoder
->base
,
3897 "active connector not linked to encoder\n");
3898 WARN(!encoder
->connectors_active
,
3899 "encoder->connectors_active not set\n");
3901 encoder_enabled
= encoder
->get_hw_state(encoder
, &pipe
);
3902 WARN(!encoder_enabled
, "encoder not enabled\n");
3903 if (WARN_ON(!encoder
->base
.crtc
))
3906 crtc
= encoder
->base
.crtc
;
3908 WARN(!crtc
->enabled
, "crtc not enabled\n");
3909 WARN(!to_intel_crtc(crtc
)->active
, "crtc not active\n");
3910 WARN(pipe
!= to_intel_crtc(crtc
)->pipe
,
3911 "encoder active on the wrong pipe\n");
3915 /* Even simpler default implementation, if there's really no special case to
3917 void intel_connector_dpms(struct drm_connector
*connector
, int mode
)
3919 struct intel_encoder
*encoder
= intel_attached_encoder(connector
);
3921 /* All the simple cases only support two dpms states. */
3922 if (mode
!= DRM_MODE_DPMS_ON
)
3923 mode
= DRM_MODE_DPMS_OFF
;
3925 if (mode
== connector
->dpms
)
3928 connector
->dpms
= mode
;
3930 /* Only need to change hw state when actually enabled */
3931 if (encoder
->base
.crtc
)
3932 intel_encoder_dpms(encoder
, mode
);
3934 WARN_ON(encoder
->connectors_active
!= false);
3936 intel_modeset_check_state(connector
->dev
);
3939 /* Simple connector->get_hw_state implementation for encoders that support only
3940 * one connector and no cloning and hence the encoder state determines the state
3941 * of the connector. */
3942 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
3945 struct intel_encoder
*encoder
= connector
->encoder
;
3947 return encoder
->get_hw_state(encoder
, &pipe
);
3950 static bool ironlake_check_fdi_lanes(struct drm_device
*dev
, enum pipe pipe
,
3951 struct intel_crtc_config
*pipe_config
)
3953 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3954 struct intel_crtc
*pipe_B_crtc
=
3955 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
3957 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3958 pipe_name(pipe
), pipe_config
->fdi_lanes
);
3959 if (pipe_config
->fdi_lanes
> 4) {
3960 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3961 pipe_name(pipe
), pipe_config
->fdi_lanes
);
3965 if (IS_HASWELL(dev
)) {
3966 if (pipe_config
->fdi_lanes
> 2) {
3967 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3968 pipe_config
->fdi_lanes
);
3975 if (INTEL_INFO(dev
)->num_pipes
== 2)
3978 /* Ivybridge 3 pipe is really complicated */
3983 if (dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]->enabled
&&
3984 pipe_config
->fdi_lanes
> 2) {
3985 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3986 pipe_name(pipe
), pipe_config
->fdi_lanes
);
3991 if (!pipe_has_enabled_pch(pipe_B_crtc
) ||
3992 pipe_B_crtc
->config
.fdi_lanes
<= 2) {
3993 if (pipe_config
->fdi_lanes
> 2) {
3994 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3995 pipe_name(pipe
), pipe_config
->fdi_lanes
);
3999 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4009 static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc
,
4010 struct intel_crtc_config
*pipe_config
)
4012 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4013 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
4014 int lane
, link_bw
, fdi_dotclock
;
4015 bool setup_ok
, needs_recompute
= false;
4018 /* FDI is a binary signal running at ~2.7GHz, encoding
4019 * each output octet as 10 bits. The actual frequency
4020 * is stored as a divider into a 100MHz clock, and the
4021 * mode pixel clock is stored in units of 1KHz.
4022 * Hence the bw of each lane in terms of the mode signal
4025 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
4027 fdi_dotclock
= adjusted_mode
->clock
;
4028 fdi_dotclock
/= pipe_config
->pixel_multiplier
;
4030 lane
= ironlake_get_lanes_required(fdi_dotclock
, link_bw
,
4031 pipe_config
->pipe_bpp
);
4033 pipe_config
->fdi_lanes
= lane
;
4035 intel_link_compute_m_n(pipe_config
->pipe_bpp
, lane
, fdi_dotclock
,
4036 link_bw
, &pipe_config
->fdi_m_n
);
4038 setup_ok
= ironlake_check_fdi_lanes(intel_crtc
->base
.dev
,
4039 intel_crtc
->pipe
, pipe_config
);
4040 if (!setup_ok
&& pipe_config
->pipe_bpp
> 6*3) {
4041 pipe_config
->pipe_bpp
-= 2*3;
4042 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4043 pipe_config
->pipe_bpp
);
4044 needs_recompute
= true;
4045 pipe_config
->bw_constrained
= true;
4050 if (needs_recompute
)
4053 return setup_ok
? 0 : -EINVAL
;
4056 static void hsw_compute_ips_config(struct intel_crtc
*crtc
,
4057 struct intel_crtc_config
*pipe_config
)
4059 pipe_config
->ips_enabled
= i915_enable_ips
&&
4060 hsw_crtc_supports_ips(crtc
) &&
4061 pipe_config
->pipe_bpp
== 24;
4064 static int intel_crtc_compute_config(struct intel_crtc
*crtc
,
4065 struct intel_crtc_config
*pipe_config
)
4067 struct drm_device
*dev
= crtc
->base
.dev
;
4068 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
4070 if (HAS_PCH_SPLIT(dev
)) {
4071 /* FDI link clock is fixed at 2.7G */
4072 if (pipe_config
->requested_mode
.clock
* 3
4073 > IRONLAKE_FDI_FREQ
* 4)
4077 /* All interlaced capable intel hw wants timings in frames. Note though
4078 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4079 * timings, so we need to be careful not to clobber these.*/
4080 if (!pipe_config
->timings_set
)
4081 drm_mode_set_crtcinfo(adjusted_mode
, 0);
4083 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4084 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4086 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
4087 adjusted_mode
->hsync_start
== adjusted_mode
->hdisplay
)
4090 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) && pipe_config
->pipe_bpp
> 10*3) {
4091 pipe_config
->pipe_bpp
= 10*3; /* 12bpc is gen5+ */
4092 } else if (INTEL_INFO(dev
)->gen
<= 4 && pipe_config
->pipe_bpp
> 8*3) {
4093 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4095 pipe_config
->pipe_bpp
= 8*3;
4099 hsw_compute_ips_config(crtc
, pipe_config
);
4101 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4102 * clock survives for now. */
4103 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
4104 pipe_config
->shared_dpll
= crtc
->config
.shared_dpll
;
4106 if (pipe_config
->has_pch_encoder
)
4107 return ironlake_fdi_compute_config(crtc
, pipe_config
);
4112 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
4114 return 400000; /* FIXME */
4117 static int i945_get_display_clock_speed(struct drm_device
*dev
)
4122 static int i915_get_display_clock_speed(struct drm_device
*dev
)
4127 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
4132 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
4136 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
4138 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
4141 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
4142 case GC_DISPLAY_CLOCK_333_MHZ
:
4145 case GC_DISPLAY_CLOCK_190_200_MHZ
:
4151 static int i865_get_display_clock_speed(struct drm_device
*dev
)
4156 static int i855_get_display_clock_speed(struct drm_device
*dev
)
4159 /* Assume that the hardware is in the high speed state. This
4160 * should be the default.
4162 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
4163 case GC_CLOCK_133_200
:
4164 case GC_CLOCK_100_200
:
4166 case GC_CLOCK_166_250
:
4168 case GC_CLOCK_100_133
:
4172 /* Shouldn't happen */
4176 static int i830_get_display_clock_speed(struct drm_device
*dev
)
4182 intel_reduce_m_n_ratio(uint32_t *num
, uint32_t *den
)
4184 while (*num
> DATA_LINK_M_N_MASK
||
4185 *den
> DATA_LINK_M_N_MASK
) {
4191 static void compute_m_n(unsigned int m
, unsigned int n
,
4192 uint32_t *ret_m
, uint32_t *ret_n
)
4194 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
4195 *ret_m
= div_u64((uint64_t) m
* *ret_n
, n
);
4196 intel_reduce_m_n_ratio(ret_m
, ret_n
);
4200 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
4201 int pixel_clock
, int link_clock
,
4202 struct intel_link_m_n
*m_n
)
4206 compute_m_n(bits_per_pixel
* pixel_clock
,
4207 link_clock
* nlanes
* 8,
4208 &m_n
->gmch_m
, &m_n
->gmch_n
);
4210 compute_m_n(pixel_clock
, link_clock
,
4211 &m_n
->link_m
, &m_n
->link_n
);
4214 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
4216 if (i915_panel_use_ssc
>= 0)
4217 return i915_panel_use_ssc
!= 0;
4218 return dev_priv
->vbt
.lvds_use_ssc
4219 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
4222 static int vlv_get_refclk(struct drm_crtc
*crtc
)
4224 struct drm_device
*dev
= crtc
->dev
;
4225 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4226 int refclk
= 27000; /* for DP & HDMI */
4228 return 100000; /* only one validated so far */
4230 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
4232 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
4233 if (intel_panel_use_ssc(dev_priv
))
4237 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
)) {
4244 static int i9xx_get_refclk(struct drm_crtc
*crtc
, int num_connectors
)
4246 struct drm_device
*dev
= crtc
->dev
;
4247 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4250 if (IS_VALLEYVIEW(dev
)) {
4251 refclk
= vlv_get_refclk(crtc
);
4252 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
4253 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
4254 refclk
= dev_priv
->vbt
.lvds_ssc_freq
* 1000;
4255 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4257 } else if (!IS_GEN2(dev
)) {
4266 static uint32_t pnv_dpll_compute_fp(struct dpll
*dpll
)
4268 return (1 << dpll
->n
) << 16 | dpll
->m2
;
4271 static uint32_t i9xx_dpll_compute_fp(struct dpll
*dpll
)
4273 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
4276 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
4277 intel_clock_t
*reduced_clock
)
4279 struct drm_device
*dev
= crtc
->base
.dev
;
4280 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4281 int pipe
= crtc
->pipe
;
4284 if (IS_PINEVIEW(dev
)) {
4285 fp
= pnv_dpll_compute_fp(&crtc
->config
.dpll
);
4287 fp2
= pnv_dpll_compute_fp(reduced_clock
);
4289 fp
= i9xx_dpll_compute_fp(&crtc
->config
.dpll
);
4291 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
4294 I915_WRITE(FP0(pipe
), fp
);
4295 crtc
->config
.dpll_hw_state
.fp0
= fp
;
4297 crtc
->lowfreq_avail
= false;
4298 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4299 reduced_clock
&& i915_powersave
) {
4300 I915_WRITE(FP1(pipe
), fp2
);
4301 crtc
->config
.dpll_hw_state
.fp1
= fp2
;
4302 crtc
->lowfreq_avail
= true;
4304 I915_WRITE(FP1(pipe
), fp
);
4305 crtc
->config
.dpll_hw_state
.fp1
= fp
;
4309 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
)
4314 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4315 * and set it to a reasonable value instead.
4317 reg_val
= vlv_dpio_read(dev_priv
, DPIO_IREF(1));
4318 reg_val
&= 0xffffff00;
4319 reg_val
|= 0x00000030;
4320 vlv_dpio_write(dev_priv
, DPIO_IREF(1), reg_val
);
4322 reg_val
= vlv_dpio_read(dev_priv
, DPIO_CALIBRATION
);
4323 reg_val
&= 0x8cffffff;
4324 reg_val
= 0x8c000000;
4325 vlv_dpio_write(dev_priv
, DPIO_CALIBRATION
, reg_val
);
4327 reg_val
= vlv_dpio_read(dev_priv
, DPIO_IREF(1));
4328 reg_val
&= 0xffffff00;
4329 vlv_dpio_write(dev_priv
, DPIO_IREF(1), reg_val
);
4331 reg_val
= vlv_dpio_read(dev_priv
, DPIO_CALIBRATION
);
4332 reg_val
&= 0x00ffffff;
4333 reg_val
|= 0xb0000000;
4334 vlv_dpio_write(dev_priv
, DPIO_CALIBRATION
, reg_val
);
4337 static void intel_pch_transcoder_set_m_n(struct intel_crtc
*crtc
,
4338 struct intel_link_m_n
*m_n
)
4340 struct drm_device
*dev
= crtc
->base
.dev
;
4341 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4342 int pipe
= crtc
->pipe
;
4344 I915_WRITE(PCH_TRANS_DATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
4345 I915_WRITE(PCH_TRANS_DATA_N1(pipe
), m_n
->gmch_n
);
4346 I915_WRITE(PCH_TRANS_LINK_M1(pipe
), m_n
->link_m
);
4347 I915_WRITE(PCH_TRANS_LINK_N1(pipe
), m_n
->link_n
);
4350 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
4351 struct intel_link_m_n
*m_n
)
4353 struct drm_device
*dev
= crtc
->base
.dev
;
4354 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4355 int pipe
= crtc
->pipe
;
4356 enum transcoder transcoder
= crtc
->config
.cpu_transcoder
;
4358 if (INTEL_INFO(dev
)->gen
>= 5) {
4359 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
4360 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
4361 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
4362 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
4364 I915_WRITE(PIPE_DATA_M_G4X(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
4365 I915_WRITE(PIPE_DATA_N_G4X(pipe
), m_n
->gmch_n
);
4366 I915_WRITE(PIPE_LINK_M_G4X(pipe
), m_n
->link_m
);
4367 I915_WRITE(PIPE_LINK_N_G4X(pipe
), m_n
->link_n
);
4371 static void intel_dp_set_m_n(struct intel_crtc
*crtc
)
4373 if (crtc
->config
.has_pch_encoder
)
4374 intel_pch_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
);
4376 intel_cpu_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
);
4379 static void vlv_update_pll(struct intel_crtc
*crtc
)
4381 struct drm_device
*dev
= crtc
->base
.dev
;
4382 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4383 struct intel_encoder
*encoder
;
4384 int pipe
= crtc
->pipe
;
4386 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
4388 u32 coreclk
, reg_val
, dpll_md
;
4390 mutex_lock(&dev_priv
->dpio_lock
);
4392 is_hdmi
= intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
);
4394 bestn
= crtc
->config
.dpll
.n
;
4395 bestm1
= crtc
->config
.dpll
.m1
;
4396 bestm2
= crtc
->config
.dpll
.m2
;
4397 bestp1
= crtc
->config
.dpll
.p1
;
4398 bestp2
= crtc
->config
.dpll
.p2
;
4400 /* See eDP HDMI DPIO driver vbios notes doc */
4402 /* PLL B needs special handling */
4404 vlv_pllb_recal_opamp(dev_priv
);
4406 /* Set up Tx target for periodic Rcomp update */
4407 vlv_dpio_write(dev_priv
, DPIO_IREF_BCAST
, 0x0100000f);
4409 /* Disable target IRef on PLL */
4410 reg_val
= vlv_dpio_read(dev_priv
, DPIO_IREF_CTL(pipe
));
4411 reg_val
&= 0x00ffffff;
4412 vlv_dpio_write(dev_priv
, DPIO_IREF_CTL(pipe
), reg_val
);
4414 /* Disable fast lock */
4415 vlv_dpio_write(dev_priv
, DPIO_FASTCLK_DISABLE
, 0x610);
4417 /* Set idtafcrecal before PLL is enabled */
4418 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
4419 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
4420 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
4421 mdiv
|= (1 << DPIO_K_SHIFT
);
4424 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4425 * but we don't support that).
4426 * Note: don't use the DAC post divider as it seems unstable.
4428 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
4429 vlv_dpio_write(dev_priv
, DPIO_DIV(pipe
), mdiv
);
4431 mdiv
|= DPIO_ENABLE_CALIBRATION
;
4432 vlv_dpio_write(dev_priv
, DPIO_DIV(pipe
), mdiv
);
4434 /* Set HBR and RBR LPF coefficients */
4435 if (crtc
->config
.port_clock
== 162000 ||
4436 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_ANALOG
) ||
4437 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
))
4438 vlv_dpio_write(dev_priv
, DPIO_LPF_COEFF(pipe
),
4441 vlv_dpio_write(dev_priv
, DPIO_LPF_COEFF(pipe
),
4444 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
) ||
4445 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
)) {
4446 /* Use SSC source */
4448 vlv_dpio_write(dev_priv
, DPIO_REFSFR(pipe
),
4451 vlv_dpio_write(dev_priv
, DPIO_REFSFR(pipe
),
4453 } else { /* HDMI or VGA */
4454 /* Use bend source */
4456 vlv_dpio_write(dev_priv
, DPIO_REFSFR(pipe
),
4459 vlv_dpio_write(dev_priv
, DPIO_REFSFR(pipe
),
4463 coreclk
= vlv_dpio_read(dev_priv
, DPIO_CORE_CLK(pipe
));
4464 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
4465 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
) ||
4466 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
))
4467 coreclk
|= 0x01000000;
4468 vlv_dpio_write(dev_priv
, DPIO_CORE_CLK(pipe
), coreclk
);
4470 vlv_dpio_write(dev_priv
, DPIO_PLL_CML(pipe
), 0x87871000);
4472 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
)
4473 if (encoder
->pre_pll_enable
)
4474 encoder
->pre_pll_enable(encoder
);
4476 /* Enable DPIO clock input */
4477 dpll
= DPLL_EXT_BUFFER_ENABLE_VLV
| DPLL_REFA_CLK_ENABLE_VLV
|
4478 DPLL_VGA_MODE_DIS
| DPLL_INTEGRATED_CLOCK_VLV
;
4480 dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
4482 dpll
|= DPLL_VCO_ENABLE
;
4483 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
4485 I915_WRITE(DPLL(pipe
), dpll
);
4486 POSTING_READ(DPLL(pipe
));
4489 if (wait_for(((I915_READ(DPLL(pipe
)) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
4490 DRM_ERROR("DPLL %d failed to lock\n", pipe
);
4492 dpll_md
= (crtc
->config
.pixel_multiplier
- 1)
4493 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4494 crtc
->config
.dpll_hw_state
.dpll_md
= dpll_md
;
4496 I915_WRITE(DPLL_MD(pipe
), dpll_md
);
4497 POSTING_READ(DPLL_MD(pipe
));
4499 if (crtc
->config
.has_dp_encoder
)
4500 intel_dp_set_m_n(crtc
);
4502 mutex_unlock(&dev_priv
->dpio_lock
);
4505 static void i9xx_update_pll(struct intel_crtc
*crtc
,
4506 intel_clock_t
*reduced_clock
,
4509 struct drm_device
*dev
= crtc
->base
.dev
;
4510 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4513 struct dpll
*clock
= &crtc
->config
.dpll
;
4515 i9xx_update_pll_dividers(crtc
, reduced_clock
);
4517 is_sdvo
= intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_SDVO
) ||
4518 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
);
4520 dpll
= DPLL_VGA_MODE_DIS
;
4522 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
))
4523 dpll
|= DPLLB_MODE_LVDS
;
4525 dpll
|= DPLLB_MODE_DAC_SERIAL
;
4527 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
4528 dpll
|= (crtc
->config
.pixel_multiplier
- 1)
4529 << SDVO_MULTIPLIER_SHIFT_HIRES
;
4533 dpll
|= DPLL_DVO_HIGH_SPEED
;
4535 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
))
4536 dpll
|= DPLL_DVO_HIGH_SPEED
;
4538 /* compute bitmask from p1 value */
4539 if (IS_PINEVIEW(dev
))
4540 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
4542 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4543 if (IS_G4X(dev
) && reduced_clock
)
4544 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
4546 switch (clock
->p2
) {
4548 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
4551 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
4554 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
4557 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
4560 if (INTEL_INFO(dev
)->gen
>= 4)
4561 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
4563 if (crtc
->config
.sdvo_tv_clock
)
4564 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
4565 else if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4566 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4567 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4569 dpll
|= PLL_REF_INPUT_DREFCLK
;
4571 dpll
|= DPLL_VCO_ENABLE
;
4572 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
4574 if (INTEL_INFO(dev
)->gen
>= 4) {
4575 u32 dpll_md
= (crtc
->config
.pixel_multiplier
- 1)
4576 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4577 crtc
->config
.dpll_hw_state
.dpll_md
= dpll_md
;
4580 if (crtc
->config
.has_dp_encoder
)
4581 intel_dp_set_m_n(crtc
);
4584 static void i8xx_update_pll(struct intel_crtc
*crtc
,
4585 intel_clock_t
*reduced_clock
,
4588 struct drm_device
*dev
= crtc
->base
.dev
;
4589 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4591 struct dpll
*clock
= &crtc
->config
.dpll
;
4593 i9xx_update_pll_dividers(crtc
, reduced_clock
);
4595 dpll
= DPLL_VGA_MODE_DIS
;
4597 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
)) {
4598 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4601 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
4603 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4605 dpll
|= PLL_P2_DIVIDE_BY_4
;
4608 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4609 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4610 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4612 dpll
|= PLL_REF_INPUT_DREFCLK
;
4614 dpll
|= DPLL_VCO_ENABLE
;
4615 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
4618 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
)
4620 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4621 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4622 enum pipe pipe
= intel_crtc
->pipe
;
4623 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
4624 struct drm_display_mode
*adjusted_mode
=
4625 &intel_crtc
->config
.adjusted_mode
;
4626 struct drm_display_mode
*mode
= &intel_crtc
->config
.requested_mode
;
4627 uint32_t vsyncshift
, crtc_vtotal
, crtc_vblank_end
;
4629 /* We need to be careful not to changed the adjusted mode, for otherwise
4630 * the hw state checker will get angry at the mismatch. */
4631 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
4632 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
4634 if (!IS_GEN2(dev
) && adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
4635 /* the chip adds 2 halflines automatically */
4637 crtc_vblank_end
-= 1;
4638 vsyncshift
= adjusted_mode
->crtc_hsync_start
4639 - adjusted_mode
->crtc_htotal
/ 2;
4644 if (INTEL_INFO(dev
)->gen
> 3)
4645 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
4647 I915_WRITE(HTOTAL(cpu_transcoder
),
4648 (adjusted_mode
->crtc_hdisplay
- 1) |
4649 ((adjusted_mode
->crtc_htotal
- 1) << 16));
4650 I915_WRITE(HBLANK(cpu_transcoder
),
4651 (adjusted_mode
->crtc_hblank_start
- 1) |
4652 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
4653 I915_WRITE(HSYNC(cpu_transcoder
),
4654 (adjusted_mode
->crtc_hsync_start
- 1) |
4655 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
4657 I915_WRITE(VTOTAL(cpu_transcoder
),
4658 (adjusted_mode
->crtc_vdisplay
- 1) |
4659 ((crtc_vtotal
- 1) << 16));
4660 I915_WRITE(VBLANK(cpu_transcoder
),
4661 (adjusted_mode
->crtc_vblank_start
- 1) |
4662 ((crtc_vblank_end
- 1) << 16));
4663 I915_WRITE(VSYNC(cpu_transcoder
),
4664 (adjusted_mode
->crtc_vsync_start
- 1) |
4665 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
4667 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4668 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4669 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4671 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
4672 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
4673 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
4675 /* pipesrc controls the size that is scaled from, which should
4676 * always be the user's requested size.
4678 I915_WRITE(PIPESRC(pipe
),
4679 ((mode
->hdisplay
- 1) << 16) | (mode
->vdisplay
- 1));
4682 static void intel_get_pipe_timings(struct intel_crtc
*crtc
,
4683 struct intel_crtc_config
*pipe_config
)
4685 struct drm_device
*dev
= crtc
->base
.dev
;
4686 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4687 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
4690 tmp
= I915_READ(HTOTAL(cpu_transcoder
));
4691 pipe_config
->adjusted_mode
.crtc_hdisplay
= (tmp
& 0xffff) + 1;
4692 pipe_config
->adjusted_mode
.crtc_htotal
= ((tmp
>> 16) & 0xffff) + 1;
4693 tmp
= I915_READ(HBLANK(cpu_transcoder
));
4694 pipe_config
->adjusted_mode
.crtc_hblank_start
= (tmp
& 0xffff) + 1;
4695 pipe_config
->adjusted_mode
.crtc_hblank_end
= ((tmp
>> 16) & 0xffff) + 1;
4696 tmp
= I915_READ(HSYNC(cpu_transcoder
));
4697 pipe_config
->adjusted_mode
.crtc_hsync_start
= (tmp
& 0xffff) + 1;
4698 pipe_config
->adjusted_mode
.crtc_hsync_end
= ((tmp
>> 16) & 0xffff) + 1;
4700 tmp
= I915_READ(VTOTAL(cpu_transcoder
));
4701 pipe_config
->adjusted_mode
.crtc_vdisplay
= (tmp
& 0xffff) + 1;
4702 pipe_config
->adjusted_mode
.crtc_vtotal
= ((tmp
>> 16) & 0xffff) + 1;
4703 tmp
= I915_READ(VBLANK(cpu_transcoder
));
4704 pipe_config
->adjusted_mode
.crtc_vblank_start
= (tmp
& 0xffff) + 1;
4705 pipe_config
->adjusted_mode
.crtc_vblank_end
= ((tmp
>> 16) & 0xffff) + 1;
4706 tmp
= I915_READ(VSYNC(cpu_transcoder
));
4707 pipe_config
->adjusted_mode
.crtc_vsync_start
= (tmp
& 0xffff) + 1;
4708 pipe_config
->adjusted_mode
.crtc_vsync_end
= ((tmp
>> 16) & 0xffff) + 1;
4710 if (I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_INTERLACE_MASK
) {
4711 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
4712 pipe_config
->adjusted_mode
.crtc_vtotal
+= 1;
4713 pipe_config
->adjusted_mode
.crtc_vblank_end
+= 1;
4716 tmp
= I915_READ(PIPESRC(crtc
->pipe
));
4717 pipe_config
->requested_mode
.vdisplay
= (tmp
& 0xffff) + 1;
4718 pipe_config
->requested_mode
.hdisplay
= ((tmp
>> 16) & 0xffff) + 1;
4721 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
)
4723 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4724 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4729 if (intel_crtc
->pipe
== 0 && INTEL_INFO(dev
)->gen
< 4) {
4730 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4733 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4736 if (intel_crtc
->config
.requested_mode
.clock
>
4737 dev_priv
->display
.get_display_clock_speed(dev
) * 9 / 10)
4738 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
4741 /* only g4x and later have fancy bpc/dither controls */
4742 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
4743 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4744 if (intel_crtc
->config
.dither
&& intel_crtc
->config
.pipe_bpp
!= 30)
4745 pipeconf
|= PIPECONF_DITHER_EN
|
4746 PIPECONF_DITHER_TYPE_SP
;
4748 switch (intel_crtc
->config
.pipe_bpp
) {
4750 pipeconf
|= PIPECONF_6BPC
;
4753 pipeconf
|= PIPECONF_8BPC
;
4756 pipeconf
|= PIPECONF_10BPC
;
4759 /* Case prevented by intel_choose_pipe_bpp_dither. */
4764 if (HAS_PIPE_CXSR(dev
)) {
4765 if (intel_crtc
->lowfreq_avail
) {
4766 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4767 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
4769 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4773 if (!IS_GEN2(dev
) &&
4774 intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
4775 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
4777 pipeconf
|= PIPECONF_PROGRESSIVE
;
4779 if (IS_VALLEYVIEW(dev
) && intel_crtc
->config
.limited_color_range
)
4780 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
4782 I915_WRITE(PIPECONF(intel_crtc
->pipe
), pipeconf
);
4783 POSTING_READ(PIPECONF(intel_crtc
->pipe
));
4786 static int i9xx_crtc_mode_set(struct drm_crtc
*crtc
,
4788 struct drm_framebuffer
*fb
)
4790 struct drm_device
*dev
= crtc
->dev
;
4791 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4792 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4793 struct drm_display_mode
*mode
= &intel_crtc
->config
.requested_mode
;
4794 int pipe
= intel_crtc
->pipe
;
4795 int plane
= intel_crtc
->plane
;
4796 int refclk
, num_connectors
= 0;
4797 intel_clock_t clock
, reduced_clock
;
4799 bool ok
, has_reduced_clock
= false;
4800 bool is_lvds
= false;
4801 struct intel_encoder
*encoder
;
4802 const intel_limit_t
*limit
;
4805 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4806 switch (encoder
->type
) {
4807 case INTEL_OUTPUT_LVDS
:
4815 refclk
= i9xx_get_refclk(crtc
, num_connectors
);
4818 * Returns a set of divisors for the desired target clock with the given
4819 * refclk, or FALSE. The returned values represent the clock equation:
4820 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4822 limit
= intel_limit(crtc
, refclk
);
4823 ok
= dev_priv
->display
.find_dpll(limit
, crtc
,
4824 intel_crtc
->config
.port_clock
,
4825 refclk
, NULL
, &clock
);
4826 if (!ok
&& !intel_crtc
->config
.clock_set
) {
4827 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4831 /* Ensure that the cursor is valid for the new mode before changing... */
4832 intel_crtc_update_cursor(crtc
, true);
4834 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
4836 * Ensure we match the reduced clock's P to the target clock.
4837 * If the clocks don't match, we can't switch the display clock
4838 * by using the FP0/FP1. In such case we will disable the LVDS
4839 * downclock feature.
4842 dev_priv
->display
.find_dpll(limit
, crtc
,
4843 dev_priv
->lvds_downclock
,
4847 /* Compat-code for transition, will disappear. */
4848 if (!intel_crtc
->config
.clock_set
) {
4849 intel_crtc
->config
.dpll
.n
= clock
.n
;
4850 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
4851 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
4852 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
4853 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
4857 i8xx_update_pll(intel_crtc
,
4858 has_reduced_clock
? &reduced_clock
: NULL
,
4860 else if (IS_VALLEYVIEW(dev
))
4861 vlv_update_pll(intel_crtc
);
4863 i9xx_update_pll(intel_crtc
,
4864 has_reduced_clock
? &reduced_clock
: NULL
,
4867 /* Set up the display plane register */
4868 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
4870 if (!IS_VALLEYVIEW(dev
)) {
4872 dspcntr
&= ~DISPPLANE_SEL_PIPE_MASK
;
4874 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
4877 intel_set_pipe_timings(intel_crtc
);
4879 /* pipesrc and dspsize control the size that is scaled from,
4880 * which should always be the user's requested size.
4882 I915_WRITE(DSPSIZE(plane
),
4883 ((mode
->vdisplay
- 1) << 16) |
4884 (mode
->hdisplay
- 1));
4885 I915_WRITE(DSPPOS(plane
), 0);
4887 i9xx_set_pipeconf(intel_crtc
);
4889 I915_WRITE(DSPCNTR(plane
), dspcntr
);
4890 POSTING_READ(DSPCNTR(plane
));
4892 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
4894 intel_update_watermarks(dev
);
4899 static void i9xx_get_pfit_config(struct intel_crtc
*crtc
,
4900 struct intel_crtc_config
*pipe_config
)
4902 struct drm_device
*dev
= crtc
->base
.dev
;
4903 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4906 tmp
= I915_READ(PFIT_CONTROL
);
4908 if (INTEL_INFO(dev
)->gen
< 4) {
4909 if (crtc
->pipe
!= PIPE_B
)
4912 /* gen2/3 store dither state in pfit control, needs to match */
4913 pipe_config
->gmch_pfit
.control
= tmp
& PANEL_8TO6_DITHER_ENABLE
;
4915 if ((tmp
& PFIT_PIPE_MASK
) != (crtc
->pipe
<< PFIT_PIPE_SHIFT
))
4919 if (!(tmp
& PFIT_ENABLE
))
4922 pipe_config
->gmch_pfit
.control
= I915_READ(PFIT_CONTROL
);
4923 pipe_config
->gmch_pfit
.pgm_ratios
= I915_READ(PFIT_PGM_RATIOS
);
4924 if (INTEL_INFO(dev
)->gen
< 5)
4925 pipe_config
->gmch_pfit
.lvds_border_bits
=
4926 I915_READ(LVDS
) & LVDS_BORDER_ENABLE
;
4929 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
4930 struct intel_crtc_config
*pipe_config
)
4932 struct drm_device
*dev
= crtc
->base
.dev
;
4933 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4936 pipe_config
->cpu_transcoder
= crtc
->pipe
;
4937 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
4939 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
4940 if (!(tmp
& PIPECONF_ENABLE
))
4943 intel_get_pipe_timings(crtc
, pipe_config
);
4945 i9xx_get_pfit_config(crtc
, pipe_config
);
4947 if (INTEL_INFO(dev
)->gen
>= 4) {
4948 tmp
= I915_READ(DPLL_MD(crtc
->pipe
));
4949 pipe_config
->pixel_multiplier
=
4950 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
4951 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
4952 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
4953 } else if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
4954 tmp
= I915_READ(DPLL(crtc
->pipe
));
4955 pipe_config
->pixel_multiplier
=
4956 ((tmp
& SDVO_MULTIPLIER_MASK
)
4957 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
4959 /* Note that on i915G/GM the pixel multiplier is in the sdvo
4960 * port and will be fixed up in the encoder->get_config
4962 pipe_config
->pixel_multiplier
= 1;
4964 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(crtc
->pipe
));
4965 if (!IS_VALLEYVIEW(dev
)) {
4966 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(crtc
->pipe
));
4967 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(crtc
->pipe
));
4973 static void ironlake_init_pch_refclk(struct drm_device
*dev
)
4975 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4976 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
4977 struct intel_encoder
*encoder
;
4979 bool has_lvds
= false;
4980 bool has_cpu_edp
= false;
4981 bool has_panel
= false;
4982 bool has_ck505
= false;
4983 bool can_ssc
= false;
4985 /* We need to take the global config into account */
4986 list_for_each_entry(encoder
, &mode_config
->encoder_list
,
4988 switch (encoder
->type
) {
4989 case INTEL_OUTPUT_LVDS
:
4993 case INTEL_OUTPUT_EDP
:
4995 if (enc_to_dig_port(&encoder
->base
)->port
== PORT_A
)
5001 if (HAS_PCH_IBX(dev
)) {
5002 has_ck505
= dev_priv
->vbt
.display_clock_mode
;
5003 can_ssc
= has_ck505
;
5009 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5010 has_panel
, has_lvds
, has_ck505
);
5012 /* Ironlake: try to setup display ref clock before DPLL
5013 * enabling. This is only under driver's control after
5014 * PCH B stepping, previous chipset stepping should be
5015 * ignoring this setting.
5017 val
= I915_READ(PCH_DREF_CONTROL
);
5019 /* As we must carefully and slowly disable/enable each source in turn,
5020 * compute the final state we want first and check if we need to
5021 * make any changes at all.
5024 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
5026 final
|= DREF_NONSPREAD_CK505_ENABLE
;
5028 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
5030 final
&= ~DREF_SSC_SOURCE_MASK
;
5031 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
5032 final
&= ~DREF_SSC1_ENABLE
;
5035 final
|= DREF_SSC_SOURCE_ENABLE
;
5037 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
5038 final
|= DREF_SSC1_ENABLE
;
5041 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
5042 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
5044 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
5046 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5048 final
|= DREF_SSC_SOURCE_DISABLE
;
5049 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5055 /* Always enable nonspread source */
5056 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
5059 val
|= DREF_NONSPREAD_CK505_ENABLE
;
5061 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
5064 val
&= ~DREF_SSC_SOURCE_MASK
;
5065 val
|= DREF_SSC_SOURCE_ENABLE
;
5067 /* SSC must be turned on before enabling the CPU output */
5068 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
5069 DRM_DEBUG_KMS("Using SSC on panel\n");
5070 val
|= DREF_SSC1_ENABLE
;
5072 val
&= ~DREF_SSC1_ENABLE
;
5074 /* Get SSC going before enabling the outputs */
5075 I915_WRITE(PCH_DREF_CONTROL
, val
);
5076 POSTING_READ(PCH_DREF_CONTROL
);
5079 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
5081 /* Enable CPU source on CPU attached eDP */
5083 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
5084 DRM_DEBUG_KMS("Using SSC on eDP\n");
5085 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
5088 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
5090 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5092 I915_WRITE(PCH_DREF_CONTROL
, val
);
5093 POSTING_READ(PCH_DREF_CONTROL
);
5096 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5098 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
5100 /* Turn off CPU output */
5101 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5103 I915_WRITE(PCH_DREF_CONTROL
, val
);
5104 POSTING_READ(PCH_DREF_CONTROL
);
5107 /* Turn off the SSC source */
5108 val
&= ~DREF_SSC_SOURCE_MASK
;
5109 val
|= DREF_SSC_SOURCE_DISABLE
;
5112 val
&= ~DREF_SSC1_ENABLE
;
5114 I915_WRITE(PCH_DREF_CONTROL
, val
);
5115 POSTING_READ(PCH_DREF_CONTROL
);
5119 BUG_ON(val
!= final
);
5122 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5123 static void lpt_init_pch_refclk(struct drm_device
*dev
)
5125 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5126 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
5127 struct intel_encoder
*encoder
;
5128 bool has_vga
= false;
5129 bool is_sdv
= false;
5132 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
) {
5133 switch (encoder
->type
) {
5134 case INTEL_OUTPUT_ANALOG
:
5143 mutex_lock(&dev_priv
->dpio_lock
);
5145 /* XXX: Rip out SDV support once Haswell ships for real. */
5146 if (IS_HASWELL(dev
) && (dev
->pci_device
& 0xFF00) == 0x0C00)
5149 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
5150 tmp
&= ~SBI_SSCCTL_DISABLE
;
5151 tmp
|= SBI_SSCCTL_PATHALT
;
5152 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
5156 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
5157 tmp
&= ~SBI_SSCCTL_PATHALT
;
5158 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
5161 tmp
= I915_READ(SOUTH_CHICKEN2
);
5162 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
5163 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
5165 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2
) &
5166 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
5167 DRM_ERROR("FDI mPHY reset assert timeout\n");
5169 tmp
= I915_READ(SOUTH_CHICKEN2
);
5170 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
5171 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
5173 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2
) &
5174 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0,
5176 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5179 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
5180 tmp
&= ~(0xFF << 24);
5181 tmp
|= (0x12 << 24);
5182 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
5185 tmp
= intel_sbi_read(dev_priv
, 0x800C, SBI_MPHY
);
5187 intel_sbi_write(dev_priv
, 0x800C, tmp
, SBI_MPHY
);
5190 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
5192 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
5194 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
5196 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
5199 tmp
= intel_sbi_read(dev_priv
, 0x2038, SBI_MPHY
);
5200 tmp
|= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5201 intel_sbi_write(dev_priv
, 0x2038, tmp
, SBI_MPHY
);
5203 tmp
= intel_sbi_read(dev_priv
, 0x2138, SBI_MPHY
);
5204 tmp
|= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5205 intel_sbi_write(dev_priv
, 0x2138, tmp
, SBI_MPHY
);
5207 tmp
= intel_sbi_read(dev_priv
, 0x203C, SBI_MPHY
);
5209 intel_sbi_write(dev_priv
, 0x203C, tmp
, SBI_MPHY
);
5211 tmp
= intel_sbi_read(dev_priv
, 0x213C, SBI_MPHY
);
5213 intel_sbi_write(dev_priv
, 0x213C, tmp
, SBI_MPHY
);
5216 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
5217 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
5218 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
5220 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
5221 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
5222 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
5225 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
5228 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
5230 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
5233 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
5236 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
5239 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
5241 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
5244 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
5246 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
5247 tmp
&= ~(0xFF << 16);
5248 tmp
|= (0x1C << 16);
5249 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
5251 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
5252 tmp
&= ~(0xFF << 16);
5253 tmp
|= (0x1C << 16);
5254 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
5257 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
5259 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
5261 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
5263 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
5265 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
5266 tmp
&= ~(0xF << 28);
5268 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
5270 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
5271 tmp
&= ~(0xF << 28);
5273 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
5276 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5277 tmp
= intel_sbi_read(dev_priv
, SBI_DBUFF0
, SBI_ICLK
);
5278 tmp
|= SBI_DBUFF0_ENABLE
;
5279 intel_sbi_write(dev_priv
, SBI_DBUFF0
, tmp
, SBI_ICLK
);
5281 mutex_unlock(&dev_priv
->dpio_lock
);
5285 * Initialize reference clocks when the driver loads
5287 void intel_init_pch_refclk(struct drm_device
*dev
)
5289 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
5290 ironlake_init_pch_refclk(dev
);
5291 else if (HAS_PCH_LPT(dev
))
5292 lpt_init_pch_refclk(dev
);
5295 static int ironlake_get_refclk(struct drm_crtc
*crtc
)
5297 struct drm_device
*dev
= crtc
->dev
;
5298 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5299 struct intel_encoder
*encoder
;
5300 int num_connectors
= 0;
5301 bool is_lvds
= false;
5303 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5304 switch (encoder
->type
) {
5305 case INTEL_OUTPUT_LVDS
:
5312 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
5313 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5314 dev_priv
->vbt
.lvds_ssc_freq
);
5315 return dev_priv
->vbt
.lvds_ssc_freq
* 1000;
5321 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
)
5323 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
5324 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5325 int pipe
= intel_crtc
->pipe
;
5330 switch (intel_crtc
->config
.pipe_bpp
) {
5332 val
|= PIPECONF_6BPC
;
5335 val
|= PIPECONF_8BPC
;
5338 val
|= PIPECONF_10BPC
;
5341 val
|= PIPECONF_12BPC
;
5344 /* Case prevented by intel_choose_pipe_bpp_dither. */
5348 if (intel_crtc
->config
.dither
)
5349 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
5351 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
5352 val
|= PIPECONF_INTERLACED_ILK
;
5354 val
|= PIPECONF_PROGRESSIVE
;
5356 if (intel_crtc
->config
.limited_color_range
)
5357 val
|= PIPECONF_COLOR_RANGE_SELECT
;
5359 I915_WRITE(PIPECONF(pipe
), val
);
5360 POSTING_READ(PIPECONF(pipe
));
5364 * Set up the pipe CSC unit.
5366 * Currently only full range RGB to limited range RGB conversion
5367 * is supported, but eventually this should handle various
5368 * RGB<->YCbCr scenarios as well.
5370 static void intel_set_pipe_csc(struct drm_crtc
*crtc
)
5372 struct drm_device
*dev
= crtc
->dev
;
5373 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5374 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5375 int pipe
= intel_crtc
->pipe
;
5376 uint16_t coeff
= 0x7800; /* 1.0 */
5379 * TODO: Check what kind of values actually come out of the pipe
5380 * with these coeff/postoff values and adjust to get the best
5381 * accuracy. Perhaps we even need to take the bpc value into
5385 if (intel_crtc
->config
.limited_color_range
)
5386 coeff
= ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5389 * GY/GU and RY/RU should be the other way around according
5390 * to BSpec, but reality doesn't agree. Just set them up in
5391 * a way that results in the correct picture.
5393 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe
), coeff
<< 16);
5394 I915_WRITE(PIPE_CSC_COEFF_BY(pipe
), 0);
5396 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe
), coeff
);
5397 I915_WRITE(PIPE_CSC_COEFF_BU(pipe
), 0);
5399 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe
), 0);
5400 I915_WRITE(PIPE_CSC_COEFF_BV(pipe
), coeff
<< 16);
5402 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe
), 0);
5403 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe
), 0);
5404 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe
), 0);
5406 if (INTEL_INFO(dev
)->gen
> 6) {
5407 uint16_t postoff
= 0;
5409 if (intel_crtc
->config
.limited_color_range
)
5410 postoff
= (16 * (1 << 13) / 255) & 0x1fff;
5412 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe
), postoff
);
5413 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe
), postoff
);
5414 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe
), postoff
);
5416 I915_WRITE(PIPE_CSC_MODE(pipe
), 0);
5418 uint32_t mode
= CSC_MODE_YUV_TO_RGB
;
5420 if (intel_crtc
->config
.limited_color_range
)
5421 mode
|= CSC_BLACK_SCREEN_OFFSET
;
5423 I915_WRITE(PIPE_CSC_MODE(pipe
), mode
);
5427 static void haswell_set_pipeconf(struct drm_crtc
*crtc
)
5429 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
5430 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5431 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
5436 if (intel_crtc
->config
.dither
)
5437 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
5439 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
5440 val
|= PIPECONF_INTERLACED_ILK
;
5442 val
|= PIPECONF_PROGRESSIVE
;
5444 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
5445 POSTING_READ(PIPECONF(cpu_transcoder
));
5447 I915_WRITE(GAMMA_MODE(intel_crtc
->pipe
), GAMMA_MODE_MODE_8BIT
);
5448 POSTING_READ(GAMMA_MODE(intel_crtc
->pipe
));
5451 static bool ironlake_compute_clocks(struct drm_crtc
*crtc
,
5452 intel_clock_t
*clock
,
5453 bool *has_reduced_clock
,
5454 intel_clock_t
*reduced_clock
)
5456 struct drm_device
*dev
= crtc
->dev
;
5457 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5458 struct intel_encoder
*intel_encoder
;
5460 const intel_limit_t
*limit
;
5461 bool ret
, is_lvds
= false;
5463 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
5464 switch (intel_encoder
->type
) {
5465 case INTEL_OUTPUT_LVDS
:
5471 refclk
= ironlake_get_refclk(crtc
);
5474 * Returns a set of divisors for the desired target clock with the given
5475 * refclk, or FALSE. The returned values represent the clock equation:
5476 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5478 limit
= intel_limit(crtc
, refclk
);
5479 ret
= dev_priv
->display
.find_dpll(limit
, crtc
,
5480 to_intel_crtc(crtc
)->config
.port_clock
,
5481 refclk
, NULL
, clock
);
5485 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
5487 * Ensure we match the reduced clock's P to the target clock.
5488 * If the clocks don't match, we can't switch the display clock
5489 * by using the FP0/FP1. In such case we will disable the LVDS
5490 * downclock feature.
5492 *has_reduced_clock
=
5493 dev_priv
->display
.find_dpll(limit
, crtc
,
5494 dev_priv
->lvds_downclock
,
5502 static void cpt_enable_fdi_bc_bifurcation(struct drm_device
*dev
)
5504 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5507 temp
= I915_READ(SOUTH_CHICKEN1
);
5508 if (temp
& FDI_BC_BIFURCATION_SELECT
)
5511 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
5512 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
5514 temp
|= FDI_BC_BIFURCATION_SELECT
;
5515 DRM_DEBUG_KMS("enabling fdi C rx\n");
5516 I915_WRITE(SOUTH_CHICKEN1
, temp
);
5517 POSTING_READ(SOUTH_CHICKEN1
);
5520 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc
*intel_crtc
)
5522 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5523 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5525 switch (intel_crtc
->pipe
) {
5529 if (intel_crtc
->config
.fdi_lanes
> 2)
5530 WARN_ON(I915_READ(SOUTH_CHICKEN1
) & FDI_BC_BIFURCATION_SELECT
);
5532 cpt_enable_fdi_bc_bifurcation(dev
);
5536 cpt_enable_fdi_bc_bifurcation(dev
);
5544 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
5547 * Account for spread spectrum to avoid
5548 * oversubscribing the link. Max center spread
5549 * is 2.5%; use 5% for safety's sake.
5551 u32 bps
= target_clock
* bpp
* 21 / 20;
5552 return bps
/ (link_bw
* 8) + 1;
5555 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
5557 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
5560 static uint32_t ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
5562 intel_clock_t
*reduced_clock
, u32
*fp2
)
5564 struct drm_crtc
*crtc
= &intel_crtc
->base
;
5565 struct drm_device
*dev
= crtc
->dev
;
5566 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5567 struct intel_encoder
*intel_encoder
;
5569 int factor
, num_connectors
= 0;
5570 bool is_lvds
= false, is_sdvo
= false;
5572 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
5573 switch (intel_encoder
->type
) {
5574 case INTEL_OUTPUT_LVDS
:
5577 case INTEL_OUTPUT_SDVO
:
5578 case INTEL_OUTPUT_HDMI
:
5586 /* Enable autotuning of the PLL clock (if permissible) */
5589 if ((intel_panel_use_ssc(dev_priv
) &&
5590 dev_priv
->vbt
.lvds_ssc_freq
== 100) ||
5591 (HAS_PCH_IBX(dev
) && intel_is_dual_link_lvds(dev
)))
5593 } else if (intel_crtc
->config
.sdvo_tv_clock
)
5596 if (ironlake_needs_fb_cb_tune(&intel_crtc
->config
.dpll
, factor
))
5599 if (fp2
&& (reduced_clock
->m
< factor
* reduced_clock
->n
))
5605 dpll
|= DPLLB_MODE_LVDS
;
5607 dpll
|= DPLLB_MODE_DAC_SERIAL
;
5609 dpll
|= (intel_crtc
->config
.pixel_multiplier
- 1)
5610 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
5613 dpll
|= DPLL_DVO_HIGH_SPEED
;
5614 if (intel_crtc
->config
.has_dp_encoder
)
5615 dpll
|= DPLL_DVO_HIGH_SPEED
;
5617 /* compute bitmask from p1 value */
5618 dpll
|= (1 << (intel_crtc
->config
.dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5620 dpll
|= (1 << (intel_crtc
->config
.dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
5622 switch (intel_crtc
->config
.dpll
.p2
) {
5624 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
5627 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
5630 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
5633 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
5637 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
5638 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
5640 dpll
|= PLL_REF_INPUT_DREFCLK
;
5642 return dpll
| DPLL_VCO_ENABLE
;
5645 static int ironlake_crtc_mode_set(struct drm_crtc
*crtc
,
5647 struct drm_framebuffer
*fb
)
5649 struct drm_device
*dev
= crtc
->dev
;
5650 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5651 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5652 int pipe
= intel_crtc
->pipe
;
5653 int plane
= intel_crtc
->plane
;
5654 int num_connectors
= 0;
5655 intel_clock_t clock
, reduced_clock
;
5656 u32 dpll
= 0, fp
= 0, fp2
= 0;
5657 bool ok
, has_reduced_clock
= false;
5658 bool is_lvds
= false;
5659 struct intel_encoder
*encoder
;
5660 struct intel_shared_dpll
*pll
;
5663 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5664 switch (encoder
->type
) {
5665 case INTEL_OUTPUT_LVDS
:
5673 WARN(!(HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)),
5674 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev
));
5676 ok
= ironlake_compute_clocks(crtc
, &clock
,
5677 &has_reduced_clock
, &reduced_clock
);
5678 if (!ok
&& !intel_crtc
->config
.clock_set
) {
5679 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5682 /* Compat-code for transition, will disappear. */
5683 if (!intel_crtc
->config
.clock_set
) {
5684 intel_crtc
->config
.dpll
.n
= clock
.n
;
5685 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
5686 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
5687 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
5688 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
5691 /* Ensure that the cursor is valid for the new mode before changing... */
5692 intel_crtc_update_cursor(crtc
, true);
5694 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5695 if (intel_crtc
->config
.has_pch_encoder
) {
5696 fp
= i9xx_dpll_compute_fp(&intel_crtc
->config
.dpll
);
5697 if (has_reduced_clock
)
5698 fp2
= i9xx_dpll_compute_fp(&reduced_clock
);
5700 dpll
= ironlake_compute_dpll(intel_crtc
,
5701 &fp
, &reduced_clock
,
5702 has_reduced_clock
? &fp2
: NULL
);
5704 intel_crtc
->config
.dpll_hw_state
.dpll
= dpll
;
5705 intel_crtc
->config
.dpll_hw_state
.fp0
= fp
;
5706 if (has_reduced_clock
)
5707 intel_crtc
->config
.dpll_hw_state
.fp1
= fp2
;
5709 intel_crtc
->config
.dpll_hw_state
.fp1
= fp
;
5711 pll
= intel_get_shared_dpll(intel_crtc
);
5713 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5718 intel_put_shared_dpll(intel_crtc
);
5720 if (intel_crtc
->config
.has_dp_encoder
)
5721 intel_dp_set_m_n(intel_crtc
);
5723 if (is_lvds
&& has_reduced_clock
&& i915_powersave
)
5724 intel_crtc
->lowfreq_avail
= true;
5726 intel_crtc
->lowfreq_avail
= false;
5728 if (intel_crtc
->config
.has_pch_encoder
) {
5729 pll
= intel_crtc_to_shared_dpll(intel_crtc
);
5733 intel_set_pipe_timings(intel_crtc
);
5735 if (intel_crtc
->config
.has_pch_encoder
) {
5736 intel_cpu_transcoder_set_m_n(intel_crtc
,
5737 &intel_crtc
->config
.fdi_m_n
);
5740 if (IS_IVYBRIDGE(dev
))
5741 ivybridge_update_fdi_bc_bifurcation(intel_crtc
);
5743 ironlake_set_pipeconf(crtc
);
5745 /* Set up the display plane register */
5746 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
);
5747 POSTING_READ(DSPCNTR(plane
));
5749 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
5751 intel_update_watermarks(dev
);
5756 static void ironlake_get_fdi_m_n_config(struct intel_crtc
*crtc
,
5757 struct intel_crtc_config
*pipe_config
)
5759 struct drm_device
*dev
= crtc
->base
.dev
;
5760 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5761 enum transcoder transcoder
= pipe_config
->cpu_transcoder
;
5763 pipe_config
->fdi_m_n
.link_m
= I915_READ(PIPE_LINK_M1(transcoder
));
5764 pipe_config
->fdi_m_n
.link_n
= I915_READ(PIPE_LINK_N1(transcoder
));
5765 pipe_config
->fdi_m_n
.gmch_m
= I915_READ(PIPE_DATA_M1(transcoder
))
5767 pipe_config
->fdi_m_n
.gmch_n
= I915_READ(PIPE_DATA_N1(transcoder
));
5768 pipe_config
->fdi_m_n
.tu
= ((I915_READ(PIPE_DATA_M1(transcoder
))
5769 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
5772 static void ironlake_get_pfit_config(struct intel_crtc
*crtc
,
5773 struct intel_crtc_config
*pipe_config
)
5775 struct drm_device
*dev
= crtc
->base
.dev
;
5776 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5779 tmp
= I915_READ(PF_CTL(crtc
->pipe
));
5781 if (tmp
& PF_ENABLE
) {
5782 pipe_config
->pch_pfit
.pos
= I915_READ(PF_WIN_POS(crtc
->pipe
));
5783 pipe_config
->pch_pfit
.size
= I915_READ(PF_WIN_SZ(crtc
->pipe
));
5785 /* We currently do not free assignements of panel fitters on
5786 * ivb/hsw (since we don't use the higher upscaling modes which
5787 * differentiates them) so just WARN about this case for now. */
5789 WARN_ON((tmp
& PF_PIPE_SEL_MASK_IVB
) !=
5790 PF_PIPE_SEL_IVB(crtc
->pipe
));
5795 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
5796 struct intel_crtc_config
*pipe_config
)
5798 struct drm_device
*dev
= crtc
->base
.dev
;
5799 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5802 pipe_config
->cpu_transcoder
= crtc
->pipe
;
5803 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
5805 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
5806 if (!(tmp
& PIPECONF_ENABLE
))
5809 if (I915_READ(PCH_TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
) {
5810 struct intel_shared_dpll
*pll
;
5812 pipe_config
->has_pch_encoder
= true;
5814 tmp
= I915_READ(FDI_RX_CTL(crtc
->pipe
));
5815 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
5816 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
5818 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
5820 /* XXX: Can't properly read out the pch dpll pixel multiplier
5821 * since we don't have state tracking for pch clocks yet. */
5822 pipe_config
->pixel_multiplier
= 1;
5824 if (HAS_PCH_IBX(dev_priv
->dev
)) {
5825 pipe_config
->shared_dpll
= crtc
->pipe
;
5827 tmp
= I915_READ(PCH_DPLL_SEL
);
5828 if (tmp
& TRANS_DPLLB_SEL(crtc
->pipe
))
5829 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_B
;
5831 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_A
;
5834 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
5836 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
5837 &pipe_config
->dpll_hw_state
));
5839 pipe_config
->pixel_multiplier
= 1;
5842 intel_get_pipe_timings(crtc
, pipe_config
);
5844 ironlake_get_pfit_config(crtc
, pipe_config
);
5849 static void haswell_modeset_global_resources(struct drm_device
*dev
)
5851 bool enable
= false;
5852 struct intel_crtc
*crtc
;
5854 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
5855 if (!crtc
->base
.enabled
)
5858 if (crtc
->pipe
!= PIPE_A
|| crtc
->config
.pch_pfit
.size
||
5859 crtc
->config
.cpu_transcoder
!= TRANSCODER_EDP
)
5863 intel_set_power_well(dev
, enable
);
5866 static int haswell_crtc_mode_set(struct drm_crtc
*crtc
,
5868 struct drm_framebuffer
*fb
)
5870 struct drm_device
*dev
= crtc
->dev
;
5871 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5872 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5873 int plane
= intel_crtc
->plane
;
5876 if (!intel_ddi_pll_mode_set(crtc
))
5879 /* Ensure that the cursor is valid for the new mode before changing... */
5880 intel_crtc_update_cursor(crtc
, true);
5882 if (intel_crtc
->config
.has_dp_encoder
)
5883 intel_dp_set_m_n(intel_crtc
);
5885 intel_crtc
->lowfreq_avail
= false;
5887 intel_set_pipe_timings(intel_crtc
);
5889 if (intel_crtc
->config
.has_pch_encoder
) {
5890 intel_cpu_transcoder_set_m_n(intel_crtc
,
5891 &intel_crtc
->config
.fdi_m_n
);
5894 haswell_set_pipeconf(crtc
);
5896 intel_set_pipe_csc(crtc
);
5898 /* Set up the display plane register */
5899 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
| DISPPLANE_PIPE_CSC_ENABLE
);
5900 POSTING_READ(DSPCNTR(plane
));
5902 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
5904 intel_update_watermarks(dev
);
5909 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
5910 struct intel_crtc_config
*pipe_config
)
5912 struct drm_device
*dev
= crtc
->base
.dev
;
5913 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5914 enum intel_display_power_domain pfit_domain
;
5917 pipe_config
->cpu_transcoder
= crtc
->pipe
;
5918 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
5920 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
5921 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
5922 enum pipe trans_edp_pipe
;
5923 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
5925 WARN(1, "unknown pipe linked to edp transcoder\n");
5926 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
5927 case TRANS_DDI_EDP_INPUT_A_ON
:
5928 trans_edp_pipe
= PIPE_A
;
5930 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
5931 trans_edp_pipe
= PIPE_B
;
5933 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
5934 trans_edp_pipe
= PIPE_C
;
5938 if (trans_edp_pipe
== crtc
->pipe
)
5939 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
5942 if (!intel_display_power_enabled(dev
,
5943 POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
)))
5946 tmp
= I915_READ(PIPECONF(pipe_config
->cpu_transcoder
));
5947 if (!(tmp
& PIPECONF_ENABLE
))
5951 * Haswell has only FDI/PCH transcoder A. It is which is connected to
5952 * DDI E. So just check whether this pipe is wired to DDI E and whether
5953 * the PCH transcoder is on.
5955 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
5956 if ((tmp
& TRANS_DDI_PORT_MASK
) == TRANS_DDI_SELECT_PORT(PORT_E
) &&
5957 I915_READ(LPT_TRANSCONF
) & TRANS_ENABLE
) {
5958 pipe_config
->has_pch_encoder
= true;
5960 tmp
= I915_READ(FDI_RX_CTL(PIPE_A
));
5961 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
5962 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
5964 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
5967 intel_get_pipe_timings(crtc
, pipe_config
);
5969 pfit_domain
= POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
);
5970 if (intel_display_power_enabled(dev
, pfit_domain
))
5971 ironlake_get_pfit_config(crtc
, pipe_config
);
5973 pipe_config
->ips_enabled
= hsw_crtc_supports_ips(crtc
) &&
5974 (I915_READ(IPS_CTL
) & IPS_ENABLE
);
5976 pipe_config
->pixel_multiplier
= 1;
5981 static int intel_crtc_mode_set(struct drm_crtc
*crtc
,
5983 struct drm_framebuffer
*fb
)
5985 struct drm_device
*dev
= crtc
->dev
;
5986 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5987 struct drm_encoder_helper_funcs
*encoder_funcs
;
5988 struct intel_encoder
*encoder
;
5989 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5990 struct drm_display_mode
*adjusted_mode
=
5991 &intel_crtc
->config
.adjusted_mode
;
5992 struct drm_display_mode
*mode
= &intel_crtc
->config
.requested_mode
;
5993 int pipe
= intel_crtc
->pipe
;
5996 drm_vblank_pre_modeset(dev
, pipe
);
5998 ret
= dev_priv
->display
.crtc_mode_set(crtc
, x
, y
, fb
);
6000 drm_vblank_post_modeset(dev
, pipe
);
6005 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
6006 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6007 encoder
->base
.base
.id
,
6008 drm_get_encoder_name(&encoder
->base
),
6009 mode
->base
.id
, mode
->name
);
6010 if (encoder
->mode_set
) {
6011 encoder
->mode_set(encoder
);
6013 encoder_funcs
= encoder
->base
.helper_private
;
6014 encoder_funcs
->mode_set(&encoder
->base
, mode
, adjusted_mode
);
6021 static bool intel_eld_uptodate(struct drm_connector
*connector
,
6022 int reg_eldv
, uint32_t bits_eldv
,
6023 int reg_elda
, uint32_t bits_elda
,
6026 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6027 uint8_t *eld
= connector
->eld
;
6030 i
= I915_READ(reg_eldv
);
6039 i
= I915_READ(reg_elda
);
6041 I915_WRITE(reg_elda
, i
);
6043 for (i
= 0; i
< eld
[2]; i
++)
6044 if (I915_READ(reg_edid
) != *((uint32_t *)eld
+ i
))
6050 static void g4x_write_eld(struct drm_connector
*connector
,
6051 struct drm_crtc
*crtc
)
6053 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6054 uint8_t *eld
= connector
->eld
;
6059 i
= I915_READ(G4X_AUD_VID_DID
);
6061 if (i
== INTEL_AUDIO_DEVBLC
|| i
== INTEL_AUDIO_DEVCL
)
6062 eldv
= G4X_ELDV_DEVCL_DEVBLC
;
6064 eldv
= G4X_ELDV_DEVCTG
;
6066 if (intel_eld_uptodate(connector
,
6067 G4X_AUD_CNTL_ST
, eldv
,
6068 G4X_AUD_CNTL_ST
, G4X_ELD_ADDR
,
6069 G4X_HDMIW_HDMIEDID
))
6072 i
= I915_READ(G4X_AUD_CNTL_ST
);
6073 i
&= ~(eldv
| G4X_ELD_ADDR
);
6074 len
= (i
>> 9) & 0x1f; /* ELD buffer size */
6075 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
6080 len
= min_t(uint8_t, eld
[2], len
);
6081 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
6082 for (i
= 0; i
< len
; i
++)
6083 I915_WRITE(G4X_HDMIW_HDMIEDID
, *((uint32_t *)eld
+ i
));
6085 i
= I915_READ(G4X_AUD_CNTL_ST
);
6087 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
6090 static void haswell_write_eld(struct drm_connector
*connector
,
6091 struct drm_crtc
*crtc
)
6093 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6094 uint8_t *eld
= connector
->eld
;
6095 struct drm_device
*dev
= crtc
->dev
;
6096 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6100 int pipe
= to_intel_crtc(crtc
)->pipe
;
6103 int hdmiw_hdmiedid
= HSW_AUD_EDID_DATA(pipe
);
6104 int aud_cntl_st
= HSW_AUD_DIP_ELD_CTRL(pipe
);
6105 int aud_config
= HSW_AUD_CFG(pipe
);
6106 int aud_cntrl_st2
= HSW_AUD_PIN_ELD_CP_VLD
;
6109 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6111 /* Audio output enable */
6112 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6113 tmp
= I915_READ(aud_cntrl_st2
);
6114 tmp
|= (AUDIO_OUTPUT_ENABLE_A
<< (pipe
* 4));
6115 I915_WRITE(aud_cntrl_st2
, tmp
);
6117 /* Wait for 1 vertical blank */
6118 intel_wait_for_vblank(dev
, pipe
);
6120 /* Set ELD valid state */
6121 tmp
= I915_READ(aud_cntrl_st2
);
6122 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp
);
6123 tmp
|= (AUDIO_ELD_VALID_A
<< (pipe
* 4));
6124 I915_WRITE(aud_cntrl_st2
, tmp
);
6125 tmp
= I915_READ(aud_cntrl_st2
);
6126 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp
);
6128 /* Enable HDMI mode */
6129 tmp
= I915_READ(aud_config
);
6130 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp
);
6131 /* clear N_programing_enable and N_value_index */
6132 tmp
&= ~(AUD_CONFIG_N_VALUE_INDEX
| AUD_CONFIG_N_PROG_ENABLE
);
6133 I915_WRITE(aud_config
, tmp
);
6135 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
6137 eldv
= AUDIO_ELD_VALID_A
<< (pipe
* 4);
6138 intel_crtc
->eld_vld
= true;
6140 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
6141 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6142 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6143 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
6145 I915_WRITE(aud_config
, 0);
6147 if (intel_eld_uptodate(connector
,
6148 aud_cntrl_st2
, eldv
,
6149 aud_cntl_st
, IBX_ELD_ADDRESS
,
6153 i
= I915_READ(aud_cntrl_st2
);
6155 I915_WRITE(aud_cntrl_st2
, i
);
6160 i
= I915_READ(aud_cntl_st
);
6161 i
&= ~IBX_ELD_ADDRESS
;
6162 I915_WRITE(aud_cntl_st
, i
);
6163 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
6164 DRM_DEBUG_DRIVER("port num:%d\n", i
);
6166 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
6167 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
6168 for (i
= 0; i
< len
; i
++)
6169 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
6171 i
= I915_READ(aud_cntrl_st2
);
6173 I915_WRITE(aud_cntrl_st2
, i
);
6177 static void ironlake_write_eld(struct drm_connector
*connector
,
6178 struct drm_crtc
*crtc
)
6180 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6181 uint8_t *eld
= connector
->eld
;
6189 int pipe
= to_intel_crtc(crtc
)->pipe
;
6191 if (HAS_PCH_IBX(connector
->dev
)) {
6192 hdmiw_hdmiedid
= IBX_HDMIW_HDMIEDID(pipe
);
6193 aud_config
= IBX_AUD_CFG(pipe
);
6194 aud_cntl_st
= IBX_AUD_CNTL_ST(pipe
);
6195 aud_cntrl_st2
= IBX_AUD_CNTL_ST2
;
6197 hdmiw_hdmiedid
= CPT_HDMIW_HDMIEDID(pipe
);
6198 aud_config
= CPT_AUD_CFG(pipe
);
6199 aud_cntl_st
= CPT_AUD_CNTL_ST(pipe
);
6200 aud_cntrl_st2
= CPT_AUD_CNTRL_ST2
;
6203 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
6205 i
= I915_READ(aud_cntl_st
);
6206 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
6208 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6209 /* operate blindly on all ports */
6210 eldv
= IBX_ELD_VALIDB
;
6211 eldv
|= IBX_ELD_VALIDB
<< 4;
6212 eldv
|= IBX_ELD_VALIDB
<< 8;
6214 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i
));
6215 eldv
= IBX_ELD_VALIDB
<< ((i
- 1) * 4);
6218 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
6219 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6220 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6221 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
6223 I915_WRITE(aud_config
, 0);
6225 if (intel_eld_uptodate(connector
,
6226 aud_cntrl_st2
, eldv
,
6227 aud_cntl_st
, IBX_ELD_ADDRESS
,
6231 i
= I915_READ(aud_cntrl_st2
);
6233 I915_WRITE(aud_cntrl_st2
, i
);
6238 i
= I915_READ(aud_cntl_st
);
6239 i
&= ~IBX_ELD_ADDRESS
;
6240 I915_WRITE(aud_cntl_st
, i
);
6242 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
6243 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
6244 for (i
= 0; i
< len
; i
++)
6245 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
6247 i
= I915_READ(aud_cntrl_st2
);
6249 I915_WRITE(aud_cntrl_st2
, i
);
6252 void intel_write_eld(struct drm_encoder
*encoder
,
6253 struct drm_display_mode
*mode
)
6255 struct drm_crtc
*crtc
= encoder
->crtc
;
6256 struct drm_connector
*connector
;
6257 struct drm_device
*dev
= encoder
->dev
;
6258 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6260 connector
= drm_select_eld(encoder
, mode
);
6264 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6266 drm_get_connector_name(connector
),
6267 connector
->encoder
->base
.id
,
6268 drm_get_encoder_name(connector
->encoder
));
6270 connector
->eld
[6] = drm_av_sync_delay(connector
, mode
) / 2;
6272 if (dev_priv
->display
.write_eld
)
6273 dev_priv
->display
.write_eld(connector
, crtc
);
6276 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6277 void intel_crtc_load_lut(struct drm_crtc
*crtc
)
6279 struct drm_device
*dev
= crtc
->dev
;
6280 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6281 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6282 enum pipe pipe
= intel_crtc
->pipe
;
6283 int palreg
= PALETTE(pipe
);
6285 bool reenable_ips
= false;
6287 /* The clocks have to be on to load the palette. */
6288 if (!crtc
->enabled
|| !intel_crtc
->active
)
6291 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
6292 assert_pll_enabled(dev_priv
, pipe
);
6294 /* use legacy palette for Ironlake */
6295 if (HAS_PCH_SPLIT(dev
))
6296 palreg
= LGC_PALETTE(pipe
);
6298 /* Workaround : Do not read or write the pipe palette/gamma data while
6299 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6301 if (intel_crtc
->config
.ips_enabled
&&
6302 ((I915_READ(GAMMA_MODE(pipe
)) & GAMMA_MODE_MODE_MASK
) ==
6303 GAMMA_MODE_MODE_SPLIT
)) {
6304 hsw_disable_ips(intel_crtc
);
6305 reenable_ips
= true;
6308 for (i
= 0; i
< 256; i
++) {
6309 I915_WRITE(palreg
+ 4 * i
,
6310 (intel_crtc
->lut_r
[i
] << 16) |
6311 (intel_crtc
->lut_g
[i
] << 8) |
6312 intel_crtc
->lut_b
[i
]);
6316 hsw_enable_ips(intel_crtc
);
6319 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6321 struct drm_device
*dev
= crtc
->dev
;
6322 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6323 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6324 bool visible
= base
!= 0;
6327 if (intel_crtc
->cursor_visible
== visible
)
6330 cntl
= I915_READ(_CURACNTR
);
6332 /* On these chipsets we can only modify the base whilst
6333 * the cursor is disabled.
6335 I915_WRITE(_CURABASE
, base
);
6337 cntl
&= ~(CURSOR_FORMAT_MASK
);
6338 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6339 cntl
|= CURSOR_ENABLE
|
6340 CURSOR_GAMMA_ENABLE
|
6343 cntl
&= ~(CURSOR_ENABLE
| CURSOR_GAMMA_ENABLE
);
6344 I915_WRITE(_CURACNTR
, cntl
);
6346 intel_crtc
->cursor_visible
= visible
;
6349 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6351 struct drm_device
*dev
= crtc
->dev
;
6352 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6353 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6354 int pipe
= intel_crtc
->pipe
;
6355 bool visible
= base
!= 0;
6357 if (intel_crtc
->cursor_visible
!= visible
) {
6358 uint32_t cntl
= I915_READ(CURCNTR(pipe
));
6360 cntl
&= ~(CURSOR_MODE
| MCURSOR_PIPE_SELECT
);
6361 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
6362 cntl
|= pipe
<< 28; /* Connect to correct pipe */
6364 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
6365 cntl
|= CURSOR_MODE_DISABLE
;
6367 I915_WRITE(CURCNTR(pipe
), cntl
);
6369 intel_crtc
->cursor_visible
= visible
;
6371 /* and commit changes on next vblank */
6372 I915_WRITE(CURBASE(pipe
), base
);
6375 static void ivb_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6377 struct drm_device
*dev
= crtc
->dev
;
6378 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6379 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6380 int pipe
= intel_crtc
->pipe
;
6381 bool visible
= base
!= 0;
6383 if (intel_crtc
->cursor_visible
!= visible
) {
6384 uint32_t cntl
= I915_READ(CURCNTR_IVB(pipe
));
6386 cntl
&= ~CURSOR_MODE
;
6387 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
6389 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
6390 cntl
|= CURSOR_MODE_DISABLE
;
6392 if (IS_HASWELL(dev
))
6393 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
6394 I915_WRITE(CURCNTR_IVB(pipe
), cntl
);
6396 intel_crtc
->cursor_visible
= visible
;
6398 /* and commit changes on next vblank */
6399 I915_WRITE(CURBASE_IVB(pipe
), base
);
6402 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6403 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
6406 struct drm_device
*dev
= crtc
->dev
;
6407 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6408 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6409 int pipe
= intel_crtc
->pipe
;
6410 int x
= intel_crtc
->cursor_x
;
6411 int y
= intel_crtc
->cursor_y
;
6417 if (on
&& crtc
->enabled
&& crtc
->fb
) {
6418 base
= intel_crtc
->cursor_addr
;
6419 if (x
> (int) crtc
->fb
->width
)
6422 if (y
> (int) crtc
->fb
->height
)
6428 if (x
+ intel_crtc
->cursor_width
< 0)
6431 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
6434 pos
|= x
<< CURSOR_X_SHIFT
;
6437 if (y
+ intel_crtc
->cursor_height
< 0)
6440 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
6443 pos
|= y
<< CURSOR_Y_SHIFT
;
6445 visible
= base
!= 0;
6446 if (!visible
&& !intel_crtc
->cursor_visible
)
6449 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
6450 I915_WRITE(CURPOS_IVB(pipe
), pos
);
6451 ivb_update_cursor(crtc
, base
);
6453 I915_WRITE(CURPOS(pipe
), pos
);
6454 if (IS_845G(dev
) || IS_I865G(dev
))
6455 i845_update_cursor(crtc
, base
);
6457 i9xx_update_cursor(crtc
, base
);
6461 static int intel_crtc_cursor_set(struct drm_crtc
*crtc
,
6462 struct drm_file
*file
,
6464 uint32_t width
, uint32_t height
)
6466 struct drm_device
*dev
= crtc
->dev
;
6467 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6468 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6469 struct drm_i915_gem_object
*obj
;
6473 /* if we want to turn off the cursor ignore width and height */
6475 DRM_DEBUG_KMS("cursor off\n");
6478 mutex_lock(&dev
->struct_mutex
);
6482 /* Currently we only support 64x64 cursors */
6483 if (width
!= 64 || height
!= 64) {
6484 DRM_ERROR("we currently only support 64x64 cursors\n");
6488 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
6489 if (&obj
->base
== NULL
)
6492 if (obj
->base
.size
< width
* height
* 4) {
6493 DRM_ERROR("buffer is to small\n");
6498 /* we only need to pin inside GTT if cursor is non-phy */
6499 mutex_lock(&dev
->struct_mutex
);
6500 if (!dev_priv
->info
->cursor_needs_physical
) {
6503 if (obj
->tiling_mode
) {
6504 DRM_ERROR("cursor cannot be tiled\n");
6509 /* Note that the w/a also requires 2 PTE of padding following
6510 * the bo. We currently fill all unused PTE with the shadow
6511 * page and so we should always have valid PTE following the
6512 * cursor preventing the VT-d warning.
6515 if (need_vtd_wa(dev
))
6516 alignment
= 64*1024;
6518 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, NULL
);
6520 DRM_ERROR("failed to move cursor bo into the GTT\n");
6524 ret
= i915_gem_object_put_fence(obj
);
6526 DRM_ERROR("failed to release fence for cursor");
6530 addr
= obj
->gtt_offset
;
6532 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
6533 ret
= i915_gem_attach_phys_object(dev
, obj
,
6534 (intel_crtc
->pipe
== 0) ? I915_GEM_PHYS_CURSOR_0
: I915_GEM_PHYS_CURSOR_1
,
6537 DRM_ERROR("failed to attach phys object\n");
6540 addr
= obj
->phys_obj
->handle
->busaddr
;
6544 I915_WRITE(CURSIZE
, (height
<< 12) | width
);
6547 if (intel_crtc
->cursor_bo
) {
6548 if (dev_priv
->info
->cursor_needs_physical
) {
6549 if (intel_crtc
->cursor_bo
!= obj
)
6550 i915_gem_detach_phys_object(dev
, intel_crtc
->cursor_bo
);
6552 i915_gem_object_unpin(intel_crtc
->cursor_bo
);
6553 drm_gem_object_unreference(&intel_crtc
->cursor_bo
->base
);
6556 mutex_unlock(&dev
->struct_mutex
);
6558 intel_crtc
->cursor_addr
= addr
;
6559 intel_crtc
->cursor_bo
= obj
;
6560 intel_crtc
->cursor_width
= width
;
6561 intel_crtc
->cursor_height
= height
;
6563 intel_crtc_update_cursor(crtc
, intel_crtc
->cursor_bo
!= NULL
);
6567 i915_gem_object_unpin(obj
);
6569 mutex_unlock(&dev
->struct_mutex
);
6571 drm_gem_object_unreference_unlocked(&obj
->base
);
6575 static int intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
6577 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6579 intel_crtc
->cursor_x
= x
;
6580 intel_crtc
->cursor_y
= y
;
6582 intel_crtc_update_cursor(crtc
, intel_crtc
->cursor_bo
!= NULL
);
6587 /** Sets the color ramps on behalf of RandR */
6588 void intel_crtc_fb_gamma_set(struct drm_crtc
*crtc
, u16 red
, u16 green
,
6589 u16 blue
, int regno
)
6591 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6593 intel_crtc
->lut_r
[regno
] = red
>> 8;
6594 intel_crtc
->lut_g
[regno
] = green
>> 8;
6595 intel_crtc
->lut_b
[regno
] = blue
>> 8;
6598 void intel_crtc_fb_gamma_get(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
6599 u16
*blue
, int regno
)
6601 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6603 *red
= intel_crtc
->lut_r
[regno
] << 8;
6604 *green
= intel_crtc
->lut_g
[regno
] << 8;
6605 *blue
= intel_crtc
->lut_b
[regno
] << 8;
6608 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
6609 u16
*blue
, uint32_t start
, uint32_t size
)
6611 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
6612 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6614 for (i
= start
; i
< end
; i
++) {
6615 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
6616 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
6617 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
6620 intel_crtc_load_lut(crtc
);
6623 /* VESA 640x480x72Hz mode to set on the pipe */
6624 static struct drm_display_mode load_detect_mode
= {
6625 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
6626 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
6629 static struct drm_framebuffer
*
6630 intel_framebuffer_create(struct drm_device
*dev
,
6631 struct drm_mode_fb_cmd2
*mode_cmd
,
6632 struct drm_i915_gem_object
*obj
)
6634 struct intel_framebuffer
*intel_fb
;
6637 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
6639 drm_gem_object_unreference_unlocked(&obj
->base
);
6640 return ERR_PTR(-ENOMEM
);
6643 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
6645 drm_gem_object_unreference_unlocked(&obj
->base
);
6647 return ERR_PTR(ret
);
6650 return &intel_fb
->base
;
6654 intel_framebuffer_pitch_for_width(int width
, int bpp
)
6656 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
6657 return ALIGN(pitch
, 64);
6661 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
6663 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
6664 return ALIGN(pitch
* mode
->vdisplay
, PAGE_SIZE
);
6667 static struct drm_framebuffer
*
6668 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
6669 struct drm_display_mode
*mode
,
6672 struct drm_i915_gem_object
*obj
;
6673 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
6675 obj
= i915_gem_alloc_object(dev
,
6676 intel_framebuffer_size_for_mode(mode
, bpp
));
6678 return ERR_PTR(-ENOMEM
);
6680 mode_cmd
.width
= mode
->hdisplay
;
6681 mode_cmd
.height
= mode
->vdisplay
;
6682 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
6684 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
6686 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
6689 static struct drm_framebuffer
*
6690 mode_fits_in_fbdev(struct drm_device
*dev
,
6691 struct drm_display_mode
*mode
)
6693 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6694 struct drm_i915_gem_object
*obj
;
6695 struct drm_framebuffer
*fb
;
6697 if (dev_priv
->fbdev
== NULL
)
6700 obj
= dev_priv
->fbdev
->ifb
.obj
;
6704 fb
= &dev_priv
->fbdev
->ifb
.base
;
6705 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
6706 fb
->bits_per_pixel
))
6709 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
6715 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
6716 struct drm_display_mode
*mode
,
6717 struct intel_load_detect_pipe
*old
)
6719 struct intel_crtc
*intel_crtc
;
6720 struct intel_encoder
*intel_encoder
=
6721 intel_attached_encoder(connector
);
6722 struct drm_crtc
*possible_crtc
;
6723 struct drm_encoder
*encoder
= &intel_encoder
->base
;
6724 struct drm_crtc
*crtc
= NULL
;
6725 struct drm_device
*dev
= encoder
->dev
;
6726 struct drm_framebuffer
*fb
;
6729 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6730 connector
->base
.id
, drm_get_connector_name(connector
),
6731 encoder
->base
.id
, drm_get_encoder_name(encoder
));
6734 * Algorithm gets a little messy:
6736 * - if the connector already has an assigned crtc, use it (but make
6737 * sure it's on first)
6739 * - try to find the first unused crtc that can drive this connector,
6740 * and use that if we find one
6743 /* See if we already have a CRTC for this connector */
6744 if (encoder
->crtc
) {
6745 crtc
= encoder
->crtc
;
6747 mutex_lock(&crtc
->mutex
);
6749 old
->dpms_mode
= connector
->dpms
;
6750 old
->load_detect_temp
= false;
6752 /* Make sure the crtc and connector are running */
6753 if (connector
->dpms
!= DRM_MODE_DPMS_ON
)
6754 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
6759 /* Find an unused one (if possible) */
6760 list_for_each_entry(possible_crtc
, &dev
->mode_config
.crtc_list
, head
) {
6762 if (!(encoder
->possible_crtcs
& (1 << i
)))
6764 if (!possible_crtc
->enabled
) {
6765 crtc
= possible_crtc
;
6771 * If we didn't find an unused CRTC, don't use any.
6774 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6778 mutex_lock(&crtc
->mutex
);
6779 intel_encoder
->new_crtc
= to_intel_crtc(crtc
);
6780 to_intel_connector(connector
)->new_encoder
= intel_encoder
;
6782 intel_crtc
= to_intel_crtc(crtc
);
6783 old
->dpms_mode
= connector
->dpms
;
6784 old
->load_detect_temp
= true;
6785 old
->release_fb
= NULL
;
6788 mode
= &load_detect_mode
;
6790 /* We need a framebuffer large enough to accommodate all accesses
6791 * that the plane may generate whilst we perform load detection.
6792 * We can not rely on the fbcon either being present (we get called
6793 * during its initialisation to detect all boot displays, or it may
6794 * not even exist) or that it is large enough to satisfy the
6797 fb
= mode_fits_in_fbdev(dev
, mode
);
6799 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6800 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
6801 old
->release_fb
= fb
;
6803 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6805 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6806 mutex_unlock(&crtc
->mutex
);
6810 if (intel_set_mode(crtc
, mode
, 0, 0, fb
)) {
6811 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6812 if (old
->release_fb
)
6813 old
->release_fb
->funcs
->destroy(old
->release_fb
);
6814 mutex_unlock(&crtc
->mutex
);
6818 /* let the connector get through one full cycle before testing */
6819 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
6823 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
6824 struct intel_load_detect_pipe
*old
)
6826 struct intel_encoder
*intel_encoder
=
6827 intel_attached_encoder(connector
);
6828 struct drm_encoder
*encoder
= &intel_encoder
->base
;
6829 struct drm_crtc
*crtc
= encoder
->crtc
;
6831 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6832 connector
->base
.id
, drm_get_connector_name(connector
),
6833 encoder
->base
.id
, drm_get_encoder_name(encoder
));
6835 if (old
->load_detect_temp
) {
6836 to_intel_connector(connector
)->new_encoder
= NULL
;
6837 intel_encoder
->new_crtc
= NULL
;
6838 intel_set_mode(crtc
, NULL
, 0, 0, NULL
);
6840 if (old
->release_fb
) {
6841 drm_framebuffer_unregister_private(old
->release_fb
);
6842 drm_framebuffer_unreference(old
->release_fb
);
6845 mutex_unlock(&crtc
->mutex
);
6849 /* Switch crtc and encoder back off if necessary */
6850 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
)
6851 connector
->funcs
->dpms(connector
, old
->dpms_mode
);
6853 mutex_unlock(&crtc
->mutex
);
6856 /* Returns the clock of the currently programmed mode of the given pipe. */
6857 static int intel_crtc_clock_get(struct drm_device
*dev
, struct drm_crtc
*crtc
)
6859 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6860 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6861 int pipe
= intel_crtc
->pipe
;
6862 u32 dpll
= I915_READ(DPLL(pipe
));
6864 intel_clock_t clock
;
6866 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
6867 fp
= I915_READ(FP0(pipe
));
6869 fp
= I915_READ(FP1(pipe
));
6871 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
6872 if (IS_PINEVIEW(dev
)) {
6873 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
6874 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
6876 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
6877 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
6880 if (!IS_GEN2(dev
)) {
6881 if (IS_PINEVIEW(dev
))
6882 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
6883 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
6885 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
6886 DPLL_FPA01_P1_POST_DIV_SHIFT
);
6888 switch (dpll
& DPLL_MODE_MASK
) {
6889 case DPLLB_MODE_DAC_SERIAL
:
6890 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
6893 case DPLLB_MODE_LVDS
:
6894 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
6898 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6899 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
6903 if (IS_PINEVIEW(dev
))
6904 pineview_clock(96000, &clock
);
6906 i9xx_clock(96000, &clock
);
6908 bool is_lvds
= (pipe
== 1) && (I915_READ(LVDS
) & LVDS_PORT_EN
);
6911 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
6912 DPLL_FPA01_P1_POST_DIV_SHIFT
);
6915 if ((dpll
& PLL_REF_INPUT_MASK
) ==
6916 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
6917 /* XXX: might not be 66MHz */
6918 i9xx_clock(66000, &clock
);
6920 i9xx_clock(48000, &clock
);
6922 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
6925 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
6926 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
6928 if (dpll
& PLL_P2_DIVIDE_BY_4
)
6933 i9xx_clock(48000, &clock
);
6937 /* XXX: It would be nice to validate the clocks, but we can't reuse
6938 * i830PllIsValid() because it relies on the xf86_config connector
6939 * configuration being accurate, which it isn't necessarily.
6945 /** Returns the currently programmed mode of the given pipe. */
6946 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
6947 struct drm_crtc
*crtc
)
6949 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6950 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6951 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
6952 struct drm_display_mode
*mode
;
6953 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
6954 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
6955 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
6956 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
6958 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
6962 mode
->clock
= intel_crtc_clock_get(dev
, crtc
);
6963 mode
->hdisplay
= (htot
& 0xffff) + 1;
6964 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
6965 mode
->hsync_start
= (hsync
& 0xffff) + 1;
6966 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
6967 mode
->vdisplay
= (vtot
& 0xffff) + 1;
6968 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
6969 mode
->vsync_start
= (vsync
& 0xffff) + 1;
6970 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
6972 drm_mode_set_name(mode
);
6977 static void intel_increase_pllclock(struct drm_crtc
*crtc
)
6979 struct drm_device
*dev
= crtc
->dev
;
6980 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6981 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6982 int pipe
= intel_crtc
->pipe
;
6983 int dpll_reg
= DPLL(pipe
);
6986 if (HAS_PCH_SPLIT(dev
))
6989 if (!dev_priv
->lvds_downclock_avail
)
6992 dpll
= I915_READ(dpll_reg
);
6993 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
6994 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6996 assert_panel_unlocked(dev_priv
, pipe
);
6998 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
6999 I915_WRITE(dpll_reg
, dpll
);
7000 intel_wait_for_vblank(dev
, pipe
);
7002 dpll
= I915_READ(dpll_reg
);
7003 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
7004 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7008 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
7010 struct drm_device
*dev
= crtc
->dev
;
7011 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7012 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7014 if (HAS_PCH_SPLIT(dev
))
7017 if (!dev_priv
->lvds_downclock_avail
)
7021 * Since this is called by a timer, we should never get here in
7024 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
7025 int pipe
= intel_crtc
->pipe
;
7026 int dpll_reg
= DPLL(pipe
);
7029 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7031 assert_panel_unlocked(dev_priv
, pipe
);
7033 dpll
= I915_READ(dpll_reg
);
7034 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
7035 I915_WRITE(dpll_reg
, dpll
);
7036 intel_wait_for_vblank(dev
, pipe
);
7037 dpll
= I915_READ(dpll_reg
);
7038 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
7039 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7044 void intel_mark_busy(struct drm_device
*dev
)
7046 i915_update_gfx_val(dev
->dev_private
);
7049 void intel_mark_idle(struct drm_device
*dev
)
7051 struct drm_crtc
*crtc
;
7053 if (!i915_powersave
)
7056 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
7060 intel_decrease_pllclock(crtc
);
7064 void intel_mark_fb_busy(struct drm_i915_gem_object
*obj
,
7065 struct intel_ring_buffer
*ring
)
7067 struct drm_device
*dev
= obj
->base
.dev
;
7068 struct drm_crtc
*crtc
;
7070 if (!i915_powersave
)
7073 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
7077 if (to_intel_framebuffer(crtc
->fb
)->obj
!= obj
)
7080 intel_increase_pllclock(crtc
);
7081 if (ring
&& intel_fbc_enabled(dev
))
7082 ring
->fbc_dirty
= true;
7086 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
7088 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7089 struct drm_device
*dev
= crtc
->dev
;
7090 struct intel_unpin_work
*work
;
7091 unsigned long flags
;
7093 spin_lock_irqsave(&dev
->event_lock
, flags
);
7094 work
= intel_crtc
->unpin_work
;
7095 intel_crtc
->unpin_work
= NULL
;
7096 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7099 cancel_work_sync(&work
->work
);
7103 intel_crtc_cursor_set(crtc
, NULL
, 0, 0, 0);
7105 drm_crtc_cleanup(crtc
);
7110 static void intel_unpin_work_fn(struct work_struct
*__work
)
7112 struct intel_unpin_work
*work
=
7113 container_of(__work
, struct intel_unpin_work
, work
);
7114 struct drm_device
*dev
= work
->crtc
->dev
;
7116 mutex_lock(&dev
->struct_mutex
);
7117 intel_unpin_fb_obj(work
->old_fb_obj
);
7118 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
7119 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
7121 intel_update_fbc(dev
);
7122 mutex_unlock(&dev
->struct_mutex
);
7124 BUG_ON(atomic_read(&to_intel_crtc(work
->crtc
)->unpin_work_count
) == 0);
7125 atomic_dec(&to_intel_crtc(work
->crtc
)->unpin_work_count
);
7130 static void do_intel_finish_page_flip(struct drm_device
*dev
,
7131 struct drm_crtc
*crtc
)
7133 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7134 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7135 struct intel_unpin_work
*work
;
7136 unsigned long flags
;
7138 /* Ignore early vblank irqs */
7139 if (intel_crtc
== NULL
)
7142 spin_lock_irqsave(&dev
->event_lock
, flags
);
7143 work
= intel_crtc
->unpin_work
;
7145 /* Ensure we don't miss a work->pending update ... */
7148 if (work
== NULL
|| atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
7149 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7153 /* and that the unpin work is consistent wrt ->pending. */
7156 intel_crtc
->unpin_work
= NULL
;
7159 drm_send_vblank_event(dev
, intel_crtc
->pipe
, work
->event
);
7161 drm_vblank_put(dev
, intel_crtc
->pipe
);
7163 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7165 wake_up_all(&dev_priv
->pending_flip_queue
);
7167 queue_work(dev_priv
->wq
, &work
->work
);
7169 trace_i915_flip_complete(intel_crtc
->plane
, work
->pending_flip_obj
);
7172 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
7174 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7175 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
7177 do_intel_finish_page_flip(dev
, crtc
);
7180 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
7182 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7183 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
7185 do_intel_finish_page_flip(dev
, crtc
);
7188 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
7190 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7191 struct intel_crtc
*intel_crtc
=
7192 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
7193 unsigned long flags
;
7195 /* NB: An MMIO update of the plane base pointer will also
7196 * generate a page-flip completion irq, i.e. every modeset
7197 * is also accompanied by a spurious intel_prepare_page_flip().
7199 spin_lock_irqsave(&dev
->event_lock
, flags
);
7200 if (intel_crtc
->unpin_work
)
7201 atomic_inc_not_zero(&intel_crtc
->unpin_work
->pending
);
7202 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7205 inline static void intel_mark_page_flip_active(struct intel_crtc
*intel_crtc
)
7207 /* Ensure that the work item is consistent when activating it ... */
7209 atomic_set(&intel_crtc
->unpin_work
->pending
, INTEL_FLIP_PENDING
);
7210 /* and that it is marked active as soon as the irq could fire. */
7214 static int intel_gen2_queue_flip(struct drm_device
*dev
,
7215 struct drm_crtc
*crtc
,
7216 struct drm_framebuffer
*fb
,
7217 struct drm_i915_gem_object
*obj
)
7219 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7220 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7222 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7225 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7229 ret
= intel_ring_begin(ring
, 6);
7233 /* Can't queue multiple flips, so wait for the previous
7234 * one to finish before executing the next.
7236 if (intel_crtc
->plane
)
7237 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
7239 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
7240 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
7241 intel_ring_emit(ring
, MI_NOOP
);
7242 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
7243 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7244 intel_ring_emit(ring
, fb
->pitches
[0]);
7245 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
7246 intel_ring_emit(ring
, 0); /* aux display base address, unused */
7248 intel_mark_page_flip_active(intel_crtc
);
7249 intel_ring_advance(ring
);
7253 intel_unpin_fb_obj(obj
);
7258 static int intel_gen3_queue_flip(struct drm_device
*dev
,
7259 struct drm_crtc
*crtc
,
7260 struct drm_framebuffer
*fb
,
7261 struct drm_i915_gem_object
*obj
)
7263 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7264 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7266 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7269 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7273 ret
= intel_ring_begin(ring
, 6);
7277 if (intel_crtc
->plane
)
7278 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
7280 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
7281 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
7282 intel_ring_emit(ring
, MI_NOOP
);
7283 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
7284 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7285 intel_ring_emit(ring
, fb
->pitches
[0]);
7286 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
7287 intel_ring_emit(ring
, MI_NOOP
);
7289 intel_mark_page_flip_active(intel_crtc
);
7290 intel_ring_advance(ring
);
7294 intel_unpin_fb_obj(obj
);
7299 static int intel_gen4_queue_flip(struct drm_device
*dev
,
7300 struct drm_crtc
*crtc
,
7301 struct drm_framebuffer
*fb
,
7302 struct drm_i915_gem_object
*obj
)
7304 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7305 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7306 uint32_t pf
, pipesrc
;
7307 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7310 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7314 ret
= intel_ring_begin(ring
, 4);
7318 /* i965+ uses the linear or tiled offsets from the
7319 * Display Registers (which do not change across a page-flip)
7320 * so we need only reprogram the base address.
7322 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
7323 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7324 intel_ring_emit(ring
, fb
->pitches
[0]);
7325 intel_ring_emit(ring
,
7326 (obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
) |
7329 /* XXX Enabling the panel-fitter across page-flip is so far
7330 * untested on non-native modes, so ignore it for now.
7331 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7334 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
7335 intel_ring_emit(ring
, pf
| pipesrc
);
7337 intel_mark_page_flip_active(intel_crtc
);
7338 intel_ring_advance(ring
);
7342 intel_unpin_fb_obj(obj
);
7347 static int intel_gen6_queue_flip(struct drm_device
*dev
,
7348 struct drm_crtc
*crtc
,
7349 struct drm_framebuffer
*fb
,
7350 struct drm_i915_gem_object
*obj
)
7352 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7353 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7354 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7355 uint32_t pf
, pipesrc
;
7358 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7362 ret
= intel_ring_begin(ring
, 4);
7366 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
7367 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7368 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
7369 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
7371 /* Contrary to the suggestions in the documentation,
7372 * "Enable Panel Fitter" does not seem to be required when page
7373 * flipping with a non-native mode, and worse causes a normal
7375 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7378 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
7379 intel_ring_emit(ring
, pf
| pipesrc
);
7381 intel_mark_page_flip_active(intel_crtc
);
7382 intel_ring_advance(ring
);
7386 intel_unpin_fb_obj(obj
);
7392 * On gen7 we currently use the blit ring because (in early silicon at least)
7393 * the render ring doesn't give us interrpts for page flip completion, which
7394 * means clients will hang after the first flip is queued. Fortunately the
7395 * blit ring generates interrupts properly, so use it instead.
7397 static int intel_gen7_queue_flip(struct drm_device
*dev
,
7398 struct drm_crtc
*crtc
,
7399 struct drm_framebuffer
*fb
,
7400 struct drm_i915_gem_object
*obj
)
7402 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7403 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7404 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[BCS
];
7405 uint32_t plane_bit
= 0;
7408 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7412 switch(intel_crtc
->plane
) {
7414 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
7417 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
7420 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
7423 WARN_ONCE(1, "unknown plane in flip command\n");
7428 ret
= intel_ring_begin(ring
, 4);
7432 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
7433 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
7434 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
7435 intel_ring_emit(ring
, (MI_NOOP
));
7437 intel_mark_page_flip_active(intel_crtc
);
7438 intel_ring_advance(ring
);
7442 intel_unpin_fb_obj(obj
);
7447 static int intel_default_queue_flip(struct drm_device
*dev
,
7448 struct drm_crtc
*crtc
,
7449 struct drm_framebuffer
*fb
,
7450 struct drm_i915_gem_object
*obj
)
7455 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
7456 struct drm_framebuffer
*fb
,
7457 struct drm_pending_vblank_event
*event
)
7459 struct drm_device
*dev
= crtc
->dev
;
7460 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7461 struct drm_framebuffer
*old_fb
= crtc
->fb
;
7462 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(fb
)->obj
;
7463 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7464 struct intel_unpin_work
*work
;
7465 unsigned long flags
;
7468 /* Can't change pixel format via MI display flips. */
7469 if (fb
->pixel_format
!= crtc
->fb
->pixel_format
)
7473 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7474 * Note that pitch changes could also affect these register.
7476 if (INTEL_INFO(dev
)->gen
> 3 &&
7477 (fb
->offsets
[0] != crtc
->fb
->offsets
[0] ||
7478 fb
->pitches
[0] != crtc
->fb
->pitches
[0]))
7481 work
= kzalloc(sizeof *work
, GFP_KERNEL
);
7485 work
->event
= event
;
7487 work
->old_fb_obj
= to_intel_framebuffer(old_fb
)->obj
;
7488 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
7490 ret
= drm_vblank_get(dev
, intel_crtc
->pipe
);
7494 /* We borrow the event spin lock for protecting unpin_work */
7495 spin_lock_irqsave(&dev
->event_lock
, flags
);
7496 if (intel_crtc
->unpin_work
) {
7497 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7499 drm_vblank_put(dev
, intel_crtc
->pipe
);
7501 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7504 intel_crtc
->unpin_work
= work
;
7505 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7507 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
7508 flush_workqueue(dev_priv
->wq
);
7510 ret
= i915_mutex_lock_interruptible(dev
);
7514 /* Reference the objects for the scheduled work. */
7515 drm_gem_object_reference(&work
->old_fb_obj
->base
);
7516 drm_gem_object_reference(&obj
->base
);
7520 work
->pending_flip_obj
= obj
;
7522 work
->enable_stall_check
= true;
7524 atomic_inc(&intel_crtc
->unpin_work_count
);
7525 intel_crtc
->reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
7527 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
);
7529 goto cleanup_pending
;
7531 intel_disable_fbc(dev
);
7532 intel_mark_fb_busy(obj
, NULL
);
7533 mutex_unlock(&dev
->struct_mutex
);
7535 trace_i915_flip_request(intel_crtc
->plane
, obj
);
7540 atomic_dec(&intel_crtc
->unpin_work_count
);
7542 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
7543 drm_gem_object_unreference(&obj
->base
);
7544 mutex_unlock(&dev
->struct_mutex
);
7547 spin_lock_irqsave(&dev
->event_lock
, flags
);
7548 intel_crtc
->unpin_work
= NULL
;
7549 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7551 drm_vblank_put(dev
, intel_crtc
->pipe
);
7558 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
7559 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
7560 .load_lut
= intel_crtc_load_lut
,
7563 static bool intel_encoder_crtc_ok(struct drm_encoder
*encoder
,
7564 struct drm_crtc
*crtc
)
7566 struct drm_device
*dev
;
7567 struct drm_crtc
*tmp
;
7570 WARN(!crtc
, "checking null crtc?\n");
7574 list_for_each_entry(tmp
, &dev
->mode_config
.crtc_list
, head
) {
7580 if (encoder
->possible_crtcs
& crtc_mask
)
7586 * intel_modeset_update_staged_output_state
7588 * Updates the staged output configuration state, e.g. after we've read out the
7591 static void intel_modeset_update_staged_output_state(struct drm_device
*dev
)
7593 struct intel_encoder
*encoder
;
7594 struct intel_connector
*connector
;
7596 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7598 connector
->new_encoder
=
7599 to_intel_encoder(connector
->base
.encoder
);
7602 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7605 to_intel_crtc(encoder
->base
.crtc
);
7610 * intel_modeset_commit_output_state
7612 * This function copies the stage display pipe configuration to the real one.
7614 static void intel_modeset_commit_output_state(struct drm_device
*dev
)
7616 struct intel_encoder
*encoder
;
7617 struct intel_connector
*connector
;
7619 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7621 connector
->base
.encoder
= &connector
->new_encoder
->base
;
7624 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7626 encoder
->base
.crtc
= &encoder
->new_crtc
->base
;
7631 connected_sink_compute_bpp(struct intel_connector
* connector
,
7632 struct intel_crtc_config
*pipe_config
)
7634 int bpp
= pipe_config
->pipe_bpp
;
7636 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7637 connector
->base
.base
.id
,
7638 drm_get_connector_name(&connector
->base
));
7640 /* Don't use an invalid EDID bpc value */
7641 if (connector
->base
.display_info
.bpc
&&
7642 connector
->base
.display_info
.bpc
* 3 < bpp
) {
7643 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7644 bpp
, connector
->base
.display_info
.bpc
*3);
7645 pipe_config
->pipe_bpp
= connector
->base
.display_info
.bpc
*3;
7648 /* Clamp bpp to 8 on screens without EDID 1.4 */
7649 if (connector
->base
.display_info
.bpc
== 0 && bpp
> 24) {
7650 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7652 pipe_config
->pipe_bpp
= 24;
7657 compute_baseline_pipe_bpp(struct intel_crtc
*crtc
,
7658 struct drm_framebuffer
*fb
,
7659 struct intel_crtc_config
*pipe_config
)
7661 struct drm_device
*dev
= crtc
->base
.dev
;
7662 struct intel_connector
*connector
;
7665 switch (fb
->pixel_format
) {
7667 bpp
= 8*3; /* since we go through a colormap */
7669 case DRM_FORMAT_XRGB1555
:
7670 case DRM_FORMAT_ARGB1555
:
7671 /* checked in intel_framebuffer_init already */
7672 if (WARN_ON(INTEL_INFO(dev
)->gen
> 3))
7674 case DRM_FORMAT_RGB565
:
7675 bpp
= 6*3; /* min is 18bpp */
7677 case DRM_FORMAT_XBGR8888
:
7678 case DRM_FORMAT_ABGR8888
:
7679 /* checked in intel_framebuffer_init already */
7680 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
7682 case DRM_FORMAT_XRGB8888
:
7683 case DRM_FORMAT_ARGB8888
:
7686 case DRM_FORMAT_XRGB2101010
:
7687 case DRM_FORMAT_ARGB2101010
:
7688 case DRM_FORMAT_XBGR2101010
:
7689 case DRM_FORMAT_ABGR2101010
:
7690 /* checked in intel_framebuffer_init already */
7691 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
7695 /* TODO: gen4+ supports 16 bpc floating point, too. */
7697 DRM_DEBUG_KMS("unsupported depth\n");
7701 pipe_config
->pipe_bpp
= bpp
;
7703 /* Clamp display bpp to EDID value */
7704 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7706 if (!connector
->new_encoder
||
7707 connector
->new_encoder
->new_crtc
!= crtc
)
7710 connected_sink_compute_bpp(connector
, pipe_config
);
7716 static void intel_dump_pipe_config(struct intel_crtc
*crtc
,
7717 struct intel_crtc_config
*pipe_config
,
7718 const char *context
)
7720 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc
->base
.base
.id
,
7721 context
, pipe_name(crtc
->pipe
));
7723 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config
->cpu_transcoder
));
7724 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7725 pipe_config
->pipe_bpp
, pipe_config
->dither
);
7726 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7727 pipe_config
->has_pch_encoder
,
7728 pipe_config
->fdi_lanes
,
7729 pipe_config
->fdi_m_n
.gmch_m
, pipe_config
->fdi_m_n
.gmch_n
,
7730 pipe_config
->fdi_m_n
.link_m
, pipe_config
->fdi_m_n
.link_n
,
7731 pipe_config
->fdi_m_n
.tu
);
7732 DRM_DEBUG_KMS("requested mode:\n");
7733 drm_mode_debug_printmodeline(&pipe_config
->requested_mode
);
7734 DRM_DEBUG_KMS("adjusted mode:\n");
7735 drm_mode_debug_printmodeline(&pipe_config
->adjusted_mode
);
7736 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7737 pipe_config
->gmch_pfit
.control
,
7738 pipe_config
->gmch_pfit
.pgm_ratios
,
7739 pipe_config
->gmch_pfit
.lvds_border_bits
);
7740 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
7741 pipe_config
->pch_pfit
.pos
,
7742 pipe_config
->pch_pfit
.size
);
7743 DRM_DEBUG_KMS("ips: %i\n", pipe_config
->ips_enabled
);
7746 static bool check_encoder_cloning(struct drm_crtc
*crtc
)
7748 int num_encoders
= 0;
7749 bool uncloneable_encoders
= false;
7750 struct intel_encoder
*encoder
;
7752 list_for_each_entry(encoder
, &crtc
->dev
->mode_config
.encoder_list
,
7754 if (&encoder
->new_crtc
->base
!= crtc
)
7758 if (!encoder
->cloneable
)
7759 uncloneable_encoders
= true;
7762 return !(num_encoders
> 1 && uncloneable_encoders
);
7765 static struct intel_crtc_config
*
7766 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
7767 struct drm_framebuffer
*fb
,
7768 struct drm_display_mode
*mode
)
7770 struct drm_device
*dev
= crtc
->dev
;
7771 struct drm_encoder_helper_funcs
*encoder_funcs
;
7772 struct intel_encoder
*encoder
;
7773 struct intel_crtc_config
*pipe_config
;
7774 int plane_bpp
, ret
= -EINVAL
;
7777 if (!check_encoder_cloning(crtc
)) {
7778 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
7779 return ERR_PTR(-EINVAL
);
7782 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
7784 return ERR_PTR(-ENOMEM
);
7786 drm_mode_copy(&pipe_config
->adjusted_mode
, mode
);
7787 drm_mode_copy(&pipe_config
->requested_mode
, mode
);
7788 pipe_config
->cpu_transcoder
= to_intel_crtc(crtc
)->pipe
;
7789 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
7791 /* Compute a starting value for pipe_config->pipe_bpp taking the source
7792 * plane pixel format and any sink constraints into account. Returns the
7793 * source plane bpp so that dithering can be selected on mismatches
7794 * after encoders and crtc also have had their say. */
7795 plane_bpp
= compute_baseline_pipe_bpp(to_intel_crtc(crtc
),
7801 /* Ensure the port clock defaults are reset when retrying. */
7802 pipe_config
->port_clock
= 0;
7803 pipe_config
->pixel_multiplier
= 1;
7805 /* Pass our mode to the connectors and the CRTC to give them a chance to
7806 * adjust it according to limitations or connector properties, and also
7807 * a chance to reject the mode entirely.
7809 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7812 if (&encoder
->new_crtc
->base
!= crtc
)
7815 if (encoder
->compute_config
) {
7816 if (!(encoder
->compute_config(encoder
, pipe_config
))) {
7817 DRM_DEBUG_KMS("Encoder config failure\n");
7824 encoder_funcs
= encoder
->base
.helper_private
;
7825 if (!(encoder_funcs
->mode_fixup(&encoder
->base
,
7826 &pipe_config
->requested_mode
,
7827 &pipe_config
->adjusted_mode
))) {
7828 DRM_DEBUG_KMS("Encoder fixup failed\n");
7833 /* Set default port clock if not overwritten by the encoder. Needs to be
7834 * done afterwards in case the encoder adjusts the mode. */
7835 if (!pipe_config
->port_clock
)
7836 pipe_config
->port_clock
= pipe_config
->adjusted_mode
.clock
;
7838 ret
= intel_crtc_compute_config(to_intel_crtc(crtc
), pipe_config
);
7840 DRM_DEBUG_KMS("CRTC fixup failed\n");
7845 if (WARN(!retry
, "loop in pipe configuration computation\n")) {
7850 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7855 pipe_config
->dither
= pipe_config
->pipe_bpp
!= plane_bpp
;
7856 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7857 plane_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
7862 return ERR_PTR(ret
);
7865 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7866 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7868 intel_modeset_affected_pipes(struct drm_crtc
*crtc
, unsigned *modeset_pipes
,
7869 unsigned *prepare_pipes
, unsigned *disable_pipes
)
7871 struct intel_crtc
*intel_crtc
;
7872 struct drm_device
*dev
= crtc
->dev
;
7873 struct intel_encoder
*encoder
;
7874 struct intel_connector
*connector
;
7875 struct drm_crtc
*tmp_crtc
;
7877 *disable_pipes
= *modeset_pipes
= *prepare_pipes
= 0;
7879 /* Check which crtcs have changed outputs connected to them, these need
7880 * to be part of the prepare_pipes mask. We don't (yet) support global
7881 * modeset across multiple crtcs, so modeset_pipes will only have one
7882 * bit set at most. */
7883 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7885 if (connector
->base
.encoder
== &connector
->new_encoder
->base
)
7888 if (connector
->base
.encoder
) {
7889 tmp_crtc
= connector
->base
.encoder
->crtc
;
7891 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
7894 if (connector
->new_encoder
)
7896 1 << connector
->new_encoder
->new_crtc
->pipe
;
7899 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7901 if (encoder
->base
.crtc
== &encoder
->new_crtc
->base
)
7904 if (encoder
->base
.crtc
) {
7905 tmp_crtc
= encoder
->base
.crtc
;
7907 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
7910 if (encoder
->new_crtc
)
7911 *prepare_pipes
|= 1 << encoder
->new_crtc
->pipe
;
7914 /* Check for any pipes that will be fully disabled ... */
7915 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
7919 /* Don't try to disable disabled crtcs. */
7920 if (!intel_crtc
->base
.enabled
)
7923 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7925 if (encoder
->new_crtc
== intel_crtc
)
7930 *disable_pipes
|= 1 << intel_crtc
->pipe
;
7934 /* set_mode is also used to update properties on life display pipes. */
7935 intel_crtc
= to_intel_crtc(crtc
);
7937 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
7940 * For simplicity do a full modeset on any pipe where the output routing
7941 * changed. We could be more clever, but that would require us to be
7942 * more careful with calling the relevant encoder->mode_set functions.
7945 *modeset_pipes
= *prepare_pipes
;
7947 /* ... and mask these out. */
7948 *modeset_pipes
&= ~(*disable_pipes
);
7949 *prepare_pipes
&= ~(*disable_pipes
);
7952 * HACK: We don't (yet) fully support global modesets. intel_set_config
7953 * obies this rule, but the modeset restore mode of
7954 * intel_modeset_setup_hw_state does not.
7956 *modeset_pipes
&= 1 << intel_crtc
->pipe
;
7957 *prepare_pipes
&= 1 << intel_crtc
->pipe
;
7959 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7960 *modeset_pipes
, *prepare_pipes
, *disable_pipes
);
7963 static bool intel_crtc_in_use(struct drm_crtc
*crtc
)
7965 struct drm_encoder
*encoder
;
7966 struct drm_device
*dev
= crtc
->dev
;
7968 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
)
7969 if (encoder
->crtc
== crtc
)
7976 intel_modeset_update_state(struct drm_device
*dev
, unsigned prepare_pipes
)
7978 struct intel_encoder
*intel_encoder
;
7979 struct intel_crtc
*intel_crtc
;
7980 struct drm_connector
*connector
;
7982 list_for_each_entry(intel_encoder
, &dev
->mode_config
.encoder_list
,
7984 if (!intel_encoder
->base
.crtc
)
7987 intel_crtc
= to_intel_crtc(intel_encoder
->base
.crtc
);
7989 if (prepare_pipes
& (1 << intel_crtc
->pipe
))
7990 intel_encoder
->connectors_active
= false;
7993 intel_modeset_commit_output_state(dev
);
7995 /* Update computed state. */
7996 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
7998 intel_crtc
->base
.enabled
= intel_crtc_in_use(&intel_crtc
->base
);
8001 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
8002 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
8005 intel_crtc
= to_intel_crtc(connector
->encoder
->crtc
);
8007 if (prepare_pipes
& (1 << intel_crtc
->pipe
)) {
8008 struct drm_property
*dpms_property
=
8009 dev
->mode_config
.dpms_property
;
8011 connector
->dpms
= DRM_MODE_DPMS_ON
;
8012 drm_object_property_set_value(&connector
->base
,
8016 intel_encoder
= to_intel_encoder(connector
->encoder
);
8017 intel_encoder
->connectors_active
= true;
8023 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8024 list_for_each_entry((intel_crtc), \
8025 &(dev)->mode_config.crtc_list, \
8027 if (mask & (1 <<(intel_crtc)->pipe))
8030 intel_pipe_config_compare(struct drm_device
*dev
,
8031 struct intel_crtc_config
*current_config
,
8032 struct intel_crtc_config
*pipe_config
)
8034 #define PIPE_CONF_CHECK_X(name) \
8035 if (current_config->name != pipe_config->name) { \
8036 DRM_ERROR("mismatch in " #name " " \
8037 "(expected 0x%08x, found 0x%08x)\n", \
8038 current_config->name, \
8039 pipe_config->name); \
8043 #define PIPE_CONF_CHECK_I(name) \
8044 if (current_config->name != pipe_config->name) { \
8045 DRM_ERROR("mismatch in " #name " " \
8046 "(expected %i, found %i)\n", \
8047 current_config->name, \
8048 pipe_config->name); \
8052 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
8053 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8054 DRM_ERROR("mismatch in " #name " " \
8055 "(expected %i, found %i)\n", \
8056 current_config->name & (mask), \
8057 pipe_config->name & (mask)); \
8061 #define PIPE_CONF_QUIRK(quirk) \
8062 ((current_config->quirks | pipe_config->quirks) & (quirk))
8064 PIPE_CONF_CHECK_I(cpu_transcoder
);
8066 PIPE_CONF_CHECK_I(has_pch_encoder
);
8067 PIPE_CONF_CHECK_I(fdi_lanes
);
8068 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_m
);
8069 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_n
);
8070 PIPE_CONF_CHECK_I(fdi_m_n
.link_m
);
8071 PIPE_CONF_CHECK_I(fdi_m_n
.link_n
);
8072 PIPE_CONF_CHECK_I(fdi_m_n
.tu
);
8074 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hdisplay
);
8075 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_htotal
);
8076 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hblank_start
);
8077 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hblank_end
);
8078 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hsync_start
);
8079 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hsync_end
);
8081 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vdisplay
);
8082 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vtotal
);
8083 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vblank_start
);
8084 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vblank_end
);
8085 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vsync_start
);
8086 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vsync_end
);
8088 if (!HAS_PCH_SPLIT(dev
))
8089 PIPE_CONF_CHECK_I(pixel_multiplier
);
8091 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8092 DRM_MODE_FLAG_INTERLACE
);
8094 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
8095 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8096 DRM_MODE_FLAG_PHSYNC
);
8097 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8098 DRM_MODE_FLAG_NHSYNC
);
8099 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8100 DRM_MODE_FLAG_PVSYNC
);
8101 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8102 DRM_MODE_FLAG_NVSYNC
);
8105 PIPE_CONF_CHECK_I(requested_mode
.hdisplay
);
8106 PIPE_CONF_CHECK_I(requested_mode
.vdisplay
);
8108 PIPE_CONF_CHECK_I(gmch_pfit
.control
);
8109 /* pfit ratios are autocomputed by the hw on gen4+ */
8110 if (INTEL_INFO(dev
)->gen
< 4)
8111 PIPE_CONF_CHECK_I(gmch_pfit
.pgm_ratios
);
8112 PIPE_CONF_CHECK_I(gmch_pfit
.lvds_border_bits
);
8113 PIPE_CONF_CHECK_I(pch_pfit
.pos
);
8114 PIPE_CONF_CHECK_I(pch_pfit
.size
);
8116 PIPE_CONF_CHECK_I(ips_enabled
);
8118 PIPE_CONF_CHECK_I(shared_dpll
);
8119 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll
);
8120 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll_md
);
8121 PIPE_CONF_CHECK_X(dpll_hw_state
.fp0
);
8122 PIPE_CONF_CHECK_X(dpll_hw_state
.fp1
);
8124 #undef PIPE_CONF_CHECK_X
8125 #undef PIPE_CONF_CHECK_I
8126 #undef PIPE_CONF_CHECK_FLAGS
8127 #undef PIPE_CONF_QUIRK
8133 check_connector_state(struct drm_device
*dev
)
8135 struct intel_connector
*connector
;
8137 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8139 /* This also checks the encoder/connector hw state with the
8140 * ->get_hw_state callbacks. */
8141 intel_connector_check_state(connector
);
8143 WARN(&connector
->new_encoder
->base
!= connector
->base
.encoder
,
8144 "connector's staged encoder doesn't match current encoder\n");
8149 check_encoder_state(struct drm_device
*dev
)
8151 struct intel_encoder
*encoder
;
8152 struct intel_connector
*connector
;
8154 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8156 bool enabled
= false;
8157 bool active
= false;
8158 enum pipe pipe
, tracked_pipe
;
8160 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8161 encoder
->base
.base
.id
,
8162 drm_get_encoder_name(&encoder
->base
));
8164 WARN(&encoder
->new_crtc
->base
!= encoder
->base
.crtc
,
8165 "encoder's stage crtc doesn't match current crtc\n");
8166 WARN(encoder
->connectors_active
&& !encoder
->base
.crtc
,
8167 "encoder's active_connectors set, but no crtc\n");
8169 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8171 if (connector
->base
.encoder
!= &encoder
->base
)
8174 if (connector
->base
.dpms
!= DRM_MODE_DPMS_OFF
)
8177 WARN(!!encoder
->base
.crtc
!= enabled
,
8178 "encoder's enabled state mismatch "
8179 "(expected %i, found %i)\n",
8180 !!encoder
->base
.crtc
, enabled
);
8181 WARN(active
&& !encoder
->base
.crtc
,
8182 "active encoder with no crtc\n");
8184 WARN(encoder
->connectors_active
!= active
,
8185 "encoder's computed active state doesn't match tracked active state "
8186 "(expected %i, found %i)\n", active
, encoder
->connectors_active
);
8188 active
= encoder
->get_hw_state(encoder
, &pipe
);
8189 WARN(active
!= encoder
->connectors_active
,
8190 "encoder's hw state doesn't match sw tracking "
8191 "(expected %i, found %i)\n",
8192 encoder
->connectors_active
, active
);
8194 if (!encoder
->base
.crtc
)
8197 tracked_pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
8198 WARN(active
&& pipe
!= tracked_pipe
,
8199 "active encoder's pipe doesn't match"
8200 "(expected %i, found %i)\n",
8201 tracked_pipe
, pipe
);
8207 check_crtc_state(struct drm_device
*dev
)
8209 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8210 struct intel_crtc
*crtc
;
8211 struct intel_encoder
*encoder
;
8212 struct intel_crtc_config pipe_config
;
8214 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
8216 bool enabled
= false;
8217 bool active
= false;
8219 memset(&pipe_config
, 0, sizeof(pipe_config
));
8221 DRM_DEBUG_KMS("[CRTC:%d]\n",
8222 crtc
->base
.base
.id
);
8224 WARN(crtc
->active
&& !crtc
->base
.enabled
,
8225 "active crtc, but not enabled in sw tracking\n");
8227 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8229 if (encoder
->base
.crtc
!= &crtc
->base
)
8232 if (encoder
->connectors_active
)
8236 WARN(active
!= crtc
->active
,
8237 "crtc's computed active state doesn't match tracked active state "
8238 "(expected %i, found %i)\n", active
, crtc
->active
);
8239 WARN(enabled
!= crtc
->base
.enabled
,
8240 "crtc's computed enabled state doesn't match tracked enabled state "
8241 "(expected %i, found %i)\n", enabled
, crtc
->base
.enabled
);
8243 active
= dev_priv
->display
.get_pipe_config(crtc
,
8246 /* hw state is inconsistent with the pipe A quirk */
8247 if (crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
8248 active
= crtc
->active
;
8250 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8252 if (encoder
->base
.crtc
!= &crtc
->base
)
8254 if (encoder
->get_config
)
8255 encoder
->get_config(encoder
, &pipe_config
);
8258 WARN(crtc
->active
!= active
,
8259 "crtc active state doesn't match with hw state "
8260 "(expected %i, found %i)\n", crtc
->active
, active
);
8263 !intel_pipe_config_compare(dev
, &crtc
->config
, &pipe_config
)) {
8264 WARN(1, "pipe state doesn't match!\n");
8265 intel_dump_pipe_config(crtc
, &pipe_config
,
8267 intel_dump_pipe_config(crtc
, &crtc
->config
,
8274 check_shared_dpll_state(struct drm_device
*dev
)
8276 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8277 struct intel_crtc
*crtc
;
8278 struct intel_dpll_hw_state dpll_hw_state
;
8281 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
8282 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
8283 int enabled_crtcs
= 0, active_crtcs
= 0;
8286 memset(&dpll_hw_state
, 0, sizeof(dpll_hw_state
));
8288 DRM_DEBUG_KMS("%s\n", pll
->name
);
8290 active
= pll
->get_hw_state(dev_priv
, pll
, &dpll_hw_state
);
8292 WARN(pll
->active
> pll
->refcount
,
8293 "more active pll users than references: %i vs %i\n",
8294 pll
->active
, pll
->refcount
);
8295 WARN(pll
->active
&& !pll
->on
,
8296 "pll in active use but not on in sw tracking\n");
8297 WARN(pll
->on
!= active
,
8298 "pll on state mismatch (expected %i, found %i)\n",
8301 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
8303 if (crtc
->base
.enabled
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
8305 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
8308 WARN(pll
->active
!= active_crtcs
,
8309 "pll active crtcs mismatch (expected %i, found %i)\n",
8310 pll
->active
, active_crtcs
);
8311 WARN(pll
->refcount
!= enabled_crtcs
,
8312 "pll enabled crtcs mismatch (expected %i, found %i)\n",
8313 pll
->refcount
, enabled_crtcs
);
8315 WARN(pll
->on
&& memcmp(&pll
->hw_state
, &dpll_hw_state
,
8316 sizeof(dpll_hw_state
)),
8317 "pll hw state mismatch\n");
8322 intel_modeset_check_state(struct drm_device
*dev
)
8324 check_connector_state(dev
);
8325 check_encoder_state(dev
);
8326 check_crtc_state(dev
);
8327 check_shared_dpll_state(dev
);
8330 static int __intel_set_mode(struct drm_crtc
*crtc
,
8331 struct drm_display_mode
*mode
,
8332 int x
, int y
, struct drm_framebuffer
*fb
)
8334 struct drm_device
*dev
= crtc
->dev
;
8335 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8336 struct drm_display_mode
*saved_mode
, *saved_hwmode
;
8337 struct intel_crtc_config
*pipe_config
= NULL
;
8338 struct intel_crtc
*intel_crtc
;
8339 unsigned disable_pipes
, prepare_pipes
, modeset_pipes
;
8342 saved_mode
= kmalloc(2 * sizeof(*saved_mode
), GFP_KERNEL
);
8345 saved_hwmode
= saved_mode
+ 1;
8347 intel_modeset_affected_pipes(crtc
, &modeset_pipes
,
8348 &prepare_pipes
, &disable_pipes
);
8350 *saved_hwmode
= crtc
->hwmode
;
8351 *saved_mode
= crtc
->mode
;
8353 /* Hack: Because we don't (yet) support global modeset on multiple
8354 * crtcs, we don't keep track of the new mode for more than one crtc.
8355 * Hence simply check whether any bit is set in modeset_pipes in all the
8356 * pieces of code that are not yet converted to deal with mutliple crtcs
8357 * changing their mode at the same time. */
8358 if (modeset_pipes
) {
8359 pipe_config
= intel_modeset_pipe_config(crtc
, fb
, mode
);
8360 if (IS_ERR(pipe_config
)) {
8361 ret
= PTR_ERR(pipe_config
);
8366 intel_dump_pipe_config(to_intel_crtc(crtc
), pipe_config
,
8370 for_each_intel_crtc_masked(dev
, disable_pipes
, intel_crtc
)
8371 intel_crtc_disable(&intel_crtc
->base
);
8373 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
8374 if (intel_crtc
->base
.enabled
)
8375 dev_priv
->display
.crtc_disable(&intel_crtc
->base
);
8378 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8379 * to set it here already despite that we pass it down the callchain.
8381 if (modeset_pipes
) {
8383 /* mode_set/enable/disable functions rely on a correct pipe
8385 to_intel_crtc(crtc
)->config
= *pipe_config
;
8388 /* Only after disabling all output pipelines that will be changed can we
8389 * update the the output configuration. */
8390 intel_modeset_update_state(dev
, prepare_pipes
);
8392 if (dev_priv
->display
.modeset_global_resources
)
8393 dev_priv
->display
.modeset_global_resources(dev
);
8395 /* Set up the DPLL and any encoders state that needs to adjust or depend
8398 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
8399 ret
= intel_crtc_mode_set(&intel_crtc
->base
,
8405 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8406 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
)
8407 dev_priv
->display
.crtc_enable(&intel_crtc
->base
);
8409 if (modeset_pipes
) {
8410 /* Store real post-adjustment hardware mode. */
8411 crtc
->hwmode
= pipe_config
->adjusted_mode
;
8413 /* Calculate and store various constants which
8414 * are later needed by vblank and swap-completion
8415 * timestamping. They are derived from true hwmode.
8417 drm_calc_timestamping_constants(crtc
);
8420 /* FIXME: add subpixel order */
8422 if (ret
&& crtc
->enabled
) {
8423 crtc
->hwmode
= *saved_hwmode
;
8424 crtc
->mode
= *saved_mode
;
8433 int intel_set_mode(struct drm_crtc
*crtc
,
8434 struct drm_display_mode
*mode
,
8435 int x
, int y
, struct drm_framebuffer
*fb
)
8439 ret
= __intel_set_mode(crtc
, mode
, x
, y
, fb
);
8442 intel_modeset_check_state(crtc
->dev
);
8447 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
8449 intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
, crtc
->fb
);
8452 #undef for_each_intel_crtc_masked
8454 static void intel_set_config_free(struct intel_set_config
*config
)
8459 kfree(config
->save_connector_encoders
);
8460 kfree(config
->save_encoder_crtcs
);
8464 static int intel_set_config_save_state(struct drm_device
*dev
,
8465 struct intel_set_config
*config
)
8467 struct drm_encoder
*encoder
;
8468 struct drm_connector
*connector
;
8471 config
->save_encoder_crtcs
=
8472 kcalloc(dev
->mode_config
.num_encoder
,
8473 sizeof(struct drm_crtc
*), GFP_KERNEL
);
8474 if (!config
->save_encoder_crtcs
)
8477 config
->save_connector_encoders
=
8478 kcalloc(dev
->mode_config
.num_connector
,
8479 sizeof(struct drm_encoder
*), GFP_KERNEL
);
8480 if (!config
->save_connector_encoders
)
8483 /* Copy data. Note that driver private data is not affected.
8484 * Should anything bad happen only the expected state is
8485 * restored, not the drivers personal bookkeeping.
8488 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
8489 config
->save_encoder_crtcs
[count
++] = encoder
->crtc
;
8493 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
8494 config
->save_connector_encoders
[count
++] = connector
->encoder
;
8500 static void intel_set_config_restore_state(struct drm_device
*dev
,
8501 struct intel_set_config
*config
)
8503 struct intel_encoder
*encoder
;
8504 struct intel_connector
*connector
;
8508 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
8510 to_intel_crtc(config
->save_encoder_crtcs
[count
++]);
8514 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
8515 connector
->new_encoder
=
8516 to_intel_encoder(config
->save_connector_encoders
[count
++]);
8521 is_crtc_connector_off(struct drm_crtc
*crtc
, struct drm_connector
*connectors
,
8526 for (i
= 0; i
< num_connectors
; i
++)
8527 if (connectors
[i
].encoder
&&
8528 connectors
[i
].encoder
->crtc
== crtc
&&
8529 connectors
[i
].dpms
!= DRM_MODE_DPMS_ON
)
8536 intel_set_config_compute_mode_changes(struct drm_mode_set
*set
,
8537 struct intel_set_config
*config
)
8540 /* We should be able to check here if the fb has the same properties
8541 * and then just flip_or_move it */
8542 if (set
->connectors
!= NULL
&&
8543 is_crtc_connector_off(set
->crtc
, *set
->connectors
,
8544 set
->num_connectors
)) {
8545 config
->mode_changed
= true;
8546 } else if (set
->crtc
->fb
!= set
->fb
) {
8547 /* If we have no fb then treat it as a full mode set */
8548 if (set
->crtc
->fb
== NULL
) {
8549 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8550 config
->mode_changed
= true;
8551 } else if (set
->fb
== NULL
) {
8552 config
->mode_changed
= true;
8553 } else if (set
->fb
->pixel_format
!=
8554 set
->crtc
->fb
->pixel_format
) {
8555 config
->mode_changed
= true;
8557 config
->fb_changed
= true;
8561 if (set
->fb
&& (set
->x
!= set
->crtc
->x
|| set
->y
!= set
->crtc
->y
))
8562 config
->fb_changed
= true;
8564 if (set
->mode
&& !drm_mode_equal(set
->mode
, &set
->crtc
->mode
)) {
8565 DRM_DEBUG_KMS("modes are different, full mode set\n");
8566 drm_mode_debug_printmodeline(&set
->crtc
->mode
);
8567 drm_mode_debug_printmodeline(set
->mode
);
8568 config
->mode_changed
= true;
8573 intel_modeset_stage_output_state(struct drm_device
*dev
,
8574 struct drm_mode_set
*set
,
8575 struct intel_set_config
*config
)
8577 struct drm_crtc
*new_crtc
;
8578 struct intel_connector
*connector
;
8579 struct intel_encoder
*encoder
;
8582 /* The upper layers ensure that we either disable a crtc or have a list
8583 * of connectors. For paranoia, double-check this. */
8584 WARN_ON(!set
->fb
&& (set
->num_connectors
!= 0));
8585 WARN_ON(set
->fb
&& (set
->num_connectors
== 0));
8588 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8590 /* Otherwise traverse passed in connector list and get encoders
8592 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
8593 if (set
->connectors
[ro
] == &connector
->base
) {
8594 connector
->new_encoder
= connector
->encoder
;
8599 /* If we disable the crtc, disable all its connectors. Also, if
8600 * the connector is on the changing crtc but not on the new
8601 * connector list, disable it. */
8602 if ((!set
->fb
|| ro
== set
->num_connectors
) &&
8603 connector
->base
.encoder
&&
8604 connector
->base
.encoder
->crtc
== set
->crtc
) {
8605 connector
->new_encoder
= NULL
;
8607 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8608 connector
->base
.base
.id
,
8609 drm_get_connector_name(&connector
->base
));
8613 if (&connector
->new_encoder
->base
!= connector
->base
.encoder
) {
8614 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8615 config
->mode_changed
= true;
8618 /* connector->new_encoder is now updated for all connectors. */
8620 /* Update crtc of enabled connectors. */
8622 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8624 if (!connector
->new_encoder
)
8627 new_crtc
= connector
->new_encoder
->base
.crtc
;
8629 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
8630 if (set
->connectors
[ro
] == &connector
->base
)
8631 new_crtc
= set
->crtc
;
8634 /* Make sure the new CRTC will work with the encoder */
8635 if (!intel_encoder_crtc_ok(&connector
->new_encoder
->base
,
8639 connector
->encoder
->new_crtc
= to_intel_crtc(new_crtc
);
8641 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8642 connector
->base
.base
.id
,
8643 drm_get_connector_name(&connector
->base
),
8647 /* Check for any encoders that needs to be disabled. */
8648 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8650 list_for_each_entry(connector
,
8651 &dev
->mode_config
.connector_list
,
8653 if (connector
->new_encoder
== encoder
) {
8654 WARN_ON(!connector
->new_encoder
->new_crtc
);
8659 encoder
->new_crtc
= NULL
;
8661 /* Only now check for crtc changes so we don't miss encoders
8662 * that will be disabled. */
8663 if (&encoder
->new_crtc
->base
!= encoder
->base
.crtc
) {
8664 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8665 config
->mode_changed
= true;
8668 /* Now we've also updated encoder->new_crtc for all encoders. */
8673 static int intel_crtc_set_config(struct drm_mode_set
*set
)
8675 struct drm_device
*dev
;
8676 struct drm_mode_set save_set
;
8677 struct intel_set_config
*config
;
8682 BUG_ON(!set
->crtc
->helper_private
);
8684 /* Enforce sane interface api - has been abused by the fb helper. */
8685 BUG_ON(!set
->mode
&& set
->fb
);
8686 BUG_ON(set
->fb
&& set
->num_connectors
== 0);
8689 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8690 set
->crtc
->base
.id
, set
->fb
->base
.id
,
8691 (int)set
->num_connectors
, set
->x
, set
->y
);
8693 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set
->crtc
->base
.id
);
8696 dev
= set
->crtc
->dev
;
8699 config
= kzalloc(sizeof(*config
), GFP_KERNEL
);
8703 ret
= intel_set_config_save_state(dev
, config
);
8707 save_set
.crtc
= set
->crtc
;
8708 save_set
.mode
= &set
->crtc
->mode
;
8709 save_set
.x
= set
->crtc
->x
;
8710 save_set
.y
= set
->crtc
->y
;
8711 save_set
.fb
= set
->crtc
->fb
;
8713 /* Compute whether we need a full modeset, only an fb base update or no
8714 * change at all. In the future we might also check whether only the
8715 * mode changed, e.g. for LVDS where we only change the panel fitter in
8717 intel_set_config_compute_mode_changes(set
, config
);
8719 ret
= intel_modeset_stage_output_state(dev
, set
, config
);
8723 if (config
->mode_changed
) {
8724 ret
= intel_set_mode(set
->crtc
, set
->mode
,
8725 set
->x
, set
->y
, set
->fb
);
8726 } else if (config
->fb_changed
) {
8727 intel_crtc_wait_for_pending_flips(set
->crtc
);
8729 ret
= intel_pipe_set_base(set
->crtc
,
8730 set
->x
, set
->y
, set
->fb
);
8734 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
8735 set
->crtc
->base
.id
, ret
);
8737 intel_set_config_restore_state(dev
, config
);
8739 /* Try to restore the config */
8740 if (config
->mode_changed
&&
8741 intel_set_mode(save_set
.crtc
, save_set
.mode
,
8742 save_set
.x
, save_set
.y
, save_set
.fb
))
8743 DRM_ERROR("failed to restore config after modeset failure\n");
8747 intel_set_config_free(config
);
8751 static const struct drm_crtc_funcs intel_crtc_funcs
= {
8752 .cursor_set
= intel_crtc_cursor_set
,
8753 .cursor_move
= intel_crtc_cursor_move
,
8754 .gamma_set
= intel_crtc_gamma_set
,
8755 .set_config
= intel_crtc_set_config
,
8756 .destroy
= intel_crtc_destroy
,
8757 .page_flip
= intel_crtc_page_flip
,
8760 static void intel_cpu_pll_init(struct drm_device
*dev
)
8763 intel_ddi_pll_init(dev
);
8766 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private
*dev_priv
,
8767 struct intel_shared_dpll
*pll
,
8768 struct intel_dpll_hw_state
*hw_state
)
8772 val
= I915_READ(PCH_DPLL(pll
->id
));
8773 hw_state
->dpll
= val
;
8774 hw_state
->fp0
= I915_READ(PCH_FP0(pll
->id
));
8775 hw_state
->fp1
= I915_READ(PCH_FP1(pll
->id
));
8777 return val
& DPLL_VCO_ENABLE
;
8780 static void ibx_pch_dpll_mode_set(struct drm_i915_private
*dev_priv
,
8781 struct intel_shared_dpll
*pll
)
8783 I915_WRITE(PCH_FP0(pll
->id
), pll
->hw_state
.fp0
);
8784 I915_WRITE(PCH_FP1(pll
->id
), pll
->hw_state
.fp1
);
8787 static void ibx_pch_dpll_enable(struct drm_i915_private
*dev_priv
,
8788 struct intel_shared_dpll
*pll
)
8790 /* PCH refclock must be enabled first */
8791 assert_pch_refclk_enabled(dev_priv
);
8793 I915_WRITE(PCH_DPLL(pll
->id
), pll
->hw_state
.dpll
);
8795 /* Wait for the clocks to stabilize. */
8796 POSTING_READ(PCH_DPLL(pll
->id
));
8799 /* The pixel multiplier can only be updated once the
8800 * DPLL is enabled and the clocks are stable.
8802 * So write it again.
8804 I915_WRITE(PCH_DPLL(pll
->id
), pll
->hw_state
.dpll
);
8805 POSTING_READ(PCH_DPLL(pll
->id
));
8809 static void ibx_pch_dpll_disable(struct drm_i915_private
*dev_priv
,
8810 struct intel_shared_dpll
*pll
)
8812 struct drm_device
*dev
= dev_priv
->dev
;
8813 struct intel_crtc
*crtc
;
8815 /* Make sure no transcoder isn't still depending on us. */
8816 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
8817 if (intel_crtc_to_shared_dpll(crtc
) == pll
)
8818 assert_pch_transcoder_disabled(dev_priv
, crtc
->pipe
);
8821 I915_WRITE(PCH_DPLL(pll
->id
), 0);
8822 POSTING_READ(PCH_DPLL(pll
->id
));
8826 static char *ibx_pch_dpll_names
[] = {
8831 static void ibx_pch_dpll_init(struct drm_device
*dev
)
8833 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8836 dev_priv
->num_shared_dpll
= 2;
8838 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
8839 dev_priv
->shared_dplls
[i
].id
= i
;
8840 dev_priv
->shared_dplls
[i
].name
= ibx_pch_dpll_names
[i
];
8841 dev_priv
->shared_dplls
[i
].mode_set
= ibx_pch_dpll_mode_set
;
8842 dev_priv
->shared_dplls
[i
].enable
= ibx_pch_dpll_enable
;
8843 dev_priv
->shared_dplls
[i
].disable
= ibx_pch_dpll_disable
;
8844 dev_priv
->shared_dplls
[i
].get_hw_state
=
8845 ibx_pch_dpll_get_hw_state
;
8849 static void intel_shared_dpll_init(struct drm_device
*dev
)
8851 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8853 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
8854 ibx_pch_dpll_init(dev
);
8856 dev_priv
->num_shared_dpll
= 0;
8858 BUG_ON(dev_priv
->num_shared_dpll
> I915_NUM_PLLS
);
8859 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
8860 dev_priv
->num_shared_dpll
);
8863 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
8865 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8866 struct intel_crtc
*intel_crtc
;
8869 intel_crtc
= kzalloc(sizeof(struct intel_crtc
) + (INTELFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
8870 if (intel_crtc
== NULL
)
8873 drm_crtc_init(dev
, &intel_crtc
->base
, &intel_crtc_funcs
);
8875 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
8876 for (i
= 0; i
< 256; i
++) {
8877 intel_crtc
->lut_r
[i
] = i
;
8878 intel_crtc
->lut_g
[i
] = i
;
8879 intel_crtc
->lut_b
[i
] = i
;
8882 /* Swap pipes & planes for FBC on pre-965 */
8883 intel_crtc
->pipe
= pipe
;
8884 intel_crtc
->plane
= pipe
;
8885 if (IS_MOBILE(dev
) && IS_GEN3(dev
)) {
8886 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8887 intel_crtc
->plane
= !pipe
;
8890 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
8891 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
8892 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
8893 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
8895 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
8898 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
8899 struct drm_file
*file
)
8901 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
8902 struct drm_mode_object
*drmmode_obj
;
8903 struct intel_crtc
*crtc
;
8905 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
8908 drmmode_obj
= drm_mode_object_find(dev
, pipe_from_crtc_id
->crtc_id
,
8909 DRM_MODE_OBJECT_CRTC
);
8912 DRM_ERROR("no such CRTC id\n");
8916 crtc
= to_intel_crtc(obj_to_crtc(drmmode_obj
));
8917 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
8922 static int intel_encoder_clones(struct intel_encoder
*encoder
)
8924 struct drm_device
*dev
= encoder
->base
.dev
;
8925 struct intel_encoder
*source_encoder
;
8929 list_for_each_entry(source_encoder
,
8930 &dev
->mode_config
.encoder_list
, base
.head
) {
8932 if (encoder
== source_encoder
)
8933 index_mask
|= (1 << entry
);
8935 /* Intel hw has only one MUX where enocoders could be cloned. */
8936 if (encoder
->cloneable
&& source_encoder
->cloneable
)
8937 index_mask
|= (1 << entry
);
8945 static bool has_edp_a(struct drm_device
*dev
)
8947 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8949 if (!IS_MOBILE(dev
))
8952 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
8956 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES
) & ILK_eDP_A_DISABLE
))
8962 static void intel_setup_outputs(struct drm_device
*dev
)
8964 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8965 struct intel_encoder
*encoder
;
8966 bool dpd_is_edp
= false;
8968 intel_lvds_init(dev
);
8971 intel_crt_init(dev
);
8976 /* Haswell uses DDI functions to detect digital outputs */
8977 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
8978 /* DDI A only supports eDP */
8980 intel_ddi_init(dev
, PORT_A
);
8982 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8984 found
= I915_READ(SFUSE_STRAP
);
8986 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
8987 intel_ddi_init(dev
, PORT_B
);
8988 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
8989 intel_ddi_init(dev
, PORT_C
);
8990 if (found
& SFUSE_STRAP_DDID_DETECTED
)
8991 intel_ddi_init(dev
, PORT_D
);
8992 } else if (HAS_PCH_SPLIT(dev
)) {
8994 dpd_is_edp
= intel_dpd_is_edp(dev
);
8997 intel_dp_init(dev
, DP_A
, PORT_A
);
8999 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
9000 /* PCH SDVOB multiplex with HDMIB */
9001 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
9003 intel_hdmi_init(dev
, PCH_HDMIB
, PORT_B
);
9004 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
9005 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
9008 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
9009 intel_hdmi_init(dev
, PCH_HDMIC
, PORT_C
);
9011 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
9012 intel_hdmi_init(dev
, PCH_HDMID
, PORT_D
);
9014 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
9015 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
9017 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
9018 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
9019 } else if (IS_VALLEYVIEW(dev
)) {
9020 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
9021 if (I915_READ(VLV_DISPLAY_BASE
+ DP_C
) & DP_DETECTED
)
9022 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_C
, PORT_C
);
9024 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIB
) & SDVO_DETECTED
) {
9025 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIB
,
9027 if (I915_READ(VLV_DISPLAY_BASE
+ DP_B
) & DP_DETECTED
)
9028 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_B
, PORT_B
);
9030 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
9033 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
9034 DRM_DEBUG_KMS("probing SDVOB\n");
9035 found
= intel_sdvo_init(dev
, GEN3_SDVOB
, true);
9036 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
9037 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
9038 intel_hdmi_init(dev
, GEN4_HDMIB
, PORT_B
);
9041 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
))
9042 intel_dp_init(dev
, DP_B
, PORT_B
);
9045 /* Before G4X SDVOC doesn't have its own detect register */
9047 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
9048 DRM_DEBUG_KMS("probing SDVOC\n");
9049 found
= intel_sdvo_init(dev
, GEN3_SDVOC
, false);
9052 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
9054 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
9055 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
9056 intel_hdmi_init(dev
, GEN4_HDMIC
, PORT_C
);
9058 if (SUPPORTS_INTEGRATED_DP(dev
))
9059 intel_dp_init(dev
, DP_C
, PORT_C
);
9062 if (SUPPORTS_INTEGRATED_DP(dev
) &&
9063 (I915_READ(DP_D
) & DP_DETECTED
))
9064 intel_dp_init(dev
, DP_D
, PORT_D
);
9065 } else if (IS_GEN2(dev
))
9066 intel_dvo_init(dev
);
9068 if (SUPPORTS_TV(dev
))
9071 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
9072 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
9073 encoder
->base
.possible_clones
=
9074 intel_encoder_clones(encoder
);
9077 intel_init_pch_refclk(dev
);
9079 drm_helper_move_panel_connectors_to_head(dev
);
9082 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
9084 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
9086 drm_framebuffer_cleanup(fb
);
9087 drm_gem_object_unreference_unlocked(&intel_fb
->obj
->base
);
9092 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
9093 struct drm_file
*file
,
9094 unsigned int *handle
)
9096 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
9097 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
9099 return drm_gem_handle_create(file
, &obj
->base
, handle
);
9102 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
9103 .destroy
= intel_user_framebuffer_destroy
,
9104 .create_handle
= intel_user_framebuffer_create_handle
,
9107 int intel_framebuffer_init(struct drm_device
*dev
,
9108 struct intel_framebuffer
*intel_fb
,
9109 struct drm_mode_fb_cmd2
*mode_cmd
,
9110 struct drm_i915_gem_object
*obj
)
9115 if (obj
->tiling_mode
== I915_TILING_Y
) {
9116 DRM_DEBUG("hardware does not support tiling Y\n");
9120 if (mode_cmd
->pitches
[0] & 63) {
9121 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9122 mode_cmd
->pitches
[0]);
9126 if (INTEL_INFO(dev
)->gen
>= 5 && !IS_VALLEYVIEW(dev
)) {
9127 pitch_limit
= 32*1024;
9128 } else if (INTEL_INFO(dev
)->gen
>= 4) {
9129 if (obj
->tiling_mode
)
9130 pitch_limit
= 16*1024;
9132 pitch_limit
= 32*1024;
9133 } else if (INTEL_INFO(dev
)->gen
>= 3) {
9134 if (obj
->tiling_mode
)
9135 pitch_limit
= 8*1024;
9137 pitch_limit
= 16*1024;
9139 /* XXX DSPC is limited to 4k tiled */
9140 pitch_limit
= 8*1024;
9142 if (mode_cmd
->pitches
[0] > pitch_limit
) {
9143 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9144 obj
->tiling_mode
? "tiled" : "linear",
9145 mode_cmd
->pitches
[0], pitch_limit
);
9149 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
9150 mode_cmd
->pitches
[0] != obj
->stride
) {
9151 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9152 mode_cmd
->pitches
[0], obj
->stride
);
9156 /* Reject formats not supported by any plane early. */
9157 switch (mode_cmd
->pixel_format
) {
9159 case DRM_FORMAT_RGB565
:
9160 case DRM_FORMAT_XRGB8888
:
9161 case DRM_FORMAT_ARGB8888
:
9163 case DRM_FORMAT_XRGB1555
:
9164 case DRM_FORMAT_ARGB1555
:
9165 if (INTEL_INFO(dev
)->gen
> 3) {
9166 DRM_DEBUG("unsupported pixel format: %s\n",
9167 drm_get_format_name(mode_cmd
->pixel_format
));
9171 case DRM_FORMAT_XBGR8888
:
9172 case DRM_FORMAT_ABGR8888
:
9173 case DRM_FORMAT_XRGB2101010
:
9174 case DRM_FORMAT_ARGB2101010
:
9175 case DRM_FORMAT_XBGR2101010
:
9176 case DRM_FORMAT_ABGR2101010
:
9177 if (INTEL_INFO(dev
)->gen
< 4) {
9178 DRM_DEBUG("unsupported pixel format: %s\n",
9179 drm_get_format_name(mode_cmd
->pixel_format
));
9183 case DRM_FORMAT_YUYV
:
9184 case DRM_FORMAT_UYVY
:
9185 case DRM_FORMAT_YVYU
:
9186 case DRM_FORMAT_VYUY
:
9187 if (INTEL_INFO(dev
)->gen
< 5) {
9188 DRM_DEBUG("unsupported pixel format: %s\n",
9189 drm_get_format_name(mode_cmd
->pixel_format
));
9194 DRM_DEBUG("unsupported pixel format: %s\n",
9195 drm_get_format_name(mode_cmd
->pixel_format
));
9199 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9200 if (mode_cmd
->offsets
[0] != 0)
9203 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
9204 intel_fb
->obj
= obj
;
9206 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
9208 DRM_ERROR("framebuffer init failed %d\n", ret
);
9215 static struct drm_framebuffer
*
9216 intel_user_framebuffer_create(struct drm_device
*dev
,
9217 struct drm_file
*filp
,
9218 struct drm_mode_fb_cmd2
*mode_cmd
)
9220 struct drm_i915_gem_object
*obj
;
9222 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
9223 mode_cmd
->handles
[0]));
9224 if (&obj
->base
== NULL
)
9225 return ERR_PTR(-ENOENT
);
9227 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
9230 static const struct drm_mode_config_funcs intel_mode_funcs
= {
9231 .fb_create
= intel_user_framebuffer_create
,
9232 .output_poll_changed
= intel_fb_output_poll_changed
,
9235 /* Set up chip specific display functions */
9236 static void intel_init_display(struct drm_device
*dev
)
9238 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9240 if (HAS_PCH_SPLIT(dev
) || IS_G4X(dev
))
9241 dev_priv
->display
.find_dpll
= g4x_find_best_dpll
;
9242 else if (IS_VALLEYVIEW(dev
))
9243 dev_priv
->display
.find_dpll
= vlv_find_best_dpll
;
9244 else if (IS_PINEVIEW(dev
))
9245 dev_priv
->display
.find_dpll
= pnv_find_best_dpll
;
9247 dev_priv
->display
.find_dpll
= i9xx_find_best_dpll
;
9250 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
9251 dev_priv
->display
.crtc_mode_set
= haswell_crtc_mode_set
;
9252 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
9253 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
9254 dev_priv
->display
.off
= haswell_crtc_off
;
9255 dev_priv
->display
.update_plane
= ironlake_update_plane
;
9256 } else if (HAS_PCH_SPLIT(dev
)) {
9257 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
9258 dev_priv
->display
.crtc_mode_set
= ironlake_crtc_mode_set
;
9259 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
9260 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
9261 dev_priv
->display
.off
= ironlake_crtc_off
;
9262 dev_priv
->display
.update_plane
= ironlake_update_plane
;
9263 } else if (IS_VALLEYVIEW(dev
)) {
9264 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
9265 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
9266 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
9267 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
9268 dev_priv
->display
.off
= i9xx_crtc_off
;
9269 dev_priv
->display
.update_plane
= i9xx_update_plane
;
9271 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
9272 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
9273 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
9274 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
9275 dev_priv
->display
.off
= i9xx_crtc_off
;
9276 dev_priv
->display
.update_plane
= i9xx_update_plane
;
9279 /* Returns the core display clock speed */
9280 if (IS_VALLEYVIEW(dev
))
9281 dev_priv
->display
.get_display_clock_speed
=
9282 valleyview_get_display_clock_speed
;
9283 else if (IS_I945G(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
9284 dev_priv
->display
.get_display_clock_speed
=
9285 i945_get_display_clock_speed
;
9286 else if (IS_I915G(dev
))
9287 dev_priv
->display
.get_display_clock_speed
=
9288 i915_get_display_clock_speed
;
9289 else if (IS_I945GM(dev
) || IS_845G(dev
) || IS_PINEVIEW_M(dev
))
9290 dev_priv
->display
.get_display_clock_speed
=
9291 i9xx_misc_get_display_clock_speed
;
9292 else if (IS_I915GM(dev
))
9293 dev_priv
->display
.get_display_clock_speed
=
9294 i915gm_get_display_clock_speed
;
9295 else if (IS_I865G(dev
))
9296 dev_priv
->display
.get_display_clock_speed
=
9297 i865_get_display_clock_speed
;
9298 else if (IS_I85X(dev
))
9299 dev_priv
->display
.get_display_clock_speed
=
9300 i855_get_display_clock_speed
;
9302 dev_priv
->display
.get_display_clock_speed
=
9303 i830_get_display_clock_speed
;
9305 if (HAS_PCH_SPLIT(dev
)) {
9307 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
9308 dev_priv
->display
.write_eld
= ironlake_write_eld
;
9309 } else if (IS_GEN6(dev
)) {
9310 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
9311 dev_priv
->display
.write_eld
= ironlake_write_eld
;
9312 } else if (IS_IVYBRIDGE(dev
)) {
9313 /* FIXME: detect B0+ stepping and use auto training */
9314 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
9315 dev_priv
->display
.write_eld
= ironlake_write_eld
;
9316 dev_priv
->display
.modeset_global_resources
=
9317 ivb_modeset_global_resources
;
9318 } else if (IS_HASWELL(dev
)) {
9319 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
9320 dev_priv
->display
.write_eld
= haswell_write_eld
;
9321 dev_priv
->display
.modeset_global_resources
=
9322 haswell_modeset_global_resources
;
9324 } else if (IS_G4X(dev
)) {
9325 dev_priv
->display
.write_eld
= g4x_write_eld
;
9328 /* Default just returns -ENODEV to indicate unsupported */
9329 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
9331 switch (INTEL_INFO(dev
)->gen
) {
9333 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
9337 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
9342 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
9346 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
9349 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
9355 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9356 * resume, or other times. This quirk makes sure that's the case for
9359 static void quirk_pipea_force(struct drm_device
*dev
)
9361 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9363 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
9364 DRM_INFO("applying pipe a force quirk\n");
9368 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9370 static void quirk_ssc_force_disable(struct drm_device
*dev
)
9372 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9373 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
9374 DRM_INFO("applying lvds SSC disable quirk\n");
9378 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9381 static void quirk_invert_brightness(struct drm_device
*dev
)
9383 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9384 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
9385 DRM_INFO("applying inverted panel brightness quirk\n");
9388 struct intel_quirk
{
9390 int subsystem_vendor
;
9391 int subsystem_device
;
9392 void (*hook
)(struct drm_device
*dev
);
9395 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9396 struct intel_dmi_quirk
{
9397 void (*hook
)(struct drm_device
*dev
);
9398 const struct dmi_system_id (*dmi_id_list
)[];
9401 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
9403 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
9407 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
9409 .dmi_id_list
= &(const struct dmi_system_id
[]) {
9411 .callback
= intel_dmi_reverse_brightness
,
9412 .ident
= "NCR Corporation",
9413 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
9414 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
9417 { } /* terminating entry */
9419 .hook
= quirk_invert_brightness
,
9423 static struct intel_quirk intel_quirks
[] = {
9424 /* HP Mini needs pipe A force quirk (LP: #322104) */
9425 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force
},
9427 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9428 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
9430 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9431 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
9433 /* 830/845 need to leave pipe A & dpll A up */
9434 { 0x2562, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
9435 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
9437 /* Lenovo U160 cannot use SSC on LVDS */
9438 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
9440 /* Sony Vaio Y cannot use SSC on LVDS */
9441 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
9443 /* Acer Aspire 5734Z must invert backlight brightness */
9444 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
9446 /* Acer/eMachines G725 */
9447 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness
},
9449 /* Acer/eMachines e725 */
9450 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness
},
9452 /* Acer/Packard Bell NCL20 */
9453 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness
},
9455 /* Acer Aspire 4736Z */
9456 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness
},
9459 static void intel_init_quirks(struct drm_device
*dev
)
9461 struct pci_dev
*d
= dev
->pdev
;
9464 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
9465 struct intel_quirk
*q
= &intel_quirks
[i
];
9467 if (d
->device
== q
->device
&&
9468 (d
->subsystem_vendor
== q
->subsystem_vendor
||
9469 q
->subsystem_vendor
== PCI_ANY_ID
) &&
9470 (d
->subsystem_device
== q
->subsystem_device
||
9471 q
->subsystem_device
== PCI_ANY_ID
))
9474 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
9475 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
9476 intel_dmi_quirks
[i
].hook(dev
);
9480 /* Disable the VGA plane that we never use */
9481 static void i915_disable_vga(struct drm_device
*dev
)
9483 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9485 u32 vga_reg
= i915_vgacntrl_reg(dev
);
9487 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
9488 outb(SR01
, VGA_SR_INDEX
);
9489 sr1
= inb(VGA_SR_DATA
);
9490 outb(sr1
| 1<<5, VGA_SR_DATA
);
9491 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
9494 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
9495 POSTING_READ(vga_reg
);
9498 void intel_modeset_init_hw(struct drm_device
*dev
)
9500 intel_init_power_well(dev
);
9502 intel_prepare_ddi(dev
);
9504 intel_init_clock_gating(dev
);
9506 mutex_lock(&dev
->struct_mutex
);
9507 intel_enable_gt_powersave(dev
);
9508 mutex_unlock(&dev
->struct_mutex
);
9511 void intel_modeset_suspend_hw(struct drm_device
*dev
)
9513 intel_suspend_hw(dev
);
9516 void intel_modeset_init(struct drm_device
*dev
)
9518 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9521 drm_mode_config_init(dev
);
9523 dev
->mode_config
.min_width
= 0;
9524 dev
->mode_config
.min_height
= 0;
9526 dev
->mode_config
.preferred_depth
= 24;
9527 dev
->mode_config
.prefer_shadow
= 1;
9529 dev
->mode_config
.funcs
= &intel_mode_funcs
;
9531 intel_init_quirks(dev
);
9535 if (INTEL_INFO(dev
)->num_pipes
== 0)
9538 intel_init_display(dev
);
9541 dev
->mode_config
.max_width
= 2048;
9542 dev
->mode_config
.max_height
= 2048;
9543 } else if (IS_GEN3(dev
)) {
9544 dev
->mode_config
.max_width
= 4096;
9545 dev
->mode_config
.max_height
= 4096;
9547 dev
->mode_config
.max_width
= 8192;
9548 dev
->mode_config
.max_height
= 8192;
9550 dev
->mode_config
.fb_base
= dev_priv
->gtt
.mappable_base
;
9552 DRM_DEBUG_KMS("%d display pipe%s available.\n",
9553 INTEL_INFO(dev
)->num_pipes
,
9554 INTEL_INFO(dev
)->num_pipes
> 1 ? "s" : "");
9556 for (i
= 0; i
< INTEL_INFO(dev
)->num_pipes
; i
++) {
9557 intel_crtc_init(dev
, i
);
9558 for (j
= 0; j
< dev_priv
->num_plane
; j
++) {
9559 ret
= intel_plane_init(dev
, i
, j
);
9561 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9562 pipe_name(i
), sprite_name(i
, j
), ret
);
9566 intel_cpu_pll_init(dev
);
9567 intel_shared_dpll_init(dev
);
9569 /* Just disable it once at startup */
9570 i915_disable_vga(dev
);
9571 intel_setup_outputs(dev
);
9573 /* Just in case the BIOS is doing something questionable. */
9574 intel_disable_fbc(dev
);
9578 intel_connector_break_all_links(struct intel_connector
*connector
)
9580 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
9581 connector
->base
.encoder
= NULL
;
9582 connector
->encoder
->connectors_active
= false;
9583 connector
->encoder
->base
.crtc
= NULL
;
9586 static void intel_enable_pipe_a(struct drm_device
*dev
)
9588 struct intel_connector
*connector
;
9589 struct drm_connector
*crt
= NULL
;
9590 struct intel_load_detect_pipe load_detect_temp
;
9592 /* We can't just switch on the pipe A, we need to set things up with a
9593 * proper mode and output configuration. As a gross hack, enable pipe A
9594 * by enabling the load detect pipe once. */
9595 list_for_each_entry(connector
,
9596 &dev
->mode_config
.connector_list
,
9598 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
9599 crt
= &connector
->base
;
9607 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
))
9608 intel_release_load_detect_pipe(crt
, &load_detect_temp
);
9614 intel_check_plane_mapping(struct intel_crtc
*crtc
)
9616 struct drm_device
*dev
= crtc
->base
.dev
;
9617 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9620 if (INTEL_INFO(dev
)->num_pipes
== 1)
9623 reg
= DSPCNTR(!crtc
->plane
);
9624 val
= I915_READ(reg
);
9626 if ((val
& DISPLAY_PLANE_ENABLE
) &&
9627 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
9633 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
9635 struct drm_device
*dev
= crtc
->base
.dev
;
9636 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9639 /* Clear any frame start delays used for debugging left by the BIOS */
9640 reg
= PIPECONF(crtc
->config
.cpu_transcoder
);
9641 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
9643 /* We need to sanitize the plane -> pipe mapping first because this will
9644 * disable the crtc (and hence change the state) if it is wrong. Note
9645 * that gen4+ has a fixed plane -> pipe mapping. */
9646 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
9647 struct intel_connector
*connector
;
9650 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9651 crtc
->base
.base
.id
);
9653 /* Pipe has the wrong plane attached and the plane is active.
9654 * Temporarily change the plane mapping and disable everything
9656 plane
= crtc
->plane
;
9657 crtc
->plane
= !plane
;
9658 dev_priv
->display
.crtc_disable(&crtc
->base
);
9659 crtc
->plane
= plane
;
9661 /* ... and break all links. */
9662 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9664 if (connector
->encoder
->base
.crtc
!= &crtc
->base
)
9667 intel_connector_break_all_links(connector
);
9670 WARN_ON(crtc
->active
);
9671 crtc
->base
.enabled
= false;
9674 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
9675 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
9676 /* BIOS forgot to enable pipe A, this mostly happens after
9677 * resume. Force-enable the pipe to fix this, the update_dpms
9678 * call below we restore the pipe to the right state, but leave
9679 * the required bits on. */
9680 intel_enable_pipe_a(dev
);
9683 /* Adjust the state of the output pipe according to whether we
9684 * have active connectors/encoders. */
9685 intel_crtc_update_dpms(&crtc
->base
);
9687 if (crtc
->active
!= crtc
->base
.enabled
) {
9688 struct intel_encoder
*encoder
;
9690 /* This can happen either due to bugs in the get_hw_state
9691 * functions or because the pipe is force-enabled due to the
9693 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9695 crtc
->base
.enabled
? "enabled" : "disabled",
9696 crtc
->active
? "enabled" : "disabled");
9698 crtc
->base
.enabled
= crtc
->active
;
9700 /* Because we only establish the connector -> encoder ->
9701 * crtc links if something is active, this means the
9702 * crtc is now deactivated. Break the links. connector
9703 * -> encoder links are only establish when things are
9704 * actually up, hence no need to break them. */
9705 WARN_ON(crtc
->active
);
9707 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
9708 WARN_ON(encoder
->connectors_active
);
9709 encoder
->base
.crtc
= NULL
;
9714 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
9716 struct intel_connector
*connector
;
9717 struct drm_device
*dev
= encoder
->base
.dev
;
9719 /* We need to check both for a crtc link (meaning that the
9720 * encoder is active and trying to read from a pipe) and the
9721 * pipe itself being active. */
9722 bool has_active_crtc
= encoder
->base
.crtc
&&
9723 to_intel_crtc(encoder
->base
.crtc
)->active
;
9725 if (encoder
->connectors_active
&& !has_active_crtc
) {
9726 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9727 encoder
->base
.base
.id
,
9728 drm_get_encoder_name(&encoder
->base
));
9730 /* Connector is active, but has no active pipe. This is
9731 * fallout from our resume register restoring. Disable
9732 * the encoder manually again. */
9733 if (encoder
->base
.crtc
) {
9734 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9735 encoder
->base
.base
.id
,
9736 drm_get_encoder_name(&encoder
->base
));
9737 encoder
->disable(encoder
);
9740 /* Inconsistent output/port/pipe state happens presumably due to
9741 * a bug in one of the get_hw_state functions. Or someplace else
9742 * in our code, like the register restore mess on resume. Clamp
9743 * things to off as a safer default. */
9744 list_for_each_entry(connector
,
9745 &dev
->mode_config
.connector_list
,
9747 if (connector
->encoder
!= encoder
)
9750 intel_connector_break_all_links(connector
);
9753 /* Enabled encoders without active connectors will be fixed in
9754 * the crtc fixup. */
9757 void i915_redisable_vga(struct drm_device
*dev
)
9759 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9760 u32 vga_reg
= i915_vgacntrl_reg(dev
);
9762 if (I915_READ(vga_reg
) != VGA_DISP_DISABLE
) {
9763 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9764 i915_disable_vga(dev
);
9768 static void intel_modeset_readout_hw_state(struct drm_device
*dev
)
9770 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9772 struct intel_crtc
*crtc
;
9773 struct intel_encoder
*encoder
;
9774 struct intel_connector
*connector
;
9777 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
9779 memset(&crtc
->config
, 0, sizeof(crtc
->config
));
9781 crtc
->active
= dev_priv
->display
.get_pipe_config(crtc
,
9784 crtc
->base
.enabled
= crtc
->active
;
9786 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9788 crtc
->active
? "enabled" : "disabled");
9791 /* FIXME: Smash this into the new shared dpll infrastructure. */
9793 intel_ddi_setup_hw_pll_state(dev
);
9795 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
9796 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
9798 pll
->on
= pll
->get_hw_state(dev_priv
, pll
, &pll
->hw_state
);
9800 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
9802 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
9805 pll
->refcount
= pll
->active
;
9807 DRM_DEBUG_KMS("%s hw state readout: refcount %i\n",
9808 pll
->name
, pll
->refcount
);
9811 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9815 if (encoder
->get_hw_state(encoder
, &pipe
)) {
9816 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
9817 encoder
->base
.crtc
= &crtc
->base
;
9818 if (encoder
->get_config
)
9819 encoder
->get_config(encoder
, &crtc
->config
);
9821 encoder
->base
.crtc
= NULL
;
9824 encoder
->connectors_active
= false;
9825 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9826 encoder
->base
.base
.id
,
9827 drm_get_encoder_name(&encoder
->base
),
9828 encoder
->base
.crtc
? "enabled" : "disabled",
9832 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9834 if (connector
->get_hw_state(connector
)) {
9835 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
9836 connector
->encoder
->connectors_active
= true;
9837 connector
->base
.encoder
= &connector
->encoder
->base
;
9839 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
9840 connector
->base
.encoder
= NULL
;
9842 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9843 connector
->base
.base
.id
,
9844 drm_get_connector_name(&connector
->base
),
9845 connector
->base
.encoder
? "enabled" : "disabled");
9849 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9850 * and i915 state tracking structures. */
9851 void intel_modeset_setup_hw_state(struct drm_device
*dev
,
9854 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9856 struct drm_plane
*plane
;
9857 struct intel_crtc
*crtc
;
9858 struct intel_encoder
*encoder
;
9860 intel_modeset_readout_hw_state(dev
);
9862 /* HW state is read out, now we need to sanitize this mess. */
9863 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9865 intel_sanitize_encoder(encoder
);
9868 for_each_pipe(pipe
) {
9869 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
9870 intel_sanitize_crtc(crtc
);
9871 intel_dump_pipe_config(crtc
, &crtc
->config
, "[setup_hw_state]");
9874 if (force_restore
) {
9876 * We need to use raw interfaces for restoring state to avoid
9877 * checking (bogus) intermediate states.
9879 for_each_pipe(pipe
) {
9880 struct drm_crtc
*crtc
=
9881 dev_priv
->pipe_to_crtc_mapping
[pipe
];
9883 __intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
,
9886 list_for_each_entry(plane
, &dev
->mode_config
.plane_list
, head
)
9887 intel_plane_restore(plane
);
9889 i915_redisable_vga(dev
);
9891 intel_modeset_update_staged_output_state(dev
);
9894 intel_modeset_check_state(dev
);
9896 drm_mode_config_reset(dev
);
9899 void intel_modeset_gem_init(struct drm_device
*dev
)
9901 intel_modeset_init_hw(dev
);
9903 intel_setup_overlay(dev
);
9905 intel_modeset_setup_hw_state(dev
, false);
9908 void intel_modeset_cleanup(struct drm_device
*dev
)
9910 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9911 struct drm_crtc
*crtc
;
9912 struct intel_crtc
*intel_crtc
;
9915 * Interrupts and polling as the first thing to avoid creating havoc.
9916 * Too much stuff here (turning of rps, connectors, ...) would
9917 * experience fancy races otherwise.
9919 drm_irq_uninstall(dev
);
9920 cancel_work_sync(&dev_priv
->hotplug_work
);
9922 * Due to the hpd irq storm handling the hotplug work can re-arm the
9923 * poll handlers. Hence disable polling after hpd handling is shut down.
9925 drm_kms_helper_poll_fini(dev
);
9927 mutex_lock(&dev
->struct_mutex
);
9929 intel_unregister_dsm_handler();
9931 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
9932 /* Skip inactive CRTCs */
9936 intel_crtc
= to_intel_crtc(crtc
);
9937 intel_increase_pllclock(crtc
);
9940 intel_disable_fbc(dev
);
9942 intel_disable_gt_powersave(dev
);
9944 ironlake_teardown_rc6(dev
);
9946 mutex_unlock(&dev
->struct_mutex
);
9948 /* flush any delayed tasks or pending work */
9949 flush_scheduled_work();
9951 /* destroy backlight, if any, before the connectors */
9952 intel_panel_destroy_backlight(dev
);
9954 drm_mode_config_cleanup(dev
);
9956 intel_cleanup_overlay(dev
);
9960 * Return which encoder is currently attached for connector.
9962 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
9964 return &intel_attached_encoder(connector
)->base
;
9967 void intel_connector_attach_encoder(struct intel_connector
*connector
,
9968 struct intel_encoder
*encoder
)
9970 connector
->encoder
= encoder
;
9971 drm_mode_connector_attach_encoder(&connector
->base
,
9976 * set vga decode state - true == enable VGA decode
9978 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
9980 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9983 pci_read_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, &gmch_ctrl
);
9985 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
9987 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
9988 pci_write_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, gmch_ctrl
);
9992 #ifdef CONFIG_DEBUG_FS
9993 #include <linux/seq_file.h>
9995 struct intel_display_error_state
{
9997 u32 power_well_driver
;
9999 struct intel_cursor_error_state
{
10004 } cursor
[I915_MAX_PIPES
];
10006 struct intel_pipe_error_state
{
10007 enum transcoder cpu_transcoder
;
10017 } pipe
[I915_MAX_PIPES
];
10019 struct intel_plane_error_state
{
10027 } plane
[I915_MAX_PIPES
];
10030 struct intel_display_error_state
*
10031 intel_display_capture_error_state(struct drm_device
*dev
)
10033 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
10034 struct intel_display_error_state
*error
;
10035 enum transcoder cpu_transcoder
;
10038 error
= kmalloc(sizeof(*error
), GFP_ATOMIC
);
10042 if (HAS_POWER_WELL(dev
))
10043 error
->power_well_driver
= I915_READ(HSW_PWR_WELL_DRIVER
);
10046 cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
, i
);
10047 error
->pipe
[i
].cpu_transcoder
= cpu_transcoder
;
10049 if (INTEL_INFO(dev
)->gen
<= 6 || IS_VALLEYVIEW(dev
)) {
10050 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
10051 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
10052 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
10054 error
->cursor
[i
].control
= I915_READ(CURCNTR_IVB(i
));
10055 error
->cursor
[i
].position
= I915_READ(CURPOS_IVB(i
));
10056 error
->cursor
[i
].base
= I915_READ(CURBASE_IVB(i
));
10059 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
10060 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
10061 if (INTEL_INFO(dev
)->gen
<= 3) {
10062 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
10063 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
10065 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
10066 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
10067 if (INTEL_INFO(dev
)->gen
>= 4) {
10068 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
10069 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
10072 error
->pipe
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
10073 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
10074 error
->pipe
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
10075 error
->pipe
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
10076 error
->pipe
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
10077 error
->pipe
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
10078 error
->pipe
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
10079 error
->pipe
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
10082 /* In the code above we read the registers without checking if the power
10083 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10084 * prevent the next I915_WRITE from detecting it and printing an error
10086 if (HAS_POWER_WELL(dev
))
10087 I915_WRITE_NOTRACE(FPGA_DBG
, FPGA_DBG_RM_NOCLAIM
);
10092 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10095 intel_display_print_error_state(struct drm_i915_error_state_buf
*m
,
10096 struct drm_device
*dev
,
10097 struct intel_display_error_state
*error
)
10101 err_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev
)->num_pipes
);
10102 if (HAS_POWER_WELL(dev
))
10103 err_printf(m
, "PWR_WELL_CTL2: %08x\n",
10104 error
->power_well_driver
);
10106 err_printf(m
, "Pipe [%d]:\n", i
);
10107 err_printf(m
, " CPU transcoder: %c\n",
10108 transcoder_name(error
->pipe
[i
].cpu_transcoder
));
10109 err_printf(m
, " CONF: %08x\n", error
->pipe
[i
].conf
);
10110 err_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
10111 err_printf(m
, " HTOTAL: %08x\n", error
->pipe
[i
].htotal
);
10112 err_printf(m
, " HBLANK: %08x\n", error
->pipe
[i
].hblank
);
10113 err_printf(m
, " HSYNC: %08x\n", error
->pipe
[i
].hsync
);
10114 err_printf(m
, " VTOTAL: %08x\n", error
->pipe
[i
].vtotal
);
10115 err_printf(m
, " VBLANK: %08x\n", error
->pipe
[i
].vblank
);
10116 err_printf(m
, " VSYNC: %08x\n", error
->pipe
[i
].vsync
);
10118 err_printf(m
, "Plane [%d]:\n", i
);
10119 err_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
10120 err_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
10121 if (INTEL_INFO(dev
)->gen
<= 3) {
10122 err_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
10123 err_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
10125 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
10126 err_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
10127 if (INTEL_INFO(dev
)->gen
>= 4) {
10128 err_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
10129 err_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
10132 err_printf(m
, "Cursor [%d]:\n", i
);
10133 err_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
10134 err_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
10135 err_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);