2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
44 static void intel_increase_pllclock(struct drm_crtc
*crtc
);
45 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
47 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
48 struct intel_crtc_config
*pipe_config
);
49 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
50 struct intel_crtc_config
*pipe_config
);
52 static int intel_set_mode(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
,
53 int x
, int y
, struct drm_framebuffer
*old_fb
);
65 typedef struct intel_limit intel_limit_t
;
67 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
72 intel_pch_rawclk(struct drm_device
*dev
)
74 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
76 WARN_ON(!HAS_PCH_SPLIT(dev
));
78 return I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
;
81 static inline u32
/* units of 100MHz */
82 intel_fdi_link_freq(struct drm_device
*dev
)
85 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
86 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
91 static const intel_limit_t intel_limits_i8xx_dac
= {
92 .dot
= { .min
= 25000, .max
= 350000 },
93 .vco
= { .min
= 930000, .max
= 1400000 },
94 .n
= { .min
= 3, .max
= 16 },
95 .m
= { .min
= 96, .max
= 140 },
96 .m1
= { .min
= 18, .max
= 26 },
97 .m2
= { .min
= 6, .max
= 16 },
98 .p
= { .min
= 4, .max
= 128 },
99 .p1
= { .min
= 2, .max
= 33 },
100 .p2
= { .dot_limit
= 165000,
101 .p2_slow
= 4, .p2_fast
= 2 },
104 static const intel_limit_t intel_limits_i8xx_dvo
= {
105 .dot
= { .min
= 25000, .max
= 350000 },
106 .vco
= { .min
= 930000, .max
= 1400000 },
107 .n
= { .min
= 3, .max
= 16 },
108 .m
= { .min
= 96, .max
= 140 },
109 .m1
= { .min
= 18, .max
= 26 },
110 .m2
= { .min
= 6, .max
= 16 },
111 .p
= { .min
= 4, .max
= 128 },
112 .p1
= { .min
= 2, .max
= 33 },
113 .p2
= { .dot_limit
= 165000,
114 .p2_slow
= 4, .p2_fast
= 4 },
117 static const intel_limit_t intel_limits_i8xx_lvds
= {
118 .dot
= { .min
= 25000, .max
= 350000 },
119 .vco
= { .min
= 930000, .max
= 1400000 },
120 .n
= { .min
= 3, .max
= 16 },
121 .m
= { .min
= 96, .max
= 140 },
122 .m1
= { .min
= 18, .max
= 26 },
123 .m2
= { .min
= 6, .max
= 16 },
124 .p
= { .min
= 4, .max
= 128 },
125 .p1
= { .min
= 1, .max
= 6 },
126 .p2
= { .dot_limit
= 165000,
127 .p2_slow
= 14, .p2_fast
= 7 },
130 static const intel_limit_t intel_limits_i9xx_sdvo
= {
131 .dot
= { .min
= 20000, .max
= 400000 },
132 .vco
= { .min
= 1400000, .max
= 2800000 },
133 .n
= { .min
= 1, .max
= 6 },
134 .m
= { .min
= 70, .max
= 120 },
135 .m1
= { .min
= 8, .max
= 18 },
136 .m2
= { .min
= 3, .max
= 7 },
137 .p
= { .min
= 5, .max
= 80 },
138 .p1
= { .min
= 1, .max
= 8 },
139 .p2
= { .dot_limit
= 200000,
140 .p2_slow
= 10, .p2_fast
= 5 },
143 static const intel_limit_t intel_limits_i9xx_lvds
= {
144 .dot
= { .min
= 20000, .max
= 400000 },
145 .vco
= { .min
= 1400000, .max
= 2800000 },
146 .n
= { .min
= 1, .max
= 6 },
147 .m
= { .min
= 70, .max
= 120 },
148 .m1
= { .min
= 8, .max
= 18 },
149 .m2
= { .min
= 3, .max
= 7 },
150 .p
= { .min
= 7, .max
= 98 },
151 .p1
= { .min
= 1, .max
= 8 },
152 .p2
= { .dot_limit
= 112000,
153 .p2_slow
= 14, .p2_fast
= 7 },
157 static const intel_limit_t intel_limits_g4x_sdvo
= {
158 .dot
= { .min
= 25000, .max
= 270000 },
159 .vco
= { .min
= 1750000, .max
= 3500000},
160 .n
= { .min
= 1, .max
= 4 },
161 .m
= { .min
= 104, .max
= 138 },
162 .m1
= { .min
= 17, .max
= 23 },
163 .m2
= { .min
= 5, .max
= 11 },
164 .p
= { .min
= 10, .max
= 30 },
165 .p1
= { .min
= 1, .max
= 3},
166 .p2
= { .dot_limit
= 270000,
172 static const intel_limit_t intel_limits_g4x_hdmi
= {
173 .dot
= { .min
= 22000, .max
= 400000 },
174 .vco
= { .min
= 1750000, .max
= 3500000},
175 .n
= { .min
= 1, .max
= 4 },
176 .m
= { .min
= 104, .max
= 138 },
177 .m1
= { .min
= 16, .max
= 23 },
178 .m2
= { .min
= 5, .max
= 11 },
179 .p
= { .min
= 5, .max
= 80 },
180 .p1
= { .min
= 1, .max
= 8},
181 .p2
= { .dot_limit
= 165000,
182 .p2_slow
= 10, .p2_fast
= 5 },
185 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
186 .dot
= { .min
= 20000, .max
= 115000 },
187 .vco
= { .min
= 1750000, .max
= 3500000 },
188 .n
= { .min
= 1, .max
= 3 },
189 .m
= { .min
= 104, .max
= 138 },
190 .m1
= { .min
= 17, .max
= 23 },
191 .m2
= { .min
= 5, .max
= 11 },
192 .p
= { .min
= 28, .max
= 112 },
193 .p1
= { .min
= 2, .max
= 8 },
194 .p2
= { .dot_limit
= 0,
195 .p2_slow
= 14, .p2_fast
= 14
199 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
200 .dot
= { .min
= 80000, .max
= 224000 },
201 .vco
= { .min
= 1750000, .max
= 3500000 },
202 .n
= { .min
= 1, .max
= 3 },
203 .m
= { .min
= 104, .max
= 138 },
204 .m1
= { .min
= 17, .max
= 23 },
205 .m2
= { .min
= 5, .max
= 11 },
206 .p
= { .min
= 14, .max
= 42 },
207 .p1
= { .min
= 2, .max
= 6 },
208 .p2
= { .dot_limit
= 0,
209 .p2_slow
= 7, .p2_fast
= 7
213 static const intel_limit_t intel_limits_pineview_sdvo
= {
214 .dot
= { .min
= 20000, .max
= 400000},
215 .vco
= { .min
= 1700000, .max
= 3500000 },
216 /* Pineview's Ncounter is a ring counter */
217 .n
= { .min
= 3, .max
= 6 },
218 .m
= { .min
= 2, .max
= 256 },
219 /* Pineview only has one combined m divider, which we treat as m2. */
220 .m1
= { .min
= 0, .max
= 0 },
221 .m2
= { .min
= 0, .max
= 254 },
222 .p
= { .min
= 5, .max
= 80 },
223 .p1
= { .min
= 1, .max
= 8 },
224 .p2
= { .dot_limit
= 200000,
225 .p2_slow
= 10, .p2_fast
= 5 },
228 static const intel_limit_t intel_limits_pineview_lvds
= {
229 .dot
= { .min
= 20000, .max
= 400000 },
230 .vco
= { .min
= 1700000, .max
= 3500000 },
231 .n
= { .min
= 3, .max
= 6 },
232 .m
= { .min
= 2, .max
= 256 },
233 .m1
= { .min
= 0, .max
= 0 },
234 .m2
= { .min
= 0, .max
= 254 },
235 .p
= { .min
= 7, .max
= 112 },
236 .p1
= { .min
= 1, .max
= 8 },
237 .p2
= { .dot_limit
= 112000,
238 .p2_slow
= 14, .p2_fast
= 14 },
241 /* Ironlake / Sandybridge
243 * We calculate clock using (register_value + 2) for N/M1/M2, so here
244 * the range value for them is (actual_value - 2).
246 static const intel_limit_t intel_limits_ironlake_dac
= {
247 .dot
= { .min
= 25000, .max
= 350000 },
248 .vco
= { .min
= 1760000, .max
= 3510000 },
249 .n
= { .min
= 1, .max
= 5 },
250 .m
= { .min
= 79, .max
= 127 },
251 .m1
= { .min
= 12, .max
= 22 },
252 .m2
= { .min
= 5, .max
= 9 },
253 .p
= { .min
= 5, .max
= 80 },
254 .p1
= { .min
= 1, .max
= 8 },
255 .p2
= { .dot_limit
= 225000,
256 .p2_slow
= 10, .p2_fast
= 5 },
259 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
260 .dot
= { .min
= 25000, .max
= 350000 },
261 .vco
= { .min
= 1760000, .max
= 3510000 },
262 .n
= { .min
= 1, .max
= 3 },
263 .m
= { .min
= 79, .max
= 118 },
264 .m1
= { .min
= 12, .max
= 22 },
265 .m2
= { .min
= 5, .max
= 9 },
266 .p
= { .min
= 28, .max
= 112 },
267 .p1
= { .min
= 2, .max
= 8 },
268 .p2
= { .dot_limit
= 225000,
269 .p2_slow
= 14, .p2_fast
= 14 },
272 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
273 .dot
= { .min
= 25000, .max
= 350000 },
274 .vco
= { .min
= 1760000, .max
= 3510000 },
275 .n
= { .min
= 1, .max
= 3 },
276 .m
= { .min
= 79, .max
= 127 },
277 .m1
= { .min
= 12, .max
= 22 },
278 .m2
= { .min
= 5, .max
= 9 },
279 .p
= { .min
= 14, .max
= 56 },
280 .p1
= { .min
= 2, .max
= 8 },
281 .p2
= { .dot_limit
= 225000,
282 .p2_slow
= 7, .p2_fast
= 7 },
285 /* LVDS 100mhz refclk limits. */
286 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
287 .dot
= { .min
= 25000, .max
= 350000 },
288 .vco
= { .min
= 1760000, .max
= 3510000 },
289 .n
= { .min
= 1, .max
= 2 },
290 .m
= { .min
= 79, .max
= 126 },
291 .m1
= { .min
= 12, .max
= 22 },
292 .m2
= { .min
= 5, .max
= 9 },
293 .p
= { .min
= 28, .max
= 112 },
294 .p1
= { .min
= 2, .max
= 8 },
295 .p2
= { .dot_limit
= 225000,
296 .p2_slow
= 14, .p2_fast
= 14 },
299 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
300 .dot
= { .min
= 25000, .max
= 350000 },
301 .vco
= { .min
= 1760000, .max
= 3510000 },
302 .n
= { .min
= 1, .max
= 3 },
303 .m
= { .min
= 79, .max
= 126 },
304 .m1
= { .min
= 12, .max
= 22 },
305 .m2
= { .min
= 5, .max
= 9 },
306 .p
= { .min
= 14, .max
= 42 },
307 .p1
= { .min
= 2, .max
= 6 },
308 .p2
= { .dot_limit
= 225000,
309 .p2_slow
= 7, .p2_fast
= 7 },
312 static const intel_limit_t intel_limits_vlv_dac
= {
313 .dot
= { .min
= 25000, .max
= 270000 },
314 .vco
= { .min
= 4000000, .max
= 6000000 },
315 .n
= { .min
= 1, .max
= 7 },
316 .m
= { .min
= 22, .max
= 450 }, /* guess */
317 .m1
= { .min
= 2, .max
= 3 },
318 .m2
= { .min
= 11, .max
= 156 },
319 .p
= { .min
= 10, .max
= 30 },
320 .p1
= { .min
= 1, .max
= 3 },
321 .p2
= { .dot_limit
= 270000,
322 .p2_slow
= 2, .p2_fast
= 20 },
325 static const intel_limit_t intel_limits_vlv_hdmi
= {
326 .dot
= { .min
= 25000, .max
= 270000 },
327 .vco
= { .min
= 4000000, .max
= 6000000 },
328 .n
= { .min
= 1, .max
= 7 },
329 .m
= { .min
= 60, .max
= 300 }, /* guess */
330 .m1
= { .min
= 2, .max
= 3 },
331 .m2
= { .min
= 11, .max
= 156 },
332 .p
= { .min
= 10, .max
= 30 },
333 .p1
= { .min
= 2, .max
= 3 },
334 .p2
= { .dot_limit
= 270000,
335 .p2_slow
= 2, .p2_fast
= 20 },
339 * Returns whether any output on the specified pipe is of the specified type
341 static bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
)
343 struct drm_device
*dev
= crtc
->dev
;
344 struct intel_encoder
*encoder
;
346 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
347 if (encoder
->type
== type
)
353 static const intel_limit_t
*intel_ironlake_limit(struct drm_crtc
*crtc
,
356 struct drm_device
*dev
= crtc
->dev
;
357 const intel_limit_t
*limit
;
359 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
360 if (intel_is_dual_link_lvds(dev
)) {
361 if (refclk
== 100000)
362 limit
= &intel_limits_ironlake_dual_lvds_100m
;
364 limit
= &intel_limits_ironlake_dual_lvds
;
366 if (refclk
== 100000)
367 limit
= &intel_limits_ironlake_single_lvds_100m
;
369 limit
= &intel_limits_ironlake_single_lvds
;
372 limit
= &intel_limits_ironlake_dac
;
377 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
379 struct drm_device
*dev
= crtc
->dev
;
380 const intel_limit_t
*limit
;
382 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
383 if (intel_is_dual_link_lvds(dev
))
384 limit
= &intel_limits_g4x_dual_channel_lvds
;
386 limit
= &intel_limits_g4x_single_channel_lvds
;
387 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
388 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
389 limit
= &intel_limits_g4x_hdmi
;
390 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
391 limit
= &intel_limits_g4x_sdvo
;
392 } else /* The option is for other outputs */
393 limit
= &intel_limits_i9xx_sdvo
;
398 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
, int refclk
)
400 struct drm_device
*dev
= crtc
->dev
;
401 const intel_limit_t
*limit
;
403 if (HAS_PCH_SPLIT(dev
))
404 limit
= intel_ironlake_limit(crtc
, refclk
);
405 else if (IS_G4X(dev
)) {
406 limit
= intel_g4x_limit(crtc
);
407 } else if (IS_PINEVIEW(dev
)) {
408 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
409 limit
= &intel_limits_pineview_lvds
;
411 limit
= &intel_limits_pineview_sdvo
;
412 } else if (IS_VALLEYVIEW(dev
)) {
413 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
))
414 limit
= &intel_limits_vlv_dac
;
416 limit
= &intel_limits_vlv_hdmi
;
417 } else if (!IS_GEN2(dev
)) {
418 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
419 limit
= &intel_limits_i9xx_lvds
;
421 limit
= &intel_limits_i9xx_sdvo
;
423 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
424 limit
= &intel_limits_i8xx_lvds
;
425 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
))
426 limit
= &intel_limits_i8xx_dvo
;
428 limit
= &intel_limits_i8xx_dac
;
433 /* m1 is reserved as 0 in Pineview, n is a ring counter */
434 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
436 clock
->m
= clock
->m2
+ 2;
437 clock
->p
= clock
->p1
* clock
->p2
;
438 clock
->vco
= refclk
* clock
->m
/ clock
->n
;
439 clock
->dot
= clock
->vco
/ clock
->p
;
442 static uint32_t i9xx_dpll_compute_m(struct dpll
*dpll
)
444 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
447 static void i9xx_clock(int refclk
, intel_clock_t
*clock
)
449 clock
->m
= i9xx_dpll_compute_m(clock
);
450 clock
->p
= clock
->p1
* clock
->p2
;
451 clock
->vco
= refclk
* clock
->m
/ (clock
->n
+ 2);
452 clock
->dot
= clock
->vco
/ clock
->p
;
455 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
457 * Returns whether the given set of divisors are valid for a given refclk with
458 * the given connectors.
461 static bool intel_PLL_is_valid(struct drm_device
*dev
,
462 const intel_limit_t
*limit
,
463 const intel_clock_t
*clock
)
465 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
466 INTELPllInvalid("p1 out of range\n");
467 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
468 INTELPllInvalid("p out of range\n");
469 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
470 INTELPllInvalid("m2 out of range\n");
471 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
472 INTELPllInvalid("m1 out of range\n");
473 if (clock
->m1
<= clock
->m2
&& !IS_PINEVIEW(dev
))
474 INTELPllInvalid("m1 <= m2\n");
475 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
476 INTELPllInvalid("m out of range\n");
477 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
478 INTELPllInvalid("n out of range\n");
479 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
480 INTELPllInvalid("vco out of range\n");
481 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
482 * connector, etc., rather than just a single range.
484 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
485 INTELPllInvalid("dot out of range\n");
491 i9xx_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
492 int target
, int refclk
, intel_clock_t
*match_clock
,
493 intel_clock_t
*best_clock
)
495 struct drm_device
*dev
= crtc
->dev
;
499 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
501 * For LVDS just rely on its current settings for dual-channel.
502 * We haven't figured out how to reliably set up different
503 * single/dual channel state, if we even can.
505 if (intel_is_dual_link_lvds(dev
))
506 clock
.p2
= limit
->p2
.p2_fast
;
508 clock
.p2
= limit
->p2
.p2_slow
;
510 if (target
< limit
->p2
.dot_limit
)
511 clock
.p2
= limit
->p2
.p2_slow
;
513 clock
.p2
= limit
->p2
.p2_fast
;
516 memset(best_clock
, 0, sizeof(*best_clock
));
518 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
520 for (clock
.m2
= limit
->m2
.min
;
521 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
522 if (clock
.m2
>= clock
.m1
)
524 for (clock
.n
= limit
->n
.min
;
525 clock
.n
<= limit
->n
.max
; clock
.n
++) {
526 for (clock
.p1
= limit
->p1
.min
;
527 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
530 i9xx_clock(refclk
, &clock
);
531 if (!intel_PLL_is_valid(dev
, limit
,
535 clock
.p
!= match_clock
->p
)
538 this_err
= abs(clock
.dot
- target
);
539 if (this_err
< err
) {
548 return (err
!= target
);
552 pnv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
553 int target
, int refclk
, intel_clock_t
*match_clock
,
554 intel_clock_t
*best_clock
)
556 struct drm_device
*dev
= crtc
->dev
;
560 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
562 * For LVDS just rely on its current settings for dual-channel.
563 * We haven't figured out how to reliably set up different
564 * single/dual channel state, if we even can.
566 if (intel_is_dual_link_lvds(dev
))
567 clock
.p2
= limit
->p2
.p2_fast
;
569 clock
.p2
= limit
->p2
.p2_slow
;
571 if (target
< limit
->p2
.dot_limit
)
572 clock
.p2
= limit
->p2
.p2_slow
;
574 clock
.p2
= limit
->p2
.p2_fast
;
577 memset(best_clock
, 0, sizeof(*best_clock
));
579 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
581 for (clock
.m2
= limit
->m2
.min
;
582 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
583 for (clock
.n
= limit
->n
.min
;
584 clock
.n
<= limit
->n
.max
; clock
.n
++) {
585 for (clock
.p1
= limit
->p1
.min
;
586 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
589 pineview_clock(refclk
, &clock
);
590 if (!intel_PLL_is_valid(dev
, limit
,
594 clock
.p
!= match_clock
->p
)
597 this_err
= abs(clock
.dot
- target
);
598 if (this_err
< err
) {
607 return (err
!= target
);
611 g4x_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
612 int target
, int refclk
, intel_clock_t
*match_clock
,
613 intel_clock_t
*best_clock
)
615 struct drm_device
*dev
= crtc
->dev
;
619 /* approximately equals target * 0.00585 */
620 int err_most
= (target
>> 8) + (target
>> 9);
623 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
624 if (intel_is_dual_link_lvds(dev
))
625 clock
.p2
= limit
->p2
.p2_fast
;
627 clock
.p2
= limit
->p2
.p2_slow
;
629 if (target
< limit
->p2
.dot_limit
)
630 clock
.p2
= limit
->p2
.p2_slow
;
632 clock
.p2
= limit
->p2
.p2_fast
;
635 memset(best_clock
, 0, sizeof(*best_clock
));
636 max_n
= limit
->n
.max
;
637 /* based on hardware requirement, prefer smaller n to precision */
638 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
639 /* based on hardware requirement, prefere larger m1,m2 */
640 for (clock
.m1
= limit
->m1
.max
;
641 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
642 for (clock
.m2
= limit
->m2
.max
;
643 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
644 for (clock
.p1
= limit
->p1
.max
;
645 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
648 i9xx_clock(refclk
, &clock
);
649 if (!intel_PLL_is_valid(dev
, limit
,
653 this_err
= abs(clock
.dot
- target
);
654 if (this_err
< err_most
) {
668 vlv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
669 int target
, int refclk
, intel_clock_t
*match_clock
,
670 intel_clock_t
*best_clock
)
672 u32 p1
, p2
, m1
, m2
, vco
, bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
674 u32 updrate
, minupdate
, p
;
675 unsigned long bestppm
, ppm
, absppm
;
679 dotclk
= target
* 1000;
682 fastclk
= dotclk
/ (2*100);
685 n
= p
= p1
= p2
= m
= m1
= m2
= vco
= bestn
= 0;
686 bestm1
= bestm2
= bestp1
= bestp2
= 0;
688 /* based on hardware requirement, prefer smaller n to precision */
689 for (n
= limit
->n
.min
; n
<= ((refclk
) / minupdate
); n
++) {
690 updrate
= refclk
/ n
;
691 for (p1
= limit
->p1
.max
; p1
> limit
->p1
.min
; p1
--) {
692 for (p2
= limit
->p2
.p2_fast
+1; p2
> 0; p2
--) {
696 /* based on hardware requirement, prefer bigger m1,m2 values */
697 for (m1
= limit
->m1
.min
; m1
<= limit
->m1
.max
; m1
++) {
698 m2
= (((2*(fastclk
* p
* n
/ m1
)) +
699 refclk
) / (2*refclk
));
702 if (vco
>= limit
->vco
.min
&& vco
< limit
->vco
.max
) {
703 ppm
= 1000000 * ((vco
/ p
) - fastclk
) / fastclk
;
704 absppm
= (ppm
> 0) ? ppm
: (-ppm
);
705 if (absppm
< 100 && ((p1
* p2
) > (bestp1
* bestp2
))) {
709 if (absppm
< bestppm
- 10) {
726 best_clock
->n
= bestn
;
727 best_clock
->m1
= bestm1
;
728 best_clock
->m2
= bestm2
;
729 best_clock
->p1
= bestp1
;
730 best_clock
->p2
= bestp2
;
735 bool intel_crtc_active(struct drm_crtc
*crtc
)
737 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
739 /* Be paranoid as we can arrive here with only partial
740 * state retrieved from the hardware during setup.
742 * We can ditch the adjusted_mode.clock check as soon
743 * as Haswell has gained clock readout/fastboot support.
745 * We can ditch the crtc->fb check as soon as we can
746 * properly reconstruct framebuffers.
748 return intel_crtc
->active
&& crtc
->fb
&&
749 intel_crtc
->config
.adjusted_mode
.clock
;
752 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
755 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
756 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
758 return intel_crtc
->config
.cpu_transcoder
;
761 static void ironlake_wait_for_vblank(struct drm_device
*dev
, int pipe
)
763 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
764 u32 frame
, frame_reg
= PIPEFRAME(pipe
);
766 frame
= I915_READ(frame_reg
);
768 if (wait_for(I915_READ_NOTRACE(frame_reg
) != frame
, 50))
769 DRM_DEBUG_KMS("vblank wait timed out\n");
773 * intel_wait_for_vblank - wait for vblank on a given pipe
775 * @pipe: pipe to wait for
777 * Wait for vblank to occur on a given pipe. Needed for various bits of
780 void intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
782 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
783 int pipestat_reg
= PIPESTAT(pipe
);
785 if (INTEL_INFO(dev
)->gen
>= 5) {
786 ironlake_wait_for_vblank(dev
, pipe
);
790 /* Clear existing vblank status. Note this will clear any other
791 * sticky status fields as well.
793 * This races with i915_driver_irq_handler() with the result
794 * that either function could miss a vblank event. Here it is not
795 * fatal, as we will either wait upon the next vblank interrupt or
796 * timeout. Generally speaking intel_wait_for_vblank() is only
797 * called during modeset at which time the GPU should be idle and
798 * should *not* be performing page flips and thus not waiting on
800 * Currently, the result of us stealing a vblank from the irq
801 * handler is that a single frame will be skipped during swapbuffers.
803 I915_WRITE(pipestat_reg
,
804 I915_READ(pipestat_reg
) | PIPE_VBLANK_INTERRUPT_STATUS
);
806 /* Wait for vblank interrupt bit to set */
807 if (wait_for(I915_READ(pipestat_reg
) &
808 PIPE_VBLANK_INTERRUPT_STATUS
,
810 DRM_DEBUG_KMS("vblank wait timed out\n");
814 * intel_wait_for_pipe_off - wait for pipe to turn off
816 * @pipe: pipe to wait for
818 * After disabling a pipe, we can't wait for vblank in the usual way,
819 * spinning on the vblank interrupt status bit, since we won't actually
820 * see an interrupt when the pipe is disabled.
823 * wait for the pipe register state bit to turn off
826 * wait for the display line value to settle (it usually
827 * ends up stopping at the start of the next frame).
830 void intel_wait_for_pipe_off(struct drm_device
*dev
, int pipe
)
832 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
833 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
836 if (INTEL_INFO(dev
)->gen
>= 4) {
837 int reg
= PIPECONF(cpu_transcoder
);
839 /* Wait for the Pipe State to go off */
840 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
842 WARN(1, "pipe_off wait timed out\n");
844 u32 last_line
, line_mask
;
845 int reg
= PIPEDSL(pipe
);
846 unsigned long timeout
= jiffies
+ msecs_to_jiffies(100);
849 line_mask
= DSL_LINEMASK_GEN2
;
851 line_mask
= DSL_LINEMASK_GEN3
;
853 /* Wait for the display line to settle */
855 last_line
= I915_READ(reg
) & line_mask
;
857 } while (((I915_READ(reg
) & line_mask
) != last_line
) &&
858 time_after(timeout
, jiffies
));
859 if (time_after(jiffies
, timeout
))
860 WARN(1, "pipe_off wait timed out\n");
865 * ibx_digital_port_connected - is the specified port connected?
866 * @dev_priv: i915 private structure
867 * @port: the port to test
869 * Returns true if @port is connected, false otherwise.
871 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
872 struct intel_digital_port
*port
)
876 if (HAS_PCH_IBX(dev_priv
->dev
)) {
879 bit
= SDE_PORTB_HOTPLUG
;
882 bit
= SDE_PORTC_HOTPLUG
;
885 bit
= SDE_PORTD_HOTPLUG
;
893 bit
= SDE_PORTB_HOTPLUG_CPT
;
896 bit
= SDE_PORTC_HOTPLUG_CPT
;
899 bit
= SDE_PORTD_HOTPLUG_CPT
;
906 return I915_READ(SDEISR
) & bit
;
909 static const char *state_string(bool enabled
)
911 return enabled
? "on" : "off";
914 /* Only for pre-ILK configs */
915 void assert_pll(struct drm_i915_private
*dev_priv
,
916 enum pipe pipe
, bool state
)
923 val
= I915_READ(reg
);
924 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
925 WARN(cur_state
!= state
,
926 "PLL state assertion failure (expected %s, current %s)\n",
927 state_string(state
), state_string(cur_state
));
930 /* XXX: the dsi pll is shared between MIPI DSI ports */
931 static void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
)
936 mutex_lock(&dev_priv
->dpio_lock
);
937 val
= vlv_cck_read(dev_priv
, CCK_REG_DSI_PLL_CONTROL
);
938 mutex_unlock(&dev_priv
->dpio_lock
);
940 cur_state
= val
& DSI_PLL_VCO_EN
;
941 WARN(cur_state
!= state
,
942 "DSI PLL state assertion failure (expected %s, current %s)\n",
943 state_string(state
), state_string(cur_state
));
945 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
946 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
948 struct intel_shared_dpll
*
949 intel_crtc_to_shared_dpll(struct intel_crtc
*crtc
)
951 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
953 if (crtc
->config
.shared_dpll
< 0)
956 return &dev_priv
->shared_dplls
[crtc
->config
.shared_dpll
];
960 void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
961 struct intel_shared_dpll
*pll
,
965 struct intel_dpll_hw_state hw_state
;
967 if (HAS_PCH_LPT(dev_priv
->dev
)) {
968 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
973 "asserting DPLL %s with no DPLL\n", state_string(state
)))
976 cur_state
= pll
->get_hw_state(dev_priv
, pll
, &hw_state
);
977 WARN(cur_state
!= state
,
978 "%s assertion failure (expected %s, current %s)\n",
979 pll
->name
, state_string(state
), state_string(cur_state
));
982 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
983 enum pipe pipe
, bool state
)
988 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
991 if (HAS_DDI(dev_priv
->dev
)) {
992 /* DDI does not have a specific FDI_TX register */
993 reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
994 val
= I915_READ(reg
);
995 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
997 reg
= FDI_TX_CTL(pipe
);
998 val
= I915_READ(reg
);
999 cur_state
= !!(val
& FDI_TX_ENABLE
);
1001 WARN(cur_state
!= state
,
1002 "FDI TX state assertion failure (expected %s, current %s)\n",
1003 state_string(state
), state_string(cur_state
));
1005 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1006 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1008 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1009 enum pipe pipe
, bool state
)
1015 reg
= FDI_RX_CTL(pipe
);
1016 val
= I915_READ(reg
);
1017 cur_state
= !!(val
& FDI_RX_ENABLE
);
1018 WARN(cur_state
!= state
,
1019 "FDI RX state assertion failure (expected %s, current %s)\n",
1020 state_string(state
), state_string(cur_state
));
1022 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1023 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1025 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1031 /* ILK FDI PLL is always enabled */
1032 if (dev_priv
->info
->gen
== 5)
1035 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1036 if (HAS_DDI(dev_priv
->dev
))
1039 reg
= FDI_TX_CTL(pipe
);
1040 val
= I915_READ(reg
);
1041 WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1044 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1045 enum pipe pipe
, bool state
)
1051 reg
= FDI_RX_CTL(pipe
);
1052 val
= I915_READ(reg
);
1053 cur_state
= !!(val
& FDI_RX_PLL_ENABLE
);
1054 WARN(cur_state
!= state
,
1055 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1056 state_string(state
), state_string(cur_state
));
1059 static void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1062 int pp_reg
, lvds_reg
;
1064 enum pipe panel_pipe
= PIPE_A
;
1067 if (HAS_PCH_SPLIT(dev_priv
->dev
)) {
1068 pp_reg
= PCH_PP_CONTROL
;
1069 lvds_reg
= PCH_LVDS
;
1071 pp_reg
= PP_CONTROL
;
1075 val
= I915_READ(pp_reg
);
1076 if (!(val
& PANEL_POWER_ON
) ||
1077 ((val
& PANEL_UNLOCK_REGS
) == PANEL_UNLOCK_REGS
))
1080 if (I915_READ(lvds_reg
) & LVDS_PIPEB_SELECT
)
1081 panel_pipe
= PIPE_B
;
1083 WARN(panel_pipe
== pipe
&& locked
,
1084 "panel assertion failure, pipe %c regs locked\n",
1088 static void assert_cursor(struct drm_i915_private
*dev_priv
,
1089 enum pipe pipe
, bool state
)
1091 struct drm_device
*dev
= dev_priv
->dev
;
1094 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
1095 cur_state
= I915_READ(CURCNTR_IVB(pipe
)) & CURSOR_MODE
;
1096 else if (IS_845G(dev
) || IS_I865G(dev
))
1097 cur_state
= I915_READ(_CURACNTR
) & CURSOR_ENABLE
;
1099 cur_state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
1101 WARN(cur_state
!= state
,
1102 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1103 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1105 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1106 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1108 void assert_pipe(struct drm_i915_private
*dev_priv
,
1109 enum pipe pipe
, bool state
)
1114 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1117 /* if we need the pipe A quirk it must be always on */
1118 if (pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
1121 if (!intel_display_power_enabled(dev_priv
->dev
,
1122 POWER_DOMAIN_TRANSCODER(cpu_transcoder
))) {
1125 reg
= PIPECONF(cpu_transcoder
);
1126 val
= I915_READ(reg
);
1127 cur_state
= !!(val
& PIPECONF_ENABLE
);
1130 WARN(cur_state
!= state
,
1131 "pipe %c assertion failure (expected %s, current %s)\n",
1132 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1135 static void assert_plane(struct drm_i915_private
*dev_priv
,
1136 enum plane plane
, bool state
)
1142 reg
= DSPCNTR(plane
);
1143 val
= I915_READ(reg
);
1144 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1145 WARN(cur_state
!= state
,
1146 "plane %c assertion failure (expected %s, current %s)\n",
1147 plane_name(plane
), state_string(state
), state_string(cur_state
));
1150 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1151 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1153 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1156 struct drm_device
*dev
= dev_priv
->dev
;
1161 /* Primary planes are fixed to pipes on gen4+ */
1162 if (INTEL_INFO(dev
)->gen
>= 4) {
1163 reg
= DSPCNTR(pipe
);
1164 val
= I915_READ(reg
);
1165 WARN((val
& DISPLAY_PLANE_ENABLE
),
1166 "plane %c assertion failure, should be disabled but not\n",
1171 /* Need to check both planes against the pipe */
1174 val
= I915_READ(reg
);
1175 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1176 DISPPLANE_SEL_PIPE_SHIFT
;
1177 WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1178 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1179 plane_name(i
), pipe_name(pipe
));
1183 static void assert_sprites_disabled(struct drm_i915_private
*dev_priv
,
1186 struct drm_device
*dev
= dev_priv
->dev
;
1190 if (IS_VALLEYVIEW(dev
)) {
1191 for (i
= 0; i
< dev_priv
->num_plane
; i
++) {
1192 reg
= SPCNTR(pipe
, i
);
1193 val
= I915_READ(reg
);
1194 WARN((val
& SP_ENABLE
),
1195 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1196 sprite_name(pipe
, i
), pipe_name(pipe
));
1198 } else if (INTEL_INFO(dev
)->gen
>= 7) {
1200 val
= I915_READ(reg
);
1201 WARN((val
& SPRITE_ENABLE
),
1202 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1203 plane_name(pipe
), pipe_name(pipe
));
1204 } else if (INTEL_INFO(dev
)->gen
>= 5) {
1205 reg
= DVSCNTR(pipe
);
1206 val
= I915_READ(reg
);
1207 WARN((val
& DVS_ENABLE
),
1208 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1209 plane_name(pipe
), pipe_name(pipe
));
1213 static void assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1218 if (HAS_PCH_LPT(dev_priv
->dev
)) {
1219 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1223 val
= I915_READ(PCH_DREF_CONTROL
);
1224 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1225 DREF_SUPERSPREAD_SOURCE_MASK
));
1226 WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1229 static void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1236 reg
= PCH_TRANSCONF(pipe
);
1237 val
= I915_READ(reg
);
1238 enabled
= !!(val
& TRANS_ENABLE
);
1240 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1244 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1245 enum pipe pipe
, u32 port_sel
, u32 val
)
1247 if ((val
& DP_PORT_EN
) == 0)
1250 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1251 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1252 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1253 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1256 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1262 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1263 enum pipe pipe
, u32 val
)
1265 if ((val
& SDVO_ENABLE
) == 0)
1268 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1269 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1272 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1278 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1279 enum pipe pipe
, u32 val
)
1281 if ((val
& LVDS_PORT_EN
) == 0)
1284 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1285 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1288 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1294 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1295 enum pipe pipe
, u32 val
)
1297 if ((val
& ADPA_DAC_ENABLE
) == 0)
1299 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1300 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1303 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1309 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1310 enum pipe pipe
, int reg
, u32 port_sel
)
1312 u32 val
= I915_READ(reg
);
1313 WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1314 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1315 reg
, pipe_name(pipe
));
1317 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& DP_PORT_EN
) == 0
1318 && (val
& DP_PIPEB_SELECT
),
1319 "IBX PCH dp port still using transcoder B\n");
1322 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1323 enum pipe pipe
, int reg
)
1325 u32 val
= I915_READ(reg
);
1326 WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1327 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1328 reg
, pipe_name(pipe
));
1330 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& SDVO_ENABLE
) == 0
1331 && (val
& SDVO_PIPE_B_SELECT
),
1332 "IBX PCH hdmi port still using transcoder B\n");
1335 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1341 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1342 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1343 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1346 val
= I915_READ(reg
);
1347 WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1348 "PCH VGA enabled on transcoder %c, should be disabled\n",
1352 val
= I915_READ(reg
);
1353 WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1354 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1357 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1358 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1359 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1362 static void vlv_enable_pll(struct intel_crtc
*crtc
)
1364 struct drm_device
*dev
= crtc
->base
.dev
;
1365 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1366 int reg
= DPLL(crtc
->pipe
);
1367 u32 dpll
= crtc
->config
.dpll_hw_state
.dpll
;
1369 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1371 /* No really, not for ILK+ */
1372 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
));
1374 /* PLL is protected by panel, make sure we can write it */
1375 if (IS_MOBILE(dev_priv
->dev
) && !IS_I830(dev_priv
->dev
))
1376 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1378 I915_WRITE(reg
, dpll
);
1382 if (wait_for(((I915_READ(reg
) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1383 DRM_ERROR("DPLL %d failed to lock\n", crtc
->pipe
);
1385 I915_WRITE(DPLL_MD(crtc
->pipe
), crtc
->config
.dpll_hw_state
.dpll_md
);
1386 POSTING_READ(DPLL_MD(crtc
->pipe
));
1388 /* We do this three times for luck */
1389 I915_WRITE(reg
, dpll
);
1391 udelay(150); /* wait for warmup */
1392 I915_WRITE(reg
, dpll
);
1394 udelay(150); /* wait for warmup */
1395 I915_WRITE(reg
, dpll
);
1397 udelay(150); /* wait for warmup */
1400 static void i9xx_enable_pll(struct intel_crtc
*crtc
)
1402 struct drm_device
*dev
= crtc
->base
.dev
;
1403 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1404 int reg
= DPLL(crtc
->pipe
);
1405 u32 dpll
= crtc
->config
.dpll_hw_state
.dpll
;
1407 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1409 /* No really, not for ILK+ */
1410 BUG_ON(dev_priv
->info
->gen
>= 5);
1412 /* PLL is protected by panel, make sure we can write it */
1413 if (IS_MOBILE(dev
) && !IS_I830(dev
))
1414 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1416 I915_WRITE(reg
, dpll
);
1418 /* Wait for the clocks to stabilize. */
1422 if (INTEL_INFO(dev
)->gen
>= 4) {
1423 I915_WRITE(DPLL_MD(crtc
->pipe
),
1424 crtc
->config
.dpll_hw_state
.dpll_md
);
1426 /* The pixel multiplier can only be updated once the
1427 * DPLL is enabled and the clocks are stable.
1429 * So write it again.
1431 I915_WRITE(reg
, dpll
);
1434 /* We do this three times for luck */
1435 I915_WRITE(reg
, dpll
);
1437 udelay(150); /* wait for warmup */
1438 I915_WRITE(reg
, dpll
);
1440 udelay(150); /* wait for warmup */
1441 I915_WRITE(reg
, dpll
);
1443 udelay(150); /* wait for warmup */
1447 * i9xx_disable_pll - disable a PLL
1448 * @dev_priv: i915 private structure
1449 * @pipe: pipe PLL to disable
1451 * Disable the PLL for @pipe, making sure the pipe is off first.
1453 * Note! This is for pre-ILK only.
1455 static void i9xx_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1457 /* Don't disable pipe A or pipe A PLLs if needed */
1458 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1461 /* Make sure the pipe isn't still relying on us */
1462 assert_pipe_disabled(dev_priv
, pipe
);
1464 I915_WRITE(DPLL(pipe
), 0);
1465 POSTING_READ(DPLL(pipe
));
1468 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
, int port
)
1473 port_mask
= DPLL_PORTB_READY_MASK
;
1475 port_mask
= DPLL_PORTC_READY_MASK
;
1477 if (wait_for((I915_READ(DPLL(0)) & port_mask
) == 0, 1000))
1478 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1479 'B' + port
, I915_READ(DPLL(0)));
1483 * ironlake_enable_shared_dpll - enable PCH PLL
1484 * @dev_priv: i915 private structure
1485 * @pipe: pipe PLL to enable
1487 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1488 * drives the transcoder clock.
1490 static void ironlake_enable_shared_dpll(struct intel_crtc
*crtc
)
1492 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1493 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1495 /* PCH PLLs only available on ILK, SNB and IVB */
1496 BUG_ON(dev_priv
->info
->gen
< 5);
1497 if (WARN_ON(pll
== NULL
))
1500 if (WARN_ON(pll
->refcount
== 0))
1503 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1504 pll
->name
, pll
->active
, pll
->on
,
1505 crtc
->base
.base
.id
);
1507 if (pll
->active
++) {
1509 assert_shared_dpll_enabled(dev_priv
, pll
);
1514 DRM_DEBUG_KMS("enabling %s\n", pll
->name
);
1515 pll
->enable(dev_priv
, pll
);
1519 static void intel_disable_shared_dpll(struct intel_crtc
*crtc
)
1521 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1522 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1524 /* PCH only available on ILK+ */
1525 BUG_ON(dev_priv
->info
->gen
< 5);
1526 if (WARN_ON(pll
== NULL
))
1529 if (WARN_ON(pll
->refcount
== 0))
1532 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1533 pll
->name
, pll
->active
, pll
->on
,
1534 crtc
->base
.base
.id
);
1536 if (WARN_ON(pll
->active
== 0)) {
1537 assert_shared_dpll_disabled(dev_priv
, pll
);
1541 assert_shared_dpll_enabled(dev_priv
, pll
);
1546 DRM_DEBUG_KMS("disabling %s\n", pll
->name
);
1547 pll
->disable(dev_priv
, pll
);
1551 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1554 struct drm_device
*dev
= dev_priv
->dev
;
1555 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1556 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1557 uint32_t reg
, val
, pipeconf_val
;
1559 /* PCH only available on ILK+ */
1560 BUG_ON(dev_priv
->info
->gen
< 5);
1562 /* Make sure PCH DPLL is enabled */
1563 assert_shared_dpll_enabled(dev_priv
,
1564 intel_crtc_to_shared_dpll(intel_crtc
));
1566 /* FDI must be feeding us bits for PCH ports */
1567 assert_fdi_tx_enabled(dev_priv
, pipe
);
1568 assert_fdi_rx_enabled(dev_priv
, pipe
);
1570 if (HAS_PCH_CPT(dev
)) {
1571 /* Workaround: Set the timing override bit before enabling the
1572 * pch transcoder. */
1573 reg
= TRANS_CHICKEN2(pipe
);
1574 val
= I915_READ(reg
);
1575 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1576 I915_WRITE(reg
, val
);
1579 reg
= PCH_TRANSCONF(pipe
);
1580 val
= I915_READ(reg
);
1581 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1583 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1585 * make the BPC in transcoder be consistent with
1586 * that in pipeconf reg.
1588 val
&= ~PIPECONF_BPC_MASK
;
1589 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
1592 val
&= ~TRANS_INTERLACE_MASK
;
1593 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1594 if (HAS_PCH_IBX(dev_priv
->dev
) &&
1595 intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
))
1596 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1598 val
|= TRANS_INTERLACED
;
1600 val
|= TRANS_PROGRESSIVE
;
1602 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1603 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1604 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
1607 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1608 enum transcoder cpu_transcoder
)
1610 u32 val
, pipeconf_val
;
1612 /* PCH only available on ILK+ */
1613 BUG_ON(dev_priv
->info
->gen
< 5);
1615 /* FDI must be feeding us bits for PCH ports */
1616 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
1617 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
1619 /* Workaround: set timing override bit. */
1620 val
= I915_READ(_TRANSA_CHICKEN2
);
1621 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1622 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1625 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
1627 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
1628 PIPECONF_INTERLACED_ILK
)
1629 val
|= TRANS_INTERLACED
;
1631 val
|= TRANS_PROGRESSIVE
;
1633 I915_WRITE(LPT_TRANSCONF
, val
);
1634 if (wait_for(I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
, 100))
1635 DRM_ERROR("Failed to enable PCH transcoder\n");
1638 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1641 struct drm_device
*dev
= dev_priv
->dev
;
1644 /* FDI relies on the transcoder */
1645 assert_fdi_tx_disabled(dev_priv
, pipe
);
1646 assert_fdi_rx_disabled(dev_priv
, pipe
);
1648 /* Ports must be off as well */
1649 assert_pch_ports_disabled(dev_priv
, pipe
);
1651 reg
= PCH_TRANSCONF(pipe
);
1652 val
= I915_READ(reg
);
1653 val
&= ~TRANS_ENABLE
;
1654 I915_WRITE(reg
, val
);
1655 /* wait for PCH transcoder off, transcoder state */
1656 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
1657 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
1659 if (!HAS_PCH_IBX(dev
)) {
1660 /* Workaround: Clear the timing override chicken bit again. */
1661 reg
= TRANS_CHICKEN2(pipe
);
1662 val
= I915_READ(reg
);
1663 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1664 I915_WRITE(reg
, val
);
1668 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
1672 val
= I915_READ(LPT_TRANSCONF
);
1673 val
&= ~TRANS_ENABLE
;
1674 I915_WRITE(LPT_TRANSCONF
, val
);
1675 /* wait for PCH transcoder off, transcoder state */
1676 if (wait_for((I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
) == 0, 50))
1677 DRM_ERROR("Failed to disable PCH transcoder\n");
1679 /* Workaround: clear timing override bit. */
1680 val
= I915_READ(_TRANSA_CHICKEN2
);
1681 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1682 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1686 * intel_enable_pipe - enable a pipe, asserting requirements
1687 * @dev_priv: i915 private structure
1688 * @pipe: pipe to enable
1689 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1691 * Enable @pipe, making sure that various hardware specific requirements
1692 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1694 * @pipe should be %PIPE_A or %PIPE_B.
1696 * Will wait until the pipe is actually running (i.e. first vblank) before
1699 static void intel_enable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
1700 bool pch_port
, bool dsi
)
1702 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1704 enum pipe pch_transcoder
;
1708 assert_planes_disabled(dev_priv
, pipe
);
1709 assert_cursor_disabled(dev_priv
, pipe
);
1710 assert_sprites_disabled(dev_priv
, pipe
);
1712 if (HAS_PCH_LPT(dev_priv
->dev
))
1713 pch_transcoder
= TRANSCODER_A
;
1715 pch_transcoder
= pipe
;
1718 * A pipe without a PLL won't actually be able to drive bits from
1719 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1722 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
1724 assert_dsi_pll_enabled(dev_priv
);
1726 assert_pll_enabled(dev_priv
, pipe
);
1729 /* if driving the PCH, we need FDI enabled */
1730 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
1731 assert_fdi_tx_pll_enabled(dev_priv
,
1732 (enum pipe
) cpu_transcoder
);
1734 /* FIXME: assert CPU port conditions for SNB+ */
1737 reg
= PIPECONF(cpu_transcoder
);
1738 val
= I915_READ(reg
);
1739 if (val
& PIPECONF_ENABLE
)
1742 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
1743 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1747 * intel_disable_pipe - disable a pipe, asserting requirements
1748 * @dev_priv: i915 private structure
1749 * @pipe: pipe to disable
1751 * Disable @pipe, making sure that various hardware specific requirements
1752 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1754 * @pipe should be %PIPE_A or %PIPE_B.
1756 * Will wait until the pipe has shut down before returning.
1758 static void intel_disable_pipe(struct drm_i915_private
*dev_priv
,
1761 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1767 * Make sure planes won't keep trying to pump pixels to us,
1768 * or we might hang the display.
1770 assert_planes_disabled(dev_priv
, pipe
);
1771 assert_cursor_disabled(dev_priv
, pipe
);
1772 assert_sprites_disabled(dev_priv
, pipe
);
1774 /* Don't disable pipe A or pipe A PLLs if needed */
1775 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1778 reg
= PIPECONF(cpu_transcoder
);
1779 val
= I915_READ(reg
);
1780 if ((val
& PIPECONF_ENABLE
) == 0)
1783 I915_WRITE(reg
, val
& ~PIPECONF_ENABLE
);
1784 intel_wait_for_pipe_off(dev_priv
->dev
, pipe
);
1788 * Plane regs are double buffered, going from enabled->disabled needs a
1789 * trigger in order to latch. The display address reg provides this.
1791 void intel_flush_display_plane(struct drm_i915_private
*dev_priv
,
1794 if (dev_priv
->info
->gen
>= 4)
1795 I915_WRITE(DSPSURF(plane
), I915_READ(DSPSURF(plane
)));
1797 I915_WRITE(DSPADDR(plane
), I915_READ(DSPADDR(plane
)));
1801 * intel_enable_plane - enable a display plane on a given pipe
1802 * @dev_priv: i915 private structure
1803 * @plane: plane to enable
1804 * @pipe: pipe being fed
1806 * Enable @plane on @pipe, making sure that @pipe is running first.
1808 static void intel_enable_plane(struct drm_i915_private
*dev_priv
,
1809 enum plane plane
, enum pipe pipe
)
1814 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1815 assert_pipe_enabled(dev_priv
, pipe
);
1817 reg
= DSPCNTR(plane
);
1818 val
= I915_READ(reg
);
1819 if (val
& DISPLAY_PLANE_ENABLE
)
1822 I915_WRITE(reg
, val
| DISPLAY_PLANE_ENABLE
);
1823 intel_flush_display_plane(dev_priv
, plane
);
1824 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1828 * intel_disable_plane - disable a display plane
1829 * @dev_priv: i915 private structure
1830 * @plane: plane to disable
1831 * @pipe: pipe consuming the data
1833 * Disable @plane; should be an independent operation.
1835 static void intel_disable_plane(struct drm_i915_private
*dev_priv
,
1836 enum plane plane
, enum pipe pipe
)
1841 reg
= DSPCNTR(plane
);
1842 val
= I915_READ(reg
);
1843 if ((val
& DISPLAY_PLANE_ENABLE
) == 0)
1846 I915_WRITE(reg
, val
& ~DISPLAY_PLANE_ENABLE
);
1847 intel_flush_display_plane(dev_priv
, plane
);
1848 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1851 static bool need_vtd_wa(struct drm_device
*dev
)
1853 #ifdef CONFIG_INTEL_IOMMU
1854 if (INTEL_INFO(dev
)->gen
>= 6 && intel_iommu_gfx_mapped
)
1861 intel_pin_and_fence_fb_obj(struct drm_device
*dev
,
1862 struct drm_i915_gem_object
*obj
,
1863 struct intel_ring_buffer
*pipelined
)
1865 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1869 switch (obj
->tiling_mode
) {
1870 case I915_TILING_NONE
:
1871 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
1872 alignment
= 128 * 1024;
1873 else if (INTEL_INFO(dev
)->gen
>= 4)
1874 alignment
= 4 * 1024;
1876 alignment
= 64 * 1024;
1879 /* pin() will align the object as required by fence */
1883 /* Despite that we check this in framebuffer_init userspace can
1884 * screw us over and change the tiling after the fact. Only
1885 * pinned buffers can't change their tiling. */
1886 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1892 /* Note that the w/a also requires 64 PTE of padding following the
1893 * bo. We currently fill all unused PTE with the shadow page and so
1894 * we should always have valid PTE following the scanout preventing
1897 if (need_vtd_wa(dev
) && alignment
< 256 * 1024)
1898 alignment
= 256 * 1024;
1900 dev_priv
->mm
.interruptible
= false;
1901 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
);
1903 goto err_interruptible
;
1905 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1906 * fence, whereas 965+ only requires a fence if using
1907 * framebuffer compression. For simplicity, we always install
1908 * a fence as the cost is not that onerous.
1910 ret
= i915_gem_object_get_fence(obj
);
1914 i915_gem_object_pin_fence(obj
);
1916 dev_priv
->mm
.interruptible
= true;
1920 i915_gem_object_unpin_from_display_plane(obj
);
1922 dev_priv
->mm
.interruptible
= true;
1926 void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
)
1928 i915_gem_object_unpin_fence(obj
);
1929 i915_gem_object_unpin_from_display_plane(obj
);
1932 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1933 * is assumed to be a power-of-two. */
1934 unsigned long intel_gen4_compute_page_offset(int *x
, int *y
,
1935 unsigned int tiling_mode
,
1939 if (tiling_mode
!= I915_TILING_NONE
) {
1940 unsigned int tile_rows
, tiles
;
1945 tiles
= *x
/ (512/cpp
);
1948 return tile_rows
* pitch
* 8 + tiles
* 4096;
1950 unsigned int offset
;
1952 offset
= *y
* pitch
+ *x
* cpp
;
1954 *x
= (offset
& 4095) / cpp
;
1955 return offset
& -4096;
1959 static int i9xx_update_plane(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
1962 struct drm_device
*dev
= crtc
->dev
;
1963 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1964 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1965 struct intel_framebuffer
*intel_fb
;
1966 struct drm_i915_gem_object
*obj
;
1967 int plane
= intel_crtc
->plane
;
1968 unsigned long linear_offset
;
1977 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane
));
1981 intel_fb
= to_intel_framebuffer(fb
);
1982 obj
= intel_fb
->obj
;
1984 reg
= DSPCNTR(plane
);
1985 dspcntr
= I915_READ(reg
);
1986 /* Mask out pixel format bits in case we change it */
1987 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
1988 switch (fb
->pixel_format
) {
1990 dspcntr
|= DISPPLANE_8BPP
;
1992 case DRM_FORMAT_XRGB1555
:
1993 case DRM_FORMAT_ARGB1555
:
1994 dspcntr
|= DISPPLANE_BGRX555
;
1996 case DRM_FORMAT_RGB565
:
1997 dspcntr
|= DISPPLANE_BGRX565
;
1999 case DRM_FORMAT_XRGB8888
:
2000 case DRM_FORMAT_ARGB8888
:
2001 dspcntr
|= DISPPLANE_BGRX888
;
2003 case DRM_FORMAT_XBGR8888
:
2004 case DRM_FORMAT_ABGR8888
:
2005 dspcntr
|= DISPPLANE_RGBX888
;
2007 case DRM_FORMAT_XRGB2101010
:
2008 case DRM_FORMAT_ARGB2101010
:
2009 dspcntr
|= DISPPLANE_BGRX101010
;
2011 case DRM_FORMAT_XBGR2101010
:
2012 case DRM_FORMAT_ABGR2101010
:
2013 dspcntr
|= DISPPLANE_RGBX101010
;
2019 if (INTEL_INFO(dev
)->gen
>= 4) {
2020 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2021 dspcntr
|= DISPPLANE_TILED
;
2023 dspcntr
&= ~DISPPLANE_TILED
;
2027 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2029 I915_WRITE(reg
, dspcntr
);
2031 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2033 if (INTEL_INFO(dev
)->gen
>= 4) {
2034 intel_crtc
->dspaddr_offset
=
2035 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2036 fb
->bits_per_pixel
/ 8,
2038 linear_offset
-= intel_crtc
->dspaddr_offset
;
2040 intel_crtc
->dspaddr_offset
= linear_offset
;
2043 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2044 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2046 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2047 if (INTEL_INFO(dev
)->gen
>= 4) {
2048 I915_MODIFY_DISPBASE(DSPSURF(plane
),
2049 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2050 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2051 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2053 I915_WRITE(DSPADDR(plane
), i915_gem_obj_ggtt_offset(obj
) + linear_offset
);
2059 static int ironlake_update_plane(struct drm_crtc
*crtc
,
2060 struct drm_framebuffer
*fb
, int x
, int y
)
2062 struct drm_device
*dev
= crtc
->dev
;
2063 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2064 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2065 struct intel_framebuffer
*intel_fb
;
2066 struct drm_i915_gem_object
*obj
;
2067 int plane
= intel_crtc
->plane
;
2068 unsigned long linear_offset
;
2078 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane
));
2082 intel_fb
= to_intel_framebuffer(fb
);
2083 obj
= intel_fb
->obj
;
2085 reg
= DSPCNTR(plane
);
2086 dspcntr
= I915_READ(reg
);
2087 /* Mask out pixel format bits in case we change it */
2088 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2089 switch (fb
->pixel_format
) {
2091 dspcntr
|= DISPPLANE_8BPP
;
2093 case DRM_FORMAT_RGB565
:
2094 dspcntr
|= DISPPLANE_BGRX565
;
2096 case DRM_FORMAT_XRGB8888
:
2097 case DRM_FORMAT_ARGB8888
:
2098 dspcntr
|= DISPPLANE_BGRX888
;
2100 case DRM_FORMAT_XBGR8888
:
2101 case DRM_FORMAT_ABGR8888
:
2102 dspcntr
|= DISPPLANE_RGBX888
;
2104 case DRM_FORMAT_XRGB2101010
:
2105 case DRM_FORMAT_ARGB2101010
:
2106 dspcntr
|= DISPPLANE_BGRX101010
;
2108 case DRM_FORMAT_XBGR2101010
:
2109 case DRM_FORMAT_ABGR2101010
:
2110 dspcntr
|= DISPPLANE_RGBX101010
;
2116 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2117 dspcntr
|= DISPPLANE_TILED
;
2119 dspcntr
&= ~DISPPLANE_TILED
;
2121 if (IS_HASWELL(dev
))
2122 dspcntr
&= ~DISPPLANE_TRICKLE_FEED_DISABLE
;
2124 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2126 I915_WRITE(reg
, dspcntr
);
2128 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2129 intel_crtc
->dspaddr_offset
=
2130 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2131 fb
->bits_per_pixel
/ 8,
2133 linear_offset
-= intel_crtc
->dspaddr_offset
;
2135 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2136 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2138 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2139 I915_MODIFY_DISPBASE(DSPSURF(plane
),
2140 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2141 if (IS_HASWELL(dev
)) {
2142 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2144 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2145 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2152 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2154 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2155 int x
, int y
, enum mode_set_atomic state
)
2157 struct drm_device
*dev
= crtc
->dev
;
2158 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2160 if (dev_priv
->display
.disable_fbc
)
2161 dev_priv
->display
.disable_fbc(dev
);
2162 intel_increase_pllclock(crtc
);
2164 return dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2167 void intel_display_handle_reset(struct drm_device
*dev
)
2169 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2170 struct drm_crtc
*crtc
;
2173 * Flips in the rings have been nuked by the reset,
2174 * so complete all pending flips so that user space
2175 * will get its events and not get stuck.
2177 * Also update the base address of all primary
2178 * planes to the the last fb to make sure we're
2179 * showing the correct fb after a reset.
2181 * Need to make two loops over the crtcs so that we
2182 * don't try to grab a crtc mutex before the
2183 * pending_flip_queue really got woken up.
2186 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2187 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2188 enum plane plane
= intel_crtc
->plane
;
2190 intel_prepare_page_flip(dev
, plane
);
2191 intel_finish_page_flip_plane(dev
, plane
);
2194 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2195 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2197 mutex_lock(&crtc
->mutex
);
2198 if (intel_crtc
->active
)
2199 dev_priv
->display
.update_plane(crtc
, crtc
->fb
,
2201 mutex_unlock(&crtc
->mutex
);
2206 intel_finish_fb(struct drm_framebuffer
*old_fb
)
2208 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(old_fb
)->obj
;
2209 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2210 bool was_interruptible
= dev_priv
->mm
.interruptible
;
2213 /* Big Hammer, we also need to ensure that any pending
2214 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2215 * current scanout is retired before unpinning the old
2218 * This should only fail upon a hung GPU, in which case we
2219 * can safely continue.
2221 dev_priv
->mm
.interruptible
= false;
2222 ret
= i915_gem_object_finish_gpu(obj
);
2223 dev_priv
->mm
.interruptible
= was_interruptible
;
2228 static void intel_crtc_update_sarea_pos(struct drm_crtc
*crtc
, int x
, int y
)
2230 struct drm_device
*dev
= crtc
->dev
;
2231 struct drm_i915_master_private
*master_priv
;
2232 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2234 if (!dev
->primary
->master
)
2237 master_priv
= dev
->primary
->master
->driver_priv
;
2238 if (!master_priv
->sarea_priv
)
2241 switch (intel_crtc
->pipe
) {
2243 master_priv
->sarea_priv
->pipeA_x
= x
;
2244 master_priv
->sarea_priv
->pipeA_y
= y
;
2247 master_priv
->sarea_priv
->pipeB_x
= x
;
2248 master_priv
->sarea_priv
->pipeB_y
= y
;
2256 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2257 struct drm_framebuffer
*fb
)
2259 struct drm_device
*dev
= crtc
->dev
;
2260 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2261 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2262 struct drm_framebuffer
*old_fb
;
2267 DRM_ERROR("No FB bound\n");
2271 if (intel_crtc
->plane
> INTEL_INFO(dev
)->num_pipes
) {
2272 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2273 plane_name(intel_crtc
->plane
),
2274 INTEL_INFO(dev
)->num_pipes
);
2278 mutex_lock(&dev
->struct_mutex
);
2279 ret
= intel_pin_and_fence_fb_obj(dev
,
2280 to_intel_framebuffer(fb
)->obj
,
2283 mutex_unlock(&dev
->struct_mutex
);
2284 DRM_ERROR("pin & fence failed\n");
2288 /* Update pipe size and adjust fitter if needed */
2289 if (i915_fastboot
) {
2290 I915_WRITE(PIPESRC(intel_crtc
->pipe
),
2291 ((crtc
->mode
.hdisplay
- 1) << 16) |
2292 (crtc
->mode
.vdisplay
- 1));
2293 if (!intel_crtc
->config
.pch_pfit
.enabled
&&
2294 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) ||
2295 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
2296 I915_WRITE(PF_CTL(intel_crtc
->pipe
), 0);
2297 I915_WRITE(PF_WIN_POS(intel_crtc
->pipe
), 0);
2298 I915_WRITE(PF_WIN_SZ(intel_crtc
->pipe
), 0);
2302 ret
= dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2304 intel_unpin_fb_obj(to_intel_framebuffer(fb
)->obj
);
2305 mutex_unlock(&dev
->struct_mutex
);
2306 DRM_ERROR("failed to update base address\n");
2316 if (intel_crtc
->active
&& old_fb
!= fb
)
2317 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2318 intel_unpin_fb_obj(to_intel_framebuffer(old_fb
)->obj
);
2321 intel_update_fbc(dev
);
2322 intel_edp_psr_update(dev
);
2323 mutex_unlock(&dev
->struct_mutex
);
2325 intel_crtc_update_sarea_pos(crtc
, x
, y
);
2330 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
2332 struct drm_device
*dev
= crtc
->dev
;
2333 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2334 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2335 int pipe
= intel_crtc
->pipe
;
2338 /* enable normal train */
2339 reg
= FDI_TX_CTL(pipe
);
2340 temp
= I915_READ(reg
);
2341 if (IS_IVYBRIDGE(dev
)) {
2342 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2343 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2345 temp
&= ~FDI_LINK_TRAIN_NONE
;
2346 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2348 I915_WRITE(reg
, temp
);
2350 reg
= FDI_RX_CTL(pipe
);
2351 temp
= I915_READ(reg
);
2352 if (HAS_PCH_CPT(dev
)) {
2353 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2354 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
2356 temp
&= ~FDI_LINK_TRAIN_NONE
;
2357 temp
|= FDI_LINK_TRAIN_NONE
;
2359 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
2361 /* wait one idle pattern time */
2365 /* IVB wants error correction enabled */
2366 if (IS_IVYBRIDGE(dev
))
2367 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
2368 FDI_FE_ERRC_ENABLE
);
2371 static bool pipe_has_enabled_pch(struct intel_crtc
*intel_crtc
)
2373 return intel_crtc
->base
.enabled
&& intel_crtc
->config
.has_pch_encoder
;
2376 static void ivb_modeset_global_resources(struct drm_device
*dev
)
2378 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2379 struct intel_crtc
*pipe_B_crtc
=
2380 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
2381 struct intel_crtc
*pipe_C_crtc
=
2382 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]);
2386 * When everything is off disable fdi C so that we could enable fdi B
2387 * with all lanes. Note that we don't care about enabled pipes without
2388 * an enabled pch encoder.
2390 if (!pipe_has_enabled_pch(pipe_B_crtc
) &&
2391 !pipe_has_enabled_pch(pipe_C_crtc
)) {
2392 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
2393 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
2395 temp
= I915_READ(SOUTH_CHICKEN1
);
2396 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
2397 DRM_DEBUG_KMS("disabling fdi C rx\n");
2398 I915_WRITE(SOUTH_CHICKEN1
, temp
);
2402 /* The FDI link training functions for ILK/Ibexpeak. */
2403 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
2405 struct drm_device
*dev
= crtc
->dev
;
2406 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2407 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2408 int pipe
= intel_crtc
->pipe
;
2409 int plane
= intel_crtc
->plane
;
2410 u32 reg
, temp
, tries
;
2412 /* FDI needs bits from pipe & plane first */
2413 assert_pipe_enabled(dev_priv
, pipe
);
2414 assert_plane_enabled(dev_priv
, plane
);
2416 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2418 reg
= FDI_RX_IMR(pipe
);
2419 temp
= I915_READ(reg
);
2420 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2421 temp
&= ~FDI_RX_BIT_LOCK
;
2422 I915_WRITE(reg
, temp
);
2426 /* enable CPU FDI TX and PCH FDI RX */
2427 reg
= FDI_TX_CTL(pipe
);
2428 temp
= I915_READ(reg
);
2429 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
2430 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2431 temp
&= ~FDI_LINK_TRAIN_NONE
;
2432 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2433 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2435 reg
= FDI_RX_CTL(pipe
);
2436 temp
= I915_READ(reg
);
2437 temp
&= ~FDI_LINK_TRAIN_NONE
;
2438 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2439 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2444 /* Ironlake workaround, enable clock pointer after FDI enable*/
2445 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2446 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
2447 FDI_RX_PHASE_SYNC_POINTER_EN
);
2449 reg
= FDI_RX_IIR(pipe
);
2450 for (tries
= 0; tries
< 5; tries
++) {
2451 temp
= I915_READ(reg
);
2452 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2454 if ((temp
& FDI_RX_BIT_LOCK
)) {
2455 DRM_DEBUG_KMS("FDI train 1 done.\n");
2456 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2461 DRM_ERROR("FDI train 1 fail!\n");
2464 reg
= FDI_TX_CTL(pipe
);
2465 temp
= I915_READ(reg
);
2466 temp
&= ~FDI_LINK_TRAIN_NONE
;
2467 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2468 I915_WRITE(reg
, temp
);
2470 reg
= FDI_RX_CTL(pipe
);
2471 temp
= I915_READ(reg
);
2472 temp
&= ~FDI_LINK_TRAIN_NONE
;
2473 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2474 I915_WRITE(reg
, temp
);
2479 reg
= FDI_RX_IIR(pipe
);
2480 for (tries
= 0; tries
< 5; tries
++) {
2481 temp
= I915_READ(reg
);
2482 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2484 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2485 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2486 DRM_DEBUG_KMS("FDI train 2 done.\n");
2491 DRM_ERROR("FDI train 2 fail!\n");
2493 DRM_DEBUG_KMS("FDI train done\n");
2497 static const int snb_b_fdi_train_param
[] = {
2498 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
2499 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
2500 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
2501 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
2504 /* The FDI link training functions for SNB/Cougarpoint. */
2505 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
2507 struct drm_device
*dev
= crtc
->dev
;
2508 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2509 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2510 int pipe
= intel_crtc
->pipe
;
2511 u32 reg
, temp
, i
, retry
;
2513 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2515 reg
= FDI_RX_IMR(pipe
);
2516 temp
= I915_READ(reg
);
2517 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2518 temp
&= ~FDI_RX_BIT_LOCK
;
2519 I915_WRITE(reg
, temp
);
2524 /* enable CPU FDI TX and PCH FDI RX */
2525 reg
= FDI_TX_CTL(pipe
);
2526 temp
= I915_READ(reg
);
2527 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
2528 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2529 temp
&= ~FDI_LINK_TRAIN_NONE
;
2530 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2531 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2533 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2534 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2536 I915_WRITE(FDI_RX_MISC(pipe
),
2537 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
2539 reg
= FDI_RX_CTL(pipe
);
2540 temp
= I915_READ(reg
);
2541 if (HAS_PCH_CPT(dev
)) {
2542 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2543 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2545 temp
&= ~FDI_LINK_TRAIN_NONE
;
2546 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2548 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2553 for (i
= 0; i
< 4; i
++) {
2554 reg
= FDI_TX_CTL(pipe
);
2555 temp
= I915_READ(reg
);
2556 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2557 temp
|= snb_b_fdi_train_param
[i
];
2558 I915_WRITE(reg
, temp
);
2563 for (retry
= 0; retry
< 5; retry
++) {
2564 reg
= FDI_RX_IIR(pipe
);
2565 temp
= I915_READ(reg
);
2566 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2567 if (temp
& FDI_RX_BIT_LOCK
) {
2568 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2569 DRM_DEBUG_KMS("FDI train 1 done.\n");
2578 DRM_ERROR("FDI train 1 fail!\n");
2581 reg
= FDI_TX_CTL(pipe
);
2582 temp
= I915_READ(reg
);
2583 temp
&= ~FDI_LINK_TRAIN_NONE
;
2584 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2586 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2588 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2590 I915_WRITE(reg
, temp
);
2592 reg
= FDI_RX_CTL(pipe
);
2593 temp
= I915_READ(reg
);
2594 if (HAS_PCH_CPT(dev
)) {
2595 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2596 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2598 temp
&= ~FDI_LINK_TRAIN_NONE
;
2599 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2601 I915_WRITE(reg
, temp
);
2606 for (i
= 0; i
< 4; i
++) {
2607 reg
= FDI_TX_CTL(pipe
);
2608 temp
= I915_READ(reg
);
2609 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2610 temp
|= snb_b_fdi_train_param
[i
];
2611 I915_WRITE(reg
, temp
);
2616 for (retry
= 0; retry
< 5; retry
++) {
2617 reg
= FDI_RX_IIR(pipe
);
2618 temp
= I915_READ(reg
);
2619 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2620 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2621 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2622 DRM_DEBUG_KMS("FDI train 2 done.\n");
2631 DRM_ERROR("FDI train 2 fail!\n");
2633 DRM_DEBUG_KMS("FDI train done.\n");
2636 /* Manual link training for Ivy Bridge A0 parts */
2637 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
2639 struct drm_device
*dev
= crtc
->dev
;
2640 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2641 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2642 int pipe
= intel_crtc
->pipe
;
2643 u32 reg
, temp
, i
, j
;
2645 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2647 reg
= FDI_RX_IMR(pipe
);
2648 temp
= I915_READ(reg
);
2649 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2650 temp
&= ~FDI_RX_BIT_LOCK
;
2651 I915_WRITE(reg
, temp
);
2656 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2657 I915_READ(FDI_RX_IIR(pipe
)));
2659 /* Try each vswing and preemphasis setting twice before moving on */
2660 for (j
= 0; j
< ARRAY_SIZE(snb_b_fdi_train_param
) * 2; j
++) {
2661 /* disable first in case we need to retry */
2662 reg
= FDI_TX_CTL(pipe
);
2663 temp
= I915_READ(reg
);
2664 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
2665 temp
&= ~FDI_TX_ENABLE
;
2666 I915_WRITE(reg
, temp
);
2668 reg
= FDI_RX_CTL(pipe
);
2669 temp
= I915_READ(reg
);
2670 temp
&= ~FDI_LINK_TRAIN_AUTO
;
2671 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2672 temp
&= ~FDI_RX_ENABLE
;
2673 I915_WRITE(reg
, temp
);
2675 /* enable CPU FDI TX and PCH FDI RX */
2676 reg
= FDI_TX_CTL(pipe
);
2677 temp
= I915_READ(reg
);
2678 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
2679 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2680 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
2681 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2682 temp
|= snb_b_fdi_train_param
[j
/2];
2683 temp
|= FDI_COMPOSITE_SYNC
;
2684 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2686 I915_WRITE(FDI_RX_MISC(pipe
),
2687 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
2689 reg
= FDI_RX_CTL(pipe
);
2690 temp
= I915_READ(reg
);
2691 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2692 temp
|= FDI_COMPOSITE_SYNC
;
2693 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2696 udelay(1); /* should be 0.5us */
2698 for (i
= 0; i
< 4; i
++) {
2699 reg
= FDI_RX_IIR(pipe
);
2700 temp
= I915_READ(reg
);
2701 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2703 if (temp
& FDI_RX_BIT_LOCK
||
2704 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
2705 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2706 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2710 udelay(1); /* should be 0.5us */
2713 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j
/ 2);
2718 reg
= FDI_TX_CTL(pipe
);
2719 temp
= I915_READ(reg
);
2720 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2721 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
2722 I915_WRITE(reg
, temp
);
2724 reg
= FDI_RX_CTL(pipe
);
2725 temp
= I915_READ(reg
);
2726 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2727 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2728 I915_WRITE(reg
, temp
);
2731 udelay(2); /* should be 1.5us */
2733 for (i
= 0; i
< 4; i
++) {
2734 reg
= FDI_RX_IIR(pipe
);
2735 temp
= I915_READ(reg
);
2736 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2738 if (temp
& FDI_RX_SYMBOL_LOCK
||
2739 (I915_READ(reg
) & FDI_RX_SYMBOL_LOCK
)) {
2740 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2741 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2745 udelay(2); /* should be 1.5us */
2748 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j
/ 2);
2752 DRM_DEBUG_KMS("FDI train done.\n");
2755 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
2757 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2758 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2759 int pipe
= intel_crtc
->pipe
;
2763 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2764 reg
= FDI_RX_CTL(pipe
);
2765 temp
= I915_READ(reg
);
2766 temp
&= ~(FDI_DP_PORT_WIDTH_MASK
| (0x7 << 16));
2767 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2768 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2769 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
2774 /* Switch from Rawclk to PCDclk */
2775 temp
= I915_READ(reg
);
2776 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
2781 /* Enable CPU FDI TX PLL, always on for Ironlake */
2782 reg
= FDI_TX_CTL(pipe
);
2783 temp
= I915_READ(reg
);
2784 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
2785 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
2792 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
2794 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2795 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2796 int pipe
= intel_crtc
->pipe
;
2799 /* Switch from PCDclk to Rawclk */
2800 reg
= FDI_RX_CTL(pipe
);
2801 temp
= I915_READ(reg
);
2802 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
2804 /* Disable CPU FDI TX PLL */
2805 reg
= FDI_TX_CTL(pipe
);
2806 temp
= I915_READ(reg
);
2807 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
2812 reg
= FDI_RX_CTL(pipe
);
2813 temp
= I915_READ(reg
);
2814 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
2816 /* Wait for the clocks to turn off. */
2821 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
2823 struct drm_device
*dev
= crtc
->dev
;
2824 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2825 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2826 int pipe
= intel_crtc
->pipe
;
2829 /* disable CPU FDI tx and PCH FDI rx */
2830 reg
= FDI_TX_CTL(pipe
);
2831 temp
= I915_READ(reg
);
2832 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
2835 reg
= FDI_RX_CTL(pipe
);
2836 temp
= I915_READ(reg
);
2837 temp
&= ~(0x7 << 16);
2838 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2839 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
2844 /* Ironlake workaround, disable clock pointer after downing FDI */
2845 if (HAS_PCH_IBX(dev
)) {
2846 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2849 /* still set train pattern 1 */
2850 reg
= FDI_TX_CTL(pipe
);
2851 temp
= I915_READ(reg
);
2852 temp
&= ~FDI_LINK_TRAIN_NONE
;
2853 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2854 I915_WRITE(reg
, temp
);
2856 reg
= FDI_RX_CTL(pipe
);
2857 temp
= I915_READ(reg
);
2858 if (HAS_PCH_CPT(dev
)) {
2859 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2860 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2862 temp
&= ~FDI_LINK_TRAIN_NONE
;
2863 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2865 /* BPC in FDI rx is consistent with that in PIPECONF */
2866 temp
&= ~(0x07 << 16);
2867 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2868 I915_WRITE(reg
, temp
);
2874 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
2876 struct drm_device
*dev
= crtc
->dev
;
2877 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2878 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2879 unsigned long flags
;
2882 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
2883 intel_crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
2886 spin_lock_irqsave(&dev
->event_lock
, flags
);
2887 pending
= to_intel_crtc(crtc
)->unpin_work
!= NULL
;
2888 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
2893 static void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
2895 struct drm_device
*dev
= crtc
->dev
;
2896 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2898 if (crtc
->fb
== NULL
)
2901 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
2903 wait_event(dev_priv
->pending_flip_queue
,
2904 !intel_crtc_has_pending_flip(crtc
));
2906 mutex_lock(&dev
->struct_mutex
);
2907 intel_finish_fb(crtc
->fb
);
2908 mutex_unlock(&dev
->struct_mutex
);
2911 /* Program iCLKIP clock to the desired frequency */
2912 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
2914 struct drm_device
*dev
= crtc
->dev
;
2915 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2916 int clock
= to_intel_crtc(crtc
)->config
.adjusted_mode
.clock
;
2917 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
2920 mutex_lock(&dev_priv
->dpio_lock
);
2922 /* It is necessary to ungate the pixclk gate prior to programming
2923 * the divisors, and gate it back when it is done.
2925 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
2927 /* Disable SSCCTL */
2928 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
2929 intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
) |
2933 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2934 if (clock
== 20000) {
2939 /* The iCLK virtual clock root frequency is in MHz,
2940 * but the adjusted_mode->clock in in KHz. To get the divisors,
2941 * it is necessary to divide one by another, so we
2942 * convert the virtual clock precision to KHz here for higher
2945 u32 iclk_virtual_root_freq
= 172800 * 1000;
2946 u32 iclk_pi_range
= 64;
2947 u32 desired_divisor
, msb_divisor_value
, pi_value
;
2949 desired_divisor
= (iclk_virtual_root_freq
/ clock
);
2950 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
2951 pi_value
= desired_divisor
% iclk_pi_range
;
2954 divsel
= msb_divisor_value
- 2;
2955 phaseinc
= pi_value
;
2958 /* This should not happen with any sane values */
2959 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
2960 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
2961 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
2962 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
2964 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2971 /* Program SSCDIVINTPHASE6 */
2972 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
2973 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
2974 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
2975 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
2976 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
2977 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
2978 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
2979 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
2981 /* Program SSCAUXDIV */
2982 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
2983 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2984 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
2985 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
2987 /* Enable modulator and associated divider */
2988 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
2989 temp
&= ~SBI_SSCCTL_DISABLE
;
2990 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
2992 /* Wait for initialization time */
2995 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
2997 mutex_unlock(&dev_priv
->dpio_lock
);
3000 static void ironlake_pch_transcoder_set_timings(struct intel_crtc
*crtc
,
3001 enum pipe pch_transcoder
)
3003 struct drm_device
*dev
= crtc
->base
.dev
;
3004 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3005 enum transcoder cpu_transcoder
= crtc
->config
.cpu_transcoder
;
3007 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder
),
3008 I915_READ(HTOTAL(cpu_transcoder
)));
3009 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder
),
3010 I915_READ(HBLANK(cpu_transcoder
)));
3011 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder
),
3012 I915_READ(HSYNC(cpu_transcoder
)));
3014 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder
),
3015 I915_READ(VTOTAL(cpu_transcoder
)));
3016 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder
),
3017 I915_READ(VBLANK(cpu_transcoder
)));
3018 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder
),
3019 I915_READ(VSYNC(cpu_transcoder
)));
3020 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder
),
3021 I915_READ(VSYNCSHIFT(cpu_transcoder
)));
3025 * Enable PCH resources required for PCH ports:
3027 * - FDI training & RX/TX
3028 * - update transcoder timings
3029 * - DP transcoding bits
3032 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
3034 struct drm_device
*dev
= crtc
->dev
;
3035 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3036 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3037 int pipe
= intel_crtc
->pipe
;
3040 assert_pch_transcoder_disabled(dev_priv
, pipe
);
3042 /* Write the TU size bits before fdi link training, so that error
3043 * detection works. */
3044 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
3045 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
3047 /* For PCH output, training FDI link */
3048 dev_priv
->display
.fdi_link_train(crtc
);
3050 /* We need to program the right clock selection before writing the pixel
3051 * mutliplier into the DPLL. */
3052 if (HAS_PCH_CPT(dev
)) {
3055 temp
= I915_READ(PCH_DPLL_SEL
);
3056 temp
|= TRANS_DPLL_ENABLE(pipe
);
3057 sel
= TRANS_DPLLB_SEL(pipe
);
3058 if (intel_crtc
->config
.shared_dpll
== DPLL_ID_PCH_PLL_B
)
3062 I915_WRITE(PCH_DPLL_SEL
, temp
);
3065 /* XXX: pch pll's can be enabled any time before we enable the PCH
3066 * transcoder, and we actually should do this to not upset any PCH
3067 * transcoder that already use the clock when we share it.
3069 * Note that enable_shared_dpll tries to do the right thing, but
3070 * get_shared_dpll unconditionally resets the pll - we need that to have
3071 * the right LVDS enable sequence. */
3072 ironlake_enable_shared_dpll(intel_crtc
);
3074 /* set transcoder timing, panel must allow it */
3075 assert_panel_unlocked(dev_priv
, pipe
);
3076 ironlake_pch_transcoder_set_timings(intel_crtc
, pipe
);
3078 intel_fdi_normal_train(crtc
);
3080 /* For PCH DP, enable TRANS_DP_CTL */
3081 if (HAS_PCH_CPT(dev
) &&
3082 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
3083 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3084 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
3085 reg
= TRANS_DP_CTL(pipe
);
3086 temp
= I915_READ(reg
);
3087 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
3088 TRANS_DP_SYNC_MASK
|
3090 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
3091 TRANS_DP_ENH_FRAMING
);
3092 temp
|= bpc
<< 9; /* same format but at 11:9 */
3094 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
3095 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
3096 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
3097 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
3099 switch (intel_trans_dp_port_sel(crtc
)) {
3101 temp
|= TRANS_DP_PORT_SEL_B
;
3104 temp
|= TRANS_DP_PORT_SEL_C
;
3107 temp
|= TRANS_DP_PORT_SEL_D
;
3113 I915_WRITE(reg
, temp
);
3116 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
3119 static void lpt_pch_enable(struct drm_crtc
*crtc
)
3121 struct drm_device
*dev
= crtc
->dev
;
3122 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3123 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3124 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
3126 assert_pch_transcoder_disabled(dev_priv
, TRANSCODER_A
);
3128 lpt_program_iclkip(crtc
);
3130 /* Set transcoder timing. */
3131 ironlake_pch_transcoder_set_timings(intel_crtc
, PIPE_A
);
3133 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
3136 static void intel_put_shared_dpll(struct intel_crtc
*crtc
)
3138 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
3143 if (pll
->refcount
== 0) {
3144 WARN(1, "bad %s refcount\n", pll
->name
);
3148 if (--pll
->refcount
== 0) {
3150 WARN_ON(pll
->active
);
3153 crtc
->config
.shared_dpll
= DPLL_ID_PRIVATE
;
3156 static struct intel_shared_dpll
*intel_get_shared_dpll(struct intel_crtc
*crtc
)
3158 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
3159 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
3160 enum intel_dpll_id i
;
3163 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3164 crtc
->base
.base
.id
, pll
->name
);
3165 intel_put_shared_dpll(crtc
);
3168 if (HAS_PCH_IBX(dev_priv
->dev
)) {
3169 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3170 i
= (enum intel_dpll_id
) crtc
->pipe
;
3171 pll
= &dev_priv
->shared_dplls
[i
];
3173 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3174 crtc
->base
.base
.id
, pll
->name
);
3179 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3180 pll
= &dev_priv
->shared_dplls
[i
];
3182 /* Only want to check enabled timings first */
3183 if (pll
->refcount
== 0)
3186 if (memcmp(&crtc
->config
.dpll_hw_state
, &pll
->hw_state
,
3187 sizeof(pll
->hw_state
)) == 0) {
3188 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3190 pll
->name
, pll
->refcount
, pll
->active
);
3196 /* Ok no matching timings, maybe there's a free one? */
3197 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3198 pll
= &dev_priv
->shared_dplls
[i
];
3199 if (pll
->refcount
== 0) {
3200 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3201 crtc
->base
.base
.id
, pll
->name
);
3209 crtc
->config
.shared_dpll
= i
;
3210 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll
->name
,
3211 pipe_name(crtc
->pipe
));
3213 if (pll
->active
== 0) {
3214 memcpy(&pll
->hw_state
, &crtc
->config
.dpll_hw_state
,
3215 sizeof(pll
->hw_state
));
3217 DRM_DEBUG_DRIVER("setting up %s\n", pll
->name
);
3219 assert_shared_dpll_disabled(dev_priv
, pll
);
3221 pll
->mode_set(dev_priv
, pll
);
3228 static void cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
3230 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3231 int dslreg
= PIPEDSL(pipe
);
3234 temp
= I915_READ(dslreg
);
3236 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
3237 if (wait_for(I915_READ(dslreg
) != temp
, 5))
3238 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
3242 static void ironlake_pfit_enable(struct intel_crtc
*crtc
)
3244 struct drm_device
*dev
= crtc
->base
.dev
;
3245 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3246 int pipe
= crtc
->pipe
;
3248 if (crtc
->config
.pch_pfit
.enabled
) {
3249 /* Force use of hard-coded filter coefficients
3250 * as some pre-programmed values are broken,
3253 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
3254 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
3255 PF_PIPE_SEL_IVB(pipe
));
3257 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
3258 I915_WRITE(PF_WIN_POS(pipe
), crtc
->config
.pch_pfit
.pos
);
3259 I915_WRITE(PF_WIN_SZ(pipe
), crtc
->config
.pch_pfit
.size
);
3263 static void intel_enable_planes(struct drm_crtc
*crtc
)
3265 struct drm_device
*dev
= crtc
->dev
;
3266 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
3267 struct intel_plane
*intel_plane
;
3269 list_for_each_entry(intel_plane
, &dev
->mode_config
.plane_list
, base
.head
)
3270 if (intel_plane
->pipe
== pipe
)
3271 intel_plane_restore(&intel_plane
->base
);
3274 static void intel_disable_planes(struct drm_crtc
*crtc
)
3276 struct drm_device
*dev
= crtc
->dev
;
3277 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
3278 struct intel_plane
*intel_plane
;
3280 list_for_each_entry(intel_plane
, &dev
->mode_config
.plane_list
, base
.head
)
3281 if (intel_plane
->pipe
== pipe
)
3282 intel_plane_disable(&intel_plane
->base
);
3285 static void hsw_enable_ips(struct intel_crtc
*crtc
)
3287 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
3289 if (!crtc
->config
.ips_enabled
)
3292 /* We can only enable IPS after we enable a plane and wait for a vblank.
3293 * We guarantee that the plane is enabled by calling intel_enable_ips
3294 * only after intel_enable_plane. And intel_enable_plane already waits
3295 * for a vblank, so all we need to do here is to enable the IPS bit. */
3296 assert_plane_enabled(dev_priv
, crtc
->plane
);
3297 I915_WRITE(IPS_CTL
, IPS_ENABLE
);
3300 static void hsw_disable_ips(struct intel_crtc
*crtc
)
3302 struct drm_device
*dev
= crtc
->base
.dev
;
3303 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3305 if (!crtc
->config
.ips_enabled
)
3308 assert_plane_enabled(dev_priv
, crtc
->plane
);
3309 I915_WRITE(IPS_CTL
, 0);
3310 POSTING_READ(IPS_CTL
);
3312 /* We need to wait for a vblank before we can disable the plane. */
3313 intel_wait_for_vblank(dev
, crtc
->pipe
);
3316 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3317 static void intel_crtc_load_lut(struct drm_crtc
*crtc
)
3319 struct drm_device
*dev
= crtc
->dev
;
3320 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3321 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3322 enum pipe pipe
= intel_crtc
->pipe
;
3323 int palreg
= PALETTE(pipe
);
3325 bool reenable_ips
= false;
3327 /* The clocks have to be on to load the palette. */
3328 if (!crtc
->enabled
|| !intel_crtc
->active
)
3331 if (!HAS_PCH_SPLIT(dev_priv
->dev
)) {
3332 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
))
3333 assert_dsi_pll_enabled(dev_priv
);
3335 assert_pll_enabled(dev_priv
, pipe
);
3338 /* use legacy palette for Ironlake */
3339 if (HAS_PCH_SPLIT(dev
))
3340 palreg
= LGC_PALETTE(pipe
);
3342 /* Workaround : Do not read or write the pipe palette/gamma data while
3343 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3345 if (intel_crtc
->config
.ips_enabled
&&
3346 ((I915_READ(GAMMA_MODE(pipe
)) & GAMMA_MODE_MODE_MASK
) ==
3347 GAMMA_MODE_MODE_SPLIT
)) {
3348 hsw_disable_ips(intel_crtc
);
3349 reenable_ips
= true;
3352 for (i
= 0; i
< 256; i
++) {
3353 I915_WRITE(palreg
+ 4 * i
,
3354 (intel_crtc
->lut_r
[i
] << 16) |
3355 (intel_crtc
->lut_g
[i
] << 8) |
3356 intel_crtc
->lut_b
[i
]);
3360 hsw_enable_ips(intel_crtc
);
3363 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
3365 struct drm_device
*dev
= crtc
->dev
;
3366 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3367 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3368 struct intel_encoder
*encoder
;
3369 int pipe
= intel_crtc
->pipe
;
3370 int plane
= intel_crtc
->plane
;
3372 WARN_ON(!crtc
->enabled
);
3374 if (intel_crtc
->active
)
3377 intel_crtc
->active
= true;
3379 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
3380 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, true);
3382 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3383 if (encoder
->pre_enable
)
3384 encoder
->pre_enable(encoder
);
3386 if (intel_crtc
->config
.has_pch_encoder
) {
3387 /* Note: FDI PLL enabling _must_ be done before we enable the
3388 * cpu pipes, hence this is separate from all the other fdi/pch
3390 ironlake_fdi_pll_enable(intel_crtc
);
3392 assert_fdi_tx_disabled(dev_priv
, pipe
);
3393 assert_fdi_rx_disabled(dev_priv
, pipe
);
3396 ironlake_pfit_enable(intel_crtc
);
3399 * On ILK+ LUT must be loaded before the pipe is running but with
3402 intel_crtc_load_lut(crtc
);
3404 intel_update_watermarks(crtc
);
3405 intel_enable_pipe(dev_priv
, pipe
,
3406 intel_crtc
->config
.has_pch_encoder
, false);
3407 intel_enable_plane(dev_priv
, plane
, pipe
);
3408 intel_enable_planes(crtc
);
3409 intel_crtc_update_cursor(crtc
, true);
3411 if (intel_crtc
->config
.has_pch_encoder
)
3412 ironlake_pch_enable(crtc
);
3414 mutex_lock(&dev
->struct_mutex
);
3415 intel_update_fbc(dev
);
3416 mutex_unlock(&dev
->struct_mutex
);
3418 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3419 encoder
->enable(encoder
);
3421 if (HAS_PCH_CPT(dev
))
3422 cpt_verify_modeset(dev
, intel_crtc
->pipe
);
3425 * There seems to be a race in PCH platform hw (at least on some
3426 * outputs) where an enabled pipe still completes any pageflip right
3427 * away (as if the pipe is off) instead of waiting for vblank. As soon
3428 * as the first vblank happend, everything works as expected. Hence just
3429 * wait for one vblank before returning to avoid strange things
3432 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3435 /* IPS only exists on ULT machines and is tied to pipe A. */
3436 static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc
)
3438 return HAS_IPS(crtc
->base
.dev
) && crtc
->pipe
== PIPE_A
;
3441 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
3443 struct drm_device
*dev
= crtc
->dev
;
3444 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3445 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3446 struct intel_encoder
*encoder
;
3447 int pipe
= intel_crtc
->pipe
;
3448 int plane
= intel_crtc
->plane
;
3450 WARN_ON(!crtc
->enabled
);
3452 if (intel_crtc
->active
)
3455 intel_crtc
->active
= true;
3457 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
3458 if (intel_crtc
->config
.has_pch_encoder
)
3459 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, true);
3461 if (intel_crtc
->config
.has_pch_encoder
)
3462 dev_priv
->display
.fdi_link_train(crtc
);
3464 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3465 if (encoder
->pre_enable
)
3466 encoder
->pre_enable(encoder
);
3468 intel_ddi_enable_pipe_clock(intel_crtc
);
3470 ironlake_pfit_enable(intel_crtc
);
3473 * On ILK+ LUT must be loaded before the pipe is running but with
3476 intel_crtc_load_lut(crtc
);
3478 intel_ddi_set_pipe_settings(crtc
);
3479 intel_ddi_enable_transcoder_func(crtc
);
3481 intel_update_watermarks(crtc
);
3482 intel_enable_pipe(dev_priv
, pipe
,
3483 intel_crtc
->config
.has_pch_encoder
, false);
3484 intel_enable_plane(dev_priv
, plane
, pipe
);
3485 intel_enable_planes(crtc
);
3486 intel_crtc_update_cursor(crtc
, true);
3488 hsw_enable_ips(intel_crtc
);
3490 if (intel_crtc
->config
.has_pch_encoder
)
3491 lpt_pch_enable(crtc
);
3493 mutex_lock(&dev
->struct_mutex
);
3494 intel_update_fbc(dev
);
3495 mutex_unlock(&dev
->struct_mutex
);
3497 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
3498 encoder
->enable(encoder
);
3499 intel_opregion_notify_encoder(encoder
, true);
3503 * There seems to be a race in PCH platform hw (at least on some
3504 * outputs) where an enabled pipe still completes any pageflip right
3505 * away (as if the pipe is off) instead of waiting for vblank. As soon
3506 * as the first vblank happend, everything works as expected. Hence just
3507 * wait for one vblank before returning to avoid strange things
3510 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3513 static void ironlake_pfit_disable(struct intel_crtc
*crtc
)
3515 struct drm_device
*dev
= crtc
->base
.dev
;
3516 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3517 int pipe
= crtc
->pipe
;
3519 /* To avoid upsetting the power well on haswell only disable the pfit if
3520 * it's in use. The hw state code will make sure we get this right. */
3521 if (crtc
->config
.pch_pfit
.enabled
) {
3522 I915_WRITE(PF_CTL(pipe
), 0);
3523 I915_WRITE(PF_WIN_POS(pipe
), 0);
3524 I915_WRITE(PF_WIN_SZ(pipe
), 0);
3528 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
3530 struct drm_device
*dev
= crtc
->dev
;
3531 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3532 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3533 struct intel_encoder
*encoder
;
3534 int pipe
= intel_crtc
->pipe
;
3535 int plane
= intel_crtc
->plane
;
3539 if (!intel_crtc
->active
)
3542 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3543 encoder
->disable(encoder
);
3545 intel_crtc_wait_for_pending_flips(crtc
);
3546 drm_vblank_off(dev
, pipe
);
3548 if (dev_priv
->fbc
.plane
== plane
)
3549 intel_disable_fbc(dev
);
3551 intel_crtc_update_cursor(crtc
, false);
3552 intel_disable_planes(crtc
);
3553 intel_disable_plane(dev_priv
, plane
, pipe
);
3555 if (intel_crtc
->config
.has_pch_encoder
)
3556 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, false);
3558 intel_disable_pipe(dev_priv
, pipe
);
3560 ironlake_pfit_disable(intel_crtc
);
3562 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3563 if (encoder
->post_disable
)
3564 encoder
->post_disable(encoder
);
3566 if (intel_crtc
->config
.has_pch_encoder
) {
3567 ironlake_fdi_disable(crtc
);
3569 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
3570 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, true);
3572 if (HAS_PCH_CPT(dev
)) {
3573 /* disable TRANS_DP_CTL */
3574 reg
= TRANS_DP_CTL(pipe
);
3575 temp
= I915_READ(reg
);
3576 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
|
3577 TRANS_DP_PORT_SEL_MASK
);
3578 temp
|= TRANS_DP_PORT_SEL_NONE
;
3579 I915_WRITE(reg
, temp
);
3581 /* disable DPLL_SEL */
3582 temp
= I915_READ(PCH_DPLL_SEL
);
3583 temp
&= ~(TRANS_DPLL_ENABLE(pipe
) | TRANS_DPLLB_SEL(pipe
));
3584 I915_WRITE(PCH_DPLL_SEL
, temp
);
3587 /* disable PCH DPLL */
3588 intel_disable_shared_dpll(intel_crtc
);
3590 ironlake_fdi_pll_disable(intel_crtc
);
3593 intel_crtc
->active
= false;
3594 intel_update_watermarks(crtc
);
3596 mutex_lock(&dev
->struct_mutex
);
3597 intel_update_fbc(dev
);
3598 mutex_unlock(&dev
->struct_mutex
);
3601 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
3603 struct drm_device
*dev
= crtc
->dev
;
3604 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3605 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3606 struct intel_encoder
*encoder
;
3607 int pipe
= intel_crtc
->pipe
;
3608 int plane
= intel_crtc
->plane
;
3609 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
3611 if (!intel_crtc
->active
)
3614 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
3615 intel_opregion_notify_encoder(encoder
, false);
3616 encoder
->disable(encoder
);
3619 intel_crtc_wait_for_pending_flips(crtc
);
3620 drm_vblank_off(dev
, pipe
);
3622 /* FBC must be disabled before disabling the plane on HSW. */
3623 if (dev_priv
->fbc
.plane
== plane
)
3624 intel_disable_fbc(dev
);
3626 hsw_disable_ips(intel_crtc
);
3628 intel_crtc_update_cursor(crtc
, false);
3629 intel_disable_planes(crtc
);
3630 intel_disable_plane(dev_priv
, plane
, pipe
);
3632 if (intel_crtc
->config
.has_pch_encoder
)
3633 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, false);
3634 intel_disable_pipe(dev_priv
, pipe
);
3636 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
3638 ironlake_pfit_disable(intel_crtc
);
3640 intel_ddi_disable_pipe_clock(intel_crtc
);
3642 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3643 if (encoder
->post_disable
)
3644 encoder
->post_disable(encoder
);
3646 if (intel_crtc
->config
.has_pch_encoder
) {
3647 lpt_disable_pch_transcoder(dev_priv
);
3648 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, true);
3649 intel_ddi_fdi_disable(crtc
);
3652 intel_crtc
->active
= false;
3653 intel_update_watermarks(crtc
);
3655 mutex_lock(&dev
->struct_mutex
);
3656 intel_update_fbc(dev
);
3657 mutex_unlock(&dev
->struct_mutex
);
3660 static void ironlake_crtc_off(struct drm_crtc
*crtc
)
3662 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3663 intel_put_shared_dpll(intel_crtc
);
3666 static void haswell_crtc_off(struct drm_crtc
*crtc
)
3668 intel_ddi_put_crtc_pll(crtc
);
3671 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
3673 if (!enable
&& intel_crtc
->overlay
) {
3674 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3675 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3677 mutex_lock(&dev
->struct_mutex
);
3678 dev_priv
->mm
.interruptible
= false;
3679 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
3680 dev_priv
->mm
.interruptible
= true;
3681 mutex_unlock(&dev
->struct_mutex
);
3684 /* Let userspace switch the overlay on again. In most cases userspace
3685 * has to recompute where to put it anyway.
3690 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3691 * cursor plane briefly if not already running after enabling the display
3693 * This workaround avoids occasional blank screens when self refresh is
3697 g4x_fixup_plane(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
3699 u32 cntl
= I915_READ(CURCNTR(pipe
));
3701 if ((cntl
& CURSOR_MODE
) == 0) {
3702 u32 fw_bcl_self
= I915_READ(FW_BLC_SELF
);
3704 I915_WRITE(FW_BLC_SELF
, fw_bcl_self
& ~FW_BLC_SELF_EN
);
3705 I915_WRITE(CURCNTR(pipe
), CURSOR_MODE_64_ARGB_AX
);
3706 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
3707 I915_WRITE(CURCNTR(pipe
), cntl
);
3708 I915_WRITE(CURBASE(pipe
), I915_READ(CURBASE(pipe
)));
3709 I915_WRITE(FW_BLC_SELF
, fw_bcl_self
);
3713 static void i9xx_pfit_enable(struct intel_crtc
*crtc
)
3715 struct drm_device
*dev
= crtc
->base
.dev
;
3716 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3717 struct intel_crtc_config
*pipe_config
= &crtc
->config
;
3719 if (!crtc
->config
.gmch_pfit
.control
)
3723 * The panel fitter should only be adjusted whilst the pipe is disabled,
3724 * according to register description and PRM.
3726 WARN_ON(I915_READ(PFIT_CONTROL
) & PFIT_ENABLE
);
3727 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
3729 I915_WRITE(PFIT_PGM_RATIOS
, pipe_config
->gmch_pfit
.pgm_ratios
);
3730 I915_WRITE(PFIT_CONTROL
, pipe_config
->gmch_pfit
.control
);
3732 /* Border color in case we don't scale up to the full screen. Black by
3733 * default, change to something else for debugging. */
3734 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
3737 static void valleyview_crtc_enable(struct drm_crtc
*crtc
)
3739 struct drm_device
*dev
= crtc
->dev
;
3740 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3741 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3742 struct intel_encoder
*encoder
;
3743 int pipe
= intel_crtc
->pipe
;
3744 int plane
= intel_crtc
->plane
;
3747 WARN_ON(!crtc
->enabled
);
3749 if (intel_crtc
->active
)
3752 intel_crtc
->active
= true;
3754 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3755 if (encoder
->pre_pll_enable
)
3756 encoder
->pre_pll_enable(encoder
);
3758 is_dsi
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
);
3761 vlv_enable_pll(intel_crtc
);
3763 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3764 if (encoder
->pre_enable
)
3765 encoder
->pre_enable(encoder
);
3767 i9xx_pfit_enable(intel_crtc
);
3769 intel_crtc_load_lut(crtc
);
3771 intel_update_watermarks(crtc
);
3772 intel_enable_pipe(dev_priv
, pipe
, false, is_dsi
);
3773 intel_enable_plane(dev_priv
, plane
, pipe
);
3774 intel_enable_planes(crtc
);
3775 intel_crtc_update_cursor(crtc
, true);
3777 intel_update_fbc(dev
);
3779 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3780 encoder
->enable(encoder
);
3783 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
3785 struct drm_device
*dev
= crtc
->dev
;
3786 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3787 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3788 struct intel_encoder
*encoder
;
3789 int pipe
= intel_crtc
->pipe
;
3790 int plane
= intel_crtc
->plane
;
3792 WARN_ON(!crtc
->enabled
);
3794 if (intel_crtc
->active
)
3797 intel_crtc
->active
= true;
3799 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3800 if (encoder
->pre_enable
)
3801 encoder
->pre_enable(encoder
);
3803 i9xx_enable_pll(intel_crtc
);
3805 i9xx_pfit_enable(intel_crtc
);
3807 intel_crtc_load_lut(crtc
);
3809 intel_update_watermarks(crtc
);
3810 intel_enable_pipe(dev_priv
, pipe
, false, false);
3811 intel_enable_plane(dev_priv
, plane
, pipe
);
3812 intel_enable_planes(crtc
);
3813 /* The fixup needs to happen before cursor is enabled */
3815 g4x_fixup_plane(dev_priv
, pipe
);
3816 intel_crtc_update_cursor(crtc
, true);
3818 /* Give the overlay scaler a chance to enable if it's on this pipe */
3819 intel_crtc_dpms_overlay(intel_crtc
, true);
3821 intel_update_fbc(dev
);
3823 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3824 encoder
->enable(encoder
);
3827 static void i9xx_pfit_disable(struct intel_crtc
*crtc
)
3829 struct drm_device
*dev
= crtc
->base
.dev
;
3830 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3832 if (!crtc
->config
.gmch_pfit
.control
)
3835 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
3837 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3838 I915_READ(PFIT_CONTROL
));
3839 I915_WRITE(PFIT_CONTROL
, 0);
3842 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
3844 struct drm_device
*dev
= crtc
->dev
;
3845 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3846 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3847 struct intel_encoder
*encoder
;
3848 int pipe
= intel_crtc
->pipe
;
3849 int plane
= intel_crtc
->plane
;
3851 if (!intel_crtc
->active
)
3854 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3855 encoder
->disable(encoder
);
3857 /* Give the overlay scaler a chance to disable if it's on this pipe */
3858 intel_crtc_wait_for_pending_flips(crtc
);
3859 drm_vblank_off(dev
, pipe
);
3861 if (dev_priv
->fbc
.plane
== plane
)
3862 intel_disable_fbc(dev
);
3864 intel_crtc_dpms_overlay(intel_crtc
, false);
3865 intel_crtc_update_cursor(crtc
, false);
3866 intel_disable_planes(crtc
);
3867 intel_disable_plane(dev_priv
, plane
, pipe
);
3869 intel_disable_pipe(dev_priv
, pipe
);
3871 i9xx_pfit_disable(intel_crtc
);
3873 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3874 if (encoder
->post_disable
)
3875 encoder
->post_disable(encoder
);
3877 if (!intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
))
3878 i9xx_disable_pll(dev_priv
, pipe
);
3880 intel_crtc
->active
= false;
3881 intel_update_watermarks(crtc
);
3883 intel_update_fbc(dev
);
3886 static void i9xx_crtc_off(struct drm_crtc
*crtc
)
3890 static void intel_crtc_update_sarea(struct drm_crtc
*crtc
,
3893 struct drm_device
*dev
= crtc
->dev
;
3894 struct drm_i915_master_private
*master_priv
;
3895 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3896 int pipe
= intel_crtc
->pipe
;
3898 if (!dev
->primary
->master
)
3901 master_priv
= dev
->primary
->master
->driver_priv
;
3902 if (!master_priv
->sarea_priv
)
3907 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3908 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3911 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3912 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3915 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe
));
3921 * Sets the power management mode of the pipe and plane.
3923 void intel_crtc_update_dpms(struct drm_crtc
*crtc
)
3925 struct drm_device
*dev
= crtc
->dev
;
3926 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3927 struct intel_encoder
*intel_encoder
;
3928 bool enable
= false;
3930 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
3931 enable
|= intel_encoder
->connectors_active
;
3934 dev_priv
->display
.crtc_enable(crtc
);
3936 dev_priv
->display
.crtc_disable(crtc
);
3938 intel_crtc_update_sarea(crtc
, enable
);
3941 static void intel_crtc_disable(struct drm_crtc
*crtc
)
3943 struct drm_device
*dev
= crtc
->dev
;
3944 struct drm_connector
*connector
;
3945 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3946 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3948 /* crtc should still be enabled when we disable it. */
3949 WARN_ON(!crtc
->enabled
);
3951 dev_priv
->display
.crtc_disable(crtc
);
3952 intel_crtc
->eld_vld
= false;
3953 intel_crtc_update_sarea(crtc
, false);
3954 dev_priv
->display
.off(crtc
);
3956 assert_plane_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->plane
);
3957 assert_cursor_disabled(dev_priv
, to_intel_crtc(crtc
)->pipe
);
3958 assert_pipe_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->pipe
);
3961 mutex_lock(&dev
->struct_mutex
);
3962 intel_unpin_fb_obj(to_intel_framebuffer(crtc
->fb
)->obj
);
3963 mutex_unlock(&dev
->struct_mutex
);
3967 /* Update computed state. */
3968 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
3969 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
3972 if (connector
->encoder
->crtc
!= crtc
)
3975 connector
->dpms
= DRM_MODE_DPMS_OFF
;
3976 to_intel_encoder(connector
->encoder
)->connectors_active
= false;
3980 void intel_encoder_destroy(struct drm_encoder
*encoder
)
3982 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
3984 drm_encoder_cleanup(encoder
);
3985 kfree(intel_encoder
);
3988 /* Simple dpms helper for encoders with just one connector, no cloning and only
3989 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3990 * state of the entire output pipe. */
3991 static void intel_encoder_dpms(struct intel_encoder
*encoder
, int mode
)
3993 if (mode
== DRM_MODE_DPMS_ON
) {
3994 encoder
->connectors_active
= true;
3996 intel_crtc_update_dpms(encoder
->base
.crtc
);
3998 encoder
->connectors_active
= false;
4000 intel_crtc_update_dpms(encoder
->base
.crtc
);
4004 /* Cross check the actual hw state with our own modeset state tracking (and it's
4005 * internal consistency). */
4006 static void intel_connector_check_state(struct intel_connector
*connector
)
4008 if (connector
->get_hw_state(connector
)) {
4009 struct intel_encoder
*encoder
= connector
->encoder
;
4010 struct drm_crtc
*crtc
;
4011 bool encoder_enabled
;
4014 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4015 connector
->base
.base
.id
,
4016 drm_get_connector_name(&connector
->base
));
4018 WARN(connector
->base
.dpms
== DRM_MODE_DPMS_OFF
,
4019 "wrong connector dpms state\n");
4020 WARN(connector
->base
.encoder
!= &encoder
->base
,
4021 "active connector not linked to encoder\n");
4022 WARN(!encoder
->connectors_active
,
4023 "encoder->connectors_active not set\n");
4025 encoder_enabled
= encoder
->get_hw_state(encoder
, &pipe
);
4026 WARN(!encoder_enabled
, "encoder not enabled\n");
4027 if (WARN_ON(!encoder
->base
.crtc
))
4030 crtc
= encoder
->base
.crtc
;
4032 WARN(!crtc
->enabled
, "crtc not enabled\n");
4033 WARN(!to_intel_crtc(crtc
)->active
, "crtc not active\n");
4034 WARN(pipe
!= to_intel_crtc(crtc
)->pipe
,
4035 "encoder active on the wrong pipe\n");
4039 /* Even simpler default implementation, if there's really no special case to
4041 void intel_connector_dpms(struct drm_connector
*connector
, int mode
)
4043 struct intel_encoder
*encoder
= intel_attached_encoder(connector
);
4045 /* All the simple cases only support two dpms states. */
4046 if (mode
!= DRM_MODE_DPMS_ON
)
4047 mode
= DRM_MODE_DPMS_OFF
;
4049 if (mode
== connector
->dpms
)
4052 connector
->dpms
= mode
;
4054 /* Only need to change hw state when actually enabled */
4055 if (encoder
->base
.crtc
)
4056 intel_encoder_dpms(encoder
, mode
);
4058 WARN_ON(encoder
->connectors_active
!= false);
4060 intel_modeset_check_state(connector
->dev
);
4063 /* Simple connector->get_hw_state implementation for encoders that support only
4064 * one connector and no cloning and hence the encoder state determines the state
4065 * of the connector. */
4066 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
4069 struct intel_encoder
*encoder
= connector
->encoder
;
4071 return encoder
->get_hw_state(encoder
, &pipe
);
4074 static bool ironlake_check_fdi_lanes(struct drm_device
*dev
, enum pipe pipe
,
4075 struct intel_crtc_config
*pipe_config
)
4077 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4078 struct intel_crtc
*pipe_B_crtc
=
4079 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
4081 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4082 pipe_name(pipe
), pipe_config
->fdi_lanes
);
4083 if (pipe_config
->fdi_lanes
> 4) {
4084 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4085 pipe_name(pipe
), pipe_config
->fdi_lanes
);
4089 if (IS_HASWELL(dev
)) {
4090 if (pipe_config
->fdi_lanes
> 2) {
4091 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4092 pipe_config
->fdi_lanes
);
4099 if (INTEL_INFO(dev
)->num_pipes
== 2)
4102 /* Ivybridge 3 pipe is really complicated */
4107 if (dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]->enabled
&&
4108 pipe_config
->fdi_lanes
> 2) {
4109 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4110 pipe_name(pipe
), pipe_config
->fdi_lanes
);
4115 if (!pipe_has_enabled_pch(pipe_B_crtc
) ||
4116 pipe_B_crtc
->config
.fdi_lanes
<= 2) {
4117 if (pipe_config
->fdi_lanes
> 2) {
4118 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4119 pipe_name(pipe
), pipe_config
->fdi_lanes
);
4123 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4133 static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc
,
4134 struct intel_crtc_config
*pipe_config
)
4136 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4137 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
4138 int lane
, link_bw
, fdi_dotclock
;
4139 bool setup_ok
, needs_recompute
= false;
4142 /* FDI is a binary signal running at ~2.7GHz, encoding
4143 * each output octet as 10 bits. The actual frequency
4144 * is stored as a divider into a 100MHz clock, and the
4145 * mode pixel clock is stored in units of 1KHz.
4146 * Hence the bw of each lane in terms of the mode signal
4149 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
4151 fdi_dotclock
= adjusted_mode
->clock
;
4153 lane
= ironlake_get_lanes_required(fdi_dotclock
, link_bw
,
4154 pipe_config
->pipe_bpp
);
4156 pipe_config
->fdi_lanes
= lane
;
4158 intel_link_compute_m_n(pipe_config
->pipe_bpp
, lane
, fdi_dotclock
,
4159 link_bw
, &pipe_config
->fdi_m_n
);
4161 setup_ok
= ironlake_check_fdi_lanes(intel_crtc
->base
.dev
,
4162 intel_crtc
->pipe
, pipe_config
);
4163 if (!setup_ok
&& pipe_config
->pipe_bpp
> 6*3) {
4164 pipe_config
->pipe_bpp
-= 2*3;
4165 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4166 pipe_config
->pipe_bpp
);
4167 needs_recompute
= true;
4168 pipe_config
->bw_constrained
= true;
4173 if (needs_recompute
)
4176 return setup_ok
? 0 : -EINVAL
;
4179 static void hsw_compute_ips_config(struct intel_crtc
*crtc
,
4180 struct intel_crtc_config
*pipe_config
)
4182 pipe_config
->ips_enabled
= i915_enable_ips
&&
4183 hsw_crtc_supports_ips(crtc
) &&
4184 pipe_config
->pipe_bpp
<= 24;
4187 static int intel_crtc_compute_config(struct intel_crtc
*crtc
,
4188 struct intel_crtc_config
*pipe_config
)
4190 struct drm_device
*dev
= crtc
->base
.dev
;
4191 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
4193 /* FIXME should check pixel clock limits on all platforms */
4194 if (INTEL_INFO(dev
)->gen
< 4) {
4195 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4197 dev_priv
->display
.get_display_clock_speed(dev
);
4200 * Enable pixel doubling when the dot clock
4201 * is > 90% of the (display) core speed.
4203 * GDG double wide on either pipe,
4204 * otherwise pipe A only.
4206 if ((crtc
->pipe
== PIPE_A
|| IS_I915G(dev
)) &&
4207 adjusted_mode
->clock
> clock_limit
* 9 / 10) {
4209 pipe_config
->double_wide
= true;
4212 if (adjusted_mode
->clock
> clock_limit
* 9 / 10)
4217 * Pipe horizontal size must be even in:
4219 * - LVDS dual channel mode
4220 * - Double wide pipe
4222 if ((intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4223 intel_is_dual_link_lvds(dev
)) || pipe_config
->double_wide
)
4224 pipe_config
->pipe_src_w
&= ~1;
4226 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4227 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4229 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
4230 adjusted_mode
->hsync_start
== adjusted_mode
->hdisplay
)
4233 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) && pipe_config
->pipe_bpp
> 10*3) {
4234 pipe_config
->pipe_bpp
= 10*3; /* 12bpc is gen5+ */
4235 } else if (INTEL_INFO(dev
)->gen
<= 4 && pipe_config
->pipe_bpp
> 8*3) {
4236 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4238 pipe_config
->pipe_bpp
= 8*3;
4242 hsw_compute_ips_config(crtc
, pipe_config
);
4244 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4245 * clock survives for now. */
4246 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
4247 pipe_config
->shared_dpll
= crtc
->config
.shared_dpll
;
4249 if (pipe_config
->has_pch_encoder
)
4250 return ironlake_fdi_compute_config(crtc
, pipe_config
);
4255 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
4257 return 400000; /* FIXME */
4260 static int i945_get_display_clock_speed(struct drm_device
*dev
)
4265 static int i915_get_display_clock_speed(struct drm_device
*dev
)
4270 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
4275 static int pnv_get_display_clock_speed(struct drm_device
*dev
)
4279 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
4281 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
4282 case GC_DISPLAY_CLOCK_267_MHZ_PNV
:
4284 case GC_DISPLAY_CLOCK_333_MHZ_PNV
:
4286 case GC_DISPLAY_CLOCK_444_MHZ_PNV
:
4288 case GC_DISPLAY_CLOCK_200_MHZ_PNV
:
4291 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc
);
4292 case GC_DISPLAY_CLOCK_133_MHZ_PNV
:
4294 case GC_DISPLAY_CLOCK_167_MHZ_PNV
:
4299 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
4303 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
4305 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
4308 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
4309 case GC_DISPLAY_CLOCK_333_MHZ
:
4312 case GC_DISPLAY_CLOCK_190_200_MHZ
:
4318 static int i865_get_display_clock_speed(struct drm_device
*dev
)
4323 static int i855_get_display_clock_speed(struct drm_device
*dev
)
4326 /* Assume that the hardware is in the high speed state. This
4327 * should be the default.
4329 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
4330 case GC_CLOCK_133_200
:
4331 case GC_CLOCK_100_200
:
4333 case GC_CLOCK_166_250
:
4335 case GC_CLOCK_100_133
:
4339 /* Shouldn't happen */
4343 static int i830_get_display_clock_speed(struct drm_device
*dev
)
4349 intel_reduce_m_n_ratio(uint32_t *num
, uint32_t *den
)
4351 while (*num
> DATA_LINK_M_N_MASK
||
4352 *den
> DATA_LINK_M_N_MASK
) {
4358 static void compute_m_n(unsigned int m
, unsigned int n
,
4359 uint32_t *ret_m
, uint32_t *ret_n
)
4361 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
4362 *ret_m
= div_u64((uint64_t) m
* *ret_n
, n
);
4363 intel_reduce_m_n_ratio(ret_m
, ret_n
);
4367 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
4368 int pixel_clock
, int link_clock
,
4369 struct intel_link_m_n
*m_n
)
4373 compute_m_n(bits_per_pixel
* pixel_clock
,
4374 link_clock
* nlanes
* 8,
4375 &m_n
->gmch_m
, &m_n
->gmch_n
);
4377 compute_m_n(pixel_clock
, link_clock
,
4378 &m_n
->link_m
, &m_n
->link_n
);
4381 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
4383 if (i915_panel_use_ssc
>= 0)
4384 return i915_panel_use_ssc
!= 0;
4385 return dev_priv
->vbt
.lvds_use_ssc
4386 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
4389 static int i9xx_get_refclk(struct drm_crtc
*crtc
, int num_connectors
)
4391 struct drm_device
*dev
= crtc
->dev
;
4392 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4395 if (IS_VALLEYVIEW(dev
)) {
4397 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
4398 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
4399 refclk
= dev_priv
->vbt
.lvds_ssc_freq
* 1000;
4400 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4402 } else if (!IS_GEN2(dev
)) {
4411 static uint32_t pnv_dpll_compute_fp(struct dpll
*dpll
)
4413 return (1 << dpll
->n
) << 16 | dpll
->m2
;
4416 static uint32_t i9xx_dpll_compute_fp(struct dpll
*dpll
)
4418 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
4421 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
4422 intel_clock_t
*reduced_clock
)
4424 struct drm_device
*dev
= crtc
->base
.dev
;
4425 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4426 int pipe
= crtc
->pipe
;
4429 if (IS_PINEVIEW(dev
)) {
4430 fp
= pnv_dpll_compute_fp(&crtc
->config
.dpll
);
4432 fp2
= pnv_dpll_compute_fp(reduced_clock
);
4434 fp
= i9xx_dpll_compute_fp(&crtc
->config
.dpll
);
4436 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
4439 I915_WRITE(FP0(pipe
), fp
);
4440 crtc
->config
.dpll_hw_state
.fp0
= fp
;
4442 crtc
->lowfreq_avail
= false;
4443 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4444 reduced_clock
&& i915_powersave
) {
4445 I915_WRITE(FP1(pipe
), fp2
);
4446 crtc
->config
.dpll_hw_state
.fp1
= fp2
;
4447 crtc
->lowfreq_avail
= true;
4449 I915_WRITE(FP1(pipe
), fp
);
4450 crtc
->config
.dpll_hw_state
.fp1
= fp
;
4454 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
, enum pipe
4460 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4461 * and set it to a reasonable value instead.
4463 reg_val
= vlv_dpio_read(dev_priv
, pipe
, DPIO_IREF(1));
4464 reg_val
&= 0xffffff00;
4465 reg_val
|= 0x00000030;
4466 vlv_dpio_write(dev_priv
, pipe
, DPIO_IREF(1), reg_val
);
4468 reg_val
= vlv_dpio_read(dev_priv
, pipe
, DPIO_CALIBRATION
);
4469 reg_val
&= 0x8cffffff;
4470 reg_val
= 0x8c000000;
4471 vlv_dpio_write(dev_priv
, pipe
, DPIO_CALIBRATION
, reg_val
);
4473 reg_val
= vlv_dpio_read(dev_priv
, pipe
, DPIO_IREF(1));
4474 reg_val
&= 0xffffff00;
4475 vlv_dpio_write(dev_priv
, pipe
, DPIO_IREF(1), reg_val
);
4477 reg_val
= vlv_dpio_read(dev_priv
, pipe
, DPIO_CALIBRATION
);
4478 reg_val
&= 0x00ffffff;
4479 reg_val
|= 0xb0000000;
4480 vlv_dpio_write(dev_priv
, pipe
, DPIO_CALIBRATION
, reg_val
);
4483 static void intel_pch_transcoder_set_m_n(struct intel_crtc
*crtc
,
4484 struct intel_link_m_n
*m_n
)
4486 struct drm_device
*dev
= crtc
->base
.dev
;
4487 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4488 int pipe
= crtc
->pipe
;
4490 I915_WRITE(PCH_TRANS_DATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
4491 I915_WRITE(PCH_TRANS_DATA_N1(pipe
), m_n
->gmch_n
);
4492 I915_WRITE(PCH_TRANS_LINK_M1(pipe
), m_n
->link_m
);
4493 I915_WRITE(PCH_TRANS_LINK_N1(pipe
), m_n
->link_n
);
4496 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
4497 struct intel_link_m_n
*m_n
)
4499 struct drm_device
*dev
= crtc
->base
.dev
;
4500 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4501 int pipe
= crtc
->pipe
;
4502 enum transcoder transcoder
= crtc
->config
.cpu_transcoder
;
4504 if (INTEL_INFO(dev
)->gen
>= 5) {
4505 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
4506 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
4507 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
4508 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
4510 I915_WRITE(PIPE_DATA_M_G4X(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
4511 I915_WRITE(PIPE_DATA_N_G4X(pipe
), m_n
->gmch_n
);
4512 I915_WRITE(PIPE_LINK_M_G4X(pipe
), m_n
->link_m
);
4513 I915_WRITE(PIPE_LINK_N_G4X(pipe
), m_n
->link_n
);
4517 static void intel_dp_set_m_n(struct intel_crtc
*crtc
)
4519 if (crtc
->config
.has_pch_encoder
)
4520 intel_pch_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
);
4522 intel_cpu_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
);
4525 static void vlv_update_pll(struct intel_crtc
*crtc
)
4527 struct drm_device
*dev
= crtc
->base
.dev
;
4528 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4529 int pipe
= crtc
->pipe
;
4531 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
4532 u32 coreclk
, reg_val
, dpll_md
;
4534 mutex_lock(&dev_priv
->dpio_lock
);
4536 bestn
= crtc
->config
.dpll
.n
;
4537 bestm1
= crtc
->config
.dpll
.m1
;
4538 bestm2
= crtc
->config
.dpll
.m2
;
4539 bestp1
= crtc
->config
.dpll
.p1
;
4540 bestp2
= crtc
->config
.dpll
.p2
;
4542 /* See eDP HDMI DPIO driver vbios notes doc */
4544 /* PLL B needs special handling */
4546 vlv_pllb_recal_opamp(dev_priv
, pipe
);
4548 /* Set up Tx target for periodic Rcomp update */
4549 vlv_dpio_write(dev_priv
, pipe
, DPIO_IREF_BCAST
, 0x0100000f);
4551 /* Disable target IRef on PLL */
4552 reg_val
= vlv_dpio_read(dev_priv
, pipe
, DPIO_IREF_CTL(pipe
));
4553 reg_val
&= 0x00ffffff;
4554 vlv_dpio_write(dev_priv
, pipe
, DPIO_IREF_CTL(pipe
), reg_val
);
4556 /* Disable fast lock */
4557 vlv_dpio_write(dev_priv
, pipe
, DPIO_FASTCLK_DISABLE
, 0x610);
4559 /* Set idtafcrecal before PLL is enabled */
4560 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
4561 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
4562 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
4563 mdiv
|= (1 << DPIO_K_SHIFT
);
4566 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4567 * but we don't support that).
4568 * Note: don't use the DAC post divider as it seems unstable.
4570 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
4571 vlv_dpio_write(dev_priv
, pipe
, DPIO_DIV(pipe
), mdiv
);
4573 mdiv
|= DPIO_ENABLE_CALIBRATION
;
4574 vlv_dpio_write(dev_priv
, pipe
, DPIO_DIV(pipe
), mdiv
);
4576 /* Set HBR and RBR LPF coefficients */
4577 if (crtc
->config
.port_clock
== 162000 ||
4578 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_ANALOG
) ||
4579 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
))
4580 vlv_dpio_write(dev_priv
, pipe
, DPIO_LPF_COEFF(pipe
),
4583 vlv_dpio_write(dev_priv
, pipe
, DPIO_LPF_COEFF(pipe
),
4586 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
) ||
4587 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
)) {
4588 /* Use SSC source */
4590 vlv_dpio_write(dev_priv
, pipe
, DPIO_REFSFR(pipe
),
4593 vlv_dpio_write(dev_priv
, pipe
, DPIO_REFSFR(pipe
),
4595 } else { /* HDMI or VGA */
4596 /* Use bend source */
4598 vlv_dpio_write(dev_priv
, pipe
, DPIO_REFSFR(pipe
),
4601 vlv_dpio_write(dev_priv
, pipe
, DPIO_REFSFR(pipe
),
4605 coreclk
= vlv_dpio_read(dev_priv
, pipe
, DPIO_CORE_CLK(pipe
));
4606 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
4607 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
) ||
4608 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
))
4609 coreclk
|= 0x01000000;
4610 vlv_dpio_write(dev_priv
, pipe
, DPIO_CORE_CLK(pipe
), coreclk
);
4612 vlv_dpio_write(dev_priv
, pipe
, DPIO_PLL_CML(pipe
), 0x87871000);
4614 /* Enable DPIO clock input */
4615 dpll
= DPLL_EXT_BUFFER_ENABLE_VLV
| DPLL_REFA_CLK_ENABLE_VLV
|
4616 DPLL_VGA_MODE_DIS
| DPLL_INTEGRATED_CLOCK_VLV
;
4618 dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
4620 dpll
|= DPLL_VCO_ENABLE
;
4621 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
4623 dpll_md
= (crtc
->config
.pixel_multiplier
- 1)
4624 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4625 crtc
->config
.dpll_hw_state
.dpll_md
= dpll_md
;
4627 if (crtc
->config
.has_dp_encoder
)
4628 intel_dp_set_m_n(crtc
);
4630 mutex_unlock(&dev_priv
->dpio_lock
);
4633 static void i9xx_update_pll(struct intel_crtc
*crtc
,
4634 intel_clock_t
*reduced_clock
,
4637 struct drm_device
*dev
= crtc
->base
.dev
;
4638 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4641 struct dpll
*clock
= &crtc
->config
.dpll
;
4643 i9xx_update_pll_dividers(crtc
, reduced_clock
);
4645 is_sdvo
= intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_SDVO
) ||
4646 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
);
4648 dpll
= DPLL_VGA_MODE_DIS
;
4650 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
))
4651 dpll
|= DPLLB_MODE_LVDS
;
4653 dpll
|= DPLLB_MODE_DAC_SERIAL
;
4655 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
4656 dpll
|= (crtc
->config
.pixel_multiplier
- 1)
4657 << SDVO_MULTIPLIER_SHIFT_HIRES
;
4661 dpll
|= DPLL_SDVO_HIGH_SPEED
;
4663 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
))
4664 dpll
|= DPLL_SDVO_HIGH_SPEED
;
4666 /* compute bitmask from p1 value */
4667 if (IS_PINEVIEW(dev
))
4668 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
4670 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4671 if (IS_G4X(dev
) && reduced_clock
)
4672 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
4674 switch (clock
->p2
) {
4676 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
4679 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
4682 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
4685 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
4688 if (INTEL_INFO(dev
)->gen
>= 4)
4689 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
4691 if (crtc
->config
.sdvo_tv_clock
)
4692 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
4693 else if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4694 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4695 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4697 dpll
|= PLL_REF_INPUT_DREFCLK
;
4699 dpll
|= DPLL_VCO_ENABLE
;
4700 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
4702 if (INTEL_INFO(dev
)->gen
>= 4) {
4703 u32 dpll_md
= (crtc
->config
.pixel_multiplier
- 1)
4704 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4705 crtc
->config
.dpll_hw_state
.dpll_md
= dpll_md
;
4708 if (crtc
->config
.has_dp_encoder
)
4709 intel_dp_set_m_n(crtc
);
4712 static void i8xx_update_pll(struct intel_crtc
*crtc
,
4713 intel_clock_t
*reduced_clock
,
4716 struct drm_device
*dev
= crtc
->base
.dev
;
4717 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4719 struct dpll
*clock
= &crtc
->config
.dpll
;
4721 i9xx_update_pll_dividers(crtc
, reduced_clock
);
4723 dpll
= DPLL_VGA_MODE_DIS
;
4725 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
)) {
4726 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4729 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
4731 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4733 dpll
|= PLL_P2_DIVIDE_BY_4
;
4736 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DVO
))
4737 dpll
|= DPLL_DVO_2X_MODE
;
4739 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4740 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4741 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4743 dpll
|= PLL_REF_INPUT_DREFCLK
;
4745 dpll
|= DPLL_VCO_ENABLE
;
4746 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
4749 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
)
4751 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4752 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4753 enum pipe pipe
= intel_crtc
->pipe
;
4754 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
4755 struct drm_display_mode
*adjusted_mode
=
4756 &intel_crtc
->config
.adjusted_mode
;
4757 uint32_t vsyncshift
, crtc_vtotal
, crtc_vblank_end
;
4759 /* We need to be careful not to changed the adjusted mode, for otherwise
4760 * the hw state checker will get angry at the mismatch. */
4761 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
4762 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
4764 if (!IS_GEN2(dev
) && adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
4765 /* the chip adds 2 halflines automatically */
4767 crtc_vblank_end
-= 1;
4768 vsyncshift
= adjusted_mode
->crtc_hsync_start
4769 - adjusted_mode
->crtc_htotal
/ 2;
4774 if (INTEL_INFO(dev
)->gen
> 3)
4775 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
4777 I915_WRITE(HTOTAL(cpu_transcoder
),
4778 (adjusted_mode
->crtc_hdisplay
- 1) |
4779 ((adjusted_mode
->crtc_htotal
- 1) << 16));
4780 I915_WRITE(HBLANK(cpu_transcoder
),
4781 (adjusted_mode
->crtc_hblank_start
- 1) |
4782 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
4783 I915_WRITE(HSYNC(cpu_transcoder
),
4784 (adjusted_mode
->crtc_hsync_start
- 1) |
4785 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
4787 I915_WRITE(VTOTAL(cpu_transcoder
),
4788 (adjusted_mode
->crtc_vdisplay
- 1) |
4789 ((crtc_vtotal
- 1) << 16));
4790 I915_WRITE(VBLANK(cpu_transcoder
),
4791 (adjusted_mode
->crtc_vblank_start
- 1) |
4792 ((crtc_vblank_end
- 1) << 16));
4793 I915_WRITE(VSYNC(cpu_transcoder
),
4794 (adjusted_mode
->crtc_vsync_start
- 1) |
4795 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
4797 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4798 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4799 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4801 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
4802 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
4803 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
4805 /* pipesrc controls the size that is scaled from, which should
4806 * always be the user's requested size.
4808 I915_WRITE(PIPESRC(pipe
),
4809 ((intel_crtc
->config
.pipe_src_w
- 1) << 16) |
4810 (intel_crtc
->config
.pipe_src_h
- 1));
4813 static void intel_get_pipe_timings(struct intel_crtc
*crtc
,
4814 struct intel_crtc_config
*pipe_config
)
4816 struct drm_device
*dev
= crtc
->base
.dev
;
4817 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4818 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
4821 tmp
= I915_READ(HTOTAL(cpu_transcoder
));
4822 pipe_config
->adjusted_mode
.crtc_hdisplay
= (tmp
& 0xffff) + 1;
4823 pipe_config
->adjusted_mode
.crtc_htotal
= ((tmp
>> 16) & 0xffff) + 1;
4824 tmp
= I915_READ(HBLANK(cpu_transcoder
));
4825 pipe_config
->adjusted_mode
.crtc_hblank_start
= (tmp
& 0xffff) + 1;
4826 pipe_config
->adjusted_mode
.crtc_hblank_end
= ((tmp
>> 16) & 0xffff) + 1;
4827 tmp
= I915_READ(HSYNC(cpu_transcoder
));
4828 pipe_config
->adjusted_mode
.crtc_hsync_start
= (tmp
& 0xffff) + 1;
4829 pipe_config
->adjusted_mode
.crtc_hsync_end
= ((tmp
>> 16) & 0xffff) + 1;
4831 tmp
= I915_READ(VTOTAL(cpu_transcoder
));
4832 pipe_config
->adjusted_mode
.crtc_vdisplay
= (tmp
& 0xffff) + 1;
4833 pipe_config
->adjusted_mode
.crtc_vtotal
= ((tmp
>> 16) & 0xffff) + 1;
4834 tmp
= I915_READ(VBLANK(cpu_transcoder
));
4835 pipe_config
->adjusted_mode
.crtc_vblank_start
= (tmp
& 0xffff) + 1;
4836 pipe_config
->adjusted_mode
.crtc_vblank_end
= ((tmp
>> 16) & 0xffff) + 1;
4837 tmp
= I915_READ(VSYNC(cpu_transcoder
));
4838 pipe_config
->adjusted_mode
.crtc_vsync_start
= (tmp
& 0xffff) + 1;
4839 pipe_config
->adjusted_mode
.crtc_vsync_end
= ((tmp
>> 16) & 0xffff) + 1;
4841 if (I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_INTERLACE_MASK
) {
4842 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
4843 pipe_config
->adjusted_mode
.crtc_vtotal
+= 1;
4844 pipe_config
->adjusted_mode
.crtc_vblank_end
+= 1;
4847 tmp
= I915_READ(PIPESRC(crtc
->pipe
));
4848 pipe_config
->pipe_src_h
= (tmp
& 0xffff) + 1;
4849 pipe_config
->pipe_src_w
= ((tmp
>> 16) & 0xffff) + 1;
4851 pipe_config
->requested_mode
.vdisplay
= pipe_config
->pipe_src_h
;
4852 pipe_config
->requested_mode
.hdisplay
= pipe_config
->pipe_src_w
;
4855 static void intel_crtc_mode_from_pipe_config(struct intel_crtc
*intel_crtc
,
4856 struct intel_crtc_config
*pipe_config
)
4858 struct drm_crtc
*crtc
= &intel_crtc
->base
;
4860 crtc
->mode
.hdisplay
= pipe_config
->adjusted_mode
.crtc_hdisplay
;
4861 crtc
->mode
.htotal
= pipe_config
->adjusted_mode
.crtc_htotal
;
4862 crtc
->mode
.hsync_start
= pipe_config
->adjusted_mode
.crtc_hsync_start
;
4863 crtc
->mode
.hsync_end
= pipe_config
->adjusted_mode
.crtc_hsync_end
;
4865 crtc
->mode
.vdisplay
= pipe_config
->adjusted_mode
.crtc_vdisplay
;
4866 crtc
->mode
.vtotal
= pipe_config
->adjusted_mode
.crtc_vtotal
;
4867 crtc
->mode
.vsync_start
= pipe_config
->adjusted_mode
.crtc_vsync_start
;
4868 crtc
->mode
.vsync_end
= pipe_config
->adjusted_mode
.crtc_vsync_end
;
4870 crtc
->mode
.flags
= pipe_config
->adjusted_mode
.flags
;
4872 crtc
->mode
.clock
= pipe_config
->adjusted_mode
.clock
;
4873 crtc
->mode
.flags
|= pipe_config
->adjusted_mode
.flags
;
4876 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
)
4878 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4879 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4884 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
4885 I915_READ(PIPECONF(intel_crtc
->pipe
)) & PIPECONF_ENABLE
)
4886 pipeconf
|= PIPECONF_ENABLE
;
4888 if (intel_crtc
->config
.double_wide
)
4889 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
4891 /* only g4x and later have fancy bpc/dither controls */
4892 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
4893 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4894 if (intel_crtc
->config
.dither
&& intel_crtc
->config
.pipe_bpp
!= 30)
4895 pipeconf
|= PIPECONF_DITHER_EN
|
4896 PIPECONF_DITHER_TYPE_SP
;
4898 switch (intel_crtc
->config
.pipe_bpp
) {
4900 pipeconf
|= PIPECONF_6BPC
;
4903 pipeconf
|= PIPECONF_8BPC
;
4906 pipeconf
|= PIPECONF_10BPC
;
4909 /* Case prevented by intel_choose_pipe_bpp_dither. */
4914 if (HAS_PIPE_CXSR(dev
)) {
4915 if (intel_crtc
->lowfreq_avail
) {
4916 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4917 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
4919 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4923 if (!IS_GEN2(dev
) &&
4924 intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
4925 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
4927 pipeconf
|= PIPECONF_PROGRESSIVE
;
4929 if (IS_VALLEYVIEW(dev
) && intel_crtc
->config
.limited_color_range
)
4930 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
4932 I915_WRITE(PIPECONF(intel_crtc
->pipe
), pipeconf
);
4933 POSTING_READ(PIPECONF(intel_crtc
->pipe
));
4936 static int i9xx_crtc_mode_set(struct drm_crtc
*crtc
,
4938 struct drm_framebuffer
*fb
)
4940 struct drm_device
*dev
= crtc
->dev
;
4941 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4942 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4943 int pipe
= intel_crtc
->pipe
;
4944 int plane
= intel_crtc
->plane
;
4945 int refclk
, num_connectors
= 0;
4946 intel_clock_t clock
, reduced_clock
;
4948 bool ok
, has_reduced_clock
= false;
4949 bool is_lvds
= false, is_dsi
= false;
4950 struct intel_encoder
*encoder
;
4951 const intel_limit_t
*limit
;
4954 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4955 switch (encoder
->type
) {
4956 case INTEL_OUTPUT_LVDS
:
4959 case INTEL_OUTPUT_DSI
:
4970 if (!intel_crtc
->config
.clock_set
) {
4971 refclk
= i9xx_get_refclk(crtc
, num_connectors
);
4974 * Returns a set of divisors for the desired target clock with
4975 * the given refclk, or FALSE. The returned values represent
4976 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
4979 limit
= intel_limit(crtc
, refclk
);
4980 ok
= dev_priv
->display
.find_dpll(limit
, crtc
,
4981 intel_crtc
->config
.port_clock
,
4982 refclk
, NULL
, &clock
);
4984 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4988 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
4990 * Ensure we match the reduced clock's P to the target
4991 * clock. If the clocks don't match, we can't switch
4992 * the display clock by using the FP0/FP1. In such case
4993 * we will disable the LVDS downclock feature.
4996 dev_priv
->display
.find_dpll(limit
, crtc
,
4997 dev_priv
->lvds_downclock
,
5001 /* Compat-code for transition, will disappear. */
5002 intel_crtc
->config
.dpll
.n
= clock
.n
;
5003 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
5004 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
5005 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
5006 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
5010 i8xx_update_pll(intel_crtc
,
5011 has_reduced_clock
? &reduced_clock
: NULL
,
5013 } else if (IS_VALLEYVIEW(dev
)) {
5014 vlv_update_pll(intel_crtc
);
5016 i9xx_update_pll(intel_crtc
,
5017 has_reduced_clock
? &reduced_clock
: NULL
,
5022 /* Set up the display plane register */
5023 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
5025 if (!IS_VALLEYVIEW(dev
)) {
5027 dspcntr
&= ~DISPPLANE_SEL_PIPE_MASK
;
5029 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
5032 intel_set_pipe_timings(intel_crtc
);
5034 /* pipesrc and dspsize control the size that is scaled from,
5035 * which should always be the user's requested size.
5037 I915_WRITE(DSPSIZE(plane
),
5038 ((intel_crtc
->config
.pipe_src_h
- 1) << 16) |
5039 (intel_crtc
->config
.pipe_src_w
- 1));
5040 I915_WRITE(DSPPOS(plane
), 0);
5042 i9xx_set_pipeconf(intel_crtc
);
5044 I915_WRITE(DSPCNTR(plane
), dspcntr
);
5045 POSTING_READ(DSPCNTR(plane
));
5047 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
5052 static void i9xx_get_pfit_config(struct intel_crtc
*crtc
,
5053 struct intel_crtc_config
*pipe_config
)
5055 struct drm_device
*dev
= crtc
->base
.dev
;
5056 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5059 tmp
= I915_READ(PFIT_CONTROL
);
5060 if (!(tmp
& PFIT_ENABLE
))
5063 /* Check whether the pfit is attached to our pipe. */
5064 if (INTEL_INFO(dev
)->gen
< 4) {
5065 if (crtc
->pipe
!= PIPE_B
)
5068 if ((tmp
& PFIT_PIPE_MASK
) != (crtc
->pipe
<< PFIT_PIPE_SHIFT
))
5072 pipe_config
->gmch_pfit
.control
= tmp
;
5073 pipe_config
->gmch_pfit
.pgm_ratios
= I915_READ(PFIT_PGM_RATIOS
);
5074 if (INTEL_INFO(dev
)->gen
< 5)
5075 pipe_config
->gmch_pfit
.lvds_border_bits
=
5076 I915_READ(LVDS
) & LVDS_BORDER_ENABLE
;
5079 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
5080 struct intel_crtc_config
*pipe_config
)
5082 struct drm_device
*dev
= crtc
->base
.dev
;
5083 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5086 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
5087 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
5089 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
5090 if (!(tmp
& PIPECONF_ENABLE
))
5093 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
5094 switch (tmp
& PIPECONF_BPC_MASK
) {
5096 pipe_config
->pipe_bpp
= 18;
5099 pipe_config
->pipe_bpp
= 24;
5101 case PIPECONF_10BPC
:
5102 pipe_config
->pipe_bpp
= 30;
5109 if (INTEL_INFO(dev
)->gen
< 4)
5110 pipe_config
->double_wide
= tmp
& PIPECONF_DOUBLE_WIDE
;
5112 intel_get_pipe_timings(crtc
, pipe_config
);
5114 i9xx_get_pfit_config(crtc
, pipe_config
);
5116 if (INTEL_INFO(dev
)->gen
>= 4) {
5117 tmp
= I915_READ(DPLL_MD(crtc
->pipe
));
5118 pipe_config
->pixel_multiplier
=
5119 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
5120 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
5121 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
5122 } else if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
5123 tmp
= I915_READ(DPLL(crtc
->pipe
));
5124 pipe_config
->pixel_multiplier
=
5125 ((tmp
& SDVO_MULTIPLIER_MASK
)
5126 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
5128 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5129 * port and will be fixed up in the encoder->get_config
5131 pipe_config
->pixel_multiplier
= 1;
5133 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(crtc
->pipe
));
5134 if (!IS_VALLEYVIEW(dev
)) {
5135 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(crtc
->pipe
));
5136 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(crtc
->pipe
));
5138 /* Mask out read-only status bits. */
5139 pipe_config
->dpll_hw_state
.dpll
&= ~(DPLL_LOCK_VLV
|
5140 DPLL_PORTC_READY_MASK
|
5141 DPLL_PORTB_READY_MASK
);
5144 i9xx_crtc_clock_get(crtc
, pipe_config
);
5149 static void ironlake_init_pch_refclk(struct drm_device
*dev
)
5151 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5152 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
5153 struct intel_encoder
*encoder
;
5155 bool has_lvds
= false;
5156 bool has_cpu_edp
= false;
5157 bool has_panel
= false;
5158 bool has_ck505
= false;
5159 bool can_ssc
= false;
5161 /* We need to take the global config into account */
5162 list_for_each_entry(encoder
, &mode_config
->encoder_list
,
5164 switch (encoder
->type
) {
5165 case INTEL_OUTPUT_LVDS
:
5169 case INTEL_OUTPUT_EDP
:
5171 if (enc_to_dig_port(&encoder
->base
)->port
== PORT_A
)
5177 if (HAS_PCH_IBX(dev
)) {
5178 has_ck505
= dev_priv
->vbt
.display_clock_mode
;
5179 can_ssc
= has_ck505
;
5185 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5186 has_panel
, has_lvds
, has_ck505
);
5188 /* Ironlake: try to setup display ref clock before DPLL
5189 * enabling. This is only under driver's control after
5190 * PCH B stepping, previous chipset stepping should be
5191 * ignoring this setting.
5193 val
= I915_READ(PCH_DREF_CONTROL
);
5195 /* As we must carefully and slowly disable/enable each source in turn,
5196 * compute the final state we want first and check if we need to
5197 * make any changes at all.
5200 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
5202 final
|= DREF_NONSPREAD_CK505_ENABLE
;
5204 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
5206 final
&= ~DREF_SSC_SOURCE_MASK
;
5207 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
5208 final
&= ~DREF_SSC1_ENABLE
;
5211 final
|= DREF_SSC_SOURCE_ENABLE
;
5213 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
5214 final
|= DREF_SSC1_ENABLE
;
5217 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
5218 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
5220 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
5222 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5224 final
|= DREF_SSC_SOURCE_DISABLE
;
5225 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5231 /* Always enable nonspread source */
5232 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
5235 val
|= DREF_NONSPREAD_CK505_ENABLE
;
5237 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
5240 val
&= ~DREF_SSC_SOURCE_MASK
;
5241 val
|= DREF_SSC_SOURCE_ENABLE
;
5243 /* SSC must be turned on before enabling the CPU output */
5244 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
5245 DRM_DEBUG_KMS("Using SSC on panel\n");
5246 val
|= DREF_SSC1_ENABLE
;
5248 val
&= ~DREF_SSC1_ENABLE
;
5250 /* Get SSC going before enabling the outputs */
5251 I915_WRITE(PCH_DREF_CONTROL
, val
);
5252 POSTING_READ(PCH_DREF_CONTROL
);
5255 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
5257 /* Enable CPU source on CPU attached eDP */
5259 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
5260 DRM_DEBUG_KMS("Using SSC on eDP\n");
5261 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
5264 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
5266 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5268 I915_WRITE(PCH_DREF_CONTROL
, val
);
5269 POSTING_READ(PCH_DREF_CONTROL
);
5272 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5274 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
5276 /* Turn off CPU output */
5277 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5279 I915_WRITE(PCH_DREF_CONTROL
, val
);
5280 POSTING_READ(PCH_DREF_CONTROL
);
5283 /* Turn off the SSC source */
5284 val
&= ~DREF_SSC_SOURCE_MASK
;
5285 val
|= DREF_SSC_SOURCE_DISABLE
;
5288 val
&= ~DREF_SSC1_ENABLE
;
5290 I915_WRITE(PCH_DREF_CONTROL
, val
);
5291 POSTING_READ(PCH_DREF_CONTROL
);
5295 BUG_ON(val
!= final
);
5298 static void lpt_reset_fdi_mphy(struct drm_i915_private
*dev_priv
)
5302 tmp
= I915_READ(SOUTH_CHICKEN2
);
5303 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
5304 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
5306 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2
) &
5307 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
5308 DRM_ERROR("FDI mPHY reset assert timeout\n");
5310 tmp
= I915_READ(SOUTH_CHICKEN2
);
5311 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
5312 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
5314 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2
) &
5315 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0, 100))
5316 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5319 /* WaMPhyProgramming:hsw */
5320 static void lpt_program_fdi_mphy(struct drm_i915_private
*dev_priv
)
5324 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
5325 tmp
&= ~(0xFF << 24);
5326 tmp
|= (0x12 << 24);
5327 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
5329 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
5331 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
5333 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
5335 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
5337 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
5338 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
5339 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
5341 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
5342 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
5343 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
5345 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
5348 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
5350 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
5353 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
5355 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
5358 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
5360 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
5363 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
5365 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
5366 tmp
&= ~(0xFF << 16);
5367 tmp
|= (0x1C << 16);
5368 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
5370 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
5371 tmp
&= ~(0xFF << 16);
5372 tmp
|= (0x1C << 16);
5373 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
5375 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
5377 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
5379 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
5381 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
5383 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
5384 tmp
&= ~(0xF << 28);
5386 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
5388 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
5389 tmp
&= ~(0xF << 28);
5391 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
5394 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5395 * Programming" based on the parameters passed:
5396 * - Sequence to enable CLKOUT_DP
5397 * - Sequence to enable CLKOUT_DP without spread
5398 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5400 static void lpt_enable_clkout_dp(struct drm_device
*dev
, bool with_spread
,
5403 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5406 if (WARN(with_fdi
&& !with_spread
, "FDI requires downspread\n"))
5408 if (WARN(dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
&&
5409 with_fdi
, "LP PCH doesn't have FDI\n"))
5412 mutex_lock(&dev_priv
->dpio_lock
);
5414 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
5415 tmp
&= ~SBI_SSCCTL_DISABLE
;
5416 tmp
|= SBI_SSCCTL_PATHALT
;
5417 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
5422 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
5423 tmp
&= ~SBI_SSCCTL_PATHALT
;
5424 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
5427 lpt_reset_fdi_mphy(dev_priv
);
5428 lpt_program_fdi_mphy(dev_priv
);
5432 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
5433 SBI_GEN0
: SBI_DBUFF0
;
5434 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
5435 tmp
|= SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
5436 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
5438 mutex_unlock(&dev_priv
->dpio_lock
);
5441 /* Sequence to disable CLKOUT_DP */
5442 static void lpt_disable_clkout_dp(struct drm_device
*dev
)
5444 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5447 mutex_lock(&dev_priv
->dpio_lock
);
5449 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
5450 SBI_GEN0
: SBI_DBUFF0
;
5451 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
5452 tmp
&= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
5453 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
5455 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
5456 if (!(tmp
& SBI_SSCCTL_DISABLE
)) {
5457 if (!(tmp
& SBI_SSCCTL_PATHALT
)) {
5458 tmp
|= SBI_SSCCTL_PATHALT
;
5459 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
5462 tmp
|= SBI_SSCCTL_DISABLE
;
5463 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
5466 mutex_unlock(&dev_priv
->dpio_lock
);
5469 static void lpt_init_pch_refclk(struct drm_device
*dev
)
5471 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
5472 struct intel_encoder
*encoder
;
5473 bool has_vga
= false;
5475 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
) {
5476 switch (encoder
->type
) {
5477 case INTEL_OUTPUT_ANALOG
:
5484 lpt_enable_clkout_dp(dev
, true, true);
5486 lpt_disable_clkout_dp(dev
);
5490 * Initialize reference clocks when the driver loads
5492 void intel_init_pch_refclk(struct drm_device
*dev
)
5494 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
5495 ironlake_init_pch_refclk(dev
);
5496 else if (HAS_PCH_LPT(dev
))
5497 lpt_init_pch_refclk(dev
);
5500 static int ironlake_get_refclk(struct drm_crtc
*crtc
)
5502 struct drm_device
*dev
= crtc
->dev
;
5503 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5504 struct intel_encoder
*encoder
;
5505 int num_connectors
= 0;
5506 bool is_lvds
= false;
5508 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5509 switch (encoder
->type
) {
5510 case INTEL_OUTPUT_LVDS
:
5517 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
5518 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5519 dev_priv
->vbt
.lvds_ssc_freq
);
5520 return dev_priv
->vbt
.lvds_ssc_freq
* 1000;
5526 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
)
5528 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
5529 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5530 int pipe
= intel_crtc
->pipe
;
5535 switch (intel_crtc
->config
.pipe_bpp
) {
5537 val
|= PIPECONF_6BPC
;
5540 val
|= PIPECONF_8BPC
;
5543 val
|= PIPECONF_10BPC
;
5546 val
|= PIPECONF_12BPC
;
5549 /* Case prevented by intel_choose_pipe_bpp_dither. */
5553 if (intel_crtc
->config
.dither
)
5554 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
5556 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
5557 val
|= PIPECONF_INTERLACED_ILK
;
5559 val
|= PIPECONF_PROGRESSIVE
;
5561 if (intel_crtc
->config
.limited_color_range
)
5562 val
|= PIPECONF_COLOR_RANGE_SELECT
;
5564 I915_WRITE(PIPECONF(pipe
), val
);
5565 POSTING_READ(PIPECONF(pipe
));
5569 * Set up the pipe CSC unit.
5571 * Currently only full range RGB to limited range RGB conversion
5572 * is supported, but eventually this should handle various
5573 * RGB<->YCbCr scenarios as well.
5575 static void intel_set_pipe_csc(struct drm_crtc
*crtc
)
5577 struct drm_device
*dev
= crtc
->dev
;
5578 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5579 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5580 int pipe
= intel_crtc
->pipe
;
5581 uint16_t coeff
= 0x7800; /* 1.0 */
5584 * TODO: Check what kind of values actually come out of the pipe
5585 * with these coeff/postoff values and adjust to get the best
5586 * accuracy. Perhaps we even need to take the bpc value into
5590 if (intel_crtc
->config
.limited_color_range
)
5591 coeff
= ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5594 * GY/GU and RY/RU should be the other way around according
5595 * to BSpec, but reality doesn't agree. Just set them up in
5596 * a way that results in the correct picture.
5598 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe
), coeff
<< 16);
5599 I915_WRITE(PIPE_CSC_COEFF_BY(pipe
), 0);
5601 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe
), coeff
);
5602 I915_WRITE(PIPE_CSC_COEFF_BU(pipe
), 0);
5604 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe
), 0);
5605 I915_WRITE(PIPE_CSC_COEFF_BV(pipe
), coeff
<< 16);
5607 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe
), 0);
5608 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe
), 0);
5609 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe
), 0);
5611 if (INTEL_INFO(dev
)->gen
> 6) {
5612 uint16_t postoff
= 0;
5614 if (intel_crtc
->config
.limited_color_range
)
5615 postoff
= (16 * (1 << 13) / 255) & 0x1fff;
5617 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe
), postoff
);
5618 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe
), postoff
);
5619 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe
), postoff
);
5621 I915_WRITE(PIPE_CSC_MODE(pipe
), 0);
5623 uint32_t mode
= CSC_MODE_YUV_TO_RGB
;
5625 if (intel_crtc
->config
.limited_color_range
)
5626 mode
|= CSC_BLACK_SCREEN_OFFSET
;
5628 I915_WRITE(PIPE_CSC_MODE(pipe
), mode
);
5632 static void haswell_set_pipeconf(struct drm_crtc
*crtc
)
5634 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
5635 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5636 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
5641 if (intel_crtc
->config
.dither
)
5642 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
5644 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
5645 val
|= PIPECONF_INTERLACED_ILK
;
5647 val
|= PIPECONF_PROGRESSIVE
;
5649 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
5650 POSTING_READ(PIPECONF(cpu_transcoder
));
5652 I915_WRITE(GAMMA_MODE(intel_crtc
->pipe
), GAMMA_MODE_MODE_8BIT
);
5653 POSTING_READ(GAMMA_MODE(intel_crtc
->pipe
));
5656 static bool ironlake_compute_clocks(struct drm_crtc
*crtc
,
5657 intel_clock_t
*clock
,
5658 bool *has_reduced_clock
,
5659 intel_clock_t
*reduced_clock
)
5661 struct drm_device
*dev
= crtc
->dev
;
5662 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5663 struct intel_encoder
*intel_encoder
;
5665 const intel_limit_t
*limit
;
5666 bool ret
, is_lvds
= false;
5668 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
5669 switch (intel_encoder
->type
) {
5670 case INTEL_OUTPUT_LVDS
:
5676 refclk
= ironlake_get_refclk(crtc
);
5679 * Returns a set of divisors for the desired target clock with the given
5680 * refclk, or FALSE. The returned values represent the clock equation:
5681 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5683 limit
= intel_limit(crtc
, refclk
);
5684 ret
= dev_priv
->display
.find_dpll(limit
, crtc
,
5685 to_intel_crtc(crtc
)->config
.port_clock
,
5686 refclk
, NULL
, clock
);
5690 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
5692 * Ensure we match the reduced clock's P to the target clock.
5693 * If the clocks don't match, we can't switch the display clock
5694 * by using the FP0/FP1. In such case we will disable the LVDS
5695 * downclock feature.
5697 *has_reduced_clock
=
5698 dev_priv
->display
.find_dpll(limit
, crtc
,
5699 dev_priv
->lvds_downclock
,
5707 static void cpt_enable_fdi_bc_bifurcation(struct drm_device
*dev
)
5709 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5712 temp
= I915_READ(SOUTH_CHICKEN1
);
5713 if (temp
& FDI_BC_BIFURCATION_SELECT
)
5716 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
5717 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
5719 temp
|= FDI_BC_BIFURCATION_SELECT
;
5720 DRM_DEBUG_KMS("enabling fdi C rx\n");
5721 I915_WRITE(SOUTH_CHICKEN1
, temp
);
5722 POSTING_READ(SOUTH_CHICKEN1
);
5725 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc
*intel_crtc
)
5727 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5728 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5730 switch (intel_crtc
->pipe
) {
5734 if (intel_crtc
->config
.fdi_lanes
> 2)
5735 WARN_ON(I915_READ(SOUTH_CHICKEN1
) & FDI_BC_BIFURCATION_SELECT
);
5737 cpt_enable_fdi_bc_bifurcation(dev
);
5741 cpt_enable_fdi_bc_bifurcation(dev
);
5749 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
5752 * Account for spread spectrum to avoid
5753 * oversubscribing the link. Max center spread
5754 * is 2.5%; use 5% for safety's sake.
5756 u32 bps
= target_clock
* bpp
* 21 / 20;
5757 return bps
/ (link_bw
* 8) + 1;
5760 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
5762 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
5765 static uint32_t ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
5767 intel_clock_t
*reduced_clock
, u32
*fp2
)
5769 struct drm_crtc
*crtc
= &intel_crtc
->base
;
5770 struct drm_device
*dev
= crtc
->dev
;
5771 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5772 struct intel_encoder
*intel_encoder
;
5774 int factor
, num_connectors
= 0;
5775 bool is_lvds
= false, is_sdvo
= false;
5777 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
5778 switch (intel_encoder
->type
) {
5779 case INTEL_OUTPUT_LVDS
:
5782 case INTEL_OUTPUT_SDVO
:
5783 case INTEL_OUTPUT_HDMI
:
5791 /* Enable autotuning of the PLL clock (if permissible) */
5794 if ((intel_panel_use_ssc(dev_priv
) &&
5795 dev_priv
->vbt
.lvds_ssc_freq
== 100) ||
5796 (HAS_PCH_IBX(dev
) && intel_is_dual_link_lvds(dev
)))
5798 } else if (intel_crtc
->config
.sdvo_tv_clock
)
5801 if (ironlake_needs_fb_cb_tune(&intel_crtc
->config
.dpll
, factor
))
5804 if (fp2
&& (reduced_clock
->m
< factor
* reduced_clock
->n
))
5810 dpll
|= DPLLB_MODE_LVDS
;
5812 dpll
|= DPLLB_MODE_DAC_SERIAL
;
5814 dpll
|= (intel_crtc
->config
.pixel_multiplier
- 1)
5815 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
5818 dpll
|= DPLL_SDVO_HIGH_SPEED
;
5819 if (intel_crtc
->config
.has_dp_encoder
)
5820 dpll
|= DPLL_SDVO_HIGH_SPEED
;
5822 /* compute bitmask from p1 value */
5823 dpll
|= (1 << (intel_crtc
->config
.dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5825 dpll
|= (1 << (intel_crtc
->config
.dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
5827 switch (intel_crtc
->config
.dpll
.p2
) {
5829 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
5832 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
5835 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
5838 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
5842 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
5843 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
5845 dpll
|= PLL_REF_INPUT_DREFCLK
;
5847 return dpll
| DPLL_VCO_ENABLE
;
5850 static int ironlake_crtc_mode_set(struct drm_crtc
*crtc
,
5852 struct drm_framebuffer
*fb
)
5854 struct drm_device
*dev
= crtc
->dev
;
5855 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5856 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5857 int pipe
= intel_crtc
->pipe
;
5858 int plane
= intel_crtc
->plane
;
5859 int num_connectors
= 0;
5860 intel_clock_t clock
, reduced_clock
;
5861 u32 dpll
= 0, fp
= 0, fp2
= 0;
5862 bool ok
, has_reduced_clock
= false;
5863 bool is_lvds
= false;
5864 struct intel_encoder
*encoder
;
5865 struct intel_shared_dpll
*pll
;
5868 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5869 switch (encoder
->type
) {
5870 case INTEL_OUTPUT_LVDS
:
5878 WARN(!(HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)),
5879 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev
));
5881 ok
= ironlake_compute_clocks(crtc
, &clock
,
5882 &has_reduced_clock
, &reduced_clock
);
5883 if (!ok
&& !intel_crtc
->config
.clock_set
) {
5884 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5887 /* Compat-code for transition, will disappear. */
5888 if (!intel_crtc
->config
.clock_set
) {
5889 intel_crtc
->config
.dpll
.n
= clock
.n
;
5890 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
5891 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
5892 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
5893 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
5896 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5897 if (intel_crtc
->config
.has_pch_encoder
) {
5898 fp
= i9xx_dpll_compute_fp(&intel_crtc
->config
.dpll
);
5899 if (has_reduced_clock
)
5900 fp2
= i9xx_dpll_compute_fp(&reduced_clock
);
5902 dpll
= ironlake_compute_dpll(intel_crtc
,
5903 &fp
, &reduced_clock
,
5904 has_reduced_clock
? &fp2
: NULL
);
5906 intel_crtc
->config
.dpll_hw_state
.dpll
= dpll
;
5907 intel_crtc
->config
.dpll_hw_state
.fp0
= fp
;
5908 if (has_reduced_clock
)
5909 intel_crtc
->config
.dpll_hw_state
.fp1
= fp2
;
5911 intel_crtc
->config
.dpll_hw_state
.fp1
= fp
;
5913 pll
= intel_get_shared_dpll(intel_crtc
);
5915 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5920 intel_put_shared_dpll(intel_crtc
);
5922 if (intel_crtc
->config
.has_dp_encoder
)
5923 intel_dp_set_m_n(intel_crtc
);
5925 if (is_lvds
&& has_reduced_clock
&& i915_powersave
)
5926 intel_crtc
->lowfreq_avail
= true;
5928 intel_crtc
->lowfreq_avail
= false;
5930 if (intel_crtc
->config
.has_pch_encoder
) {
5931 pll
= intel_crtc_to_shared_dpll(intel_crtc
);
5935 intel_set_pipe_timings(intel_crtc
);
5937 if (intel_crtc
->config
.has_pch_encoder
) {
5938 intel_cpu_transcoder_set_m_n(intel_crtc
,
5939 &intel_crtc
->config
.fdi_m_n
);
5942 if (IS_IVYBRIDGE(dev
))
5943 ivybridge_update_fdi_bc_bifurcation(intel_crtc
);
5945 ironlake_set_pipeconf(crtc
);
5947 /* Set up the display plane register */
5948 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
);
5949 POSTING_READ(DSPCNTR(plane
));
5951 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
5956 static void intel_pch_transcoder_get_m_n(struct intel_crtc
*crtc
,
5957 struct intel_link_m_n
*m_n
)
5959 struct drm_device
*dev
= crtc
->base
.dev
;
5960 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5961 enum pipe pipe
= crtc
->pipe
;
5963 m_n
->link_m
= I915_READ(PCH_TRANS_LINK_M1(pipe
));
5964 m_n
->link_n
= I915_READ(PCH_TRANS_LINK_N1(pipe
));
5965 m_n
->gmch_m
= I915_READ(PCH_TRANS_DATA_M1(pipe
))
5967 m_n
->gmch_n
= I915_READ(PCH_TRANS_DATA_N1(pipe
));
5968 m_n
->tu
= ((I915_READ(PCH_TRANS_DATA_M1(pipe
))
5969 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
5972 static void intel_cpu_transcoder_get_m_n(struct intel_crtc
*crtc
,
5973 enum transcoder transcoder
,
5974 struct intel_link_m_n
*m_n
)
5976 struct drm_device
*dev
= crtc
->base
.dev
;
5977 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5978 enum pipe pipe
= crtc
->pipe
;
5980 if (INTEL_INFO(dev
)->gen
>= 5) {
5981 m_n
->link_m
= I915_READ(PIPE_LINK_M1(transcoder
));
5982 m_n
->link_n
= I915_READ(PIPE_LINK_N1(transcoder
));
5983 m_n
->gmch_m
= I915_READ(PIPE_DATA_M1(transcoder
))
5985 m_n
->gmch_n
= I915_READ(PIPE_DATA_N1(transcoder
));
5986 m_n
->tu
= ((I915_READ(PIPE_DATA_M1(transcoder
))
5987 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
5989 m_n
->link_m
= I915_READ(PIPE_LINK_M_G4X(pipe
));
5990 m_n
->link_n
= I915_READ(PIPE_LINK_N_G4X(pipe
));
5991 m_n
->gmch_m
= I915_READ(PIPE_DATA_M_G4X(pipe
))
5993 m_n
->gmch_n
= I915_READ(PIPE_DATA_N_G4X(pipe
));
5994 m_n
->tu
= ((I915_READ(PIPE_DATA_M_G4X(pipe
))
5995 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
5999 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
6000 struct intel_crtc_config
*pipe_config
)
6002 if (crtc
->config
.has_pch_encoder
)
6003 intel_pch_transcoder_get_m_n(crtc
, &pipe_config
->dp_m_n
);
6005 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
6006 &pipe_config
->dp_m_n
);
6009 static void ironlake_get_fdi_m_n_config(struct intel_crtc
*crtc
,
6010 struct intel_crtc_config
*pipe_config
)
6012 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
6013 &pipe_config
->fdi_m_n
);
6016 static void ironlake_get_pfit_config(struct intel_crtc
*crtc
,
6017 struct intel_crtc_config
*pipe_config
)
6019 struct drm_device
*dev
= crtc
->base
.dev
;
6020 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6023 tmp
= I915_READ(PF_CTL(crtc
->pipe
));
6025 if (tmp
& PF_ENABLE
) {
6026 pipe_config
->pch_pfit
.enabled
= true;
6027 pipe_config
->pch_pfit
.pos
= I915_READ(PF_WIN_POS(crtc
->pipe
));
6028 pipe_config
->pch_pfit
.size
= I915_READ(PF_WIN_SZ(crtc
->pipe
));
6030 /* We currently do not free assignements of panel fitters on
6031 * ivb/hsw (since we don't use the higher upscaling modes which
6032 * differentiates them) so just WARN about this case for now. */
6034 WARN_ON((tmp
& PF_PIPE_SEL_MASK_IVB
) !=
6035 PF_PIPE_SEL_IVB(crtc
->pipe
));
6040 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
6041 struct intel_crtc_config
*pipe_config
)
6043 struct drm_device
*dev
= crtc
->base
.dev
;
6044 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6047 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
6048 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
6050 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
6051 if (!(tmp
& PIPECONF_ENABLE
))
6054 switch (tmp
& PIPECONF_BPC_MASK
) {
6056 pipe_config
->pipe_bpp
= 18;
6059 pipe_config
->pipe_bpp
= 24;
6061 case PIPECONF_10BPC
:
6062 pipe_config
->pipe_bpp
= 30;
6064 case PIPECONF_12BPC
:
6065 pipe_config
->pipe_bpp
= 36;
6071 if (I915_READ(PCH_TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
) {
6072 struct intel_shared_dpll
*pll
;
6074 pipe_config
->has_pch_encoder
= true;
6076 tmp
= I915_READ(FDI_RX_CTL(crtc
->pipe
));
6077 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
6078 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
6080 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
6082 if (HAS_PCH_IBX(dev_priv
->dev
)) {
6083 pipe_config
->shared_dpll
=
6084 (enum intel_dpll_id
) crtc
->pipe
;
6086 tmp
= I915_READ(PCH_DPLL_SEL
);
6087 if (tmp
& TRANS_DPLLB_SEL(crtc
->pipe
))
6088 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_B
;
6090 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_A
;
6093 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
6095 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
6096 &pipe_config
->dpll_hw_state
));
6098 tmp
= pipe_config
->dpll_hw_state
.dpll
;
6099 pipe_config
->pixel_multiplier
=
6100 ((tmp
& PLL_REF_SDVO_HDMI_MULTIPLIER_MASK
)
6101 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
) + 1;
6103 ironlake_pch_clock_get(crtc
, pipe_config
);
6105 pipe_config
->pixel_multiplier
= 1;
6108 intel_get_pipe_timings(crtc
, pipe_config
);
6110 ironlake_get_pfit_config(crtc
, pipe_config
);
6115 static void assert_can_disable_lcpll(struct drm_i915_private
*dev_priv
)
6117 struct drm_device
*dev
= dev_priv
->dev
;
6118 struct intel_ddi_plls
*plls
= &dev_priv
->ddi_plls
;
6119 struct intel_crtc
*crtc
;
6120 unsigned long irqflags
;
6123 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
)
6124 WARN(crtc
->base
.enabled
, "CRTC for pipe %c enabled\n",
6125 pipe_name(crtc
->pipe
));
6127 WARN(I915_READ(HSW_PWR_WELL_DRIVER
), "Power well on\n");
6128 WARN(plls
->spll_refcount
, "SPLL enabled\n");
6129 WARN(plls
->wrpll1_refcount
, "WRPLL1 enabled\n");
6130 WARN(plls
->wrpll2_refcount
, "WRPLL2 enabled\n");
6131 WARN(I915_READ(PCH_PP_STATUS
) & PP_ON
, "Panel power on\n");
6132 WARN(I915_READ(BLC_PWM_CPU_CTL2
) & BLM_PWM_ENABLE
,
6133 "CPU PWM1 enabled\n");
6134 WARN(I915_READ(HSW_BLC_PWM2_CTL
) & BLM_PWM_ENABLE
,
6135 "CPU PWM2 enabled\n");
6136 WARN(I915_READ(BLC_PWM_PCH_CTL1
) & BLM_PCH_PWM_ENABLE
,
6137 "PCH PWM1 enabled\n");
6138 WARN(I915_READ(UTIL_PIN_CTL
) & UTIL_PIN_ENABLE
,
6139 "Utility pin enabled\n");
6140 WARN(I915_READ(PCH_GTC_CTL
) & PCH_GTC_ENABLE
, "PCH GTC enabled\n");
6142 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
6143 val
= I915_READ(DEIMR
);
6144 WARN((val
& ~DE_PCH_EVENT_IVB
) != val
,
6145 "Unexpected DEIMR bits enabled: 0x%x\n", val
);
6146 val
= I915_READ(SDEIMR
);
6147 WARN((val
| SDE_HOTPLUG_MASK_CPT
) != 0xffffffff,
6148 "Unexpected SDEIMR bits enabled: 0x%x\n", val
);
6149 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
6153 * This function implements pieces of two sequences from BSpec:
6154 * - Sequence for display software to disable LCPLL
6155 * - Sequence for display software to allow package C8+
6156 * The steps implemented here are just the steps that actually touch the LCPLL
6157 * register. Callers should take care of disabling all the display engine
6158 * functions, doing the mode unset, fixing interrupts, etc.
6160 void hsw_disable_lcpll(struct drm_i915_private
*dev_priv
,
6161 bool switch_to_fclk
, bool allow_power_down
)
6165 assert_can_disable_lcpll(dev_priv
);
6167 val
= I915_READ(LCPLL_CTL
);
6169 if (switch_to_fclk
) {
6170 val
|= LCPLL_CD_SOURCE_FCLK
;
6171 I915_WRITE(LCPLL_CTL
, val
);
6173 if (wait_for_atomic_us(I915_READ(LCPLL_CTL
) &
6174 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
6175 DRM_ERROR("Switching to FCLK failed\n");
6177 val
= I915_READ(LCPLL_CTL
);
6180 val
|= LCPLL_PLL_DISABLE
;
6181 I915_WRITE(LCPLL_CTL
, val
);
6182 POSTING_READ(LCPLL_CTL
);
6184 if (wait_for((I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
) == 0, 1))
6185 DRM_ERROR("LCPLL still locked\n");
6187 val
= I915_READ(D_COMP
);
6188 val
|= D_COMP_COMP_DISABLE
;
6189 mutex_lock(&dev_priv
->rps
.hw_lock
);
6190 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
, val
))
6191 DRM_ERROR("Failed to disable D_COMP\n");
6192 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6193 POSTING_READ(D_COMP
);
6196 if (wait_for((I915_READ(D_COMP
) & D_COMP_RCOMP_IN_PROGRESS
) == 0, 1))
6197 DRM_ERROR("D_COMP RCOMP still in progress\n");
6199 if (allow_power_down
) {
6200 val
= I915_READ(LCPLL_CTL
);
6201 val
|= LCPLL_POWER_DOWN_ALLOW
;
6202 I915_WRITE(LCPLL_CTL
, val
);
6203 POSTING_READ(LCPLL_CTL
);
6208 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6211 void hsw_restore_lcpll(struct drm_i915_private
*dev_priv
)
6215 val
= I915_READ(LCPLL_CTL
);
6217 if ((val
& (LCPLL_PLL_LOCK
| LCPLL_PLL_DISABLE
| LCPLL_CD_SOURCE_FCLK
|
6218 LCPLL_POWER_DOWN_ALLOW
)) == LCPLL_PLL_LOCK
)
6221 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6222 * we'll hang the machine! */
6223 dev_priv
->uncore
.funcs
.force_wake_get(dev_priv
);
6225 if (val
& LCPLL_POWER_DOWN_ALLOW
) {
6226 val
&= ~LCPLL_POWER_DOWN_ALLOW
;
6227 I915_WRITE(LCPLL_CTL
, val
);
6228 POSTING_READ(LCPLL_CTL
);
6231 val
= I915_READ(D_COMP
);
6232 val
|= D_COMP_COMP_FORCE
;
6233 val
&= ~D_COMP_COMP_DISABLE
;
6234 mutex_lock(&dev_priv
->rps
.hw_lock
);
6235 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
, val
))
6236 DRM_ERROR("Failed to enable D_COMP\n");
6237 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6238 POSTING_READ(D_COMP
);
6240 val
= I915_READ(LCPLL_CTL
);
6241 val
&= ~LCPLL_PLL_DISABLE
;
6242 I915_WRITE(LCPLL_CTL
, val
);
6244 if (wait_for(I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
, 5))
6245 DRM_ERROR("LCPLL not locked yet\n");
6247 if (val
& LCPLL_CD_SOURCE_FCLK
) {
6248 val
= I915_READ(LCPLL_CTL
);
6249 val
&= ~LCPLL_CD_SOURCE_FCLK
;
6250 I915_WRITE(LCPLL_CTL
, val
);
6252 if (wait_for_atomic_us((I915_READ(LCPLL_CTL
) &
6253 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
6254 DRM_ERROR("Switching back to LCPLL failed\n");
6257 dev_priv
->uncore
.funcs
.force_wake_put(dev_priv
);
6260 void hsw_enable_pc8_work(struct work_struct
*__work
)
6262 struct drm_i915_private
*dev_priv
=
6263 container_of(to_delayed_work(__work
), struct drm_i915_private
,
6265 struct drm_device
*dev
= dev_priv
->dev
;
6268 if (dev_priv
->pc8
.enabled
)
6271 DRM_DEBUG_KMS("Enabling package C8+\n");
6273 dev_priv
->pc8
.enabled
= true;
6275 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
6276 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
6277 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
6278 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
6281 lpt_disable_clkout_dp(dev
);
6282 hsw_pc8_disable_interrupts(dev
);
6283 hsw_disable_lcpll(dev_priv
, true, true);
6286 static void __hsw_enable_package_c8(struct drm_i915_private
*dev_priv
)
6288 WARN_ON(!mutex_is_locked(&dev_priv
->pc8
.lock
));
6289 WARN(dev_priv
->pc8
.disable_count
< 1,
6290 "pc8.disable_count: %d\n", dev_priv
->pc8
.disable_count
);
6292 dev_priv
->pc8
.disable_count
--;
6293 if (dev_priv
->pc8
.disable_count
!= 0)
6296 schedule_delayed_work(&dev_priv
->pc8
.enable_work
,
6297 msecs_to_jiffies(i915_pc8_timeout
));
6300 static void __hsw_disable_package_c8(struct drm_i915_private
*dev_priv
)
6302 struct drm_device
*dev
= dev_priv
->dev
;
6305 WARN_ON(!mutex_is_locked(&dev_priv
->pc8
.lock
));
6306 WARN(dev_priv
->pc8
.disable_count
< 0,
6307 "pc8.disable_count: %d\n", dev_priv
->pc8
.disable_count
);
6309 dev_priv
->pc8
.disable_count
++;
6310 if (dev_priv
->pc8
.disable_count
!= 1)
6313 cancel_delayed_work_sync(&dev_priv
->pc8
.enable_work
);
6314 if (!dev_priv
->pc8
.enabled
)
6317 DRM_DEBUG_KMS("Disabling package C8+\n");
6319 hsw_restore_lcpll(dev_priv
);
6320 hsw_pc8_restore_interrupts(dev
);
6321 lpt_init_pch_refclk(dev
);
6323 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
6324 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
6325 val
|= PCH_LP_PARTITION_LEVEL_DISABLE
;
6326 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
6329 intel_prepare_ddi(dev
);
6330 i915_gem_init_swizzling(dev
);
6331 mutex_lock(&dev_priv
->rps
.hw_lock
);
6332 gen6_update_ring_freq(dev
);
6333 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6334 dev_priv
->pc8
.enabled
= false;
6337 void hsw_enable_package_c8(struct drm_i915_private
*dev_priv
)
6339 mutex_lock(&dev_priv
->pc8
.lock
);
6340 __hsw_enable_package_c8(dev_priv
);
6341 mutex_unlock(&dev_priv
->pc8
.lock
);
6344 void hsw_disable_package_c8(struct drm_i915_private
*dev_priv
)
6346 mutex_lock(&dev_priv
->pc8
.lock
);
6347 __hsw_disable_package_c8(dev_priv
);
6348 mutex_unlock(&dev_priv
->pc8
.lock
);
6351 static bool hsw_can_enable_package_c8(struct drm_i915_private
*dev_priv
)
6353 struct drm_device
*dev
= dev_priv
->dev
;
6354 struct intel_crtc
*crtc
;
6357 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
)
6358 if (crtc
->base
.enabled
)
6361 /* This case is still possible since we have the i915.disable_power_well
6362 * parameter and also the KVMr or something else might be requesting the
6364 val
= I915_READ(HSW_PWR_WELL_DRIVER
);
6366 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6373 /* Since we're called from modeset_global_resources there's no way to
6374 * symmetrically increase and decrease the refcount, so we use
6375 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6378 static void hsw_update_package_c8(struct drm_device
*dev
)
6380 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6383 if (!i915_enable_pc8
)
6386 mutex_lock(&dev_priv
->pc8
.lock
);
6388 allow
= hsw_can_enable_package_c8(dev_priv
);
6390 if (allow
== dev_priv
->pc8
.requirements_met
)
6393 dev_priv
->pc8
.requirements_met
= allow
;
6396 __hsw_enable_package_c8(dev_priv
);
6398 __hsw_disable_package_c8(dev_priv
);
6401 mutex_unlock(&dev_priv
->pc8
.lock
);
6404 static void hsw_package_c8_gpu_idle(struct drm_i915_private
*dev_priv
)
6406 if (!dev_priv
->pc8
.gpu_idle
) {
6407 dev_priv
->pc8
.gpu_idle
= true;
6408 hsw_enable_package_c8(dev_priv
);
6412 static void hsw_package_c8_gpu_busy(struct drm_i915_private
*dev_priv
)
6414 if (dev_priv
->pc8
.gpu_idle
) {
6415 dev_priv
->pc8
.gpu_idle
= false;
6416 hsw_disable_package_c8(dev_priv
);
6420 static void haswell_modeset_global_resources(struct drm_device
*dev
)
6422 bool enable
= false;
6423 struct intel_crtc
*crtc
;
6425 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
6426 if (!crtc
->base
.enabled
)
6429 if (crtc
->pipe
!= PIPE_A
|| crtc
->config
.pch_pfit
.enabled
||
6430 crtc
->config
.cpu_transcoder
!= TRANSCODER_EDP
)
6434 intel_set_power_well(dev
, enable
);
6436 hsw_update_package_c8(dev
);
6439 static int haswell_crtc_mode_set(struct drm_crtc
*crtc
,
6441 struct drm_framebuffer
*fb
)
6443 struct drm_device
*dev
= crtc
->dev
;
6444 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6445 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6446 int plane
= intel_crtc
->plane
;
6449 if (!intel_ddi_pll_mode_set(crtc
))
6452 if (intel_crtc
->config
.has_dp_encoder
)
6453 intel_dp_set_m_n(intel_crtc
);
6455 intel_crtc
->lowfreq_avail
= false;
6457 intel_set_pipe_timings(intel_crtc
);
6459 if (intel_crtc
->config
.has_pch_encoder
) {
6460 intel_cpu_transcoder_set_m_n(intel_crtc
,
6461 &intel_crtc
->config
.fdi_m_n
);
6464 haswell_set_pipeconf(crtc
);
6466 intel_set_pipe_csc(crtc
);
6468 /* Set up the display plane register */
6469 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
| DISPPLANE_PIPE_CSC_ENABLE
);
6470 POSTING_READ(DSPCNTR(plane
));
6472 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
6477 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
6478 struct intel_crtc_config
*pipe_config
)
6480 struct drm_device
*dev
= crtc
->base
.dev
;
6481 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6482 enum intel_display_power_domain pfit_domain
;
6485 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
6486 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
6488 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
6489 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
6490 enum pipe trans_edp_pipe
;
6491 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
6493 WARN(1, "unknown pipe linked to edp transcoder\n");
6494 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
6495 case TRANS_DDI_EDP_INPUT_A_ON
:
6496 trans_edp_pipe
= PIPE_A
;
6498 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
6499 trans_edp_pipe
= PIPE_B
;
6501 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
6502 trans_edp_pipe
= PIPE_C
;
6506 if (trans_edp_pipe
== crtc
->pipe
)
6507 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
6510 if (!intel_display_power_enabled(dev
,
6511 POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
)))
6514 tmp
= I915_READ(PIPECONF(pipe_config
->cpu_transcoder
));
6515 if (!(tmp
& PIPECONF_ENABLE
))
6519 * Haswell has only FDI/PCH transcoder A. It is which is connected to
6520 * DDI E. So just check whether this pipe is wired to DDI E and whether
6521 * the PCH transcoder is on.
6523 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
6524 if ((tmp
& TRANS_DDI_PORT_MASK
) == TRANS_DDI_SELECT_PORT(PORT_E
) &&
6525 I915_READ(LPT_TRANSCONF
) & TRANS_ENABLE
) {
6526 pipe_config
->has_pch_encoder
= true;
6528 tmp
= I915_READ(FDI_RX_CTL(PIPE_A
));
6529 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
6530 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
6532 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
6535 intel_get_pipe_timings(crtc
, pipe_config
);
6537 pfit_domain
= POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
);
6538 if (intel_display_power_enabled(dev
, pfit_domain
))
6539 ironlake_get_pfit_config(crtc
, pipe_config
);
6541 pipe_config
->ips_enabled
= hsw_crtc_supports_ips(crtc
) &&
6542 (I915_READ(IPS_CTL
) & IPS_ENABLE
);
6544 pipe_config
->pixel_multiplier
= 1;
6549 static int intel_crtc_mode_set(struct drm_crtc
*crtc
,
6551 struct drm_framebuffer
*fb
)
6553 struct drm_device
*dev
= crtc
->dev
;
6554 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6555 struct intel_encoder
*encoder
;
6556 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6557 struct drm_display_mode
*mode
= &intel_crtc
->config
.requested_mode
;
6558 int pipe
= intel_crtc
->pipe
;
6561 drm_vblank_pre_modeset(dev
, pipe
);
6563 ret
= dev_priv
->display
.crtc_mode_set(crtc
, x
, y
, fb
);
6565 drm_vblank_post_modeset(dev
, pipe
);
6570 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
6571 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6572 encoder
->base
.base
.id
,
6573 drm_get_encoder_name(&encoder
->base
),
6574 mode
->base
.id
, mode
->name
);
6575 encoder
->mode_set(encoder
);
6581 static bool intel_eld_uptodate(struct drm_connector
*connector
,
6582 int reg_eldv
, uint32_t bits_eldv
,
6583 int reg_elda
, uint32_t bits_elda
,
6586 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6587 uint8_t *eld
= connector
->eld
;
6590 i
= I915_READ(reg_eldv
);
6599 i
= I915_READ(reg_elda
);
6601 I915_WRITE(reg_elda
, i
);
6603 for (i
= 0; i
< eld
[2]; i
++)
6604 if (I915_READ(reg_edid
) != *((uint32_t *)eld
+ i
))
6610 static void g4x_write_eld(struct drm_connector
*connector
,
6611 struct drm_crtc
*crtc
)
6613 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6614 uint8_t *eld
= connector
->eld
;
6619 i
= I915_READ(G4X_AUD_VID_DID
);
6621 if (i
== INTEL_AUDIO_DEVBLC
|| i
== INTEL_AUDIO_DEVCL
)
6622 eldv
= G4X_ELDV_DEVCL_DEVBLC
;
6624 eldv
= G4X_ELDV_DEVCTG
;
6626 if (intel_eld_uptodate(connector
,
6627 G4X_AUD_CNTL_ST
, eldv
,
6628 G4X_AUD_CNTL_ST
, G4X_ELD_ADDR
,
6629 G4X_HDMIW_HDMIEDID
))
6632 i
= I915_READ(G4X_AUD_CNTL_ST
);
6633 i
&= ~(eldv
| G4X_ELD_ADDR
);
6634 len
= (i
>> 9) & 0x1f; /* ELD buffer size */
6635 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
6640 len
= min_t(uint8_t, eld
[2], len
);
6641 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
6642 for (i
= 0; i
< len
; i
++)
6643 I915_WRITE(G4X_HDMIW_HDMIEDID
, *((uint32_t *)eld
+ i
));
6645 i
= I915_READ(G4X_AUD_CNTL_ST
);
6647 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
6650 static void haswell_write_eld(struct drm_connector
*connector
,
6651 struct drm_crtc
*crtc
)
6653 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6654 uint8_t *eld
= connector
->eld
;
6655 struct drm_device
*dev
= crtc
->dev
;
6656 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6660 int pipe
= to_intel_crtc(crtc
)->pipe
;
6663 int hdmiw_hdmiedid
= HSW_AUD_EDID_DATA(pipe
);
6664 int aud_cntl_st
= HSW_AUD_DIP_ELD_CTRL(pipe
);
6665 int aud_config
= HSW_AUD_CFG(pipe
);
6666 int aud_cntrl_st2
= HSW_AUD_PIN_ELD_CP_VLD
;
6669 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6671 /* Audio output enable */
6672 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6673 tmp
= I915_READ(aud_cntrl_st2
);
6674 tmp
|= (AUDIO_OUTPUT_ENABLE_A
<< (pipe
* 4));
6675 I915_WRITE(aud_cntrl_st2
, tmp
);
6677 /* Wait for 1 vertical blank */
6678 intel_wait_for_vblank(dev
, pipe
);
6680 /* Set ELD valid state */
6681 tmp
= I915_READ(aud_cntrl_st2
);
6682 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp
);
6683 tmp
|= (AUDIO_ELD_VALID_A
<< (pipe
* 4));
6684 I915_WRITE(aud_cntrl_st2
, tmp
);
6685 tmp
= I915_READ(aud_cntrl_st2
);
6686 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp
);
6688 /* Enable HDMI mode */
6689 tmp
= I915_READ(aud_config
);
6690 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp
);
6691 /* clear N_programing_enable and N_value_index */
6692 tmp
&= ~(AUD_CONFIG_N_VALUE_INDEX
| AUD_CONFIG_N_PROG_ENABLE
);
6693 I915_WRITE(aud_config
, tmp
);
6695 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
6697 eldv
= AUDIO_ELD_VALID_A
<< (pipe
* 4);
6698 intel_crtc
->eld_vld
= true;
6700 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
6701 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6702 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6703 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
6705 I915_WRITE(aud_config
, 0);
6707 if (intel_eld_uptodate(connector
,
6708 aud_cntrl_st2
, eldv
,
6709 aud_cntl_st
, IBX_ELD_ADDRESS
,
6713 i
= I915_READ(aud_cntrl_st2
);
6715 I915_WRITE(aud_cntrl_st2
, i
);
6720 i
= I915_READ(aud_cntl_st
);
6721 i
&= ~IBX_ELD_ADDRESS
;
6722 I915_WRITE(aud_cntl_st
, i
);
6723 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
6724 DRM_DEBUG_DRIVER("port num:%d\n", i
);
6726 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
6727 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
6728 for (i
= 0; i
< len
; i
++)
6729 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
6731 i
= I915_READ(aud_cntrl_st2
);
6733 I915_WRITE(aud_cntrl_st2
, i
);
6737 static void ironlake_write_eld(struct drm_connector
*connector
,
6738 struct drm_crtc
*crtc
)
6740 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6741 uint8_t *eld
= connector
->eld
;
6749 int pipe
= to_intel_crtc(crtc
)->pipe
;
6751 if (HAS_PCH_IBX(connector
->dev
)) {
6752 hdmiw_hdmiedid
= IBX_HDMIW_HDMIEDID(pipe
);
6753 aud_config
= IBX_AUD_CFG(pipe
);
6754 aud_cntl_st
= IBX_AUD_CNTL_ST(pipe
);
6755 aud_cntrl_st2
= IBX_AUD_CNTL_ST2
;
6757 hdmiw_hdmiedid
= CPT_HDMIW_HDMIEDID(pipe
);
6758 aud_config
= CPT_AUD_CFG(pipe
);
6759 aud_cntl_st
= CPT_AUD_CNTL_ST(pipe
);
6760 aud_cntrl_st2
= CPT_AUD_CNTRL_ST2
;
6763 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
6765 i
= I915_READ(aud_cntl_st
);
6766 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
6768 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6769 /* operate blindly on all ports */
6770 eldv
= IBX_ELD_VALIDB
;
6771 eldv
|= IBX_ELD_VALIDB
<< 4;
6772 eldv
|= IBX_ELD_VALIDB
<< 8;
6774 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i
));
6775 eldv
= IBX_ELD_VALIDB
<< ((i
- 1) * 4);
6778 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
6779 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6780 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6781 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
6783 I915_WRITE(aud_config
, 0);
6785 if (intel_eld_uptodate(connector
,
6786 aud_cntrl_st2
, eldv
,
6787 aud_cntl_st
, IBX_ELD_ADDRESS
,
6791 i
= I915_READ(aud_cntrl_st2
);
6793 I915_WRITE(aud_cntrl_st2
, i
);
6798 i
= I915_READ(aud_cntl_st
);
6799 i
&= ~IBX_ELD_ADDRESS
;
6800 I915_WRITE(aud_cntl_st
, i
);
6802 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
6803 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
6804 for (i
= 0; i
< len
; i
++)
6805 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
6807 i
= I915_READ(aud_cntrl_st2
);
6809 I915_WRITE(aud_cntrl_st2
, i
);
6812 void intel_write_eld(struct drm_encoder
*encoder
,
6813 struct drm_display_mode
*mode
)
6815 struct drm_crtc
*crtc
= encoder
->crtc
;
6816 struct drm_connector
*connector
;
6817 struct drm_device
*dev
= encoder
->dev
;
6818 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6820 connector
= drm_select_eld(encoder
, mode
);
6824 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6826 drm_get_connector_name(connector
),
6827 connector
->encoder
->base
.id
,
6828 drm_get_encoder_name(connector
->encoder
));
6830 connector
->eld
[6] = drm_av_sync_delay(connector
, mode
) / 2;
6832 if (dev_priv
->display
.write_eld
)
6833 dev_priv
->display
.write_eld(connector
, crtc
);
6836 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6838 struct drm_device
*dev
= crtc
->dev
;
6839 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6840 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6841 bool visible
= base
!= 0;
6844 if (intel_crtc
->cursor_visible
== visible
)
6847 cntl
= I915_READ(_CURACNTR
);
6849 /* On these chipsets we can only modify the base whilst
6850 * the cursor is disabled.
6852 I915_WRITE(_CURABASE
, base
);
6854 cntl
&= ~(CURSOR_FORMAT_MASK
);
6855 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6856 cntl
|= CURSOR_ENABLE
|
6857 CURSOR_GAMMA_ENABLE
|
6860 cntl
&= ~(CURSOR_ENABLE
| CURSOR_GAMMA_ENABLE
);
6861 I915_WRITE(_CURACNTR
, cntl
);
6863 intel_crtc
->cursor_visible
= visible
;
6866 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6868 struct drm_device
*dev
= crtc
->dev
;
6869 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6870 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6871 int pipe
= intel_crtc
->pipe
;
6872 bool visible
= base
!= 0;
6874 if (intel_crtc
->cursor_visible
!= visible
) {
6875 uint32_t cntl
= I915_READ(CURCNTR(pipe
));
6877 cntl
&= ~(CURSOR_MODE
| MCURSOR_PIPE_SELECT
);
6878 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
6879 cntl
|= pipe
<< 28; /* Connect to correct pipe */
6881 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
6882 cntl
|= CURSOR_MODE_DISABLE
;
6884 I915_WRITE(CURCNTR(pipe
), cntl
);
6886 intel_crtc
->cursor_visible
= visible
;
6888 /* and commit changes on next vblank */
6889 I915_WRITE(CURBASE(pipe
), base
);
6892 static void ivb_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6894 struct drm_device
*dev
= crtc
->dev
;
6895 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6896 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6897 int pipe
= intel_crtc
->pipe
;
6898 bool visible
= base
!= 0;
6900 if (intel_crtc
->cursor_visible
!= visible
) {
6901 uint32_t cntl
= I915_READ(CURCNTR_IVB(pipe
));
6903 cntl
&= ~CURSOR_MODE
;
6904 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
6906 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
6907 cntl
|= CURSOR_MODE_DISABLE
;
6909 if (IS_HASWELL(dev
)) {
6910 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
6911 cntl
&= ~CURSOR_TRICKLE_FEED_DISABLE
;
6913 I915_WRITE(CURCNTR_IVB(pipe
), cntl
);
6915 intel_crtc
->cursor_visible
= visible
;
6917 /* and commit changes on next vblank */
6918 I915_WRITE(CURBASE_IVB(pipe
), base
);
6921 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6922 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
6925 struct drm_device
*dev
= crtc
->dev
;
6926 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6927 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6928 int pipe
= intel_crtc
->pipe
;
6929 int x
= intel_crtc
->cursor_x
;
6930 int y
= intel_crtc
->cursor_y
;
6931 u32 base
= 0, pos
= 0;
6935 base
= intel_crtc
->cursor_addr
;
6937 if (x
>= intel_crtc
->config
.pipe_src_w
)
6940 if (y
>= intel_crtc
->config
.pipe_src_h
)
6944 if (x
+ intel_crtc
->cursor_width
<= 0)
6947 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
6950 pos
|= x
<< CURSOR_X_SHIFT
;
6953 if (y
+ intel_crtc
->cursor_height
<= 0)
6956 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
6959 pos
|= y
<< CURSOR_Y_SHIFT
;
6961 visible
= base
!= 0;
6962 if (!visible
&& !intel_crtc
->cursor_visible
)
6965 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
6966 I915_WRITE(CURPOS_IVB(pipe
), pos
);
6967 ivb_update_cursor(crtc
, base
);
6969 I915_WRITE(CURPOS(pipe
), pos
);
6970 if (IS_845G(dev
) || IS_I865G(dev
))
6971 i845_update_cursor(crtc
, base
);
6973 i9xx_update_cursor(crtc
, base
);
6977 static int intel_crtc_cursor_set(struct drm_crtc
*crtc
,
6978 struct drm_file
*file
,
6980 uint32_t width
, uint32_t height
)
6982 struct drm_device
*dev
= crtc
->dev
;
6983 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6984 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6985 struct drm_i915_gem_object
*obj
;
6989 /* if we want to turn off the cursor ignore width and height */
6991 DRM_DEBUG_KMS("cursor off\n");
6994 mutex_lock(&dev
->struct_mutex
);
6998 /* Currently we only support 64x64 cursors */
6999 if (width
!= 64 || height
!= 64) {
7000 DRM_ERROR("we currently only support 64x64 cursors\n");
7004 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
7005 if (&obj
->base
== NULL
)
7008 if (obj
->base
.size
< width
* height
* 4) {
7009 DRM_ERROR("buffer is to small\n");
7014 /* we only need to pin inside GTT if cursor is non-phy */
7015 mutex_lock(&dev
->struct_mutex
);
7016 if (!dev_priv
->info
->cursor_needs_physical
) {
7019 if (obj
->tiling_mode
) {
7020 DRM_ERROR("cursor cannot be tiled\n");
7025 /* Note that the w/a also requires 2 PTE of padding following
7026 * the bo. We currently fill all unused PTE with the shadow
7027 * page and so we should always have valid PTE following the
7028 * cursor preventing the VT-d warning.
7031 if (need_vtd_wa(dev
))
7032 alignment
= 64*1024;
7034 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, NULL
);
7036 DRM_ERROR("failed to move cursor bo into the GTT\n");
7040 ret
= i915_gem_object_put_fence(obj
);
7042 DRM_ERROR("failed to release fence for cursor");
7046 addr
= i915_gem_obj_ggtt_offset(obj
);
7048 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
7049 ret
= i915_gem_attach_phys_object(dev
, obj
,
7050 (intel_crtc
->pipe
== 0) ? I915_GEM_PHYS_CURSOR_0
: I915_GEM_PHYS_CURSOR_1
,
7053 DRM_ERROR("failed to attach phys object\n");
7056 addr
= obj
->phys_obj
->handle
->busaddr
;
7060 I915_WRITE(CURSIZE
, (height
<< 12) | width
);
7063 if (intel_crtc
->cursor_bo
) {
7064 if (dev_priv
->info
->cursor_needs_physical
) {
7065 if (intel_crtc
->cursor_bo
!= obj
)
7066 i915_gem_detach_phys_object(dev
, intel_crtc
->cursor_bo
);
7068 i915_gem_object_unpin_from_display_plane(intel_crtc
->cursor_bo
);
7069 drm_gem_object_unreference(&intel_crtc
->cursor_bo
->base
);
7072 mutex_unlock(&dev
->struct_mutex
);
7074 intel_crtc
->cursor_addr
= addr
;
7075 intel_crtc
->cursor_bo
= obj
;
7076 intel_crtc
->cursor_width
= width
;
7077 intel_crtc
->cursor_height
= height
;
7079 if (intel_crtc
->active
)
7080 intel_crtc_update_cursor(crtc
, intel_crtc
->cursor_bo
!= NULL
);
7084 i915_gem_object_unpin_from_display_plane(obj
);
7086 mutex_unlock(&dev
->struct_mutex
);
7088 drm_gem_object_unreference_unlocked(&obj
->base
);
7092 static int intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
7094 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7096 intel_crtc
->cursor_x
= x
;
7097 intel_crtc
->cursor_y
= y
;
7099 if (intel_crtc
->active
)
7100 intel_crtc_update_cursor(crtc
, intel_crtc
->cursor_bo
!= NULL
);
7105 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
7106 u16
*blue
, uint32_t start
, uint32_t size
)
7108 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
7109 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7111 for (i
= start
; i
< end
; i
++) {
7112 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
7113 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
7114 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
7117 intel_crtc_load_lut(crtc
);
7120 /* VESA 640x480x72Hz mode to set on the pipe */
7121 static struct drm_display_mode load_detect_mode
= {
7122 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
7123 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
7126 static struct drm_framebuffer
*
7127 intel_framebuffer_create(struct drm_device
*dev
,
7128 struct drm_mode_fb_cmd2
*mode_cmd
,
7129 struct drm_i915_gem_object
*obj
)
7131 struct intel_framebuffer
*intel_fb
;
7134 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
7136 drm_gem_object_unreference_unlocked(&obj
->base
);
7137 return ERR_PTR(-ENOMEM
);
7140 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
7142 drm_gem_object_unreference_unlocked(&obj
->base
);
7144 return ERR_PTR(ret
);
7147 return &intel_fb
->base
;
7151 intel_framebuffer_pitch_for_width(int width
, int bpp
)
7153 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
7154 return ALIGN(pitch
, 64);
7158 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
7160 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
7161 return ALIGN(pitch
* mode
->vdisplay
, PAGE_SIZE
);
7164 static struct drm_framebuffer
*
7165 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
7166 struct drm_display_mode
*mode
,
7169 struct drm_i915_gem_object
*obj
;
7170 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
7172 obj
= i915_gem_alloc_object(dev
,
7173 intel_framebuffer_size_for_mode(mode
, bpp
));
7175 return ERR_PTR(-ENOMEM
);
7177 mode_cmd
.width
= mode
->hdisplay
;
7178 mode_cmd
.height
= mode
->vdisplay
;
7179 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
7181 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
7183 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
7186 static struct drm_framebuffer
*
7187 mode_fits_in_fbdev(struct drm_device
*dev
,
7188 struct drm_display_mode
*mode
)
7190 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7191 struct drm_i915_gem_object
*obj
;
7192 struct drm_framebuffer
*fb
;
7194 if (dev_priv
->fbdev
== NULL
)
7197 obj
= dev_priv
->fbdev
->ifb
.obj
;
7201 fb
= &dev_priv
->fbdev
->ifb
.base
;
7202 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
7203 fb
->bits_per_pixel
))
7206 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
7212 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
7213 struct drm_display_mode
*mode
,
7214 struct intel_load_detect_pipe
*old
)
7216 struct intel_crtc
*intel_crtc
;
7217 struct intel_encoder
*intel_encoder
=
7218 intel_attached_encoder(connector
);
7219 struct drm_crtc
*possible_crtc
;
7220 struct drm_encoder
*encoder
= &intel_encoder
->base
;
7221 struct drm_crtc
*crtc
= NULL
;
7222 struct drm_device
*dev
= encoder
->dev
;
7223 struct drm_framebuffer
*fb
;
7226 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7227 connector
->base
.id
, drm_get_connector_name(connector
),
7228 encoder
->base
.id
, drm_get_encoder_name(encoder
));
7231 * Algorithm gets a little messy:
7233 * - if the connector already has an assigned crtc, use it (but make
7234 * sure it's on first)
7236 * - try to find the first unused crtc that can drive this connector,
7237 * and use that if we find one
7240 /* See if we already have a CRTC for this connector */
7241 if (encoder
->crtc
) {
7242 crtc
= encoder
->crtc
;
7244 mutex_lock(&crtc
->mutex
);
7246 old
->dpms_mode
= connector
->dpms
;
7247 old
->load_detect_temp
= false;
7249 /* Make sure the crtc and connector are running */
7250 if (connector
->dpms
!= DRM_MODE_DPMS_ON
)
7251 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
7256 /* Find an unused one (if possible) */
7257 list_for_each_entry(possible_crtc
, &dev
->mode_config
.crtc_list
, head
) {
7259 if (!(encoder
->possible_crtcs
& (1 << i
)))
7261 if (!possible_crtc
->enabled
) {
7262 crtc
= possible_crtc
;
7268 * If we didn't find an unused CRTC, don't use any.
7271 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7275 mutex_lock(&crtc
->mutex
);
7276 intel_encoder
->new_crtc
= to_intel_crtc(crtc
);
7277 to_intel_connector(connector
)->new_encoder
= intel_encoder
;
7279 intel_crtc
= to_intel_crtc(crtc
);
7280 old
->dpms_mode
= connector
->dpms
;
7281 old
->load_detect_temp
= true;
7282 old
->release_fb
= NULL
;
7285 mode
= &load_detect_mode
;
7287 /* We need a framebuffer large enough to accommodate all accesses
7288 * that the plane may generate whilst we perform load detection.
7289 * We can not rely on the fbcon either being present (we get called
7290 * during its initialisation to detect all boot displays, or it may
7291 * not even exist) or that it is large enough to satisfy the
7294 fb
= mode_fits_in_fbdev(dev
, mode
);
7296 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7297 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
7298 old
->release_fb
= fb
;
7300 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7302 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7303 mutex_unlock(&crtc
->mutex
);
7307 if (intel_set_mode(crtc
, mode
, 0, 0, fb
)) {
7308 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7309 if (old
->release_fb
)
7310 old
->release_fb
->funcs
->destroy(old
->release_fb
);
7311 mutex_unlock(&crtc
->mutex
);
7315 /* let the connector get through one full cycle before testing */
7316 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
7320 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
7321 struct intel_load_detect_pipe
*old
)
7323 struct intel_encoder
*intel_encoder
=
7324 intel_attached_encoder(connector
);
7325 struct drm_encoder
*encoder
= &intel_encoder
->base
;
7326 struct drm_crtc
*crtc
= encoder
->crtc
;
7328 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7329 connector
->base
.id
, drm_get_connector_name(connector
),
7330 encoder
->base
.id
, drm_get_encoder_name(encoder
));
7332 if (old
->load_detect_temp
) {
7333 to_intel_connector(connector
)->new_encoder
= NULL
;
7334 intel_encoder
->new_crtc
= NULL
;
7335 intel_set_mode(crtc
, NULL
, 0, 0, NULL
);
7337 if (old
->release_fb
) {
7338 drm_framebuffer_unregister_private(old
->release_fb
);
7339 drm_framebuffer_unreference(old
->release_fb
);
7342 mutex_unlock(&crtc
->mutex
);
7346 /* Switch crtc and encoder back off if necessary */
7347 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
)
7348 connector
->funcs
->dpms(connector
, old
->dpms_mode
);
7350 mutex_unlock(&crtc
->mutex
);
7353 static int i9xx_pll_refclk(struct drm_device
*dev
,
7354 const struct intel_crtc_config
*pipe_config
)
7356 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7357 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
7359 if ((dpll
& PLL_REF_INPUT_MASK
) == PLLB_REF_INPUT_SPREADSPECTRUMIN
)
7360 return dev_priv
->vbt
.lvds_ssc_freq
* 1000;
7361 else if (HAS_PCH_SPLIT(dev
))
7363 else if (!IS_GEN2(dev
))
7369 /* Returns the clock of the currently programmed mode of the given pipe. */
7370 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
7371 struct intel_crtc_config
*pipe_config
)
7373 struct drm_device
*dev
= crtc
->base
.dev
;
7374 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7375 int pipe
= pipe_config
->cpu_transcoder
;
7376 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
7378 intel_clock_t clock
;
7379 int refclk
= i9xx_pll_refclk(dev
, pipe_config
);
7381 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
7382 fp
= pipe_config
->dpll_hw_state
.fp0
;
7384 fp
= pipe_config
->dpll_hw_state
.fp1
;
7386 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
7387 if (IS_PINEVIEW(dev
)) {
7388 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
7389 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
7391 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
7392 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
7395 if (!IS_GEN2(dev
)) {
7396 if (IS_PINEVIEW(dev
))
7397 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
7398 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
7400 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
7401 DPLL_FPA01_P1_POST_DIV_SHIFT
);
7403 switch (dpll
& DPLL_MODE_MASK
) {
7404 case DPLLB_MODE_DAC_SERIAL
:
7405 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
7408 case DPLLB_MODE_LVDS
:
7409 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
7413 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7414 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
7418 if (IS_PINEVIEW(dev
))
7419 pineview_clock(refclk
, &clock
);
7421 i9xx_clock(refclk
, &clock
);
7423 bool is_lvds
= (pipe
== 1) && (I915_READ(LVDS
) & LVDS_PORT_EN
);
7426 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
7427 DPLL_FPA01_P1_POST_DIV_SHIFT
);
7430 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
7433 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
7434 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
7436 if (dpll
& PLL_P2_DIVIDE_BY_4
)
7442 i9xx_clock(refclk
, &clock
);
7446 * This value includes pixel_multiplier. We will use
7447 * port_clock to compute adjusted_mode.clock in the
7448 * encoder's get_config() function.
7450 pipe_config
->port_clock
= clock
.dot
;
7453 int intel_dotclock_calculate(int link_freq
,
7454 const struct intel_link_m_n
*m_n
)
7457 * The calculation for the data clock is:
7458 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
7459 * But we want to avoid losing precison if possible, so:
7460 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
7462 * and the link clock is simpler:
7463 * link_clock = (m * link_clock) / n
7469 return div_u64((u64
)m_n
->link_m
* link_freq
, m_n
->link_n
);
7472 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
7473 struct intel_crtc_config
*pipe_config
)
7475 struct drm_device
*dev
= crtc
->base
.dev
;
7477 /* read out port_clock from the DPLL */
7478 i9xx_crtc_clock_get(crtc
, pipe_config
);
7481 * This value does not include pixel_multiplier.
7482 * We will check that port_clock and adjusted_mode.clock
7483 * agree once we know their relationship in the encoder's
7484 * get_config() function.
7486 pipe_config
->adjusted_mode
.clock
=
7487 intel_dotclock_calculate(intel_fdi_link_freq(dev
) * 10000,
7488 &pipe_config
->fdi_m_n
);
7491 /** Returns the currently programmed mode of the given pipe. */
7492 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
7493 struct drm_crtc
*crtc
)
7495 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7496 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7497 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
7498 struct drm_display_mode
*mode
;
7499 struct intel_crtc_config pipe_config
;
7500 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
7501 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
7502 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
7503 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
7504 enum pipe pipe
= intel_crtc
->pipe
;
7506 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
7511 * Construct a pipe_config sufficient for getting the clock info
7512 * back out of crtc_clock_get.
7514 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7515 * to use a real value here instead.
7517 pipe_config
.cpu_transcoder
= (enum transcoder
) pipe
;
7518 pipe_config
.pixel_multiplier
= 1;
7519 pipe_config
.dpll_hw_state
.dpll
= I915_READ(DPLL(pipe
));
7520 pipe_config
.dpll_hw_state
.fp0
= I915_READ(FP0(pipe
));
7521 pipe_config
.dpll_hw_state
.fp1
= I915_READ(FP1(pipe
));
7522 i9xx_crtc_clock_get(intel_crtc
, &pipe_config
);
7524 mode
->clock
= pipe_config
.port_clock
/ pipe_config
.pixel_multiplier
;
7525 mode
->hdisplay
= (htot
& 0xffff) + 1;
7526 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
7527 mode
->hsync_start
= (hsync
& 0xffff) + 1;
7528 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
7529 mode
->vdisplay
= (vtot
& 0xffff) + 1;
7530 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
7531 mode
->vsync_start
= (vsync
& 0xffff) + 1;
7532 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
7534 drm_mode_set_name(mode
);
7539 static void intel_increase_pllclock(struct drm_crtc
*crtc
)
7541 struct drm_device
*dev
= crtc
->dev
;
7542 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7543 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7544 int pipe
= intel_crtc
->pipe
;
7545 int dpll_reg
= DPLL(pipe
);
7548 if (HAS_PCH_SPLIT(dev
))
7551 if (!dev_priv
->lvds_downclock_avail
)
7554 dpll
= I915_READ(dpll_reg
);
7555 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
7556 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7558 assert_panel_unlocked(dev_priv
, pipe
);
7560 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
7561 I915_WRITE(dpll_reg
, dpll
);
7562 intel_wait_for_vblank(dev
, pipe
);
7564 dpll
= I915_READ(dpll_reg
);
7565 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
7566 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7570 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
7572 struct drm_device
*dev
= crtc
->dev
;
7573 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7574 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7576 if (HAS_PCH_SPLIT(dev
))
7579 if (!dev_priv
->lvds_downclock_avail
)
7583 * Since this is called by a timer, we should never get here in
7586 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
7587 int pipe
= intel_crtc
->pipe
;
7588 int dpll_reg
= DPLL(pipe
);
7591 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7593 assert_panel_unlocked(dev_priv
, pipe
);
7595 dpll
= I915_READ(dpll_reg
);
7596 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
7597 I915_WRITE(dpll_reg
, dpll
);
7598 intel_wait_for_vblank(dev
, pipe
);
7599 dpll
= I915_READ(dpll_reg
);
7600 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
7601 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7606 void intel_mark_busy(struct drm_device
*dev
)
7608 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7610 hsw_package_c8_gpu_busy(dev_priv
);
7611 i915_update_gfx_val(dev_priv
);
7614 void intel_mark_idle(struct drm_device
*dev
)
7616 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7617 struct drm_crtc
*crtc
;
7619 hsw_package_c8_gpu_idle(dev_priv
);
7621 if (!i915_powersave
)
7624 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
7628 intel_decrease_pllclock(crtc
);
7632 void intel_mark_fb_busy(struct drm_i915_gem_object
*obj
,
7633 struct intel_ring_buffer
*ring
)
7635 struct drm_device
*dev
= obj
->base
.dev
;
7636 struct drm_crtc
*crtc
;
7638 if (!i915_powersave
)
7641 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
7645 if (to_intel_framebuffer(crtc
->fb
)->obj
!= obj
)
7648 intel_increase_pllclock(crtc
);
7649 if (ring
&& intel_fbc_enabled(dev
))
7650 ring
->fbc_dirty
= true;
7654 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
7656 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7657 struct drm_device
*dev
= crtc
->dev
;
7658 struct intel_unpin_work
*work
;
7659 unsigned long flags
;
7661 spin_lock_irqsave(&dev
->event_lock
, flags
);
7662 work
= intel_crtc
->unpin_work
;
7663 intel_crtc
->unpin_work
= NULL
;
7664 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7667 cancel_work_sync(&work
->work
);
7671 intel_crtc_cursor_set(crtc
, NULL
, 0, 0, 0);
7673 drm_crtc_cleanup(crtc
);
7678 static void intel_unpin_work_fn(struct work_struct
*__work
)
7680 struct intel_unpin_work
*work
=
7681 container_of(__work
, struct intel_unpin_work
, work
);
7682 struct drm_device
*dev
= work
->crtc
->dev
;
7684 mutex_lock(&dev
->struct_mutex
);
7685 intel_unpin_fb_obj(work
->old_fb_obj
);
7686 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
7687 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
7689 intel_update_fbc(dev
);
7690 mutex_unlock(&dev
->struct_mutex
);
7692 BUG_ON(atomic_read(&to_intel_crtc(work
->crtc
)->unpin_work_count
) == 0);
7693 atomic_dec(&to_intel_crtc(work
->crtc
)->unpin_work_count
);
7698 static void do_intel_finish_page_flip(struct drm_device
*dev
,
7699 struct drm_crtc
*crtc
)
7701 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7702 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7703 struct intel_unpin_work
*work
;
7704 unsigned long flags
;
7706 /* Ignore early vblank irqs */
7707 if (intel_crtc
== NULL
)
7710 spin_lock_irqsave(&dev
->event_lock
, flags
);
7711 work
= intel_crtc
->unpin_work
;
7713 /* Ensure we don't miss a work->pending update ... */
7716 if (work
== NULL
|| atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
7717 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7721 /* and that the unpin work is consistent wrt ->pending. */
7724 intel_crtc
->unpin_work
= NULL
;
7727 drm_send_vblank_event(dev
, intel_crtc
->pipe
, work
->event
);
7729 drm_vblank_put(dev
, intel_crtc
->pipe
);
7731 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7733 wake_up_all(&dev_priv
->pending_flip_queue
);
7735 queue_work(dev_priv
->wq
, &work
->work
);
7737 trace_i915_flip_complete(intel_crtc
->plane
, work
->pending_flip_obj
);
7740 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
7742 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7743 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
7745 do_intel_finish_page_flip(dev
, crtc
);
7748 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
7750 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7751 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
7753 do_intel_finish_page_flip(dev
, crtc
);
7756 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
7758 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7759 struct intel_crtc
*intel_crtc
=
7760 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
7761 unsigned long flags
;
7763 /* NB: An MMIO update of the plane base pointer will also
7764 * generate a page-flip completion irq, i.e. every modeset
7765 * is also accompanied by a spurious intel_prepare_page_flip().
7767 spin_lock_irqsave(&dev
->event_lock
, flags
);
7768 if (intel_crtc
->unpin_work
)
7769 atomic_inc_not_zero(&intel_crtc
->unpin_work
->pending
);
7770 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7773 inline static void intel_mark_page_flip_active(struct intel_crtc
*intel_crtc
)
7775 /* Ensure that the work item is consistent when activating it ... */
7777 atomic_set(&intel_crtc
->unpin_work
->pending
, INTEL_FLIP_PENDING
);
7778 /* and that it is marked active as soon as the irq could fire. */
7782 static int intel_gen2_queue_flip(struct drm_device
*dev
,
7783 struct drm_crtc
*crtc
,
7784 struct drm_framebuffer
*fb
,
7785 struct drm_i915_gem_object
*obj
,
7788 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7789 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7791 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7794 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7798 ret
= intel_ring_begin(ring
, 6);
7802 /* Can't queue multiple flips, so wait for the previous
7803 * one to finish before executing the next.
7805 if (intel_crtc
->plane
)
7806 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
7808 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
7809 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
7810 intel_ring_emit(ring
, MI_NOOP
);
7811 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
7812 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7813 intel_ring_emit(ring
, fb
->pitches
[0]);
7814 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
7815 intel_ring_emit(ring
, 0); /* aux display base address, unused */
7817 intel_mark_page_flip_active(intel_crtc
);
7818 __intel_ring_advance(ring
);
7822 intel_unpin_fb_obj(obj
);
7827 static int intel_gen3_queue_flip(struct drm_device
*dev
,
7828 struct drm_crtc
*crtc
,
7829 struct drm_framebuffer
*fb
,
7830 struct drm_i915_gem_object
*obj
,
7833 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7834 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7836 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7839 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7843 ret
= intel_ring_begin(ring
, 6);
7847 if (intel_crtc
->plane
)
7848 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
7850 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
7851 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
7852 intel_ring_emit(ring
, MI_NOOP
);
7853 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
7854 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7855 intel_ring_emit(ring
, fb
->pitches
[0]);
7856 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
7857 intel_ring_emit(ring
, MI_NOOP
);
7859 intel_mark_page_flip_active(intel_crtc
);
7860 __intel_ring_advance(ring
);
7864 intel_unpin_fb_obj(obj
);
7869 static int intel_gen4_queue_flip(struct drm_device
*dev
,
7870 struct drm_crtc
*crtc
,
7871 struct drm_framebuffer
*fb
,
7872 struct drm_i915_gem_object
*obj
,
7875 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7876 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7877 uint32_t pf
, pipesrc
;
7878 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7881 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7885 ret
= intel_ring_begin(ring
, 4);
7889 /* i965+ uses the linear or tiled offsets from the
7890 * Display Registers (which do not change across a page-flip)
7891 * so we need only reprogram the base address.
7893 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
7894 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7895 intel_ring_emit(ring
, fb
->pitches
[0]);
7896 intel_ring_emit(ring
,
7897 (i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
) |
7900 /* XXX Enabling the panel-fitter across page-flip is so far
7901 * untested on non-native modes, so ignore it for now.
7902 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7905 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
7906 intel_ring_emit(ring
, pf
| pipesrc
);
7908 intel_mark_page_flip_active(intel_crtc
);
7909 __intel_ring_advance(ring
);
7913 intel_unpin_fb_obj(obj
);
7918 static int intel_gen6_queue_flip(struct drm_device
*dev
,
7919 struct drm_crtc
*crtc
,
7920 struct drm_framebuffer
*fb
,
7921 struct drm_i915_gem_object
*obj
,
7924 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7925 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7926 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7927 uint32_t pf
, pipesrc
;
7930 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7934 ret
= intel_ring_begin(ring
, 4);
7938 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
7939 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7940 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
7941 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
7943 /* Contrary to the suggestions in the documentation,
7944 * "Enable Panel Fitter" does not seem to be required when page
7945 * flipping with a non-native mode, and worse causes a normal
7947 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7950 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
7951 intel_ring_emit(ring
, pf
| pipesrc
);
7953 intel_mark_page_flip_active(intel_crtc
);
7954 __intel_ring_advance(ring
);
7958 intel_unpin_fb_obj(obj
);
7963 static int intel_gen7_queue_flip(struct drm_device
*dev
,
7964 struct drm_crtc
*crtc
,
7965 struct drm_framebuffer
*fb
,
7966 struct drm_i915_gem_object
*obj
,
7969 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7970 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7971 struct intel_ring_buffer
*ring
;
7972 uint32_t plane_bit
= 0;
7976 if (IS_VALLEYVIEW(dev
) || ring
== NULL
|| ring
->id
!= RCS
)
7977 ring
= &dev_priv
->ring
[BCS
];
7979 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7983 switch(intel_crtc
->plane
) {
7985 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
7988 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
7991 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
7994 WARN_ONCE(1, "unknown plane in flip command\n");
8000 if (ring
->id
== RCS
)
8003 ret
= intel_ring_begin(ring
, len
);
8007 /* Unmask the flip-done completion message. Note that the bspec says that
8008 * we should do this for both the BCS and RCS, and that we must not unmask
8009 * more than one flip event at any time (or ensure that one flip message
8010 * can be sent by waiting for flip-done prior to queueing new flips).
8011 * Experimentation says that BCS works despite DERRMR masking all
8012 * flip-done completion events and that unmasking all planes at once
8013 * for the RCS also doesn't appear to drop events. Setting the DERRMR
8014 * to zero does lead to lockups within MI_DISPLAY_FLIP.
8016 if (ring
->id
== RCS
) {
8017 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
8018 intel_ring_emit(ring
, DERRMR
);
8019 intel_ring_emit(ring
, ~(DERRMR_PIPEA_PRI_FLIP_DONE
|
8020 DERRMR_PIPEB_PRI_FLIP_DONE
|
8021 DERRMR_PIPEC_PRI_FLIP_DONE
));
8022 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM(1));
8023 intel_ring_emit(ring
, DERRMR
);
8024 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
+ 256);
8027 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
8028 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
8029 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
8030 intel_ring_emit(ring
, (MI_NOOP
));
8032 intel_mark_page_flip_active(intel_crtc
);
8033 __intel_ring_advance(ring
);
8037 intel_unpin_fb_obj(obj
);
8042 static int intel_default_queue_flip(struct drm_device
*dev
,
8043 struct drm_crtc
*crtc
,
8044 struct drm_framebuffer
*fb
,
8045 struct drm_i915_gem_object
*obj
,
8051 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
8052 struct drm_framebuffer
*fb
,
8053 struct drm_pending_vblank_event
*event
,
8054 uint32_t page_flip_flags
)
8056 struct drm_device
*dev
= crtc
->dev
;
8057 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8058 struct drm_framebuffer
*old_fb
= crtc
->fb
;
8059 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(fb
)->obj
;
8060 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8061 struct intel_unpin_work
*work
;
8062 unsigned long flags
;
8065 /* Can't change pixel format via MI display flips. */
8066 if (fb
->pixel_format
!= crtc
->fb
->pixel_format
)
8070 * TILEOFF/LINOFF registers can't be changed via MI display flips.
8071 * Note that pitch changes could also affect these register.
8073 if (INTEL_INFO(dev
)->gen
> 3 &&
8074 (fb
->offsets
[0] != crtc
->fb
->offsets
[0] ||
8075 fb
->pitches
[0] != crtc
->fb
->pitches
[0]))
8078 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
8082 work
->event
= event
;
8084 work
->old_fb_obj
= to_intel_framebuffer(old_fb
)->obj
;
8085 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
8087 ret
= drm_vblank_get(dev
, intel_crtc
->pipe
);
8091 /* We borrow the event spin lock for protecting unpin_work */
8092 spin_lock_irqsave(&dev
->event_lock
, flags
);
8093 if (intel_crtc
->unpin_work
) {
8094 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
8096 drm_vblank_put(dev
, intel_crtc
->pipe
);
8098 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
8101 intel_crtc
->unpin_work
= work
;
8102 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
8104 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
8105 flush_workqueue(dev_priv
->wq
);
8107 ret
= i915_mutex_lock_interruptible(dev
);
8111 /* Reference the objects for the scheduled work. */
8112 drm_gem_object_reference(&work
->old_fb_obj
->base
);
8113 drm_gem_object_reference(&obj
->base
);
8117 work
->pending_flip_obj
= obj
;
8119 work
->enable_stall_check
= true;
8121 atomic_inc(&intel_crtc
->unpin_work_count
);
8122 intel_crtc
->reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
8124 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
, page_flip_flags
);
8126 goto cleanup_pending
;
8128 intel_disable_fbc(dev
);
8129 intel_mark_fb_busy(obj
, NULL
);
8130 mutex_unlock(&dev
->struct_mutex
);
8132 trace_i915_flip_request(intel_crtc
->plane
, obj
);
8137 atomic_dec(&intel_crtc
->unpin_work_count
);
8139 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
8140 drm_gem_object_unreference(&obj
->base
);
8141 mutex_unlock(&dev
->struct_mutex
);
8144 spin_lock_irqsave(&dev
->event_lock
, flags
);
8145 intel_crtc
->unpin_work
= NULL
;
8146 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
8148 drm_vblank_put(dev
, intel_crtc
->pipe
);
8155 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
8156 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
8157 .load_lut
= intel_crtc_load_lut
,
8160 static bool intel_encoder_crtc_ok(struct drm_encoder
*encoder
,
8161 struct drm_crtc
*crtc
)
8163 struct drm_device
*dev
;
8164 struct drm_crtc
*tmp
;
8167 WARN(!crtc
, "checking null crtc?\n");
8171 list_for_each_entry(tmp
, &dev
->mode_config
.crtc_list
, head
) {
8177 if (encoder
->possible_crtcs
& crtc_mask
)
8183 * intel_modeset_update_staged_output_state
8185 * Updates the staged output configuration state, e.g. after we've read out the
8188 static void intel_modeset_update_staged_output_state(struct drm_device
*dev
)
8190 struct intel_encoder
*encoder
;
8191 struct intel_connector
*connector
;
8193 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8195 connector
->new_encoder
=
8196 to_intel_encoder(connector
->base
.encoder
);
8199 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8202 to_intel_crtc(encoder
->base
.crtc
);
8207 * intel_modeset_commit_output_state
8209 * This function copies the stage display pipe configuration to the real one.
8211 static void intel_modeset_commit_output_state(struct drm_device
*dev
)
8213 struct intel_encoder
*encoder
;
8214 struct intel_connector
*connector
;
8216 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8218 connector
->base
.encoder
= &connector
->new_encoder
->base
;
8221 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8223 encoder
->base
.crtc
= &encoder
->new_crtc
->base
;
8228 connected_sink_compute_bpp(struct intel_connector
* connector
,
8229 struct intel_crtc_config
*pipe_config
)
8231 int bpp
= pipe_config
->pipe_bpp
;
8233 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8234 connector
->base
.base
.id
,
8235 drm_get_connector_name(&connector
->base
));
8237 /* Don't use an invalid EDID bpc value */
8238 if (connector
->base
.display_info
.bpc
&&
8239 connector
->base
.display_info
.bpc
* 3 < bpp
) {
8240 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8241 bpp
, connector
->base
.display_info
.bpc
*3);
8242 pipe_config
->pipe_bpp
= connector
->base
.display_info
.bpc
*3;
8245 /* Clamp bpp to 8 on screens without EDID 1.4 */
8246 if (connector
->base
.display_info
.bpc
== 0 && bpp
> 24) {
8247 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8249 pipe_config
->pipe_bpp
= 24;
8254 compute_baseline_pipe_bpp(struct intel_crtc
*crtc
,
8255 struct drm_framebuffer
*fb
,
8256 struct intel_crtc_config
*pipe_config
)
8258 struct drm_device
*dev
= crtc
->base
.dev
;
8259 struct intel_connector
*connector
;
8262 switch (fb
->pixel_format
) {
8264 bpp
= 8*3; /* since we go through a colormap */
8266 case DRM_FORMAT_XRGB1555
:
8267 case DRM_FORMAT_ARGB1555
:
8268 /* checked in intel_framebuffer_init already */
8269 if (WARN_ON(INTEL_INFO(dev
)->gen
> 3))
8271 case DRM_FORMAT_RGB565
:
8272 bpp
= 6*3; /* min is 18bpp */
8274 case DRM_FORMAT_XBGR8888
:
8275 case DRM_FORMAT_ABGR8888
:
8276 /* checked in intel_framebuffer_init already */
8277 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
8279 case DRM_FORMAT_XRGB8888
:
8280 case DRM_FORMAT_ARGB8888
:
8283 case DRM_FORMAT_XRGB2101010
:
8284 case DRM_FORMAT_ARGB2101010
:
8285 case DRM_FORMAT_XBGR2101010
:
8286 case DRM_FORMAT_ABGR2101010
:
8287 /* checked in intel_framebuffer_init already */
8288 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
8292 /* TODO: gen4+ supports 16 bpc floating point, too. */
8294 DRM_DEBUG_KMS("unsupported depth\n");
8298 pipe_config
->pipe_bpp
= bpp
;
8300 /* Clamp display bpp to EDID value */
8301 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8303 if (!connector
->new_encoder
||
8304 connector
->new_encoder
->new_crtc
!= crtc
)
8307 connected_sink_compute_bpp(connector
, pipe_config
);
8313 static void intel_dump_crtc_timings(const struct drm_display_mode
*mode
)
8315 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
8316 "type: 0x%x flags: 0x%x\n",
8318 mode
->crtc_hdisplay
, mode
->crtc_hsync_start
,
8319 mode
->crtc_hsync_end
, mode
->crtc_htotal
,
8320 mode
->crtc_vdisplay
, mode
->crtc_vsync_start
,
8321 mode
->crtc_vsync_end
, mode
->crtc_vtotal
, mode
->type
, mode
->flags
);
8324 static void intel_dump_pipe_config(struct intel_crtc
*crtc
,
8325 struct intel_crtc_config
*pipe_config
,
8326 const char *context
)
8328 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc
->base
.base
.id
,
8329 context
, pipe_name(crtc
->pipe
));
8331 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config
->cpu_transcoder
));
8332 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8333 pipe_config
->pipe_bpp
, pipe_config
->dither
);
8334 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8335 pipe_config
->has_pch_encoder
,
8336 pipe_config
->fdi_lanes
,
8337 pipe_config
->fdi_m_n
.gmch_m
, pipe_config
->fdi_m_n
.gmch_n
,
8338 pipe_config
->fdi_m_n
.link_m
, pipe_config
->fdi_m_n
.link_n
,
8339 pipe_config
->fdi_m_n
.tu
);
8340 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8341 pipe_config
->has_dp_encoder
,
8342 pipe_config
->dp_m_n
.gmch_m
, pipe_config
->dp_m_n
.gmch_n
,
8343 pipe_config
->dp_m_n
.link_m
, pipe_config
->dp_m_n
.link_n
,
8344 pipe_config
->dp_m_n
.tu
);
8345 DRM_DEBUG_KMS("requested mode:\n");
8346 drm_mode_debug_printmodeline(&pipe_config
->requested_mode
);
8347 DRM_DEBUG_KMS("adjusted mode:\n");
8348 drm_mode_debug_printmodeline(&pipe_config
->adjusted_mode
);
8349 intel_dump_crtc_timings(&pipe_config
->adjusted_mode
);
8350 DRM_DEBUG_KMS("port clock: %d\n", pipe_config
->port_clock
);
8351 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8352 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
);
8353 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8354 pipe_config
->gmch_pfit
.control
,
8355 pipe_config
->gmch_pfit
.pgm_ratios
,
8356 pipe_config
->gmch_pfit
.lvds_border_bits
);
8357 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
8358 pipe_config
->pch_pfit
.pos
,
8359 pipe_config
->pch_pfit
.size
,
8360 pipe_config
->pch_pfit
.enabled
? "enabled" : "disabled");
8361 DRM_DEBUG_KMS("ips: %i\n", pipe_config
->ips_enabled
);
8362 DRM_DEBUG_KMS("double wide: %i\n", pipe_config
->double_wide
);
8365 static bool check_encoder_cloning(struct drm_crtc
*crtc
)
8367 int num_encoders
= 0;
8368 bool uncloneable_encoders
= false;
8369 struct intel_encoder
*encoder
;
8371 list_for_each_entry(encoder
, &crtc
->dev
->mode_config
.encoder_list
,
8373 if (&encoder
->new_crtc
->base
!= crtc
)
8377 if (!encoder
->cloneable
)
8378 uncloneable_encoders
= true;
8381 return !(num_encoders
> 1 && uncloneable_encoders
);
8384 static struct intel_crtc_config
*
8385 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
8386 struct drm_framebuffer
*fb
,
8387 struct drm_display_mode
*mode
)
8389 struct drm_device
*dev
= crtc
->dev
;
8390 struct intel_encoder
*encoder
;
8391 struct intel_crtc_config
*pipe_config
;
8392 int plane_bpp
, ret
= -EINVAL
;
8395 if (!check_encoder_cloning(crtc
)) {
8396 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8397 return ERR_PTR(-EINVAL
);
8400 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
8402 return ERR_PTR(-ENOMEM
);
8404 drm_mode_copy(&pipe_config
->adjusted_mode
, mode
);
8405 drm_mode_copy(&pipe_config
->requested_mode
, mode
);
8407 pipe_config
->pipe_src_w
= mode
->hdisplay
;
8408 pipe_config
->pipe_src_h
= mode
->vdisplay
;
8410 pipe_config
->cpu_transcoder
=
8411 (enum transcoder
) to_intel_crtc(crtc
)->pipe
;
8412 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
8415 * Sanitize sync polarity flags based on requested ones. If neither
8416 * positive or negative polarity is requested, treat this as meaning
8417 * negative polarity.
8419 if (!(pipe_config
->adjusted_mode
.flags
&
8420 (DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NHSYNC
)))
8421 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
8423 if (!(pipe_config
->adjusted_mode
.flags
&
8424 (DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_NVSYNC
)))
8425 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
8427 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8428 * plane pixel format and any sink constraints into account. Returns the
8429 * source plane bpp so that dithering can be selected on mismatches
8430 * after encoders and crtc also have had their say. */
8431 plane_bpp
= compute_baseline_pipe_bpp(to_intel_crtc(crtc
),
8437 /* Ensure the port clock defaults are reset when retrying. */
8438 pipe_config
->port_clock
= 0;
8439 pipe_config
->pixel_multiplier
= 1;
8441 /* Fill in default crtc timings, allow encoders to overwrite them. */
8442 drm_mode_set_crtcinfo(&pipe_config
->adjusted_mode
, 0);
8444 /* Pass our mode to the connectors and the CRTC to give them a chance to
8445 * adjust it according to limitations or connector properties, and also
8446 * a chance to reject the mode entirely.
8448 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8451 if (&encoder
->new_crtc
->base
!= crtc
)
8454 if (!(encoder
->compute_config(encoder
, pipe_config
))) {
8455 DRM_DEBUG_KMS("Encoder config failure\n");
8460 /* Set default port clock if not overwritten by the encoder. Needs to be
8461 * done afterwards in case the encoder adjusts the mode. */
8462 if (!pipe_config
->port_clock
)
8463 pipe_config
->port_clock
= pipe_config
->adjusted_mode
.clock
*
8464 pipe_config
->pixel_multiplier
;
8466 ret
= intel_crtc_compute_config(to_intel_crtc(crtc
), pipe_config
);
8468 DRM_DEBUG_KMS("CRTC fixup failed\n");
8473 if (WARN(!retry
, "loop in pipe configuration computation\n")) {
8478 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8483 pipe_config
->dither
= pipe_config
->pipe_bpp
!= plane_bpp
;
8484 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8485 plane_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
8490 return ERR_PTR(ret
);
8493 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
8494 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8496 intel_modeset_affected_pipes(struct drm_crtc
*crtc
, unsigned *modeset_pipes
,
8497 unsigned *prepare_pipes
, unsigned *disable_pipes
)
8499 struct intel_crtc
*intel_crtc
;
8500 struct drm_device
*dev
= crtc
->dev
;
8501 struct intel_encoder
*encoder
;
8502 struct intel_connector
*connector
;
8503 struct drm_crtc
*tmp_crtc
;
8505 *disable_pipes
= *modeset_pipes
= *prepare_pipes
= 0;
8507 /* Check which crtcs have changed outputs connected to them, these need
8508 * to be part of the prepare_pipes mask. We don't (yet) support global
8509 * modeset across multiple crtcs, so modeset_pipes will only have one
8510 * bit set at most. */
8511 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8513 if (connector
->base
.encoder
== &connector
->new_encoder
->base
)
8516 if (connector
->base
.encoder
) {
8517 tmp_crtc
= connector
->base
.encoder
->crtc
;
8519 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
8522 if (connector
->new_encoder
)
8524 1 << connector
->new_encoder
->new_crtc
->pipe
;
8527 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8529 if (encoder
->base
.crtc
== &encoder
->new_crtc
->base
)
8532 if (encoder
->base
.crtc
) {
8533 tmp_crtc
= encoder
->base
.crtc
;
8535 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
8538 if (encoder
->new_crtc
)
8539 *prepare_pipes
|= 1 << encoder
->new_crtc
->pipe
;
8542 /* Check for any pipes that will be fully disabled ... */
8543 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
8547 /* Don't try to disable disabled crtcs. */
8548 if (!intel_crtc
->base
.enabled
)
8551 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8553 if (encoder
->new_crtc
== intel_crtc
)
8558 *disable_pipes
|= 1 << intel_crtc
->pipe
;
8562 /* set_mode is also used to update properties on life display pipes. */
8563 intel_crtc
= to_intel_crtc(crtc
);
8565 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
8568 * For simplicity do a full modeset on any pipe where the output routing
8569 * changed. We could be more clever, but that would require us to be
8570 * more careful with calling the relevant encoder->mode_set functions.
8573 *modeset_pipes
= *prepare_pipes
;
8575 /* ... and mask these out. */
8576 *modeset_pipes
&= ~(*disable_pipes
);
8577 *prepare_pipes
&= ~(*disable_pipes
);
8580 * HACK: We don't (yet) fully support global modesets. intel_set_config
8581 * obies this rule, but the modeset restore mode of
8582 * intel_modeset_setup_hw_state does not.
8584 *modeset_pipes
&= 1 << intel_crtc
->pipe
;
8585 *prepare_pipes
&= 1 << intel_crtc
->pipe
;
8587 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8588 *modeset_pipes
, *prepare_pipes
, *disable_pipes
);
8591 static bool intel_crtc_in_use(struct drm_crtc
*crtc
)
8593 struct drm_encoder
*encoder
;
8594 struct drm_device
*dev
= crtc
->dev
;
8596 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
)
8597 if (encoder
->crtc
== crtc
)
8604 intel_modeset_update_state(struct drm_device
*dev
, unsigned prepare_pipes
)
8606 struct intel_encoder
*intel_encoder
;
8607 struct intel_crtc
*intel_crtc
;
8608 struct drm_connector
*connector
;
8610 list_for_each_entry(intel_encoder
, &dev
->mode_config
.encoder_list
,
8612 if (!intel_encoder
->base
.crtc
)
8615 intel_crtc
= to_intel_crtc(intel_encoder
->base
.crtc
);
8617 if (prepare_pipes
& (1 << intel_crtc
->pipe
))
8618 intel_encoder
->connectors_active
= false;
8621 intel_modeset_commit_output_state(dev
);
8623 /* Update computed state. */
8624 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
8626 intel_crtc
->base
.enabled
= intel_crtc_in_use(&intel_crtc
->base
);
8629 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
8630 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
8633 intel_crtc
= to_intel_crtc(connector
->encoder
->crtc
);
8635 if (prepare_pipes
& (1 << intel_crtc
->pipe
)) {
8636 struct drm_property
*dpms_property
=
8637 dev
->mode_config
.dpms_property
;
8639 connector
->dpms
= DRM_MODE_DPMS_ON
;
8640 drm_object_property_set_value(&connector
->base
,
8644 intel_encoder
= to_intel_encoder(connector
->encoder
);
8645 intel_encoder
->connectors_active
= true;
8651 static bool intel_fuzzy_clock_check(int clock1
, int clock2
)
8655 if (clock1
== clock2
)
8658 if (!clock1
|| !clock2
)
8661 diff
= abs(clock1
- clock2
);
8663 if (((((diff
+ clock1
+ clock2
) * 100)) / (clock1
+ clock2
)) < 105)
8669 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8670 list_for_each_entry((intel_crtc), \
8671 &(dev)->mode_config.crtc_list, \
8673 if (mask & (1 <<(intel_crtc)->pipe))
8676 intel_pipe_config_compare(struct drm_device
*dev
,
8677 struct intel_crtc_config
*current_config
,
8678 struct intel_crtc_config
*pipe_config
)
8680 #define PIPE_CONF_CHECK_X(name) \
8681 if (current_config->name != pipe_config->name) { \
8682 DRM_ERROR("mismatch in " #name " " \
8683 "(expected 0x%08x, found 0x%08x)\n", \
8684 current_config->name, \
8685 pipe_config->name); \
8689 #define PIPE_CONF_CHECK_I(name) \
8690 if (current_config->name != pipe_config->name) { \
8691 DRM_ERROR("mismatch in " #name " " \
8692 "(expected %i, found %i)\n", \
8693 current_config->name, \
8694 pipe_config->name); \
8698 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
8699 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8700 DRM_ERROR("mismatch in " #name "(" #mask ") " \
8701 "(expected %i, found %i)\n", \
8702 current_config->name & (mask), \
8703 pipe_config->name & (mask)); \
8707 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
8708 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
8709 DRM_ERROR("mismatch in " #name " " \
8710 "(expected %i, found %i)\n", \
8711 current_config->name, \
8712 pipe_config->name); \
8716 #define PIPE_CONF_QUIRK(quirk) \
8717 ((current_config->quirks | pipe_config->quirks) & (quirk))
8719 PIPE_CONF_CHECK_I(cpu_transcoder
);
8721 PIPE_CONF_CHECK_I(has_pch_encoder
);
8722 PIPE_CONF_CHECK_I(fdi_lanes
);
8723 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_m
);
8724 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_n
);
8725 PIPE_CONF_CHECK_I(fdi_m_n
.link_m
);
8726 PIPE_CONF_CHECK_I(fdi_m_n
.link_n
);
8727 PIPE_CONF_CHECK_I(fdi_m_n
.tu
);
8729 PIPE_CONF_CHECK_I(has_dp_encoder
);
8730 PIPE_CONF_CHECK_I(dp_m_n
.gmch_m
);
8731 PIPE_CONF_CHECK_I(dp_m_n
.gmch_n
);
8732 PIPE_CONF_CHECK_I(dp_m_n
.link_m
);
8733 PIPE_CONF_CHECK_I(dp_m_n
.link_n
);
8734 PIPE_CONF_CHECK_I(dp_m_n
.tu
);
8736 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hdisplay
);
8737 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_htotal
);
8738 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hblank_start
);
8739 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hblank_end
);
8740 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hsync_start
);
8741 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hsync_end
);
8743 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vdisplay
);
8744 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vtotal
);
8745 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vblank_start
);
8746 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vblank_end
);
8747 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vsync_start
);
8748 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vsync_end
);
8750 PIPE_CONF_CHECK_I(pixel_multiplier
);
8752 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8753 DRM_MODE_FLAG_INTERLACE
);
8755 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
8756 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8757 DRM_MODE_FLAG_PHSYNC
);
8758 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8759 DRM_MODE_FLAG_NHSYNC
);
8760 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8761 DRM_MODE_FLAG_PVSYNC
);
8762 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8763 DRM_MODE_FLAG_NVSYNC
);
8766 PIPE_CONF_CHECK_I(pipe_src_w
);
8767 PIPE_CONF_CHECK_I(pipe_src_h
);
8769 PIPE_CONF_CHECK_I(gmch_pfit
.control
);
8770 /* pfit ratios are autocomputed by the hw on gen4+ */
8771 if (INTEL_INFO(dev
)->gen
< 4)
8772 PIPE_CONF_CHECK_I(gmch_pfit
.pgm_ratios
);
8773 PIPE_CONF_CHECK_I(gmch_pfit
.lvds_border_bits
);
8774 PIPE_CONF_CHECK_I(pch_pfit
.enabled
);
8775 if (current_config
->pch_pfit
.enabled
) {
8776 PIPE_CONF_CHECK_I(pch_pfit
.pos
);
8777 PIPE_CONF_CHECK_I(pch_pfit
.size
);
8780 PIPE_CONF_CHECK_I(ips_enabled
);
8782 PIPE_CONF_CHECK_I(double_wide
);
8784 PIPE_CONF_CHECK_I(shared_dpll
);
8785 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll
);
8786 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll_md
);
8787 PIPE_CONF_CHECK_X(dpll_hw_state
.fp0
);
8788 PIPE_CONF_CHECK_X(dpll_hw_state
.fp1
);
8790 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5)
8791 PIPE_CONF_CHECK_I(pipe_bpp
);
8793 if (!IS_HASWELL(dev
)) {
8794 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode
.clock
);
8795 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock
);
8798 #undef PIPE_CONF_CHECK_X
8799 #undef PIPE_CONF_CHECK_I
8800 #undef PIPE_CONF_CHECK_FLAGS
8801 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
8802 #undef PIPE_CONF_QUIRK
8808 check_connector_state(struct drm_device
*dev
)
8810 struct intel_connector
*connector
;
8812 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8814 /* This also checks the encoder/connector hw state with the
8815 * ->get_hw_state callbacks. */
8816 intel_connector_check_state(connector
);
8818 WARN(&connector
->new_encoder
->base
!= connector
->base
.encoder
,
8819 "connector's staged encoder doesn't match current encoder\n");
8824 check_encoder_state(struct drm_device
*dev
)
8826 struct intel_encoder
*encoder
;
8827 struct intel_connector
*connector
;
8829 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8831 bool enabled
= false;
8832 bool active
= false;
8833 enum pipe pipe
, tracked_pipe
;
8835 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8836 encoder
->base
.base
.id
,
8837 drm_get_encoder_name(&encoder
->base
));
8839 WARN(&encoder
->new_crtc
->base
!= encoder
->base
.crtc
,
8840 "encoder's stage crtc doesn't match current crtc\n");
8841 WARN(encoder
->connectors_active
&& !encoder
->base
.crtc
,
8842 "encoder's active_connectors set, but no crtc\n");
8844 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8846 if (connector
->base
.encoder
!= &encoder
->base
)
8849 if (connector
->base
.dpms
!= DRM_MODE_DPMS_OFF
)
8852 WARN(!!encoder
->base
.crtc
!= enabled
,
8853 "encoder's enabled state mismatch "
8854 "(expected %i, found %i)\n",
8855 !!encoder
->base
.crtc
, enabled
);
8856 WARN(active
&& !encoder
->base
.crtc
,
8857 "active encoder with no crtc\n");
8859 WARN(encoder
->connectors_active
!= active
,
8860 "encoder's computed active state doesn't match tracked active state "
8861 "(expected %i, found %i)\n", active
, encoder
->connectors_active
);
8863 active
= encoder
->get_hw_state(encoder
, &pipe
);
8864 WARN(active
!= encoder
->connectors_active
,
8865 "encoder's hw state doesn't match sw tracking "
8866 "(expected %i, found %i)\n",
8867 encoder
->connectors_active
, active
);
8869 if (!encoder
->base
.crtc
)
8872 tracked_pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
8873 WARN(active
&& pipe
!= tracked_pipe
,
8874 "active encoder's pipe doesn't match"
8875 "(expected %i, found %i)\n",
8876 tracked_pipe
, pipe
);
8882 check_crtc_state(struct drm_device
*dev
)
8884 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8885 struct intel_crtc
*crtc
;
8886 struct intel_encoder
*encoder
;
8887 struct intel_crtc_config pipe_config
;
8889 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
8891 bool enabled
= false;
8892 bool active
= false;
8894 memset(&pipe_config
, 0, sizeof(pipe_config
));
8896 DRM_DEBUG_KMS("[CRTC:%d]\n",
8897 crtc
->base
.base
.id
);
8899 WARN(crtc
->active
&& !crtc
->base
.enabled
,
8900 "active crtc, but not enabled in sw tracking\n");
8902 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8904 if (encoder
->base
.crtc
!= &crtc
->base
)
8907 if (encoder
->connectors_active
)
8911 WARN(active
!= crtc
->active
,
8912 "crtc's computed active state doesn't match tracked active state "
8913 "(expected %i, found %i)\n", active
, crtc
->active
);
8914 WARN(enabled
!= crtc
->base
.enabled
,
8915 "crtc's computed enabled state doesn't match tracked enabled state "
8916 "(expected %i, found %i)\n", enabled
, crtc
->base
.enabled
);
8918 active
= dev_priv
->display
.get_pipe_config(crtc
,
8921 /* hw state is inconsistent with the pipe A quirk */
8922 if (crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
8923 active
= crtc
->active
;
8925 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8928 if (encoder
->base
.crtc
!= &crtc
->base
)
8930 if (encoder
->get_config
&&
8931 encoder
->get_hw_state(encoder
, &pipe
))
8932 encoder
->get_config(encoder
, &pipe_config
);
8935 WARN(crtc
->active
!= active
,
8936 "crtc active state doesn't match with hw state "
8937 "(expected %i, found %i)\n", crtc
->active
, active
);
8940 !intel_pipe_config_compare(dev
, &crtc
->config
, &pipe_config
)) {
8941 WARN(1, "pipe state doesn't match!\n");
8942 intel_dump_pipe_config(crtc
, &pipe_config
,
8944 intel_dump_pipe_config(crtc
, &crtc
->config
,
8951 check_shared_dpll_state(struct drm_device
*dev
)
8953 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8954 struct intel_crtc
*crtc
;
8955 struct intel_dpll_hw_state dpll_hw_state
;
8958 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
8959 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
8960 int enabled_crtcs
= 0, active_crtcs
= 0;
8963 memset(&dpll_hw_state
, 0, sizeof(dpll_hw_state
));
8965 DRM_DEBUG_KMS("%s\n", pll
->name
);
8967 active
= pll
->get_hw_state(dev_priv
, pll
, &dpll_hw_state
);
8969 WARN(pll
->active
> pll
->refcount
,
8970 "more active pll users than references: %i vs %i\n",
8971 pll
->active
, pll
->refcount
);
8972 WARN(pll
->active
&& !pll
->on
,
8973 "pll in active use but not on in sw tracking\n");
8974 WARN(pll
->on
&& !pll
->active
,
8975 "pll in on but not on in use in sw tracking\n");
8976 WARN(pll
->on
!= active
,
8977 "pll on state mismatch (expected %i, found %i)\n",
8980 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
8982 if (crtc
->base
.enabled
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
8984 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
8987 WARN(pll
->active
!= active_crtcs
,
8988 "pll active crtcs mismatch (expected %i, found %i)\n",
8989 pll
->active
, active_crtcs
);
8990 WARN(pll
->refcount
!= enabled_crtcs
,
8991 "pll enabled crtcs mismatch (expected %i, found %i)\n",
8992 pll
->refcount
, enabled_crtcs
);
8994 WARN(pll
->on
&& memcmp(&pll
->hw_state
, &dpll_hw_state
,
8995 sizeof(dpll_hw_state
)),
8996 "pll hw state mismatch\n");
9001 intel_modeset_check_state(struct drm_device
*dev
)
9003 check_connector_state(dev
);
9004 check_encoder_state(dev
);
9005 check_crtc_state(dev
);
9006 check_shared_dpll_state(dev
);
9009 void ironlake_check_encoder_dotclock(const struct intel_crtc_config
*pipe_config
,
9013 * FDI already provided one idea for the dotclock.
9014 * Yell if the encoder disagrees.
9016 WARN(!intel_fuzzy_clock_check(pipe_config
->adjusted_mode
.clock
, dotclock
),
9017 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
9018 pipe_config
->adjusted_mode
.clock
, dotclock
);
9021 static int __intel_set_mode(struct drm_crtc
*crtc
,
9022 struct drm_display_mode
*mode
,
9023 int x
, int y
, struct drm_framebuffer
*fb
)
9025 struct drm_device
*dev
= crtc
->dev
;
9026 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
9027 struct drm_display_mode
*saved_mode
, *saved_hwmode
;
9028 struct intel_crtc_config
*pipe_config
= NULL
;
9029 struct intel_crtc
*intel_crtc
;
9030 unsigned disable_pipes
, prepare_pipes
, modeset_pipes
;
9033 saved_mode
= kcalloc(2, sizeof(*saved_mode
), GFP_KERNEL
);
9036 saved_hwmode
= saved_mode
+ 1;
9038 intel_modeset_affected_pipes(crtc
, &modeset_pipes
,
9039 &prepare_pipes
, &disable_pipes
);
9041 *saved_hwmode
= crtc
->hwmode
;
9042 *saved_mode
= crtc
->mode
;
9044 /* Hack: Because we don't (yet) support global modeset on multiple
9045 * crtcs, we don't keep track of the new mode for more than one crtc.
9046 * Hence simply check whether any bit is set in modeset_pipes in all the
9047 * pieces of code that are not yet converted to deal with mutliple crtcs
9048 * changing their mode at the same time. */
9049 if (modeset_pipes
) {
9050 pipe_config
= intel_modeset_pipe_config(crtc
, fb
, mode
);
9051 if (IS_ERR(pipe_config
)) {
9052 ret
= PTR_ERR(pipe_config
);
9057 intel_dump_pipe_config(to_intel_crtc(crtc
), pipe_config
,
9061 for_each_intel_crtc_masked(dev
, disable_pipes
, intel_crtc
)
9062 intel_crtc_disable(&intel_crtc
->base
);
9064 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
9065 if (intel_crtc
->base
.enabled
)
9066 dev_priv
->display
.crtc_disable(&intel_crtc
->base
);
9069 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9070 * to set it here already despite that we pass it down the callchain.
9072 if (modeset_pipes
) {
9074 /* mode_set/enable/disable functions rely on a correct pipe
9076 to_intel_crtc(crtc
)->config
= *pipe_config
;
9079 /* Only after disabling all output pipelines that will be changed can we
9080 * update the the output configuration. */
9081 intel_modeset_update_state(dev
, prepare_pipes
);
9083 if (dev_priv
->display
.modeset_global_resources
)
9084 dev_priv
->display
.modeset_global_resources(dev
);
9086 /* Set up the DPLL and any encoders state that needs to adjust or depend
9089 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
9090 ret
= intel_crtc_mode_set(&intel_crtc
->base
,
9096 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
9097 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
)
9098 dev_priv
->display
.crtc_enable(&intel_crtc
->base
);
9100 if (modeset_pipes
) {
9101 /* Store real post-adjustment hardware mode. */
9102 crtc
->hwmode
= pipe_config
->adjusted_mode
;
9104 /* Calculate and store various constants which
9105 * are later needed by vblank and swap-completion
9106 * timestamping. They are derived from true hwmode.
9108 drm_calc_timestamping_constants(crtc
);
9111 /* FIXME: add subpixel order */
9113 if (ret
&& crtc
->enabled
) {
9114 crtc
->hwmode
= *saved_hwmode
;
9115 crtc
->mode
= *saved_mode
;
9124 static int intel_set_mode(struct drm_crtc
*crtc
,
9125 struct drm_display_mode
*mode
,
9126 int x
, int y
, struct drm_framebuffer
*fb
)
9130 ret
= __intel_set_mode(crtc
, mode
, x
, y
, fb
);
9133 intel_modeset_check_state(crtc
->dev
);
9138 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
9140 intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
, crtc
->fb
);
9143 #undef for_each_intel_crtc_masked
9145 static void intel_set_config_free(struct intel_set_config
*config
)
9150 kfree(config
->save_connector_encoders
);
9151 kfree(config
->save_encoder_crtcs
);
9155 static int intel_set_config_save_state(struct drm_device
*dev
,
9156 struct intel_set_config
*config
)
9158 struct drm_encoder
*encoder
;
9159 struct drm_connector
*connector
;
9162 config
->save_encoder_crtcs
=
9163 kcalloc(dev
->mode_config
.num_encoder
,
9164 sizeof(struct drm_crtc
*), GFP_KERNEL
);
9165 if (!config
->save_encoder_crtcs
)
9168 config
->save_connector_encoders
=
9169 kcalloc(dev
->mode_config
.num_connector
,
9170 sizeof(struct drm_encoder
*), GFP_KERNEL
);
9171 if (!config
->save_connector_encoders
)
9174 /* Copy data. Note that driver private data is not affected.
9175 * Should anything bad happen only the expected state is
9176 * restored, not the drivers personal bookkeeping.
9179 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
9180 config
->save_encoder_crtcs
[count
++] = encoder
->crtc
;
9184 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
9185 config
->save_connector_encoders
[count
++] = connector
->encoder
;
9191 static void intel_set_config_restore_state(struct drm_device
*dev
,
9192 struct intel_set_config
*config
)
9194 struct intel_encoder
*encoder
;
9195 struct intel_connector
*connector
;
9199 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
9201 to_intel_crtc(config
->save_encoder_crtcs
[count
++]);
9205 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
9206 connector
->new_encoder
=
9207 to_intel_encoder(config
->save_connector_encoders
[count
++]);
9212 is_crtc_connector_off(struct drm_mode_set
*set
)
9216 if (set
->num_connectors
== 0)
9219 if (WARN_ON(set
->connectors
== NULL
))
9222 for (i
= 0; i
< set
->num_connectors
; i
++)
9223 if (set
->connectors
[i
]->encoder
&&
9224 set
->connectors
[i
]->encoder
->crtc
== set
->crtc
&&
9225 set
->connectors
[i
]->dpms
!= DRM_MODE_DPMS_ON
)
9232 intel_set_config_compute_mode_changes(struct drm_mode_set
*set
,
9233 struct intel_set_config
*config
)
9236 /* We should be able to check here if the fb has the same properties
9237 * and then just flip_or_move it */
9238 if (is_crtc_connector_off(set
)) {
9239 config
->mode_changed
= true;
9240 } else if (set
->crtc
->fb
!= set
->fb
) {
9241 /* If we have no fb then treat it as a full mode set */
9242 if (set
->crtc
->fb
== NULL
) {
9243 struct intel_crtc
*intel_crtc
=
9244 to_intel_crtc(set
->crtc
);
9246 if (intel_crtc
->active
&& i915_fastboot
) {
9247 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9248 config
->fb_changed
= true;
9250 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9251 config
->mode_changed
= true;
9253 } else if (set
->fb
== NULL
) {
9254 config
->mode_changed
= true;
9255 } else if (set
->fb
->pixel_format
!=
9256 set
->crtc
->fb
->pixel_format
) {
9257 config
->mode_changed
= true;
9259 config
->fb_changed
= true;
9263 if (set
->fb
&& (set
->x
!= set
->crtc
->x
|| set
->y
!= set
->crtc
->y
))
9264 config
->fb_changed
= true;
9266 if (set
->mode
&& !drm_mode_equal(set
->mode
, &set
->crtc
->mode
)) {
9267 DRM_DEBUG_KMS("modes are different, full mode set\n");
9268 drm_mode_debug_printmodeline(&set
->crtc
->mode
);
9269 drm_mode_debug_printmodeline(set
->mode
);
9270 config
->mode_changed
= true;
9273 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9274 set
->crtc
->base
.id
, config
->mode_changed
, config
->fb_changed
);
9278 intel_modeset_stage_output_state(struct drm_device
*dev
,
9279 struct drm_mode_set
*set
,
9280 struct intel_set_config
*config
)
9282 struct drm_crtc
*new_crtc
;
9283 struct intel_connector
*connector
;
9284 struct intel_encoder
*encoder
;
9287 /* The upper layers ensure that we either disable a crtc or have a list
9288 * of connectors. For paranoia, double-check this. */
9289 WARN_ON(!set
->fb
&& (set
->num_connectors
!= 0));
9290 WARN_ON(set
->fb
&& (set
->num_connectors
== 0));
9292 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9294 /* Otherwise traverse passed in connector list and get encoders
9296 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
9297 if (set
->connectors
[ro
] == &connector
->base
) {
9298 connector
->new_encoder
= connector
->encoder
;
9303 /* If we disable the crtc, disable all its connectors. Also, if
9304 * the connector is on the changing crtc but not on the new
9305 * connector list, disable it. */
9306 if ((!set
->fb
|| ro
== set
->num_connectors
) &&
9307 connector
->base
.encoder
&&
9308 connector
->base
.encoder
->crtc
== set
->crtc
) {
9309 connector
->new_encoder
= NULL
;
9311 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9312 connector
->base
.base
.id
,
9313 drm_get_connector_name(&connector
->base
));
9317 if (&connector
->new_encoder
->base
!= connector
->base
.encoder
) {
9318 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
9319 config
->mode_changed
= true;
9322 /* connector->new_encoder is now updated for all connectors. */
9324 /* Update crtc of enabled connectors. */
9325 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9327 if (!connector
->new_encoder
)
9330 new_crtc
= connector
->new_encoder
->base
.crtc
;
9332 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
9333 if (set
->connectors
[ro
] == &connector
->base
)
9334 new_crtc
= set
->crtc
;
9337 /* Make sure the new CRTC will work with the encoder */
9338 if (!intel_encoder_crtc_ok(&connector
->new_encoder
->base
,
9342 connector
->encoder
->new_crtc
= to_intel_crtc(new_crtc
);
9344 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9345 connector
->base
.base
.id
,
9346 drm_get_connector_name(&connector
->base
),
9350 /* Check for any encoders that needs to be disabled. */
9351 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9353 list_for_each_entry(connector
,
9354 &dev
->mode_config
.connector_list
,
9356 if (connector
->new_encoder
== encoder
) {
9357 WARN_ON(!connector
->new_encoder
->new_crtc
);
9362 encoder
->new_crtc
= NULL
;
9364 /* Only now check for crtc changes so we don't miss encoders
9365 * that will be disabled. */
9366 if (&encoder
->new_crtc
->base
!= encoder
->base
.crtc
) {
9367 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
9368 config
->mode_changed
= true;
9371 /* Now we've also updated encoder->new_crtc for all encoders. */
9376 static int intel_crtc_set_config(struct drm_mode_set
*set
)
9378 struct drm_device
*dev
;
9379 struct drm_mode_set save_set
;
9380 struct intel_set_config
*config
;
9385 BUG_ON(!set
->crtc
->helper_private
);
9387 /* Enforce sane interface api - has been abused by the fb helper. */
9388 BUG_ON(!set
->mode
&& set
->fb
);
9389 BUG_ON(set
->fb
&& set
->num_connectors
== 0);
9392 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9393 set
->crtc
->base
.id
, set
->fb
->base
.id
,
9394 (int)set
->num_connectors
, set
->x
, set
->y
);
9396 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set
->crtc
->base
.id
);
9399 dev
= set
->crtc
->dev
;
9402 config
= kzalloc(sizeof(*config
), GFP_KERNEL
);
9406 ret
= intel_set_config_save_state(dev
, config
);
9410 save_set
.crtc
= set
->crtc
;
9411 save_set
.mode
= &set
->crtc
->mode
;
9412 save_set
.x
= set
->crtc
->x
;
9413 save_set
.y
= set
->crtc
->y
;
9414 save_set
.fb
= set
->crtc
->fb
;
9416 /* Compute whether we need a full modeset, only an fb base update or no
9417 * change at all. In the future we might also check whether only the
9418 * mode changed, e.g. for LVDS where we only change the panel fitter in
9420 intel_set_config_compute_mode_changes(set
, config
);
9422 ret
= intel_modeset_stage_output_state(dev
, set
, config
);
9426 if (config
->mode_changed
) {
9427 ret
= intel_set_mode(set
->crtc
, set
->mode
,
9428 set
->x
, set
->y
, set
->fb
);
9429 } else if (config
->fb_changed
) {
9430 intel_crtc_wait_for_pending_flips(set
->crtc
);
9432 ret
= intel_pipe_set_base(set
->crtc
,
9433 set
->x
, set
->y
, set
->fb
);
9437 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9438 set
->crtc
->base
.id
, ret
);
9440 intel_set_config_restore_state(dev
, config
);
9442 /* Try to restore the config */
9443 if (config
->mode_changed
&&
9444 intel_set_mode(save_set
.crtc
, save_set
.mode
,
9445 save_set
.x
, save_set
.y
, save_set
.fb
))
9446 DRM_ERROR("failed to restore config after modeset failure\n");
9450 intel_set_config_free(config
);
9454 static const struct drm_crtc_funcs intel_crtc_funcs
= {
9455 .cursor_set
= intel_crtc_cursor_set
,
9456 .cursor_move
= intel_crtc_cursor_move
,
9457 .gamma_set
= intel_crtc_gamma_set
,
9458 .set_config
= intel_crtc_set_config
,
9459 .destroy
= intel_crtc_destroy
,
9460 .page_flip
= intel_crtc_page_flip
,
9463 static void intel_cpu_pll_init(struct drm_device
*dev
)
9466 intel_ddi_pll_init(dev
);
9469 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private
*dev_priv
,
9470 struct intel_shared_dpll
*pll
,
9471 struct intel_dpll_hw_state
*hw_state
)
9475 val
= I915_READ(PCH_DPLL(pll
->id
));
9476 hw_state
->dpll
= val
;
9477 hw_state
->fp0
= I915_READ(PCH_FP0(pll
->id
));
9478 hw_state
->fp1
= I915_READ(PCH_FP1(pll
->id
));
9480 return val
& DPLL_VCO_ENABLE
;
9483 static void ibx_pch_dpll_mode_set(struct drm_i915_private
*dev_priv
,
9484 struct intel_shared_dpll
*pll
)
9486 I915_WRITE(PCH_FP0(pll
->id
), pll
->hw_state
.fp0
);
9487 I915_WRITE(PCH_FP1(pll
->id
), pll
->hw_state
.fp1
);
9490 static void ibx_pch_dpll_enable(struct drm_i915_private
*dev_priv
,
9491 struct intel_shared_dpll
*pll
)
9493 /* PCH refclock must be enabled first */
9494 assert_pch_refclk_enabled(dev_priv
);
9496 I915_WRITE(PCH_DPLL(pll
->id
), pll
->hw_state
.dpll
);
9498 /* Wait for the clocks to stabilize. */
9499 POSTING_READ(PCH_DPLL(pll
->id
));
9502 /* The pixel multiplier can only be updated once the
9503 * DPLL is enabled and the clocks are stable.
9505 * So write it again.
9507 I915_WRITE(PCH_DPLL(pll
->id
), pll
->hw_state
.dpll
);
9508 POSTING_READ(PCH_DPLL(pll
->id
));
9512 static void ibx_pch_dpll_disable(struct drm_i915_private
*dev_priv
,
9513 struct intel_shared_dpll
*pll
)
9515 struct drm_device
*dev
= dev_priv
->dev
;
9516 struct intel_crtc
*crtc
;
9518 /* Make sure no transcoder isn't still depending on us. */
9519 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
9520 if (intel_crtc_to_shared_dpll(crtc
) == pll
)
9521 assert_pch_transcoder_disabled(dev_priv
, crtc
->pipe
);
9524 I915_WRITE(PCH_DPLL(pll
->id
), 0);
9525 POSTING_READ(PCH_DPLL(pll
->id
));
9529 static char *ibx_pch_dpll_names
[] = {
9534 static void ibx_pch_dpll_init(struct drm_device
*dev
)
9536 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9539 dev_priv
->num_shared_dpll
= 2;
9541 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
9542 dev_priv
->shared_dplls
[i
].id
= i
;
9543 dev_priv
->shared_dplls
[i
].name
= ibx_pch_dpll_names
[i
];
9544 dev_priv
->shared_dplls
[i
].mode_set
= ibx_pch_dpll_mode_set
;
9545 dev_priv
->shared_dplls
[i
].enable
= ibx_pch_dpll_enable
;
9546 dev_priv
->shared_dplls
[i
].disable
= ibx_pch_dpll_disable
;
9547 dev_priv
->shared_dplls
[i
].get_hw_state
=
9548 ibx_pch_dpll_get_hw_state
;
9552 static void intel_shared_dpll_init(struct drm_device
*dev
)
9554 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9556 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
9557 ibx_pch_dpll_init(dev
);
9559 dev_priv
->num_shared_dpll
= 0;
9561 BUG_ON(dev_priv
->num_shared_dpll
> I915_NUM_PLLS
);
9562 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9563 dev_priv
->num_shared_dpll
);
9566 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
9568 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
9569 struct intel_crtc
*intel_crtc
;
9572 intel_crtc
= kzalloc(sizeof(*intel_crtc
), GFP_KERNEL
);
9573 if (intel_crtc
== NULL
)
9576 drm_crtc_init(dev
, &intel_crtc
->base
, &intel_crtc_funcs
);
9578 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
9579 for (i
= 0; i
< 256; i
++) {
9580 intel_crtc
->lut_r
[i
] = i
;
9581 intel_crtc
->lut_g
[i
] = i
;
9582 intel_crtc
->lut_b
[i
] = i
;
9585 /* Swap pipes & planes for FBC on pre-965 */
9586 intel_crtc
->pipe
= pipe
;
9587 intel_crtc
->plane
= pipe
;
9588 if (IS_MOBILE(dev
) && IS_GEN3(dev
)) {
9589 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
9590 intel_crtc
->plane
= !pipe
;
9593 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
9594 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
9595 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
9596 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
9598 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
9601 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
9602 struct drm_file
*file
)
9604 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
9605 struct drm_mode_object
*drmmode_obj
;
9606 struct intel_crtc
*crtc
;
9608 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
9611 drmmode_obj
= drm_mode_object_find(dev
, pipe_from_crtc_id
->crtc_id
,
9612 DRM_MODE_OBJECT_CRTC
);
9615 DRM_ERROR("no such CRTC id\n");
9619 crtc
= to_intel_crtc(obj_to_crtc(drmmode_obj
));
9620 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
9625 static int intel_encoder_clones(struct intel_encoder
*encoder
)
9627 struct drm_device
*dev
= encoder
->base
.dev
;
9628 struct intel_encoder
*source_encoder
;
9632 list_for_each_entry(source_encoder
,
9633 &dev
->mode_config
.encoder_list
, base
.head
) {
9635 if (encoder
== source_encoder
)
9636 index_mask
|= (1 << entry
);
9638 /* Intel hw has only one MUX where enocoders could be cloned. */
9639 if (encoder
->cloneable
&& source_encoder
->cloneable
)
9640 index_mask
|= (1 << entry
);
9648 static bool has_edp_a(struct drm_device
*dev
)
9650 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9652 if (!IS_MOBILE(dev
))
9655 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
9659 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES
) & ILK_eDP_A_DISABLE
))
9665 static void intel_setup_outputs(struct drm_device
*dev
)
9667 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9668 struct intel_encoder
*encoder
;
9669 bool dpd_is_edp
= false;
9671 intel_lvds_init(dev
);
9674 intel_crt_init(dev
);
9679 /* Haswell uses DDI functions to detect digital outputs */
9680 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
9681 /* DDI A only supports eDP */
9683 intel_ddi_init(dev
, PORT_A
);
9685 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9687 found
= I915_READ(SFUSE_STRAP
);
9689 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
9690 intel_ddi_init(dev
, PORT_B
);
9691 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
9692 intel_ddi_init(dev
, PORT_C
);
9693 if (found
& SFUSE_STRAP_DDID_DETECTED
)
9694 intel_ddi_init(dev
, PORT_D
);
9695 } else if (HAS_PCH_SPLIT(dev
)) {
9697 dpd_is_edp
= intel_dpd_is_edp(dev
);
9700 intel_dp_init(dev
, DP_A
, PORT_A
);
9702 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
9703 /* PCH SDVOB multiplex with HDMIB */
9704 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
9706 intel_hdmi_init(dev
, PCH_HDMIB
, PORT_B
);
9707 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
9708 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
9711 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
9712 intel_hdmi_init(dev
, PCH_HDMIC
, PORT_C
);
9714 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
9715 intel_hdmi_init(dev
, PCH_HDMID
, PORT_D
);
9717 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
9718 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
9720 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
9721 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
9722 } else if (IS_VALLEYVIEW(dev
)) {
9723 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
9724 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIC
) & SDVO_DETECTED
) {
9725 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIC
,
9727 if (I915_READ(VLV_DISPLAY_BASE
+ DP_C
) & DP_DETECTED
)
9728 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_C
,
9732 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIB
) & SDVO_DETECTED
) {
9733 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIB
,
9735 if (I915_READ(VLV_DISPLAY_BASE
+ DP_B
) & DP_DETECTED
)
9736 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_B
, PORT_B
);
9739 intel_dsi_init(dev
);
9740 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
9743 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
9744 DRM_DEBUG_KMS("probing SDVOB\n");
9745 found
= intel_sdvo_init(dev
, GEN3_SDVOB
, true);
9746 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
9747 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
9748 intel_hdmi_init(dev
, GEN4_HDMIB
, PORT_B
);
9751 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
))
9752 intel_dp_init(dev
, DP_B
, PORT_B
);
9755 /* Before G4X SDVOC doesn't have its own detect register */
9757 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
9758 DRM_DEBUG_KMS("probing SDVOC\n");
9759 found
= intel_sdvo_init(dev
, GEN3_SDVOC
, false);
9762 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
9764 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
9765 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
9766 intel_hdmi_init(dev
, GEN4_HDMIC
, PORT_C
);
9768 if (SUPPORTS_INTEGRATED_DP(dev
))
9769 intel_dp_init(dev
, DP_C
, PORT_C
);
9772 if (SUPPORTS_INTEGRATED_DP(dev
) &&
9773 (I915_READ(DP_D
) & DP_DETECTED
))
9774 intel_dp_init(dev
, DP_D
, PORT_D
);
9775 } else if (IS_GEN2(dev
))
9776 intel_dvo_init(dev
);
9778 if (SUPPORTS_TV(dev
))
9781 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
9782 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
9783 encoder
->base
.possible_clones
=
9784 intel_encoder_clones(encoder
);
9787 intel_init_pch_refclk(dev
);
9789 drm_helper_move_panel_connectors_to_head(dev
);
9792 void intel_framebuffer_fini(struct intel_framebuffer
*fb
)
9794 drm_framebuffer_cleanup(&fb
->base
);
9795 drm_gem_object_unreference_unlocked(&fb
->obj
->base
);
9798 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
9800 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
9802 intel_framebuffer_fini(intel_fb
);
9806 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
9807 struct drm_file
*file
,
9808 unsigned int *handle
)
9810 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
9811 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
9813 return drm_gem_handle_create(file
, &obj
->base
, handle
);
9816 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
9817 .destroy
= intel_user_framebuffer_destroy
,
9818 .create_handle
= intel_user_framebuffer_create_handle
,
9821 int intel_framebuffer_init(struct drm_device
*dev
,
9822 struct intel_framebuffer
*intel_fb
,
9823 struct drm_mode_fb_cmd2
*mode_cmd
,
9824 struct drm_i915_gem_object
*obj
)
9829 if (obj
->tiling_mode
== I915_TILING_Y
) {
9830 DRM_DEBUG("hardware does not support tiling Y\n");
9834 if (mode_cmd
->pitches
[0] & 63) {
9835 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9836 mode_cmd
->pitches
[0]);
9840 if (INTEL_INFO(dev
)->gen
>= 5 && !IS_VALLEYVIEW(dev
)) {
9841 pitch_limit
= 32*1024;
9842 } else if (INTEL_INFO(dev
)->gen
>= 4) {
9843 if (obj
->tiling_mode
)
9844 pitch_limit
= 16*1024;
9846 pitch_limit
= 32*1024;
9847 } else if (INTEL_INFO(dev
)->gen
>= 3) {
9848 if (obj
->tiling_mode
)
9849 pitch_limit
= 8*1024;
9851 pitch_limit
= 16*1024;
9853 /* XXX DSPC is limited to 4k tiled */
9854 pitch_limit
= 8*1024;
9856 if (mode_cmd
->pitches
[0] > pitch_limit
) {
9857 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9858 obj
->tiling_mode
? "tiled" : "linear",
9859 mode_cmd
->pitches
[0], pitch_limit
);
9863 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
9864 mode_cmd
->pitches
[0] != obj
->stride
) {
9865 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9866 mode_cmd
->pitches
[0], obj
->stride
);
9870 /* Reject formats not supported by any plane early. */
9871 switch (mode_cmd
->pixel_format
) {
9873 case DRM_FORMAT_RGB565
:
9874 case DRM_FORMAT_XRGB8888
:
9875 case DRM_FORMAT_ARGB8888
:
9877 case DRM_FORMAT_XRGB1555
:
9878 case DRM_FORMAT_ARGB1555
:
9879 if (INTEL_INFO(dev
)->gen
> 3) {
9880 DRM_DEBUG("unsupported pixel format: %s\n",
9881 drm_get_format_name(mode_cmd
->pixel_format
));
9885 case DRM_FORMAT_XBGR8888
:
9886 case DRM_FORMAT_ABGR8888
:
9887 case DRM_FORMAT_XRGB2101010
:
9888 case DRM_FORMAT_ARGB2101010
:
9889 case DRM_FORMAT_XBGR2101010
:
9890 case DRM_FORMAT_ABGR2101010
:
9891 if (INTEL_INFO(dev
)->gen
< 4) {
9892 DRM_DEBUG("unsupported pixel format: %s\n",
9893 drm_get_format_name(mode_cmd
->pixel_format
));
9897 case DRM_FORMAT_YUYV
:
9898 case DRM_FORMAT_UYVY
:
9899 case DRM_FORMAT_YVYU
:
9900 case DRM_FORMAT_VYUY
:
9901 if (INTEL_INFO(dev
)->gen
< 5) {
9902 DRM_DEBUG("unsupported pixel format: %s\n",
9903 drm_get_format_name(mode_cmd
->pixel_format
));
9908 DRM_DEBUG("unsupported pixel format: %s\n",
9909 drm_get_format_name(mode_cmd
->pixel_format
));
9913 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9914 if (mode_cmd
->offsets
[0] != 0)
9917 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
9918 intel_fb
->obj
= obj
;
9920 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
9922 DRM_ERROR("framebuffer init failed %d\n", ret
);
9929 static struct drm_framebuffer
*
9930 intel_user_framebuffer_create(struct drm_device
*dev
,
9931 struct drm_file
*filp
,
9932 struct drm_mode_fb_cmd2
*mode_cmd
)
9934 struct drm_i915_gem_object
*obj
;
9936 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
9937 mode_cmd
->handles
[0]));
9938 if (&obj
->base
== NULL
)
9939 return ERR_PTR(-ENOENT
);
9941 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
9944 static const struct drm_mode_config_funcs intel_mode_funcs
= {
9945 .fb_create
= intel_user_framebuffer_create
,
9946 .output_poll_changed
= intel_fb_output_poll_changed
,
9949 /* Set up chip specific display functions */
9950 static void intel_init_display(struct drm_device
*dev
)
9952 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9954 if (HAS_PCH_SPLIT(dev
) || IS_G4X(dev
))
9955 dev_priv
->display
.find_dpll
= g4x_find_best_dpll
;
9956 else if (IS_VALLEYVIEW(dev
))
9957 dev_priv
->display
.find_dpll
= vlv_find_best_dpll
;
9958 else if (IS_PINEVIEW(dev
))
9959 dev_priv
->display
.find_dpll
= pnv_find_best_dpll
;
9961 dev_priv
->display
.find_dpll
= i9xx_find_best_dpll
;
9964 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
9965 dev_priv
->display
.crtc_mode_set
= haswell_crtc_mode_set
;
9966 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
9967 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
9968 dev_priv
->display
.off
= haswell_crtc_off
;
9969 dev_priv
->display
.update_plane
= ironlake_update_plane
;
9970 } else if (HAS_PCH_SPLIT(dev
)) {
9971 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
9972 dev_priv
->display
.crtc_mode_set
= ironlake_crtc_mode_set
;
9973 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
9974 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
9975 dev_priv
->display
.off
= ironlake_crtc_off
;
9976 dev_priv
->display
.update_plane
= ironlake_update_plane
;
9977 } else if (IS_VALLEYVIEW(dev
)) {
9978 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
9979 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
9980 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
9981 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
9982 dev_priv
->display
.off
= i9xx_crtc_off
;
9983 dev_priv
->display
.update_plane
= i9xx_update_plane
;
9985 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
9986 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
9987 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
9988 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
9989 dev_priv
->display
.off
= i9xx_crtc_off
;
9990 dev_priv
->display
.update_plane
= i9xx_update_plane
;
9993 /* Returns the core display clock speed */
9994 if (IS_VALLEYVIEW(dev
))
9995 dev_priv
->display
.get_display_clock_speed
=
9996 valleyview_get_display_clock_speed
;
9997 else if (IS_I945G(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
9998 dev_priv
->display
.get_display_clock_speed
=
9999 i945_get_display_clock_speed
;
10000 else if (IS_I915G(dev
))
10001 dev_priv
->display
.get_display_clock_speed
=
10002 i915_get_display_clock_speed
;
10003 else if (IS_I945GM(dev
) || IS_845G(dev
))
10004 dev_priv
->display
.get_display_clock_speed
=
10005 i9xx_misc_get_display_clock_speed
;
10006 else if (IS_PINEVIEW(dev
))
10007 dev_priv
->display
.get_display_clock_speed
=
10008 pnv_get_display_clock_speed
;
10009 else if (IS_I915GM(dev
))
10010 dev_priv
->display
.get_display_clock_speed
=
10011 i915gm_get_display_clock_speed
;
10012 else if (IS_I865G(dev
))
10013 dev_priv
->display
.get_display_clock_speed
=
10014 i865_get_display_clock_speed
;
10015 else if (IS_I85X(dev
))
10016 dev_priv
->display
.get_display_clock_speed
=
10017 i855_get_display_clock_speed
;
10018 else /* 852, 830 */
10019 dev_priv
->display
.get_display_clock_speed
=
10020 i830_get_display_clock_speed
;
10022 if (HAS_PCH_SPLIT(dev
)) {
10023 if (IS_GEN5(dev
)) {
10024 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
10025 dev_priv
->display
.write_eld
= ironlake_write_eld
;
10026 } else if (IS_GEN6(dev
)) {
10027 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
10028 dev_priv
->display
.write_eld
= ironlake_write_eld
;
10029 } else if (IS_IVYBRIDGE(dev
)) {
10030 /* FIXME: detect B0+ stepping and use auto training */
10031 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
10032 dev_priv
->display
.write_eld
= ironlake_write_eld
;
10033 dev_priv
->display
.modeset_global_resources
=
10034 ivb_modeset_global_resources
;
10035 } else if (IS_HASWELL(dev
)) {
10036 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
10037 dev_priv
->display
.write_eld
= haswell_write_eld
;
10038 dev_priv
->display
.modeset_global_resources
=
10039 haswell_modeset_global_resources
;
10041 } else if (IS_G4X(dev
)) {
10042 dev_priv
->display
.write_eld
= g4x_write_eld
;
10045 /* Default just returns -ENODEV to indicate unsupported */
10046 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
10048 switch (INTEL_INFO(dev
)->gen
) {
10050 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
10054 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
10059 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
10063 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
10066 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
10072 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10073 * resume, or other times. This quirk makes sure that's the case for
10074 * affected systems.
10076 static void quirk_pipea_force(struct drm_device
*dev
)
10078 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10080 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
10081 DRM_INFO("applying pipe a force quirk\n");
10085 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10087 static void quirk_ssc_force_disable(struct drm_device
*dev
)
10089 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10090 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
10091 DRM_INFO("applying lvds SSC disable quirk\n");
10095 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10098 static void quirk_invert_brightness(struct drm_device
*dev
)
10100 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10101 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
10102 DRM_INFO("applying inverted panel brightness quirk\n");
10106 * Some machines (Dell XPS13) suffer broken backlight controls if
10107 * BLM_PCH_PWM_ENABLE is set.
10109 static void quirk_no_pcm_pwm_enable(struct drm_device
*dev
)
10111 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10112 dev_priv
->quirks
|= QUIRK_NO_PCH_PWM_ENABLE
;
10113 DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
10116 struct intel_quirk
{
10118 int subsystem_vendor
;
10119 int subsystem_device
;
10120 void (*hook
)(struct drm_device
*dev
);
10123 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10124 struct intel_dmi_quirk
{
10125 void (*hook
)(struct drm_device
*dev
);
10126 const struct dmi_system_id (*dmi_id_list
)[];
10129 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
10131 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
10135 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
10137 .dmi_id_list
= &(const struct dmi_system_id
[]) {
10139 .callback
= intel_dmi_reverse_brightness
,
10140 .ident
= "NCR Corporation",
10141 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
10142 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
10145 { } /* terminating entry */
10147 .hook
= quirk_invert_brightness
,
10151 static struct intel_quirk intel_quirks
[] = {
10152 /* HP Mini needs pipe A force quirk (LP: #322104) */
10153 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force
},
10155 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10156 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
10158 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10159 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
10161 /* 830/845 need to leave pipe A & dpll A up */
10162 { 0x2562, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
10163 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
10165 /* Lenovo U160 cannot use SSC on LVDS */
10166 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
10168 /* Sony Vaio Y cannot use SSC on LVDS */
10169 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
10172 * All GM45 Acer (and its brands eMachines and Packard Bell) laptops
10173 * seem to use inverted backlight PWM.
10175 { 0x2a42, 0x1025, PCI_ANY_ID
, quirk_invert_brightness
},
10177 /* Dell XPS13 HD Sandy Bridge */
10178 { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable
},
10179 /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10180 { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable
},
10183 static void intel_init_quirks(struct drm_device
*dev
)
10185 struct pci_dev
*d
= dev
->pdev
;
10188 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
10189 struct intel_quirk
*q
= &intel_quirks
[i
];
10191 if (d
->device
== q
->device
&&
10192 (d
->subsystem_vendor
== q
->subsystem_vendor
||
10193 q
->subsystem_vendor
== PCI_ANY_ID
) &&
10194 (d
->subsystem_device
== q
->subsystem_device
||
10195 q
->subsystem_device
== PCI_ANY_ID
))
10198 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
10199 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
10200 intel_dmi_quirks
[i
].hook(dev
);
10204 /* Disable the VGA plane that we never use */
10205 static void i915_disable_vga(struct drm_device
*dev
)
10207 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10209 u32 vga_reg
= i915_vgacntrl_reg(dev
);
10211 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
10212 outb(SR01
, VGA_SR_INDEX
);
10213 sr1
= inb(VGA_SR_DATA
);
10214 outb(sr1
| 1<<5, VGA_SR_DATA
);
10215 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
10218 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
10219 POSTING_READ(vga_reg
);
10222 static void i915_enable_vga_mem(struct drm_device
*dev
)
10224 /* Enable VGA memory on Intel HD */
10225 if (HAS_PCH_SPLIT(dev
)) {
10226 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
10227 outb(inb(VGA_MSR_READ
) | VGA_MSR_MEM_EN
, VGA_MSR_WRITE
);
10228 vga_set_legacy_decoding(dev
->pdev
, VGA_RSRC_LEGACY_IO
|
10229 VGA_RSRC_LEGACY_MEM
|
10230 VGA_RSRC_NORMAL_IO
|
10231 VGA_RSRC_NORMAL_MEM
);
10232 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
10236 void i915_disable_vga_mem(struct drm_device
*dev
)
10238 /* Disable VGA memory on Intel HD */
10239 if (HAS_PCH_SPLIT(dev
)) {
10240 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
10241 outb(inb(VGA_MSR_READ
) & ~VGA_MSR_MEM_EN
, VGA_MSR_WRITE
);
10242 vga_set_legacy_decoding(dev
->pdev
, VGA_RSRC_LEGACY_IO
|
10243 VGA_RSRC_NORMAL_IO
|
10244 VGA_RSRC_NORMAL_MEM
);
10245 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
10249 void intel_modeset_init_hw(struct drm_device
*dev
)
10251 intel_prepare_ddi(dev
);
10253 intel_init_clock_gating(dev
);
10255 mutex_lock(&dev
->struct_mutex
);
10256 intel_enable_gt_powersave(dev
);
10257 mutex_unlock(&dev
->struct_mutex
);
10260 void intel_modeset_suspend_hw(struct drm_device
*dev
)
10262 intel_suspend_hw(dev
);
10265 void intel_modeset_init(struct drm_device
*dev
)
10267 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10270 drm_mode_config_init(dev
);
10272 dev
->mode_config
.min_width
= 0;
10273 dev
->mode_config
.min_height
= 0;
10275 dev
->mode_config
.preferred_depth
= 24;
10276 dev
->mode_config
.prefer_shadow
= 1;
10278 dev
->mode_config
.funcs
= &intel_mode_funcs
;
10280 intel_init_quirks(dev
);
10282 intel_init_pm(dev
);
10284 if (INTEL_INFO(dev
)->num_pipes
== 0)
10287 intel_init_display(dev
);
10289 if (IS_GEN2(dev
)) {
10290 dev
->mode_config
.max_width
= 2048;
10291 dev
->mode_config
.max_height
= 2048;
10292 } else if (IS_GEN3(dev
)) {
10293 dev
->mode_config
.max_width
= 4096;
10294 dev
->mode_config
.max_height
= 4096;
10296 dev
->mode_config
.max_width
= 8192;
10297 dev
->mode_config
.max_height
= 8192;
10299 dev
->mode_config
.fb_base
= dev_priv
->gtt
.mappable_base
;
10301 DRM_DEBUG_KMS("%d display pipe%s available.\n",
10302 INTEL_INFO(dev
)->num_pipes
,
10303 INTEL_INFO(dev
)->num_pipes
> 1 ? "s" : "");
10306 intel_crtc_init(dev
, i
);
10307 for (j
= 0; j
< dev_priv
->num_plane
; j
++) {
10308 ret
= intel_plane_init(dev
, i
, j
);
10310 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10311 pipe_name(i
), sprite_name(i
, j
), ret
);
10315 intel_cpu_pll_init(dev
);
10316 intel_shared_dpll_init(dev
);
10318 /* Just disable it once at startup */
10319 i915_disable_vga(dev
);
10320 intel_setup_outputs(dev
);
10322 /* Just in case the BIOS is doing something questionable. */
10323 intel_disable_fbc(dev
);
10327 intel_connector_break_all_links(struct intel_connector
*connector
)
10329 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
10330 connector
->base
.encoder
= NULL
;
10331 connector
->encoder
->connectors_active
= false;
10332 connector
->encoder
->base
.crtc
= NULL
;
10335 static void intel_enable_pipe_a(struct drm_device
*dev
)
10337 struct intel_connector
*connector
;
10338 struct drm_connector
*crt
= NULL
;
10339 struct intel_load_detect_pipe load_detect_temp
;
10341 /* We can't just switch on the pipe A, we need to set things up with a
10342 * proper mode and output configuration. As a gross hack, enable pipe A
10343 * by enabling the load detect pipe once. */
10344 list_for_each_entry(connector
,
10345 &dev
->mode_config
.connector_list
,
10347 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
10348 crt
= &connector
->base
;
10356 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
))
10357 intel_release_load_detect_pipe(crt
, &load_detect_temp
);
10363 intel_check_plane_mapping(struct intel_crtc
*crtc
)
10365 struct drm_device
*dev
= crtc
->base
.dev
;
10366 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10369 if (INTEL_INFO(dev
)->num_pipes
== 1)
10372 reg
= DSPCNTR(!crtc
->plane
);
10373 val
= I915_READ(reg
);
10375 if ((val
& DISPLAY_PLANE_ENABLE
) &&
10376 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
10382 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
10384 struct drm_device
*dev
= crtc
->base
.dev
;
10385 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10388 /* Clear any frame start delays used for debugging left by the BIOS */
10389 reg
= PIPECONF(crtc
->config
.cpu_transcoder
);
10390 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
10392 /* We need to sanitize the plane -> pipe mapping first because this will
10393 * disable the crtc (and hence change the state) if it is wrong. Note
10394 * that gen4+ has a fixed plane -> pipe mapping. */
10395 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
10396 struct intel_connector
*connector
;
10399 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10400 crtc
->base
.base
.id
);
10402 /* Pipe has the wrong plane attached and the plane is active.
10403 * Temporarily change the plane mapping and disable everything
10405 plane
= crtc
->plane
;
10406 crtc
->plane
= !plane
;
10407 dev_priv
->display
.crtc_disable(&crtc
->base
);
10408 crtc
->plane
= plane
;
10410 /* ... and break all links. */
10411 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10413 if (connector
->encoder
->base
.crtc
!= &crtc
->base
)
10416 intel_connector_break_all_links(connector
);
10419 WARN_ON(crtc
->active
);
10420 crtc
->base
.enabled
= false;
10423 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
10424 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
10425 /* BIOS forgot to enable pipe A, this mostly happens after
10426 * resume. Force-enable the pipe to fix this, the update_dpms
10427 * call below we restore the pipe to the right state, but leave
10428 * the required bits on. */
10429 intel_enable_pipe_a(dev
);
10432 /* Adjust the state of the output pipe according to whether we
10433 * have active connectors/encoders. */
10434 intel_crtc_update_dpms(&crtc
->base
);
10436 if (crtc
->active
!= crtc
->base
.enabled
) {
10437 struct intel_encoder
*encoder
;
10439 /* This can happen either due to bugs in the get_hw_state
10440 * functions or because the pipe is force-enabled due to the
10442 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10443 crtc
->base
.base
.id
,
10444 crtc
->base
.enabled
? "enabled" : "disabled",
10445 crtc
->active
? "enabled" : "disabled");
10447 crtc
->base
.enabled
= crtc
->active
;
10449 /* Because we only establish the connector -> encoder ->
10450 * crtc links if something is active, this means the
10451 * crtc is now deactivated. Break the links. connector
10452 * -> encoder links are only establish when things are
10453 * actually up, hence no need to break them. */
10454 WARN_ON(crtc
->active
);
10456 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
10457 WARN_ON(encoder
->connectors_active
);
10458 encoder
->base
.crtc
= NULL
;
10463 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
10465 struct intel_connector
*connector
;
10466 struct drm_device
*dev
= encoder
->base
.dev
;
10468 /* We need to check both for a crtc link (meaning that the
10469 * encoder is active and trying to read from a pipe) and the
10470 * pipe itself being active. */
10471 bool has_active_crtc
= encoder
->base
.crtc
&&
10472 to_intel_crtc(encoder
->base
.crtc
)->active
;
10474 if (encoder
->connectors_active
&& !has_active_crtc
) {
10475 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10476 encoder
->base
.base
.id
,
10477 drm_get_encoder_name(&encoder
->base
));
10479 /* Connector is active, but has no active pipe. This is
10480 * fallout from our resume register restoring. Disable
10481 * the encoder manually again. */
10482 if (encoder
->base
.crtc
) {
10483 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10484 encoder
->base
.base
.id
,
10485 drm_get_encoder_name(&encoder
->base
));
10486 encoder
->disable(encoder
);
10489 /* Inconsistent output/port/pipe state happens presumably due to
10490 * a bug in one of the get_hw_state functions. Or someplace else
10491 * in our code, like the register restore mess on resume. Clamp
10492 * things to off as a safer default. */
10493 list_for_each_entry(connector
,
10494 &dev
->mode_config
.connector_list
,
10496 if (connector
->encoder
!= encoder
)
10499 intel_connector_break_all_links(connector
);
10502 /* Enabled encoders without active connectors will be fixed in
10503 * the crtc fixup. */
10506 void i915_redisable_vga(struct drm_device
*dev
)
10508 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10509 u32 vga_reg
= i915_vgacntrl_reg(dev
);
10511 /* This function can be called both from intel_modeset_setup_hw_state or
10512 * at a very early point in our resume sequence, where the power well
10513 * structures are not yet restored. Since this function is at a very
10514 * paranoid "someone might have enabled VGA while we were not looking"
10515 * level, just check if the power well is enabled instead of trying to
10516 * follow the "don't touch the power well if we don't need it" policy
10517 * the rest of the driver uses. */
10518 if (HAS_POWER_WELL(dev
) &&
10519 (I915_READ(HSW_PWR_WELL_DRIVER
) & HSW_PWR_WELL_STATE_ENABLED
) == 0)
10522 if (I915_READ(vga_reg
) != VGA_DISP_DISABLE
) {
10523 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
10524 i915_disable_vga(dev
);
10525 i915_disable_vga_mem(dev
);
10529 static void intel_modeset_readout_hw_state(struct drm_device
*dev
)
10531 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10533 struct intel_crtc
*crtc
;
10534 struct intel_encoder
*encoder
;
10535 struct intel_connector
*connector
;
10538 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
10540 memset(&crtc
->config
, 0, sizeof(crtc
->config
));
10542 crtc
->active
= dev_priv
->display
.get_pipe_config(crtc
,
10545 crtc
->base
.enabled
= crtc
->active
;
10547 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10548 crtc
->base
.base
.id
,
10549 crtc
->active
? "enabled" : "disabled");
10552 /* FIXME: Smash this into the new shared dpll infrastructure. */
10554 intel_ddi_setup_hw_pll_state(dev
);
10556 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
10557 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
10559 pll
->on
= pll
->get_hw_state(dev_priv
, pll
, &pll
->hw_state
);
10561 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
10563 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
10566 pll
->refcount
= pll
->active
;
10568 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10569 pll
->name
, pll
->refcount
, pll
->on
);
10572 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
10576 if (encoder
->get_hw_state(encoder
, &pipe
)) {
10577 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
10578 encoder
->base
.crtc
= &crtc
->base
;
10579 if (encoder
->get_config
)
10580 encoder
->get_config(encoder
, &crtc
->config
);
10582 encoder
->base
.crtc
= NULL
;
10585 encoder
->connectors_active
= false;
10586 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10587 encoder
->base
.base
.id
,
10588 drm_get_encoder_name(&encoder
->base
),
10589 encoder
->base
.crtc
? "enabled" : "disabled",
10593 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10595 if (connector
->get_hw_state(connector
)) {
10596 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
10597 connector
->encoder
->connectors_active
= true;
10598 connector
->base
.encoder
= &connector
->encoder
->base
;
10600 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
10601 connector
->base
.encoder
= NULL
;
10603 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10604 connector
->base
.base
.id
,
10605 drm_get_connector_name(&connector
->base
),
10606 connector
->base
.encoder
? "enabled" : "disabled");
10610 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10611 * and i915 state tracking structures. */
10612 void intel_modeset_setup_hw_state(struct drm_device
*dev
,
10613 bool force_restore
)
10615 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10617 struct intel_crtc
*crtc
;
10618 struct intel_encoder
*encoder
;
10621 intel_modeset_readout_hw_state(dev
);
10624 * Now that we have the config, copy it to each CRTC struct
10625 * Note that this could go away if we move to using crtc_config
10626 * checking everywhere.
10628 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
10630 if (crtc
->active
&& i915_fastboot
) {
10631 intel_crtc_mode_from_pipe_config(crtc
, &crtc
->config
);
10633 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10634 crtc
->base
.base
.id
);
10635 drm_mode_debug_printmodeline(&crtc
->base
.mode
);
10639 /* HW state is read out, now we need to sanitize this mess. */
10640 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
10642 intel_sanitize_encoder(encoder
);
10645 for_each_pipe(pipe
) {
10646 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
10647 intel_sanitize_crtc(crtc
);
10648 intel_dump_pipe_config(crtc
, &crtc
->config
, "[setup_hw_state]");
10651 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
10652 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
10654 if (!pll
->on
|| pll
->active
)
10657 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll
->name
);
10659 pll
->disable(dev_priv
, pll
);
10663 if (force_restore
) {
10664 i915_redisable_vga(dev
);
10667 * We need to use raw interfaces for restoring state to avoid
10668 * checking (bogus) intermediate states.
10670 for_each_pipe(pipe
) {
10671 struct drm_crtc
*crtc
=
10672 dev_priv
->pipe_to_crtc_mapping
[pipe
];
10674 __intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
,
10678 intel_modeset_update_staged_output_state(dev
);
10681 intel_modeset_check_state(dev
);
10683 drm_mode_config_reset(dev
);
10686 void intel_modeset_gem_init(struct drm_device
*dev
)
10688 intel_modeset_init_hw(dev
);
10690 intel_setup_overlay(dev
);
10692 intel_modeset_setup_hw_state(dev
, false);
10695 void intel_modeset_cleanup(struct drm_device
*dev
)
10697 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10698 struct drm_crtc
*crtc
;
10701 * Interrupts and polling as the first thing to avoid creating havoc.
10702 * Too much stuff here (turning of rps, connectors, ...) would
10703 * experience fancy races otherwise.
10705 drm_irq_uninstall(dev
);
10706 cancel_work_sync(&dev_priv
->hotplug_work
);
10708 * Due to the hpd irq storm handling the hotplug work can re-arm the
10709 * poll handlers. Hence disable polling after hpd handling is shut down.
10711 drm_kms_helper_poll_fini(dev
);
10713 mutex_lock(&dev
->struct_mutex
);
10715 intel_unregister_dsm_handler();
10717 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
10718 /* Skip inactive CRTCs */
10722 intel_increase_pllclock(crtc
);
10725 intel_disable_fbc(dev
);
10727 i915_enable_vga_mem(dev
);
10729 intel_disable_gt_powersave(dev
);
10731 ironlake_teardown_rc6(dev
);
10733 mutex_unlock(&dev
->struct_mutex
);
10735 /* flush any delayed tasks or pending work */
10736 flush_scheduled_work();
10738 /* destroy backlight, if any, before the connectors */
10739 intel_panel_destroy_backlight(dev
);
10741 drm_mode_config_cleanup(dev
);
10743 intel_cleanup_overlay(dev
);
10747 * Return which encoder is currently attached for connector.
10749 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
10751 return &intel_attached_encoder(connector
)->base
;
10754 void intel_connector_attach_encoder(struct intel_connector
*connector
,
10755 struct intel_encoder
*encoder
)
10757 connector
->encoder
= encoder
;
10758 drm_mode_connector_attach_encoder(&connector
->base
,
10763 * set vga decode state - true == enable VGA decode
10765 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
10767 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10770 pci_read_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, &gmch_ctrl
);
10772 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
10774 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
10775 pci_write_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, gmch_ctrl
);
10779 struct intel_display_error_state
{
10781 u32 power_well_driver
;
10783 int num_transcoders
;
10785 struct intel_cursor_error_state
{
10790 } cursor
[I915_MAX_PIPES
];
10792 struct intel_pipe_error_state
{
10794 } pipe
[I915_MAX_PIPES
];
10796 struct intel_plane_error_state
{
10804 } plane
[I915_MAX_PIPES
];
10806 struct intel_transcoder_error_state
{
10807 enum transcoder cpu_transcoder
;
10820 struct intel_display_error_state
*
10821 intel_display_capture_error_state(struct drm_device
*dev
)
10823 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
10824 struct intel_display_error_state
*error
;
10825 int transcoders
[] = {
10833 if (INTEL_INFO(dev
)->num_pipes
== 0)
10836 error
= kmalloc(sizeof(*error
), GFP_ATOMIC
);
10840 if (HAS_POWER_WELL(dev
))
10841 error
->power_well_driver
= I915_READ(HSW_PWR_WELL_DRIVER
);
10844 if (INTEL_INFO(dev
)->gen
<= 6 || IS_VALLEYVIEW(dev
)) {
10845 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
10846 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
10847 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
10849 error
->cursor
[i
].control
= I915_READ(CURCNTR_IVB(i
));
10850 error
->cursor
[i
].position
= I915_READ(CURPOS_IVB(i
));
10851 error
->cursor
[i
].base
= I915_READ(CURBASE_IVB(i
));
10854 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
10855 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
10856 if (INTEL_INFO(dev
)->gen
<= 3) {
10857 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
10858 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
10860 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
10861 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
10862 if (INTEL_INFO(dev
)->gen
>= 4) {
10863 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
10864 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
10867 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
10870 error
->num_transcoders
= INTEL_INFO(dev
)->num_pipes
;
10871 if (HAS_DDI(dev_priv
->dev
))
10872 error
->num_transcoders
++; /* Account for eDP. */
10874 for (i
= 0; i
< error
->num_transcoders
; i
++) {
10875 enum transcoder cpu_transcoder
= transcoders
[i
];
10877 error
->transcoder
[i
].cpu_transcoder
= cpu_transcoder
;
10879 error
->transcoder
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
10880 error
->transcoder
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
10881 error
->transcoder
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
10882 error
->transcoder
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
10883 error
->transcoder
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
10884 error
->transcoder
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
10885 error
->transcoder
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
10888 /* In the code above we read the registers without checking if the power
10889 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10890 * prevent the next I915_WRITE from detecting it and printing an error
10892 intel_uncore_clear_errors(dev
);
10897 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10900 intel_display_print_error_state(struct drm_i915_error_state_buf
*m
,
10901 struct drm_device
*dev
,
10902 struct intel_display_error_state
*error
)
10909 err_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev
)->num_pipes
);
10910 if (HAS_POWER_WELL(dev
))
10911 err_printf(m
, "PWR_WELL_CTL2: %08x\n",
10912 error
->power_well_driver
);
10914 err_printf(m
, "Pipe [%d]:\n", i
);
10915 err_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
10917 err_printf(m
, "Plane [%d]:\n", i
);
10918 err_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
10919 err_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
10920 if (INTEL_INFO(dev
)->gen
<= 3) {
10921 err_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
10922 err_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
10924 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
10925 err_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
10926 if (INTEL_INFO(dev
)->gen
>= 4) {
10927 err_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
10928 err_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
10931 err_printf(m
, "Cursor [%d]:\n", i
);
10932 err_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
10933 err_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
10934 err_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);
10937 for (i
= 0; i
< error
->num_transcoders
; i
++) {
10938 err_printf(m
, " CPU transcoder: %c\n",
10939 transcoder_name(error
->transcoder
[i
].cpu_transcoder
));
10940 err_printf(m
, " CONF: %08x\n", error
->transcoder
[i
].conf
);
10941 err_printf(m
, " HTOTAL: %08x\n", error
->transcoder
[i
].htotal
);
10942 err_printf(m
, " HBLANK: %08x\n", error
->transcoder
[i
].hblank
);
10943 err_printf(m
, " HSYNC: %08x\n", error
->transcoder
[i
].hsync
);
10944 err_printf(m
, " VTOTAL: %08x\n", error
->transcoder
[i
].vtotal
);
10945 err_printf(m
, " VBLANK: %08x\n", error
->transcoder
[i
].vblank
);
10946 err_printf(m
, " VSYNC: %08x\n", error
->transcoder
[i
].vsync
);