2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
48 /* Primary plane formats for gen <= 3 */
49 static const uint32_t i8xx_primary_formats
[] = {
58 /* Primary plane formats for gen >= 4 */
59 static const uint32_t i965_primary_formats
[] = {
66 DRM_FORMAT_XRGB2101010
,
67 DRM_FORMAT_ARGB2101010
,
68 DRM_FORMAT_XBGR2101010
,
69 DRM_FORMAT_ABGR2101010
,
73 static const uint32_t intel_cursor_formats
[] = {
77 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
79 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
80 struct intel_crtc_state
*pipe_config
);
81 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
82 struct intel_crtc_state
*pipe_config
);
84 static int intel_set_mode(struct drm_crtc
*crtc
,
85 struct drm_atomic_state
*state
);
86 static int intel_framebuffer_init(struct drm_device
*dev
,
87 struct intel_framebuffer
*ifb
,
88 struct drm_mode_fb_cmd2
*mode_cmd
,
89 struct drm_i915_gem_object
*obj
);
90 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
);
91 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
);
92 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
93 struct intel_link_m_n
*m_n
,
94 struct intel_link_m_n
*m2_n2
);
95 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
);
96 static void haswell_set_pipeconf(struct drm_crtc
*crtc
);
97 static void intel_set_pipe_csc(struct drm_crtc
*crtc
);
98 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
99 const struct intel_crtc_state
*pipe_config
);
100 static void chv_prepare_pll(struct intel_crtc
*crtc
,
101 const struct intel_crtc_state
*pipe_config
);
102 static void intel_begin_crtc_commit(struct drm_crtc
*crtc
);
103 static void intel_finish_crtc_commit(struct drm_crtc
*crtc
);
104 static void skl_init_scalers(struct drm_device
*dev
, struct intel_crtc
*intel_crtc
,
105 struct intel_crtc_state
*crtc_state
);
106 static int i9xx_get_refclk(const struct intel_crtc_state
*crtc_state
,
108 static void intel_crtc_enable_planes(struct drm_crtc
*crtc
);
109 static void intel_crtc_disable_planes(struct drm_crtc
*crtc
);
111 static struct intel_encoder
*intel_find_encoder(struct intel_connector
*connector
, int pipe
)
113 if (!connector
->mst_port
)
114 return connector
->encoder
;
116 return &connector
->mst_port
->mst_encoders
[pipe
]->base
;
125 int p2_slow
, p2_fast
;
128 typedef struct intel_limit intel_limit_t
;
130 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
135 intel_pch_rawclk(struct drm_device
*dev
)
137 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
139 WARN_ON(!HAS_PCH_SPLIT(dev
));
141 return I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
;
144 static inline u32
/* units of 100MHz */
145 intel_fdi_link_freq(struct drm_device
*dev
)
148 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
149 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
154 static const intel_limit_t intel_limits_i8xx_dac
= {
155 .dot
= { .min
= 25000, .max
= 350000 },
156 .vco
= { .min
= 908000, .max
= 1512000 },
157 .n
= { .min
= 2, .max
= 16 },
158 .m
= { .min
= 96, .max
= 140 },
159 .m1
= { .min
= 18, .max
= 26 },
160 .m2
= { .min
= 6, .max
= 16 },
161 .p
= { .min
= 4, .max
= 128 },
162 .p1
= { .min
= 2, .max
= 33 },
163 .p2
= { .dot_limit
= 165000,
164 .p2_slow
= 4, .p2_fast
= 2 },
167 static const intel_limit_t intel_limits_i8xx_dvo
= {
168 .dot
= { .min
= 25000, .max
= 350000 },
169 .vco
= { .min
= 908000, .max
= 1512000 },
170 .n
= { .min
= 2, .max
= 16 },
171 .m
= { .min
= 96, .max
= 140 },
172 .m1
= { .min
= 18, .max
= 26 },
173 .m2
= { .min
= 6, .max
= 16 },
174 .p
= { .min
= 4, .max
= 128 },
175 .p1
= { .min
= 2, .max
= 33 },
176 .p2
= { .dot_limit
= 165000,
177 .p2_slow
= 4, .p2_fast
= 4 },
180 static const intel_limit_t intel_limits_i8xx_lvds
= {
181 .dot
= { .min
= 25000, .max
= 350000 },
182 .vco
= { .min
= 908000, .max
= 1512000 },
183 .n
= { .min
= 2, .max
= 16 },
184 .m
= { .min
= 96, .max
= 140 },
185 .m1
= { .min
= 18, .max
= 26 },
186 .m2
= { .min
= 6, .max
= 16 },
187 .p
= { .min
= 4, .max
= 128 },
188 .p1
= { .min
= 1, .max
= 6 },
189 .p2
= { .dot_limit
= 165000,
190 .p2_slow
= 14, .p2_fast
= 7 },
193 static const intel_limit_t intel_limits_i9xx_sdvo
= {
194 .dot
= { .min
= 20000, .max
= 400000 },
195 .vco
= { .min
= 1400000, .max
= 2800000 },
196 .n
= { .min
= 1, .max
= 6 },
197 .m
= { .min
= 70, .max
= 120 },
198 .m1
= { .min
= 8, .max
= 18 },
199 .m2
= { .min
= 3, .max
= 7 },
200 .p
= { .min
= 5, .max
= 80 },
201 .p1
= { .min
= 1, .max
= 8 },
202 .p2
= { .dot_limit
= 200000,
203 .p2_slow
= 10, .p2_fast
= 5 },
206 static const intel_limit_t intel_limits_i9xx_lvds
= {
207 .dot
= { .min
= 20000, .max
= 400000 },
208 .vco
= { .min
= 1400000, .max
= 2800000 },
209 .n
= { .min
= 1, .max
= 6 },
210 .m
= { .min
= 70, .max
= 120 },
211 .m1
= { .min
= 8, .max
= 18 },
212 .m2
= { .min
= 3, .max
= 7 },
213 .p
= { .min
= 7, .max
= 98 },
214 .p1
= { .min
= 1, .max
= 8 },
215 .p2
= { .dot_limit
= 112000,
216 .p2_slow
= 14, .p2_fast
= 7 },
220 static const intel_limit_t intel_limits_g4x_sdvo
= {
221 .dot
= { .min
= 25000, .max
= 270000 },
222 .vco
= { .min
= 1750000, .max
= 3500000},
223 .n
= { .min
= 1, .max
= 4 },
224 .m
= { .min
= 104, .max
= 138 },
225 .m1
= { .min
= 17, .max
= 23 },
226 .m2
= { .min
= 5, .max
= 11 },
227 .p
= { .min
= 10, .max
= 30 },
228 .p1
= { .min
= 1, .max
= 3},
229 .p2
= { .dot_limit
= 270000,
235 static const intel_limit_t intel_limits_g4x_hdmi
= {
236 .dot
= { .min
= 22000, .max
= 400000 },
237 .vco
= { .min
= 1750000, .max
= 3500000},
238 .n
= { .min
= 1, .max
= 4 },
239 .m
= { .min
= 104, .max
= 138 },
240 .m1
= { .min
= 16, .max
= 23 },
241 .m2
= { .min
= 5, .max
= 11 },
242 .p
= { .min
= 5, .max
= 80 },
243 .p1
= { .min
= 1, .max
= 8},
244 .p2
= { .dot_limit
= 165000,
245 .p2_slow
= 10, .p2_fast
= 5 },
248 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
249 .dot
= { .min
= 20000, .max
= 115000 },
250 .vco
= { .min
= 1750000, .max
= 3500000 },
251 .n
= { .min
= 1, .max
= 3 },
252 .m
= { .min
= 104, .max
= 138 },
253 .m1
= { .min
= 17, .max
= 23 },
254 .m2
= { .min
= 5, .max
= 11 },
255 .p
= { .min
= 28, .max
= 112 },
256 .p1
= { .min
= 2, .max
= 8 },
257 .p2
= { .dot_limit
= 0,
258 .p2_slow
= 14, .p2_fast
= 14
262 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
263 .dot
= { .min
= 80000, .max
= 224000 },
264 .vco
= { .min
= 1750000, .max
= 3500000 },
265 .n
= { .min
= 1, .max
= 3 },
266 .m
= { .min
= 104, .max
= 138 },
267 .m1
= { .min
= 17, .max
= 23 },
268 .m2
= { .min
= 5, .max
= 11 },
269 .p
= { .min
= 14, .max
= 42 },
270 .p1
= { .min
= 2, .max
= 6 },
271 .p2
= { .dot_limit
= 0,
272 .p2_slow
= 7, .p2_fast
= 7
276 static const intel_limit_t intel_limits_pineview_sdvo
= {
277 .dot
= { .min
= 20000, .max
= 400000},
278 .vco
= { .min
= 1700000, .max
= 3500000 },
279 /* Pineview's Ncounter is a ring counter */
280 .n
= { .min
= 3, .max
= 6 },
281 .m
= { .min
= 2, .max
= 256 },
282 /* Pineview only has one combined m divider, which we treat as m2. */
283 .m1
= { .min
= 0, .max
= 0 },
284 .m2
= { .min
= 0, .max
= 254 },
285 .p
= { .min
= 5, .max
= 80 },
286 .p1
= { .min
= 1, .max
= 8 },
287 .p2
= { .dot_limit
= 200000,
288 .p2_slow
= 10, .p2_fast
= 5 },
291 static const intel_limit_t intel_limits_pineview_lvds
= {
292 .dot
= { .min
= 20000, .max
= 400000 },
293 .vco
= { .min
= 1700000, .max
= 3500000 },
294 .n
= { .min
= 3, .max
= 6 },
295 .m
= { .min
= 2, .max
= 256 },
296 .m1
= { .min
= 0, .max
= 0 },
297 .m2
= { .min
= 0, .max
= 254 },
298 .p
= { .min
= 7, .max
= 112 },
299 .p1
= { .min
= 1, .max
= 8 },
300 .p2
= { .dot_limit
= 112000,
301 .p2_slow
= 14, .p2_fast
= 14 },
304 /* Ironlake / Sandybridge
306 * We calculate clock using (register_value + 2) for N/M1/M2, so here
307 * the range value for them is (actual_value - 2).
309 static const intel_limit_t intel_limits_ironlake_dac
= {
310 .dot
= { .min
= 25000, .max
= 350000 },
311 .vco
= { .min
= 1760000, .max
= 3510000 },
312 .n
= { .min
= 1, .max
= 5 },
313 .m
= { .min
= 79, .max
= 127 },
314 .m1
= { .min
= 12, .max
= 22 },
315 .m2
= { .min
= 5, .max
= 9 },
316 .p
= { .min
= 5, .max
= 80 },
317 .p1
= { .min
= 1, .max
= 8 },
318 .p2
= { .dot_limit
= 225000,
319 .p2_slow
= 10, .p2_fast
= 5 },
322 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
323 .dot
= { .min
= 25000, .max
= 350000 },
324 .vco
= { .min
= 1760000, .max
= 3510000 },
325 .n
= { .min
= 1, .max
= 3 },
326 .m
= { .min
= 79, .max
= 118 },
327 .m1
= { .min
= 12, .max
= 22 },
328 .m2
= { .min
= 5, .max
= 9 },
329 .p
= { .min
= 28, .max
= 112 },
330 .p1
= { .min
= 2, .max
= 8 },
331 .p2
= { .dot_limit
= 225000,
332 .p2_slow
= 14, .p2_fast
= 14 },
335 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
336 .dot
= { .min
= 25000, .max
= 350000 },
337 .vco
= { .min
= 1760000, .max
= 3510000 },
338 .n
= { .min
= 1, .max
= 3 },
339 .m
= { .min
= 79, .max
= 127 },
340 .m1
= { .min
= 12, .max
= 22 },
341 .m2
= { .min
= 5, .max
= 9 },
342 .p
= { .min
= 14, .max
= 56 },
343 .p1
= { .min
= 2, .max
= 8 },
344 .p2
= { .dot_limit
= 225000,
345 .p2_slow
= 7, .p2_fast
= 7 },
348 /* LVDS 100mhz refclk limits. */
349 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
350 .dot
= { .min
= 25000, .max
= 350000 },
351 .vco
= { .min
= 1760000, .max
= 3510000 },
352 .n
= { .min
= 1, .max
= 2 },
353 .m
= { .min
= 79, .max
= 126 },
354 .m1
= { .min
= 12, .max
= 22 },
355 .m2
= { .min
= 5, .max
= 9 },
356 .p
= { .min
= 28, .max
= 112 },
357 .p1
= { .min
= 2, .max
= 8 },
358 .p2
= { .dot_limit
= 225000,
359 .p2_slow
= 14, .p2_fast
= 14 },
362 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
363 .dot
= { .min
= 25000, .max
= 350000 },
364 .vco
= { .min
= 1760000, .max
= 3510000 },
365 .n
= { .min
= 1, .max
= 3 },
366 .m
= { .min
= 79, .max
= 126 },
367 .m1
= { .min
= 12, .max
= 22 },
368 .m2
= { .min
= 5, .max
= 9 },
369 .p
= { .min
= 14, .max
= 42 },
370 .p1
= { .min
= 2, .max
= 6 },
371 .p2
= { .dot_limit
= 225000,
372 .p2_slow
= 7, .p2_fast
= 7 },
375 static const intel_limit_t intel_limits_vlv
= {
377 * These are the data rate limits (measured in fast clocks)
378 * since those are the strictest limits we have. The fast
379 * clock and actual rate limits are more relaxed, so checking
380 * them would make no difference.
382 .dot
= { .min
= 25000 * 5, .max
= 270000 * 5 },
383 .vco
= { .min
= 4000000, .max
= 6000000 },
384 .n
= { .min
= 1, .max
= 7 },
385 .m1
= { .min
= 2, .max
= 3 },
386 .m2
= { .min
= 11, .max
= 156 },
387 .p1
= { .min
= 2, .max
= 3 },
388 .p2
= { .p2_slow
= 2, .p2_fast
= 20 }, /* slow=min, fast=max */
391 static const intel_limit_t intel_limits_chv
= {
393 * These are the data rate limits (measured in fast clocks)
394 * since those are the strictest limits we have. The fast
395 * clock and actual rate limits are more relaxed, so checking
396 * them would make no difference.
398 .dot
= { .min
= 25000 * 5, .max
= 540000 * 5},
399 .vco
= { .min
= 4800000, .max
= 6480000 },
400 .n
= { .min
= 1, .max
= 1 },
401 .m1
= { .min
= 2, .max
= 2 },
402 .m2
= { .min
= 24 << 22, .max
= 175 << 22 },
403 .p1
= { .min
= 2, .max
= 4 },
404 .p2
= { .p2_slow
= 1, .p2_fast
= 14 },
407 static const intel_limit_t intel_limits_bxt
= {
408 /* FIXME: find real dot limits */
409 .dot
= { .min
= 0, .max
= INT_MAX
},
410 .vco
= { .min
= 4800000, .max
= 6480000 },
411 .n
= { .min
= 1, .max
= 1 },
412 .m1
= { .min
= 2, .max
= 2 },
413 /* FIXME: find real m2 limits */
414 .m2
= { .min
= 2 << 22, .max
= 255 << 22 },
415 .p1
= { .min
= 2, .max
= 4 },
416 .p2
= { .p2_slow
= 1, .p2_fast
= 20 },
419 static void vlv_clock(int refclk
, intel_clock_t
*clock
)
421 clock
->m
= clock
->m1
* clock
->m2
;
422 clock
->p
= clock
->p1
* clock
->p2
;
423 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
425 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
426 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
430 * Returns whether any output on the specified pipe is of the specified type
432 bool intel_pipe_has_type(struct intel_crtc
*crtc
, enum intel_output_type type
)
434 struct drm_device
*dev
= crtc
->base
.dev
;
435 struct intel_encoder
*encoder
;
437 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
)
438 if (encoder
->type
== type
)
445 * Returns whether any output on the specified pipe will have the specified
446 * type after a staged modeset is complete, i.e., the same as
447 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
450 static bool intel_pipe_will_have_type(const struct intel_crtc_state
*crtc_state
,
453 struct drm_atomic_state
*state
= crtc_state
->base
.state
;
454 struct drm_connector
*connector
;
455 struct drm_connector_state
*connector_state
;
456 struct intel_encoder
*encoder
;
457 int i
, num_connectors
= 0;
459 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
460 if (connector_state
->crtc
!= crtc_state
->base
.crtc
)
465 encoder
= to_intel_encoder(connector_state
->best_encoder
);
466 if (encoder
->type
== type
)
470 WARN_ON(num_connectors
== 0);
475 static const intel_limit_t
*
476 intel_ironlake_limit(struct intel_crtc_state
*crtc_state
, int refclk
)
478 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
479 const intel_limit_t
*limit
;
481 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
482 if (intel_is_dual_link_lvds(dev
)) {
483 if (refclk
== 100000)
484 limit
= &intel_limits_ironlake_dual_lvds_100m
;
486 limit
= &intel_limits_ironlake_dual_lvds
;
488 if (refclk
== 100000)
489 limit
= &intel_limits_ironlake_single_lvds_100m
;
491 limit
= &intel_limits_ironlake_single_lvds
;
494 limit
= &intel_limits_ironlake_dac
;
499 static const intel_limit_t
*
500 intel_g4x_limit(struct intel_crtc_state
*crtc_state
)
502 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
503 const intel_limit_t
*limit
;
505 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
506 if (intel_is_dual_link_lvds(dev
))
507 limit
= &intel_limits_g4x_dual_channel_lvds
;
509 limit
= &intel_limits_g4x_single_channel_lvds
;
510 } else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_HDMI
) ||
511 intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_ANALOG
)) {
512 limit
= &intel_limits_g4x_hdmi
;
513 } else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_SDVO
)) {
514 limit
= &intel_limits_g4x_sdvo
;
515 } else /* The option is for other outputs */
516 limit
= &intel_limits_i9xx_sdvo
;
521 static const intel_limit_t
*
522 intel_limit(struct intel_crtc_state
*crtc_state
, int refclk
)
524 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
525 const intel_limit_t
*limit
;
528 limit
= &intel_limits_bxt
;
529 else if (HAS_PCH_SPLIT(dev
))
530 limit
= intel_ironlake_limit(crtc_state
, refclk
);
531 else if (IS_G4X(dev
)) {
532 limit
= intel_g4x_limit(crtc_state
);
533 } else if (IS_PINEVIEW(dev
)) {
534 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
))
535 limit
= &intel_limits_pineview_lvds
;
537 limit
= &intel_limits_pineview_sdvo
;
538 } else if (IS_CHERRYVIEW(dev
)) {
539 limit
= &intel_limits_chv
;
540 } else if (IS_VALLEYVIEW(dev
)) {
541 limit
= &intel_limits_vlv
;
542 } else if (!IS_GEN2(dev
)) {
543 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
))
544 limit
= &intel_limits_i9xx_lvds
;
546 limit
= &intel_limits_i9xx_sdvo
;
548 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
))
549 limit
= &intel_limits_i8xx_lvds
;
550 else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_DVO
))
551 limit
= &intel_limits_i8xx_dvo
;
553 limit
= &intel_limits_i8xx_dac
;
558 /* m1 is reserved as 0 in Pineview, n is a ring counter */
559 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
561 clock
->m
= clock
->m2
+ 2;
562 clock
->p
= clock
->p1
* clock
->p2
;
563 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
565 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
566 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
569 static uint32_t i9xx_dpll_compute_m(struct dpll
*dpll
)
571 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
574 static void i9xx_clock(int refclk
, intel_clock_t
*clock
)
576 clock
->m
= i9xx_dpll_compute_m(clock
);
577 clock
->p
= clock
->p1
* clock
->p2
;
578 if (WARN_ON(clock
->n
+ 2 == 0 || clock
->p
== 0))
580 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
+ 2);
581 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
584 static void chv_clock(int refclk
, intel_clock_t
*clock
)
586 clock
->m
= clock
->m1
* clock
->m2
;
587 clock
->p
= clock
->p1
* clock
->p2
;
588 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
590 clock
->vco
= DIV_ROUND_CLOSEST_ULL((uint64_t)refclk
* clock
->m
,
592 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
595 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
597 * Returns whether the given set of divisors are valid for a given refclk with
598 * the given connectors.
601 static bool intel_PLL_is_valid(struct drm_device
*dev
,
602 const intel_limit_t
*limit
,
603 const intel_clock_t
*clock
)
605 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
606 INTELPllInvalid("n out of range\n");
607 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
608 INTELPllInvalid("p1 out of range\n");
609 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
610 INTELPllInvalid("m2 out of range\n");
611 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
612 INTELPllInvalid("m1 out of range\n");
614 if (!IS_PINEVIEW(dev
) && !IS_VALLEYVIEW(dev
) && !IS_BROXTON(dev
))
615 if (clock
->m1
<= clock
->m2
)
616 INTELPllInvalid("m1 <= m2\n");
618 if (!IS_VALLEYVIEW(dev
) && !IS_BROXTON(dev
)) {
619 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
620 INTELPllInvalid("p out of range\n");
621 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
622 INTELPllInvalid("m out of range\n");
625 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
626 INTELPllInvalid("vco out of range\n");
627 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
628 * connector, etc., rather than just a single range.
630 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
631 INTELPllInvalid("dot out of range\n");
637 i9xx_find_best_dpll(const intel_limit_t
*limit
,
638 struct intel_crtc_state
*crtc_state
,
639 int target
, int refclk
, intel_clock_t
*match_clock
,
640 intel_clock_t
*best_clock
)
642 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
643 struct drm_device
*dev
= crtc
->base
.dev
;
647 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
649 * For LVDS just rely on its current settings for dual-channel.
650 * We haven't figured out how to reliably set up different
651 * single/dual channel state, if we even can.
653 if (intel_is_dual_link_lvds(dev
))
654 clock
.p2
= limit
->p2
.p2_fast
;
656 clock
.p2
= limit
->p2
.p2_slow
;
658 if (target
< limit
->p2
.dot_limit
)
659 clock
.p2
= limit
->p2
.p2_slow
;
661 clock
.p2
= limit
->p2
.p2_fast
;
664 memset(best_clock
, 0, sizeof(*best_clock
));
666 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
668 for (clock
.m2
= limit
->m2
.min
;
669 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
670 if (clock
.m2
>= clock
.m1
)
672 for (clock
.n
= limit
->n
.min
;
673 clock
.n
<= limit
->n
.max
; clock
.n
++) {
674 for (clock
.p1
= limit
->p1
.min
;
675 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
678 i9xx_clock(refclk
, &clock
);
679 if (!intel_PLL_is_valid(dev
, limit
,
683 clock
.p
!= match_clock
->p
)
686 this_err
= abs(clock
.dot
- target
);
687 if (this_err
< err
) {
696 return (err
!= target
);
700 pnv_find_best_dpll(const intel_limit_t
*limit
,
701 struct intel_crtc_state
*crtc_state
,
702 int target
, int refclk
, intel_clock_t
*match_clock
,
703 intel_clock_t
*best_clock
)
705 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
706 struct drm_device
*dev
= crtc
->base
.dev
;
710 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
712 * For LVDS just rely on its current settings for dual-channel.
713 * We haven't figured out how to reliably set up different
714 * single/dual channel state, if we even can.
716 if (intel_is_dual_link_lvds(dev
))
717 clock
.p2
= limit
->p2
.p2_fast
;
719 clock
.p2
= limit
->p2
.p2_slow
;
721 if (target
< limit
->p2
.dot_limit
)
722 clock
.p2
= limit
->p2
.p2_slow
;
724 clock
.p2
= limit
->p2
.p2_fast
;
727 memset(best_clock
, 0, sizeof(*best_clock
));
729 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
731 for (clock
.m2
= limit
->m2
.min
;
732 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
733 for (clock
.n
= limit
->n
.min
;
734 clock
.n
<= limit
->n
.max
; clock
.n
++) {
735 for (clock
.p1
= limit
->p1
.min
;
736 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
739 pineview_clock(refclk
, &clock
);
740 if (!intel_PLL_is_valid(dev
, limit
,
744 clock
.p
!= match_clock
->p
)
747 this_err
= abs(clock
.dot
- target
);
748 if (this_err
< err
) {
757 return (err
!= target
);
761 g4x_find_best_dpll(const intel_limit_t
*limit
,
762 struct intel_crtc_state
*crtc_state
,
763 int target
, int refclk
, intel_clock_t
*match_clock
,
764 intel_clock_t
*best_clock
)
766 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
767 struct drm_device
*dev
= crtc
->base
.dev
;
771 /* approximately equals target * 0.00585 */
772 int err_most
= (target
>> 8) + (target
>> 9);
775 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
776 if (intel_is_dual_link_lvds(dev
))
777 clock
.p2
= limit
->p2
.p2_fast
;
779 clock
.p2
= limit
->p2
.p2_slow
;
781 if (target
< limit
->p2
.dot_limit
)
782 clock
.p2
= limit
->p2
.p2_slow
;
784 clock
.p2
= limit
->p2
.p2_fast
;
787 memset(best_clock
, 0, sizeof(*best_clock
));
788 max_n
= limit
->n
.max
;
789 /* based on hardware requirement, prefer smaller n to precision */
790 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
791 /* based on hardware requirement, prefere larger m1,m2 */
792 for (clock
.m1
= limit
->m1
.max
;
793 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
794 for (clock
.m2
= limit
->m2
.max
;
795 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
796 for (clock
.p1
= limit
->p1
.max
;
797 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
800 i9xx_clock(refclk
, &clock
);
801 if (!intel_PLL_is_valid(dev
, limit
,
805 this_err
= abs(clock
.dot
- target
);
806 if (this_err
< err_most
) {
820 * Check if the calculated PLL configuration is more optimal compared to the
821 * best configuration and error found so far. Return the calculated error.
823 static bool vlv_PLL_is_optimal(struct drm_device
*dev
, int target_freq
,
824 const intel_clock_t
*calculated_clock
,
825 const intel_clock_t
*best_clock
,
826 unsigned int best_error_ppm
,
827 unsigned int *error_ppm
)
830 * For CHV ignore the error and consider only the P value.
831 * Prefer a bigger P value based on HW requirements.
833 if (IS_CHERRYVIEW(dev
)) {
836 return calculated_clock
->p
> best_clock
->p
;
839 if (WARN_ON_ONCE(!target_freq
))
842 *error_ppm
= div_u64(1000000ULL *
843 abs(target_freq
- calculated_clock
->dot
),
846 * Prefer a better P value over a better (smaller) error if the error
847 * is small. Ensure this preference for future configurations too by
848 * setting the error to 0.
850 if (*error_ppm
< 100 && calculated_clock
->p
> best_clock
->p
) {
856 return *error_ppm
+ 10 < best_error_ppm
;
860 vlv_find_best_dpll(const intel_limit_t
*limit
,
861 struct intel_crtc_state
*crtc_state
,
862 int target
, int refclk
, intel_clock_t
*match_clock
,
863 intel_clock_t
*best_clock
)
865 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
866 struct drm_device
*dev
= crtc
->base
.dev
;
868 unsigned int bestppm
= 1000000;
869 /* min update 19.2 MHz */
870 int max_n
= min(limit
->n
.max
, refclk
/ 19200);
873 target
*= 5; /* fast clock */
875 memset(best_clock
, 0, sizeof(*best_clock
));
877 /* based on hardware requirement, prefer smaller n to precision */
878 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
879 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
880 for (clock
.p2
= limit
->p2
.p2_fast
; clock
.p2
>= limit
->p2
.p2_slow
;
881 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
882 clock
.p
= clock
.p1
* clock
.p2
;
883 /* based on hardware requirement, prefer bigger m1,m2 values */
884 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
; clock
.m1
++) {
887 clock
.m2
= DIV_ROUND_CLOSEST(target
* clock
.p
* clock
.n
,
890 vlv_clock(refclk
, &clock
);
892 if (!intel_PLL_is_valid(dev
, limit
,
896 if (!vlv_PLL_is_optimal(dev
, target
,
914 chv_find_best_dpll(const intel_limit_t
*limit
,
915 struct intel_crtc_state
*crtc_state
,
916 int target
, int refclk
, intel_clock_t
*match_clock
,
917 intel_clock_t
*best_clock
)
919 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
920 struct drm_device
*dev
= crtc
->base
.dev
;
921 unsigned int best_error_ppm
;
926 memset(best_clock
, 0, sizeof(*best_clock
));
927 best_error_ppm
= 1000000;
930 * Based on hardware doc, the n always set to 1, and m1 always
931 * set to 2. If requires to support 200Mhz refclk, we need to
932 * revisit this because n may not 1 anymore.
934 clock
.n
= 1, clock
.m1
= 2;
935 target
*= 5; /* fast clock */
937 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
938 for (clock
.p2
= limit
->p2
.p2_fast
;
939 clock
.p2
>= limit
->p2
.p2_slow
;
940 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
941 unsigned int error_ppm
;
943 clock
.p
= clock
.p1
* clock
.p2
;
945 m2
= DIV_ROUND_CLOSEST_ULL(((uint64_t)target
* clock
.p
*
946 clock
.n
) << 22, refclk
* clock
.m1
);
948 if (m2
> INT_MAX
/clock
.m1
)
953 chv_clock(refclk
, &clock
);
955 if (!intel_PLL_is_valid(dev
, limit
, &clock
))
958 if (!vlv_PLL_is_optimal(dev
, target
, &clock
, best_clock
,
959 best_error_ppm
, &error_ppm
))
963 best_error_ppm
= error_ppm
;
971 bool bxt_find_best_dpll(struct intel_crtc_state
*crtc_state
, int target_clock
,
972 intel_clock_t
*best_clock
)
974 int refclk
= i9xx_get_refclk(crtc_state
, 0);
976 return chv_find_best_dpll(intel_limit(crtc_state
, refclk
), crtc_state
,
977 target_clock
, refclk
, NULL
, best_clock
);
980 bool intel_crtc_active(struct drm_crtc
*crtc
)
982 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
984 /* Be paranoid as we can arrive here with only partial
985 * state retrieved from the hardware during setup.
987 * We can ditch the adjusted_mode.crtc_clock check as soon
988 * as Haswell has gained clock readout/fastboot support.
990 * We can ditch the crtc->primary->fb check as soon as we can
991 * properly reconstruct framebuffers.
993 * FIXME: The intel_crtc->active here should be switched to
994 * crtc->state->active once we have proper CRTC states wired up
997 return intel_crtc
->active
&& crtc
->primary
->state
->fb
&&
998 intel_crtc
->config
->base
.adjusted_mode
.crtc_clock
;
1001 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
1004 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1005 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1007 return intel_crtc
->config
->cpu_transcoder
;
1010 static bool pipe_dsl_stopped(struct drm_device
*dev
, enum pipe pipe
)
1012 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1013 u32 reg
= PIPEDSL(pipe
);
1018 line_mask
= DSL_LINEMASK_GEN2
;
1020 line_mask
= DSL_LINEMASK_GEN3
;
1022 line1
= I915_READ(reg
) & line_mask
;
1024 line2
= I915_READ(reg
) & line_mask
;
1026 return line1
== line2
;
1030 * intel_wait_for_pipe_off - wait for pipe to turn off
1031 * @crtc: crtc whose pipe to wait for
1033 * After disabling a pipe, we can't wait for vblank in the usual way,
1034 * spinning on the vblank interrupt status bit, since we won't actually
1035 * see an interrupt when the pipe is disabled.
1037 * On Gen4 and above:
1038 * wait for the pipe register state bit to turn off
1041 * wait for the display line value to settle (it usually
1042 * ends up stopping at the start of the next frame).
1045 static void intel_wait_for_pipe_off(struct intel_crtc
*crtc
)
1047 struct drm_device
*dev
= crtc
->base
.dev
;
1048 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1049 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
1050 enum pipe pipe
= crtc
->pipe
;
1052 if (INTEL_INFO(dev
)->gen
>= 4) {
1053 int reg
= PIPECONF(cpu_transcoder
);
1055 /* Wait for the Pipe State to go off */
1056 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
1058 WARN(1, "pipe_off wait timed out\n");
1060 /* Wait for the display line to settle */
1061 if (wait_for(pipe_dsl_stopped(dev
, pipe
), 100))
1062 WARN(1, "pipe_off wait timed out\n");
1067 * ibx_digital_port_connected - is the specified port connected?
1068 * @dev_priv: i915 private structure
1069 * @port: the port to test
1071 * Returns true if @port is connected, false otherwise.
1073 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
1074 struct intel_digital_port
*port
)
1078 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1079 switch (port
->port
) {
1081 bit
= SDE_PORTB_HOTPLUG
;
1084 bit
= SDE_PORTC_HOTPLUG
;
1087 bit
= SDE_PORTD_HOTPLUG
;
1093 switch (port
->port
) {
1095 bit
= SDE_PORTB_HOTPLUG_CPT
;
1098 bit
= SDE_PORTC_HOTPLUG_CPT
;
1101 bit
= SDE_PORTD_HOTPLUG_CPT
;
1108 return I915_READ(SDEISR
) & bit
;
1111 static const char *state_string(bool enabled
)
1113 return enabled
? "on" : "off";
1116 /* Only for pre-ILK configs */
1117 void assert_pll(struct drm_i915_private
*dev_priv
,
1118 enum pipe pipe
, bool state
)
1125 val
= I915_READ(reg
);
1126 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1127 I915_STATE_WARN(cur_state
!= state
,
1128 "PLL state assertion failure (expected %s, current %s)\n",
1129 state_string(state
), state_string(cur_state
));
1132 /* XXX: the dsi pll is shared between MIPI DSI ports */
1133 static void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
)
1138 mutex_lock(&dev_priv
->dpio_lock
);
1139 val
= vlv_cck_read(dev_priv
, CCK_REG_DSI_PLL_CONTROL
);
1140 mutex_unlock(&dev_priv
->dpio_lock
);
1142 cur_state
= val
& DSI_PLL_VCO_EN
;
1143 I915_STATE_WARN(cur_state
!= state
,
1144 "DSI PLL state assertion failure (expected %s, current %s)\n",
1145 state_string(state
), state_string(cur_state
));
1147 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1148 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1150 struct intel_shared_dpll
*
1151 intel_crtc_to_shared_dpll(struct intel_crtc
*crtc
)
1153 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1155 if (crtc
->config
->shared_dpll
< 0)
1158 return &dev_priv
->shared_dplls
[crtc
->config
->shared_dpll
];
1162 void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
1163 struct intel_shared_dpll
*pll
,
1167 struct intel_dpll_hw_state hw_state
;
1170 "asserting DPLL %s with no DPLL\n", state_string(state
)))
1173 cur_state
= pll
->get_hw_state(dev_priv
, pll
, &hw_state
);
1174 I915_STATE_WARN(cur_state
!= state
,
1175 "%s assertion failure (expected %s, current %s)\n",
1176 pll
->name
, state_string(state
), state_string(cur_state
));
1179 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1180 enum pipe pipe
, bool state
)
1185 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1188 if (HAS_DDI(dev_priv
->dev
)) {
1189 /* DDI does not have a specific FDI_TX register */
1190 reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1191 val
= I915_READ(reg
);
1192 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
1194 reg
= FDI_TX_CTL(pipe
);
1195 val
= I915_READ(reg
);
1196 cur_state
= !!(val
& FDI_TX_ENABLE
);
1198 I915_STATE_WARN(cur_state
!= state
,
1199 "FDI TX state assertion failure (expected %s, current %s)\n",
1200 state_string(state
), state_string(cur_state
));
1202 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1203 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1205 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1206 enum pipe pipe
, bool state
)
1212 reg
= FDI_RX_CTL(pipe
);
1213 val
= I915_READ(reg
);
1214 cur_state
= !!(val
& FDI_RX_ENABLE
);
1215 I915_STATE_WARN(cur_state
!= state
,
1216 "FDI RX state assertion failure (expected %s, current %s)\n",
1217 state_string(state
), state_string(cur_state
));
1219 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1220 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1222 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1228 /* ILK FDI PLL is always enabled */
1229 if (INTEL_INFO(dev_priv
->dev
)->gen
== 5)
1232 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1233 if (HAS_DDI(dev_priv
->dev
))
1236 reg
= FDI_TX_CTL(pipe
);
1237 val
= I915_READ(reg
);
1238 I915_STATE_WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1241 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1242 enum pipe pipe
, bool state
)
1248 reg
= FDI_RX_CTL(pipe
);
1249 val
= I915_READ(reg
);
1250 cur_state
= !!(val
& FDI_RX_PLL_ENABLE
);
1251 I915_STATE_WARN(cur_state
!= state
,
1252 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1253 state_string(state
), state_string(cur_state
));
1256 void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1259 struct drm_device
*dev
= dev_priv
->dev
;
1262 enum pipe panel_pipe
= PIPE_A
;
1265 if (WARN_ON(HAS_DDI(dev
)))
1268 if (HAS_PCH_SPLIT(dev
)) {
1271 pp_reg
= PCH_PP_CONTROL
;
1272 port_sel
= I915_READ(PCH_PP_ON_DELAYS
) & PANEL_PORT_SELECT_MASK
;
1274 if (port_sel
== PANEL_PORT_SELECT_LVDS
&&
1275 I915_READ(PCH_LVDS
) & LVDS_PIPEB_SELECT
)
1276 panel_pipe
= PIPE_B
;
1277 /* XXX: else fix for eDP */
1278 } else if (IS_VALLEYVIEW(dev
)) {
1279 /* presumably write lock depends on pipe, not port select */
1280 pp_reg
= VLV_PIPE_PP_CONTROL(pipe
);
1283 pp_reg
= PP_CONTROL
;
1284 if (I915_READ(LVDS
) & LVDS_PIPEB_SELECT
)
1285 panel_pipe
= PIPE_B
;
1288 val
= I915_READ(pp_reg
);
1289 if (!(val
& PANEL_POWER_ON
) ||
1290 ((val
& PANEL_UNLOCK_MASK
) == PANEL_UNLOCK_REGS
))
1293 I915_STATE_WARN(panel_pipe
== pipe
&& locked
,
1294 "panel assertion failure, pipe %c regs locked\n",
1298 static void assert_cursor(struct drm_i915_private
*dev_priv
,
1299 enum pipe pipe
, bool state
)
1301 struct drm_device
*dev
= dev_priv
->dev
;
1304 if (IS_845G(dev
) || IS_I865G(dev
))
1305 cur_state
= I915_READ(_CURACNTR
) & CURSOR_ENABLE
;
1307 cur_state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
1309 I915_STATE_WARN(cur_state
!= state
,
1310 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1311 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1313 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1314 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1316 void assert_pipe(struct drm_i915_private
*dev_priv
,
1317 enum pipe pipe
, bool state
)
1322 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1325 /* if we need the pipe quirk it must be always on */
1326 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1327 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1330 if (!intel_display_power_is_enabled(dev_priv
,
1331 POWER_DOMAIN_TRANSCODER(cpu_transcoder
))) {
1334 reg
= PIPECONF(cpu_transcoder
);
1335 val
= I915_READ(reg
);
1336 cur_state
= !!(val
& PIPECONF_ENABLE
);
1339 I915_STATE_WARN(cur_state
!= state
,
1340 "pipe %c assertion failure (expected %s, current %s)\n",
1341 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1344 static void assert_plane(struct drm_i915_private
*dev_priv
,
1345 enum plane plane
, bool state
)
1351 reg
= DSPCNTR(plane
);
1352 val
= I915_READ(reg
);
1353 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1354 I915_STATE_WARN(cur_state
!= state
,
1355 "plane %c assertion failure (expected %s, current %s)\n",
1356 plane_name(plane
), state_string(state
), state_string(cur_state
));
1359 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1360 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1362 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1365 struct drm_device
*dev
= dev_priv
->dev
;
1370 /* Primary planes are fixed to pipes on gen4+ */
1371 if (INTEL_INFO(dev
)->gen
>= 4) {
1372 reg
= DSPCNTR(pipe
);
1373 val
= I915_READ(reg
);
1374 I915_STATE_WARN(val
& DISPLAY_PLANE_ENABLE
,
1375 "plane %c assertion failure, should be disabled but not\n",
1380 /* Need to check both planes against the pipe */
1381 for_each_pipe(dev_priv
, i
) {
1383 val
= I915_READ(reg
);
1384 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1385 DISPPLANE_SEL_PIPE_SHIFT
;
1386 I915_STATE_WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1387 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1388 plane_name(i
), pipe_name(pipe
));
1392 static void assert_sprites_disabled(struct drm_i915_private
*dev_priv
,
1395 struct drm_device
*dev
= dev_priv
->dev
;
1399 if (INTEL_INFO(dev
)->gen
>= 9) {
1400 for_each_sprite(dev_priv
, pipe
, sprite
) {
1401 val
= I915_READ(PLANE_CTL(pipe
, sprite
));
1402 I915_STATE_WARN(val
& PLANE_CTL_ENABLE
,
1403 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1404 sprite
, pipe_name(pipe
));
1406 } else if (IS_VALLEYVIEW(dev
)) {
1407 for_each_sprite(dev_priv
, pipe
, sprite
) {
1408 reg
= SPCNTR(pipe
, sprite
);
1409 val
= I915_READ(reg
);
1410 I915_STATE_WARN(val
& SP_ENABLE
,
1411 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1412 sprite_name(pipe
, sprite
), pipe_name(pipe
));
1414 } else if (INTEL_INFO(dev
)->gen
>= 7) {
1416 val
= I915_READ(reg
);
1417 I915_STATE_WARN(val
& SPRITE_ENABLE
,
1418 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1419 plane_name(pipe
), pipe_name(pipe
));
1420 } else if (INTEL_INFO(dev
)->gen
>= 5) {
1421 reg
= DVSCNTR(pipe
);
1422 val
= I915_READ(reg
);
1423 I915_STATE_WARN(val
& DVS_ENABLE
,
1424 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1425 plane_name(pipe
), pipe_name(pipe
));
1429 static void assert_vblank_disabled(struct drm_crtc
*crtc
)
1431 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc
) == 0))
1432 drm_crtc_vblank_put(crtc
);
1435 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1440 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv
->dev
) || HAS_PCH_CPT(dev_priv
->dev
)));
1442 val
= I915_READ(PCH_DREF_CONTROL
);
1443 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1444 DREF_SUPERSPREAD_SOURCE_MASK
));
1445 I915_STATE_WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1448 static void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1455 reg
= PCH_TRANSCONF(pipe
);
1456 val
= I915_READ(reg
);
1457 enabled
= !!(val
& TRANS_ENABLE
);
1458 I915_STATE_WARN(enabled
,
1459 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1463 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1464 enum pipe pipe
, u32 port_sel
, u32 val
)
1466 if ((val
& DP_PORT_EN
) == 0)
1469 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1470 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1471 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1472 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1474 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1475 if ((val
& DP_PIPE_MASK_CHV
) != DP_PIPE_SELECT_CHV(pipe
))
1478 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1484 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1485 enum pipe pipe
, u32 val
)
1487 if ((val
& SDVO_ENABLE
) == 0)
1490 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1491 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1493 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1494 if ((val
& SDVO_PIPE_SEL_MASK_CHV
) != SDVO_PIPE_SEL_CHV(pipe
))
1497 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1503 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1504 enum pipe pipe
, u32 val
)
1506 if ((val
& LVDS_PORT_EN
) == 0)
1509 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1510 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1513 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1519 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1520 enum pipe pipe
, u32 val
)
1522 if ((val
& ADPA_DAC_ENABLE
) == 0)
1524 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1525 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1528 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1534 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1535 enum pipe pipe
, int reg
, u32 port_sel
)
1537 u32 val
= I915_READ(reg
);
1538 I915_STATE_WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1539 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1540 reg
, pipe_name(pipe
));
1542 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& DP_PORT_EN
) == 0
1543 && (val
& DP_PIPEB_SELECT
),
1544 "IBX PCH dp port still using transcoder B\n");
1547 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1548 enum pipe pipe
, int reg
)
1550 u32 val
= I915_READ(reg
);
1551 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1552 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1553 reg
, pipe_name(pipe
));
1555 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& SDVO_ENABLE
) == 0
1556 && (val
& SDVO_PIPE_B_SELECT
),
1557 "IBX PCH hdmi port still using transcoder B\n");
1560 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1566 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1567 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1568 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1571 val
= I915_READ(reg
);
1572 I915_STATE_WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1573 "PCH VGA enabled on transcoder %c, should be disabled\n",
1577 val
= I915_READ(reg
);
1578 I915_STATE_WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1579 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1582 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1583 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1584 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1587 static void intel_init_dpio(struct drm_device
*dev
)
1589 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1591 if (!IS_VALLEYVIEW(dev
))
1595 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1596 * CHV x1 PHY (DP/HDMI D)
1597 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1599 if (IS_CHERRYVIEW(dev
)) {
1600 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO_2
;
1601 DPIO_PHY_IOSF_PORT(DPIO_PHY1
) = IOSF_PORT_DPIO
;
1603 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO
;
1607 static void vlv_enable_pll(struct intel_crtc
*crtc
,
1608 const struct intel_crtc_state
*pipe_config
)
1610 struct drm_device
*dev
= crtc
->base
.dev
;
1611 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1612 int reg
= DPLL(crtc
->pipe
);
1613 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
1615 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1617 /* No really, not for ILK+ */
1618 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
));
1620 /* PLL is protected by panel, make sure we can write it */
1621 if (IS_MOBILE(dev_priv
->dev
))
1622 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1624 I915_WRITE(reg
, dpll
);
1628 if (wait_for(((I915_READ(reg
) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1629 DRM_ERROR("DPLL %d failed to lock\n", crtc
->pipe
);
1631 I915_WRITE(DPLL_MD(crtc
->pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1632 POSTING_READ(DPLL_MD(crtc
->pipe
));
1634 /* We do this three times for luck */
1635 I915_WRITE(reg
, dpll
);
1637 udelay(150); /* wait for warmup */
1638 I915_WRITE(reg
, dpll
);
1640 udelay(150); /* wait for warmup */
1641 I915_WRITE(reg
, dpll
);
1643 udelay(150); /* wait for warmup */
1646 static void chv_enable_pll(struct intel_crtc
*crtc
,
1647 const struct intel_crtc_state
*pipe_config
)
1649 struct drm_device
*dev
= crtc
->base
.dev
;
1650 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1651 int pipe
= crtc
->pipe
;
1652 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1655 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1657 BUG_ON(!IS_CHERRYVIEW(dev_priv
->dev
));
1659 mutex_lock(&dev_priv
->dpio_lock
);
1661 /* Enable back the 10bit clock to display controller */
1662 tmp
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1663 tmp
|= DPIO_DCLKP_EN
;
1664 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), tmp
);
1667 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1672 I915_WRITE(DPLL(pipe
), pipe_config
->dpll_hw_state
.dpll
);
1674 /* Check PLL is locked */
1675 if (wait_for(((I915_READ(DPLL(pipe
)) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1676 DRM_ERROR("PLL %d failed to lock\n", pipe
);
1678 /* not sure when this should be written */
1679 I915_WRITE(DPLL_MD(pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1680 POSTING_READ(DPLL_MD(pipe
));
1682 mutex_unlock(&dev_priv
->dpio_lock
);
1685 static int intel_num_dvo_pipes(struct drm_device
*dev
)
1687 struct intel_crtc
*crtc
;
1690 for_each_intel_crtc(dev
, crtc
)
1691 count
+= crtc
->active
&&
1692 intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
);
1697 static void i9xx_enable_pll(struct intel_crtc
*crtc
)
1699 struct drm_device
*dev
= crtc
->base
.dev
;
1700 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1701 int reg
= DPLL(crtc
->pipe
);
1702 u32 dpll
= crtc
->config
->dpll_hw_state
.dpll
;
1704 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1706 /* No really, not for ILK+ */
1707 BUG_ON(INTEL_INFO(dev
)->gen
>= 5);
1709 /* PLL is protected by panel, make sure we can write it */
1710 if (IS_MOBILE(dev
) && !IS_I830(dev
))
1711 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1713 /* Enable DVO 2x clock on both PLLs if necessary */
1714 if (IS_I830(dev
) && intel_num_dvo_pipes(dev
) > 0) {
1716 * It appears to be important that we don't enable this
1717 * for the current pipe before otherwise configuring the
1718 * PLL. No idea how this should be handled if multiple
1719 * DVO outputs are enabled simultaneosly.
1721 dpll
|= DPLL_DVO_2X_MODE
;
1722 I915_WRITE(DPLL(!crtc
->pipe
),
1723 I915_READ(DPLL(!crtc
->pipe
)) | DPLL_DVO_2X_MODE
);
1726 /* Wait for the clocks to stabilize. */
1730 if (INTEL_INFO(dev
)->gen
>= 4) {
1731 I915_WRITE(DPLL_MD(crtc
->pipe
),
1732 crtc
->config
->dpll_hw_state
.dpll_md
);
1734 /* The pixel multiplier can only be updated once the
1735 * DPLL is enabled and the clocks are stable.
1737 * So write it again.
1739 I915_WRITE(reg
, dpll
);
1742 /* We do this three times for luck */
1743 I915_WRITE(reg
, dpll
);
1745 udelay(150); /* wait for warmup */
1746 I915_WRITE(reg
, dpll
);
1748 udelay(150); /* wait for warmup */
1749 I915_WRITE(reg
, dpll
);
1751 udelay(150); /* wait for warmup */
1755 * i9xx_disable_pll - disable a PLL
1756 * @dev_priv: i915 private structure
1757 * @pipe: pipe PLL to disable
1759 * Disable the PLL for @pipe, making sure the pipe is off first.
1761 * Note! This is for pre-ILK only.
1763 static void i9xx_disable_pll(struct intel_crtc
*crtc
)
1765 struct drm_device
*dev
= crtc
->base
.dev
;
1766 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1767 enum pipe pipe
= crtc
->pipe
;
1769 /* Disable DVO 2x clock on both PLLs if necessary */
1771 intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
) &&
1772 intel_num_dvo_pipes(dev
) == 1) {
1773 I915_WRITE(DPLL(PIPE_B
),
1774 I915_READ(DPLL(PIPE_B
)) & ~DPLL_DVO_2X_MODE
);
1775 I915_WRITE(DPLL(PIPE_A
),
1776 I915_READ(DPLL(PIPE_A
)) & ~DPLL_DVO_2X_MODE
);
1779 /* Don't disable pipe or pipe PLLs if needed */
1780 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1781 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1784 /* Make sure the pipe isn't still relying on us */
1785 assert_pipe_disabled(dev_priv
, pipe
);
1787 I915_WRITE(DPLL(pipe
), 0);
1788 POSTING_READ(DPLL(pipe
));
1791 static void vlv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1795 /* Make sure the pipe isn't still relying on us */
1796 assert_pipe_disabled(dev_priv
, pipe
);
1799 * Leave integrated clock source and reference clock enabled for pipe B.
1800 * The latter is needed for VGA hotplug / manual detection.
1803 val
= DPLL_INTEGRATED_CRI_CLK_VLV
| DPLL_REFA_CLK_ENABLE_VLV
;
1804 I915_WRITE(DPLL(pipe
), val
);
1805 POSTING_READ(DPLL(pipe
));
1809 static void chv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1811 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1814 /* Make sure the pipe isn't still relying on us */
1815 assert_pipe_disabled(dev_priv
, pipe
);
1817 /* Set PLL en = 0 */
1818 val
= DPLL_SSC_REF_CLOCK_CHV
| DPLL_REFA_CLK_ENABLE_VLV
;
1820 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
1821 I915_WRITE(DPLL(pipe
), val
);
1822 POSTING_READ(DPLL(pipe
));
1824 mutex_lock(&dev_priv
->dpio_lock
);
1826 /* Disable 10bit clock to display controller */
1827 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1828 val
&= ~DPIO_DCLKP_EN
;
1829 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), val
);
1831 /* disable left/right clock distribution */
1832 if (pipe
!= PIPE_B
) {
1833 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
);
1834 val
&= ~(CHV_BUFLEFTENA1_MASK
| CHV_BUFRIGHTENA1_MASK
);
1835 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
, val
);
1837 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
);
1838 val
&= ~(CHV_BUFLEFTENA2_MASK
| CHV_BUFRIGHTENA2_MASK
);
1839 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
, val
);
1842 mutex_unlock(&dev_priv
->dpio_lock
);
1845 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1846 struct intel_digital_port
*dport
,
1847 unsigned int expected_mask
)
1852 switch (dport
->port
) {
1854 port_mask
= DPLL_PORTB_READY_MASK
;
1858 port_mask
= DPLL_PORTC_READY_MASK
;
1860 expected_mask
<<= 4;
1863 port_mask
= DPLL_PORTD_READY_MASK
;
1864 dpll_reg
= DPIO_PHY_STATUS
;
1870 if (wait_for((I915_READ(dpll_reg
) & port_mask
) == expected_mask
, 1000))
1871 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1872 port_name(dport
->port
), I915_READ(dpll_reg
) & port_mask
, expected_mask
);
1875 static void intel_prepare_shared_dpll(struct intel_crtc
*crtc
)
1877 struct drm_device
*dev
= crtc
->base
.dev
;
1878 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1879 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1881 if (WARN_ON(pll
== NULL
))
1884 WARN_ON(!pll
->config
.crtc_mask
);
1885 if (pll
->active
== 0) {
1886 DRM_DEBUG_DRIVER("setting up %s\n", pll
->name
);
1888 assert_shared_dpll_disabled(dev_priv
, pll
);
1890 pll
->mode_set(dev_priv
, pll
);
1895 * intel_enable_shared_dpll - enable PCH PLL
1896 * @dev_priv: i915 private structure
1897 * @pipe: pipe PLL to enable
1899 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1900 * drives the transcoder clock.
1902 static void intel_enable_shared_dpll(struct intel_crtc
*crtc
)
1904 struct drm_device
*dev
= crtc
->base
.dev
;
1905 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1906 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1908 if (WARN_ON(pll
== NULL
))
1911 if (WARN_ON(pll
->config
.crtc_mask
== 0))
1914 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1915 pll
->name
, pll
->active
, pll
->on
,
1916 crtc
->base
.base
.id
);
1918 if (pll
->active
++) {
1920 assert_shared_dpll_enabled(dev_priv
, pll
);
1925 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
1927 DRM_DEBUG_KMS("enabling %s\n", pll
->name
);
1928 pll
->enable(dev_priv
, pll
);
1932 static void intel_disable_shared_dpll(struct intel_crtc
*crtc
)
1934 struct drm_device
*dev
= crtc
->base
.dev
;
1935 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1936 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1938 /* PCH only available on ILK+ */
1939 BUG_ON(INTEL_INFO(dev
)->gen
< 5);
1940 if (WARN_ON(pll
== NULL
))
1943 if (WARN_ON(pll
->config
.crtc_mask
== 0))
1946 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1947 pll
->name
, pll
->active
, pll
->on
,
1948 crtc
->base
.base
.id
);
1950 if (WARN_ON(pll
->active
== 0)) {
1951 assert_shared_dpll_disabled(dev_priv
, pll
);
1955 assert_shared_dpll_enabled(dev_priv
, pll
);
1960 DRM_DEBUG_KMS("disabling %s\n", pll
->name
);
1961 pll
->disable(dev_priv
, pll
);
1964 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
1967 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1970 struct drm_device
*dev
= dev_priv
->dev
;
1971 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1972 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1973 uint32_t reg
, val
, pipeconf_val
;
1975 /* PCH only available on ILK+ */
1976 BUG_ON(!HAS_PCH_SPLIT(dev
));
1978 /* Make sure PCH DPLL is enabled */
1979 assert_shared_dpll_enabled(dev_priv
,
1980 intel_crtc_to_shared_dpll(intel_crtc
));
1982 /* FDI must be feeding us bits for PCH ports */
1983 assert_fdi_tx_enabled(dev_priv
, pipe
);
1984 assert_fdi_rx_enabled(dev_priv
, pipe
);
1986 if (HAS_PCH_CPT(dev
)) {
1987 /* Workaround: Set the timing override bit before enabling the
1988 * pch transcoder. */
1989 reg
= TRANS_CHICKEN2(pipe
);
1990 val
= I915_READ(reg
);
1991 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1992 I915_WRITE(reg
, val
);
1995 reg
= PCH_TRANSCONF(pipe
);
1996 val
= I915_READ(reg
);
1997 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1999 if (HAS_PCH_IBX(dev_priv
->dev
)) {
2001 * make the BPC in transcoder be consistent with
2002 * that in pipeconf reg.
2004 val
&= ~PIPECONF_BPC_MASK
;
2005 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
2008 val
&= ~TRANS_INTERLACE_MASK
;
2009 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
2010 if (HAS_PCH_IBX(dev_priv
->dev
) &&
2011 intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
2012 val
|= TRANS_LEGACY_INTERLACED_ILK
;
2014 val
|= TRANS_INTERLACED
;
2016 val
|= TRANS_PROGRESSIVE
;
2018 I915_WRITE(reg
, val
| TRANS_ENABLE
);
2019 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
2020 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
2023 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
2024 enum transcoder cpu_transcoder
)
2026 u32 val
, pipeconf_val
;
2028 /* PCH only available on ILK+ */
2029 BUG_ON(!HAS_PCH_SPLIT(dev_priv
->dev
));
2031 /* FDI must be feeding us bits for PCH ports */
2032 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
2033 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
2035 /* Workaround: set timing override bit. */
2036 val
= I915_READ(_TRANSA_CHICKEN2
);
2037 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
2038 I915_WRITE(_TRANSA_CHICKEN2
, val
);
2041 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
2043 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
2044 PIPECONF_INTERLACED_ILK
)
2045 val
|= TRANS_INTERLACED
;
2047 val
|= TRANS_PROGRESSIVE
;
2049 I915_WRITE(LPT_TRANSCONF
, val
);
2050 if (wait_for(I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
, 100))
2051 DRM_ERROR("Failed to enable PCH transcoder\n");
2054 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
2057 struct drm_device
*dev
= dev_priv
->dev
;
2060 /* FDI relies on the transcoder */
2061 assert_fdi_tx_disabled(dev_priv
, pipe
);
2062 assert_fdi_rx_disabled(dev_priv
, pipe
);
2064 /* Ports must be off as well */
2065 assert_pch_ports_disabled(dev_priv
, pipe
);
2067 reg
= PCH_TRANSCONF(pipe
);
2068 val
= I915_READ(reg
);
2069 val
&= ~TRANS_ENABLE
;
2070 I915_WRITE(reg
, val
);
2071 /* wait for PCH transcoder off, transcoder state */
2072 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
2073 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
2075 if (!HAS_PCH_IBX(dev
)) {
2076 /* Workaround: Clear the timing override chicken bit again. */
2077 reg
= TRANS_CHICKEN2(pipe
);
2078 val
= I915_READ(reg
);
2079 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
2080 I915_WRITE(reg
, val
);
2084 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
2088 val
= I915_READ(LPT_TRANSCONF
);
2089 val
&= ~TRANS_ENABLE
;
2090 I915_WRITE(LPT_TRANSCONF
, val
);
2091 /* wait for PCH transcoder off, transcoder state */
2092 if (wait_for((I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
) == 0, 50))
2093 DRM_ERROR("Failed to disable PCH transcoder\n");
2095 /* Workaround: clear timing override bit. */
2096 val
= I915_READ(_TRANSA_CHICKEN2
);
2097 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
2098 I915_WRITE(_TRANSA_CHICKEN2
, val
);
2102 * intel_enable_pipe - enable a pipe, asserting requirements
2103 * @crtc: crtc responsible for the pipe
2105 * Enable @crtc's pipe, making sure that various hardware specific requirements
2106 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2108 static void intel_enable_pipe(struct intel_crtc
*crtc
)
2110 struct drm_device
*dev
= crtc
->base
.dev
;
2111 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2112 enum pipe pipe
= crtc
->pipe
;
2113 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
2115 enum pipe pch_transcoder
;
2119 assert_planes_disabled(dev_priv
, pipe
);
2120 assert_cursor_disabled(dev_priv
, pipe
);
2121 assert_sprites_disabled(dev_priv
, pipe
);
2123 if (HAS_PCH_LPT(dev_priv
->dev
))
2124 pch_transcoder
= TRANSCODER_A
;
2126 pch_transcoder
= pipe
;
2129 * A pipe without a PLL won't actually be able to drive bits from
2130 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2133 if (HAS_GMCH_DISPLAY(dev_priv
->dev
))
2134 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
))
2135 assert_dsi_pll_enabled(dev_priv
);
2137 assert_pll_enabled(dev_priv
, pipe
);
2139 if (crtc
->config
->has_pch_encoder
) {
2140 /* if driving the PCH, we need FDI enabled */
2141 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
2142 assert_fdi_tx_pll_enabled(dev_priv
,
2143 (enum pipe
) cpu_transcoder
);
2145 /* FIXME: assert CPU port conditions for SNB+ */
2148 reg
= PIPECONF(cpu_transcoder
);
2149 val
= I915_READ(reg
);
2150 if (val
& PIPECONF_ENABLE
) {
2151 WARN_ON(!((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
2152 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
)));
2156 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
2161 * intel_disable_pipe - disable a pipe, asserting requirements
2162 * @crtc: crtc whose pipes is to be disabled
2164 * Disable the pipe of @crtc, making sure that various hardware
2165 * specific requirements are met, if applicable, e.g. plane
2166 * disabled, panel fitter off, etc.
2168 * Will wait until the pipe has shut down before returning.
2170 static void intel_disable_pipe(struct intel_crtc
*crtc
)
2172 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
2173 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
2174 enum pipe pipe
= crtc
->pipe
;
2179 * Make sure planes won't keep trying to pump pixels to us,
2180 * or we might hang the display.
2182 assert_planes_disabled(dev_priv
, pipe
);
2183 assert_cursor_disabled(dev_priv
, pipe
);
2184 assert_sprites_disabled(dev_priv
, pipe
);
2186 reg
= PIPECONF(cpu_transcoder
);
2187 val
= I915_READ(reg
);
2188 if ((val
& PIPECONF_ENABLE
) == 0)
2192 * Double wide has implications for planes
2193 * so best keep it disabled when not needed.
2195 if (crtc
->config
->double_wide
)
2196 val
&= ~PIPECONF_DOUBLE_WIDE
;
2198 /* Don't disable pipe or pipe PLLs if needed */
2199 if (!(pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) &&
2200 !(pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
2201 val
&= ~PIPECONF_ENABLE
;
2203 I915_WRITE(reg
, val
);
2204 if ((val
& PIPECONF_ENABLE
) == 0)
2205 intel_wait_for_pipe_off(crtc
);
2209 * Plane regs are double buffered, going from enabled->disabled needs a
2210 * trigger in order to latch. The display address reg provides this.
2212 void intel_flush_primary_plane(struct drm_i915_private
*dev_priv
,
2215 struct drm_device
*dev
= dev_priv
->dev
;
2216 u32 reg
= INTEL_INFO(dev
)->gen
>= 4 ? DSPSURF(plane
) : DSPADDR(plane
);
2218 I915_WRITE(reg
, I915_READ(reg
));
2223 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2224 * @plane: plane to be enabled
2225 * @crtc: crtc for the plane
2227 * Enable @plane on @crtc, making sure that the pipe is running first.
2229 static void intel_enable_primary_hw_plane(struct drm_plane
*plane
,
2230 struct drm_crtc
*crtc
)
2232 struct drm_device
*dev
= plane
->dev
;
2233 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2234 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2236 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2237 assert_pipe_enabled(dev_priv
, intel_crtc
->pipe
);
2238 to_intel_plane_state(plane
->state
)->visible
= true;
2240 dev_priv
->display
.update_primary_plane(crtc
, plane
->fb
,
2244 static bool need_vtd_wa(struct drm_device
*dev
)
2246 #ifdef CONFIG_INTEL_IOMMU
2247 if (INTEL_INFO(dev
)->gen
>= 6 && intel_iommu_gfx_mapped
)
2254 intel_tile_height(struct drm_device
*dev
, uint32_t pixel_format
,
2255 uint64_t fb_format_modifier
)
2257 unsigned int tile_height
;
2258 uint32_t pixel_bytes
;
2260 switch (fb_format_modifier
) {
2261 case DRM_FORMAT_MOD_NONE
:
2264 case I915_FORMAT_MOD_X_TILED
:
2265 tile_height
= IS_GEN2(dev
) ? 16 : 8;
2267 case I915_FORMAT_MOD_Y_TILED
:
2270 case I915_FORMAT_MOD_Yf_TILED
:
2271 pixel_bytes
= drm_format_plane_cpp(pixel_format
, 0);
2272 switch (pixel_bytes
) {
2286 "128-bit pixels are not supported for display!");
2292 MISSING_CASE(fb_format_modifier
);
2301 intel_fb_align_height(struct drm_device
*dev
, unsigned int height
,
2302 uint32_t pixel_format
, uint64_t fb_format_modifier
)
2304 return ALIGN(height
, intel_tile_height(dev
, pixel_format
,
2305 fb_format_modifier
));
2309 intel_fill_fb_ggtt_view(struct i915_ggtt_view
*view
, struct drm_framebuffer
*fb
,
2310 const struct drm_plane_state
*plane_state
)
2312 struct intel_rotation_info
*info
= &view
->rotation_info
;
2314 *view
= i915_ggtt_view_normal
;
2319 if (!intel_rotation_90_or_270(plane_state
->rotation
))
2322 *view
= i915_ggtt_view_rotated
;
2324 info
->height
= fb
->height
;
2325 info
->pixel_format
= fb
->pixel_format
;
2326 info
->pitch
= fb
->pitches
[0];
2327 info
->fb_modifier
= fb
->modifier
[0];
2333 intel_pin_and_fence_fb_obj(struct drm_plane
*plane
,
2334 struct drm_framebuffer
*fb
,
2335 const struct drm_plane_state
*plane_state
,
2336 struct intel_engine_cs
*pipelined
)
2338 struct drm_device
*dev
= fb
->dev
;
2339 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2340 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2341 struct i915_ggtt_view view
;
2345 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
2347 switch (fb
->modifier
[0]) {
2348 case DRM_FORMAT_MOD_NONE
:
2349 if (INTEL_INFO(dev
)->gen
>= 9)
2350 alignment
= 256 * 1024;
2351 else if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
2352 alignment
= 128 * 1024;
2353 else if (INTEL_INFO(dev
)->gen
>= 4)
2354 alignment
= 4 * 1024;
2356 alignment
= 64 * 1024;
2358 case I915_FORMAT_MOD_X_TILED
:
2359 if (INTEL_INFO(dev
)->gen
>= 9)
2360 alignment
= 256 * 1024;
2362 /* pin() will align the object as required by fence */
2366 case I915_FORMAT_MOD_Y_TILED
:
2367 case I915_FORMAT_MOD_Yf_TILED
:
2368 if (WARN_ONCE(INTEL_INFO(dev
)->gen
< 9,
2369 "Y tiling bo slipped through, driver bug!\n"))
2371 alignment
= 1 * 1024 * 1024;
2374 MISSING_CASE(fb
->modifier
[0]);
2378 ret
= intel_fill_fb_ggtt_view(&view
, fb
, plane_state
);
2382 /* Note that the w/a also requires 64 PTE of padding following the
2383 * bo. We currently fill all unused PTE with the shadow page and so
2384 * we should always have valid PTE following the scanout preventing
2387 if (need_vtd_wa(dev
) && alignment
< 256 * 1024)
2388 alignment
= 256 * 1024;
2391 * Global gtt pte registers are special registers which actually forward
2392 * writes to a chunk of system memory. Which means that there is no risk
2393 * that the register values disappear as soon as we call
2394 * intel_runtime_pm_put(), so it is correct to wrap only the
2395 * pin/unpin/fence and not more.
2397 intel_runtime_pm_get(dev_priv
);
2399 dev_priv
->mm
.interruptible
= false;
2400 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
,
2403 goto err_interruptible
;
2405 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2406 * fence, whereas 965+ only requires a fence if using
2407 * framebuffer compression. For simplicity, we always install
2408 * a fence as the cost is not that onerous.
2410 ret
= i915_gem_object_get_fence(obj
);
2414 i915_gem_object_pin_fence(obj
);
2416 dev_priv
->mm
.interruptible
= true;
2417 intel_runtime_pm_put(dev_priv
);
2421 i915_gem_object_unpin_from_display_plane(obj
, &view
);
2423 dev_priv
->mm
.interruptible
= true;
2424 intel_runtime_pm_put(dev_priv
);
2428 static void intel_unpin_fb_obj(struct drm_framebuffer
*fb
,
2429 const struct drm_plane_state
*plane_state
)
2431 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2432 struct i915_ggtt_view view
;
2435 WARN_ON(!mutex_is_locked(&obj
->base
.dev
->struct_mutex
));
2437 ret
= intel_fill_fb_ggtt_view(&view
, fb
, plane_state
);
2438 WARN_ONCE(ret
, "Couldn't get view from plane state!");
2440 i915_gem_object_unpin_fence(obj
);
2441 i915_gem_object_unpin_from_display_plane(obj
, &view
);
2444 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2445 * is assumed to be a power-of-two. */
2446 unsigned long intel_gen4_compute_page_offset(int *x
, int *y
,
2447 unsigned int tiling_mode
,
2451 if (tiling_mode
!= I915_TILING_NONE
) {
2452 unsigned int tile_rows
, tiles
;
2457 tiles
= *x
/ (512/cpp
);
2460 return tile_rows
* pitch
* 8 + tiles
* 4096;
2462 unsigned int offset
;
2464 offset
= *y
* pitch
+ *x
* cpp
;
2466 *x
= (offset
& 4095) / cpp
;
2467 return offset
& -4096;
2471 static int i9xx_format_to_fourcc(int format
)
2474 case DISPPLANE_8BPP
:
2475 return DRM_FORMAT_C8
;
2476 case DISPPLANE_BGRX555
:
2477 return DRM_FORMAT_XRGB1555
;
2478 case DISPPLANE_BGRX565
:
2479 return DRM_FORMAT_RGB565
;
2481 case DISPPLANE_BGRX888
:
2482 return DRM_FORMAT_XRGB8888
;
2483 case DISPPLANE_RGBX888
:
2484 return DRM_FORMAT_XBGR8888
;
2485 case DISPPLANE_BGRX101010
:
2486 return DRM_FORMAT_XRGB2101010
;
2487 case DISPPLANE_RGBX101010
:
2488 return DRM_FORMAT_XBGR2101010
;
2492 static int skl_format_to_fourcc(int format
, bool rgb_order
, bool alpha
)
2495 case PLANE_CTL_FORMAT_RGB_565
:
2496 return DRM_FORMAT_RGB565
;
2498 case PLANE_CTL_FORMAT_XRGB_8888
:
2501 return DRM_FORMAT_ABGR8888
;
2503 return DRM_FORMAT_XBGR8888
;
2506 return DRM_FORMAT_ARGB8888
;
2508 return DRM_FORMAT_XRGB8888
;
2510 case PLANE_CTL_FORMAT_XRGB_2101010
:
2512 return DRM_FORMAT_XBGR2101010
;
2514 return DRM_FORMAT_XRGB2101010
;
2519 intel_alloc_initial_plane_obj(struct intel_crtc
*crtc
,
2520 struct intel_initial_plane_config
*plane_config
)
2522 struct drm_device
*dev
= crtc
->base
.dev
;
2523 struct drm_i915_gem_object
*obj
= NULL
;
2524 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
2525 struct drm_framebuffer
*fb
= &plane_config
->fb
->base
;
2526 u32 base_aligned
= round_down(plane_config
->base
, PAGE_SIZE
);
2527 u32 size_aligned
= round_up(plane_config
->base
+ plane_config
->size
,
2530 size_aligned
-= base_aligned
;
2532 if (plane_config
->size
== 0)
2535 obj
= i915_gem_object_create_stolen_for_preallocated(dev
,
2542 obj
->tiling_mode
= plane_config
->tiling
;
2543 if (obj
->tiling_mode
== I915_TILING_X
)
2544 obj
->stride
= fb
->pitches
[0];
2546 mode_cmd
.pixel_format
= fb
->pixel_format
;
2547 mode_cmd
.width
= fb
->width
;
2548 mode_cmd
.height
= fb
->height
;
2549 mode_cmd
.pitches
[0] = fb
->pitches
[0];
2550 mode_cmd
.modifier
[0] = fb
->modifier
[0];
2551 mode_cmd
.flags
= DRM_MODE_FB_MODIFIERS
;
2553 mutex_lock(&dev
->struct_mutex
);
2554 if (intel_framebuffer_init(dev
, to_intel_framebuffer(fb
),
2556 DRM_DEBUG_KMS("intel fb init failed\n");
2559 mutex_unlock(&dev
->struct_mutex
);
2561 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj
);
2565 drm_gem_object_unreference(&obj
->base
);
2566 mutex_unlock(&dev
->struct_mutex
);
2570 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2572 update_state_fb(struct drm_plane
*plane
)
2574 if (plane
->fb
== plane
->state
->fb
)
2577 if (plane
->state
->fb
)
2578 drm_framebuffer_unreference(plane
->state
->fb
);
2579 plane
->state
->fb
= plane
->fb
;
2580 if (plane
->state
->fb
)
2581 drm_framebuffer_reference(plane
->state
->fb
);
2585 intel_find_initial_plane_obj(struct intel_crtc
*intel_crtc
,
2586 struct intel_initial_plane_config
*plane_config
)
2588 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2589 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2591 struct intel_crtc
*i
;
2592 struct drm_i915_gem_object
*obj
;
2593 struct drm_plane
*primary
= intel_crtc
->base
.primary
;
2594 struct drm_framebuffer
*fb
;
2596 if (!plane_config
->fb
)
2599 if (intel_alloc_initial_plane_obj(intel_crtc
, plane_config
)) {
2600 fb
= &plane_config
->fb
->base
;
2604 kfree(plane_config
->fb
);
2607 * Failed to alloc the obj, check to see if we should share
2608 * an fb with another CRTC instead
2610 for_each_crtc(dev
, c
) {
2611 i
= to_intel_crtc(c
);
2613 if (c
== &intel_crtc
->base
)
2619 fb
= c
->primary
->fb
;
2623 obj
= intel_fb_obj(fb
);
2624 if (i915_gem_obj_ggtt_offset(obj
) == plane_config
->base
) {
2625 drm_framebuffer_reference(fb
);
2633 obj
= intel_fb_obj(fb
);
2634 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2635 dev_priv
->preserve_bios_swizzle
= true;
2638 primary
->state
->crtc
= &intel_crtc
->base
;
2639 primary
->crtc
= &intel_crtc
->base
;
2640 update_state_fb(primary
);
2641 obj
->frontbuffer_bits
|= INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
);
2644 static void i9xx_update_primary_plane(struct drm_crtc
*crtc
,
2645 struct drm_framebuffer
*fb
,
2648 struct drm_device
*dev
= crtc
->dev
;
2649 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2650 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2651 struct drm_plane
*primary
= crtc
->primary
;
2652 bool visible
= to_intel_plane_state(primary
->state
)->visible
;
2653 struct drm_i915_gem_object
*obj
;
2654 int plane
= intel_crtc
->plane
;
2655 unsigned long linear_offset
;
2657 u32 reg
= DSPCNTR(plane
);
2660 if (!visible
|| !fb
) {
2662 if (INTEL_INFO(dev
)->gen
>= 4)
2663 I915_WRITE(DSPSURF(plane
), 0);
2665 I915_WRITE(DSPADDR(plane
), 0);
2670 obj
= intel_fb_obj(fb
);
2671 if (WARN_ON(obj
== NULL
))
2674 pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2676 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2678 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2680 if (INTEL_INFO(dev
)->gen
< 4) {
2681 if (intel_crtc
->pipe
== PIPE_B
)
2682 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
2684 /* pipesrc and dspsize control the size that is scaled from,
2685 * which should always be the user's requested size.
2687 I915_WRITE(DSPSIZE(plane
),
2688 ((intel_crtc
->config
->pipe_src_h
- 1) << 16) |
2689 (intel_crtc
->config
->pipe_src_w
- 1));
2690 I915_WRITE(DSPPOS(plane
), 0);
2691 } else if (IS_CHERRYVIEW(dev
) && plane
== PLANE_B
) {
2692 I915_WRITE(PRIMSIZE(plane
),
2693 ((intel_crtc
->config
->pipe_src_h
- 1) << 16) |
2694 (intel_crtc
->config
->pipe_src_w
- 1));
2695 I915_WRITE(PRIMPOS(plane
), 0);
2696 I915_WRITE(PRIMCNSTALPHA(plane
), 0);
2699 switch (fb
->pixel_format
) {
2701 dspcntr
|= DISPPLANE_8BPP
;
2703 case DRM_FORMAT_XRGB1555
:
2704 case DRM_FORMAT_ARGB1555
:
2705 dspcntr
|= DISPPLANE_BGRX555
;
2707 case DRM_FORMAT_RGB565
:
2708 dspcntr
|= DISPPLANE_BGRX565
;
2710 case DRM_FORMAT_XRGB8888
:
2711 case DRM_FORMAT_ARGB8888
:
2712 dspcntr
|= DISPPLANE_BGRX888
;
2714 case DRM_FORMAT_XBGR8888
:
2715 case DRM_FORMAT_ABGR8888
:
2716 dspcntr
|= DISPPLANE_RGBX888
;
2718 case DRM_FORMAT_XRGB2101010
:
2719 case DRM_FORMAT_ARGB2101010
:
2720 dspcntr
|= DISPPLANE_BGRX101010
;
2722 case DRM_FORMAT_XBGR2101010
:
2723 case DRM_FORMAT_ABGR2101010
:
2724 dspcntr
|= DISPPLANE_RGBX101010
;
2730 if (INTEL_INFO(dev
)->gen
>= 4 &&
2731 obj
->tiling_mode
!= I915_TILING_NONE
)
2732 dspcntr
|= DISPPLANE_TILED
;
2735 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2737 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
2739 if (INTEL_INFO(dev
)->gen
>= 4) {
2740 intel_crtc
->dspaddr_offset
=
2741 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2744 linear_offset
-= intel_crtc
->dspaddr_offset
;
2746 intel_crtc
->dspaddr_offset
= linear_offset
;
2749 if (crtc
->primary
->state
->rotation
== BIT(DRM_ROTATE_180
)) {
2750 dspcntr
|= DISPPLANE_ROTATE_180
;
2752 x
+= (intel_crtc
->config
->pipe_src_w
- 1);
2753 y
+= (intel_crtc
->config
->pipe_src_h
- 1);
2755 /* Finding the last pixel of the last line of the display
2756 data and adding to linear_offset*/
2758 (intel_crtc
->config
->pipe_src_h
- 1) * fb
->pitches
[0] +
2759 (intel_crtc
->config
->pipe_src_w
- 1) * pixel_size
;
2762 I915_WRITE(reg
, dspcntr
);
2764 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2765 if (INTEL_INFO(dev
)->gen
>= 4) {
2766 I915_WRITE(DSPSURF(plane
),
2767 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2768 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2769 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2771 I915_WRITE(DSPADDR(plane
), i915_gem_obj_ggtt_offset(obj
) + linear_offset
);
2775 static void ironlake_update_primary_plane(struct drm_crtc
*crtc
,
2776 struct drm_framebuffer
*fb
,
2779 struct drm_device
*dev
= crtc
->dev
;
2780 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2781 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2782 struct drm_plane
*primary
= crtc
->primary
;
2783 bool visible
= to_intel_plane_state(primary
->state
)->visible
;
2784 struct drm_i915_gem_object
*obj
;
2785 int plane
= intel_crtc
->plane
;
2786 unsigned long linear_offset
;
2788 u32 reg
= DSPCNTR(plane
);
2791 if (!visible
|| !fb
) {
2793 I915_WRITE(DSPSURF(plane
), 0);
2798 obj
= intel_fb_obj(fb
);
2799 if (WARN_ON(obj
== NULL
))
2802 pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2804 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2806 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2808 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2809 dspcntr
|= DISPPLANE_PIPE_CSC_ENABLE
;
2811 switch (fb
->pixel_format
) {
2813 dspcntr
|= DISPPLANE_8BPP
;
2815 case DRM_FORMAT_RGB565
:
2816 dspcntr
|= DISPPLANE_BGRX565
;
2818 case DRM_FORMAT_XRGB8888
:
2819 case DRM_FORMAT_ARGB8888
:
2820 dspcntr
|= DISPPLANE_BGRX888
;
2822 case DRM_FORMAT_XBGR8888
:
2823 case DRM_FORMAT_ABGR8888
:
2824 dspcntr
|= DISPPLANE_RGBX888
;
2826 case DRM_FORMAT_XRGB2101010
:
2827 case DRM_FORMAT_ARGB2101010
:
2828 dspcntr
|= DISPPLANE_BGRX101010
;
2830 case DRM_FORMAT_XBGR2101010
:
2831 case DRM_FORMAT_ABGR2101010
:
2832 dspcntr
|= DISPPLANE_RGBX101010
;
2838 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2839 dspcntr
|= DISPPLANE_TILED
;
2841 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
))
2842 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2844 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
2845 intel_crtc
->dspaddr_offset
=
2846 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2849 linear_offset
-= intel_crtc
->dspaddr_offset
;
2850 if (crtc
->primary
->state
->rotation
== BIT(DRM_ROTATE_180
)) {
2851 dspcntr
|= DISPPLANE_ROTATE_180
;
2853 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
)) {
2854 x
+= (intel_crtc
->config
->pipe_src_w
- 1);
2855 y
+= (intel_crtc
->config
->pipe_src_h
- 1);
2857 /* Finding the last pixel of the last line of the display
2858 data and adding to linear_offset*/
2860 (intel_crtc
->config
->pipe_src_h
- 1) * fb
->pitches
[0] +
2861 (intel_crtc
->config
->pipe_src_w
- 1) * pixel_size
;
2865 I915_WRITE(reg
, dspcntr
);
2867 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2868 I915_WRITE(DSPSURF(plane
),
2869 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2870 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2871 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2873 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2874 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2879 u32
intel_fb_stride_alignment(struct drm_device
*dev
, uint64_t fb_modifier
,
2880 uint32_t pixel_format
)
2882 u32 bits_per_pixel
= drm_format_plane_cpp(pixel_format
, 0) * 8;
2885 * The stride is either expressed as a multiple of 64 bytes
2886 * chunks for linear buffers or in number of tiles for tiled
2889 switch (fb_modifier
) {
2890 case DRM_FORMAT_MOD_NONE
:
2892 case I915_FORMAT_MOD_X_TILED
:
2893 if (INTEL_INFO(dev
)->gen
== 2)
2896 case I915_FORMAT_MOD_Y_TILED
:
2897 /* No need to check for old gens and Y tiling since this is
2898 * about the display engine and those will be blocked before
2902 case I915_FORMAT_MOD_Yf_TILED
:
2903 if (bits_per_pixel
== 8)
2908 MISSING_CASE(fb_modifier
);
2913 unsigned long intel_plane_obj_offset(struct intel_plane
*intel_plane
,
2914 struct drm_i915_gem_object
*obj
)
2916 const struct i915_ggtt_view
*view
= &i915_ggtt_view_normal
;
2918 if (intel_rotation_90_or_270(intel_plane
->base
.state
->rotation
))
2919 view
= &i915_ggtt_view_rotated
;
2921 return i915_gem_obj_ggtt_offset_view(obj
, view
);
2925 * This function detaches (aka. unbinds) unused scalers in hardware
2927 void skl_detach_scalers(struct intel_crtc
*intel_crtc
)
2929 struct drm_device
*dev
;
2930 struct drm_i915_private
*dev_priv
;
2931 struct intel_crtc_scaler_state
*scaler_state
;
2934 if (!intel_crtc
|| !intel_crtc
->config
)
2937 dev
= intel_crtc
->base
.dev
;
2938 dev_priv
= dev
->dev_private
;
2939 scaler_state
= &intel_crtc
->config
->scaler_state
;
2941 /* loop through and disable scalers that aren't in use */
2942 for (i
= 0; i
< intel_crtc
->num_scalers
; i
++) {
2943 if (!scaler_state
->scalers
[i
].in_use
) {
2944 I915_WRITE(SKL_PS_CTRL(intel_crtc
->pipe
, i
), 0);
2945 I915_WRITE(SKL_PS_WIN_POS(intel_crtc
->pipe
, i
), 0);
2946 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc
->pipe
, i
), 0);
2947 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2948 intel_crtc
->base
.base
.id
, intel_crtc
->pipe
, i
);
2953 u32
skl_plane_ctl_format(uint32_t pixel_format
)
2955 switch (pixel_format
) {
2957 return PLANE_CTL_FORMAT_INDEXED
;
2958 case DRM_FORMAT_RGB565
:
2959 return PLANE_CTL_FORMAT_RGB_565
;
2960 case DRM_FORMAT_XBGR8888
:
2961 return PLANE_CTL_FORMAT_XRGB_8888
| PLANE_CTL_ORDER_RGBX
;
2962 case DRM_FORMAT_XRGB8888
:
2963 return PLANE_CTL_FORMAT_XRGB_8888
;
2965 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2966 * to be already pre-multiplied. We need to add a knob (or a different
2967 * DRM_FORMAT) for user-space to configure that.
2969 case DRM_FORMAT_ABGR8888
:
2970 return PLANE_CTL_FORMAT_XRGB_8888
| PLANE_CTL_ORDER_RGBX
|
2971 PLANE_CTL_ALPHA_SW_PREMULTIPLY
;
2972 case DRM_FORMAT_ARGB8888
:
2973 return PLANE_CTL_FORMAT_XRGB_8888
|
2974 PLANE_CTL_ALPHA_SW_PREMULTIPLY
;
2975 case DRM_FORMAT_XRGB2101010
:
2976 return PLANE_CTL_FORMAT_XRGB_2101010
;
2977 case DRM_FORMAT_XBGR2101010
:
2978 return PLANE_CTL_ORDER_RGBX
| PLANE_CTL_FORMAT_XRGB_2101010
;
2979 case DRM_FORMAT_YUYV
:
2980 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_YUYV
;
2981 case DRM_FORMAT_YVYU
:
2982 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_YVYU
;
2983 case DRM_FORMAT_UYVY
:
2984 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_UYVY
;
2985 case DRM_FORMAT_VYUY
:
2986 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_VYUY
;
2988 MISSING_CASE(pixel_format
);
2994 u32
skl_plane_ctl_tiling(uint64_t fb_modifier
)
2996 switch (fb_modifier
) {
2997 case DRM_FORMAT_MOD_NONE
:
2999 case I915_FORMAT_MOD_X_TILED
:
3000 return PLANE_CTL_TILED_X
;
3001 case I915_FORMAT_MOD_Y_TILED
:
3002 return PLANE_CTL_TILED_Y
;
3003 case I915_FORMAT_MOD_Yf_TILED
:
3004 return PLANE_CTL_TILED_YF
;
3006 MISSING_CASE(fb_modifier
);
3012 u32
skl_plane_ctl_rotation(unsigned int rotation
)
3015 case BIT(DRM_ROTATE_0
):
3017 case BIT(DRM_ROTATE_90
):
3018 return PLANE_CTL_ROTATE_90
;
3019 case BIT(DRM_ROTATE_180
):
3020 return PLANE_CTL_ROTATE_180
;
3021 case BIT(DRM_ROTATE_270
):
3022 return PLANE_CTL_ROTATE_270
;
3024 MISSING_CASE(rotation
);
3030 static void skylake_update_primary_plane(struct drm_crtc
*crtc
,
3031 struct drm_framebuffer
*fb
,
3034 struct drm_device
*dev
= crtc
->dev
;
3035 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3036 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3037 struct drm_plane
*plane
= crtc
->primary
;
3038 bool visible
= to_intel_plane_state(plane
->state
)->visible
;
3039 struct drm_i915_gem_object
*obj
;
3040 int pipe
= intel_crtc
->pipe
;
3041 u32 plane_ctl
, stride_div
, stride
;
3042 u32 tile_height
, plane_offset
, plane_size
;
3043 unsigned int rotation
;
3044 int x_offset
, y_offset
;
3045 unsigned long surf_addr
;
3046 struct intel_crtc_state
*crtc_state
= intel_crtc
->config
;
3047 struct intel_plane_state
*plane_state
;
3048 int src_x
= 0, src_y
= 0, src_w
= 0, src_h
= 0;
3049 int dst_x
= 0, dst_y
= 0, dst_w
= 0, dst_h
= 0;
3052 plane_state
= to_intel_plane_state(plane
->state
);
3054 if (!visible
|| !fb
) {
3055 I915_WRITE(PLANE_CTL(pipe
, 0), 0);
3056 I915_WRITE(PLANE_SURF(pipe
, 0), 0);
3057 POSTING_READ(PLANE_CTL(pipe
, 0));
3061 plane_ctl
= PLANE_CTL_ENABLE
|
3062 PLANE_CTL_PIPE_GAMMA_ENABLE
|
3063 PLANE_CTL_PIPE_CSC_ENABLE
;
3065 plane_ctl
|= skl_plane_ctl_format(fb
->pixel_format
);
3066 plane_ctl
|= skl_plane_ctl_tiling(fb
->modifier
[0]);
3067 plane_ctl
|= PLANE_CTL_PLANE_GAMMA_DISABLE
;
3069 rotation
= plane
->state
->rotation
;
3070 plane_ctl
|= skl_plane_ctl_rotation(rotation
);
3072 obj
= intel_fb_obj(fb
);
3073 stride_div
= intel_fb_stride_alignment(dev
, fb
->modifier
[0],
3075 surf_addr
= intel_plane_obj_offset(to_intel_plane(plane
), obj
);
3078 * FIXME: intel_plane_state->src, dst aren't set when transitional
3079 * update_plane helpers are called from legacy paths.
3080 * Once full atomic crtc is available, below check can be avoided.
3082 if (drm_rect_width(&plane_state
->src
)) {
3083 scaler_id
= plane_state
->scaler_id
;
3084 src_x
= plane_state
->src
.x1
>> 16;
3085 src_y
= plane_state
->src
.y1
>> 16;
3086 src_w
= drm_rect_width(&plane_state
->src
) >> 16;
3087 src_h
= drm_rect_height(&plane_state
->src
) >> 16;
3088 dst_x
= plane_state
->dst
.x1
;
3089 dst_y
= plane_state
->dst
.y1
;
3090 dst_w
= drm_rect_width(&plane_state
->dst
);
3091 dst_h
= drm_rect_height(&plane_state
->dst
);
3093 WARN_ON(x
!= src_x
|| y
!= src_y
);
3095 src_w
= intel_crtc
->config
->pipe_src_w
;
3096 src_h
= intel_crtc
->config
->pipe_src_h
;
3099 if (intel_rotation_90_or_270(rotation
)) {
3100 /* stride = Surface height in tiles */
3101 tile_height
= intel_tile_height(dev
, fb
->pixel_format
,
3103 stride
= DIV_ROUND_UP(fb
->height
, tile_height
);
3104 x_offset
= stride
* tile_height
- y
- src_h
;
3106 plane_size
= (src_w
- 1) << 16 | (src_h
- 1);
3108 stride
= fb
->pitches
[0] / stride_div
;
3111 plane_size
= (src_h
- 1) << 16 | (src_w
- 1);
3113 plane_offset
= y_offset
<< 16 | x_offset
;
3115 I915_WRITE(PLANE_CTL(pipe
, 0), plane_ctl
);
3116 I915_WRITE(PLANE_OFFSET(pipe
, 0), plane_offset
);
3117 I915_WRITE(PLANE_SIZE(pipe
, 0), plane_size
);
3118 I915_WRITE(PLANE_STRIDE(pipe
, 0), stride
);
3120 if (scaler_id
>= 0) {
3121 uint32_t ps_ctrl
= 0;
3123 WARN_ON(!dst_w
|| !dst_h
);
3124 ps_ctrl
= PS_SCALER_EN
| PS_PLANE_SEL(0) |
3125 crtc_state
->scaler_state
.scalers
[scaler_id
].mode
;
3126 I915_WRITE(SKL_PS_CTRL(pipe
, scaler_id
), ps_ctrl
);
3127 I915_WRITE(SKL_PS_PWR_GATE(pipe
, scaler_id
), 0);
3128 I915_WRITE(SKL_PS_WIN_POS(pipe
, scaler_id
), (dst_x
<< 16) | dst_y
);
3129 I915_WRITE(SKL_PS_WIN_SZ(pipe
, scaler_id
), (dst_w
<< 16) | dst_h
);
3130 I915_WRITE(PLANE_POS(pipe
, 0), 0);
3132 I915_WRITE(PLANE_POS(pipe
, 0), (dst_y
<< 16) | dst_x
);
3135 I915_WRITE(PLANE_SURF(pipe
, 0), surf_addr
);
3137 POSTING_READ(PLANE_SURF(pipe
, 0));
3140 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3142 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
3143 int x
, int y
, enum mode_set_atomic state
)
3145 struct drm_device
*dev
= crtc
->dev
;
3146 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3148 if (dev_priv
->display
.disable_fbc
)
3149 dev_priv
->display
.disable_fbc(dev
);
3151 dev_priv
->display
.update_primary_plane(crtc
, fb
, x
, y
);
3156 static void intel_complete_page_flips(struct drm_device
*dev
)
3158 struct drm_crtc
*crtc
;
3160 for_each_crtc(dev
, crtc
) {
3161 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3162 enum plane plane
= intel_crtc
->plane
;
3164 intel_prepare_page_flip(dev
, plane
);
3165 intel_finish_page_flip_plane(dev
, plane
);
3169 static void intel_update_primary_planes(struct drm_device
*dev
)
3171 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3172 struct drm_crtc
*crtc
;
3174 for_each_crtc(dev
, crtc
) {
3175 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3177 drm_modeset_lock(&crtc
->mutex
, NULL
);
3179 * FIXME: Once we have proper support for primary planes (and
3180 * disabling them without disabling the entire crtc) allow again
3181 * a NULL crtc->primary->fb.
3183 if (intel_crtc
->active
&& crtc
->primary
->fb
)
3184 dev_priv
->display
.update_primary_plane(crtc
,
3188 drm_modeset_unlock(&crtc
->mutex
);
3192 void intel_crtc_reset(struct intel_crtc
*crtc
)
3194 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
3199 intel_crtc_disable_planes(&crtc
->base
);
3200 dev_priv
->display
.crtc_disable(&crtc
->base
);
3201 dev_priv
->display
.crtc_enable(&crtc
->base
);
3202 intel_crtc_enable_planes(&crtc
->base
);
3205 void intel_prepare_reset(struct drm_device
*dev
)
3207 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3208 struct intel_crtc
*crtc
;
3210 /* no reset support for gen2 */
3214 /* reset doesn't touch the display */
3215 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
3218 drm_modeset_lock_all(dev
);
3221 * Disabling the crtcs gracefully seems nicer. Also the
3222 * g33 docs say we should at least disable all the planes.
3224 for_each_intel_crtc(dev
, crtc
) {
3228 intel_crtc_disable_planes(&crtc
->base
);
3229 dev_priv
->display
.crtc_disable(&crtc
->base
);
3233 void intel_finish_reset(struct drm_device
*dev
)
3235 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3238 * Flips in the rings will be nuked by the reset,
3239 * so complete all pending flips so that user space
3240 * will get its events and not get stuck.
3242 intel_complete_page_flips(dev
);
3244 /* no reset support for gen2 */
3248 /* reset doesn't touch the display */
3249 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
)) {
3251 * Flips in the rings have been nuked by the reset,
3252 * so update the base address of all primary
3253 * planes to the the last fb to make sure we're
3254 * showing the correct fb after a reset.
3256 intel_update_primary_planes(dev
);
3261 * The display has been reset as well,
3262 * so need a full re-initialization.
3264 intel_runtime_pm_disable_interrupts(dev_priv
);
3265 intel_runtime_pm_enable_interrupts(dev_priv
);
3267 intel_modeset_init_hw(dev
);
3269 spin_lock_irq(&dev_priv
->irq_lock
);
3270 if (dev_priv
->display
.hpd_irq_setup
)
3271 dev_priv
->display
.hpd_irq_setup(dev
);
3272 spin_unlock_irq(&dev_priv
->irq_lock
);
3274 intel_modeset_setup_hw_state(dev
, true);
3276 intel_hpd_init(dev_priv
);
3278 drm_modeset_unlock_all(dev
);
3282 intel_finish_fb(struct drm_framebuffer
*old_fb
)
3284 struct drm_i915_gem_object
*obj
= intel_fb_obj(old_fb
);
3285 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
3286 bool was_interruptible
= dev_priv
->mm
.interruptible
;
3289 /* Big Hammer, we also need to ensure that any pending
3290 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3291 * current scanout is retired before unpinning the old
3292 * framebuffer. Note that we rely on userspace rendering
3293 * into the buffer attached to the pipe they are waiting
3294 * on. If not, userspace generates a GPU hang with IPEHR
3295 * point to the MI_WAIT_FOR_EVENT.
3297 * This should only fail upon a hung GPU, in which case we
3298 * can safely continue.
3300 dev_priv
->mm
.interruptible
= false;
3301 ret
= i915_gem_object_wait_rendering(obj
, true);
3302 dev_priv
->mm
.interruptible
= was_interruptible
;
3307 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
3309 struct drm_device
*dev
= crtc
->dev
;
3310 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3311 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3314 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
3315 intel_crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
3318 spin_lock_irq(&dev
->event_lock
);
3319 pending
= to_intel_crtc(crtc
)->unpin_work
!= NULL
;
3320 spin_unlock_irq(&dev
->event_lock
);
3325 static void intel_update_pipe_size(struct intel_crtc
*crtc
)
3327 struct drm_device
*dev
= crtc
->base
.dev
;
3328 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3329 const struct drm_display_mode
*adjusted_mode
;
3335 * Update pipe size and adjust fitter if needed: the reason for this is
3336 * that in compute_mode_changes we check the native mode (not the pfit
3337 * mode) to see if we can flip rather than do a full mode set. In the
3338 * fastboot case, we'll flip, but if we don't update the pipesrc and
3339 * pfit state, we'll end up with a big fb scanned out into the wrong
3342 * To fix this properly, we need to hoist the checks up into
3343 * compute_mode_changes (or above), check the actual pfit state and
3344 * whether the platform allows pfit disable with pipe active, and only
3345 * then update the pipesrc and pfit state, even on the flip path.
3348 adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
3350 I915_WRITE(PIPESRC(crtc
->pipe
),
3351 ((adjusted_mode
->crtc_hdisplay
- 1) << 16) |
3352 (adjusted_mode
->crtc_vdisplay
- 1));
3353 if (!crtc
->config
->pch_pfit
.enabled
&&
3354 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) ||
3355 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3356 I915_WRITE(PF_CTL(crtc
->pipe
), 0);
3357 I915_WRITE(PF_WIN_POS(crtc
->pipe
), 0);
3358 I915_WRITE(PF_WIN_SZ(crtc
->pipe
), 0);
3360 crtc
->config
->pipe_src_w
= adjusted_mode
->crtc_hdisplay
;
3361 crtc
->config
->pipe_src_h
= adjusted_mode
->crtc_vdisplay
;
3364 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
3366 struct drm_device
*dev
= crtc
->dev
;
3367 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3368 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3369 int pipe
= intel_crtc
->pipe
;
3372 /* enable normal train */
3373 reg
= FDI_TX_CTL(pipe
);
3374 temp
= I915_READ(reg
);
3375 if (IS_IVYBRIDGE(dev
)) {
3376 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3377 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
3379 temp
&= ~FDI_LINK_TRAIN_NONE
;
3380 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
3382 I915_WRITE(reg
, temp
);
3384 reg
= FDI_RX_CTL(pipe
);
3385 temp
= I915_READ(reg
);
3386 if (HAS_PCH_CPT(dev
)) {
3387 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3388 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
3390 temp
&= ~FDI_LINK_TRAIN_NONE
;
3391 temp
|= FDI_LINK_TRAIN_NONE
;
3393 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
3395 /* wait one idle pattern time */
3399 /* IVB wants error correction enabled */
3400 if (IS_IVYBRIDGE(dev
))
3401 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
3402 FDI_FE_ERRC_ENABLE
);
3405 /* The FDI link training functions for ILK/Ibexpeak. */
3406 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
3408 struct drm_device
*dev
= crtc
->dev
;
3409 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3410 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3411 int pipe
= intel_crtc
->pipe
;
3412 u32 reg
, temp
, tries
;
3414 /* FDI needs bits from pipe first */
3415 assert_pipe_enabled(dev_priv
, pipe
);
3417 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3419 reg
= FDI_RX_IMR(pipe
);
3420 temp
= I915_READ(reg
);
3421 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3422 temp
&= ~FDI_RX_BIT_LOCK
;
3423 I915_WRITE(reg
, temp
);
3427 /* enable CPU FDI TX and PCH FDI RX */
3428 reg
= FDI_TX_CTL(pipe
);
3429 temp
= I915_READ(reg
);
3430 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3431 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3432 temp
&= ~FDI_LINK_TRAIN_NONE
;
3433 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3434 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3436 reg
= FDI_RX_CTL(pipe
);
3437 temp
= I915_READ(reg
);
3438 temp
&= ~FDI_LINK_TRAIN_NONE
;
3439 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3440 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3445 /* Ironlake workaround, enable clock pointer after FDI enable*/
3446 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3447 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
3448 FDI_RX_PHASE_SYNC_POINTER_EN
);
3450 reg
= FDI_RX_IIR(pipe
);
3451 for (tries
= 0; tries
< 5; tries
++) {
3452 temp
= I915_READ(reg
);
3453 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3455 if ((temp
& FDI_RX_BIT_LOCK
)) {
3456 DRM_DEBUG_KMS("FDI train 1 done.\n");
3457 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3462 DRM_ERROR("FDI train 1 fail!\n");
3465 reg
= FDI_TX_CTL(pipe
);
3466 temp
= I915_READ(reg
);
3467 temp
&= ~FDI_LINK_TRAIN_NONE
;
3468 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3469 I915_WRITE(reg
, temp
);
3471 reg
= FDI_RX_CTL(pipe
);
3472 temp
= I915_READ(reg
);
3473 temp
&= ~FDI_LINK_TRAIN_NONE
;
3474 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3475 I915_WRITE(reg
, temp
);
3480 reg
= FDI_RX_IIR(pipe
);
3481 for (tries
= 0; tries
< 5; tries
++) {
3482 temp
= I915_READ(reg
);
3483 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3485 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3486 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3487 DRM_DEBUG_KMS("FDI train 2 done.\n");
3492 DRM_ERROR("FDI train 2 fail!\n");
3494 DRM_DEBUG_KMS("FDI train done\n");
3498 static const int snb_b_fdi_train_param
[] = {
3499 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
3500 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
3501 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
3502 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
3505 /* The FDI link training functions for SNB/Cougarpoint. */
3506 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
3508 struct drm_device
*dev
= crtc
->dev
;
3509 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3510 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3511 int pipe
= intel_crtc
->pipe
;
3512 u32 reg
, temp
, i
, retry
;
3514 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3516 reg
= FDI_RX_IMR(pipe
);
3517 temp
= I915_READ(reg
);
3518 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3519 temp
&= ~FDI_RX_BIT_LOCK
;
3520 I915_WRITE(reg
, temp
);
3525 /* enable CPU FDI TX and PCH FDI RX */
3526 reg
= FDI_TX_CTL(pipe
);
3527 temp
= I915_READ(reg
);
3528 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3529 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3530 temp
&= ~FDI_LINK_TRAIN_NONE
;
3531 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3532 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3534 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3535 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3537 I915_WRITE(FDI_RX_MISC(pipe
),
3538 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3540 reg
= FDI_RX_CTL(pipe
);
3541 temp
= I915_READ(reg
);
3542 if (HAS_PCH_CPT(dev
)) {
3543 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3544 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3546 temp
&= ~FDI_LINK_TRAIN_NONE
;
3547 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3549 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3554 for (i
= 0; i
< 4; i
++) {
3555 reg
= FDI_TX_CTL(pipe
);
3556 temp
= I915_READ(reg
);
3557 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3558 temp
|= snb_b_fdi_train_param
[i
];
3559 I915_WRITE(reg
, temp
);
3564 for (retry
= 0; retry
< 5; retry
++) {
3565 reg
= FDI_RX_IIR(pipe
);
3566 temp
= I915_READ(reg
);
3567 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3568 if (temp
& FDI_RX_BIT_LOCK
) {
3569 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3570 DRM_DEBUG_KMS("FDI train 1 done.\n");
3579 DRM_ERROR("FDI train 1 fail!\n");
3582 reg
= FDI_TX_CTL(pipe
);
3583 temp
= I915_READ(reg
);
3584 temp
&= ~FDI_LINK_TRAIN_NONE
;
3585 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3587 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3589 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3591 I915_WRITE(reg
, temp
);
3593 reg
= FDI_RX_CTL(pipe
);
3594 temp
= I915_READ(reg
);
3595 if (HAS_PCH_CPT(dev
)) {
3596 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3597 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3599 temp
&= ~FDI_LINK_TRAIN_NONE
;
3600 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3602 I915_WRITE(reg
, temp
);
3607 for (i
= 0; i
< 4; i
++) {
3608 reg
= FDI_TX_CTL(pipe
);
3609 temp
= I915_READ(reg
);
3610 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3611 temp
|= snb_b_fdi_train_param
[i
];
3612 I915_WRITE(reg
, temp
);
3617 for (retry
= 0; retry
< 5; retry
++) {
3618 reg
= FDI_RX_IIR(pipe
);
3619 temp
= I915_READ(reg
);
3620 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3621 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3622 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3623 DRM_DEBUG_KMS("FDI train 2 done.\n");
3632 DRM_ERROR("FDI train 2 fail!\n");
3634 DRM_DEBUG_KMS("FDI train done.\n");
3637 /* Manual link training for Ivy Bridge A0 parts */
3638 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
3640 struct drm_device
*dev
= crtc
->dev
;
3641 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3642 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3643 int pipe
= intel_crtc
->pipe
;
3644 u32 reg
, temp
, i
, j
;
3646 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3648 reg
= FDI_RX_IMR(pipe
);
3649 temp
= I915_READ(reg
);
3650 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3651 temp
&= ~FDI_RX_BIT_LOCK
;
3652 I915_WRITE(reg
, temp
);
3657 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3658 I915_READ(FDI_RX_IIR(pipe
)));
3660 /* Try each vswing and preemphasis setting twice before moving on */
3661 for (j
= 0; j
< ARRAY_SIZE(snb_b_fdi_train_param
) * 2; j
++) {
3662 /* disable first in case we need to retry */
3663 reg
= FDI_TX_CTL(pipe
);
3664 temp
= I915_READ(reg
);
3665 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
3666 temp
&= ~FDI_TX_ENABLE
;
3667 I915_WRITE(reg
, temp
);
3669 reg
= FDI_RX_CTL(pipe
);
3670 temp
= I915_READ(reg
);
3671 temp
&= ~FDI_LINK_TRAIN_AUTO
;
3672 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3673 temp
&= ~FDI_RX_ENABLE
;
3674 I915_WRITE(reg
, temp
);
3676 /* enable CPU FDI TX and PCH FDI RX */
3677 reg
= FDI_TX_CTL(pipe
);
3678 temp
= I915_READ(reg
);
3679 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3680 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3681 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
3682 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3683 temp
|= snb_b_fdi_train_param
[j
/2];
3684 temp
|= FDI_COMPOSITE_SYNC
;
3685 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3687 I915_WRITE(FDI_RX_MISC(pipe
),
3688 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3690 reg
= FDI_RX_CTL(pipe
);
3691 temp
= I915_READ(reg
);
3692 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3693 temp
|= FDI_COMPOSITE_SYNC
;
3694 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3697 udelay(1); /* should be 0.5us */
3699 for (i
= 0; i
< 4; i
++) {
3700 reg
= FDI_RX_IIR(pipe
);
3701 temp
= I915_READ(reg
);
3702 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3704 if (temp
& FDI_RX_BIT_LOCK
||
3705 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
3706 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3707 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3711 udelay(1); /* should be 0.5us */
3714 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j
/ 2);
3719 reg
= FDI_TX_CTL(pipe
);
3720 temp
= I915_READ(reg
);
3721 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3722 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
3723 I915_WRITE(reg
, temp
);
3725 reg
= FDI_RX_CTL(pipe
);
3726 temp
= I915_READ(reg
);
3727 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3728 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3729 I915_WRITE(reg
, temp
);
3732 udelay(2); /* should be 1.5us */
3734 for (i
= 0; i
< 4; i
++) {
3735 reg
= FDI_RX_IIR(pipe
);
3736 temp
= I915_READ(reg
);
3737 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3739 if (temp
& FDI_RX_SYMBOL_LOCK
||
3740 (I915_READ(reg
) & FDI_RX_SYMBOL_LOCK
)) {
3741 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3742 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3746 udelay(2); /* should be 1.5us */
3749 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j
/ 2);
3753 DRM_DEBUG_KMS("FDI train done.\n");
3756 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
3758 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3759 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3760 int pipe
= intel_crtc
->pipe
;
3764 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3765 reg
= FDI_RX_CTL(pipe
);
3766 temp
= I915_READ(reg
);
3767 temp
&= ~(FDI_DP_PORT_WIDTH_MASK
| (0x7 << 16));
3768 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3769 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3770 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
3775 /* Switch from Rawclk to PCDclk */
3776 temp
= I915_READ(reg
);
3777 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
3782 /* Enable CPU FDI TX PLL, always on for Ironlake */
3783 reg
= FDI_TX_CTL(pipe
);
3784 temp
= I915_READ(reg
);
3785 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
3786 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
3793 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
3795 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3796 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3797 int pipe
= intel_crtc
->pipe
;
3800 /* Switch from PCDclk to Rawclk */
3801 reg
= FDI_RX_CTL(pipe
);
3802 temp
= I915_READ(reg
);
3803 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
3805 /* Disable CPU FDI TX PLL */
3806 reg
= FDI_TX_CTL(pipe
);
3807 temp
= I915_READ(reg
);
3808 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
3813 reg
= FDI_RX_CTL(pipe
);
3814 temp
= I915_READ(reg
);
3815 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
3817 /* Wait for the clocks to turn off. */
3822 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
3824 struct drm_device
*dev
= crtc
->dev
;
3825 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3826 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3827 int pipe
= intel_crtc
->pipe
;
3830 /* disable CPU FDI tx and PCH FDI rx */
3831 reg
= FDI_TX_CTL(pipe
);
3832 temp
= I915_READ(reg
);
3833 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
3836 reg
= FDI_RX_CTL(pipe
);
3837 temp
= I915_READ(reg
);
3838 temp
&= ~(0x7 << 16);
3839 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3840 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
3845 /* Ironlake workaround, disable clock pointer after downing FDI */
3846 if (HAS_PCH_IBX(dev
))
3847 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3849 /* still set train pattern 1 */
3850 reg
= FDI_TX_CTL(pipe
);
3851 temp
= I915_READ(reg
);
3852 temp
&= ~FDI_LINK_TRAIN_NONE
;
3853 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3854 I915_WRITE(reg
, temp
);
3856 reg
= FDI_RX_CTL(pipe
);
3857 temp
= I915_READ(reg
);
3858 if (HAS_PCH_CPT(dev
)) {
3859 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3860 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3862 temp
&= ~FDI_LINK_TRAIN_NONE
;
3863 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3865 /* BPC in FDI rx is consistent with that in PIPECONF */
3866 temp
&= ~(0x07 << 16);
3867 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3868 I915_WRITE(reg
, temp
);
3874 bool intel_has_pending_fb_unpin(struct drm_device
*dev
)
3876 struct intel_crtc
*crtc
;
3878 /* Note that we don't need to be called with mode_config.lock here
3879 * as our list of CRTC objects is static for the lifetime of the
3880 * device and so cannot disappear as we iterate. Similarly, we can
3881 * happily treat the predicates as racy, atomic checks as userspace
3882 * cannot claim and pin a new fb without at least acquring the
3883 * struct_mutex and so serialising with us.
3885 for_each_intel_crtc(dev
, crtc
) {
3886 if (atomic_read(&crtc
->unpin_work_count
) == 0)
3889 if (crtc
->unpin_work
)
3890 intel_wait_for_vblank(dev
, crtc
->pipe
);
3898 static void page_flip_completed(struct intel_crtc
*intel_crtc
)
3900 struct drm_i915_private
*dev_priv
= to_i915(intel_crtc
->base
.dev
);
3901 struct intel_unpin_work
*work
= intel_crtc
->unpin_work
;
3903 /* ensure that the unpin work is consistent wrt ->pending. */
3905 intel_crtc
->unpin_work
= NULL
;
3908 drm_send_vblank_event(intel_crtc
->base
.dev
,
3912 drm_crtc_vblank_put(&intel_crtc
->base
);
3914 wake_up_all(&dev_priv
->pending_flip_queue
);
3915 queue_work(dev_priv
->wq
, &work
->work
);
3917 trace_i915_flip_complete(intel_crtc
->plane
,
3918 work
->pending_flip_obj
);
3921 void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
3923 struct drm_device
*dev
= crtc
->dev
;
3924 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3926 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
3927 if (WARN_ON(wait_event_timeout(dev_priv
->pending_flip_queue
,
3928 !intel_crtc_has_pending_flip(crtc
),
3930 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3932 spin_lock_irq(&dev
->event_lock
);
3933 if (intel_crtc
->unpin_work
) {
3934 WARN_ONCE(1, "Removing stuck page flip\n");
3935 page_flip_completed(intel_crtc
);
3937 spin_unlock_irq(&dev
->event_lock
);
3940 if (crtc
->primary
->fb
) {
3941 mutex_lock(&dev
->struct_mutex
);
3942 intel_finish_fb(crtc
->primary
->fb
);
3943 mutex_unlock(&dev
->struct_mutex
);
3947 /* Program iCLKIP clock to the desired frequency */
3948 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
3950 struct drm_device
*dev
= crtc
->dev
;
3951 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3952 int clock
= to_intel_crtc(crtc
)->config
->base
.adjusted_mode
.crtc_clock
;
3953 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
3956 mutex_lock(&dev_priv
->dpio_lock
);
3958 /* It is necessary to ungate the pixclk gate prior to programming
3959 * the divisors, and gate it back when it is done.
3961 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
3963 /* Disable SSCCTL */
3964 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
3965 intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
) |
3969 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3970 if (clock
== 20000) {
3975 /* The iCLK virtual clock root frequency is in MHz,
3976 * but the adjusted_mode->crtc_clock in in KHz. To get the
3977 * divisors, it is necessary to divide one by another, so we
3978 * convert the virtual clock precision to KHz here for higher
3981 u32 iclk_virtual_root_freq
= 172800 * 1000;
3982 u32 iclk_pi_range
= 64;
3983 u32 desired_divisor
, msb_divisor_value
, pi_value
;
3985 desired_divisor
= (iclk_virtual_root_freq
/ clock
);
3986 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
3987 pi_value
= desired_divisor
% iclk_pi_range
;
3990 divsel
= msb_divisor_value
- 2;
3991 phaseinc
= pi_value
;
3994 /* This should not happen with any sane values */
3995 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
3996 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
3997 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
3998 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
4000 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4007 /* Program SSCDIVINTPHASE6 */
4008 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
4009 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
4010 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
4011 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
4012 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
4013 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
4014 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
4015 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
4017 /* Program SSCAUXDIV */
4018 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
4019 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4020 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
4021 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
4023 /* Enable modulator and associated divider */
4024 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
4025 temp
&= ~SBI_SSCCTL_DISABLE
;
4026 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
4028 /* Wait for initialization time */
4031 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
4033 mutex_unlock(&dev_priv
->dpio_lock
);
4036 static void ironlake_pch_transcoder_set_timings(struct intel_crtc
*crtc
,
4037 enum pipe pch_transcoder
)
4039 struct drm_device
*dev
= crtc
->base
.dev
;
4040 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4041 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
4043 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder
),
4044 I915_READ(HTOTAL(cpu_transcoder
)));
4045 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder
),
4046 I915_READ(HBLANK(cpu_transcoder
)));
4047 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder
),
4048 I915_READ(HSYNC(cpu_transcoder
)));
4050 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder
),
4051 I915_READ(VTOTAL(cpu_transcoder
)));
4052 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder
),
4053 I915_READ(VBLANK(cpu_transcoder
)));
4054 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder
),
4055 I915_READ(VSYNC(cpu_transcoder
)));
4056 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder
),
4057 I915_READ(VSYNCSHIFT(cpu_transcoder
)));
4060 static void cpt_set_fdi_bc_bifurcation(struct drm_device
*dev
, bool enable
)
4062 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4065 temp
= I915_READ(SOUTH_CHICKEN1
);
4066 if (!!(temp
& FDI_BC_BIFURCATION_SELECT
) == enable
)
4069 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
4070 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
4072 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
4074 temp
|= FDI_BC_BIFURCATION_SELECT
;
4076 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable
? "en" : "dis");
4077 I915_WRITE(SOUTH_CHICKEN1
, temp
);
4078 POSTING_READ(SOUTH_CHICKEN1
);
4081 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc
*intel_crtc
)
4083 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4085 switch (intel_crtc
->pipe
) {
4089 if (intel_crtc
->config
->fdi_lanes
> 2)
4090 cpt_set_fdi_bc_bifurcation(dev
, false);
4092 cpt_set_fdi_bc_bifurcation(dev
, true);
4096 cpt_set_fdi_bc_bifurcation(dev
, true);
4105 * Enable PCH resources required for PCH ports:
4107 * - FDI training & RX/TX
4108 * - update transcoder timings
4109 * - DP transcoding bits
4112 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
4114 struct drm_device
*dev
= crtc
->dev
;
4115 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4116 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4117 int pipe
= intel_crtc
->pipe
;
4120 assert_pch_transcoder_disabled(dev_priv
, pipe
);
4122 if (IS_IVYBRIDGE(dev
))
4123 ivybridge_update_fdi_bc_bifurcation(intel_crtc
);
4125 /* Write the TU size bits before fdi link training, so that error
4126 * detection works. */
4127 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
4128 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
4130 /* For PCH output, training FDI link */
4131 dev_priv
->display
.fdi_link_train(crtc
);
4133 /* We need to program the right clock selection before writing the pixel
4134 * mutliplier into the DPLL. */
4135 if (HAS_PCH_CPT(dev
)) {
4138 temp
= I915_READ(PCH_DPLL_SEL
);
4139 temp
|= TRANS_DPLL_ENABLE(pipe
);
4140 sel
= TRANS_DPLLB_SEL(pipe
);
4141 if (intel_crtc
->config
->shared_dpll
== DPLL_ID_PCH_PLL_B
)
4145 I915_WRITE(PCH_DPLL_SEL
, temp
);
4148 /* XXX: pch pll's can be enabled any time before we enable the PCH
4149 * transcoder, and we actually should do this to not upset any PCH
4150 * transcoder that already use the clock when we share it.
4152 * Note that enable_shared_dpll tries to do the right thing, but
4153 * get_shared_dpll unconditionally resets the pll - we need that to have
4154 * the right LVDS enable sequence. */
4155 intel_enable_shared_dpll(intel_crtc
);
4157 /* set transcoder timing, panel must allow it */
4158 assert_panel_unlocked(dev_priv
, pipe
);
4159 ironlake_pch_transcoder_set_timings(intel_crtc
, pipe
);
4161 intel_fdi_normal_train(crtc
);
4163 /* For PCH DP, enable TRANS_DP_CTL */
4164 if (HAS_PCH_CPT(dev
) && intel_crtc
->config
->has_dp_encoder
) {
4165 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
4166 reg
= TRANS_DP_CTL(pipe
);
4167 temp
= I915_READ(reg
);
4168 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
4169 TRANS_DP_SYNC_MASK
|
4171 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
4172 TRANS_DP_ENH_FRAMING
);
4173 temp
|= bpc
<< 9; /* same format but at 11:9 */
4175 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
4176 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
4177 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
4178 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
4180 switch (intel_trans_dp_port_sel(crtc
)) {
4182 temp
|= TRANS_DP_PORT_SEL_B
;
4185 temp
|= TRANS_DP_PORT_SEL_C
;
4188 temp
|= TRANS_DP_PORT_SEL_D
;
4194 I915_WRITE(reg
, temp
);
4197 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
4200 static void lpt_pch_enable(struct drm_crtc
*crtc
)
4202 struct drm_device
*dev
= crtc
->dev
;
4203 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4204 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4205 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
4207 assert_pch_transcoder_disabled(dev_priv
, TRANSCODER_A
);
4209 lpt_program_iclkip(crtc
);
4211 /* Set transcoder timing. */
4212 ironlake_pch_transcoder_set_timings(intel_crtc
, PIPE_A
);
4214 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
4217 void intel_put_shared_dpll(struct intel_crtc
*crtc
)
4219 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
4224 if (!(pll
->config
.crtc_mask
& (1 << crtc
->pipe
))) {
4225 WARN(1, "bad %s crtc mask\n", pll
->name
);
4229 pll
->config
.crtc_mask
&= ~(1 << crtc
->pipe
);
4230 if (pll
->config
.crtc_mask
== 0) {
4232 WARN_ON(pll
->active
);
4235 crtc
->config
->shared_dpll
= DPLL_ID_PRIVATE
;
4238 struct intel_shared_dpll
*intel_get_shared_dpll(struct intel_crtc
*crtc
,
4239 struct intel_crtc_state
*crtc_state
)
4241 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
4242 struct intel_shared_dpll
*pll
;
4243 enum intel_dpll_id i
;
4245 if (HAS_PCH_IBX(dev_priv
->dev
)) {
4246 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4247 i
= (enum intel_dpll_id
) crtc
->pipe
;
4248 pll
= &dev_priv
->shared_dplls
[i
];
4250 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4251 crtc
->base
.base
.id
, pll
->name
);
4253 WARN_ON(pll
->new_config
->crtc_mask
);
4258 if (IS_BROXTON(dev_priv
->dev
)) {
4259 /* PLL is attached to port in bxt */
4260 struct intel_encoder
*encoder
;
4261 struct intel_digital_port
*intel_dig_port
;
4263 encoder
= intel_ddi_get_crtc_new_encoder(crtc_state
);
4264 if (WARN_ON(!encoder
))
4267 intel_dig_port
= enc_to_dig_port(&encoder
->base
);
4268 /* 1:1 mapping between ports and PLLs */
4269 i
= (enum intel_dpll_id
)intel_dig_port
->port
;
4270 pll
= &dev_priv
->shared_dplls
[i
];
4271 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4272 crtc
->base
.base
.id
, pll
->name
);
4273 WARN_ON(pll
->new_config
->crtc_mask
);
4278 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4279 pll
= &dev_priv
->shared_dplls
[i
];
4281 /* Only want to check enabled timings first */
4282 if (pll
->new_config
->crtc_mask
== 0)
4285 if (memcmp(&crtc_state
->dpll_hw_state
,
4286 &pll
->new_config
->hw_state
,
4287 sizeof(pll
->new_config
->hw_state
)) == 0) {
4288 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4289 crtc
->base
.base
.id
, pll
->name
,
4290 pll
->new_config
->crtc_mask
,
4296 /* Ok no matching timings, maybe there's a free one? */
4297 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4298 pll
= &dev_priv
->shared_dplls
[i
];
4299 if (pll
->new_config
->crtc_mask
== 0) {
4300 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4301 crtc
->base
.base
.id
, pll
->name
);
4309 if (pll
->new_config
->crtc_mask
== 0)
4310 pll
->new_config
->hw_state
= crtc_state
->dpll_hw_state
;
4312 crtc_state
->shared_dpll
= i
;
4313 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll
->name
,
4314 pipe_name(crtc
->pipe
));
4316 pll
->new_config
->crtc_mask
|= 1 << crtc
->pipe
;
4322 * intel_shared_dpll_start_config - start a new PLL staged config
4323 * @dev_priv: DRM device
4324 * @clear_pipes: mask of pipes that will have their PLLs freed
4326 * Starts a new PLL staged config, copying the current config but
4327 * releasing the references of pipes specified in clear_pipes.
4329 static int intel_shared_dpll_start_config(struct drm_i915_private
*dev_priv
,
4330 unsigned clear_pipes
)
4332 struct intel_shared_dpll
*pll
;
4333 enum intel_dpll_id i
;
4335 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4336 pll
= &dev_priv
->shared_dplls
[i
];
4338 pll
->new_config
= kmemdup(&pll
->config
, sizeof pll
->config
,
4340 if (!pll
->new_config
)
4343 pll
->new_config
->crtc_mask
&= ~clear_pipes
;
4350 pll
= &dev_priv
->shared_dplls
[i
];
4351 kfree(pll
->new_config
);
4352 pll
->new_config
= NULL
;
4358 static void intel_shared_dpll_commit(struct drm_i915_private
*dev_priv
)
4360 struct intel_shared_dpll
*pll
;
4361 enum intel_dpll_id i
;
4363 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4364 pll
= &dev_priv
->shared_dplls
[i
];
4366 WARN_ON(pll
->new_config
== &pll
->config
);
4368 pll
->config
= *pll
->new_config
;
4369 kfree(pll
->new_config
);
4370 pll
->new_config
= NULL
;
4374 static void intel_shared_dpll_abort_config(struct drm_i915_private
*dev_priv
)
4376 struct intel_shared_dpll
*pll
;
4377 enum intel_dpll_id i
;
4379 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4380 pll
= &dev_priv
->shared_dplls
[i
];
4382 WARN_ON(pll
->new_config
== &pll
->config
);
4384 kfree(pll
->new_config
);
4385 pll
->new_config
= NULL
;
4389 static void cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
4391 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4392 int dslreg
= PIPEDSL(pipe
);
4395 temp
= I915_READ(dslreg
);
4397 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
4398 if (wait_for(I915_READ(dslreg
) != temp
, 5))
4399 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
4404 * skl_update_scaler_users - Stages update to crtc's scaler state
4406 * @crtc_state: crtc_state
4407 * @plane: plane (NULL indicates crtc is requesting update)
4408 * @plane_state: plane's state
4409 * @force_detach: request unconditional detachment of scaler
4411 * This function updates scaler state for requested plane or crtc.
4412 * To request scaler usage update for a plane, caller shall pass plane pointer.
4413 * To request scaler usage update for crtc, caller shall pass plane pointer
4417 * 0 - scaler_usage updated successfully
4418 * error - requested scaling cannot be supported or other error condition
4421 skl_update_scaler_users(
4422 struct intel_crtc
*intel_crtc
, struct intel_crtc_state
*crtc_state
,
4423 struct intel_plane
*intel_plane
, struct intel_plane_state
*plane_state
,
4428 int src_w
, src_h
, dst_w
, dst_h
;
4430 struct drm_framebuffer
*fb
;
4431 struct intel_crtc_scaler_state
*scaler_state
;
4432 unsigned int rotation
;
4434 if (!intel_crtc
|| !crtc_state
)
4437 scaler_state
= &crtc_state
->scaler_state
;
4439 idx
= intel_plane
? drm_plane_index(&intel_plane
->base
) : SKL_CRTC_INDEX
;
4440 fb
= intel_plane
? plane_state
->base
.fb
: NULL
;
4443 src_w
= drm_rect_width(&plane_state
->src
) >> 16;
4444 src_h
= drm_rect_height(&plane_state
->src
) >> 16;
4445 dst_w
= drm_rect_width(&plane_state
->dst
);
4446 dst_h
= drm_rect_height(&plane_state
->dst
);
4447 scaler_id
= &plane_state
->scaler_id
;
4448 rotation
= plane_state
->base
.rotation
;
4450 struct drm_display_mode
*adjusted_mode
=
4451 &crtc_state
->base
.adjusted_mode
;
4452 src_w
= crtc_state
->pipe_src_w
;
4453 src_h
= crtc_state
->pipe_src_h
;
4454 dst_w
= adjusted_mode
->hdisplay
;
4455 dst_h
= adjusted_mode
->vdisplay
;
4456 scaler_id
= &scaler_state
->scaler_id
;
4457 rotation
= DRM_ROTATE_0
;
4460 need_scaling
= intel_rotation_90_or_270(rotation
) ?
4461 (src_h
!= dst_w
|| src_w
!= dst_h
):
4462 (src_w
!= dst_w
|| src_h
!= dst_h
);
4465 * if plane is being disabled or scaler is no more required or force detach
4466 * - free scaler binded to this plane/crtc
4467 * - in order to do this, update crtc->scaler_usage
4469 * Here scaler state in crtc_state is set free so that
4470 * scaler can be assigned to other user. Actual register
4471 * update to free the scaler is done in plane/panel-fit programming.
4472 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4474 if (force_detach
|| !need_scaling
|| (intel_plane
&&
4475 (!fb
|| !plane_state
->visible
))) {
4476 if (*scaler_id
>= 0) {
4477 scaler_state
->scaler_users
&= ~(1 << idx
);
4478 scaler_state
->scalers
[*scaler_id
].in_use
= 0;
4480 DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d "
4481 "crtc_state = %p scaler_users = 0x%x\n",
4482 intel_crtc
->pipe
, *scaler_id
, intel_plane
? "PLANE" : "CRTC",
4483 intel_plane
? intel_plane
->base
.base
.id
:
4484 intel_crtc
->base
.base
.id
, crtc_state
,
4485 scaler_state
->scaler_users
);
4492 if (src_w
< SKL_MIN_SRC_W
|| src_h
< SKL_MIN_SRC_H
||
4493 dst_w
< SKL_MIN_DST_W
|| dst_h
< SKL_MIN_DST_H
||
4495 src_w
> SKL_MAX_SRC_W
|| src_h
> SKL_MAX_SRC_H
||
4496 dst_w
> SKL_MAX_DST_W
|| dst_h
> SKL_MAX_DST_H
) {
4497 DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u "
4498 "size is out of scaler range\n",
4499 intel_plane
? "PLANE" : "CRTC",
4500 intel_plane
? intel_plane
->base
.base
.id
: intel_crtc
->base
.base
.id
,
4501 intel_crtc
->pipe
, idx
, src_w
, src_h
, dst_w
, dst_h
);
4505 /* check colorkey */
4506 if (intel_plane
&& intel_plane
->ckey
.flags
!= I915_SET_COLORKEY_NONE
) {
4507 DRM_DEBUG_KMS("PLANE:%d scaling with color key not allowed",
4508 intel_plane
->base
.base
.id
);
4512 /* Check src format */
4514 switch (fb
->pixel_format
) {
4515 case DRM_FORMAT_RGB565
:
4516 case DRM_FORMAT_XBGR8888
:
4517 case DRM_FORMAT_XRGB8888
:
4518 case DRM_FORMAT_ABGR8888
:
4519 case DRM_FORMAT_ARGB8888
:
4520 case DRM_FORMAT_XRGB2101010
:
4521 case DRM_FORMAT_ARGB2101010
:
4522 case DRM_FORMAT_XBGR2101010
:
4523 case DRM_FORMAT_ABGR2101010
:
4524 case DRM_FORMAT_YUYV
:
4525 case DRM_FORMAT_YVYU
:
4526 case DRM_FORMAT_UYVY
:
4527 case DRM_FORMAT_VYUY
:
4530 DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n",
4531 intel_plane
->base
.base
.id
, fb
->base
.id
, fb
->pixel_format
);
4536 /* mark this plane as a scaler user in crtc_state */
4537 scaler_state
->scaler_users
|= (1 << idx
);
4538 DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u "
4539 "crtc_state = %p scaler_users = 0x%x\n",
4540 intel_plane
? "PLANE" : "CRTC",
4541 intel_plane
? intel_plane
->base
.base
.id
: intel_crtc
->base
.base
.id
,
4542 src_w
, src_h
, dst_w
, dst_h
, crtc_state
, scaler_state
->scaler_users
);
4546 static void skylake_pfit_update(struct intel_crtc
*crtc
, int enable
)
4548 struct drm_device
*dev
= crtc
->base
.dev
;
4549 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4550 int pipe
= crtc
->pipe
;
4551 struct intel_crtc_scaler_state
*scaler_state
=
4552 &crtc
->config
->scaler_state
;
4554 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc
->config
);
4556 /* To update pfit, first update scaler state */
4557 skl_update_scaler_users(crtc
, crtc
->config
, NULL
, NULL
, !enable
);
4558 intel_atomic_setup_scalers(crtc
->base
.dev
, crtc
, crtc
->config
);
4559 skl_detach_scalers(crtc
);
4563 if (crtc
->config
->pch_pfit
.enabled
) {
4566 if (WARN_ON(crtc
->config
->scaler_state
.scaler_id
< 0)) {
4567 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4571 id
= scaler_state
->scaler_id
;
4572 I915_WRITE(SKL_PS_CTRL(pipe
, id
), PS_SCALER_EN
|
4573 PS_FILTER_MEDIUM
| scaler_state
->scalers
[id
].mode
);
4574 I915_WRITE(SKL_PS_WIN_POS(pipe
, id
), crtc
->config
->pch_pfit
.pos
);
4575 I915_WRITE(SKL_PS_WIN_SZ(pipe
, id
), crtc
->config
->pch_pfit
.size
);
4577 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc
->config
, id
);
4581 static void ironlake_pfit_enable(struct intel_crtc
*crtc
)
4583 struct drm_device
*dev
= crtc
->base
.dev
;
4584 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4585 int pipe
= crtc
->pipe
;
4587 if (crtc
->config
->pch_pfit
.enabled
) {
4588 /* Force use of hard-coded filter coefficients
4589 * as some pre-programmed values are broken,
4592 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
4593 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
4594 PF_PIPE_SEL_IVB(pipe
));
4596 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
4597 I915_WRITE(PF_WIN_POS(pipe
), crtc
->config
->pch_pfit
.pos
);
4598 I915_WRITE(PF_WIN_SZ(pipe
), crtc
->config
->pch_pfit
.size
);
4602 static void intel_enable_sprite_planes(struct drm_crtc
*crtc
)
4604 struct drm_device
*dev
= crtc
->dev
;
4605 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
4606 struct drm_plane
*plane
;
4607 struct intel_plane
*intel_plane
;
4609 drm_for_each_legacy_plane(plane
, &dev
->mode_config
.plane_list
) {
4610 intel_plane
= to_intel_plane(plane
);
4611 if (intel_plane
->pipe
== pipe
)
4612 intel_plane_restore(&intel_plane
->base
);
4616 void hsw_enable_ips(struct intel_crtc
*crtc
)
4618 struct drm_device
*dev
= crtc
->base
.dev
;
4619 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4621 if (!crtc
->config
->ips_enabled
)
4624 /* We can only enable IPS after we enable a plane and wait for a vblank */
4625 intel_wait_for_vblank(dev
, crtc
->pipe
);
4627 assert_plane_enabled(dev_priv
, crtc
->plane
);
4628 if (IS_BROADWELL(dev
)) {
4629 mutex_lock(&dev_priv
->rps
.hw_lock
);
4630 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0xc0000000));
4631 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4632 /* Quoting Art Runyan: "its not safe to expect any particular
4633 * value in IPS_CTL bit 31 after enabling IPS through the
4634 * mailbox." Moreover, the mailbox may return a bogus state,
4635 * so we need to just enable it and continue on.
4638 I915_WRITE(IPS_CTL
, IPS_ENABLE
);
4639 /* The bit only becomes 1 in the next vblank, so this wait here
4640 * is essentially intel_wait_for_vblank. If we don't have this
4641 * and don't wait for vblanks until the end of crtc_enable, then
4642 * the HW state readout code will complain that the expected
4643 * IPS_CTL value is not the one we read. */
4644 if (wait_for(I915_READ_NOTRACE(IPS_CTL
) & IPS_ENABLE
, 50))
4645 DRM_ERROR("Timed out waiting for IPS enable\n");
4649 void hsw_disable_ips(struct intel_crtc
*crtc
)
4651 struct drm_device
*dev
= crtc
->base
.dev
;
4652 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4654 if (!crtc
->config
->ips_enabled
)
4657 assert_plane_enabled(dev_priv
, crtc
->plane
);
4658 if (IS_BROADWELL(dev
)) {
4659 mutex_lock(&dev_priv
->rps
.hw_lock
);
4660 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0));
4661 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4662 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4663 if (wait_for((I915_READ(IPS_CTL
) & IPS_ENABLE
) == 0, 42))
4664 DRM_ERROR("Timed out waiting for IPS disable\n");
4666 I915_WRITE(IPS_CTL
, 0);
4667 POSTING_READ(IPS_CTL
);
4670 /* We need to wait for a vblank before we can disable the plane. */
4671 intel_wait_for_vblank(dev
, crtc
->pipe
);
4674 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4675 static void intel_crtc_load_lut(struct drm_crtc
*crtc
)
4677 struct drm_device
*dev
= crtc
->dev
;
4678 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4679 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4680 enum pipe pipe
= intel_crtc
->pipe
;
4681 int palreg
= PALETTE(pipe
);
4683 bool reenable_ips
= false;
4685 /* The clocks have to be on to load the palette. */
4686 if (!crtc
->state
->enable
|| !intel_crtc
->active
)
4689 if (HAS_GMCH_DISPLAY(dev_priv
->dev
)) {
4690 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
))
4691 assert_dsi_pll_enabled(dev_priv
);
4693 assert_pll_enabled(dev_priv
, pipe
);
4696 /* use legacy palette for Ironlake */
4697 if (!HAS_GMCH_DISPLAY(dev
))
4698 palreg
= LGC_PALETTE(pipe
);
4700 /* Workaround : Do not read or write the pipe palette/gamma data while
4701 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4703 if (IS_HASWELL(dev
) && intel_crtc
->config
->ips_enabled
&&
4704 ((I915_READ(GAMMA_MODE(pipe
)) & GAMMA_MODE_MODE_MASK
) ==
4705 GAMMA_MODE_MODE_SPLIT
)) {
4706 hsw_disable_ips(intel_crtc
);
4707 reenable_ips
= true;
4710 for (i
= 0; i
< 256; i
++) {
4711 I915_WRITE(palreg
+ 4 * i
,
4712 (intel_crtc
->lut_r
[i
] << 16) |
4713 (intel_crtc
->lut_g
[i
] << 8) |
4714 intel_crtc
->lut_b
[i
]);
4718 hsw_enable_ips(intel_crtc
);
4721 static void intel_crtc_dpms_overlay_disable(struct intel_crtc
*intel_crtc
)
4723 if (intel_crtc
->overlay
) {
4724 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4725 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4727 mutex_lock(&dev
->struct_mutex
);
4728 dev_priv
->mm
.interruptible
= false;
4729 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
4730 dev_priv
->mm
.interruptible
= true;
4731 mutex_unlock(&dev
->struct_mutex
);
4734 /* Let userspace switch the overlay on again. In most cases userspace
4735 * has to recompute where to put it anyway.
4740 * intel_post_enable_primary - Perform operations after enabling primary plane
4741 * @crtc: the CRTC whose primary plane was just enabled
4743 * Performs potentially sleeping operations that must be done after the primary
4744 * plane is enabled, such as updating FBC and IPS. Note that this may be
4745 * called due to an explicit primary plane update, or due to an implicit
4746 * re-enable that is caused when a sprite plane is updated to no longer
4747 * completely hide the primary plane.
4750 intel_post_enable_primary(struct drm_crtc
*crtc
)
4752 struct drm_device
*dev
= crtc
->dev
;
4753 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4754 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4755 int pipe
= intel_crtc
->pipe
;
4758 * BDW signals flip done immediately if the plane
4759 * is disabled, even if the plane enable is already
4760 * armed to occur at the next vblank :(
4762 if (IS_BROADWELL(dev
))
4763 intel_wait_for_vblank(dev
, pipe
);
4766 * FIXME IPS should be fine as long as one plane is
4767 * enabled, but in practice it seems to have problems
4768 * when going from primary only to sprite only and vice
4771 hsw_enable_ips(intel_crtc
);
4773 mutex_lock(&dev
->struct_mutex
);
4774 intel_fbc_update(dev
);
4775 mutex_unlock(&dev
->struct_mutex
);
4778 * Gen2 reports pipe underruns whenever all planes are disabled.
4779 * So don't enable underrun reporting before at least some planes
4781 * FIXME: Need to fix the logic to work when we turn off all planes
4782 * but leave the pipe running.
4785 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4787 /* Underruns don't raise interrupts, so check manually. */
4788 if (HAS_GMCH_DISPLAY(dev
))
4789 i9xx_check_fifo_underruns(dev_priv
);
4793 * intel_pre_disable_primary - Perform operations before disabling primary plane
4794 * @crtc: the CRTC whose primary plane is to be disabled
4796 * Performs potentially sleeping operations that must be done before the
4797 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4798 * be called due to an explicit primary plane update, or due to an implicit
4799 * disable that is caused when a sprite plane completely hides the primary
4803 intel_pre_disable_primary(struct drm_crtc
*crtc
)
4805 struct drm_device
*dev
= crtc
->dev
;
4806 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4807 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4808 int pipe
= intel_crtc
->pipe
;
4811 * Gen2 reports pipe underruns whenever all planes are disabled.
4812 * So diasble underrun reporting before all the planes get disabled.
4813 * FIXME: Need to fix the logic to work when we turn off all planes
4814 * but leave the pipe running.
4817 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
4820 * Vblank time updates from the shadow to live plane control register
4821 * are blocked if the memory self-refresh mode is active at that
4822 * moment. So to make sure the plane gets truly disabled, disable
4823 * first the self-refresh mode. The self-refresh enable bit in turn
4824 * will be checked/applied by the HW only at the next frame start
4825 * event which is after the vblank start event, so we need to have a
4826 * wait-for-vblank between disabling the plane and the pipe.
4828 if (HAS_GMCH_DISPLAY(dev
))
4829 intel_set_memory_cxsr(dev_priv
, false);
4831 mutex_lock(&dev
->struct_mutex
);
4832 if (dev_priv
->fbc
.crtc
== intel_crtc
)
4833 intel_fbc_disable(dev
);
4834 mutex_unlock(&dev
->struct_mutex
);
4837 * FIXME IPS should be fine as long as one plane is
4838 * enabled, but in practice it seems to have problems
4839 * when going from primary only to sprite only and vice
4842 hsw_disable_ips(intel_crtc
);
4845 static void intel_crtc_enable_planes(struct drm_crtc
*crtc
)
4847 intel_enable_primary_hw_plane(crtc
->primary
, crtc
);
4848 intel_enable_sprite_planes(crtc
);
4849 intel_crtc_update_cursor(crtc
, true);
4851 intel_post_enable_primary(crtc
);
4854 static void intel_crtc_disable_planes(struct drm_crtc
*crtc
)
4856 struct drm_device
*dev
= crtc
->dev
;
4857 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4858 struct intel_plane
*intel_plane
;
4859 int pipe
= intel_crtc
->pipe
;
4861 intel_crtc_wait_for_pending_flips(crtc
);
4863 intel_pre_disable_primary(crtc
);
4865 intel_crtc_dpms_overlay_disable(intel_crtc
);
4866 for_each_intel_plane(dev
, intel_plane
) {
4867 if (intel_plane
->pipe
== pipe
) {
4868 struct drm_crtc
*from
= intel_plane
->base
.crtc
;
4870 intel_plane
->disable_plane(&intel_plane
->base
,
4871 from
?: crtc
, true);
4876 * FIXME: Once we grow proper nuclear flip support out of this we need
4877 * to compute the mask of flip planes precisely. For the time being
4878 * consider this a flip to a NULL plane.
4880 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_ALL_MASK(pipe
));
4883 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
4885 struct drm_device
*dev
= crtc
->dev
;
4886 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4887 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4888 struct intel_encoder
*encoder
;
4889 int pipe
= intel_crtc
->pipe
;
4891 WARN_ON(!crtc
->state
->enable
);
4893 if (intel_crtc
->active
)
4896 if (intel_crtc
->config
->has_pch_encoder
)
4897 intel_prepare_shared_dpll(intel_crtc
);
4899 if (intel_crtc
->config
->has_dp_encoder
)
4900 intel_dp_set_m_n(intel_crtc
, M1_N1
);
4902 intel_set_pipe_timings(intel_crtc
);
4904 if (intel_crtc
->config
->has_pch_encoder
) {
4905 intel_cpu_transcoder_set_m_n(intel_crtc
,
4906 &intel_crtc
->config
->fdi_m_n
, NULL
);
4909 ironlake_set_pipeconf(crtc
);
4911 intel_crtc
->active
= true;
4913 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4914 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, true);
4916 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4917 if (encoder
->pre_enable
)
4918 encoder
->pre_enable(encoder
);
4920 if (intel_crtc
->config
->has_pch_encoder
) {
4921 /* Note: FDI PLL enabling _must_ be done before we enable the
4922 * cpu pipes, hence this is separate from all the other fdi/pch
4924 ironlake_fdi_pll_enable(intel_crtc
);
4926 assert_fdi_tx_disabled(dev_priv
, pipe
);
4927 assert_fdi_rx_disabled(dev_priv
, pipe
);
4930 ironlake_pfit_enable(intel_crtc
);
4933 * On ILK+ LUT must be loaded before the pipe is running but with
4936 intel_crtc_load_lut(crtc
);
4938 intel_update_watermarks(crtc
);
4939 intel_enable_pipe(intel_crtc
);
4941 if (intel_crtc
->config
->has_pch_encoder
)
4942 ironlake_pch_enable(crtc
);
4944 assert_vblank_disabled(crtc
);
4945 drm_crtc_vblank_on(crtc
);
4947 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4948 encoder
->enable(encoder
);
4950 if (HAS_PCH_CPT(dev
))
4951 cpt_verify_modeset(dev
, intel_crtc
->pipe
);
4954 /* IPS only exists on ULT machines and is tied to pipe A. */
4955 static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc
)
4957 return HAS_IPS(crtc
->base
.dev
) && crtc
->pipe
== PIPE_A
;
4961 * This implements the workaround described in the "notes" section of the mode
4962 * set sequence documentation. When going from no pipes or single pipe to
4963 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4964 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4966 static void haswell_mode_set_planes_workaround(struct intel_crtc
*crtc
)
4968 struct drm_device
*dev
= crtc
->base
.dev
;
4969 struct intel_crtc
*crtc_it
, *other_active_crtc
= NULL
;
4971 /* We want to get the other_active_crtc only if there's only 1 other
4973 for_each_intel_crtc(dev
, crtc_it
) {
4974 if (!crtc_it
->active
|| crtc_it
== crtc
)
4977 if (other_active_crtc
)
4980 other_active_crtc
= crtc_it
;
4982 if (!other_active_crtc
)
4985 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
4986 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
4989 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
4991 struct drm_device
*dev
= crtc
->dev
;
4992 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4993 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4994 struct intel_encoder
*encoder
;
4995 int pipe
= intel_crtc
->pipe
;
4997 WARN_ON(!crtc
->state
->enable
);
4999 if (intel_crtc
->active
)
5002 if (intel_crtc_to_shared_dpll(intel_crtc
))
5003 intel_enable_shared_dpll(intel_crtc
);
5005 if (intel_crtc
->config
->has_dp_encoder
)
5006 intel_dp_set_m_n(intel_crtc
, M1_N1
);
5008 intel_set_pipe_timings(intel_crtc
);
5010 if (intel_crtc
->config
->cpu_transcoder
!= TRANSCODER_EDP
) {
5011 I915_WRITE(PIPE_MULT(intel_crtc
->config
->cpu_transcoder
),
5012 intel_crtc
->config
->pixel_multiplier
- 1);
5015 if (intel_crtc
->config
->has_pch_encoder
) {
5016 intel_cpu_transcoder_set_m_n(intel_crtc
,
5017 &intel_crtc
->config
->fdi_m_n
, NULL
);
5020 haswell_set_pipeconf(crtc
);
5022 intel_set_pipe_csc(crtc
);
5024 intel_crtc
->active
= true;
5026 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5027 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5028 if (encoder
->pre_enable
)
5029 encoder
->pre_enable(encoder
);
5031 if (intel_crtc
->config
->has_pch_encoder
) {
5032 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
5034 dev_priv
->display
.fdi_link_train(crtc
);
5037 intel_ddi_enable_pipe_clock(intel_crtc
);
5039 if (INTEL_INFO(dev
)->gen
== 9)
5040 skylake_pfit_update(intel_crtc
, 1);
5041 else if (INTEL_INFO(dev
)->gen
< 9)
5042 ironlake_pfit_enable(intel_crtc
);
5044 MISSING_CASE(INTEL_INFO(dev
)->gen
);
5047 * On ILK+ LUT must be loaded before the pipe is running but with
5050 intel_crtc_load_lut(crtc
);
5052 intel_ddi_set_pipe_settings(crtc
);
5053 intel_ddi_enable_transcoder_func(crtc
);
5055 intel_update_watermarks(crtc
);
5056 intel_enable_pipe(intel_crtc
);
5058 if (intel_crtc
->config
->has_pch_encoder
)
5059 lpt_pch_enable(crtc
);
5061 if (intel_crtc
->config
->dp_encoder_is_mst
)
5062 intel_ddi_set_vc_payload_alloc(crtc
, true);
5064 assert_vblank_disabled(crtc
);
5065 drm_crtc_vblank_on(crtc
);
5067 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5068 encoder
->enable(encoder
);
5069 intel_opregion_notify_encoder(encoder
, true);
5072 /* If we change the relative order between pipe/planes enabling, we need
5073 * to change the workaround. */
5074 haswell_mode_set_planes_workaround(intel_crtc
);
5077 static void ironlake_pfit_disable(struct intel_crtc
*crtc
)
5079 struct drm_device
*dev
= crtc
->base
.dev
;
5080 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5081 int pipe
= crtc
->pipe
;
5083 /* To avoid upsetting the power well on haswell only disable the pfit if
5084 * it's in use. The hw state code will make sure we get this right. */
5085 if (crtc
->config
->pch_pfit
.enabled
) {
5086 I915_WRITE(PF_CTL(pipe
), 0);
5087 I915_WRITE(PF_WIN_POS(pipe
), 0);
5088 I915_WRITE(PF_WIN_SZ(pipe
), 0);
5092 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
5094 struct drm_device
*dev
= crtc
->dev
;
5095 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5096 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5097 struct intel_encoder
*encoder
;
5098 int pipe
= intel_crtc
->pipe
;
5101 if (!intel_crtc
->active
)
5104 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5105 encoder
->disable(encoder
);
5107 drm_crtc_vblank_off(crtc
);
5108 assert_vblank_disabled(crtc
);
5110 if (intel_crtc
->config
->has_pch_encoder
)
5111 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, false);
5113 intel_disable_pipe(intel_crtc
);
5115 ironlake_pfit_disable(intel_crtc
);
5117 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5118 if (encoder
->post_disable
)
5119 encoder
->post_disable(encoder
);
5121 if (intel_crtc
->config
->has_pch_encoder
) {
5122 ironlake_fdi_disable(crtc
);
5124 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
5126 if (HAS_PCH_CPT(dev
)) {
5127 /* disable TRANS_DP_CTL */
5128 reg
= TRANS_DP_CTL(pipe
);
5129 temp
= I915_READ(reg
);
5130 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
|
5131 TRANS_DP_PORT_SEL_MASK
);
5132 temp
|= TRANS_DP_PORT_SEL_NONE
;
5133 I915_WRITE(reg
, temp
);
5135 /* disable DPLL_SEL */
5136 temp
= I915_READ(PCH_DPLL_SEL
);
5137 temp
&= ~(TRANS_DPLL_ENABLE(pipe
) | TRANS_DPLLB_SEL(pipe
));
5138 I915_WRITE(PCH_DPLL_SEL
, temp
);
5141 /* disable PCH DPLL */
5142 intel_disable_shared_dpll(intel_crtc
);
5144 ironlake_fdi_pll_disable(intel_crtc
);
5147 intel_crtc
->active
= false;
5148 intel_update_watermarks(crtc
);
5150 mutex_lock(&dev
->struct_mutex
);
5151 intel_fbc_update(dev
);
5152 mutex_unlock(&dev
->struct_mutex
);
5155 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
5157 struct drm_device
*dev
= crtc
->dev
;
5158 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5159 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5160 struct intel_encoder
*encoder
;
5161 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
5163 if (!intel_crtc
->active
)
5166 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5167 intel_opregion_notify_encoder(encoder
, false);
5168 encoder
->disable(encoder
);
5171 drm_crtc_vblank_off(crtc
);
5172 assert_vblank_disabled(crtc
);
5174 if (intel_crtc
->config
->has_pch_encoder
)
5175 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
5177 intel_disable_pipe(intel_crtc
);
5179 if (intel_crtc
->config
->dp_encoder_is_mst
)
5180 intel_ddi_set_vc_payload_alloc(crtc
, false);
5182 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
5184 if (INTEL_INFO(dev
)->gen
== 9)
5185 skylake_pfit_update(intel_crtc
, 0);
5186 else if (INTEL_INFO(dev
)->gen
< 9)
5187 ironlake_pfit_disable(intel_crtc
);
5189 MISSING_CASE(INTEL_INFO(dev
)->gen
);
5191 intel_ddi_disable_pipe_clock(intel_crtc
);
5193 if (intel_crtc
->config
->has_pch_encoder
) {
5194 lpt_disable_pch_transcoder(dev_priv
);
5195 intel_ddi_fdi_disable(crtc
);
5198 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5199 if (encoder
->post_disable
)
5200 encoder
->post_disable(encoder
);
5202 intel_crtc
->active
= false;
5203 intel_update_watermarks(crtc
);
5205 mutex_lock(&dev
->struct_mutex
);
5206 intel_fbc_update(dev
);
5207 mutex_unlock(&dev
->struct_mutex
);
5209 if (intel_crtc_to_shared_dpll(intel_crtc
))
5210 intel_disable_shared_dpll(intel_crtc
);
5213 static void ironlake_crtc_off(struct drm_crtc
*crtc
)
5215 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5216 intel_put_shared_dpll(intel_crtc
);
5220 static void i9xx_pfit_enable(struct intel_crtc
*crtc
)
5222 struct drm_device
*dev
= crtc
->base
.dev
;
5223 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5224 struct intel_crtc_state
*pipe_config
= crtc
->config
;
5226 if (!pipe_config
->gmch_pfit
.control
)
5230 * The panel fitter should only be adjusted whilst the pipe is disabled,
5231 * according to register description and PRM.
5233 WARN_ON(I915_READ(PFIT_CONTROL
) & PFIT_ENABLE
);
5234 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
5236 I915_WRITE(PFIT_PGM_RATIOS
, pipe_config
->gmch_pfit
.pgm_ratios
);
5237 I915_WRITE(PFIT_CONTROL
, pipe_config
->gmch_pfit
.control
);
5239 /* Border color in case we don't scale up to the full screen. Black by
5240 * default, change to something else for debugging. */
5241 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
5244 static enum intel_display_power_domain
port_to_power_domain(enum port port
)
5248 return POWER_DOMAIN_PORT_DDI_A_4_LANES
;
5250 return POWER_DOMAIN_PORT_DDI_B_4_LANES
;
5252 return POWER_DOMAIN_PORT_DDI_C_4_LANES
;
5254 return POWER_DOMAIN_PORT_DDI_D_4_LANES
;
5257 return POWER_DOMAIN_PORT_OTHER
;
5261 #define for_each_power_domain(domain, mask) \
5262 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5263 if ((1 << (domain)) & (mask))
5265 enum intel_display_power_domain
5266 intel_display_port_power_domain(struct intel_encoder
*intel_encoder
)
5268 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5269 struct intel_digital_port
*intel_dig_port
;
5271 switch (intel_encoder
->type
) {
5272 case INTEL_OUTPUT_UNKNOWN
:
5273 /* Only DDI platforms should ever use this output type */
5274 WARN_ON_ONCE(!HAS_DDI(dev
));
5275 case INTEL_OUTPUT_DISPLAYPORT
:
5276 case INTEL_OUTPUT_HDMI
:
5277 case INTEL_OUTPUT_EDP
:
5278 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
5279 return port_to_power_domain(intel_dig_port
->port
);
5280 case INTEL_OUTPUT_DP_MST
:
5281 intel_dig_port
= enc_to_mst(&intel_encoder
->base
)->primary
;
5282 return port_to_power_domain(intel_dig_port
->port
);
5283 case INTEL_OUTPUT_ANALOG
:
5284 return POWER_DOMAIN_PORT_CRT
;
5285 case INTEL_OUTPUT_DSI
:
5286 return POWER_DOMAIN_PORT_DSI
;
5288 return POWER_DOMAIN_PORT_OTHER
;
5292 static unsigned long get_crtc_power_domains(struct drm_crtc
*crtc
)
5294 struct drm_device
*dev
= crtc
->dev
;
5295 struct intel_encoder
*intel_encoder
;
5296 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5297 enum pipe pipe
= intel_crtc
->pipe
;
5299 enum transcoder transcoder
;
5301 transcoder
= intel_pipe_to_cpu_transcoder(dev
->dev_private
, pipe
);
5303 mask
= BIT(POWER_DOMAIN_PIPE(pipe
));
5304 mask
|= BIT(POWER_DOMAIN_TRANSCODER(transcoder
));
5305 if (intel_crtc
->config
->pch_pfit
.enabled
||
5306 intel_crtc
->config
->pch_pfit
.force_thru
)
5307 mask
|= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe
));
5309 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
5310 mask
|= BIT(intel_display_port_power_domain(intel_encoder
));
5315 static void modeset_update_crtc_power_domains(struct drm_atomic_state
*state
)
5317 struct drm_device
*dev
= state
->dev
;
5318 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5319 unsigned long pipe_domains
[I915_MAX_PIPES
] = { 0, };
5320 struct intel_crtc
*crtc
;
5323 * First get all needed power domains, then put all unneeded, to avoid
5324 * any unnecessary toggling of the power wells.
5326 for_each_intel_crtc(dev
, crtc
) {
5327 enum intel_display_power_domain domain
;
5329 if (!crtc
->base
.state
->enable
)
5332 pipe_domains
[crtc
->pipe
] = get_crtc_power_domains(&crtc
->base
);
5334 for_each_power_domain(domain
, pipe_domains
[crtc
->pipe
])
5335 intel_display_power_get(dev_priv
, domain
);
5338 if (dev_priv
->display
.modeset_global_resources
)
5339 dev_priv
->display
.modeset_global_resources(state
);
5341 for_each_intel_crtc(dev
, crtc
) {
5342 enum intel_display_power_domain domain
;
5344 for_each_power_domain(domain
, crtc
->enabled_power_domains
)
5345 intel_display_power_put(dev_priv
, domain
);
5347 crtc
->enabled_power_domains
= pipe_domains
[crtc
->pipe
];
5350 intel_display_set_init_power(dev_priv
, false);
5353 void broxton_set_cdclk(struct drm_device
*dev
, int frequency
)
5355 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5358 uint32_t current_freq
;
5361 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5362 switch (frequency
) {
5364 divider
= BXT_CDCLK_CD2X_DIV_SEL_4
;
5365 ratio
= BXT_DE_PLL_RATIO(60);
5368 divider
= BXT_CDCLK_CD2X_DIV_SEL_2
;
5369 ratio
= BXT_DE_PLL_RATIO(60);
5372 divider
= BXT_CDCLK_CD2X_DIV_SEL_1_5
;
5373 ratio
= BXT_DE_PLL_RATIO(60);
5376 divider
= BXT_CDCLK_CD2X_DIV_SEL_1
;
5377 ratio
= BXT_DE_PLL_RATIO(60);
5380 divider
= BXT_CDCLK_CD2X_DIV_SEL_1
;
5381 ratio
= BXT_DE_PLL_RATIO(65);
5385 * Bypass frequency with DE PLL disabled. Init ratio, divider
5386 * to suppress GCC warning.
5392 DRM_ERROR("unsupported CDCLK freq %d", frequency
);
5397 mutex_lock(&dev_priv
->rps
.hw_lock
);
5398 /* Inform power controller of upcoming frequency change */
5399 ret
= sandybridge_pcode_write(dev_priv
, HSW_PCODE_DE_WRITE_FREQ_REQ
,
5401 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5404 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5409 current_freq
= I915_READ(CDCLK_CTL
) & CDCLK_FREQ_DECIMAL_MASK
;
5410 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5411 current_freq
= current_freq
* 500 + 1000;
5414 * DE PLL has to be disabled when
5415 * - setting to 19.2MHz (bypass, PLL isn't used)
5416 * - before setting to 624MHz (PLL needs toggling)
5417 * - before setting to any frequency from 624MHz (PLL needs toggling)
5419 if (frequency
== 19200 || frequency
== 624000 ||
5420 current_freq
== 624000) {
5421 I915_WRITE(BXT_DE_PLL_ENABLE
, ~BXT_DE_PLL_PLL_ENABLE
);
5423 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE
) & BXT_DE_PLL_LOCK
),
5425 DRM_ERROR("timout waiting for DE PLL unlock\n");
5428 if (frequency
!= 19200) {
5431 val
= I915_READ(BXT_DE_PLL_CTL
);
5432 val
&= ~BXT_DE_PLL_RATIO_MASK
;
5434 I915_WRITE(BXT_DE_PLL_CTL
, val
);
5436 I915_WRITE(BXT_DE_PLL_ENABLE
, BXT_DE_PLL_PLL_ENABLE
);
5438 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE
) & BXT_DE_PLL_LOCK
, 1))
5439 DRM_ERROR("timeout waiting for DE PLL lock\n");
5441 val
= I915_READ(CDCLK_CTL
);
5442 val
&= ~BXT_CDCLK_CD2X_DIV_SEL_MASK
;
5445 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5448 val
&= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE
;
5449 if (frequency
>= 500000)
5450 val
|= BXT_CDCLK_SSA_PRECHARGE_ENABLE
;
5452 val
&= ~CDCLK_FREQ_DECIMAL_MASK
;
5453 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5454 val
|= (frequency
- 1000) / 500;
5455 I915_WRITE(CDCLK_CTL
, val
);
5458 mutex_lock(&dev_priv
->rps
.hw_lock
);
5459 ret
= sandybridge_pcode_write(dev_priv
, HSW_PCODE_DE_WRITE_FREQ_REQ
,
5460 DIV_ROUND_UP(frequency
, 25000));
5461 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5464 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5469 dev_priv
->cdclk_freq
= frequency
;
5472 void broxton_init_cdclk(struct drm_device
*dev
)
5474 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5478 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5479 * or else the reset will hang because there is no PCH to respond.
5480 * Move the handshake programming to initialization sequence.
5481 * Previously was left up to BIOS.
5483 val
= I915_READ(HSW_NDE_RSTWRN_OPT
);
5484 val
&= ~RESET_PCH_HANDSHAKE_ENABLE
;
5485 I915_WRITE(HSW_NDE_RSTWRN_OPT
, val
);
5487 /* Enable PG1 for cdclk */
5488 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
5490 /* check if cd clock is enabled */
5491 if (I915_READ(BXT_DE_PLL_ENABLE
) & BXT_DE_PLL_PLL_ENABLE
) {
5492 DRM_DEBUG_KMS("Display already initialized\n");
5498 * - The initial CDCLK needs to be read from VBT.
5499 * Need to make this change after VBT has changes for BXT.
5500 * - check if setting the max (or any) cdclk freq is really necessary
5501 * here, it belongs to modeset time
5503 broxton_set_cdclk(dev
, 624000);
5505 I915_WRITE(DBUF_CTL
, I915_READ(DBUF_CTL
) | DBUF_POWER_REQUEST
);
5506 POSTING_READ(DBUF_CTL
);
5510 if (!(I915_READ(DBUF_CTL
) & DBUF_POWER_STATE
))
5511 DRM_ERROR("DBuf power enable timeout!\n");
5514 void broxton_uninit_cdclk(struct drm_device
*dev
)
5516 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5518 I915_WRITE(DBUF_CTL
, I915_READ(DBUF_CTL
) & ~DBUF_POWER_REQUEST
);
5519 POSTING_READ(DBUF_CTL
);
5523 if (I915_READ(DBUF_CTL
) & DBUF_POWER_STATE
)
5524 DRM_ERROR("DBuf power disable timeout!\n");
5526 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5527 broxton_set_cdclk(dev
, 19200);
5529 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
5532 /* returns HPLL frequency in kHz */
5533 static int valleyview_get_vco(struct drm_i915_private
*dev_priv
)
5535 int hpll_freq
, vco_freq
[] = { 800, 1600, 2000, 2400 };
5537 /* Obtain SKU information */
5538 mutex_lock(&dev_priv
->dpio_lock
);
5539 hpll_freq
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
) &
5540 CCK_FUSE_HPLL_FREQ_MASK
;
5541 mutex_unlock(&dev_priv
->dpio_lock
);
5543 return vco_freq
[hpll_freq
] * 1000;
5546 static void vlv_update_cdclk(struct drm_device
*dev
)
5548 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5550 dev_priv
->cdclk_freq
= dev_priv
->display
.get_display_clock_speed(dev
);
5551 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5552 dev_priv
->cdclk_freq
);
5555 * Program the gmbus_freq based on the cdclk frequency.
5556 * BSpec erroneously claims we should aim for 4MHz, but
5557 * in fact 1MHz is the correct frequency.
5559 I915_WRITE(GMBUSFREQ_VLV
, DIV_ROUND_UP(dev_priv
->cdclk_freq
, 1000));
5562 /* Adjust CDclk dividers to allow high res or save power if possible */
5563 static void valleyview_set_cdclk(struct drm_device
*dev
, int cdclk
)
5565 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5568 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
)
5569 != dev_priv
->cdclk_freq
);
5571 if (cdclk
>= 320000) /* jump to highest voltage for 400MHz too */
5573 else if (cdclk
== 266667)
5578 mutex_lock(&dev_priv
->rps
.hw_lock
);
5579 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
5580 val
&= ~DSPFREQGUAR_MASK
;
5581 val
|= (cmd
<< DSPFREQGUAR_SHIFT
);
5582 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
5583 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
5584 DSPFREQSTAT_MASK
) == (cmd
<< DSPFREQSTAT_SHIFT
),
5586 DRM_ERROR("timed out waiting for CDclk change\n");
5588 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5590 if (cdclk
== 400000) {
5593 divider
= DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, cdclk
) - 1;
5595 mutex_lock(&dev_priv
->dpio_lock
);
5596 /* adjust cdclk divider */
5597 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
5598 val
&= ~DISPLAY_FREQUENCY_VALUES
;
5600 vlv_cck_write(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
, val
);
5602 if (wait_for((vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
) &
5603 DISPLAY_FREQUENCY_STATUS
) == (divider
<< DISPLAY_FREQUENCY_STATUS_SHIFT
),
5605 DRM_ERROR("timed out waiting for CDclk change\n");
5606 mutex_unlock(&dev_priv
->dpio_lock
);
5609 mutex_lock(&dev_priv
->dpio_lock
);
5610 /* adjust self-refresh exit latency value */
5611 val
= vlv_bunit_read(dev_priv
, BUNIT_REG_BISOC
);
5615 * For high bandwidth configs, we set a higher latency in the bunit
5616 * so that the core display fetch happens in time to avoid underruns.
5618 if (cdclk
== 400000)
5619 val
|= 4500 / 250; /* 4.5 usec */
5621 val
|= 3000 / 250; /* 3.0 usec */
5622 vlv_bunit_write(dev_priv
, BUNIT_REG_BISOC
, val
);
5623 mutex_unlock(&dev_priv
->dpio_lock
);
5625 vlv_update_cdclk(dev
);
5628 static void cherryview_set_cdclk(struct drm_device
*dev
, int cdclk
)
5630 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5633 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
)
5634 != dev_priv
->cdclk_freq
);
5643 MISSING_CASE(cdclk
);
5648 * Specs are full of misinformation, but testing on actual
5649 * hardware has shown that we just need to write the desired
5650 * CCK divider into the Punit register.
5652 cmd
= DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, cdclk
) - 1;
5654 mutex_lock(&dev_priv
->rps
.hw_lock
);
5655 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
5656 val
&= ~DSPFREQGUAR_MASK_CHV
;
5657 val
|= (cmd
<< DSPFREQGUAR_SHIFT_CHV
);
5658 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
5659 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
5660 DSPFREQSTAT_MASK_CHV
) == (cmd
<< DSPFREQSTAT_SHIFT_CHV
),
5662 DRM_ERROR("timed out waiting for CDclk change\n");
5664 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5666 vlv_update_cdclk(dev
);
5669 static int valleyview_calc_cdclk(struct drm_i915_private
*dev_priv
,
5672 int freq_320
= (dev_priv
->hpll_freq
<< 1) % 320000 != 0 ? 333333 : 320000;
5673 int limit
= IS_CHERRYVIEW(dev_priv
) ? 95 : 90;
5676 * Really only a few cases to deal with, as only 4 CDclks are supported:
5679 * 320/333MHz (depends on HPLL freq)
5681 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5682 * of the lower bin and adjust if needed.
5684 * We seem to get an unstable or solid color picture at 200MHz.
5685 * Not sure what's wrong. For now use 200MHz only when all pipes
5688 if (!IS_CHERRYVIEW(dev_priv
) &&
5689 max_pixclk
> freq_320
*limit
/100)
5691 else if (max_pixclk
> 266667*limit
/100)
5693 else if (max_pixclk
> 0)
5699 static int broxton_calc_cdclk(struct drm_i915_private
*dev_priv
,
5704 * - remove the guardband, it's not needed on BXT
5705 * - set 19.2MHz bypass frequency if there are no active pipes
5707 if (max_pixclk
> 576000*9/10)
5709 else if (max_pixclk
> 384000*9/10)
5711 else if (max_pixclk
> 288000*9/10)
5713 else if (max_pixclk
> 144000*9/10)
5719 /* Compute the max pixel clock for new configuration. Uses atomic state if
5720 * that's non-NULL, look at current state otherwise. */
5721 static int intel_mode_max_pixclk(struct drm_device
*dev
,
5722 struct drm_atomic_state
*state
)
5724 struct intel_crtc
*intel_crtc
;
5725 struct intel_crtc_state
*crtc_state
;
5728 for_each_intel_crtc(dev
, intel_crtc
) {
5731 intel_atomic_get_crtc_state(state
, intel_crtc
);
5733 crtc_state
= intel_crtc
->config
;
5734 if (IS_ERR(crtc_state
))
5735 return PTR_ERR(crtc_state
);
5737 if (!crtc_state
->base
.enable
)
5740 max_pixclk
= max(max_pixclk
,
5741 crtc_state
->base
.adjusted_mode
.crtc_clock
);
5747 static int valleyview_modeset_global_pipes(struct drm_atomic_state
*state
)
5749 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
5750 struct drm_crtc
*crtc
;
5751 struct drm_crtc_state
*crtc_state
;
5752 int max_pixclk
= intel_mode_max_pixclk(state
->dev
, state
);
5758 if (IS_VALLEYVIEW(dev_priv
))
5759 cdclk
= valleyview_calc_cdclk(dev_priv
, max_pixclk
);
5761 cdclk
= broxton_calc_cdclk(dev_priv
, max_pixclk
);
5763 if (cdclk
== dev_priv
->cdclk_freq
)
5766 /* add all active pipes to the state */
5767 for_each_crtc(state
->dev
, crtc
) {
5768 if (!crtc
->state
->enable
)
5771 crtc_state
= drm_atomic_get_crtc_state(state
, crtc
);
5772 if (IS_ERR(crtc_state
))
5773 return PTR_ERR(crtc_state
);
5776 /* disable/enable all currently active pipes while we change cdclk */
5777 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
)
5778 if (crtc_state
->enable
)
5779 crtc_state
->mode_changed
= true;
5784 static void vlv_program_pfi_credits(struct drm_i915_private
*dev_priv
)
5786 unsigned int credits
, default_credits
;
5788 if (IS_CHERRYVIEW(dev_priv
))
5789 default_credits
= PFI_CREDIT(12);
5791 default_credits
= PFI_CREDIT(8);
5793 if (DIV_ROUND_CLOSEST(dev_priv
->cdclk_freq
, 1000) >= dev_priv
->rps
.cz_freq
) {
5794 /* CHV suggested value is 31 or 63 */
5795 if (IS_CHERRYVIEW(dev_priv
))
5796 credits
= PFI_CREDIT_31
;
5798 credits
= PFI_CREDIT(15);
5800 credits
= default_credits
;
5804 * WA - write default credits before re-programming
5805 * FIXME: should we also set the resend bit here?
5807 I915_WRITE(GCI_CONTROL
, VGA_FAST_MODE_DISABLE
|
5810 I915_WRITE(GCI_CONTROL
, VGA_FAST_MODE_DISABLE
|
5811 credits
| PFI_CREDIT_RESEND
);
5814 * FIXME is this guaranteed to clear
5815 * immediately or should we poll for it?
5817 WARN_ON(I915_READ(GCI_CONTROL
) & PFI_CREDIT_RESEND
);
5820 static void valleyview_modeset_global_resources(struct drm_atomic_state
*old_state
)
5822 struct drm_device
*dev
= old_state
->dev
;
5823 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5824 int max_pixclk
= intel_mode_max_pixclk(dev
, NULL
);
5827 /* The path in intel_mode_max_pixclk() with a NULL atomic state should
5829 if (WARN_ON(max_pixclk
< 0))
5832 req_cdclk
= valleyview_calc_cdclk(dev_priv
, max_pixclk
);
5834 if (req_cdclk
!= dev_priv
->cdclk_freq
) {
5836 * FIXME: We can end up here with all power domains off, yet
5837 * with a CDCLK frequency other than the minimum. To account
5838 * for this take the PIPE-A power domain, which covers the HW
5839 * blocks needed for the following programming. This can be
5840 * removed once it's guaranteed that we get here either with
5841 * the minimum CDCLK set, or the required power domains
5844 intel_display_power_get(dev_priv
, POWER_DOMAIN_PIPE_A
);
5846 if (IS_CHERRYVIEW(dev
))
5847 cherryview_set_cdclk(dev
, req_cdclk
);
5849 valleyview_set_cdclk(dev
, req_cdclk
);
5851 vlv_program_pfi_credits(dev_priv
);
5853 intel_display_power_put(dev_priv
, POWER_DOMAIN_PIPE_A
);
5857 static void valleyview_crtc_enable(struct drm_crtc
*crtc
)
5859 struct drm_device
*dev
= crtc
->dev
;
5860 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5861 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5862 struct intel_encoder
*encoder
;
5863 int pipe
= intel_crtc
->pipe
;
5866 WARN_ON(!crtc
->state
->enable
);
5868 if (intel_crtc
->active
)
5871 is_dsi
= intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
);
5874 if (IS_CHERRYVIEW(dev
))
5875 chv_prepare_pll(intel_crtc
, intel_crtc
->config
);
5877 vlv_prepare_pll(intel_crtc
, intel_crtc
->config
);
5880 if (intel_crtc
->config
->has_dp_encoder
)
5881 intel_dp_set_m_n(intel_crtc
, M1_N1
);
5883 intel_set_pipe_timings(intel_crtc
);
5885 if (IS_CHERRYVIEW(dev
) && pipe
== PIPE_B
) {
5886 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5888 I915_WRITE(CHV_BLEND(pipe
), CHV_BLEND_LEGACY
);
5889 I915_WRITE(CHV_CANVAS(pipe
), 0);
5892 i9xx_set_pipeconf(intel_crtc
);
5894 intel_crtc
->active
= true;
5896 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5898 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5899 if (encoder
->pre_pll_enable
)
5900 encoder
->pre_pll_enable(encoder
);
5903 if (IS_CHERRYVIEW(dev
))
5904 chv_enable_pll(intel_crtc
, intel_crtc
->config
);
5906 vlv_enable_pll(intel_crtc
, intel_crtc
->config
);
5909 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5910 if (encoder
->pre_enable
)
5911 encoder
->pre_enable(encoder
);
5913 i9xx_pfit_enable(intel_crtc
);
5915 intel_crtc_load_lut(crtc
);
5917 intel_update_watermarks(crtc
);
5918 intel_enable_pipe(intel_crtc
);
5920 assert_vblank_disabled(crtc
);
5921 drm_crtc_vblank_on(crtc
);
5923 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5924 encoder
->enable(encoder
);
5927 static void i9xx_set_pll_dividers(struct intel_crtc
*crtc
)
5929 struct drm_device
*dev
= crtc
->base
.dev
;
5930 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5932 I915_WRITE(FP0(crtc
->pipe
), crtc
->config
->dpll_hw_state
.fp0
);
5933 I915_WRITE(FP1(crtc
->pipe
), crtc
->config
->dpll_hw_state
.fp1
);
5936 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
5938 struct drm_device
*dev
= crtc
->dev
;
5939 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5940 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5941 struct intel_encoder
*encoder
;
5942 int pipe
= intel_crtc
->pipe
;
5944 WARN_ON(!crtc
->state
->enable
);
5946 if (intel_crtc
->active
)
5949 i9xx_set_pll_dividers(intel_crtc
);
5951 if (intel_crtc
->config
->has_dp_encoder
)
5952 intel_dp_set_m_n(intel_crtc
, M1_N1
);
5954 intel_set_pipe_timings(intel_crtc
);
5956 i9xx_set_pipeconf(intel_crtc
);
5958 intel_crtc
->active
= true;
5961 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5963 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5964 if (encoder
->pre_enable
)
5965 encoder
->pre_enable(encoder
);
5967 i9xx_enable_pll(intel_crtc
);
5969 i9xx_pfit_enable(intel_crtc
);
5971 intel_crtc_load_lut(crtc
);
5973 intel_update_watermarks(crtc
);
5974 intel_enable_pipe(intel_crtc
);
5976 assert_vblank_disabled(crtc
);
5977 drm_crtc_vblank_on(crtc
);
5979 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5980 encoder
->enable(encoder
);
5983 static void i9xx_pfit_disable(struct intel_crtc
*crtc
)
5985 struct drm_device
*dev
= crtc
->base
.dev
;
5986 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5988 if (!crtc
->config
->gmch_pfit
.control
)
5991 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
5993 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5994 I915_READ(PFIT_CONTROL
));
5995 I915_WRITE(PFIT_CONTROL
, 0);
5998 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
6000 struct drm_device
*dev
= crtc
->dev
;
6001 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6002 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6003 struct intel_encoder
*encoder
;
6004 int pipe
= intel_crtc
->pipe
;
6006 if (!intel_crtc
->active
)
6010 * On gen2 planes are double buffered but the pipe isn't, so we must
6011 * wait for planes to fully turn off before disabling the pipe.
6012 * We also need to wait on all gmch platforms because of the
6013 * self-refresh mode constraint explained above.
6015 intel_wait_for_vblank(dev
, pipe
);
6017 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6018 encoder
->disable(encoder
);
6020 drm_crtc_vblank_off(crtc
);
6021 assert_vblank_disabled(crtc
);
6023 intel_disable_pipe(intel_crtc
);
6025 i9xx_pfit_disable(intel_crtc
);
6027 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6028 if (encoder
->post_disable
)
6029 encoder
->post_disable(encoder
);
6031 if (!intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
)) {
6032 if (IS_CHERRYVIEW(dev
))
6033 chv_disable_pll(dev_priv
, pipe
);
6034 else if (IS_VALLEYVIEW(dev
))
6035 vlv_disable_pll(dev_priv
, pipe
);
6037 i9xx_disable_pll(intel_crtc
);
6041 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
6043 intel_crtc
->active
= false;
6044 intel_update_watermarks(crtc
);
6046 mutex_lock(&dev
->struct_mutex
);
6047 intel_fbc_update(dev
);
6048 mutex_unlock(&dev
->struct_mutex
);
6051 static void i9xx_crtc_off(struct drm_crtc
*crtc
)
6055 /* Master function to enable/disable CRTC and corresponding power wells */
6056 void intel_crtc_control(struct drm_crtc
*crtc
, bool enable
)
6058 struct drm_device
*dev
= crtc
->dev
;
6059 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6060 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6061 enum intel_display_power_domain domain
;
6062 unsigned long domains
;
6065 if (!intel_crtc
->active
) {
6066 domains
= get_crtc_power_domains(crtc
);
6067 for_each_power_domain(domain
, domains
)
6068 intel_display_power_get(dev_priv
, domain
);
6069 intel_crtc
->enabled_power_domains
= domains
;
6071 dev_priv
->display
.crtc_enable(crtc
);
6072 intel_crtc_enable_planes(crtc
);
6075 if (intel_crtc
->active
) {
6076 intel_crtc_disable_planes(crtc
);
6077 dev_priv
->display
.crtc_disable(crtc
);
6079 domains
= intel_crtc
->enabled_power_domains
;
6080 for_each_power_domain(domain
, domains
)
6081 intel_display_power_put(dev_priv
, domain
);
6082 intel_crtc
->enabled_power_domains
= 0;
6088 * Sets the power management mode of the pipe and plane.
6090 void intel_crtc_update_dpms(struct drm_crtc
*crtc
)
6092 struct drm_device
*dev
= crtc
->dev
;
6093 struct intel_encoder
*intel_encoder
;
6094 bool enable
= false;
6096 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
6097 enable
|= intel_encoder
->connectors_active
;
6099 intel_crtc_control(crtc
, enable
);
6101 crtc
->state
->active
= enable
;
6104 static void intel_crtc_disable(struct drm_crtc
*crtc
)
6106 struct drm_device
*dev
= crtc
->dev
;
6107 struct drm_connector
*connector
;
6108 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6110 /* crtc should still be enabled when we disable it. */
6111 WARN_ON(!crtc
->state
->enable
);
6113 intel_crtc_disable_planes(crtc
);
6114 dev_priv
->display
.crtc_disable(crtc
);
6115 dev_priv
->display
.off(crtc
);
6117 drm_plane_helper_disable(crtc
->primary
);
6119 /* Update computed state. */
6120 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
6121 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
6124 if (connector
->encoder
->crtc
!= crtc
)
6127 connector
->dpms
= DRM_MODE_DPMS_OFF
;
6128 to_intel_encoder(connector
->encoder
)->connectors_active
= false;
6132 void intel_encoder_destroy(struct drm_encoder
*encoder
)
6134 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
6136 drm_encoder_cleanup(encoder
);
6137 kfree(intel_encoder
);
6140 /* Simple dpms helper for encoders with just one connector, no cloning and only
6141 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6142 * state of the entire output pipe. */
6143 static void intel_encoder_dpms(struct intel_encoder
*encoder
, int mode
)
6145 if (mode
== DRM_MODE_DPMS_ON
) {
6146 encoder
->connectors_active
= true;
6148 intel_crtc_update_dpms(encoder
->base
.crtc
);
6150 encoder
->connectors_active
= false;
6152 intel_crtc_update_dpms(encoder
->base
.crtc
);
6156 /* Cross check the actual hw state with our own modeset state tracking (and it's
6157 * internal consistency). */
6158 static void intel_connector_check_state(struct intel_connector
*connector
)
6160 if (connector
->get_hw_state(connector
)) {
6161 struct intel_encoder
*encoder
= connector
->encoder
;
6162 struct drm_crtc
*crtc
;
6163 bool encoder_enabled
;
6166 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6167 connector
->base
.base
.id
,
6168 connector
->base
.name
);
6170 /* there is no real hw state for MST connectors */
6171 if (connector
->mst_port
)
6174 I915_STATE_WARN(connector
->base
.dpms
== DRM_MODE_DPMS_OFF
,
6175 "wrong connector dpms state\n");
6176 I915_STATE_WARN(connector
->base
.encoder
!= &encoder
->base
,
6177 "active connector not linked to encoder\n");
6180 I915_STATE_WARN(!encoder
->connectors_active
,
6181 "encoder->connectors_active not set\n");
6183 encoder_enabled
= encoder
->get_hw_state(encoder
, &pipe
);
6184 I915_STATE_WARN(!encoder_enabled
, "encoder not enabled\n");
6185 if (I915_STATE_WARN_ON(!encoder
->base
.crtc
))
6188 crtc
= encoder
->base
.crtc
;
6190 I915_STATE_WARN(!crtc
->state
->enable
,
6191 "crtc not enabled\n");
6192 I915_STATE_WARN(!to_intel_crtc(crtc
)->active
, "crtc not active\n");
6193 I915_STATE_WARN(pipe
!= to_intel_crtc(crtc
)->pipe
,
6194 "encoder active on the wrong pipe\n");
6199 int intel_connector_init(struct intel_connector
*connector
)
6201 struct drm_connector_state
*connector_state
;
6203 connector_state
= kzalloc(sizeof *connector_state
, GFP_KERNEL
);
6204 if (!connector_state
)
6207 connector
->base
.state
= connector_state
;
6211 struct intel_connector
*intel_connector_alloc(void)
6213 struct intel_connector
*connector
;
6215 connector
= kzalloc(sizeof *connector
, GFP_KERNEL
);
6219 if (intel_connector_init(connector
) < 0) {
6227 /* Even simpler default implementation, if there's really no special case to
6229 void intel_connector_dpms(struct drm_connector
*connector
, int mode
)
6231 /* All the simple cases only support two dpms states. */
6232 if (mode
!= DRM_MODE_DPMS_ON
)
6233 mode
= DRM_MODE_DPMS_OFF
;
6235 if (mode
== connector
->dpms
)
6238 connector
->dpms
= mode
;
6240 /* Only need to change hw state when actually enabled */
6241 if (connector
->encoder
)
6242 intel_encoder_dpms(to_intel_encoder(connector
->encoder
), mode
);
6244 intel_modeset_check_state(connector
->dev
);
6247 /* Simple connector->get_hw_state implementation for encoders that support only
6248 * one connector and no cloning and hence the encoder state determines the state
6249 * of the connector. */
6250 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
6253 struct intel_encoder
*encoder
= connector
->encoder
;
6255 return encoder
->get_hw_state(encoder
, &pipe
);
6258 static int pipe_required_fdi_lanes(struct intel_crtc_state
*crtc_state
)
6260 if (crtc_state
->base
.enable
&& crtc_state
->has_pch_encoder
)
6261 return crtc_state
->fdi_lanes
;
6266 static int ironlake_check_fdi_lanes(struct drm_device
*dev
, enum pipe pipe
,
6267 struct intel_crtc_state
*pipe_config
)
6269 struct drm_atomic_state
*state
= pipe_config
->base
.state
;
6270 struct intel_crtc
*other_crtc
;
6271 struct intel_crtc_state
*other_crtc_state
;
6273 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6274 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6275 if (pipe_config
->fdi_lanes
> 4) {
6276 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6277 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6281 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
6282 if (pipe_config
->fdi_lanes
> 2) {
6283 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6284 pipe_config
->fdi_lanes
);
6291 if (INTEL_INFO(dev
)->num_pipes
== 2)
6294 /* Ivybridge 3 pipe is really complicated */
6299 if (pipe_config
->fdi_lanes
<= 2)
6302 other_crtc
= to_intel_crtc(intel_get_crtc_for_pipe(dev
, PIPE_C
));
6304 intel_atomic_get_crtc_state(state
, other_crtc
);
6305 if (IS_ERR(other_crtc_state
))
6306 return PTR_ERR(other_crtc_state
);
6308 if (pipe_required_fdi_lanes(other_crtc_state
) > 0) {
6309 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6310 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6315 if (pipe_config
->fdi_lanes
> 2) {
6316 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6317 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6321 other_crtc
= to_intel_crtc(intel_get_crtc_for_pipe(dev
, PIPE_B
));
6323 intel_atomic_get_crtc_state(state
, other_crtc
);
6324 if (IS_ERR(other_crtc_state
))
6325 return PTR_ERR(other_crtc_state
);
6327 if (pipe_required_fdi_lanes(other_crtc_state
) > 2) {
6328 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6338 static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc
,
6339 struct intel_crtc_state
*pipe_config
)
6341 struct drm_device
*dev
= intel_crtc
->base
.dev
;
6342 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
6343 int lane
, link_bw
, fdi_dotclock
, ret
;
6344 bool needs_recompute
= false;
6347 /* FDI is a binary signal running at ~2.7GHz, encoding
6348 * each output octet as 10 bits. The actual frequency
6349 * is stored as a divider into a 100MHz clock, and the
6350 * mode pixel clock is stored in units of 1KHz.
6351 * Hence the bw of each lane in terms of the mode signal
6354 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
6356 fdi_dotclock
= adjusted_mode
->crtc_clock
;
6358 lane
= ironlake_get_lanes_required(fdi_dotclock
, link_bw
,
6359 pipe_config
->pipe_bpp
);
6361 pipe_config
->fdi_lanes
= lane
;
6363 intel_link_compute_m_n(pipe_config
->pipe_bpp
, lane
, fdi_dotclock
,
6364 link_bw
, &pipe_config
->fdi_m_n
);
6366 ret
= ironlake_check_fdi_lanes(intel_crtc
->base
.dev
,
6367 intel_crtc
->pipe
, pipe_config
);
6368 if (ret
== -EINVAL
&& pipe_config
->pipe_bpp
> 6*3) {
6369 pipe_config
->pipe_bpp
-= 2*3;
6370 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6371 pipe_config
->pipe_bpp
);
6372 needs_recompute
= true;
6373 pipe_config
->bw_constrained
= true;
6378 if (needs_recompute
)
6384 static void hsw_compute_ips_config(struct intel_crtc
*crtc
,
6385 struct intel_crtc_state
*pipe_config
)
6387 pipe_config
->ips_enabled
= i915
.enable_ips
&&
6388 hsw_crtc_supports_ips(crtc
) &&
6389 pipe_config
->pipe_bpp
<= 24;
6392 static int intel_crtc_compute_config(struct intel_crtc
*crtc
,
6393 struct intel_crtc_state
*pipe_config
)
6395 struct drm_device
*dev
= crtc
->base
.dev
;
6396 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6397 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
6400 /* FIXME should check pixel clock limits on all platforms */
6401 if (INTEL_INFO(dev
)->gen
< 4) {
6403 dev_priv
->display
.get_display_clock_speed(dev
);
6406 * Enable pixel doubling when the dot clock
6407 * is > 90% of the (display) core speed.
6409 * GDG double wide on either pipe,
6410 * otherwise pipe A only.
6412 if ((crtc
->pipe
== PIPE_A
|| IS_I915G(dev
)) &&
6413 adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10) {
6415 pipe_config
->double_wide
= true;
6418 if (adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10)
6423 * Pipe horizontal size must be even in:
6425 * - LVDS dual channel mode
6426 * - Double wide pipe
6428 if ((intel_pipe_will_have_type(pipe_config
, INTEL_OUTPUT_LVDS
) &&
6429 intel_is_dual_link_lvds(dev
)) || pipe_config
->double_wide
)
6430 pipe_config
->pipe_src_w
&= ~1;
6432 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6433 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6435 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
6436 adjusted_mode
->hsync_start
== adjusted_mode
->hdisplay
)
6440 hsw_compute_ips_config(crtc
, pipe_config
);
6442 if (pipe_config
->has_pch_encoder
)
6443 return ironlake_fdi_compute_config(crtc
, pipe_config
);
6445 /* FIXME: remove below call once atomic mode set is place and all crtc
6446 * related checks called from atomic_crtc_check function */
6448 DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n",
6449 crtc
, pipe_config
->base
.state
);
6450 ret
= intel_atomic_setup_scalers(dev
, crtc
, pipe_config
);
6455 static int skylake_get_display_clock_speed(struct drm_device
*dev
)
6457 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6458 uint32_t lcpll1
= I915_READ(LCPLL1_CTL
);
6459 uint32_t cdctl
= I915_READ(CDCLK_CTL
);
6462 if (!(lcpll1
& LCPLL_PLL_ENABLE
)) {
6463 WARN(1, "LCPLL1 not enabled\n");
6464 return 24000; /* 24MHz is the cd freq with NSSC ref */
6467 if ((cdctl
& CDCLK_FREQ_SEL_MASK
) == CDCLK_FREQ_540
)
6470 linkrate
= (I915_READ(DPLL_CTRL1
) &
6471 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0
)) >> 1;
6473 if (linkrate
== DPLL_CTRL1_LINK_RATE_2160
||
6474 linkrate
== DPLL_CTRL1_LINK_RATE_1080
) {
6476 switch (cdctl
& CDCLK_FREQ_SEL_MASK
) {
6477 case CDCLK_FREQ_450_432
:
6479 case CDCLK_FREQ_337_308
:
6481 case CDCLK_FREQ_675_617
:
6484 WARN(1, "Unknown cd freq selection\n");
6488 switch (cdctl
& CDCLK_FREQ_SEL_MASK
) {
6489 case CDCLK_FREQ_450_432
:
6491 case CDCLK_FREQ_337_308
:
6493 case CDCLK_FREQ_675_617
:
6496 WARN(1, "Unknown cd freq selection\n");
6500 /* error case, do as if DPLL0 isn't enabled */
6504 static int broadwell_get_display_clock_speed(struct drm_device
*dev
)
6506 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6507 uint32_t lcpll
= I915_READ(LCPLL_CTL
);
6508 uint32_t freq
= lcpll
& LCPLL_CLK_FREQ_MASK
;
6510 if (lcpll
& LCPLL_CD_SOURCE_FCLK
)
6512 else if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
6514 else if (freq
== LCPLL_CLK_FREQ_450
)
6516 else if (freq
== LCPLL_CLK_FREQ_54O_BDW
)
6518 else if (freq
== LCPLL_CLK_FREQ_337_5_BDW
)
6524 static int haswell_get_display_clock_speed(struct drm_device
*dev
)
6526 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6527 uint32_t lcpll
= I915_READ(LCPLL_CTL
);
6528 uint32_t freq
= lcpll
& LCPLL_CLK_FREQ_MASK
;
6530 if (lcpll
& LCPLL_CD_SOURCE_FCLK
)
6532 else if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
6534 else if (freq
== LCPLL_CLK_FREQ_450
)
6536 else if (IS_HSW_ULT(dev
))
6542 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
6544 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6548 if (dev_priv
->hpll_freq
== 0)
6549 dev_priv
->hpll_freq
= valleyview_get_vco(dev_priv
);
6551 mutex_lock(&dev_priv
->dpio_lock
);
6552 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
6553 mutex_unlock(&dev_priv
->dpio_lock
);
6555 divider
= val
& DISPLAY_FREQUENCY_VALUES
;
6557 WARN((val
& DISPLAY_FREQUENCY_STATUS
) !=
6558 (divider
<< DISPLAY_FREQUENCY_STATUS_SHIFT
),
6559 "cdclk change in progress\n");
6561 return DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, divider
+ 1);
6564 static int ilk_get_display_clock_speed(struct drm_device
*dev
)
6569 static int i945_get_display_clock_speed(struct drm_device
*dev
)
6574 static int i915_get_display_clock_speed(struct drm_device
*dev
)
6579 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
6584 static int pnv_get_display_clock_speed(struct drm_device
*dev
)
6588 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
6590 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
6591 case GC_DISPLAY_CLOCK_267_MHZ_PNV
:
6593 case GC_DISPLAY_CLOCK_333_MHZ_PNV
:
6595 case GC_DISPLAY_CLOCK_444_MHZ_PNV
:
6597 case GC_DISPLAY_CLOCK_200_MHZ_PNV
:
6600 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc
);
6601 case GC_DISPLAY_CLOCK_133_MHZ_PNV
:
6603 case GC_DISPLAY_CLOCK_167_MHZ_PNV
:
6608 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
6612 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
6614 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
6617 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
6618 case GC_DISPLAY_CLOCK_333_MHZ
:
6621 case GC_DISPLAY_CLOCK_190_200_MHZ
:
6627 static int i865_get_display_clock_speed(struct drm_device
*dev
)
6632 static int i855_get_display_clock_speed(struct drm_device
*dev
)
6635 /* Assume that the hardware is in the high speed state. This
6636 * should be the default.
6638 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
6639 case GC_CLOCK_133_200
:
6640 case GC_CLOCK_100_200
:
6642 case GC_CLOCK_166_250
:
6644 case GC_CLOCK_100_133
:
6648 /* Shouldn't happen */
6652 static int i830_get_display_clock_speed(struct drm_device
*dev
)
6658 intel_reduce_m_n_ratio(uint32_t *num
, uint32_t *den
)
6660 while (*num
> DATA_LINK_M_N_MASK
||
6661 *den
> DATA_LINK_M_N_MASK
) {
6667 static void compute_m_n(unsigned int m
, unsigned int n
,
6668 uint32_t *ret_m
, uint32_t *ret_n
)
6670 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
6671 *ret_m
= div_u64((uint64_t) m
* *ret_n
, n
);
6672 intel_reduce_m_n_ratio(ret_m
, ret_n
);
6676 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
6677 int pixel_clock
, int link_clock
,
6678 struct intel_link_m_n
*m_n
)
6682 compute_m_n(bits_per_pixel
* pixel_clock
,
6683 link_clock
* nlanes
* 8,
6684 &m_n
->gmch_m
, &m_n
->gmch_n
);
6686 compute_m_n(pixel_clock
, link_clock
,
6687 &m_n
->link_m
, &m_n
->link_n
);
6690 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
6692 if (i915
.panel_use_ssc
>= 0)
6693 return i915
.panel_use_ssc
!= 0;
6694 return dev_priv
->vbt
.lvds_use_ssc
6695 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
6698 static int i9xx_get_refclk(const struct intel_crtc_state
*crtc_state
,
6701 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
6702 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6705 WARN_ON(!crtc_state
->base
.state
);
6707 if (IS_VALLEYVIEW(dev
) || IS_BROXTON(dev
)) {
6709 } else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
6710 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
6711 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
6712 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
6713 } else if (!IS_GEN2(dev
)) {
6722 static uint32_t pnv_dpll_compute_fp(struct dpll
*dpll
)
6724 return (1 << dpll
->n
) << 16 | dpll
->m2
;
6727 static uint32_t i9xx_dpll_compute_fp(struct dpll
*dpll
)
6729 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
6732 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
6733 struct intel_crtc_state
*crtc_state
,
6734 intel_clock_t
*reduced_clock
)
6736 struct drm_device
*dev
= crtc
->base
.dev
;
6739 if (IS_PINEVIEW(dev
)) {
6740 fp
= pnv_dpll_compute_fp(&crtc_state
->dpll
);
6742 fp2
= pnv_dpll_compute_fp(reduced_clock
);
6744 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
6746 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
6749 crtc_state
->dpll_hw_state
.fp0
= fp
;
6751 crtc
->lowfreq_avail
= false;
6752 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
6754 crtc_state
->dpll_hw_state
.fp1
= fp2
;
6755 crtc
->lowfreq_avail
= true;
6757 crtc_state
->dpll_hw_state
.fp1
= fp
;
6761 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
, enum pipe
6767 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6768 * and set it to a reasonable value instead.
6770 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
6771 reg_val
&= 0xffffff00;
6772 reg_val
|= 0x00000030;
6773 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
6775 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
6776 reg_val
&= 0x8cffffff;
6777 reg_val
= 0x8c000000;
6778 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
6780 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
6781 reg_val
&= 0xffffff00;
6782 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
6784 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
6785 reg_val
&= 0x00ffffff;
6786 reg_val
|= 0xb0000000;
6787 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
6790 static void intel_pch_transcoder_set_m_n(struct intel_crtc
*crtc
,
6791 struct intel_link_m_n
*m_n
)
6793 struct drm_device
*dev
= crtc
->base
.dev
;
6794 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6795 int pipe
= crtc
->pipe
;
6797 I915_WRITE(PCH_TRANS_DATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
6798 I915_WRITE(PCH_TRANS_DATA_N1(pipe
), m_n
->gmch_n
);
6799 I915_WRITE(PCH_TRANS_LINK_M1(pipe
), m_n
->link_m
);
6800 I915_WRITE(PCH_TRANS_LINK_N1(pipe
), m_n
->link_n
);
6803 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
6804 struct intel_link_m_n
*m_n
,
6805 struct intel_link_m_n
*m2_n2
)
6807 struct drm_device
*dev
= crtc
->base
.dev
;
6808 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6809 int pipe
= crtc
->pipe
;
6810 enum transcoder transcoder
= crtc
->config
->cpu_transcoder
;
6812 if (INTEL_INFO(dev
)->gen
>= 5) {
6813 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
6814 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
6815 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
6816 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
6817 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6818 * for gen < 8) and if DRRS is supported (to make sure the
6819 * registers are not unnecessarily accessed).
6821 if (m2_n2
&& (IS_CHERRYVIEW(dev
) || INTEL_INFO(dev
)->gen
< 8) &&
6822 crtc
->config
->has_drrs
) {
6823 I915_WRITE(PIPE_DATA_M2(transcoder
),
6824 TU_SIZE(m2_n2
->tu
) | m2_n2
->gmch_m
);
6825 I915_WRITE(PIPE_DATA_N2(transcoder
), m2_n2
->gmch_n
);
6826 I915_WRITE(PIPE_LINK_M2(transcoder
), m2_n2
->link_m
);
6827 I915_WRITE(PIPE_LINK_N2(transcoder
), m2_n2
->link_n
);
6830 I915_WRITE(PIPE_DATA_M_G4X(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
6831 I915_WRITE(PIPE_DATA_N_G4X(pipe
), m_n
->gmch_n
);
6832 I915_WRITE(PIPE_LINK_M_G4X(pipe
), m_n
->link_m
);
6833 I915_WRITE(PIPE_LINK_N_G4X(pipe
), m_n
->link_n
);
6837 void intel_dp_set_m_n(struct intel_crtc
*crtc
, enum link_m_n_set m_n
)
6839 struct intel_link_m_n
*dp_m_n
, *dp_m2_n2
= NULL
;
6842 dp_m_n
= &crtc
->config
->dp_m_n
;
6843 dp_m2_n2
= &crtc
->config
->dp_m2_n2
;
6844 } else if (m_n
== M2_N2
) {
6847 * M2_N2 registers are not supported. Hence m2_n2 divider value
6848 * needs to be programmed into M1_N1.
6850 dp_m_n
= &crtc
->config
->dp_m2_n2
;
6852 DRM_ERROR("Unsupported divider value\n");
6856 if (crtc
->config
->has_pch_encoder
)
6857 intel_pch_transcoder_set_m_n(crtc
, &crtc
->config
->dp_m_n
);
6859 intel_cpu_transcoder_set_m_n(crtc
, dp_m_n
, dp_m2_n2
);
6862 static void vlv_update_pll(struct intel_crtc
*crtc
,
6863 struct intel_crtc_state
*pipe_config
)
6868 * Enable DPIO clock input. We should never disable the reference
6869 * clock for pipe B, since VGA hotplug / manual detection depends
6872 dpll
= DPLL_EXT_BUFFER_ENABLE_VLV
| DPLL_REFA_CLK_ENABLE_VLV
|
6873 DPLL_VGA_MODE_DIS
| DPLL_INTEGRATED_CLOCK_VLV
;
6874 /* We should never disable this, set it here for state tracking */
6875 if (crtc
->pipe
== PIPE_B
)
6876 dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
6877 dpll
|= DPLL_VCO_ENABLE
;
6878 pipe_config
->dpll_hw_state
.dpll
= dpll
;
6880 dpll_md
= (pipe_config
->pixel_multiplier
- 1)
6881 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
6882 pipe_config
->dpll_hw_state
.dpll_md
= dpll_md
;
6885 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
6886 const struct intel_crtc_state
*pipe_config
)
6888 struct drm_device
*dev
= crtc
->base
.dev
;
6889 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6890 int pipe
= crtc
->pipe
;
6892 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
6893 u32 coreclk
, reg_val
;
6895 mutex_lock(&dev_priv
->dpio_lock
);
6897 bestn
= pipe_config
->dpll
.n
;
6898 bestm1
= pipe_config
->dpll
.m1
;
6899 bestm2
= pipe_config
->dpll
.m2
;
6900 bestp1
= pipe_config
->dpll
.p1
;
6901 bestp2
= pipe_config
->dpll
.p2
;
6903 /* See eDP HDMI DPIO driver vbios notes doc */
6905 /* PLL B needs special handling */
6907 vlv_pllb_recal_opamp(dev_priv
, pipe
);
6909 /* Set up Tx target for periodic Rcomp update */
6910 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9_BCAST
, 0x0100000f);
6912 /* Disable target IRef on PLL */
6913 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW8(pipe
));
6914 reg_val
&= 0x00ffffff;
6915 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW8(pipe
), reg_val
);
6917 /* Disable fast lock */
6918 vlv_dpio_write(dev_priv
, pipe
, VLV_CMN_DW0
, 0x610);
6920 /* Set idtafcrecal before PLL is enabled */
6921 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
6922 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
6923 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
6924 mdiv
|= (1 << DPIO_K_SHIFT
);
6927 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6928 * but we don't support that).
6929 * Note: don't use the DAC post divider as it seems unstable.
6931 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
6932 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
6934 mdiv
|= DPIO_ENABLE_CALIBRATION
;
6935 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
6937 /* Set HBR and RBR LPF coefficients */
6938 if (pipe_config
->port_clock
== 162000 ||
6939 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
) ||
6940 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
))
6941 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
6944 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
6947 if (pipe_config
->has_dp_encoder
) {
6948 /* Use SSC source */
6950 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
6953 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
6955 } else { /* HDMI or VGA */
6956 /* Use bend source */
6958 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
6961 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
6965 coreclk
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW7(pipe
));
6966 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
6967 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
6968 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))
6969 coreclk
|= 0x01000000;
6970 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW7(pipe
), coreclk
);
6972 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW11(pipe
), 0x87871000);
6973 mutex_unlock(&dev_priv
->dpio_lock
);
6976 static void chv_update_pll(struct intel_crtc
*crtc
,
6977 struct intel_crtc_state
*pipe_config
)
6979 pipe_config
->dpll_hw_state
.dpll
= DPLL_SSC_REF_CLOCK_CHV
|
6980 DPLL_REFA_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
|
6982 if (crtc
->pipe
!= PIPE_A
)
6983 pipe_config
->dpll_hw_state
.dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
6985 pipe_config
->dpll_hw_state
.dpll_md
=
6986 (pipe_config
->pixel_multiplier
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
6989 static void chv_prepare_pll(struct intel_crtc
*crtc
,
6990 const struct intel_crtc_state
*pipe_config
)
6992 struct drm_device
*dev
= crtc
->base
.dev
;
6993 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6994 int pipe
= crtc
->pipe
;
6995 int dpll_reg
= DPLL(crtc
->pipe
);
6996 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
6997 u32 loopfilter
, tribuf_calcntr
;
6998 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
, bestm2_frac
;
7002 bestn
= pipe_config
->dpll
.n
;
7003 bestm2_frac
= pipe_config
->dpll
.m2
& 0x3fffff;
7004 bestm1
= pipe_config
->dpll
.m1
;
7005 bestm2
= pipe_config
->dpll
.m2
>> 22;
7006 bestp1
= pipe_config
->dpll
.p1
;
7007 bestp2
= pipe_config
->dpll
.p2
;
7008 vco
= pipe_config
->dpll
.vco
;
7013 * Enable Refclk and SSC
7015 I915_WRITE(dpll_reg
,
7016 pipe_config
->dpll_hw_state
.dpll
& ~DPLL_VCO_ENABLE
);
7018 mutex_lock(&dev_priv
->dpio_lock
);
7020 /* p1 and p2 divider */
7021 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW13(port
),
7022 5 << DPIO_CHV_S1_DIV_SHIFT
|
7023 bestp1
<< DPIO_CHV_P1_DIV_SHIFT
|
7024 bestp2
<< DPIO_CHV_P2_DIV_SHIFT
|
7025 1 << DPIO_CHV_K_DIV_SHIFT
);
7027 /* Feedback post-divider - m2 */
7028 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW0(port
), bestm2
);
7030 /* Feedback refclk divider - n and m1 */
7031 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW1(port
),
7032 DPIO_CHV_M1_DIV_BY_2
|
7033 1 << DPIO_CHV_N_DIV_SHIFT
);
7035 /* M2 fraction division */
7037 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW2(port
), bestm2_frac
);
7039 /* M2 fraction division enable */
7040 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW3(port
));
7041 dpio_val
&= ~(DPIO_CHV_FEEDFWD_GAIN_MASK
| DPIO_CHV_FRAC_DIV_EN
);
7042 dpio_val
|= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT
);
7044 dpio_val
|= DPIO_CHV_FRAC_DIV_EN
;
7045 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW3(port
), dpio_val
);
7047 /* Program digital lock detect threshold */
7048 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW9(port
));
7049 dpio_val
&= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK
|
7050 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE
);
7051 dpio_val
|= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT
);
7053 dpio_val
|= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE
;
7054 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW9(port
), dpio_val
);
7057 if (vco
== 5400000) {
7058 loopfilter
|= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT
);
7059 loopfilter
|= (0x8 << DPIO_CHV_INT_COEFF_SHIFT
);
7060 loopfilter
|= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7061 tribuf_calcntr
= 0x9;
7062 } else if (vco
<= 6200000) {
7063 loopfilter
|= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT
);
7064 loopfilter
|= (0xB << DPIO_CHV_INT_COEFF_SHIFT
);
7065 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7066 tribuf_calcntr
= 0x9;
7067 } else if (vco
<= 6480000) {
7068 loopfilter
|= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT
);
7069 loopfilter
|= (0x9 << DPIO_CHV_INT_COEFF_SHIFT
);
7070 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7071 tribuf_calcntr
= 0x8;
7073 /* Not supported. Apply the same limits as in the max case */
7074 loopfilter
|= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT
);
7075 loopfilter
|= (0x9 << DPIO_CHV_INT_COEFF_SHIFT
);
7076 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7079 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW6(port
), loopfilter
);
7081 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW8(port
));
7082 dpio_val
&= ~DPIO_CHV_TDC_TARGET_CNT_MASK
;
7083 dpio_val
|= (tribuf_calcntr
<< DPIO_CHV_TDC_TARGET_CNT_SHIFT
);
7084 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW8(port
), dpio_val
);
7087 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
),
7088 vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
)) |
7091 mutex_unlock(&dev_priv
->dpio_lock
);
7095 * vlv_force_pll_on - forcibly enable just the PLL
7096 * @dev_priv: i915 private structure
7097 * @pipe: pipe PLL to enable
7098 * @dpll: PLL configuration
7100 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7101 * in cases where we need the PLL enabled even when @pipe is not going to
7104 void vlv_force_pll_on(struct drm_device
*dev
, enum pipe pipe
,
7105 const struct dpll
*dpll
)
7107 struct intel_crtc
*crtc
=
7108 to_intel_crtc(intel_get_crtc_for_pipe(dev
, pipe
));
7109 struct intel_crtc_state pipe_config
= {
7110 .base
.crtc
= &crtc
->base
,
7111 .pixel_multiplier
= 1,
7115 if (IS_CHERRYVIEW(dev
)) {
7116 chv_update_pll(crtc
, &pipe_config
);
7117 chv_prepare_pll(crtc
, &pipe_config
);
7118 chv_enable_pll(crtc
, &pipe_config
);
7120 vlv_update_pll(crtc
, &pipe_config
);
7121 vlv_prepare_pll(crtc
, &pipe_config
);
7122 vlv_enable_pll(crtc
, &pipe_config
);
7127 * vlv_force_pll_off - forcibly disable just the PLL
7128 * @dev_priv: i915 private structure
7129 * @pipe: pipe PLL to disable
7131 * Disable the PLL for @pipe. To be used in cases where we need
7132 * the PLL enabled even when @pipe is not going to be enabled.
7134 void vlv_force_pll_off(struct drm_device
*dev
, enum pipe pipe
)
7136 if (IS_CHERRYVIEW(dev
))
7137 chv_disable_pll(to_i915(dev
), pipe
);
7139 vlv_disable_pll(to_i915(dev
), pipe
);
7142 static void i9xx_update_pll(struct intel_crtc
*crtc
,
7143 struct intel_crtc_state
*crtc_state
,
7144 intel_clock_t
*reduced_clock
,
7147 struct drm_device
*dev
= crtc
->base
.dev
;
7148 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7151 struct dpll
*clock
= &crtc_state
->dpll
;
7153 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
7155 is_sdvo
= intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_SDVO
) ||
7156 intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_HDMI
);
7158 dpll
= DPLL_VGA_MODE_DIS
;
7160 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
))
7161 dpll
|= DPLLB_MODE_LVDS
;
7163 dpll
|= DPLLB_MODE_DAC_SERIAL
;
7165 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
7166 dpll
|= (crtc_state
->pixel_multiplier
- 1)
7167 << SDVO_MULTIPLIER_SHIFT_HIRES
;
7171 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7173 if (crtc_state
->has_dp_encoder
)
7174 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7176 /* compute bitmask from p1 value */
7177 if (IS_PINEVIEW(dev
))
7178 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
7180 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7181 if (IS_G4X(dev
) && reduced_clock
)
7182 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
7184 switch (clock
->p2
) {
7186 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
7189 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
7192 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
7195 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
7198 if (INTEL_INFO(dev
)->gen
>= 4)
7199 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
7201 if (crtc_state
->sdvo_tv_clock
)
7202 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
7203 else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7204 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
7205 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
7207 dpll
|= PLL_REF_INPUT_DREFCLK
;
7209 dpll
|= DPLL_VCO_ENABLE
;
7210 crtc_state
->dpll_hw_state
.dpll
= dpll
;
7212 if (INTEL_INFO(dev
)->gen
>= 4) {
7213 u32 dpll_md
= (crtc_state
->pixel_multiplier
- 1)
7214 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
7215 crtc_state
->dpll_hw_state
.dpll_md
= dpll_md
;
7219 static void i8xx_update_pll(struct intel_crtc
*crtc
,
7220 struct intel_crtc_state
*crtc_state
,
7221 intel_clock_t
*reduced_clock
,
7224 struct drm_device
*dev
= crtc
->base
.dev
;
7225 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7227 struct dpll
*clock
= &crtc_state
->dpll
;
7229 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
7231 dpll
= DPLL_VGA_MODE_DIS
;
7233 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
7234 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7237 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
7239 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7241 dpll
|= PLL_P2_DIVIDE_BY_4
;
7244 if (!IS_I830(dev
) && intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_DVO
))
7245 dpll
|= DPLL_DVO_2X_MODE
;
7247 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7248 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
7249 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
7251 dpll
|= PLL_REF_INPUT_DREFCLK
;
7253 dpll
|= DPLL_VCO_ENABLE
;
7254 crtc_state
->dpll_hw_state
.dpll
= dpll
;
7257 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
)
7259 struct drm_device
*dev
= intel_crtc
->base
.dev
;
7260 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7261 enum pipe pipe
= intel_crtc
->pipe
;
7262 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
7263 struct drm_display_mode
*adjusted_mode
=
7264 &intel_crtc
->config
->base
.adjusted_mode
;
7265 uint32_t crtc_vtotal
, crtc_vblank_end
;
7268 /* We need to be careful not to changed the adjusted mode, for otherwise
7269 * the hw state checker will get angry at the mismatch. */
7270 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
7271 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
7273 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
7274 /* the chip adds 2 halflines automatically */
7276 crtc_vblank_end
-= 1;
7278 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
7279 vsyncshift
= (adjusted_mode
->crtc_htotal
- 1) / 2;
7281 vsyncshift
= adjusted_mode
->crtc_hsync_start
-
7282 adjusted_mode
->crtc_htotal
/ 2;
7284 vsyncshift
+= adjusted_mode
->crtc_htotal
;
7287 if (INTEL_INFO(dev
)->gen
> 3)
7288 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
7290 I915_WRITE(HTOTAL(cpu_transcoder
),
7291 (adjusted_mode
->crtc_hdisplay
- 1) |
7292 ((adjusted_mode
->crtc_htotal
- 1) << 16));
7293 I915_WRITE(HBLANK(cpu_transcoder
),
7294 (adjusted_mode
->crtc_hblank_start
- 1) |
7295 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
7296 I915_WRITE(HSYNC(cpu_transcoder
),
7297 (adjusted_mode
->crtc_hsync_start
- 1) |
7298 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
7300 I915_WRITE(VTOTAL(cpu_transcoder
),
7301 (adjusted_mode
->crtc_vdisplay
- 1) |
7302 ((crtc_vtotal
- 1) << 16));
7303 I915_WRITE(VBLANK(cpu_transcoder
),
7304 (adjusted_mode
->crtc_vblank_start
- 1) |
7305 ((crtc_vblank_end
- 1) << 16));
7306 I915_WRITE(VSYNC(cpu_transcoder
),
7307 (adjusted_mode
->crtc_vsync_start
- 1) |
7308 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
7310 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7311 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7312 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7314 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
7315 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
7316 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
7318 /* pipesrc controls the size that is scaled from, which should
7319 * always be the user's requested size.
7321 I915_WRITE(PIPESRC(pipe
),
7322 ((intel_crtc
->config
->pipe_src_w
- 1) << 16) |
7323 (intel_crtc
->config
->pipe_src_h
- 1));
7326 static void intel_get_pipe_timings(struct intel_crtc
*crtc
,
7327 struct intel_crtc_state
*pipe_config
)
7329 struct drm_device
*dev
= crtc
->base
.dev
;
7330 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7331 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
7334 tmp
= I915_READ(HTOTAL(cpu_transcoder
));
7335 pipe_config
->base
.adjusted_mode
.crtc_hdisplay
= (tmp
& 0xffff) + 1;
7336 pipe_config
->base
.adjusted_mode
.crtc_htotal
= ((tmp
>> 16) & 0xffff) + 1;
7337 tmp
= I915_READ(HBLANK(cpu_transcoder
));
7338 pipe_config
->base
.adjusted_mode
.crtc_hblank_start
= (tmp
& 0xffff) + 1;
7339 pipe_config
->base
.adjusted_mode
.crtc_hblank_end
= ((tmp
>> 16) & 0xffff) + 1;
7340 tmp
= I915_READ(HSYNC(cpu_transcoder
));
7341 pipe_config
->base
.adjusted_mode
.crtc_hsync_start
= (tmp
& 0xffff) + 1;
7342 pipe_config
->base
.adjusted_mode
.crtc_hsync_end
= ((tmp
>> 16) & 0xffff) + 1;
7344 tmp
= I915_READ(VTOTAL(cpu_transcoder
));
7345 pipe_config
->base
.adjusted_mode
.crtc_vdisplay
= (tmp
& 0xffff) + 1;
7346 pipe_config
->base
.adjusted_mode
.crtc_vtotal
= ((tmp
>> 16) & 0xffff) + 1;
7347 tmp
= I915_READ(VBLANK(cpu_transcoder
));
7348 pipe_config
->base
.adjusted_mode
.crtc_vblank_start
= (tmp
& 0xffff) + 1;
7349 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
= ((tmp
>> 16) & 0xffff) + 1;
7350 tmp
= I915_READ(VSYNC(cpu_transcoder
));
7351 pipe_config
->base
.adjusted_mode
.crtc_vsync_start
= (tmp
& 0xffff) + 1;
7352 pipe_config
->base
.adjusted_mode
.crtc_vsync_end
= ((tmp
>> 16) & 0xffff) + 1;
7354 if (I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_INTERLACE_MASK
) {
7355 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
7356 pipe_config
->base
.adjusted_mode
.crtc_vtotal
+= 1;
7357 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
+= 1;
7360 tmp
= I915_READ(PIPESRC(crtc
->pipe
));
7361 pipe_config
->pipe_src_h
= (tmp
& 0xffff) + 1;
7362 pipe_config
->pipe_src_w
= ((tmp
>> 16) & 0xffff) + 1;
7364 pipe_config
->base
.mode
.vdisplay
= pipe_config
->pipe_src_h
;
7365 pipe_config
->base
.mode
.hdisplay
= pipe_config
->pipe_src_w
;
7368 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
7369 struct intel_crtc_state
*pipe_config
)
7371 mode
->hdisplay
= pipe_config
->base
.adjusted_mode
.crtc_hdisplay
;
7372 mode
->htotal
= pipe_config
->base
.adjusted_mode
.crtc_htotal
;
7373 mode
->hsync_start
= pipe_config
->base
.adjusted_mode
.crtc_hsync_start
;
7374 mode
->hsync_end
= pipe_config
->base
.adjusted_mode
.crtc_hsync_end
;
7376 mode
->vdisplay
= pipe_config
->base
.adjusted_mode
.crtc_vdisplay
;
7377 mode
->vtotal
= pipe_config
->base
.adjusted_mode
.crtc_vtotal
;
7378 mode
->vsync_start
= pipe_config
->base
.adjusted_mode
.crtc_vsync_start
;
7379 mode
->vsync_end
= pipe_config
->base
.adjusted_mode
.crtc_vsync_end
;
7381 mode
->flags
= pipe_config
->base
.adjusted_mode
.flags
;
7383 mode
->clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
7384 mode
->flags
|= pipe_config
->base
.adjusted_mode
.flags
;
7387 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
)
7389 struct drm_device
*dev
= intel_crtc
->base
.dev
;
7390 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7395 if ((intel_crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
7396 (intel_crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
7397 pipeconf
|= I915_READ(PIPECONF(intel_crtc
->pipe
)) & PIPECONF_ENABLE
;
7399 if (intel_crtc
->config
->double_wide
)
7400 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
7402 /* only g4x and later have fancy bpc/dither controls */
7403 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
7404 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7405 if (intel_crtc
->config
->dither
&& intel_crtc
->config
->pipe_bpp
!= 30)
7406 pipeconf
|= PIPECONF_DITHER_EN
|
7407 PIPECONF_DITHER_TYPE_SP
;
7409 switch (intel_crtc
->config
->pipe_bpp
) {
7411 pipeconf
|= PIPECONF_6BPC
;
7414 pipeconf
|= PIPECONF_8BPC
;
7417 pipeconf
|= PIPECONF_10BPC
;
7420 /* Case prevented by intel_choose_pipe_bpp_dither. */
7425 if (HAS_PIPE_CXSR(dev
)) {
7426 if (intel_crtc
->lowfreq_avail
) {
7427 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7428 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
7430 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7434 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
7435 if (INTEL_INFO(dev
)->gen
< 4 ||
7436 intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
7437 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
7439 pipeconf
|= PIPECONF_INTERLACE_W_SYNC_SHIFT
;
7441 pipeconf
|= PIPECONF_PROGRESSIVE
;
7443 if (IS_VALLEYVIEW(dev
) && intel_crtc
->config
->limited_color_range
)
7444 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
7446 I915_WRITE(PIPECONF(intel_crtc
->pipe
), pipeconf
);
7447 POSTING_READ(PIPECONF(intel_crtc
->pipe
));
7450 static int i9xx_crtc_compute_clock(struct intel_crtc
*crtc
,
7451 struct intel_crtc_state
*crtc_state
)
7453 struct drm_device
*dev
= crtc
->base
.dev
;
7454 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7455 int refclk
, num_connectors
= 0;
7456 intel_clock_t clock
, reduced_clock
;
7457 bool ok
, has_reduced_clock
= false;
7458 bool is_lvds
= false, is_dsi
= false;
7459 struct intel_encoder
*encoder
;
7460 const intel_limit_t
*limit
;
7461 struct drm_atomic_state
*state
= crtc_state
->base
.state
;
7462 struct drm_connector
*connector
;
7463 struct drm_connector_state
*connector_state
;
7466 memset(&crtc_state
->dpll_hw_state
, 0,
7467 sizeof(crtc_state
->dpll_hw_state
));
7469 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
7470 if (connector_state
->crtc
!= &crtc
->base
)
7473 encoder
= to_intel_encoder(connector_state
->best_encoder
);
7475 switch (encoder
->type
) {
7476 case INTEL_OUTPUT_LVDS
:
7479 case INTEL_OUTPUT_DSI
:
7492 if (!crtc_state
->clock_set
) {
7493 refclk
= i9xx_get_refclk(crtc_state
, num_connectors
);
7496 * Returns a set of divisors for the desired target clock with
7497 * the given refclk, or FALSE. The returned values represent
7498 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7501 limit
= intel_limit(crtc_state
, refclk
);
7502 ok
= dev_priv
->display
.find_dpll(limit
, crtc_state
,
7503 crtc_state
->port_clock
,
7504 refclk
, NULL
, &clock
);
7506 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7510 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
7512 * Ensure we match the reduced clock's P to the target
7513 * clock. If the clocks don't match, we can't switch
7514 * the display clock by using the FP0/FP1. In such case
7515 * we will disable the LVDS downclock feature.
7518 dev_priv
->display
.find_dpll(limit
, crtc_state
,
7519 dev_priv
->lvds_downclock
,
7523 /* Compat-code for transition, will disappear. */
7524 crtc_state
->dpll
.n
= clock
.n
;
7525 crtc_state
->dpll
.m1
= clock
.m1
;
7526 crtc_state
->dpll
.m2
= clock
.m2
;
7527 crtc_state
->dpll
.p1
= clock
.p1
;
7528 crtc_state
->dpll
.p2
= clock
.p2
;
7532 i8xx_update_pll(crtc
, crtc_state
,
7533 has_reduced_clock
? &reduced_clock
: NULL
,
7535 } else if (IS_CHERRYVIEW(dev
)) {
7536 chv_update_pll(crtc
, crtc_state
);
7537 } else if (IS_VALLEYVIEW(dev
)) {
7538 vlv_update_pll(crtc
, crtc_state
);
7540 i9xx_update_pll(crtc
, crtc_state
,
7541 has_reduced_clock
? &reduced_clock
: NULL
,
7548 static void i9xx_get_pfit_config(struct intel_crtc
*crtc
,
7549 struct intel_crtc_state
*pipe_config
)
7551 struct drm_device
*dev
= crtc
->base
.dev
;
7552 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7555 if (INTEL_INFO(dev
)->gen
<= 3 && (IS_I830(dev
) || !IS_MOBILE(dev
)))
7558 tmp
= I915_READ(PFIT_CONTROL
);
7559 if (!(tmp
& PFIT_ENABLE
))
7562 /* Check whether the pfit is attached to our pipe. */
7563 if (INTEL_INFO(dev
)->gen
< 4) {
7564 if (crtc
->pipe
!= PIPE_B
)
7567 if ((tmp
& PFIT_PIPE_MASK
) != (crtc
->pipe
<< PFIT_PIPE_SHIFT
))
7571 pipe_config
->gmch_pfit
.control
= tmp
;
7572 pipe_config
->gmch_pfit
.pgm_ratios
= I915_READ(PFIT_PGM_RATIOS
);
7573 if (INTEL_INFO(dev
)->gen
< 5)
7574 pipe_config
->gmch_pfit
.lvds_border_bits
=
7575 I915_READ(LVDS
) & LVDS_BORDER_ENABLE
;
7578 static void vlv_crtc_clock_get(struct intel_crtc
*crtc
,
7579 struct intel_crtc_state
*pipe_config
)
7581 struct drm_device
*dev
= crtc
->base
.dev
;
7582 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7583 int pipe
= pipe_config
->cpu_transcoder
;
7584 intel_clock_t clock
;
7586 int refclk
= 100000;
7588 /* In case of MIPI DPLL will not even be used */
7589 if (!(pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
))
7592 mutex_lock(&dev_priv
->dpio_lock
);
7593 mdiv
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW3(pipe
));
7594 mutex_unlock(&dev_priv
->dpio_lock
);
7596 clock
.m1
= (mdiv
>> DPIO_M1DIV_SHIFT
) & 7;
7597 clock
.m2
= mdiv
& DPIO_M2DIV_MASK
;
7598 clock
.n
= (mdiv
>> DPIO_N_SHIFT
) & 0xf;
7599 clock
.p1
= (mdiv
>> DPIO_P1_SHIFT
) & 7;
7600 clock
.p2
= (mdiv
>> DPIO_P2_SHIFT
) & 0x1f;
7602 vlv_clock(refclk
, &clock
);
7604 /* clock.dot is the fast clock */
7605 pipe_config
->port_clock
= clock
.dot
/ 5;
7609 i9xx_get_initial_plane_config(struct intel_crtc
*crtc
,
7610 struct intel_initial_plane_config
*plane_config
)
7612 struct drm_device
*dev
= crtc
->base
.dev
;
7613 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7614 u32 val
, base
, offset
;
7615 int pipe
= crtc
->pipe
, plane
= crtc
->plane
;
7616 int fourcc
, pixel_format
;
7617 unsigned int aligned_height
;
7618 struct drm_framebuffer
*fb
;
7619 struct intel_framebuffer
*intel_fb
;
7621 val
= I915_READ(DSPCNTR(plane
));
7622 if (!(val
& DISPLAY_PLANE_ENABLE
))
7625 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
7627 DRM_DEBUG_KMS("failed to alloc fb\n");
7631 fb
= &intel_fb
->base
;
7633 if (INTEL_INFO(dev
)->gen
>= 4) {
7634 if (val
& DISPPLANE_TILED
) {
7635 plane_config
->tiling
= I915_TILING_X
;
7636 fb
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
7640 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
7641 fourcc
= i9xx_format_to_fourcc(pixel_format
);
7642 fb
->pixel_format
= fourcc
;
7643 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
7645 if (INTEL_INFO(dev
)->gen
>= 4) {
7646 if (plane_config
->tiling
)
7647 offset
= I915_READ(DSPTILEOFF(plane
));
7649 offset
= I915_READ(DSPLINOFF(plane
));
7650 base
= I915_READ(DSPSURF(plane
)) & 0xfffff000;
7652 base
= I915_READ(DSPADDR(plane
));
7654 plane_config
->base
= base
;
7656 val
= I915_READ(PIPESRC(pipe
));
7657 fb
->width
= ((val
>> 16) & 0xfff) + 1;
7658 fb
->height
= ((val
>> 0) & 0xfff) + 1;
7660 val
= I915_READ(DSPSTRIDE(pipe
));
7661 fb
->pitches
[0] = val
& 0xffffffc0;
7663 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
7667 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
7669 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7670 pipe_name(pipe
), plane
, fb
->width
, fb
->height
,
7671 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
7672 plane_config
->size
);
7674 plane_config
->fb
= intel_fb
;
7677 static void chv_crtc_clock_get(struct intel_crtc
*crtc
,
7678 struct intel_crtc_state
*pipe_config
)
7680 struct drm_device
*dev
= crtc
->base
.dev
;
7681 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7682 int pipe
= pipe_config
->cpu_transcoder
;
7683 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
7684 intel_clock_t clock
;
7685 u32 cmn_dw13
, pll_dw0
, pll_dw1
, pll_dw2
;
7686 int refclk
= 100000;
7688 mutex_lock(&dev_priv
->dpio_lock
);
7689 cmn_dw13
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW13(port
));
7690 pll_dw0
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW0(port
));
7691 pll_dw1
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW1(port
));
7692 pll_dw2
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW2(port
));
7693 mutex_unlock(&dev_priv
->dpio_lock
);
7695 clock
.m1
= (pll_dw1
& 0x7) == DPIO_CHV_M1_DIV_BY_2
? 2 : 0;
7696 clock
.m2
= ((pll_dw0
& 0xff) << 22) | (pll_dw2
& 0x3fffff);
7697 clock
.n
= (pll_dw1
>> DPIO_CHV_N_DIV_SHIFT
) & 0xf;
7698 clock
.p1
= (cmn_dw13
>> DPIO_CHV_P1_DIV_SHIFT
) & 0x7;
7699 clock
.p2
= (cmn_dw13
>> DPIO_CHV_P2_DIV_SHIFT
) & 0x1f;
7701 chv_clock(refclk
, &clock
);
7703 /* clock.dot is the fast clock */
7704 pipe_config
->port_clock
= clock
.dot
/ 5;
7707 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
7708 struct intel_crtc_state
*pipe_config
)
7710 struct drm_device
*dev
= crtc
->base
.dev
;
7711 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7714 if (!intel_display_power_is_enabled(dev_priv
,
7715 POWER_DOMAIN_PIPE(crtc
->pipe
)))
7718 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
7719 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
7721 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
7722 if (!(tmp
& PIPECONF_ENABLE
))
7725 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
7726 switch (tmp
& PIPECONF_BPC_MASK
) {
7728 pipe_config
->pipe_bpp
= 18;
7731 pipe_config
->pipe_bpp
= 24;
7733 case PIPECONF_10BPC
:
7734 pipe_config
->pipe_bpp
= 30;
7741 if (IS_VALLEYVIEW(dev
) && (tmp
& PIPECONF_COLOR_RANGE_SELECT
))
7742 pipe_config
->limited_color_range
= true;
7744 if (INTEL_INFO(dev
)->gen
< 4)
7745 pipe_config
->double_wide
= tmp
& PIPECONF_DOUBLE_WIDE
;
7747 intel_get_pipe_timings(crtc
, pipe_config
);
7749 i9xx_get_pfit_config(crtc
, pipe_config
);
7751 if (INTEL_INFO(dev
)->gen
>= 4) {
7752 tmp
= I915_READ(DPLL_MD(crtc
->pipe
));
7753 pipe_config
->pixel_multiplier
=
7754 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
7755 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
7756 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
7757 } else if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
7758 tmp
= I915_READ(DPLL(crtc
->pipe
));
7759 pipe_config
->pixel_multiplier
=
7760 ((tmp
& SDVO_MULTIPLIER_MASK
)
7761 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
7763 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7764 * port and will be fixed up in the encoder->get_config
7766 pipe_config
->pixel_multiplier
= 1;
7768 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(crtc
->pipe
));
7769 if (!IS_VALLEYVIEW(dev
)) {
7771 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7772 * on 830. Filter it out here so that we don't
7773 * report errors due to that.
7776 pipe_config
->dpll_hw_state
.dpll
&= ~DPLL_DVO_2X_MODE
;
7778 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(crtc
->pipe
));
7779 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(crtc
->pipe
));
7781 /* Mask out read-only status bits. */
7782 pipe_config
->dpll_hw_state
.dpll
&= ~(DPLL_LOCK_VLV
|
7783 DPLL_PORTC_READY_MASK
|
7784 DPLL_PORTB_READY_MASK
);
7787 if (IS_CHERRYVIEW(dev
))
7788 chv_crtc_clock_get(crtc
, pipe_config
);
7789 else if (IS_VALLEYVIEW(dev
))
7790 vlv_crtc_clock_get(crtc
, pipe_config
);
7792 i9xx_crtc_clock_get(crtc
, pipe_config
);
7797 static void ironlake_init_pch_refclk(struct drm_device
*dev
)
7799 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7800 struct intel_encoder
*encoder
;
7802 bool has_lvds
= false;
7803 bool has_cpu_edp
= false;
7804 bool has_panel
= false;
7805 bool has_ck505
= false;
7806 bool can_ssc
= false;
7808 /* We need to take the global config into account */
7809 for_each_intel_encoder(dev
, encoder
) {
7810 switch (encoder
->type
) {
7811 case INTEL_OUTPUT_LVDS
:
7815 case INTEL_OUTPUT_EDP
:
7817 if (enc_to_dig_port(&encoder
->base
)->port
== PORT_A
)
7825 if (HAS_PCH_IBX(dev
)) {
7826 has_ck505
= dev_priv
->vbt
.display_clock_mode
;
7827 can_ssc
= has_ck505
;
7833 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
7834 has_panel
, has_lvds
, has_ck505
);
7836 /* Ironlake: try to setup display ref clock before DPLL
7837 * enabling. This is only under driver's control after
7838 * PCH B stepping, previous chipset stepping should be
7839 * ignoring this setting.
7841 val
= I915_READ(PCH_DREF_CONTROL
);
7843 /* As we must carefully and slowly disable/enable each source in turn,
7844 * compute the final state we want first and check if we need to
7845 * make any changes at all.
7848 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
7850 final
|= DREF_NONSPREAD_CK505_ENABLE
;
7852 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
7854 final
&= ~DREF_SSC_SOURCE_MASK
;
7855 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
7856 final
&= ~DREF_SSC1_ENABLE
;
7859 final
|= DREF_SSC_SOURCE_ENABLE
;
7861 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
7862 final
|= DREF_SSC1_ENABLE
;
7865 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
7866 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
7868 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
7870 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
7872 final
|= DREF_SSC_SOURCE_DISABLE
;
7873 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
7879 /* Always enable nonspread source */
7880 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
7883 val
|= DREF_NONSPREAD_CK505_ENABLE
;
7885 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
7888 val
&= ~DREF_SSC_SOURCE_MASK
;
7889 val
|= DREF_SSC_SOURCE_ENABLE
;
7891 /* SSC must be turned on before enabling the CPU output */
7892 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
7893 DRM_DEBUG_KMS("Using SSC on panel\n");
7894 val
|= DREF_SSC1_ENABLE
;
7896 val
&= ~DREF_SSC1_ENABLE
;
7898 /* Get SSC going before enabling the outputs */
7899 I915_WRITE(PCH_DREF_CONTROL
, val
);
7900 POSTING_READ(PCH_DREF_CONTROL
);
7903 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
7905 /* Enable CPU source on CPU attached eDP */
7907 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
7908 DRM_DEBUG_KMS("Using SSC on eDP\n");
7909 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
7911 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
7913 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
7915 I915_WRITE(PCH_DREF_CONTROL
, val
);
7916 POSTING_READ(PCH_DREF_CONTROL
);
7919 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7921 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
7923 /* Turn off CPU output */
7924 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
7926 I915_WRITE(PCH_DREF_CONTROL
, val
);
7927 POSTING_READ(PCH_DREF_CONTROL
);
7930 /* Turn off the SSC source */
7931 val
&= ~DREF_SSC_SOURCE_MASK
;
7932 val
|= DREF_SSC_SOURCE_DISABLE
;
7935 val
&= ~DREF_SSC1_ENABLE
;
7937 I915_WRITE(PCH_DREF_CONTROL
, val
);
7938 POSTING_READ(PCH_DREF_CONTROL
);
7942 BUG_ON(val
!= final
);
7945 static void lpt_reset_fdi_mphy(struct drm_i915_private
*dev_priv
)
7949 tmp
= I915_READ(SOUTH_CHICKEN2
);
7950 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
7951 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
7953 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2
) &
7954 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
7955 DRM_ERROR("FDI mPHY reset assert timeout\n");
7957 tmp
= I915_READ(SOUTH_CHICKEN2
);
7958 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
7959 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
7961 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2
) &
7962 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0, 100))
7963 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7966 /* WaMPhyProgramming:hsw */
7967 static void lpt_program_fdi_mphy(struct drm_i915_private
*dev_priv
)
7971 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
7972 tmp
&= ~(0xFF << 24);
7973 tmp
|= (0x12 << 24);
7974 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
7976 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
7978 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
7980 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
7982 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
7984 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
7985 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
7986 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
7988 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
7989 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
7990 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
7992 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
7995 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
7997 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
8000 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
8002 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
8005 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
8007 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
8010 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
8012 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
8013 tmp
&= ~(0xFF << 16);
8014 tmp
|= (0x1C << 16);
8015 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
8017 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
8018 tmp
&= ~(0xFF << 16);
8019 tmp
|= (0x1C << 16);
8020 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
8022 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
8024 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
8026 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
8028 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
8030 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
8031 tmp
&= ~(0xF << 28);
8033 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
8035 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
8036 tmp
&= ~(0xF << 28);
8038 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
8041 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8042 * Programming" based on the parameters passed:
8043 * - Sequence to enable CLKOUT_DP
8044 * - Sequence to enable CLKOUT_DP without spread
8045 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8047 static void lpt_enable_clkout_dp(struct drm_device
*dev
, bool with_spread
,
8050 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8053 if (WARN(with_fdi
&& !with_spread
, "FDI requires downspread\n"))
8055 if (WARN(dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
&&
8056 with_fdi
, "LP PCH doesn't have FDI\n"))
8059 mutex_lock(&dev_priv
->dpio_lock
);
8061 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
8062 tmp
&= ~SBI_SSCCTL_DISABLE
;
8063 tmp
|= SBI_SSCCTL_PATHALT
;
8064 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8069 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
8070 tmp
&= ~SBI_SSCCTL_PATHALT
;
8071 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8074 lpt_reset_fdi_mphy(dev_priv
);
8075 lpt_program_fdi_mphy(dev_priv
);
8079 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
8080 SBI_GEN0
: SBI_DBUFF0
;
8081 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
8082 tmp
|= SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
8083 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
8085 mutex_unlock(&dev_priv
->dpio_lock
);
8088 /* Sequence to disable CLKOUT_DP */
8089 static void lpt_disable_clkout_dp(struct drm_device
*dev
)
8091 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8094 mutex_lock(&dev_priv
->dpio_lock
);
8096 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
8097 SBI_GEN0
: SBI_DBUFF0
;
8098 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
8099 tmp
&= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
8100 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
8102 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
8103 if (!(tmp
& SBI_SSCCTL_DISABLE
)) {
8104 if (!(tmp
& SBI_SSCCTL_PATHALT
)) {
8105 tmp
|= SBI_SSCCTL_PATHALT
;
8106 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8109 tmp
|= SBI_SSCCTL_DISABLE
;
8110 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8113 mutex_unlock(&dev_priv
->dpio_lock
);
8116 static void lpt_init_pch_refclk(struct drm_device
*dev
)
8118 struct intel_encoder
*encoder
;
8119 bool has_vga
= false;
8121 for_each_intel_encoder(dev
, encoder
) {
8122 switch (encoder
->type
) {
8123 case INTEL_OUTPUT_ANALOG
:
8132 lpt_enable_clkout_dp(dev
, true, true);
8134 lpt_disable_clkout_dp(dev
);
8138 * Initialize reference clocks when the driver loads
8140 void intel_init_pch_refclk(struct drm_device
*dev
)
8142 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
8143 ironlake_init_pch_refclk(dev
);
8144 else if (HAS_PCH_LPT(dev
))
8145 lpt_init_pch_refclk(dev
);
8148 static int ironlake_get_refclk(struct intel_crtc_state
*crtc_state
)
8150 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
8151 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8152 struct drm_atomic_state
*state
= crtc_state
->base
.state
;
8153 struct drm_connector
*connector
;
8154 struct drm_connector_state
*connector_state
;
8155 struct intel_encoder
*encoder
;
8156 int num_connectors
= 0, i
;
8157 bool is_lvds
= false;
8159 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
8160 if (connector_state
->crtc
!= crtc_state
->base
.crtc
)
8163 encoder
= to_intel_encoder(connector_state
->best_encoder
);
8165 switch (encoder
->type
) {
8166 case INTEL_OUTPUT_LVDS
:
8175 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
8176 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8177 dev_priv
->vbt
.lvds_ssc_freq
);
8178 return dev_priv
->vbt
.lvds_ssc_freq
;
8184 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
)
8186 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
8187 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8188 int pipe
= intel_crtc
->pipe
;
8193 switch (intel_crtc
->config
->pipe_bpp
) {
8195 val
|= PIPECONF_6BPC
;
8198 val
|= PIPECONF_8BPC
;
8201 val
|= PIPECONF_10BPC
;
8204 val
|= PIPECONF_12BPC
;
8207 /* Case prevented by intel_choose_pipe_bpp_dither. */
8211 if (intel_crtc
->config
->dither
)
8212 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
8214 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
8215 val
|= PIPECONF_INTERLACED_ILK
;
8217 val
|= PIPECONF_PROGRESSIVE
;
8219 if (intel_crtc
->config
->limited_color_range
)
8220 val
|= PIPECONF_COLOR_RANGE_SELECT
;
8222 I915_WRITE(PIPECONF(pipe
), val
);
8223 POSTING_READ(PIPECONF(pipe
));
8227 * Set up the pipe CSC unit.
8229 * Currently only full range RGB to limited range RGB conversion
8230 * is supported, but eventually this should handle various
8231 * RGB<->YCbCr scenarios as well.
8233 static void intel_set_pipe_csc(struct drm_crtc
*crtc
)
8235 struct drm_device
*dev
= crtc
->dev
;
8236 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8237 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8238 int pipe
= intel_crtc
->pipe
;
8239 uint16_t coeff
= 0x7800; /* 1.0 */
8242 * TODO: Check what kind of values actually come out of the pipe
8243 * with these coeff/postoff values and adjust to get the best
8244 * accuracy. Perhaps we even need to take the bpc value into
8248 if (intel_crtc
->config
->limited_color_range
)
8249 coeff
= ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8252 * GY/GU and RY/RU should be the other way around according
8253 * to BSpec, but reality doesn't agree. Just set them up in
8254 * a way that results in the correct picture.
8256 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe
), coeff
<< 16);
8257 I915_WRITE(PIPE_CSC_COEFF_BY(pipe
), 0);
8259 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe
), coeff
);
8260 I915_WRITE(PIPE_CSC_COEFF_BU(pipe
), 0);
8262 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe
), 0);
8263 I915_WRITE(PIPE_CSC_COEFF_BV(pipe
), coeff
<< 16);
8265 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe
), 0);
8266 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe
), 0);
8267 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe
), 0);
8269 if (INTEL_INFO(dev
)->gen
> 6) {
8270 uint16_t postoff
= 0;
8272 if (intel_crtc
->config
->limited_color_range
)
8273 postoff
= (16 * (1 << 12) / 255) & 0x1fff;
8275 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe
), postoff
);
8276 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe
), postoff
);
8277 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe
), postoff
);
8279 I915_WRITE(PIPE_CSC_MODE(pipe
), 0);
8281 uint32_t mode
= CSC_MODE_YUV_TO_RGB
;
8283 if (intel_crtc
->config
->limited_color_range
)
8284 mode
|= CSC_BLACK_SCREEN_OFFSET
;
8286 I915_WRITE(PIPE_CSC_MODE(pipe
), mode
);
8290 static void haswell_set_pipeconf(struct drm_crtc
*crtc
)
8292 struct drm_device
*dev
= crtc
->dev
;
8293 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8294 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8295 enum pipe pipe
= intel_crtc
->pipe
;
8296 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
8301 if (IS_HASWELL(dev
) && intel_crtc
->config
->dither
)
8302 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
8304 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
8305 val
|= PIPECONF_INTERLACED_ILK
;
8307 val
|= PIPECONF_PROGRESSIVE
;
8309 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
8310 POSTING_READ(PIPECONF(cpu_transcoder
));
8312 I915_WRITE(GAMMA_MODE(intel_crtc
->pipe
), GAMMA_MODE_MODE_8BIT
);
8313 POSTING_READ(GAMMA_MODE(intel_crtc
->pipe
));
8315 if (IS_BROADWELL(dev
) || INTEL_INFO(dev
)->gen
>= 9) {
8318 switch (intel_crtc
->config
->pipe_bpp
) {
8320 val
|= PIPEMISC_DITHER_6_BPC
;
8323 val
|= PIPEMISC_DITHER_8_BPC
;
8326 val
|= PIPEMISC_DITHER_10_BPC
;
8329 val
|= PIPEMISC_DITHER_12_BPC
;
8332 /* Case prevented by pipe_config_set_bpp. */
8336 if (intel_crtc
->config
->dither
)
8337 val
|= PIPEMISC_DITHER_ENABLE
| PIPEMISC_DITHER_TYPE_SP
;
8339 I915_WRITE(PIPEMISC(pipe
), val
);
8343 static bool ironlake_compute_clocks(struct drm_crtc
*crtc
,
8344 struct intel_crtc_state
*crtc_state
,
8345 intel_clock_t
*clock
,
8346 bool *has_reduced_clock
,
8347 intel_clock_t
*reduced_clock
)
8349 struct drm_device
*dev
= crtc
->dev
;
8350 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8352 const intel_limit_t
*limit
;
8353 bool ret
, is_lvds
= false;
8355 is_lvds
= intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
);
8357 refclk
= ironlake_get_refclk(crtc_state
);
8360 * Returns a set of divisors for the desired target clock with the given
8361 * refclk, or FALSE. The returned values represent the clock equation:
8362 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8364 limit
= intel_limit(crtc_state
, refclk
);
8365 ret
= dev_priv
->display
.find_dpll(limit
, crtc_state
,
8366 crtc_state
->port_clock
,
8367 refclk
, NULL
, clock
);
8371 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
8373 * Ensure we match the reduced clock's P to the target clock.
8374 * If the clocks don't match, we can't switch the display clock
8375 * by using the FP0/FP1. In such case we will disable the LVDS
8376 * downclock feature.
8378 *has_reduced_clock
=
8379 dev_priv
->display
.find_dpll(limit
, crtc_state
,
8380 dev_priv
->lvds_downclock
,
8388 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
8391 * Account for spread spectrum to avoid
8392 * oversubscribing the link. Max center spread
8393 * is 2.5%; use 5% for safety's sake.
8395 u32 bps
= target_clock
* bpp
* 21 / 20;
8396 return DIV_ROUND_UP(bps
, link_bw
* 8);
8399 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
8401 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
8404 static uint32_t ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
8405 struct intel_crtc_state
*crtc_state
,
8407 intel_clock_t
*reduced_clock
, u32
*fp2
)
8409 struct drm_crtc
*crtc
= &intel_crtc
->base
;
8410 struct drm_device
*dev
= crtc
->dev
;
8411 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8412 struct drm_atomic_state
*state
= crtc_state
->base
.state
;
8413 struct drm_connector
*connector
;
8414 struct drm_connector_state
*connector_state
;
8415 struct intel_encoder
*encoder
;
8417 int factor
, num_connectors
= 0, i
;
8418 bool is_lvds
= false, is_sdvo
= false;
8420 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
8421 if (connector_state
->crtc
!= crtc_state
->base
.crtc
)
8424 encoder
= to_intel_encoder(connector_state
->best_encoder
);
8426 switch (encoder
->type
) {
8427 case INTEL_OUTPUT_LVDS
:
8430 case INTEL_OUTPUT_SDVO
:
8431 case INTEL_OUTPUT_HDMI
:
8441 /* Enable autotuning of the PLL clock (if permissible) */
8444 if ((intel_panel_use_ssc(dev_priv
) &&
8445 dev_priv
->vbt
.lvds_ssc_freq
== 100000) ||
8446 (HAS_PCH_IBX(dev
) && intel_is_dual_link_lvds(dev
)))
8448 } else if (crtc_state
->sdvo_tv_clock
)
8451 if (ironlake_needs_fb_cb_tune(&crtc_state
->dpll
, factor
))
8454 if (fp2
&& (reduced_clock
->m
< factor
* reduced_clock
->n
))
8460 dpll
|= DPLLB_MODE_LVDS
;
8462 dpll
|= DPLLB_MODE_DAC_SERIAL
;
8464 dpll
|= (crtc_state
->pixel_multiplier
- 1)
8465 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
8468 dpll
|= DPLL_SDVO_HIGH_SPEED
;
8469 if (crtc_state
->has_dp_encoder
)
8470 dpll
|= DPLL_SDVO_HIGH_SPEED
;
8472 /* compute bitmask from p1 value */
8473 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
8475 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
8477 switch (crtc_state
->dpll
.p2
) {
8479 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
8482 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
8485 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
8488 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
8492 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
8493 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
8495 dpll
|= PLL_REF_INPUT_DREFCLK
;
8497 return dpll
| DPLL_VCO_ENABLE
;
8500 static int ironlake_crtc_compute_clock(struct intel_crtc
*crtc
,
8501 struct intel_crtc_state
*crtc_state
)
8503 struct drm_device
*dev
= crtc
->base
.dev
;
8504 intel_clock_t clock
, reduced_clock
;
8505 u32 dpll
= 0, fp
= 0, fp2
= 0;
8506 bool ok
, has_reduced_clock
= false;
8507 bool is_lvds
= false;
8508 struct intel_shared_dpll
*pll
;
8510 memset(&crtc_state
->dpll_hw_state
, 0,
8511 sizeof(crtc_state
->dpll_hw_state
));
8513 is_lvds
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
);
8515 WARN(!(HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)),
8516 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev
));
8518 ok
= ironlake_compute_clocks(&crtc
->base
, crtc_state
, &clock
,
8519 &has_reduced_clock
, &reduced_clock
);
8520 if (!ok
&& !crtc_state
->clock_set
) {
8521 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8524 /* Compat-code for transition, will disappear. */
8525 if (!crtc_state
->clock_set
) {
8526 crtc_state
->dpll
.n
= clock
.n
;
8527 crtc_state
->dpll
.m1
= clock
.m1
;
8528 crtc_state
->dpll
.m2
= clock
.m2
;
8529 crtc_state
->dpll
.p1
= clock
.p1
;
8530 crtc_state
->dpll
.p2
= clock
.p2
;
8533 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8534 if (crtc_state
->has_pch_encoder
) {
8535 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
8536 if (has_reduced_clock
)
8537 fp2
= i9xx_dpll_compute_fp(&reduced_clock
);
8539 dpll
= ironlake_compute_dpll(crtc
, crtc_state
,
8540 &fp
, &reduced_clock
,
8541 has_reduced_clock
? &fp2
: NULL
);
8543 crtc_state
->dpll_hw_state
.dpll
= dpll
;
8544 crtc_state
->dpll_hw_state
.fp0
= fp
;
8545 if (has_reduced_clock
)
8546 crtc_state
->dpll_hw_state
.fp1
= fp2
;
8548 crtc_state
->dpll_hw_state
.fp1
= fp
;
8550 pll
= intel_get_shared_dpll(crtc
, crtc_state
);
8552 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8553 pipe_name(crtc
->pipe
));
8558 if (is_lvds
&& has_reduced_clock
)
8559 crtc
->lowfreq_avail
= true;
8561 crtc
->lowfreq_avail
= false;
8566 static void intel_pch_transcoder_get_m_n(struct intel_crtc
*crtc
,
8567 struct intel_link_m_n
*m_n
)
8569 struct drm_device
*dev
= crtc
->base
.dev
;
8570 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8571 enum pipe pipe
= crtc
->pipe
;
8573 m_n
->link_m
= I915_READ(PCH_TRANS_LINK_M1(pipe
));
8574 m_n
->link_n
= I915_READ(PCH_TRANS_LINK_N1(pipe
));
8575 m_n
->gmch_m
= I915_READ(PCH_TRANS_DATA_M1(pipe
))
8577 m_n
->gmch_n
= I915_READ(PCH_TRANS_DATA_N1(pipe
));
8578 m_n
->tu
= ((I915_READ(PCH_TRANS_DATA_M1(pipe
))
8579 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
8582 static void intel_cpu_transcoder_get_m_n(struct intel_crtc
*crtc
,
8583 enum transcoder transcoder
,
8584 struct intel_link_m_n
*m_n
,
8585 struct intel_link_m_n
*m2_n2
)
8587 struct drm_device
*dev
= crtc
->base
.dev
;
8588 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8589 enum pipe pipe
= crtc
->pipe
;
8591 if (INTEL_INFO(dev
)->gen
>= 5) {
8592 m_n
->link_m
= I915_READ(PIPE_LINK_M1(transcoder
));
8593 m_n
->link_n
= I915_READ(PIPE_LINK_N1(transcoder
));
8594 m_n
->gmch_m
= I915_READ(PIPE_DATA_M1(transcoder
))
8596 m_n
->gmch_n
= I915_READ(PIPE_DATA_N1(transcoder
));
8597 m_n
->tu
= ((I915_READ(PIPE_DATA_M1(transcoder
))
8598 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
8599 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8600 * gen < 8) and if DRRS is supported (to make sure the
8601 * registers are not unnecessarily read).
8603 if (m2_n2
&& INTEL_INFO(dev
)->gen
< 8 &&
8604 crtc
->config
->has_drrs
) {
8605 m2_n2
->link_m
= I915_READ(PIPE_LINK_M2(transcoder
));
8606 m2_n2
->link_n
= I915_READ(PIPE_LINK_N2(transcoder
));
8607 m2_n2
->gmch_m
= I915_READ(PIPE_DATA_M2(transcoder
))
8609 m2_n2
->gmch_n
= I915_READ(PIPE_DATA_N2(transcoder
));
8610 m2_n2
->tu
= ((I915_READ(PIPE_DATA_M2(transcoder
))
8611 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
8614 m_n
->link_m
= I915_READ(PIPE_LINK_M_G4X(pipe
));
8615 m_n
->link_n
= I915_READ(PIPE_LINK_N_G4X(pipe
));
8616 m_n
->gmch_m
= I915_READ(PIPE_DATA_M_G4X(pipe
))
8618 m_n
->gmch_n
= I915_READ(PIPE_DATA_N_G4X(pipe
));
8619 m_n
->tu
= ((I915_READ(PIPE_DATA_M_G4X(pipe
))
8620 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
8624 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
8625 struct intel_crtc_state
*pipe_config
)
8627 if (pipe_config
->has_pch_encoder
)
8628 intel_pch_transcoder_get_m_n(crtc
, &pipe_config
->dp_m_n
);
8630 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
8631 &pipe_config
->dp_m_n
,
8632 &pipe_config
->dp_m2_n2
);
8635 static void ironlake_get_fdi_m_n_config(struct intel_crtc
*crtc
,
8636 struct intel_crtc_state
*pipe_config
)
8638 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
8639 &pipe_config
->fdi_m_n
, NULL
);
8642 static void skylake_get_pfit_config(struct intel_crtc
*crtc
,
8643 struct intel_crtc_state
*pipe_config
)
8645 struct drm_device
*dev
= crtc
->base
.dev
;
8646 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8647 struct intel_crtc_scaler_state
*scaler_state
= &pipe_config
->scaler_state
;
8648 uint32_t ps_ctrl
= 0;
8652 /* find scaler attached to this pipe */
8653 for (i
= 0; i
< crtc
->num_scalers
; i
++) {
8654 ps_ctrl
= I915_READ(SKL_PS_CTRL(crtc
->pipe
, i
));
8655 if (ps_ctrl
& PS_SCALER_EN
&& !(ps_ctrl
& PS_PLANE_SEL_MASK
)) {
8657 pipe_config
->pch_pfit
.enabled
= true;
8658 pipe_config
->pch_pfit
.pos
= I915_READ(SKL_PS_WIN_POS(crtc
->pipe
, i
));
8659 pipe_config
->pch_pfit
.size
= I915_READ(SKL_PS_WIN_SZ(crtc
->pipe
, i
));
8664 scaler_state
->scaler_id
= id
;
8666 scaler_state
->scaler_users
|= (1 << SKL_CRTC_INDEX
);
8668 scaler_state
->scaler_users
&= ~(1 << SKL_CRTC_INDEX
);
8673 skylake_get_initial_plane_config(struct intel_crtc
*crtc
,
8674 struct intel_initial_plane_config
*plane_config
)
8676 struct drm_device
*dev
= crtc
->base
.dev
;
8677 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8678 u32 val
, base
, offset
, stride_mult
, tiling
;
8679 int pipe
= crtc
->pipe
;
8680 int fourcc
, pixel_format
;
8681 unsigned int aligned_height
;
8682 struct drm_framebuffer
*fb
;
8683 struct intel_framebuffer
*intel_fb
;
8685 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
8687 DRM_DEBUG_KMS("failed to alloc fb\n");
8691 fb
= &intel_fb
->base
;
8693 val
= I915_READ(PLANE_CTL(pipe
, 0));
8694 if (!(val
& PLANE_CTL_ENABLE
))
8697 pixel_format
= val
& PLANE_CTL_FORMAT_MASK
;
8698 fourcc
= skl_format_to_fourcc(pixel_format
,
8699 val
& PLANE_CTL_ORDER_RGBX
,
8700 val
& PLANE_CTL_ALPHA_MASK
);
8701 fb
->pixel_format
= fourcc
;
8702 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
8704 tiling
= val
& PLANE_CTL_TILED_MASK
;
8706 case PLANE_CTL_TILED_LINEAR
:
8707 fb
->modifier
[0] = DRM_FORMAT_MOD_NONE
;
8709 case PLANE_CTL_TILED_X
:
8710 plane_config
->tiling
= I915_TILING_X
;
8711 fb
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
8713 case PLANE_CTL_TILED_Y
:
8714 fb
->modifier
[0] = I915_FORMAT_MOD_Y_TILED
;
8716 case PLANE_CTL_TILED_YF
:
8717 fb
->modifier
[0] = I915_FORMAT_MOD_Yf_TILED
;
8720 MISSING_CASE(tiling
);
8724 base
= I915_READ(PLANE_SURF(pipe
, 0)) & 0xfffff000;
8725 plane_config
->base
= base
;
8727 offset
= I915_READ(PLANE_OFFSET(pipe
, 0));
8729 val
= I915_READ(PLANE_SIZE(pipe
, 0));
8730 fb
->height
= ((val
>> 16) & 0xfff) + 1;
8731 fb
->width
= ((val
>> 0) & 0x1fff) + 1;
8733 val
= I915_READ(PLANE_STRIDE(pipe
, 0));
8734 stride_mult
= intel_fb_stride_alignment(dev
, fb
->modifier
[0],
8736 fb
->pitches
[0] = (val
& 0x3ff) * stride_mult
;
8738 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
8742 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
8744 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8745 pipe_name(pipe
), fb
->width
, fb
->height
,
8746 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
8747 plane_config
->size
);
8749 plane_config
->fb
= intel_fb
;
8756 static void ironlake_get_pfit_config(struct intel_crtc
*crtc
,
8757 struct intel_crtc_state
*pipe_config
)
8759 struct drm_device
*dev
= crtc
->base
.dev
;
8760 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8763 tmp
= I915_READ(PF_CTL(crtc
->pipe
));
8765 if (tmp
& PF_ENABLE
) {
8766 pipe_config
->pch_pfit
.enabled
= true;
8767 pipe_config
->pch_pfit
.pos
= I915_READ(PF_WIN_POS(crtc
->pipe
));
8768 pipe_config
->pch_pfit
.size
= I915_READ(PF_WIN_SZ(crtc
->pipe
));
8770 /* We currently do not free assignements of panel fitters on
8771 * ivb/hsw (since we don't use the higher upscaling modes which
8772 * differentiates them) so just WARN about this case for now. */
8774 WARN_ON((tmp
& PF_PIPE_SEL_MASK_IVB
) !=
8775 PF_PIPE_SEL_IVB(crtc
->pipe
));
8781 ironlake_get_initial_plane_config(struct intel_crtc
*crtc
,
8782 struct intel_initial_plane_config
*plane_config
)
8784 struct drm_device
*dev
= crtc
->base
.dev
;
8785 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8786 u32 val
, base
, offset
;
8787 int pipe
= crtc
->pipe
;
8788 int fourcc
, pixel_format
;
8789 unsigned int aligned_height
;
8790 struct drm_framebuffer
*fb
;
8791 struct intel_framebuffer
*intel_fb
;
8793 val
= I915_READ(DSPCNTR(pipe
));
8794 if (!(val
& DISPLAY_PLANE_ENABLE
))
8797 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
8799 DRM_DEBUG_KMS("failed to alloc fb\n");
8803 fb
= &intel_fb
->base
;
8805 if (INTEL_INFO(dev
)->gen
>= 4) {
8806 if (val
& DISPPLANE_TILED
) {
8807 plane_config
->tiling
= I915_TILING_X
;
8808 fb
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
8812 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
8813 fourcc
= i9xx_format_to_fourcc(pixel_format
);
8814 fb
->pixel_format
= fourcc
;
8815 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
8817 base
= I915_READ(DSPSURF(pipe
)) & 0xfffff000;
8818 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
8819 offset
= I915_READ(DSPOFFSET(pipe
));
8821 if (plane_config
->tiling
)
8822 offset
= I915_READ(DSPTILEOFF(pipe
));
8824 offset
= I915_READ(DSPLINOFF(pipe
));
8826 plane_config
->base
= base
;
8828 val
= I915_READ(PIPESRC(pipe
));
8829 fb
->width
= ((val
>> 16) & 0xfff) + 1;
8830 fb
->height
= ((val
>> 0) & 0xfff) + 1;
8832 val
= I915_READ(DSPSTRIDE(pipe
));
8833 fb
->pitches
[0] = val
& 0xffffffc0;
8835 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
8839 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
8841 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8842 pipe_name(pipe
), fb
->width
, fb
->height
,
8843 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
8844 plane_config
->size
);
8846 plane_config
->fb
= intel_fb
;
8849 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
8850 struct intel_crtc_state
*pipe_config
)
8852 struct drm_device
*dev
= crtc
->base
.dev
;
8853 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8856 if (!intel_display_power_is_enabled(dev_priv
,
8857 POWER_DOMAIN_PIPE(crtc
->pipe
)))
8860 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
8861 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
8863 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
8864 if (!(tmp
& PIPECONF_ENABLE
))
8867 switch (tmp
& PIPECONF_BPC_MASK
) {
8869 pipe_config
->pipe_bpp
= 18;
8872 pipe_config
->pipe_bpp
= 24;
8874 case PIPECONF_10BPC
:
8875 pipe_config
->pipe_bpp
= 30;
8877 case PIPECONF_12BPC
:
8878 pipe_config
->pipe_bpp
= 36;
8884 if (tmp
& PIPECONF_COLOR_RANGE_SELECT
)
8885 pipe_config
->limited_color_range
= true;
8887 if (I915_READ(PCH_TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
) {
8888 struct intel_shared_dpll
*pll
;
8890 pipe_config
->has_pch_encoder
= true;
8892 tmp
= I915_READ(FDI_RX_CTL(crtc
->pipe
));
8893 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
8894 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
8896 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
8898 if (HAS_PCH_IBX(dev_priv
->dev
)) {
8899 pipe_config
->shared_dpll
=
8900 (enum intel_dpll_id
) crtc
->pipe
;
8902 tmp
= I915_READ(PCH_DPLL_SEL
);
8903 if (tmp
& TRANS_DPLLB_SEL(crtc
->pipe
))
8904 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_B
;
8906 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_A
;
8909 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
8911 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
8912 &pipe_config
->dpll_hw_state
));
8914 tmp
= pipe_config
->dpll_hw_state
.dpll
;
8915 pipe_config
->pixel_multiplier
=
8916 ((tmp
& PLL_REF_SDVO_HDMI_MULTIPLIER_MASK
)
8917 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
) + 1;
8919 ironlake_pch_clock_get(crtc
, pipe_config
);
8921 pipe_config
->pixel_multiplier
= 1;
8924 intel_get_pipe_timings(crtc
, pipe_config
);
8926 ironlake_get_pfit_config(crtc
, pipe_config
);
8931 static void assert_can_disable_lcpll(struct drm_i915_private
*dev_priv
)
8933 struct drm_device
*dev
= dev_priv
->dev
;
8934 struct intel_crtc
*crtc
;
8936 for_each_intel_crtc(dev
, crtc
)
8937 I915_STATE_WARN(crtc
->active
, "CRTC for pipe %c enabled\n",
8938 pipe_name(crtc
->pipe
));
8940 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER
), "Power well on\n");
8941 I915_STATE_WARN(I915_READ(SPLL_CTL
) & SPLL_PLL_ENABLE
, "SPLL enabled\n");
8942 I915_STATE_WARN(I915_READ(WRPLL_CTL1
) & WRPLL_PLL_ENABLE
, "WRPLL1 enabled\n");
8943 I915_STATE_WARN(I915_READ(WRPLL_CTL2
) & WRPLL_PLL_ENABLE
, "WRPLL2 enabled\n");
8944 I915_STATE_WARN(I915_READ(PCH_PP_STATUS
) & PP_ON
, "Panel power on\n");
8945 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2
) & BLM_PWM_ENABLE
,
8946 "CPU PWM1 enabled\n");
8947 if (IS_HASWELL(dev
))
8948 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL
) & BLM_PWM_ENABLE
,
8949 "CPU PWM2 enabled\n");
8950 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1
) & BLM_PCH_PWM_ENABLE
,
8951 "PCH PWM1 enabled\n");
8952 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL
) & UTIL_PIN_ENABLE
,
8953 "Utility pin enabled\n");
8954 I915_STATE_WARN(I915_READ(PCH_GTC_CTL
) & PCH_GTC_ENABLE
, "PCH GTC enabled\n");
8957 * In theory we can still leave IRQs enabled, as long as only the HPD
8958 * interrupts remain enabled. We used to check for that, but since it's
8959 * gen-specific and since we only disable LCPLL after we fully disable
8960 * the interrupts, the check below should be enough.
8962 I915_STATE_WARN(intel_irqs_enabled(dev_priv
), "IRQs enabled\n");
8965 static uint32_t hsw_read_dcomp(struct drm_i915_private
*dev_priv
)
8967 struct drm_device
*dev
= dev_priv
->dev
;
8969 if (IS_HASWELL(dev
))
8970 return I915_READ(D_COMP_HSW
);
8972 return I915_READ(D_COMP_BDW
);
8975 static void hsw_write_dcomp(struct drm_i915_private
*dev_priv
, uint32_t val
)
8977 struct drm_device
*dev
= dev_priv
->dev
;
8979 if (IS_HASWELL(dev
)) {
8980 mutex_lock(&dev_priv
->rps
.hw_lock
);
8981 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
,
8983 DRM_ERROR("Failed to write to D_COMP\n");
8984 mutex_unlock(&dev_priv
->rps
.hw_lock
);
8986 I915_WRITE(D_COMP_BDW
, val
);
8987 POSTING_READ(D_COMP_BDW
);
8992 * This function implements pieces of two sequences from BSpec:
8993 * - Sequence for display software to disable LCPLL
8994 * - Sequence for display software to allow package C8+
8995 * The steps implemented here are just the steps that actually touch the LCPLL
8996 * register. Callers should take care of disabling all the display engine
8997 * functions, doing the mode unset, fixing interrupts, etc.
8999 static void hsw_disable_lcpll(struct drm_i915_private
*dev_priv
,
9000 bool switch_to_fclk
, bool allow_power_down
)
9004 assert_can_disable_lcpll(dev_priv
);
9006 val
= I915_READ(LCPLL_CTL
);
9008 if (switch_to_fclk
) {
9009 val
|= LCPLL_CD_SOURCE_FCLK
;
9010 I915_WRITE(LCPLL_CTL
, val
);
9012 if (wait_for_atomic_us(I915_READ(LCPLL_CTL
) &
9013 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
9014 DRM_ERROR("Switching to FCLK failed\n");
9016 val
= I915_READ(LCPLL_CTL
);
9019 val
|= LCPLL_PLL_DISABLE
;
9020 I915_WRITE(LCPLL_CTL
, val
);
9021 POSTING_READ(LCPLL_CTL
);
9023 if (wait_for((I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
) == 0, 1))
9024 DRM_ERROR("LCPLL still locked\n");
9026 val
= hsw_read_dcomp(dev_priv
);
9027 val
|= D_COMP_COMP_DISABLE
;
9028 hsw_write_dcomp(dev_priv
, val
);
9031 if (wait_for((hsw_read_dcomp(dev_priv
) & D_COMP_RCOMP_IN_PROGRESS
) == 0,
9033 DRM_ERROR("D_COMP RCOMP still in progress\n");
9035 if (allow_power_down
) {
9036 val
= I915_READ(LCPLL_CTL
);
9037 val
|= LCPLL_POWER_DOWN_ALLOW
;
9038 I915_WRITE(LCPLL_CTL
, val
);
9039 POSTING_READ(LCPLL_CTL
);
9044 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9047 static void hsw_restore_lcpll(struct drm_i915_private
*dev_priv
)
9051 val
= I915_READ(LCPLL_CTL
);
9053 if ((val
& (LCPLL_PLL_LOCK
| LCPLL_PLL_DISABLE
| LCPLL_CD_SOURCE_FCLK
|
9054 LCPLL_POWER_DOWN_ALLOW
)) == LCPLL_PLL_LOCK
)
9058 * Make sure we're not on PC8 state before disabling PC8, otherwise
9059 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9061 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
9063 if (val
& LCPLL_POWER_DOWN_ALLOW
) {
9064 val
&= ~LCPLL_POWER_DOWN_ALLOW
;
9065 I915_WRITE(LCPLL_CTL
, val
);
9066 POSTING_READ(LCPLL_CTL
);
9069 val
= hsw_read_dcomp(dev_priv
);
9070 val
|= D_COMP_COMP_FORCE
;
9071 val
&= ~D_COMP_COMP_DISABLE
;
9072 hsw_write_dcomp(dev_priv
, val
);
9074 val
= I915_READ(LCPLL_CTL
);
9075 val
&= ~LCPLL_PLL_DISABLE
;
9076 I915_WRITE(LCPLL_CTL
, val
);
9078 if (wait_for(I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
, 5))
9079 DRM_ERROR("LCPLL not locked yet\n");
9081 if (val
& LCPLL_CD_SOURCE_FCLK
) {
9082 val
= I915_READ(LCPLL_CTL
);
9083 val
&= ~LCPLL_CD_SOURCE_FCLK
;
9084 I915_WRITE(LCPLL_CTL
, val
);
9086 if (wait_for_atomic_us((I915_READ(LCPLL_CTL
) &
9087 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
9088 DRM_ERROR("Switching back to LCPLL failed\n");
9091 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
9095 * Package states C8 and deeper are really deep PC states that can only be
9096 * reached when all the devices on the system allow it, so even if the graphics
9097 * device allows PC8+, it doesn't mean the system will actually get to these
9098 * states. Our driver only allows PC8+ when going into runtime PM.
9100 * The requirements for PC8+ are that all the outputs are disabled, the power
9101 * well is disabled and most interrupts are disabled, and these are also
9102 * requirements for runtime PM. When these conditions are met, we manually do
9103 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9104 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9107 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9108 * the state of some registers, so when we come back from PC8+ we need to
9109 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9110 * need to take care of the registers kept by RC6. Notice that this happens even
9111 * if we don't put the device in PCI D3 state (which is what currently happens
9112 * because of the runtime PM support).
9114 * For more, read "Display Sequences for Package C8" on the hardware
9117 void hsw_enable_pc8(struct drm_i915_private
*dev_priv
)
9119 struct drm_device
*dev
= dev_priv
->dev
;
9122 DRM_DEBUG_KMS("Enabling package C8+\n");
9124 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
9125 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
9126 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
9127 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
9130 lpt_disable_clkout_dp(dev
);
9131 hsw_disable_lcpll(dev_priv
, true, true);
9134 void hsw_disable_pc8(struct drm_i915_private
*dev_priv
)
9136 struct drm_device
*dev
= dev_priv
->dev
;
9139 DRM_DEBUG_KMS("Disabling package C8+\n");
9141 hsw_restore_lcpll(dev_priv
);
9142 lpt_init_pch_refclk(dev
);
9144 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
9145 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
9146 val
|= PCH_LP_PARTITION_LEVEL_DISABLE
;
9147 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
9150 intel_prepare_ddi(dev
);
9153 static void broxton_modeset_global_resources(struct drm_atomic_state
*old_state
)
9155 struct drm_device
*dev
= old_state
->dev
;
9156 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9157 int max_pixclk
= intel_mode_max_pixclk(dev
, NULL
);
9160 /* see the comment in valleyview_modeset_global_resources */
9161 if (WARN_ON(max_pixclk
< 0))
9164 req_cdclk
= broxton_calc_cdclk(dev_priv
, max_pixclk
);
9166 if (req_cdclk
!= dev_priv
->cdclk_freq
)
9167 broxton_set_cdclk(dev
, req_cdclk
);
9170 static int haswell_crtc_compute_clock(struct intel_crtc
*crtc
,
9171 struct intel_crtc_state
*crtc_state
)
9173 if (!intel_ddi_pll_select(crtc
, crtc_state
))
9176 crtc
->lowfreq_avail
= false;
9181 static void bxt_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9183 struct intel_crtc_state
*pipe_config
)
9187 pipe_config
->ddi_pll_sel
= SKL_DPLL0
;
9188 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL1
;
9191 pipe_config
->ddi_pll_sel
= SKL_DPLL1
;
9192 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL2
;
9195 pipe_config
->ddi_pll_sel
= SKL_DPLL2
;
9196 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL3
;
9199 DRM_ERROR("Incorrect port type\n");
9203 static void skylake_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9205 struct intel_crtc_state
*pipe_config
)
9207 u32 temp
, dpll_ctl1
;
9209 temp
= I915_READ(DPLL_CTRL2
) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port
);
9210 pipe_config
->ddi_pll_sel
= temp
>> (port
* 3 + 1);
9212 switch (pipe_config
->ddi_pll_sel
) {
9215 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9216 * of the shared DPLL framework and thus needs to be read out
9219 dpll_ctl1
= I915_READ(DPLL_CTRL1
);
9220 pipe_config
->dpll_hw_state
.ctrl1
= dpll_ctl1
& 0x3f;
9223 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL1
;
9226 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL2
;
9229 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL3
;
9234 static void haswell_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9236 struct intel_crtc_state
*pipe_config
)
9238 pipe_config
->ddi_pll_sel
= I915_READ(PORT_CLK_SEL(port
));
9240 switch (pipe_config
->ddi_pll_sel
) {
9241 case PORT_CLK_SEL_WRPLL1
:
9242 pipe_config
->shared_dpll
= DPLL_ID_WRPLL1
;
9244 case PORT_CLK_SEL_WRPLL2
:
9245 pipe_config
->shared_dpll
= DPLL_ID_WRPLL2
;
9250 static void haswell_get_ddi_port_state(struct intel_crtc
*crtc
,
9251 struct intel_crtc_state
*pipe_config
)
9253 struct drm_device
*dev
= crtc
->base
.dev
;
9254 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9255 struct intel_shared_dpll
*pll
;
9259 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
9261 port
= (tmp
& TRANS_DDI_PORT_MASK
) >> TRANS_DDI_PORT_SHIFT
;
9263 if (IS_SKYLAKE(dev
))
9264 skylake_get_ddi_pll(dev_priv
, port
, pipe_config
);
9265 else if (IS_BROXTON(dev
))
9266 bxt_get_ddi_pll(dev_priv
, port
, pipe_config
);
9268 haswell_get_ddi_pll(dev_priv
, port
, pipe_config
);
9270 if (pipe_config
->shared_dpll
>= 0) {
9271 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
9273 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
9274 &pipe_config
->dpll_hw_state
));
9278 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9279 * DDI E. So just check whether this pipe is wired to DDI E and whether
9280 * the PCH transcoder is on.
9282 if (INTEL_INFO(dev
)->gen
< 9 &&
9283 (port
== PORT_E
) && I915_READ(LPT_TRANSCONF
) & TRANS_ENABLE
) {
9284 pipe_config
->has_pch_encoder
= true;
9286 tmp
= I915_READ(FDI_RX_CTL(PIPE_A
));
9287 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
9288 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
9290 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
9294 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
9295 struct intel_crtc_state
*pipe_config
)
9297 struct drm_device
*dev
= crtc
->base
.dev
;
9298 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9299 enum intel_display_power_domain pfit_domain
;
9302 if (!intel_display_power_is_enabled(dev_priv
,
9303 POWER_DOMAIN_PIPE(crtc
->pipe
)))
9306 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
9307 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
9309 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
9310 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
9311 enum pipe trans_edp_pipe
;
9312 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
9314 WARN(1, "unknown pipe linked to edp transcoder\n");
9315 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
9316 case TRANS_DDI_EDP_INPUT_A_ON
:
9317 trans_edp_pipe
= PIPE_A
;
9319 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
9320 trans_edp_pipe
= PIPE_B
;
9322 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
9323 trans_edp_pipe
= PIPE_C
;
9327 if (trans_edp_pipe
== crtc
->pipe
)
9328 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
9331 if (!intel_display_power_is_enabled(dev_priv
,
9332 POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
)))
9335 tmp
= I915_READ(PIPECONF(pipe_config
->cpu_transcoder
));
9336 if (!(tmp
& PIPECONF_ENABLE
))
9339 haswell_get_ddi_port_state(crtc
, pipe_config
);
9341 intel_get_pipe_timings(crtc
, pipe_config
);
9343 if (INTEL_INFO(dev
)->gen
>= 9) {
9344 skl_init_scalers(dev
, crtc
, pipe_config
);
9347 pfit_domain
= POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
);
9349 if (INTEL_INFO(dev
)->gen
>= 9) {
9350 pipe_config
->scaler_state
.scaler_id
= -1;
9351 pipe_config
->scaler_state
.scaler_users
&= ~(1 << SKL_CRTC_INDEX
);
9354 if (intel_display_power_is_enabled(dev_priv
, pfit_domain
)) {
9355 if (INTEL_INFO(dev
)->gen
== 9)
9356 skylake_get_pfit_config(crtc
, pipe_config
);
9357 else if (INTEL_INFO(dev
)->gen
< 9)
9358 ironlake_get_pfit_config(crtc
, pipe_config
);
9360 MISSING_CASE(INTEL_INFO(dev
)->gen
);
9363 if (IS_HASWELL(dev
))
9364 pipe_config
->ips_enabled
= hsw_crtc_supports_ips(crtc
) &&
9365 (I915_READ(IPS_CTL
) & IPS_ENABLE
);
9367 if (pipe_config
->cpu_transcoder
!= TRANSCODER_EDP
) {
9368 pipe_config
->pixel_multiplier
=
9369 I915_READ(PIPE_MULT(pipe_config
->cpu_transcoder
)) + 1;
9371 pipe_config
->pixel_multiplier
= 1;
9377 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
9379 struct drm_device
*dev
= crtc
->dev
;
9380 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9381 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9382 uint32_t cntl
= 0, size
= 0;
9385 unsigned int width
= intel_crtc
->base
.cursor
->state
->crtc_w
;
9386 unsigned int height
= intel_crtc
->base
.cursor
->state
->crtc_h
;
9387 unsigned int stride
= roundup_pow_of_two(width
) * 4;
9391 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9402 cntl
|= CURSOR_ENABLE
|
9403 CURSOR_GAMMA_ENABLE
|
9404 CURSOR_FORMAT_ARGB
|
9405 CURSOR_STRIDE(stride
);
9407 size
= (height
<< 12) | width
;
9410 if (intel_crtc
->cursor_cntl
!= 0 &&
9411 (intel_crtc
->cursor_base
!= base
||
9412 intel_crtc
->cursor_size
!= size
||
9413 intel_crtc
->cursor_cntl
!= cntl
)) {
9414 /* On these chipsets we can only modify the base/size/stride
9415 * whilst the cursor is disabled.
9417 I915_WRITE(_CURACNTR
, 0);
9418 POSTING_READ(_CURACNTR
);
9419 intel_crtc
->cursor_cntl
= 0;
9422 if (intel_crtc
->cursor_base
!= base
) {
9423 I915_WRITE(_CURABASE
, base
);
9424 intel_crtc
->cursor_base
= base
;
9427 if (intel_crtc
->cursor_size
!= size
) {
9428 I915_WRITE(CURSIZE
, size
);
9429 intel_crtc
->cursor_size
= size
;
9432 if (intel_crtc
->cursor_cntl
!= cntl
) {
9433 I915_WRITE(_CURACNTR
, cntl
);
9434 POSTING_READ(_CURACNTR
);
9435 intel_crtc
->cursor_cntl
= cntl
;
9439 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
9441 struct drm_device
*dev
= crtc
->dev
;
9442 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9443 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9444 int pipe
= intel_crtc
->pipe
;
9449 cntl
= MCURSOR_GAMMA_ENABLE
;
9450 switch (intel_crtc
->base
.cursor
->state
->crtc_w
) {
9452 cntl
|= CURSOR_MODE_64_ARGB_AX
;
9455 cntl
|= CURSOR_MODE_128_ARGB_AX
;
9458 cntl
|= CURSOR_MODE_256_ARGB_AX
;
9461 MISSING_CASE(intel_crtc
->base
.cursor
->state
->crtc_w
);
9464 cntl
|= pipe
<< 28; /* Connect to correct pipe */
9466 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
9467 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
9470 if (crtc
->cursor
->state
->rotation
== BIT(DRM_ROTATE_180
))
9471 cntl
|= CURSOR_ROTATE_180
;
9473 if (intel_crtc
->cursor_cntl
!= cntl
) {
9474 I915_WRITE(CURCNTR(pipe
), cntl
);
9475 POSTING_READ(CURCNTR(pipe
));
9476 intel_crtc
->cursor_cntl
= cntl
;
9479 /* and commit changes on next vblank */
9480 I915_WRITE(CURBASE(pipe
), base
);
9481 POSTING_READ(CURBASE(pipe
));
9483 intel_crtc
->cursor_base
= base
;
9486 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9487 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
9490 struct drm_device
*dev
= crtc
->dev
;
9491 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9492 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9493 int pipe
= intel_crtc
->pipe
;
9494 int x
= crtc
->cursor_x
;
9495 int y
= crtc
->cursor_y
;
9496 u32 base
= 0, pos
= 0;
9499 base
= intel_crtc
->cursor_addr
;
9501 if (x
>= intel_crtc
->config
->pipe_src_w
)
9504 if (y
>= intel_crtc
->config
->pipe_src_h
)
9508 if (x
+ intel_crtc
->base
.cursor
->state
->crtc_w
<= 0)
9511 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
9514 pos
|= x
<< CURSOR_X_SHIFT
;
9517 if (y
+ intel_crtc
->base
.cursor
->state
->crtc_h
<= 0)
9520 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
9523 pos
|= y
<< CURSOR_Y_SHIFT
;
9525 if (base
== 0 && intel_crtc
->cursor_base
== 0)
9528 I915_WRITE(CURPOS(pipe
), pos
);
9530 /* ILK+ do this automagically */
9531 if (HAS_GMCH_DISPLAY(dev
) &&
9532 crtc
->cursor
->state
->rotation
== BIT(DRM_ROTATE_180
)) {
9533 base
+= (intel_crtc
->base
.cursor
->state
->crtc_h
*
9534 intel_crtc
->base
.cursor
->state
->crtc_w
- 1) * 4;
9537 if (IS_845G(dev
) || IS_I865G(dev
))
9538 i845_update_cursor(crtc
, base
);
9540 i9xx_update_cursor(crtc
, base
);
9543 static bool cursor_size_ok(struct drm_device
*dev
,
9544 uint32_t width
, uint32_t height
)
9546 if (width
== 0 || height
== 0)
9550 * 845g/865g are special in that they are only limited by
9551 * the width of their cursors, the height is arbitrary up to
9552 * the precision of the register. Everything else requires
9553 * square cursors, limited to a few power-of-two sizes.
9555 if (IS_845G(dev
) || IS_I865G(dev
)) {
9556 if ((width
& 63) != 0)
9559 if (width
> (IS_845G(dev
) ? 64 : 512))
9565 switch (width
| height
) {
9580 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
9581 u16
*blue
, uint32_t start
, uint32_t size
)
9583 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
9584 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9586 for (i
= start
; i
< end
; i
++) {
9587 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
9588 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
9589 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
9592 intel_crtc_load_lut(crtc
);
9595 /* VESA 640x480x72Hz mode to set on the pipe */
9596 static struct drm_display_mode load_detect_mode
= {
9597 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
9598 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
9601 struct drm_framebuffer
*
9602 __intel_framebuffer_create(struct drm_device
*dev
,
9603 struct drm_mode_fb_cmd2
*mode_cmd
,
9604 struct drm_i915_gem_object
*obj
)
9606 struct intel_framebuffer
*intel_fb
;
9609 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
9611 drm_gem_object_unreference(&obj
->base
);
9612 return ERR_PTR(-ENOMEM
);
9615 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
9619 return &intel_fb
->base
;
9621 drm_gem_object_unreference(&obj
->base
);
9624 return ERR_PTR(ret
);
9627 static struct drm_framebuffer
*
9628 intel_framebuffer_create(struct drm_device
*dev
,
9629 struct drm_mode_fb_cmd2
*mode_cmd
,
9630 struct drm_i915_gem_object
*obj
)
9632 struct drm_framebuffer
*fb
;
9635 ret
= i915_mutex_lock_interruptible(dev
);
9637 return ERR_PTR(ret
);
9638 fb
= __intel_framebuffer_create(dev
, mode_cmd
, obj
);
9639 mutex_unlock(&dev
->struct_mutex
);
9645 intel_framebuffer_pitch_for_width(int width
, int bpp
)
9647 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
9648 return ALIGN(pitch
, 64);
9652 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
9654 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
9655 return PAGE_ALIGN(pitch
* mode
->vdisplay
);
9658 static struct drm_framebuffer
*
9659 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
9660 struct drm_display_mode
*mode
,
9663 struct drm_i915_gem_object
*obj
;
9664 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
9666 obj
= i915_gem_alloc_object(dev
,
9667 intel_framebuffer_size_for_mode(mode
, bpp
));
9669 return ERR_PTR(-ENOMEM
);
9671 mode_cmd
.width
= mode
->hdisplay
;
9672 mode_cmd
.height
= mode
->vdisplay
;
9673 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
9675 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
9677 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
9680 static struct drm_framebuffer
*
9681 mode_fits_in_fbdev(struct drm_device
*dev
,
9682 struct drm_display_mode
*mode
)
9684 #ifdef CONFIG_DRM_I915_FBDEV
9685 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9686 struct drm_i915_gem_object
*obj
;
9687 struct drm_framebuffer
*fb
;
9689 if (!dev_priv
->fbdev
)
9692 if (!dev_priv
->fbdev
->fb
)
9695 obj
= dev_priv
->fbdev
->fb
->obj
;
9698 fb
= &dev_priv
->fbdev
->fb
->base
;
9699 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
9700 fb
->bits_per_pixel
))
9703 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
9712 static int intel_modeset_setup_plane_state(struct drm_atomic_state
*state
,
9713 struct drm_crtc
*crtc
,
9714 struct drm_display_mode
*mode
,
9715 struct drm_framebuffer
*fb
,
9718 struct drm_plane_state
*plane_state
;
9719 int hdisplay
, vdisplay
;
9722 plane_state
= drm_atomic_get_plane_state(state
, crtc
->primary
);
9723 if (IS_ERR(plane_state
))
9724 return PTR_ERR(plane_state
);
9727 drm_crtc_get_hv_timing(mode
, &hdisplay
, &vdisplay
);
9729 hdisplay
= vdisplay
= 0;
9731 ret
= drm_atomic_set_crtc_for_plane(plane_state
, fb
? crtc
: NULL
);
9734 drm_atomic_set_fb_for_plane(plane_state
, fb
);
9735 plane_state
->crtc_x
= 0;
9736 plane_state
->crtc_y
= 0;
9737 plane_state
->crtc_w
= hdisplay
;
9738 plane_state
->crtc_h
= vdisplay
;
9739 plane_state
->src_x
= x
<< 16;
9740 plane_state
->src_y
= y
<< 16;
9741 plane_state
->src_w
= hdisplay
<< 16;
9742 plane_state
->src_h
= vdisplay
<< 16;
9747 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
9748 struct drm_display_mode
*mode
,
9749 struct intel_load_detect_pipe
*old
,
9750 struct drm_modeset_acquire_ctx
*ctx
)
9752 struct intel_crtc
*intel_crtc
;
9753 struct intel_encoder
*intel_encoder
=
9754 intel_attached_encoder(connector
);
9755 struct drm_crtc
*possible_crtc
;
9756 struct drm_encoder
*encoder
= &intel_encoder
->base
;
9757 struct drm_crtc
*crtc
= NULL
;
9758 struct drm_device
*dev
= encoder
->dev
;
9759 struct drm_framebuffer
*fb
;
9760 struct drm_mode_config
*config
= &dev
->mode_config
;
9761 struct drm_atomic_state
*state
= NULL
;
9762 struct drm_connector_state
*connector_state
;
9763 struct intel_crtc_state
*crtc_state
;
9766 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9767 connector
->base
.id
, connector
->name
,
9768 encoder
->base
.id
, encoder
->name
);
9771 ret
= drm_modeset_lock(&config
->connection_mutex
, ctx
);
9776 * Algorithm gets a little messy:
9778 * - if the connector already has an assigned crtc, use it (but make
9779 * sure it's on first)
9781 * - try to find the first unused crtc that can drive this connector,
9782 * and use that if we find one
9785 /* See if we already have a CRTC for this connector */
9786 if (encoder
->crtc
) {
9787 crtc
= encoder
->crtc
;
9789 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
9792 ret
= drm_modeset_lock(&crtc
->primary
->mutex
, ctx
);
9796 old
->dpms_mode
= connector
->dpms
;
9797 old
->load_detect_temp
= false;
9799 /* Make sure the crtc and connector are running */
9800 if (connector
->dpms
!= DRM_MODE_DPMS_ON
)
9801 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
9806 /* Find an unused one (if possible) */
9807 for_each_crtc(dev
, possible_crtc
) {
9809 if (!(encoder
->possible_crtcs
& (1 << i
)))
9811 if (possible_crtc
->state
->enable
)
9813 /* This can occur when applying the pipe A quirk on resume. */
9814 if (to_intel_crtc(possible_crtc
)->new_enabled
)
9817 crtc
= possible_crtc
;
9822 * If we didn't find an unused CRTC, don't use any.
9825 DRM_DEBUG_KMS("no pipe available for load-detect\n");
9829 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
9832 ret
= drm_modeset_lock(&crtc
->primary
->mutex
, ctx
);
9835 intel_encoder
->new_crtc
= to_intel_crtc(crtc
);
9836 to_intel_connector(connector
)->new_encoder
= intel_encoder
;
9838 intel_crtc
= to_intel_crtc(crtc
);
9839 intel_crtc
->new_enabled
= true;
9840 old
->dpms_mode
= connector
->dpms
;
9841 old
->load_detect_temp
= true;
9842 old
->release_fb
= NULL
;
9844 state
= drm_atomic_state_alloc(dev
);
9848 state
->acquire_ctx
= ctx
;
9850 connector_state
= drm_atomic_get_connector_state(state
, connector
);
9851 if (IS_ERR(connector_state
)) {
9852 ret
= PTR_ERR(connector_state
);
9856 connector_state
->crtc
= crtc
;
9857 connector_state
->best_encoder
= &intel_encoder
->base
;
9859 crtc_state
= intel_atomic_get_crtc_state(state
, intel_crtc
);
9860 if (IS_ERR(crtc_state
)) {
9861 ret
= PTR_ERR(crtc_state
);
9865 crtc_state
->base
.active
= crtc_state
->base
.enable
= true;
9868 mode
= &load_detect_mode
;
9870 /* We need a framebuffer large enough to accommodate all accesses
9871 * that the plane may generate whilst we perform load detection.
9872 * We can not rely on the fbcon either being present (we get called
9873 * during its initialisation to detect all boot displays, or it may
9874 * not even exist) or that it is large enough to satisfy the
9877 fb
= mode_fits_in_fbdev(dev
, mode
);
9879 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
9880 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
9881 old
->release_fb
= fb
;
9883 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
9885 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
9889 ret
= intel_modeset_setup_plane_state(state
, crtc
, mode
, fb
, 0, 0);
9893 drm_mode_copy(&crtc_state
->base
.mode
, mode
);
9895 if (intel_set_mode(crtc
, state
)) {
9896 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
9897 if (old
->release_fb
)
9898 old
->release_fb
->funcs
->destroy(old
->release_fb
);
9901 crtc
->primary
->crtc
= crtc
;
9903 /* let the connector get through one full cycle before testing */
9904 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
9908 intel_crtc
->new_enabled
= crtc
->state
->enable
;
9910 drm_atomic_state_free(state
);
9913 if (ret
== -EDEADLK
) {
9914 drm_modeset_backoff(ctx
);
9921 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
9922 struct intel_load_detect_pipe
*old
,
9923 struct drm_modeset_acquire_ctx
*ctx
)
9925 struct drm_device
*dev
= connector
->dev
;
9926 struct intel_encoder
*intel_encoder
=
9927 intel_attached_encoder(connector
);
9928 struct drm_encoder
*encoder
= &intel_encoder
->base
;
9929 struct drm_crtc
*crtc
= encoder
->crtc
;
9930 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9931 struct drm_atomic_state
*state
;
9932 struct drm_connector_state
*connector_state
;
9933 struct intel_crtc_state
*crtc_state
;
9936 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9937 connector
->base
.id
, connector
->name
,
9938 encoder
->base
.id
, encoder
->name
);
9940 if (old
->load_detect_temp
) {
9941 state
= drm_atomic_state_alloc(dev
);
9945 state
->acquire_ctx
= ctx
;
9947 connector_state
= drm_atomic_get_connector_state(state
, connector
);
9948 if (IS_ERR(connector_state
))
9951 crtc_state
= intel_atomic_get_crtc_state(state
, intel_crtc
);
9952 if (IS_ERR(crtc_state
))
9955 to_intel_connector(connector
)->new_encoder
= NULL
;
9956 intel_encoder
->new_crtc
= NULL
;
9957 intel_crtc
->new_enabled
= false;
9959 connector_state
->best_encoder
= NULL
;
9960 connector_state
->crtc
= NULL
;
9962 crtc_state
->base
.enable
= crtc_state
->base
.active
= false;
9964 ret
= intel_modeset_setup_plane_state(state
, crtc
, NULL
, NULL
,
9969 ret
= intel_set_mode(crtc
, state
);
9973 if (old
->release_fb
) {
9974 drm_framebuffer_unregister_private(old
->release_fb
);
9975 drm_framebuffer_unreference(old
->release_fb
);
9981 /* Switch crtc and encoder back off if necessary */
9982 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
)
9983 connector
->funcs
->dpms(connector
, old
->dpms_mode
);
9987 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
9988 drm_atomic_state_free(state
);
9991 static int i9xx_pll_refclk(struct drm_device
*dev
,
9992 const struct intel_crtc_state
*pipe_config
)
9994 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9995 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
9997 if ((dpll
& PLL_REF_INPUT_MASK
) == PLLB_REF_INPUT_SPREADSPECTRUMIN
)
9998 return dev_priv
->vbt
.lvds_ssc_freq
;
9999 else if (HAS_PCH_SPLIT(dev
))
10001 else if (!IS_GEN2(dev
))
10007 /* Returns the clock of the currently programmed mode of the given pipe. */
10008 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
10009 struct intel_crtc_state
*pipe_config
)
10011 struct drm_device
*dev
= crtc
->base
.dev
;
10012 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10013 int pipe
= pipe_config
->cpu_transcoder
;
10014 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
10016 intel_clock_t clock
;
10017 int refclk
= i9xx_pll_refclk(dev
, pipe_config
);
10019 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
10020 fp
= pipe_config
->dpll_hw_state
.fp0
;
10022 fp
= pipe_config
->dpll_hw_state
.fp1
;
10024 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
10025 if (IS_PINEVIEW(dev
)) {
10026 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
10027 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
10029 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
10030 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
10033 if (!IS_GEN2(dev
)) {
10034 if (IS_PINEVIEW(dev
))
10035 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
10036 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
10038 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
10039 DPLL_FPA01_P1_POST_DIV_SHIFT
);
10041 switch (dpll
& DPLL_MODE_MASK
) {
10042 case DPLLB_MODE_DAC_SERIAL
:
10043 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
10046 case DPLLB_MODE_LVDS
:
10047 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
10051 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10052 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
10056 if (IS_PINEVIEW(dev
))
10057 pineview_clock(refclk
, &clock
);
10059 i9xx_clock(refclk
, &clock
);
10061 u32 lvds
= IS_I830(dev
) ? 0 : I915_READ(LVDS
);
10062 bool is_lvds
= (pipe
== 1) && (lvds
& LVDS_PORT_EN
);
10065 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
10066 DPLL_FPA01_P1_POST_DIV_SHIFT
);
10068 if (lvds
& LVDS_CLKB_POWER_UP
)
10073 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
10076 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
10077 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
10079 if (dpll
& PLL_P2_DIVIDE_BY_4
)
10085 i9xx_clock(refclk
, &clock
);
10089 * This value includes pixel_multiplier. We will use
10090 * port_clock to compute adjusted_mode.crtc_clock in the
10091 * encoder's get_config() function.
10093 pipe_config
->port_clock
= clock
.dot
;
10096 int intel_dotclock_calculate(int link_freq
,
10097 const struct intel_link_m_n
*m_n
)
10100 * The calculation for the data clock is:
10101 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10102 * But we want to avoid losing precison if possible, so:
10103 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10105 * and the link clock is simpler:
10106 * link_clock = (m * link_clock) / n
10112 return div_u64((u64
)m_n
->link_m
* link_freq
, m_n
->link_n
);
10115 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
10116 struct intel_crtc_state
*pipe_config
)
10118 struct drm_device
*dev
= crtc
->base
.dev
;
10120 /* read out port_clock from the DPLL */
10121 i9xx_crtc_clock_get(crtc
, pipe_config
);
10124 * This value does not include pixel_multiplier.
10125 * We will check that port_clock and adjusted_mode.crtc_clock
10126 * agree once we know their relationship in the encoder's
10127 * get_config() function.
10129 pipe_config
->base
.adjusted_mode
.crtc_clock
=
10130 intel_dotclock_calculate(intel_fdi_link_freq(dev
) * 10000,
10131 &pipe_config
->fdi_m_n
);
10134 /** Returns the currently programmed mode of the given pipe. */
10135 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
10136 struct drm_crtc
*crtc
)
10138 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10139 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10140 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
10141 struct drm_display_mode
*mode
;
10142 struct intel_crtc_state pipe_config
;
10143 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
10144 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
10145 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
10146 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
10147 enum pipe pipe
= intel_crtc
->pipe
;
10149 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
10154 * Construct a pipe_config sufficient for getting the clock info
10155 * back out of crtc_clock_get.
10157 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10158 * to use a real value here instead.
10160 pipe_config
.cpu_transcoder
= (enum transcoder
) pipe
;
10161 pipe_config
.pixel_multiplier
= 1;
10162 pipe_config
.dpll_hw_state
.dpll
= I915_READ(DPLL(pipe
));
10163 pipe_config
.dpll_hw_state
.fp0
= I915_READ(FP0(pipe
));
10164 pipe_config
.dpll_hw_state
.fp1
= I915_READ(FP1(pipe
));
10165 i9xx_crtc_clock_get(intel_crtc
, &pipe_config
);
10167 mode
->clock
= pipe_config
.port_clock
/ pipe_config
.pixel_multiplier
;
10168 mode
->hdisplay
= (htot
& 0xffff) + 1;
10169 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
10170 mode
->hsync_start
= (hsync
& 0xffff) + 1;
10171 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
10172 mode
->vdisplay
= (vtot
& 0xffff) + 1;
10173 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
10174 mode
->vsync_start
= (vsync
& 0xffff) + 1;
10175 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
10177 drm_mode_set_name(mode
);
10182 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
10184 struct drm_device
*dev
= crtc
->dev
;
10185 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10186 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10188 if (!HAS_GMCH_DISPLAY(dev
))
10191 if (!dev_priv
->lvds_downclock_avail
)
10195 * Since this is called by a timer, we should never get here in
10198 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
10199 int pipe
= intel_crtc
->pipe
;
10200 int dpll_reg
= DPLL(pipe
);
10203 DRM_DEBUG_DRIVER("downclocking LVDS\n");
10205 assert_panel_unlocked(dev_priv
, pipe
);
10207 dpll
= I915_READ(dpll_reg
);
10208 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
10209 I915_WRITE(dpll_reg
, dpll
);
10210 intel_wait_for_vblank(dev
, pipe
);
10211 dpll
= I915_READ(dpll_reg
);
10212 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
10213 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
10218 void intel_mark_busy(struct drm_device
*dev
)
10220 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10222 if (dev_priv
->mm
.busy
)
10225 intel_runtime_pm_get(dev_priv
);
10226 i915_update_gfx_val(dev_priv
);
10227 if (INTEL_INFO(dev
)->gen
>= 6)
10228 gen6_rps_busy(dev_priv
);
10229 dev_priv
->mm
.busy
= true;
10232 void intel_mark_idle(struct drm_device
*dev
)
10234 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10235 struct drm_crtc
*crtc
;
10237 if (!dev_priv
->mm
.busy
)
10240 dev_priv
->mm
.busy
= false;
10242 for_each_crtc(dev
, crtc
) {
10243 if (!crtc
->primary
->fb
)
10246 intel_decrease_pllclock(crtc
);
10249 if (INTEL_INFO(dev
)->gen
>= 6)
10250 gen6_rps_idle(dev
->dev_private
);
10252 intel_runtime_pm_put(dev_priv
);
10255 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
10257 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10258 struct drm_device
*dev
= crtc
->dev
;
10259 struct intel_unpin_work
*work
;
10261 spin_lock_irq(&dev
->event_lock
);
10262 work
= intel_crtc
->unpin_work
;
10263 intel_crtc
->unpin_work
= NULL
;
10264 spin_unlock_irq(&dev
->event_lock
);
10267 cancel_work_sync(&work
->work
);
10271 drm_crtc_cleanup(crtc
);
10276 static void intel_unpin_work_fn(struct work_struct
*__work
)
10278 struct intel_unpin_work
*work
=
10279 container_of(__work
, struct intel_unpin_work
, work
);
10280 struct drm_device
*dev
= work
->crtc
->dev
;
10281 enum pipe pipe
= to_intel_crtc(work
->crtc
)->pipe
;
10283 mutex_lock(&dev
->struct_mutex
);
10284 intel_unpin_fb_obj(work
->old_fb
, work
->crtc
->primary
->state
);
10285 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
10287 intel_fbc_update(dev
);
10289 if (work
->flip_queued_req
)
10290 i915_gem_request_assign(&work
->flip_queued_req
, NULL
);
10291 mutex_unlock(&dev
->struct_mutex
);
10293 intel_frontbuffer_flip_complete(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
10294 drm_framebuffer_unreference(work
->old_fb
);
10296 BUG_ON(atomic_read(&to_intel_crtc(work
->crtc
)->unpin_work_count
) == 0);
10297 atomic_dec(&to_intel_crtc(work
->crtc
)->unpin_work_count
);
10302 static void do_intel_finish_page_flip(struct drm_device
*dev
,
10303 struct drm_crtc
*crtc
)
10305 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10306 struct intel_unpin_work
*work
;
10307 unsigned long flags
;
10309 /* Ignore early vblank irqs */
10310 if (intel_crtc
== NULL
)
10314 * This is called both by irq handlers and the reset code (to complete
10315 * lost pageflips) so needs the full irqsave spinlocks.
10317 spin_lock_irqsave(&dev
->event_lock
, flags
);
10318 work
= intel_crtc
->unpin_work
;
10320 /* Ensure we don't miss a work->pending update ... */
10323 if (work
== NULL
|| atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
10324 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
10328 page_flip_completed(intel_crtc
);
10330 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
10333 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
10335 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10336 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
10338 do_intel_finish_page_flip(dev
, crtc
);
10341 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
10343 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10344 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
10346 do_intel_finish_page_flip(dev
, crtc
);
10349 /* Is 'a' after or equal to 'b'? */
10350 static bool g4x_flip_count_after_eq(u32 a
, u32 b
)
10352 return !((a
- b
) & 0x80000000);
10355 static bool page_flip_finished(struct intel_crtc
*crtc
)
10357 struct drm_device
*dev
= crtc
->base
.dev
;
10358 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10360 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
10361 crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
10365 * The relevant registers doen't exist on pre-ctg.
10366 * As the flip done interrupt doesn't trigger for mmio
10367 * flips on gmch platforms, a flip count check isn't
10368 * really needed there. But since ctg has the registers,
10369 * include it in the check anyway.
10371 if (INTEL_INFO(dev
)->gen
< 5 && !IS_G4X(dev
))
10375 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10376 * used the same base address. In that case the mmio flip might
10377 * have completed, but the CS hasn't even executed the flip yet.
10379 * A flip count check isn't enough as the CS might have updated
10380 * the base address just after start of vblank, but before we
10381 * managed to process the interrupt. This means we'd complete the
10382 * CS flip too soon.
10384 * Combining both checks should get us a good enough result. It may
10385 * still happen that the CS flip has been executed, but has not
10386 * yet actually completed. But in case the base address is the same
10387 * anyway, we don't really care.
10389 return (I915_READ(DSPSURFLIVE(crtc
->plane
)) & ~0xfff) ==
10390 crtc
->unpin_work
->gtt_offset
&&
10391 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc
->pipe
)),
10392 crtc
->unpin_work
->flip_count
);
10395 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
10397 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10398 struct intel_crtc
*intel_crtc
=
10399 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
10400 unsigned long flags
;
10404 * This is called both by irq handlers and the reset code (to complete
10405 * lost pageflips) so needs the full irqsave spinlocks.
10407 * NB: An MMIO update of the plane base pointer will also
10408 * generate a page-flip completion irq, i.e. every modeset
10409 * is also accompanied by a spurious intel_prepare_page_flip().
10411 spin_lock_irqsave(&dev
->event_lock
, flags
);
10412 if (intel_crtc
->unpin_work
&& page_flip_finished(intel_crtc
))
10413 atomic_inc_not_zero(&intel_crtc
->unpin_work
->pending
);
10414 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
10417 static inline void intel_mark_page_flip_active(struct intel_crtc
*intel_crtc
)
10419 /* Ensure that the work item is consistent when activating it ... */
10421 atomic_set(&intel_crtc
->unpin_work
->pending
, INTEL_FLIP_PENDING
);
10422 /* and that it is marked active as soon as the irq could fire. */
10426 static int intel_gen2_queue_flip(struct drm_device
*dev
,
10427 struct drm_crtc
*crtc
,
10428 struct drm_framebuffer
*fb
,
10429 struct drm_i915_gem_object
*obj
,
10430 struct intel_engine_cs
*ring
,
10433 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10437 ret
= intel_ring_begin(ring
, 6);
10441 /* Can't queue multiple flips, so wait for the previous
10442 * one to finish before executing the next.
10444 if (intel_crtc
->plane
)
10445 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
10447 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
10448 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
10449 intel_ring_emit(ring
, MI_NOOP
);
10450 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
10451 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
10452 intel_ring_emit(ring
, fb
->pitches
[0]);
10453 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
10454 intel_ring_emit(ring
, 0); /* aux display base address, unused */
10456 intel_mark_page_flip_active(intel_crtc
);
10457 __intel_ring_advance(ring
);
10461 static int intel_gen3_queue_flip(struct drm_device
*dev
,
10462 struct drm_crtc
*crtc
,
10463 struct drm_framebuffer
*fb
,
10464 struct drm_i915_gem_object
*obj
,
10465 struct intel_engine_cs
*ring
,
10468 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10472 ret
= intel_ring_begin(ring
, 6);
10476 if (intel_crtc
->plane
)
10477 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
10479 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
10480 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
10481 intel_ring_emit(ring
, MI_NOOP
);
10482 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
10483 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
10484 intel_ring_emit(ring
, fb
->pitches
[0]);
10485 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
10486 intel_ring_emit(ring
, MI_NOOP
);
10488 intel_mark_page_flip_active(intel_crtc
);
10489 __intel_ring_advance(ring
);
10493 static int intel_gen4_queue_flip(struct drm_device
*dev
,
10494 struct drm_crtc
*crtc
,
10495 struct drm_framebuffer
*fb
,
10496 struct drm_i915_gem_object
*obj
,
10497 struct intel_engine_cs
*ring
,
10500 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10501 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10502 uint32_t pf
, pipesrc
;
10505 ret
= intel_ring_begin(ring
, 4);
10509 /* i965+ uses the linear or tiled offsets from the
10510 * Display Registers (which do not change across a page-flip)
10511 * so we need only reprogram the base address.
10513 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
10514 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
10515 intel_ring_emit(ring
, fb
->pitches
[0]);
10516 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
|
10519 /* XXX Enabling the panel-fitter across page-flip is so far
10520 * untested on non-native modes, so ignore it for now.
10521 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10524 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
10525 intel_ring_emit(ring
, pf
| pipesrc
);
10527 intel_mark_page_flip_active(intel_crtc
);
10528 __intel_ring_advance(ring
);
10532 static int intel_gen6_queue_flip(struct drm_device
*dev
,
10533 struct drm_crtc
*crtc
,
10534 struct drm_framebuffer
*fb
,
10535 struct drm_i915_gem_object
*obj
,
10536 struct intel_engine_cs
*ring
,
10539 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10540 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10541 uint32_t pf
, pipesrc
;
10544 ret
= intel_ring_begin(ring
, 4);
10548 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
10549 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
10550 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
10551 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
10553 /* Contrary to the suggestions in the documentation,
10554 * "Enable Panel Fitter" does not seem to be required when page
10555 * flipping with a non-native mode, and worse causes a normal
10557 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10560 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
10561 intel_ring_emit(ring
, pf
| pipesrc
);
10563 intel_mark_page_flip_active(intel_crtc
);
10564 __intel_ring_advance(ring
);
10568 static int intel_gen7_queue_flip(struct drm_device
*dev
,
10569 struct drm_crtc
*crtc
,
10570 struct drm_framebuffer
*fb
,
10571 struct drm_i915_gem_object
*obj
,
10572 struct intel_engine_cs
*ring
,
10575 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10576 uint32_t plane_bit
= 0;
10579 switch (intel_crtc
->plane
) {
10581 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
10584 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
10587 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
10590 WARN_ONCE(1, "unknown plane in flip command\n");
10595 if (ring
->id
== RCS
) {
10598 * On Gen 8, SRM is now taking an extra dword to accommodate
10599 * 48bits addresses, and we need a NOOP for the batch size to
10607 * BSpec MI_DISPLAY_FLIP for IVB:
10608 * "The full packet must be contained within the same cache line."
10610 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10611 * cacheline, if we ever start emitting more commands before
10612 * the MI_DISPLAY_FLIP we may need to first emit everything else,
10613 * then do the cacheline alignment, and finally emit the
10616 ret
= intel_ring_cacheline_align(ring
);
10620 ret
= intel_ring_begin(ring
, len
);
10624 /* Unmask the flip-done completion message. Note that the bspec says that
10625 * we should do this for both the BCS and RCS, and that we must not unmask
10626 * more than one flip event at any time (or ensure that one flip message
10627 * can be sent by waiting for flip-done prior to queueing new flips).
10628 * Experimentation says that BCS works despite DERRMR masking all
10629 * flip-done completion events and that unmasking all planes at once
10630 * for the RCS also doesn't appear to drop events. Setting the DERRMR
10631 * to zero does lead to lockups within MI_DISPLAY_FLIP.
10633 if (ring
->id
== RCS
) {
10634 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
10635 intel_ring_emit(ring
, DERRMR
);
10636 intel_ring_emit(ring
, ~(DERRMR_PIPEA_PRI_FLIP_DONE
|
10637 DERRMR_PIPEB_PRI_FLIP_DONE
|
10638 DERRMR_PIPEC_PRI_FLIP_DONE
));
10640 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM_GEN8(1) |
10641 MI_SRM_LRM_GLOBAL_GTT
);
10643 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM(1) |
10644 MI_SRM_LRM_GLOBAL_GTT
);
10645 intel_ring_emit(ring
, DERRMR
);
10646 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
+ 256);
10647 if (IS_GEN8(dev
)) {
10648 intel_ring_emit(ring
, 0);
10649 intel_ring_emit(ring
, MI_NOOP
);
10653 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
10654 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
10655 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
10656 intel_ring_emit(ring
, (MI_NOOP
));
10658 intel_mark_page_flip_active(intel_crtc
);
10659 __intel_ring_advance(ring
);
10663 static bool use_mmio_flip(struct intel_engine_cs
*ring
,
10664 struct drm_i915_gem_object
*obj
)
10667 * This is not being used for older platforms, because
10668 * non-availability of flip done interrupt forces us to use
10669 * CS flips. Older platforms derive flip done using some clever
10670 * tricks involving the flip_pending status bits and vblank irqs.
10671 * So using MMIO flips there would disrupt this mechanism.
10677 if (INTEL_INFO(ring
->dev
)->gen
< 5)
10680 if (i915
.use_mmio_flip
< 0)
10682 else if (i915
.use_mmio_flip
> 0)
10684 else if (i915
.enable_execlists
)
10687 return ring
!= i915_gem_request_get_ring(obj
->last_read_req
);
10690 static void skl_do_mmio_flip(struct intel_crtc
*intel_crtc
)
10692 struct drm_device
*dev
= intel_crtc
->base
.dev
;
10693 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10694 struct drm_framebuffer
*fb
= intel_crtc
->base
.primary
->fb
;
10695 const enum pipe pipe
= intel_crtc
->pipe
;
10698 ctl
= I915_READ(PLANE_CTL(pipe
, 0));
10699 ctl
&= ~PLANE_CTL_TILED_MASK
;
10700 switch (fb
->modifier
[0]) {
10701 case DRM_FORMAT_MOD_NONE
:
10703 case I915_FORMAT_MOD_X_TILED
:
10704 ctl
|= PLANE_CTL_TILED_X
;
10706 case I915_FORMAT_MOD_Y_TILED
:
10707 ctl
|= PLANE_CTL_TILED_Y
;
10709 case I915_FORMAT_MOD_Yf_TILED
:
10710 ctl
|= PLANE_CTL_TILED_YF
;
10713 MISSING_CASE(fb
->modifier
[0]);
10717 * The stride is either expressed as a multiple of 64 bytes chunks for
10718 * linear buffers or in number of tiles for tiled buffers.
10720 stride
= fb
->pitches
[0] /
10721 intel_fb_stride_alignment(dev
, fb
->modifier
[0],
10725 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10726 * PLANE_SURF updates, the update is then guaranteed to be atomic.
10728 I915_WRITE(PLANE_CTL(pipe
, 0), ctl
);
10729 I915_WRITE(PLANE_STRIDE(pipe
, 0), stride
);
10731 I915_WRITE(PLANE_SURF(pipe
, 0), intel_crtc
->unpin_work
->gtt_offset
);
10732 POSTING_READ(PLANE_SURF(pipe
, 0));
10735 static void ilk_do_mmio_flip(struct intel_crtc
*intel_crtc
)
10737 struct drm_device
*dev
= intel_crtc
->base
.dev
;
10738 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10739 struct intel_framebuffer
*intel_fb
=
10740 to_intel_framebuffer(intel_crtc
->base
.primary
->fb
);
10741 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
10745 reg
= DSPCNTR(intel_crtc
->plane
);
10746 dspcntr
= I915_READ(reg
);
10748 if (obj
->tiling_mode
!= I915_TILING_NONE
)
10749 dspcntr
|= DISPPLANE_TILED
;
10751 dspcntr
&= ~DISPPLANE_TILED
;
10753 I915_WRITE(reg
, dspcntr
);
10755 I915_WRITE(DSPSURF(intel_crtc
->plane
),
10756 intel_crtc
->unpin_work
->gtt_offset
);
10757 POSTING_READ(DSPSURF(intel_crtc
->plane
));
10762 * XXX: This is the temporary way to update the plane registers until we get
10763 * around to using the usual plane update functions for MMIO flips
10765 static void intel_do_mmio_flip(struct intel_crtc
*intel_crtc
)
10767 struct drm_device
*dev
= intel_crtc
->base
.dev
;
10768 bool atomic_update
;
10769 u32 start_vbl_count
;
10771 intel_mark_page_flip_active(intel_crtc
);
10773 atomic_update
= intel_pipe_update_start(intel_crtc
, &start_vbl_count
);
10775 if (INTEL_INFO(dev
)->gen
>= 9)
10776 skl_do_mmio_flip(intel_crtc
);
10778 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10779 ilk_do_mmio_flip(intel_crtc
);
10782 intel_pipe_update_end(intel_crtc
, start_vbl_count
);
10785 static void intel_mmio_flip_work_func(struct work_struct
*work
)
10787 struct intel_mmio_flip
*mmio_flip
=
10788 container_of(work
, struct intel_mmio_flip
, work
);
10791 WARN_ON(__i915_wait_request(mmio_flip
->rq
,
10792 mmio_flip
->crtc
->reset_counter
,
10793 false, NULL
, NULL
));
10795 intel_do_mmio_flip(mmio_flip
->crtc
);
10797 i915_gem_request_unreference__unlocked(mmio_flip
->rq
);
10801 static int intel_queue_mmio_flip(struct drm_device
*dev
,
10802 struct drm_crtc
*crtc
,
10803 struct drm_framebuffer
*fb
,
10804 struct drm_i915_gem_object
*obj
,
10805 struct intel_engine_cs
*ring
,
10808 struct intel_mmio_flip
*mmio_flip
;
10810 mmio_flip
= kmalloc(sizeof(*mmio_flip
), GFP_KERNEL
);
10811 if (mmio_flip
== NULL
)
10814 mmio_flip
->rq
= i915_gem_request_reference(obj
->last_write_req
);
10815 mmio_flip
->crtc
= to_intel_crtc(crtc
);
10817 INIT_WORK(&mmio_flip
->work
, intel_mmio_flip_work_func
);
10818 schedule_work(&mmio_flip
->work
);
10823 static int intel_default_queue_flip(struct drm_device
*dev
,
10824 struct drm_crtc
*crtc
,
10825 struct drm_framebuffer
*fb
,
10826 struct drm_i915_gem_object
*obj
,
10827 struct intel_engine_cs
*ring
,
10833 static bool __intel_pageflip_stall_check(struct drm_device
*dev
,
10834 struct drm_crtc
*crtc
)
10836 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10837 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10838 struct intel_unpin_work
*work
= intel_crtc
->unpin_work
;
10841 if (atomic_read(&work
->pending
) >= INTEL_FLIP_COMPLETE
)
10844 if (!work
->enable_stall_check
)
10847 if (work
->flip_ready_vblank
== 0) {
10848 if (work
->flip_queued_req
&&
10849 !i915_gem_request_completed(work
->flip_queued_req
, true))
10852 work
->flip_ready_vblank
= drm_crtc_vblank_count(crtc
);
10855 if (drm_crtc_vblank_count(crtc
) - work
->flip_ready_vblank
< 3)
10858 /* Potential stall - if we see that the flip has happened,
10859 * assume a missed interrupt. */
10860 if (INTEL_INFO(dev
)->gen
>= 4)
10861 addr
= I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc
->plane
)));
10863 addr
= I915_READ(DSPADDR(intel_crtc
->plane
));
10865 /* There is a potential issue here with a false positive after a flip
10866 * to the same address. We could address this by checking for a
10867 * non-incrementing frame counter.
10869 return addr
== work
->gtt_offset
;
10872 void intel_check_page_flip(struct drm_device
*dev
, int pipe
)
10874 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10875 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
10876 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10877 struct intel_unpin_work
*work
;
10879 WARN_ON(!in_interrupt());
10884 spin_lock(&dev
->event_lock
);
10885 work
= intel_crtc
->unpin_work
;
10886 if (work
!= NULL
&& __intel_pageflip_stall_check(dev
, crtc
)) {
10887 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
10888 work
->flip_queued_vblank
, drm_vblank_count(dev
, pipe
));
10889 page_flip_completed(intel_crtc
);
10892 if (work
!= NULL
&&
10893 drm_vblank_count(dev
, pipe
) - work
->flip_queued_vblank
> 1)
10894 intel_queue_rps_boost_for_request(dev
, work
->flip_queued_req
);
10895 spin_unlock(&dev
->event_lock
);
10898 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
10899 struct drm_framebuffer
*fb
,
10900 struct drm_pending_vblank_event
*event
,
10901 uint32_t page_flip_flags
)
10903 struct drm_device
*dev
= crtc
->dev
;
10904 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10905 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
10906 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
10907 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10908 struct drm_plane
*primary
= crtc
->primary
;
10909 enum pipe pipe
= intel_crtc
->pipe
;
10910 struct intel_unpin_work
*work
;
10911 struct intel_engine_cs
*ring
;
10916 * drm_mode_page_flip_ioctl() should already catch this, but double
10917 * check to be safe. In the future we may enable pageflipping from
10918 * a disabled primary plane.
10920 if (WARN_ON(intel_fb_obj(old_fb
) == NULL
))
10923 /* Can't change pixel format via MI display flips. */
10924 if (fb
->pixel_format
!= crtc
->primary
->fb
->pixel_format
)
10928 * TILEOFF/LINOFF registers can't be changed via MI display flips.
10929 * Note that pitch changes could also affect these register.
10931 if (INTEL_INFO(dev
)->gen
> 3 &&
10932 (fb
->offsets
[0] != crtc
->primary
->fb
->offsets
[0] ||
10933 fb
->pitches
[0] != crtc
->primary
->fb
->pitches
[0]))
10936 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
10939 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
10943 work
->event
= event
;
10945 work
->old_fb
= old_fb
;
10946 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
10948 ret
= drm_crtc_vblank_get(crtc
);
10952 /* We borrow the event spin lock for protecting unpin_work */
10953 spin_lock_irq(&dev
->event_lock
);
10954 if (intel_crtc
->unpin_work
) {
10955 /* Before declaring the flip queue wedged, check if
10956 * the hardware completed the operation behind our backs.
10958 if (__intel_pageflip_stall_check(dev
, crtc
)) {
10959 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10960 page_flip_completed(intel_crtc
);
10962 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
10963 spin_unlock_irq(&dev
->event_lock
);
10965 drm_crtc_vblank_put(crtc
);
10970 intel_crtc
->unpin_work
= work
;
10971 spin_unlock_irq(&dev
->event_lock
);
10973 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
10974 flush_workqueue(dev_priv
->wq
);
10976 /* Reference the objects for the scheduled work. */
10977 drm_framebuffer_reference(work
->old_fb
);
10978 drm_gem_object_reference(&obj
->base
);
10980 crtc
->primary
->fb
= fb
;
10981 update_state_fb(crtc
->primary
);
10983 work
->pending_flip_obj
= obj
;
10985 ret
= i915_mutex_lock_interruptible(dev
);
10989 atomic_inc(&intel_crtc
->unpin_work_count
);
10990 intel_crtc
->reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
10992 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
10993 work
->flip_count
= I915_READ(PIPE_FLIPCOUNT_GM45(pipe
)) + 1;
10995 if (IS_VALLEYVIEW(dev
)) {
10996 ring
= &dev_priv
->ring
[BCS
];
10997 if (obj
->tiling_mode
!= intel_fb_obj(work
->old_fb
)->tiling_mode
)
10998 /* vlv: DISPLAY_FLIP fails to change tiling */
11000 } else if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
11001 ring
= &dev_priv
->ring
[BCS
];
11002 } else if (INTEL_INFO(dev
)->gen
>= 7) {
11003 ring
= i915_gem_request_get_ring(obj
->last_read_req
);
11004 if (ring
== NULL
|| ring
->id
!= RCS
)
11005 ring
= &dev_priv
->ring
[BCS
];
11007 ring
= &dev_priv
->ring
[RCS
];
11010 mmio_flip
= use_mmio_flip(ring
, obj
);
11012 /* When using CS flips, we want to emit semaphores between rings.
11013 * However, when using mmio flips we will create a task to do the
11014 * synchronisation, so all we want here is to pin the framebuffer
11015 * into the display plane and skip any waits.
11017 ret
= intel_pin_and_fence_fb_obj(crtc
->primary
, fb
,
11018 crtc
->primary
->state
,
11019 mmio_flip
? i915_gem_request_get_ring(obj
->last_read_req
) : ring
);
11021 goto cleanup_pending
;
11023 work
->gtt_offset
= intel_plane_obj_offset(to_intel_plane(primary
), obj
)
11024 + intel_crtc
->dspaddr_offset
;
11027 ret
= intel_queue_mmio_flip(dev
, crtc
, fb
, obj
, ring
,
11030 goto cleanup_unpin
;
11032 i915_gem_request_assign(&work
->flip_queued_req
,
11033 obj
->last_write_req
);
11035 if (obj
->last_write_req
) {
11036 ret
= i915_gem_check_olr(obj
->last_write_req
);
11038 goto cleanup_unpin
;
11041 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
, ring
,
11044 goto cleanup_unpin
;
11046 i915_gem_request_assign(&work
->flip_queued_req
,
11047 intel_ring_get_request(ring
));
11050 work
->flip_queued_vblank
= drm_crtc_vblank_count(crtc
);
11051 work
->enable_stall_check
= true;
11053 i915_gem_track_fb(intel_fb_obj(work
->old_fb
), obj
,
11054 INTEL_FRONTBUFFER_PRIMARY(pipe
));
11056 intel_fbc_disable(dev
);
11057 intel_frontbuffer_flip_prepare(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
11058 mutex_unlock(&dev
->struct_mutex
);
11060 trace_i915_flip_request(intel_crtc
->plane
, obj
);
11065 intel_unpin_fb_obj(fb
, crtc
->primary
->state
);
11067 atomic_dec(&intel_crtc
->unpin_work_count
);
11068 mutex_unlock(&dev
->struct_mutex
);
11070 crtc
->primary
->fb
= old_fb
;
11071 update_state_fb(crtc
->primary
);
11073 drm_gem_object_unreference_unlocked(&obj
->base
);
11074 drm_framebuffer_unreference(work
->old_fb
);
11076 spin_lock_irq(&dev
->event_lock
);
11077 intel_crtc
->unpin_work
= NULL
;
11078 spin_unlock_irq(&dev
->event_lock
);
11080 drm_crtc_vblank_put(crtc
);
11086 ret
= intel_plane_restore(primary
);
11087 if (ret
== 0 && event
) {
11088 spin_lock_irq(&dev
->event_lock
);
11089 drm_send_vblank_event(dev
, pipe
, event
);
11090 spin_unlock_irq(&dev
->event_lock
);
11096 static const struct drm_crtc_helper_funcs intel_helper_funcs
= {
11097 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
11098 .load_lut
= intel_crtc_load_lut
,
11099 .atomic_begin
= intel_begin_crtc_commit
,
11100 .atomic_flush
= intel_finish_crtc_commit
,
11104 * intel_modeset_update_staged_output_state
11106 * Updates the staged output configuration state, e.g. after we've read out the
11107 * current hw state.
11109 static void intel_modeset_update_staged_output_state(struct drm_device
*dev
)
11111 struct intel_crtc
*crtc
;
11112 struct intel_encoder
*encoder
;
11113 struct intel_connector
*connector
;
11115 for_each_intel_connector(dev
, connector
) {
11116 connector
->new_encoder
=
11117 to_intel_encoder(connector
->base
.encoder
);
11120 for_each_intel_encoder(dev
, encoder
) {
11121 encoder
->new_crtc
=
11122 to_intel_crtc(encoder
->base
.crtc
);
11125 for_each_intel_crtc(dev
, crtc
) {
11126 crtc
->new_enabled
= crtc
->base
.state
->enable
;
11130 /* Transitional helper to copy current connector/encoder state to
11131 * connector->state. This is needed so that code that is partially
11132 * converted to atomic does the right thing.
11134 static void intel_modeset_update_connector_atomic_state(struct drm_device
*dev
)
11136 struct intel_connector
*connector
;
11138 for_each_intel_connector(dev
, connector
) {
11139 if (connector
->base
.encoder
) {
11140 connector
->base
.state
->best_encoder
=
11141 connector
->base
.encoder
;
11142 connector
->base
.state
->crtc
=
11143 connector
->base
.encoder
->crtc
;
11145 connector
->base
.state
->best_encoder
= NULL
;
11146 connector
->base
.state
->crtc
= NULL
;
11151 /* Fixup legacy state after an atomic state swap.
11153 static void intel_modeset_fixup_state(struct drm_atomic_state
*state
)
11155 struct intel_crtc
*crtc
;
11156 struct intel_encoder
*encoder
;
11157 struct intel_connector
*connector
;
11159 for_each_intel_connector(state
->dev
, connector
) {
11160 connector
->base
.encoder
= connector
->base
.state
->best_encoder
;
11161 if (connector
->base
.encoder
)
11162 connector
->base
.encoder
->crtc
=
11163 connector
->base
.state
->crtc
;
11166 /* Update crtc of disabled encoders */
11167 for_each_intel_encoder(state
->dev
, encoder
) {
11168 int num_connectors
= 0;
11170 for_each_intel_connector(state
->dev
, connector
)
11171 if (connector
->base
.encoder
== &encoder
->base
)
11174 if (num_connectors
== 0)
11175 encoder
->base
.crtc
= NULL
;
11178 for_each_intel_crtc(state
->dev
, crtc
) {
11179 crtc
->base
.enabled
= crtc
->base
.state
->enable
;
11180 crtc
->config
= to_intel_crtc_state(crtc
->base
.state
);
11183 /* Copy the new configuration to the staged state, to keep the few
11184 * pieces of code that haven't been converted yet happy */
11185 intel_modeset_update_staged_output_state(state
->dev
);
11189 connected_sink_compute_bpp(struct intel_connector
*connector
,
11190 struct intel_crtc_state
*pipe_config
)
11192 int bpp
= pipe_config
->pipe_bpp
;
11194 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11195 connector
->base
.base
.id
,
11196 connector
->base
.name
);
11198 /* Don't use an invalid EDID bpc value */
11199 if (connector
->base
.display_info
.bpc
&&
11200 connector
->base
.display_info
.bpc
* 3 < bpp
) {
11201 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11202 bpp
, connector
->base
.display_info
.bpc
*3);
11203 pipe_config
->pipe_bpp
= connector
->base
.display_info
.bpc
*3;
11206 /* Clamp bpp to 8 on screens without EDID 1.4 */
11207 if (connector
->base
.display_info
.bpc
== 0 && bpp
> 24) {
11208 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11210 pipe_config
->pipe_bpp
= 24;
11215 compute_baseline_pipe_bpp(struct intel_crtc
*crtc
,
11216 struct intel_crtc_state
*pipe_config
)
11218 struct drm_device
*dev
= crtc
->base
.dev
;
11219 struct drm_atomic_state
*state
;
11220 struct drm_connector
*connector
;
11221 struct drm_connector_state
*connector_state
;
11224 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
)))
11226 else if (INTEL_INFO(dev
)->gen
>= 5)
11232 pipe_config
->pipe_bpp
= bpp
;
11234 state
= pipe_config
->base
.state
;
11236 /* Clamp display bpp to EDID value */
11237 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
11238 if (connector_state
->crtc
!= &crtc
->base
)
11241 connected_sink_compute_bpp(to_intel_connector(connector
),
11248 static void intel_dump_crtc_timings(const struct drm_display_mode
*mode
)
11250 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11251 "type: 0x%x flags: 0x%x\n",
11253 mode
->crtc_hdisplay
, mode
->crtc_hsync_start
,
11254 mode
->crtc_hsync_end
, mode
->crtc_htotal
,
11255 mode
->crtc_vdisplay
, mode
->crtc_vsync_start
,
11256 mode
->crtc_vsync_end
, mode
->crtc_vtotal
, mode
->type
, mode
->flags
);
11259 static void intel_dump_pipe_config(struct intel_crtc
*crtc
,
11260 struct intel_crtc_state
*pipe_config
,
11261 const char *context
)
11263 struct drm_device
*dev
= crtc
->base
.dev
;
11264 struct drm_plane
*plane
;
11265 struct intel_plane
*intel_plane
;
11266 struct intel_plane_state
*state
;
11267 struct drm_framebuffer
*fb
;
11269 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc
->base
.base
.id
,
11270 context
, pipe_config
, pipe_name(crtc
->pipe
));
11272 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config
->cpu_transcoder
));
11273 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11274 pipe_config
->pipe_bpp
, pipe_config
->dither
);
11275 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11276 pipe_config
->has_pch_encoder
,
11277 pipe_config
->fdi_lanes
,
11278 pipe_config
->fdi_m_n
.gmch_m
, pipe_config
->fdi_m_n
.gmch_n
,
11279 pipe_config
->fdi_m_n
.link_m
, pipe_config
->fdi_m_n
.link_n
,
11280 pipe_config
->fdi_m_n
.tu
);
11281 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11282 pipe_config
->has_dp_encoder
,
11283 pipe_config
->dp_m_n
.gmch_m
, pipe_config
->dp_m_n
.gmch_n
,
11284 pipe_config
->dp_m_n
.link_m
, pipe_config
->dp_m_n
.link_n
,
11285 pipe_config
->dp_m_n
.tu
);
11287 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11288 pipe_config
->has_dp_encoder
,
11289 pipe_config
->dp_m2_n2
.gmch_m
,
11290 pipe_config
->dp_m2_n2
.gmch_n
,
11291 pipe_config
->dp_m2_n2
.link_m
,
11292 pipe_config
->dp_m2_n2
.link_n
,
11293 pipe_config
->dp_m2_n2
.tu
);
11295 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11296 pipe_config
->has_audio
,
11297 pipe_config
->has_infoframe
);
11299 DRM_DEBUG_KMS("requested mode:\n");
11300 drm_mode_debug_printmodeline(&pipe_config
->base
.mode
);
11301 DRM_DEBUG_KMS("adjusted mode:\n");
11302 drm_mode_debug_printmodeline(&pipe_config
->base
.adjusted_mode
);
11303 intel_dump_crtc_timings(&pipe_config
->base
.adjusted_mode
);
11304 DRM_DEBUG_KMS("port clock: %d\n", pipe_config
->port_clock
);
11305 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11306 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
);
11307 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11309 pipe_config
->scaler_state
.scaler_users
,
11310 pipe_config
->scaler_state
.scaler_id
);
11311 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11312 pipe_config
->gmch_pfit
.control
,
11313 pipe_config
->gmch_pfit
.pgm_ratios
,
11314 pipe_config
->gmch_pfit
.lvds_border_bits
);
11315 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11316 pipe_config
->pch_pfit
.pos
,
11317 pipe_config
->pch_pfit
.size
,
11318 pipe_config
->pch_pfit
.enabled
? "enabled" : "disabled");
11319 DRM_DEBUG_KMS("ips: %i\n", pipe_config
->ips_enabled
);
11320 DRM_DEBUG_KMS("double wide: %i\n", pipe_config
->double_wide
);
11322 if (IS_BROXTON(dev
)) {
11323 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, "
11324 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11325 "pll6: 0x%x, pll8: 0x%x, pcsdw12: 0x%x\n",
11326 pipe_config
->ddi_pll_sel
,
11327 pipe_config
->dpll_hw_state
.ebb0
,
11328 pipe_config
->dpll_hw_state
.pll0
,
11329 pipe_config
->dpll_hw_state
.pll1
,
11330 pipe_config
->dpll_hw_state
.pll2
,
11331 pipe_config
->dpll_hw_state
.pll3
,
11332 pipe_config
->dpll_hw_state
.pll6
,
11333 pipe_config
->dpll_hw_state
.pll8
,
11334 pipe_config
->dpll_hw_state
.pcsdw12
);
11335 } else if (IS_SKYLAKE(dev
)) {
11336 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11337 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11338 pipe_config
->ddi_pll_sel
,
11339 pipe_config
->dpll_hw_state
.ctrl1
,
11340 pipe_config
->dpll_hw_state
.cfgcr1
,
11341 pipe_config
->dpll_hw_state
.cfgcr2
);
11342 } else if (HAS_DDI(dev
)) {
11343 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11344 pipe_config
->ddi_pll_sel
,
11345 pipe_config
->dpll_hw_state
.wrpll
);
11347 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11348 "fp0: 0x%x, fp1: 0x%x\n",
11349 pipe_config
->dpll_hw_state
.dpll
,
11350 pipe_config
->dpll_hw_state
.dpll_md
,
11351 pipe_config
->dpll_hw_state
.fp0
,
11352 pipe_config
->dpll_hw_state
.fp1
);
11355 DRM_DEBUG_KMS("planes on this crtc\n");
11356 list_for_each_entry(plane
, &dev
->mode_config
.plane_list
, head
) {
11357 intel_plane
= to_intel_plane(plane
);
11358 if (intel_plane
->pipe
!= crtc
->pipe
)
11361 state
= to_intel_plane_state(plane
->state
);
11362 fb
= state
->base
.fb
;
11364 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11365 "disabled, scaler_id = %d\n",
11366 plane
->type
== DRM_PLANE_TYPE_CURSOR
? "CURSOR" : "STANDARD",
11367 plane
->base
.id
, intel_plane
->pipe
,
11368 (crtc
->base
.primary
== plane
) ? 0 : intel_plane
->plane
+ 1,
11369 drm_plane_index(plane
), state
->scaler_id
);
11373 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11374 plane
->type
== DRM_PLANE_TYPE_CURSOR
? "CURSOR" : "STANDARD",
11375 plane
->base
.id
, intel_plane
->pipe
,
11376 crtc
->base
.primary
== plane
? 0 : intel_plane
->plane
+ 1,
11377 drm_plane_index(plane
));
11378 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11379 fb
->base
.id
, fb
->width
, fb
->height
, fb
->pixel_format
);
11380 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11382 state
->src
.x1
>> 16, state
->src
.y1
>> 16,
11383 drm_rect_width(&state
->src
) >> 16,
11384 drm_rect_height(&state
->src
) >> 16,
11385 state
->dst
.x1
, state
->dst
.y1
,
11386 drm_rect_width(&state
->dst
), drm_rect_height(&state
->dst
));
11390 static bool encoders_cloneable(const struct intel_encoder
*a
,
11391 const struct intel_encoder
*b
)
11393 /* masks could be asymmetric, so check both ways */
11394 return a
== b
|| (a
->cloneable
& (1 << b
->type
) &&
11395 b
->cloneable
& (1 << a
->type
));
11398 static bool check_single_encoder_cloning(struct drm_atomic_state
*state
,
11399 struct intel_crtc
*crtc
,
11400 struct intel_encoder
*encoder
)
11402 struct intel_encoder
*source_encoder
;
11403 struct drm_connector
*connector
;
11404 struct drm_connector_state
*connector_state
;
11407 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
11408 if (connector_state
->crtc
!= &crtc
->base
)
11412 to_intel_encoder(connector_state
->best_encoder
);
11413 if (!encoders_cloneable(encoder
, source_encoder
))
11420 static bool check_encoder_cloning(struct drm_atomic_state
*state
,
11421 struct intel_crtc
*crtc
)
11423 struct intel_encoder
*encoder
;
11424 struct drm_connector
*connector
;
11425 struct drm_connector_state
*connector_state
;
11428 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
11429 if (connector_state
->crtc
!= &crtc
->base
)
11432 encoder
= to_intel_encoder(connector_state
->best_encoder
);
11433 if (!check_single_encoder_cloning(state
, crtc
, encoder
))
11440 static bool check_digital_port_conflicts(struct drm_atomic_state
*state
)
11442 struct drm_device
*dev
= state
->dev
;
11443 struct intel_encoder
*encoder
;
11444 struct drm_connector
*connector
;
11445 struct drm_connector_state
*connector_state
;
11446 unsigned int used_ports
= 0;
11450 * Walk the connector list instead of the encoder
11451 * list to detect the problem on ddi platforms
11452 * where there's just one encoder per digital port.
11454 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
11455 if (!connector_state
->best_encoder
)
11458 encoder
= to_intel_encoder(connector_state
->best_encoder
);
11460 WARN_ON(!connector_state
->crtc
);
11462 switch (encoder
->type
) {
11463 unsigned int port_mask
;
11464 case INTEL_OUTPUT_UNKNOWN
:
11465 if (WARN_ON(!HAS_DDI(dev
)))
11467 case INTEL_OUTPUT_DISPLAYPORT
:
11468 case INTEL_OUTPUT_HDMI
:
11469 case INTEL_OUTPUT_EDP
:
11470 port_mask
= 1 << enc_to_dig_port(&encoder
->base
)->port
;
11472 /* the same port mustn't appear more than once */
11473 if (used_ports
& port_mask
)
11476 used_ports
|= port_mask
;
11486 clear_intel_crtc_state(struct intel_crtc_state
*crtc_state
)
11488 struct drm_crtc_state tmp_state
;
11489 struct intel_crtc_scaler_state scaler_state
;
11490 struct intel_dpll_hw_state dpll_hw_state
;
11491 enum intel_dpll_id shared_dpll
;
11492 uint32_t ddi_pll_sel
;
11494 /* Clear only the intel specific part of the crtc state excluding scalers */
11495 tmp_state
= crtc_state
->base
;
11496 scaler_state
= crtc_state
->scaler_state
;
11497 shared_dpll
= crtc_state
->shared_dpll
;
11498 dpll_hw_state
= crtc_state
->dpll_hw_state
;
11499 ddi_pll_sel
= crtc_state
->ddi_pll_sel
;
11501 memset(crtc_state
, 0, sizeof *crtc_state
);
11503 crtc_state
->base
= tmp_state
;
11504 crtc_state
->scaler_state
= scaler_state
;
11505 crtc_state
->shared_dpll
= shared_dpll
;
11506 crtc_state
->dpll_hw_state
= dpll_hw_state
;
11507 crtc_state
->ddi_pll_sel
= ddi_pll_sel
;
11511 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
11512 struct drm_atomic_state
*state
,
11513 struct intel_crtc_state
*pipe_config
)
11515 struct intel_encoder
*encoder
;
11516 struct drm_connector
*connector
;
11517 struct drm_connector_state
*connector_state
;
11518 int base_bpp
, ret
= -EINVAL
;
11522 if (!check_encoder_cloning(state
, to_intel_crtc(crtc
))) {
11523 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11527 if (!check_digital_port_conflicts(state
)) {
11528 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
11532 clear_intel_crtc_state(pipe_config
);
11534 pipe_config
->cpu_transcoder
=
11535 (enum transcoder
) to_intel_crtc(crtc
)->pipe
;
11538 * Sanitize sync polarity flags based on requested ones. If neither
11539 * positive or negative polarity is requested, treat this as meaning
11540 * negative polarity.
11542 if (!(pipe_config
->base
.adjusted_mode
.flags
&
11543 (DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NHSYNC
)))
11544 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
11546 if (!(pipe_config
->base
.adjusted_mode
.flags
&
11547 (DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_NVSYNC
)))
11548 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
11550 /* Compute a starting value for pipe_config->pipe_bpp taking the source
11551 * plane pixel format and any sink constraints into account. Returns the
11552 * source plane bpp so that dithering can be selected on mismatches
11553 * after encoders and crtc also have had their say. */
11554 base_bpp
= compute_baseline_pipe_bpp(to_intel_crtc(crtc
),
11560 * Determine the real pipe dimensions. Note that stereo modes can
11561 * increase the actual pipe size due to the frame doubling and
11562 * insertion of additional space for blanks between the frame. This
11563 * is stored in the crtc timings. We use the requested mode to do this
11564 * computation to clearly distinguish it from the adjusted mode, which
11565 * can be changed by the connectors in the below retry loop.
11567 drm_crtc_get_hv_timing(&pipe_config
->base
.mode
,
11568 &pipe_config
->pipe_src_w
,
11569 &pipe_config
->pipe_src_h
);
11572 /* Ensure the port clock defaults are reset when retrying. */
11573 pipe_config
->port_clock
= 0;
11574 pipe_config
->pixel_multiplier
= 1;
11576 /* Fill in default crtc timings, allow encoders to overwrite them. */
11577 drm_mode_set_crtcinfo(&pipe_config
->base
.adjusted_mode
,
11578 CRTC_STEREO_DOUBLE
);
11580 /* Pass our mode to the connectors and the CRTC to give them a chance to
11581 * adjust it according to limitations or connector properties, and also
11582 * a chance to reject the mode entirely.
11584 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
11585 if (connector_state
->crtc
!= crtc
)
11588 encoder
= to_intel_encoder(connector_state
->best_encoder
);
11590 if (!(encoder
->compute_config(encoder
, pipe_config
))) {
11591 DRM_DEBUG_KMS("Encoder config failure\n");
11596 /* Set default port clock if not overwritten by the encoder. Needs to be
11597 * done afterwards in case the encoder adjusts the mode. */
11598 if (!pipe_config
->port_clock
)
11599 pipe_config
->port_clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
11600 * pipe_config
->pixel_multiplier
;
11602 ret
= intel_crtc_compute_config(to_intel_crtc(crtc
), pipe_config
);
11604 DRM_DEBUG_KMS("CRTC fixup failed\n");
11608 if (ret
== RETRY
) {
11609 if (WARN(!retry
, "loop in pipe configuration computation\n")) {
11614 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11616 goto encoder_retry
;
11619 pipe_config
->dither
= pipe_config
->pipe_bpp
!= base_bpp
;
11620 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
11621 base_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
11628 static bool intel_crtc_in_use(struct drm_crtc
*crtc
)
11630 struct drm_encoder
*encoder
;
11631 struct drm_device
*dev
= crtc
->dev
;
11633 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
)
11634 if (encoder
->crtc
== crtc
)
11641 needs_modeset(struct drm_crtc_state
*state
)
11643 return state
->mode_changed
|| state
->active_changed
;
11647 intel_modeset_update_state(struct drm_atomic_state
*state
)
11649 struct drm_device
*dev
= state
->dev
;
11650 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11651 struct intel_encoder
*intel_encoder
;
11652 struct drm_crtc
*crtc
;
11653 struct drm_crtc_state
*crtc_state
;
11654 struct drm_connector
*connector
;
11657 intel_shared_dpll_commit(dev_priv
);
11659 for_each_intel_encoder(dev
, intel_encoder
) {
11660 if (!intel_encoder
->base
.crtc
)
11663 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
)
11664 if (crtc
== intel_encoder
->base
.crtc
)
11667 if (crtc
!= intel_encoder
->base
.crtc
)
11670 if (crtc_state
->enable
&& needs_modeset(crtc_state
))
11671 intel_encoder
->connectors_active
= false;
11674 drm_atomic_helper_swap_state(state
->dev
, state
);
11675 intel_modeset_fixup_state(state
);
11677 /* Double check state. */
11678 for_each_crtc(dev
, crtc
) {
11679 WARN_ON(crtc
->state
->enable
!= intel_crtc_in_use(crtc
));
11682 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
11683 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
11686 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
)
11687 if (crtc
== connector
->encoder
->crtc
)
11690 if (crtc
!= connector
->encoder
->crtc
)
11693 if (crtc
->state
->enable
&& needs_modeset(crtc
->state
)) {
11694 struct drm_property
*dpms_property
=
11695 dev
->mode_config
.dpms_property
;
11697 connector
->dpms
= DRM_MODE_DPMS_ON
;
11698 drm_object_property_set_value(&connector
->base
,
11702 intel_encoder
= to_intel_encoder(connector
->encoder
);
11703 intel_encoder
->connectors_active
= true;
11709 static bool intel_fuzzy_clock_check(int clock1
, int clock2
)
11713 if (clock1
== clock2
)
11716 if (!clock1
|| !clock2
)
11719 diff
= abs(clock1
- clock2
);
11721 if (((((diff
+ clock1
+ clock2
) * 100)) / (clock1
+ clock2
)) < 105)
11727 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
11728 list_for_each_entry((intel_crtc), \
11729 &(dev)->mode_config.crtc_list, \
11731 if (mask & (1 <<(intel_crtc)->pipe))
11734 intel_pipe_config_compare(struct drm_device
*dev
,
11735 struct intel_crtc_state
*current_config
,
11736 struct intel_crtc_state
*pipe_config
)
11738 #define PIPE_CONF_CHECK_X(name) \
11739 if (current_config->name != pipe_config->name) { \
11740 DRM_ERROR("mismatch in " #name " " \
11741 "(expected 0x%08x, found 0x%08x)\n", \
11742 current_config->name, \
11743 pipe_config->name); \
11747 #define PIPE_CONF_CHECK_I(name) \
11748 if (current_config->name != pipe_config->name) { \
11749 DRM_ERROR("mismatch in " #name " " \
11750 "(expected %i, found %i)\n", \
11751 current_config->name, \
11752 pipe_config->name); \
11756 /* This is required for BDW+ where there is only one set of registers for
11757 * switching between high and low RR.
11758 * This macro can be used whenever a comparison has to be made between one
11759 * hw state and multiple sw state variables.
11761 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
11762 if ((current_config->name != pipe_config->name) && \
11763 (current_config->alt_name != pipe_config->name)) { \
11764 DRM_ERROR("mismatch in " #name " " \
11765 "(expected %i or %i, found %i)\n", \
11766 current_config->name, \
11767 current_config->alt_name, \
11768 pipe_config->name); \
11772 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
11773 if ((current_config->name ^ pipe_config->name) & (mask)) { \
11774 DRM_ERROR("mismatch in " #name "(" #mask ") " \
11775 "(expected %i, found %i)\n", \
11776 current_config->name & (mask), \
11777 pipe_config->name & (mask)); \
11781 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11782 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11783 DRM_ERROR("mismatch in " #name " " \
11784 "(expected %i, found %i)\n", \
11785 current_config->name, \
11786 pipe_config->name); \
11790 #define PIPE_CONF_QUIRK(quirk) \
11791 ((current_config->quirks | pipe_config->quirks) & (quirk))
11793 PIPE_CONF_CHECK_I(cpu_transcoder
);
11795 PIPE_CONF_CHECK_I(has_pch_encoder
);
11796 PIPE_CONF_CHECK_I(fdi_lanes
);
11797 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_m
);
11798 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_n
);
11799 PIPE_CONF_CHECK_I(fdi_m_n
.link_m
);
11800 PIPE_CONF_CHECK_I(fdi_m_n
.link_n
);
11801 PIPE_CONF_CHECK_I(fdi_m_n
.tu
);
11803 PIPE_CONF_CHECK_I(has_dp_encoder
);
11805 if (INTEL_INFO(dev
)->gen
< 8) {
11806 PIPE_CONF_CHECK_I(dp_m_n
.gmch_m
);
11807 PIPE_CONF_CHECK_I(dp_m_n
.gmch_n
);
11808 PIPE_CONF_CHECK_I(dp_m_n
.link_m
);
11809 PIPE_CONF_CHECK_I(dp_m_n
.link_n
);
11810 PIPE_CONF_CHECK_I(dp_m_n
.tu
);
11812 if (current_config
->has_drrs
) {
11813 PIPE_CONF_CHECK_I(dp_m2_n2
.gmch_m
);
11814 PIPE_CONF_CHECK_I(dp_m2_n2
.gmch_n
);
11815 PIPE_CONF_CHECK_I(dp_m2_n2
.link_m
);
11816 PIPE_CONF_CHECK_I(dp_m2_n2
.link_n
);
11817 PIPE_CONF_CHECK_I(dp_m2_n2
.tu
);
11820 PIPE_CONF_CHECK_I_ALT(dp_m_n
.gmch_m
, dp_m2_n2
.gmch_m
);
11821 PIPE_CONF_CHECK_I_ALT(dp_m_n
.gmch_n
, dp_m2_n2
.gmch_n
);
11822 PIPE_CONF_CHECK_I_ALT(dp_m_n
.link_m
, dp_m2_n2
.link_m
);
11823 PIPE_CONF_CHECK_I_ALT(dp_m_n
.link_n
, dp_m2_n2
.link_n
);
11824 PIPE_CONF_CHECK_I_ALT(dp_m_n
.tu
, dp_m2_n2
.tu
);
11827 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hdisplay
);
11828 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_htotal
);
11829 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_start
);
11830 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_end
);
11831 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_start
);
11832 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_end
);
11834 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vdisplay
);
11835 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vtotal
);
11836 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_start
);
11837 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_end
);
11838 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_start
);
11839 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_end
);
11841 PIPE_CONF_CHECK_I(pixel_multiplier
);
11842 PIPE_CONF_CHECK_I(has_hdmi_sink
);
11843 if ((INTEL_INFO(dev
)->gen
< 8 && !IS_HASWELL(dev
)) ||
11844 IS_VALLEYVIEW(dev
))
11845 PIPE_CONF_CHECK_I(limited_color_range
);
11846 PIPE_CONF_CHECK_I(has_infoframe
);
11848 PIPE_CONF_CHECK_I(has_audio
);
11850 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
11851 DRM_MODE_FLAG_INTERLACE
);
11853 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
11854 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
11855 DRM_MODE_FLAG_PHSYNC
);
11856 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
11857 DRM_MODE_FLAG_NHSYNC
);
11858 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
11859 DRM_MODE_FLAG_PVSYNC
);
11860 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
11861 DRM_MODE_FLAG_NVSYNC
);
11864 PIPE_CONF_CHECK_I(pipe_src_w
);
11865 PIPE_CONF_CHECK_I(pipe_src_h
);
11868 * FIXME: BIOS likes to set up a cloned config with lvds+external
11869 * screen. Since we don't yet re-compute the pipe config when moving
11870 * just the lvds port away to another pipe the sw tracking won't match.
11872 * Proper atomic modesets with recomputed global state will fix this.
11873 * Until then just don't check gmch state for inherited modes.
11875 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE
)) {
11876 PIPE_CONF_CHECK_I(gmch_pfit
.control
);
11877 /* pfit ratios are autocomputed by the hw on gen4+ */
11878 if (INTEL_INFO(dev
)->gen
< 4)
11879 PIPE_CONF_CHECK_I(gmch_pfit
.pgm_ratios
);
11880 PIPE_CONF_CHECK_I(gmch_pfit
.lvds_border_bits
);
11883 PIPE_CONF_CHECK_I(pch_pfit
.enabled
);
11884 if (current_config
->pch_pfit
.enabled
) {
11885 PIPE_CONF_CHECK_I(pch_pfit
.pos
);
11886 PIPE_CONF_CHECK_I(pch_pfit
.size
);
11889 PIPE_CONF_CHECK_I(scaler_state
.scaler_id
);
11891 /* BDW+ don't expose a synchronous way to read the state */
11892 if (IS_HASWELL(dev
))
11893 PIPE_CONF_CHECK_I(ips_enabled
);
11895 PIPE_CONF_CHECK_I(double_wide
);
11897 PIPE_CONF_CHECK_X(ddi_pll_sel
);
11899 PIPE_CONF_CHECK_I(shared_dpll
);
11900 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll
);
11901 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll_md
);
11902 PIPE_CONF_CHECK_X(dpll_hw_state
.fp0
);
11903 PIPE_CONF_CHECK_X(dpll_hw_state
.fp1
);
11904 PIPE_CONF_CHECK_X(dpll_hw_state
.wrpll
);
11905 PIPE_CONF_CHECK_X(dpll_hw_state
.ctrl1
);
11906 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr1
);
11907 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr2
);
11909 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5)
11910 PIPE_CONF_CHECK_I(pipe_bpp
);
11912 PIPE_CONF_CHECK_CLOCK_FUZZY(base
.adjusted_mode
.crtc_clock
);
11913 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock
);
11915 #undef PIPE_CONF_CHECK_X
11916 #undef PIPE_CONF_CHECK_I
11917 #undef PIPE_CONF_CHECK_I_ALT
11918 #undef PIPE_CONF_CHECK_FLAGS
11919 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11920 #undef PIPE_CONF_QUIRK
11925 static void check_wm_state(struct drm_device
*dev
)
11927 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11928 struct skl_ddb_allocation hw_ddb
, *sw_ddb
;
11929 struct intel_crtc
*intel_crtc
;
11932 if (INTEL_INFO(dev
)->gen
< 9)
11935 skl_ddb_get_hw_state(dev_priv
, &hw_ddb
);
11936 sw_ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
11938 for_each_intel_crtc(dev
, intel_crtc
) {
11939 struct skl_ddb_entry
*hw_entry
, *sw_entry
;
11940 const enum pipe pipe
= intel_crtc
->pipe
;
11942 if (!intel_crtc
->active
)
11946 for_each_plane(dev_priv
, pipe
, plane
) {
11947 hw_entry
= &hw_ddb
.plane
[pipe
][plane
];
11948 sw_entry
= &sw_ddb
->plane
[pipe
][plane
];
11950 if (skl_ddb_entry_equal(hw_entry
, sw_entry
))
11953 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
11954 "(expected (%u,%u), found (%u,%u))\n",
11955 pipe_name(pipe
), plane
+ 1,
11956 sw_entry
->start
, sw_entry
->end
,
11957 hw_entry
->start
, hw_entry
->end
);
11961 hw_entry
= &hw_ddb
.cursor
[pipe
];
11962 sw_entry
= &sw_ddb
->cursor
[pipe
];
11964 if (skl_ddb_entry_equal(hw_entry
, sw_entry
))
11967 DRM_ERROR("mismatch in DDB state pipe %c cursor "
11968 "(expected (%u,%u), found (%u,%u))\n",
11970 sw_entry
->start
, sw_entry
->end
,
11971 hw_entry
->start
, hw_entry
->end
);
11976 check_connector_state(struct drm_device
*dev
)
11978 struct intel_connector
*connector
;
11980 for_each_intel_connector(dev
, connector
) {
11981 /* This also checks the encoder/connector hw state with the
11982 * ->get_hw_state callbacks. */
11983 intel_connector_check_state(connector
);
11985 I915_STATE_WARN(&connector
->new_encoder
->base
!= connector
->base
.encoder
,
11986 "connector's staged encoder doesn't match current encoder\n");
11991 check_encoder_state(struct drm_device
*dev
)
11993 struct intel_encoder
*encoder
;
11994 struct intel_connector
*connector
;
11996 for_each_intel_encoder(dev
, encoder
) {
11997 bool enabled
= false;
11998 bool active
= false;
11999 enum pipe pipe
, tracked_pipe
;
12001 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12002 encoder
->base
.base
.id
,
12003 encoder
->base
.name
);
12005 I915_STATE_WARN(&encoder
->new_crtc
->base
!= encoder
->base
.crtc
,
12006 "encoder's stage crtc doesn't match current crtc\n");
12007 I915_STATE_WARN(encoder
->connectors_active
&& !encoder
->base
.crtc
,
12008 "encoder's active_connectors set, but no crtc\n");
12010 for_each_intel_connector(dev
, connector
) {
12011 if (connector
->base
.encoder
!= &encoder
->base
)
12014 if (connector
->base
.dpms
!= DRM_MODE_DPMS_OFF
)
12018 * for MST connectors if we unplug the connector is gone
12019 * away but the encoder is still connected to a crtc
12020 * until a modeset happens in response to the hotplug.
12022 if (!enabled
&& encoder
->base
.encoder_type
== DRM_MODE_ENCODER_DPMST
)
12025 I915_STATE_WARN(!!encoder
->base
.crtc
!= enabled
,
12026 "encoder's enabled state mismatch "
12027 "(expected %i, found %i)\n",
12028 !!encoder
->base
.crtc
, enabled
);
12029 I915_STATE_WARN(active
&& !encoder
->base
.crtc
,
12030 "active encoder with no crtc\n");
12032 I915_STATE_WARN(encoder
->connectors_active
!= active
,
12033 "encoder's computed active state doesn't match tracked active state "
12034 "(expected %i, found %i)\n", active
, encoder
->connectors_active
);
12036 active
= encoder
->get_hw_state(encoder
, &pipe
);
12037 I915_STATE_WARN(active
!= encoder
->connectors_active
,
12038 "encoder's hw state doesn't match sw tracking "
12039 "(expected %i, found %i)\n",
12040 encoder
->connectors_active
, active
);
12042 if (!encoder
->base
.crtc
)
12045 tracked_pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
12046 I915_STATE_WARN(active
&& pipe
!= tracked_pipe
,
12047 "active encoder's pipe doesn't match"
12048 "(expected %i, found %i)\n",
12049 tracked_pipe
, pipe
);
12055 check_crtc_state(struct drm_device
*dev
)
12057 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12058 struct intel_crtc
*crtc
;
12059 struct intel_encoder
*encoder
;
12060 struct intel_crtc_state pipe_config
;
12062 for_each_intel_crtc(dev
, crtc
) {
12063 bool enabled
= false;
12064 bool active
= false;
12066 memset(&pipe_config
, 0, sizeof(pipe_config
));
12068 DRM_DEBUG_KMS("[CRTC:%d]\n",
12069 crtc
->base
.base
.id
);
12071 I915_STATE_WARN(crtc
->active
&& !crtc
->base
.state
->enable
,
12072 "active crtc, but not enabled in sw tracking\n");
12074 for_each_intel_encoder(dev
, encoder
) {
12075 if (encoder
->base
.crtc
!= &crtc
->base
)
12078 if (encoder
->connectors_active
)
12082 I915_STATE_WARN(active
!= crtc
->active
,
12083 "crtc's computed active state doesn't match tracked active state "
12084 "(expected %i, found %i)\n", active
, crtc
->active
);
12085 I915_STATE_WARN(enabled
!= crtc
->base
.state
->enable
,
12086 "crtc's computed enabled state doesn't match tracked enabled state "
12087 "(expected %i, found %i)\n", enabled
,
12088 crtc
->base
.state
->enable
);
12090 active
= dev_priv
->display
.get_pipe_config(crtc
,
12093 /* hw state is inconsistent with the pipe quirk */
12094 if ((crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
12095 (crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
12096 active
= crtc
->active
;
12098 for_each_intel_encoder(dev
, encoder
) {
12100 if (encoder
->base
.crtc
!= &crtc
->base
)
12102 if (encoder
->get_hw_state(encoder
, &pipe
))
12103 encoder
->get_config(encoder
, &pipe_config
);
12106 I915_STATE_WARN(crtc
->active
!= active
,
12107 "crtc active state doesn't match with hw state "
12108 "(expected %i, found %i)\n", crtc
->active
, active
);
12111 !intel_pipe_config_compare(dev
, crtc
->config
, &pipe_config
)) {
12112 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12113 intel_dump_pipe_config(crtc
, &pipe_config
,
12115 intel_dump_pipe_config(crtc
, crtc
->config
,
12122 check_shared_dpll_state(struct drm_device
*dev
)
12124 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12125 struct intel_crtc
*crtc
;
12126 struct intel_dpll_hw_state dpll_hw_state
;
12129 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
12130 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
12131 int enabled_crtcs
= 0, active_crtcs
= 0;
12134 memset(&dpll_hw_state
, 0, sizeof(dpll_hw_state
));
12136 DRM_DEBUG_KMS("%s\n", pll
->name
);
12138 active
= pll
->get_hw_state(dev_priv
, pll
, &dpll_hw_state
);
12140 I915_STATE_WARN(pll
->active
> hweight32(pll
->config
.crtc_mask
),
12141 "more active pll users than references: %i vs %i\n",
12142 pll
->active
, hweight32(pll
->config
.crtc_mask
));
12143 I915_STATE_WARN(pll
->active
&& !pll
->on
,
12144 "pll in active use but not on in sw tracking\n");
12145 I915_STATE_WARN(pll
->on
&& !pll
->active
,
12146 "pll in on but not on in use in sw tracking\n");
12147 I915_STATE_WARN(pll
->on
!= active
,
12148 "pll on state mismatch (expected %i, found %i)\n",
12151 for_each_intel_crtc(dev
, crtc
) {
12152 if (crtc
->base
.state
->enable
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
12154 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
12157 I915_STATE_WARN(pll
->active
!= active_crtcs
,
12158 "pll active crtcs mismatch (expected %i, found %i)\n",
12159 pll
->active
, active_crtcs
);
12160 I915_STATE_WARN(hweight32(pll
->config
.crtc_mask
) != enabled_crtcs
,
12161 "pll enabled crtcs mismatch (expected %i, found %i)\n",
12162 hweight32(pll
->config
.crtc_mask
), enabled_crtcs
);
12164 I915_STATE_WARN(pll
->on
&& memcmp(&pll
->config
.hw_state
, &dpll_hw_state
,
12165 sizeof(dpll_hw_state
)),
12166 "pll hw state mismatch\n");
12171 intel_modeset_check_state(struct drm_device
*dev
)
12173 check_wm_state(dev
);
12174 check_connector_state(dev
);
12175 check_encoder_state(dev
);
12176 check_crtc_state(dev
);
12177 check_shared_dpll_state(dev
);
12180 void ironlake_check_encoder_dotclock(const struct intel_crtc_state
*pipe_config
,
12184 * FDI already provided one idea for the dotclock.
12185 * Yell if the encoder disagrees.
12187 WARN(!intel_fuzzy_clock_check(pipe_config
->base
.adjusted_mode
.crtc_clock
, dotclock
),
12188 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12189 pipe_config
->base
.adjusted_mode
.crtc_clock
, dotclock
);
12192 static void update_scanline_offset(struct intel_crtc
*crtc
)
12194 struct drm_device
*dev
= crtc
->base
.dev
;
12197 * The scanline counter increments at the leading edge of hsync.
12199 * On most platforms it starts counting from vtotal-1 on the
12200 * first active line. That means the scanline counter value is
12201 * always one less than what we would expect. Ie. just after
12202 * start of vblank, which also occurs at start of hsync (on the
12203 * last active line), the scanline counter will read vblank_start-1.
12205 * On gen2 the scanline counter starts counting from 1 instead
12206 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12207 * to keep the value positive), instead of adding one.
12209 * On HSW+ the behaviour of the scanline counter depends on the output
12210 * type. For DP ports it behaves like most other platforms, but on HDMI
12211 * there's an extra 1 line difference. So we need to add two instead of
12212 * one to the value.
12214 if (IS_GEN2(dev
)) {
12215 const struct drm_display_mode
*mode
= &crtc
->config
->base
.adjusted_mode
;
12218 vtotal
= mode
->crtc_vtotal
;
12219 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
12222 crtc
->scanline_offset
= vtotal
- 1;
12223 } else if (HAS_DDI(dev
) &&
12224 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
)) {
12225 crtc
->scanline_offset
= 2;
12227 crtc
->scanline_offset
= 1;
12230 static struct intel_crtc_state
*
12231 intel_modeset_compute_config(struct drm_crtc
*crtc
,
12232 struct drm_atomic_state
*state
)
12234 struct intel_crtc_state
*pipe_config
;
12237 ret
= drm_atomic_add_affected_connectors(state
, crtc
);
12239 return ERR_PTR(ret
);
12241 ret
= drm_atomic_helper_check_modeset(state
->dev
, state
);
12243 return ERR_PTR(ret
);
12246 * Note this needs changes when we start tracking multiple modes
12247 * and crtcs. At that point we'll need to compute the whole config
12248 * (i.e. one pipe_config for each crtc) rather than just the one
12251 pipe_config
= intel_atomic_get_crtc_state(state
, to_intel_crtc(crtc
));
12252 if (IS_ERR(pipe_config
))
12253 return pipe_config
;
12255 if (!pipe_config
->base
.enable
)
12256 return pipe_config
;
12258 ret
= intel_modeset_pipe_config(crtc
, state
, pipe_config
);
12260 return ERR_PTR(ret
);
12262 /* Check things that can only be changed through modeset */
12263 if (pipe_config
->has_audio
!=
12264 to_intel_crtc(crtc
)->config
->has_audio
)
12265 pipe_config
->base
.mode_changed
= true;
12268 * Note we have an issue here with infoframes: current code
12269 * only updates them on the full mode set path per hw
12270 * requirements. So here we should be checking for any
12271 * required changes and forcing a mode set.
12274 intel_dump_pipe_config(to_intel_crtc(crtc
), pipe_config
,"[modeset]");
12276 ret
= drm_atomic_helper_check_planes(state
->dev
, state
);
12278 return ERR_PTR(ret
);
12280 return pipe_config
;
12283 static int __intel_set_mode_setup_plls(struct drm_atomic_state
*state
)
12285 struct drm_device
*dev
= state
->dev
;
12286 struct drm_i915_private
*dev_priv
= to_i915(dev
);
12287 unsigned clear_pipes
= 0;
12288 struct intel_crtc
*intel_crtc
;
12289 struct intel_crtc_state
*intel_crtc_state
;
12290 struct drm_crtc
*crtc
;
12291 struct drm_crtc_state
*crtc_state
;
12295 if (!dev_priv
->display
.crtc_compute_clock
)
12298 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
12299 intel_crtc
= to_intel_crtc(crtc
);
12300 intel_crtc_state
= to_intel_crtc_state(crtc_state
);
12302 if (needs_modeset(crtc_state
)) {
12303 clear_pipes
|= 1 << intel_crtc
->pipe
;
12304 intel_crtc_state
->shared_dpll
= DPLL_ID_PRIVATE
;
12308 ret
= intel_shared_dpll_start_config(dev_priv
, clear_pipes
);
12312 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
12313 if (!needs_modeset(crtc_state
) || !crtc_state
->enable
)
12316 intel_crtc
= to_intel_crtc(crtc
);
12317 intel_crtc_state
= to_intel_crtc_state(crtc_state
);
12319 ret
= dev_priv
->display
.crtc_compute_clock(intel_crtc
,
12322 intel_shared_dpll_abort_config(dev_priv
);
12331 /* Code that should eventually be part of atomic_check() */
12332 static int __intel_set_mode_checks(struct drm_atomic_state
*state
)
12334 struct drm_device
*dev
= state
->dev
;
12338 * See if the config requires any additional preparation, e.g.
12339 * to adjust global state with pipes off. We need to do this
12340 * here so we can get the modeset_pipe updated config for the new
12341 * mode set on this crtc. For other crtcs we need to use the
12342 * adjusted_mode bits in the crtc directly.
12344 if (IS_VALLEYVIEW(dev
) || IS_BROXTON(dev
)) {
12345 ret
= valleyview_modeset_global_pipes(state
);
12350 ret
= __intel_set_mode_setup_plls(state
);
12357 static int __intel_set_mode(struct drm_crtc
*modeset_crtc
,
12358 struct intel_crtc_state
*pipe_config
)
12360 struct drm_device
*dev
= modeset_crtc
->dev
;
12361 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12362 struct drm_atomic_state
*state
= pipe_config
->base
.state
;
12363 struct drm_crtc
*crtc
;
12364 struct drm_crtc_state
*crtc_state
;
12368 ret
= __intel_set_mode_checks(state
);
12372 ret
= drm_atomic_helper_prepare_planes(dev
, state
);
12376 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
12377 if (!needs_modeset(crtc_state
))
12380 if (!crtc_state
->enable
) {
12381 intel_crtc_disable(crtc
);
12382 } else if (crtc
->state
->enable
) {
12383 intel_crtc_disable_planes(crtc
);
12384 dev_priv
->display
.crtc_disable(crtc
);
12388 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
12389 * to set it here already despite that we pass it down the callchain.
12391 * Note we'll need to fix this up when we start tracking multiple
12392 * pipes; here we assume a single modeset_pipe and only track the
12393 * single crtc and mode.
12395 if (pipe_config
->base
.enable
&& needs_modeset(&pipe_config
->base
)) {
12396 modeset_crtc
->mode
= pipe_config
->base
.mode
;
12399 * Calculate and store various constants which
12400 * are later needed by vblank and swap-completion
12401 * timestamping. They are derived from true hwmode.
12403 drm_calc_timestamping_constants(modeset_crtc
,
12404 &pipe_config
->base
.adjusted_mode
);
12407 /* Only after disabling all output pipelines that will be changed can we
12408 * update the the output configuration. */
12409 intel_modeset_update_state(state
);
12411 /* The state has been swaped above, so state actually contains the
12412 * old state now. */
12414 modeset_update_crtc_power_domains(state
);
12416 drm_atomic_helper_commit_planes(dev
, state
);
12418 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12419 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
12420 if (!needs_modeset(crtc
->state
) || !crtc
->state
->enable
)
12423 update_scanline_offset(to_intel_crtc(crtc
));
12425 dev_priv
->display
.crtc_enable(crtc
);
12426 intel_crtc_enable_planes(crtc
);
12429 /* FIXME: add subpixel order */
12431 drm_atomic_helper_cleanup_planes(dev
, state
);
12433 drm_atomic_state_free(state
);
12438 static int intel_set_mode_with_config(struct drm_crtc
*crtc
,
12439 struct intel_crtc_state
*pipe_config
)
12443 ret
= __intel_set_mode(crtc
, pipe_config
);
12446 intel_modeset_check_state(crtc
->dev
);
12451 static int intel_set_mode(struct drm_crtc
*crtc
,
12452 struct drm_atomic_state
*state
)
12454 struct intel_crtc_state
*pipe_config
;
12457 pipe_config
= intel_modeset_compute_config(crtc
, state
);
12458 if (IS_ERR(pipe_config
)) {
12459 ret
= PTR_ERR(pipe_config
);
12463 ret
= intel_set_mode_with_config(crtc
, pipe_config
);
12471 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
12473 struct drm_device
*dev
= crtc
->dev
;
12474 struct drm_atomic_state
*state
;
12475 struct intel_crtc
*intel_crtc
;
12476 struct intel_encoder
*encoder
;
12477 struct intel_connector
*connector
;
12478 struct drm_connector_state
*connector_state
;
12479 struct intel_crtc_state
*crtc_state
;
12482 state
= drm_atomic_state_alloc(dev
);
12484 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
12489 state
->acquire_ctx
= dev
->mode_config
.acquire_ctx
;
12491 /* The force restore path in the HW readout code relies on the staged
12492 * config still keeping the user requested config while the actual
12493 * state has been overwritten by the configuration read from HW. We
12494 * need to copy the staged config to the atomic state, otherwise the
12495 * mode set will just reapply the state the HW is already in. */
12496 for_each_intel_encoder(dev
, encoder
) {
12497 if (&encoder
->new_crtc
->base
!= crtc
)
12500 for_each_intel_connector(dev
, connector
) {
12501 if (connector
->new_encoder
!= encoder
)
12504 connector_state
= drm_atomic_get_connector_state(state
, &connector
->base
);
12505 if (IS_ERR(connector_state
)) {
12506 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
12507 connector
->base
.base
.id
,
12508 connector
->base
.name
,
12509 PTR_ERR(connector_state
));
12513 connector_state
->crtc
= crtc
;
12514 connector_state
->best_encoder
= &encoder
->base
;
12518 for_each_intel_crtc(dev
, intel_crtc
) {
12519 if (intel_crtc
->new_enabled
== intel_crtc
->base
.enabled
)
12522 crtc_state
= intel_atomic_get_crtc_state(state
, intel_crtc
);
12523 if (IS_ERR(crtc_state
)) {
12524 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
12525 intel_crtc
->base
.base
.id
,
12526 PTR_ERR(crtc_state
));
12530 crtc_state
->base
.active
= crtc_state
->base
.enable
=
12531 intel_crtc
->new_enabled
;
12533 if (&intel_crtc
->base
== crtc
)
12534 drm_mode_copy(&crtc_state
->base
.mode
, &crtc
->mode
);
12537 intel_modeset_setup_plane_state(state
, crtc
, &crtc
->mode
,
12538 crtc
->primary
->fb
, crtc
->x
, crtc
->y
);
12540 ret
= intel_set_mode(crtc
, state
);
12542 drm_atomic_state_free(state
);
12545 #undef for_each_intel_crtc_masked
12547 static bool intel_connector_in_mode_set(struct intel_connector
*connector
,
12548 struct drm_mode_set
*set
)
12552 for (ro
= 0; ro
< set
->num_connectors
; ro
++)
12553 if (set
->connectors
[ro
] == &connector
->base
)
12560 intel_modeset_stage_output_state(struct drm_device
*dev
,
12561 struct drm_mode_set
*set
,
12562 struct drm_atomic_state
*state
)
12564 struct intel_connector
*connector
;
12565 struct drm_connector
*drm_connector
;
12566 struct drm_connector_state
*connector_state
;
12567 struct drm_crtc
*crtc
;
12568 struct drm_crtc_state
*crtc_state
;
12571 /* The upper layers ensure that we either disable a crtc or have a list
12572 * of connectors. For paranoia, double-check this. */
12573 WARN_ON(!set
->fb
&& (set
->num_connectors
!= 0));
12574 WARN_ON(set
->fb
&& (set
->num_connectors
== 0));
12576 for_each_intel_connector(dev
, connector
) {
12577 bool in_mode_set
= intel_connector_in_mode_set(connector
, set
);
12579 if (!in_mode_set
&& connector
->base
.state
->crtc
!= set
->crtc
)
12583 drm_atomic_get_connector_state(state
, &connector
->base
);
12584 if (IS_ERR(connector_state
))
12585 return PTR_ERR(connector_state
);
12588 int pipe
= to_intel_crtc(set
->crtc
)->pipe
;
12589 connector_state
->best_encoder
=
12590 &intel_find_encoder(connector
, pipe
)->base
;
12593 if (connector
->base
.state
->crtc
!= set
->crtc
)
12596 /* If we disable the crtc, disable all its connectors. Also, if
12597 * the connector is on the changing crtc but not on the new
12598 * connector list, disable it. */
12599 if (!set
->fb
|| !in_mode_set
) {
12600 connector_state
->best_encoder
= NULL
;
12602 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
12603 connector
->base
.base
.id
,
12604 connector
->base
.name
);
12607 /* connector->new_encoder is now updated for all connectors. */
12609 for_each_connector_in_state(state
, drm_connector
, connector_state
, i
) {
12610 connector
= to_intel_connector(drm_connector
);
12612 if (!connector_state
->best_encoder
) {
12613 ret
= drm_atomic_set_crtc_for_connector(connector_state
,
12621 if (intel_connector_in_mode_set(connector
, set
)) {
12622 struct drm_crtc
*crtc
= connector
->base
.state
->crtc
;
12624 /* If this connector was in a previous crtc, add it
12625 * to the state. We might need to disable it. */
12628 drm_atomic_get_crtc_state(state
, crtc
);
12629 if (IS_ERR(crtc_state
))
12630 return PTR_ERR(crtc_state
);
12633 ret
= drm_atomic_set_crtc_for_connector(connector_state
,
12639 /* Make sure the new CRTC will work with the encoder */
12640 if (!drm_encoder_crtc_ok(connector_state
->best_encoder
,
12641 connector_state
->crtc
)) {
12645 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
12646 connector
->base
.base
.id
,
12647 connector
->base
.name
,
12648 connector_state
->crtc
->base
.id
);
12650 if (connector_state
->best_encoder
!= &connector
->encoder
->base
)
12651 connector
->encoder
=
12652 to_intel_encoder(connector_state
->best_encoder
);
12655 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
12656 bool has_connectors
;
12658 ret
= drm_atomic_add_affected_connectors(state
, crtc
);
12662 has_connectors
= !!drm_atomic_connectors_for_crtc(state
, crtc
);
12663 if (has_connectors
!= crtc_state
->enable
)
12664 crtc_state
->enable
=
12665 crtc_state
->active
= has_connectors
;
12668 ret
= intel_modeset_setup_plane_state(state
, set
->crtc
, set
->mode
,
12669 set
->fb
, set
->x
, set
->y
);
12673 crtc_state
= drm_atomic_get_crtc_state(state
, set
->crtc
);
12674 if (IS_ERR(crtc_state
))
12675 return PTR_ERR(crtc_state
);
12678 drm_mode_copy(&crtc_state
->mode
, set
->mode
);
12680 if (set
->num_connectors
)
12681 crtc_state
->active
= true;
12686 static bool primary_plane_visible(struct drm_crtc
*crtc
)
12688 struct intel_plane_state
*plane_state
=
12689 to_intel_plane_state(crtc
->primary
->state
);
12691 return plane_state
->visible
;
12694 static int intel_crtc_set_config(struct drm_mode_set
*set
)
12696 struct drm_device
*dev
;
12697 struct drm_atomic_state
*state
= NULL
;
12698 struct intel_crtc_state
*pipe_config
;
12699 bool primary_plane_was_visible
;
12703 BUG_ON(!set
->crtc
);
12704 BUG_ON(!set
->crtc
->helper_private
);
12706 /* Enforce sane interface api - has been abused by the fb helper. */
12707 BUG_ON(!set
->mode
&& set
->fb
);
12708 BUG_ON(set
->fb
&& set
->num_connectors
== 0);
12711 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
12712 set
->crtc
->base
.id
, set
->fb
->base
.id
,
12713 (int)set
->num_connectors
, set
->x
, set
->y
);
12715 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set
->crtc
->base
.id
);
12718 dev
= set
->crtc
->dev
;
12720 state
= drm_atomic_state_alloc(dev
);
12724 state
->acquire_ctx
= dev
->mode_config
.acquire_ctx
;
12726 ret
= intel_modeset_stage_output_state(dev
, set
, state
);
12730 pipe_config
= intel_modeset_compute_config(set
->crtc
, state
);
12731 if (IS_ERR(pipe_config
)) {
12732 ret
= PTR_ERR(pipe_config
);
12736 intel_update_pipe_size(to_intel_crtc(set
->crtc
));
12738 primary_plane_was_visible
= primary_plane_visible(set
->crtc
);
12740 ret
= intel_set_mode_with_config(set
->crtc
, pipe_config
);
12743 pipe_config
->base
.enable
&&
12744 pipe_config
->base
.planes_changed
&&
12745 !needs_modeset(&pipe_config
->base
)) {
12746 struct intel_crtc
*intel_crtc
= to_intel_crtc(set
->crtc
);
12749 * We need to make sure the primary plane is re-enabled if it
12750 * has previously been turned off.
12752 if (ret
== 0 && !primary_plane_was_visible
&&
12753 primary_plane_visible(set
->crtc
)) {
12754 WARN_ON(!intel_crtc
->active
);
12755 intel_post_enable_primary(set
->crtc
);
12759 * In the fastboot case this may be our only check of the
12760 * state after boot. It would be better to only do it on
12761 * the first update, but we don't have a nice way of doing that
12762 * (and really, set_config isn't used much for high freq page
12763 * flipping, so increasing its cost here shouldn't be a big
12766 if (i915
.fastboot
&& ret
== 0)
12767 intel_modeset_check_state(set
->crtc
->dev
);
12771 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
12772 set
->crtc
->base
.id
, ret
);
12777 drm_atomic_state_free(state
);
12781 static const struct drm_crtc_funcs intel_crtc_funcs
= {
12782 .gamma_set
= intel_crtc_gamma_set
,
12783 .set_config
= intel_crtc_set_config
,
12784 .destroy
= intel_crtc_destroy
,
12785 .page_flip
= intel_crtc_page_flip
,
12786 .atomic_duplicate_state
= intel_crtc_duplicate_state
,
12787 .atomic_destroy_state
= intel_crtc_destroy_state
,
12790 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private
*dev_priv
,
12791 struct intel_shared_dpll
*pll
,
12792 struct intel_dpll_hw_state
*hw_state
)
12796 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
12799 val
= I915_READ(PCH_DPLL(pll
->id
));
12800 hw_state
->dpll
= val
;
12801 hw_state
->fp0
= I915_READ(PCH_FP0(pll
->id
));
12802 hw_state
->fp1
= I915_READ(PCH_FP1(pll
->id
));
12804 return val
& DPLL_VCO_ENABLE
;
12807 static void ibx_pch_dpll_mode_set(struct drm_i915_private
*dev_priv
,
12808 struct intel_shared_dpll
*pll
)
12810 I915_WRITE(PCH_FP0(pll
->id
), pll
->config
.hw_state
.fp0
);
12811 I915_WRITE(PCH_FP1(pll
->id
), pll
->config
.hw_state
.fp1
);
12814 static void ibx_pch_dpll_enable(struct drm_i915_private
*dev_priv
,
12815 struct intel_shared_dpll
*pll
)
12817 /* PCH refclock must be enabled first */
12818 ibx_assert_pch_refclk_enabled(dev_priv
);
12820 I915_WRITE(PCH_DPLL(pll
->id
), pll
->config
.hw_state
.dpll
);
12822 /* Wait for the clocks to stabilize. */
12823 POSTING_READ(PCH_DPLL(pll
->id
));
12826 /* The pixel multiplier can only be updated once the
12827 * DPLL is enabled and the clocks are stable.
12829 * So write it again.
12831 I915_WRITE(PCH_DPLL(pll
->id
), pll
->config
.hw_state
.dpll
);
12832 POSTING_READ(PCH_DPLL(pll
->id
));
12836 static void ibx_pch_dpll_disable(struct drm_i915_private
*dev_priv
,
12837 struct intel_shared_dpll
*pll
)
12839 struct drm_device
*dev
= dev_priv
->dev
;
12840 struct intel_crtc
*crtc
;
12842 /* Make sure no transcoder isn't still depending on us. */
12843 for_each_intel_crtc(dev
, crtc
) {
12844 if (intel_crtc_to_shared_dpll(crtc
) == pll
)
12845 assert_pch_transcoder_disabled(dev_priv
, crtc
->pipe
);
12848 I915_WRITE(PCH_DPLL(pll
->id
), 0);
12849 POSTING_READ(PCH_DPLL(pll
->id
));
12853 static char *ibx_pch_dpll_names
[] = {
12858 static void ibx_pch_dpll_init(struct drm_device
*dev
)
12860 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12863 dev_priv
->num_shared_dpll
= 2;
12865 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
12866 dev_priv
->shared_dplls
[i
].id
= i
;
12867 dev_priv
->shared_dplls
[i
].name
= ibx_pch_dpll_names
[i
];
12868 dev_priv
->shared_dplls
[i
].mode_set
= ibx_pch_dpll_mode_set
;
12869 dev_priv
->shared_dplls
[i
].enable
= ibx_pch_dpll_enable
;
12870 dev_priv
->shared_dplls
[i
].disable
= ibx_pch_dpll_disable
;
12871 dev_priv
->shared_dplls
[i
].get_hw_state
=
12872 ibx_pch_dpll_get_hw_state
;
12876 static void intel_shared_dpll_init(struct drm_device
*dev
)
12878 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12881 intel_ddi_pll_init(dev
);
12882 else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
12883 ibx_pch_dpll_init(dev
);
12885 dev_priv
->num_shared_dpll
= 0;
12887 BUG_ON(dev_priv
->num_shared_dpll
> I915_NUM_PLLS
);
12891 * intel_wm_need_update - Check whether watermarks need updating
12892 * @plane: drm plane
12893 * @state: new plane state
12895 * Check current plane state versus the new one to determine whether
12896 * watermarks need to be recalculated.
12898 * Returns true or false.
12900 bool intel_wm_need_update(struct drm_plane
*plane
,
12901 struct drm_plane_state
*state
)
12903 /* Update watermarks on tiling changes. */
12904 if (!plane
->state
->fb
|| !state
->fb
||
12905 plane
->state
->fb
->modifier
[0] != state
->fb
->modifier
[0] ||
12906 plane
->state
->rotation
!= state
->rotation
)
12913 * intel_prepare_plane_fb - Prepare fb for usage on plane
12914 * @plane: drm plane to prepare for
12915 * @fb: framebuffer to prepare for presentation
12917 * Prepares a framebuffer for usage on a display plane. Generally this
12918 * involves pinning the underlying object and updating the frontbuffer tracking
12919 * bits. Some older platforms need special physical address handling for
12922 * Returns 0 on success, negative error code on failure.
12925 intel_prepare_plane_fb(struct drm_plane
*plane
,
12926 struct drm_framebuffer
*fb
,
12927 const struct drm_plane_state
*new_state
)
12929 struct drm_device
*dev
= plane
->dev
;
12930 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
12931 enum pipe pipe
= intel_plane
->pipe
;
12932 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
12933 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(plane
->fb
);
12934 unsigned frontbuffer_bits
= 0;
12940 switch (plane
->type
) {
12941 case DRM_PLANE_TYPE_PRIMARY
:
12942 frontbuffer_bits
= INTEL_FRONTBUFFER_PRIMARY(pipe
);
12944 case DRM_PLANE_TYPE_CURSOR
:
12945 frontbuffer_bits
= INTEL_FRONTBUFFER_CURSOR(pipe
);
12947 case DRM_PLANE_TYPE_OVERLAY
:
12948 frontbuffer_bits
= INTEL_FRONTBUFFER_SPRITE(pipe
);
12952 mutex_lock(&dev
->struct_mutex
);
12954 if (plane
->type
== DRM_PLANE_TYPE_CURSOR
&&
12955 INTEL_INFO(dev
)->cursor_needs_physical
) {
12956 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
12957 ret
= i915_gem_object_attach_phys(obj
, align
);
12959 DRM_DEBUG_KMS("failed to attach phys object\n");
12961 ret
= intel_pin_and_fence_fb_obj(plane
, fb
, new_state
, NULL
);
12965 i915_gem_track_fb(old_obj
, obj
, frontbuffer_bits
);
12967 mutex_unlock(&dev
->struct_mutex
);
12973 * intel_cleanup_plane_fb - Cleans up an fb after plane use
12974 * @plane: drm plane to clean up for
12975 * @fb: old framebuffer that was on plane
12977 * Cleans up a framebuffer that has just been removed from a plane.
12980 intel_cleanup_plane_fb(struct drm_plane
*plane
,
12981 struct drm_framebuffer
*fb
,
12982 const struct drm_plane_state
*old_state
)
12984 struct drm_device
*dev
= plane
->dev
;
12985 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
12990 if (plane
->type
!= DRM_PLANE_TYPE_CURSOR
||
12991 !INTEL_INFO(dev
)->cursor_needs_physical
) {
12992 mutex_lock(&dev
->struct_mutex
);
12993 intel_unpin_fb_obj(fb
, old_state
);
12994 mutex_unlock(&dev
->struct_mutex
);
12999 skl_max_scale(struct intel_crtc
*intel_crtc
, struct intel_crtc_state
*crtc_state
)
13002 struct drm_device
*dev
;
13003 struct drm_i915_private
*dev_priv
;
13004 int crtc_clock
, cdclk
;
13006 if (!intel_crtc
|| !crtc_state
)
13007 return DRM_PLANE_HELPER_NO_SCALING
;
13009 dev
= intel_crtc
->base
.dev
;
13010 dev_priv
= dev
->dev_private
;
13011 crtc_clock
= crtc_state
->base
.adjusted_mode
.crtc_clock
;
13012 cdclk
= dev_priv
->display
.get_display_clock_speed(dev
);
13014 if (!crtc_clock
|| !cdclk
)
13015 return DRM_PLANE_HELPER_NO_SCALING
;
13018 * skl max scale is lower of:
13019 * close to 3 but not 3, -1 is for that purpose
13023 max_scale
= min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk
<< 8) / crtc_clock
));
13029 intel_check_primary_plane(struct drm_plane
*plane
,
13030 struct intel_plane_state
*state
)
13032 struct drm_device
*dev
= plane
->dev
;
13033 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13034 struct drm_crtc
*crtc
= state
->base
.crtc
;
13035 struct intel_crtc
*intel_crtc
;
13036 struct intel_crtc_state
*crtc_state
;
13037 struct drm_framebuffer
*fb
= state
->base
.fb
;
13038 struct drm_rect
*dest
= &state
->dst
;
13039 struct drm_rect
*src
= &state
->src
;
13040 const struct drm_rect
*clip
= &state
->clip
;
13041 bool can_position
= false;
13042 int max_scale
= DRM_PLANE_HELPER_NO_SCALING
;
13043 int min_scale
= DRM_PLANE_HELPER_NO_SCALING
;
13046 crtc
= crtc
? crtc
: plane
->crtc
;
13047 intel_crtc
= to_intel_crtc(crtc
);
13048 crtc_state
= state
->base
.state
?
13049 intel_atomic_get_crtc_state(state
->base
.state
, intel_crtc
) : NULL
;
13051 if (INTEL_INFO(dev
)->gen
>= 9) {
13053 max_scale
= skl_max_scale(intel_crtc
, crtc_state
);
13054 can_position
= true;
13057 ret
= drm_plane_helper_check_update(plane
, crtc
, fb
,
13061 can_position
, true,
13066 if (intel_crtc
->active
) {
13067 struct intel_plane_state
*old_state
=
13068 to_intel_plane_state(plane
->state
);
13070 intel_crtc
->atomic
.wait_for_flips
= true;
13073 * FBC does not work on some platforms for rotated
13074 * planes, so disable it when rotation is not 0 and
13075 * update it when rotation is set back to 0.
13077 * FIXME: This is redundant with the fbc update done in
13078 * the primary plane enable function except that that
13079 * one is done too late. We eventually need to unify
13082 if (state
->visible
&&
13083 INTEL_INFO(dev
)->gen
<= 4 && !IS_G4X(dev
) &&
13084 dev_priv
->fbc
.crtc
== intel_crtc
&&
13085 state
->base
.rotation
!= BIT(DRM_ROTATE_0
)) {
13086 intel_crtc
->atomic
.disable_fbc
= true;
13089 if (state
->visible
&& !old_state
->visible
) {
13091 * BDW signals flip done immediately if the plane
13092 * is disabled, even if the plane enable is already
13093 * armed to occur at the next vblank :(
13095 if (IS_BROADWELL(dev
))
13096 intel_crtc
->atomic
.wait_vblank
= true;
13099 intel_crtc
->atomic
.fb_bits
|=
13100 INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
);
13102 intel_crtc
->atomic
.update_fbc
= true;
13104 if (intel_wm_need_update(plane
, &state
->base
))
13105 intel_crtc
->atomic
.update_wm
= true;
13108 if (INTEL_INFO(dev
)->gen
>= 9) {
13109 ret
= skl_update_scaler_users(intel_crtc
, crtc_state
,
13110 to_intel_plane(plane
), state
, 0);
13119 intel_commit_primary_plane(struct drm_plane
*plane
,
13120 struct intel_plane_state
*state
)
13122 struct drm_crtc
*crtc
= state
->base
.crtc
;
13123 struct drm_framebuffer
*fb
= state
->base
.fb
;
13124 struct drm_device
*dev
= plane
->dev
;
13125 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13126 struct intel_crtc
*intel_crtc
;
13127 struct drm_rect
*src
= &state
->src
;
13129 crtc
= crtc
? crtc
: plane
->crtc
;
13130 intel_crtc
= to_intel_crtc(crtc
);
13133 crtc
->x
= src
->x1
>> 16;
13134 crtc
->y
= src
->y1
>> 16;
13136 if (intel_crtc
->active
) {
13137 if (state
->visible
)
13138 /* FIXME: kill this fastboot hack */
13139 intel_update_pipe_size(intel_crtc
);
13141 dev_priv
->display
.update_primary_plane(crtc
, plane
->fb
,
13147 intel_disable_primary_plane(struct drm_plane
*plane
,
13148 struct drm_crtc
*crtc
,
13151 struct drm_device
*dev
= plane
->dev
;
13152 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13154 dev_priv
->display
.update_primary_plane(crtc
, NULL
, 0, 0);
13157 static void intel_begin_crtc_commit(struct drm_crtc
*crtc
)
13159 struct drm_device
*dev
= crtc
->dev
;
13160 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13161 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13162 struct intel_plane
*intel_plane
;
13163 struct drm_plane
*p
;
13164 unsigned fb_bits
= 0;
13166 /* Track fb's for any planes being disabled */
13167 list_for_each_entry(p
, &dev
->mode_config
.plane_list
, head
) {
13168 intel_plane
= to_intel_plane(p
);
13170 if (intel_crtc
->atomic
.disabled_planes
&
13171 (1 << drm_plane_index(p
))) {
13173 case DRM_PLANE_TYPE_PRIMARY
:
13174 fb_bits
= INTEL_FRONTBUFFER_PRIMARY(intel_plane
->pipe
);
13176 case DRM_PLANE_TYPE_CURSOR
:
13177 fb_bits
= INTEL_FRONTBUFFER_CURSOR(intel_plane
->pipe
);
13179 case DRM_PLANE_TYPE_OVERLAY
:
13180 fb_bits
= INTEL_FRONTBUFFER_SPRITE(intel_plane
->pipe
);
13184 mutex_lock(&dev
->struct_mutex
);
13185 i915_gem_track_fb(intel_fb_obj(p
->fb
), NULL
, fb_bits
);
13186 mutex_unlock(&dev
->struct_mutex
);
13190 if (intel_crtc
->atomic
.wait_for_flips
)
13191 intel_crtc_wait_for_pending_flips(crtc
);
13193 if (intel_crtc
->atomic
.disable_fbc
)
13194 intel_fbc_disable(dev
);
13196 if (intel_crtc
->atomic
.pre_disable_primary
)
13197 intel_pre_disable_primary(crtc
);
13199 if (intel_crtc
->atomic
.update_wm
)
13200 intel_update_watermarks(crtc
);
13202 intel_runtime_pm_get(dev_priv
);
13204 /* Perform vblank evasion around commit operation */
13205 if (intel_crtc
->active
)
13206 intel_crtc
->atomic
.evade
=
13207 intel_pipe_update_start(intel_crtc
,
13208 &intel_crtc
->atomic
.start_vbl_count
);
13211 static void intel_finish_crtc_commit(struct drm_crtc
*crtc
)
13213 struct drm_device
*dev
= crtc
->dev
;
13214 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13215 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13216 struct drm_plane
*p
;
13218 if (intel_crtc
->atomic
.evade
)
13219 intel_pipe_update_end(intel_crtc
,
13220 intel_crtc
->atomic
.start_vbl_count
);
13222 intel_runtime_pm_put(dev_priv
);
13224 if (intel_crtc
->atomic
.wait_vblank
)
13225 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
13227 intel_frontbuffer_flip(dev
, intel_crtc
->atomic
.fb_bits
);
13229 if (intel_crtc
->atomic
.update_fbc
) {
13230 mutex_lock(&dev
->struct_mutex
);
13231 intel_fbc_update(dev
);
13232 mutex_unlock(&dev
->struct_mutex
);
13235 if (intel_crtc
->atomic
.post_enable_primary
)
13236 intel_post_enable_primary(crtc
);
13238 drm_for_each_legacy_plane(p
, &dev
->mode_config
.plane_list
)
13239 if (intel_crtc
->atomic
.update_sprite_watermarks
& drm_plane_index(p
))
13240 intel_update_sprite_watermarks(p
, crtc
, 0, 0, 0,
13243 memset(&intel_crtc
->atomic
, 0, sizeof(intel_crtc
->atomic
));
13247 * intel_plane_destroy - destroy a plane
13248 * @plane: plane to destroy
13250 * Common destruction function for all types of planes (primary, cursor,
13253 void intel_plane_destroy(struct drm_plane
*plane
)
13255 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
13256 drm_plane_cleanup(plane
);
13257 kfree(intel_plane
);
13260 const struct drm_plane_funcs intel_plane_funcs
= {
13261 .update_plane
= drm_atomic_helper_update_plane
,
13262 .disable_plane
= drm_atomic_helper_disable_plane
,
13263 .destroy
= intel_plane_destroy
,
13264 .set_property
= drm_atomic_helper_plane_set_property
,
13265 .atomic_get_property
= intel_plane_atomic_get_property
,
13266 .atomic_set_property
= intel_plane_atomic_set_property
,
13267 .atomic_duplicate_state
= intel_plane_duplicate_state
,
13268 .atomic_destroy_state
= intel_plane_destroy_state
,
13272 static struct drm_plane
*intel_primary_plane_create(struct drm_device
*dev
,
13275 struct intel_plane
*primary
;
13276 struct intel_plane_state
*state
;
13277 const uint32_t *intel_primary_formats
;
13280 primary
= kzalloc(sizeof(*primary
), GFP_KERNEL
);
13281 if (primary
== NULL
)
13284 state
= intel_create_plane_state(&primary
->base
);
13289 primary
->base
.state
= &state
->base
;
13291 primary
->can_scale
= false;
13292 primary
->max_downscale
= 1;
13293 if (INTEL_INFO(dev
)->gen
>= 9) {
13294 primary
->can_scale
= true;
13295 state
->scaler_id
= -1;
13297 primary
->pipe
= pipe
;
13298 primary
->plane
= pipe
;
13299 primary
->check_plane
= intel_check_primary_plane
;
13300 primary
->commit_plane
= intel_commit_primary_plane
;
13301 primary
->disable_plane
= intel_disable_primary_plane
;
13302 primary
->ckey
.flags
= I915_SET_COLORKEY_NONE
;
13303 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4)
13304 primary
->plane
= !pipe
;
13306 if (INTEL_INFO(dev
)->gen
<= 3) {
13307 intel_primary_formats
= i8xx_primary_formats
;
13308 num_formats
= ARRAY_SIZE(i8xx_primary_formats
);
13310 intel_primary_formats
= i965_primary_formats
;
13311 num_formats
= ARRAY_SIZE(i965_primary_formats
);
13314 drm_universal_plane_init(dev
, &primary
->base
, 0,
13315 &intel_plane_funcs
,
13316 intel_primary_formats
, num_formats
,
13317 DRM_PLANE_TYPE_PRIMARY
);
13319 if (INTEL_INFO(dev
)->gen
>= 4)
13320 intel_create_rotation_property(dev
, primary
);
13322 drm_plane_helper_add(&primary
->base
, &intel_plane_helper_funcs
);
13324 return &primary
->base
;
13327 void intel_create_rotation_property(struct drm_device
*dev
, struct intel_plane
*plane
)
13329 if (!dev
->mode_config
.rotation_property
) {
13330 unsigned long flags
= BIT(DRM_ROTATE_0
) |
13331 BIT(DRM_ROTATE_180
);
13333 if (INTEL_INFO(dev
)->gen
>= 9)
13334 flags
|= BIT(DRM_ROTATE_90
) | BIT(DRM_ROTATE_270
);
13336 dev
->mode_config
.rotation_property
=
13337 drm_mode_create_rotation_property(dev
, flags
);
13339 if (dev
->mode_config
.rotation_property
)
13340 drm_object_attach_property(&plane
->base
.base
,
13341 dev
->mode_config
.rotation_property
,
13342 plane
->base
.state
->rotation
);
13346 intel_check_cursor_plane(struct drm_plane
*plane
,
13347 struct intel_plane_state
*state
)
13349 struct drm_crtc
*crtc
= state
->base
.crtc
;
13350 struct drm_device
*dev
= plane
->dev
;
13351 struct drm_framebuffer
*fb
= state
->base
.fb
;
13352 struct drm_rect
*dest
= &state
->dst
;
13353 struct drm_rect
*src
= &state
->src
;
13354 const struct drm_rect
*clip
= &state
->clip
;
13355 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
13356 struct intel_crtc
*intel_crtc
;
13360 crtc
= crtc
? crtc
: plane
->crtc
;
13361 intel_crtc
= to_intel_crtc(crtc
);
13363 ret
= drm_plane_helper_check_update(plane
, crtc
, fb
,
13365 DRM_PLANE_HELPER_NO_SCALING
,
13366 DRM_PLANE_HELPER_NO_SCALING
,
13367 true, true, &state
->visible
);
13372 /* if we want to turn off the cursor ignore width and height */
13376 /* Check for which cursor types we support */
13377 if (!cursor_size_ok(dev
, state
->base
.crtc_w
, state
->base
.crtc_h
)) {
13378 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13379 state
->base
.crtc_w
, state
->base
.crtc_h
);
13383 stride
= roundup_pow_of_two(state
->base
.crtc_w
) * 4;
13384 if (obj
->base
.size
< stride
* state
->base
.crtc_h
) {
13385 DRM_DEBUG_KMS("buffer is too small\n");
13389 if (fb
->modifier
[0] != DRM_FORMAT_MOD_NONE
) {
13390 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13395 if (intel_crtc
->active
) {
13396 if (plane
->state
->crtc_w
!= state
->base
.crtc_w
)
13397 intel_crtc
->atomic
.update_wm
= true;
13399 intel_crtc
->atomic
.fb_bits
|=
13400 INTEL_FRONTBUFFER_CURSOR(intel_crtc
->pipe
);
13407 intel_disable_cursor_plane(struct drm_plane
*plane
,
13408 struct drm_crtc
*crtc
,
13411 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13415 intel_crtc
->cursor_bo
= NULL
;
13416 intel_crtc
->cursor_addr
= 0;
13419 intel_crtc_update_cursor(crtc
, false);
13423 intel_commit_cursor_plane(struct drm_plane
*plane
,
13424 struct intel_plane_state
*state
)
13426 struct drm_crtc
*crtc
= state
->base
.crtc
;
13427 struct drm_device
*dev
= plane
->dev
;
13428 struct intel_crtc
*intel_crtc
;
13429 struct drm_i915_gem_object
*obj
= intel_fb_obj(state
->base
.fb
);
13432 crtc
= crtc
? crtc
: plane
->crtc
;
13433 intel_crtc
= to_intel_crtc(crtc
);
13435 plane
->fb
= state
->base
.fb
;
13436 crtc
->cursor_x
= state
->base
.crtc_x
;
13437 crtc
->cursor_y
= state
->base
.crtc_y
;
13439 if (intel_crtc
->cursor_bo
== obj
)
13444 else if (!INTEL_INFO(dev
)->cursor_needs_physical
)
13445 addr
= i915_gem_obj_ggtt_offset(obj
);
13447 addr
= obj
->phys_handle
->busaddr
;
13449 intel_crtc
->cursor_addr
= addr
;
13450 intel_crtc
->cursor_bo
= obj
;
13453 if (intel_crtc
->active
)
13454 intel_crtc_update_cursor(crtc
, state
->visible
);
13457 static struct drm_plane
*intel_cursor_plane_create(struct drm_device
*dev
,
13460 struct intel_plane
*cursor
;
13461 struct intel_plane_state
*state
;
13463 cursor
= kzalloc(sizeof(*cursor
), GFP_KERNEL
);
13464 if (cursor
== NULL
)
13467 state
= intel_create_plane_state(&cursor
->base
);
13472 cursor
->base
.state
= &state
->base
;
13474 cursor
->can_scale
= false;
13475 cursor
->max_downscale
= 1;
13476 cursor
->pipe
= pipe
;
13477 cursor
->plane
= pipe
;
13478 cursor
->check_plane
= intel_check_cursor_plane
;
13479 cursor
->commit_plane
= intel_commit_cursor_plane
;
13480 cursor
->disable_plane
= intel_disable_cursor_plane
;
13482 drm_universal_plane_init(dev
, &cursor
->base
, 0,
13483 &intel_plane_funcs
,
13484 intel_cursor_formats
,
13485 ARRAY_SIZE(intel_cursor_formats
),
13486 DRM_PLANE_TYPE_CURSOR
);
13488 if (INTEL_INFO(dev
)->gen
>= 4) {
13489 if (!dev
->mode_config
.rotation_property
)
13490 dev
->mode_config
.rotation_property
=
13491 drm_mode_create_rotation_property(dev
,
13492 BIT(DRM_ROTATE_0
) |
13493 BIT(DRM_ROTATE_180
));
13494 if (dev
->mode_config
.rotation_property
)
13495 drm_object_attach_property(&cursor
->base
.base
,
13496 dev
->mode_config
.rotation_property
,
13497 state
->base
.rotation
);
13500 if (INTEL_INFO(dev
)->gen
>=9)
13501 state
->scaler_id
= -1;
13503 drm_plane_helper_add(&cursor
->base
, &intel_plane_helper_funcs
);
13505 return &cursor
->base
;
13508 static void skl_init_scalers(struct drm_device
*dev
, struct intel_crtc
*intel_crtc
,
13509 struct intel_crtc_state
*crtc_state
)
13512 struct intel_scaler
*intel_scaler
;
13513 struct intel_crtc_scaler_state
*scaler_state
= &crtc_state
->scaler_state
;
13515 for (i
= 0; i
< intel_crtc
->num_scalers
; i
++) {
13516 intel_scaler
= &scaler_state
->scalers
[i
];
13517 intel_scaler
->in_use
= 0;
13518 intel_scaler
->id
= i
;
13520 intel_scaler
->mode
= PS_SCALER_MODE_DYN
;
13523 scaler_state
->scaler_id
= -1;
13526 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
13528 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13529 struct intel_crtc
*intel_crtc
;
13530 struct intel_crtc_state
*crtc_state
= NULL
;
13531 struct drm_plane
*primary
= NULL
;
13532 struct drm_plane
*cursor
= NULL
;
13535 intel_crtc
= kzalloc(sizeof(*intel_crtc
), GFP_KERNEL
);
13536 if (intel_crtc
== NULL
)
13539 crtc_state
= kzalloc(sizeof(*crtc_state
), GFP_KERNEL
);
13542 intel_crtc
->config
= crtc_state
;
13543 intel_crtc
->base
.state
= &crtc_state
->base
;
13544 crtc_state
->base
.crtc
= &intel_crtc
->base
;
13546 /* initialize shared scalers */
13547 if (INTEL_INFO(dev
)->gen
>= 9) {
13548 if (pipe
== PIPE_C
)
13549 intel_crtc
->num_scalers
= 1;
13551 intel_crtc
->num_scalers
= SKL_NUM_SCALERS
;
13553 skl_init_scalers(dev
, intel_crtc
, crtc_state
);
13556 primary
= intel_primary_plane_create(dev
, pipe
);
13560 cursor
= intel_cursor_plane_create(dev
, pipe
);
13564 ret
= drm_crtc_init_with_planes(dev
, &intel_crtc
->base
, primary
,
13565 cursor
, &intel_crtc_funcs
);
13569 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
13570 for (i
= 0; i
< 256; i
++) {
13571 intel_crtc
->lut_r
[i
] = i
;
13572 intel_crtc
->lut_g
[i
] = i
;
13573 intel_crtc
->lut_b
[i
] = i
;
13577 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13578 * is hooked to pipe B. Hence we want plane A feeding pipe B.
13580 intel_crtc
->pipe
= pipe
;
13581 intel_crtc
->plane
= pipe
;
13582 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4) {
13583 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13584 intel_crtc
->plane
= !pipe
;
13587 intel_crtc
->cursor_base
= ~0;
13588 intel_crtc
->cursor_cntl
= ~0;
13589 intel_crtc
->cursor_size
= ~0;
13591 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
13592 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
13593 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
13594 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
13596 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
13598 WARN_ON(drm_crtc_index(&intel_crtc
->base
) != intel_crtc
->pipe
);
13603 drm_plane_cleanup(primary
);
13605 drm_plane_cleanup(cursor
);
13610 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
)
13612 struct drm_encoder
*encoder
= connector
->base
.encoder
;
13613 struct drm_device
*dev
= connector
->base
.dev
;
13615 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
13617 if (!encoder
|| WARN_ON(!encoder
->crtc
))
13618 return INVALID_PIPE
;
13620 return to_intel_crtc(encoder
->crtc
)->pipe
;
13623 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
13624 struct drm_file
*file
)
13626 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
13627 struct drm_crtc
*drmmode_crtc
;
13628 struct intel_crtc
*crtc
;
13630 drmmode_crtc
= drm_crtc_find(dev
, pipe_from_crtc_id
->crtc_id
);
13632 if (!drmmode_crtc
) {
13633 DRM_ERROR("no such CRTC id\n");
13637 crtc
= to_intel_crtc(drmmode_crtc
);
13638 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
13643 static int intel_encoder_clones(struct intel_encoder
*encoder
)
13645 struct drm_device
*dev
= encoder
->base
.dev
;
13646 struct intel_encoder
*source_encoder
;
13647 int index_mask
= 0;
13650 for_each_intel_encoder(dev
, source_encoder
) {
13651 if (encoders_cloneable(encoder
, source_encoder
))
13652 index_mask
|= (1 << entry
);
13660 static bool has_edp_a(struct drm_device
*dev
)
13662 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13664 if (!IS_MOBILE(dev
))
13667 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
13670 if (IS_GEN5(dev
) && (I915_READ(FUSE_STRAP
) & ILK_eDP_A_DISABLE
))
13676 static bool intel_crt_present(struct drm_device
*dev
)
13678 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13680 if (INTEL_INFO(dev
)->gen
>= 9)
13683 if (IS_HSW_ULT(dev
) || IS_BDW_ULT(dev
))
13686 if (IS_CHERRYVIEW(dev
))
13689 if (IS_VALLEYVIEW(dev
) && !dev_priv
->vbt
.int_crt_support
)
13695 static void intel_setup_outputs(struct drm_device
*dev
)
13697 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13698 struct intel_encoder
*encoder
;
13699 bool dpd_is_edp
= false;
13701 intel_lvds_init(dev
);
13703 if (intel_crt_present(dev
))
13704 intel_crt_init(dev
);
13706 if (IS_BROXTON(dev
)) {
13708 * FIXME: Broxton doesn't support port detection via the
13709 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13710 * detect the ports.
13712 intel_ddi_init(dev
, PORT_A
);
13713 intel_ddi_init(dev
, PORT_B
);
13714 intel_ddi_init(dev
, PORT_C
);
13715 } else if (HAS_DDI(dev
)) {
13719 * Haswell uses DDI functions to detect digital outputs.
13720 * On SKL pre-D0 the strap isn't connected, so we assume
13723 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
13724 /* WaIgnoreDDIAStrap: skl */
13726 (IS_SKYLAKE(dev
) && INTEL_REVID(dev
) < SKL_REVID_D0
))
13727 intel_ddi_init(dev
, PORT_A
);
13729 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13731 found
= I915_READ(SFUSE_STRAP
);
13733 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
13734 intel_ddi_init(dev
, PORT_B
);
13735 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
13736 intel_ddi_init(dev
, PORT_C
);
13737 if (found
& SFUSE_STRAP_DDID_DETECTED
)
13738 intel_ddi_init(dev
, PORT_D
);
13739 } else if (HAS_PCH_SPLIT(dev
)) {
13741 dpd_is_edp
= intel_dp_is_edp(dev
, PORT_D
);
13743 if (has_edp_a(dev
))
13744 intel_dp_init(dev
, DP_A
, PORT_A
);
13746 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
13747 /* PCH SDVOB multiplex with HDMIB */
13748 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
13750 intel_hdmi_init(dev
, PCH_HDMIB
, PORT_B
);
13751 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
13752 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
13755 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
13756 intel_hdmi_init(dev
, PCH_HDMIC
, PORT_C
);
13758 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
13759 intel_hdmi_init(dev
, PCH_HDMID
, PORT_D
);
13761 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
13762 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
13764 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
13765 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
13766 } else if (IS_VALLEYVIEW(dev
)) {
13768 * The DP_DETECTED bit is the latched state of the DDC
13769 * SDA pin at boot. However since eDP doesn't require DDC
13770 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13771 * eDP ports may have been muxed to an alternate function.
13772 * Thus we can't rely on the DP_DETECTED bit alone to detect
13773 * eDP ports. Consult the VBT as well as DP_DETECTED to
13774 * detect eDP ports.
13776 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIB
) & SDVO_DETECTED
&&
13777 !intel_dp_is_edp(dev
, PORT_B
))
13778 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIB
,
13780 if (I915_READ(VLV_DISPLAY_BASE
+ DP_B
) & DP_DETECTED
||
13781 intel_dp_is_edp(dev
, PORT_B
))
13782 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_B
, PORT_B
);
13784 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIC
) & SDVO_DETECTED
&&
13785 !intel_dp_is_edp(dev
, PORT_C
))
13786 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIC
,
13788 if (I915_READ(VLV_DISPLAY_BASE
+ DP_C
) & DP_DETECTED
||
13789 intel_dp_is_edp(dev
, PORT_C
))
13790 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_C
, PORT_C
);
13792 if (IS_CHERRYVIEW(dev
)) {
13793 if (I915_READ(VLV_DISPLAY_BASE
+ CHV_HDMID
) & SDVO_DETECTED
)
13794 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ CHV_HDMID
,
13796 /* eDP not supported on port D, so don't check VBT */
13797 if (I915_READ(VLV_DISPLAY_BASE
+ DP_D
) & DP_DETECTED
)
13798 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_D
, PORT_D
);
13801 intel_dsi_init(dev
);
13802 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
13803 bool found
= false;
13805 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
13806 DRM_DEBUG_KMS("probing SDVOB\n");
13807 found
= intel_sdvo_init(dev
, GEN3_SDVOB
, true);
13808 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
13809 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
13810 intel_hdmi_init(dev
, GEN4_HDMIB
, PORT_B
);
13813 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
))
13814 intel_dp_init(dev
, DP_B
, PORT_B
);
13817 /* Before G4X SDVOC doesn't have its own detect register */
13819 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
13820 DRM_DEBUG_KMS("probing SDVOC\n");
13821 found
= intel_sdvo_init(dev
, GEN3_SDVOC
, false);
13824 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
13826 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
13827 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
13828 intel_hdmi_init(dev
, GEN4_HDMIC
, PORT_C
);
13830 if (SUPPORTS_INTEGRATED_DP(dev
))
13831 intel_dp_init(dev
, DP_C
, PORT_C
);
13834 if (SUPPORTS_INTEGRATED_DP(dev
) &&
13835 (I915_READ(DP_D
) & DP_DETECTED
))
13836 intel_dp_init(dev
, DP_D
, PORT_D
);
13837 } else if (IS_GEN2(dev
))
13838 intel_dvo_init(dev
);
13840 if (SUPPORTS_TV(dev
))
13841 intel_tv_init(dev
);
13843 intel_psr_init(dev
);
13845 for_each_intel_encoder(dev
, encoder
) {
13846 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
13847 encoder
->base
.possible_clones
=
13848 intel_encoder_clones(encoder
);
13851 intel_init_pch_refclk(dev
);
13853 drm_helper_move_panel_connectors_to_head(dev
);
13856 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
13858 struct drm_device
*dev
= fb
->dev
;
13859 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
13861 drm_framebuffer_cleanup(fb
);
13862 mutex_lock(&dev
->struct_mutex
);
13863 WARN_ON(!intel_fb
->obj
->framebuffer_references
--);
13864 drm_gem_object_unreference(&intel_fb
->obj
->base
);
13865 mutex_unlock(&dev
->struct_mutex
);
13869 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
13870 struct drm_file
*file
,
13871 unsigned int *handle
)
13873 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
13874 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
13876 return drm_gem_handle_create(file
, &obj
->base
, handle
);
13879 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
13880 .destroy
= intel_user_framebuffer_destroy
,
13881 .create_handle
= intel_user_framebuffer_create_handle
,
13885 u32
intel_fb_pitch_limit(struct drm_device
*dev
, uint64_t fb_modifier
,
13886 uint32_t pixel_format
)
13888 u32 gen
= INTEL_INFO(dev
)->gen
;
13891 /* "The stride in bytes must not exceed the of the size of 8K
13892 * pixels and 32K bytes."
13894 return min(8192*drm_format_plane_cpp(pixel_format
, 0), 32768);
13895 } else if (gen
>= 5 && !IS_VALLEYVIEW(dev
)) {
13897 } else if (gen
>= 4) {
13898 if (fb_modifier
== I915_FORMAT_MOD_X_TILED
)
13902 } else if (gen
>= 3) {
13903 if (fb_modifier
== I915_FORMAT_MOD_X_TILED
)
13908 /* XXX DSPC is limited to 4k tiled */
13913 static int intel_framebuffer_init(struct drm_device
*dev
,
13914 struct intel_framebuffer
*intel_fb
,
13915 struct drm_mode_fb_cmd2
*mode_cmd
,
13916 struct drm_i915_gem_object
*obj
)
13918 unsigned int aligned_height
;
13920 u32 pitch_limit
, stride_alignment
;
13922 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
13924 if (mode_cmd
->flags
& DRM_MODE_FB_MODIFIERS
) {
13925 /* Enforce that fb modifier and tiling mode match, but only for
13926 * X-tiled. This is needed for FBC. */
13927 if (!!(obj
->tiling_mode
== I915_TILING_X
) !=
13928 !!(mode_cmd
->modifier
[0] == I915_FORMAT_MOD_X_TILED
)) {
13929 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
13933 if (obj
->tiling_mode
== I915_TILING_X
)
13934 mode_cmd
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
13935 else if (obj
->tiling_mode
== I915_TILING_Y
) {
13936 DRM_DEBUG("No Y tiling for legacy addfb\n");
13941 /* Passed in modifier sanity checking. */
13942 switch (mode_cmd
->modifier
[0]) {
13943 case I915_FORMAT_MOD_Y_TILED
:
13944 case I915_FORMAT_MOD_Yf_TILED
:
13945 if (INTEL_INFO(dev
)->gen
< 9) {
13946 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
13947 mode_cmd
->modifier
[0]);
13950 case DRM_FORMAT_MOD_NONE
:
13951 case I915_FORMAT_MOD_X_TILED
:
13954 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
13955 mode_cmd
->modifier
[0]);
13959 stride_alignment
= intel_fb_stride_alignment(dev
, mode_cmd
->modifier
[0],
13960 mode_cmd
->pixel_format
);
13961 if (mode_cmd
->pitches
[0] & (stride_alignment
- 1)) {
13962 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
13963 mode_cmd
->pitches
[0], stride_alignment
);
13967 pitch_limit
= intel_fb_pitch_limit(dev
, mode_cmd
->modifier
[0],
13968 mode_cmd
->pixel_format
);
13969 if (mode_cmd
->pitches
[0] > pitch_limit
) {
13970 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
13971 mode_cmd
->modifier
[0] != DRM_FORMAT_MOD_NONE
?
13972 "tiled" : "linear",
13973 mode_cmd
->pitches
[0], pitch_limit
);
13977 if (mode_cmd
->modifier
[0] == I915_FORMAT_MOD_X_TILED
&&
13978 mode_cmd
->pitches
[0] != obj
->stride
) {
13979 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
13980 mode_cmd
->pitches
[0], obj
->stride
);
13984 /* Reject formats not supported by any plane early. */
13985 switch (mode_cmd
->pixel_format
) {
13986 case DRM_FORMAT_C8
:
13987 case DRM_FORMAT_RGB565
:
13988 case DRM_FORMAT_XRGB8888
:
13989 case DRM_FORMAT_ARGB8888
:
13991 case DRM_FORMAT_XRGB1555
:
13992 case DRM_FORMAT_ARGB1555
:
13993 if (INTEL_INFO(dev
)->gen
> 3) {
13994 DRM_DEBUG("unsupported pixel format: %s\n",
13995 drm_get_format_name(mode_cmd
->pixel_format
));
13999 case DRM_FORMAT_XBGR8888
:
14000 case DRM_FORMAT_ABGR8888
:
14001 case DRM_FORMAT_XRGB2101010
:
14002 case DRM_FORMAT_ARGB2101010
:
14003 case DRM_FORMAT_XBGR2101010
:
14004 case DRM_FORMAT_ABGR2101010
:
14005 if (INTEL_INFO(dev
)->gen
< 4) {
14006 DRM_DEBUG("unsupported pixel format: %s\n",
14007 drm_get_format_name(mode_cmd
->pixel_format
));
14011 case DRM_FORMAT_YUYV
:
14012 case DRM_FORMAT_UYVY
:
14013 case DRM_FORMAT_YVYU
:
14014 case DRM_FORMAT_VYUY
:
14015 if (INTEL_INFO(dev
)->gen
< 5) {
14016 DRM_DEBUG("unsupported pixel format: %s\n",
14017 drm_get_format_name(mode_cmd
->pixel_format
));
14022 DRM_DEBUG("unsupported pixel format: %s\n",
14023 drm_get_format_name(mode_cmd
->pixel_format
));
14027 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14028 if (mode_cmd
->offsets
[0] != 0)
14031 aligned_height
= intel_fb_align_height(dev
, mode_cmd
->height
,
14032 mode_cmd
->pixel_format
,
14033 mode_cmd
->modifier
[0]);
14034 /* FIXME drm helper for size checks (especially planar formats)? */
14035 if (obj
->base
.size
< aligned_height
* mode_cmd
->pitches
[0])
14038 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
14039 intel_fb
->obj
= obj
;
14040 intel_fb
->obj
->framebuffer_references
++;
14042 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
14044 DRM_ERROR("framebuffer init failed %d\n", ret
);
14051 static struct drm_framebuffer
*
14052 intel_user_framebuffer_create(struct drm_device
*dev
,
14053 struct drm_file
*filp
,
14054 struct drm_mode_fb_cmd2
*mode_cmd
)
14056 struct drm_i915_gem_object
*obj
;
14058 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
14059 mode_cmd
->handles
[0]));
14060 if (&obj
->base
== NULL
)
14061 return ERR_PTR(-ENOENT
);
14063 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
14066 #ifndef CONFIG_DRM_I915_FBDEV
14067 static inline void intel_fbdev_output_poll_changed(struct drm_device
*dev
)
14072 static const struct drm_mode_config_funcs intel_mode_funcs
= {
14073 .fb_create
= intel_user_framebuffer_create
,
14074 .output_poll_changed
= intel_fbdev_output_poll_changed
,
14075 .atomic_check
= intel_atomic_check
,
14076 .atomic_commit
= intel_atomic_commit
,
14079 /* Set up chip specific display functions */
14080 static void intel_init_display(struct drm_device
*dev
)
14082 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14084 if (HAS_PCH_SPLIT(dev
) || IS_G4X(dev
))
14085 dev_priv
->display
.find_dpll
= g4x_find_best_dpll
;
14086 else if (IS_CHERRYVIEW(dev
))
14087 dev_priv
->display
.find_dpll
= chv_find_best_dpll
;
14088 else if (IS_VALLEYVIEW(dev
))
14089 dev_priv
->display
.find_dpll
= vlv_find_best_dpll
;
14090 else if (IS_PINEVIEW(dev
))
14091 dev_priv
->display
.find_dpll
= pnv_find_best_dpll
;
14093 dev_priv
->display
.find_dpll
= i9xx_find_best_dpll
;
14095 if (INTEL_INFO(dev
)->gen
>= 9) {
14096 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
14097 dev_priv
->display
.get_initial_plane_config
=
14098 skylake_get_initial_plane_config
;
14099 dev_priv
->display
.crtc_compute_clock
=
14100 haswell_crtc_compute_clock
;
14101 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
14102 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
14103 dev_priv
->display
.off
= ironlake_crtc_off
;
14104 dev_priv
->display
.update_primary_plane
=
14105 skylake_update_primary_plane
;
14106 } else if (HAS_DDI(dev
)) {
14107 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
14108 dev_priv
->display
.get_initial_plane_config
=
14109 ironlake_get_initial_plane_config
;
14110 dev_priv
->display
.crtc_compute_clock
=
14111 haswell_crtc_compute_clock
;
14112 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
14113 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
14114 dev_priv
->display
.off
= ironlake_crtc_off
;
14115 dev_priv
->display
.update_primary_plane
=
14116 ironlake_update_primary_plane
;
14117 } else if (HAS_PCH_SPLIT(dev
)) {
14118 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
14119 dev_priv
->display
.get_initial_plane_config
=
14120 ironlake_get_initial_plane_config
;
14121 dev_priv
->display
.crtc_compute_clock
=
14122 ironlake_crtc_compute_clock
;
14123 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
14124 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
14125 dev_priv
->display
.off
= ironlake_crtc_off
;
14126 dev_priv
->display
.update_primary_plane
=
14127 ironlake_update_primary_plane
;
14128 } else if (IS_VALLEYVIEW(dev
)) {
14129 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
14130 dev_priv
->display
.get_initial_plane_config
=
14131 i9xx_get_initial_plane_config
;
14132 dev_priv
->display
.crtc_compute_clock
= i9xx_crtc_compute_clock
;
14133 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
14134 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
14135 dev_priv
->display
.off
= i9xx_crtc_off
;
14136 dev_priv
->display
.update_primary_plane
=
14137 i9xx_update_primary_plane
;
14139 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
14140 dev_priv
->display
.get_initial_plane_config
=
14141 i9xx_get_initial_plane_config
;
14142 dev_priv
->display
.crtc_compute_clock
= i9xx_crtc_compute_clock
;
14143 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
14144 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
14145 dev_priv
->display
.off
= i9xx_crtc_off
;
14146 dev_priv
->display
.update_primary_plane
=
14147 i9xx_update_primary_plane
;
14150 /* Returns the core display clock speed */
14151 if (IS_SKYLAKE(dev
))
14152 dev_priv
->display
.get_display_clock_speed
=
14153 skylake_get_display_clock_speed
;
14154 else if (IS_BROADWELL(dev
))
14155 dev_priv
->display
.get_display_clock_speed
=
14156 broadwell_get_display_clock_speed
;
14157 else if (IS_HASWELL(dev
))
14158 dev_priv
->display
.get_display_clock_speed
=
14159 haswell_get_display_clock_speed
;
14160 else if (IS_VALLEYVIEW(dev
))
14161 dev_priv
->display
.get_display_clock_speed
=
14162 valleyview_get_display_clock_speed
;
14163 else if (IS_GEN5(dev
))
14164 dev_priv
->display
.get_display_clock_speed
=
14165 ilk_get_display_clock_speed
;
14166 else if (IS_I945G(dev
) || IS_BROADWATER(dev
) ||
14167 IS_GEN6(dev
) || IS_IVYBRIDGE(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
14168 dev_priv
->display
.get_display_clock_speed
=
14169 i945_get_display_clock_speed
;
14170 else if (IS_I915G(dev
))
14171 dev_priv
->display
.get_display_clock_speed
=
14172 i915_get_display_clock_speed
;
14173 else if (IS_I945GM(dev
) || IS_845G(dev
))
14174 dev_priv
->display
.get_display_clock_speed
=
14175 i9xx_misc_get_display_clock_speed
;
14176 else if (IS_PINEVIEW(dev
))
14177 dev_priv
->display
.get_display_clock_speed
=
14178 pnv_get_display_clock_speed
;
14179 else if (IS_I915GM(dev
))
14180 dev_priv
->display
.get_display_clock_speed
=
14181 i915gm_get_display_clock_speed
;
14182 else if (IS_I865G(dev
))
14183 dev_priv
->display
.get_display_clock_speed
=
14184 i865_get_display_clock_speed
;
14185 else if (IS_I85X(dev
))
14186 dev_priv
->display
.get_display_clock_speed
=
14187 i855_get_display_clock_speed
;
14188 else /* 852, 830 */
14189 dev_priv
->display
.get_display_clock_speed
=
14190 i830_get_display_clock_speed
;
14192 if (IS_GEN5(dev
)) {
14193 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
14194 } else if (IS_GEN6(dev
)) {
14195 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
14196 } else if (IS_IVYBRIDGE(dev
)) {
14197 /* FIXME: detect B0+ stepping and use auto training */
14198 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
14199 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
14200 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
14201 } else if (IS_VALLEYVIEW(dev
)) {
14202 dev_priv
->display
.modeset_global_resources
=
14203 valleyview_modeset_global_resources
;
14204 } else if (IS_BROXTON(dev
)) {
14205 dev_priv
->display
.modeset_global_resources
=
14206 broxton_modeset_global_resources
;
14209 switch (INTEL_INFO(dev
)->gen
) {
14211 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
14215 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
14220 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
14224 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
14227 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14228 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
14231 /* Drop through - unsupported since execlist only. */
14233 /* Default just returns -ENODEV to indicate unsupported */
14234 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
14237 intel_panel_init_backlight_funcs(dev
);
14239 mutex_init(&dev_priv
->pps_mutex
);
14243 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14244 * resume, or other times. This quirk makes sure that's the case for
14245 * affected systems.
14247 static void quirk_pipea_force(struct drm_device
*dev
)
14249 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14251 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
14252 DRM_INFO("applying pipe a force quirk\n");
14255 static void quirk_pipeb_force(struct drm_device
*dev
)
14257 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14259 dev_priv
->quirks
|= QUIRK_PIPEB_FORCE
;
14260 DRM_INFO("applying pipe b force quirk\n");
14264 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14266 static void quirk_ssc_force_disable(struct drm_device
*dev
)
14268 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14269 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
14270 DRM_INFO("applying lvds SSC disable quirk\n");
14274 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14277 static void quirk_invert_brightness(struct drm_device
*dev
)
14279 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14280 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
14281 DRM_INFO("applying inverted panel brightness quirk\n");
14284 /* Some VBT's incorrectly indicate no backlight is present */
14285 static void quirk_backlight_present(struct drm_device
*dev
)
14287 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14288 dev_priv
->quirks
|= QUIRK_BACKLIGHT_PRESENT
;
14289 DRM_INFO("applying backlight present quirk\n");
14292 struct intel_quirk
{
14294 int subsystem_vendor
;
14295 int subsystem_device
;
14296 void (*hook
)(struct drm_device
*dev
);
14299 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14300 struct intel_dmi_quirk
{
14301 void (*hook
)(struct drm_device
*dev
);
14302 const struct dmi_system_id (*dmi_id_list
)[];
14305 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
14307 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
14311 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
14313 .dmi_id_list
= &(const struct dmi_system_id
[]) {
14315 .callback
= intel_dmi_reverse_brightness
,
14316 .ident
= "NCR Corporation",
14317 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
14318 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
14321 { } /* terminating entry */
14323 .hook
= quirk_invert_brightness
,
14327 static struct intel_quirk intel_quirks
[] = {
14328 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14329 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
14331 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14332 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
14334 /* 830 needs to leave pipe A & dpll A up */
14335 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
14337 /* 830 needs to leave pipe B & dpll B up */
14338 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipeb_force
},
14340 /* Lenovo U160 cannot use SSC on LVDS */
14341 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
14343 /* Sony Vaio Y cannot use SSC on LVDS */
14344 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
14346 /* Acer Aspire 5734Z must invert backlight brightness */
14347 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
14349 /* Acer/eMachines G725 */
14350 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness
},
14352 /* Acer/eMachines e725 */
14353 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness
},
14355 /* Acer/Packard Bell NCL20 */
14356 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness
},
14358 /* Acer Aspire 4736Z */
14359 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness
},
14361 /* Acer Aspire 5336 */
14362 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness
},
14364 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14365 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present
},
14367 /* Acer C720 Chromebook (Core i3 4005U) */
14368 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present
},
14370 /* Apple Macbook 2,1 (Core 2 T7400) */
14371 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present
},
14373 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14374 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present
},
14376 /* HP Chromebook 14 (Celeron 2955U) */
14377 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present
},
14379 /* Dell Chromebook 11 */
14380 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present
},
14383 static void intel_init_quirks(struct drm_device
*dev
)
14385 struct pci_dev
*d
= dev
->pdev
;
14388 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
14389 struct intel_quirk
*q
= &intel_quirks
[i
];
14391 if (d
->device
== q
->device
&&
14392 (d
->subsystem_vendor
== q
->subsystem_vendor
||
14393 q
->subsystem_vendor
== PCI_ANY_ID
) &&
14394 (d
->subsystem_device
== q
->subsystem_device
||
14395 q
->subsystem_device
== PCI_ANY_ID
))
14398 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
14399 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
14400 intel_dmi_quirks
[i
].hook(dev
);
14404 /* Disable the VGA plane that we never use */
14405 static void i915_disable_vga(struct drm_device
*dev
)
14407 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14409 u32 vga_reg
= i915_vgacntrl_reg(dev
);
14411 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14412 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
14413 outb(SR01
, VGA_SR_INDEX
);
14414 sr1
= inb(VGA_SR_DATA
);
14415 outb(sr1
| 1<<5, VGA_SR_DATA
);
14416 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
14419 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
14420 POSTING_READ(vga_reg
);
14423 void intel_modeset_init_hw(struct drm_device
*dev
)
14425 intel_prepare_ddi(dev
);
14427 if (IS_VALLEYVIEW(dev
))
14428 vlv_update_cdclk(dev
);
14430 intel_init_clock_gating(dev
);
14432 intel_enable_gt_powersave(dev
);
14435 void intel_modeset_init(struct drm_device
*dev
)
14437 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14440 struct intel_crtc
*crtc
;
14442 drm_mode_config_init(dev
);
14444 dev
->mode_config
.min_width
= 0;
14445 dev
->mode_config
.min_height
= 0;
14447 dev
->mode_config
.preferred_depth
= 24;
14448 dev
->mode_config
.prefer_shadow
= 1;
14450 dev
->mode_config
.allow_fb_modifiers
= true;
14452 dev
->mode_config
.funcs
= &intel_mode_funcs
;
14454 intel_init_quirks(dev
);
14456 intel_init_pm(dev
);
14458 if (INTEL_INFO(dev
)->num_pipes
== 0)
14461 intel_init_display(dev
);
14462 intel_init_audio(dev
);
14464 if (IS_GEN2(dev
)) {
14465 dev
->mode_config
.max_width
= 2048;
14466 dev
->mode_config
.max_height
= 2048;
14467 } else if (IS_GEN3(dev
)) {
14468 dev
->mode_config
.max_width
= 4096;
14469 dev
->mode_config
.max_height
= 4096;
14471 dev
->mode_config
.max_width
= 8192;
14472 dev
->mode_config
.max_height
= 8192;
14475 if (IS_845G(dev
) || IS_I865G(dev
)) {
14476 dev
->mode_config
.cursor_width
= IS_845G(dev
) ? 64 : 512;
14477 dev
->mode_config
.cursor_height
= 1023;
14478 } else if (IS_GEN2(dev
)) {
14479 dev
->mode_config
.cursor_width
= GEN2_CURSOR_WIDTH
;
14480 dev
->mode_config
.cursor_height
= GEN2_CURSOR_HEIGHT
;
14482 dev
->mode_config
.cursor_width
= MAX_CURSOR_WIDTH
;
14483 dev
->mode_config
.cursor_height
= MAX_CURSOR_HEIGHT
;
14486 dev
->mode_config
.fb_base
= dev_priv
->gtt
.mappable_base
;
14488 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14489 INTEL_INFO(dev
)->num_pipes
,
14490 INTEL_INFO(dev
)->num_pipes
> 1 ? "s" : "");
14492 for_each_pipe(dev_priv
, pipe
) {
14493 intel_crtc_init(dev
, pipe
);
14494 for_each_sprite(dev_priv
, pipe
, sprite
) {
14495 ret
= intel_plane_init(dev
, pipe
, sprite
);
14497 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14498 pipe_name(pipe
), sprite_name(pipe
, sprite
), ret
);
14502 intel_init_dpio(dev
);
14504 intel_shared_dpll_init(dev
);
14506 /* Just disable it once at startup */
14507 i915_disable_vga(dev
);
14508 intel_setup_outputs(dev
);
14510 /* Just in case the BIOS is doing something questionable. */
14511 intel_fbc_disable(dev
);
14513 drm_modeset_lock_all(dev
);
14514 intel_modeset_setup_hw_state(dev
, false);
14515 drm_modeset_unlock_all(dev
);
14517 for_each_intel_crtc(dev
, crtc
) {
14522 * Note that reserving the BIOS fb up front prevents us
14523 * from stuffing other stolen allocations like the ring
14524 * on top. This prevents some ugliness at boot time, and
14525 * can even allow for smooth boot transitions if the BIOS
14526 * fb is large enough for the active pipe configuration.
14528 if (dev_priv
->display
.get_initial_plane_config
) {
14529 dev_priv
->display
.get_initial_plane_config(crtc
,
14530 &crtc
->plane_config
);
14532 * If the fb is shared between multiple heads, we'll
14533 * just get the first one.
14535 intel_find_initial_plane_obj(crtc
, &crtc
->plane_config
);
14540 static void intel_enable_pipe_a(struct drm_device
*dev
)
14542 struct intel_connector
*connector
;
14543 struct drm_connector
*crt
= NULL
;
14544 struct intel_load_detect_pipe load_detect_temp
;
14545 struct drm_modeset_acquire_ctx
*ctx
= dev
->mode_config
.acquire_ctx
;
14547 /* We can't just switch on the pipe A, we need to set things up with a
14548 * proper mode and output configuration. As a gross hack, enable pipe A
14549 * by enabling the load detect pipe once. */
14550 for_each_intel_connector(dev
, connector
) {
14551 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
14552 crt
= &connector
->base
;
14560 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
, ctx
))
14561 intel_release_load_detect_pipe(crt
, &load_detect_temp
, ctx
);
14565 intel_check_plane_mapping(struct intel_crtc
*crtc
)
14567 struct drm_device
*dev
= crtc
->base
.dev
;
14568 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14571 if (INTEL_INFO(dev
)->num_pipes
== 1)
14574 reg
= DSPCNTR(!crtc
->plane
);
14575 val
= I915_READ(reg
);
14577 if ((val
& DISPLAY_PLANE_ENABLE
) &&
14578 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
14584 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
14586 struct drm_device
*dev
= crtc
->base
.dev
;
14587 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14590 /* Clear any frame start delays used for debugging left by the BIOS */
14591 reg
= PIPECONF(crtc
->config
->cpu_transcoder
);
14592 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
14594 /* restore vblank interrupts to correct state */
14595 drm_crtc_vblank_reset(&crtc
->base
);
14596 if (crtc
->active
) {
14597 update_scanline_offset(crtc
);
14598 drm_crtc_vblank_on(&crtc
->base
);
14601 /* We need to sanitize the plane -> pipe mapping first because this will
14602 * disable the crtc (and hence change the state) if it is wrong. Note
14603 * that gen4+ has a fixed plane -> pipe mapping. */
14604 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
14605 struct intel_connector
*connector
;
14608 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14609 crtc
->base
.base
.id
);
14611 /* Pipe has the wrong plane attached and the plane is active.
14612 * Temporarily change the plane mapping and disable everything
14614 plane
= crtc
->plane
;
14615 to_intel_plane_state(crtc
->base
.primary
->state
)->visible
= true;
14616 crtc
->plane
= !plane
;
14617 intel_crtc_disable_planes(&crtc
->base
);
14618 dev_priv
->display
.crtc_disable(&crtc
->base
);
14619 crtc
->plane
= plane
;
14621 /* ... and break all links. */
14622 for_each_intel_connector(dev
, connector
) {
14623 if (connector
->encoder
->base
.crtc
!= &crtc
->base
)
14626 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
14627 connector
->base
.encoder
= NULL
;
14629 /* multiple connectors may have the same encoder:
14630 * handle them and break crtc link separately */
14631 for_each_intel_connector(dev
, connector
)
14632 if (connector
->encoder
->base
.crtc
== &crtc
->base
) {
14633 connector
->encoder
->base
.crtc
= NULL
;
14634 connector
->encoder
->connectors_active
= false;
14637 WARN_ON(crtc
->active
);
14638 crtc
->base
.state
->enable
= false;
14639 crtc
->base
.state
->active
= false;
14640 crtc
->base
.enabled
= false;
14643 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
14644 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
14645 /* BIOS forgot to enable pipe A, this mostly happens after
14646 * resume. Force-enable the pipe to fix this, the update_dpms
14647 * call below we restore the pipe to the right state, but leave
14648 * the required bits on. */
14649 intel_enable_pipe_a(dev
);
14652 /* Adjust the state of the output pipe according to whether we
14653 * have active connectors/encoders. */
14654 intel_crtc_update_dpms(&crtc
->base
);
14656 if (crtc
->active
!= crtc
->base
.state
->enable
) {
14657 struct intel_encoder
*encoder
;
14659 /* This can happen either due to bugs in the get_hw_state
14660 * functions or because the pipe is force-enabled due to the
14662 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14663 crtc
->base
.base
.id
,
14664 crtc
->base
.state
->enable
? "enabled" : "disabled",
14665 crtc
->active
? "enabled" : "disabled");
14667 crtc
->base
.state
->enable
= crtc
->active
;
14668 crtc
->base
.state
->active
= crtc
->active
;
14669 crtc
->base
.enabled
= crtc
->active
;
14671 /* Because we only establish the connector -> encoder ->
14672 * crtc links if something is active, this means the
14673 * crtc is now deactivated. Break the links. connector
14674 * -> encoder links are only establish when things are
14675 * actually up, hence no need to break them. */
14676 WARN_ON(crtc
->active
);
14678 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
14679 WARN_ON(encoder
->connectors_active
);
14680 encoder
->base
.crtc
= NULL
;
14684 if (crtc
->active
|| HAS_GMCH_DISPLAY(dev
)) {
14686 * We start out with underrun reporting disabled to avoid races.
14687 * For correct bookkeeping mark this on active crtcs.
14689 * Also on gmch platforms we dont have any hardware bits to
14690 * disable the underrun reporting. Which means we need to start
14691 * out with underrun reporting disabled also on inactive pipes,
14692 * since otherwise we'll complain about the garbage we read when
14693 * e.g. coming up after runtime pm.
14695 * No protection against concurrent access is required - at
14696 * worst a fifo underrun happens which also sets this to false.
14698 crtc
->cpu_fifo_underrun_disabled
= true;
14699 crtc
->pch_fifo_underrun_disabled
= true;
14703 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
14705 struct intel_connector
*connector
;
14706 struct drm_device
*dev
= encoder
->base
.dev
;
14708 /* We need to check both for a crtc link (meaning that the
14709 * encoder is active and trying to read from a pipe) and the
14710 * pipe itself being active. */
14711 bool has_active_crtc
= encoder
->base
.crtc
&&
14712 to_intel_crtc(encoder
->base
.crtc
)->active
;
14714 if (encoder
->connectors_active
&& !has_active_crtc
) {
14715 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14716 encoder
->base
.base
.id
,
14717 encoder
->base
.name
);
14719 /* Connector is active, but has no active pipe. This is
14720 * fallout from our resume register restoring. Disable
14721 * the encoder manually again. */
14722 if (encoder
->base
.crtc
) {
14723 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14724 encoder
->base
.base
.id
,
14725 encoder
->base
.name
);
14726 encoder
->disable(encoder
);
14727 if (encoder
->post_disable
)
14728 encoder
->post_disable(encoder
);
14730 encoder
->base
.crtc
= NULL
;
14731 encoder
->connectors_active
= false;
14733 /* Inconsistent output/port/pipe state happens presumably due to
14734 * a bug in one of the get_hw_state functions. Or someplace else
14735 * in our code, like the register restore mess on resume. Clamp
14736 * things to off as a safer default. */
14737 for_each_intel_connector(dev
, connector
) {
14738 if (connector
->encoder
!= encoder
)
14740 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
14741 connector
->base
.encoder
= NULL
;
14744 /* Enabled encoders without active connectors will be fixed in
14745 * the crtc fixup. */
14748 void i915_redisable_vga_power_on(struct drm_device
*dev
)
14750 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14751 u32 vga_reg
= i915_vgacntrl_reg(dev
);
14753 if (!(I915_READ(vga_reg
) & VGA_DISP_DISABLE
)) {
14754 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14755 i915_disable_vga(dev
);
14759 void i915_redisable_vga(struct drm_device
*dev
)
14761 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14763 /* This function can be called both from intel_modeset_setup_hw_state or
14764 * at a very early point in our resume sequence, where the power well
14765 * structures are not yet restored. Since this function is at a very
14766 * paranoid "someone might have enabled VGA while we were not looking"
14767 * level, just check if the power well is enabled instead of trying to
14768 * follow the "don't touch the power well if we don't need it" policy
14769 * the rest of the driver uses. */
14770 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_VGA
))
14773 i915_redisable_vga_power_on(dev
);
14776 static bool primary_get_hw_state(struct intel_crtc
*crtc
)
14778 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
14783 return I915_READ(DSPCNTR(crtc
->plane
)) & DISPLAY_PLANE_ENABLE
;
14786 static void intel_modeset_readout_hw_state(struct drm_device
*dev
)
14788 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14790 struct intel_crtc
*crtc
;
14791 struct intel_encoder
*encoder
;
14792 struct intel_connector
*connector
;
14795 for_each_intel_crtc(dev
, crtc
) {
14796 struct drm_plane
*primary
= crtc
->base
.primary
;
14797 struct intel_plane_state
*plane_state
;
14799 memset(crtc
->config
, 0, sizeof(*crtc
->config
));
14801 crtc
->config
->quirks
|= PIPE_CONFIG_QUIRK_INHERITED_MODE
;
14803 crtc
->active
= dev_priv
->display
.get_pipe_config(crtc
,
14806 crtc
->base
.state
->enable
= crtc
->active
;
14807 crtc
->base
.state
->active
= crtc
->active
;
14808 crtc
->base
.enabled
= crtc
->active
;
14810 plane_state
= to_intel_plane_state(primary
->state
);
14811 plane_state
->visible
= primary_get_hw_state(crtc
);
14813 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
14814 crtc
->base
.base
.id
,
14815 crtc
->active
? "enabled" : "disabled");
14818 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
14819 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
14821 pll
->on
= pll
->get_hw_state(dev_priv
, pll
,
14822 &pll
->config
.hw_state
);
14824 pll
->config
.crtc_mask
= 0;
14825 for_each_intel_crtc(dev
, crtc
) {
14826 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
) {
14828 pll
->config
.crtc_mask
|= 1 << crtc
->pipe
;
14832 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
14833 pll
->name
, pll
->config
.crtc_mask
, pll
->on
);
14835 if (pll
->config
.crtc_mask
)
14836 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
14839 for_each_intel_encoder(dev
, encoder
) {
14842 if (encoder
->get_hw_state(encoder
, &pipe
)) {
14843 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
14844 encoder
->base
.crtc
= &crtc
->base
;
14845 encoder
->get_config(encoder
, crtc
->config
);
14847 encoder
->base
.crtc
= NULL
;
14850 encoder
->connectors_active
= false;
14851 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
14852 encoder
->base
.base
.id
,
14853 encoder
->base
.name
,
14854 encoder
->base
.crtc
? "enabled" : "disabled",
14858 for_each_intel_connector(dev
, connector
) {
14859 if (connector
->get_hw_state(connector
)) {
14860 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
14861 connector
->encoder
->connectors_active
= true;
14862 connector
->base
.encoder
= &connector
->encoder
->base
;
14864 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
14865 connector
->base
.encoder
= NULL
;
14867 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
14868 connector
->base
.base
.id
,
14869 connector
->base
.name
,
14870 connector
->base
.encoder
? "enabled" : "disabled");
14874 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
14875 * and i915 state tracking structures. */
14876 void intel_modeset_setup_hw_state(struct drm_device
*dev
,
14877 bool force_restore
)
14879 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14881 struct intel_crtc
*crtc
;
14882 struct intel_encoder
*encoder
;
14885 intel_modeset_readout_hw_state(dev
);
14888 * Now that we have the config, copy it to each CRTC struct
14889 * Note that this could go away if we move to using crtc_config
14890 * checking everywhere.
14892 for_each_intel_crtc(dev
, crtc
) {
14893 if (crtc
->active
&& i915
.fastboot
) {
14894 intel_mode_from_pipe_config(&crtc
->base
.mode
,
14896 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
14897 crtc
->base
.base
.id
);
14898 drm_mode_debug_printmodeline(&crtc
->base
.mode
);
14902 /* HW state is read out, now we need to sanitize this mess. */
14903 for_each_intel_encoder(dev
, encoder
) {
14904 intel_sanitize_encoder(encoder
);
14907 for_each_pipe(dev_priv
, pipe
) {
14908 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
14909 intel_sanitize_crtc(crtc
);
14910 intel_dump_pipe_config(crtc
, crtc
->config
,
14911 "[setup_hw_state]");
14914 intel_modeset_update_connector_atomic_state(dev
);
14916 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
14917 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
14919 if (!pll
->on
|| pll
->active
)
14922 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll
->name
);
14924 pll
->disable(dev_priv
, pll
);
14929 skl_wm_get_hw_state(dev
);
14930 else if (HAS_PCH_SPLIT(dev
))
14931 ilk_wm_get_hw_state(dev
);
14933 if (force_restore
) {
14934 i915_redisable_vga(dev
);
14937 * We need to use raw interfaces for restoring state to avoid
14938 * checking (bogus) intermediate states.
14940 for_each_pipe(dev_priv
, pipe
) {
14941 struct drm_crtc
*crtc
=
14942 dev_priv
->pipe_to_crtc_mapping
[pipe
];
14944 intel_crtc_restore_mode(crtc
);
14947 intel_modeset_update_staged_output_state(dev
);
14950 intel_modeset_check_state(dev
);
14953 void intel_modeset_gem_init(struct drm_device
*dev
)
14955 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14956 struct drm_crtc
*c
;
14957 struct drm_i915_gem_object
*obj
;
14960 mutex_lock(&dev
->struct_mutex
);
14961 intel_init_gt_powersave(dev
);
14962 mutex_unlock(&dev
->struct_mutex
);
14965 * There may be no VBT; and if the BIOS enabled SSC we can
14966 * just keep using it to avoid unnecessary flicker. Whereas if the
14967 * BIOS isn't using it, don't assume it will work even if the VBT
14968 * indicates as much.
14970 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
14971 dev_priv
->vbt
.lvds_use_ssc
= !!(I915_READ(PCH_DREF_CONTROL
) &
14974 intel_modeset_init_hw(dev
);
14976 intel_setup_overlay(dev
);
14979 * Make sure any fbs we allocated at startup are properly
14980 * pinned & fenced. When we do the allocation it's too early
14983 for_each_crtc(dev
, c
) {
14984 obj
= intel_fb_obj(c
->primary
->fb
);
14988 mutex_lock(&dev
->struct_mutex
);
14989 ret
= intel_pin_and_fence_fb_obj(c
->primary
,
14993 mutex_unlock(&dev
->struct_mutex
);
14995 DRM_ERROR("failed to pin boot fb on pipe %d\n",
14996 to_intel_crtc(c
)->pipe
);
14997 drm_framebuffer_unreference(c
->primary
->fb
);
14998 c
->primary
->fb
= NULL
;
14999 update_state_fb(c
->primary
);
15003 intel_backlight_register(dev
);
15006 void intel_connector_unregister(struct intel_connector
*intel_connector
)
15008 struct drm_connector
*connector
= &intel_connector
->base
;
15010 intel_panel_destroy_backlight(connector
);
15011 drm_connector_unregister(connector
);
15014 void intel_modeset_cleanup(struct drm_device
*dev
)
15016 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15017 struct drm_connector
*connector
;
15019 intel_disable_gt_powersave(dev
);
15021 intel_backlight_unregister(dev
);
15024 * Interrupts and polling as the first thing to avoid creating havoc.
15025 * Too much stuff here (turning of connectors, ...) would
15026 * experience fancy races otherwise.
15028 intel_irq_uninstall(dev_priv
);
15031 * Due to the hpd irq storm handling the hotplug work can re-arm the
15032 * poll handlers. Hence disable polling after hpd handling is shut down.
15034 drm_kms_helper_poll_fini(dev
);
15036 mutex_lock(&dev
->struct_mutex
);
15038 intel_unregister_dsm_handler();
15040 intel_fbc_disable(dev
);
15042 mutex_unlock(&dev
->struct_mutex
);
15044 /* flush any delayed tasks or pending work */
15045 flush_scheduled_work();
15047 /* destroy the backlight and sysfs files before encoders/connectors */
15048 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
15049 struct intel_connector
*intel_connector
;
15051 intel_connector
= to_intel_connector(connector
);
15052 intel_connector
->unregister(intel_connector
);
15055 drm_mode_config_cleanup(dev
);
15057 intel_cleanup_overlay(dev
);
15059 mutex_lock(&dev
->struct_mutex
);
15060 intel_cleanup_gt_powersave(dev
);
15061 mutex_unlock(&dev
->struct_mutex
);
15065 * Return which encoder is currently attached for connector.
15067 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
15069 return &intel_attached_encoder(connector
)->base
;
15072 void intel_connector_attach_encoder(struct intel_connector
*connector
,
15073 struct intel_encoder
*encoder
)
15075 connector
->encoder
= encoder
;
15076 drm_mode_connector_attach_encoder(&connector
->base
,
15081 * set vga decode state - true == enable VGA decode
15083 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
15085 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15086 unsigned reg
= INTEL_INFO(dev
)->gen
>= 6 ? SNB_GMCH_CTRL
: INTEL_GMCH_CTRL
;
15089 if (pci_read_config_word(dev_priv
->bridge_dev
, reg
, &gmch_ctrl
)) {
15090 DRM_ERROR("failed to read control word\n");
15094 if (!!(gmch_ctrl
& INTEL_GMCH_VGA_DISABLE
) == !state
)
15098 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
15100 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
15102 if (pci_write_config_word(dev_priv
->bridge_dev
, reg
, gmch_ctrl
)) {
15103 DRM_ERROR("failed to write control word\n");
15110 struct intel_display_error_state
{
15112 u32 power_well_driver
;
15114 int num_transcoders
;
15116 struct intel_cursor_error_state
{
15121 } cursor
[I915_MAX_PIPES
];
15123 struct intel_pipe_error_state
{
15124 bool power_domain_on
;
15127 } pipe
[I915_MAX_PIPES
];
15129 struct intel_plane_error_state
{
15137 } plane
[I915_MAX_PIPES
];
15139 struct intel_transcoder_error_state
{
15140 bool power_domain_on
;
15141 enum transcoder cpu_transcoder
;
15154 struct intel_display_error_state
*
15155 intel_display_capture_error_state(struct drm_device
*dev
)
15157 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15158 struct intel_display_error_state
*error
;
15159 int transcoders
[] = {
15167 if (INTEL_INFO(dev
)->num_pipes
== 0)
15170 error
= kzalloc(sizeof(*error
), GFP_ATOMIC
);
15174 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
15175 error
->power_well_driver
= I915_READ(HSW_PWR_WELL_DRIVER
);
15177 for_each_pipe(dev_priv
, i
) {
15178 error
->pipe
[i
].power_domain_on
=
15179 __intel_display_power_is_enabled(dev_priv
,
15180 POWER_DOMAIN_PIPE(i
));
15181 if (!error
->pipe
[i
].power_domain_on
)
15184 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
15185 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
15186 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
15188 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
15189 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
15190 if (INTEL_INFO(dev
)->gen
<= 3) {
15191 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
15192 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
15194 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
15195 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
15196 if (INTEL_INFO(dev
)->gen
>= 4) {
15197 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
15198 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
15201 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
15203 if (HAS_GMCH_DISPLAY(dev
))
15204 error
->pipe
[i
].stat
= I915_READ(PIPESTAT(i
));
15207 error
->num_transcoders
= INTEL_INFO(dev
)->num_pipes
;
15208 if (HAS_DDI(dev_priv
->dev
))
15209 error
->num_transcoders
++; /* Account for eDP. */
15211 for (i
= 0; i
< error
->num_transcoders
; i
++) {
15212 enum transcoder cpu_transcoder
= transcoders
[i
];
15214 error
->transcoder
[i
].power_domain_on
=
15215 __intel_display_power_is_enabled(dev_priv
,
15216 POWER_DOMAIN_TRANSCODER(cpu_transcoder
));
15217 if (!error
->transcoder
[i
].power_domain_on
)
15220 error
->transcoder
[i
].cpu_transcoder
= cpu_transcoder
;
15222 error
->transcoder
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
15223 error
->transcoder
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
15224 error
->transcoder
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
15225 error
->transcoder
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
15226 error
->transcoder
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
15227 error
->transcoder
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
15228 error
->transcoder
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
15234 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15237 intel_display_print_error_state(struct drm_i915_error_state_buf
*m
,
15238 struct drm_device
*dev
,
15239 struct intel_display_error_state
*error
)
15241 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15247 err_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev
)->num_pipes
);
15248 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
15249 err_printf(m
, "PWR_WELL_CTL2: %08x\n",
15250 error
->power_well_driver
);
15251 for_each_pipe(dev_priv
, i
) {
15252 err_printf(m
, "Pipe [%d]:\n", i
);
15253 err_printf(m
, " Power: %s\n",
15254 error
->pipe
[i
].power_domain_on
? "on" : "off");
15255 err_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
15256 err_printf(m
, " STAT: %08x\n", error
->pipe
[i
].stat
);
15258 err_printf(m
, "Plane [%d]:\n", i
);
15259 err_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
15260 err_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
15261 if (INTEL_INFO(dev
)->gen
<= 3) {
15262 err_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
15263 err_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
15265 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
15266 err_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
15267 if (INTEL_INFO(dev
)->gen
>= 4) {
15268 err_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
15269 err_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
15272 err_printf(m
, "Cursor [%d]:\n", i
);
15273 err_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
15274 err_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
15275 err_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);
15278 for (i
= 0; i
< error
->num_transcoders
; i
++) {
15279 err_printf(m
, "CPU transcoder: %c\n",
15280 transcoder_name(error
->transcoder
[i
].cpu_transcoder
));
15281 err_printf(m
, " Power: %s\n",
15282 error
->transcoder
[i
].power_domain_on
? "on" : "off");
15283 err_printf(m
, " CONF: %08x\n", error
->transcoder
[i
].conf
);
15284 err_printf(m
, " HTOTAL: %08x\n", error
->transcoder
[i
].htotal
);
15285 err_printf(m
, " HBLANK: %08x\n", error
->transcoder
[i
].hblank
);
15286 err_printf(m
, " HSYNC: %08x\n", error
->transcoder
[i
].hsync
);
15287 err_printf(m
, " VTOTAL: %08x\n", error
->transcoder
[i
].vtotal
);
15288 err_printf(m
, " VBLANK: %08x\n", error
->transcoder
[i
].vblank
);
15289 err_printf(m
, " VSYNC: %08x\n", error
->transcoder
[i
].vsync
);
15293 void intel_modeset_preclose(struct drm_device
*dev
, struct drm_file
*file
)
15295 struct intel_crtc
*crtc
;
15297 for_each_intel_crtc(dev
, crtc
) {
15298 struct intel_unpin_work
*work
;
15300 spin_lock_irq(&dev
->event_lock
);
15302 work
= crtc
->unpin_work
;
15304 if (work
&& work
->event
&&
15305 work
->event
->base
.file_priv
== file
) {
15306 kfree(work
->event
);
15307 work
->event
= NULL
;
15310 spin_unlock_irq(&dev
->event_lock
);